diff --git a/CMakeLists.txt b/CMakeLists.txt
index 18df549a..16b411ce 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -2,3 +2,4 @@
 # SPDX-License-Identifier: Apache-2.0
 
 add_subdirectory_ifdef(CONFIG_SOC_FAMILY_REALTEK_AMEBA ameba)
+add_subdirectory_ifdef(CONFIG_SOC_FAMILY_REALTEK_BEE bee)
diff --git a/Kconfig b/Kconfig
index f1e0dae3..038bb213 100644
--- a/Kconfig
+++ b/Kconfig
@@ -2,3 +2,4 @@
 # SPDX-License-Identifier: Apache-2.0
 
 rsource "ameba/Kconfig"
+rsource "bee/Kconfig"
diff --git a/README.rst b/README.rst
index 609f7b1c..7740d30d 100644
--- a/README.rst
+++ b/README.rst
@@ -1,8 +1,35 @@
-Important Information About This Repository
-*******************************************
 
-HAL Realtek (or `hal_realtek`) is a collection of tools, low-level APIs, and hardware access functions for Realtek Devices.
+Realtek HAL Module (hal_realtek)
+################################
 
-This repository is a copy (not a fork) of the [ameba-rtos repository](https://github.com/Ameba-AIoT/ameba-rtos) that contains Ameba SoCs.
+HAL Realtek (or ``hal_realtek``) is a collection of tools, low-level APIs, and hardware access functions for Realtek Devices, enabling support within the Zephyr RTOS ecosystem.
 
-After following the standard Zephyr guide for compilation, both app and bootloader images tailored for Ameba SoCs will be generated. [Refer to this tutorial](https://github.com/Ameba-AIoT/ameba-rtos/) for Flashing these images and running on Ameba SoCs.
+Currently, the ``hal_realtek`` repository supports two primary SoC series: **Ameba** and **Bee**.
+
+Supported SoC Series
+*******************
+
+Ameba Series (ameba)
+====================
+
+The ``ameba`` directory contains the HAL for Ameba series SoCs.
+
+This repository is a copy (not a fork) of the `ameba-rtos repository <https://github.com/Ameba-AIoT/ameba-rtos>`_ that contains Ameba SoCs.
+
+After following the standard Zephyr guide for compilation, both app and bootloader images tailored for Ameba SoCs will be generated. Refer to this `tutorial <https://github.com/Ameba-AIoT/ameba-rtos/>`_ for Flashing these images and running on Ameba SoCs.
+
+Bee Series (bee)
+================
+
+The ``bee`` directory hosts the HAL for Bee series SoCs. The sources in this directory are extracted from their respective SDKs:
+
+* **RTL87x2G**: `rtkconnectivity/rtl87x2g_sdk <https://github.com/rtkconnectivity/rtl87x2g_sdk>`_
+
+* **RTL8752H**: `rtkconnectivity/rtl8752h_sdk <https://github.com/rtkconnectivity/rtl8752h_sdk>`_
+
+Maintenance & Synchronization Strategy
+**************************************
+
+Since the HALs for the **Ameba** and **Bee** series are maintained by different teams within Realtek, and additional SoC series may be added to ``hal_realtek`` in the future, there is no single upstream Git history for this repository.
+
+Therefore, this module adheres to the **"Updating modules with a diff from upstream"** practice as defined in the `Zephyr Project Documentation <https://docs.zephyrproject.org/latest/develop/modules.html#allowed-practices>`_.
\ No newline at end of file
diff --git a/ameba/Kconfig b/ameba/Kconfig
index a192b6fd..6f611486 100644
--- a/ameba/Kconfig
+++ b/ameba/Kconfig
@@ -10,5 +10,6 @@ config REALTEK_AMEBA_HAL_LIB
 	  This option enables the Realtek Ameba HAL library.
 
 rsource "ameba*/Kconfig"
+rsource "common/wifi/Kconfig"
 
 endif # SOC_FAMILY_REALTEK_AMEBA
diff --git a/ameba/amebaG2/source/fwlib/include/ameba_phy.h b/ameba/amebaG2/source/fwlib/include/ameba_phy.h
deleted file mode 100644
index c4eb037e..00000000
--- a/ameba/amebaG2/source/fwlib/include/ameba_phy.h
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * Copyright (c) 2024 Realtek Semiconductor Corp.
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-enum  eth_phy_type {
-	RTL_8721F,
-	RTL_8721G,
-};
-
-enum  eth_mode {
-	ETH_MAC_MODE,
-	ETH_PHY_MODE,
-};
-
-enum  phy_clk_mode {
-	EXTERNAL_50M,
-	EXTERNAL_25M,
-	INTERNAL_XTAL,
-};
-
-enum  phy_MMD_type {
-	RTK_MMD_TYPE,
-
-};
-
-enum  phy_address {
-	PHYID_0,
-	PHYID_1,
-	PHYID_2,
-	PHYID_3,
-};
-
-#define RTK_EEEPC1R_DEVICE 0x3
-#define RTK_EEEPC1R_ADDRESS 0x0
-
-#define RTK_EEEPS1R_DEVICE 0x3
-#define RTK_EEEPS1R_ADDRESS 0x1
-
-#define RTK_EEECR_DEVICE 0x3
-#define RTK_EEECR_ADDRESS 0x14
-
-#define RTK_EEEWER_DEVICE 0x3
-#define RTK_EEEWER_ADDRESS 0x16
-
-#define RTK_EEEAR_DEVICE 0x7
-#define RTK_EEEAR_ADDRESS 0x3c
-#define RTK_EEEAR_ADVERTISE_EEE 0x2
-#define RTK_EEEAR_NOT_ADVERTISE_EEE 0x0
-
-#define RTK_EEELPAR_DEVICE 0x7
-#define RTK_EEELPAR_ADDRESS 0x3d
-
-
-#define RTK8201F_EEE_CAPAB_PAGE 0x4
-#define RTK8201F_EEE_CAPAB_REG 0x10
-#define RTK8201F_EEE_CAPAB_EN 0x7377
-
-#define RTK8201F_EEE_MODE_PAGE 0x7
-#define RTK8201F_EEE_MODE_REG 0x14
-#define RTK8201F_EEE_MAC_MODE_SET 0xD5
-#define RTK8201F_EEE_PHY_MODE_SET 0x10D5
-
-#define RTK8201F_RMSR_MODE_PAGE 0x7
-#define RTK8201F_RMSR_MODE_REG 0x10
-#define RTK8201F_RMSR_MAC_OUTPUT 0x1ffa
-#define RTK8201F_PMSR_MAC_INPUT 0xffa
-
-#define RTK_MACR_DATA BIT(14)
-
-void PHY_SW_RESET(void);
-void PHY_RESTART_AN(void);
-void PHY_SET_MMD_REG(u32 type, u32 device, u32 addr, u32 data);
-u32 PHY_GET_MMD_REG(u32 type, u32 device, u32 addr);
-void PHY_ENABLE_EEE(u32 type, u32 STATUS);
-void PHY_SET_EEE_MODE(u32 type, u32 mode);
-void PHY_SET_REFCLK_DIR(u32 type, u32 MACDIR);
\ No newline at end of file
diff --git a/ameba/amebaG2/source/fwlib/ram_km4tz/ameba_phy.c b/ameba/amebaG2/source/fwlib/ram_km4tz/ameba_phy.c
deleted file mode 100644
index 044dee40..00000000
--- a/ameba/amebaG2/source/fwlib/ram_km4tz/ameba_phy.c
+++ /dev/null
@@ -1,114 +0,0 @@
-/*
- * Copyright (c) 2024 Realtek Semiconductor Corp.
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include "ameba_soc.h"
-// static const char *const TAG = "PHY";
-
-
-void PHY_SW_RESET(void)
-{
-	Ethernet_Write_PhyReg(FEPHY_REG_PAGE_0, FEPHY_REG_ADDR_0, 0x8000);
-	DelayMs(150);
-}
-
-void PHY_RESTART_AN(void)
-{
-	Ethernet_Write_PhyReg(FEPHY_REG_PAGE_0, FEPHY_REG_ADDR_0, 0x1200);
-}
-
-
-void PHY_SET_MMD_REG(u32 type, u32 device, u32 addr, u32 data)
-{
-	switch (type) {
-	case RTK_MMD_TYPE:
-		Ethernet_Write_PhyReg(FEPHY_REG_PAGE_0, FEPHY_REG_ADDR_13, device);
-		Ethernet_Write_PhyReg(FEPHY_REG_PAGE_0, FEPHY_REG_ADDR_14, addr);
-		Ethernet_Write_PhyReg(FEPHY_REG_PAGE_0, FEPHY_REG_ADDR_13, (device | RTK_MACR_DATA));
-		Ethernet_Write_PhyReg(FEPHY_REG_PAGE_0, FEPHY_REG_ADDR_14, data);
-		break;
-
-	default:
-		break;
-	}
-}
-
-u32 PHY_GET_MMD_REG(u32 type, u32 device, u32 addr)
-{
-	u32 rvalue = 0;
-	switch (type) {
-	case RTK_MMD_TYPE:
-		Ethernet_Write_PhyReg(FEPHY_REG_PAGE_0, FEPHY_REG_ADDR_13, device);
-		Ethernet_Write_PhyReg(FEPHY_REG_PAGE_0, FEPHY_REG_ADDR_14, addr);
-		Ethernet_Write_PhyReg(FEPHY_REG_PAGE_0, FEPHY_REG_ADDR_13, (device | RTK_MACR_DATA));
-		rvalue = Ethernet_Read_PhyReg(FEPHY_REG_PAGE_0, FEPHY_REG_ADDR_14);
-		break;
-
-	default:
-		break;
-	}
-	return rvalue;
-}
-
-void PHY_ENABLE_EEE(u32 type, u32 STATUS)
-{
-	switch (type) {
-	case RTL_8721F:
-		if (STATUS) {
-			Ethernet_Write_PhyReg(RTK8201F_EEE_CAPAB_PAGE, RTK8201F_EEE_CAPAB_REG, RTK8201F_EEE_CAPAB_EN);
-			PHY_SET_MMD_REG(RTK_MMD_TYPE, RTK_EEEAR_DEVICE, RTK_EEEAR_ADDRESS, RTK_EEEAR_ADVERTISE_EEE);
-			PHY_RESTART_AN();
-		} else {
-
-
-		}
-		break;
-	case RTL_8721G:
-		if (STATUS) {
-
-		} else {
-
-		}
-		break;
-	default:
-		break;
-	}
-}
-
-void PHY_SET_EEE_MODE(u32 type, u32 mode)
-{
-	switch (type) {
-	case RTL_8721F:
-		if (mode == ETH_MAC_MODE) {
-			Ethernet_Write_PhyReg(RTK8201F_EEE_MODE_PAGE, RTK8201F_EEE_MODE_REG, RTK8201F_EEE_MAC_MODE_SET);
-		} else {
-
-
-		}
-		break;
-	case RTL_8721G:
-		break;
-	default:
-		break;
-	}
-}
-
-
-void PHY_SET_REFCLK_DIR(u32 type, u32 MACDIR)
-{
-	switch (type) {
-	case RTL_8721F:
-		if (MACDIR == ETH_REFCLK_ON) {
-			Ethernet_Write_PhyReg(RTK8201F_RMSR_MODE_PAGE, RTK8201F_RMSR_MODE_REG, RTK8201F_RMSR_MAC_OUTPUT);
-		} else {
-			Ethernet_Write_PhyReg(RTK8201F_RMSR_MODE_PAGE, RTK8201F_RMSR_MODE_REG, RTK8201F_PMSR_MAC_INPUT);
-		}
-		break;
-	case RTL_8721G:
-		break;
-	default:
-		break;
-	}
-}
\ No newline at end of file
diff --git a/ameba/amebad/CMakeLists.txt b/ameba/amebad/CMakeLists.txt
index c20f2462..25128f5e 100644
--- a/ameba/amebad/CMakeLists.txt
+++ b/ameba/amebad/CMakeLists.txt
@@ -1,5 +1,16 @@
 # Copyright (c) 2024 Realtek Semiconductor Corp.
 # SPDX-License-Identifier: Apache-2.0
+
+zephyr_link_libraries_ifdef(CONFIG_WIFI_AMEBA
+  -Wl,--start-group
+  ${LIB_PATH}/lib_wifi_rtk_app.a
+  ${LIB_PATH}/lib_wifi_single_core.a
+  -Wl,--end-group
+  ${LIB_PATH}/lib_wifi_api.a
+  ${LIB_PATH}/lib_rtw_event.a
+  ${LIB_PATH}/lib_wpa_lite.a
+  ${LIB_PATH}/lib_wifi_com_sec.a
+)
 zephyr_compile_options(-mcmse)
 
 zephyr_include_directories(
@@ -7,14 +18,18 @@ zephyr_include_directories(
   source/cmsis
   source/misc
   source/swlib
+  source/lib/include
   source/fwlib/include
+  source/usrcfg/include
   source/app/monitor/include
 )
 
 # used by common
 zephyr_library_sources(
   source/fwlib/ram_hp/ameba_system.c
+  source/fwlib/ram_common/ameba_pll.c
   source/swlib/log.c
+  source/fwlib/ram_common/ameba_reset.c
 )
 
 # used by driver, need use zephyr_library_sources_ifdef
@@ -37,31 +52,3 @@ zephyr_link_libraries(
   gcc
   -T${CMAKE_CURRENT_SOURCE_DIR}/ld/ameba_rom_symbol_acut.ld
 )
-
-# west sign
-if(CONFIG_SOC_AMEBA_NP_IMAGE)
-  file(GLOB blob_bin_file "${ZEPHYR_HAL_REALTEK_MODULE_DIR}/zephyr/blobs/${CONFIG_SOC_SERIES}/bin/*.bin")
-
-  if(blob_bin_file)
-    set(python_script_args
-      --soc ${CONFIG_SOC_SERIES}
-      --bin-file ${ZEPHYR_BINARY_DIR}/${KERNEL_BIN_NAME}
-      --out-dir ${CMAKE_BINARY_DIR}
-      --module-dir ${ZEPHYR_HAL_REALTEK_MODULE_DIR}
-    )
-
-    add_custom_target(zephyr.raw.map ALL
-      DEPENDS ${ZEPHYR_BINARY_DIR}/${KERNEL_NAME}.raw.map
-    )
-
-    add_custom_command(
-      OUTPUT ${ZEPHYR_BINARY_DIR}/${KERNEL_NAME}.raw.map
-      COMMAND ${CMAKE_NM} ${ZEPHYR_BINARY_DIR}/${KERNEL_ELF_NAME} | sort > ${ZEPHYR_BINARY_DIR}/${KERNEL_NAME}.raw.map
-      COMMAND ${CMAKE_OBJDUMP} -d ${ZEPHYR_BINARY_DIR}/${KERNEL_ELF_NAME} > ${ZEPHYR_BINARY_DIR}/${KERNEL_NAME}.asm
-      COMMAND ${PYTHON_EXECUTABLE} ${ZEPHYR_HAL_REALTEK_MODULE_DIR}/ameba/scripts/merge_bin.py ${python_script_args}
-      DEPENDS ${ZEPHYR_BINARY_DIR}/${KERNEL_ELF_NAME} ${blob_bin_file} ${CMAKE_CURRENT_SOURCE_DIR}/manifest.json5
-    )
-  else()
-    message(WARNING "Missing Realtek blobs. Run: `west blobs fetch hal_realtek`")
-  endif()
-endif()
diff --git a/ameba/amebad/Kconfig b/ameba/amebad/Kconfig
index d3687b53..fce66f25 100644
--- a/ameba/amebad/Kconfig
+++ b/ameba/amebad/Kconfig
@@ -4,3 +4,6 @@
 config ARM_CORE_CM4
 	bool
 	default y if SOC_SERIES_AMEBAD
+
+config SOC_SERIES_AMEBAD
+	select SINGLE_CORE_WIFI if WLAN
diff --git a/ameba/amebad/include/platform_autoconf.h b/ameba/amebad/include/platform_autoconf.h
index 120e64d2..4a67a5f5 100644
--- a/ameba/amebad/include/platform_autoconf.h
+++ b/ameba/amebad/include/platform_autoconf.h
@@ -9,6 +9,7 @@
 #define CONFIG_IMG2_FLASH 1
 #define CONFIG_SUPPORT_ATCMD 1
 #define CONFIG_ATCMD_LOGUART 1
+#define CONFIG_VFS_LITTLEFS_INCLUDED 1
 #define CONFIG_LINK_ROM_SYMB 1
 #define CONFIG_CPU_HAS_FPU 1
 #define CONFIG_ARM_CORE_CM4 1
@@ -18,3 +19,4 @@
 #define CONFIG_AMEBAD_B_CUT 1
 #define CONFIG_SOC_PS_EN 1
 #define CONFIG_SOC_PS_MODULE 1
+#include <zephyr/autoconf.h>
diff --git a/ameba/amebad/source/fwlib/include/ameba.h b/ameba/amebad/source/fwlib/include/ameba.h
index 3c2e5527..7f75ed09 100644
--- a/ameba/amebad/source/fwlib/include/ameba.h
+++ b/ameba/amebad/source/fwlib/include/ameba.h
@@ -51,7 +51,7 @@
 #else
 #include "ameba_rcc_lp.h"
 #endif
-// #include "sscanf_minimal.h"
+#include "sscanf_minimal.h"
 
 #include "ameba_trustzone.h"
 #include "ameba_arch.h"
diff --git a/ameba/amebad/source/fwlib/include/ameba_efuse.h b/ameba/amebad/source/fwlib/include/ameba_efuse.h
index 51ccdff2..63cba7a1 100644
--- a/ameba/amebad/source/fwlib/include/ameba_efuse.h
+++ b/ameba/amebad/source/fwlib/include/ameba_efuse.h
@@ -159,7 +159,7 @@ int OTP_LogicalMap_Write(u32 addr, u32 cnts, u8 *data);
 int OTPSetCRC(void);
 int OTP_Read8(u32 Addr, u8 *Data);
 int OTP_Write8(u32 Addr, u8 Data);
-
+void EFUSE_GetUUID(u32 *UUID);
 /**
   * @}
   */
diff --git a/ameba/amebad/source/fwlib/include/ameba_gdma.h b/ameba/amebad/source/fwlib/include/ameba_gdma.h
index 063360e0..d87a4fa6 100644
--- a/ameba/amebad/source/fwlib/include/ameba_gdma.h
+++ b/ameba/amebad/source/fwlib/include/ameba_gdma.h
@@ -459,7 +459,7 @@ _LONG_CALL_ void GDMA_SetChnlPriority(u8 GDMA_Index, u8 GDMA_ChNum, u32 ChnlPrio
 _LONG_CALL_ void GDMA_Suspend(u8 GDMA_Index, u8 GDMA_ChNum);
 _LONG_CALL_ void GDMA_Resume(u8 GDMA_Index, u8 GDMA_ChNum);
 _LONG_CALL_ u8 GDMA_Abort(u8 GDMA_Index, u8 GDMA_ChNum);
-
+_LONG_CALL_ u8 GDMA_ChannelIsActive(u8 GDMA_Index, u8 GDMA_ChNum);
 
 /**
   * @}
diff --git a/ameba/amebad/source/fwlib/include/ameba_reset.h b/ameba/amebad/source/fwlib/include/ameba_reset.h
index b60db37e..60214b6c 100644
--- a/ameba/amebad/source/fwlib/include/ameba_reset.h
+++ b/ameba/amebad/source/fwlib/include/ameba_reset.h
@@ -12,6 +12,12 @@
 
 /* AUTO_GEN_END */
 
+#define	AON_BIT_RSTF_DSLP		BIT_BOOT_DSLP_RESET_HAPPEN
+#define	AON_BIT_RSTF_BOR		BIT_BOOT_BOD_RESET_HAPPEN
+
+#define IS_WDG_RESET(reason)	((reason) & (BIT_BOOT_WDG_RESET_HAPPEN | BIT_BOOT_KM4WDG_RESET_HAPPEN))
+#define IS_SYS_RESET(reason)	((reason) & (BIT_BOOT_SYS_RESET_HAPPEN | BIT_BOOT_KM4SYS_RESET_HAPPEN))
+
 extern void System_Reset(void);
 
 #endif
diff --git a/ameba/amebad/source/fwlib/include/ameba_ssi.h b/ameba/amebad/source/fwlib/include/ameba_ssi.h
index 8a421958..1dcec3e1 100644
--- a/ameba/amebad/source/fwlib/include/ameba_ssi.h
+++ b/ameba/amebad/source/fwlib/include/ameba_ssi.h
@@ -660,6 +660,11 @@ extern const SPI_DevTable SPI_DEV_TABLE[2];
 #define SPI_BIT_RXFIS		BIT_ISR_RXFIS
 #define SPI_BIT_TXEIS		BIT_ISR_TXEIS
 
+/* SPI_SR */
+#define SPI_BIT_DCOL		BIT_SR_DCOL
+#define SPI_BIT_TFE			BIT_SR_TFE
+#define SPI_BIT_BUSY		BIT_SR_BUSY
+
 /* SPI_IMR */
 #define SPI_BIT_RXFIM		BIT_IMR_RXFIM
 #define SPI_BIT_RXOIM		BIT_IMR_RXOIM
diff --git a/ameba/amebad/source/fwlib/include/ameba_trustzone.h b/ameba/amebad/source/fwlib/include/ameba_trustzone.h
index 2c6ca635..b58bdf8f 100644
--- a/ameba/amebad/source/fwlib/include/ameba_trustzone.h
+++ b/ameba/amebad/source/fwlib/include/ameba_trustzone.h
@@ -28,8 +28,8 @@ typedef struct {
   */
 #define SAU_INIT_CTRL_ALLNS  0
 
-#define SAU_ENTRYS_NUM			8
-#define IDAU_ENTRYS_NUM		8
+#define SAU_ENTRY_NUM			8
+#define IDAU_ENTRY_NUM		8
 
 void BOOT_RAM_TZCfg(void);
 
diff --git a/ameba/amebad/source/fwlib/ram_common/ameba_efuse.c b/ameba/amebad/source/fwlib/ram_common/ameba_efuse.c
index cd6132b2..0f65c683 100644
--- a/ameba/amebad/source/fwlib/ram_common/ameba_efuse.c
+++ b/ameba/amebad/source/fwlib/ram_common/ameba_efuse.c
@@ -6,4 +6,18 @@
 
 #include "ameba_soc.h"
 
+#define OTP_UUID							0x1F4
+
+void EFUSE_GetUUID(u32 *UUID)
+{
+	u8 index, ID[4];
+
+	for (index = 0; index < 4; index++) {
+		OTP_Read8(OTP_UUID + index, &ID[index]);
+	}
+
+	UUID[0] = (ID[3] << 24) | (ID[2] << 16) | (ID[1] << 8) | ID[0];
+	UUID[1] = 0;
+}
+
 /******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/
diff --git a/ameba/amebad/source/fwlib/ram_common/ameba_gdma_ram.c b/ameba/amebad/source/fwlib/ram_common/ameba_gdma_ram.c
index ce8ed193..938069f2 100644
--- a/ameba/amebad/source/fwlib/ram_common/ameba_gdma_ram.c
+++ b/ameba/amebad/source/fwlib/ram_common/ameba_gdma_ram.c
@@ -267,3 +267,27 @@ u8 GDMA_Abort(u8 GDMA_Index, u8 GDMA_ChNum)
 	return TRUE;
 }
 
+/**
+ * @brief Check if the channel is active
+ *
+ * @param GDMA_Index 0
+ * @param GDMA_ChNum 0 ~ 7
+ * @retval TRUE/FALSE
+ */
+__weak
+u8 GDMA_ChannelIsActive(u8 GDMA_Index, u8 GDMA_ChNum)
+{
+	GDMA_TypeDef *GDMA = ((GDMA_TypeDef *) GDMA_BASE);
+	if (TrustZone_IsSecure()) {
+		GDMA = ((GDMA_TypeDef *) GDMA0S_REG_BASE);
+	}
+	/* Check the parameters */
+	assert_param(IS_GDMA_Index(GDMA_Index));
+	assert_param(IS_GDMA_ChannelNum(GDMA_ChNum));
+
+	if ((GDMA->ChEnReg & BIT(GDMA_ChNum)) && \
+		((GDMA->CH[GDMA_ChNum].CFG_LOW & BIT_CFGx_L_INACTIVE) == 0)) {
+		return TRUE;
+	}
+	return FALSE;
+}
diff --git a/ameba/amebad/source/fwlib/ram_common/ameba_gpio.c b/ameba/amebad/source/fwlib/ram_common/ameba_gpio.c
index 99b7057f..1c3c8abd 100644
--- a/ameba/amebad/source/fwlib/ram_common/ameba_gpio.c
+++ b/ameba/amebad/source/fwlib/ram_common/ameba_gpio.c
@@ -6,6 +6,30 @@
 
 #include "ameba_soc.h"
 
+/**
+  * @brief  Reads the specified GPIO pins.
+  * @param  GPIO_Port: Specifies port number
+  *          This parameter can be one of the following values:
+  *		 		@arg GPIO_PORT_A: port number is A
+  *		 		@arg GPIO_PORT_B: port number is B
+  * @param  GPIO_Mask: One bit one GPIO pin, PortA/B:0x00000000 ~0xFFFFFFFF.
+  * @note   It can config multiple pins of one port by parameter GPIO_Mask
+  * @retval The value of the specified port pins
+  */
+u32 GPIO_PortRead(u32 GPIO_Port, u32 GPIO_Mask)
+{
+	GPIO_TypeDef *GPIO = NULL;
+	u32 RegValue;
+
+	GPIO = PORT_AB[GPIO_Port];
+
+	RegValue = GPIO->EXT_PORT[0];
+
+	RegValue &= GPIO_Mask;
+
+	return RegValue;
+}
+
 static GPIO_TypeDef *GPIO_PortAddrGet(u32 GPIO_Port)
 {
 	GPIO_TypeDef *GPIO = NULL;
diff --git a/ameba/amebad/source/fwlib/ram_common/ameba_pll.c b/ameba/amebad/source/fwlib/ram_common/ameba_pll.c
index 32111365..4a22aea8 100644
--- a/ameba/amebad/source/fwlib/ram_common/ameba_pll.c
+++ b/ameba/amebad/source/fwlib/ram_common/ameba_pll.c
@@ -319,4 +319,42 @@ void PLL3_Set(u32 BitMask, u32 NewState)
 
 	RTK_LOGW(TAG, "%s Please check this function \n", __func__);
 }
+
+/**
+  * @brief  Check whether the APB peripheral's clock has been enabled or not
+  * @param  APBPeriph_Clock_in: specifies the APB peripheral to check.
+  *      This parameter can be one of @ref APBPeriph_UART0_CLOCK, APBPeriph_ATIM_CLOCK and etc.
+  * @retval TRUE: The APB peripheral's clock has been enabled
+  * 		FALSE: The APB peripheral's clock has not been enabled
+  */
+u8 RCC_PeriphClockEnableChk(u32 APBPeriph_Clock_in)
+{
+	u8 ret;
+	u32 TempVal, CkeRegOffset = 0;
+	u32 ClkRegIndx = (APBPeriph_Clock_in >> 30) & 0x03;
+	u32 APBPeriph_Clock = APBPeriph_Clock_in & (~(BIT(31) | BIT(30)));
+	assert_param((ClkRegIndx == 0x1) || (ClkRegIndx == 0x2) || (ClkRegIndx == 0x3));
+
+	switch (ClkRegIndx) {
+	case SYS_CLK_CTRL1:
+		CkeRegOffset = REG_HS_PERI_CLK_CTRL1;
+		break;
+	case SYS_CLK_CTRL2:
+		CkeRegOffset = REG_HS_PERI_CLK_CTRL2;
+		break;
+	case SYS_CLK_CTRL3:
+		CkeRegOffset = REG_HS_PERI_CLK_CTRL3;
+		break;
+	}
+
+	TempVal = HAL_READ32(SYSTEM_CTRL_BASE, CkeRegOffset);
+	if (TempVal & APBPeriph_Clock) {
+		ret = TRUE;
+	} else {
+		ret = FALSE;
+	}
+
+	return ret;
+}
+
 /******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/
diff --git a/ameba/amebad/source/swlib/sscanf_minimal.c b/ameba/amebad/source/swlib/sscanf_minimal.c
new file mode 100644
index 00000000..02cb7cd6
--- /dev/null
+++ b/ameba/amebad/source/swlib/sscanf_minimal.c
@@ -0,0 +1,467 @@
+/*
+ * Copyright (c) 2024 Realtek Semiconductor Corp.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "ameba_soc.h"
+#include <string.h>
+#include <stdlib.h>
+
+#define USHRT_MAX_INTERNAL       ((u16)(~0U))
+#define BUF_MAX        			((s16)(USHRT_MAX_INTERNAL>>1))
+#define STR_STORE_MAX_LEN		24
+#define KSTRTOX_OVERFLOW        (1U << 31)
+
+#define in_range(c, lo, up)  ((u8)c >= lo && (u8)c <= up)
+#define isprint(c)           in_range(c, 0x20, 0x7f)
+#define isdigit(c)           in_range(c, '0', '9')
+#define isxdigit(c)          (isdigit(c) || in_range(c, 'a', 'f') || in_range(c, 'A', 'F'))
+#define isspace(c)           (c == ' ' || c == '\f' || c == '\n' || c == '\r' || c == '\t' || c == '\v' || c == ',')
+
+
+/**
+ * div_u64_rem - unsigned 64bit divide with 32bit divisor with remainder
+ *
+ * This is commonly provided by 32bit archs to provide an optimized 64bit
+ * divide.
+ */
+static u64 div_u64_rem(u64 dividend, u32 divisor, u32 *remainder)
+{
+	*remainder = (u32)dividend % divisor;
+	return (u32)dividend / divisor;
+}
+
+/**
+ * div_s64_rem - signed 64bit divide with 32bit divisor with remainder
+ */
+static s64 div_s64_rem(s64 dividend, s32 divisor, s32 *remainder)
+{
+	*remainder = (s32)dividend % divisor;
+	return (s32)dividend / divisor;
+}
+
+/**
+ * div_u64 - unsigned 64bit divide with 32bit divisor
+ *
+ * This is the most common 64bit divide and should be used if possible,
+ * as many 32bit archs can optimize this variant better than a full 64bit
+ * divide.
+ */
+
+static u64 div_u64(u64 dividend, u32 divisor)
+{
+	u32 remainder;
+	return div_u64_rem(dividend, divisor, &remainder);
+}
+
+/**
+ * div_s64 - signed 64bit divide with 32bit divisor
+ */
+
+static s64 div_s64(s64 dividend, s32 divisor)
+{
+	s32 remainder;
+	return div_s64_rem(dividend, divisor, &remainder);
+}
+
+
+static const char *_parse_integer_fixup_radix(const char *s, unsigned int *base)
+{
+	if (*base == 0) {
+		if (s[0] == '0') {
+			if (_tolower(s[1]) == 'x' && isxdigit(s[2])) {
+				*base = 16;
+			} else {
+				*base = 8;
+			}
+		} else {
+			*base = 10;
+		}
+	}
+	if (*base == 16 && s[0] == '0' && _tolower(s[1]) == 'x') {
+		s += 2;
+	}
+	return s;
+}
+
+static char *skip_spaces(const char *str)
+{
+	while (isspace(*str)) {
+		++str;
+	}
+
+	return (char *)str;
+}
+static int skip_atoi(const char **s)
+{
+	int i = 0;
+
+	while (isdigit(**s)) {
+		i = i * 10 + *((*s)++) - '0';
+	}
+
+	return i;
+}
+
+static int judge_digit_width(const char *str, unsigned int base)
+{
+
+	int width = 0;
+
+	if ((base == 16 || base == 0) && str[0] == '0' && _tolower(str[1]) == 'x') {
+		str += 2;
+		width += 2;
+
+		while (isxdigit(*str)) {
+			width++;
+			str++;
+		}
+	} else if (base == 16) {
+		while (isxdigit(*str)) {
+			width++;
+			str++;
+		}
+	} else if (base == 8 || (base == 0 && str[0] == '0')) {
+		while (isdigit(*str) && (*str) < '8') {
+			width++;
+			str++;
+		}
+	} else {
+		while (isdigit(*str)) {
+			width++;
+			str++;
+		}
+	}
+
+	return width;
+}
+
+//_OPTIMIZE_NONE_
+int _vsscanf_minimal(const char *buf, const char *fmt, va_list args)
+{
+	const char *str = buf;
+	char *next;
+	char digit;
+	int num = 0;
+	int i = 0;
+	u8 qualifier;
+	unsigned int base;
+	union {
+		long long s;
+		unsigned long long u;
+	} val;
+	s16 field_width;
+	bool is_sign;
+
+	char str_store[STR_STORE_MAX_LEN] = {0};
+
+	while (*fmt) {
+		/* skip any white space in format */
+		/* white space in format matchs any amount of
+		    * white space, including none, in the input.
+		    */
+		if (isspace(*fmt)) {
+			fmt = skip_spaces(++fmt);
+			str = skip_spaces(str);
+		}
+
+		/* anything that is not a conversion must match exactly */
+		if (*fmt != '%' && *fmt) {
+			if (*fmt++ != *str++) {
+				break;
+			}
+
+			continue;
+		}
+
+		if (!*fmt) {
+			break;
+		}
+
+		++fmt;
+
+		/* skip this conversion.
+		    * advance both strings to next white space
+		    */
+		if (*fmt == '*') {
+			if (!*str) {
+				break;
+			}
+
+			while (!isspace(*fmt) && *fmt != '%' && *fmt) {
+				fmt++;
+			}
+			while (!isspace(*str) && *str) {
+				str++;
+			}
+
+			continue;
+		}
+
+		/* get field width */
+		field_width = -1;
+
+		if (isdigit(*fmt)) {
+
+			field_width = skip_atoi(&fmt);
+
+			if (field_width <= 0) {
+				break;
+			}
+		}
+
+		/* get conversion qualifier */
+		qualifier = -1;
+
+		if (*fmt == 'h' || _tolower(*fmt) == 'l' || _tolower(*fmt) == 'z') {
+			qualifier = *fmt++;
+
+			if (qualifier == *fmt) {
+				if (qualifier == 'h') {
+					qualifier = 'H';
+					fmt++;
+				} else if (qualifier == 'l') {
+					qualifier = 'L';
+					fmt++;
+				}
+			}
+		}
+
+		if (!*fmt) {
+			break;
+		}
+
+		if (*fmt == 'n') {
+			/* return number of characters read so far */
+			*va_arg(args, int *) = str - buf;
+			++fmt;
+			continue;
+		}
+
+		if (!*str) {
+			break;
+		}
+
+		base = 10;
+		is_sign = 0;
+
+		switch (*fmt++) {
+		case 'c': {
+			char *s = (char *)va_arg(args, char *);
+
+			if (field_width == -1) {
+				field_width = 1;
+			}
+
+			do {
+				*s++ = *str++;
+			} while (--field_width > 0 && *str);
+
+			num++;
+		}
+
+		continue;
+
+		case 's': {
+			char *s = (char *)va_arg(args, char *);
+			if (field_width == -1) {
+				field_width = SHRT_MAX;
+			}
+			/* first, skip leading white space in buffer */
+			str = skip_spaces(str);
+
+			/* now copy until next white space */
+			while (*str && !isspace(*str) && field_width--) {
+				*s++ = *str++;
+			}
+
+			*s = '\0';
+			num++;
+		}
+		continue;
+
+		case 'o':
+			base = 8;
+			break;
+
+		case 'x':
+		case 'X':
+			base = 16;
+			break;
+
+		case 'i':
+			base = 0;
+			is_sign = 1;
+			break;
+
+		case 'd':
+			is_sign = 1;
+			break;
+
+		case 'u':
+			break;
+
+		case '%':
+			/* looking for '%' in str */
+			if (*str++ != '%') {
+				return num;
+			}
+			continue;
+
+		default:
+			/* invalid format; stop here */
+			return num;
+		}
+
+		/* have some sort of integer conversion.
+		    * first, skip white space in buffer.
+		*/
+		str = skip_spaces(str);
+
+		digit = *str;
+
+		if (is_sign && digit == '-') {
+			if (field_width == -1) {
+				field_width = judge_digit_width(str + 1, base);
+				field_width++;
+			} else {
+				field_width = (judge_digit_width(str + 1, base) + 1) < field_width ?
+							  (judge_digit_width(str + 1, base) + 1) :
+							  field_width;
+			}
+			digit = *(str + 1);
+		} else if (field_width == -1) {
+			field_width = judge_digit_width(str, base);
+		} else {
+			field_width = judge_digit_width(str, base) < field_width ?
+						  judge_digit_width(str, base) :
+						  field_width;
+		}
+
+		if (!digit
+			|| (base == 16 && !isxdigit(digit))
+			|| (base == 10 && !isdigit(digit))
+			|| (base == 8 && (!isdigit(digit) || digit > '7'))
+			|| (base == 0 && !isdigit(digit))) {
+			break;
+		}
+
+		//assert_param (field_width <= STR_STORE_MAX_LEN);
+		for (i = 0; i < field_width ; i++) {
+			str_store[i] = str[i];
+		}
+
+		if (is_sign) {
+			val.s = qualifier != 'L' ?
+					strtol(str_store, &next, base) :
+					strtoll(str_store, &next, base);
+		} else {
+			val.u = qualifier != 'L' ?
+					_strtoul(str_store, &next, base) :
+					strtoull(str_store, &next, base);
+		}
+
+		/* standard strtoul need this */
+		next = (char *)str + field_width;
+
+		for (i = 0; i < STR_STORE_MAX_LEN ; i++) {
+			str_store[i] = 0;
+		}
+
+
+		//判断转换的字符串的宽度是否大于 %2d
+		if (field_width > 0 && next - str > field_width) {
+			if (base == 0) {
+				_parse_integer_fixup_radix(str, &base);
+			}
+
+			while (next - str > field_width) {
+				if (is_sign) {
+					val.s = div_s64(val.s, base);
+				} else {
+					val.u = div_u64(val.u, base);
+				}
+
+				--next;
+			}
+		}
+
+		switch (qualifier) {
+		case 'H':       /* that's 'hh' in format */
+			if (is_sign) {
+				*va_arg(args, signed char *) = val.s;
+			} else {
+				*va_arg(args, unsigned char *) = val.u;
+			}
+			break;
+
+		case 'h':
+			if (is_sign) {
+				memcpy(va_arg(args, short *), &(val.s), sizeof(short));
+			} else {
+				memcpy(va_arg(args, unsigned short *), &(val.u), sizeof(unsigned short));
+			}
+			break;
+
+		case 'l':
+			if (is_sign) {
+				memcpy(va_arg(args, long *), &(val.s), sizeof(long));
+			} else {
+				memcpy(va_arg(args, unsigned long *), &(val.u), sizeof(unsigned long));
+			}
+			break;
+
+		case 'L':
+			if (is_sign) {
+				memcpy(va_arg(args, long long *), &(val.s), sizeof(long long));
+			} else {
+				memcpy(va_arg(args, unsigned long long *), &(val.u), sizeof(unsigned long long));
+			}
+			break;
+
+		case 'Z':
+		case 'z':
+			memcpy(va_arg(args, size_t *), &(val.u), sizeof(size_t));
+			break;
+
+		default:
+			if (is_sign) {
+				memcpy(va_arg(args, int *), &(val.s), sizeof(int));
+			} else {
+				memcpy(va_arg(args, unsigned int *), &(val.u), sizeof(unsigned int));
+			}
+			break;
+		}
+
+		num++;
+
+		if (!next) {
+			break;
+		}
+
+		str = next;
+	}
+
+	return num;
+}
+
+/**
+* sscanf - Unformat a buffer into a list of arguments
+* @buf:        input buffer
+* @fmt:        formatting of buffer
+* @...:        resulting arguments
+*/
+/* support %* %x %c %s %o %x %i %d %u %h %z and %l(within len 24) */
+/* for internal use, not support [] and ^ */
+int _sscanf_ss(const char *buf, const char *fmt, ...)
+{
+	va_list args;
+	int i;
+
+	va_start(args, fmt);
+	i = _vsscanf_minimal(buf, fmt, args);
+	va_end(args);
+
+	return i;
+}
diff --git a/ameba/amebaG2/source/fwlib/include/rom/sscanf_minimal.h b/ameba/amebad/source/swlib/sscanf_minimal.h
similarity index 100%
rename from ameba/amebaG2/source/fwlib/include/rom/sscanf_minimal.h
rename to ameba/amebad/source/swlib/sscanf_minimal.h
diff --git a/ameba/amebadplus/CMakeLists.txt b/ameba/amebadplus/CMakeLists.txt
index d6f51ef9..9faba7e5 100644
--- a/ameba/amebadplus/CMakeLists.txt
+++ b/ameba/amebadplus/CMakeLists.txt
@@ -3,23 +3,42 @@
 
 zephyr_compile_options(-mcmse)
 
+set(LIB_PATH ${ZEPHYR_CURRENT_MODULE_DIR}/zephyr/blobs/ameba/${CONFIG_SOC_SERIES}/lib)
+
+zephyr_link_libraries_ifdef(CONFIG_WIFI_AMEBA
+  ${LIB_PATH}/lib_wifi_whc_ap.a
+  ${LIB_PATH}/lib_wifi_api.a
+  ${LIB_PATH}/lib_rtw_event.a
+  ${LIB_PATH}/lib_wpa_lite.a
+  ${LIB_PATH}/lib_wifi_com_sec.a
+  ${LIB_PATH}/lib_coex_api.a
+  ${LIB_PATH}/lib_wifi_rtk_app.a
+)
 zephyr_include_directories(
   include
+  source/cmsis
+  source/misc
   source/swlib
   source/fwlib/include
+  source/usrcfg/include
+  source/app/monitor/include
 )
 
 # used by common
 zephyr_library_sources(
-  source/fwlib/ram_common/ameba_loguart.c
+  source/fwlib/ram_common/ameba_rtc_io.c
   source/fwlib/ram_common/ameba_reset.c
   source/fwlib/ram_common/ameba_clk.c
   source/swlib/log.c
+  source/fwlib/ram_common/ameba_adc.c
+  source/fwlib/ram_common/ameba_loguart.c
+  source/fwlib/ram_common/ameba_arch.c
+  source/fwlib/ram_common/ameba_ipc_api.c
+  source/fwlib/ram_common/ameba_ipc_ram.c
 )
 
 # used by driver, need use zephyr_library_sources_ifdef
 zephyr_library_sources_ifdef(CONFIG_GPIO_AMEBA source/fwlib/ram_common/ameba_gpio.c)
-zephyr_library_sources_ifdef(CONFIG_ADC_AMEBA source/fwlib/ram_common/ameba_adc.c)
 zephyr_library_sources_ifdef(CONFIG_INPUT_CTC_AMEBA source/fwlib/ram_common/ameba_captouch.c)
 zephyr_library_sources_ifdef(CONFIG_I2S_AMEBA source/fwlib/ram_common/ameba_audio_clock.c)
 zephyr_library_sources_ifdef(CONFIG_I2S_AMEBA source/fwlib/ram_common/ameba_pll.c)
@@ -39,49 +58,3 @@ zephyr_link_libraries(
     -T${CMAKE_CURRENT_SOURCE_DIR}/ld/ameba_rom_symbol_acut_s.ld
     -T${CMAKE_CURRENT_SOURCE_DIR}/ld/ameba_rom_symbol_stdlib.ld
   )
-
-zephyr_link_libraries(
-    "-Wl,-wrap,memchr"
-    "-Wl,-wrap,memcmp"
-    "-Wl,-wrap,memcpy"
-    "-Wl,-wrap,memmove"
-    "-Wl,-wrap,memset"
-    "-Wl,-wrap,strcmp"
-    "-Wl,-wrap,strlen"
-    "-Wl,-wrap,strtoul"
-    "-Wl,-wrap,strupr"
-    "-Wl,-wrap,stricmp"
-    "-Wl,-wrap,rand"
-    "-Wl,-wrap,strchr"
-    "-Wl,-wrap,strncmp"
-    "-Wl,-wrap,strstr"
-    "-Wl,-wrap,strncpy"
-)
-
-# west sign
-if(CONFIG_SOC_AMEBA_NP_IMAGE)
-  file(GLOB blob_bin_file "${ZEPHYR_HAL_REALTEK_MODULE_DIR}/zephyr/blobs/${CONFIG_SOC_SERIES}/bin/*.bin")
-
-  if(blob_bin_file)
-    set(python_script_args
-      --soc ${CONFIG_SOC_SERIES}
-      --bin-file ${ZEPHYR_BINARY_DIR}/${KERNEL_BIN_NAME}
-      --out-dir ${CMAKE_BINARY_DIR}
-      --module-dir ${ZEPHYR_HAL_REALTEK_MODULE_DIR}
-    )
-
-    add_custom_target(zephyr.raw.map ALL
-      DEPENDS ${ZEPHYR_BINARY_DIR}/${KERNEL_NAME}.raw.map
-    )
-
-    add_custom_command(
-      OUTPUT ${ZEPHYR_BINARY_DIR}/${KERNEL_NAME}.raw.map
-      COMMAND ${CMAKE_NM} ${ZEPHYR_BINARY_DIR}/${KERNEL_ELF_NAME} | sort > ${ZEPHYR_BINARY_DIR}/${KERNEL_NAME}.raw.map
-      COMMAND ${CMAKE_OBJDUMP} -d ${ZEPHYR_BINARY_DIR}/${KERNEL_ELF_NAME} > ${ZEPHYR_BINARY_DIR}/${KERNEL_NAME}.asm
-      COMMAND ${PYTHON_EXECUTABLE} ${ZEPHYR_HAL_REALTEK_MODULE_DIR}/ameba/scripts/merge_bin.py ${python_script_args}
-      DEPENDS ${ZEPHYR_BINARY_DIR}/${KERNEL_ELF_NAME} ${blob_bin_file} ${CMAKE_CURRENT_SOURCE_DIR}/manifest.json5
-    )
-  else()
-    message(WARNING "Missing Realtek blobs. Run: `west blobs fetch hal_realtek`")
-  endif()
-endif()
diff --git a/ameba/amebadplus/Kconfig b/ameba/amebadplus/Kconfig
index b5dc19d0..978ec72f 100644
--- a/ameba/amebadplus/Kconfig
+++ b/ameba/amebadplus/Kconfig
@@ -4,3 +4,6 @@
 config ARM_CORE_CM4
 	bool
 	default y if SOC_SERIES_AMEBADPLUS
+
+config SOC_SERIES_AMEBADPLUS
+	select AS_INIC_AP if WLAN
diff --git a/ameba/amebadplus/include/platform_autoconf.h b/ameba/amebadplus/include/platform_autoconf.h
index f09ba2a7..45a5f175 100644
--- a/ameba/amebadplus/include/platform_autoconf.h
+++ b/ameba/amebadplus/include/platform_autoconf.h
@@ -3,12 +3,26 @@
  *
  * SPDX-License-Identifier: Apache-2.0
  */
+
 #define CONFIG_AMEBADPLUS 1
 #define CONFIG_IMG1_FLASH 1
 #define CONFIG_IMG2_FLASH 1
+#define CONFIG_SUPPORT_ATCMD 1
+#define CONFIG_ATCMD_MANUAL_TEST 1
+#define CONFIG_ATCMD_NETWORK 1
+#define CONFIG_BACK_TRACE_DEPTH_LIMIT 8
+#define CONFIG_WHC_INTF_IPC_MENU 1
 #define CONFIG_CORE_AS_AP 1
-
+#define CONFIG_WLAN_MENU 1
+#define CONFIG_NORMAL_SDK 1
+#define CONFIG_WLAN 1
+#define CONFIG_WHC_INTF_IPC 1
+#define CONFIG_WHC_HOST 1
+//#define CONFIG_LWIP_LAYER 1  // not set in zephyr
+#define CONFIG_LWIP_NETCONN_SEM_PER_THREAD_MENU 1
+#define CONFIG_LWIP_NETCONN_SEM_PER_THREAD 1
 #define CONFIG_LINK_ROM_SYMB 1
 #define CONFIG_CPU_HAS_FPU 1
 #define CONFIG_ARM_CORE_CM4 1
 #define CONFIG_AMEBADPLUS_B_CUT 1
+#include <zephyr/autoconf.h>
diff --git a/ameba/amebadplus/source/fwlib/include/ameba.h b/ameba/amebadplus/source/fwlib/include/ameba.h
index f373f077..69978cb9 100644
--- a/ameba/amebadplus/source/fwlib/include/ameba.h
+++ b/ameba/amebadplus/source/fwlib/include/ameba.h
@@ -78,9 +78,9 @@
 #include "ameba_aontimer.h"
 #include "ameba_rcc.h"
 #include "ameba_rom_patch.h"
-// #include "ameba_usrcfg.h"
+#include "ameba_usrcfg.h"
 #include "log.h"
-// #include "sscanf_minimal.h"
+#include "sscanf_minimal.h"
 
 #define IMAGE_HEADER_LEN		0x20
 typedef struct {
diff --git a/ameba/amebadplus/source/fwlib/include/ameba_clk.h b/ameba/amebadplus/source/fwlib/include/ameba_clk.h
index 9db53829..8aab6132 100644
--- a/ameba/amebadplus/source/fwlib/include/ameba_clk.h
+++ b/ameba/amebadplus/source/fwlib/include/ameba_clk.h
@@ -176,6 +176,16 @@
 #define PERI_CLK_LIMIT			(100 * MHZ_TICK_CNT)
 #define SRAM_CLK_LIMIT			(200 * MHZ_TICK_CNT)
 
+/** @defgroup HS_RCC_definitions
+  * @{
+  */
+struct Rcc_ClkDiv {
+	u32 CkdGroupOfs;
+	u32 BitMask;
+	u32 DivShift;
+	u32 DivVal; /* Note in some IP, the real work divider equals (regval + 1) */
+};
+
 /**
   * @}
   */
@@ -236,6 +246,11 @@ _LONG_CALL_ bool PLL_State(void);
 _LONG_CALL_ void PLL_ClkSet(u32 PllClk);
 _LONG_CALL_ void OSC131K_Reset(void);
 
+/**
+  * @}defgroup HS_RCC_Exported_Functions HS_RCC Exported Functions
+  */
+_LONG_CALL_ void RCC_PeriphClockDivSet(const struct Rcc_ClkDiv *pdiv);
+_LONG_CALL_ u8 RCC_PeriphClockEnableChk(u32 APBPeriph_Clock_in);
 
 /* Registers Definitions --------------------------------------------------------*/
 /**************************************************************************//**
diff --git a/ameba/amebadplus/source/fwlib/include/ameba_gdma.h b/ameba/amebadplus/source/fwlib/include/ameba_gdma.h
index c1c6efbb..6ec98f68 100644
--- a/ameba/amebadplus/source/fwlib/include/ameba_gdma.h
+++ b/ameba/amebadplus/source/fwlib/include/ameba_gdma.h
@@ -612,6 +612,6 @@ _LONG_CALL_ void GDMA_SetChnlPriority(u8 GDMA_Index, u8 GDMA_ChNum, u32 ChnlPrio
 _LONG_CALL_ void GDMA_Suspend(u8 GDMA_Index, u8 GDMA_ChNum);
 _LONG_CALL_ void GDMA_Resume(u8 GDMA_Index, u8 GDMA_ChNum);
 _LONG_CALL_ u8   GDMA_Abort(u8 GDMA_Index, u8 GDMA_ChNum);
+_LONG_CALL_ u8   GDMA_ChannelIsActive(u8 GDMA_Index, u8 GDMA_ChNum);
 
-
-#endif //_AMEBA_GDMA_H_
\ No newline at end of file
+#endif //_AMEBA_GDMA_H_
diff --git a/ameba/amebadplus/source/fwlib/include/ameba_reset.h b/ameba/amebadplus/source/fwlib/include/ameba_reset.h
index 9b4226cb..fb5a74e6 100644
--- a/ameba/amebadplus/source/fwlib/include/ameba_reset.h
+++ b/ameba/amebadplus/source/fwlib/include/ameba_reset.h
@@ -83,6 +83,9 @@ enum CHIPEN_WORK_MODE {
 #define SYS_RESET_KEY 0x96969696
 #define SYS_RESET_TRIG 0x69696969
 
+#define IS_WDG_RESET(reason)	((reason) & (AON_BIT_RSTF_IWDG | AON_BIT_RSTF_WDG0 | \
+                                           AON_BIT_RSTF_WDG1 | AON_BIT_RSTF_WDG2))
+#define IS_SYS_RESET(reason)	((reason) & (AON_BIT_RSTF_KM0_SYS | AON_BIT_RSTF_KM4_SYS))
 
 extern void CHIPEN_WorkMode(enum CHIPEN_WORK_MODE mode);
 extern void CHIPEN_DebounceSet(u32 Debounce);
diff --git a/ameba/amebadplus/source/fwlib/include/ameba_rom_patch.h b/ameba/amebadplus/source/fwlib/include/ameba_rom_patch.h
index 92012748..5c1d27b8 100644
--- a/ameba/amebadplus/source/fwlib/include/ameba_rom_patch.h
+++ b/ameba/amebadplus/source/fwlib/include/ameba_rom_patch.h
@@ -12,27 +12,18 @@
   * @{
   */
 
+// add your constants here
+
 /** @defgroup ROM_PATCH_Structure_Type Structure Type
   * @{
   */
 
-struct Rcc_ClkDiv {
-	u32 CkdGroupOfs;
-	u32 BitMask;
-	u32 DivShift;
-	u32 DivVal; /* Note in some IP, the real work divider equals (regval + 1) */
-};
-/** @} */
-/** @} */
-
 /* Exported functions -------------------------------------------------------- */
 /** @defgroup ROM_PATCH_Exported_Functions ROM_PATCH Exported Functions
   * @{
   */
 
 // add your function statements here
-_LONG_CALL_ void RCC_PeriphClockDivSet(const struct Rcc_ClkDiv *pdiv);
-_LONG_CALL_ u8 RCC_PeriphClockEnableChk(u32 APBPeriph_Clock_in);
 _LONG_CALL_ void RCC_PeriphClockSource_UART(UART_TypeDef *UARTx, u32 Source);
 _LONG_CALL_ void RCC_PeriphClockSource_LOGUART(u32 Source);
 _LONG_CALL_ void UART_Init(UART_TypeDef *UARTx, UART_InitTypeDef *UART_InitStruct);
diff --git a/ameba/amebadplus/source/fwlib/include/ameba_trustzone.h b/ameba/amebadplus/source/fwlib/include/ameba_trustzone.h
index 77a65446..cd9f36c3 100644
--- a/ameba/amebadplus/source/fwlib/include/ameba_trustzone.h
+++ b/ameba/amebadplus/source/fwlib/include/ameba_trustzone.h
@@ -99,8 +99,8 @@ typedef enum {
   */
 #define SAU_INIT_CTRL_ALLNS  0
 
-#define SAU_ENTRYS_NUM			8
-#define MPC_ENTRYS_NUM			8
+#define SAU_ENTRY_NUM			8
+#define MPC_ENTRY_NUM			8
 
 #define MPC_CNT					2
 
@@ -156,4 +156,4 @@ __STATIC_INLINE u32 TrustZone_IsSecure(void)
 }
 
 
-#endif
\ No newline at end of file
+#endif
diff --git a/ameba/amebadplus/source/fwlib/ram_common/ameba_arch.c b/ameba/amebadplus/source/fwlib/ram_common/ameba_arch.c
index 5b031694..5cefbd9b 100644
--- a/ameba/amebadplus/source/fwlib/ram_common/ameba_arch.c
+++ b/ameba/amebadplus/source/fwlib/ram_common/ameba_arch.c
@@ -143,4 +143,3 @@ void irq_enable_restore(u32 PrevStatus)
 {
 	__set_PRIMASK(PrevStatus);
 }
-
diff --git a/ameba/amebadplus/source/fwlib/ram_common/ameba_bor.c b/ameba/amebadplus/source/fwlib/ram_common/ameba_bor.c
new file mode 100644
index 00000000..a31bdbf9
--- /dev/null
+++ b/ameba/amebadplus/source/fwlib/ram_common/ameba_bor.c
@@ -0,0 +1,185 @@
+/*
+ * Copyright (c) 2024 Realtek Semiconductor Corp.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "ameba_soc.h"
+
+/** @addtogroup Ameba_Periph_Driver
+ * @{
+ */
+
+/** @defgroup BOR
+ * @brief BOR driver modules
+ * @{
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup BOR_Exported_Functions BOR Exported Functions
+ * @{
+ */
+
+/**
+ * @brief Set BOR rising and falling threshold.
+ * @param Thres_Fall BOR falling threshold.
+ * 		This parameter can be one of the following values:
+ * 		@arg 00010: 2.82
+ * 		@arg 00011: 2.78
+ * 		@arg 00100: 2.74
+ * 		@arg 00101: 2.69
+ * 		@arg 00110: 2.65
+ * 		@arg 00111: 2.61
+ * 		@arg 01000: 2.56
+ * 		@arg 01001: 2.53
+ * 		@arg 01010: 2.49
+ * 		@arg 01011: 2.45
+ * 		@arg 01100: 2.41
+ * 		@arg 01101: 2.37
+ * 		@arg 01110: 2.32
+ * 		@arg 01111: 2.21
+ * 		@arg 10000: 2.16
+ * 		@arg 10001: 2.12
+ * 		@arg 10010: 2.08
+ * 		@arg 10011: 2.04
+ * 		@arg 10100: 2.00
+ * 		@arg 10101: 1.96
+ * 		@arg 10110: 1.93
+ * 		@arg 10111: 1.88
+ * 		@arg 11000: 1.83
+ * 		@arg 11001: 1.79
+ * 		@arg 11010: 1.75
+ * 		@arg 11011: 1.71
+ * 		@arg 11100: 1.69
+ * 		@arg 11101: 1.65
+ * 		@arg 11110: 1.61
+ * 		@arg 11111: 1.58
+ * @param Thres_Rise: BOR rising threshold.
+ * 		This parameter can be one of the following values:
+ * 		@arg 00000: 2.94
+ * 		@arg 00001: 2.86
+ * 		@arg 00010: 2.83
+ * 		@arg 00011: 2.79
+ * 		@arg 00100: 2.75
+ * 		@arg 00101: 2.71
+ * 		@arg 00110: 2.66
+ * 		@arg 00111: 2.62
+ * 		@arg 01000: 2.58
+ * 		@arg 01001: 2.54
+ * 		@arg 01010: 2.50
+ * 		@arg 01011: 2.46
+ * 		@arg 01100: 2.42
+ * 		@arg 01101: 2.38
+ * 		@arg 01110: 2.33
+ * 		@arg 01111: 2.22
+ * 		@arg 10000: 2.17
+ * 		@arg 10001: 2.13
+ * 		@arg 10010: 2.09
+ * 		@arg 10011: 2.05
+ * 		@arg 10100: 2.01
+ * 		@arg 10101: 1.97
+ * 		@arg 10110: 1.94
+ * 		@arg 10111: 1.89
+ * 		@arg 11000: 1.85
+ * 		@arg 11001: 1.80
+ * 		@arg 11010: 1.77
+ * 		@arg 11011: 1.73
+ * 		@arg 11100: 1.70
+ * 		@arg 11101: 1.66
+ * @note For chip to work normally, it is advised to make rising threshold 200mV larger than falling threshold at least.
+ * @return None
+ */
+void BOR_ThresholdSet(u32 Thres_Fall, u32 Thres_Rise)
+{
+	u32 temp;
+	assert_param(IS_BOR_TH_FALL(Thres_Fall));
+	assert_param(IS_BOR_TH_RISE(Thres_Rise));
+
+	temp = LDO_BASE->LDO_BOD;
+	temp &= ~(LDO_MASK_REG_BOD_F | LDO_MASK_REG_BOD_R);
+	temp |= LDO_REG_BOD_F(Thres_Fall) | LDO_REG_BOD_R(Thres_Rise);
+	LDO_BASE->LDO_BOD = temp;
+}
+
+/**
+ * @brief Enable BOD or not.
+ * @param newstatus This parameter can be one of the following values:
+ * 		@arg ENABLE: Enable bod.
+ * 		@arg DISABLE: Disable bod.
+ * @return None
+ */
+void BOR_Enable(u32 newstatus)
+{
+	if (newstatus == ENABLE) {
+		LDO_BASE->LDO_BOD |= LDO_BIT_REG_BOD_R_EN;
+	} else {
+		LDO_BASE->LDO_BOD &= ~LDO_BIT_REG_BOD_R_EN;
+	}
+}
+
+/**
+ * @brief Set BOR interrupt mode debounce cycle.
+ * @param Option BOR mode. This parameter can be one of the following values:
+ * 		@arg BOR_RESET: BOR reset mode
+ * 		@arg BOR_INTR: BOR interrupt mode
+ * @param Dbnc_Value Debounce cycle in unit of ANA4M clock cycles.
+ * 		@arg 000: 0us
+ * 		@arg 001: 100us
+ * 		@arg 010: 500us
+ * 		@arg 011: 1000us
+ * 		@arg 100: 2000us
+ * 		@arg 101: 4000us
+ * 		@arg 110: 8000us
+ * 		@arg 111: 16000us
+ * @return None
+ */
+void BOR_DbncSet(u32 Option, u32 Dbnc_Value)
+{
+	u32 temp = 0;
+	if (BOR_INTR == Option) {
+		assert_param(IS_BOR_INTR_DBNC_THRES(Dbnc_Value));
+		temp = HAL_READ32(SYSTEM_CTRL_BASE, REG_AON_BOR_CTRL);
+		temp &= ~AON_MASK_BOR_TDBC;
+		temp |= AON_BOR_TDBC(Dbnc_Value);
+		HAL_WRITE32(SYSTEM_CTRL_BASE, REG_AON_BOR_CTRL, temp);
+	}
+}
+
+/**
+ * @brief Clear BOR interrupt.
+ * @return None
+ */
+void BOR_ClearINT(void)
+{
+	u32 temp = 0;
+
+	temp = HAL_READ32(SYSTEM_CTRL_BASE, REG_AON_BOR_ISR);
+	temp |= AON_BIT_BOR_ISR;
+	HAL_WRITE32(SYSTEM_CTRL_BASE, REG_AON_BOR_ISR, temp);
+}
+
+/**
+ * @brief Enable BOR.
+ * @param Option BOR mode. This parameter can be one of the following values:
+ * 		@arg BOR_RESET: BOR reset mode
+ * 		@arg BOR_INTR: BOR interrupt mode
+ * @return None
+ */
+void BOR_ModeSet(u32 Option)
+{
+	u32 temp = 0;
+
+	if (BOR_INTR == Option) {
+		temp = HAL_READ32(SYSTEM_CTRL_BASE, REG_AON_BOR_CTRL);
+		temp |= AON_BIT_BOR_INTR_MODE;
+		HAL_WRITE32(SYSTEM_CTRL_BASE, REG_AON_BOR_CTRL, temp);
+
+		temp = HAL_READ32(PMC_BASE, WAK_MASK0_NP);
+		temp |= PMC_WAK_KM0_IMR_31_0(WAKE_SRC_BOR);
+		HAL_WRITE32(PMC_BASE, WAK_MASK0_NP, temp);
+	} else {
+		temp = HAL_READ32(SYSTEM_CTRL_BASE, REG_AON_BOR_CTRL);
+		temp &= ~AON_BIT_BOR_INTR_MODE;
+		HAL_WRITE32(SYSTEM_CTRL_BASE, REG_AON_BOR_CTRL, temp);
+	}
+}
diff --git a/ameba/amebadplus/source/fwlib/ram_common/ameba_clk.c b/ameba/amebadplus/source/fwlib/ram_common/ameba_clk.c
index 414d4551..424551cf 100644
--- a/ameba/amebadplus/source/fwlib/ram_common/ameba_clk.c
+++ b/ameba/amebadplus/source/fwlib/ram_common/ameba_clk.c
@@ -176,10 +176,10 @@ u32 OSC131K_Calibration(u32 ppm_limit)
 	}
 
 	cur_ppm = delta * 1000000 / target_40m_counter;
-	RTK_LOGI(TAG, "[CAL131K]: delta:%d target:%d PPM: %d PPM_Limit:%d \n", delta, target_40m_counter, cur_ppm, ppm_limit);
+	RTK_LOGI(TAG, "[CAL131K]: delta:%lu target:%lu PPM: %lu PPM_Limit:%lu \n", delta, target_40m_counter, cur_ppm, ppm_limit);
 
 	if (cur_ppm >= ppm_limit) {
-		RTK_LOGE(TAG, "[CAL131K]: !!! cal fail !!! PPM: %d PPM_Limit:%d \n", cur_ppm, ppm_limit);
+		RTK_LOGE(TAG, "[CAL131K]: !!! cal fail !!! PPM: %lu PPM_Limit:%lu \n", cur_ppm, ppm_limit);
 		assert_param(0);
 	}
 
@@ -354,10 +354,10 @@ u32 OSC4M_Calibration(u32 ppm_limit)
 
 cal_end:
 	cur_ppm = delta * 1000000 / target_40m_counter;
-	RTK_LOGI(TAG, "[CAL4M]: delta:%d target:%d PPM: %d PPM_Limit:%d \n", delta, target_40m_counter, cur_ppm, ppm_limit);
+	RTK_LOGI(TAG, "[CAL4M]: delta:%lu target:%lu PPM: %lu PPM_Limit:%lu \n", delta, target_40m_counter, cur_ppm, ppm_limit);
 
 	if (cur_ppm >= ppm_limit) {
-		RTK_LOGW(TAG, "[CAL4M]: PPM: %d PPM_Limit:%d \n", cur_ppm, ppm_limit);
+		RTK_LOGW(TAG, "[CAL4M]: PPM: %lu PPM_Limit:%lu \n", cur_ppm, ppm_limit);
 		assert_param(0);
 	}
 
@@ -441,4 +441,67 @@ void OSC131K_Reset(void)
 	/*reset osc 131k counter, only for RTL6845*/
 	LDO_BASE->LDO_32_OSC_XTAL_POW &= ~LDO_BIT_POW_32KOSC;
 	LDO_BASE->LDO_32_OSC_XTAL_POW |= LDO_BIT_POW_32KOSC;
-}
\ No newline at end of file
+}
+
+/**
+  * @brief  Set specific APB peripheral's clock divider
+  * @param  pdiv: Specifies the peripheral's cke offset address, divider, shift, and mask field.
+  * @note	In some IP, the real work divider equals (regval + 1).
+  * @retval None
+  */
+void RCC_PeriphClockDivSet(const struct Rcc_ClkDiv *pdiv)
+{
+	u32 Regtmp;
+
+	u32 GroupOffset = pdiv->CkdGroupOfs;
+	u32 DivMask = pdiv->BitMask;
+
+	assert_param((GroupOffset == REG_LSYS_CKD_GRP0) || (GroupOffset == REG_LSYS_CKD_GRP1));
+
+	Regtmp = HAL_READ32(SYSTEM_CTRL_BASE, GroupOffset);
+	Regtmp &= (~DivMask);
+	Regtmp |= (((pdiv->DivVal) << (pdiv->DivShift)) & DivMask);
+
+	HAL_WRITE32(SYSTEM_CTRL_BASE, GroupOffset, Regtmp);
+
+}
+
+/**
+  * @brief  Check whether the APB peripheral's clock has been enabled or not
+  * @param  APBPeriph_Clock_in: specifies the APB peripheral to check.
+  *      This parameter can be one of @ref APBPeriph_UART0_CLOCK, APBPeriph_ATIM_CLOCK and etc.
+  * @retval TRUE: The APB peripheral's clock has been enabled
+  * 		FALSE: The APB peripheral's clock has not been enabled
+  */
+u8 RCC_PeriphClockEnableChk(u32 APBPeriph_Clock_in)
+{
+	u8 ret;
+	u32 CkeRegVal, CkeBitMask;
+	u32 CkeRegOffset = 0;
+
+	u32 ClkRegIndx = (APBPeriph_Clock_in >> 30) & 0x03;
+	assert_param((ClkRegIndx == 0x0) || (ClkRegIndx == 0x1) || (ClkRegIndx == 0x3));
+
+	switch (ClkRegIndx) {
+	case 0x0:
+		CkeRegOffset = REG_LSYS_CKE_GRP0;
+		break;
+	case 0x1:
+		CkeRegOffset = REG_LSYS_CKE_GRP1;
+		break;
+	case 0x3:
+		CkeRegOffset = REG_AON_CLK;
+		break;
+	}
+
+	CkeRegVal = HAL_READ32(SYSTEM_CTRL_BASE, CkeRegOffset);
+	CkeBitMask = APBPeriph_Clock_in & (~(BIT(31) | BIT(30)));
+
+	if (CkeRegVal & CkeBitMask) {
+		ret = TRUE;
+	} else {
+		ret = FALSE;
+	}
+
+	return ret;
+}
diff --git a/ameba/amebadplus/source/fwlib/ram_common/ameba_comparator.c b/ameba/amebadplus/source/fwlib/ram_common/ameba_comparator.c
new file mode 100644
index 00000000..3c6a17a3
--- /dev/null
+++ b/ameba/amebadplus/source/fwlib/ram_common/ameba_comparator.c
@@ -0,0 +1,521 @@
+/*
+ * Copyright (c) 2024 Realtek Semiconductor Corp.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "ameba_soc.h"
+
+/** @addtogroup Ameba_Periph_Driver
+  * @{
+  */
+
+/** @addtogroup ADC
+  * @brief Comparator driver modules
+  * @{
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup COMP_Exported_Functions COMP Exported Functions
+  * @{
+  */
+
+/**
+  * @brief	 Initializes the parameters in the CMP_InitStruct with default value.
+  * @param CMP_InitStruct: pointer to a CMP_InitTypeDef structure that contains
+  *         the configuration information for the Comparator peripheral.
+  * @retval None
+  */
+void CMP_StructInit(CMP_InitTypeDef *CMP_InitStruct)
+{
+	u8 i;
+
+	for (i = 0; i < COMP_CH_NUM; i++) {
+		CMP_InitStruct->CMP_ChanCtrl[i].CMP_ChIndex = i;
+		CMP_InitStruct->CMP_ChanCtrl[i].CMP_Ref0 = 0;		// Vref0 = 0.1*0=0v
+		CMP_InitStruct->CMP_ChanCtrl[i].CMP_Ref1 = 0x1F;		//  Vref1 = 0.1*31=3.1v
+		CMP_InitStruct->CMP_ChanCtrl[i].CMP_WakeType = COMP_WK_NONE;
+		CMP_InitStruct->CMP_ChanCtrl[i].CMP_WakeSysCtrl = COMP_WITHIN_REF0_AND_REF1;
+		CMP_InitStruct->CMP_ChanCtrl[i].CMP_WakeADCCtrl = COMP_WITHIN_REF0_AND_REF1;
+	}
+}
+
+/**
+  * @brief	 Initializes the Comparator according to the specified parameters in CMP_InitStruct.
+  * @param  CMP_InitStruct: pointer to a CMP_InitTypeDef structure that contains
+  *         the configuration for the Comparator peripheral.
+  * @retval None
+  */
+void CMP_Init(CMP_InitTypeDef *CMP_InitStruct)
+{
+	u8 i, index;
+	u32 tmp, val_ch = 0;
+
+	CMP_TypeDef *comparator = CMP_DEV;
+
+	if (TrustZone_IsSecure()) {
+		comparator = CMP_DEV_S;
+	}
+
+	CMP_CHTypeDef *compChan = CMP_InitStruct->CMP_ChanCtrl;
+
+	CMP_Cmd(DISABLE);
+
+	tmp = comparator->COMP_INTR_CTRL;
+
+	for (i = 0; i < COMP_CH_NUM; i++) {
+		index = compChan[i].CMP_ChIndex;
+
+		val_ch |= (u32)(index << COMP_SHIFT_CHSW(i));
+
+		comparator->COMP_REF_CHx[index] = (u32)(COMP_REF0_CHx(compChan[i].CMP_Ref0) | COMP_REF1_CHx(compChan[i].CMP_Ref1));
+
+		if (compChan[i].CMP_WakeType & COMP_WK_ADC) {
+			tmp &= ~ COMP_MASK_WK_ADC_CTRL(index);
+			tmp |= (compChan[i].CMP_WakeADCCtrl << COMP_SHIFT_WK_ADC_CTRL(index)) | \
+				   COMP_WK_ADC_EN(index);
+		}
+
+		if (compChan[i].CMP_WakeType & COMP_WK_SYS) {
+			tmp &= ~ COMP_MASK_WK_SYS_CTRL(index);
+			tmp |= (compChan[i].CMP_WakeSysCtrl << COMP_SHIFT_WK_SYS_CTRL(index)) | \
+				   COMP_WK_SYS_EN(index);
+		}
+	}
+
+	comparator->COMP_INTR_CTRL = tmp;
+	comparator->COMP_CHSW_LIST = val_ch;
+	comparator->COMP_AUTO_SHUT = COMP_BIT_AUTO_SHUT;
+
+	tmp = PLL_BASE->PLL_LPSD;
+	tmp |= PLL_BIT_SD_POSEDGE;
+	PLL_BASE->PLL_LPSD = tmp;
+}
+
+/**
+  * @brief  Enable or Disable the Comparator peripheral.
+  * @param  NewState: new state of the Comparator peripheral.
+  *   			This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void CMP_Cmd(u32 NewState)
+{
+	CMP_TypeDef *comparator = CMP_DEV;
+
+	if (TrustZone_IsSecure()) {
+		comparator = CMP_DEV_S;
+	}
+
+	if (NewState != DISABLE) {
+		comparator->COMP_EN_TRIG |= COMP_BIT_ENABLE;
+	} else {
+		comparator->COMP_EN_TRIG &= ~COMP_BIT_ENABLE;
+	}
+}
+
+/**
+  * @brief  Indicate the Comparator is busy or not .
+  * @param  None
+  * @retval   busy status value:
+  *           - 1: Busy
+  *           - 0: Not Busy.
+  */
+u32 CMP_Busy(void)
+{
+	CMP_TypeDef *comparator = CMP_DEV;
+
+	if (TrustZone_IsSecure()) {
+		comparator = CMP_DEV_S;
+	}
+
+	if (comparator->COMP_BUSY_STS & COMP_BIT_BUSY_STS) {
+		return 1;
+	} else {
+		return 0;
+	}
+}
+
+/**
+  * @brief  ENABLE/DISABLE  the comparator's interrupt bits.
+  * @param  Cmp_IT: specifies the interrupt bits to be configured.
+  *     This parameter can be one or combinations of the following values:
+  *     @arg COMP_IT_CTN_VS: Rising edge interrupt of hysteresis cmp result at continuous mode.
+  *     @arg COMP_IT_CTN_VH: Rising edge interrupt of vref1 cmp result at continuous mode.
+  *     @arg COMP_IT_CTN_VL: Rising edge interrupt of vref0 cmp result at continuous mode.
+  * @param NewState: ENABLE or DISABLE
+  * @note None
+  * @retval None
+  */
+void CMP_INTConfig(u32 Cmp_IT, u32 NewState)
+{
+	/* Check the parameters */
+	assert_param(IS_COMP_IT(Cmp_IT));
+
+	CMP_TypeDef *comparator = CMP_DEV;
+
+	if (TrustZone_IsSecure()) {
+		comparator = CMP_DEV_S;
+	}
+
+	if (NewState != DISABLE) {
+		/* Enable the Interrupt sources */
+		comparator->COMP_INTR_CTRL |= COMP_IT_CONFIG(Cmp_IT);
+	} else {
+		/* Disable the Interrupt sources */
+		comparator->COMP_INTR_CTRL &= ~COMP_IT_CONFIG(Cmp_IT);
+	}
+}
+
+/**
+  * @brief Set the comparator's comparison detection mode.
+  * @param det_mode: can be one of the following values:
+  *		@arg COMP_LEVEL_DETECT: Level detection mode. When the comparison criterion matches, bit_comp_wkx will send interrupt continuously.
+  *		@arg COMP_EDGE_DETECT: Edge detection mode. When the comparison criterion matches, bit_comp_wkx will send interrupt once at the time of matching.
+  * @retval None
+  */
+void CMP_SetCompMode(u8 det_mode)
+{
+	CMP_TypeDef *comparator = CMP_DEV;
+
+	if (TrustZone_IsSecure()) {
+		comparator = CMP_DEV_S;
+	}
+
+	if (COMP_LEVEL_DETECT == det_mode) {
+		comparator->COMP_INTR_CTRL &= ~COMP_BIT_IT_DET_MOD;
+	} else {
+		comparator->COMP_INTR_CTRL |= COMP_BIT_IT_DET_MOD;
+	}
+}
+
+/**
+  * @brief  Get value of Comparator Wakeup ADC/SYS Status Register .
+  * @param  None
+  * @retval Current Comparator Wakeup ADC/SYS and cmp result's rising edge interrupt status
+  */
+u32 CMP_GetISR(void)
+{
+	CMP_TypeDef *comparator = CMP_DEV;
+
+	if (TrustZone_IsSecure()) {
+		comparator = CMP_DEV_S;
+	}
+
+	return comparator->COMP_WK_STS;
+}
+
+/**
+  * @brief  Clear pending bit in Comparator Wakeup ADC/SYS Status Register.
+  * @param  Cmp_IT: specifies the interrupt bits to be cleared.
+  *     This parameter can be one or combinations of the following values:
+  *     @arg COMP_IT_CTN_VS: Rising edge interrupt of hysteresis cmp result at continuous mode.
+  *     @arg COMP_IT_CTN_VH: Rising edge interrupt of vref1 cmp result at continuous mode.
+  *     @arg COMP_IT_CTN_VL: Rising edge interrupt of vref0 cmp result at continuous mode.
+  *     @arg COMP_WK_SYS_EN(3): Channel3 wakeup system
+  *     @arg COMP_WK_SYS_EN(2): Channel2 wakeup system
+  *     @arg COMP_WK_SYS_EN(1): Channel1 wakeup system
+  *     @arg COMP_WK_SYS_EN(0): Channel0 wakeup system
+  *     @arg COMP_WK_ADC_EN(3): Channel3 wakeup ADC
+  *     @arg COMP_WK_ADC_EN(2): Channel2 wakeup ADC
+  *     @arg COMP_WK_ADC_EN(1): Channel1 wakeup ADC
+  *     @arg COMP_WK_ADC_EN(0): Channel0 wakeup ADC
+  * @retval   None
+  */
+void CMP_INTClearPendingBit(u32 Cmp_IT)
+{
+	CMP_TypeDef *comparator = CMP_DEV;
+
+	if (TrustZone_IsSecure()) {
+		comparator = CMP_DEV_S;
+	}
+
+	comparator->COMP_WK_STS = Cmp_IT;
+}
+
+/**
+  * @brief  Get the comparison result .
+  * @param  channel : the Comparator channel index
+  * @retval  The comparison result of specified channel index. The return value can be:
+  *		-0: when Vin < Vref0
+  *		-2: when Vin > Vref0 & Vin < Vref1
+  *		-3: when Vin > Vref1
+  */
+u32 CMP_GetCompStatus(u8 channel)
+{
+	CMP_TypeDef *comparator = CMP_DEV;
+
+	if (TrustZone_IsSecure()) {
+		comparator = CMP_DEV_S;
+	}
+
+	u32 value = (comparator->COMP_CH_STS & COMP_MASK_CH_STS(channel)) >> \
+				COMP_SHIFT_CH_STS(channel);
+
+	return value;
+}
+
+/**
+  * @brief  Reset the channel switch to default state.
+  * @param  None
+  * @retval  None
+  */
+void CMP_ResetCSwList(void)
+{
+	CMP_TypeDef *comparator = CMP_DEV;
+
+	if (TrustZone_IsSecure()) {
+		comparator = CMP_DEV_S;
+	}
+
+	comparator->COMP_RST_LIST = COMP_BIT_RST_LIST;
+	comparator->COMP_RST_LIST = 0;
+}
+
+/**
+  * @brief  Enable or disable automatic shut after the analog conversion is done.
+  * @param  NewState: can be one of the following value:
+  *			@arg ENABLE: The analog module and mux will be disabled automatically after the analog conversion is done.
+  *			@arg DISABLE: The analog module and mux will not be disabled.
+  * @retval  None.
+  */
+void CMP_AutoShutCmd(u32 NewState)
+{
+	CMP_TypeDef *comparator = CMP_DEV;
+
+	if (TrustZone_IsSecure()) {
+		comparator = CMP_DEV_S;
+	}
+
+	if (NewState != DISABLE) {
+		comparator->COMP_AUTO_SHUT |= COMP_BIT_AUTO_SHUT;
+	} else {
+		comparator->COMP_AUTO_SHUT &= ~COMP_BIT_AUTO_SHUT;
+	}
+}
+
+/**
+  * @brief  Controls the automatic channel swtich enabled or disabled in Comparator Automatic Mode.
+  * @param  NewState: can be one of the following value:
+  *			@arg ENABLE: Enable the automatic channel switch.
+  *				When setting this bit, an automatic channel switch starts from the first channel in the channel switch list.
+  *			@arg DISABLE:  Disable the automatic channel switch.
+  *				If an automatic channel switch is in progess, writing 0 will terminate the automatic channel switch.
+  * @retval  None.
+  */
+void CMP_AutoCSwCmd(u32 NewState)
+{
+	CMP_TypeDef *comparator = CMP_DEV;
+
+	if (TrustZone_IsSecure()) {
+		comparator = CMP_DEV_S;
+	}
+
+	if (NewState != DISABLE) {
+		comparator->COMP_AUTOSW_EN = COMP_BIT_AUTOSW_EN;
+		comparator->COMP_EN_TRIG |= COMP_BIT_EN_TRIG;
+	} else {
+		comparator->COMP_AUTOSW_EN = 0;
+		comparator->COMP_EN_TRIG &= ~COMP_BIT_EN_TRIG;
+	}
+}
+
+/**
+  * @brief  Enabled or disabled software-trigger channel switch in Comparator Software-Trigger Mode.
+  * @param  NewState: can be one of the following value:
+  *			@arg ENABLE: Enable the software-trigger channel switch.
+  *				When setting this bit, do one channel switch in the channel switch list.
+  *			@arg DISABLE:  Disable the software-trigger channel switch.
+  * @retval  None.
+  */
+void CMP_SwTrigCmd(u32 NewState)
+{
+	CMP_TypeDef *comparator = CMP_DEV;
+
+	if (TrustZone_IsSecure()) {
+		comparator = CMP_DEV_S;
+	}
+
+	if (NewState != DISABLE) {
+		comparator->COMP_EN_TRIG |= COMP_BIT_EN_TRIG;
+	} else {
+		comparator->COMP_EN_TRIG &= ~COMP_BIT_EN_TRIG;
+	}
+}
+
+/**
+  * @brief	 Initialize the trigger timer when in Comparator Timer-Trigger Mode.
+  * @param  Tim_Idx: The timer index would be used to make the Comparator module do a comparison.
+  * @param  PeriodMs: Indicate the period of trigger timer.
+  * @param  NewState: can be one of the following value:
+  *			@arg ENABLE: Enable the Comparator timer trigger mode.
+  *			@arg DISABLE: Disable the Comparator timer trigger mode.
+  * @retval  None.
+  * @note  Used in Comparator Timer-Trigger Mode, period range: 1ms ~ 131071ms.
+  */
+void CMP_TimerTrigCmd(u8 Tim_Idx, u32 PeriodMs, u32 NewState)
+{
+	CMP_TypeDef *comparator = CMP_DEV;
+
+	if (TrustZone_IsSecure()) {
+		comparator = CMP_DEV_S;
+	}
+
+	RTIM_TimeBaseInitTypeDef TIM_InitStruct;
+
+	assert_param(IS_ADC_VALID_TIM(Tim_Idx));
+	assert_param(PeriodMs > 0 && PeriodMs < 131072); // avoid overflow
+
+	comparator->COMP_EXT_TRIG_TIMER_SEL = Tim_Idx;
+
+	if (NewState != DISABLE) {
+		RTIM_TimeBaseStructInit(&TIM_InitStruct);
+		TIM_InitStruct.TIM_Idx = Tim_Idx;
+		TIM_InitStruct.TIM_Period = (PeriodMs * 32768) / 1000; //ms to tick
+
+		RTIM_TimeBaseInit(TIMx[Tim_Idx], &TIM_InitStruct, TIMx_irq[Tim_Idx], (IRQ_FUN)NULL, (u32)NULL);
+		RTIM_Cmd(TIMx[Tim_Idx], ENABLE);
+
+		comparator->COMP_EXT_TRIG_CTRL = COMP_BIT_EXT_WK_TIMER;
+	} else {
+		RTIM_Cmd(TIMx[Tim_Idx], DISABLE);
+		comparator->COMP_EXT_TRIG_CTRL = 0;
+	}
+}
+
+/**
+  * @brief Enable or disable continuous sample function in autoswitch mode.
+  * @param  NewState: can be one of the following value:
+  *			@arg ENABLE: Enable continuous sample function.
+  *			@arg DISABLE: Disable continuous sample function.
+  * @note Continuous sample function can only take effect in autoswitch mode with autoshut disabled meanwhile.
+  * @retval  None.
+  */
+void CMP_ContinousCmd(u32 NewState)
+{
+	CMP_TypeDef *comparator = CMP_DEV;
+
+	if (TrustZone_IsSecure()) {
+		comparator = CMP_DEV_S;
+	}
+
+	if (NewState != DISABLE) {
+		comparator->COMP_CONTINUOUS_CTRL_0 |= COMP_BIT_CONTINUOUS_EN;
+	} else {
+		comparator->COMP_CONTINUOUS_CTRL_0 &= ~COMP_BIT_CONTINUOUS_EN;
+	}
+}
+
+/**
+  * @brief Enable or disable hysteresis circuit function in continuous function.
+  * @param  NewState: can be one of the following value:
+  *			@arg ENABLE: Enable hysteresis circuit function.
+  *			@arg DISABLE: Disable hysteresis circuit function.
+  * @note Hysteresis circuit function can only take effect in continuous function.
+  * @retval  None.
+  */
+void CMP_HystCmd(u32 NewState)
+{
+	CMP_TypeDef *comparator = CMP_DEV;
+
+	if (TrustZone_IsSecure()) {
+		comparator = CMP_DEV_S;
+	}
+
+	u32 reg_chsw = comparator->COMP_CHSW_LIST;
+
+	if (NewState != DISABLE) {
+		/* check whether in continuous mode */
+		assert_param(comparator->COMP_CONTINUOUS_CTRL_0 & COMP_BIT_CONTINUOUS_EN);
+		assert_param(comparator->COMP_AUTOSW_EN & COMP_BIT_AUTOSW_EN);
+		assert_param((comparator->COMP_AUTO_SHUT & COMP_BIT_AUTO_SHUT) == 0);
+		assert_param(COMP_GET_CHSW_0(reg_chsw) == COMP_GET_CHSW_1(reg_chsw));
+		assert_param(COMP_GET_CHSW_1(reg_chsw) == COMP_GET_CHSW_2(reg_chsw));
+		assert_param(COMP_GET_CHSW_2(reg_chsw) == COMP_GET_CHSW_3(reg_chsw));
+
+		comparator->COMP_CONTINUOUS_CTRL_0 |= COMP_BIT_HYST_EN;
+	} else {
+		comparator->COMP_CONTINUOUS_CTRL_0 &= ~COMP_BIT_HYST_EN;
+	}
+}
+
+/**
+  * @brief	Select specified comparison result as ZCD output.
+  * @param  Src_Type: Comparison result type.
+  *     This parameter can be one of the following values:
+  *			@arg COMP_ZCD_SRC_NONE: None.
+  *			@arg COMP_ZCD_SRC_VHOUT: ZCD out is from high level Vref1 cmp.
+  *			@arg COMP_ZCD_SRC_VLOUT: ZCD out is from low level Vref0 cmp.
+  *			@arg COMP_ZCD_SRC_VSOUT: ZCD out is from Hysteresis cmp.
+  *	@note Make sure hysteresis function is enabled when select COMP_ZCD_SRC_VSOUT.
+  * @retval  None.
+  */
+void CMP_SetZcdSrc(u32 Src_Type)
+{
+	/* Check the parameters */
+	assert_param(IS_COMP_ZCD_SRC_TYPE(Src_Type));
+
+	CMP_TypeDef *comparator = CMP_DEV;
+
+	if (TrustZone_IsSecure()) {
+		comparator = CMP_DEV_S;
+	}
+
+	u32 temp = comparator->COMP_CONTINUOUS_CTRL_0;
+	temp &= ~ COMP_MASK_ZCD_SEL;
+	temp |= COMP_ZCD_SEL(Src_Type);
+	comparator->COMP_CONTINUOUS_CTRL_0 = temp;
+
+}
+
+/**
+  * @brief	Set debounce counter for comparison output of different types.
+  * @param  Dbc_Type: Indicate the comparison type.
+  *     This parameter can be one of the following values:
+  *			@arg COMP_DBC_VS: Debounce result of hysteresis cmp.
+  *			@arg COMP_DBC_VH: Debounce result of high level Vref1 cmp.
+  *			@arg COMP_DBC_VL: Debounce result of lov level Vref0 cmp.
+  * @param  Dbc_Cnt: Debounce counter to be set.
+  *	@note Dbc_Cnt = 0 means debounce function is disabled.
+  * @retval  None.
+  */
+void CMP_SetDbcCnt(u8 Dbc_Type, u32 Dbc_Cnt)
+{
+	/* Check the parameters */
+	assert_param(IS_COMP_DBC_TYPE(Dbc_Type));
+
+	CMP_TypeDef *comparator = CMP_DEV;
+
+	if (TrustZone_IsSecure()) {
+		comparator = CMP_DEV_S;
+	}
+
+	/* Set debounce counter for Hysterisis comparison result S_out */
+	if (COMP_DBC_VS == Dbc_Type) {
+		/* Check the parameters */
+		assert_param(IS_COMP_VS_BC_CNT(Dbc_Cnt));
+
+		u32 temp = comparator->COMP_CONTINUOUS_CTRL_0;
+		temp &= ~ COMP_MASK_VS_DBC_CNT;
+		temp |= COMP_VS_DBC_CNT(Dbc_Cnt);
+		comparator->COMP_CONTINUOUS_CTRL_0 = temp;
+		/* Set debounce counter for Vref1 comparison result H_out */
+	} else if (COMP_DBC_VH == Dbc_Type) {
+		/* Check the parameters */
+		assert_param(IS_COMP_VH_BC_CNT(Dbc_Cnt));
+
+		u32 temp = comparator->COMP_CONTINUOUS_CTRL_1;
+		temp &= ~ COMP_MASK_VH_DBC_CNT;
+		temp |= COMP_VH_DBC_CNT(Dbc_Cnt);
+		comparator->COMP_CONTINUOUS_CTRL_1 = temp;
+		/* Set debounce counter for Vref0 comparison result L_out */
+	} else if (COMP_DBC_VL == Dbc_Type) {
+		/* Check the parameters */
+		assert_param(IS_COMP_VL_BC_CNT(Dbc_Cnt));
+
+		u32 temp = comparator->COMP_CONTINUOUS_CTRL_1;
+		temp &= ~ COMP_MASK_VL_DBC_CNT;
+		temp |= COMP_VL_DBC_CNT(Dbc_Cnt);
+		comparator->COMP_CONTINUOUS_CTRL_1 = temp;
+	}
+
+}
diff --git a/ameba/amebadplus/source/fwlib/ram_common/ameba_fault_handle.c b/ameba/amebadplus/source/fwlib/ram_common/ameba_fault_handle.c
new file mode 100644
index 00000000..6b585827
--- /dev/null
+++ b/ameba/amebadplus/source/fwlib/ram_common/ameba_fault_handle.c
@@ -0,0 +1,257 @@
+/*
+ * Copyright (c) 2024 Realtek Semiconductor Corp.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "ameba_soc.h"
+#include "ameba_v8m_crashdump.h"
+#include "ameba_fault_handle.h"
+
+static const char *const TAG = "FAULT";
+
+#if defined(CONFIG_ARM_CORE_CM4)
+/* Redefine secure fault handler and replace old INT_SecureFault in rom code. */
+void HANDLER_SecureFault(void)
+{
+	__ASM volatile(
+		"MRS 		R0, MSP_NS				\n\t"
+		"MRS 		R1, PSP_NS				\n\t"
+		"MOV 		R2, LR					\n\t"
+		"MRS 		R3, MSP_NS				\n\t"
+		"STMDB 		R3!, {R4-R11}			\n\t" //Note: [MSPLIM_NS, MSP_NS] may overflow, MSP_NS is not update.
+		"MOV 		R3, #4					\n\t"
+		"B			Fault_Handler		    \n\t"
+	);
+}
+
+void HANDLER_MemFault(void)
+{
+	__ASM volatile(
+		"MRS 		R0, MSP					\n\t"
+		"MRS 		R1, PSP					\n\t"
+		"MOV 		R2, LR					\n\t"
+		"MOV 		R3, #3					\n\t"
+		"PUSH 		{R4-R11}				\n\t"
+		"B			Fault_Handler		    \n\t"
+	);
+}
+
+void HANDLER_BusFault(void)
+{
+	__ASM volatile(
+		"MRS 		R0, MSP					\n\t"
+		"MRS 		R1, PSP					\n\t"
+		"MOV 		R2, LR					\n\t"
+		"MOV 		R3, #2					\n\t"
+		"PUSH 		{R4-R11}				\n\t"
+		"B			Fault_Handler		    \n\t"
+	);
+}
+
+void HANDLER_UsageFault(void)
+{
+	__ASM volatile(
+		"MRS 		R0, MSP					\n\t"
+		"MRS 		R1, PSP					\n\t"
+		"MOV 		R2, LR					\n\t"
+		"MOV 		R3, #1					\n\t"
+		"PUSH 		{R4-R11}				\n\t"
+		"B			Fault_Handler		    \n\t"
+	);
+}
+
+void HANDLER_HardFault(void)
+{
+	__ASM volatile(
+		"MRS 		R0, MSP					\n\t"
+		"MRS 		R1, PSP					\n\t"
+		"MOV 		R2, LR					\n\t"
+		"MOV 		R3, #0					\n\t"
+		"PUSH 		{R4-R11}				\n\t"
+		"B			Fault_Handler		    \n\t"
+	);
+}
+void Fault_Handler(uint32_t mstack[], uint32_t pstack[], uint32_t lr_value, uint32_t fault_id)
+{
+	uint32_t *cstack;
+
+	uint32_t *extra_regs = mstack;
+
+	uint32_t control_ns = 0;
+
+	uint32_t regs[17] = {0x0};
+
+	u8 is_psp = 0;
+
+	enum {
+		REG_EXCR = 0, REG_R4, REG_R5, REG_R6, REG_R7, REG_R8, REG_R9, REG_R10, REG_R11, \
+		REG_R0, REG_R1, REG_R2, REG_R3, REG_R12, REG_LR, REG_EPC, REG_xPSR, REG_END
+	};
+	/* If Bit[0] is 1, here is Secure world. */
+	if (lr_value & EXC_RETURN_ES) {
+		/* 1.1 Exception cames from secure world. */
+		if (lr_value & EXC_RETURN_S) {
+			/* Whether PSP_S has been used*/
+			if ((lr_value & EXC_RETURN_MODE) && (lr_value & EXC_RETURN_SPSEL)) {
+				is_psp = 1;
+			}
+			/* 1.2 Exception cames from non-secure world.*/
+		} else {
+			/* what stack was used according to control_ns[1] in non-secure world!*/
+			control_ns = __TZ_get_CONTROL_NS();
+			if ((lr_value & EXC_RETURN_MODE) && (control_ns & CONTROL_SPSEL_Msk)) {
+				is_psp = 1;
+			}
+		}
+
+	} else {
+		/* 2.1 Non-Secure world cannot dump registers about exception from secure world. */
+		if (lr_value & EXC_RETURN_S) {
+			RTK_LOGA(TAG, "\nNon-Secure world cannot dump registers about exception from secure world!\n");
+			while (1);
+			/* 2.2 Non-secure exception from non-secure world!*/
+		} else {
+			if ((lr_value & EXC_RETURN_MODE) && (lr_value & EXC_RETURN_SPSEL)) {
+				is_psp = 1;
+			}
+		}
+	}
+
+	regs[REG_EXCR] = lr_value;
+	/* put r4-r11 to mstack before
+	High addr -> |  xxx  | <--- &extra_regs[0] is mstack;
+	  ^          |  R11  | <--- extra_regs[-1]
+	  |	         |  R10  |
+	  |	         |  ...  |
+	Low addr  -> |  R4   | <--- extra_regs[-8]*/
+
+	extra_regs--; //point to R11
+	for (int i = REG_R4; i <= REG_R11; i++) {
+		regs[i] = extra_regs[-REG_R11 + i];
+	}
+
+	cstack = is_psp ? pstack : mstack;
+
+	for (int i = REG_R0; i < REG_END; i++) {
+		regs[i] = cstack[i - REG_R0];
+	}
+
+	crash_dump((uint32_t *)cstack[REG_EPC], cstack, regs);
+
+	if (fault_id == SECUREFAULT_ID) {
+		RTK_LOGA(TAG, "SFSR  = 0x%08lx\r\n", SAU->SFSR);
+		RTK_LOGA(TAG, "SFAR  = 0x%08lx\r\n", SAU->SFAR);
+	}
+	if (control_ns) {
+		RTK_LOGA(TAG, "CONTROL_NS = 0x%08lX\r\n", control_ns);
+	}
+	RTK_LOGA(TAG, "SHCSR = 0x%08lx\r\n", SCB->SHCSR);
+	RTK_LOGA(TAG, "AIRCR = 0x%08lx\r\n", SCB->AIRCR);
+	RTK_LOGA(TAG, "CONTROL = 0x%08lx\r\n", __get_CONTROL());
+
+	extern void INT_HardFault_C(uint32_t mstack[], uint32_t pstack[], uint32_t lr_value, uint32_t fault_id);
+	INT_HardFault_C(mstack, pstack, lr_value, fault_id);
+}
+#else
+void HANDLER_HardFault(void)
+{
+	__ASM volatile(
+		"MRS 		R0, MSP					\n\t"
+		"MRS 		R1, PSP					\n\t"
+		"MOV 		R2, LR					\n\t" /* Third parameter is LR current value */
+		"MOV 		R3, #0					\n\t"
+		"PUSH 		{R4-R7}					\n\t"
+		"MOV		R6, #16					\n\t"
+		"ADD		R4, R0, R6				\n\t" /* Skip R4-R7, and point to top of mstack*/
+		"MOV 		R5, R8					\n\t"
+		"STR        R5, [R4, #0]			\n\t"
+		"MOV 		R5, R9					\n\t"
+		"STR        R5, [R4, #4]			\n\t"
+		"MOV 		R5, R10					\n\t"
+		"STR        R5, [R4, #8]			\n\t"
+		"MOV 		R5, R11					\n\t"
+		"STR        R5, [R4, #12]			\n\t"
+		"B			Fault_Handler			\n\t"
+	);
+}
+
+void Fault_Handler(uint32_t mstack[], uint32_t pstack[], uint32_t lr_value, uint32_t fault_id)
+{
+	RTK_LOGA(TAG, "Hard Fault Patch (KM0)\r\n");
+	if (fault_id == 0) {
+		RTK_LOGA(TAG, "Hard Fault: \r\n");
+	} else {
+		RTK_LOGA(TAG, "Unsupported faults\r\n");
+		while (1);
+	}
+	uint32_t *cstack;
+
+	uint32_t *extra_regs = mstack;
+
+	uint32_t regs[17] = {0x0};
+
+	u8 is_psp = 0;
+
+	enum {
+		REG_EXCR = 0, REG_R4, REG_R5, REG_R6, REG_R7, REG_R8, REG_R9, REG_R10, REG_R11, \
+		REG_R0, REG_R1, REG_R2, REG_R3, REG_R12, REG_LR, REG_EPC, REG_xPSR, REG_END
+	};
+
+	if (lr_value & BIT(3)) {		//Thread Mode
+		if (lr_value & BIT(2)) { 	//PSP
+			is_psp = 1;
+		}
+	}
+	regs[REG_EXCR] = lr_value;
+	/* MSP stack
+	High addr -> |  xxx  | <--- &extra_regs[0] is mstack;
+	  ^          |  R7   | <--- extra_regs[-1]
+	  |	         |  ...  |
+	  |	         |  R4   |
+	  |	         |  R8   |
+	  |	         |  ...  |
+	Low addr  -> |  R11  | <--- extra_regs[-8]*/
+
+	//point to R7, R8 ~ R11 were not saved.
+	extra_regs--;
+	for (int i = REG_R4; i <= REG_R7; i++) {
+		regs[i] = extra_regs[-REG_R7 + i];
+	}
+	for (int i = REG_R8; i <= REG_R11; i++) {
+		regs[i] = extra_regs[-i];
+	}
+	cstack = is_psp ? pstack : mstack;
+
+	for (int i = REG_R0; i < REG_END; i++) {
+		regs[i] = cstack[i - REG_R0];
+	}
+
+	crash_dump((uint32_t *)cstack[REG_EPC], cstack, regs);
+
+	RTK_LOGA(TAG, "MSP     = %p\r\n", mstack);
+	RTK_LOGA(TAG, "PSP     = %p\r\n", pstack);
+	RTK_LOGA(TAG, "CONTROL = 0x%08lX\r\n", __get_CONTROL());
+	RTK_LOGA(TAG, "SVC priority: 	 %lu\r\n", __NVIC_GetPriority(SVCall_IRQn));
+	RTK_LOGA(TAG, "PendSVC priority:  %lu\r\n", __NVIC_GetPriority(PendSV_IRQn));
+	RTK_LOGA(TAG, "Systick priority:  %lu\r\n", __NVIC_GetPriority(SysTick_IRQn));
+	RTK_LOGA(TAG, "\r\n");
+
+	extern void INT_HardFault_C(u32 * stack);
+	INT_HardFault_C(cstack);
+}
+#endif
+
+void Fault_Hanlder_Redirect(crash_on_task crash_on_task_func)
+{
+	crash_task_info = crash_on_task_func;
+#ifdef CONFIG_ARM_CORE_CM4
+	NewVectorTable[3] = (HAL_VECTOR_FUN)HANDLER_HardFault;
+	NewVectorTable[4] = (HAL_VECTOR_FUN)HANDLER_MemFault;
+	NewVectorTable[5] = (HAL_VECTOR_FUN)HANDLER_BusFault;
+	NewVectorTable[6] = (HAL_VECTOR_FUN)HANDLER_UsageFault;
+	NewVectorTable[7] = (HAL_VECTOR_FUN)HANDLER_SecureFault;
+#else
+	NewVectorTable[3] = (HAL_VECTOR_FUN)HANDLER_HardFault;
+#endif
+}
diff --git a/ameba/amebadplus/source/fwlib/ram_common/ameba_gdma_memcpy.c b/ameba/amebadplus/source/fwlib/ram_common/ameba_gdma_memcpy.c
new file mode 100644
index 00000000..9cfe7888
--- /dev/null
+++ b/ameba/amebadplus/source/fwlib/ram_common/ameba_gdma_memcpy.c
@@ -0,0 +1,110 @@
+/*
+ * Copyright (c) 2024 Realtek Semiconductor Corp.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "ameba_soc.h"
+
+struct gdma_memcopy_s {
+	u32 ch_num;
+	volatile u32 dma_done;
+	GDMA_InitTypeDef GDMA_InitStruct;
+};
+
+TIMESENSITIVE_DATA_SECTION
+struct gdma_memcopy_s gdma_memcpy;
+//rtos_sema_t dma_memcpy_sema = NULL;
+
+TIMESENSITIVE_TEXT_SECTION
+static u32 memcpy_gdma_int(void *pData)
+{
+	/* To avoid gcc warnings */
+	UNUSED(pData);
+
+	/* Clear Pending ISR */
+	GDMA_ClearINT(0, gdma_memcpy.ch_num);
+	GDMA_Cmd(0, gdma_memcpy.ch_num, DISABLE);
+
+	gdma_memcpy.dma_done = 1;
+	//rtos_sema_give(dma_memcpy_sema);
+	return TRUE;
+}
+
+TIMESENSITIVE_TEXT_SECTION
+void memcpy_gdma_init(void)
+{
+	gdma_memcpy.dma_done = 1;
+	gdma_memcpy.ch_num = GDMA_ChnlAlloc(0, (IRQ_FUN)memcpy_gdma_int, (u32)NULL, INT_PRI_MIDDLE);
+
+	GDMA_StructInit(&(gdma_memcpy.GDMA_InitStruct));
+	gdma_memcpy.GDMA_InitStruct.GDMA_ChNum = gdma_memcpy.ch_num;
+	gdma_memcpy.GDMA_InitStruct.GDMA_Index = 0;
+	gdma_memcpy.GDMA_InitStruct.GDMA_IsrType = (TransferType | ErrType);
+
+	gdma_memcpy.GDMA_InitStruct.GDMA_SrcMsize = MsizeEight;
+	gdma_memcpy.GDMA_InitStruct.GDMA_DstMsize = MsizeEight;
+
+	//rtos_sema_create_binary(&dma_memcpy_sema);
+}
+
+TIMESENSITIVE_TEXT_SECTION
+static inline u32 memcpy_use_cpu(void *dest, void *src, u32 size)
+{
+	/* To avoid gcc warnings */
+	(void) dest;
+	(void) src;
+
+	if (size < 128) {
+		return TRUE;
+	}
+
+	if (gdma_memcpy.dma_done == 0) {
+		return TRUE;
+	}
+
+	return FALSE;
+}
+
+TIMESENSITIVE_TEXT_SECTION
+int memcpy_gdma(void *dest, void *src, u32 size)
+{
+	u32 size_4byte = size & ~(0x03);
+	u32 left = size & (0x03);
+
+	if (memcpy_use_cpu(dest, src, size) == TRUE) {
+		_memcpy(dest, src, size);
+
+		return 0;
+	}
+	gdma_memcpy.dma_done = 0;
+
+	if (((u32)(src) & 0x03) || ((u32)(dest) & 0x03)) {
+		gdma_memcpy.GDMA_InitStruct.GDMA_SrcDataWidth = TrWidthOneByte;
+		gdma_memcpy.GDMA_InitStruct.GDMA_DstDataWidth = TrWidthOneByte;
+		gdma_memcpy.GDMA_InitStruct.GDMA_BlockSize = size;
+	} else {
+		/* 4-bytes aligned, move 4 bytes each transfer */
+		gdma_memcpy.GDMA_InitStruct.GDMA_SrcDataWidth = TrWidthFourBytes;
+		gdma_memcpy.GDMA_InitStruct.GDMA_DstDataWidth = TrWidthFourBytes;
+		gdma_memcpy.GDMA_InitStruct.GDMA_BlockSize = size_4byte >> 2;
+
+		if (left != 0) {
+			char *dst0 = (char *) dest + size_4byte;
+			char *src0 = (char *) src + size_4byte;
+			while (left--) {
+				*dst0++ = *src0++;
+			}
+		}
+	}
+
+	gdma_memcpy.GDMA_InitStruct.GDMA_SrcAddr = (u32)(src);
+	gdma_memcpy.GDMA_InitStruct.GDMA_DstAddr = (u32)(dest);
+	GDMA_Init(0, gdma_memcpy.ch_num, &(gdma_memcpy.GDMA_InitStruct));
+	GDMA_Cmd(0, gdma_memcpy.ch_num, ENABLE);
+
+	//rtos_sema_take(dma_memcpy_sema, portMAX_DELAY);
+	while (gdma_memcpy.dma_done == 0);
+
+	return 0;
+}
diff --git a/ameba/amebadplus/source/fwlib/ram_common/ameba_gdma_ram.c b/ameba/amebadplus/source/fwlib/ram_common/ameba_gdma_ram.c
index 3b4ce012..8663b208 100644
--- a/ameba/amebadplus/source/fwlib/ram_common/ameba_gdma_ram.c
+++ b/ameba/amebadplus/source/fwlib/ram_common/ameba_gdma_ram.c
@@ -868,15 +868,27 @@ GDMA_Abort(u8 GDMA_Index, u8 GDMA_ChNum)
 	return TRUE;
 }
 
-
-/**
-  * @}
-  */
-
 /**
-  * @}
-  */
+ * @brief Check if the channel is active
+ *
+ * @param GDMA_Index 0
+ * @param GDMA_ChNum 0 ~ 7
+ * @retval TRUE/FALSE
+ */
+__weak
+u8 GDMA_ChannelIsActive(u8 GDMA_Index, u8 GDMA_ChNum)
+{
+	GDMA_TypeDef *GDMA = ((GDMA_TypeDef *) GDMA_BASE);
+	if (TrustZone_IsSecure()) {
+		GDMA = ((GDMA_TypeDef *) GDMA0_REG_BASE_S);
+	}
+	/* Check the parameters */
+	assert_param(IS_GDMA_Index(GDMA_Index));
+	assert_param(IS_GDMA_ChannelNum(GDMA_ChNum));
 
-/**
-  * @}
-  */
+	if ((GDMA->ChEnReg & BIT(GDMA_ChNum)) && \
+		((GDMA->CH[GDMA_ChNum].CFG_LOW & BIT_CFGx_L_INACTIVE) == 0)) {
+		return TRUE;
+	}
+	return FALSE;
+}
diff --git a/ameba/amebadplus/source/fwlib/ram_common/ameba_gpio.c b/ameba/amebadplus/source/fwlib/ram_common/ameba_gpio.c
index 71fc7e89..542e41ac 100644
--- a/ameba/amebadplus/source/fwlib/ram_common/ameba_gpio.c
+++ b/ameba/amebadplus/source/fwlib/ram_common/ameba_gpio.c
@@ -6,6 +6,34 @@
 
 #include "ameba_soc.h"
 
+void GPIO_Init(GPIO_InitTypeDef  *GPIO_InitStruct)
+{
+	/* open gpio function and clock */
+	//RCC_PeriphClockCmd(APBPeriph_GPIO, APBPeriph_GPIO_CLOCK, ENABLE);
+
+	assert_param(GPIO_InitStruct->GPIO_Mode <= GPIO_Mode_INT);
+
+	/* GPIO Pad shouddown control: Turn on the corresponding GPIO Pad and pinmux to GPIO */
+	Pinmux_Config(GPIO_InitStruct->GPIO_Pin, PINMUX_FUNCTION_GPIO);
+
+	if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_INT) {
+		GPIO_Direction(GPIO_InitStruct->GPIO_Pin, GPIO_Mode_IN);
+		PAD_PullCtrl(GPIO_InitStruct->GPIO_Pin, GPIO_InitStruct->GPIO_PuPd);
+
+		GPIO_INTMode(GPIO_InitStruct->GPIO_Pin, ENABLE, GPIO_InitStruct->GPIO_ITTrigger,
+					 GPIO_InitStruct->GPIO_ITPolarity, GPIO_InitStruct->GPIO_ITDebounce);
+	} else {
+		GPIO_INTMode(GPIO_InitStruct->GPIO_Pin, DISABLE, 0, 0, 0);
+
+		if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_OUT) {
+			GPIO_Direction(GPIO_InitStruct->GPIO_Pin, GPIO_Mode_OUT);
+		} else if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IN) {
+			GPIO_Direction(GPIO_InitStruct->GPIO_Pin, GPIO_Mode_IN);
+			PAD_PullCtrl(GPIO_InitStruct->GPIO_Pin, GPIO_InitStruct->GPIO_PuPd);
+		}
+	}
+}
+
 static GPIO_TypeDef *GPIO_PortAddrGet(u32 GPIO_Port)
 {
 	GPIO_TypeDef *GPIO = NULL;
diff --git a/ameba/amebadplus/source/fwlib/ram_common/ameba_ipc_api.c b/ameba/amebadplus/source/fwlib/ram_common/ameba_ipc_api.c
index b130395a..095d7d6c 100644
--- a/ameba/amebadplus/source/fwlib/ram_common/ameba_ipc_api.c
+++ b/ameba/amebadplus/source/fwlib/ram_common/ameba_ipc_api.c
@@ -181,4 +181,4 @@ PIPC_MSG_STRUCT ipc_get_message(u32 IPC_Dir, u8 IPC_ChNum)
 	DCache_Invalidate((u32)&IPC_MSG[msg_idx], sizeof(IPC_MSG_STRUCT));
 
 	return &IPC_MSG[msg_idx];
-}
\ No newline at end of file
+}
diff --git a/ameba/amebadplus/source/fwlib/ram_common/ameba_ipc_ram.c b/ameba/amebadplus/source/fwlib/ram_common/ameba_ipc_ram.c
index ac97e82d..ea89bfd6 100644
--- a/ameba/amebadplus/source/fwlib/ram_common/ameba_ipc_ram.c
+++ b/ameba/amebadplus/source/fwlib/ram_common/ameba_ipc_ram.c
@@ -208,4 +208,4 @@ IPC_TypeDef *IPC_GetDevById(u32 cpu_id)
 
 /**
   * @}
-  */
\ No newline at end of file
+  */
diff --git a/ameba/amebadplus/source/fwlib/ram_common/ameba_ir.c b/ameba/amebadplus/source/fwlib/ram_common/ameba_ir.c
new file mode 100644
index 00000000..056b0268
--- /dev/null
+++ b/ameba/amebadplus/source/fwlib/ram_common/ameba_ir.c
@@ -0,0 +1,483 @@
+/*
+ * Copyright (c) 2024 Realtek Semiconductor Corp.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "ameba_soc.h"
+
+/** @addtogroup Ameba_Periph_Driver
+  * @{
+  */
+
+/** @defgroup IR
+* @brief IR driver modules
+* @{
+*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup IR_Exported_Functions IR Exported Functions
+  * @{
+  */
+
+/**
+  * @brief  Deinitialize the IR peripheral registers to their default values.
+  * @param  None.
+  * @retval None
+  */
+void IR_DeInit(void)
+{
+	//1TODO:
+	// RCC_PeriphClockCmd(APBPeriph_IR, APBPeriph_IR_CLOCK, DISABLE);
+}
+
+
+/**
+  * @brief Initialize the IR peripheral according to the specified
+  *   parameters in the IR_InitStruct
+  * @param  IR_InitStruct: pointer to a IR_InitTypeDef structure that
+  *   contains the configuration information for the specified IR peripheral
+  * @retval None
+  */
+void IR_Init(IR_TypeDef *IRx, IR_InitTypeDef *IR_InitStruct)
+{
+	/* Configure IR clock divider. Formula: IR_CLK = IO_CLK/(1+IR_CLK_DIV) */
+	IRx->IR_CLK_DIV = (IR_InitStruct->IR_Clock) / (IR_InitStruct->IR_Freq) - 1;
+
+	if (IR_InitStruct->IR_Mode == IR_MODE_TX) {
+		/* Check the parameters in TX mode */
+		assert_param(IS_IR_FREQUENCY(IR_InitStruct->IR_Freq));
+
+		/* save IR TX interrupt configuration */
+		IRx->IR_TX_CONFIG &= 0x3F;
+
+		/* Configure TX mode parameters and disable all TX interrupt */
+		IRx->IR_TX_CONFIG |= (IR_TX_DUTY_NUM((IRx->IR_CLK_DIV + 1) / (IR_InitStruct->IR_DutyCycle))) | \
+							 (IR_TX_DATA_TYPE_SET(IR_InitStruct->IR_TxInverse)) | \
+							 (IR_TX_FIFO_LEVEL_TH(IR_InitStruct->IR_TxFIFOThrLevel));
+		if (IR_InitStruct->IR_TxIdleLevel) {
+			IRx->IR_TX_CONFIG |= IR_BIT_TX_IDLE_STATE;
+		} else {
+			IRx->IR_TX_CONFIG &= ~IR_BIT_TX_IDLE_STATE;
+		}
+
+		/* Clear all TX interrupt and TX FIFO */
+		IRx->IR_TX_INT_CLR = IR_TX_INT_ALL_CLR | IR_BIT_TX_FIFO_CLR;
+
+		/* Configure IR tx compensation clock divisor. */
+		IRx->IR_TX_COMPE_DIV = (IR_InitStruct->IR_Clock) / (IR_InitStruct->IR_TxCOMP_CLK) - 1;
+	} else {
+		/* Check the parameters in RX mode */
+		assert_param(IS_IR_RX_TRIGGER_EDGE(IR_InitStruct->IR_RxTriggerMode));
+
+		/* Enable RX mode */
+		IRx->IR_TX_CONFIG |= IR_BIT_MODE_SEL;
+		/* Configure RX mode parameters and disable all RX interrupt */
+		if (IR_InitStruct->IR_RxStartMode)
+			IRx->IR_RX_CONFIG = IR_BIT_RX_START_MODE | \
+								(IR_RX_TRIGGER_MODE(IR_InitStruct->IR_RxTriggerMode)) | \
+								(IR_RX_FILTER_STAGETX(IR_InitStruct->IR_RxFilterTime)) | \
+								(IR_RX_FIFO_LEVEL_TH(IR_InitStruct->IR_RxFIFOThrLevel));
+		else
+			IRx->IR_RX_CONFIG = (IR_RX_TRIGGER_MODE(IR_InitStruct->IR_RxTriggerMode)) | \
+								(IR_RX_FILTER_STAGETX(IR_InitStruct->IR_RxFilterTime)) | \
+								(IR_RX_FIFO_LEVEL_TH(IR_InitStruct->IR_RxFIFOThrLevel));
+
+		if (IR_InitStruct->IR_RxFIFOFullCtrl) {
+			IRx->IR_RX_CONFIG |= IR_BIT_RX_FIFO_DISCARD_SET;
+		} else {
+			IRx->IR_RX_CONFIG &= ~IR_BIT_RX_FIFO_DISCARD_SET;
+		}
+
+		/* Configure IR RX counter threshold parameters */
+		if (IR_InitStruct->IR_RxCntThrType) {
+			IRx->IR_RX_CNT_INT_SEL = IR_BIT_RX_CNT_THR_TRIGGER_LV | IR_RX_CNT_THR(IR_InitStruct->IR_RxCntThr);
+		} else {
+			IRx->IR_RX_CNT_INT_SEL = IR_RX_CNT_THR(IR_InitStruct->IR_RxCntThr);
+		}
+
+		/* Clear all RX interrupt and RX FIFO */
+		IRx->IR_RX_INT_CLR = IR_RX_INT_ALL_CLR | IR_BIT_RX_FIFO_CLR;
+	}
+}
+
+/**
+  * @brief  Fill each IR_InitStruct member with its default value.
+  * @param  IR_InitStruct: pointer to an IR_InitTypeDef structure which will be initialized.
+  * @retval None
+  */
+void IR_StructInit(IR_InitTypeDef *IR_InitStruct)
+{
+	IR_InitStruct->IR_Clock				= 100000000; /*100MHz*/
+	IR_InitStruct->IR_Freq				= 38000;
+	IR_InitStruct->IR_DutyCycle			= 3;
+	IR_InitStruct->IR_Mode				= IR_MODE_TX;
+	IR_InitStruct->IR_TxIdleLevel		= IR_IDLE_OUTPUT_LOW;
+	IR_InitStruct->IR_TxInverse			= IR_TX_DATA_NORMAL_CARRIER_NORMAL;
+	IR_InitStruct->IR_TxFIFOThrLevel	= 0;
+	IR_InitStruct->IR_TxCOMP_CLK		= 1000000; /*1M*/
+	IR_InitStruct->IR_RxStartMode		= IR_RX_AUTO_MODE;
+	IR_InitStruct->IR_RxFIFOThrLevel	= 0;
+	IR_InitStruct->IR_RxFIFOFullCtrl	= IR_RX_FIFO_FULL_DISCARD_NEWEST;
+	IR_InitStruct->IR_RxTriggerMode		= IR_RX_DOUBLE_EDGE;
+	IR_InitStruct->IR_RxFilterTime		= IR_RX_FILTER_TIME_50NS;
+	IR_InitStruct->IR_RxCntThrType		= IR_RX_COUNT_LOW_LEVEL;
+	IR_InitStruct->IR_RxCntThr			= 0x23a; /* This value can be 0 to 0x7fffffff */
+}
+
+/**
+  * @brief   Enable or disable the selected IR mode.
+  * @param  mode: selected IR operation mode.
+  *   This parameter can be the following values:
+  *     @arg IR_MODE_TX: Transmission mode.
+  *     @arg IR_MODE_RX: Receiving mode.
+  * @param  NewState: new state of the operation mode.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void IR_Cmd(IR_TypeDef *IRx, u32 mode, u32 NewState)
+{
+	if (NewState == ENABLE) {
+		if (mode == IR_MODE_TX) {
+			IRx->IR_TX_CONFIG |= IR_BIT_TX_START;
+		} else {
+			IRx->IR_RX_CONFIG |= IR_BIT_RX_START;
+		}
+
+	} else if (NewState == DISABLE) {
+		if (mode == IR_MODE_TX) {
+			IRx->IR_TX_CONFIG &= ~IR_BIT_TX_START;
+		} else {
+			IRx->IR_RX_CONFIG &= ~IR_BIT_RX_START;
+		}
+
+	}
+}
+
+/**
+  * @brief   Configure counter threshold value in receiving mode.You can use it to stop receiving IR data.
+  * @param  IR_RxCntThrType:
+  *   This parameter can be the following values:
+  *     @arg IR_RX_Count_Low_Level: Low level counter value >= IR_RxCntThr, trigger IR_INT_RX_CNT_THR interrupt.
+  *     @arg IR_RX_Count_High_Level: High level counter value >= IR_RxCntThr, trigger IR_INT_RX_CNT_THR interrupt.
+  * @param  IR_RxCntThr: Configure IR Rx counter threshold value which can be 0 to 0x7fffffffUL.
+  * @retval None
+  */
+void IR_SetRxCounterThreshold(IR_TypeDef *IRx, u32 IR_RxCntThrType, u32 IR_RxCntThr)
+{
+	/* Configure IR RX counter threshold parameters */
+	IRx->IR_RX_CNT_INT_SEL = (IR_RxCntThrType) | IR_RX_CNT_THR(IR_RxCntThr);
+}
+
+/**
+  * @brief  Send data.
+  * @param  buf: data buffer to send.
+  * @param  length: buffer length.
+  * @param IsLastPacket:
+  *   This parameter can be the following values:
+  *     @arg ENABLE: The last data in IR packet and there is no continous data.In other words, An infrared data transmission is completed.
+  *     @arg DISABLE: There is data to be transmitted continuously.
+  * @retval None
+  */
+void IR_SendBuf(IR_TypeDef *IRx, u32 *pBuf, u32 len, u32 IsLastPacket)
+{
+	if (len == 0) {
+		return;
+	}
+
+	while (--len) {
+		IRx->IR_TX_FIFO = *pBuf++;
+	}
+
+	/* If send the last IR packet, SET the following bit */
+	if (IsLastPacket == TRUE) {
+		IRx->IR_TX_FIFO =  *pBuf | IR_BIT_TX_DATA_END_FLAG;
+	} else {
+		IRx->IR_TX_FIFO =  *pBuf;
+	}
+
+}
+
+/**
+  * @brief  Read data From RX FIFO.
+  * @param  buf: buffer address to receive data.
+  * @param  length: read data length.
+  * @retval None
+  */
+void IR_ReceiveBuf(IR_TypeDef *IRx, u32 *pBuf, u32 len)
+{
+	while (len--) {
+		*pBuf++ = IRx->IR_RX_FIFO;
+	}
+
+}
+
+/**
+  * @brief  Enables or disables the specified IR interrupts.
+  * @param  IR_INT: specifies the IR interrupts sources to be enabled or disabled.
+  *   This parameter can be the following values:
+  *     @arg IR_TX_FIFO_EMPTY_INT_EN: TX FIFO empty interrupt.
+  *     @arg IR_TX_FIFO_LEVEL_INT_EN: TX FIFO threshold interrupt.
+  *     @arg IR_TX_FIFO_OVER_INT_EN: TX FIFO overflow interrupt.
+  *     @arg IR_RX_FIFO_FULL_INT_EN: RX FIFO  full interrupt.
+  *     @arg IR_RX_FIFO_LEVEL_INT_EN: RX FIFO threshold interrupt.
+  *     @arg IR_RX_CNT_OF_INT_EN: RX counter overflow interrupt.
+  *     @arg IR_RX_FIFO_OF_INT_EN: RX FIFO overflow interrupt.
+  *     @arg IR_RX_CNT_THR_INT_EN: RX counter threshold interrupt.
+  *     @arg IR_RX_FIFO_ERROR_INT_EN: RX FIFO error read interrupt. Trigger when RX FIFO empty and read RX FIFO.
+  * @param  NewState: new state of the specified IR interrupts.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void IR_INTConfig(IR_TypeDef *IRx, u32 IR_INT, u32 newState)
+{
+	if (IR_MODE(IRx->IR_TX_CONFIG)) {
+		assert_param(IS_RX_INT(IR_INT));
+
+		if (newState == ENABLE) {
+			IRx->IR_RX_CONFIG |= IR_INT;
+		} else {
+			IRx->IR_RX_CONFIG &= ~IR_INT;
+		}
+	} else {
+		assert_param(IS_TX_INT(IR_INT));
+
+		if (newState == ENABLE) {
+			IRx->IR_TX_CONFIG |= IR_INT;
+		} else {
+			IRx->IR_TX_CONFIG &= ~IR_INT;
+		}
+	}
+}
+
+/**
+  * @brief  Mask or unmask the specified IR interrupts.
+  * @param  IR_INT: specifies the IR interrupts sources to be mask or unmask.
+  *   This parameter can be the following values:
+  *     @arg IR_TX_FIFO_EMPTY_INT_MASK: TX FIFO empty interrupt mask.
+  *     @arg IR_TX_FIFO_LEVEL_INT_MASK: TX FIFO threshold interrupt mask.
+  *     @arg IR_TX_FIFO_OVER_INT_MASK: TX FIFO overflow interrupt mask.
+  *     @arg IR_RX_FIFO_FULL_INT_Msk: RX FIFO  full interrupt mask.
+  *     @arg IR_RX_FIFO_LEVEL_INT_Msk: RX FIFO threshold interrupt mask.
+  *     @arg IR_RX_CNT_OF_INT_Msk: RX counter overflow interrupt mask.
+  *     @arg IR_RX_FIFO_OF_INT_Msk: RX FIFO overflow interrupt mask.
+  *     @arg IR_RX_CNT_THR_INT_Msk: RX counter threshold interrupt mask.
+  *     @arg IR_RX_FIFO_ERROR_INT_Msk: RX FIFO error read interrupt mask. Trigger when RX FIFO empty and read RX FIFO.
+  * @param  NewState: new state of the specified IR interrupts.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void IR_MaskINTConfig(IR_TypeDef *IRx, u32 IR_INT, u32 newState)
+{
+	if (IR_MODE(IRx->IR_TX_CONFIG)) {
+		assert_param(IS_RX_INT_MASK(IR_INT));
+
+		if (newState == ENABLE) {
+			IRx->IR_RX_CONFIG |= IR_INT;
+		} else {
+			IRx->IR_RX_CONFIG &= ~IR_INT;
+		}
+
+	} else {
+		assert_param(IS_TX_INT_MASK(IR_INT));
+
+		if (newState == ENABLE) {
+			IRx->IR_TX_CONFIG |= IR_INT;
+		} else {
+			IRx->IR_TX_CONFIG &= ~IR_INT;
+		}
+	}
+}
+
+/**
+  * @brief Get the specified IR interrupt status.
+  * @retval The new state of IR_INT (SET or RESET).
+  */
+u32 IR_GetINTStatus(IR_TypeDef *IRx)
+{
+	u32 status;
+
+	if (IR_MODE(IRx->IR_TX_CONFIG)) {
+		status = (IRx->IR_RX_SR);
+	} else {
+		status = (IRx->IR_TX_SR);
+	}
+
+	/* Return the IR_INT status */
+	return status;
+}
+
+/**
+  * @brief Get the specified IR interrupt mask status.
+  * @retval The new mask state of IR_INT (SET or RESET).
+  */
+u32 IR_GetIMR(IR_TypeDef *IRx)
+{
+	u32 mask;
+
+	if (IR_MODE(IRx->IR_TX_CONFIG)) {
+		mask = IRx->IR_RX_CONFIG  & IR_RX_INT_ALL_MASK;
+	} else {
+		mask = IRx->IR_TX_CONFIG  & IR_TX_INT_ALL_MASK;
+	}
+
+	/* Return the IR_INT mask status */
+	return  mask;
+}
+
+/**
+  * @brief Get the specified IR FSM status.
+  * @retval The new state of FSM (IDLE or RUN).
+  * @TRUE:RUN, FALSE:IDLE.
+  */
+u32 IR_FSMRunning(IR_TypeDef *IRx)
+{
+	u32 status = FALSE;
+
+	if (IR_MODE(IRx->IR_TX_CONFIG)) {
+		if ((IRx->IR_RX_SR) & IR_BIT_RX_STATE) {
+			status = TRUE;
+		}
+	} else {
+		if ((IRx->IR_TX_SR) & IR_BIT_TX_STATUS) {
+			status = TRUE;
+		}
+	}
+
+	return  status;
+}
+
+/**
+  * @brief  Clear the IR interrupt pending bits.
+  * @param  IR_IT: specifies the interrupt pending bit to clear.
+  *   This parameter can be any combination of the following values:
+  *     @arg IR_TX_FIFO_EMPTY_INT_CLR: Clear TX FIFO empty interrupt.
+  *     @arg IR_TX_FIFO_LEVEL_INT_CLR: Clear TX FIFO threshold interrupt.
+  *     @arg IR_TX_FIFO_OVER_INT_CLR: Clear TX FIFO overflow interrupt.
+  *     @arg IR_RX_FIFO_FULL_INT_CLR: Clear RX FIFO  full interrupt.
+  *     @arg IR_RX_FIFO_LEVEL_INT_CLR: Clear RX FIFO threshold interrupt.
+  *     @arg IR_RX_CNT_OF_INT_CLR: Clear RX counter overflow interrupt.
+  *     @arg IR_RX_FIFO_OF_INT_CLR: Clear RX FIFO overflow interrupt.
+  *     @arg IR_RX_CNT_THR_INT_CLR: Clear RX counter threshold interrupt.
+  *     @arg IR_RX_FIFO_ERROR_INT_CLR: Clear RX FIFO error read interrupt. Trigger when RX FIFO empty and read RX FIFO.
+  * @retval None
+  */
+void IR_ClearINTPendingBit(IR_TypeDef *IRx, u32 IR_CLEAR_INT)
+{
+	if (IR_MODE(IRx->IR_TX_CONFIG)) {
+		assert_param(IS_RX_INT_CLR(IR_CLEAR_INT));
+		IRx->IR_RX_INT_CLR |= IR_CLEAR_INT;
+	} else {
+		assert_param(IS_TX_INT_CLR(IR_CLEAR_INT));
+		IRx->IR_TX_INT_CLR |= IR_CLEAR_INT;
+	}
+}
+
+
+/**
+  * @brief  Set tx threshold.when TX FIFO depth <= threshold value, trigger  interrupt
+  * @param  thd: tx threshold.
+  * @retval None
+  */
+void IR_SetTxThreshold(IR_TypeDef *IRx, uint8_t thd)
+{
+	u32 Tx_config;
+
+	Tx_config = IRx->IR_TX_CONFIG;
+	Tx_config &= ~IR_MASK_TX_FIFO_LEVEL_TH;
+	Tx_config |= IR_TX_FIFO_LEVEL_TH(thd);
+	IRx->IR_TX_CONFIG = Tx_config;
+}
+
+
+/**
+  * @brief  Set rx threshold.when RX FIFO depth > threshold value, trigger  interrupt
+  * @param  thd: rx threshold.
+  * @retval None
+  */
+void IR_SetRxThreshold(IR_TypeDef *IRx, uint8_t thd)
+{
+	u32 Rx_config;
+
+	Rx_config = IRx->IR_RX_CONFIG;
+	Rx_config &= ~IR_MASK_RX_FIFO_LEVEL_TH;
+	Rx_config |= IR_RX_FIFO_LEVEL_TH(thd);
+	IRx->IR_RX_CONFIG = Rx_config;
+}
+
+
+/**
+  * @brief  Get free size of TX FIFO .
+  * @param  None
+  * @retval the free size of TX FIFO
+  */
+u32 IR_GetTxFIFOFreeLen(IR_TypeDef *IRx)
+{
+	return (IR_TX_FIFO_SIZE - IR_GET_TX_FIFO_OFFSET(IRx->IR_TX_SR));   //IR_TX_FIFO_SIZE - TX FIFO offset
+}
+
+
+/**
+  * @brief  Get data size in RX FIFO.
+  * @param  None
+  * @retval current data size in RX FIFO.
+  */
+u32 IR_GetRxDataLen(IR_TypeDef *IRx)
+{
+	return (IR_GET_RX_FIFO_OFFSET(IRx->IR_RX_SR));
+}
+
+
+/**
+  * @brief  Send one data.
+  * @param  data: send data.
+  * @retval None
+  */
+void IR_SendData(IR_TypeDef *IRx, u32 data)
+{
+	IRx->IR_TX_FIFO = data;
+}
+
+
+/**
+  * @brief   Start trigger only in manual receive mode.
+  * @param  None.
+  * @retval None
+  */
+void IR_StartManualRxTrigger(IR_TypeDef *IRx)
+{
+	/* Start Rx manual mode */
+	IRx->IR_RX_CONFIG |= IR_BIT_RX_MAN_START;
+}
+
+
+/**
+  * @brief Read one data.
+  * @param none
+  * @retval data which read from RX FIFO.
+  */
+u32 IR_ReceiveData(IR_TypeDef *IRx)
+{
+	return IRx->IR_RX_FIFO;
+}
+
+/**
+  * @brief  Clear IR TX FIFO.
+  * @param  none
+  * @retval None
+  */
+void IR_ClearTxFIFO(IR_TypeDef *IRx)
+{
+	IRx->IR_TX_INT_CLR = IR_BIT_TX_FIFO_CLR;
+}
+
+
+/**
+  * @brief  Clear IR RX FIFO.
+  * @param  none
+  * @retval None
+  */
+void IR_ClearRxFIFO(IR_TypeDef *IRx)
+{
+	IRx->IR_RX_INT_CLR = IR_BIT_RX_FIFO_CLR;
+}
diff --git a/ameba/amebadplus/source/fwlib/ram_common/ameba_keyscan.c b/ameba/amebadplus/source/fwlib/ram_common/ameba_keyscan.c
new file mode 100644
index 00000000..cf27a2c3
--- /dev/null
+++ b/ameba/amebadplus/source/fwlib/ram_common/ameba_keyscan.c
@@ -0,0 +1,409 @@
+/*
+ * Copyright (c) 2024 Realtek Semiconductor Corp.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "ameba_soc.h"
+
+/** @addtogroup Ameba_Periph_Driver
+  * @{
+  */
+
+/** @defgroup KSCAN
+* @brief KSCAN driver modules
+* @{
+*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup KSCAN_Exported_Functions KSCAN Exported Functions
+  * @{
+  */
+
+/**
+  * @brief  Fills each KeyScan_InitStruct member with its default value.
+  * @param  KeyScan_InitStruct: pointer to an KeyScan_InitTypeDef structure which will be initialized.
+  * @retval None
+  */
+void KeyScan_StructInit(KeyScan_InitTypeDef *KeyScan_InitStruct)
+{
+	/* Load HAL initial data structure default value */
+	KeyScan_InitStruct->KS_ClkDiv = 199;
+	KeyScan_InitStruct->KS_ColSel = 0x03;
+	KeyScan_InitStruct->KS_RowSel = 0x03;
+
+	KeyScan_InitStruct->KS_WorkMode = KS_REGULAR_SCAN_MODE;
+
+	KeyScan_InitStruct->KS_DebounceCnt = 0x3e7;
+	KeyScan_InitStruct->KS_IntervalCnt = 0x7cf;
+	KeyScan_InitStruct->KS_ReleaseCnt = 0x3e7;
+
+	KeyScan_InitStruct->KS_ThreholdLevel = 8;
+	KeyScan_InitStruct->KS_LimitLevel = 2;
+	KeyScan_InitStruct->KS_OverCtrl = KS_FIFO_OVER_CTRL_DIS_NEW;
+}
+
+/**
+  * @brief  Initializes the KeyScan peripheral according to the specified
+  *			parameters in the KeyScan_InitStruct.
+  * @param  KeyScan: selected KeyScan peripheral.
+  * @param  KeyScan_InitStruct: pointer to a KeyScan_InitTypeDef structure that contains
+  * 		the configuration information for the specified KeyScan peripheral.
+  * @retval None
+  */
+void KeyScan_Init(KSCAN_TypeDef *KeyScan, KeyScan_InitTypeDef *KeyScan_InitStruct)
+{
+	/* Check the parameters */
+	assert_param(IS_KEYSCAN_ALL_PERIPH(KeyScan));
+	assert_param(KeyScan_InitStruct->KS_ClkDiv <= 0xfff);
+	assert_param((KeyScan_InitStruct->KS_ColSel >= 0x1) && (KeyScan_InitStruct->KS_ColSel <= 0xff));
+	assert_param((KeyScan_InitStruct->KS_RowSel >= 0x1) && (KeyScan_InitStruct->KS_RowSel <= 0xff));
+	assert_param(KeyScan_InitStruct->KS_DebounceCnt <= 0xfff);
+	assert_param(KeyScan_InitStruct->KS_IntervalCnt <= 0xfff);
+	assert_param(KeyScan_InitStruct->KS_ReleaseCnt <= 0xfff);
+	assert_param(IS_KS_WORK_MODE(KeyScan_InitStruct->KS_WorkMode));
+	assert_param(IS_KS_FIFO_OVER_CTRL(KeyScan_InitStruct->KS_OverCtrl));
+	assert_param(IS_KS_FIFO_LIMIT_LEVEL(KeyScan_InitStruct->KS_LimitLevel));
+	assert_param(IS_KS_FIFO_TH_LEVEL(KeyScan_InitStruct->KS_ThreholdLevel));
+
+	/* Disable the IC first */
+	KeyScan->KS_CTRL &= (~KS_BIT_RUN_ENABLE);
+
+	/* Mask all keyscan interrupt */
+	KeyScan->KS_IMR &= (~KS_BIT_ALL_INT_MSK);
+
+	/* clock divider config */
+	KeyScan->KS_CLK_DIV &= (~KS_MASK_CLK_DIV);
+	KeyScan->KS_CLK_DIV |= KS_CLK_DIV(KeyScan_InitStruct->KS_ClkDiv);
+
+	/* Config scan mode*/
+	KeyScan->KS_CTRL &= (~KS_BIT_WORK_MODE);
+	if (KeyScan_InitStruct->KS_WorkMode) {
+		KeyScan->KS_CTRL |= KS_BIT_WORK_MODE;
+	}
+
+	KeyScan->KS_FIFO_CFG = KS_FIFO_TH_LEVEL(KeyScan_InitStruct->KS_ThreholdLevel) | \
+						   KS_FIFO_LIMIT_LEVEL(KeyScan_InitStruct->KS_LimitLevel);
+	if (KeyScan_InitStruct->KS_OverCtrl) {
+		KeyScan->KS_FIFO_CFG |= KS_BIT_FIFO_OV_CTRL;
+	}
+
+	/* time count config */
+	KeyScan->KS_TIM_CFG0 &= (~KS_MASK_DEB_TIMER);
+	KeyScan->KS_TIM_CFG0 |= KS_DEB_TIMER(KeyScan_InitStruct->KS_DebounceCnt);
+	KeyScan->KS_TIM_CFG1 = KS_INTERVAL_TIMER(KeyScan_InitStruct->KS_IntervalCnt) | \
+						   KS_RELEASE_TIMER(KeyScan_InitStruct->KS_ReleaseCnt);
+
+	/* Set col map, config which col to work */
+	KeyScan->KS_COL_CFG = KS_COL_SEL(KeyScan_InitStruct->KS_ColSel);
+
+	/* Set row map, config which row to work */
+	KeyScan->KS_ROW_CFG = KS_ROW_SEL(KeyScan_InitStruct->KS_RowSel);
+
+	/* clear all interrupt status and status flag */
+	KeyScan->KS_ICR |= KS_BIT_ALL_INT_CLR;
+
+	return;
+}
+
+/**
+  * @brief  Enables or disables the specified KeyScan interrupts mask.
+  * @param  KeyScan: selected KeyScan peripheral.
+  * @param  KeyScan_IT: specifies the KeyScan interrupt sources to be enabled or masked.
+  *          This parameter can be one or combinations of the following values:
+  *            @arg KS_BIT_ALL_DEFAULT_INT_MASK: Unmask all default interrupt
+  *            @arg KS_BIT_FALSE_ALARM_INT_MASK: Unmask false alarm interrupt
+  *            @arg KS_BIT_STUCK_EVENT_INT_MASK: Unmask Stuck event interrupt
+  *            @arg KS_BIT_SCAN_EVENT_INT_MASK: Unmask Scan event interrupt
+  *            @arg KS_BIT_FIFO_LIMIT_INT_MASK: Unmask FIFO limit interrupt
+  *            @arg KS_BIT_FIFO_OV_INT_MASK: Unmask FIFO overflow interrupt
+  *            @arg KS_BIT_FIFO_FULL_INT_MASK: Unmask FIFO full interrupt
+  *            @arg KS_BIT_SCAN_FINISH_INT_MASK: Unmask scan finish interrupt
+  *            @arg KS_BIT_FIFO_NOTEMPTY_INT_MASK: Unmask FIFO nonempty interrupt
+  *            @arg KS_BIT_ALL_RELEASE_INT_MASK: Unmask All Release interrupt
+  * @param  NewState: new state of the specified KeyScan interrupts mask.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void KeyScan_INTConfig(KSCAN_TypeDef *KeyScan, u32 KeyScan_IT, u8 newState)
+{
+	/* Check the parameters */
+	assert_param(IS_KEYSCAN_ALL_PERIPH(KeyScan));
+
+	if (newState == ENABLE) {
+		/* Enable KeyScan interrupts */
+		KeyScan->KS_IMR |= KeyScan_IT;
+	} else {
+		/* Disable KeyScan interrupts */
+		KeyScan->KS_IMR &= (~KeyScan_IT);
+	}
+}
+
+/**
+  * @brief  Clears the specified KeyScan interrupt pending bit.
+  * @param  KeyScan: selected KeyScan peripheral.
+  * @param  KeyScan_IT: specifies the KeyScan interrupt to be cleared.
+  *          This parameter can be one or combinations of the following values:
+  *            @arg KS_BIT_ALL_DEFAULT_INT_CLR: all default flag
+  *            @arg KS_BIT_FALSE_ALARM_INT_CLR: false alarm flag
+  *            @arg KS_BIT_STUCK_INT_CLR: Stuck event interrupt flag
+  *            @arg KS_BIT_FIFO_LIMIT_INT_CLR: FIFO limit interrupt flag
+  *            @arg KS_BIT_FIFO_OV_INT_CLR: FIFO overflow interrupt flag
+  *            @arg KS_BIT_SCAN_FINISH_INT_CLR: Scan finish interrupt flag
+  *            @arg KS_BIT_ALL_RELEASE_INT_CLR: All Release interrupt flag
+  * @note   KS_BIT_SCAN_EVENT_INT_STATUS is automatically cleared by hardware when the data is read.
+  *             KS_BIT_FIFO_FULL_INT_STATUS is automatically cleared by hardware when the buffer level
+  *        goes below the KS_FIFO_TH_LEVEL threshold.
+  *             KS_BIT_FIFO_NOTEMPTY_INT_STATUS is automatically cleared by hardware when the FIFO is empty.
+  * @retval None
+  */
+void KeyScan_ClearINT(KSCAN_TypeDef *KeyScan, u32 KeyScan_IT)
+{
+	/* Check the parameters */
+	assert_param(IS_KEYSCAN_ALL_PERIPH(KeyScan));
+
+	KeyScan->KS_ICR |= KeyScan_IT;
+}
+
+/**
+  * @brief  Get KeyScan Raw Interrupt Status.
+  * @param  KeyScan: selected KeyScan peripheral.
+  * @retval raw interrupt status
+  */
+u32 KeyScan_GetRawINT(KSCAN_TypeDef *KeyScan)
+{
+	/* Check the parameters */
+	assert_param(IS_KEYSCAN_ALL_PERIPH(KeyScan));
+
+	return KeyScan->KS_ISR_RAW;
+}
+
+/**
+  * @brief  Get KeyScan interrupt status.
+  * @param  KeyScan: selected KeyScan peripheral.
+  * @retval interrupt status
+  */
+u32 KeyScan_GetINT(KSCAN_TypeDef *KeyScan)
+{
+	/* Check the parameters */
+	assert_param(IS_KEYSCAN_ALL_PERIPH(KeyScan));
+
+	return KeyScan->KS_ISR;
+}
+
+/**
+  * @brief  Get data number of keyscan FIFO.
+  * @param  KeyScan: selected KeyScan peripheral.
+  * @retval data number of keyscan FIFO
+  */
+u8 KeyScan_GetDataNum(KSCAN_TypeDef *KeyScan)
+{
+	/* Check the parameters */
+	assert_param(IS_KEYSCAN_ALL_PERIPH(KeyScan));
+
+	return KS_GET_FIFO_DATA_LEVEL(KeyScan->KS_DATA_NUM);
+}
+
+/**
+  * @brief  Clears the FIFO data.
+  * @param  KeyScan: selected KeyScan peripheral.
+  * @retval None
+  */
+void KeyScan_ClearFIFOData(KSCAN_TypeDef *KeyScan)
+{
+	/* Check the parameters */
+	assert_param(IS_KEYSCAN_ALL_PERIPH(KeyScan));
+
+	KeyScan->KS_FIFO_CFG |= KS_BIT_FIFO_CLR;
+}
+
+/**
+  * @brief  Get status of keyscan FIFO.
+  * @param  KeyScan: selected KeyScan peripheral.
+  * @param  KeyScan_Flag: specifies the flag to check.
+  *   This parameter can be one of the following values:
+  *     @arg KS_BIT_FIFO_FULL
+  *     @arg KS_BIT_FIFO_EMPTY
+  * @retval the new statue of the specified flag.
+  *   This parameter can be: TRUE or FALSE.
+  */
+bool KeyScan_GetFIFOState(KSCAN_TypeDef *KeyScan, u32 KeyScan_Flag)
+{
+	/* Check the parameters */
+	assert_param(IS_KEYSCAN_ALL_PERIPH(KeyScan));
+
+	if ((KeyScan->KS_DATA_NUM & KeyScan_Flag) != 0) {
+		return TRUE;
+	} else {
+		return FALSE;
+	}
+}
+
+/**
+  * @brief  Read data from keyscan FIFO.
+  * @param  KeyScan: selected KeyScan peripheral.
+  * @param  *outBuf: buffer to save data read from KeyScan FIFO.
+  * @param  count: number of data to be read.
+  * @retval None
+  */
+void KeyScan_Read(KSCAN_TypeDef *KeyScan, u32 *outBuf, u8 count)
+{
+	u32 TempVal;
+
+	/* Check the parameters */
+	assert_param(IS_KEYSCAN_ALL_PERIPH(KeyScan));
+
+	for (TempVal = 0; TempVal < count; TempVal++) {
+		*outBuf++ = KS_GET_DATA(KeyScan->KS_DATA);
+	}
+}
+
+/**
+  * @brief  Enables or disables the specified KeyScan peripheral.
+  * @param  KeyScan: selected KeyScan peripheral.
+  * @param  NewState: new state of the KeyScan peripheral.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void KeyScan_Cmd(KSCAN_TypeDef *KeyScan, u8 NewState)
+{
+	/* Check the parameters */
+	assert_param(IS_KEYSCAN_ALL_PERIPH(KeyScan));
+
+	if (NewState != DISABLE) {
+		/* Enable the KeyScan peripheral */
+		KeyScan->KS_CTRL |= KS_BIT_RUN_ENABLE;
+	} else {
+		/* Disable the KeyScan peripheral */
+		KeyScan->KS_CTRL &= (~KS_BIT_RUN_ENABLE);
+	}
+}
+
+/**
+  * @brief  Set Keyscan Column and Row that used.
+  * @param  column_sel: Specifies which column(s) is used.
+  *   This parameter must be set to a value in the 0x1-0xff range.
+  * @param  row_sel: Specifies which row(s) is used.
+  *   This parameter must be set to a value in the 0x1-0xff range.
+  * @retval None
+  */
+void KeyScan_SetColRow(KSCAN_TypeDef *KeyScan, u32 column_sel, u32 row_sel)
+{
+	assert_param((column_sel >= 0x1) && (column_sel <= 0xff));
+	assert_param((row_sel >= 0x1) && (row_sel <= 0xff));
+
+	/* Set col map, config which col to work */
+	KeyScan->KS_COL_CFG = KS_COL_SEL(column_sel);
+
+	/* Set row map, config which row to work */
+	KeyScan->KS_ROW_CFG = KS_ROW_SEL(row_sel);
+}
+
+/**
+  * @brief  Enables or disables KeyScan stuck auto check function.
+  * @param  KeyScan: selected KeyScan peripheral.
+  * @param  NewState: new state of the KeyScan stuck auto check function.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void KeyScan_StuckAutoCmd(KSCAN_TypeDef *KeyScan, u8 NewState)
+{
+	/* Check the parameters */
+	assert_param(IS_KEYSCAN_ALL_PERIPH(KeyScan));
+
+	if (NewState != DISABLE) {
+		/* Enable the KeyScan stuck auto check function */
+		KeyScan->KS_STUCK_CFG0 |= KS_BIT_AUTO_CHECK_STUCK_ENABLE;
+	} else {
+		/* Disable the KeyScan stuck auto check function */
+		KeyScan->KS_STUCK_CFG0 &= (~KS_BIT_AUTO_CHECK_STUCK_ENABLE);
+	}
+}
+
+/**
+  * @brief  Set stuck time threshold.
+  * @param  KeyScan: selected KeyScan peripheral.
+  * @param  ThresholdMs: stuck time threshold convert to ms.
+  *   ThresholdMs = (Threshold +1)* Scan_clk(ms).
+  *   Threshold must be set to a value in the 0x0-0x7fffffff range.
+  * @retval None
+  */
+void KeyScan_SetStuckThreshold(KSCAN_TypeDef *KeyScan, u32 ThresholdMs)
+{
+	/* Check the parameters */
+	assert_param(IS_KEYSCAN_ALL_PERIPH(KeyScan));
+
+	u32 Threshold = (ThresholdMs * 40 * 1000) / (KS_CLK_DIV(KeyScan->KS_CLK_DIV) + 1) - 1;
+	assert_param(Threshold <= 0x7fffffff);
+
+	KeyScan->KS_STUCK_CFG0 &= (~KS_MASK_STUCK_TIME_THRESHOLD);
+	KeyScan->KS_STUCK_CFG0 |= KS_STUCK_TIME_THRESHOLD(Threshold);
+}
+
+
+/**
+  * @brief  Set stuckrow detect periodical no pull time.
+  * @param  KeyScan: selected KeyScan peripheral.
+  * @param  PullUpUs: stuckrow detect pullup time convert to us.
+  *   PullUpUs = (PullUpCnt +1)* clk_131k(us), max value is 15625us.
+  *   PullUpCnt must be set to a value in the 0x0-0x7ff range.
+  * @param  NoPullUs: stuckrow detect no pull time convert to us.
+  *   When NoPullUs is 0, disable stuckrow detect function.
+  *   When NoPullUs is not 0, NoPullUs = (NoPullCnt +1)* clk_131k(us), max value is 31259us.
+  *   NoPullUs can be set to a value in the 0x0-0xfff range.
+  * @retval None
+  */
+void KeyScan_StuckPeriodicalPull(KSCAN_TypeDef *KeyScan, u32 PullUpUs, u32 NoPullUs)
+{
+	/* Check the parameters */
+	assert_param(IS_KEYSCAN_ALL_PERIPH(KeyScan));
+
+	u32 PullUpCnt = PullUpUs * 131 / 1000 - 1;
+	u32 NoPullCnt = NoPullUs * 131 / 1000 - 1;
+	assert_param(PullUpCnt <= 0x7ff);
+	assert_param(NoPullCnt <= 0xfff);
+
+	if (NoPullUs != 0) {
+		/* Enable the KeyScan stuckrow detect function */
+		KeyScan->KS_STUCK_CFG2 |= KS_BIT_STUCKROW_DETECT_ENABLE;
+
+		KeyScan->KS_STUCK_CFG2 &= ~(KS_MASK_STUCKROW_DETECT_TIME | KS_MASK_STUCKROW_DETECT_TIME_INTERVAL);
+		KeyScan->KS_STUCK_CFG2 |= (KS_STUCKROW_DETECT_TIME(PullUpCnt) | KS_STUCKROW_DETECT_TIME_INTERVAL(NoPullCnt));
+	} else {
+		/* Disable the KeyScan stuckrow detect function */
+		KeyScan->KS_STUCK_CFG2 &= (~KS_BIT_STUCKROW_DETECT_ENABLE);
+	}
+}
+
+/**
+  * @brief  Get stuckrow default status.
+  * @param  KeyScan: selected KeyScan peripheral.
+  * @retval row0 ~ row7 default status.
+  *   one bit one row, bit 0 means row0, bit 7 means row7.
+  *   1: row stucked
+  *   0: row unstucked
+  */
+u32 KeyScan_GetStuckRow(KSCAN_TypeDef *KeyScan)
+{
+	/* Check the parameters */
+	assert_param(IS_KEYSCAN_ALL_PERIPH(KeyScan));
+
+	return KS_ROW_STATUS(KeyScan->KS_STUCK_KEY_ROW_STATUS1);
+}
+
+/**
+  * @brief  Set stuckrow default status.
+  * @param  KeyScan: selected KeyScan peripheral.
+  * @param  Status: row default status.
+  *   one bit one row, bit 0 means row0, bit 7 means row7.
+  *   1: row stucked
+  *   0: row unstucked
+  * @retval None
+  */
+void KeyScan_SetStuckRow(KSCAN_TypeDef *KeyScan, u32 Status)
+{
+	/* Check the parameters */
+	assert_param(IS_KEYSCAN_ALL_PERIPH(KeyScan));
+
+	KeyScan->KS_STUCK_CFG1 = KS_ROW_DEFAULT_STATUS(~Status);
+}
diff --git a/ameba/amebadplus/source/fwlib/ram_common/ameba_ldo.c b/ameba/amebadplus/source/fwlib/ram_common/ameba_ldo.c
new file mode 100644
index 00000000..96b37533
--- /dev/null
+++ b/ameba/amebadplus/source/fwlib/ram_common/ameba_ldo.c
@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2024 Realtek Semiconductor Corp.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "ameba_soc.h"
+static const char *const TAG = "BOOT";
+
+/**
+  * @brief  Set Core voltage Type.
+  * @param  Source: This parameter can be one of the following values:
+  *		 @arg CORE_VOL_0P9
+  *		 @arg CORE_VOL_1P0
+  */
+void CORE_LDO_Vol_Set(u8 vol_type)
+{
+	u32 Temp;
+
+	Temp = HAL_READ32(OTPC_REG_BASE, SEC_OTP_HWCFG);
+	if (vol_type == CORE_VOL_1P0) { /*Core LDO 1.0V & SWR 1.35V */
+		if ((Temp & SEC_BIT_BOOT_VOL_SEL) == 0) {
+			/* if OTP not set, trigger to 1.0V manually */
+			Temp |= SEC_BIT_BOOT_VOL_SEL;
+			HAL_WRITE32(OTPC_REG_BASE, SEC_OTP_HWCFG, Temp);
+			Temp = HAL_READ32(PMC_BASE, AIP_TRIGGER);
+			Temp |= PMC_BIT_TRG_SYS_REGU_STS;
+			HAL_WRITE32(PMC_BASE, AIP_TRIGGER, Temp);
+		}
+	} else if ((vol_type == CORE_VOL_0P9) && ((Temp & SEC_BIT_BOOT_VOL_SEL) != 0)) {
+		RTK_LOGE(TAG, "OTP BOOT VOL choose 1.0V but usrcfg choose 0.9V!\n");
+	}
+}
+
+/**
+  * @brief  Set LDO_Mem with different dummyload.
+  * @param  dummy_load: LDO_MEM_DUMMY_200UA/LDO_MEM_DUMMY_500UA/LDO_MEM_DUMMY_700UA
+  */
+void LDO_Mem_Dummy_Ctrl(u32 dummy_load)
+{
+	LDO_TypeDef *LDO = LDO_BASE;
+
+	LDO->LDO_3318 &= ~LDO_MASK_DMY_LOAD;
+	LDO->LDO_3318 |= LDO_DMY_LOAD(dummy_load);
+}
diff --git a/ameba/amebadplus/source/fwlib/ram_common/ameba_loguart.c b/ameba/amebadplus/source/fwlib/ram_common/ameba_loguart.c
index 3c4551e6..5e454fcd 100644
--- a/ameba/amebadplus/source/fwlib/ram_common/ameba_loguart.c
+++ b/ameba/amebadplus/source/fwlib/ram_common/ameba_loguart.c
@@ -17,3 +17,134 @@ void LOGUART_INT_NP2AP(void)
 	LOGUART_INTCoreConfig(LOGUART_DEV, LOGUART_BIT_INTR_MASK_KM0, DISABLE);
 	LOGUART_INTCoreConfig(LOGUART_DEV, LOGUART_BIT_INTR_MASK_KM4, ENABLE);
 }
+
+/**
+  * @brief Switch LOGUART interrupt from AP to NP.
+  * @param None
+  * @retval None
+  * @note KM0 is NP and KM4 is AP.
+  */
+void LOGUART_INT_AP2NP(void)
+{
+	LOGUART_INTCoreConfig(LOGUART_DEV, LOGUART_BIT_INTR_MASK_KM4, DISABLE);
+	LOGUART_INTCoreConfig(LOGUART_DEV, LOGUART_BIT_INTR_MASK_KM0, ENABLE);
+}
+
+/**
+  * @brief  Set LOGUART IMR
+  * @param  SetValue: specifies the LOGUART interrupt sources to be enabled or disabled.
+  *          This parameter can be one or combinations of the following values:
+  *            @arg LOGUART_BIT_ERBI:  Received Data Available interrupt
+  *            @arg LOGUART_BIT_ELSI:  Receiver Line Status interrupt
+  *            @arg LOGUART_BIT_ETOI: Rx Time Out interrupt
+  *            @arg LOGUART_BIT_EDSSI: Modem Status Interrupt
+  *            @arg LOGUART_TX_EMPTY_PATH_1_INTR: Tx Path 1 Transmitter FIFO Empty interrupt
+  *            @arg LOGUART_TX_EMPTY_PATH_2_INTR: Tx Path 2 Transmitter FIFO Empty interrupt
+  *            @arg LOGUART_TX_EMPTY_PATH_3_INTR: Tx Path 3 Transmitter FIFO Empty interrupt
+  *            @arg LOGUART_TX_EMPTY_PATH_4_INTR: Tx Path 4 Transmitter FIFO Empty interrupt
+  * @retval none
+  */
+void LOGUART_INTConfig(LOGUART_TypeDef *UARTLOG, u32 UART_IT, u32 newState)
+{
+	(void)UARTLOG;
+
+	u32 IerVal = LOGUART_GetIMR();
+
+	if (IS_LOGUART_TX_EMPTY_ENABLE(UART_IT & LOGUART_MASK_ETPFEI)) {
+		IerVal &= ~LOGUART_MASK_ETPFEI;
+	}
+
+	if (newState == ENABLE) {
+		/* Enable the selected UARTx interrupts */
+		IerVal |= UART_IT;
+	} else {
+		/* Disable the selected UARTx interrupts */
+		IerVal &= (u32)~(UART_IT & (~LOGUART_MASK_ETPFEI));
+	}
+
+	LOGUART_SetIMR(IerVal);
+}
+
+extern LOG_UART_PORT LOG_UART_IDX_FLAG[];
+/**
+* @brief  Check if there is space in loguart tx path fifo.
+* @retval Status value:
+*          - 1: tx path fifo is not full
+*          - 0: tx path fifo is full
+*/
+u8 LOGUART_Writable(void)
+{
+	LOGUART_TypeDef *UARTLOG = LOGUART_DEV;
+	u32 CPUID = SYS_CPUID();
+
+	if (UARTLOG->LOGUART_UART_LSR & LOG_UART_IDX_FLAG[CPUID].not_full) {
+		return 1;
+	} else {
+		return 0;
+	}
+}
+
+/**
+ * @brief Wait until current tx path FIFO turns empty.
+ * @return None
+ * @note This function is called to check current tx path FIFO is empty or not.
+ * 		To check if tx process has been finished, call LOGUART_WaitTxComplete instead.
+ */
+void LOGUART_WaitBusy(void)
+{
+	LOGUART_TypeDef *UARTLOG = LOGUART_DEV;
+	u32 CPUID = SYS_CPUID();
+
+	/* Wait for LogUart print out */
+	while (1) {
+		if (UARTLOG->LOGUART_UART_LSR & LOG_UART_IDX_FLAG[CPUID].empty) {
+			break;
+		}
+
+		/* exit while-loop ASAP */
+		DelayUs(1);
+	}
+}
+
+/**
+ * @brief Wait until tx process finishes.
+ * @return None
+ * @note This function is called to wait until tx data is completely pushed from tx FIFO
+ * 		and all the tx path FIFO is empty.
+ */
+void LOGUART_WaitTxComplete(void)
+{
+	LOGUART_TypeDef *UARTLOG = LOGUART_DEV;
+	u32 lsr;
+
+	while (1) {
+		lsr = UARTLOG->LOGUART_UART_LSR;
+
+		if ((lsr & LOGUART_BIT_TP1F_EMPTY) && (lsr & LOGUART_BIT_TP2F_EMPTY) && (lsr & LOGUART_BIT_TP3F_EMPTY)  && \
+			(lsr & LOGUART_BIT_TP4F_EMPTY) && (!(lsr & LOGUART_BIT_RPF_DRDY)) && (lsr & LOGUART_BIT_TX_EMPTY)) {
+			break;
+		}
+
+		/* exit while-loop ASAP */
+		DelayUs(1);
+	}
+}
+
+/**
+ * @brief Transmit single byte to current tx path FIFO without appending characters.
+ * @param c Data to be transmitted.
+ * @return None
+ */
+void LOGUART_PutChar_RAM(u8 c)
+{
+	LOGUART_TypeDef *UARTLOG = LOGUART_DEV;
+	u32 CPUID = SYS_CPUID();
+
+	if (ConfigDebugClose == 1) {
+		return;
+	}
+
+	LOGUART_WaitTx();
+
+	UARTLOG->LOGUART_UART_THRx[LOG_UART_IDX_FLAG[CPUID].idx] = c;
+}
diff --git a/ameba/amebadplus/source/fwlib/ram_common/ameba_mpu_ram.c b/ameba/amebadplus/source/fwlib/ram_common/ameba_mpu_ram.c
new file mode 100644
index 00000000..3d199bc0
--- /dev/null
+++ b/ameba/amebadplus/source/fwlib/ram_common/ameba_mpu_ram.c
@@ -0,0 +1,121 @@
+/*
+ * Copyright (c) 2024 Realtek Semiconductor Corp.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "cmsis.h"
+#include "mpu_config.h"
+
+static const char *const TAG = "MPU";
+u8 mpu_entry_register[MPU_MAX_REGION];
+
+/**
+  * @brief  init mpu memory attribute to typical value.
+  * @param  NA.
+  * @note   typical value:
+  *              - typical value if defined in @ref mpu_mem_attri_typical_define.
+  * @retval   None
+  */
+void mpu_init(void)
+{
+	ARM_MPU_Disable();
+
+	/* Configure memory types */
+	MPU->MAIR0 = ((MPU_MEM_ATTR0) << MPU_MAIR0_Attr0_Pos) | \
+				 ((MPU_MEM_ATTR1) << MPU_MAIR0_Attr1_Pos) | \
+				 ((MPU_MEM_ATTR2) << MPU_MAIR0_Attr2_Pos) | \
+				 ((MPU_MEM_ATTR3) << MPU_MAIR0_Attr3_Pos);
+
+	MPU->MAIR1 = ((MPU_MEM_ATTR4) << MPU_MAIR1_Attr4_Pos) | \
+				 ((MPU_MEM_ATTR5) << MPU_MAIR1_Attr5_Pos) | \
+				 ((MPU_MEM_ATTR6) << MPU_MAIR1_Attr6_Pos) | \
+				 ((MPU_MEM_ATTR7) << MPU_MAIR1_Attr7_Pos);
+
+	/* PRIVDEFENA Privileged background region enable:
+	 *    <0=> All accesses to unmapped addresses result in faults.
+	 *    <1=> Enables the default memory map for privilege code when the address accessed does not map into any MPU region.
+	 * HFNMIENA MPU Enable for HardFault and NMI (Non-Maskable Interrupt):
+	 *    <0=> HardFault and NMI handlers bypass MPU configuration as if MPU is disabled.
+	 *    <1=> MPU access rules apply to HardFault and NMI handlers.
+	 */
+	ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk & ~MPU_CTRL_HFNMIENA_Msk);
+}
+
+/**
+  * @brief  change mpu memory attribute.
+  * @param  attr_idx: where x can be 0~7.
+  * @param  mem_attr: memory attribute. @ref mpu_region_memory_attribute_define.
+  * @note   NA:
+  *              - NA.
+  * @retval   None
+  */
+void mpu_set_mem_attr(uint8_t attr_idx, uint8_t mem_attr)
+{
+	assert_param(attr_idx < MPU_MAX_REGION);
+
+	ARM_MPU_Disable();
+	ARM_MPU_SetMemAttr(attr_idx, mem_attr);
+	ARM_MPU_Enable(MPU->CTRL);
+}
+
+/**
+  * @brief  config mpu region memory attribute.
+  * @param  region_num: where x can be 0~3. (KM0 & KM4 both)
+  * @param  pmpu_cfg: pointer to an mpu_region_config structure which has been configured.
+  * @note    NA:
+  *              - NA.
+  * @retval   None
+  */
+void mpu_region_cfg(uint8_t region_num, mpu_region_config *pmpu_cfg)
+{
+	MPU_Type *mpu = MPU;
+	u32 region_limit = pmpu_cfg->region_base + pmpu_cfg->region_size - 1;
+
+	assert_param(region_num < MPU_MAX_REGION);
+	assert_param((pmpu_cfg->region_base & ~MPU_RBAR_BASE_Msk) == 0);
+	assert_param((pmpu_cfg->region_size & ~MPU_RLAR_LIMIT_Msk) == 0);
+
+	ARM_MPU_Disable();
+
+	mpu->RNR = region_num;
+	mpu->RBAR = (pmpu_cfg->region_base & MPU_RBAR_BASE_Msk) | \
+				pmpu_cfg->sh | \
+				pmpu_cfg->ap | \
+				pmpu_cfg->xn;
+	mpu->RLAR = ARM_MPU_RLAR(region_limit, pmpu_cfg->attr_idx);
+
+	ARM_MPU_Enable(mpu->CTRL);
+
+	RTK_LOGD(TAG, "mpu_region[%d] RBAR:0x%lx RLAR:0x%lx attr_idx:%d\n", mpu->RNR, mpu->RBAR, mpu->RLAR, pmpu_cfg->attr_idx);
+	RTK_LOGD(TAG, "MAIR0:0x%lx MAIR1:0x%lx CTRL:0x%lx TYPE:0x%lx\n", mpu->MAIR0, mpu->MAIR1, mpu->CTRL, mpu->TYPE);
+}
+
+/**
+  * @brief  free mpu entry.
+  * @param  entry_index: KM0: 0~3, KM4_NS: 0~7; KM4_S: 0~3.
+  * @retval   None
+  */
+void mpu_entry_free(u32 entry_index)
+{
+	mpu_entry_register[entry_index] = 0;
+}
+
+/**
+  * @brief  alloc a free mpu entry.
+  * @param  NA.
+  * @retval value: mpu entry index KM0: 0~3, KM4_NS: 0~7; KM4_S: 0~3, -1 is fail.
+  */
+char mpu_entry_alloc(void)
+{
+	u32 entry_index = 0;
+
+	for (entry_index = 0; entry_index < MPU_MAX_REGION; entry_index++) {
+		if (mpu_entry_register[entry_index] == 0) {
+			mpu_entry_register[entry_index] = 1;
+			return entry_index;
+		}
+	}
+
+	return -1;
+}
diff --git a/ameba/amebadplus/source/fwlib/ram_common/ameba_ppe.c b/ameba/amebadplus/source/fwlib/ram_common/ameba_ppe.c
new file mode 100644
index 00000000..31f5e024
--- /dev/null
+++ b/ameba/amebadplus/source/fwlib/ram_common/ameba_ppe.c
@@ -0,0 +1,448 @@
+/*
+ * Copyright (c) 2024 Realtek Semiconductor Corp.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "ameba_soc.h"
+/** @addtogroup Ameba_Periph_Driver
+  * @{
+  */
+
+/** @defgroup PPE
+* @brief PPE driver modules
+* @{
+*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup PPE_Exported_Functions PPE Exported Functions
+  * @{
+  */
+
+
+/**
+  * @brief  Enable PPE.
+  * @param  state: the state of PPE.
+  *              This parameter can only be ENABLE.
+  * @retval None.
+  */
+void PPE_Cmd(int state)
+{
+	if (state) {
+		PPE->GLB_CTL |= PPE_GLB_EN_MSK;
+	}
+}
+
+/**
+  * @brief  Get PPE global state.
+  * @param  None.
+  * @retval Global state. 0 means PPE is not working, 1 means PPE is working.
+  */
+u32 PPE_GetGlobalState(void)
+{
+	return (PPE->GLB_CTL & PPE_GLB_EN_MSK);
+}
+
+/**
+  * @brief  Suspend PPE.
+  * @param  None.
+  * @retval None.
+  */
+void PPE_Suspend(void)
+{
+	PPE->GLB_CTL |= PPE_SUSPEND_MSK;
+}
+
+/**
+  * @brief  Resume PPE from suspend state.
+  * @param  None.
+  * @retval None.
+  */
+void PPE_Resume(void)
+{
+	PPE->GLB_CTL = PPE_RESUME_MSK;
+}
+
+/**
+  * @brief  PPE abort.
+  * @param  None.
+  * @retval None.
+  */
+void PPE_Abort(void)
+{
+	/* Abort the transaction when the values of SUSP and ALL_INACT are both 1*/
+	PPE->GLB_CTL |= PPE_SUSPEND_MSK;
+	while (!(PPE->GLB_CTL & PPE_ALL_INACT_MSK));
+	PPE->GLB_CTL = PPE_ABORT_MSK;
+}
+
+
+/**
+  * @brief  Check if a layer is inactive.
+  * @param  chn_id: the layer number to be checked.
+  * @retval Status.
+  */
+int PPE_ChannelInactiveCheck(u8 chn_id)
+{
+	int rv = 0;
+
+	if (PPE->GLB_CTL & ((BIT0 << PPE_CHN_INACT_POS) << chn_id)) {
+		rv = 1;
+	}
+	return rv;
+}
+
+/**
+  * @brief  Set ration of scale function.
+  * @param  scale_x: ration of scale in X diretion. No smaller than 1/16.
+  *         scale_y: ration of scale in Y diretion. No smaller than 1/16.
+  * @retval None.
+  */
+void PPE_SetScaleRation(float scale_x, float scale_y)
+{
+	u32 fix_x, fix_y;
+
+	assert_param(scale_x > 0);
+	assert_param(scale_y > 0);
+
+	fix_x = (u32)(65536 / scale_x);
+	fix_y = (u32)(65536 / scale_y);
+
+	/* workaround: In multi-frame function, if fix_y of first frame is multiple of 65536 and fix_y of
+	second frame, and input layer1 is not reload for the second frame, error may occur. So here set fix_y
+	minus 1 */
+	if ((fix_y >= 65536) && (fix_y % 65536 == 0)) {
+		fix_y = fix_y - 1;
+	}
+
+	PPE->SCA_RATIO_X = fix_x;
+	PPE->SCA_RATIO_Y = fix_y;
+}
+
+/**
+  * @brief  Get all interrupt status.
+  * @param  None.
+  * @retval Status.
+  */
+u32 PPE_GetAllIntStatus(void)
+{
+	return PPE->INT_STATUS;
+}
+
+/**
+  * @brief  Clear specific interrupt status.
+  * @param  PPE_INT: specifies the PPE interrupt type.
+  *          This parameter can be one or combinations of the following values:
+  *            @arg PPE_ALL_OVER_INT: All frames blend or scale over.
+  *            @arg PPE_FR_OVER_INT: One frame blend or scale over.
+  *            @arg PPE_LOAD_OVER_INT: layers register be loaded to internal register over.
+  *            @arg PPE_LINE_WL_INT: Specific line blend/scale over.
+  *            @arg PPE_SUSP_INAC_INT: All channels come to inactive after suspend.
+  * @retval None.
+  */
+void PPE_ClearINTPendingBit(u32 PPE_INT)
+{
+	PPE->INT_CLR |= PPE_INT;
+}
+
+/**
+  * @brief  Enable/disable specific interrupt.
+  * @param  PPE_INT_MSK: specifies the PPE interrupt type.
+  *          This parameter can be one or combinations of the following values:
+  *            @arg PPE_ALL_OVER_INT: All frames blend or scale over.
+  *            @arg PPE_FR_OVER_INT: One frame blend or scale over.
+  *            @arg PPE_LOAD_OVER_INT: layers register be loaded to internal register over.
+  *            @arg PPE_LINE_WL_INT: Specific line blend/scale over.
+  *            @arg PPE_SUSP_INAC_INT: All channels come to inactive after suspend.
+  *         NewState: the new state.
+  *              This parameter can be: ENABLE or DISABLE.
+  * @retval None.
+  */
+void PPE_MaskINTConfig(u32 PPE_INT_MSK, int NewState)
+{
+	if (NewState == ENABLE) {
+		PPE->INT_MASK |= PPE_INT_MSK;
+	} else {
+		PPE->INT_MASK &= ~PPE_INT_MSK;
+	}
+}
+
+/**
+  * @brief  Mask all interrupt.
+  * @param  None.
+  * @retval None.
+  */
+void PPE_MaskAllInt(void)
+{
+	PPE->INT_MASK = 0x0;
+}
+
+/**
+  * @brief  Configure auto reload layers.
+  * @param  layers: auto reload layers.
+  *          This parameter can be one or combinations of the following values:
+  *            @arg PPE_RESULT_LAYER_BIT: result layer.
+  *            @arg PPE_INPUT_LAYER1_BIT: input layer1.
+  *            @arg PPE_INPUT_LAYER2_BIT: input layer2.
+  *            @arg PPE_INPUT_LAYER3_BIT: input layer3.
+  * @retval None.
+  */
+void PPE_AutoReloadSetLayer(u32 layers)
+{
+	u32 reload_en;
+
+	reload_en = PPE_LAYER_RELOAD_EN_MSK & layers;
+	PPE->RELOAD_CFG &= PPE_LAYER_RELOAD_EN_CLR;
+	PPE->RELOAD_CFG |= reload_en;
+}
+
+/**
+  * @brief  Enable/disable Auto reload function.
+  * @param  NewState: the new state.
+  *              This parameter can be: ENABLE or DISABLE.
+  * @retval None.
+  */
+void PPE_AutoReloadClrLayerAll(void)
+{
+	PPE->RELOAD_CFG &= PPE_LAYER_RELOAD_EN_CLR;
+}
+
+/**
+  * @brief  Enable/disable auto cleared after loading.
+  * @param  NewState:the new state.
+  *              This parameter can be: ENABLE or DISABLE.
+  * @retval None.
+  */
+void PPE_AutoClearCmd(int NewState)
+{
+	if (NewState) {
+		PPE->RELOAD_CFG |= PPE_AUTO_CLR_MSK;
+	} else {
+		PPE->RELOAD_CFG &= PPE_AUTO_CLR_CLR;
+	}
+}
+
+/**
+  * @brief  Tell PPE setting is vaild for auto reload function.
+  * @param  None
+  * @retval None.
+  */
+void PPE_SetValid(void)
+{
+	PPE->RELOAD_CFG |= PPE_SET_VALID_MSK;
+}
+
+/**
+  * @brief  Get setting valid value to polling.
+  * @param  None.
+  * @retval Set valid bit value. 0 means user can use to PPE_SetValid tell PPE setting is valid.
+  */
+u32 PPE_GetValid(void)
+{
+	return ((PPE->RELOAD_CFG & PPE_SET_VALID_MSK) == 0) ? 0 : 1;
+}
+
+/**
+  * @brief  Set LLP value to the pointer of first linklist item.
+  * @param  lli: pointer to first listlist item. Must align to 4Byte.
+  * @retval None.
+  */
+void PPE_SetLLP(u32      lli)
+{
+	PPE->LLP = lli;
+}
+
+/**
+  * @brief  Set layer used by first linklist item.
+  * @param  layers: linklist layers.
+  *          This parameter can be one or combinations of the following values:
+  *            @arg PPE_RESULT_LAYER_BIT: result layer.
+  *            @arg PPE_INPUT_LAYER1_BIT: input layer1.
+  *            @arg PPE_INPUT_LAYER2_BIT: input layer2.
+  *            @arg PPE_INPUT_LAYER3_BIT: input layer3.
+  * @retval None.
+  */
+void PPE_LLSetLayer(u32 layers)
+{
+	u32 layer_ll_en;
+
+	layer_ll_en = PPE_LAYER_LL_EN_MSK & layers;
+	PPE->LL_CFG &= PPE_LAYER_LL_EN_CLR;
+	PPE->LL_CFG |= layer_ll_en;
+}
+
+
+/**
+  * @brief  Set line index for line over interrupt.
+  * @param  line: the link index.
+  * @retval None.
+  */
+void PPE_SetLine(u32 line)
+{
+	PPE->LINE_INDEX = line;
+}
+
+
+/**
+  * @brief  Fills each PPE_init_struct member with its default value.
+  * @param  PPE_init_struct: pointer to an PPE_InitTypeDef structure which will be initialized.
+  * @retval None
+  */
+void PPE_StructInit(PPE_InitTypeDef *PPE_init_struct)
+{
+	assert_param(PPE_init_struct != NULL);
+
+	PPE_init_struct->function = PPE_FUNCTION_ALPHA_BLEND;
+	PPE_init_struct->blend_layer_num = 0;
+}
+
+/**
+  * @brief  Fills each layer_init_struct member with its default value.
+  * @param  layer_init_struct: pointer to an PPE_InputLayer_InitTypeDef structure which will be initialized.
+  * @retval None
+  */
+void PPE_InputLayer_StructInit(PPE_InputLayer_InitTypeDef *layer_init_struct)
+{
+	layer_init_struct->src_addr 								= 0;
+	layer_init_struct->start_x									= 0;
+	layer_init_struct->start_y									= 0;
+	layer_init_struct->width									= 1;
+	layer_init_struct->height									= 1;
+	layer_init_struct->const_ABGR8888_value						= 0xFFFFFFFF;
+	layer_init_struct->format									= PPE_RGB888;
+	layer_init_struct->src										= PPE_LAYER_SRC_FROM_DMA;
+	layer_init_struct->color_key_en								= DISABLE;
+	layer_init_struct->line_len									= 0;
+	layer_init_struct->key_color_value							= 0xFFFFFFFF;
+}
+
+/**
+  * @brief  Fills each layer_init_struct member with its default value.
+  * @param  layer_init_struct: pointer to an PPE_ResultLayer_InitTypeDef structure which will be initialized.
+  * @retval None
+  */
+void PPE_ResultLayer_StructInit(PPE_ResultLayer_InitTypeDef *layer_init_struct)
+{
+	layer_init_struct->src_addr						= 0;
+	layer_init_struct->width						= 1;
+	layer_init_struct->height						= 1;
+	layer_init_struct->format 						= PPE_RGB888;
+	layer_init_struct->line_len						= 1;
+	layer_init_struct->type 						= PPE_ADDR_MEM;
+}
+
+/**
+  * @brief  Initializes the PPE peripheral according to the specified
+  *              parameters in the PPE_init_struct.
+  * @param  PPE_init_struct: pointer to a PPE_InitTypeDef structure that contains
+  *              the configuration information for the specified PPE peripheral.
+  * @retval None
+  */
+void PPE_Init(PPE_InitTypeDef *PPE_init_struct)
+{
+	assert_param(PPE_init_struct != NULL);
+	assert_param(IS_PPE_FUNCTION(PPE_init_struct->function));
+
+	switch (PPE_init_struct->function) {
+	case PPE_FUNCTION_ALPHA_BLEND: {
+		assert_param(IS_PPE_ALPHA_BLEND_LAYER_NUM(PPE_init_struct->blend_layer_num));
+		PPE->FUNC_CFG &= PPE_FUNC_SEL_CLR;
+		PPE->FUNC_CFG |= ((PPE_FUNCTION_ALPHA_BLEND << PPE_FUNC_SEL_POS) & PPE_FUNC_SEL_MSK);
+		PPE->FUNC_CFG &= PPE_BLEND_LAYER_NUM_CLR;
+		PPE->FUNC_CFG |= ((PPE_init_struct->blend_layer_num << PPE_BLEND_LAYER_NUM_POS) & PPE_BLEND_LAYER_NUM_MSK);
+		break;
+	}
+	case PPE_FUNCTION_SCALE: {
+		PPE->FUNC_CFG &= PPE_FUNC_SEL_CLR;
+		PPE->FUNC_CFG |= ((PPE_FUNCTION_SCALE << PPE_FUNC_SEL_POS) & PPE_FUNC_SEL_MSK);
+		break;
+	}
+	}
+}
+
+/**
+  * @brief  Initialize specific input layer.
+  * @param  id: Input layer number. Can be 1/2/3.
+  *         layer_init_struct: pointer to a PPE_InputLayer_InitTypeDef structure that contains
+  *              the configuration information for the specified input layer.
+  * @retval None
+  */
+void PPE_InitInputLayer(u8 id, PPE_InputLayer_InitTypeDef *layer_init_struct)
+{
+	u8 cov_layer_id = id - 1;
+
+	PPE_LAYER->INPUT_LAYER[cov_layer_id].ADDR = layer_init_struct->src_addr;
+	PPE_LAYER->INPUT_LAYER[cov_layer_id].CONST_PIX = layer_init_struct->const_ABGR8888_value;
+	PPE_LAYER->INPUT_LAYER[cov_layer_id].POS = (
+				((layer_init_struct->start_x << INPUT_LAYER_POS_X_POS) & INPUT_LAYER_POS_X_MSK) |
+				((layer_init_struct->start_y << INPUT_LAYER_POS_Y_POS) & INPUT_LAYER_POS_Y_MSK)
+			);
+	PPE_LAYER->INPUT_LAYER[cov_layer_id].WIN_SIZE = (
+				((layer_init_struct->width << INPUT_LAYER_WIDTH_POS) & INPUT_LAYER_WIDTH_MSK) |
+				((layer_init_struct->height << INPUT_LAYER_HEIGHT_POS) & INPUT_LAYER_HEIGHT_MSK)
+			);
+	PPE_LAYER->INPUT_LAYER[cov_layer_id].PIC_CFG = (
+				((layer_init_struct->format << INPUT_LAYER_PIX_FORMAT_POS) & INPUT_LAYER_PIX_FORMAT_MSK) |
+				((layer_init_struct->src << INPUT_LAYER_PIX_SRC_POS) & INPUT_LAYER_PIX_SRC_MSK) |
+				((layer_init_struct->color_key_en << INPUT_LAYER_KEY_EN_POS) & INPUT_LAYER_KEY_EN_MSK) |
+				((layer_init_struct->line_len << INPUT_LAYER_LINE_LEN_POS) & INPUT_LAYER_LINE_LEN_MSK)
+			);
+	PPE_LAYER->INPUT_LAYER[cov_layer_id].KEY_COLOR = layer_init_struct->key_color_value;
+	PPE_LAYER->INPUT_LAYER[cov_layer_id].HS_CFG = (
+				((0 << INPUT_LAYER_HW_INDEX_POS) & INPUT_LAYER_HW_INDEX_MSK) |
+				((PPE_MSIZE_8 << INPUT_LAYER_MSIZE_LOG_POS) & INPUT_LAYER_MSIZE_LOG_MSK) |
+				((DISABLE << INPUT_LAYER_HS_EN_POS) & INPUT_LAYER_HS_EN_MSK) |
+				((PPE_POLARITY_HIGH << INPUT_LAYER_POLAR_POS) & INPUT_LAYER_POLAR_MSK) |
+				((PPE_DMA_HW_HANDSHAKE << INPUT_LAYER_HW_HS_POS) & INPUT_LAYER_HW_HS_MSK)
+			);
+	PPE_LAYER->INPUT_LAYER[cov_layer_id].BUS_CFG = (
+				((0 << INPUT_LAYER_PRIOR_POS) & INPUT_LAYER_PRIOR_MSK) |
+				((PPE_MAX_AXLEN_127 << INPUT_LAYER_MAX_AXLEN_LOG_POS) & INPUT_LAYER_MAX_AXLEN_LOG_MSK) |
+				((1 << INPUT_LAYER_AXCACHE_POS) & INPUT_LAYER_AXCACHE_MSK) |
+				((PPE_ARBURST_INCR << INPUT_LAYER_INCR_POS) & INPUT_LAYER_INCR_MSK) |
+				((2 << INPUT_LAYER_AXSIZE_POS) & INPUT_LAYER_AXSIZE_MSK)
+			);
+}
+
+/**
+  * @brief  Initialize result layer.
+  * @param  layer_init_struct: pointer to a PPE_ResultLayer_InitTypeDef structure that contains
+  *              the configuration information for the result layer.
+  * @retval None
+  */
+void PPE_InitResultLayer(PPE_ResultLayer_InitTypeDef *layer_init_struct)
+{
+	u32 handshake_en, INCR;
+
+	if (layer_init_struct->type == PPE_ADDR_QSPI) {
+		handshake_en = ENABLE;
+		INCR = PPE_ARBURST_FIX;
+	} else {
+		handshake_en = DISABLE;
+		INCR = PPE_ARBURST_INCR;
+	}
+
+	PPE_LAYER->RESULT_LAYER.ADDR = layer_init_struct->src_addr;
+	PPE_LAYER->RESULT_LAYER.WIN_SIZE = (
+										   ((layer_init_struct->width << RESULT_LAYER_WIDTH_POS) & RESULT_LAYER_WIDTH_MSK) |
+										   ((layer_init_struct->height << RESULT_LAYER_HEIGHT_POS) & RESULT_LAYER_HEIGHT_MSK)
+									   );
+	PPE_LAYER->RESULT_LAYER.PIC_CFG = (
+										  ((layer_init_struct->format << RESULT_LAYER_PIX_FORMAT_POS) & RESULT_LAYER_PIX_FORMAT_MSK) |
+										  ((layer_init_struct->line_len << RESULT_LAYER_LINE_LEN_POS) & RESULT_LAYER_LINE_LEN_MSK)
+									  );
+	PPE_LAYER->RESULT_LAYER.HS_CFG = (
+										 ((0 << RESULT_LAYER_HW_INDEX_POS) & RESULT_LAYER_HW_INDEX_MSK) |
+										 ((PPE_MSIZE_8 << RESULT_LAYER_MSIZE_LOG_POS) & RESULT_LAYER_MSIZE_LOG_MSK) |
+										 ((handshake_en << RESULT_LAYER_HS_EN_POS) & RESULT_LAYER_HS_EN_MSK) |
+										 ((PPE_POLARITY_HIGH << RESULT_LAYER_POLAR_POS) & RESULT_LAYER_POLAR_MSK) |
+										 ((PPE_DMA_HW_HANDSHAKE << RESULT_LAYER_HW_HS_POS) & RESULT_LAYER_HW_HS_MSK)
+									 );
+	PPE_LAYER->RESULT_LAYER.BUS_CFG = (
+										  ((0 << RESULT_LAYER_PRIOR_POS) & RESULT_LAYER_PRIOR_MSK) |
+										  ((PPE_MAX_AXLEN_127 << RESULT_LAYER_MAX_AXLEN_LOG_POS) & RESULT_LAYER_MAX_AXLEN_LOG_MSK) |
+										  ((1 << RESULT_LAYER_AXCACHE_POS) & RESULT_LAYER_AXCACHE_MSK) |
+										  ((INCR << RESULT_LAYER_INCR_POS) & RESULT_LAYER_INCR_MSK) |
+										  ((2 << RESULT_LAYER_AXSIZE_POS) & RESULT_LAYER_AXSIZE_MSK)
+									  );
+}
diff --git a/ameba/amebadplus/source/fwlib/ram_common/ameba_psram.c b/ameba/amebadplus/source/fwlib/ram_common/ameba_psram.c
new file mode 100644
index 00000000..19b765c1
--- /dev/null
+++ b/ameba/amebadplus/source/fwlib/ram_common/ameba_psram.c
@@ -0,0 +1,854 @@
+/*
+ * Copyright (c) 2024 Realtek Semiconductor Corp.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "ameba_soc.h"
+static const char *const TAG = "PSRAM";
+u8 APM_WR_INIT_LATENCY_SPEC[6] = {
+	APM_WR_INIT_LATENCY_3CLK,
+	APM_WR_INIT_LATENCY_4CLK,
+	APM_WR_INIT_LATENCY_5CLK,
+	APM_WR_INIT_LATENCY_6CLK,
+	APM_WR_INIT_LATENCY_7CLK,
+	APM_WR_INIT_LATENCY_8CLK,
+};
+
+
+static const u32 PSRAM_CALIB_PATTERN[6] = {
+	0x11223344,
+	0xA55AA55A,
+	0x5AA55AA5,
+	0x44332211,
+	0x96696996,
+	0x69969669,
+};
+PSRAMINFO_TypeDef PsramInfo;
+
+
+/**
+ * @brief  Initialize PSRAMINFO_TypeDef according to the memory configuration from MCM_MemTypeDef.
+ * @param  meminfo [in]  Pointer to MCM_MemTypeDef structure (typically from ChipInfo_MCMInfo()).
+ * @param  info    [out] Pointer to PSRAMINFO_TypeDef structure to fill in.
+ * @return None
+ * @note
+ */
+void ChipInfo_InitPsramInfoFromMemInfo(const MCM_MemTypeDef *meminfo, PSRAMINFO_TypeDef *info)
+{
+	_memset(info, 0, sizeof(PSRAMINFO_TypeDef));
+	info->Psram_Page_size = 0;
+	info->Psram_Clk_Limit = 0;
+	info->Psram_Type      = 0;
+	RRAM_TypeDef *rram = RRAM_DEV;
+
+	if (meminfo == NULL || info == NULL) {
+		return;
+	}
+
+	if (meminfo->mem_type == MCM_TYPE_PSRAM) {
+		switch (meminfo->dram_info.model) {
+		case MCM_PSRAM_VENDOR_WB:
+			info->Psram_Vendor = MCM_PSRAM_VENDOR_WB;
+			switch (meminfo->dram_info.density) {
+			case MCM_PSRAM_SIZE_32Mb:
+				info->Psram_Size	   = 4 * 1024 * 1024;
+				info->Psram_Page_size  = PSRAM_PAGE128;
+				info->Psram_Clk_Limit  = PSRAM_DEVICE_CLK_200;
+				info->Psram_Type       = PSRAM_TYPE_WB955;
+				break;
+			case MCM_PSRAM_SIZE_128Mb:
+				info->Psram_Size	   = 16 * 1024 * 1024;
+				info->Psram_Page_size  = PSRAM_PAGE2048;
+				info->Psram_Clk_Limit  = PSRAM_DEVICE_CLK_250;
+				info->Psram_Type       = PSRAM_TYPE_WB957;
+				break;
+			case MCM_PSRAM_SIZE_256Mb:
+				info->Psram_Size	   = 32 * 1024 * 1024;
+				info->Psram_Page_size  = PSRAM_PAGE1024;
+				info->Psram_Clk_Limit  = PSRAM_DEVICE_CLK_250;
+				info->Psram_Type       = PSRAM_TYPE_WB958;
+				break;
+			default:
+				break;
+			}
+			break;
+		case MCM_PSRAM_VENDOR_APM:
+			info->Psram_Vendor = MCM_PSRAM_VENDOR_APM;
+			switch (meminfo->dram_info.density) {
+			case MCM_PSRAM_SIZE_64Mb:
+				info->Psram_Size	   = 8 * 1024 * 1024;
+				info->Psram_Page_size  = PSRAM_PAGE1024;
+				info->Psram_Clk_Limit  = PSRAM_DEVICE_CLK_200;
+				info->Psram_Type       = PSRAM_TYPE_APM64;
+				break;
+			default:
+				break;
+			}
+			break;
+
+		default:
+			info->Psram_Vendor = MCM_PSRAM_VENDOR_NOTCARE;
+			break;
+		}
+	} else {
+		info->Psram_Vendor = MCM_PSRAM_VENDOR_NOTCARE;
+	}
+	rram->PSRAM_TYPE = info->Psram_Vendor;
+}
+
+
+/**
+  * @brief get psram clk info
+  * @param  none
+  * @retval none
+  */
+void PSRAM_CLK_Update(void)
+{
+	MCM_MemTypeDef meminfo = ChipInfo_MCMInfo();
+	ChipInfo_InitPsramInfoFromMemInfo(&meminfo, &PsramInfo);
+
+	u32 PsramClk = 0;
+	u32 PLLCLk, Div;
+	u32 Temp = HAL_READ32(SYSTEM_CTRL_BASE, REG_LSYS_CKSL_GRP0);
+	u32 ClkSel = LSYS_GET_CKSL_PSRAM(Temp);
+
+	if (ClkSel == BIT_LSYS_CKSL_SPIC_XTAL) {
+
+		PsramClk = XTAL_ClkGet();
+
+	} else if (ClkSel == BIT_LSYS_CKSL_SPIC_PLL) {
+		Div = LSYS_GET_PSRAMC_FLASH_DIV_INT(HAL_READ32(SYSTEM_CTRL_BASE, REG_LSYS_PSRAMC_FLASH_CTRL));
+		Div += 1;
+
+		PLLCLk = PLL_ClkGet();
+		PsramClk = PLLCLk / Div;
+
+	}
+
+	if (!PsramClk) {
+		RTK_LOGE(TAG, "Invalid PsramClk\n");
+		return ;
+	}
+
+	PsramInfo.Psram_Clk_Set = PsramClk / 2;
+	PsramInfo.PSRAMC_Clk_Unit = 1000000000000 / PsramClk;// unit ps
+
+	if (PsramInfo.Psram_Vendor == MCM_PSRAM_VENDOR_WB) {
+		if (PsramInfo.Psram_Clk_Set <= 83000000) {
+			PsramInfo.Psram_Latency_Set = 3;
+			PsramInfo.Psram_TRWR = Psram_WB_TRWR133;
+			PsramInfo.Psram_Latency_Code = WB_INIT_LATENCY_3CLK;
+		} else if (PsramInfo.Psram_Clk_Set <= 104000000) {
+			PsramInfo.Psram_Latency_Set = 4;
+			PsramInfo.Psram_TRWR = Psram_WB_TRWR133;
+			PsramInfo.Psram_Latency_Code = WB_INIT_LATENCY_4CLK;
+		} else if (PsramInfo.Psram_Clk_Set <= 133000000) {
+			PsramInfo.Psram_Latency_Set = 5;
+			PsramInfo.Psram_TRWR = Psram_WB_TRWR133;
+			PsramInfo.Psram_Latency_Code = WB_INIT_LATENCY_5CLK;
+		} else if (PsramInfo.Psram_Clk_Set <= 200000000) {
+			PsramInfo.Psram_Latency_Set = 6;
+			PsramInfo.Psram_TRWR = Psram_WB_TRWR166;
+			PsramInfo.Psram_Latency_Code = WB_INIT_LATENCY_6CLK;
+		}
+
+	} else if (PsramInfo.Psram_Vendor == MCM_PSRAM_VENDOR_APM) {
+
+		if (PsramInfo.Psram_Clk_Set <= 104000000) {
+			PsramInfo.Psram_Latency_Set = 4;
+			PsramInfo.Psram_CSHI = Psram_APM_CSHI133;
+		} else if (PsramInfo.Psram_Clk_Set <= 133000000) {
+			PsramInfo.Psram_Latency_Set = 5;
+			PsramInfo.Psram_CSHI = Psram_APM_CSHI133;
+		} else if (PsramInfo.Psram_Clk_Set <= 166000000) {
+			PsramInfo.Psram_Latency_Set = 6;
+			PsramInfo.Psram_CSHI = Psram_APM_CSHI166;
+		} else if (PsramInfo.Psram_Clk_Set <= 200000000) {
+			PsramInfo.Psram_Latency_Set = 7;
+			PsramInfo.Psram_CSHI = Psram_APM_CSHI200;
+		} else if (PsramInfo.Psram_Clk_Set <= 250000000) {
+			PsramInfo.Psram_Latency_Set = 8;
+			PsramInfo.Psram_CSHI = Psram_APM_CSHI250;
+		}
+	}
+
+	// RTK_LOGI(TAG, "PSRAM Ctrl CLK: %lu Hz \n", PsramClk);
+}
+
+/**
+  * @brief  Fills each PSPHY_InitStruct member with its default value.
+  * @param  PSPHY_InitStruct: pointer to an PSPHY_InitStruct structure which will be initialized.
+  * @retval None
+  */
+void PSRAM_PHY_StructInit(PSPHY_InitTypeDef *PSPHY_InitStruct)
+{
+	// 0x04
+	PSPHY_InitStruct->PSRAMP_PRE_CAL_PHASE = 0x0; /* only for rtl now, default choose 1 on asic */
+	PSPHY_InitStruct->PSRAMP_CFG_CAL_JMIN = 0x2;
+	PSPHY_InitStruct->PSRAMP_CFG_CAL_JMAX = 0x3;
+	PSPHY_InitStruct->PSRAMP_CFG_CAL_J = 0x3;
+	PSPHY_InitStruct->PSRAMP_CFG_CAL_N = 0xA;
+
+	//0x18
+	PSPHY_InitStruct->PSRAMP_SW_RST_N = 0x1;
+	PSPHY_InitStruct->PSRAMP_LATENCY_TYPE = PSRSAM_FIX_LATENCY;	//0:variable latency 1:fix leatency
+	PSPHY_InitStruct->PSRAMP_RWDS_CHK_OPT = 0x1; //1:for fpga
+	PSPHY_InitStruct->PSRAMP_RWDS_PD_EN = 0x0; //0: for fpga
+	PSPHY_InitStruct->PSRAMP_CAL_RWDS_PHASE = 0x1;
+	if (PSPHY_InitStruct->PSRAMP_LATENCY_TYPE) {
+		PSPHY_InitStruct->PSRAMP_RFIFO_RDY_DLY = PSPHY_RFIFO_READY_DELAY_FIX;
+	} else {
+		PSPHY_InitStruct->PSRAMP_RFIFO_RDY_DLY = PSPHY_RFIFO_READY_DELAY_VL;
+
+	}
+}
+
+/**
+  * @brief Initializes the PSRAM phy according to the specified
+  *   parameters in the PSPHY_InitStruct
+  * @param  PSPHY_InitStruct: pointer to a PSPHY_InitStruct structure that
+  *   contains the configuration information for the specified PSRAM phy
+  * @retval None
+  */
+void PSRAM_PHY_Init(PSPHY_InitTypeDef *PSPHY_InitStruct)
+{
+
+	PSPHY_TypeDef *psram_phy = PSRAMPHY_DEV;
+
+	//0x04
+	psram_phy->PSPHY_CAL_PAR = PSPHY_PRE_CAL_PHASE(PSPHY_InitStruct->PSRAMP_PRE_CAL_PHASE) | \
+							   PSPHY_CFG_CAL_JMIN(PSPHY_InitStruct->PSRAMP_CFG_CAL_JMIN) | \
+							   PSPHY_CFG_CAL_JMAX(PSPHY_InitStruct->PSRAMP_CFG_CAL_JMAX) | \
+							   PSPHY_CFG_CAL_J(PSPHY_InitStruct->PSRAMP_CFG_CAL_J) | \
+							   PSPHY_CFG_CAL_N(PSPHY_InitStruct->PSRAMP_CFG_CAL_N);
+
+	//0x18
+	psram_phy->PSPHY_PHY_CTRL = PSPHY_PSRAM_SW_RST_N(PSPHY_InitStruct->PSRAMP_SW_RST_N) | \
+								PSPHY_RWDS_CHK_OPT(PSPHY_InitStruct->PSRAMP_RWDS_CHK_OPT) | \
+								PSPHY_RWDS_PD_EN(PSPHY_InitStruct->PSRAMP_RWDS_PD_EN) | \
+								PSPHY_LATENCY_TYPE(PSPHY_InitStruct->PSRAMP_LATENCY_TYPE) | \
+								PSPHY_CAL_RWDS_PHASE(PSPHY_InitStruct->PSRAMP_CAL_RWDS_PHASE) | \
+								PSPHY_RFIFO_RDY_DLY(PSPHY_InitStruct->PSRAMP_RFIFO_RDY_DLY);
+
+}
+
+void PSRAM_InfoDump(void)
+{
+	SPIC_TypeDef *psram_ctrl = PSRAMC_DEV;
+	PSPHY_TypeDef *psram_phy = PSRAMPHY_DEV;
+	RRAM_TypeDef *rram = RRAM_DEV;
+	u8 psramir0[2] = {0, 0};
+	u8 psramcr0[2] = {0, 0};
+	u8 psramcr1[2] = {0, 0};
+	u8 psram_type = rram->PSRAM_TYPE;
+
+	RTK_LOGI(TAG, "BDnum is 0x%x\n", ChipInfo_BDNum());
+
+	RTK_LOGI(TAG, "SSIENR\t0x%x=0x%x\n", &psram_ctrl->SSIENR, psram_ctrl->SSIENR);
+	RTK_LOGI(TAG, "CTRLR0\t0x%x=0x%x\n", &psram_ctrl->CTRLR0, psram_ctrl->CTRLR0);
+	RTK_LOGI(TAG, "BAUDR\t0x%x=0x%x\n", &psram_ctrl->BAUDR, psram_ctrl->BAUDR);
+	RTK_LOGI(TAG, "VALID_CMD\t0x%x=0x%x\n", &psram_ctrl->VALID_CMD, psram_ctrl->VALID_CMD);
+	RTK_LOGI(TAG, "CTRLR2\t0x%x=0x%x\n", &psram_ctrl->CTRLR2, psram_ctrl->CTRLR2);
+	RTK_LOGI(TAG, "DEVICE_INFO\t0x%x=0x%x\n", &psram_ctrl->DEVICE_INFO, psram_ctrl->DEVICE_INFO);
+	RTK_LOGI(TAG, "TPR0\t0x%x=0x%x\n", &psram_ctrl->TPR0, psram_ctrl->TPR0);
+	RTK_LOGI(TAG, "READ_FAST_SINGLE\t0x%x=0x%x\n", &psram_ctrl->READ_FAST_SINGLE, psram_ctrl->READ_FAST_SINGLE);
+	RTK_LOGI(TAG, "WRITE_SIGNLE\t0x%x=0x%x\n", &psram_ctrl->WRITE_SIGNLE, psram_ctrl->WRITE_SIGNLE);
+	RTK_LOGI(TAG, "AUTO_LENGTH\t0x%x=0x%x\n", &psram_ctrl->AUTO_LENGTH, psram_ctrl->AUTO_LENGTH);
+	RTK_LOGI(TAG, "USER_LENGTH\t0x%x=0x%x\n", &psram_ctrl->USER_LENGTH, psram_ctrl->USER_LENGTH);
+	RTK_LOGI(TAG, "AUTO_LENGTH2\t0x%x=0x%x\n", &psram_ctrl->AUTO_LENGTH2, psram_ctrl->AUTO_LENGTH2);
+	RTK_LOGI(TAG, "SR\t0x%x=0x%x\n", &psram_ctrl->SR, psram_ctrl->SR);
+
+	RTK_LOGI(TAG, "PSPHY_CAL_PAR\t0x%x=0x%x\n", &psram_phy->PSPHY_CAL_PAR, psram_phy->PSPHY_CAL_PAR);
+	RTK_LOGI(TAG, "PSPHY_PHY_CTRL\t0x%x=0x%x\n", &psram_phy->PSPHY_PHY_CTRL, psram_phy->PSPHY_PHY_CTRL);
+	RTK_LOGI(TAG, "PSPHY_DBG_SEL\t0x%x=0x%x\n", &psram_phy->PSPHY_DBG_SEL, psram_phy->PSPHY_DBG_SEL);
+
+	PSRAM_REG_Read(psram_type, 0x0, 2, psramir0, 0);
+	RTK_LOGI(TAG, "IR0[1]=0x%x\n", psramir0[1]);
+	RTK_LOGI(TAG, "IR0[0]=0x%x\n", psramir0[0]);
+	PSRAM_REG_Read(psram_type, 0x0, 2, psramcr0, 1);
+	RTK_LOGI(TAG, "CR0[1]=0x%x\n", psramcr0[1]);
+	RTK_LOGI(TAG, "CR0[0]=0x%x\n", psramcr0[0]);
+	PSRAM_REG_Read(psram_type, 0x1, 2, psramcr1, 1);
+	RTK_LOGI(TAG, "CR1[1]=0x%x\n", psramcr1[1]);
+	RTK_LOGI(TAG, "CR1[0]=0x%x\n", psramcr1[0]);
+
+}
+
+
+/**
+  * @brief Initializes the PSRAM controller according to the specified
+  *   parameters in the PSRAM_InitStruct
+  * @param  PSRAM_InitStruct: pointer to a PSRAM_InitTypeDef structure that
+  *   contains the configuration information for the specified PSRAM controller
+  * @retval None
+  */
+void PSRAM_CTRL_Init(void)
+{
+	SPIC_TypeDef *psram_ctrl = PSRAMC_DEV;
+
+	/* Disable psramc */
+	psram_ctrl->SSIENR = 0;
+
+	//0x00
+	psram_ctrl->CTRLR0 = MASK_DDR_EN | MASK_ADDR_CH | CK_MTIMES(0x1) | MASK_DATA_CH | MASK_CMD_CH;
+
+	//0x14
+	psram_ctrl->BAUDR = SCKDV(Psram_ClkDiv2);
+
+	//0x120
+	psram_ctrl->VALID_CMD = BIT_SEQ_WR_EN | BIT_SEQ_RD_EN | BIT_FRD_SINGLE | BIT_CTRLR0_CH;
+
+	//psram_ctrl->CTRLR2 &= ~BIT_FULL_WR;  //bit 13 = 0 need to disable,default = 0
+	//0x110
+	if (PsramInfo.Psram_Vendor == MCM_PSRAM_VENDOR_WB) {
+		psram_ctrl->CTRLR2 = BIT_SO_DNUM | TX_FIFO_ENTRY(0x5) | RX_FIFO_ENTRY(0x5) | BIT_DM_ACT | BIT_DIS_DM_CA | \
+							 WR_VL_EN(!PSRSAM_FIX_LATENCY) | RD_VL_EN(!PSRSAM_FIX_LATENCY) | RD_WEIGHT(0x2);
+		//0x134 waiting update typedefine
+		psram_ctrl->DEVICE_INFO = BIT_DATA_UNIT_2B | BIT_JEDEC_P2CMF | BIT_PSRAM | ATOM_SIZE(0x1) | BIT_RD_PAGE_EN | \
+								  BIT_WR_PAGE_EN | PAGE_SIZE(PsramInfo.Psram_Page_size);
+		psram_ctrl->TPR1 &= ~(MASK_CR_IDLE_WINDOW | MASK_CR_TPWR);
+		psram_ctrl->TPR0 = (CS_TCEM(Psram_Tcem_T85 * 1000 / PsramInfo.PSRAMC_Clk_Unit / 32)) | \
+						   (CS_SEQ_TIMEOUT(Psram_Seq_timeout)) | \
+						   (CS_ACTIVE_HOLD(Psram_WB_CSH)) | \
+						   (CS_H_WR_DUM_LEN(((PsramInfo.Psram_TRWR * 1000 + PsramInfo.PSRAMC_Clk_Unit - 1) / PsramInfo.PSRAMC_Clk_Unit - 2 - 3 - 1))) | \
+						   (CS_H_RD_DUM_LEN(((PsramInfo.Psram_TRWR * 1000 + PsramInfo.PSRAMC_Clk_Unit - 1) / PsramInfo.PSRAMC_Clk_Unit - 2 - 3 - 1)));
+		//0xe0
+		psram_ctrl->READ_FAST_SINGLE = FRD_CMD(WB_RD_CMD);
+		//0xf4
+		psram_ctrl->WRITE_SIGNLE = WR_CMD(WB_WR_CMD);
+		//0x11c
+		psram_ctrl->AUTO_LENGTH = AUTO_ADDR_LENGTH(0x5);
+		//0x118
+		psram_ctrl->USER_LENGTH = USER_ADDR_LENGTH(0x5) | USER_CMD_LENGHT(0x1);
+	} else {
+
+		//0x110
+		psram_ctrl->CTRLR2 = BIT_SO_DNUM | TX_FIFO_ENTRY(0x5) | RX_FIFO_ENTRY(0x5) | BIT_DM_ACT | \
+							 WR_VL_EN(!PSRSAM_FIX_LATENCY) | RD_VL_EN(!PSRSAM_FIX_LATENCY) | RD_WEIGHT(0x2);
+		//0x134 waiting update typedefine
+		psram_ctrl->DEVICE_INFO = BIT_PSRAM | ATOM_SIZE(0x1) | BIT_RD_PAGE_EN | \
+								  BIT_WR_PAGE_EN | PAGE_SIZE(PsramInfo.Psram_Page_size);
+		//0x138 waiting update typedefine
+		//CS_TCEM = 0 for seq performance
+		//todo
+		psram_ctrl->TPR0 = (CS_TCEM(Psram_Tcem_T85 * 1000 / PsramInfo.PSRAMC_Clk_Unit / 32)) | \
+						   (CS_SEQ_TIMEOUT(Psram_Seq_timeout)) | \
+						   (CS_ACTIVE_HOLD(Psram_APM_CSH)) | \
+						   (CS_H_WR_DUM_LEN(PsramInfo.Psram_CSHI * 1000 / PsramInfo.PSRAMC_Clk_Unit)) | \
+						   (CS_H_RD_DUM_LEN(PsramInfo.Psram_CSHI * 1000 / PsramInfo.PSRAMC_Clk_Unit));
+		psram_ctrl->READ_FAST_SINGLE = FRD_CMD(APM_RD_CMD);
+		psram_ctrl->WRITE_SIGNLE = WR_CMD(APM_WR_CMD);
+		//0x11c
+		psram_ctrl->AUTO_LENGTH = AUTO_ADDR_LENGTH(0x4);
+		//0x118
+		psram_ctrl->USER_LENGTH = USER_ADDR_LENGTH(0x4) | USER_CMD_LENGHT(0x2);
+	}
+
+
+	if (PSRSAM_FIX_LATENCY) {
+		//auto rd latency
+		psram_ctrl->AUTO_LENGTH |= RD_DUMMY_LENGTH(2 * 2 * PsramInfo.Psram_Latency_Set - 1) | \
+								   IN_PHYSICAL_CYC(PSPHY_RFIFO_READY_DELAY_FIX + 2);
+		//auto wr latency
+		psram_ctrl->AUTO_LENGTH2 = WR_DUMMY_LENGTH(2 * 2 * PsramInfo.Psram_Latency_Set - 2);
+
+		psram_ctrl->USER_LENGTH |= USER_RD_DUMMY_LENGTH(2 * 2 * PsramInfo.Psram_Latency_Set - 1);
+	} else {
+		//auto rd latency
+		psram_ctrl->AUTO_LENGTH |= RD_DUMMY_LENGTH(2 * PsramInfo.Psram_Latency_Set - 1) ;
+		//auto wr latency
+		psram_ctrl->AUTO_LENGTH2 = WR_DUMMY_LENGTH(2 * PsramInfo.Psram_Latency_Set - 2);
+		psram_ctrl->USER_LENGTH |= USER_RD_DUMMY_LENGTH(2 * PsramInfo.Psram_Latency_Set - 1);
+	}
+}
+
+
+
+void PSRAM_APM_DEVIC_Init(void)
+{
+	u8 mr0[2];
+	u8 mr4[2];
+	mr0[0] = PSRAM_READ_LATENCY_CODE(PsramInfo.Psram_Latency_Set - 3) | \
+			 PSRAM_LT_SELECT(PSRSAM_FIX_LATENCY) | \
+			 PSRAM_Drive_Strength(APM_Drive_Strength_100ohms); //0:variable latency 1:fix latency
+
+	mr4[0] = PSRAM_WRITE_LATENCY_CODE(APM_WR_INIT_LATENCY_SPEC[PsramInfo.Psram_Latency_Set - 3]);
+
+	mr0[1] = mr0[0];
+	mr4[1] = mr4[0];
+
+	PSRAM_REG_Write(MCM_PSRAM_VENDOR_APM, 0x0, 2, mr0);
+	PSRAM_REG_Write(MCM_PSRAM_VENDOR_APM, 0x4, 2, mr4);
+}
+
+void PSRAM_WB_DEVIC_Init(void)
+{
+	u8 data[2];
+	data[0] = PSRAM_WB_RESERVER | \
+			  PSRAM_WB_DRIVE_STRENGTH(WB_Drive_Strength_100ohms) | \
+			  PSRAM_WB_DPD_EN(WB_NORMAL_OPE);
+
+	data[1] = PSRAM_WB_BURST_LENGTH(WB_BURST_LEN_128B) | \
+			  PSRAM_WB_HyBURSE_EN | \
+			  PSRAM_WB_FIX_LATENCY_EN(PSRSAM_FIX_LATENCY) | \
+			  PSRAM_WB_INIT_LATENCY(PsramInfo.Psram_Latency_Code);
+
+	PSRAM_REG_Write(MCM_PSRAM_VENDOR_WB, PSRAM_WB_CR0, 2, data);
+}
+
+
+/**
+  * @brief Get APM/Winbond PSRAM register value
+  * @param  type: APM :0 Winbond:1
+  * @param  addr: APM/Winbond PSRAM register addr
+  * @param  read_len: read data length
+  * @param  read_data: read data output buf
+  * @retval None
+  */
+NON_DRAM_TEXT_SECTION
+void PSRAM_REG_Read(u8 type, u32 addr, u32 read_len, u8 *read_data, u32 CR)
+{
+	SPIC_TypeDef *psram_ctrl = PSRAMC_DEV;
+	u32 rx_num = 0;
+
+	/* Wait spic busy done before switch to user mode */
+	while (psram_ctrl->SR & BIT_BUSY);
+
+	/* Enter User Mode */
+	psram_ctrl->CTRLR0 |= BIT_USER_MODE;
+
+	/* Disable SSIENR to program control registers*/
+	psram_ctrl->SSIENR = 0;
+
+	/* Set RX_NDF: frame number of receiving data. TX_NDF should be set in both transmit mode and receive mode.
+		TX_NDF should be set to zero in receive mode to skip the TX_DATA phase. */
+	psram_ctrl->RX_NDF = RX_NDF(read_len);
+	psram_ctrl->TX_NDF = 0;
+	//RTK_LOGD(TAG, "RX_NDF = %p %lx\n", &(psram_ctrl->RX_NDF), psram_ctrl->RX_NDF);
+
+	//set rx mode
+	psram_ctrl->CTRLR0 |= TMOD(3);
+	//RTK_LOGD(TAG, "CTRLR0 = %p %lx\n", &(psram_ctrl->CTRLR0), psram_ctrl->CTRLR0);
+
+	/* set flash_cmd: write cmd to fifo */
+	if (type == MCM_PSRAM_VENDOR_APM) {
+		psram_ctrl->DR[0].BYTE = 0x40;
+		psram_ctrl->DR[0].BYTE = 0x40;
+	} else {
+		psram_ctrl->DR[0].BYTE = 0xe0;
+		psram_ctrl->DR[0].BYTE = 0x00;
+	}
+
+
+	if (CR) {
+		psram_ctrl->DR[0].BYTE = 0x01;
+	} else {
+		psram_ctrl->DR[0].BYTE = 0x00;    // IR reg read only
+	}
+
+	psram_ctrl->DR[0].BYTE = 0x00;
+	psram_ctrl->DR[0].BYTE = 0x00;
+
+	psram_ctrl->DR[0].BYTE = (u8)(addr & 0xFF);//addr
+
+
+	/* Enable SPI_FLASH  User Mode */
+	psram_ctrl->SSIENR = BIT_SPIC_EN;
+	while (psram_ctrl->SSIENR & BIT_SPIC_EN) {
+	};
+
+	/* read data */
+	rx_num = 0;
+
+	while (rx_num < read_len) {
+		read_data[rx_num] = psram_ctrl->DR[0].BYTE;
+		rx_num += 1;
+	}
+
+	/* Wait transfer complete. When complete, SSIENR[0] and CTRLR0[31] is cleared by HW automatically. */
+	while (psram_ctrl->SR & BIT_BUSY);
+
+	/* Restore to auto mode */
+	psram_ctrl->CTRLR0 &= ~BIT_USER_MODE;
+
+}
+
+/**
+  * @brief set APM/Winbond PSRAM register value
+  * @param  type: APM :0 Winbond:1
+  * @param  addr: PSRAM register addr
+  * @param  write_len: write data length
+  * @param  write_data: write data buf
+  * @retval None
+  */
+NON_DRAM_TEXT_SECTION
+void PSRAM_REG_Write(u8 type, u32 addr, u32 write_len, u8 *write_data)
+{
+	SPIC_TypeDef *psram_ctrl = PSRAMC_DEV;
+	u32 tx_num = 0;
+
+	/* Wait spic busy done before switch to user mode */
+	while (psram_ctrl->SR & BIT_BUSY);
+
+	/* Enter User Mode */
+	psram_ctrl->CTRLR0 |= BIT_USER_MODE;
+
+	/* Disable SSIENR to program control registers*/
+	psram_ctrl->SSIENR = 0;
+
+	//set tx mode
+	psram_ctrl->CTRLR0 &= ~(TMOD(3));
+
+	/* Set RX_NDF: frame number of receiving data. TX_NDF should be set in both transmit mode and receive mode.
+		TX_NDF should be set to zero in receive mode to skip the TX_DATA phase. */
+	psram_ctrl->RX_NDF = 0;
+	psram_ctrl->TX_NDF = TX_NDF(write_len);
+
+	/* set flash_cmd: write cmd to fifo */
+	if (type == MCM_PSRAM_VENDOR_APM) {
+
+		psram_ctrl->DR[0].BYTE = 0xc0;
+		psram_ctrl->DR[0].BYTE = 0xc0;
+	} else {
+
+		psram_ctrl->DR[0].BYTE = 0x60;
+		psram_ctrl->DR[0].BYTE = 0x00;
+	}
+
+	psram_ctrl->DR[0].BYTE = 0x01;
+	psram_ctrl->DR[0].BYTE = 0x00;
+	psram_ctrl->DR[0].BYTE = 0x00;
+
+	psram_ctrl->DR[0].BYTE = (u8)(addr & 0xFF);//addr
+
+	/* fill data */
+	for (tx_num = 0; tx_num < write_len; tx_num++) {
+		psram_ctrl->DR[0].BYTE = (u8) * (write_data + tx_num);
+	}
+
+	/* Enable SPI_FLASH  User Mode */
+	psram_ctrl->SSIENR = BIT_SPIC_EN;
+	while (psram_ctrl->SSIENR & BIT_SPIC_EN) {
+	};
+
+	/* Wait transfer complete. When complete, SSIENR[0] and CTRLR0[31] is cleared by HW automatically. */
+	while (psram_ctrl->SR & BIT_BUSY);
+
+	/* Restore to auto mode */
+	psram_ctrl->CTRLR0 &= ~BIT_USER_MODE;
+
+}
+
+/**
+  * @brief set APM PSRAM register value
+  * @param  cmd: APM PSRAM write mem cmd: 0x80 or 0xa0
+  * @param  addr: APM PSRAM register addr
+  * @param  write_len: write data length
+  * @param  write_data: write data buf
+  * @retval None
+  */
+
+void PSRAM_MEM_Write(u8 cmd, u32 addr, u32 write_len, u8 *write_data)
+{
+	SPIC_TypeDef *psram_ctrl = PSRAMC_DEV;
+	u32 tx_num = 0;
+	u32 txlen = write_len + (PsramInfo.Psram_Latency_Set - 1) * 2;
+
+	/* Wait spic busy done before switch to user mode */
+	while (psram_ctrl->SR & BIT_BUSY);
+
+	/* Enter User Mode */
+	psram_ctrl->CTRLR0 |= BIT_USER_MODE;
+
+	/* Disable SSIENR to program control registers*/
+	psram_ctrl->SSIENR = 0;
+
+	//set tx mode
+	psram_ctrl->CTRLR0 &= ~(TMOD(3));
+	RTK_LOGI(TAG, "CTRLR0 = %p %lx\n", &(psram_ctrl->CTRLR0), psram_ctrl->CTRLR0);
+
+	/* Set RX_NDF: frame number of receiving data. TX_NDF should be set in both transmit mode and receive mode.
+		TX_NDF should be set to zero in receive mode to skip the TX_DATA phase. */
+	psram_ctrl->RX_NDF = 0;
+	psram_ctrl->TX_NDF = TX_NDF(txlen);
+
+	addr = addr - PSRAM_BASE;
+
+	/* set flash_cmd: write cmd to fifo */
+	psram_ctrl->DR[0].BYTE = cmd;
+	psram_ctrl->DR[0].BYTE = cmd;
+	psram_ctrl->DR[0].BYTE = (u8)((addr & 0xFF000000) >> 24);
+	psram_ctrl->DR[0].BYTE = (u8)((addr & 0xFF0000) >> 16);
+	psram_ctrl->DR[0].BYTE = (u8)((addr & 0xFF00) >> 8);
+	psram_ctrl->DR[0].BYTE = (u8)(addr & 0xFF);
+
+	/* fill data */
+	for (tx_num = 0; tx_num < (PsramInfo.Psram_Latency_Set - 1) * 2; tx_num++) {
+		psram_ctrl->DR[0].BYTE = 0x0;
+	}
+
+	/* fill data */
+	for (tx_num = 0; tx_num < write_len; tx_num++) {
+		psram_ctrl->DR[0].BYTE = (u8) * (write_data + tx_num);
+	}
+
+	/* Enable SPI_FLASH  User Mode */
+	psram_ctrl->SSIENR = BIT_SPIC_EN;
+
+	while (psram_ctrl->SSIENR & BIT_SPIC_EN) {
+	};
+
+	/* Wait transfer complete. When complete, SSIENR[0] and CTRLR0[31] is cleared by HW automatically. */
+	while (psram_ctrl->SR & BIT_BUSY);
+
+	/* Restore to auto mode */
+	psram_ctrl->CTRLR0 &= ~BIT_USER_MODE;
+
+}
+
+void PSRAM_calwindow(int window_start, int window_end, PCAL_InitTypeDef *PCAL_InitStruct)
+{
+	u32 suggest_phase = 0;
+	int window_size = 0;
+	int windowt_size, windowt_start, windowt_end;
+	int JMAX_val = 0;
+	int J_val = 0;
+	int N_val = 0;
+	int i, head, tail;
+	u32 phase;
+	for (i = 0; i < 4; i++) {
+		head = i * 16;
+		tail = head + 31;
+		phase = BIT(i);
+		windowt_start = head > window_start ? head : window_start;
+		windowt_end = tail < window_end ? tail : window_end;
+		windowt_size = windowt_end - windowt_start + 1;
+		if (windowt_size > window_size) {
+
+			window_size = windowt_size;
+			N_val = (windowt_start + windowt_end - head - head) / 2;
+			JMAX_val = (windowt_end - windowt_start) / 2 - 2;
+			J_val = (windowt_end - windowt_start) / 2 - 2;
+			suggest_phase = phase;
+		}
+	}
+
+	if (window_size > PCAL_InitStruct->window_size) {
+		PCAL_InitStruct->window_size = window_size;
+		PCAL_InitStruct->CAL_JMAX = JMAX_val;
+		PCAL_InitStruct->CAL_J = J_val;
+		PCAL_InitStruct->CAL_N = N_val;
+		PCAL_InitStruct->phase = suggest_phase;
+	}
+
+}
+
+/**
+  * @brief PSRAM FW calibration function
+  * @retval None
+  * @note cache will be disable during calibration
+  */
+bool PSRAM_calibration(u32 log_en)
+{
+	PSPHY_TypeDef *psram_phy = PSRAMPHY_DEV;
+
+	u32 caltempN = 0;
+	u32 phase = 0;
+	u32 tempPHYPara = psram_phy->PSPHY_CAL_PAR & (~PSPHY_MASK_CFG_CAL_N) & (~PSPHY_MASK_PRE_CAL_PHASE);
+	const u32 *tempdatawr = PSRAM_CALIB_PATTERN;
+	u32 tempdatard[6] = {0, 0, 0, 0, 0, 0};
+	int window_start = -1;
+	int window_end = -1;
+	int window_size = 0;
+
+	int windowt_start = -1;
+	int windowt_size = 0;
+	int windowt_end = -1;
+
+	int phase_cnt = -1;
+
+	/*Disable HW calibration*/
+	psram_phy->PSPHY_CAL_CTRL &= (~PSPHY_BIT_CFG_CAL_EN);
+	for (phase = 0x0; phase <= 0x8; phase = (phase == 0 ? phase + 1 : phase * 2)) {
+		windowt_size = 0;
+		windowt_start = -1;
+		windowt_end = -1;
+		if (log_en) {
+			RTK_LOGI(TAG, "===phase %lx =====\n", phase);
+		}
+		for (caltempN = 0; caltempN < 32; caltempN++) {
+			psram_phy->PSPHY_CAL_PAR = tempPHYPara | caltempN | PSPHY_PRE_CAL_PHASE(phase);
+			/*PG needs to be recalibrated when the temperature changes sharply.
+			To avoid accessing the secure address, the calibration address starts from __km4_bd_psram_start__.*/
+			for (int i = 0; i < 6; i += 1) {
+				HAL_WRITE32((u32)__km4_bd_psram_start__, i * 0x50000, tempdatawr[i]);
+				DCache_CleanInvalidate((u32)__km4_bd_psram_start__ + i * 0x50000, CACHE_LINE_SIZE);
+				tempdatard[i] = HAL_READ32((u32)__km4_bd_psram_start__, i * 0x50000);
+			}
+
+			if (_memcmp(tempdatard, PSRAM_CALIB_PATTERN, 24) == 0) {
+				if (log_en) {
+					RTK_LOGI(TAG, "ok %lx %lx %lx %lx %lx %lx %lx\n", caltempN, tempdatard[0], tempdatard[1], tempdatard[2], tempdatard[3], tempdatard[4], tempdatard[5]);
+				}
+				if (windowt_start < 0) {
+					windowt_start = caltempN;
+				}
+				windowt_end = windowt_start + windowt_size;
+				windowt_size ++;
+
+				if (caltempN == (32 - 1)) {
+					if (windowt_size > window_size) {
+						window_start = windowt_start;
+						window_end = windowt_end;
+						window_size = windowt_size;
+						phase_cnt = phase;
+					}
+				}
+			} else {
+				if (log_en) {
+					RTK_LOGI(TAG, "fail %lx %lx %lx %lx %lx %lx %lx\n", caltempN, tempdatard[0], tempdatard[1], tempdatard[2], tempdatard[3], tempdatard[4], tempdatard[5]);
+				}
+				if (windowt_start >= 0) {
+					if (windowt_size > window_size) {
+						window_start = windowt_start;
+						window_end = windowt_end;
+						window_size = windowt_size;
+						phase_cnt = phase;
+
+					}
+					windowt_start = -1;
+					windowt_size = 0;
+					windowt_end = -1;
+				}
+			}
+		}
+	}
+
+
+	RTK_LOGI(TAG, "CalNmin = %x CalNmax = %x WindowSize = %x phase: %x \n", window_start, window_end, window_size, phase_cnt);
+
+	if ((window_size) < 9) {
+		return FALSE;
+	}
+	tempPHYPara &= (~0xfffff);
+	tempPHYPara |= PSPHY_CFG_CAL_JMAX((window_end - window_start) / 2 - 2) | \
+				   PSPHY_CFG_CAL_J((window_end - window_start) / 2 - 2)	| \
+				   PSPHY_CFG_CAL_N((window_end + window_start) / 2) | \
+				   PSPHY_PRE_CAL_PHASE(phase_cnt);
+
+	psram_phy->PSPHY_CAL_PAR = tempPHYPara;
+
+	/*start HW calibration*/
+	psram_phy->PSPHY_CAL_CTRL |= PSPHY_BIT_CFG_CAL_EN;
+
+	return TRUE;
+
+}
+
+
+/**
+  * @brief  set psram into half sleep mode.
+  * @param  type: 0:apm psram type 1: winbond psram type
+  * @retval None
+  * @note None
+  */
+NON_DRAM_TEXT_SECTION
+void set_psram_sleep_mode(void)
+{
+	u8 psram_halfsleep[2];
+	u8 mr4[2];
+
+	RRAM_TypeDef *rram = RRAM_DEV;
+	PSPHY_TypeDef *psram_phy = PSRAMPHY_DEV;
+	psram_phy->PSPHY_CAL_CTRL = PSRAM_MASK_CAL_ITT;
+
+	rram->psram_backup[0] = HAL_READ32((u32)__km4_bd_psram_start__, 0x0);
+	rram->psram_backup[1] = HAL_READ32((u32)__km4_bd_psram_start__, 0x50000);
+	rram->psram_backup[2] = HAL_READ32((u32)__km4_bd_psram_start__, 0x100000);
+	rram->psram_backup[3] = HAL_READ32((u32)__km4_bd_psram_start__, 0x150000);
+	rram->psram_backup[4] = HAL_READ32((u32)__km4_bd_psram_start__, 0x200000);
+	rram->psram_backup[5] = HAL_READ32((u32)__km4_bd_psram_start__, 0x250000);
+
+	if (rram->PSRAM_TYPE == MCM_PSRAM_VENDOR_APM) {
+		psram_halfsleep[0] = 0xF0;
+		psram_halfsleep[1] = 0xF0;
+
+		/*enable apm slow refresh*/
+		PSRAM_REG_Read(MCM_PSRAM_VENDOR_APM, 0x4, 2, mr4, 1);
+		mr4[0] |= PSRAM_ENABLE_SLOW_REFRESH;
+		mr4[1] = mr4[0];
+		PSRAM_REG_Write(MCM_PSRAM_VENDOR_APM, 0x4, 2, mr4);
+		PSRAM_REG_Write(MCM_PSRAM_VENDOR_APM, 0x06, 2, psram_halfsleep);
+
+	} else {
+		psram_halfsleep[0] = 0xFF;
+		psram_halfsleep[1] = 0x20;
+
+		PSRAM_REG_Write(MCM_PSRAM_VENDOR_WB, 0x1, 2, psram_halfsleep);
+	}
+
+}
+
+/**
+  * @brief  Wake PSRAM from half sleep mode.
+  * @param  type: 0:apm psram type 1: winbond psram type
+  * @retval None
+  * @note None
+  */
+_OPTIMIZE_NONE_
+NON_DRAM_TEXT_SECTION
+void set_psram_wakeup_mode(void)
+{
+	u32 temp, rdata;
+	u8 mr4[2];
+	u8 psram_type;
+
+	RRAM_TypeDef *rram = RRAM_DEV;
+	PSPHY_TypeDef *psram_phy = PSRAMPHY_DEV;
+	SPIC_TypeDef *psram_ctrl = PSRAMC_DEV;
+	psram_type = rram->PSRAM_TYPE;
+
+	/*1. auto read , trigger psram to exit sleep mode*/
+	DCache_Invalidate((u32)__km4_bd_psram_start__, 32);
+	rdata = HAL_READ32((u32)__km4_bd_psram_start__, 0);
+
+	/* 2. when PG wakeup, fisrt read will cause phy hang, set PSPHY_PHY_INFO to return work correctly*/
+	temp = psram_phy->PSPHY_PHY_INFO;
+	psram_phy->PSPHY_PHY_INFO = temp;
+
+	/*3. wait for Txhs until psram exit sleep mode*/
+	if (psram_type == MCM_PSRAM_VENDOR_APM) {
+		DelayUs(150);
+	} else if (psram_type == MCM_PSRAM_VENDOR_WB) {
+		DelayUs(100);
+	}
+
+	/* 4. read again. */
+	DCache_Invalidate((u32)__km4_bd_psram_start__, 32);
+	rdata = HAL_READ32((u32)__km4_bd_psram_start__, 0);
+
+	/* 5. Check if the window has changed. */
+	if (PSRAM_CHECK_INT(psram_phy->PSPHY_CAL_CTRL)) {
+		rdata = psram_phy->PSPHY_CAL_CTRL;
+		psram_phy->PSPHY_CAL_CTRL = rdata;
+		PSRAM_calibration(DISABLE);
+		HAL_WRITE32((u32)__km4_bd_psram_start__, 0x0, rram->psram_backup[0]);
+		HAL_WRITE32((u32)__km4_bd_psram_start__, 0x50000, rram->psram_backup[1]);
+		HAL_WRITE32((u32)__km4_bd_psram_start__, 0x100000, rram->psram_backup[2]);
+		HAL_WRITE32((u32)__km4_bd_psram_start__, 0x150000, rram->psram_backup[3]);
+		HAL_WRITE32((u32)__km4_bd_psram_start__, 0x200000, rram->psram_backup[4]);
+		HAL_WRITE32((u32)__km4_bd_psram_start__, 0x250000, rram->psram_backup[5]);
+	}
+
+	/*6. backfill the value of the register*/
+	psram_ctrl->TPR1 &= ~(MASK_CR_IDLE_WINDOW | MASK_CR_TPWR);
+
+	/*7. disable apm slow refresh*/
+	if (psram_type == MCM_PSRAM_VENDOR_APM) {
+		PSRAM_REG_Read(MCM_PSRAM_VENDOR_APM, 0x4, 2, mr4, 1);
+		mr4[0] &= ~PSRAM_ENABLE_SLOW_REFRESH;
+		mr4[1] = mr4[0];
+		PSRAM_REG_Write(MCM_PSRAM_VENDOR_APM, 0x4, 2, mr4);
+	}
+}
diff --git a/ameba/amebadplus/source/fwlib/ram_common/ameba_qspi.c b/ameba/amebadplus/source/fwlib/ram_common/ameba_qspi.c
new file mode 100644
index 00000000..33f14bc5
--- /dev/null
+++ b/ameba/amebadplus/source/fwlib/ram_common/ameba_qspi.c
@@ -0,0 +1,386 @@
+/*
+ * Copyright (c) 2024 Realtek Semiconductor Corp.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "ameba_soc.h"
+#include "os_wrapper.h"
+
+static const char *const TAG = "QSPI";
+static struct GDMA_CH_LLI *qspi_gdma_lli;
+
+/** @addtogroup Ameba_Periph_Driver
+  * @{
+  */
+
+/** @defgroup QSPI
+* @brief QSPI driver modules
+* @{
+*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup QSPI_Exported_Functions QSPI Exported Functions
+  * @{
+  */
+
+/**
+  * @brief  Initialize QSPI to user mode.
+  * @param  None.
+  * @retval None.
+  */
+void QSPI_Init(void)
+{
+	/* set cs and baudrate */
+	QSPI->SSIENR = 0;
+	QSPI->SER = BIT_SER;
+	QSPI->BAUDR = 1;
+
+	/* enter user mode */
+	QSPI->CTRLR0 |= BIT_USER_MODE;
+	QSPI->CTRLR0 |= BIT_SPI_DREIR_R_DIS;
+
+	/* user mode is entered after auto cmd is done, which means if SPIC BUSY=1, HW will not write Ctrl0 */
+	while (!(QSPI->CTRLR0 & BIT_USER_MODE));
+}
+
+/**
+  * @brief  Initialize QSPI_CmdAddrInfo structure.
+  * @param  info: cmd and addr info given by user.
+  * @retval None.
+  */
+void QSPI_StructInit(QSPI_CmdAddrInfo *info)
+{
+	info->cmd_length = 1;
+	info->addr_length = 0;
+	info->cmd_ch = 0;
+	info->addr_ch = 0;
+	info->data_ch = 0;
+	info->ddr_en = 0;
+	info->rx_dummy_cycle = 0;
+}
+
+/**
+  * @brief  Set baud value to divide clock.
+  * @param  div: actual QSPI clock = bus_clk/(2 * div).
+  * @retval None.
+  */
+void QSPI_SetBaud(u32 div)
+{
+	QSPI->BAUDR = div;
+}
+
+
+/**
+  * @brief  Set SO_DUM value to determine if sdo & sdi use same line.
+  * @param  val: val = 0 means use same line, other value means use different line.
+  * @retval None.
+  */
+void QSPI_SO_DNUM(u32 val)
+{
+	if (val == 0) {
+		QSPI->CTRLR2 &= ~(BIT_SO_DNUM);
+	} else {
+		QSPI->CTRLR2 |= BIT_SO_DNUM;
+	}
+}
+
+
+/**
+  * @brief  Write data by CPU according to the given parameter.
+  * @param  info: cmd and addr info given by user.
+  *         data: data to transmit.
+  *         len: transmit data length.
+  * @retval None.
+  */
+void QSPI_Write(QSPI_CmdAddrInfo *info, u8 *data, u32 len)
+{
+	u32 reg, i;
+	QSPI->SER = BIT_SER;
+
+	/* Disable QSPI */
+	QSPI->SSIENR = 0;
+
+	QSPI->CTRLR0 &= ~MASK_DDR_EN;
+	QSPI->CTRLR0 |= DDR_EN(info->ddr_en);
+
+	/* Set Channel number */
+	QSPI->CTRLR0 &= ~(TMOD(3) | CMD_CH(3) | ADDR_CH(3) | DATA_CH(3));
+	QSPI->CTRLR0 |= (CMD_CH(info->cmd_ch) | ADDR_CH(info->addr_ch) | DATA_CH(info->data_ch));
+
+	/* Set tx mode */
+	QSPI->CTRLR0 &= ~(TMOD(3));
+
+	/* Set cmd and addr length */
+	reg = QSPI->USER_LENGTH & ~(MASK_USER_ADDR_LENGTH | MASK_USER_CMD_LENGHT);
+	QSPI->USER_LENGTH = reg | USER_ADDR_LENGTH(info->addr_length) | USER_CMD_LENGHT(info->cmd_length);
+
+	/* Set tx length */
+	QSPI->RX_NDF = 0;
+	QSPI->TX_NDF = TX_NDF(len);
+
+	/* Send cmd */
+	for (i = 0; i < info->cmd_length; i++) {
+		QSPI->DR[0].BYTE = info->cmd[i];
+	}
+
+	/* Send addr */
+	for (i = 0; i < info->addr_length; i++) {
+		QSPI->DR[0].BYTE = info->addr[i];
+	}
+
+	/* Enable QSPI */
+	QSPI->SSIENR = BIT_SPIC_EN;
+
+	/* Send data */
+	for (i = 0; i < len;) {
+		if (QSPI->SR & BIT_TFNF) {
+			QSPI->DR[0].BYTE = data[i];
+			i++;
+		}
+	}
+
+	/* Wait bus busy */
+	while (QSPI->SR & BIT_BUSY);
+
+	/* Disable QSPI */
+	QSPI->SSIENR = 0;
+}
+
+/**
+  * @brief  Read data by CPU according to the given parameter.
+  * @param  info: cmd and addr info given by user.
+  *         data: pointer to recevie data.
+  *         len: receive data length.
+  * @retval None.
+  */
+void QSPI_Read(QSPI_CmdAddrInfo *info, u8 *data, u32 len)
+{
+	u32 reg, i;
+	u32 rd_num = 0;
+
+	/* Disable QSPI */
+	QSPI->SSIENR = 0;
+
+	/* Set Channel number */
+	QSPI->CTRLR0 &= ~(CMD_CH(3) | ADDR_CH(3) | DATA_CH(3));
+	QSPI->CTRLR0 |= (CMD_CH(info->cmd_ch) | ADDR_CH(info->addr_ch) | DATA_CH(info->data_ch));
+
+	/* Set rx mode */
+	QSPI->CTRLR0 |= TMOD(3);
+
+	/* Set rx length */
+	QSPI->RX_NDF = RX_NDF(len);
+	QSPI->TX_NDF = 0;
+
+	/* Set cmd and addr and dummy cycle length */
+	reg = QSPI->USER_LENGTH & ~(MASK_USER_ADDR_LENGTH | MASK_USER_CMD_LENGHT);
+	QSPI->USER_LENGTH = reg | USER_ADDR_LENGTH(info->addr_length) | USER_CMD_LENGHT(info->cmd_length)
+						| USER_RD_DUMMY_LENGTH(info->rx_dummy_cycle * 2);
+
+	/* Send cmd */
+	for (i = 0; i < info->cmd_length; i++) {
+		QSPI->DR[0].BYTE = info->cmd[i];
+	}
+
+	/* Send addr */
+	for (i = 0; i < info->addr_length; i++) {
+		QSPI->DR[0].BYTE = info->addr[i];
+	}
+
+	/* Enable QSPI */
+	QSPI->SSIENR = BIT_SPIC_EN;
+
+	while (rd_num < len) {
+		if (QSPI->SR & BIT_RFNE) {
+			data[rd_num] = QSPI->DR[0].BYTE;
+			rd_num ++;
+		}
+	}
+
+	/* Disable QSPI */
+	QSPI->SSIENR = 0;
+}
+
+/**
+  * @brief  Write data according to the given parameter through PPE or GDMA. User should
+  *            enable PPE to QSPI or GDMA to QSPI handshake to start data transfer.
+  * @param  info: cmd and addr info given by user.
+  *         len: transmit data length.
+  * @retval None.
+  */
+void QSPI_WriteStart(QSPI_CmdAddrInfo *info, u32 len)
+{
+	u32 reg, i;
+	QSPI->SER = BIT_SER;
+
+	/* Disable QSPI */
+	QSPI->SSIENR = 0;
+
+	QSPI->CTRLR0 &= ~MASK_DDR_EN;
+	QSPI->CTRLR0 |= DDR_EN(info->ddr_en);
+
+	/* Set Channel number */
+	QSPI->CTRLR0 &= ~(TMOD(3) | CMD_CH(3) | ADDR_CH(3) | DATA_CH(3));
+	QSPI->CTRLR0 |= (CMD_CH(info->cmd_ch) | ADDR_CH(info->addr_ch) | DATA_CH(info->data_ch));
+
+	/* Set tx mode */
+	QSPI->CTRLR0 &= ~(TMOD(3));
+
+	/* Set cmd and addr length */
+	reg = QSPI->USER_LENGTH & ~(MASK_USER_ADDR_LENGTH | MASK_USER_CMD_LENGHT);
+	QSPI->USER_LENGTH = reg | USER_ADDR_LENGTH(info->addr_length) | USER_CMD_LENGHT(info->cmd_length);
+
+	/* Set tx length */
+	QSPI->RX_NDF = 0;
+	QSPI->TX_NDF = TX_NDF(len);
+
+	/* DMA configuration*/
+	QSPI->DMACR = 2;
+	QSPI->DMATDLR = 16;
+
+	/* Send cmd */
+	for (i = 0; i < info->cmd_length; i++) {
+		QSPI->DR[0].BYTE = info->cmd[i];
+	}
+
+	/* Send addr */
+	for (i = 0; i < info->addr_length; i++) {
+		QSPI->DR[0].BYTE = info->addr[i];
+	}
+
+	/* Enable QSPI */
+	QSPI->SSIENR = BIT_SPIC_EN;
+}
+
+
+/**
+  * @brief  User could use this to disable QSPI After PPE or GDMA transfer complete.
+  * @param  None.
+  * @retval None.
+  */
+void QSPI_WriteEnd(void)
+{
+	/* Wait bus busy */
+	while (QSPI->SR & BIT_BUSY);
+
+	/* Disable QSPI */
+	QSPI->SSIENR = 0;
+}
+
+
+/**
+  * @brief  Init data transfer from GDMA to QSPI. If size exceed GDMA max block size, use GDMA linklist function.
+  * @param  GDMA_InitStruct: pointer to a GDMA_InitTypeDef structure that contains
+  *         the configuration information for the GDMA peripheral.
+  * @param  CallbackData: GDMA callback data.
+  * @param  CallbackFunc: GDMA callback function.
+  * @param  pbuf: data buffer send to QSPI. Must be 4-bytes aligned.
+  * @param  size: buffer size;
+  * @retval   TRUE/FLASE
+  */
+int QSPI_GDMAInit(GDMA_InitTypeDef *GDMA_InitStruct,
+				  IRQ_FUN CallbackFunc,
+				  void *CallbackData,
+				  u8 *Pbuf,
+				  u32 Size)
+{
+	u8 GdmaChnl;
+	u32 blocksize = 65535 * 4;   //GDMA max block size 65535, data width 4B
+	u32 blockcnt = (Size / blocksize) + 1;
+	u32 llisize;
+
+	GdmaChnl = GDMA_ChnlAlloc(0, (IRQ_FUN)CallbackFunc, (u32)CallbackData, INT_PRI_HIGHEST);
+	if (GdmaChnl == 0xFF) {
+		/* No Available DMA channel */
+		RTK_LOGE(TAG, "Alloc dma channel fail\n");
+		return FALSE;
+	}
+
+	/* Set QSPI hw handshake to GDMA */
+	HAL_WRITE32(SYSTEM_CTRL_BASE, REG_LSYS_ECO_CTRL, HAL_READ32(SYSTEM_CTRL_BASE, REG_LSYS_ECO_CTRL) | BIT_QSPI_HW_HANDSHAKE_SEL);
+
+	_memset((void *)GDMA_InitStruct, 0, sizeof(GDMA_InitTypeDef));
+	GDMA_InitStruct->MuliBlockCunt = 0;
+	GDMA_InitStruct->MaxMuliBlock  = blockcnt;
+	GDMA_InitStruct->GDMA_DIR     = TTFCMemToPeri;
+	GDMA_InitStruct->GDMA_DstHandshakeInterface = GDMA_HANDSHAKE_INTERFACE_SPIC_TX;
+	GDMA_InitStruct->GDMA_DstAddr = (u32) & (QSPI->DR[0].BYTE);
+	GDMA_InitStruct->GDMA_Index   = 0;
+	GDMA_InitStruct->GDMA_ChNum   = GdmaChnl;
+	GDMA_InitStruct->GDMA_IsrType = (TransferType | ErrType);
+	GDMA_InitStruct->GDMA_DstMsize = MsizeFour;
+	GDMA_InitStruct->GDMA_DstDataWidth = TrWidthFourBytes;
+	GDMA_InitStruct->GDMA_DstInc = NoChange;
+	GDMA_InitStruct->GDMA_SrcInc = IncType;
+	/* 4-bytes aligned, move 4 bytes each transfer */
+	GDMA_InitStruct->GDMA_SrcMsize   = MsizeFour;
+	GDMA_InitStruct->GDMA_SrcDataWidth = TrWidthFourBytes;
+	GDMA_InitStruct->GDMA_BlockSize = Size >> 2;
+	GDMA_InitStruct->GDMA_SrcAddr = (u32)(Pbuf);
+
+	if (blockcnt > 1) {
+		GDMA_InitStruct->GDMA_LlpSrcEn = 1;
+		GDMA_InitStruct->GDMA_LlpDstEn = 1;
+	} else {
+		GDMA_InitStruct->GDMA_LlpSrcEn = 0;
+		GDMA_InitStruct->GDMA_LlpDstEn = 0;
+	}
+
+	GDMA_Init(GDMA_InitStruct->GDMA_Index, GDMA_InitStruct->GDMA_ChNum, GDMA_InitStruct);
+
+	/* Note that GDMA max block size is 65536*4. If display buffer is exceed it, GDMA linklist function should be used.
+	   GDMA multi-block function is not suitable because it need extra interrupt for each block but we need only a
+	   transfer done interrupt. */
+	if (blockcnt > 1) {
+		llisize = blockcnt * sizeof(struct GDMA_CH_LLI);
+		qspi_gdma_lli = (struct GDMA_CH_LLI *) rtos_mem_malloc(llisize);
+		_memset(qspi_gdma_lli, 0, llisize);
+
+		for (u32 i = 0; i < blockcnt; i++) {
+			qspi_gdma_lli[i].LliEle.Sarx = ((u32)Pbuf) + blocksize * i;
+			qspi_gdma_lli[i].LliEle.Darx = (u32) & (QSPI->DR[0].BYTE);
+
+			if (i != (blockcnt - 1)) {
+				qspi_gdma_lli[i].BlockSize = (blocksize) >>  GDMA_InitStruct->GDMA_SrcDataWidth;
+				qspi_gdma_lli[i].pNextLli = &qspi_gdma_lli[i + 1];
+			} else {
+				qspi_gdma_lli[i].BlockSize = (Size - i * blocksize) >>  GDMA_InitStruct->GDMA_SrcDataWidth;
+				qspi_gdma_lli[i].pNextLli = NULL;
+			}
+		}
+		GDMA_SetLLP(GDMA_InitStruct->GDMA_Index, GDMA_InitStruct->GDMA_ChNum, GDMA_InitStruct->MaxMuliBlock, qspi_gdma_lli, 0);
+	}
+
+	return TRUE;
+}
+
+/**
+  * @brief  Deinit GDMA used by QSPI.
+  * @param  GDMA_InitStruct: pointer to a GDMA_InitTypeDef structure that contains
+  *         the configuration information for the GDMA peripheral.
+  * @retval   TRUE/FLASE
+  */
+int QSPI_GDMADeinit(GDMA_InitTypeDef *GDMA_InitStruct)
+{
+	GDMA_ChnlFree(GDMA_InitStruct->GDMA_Index, GDMA_InitStruct->GDMA_ChNum);
+	GDMA_Cmd(GDMA_InitStruct->GDMA_Index, GDMA_InitStruct->GDMA_ChNum, DISABLE);
+
+	if (qspi_gdma_lli) {
+		rtos_mem_free(qspi_gdma_lli);
+	}
+
+	return TRUE;
+}
+
+
+/**
+  * @brief  start data transfer from GDMA to QSPI.
+  * @param  GDMA_InitStruct: pointer to a GDMA_InitTypeDef structure that contains
+  *         the configuration information for the GDMA peripheral.
+  * @retval None.
+  */
+void QSPI_GDMAStart(GDMA_InitTypeDef *GDMA_InitStruct)
+{
+	GDMA_Cmd(GDMA_InitStruct->GDMA_Index, GDMA_InitStruct->GDMA_ChNum, ENABLE);
+}
diff --git a/ameba/amebadplus/source/fwlib/ram_common/ameba_sdio.c b/ameba/amebadplus/source/fwlib/ram_common/ameba_sdio.c
new file mode 100644
index 00000000..1334bdb5
--- /dev/null
+++ b/ameba/amebadplus/source/fwlib/ram_common/ameba_sdio.c
@@ -0,0 +1,363 @@
+/*
+ * Copyright (c) 2024 Realtek Semiconductor Corp.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "ameba_soc.h"
+/** @addtogroup Ameba_Periph_Driver
+  * @{
+  */
+
+/** @defgroup SDIO
+  * @brief SDIO driver modules
+  * @{
+  */
+
+/** @defgroup SDIO_Exported_Functions SDIO Exported Functions
+  * @{
+  */
+
+/**
+  * @brief  Fills each SDIO_InitStruct member with its default value.
+  * @param  SDIO_InitStruct: pointer to a SDIO_InitTypeDef structure which will be
+  *         initialized.
+  * @retval None
+  */
+void SDIO_StructInit(SDIO_InitTypeDef *SDIO_InitStruct)
+{
+	/* TXBD */
+	SDIO_InitStruct->TXBD_BAR = (u32)NULL; /* init txbd_bar */
+	SDIO_InitStruct->TXBD_RING_SIZE = 20; /* init TXBD ring size */
+	SDIO_InitStruct->TX_BUFFER_SIZE = 0xFF; /* init txbuf_size */
+
+	/* RXBD */
+	SDIO_InitStruct->RXBD_BAR = (u32)NULL; /* init rxbd_bar reg */
+	SDIO_InitStruct->RXBD_RING_SIZE = 32; /* init rxbd ring size */
+	SDIO_InitStruct->RXBD_FREE_TH = 5; /* init AHB rx_blk_size */
+}
+
+/**
+  * @brief  Initializes the SDIO registers according to the specified parameters
+  *         in SDIO_InitStruct. Note that pinmux function and CCCR(if need) should be
+  *         configured before this function.
+  * @param  SDIO_InitStruct: pointer to a SDIO_InitTypeDef structure that contains
+  *         the configuration information for the SDIO peripheral.
+  * @retval None
+  */
+void SDIO_Init(SDIO_TypeDef *SDIO, SDIO_InitTypeDef *SDIOInit_Struct)
+{
+	UNUSED(SDIO);
+
+	u16 Temp = 0;
+
+	/* Set PID to 0x8722 */
+	HAL_WRITE16(SDIO_CCCR_REG_BASE, MANF_PID, 0x8722);
+
+	/* CCCR Autoload done */
+	HAL_WRITE8(SDIO_REG_BASE, REG_SPDIO_CPU_IND,
+			   HAL_READ8(SDIO_REG_BASE, REG_SPDIO_CPU_IND) | BIT_SYSTEM_READEE_DONE);
+
+	/* SDIO pinmux funtion enable */
+	HAL_WRITE32(SYSTEM_CTRL_BASE, REG_LSYS_USB_SDIO_CTRL,
+				HAL_READ32(SYSTEM_CTRL_BASE, REG_LSYS_USB_SDIO_CTRL) | LSYS_BIT_SDD_PMUX_FEN);
+
+	/* Reset SDIO DMA */
+	HAL_WRITE8(SDIO_REG_BASE, REG_SPDIO_CPU_RST_DMA, BIT_CPU_RST_SDIO_DMA);
+
+	/* initial TX BD */
+	HAL_WRITE32(SDIO_REG_BASE, REG_SPDIO_TXBD_ADDR, SDIOInit_Struct->TXBD_BAR);
+	HAL_WRITE16(SDIO_REG_BASE, REG_SPDIO_TXBD_SIZE, SDIOInit_Struct->TXBD_RING_SIZE);
+
+	/* Set TX_BUFF_UNIT_SIZE */
+	HAL_WRITE8(SDIO_REG_BASE, REG_SPDIO_TX_BUF_UNIT_SZ, SDIOInit_Struct->TX_BUFFER_SIZE);
+
+	/* Set DISPATCH_TXAGG_PKT */
+	HAL_WRITE32(SDIO_REG_BASE, REG_SPDIO_AHB_DMA_CTRL, HAL_READ32(SDIO_REG_BASE, REG_SPDIO_AHB_DMA_CTRL) | DISPATCH_TXAGG_PKT);
+
+	/*  Reset HW TX BD pointer */
+	HAL_WRITE32(SDIO_REG_BASE, REG_SPDIO_TXBD_RPTR, HAL_READ32(SDIO_REG_BASE, REG_SPDIO_TXBD_WPTR));
+
+	/* Init RX BD and RX Buffer */
+	HAL_WRITE32(SDIO_REG_BASE, REG_SPDIO_RXBD_ADDR, SDIOInit_Struct->RXBD_BAR);
+	HAL_WRITE16(SDIO_REG_BASE, REG_SPDIO_RXBD_SIZE, SDIOInit_Struct->RXBD_RING_SIZE);
+
+	/*  Reset HW RX BD pointer */
+	HAL_WRITE16(SDIO_REG_BASE, REG_SPDIO_RXBD_C2H_WPTR, HAL_READ16(SDIO_REG_BASE, REG_SPDIO_RXBD_C2H_RPTR));
+
+	/* Set the threshold of free RX BD count to trigger interrupt */
+	HAL_WRITE16(SDIO_REG_BASE, REG_SPDIO_RX_BD_FREE_CNT, SDIOInit_Struct->RXBD_FREE_TH);
+
+	/*  Indicate Host this is a iNIC FW */
+	Temp = HAL_READ16(SDIO_REG_BASE, REG_SPDIO_CCPWM2);
+	Temp |= CPWM2_INIC_FW_RDY_BIT;
+	Temp ^= CPWM2_TOGGLE_BIT;
+	HAL_WRITE16(SDIO_REG_BASE, REG_SPDIO_CCPWM2, Temp);
+}
+
+/**
+  * @brief  SDIO interrupt clear
+  * @note	clear all interrupt of SDIO
+  * @retval None
+  */
+void SDIO_INTClear(SDIO_TypeDef *SDIO, u16 IntStatus)
+{
+	UNUSED(SDIO);
+
+	HAL_WRITE16(SDIO_REG_BASE, REG_SPDIO_CPU_INT_STAS, IntStatus);	// clean the ISR
+}
+
+/**
+  * @brief  SDIO interrupt clear
+  * @note	clear all interrupt of SDIO
+  * @retval None
+  */
+void SDIO_INTClearAll(SDIO_TypeDef *SDIO)
+{
+	UNUSED(SDIO);
+
+	u16 IntStatus;
+
+	IntStatus = HAL_READ16(SDIO_REG_BASE, REG_SPDIO_CPU_INT_STAS);
+	HAL_WRITE16(SDIO_REG_BASE, REG_SPDIO_CPU_INT_STAS, IntStatus);	// clean the ISR
+}
+
+
+/**
+  * @brief  SDIO disable or enable interrupt by modify the interrupt mask
+  * @param  IntMask: The bit map to enable the interrupt.
+  *          This parameter can be one or combinations of the following values:
+  *            @arg BIT_TXFIFO_H2C_OVF:
+  *            @arg BIT_H2C_BUS_RES_FAIL:
+  *            @arg BIT_H2C_DMA_OK:
+  *            @arg BIT_C2H_DMA_OK:
+  *            @arg BIT_H2C_MSG_INT:
+  *            @arg BIT_RPWM1_INT:
+  *            @arg BIT_RPWM2_INT:
+  *            @arg BIT_SDIO_RST_CMD_INT:
+  *            @arg BIT_RXBD_FLAG_ERR_INT:
+  *            @arg BIT_RX_BD_AVAI_INT:
+  *            @arg BIT_HOST_WAKE_CPU_INT:
+  * @param  NewState: ENABLE or DISABLE.
+  * @retval None
+  */
+void SDIO_INTConfig(SDIO_TypeDef *SDIO, u16 IntMask, u32 NewState)
+{
+	UNUSED(SDIO);
+
+	u16 IntMaskTmp = HAL_READ16(SDIO_REG_BASE, REG_SPDIO_CPU_INT_MASK);
+
+	if (NewState == ENABLE) {
+		IntMaskTmp |= IntMask;
+	} else {
+		IntMaskTmp &= ~IntMask;
+	}
+
+	HAL_WRITE16(SDIO_REG_BASE, REG_SPDIO_CPU_INT_MASK, IntMaskTmp);
+}
+
+/**
+  * @brief  Get SDIO interrupt status
+  * @param  None.
+  * @retval Interrupt status
+  */
+u16 SDIO_INTStatus(SDIO_TypeDef *SDIO)
+{
+	UNUSED(SDIO);
+
+	return HAL_READ16(SDIO_REG_BASE, REG_SPDIO_CPU_INT_STAS);
+}
+
+/**
+  * @brief  Get RPWM1 from host.
+  * @param  None.
+  * @retval RPWM1 val.
+  */
+u8 SDIO_RPWM1_Get(SDIO_TypeDef *SDIO)
+{
+	UNUSED(SDIO);
+
+	return HAL_READ8(SDIO_REG_BASE, REG_SPDIO_CRPWM);
+}
+
+/**
+  * @brief  Get RPWM2 from host.
+  * @param  None.
+  * @retval RPWM2 val.
+  */
+u16 SDIO_RPWM2_Get(SDIO_TypeDef *SDIO)
+{
+	UNUSED(SDIO);
+
+	return HAL_READ16(SDIO_REG_BASE, REG_SPDIO_CRPWM2);
+}
+
+/**
+  * @brief  Set CPWM1 to host
+  * @param  Val: CPWM msg to send.
+  * @retval None
+  */
+void SDIO_CPWM1_Set(SDIO_TypeDef *SDIO, u8 Val)
+{
+	UNUSED(SDIO);
+
+	u8  Temp = HAL_READ8(SDIO_REG_BASE, REG_SPDIO_CCPWM);
+
+	Temp ^= CPWM1_TOGGLE_BIT;
+	Temp |= Val;
+
+	HAL_WRITE8(SDIO_REG_BASE, REG_SPDIO_CCPWM, Temp);
+}
+
+/**
+  * @brief  Set CPWM2 to host
+  * @param  Val: CPWM msg to send.
+  * @param  Newstate: DISABLE/ENABLE.
+  * @retval None
+  */
+void SDIO_CPWM2_Set(SDIO_TypeDef *SDIO, u16 Val, u32 Newstate)
+{
+	UNUSED(SDIO);
+
+	u16  Temp = HAL_READ16(SDIO_REG_BASE, REG_SPDIO_CCPWM2);
+
+	Temp ^= CPWM2_TOGGLE_BIT;
+
+	if (Newstate == ENABLE) {
+		Temp |= Val;
+	} else {
+		Temp &= ~Val;
+	}
+
+	HAL_WRITE16(SDIO_REG_BASE, REG_SPDIO_CCPWM2, Temp);
+}
+
+/**
+  * @brief  Get H2C message from host.
+  * @param  None.
+  * @retval H2C message val.
+  */
+u32 SDIO_H2C_MSG_Get(SDIO_TypeDef *SDIO)
+{
+	UNUSED(SDIO);
+
+	return HAL_READ32(SDIO_REG_BASE, REG_SPDIO_CPU_H2C_MSG);
+}
+
+/**
+  * @brief  Get RXBD read pointer, updated by SDIO IP.
+  * @param  None
+  * @retval RXBD read pointer
+  */
+u16 SDIO_RXBD_RPTR_Get(SDIO_TypeDef *SDIO)
+{
+	UNUSED(SDIO);
+
+	return HAL_READ16(SDIO_REG_BASE, REG_SPDIO_RXBD_C2H_RPTR);
+}
+
+/**
+  * @brief  Set RXBD write pointer, updated by cpu CM4 driver.
+  * @param  Val: RXBD write pointer
+  * @retval None
+  */
+void SDIO_RXBD_WPTR_Set(SDIO_TypeDef *SDIO, u16 Val)
+{
+	UNUSED(SDIO);
+
+	HAL_WRITE16(SDIO_REG_BASE, REG_SPDIO_RXBD_C2H_WPTR, Val);
+}
+
+/**
+  * @brief  Get TXBD write pointer, updated by SDIO IP.
+  * @param  None
+  * @retval TXBD write pointer
+  */
+u32 SDIO_TXBD_WPTR_Get(SDIO_TypeDef *SDIO)
+{
+	UNUSED(SDIO);
+
+	return HAL_READ32(SDIO_REG_BASE, REG_SPDIO_TXBD_WPTR);
+}
+
+/**
+  * @brief  Set TXBD read pointer, updated by CM4 driver.
+  * @param  None
+  * @retval TXBD read pointer
+  */
+void SDIO_TXBD_RPTR_Set(SDIO_TypeDef *SDIO, u32 Val)
+{
+	UNUSED(SDIO);
+
+	HAL_WRITE32(SDIO_REG_BASE, REG_SPDIO_TXBD_RPTR, Val);
+}
+
+/**
+  * @brief  Get TXBD read pointer.
+  * @param  None
+  * @retval TXBD read pointer
+  */
+u32 SDIO_TXBD_RPTR_Get(SDIO_TypeDef *SDIO)
+{
+	UNUSED(SDIO);
+
+	return HAL_READ32(SDIO_REG_BASE, REG_SPDIO_TXBD_RPTR);
+}
+
+/**
+  * @brief  Reset SDIO DMA.
+  * @param  None
+  * @retval TXBD read pointer
+  */
+void SDIO_DMA_Reset(SDIO_TypeDef *SDIO)
+{
+	UNUSED(SDIO);
+
+	HAL_WRITE8(SDIO_REG_BASE, REG_SPDIO_CPU_RST_DMA, BIT_CPU_RST_SDIO_DMA);
+}
+
+/**
+  * @brief  Get AHB DMA control.
+  * @param  None.
+  * @retval H2C message val.
+  */
+u32 SDIO_DMA_CTRL_Get(SDIO_TypeDef *SDIO)
+{
+	UNUSED(SDIO);
+
+	return HAL_READ32(SDIO_REG_BASE, REG_SPDIO_AHB_DMA_CTRL);
+}
+
+/**
+  * @brief  Set SDIO ready bit.
+  * @param  ready: Set if SDIO is ready. It can be ENABLE/DISABLE.
+  * @retval None
+  */
+void SDIO_SetReady(SDIO_TypeDef *SDIO, int ready)
+{
+	UNUSED(SDIO);
+
+	u8 reg;
+
+	reg = HAL_READ8(SDIO_REG_BASE, REG_SPDIO_CPU_IND);
+
+	if (ready == ENABLE) {
+		reg |= BIT_SYSTEM_TRX_RDY_IND;
+	} else {
+		reg &= ~BIT_SYSTEM_TRX_RDY_IND;
+	}
+
+	HAL_WRITE8(SDIO_REG_BASE, REG_SPDIO_CPU_IND, reg);
+}
+
+/**
+  * @brief  SDIO set Rx request.
+  * @param  None
+  * @retval None
+  */
+void SDIO_RxReq(SDIO_TypeDef *SDIO)
+{
+	UNUSED(SDIO);
+
+	HAL_WRITE8(SDIO_REG_BASE, REG_SPDIO_HCI_RX_REQ, BIT_HCI_RX_REQ);
+}
diff --git a/ameba/amebadplus/source/fwlib/ram_common/ameba_ups.c b/ameba/amebadplus/source/fwlib/ram_common/ameba_ups.c
new file mode 100644
index 00000000..98d5f28d
--- /dev/null
+++ b/ameba/amebadplus/source/fwlib/ram_common/ameba_ups.c
@@ -0,0 +1,147 @@
+/*
+ * Copyright (c) 2024 Realtek Semiconductor Corp.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "ameba_soc.h"
+/** @addtogroup Ameba_Periph_Driver
+  * @{
+  */
+
+/** @defgroup UPS
+  * @brief  UPS driver modules
+  * @{
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup UPS_Exported_Functions UPS Exported Functions
+  * @{
+  */
+
+/**
+  * @brief  Initializes the parameters in the UPS_InitStruct with default values.
+  * @param  UPS_InitStruct: pointer to a UPS_InitTypeDef structure that contains
+  *         the configuration information for the UPS.
+  * @retval  None
+  */
+void UPS_StructInit(UPS_InitTypeDef *UPS_InitStruct)
+{
+	UPS_InitStruct->UPS_ProducerType = UPS_SRC_GPIO;
+	UPS_InitStruct->UPS_ConsumerType = UPS_DST_TIM_EN | UPS_DST_PWM_TRIG;
+	UPS_InitStruct->UPS_TimerOfIn = ENABLE;
+	UPS_InitStruct->UPS_ReverseSig = DISABLE;
+	UPS_InitStruct->UPS_DebounceCnt = 0x0;
+}
+
+/**
+  * @brief  Initializes the UPS according to the specified parameters in UPS_InitStruct.
+  * @param  UPS_InitStruct: pointer to a UPS_InitTypeDef structure that contains
+  *         the configuration information for the UPS.
+  * @retval  None
+  */
+void UPS_Init(UPS_InitTypeDef *UPS_InitStruct)
+{
+	UPS_SrcConfig(UPS_InitStruct->UPS_ProducerType);
+	UPS_DstConfig(UPS_InitStruct->UPS_ConsumerType);
+	UPS_TimOfInCmd(UPS_InitStruct->UPS_TimerOfIn);
+	UPS_ReverseCmd(UPS_InitStruct->UPS_ReverseSig);
+	UPS_SetDbcCnt(UPS_InitStruct->UPS_DebounceCnt);
+}
+
+/**
+  * @brief  Specify the source signal type of UPS.
+  * @param  SrcType: Specified signal source.
+  *   			This parameter can be a value of @ref UPS_Producer_Signal_Type_Definitions.
+  * @retval None
+  */
+void UPS_SrcConfig(u8 SrcType)
+{
+	assert_param(IS_UPS_PRODUCER_TYPE(SrcType));
+
+	u32 Temp = HAL_READ32(SYSTEM_CTRL_BASE, REG_LSYS_UPS_CTRL);
+	Temp &= ~LSYS_MASK_UPS_SRC_SEL;
+	Temp |= LSYS_UPS_SRC_SEL(SrcType);
+	HAL_WRITE32(SYSTEM_CTRL_BASE, REG_LSYS_UPS_CTRL, Temp);
+}
+
+/**
+  * @brief  Specify the destination signal type of UPS.
+  * @param  DstType: Specified signal destination.
+  *   			This parameter can be a value or combinations of @ref UPS_Consumer_Signal_Type_Definitions.
+  * @retval None
+  */
+void UPS_DstConfig(u8 DstType)
+{
+	assert_param(IS_UPS_CONSUMER_TYPE(DstType));
+
+	if (DstType == UPS_DST_NONE) {
+		u32 Temp = HAL_READ32(SYSTEM_CTRL_BASE, REG_LSYS_UPS_CTRL);
+		Temp &= ~(LSYS_BIT_UPS_OUT_PWM_TRIG | LSYS_BIT_UPS_OUT_TIM_EN);
+		HAL_WRITE32(SYSTEM_CTRL_BASE, REG_LSYS_UPS_CTRL, Temp);
+		return;
+	}
+
+	if (DstType & UPS_DST_TIM_EN) {
+		u32 Temp = HAL_READ32(SYSTEM_CTRL_BASE, REG_LSYS_UPS_CTRL);
+		Temp |= LSYS_BIT_UPS_OUT_TIM_EN;
+		HAL_WRITE32(SYSTEM_CTRL_BASE, REG_LSYS_UPS_CTRL, Temp);
+	}
+
+	if (DstType & UPS_DST_PWM_TRIG) {
+		u32 Temp = HAL_READ32(SYSTEM_CTRL_BASE, REG_LSYS_UPS_CTRL);
+		Temp |= LSYS_BIT_UPS_OUT_PWM_TRIG;
+		HAL_WRITE32(SYSTEM_CTRL_BASE, REG_LSYS_UPS_CTRL, Temp);
+	}
+}
+
+/**
+  * @brief Enable or disable basic timer overflow input.
+  * @param NewState: can be ENABLE or DISABLE.
+  * @retval None.
+  */
+void UPS_TimOfInCmd(u32 NewState)
+{
+	u32 Temp = HAL_READ32(SYSTEM_CTRL_BASE, REG_LSYS_UPS_CTRL);
+
+	if (NewState != DISABLE) {
+		Temp |= LSYS_BIT_UPS_IN_TIM_OF;
+	} else {
+		Temp &= ~LSYS_BIT_UPS_IN_TIM_OF;
+	}
+
+	HAL_WRITE32(SYSTEM_CTRL_BASE, REG_LSYS_UPS_CTRL, Temp);
+}
+
+/**
+  * @brief Enable or disable signal_reverse function in circuit.
+  * @param  NewState: can be one of the following value:
+  *			@arg ENABLE: Reverse source signal.
+  *			@arg DISABLE: Do not reverse source signal.
+  * @retval  None.
+  */
+void UPS_ReverseCmd(u32 NewState)
+{
+	u32 Temp = HAL_READ32(SYSTEM_CTRL_BASE, REG_LSYS_UPS_CTRL);
+	Temp &= ~LSYS_BIT_UPS_RVS_EN;
+
+	if (NewState != DISABLE) {
+		Temp |= LSYS_BIT_UPS_RVS_EN;
+	}
+
+	HAL_WRITE32(SYSTEM_CTRL_BASE, REG_LSYS_UPS_CTRL, Temp);
+}
+
+/**
+  * @brief  Set debounce counter under XTAL40M to realize signal deglitch.
+  * @param  Dbc_Cnt: Debounce counter to be set.
+  *	@note Dbc_Cnt = 0 means debounce function is disabled.
+  * @retval None
+  */
+void UPS_SetDbcCnt(u16 Dbc_Cnt)
+{
+	u32 Temp = HAL_READ32(SYSTEM_CTRL_BASE, REG_LSYS_UPS_CTRL);
+	Temp &= ~LSYS_MASK_UPS_DBC_CNT;
+	Temp |= LSYS_UPS_DBC_CNT(Dbc_Cnt);
+	HAL_WRITE32(SYSTEM_CTRL_BASE, REG_LSYS_UPS_CTRL, Temp);
+}
diff --git a/ameba/amebadplus/source/swlib/log.c b/ameba/amebadplus/source/swlib/log.c
index e69f3a1d..e729b66f 100644
--- a/ameba/amebadplus/source/swlib/log.c
+++ b/ameba/amebadplus/source/swlib/log.c
@@ -17,6 +17,713 @@ rtk_log_tag_t rtk_log_tag_array[LOG_TAG_CACHE_ARRAY_SIZE] = {0};
 /* Count cache array usage */
 static volatile uint32_t rtk_log_entry_count = 0;
 
+#define get_num_va_args(_args, _lcount)				\
+	(((_lcount) > 1)  ? va_arg(_args, long long int) :	\
+	(((_lcount) == 1) ? va_arg(_args, long int) :		\
+			    va_arg(_args, int)))
+
+#define get_unum_va_args(_args, _lcount)				\
+	(((_lcount) > 1)  ? va_arg(_args, unsigned long long int) :	\
+	(((_lcount) == 1) ? va_arg(_args, unsigned long int) :		\
+			    va_arg(_args, unsigned int)))
+
+#define get_char_upper_lower(_upper, _rem)				\
+	(((_rem) < 0xa)   ?  ('0' + _rem) : 					\
+	(((_upper) == 1)   ?  ('A' + (_rem - 0xa)) : 			\
+	('a' + (_rem - 0xa))))
+
+#define is_digit(c) ((c >= '0') && (c <= '9'))
+
+static int print_string(const char *str)
+{
+	int count = 0;
+
+	//assert_param(str != NULL);
+	if (str == NULL) {
+		return -1;
+	}
+	for (; *str != '\0'; str++) {
+		DiagPutChar(*str);
+		count++;
+	}
+	return count;
+}
+
+static int print_unsigned_num(unsigned long long int unum, unsigned int radix,
+							  char padc, int padn, int upper, int sign)
+{
+	/* Just need enough space to store 64 bit decimal integer */
+	char num_buf[20];
+	int i = 0, count = 0;
+	unsigned int rem;
+	/* 1. convert num to str*/
+	do {
+		rem = unum % radix;
+		num_buf[i] = get_char_upper_lower(upper, rem);
+		i++;
+		unum /= radix;
+	} while (unum > 0U);
+	/* 2. If there is a sign bit, subtract the padn by 1. */
+	if (sign) {
+		count++;
+		padn--;
+	}
+
+	/* 3. If fill 0, need to print the sign first, and then fill in 0 */
+	if (sign && (padc == '0')) {
+		DiagPutChar('-');
+	}
+	/* 4. Fill the character padc */
+	if (padn > 0) {
+		while (i < padn) {
+			DiagPutChar(padc);
+			count++;
+			padn--;
+		}
+	}
+	/* 5.If fill a space, need to wait for step 4 to complete before filling the sign. */
+	if (sign && (padc == ' ' || padc == '\0')) {
+		DiagPutChar('-');
+	}
+	/* 6. Print the numbers*/
+	while (--i >= 0) {
+		DiagPutChar(num_buf[i]);
+		count++;
+	}
+
+	return count;
+}
+
+static inline int pad_char_control(int padn, char padc)
+{
+	int count = 0;
+	while (padn > 0) {
+		DiagPutChar(padc);
+		padn--;
+		count++;
+	}
+	return count;
+}
+
+static inline int pad_num_control(unsigned long long int unum, unsigned int radix, char padc,
+								  int padn, int upper, int sign, int pad_on_right)
+{
+	int count = 0;
+	/* 1. if '-' left align was set, pad character in the right of num*/
+	if (pad_on_right) {
+		int width = print_unsigned_num(unum, radix, padc, 0, upper, sign);
+		count += width;
+		//if padc is equal to '\space' and pad number is great than width of num, execute pad opration. Otherwise, no operation.
+		if ((padn > width) && (padc  == ' ')) {
+			count += pad_char_control(padn - width, padc);
+		}
+		/* 2. Normally, pad operation is executed on the left of num.*/
+	} else {
+		count += print_unsigned_num(unum, radix, padc, padn, upper, sign);
+	}
+	return count;
+}
+/*******************************************************************
+ * Reduced format print for Trusted firmware.
+ * The following type specifiers are supported by this print
+ * %lx - hexadecimal format
+ * %s - string format
+ * %lu or %i - signed decimal format
+ * %u - unsigned decimal format
+ * %p - pointer format
+ *
+ * The following length specifiers are supported by this print
+ * %l - long int (64-bit on AArch64)
+ * %ll - long long int (64-bit on AArch64)
+ * %z - size_t sized integer formats (64 bit on AArch64)
+ *
+ * The following padding specifiers are supported by this print
+ * %0NN - Left-pad the number with 0s (NN is a decimal number)
+ * %NN - Left-pad the number with spaces
+ * %-NN - Right-pad the number with spaces
+ *
+ * The print exits on all other formats specifiers other than valid
+ * combinations of the above specifiers.
+ *******************************************************************/
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wimplicit-fallthrough"
+int DiagVprintf(const char *fmt, va_list args)
+{
+	int l_count;
+	long long int num;
+	unsigned long long int unum;
+	char *str;
+
+	int count = 0; 		/* Number of printed characters */
+	int upper = 0;
+
+	// pad control
+	char padc = '\0'; 	/* Padding character */
+	int padn; 			/* Number of characters to pad */
+	int pad_on_right;
+	int sign = 0;
+
+	char c = '\0';
+	int percent_flag = 0;
+	char *tempstr = NULL;
+	int tempcount = 0;
+
+	while (*fmt != '\0') {
+		l_count = 0;
+		percent_flag = pad_on_right = padn = sign = 0;
+		padc = '\0';
+
+		if (*fmt == '%') {
+			percent_flag = 1;
+			fmt++;
+			/* Check the format specifier */
+loop:
+			switch (*fmt) {
+			case 'i': /* Fall through to next one */
+			case 'd':
+				num = get_num_va_args(args, l_count);
+				if (num < 0) {
+					sign = 1;
+					unum = (unsigned long long int) - num;
+				} else {
+					unum = (unsigned long long int)num;
+				}
+				count += pad_num_control(unum, 10, padc, padn, upper, sign, pad_on_right);
+				break;
+			case 'u':
+				unum = get_unum_va_args(args, l_count);
+				count += pad_num_control(unum, 10, padc, padn, upper, sign, pad_on_right);
+				break;
+			case 'B':
+			case 'b':
+				unum = get_unum_va_args(args, l_count);
+				count += pad_num_control(unum, 2, padc, padn, upper, sign, pad_on_right);
+				break;
+			case 'O':
+			case 'o':
+				unum = get_unum_va_args(args, l_count);
+				count += pad_num_control(unum, 8, padc, padn, upper, sign, pad_on_right);
+				break;
+			case 'X':
+				upper = 1;
+			case 'x':
+				unum = get_unum_va_args(args, l_count);
+				count += pad_num_control(unum, 16, padc, padn, upper, sign, pad_on_right);
+				break;
+			case 'p':
+				upper = 1;
+				unum = (uintptr_t)va_arg(args, void *);
+				if (sizeof(uintptr_t) == 4U) {
+					padc = '0';
+					padn = 8;
+				} else {
+					padc = '0';
+					padn = 16;
+				}
+				count += pad_num_control(unum, 16, padc, padn, upper, sign, pad_on_right);
+				break;
+			case 's':
+				str = va_arg(args, char *);
+				tempstr = str;
+				tempcount = 0;
+				while (*tempstr != '\0') {
+					tempstr++;
+					tempcount++;
+				}
+				// left pad
+				if (!pad_on_right && (padn - tempcount > 0)) {
+					count += pad_char_control(padn - tempcount, padc);
+				}
+				// print string
+				count += print_string(str);
+				// right pad
+				if (pad_on_right && (padn - tempcount > 0)) {
+					count += pad_char_control(padn - tempcount, padc);
+				}
+				break;
+			case 'c':
+			case 'C':
+				c = va_arg(args, int);
+				// left pad
+				if (!pad_on_right && (padn > 1)) {
+					count += pad_char_control(padn - 1, padc);
+				}
+				DiagPutChar(c);
+				count++;
+				//right pad
+				if (pad_on_right && (padn > 1)) {
+					count += pad_char_control(padn - 1, padc);
+				}
+				break;
+			case 'z':
+				if (sizeof(size_t) == 8U) {
+					goto not_support;
+				}
+				fmt++;
+				goto loop;
+			case 'L':
+			case 'l':
+				l_count++;
+				fmt++;
+				goto loop;
+			case '-':
+				fmt++;
+				pad_on_right++;
+				goto loop;
+			/*% is followed by a %. */
+			case '%':
+				if (percent_flag) {
+					DiagPutChar('%');
+				}
+				count++;
+				break;
+			case '0':
+				padc = '0';
+				padn = 0;
+				fmt++;
+				goto pad_count;
+			case '1':
+			case '2':
+			case '3':
+			case '4':
+			case '5':
+			case '6':
+			case '7':
+			case '8':
+			case '9':
+				padc = ' ';
+				padn = 0;
+				goto pad_count;
+			/*% is followed by a spaces, so padc = \space. */
+			case ' ':
+				padc = ' ';
+				padn = 0;
+				fmt++;
+pad_count:
+				for (;;) {
+					char ch = *fmt;
+					if (ch == '\0') { // deal with case '% \0'.
+						goto exit;
+					} else if (!is_digit(ch)) {
+						goto loop;
+					}
+					padn = (padn * 10) + (ch - '0');
+					fmt++;
+				}
+			case '\0':
+				break;
+			default:
+not_support:
+				/* Exit on any other format specifier */
+				return -1;
+			}
+			fmt++;
+			continue;
+		}
+		DiagPutChar(*fmt);
+		fmt++;
+		count++;
+	}
+exit:
+	return count;
+}
+
+static inline int print_decimal_num(unsigned int unum, int radix, char padc, int padn, int sign)
+{
+	/* Just need enough space to store 31 bit decimal integer */
+	char num_buf[10];
+	int i = 0, count = 0;
+	unsigned int rem;
+	/* 1. convert num to str*/
+	do {
+		rem = unum % radix;
+		num_buf[i] = get_char_upper_lower(0, rem);
+		i++;
+		unum /= radix;
+	} while (unum > 0U);
+
+	if (sign) {
+		count++;
+		padn--;
+	}
+
+	if (sign && (padc == '0')) {
+		DiagPutChar('-');
+	}
+
+	/* 2. Fill the character padc */
+	if (padn > 0) {
+		while (i < padn) {
+			DiagPutChar(padc);
+			count++;
+			padn--;
+		}
+	}
+	if (sign && (padc == ' ' || padc == '\0')) {
+		DiagPutChar('-');
+	}
+	/* 3. Print the numbers*/
+	while (--i >= 0) {
+		DiagPutChar(num_buf[i]);
+		count++;
+	}
+
+	return count;
+}
+
+/*************************************************************************
+ * Internal Nano format print to reduce stack size, num must within 32bits
+ * The following type specifiers are supported by this print
+ * %x - hexadecimal format
+ * %s - string format
+ * %c - char format
+ * %d or %i - signed decimal format
+ *
+ * The following padding specifiers are supported by this print
+ * %0NN - Left-pad the number with 0s (NN is a decimal number)
+ * %NN - Left-pad the number with space
+ *
+ * The print exits on all other formats specifiers other than valid
+ * combinations of the above specifiers.
+ **************************************************************************/
+int DiagVprintfNano(const char *fmt, va_list args)
+{
+	char *str;
+
+	int count = 0; 		/* Number of printed characters */
+	int sign = 0, num = 0;
+	// pad control
+	char padc = '\0'; 	/* Padding character */
+	int padn; 			/* Number of characters to pad */
+	int pad_on_right;
+
+	char c = '\0';
+	int percent_flag = 0;
+	char *tempstr = NULL;
+	int tempcount = 0;
+
+	unsigned int unum;
+	while (*fmt != '\0') {
+		percent_flag = pad_on_right = padn = 0;
+		padc = '\0';
+		sign = 0;
+
+		if (*fmt == '%') {
+			percent_flag = 1;
+			fmt++;
+loop:
+			/* Check the format specifier */
+			switch (*fmt) {
+			case 'i':
+			case 'd':
+				num = get_num_va_args(args, 0);
+				if (num < 0) {
+					sign = 1;
+					unum = (unsigned int) - num;
+				} else {
+					unum = (unsigned int)num;
+				}
+				count += print_decimal_num(unum, 10, padc, padn, sign);
+				break;
+			case 'u':
+				unum = (unsigned int)get_unum_va_args(args, 0);
+				count += print_decimal_num(unum, 10, padc, padn, 0);
+				break;
+			case 'x':
+				unum = (unsigned int)get_unum_va_args(args, 0);
+				count += print_decimal_num(unum, 16, padc, padn, 0);
+				break;
+			case 's':
+				str = va_arg(args, char *);
+				tempstr = str;
+				tempcount = 0;
+				while (*tempstr != '\0') {
+					tempstr++;
+					tempcount++;
+				}
+				// left pad
+				if (!pad_on_right && (padn - tempcount > 0)) {
+					count += pad_char_control(padn - tempcount, padc);
+				}
+				// print string
+				count += print_string(str);
+				// right pad
+				if (pad_on_right && (padn - tempcount > 0)) {
+					count += pad_char_control(padn - tempcount, padc);
+				}
+				break;
+			case 'c':
+			case 'C':
+				c = va_arg(args, int);
+				// left pad
+				if (!pad_on_right && (padn > 1)) {
+					count += pad_char_control(padn - 1, padc);
+				}
+				DiagPutChar(c);
+				count++;
+				//right pad
+				if (pad_on_right && (padn > 1)) {
+					count += pad_char_control(padn - 1, padc);
+				}
+				break;
+			/*% is followed by a %. */
+			case '%':
+				if (percent_flag) {
+					DiagPutChar('%');
+				}
+				count++;
+				break;
+			case '0':
+				padc = '0';
+				padn = 0;
+				fmt++;
+				goto pad_count;
+			case '1':
+			case '2':
+			case '3':
+			case '4':
+			case '5':
+			case '6':
+			case '7':
+			case '8':
+			case '9':
+				padc = ' ';
+				padn = 0;
+				goto pad_count;
+			/*% is followed by a spaces, so padc = \space. */
+			case ' ':
+				padc = ' ';
+				padn = 0;
+				fmt++;
+pad_count:
+				for (;;) {
+					char ch = *fmt;
+					if (ch == '\0') { // deal with case '% \0'.
+						return count;
+					} else if (!is_digit(ch)) {
+						goto loop;
+					}
+					padn = (padn * 10) + (ch - '0');
+					fmt++;
+				}
+
+			case '\0':
+				break;
+			default:
+				/* Exit on any other format specifier */
+				return -1;
+			}
+			fmt++;
+			continue;
+		}
+		DiagPutChar(*fmt);
+		fmt++;
+		count++;
+	}
+
+	return count;
+}
+#pragma GCC diagnostic pop
+
+u32 DiagPrintf(const char *fmt, ...)
+{
+	int ret;
+	va_list va;
+
+	va_start(va, fmt);
+	ret = DiagVprintf(fmt, va);
+	va_end(va);
+	return ret;
+}
+
+u32 DiagPrintfNano(const char *fmt, ...)
+{
+	int ret;
+	va_list va;
+
+	va_start(va, fmt);
+	ret = DiagVprintfNano(fmt, va);
+	va_end(va);
+	return ret;
+}
+
+/* support %s %d %x %c, %08x.*/
+int DiagSnPrintf(char *buf, size_t size, const char *fmt, ...)
+{
+	va_list     ap;
+	char *p, *s, *buf_end = NULL;
+	char padc = ' ';
+	int padn = 0;
+
+	if (buf == NULL) {
+		return 0;
+	}
+
+	va_start(ap, fmt);
+	s = buf;
+	buf_end = size ? (buf + size) : (char *)~0;
+	for (; *fmt != '\0'; ++fmt) {
+		padn = 0;
+		padc = ' ';
+		if (*fmt != '%') {
+			*s++ = *fmt;
+
+			if (s >= buf_end) {
+				goto Exit;
+			}
+
+			continue;
+		}
+		if (*++fmt == 's') {
+			p = va_arg(ap, char *);
+			while (*p != '\0') {
+				*s++ = *p++;
+				if (s >= buf_end) {
+					goto Exit;
+				}
+			}
+		} else {	/* Length of item is bounded */
+
+			char tmp[20], *q = tmp;
+			int shift = 0;// = 12;
+
+			int lpforchk = 0;
+			if ((*fmt == 'p') || (*fmt == 'P')) {
+				lpforchk = (uintptr_t)va_arg(ap, void *);
+				if (sizeof(uintptr_t) == 4U) {
+					padc = '0';
+					padn = 8;
+				} else {
+					padc = '0';
+					padn = 16;
+				}
+			} else {
+				lpforchk = va_arg(ap, int);
+			}
+			if ((lpforchk) < 0x10) {
+				shift = 0;
+			} else if (((lpforchk) >= 0x10) && ((lpforchk) < 0x100)) {
+				shift = 4;
+			} else if (((lpforchk) >= 0x100) && ((lpforchk) < 0x1000)) {
+				shift = 8;
+			} else if (((lpforchk) >= 0x1000) && ((lpforchk) < 0x10000)) {
+				shift = 12;
+			} else if (((lpforchk) >= 0x10000) && ((lpforchk) < 0x100000)) {
+				shift = 16;
+			} else if (((lpforchk) >= 0x100000) && ((lpforchk) < 0x1000000)) {
+				shift = 20;
+			} else if (((lpforchk) >= 0x1000000) && ((lpforchk) < 0x10000000)) {
+				shift = 24;
+			} else if ((lpforchk) >= 0x10000000) {
+				shift = 28;
+			} else {
+				shift = 28;
+			}
+
+			if (*fmt == '0') {
+				fmt++;
+				padc = '0';
+			}
+
+			if ((*fmt  > '0') && (*fmt  <= '9')) {
+				int width;
+				unsigned char fch = *fmt;
+				for (width = 0; (fch >= '0') && (fch <= '9'); fch = *++fmt) {
+					width = width * 10 + fch - '0';
+				}
+				padn = width;
+			}
+			/*
+			 * Before each format q points to tmp buffer
+			 * After each format q points past end of item
+			 * Only %p and %x can be filled with digits 0 or spaces.
+			 */
+			if ((*fmt == 'x') || (*fmt == 'X') || (*fmt == 'p') || (*fmt == 'P')) {
+				/* With x86 gcc, sizeof(long) == sizeof(int) */
+				const int lp = lpforchk;
+				int h = lp;
+				int hex_count = 0;
+				unsigned int h_back = h;
+				int ncase = (*fmt & 0x20);
+
+				if ((*fmt == 'p') || (*fmt == 'P')) {
+					*q++ = '0';
+					*q++ = 'X' | ncase;
+				}
+
+				while (h_back) {
+					hex_count += 1;
+					h_back  = h_back >> 4;
+				}
+				while (padn-- > hex_count) {
+					*q++ = padc;
+				}
+
+				for (; shift >= 0; shift -= 4) {
+					*q++ = "0123456789ABCDEF"[(h >> shift) & 0xF] | ncase;
+				}
+			} else if (*fmt == 'd') {
+				int i = lpforchk;
+				char *r;
+				int digit_space = 0;
+
+				if (i < 0) {
+					*q++ = '-';
+					i = -i;
+					digit_space++;
+				}
+
+				p = q;		/* save beginning of digits */
+
+				do {
+					*q++ = '0' + (i % 10);
+					i /= 10;
+					digit_space++;
+				} while (i);
+
+
+				for (; shift >= 0; shift -= 4) {
+
+					if (digit_space-- > 0) {
+						; //do nothing
+					} else {
+						*q++ = '0';
+					}
+				}
+
+				/* reverse digits, stop in middle */
+				r = q;		/* don't alter q */
+
+				while (--r > p) {
+					i = *r;
+					*r = *p;
+					*p++ = i;
+				}
+			} else if (*fmt == 'c') {
+				*q++ = lpforchk;
+			} else {
+				*q++ = *fmt;
+			}
+
+			/* now output the saved string */
+			for (p = tmp; p < q; ++p) {
+				*s++ = *p;
+
+				if (s >= buf_end) {
+					goto Exit;
+				}
+			}
+		}
+	}
+Exit:
+
+	if (buf) {
+		*s = '\0';
+	}
+	va_end(ap);
+	return (s - buf);
+}
+
 /***
 *  @brief	Print the modules' tag/level set by the rtk_log_level_set()
 *
diff --git a/ameba/amebadplus/source/swlib/sscanf_minimal.c b/ameba/amebadplus/source/swlib/sscanf_minimal.c
new file mode 100644
index 00000000..02cb7cd6
--- /dev/null
+++ b/ameba/amebadplus/source/swlib/sscanf_minimal.c
@@ -0,0 +1,467 @@
+/*
+ * Copyright (c) 2024 Realtek Semiconductor Corp.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "ameba_soc.h"
+#include <string.h>
+#include <stdlib.h>
+
+#define USHRT_MAX_INTERNAL       ((u16)(~0U))
+#define BUF_MAX        			((s16)(USHRT_MAX_INTERNAL>>1))
+#define STR_STORE_MAX_LEN		24
+#define KSTRTOX_OVERFLOW        (1U << 31)
+
+#define in_range(c, lo, up)  ((u8)c >= lo && (u8)c <= up)
+#define isprint(c)           in_range(c, 0x20, 0x7f)
+#define isdigit(c)           in_range(c, '0', '9')
+#define isxdigit(c)          (isdigit(c) || in_range(c, 'a', 'f') || in_range(c, 'A', 'F'))
+#define isspace(c)           (c == ' ' || c == '\f' || c == '\n' || c == '\r' || c == '\t' || c == '\v' || c == ',')
+
+
+/**
+ * div_u64_rem - unsigned 64bit divide with 32bit divisor with remainder
+ *
+ * This is commonly provided by 32bit archs to provide an optimized 64bit
+ * divide.
+ */
+static u64 div_u64_rem(u64 dividend, u32 divisor, u32 *remainder)
+{
+	*remainder = (u32)dividend % divisor;
+	return (u32)dividend / divisor;
+}
+
+/**
+ * div_s64_rem - signed 64bit divide with 32bit divisor with remainder
+ */
+static s64 div_s64_rem(s64 dividend, s32 divisor, s32 *remainder)
+{
+	*remainder = (s32)dividend % divisor;
+	return (s32)dividend / divisor;
+}
+
+/**
+ * div_u64 - unsigned 64bit divide with 32bit divisor
+ *
+ * This is the most common 64bit divide and should be used if possible,
+ * as many 32bit archs can optimize this variant better than a full 64bit
+ * divide.
+ */
+
+static u64 div_u64(u64 dividend, u32 divisor)
+{
+	u32 remainder;
+	return div_u64_rem(dividend, divisor, &remainder);
+}
+
+/**
+ * div_s64 - signed 64bit divide with 32bit divisor
+ */
+
+static s64 div_s64(s64 dividend, s32 divisor)
+{
+	s32 remainder;
+	return div_s64_rem(dividend, divisor, &remainder);
+}
+
+
+static const char *_parse_integer_fixup_radix(const char *s, unsigned int *base)
+{
+	if (*base == 0) {
+		if (s[0] == '0') {
+			if (_tolower(s[1]) == 'x' && isxdigit(s[2])) {
+				*base = 16;
+			} else {
+				*base = 8;
+			}
+		} else {
+			*base = 10;
+		}
+	}
+	if (*base == 16 && s[0] == '0' && _tolower(s[1]) == 'x') {
+		s += 2;
+	}
+	return s;
+}
+
+static char *skip_spaces(const char *str)
+{
+	while (isspace(*str)) {
+		++str;
+	}
+
+	return (char *)str;
+}
+static int skip_atoi(const char **s)
+{
+	int i = 0;
+
+	while (isdigit(**s)) {
+		i = i * 10 + *((*s)++) - '0';
+	}
+
+	return i;
+}
+
+static int judge_digit_width(const char *str, unsigned int base)
+{
+
+	int width = 0;
+
+	if ((base == 16 || base == 0) && str[0] == '0' && _tolower(str[1]) == 'x') {
+		str += 2;
+		width += 2;
+
+		while (isxdigit(*str)) {
+			width++;
+			str++;
+		}
+	} else if (base == 16) {
+		while (isxdigit(*str)) {
+			width++;
+			str++;
+		}
+	} else if (base == 8 || (base == 0 && str[0] == '0')) {
+		while (isdigit(*str) && (*str) < '8') {
+			width++;
+			str++;
+		}
+	} else {
+		while (isdigit(*str)) {
+			width++;
+			str++;
+		}
+	}
+
+	return width;
+}
+
+//_OPTIMIZE_NONE_
+int _vsscanf_minimal(const char *buf, const char *fmt, va_list args)
+{
+	const char *str = buf;
+	char *next;
+	char digit;
+	int num = 0;
+	int i = 0;
+	u8 qualifier;
+	unsigned int base;
+	union {
+		long long s;
+		unsigned long long u;
+	} val;
+	s16 field_width;
+	bool is_sign;
+
+	char str_store[STR_STORE_MAX_LEN] = {0};
+
+	while (*fmt) {
+		/* skip any white space in format */
+		/* white space in format matchs any amount of
+		    * white space, including none, in the input.
+		    */
+		if (isspace(*fmt)) {
+			fmt = skip_spaces(++fmt);
+			str = skip_spaces(str);
+		}
+
+		/* anything that is not a conversion must match exactly */
+		if (*fmt != '%' && *fmt) {
+			if (*fmt++ != *str++) {
+				break;
+			}
+
+			continue;
+		}
+
+		if (!*fmt) {
+			break;
+		}
+
+		++fmt;
+
+		/* skip this conversion.
+		    * advance both strings to next white space
+		    */
+		if (*fmt == '*') {
+			if (!*str) {
+				break;
+			}
+
+			while (!isspace(*fmt) && *fmt != '%' && *fmt) {
+				fmt++;
+			}
+			while (!isspace(*str) && *str) {
+				str++;
+			}
+
+			continue;
+		}
+
+		/* get field width */
+		field_width = -1;
+
+		if (isdigit(*fmt)) {
+
+			field_width = skip_atoi(&fmt);
+
+			if (field_width <= 0) {
+				break;
+			}
+		}
+
+		/* get conversion qualifier */
+		qualifier = -1;
+
+		if (*fmt == 'h' || _tolower(*fmt) == 'l' || _tolower(*fmt) == 'z') {
+			qualifier = *fmt++;
+
+			if (qualifier == *fmt) {
+				if (qualifier == 'h') {
+					qualifier = 'H';
+					fmt++;
+				} else if (qualifier == 'l') {
+					qualifier = 'L';
+					fmt++;
+				}
+			}
+		}
+
+		if (!*fmt) {
+			break;
+		}
+
+		if (*fmt == 'n') {
+			/* return number of characters read so far */
+			*va_arg(args, int *) = str - buf;
+			++fmt;
+			continue;
+		}
+
+		if (!*str) {
+			break;
+		}
+
+		base = 10;
+		is_sign = 0;
+
+		switch (*fmt++) {
+		case 'c': {
+			char *s = (char *)va_arg(args, char *);
+
+			if (field_width == -1) {
+				field_width = 1;
+			}
+
+			do {
+				*s++ = *str++;
+			} while (--field_width > 0 && *str);
+
+			num++;
+		}
+
+		continue;
+
+		case 's': {
+			char *s = (char *)va_arg(args, char *);
+			if (field_width == -1) {
+				field_width = SHRT_MAX;
+			}
+			/* first, skip leading white space in buffer */
+			str = skip_spaces(str);
+
+			/* now copy until next white space */
+			while (*str && !isspace(*str) && field_width--) {
+				*s++ = *str++;
+			}
+
+			*s = '\0';
+			num++;
+		}
+		continue;
+
+		case 'o':
+			base = 8;
+			break;
+
+		case 'x':
+		case 'X':
+			base = 16;
+			break;
+
+		case 'i':
+			base = 0;
+			is_sign = 1;
+			break;
+
+		case 'd':
+			is_sign = 1;
+			break;
+
+		case 'u':
+			break;
+
+		case '%':
+			/* looking for '%' in str */
+			if (*str++ != '%') {
+				return num;
+			}
+			continue;
+
+		default:
+			/* invalid format; stop here */
+			return num;
+		}
+
+		/* have some sort of integer conversion.
+		    * first, skip white space in buffer.
+		*/
+		str = skip_spaces(str);
+
+		digit = *str;
+
+		if (is_sign && digit == '-') {
+			if (field_width == -1) {
+				field_width = judge_digit_width(str + 1, base);
+				field_width++;
+			} else {
+				field_width = (judge_digit_width(str + 1, base) + 1) < field_width ?
+							  (judge_digit_width(str + 1, base) + 1) :
+							  field_width;
+			}
+			digit = *(str + 1);
+		} else if (field_width == -1) {
+			field_width = judge_digit_width(str, base);
+		} else {
+			field_width = judge_digit_width(str, base) < field_width ?
+						  judge_digit_width(str, base) :
+						  field_width;
+		}
+
+		if (!digit
+			|| (base == 16 && !isxdigit(digit))
+			|| (base == 10 && !isdigit(digit))
+			|| (base == 8 && (!isdigit(digit) || digit > '7'))
+			|| (base == 0 && !isdigit(digit))) {
+			break;
+		}
+
+		//assert_param (field_width <= STR_STORE_MAX_LEN);
+		for (i = 0; i < field_width ; i++) {
+			str_store[i] = str[i];
+		}
+
+		if (is_sign) {
+			val.s = qualifier != 'L' ?
+					strtol(str_store, &next, base) :
+					strtoll(str_store, &next, base);
+		} else {
+			val.u = qualifier != 'L' ?
+					_strtoul(str_store, &next, base) :
+					strtoull(str_store, &next, base);
+		}
+
+		/* standard strtoul need this */
+		next = (char *)str + field_width;
+
+		for (i = 0; i < STR_STORE_MAX_LEN ; i++) {
+			str_store[i] = 0;
+		}
+
+
+		//判断转换的字符串的宽度是否大于 %2d
+		if (field_width > 0 && next - str > field_width) {
+			if (base == 0) {
+				_parse_integer_fixup_radix(str, &base);
+			}
+
+			while (next - str > field_width) {
+				if (is_sign) {
+					val.s = div_s64(val.s, base);
+				} else {
+					val.u = div_u64(val.u, base);
+				}
+
+				--next;
+			}
+		}
+
+		switch (qualifier) {
+		case 'H':       /* that's 'hh' in format */
+			if (is_sign) {
+				*va_arg(args, signed char *) = val.s;
+			} else {
+				*va_arg(args, unsigned char *) = val.u;
+			}
+			break;
+
+		case 'h':
+			if (is_sign) {
+				memcpy(va_arg(args, short *), &(val.s), sizeof(short));
+			} else {
+				memcpy(va_arg(args, unsigned short *), &(val.u), sizeof(unsigned short));
+			}
+			break;
+
+		case 'l':
+			if (is_sign) {
+				memcpy(va_arg(args, long *), &(val.s), sizeof(long));
+			} else {
+				memcpy(va_arg(args, unsigned long *), &(val.u), sizeof(unsigned long));
+			}
+			break;
+
+		case 'L':
+			if (is_sign) {
+				memcpy(va_arg(args, long long *), &(val.s), sizeof(long long));
+			} else {
+				memcpy(va_arg(args, unsigned long long *), &(val.u), sizeof(unsigned long long));
+			}
+			break;
+
+		case 'Z':
+		case 'z':
+			memcpy(va_arg(args, size_t *), &(val.u), sizeof(size_t));
+			break;
+
+		default:
+			if (is_sign) {
+				memcpy(va_arg(args, int *), &(val.s), sizeof(int));
+			} else {
+				memcpy(va_arg(args, unsigned int *), &(val.u), sizeof(unsigned int));
+			}
+			break;
+		}
+
+		num++;
+
+		if (!next) {
+			break;
+		}
+
+		str = next;
+	}
+
+	return num;
+}
+
+/**
+* sscanf - Unformat a buffer into a list of arguments
+* @buf:        input buffer
+* @fmt:        formatting of buffer
+* @...:        resulting arguments
+*/
+/* support %* %x %c %s %o %x %i %d %u %h %z and %l(within len 24) */
+/* for internal use, not support [] and ^ */
+int _sscanf_ss(const char *buf, const char *fmt, ...)
+{
+	va_list args;
+	int i;
+
+	va_start(args, fmt);
+	i = _vsscanf_minimal(buf, fmt, args);
+	va_end(args);
+
+	return i;
+}
diff --git a/ameba/amebadplus/source/swlib/sscanf_minimal.h b/ameba/amebadplus/source/swlib/sscanf_minimal.h
new file mode 100644
index 00000000..434ca782
--- /dev/null
+++ b/ameba/amebadplus/source/swlib/sscanf_minimal.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2024 Realtek Semiconductor Corp.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _SSCANF_MINIMAL_H_
+#define _SSCANF_MINIMAL_H_
+
+extern int _sscanf_ss(const char *buf, const char *fmt, ...);
+
+#endif
diff --git a/ameba/amebaG2/CMakeLists.txt b/ameba/amebag2/CMakeLists.txt
similarity index 66%
rename from ameba/amebaG2/CMakeLists.txt
rename to ameba/amebag2/CMakeLists.txt
index f8a69c25..302d245a 100644
--- a/ameba/amebaG2/CMakeLists.txt
+++ b/ameba/amebag2/CMakeLists.txt
@@ -1,8 +1,20 @@
-#
+# Copyright (c) 2024 Realtek Semiconductor Corp.
 # SPDX-License-Identifier: Apache-2.0
 
 zephyr_compile_options(-mcmse)
 
+set(LIB_PATH ${ZEPHYR_CURRENT_MODULE_DIR}/zephyr/blobs/ameba/${CONFIG_SOC_SERIES}/lib)
+
+set(WIFI_LIB_PATH ${LIB_PATH})
+zephyr_link_libraries_ifdef(CONFIG_WIFI_AMEBA
+  ${WIFI_LIB_PATH}/lib_wifi_whc_ap.a
+  ${WIFI_LIB_PATH}/lib_rtw_event.a
+  ${WIFI_LIB_PATH}/lib_wifi_api.a
+  ${WIFI_LIB_PATH}/lib_wpa_lite.a
+  ${WIFI_LIB_PATH}/lib_wifi_common.a
+  ${WIFI_LIB_PATH}/lib_coex_api.a
+  ${WIFI_LIB_PATH}/lib_wifi_rtk_app.a
+)
 zephyr_include_directories(
   include
   source/fwlib/include
@@ -17,6 +29,9 @@ zephyr_library_sources(
   source/fwlib/ram_common/ameba_clk.c
   source/fwlib/ram_common/ameba_rcc.c
   source/fwlib/ram_common/ameba_rtc.c
+  source/fwlib/ram_common/ameba_arch.c
+  source/fwlib/ram_common/ameba_ipc_api.c
+  source/fwlib/ram_common/ameba_ipc_ram.c
 )
 
 # used by driver, need use zephyr_library_sources_ifdef
@@ -40,40 +55,15 @@ zephyr_library_sources_ifdef(CONFIG_COUNTER_TMR_AMEBA source/fwlib/ram_common/am
 zephyr_library_sources_ifdef(CONFIG_COUNTER_TMR_AMEBA source/fwlib/ram_common/ameba_ups.c)
 zephyr_library_sources_ifdef(CONFIG_UART_AMEBA source/fwlib/ram_common/ameba_uart.c)
 zephyr_library_sources_ifdef(CONFIG_TEMP_AMEBA source/fwlib/ram_common/ameba_thermal.c)
-zephyr_library_sources_ifdef(CONFIG_REALTEK_AMEBA_ZEPHYR_USB source/fwlib/ram_common/ameba_usb.c)
 zephyr_library_sources_ifdef(CONFIG_WIFI_AMEBA source/fwlib/ram_common/ameba_pmu.c)
 zephyr_library_sources_ifdef(CONFIG_WIFI_AMEBA source/fwlib/ram_common/ameba_pmctimer.c)
 zephyr_library_sources_ifdef(CONFIG_AMEBA_PPE source/fwlib/ram_common/ameba_ppe.c)
+zephyr_library_sources_ifdef(CONFIG_SDHC_AMEBA source/fwlib/ram_common/ameba_sd.c)
+zephyr_library_sources_ifdef(CONFIG_SDHC_AMEBA source/fwlib/ram_common/ameba_sd_host.c)
 
 zephyr_link_libraries(
-  -T${CMAKE_CURRENT_SOURCE_DIR}/ld/ameba_rom_symbol_bcut_s.ld
+  -T${CMAKE_CURRENT_SOURCE_DIR}/ld/ameba_rom_symbol_bcut.ld
   -T${CMAKE_CURRENT_SOURCE_DIR}/ld/ameba_rom_symbol_bcut_wifi.ld
 )
 
-# west sign
-if(CONFIG_SOC_AMEBA_NP_IMAGE)
-  file(GLOB blob_bin_file "${ZEPHYR_HAL_REALTEK_MODULE_DIR}/zephyr/blobs/${CONFIG_SOC_SERIES}/bin/*.bin")
-
-  if(blob_bin_file)
-    set(python_script_args
-      --soc ${CONFIG_SOC_SERIES}
-      --bin-file ${ZEPHYR_BINARY_DIR}/${KERNEL_BIN_NAME}
-      --out-dir ${CMAKE_BINARY_DIR}
-      --module-dir ${ZEPHYR_HAL_REALTEK_MODULE_DIR}
-    )
-
-    add_custom_target(zephyr.raw.map ALL
-      DEPENDS ${ZEPHYR_BINARY_DIR}/${KERNEL_NAME}.raw.map
-    )
-
-    add_custom_command(
-      OUTPUT ${ZEPHYR_BINARY_DIR}/${KERNEL_NAME}.raw.map
-      COMMAND ${CMAKE_NM} ${ZEPHYR_BINARY_DIR}/${KERNEL_ELF_NAME} | sort > ${ZEPHYR_BINARY_DIR}/${KERNEL_NAME}.raw.map
-      COMMAND ${CMAKE_OBJDUMP} -d ${ZEPHYR_BINARY_DIR}/${KERNEL_ELF_NAME} > ${ZEPHYR_BINARY_DIR}/${KERNEL_NAME}.asm
-      COMMAND ${PYTHON_EXECUTABLE} ${ZEPHYR_HAL_REALTEK_MODULE_DIR}/ameba/scripts/merge_bin.py ${python_script_args}
-      DEPENDS ${ZEPHYR_BINARY_DIR}/${KERNEL_ELF_NAME} ${blob_bin_file} ${CMAKE_CURRENT_SOURCE_DIR}/manifest.json5
-    )
-  else()
-    message(WARNING "Missing Realtek blobs. Run: `west blobs fetch hal_realtek`")
-  endif()
-endif()
+add_subdirectory_ifdef(CONFIG_AMEBA_MJPEG source/fwlib/jpeg_decoder)
diff --git a/ameba/amebaG2/Kconfig b/ameba/amebag2/Kconfig
similarity index 100%
rename from ameba/amebaG2/Kconfig
rename to ameba/amebag2/Kconfig
diff --git a/ameba/amebaG2/ameba_layout.ld b/ameba/amebag2/ameba_layout.ld
similarity index 100%
rename from ameba/amebaG2/ameba_layout.ld
rename to ameba/amebag2/ameba_layout.ld
diff --git a/ameba/amebaG2/include/platform_autoconf.h b/ameba/amebag2/include/platform_autoconf.h
similarity index 83%
rename from ameba/amebaG2/include/platform_autoconf.h
rename to ameba/amebag2/include/platform_autoconf.h
index e7d32c98..2ce39ea9 100644
--- a/ameba/amebaG2/include/platform_autoconf.h
+++ b/ameba/amebag2/include/platform_autoconf.h
@@ -20,8 +20,6 @@
 #define CONFIG_SUPPORT_ATCMD 1
 #define CONFIG_ATCMD_MANUAL_TEST 1
 #define CONFIG_ATCMD_NETWORK 1
-#define CONFIG_ASSERTION_ENABLE 1
-#define CONFIG_VFS_LITTLEFS_INCLUDED 1
 #define CONFIG_BACK_TRACE_DEPTH_LIMIT 8
 #define CONFIG_WHC_WIFI_API_PATH 1
 #define CONFIG_KM4TZ_AS_AP 1
@@ -29,11 +27,7 @@
 #define CONFIG_WLAN 1
 #define CONFIG_WHC_INTF_IPC 1
 #define CONFIG_LWIP_LAYER 1
-
 #define CONFIG_USE_MBEDTLS_ROM_ALG 1
-#define CONFIG_MBEDTLS_ENABLED 1
-#define CONFIG_MBEDTLS_SSL_IN_CONTENT_LEN 16384
-#define CONFIG_MBEDTLS_SSL_OUT_CONTENT_LEN 4096
 //#define CONFIG_BT_COEXIST 1
 #define CONFIG_COEXIST_HOST 1
 #define CONFIG_LINK_ROM_SYMB 1
diff --git a/ameba/amebaG2/ld/ameba_rom_symbol_bcut.ld b/ameba/amebag2/ld/ameba_rom_symbol_bcut.ld
similarity index 100%
rename from ameba/amebaG2/ld/ameba_rom_symbol_bcut.ld
rename to ameba/amebag2/ld/ameba_rom_symbol_bcut.ld
diff --git a/ameba/amebaG2/ld/ameba_rom_symbol_bcut_s.ld b/ameba/amebag2/ld/ameba_rom_symbol_bcut_s.ld
similarity index 100%
rename from ameba/amebaG2/ld/ameba_rom_symbol_bcut_s.ld
rename to ameba/amebag2/ld/ameba_rom_symbol_bcut_s.ld
diff --git a/ameba/amebaG2/ld/ameba_rom_symbol_bcut_wifi.ld b/ameba/amebag2/ld/ameba_rom_symbol_bcut_wifi.ld
similarity index 100%
rename from ameba/amebaG2/ld/ameba_rom_symbol_bcut_wifi.ld
rename to ameba/amebag2/ld/ameba_rom_symbol_bcut_wifi.ld
diff --git a/ameba/amebaG2/manifest.json5 b/ameba/amebag2/manifest.json5
similarity index 100%
rename from ameba/amebaG2/manifest.json5
rename to ameba/amebag2/manifest.json5
diff --git a/ameba/amebaG2/source/fwlib/include/ameba.h b/ameba/amebag2/source/fwlib/include/ameba.h
similarity index 100%
rename from ameba/amebaG2/source/fwlib/include/ameba.h
rename to ameba/amebag2/source/fwlib/include/ameba.h
diff --git a/ameba/amebaG2/source/fwlib/include/ameba_a2c.h b/ameba/amebag2/source/fwlib/include/ameba_a2c.h
similarity index 97%
rename from ameba/amebaG2/source/fwlib/include/ameba_a2c.h
rename to ameba/amebag2/source/fwlib/include/ameba_a2c.h
index ecc508ae..4f9c1a3f 100644
--- a/ameba/amebaG2/source/fwlib/include/ameba_a2c.h
+++ b/ameba/amebag2/source/fwlib/include/ameba_a2c.h
@@ -567,23 +567,12 @@ typedef struct {
 	u32 DLC;     /*!< Specifies the length of the frame that will be
                         transmitted. This parameter can be a value between
                         0 to 8 */
-
-	u32 ESI;     /*!< Specifies the FD frame esi bit, indicate error passive of message sending node,
-  		read bit, should always write 0, hardware automatic fill*/
-
-	u32 BRS;     /*!< Specifies the FD frame brs bit, indicate switch bit timing*/
-
-	u32 EDL;     /*!< Specifies the FD frame edl bit, indicate it's a FD frame*/
-
-	__attribute__((aligned(4)))
-	u8 Data[64]; /*!< Contains the data to be transmitted. It ranges from 0
-                        to 0xFF. */
-
-	u32 IDE_MASK;     /*!< Specifies the IDE MASK, ####*/
-
-	u32 ID_MASK;     /*!< Specifies the ID MASK, ####*/
-
-	u32 RTR_Mask;     /*!< Specifies the RTR MASK, ####*/
+	union {
+		/** Payload data accessed as unsigned 8 bit values. */
+		uint8_t Data[64];
+		/** Payload data accessed as unsigned 32 bit values. */
+		uint32_t Data_32[16];
+	};
 } A2C_TxMsgTypeDef;
 
 /**
@@ -618,16 +607,12 @@ typedef struct {
 	u32 DLC;     /*!< Specifies the length of the frame that will be
                         transmitted. This parameter can be a value between
                         0 to 8*/
-	u32 ESI;     /*!< Specifies the FD frame esi bit, indicate error passive of message sending node,
-  		read bit, should always write 0, hardware automatic fill*/
-
-	u32 BRS;     /*!< Specifies the FD frame brs bit, indicate switch bit timing*/
-
-	u32 EDL;     /*!< Specifies the FD frame edl bit, indicate it's a FD frame*/
-
-	__attribute__((aligned(4)))
-	u8 Data[64]; /*!< Contains the data to be transmitted. It ranges from 0
-                        to 0xFF. */
+	union {
+		/** Payload data accessed as unsigned 8 bit values. */
+		uint8_t Data[64];
+		/** Payload data accessed as unsigned 32 bit values. */
+		uint32_t Data_32[16];
+	};
 
 	u32 ID_MASK;     /*!< Specifies the ID MASK*/
 
@@ -652,10 +637,10 @@ typedef struct {
 /** @defgroup A2C_WORK_MODE_define
   * @{
   */
-#define A2C_NORMAL_MODE					        ((u32)0x00000000)
-#define A2C_SILENCE_MODE					        ((u32)0x00000001)
-#define A2C_EXT_LOOPBACK_MODE					  ((u32)0x00000002)
-#define A2C_INT_LOOPBACK_MODE            ((u32)0x00000003)
+#define A2C_NORMAL_MODE					          ((u32)0x00000000)
+#define A2C_SILENCE_MODE					        ((u32)0x00000000)
+#define A2C_EXT_LOOPBACK_MODE					    ((u32)0x00000001)
+#define A2C_INT_LOOPBACK_MODE             ((u32)0x00000002)
 #define IS_A2C_WORK_MODE(MODE) (((MODE) == A2C_NORMAL_MODE) || \
 									((MODE) == A2C_SILENCE_MODE) || \
 									((MODE) == A2C_EXT_LOOPBACK_MODE) || \
@@ -964,4 +949,4 @@ struct A2C_DevTable {
 extern const struct A2C_DevTable A2C_DEV_TABLE[MAX_A2C_INDEX];
 
 
-#endif
\ No newline at end of file
+#endif
diff --git a/ameba/amebaG2/source/fwlib/include/ameba_adc.h b/ameba/amebag2/source/fwlib/include/ameba_adc.h
similarity index 99%
rename from ameba/amebaG2/source/fwlib/include/ameba_adc.h
rename to ameba/amebag2/source/fwlib/include/ameba_adc.h
index c92d16f1..372be27a 100644
--- a/ameba/amebaG2/source/fwlib/include/ameba_adc.h
+++ b/ameba/amebag2/source/fwlib/include/ameba_adc.h
@@ -900,4 +900,4 @@ _LONG_CALL_ u32 ADC_GetSampleValue(s32 VolMV);
 
 /* MANUAL_GEN_END */
 
-#endif
\ No newline at end of file
+#endif
diff --git a/ameba/amebaG2/source/fwlib/include/ameba_aes.h b/ameba/amebag2/source/fwlib/include/ameba_aes.h
similarity index 99%
rename from ameba/amebaG2/source/fwlib/include/ameba_aes.h
rename to ameba/amebag2/source/fwlib/include/ameba_aes.h
index 44501a2b..6e2343bc 100644
--- a/ameba/amebaG2/source/fwlib/include/ameba_aes.h
+++ b/ameba/amebag2/source/fwlib/include/ameba_aes.h
@@ -868,4 +868,4 @@ _LONG_CALL_ int crypto_gcm_auth_decrypt(u8 key_id, u32 key_len_bits, u32 len, u8
 /** @} */
 
 /* MANUAL_GEN_END */
-#endif
\ No newline at end of file
+#endif
diff --git a/ameba/amebaG2/source/fwlib/include/ameba_aontimer.h b/ameba/amebag2/source/fwlib/include/ameba_aontimer.h
similarity index 100%
rename from ameba/amebaG2/source/fwlib/include/ameba_aontimer.h
rename to ameba/amebag2/source/fwlib/include/ameba_aontimer.h
diff --git a/ameba/amebaG2/source/fwlib/include/ameba_arch.h b/ameba/amebag2/source/fwlib/include/ameba_arch.h
similarity index 100%
rename from ameba/amebaG2/source/fwlib/include/ameba_arch.h
rename to ameba/amebag2/source/fwlib/include/ameba_arch.h
diff --git a/ameba/amebaG2/source/fwlib/include/ameba_audio.h b/ameba/amebag2/source/fwlib/include/ameba_audio.h
similarity index 100%
rename from ameba/amebaG2/source/fwlib/include/ameba_audio.h
rename to ameba/amebag2/source/fwlib/include/ameba_audio.h
diff --git a/ameba/amebaG2/source/fwlib/include/ameba_audio_clock.h b/ameba/amebag2/source/fwlib/include/ameba_audio_clock.h
similarity index 100%
rename from ameba/amebaG2/source/fwlib/include/ameba_audio_clock.h
rename to ameba/amebag2/source/fwlib/include/ameba_audio_clock.h
diff --git a/ameba/amebaG2/source/fwlib/include/ameba_backup_reg.h b/ameba/amebag2/source/fwlib/include/ameba_backup_reg.h
similarity index 100%
rename from ameba/amebaG2/source/fwlib/include/ameba_backup_reg.h
rename to ameba/amebag2/source/fwlib/include/ameba_backup_reg.h
diff --git a/ameba/amebaG2/source/fwlib/include/ameba_boot.h b/ameba/amebag2/source/fwlib/include/ameba_boot.h
similarity index 100%
rename from ameba/amebaG2/source/fwlib/include/ameba_boot.h
rename to ameba/amebag2/source/fwlib/include/ameba_boot.h
diff --git a/ameba/amebaG2/source/fwlib/include/ameba_bor.h b/ameba/amebag2/source/fwlib/include/ameba_bor.h
similarity index 99%
rename from ameba/amebaG2/source/fwlib/include/ameba_bor.h
rename to ameba/amebag2/source/fwlib/include/ameba_bor.h
index a08ebf87..19dfa415 100644
--- a/ameba/amebaG2/source/fwlib/include/ameba_bor.h
+++ b/ameba/amebag2/source/fwlib/include/ameba_bor.h
@@ -100,4 +100,4 @@ void BOR_DbncSet(u32 Option, u32 Dbnc_Value);
 void BOR_ClearINT(void);
 void BOR_ModeSet(u32 Option);
 
-#endif //_AMEBA_BOR_H_
\ No newline at end of file
+#endif //_AMEBA_BOR_H_
diff --git a/ameba/amebaG2/source/fwlib/include/ameba_cache.h b/ameba/amebag2/source/fwlib/include/ameba_cache.h
similarity index 100%
rename from ameba/amebaG2/source/fwlib/include/ameba_cache.h
rename to ameba/amebag2/source/fwlib/include/ameba_cache.h
diff --git a/ameba/amebaG2/source/fwlib/include/ameba_captouch.h b/ameba/amebag2/source/fwlib/include/ameba_captouch.h
similarity index 99%
rename from ameba/amebaG2/source/fwlib/include/ameba_captouch.h
rename to ameba/amebag2/source/fwlib/include/ameba_captouch.h
index bddc2b30..6989d9fd 100644
--- a/ameba/amebaG2/source/fwlib/include/ameba_captouch.h
+++ b/ameba/amebag2/source/fwlib/include/ameba_captouch.h
@@ -821,4 +821,4 @@ u8 CapTouch_RXGDMA_Init(CAPTOUCH_TypeDef *CapTouch, GDMA_InitTypeDef *GDMA_InitS
 
 /* MANUAL_GEN_END */
 
-#endif
\ No newline at end of file
+#endif
diff --git a/ameba/amebaG2/source/fwlib/include/ameba_chipinfo.h b/ameba/amebag2/source/fwlib/include/ameba_chipinfo.h
similarity index 100%
rename from ameba/amebaG2/source/fwlib/include/ameba_chipinfo.h
rename to ameba/amebag2/source/fwlib/include/ameba_chipinfo.h
diff --git a/ameba/amebaG2/source/fwlib/include/ameba_clk.h b/ameba/amebag2/source/fwlib/include/ameba_clk.h
similarity index 96%
rename from ameba/amebaG2/source/fwlib/include/ameba_clk.h
rename to ameba/amebag2/source/fwlib/include/ameba_clk.h
index b4e1e93d..a3121fc1 100644
--- a/ameba/amebaG2/source/fwlib/include/ameba_clk.h
+++ b/ameba/amebag2/source/fwlib/include/ameba_clk.h
@@ -7,6 +7,10 @@
 #ifndef _AMEBA_CLK_H_
 #define _AMEBA_CLK_H_
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /** @addtogroup AmebaD_Platform
   * @{
   */
@@ -109,6 +113,17 @@
   * @}
   */
 
+/** @defgroup SDM_USER_DEFINED_param_definitions
+  * @{
+  */
+#define SDM_OBS_CYC_DEFAULT		1024
+#define SDM_OBS_REF_CYC_DEFAULT		312500
+#define SDM_OBS_REF_CYC_MODIFY		312503
+#define SDM_XTAL_PERIOD_DEFAULT   102400
+/**
+  * @}
+  */
+
 /** @defgroup XTAL_CLK_definitions
 * @{
 */
@@ -179,6 +194,7 @@
   */
 _LONG_CALL_ void SDM32K_Enable(void);
 _LONG_CALL_ void SDM32K_TimerCalEnable(u32 RTCCalibration);
+_LONG_CALL_ void SDM32K_CalFactorModify(u32 newstatus);
 /**
   * @}
   */
@@ -336,4 +352,8 @@ u32 OSC_CalResult_Get(u8 cal_clk);
 void XTAL_INIT(void);
 void XTAL_AACK(void);
 
+#ifdef __cplusplus
+}
+#endif
+
 #endif //_AMEBA_CLK_H_
\ No newline at end of file
diff --git a/ameba/amebaG2/source/fwlib/include/ameba_crypto.h b/ameba/amebag2/source/fwlib/include/ameba_crypto.h
similarity index 100%
rename from ameba/amebaG2/source/fwlib/include/ameba_crypto.h
rename to ameba/amebag2/source/fwlib/include/ameba_crypto.h
diff --git a/ameba/amebaG2/source/fwlib/include/ameba_data_flash.h b/ameba/amebag2/source/fwlib/include/ameba_data_flash.h
similarity index 100%
rename from ameba/amebaG2/source/fwlib/include/ameba_data_flash.h
rename to ameba/amebag2/source/fwlib/include/ameba_data_flash.h
diff --git a/ameba/amebaG2/source/fwlib/include/ameba_data_nand_flash.h b/ameba/amebag2/source/fwlib/include/ameba_data_nand_flash.h
similarity index 100%
rename from ameba/amebaG2/source/fwlib/include/ameba_data_nand_flash.h
rename to ameba/amebag2/source/fwlib/include/ameba_data_nand_flash.h
diff --git a/ameba/amebaG2/source/fwlib/include/ameba_debug_port.h b/ameba/amebag2/source/fwlib/include/ameba_debug_port.h
similarity index 100%
rename from ameba/amebaG2/source/fwlib/include/ameba_debug_port.h
rename to ameba/amebag2/source/fwlib/include/ameba_debug_port.h
diff --git a/ameba/amebaG2/source/fwlib/include/ameba_debugtimer.h b/ameba/amebag2/source/fwlib/include/ameba_debugtimer.h
similarity index 99%
rename from ameba/amebaG2/source/fwlib/include/ameba_debugtimer.h
rename to ameba/amebag2/source/fwlib/include/ameba_debugtimer.h
index 993f0583..2605087a 100644
--- a/ameba/amebaG2/source/fwlib/include/ameba_debugtimer.h
+++ b/ameba/amebag2/source/fwlib/include/ameba_debugtimer.h
@@ -288,4 +288,4 @@ __STATIC_INLINE void DTimer_ScratchSet(u32 NewVaule)
 
 /* MANUAL_GEN_END */
 
-#endif
\ No newline at end of file
+#endif
diff --git a/ameba/amebaG2/source/fwlib/include/ameba_delay.h b/ameba/amebag2/source/fwlib/include/ameba_delay.h
similarity index 98%
rename from ameba/amebaG2/source/fwlib/include/ameba_delay.h
rename to ameba/amebag2/source/fwlib/include/ameba_delay.h
index 064ee7e3..c8eeb455 100644
--- a/ameba/amebaG2/source/fwlib/include/ameba_delay.h
+++ b/ameba/amebag2/source/fwlib/include/ameba_delay.h
@@ -58,4 +58,4 @@ _LONG_CALL_ void DelayNop(u32 count);
 extern u32 RBSS_UDELAY_CLK;
 extern u8 RBSS_UDELAY_DIV;
 
-#endif//_AMEBA_DELAY_H_
\ No newline at end of file
+#endif//_AMEBA_DELAY_H_
diff --git a/ameba/amebaG2/source/fwlib/include/ameba_ethernet.h b/ameba/amebag2/source/fwlib/include/ameba_ethernet.h
similarity index 98%
rename from ameba/amebaG2/source/fwlib/include/ameba_ethernet.h
rename to ameba/amebag2/source/fwlib/include/ameba_ethernet.h
index bbf0c247..d9a076f8 100644
--- a/ameba/amebaG2/source/fwlib/include/ameba_ethernet.h
+++ b/ameba/amebag2/source/fwlib/include/ameba_ethernet.h
@@ -2243,10 +2243,18 @@ typedef struct {
 /* MANUAL_GEN_START */
 
 // Please add your definitions here
-/// Defines the packet buffer size
-#define ETH_PKT_BUFF_SZ                 1600 //1514?
-/// Defines the MAC address length
-#define ETH_MAC_ADDR_LEN                6
+/* Define Ethernet Packet Field length */
+#define ETH_MAC_ADDR_LEN        (6)
+#define ETH_HEADER_LEN          (2 * ETH_MAC_ADDR_LEN + 2) /* Ethernet frame header size: Dest addr(6 Bytes) + Src addr(6 Bytes) + length/type(2 Bytes) */
+#define ETH_VLAN_TAG_LEN        (4)  /* Optional 802.1q VLAN Tag length */
+#define ETH_CRC_LEN             (4)  /* Ethernet frame CRC length */
+
+#define ETH_PAYLOAD_MAX_LEN     (1500)     /*< Ethernet maximum payload size (bytes) */
+#define ETH_PAYLOAD_MIN_LEN     (46)       /* Minimum Ethernet payload size */
+#define ETH_JUMBO_FRAME_PAYLOAD_LEN (16*1024) /* Jumbo frame payload size */
+
+#define ETH_PKT_MAX_SIZE        (ETH_HEADER_LEN + ETH_VLAN_TAG_LEN + ETH_PAYLOAD_MAX_LEN + ETH_CRC_LEN) /* Maximum frame size (1522 Bytes) */
+
 /// Defines the delay period when checking the own bit of the Tx/Rx descriptors
 #define ETH_OWN_BIT_UPDATE_PERIOD       10
 /// Defines the max. timeout value when checking the flag of MDIO operations
@@ -2369,24 +2377,28 @@ typedef struct {
   \brief  Defines FEMAC Tx command descriptor
 */
 #define FEMAC_TX_DSC_SHIFT_OWN          31
-#define FEMAC_TX_DSC_BIT_OWN            ((u32)0x00000001 << 31)
+#define FEMAC_TX_DSC_BIT_OWN            ((u32)0x00000001 << FEMAC_TX_DSC_SHIFT_OWN)
 #define FEMAC_TX_DSC_SHIFT_EOR          30
-#define FEMAC_TX_DSC_BIT_EOR            ((u32)0x00000001 << 30)
+#define FEMAC_TX_DSC_BIT_EOR            ((u32)0x00000001 << FEMAC_TX_DSC_SHIFT_EOR)
 #define FEMAC_TX_DSC_SHIFT_FS           29
-#define FEMAC_TX_DSC_BIT_FS             ((u32)0x00000001 << 29)
+#define FEMAC_TX_DSC_BIT_FS             ((u32)0x00000001 << FEMAC_TX_DSC_SHIFT_FS)
 #define FEMAC_TX_DSC_SHIFT_LS           28
-#define FEMAC_TX_DSC_BIT_LS             ((u32)0x00000001 << 28)
+#define FEMAC_TX_DSC_BIT_LS             ((u32)0x00000001 << FEMAC_TX_DSC_SHIFT_LS)
+#define FEMAC_TX_DSC_SHIFT_IPCS         27
+#define FEMAC_TX_DSC_BIT_IPCS           ((u32)0x00000001 << FEMAC_TX_DSC_SHIFT_IPCS)
+#define FEMAC_TX_DSC_SHIFT_L4CS         26
+#define FEMAC_TX_DSC_BIT_L4CS           ((u32)0x00000001 << FEMAC_TX_DSC_SHIFT_L4CS)
 #define FEMAC_TX_DSC_SHIFT_CRC          23
-#define FEMAC_TX_DSC_BIT_CRC            ((u32)0x00000001 << 23)
-
+#define FEMAC_TX_DSC_BIT_CRC            ((u32)0x00000001 << FEMAC_TX_DSC_SHIFT_CRC)
+#define FEMAC_TX_DSC_BIT_SIZE(dw1)     ((u32)((dw1) & 0x1FFFF))
 /**
   \brief  Defines FEMAC Rx command descriptor
 */
 #define FEMAC_RX_DSC_SHIFT_OWN          31
-#define FEMAC_RX_DSC_BIT_OWN            ((u32)0x00000001 << 31)
+#define FEMAC_RX_DSC_BIT_OWN            ((u32)0x00000001 << FEMAC_RX_DSC_SHIFT_OWN)
 #define FEMAC_RX_DSC_SHIFT_EOR          30
-#define FEMAC_RX_DSC_BIT_EOR            ((u32)0x00000001 << 30)
-
+#define FEMAC_RX_DSC_BIT_EOR            ((u32)0x00000001 << FEMAC_RX_DSC_SHIFT_EOR)
+#define FEMAC_RX_DSC_LEN(dw1)           ((u32)((dw1) & 0x0FFF))
 /**
   \brief  Defines FEPHY register page number
 */
@@ -2422,6 +2434,11 @@ typedef struct {
   * @}
   */
 
+/**
+  \brief  Defines MDIO Wait Time(us)
+*/
+#define MDIO_WAIT_TIME (64)
+
 /**
   \brief  Defines the FEPHY register address
 */
@@ -2747,8 +2764,8 @@ void Ethernet_SetDescAddr(ETH_InitTypeDef *ETH_InitStruct);
 void Ethernet_SetMacAddr(u8 *ETH_MacAddr);
 void Ethernet_StructInit(ETH_InitTypeDef *ETH_InitStruct);
 u32 Ethernet_init(ETH_InitTypeDef *ETH_InitStruct);
-u16 Ethernet_Read_PhyReg(u16 page, u16 reg_addr);
-u32 Ethernet_Write_PhyReg(u16 page, u16 reg_addr, u16 data);
+int Ethernet_ReadPhyReg(uint8_t phy_id, uint8_t reg_addr, uint16_t *data);
+int Ethernet_WritePhyReg(uint8_t phy_id, uint8_t reg_addr, uint16_t data);
 u32 Ethernet_GetLinkStatus(void);
 void Ethernet_SetRefclkDirec(u32 refclk_mode);
 void Ethernet_OutputClk2Phy(u32 pin);
@@ -2772,4 +2789,4 @@ extern int link_is_up;
 /** @} */
 
 
-#endif
\ No newline at end of file
+#endif
diff --git a/ameba/amebaG2/source/fwlib/include/ameba_flashclk.h b/ameba/amebag2/source/fwlib/include/ameba_flashclk.h
similarity index 95%
rename from ameba/amebaG2/source/fwlib/include/ameba_flashclk.h
rename to ameba/amebag2/source/fwlib/include/ameba_flashclk.h
index 752cce1c..0831d0d5 100644
--- a/ameba/amebaG2/source/fwlib/include/ameba_flashclk.h
+++ b/ameba/amebag2/source/fwlib/include/ameba_flashclk.h
@@ -30,4 +30,4 @@ typedef struct {
 void flash_highspeed_setup(void);
 void Combo_SPIC_Init(void);
 
-#endif  //_AMEBA_FLASH_CLK_H
\ No newline at end of file
+#endif  //_AMEBA_FLASH_CLK_H
diff --git a/ameba/amebaG2/source/fwlib/include/ameba_gdma.h b/ameba/amebag2/source/fwlib/include/ameba_gdma.h
similarity index 99%
rename from ameba/amebaG2/source/fwlib/include/ameba_gdma.h
rename to ameba/amebag2/source/fwlib/include/ameba_gdma.h
index 812b75a9..0db4fbe6 100644
--- a/ameba/amebaG2/source/fwlib/include/ameba_gdma.h
+++ b/ameba/amebag2/source/fwlib/include/ameba_gdma.h
@@ -1309,6 +1309,7 @@ _LONG_CALL_ void GDMA_Resume(u8 GDMA_Index, u8 GDMA_ChNum);
 _LONG_CALL_ u8   GDMA_Abort(u8 GDMA_Index, u8 GDMA_ChNum);
 _LONG_CALL_ void GDMA_SourceGather(u8 GDMA_Index, u8 GDMA_ChNum, u32 Src_GatherCount, u32 Src_GatherInterval);
 _LONG_CALL_ void GDMA_DestinationScatter(u8 GDMA_Index, u8 GDMA_ChNum, u32 Dst_ScatterCount, u32 Dst_ScatterInterval);
+_LONG_CALL_ u8   GDMA_ChannelIsActive(u8 GDMA_Index, u8 GDMA_ChNum);
 /**
   * @}
   */
diff --git a/ameba/amebaG2/source/fwlib/include/ameba_gpio.h b/ameba/amebag2/source/fwlib/include/ameba_gpio.h
similarity index 100%
rename from ameba/amebaG2/source/fwlib/include/ameba_gpio.h
rename to ameba/amebag2/source/fwlib/include/ameba_gpio.h
diff --git a/ameba/amebaG2/source/fwlib/include/ameba_i2c.h b/ameba/amebag2/source/fwlib/include/ameba_i2c.h
similarity index 99%
rename from ameba/amebaG2/source/fwlib/include/ameba_i2c.h
rename to ameba/amebag2/source/fwlib/include/ameba_i2c.h
index 9e176bed..e52a9b35 100644
--- a/ameba/amebaG2/source/fwlib/include/ameba_i2c.h
+++ b/ameba/amebag2/source/fwlib/include/ameba_i2c.h
@@ -939,4 +939,4 @@ extern u32 IC_FS_SCL_LCNT_TRIM;
 
 /* MANUAL_GEN_END */
 
-#endif
\ No newline at end of file
+#endif
diff --git a/ameba/amebaG2/source/fwlib/include/ameba_inic.h b/ameba/amebag2/source/fwlib/include/ameba_inic.h
similarity index 99%
rename from ameba/amebaG2/source/fwlib/include/ameba_inic.h
rename to ameba/amebag2/source/fwlib/include/ameba_inic.h
index 19e4506b..3117708a 100644
--- a/ameba/amebaG2/source/fwlib/include/ameba_inic.h
+++ b/ameba/amebag2/source/fwlib/include/ameba_inic.h
@@ -154,4 +154,4 @@ typedef struct {
   * @}
   */
 
-#endif
\ No newline at end of file
+#endif
diff --git a/ameba/amebaG2/source/fwlib/include/ameba_ipc.h b/ameba/amebag2/source/fwlib/include/ameba_ipc.h
similarity index 99%
rename from ameba/amebaG2/source/fwlib/include/ameba_ipc.h
rename to ameba/amebag2/source/fwlib/include/ameba_ipc.h
index 1fc08d22..ab19fae9 100644
--- a/ameba/amebaG2/source/fwlib/include/ameba_ipc.h
+++ b/ameba/amebag2/source/fwlib/include/ameba_ipc.h
@@ -322,4 +322,4 @@ extern const IPC_INIT_TABLE  ipc_init_config[];
 
 /* MANUAL_GEN_END */
 
-#endif
\ No newline at end of file
+#endif
diff --git a/ameba/amebaG2/source/fwlib/include/ameba_ipc_api.h b/ameba/amebag2/source/fwlib/include/ameba_ipc_api.h
similarity index 99%
rename from ameba/amebaG2/source/fwlib/include/ameba_ipc_api.h
rename to ameba/amebag2/source/fwlib/include/ameba_ipc_api.h
index 25b55ef4..14fa1a03 100644
--- a/ameba/amebaG2/source/fwlib/include/ameba_ipc_api.h
+++ b/ameba/amebag2/source/fwlib/include/ameba_ipc_api.h
@@ -64,4 +64,4 @@ u32 ipc_send_message(u32 IPC_Dir, u8 IPC_ChNum, PIPC_MSG_STRUCT IPC_Msg);
 PIPC_MSG_STRUCT ipc_get_message(u32 IPC_Dir, u8 IPC_ChNum);
 extern IPC_IRQ_FUN IPC_IrqHandler[32];
 
-#endif
\ No newline at end of file
+#endif
diff --git a/ameba/amebaG2/source/fwlib/include/ameba_ipccfg.h b/ameba/amebag2/source/fwlib/include/ameba_ipccfg.h
similarity index 100%
rename from ameba/amebaG2/source/fwlib/include/ameba_ipccfg.h
rename to ameba/amebag2/source/fwlib/include/ameba_ipccfg.h
diff --git a/ameba/amebaG2/source/fwlib/include/ameba_ir.h b/ameba/amebag2/source/fwlib/include/ameba_ir.h
similarity index 99%
rename from ameba/amebaG2/source/fwlib/include/ameba_ir.h
rename to ameba/amebag2/source/fwlib/include/ameba_ir.h
index 2cb291ff..cbd63c0b 100644
--- a/ameba/amebaG2/source/fwlib/include/ameba_ir.h
+++ b/ameba/amebag2/source/fwlib/include/ameba_ir.h
@@ -453,4 +453,4 @@ void IR_ClearRxFIFO(IR_TypeDef *IRx);
 
 /* MANUAL_GEN_END */
 
-#endif
\ No newline at end of file
+#endif
diff --git a/ameba/amebaG2/source/fwlib/include/ameba_key_management_aes.h b/ameba/amebag2/source/fwlib/include/ameba_key_management_aes.h
similarity index 99%
rename from ameba/amebaG2/source/fwlib/include/ameba_key_management_aes.h
rename to ameba/amebag2/source/fwlib/include/ameba_key_management_aes.h
index 812589e7..9d035d22 100755
--- a/ameba/amebaG2/source/fwlib/include/ameba_key_management_aes.h
+++ b/ameba/amebag2/source/fwlib/include/ameba_key_management_aes.h
@@ -175,4 +175,4 @@ typedef struct {
                                        ((ID) == KM_AES_KEY_NS_SW2))
 
 /* MANUAL_GEN_END */
-#endif
\ No newline at end of file
+#endif
diff --git a/ameba/amebaG2/source/fwlib/include/ameba_key_management_hmac.h b/ameba/amebag2/source/fwlib/include/ameba_key_management_hmac.h
similarity index 99%
rename from ameba/amebaG2/source/fwlib/include/ameba_key_management_hmac.h
rename to ameba/amebag2/source/fwlib/include/ameba_key_management_hmac.h
index 4655031b..ac1c34bd 100755
--- a/ameba/amebaG2/source/fwlib/include/ameba_key_management_hmac.h
+++ b/ameba/amebag2/source/fwlib/include/ameba_key_management_hmac.h
@@ -140,4 +140,4 @@ typedef struct {
                                         ((ID) == KM_HMAC_KEY_NS_SW))
 /* MANUAL_GEN_END */
 
-#endif
\ No newline at end of file
+#endif
diff --git a/ameba/amebaG2/source/fwlib/include/ameba_lcdc.h b/ameba/amebag2/source/fwlib/include/ameba_lcdc.h
similarity index 99%
rename from ameba/amebaG2/source/fwlib/include/ameba_lcdc.h
rename to ameba/amebag2/source/fwlib/include/ameba_lcdc.h
index 9586beaa..dd63ad11 100644
--- a/ameba/amebaG2/source/fwlib/include/ameba_lcdc.h
+++ b/ameba/amebag2/source/fwlib/include/ameba_lcdc.h
@@ -1163,4 +1163,4 @@ extern u32 LCDC_SYS_CLK;// = 400000000;
 /* MANUAL_GEN_END */
 
 
-#endif
\ No newline at end of file
+#endif
diff --git a/ameba/amebaG2/source/fwlib/include/ameba_ledc_pro.h b/ameba/amebag2/source/fwlib/include/ameba_ledc_pro.h
similarity index 99%
rename from ameba/amebaG2/source/fwlib/include/ameba_ledc_pro.h
rename to ameba/amebag2/source/fwlib/include/ameba_ledc_pro.h
index 322df799..0d6b8560 100644
--- a/ameba/amebaG2/source/fwlib/include/ameba_ledc_pro.h
+++ b/ameba/amebag2/source/fwlib/include/ameba_ledc_pro.h
@@ -168,4 +168,4 @@ _LONG_CALL_ void pseudo_i2c_set_len(u32 len);
 
 /* MANUAL_GEN_END */
 
-#endif
\ No newline at end of file
+#endif
diff --git a/ameba/amebaG2/source/fwlib/include/ameba_loguart.h b/ameba/amebag2/source/fwlib/include/ameba_loguart.h
similarity index 99%
rename from ameba/amebaG2/source/fwlib/include/ameba_loguart.h
rename to ameba/amebag2/source/fwlib/include/ameba_loguart.h
index 62e5d1a8..5184f6ff 100644
--- a/ameba/amebaG2/source/fwlib/include/ameba_loguart.h
+++ b/ameba/amebag2/source/fwlib/include/ameba_loguart.h
@@ -865,4 +865,4 @@ _LONG_CALL_ void LOGUART_PutChar_RAM(u8 c);
 
 /* MANUAL_GEN_END */
 
-#endif
\ No newline at end of file
+#endif
diff --git a/ameba/amebaG2/source/fwlib/include/ameba_osc131k.h b/ameba/amebag2/source/fwlib/include/ameba_osc131k.h
similarity index 100%
rename from ameba/amebaG2/source/fwlib/include/ameba_osc131k.h
rename to ameba/amebag2/source/fwlib/include/ameba_osc131k.h
diff --git a/ameba/amebaG2/source/fwlib/include/ameba_ota.h b/ameba/amebag2/source/fwlib/include/ameba_ota.h
similarity index 100%
rename from ameba/amebaG2/source/fwlib/include/ameba_ota.h
rename to ameba/amebag2/source/fwlib/include/ameba_ota.h
diff --git a/ameba/amebaG2/source/fwlib/include/ameba_otpc.h b/ameba/amebag2/source/fwlib/include/ameba_otpc.h
similarity index 99%
rename from ameba/amebaG2/source/fwlib/include/ameba_otpc.h
rename to ameba/amebag2/source/fwlib/include/ameba_otpc.h
index f1f39cac..a7b2c0a2 100644
--- a/ameba/amebaG2/source/fwlib/include/ameba_otpc.h
+++ b/ameba/amebag2/source/fwlib/include/ameba_otpc.h
@@ -358,4 +358,4 @@ _LONG_CALL_ int OTP_Write8(u32 Addr, u8 Data);
 _LONG_CALL_ int OTP_Read32(u32 Addr, u32 *Data);
 /* MANUAL_GEN_END */
 
-#endif
\ No newline at end of file
+#endif
diff --git a/ameba/amebag2/source/fwlib/include/ameba_phy.h b/ameba/amebag2/source/fwlib/include/ameba_phy.h
new file mode 100644
index 00000000..a5216888
--- /dev/null
+++ b/ameba/amebag2/source/fwlib/include/ameba_phy.h
@@ -0,0 +1,149 @@
+/*
+ * Copyright (c) 2024 Realtek Semiconductor Corp.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+enum  eth_phy_type {
+	RTL_8721F,
+	RTL_8721G,
+};
+
+enum  eth_mode {
+	ETH_MAC_MODE,
+	ETH_PHY_MODE,
+};
+
+enum  phy_clk_mode {
+	EXTERNAL_50M,
+	EXTERNAL_25M,
+	INTERNAL_XTAL,
+};
+
+enum  phy_MMD_type {
+	RTK_MMD_TYPE,
+
+};
+
+enum  phy_address {
+	PHYID_0,
+	PHYID_1,
+	PHYID_2,
+	PHYID_3,
+};
+
+enum phy_mmd_access_mode {
+	PHY_MMD_ADDR,
+	PHY_MMD_DATA_NO_POST_INC,
+	PHY_MMD_DATA_RD_WR_POST_INC,
+	PHY_MMD_DATA_RD_POST_INC
+};
+
+/* MMD register mapping table */
+enum rtl8201fr_mmd_device_t {
+	RTL8201FR_MMD_DEV_PCS = 3,      /* PCS (Physical Coding Sublayer) MMD device address */
+	RTL8201FR_MMD_DEV_EEE_ADV = 7   /* EEE advertisement/ability MMD device address */
+};
+
+enum rtl8201fr_mmd_reg_t {
+	RTL8201FR_MMD_REG_EEEPC1R  = 0x0,   /* EEE PCS Control 1 Register Offset */
+	RTL8201FR_MMD_REG_EEEPS1R  = 0x01,  /* EEE PCS Status 1 Register Offset */
+	RTL8201FR_MMD_REG_EEECR    = 0x14,  /* EEE Capability Register Offset */
+	RTL8201FR_MMD_REG_EEEWER   = 0x16,  /* EEE Wake Error Register Offset */
+	RTL8201FR_MMD_REG_EEEAR    = 0x3c,  /* EEE Advertisement Register Offset */
+	RTL8201FR_MMD_REG_EEELPAR  = 0x3d   /* EEE Link Partner Ability Register Offset */
+};
+
+/* RTL8201FR Page0 Register 13: MACR Register (0x0D) */
+#define RTL8201FR_MACR_FUNC_ADDR_MASK       (0x3 << 14)         	/*[15:14] Function selection for MMD access*/
+#define RTL8201FR_MACR_FUNC_ADDR(x)         (((x) & 0x3) << 14)
+#define RTL8201FR_MACR_FUNC_ADDR_GET(x)		(((x) & 0x3) >> 14)
+#define RTL8201FR_MACR_DEVAD_MASK      		(0x1F << 0)				/*[4:0] MMD device address*/
+#define RTL8201FR_MACR_DEVAD(x)        		(((x) & 0x1F) << 0)
+#define RTL8201FR_MACR_DEVAD_GET(x)    		(((x) & 0x1F) >> 0)
+
+/* RTL8201FR Page0 Register 14: MAADR (MMD Access Address/Data Register) */
+#define RTL8201FR_MAADR_DATA_MASK        (0xFFFF << 0)     			/* [15:0] Address/Data field, used for MMD management via MACR/MAADR pair */
+#define RTL8201FR_MAADR_DATA(x)          (((x) & 0xFFFF) << 0)
+#define RTL8201FR_MAADR_DATA_GET(x)      (((x) & 0xFFFF) >> 0)
+
+
+/* --- Page 4: Energy Efficient Ethernet (EEE) --- */
+#define	RTL8201FR_PAGE4_REG_EEE_CAP_EN          (0x10)   /*!< EEE Capability Register (Page 4, Reg 21) */
+#define RTL8201FR_PAGE4_REG_EEE_CAP             (0x15)   /*!< EEE Capability Register (Page 4, Reg 21) */
+
+/* --- Page 7: Special/Custom registers --- */
+#define RTL8201FR_PAGE7_REG_RMII_MODE_SET		(0x10)   /*!< LED Mode Register (Page 7, Reg 11) */
+#define RTL8201FR_PAGE7_REG_CUSTOM_LED_SET      (0x11)   /*!< LED Mode Register (Page 7, Reg 11) */
+
+/*******************************************************************************
+ * RTL8201FR PAGE4 Registers
+ ******************************************************************************/
+
+/* Page4 Register 16: EEE Capability Enable Register */
+#define RTL8201FR_P4_16_EEE_10_CAP           (1U << 13)   /* [13] Enable EEE 10M capability */
+#define RTL8201FR_P4_16_EEE_NWAY_EN          (1U << 12)   /* [12] Enable Next Page Exchange for EEE 100M */
+#define RTL8201FR_P4_16_TX_QUIET_EN          (1U << 9)    /* [9] Enable turning off 100TX when TX Quiet State (recommended for EEE) */
+#define RTL8201FR_P4_16_RX_QUIET_EN          (1U << 8)    /* [8] Enable turning off 100RX when RX Quiet State (recommended for EEE) */
+
+/* Page4 Register 21: EEE Capability Register */
+#define RTL8201FR_P4_21_RG_DIS_LDVT          (1U << 12)   /* [12] Set 1: Disable line driver of the analog circuit */
+#define RTL8201FR_P4_21_EEE_100_CAP_GET(x)   (((x) >> 0) & 0x1) /* [0] Indicate link partner supports EEE 100M (NWay result, Read Only) */
+
+
+/*******************************************************************************
+ * RTL8201FR PAGE7 Registers
+ ******************************************************************************/
+
+/* Page7 Register 16: RMII Mode Setting Register (RMSR) */
+#define RTL8201FR_P7_16_RMII_CLK_DIR		 (1U << 12)			 /* [12] This bit sets type of TXC in RMII mode. */
+#define RTL8201FR_P7_16_RMII_TX_OFFSET(x)    (((x) & 0xF) << 8)  /* [11:8] Adjust RMII TX interface timing */
+#define RTL8201FR_P7_16_RMII_RX_OFFSET(x)    (((x) & 0xF) << 4)  /* [7:4]  Adjust RMII RX interface timing */
+#define RTL8201FR_P7_16_RMII_MODE            (1U << 3)           /* [3]    1: Set RMII mode (Must keep to 1) */
+#define RTL8201FR_P7_16_RMII_RXDV_SEL        (1U << 2)           /* [2]    1: CRS_DV pin is RXDV; 0: CRS_DV is CRS_DV signal */
+#define RTL8201FR_P7_16_RMII_RXDSEL          (1U << 1)           /* [1]    1: RMII data with SSD error; 0: RMII data only */
+
+/*******************************************************************************
+ * RTL8201FR MMD Register Mapping (accessed via MACR/MAADR)
+ ******************************************************************************/
+/* Device 3, Offset 0: EEEPCS Control 1 Register */
+#define RTL8201FR_EEEPC1R_CLK_STOP_EN      (0x1 << 10)   			/* [10] Enable RXC clock stop in LPI mode */
+
+/* Device 3, Offset 1: EEEPCS Status 1 Register (Read Only) */
+#define RTL8201FR_EEEPS1R_TX_LPI_RCVD_GET(x)    (((x) >> 11) & 0x1)	/* [11] TX PCS received LPI indication */
+#define RTL8201FR_EEEPS1R_RX_LPI_RCVD_GET(x)    (((x) >> 10) & 0x1)	/* [10] RX PCS received LPI indication */
+#define RTL8201FR_EEEPS1R_TX_LPI_IND_GET(x)     (((x) >> 9) & 0x1) 	/* [9] TX PCS LPI indication in progress */
+#define RTL8201FR_EEEPS1R_RX_LPI_IND_GET(x)     (((x) >> 8) & 0x1) 	/* [8] RX PCS LPI indication in progress */
+#define RTL8201FR_EEEPS1R_CLK_STOP_CAP_GET(x)   (((x) >> 6) & 0x1) 	/* [6] LPI TXC clock stop capability */
+
+/* Device 3, Offset 0x14: EEE Capability Register (Read Only) */
+#define RTL8201FR_EEECR_100BT_EEE_SUP_GET(x)    (((x) >> 1) & 0x1)  /* [1] 100Base-TX EEE support */
+
+/* Device 3, Offset 0x16: EEE Wake Error Register (Read Clear)*/
+#define RTL8201FR_EEEWER_WAKE_ERR_CNT_MASK      (0xFFFF)       		/* [15:0] EEE Wake error counter */
+#define RTL8201FR_EEEWER_WAKE_ERR_CNT(x)        ((x) & 0xFFFF)
+#define RTL8201FR_EEEWER_WAKE_ERR_CNT_GET(x)    ((x) & 0xFFFF)
+
+/* Device 7, Offset 0x3c: EEE Advertisement Register */
+#define RTL8201FR_EEEAR_100BT_EEE_ADV_MASK      (0x1 << 1)     		/* [1] Advertise 100Base-TX EEE capability */
+#define RTL8201FR_EEEAR_100BT_EEE_ADV(x)        (((x) & 0x1) << 1)
+#define RTL8201FR_EEEAR_100BT_EEE_ADV_GET(x)    (((x) >> 1) & 0x1)
+
+/* Device 7, Offset 0x3d: EEE Link Partner Ability Register */
+#define RTL8201FR_EEELPAR_LP_100BT_EEE_GET(x)   (((x) >> 1) & 0x1)  /* [1] Link partner advertises 100Base-TX EEE */
+
+
+/* RTL8211F Page 0xA43 Register 0x19: PHY Specific Control Register 2*/
+#define RTL8211F_PHY_MODE_PAGE					(0xA43)
+#define RTL8211F_PHYCR2_ADDR					(0x19)
+#define RTL8211F_PHCR2_PHY_MODE					(0x0863)
+#define RTL8211F_PHCR2_MAC_MODE					(0x0843)
+
+
+int PHY_SoftWareReset(uint8_t phy_id);
+int PHY_RestartAutoNego(uint8_t phy_id);
+int PHY_SetMmdReg(uint8_t phy_id, uint8_t mmd_dev, uint16_t mmd_addr, uint16_t data);
+int PHY_GetMmdReg(uint8_t phy_id, uint8_t mmd_dev, uint16_t mmd_addr, uint16_t *p_data);
+int PHY_EnableEEE(uint8_t phy_id, u32 status);
+int PHY_SetEEEMode(uint8_t phy_id, uint8_t eth_mode);
+int PHY_SetRefclkDir(uint8_t phy_id, u32 mac_dir);
diff --git a/ameba/amebaG2/source/fwlib/include/ameba_pinmap.h b/ameba/amebag2/source/fwlib/include/ameba_pinmap.h
similarity index 98%
rename from ameba/amebaG2/source/fwlib/include/ameba_pinmap.h
rename to ameba/amebag2/source/fwlib/include/ameba_pinmap.h
index aaeeba02..a0d8b4ca 100644
--- a/ameba/amebaG2/source/fwlib/include/ameba_pinmap.h
+++ b/ameba/amebag2/source/fwlib/include/ameba_pinmap.h
@@ -63,4 +63,4 @@ void pinmap_init(void);
 
 /* Other definations --------------------------------------------------------*/
 #define GPIO_PuPd_KEEP	0xFF /* keep pupd unchanged */
-#endif //_AMEBA_PINMAP_H_
\ No newline at end of file
+#endif //_AMEBA_PINMAP_H_
diff --git a/ameba/amebaG2/source/fwlib/include/ameba_pinmux.h b/ameba/amebag2/source/fwlib/include/ameba_pinmux.h
similarity index 100%
rename from ameba/amebaG2/source/fwlib/include/ameba_pinmux.h
rename to ameba/amebag2/source/fwlib/include/ameba_pinmux.h
diff --git a/ameba/amebaG2/source/fwlib/include/ameba_pke.h b/ameba/amebag2/source/fwlib/include/ameba_pke.h
similarity index 99%
rename from ameba/amebaG2/source/fwlib/include/ameba_pke.h
rename to ameba/amebag2/source/fwlib/include/ameba_pke.h
index c22c8955..8c62120b 100644
--- a/ameba/amebaG2/source/fwlib/include/ameba_pke.h
+++ b/ameba/amebag2/source/fwlib/include/ameba_pke.h
@@ -450,4 +450,4 @@ _LONG_CALL_ int pke_eddsa_ed25519_read_signature(uint8_t *message, size_t msg_le
 
 /** @} */
 
-#endif
\ No newline at end of file
+#endif
diff --git a/ameba/amebag2/source/fwlib/include/ameba_plic.h b/ameba/amebag2/source/fwlib/include/ameba_plic.h
new file mode 100644
index 00000000..e6e8c73c
--- /dev/null
+++ b/ameba/amebag2/source/fwlib/include/ameba_plic.h
@@ -0,0 +1,230 @@
+/*
+ * Copyright (c) 2024 Realtek Semiconductor Corp.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __AMEBA_PLIC_H__
+#define __AMEBA_PLIC_H__
+
+#define PLIC_INT_PRI_BITS               3               // Interrupt priority bits, max interrupt priority = 2^PLIC_INT_PRI_BITS-1. 2 ~ 4
+#define PLIC_INT_PRIS                   ((1 << PLIC_INT_PRI_BITS) - 1)
+
+#define PLIC_INT_PRI_REG_OFFSET         0x0800          // the address offset of Interrupt Priority Register
+#define PLIC_INT_PEND_REG_OFFSET        0x0C00          // the address offset of Interrupt Pending Register
+#define PLIC_INT_CLAIMED_REG_OFFSET     0x0C20          // the address offset of Interrupt Claimed Register
+#define PLIC_INT_PEND_CLEAR_REG_OFFSET  0x0C40          // the address offset of Interrupt Pending Clear Register
+#define PLIC_INT_PEND_SET_REG_OFFSET    0x0C60          // the address offset of Interrupt Pending Set Register
+#define PLIC_INT_SIP_REG_OFFSET         MSIP_ADDR       // the address offset of Software Interrupt Pending Register
+#define PLIC_INT_CLAIM_REG_OFFSET       0x0014          // the address offset of Interrupt Claim Register (Pending IRQ ID reading)
+#define PLIC_INT_COMP_REG_OFFSET        0x0018          // the address offset of Interrupt Complete Register (IRQ Ack)
+#define PLIC_INT_THRD_REG_OFFSET        0x001C          // the address offset of Interrupt Threshold Register
+#define PLIC_INT_EN_REG_OFFSET          0x0020          // the address offset of Interrupt Enable Register
+
+#define MAX_HART_NUM                    8               // Max HART number supported
+#define PLIC_HART_SELF                  0xFFFFFFFFUL    // Get PLIC self id from mhartid
+
+
+#define PLIC_HART_REG(hart, reg) REG32((PLIC_BASE) + ((hart) << 8) + (reg))
+
+#define PLIC_HART_IRQ_READ(reg, hart, irq) \
+    PLIC_HART_REG((hart), (reg) + (((irq) >> 5) << 2))
+
+#define PLIC_HART_IRQ_SET(reg, hart, irq) \
+do { \
+    PLIC_HART_REG((hart), (reg) + (((irq) >> 5) << 2)) |= (1 << ((irq) & 0x1f)); \
+} while(0)
+
+#define PLIC_HART_IRQ_CLEAR(reg, hart, irq) \
+do { \
+    PLIC_HART_REG((hart), (reg) + (((irq) >> 5) << 2)) &= ~(1 << ((irq) & 0x1f)); \
+} while(0)
+
+#define PLIC_IRQ_REG(reg, irq) REG32((PLIC_BASE) + (reg) + ((irq) << 2))
+#define PLIC_IRQ_PEND_REG(irq) \
+  REG32((PLIC_BASE) + (PLIC_INT_PEND_REG_OFFSET) + ((irq >> 5) << 2))
+#define PLIC_IRQ_PEND_CLEAR_REG(irq) \
+  REG32((PLIC_BASE) + (PLIC_INT_PEND_CLEAR_REG_OFFSET) + ((irq >> 5) << 2))
+#define PLIC_IRQ_PEND_SET_REG(irq) \
+  REG32((PLIC_BASE) + (PLIC_INT_PEND_SET_REG_OFFSET) + ((irq >> 5) << 2))
+#define PLIC_IRQ_CLAIMED_REG(irq) \
+  REG32((PLIC_BASE) + (PLIC_INT_CLAIMED_REG_OFFSET) + ((irq >> 5) << 2))
+
+#define PLIC_IRQ_SET(reg, irq) \
+do { \
+    REG32((reg) + ((irq) << 2)) |= (1 << ((irq) & 0x1f)); \
+} while(0)
+
+#define PLIC_IRQ_CLEAR(reg, irq) \
+do { \
+    REG32((reg) + ((irq) << 2)) &= ~(1 << ((irq) & 0x1f)); \
+} while(0)
+
+/**
+  \brief   Enable an Interrupt.
+  \details To enable an interrupt whith a given IRQ ID.
+  \param   irq_id the interrupt ID.
+ */
+extern void plic_enable_irq(uint32_t irq_id);
+
+/**
+  \brief   Disable an Interrupt.
+  \details To disable an interrupt whith a given IRQ ID.
+  \param   irq_id the interrupt ID.
+ */
+extern void plic_disable_irq(uint32_t irq_id);
+
+/**
+  \brief   Get the enabling of an Interrupt.
+  \details To enable an interrupt whith a given IRQ ID.
+  \param   irq_id the interrupt ID.
+  \return  The status of the interrupt enabling.
+ */
+extern uint32_t plic_get_irq_enable(uint32_t irq_id);
+
+/**
+  \brief   Set the enable status of 32 Interrupts in the same register.
+  \details To set 32 interrupt enable bits with a given register id
+  \param   irq_id the interrupt ID.
+  \return  The status of the interrupt enabling.
+ */
+extern void plic_set_enable(uint32_t reg_id, uint32_t interrupt);
+
+/**
+  \brief   Get the enable status of 32 Interrupts in the same register.
+  \details To get 32 interrupt enable bits with a given register id
+  \param   irq_id the interrupt ID.
+  \return  The status of the interrupt enabling.
+ */
+extern uint32_t plic_get_enable(uint32_t reg_id);
+
+
+
+/**
+  \brief   Write the interrupt enable bit maps.
+  \details To write the interrupt enble bit maps
+  \param   enable the buffer of the interrupt enable bits map.
+ */
+extern void plic_write_enables(uint32_t *enable);
+
+/**
+  \brief   Set Interrupt Priority.
+  \details Set the Priority of a given Interrupt ID. IRQ ID 0 is reserved.
+  \param   irq_id the interrupt ID.
+  \param   priority the priority of the interrupt ID.
+ */
+extern void plic_set_irq_priority(uint32_t irq_id, uint32_t priority);
+
+/**
+  \brief   Get Interrupt Priority of given IRQ ID.
+  \details Get the Priority of a given Interrupt ID. IRQ ID 0 is reserved.
+  \param   irq_id the interrupt ID.
+  \return  The priority of given IRQ ID.
+ */
+extern uint32_t plic_get_irq_priority(uint32_t irq_id);
+
+/**
+  \brief   Get the pending status of 32 Interrupts in the same register.
+  \details To get 32 interrupt pending bits with a given register id
+  \param   reg_id the register ID.
+  \return  The status of the interrupt pending.
+ */
+extern uint32_t plic_get_pending(uint32_t reg_id);
+
+/**
+  \brief   Get the pending status of an interrupt.
+  \details Get the pending status of the given IRQ ID.
+  \param   irq_id the IRQ ID.
+  \return  The interrupt pending status of the given IRQ ID.
+           0: interrupt is not pending
+           1: interrupt is pending.
+ */
+extern uint32_t plic_get_irq_pending(uint32_t irq_id);
+
+/**
+ \brief   Clear the pending status of an interrupt.
+ \details Clear he pending status of the given IRQ ID.
+ \param   irq_id the IRQ ID.
+ */
+extern void plic_clear_irq_pending(uint32_t irq_id);
+
+/**
+ \brief   Clear the pending status of an interrupt.
+ \details Clear he pending status of the given IRQ ID.
+ \param   irq_id the IRQ ID.
+ */
+extern void plic_set_irq_pending(uint32_t irq_id);
+
+/**
+ \brief   Check interrupt claim status
+ \details Check whether IRQ ID is claimed but not completed yet
+ \para    irq_id the IRQ ID.
+ \return  0: IRQ ID is not claimed
+          1: IRQ ID is claimed
+ */
+extern uint32_t plic_get_irq_claimed(uint32_t irq_id);
+
+/**
+  \brief   To claim the highest priority pending interrupt.
+  \details Claims the highest priority pending interrupt and get its IRQ ID.
+  \return  The IRQ ID of the highest priority pending interrupt.
+ */
+extern uint32_t plic_claim_irq(void);
+
+/**
+  \brief   To complete an interrupt.
+  \details Completes an interrupt handleing and clean its pending status.
+  \param   irq_id The given IRQ ID of the interrupt to be completed.
+  \return  void.
+ */
+extern void plic_complete_irq(uint32_t irq_id);
+
+/**
+  \brief   Set interrupt priority threshold.
+  \details Set the interrupt priority threshold. Only interrupts with its
+           priority higher than this threshold can active.
+  \param   priority The interrupt priority threshold.
+  \return  void.
+ */
+extern void plic_set_threshold(uint32_t priority);
+
+/**
+  \brief   Get interrupt priority threshold.
+  \details Get the interrupt priority threshold. Only interrupts with its
+           priority higher than this threshold can active.
+  \param   priority The interrupt priority threshold.
+  \return  void.
+ */
+extern uint32_t plic_get_threshold(void);
+
+/**
+  \brief   Set software interrupt pending.
+  \details To assert the software interrupt pending signal of the Hardware Architecture Target.
+  \param   hart The hart target to set software interrupt.
+  \return  void.
+ */
+extern void plic_set_sip(uint32_t hart);
+
+/**
+  \brief   Clear software interrupt pending.
+  \details To clear the software interrupt pending signal of the Hardware Architecture Target.
+  \param   hart The hart target to clear software interrupt.
+  \return  void.
+ */
+extern void plic_clear_sip(uint32_t hart);
+
+/**
+  \brief   PLIC HAL initialization
+  \details To initial the PLIC HAL code.
+  \return  void.
+ */
+extern void plic_init(void);
+
+/**
+  \brief   PLIC get active IRQ Id.
+  \details To get currently active IRQ Id.
+  \return  The active IRQ Id.
+ */
+extern uint32_t plic_get_active_irq_id(void);
+
+#endif /* end of #define __PLIC_H */
diff --git a/ameba/amebaG2/source/fwlib/include/ameba_pmc.h b/ameba/amebag2/source/fwlib/include/ameba_pmc.h
similarity index 95%
rename from ameba/amebaG2/source/fwlib/include/ameba_pmc.h
rename to ameba/amebag2/source/fwlib/include/ameba_pmc.h
index c2e190a5..af70581e 100644
--- a/ameba/amebaG2/source/fwlib/include/ameba_pmc.h
+++ b/ameba/amebag2/source/fwlib/include/ameba_pmc.h
@@ -7,6 +7,10 @@
 #ifndef _AMEBA_PMC_H_
 #define _AMEBA_PMC_H_
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /** @addtogroup AmebaD_Platform
   * @{
   */
@@ -191,12 +195,6 @@ enum PMC_AP_WAKE_STATUS {
   * @}
   */
 
-struct PSCFG_TypeDef {
-	u8 keep_osc4m_on_in_sleep;  /* keep OSC4M on or off for sleep*/
-	u8 xtal_mode_in_sleep;	    /* see enum xtal_mode_sleep for detail */
-	u8 regu_state_in_sleep;	    /* set work state of regu(SWR+LDO) in sleep, default sleep to 0.7V(SWR:PFM mode, LDO:power cut)*/
-};
-
 int ap_suspend(void);
 void ap_resume(void);
 u32 ap_status_on(void);
@@ -218,4 +216,9 @@ void SOCPS_PeriPermissionEntry(uint32_t ip_mask, u32 enable);
 void SOCPS_BitPermissionEntry(uint32_t ip_mask, u32 enable);
 
 extern SLEEP_ParamDef sleep_param;
-#endif //_AMEBA_PMC_H_
\ No newline at end of file
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //_AMEBA_PMC_H_
diff --git a/ameba/amebaG2/source/fwlib/include/ameba_pmctimer.h b/ameba/amebag2/source/fwlib/include/ameba_pmctimer.h
similarity index 99%
rename from ameba/amebaG2/source/fwlib/include/ameba_pmctimer.h
rename to ameba/amebag2/source/fwlib/include/ameba_pmctimer.h
index 4c570145..62bcbb77 100644
--- a/ameba/amebaG2/source/fwlib/include/ameba_pmctimer.h
+++ b/ameba/amebag2/source/fwlib/include/ameba_pmctimer.h
@@ -192,4 +192,4 @@ void PMCTimer_Reset(void);
 
 /* MANUAL_GEN_END */
 
-#endif
\ No newline at end of file
+#endif
diff --git a/ameba/amebaG2/source/fwlib/include/ameba_pmu.h b/ameba/amebag2/source/fwlib/include/ameba_pmu.h
similarity index 92%
rename from ameba/amebaG2/source/fwlib/include/ameba_pmu.h
rename to ameba/amebag2/source/fwlib/include/ameba_pmu.h
index ffa3eb48..5ddafb62 100644
--- a/ameba/amebaG2/source/fwlib/include/ameba_pmu.h
+++ b/ameba/amebag2/source/fwlib/include/ameba_pmu.h
@@ -7,13 +7,18 @@
 #ifndef _AMEBA_PMU_H_
 #define _AMEBA_PMU_H_
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 typedef enum {
 	PMU_OS				= 0,
 	PMU_WLAN_DEVICE,
 	PMU_CPU0_RUN,
 	PMU_CPU1_RUN,
 	PMU_WLAN_FW_DEVICE,
-	PMU_BT_DEVICE,
+	PMU_BT_CONTROLLER,
+	PMU_BT_HOST,
 	PMU_WHC_WIFI,
 	PMU_DHCP_PROCESS,
 	PMU_LWIP_STACK,
@@ -41,7 +46,7 @@ typedef struct {
 
 uint32_t pmu_yield_os_check(void);
 uint32_t pmu_exec_sleep_hook_funs(void);
-void pmu_exec_wakeup_hook_funs(uint32_t nDeviceIdMax);
+void pmu_exec_wakeup_hook_funs(uint32_t nDeviceIdMax, uint32_t common_param);
 uint32_t pmu_set_sleep_type(uint32_t type);
 uint32_t pmu_get_sleep_type(void);
 uint32_t pmu_get_sleep_time(void);
@@ -83,4 +88,10 @@ extern void Systick_Cmd(uint32_t enable);
 extern uint32_t SYSTIMER_GetPassTick(uint32_t start);
 
 extern uint32_t system_can_yield;
+extern uint32_t cur_device_id;
+
+#ifdef __cplusplus
+}
+#endif
+
 #endif
diff --git a/ameba/amebaG2/source/fwlib/include/ameba_ppe.h b/ameba/amebag2/source/fwlib/include/ameba_ppe.h
similarity index 100%
rename from ameba/amebaG2/source/fwlib/include/ameba_ppe.h
rename to ameba/amebag2/source/fwlib/include/ameba_ppe.h
diff --git a/ameba/amebaG2/source/fwlib/include/ameba_psphy.h b/ameba/amebag2/source/fwlib/include/ameba_psphy.h
similarity index 99%
rename from ameba/amebaG2/source/fwlib/include/ameba_psphy.h
rename to ameba/amebag2/source/fwlib/include/ameba_psphy.h
index 7b8c5c9b..200ff890 100644
--- a/ameba/amebaG2/source/fwlib/include/ameba_psphy.h
+++ b/ameba/amebag2/source/fwlib/include/ameba_psphy.h
@@ -262,4 +262,4 @@ typedef struct {
 
 /** @} */
 
-/** @} */
\ No newline at end of file
+/** @} */
diff --git a/ameba/amebaG2/source/fwlib/include/ameba_psram.h b/ameba/amebag2/source/fwlib/include/ameba_psram.h
similarity index 100%
rename from ameba/amebaG2/source/fwlib/include/ameba_psram.h
rename to ameba/amebag2/source/fwlib/include/ameba_psram.h
diff --git a/ameba/amebaG2/source/fwlib/include/ameba_pwmtimer.h b/ameba/amebag2/source/fwlib/include/ameba_pwmtimer.h
similarity index 99%
rename from ameba/amebaG2/source/fwlib/include/ameba_pwmtimer.h
rename to ameba/amebag2/source/fwlib/include/ameba_pwmtimer.h
index 35d4ae0c..f625e611 100644
--- a/ameba/amebaG2/source/fwlib/include/ameba_pwmtimer.h
+++ b/ameba/amebag2/source/fwlib/include/ameba_pwmtimer.h
@@ -624,4 +624,4 @@ extern u32 TIM_IT_CCx[PWM_CHAN_MAX];
 
 /* MANUAL_GEN_END */
 
-#endif
\ No newline at end of file
+#endif
diff --git a/ameba/amebaG2/source/fwlib/include/ameba_rcc.h b/ameba/amebag2/source/fwlib/include/ameba_rcc.h
similarity index 100%
rename from ameba/amebaG2/source/fwlib/include/ameba_rcc.h
rename to ameba/amebag2/source/fwlib/include/ameba_rcc.h
diff --git a/ameba/amebaG2/source/fwlib/include/ameba_reset.h b/ameba/amebag2/source/fwlib/include/ameba_reset.h
similarity index 100%
rename from ameba/amebaG2/source/fwlib/include/ameba_reset.h
rename to ameba/amebag2/source/fwlib/include/ameba_reset.h
diff --git a/ameba/amebaG2/source/fwlib/include/ameba_rsip.h b/ameba/amebag2/source/fwlib/include/ameba_rsip.h
similarity index 99%
rename from ameba/amebaG2/source/fwlib/include/ameba_rsip.h
rename to ameba/amebag2/source/fwlib/include/ameba_rsip.h
index 92bd6705..23fe551f 100644
--- a/ameba/amebaG2/source/fwlib/include/ameba_rsip.h
+++ b/ameba/amebag2/source/fwlib/include/ameba_rsip.h
@@ -544,4 +544,4 @@ _LONG_CALL_ void RSIP_MMU_Cache_Clean(void);
 
 /** @} */
 
-/** @} */
\ No newline at end of file
+/** @} */
diff --git a/ameba/amebaG2/source/fwlib/include/ameba_rtc.h b/ameba/amebag2/source/fwlib/include/ameba_rtc.h
similarity index 100%
rename from ameba/amebaG2/source/fwlib/include/ameba_rtc.h
rename to ameba/amebag2/source/fwlib/include/ameba_rtc.h
diff --git a/ameba/amebaG2/source/fwlib/include/ameba_rxi300.h b/ameba/amebag2/source/fwlib/include/ameba_rxi300.h
similarity index 99%
rename from ameba/amebaG2/source/fwlib/include/ameba_rxi300.h
rename to ameba/amebag2/source/fwlib/include/ameba_rxi300.h
index 795eb602..a592cc4c 100644
--- a/ameba/amebaG2/source/fwlib/include/ameba_rxi300.h
+++ b/ameba/amebag2/source/fwlib/include/ameba_rxi300.h
@@ -873,4 +873,4 @@ typedef struct {
 
 /** @} */
 
-#endif
\ No newline at end of file
+#endif
diff --git a/ameba/amebaG2/source/fwlib/include/ameba_sd.h b/ameba/amebag2/source/fwlib/include/ameba_sd.h
similarity index 99%
rename from ameba/amebaG2/source/fwlib/include/ameba_sd.h
rename to ameba/amebag2/source/fwlib/include/ameba_sd.h
index 4c645b48..15303b9d 100644
--- a/ameba/amebaG2/source/fwlib/include/ameba_sd.h
+++ b/ameba/amebag2/source/fwlib/include/ameba_sd.h
@@ -450,6 +450,7 @@ typedef struct {
   */
 SD_RESULT SD_Init(void);
 SD_RESULT SD_DeInit(void);
+u32 SD_IRQHandler(void *pData);
 /**
   * @}
   */
@@ -495,7 +496,8 @@ SD_RESULT SD_GetCardCSD(SD_HdlTypeDef *hsd, SD_CardCSDTypeDef *pCSD);
 SD_RESULT SD_GetSDStatus(SD_HdlTypeDef *hsd, SD_StatusTypeDef *pStatus);
 
 _LONG_CALL_ void SD_SetSema(int (*sema_take_fn)(u32), int (*sema_give_isr_fn)(u32));
-u32 SD_WaitTransDone(SD_HdlTypeDef *hsd, u32 timeout_us);
+_LONG_CALL_ void SD_PreDMATrans(SD_HdlTypeDef *hsd);
+_LONG_CALL_ u32 SD_WaitTransDone(SD_HdlTypeDef *hsd, u32 timeout_us);
 _LONG_CALL_ SD_RESULT SD_Status(void);
 _LONG_CALL_ int SD_CheckStatusTO(SD_HdlTypeDef *hsd, u32 timeout_us);
 _LONG_CALL_ SD_RESULT SD_ReadBlocks(u32 sector, u8 *data, u32 count);
diff --git a/ameba/amebaG2/source/fwlib/include/ameba_sd_host.h b/ameba/amebag2/source/fwlib/include/ameba_sd_host.h
similarity index 99%
rename from ameba/amebaG2/source/fwlib/include/ameba_sd_host.h
rename to ameba/amebag2/source/fwlib/include/ameba_sd_host.h
index 2c75b8c4..94d2a987 100644
--- a/ameba/amebaG2/source/fwlib/include/ameba_sd_host.h
+++ b/ameba/amebag2/source/fwlib/include/ameba_sd_host.h
@@ -1602,12 +1602,11 @@ typedef struct {
 #define SDMMC_R6_ILLEGAL_CMD 0x00004000U
 #define SDMMC_R6_COM_CRC_FAILED 0x00008000U
 
-#define SDMMC_VOLTAGE_WINDOW_SD 0x80100000U
 #define SDMMC_HIGH_CAPACITY 0x40000000U
-#define SDMMC_STD_CAPACITY 0x00000000U
-#define SDMMC_CHECK_PATTERN 0x000001AAU
-#define SDMMC_SWITCH_1_8V_CAPACITY 0x01000000U
+#define SDMMC_SWITCH_1_8V_CAPACITY 0x10000000U
+#define SDMMC_VOLTAGE_WINDOW_SD 0x00100000U // 3.2-3.3V
 
+#define SDMMC_CHECK_PATTERN 0x000001AAU
 /**
  * @brief  Masks for SCR
  */
@@ -1967,7 +1966,7 @@ u32 SDMMC_CmdSetWrBlkEraseCnt(SDIOHOST_TypeDef *SDIOx, u32 BlockCnt);
 u32 SDMMC_CmdSendSCR(SDIOHOST_TypeDef *SDIOx);
 u32 SDMMC_CmdSendCID(SDIOHOST_TypeDef *SDIOx);
 u32 SDMMC_CmdSendCSD(SDIOHOST_TypeDef *SDIOx, u32 Argument);
-u32 SDMMC_CmdSetRelAdd(SDIOHOST_TypeDef *SDIOx, u16 *pRCA);
+u32 SDMMC_CmdSetRelAdd(SDIOHOST_TypeDef *SDIOx);
 u32 SDMMC_CmdSendStatus(SDIOHOST_TypeDef *SDIOx, u32 Argument);
 u32 SDMMC_CmdStatusRegister(SDIOHOST_TypeDef *SDIOx);
 u32 SDMMC_CmdSwitch(SDIOHOST_TypeDef *SDIOx, u32 Argument);
@@ -1978,15 +1977,10 @@ u32 SDIO_CmdRWDirect(SDIOHOST_TypeDef *SDIOx, u32 Argument);
 u32 SDIO_CmdRWExtended(SDIOHOST_TypeDef *SDIOx, u32 Argument);
 
 /* SDMMC Responses management functions */
-u32 SDMMC_GetCmdError(SDIOHOST_TypeDef *SDIOx);
-u32 SDMMC_GetCmdResp1(SDIOHOST_TypeDef *SDIOx);
-u32 SDMMC_GetCmdResp1B(SDIOHOST_TypeDef *SDIOx, u32 Timeout);
-u32 SDMMC_GetCmdResp2(SDIOHOST_TypeDef *SDIOx);
-u32 SDMMC_GetCmdResp3(SDIOHOST_TypeDef *SDIOx);
-u32 SDMMC_GetCmdResp4(SDIOHOST_TypeDef *SDIOx);
-u32 SDMMC_GetCmdResp5(SDIOHOST_TypeDef *SDIOx);
-u32 SDMMC_GetCmdResp6(SDIOHOST_TypeDef *SDIOx, u16 *pRCA);
-u32 SDMMC_GetCmdResp7(SDIOHOST_TypeDef *SDIOx);
+u32 SDIO_WaitResp(SDIOHOST_TypeDef *SDIOx, u8 RespType, u32 TimeOutUs);
+u32 SDMMC_CheckErrResp1(u32 resp);
+u32 SDMMC_CheckErrResp5(u32 resp);
+u32 SDMMC_CheckErrResp6(u32 resp);
 
 /**
  * @}
diff --git a/ameba/amebaG2/source/fwlib/include/ameba_sdio_bt.h b/ameba/amebag2/source/fwlib/include/ameba_sdio_bt.h
similarity index 99%
rename from ameba/amebaG2/source/fwlib/include/ameba_sdio_bt.h
rename to ameba/amebag2/source/fwlib/include/ameba_sdio_bt.h
index 34b8f31b..574b9d24 100644
--- a/ameba/amebaG2/source/fwlib/include/ameba_sdio_bt.h
+++ b/ameba/amebag2/source/fwlib/include/ameba_sdio_bt.h
@@ -236,4 +236,4 @@
 
 /** @} */
 
-#endif
\ No newline at end of file
+#endif
diff --git a/ameba/amebaG2/source/fwlib/include/ameba_sdio_device.h b/ameba/amebag2/source/fwlib/include/ameba_sdio_device.h
similarity index 100%
rename from ameba/amebaG2/source/fwlib/include/ameba_sdio_device.h
rename to ameba/amebag2/source/fwlib/include/ameba_sdio_device.h
diff --git a/ameba/amebaG2/source/fwlib/include/ameba_sdio_wifi.h b/ameba/amebag2/source/fwlib/include/ameba_sdio_wifi.h
similarity index 100%
rename from ameba/amebaG2/source/fwlib/include/ameba_sdio_wifi.h
rename to ameba/amebag2/source/fwlib/include/ameba_sdio_wifi.h
diff --git a/ameba/amebaG2/source/fwlib/include/ameba_secure_boot.h b/ameba/amebag2/source/fwlib/include/ameba_secure_boot.h
similarity index 100%
rename from ameba/amebaG2/source/fwlib/include/ameba_secure_boot.h
rename to ameba/amebag2/source/fwlib/include/ameba_secure_boot.h
diff --git a/ameba/amebaG2/source/fwlib/include/ameba_sema_rom.h b/ameba/amebag2/source/fwlib/include/ameba_sema_rom.h
similarity index 100%
rename from ameba/amebaG2/source/fwlib/include/ameba_sema_rom.h
rename to ameba/amebag2/source/fwlib/include/ameba_sema_rom.h
diff --git a/ameba/amebaG2/source/fwlib/include/ameba_sha.h b/ameba/amebag2/source/fwlib/include/ameba_sha.h
similarity index 99%
rename from ameba/amebaG2/source/fwlib/include/ameba_sha.h
rename to ameba/amebag2/source/fwlib/include/ameba_sha.h
index d6e5de3c..044552b8 100644
--- a/ameba/amebaG2/source/fwlib/include/ameba_sha.h
+++ b/ameba/amebag2/source/fwlib/include/ameba_sha.h
@@ -697,4 +697,4 @@ _LONG_CALL_ int crypto_hmac_sha2_final(SHA_context *ctx, u8 *output);
 /* MANUAL_GEN_END */
 
 
-#endif
\ No newline at end of file
+#endif
diff --git a/ameba/amebaG2/source/fwlib/include/ameba_soc.h b/ameba/amebag2/source/fwlib/include/ameba_soc.h
similarity index 93%
rename from ameba/amebaG2/source/fwlib/include/ameba_soc.h
rename to ameba/amebag2/source/fwlib/include/ameba_soc.h
index 419e6684..99e1f6b6 100644
--- a/ameba/amebaG2/source/fwlib/include/ameba_soc.h
+++ b/ameba/amebag2/source/fwlib/include/ameba_soc.h
@@ -19,7 +19,7 @@
 #ifndef CONFIG_BUILD_ROM
 /* ram headers */
 #include "ameba_ota.h"
-// #include "os_wrapper.h"
+#include "os_wrapper.h"
 #include "ameba_pmu.h"
 #endif
 
diff --git a/ameba/amebaG2/source/fwlib/include/ameba_soc_ps.h b/ameba/amebag2/source/fwlib/include/ameba_soc_ps.h
similarity index 90%
rename from ameba/amebaG2/source/fwlib/include/ameba_soc_ps.h
rename to ameba/amebag2/source/fwlib/include/ameba_soc_ps.h
index d8e0ea88..fc6324d4 100644
--- a/ameba/amebaG2/source/fwlib/include/ameba_soc_ps.h
+++ b/ameba/amebag2/source/fwlib/include/ameba_soc_ps.h
@@ -7,6 +7,11 @@
 #ifndef _AMEBA_SOCPS_H_
 #define _AMEBA_SOCPS_H_
 
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 enum wakeup_mask {
 	WAKEUP_NULL	= 0,
 	WAKEUP_NP	= 1,
@@ -16,7 +21,13 @@ enum wakeup_mask {
 struct WakeEvent_TypeDef {
 	u32 Module;
 	enum wakeup_mask Wakeup;
-} ;
+};
+
+struct PSCFG_TypeDef {
+	u8 keep_osc4m_on;			/* keep OSC4M on or off for sleep and dslp*/
+	u8 xtal_mode_in_sleep;		/* set xtal mode during sleep mode*/
+	u8 sleep_to_08V;			/* default sleep to 0.7V, set this option to TRUE will sleep to 0.8V */
+};
 
 struct MPU_BackUp_TypeDef {
 	u32 CTRL;
@@ -94,4 +105,8 @@ void SOCPS_USBSuspendWakeControl(u8 status);
 void SOCPS_PowerStateSetInSleep(u8 pwr_sts);
 void SOCPS_PowerStateSetInNormal(u8 pwr_sts);
 void SOCPS_SetMemMode(u32 module, u32 mem_mode);
+
+#ifdef __cplusplus
+}
+#endif
 #endif  //_AMEBA_SOCPS_H_
\ No newline at end of file
diff --git a/ameba/amebaG2/source/fwlib/include/ameba_spi.h b/ameba/amebag2/source/fwlib/include/ameba_spi.h
similarity index 99%
rename from ameba/amebaG2/source/fwlib/include/ameba_spi.h
rename to ameba/amebag2/source/fwlib/include/ameba_spi.h
index 86f41f49..40b9b0b1 100644
--- a/ameba/amebaG2/source/fwlib/include/ameba_spi.h
+++ b/ameba/amebag2/source/fwlib/include/ameba_spi.h
@@ -689,4 +689,4 @@ extern const SPI_DevTable SPI_DEV_TABLE[2];
 
 /* MANUAL_GEN_END */
 
-#endif
\ No newline at end of file
+#endif
diff --git a/ameba/amebaG2/source/fwlib/include/ameba_spic.h b/ameba/amebag2/source/fwlib/include/ameba_spic.h
similarity index 100%
rename from ameba/amebaG2/source/fwlib/include/ameba_spic.h
rename to ameba/amebag2/source/fwlib/include/ameba_spic.h
diff --git a/ameba/amebaG2/source/fwlib/include/ameba_spinand.h b/ameba/amebag2/source/fwlib/include/ameba_spinand.h
similarity index 100%
rename from ameba/amebaG2/source/fwlib/include/ameba_spinand.h
rename to ameba/amebag2/source/fwlib/include/ameba_spinand.h
diff --git a/ameba/amebaG2/source/fwlib/include/ameba_sport.h b/ameba/amebag2/source/fwlib/include/ameba_sport.h
similarity index 99%
rename from ameba/amebaG2/source/fwlib/include/ameba_sport.h
rename to ameba/amebag2/source/fwlib/include/ameba_sport.h
index 41226758..fa874f21 100644
--- a/ameba/amebaG2/source/fwlib/include/ameba_sport.h
+++ b/ameba/amebag2/source/fwlib/include/ameba_sport.h
@@ -1321,4 +1321,4 @@ extern const AUDIO_DevTable AUDIO_DEV_TABLE[1];
 
 /* MANUAL_GEN_END */
 
-#endif
\ No newline at end of file
+#endif
diff --git a/ameba/amebaG2/source/fwlib/include/ameba_syscfg.h b/ameba/amebag2/source/fwlib/include/ameba_syscfg.h
similarity index 98%
rename from ameba/amebaG2/source/fwlib/include/ameba_syscfg.h
rename to ameba/amebag2/source/fwlib/include/ameba_syscfg.h
index 98ff811c..0536209b 100644
--- a/ameba/amebaG2/source/fwlib/include/ameba_syscfg.h
+++ b/ameba/amebag2/source/fwlib/include/ameba_syscfg.h
@@ -181,8 +181,8 @@ _LONG_CALL_ u32 SYSCFG_OTP_RomPatchEn(void);
 #define SYSCFG_OTP_BOOT_FROM_EXT					2
 
 /*******************  Macro definition for Lifecycle ********************/
-#define PSA_LIFECYCLE_RMA				        	1
-#define PSA_LIFECYCLE_DECOMMISSIONED			2
+#define RTK_PSA_LIFECYCLE_RMA				        	1
+#define RTK_PSA_LIFECYCLE_DECOMMISSIONED			2
 
 /*******************  Macro definition for RSIP MODE ********************/
 #define RSIP_XTS_MODE                     0
diff --git a/ameba/amebaG2/source/fwlib/include/ameba_thermal.h b/ameba/amebag2/source/fwlib/include/ameba_thermal.h
similarity index 99%
rename from ameba/amebaG2/source/fwlib/include/ameba_thermal.h
rename to ameba/amebag2/source/fwlib/include/ameba_thermal.h
index 31f68e73..51371b7d 100644
--- a/ameba/amebaG2/source/fwlib/include/ameba_thermal.h
+++ b/ameba/amebag2/source/fwlib/include/ameba_thermal.h
@@ -357,4 +357,4 @@ _LONG_CALL_ float TM_GetFdegree(u32 Data);
 /* MANUAL_GEN_END */
 
 
-#endif
\ No newline at end of file
+#endif
diff --git a/ameba/amebaG2/source/fwlib/include/ameba_trng.h b/ameba/amebag2/source/fwlib/include/ameba_trng.h
similarity index 99%
rename from ameba/amebaG2/source/fwlib/include/ameba_trng.h
rename to ameba/amebag2/source/fwlib/include/ameba_trng.h
index 64a36ffc..65efb26b 100644
--- a/ameba/amebaG2/source/fwlib/include/ameba_trng.h
+++ b/ameba/amebag2/source/fwlib/include/ameba_trng.h
@@ -317,4 +317,4 @@ _LONG_CALL_ u32 __wrap_rand(void);
 
 /** @} */
 
-/** @} */
\ No newline at end of file
+/** @} */
diff --git a/ameba/amebaG2/source/fwlib/include/ameba_trustzone.h b/ameba/amebag2/source/fwlib/include/ameba_trustzone.h
similarity index 98%
rename from ameba/amebaG2/source/fwlib/include/ameba_trustzone.h
rename to ameba/amebag2/source/fwlib/include/ameba_trustzone.h
index 7730b153..ef7b70b0 100644
--- a/ameba/amebaG2/source/fwlib/include/ameba_trustzone.h
+++ b/ameba/amebag2/source/fwlib/include/ameba_trustzone.h
@@ -57,9 +57,9 @@ typedef enum {
   */
 #define SAU_INIT_CTRL_ALLNS  0
 
-#define SAU_ENTRYS_NUM			8
+#define SAU_ENTRY_NUM			8
 
-#define MPC_ENTRYS_NUM			6
+#define MPC_ENTRY_NUM			6
 #define MPC_CNT					3
 
 /**
diff --git a/ameba/amebaG2/source/fwlib/include/ameba_uart.h b/ameba/amebag2/source/fwlib/include/ameba_uart.h
similarity index 99%
rename from ameba/amebaG2/source/fwlib/include/ameba_uart.h
rename to ameba/amebag2/source/fwlib/include/ameba_uart.h
index 923e04c8..c3edaea3 100644
--- a/ameba/amebaG2/source/fwlib/include/ameba_uart.h
+++ b/ameba/amebag2/source/fwlib/include/ameba_uart.h
@@ -701,6 +701,8 @@ _LONG_CALL_ void UART_RxDebounceCmd(UART_TypeDef *UARTx, u32 NewState);
 _LONG_CALL_ void UART_RxDMADummyDataConfig(UART_TypeDef *UARTx, u8 Byte);
 _LONG_CALL_ u32 UART_GetRxDMADummyFlag(UART_TypeDef *UARTx);
 _LONG_CALL_ void UART_RxClearDMADummyFlag(UART_TypeDef *UARTx);
+_LONG_CALL_ void UART_RxToThreConfig(UART_TypeDef *UARTx, u32 RxTimeout);
+_LONG_CALL_ void UART_REToThreConfig(UART_TypeDef *UARTx, u32 RxTimeout);
 
 
 /* Other Definitions --------------------------------------------------------*/
@@ -738,4 +740,4 @@ UART_GetRxFlag(u32 UartIdx)
 
 /* MANUAL_GEN_END */
 
-#endif
\ No newline at end of file
+#endif
diff --git a/ameba/amebaG2/source/fwlib/include/ameba_ups.h b/ameba/amebag2/source/fwlib/include/ameba_ups.h
similarity index 99%
rename from ameba/amebaG2/source/fwlib/include/ameba_ups.h
rename to ameba/amebag2/source/fwlib/include/ameba_ups.h
index f5ee5e84..a7749bdf 100644
--- a/ameba/amebaG2/source/fwlib/include/ameba_ups.h
+++ b/ameba/amebag2/source/fwlib/include/ameba_ups.h
@@ -216,4 +216,4 @@ _LONG_CALL_ void UPS_SetDbcCnt(u16 Dbc_Cnt, u8 idx);
 /** @} */
 
 /* MANUAL_GEN_END */
-#endif
\ No newline at end of file
+#endif
diff --git a/ameba/amebaG2/source/fwlib/include/ameba_usb.h b/ameba/amebag2/source/fwlib/include/ameba_usb.h
similarity index 100%
rename from ameba/amebaG2/source/fwlib/include/ameba_usb.h
rename to ameba/amebag2/source/fwlib/include/ameba_usb.h
diff --git a/ameba/amebaG2/source/fwlib/include/ameba_uvc.h b/ameba/amebag2/source/fwlib/include/ameba_uvc.h
similarity index 100%
rename from ameba/amebaG2/source/fwlib/include/ameba_uvc.h
rename to ameba/amebag2/source/fwlib/include/ameba_uvc.h
diff --git a/ameba/amebaG2/source/fwlib/include/ameba_vector.h b/ameba/amebag2/source/fwlib/include/ameba_vector.h
similarity index 100%
rename from ameba/amebaG2/source/fwlib/include/ameba_vector.h
rename to ameba/amebag2/source/fwlib/include/ameba_vector.h
diff --git a/ameba/amebaG2/source/fwlib/include/ameba_vector_table.h b/ameba/amebag2/source/fwlib/include/ameba_vector_table.h
similarity index 98%
rename from ameba/amebaG2/source/fwlib/include/ameba_vector_table.h
rename to ameba/amebag2/source/fwlib/include/ameba_vector_table.h
index 19e84156..65ea967a 100644
--- a/ameba/amebaG2/source/fwlib/include/ameba_vector_table.h
+++ b/ameba/amebag2/source/fwlib/include/ameba_vector_table.h
@@ -23,6 +23,7 @@ typedef enum APIRQn {
 	MemoryManagement_IRQn  			= -12,	/*!< 4 Cortex-M3 Memory Management Interrupt */
 	BusFault_IRQn          			= -11,	/*!< 5 Cortex-M3 Bus Fault Interrupt */
 	UsageFault_IRQn        			= -10,	/*!< 6 Cortex-M3 Usage Fault Interrupt */
+	SecureFault_IRQn       			= -9,	/**< Cortex-M33 Secure Fault Interrupt */
 	SVCall_IRQn            			= -5,	/*!< 11 Cortex-M3 SV Call Interrupt  */
 	DebugMonitor_IRQn      			= -4,	/*!< 12 Cortex-M3 Debug Monitor Interrupt */
 	PendSV_IRQn            			= -2,	/*!< 14 Cortex-M3 Pend SV Interrupt */
diff --git a/ameba/amebaG2/source/fwlib/include/ameba_wakepin.h b/ameba/amebag2/source/fwlib/include/ameba_wakepin.h
similarity index 100%
rename from ameba/amebaG2/source/fwlib/include/ameba_wakepin.h
rename to ameba/amebag2/source/fwlib/include/ameba_wakepin.h
diff --git a/ameba/amebaG2/source/fwlib/include/ameba_wdg.h b/ameba/amebag2/source/fwlib/include/ameba_wdg.h
similarity index 99%
rename from ameba/amebaG2/source/fwlib/include/ameba_wdg.h
rename to ameba/amebag2/source/fwlib/include/ameba_wdg.h
index f0a83015..0ccd65d3 100644
--- a/ameba/amebaG2/source/fwlib/include/ameba_wdg.h
+++ b/ameba/amebag2/source/fwlib/include/ameba_wdg.h
@@ -210,4 +210,4 @@ _LONG_CALL_ void WDG_Cmd(WDG_TypeDef *WDG, u32 NewState);
 
 /** @} */
 
-/** @} */
\ No newline at end of file
+/** @} */
diff --git a/ameba/amebaG2/source/fwlib/include/basic_types.h b/ameba/amebag2/source/fwlib/include/basic_types.h
similarity index 100%
rename from ameba/amebaG2/source/fwlib/include/basic_types.h
rename to ameba/amebag2/source/fwlib/include/basic_types.h
diff --git a/ameba/amebaG2/source/fwlib/include/cmsis.h b/ameba/amebag2/source/fwlib/include/cmsis.h
similarity index 100%
rename from ameba/amebaG2/source/fwlib/include/cmsis.h
rename to ameba/amebag2/source/fwlib/include/cmsis.h
diff --git a/ameba/amebaG2/source/fwlib/include/cmsis_cpu.h b/ameba/amebag2/source/fwlib/include/cmsis_cpu.h
similarity index 100%
rename from ameba/amebaG2/source/fwlib/include/cmsis_cpu.h
rename to ameba/amebag2/source/fwlib/include/cmsis_cpu.h
diff --git a/ameba/amebaG2/source/fwlib/include/cmsis_ridr.h b/ameba/amebag2/source/fwlib/include/cmsis_ridr.h
similarity index 100%
rename from ameba/amebaG2/source/fwlib/include/cmsis_ridr.h
rename to ameba/amebag2/source/fwlib/include/cmsis_ridr.h
diff --git a/ameba/amebaG2/source/fwlib/include/hal_platform.h b/ameba/amebag2/source/fwlib/include/hal_platform.h
similarity index 100%
rename from ameba/amebaG2/source/fwlib/include/hal_platform.h
rename to ameba/amebag2/source/fwlib/include/hal_platform.h
diff --git a/ameba/amebaG2/source/fwlib/include/mpu_config.h b/ameba/amebag2/source/fwlib/include/mpu_config.h
similarity index 100%
rename from ameba/amebaG2/source/fwlib/include/mpu_config.h
rename to ameba/amebag2/source/fwlib/include/mpu_config.h
diff --git a/ameba/amebaG2/source/fwlib/include/rom/ameba_dump_stack.h b/ameba/amebag2/source/fwlib/include/rom/ameba_dump_stack.h
similarity index 100%
rename from ameba/amebaG2/source/fwlib/include/rom/ameba_dump_stack.h
rename to ameba/amebag2/source/fwlib/include/rom/ameba_dump_stack.h
diff --git a/ameba/amebaG2/source/fwlib/include/rom/ameba_monitor.h b/ameba/amebag2/source/fwlib/include/rom/ameba_monitor.h
similarity index 100%
rename from ameba/amebaG2/source/fwlib/include/rom/ameba_monitor.h
rename to ameba/amebag2/source/fwlib/include/rom/ameba_monitor.h
diff --git a/ameba/amebaG2/source/fwlib/include/rom/ameba_rv32_crashdump.h b/ameba/amebag2/source/fwlib/include/rom/ameba_rv32_crashdump.h
similarity index 100%
rename from ameba/amebaG2/source/fwlib/include/rom/ameba_rv32_crashdump.h
rename to ameba/amebag2/source/fwlib/include/rom/ameba_rv32_crashdump.h
diff --git a/ameba/amebaG2/source/fwlib/include/rom/ameba_shell.h b/ameba/amebag2/source/fwlib/include/rom/ameba_shell.h
similarity index 100%
rename from ameba/amebaG2/source/fwlib/include/rom/ameba_shell.h
rename to ameba/amebag2/source/fwlib/include/rom/ameba_shell.h
diff --git a/ameba/amebaG2/source/fwlib/include/rom/ameba_v8m_crashdump.h b/ameba/amebag2/source/fwlib/include/rom/ameba_v8m_crashdump.h
similarity index 100%
rename from ameba/amebaG2/source/fwlib/include/rom/ameba_v8m_crashdump.h
rename to ameba/amebag2/source/fwlib/include/rom/ameba_v8m_crashdump.h
diff --git a/ameba/amebaG2/source/fwlib/include/rom/bootutil_misc.h b/ameba/amebag2/source/fwlib/include/rom/bootutil_misc.h
similarity index 100%
rename from ameba/amebaG2/source/fwlib/include/rom/bootutil_misc.h
rename to ameba/amebag2/source/fwlib/include/rom/bootutil_misc.h
diff --git a/ameba/amebaG2/source/fwlib/include/rom/diag.h b/ameba/amebag2/source/fwlib/include/rom/diag.h
similarity index 100%
rename from ameba/amebaG2/source/fwlib/include/rom/diag.h
rename to ameba/amebag2/source/fwlib/include/rom/diag.h
diff --git a/ameba/amebaG2/source/fwlib/include/rom/fault_injection_hardening.h b/ameba/amebag2/source/fwlib/include/rom/fault_injection_hardening.h
similarity index 100%
rename from ameba/amebaG2/source/fwlib/include/rom/fault_injection_hardening.h
rename to ameba/amebag2/source/fwlib/include/rom/fault_injection_hardening.h
diff --git a/ameba/amebaG2/source/fwlib/include/rom/fault_injection_hardening_delay_rng.h b/ameba/amebag2/source/fwlib/include/rom/fault_injection_hardening_delay_rng.h
similarity index 100%
rename from ameba/amebaG2/source/fwlib/include/rom/fault_injection_hardening_delay_rng.h
rename to ameba/amebag2/source/fwlib/include/rom/fault_injection_hardening_delay_rng.h
diff --git a/ameba/amebaG2/source/fwlib/include/rom/log.h b/ameba/amebag2/source/fwlib/include/rom/log.h
similarity index 100%
rename from ameba/amebaG2/source/fwlib/include/rom/log.h
rename to ameba/amebag2/source/fwlib/include/rom/log.h
diff --git a/ameba/amebaG2/source/fwlib/include/rom/memproc.h b/ameba/amebag2/source/fwlib/include/rom/memproc.h
similarity index 100%
rename from ameba/amebaG2/source/fwlib/include/rom/memproc.h
rename to ameba/amebag2/source/fwlib/include/rom/memproc.h
diff --git a/ameba/amebaG2/source/fwlib/include/rom/rand.h b/ameba/amebag2/source/fwlib/include/rom/rand.h
similarity index 100%
rename from ameba/amebaG2/source/fwlib/include/rom/rand.h
rename to ameba/amebag2/source/fwlib/include/rom/rand.h
diff --git a/ameba/amebag2/source/fwlib/include/rom/sscanf_minimal.h b/ameba/amebag2/source/fwlib/include/rom/sscanf_minimal.h
new file mode 100644
index 00000000..434ca782
--- /dev/null
+++ b/ameba/amebag2/source/fwlib/include/rom/sscanf_minimal.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2024 Realtek Semiconductor Corp.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _SSCANF_MINIMAL_H_
+#define _SSCANF_MINIMAL_H_
+
+extern int _sscanf_ss(const char *buf, const char *fmt, ...);
+
+#endif
diff --git a/ameba/amebaG2/source/fwlib/include/rom/strproc.h b/ameba/amebag2/source/fwlib/include/rom/strproc.h
similarity index 100%
rename from ameba/amebaG2/source/fwlib/include/rom/strproc.h
rename to ameba/amebag2/source/fwlib/include/rom/strproc.h
diff --git a/ameba/amebaG2/source/fwlib/include/rom/strproc_private.h b/ameba/amebag2/source/fwlib/include/rom/strproc_private.h
similarity index 100%
rename from ameba/amebaG2/source/fwlib/include/rom/strproc_private.h
rename to ameba/amebag2/source/fwlib/include/rom/strproc_private.h
diff --git a/ameba/amebaG2/source/fwlib/include/section_config.h b/ameba/amebag2/source/fwlib/include/section_config.h
similarity index 100%
rename from ameba/amebaG2/source/fwlib/include/section_config.h
rename to ameba/amebag2/source/fwlib/include/section_config.h
diff --git a/ameba/amebaG2/source/fwlib/include/sysreg.h b/ameba/amebag2/source/fwlib/include/sysreg.h
similarity index 100%
rename from ameba/amebaG2/source/fwlib/include/sysreg.h
rename to ameba/amebag2/source/fwlib/include/sysreg.h
diff --git a/ameba/amebaG2/source/fwlib/include/sysreg_aon.h b/ameba/amebag2/source/fwlib/include/sysreg_aon.h
similarity index 99%
rename from ameba/amebaG2/source/fwlib/include/sysreg_aon.h
rename to ameba/amebag2/source/fwlib/include/sysreg_aon.h
index 103eebcf..7a67a0dc 100644
--- a/ameba/amebaG2/source/fwlib/include/sysreg_aon.h
+++ b/ameba/amebag2/source/fwlib/include/sysreg_aon.h
@@ -662,4 +662,4 @@
 
 /** @} */
 
-/** @} */
\ No newline at end of file
+/** @} */
diff --git a/ameba/amebaG2/source/fwlib/include/sysreg_cpu_mmu.h b/ameba/amebag2/source/fwlib/include/sysreg_cpu_mmu.h
similarity index 100%
rename from ameba/amebaG2/source/fwlib/include/sysreg_cpu_mmu.h
rename to ameba/amebag2/source/fwlib/include/sysreg_cpu_mmu.h
diff --git a/ameba/amebaG2/source/fwlib/include/sysreg_ldo.h b/ameba/amebag2/source/fwlib/include/sysreg_ldo.h
similarity index 99%
rename from ameba/amebaG2/source/fwlib/include/sysreg_ldo.h
rename to ameba/amebag2/source/fwlib/include/sysreg_ldo.h
index 45a14610..cd43b4e6 100644
--- a/ameba/amebaG2/source/fwlib/include/sysreg_ldo.h
+++ b/ameba/amebag2/source/fwlib/include/sysreg_ldo.h
@@ -435,4 +435,4 @@ bool LDO_MemSetInSleep(u8 sleep_mode);
 
 /** @} */
 
-#endif
\ No newline at end of file
+#endif
diff --git a/ameba/amebaG2/source/fwlib/include/sysreg_lsys.h b/ameba/amebag2/source/fwlib/include/sysreg_lsys.h
similarity index 100%
rename from ameba/amebaG2/source/fwlib/include/sysreg_lsys.h
rename to ameba/amebag2/source/fwlib/include/sysreg_lsys.h
diff --git a/ameba/amebaG2/source/fwlib/include/sysreg_mem_ctrl.h b/ameba/amebag2/source/fwlib/include/sysreg_mem_ctrl.h
similarity index 99%
rename from ameba/amebaG2/source/fwlib/include/sysreg_mem_ctrl.h
rename to ameba/amebag2/source/fwlib/include/sysreg_mem_ctrl.h
index b24de727..21091c13 100644
--- a/ameba/amebaG2/source/fwlib/include/sysreg_mem_ctrl.h
+++ b/ameba/amebag2/source/fwlib/include/sysreg_mem_ctrl.h
@@ -1443,4 +1443,4 @@
 
 /** @} */
 
-/** @} */
\ No newline at end of file
+/** @} */
diff --git a/ameba/amebaG2/source/fwlib/include/sysreg_pad.h b/ameba/amebag2/source/fwlib/include/sysreg_pad.h
similarity index 99%
rename from ameba/amebaG2/source/fwlib/include/sysreg_pad.h
rename to ameba/amebag2/source/fwlib/include/sysreg_pad.h
index 657dffce..aa1030d4 100644
--- a/ameba/amebaG2/source/fwlib/include/sysreg_pad.h
+++ b/ameba/amebag2/source/fwlib/include/sysreg_pad.h
@@ -298,4 +298,4 @@
 
 /** @} */
 
-/** @} */
\ No newline at end of file
+/** @} */
diff --git a/ameba/amebaG2/source/fwlib/include/sysreg_pll.h b/ameba/amebag2/source/fwlib/include/sysreg_pll.h
similarity index 99%
rename from ameba/amebaG2/source/fwlib/include/sysreg_pll.h
rename to ameba/amebag2/source/fwlib/include/sysreg_pll.h
index a9d76701..50cc5594 100644
--- a/ameba/amebaG2/source/fwlib/include/sysreg_pll.h
+++ b/ameba/amebag2/source/fwlib/include/sysreg_pll.h
@@ -406,4 +406,4 @@ typedef struct {
 
 /** @} */
 
-/** @} */
\ No newline at end of file
+/** @} */
diff --git a/ameba/amebaG2/source/fwlib/include/sysreg_pmc.h b/ameba/amebag2/source/fwlib/include/sysreg_pmc.h
similarity index 100%
rename from ameba/amebaG2/source/fwlib/include/sysreg_pmc.h
rename to ameba/amebag2/source/fwlib/include/sysreg_pmc.h
diff --git a/ameba/amebaG2/source/fwlib/include/sysreg_sdm.h b/ameba/amebag2/source/fwlib/include/sysreg_sdm.h
similarity index 99%
rename from ameba/amebaG2/source/fwlib/include/sysreg_sdm.h
rename to ameba/amebag2/source/fwlib/include/sysreg_sdm.h
index f8b0c40f..684e94e0 100644
--- a/ameba/amebaG2/source/fwlib/include/sysreg_sdm.h
+++ b/ameba/amebag2/source/fwlib/include/sysreg_sdm.h
@@ -134,4 +134,4 @@ typedef struct {
 
 /* MANUAL_GEN_END */
 
-#endif
\ No newline at end of file
+#endif
diff --git a/ameba/amebaG2/source/fwlib/include/sysreg_sec.h b/ameba/amebag2/source/fwlib/include/sysreg_sec.h
similarity index 99%
rename from ameba/amebaG2/source/fwlib/include/sysreg_sec.h
rename to ameba/amebag2/source/fwlib/include/sysreg_sec.h
index f56f4a97..0a3a1a96 100644
--- a/ameba/amebaG2/source/fwlib/include/sysreg_sec.h
+++ b/ameba/amebag2/source/fwlib/include/sysreg_sec.h
@@ -614,4 +614,4 @@
 
 /** @} */
 
-/** @} */
\ No newline at end of file
+/** @} */
diff --git a/ameba/amebaG2/source/fwlib/include/sysreg_swr.h b/ameba/amebag2/source/fwlib/include/sysreg_swr.h
similarity index 99%
rename from ameba/amebaG2/source/fwlib/include/sysreg_swr.h
rename to ameba/amebag2/source/fwlib/include/sysreg_swr.h
index d6d83063..4c32d64c 100644
--- a/ameba/amebaG2/source/fwlib/include/sysreg_swr.h
+++ b/ameba/amebag2/source/fwlib/include/sysreg_swr.h
@@ -443,4 +443,4 @@ enum SWR_Mode {
 
 /* MANUAL_GEN_END */
 
-#endif
\ No newline at end of file
+#endif
diff --git a/ameba/amebaG2/source/fwlib/include/sysreg_wlafe.h b/ameba/amebag2/source/fwlib/include/sysreg_wlafe.h
similarity index 99%
rename from ameba/amebaG2/source/fwlib/include/sysreg_wlafe.h
rename to ameba/amebag2/source/fwlib/include/sysreg_wlafe.h
index 3434abd5..88291f91 100644
--- a/ameba/amebaG2/source/fwlib/include/sysreg_wlafe.h
+++ b/ameba/amebag2/source/fwlib/include/sysreg_wlafe.h
@@ -381,4 +381,4 @@ typedef struct {
 
 /** @} */
 
-/** @} */
\ No newline at end of file
+/** @} */
diff --git a/ameba/amebaG2/source/fwlib/include/sysreg_xtal.h b/ameba/amebag2/source/fwlib/include/sysreg_xtal.h
similarity index 99%
rename from ameba/amebaG2/source/fwlib/include/sysreg_xtal.h
rename to ameba/amebag2/source/fwlib/include/sysreg_xtal.h
index 73f1ddc2..11892b0c 100644
--- a/ameba/amebaG2/source/fwlib/include/sysreg_xtal.h
+++ b/ameba/amebag2/source/fwlib/include/sysreg_xtal.h
@@ -461,4 +461,4 @@ enum xtal_mode_sleep {
 
 /** @} */
 
-/** @} */
\ No newline at end of file
+/** @} */
diff --git a/ameba/amebaG2/source/fwlib/ram_common/ameba_a2c.c b/ameba/amebag2/source/fwlib/ram_common/ameba_a2c.c
similarity index 96%
rename from ameba/amebaG2/source/fwlib/ram_common/ameba_a2c.c
rename to ameba/amebag2/source/fwlib/ram_common/ameba_a2c.c
index d004e1e9..b8bd412f 100644
--- a/ameba/amebaG2/source/fwlib/ram_common/ameba_a2c.c
+++ b/ameba/amebag2/source/fwlib/ram_common/ameba_a2c.c
@@ -333,7 +333,6 @@ void A2C_WriteMsg(A2C_TypeDef *A2Cx, A2C_TxMsgTypeDef *TxMsg)
 	u32 a2c_ram_arb = 0;
 	u32 a2c_ram_cmd = 0;
 	u32 a2c_ram_cs = 0;
-	u32 i;
 
 	assert_param(IS_A2C_ALL_PERIPH(A2Cx));
 	assert_param(IS_A2C_FRAME_TYPE(TxMsg->RTR));
@@ -341,7 +340,7 @@ void A2C_WriteMsg(A2C_TypeDef *A2Cx, A2C_TxMsgTypeDef *TxMsg)
 	assert_param(TxMsg->DLC <= 64);
 	assert_param(TxMsg->MsgBufferIdx <= 15);
 
-	/*configure cmd register, enable access*/
+	/* Enable Msg buf[x] access*/
 	a2c_ram_cmd |= (A2C_BIT_RAM_BUFFER_EN | A2C_BIT_RAM_ACC_ARB | A2C_BIT_RAM_ACC_CS | A2C_BIT_RAM_ACC_MASK | \
 					A2C_BIT_RAM_ACC_DATA_MASK | A2C_BIT_RAM_DIR);
 	a2c_ram_cmd |= TxMsg->MsgBufferIdx;
@@ -369,12 +368,12 @@ void A2C_WriteMsg(A2C_TypeDef *A2Cx, A2C_TxMsgTypeDef *TxMsg)
 
 	/*fill data, can2.0 8 bytes, can fd 64 bytes*/
 	if (TxMsg->RTR == A2C_DATA_FRAME) {
-		for (i = 0; i < 16; i++) {
-			HAL_WRITE32(&A2Cx->A2C_RAM_FDDATA_x[i], 0, *(u32 *)(&TxMsg->Data[(16 - i - 1) * 4]));
+		for (int i = 0; i < 16; i++) {
+			A2Cx->A2C_RAM_FDDATA_x[16 - i - 1] = TxMsg->Data_32[i];
 		}
 	}
 
-	/*finally, operate cmd register to write frame info in register into the ram message buffer*/
+	/* Write frame info in register into the ram message buffer */
 	a2c_ram_cmd |= A2C_BIT_RAM_START;
 	A2Cx->A2C_RAM_CMD = a2c_ram_cmd;
 	while (A2Cx->A2C_RAM_CMD & A2C_BIT_RAM_START);
@@ -415,12 +414,17 @@ void A2C_SetRxMsgBuf(A2C_TypeDef *A2Cx, A2C_RxMsgTypeDef *RxMsg)
 
 
 	/*configure MASK ID register*/
-	a2c_ram_mask |= A2C_RAM_ID_MASK(RxMsg->ID_MASK);
+	if (RxMsg->IDE == A2C_STANDARD_FRAME) {
+		A2Cx->A2C_RAM_MASK = A2C_RAM_ID_MASK(RxMsg->ID_MASK << 18);
+	} else {
+		A2Cx->A2C_RAM_MASK = A2C_RAM_ID_MASK(RxMsg->ID_MASK);
+	}
+
 	a2c_ram_mask |= RxMsg->IDE_Mask;
 	a2c_ram_mask |= RxMsg->RTR_Mask;
 	A2Cx->A2C_RAM_MASK = a2c_ram_mask;
 
-	/*finally, operate cmd register to write RX setting info in register into the ram message buffer*/
+	/* Write RX setting info in register into the ram message buffer */
 	a2c_ram_cmd |= A2C_BIT_RAM_START;
 	A2Cx->A2C_RAM_CMD = a2c_ram_cmd;
 	while (A2Cx->A2C_RAM_CMD & A2C_BIT_RAM_START);
@@ -443,11 +447,12 @@ void A2C_ReadMsg(A2C_TypeDef *A2Cx, A2C_RxMsgTypeDef *RxMsg)
 	assert_param(IS_A2C_ALL_PERIPH(A2Cx));
 	assert_param(RxMsg->MsgBufferIdx <= 15);
 
-	/*configure cmd register, enable access*/
+	/* Enable Msg buf[x] access */
 	a2c_ram_cmd |= (A2C_BIT_RAM_BUFFER_EN | A2C_BIT_RAM_ACC_ARB | A2C_BIT_RAM_ACC_CS | A2C_BIT_RAM_ACC_MASK | A2C_BIT_RAM_ACC_DATA_MASK);
 	a2c_ram_cmd |= RxMsg->MsgBufferIdx;
 	a2c_ram_cmd |= A2C_BIT_RAM_START;
-	A2Cx->A2C_RAM_CMD = a2c_ram_cmd;/*firstly, operate cmd register to read frame into register from ram message buffer*/
+	A2Cx->A2C_RAM_CMD = a2c_ram_cmd;
+	/* Read frame into register from ram message buffer */
 	while (A2Cx->A2C_RAM_CMD & A2C_BIT_RAM_START);
 
 	/*read ARB register*/
@@ -488,7 +493,7 @@ void A2C_ReadMsg(A2C_TypeDef *A2Cx, A2C_RxMsgTypeDef *RxMsg)
 	/*configure DATA register: can2.0 8 bytes, can fd 64 bytes*/
 	if (RxMsg->RTR == A2C_DATA_FRAME) {
 		for (i = 0; i < 16; i++) {
-			*((u32 *)(&RxMsg->Data[(16 - i - 1) * 4])) = HAL_READ32(&A2Cx->A2C_RAM_FDDATA_x[i], 0);
+			RxMsg->Data_32[i] = A2Cx->A2C_RAM_FDDATA_x[16 - i - 1];
 		}
 	}
 }
@@ -512,7 +517,7 @@ void A2C_TxAutoReply(A2C_TypeDef *A2Cx, A2C_TxMsgTypeDef *TxMsg)
 	assert_param(TxMsg->DLC <= 64);
 	assert_param(TxMsg->MsgBufferIdx <= 15);
 
-	/*configure cmd register, enable access*/
+	/* Enable Msg buf[x] access */
 	a2c_ram_cmd |= (A2C_BIT_RAM_BUFFER_EN | A2C_BIT_RAM_ACC_ARB | A2C_BIT_RAM_ACC_CS | A2C_BIT_RAM_ACC_MASK | \
 					A2C_BIT_RAM_ACC_DATA_MASK | A2C_BIT_RAM_DIR);
 	a2c_ram_cmd |= TxMsg->MsgBufferIdx;
@@ -548,7 +553,7 @@ void A2C_TxAutoReply(A2C_TypeDef *A2Cx, A2C_TxMsgTypeDef *TxMsg)
 		}
 	}
 
-	/*finally, operate cmd register to write frame info in register into the ram message buffer*/
+	/* Write frame info in register into the ram message buffer*/
 	a2c_ram_cmd |= A2C_BIT_RAM_START;
 	A2Cx->A2C_RAM_CMD = a2c_ram_cmd;
 	while (A2Cx->A2C_RAM_CMD & A2C_BIT_RAM_START);
@@ -576,7 +581,6 @@ void A2C_RxAutoReply(A2C_TypeDef *A2Cx, A2C_RxMsgTypeDef *RxMsg)
 	a2c_ram_cmd |= (A2C_BIT_RAM_BUFFER_EN | A2C_BIT_RAM_ACC_ARB | A2C_BIT_RAM_ACC_CS | A2C_BIT_RAM_ACC_MASK | \
 					A2C_BIT_RAM_ACC_DATA_MASK | A2C_BIT_RAM_DIR);
 	a2c_ram_cmd |= RxMsg->MsgBufferIdx;
-	//A2Cx->A2C_RAM_CMD = a2c_ram_cmd;
 
 	/*configure frame ARB register*/
 	a2c_ram_arb = A2Cx->A2C_RAM_ARB;
@@ -607,7 +611,7 @@ void A2C_RxAutoReply(A2C_TypeDef *A2Cx, A2C_RxMsgTypeDef *RxMsg)
 	a2c_ram_mask |= RxMsg->RTR_Mask;
 	A2Cx->A2C_RAM_MASK = a2c_ram_mask;
 
-	/*finally, operate cmd register to write RX setting info in register into the ram message buffer*/
+	/* Write RX setting into the ram message buffer*/
 	a2c_ram_cmd |= A2C_BIT_RAM_START;
 	A2Cx->A2C_RAM_CMD = a2c_ram_cmd;
 	while (A2Cx->A2C_RAM_CMD & A2C_BIT_RAM_START);
@@ -1150,7 +1154,7 @@ void A2C_FillTXDmaBuffer(A2C_TypeDef *A2Cx, A2C_TxMsgTypeDef *TxMsg)
 
 	/*configure cmd register, enable access*/
 	a2c_ram_cmd |= (A2C_BIT_RAM_BUFFER_EN | A2C_BIT_RAM_ACC_ARB | A2C_BIT_RAM_ACC_CS | A2C_BIT_RAM_ACC_MASK | \
-					/* A2C_RAM_ACC_DAT_MASK  | */ A2C_BIT_RAM_DIR);
+					A2C_BIT_RAM_ACC_DATA_MASK  |  A2C_BIT_RAM_DIR);
 	a2c_ram_cmd |= TxMsg->MsgBufferIdx;
 	A2Cx->A2C_RAM_CMD = a2c_ram_cmd;
 
@@ -1179,16 +1183,15 @@ void A2C_FillTXDmaBuffer(A2C_TypeDef *A2Cx, A2C_TxMsgTypeDef *TxMsg)
 
 	/*fill data, can2.0 8 bytes, can fd 64 bytes*/
 	if (TxMsg->RTR == A2C_DATA_FRAME) {
-		for (i = 0; i < 2; i++) {
-			// A2Cx->A2C_RAM_FDDATA_x[i] = TxMsg->Data[(16 - i - 1) * 4];
-			A2Cx->A2C_RAM_FDDATA_x[i] = TxMsg->Data[(2 - i - 1) * 4];
+		for (i = 0; i < 16; i++) {
+			A2Cx->A2C_RAM_FDDATA_x[16 - i - 1] = TxMsg->Data_32[i];
 		}
 	}
 
-	/*finally, operate cmd register to write frame info in register into the ram message buffer*/
+	/* Write frame info into the ram message buffer*/
 	a2c_ram_cmd |= A2C_BIT_RAM_START;
 	A2Cx->A2C_RAM_CMD = a2c_ram_cmd;
-	//while(A2CxBufer->A2C_RAM_CMD&A2C_BIT_RAM_START);
+	while (A2Cx->A2C_RAM_CMD & A2C_BIT_RAM_START);
 }
 
 
@@ -1221,4 +1224,4 @@ void A2C_RamBufferMapConfig(A2C_TypeDef *A2Cx, u32 *pPara)
 
 /**
   * @}
-  */
\ No newline at end of file
+  */
diff --git a/ameba/amebaG2/source/fwlib/ram_common/ameba_adc.c b/ameba/amebag2/source/fwlib/ram_common/ameba_adc.c
similarity index 99%
rename from ameba/amebaG2/source/fwlib/ram_common/ameba_adc.c
rename to ameba/amebag2/source/fwlib/ram_common/ameba_adc.c
index 4f849216..bd3fafb0 100644
--- a/ameba/amebaG2/source/fwlib/ram_common/ameba_adc.c
+++ b/ameba/amebag2/source/fwlib/ram_common/ameba_adc.c
@@ -905,4 +905,4 @@ u32 ADC_GetSampleValue(s32 VolMV)
 
 /**
  * @}
- */
\ No newline at end of file
+ */
diff --git a/ameba/amebaG2/source/fwlib/ram_common/ameba_aontimer.c b/ameba/amebag2/source/fwlib/ram_common/ameba_aontimer.c
similarity index 100%
rename from ameba/amebaG2/source/fwlib/ram_common/ameba_aontimer.c
rename to ameba/amebag2/source/fwlib/ram_common/ameba_aontimer.c
diff --git a/ameba/amebaG2/source/fwlib/ram_common/ameba_arch.c b/ameba/amebag2/source/fwlib/ram_common/ameba_arch.c
similarity index 99%
rename from ameba/amebaG2/source/fwlib/ram_common/ameba_arch.c
rename to ameba/amebag2/source/fwlib/ram_common/ameba_arch.c
index eb6c3d76..0f27540f 100644
--- a/ameba/amebaG2/source/fwlib/ram_common/ameba_arch.c
+++ b/ameba/amebag2/source/fwlib/ram_common/ameba_arch.c
@@ -156,4 +156,3 @@ void irq_enable_restore(u32 PrevStatus)
 {
 	__set_PRIMASK(PrevStatus);
 }
-
diff --git a/ameba/amebaG2/source/fwlib/ram_common/ameba_audio_clock.c b/ameba/amebag2/source/fwlib/ram_common/ameba_audio_clock.c
similarity index 100%
rename from ameba/amebaG2/source/fwlib/ram_common/ameba_audio_clock.c
rename to ameba/amebag2/source/fwlib/ram_common/ameba_audio_clock.c
diff --git a/ameba/amebaG2/source/fwlib/ram_common/ameba_bor.c b/ameba/amebag2/source/fwlib/ram_common/ameba_bor.c
similarity index 100%
rename from ameba/amebaG2/source/fwlib/ram_common/ameba_bor.c
rename to ameba/amebag2/source/fwlib/ram_common/ameba_bor.c
diff --git a/ameba/amebaG2/source/fwlib/ram_common/ameba_captouch.c b/ameba/amebag2/source/fwlib/ram_common/ameba_captouch.c
similarity index 99%
rename from ameba/amebaG2/source/fwlib/ram_common/ameba_captouch.c
rename to ameba/amebag2/source/fwlib/ram_common/ameba_captouch.c
index 7675e823..a136b8dc 100644
--- a/ameba/amebaG2/source/fwlib/ram_common/ameba_captouch.c
+++ b/ameba/amebag2/source/fwlib/ram_common/ameba_captouch.c
@@ -1175,4 +1175,4 @@ u8 CapTouch_RXGDMA_Init(
 
 /**
  * @}
- */
\ No newline at end of file
+ */
diff --git a/ameba/amebaG2/source/fwlib/ram_common/ameba_clk.c b/ameba/amebag2/source/fwlib/ram_common/ameba_clk.c
similarity index 94%
rename from ameba/amebaG2/source/fwlib/ram_common/ameba_clk.c
rename to ameba/amebag2/source/fwlib/ram_common/ameba_clk.c
index e192f36d..95a437b6 100644
--- a/ameba/amebaG2/source/fwlib/ram_common/ameba_clk.c
+++ b/ameba/amebag2/source/fwlib/ram_common/ameba_clk.c
@@ -15,9 +15,14 @@ void SDM32K_Enable(void)
 {
 
 	SDM_TypeDef *SDM = SDM_DEV;
+	u32 temp = SDM->SDM_CTRL0;
 
 	SDM->SDM_TIMEOUT = SDM_TIEMRCAL_INTERVAL_1MIN;
-	SDM->SDM_CTRL0 |= SDM_BIT_EN | SDM_BIT_RST | SDM_BIT_ALWAYS_CAL_EN | SDM_BIT_TIMER_CAL_EN;
+	temp |= SDM_BIT_EN | SDM_BIT_RST | SDM_BIT_ALWAYS_CAL_EN | SDM_BIT_TIMER_CAL_EN;
+
+	/*Switch sdm32k mode from user_defined parameter mode to default mode.*/
+	temp &= ~SDM_BIT_MOD_SEL;
+	SDM->SDM_CTRL0 = temp;
 }
 
 /**
@@ -38,6 +43,32 @@ void SDM32K_TimerCalEnable(u32 newstatus)
 	}
 }
 
+/**
+  * @brief  32K clock calibration factor modify
+  * @param  newstatus: can be one of the following values:
+  *		 @arg ENABLE
+  *		 @arg FALSE
+  * @note
+  *		From HW Experiment, add 3 to SDM_OBS_REF_CYC(default 312500)
+  */
+void SDM32K_CalFactorModify(u32 newstatus)
+{
+	SDM_TypeDef *SDM = SDM_DEV;
+	u32 temp = 0;
+
+	if (newstatus == ENABLE) {
+		SDM->SDM_CTRL1 = SDM_OBS_CYC_DEFAULT;
+		SDM->SDM_CTRL2 = SDM_OBS_REF_CYC_MODIFY;
+		SDM->SDM_CTRL3 = SDM_XTAL_PERIOD_DEFAULT;
+		temp = SDM->SDM_CTRL0 | SDM_BIT_MOD_SEL;
+		SDM->SDM_CTRL0 = temp;
+	} else {
+		temp = SDM->SDM_CTRL0 & ~SDM_BIT_MOD_SEL;
+		SDM->SDM_CTRL0 = temp;
+	}
+
+}
+
 /**
   * @brief  Get osc calibration result.
   * @param  Option: can be one of the following values:
diff --git a/ameba/amebaG2/source/fwlib/ram_common/ameba_codec.c b/ameba/amebag2/source/fwlib/ram_common/ameba_codec.c
similarity index 100%
rename from ameba/amebaG2/source/fwlib/ram_common/ameba_codec.c
rename to ameba/amebag2/source/fwlib/ram_common/ameba_codec.c
diff --git a/ameba/amebaG2/source/fwlib/ram_common/ameba_flash_ram.c b/ameba/amebag2/source/fwlib/ram_common/ameba_flash_ram.c
similarity index 100%
rename from ameba/amebaG2/source/fwlib/ram_common/ameba_flash_ram.c
rename to ameba/amebag2/source/fwlib/ram_common/ameba_flash_ram.c
diff --git a/ameba/amebaG2/source/fwlib/ram_common/ameba_gdma_memcpy.c b/ameba/amebag2/source/fwlib/ram_common/ameba_gdma_memcpy.c
similarity index 100%
rename from ameba/amebaG2/source/fwlib/ram_common/ameba_gdma_memcpy.c
rename to ameba/amebag2/source/fwlib/ram_common/ameba_gdma_memcpy.c
diff --git a/ameba/amebaG2/source/fwlib/ram_common/ameba_gdma_ram.c b/ameba/amebag2/source/fwlib/ram_common/ameba_gdma_ram.c
similarity index 97%
rename from ameba/amebaG2/source/fwlib/ram_common/ameba_gdma_ram.c
rename to ameba/amebag2/source/fwlib/ram_common/ameba_gdma_ram.c
index cc5bc757..99aab93f 100644
--- a/ameba/amebaG2/source/fwlib/ram_common/ameba_gdma_ram.c
+++ b/ameba/amebag2/source/fwlib/ram_common/ameba_gdma_ram.c
@@ -600,9 +600,9 @@ u32 GDMA_GetBlkSize(u8 GDMA_Index, u8 GDMA_ChNum)
 	/* Check the parameters */
 	assert_param(IS_GDMA_Index(GDMA_Index));
 	assert_param(IS_GDMA_ChannelNum(GDMA_ChNum));
-	/* block size = DSRx_H(high 5 bit) + SGRx_H(Low 16 bit)*/
-	BlkSize = (GDMA_GET_DSRx_H_BLOCK_TS_H(GDMA->CH[GDMA_ChNum].GDMA_DSRx_H) << 16) + GDMA_GET_SGRx_H_BLOCK_TS_L(GDMA->CH[GDMA_ChNum].GDMA_SGRx_H);
-	return BlkSize;
+
+	BlkSize = GDMA->CH[GDMA_ChNum].GDMA_CTLx_H;
+	return 	BlkSize;
 }
 
 /**
@@ -931,7 +931,30 @@ void GDMA_DestinationScatter(u8 GDMA_Index, u8 GDMA_ChNum, u32 Dst_ScatterCount,
 	GDMA->CH[GDMA_ChNum].GDMA_CTLx_L |= GDMA_BIT_CTLx_L_DST_SCATTER_EN;
 	GDMA->CH[GDMA_ChNum].GDMA_DSRx_L = GDMA_DSRx_L_DSC(Dst_ScatterCount) | GDMA_DSRx_L_DSI(Dst_ScatterInterval);
 }
+/**
+ * @brief Check if the channel is active
+ *
+ * @param GDMA_Index 0
+ * @param GDMA_ChNum 0 ~ 7
+ * @retval TRUE/FALSE
+ */
+__weak
+u8 GDMA_ChannelIsActive(u8 GDMA_Index, u8 GDMA_ChNum)
+{
+	GDMA_TypeDef *GDMA = ((GDMA_TypeDef *) GDMA_BASE);
+	if (TrustZone_IsSecure()) {
+		GDMA = ((GDMA_TypeDef *) GDMA0_REG_BASE_S);
+	}
+	/* Check the parameters */
+	assert_param(IS_GDMA_Index(GDMA_Index));
+	assert_param(IS_GDMA_ChannelNum(GDMA_ChNum));
 
+	if ((GDMA_GET_CHENREG_L_1_CH_EN(GDMA->GDMA_CHENREG_L_1) & BIT(GDMA_ChNum)) && \
+		((GDMA->CH[GDMA_ChNum].GDMA_CFGx_L & GDMA_BIT_CFGx_L_INACTIVE) == 0)) {
+		return TRUE;
+	}
+	return FALSE;
+}
 /**
   * @}
   */
diff --git a/ameba/amebaG2/source/fwlib/ram_common/ameba_gpio_ram.c b/ameba/amebag2/source/fwlib/ram_common/ameba_gpio_ram.c
similarity index 99%
rename from ameba/amebaG2/source/fwlib/ram_common/ameba_gpio_ram.c
rename to ameba/amebag2/source/fwlib/ram_common/ameba_gpio_ram.c
index 9c7d039c..e6c6e975 100644
--- a/ameba/amebaG2/source/fwlib/ram_common/ameba_gpio_ram.c
+++ b/ameba/amebag2/source/fwlib/ram_common/ameba_gpio_ram.c
@@ -179,4 +179,4 @@ void GPIO_UserUnRegIrq(u32 GPIO_Pin)
 
 /** @} */
 
-/** @} */
\ No newline at end of file
+/** @} */
diff --git a/ameba/amebaG2/source/fwlib/ram_common/ameba_i2c.c b/ameba/amebag2/source/fwlib/ram_common/ameba_i2c.c
similarity index 100%
rename from ameba/amebaG2/source/fwlib/ram_common/ameba_i2c.c
rename to ameba/amebag2/source/fwlib/ram_common/ameba_i2c.c
diff --git a/ameba/amebaG2/source/fwlib/ram_common/ameba_ipc_api.c b/ameba/amebag2/source/fwlib/ram_common/ameba_ipc_api.c
similarity index 99%
rename from ameba/amebaG2/source/fwlib/ram_common/ameba_ipc_api.c
rename to ameba/amebag2/source/fwlib/ram_common/ameba_ipc_api.c
index 26496028..65004c0a 100644
--- a/ameba/amebaG2/source/fwlib/ram_common/ameba_ipc_api.c
+++ b/ameba/amebag2/source/fwlib/ram_common/ameba_ipc_api.c
@@ -180,4 +180,4 @@ PIPC_MSG_STRUCT ipc_get_message(u32 IPC_Dir, u8 IPC_ChNum)
 	DCache_Invalidate((u32)&IPC_MSG[msg_idx], sizeof(IPC_MSG_STRUCT));
 
 	return &IPC_MSG[msg_idx];
-}
\ No newline at end of file
+}
diff --git a/ameba/amebaG2/source/fwlib/ram_common/ameba_ipc_ram.c b/ameba/amebag2/source/fwlib/ram_common/ameba_ipc_ram.c
similarity index 99%
rename from ameba/amebaG2/source/fwlib/ram_common/ameba_ipc_ram.c
rename to ameba/amebag2/source/fwlib/ram_common/ameba_ipc_ram.c
index 1008ef60..5bc4968b 100644
--- a/ameba/amebaG2/source/fwlib/ram_common/ameba_ipc_ram.c
+++ b/ameba/amebag2/source/fwlib/ram_common/ameba_ipc_ram.c
@@ -196,4 +196,4 @@ IPC_TypeDef *IPC_GetDevById(u32 cpu_id)
 	} else {
 		return IPCNP_DEV;
 	}
-}
\ No newline at end of file
+}
diff --git a/ameba/amebaG2/source/fwlib/ram_common/ameba_ir.c b/ameba/amebag2/source/fwlib/ram_common/ameba_ir.c
similarity index 100%
rename from ameba/amebaG2/source/fwlib/ram_common/ameba_ir.c
rename to ameba/amebag2/source/fwlib/ram_common/ameba_ir.c
diff --git a/ameba/amebaG2/source/fwlib/ram_common/ameba_lcdc.c b/ameba/amebag2/source/fwlib/ram_common/ameba_lcdc.c
similarity index 99%
rename from ameba/amebaG2/source/fwlib/ram_common/ameba_lcdc.c
rename to ameba/amebag2/source/fwlib/ram_common/ameba_lcdc.c
index d8b103a0..ac3a4684 100644
--- a/ameba/amebaG2/source/fwlib/ram_common/ameba_lcdc.c
+++ b/ameba/amebag2/source/fwlib/ram_common/ameba_lcdc.c
@@ -1197,4 +1197,4 @@ void LCDC_MCUCtrlSwap(LCDC_TypeDef *LCDCx, u8 Status)
 
 /**
  * @}
- */
\ No newline at end of file
+ */
diff --git a/ameba/amebaG2/source/fwlib/ram_common/ameba_ldo.c b/ameba/amebag2/source/fwlib/ram_common/ameba_ldo.c
similarity index 99%
rename from ameba/amebaG2/source/fwlib/ram_common/ameba_ldo.c
rename to ameba/amebag2/source/fwlib/ram_common/ameba_ldo.c
index 26b82f46..116d143e 100644
--- a/ameba/amebaG2/source/fwlib/ram_common/ameba_ldo.c
+++ b/ameba/amebag2/source/fwlib/ram_common/ameba_ldo.c
@@ -84,4 +84,4 @@ bool LDO_MemSetInSleep(u8 sleep_mode)
 	HAL_WRITE32(PMC_BASE, AIP_TRIGGER, Rtemp);
 	ret = TRUE;
 	return ret;
-}
\ No newline at end of file
+}
diff --git a/ameba/amebaG2/source/fwlib/ram_common/ameba_loguart.c b/ameba/amebag2/source/fwlib/ram_common/ameba_loguart.c
similarity index 99%
rename from ameba/amebaG2/source/fwlib/ram_common/ameba_loguart.c
rename to ameba/amebag2/source/fwlib/ram_common/ameba_loguart.c
index d65b93a8..045c87e6 100644
--- a/ameba/amebaG2/source/fwlib/ram_common/ameba_loguart.c
+++ b/ameba/amebag2/source/fwlib/ram_common/ameba_loguart.c
@@ -259,4 +259,4 @@ void LOGUART_PutChar_RAM(u8 c)
 
 /**
  * @}
- */
\ No newline at end of file
+ */
diff --git a/ameba/amebaG2/source/fwlib/ram_common/ameba_mpu_ram.c b/ameba/amebag2/source/fwlib/ram_common/ameba_mpu_ram.c
similarity index 100%
rename from ameba/amebaG2/source/fwlib/ram_common/ameba_mpu_ram.c
rename to ameba/amebag2/source/fwlib/ram_common/ameba_mpu_ram.c
diff --git a/ameba/amebaG2/source/fwlib/ram_common/ameba_pll.c b/ameba/amebag2/source/fwlib/ram_common/ameba_pll.c
similarity index 99%
rename from ameba/amebaG2/source/fwlib/ram_common/ameba_pll.c
rename to ameba/amebag2/source/fwlib/ram_common/ameba_pll.c
index 4b97dac0..cb41ff25 100644
--- a/ameba/amebaG2/source/fwlib/ram_common/ameba_pll.c
+++ b/ameba/amebag2/source/fwlib/ram_common/ameba_pll.c
@@ -393,3 +393,5 @@ void RCC_PeriphClockSource_SPORT(AUDIO_SPORT_TypeDef *Sportx, u32 Source)
 		RTK_LOGE(TAG, "invaild clk source!!!");
 	}
 }
+
+/******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/
diff --git a/ameba/amebaG2/source/fwlib/ram_common/ameba_pmc_com.c b/ameba/amebag2/source/fwlib/ram_common/ameba_pmc_com.c
similarity index 100%
rename from ameba/amebaG2/source/fwlib/ram_common/ameba_pmc_com.c
rename to ameba/amebag2/source/fwlib/ram_common/ameba_pmc_com.c
diff --git a/ameba/amebaG2/source/fwlib/ram_common/ameba_pmctimer.c b/ameba/amebag2/source/fwlib/ram_common/ameba_pmctimer.c
similarity index 100%
rename from ameba/amebaG2/source/fwlib/ram_common/ameba_pmctimer.c
rename to ameba/amebag2/source/fwlib/ram_common/ameba_pmctimer.c
diff --git a/ameba/amebaG2/source/fwlib/ram_common/ameba_pmu.c b/ameba/amebag2/source/fwlib/ram_common/ameba_pmu.c
similarity index 84%
rename from ameba/amebaG2/source/fwlib/ram_common/ameba_pmu.c
rename to ameba/amebag2/source/fwlib/ram_common/ameba_pmu.c
index b61b6313..b134f6fa 100644
--- a/ameba/amebaG2/source/fwlib/ram_common/ameba_pmu.c
+++ b/ameba/amebag2/source/fwlib/ram_common/ameba_pmu.c
@@ -7,7 +7,7 @@
 #include "platform_autoconf.h"
 #include "ameba_soc.h"
 
-uint32_t missing_tick = 0;
+uint32_t cur_device_id = 0;
 
 static uint32_t wakelock     = DEFAULT_WAKELOCK;
 static uint32_t sleep_type = SLEEP_PG; /* 0 is power gate, 1 is clock gate */
@@ -45,7 +45,7 @@ uint32_t pmu_exec_sleep_hook_funs(void)
 	return nDeviceIdOffset;
 }
 
-void pmu_exec_wakeup_hook_funs(uint32_t nDeviceIdMax)
+void pmu_exec_wakeup_hook_funs(uint32_t nDeviceIdMax, uint32_t common_param)
 {
 	PSM_DD_HOOK_INFO *pPsmDdHookInfo = NULL;
 	uint32_t nDeviceIdOffset = 0;
@@ -55,7 +55,7 @@ void pmu_exec_wakeup_hook_funs(uint32_t nDeviceIdMax)
 
 		/*if this device register and sleep_hook_fun not NULL*/
 		if (pPsmDdHookInfo && pPsmDdHookInfo->wakeup_hook_fun) {
-			pPsmDdHookInfo->wakeup_hook_fun(0, pPsmDdHookInfo->wakeup_param_ptr);
+			pPsmDdHookInfo->wakeup_hook_fun(common_param, pPsmDdHookInfo->wakeup_param_ptr);
 		}
 	}
 }
@@ -65,7 +65,13 @@ uint32_t pmu_set_sysactive_time(uint32_t timeout)
 	uint32_t New_Cnt = 0;
 	PMCTIMER_TpyeDef *PMC_TIMER = PMC_TIMER_DEV;
 
-	New_Cnt = (u32)((((u64)timeout) << 15) / 1000); /*convert ms to cnt*/
+	/*convert ms to cnt:
+	  method: the ticks/ms equals 32 + 197/256 = 32.7695, and the deviation is 32.7695 - 32.768 = 0.0046%.
+	  The error is 46µs per second.The reason for using bit shift operations is to avoid division and
+	  improve the speed of operation.
+	*/
+	New_Cnt = (timeout << 5) + (((timeout << 7) + (timeout << 6) + (timeout << 2) + timeout) >> 8);
+
 	PMCTimerCnt_Set(PMC_TIMER, PMC_SLEEP_TIMER, New_Cnt);
 
 	return 0;
@@ -218,13 +224,19 @@ void pmu_pre_sleep_processing(uint32_t *tick_before_sleep)
 #endif
 		sleep_param.dlps_enable = DISABLE;
 	}
-
 	/*  Store gtimer timestamp before sleep */
 	*tick_before_sleep = SYSTIMER_TickGet();
 	/*Disable systick interrupt to avoid interrupting sleep flow*/
 	Systick_Cmd(DISABLE);
+	/* exec sleep hook functions */
+	cur_device_id = pmu_exec_sleep_hook_funs();
+
+	if (cur_device_id != PMU_MAX) {
+		RTK_LOGS(NOTAG, RTK_LOG_ALWAYS, "Sleep blocked because Dev %x  busy\n", cur_device_id);
+		return;
+	}
 
-#if defined(CONFIG_WIFI_HOST_CONTROL)
+#if (!defined (CONFIG_WHC_INTF_IPC) && defined (CONFIG_WHC_DEV))
 	SOCPS_Sleep_FULLMAC(sleep_type);
 #else
 	if (sleep_type == SLEEP_PG) {
@@ -233,7 +245,6 @@ void pmu_pre_sleep_processing(uint32_t *tick_before_sleep)
 		SOCPS_SleepCG();
 	}
 #endif
-	Systick_Cmd(ENABLE);
 }
 
 /* -------- FreeRTOS macro implementation -------- */
@@ -313,7 +324,7 @@ u32 pmc_wakeuptimer_int_hdl(void *Data)
 
 void pmu_init_wakeup_timer(void)
 {
-	InterruptRegister(pmc_wakeuptimer_int_hdl, PMC_TIMER_IRQ, (uint32_t)NULL, PMC_TIMER_INT_PRIO);
+	InterruptRegister(pmc_wakeuptimer_int_hdl, PMC_TIMER_IRQ, 0, PMC_TIMER_INT_PRIO);
 	InterruptEn(PMC_TIMER_IRQ, PMC_TIMER_INT_PRIO);
 	PMCTimer_INTConfig(PMC_TIMER_DEV, PMC_WAKEUP_TIMER, ENABLE);
 }
@@ -322,8 +333,12 @@ void pmu_set_wakeup_timer(uint32_t timeout_ms)
 {
 	uint32_t timeout_cnt = 0;
 	PMCTIMER_TpyeDef *PMC_TIMER = PMC_TIMER_DEV;
-
-	timeout_cnt = (timeout_ms << 15) / 1000;  /*convert ms to cnt*/
+	/*convert ms to cnt:
+	  method: the ticks/ms equals 32 + 197/256 = 32.7695, and the deviation is 32.7695 - 32.768 = 0.0046%.
+	  The error is 46µs per second.The reason for using bit shift operations is to avoid division and
+	  improve the speed of operation.
+	*/
+	timeout_cnt = (timeout_ms << 5) + (((timeout_ms << 7) + (timeout_ms << 6) + (timeout_ms << 2) + timeout_ms) >> 8);
 
 	PMCTimerCnt_Set(PMC_TIMER, PMC_WAKEUP_TIMER, timeout_cnt);
 }
@@ -340,7 +355,13 @@ void pmu_set_dsleep_active_time(uint32_t TimeOutMs)
 	uint32_t New_Cnt = 0;
 	PMCTIMER_TpyeDef *PMC_TIMER = PMC_TIMER_DEV;
 
-	New_Cnt = (TimeOutMs << 15) / 1000;  /*convert ms to cnt*/
+	/*convert ms to cnt:
+	  method: the ticks/ms equals 32 + 197/256 = 32.7695, and the deviation is 32.7695 - 32.768 = 0.0046%.
+	  The error is 46µs per second.The reason for using bit shift operations is to avoid division and
+	  improve the speed of operation.
+	*/
+	New_Cnt = (TimeOutMs << 5) + (((TimeOutMs << 7) + (TimeOutMs << 6) + (TimeOutMs << 2) + TimeOutMs) >> 8);
+
 	PMCTimerCnt_Set(PMC_TIMER, PMC_DSLP_TIMER, New_Cnt);
 }
 
diff --git a/ameba/amebaG2/source/fwlib/ram_common/ameba_ppe.c b/ameba/amebag2/source/fwlib/ram_common/ameba_ppe.c
similarity index 100%
rename from ameba/amebaG2/source/fwlib/ram_common/ameba_ppe.c
rename to ameba/amebag2/source/fwlib/ram_common/ameba_ppe.c
diff --git a/ameba/amebaG2/source/fwlib/ram_common/ameba_pseduo_i2c.c b/ameba/amebag2/source/fwlib/ram_common/ameba_pseduo_i2c.c
similarity index 100%
rename from ameba/amebaG2/source/fwlib/ram_common/ameba_pseduo_i2c.c
rename to ameba/amebag2/source/fwlib/ram_common/ameba_pseduo_i2c.c
diff --git a/ameba/amebaG2/source/fwlib/ram_common/ameba_psram.c b/ameba/amebag2/source/fwlib/ram_common/ameba_psram.c
similarity index 99%
rename from ameba/amebaG2/source/fwlib/ram_common/ameba_psram.c
rename to ameba/amebag2/source/fwlib/ram_common/ameba_psram.c
index 7559e942..fd1a99b6 100644
--- a/ameba/amebaG2/source/fwlib/ram_common/ameba_psram.c
+++ b/ameba/amebag2/source/fwlib/ram_common/ameba_psram.c
@@ -22,8 +22,8 @@ u8 WB_WR_INIT_LATENCY_SPEC[8] = {
 	WB_WR_INIT_LATENCY_5CLK,
 	WB_WR_INIT_LATENCY_6CLK,
 	WB_WR_INIT_LATENCY_7CLK,
-	NULL,
-	NULL,
+	0, //NULL,
+	0, //NULL,
 	WB_WR_INIT_LATENCY_10CLK
 };
 
diff --git a/ameba/amebaG2/source/fwlib/ram_common/ameba_rcc.c b/ameba/amebag2/source/fwlib/ram_common/ameba_rcc.c
similarity index 100%
rename from ameba/amebaG2/source/fwlib/ram_common/ameba_rcc.c
rename to ameba/amebag2/source/fwlib/ram_common/ameba_rcc.c
diff --git a/ameba/amebaG2/source/fwlib/ram_common/ameba_reset.c b/ameba/amebag2/source/fwlib/ram_common/ameba_reset.c
similarity index 99%
rename from ameba/amebaG2/source/fwlib/ram_common/ameba_reset.c
rename to ameba/amebag2/source/fwlib/ram_common/ameba_reset.c
index 47a6916b..6738e0a5 100644
--- a/ameba/amebaG2/source/fwlib/ram_common/ameba_reset.c
+++ b/ameba/amebag2/source/fwlib/ram_common/ameba_reset.c
@@ -203,4 +203,4 @@ void System_Reset(void)
 
 	/* wait for reset */
 	while (1);
-}
\ No newline at end of file
+}
diff --git a/ameba/amebaG2/source/fwlib/ram_common/ameba_rtc.c b/ameba/amebag2/source/fwlib/ram_common/ameba_rtc.c
similarity index 100%
rename from ameba/amebaG2/source/fwlib/ram_common/ameba_rtc.c
rename to ameba/amebag2/source/fwlib/ram_common/ameba_rtc.c
diff --git a/ameba/amebaG2/source/fwlib/ram_common/ameba_sd.c b/ameba/amebag2/source/fwlib/ram_common/ameba_sd.c
similarity index 98%
rename from ameba/amebaG2/source/fwlib/ram_common/ameba_sd.c
rename to ameba/amebag2/source/fwlib/ram_common/ameba_sd.c
index b5592890..2e48edd8 100644
--- a/ameba/amebaG2/source/fwlib/ram_common/ameba_sd.c
+++ b/ameba/amebag2/source/fwlib/ram_common/ameba_sd.c
@@ -27,7 +27,6 @@ static u32 SD_WideBus_Disable(SD_HdlTypeDef *hsd);
 static u32 SD_GetCardSCR(SD_HdlTypeDef *hsd);
 static void SD_Write_IT(SD_HdlTypeDef *hsd);
 static void SD_Read_IT(SD_HdlTypeDef *hsd);
-static u32 SD_IRQHandler(void *pData);
 
 static u8 is_timeout(u32 start_us, u32 timeout_us)
 {
@@ -128,7 +127,7 @@ static void SDIOH_Pinmux(void)
 	}
 }
 
-static void SD_PreDMATrans(SD_HdlTypeDef *hsd)
+void SD_PreDMATrans(SD_HdlTypeDef *hsd)
 {
 	if ((CPU_InInterrupt() == 0) && (rtos_sched_get_state() == RTOS_SCHED_RUNNING) && (sd_sema_take_fn != NULL)) {
 		wait_for_sema = 1;
@@ -274,7 +273,7 @@ SD_RESULT SD_Init(void)
 
 		/* Wait until func1 is ready */
 		while (1) {
-			ret = SD_IO_RW_Direct(hsd, BUS_READ, SDIO_FUNC0, SDIOD_CCCR_IORDY, NULL, &val);
+			ret = SD_IO_RW_Direct(hsd, BUS_READ, SDIO_FUNC0, SDIOD_CCCR_IORDY, (u8)0x0, &val);
 			if (ret != SD_OK) {
 				return SD_ERROR;
 			}
@@ -470,10 +469,12 @@ static SD_RESULT SD_InitCard(SD_HdlTypeDef *hsd)
 
 	/* Send CMD3 SET_REL_ADDR with argument 0 */
 	/* CMD3: SD Card publishes its RCA. */
-	errorstate = SDMMC_CmdSetRelAdd(SDIOx, &sd_rca);
+	errorstate = SDMMC_CmdSetRelAdd(SDIOx);
 	if (errorstate != SD_ERROR_NONE) {
 		hsd->ErrorCode |= errorstate;
 		return SD_ERROR;
+	} else {
+		sd_rca = SDIO_GetResponse(SDIOx, SDIO_RESP0) >> 16;
 	}
 
 	/* Get the SD card RCA */
@@ -1733,7 +1734,7 @@ __weak void SD_IRQ_NOTIFY(void)
  * @param  hsd: Pointer to SD handle
  * @retval None
  */
-static u32 SD_IRQHandler(void *pData)
+u32 SD_IRQHandler(void *pData)
 {
 	SD_HdlTypeDef *hsd = (SD_HdlTypeDef *)pData;
 	SDIOHOST_TypeDef *SDIOx = hsd->Instance;
@@ -2106,7 +2107,7 @@ static SD_RESULT SD_SendSDStatus(SD_HdlTypeDef *hsd, u32 *pSDstatus)
 	/* Configure the SD DPSM (Data Path State Machine) */
 	config.TransType = SDIO_TRANS_SINGLE_BLK;
 	config.TransDir = SDIO_TRANS_CARD_TO_HOST;
-	config.BlockSize = 512U;
+	config.BlockSize = 64U; // 512bit/8
 	config.BlockCnt = 1U; // DON'T CARE
 	config.AutoCmdEn = SDIO_TRANS_AUTO_DIS;
 	config.DmaEn = SDIO_TRANS_DMA_DIS;
@@ -2319,7 +2320,7 @@ SD_RESULT SD_ConfigBusSpeed(SD_HdlTypeDef *hsd, u8 BusSpeed)
 
 	if (BusSpeed == SD_SPEED_HS) {
 		if (hsd->Card.CardType == CARD_SDIO_ONLY) {
-			ret = SD_IO_RW_Direct(hsd, BUS_READ, SDIO_FUNC0, SDIOD_CCCR_SPEED_CONTROL, NULL, &val);
+			ret = SD_IO_RW_Direct(hsd, BUS_READ, SDIO_FUNC0, SDIOD_CCCR_SPEED_CONTROL, (u8)0x0, &val);
 			if (ret != SD_OK) {
 				return ret;
 			}
@@ -2348,7 +2349,7 @@ SD_RESULT SD_ConfigBusSpeed(SD_HdlTypeDef *hsd, u8 BusSpeed)
 		}
 	} else if (BusSpeed == SD_SPEED_DS) {
 		if (hsd->Card.CardType == CARD_SDIO_ONLY) {
-			ret = SD_IO_RW_Direct(hsd, BUS_WRITE, SDIO_FUNC0, SDIOD_CCCR_SPEED_CONTROL, 0x0, &val);
+			ret = SD_IO_RW_Direct(hsd, BUS_WRITE, SDIO_FUNC0, SDIOD_CCCR_SPEED_CONTROL, (u8)0x0, &val);
 			if (ret != SD_OK) {
 				return ret;
 			}
@@ -2453,7 +2454,7 @@ static u32 SD_WideBus_Enable(SD_HdlTypeDef *hsd)
 
 	if (hsd->Card.CardType == CARD_SDIO_ONLY) {
 
-		ret = SD_IO_RW_Direct(hsd, BUS_READ, SDIO_FUNC0, SDIOD_CCCR_BICTRL, NULL, &val);
+		ret = SD_IO_RW_Direct(hsd, BUS_READ, SDIO_FUNC0, SDIOD_CCCR_BICTRL, (u8)0x0, &val);
 		if (ret != SD_OK) {
 			return SD_ERROR;
 		}
@@ -2506,7 +2507,7 @@ static u32 SD_WideBus_Disable(SD_HdlTypeDef *hsd)
 
 	if (hsd->Card.CardType == CARD_SDIO_ONLY) {
 
-		ret = SD_IO_RW_Direct(hsd, BUS_READ, SDIO_FUNC0, SDIOD_CCCR_BICTRL, NULL, &val);
+		ret = SD_IO_RW_Direct(hsd, BUS_READ, SDIO_FUNC0, SDIOD_CCCR_BICTRL, (u8)0x0, &val);
 		if (ret != SD_OK) {
 			return SD_ERROR;
 		}
@@ -2550,10 +2551,8 @@ static u32 SD_GetCardSCR(SD_HdlTypeDef *hsd)
 	SDIOHOST_TypeDef *SDIOx = hsd->Instance;
 	SDIO_DataInitTypeDef config;
 	u32 errorstate;
-	u32 tickstart = DTimestamp_Get();
-	u32 index = 0U;
-	u32 tempscr[2U] = {0U, 0U};
-	u32 dataremaining;
+	/* 32byte for cache operation, only the first 2bytes are valid */
+	u32 tempscr[8]__attribute__((aligned(32))) = {0U};
 
 	// avoid crc_err_sts is set during ACMD51
 	SDIO_ConfigErrIntSts(SDIOx, SDIOHOST_BIT_DATA_CRC_ERR_STATUS_EN, DISABLE);
@@ -2569,35 +2568,30 @@ static u32 SD_GetCardSCR(SD_HdlTypeDef *hsd)
 	config.BlockSize = 8U; // 64bit/8
 	config.BlockCnt = 0U; // DON'T CARE when TRANS_SINGLE_BLK
 	config.AutoCmdEn = SDIO_TRANS_AUTO_DIS;
-	config.DmaEn = SDIO_TRANS_DMA_DIS;
+	config.DmaEn = SDIO_TRANS_DMA_EN;
 	SDIO_ConfigData(SDIOx, &config);
 
+	errorstate = SDIO_ConfigDMA(SDIOx, SDIO_SDMA_MODE, (u32)tempscr);
+	if (errorstate != HAL_OK) {
+		hsd->ErrorCode |= SD_ERROR_INVALID_PARAMETER;
+		hsd->State = SD_STATE_READY;
+		return SD_ERROR;
+	}
+	SD_PreDMATrans(hsd);
+
 	/* Send ACMD51 SD_APP_SEND_SCR with argument as 0 */
 	errorstate = SDMMC_CmdSendSCR(SDIOx);
 	if (errorstate != SD_ERROR_NONE) {
 		return errorstate;
 	}
 
-	dataremaining = 8U; // size of SCR: 8Bytes
-
-	/* SDIOHOST_BIT_XFER_COMPLETE will not be set under this case */
-	while (!((SDIO_GetErrSts(SDIOx) & SDIO_DAT_ERR))) {
-
-		if (dataremaining  == 0U) {
-			break;
-		}
-
-		if ((SDIO_GetStatus(SDIOx) & SDIOHOST_BIT_BUFF_READ_EN) && (dataremaining > 0U)) {
-			*(tempscr + index) = SDIO_ReadFIFO(SDIOx);
-			index++;
-			dataremaining -= 4U;
-		}
-
-		if (is_timeout(tickstart, SDMMC_DAT_TIMEOUT)) {
-			return SD_ERROR_TIMEOUT;
-		}
+	if (SD_WaitTransDone(hsd, SDMMC_DAT_TIMEOUT) != HAL_OK) {
+		RTK_LOGE(TAG, "%s WaitTransDone error!\n", __FUNCTION__);
+		return SD_ERROR;
 	}
 
+	DCache_Invalidate((u32)tempscr, sizeof(tempscr));
+
 	if (SDIO_GetErrSts(SDIOx) & SDIOHOST_BIT_DATA_TIMEOUT_ERR) {
 		SDIO_ClearErrSts(SDIOx, SDIOHOST_BIT_DATA_TIMEOUT_ERR);
 		return SD_ERROR_DATA_TIMEOUT;
diff --git a/ameba/amebaG2/source/fwlib/ram_common/ameba_sd_host.c b/ameba/amebag2/source/fwlib/ram_common/ameba_sd_host.c
similarity index 70%
rename from ameba/amebaG2/source/fwlib/ram_common/ameba_sd_host.c
rename to ameba/amebag2/source/fwlib/ram_common/ameba_sd_host.c
index da852047..3564fa55 100644
--- a/ameba/amebaG2/source/fwlib/ram_common/ameba_sd_host.c
+++ b/ameba/amebag2/source/fwlib/ram_common/ameba_sd_host.c
@@ -476,7 +476,7 @@ u32 SDIO_CmdSendOpCond(SDIOHOST_TypeDef *SDIOx, u32 Ocr)
 	SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
 
 	/* Check for error conditions */
-	errorstate = SDMMC_GetCmdResp4(SDIOx);
+	errorstate = SDIO_WaitResp(SDIOx, sdmmc_cmdinit.RespType, SDMMC_CMD_TIMEOUT);
 
 	return errorstate;
 }
@@ -494,7 +494,7 @@ u32 SDIO_CmdRWDirect(SDIOHOST_TypeDef *SDIOx, u32 Argument)
 	SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
 
 	/* Check for error conditions */
-	errorstate = SDMMC_GetCmdResp5(SDIOx);
+	errorstate = SDIO_WaitResp(SDIOx, sdmmc_cmdinit.RespType, SDMMC_CMD_TIMEOUT);
 
 	return errorstate;
 }
@@ -512,7 +512,7 @@ u32 SDIO_CmdRWExtended(SDIOHOST_TypeDef *SDIOx, u32 Argument)
 	SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
 
 	/* Check for error conditions */
-	errorstate = SDMMC_GetCmdResp5(SDIOx);
+	errorstate = SDIO_WaitResp(SDIOx, sdmmc_cmdinit.RespType, SDMMC_CMD_TIMEOUT);
 
 	return errorstate;
 }
@@ -665,7 +665,7 @@ u32 SDMMC_CmdBlockLength(SDIOHOST_TypeDef *SDIOx, u32 BlockSize)
 	SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
 
 	/* Check for error conditions */
-	errorstate = SDMMC_GetCmdResp1(SDIOx);
+	errorstate = SDIO_WaitResp(SDIOx, sdmmc_cmdinit.RespType, SDMMC_CMD_TIMEOUT);
 
 	return errorstate;
 }
@@ -689,7 +689,7 @@ u32 SDMMC_CmdReadSingleBlock(SDIOHOST_TypeDef *SDIOx, u32 ReadAdd)
 	SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
 
 	/* Check for error conditions */
-	errorstate = SDMMC_GetCmdResp1(SDIOx);
+	errorstate = SDIO_WaitResp(SDIOx, sdmmc_cmdinit.RespType, SDMMC_CMD_TIMEOUT);
 
 	return errorstate;
 }
@@ -713,7 +713,7 @@ u32 SDMMC_CmdReadMultiBlock(SDIOHOST_TypeDef *SDIOx, u32 ReadAdd)
 	SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
 
 	/* Check for error conditions */
-	errorstate = SDMMC_GetCmdResp1(SDIOx);
+	errorstate = SDIO_WaitResp(SDIOx, sdmmc_cmdinit.RespType, SDMMC_CMD_TIMEOUT);
 
 	return errorstate;
 }
@@ -737,7 +737,7 @@ u32 SDMMC_CmdWriteSingleBlock(SDIOHOST_TypeDef *SDIOx, u32 WriteAdd)
 	SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
 
 	/* Check for error conditions */
-	errorstate = SDMMC_GetCmdResp1(SDIOx);
+	errorstate = SDIO_WaitResp(SDIOx, sdmmc_cmdinit.RespType, SDMMC_CMD_TIMEOUT);
 
 	return errorstate;
 }
@@ -761,7 +761,7 @@ u32 SDMMC_CmdWriteMultiBlock(SDIOHOST_TypeDef *SDIOx, u32 WriteAdd)
 	SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
 
 	/* Check for error conditions */
-	errorstate = SDMMC_GetCmdResp1(SDIOx);
+	errorstate = SDIO_WaitResp(SDIOx, sdmmc_cmdinit.RespType, SDMMC_CMD_TIMEOUT);
 
 	return errorstate;
 }
@@ -785,7 +785,7 @@ u32 SDMMC_CmdSDEraseStartAdd(SDIOHOST_TypeDef *SDIOx, u32 StartAdd)
 	SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
 
 	/* Check for error conditions */
-	errorstate = SDMMC_GetCmdResp1(SDIOx);
+	errorstate = SDIO_WaitResp(SDIOx, sdmmc_cmdinit.RespType, SDMMC_CMD_TIMEOUT);
 
 	return errorstate;
 }
@@ -809,7 +809,7 @@ u32 SDMMC_CmdSDEraseEndAdd(SDIOHOST_TypeDef *SDIOx, u32 EndAdd)
 	SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
 
 	/* Check for error conditions */
-	errorstate = SDMMC_GetCmdResp1(SDIOx);
+	errorstate = SDIO_WaitResp(SDIOx, sdmmc_cmdinit.RespType, SDMMC_CMD_TIMEOUT);
 
 	return errorstate;
 }
@@ -834,7 +834,7 @@ u32 SDMMC_CmdErase(SDIOHOST_TypeDef *SDIOx, u32 BlockCnt)
 	SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
 
 	/* Check for error conditions */
-	errorstate = SDMMC_GetCmdResp1B(SDIOx, SDMMC_ERASE_TIMEOUT * BlockCnt);
+	errorstate = SDIO_WaitResp(SDIOx, sdmmc_cmdinit.RespType, SDMMC_ERASE_TIMEOUT * BlockCnt);
 
 	return errorstate;
 }
@@ -858,7 +858,7 @@ u32 SDMMC_CmdStopTransfer(SDIOHOST_TypeDef *SDIOx)
 	SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
 
 	/* Check for error conditions */
-	errorstate = SDMMC_GetCmdResp1B(SDIOx, SDMMC_STOP_TRANS_TIMEOUT);
+	errorstate = SDIO_WaitResp(SDIOx, sdmmc_cmdinit.RespType, SDMMC_STOP_TRANS_TIMEOUT);
 
 	return errorstate;
 }
@@ -888,11 +888,7 @@ u32 SDMMC_CmdSelDesel(SDIOHOST_TypeDef *SDIOx, u32 Addr)
 	SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
 
 	/* Check for error conditions */
-	if (Addr != 0x0) {
-		errorstate = SDMMC_GetCmdResp1B(SDIOx, SDMMC_DAT_TIMEOUT);
-	} else {
-		errorstate = SDMMC_GetCmdResp1(SDIOx);
-	}
+	errorstate = SDIO_WaitResp(SDIOx, sdmmc_cmdinit.RespType, SDMMC_DAT_TIMEOUT);
 
 	return errorstate;
 }
@@ -915,7 +911,7 @@ u32 SDMMC_CmdGoIdleState(SDIOHOST_TypeDef *SDIOx)
 	SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
 
 	/* Check for error conditions */
-	errorstate = SDMMC_GetCmdError(SDIOx);
+	errorstate = SDIO_WaitResp(SDIOx, sdmmc_cmdinit.RespType, SDMMC_CMD_TIMEOUT);
 
 	return errorstate;
 }
@@ -943,7 +939,7 @@ u32 SDMMC_CmdOperCond(SDIOHOST_TypeDef *SDIOx)
 	SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
 
 	/* Check for error conditions */
-	errorstate = SDMMC_GetCmdResp7(SDIOx); // R7
+	errorstate = SDIO_WaitResp(SDIOx, sdmmc_cmdinit.RespType, SDMMC_CMD_TIMEOUT);
 
 	return errorstate;
 }
@@ -972,7 +968,7 @@ u32 SDMMC_CmdAppCommand(SDIOHOST_TypeDef *SDIOx, u32 Argument)
 	/* If there is a HAL_ERR_PARA, it is a MMC card, else
 	it is a SD card: SD card 2.0 (voltage range mismatch)
 	   or SD card 1.x */
-	errorstate = SDMMC_GetCmdResp1(SDIOx);
+	errorstate = SDIO_WaitResp(SDIOx, sdmmc_cmdinit.RespType, SDMMC_CMD_TIMEOUT);
 
 	return errorstate;
 }
@@ -989,7 +985,7 @@ u32 SDMMC_CmdAppOperCommand(SDIOHOST_TypeDef *SDIOx, u32 Argument)
 	SDIO_CmdInitTypeDef sdmmc_cmdinit;
 	u32 errorstate;
 
-	sdmmc_cmdinit.Argument = SDMMC_VOLTAGE_WINDOW_SD | Argument;
+	sdmmc_cmdinit.Argument = Argument;
 	sdmmc_cmdinit.CmdIndex = SDMMC_APP_OP_COND; // ACMD41(CMD55 + CMD41)
 	sdmmc_cmdinit.CmdType = SDMMC_CMD_NORMAL;
 	sdmmc_cmdinit.RespType = SDMMC_RSP_R3;
@@ -997,7 +993,7 @@ u32 SDMMC_CmdAppOperCommand(SDIOHOST_TypeDef *SDIOx, u32 Argument)
 	SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
 
 	/* Check for error conditions */
-	errorstate = SDMMC_GetCmdResp3(SDIOx);
+	errorstate = SDIO_WaitResp(SDIOx, sdmmc_cmdinit.RespType, SDMMC_CMD_TIMEOUT);
 
 	return errorstate;
 }
@@ -1021,7 +1017,7 @@ u32 SDMMC_CmdBusWidth(SDIOHOST_TypeDef *SDIOx, u32 BusWidth)
 	SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
 
 	/* Check for error conditions */
-	errorstate = SDMMC_GetCmdResp1(SDIOx);
+	errorstate = SDIO_WaitResp(SDIOx, sdmmc_cmdinit.RespType, SDMMC_CMD_TIMEOUT);
 
 	return errorstate;
 }
@@ -1045,7 +1041,7 @@ u32 SDMMC_CmdSetWrBlkEraseCnt(SDIOHOST_TypeDef *SDIOx, u32 BlockCnt)
 	SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
 
 	/* Check for error conditions */
-	errorstate = SDMMC_GetCmdResp1(SDIOx);
+	errorstate = SDIO_WaitResp(SDIOx, sdmmc_cmdinit.RespType, SDMMC_CMD_TIMEOUT);
 
 	return errorstate;
 }
@@ -1069,7 +1065,7 @@ u32 SDMMC_CmdSendSCR(SDIOHOST_TypeDef *SDIOx)
 	SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
 
 	/* Check for error conditions */
-	errorstate = SDMMC_GetCmdResp1(SDIOx);
+	errorstate = SDIO_WaitResp(SDIOx, sdmmc_cmdinit.RespType, SDMMC_CMD_TIMEOUT);
 
 	return errorstate;
 }
@@ -1093,7 +1089,7 @@ u32 SDMMC_CmdSendCID(SDIOHOST_TypeDef *SDIOx)
 	SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
 
 	/* Check for error conditions */
-	errorstate = SDMMC_GetCmdResp2(SDIOx);
+	errorstate = SDIO_WaitResp(SDIOx, sdmmc_cmdinit.RespType, SDMMC_CMD_TIMEOUT);
 
 	return errorstate;
 }
@@ -1118,7 +1114,7 @@ u32 SDMMC_CmdSendCSD(SDIOHOST_TypeDef *SDIOx, u32 Argument)
 	SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
 
 	/* Check for error conditions */
-	errorstate = SDMMC_GetCmdResp2(SDIOx);
+	errorstate = SDIO_WaitResp(SDIOx, sdmmc_cmdinit.RespType, SDMMC_CMD_TIMEOUT);
 
 	return errorstate;
 }
@@ -1129,7 +1125,7 @@ u32 SDMMC_CmdSendCSD(SDIOHOST_TypeDef *SDIOx, u32 Argument)
  * @param  pRCA: Card RCA
  * @retval HAL status
  */
-u32 SDMMC_CmdSetRelAdd(SDIOHOST_TypeDef *SDIOx, u16 *pRCA)
+u32 SDMMC_CmdSetRelAdd(SDIOHOST_TypeDef *SDIOx)
 {
 	SDIO_CmdInitTypeDef sdmmc_cmdinit;
 	u32 errorstate;
@@ -1143,7 +1139,7 @@ u32 SDMMC_CmdSetRelAdd(SDIOHOST_TypeDef *SDIOx, u16 *pRCA)
 	SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
 
 	/* Check for error conditions */
-	errorstate = SDMMC_GetCmdResp6(SDIOx, pRCA);
+	errorstate = SDIO_WaitResp(SDIOx, sdmmc_cmdinit.RespType, SDMMC_CMD_TIMEOUT);
 
 	return errorstate;
 }
@@ -1167,7 +1163,7 @@ u32 SDMMC_CmdSendStatus(SDIOHOST_TypeDef *SDIOx, u32 Argument)
 	SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
 
 	/* Check for error conditions */
-	errorstate = SDMMC_GetCmdResp1(SDIOx);
+	errorstate = SDIO_WaitResp(SDIOx, sdmmc_cmdinit.RespType, SDMMC_CMD_TIMEOUT);
 
 	return errorstate;
 }
@@ -1190,7 +1186,7 @@ u32 SDMMC_CmdStatusRegister(SDIOHOST_TypeDef *SDIOx)
 	SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
 
 	/* Check for error conditions */
-	errorstate = SDMMC_GetCmdResp1(SDIOx);
+	errorstate = SDIO_WaitResp(SDIOx, sdmmc_cmdinit.RespType, SDMMC_CMD_TIMEOUT);
 
 	return errorstate;
 }
@@ -1217,213 +1213,194 @@ u32 SDMMC_CmdSwitch(SDIOHOST_TypeDef *SDIOx, u32 Argument)
 	SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
 
 	/* Check for error conditions */
-	errorstate = SDMMC_GetCmdResp1(SDIOx);
+	errorstate = SDIO_WaitResp(SDIOx, sdmmc_cmdinit.RespType, SDMMC_CMD_TIMEOUT);
 
 	return errorstate;
 }
 
 /**
- * @brief  Checks for error conditions for CMD0.
+ * @brief  Checks for error conditions after sending CMD.
  * @param  SDIOx Pointer to SDIO host
+ * @param  RespType Response type, which can be a value of @ref SDIO_LL_Response_Type.
+ * @param  TimeOutUs Timeout value in us.
  * @retval SD Card error state
  */
-u32 SDMMC_GetCmdError(SDIOHOST_TypeDef *SDIOx)
+u32 SDIO_WaitResp(SDIOHOST_TypeDef *SDIOx, u8 RespType, u32 TimeOutUs)
 {
+	u32 response_r0;
 	u32 count = 0;
+	u32 norm_int, err_int;
 
-	while (!(SDIO_GetNormSts(SDIOx) & SDIOHOST_BIT_CMD_COMPLETE)) {
-		if (count++ >= SDMMC_CMD_TIMEOUT) {
-			RTK_LOGE(TAG, "%s timeout\n", __FUNCTION__);
-			return SD_ERROR_TIMEOUT;
-		}
-
-		/* exit while-loop ASAP */
-		DelayUs(1);
-	}
-
-	SDIO_ClearNormSts(SDIOx, SDIOHOST_BIT_CMD_COMPLETE);
+	assert_param(IS_SD_RESP_TYPE(RespType));
 
-	return SD_ERROR_NONE;
-}
+	switch (RespType) {
+	case SDMMC_RSP_R1:
+	case SDMMC_RSP_R2:
+	case SDMMC_RSP_R3:
+	case SDMMC_RSP_R4:
+	case SDMMC_RSP_R5:
+	case SDMMC_RSP_R6:
+	case SDMMC_RSP_R7:
+		while (1) {
+			norm_int = SDIO_GetNormSts(SDIOx);
+			err_int = SDIO_GetErrSts(SDIOx);
 
-/**
- * @brief  Checks for error conditions for R1 response.
- * @param  SDIOx Pointer to SDIO host
- * @retval SD Card error state
- */
-u32 SDMMC_GetCmdResp1(SDIOHOST_TypeDef *SDIOx)
-{
-	u32 response_r0;
-	u32 count = 0;
-	u32 norm_int, err_int;
+			if ((norm_int & SDIOHOST_BIT_CMD_COMPLETE) || (err_int & SDIO_CMD_ERR)) {
+				break;
+			}
 
-	while (1) {
-		norm_int = SDIO_GetNormSts(SDIOx);
-		err_int = SDIO_GetErrSts(SDIOx);
+			if (count++ >= TimeOutUs) {
+				RTK_LOGE(TAG, "%s timeout\n", __FUNCTION__);
+				return SD_ERROR_TIMEOUT;
+			}
 
-		if ((norm_int & SDIOHOST_BIT_CMD_COMPLETE) || (err_int & SDIO_CMD_ERR)) {
-			break;
+			/* exit while-loop ASAP */
+			DelayUs(1);
 		}
 
-		if (count++ >= SDMMC_CMD_TIMEOUT) {
-			RTK_LOGE(TAG, "%s timeout\n", __FUNCTION__);
-			return SD_ERROR_TIMEOUT;
+		if (norm_int & SDIOHOST_BIT_CMD_COMPLETE) {
+			SDIO_ClearNormSts(SDIOx, SDIOHOST_BIT_CMD_COMPLETE);
 		}
 
-		/* exit while-loop ASAP */
-		DelayUs(1);
-	}
-
-	if (norm_int & SDIOHOST_BIT_CMD_COMPLETE) {
-		SDIO_ClearNormSts(SDIOx, SDIOHOST_BIT_CMD_COMPLETE);
-	}
+		if (err_int & SDIO_CMD_ERR) {
+			if (RespType == SDMMC_RSP_R7) {
+				DelayUs(10); // avoid cmd_err sts is set again after clear
+			}
+			SDIO_ClearErrSts(SDIOx, SDIO_CMD_ERR);
+			if (err_int & SDIOHOST_BIT_CMD_TIMEOUT_ERR) {
+				return SD_ERROR_CMD_RSP_TIMEOUT;
+			} else {
+				return SD_ERROR_GENERAL_UNKNOWN_ERR;
+			}
+		}
 
-	if (err_int & SDIO_CMD_ERR) {
-		SDIO_ClearErrSts(SDIOx, SDIO_CMD_ERR);
-		if (err_int & SDIOHOST_BIT_CMD_TIMEOUT_ERR) {
-			return SD_ERROR_CMD_RSP_TIMEOUT;
+		if (RespType == SDMMC_RSP_R2 || RespType == SDMMC_RSP_R3 || RespType == SDMMC_RSP_R4 || RespType == SDMMC_RSP_R7) {
+			return SD_ERROR_NONE;
 		} else {
-			return SD_ERROR_GENERAL_UNKNOWN_ERR;
+			response_r0 = SDIO_GetResponse(SDIOx, SDIO_RESP0);
+			if (RespType == SDMMC_RSP_R1) {
+				return SDMMC_CheckErrResp1(response_r0);
+			} else if (RespType == SDMMC_RSP_R5) {
+				return SDMMC_CheckErrResp5(response_r0);
+			} else if (RespType == SDMMC_RSP_R6) {
+				return SDMMC_CheckErrResp6(response_r0);
+			}
 		}
-	}
-
-	/* We have received response, retrieve it for analysis  */
-	response_r0 = SDIO_GetResponse(SDIOx, SDIO_RESP0);
+		break;
+	case SDMMC_RSP_R1B:
+	case SDMMC_RSP_R5B:
+		while (1) {
+			norm_int = SDIO_GetNormSts(SDIOx);
+			err_int = SDIO_GetErrSts(SDIOx);
 
-	if ((response_r0 & SDMMC_R1_ERRORBITS) == SDMMC_ALLZERO) {
-		return SD_ERROR_NONE;
-	} else if ((response_r0 & SDMMC_R1_ADDR_OUT_OF_RANGE) == SDMMC_R1_ADDR_OUT_OF_RANGE) {
-		return SD_ERROR_ADDR_OUT_OF_RANGE;
-	} else if ((response_r0 & SDMMC_R1_ADDR_MISALIGNED) == SDMMC_R1_ADDR_MISALIGNED) {
-		return SD_ERROR_ADDR_MISALIGNED;
-	} else if ((response_r0 & SDMMC_R1_BLOCK_LEN_ERR) == SDMMC_R1_BLOCK_LEN_ERR) {
-		return SD_ERROR_BLOCK_LEN_ERR;
-	} else if ((response_r0 & SDMMC_R1_ERASE_SEQ_ERR) == SDMMC_R1_ERASE_SEQ_ERR) {
-		return SD_ERROR_ERASE_SEQ_ERR;
-	} else if ((response_r0 & SDMMC_R1_BAD_ERASE_PARAM) == SDMMC_R1_BAD_ERASE_PARAM) {
-		return SD_ERROR_BAD_ERASE_PARAM;
-	} else if ((response_r0 & SDMMC_R1_WRITE_PROT_VIOLATION) == SDMMC_R1_WRITE_PROT_VIOLATION) {
-		return SD_ERROR_WRITE_PROT_VIOLATION;
-	} else if ((response_r0 & SDMMC_R1_LOCK_UNLOCK_FAILED) == SDMMC_R1_LOCK_UNLOCK_FAILED) {
-		return SD_ERROR_LOCK_UNLOCK_FAILED;
-	} else if ((response_r0 & SDMMC_R1_COM_CRC_FAILED) == SDMMC_R1_COM_CRC_FAILED) {
-		return SD_ERROR_COM_CRC_FAILED;
-	} else if ((response_r0 & SDMMC_R1_ILLEGAL_CMD) == SDMMC_R1_ILLEGAL_CMD) {
-		return SD_ERROR_ILLEGAL_CMD;
-	} else if ((response_r0 & SDMMC_R1_CARD_ECC_FAILED) == SDMMC_R1_CARD_ECC_FAILED) {
-		return SD_ERROR_CARD_ECC_FAILED;
-	} else if ((response_r0 & SDMMC_R1_CC_ERROR) == SDMMC_R1_CC_ERROR) {
-		return SD_ERROR_CC_ERR;
-	} else if ((response_r0 & SDMMC_R1_STREAM_READ_UNDERRUN) == SDMMC_R1_STREAM_READ_UNDERRUN) {
-		return SD_ERROR_STREAM_READ_UNDERRUN;
-	} else if ((response_r0 & SDMMC_R1_STREAM_WRITE_OVERRUN) == SDMMC_R1_STREAM_WRITE_OVERRUN) {
-		return SD_ERROR_STREAM_WRITE_OVERRUN;
-	} else if ((response_r0 & SDMMC_R1_CID_CSDMMC_OVERWRITE) == SDMMC_R1_CID_CSDMMC_OVERWRITE) {
-		return SD_ERROR_CID_CSDMMC_OVERWRITE;
-	} else if ((response_r0 & SDMMC_R1_WP_ERASE_SKIP) == SDMMC_R1_WP_ERASE_SKIP) {
-		return SD_ERROR_WP_ERASE_SKIP;
-	} else if ((response_r0 & SDMMC_R1_CARD_ECC_DISABLED) == SDMMC_R1_CARD_ECC_DISABLED) {
-		return SD_ERROR_CARD_ECC_DISABLED;
-	} else if ((response_r0 & SDMMC_R1_ERASE_RESET) == SDMMC_R1_ERASE_RESET) {
-		return SD_ERROR_ERASE_RESET;
-	} else if ((response_r0 & SDMMC_R1_AKE_SEQ_ERROR) == SDMMC_R1_AKE_SEQ_ERROR) {
-		return SD_ERROR_AKE_SEQ_ERR;
-	} else {
-		return SD_ERROR_GENERAL_UNKNOWN_ERR;
-	}
-}
+			if ((norm_int & SDIOHOST_BIT_XFER_COMPLETE) || (err_int & (SDIO_CMD_ERR | SDIOHOST_BIT_DATA_TIMEOUT_ERR))) {
+				break;
+			}
 
-/**
- * @brief  Checks for error conditions for R1 response.
- * @param  SDIOx Pointer to SDIO host
- * @param  Timeout: Timeout value in us.
- * @retval SD Card error state
- */
-u32 SDMMC_GetCmdResp1B(SDIOHOST_TypeDef *SDIOx, u32 Timeout)
-{
-	u32 response_r0;
-	u32 count = 0;
-	u32 norm_int, err_int;
+			if (count++ >= TimeOutUs) {
+				RTK_LOGE(TAG, "%s timeout\n", __FUNCTION__);
+				return SD_ERROR_TIMEOUT;
+			}
 
-	while (1) {
-		norm_int = SDIO_GetNormSts(SDIOx);
-		err_int = SDIO_GetErrSts(SDIOx);
+			/* exit while-loop ASAP */
+			DelayUs(1);
+		}
 
-		if ((norm_int & SDIOHOST_BIT_XFER_COMPLETE) || (err_int & (SDIO_CMD_ERR | SDIOHOST_BIT_DATA_TIMEOUT_ERR))) {
-			break;
+		if (norm_int & SDIOHOST_BIT_CMD_COMPLETE) {
+			SDIO_ClearNormSts(SDIOx, SDIOHOST_BIT_CMD_COMPLETE);
 		}
 
-		if (count++ >= Timeout) {
-			RTK_LOGE(TAG, "%s timeout\n", __FUNCTION__);
-			return SD_ERROR_TIMEOUT;
+		if (norm_int & SDIOHOST_BIT_XFER_COMPLETE) {
+			SDIO_ClearNormSts(SDIOx, SDIOHOST_BIT_XFER_COMPLETE);
 		}
 
-		/* exit while-loop ASAP */
-		DelayUs(1);
-	}
+		if (!(norm_int & SDIOHOST_BIT_XFER_COMPLETE) && (err_int & SDIOHOST_BIT_DATA_TIMEOUT_ERR)) {
+			RTK_LOGE(TAG, "%s busy\n", __FUNCTION__);
+			return SD_ERROR_BUSY;
+		}
 
-	if (norm_int & SDIOHOST_BIT_CMD_COMPLETE) {
-		SDIO_ClearNormSts(SDIOx, SDIOHOST_BIT_CMD_COMPLETE);
-	}
+		if (err_int & SDIO_CMD_ERR) {
+			SDIO_ClearErrSts(SDIOx, SDIO_CMD_ERR);
+			if (err_int & SDIOHOST_BIT_CMD_TIMEOUT_ERR) {
+				return SD_ERROR_CMD_RSP_TIMEOUT;
+			} else {
+				return SD_ERROR_GENERAL_UNKNOWN_ERR;
+			}
+		}
 
-	if (norm_int & SDIOHOST_BIT_XFER_COMPLETE) {
-		SDIO_ClearNormSts(SDIOx, SDIOHOST_BIT_XFER_COMPLETE);
-	}
+		response_r0 = SDIO_GetResponse(SDIOx, SDIO_RESP0);
+		if (RespType == SDMMC_RSP_R1B) {
+			return SDMMC_CheckErrResp1(response_r0);
+		} else if (RespType == SDMMC_RSP_R5B) {
+			return SDMMC_CheckErrResp5(response_r0);
+		}
+		break;
+	case SDMMC_RSP_NONE:
+		while (!(SDIO_GetNormSts(SDIOx) & SDIOHOST_BIT_CMD_COMPLETE)) {
+			if (count++ >= TimeOutUs) {
+				RTK_LOGE(TAG, "%s timeout\n", __FUNCTION__);
+				return SD_ERROR_TIMEOUT;
+			}
+
+			/* exit while-loop ASAP */
+			DelayUs(1);
+		}
 
-	if (!(norm_int & SDIOHOST_BIT_XFER_COMPLETE) && (err_int & SDIOHOST_BIT_DATA_TIMEOUT_ERR)) {
-		RTK_LOGE(TAG, "%s busy\n", __FUNCTION__);
-		return SD_ERROR_BUSY;
-	}
+		SDIO_ClearNormSts(SDIOx, SDIOHOST_BIT_CMD_COMPLETE);
 
-	if (err_int & SDIO_CMD_ERR) {
-		SDIO_ClearErrSts(SDIOx, SDIO_CMD_ERR);
-		if (err_int & SDIOHOST_BIT_CMD_TIMEOUT_ERR) {
-			return SD_ERROR_CMD_RSP_TIMEOUT;
-		} else {
-			return SD_ERROR_GENERAL_UNKNOWN_ERR;
-		}
+		return SD_ERROR_NONE;
+		break;
+	default:
+		RTK_LOGE(TAG, "%s: Invalid response type!!!\n", __FUNCTION__);
 	}
 
-	/* We have received response, retrieve it for analysis  */
-	response_r0 = SDIO_GetResponse(SDIOx, SDIO_RESP0);
+	return SD_ERROR_GENERAL_UNKNOWN_ERR;
+}
 
-	if ((response_r0 & SDMMC_R1_ERRORBITS) == SDMMC_ALLZERO) {
+/**
+ * @brief  Checks for error conditions for R1 response.
+ * @param  resp R1 Response of CMD.
+ * @retval SD Card error state.
+ */
+u32 SDMMC_CheckErrResp1(u32 resp)
+{
+	if ((resp & SDMMC_R1_ERRORBITS) == SDMMC_ALLZERO) {
 		return SD_ERROR_NONE;
-	} else if ((response_r0 & SDMMC_R1_ADDR_OUT_OF_RANGE) == SDMMC_R1_ADDR_OUT_OF_RANGE) {
+	} else if ((resp & SDMMC_R1_ADDR_OUT_OF_RANGE) == SDMMC_R1_ADDR_OUT_OF_RANGE) {
 		return SD_ERROR_ADDR_OUT_OF_RANGE;
-	} else if ((response_r0 & SDMMC_R1_ADDR_MISALIGNED) == SDMMC_R1_ADDR_MISALIGNED) {
+	} else if ((resp & SDMMC_R1_ADDR_MISALIGNED) == SDMMC_R1_ADDR_MISALIGNED) {
 		return SD_ERROR_ADDR_MISALIGNED;
-	} else if ((response_r0 & SDMMC_R1_BLOCK_LEN_ERR) == SDMMC_R1_BLOCK_LEN_ERR) {
+	} else if ((resp & SDMMC_R1_BLOCK_LEN_ERR) == SDMMC_R1_BLOCK_LEN_ERR) {
 		return SD_ERROR_BLOCK_LEN_ERR;
-	} else if ((response_r0 & SDMMC_R1_ERASE_SEQ_ERR) == SDMMC_R1_ERASE_SEQ_ERR) {
+	} else if ((resp & SDMMC_R1_ERASE_SEQ_ERR) == SDMMC_R1_ERASE_SEQ_ERR) {
 		return SD_ERROR_ERASE_SEQ_ERR;
-	} else if ((response_r0 & SDMMC_R1_BAD_ERASE_PARAM) == SDMMC_R1_BAD_ERASE_PARAM) {
+	} else if ((resp & SDMMC_R1_BAD_ERASE_PARAM) == SDMMC_R1_BAD_ERASE_PARAM) {
 		return SD_ERROR_BAD_ERASE_PARAM;
-	} else if ((response_r0 & SDMMC_R1_WRITE_PROT_VIOLATION) == SDMMC_R1_WRITE_PROT_VIOLATION) {
+	} else if ((resp & SDMMC_R1_WRITE_PROT_VIOLATION) == SDMMC_R1_WRITE_PROT_VIOLATION) {
 		return SD_ERROR_WRITE_PROT_VIOLATION;
-	} else if ((response_r0 & SDMMC_R1_LOCK_UNLOCK_FAILED) == SDMMC_R1_LOCK_UNLOCK_FAILED) {
+	} else if ((resp & SDMMC_R1_LOCK_UNLOCK_FAILED) == SDMMC_R1_LOCK_UNLOCK_FAILED) {
 		return SD_ERROR_LOCK_UNLOCK_FAILED;
-	} else if ((response_r0 & SDMMC_R1_COM_CRC_FAILED) == SDMMC_R1_COM_CRC_FAILED) {
+	} else if ((resp & SDMMC_R1_COM_CRC_FAILED) == SDMMC_R1_COM_CRC_FAILED) {
 		return SD_ERROR_COM_CRC_FAILED;
-	} else if ((response_r0 & SDMMC_R1_ILLEGAL_CMD) == SDMMC_R1_ILLEGAL_CMD) {
+	} else if ((resp & SDMMC_R1_ILLEGAL_CMD) == SDMMC_R1_ILLEGAL_CMD) {
 		return SD_ERROR_ILLEGAL_CMD;
-	} else if ((response_r0 & SDMMC_R1_CARD_ECC_FAILED) == SDMMC_R1_CARD_ECC_FAILED) {
+	} else if ((resp & SDMMC_R1_CARD_ECC_FAILED) == SDMMC_R1_CARD_ECC_FAILED) {
 		return SD_ERROR_CARD_ECC_FAILED;
-	} else if ((response_r0 & SDMMC_R1_CC_ERROR) == SDMMC_R1_CC_ERROR) {
+	} else if ((resp & SDMMC_R1_CC_ERROR) == SDMMC_R1_CC_ERROR) {
 		return SD_ERROR_CC_ERR;
-	} else if ((response_r0 & SDMMC_R1_STREAM_READ_UNDERRUN) == SDMMC_R1_STREAM_READ_UNDERRUN) {
+	} else if ((resp & SDMMC_R1_STREAM_READ_UNDERRUN) == SDMMC_R1_STREAM_READ_UNDERRUN) {
 		return SD_ERROR_STREAM_READ_UNDERRUN;
-	} else if ((response_r0 & SDMMC_R1_STREAM_WRITE_OVERRUN) == SDMMC_R1_STREAM_WRITE_OVERRUN) {
+	} else if ((resp & SDMMC_R1_STREAM_WRITE_OVERRUN) == SDMMC_R1_STREAM_WRITE_OVERRUN) {
 		return SD_ERROR_STREAM_WRITE_OVERRUN;
-	} else if ((response_r0 & SDMMC_R1_CID_CSDMMC_OVERWRITE) == SDMMC_R1_CID_CSDMMC_OVERWRITE) {
+	} else if ((resp & SDMMC_R1_CID_CSDMMC_OVERWRITE) == SDMMC_R1_CID_CSDMMC_OVERWRITE) {
 		return SD_ERROR_CID_CSDMMC_OVERWRITE;
-	} else if ((response_r0 & SDMMC_R1_WP_ERASE_SKIP) == SDMMC_R1_WP_ERASE_SKIP) {
+	} else if ((resp & SDMMC_R1_WP_ERASE_SKIP) == SDMMC_R1_WP_ERASE_SKIP) {
 		return SD_ERROR_WP_ERASE_SKIP;
-	} else if ((response_r0 & SDMMC_R1_CARD_ECC_DISABLED) == SDMMC_R1_CARD_ECC_DISABLED) {
+	} else if ((resp & SDMMC_R1_CARD_ECC_DISABLED) == SDMMC_R1_CARD_ECC_DISABLED) {
 		return SD_ERROR_CARD_ECC_DISABLED;
-	} else if ((response_r0 & SDMMC_R1_ERASE_RESET) == SDMMC_R1_ERASE_RESET) {
+	} else if ((resp & SDMMC_R1_ERASE_RESET) == SDMMC_R1_ERASE_RESET) {
 		return SD_ERROR_ERASE_RESET;
-	} else if ((response_r0 & SDMMC_R1_AKE_SEQ_ERROR) == SDMMC_R1_AKE_SEQ_ERROR) {
+	} else if ((resp & SDMMC_R1_AKE_SEQ_ERROR) == SDMMC_R1_AKE_SEQ_ERROR) {
 		return SD_ERROR_AKE_SEQ_ERR;
 	} else {
 		return SD_ERROR_GENERAL_UNKNOWN_ERR;
@@ -1431,185 +1408,19 @@ u32 SDMMC_GetCmdResp1B(SDIOHOST_TypeDef *SDIOx, u32 Timeout)
 }
 
 /**
- * @brief  Checks for error conditions for R2 (CID or CSD) response.
- * @param  SDIOx Pointer to SDIO host
- * @retval SD Card error state
- */
-u32 SDMMC_GetCmdResp2(SDIOHOST_TypeDef *SDIOx)
-{
-	u32 count = 0;
-	u32 norm_int, err_int;
-
-	while (1) {
-		norm_int = SDIO_GetNormSts(SDIOx);
-		err_int = SDIO_GetErrSts(SDIOx);
-
-		if ((norm_int & SDIOHOST_BIT_CMD_COMPLETE) || (err_int & SDIO_CMD_ERR)) {
-			break;
-		}
-
-		if (count++ >= SDMMC_CMD_TIMEOUT) {
-			RTK_LOGE(TAG, "%s timeout\n", __FUNCTION__);
-			return SD_ERROR_TIMEOUT;
-		}
-
-		/* exit while-loop ASAP */
-		DelayUs(1);
-	}
-
-	if (norm_int & SDIOHOST_BIT_CMD_COMPLETE) {
-		SDIO_ClearNormSts(SDIOx, SDIOHOST_BIT_CMD_COMPLETE);
-	}
-
-	if (err_int & SDIO_CMD_ERR) {
-		SDIO_ClearErrSts(SDIOx, SDIO_CMD_ERR);
-		if (err_int & SDIOHOST_BIT_CMD_TIMEOUT_ERR) {
-			return SD_ERROR_CMD_RSP_TIMEOUT;
-		} else {
-			return SD_ERROR_GENERAL_UNKNOWN_ERR;
-		}
-	}
-
-	return SD_ERROR_NONE;
-}
-
-/**
- * @brief  Checks for error conditions for R3 (OCR) response.
- * @param  SDIOx Pointer to SDIO host
- * @retval SD Card error state
- */
-u32 SDMMC_GetCmdResp3(SDIOHOST_TypeDef *SDIOx)
-{
-	u32 count = 0;
-	u32 norm_int, err_int;
-
-	while (1) {
-		norm_int = SDIO_GetNormSts(SDIOx);
-		err_int = SDIO_GetErrSts(SDIOx);
-
-		if ((norm_int & SDIOHOST_BIT_CMD_COMPLETE) || (err_int & SDIO_CMD_ERR)) {
-			break;
-		}
-
-		if (count++ >= SDMMC_CMD_TIMEOUT) {
-			RTK_LOGE(TAG, "%s timeout\n", __FUNCTION__);
-			return SD_ERROR_TIMEOUT;
-		}
-
-		/* exit while-loop ASAP */
-		DelayUs(1);
-	}
-
-	if (norm_int & SDIOHOST_BIT_CMD_COMPLETE) {
-		SDIO_ClearNormSts(SDIOx, SDIOHOST_BIT_CMD_COMPLETE);
-	}
-
-	if (err_int & SDIO_CMD_ERR) {
-		SDIO_ClearErrSts(SDIOx, SDIO_CMD_ERR);
-		if (err_int & SDIOHOST_BIT_CMD_TIMEOUT_ERR) {
-			return SD_ERROR_CMD_RSP_TIMEOUT;
-		} else {
-			return SD_ERROR_GENERAL_UNKNOWN_ERR;
-		}
-	}
-
-	return SD_ERROR_NONE;
-}
-
-/**
- * @brief  Checks for error conditions for R3 (OCR) response.
- * @param  SDIOx Pointer to SDIO host
- * @retval SD Card error state
- */
-u32 SDMMC_GetCmdResp4(SDIOHOST_TypeDef *SDIOx)
-{
-	u32 count = 0;
-	u32 norm_int, err_int;
-
-	while (1) {
-		norm_int = SDIO_GetNormSts(SDIOx);
-		err_int = SDIO_GetErrSts(SDIOx);
-
-		if ((norm_int & SDIOHOST_BIT_CMD_COMPLETE) || (err_int & SDIO_CMD_ERR)) {
-			break;
-		}
-
-		if (count++ >= SDMMC_CMD_TIMEOUT) {
-			RTK_LOGE(TAG, "%s timeout\n", __FUNCTION__);
-			return SD_ERROR_TIMEOUT;
-		}
-
-		/* exit while-loop ASAP */
-		DelayUs(1);
-	}
-
-	if (norm_int & SDIOHOST_BIT_CMD_COMPLETE) {
-		SDIO_ClearNormSts(SDIOx, SDIOHOST_BIT_CMD_COMPLETE);
-	}
-
-	if (err_int & SDIO_CMD_ERR) {
-		SDIO_ClearErrSts(SDIOx, SDIO_CMD_ERR);
-		if (err_int & SDIOHOST_BIT_CMD_TIMEOUT_ERR) {
-			return SD_ERROR_CMD_RSP_TIMEOUT;
-		} else {
-			return SD_ERROR_GENERAL_UNKNOWN_ERR;
-		}
-	}
-
-	return SD_ERROR_NONE;
-}
-
-/**
- * @brief  Checks for error conditions for R1 response.
- * @param  SDIOx Pointer to SDIO host
- * @retval SD Card error state
+ * @brief  Checks for error conditions for R5 response.
+ * @param  resp R5 Response of CMD.
+ * @retval SD Card error state.
  */
-u32 SDMMC_GetCmdResp5(SDIOHOST_TypeDef *SDIOx)
+u32 SDMMC_CheckErrResp5(u32 resp)
 {
-	u32 response_r0;
-	u32 count = 0;
-	u32 norm_int, err_int;
-
-	while (1) {
-		norm_int = SDIO_GetNormSts(SDIOx);
-		err_int = SDIO_GetErrSts(SDIOx);
-
-		if ((norm_int & SDIOHOST_BIT_CMD_COMPLETE) || (err_int & SDIO_CMD_ERR)) {
-			break;
-		}
-
-		if (count++ >= SDMMC_CMD_TIMEOUT) {
-			RTK_LOGE(TAG, "%s timeout\n", __FUNCTION__);
-			return SD_ERROR_TIMEOUT;
-		}
-
-		/* exit while-loop ASAP */
-		DelayUs(1);
-	}
-
-	if (norm_int & SDIOHOST_BIT_CMD_COMPLETE) {
-		SDIO_ClearNormSts(SDIOx, SDIOHOST_BIT_CMD_COMPLETE);
-	}
-
-	if (err_int & SDIO_CMD_ERR) {
-		SDIO_ClearErrSts(SDIOx, SDIO_CMD_ERR);
-		if (err_int & SDIOHOST_BIT_CMD_TIMEOUT_ERR) {
-			return SD_ERROR_CMD_RSP_TIMEOUT;
-		} else {
-			return SD_ERROR_GENERAL_UNKNOWN_ERR;
-		}
-	}
-
-	/* We have received response, retrieve it.  */
-	response_r0 = SDIO_GetResponse(SDIOx, SDIO_RESP0);
-
-	if ((response_r0 & SDMMC_R5_ERRORBITS) == SDMMC_ALLZERO) {
+	if ((resp & SDMMC_R5_ERRORBITS) == SDMMC_ALLZERO) {
 		return SD_ERROR_NONE;
-	} else if ((response_r0 & SDMMC_R5_COM_CRC_ERROR) == SDMMC_R5_COM_CRC_ERROR) {
+	} else if ((resp & SDMMC_R5_COM_CRC_ERROR) == SDMMC_R5_COM_CRC_ERROR) {
 		return SD_ERROR_CMD_CRC_FAIL;
-	} else if ((response_r0 & SDMMC_R5_ILLEGAL_COMMAND) == SDMMC_R5_ILLEGAL_COMMAND) {
+	} else if ((resp & SDMMC_R5_ILLEGAL_COMMAND) == SDMMC_R5_ILLEGAL_COMMAND) {
 		return SD_ERROR_ILLEGAL_CMD;
-	} else if ((response_r0 & SDMMC_R5_OUT_OF_RANGE) == SDMMC_R5_OUT_OF_RANGE) {
+	} else if ((resp & SDMMC_R5_OUT_OF_RANGE) == SDMMC_R5_OUT_OF_RANGE) {
 		return SD_ERROR_ADDR_OUT_OF_RANGE;
 	} else {
 		return SD_ERROR_GENERAL_UNKNOWN_ERR;
@@ -1617,106 +1428,20 @@ u32 SDMMC_GetCmdResp5(SDIOHOST_TypeDef *SDIOx)
 }
 
 /**
- * @brief  Checks for error conditions for R6 (RCA) response.
- * @param  SDIOx Pointer to SDIO host
- * @param  SDMMC_CMD: The sent command index
- * @param  pRCA: Pointer to the variable that will contain the SD card relative
- *         address RCA
- * @retval SD Card error state
+ * @brief  Checks for error conditions for R6 response.
+ * @param  resp R6 Response of CMD.
+ * @retval SD Card error state.
  */
-u32 SDMMC_GetCmdResp6(SDIOHOST_TypeDef *SDIOx, u16 *pRCA)
+u32 SDMMC_CheckErrResp6(u32 resp)
 {
-	u32 response_r0;
-	u32 count = 0;
-	u32 norm_int, err_int;
-
-	while (1) {
-		norm_int = SDIO_GetNormSts(SDIOx);
-		err_int = SDIO_GetErrSts(SDIOx);
-
-		if ((norm_int & SDIOHOST_BIT_CMD_COMPLETE) || (err_int & SDIO_CMD_ERR)) {
-			break;
-		}
-
-		if (count++ >= SDMMC_CMD_TIMEOUT) {
-			RTK_LOGE(TAG, "%s timeout\n", __FUNCTION__);
-			return SD_ERROR_TIMEOUT;
-		}
-
-		/* exit while-loop ASAP */
-		DelayUs(1);
-	}
-
-	if (norm_int & SDIOHOST_BIT_CMD_COMPLETE) {
-		SDIO_ClearNormSts(SDIOx, SDIOHOST_BIT_CMD_COMPLETE);
-	}
-
-	if (err_int & SDIO_CMD_ERR) {
-		SDIO_ClearErrSts(SDIOx, SDIO_CMD_ERR);
-		if (err_int & SDIOHOST_BIT_CMD_TIMEOUT_ERR) {
-			return SD_ERROR_CMD_RSP_TIMEOUT;
-		} else {
-			return SD_ERROR_GENERAL_UNKNOWN_ERR;
-		}
-	}
-
-	/* We have received response, retrieve it.  */
-	response_r0 = SDIO_GetResponse(SDIOx, SDIO_RESP0);
-
-	if ((response_r0 & (SDMMC_R6_GENERAL_UNKNOWN_ERROR | SDMMC_R6_ILLEGAL_CMD |
-						SDMMC_R6_COM_CRC_FAILED)) == SDMMC_ALLZERO) {
-		*pRCA = (u16)(response_r0 >> 16);
-
+	if ((resp & (SDMMC_R6_GENERAL_UNKNOWN_ERROR | SDMMC_R6_ILLEGAL_CMD |
+				 SDMMC_R6_COM_CRC_FAILED)) == SDMMC_ALLZERO) {
 		return SD_ERROR_NONE;
-	} else if ((response_r0 & SDMMC_R6_ILLEGAL_CMD) == SDMMC_R6_ILLEGAL_CMD) {
+	} else if ((resp & SDMMC_R6_ILLEGAL_CMD) == SDMMC_R6_ILLEGAL_CMD) {
 		return SD_ERROR_ILLEGAL_CMD;
-	} else if ((response_r0 & SDMMC_R6_COM_CRC_FAILED) == SDMMC_R6_COM_CRC_FAILED) {
+	} else if ((resp & SDMMC_R6_COM_CRC_FAILED) == SDMMC_R6_COM_CRC_FAILED) {
 		return SD_ERROR_COM_CRC_FAILED;
 	} else {
 		return SD_ERROR_GENERAL_UNKNOWN_ERR;
 	}
 }
-
-/**
- * @brief  Checks for error conditions for R7 response.
- * @param  SDIOx Pointer to SDIO host
- * @retval SD Card error state
- */
-u32 SDMMC_GetCmdResp7(SDIOHOST_TypeDef *SDIOx)
-{
-	u32 count = 0;
-	u32 norm_int, err_int;
-
-	while (1) {
-		norm_int = SDIO_GetNormSts(SDIOx);
-		err_int = SDIO_GetErrSts(SDIOx);
-
-		if ((norm_int & SDIOHOST_BIT_CMD_COMPLETE) || (err_int & SDIO_CMD_ERR)) {
-			break;
-		}
-
-		if (count++ >= SDMMC_CMD_TIMEOUT) {
-			RTK_LOGE(TAG, "%s timeout\n", __FUNCTION__);
-			return SD_ERROR_TIMEOUT;
-		}
-
-		/* exit while-loop ASAP */
-		DelayUs(1);
-	}
-
-	if (norm_int & SDIOHOST_BIT_CMD_COMPLETE) {
-		SDIO_ClearNormSts(SDIOx, SDIOHOST_BIT_CMD_COMPLETE);
-	}
-
-	if (err_int & SDIO_CMD_ERR) {
-		DelayUs(10); // avoid cmd_err sts is set again after clear
-		SDIO_ClearErrSts(SDIOx, SDIO_CMD_ERR);
-		if (err_int & SDIOHOST_BIT_CMD_TIMEOUT_ERR) {
-			return SD_ERROR_CMD_RSP_TIMEOUT;
-		} else {
-			return SD_ERROR_GENERAL_UNKNOWN_ERR;
-		}
-	}
-
-	return SD_ERROR_NONE;
-}
diff --git a/ameba/amebaG2/source/fwlib/ram_common/ameba_sdio_device.c b/ameba/amebag2/source/fwlib/ram_common/ameba_sdio_device.c
similarity index 100%
rename from ameba/amebaG2/source/fwlib/ram_common/ameba_sdio_device.c
rename to ameba/amebag2/source/fwlib/ram_common/ameba_sdio_device.c
diff --git a/ameba/amebaG2/source/fwlib/ram_common/ameba_spi.c b/ameba/amebag2/source/fwlib/ram_common/ameba_spi.c
similarity index 99%
rename from ameba/amebaG2/source/fwlib/ram_common/ameba_spi.c
rename to ameba/amebag2/source/fwlib/ram_common/ameba_spi.c
index a8d768c6..db196a76 100644
--- a/ameba/amebaG2/source/fwlib/ram_common/ameba_spi.c
+++ b/ameba/amebag2/source/fwlib/ram_common/ameba_spi.c
@@ -1187,4 +1187,4 @@ void SSI_SlaveOutputEnable(SPI_TypeDef *spi_dev, u32 Status)
 
 /** @} */
 
-/** @} */
\ No newline at end of file
+/** @} */
diff --git a/ameba/amebaG2/source/fwlib/ram_common/ameba_sport.c b/ameba/amebag2/source/fwlib/ram_common/ameba_sport.c
similarity index 99%
rename from ameba/amebaG2/source/fwlib/ram_common/ameba_sport.c
rename to ameba/amebag2/source/fwlib/ram_common/ameba_sport.c
index 2a997780..7aa97219 100644
--- a/ameba/amebaG2/source/fwlib/ram_common/ameba_sport.c
+++ b/ameba/amebag2/source/fwlib/ram_common/ameba_sport.c
@@ -1991,4 +1991,4 @@ void AUDIO_SP_SetRxDataFormat(u32 index, u32 format)
 
 /** @} */
 
-/** @} */
\ No newline at end of file
+/** @} */
diff --git a/ameba/amebaG2/source/fwlib/ram_common/ameba_swr.c b/ameba/amebag2/source/fwlib/ram_common/ameba_swr.c
similarity index 100%
rename from ameba/amebaG2/source/fwlib/ram_common/ameba_swr.c
rename to ameba/amebag2/source/fwlib/ram_common/ameba_swr.c
diff --git a/ameba/amebaG2/source/fwlib/ram_common/ameba_thermal.c b/ameba/amebag2/source/fwlib/ram_common/ameba_thermal.c
similarity index 99%
rename from ameba/amebaG2/source/fwlib/ram_common/ameba_thermal.c
rename to ameba/amebag2/source/fwlib/ram_common/ameba_thermal.c
index 96084b5d..5a30cc92 100644
--- a/ameba/amebaG2/source/fwlib/ram_common/ameba_thermal.c
+++ b/ameba/amebag2/source/fwlib/ram_common/ameba_thermal.c
@@ -499,4 +499,4 @@ float TM_GetFdegree(u32 Data)
 /** @} */
 
 /** @} */
-/** @} */
\ No newline at end of file
+/** @} */
diff --git a/ameba/amebaG2/source/fwlib/ram_common/ameba_tim.c b/ameba/amebag2/source/fwlib/ram_common/ameba_tim.c
similarity index 99%
rename from ameba/amebaG2/source/fwlib/ram_common/ameba_tim.c
rename to ameba/amebag2/source/fwlib/ram_common/ameba_tim.c
index 0f7c401b..49d80ec4 100644
--- a/ameba/amebaG2/source/fwlib/ram_common/ameba_tim.c
+++ b/ameba/amebag2/source/fwlib/ram_common/ameba_tim.c
@@ -838,4 +838,4 @@ u32 RTIM_IsChannelCaptureEnabled(RTIM_TypeDef *TIMx, u16 TIM_Channel)
 		return RTK_FAIL;
 	}
 
-}
\ No newline at end of file
+}
diff --git a/ameba/amebaG2/source/fwlib/ram_common/ameba_uart.c b/ameba/amebag2/source/fwlib/ram_common/ameba_uart.c
similarity index 96%
rename from ameba/amebaG2/source/fwlib/ram_common/ameba_uart.c
rename to ameba/amebag2/source/fwlib/ram_common/ameba_uart.c
index 886402b3..12f14974 100644
--- a/ameba/amebaG2/source/fwlib/ram_common/ameba_uart.c
+++ b/ameba/amebag2/source/fwlib/ram_common/ameba_uart.c
@@ -633,6 +633,38 @@ void UART_RTSForceCmd(UART_TypeDef *UARTx, u32 NewState)
 	}
 }
 
+/**
+ * @brief Configure UART rx timeout threshold.
+ * @param UARTx UART device, where x can be 0~3.
+ * @param RxTimeout Rx timeout value, unit is one bit time.
+ * @return None
+ */
+void UART_RxToThreConfig(UART_TypeDef *UARTx, u32 RxTimeout)
+{
+	assert_param(RxTimeout <= 0xFFFF);
+
+	u32 reg = UARTx->RX_PATH_CTRL;
+	reg &= ~RUART_MASK_R_RXTO_THRS;
+	reg |= RUART_R_RXTO_THRS(RxTimeout);
+	UARTx->RX_PATH_CTRL = reg;
+}
+
+/**
+ * @brief Configure UART rxfifo empty timeout threshold.
+ * @param UARTx UART device, where x can be 0~3.
+ * @param RxTimeout Rx timeout counter works in uart_rclk.
+ * @return None
+ */
+void UART_REToThreConfig(UART_TypeDef *UARTx, u32 RxTimeout)
+{
+	assert_param(RxTimeout <= 0xFFFFFFF);
+
+	u32 reg = UARTx->TH_RETI;
+	reg &= ~RUART_MASK_TH_RETI;
+	reg |= RUART_TH_RETI(RxTimeout);
+	UARTx->TH_RETI = reg;
+}
+
 /**
  * @}
  */
@@ -643,4 +675,4 @@ void UART_RTSForceCmd(UART_TypeDef *UARTx, u32 NewState)
 
 /**
  * @}
- */
\ No newline at end of file
+ */
diff --git a/ameba/amebaG2/source/fwlib/ram_common/ameba_ups.c b/ameba/amebag2/source/fwlib/ram_common/ameba_ups.c
similarity index 99%
rename from ameba/amebaG2/source/fwlib/ram_common/ameba_ups.c
rename to ameba/amebag2/source/fwlib/ram_common/ameba_ups.c
index e7c5e973..8465299c 100644
--- a/ameba/amebaG2/source/fwlib/ram_common/ameba_ups.c
+++ b/ameba/amebag2/source/fwlib/ram_common/ameba_ups.c
@@ -146,4 +146,4 @@ void UPS_SetDbcCnt(u16 Dbc_Cnt, u8 idx)
 	Temp &= ~TIM_MASK_UPS0_DBC_CNT;
 	Temp |= TIM_UPS0_DBC_CNT(Dbc_Cnt);
 	HAL_WRITE32(UPS_REG_BASE, REG_LSYS_UPS_CTRLx[idx], Temp);
-}
\ No newline at end of file
+}
diff --git a/ameba/amebaG2/source/fwlib/ram_common/ameba_usb.c b/ameba/amebag2/source/fwlib/ram_common/ameba_usb.c
similarity index 77%
rename from ameba/amebaG2/source/fwlib/ram_common/ameba_usb.c
rename to ameba/amebag2/source/fwlib/ram_common/ameba_usb.c
index f86963eb..39ca36ce 100644
--- a/ameba/amebaG2/source/fwlib/ram_common/ameba_usb.c
+++ b/ameba/amebag2/source/fwlib/ram_common/ameba_usb.c
@@ -8,6 +8,7 @@
 
 #include "ameba_soc.h"
 #include "usb_hal.h"
+#include "usb_regs.h"
 
 /* Private defines -----------------------------------------------------------*/
 
@@ -33,7 +34,9 @@ static void usb_chip_enable_interrupt(u8 priority);
 static void usb_chip_disable_interrupt(void);
 static void usb_chip_register_irq_handler(void *handler, u8 priority);
 static void usb_chip_unregister_irq_handler(void);
-
+#if CONFIG_USB_PM
+static void usb_chip_cg(u32 ms);
+#endif
 /* Private variables ---------------------------------------------------------*/
 
 static usb_cal_data_t usb_cal_data[USB_CAL_DATA_LEN];
@@ -48,6 +51,9 @@ usb_hal_driver_t usb_hal_driver = {
 	.disable_interrupt = usb_chip_disable_interrupt,
 	.register_irq_handler = usb_chip_register_irq_handler,
 	.unregister_irq_handler = usb_chip_unregister_irq_handler,
+#if CONFIG_USB_PM
+	.cg = usb_chip_cg,
+#endif
 };
 
 /* Private functions ---------------------------------------------------------*/
@@ -319,7 +325,7 @@ static void usb_chip_disable_interrupt(void)
 static void usb_chip_register_irq_handler(void *handler, u8 priority)
 {
 	if (handler != NULL) {
-		InterruptRegister((IRQ_FUN)handler, USB_IRQ, (u32)NULL, priority);
+		InterruptRegister((IRQ_FUN)handler, USB_IRQ, NULL, priority);
 	}
 }
 
@@ -331,4 +337,92 @@ static void usb_chip_unregister_irq_handler(void)
 {
 	InterruptUnRegister(USB_IRQ);
 }
+
+#if CONFIG_USB_PM
+static void usb_chip_wake_event(u8 enable)
+{
+	if (enable) {
+		SOCPS_SetAPWakeEvent(WAKE_SRC_USB, ENABLE);
+	} else {
+		SOCPS_SetAPWakeEvent(WAKE_SRC_USB, DISABLE);
+	}
+}
+
+static u32 usb_chip_cg_suspend_cb(u32 expected_idle_time, void *param)
+{
+	(void) expected_idle_time;
+	(void) param;
+	PLL_TypeDef *sys_pll = (PLL_TypeDef *)PLL_REG_BASE;
+
+	USB_PCGCCTL = USB_PCGCCTL | USB_OTG_PCGCCTL_STOPCLK;
+
+	sys_pll->PLL_UPLL_CTRL0 |= PLL_BIT_SUSPEND_WAK_MSK;
+	return TRUE;
+}
+
+static u32 usb_chip_cg_resume_cb(u32 expected_idle_time, void *param)
+{
+	(void) expected_idle_time;
+	(void) param;
+	u32 reg;
+
+	USB_PCGCCTL = USB_PCGCCTL & (~(USB_OTG_PCGCCTL_STOPCLK | USB_OTG_PCGCCTL_GATECLK));
+
+	reg = HAL_READ32(USB_ADDON_REG_CTRL, 0);
+	reg &= ~USB_ADDON_REG_CTRL_BIT_DIS_SUSPEND;
+	HAL_WRITE32(USB_ADDON_REG_CTRL, 0U, reg);
+
+	PLL_TypeDef *sys_pll = (PLL_TypeDef *)PLL_REG_BASE;
+	sys_pll->PLL_UPLL_CTRL0 &= ~PLL_BIT_SUSPEND_WAK_MSK;
+
+	usb_chip_wake_event(0);
+	pmu_acquire_wakelock(PMU_OS);//Stay active
+	pmu_unregister_sleep_callback(PMU_DEV_USER_BASE);
+	return TRUE;
+}
+
+static u32 usb_chip_aontimer_cb(void *Data)
+{
+	(void)Data;
+
+	RTK_LOGS(NOTAG, RTK_LOG_INFO, "AON timer handler: %x\n", SOCPS_AONWakeReason());
+	AONTimer_ClearINT();
+	RCC_PeriphClockCmd(APBPeriph_ATIM, APBPeriph_ATIM_CLOCK, DISABLE);
+	pmu_acquire_wakelock(PMU_OS);//Stay active
+	return 0;
+}
+
+static void usb_chip_aontimer_cg(u32 ms)
+{
+	RCC_PeriphClockCmd(APBPeriph_ATIM, APBPeriph_ATIM_CLOCK, ENABLE);
+	RTK_LOGS(NOTAG, RTK_LOG_INFO, "AON timer %d ms\n", ms);
+
+	AONTimer_Setting(ms);
+	AONTimer_INT(ENABLE);
+
+	InterruptRegister((IRQ_FUN)usb_chip_aontimer_cb, AON_TIM_IRQ, NULL, 3);
+	InterruptEn(AON_TIM_IRQ, 3);
+
+	SOCPS_SetAPWakeEvent(WAKE_SRC_AON_TIM, ENABLE);
+}
+
+static void usb_chip_cg(u32 ms)
+{
+	/*Set AP sleep type*/
+	pmu_set_sleep_type(SLEEP_CG);
+	/*Acquire wakelock to avoid AP enter sleep mode*/
+	pmu_acquire_wakelock(PMU_OS);
+
+	pmu_register_sleep_callback(PMU_DEV_USER_BASE, (PSM_HOOK_FUN)usb_chip_cg_suspend_cb, NULL, (PSM_HOOK_FUN)usb_chip_cg_resume_cb, NULL);
+
+	if (ms) {//Select CG wake event
+		usb_chip_aontimer_cg(ms);//Aon timer wakeup
+	} else {
+		usb_chip_wake_event(1);//USB event wakeup
+	}
+	/* Release wakelock, to make CPU enter sleep mode */
+	pmu_release_wakelock(PMU_OS);
+}
+#endif
+
 /* Exported functions --------------------------------------------------------*/
diff --git a/ameba/amebaG2/source/fwlib/ram_common/ameba_uvc.c b/ameba/amebag2/source/fwlib/ram_common/ameba_uvc.c
similarity index 100%
rename from ameba/amebaG2/source/fwlib/ram_common/ameba_uvc.c
rename to ameba/amebag2/source/fwlib/ram_common/ameba_uvc.c
diff --git a/ameba/amebaG2/source/fwlib/ram_common/ameba_wakepin.c b/ameba/amebag2/source/fwlib/ram_common/ameba_wakepin.c
similarity index 100%
rename from ameba/amebaG2/source/fwlib/ram_common/ameba_wakepin.c
rename to ameba/amebag2/source/fwlib/ram_common/ameba_wakepin.c
diff --git a/ameba/amebaG2/source/fwlib/ram_km4tz/ameba_ethernet.c b/ameba/amebag2/source/fwlib/ram_km4tz/ameba_ethernet.c
similarity index 73%
rename from ameba/amebaG2/source/fwlib/ram_km4tz/ameba_ethernet.c
rename to ameba/amebag2/source/fwlib/ram_km4tz/ameba_ethernet.c
index 9abeceac..b6afae7a 100644
--- a/ameba/amebaG2/source/fwlib/ram_km4tz/ameba_ethernet.c
+++ b/ameba/amebag2/source/fwlib/ram_km4tz/ameba_ethernet.c
@@ -189,7 +189,7 @@ void Ethernet_AutoPolling(u32 opt)
 u8 *Ethernet_GetTXPktInfo(ETH_InitTypeDef *ETH_InitStruct)
 {
 	ETHERNET_TypeDef *RMII = ((ETHERNET_TypeDef *) RMII_REG_BASE);
-	u8 tx_search_idx = ETH_InitStruct->ETH_TxDescCurrentNum;
+	u8 tx_idx = ETH_InitStruct->ETH_TxDescCurrentNum;
 	u8 *buf = NULL;
 
 	if (ETH_InitStruct == NULL) {
@@ -198,13 +198,10 @@ u8 *Ethernet_GetTXPktInfo(ETH_InitTypeDef *ETH_InitStruct)
 	}
 
 	/* check if current Tx descriptor is available */
-	if ((((u32)(ETH_InitStruct->ETH_TxDesc[tx_search_idx].dw1)) & FEMAC_TX_DSC_BIT_OWN) == 0) {
-		buf = (u8 *)ETH_InitStruct->ETH_TxDesc[tx_search_idx].addr;
+	if ((((u32)(ETH_InitStruct->ETH_TxDesc[tx_idx].dw1)) & FEMAC_TX_DSC_BIT_OWN) == 0) {
+		buf = (u8 *)ETH_InitStruct->ETH_TxDesc[tx_idx].addr;
 	} else {
 		RMII->ETH_ISR_AND_IMR |= BIT_ISR_TOK_TI;
-		/* enable Tx ring1 */
-		//RMII->ETH_ETHER_IO_CMD |= BIT_TXFN1ST;
-		//RTK_LOGE(TAG, "Tx descriptor ring is full !!\r\n");
 	}
 
 	return buf;
@@ -221,7 +218,7 @@ u8 *Ethernet_GetTXPktInfo(ETH_InitTypeDef *ETH_InitStruct)
 void Ethernet_UpdateTXDESCAndSend(ETH_InitTypeDef *ETH_InitStruct, u32 size)
 {
 	ETHERNET_TypeDef *RMII = ((ETHERNET_TypeDef *) RMII_REG_BASE);
-	u8 tx_search_idx = ETH_InitStruct->ETH_TxDescCurrentNum;
+	u8 tx_idx = ETH_InitStruct->ETH_TxDescCurrentNum;
 
 	if (ETH_InitStruct == NULL) {
 		RTK_LOGE(TAG, "Invalid parameter !!\r\n");
@@ -233,23 +230,26 @@ void Ethernet_UpdateTXDESCAndSend(ETH_InitTypeDef *ETH_InitStruct, u32 size)
 		return;
 	}
 
-	DCache_Clean((u32)ETH_InitStruct->ETH_TxDesc[tx_search_idx].addr, (u32)ETH_PKT_BUFF_SZ); //TODO: need invalidate or not
+	DCache_Clean((u32)ETH_InitStruct->ETH_TxDesc[tx_idx].addr, (u32)size); //TODO: need invalidate or not
 
-	ETH_InitStruct->ETH_TxDesc[tx_search_idx].dw2 = 0;
-	ETH_InitStruct->ETH_TxDesc[tx_search_idx].dw3 = 0;
-	ETH_InitStruct->ETH_TxDesc[tx_search_idx].dw4 = 0;
+	ETH_InitStruct->ETH_TxDesc[tx_idx].dw2 = 0;
+	ETH_InitStruct->ETH_TxDesc[tx_idx].dw3 = 0;
+	ETH_InitStruct->ETH_TxDesc[tx_idx].dw4 = 0;
 
-	if (tx_search_idx == ((ETH_InitStruct->ETH_TxDescNum) - 1)) {
-		ETH_InitStruct->ETH_TxDesc[tx_search_idx].dw1 = (FEMAC_TX_DSC_BIT_EOR | FEMAC_TX_DSC_BIT_FS | FEMAC_TX_DSC_BIT_LS | FEMAC_TX_DSC_BIT_CRC | (size & 0x1ffff));
+	if (tx_idx == ((ETH_InitStruct->ETH_TxDescNum) - 1)) {
+		ETH_InitStruct->ETH_TxDesc[tx_idx].dw1 = FEMAC_TX_DSC_BIT_EOR | FEMAC_TX_DSC_BIT_FS | FEMAC_TX_DSC_BIT_IPCS | \
+				FEMAC_TX_DSC_BIT_L4CS | FEMAC_TX_DSC_BIT_LS | FEMAC_TX_DSC_BIT_CRC | \
+				FEMAC_TX_DSC_BIT_SIZE(size);
 	} else {
-		ETH_InitStruct->ETH_TxDesc[tx_search_idx].dw1 = (FEMAC_TX_DSC_BIT_FS | FEMAC_TX_DSC_BIT_LS | FEMAC_TX_DSC_BIT_CRC | (size & 0x1ffff));
+		ETH_InitStruct->ETH_TxDesc[tx_idx].dw1 = FEMAC_TX_DSC_BIT_FS | FEMAC_TX_DSC_BIT_LS | FEMAC_TX_DSC_BIT_IPCS | \
+				FEMAC_TX_DSC_BIT_L4CS | FEMAC_TX_DSC_BIT_CRC | FEMAC_TX_DSC_BIT_SIZE(size);
 	}
-	ETH_InitStruct->ETH_TxDesc[tx_search_idx].dw1 |= FEMAC_TX_DSC_BIT_OWN;
+	ETH_InitStruct->ETH_TxDesc[tx_idx].dw1 |= FEMAC_TX_DSC_BIT_OWN;
 
 	RMII->ETH_ISR_AND_IMR |= BIT_ISR_TOK_TI;
 	RMII->ETH_ETHER_IO_CMD |= BIT_TXFN1ST; //TODO: not need set for each pkt
 
-	if (tx_search_idx == ((ETH_InitStruct->ETH_TxDescNum) - 1)) {
+	if (tx_idx == ((ETH_InitStruct->ETH_TxDescNum) - 1)) {
 		ETH_InitStruct->ETH_TxDescCurrentNum = 0;
 	} else {
 		ETH_InitStruct->ETH_TxDescCurrentNum++;
@@ -267,20 +267,21 @@ void Ethernet_UpdateTXDESCAndSend(ETH_InitTypeDef *ETH_InitStruct, u32 size)
 u8 *Ethernet_GetRXPktInfo(ETH_InitTypeDef *ETH_InitStruct, u32 *rx_len)
 {
 	ETHERNET_TypeDef *RMII = ((ETHERNET_TypeDef *) RMII_REG_BASE);
-	u8 rx_search_idx = ETH_InitStruct->ETH_RxDescCurrentNum;
+	u32 pkt_size = 0;
+	u8 rx_idx = ETH_InitStruct->ETH_RxDescCurrentNum;
 	u8 *buf = NULL;
 
 	/* check if current Rx descriptor is available */
-	if ((((volatile u32)(ETH_InitStruct->ETH_RxDesc[rx_search_idx].dw1)) & FEMAC_TX_DSC_BIT_OWN) == 0) {
-		*rx_len = (ETH_InitStruct->ETH_RxDesc[rx_search_idx].dw1) & 0xFFF;
-		buf = (u8 *)(ETH_InitStruct->ETH_RxDesc[rx_search_idx].addr + 2);
-		DCache_Invalidate((u32)(ETH_InitStruct->ETH_RxDesc[rx_search_idx].addr), (u32)ETH_PKT_BUFF_SZ);
+	if ((((volatile u32)(ETH_InitStruct->ETH_RxDesc[rx_idx].dw1)) & FEMAC_RX_DSC_BIT_OWN) == 0) {
+		pkt_size = FEMAC_RX_DSC_LEN(ETH_InitStruct->ETH_RxDesc[rx_idx].dw1);
+		buf = (u8 *)(ETH_InitStruct->ETH_RxDesc[rx_idx].addr + 2);
+		DCache_Invalidate((u32)(ETH_InitStruct->ETH_RxDesc[rx_idx].addr), (u32)pkt_size);
 	} else {
 		RMII->ETH_ISR_AND_IMR |= BIT_ISR_ROK;
-		*rx_len = 0;
-		return 0;
 	}
 
+	*rx_len = pkt_size;
+
 	return buf;
 }
 
@@ -302,8 +303,8 @@ void Ethernet_UpdateRXDESC(ETH_InitTypeDef *ETH_InitStruct)
 	}
 
 
-	ETH_InitStruct->ETH_RxDesc[read_idx].dw1 &= FEMAC_TX_DSC_BIT_EOR;//? clear
-	ETH_InitStruct->ETH_RxDesc[read_idx].dw1 |= (FEMAC_TX_DSC_BIT_OWN | ETH_PKT_BUFF_SZ);//1600
+	ETH_InitStruct->ETH_RxDesc[read_idx].dw1 &= FEMAC_RX_DSC_BIT_EOR;
+	ETH_InitStruct->ETH_RxDesc[read_idx].dw1 |= (FEMAC_RX_DSC_BIT_OWN | ETH_InitStruct->ETH_RxBufSize);
 	ETH_InitStruct->ETH_RxDesc[read_idx].dw2 = 0;
 	ETH_InitStruct->ETH_RxDesc[read_idx].dw3 = 0;
 
@@ -370,76 +371,82 @@ u8 Ethernet_WaitBusy(u32 WaitType)
 }
 
 /**
- *  @brief To read the specified FEPHY register
- *
- *  @param[in]  page The specified page number.
- *  @param[in]  reg_addr The specified register address.
- *
- *  @returns    The register value.
+ * @brief Waits for the PHY MDIO bus to become idle.
+ *        This function polls the MDIO busy flag until it is cleared or a timeout occurs.
+ * @param RMII         Pointer to the Ethernet MAC register structure.
+ * @param timeout_us   Timeout threshold in microseconds.
+ * @return 0 on success (MDIO idle), -1 on timeout.
  */
-u16 Ethernet_Read_PhyReg(u16 page, u16 reg_addr)
+static inline int Ethernet_WaitPhyIdle(ETHERNET_TypeDef *RMII, uint32_t timeout_us)
 {
-	ETHERNET_TypeDef *RMII = ((ETHERNET_TypeDef *) RMII_REG_BASE);
-	u16 rd_data = 0;
-
-	while (RMII->ETH_MIIAR & BIT_MDIO_BUSY);
-
-	if (reg_addr > 0x1F) {
-		RTK_LOGE(TAG, "Invalid parameter !!\r\n");
-		return 0;
+	uint32_t start = DTimestamp_Get();
+	while ((DTimestamp_Get() - start) <= timeout_us) {
+		if (!(RMII->ETH_MIIAR & BIT_MDIO_BUSY)) {
+			return RTK_SUCCESS;
+		}
+	}
+	return -RTK_ERR_TIMEOUT;
+}
+/**
+ * @brief Reads a 16-bit value from a PHY register via MDIO.
+ * @param phy_id     Physical address of the target PHY.
+ * @param reg_addr   Register address (0~31).
+ * @param data       Output pointer to store the read value.
+ * @return 0 (RTK_SUCCESS) on success, negative value on error.
+ */
+int Ethernet_ReadPhyReg(uint8_t phy_id, uint8_t reg_addr, uint16_t *data)
+{
+	ETHERNET_TypeDef *RMII = (ETHERNET_TypeDef *) RMII_REG_BASE;
+	if (TrustZone_IsSecure()) {
+		RMII = (ETHERNET_TypeDef *) RMII_REG_BASE_S;
+	}
+	if (reg_addr > FEPHY_REG_ADDR_31) {
+		return -RTK_FAIL;
 	}
 
-	// Switch to the specified page by register 31
-	RMII->ETH_MIIAR = (BIT_FLAG | PHYADDRESS(phy_id) | REGADDR4_0(0x1F) | page);
-	DelayUs(70);  // wait for command complete
-
-	Ethernet_WaitBusy(WAIT_SMI_WRITE_DONE);
+	if (Ethernet_WaitPhyIdle(RMII, MDIO_WAIT_TIME) != RTK_SUCCESS) {
+		return -RTK_ERR_BUSY;
+	}
 
 	RMII->ETH_MIIAR = (PHYADDRESS(phy_id) | REGADDR4_0(reg_addr));
-	DelayUs(70);  // wait for command complete
 
+	if (Ethernet_WaitPhyIdle(RMII, MDIO_WAIT_TIME) != RTK_SUCCESS) {
+		return -RTK_ERR_BUSY;
+	}
 
-	Ethernet_WaitBusy(WAIT_SMI_READ_DONE);
-	rd_data = (u16)(RMII->ETH_MIIAR & 0xFFFF);
-
+	*data = (uint16_t)GET_DATA15_0(RMII->ETH_MIIAR);
 
-	return rd_data;
+	return RTK_SUCCESS;
 }
 
 
 /**
- *  @brief To write "data" value to the specified FEPHY register
- *  @param[in]  page The specified page number.
- *  @param[in]  reg_addr The specified register address.
- *  @param[in]  data The specified data value.
- *
- *  @returns    0.
+ * @brief Writes a 16-bit value to a PHY register via MDIO.
+ * @param phy_id    Physical address of the target PHY (refer to datasheet, usually from hardware pins).
+ * @param reg_addr  Register address (0~31, according to IEEE 802.3 standard).
+ * @param data      The value to write.
+ * @return 0 (RTK_SUCCESS) on success, negative value on error.
  */
-u32 Ethernet_Write_PhyReg(u16 page, u16 reg_addr, u16 data)
+int Ethernet_WritePhyReg(uint8_t phy_id, uint8_t reg_addr, uint16_t data)
 {
-	ETHERNET_TypeDef *RMII = ((ETHERNET_TypeDef *) RMII_REG_BASE);
-
-	if (reg_addr > 0x1F) {
-		RTK_LOGE(TAG, "Invalid parameter !!\r\n");
-		return 0;
+	ETHERNET_TypeDef *RMII = (ETHERNET_TypeDef *) RMII_REG_BASE;
+	if (TrustZone_IsSecure()) {
+		RMII = (ETHERNET_TypeDef *) RMII_REG_BASE_S;
+	}
+	if (reg_addr > FEPHY_REG_ADDR_31) {
+		return -RTK_FAIL;
 	}
 
-	while (RMII->ETH_MIIAR & BIT_MDIO_BUSY);
-
-	// Switch to the specified page by register 31
-	RMII->ETH_MIIAR = (BIT_FLAG | PHYADDRESS(phy_id) | BIT_DISABLE_AUTO_POLLING | REGADDR4_0(0x1F) | page);
-	DelayUs(70);  // wait for command complete
-
-	Ethernet_WaitBusy(WAIT_SMI_WRITE_DONE);
+	if (Ethernet_WaitPhyIdle(RMII, MDIO_WAIT_TIME) != RTK_SUCCESS) {
+		return -RTK_ERR_BUSY;
+	}
 
 	RMII->ETH_MIIAR = (BIT_FLAG | BIT_DISABLE_AUTO_POLLING | PHYADDRESS(phy_id) | REGADDR4_0(reg_addr) | data);
-	DelayUs(70);  // wait for command complete
-
-	Ethernet_WaitBusy(WAIT_SMI_WRITE_DONE);
 
-	return 0;
+	return RTK_SUCCESS;
 }
 
+
 /**
   * \brief  Enable ethernet RX.
   * \param  None.
@@ -496,11 +503,12 @@ void Ethernet_StructInit(ETH_InitTypeDef *ETH_InitStruct)
 	ETH_InitStruct->ETH_TxDescCurrentNum = 0;
 	ETH_InitStruct->ETH_RxFrameStartDescIdx = 0;
 	ETH_InitStruct->ETH_RxFrameLen = 0;
+	ETH_InitStruct->ETH_TxFrameLen = 0;
 	ETH_InitStruct->ETH_RxSegmentCount = 0;
 	ETH_InitStruct->ETH_TxAllocBufSize = 1600;
 	ETH_InitStruct->ETH_RxAllocBufSize = 1600;
-	ETH_InitStruct->ETH_TxBufSize = 1524;
-	ETH_InitStruct->ETH_RxBufSize = 1524;
+	ETH_InitStruct->ETH_TxBufSize = ETH_PKT_MAX_SIZE;
+	ETH_InitStruct->ETH_RxBufSize = ETH_PKT_MAX_SIZE;
 }
 
 u32 Ethernet_init(ETH_InitTypeDef *ETH_InitStruct)
@@ -522,35 +530,39 @@ u32 Ethernet_init(ETH_InitTypeDef *ETH_InitStruct)
 	} while (RMII->ETH_CR & BIT_RST);
 
 	/* reset phy */
-	PHY_SW_RESET();
+	PHY_SoftWareReset(PHYID_1);
 
-	DelayMs(200);
+	PHY_SetRefclkDir(PHYID_1, ETH_InitStruct->ETH_RefClkDirec);
 
-	PHY_SET_REFCLK_DIR(RTL_8721F, ETH_InitStruct->ETH_RefClkDirec);
+#ifdef ENABLE_EEE_FUNCTION
+	PHY_SetEEEMode(PHYID_1, ETH_MAC_MODE);
+#endif
 
 #ifdef CHECK_PHY_STATUS
-	u32 tmp;
-	tmp = Ethernet_Read_PhyReg(FEPHY_REG_ADDR_0, FEPHY_REG_ADDR_0);
+	uint16_t tmp;
+	/*select page 0*/
+	Ethernet_WritePhyReg(PHYID_1, FEPHY_REG_ADDR_31, FEPHY_REG_PAGE_0);
+
+	Ethernet_ReadPhyReg(PHYID_1, FEPHY_REG_ADDR_0, &tmp);
 	RTK_LOGI(TAG, "page0 reg0=0x%x\n", tmp);
 
-	tmp = Ethernet_Read_PhyReg(FEPHY_REG_ADDR_0, FEPHY_REG_ADDR_1);
+	Ethernet_ReadPhyReg(PHYID_1, FEPHY_REG_ADDR_1, &tmp);
 	RTK_LOGI(TAG, "page0 reg1=0x%x\n", tmp);
 
-	tmp = Ethernet_Read_PhyReg(FEPHY_REG_ADDR_0, FEPHY_REG_ADDR_2);
+	Ethernet_ReadPhyReg(PHYID_1, FEPHY_REG_ADDR_2, &tmp);
 	RTK_LOGI(TAG, "page0 reg2=0x%x\n", tmp);
 
-	tmp = Ethernet_Read_PhyReg(FEPHY_REG_ADDR_0, FEPHY_REG_ADDR_3);
+	Ethernet_ReadPhyReg(PHYID_1, FEPHY_REG_ADDR_3, &tmp);
 	RTK_LOGI(TAG, "page0 reg3=0x%x\n", tmp);
 
-	tmp = Ethernet_Read_PhyReg(FEPHY_REG_ADDR_7, FEPHY_REG_ADDR_16);
+	/*select page 7*/
+	Ethernet_WritePhyReg(PHYID_1, FEPHY_REG_ADDR_31, FEPHY_REG_ADDR_7);
+
+	Ethernet_ReadPhyReg(PHYID_1, RTL8201FR_PAGE7_REG_RMII_MODE_SET, &tmp);
 	RTK_LOGI(TAG, "page7 reg16=0x%x\n", tmp);
 
 #endif
-
-#ifdef ENABLE_EEE_FUNCTION
-	PHY_ENABLE_EEE(PHY_TYPE_SELECT, ENABLE);
-	PHY_SET_EEE_MODE(PHY_TYPE_SELECT, ETH_MAC_MODE);
-#endif
+	PHY_RestartAutoNego(PHYID_1);
 
 	/* Tx settings */
 
@@ -586,7 +598,7 @@ u32 Ethernet_init(ETH_InitTypeDef *ETH_InitStruct)
 	/* initialize Tx descriptors */
 	for (i = 0; i < (ETH_InitStruct->ETH_TxDescNum); i++) {
 		ETH_InitStruct->ETH_TxDesc[i].dw1 = 0;
-		ETH_InitStruct->ETH_TxDesc[i].addr = (u32)(ETH_InitStruct->ETH_TxPktBuf + (i * ETH_PKT_BUFF_SZ));
+		ETH_InitStruct->ETH_TxDesc[i].addr = (u32)(ETH_InitStruct->ETH_TxPktBuf + (i * ETH_InitStruct->ETH_TxBufSize));
 		ETH_InitStruct->ETH_TxDesc[i].dw2 = 0;//(eth_vlan_hdr_remove << 25) | (ETH_C_VLAN_HDR & 0xFFFF);
 		ETH_InitStruct->ETH_TxDesc[i].dw3 = 0;
 		ETH_InitStruct->ETH_TxDesc[i].dw4 = 0;
@@ -595,11 +607,11 @@ u32 Ethernet_init(ETH_InitTypeDef *ETH_InitStruct)
 	/* initialize Rx descriptors */
 	for (i = 0; i < (ETH_InitStruct->ETH_RxDescNum); i++) {
 		if (i == ((ETH_InitStruct->ETH_RxDescNum) - 1)) {
-			ETH_InitStruct->ETH_RxDesc[i].dw1 = BIT31 | BIT30 | ETH_PKT_BUFF_SZ;
+			ETH_InitStruct->ETH_RxDesc[i].dw1 = FEMAC_RX_DSC_BIT_OWN | FEMAC_RX_DSC_BIT_EOR | ETH_InitStruct->ETH_RxBufSize;
 		} else {
-			ETH_InitStruct->ETH_RxDesc[i].dw1 = BIT31 | ETH_PKT_BUFF_SZ;
+			ETH_InitStruct->ETH_RxDesc[i].dw1 = FEMAC_RX_DSC_BIT_OWN | ETH_InitStruct->ETH_RxBufSize;
 		}
-		ETH_InitStruct->ETH_RxDesc[i].addr = (u32)(ETH_InitStruct->ETH_RxPktBuf + (i * ETH_PKT_BUFF_SZ));
+		ETH_InitStruct->ETH_RxDesc[i].addr = (u32)(ETH_InitStruct->ETH_RxPktBuf + (i * ETH_InitStruct->ETH_RxBufSize));
 		ETH_InitStruct->ETH_RxDesc[i].dw2 = 0;
 		ETH_InitStruct->ETH_RxDesc[i].dw3 = 0;
 	}
@@ -646,4 +658,4 @@ u32 Ethernet_init(ETH_InitTypeDef *ETH_InitStruct)
 	ETH_EnableRx();
 
 	return HAL_OK;
-}
\ No newline at end of file
+}
diff --git a/ameba/amebaG2/source/fwlib/ram_km4tz/ameba_flashclk.c b/ameba/amebag2/source/fwlib/ram_km4tz/ameba_flashclk.c
similarity index 95%
rename from ameba/amebaG2/source/fwlib/ram_km4tz/ameba_flashclk.c
rename to ameba/amebag2/source/fwlib/ram_km4tz/ameba_flashclk.c
index 391f2a25..c898b109 100644
--- a/ameba/amebaG2/source/fwlib/ram_km4tz/ameba_flashclk.c
+++ b/ameba/amebag2/source/fwlib/ram_km4tz/ameba_flashclk.c
@@ -35,15 +35,22 @@ static void FLASH_PLLInit_ClockDiv(void)
 	u32 sys_pll_clk = RRAM_DEV->clk_info_bk.SYSPLL_CLK;
 
 	/* set spic clock src and div */
-	spic_ckd = PLL_ClkSrcGet(sys_pll_clk, usb_pll_clk, CLK_LIMIT_SPIC);
+
+	/* SPIC work in this clock will effect RF performance*/
+	if (sys_pll_clk == PLL_393P216M) {
+		spic_ckd = PLL_ClkSrcGet(PLL_NONE, usb_pll_clk, CLK_LIMIT_SPIC);
+	} else {
+		spic_ckd = PLL_ClkSrcGet(sys_pll_clk, usb_pll_clk, CLK_LIMIT_SPIC);
+	}
+
 	if (spic_ckd & IS_SYS_PLL) {
 		RCC_PeriphClockDividerSet(SYS_PLL_SPIC, GET_CLK_DIV(spic_ckd));
 		RCC_PeriphClockSourceSet(SPIC, SYS_PLL);
-		RTK_LOGI(TAG, "SPIC CLK: %d Hz\n", sys_pll_clk / GET_CLK_DIV(spic_ckd));
+		RTK_LOGI(TAG, "FLASH CLK: %d Hz\n", sys_pll_clk / (2 * GET_CLK_DIV(spic_ckd)));
 	} else {
 		RCC_PeriphClockDividerSet(USB_PLL_SPIC, GET_CLK_DIV(spic_ckd));
 		RCC_PeriphClockSourceSet(SPIC, USB_PLL);
-		RTK_LOGI(TAG, "SPIC CLK: %d Hz\n", usb_pll_clk / GET_CLK_DIV(spic_ckd));
+		RTK_LOGI(TAG, "FLASH CLK: %d Hz\n", usb_pll_clk / (2 * GET_CLK_DIV(spic_ckd)));
 	}
 
 	/* save spic clock para into retention memory */
@@ -58,8 +65,6 @@ int flash_handshake_highspeed(void)
 	u8 Dphy_Dly_Cnt = 3; /* DD recommend this value */
 	int Ret = RTK_FAIL;
 
-	FLASH_PLLInit_ClockDiv();
-
 	/* Note: some full voltage range Flash e.g.GD25WQ64E need 10ns
 	   HW recommend: at leaset 10ns */
 	SPIC->TPR1 = (SPIC->TPR1 & ~MASK_CS_ACTIVE_SETUP) | CS_ACTIVE_SETUP(2);
@@ -70,6 +75,9 @@ int flash_handshake_highspeed(void)
 	/* Open handshake function */
 	FLASH_Read_HandShake_Cmd(Dphy_Dly_Cnt, ENABLE);
 
+	/* If XiP, code may in flash. Handshake should be enabled before set to PLL clk */
+	FLASH_PLLInit_ClockDiv();
+
 	if (FLASH_Read_DataIsRight(valid_img1_addr)) {
 		Ret = RTK_SUCCESS;
 	} else {
diff --git a/ameba/amebaG2/source/fwlib/ram_km4tz/ameba_npcap.c b/ameba/amebag2/source/fwlib/ram_km4tz/ameba_npcap.c
similarity index 100%
rename from ameba/amebaG2/source/fwlib/ram_km4tz/ameba_npcap.c
rename to ameba/amebag2/source/fwlib/ram_km4tz/ameba_npcap.c
diff --git a/ameba/amebag2/source/fwlib/ram_km4tz/ameba_phy.c b/ameba/amebag2/source/fwlib/ram_km4tz/ameba_phy.c
new file mode 100644
index 00000000..9a80ca42
--- /dev/null
+++ b/ameba/amebag2/source/fwlib/ram_km4tz/ameba_phy.c
@@ -0,0 +1,228 @@
+/*
+ * Copyright (c) 2024 Realtek Semiconductor Corp.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "ameba_soc.h"
+static const char *const TAG = "PHY";
+
+
+int PHY_SoftWareReset(uint8_t phy_id)
+{
+	int ret = 0;
+
+	/* Select page 0 */
+	ret = Ethernet_WritePhyReg(phy_id, FEPHY_REG_ADDR_31, FEPHY_REG_PAGE_0);
+	if (ret != RTK_SUCCESS) {
+		RTK_LOGE(TAG, "Failed to select page 0. PHY(%d)", phy_id);
+		return ret;
+	}
+
+	/* Write reset command to Basic Control Register */
+	ret = Ethernet_WritePhyReg(phy_id, FEPHY_REG_ADDR_0, PHY_RESET);
+	if (ret != RTK_SUCCESS) {
+		RTK_LOGE(TAG, "Failed to write software reset. PHY(%d)", phy_id);
+		return ret;
+	}
+
+	/* Wait for reset to complete as required by the datasheet */
+	DelayMs(20);
+	return RTK_SUCCESS;
+}
+
+int PHY_RestartAutoNego(uint8_t phy_id)
+{
+	int ret = 0;
+
+	/* Select page 0 */
+	ret = Ethernet_WritePhyReg(phy_id, FEPHY_REG_ADDR_31, FEPHY_REG_PAGE_0);
+	if (ret != RTK_SUCCESS) {
+		RTK_LOGE(TAG, "Failed to select page 0. PHY(%d)", phy_id);
+		return ret;
+	}
+
+	/* Restart auto-negotiation */
+	ret = Ethernet_WritePhyReg(phy_id, FEPHY_REG_ADDR_0, EN_AUTO_GEN | RESTART_AUTO_GEN);
+	if (ret != RTK_SUCCESS) {
+		RTK_LOGE(TAG, "Failed to restart auto-negotiation. PHY(%d)", phy_id);
+		return ret;
+	}
+	return RTK_SUCCESS;
+}
+
+int PHY_SetMmdReg(uint8_t phy_id, uint8_t mmd_dev, uint16_t mmd_addr, uint16_t data)
+{
+	int ret = 0;
+
+	/* Select page 0 */
+	ret = Ethernet_WritePhyReg(phy_id, FEPHY_REG_ADDR_31, FEPHY_REG_PAGE_0);
+	if (ret != RTK_SUCCESS) {
+		RTK_LOGE(TAG, "Failed to select page 0. PHY(%d)", phy_id);
+		return ret;
+	}
+	/* Set address mode and select MMD device */
+	ret = Ethernet_WritePhyReg(phy_id, FEPHY_REG_ADDR_13, RTL8201FR_MACR_FUNC_ADDR(PHY_MMD_ADDR) | mmd_dev);
+	if (ret != RTK_SUCCESS) {
+		RTK_LOGE(TAG, "Failed to set address mode. PHY(%d), DEV(%d)", phy_id, mmd_dev);
+		return ret;
+	}
+	/* Write address value */
+	ret = Ethernet_WritePhyReg(phy_id, FEPHY_REG_ADDR_14, mmd_addr);
+	if (ret != RTK_SUCCESS) {
+		RTK_LOGE(TAG, "Failed to set MMD address. PHY(%d), ADDR(0x%X)", phy_id, mmd_addr);
+		return ret;
+	}
+	/* Set data mode and select MMD device */
+	ret = Ethernet_WritePhyReg(phy_id, FEPHY_REG_ADDR_13, RTL8201FR_MACR_FUNC_ADDR(PHY_MMD_DATA_NO_POST_INC) | mmd_dev);
+	if (ret != RTK_SUCCESS) {
+		RTK_LOGE(TAG, "Failed to set data mode. PHY(%d), DEV(%d)", phy_id, mmd_dev);
+		return ret;
+	}
+	/* Write data to MMD register */
+	ret = Ethernet_WritePhyReg(phy_id, FEPHY_REG_ADDR_14, data);
+	if (ret != RTK_SUCCESS) {
+		RTK_LOGE(TAG, "Failed to write data to MMD register. PHY(%d), DATA(0x%X)", phy_id, data);
+		return ret;
+	}
+	return RTK_SUCCESS;
+}
+
+int PHY_GetMmdReg(uint8_t phy_id, uint8_t mmd_dev, uint16_t mmd_addr, uint16_t *p_data)
+{
+	int ret = 0;
+	uint16_t data = 0;
+
+	/* Select page 0 */
+	ret = Ethernet_WritePhyReg(phy_id, FEPHY_REG_ADDR_31, FEPHY_REG_PAGE_0);
+	if (ret != RTK_SUCCESS) {
+		RTK_LOGE(TAG, "Failed to select page 0. PHY(%d)", phy_id);
+		return ret;
+	}
+	/* Set address mode and select MMD device */
+	ret = Ethernet_WritePhyReg(phy_id, FEPHY_REG_ADDR_13, RTL8201FR_MACR_FUNC_ADDR(PHY_MMD_ADDR) | mmd_dev);
+	if (ret != RTK_SUCCESS) {
+		RTK_LOGE(TAG, "Failed to set address mode. PHY(%d), DEV(%d)", phy_id, mmd_dev);
+		return ret;
+	}
+	/* Write address value */
+	ret = Ethernet_WritePhyReg(phy_id, FEPHY_REG_ADDR_14, mmd_addr);
+	if (ret != RTK_SUCCESS) {
+		RTK_LOGE(TAG, "Failed to set MMD address. PHY(%d), ADDR(0x%X)", phy_id, mmd_addr);
+		return ret;
+	}
+	/* Set data mode and select MMD device */
+	ret = Ethernet_WritePhyReg(phy_id, FEPHY_REG_ADDR_13, RTL8201FR_MACR_FUNC_ADDR(PHY_MMD_DATA_NO_POST_INC) | mmd_dev);
+	if (ret != RTK_SUCCESS) {
+		RTK_LOGE(TAG, "Failed to set data mode. PHY(%d), DEV(%d)", phy_id, mmd_dev);
+		return ret;
+	}
+	/* Read data from MMD register */
+	ret = Ethernet_ReadPhyReg(phy_id, FEPHY_REG_ADDR_14, &data);
+	if (ret != RTK_SUCCESS) {
+		RTK_LOGE(TAG, "Failed to read data from MMD register. PHY(%d)", phy_id);
+		return ret;
+	}
+
+	if (p_data) {
+		*p_data = data;
+	}
+	return RTK_SUCCESS;
+}
+
+int PHY_EnableEEE(uint8_t phy_id, u32 status)
+{
+	int ret = 0;
+
+	/* Reset PHY and select page 0 */
+	PHY_SoftWareReset(phy_id);
+
+	if (status != DISABLE) {
+		/* Enable 100BASE-TX EEE capability */
+		ret = PHY_SetMmdReg(phy_id, RTL8201FR_MMD_DEV_EEE_ADV, RTL8201FR_MMD_REG_EEEAR, RTL8201FR_EEEAR_100BT_EEE_ADV(1));
+		if (ret != RTK_SUCCESS) {
+			return ret;
+		}
+
+		/* Restart auto-negotiation */
+		ret = PHY_RestartAutoNego(phy_id);
+		if (ret != RTK_SUCCESS) {
+			return ret;
+		}
+	} else {
+		/* Disable 100BASE-TX EEE capability */
+		ret = PHY_SetMmdReg(phy_id, RTL8201FR_MMD_DEV_EEE_ADV, RTL8201FR_MMD_REG_EEEAR, RTL8201FR_EEEAR_100BT_EEE_ADV(0));
+		if (ret != RTK_SUCCESS) {
+			return ret;
+		}
+
+		/* Reset PHY, enable and restart auto-negotiation */
+		ret = Ethernet_WritePhyReg(phy_id, FEPHY_REG_ADDR_0, PHY_RESET | EN_AUTO_GEN | RESTART_AUTO_GEN);
+		if (ret != RTK_SUCCESS) {
+			return ret;
+		}
+		DelayMs(20);
+	}
+
+	return RTK_SUCCESS;
+}
+
+int PHY_SetEEEMode(uint8_t phy_id, uint8_t eth_mode)
+{
+	int ret = 0;
+
+	/* Reset PHY and select page 0 */
+	PHY_SoftWareReset(phy_id);
+
+	/* Select MAC/PHY mode configuration page */
+	ret = Ethernet_WritePhyReg(phy_id, FEPHY_REG_ADDR_31, RTL8211F_PHY_MODE_PAGE);
+	if (ret != RTK_SUCCESS) {
+		return ret;
+	}
+
+	if (eth_mode == ETH_MAC_MODE) {
+		ret = Ethernet_WritePhyReg(phy_id, RTL8211F_PHYCR2_ADDR, RTL8211F_PHCR2_MAC_MODE);
+		if (ret != RTK_SUCCESS) {
+			return ret;
+		}
+	} else {
+		ret = Ethernet_WritePhyReg(phy_id, RTL8211F_PHYCR2_ADDR, RTL8211F_PHCR2_PHY_MODE);
+		if (ret != RTK_SUCCESS) {
+			return ret;
+		}
+	}
+
+	return RTK_SUCCESS;
+}
+
+int PHY_SetRefclkDir(uint8_t phy_id, u32 mac_dir)
+{
+	int ret = 0;
+	uint16_t data = 0;
+
+	/* Select page 7 */
+	ret = Ethernet_WritePhyReg(phy_id, FEPHY_REG_ADDR_31, FEPHY_REG_PAGE_7);
+	if (ret != RTK_SUCCESS) {
+		return ret;
+	}
+
+	/* Read RMII mode register */
+	ret = Ethernet_ReadPhyReg(phy_id, RTL8201FR_PAGE7_REG_RMII_MODE_SET, &data);
+	if (ret != RTK_SUCCESS) {
+		return ret;
+	}
+
+	if (mac_dir == ETH_REFCLK_ON) {
+		data |= RTL8201FR_P7_16_RMII_CLK_DIR;
+	} else {
+		data &= ~RTL8201FR_P7_16_RMII_CLK_DIR;
+	}
+
+	/* Write clock direction configuration back */
+	ret = Ethernet_WritePhyReg(phy_id, RTL8201FR_PAGE7_REG_RMII_MODE_SET, data);
+	if (ret != RTK_SUCCESS) {
+		return ret;
+	}
+
+	return RTK_SUCCESS;
+}
diff --git a/ameba/amebaG2/source/fwlib/ram_km4tz/ameba_pmc.c b/ameba/amebag2/source/fwlib/ram_km4tz/ameba_pmc.c
similarity index 91%
rename from ameba/amebaG2/source/fwlib/ram_km4tz/ameba_pmc.c
rename to ameba/amebag2/source/fwlib/ram_km4tz/ameba_pmc.c
index 71320f89..309e39d6 100644
--- a/ameba/amebaG2/source/fwlib/ram_km4tz/ameba_pmc.c
+++ b/ameba/amebag2/source/fwlib/ram_km4tz/ameba_pmc.c
@@ -23,10 +23,10 @@ PMC_ENTRY_SECTION
 void PMC_ENTRY SOCPS_SleepInitEntry(struct PSCFG_TypeDef *ps_config)
 {
 	/*2. Clock configuration*/
-	SOCPS_ClockSourceConfig(ps_config->regu_state_in_sleep, ps_config->xtal_mode_in_sleep, ps_config->keep_osc4m_on_in_sleep);
+	SOCPS_ClockSourceConfig(ps_config->sleep_to_08V, ps_config->xtal_mode_in_sleep, ps_config->keep_osc4m_on);
 
 	/*3. Power settings*/
-	SOCPS_PowerManage(ps_config->regu_state_in_sleep);
+	SOCPS_PowerManage(ps_config->sleep_to_08V);
 
 	if (EFUSE_GetChipVersion() == SYSCFG_CUT_VERSION_A) {
 		/*Timing fix: Delay at least 1T before pulling down rst_n to avoid postsim bit errors.
diff --git a/ameba/common/CMakeLists.txt b/ameba/common/CMakeLists.txt
index 4a9540b9..68bed0f0 100644
--- a/ameba/common/CMakeLists.txt
+++ b/ameba/common/CMakeLists.txt
@@ -2,3 +2,6 @@
 # SPDX-License-Identifier: Apache-2.0
 
 zephyr_include_directories(include)
+add_subdirectory(os_wrapper)
+
+add_subdirectory_ifdef(CONFIG_REALTEK_AMEBA_ZEPHYR_WIFI wifi)
diff --git a/ameba/common/include/rtk_compiler.h b/ameba/common/include/rtk_compiler.h
index a89aa11a..30eac7a7 100644
--- a/ameba/common/include/rtk_compiler.h
+++ b/ameba/common/include/rtk_compiler.h
@@ -7,7 +7,9 @@
 #ifndef __RTK_COMPILER_H__
 #define __RTK_COMPILER_H__
 
+#ifdef __ZEPHYR__
 #include <zephyr/toolchain.h>
+#endif
 
 #define Compile_Assert(exp, str) extern char __ct_[(exp) ? 1 : -1]
 
diff --git a/ameba/usrcfg/amebaG2/CMakeLists.txt b/ameba/common/os_wrapper/CMakeLists.txt
similarity index 100%
rename from ameba/usrcfg/amebaG2/CMakeLists.txt
rename to ameba/common/os_wrapper/CMakeLists.txt
diff --git a/ameba/common/os_wrapper/include/os_wrapper.h b/ameba/common/os_wrapper/include/os_wrapper.h
new file mode 100644
index 00000000..52bce6ef
--- /dev/null
+++ b/ameba/common/os_wrapper/include/os_wrapper.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2024 Realtek Semiconductor Corp.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __OS_WRAPPER_H__
+#define __OS_WRAPPER_H__
+
+/**
+ * @brief  Necessary headers
+ */
+#include "platform_autoconf.h"
+#include <stdio.h>
+#include <string.h>
+#include <stdint.h>
+
+#include "ameba.h"
+#ifdef __ZEPHYR__
+#include <zephyr/kernel.h>
+#endif
+/**
+ * @brief  Common header file
+ */
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "os_wrapper_semaphore.h"
+#include "os_wrapper_critical.h"
+#include "os_wrapper_memory.h"
+#include "os_wrapper_mutex.h"
+#include "os_wrapper_queue.h"
+#include "os_wrapper_semaphore.h"
+#include "os_wrapper_task.h"
+#include "os_wrapper_time.h"
+#include "os_wrapper_timer.h"
+#ifdef __cplusplus
+}
+#endif
+
+/**
+ * @brief  General macro definition
+ */
+#define RTOS_MAX_DELAY    				0xFFFFFFFFUL
+#define RTOS_MAX_TIMEOUT    			0xFFFFFFFFUL
+
+#endif
diff --git a/ameba/common/os_wrapper/include/os_wrapper_critical.h b/ameba/common/os_wrapper/include/os_wrapper_critical.h
new file mode 100644
index 00000000..18209c16
--- /dev/null
+++ b/ameba/common/os_wrapper/include/os_wrapper_critical.h
@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2024 Realtek Semiconductor Corp.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __OS_WRAPPER_CRITCAL_H__
+#define __OS_WRAPPER_CRITCAL_H__
+
+/**
+ * Define CA32 SMP spin lock id
+ */
+typedef enum {
+	RTOS_CRITICAL_DEFAULT = 0,
+	RTOS_CRITICAL_SOC,
+	RTOS_CRITICAL_AUDIO,
+	RTOS_CRITICAL_WIFI,
+	RTOS_CRITICAL_NETWORK,
+	RTOS_CRITICAL_LWIP,
+	RTOS_CRITICAL_BT,
+	RTOS_CRITICAL_USB,
+	RTOS_CRITICAL_WPAN,
+	RTOS_CRITICAL_SEMA,
+	RTOS_CRITICAL_LOG,
+	RTOS_CRITICAL_MAX
+} RTOS_CRITICAL_LIST;
+
+/**
+ * @brief  Check if in task interrupt
+ * @retval 1: interrupt; 0: context
+ */
+int rtos_critical_is_in_interrupt(void);
+
+/**
+ * @brief  Internally handles interrupt status (PRIMASK/CPSR) save
+ */
+void rtos_critical_enter(uint32_t component_id);
+
+/**
+ * @brief  Internally handles interrupt status(PRIMASK/CPSR) restore
+ */
+void rtos_critical_exit(uint32_t component_id);
+
+/**
+ * @brief  get task enter critical state
+ * @retval >0: in critical state; 0: exit critical state
+ */
+uint32_t rtos_get_critical_state(void);
+#endif
diff --git a/ameba/common/os_wrapper/include/os_wrapper_memory.h b/ameba/common/os_wrapper/include/os_wrapper_memory.h
new file mode 100644
index 00000000..f52f2e03
--- /dev/null
+++ b/ameba/common/os_wrapper/include/os_wrapper_memory.h
@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2024 Realtek Semiconductor Corp.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __OS_WRAPPER_MEMORY_H__
+#define __OS_WRAPPER_MEMORY_H__
+
+/**
+ * @brief  Initialize dynamic memory pool
+ */
+void rtos_mem_init(void);
+
+/**
+ * @brief  Allocate memory from the heap. The buffer value is random
+ * @note   The return buffer size/address is cacheline size aligned
+ * @param  size: buffer size in byte
+ * @retval Pointer to memory the caller can now use
+ */
+void *rtos_mem_malloc(uint32_t size);
+
+/**
+ * @brief  Allocate memory from the heap. The buffer value is zero
+ * @note   The return buffer size/address is cacheline size aligned
+ * @param  size: buffer size in byte
+ * @retval Pointer to memory the caller can now use
+ */
+void *rtos_mem_zmalloc(uint32_t size);
+
+/**
+ * @brief  Allocate memory from the heap. The buffer value is zero
+ * @note   The return buffer size/address is cacheline size aligned
+ * @param  elementNum:  Number of elements, memory size is elementNum*elementSize
+ * @param  elementSize: Size of each array element (in bytes).
+ * @retval Pointer to memory the caller can now use
+ */
+void *rtos_mem_calloc(uint32_t elementNum, uint32_t elementSize);
+
+/**
+ * @brief  Reuse or extend memory previously allocated by the malloc(), calloc(), and realloc()
+ * functions
+ * @note   The return buffer size/address is cacheline size aligned
+ * @param  pbuf: Pointer containing the address
+ * @param  size: The number of bytes of memory to be newly allocated.
+ * @retval Pointer to memory the caller can now use
+ */
+void *rtos_mem_realloc(void *pbuf, uint32_t size);
+
+/**
+ * @brief  Deallocate memory from the heap.
+ * @param  pbuf: a pointer to memory previously allocated
+ */
+void rtos_mem_free(void *pbuf);
+
+/**
+ * @brief  Get free heap size.
+ * @retval Free heap size in byte
+ */
+uint32_t rtos_mem_get_free_heap_size(void);
+
+/**
+ * @brief  Get minimum ever free heap size.
+ * @retval Minimum ever free heap size in byte
+ */
+uint32_t rtos_mem_get_minimum_ever_free_heap_size(void);
+
+#endif
diff --git a/ameba/common/os_wrapper/include/os_wrapper_mutex.h b/ameba/common/os_wrapper/include/os_wrapper_mutex.h
new file mode 100644
index 00000000..10af266a
--- /dev/null
+++ b/ameba/common/os_wrapper/include/os_wrapper_mutex.h
@@ -0,0 +1,136 @@
+/*
+ * Copyright (c) 2024 Realtek Semiconductor Corp.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __OS_WRAPPER_MUTEX_H__
+#define __OS_WRAPPER_MUTEX_H__
+
+/**
+ * @brief  mutex handle type
+ */
+typedef void *rtos_mutex_t;
+
+#define MUTEX_WAIT_TIMEOUT 0xFFFFFFFFU /* will be replaced by common max timeout later */
+
+/**
+ * @brief  Static memory allocation implementation of rtos_mutex_create
+ * @param  pp_handle: The handle itself is a pointer, and the pp_handle means a pointer to
+ *                    the handle.
+ * @retval The status is RTK_SUCCESS or RTK_FAIL
+ */
+int rtos_mutex_create_static(rtos_mutex_t *pp_handle);
+
+/**
+ * @brief  Static memory allocation implementation of rtos_mutex_delete
+ * @param  p_handle: Address of the mutex
+ * @retval The status is RTK_SUCCESS or RTK_FAIL
+ */
+int rtos_mutex_delete_static(rtos_mutex_t p_handle);
+
+/**
+ * @brief  Static memory allocation implementation of rtos_mutex_recursive_create
+ * @param  pp_handle: The handle itself is a pointer, and the pp_handle means a pointer to
+ *                    the handle.
+ * @retval The status is RTK_SUCCESS or RTK_FAIL
+ */
+int rtos_mutex_recursive_create_static(rtos_mutex_t *pp_handle);
+
+/**
+ * @brief  Static memory allocation implementation of rtos_mutex_recursive_delete
+ * @param  p_handle: Address of the mutex
+ * @retval The status is RTK_SUCCESS or RTK_FAIL
+ */
+int rtos_mutex_recursive_delete_static(rtos_mutex_t p_handle);
+
+/**
+ * @brief  Compared to semaphores, Mutex has a priority inheritance mechanism.
+ *         Dynamic allocate memory.
+ * @note   Usage example:
+ * Create:
+ *          rtos_mutex_t mutex_handle;
+ *          rtos_mutex_create(&mutex_handle);
+ * Give:
+ *          rtos_mutex_give(mutex_handle);
+ * Take:
+ *          rtos_mutex_take(mutex_handle, 100);
+ * Delete:
+ *          rtos_mutex_delete(mutex_handle);
+ * @param  pp_handle: The handle itself is a pointer, and the pp_handle means a pointer to
+ *                    the handle.
+ * @retval The status is RTK_SUCCESS or RTK_FAIL
+ */
+int rtos_mutex_create(rtos_mutex_t *pp_handle);
+
+/**
+ * @brief  Delete a mutex.
+ * @note   Do not delete mutex if held by a task
+ * @param  p_handle: Address of the mutex
+ * @retval The status is RTK_SUCCESS or RTK_FAIL
+ */
+int rtos_mutex_delete(rtos_mutex_t p_handle);
+
+/**
+ * @brief  Take a mutex. The API internally determines whether it is in the interrupt state and
+ *         calls the corresponding RTOS interface.
+ * @param  p_handle: Address of the mutex
+ * @param  wait_ms: The time in milliseconds to wait, 0xFFFFFFFF means Block infinitely until
+ *                  the semaphore taken.
+ * @retval The status is RTK_SUCCESS or RTK_FAIL
+ */
+int rtos_mutex_take(rtos_mutex_t p_handle, uint32_t wait_ms);
+
+/**
+ * @brief  Give a semaphore. The API internally determines whether it is in the interrupt state and
+ *         calls the corresponding RTOS interface.
+ * @param  p_handle: Address of the mutex
+ * @retval The status is RTK_SUCCESS or RTK_FAIL
+ */
+int rtos_mutex_give(rtos_mutex_t p_handle);
+
+/**
+ * @brief  Creates a new recursive mutex, compared to semaphores, Mutex has a priority
+ *         inheritance mechanism. Dynamic allocate memory.
+ * @note   Usage example:
+ * Create:
+ *          rtos_mutex_t mutex_handle;
+ *          rtos_mutex_recursive_create(&mutex_handle);
+ * Give:
+ *          rtos_mutex_recursive_give(mutex_handle);
+ * Take:
+ *          rtos_mutex_recursive_take(mutex_handle, 100);
+ * Delete:
+ *          rtos_mutex_recursive_delete(mutex_handle);
+ * @param  pp_handle: The handle itself is a pointer, and the pp_handle means a pointer to
+ *                    the handle.
+ * @retval The status is RTK_SUCCESS or RTK_FAIL
+ */
+int rtos_mutex_recursive_create(rtos_mutex_t *pp_handle);
+
+/**
+ * @brief  Delete a mutex.
+ * @param  p_handle: Address of the mutex
+ * @retval The status is RTK_SUCCESS or RTK_FAIL
+ */
+int rtos_mutex_recursive_delete(rtos_mutex_t p_handle);
+
+/**
+ * @brief  Take a mutex.
+ * @note   recursive mutexes cannot be used in interrupt service routines.
+ * @param  p_handle: Address of the mutex
+ * @param  wait_ms: The time in milliseconds to wait, 0xFFFFFFFF means Block infinitely until
+ *                  the semaphore taken.
+ * @retval The status is RTK_SUCCESS or RTK_FAIL
+ */
+int rtos_mutex_recursive_take(rtos_mutex_t p_handle, uint32_t wait_ms);
+
+/**
+ * @brief  Give a semaphore.
+ * @note   Recursive mutexes cannot be used in interrupt service routines.
+ * @param  p_handle: Address of the mutex
+ * @retval The status is RTK_SUCCESS or RTK_FAIL
+ */
+int rtos_mutex_recursive_give(rtos_mutex_t p_handle);
+
+#endif
diff --git a/ameba/common/os_wrapper/include/os_wrapper_queue.h b/ameba/common/os_wrapper/include/os_wrapper_queue.h
new file mode 100644
index 00000000..1bf07487
--- /dev/null
+++ b/ameba/common/os_wrapper/include/os_wrapper_queue.h
@@ -0,0 +1,90 @@
+/*
+ * Copyright (c) 2024 Realtek Semiconductor Corp.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __OS_WRAPPER_QUEUE_H__
+#define __OS_WRAPPER_QUEUE_H__
+
+/**
+ * @brief  queue handle type
+ */
+typedef void *rtos_queue_t;
+
+/**
+ * @brief  Creates a new queue instance
+ * @note   Usage example:
+ * Create:
+ *          rtos_queue_t queue_handle;
+ *          rtos_queue_create(&queue_handle, 5, sizeof(uint32_t));
+ * Send:
+ *          rtos_queue_send(queue_handle, p_msg, RTOS_MAX_DELAY);
+ * Receive:
+ *          rtos_queue_receive(queue_handle, p_msg, RTOS_MAX_DELAY);
+ * Delete:
+ *          rtos_queue_delete(queue_handle);
+ * @param  pp_handle: The handle itself is a pointer, and the pp_handle means a pointer to
+ *                    the handle.
+ * @param  msg_num:  Maximum number of messages that can be queued.
+ * @param  msg_size: Message size (in bytes).
+ * @retval The status is RTK_SUCCESS or RTK_FAIL
+ */
+int rtos_queue_create(rtos_queue_t *pp_handle, uint32_t msg_num, uint32_t msg_size);
+
+/**
+ * @brief  Delete a queue - freeing all the memory allocated for storing of items placed on
+ *         the queue.
+ * @param  p_handle: A handle to the queue to be deleted.
+ * @retval The status is RTK_SUCCESS or RTK_FAIL
+ */
+int rtos_queue_delete(rtos_queue_t p_handle);
+
+/**
+ * @brief  Return the number of messages stored in a queue.
+ * @param  p_handle: A handle to the queue being queried.
+ * @retval The number of messages available in the queue.
+ */
+uint32_t rtos_queue_message_waiting(rtos_queue_t p_handle);
+
+/**
+ * @brief  Send a message to a message queue in a "first in, first out" manner.
+ * @param  p_handle: Address of the message queue.
+ * @param  p_msg: Pointer to the message.
+ * @param  wait_ms: Waiting period to add the message, 0xFFFFFFFF means Block infinitely.
+ * @retval The status is RTK_SUCCESS or RTK_FAIL
+ */
+int rtos_queue_send(rtos_queue_t p_handle, void *p_msg, uint32_t wait_ms);
+
+/**
+ * @brief  Send a message to the head of message queue in a "last in, first out" manner.
+ * @param  p_handle: Address of the message queue.
+ * @param  p_msg: Pointer to the message.
+ * @param  wait_ms: Waiting period to add the message, 0xFFFFFFFF means Block infinitely.
+ * @retval The status is RTK_SUCCESS or RTK_FAIL
+ */
+int rtos_queue_send_to_front(rtos_queue_t p_handle, void *p_msg, uint32_t wait_ms);
+
+/**
+ * @brief  Receive a message from a message queue in a "first in, first out" manner.
+ *         Messages are received from the queue and removed from the queue, so the queue's
+ *         state changes.
+ * @param  p_handle: Address of the message queue.
+ * @param  p_msg: Address of area to hold the received message.
+ * @param  wait_ms: Waiting period to add the message, 0xFFFFFFFF means Block infinitely.
+ * @retval The status is RTK_SUCCESS or RTK_FAIL
+ */
+int rtos_queue_receive(rtos_queue_t p_handle, void *p_msg, uint32_t wait_ms);
+
+/**
+ * @brief  Peek/read a message from a message queue in a "first in, first out" manner.
+ *         Simply viewing the next message in the queue does not remove it from the queue,
+ *         so the state of the queue remains unchanged.
+ * @param  p_handle: Address of the message queue.
+ * @param  p_msg: Address of area to hold the received message.
+ * @param  wait_ms: Waiting period to add the message, 0xFFFFFFFF means Block infinitely.
+ * @retval The status is RTK_SUCCESS or RTK_FAIL
+ */
+int rtos_queue_peek(rtos_queue_t p_handle, void *p_msg, uint32_t wait_ms);
+
+#endif
diff --git a/ameba/common/os_wrapper/include/os_wrapper_semaphore.h b/ameba/common/os_wrapper/include/os_wrapper_semaphore.h
new file mode 100644
index 00000000..a9f999fb
--- /dev/null
+++ b/ameba/common/os_wrapper/include/os_wrapper_semaphore.h
@@ -0,0 +1,119 @@
+/*
+ * Copyright (c) 2024 Realtek Semiconductor Corp.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __OS_WRAPPER_SEMA_H__
+#define __OS_WRAPPER_SEMA_H__
+
+#define RTOS_SEMA_MIN_COUNT 0x0UL
+#define RTOS_SEMA_MAX_COUNT 0xFFFFFFFFUL
+
+/**
+ * @brief  semaphore handle type
+ */
+typedef void *rtos_sema_t;
+
+/**
+ * @brief  Static memory allocation implementation of rtos_sema_create
+ * @param  pp_handle: The handle itself is a pointer, and the pp_handle means a pointer to
+ *                    the handle.
+ * @param  init_count: The count value assigned to the semaphore when it is created.
+ * @param  max_count:  The maximum count value that can be reached.
+ * @retval The status is RTK_SUCCESS or RTK_FAIL
+ */
+int rtos_sema_create_static(rtos_sema_t *pp_handle, uint32_t init_count, uint32_t max_count);
+
+/**
+ * @brief  Static memory allocation implementation of rtos_sema_create_binary
+ * @param  pp_handle: The handle itself is a pointer, and the pp_handle means a pointer to
+ *                    the handle.
+ * @retval The status is RTK_SUCCESS or RTK_FAIL
+ */
+int rtos_sema_create_binary_static(rtos_sema_t *pp_handle);
+
+/**
+ * @brief  Static memory allocation implementation of rtos_sema_delete
+ * @param  p_handle: Address of the semaphore
+ * @retval The status is RTK_SUCCESS or RTK_FAIL
+ */
+int rtos_sema_delete_static(rtos_sema_t p_handle);
+
+/**
+ * @brief  Creates a new counting semaphore instance
+ *         Dynamic allocate memory.
+ * @note   Usage example:
+ * Create:
+ *          rtos_sema_t sema_handle;
+ *          rtos_sema_create(&sema_handle, 0, 10);
+ * Give:
+ *          rtos_sema_give(sema_handle);
+ * Take:
+ *          rtos_sema_take(sema_handle, 100);
+ * Delete:
+ *          rtos_sema_delete(sema_handle);
+ * @param  pp_handle: The handle itself is a pointer, and the pp_handle means a pointer to
+ *                    the handle.
+ * @param  init_count: The count value assigned to the semaphore when it is created.
+ * @param  max_count:  The maximum count value that can be reached.
+ * @retval The status is RTK_SUCCESS or RTK_FAIL
+ */
+int rtos_sema_create(rtos_sema_t *pp_handle, uint32_t init_count, uint32_t max_count);
+
+/**
+ * @brief  Creates a new binary semaphore instance
+ *         Dynamic allocate memory.
+ * @note   The semaphore must first be 'given' before it can be 'taken'.
+ * Usage example:
+ * Create:
+ *          rtos_sema_t sema_handle;
+ *          rtos_sema_create_binary(&sema_handle);
+ * Give:
+ *          rtos_sema_give(sema_handle);
+ * Take:
+ *          rtos_sema_take(sema_handle, 100);
+ * Delete:
+ *          rtos_sema_delete(sema_handle);
+ * @param  pp_handle: The handle itself is a pointer, and the pp_handle means a pointer to
+ *                    the handle.
+ * @retval The status is RTK_SUCCESS or RTK_FAIL
+ */
+int rtos_sema_create_binary(rtos_sema_t *pp_handle);
+
+/**
+ * @brief  Delete a semaphore.
+ * @param  p_handle: A handle to the semaphore to be deleted.
+ * @retval The status is RTK_SUCCESS or RTK_FAIL
+ */
+int rtos_sema_delete(rtos_sema_t p_handle);
+
+/**
+ * @brief  Take a semaphore. The API internally determines whether it is in the interrupt state and
+ *         calls the corresponding RTOS interface.
+ *
+ * @note   If timeout_ms is set to the maximum value, then if the semaphore cannot be obtained
+ *         consistently, the log will be printed every 10 seconds.
+ * @param  p_handle: Address of the semaphore.
+ * @param  timeout_ms: Waiting period to add the message, 0xFFFFFFFF means Block infinitely.
+ * @retval The status is RTK_SUCCESS or RTK_FAIL
+ */
+int rtos_sema_take(rtos_sema_t p_handle, uint32_t timeout_ms);
+
+/**
+ * @brief  Give a semaphore. The API internally determines whether it is in the interrupt state and
+ *         calls the corresponding RTOS interface.
+ * @param  p_handle: Address of the semaphore.
+ * @retval The status is RTK_SUCCESS or RTK_FAIL
+ */
+int rtos_sema_give(rtos_sema_t p_handle);
+
+/**
+ * @brief  Get a semaphore's count. If the semaphore is a binary semaphore then returns 1 if
+ *         the semaphore is available, and 0 if the semaphore is not available.
+ * @param  p_handle: Address of the semaphore.
+ * @retval Current semaphore count.
+ */
+uint32_t rtos_sema_get_count(rtos_sema_t p_handle);
+
+#endif
diff --git a/ameba/common/os_wrapper/include/os_wrapper_specific.h b/ameba/common/os_wrapper/include/os_wrapper_specific.h
new file mode 100644
index 00000000..33b9acb5
--- /dev/null
+++ b/ameba/common/os_wrapper/include/os_wrapper_specific.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2024 Realtek Semiconductor Corp.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __OS_WRAPPER_SPECIFIC_H__
+#define __OS_WRAPPER_SPECIFIC_H__
+
+#define RTOS_CONVERT_MS_TO_TICKS(MS) k_ms_to_cyc_floor32(MS)
+
+#endif
diff --git a/ameba/common/os_wrapper/include/os_wrapper_task.h b/ameba/common/os_wrapper/include/os_wrapper_task.h
new file mode 100644
index 00000000..9fb55792
--- /dev/null
+++ b/ameba/common/os_wrapper/include/os_wrapper_task.h
@@ -0,0 +1,139 @@
+/*
+ * Copyright (c) 2024 Realtek Semiconductor Corp.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __OS_WRAPPER_TASK_H__
+#define __OS_WRAPPER_TASK_H__
+
+/* CONFIG_NUM_COOP_PRIORITIES shall be 0 */
+#define RTOS_TASK_MAX_PRIORITIES       (CONFIG_NUM_PREEMPT_PRIORITIES)
+#define RTOS_MINIMAL_STACK_SIZE        (1024)
+#define RTOS_MINIMAL_SECURE_STACK_SIZE (1024)
+
+#define RTOS_SCHED_SUSPENDED   0x0UL
+#define RTOS_SCHED_NOT_STARTED 0x1UL
+#define RTOS_SCHED_RUNNING     0x2UL
+
+/**
+ * @brief  task handle and function type
+ */
+typedef void *rtos_task_t;
+typedef void (*rtos_task_function_t)(void *);
+
+/**
+ * @brief  Start os kernel scheduler
+ * @retval return RTK_SUCCESS Only
+ */
+int rtos_sched_start(void);
+
+/**
+ * @brief  Stop os kernel scheduler
+ * @retval RTK_SUCCESS(0) / RTK_FAIL(-1)
+ */
+int rtos_sched_stop(void);
+
+/**
+ * @brief  Suspend os kernel scheduler
+ * @retval RTK_SUCCESS(0) / RTK_FAIL(-1)
+ */
+int rtos_sched_suspend(void);
+
+/**
+ * @brief  Resume os kernel scheduler
+ * @retval RTK_SUCCESS(0) / RTK_FAIL(-1)
+ */
+int rtos_sched_resume(void);
+
+/**
+ * @brief  Get scheduler status.
+ * @retval RTOS_SCHED_SUSPENDED / RTOS_SCHED_NOT_STARTED / RTOS_SCHED_RUNNING
+ */
+int rtos_sched_get_state(void);
+
+/**
+ * @brief  Create os level task routine.
+ * @note   Usage example:
+ * Create:
+ *          rtos_task_t handle;
+ *          rtos_task_create(&handle, "test_task", task, NULL, 1024, 2);
+ * Suspend:
+ *          rtos_task_suspend(handle);
+ * Resume:
+ *          rtos_task_resume(handle);
+ * Delete:
+ *          rtos_task_delete(handle);
+ * @param  pp_handle: The handle itself is a pointer, and the pp_handle means a pointer to
+ *                    the handle.
+ * @param  p_name: A descriptive name for the task.
+ * @param  p_routine: Pointer to the task entry function. Tasks must be implemented to never return
+ *                    (i.e. continuous loop).
+ * @param  p_param: Pointer that will be used as the parameter
+ * @param  stack_size_in_byte: The size of the task stack specified
+ * @param  priority: The priority at which the task should run (higher value, higher priority)
+ * @retval RTK_SUCCESS(0) / RTK_FAIL(-1)
+ */
+int rtos_task_create(rtos_task_t *pp_handle, const char *p_name, rtos_task_function_t p_routine,
+					 void *p_param, uint16_t stack_size_in_byte, uint16_t priority);
+
+/**
+ * @brief  Delete os level task routine.
+ * @param  p_handle: Task handle. If a null pointer is passed, the task itself is deleted.
+ * @retval RTK_SUCCESS(0) / RTK_FAIL(-1)
+ */
+int rtos_task_delete(rtos_task_t p_handle);
+
+/**
+ * @brief  Suspend os level task routine.
+ * @param  p_handle: Task handle.
+ * @retval RTK_SUCCESS(0) / RTK_FAIL(-1)
+ */
+int rtos_task_suspend(rtos_task_t p_handle);
+
+/**
+ * @brief  Resume os level task routine.
+ * @param  p_handle: Task handle.
+ * @retval RTK_SUCCESS(0) / RTK_FAIL(-1)
+ */
+int rtos_task_resume(rtos_task_t p_handle);
+
+/**
+ * @brief  Yield current os level task routine.
+ * @retval RTK_SUCCESS(0) / RTK_FAIL(-1)
+ */
+int rtos_task_yield(void);
+
+/**
+ * @brief  Get current os level task routine handle.
+ * @retval The task handle pointer
+ */
+rtos_task_t rtos_task_handle_get(void);
+
+/**
+ * @brief  Get os level task routine priority.
+ * @param  p_handle: Task handle.
+ * @retval Task priority value
+ */
+uint32_t rtos_task_priority_get(rtos_task_t p_handle);
+
+/**
+ * @brief  Set os level task routine priority.
+ * @param  p_handle: Task handle.
+ * @param  priority: The priority at which the task should run (higher value, higher priority)
+ * @retval RTK_SUCCESS(0) / RTK_FAIL(-1)
+ */
+int rtos_task_priority_set(rtos_task_t p_handle, uint16_t priority);
+
+/**
+ * @brief  Print current task status
+ */
+void rtos_task_out_current_status(void);
+
+/**
+ * @brief  Allocate a secure context for the task.
+ * @note   trustzone is required. Otherwise it's just an empty implementation.
+ */
+void rtos_create_secure_context(uint32_t size);
+
+#endif
diff --git a/ameba/common/os_wrapper/include/os_wrapper_time.h b/ameba/common/os_wrapper/include/os_wrapper_time.h
new file mode 100644
index 00000000..f70310e2
--- /dev/null
+++ b/ameba/common/os_wrapper/include/os_wrapper_time.h
@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2024 Realtek Semiconductor Corp.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __OS_WRAPPER_TIME_H__
+#define __OS_WRAPPER_TIME_H__
+
+#define RTOS_TICK_RATE_HZ 1000UL
+#define RTOS_TICK_RATE_MS (1000UL / RTOS_TICK_RATE_HZ)
+
+#define RTOS_TIME_GET_PASSING_TIME_MS(start) (rtos_time_get_current_system_time_ms() - (start))
+
+#define RTOS_TIME_GET_TIME_INTERVAL_MS(start, end) ((end) - (start))
+#define RTOS_TIME_SET_MS_TO_SYSTIME(time)          (time / RTOS_TICK_RATE_MS)
+
+/**
+ * @brief  If the current system is in a scheduling and non-interrupted state, it will switch to
+ *         other tasks. Otherwise, the nop instruction will be executed.
+ * @param  ms: Delay time in milliseconds
+ */
+void rtos_time_delay_ms(uint32_t ms);
+
+/**
+ * @brief  The system will execute the nop instruction without scheduling.
+ * @param  us: Delay time in microseconds
+ */
+void rtos_time_delay_us(uint32_t us);
+
+/**
+ * @brief  Get the count of ticks since rtos_sched_start was called, and convert the return value
+ *         to milliseconds.
+ * @note   This interface does not consider systick overflow issues.
+ */
+uint32_t rtos_time_get_current_system_time_ms(void);
+
+/**
+ * @brief  Return value to in microseconds.
+ * @note   This interface does not consider systick overflow issues.
+ */
+uint64_t rtos_time_get_current_system_time_us(void);
+
+/**
+ * @brief  Return value to in nanoseconds.
+ * @note   This interface does not consider systick overflow issues. The accuracy is the clk
+ *         frequency of the CPU
+ */
+uint64_t rtos_time_get_current_system_time_ns(void);
+
+/**
+ * @brief  Get the count of pended ticks since rtos_sched_suspend was called, and convert the
+ *         return value to milliseconds.
+ */
+uint32_t rtos_time_get_current_pended_time_ms(void);
+
+#endif
diff --git a/ameba/common/os_wrapper/include/os_wrapper_timer.h b/ameba/common/os_wrapper/include/os_wrapper_timer.h
new file mode 100644
index 00000000..0dc6913a
--- /dev/null
+++ b/ameba/common/os_wrapper/include/os_wrapper_timer.h
@@ -0,0 +1,128 @@
+/*
+ * Copyright (c) 2024 Realtek Semiconductor Corp.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __OS_WRAPPER_TIMER_H__
+#define __OS_WRAPPER_TIMER_H__
+
+#define RTOS_TIMER_MAX_DELAY 0xFFFFFFFFUL
+
+/**
+ * @brief  timer handle type
+ */
+typedef void *rtos_timer_t;
+
+/**
+ * @brief  Static memory allocation implementation of rtos_timer_create
+ * @param  pp_handle: The handle itself is a pointer, and the pp_handle means a pointer to
+ *                    the handle.
+ * @param  p_timer_name: A descriptive name for the timer.
+ * @param  timer_id: An identifier that is assigned to the timer being created. Typically this
+ *                   would be used in the timer callback function to identify which timer expired
+ *                   when the same callback function is assigned to more than one timer.
+ * @param  interval_ms: The timer period in milliseconds.
+ * @param  reload: Used to set the timer as a periodic or one-shot timer.
+ * @param  p_timer_callback: The function to call when the timer expires.
+ * @retval The status is RTK_SUCCESS or RTK_FAIL
+ */
+int rtos_timer_create_static(rtos_timer_t *pp_handle, const char *p_timer_name, uint32_t timer_id,
+							 uint32_t interval_ms, uint8_t reload,
+							 void (*p_timer_callback)(void *));
+
+/**
+ * @brief  Static memory allocation implementation of rtos_timer_delete
+ * @param  p_handle: The handle of the timer being deleted.
+ * @param  wait_ms: Specifies the time that the calling task should be held in the Blocked state to
+ *                  wait for the delete command to be successfully sent to the timer command queue.
+ * @retval The status is RTK_SUCCESS or RTK_FAIL
+ */
+int rtos_timer_delete_static(rtos_timer_t p_handle, uint32_t wait_ms);
+
+/**
+ * @brief  Create a new software timer instance. This allocates the storage required by the new
+ *         timer, initializes the new timers internal state, and returns a handle by which the new
+ *         timer can be referenced.
+ * @note   Usage example:
+ * Create:
+ *          rtos_timer_t timer_handle;
+ *          rtos_timer_create(&timer_handle, "timer_test", timer_id, delay_ms, is_reload,
+ *                            timer_cb_function);
+ * Start:
+ *          rtos_timer_start(timer_handle, wait_ms);
+ * Stop:
+ *          rtos_timer_stop(timer_handle, wait_ms);
+ * Delete:
+ *          rtos_timer_delete(timer_handle, wait_ms);
+ * @param  pp_handle: The handle itself is a pointer, and the pp_handle means a pointer to
+ *                    the handle.
+ * @param  p_timer_name: A descriptive name for the timer.
+ * @param  timer_id: An identifier that is assigned to the timer being created. Typically this
+ *                   would be used in the timer callback function to identify which timer expired
+ *                   when the same callback function is assigned to more than one timer.
+ * @param  interval_ms: The timer period in milliseconds.
+ * @param  reload: Used to set the timer as a periodic or one-shot timer.
+ * @param  p_timer_callback: The function to call when the timer expires.
+ * @retval The status is RTK_SUCCESS or RTK_FAIL
+ */
+int rtos_timer_create(rtos_timer_t *pp_handle, const char *p_timer_name, uint32_t timer_id,
+					  uint32_t interval_ms, uint8_t reload, void (*p_timer_callback)(void *));
+
+/**
+ * @brief  Delete a timer that was previously created using a call to rtos_timer_create.
+ * @param  p_handle: The handle of the timer being deleted.
+ * @param  wait_ms: Specifies the time that the calling task should be held in the Blocked state to
+ *                  wait for the delete command to be successfully sent to the timer command queue.
+ * @retval The status is RTK_SUCCESS or RTK_FAIL
+ */
+int rtos_timer_delete(rtos_timer_t p_handle, uint32_t wait_ms);
+
+/**
+ * @brief  Start a timer that was previously created using a call to rtos_timer_create.
+ * @param  p_handle: The handle of the created timer
+ * @param  wait_ms: Specifies the time that the calling task should be held in the Blocked state to
+ *                  wait for the start command to be successfully sent to the timer command queue.
+ * @retval The status is RTK_SUCCESS or RTK_FAIL
+ */
+int rtos_timer_start(rtos_timer_t p_handle, uint32_t wait_ms);
+
+/**
+ * @brief  Stopping a timer ensures the timer is not in the active state.
+ * @param  p_handle: The handle of the created timer
+ * @param  wait_ms: Specifies the time that the calling task should be held in the Blocked state
+ *                  to wait for the stop command to be successfully sent to the timer command queue.
+ * @retval The status is RTK_SUCCESS or RTK_FAIL
+ */
+int rtos_timer_stop(rtos_timer_t p_handle, uint32_t wait_ms);
+
+/**
+ * @brief  changes the period of a timer that was previously created using a call
+ *         to rtos_timer_create.
+ * @param  p_handle: The handle of the created timer
+ * @param  interval_ms: The new period for the timer.
+ * @param  wait_ms: Specifies the time that the calling task should be held in the Blocked state to
+ *                  wait for the change command to be successfully sent to the timer command queue.
+ * @retval The status is RTK_SUCCESS or RTK_FAIL
+ */
+int rtos_timer_change_period(rtos_timer_t p_handle, uint32_t interval_ms, uint32_t wait_ms);
+
+/**
+ * @brief  Queries a timer to see if it is active or dormant. A timer will be dormant if:
+ *         1) It has been created but not started, or
+ *         2) It is an expired one-shot timer that has not been restarted.
+ * @note   non-interrupt safety
+ * @param  p_handle: The handle of the created timer
+ * @retval Timer is active or not.
+ */
+uint32_t rtos_timer_is_timer_active(rtos_timer_t p_handle);
+
+/**
+ * @brief  Get the ID assigned to the timer when created.
+ * @note   non-interrupt safety
+ * @param  p_handle: Pointer to the created timer handle.
+ * @retval the ID assigned to the timer.
+ */
+uint32_t rtos_timer_get_id(rtos_timer_t p_handle);
+
+#endif
diff --git a/ameba/common/os_wrapper/include/platform_stdlib.h b/ameba/common/os_wrapper/include/platform_stdlib.h
new file mode 100644
index 00000000..84f34943
--- /dev/null
+++ b/ameba/common/os_wrapper/include/platform_stdlib.h
@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2024 Realtek Semiconductor Corp.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __PLATFORM_STDLIB_H__
+#define __PLATFORM_STDLIB_H__
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <stdint.h>
+#include <stdarg.h> /* va_list */
+
+#endif
diff --git a/ameba/common/wifi/CMakeLists.txt b/ameba/common/wifi/CMakeLists.txt
new file mode 100644
index 00000000..91d50b99
--- /dev/null
+++ b/ameba/common/wifi/CMakeLists.txt
@@ -0,0 +1,8 @@
+# Copyright (c) 2024 Realtek Semiconductor Corp.
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_include_directories(source)
+zephyr_include_directories(../../usrcfg/common)
+
+zephyr_library_sources_ifdef(CONFIG_WIFI source/wifi_feature_dis_antdiv.c)
+zephyr_library_sources_ifdef(CONFIG_WIFI source/wifi_init_zephyr.c)
diff --git a/ameba/common/wifi/Kconfig b/ameba/common/wifi/Kconfig
new file mode 100644
index 00000000..27f4f9c0
--- /dev/null
+++ b/ameba/common/wifi/Kconfig
@@ -0,0 +1,21 @@
+# Copyright (c) 2024 Realtek Semiconductor Corp.
+# SPDX-License-Identifier: Apache-2.0
+
+config REALTEK_AMEBA_ZEPHYR_WIFI
+	bool "RealTek Ameba Zephyr WIFI"
+	default y
+	help
+	  This option enables the Realtek Ameba WIFI.
+
+if REALTEK_AMEBA_ZEPHYR_WIFI
+config WLAN
+	bool "enable wifi"
+	default y
+
+config AS_INIC_AP
+	bool
+
+config SINGLE_CORE_WIFI
+	bool
+
+endif # REALTEK_AMEBA_ZEPHYR_WIFI
diff --git a/ameba/common/wifi/source/rtw_autoconf.h b/ameba/common/wifi/source/rtw_autoconf.h
new file mode 100644
index 00000000..8d3f3e48
--- /dev/null
+++ b/ameba/common/wifi/source/rtw_autoconf.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2024 Realtek Semiconductor Corp.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef WLANCONFIG_H
+#define WLANCONFIG_H
+
+/*
+ * Include user defined options first. Anything not defined in these files
+ * will be set to standard values. Override anything you dont like!
+ */
+#include "platform_autoconf.h"
+
+#ifndef CONFIG_LITTLE_ENDIAN
+#define CONFIG_LITTLE_ENDIAN
+#endif
+
+#define WIFI_LOGO_CERTIFICATION 0
+
+#define MACID_HW_MAX_NUM 16
+#define NET_IF_NUM 2
+
+#endif //WLANCONFIG_H
diff --git a/ameba/common/wifi/source/rtw_wifi_defs.h b/ameba/common/wifi/source/rtw_wifi_defs.h
new file mode 100644
index 00000000..bb1decc1
--- /dev/null
+++ b/ameba/common/wifi/source/rtw_wifi_defs.h
@@ -0,0 +1,688 @@
+/*
+ * Copyright (c) 2024 Realtek Semiconductor Corp.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef	__RTW_WIFI_DEFS_H_
+#define __RTW_WIFI_DEFS_H_
+
+#define _WEAK           __attribute__ ((weak))
+
+/** @defgroup WIFI_Exported_Constants WIFI Exported Constants
+  * @{
+  */
+
+/** @defgroup WLAN_Defs
+   *@{
+   */
+#ifndef WLAN0_NAME
+#define WLAN0_NAME		"wlan0"    /**< WLAN0 NAME */
+#endif
+
+#ifndef WLAN1_NAME
+#define WLAN1_NAME		"wlan1"    /**< WLAN1 NAME */
+#endif
+
+#ifndef WLAN0_IDX
+#define WLAN0_IDX	0  /**< wlan0 index */
+#endif
+
+#ifndef WLAN1_IDX
+#define WLAN1_IDX	1  /**< wlan1 index */
+#endif
+
+#ifndef STA_WLAN_INDEX
+#define STA_WLAN_INDEX	0
+#endif
+
+#ifndef SOFTAP_WLAN_INDEX
+#define SOFTAP_WLAN_INDEX	1
+#endif
+
+#ifndef NAN_WLAN_INDEX
+#define NAN_WLAN_INDEX	2
+#endif
+
+#ifndef STA_WLAN_NAME
+#define STA_WLAN_NAME	"wlan0"
+#endif
+
+#ifndef SOFTAP_WLAN_NAME
+#define SOFTAP_WLAN_NAME	"wlan1"
+#endif
+
+#ifndef NAN_WLAN_NAME
+#define NAN_WLAN_NAME	"wlan2"
+#endif
+
+#define IsSupported24G(band_type) ((band_type) & BAND_CAP_2G? TRUE : FALSE)
+#define IsSupported5G(band_type) ((band_type) & BAND_CAP_5G ?  TRUE : FALSE)
+
+#define IsLegacyOnly(NetType)  ((NetType) == ((NetType) & (WLAN_MD_11BG | WLAN_MD_11A)))
+
+#define IsSupportedTxOFDM(NetType) ((NetType) & (WLAN_MD_11G | WLAN_MD_11A) ? TRUE : FALSE)
+
+#define is_supported_ht(NetType) ((NetType) & (WLAN_MD_11N) ? TRUE : FALSE)
+#define is_supported_vht(NetType) ((NetType) & (WLAN_MD_11AC) ? TRUE : FALSE)
+#define is_supported_he(NetType) ((NetType) & (WLAN_MD_11AX) ? TRUE : FALSE)
+
+#define IS_HT_RATE(_rate)				(((_rate) & 0x80) ? TRUE : FALSE)
+#define IS_CCK_RATE(_rate) 				(MGN_1M == _rate || _rate == MGN_2M || _rate == MGN_5_5M || _rate == MGN_11M )
+#define IS_OFDM_RATE(_rate)				(MGN_6M <= _rate && _rate <= MGN_54M )
+
+/**
+ * @brief  mac address format.
+ */
+#define MAC_ARG(x)		((u8*)(x))[0],((u8*)(x))[1],\
+				((u8*)(x))[2],((u8*)(x))[3],\
+				((u8*)(x))[4],((u8*)(x))[5]
+#define MAC_FMT "%02x:%02x:%02x:%02x:%02x:%02x"
+
+#define is_broadcast_mac_addr(Addr) ((((Addr[0]) & 0xff) == 0xff) && (((Addr[1]) & 0xff) == 0xff) && \
+(((Addr[2]) & 0xff) == 0xff) && (((Addr[3]) & 0xff) == 0xff) && (((Addr[4]) & 0xff) == 0xff) && \
+(((Addr[5]) & 0xff) == 0xff))
+#define is_zero_mac_addr(Addr)	((Addr[0] == 0x00) && (Addr[1] == 0x00) && (Addr[2] == 0x00) &&   \
+                    (Addr[3] == 0x00) && (Addr[4] == 0x00) && (Addr[5] == 0x00))
+
+/**
+  * @}
+  */
+
+
+/** @defgroup Security_Defs
+   *@{
+   */
+#define AUTH_ALG_OPEN_SYSTEM	0x1
+#define AUTH_ALG_SHARED_KEY	0x2
+#define AUTH_ALG_SAE		0x8
+#define AUTH_ALG_LEAP		0x00000004
+
+#define WEP_ENABLED		0x0001		/**< wep enable */
+#define TKIP_ENABLED		0x0002		/**< tkip enable */
+#define AES_ENABLED		0x0004		/**< aes enable */
+#define WSEC_SWFLAG		0x0008		/**< WSEC SWFLAG */
+#define AES_CMAC_ENABLED	0x0010		/**< aes cmac enable */
+#define ENTERPRISE_ENABLED	0x0020		/**< enterprise enable */
+#define OWE_ENABLED		0X0040		/**< owe enable */
+#define SHARED_ENABLED		0x00008000	/**< shared enable */
+#define WPA_SECURITY		0x00200000	/**< wpa */
+#define WPA2_SECURITY		0x00400000	/**< wpa2 */
+#define WPA3_SECURITY		0x00800000	/**< wpa3 */
+#define WPS_ENABLED		0x10000000	/**< wps  enable*/
+
+/*cipher suite from 802.11-2016 p884*/
+#define WIFI_CIPHER_SUITE_WEP_40			0x000FAC01
+#define WIFI_CIPHER_SUITE_TKIP				0x000FAC02
+#define WIFI_CIPHER_SUITE_CCMP_128		0x000FAC04
+#define WIFI_CIPHER_SUITE_WEP_104			0x000FAC05
+#define WIFI_CIPHER_SUITE_BIP_CMAC_128	0x000FAC06
+#define WIFI_CIPHER_SUITE_GCMP				0x000FAC08
+#define WIFI_CIPHER_SUITE_GCMP_256		0x000FAC09
+#define WIFI_CIPHER_SUITE_CCMP_256		0x000FAC0A
+#define WIFI_CIPHER_SUITE_BIP_GMAC_128	0x000FAC0B
+#define WIFI_CIPHER_SUITE_BIP_GMAC_256	0x000FAC0C
+#define WIFI_CIPHER_SUITE_BIP_CMAC_256	0x000FAC0D
+
+#define RTW_WPA2_MAX_PSK_LEN		(64)
+#define RTW_WPA3_MAX_PSK_LEN		(128)		/**< maxmum psk length */
+#define RTW_MAX_PSK_LEN		RTW_WPA3_MAX_PSK_LEN
+#define RTW_MIN_PSK_LEN		(8)		/**< minimum psk length */
+#define MCSSET_LEN		16		/**<mcsset length */
+#define RTW_OWE_KEY_LEN		32 /*32(Temporarily support group 19 with 256 bit public key)*/
+
+/* adaptivity */
+#define RTW_ADAPTIVITY_EN_DISABLE			0
+#define RTW_ADAPTIVITY_EN_ENABLE			1
+
+#ifndef CONFIG_WIFI_CRITICAL_CODE_SECTION
+#define CONFIG_WIFI_CRITICAL_CODE_SECTION
+#endif
+
+#define RTW_SEND_AND_WAIT_ACK 				2
+#define RTW_SEND_BY_HIGH_RATE				4 // IEEE80211_OFDM_RATE_54MB
+#define RTW_NAV_BY_USER						8
+
+/**
+  * @}
+  */
+
+/** @defgroup Packet_Defs
+   *@{
+   */
+#define	PACKET_NORMAL			0
+#define	PACKET_DHCP			1
+#define	PACKET_ARP			2
+#define	PACKET_EAPOL			3
+
+/**
+  * @}
+  */
+
+
+/** @defgroup WPA_MODE_CHECK_Defs
+   *@{
+   */
+#define WPA2_MODE_CHECK(wpa_mode) ((wpa_mode == WPA_AUTO_MODE) || (wpa_mode == WPA2_ONLY_MODE) || (wpa_mode == WPA3_ONLY_MODE) || \
+									(wpa_mode == WPA_WPA2_MIXED_MODE) || (wpa_mode == WPA2_WPA3_MIXED_MODE))
+#define WPA_MODE_CHECK(wpa_mode) ((wpa_mode == WPA_AUTO_MODE) ||(wpa_mode == WPA_ONLY_MODE) ||(wpa_mode == WPA_WPA2_MIXED_MODE))
+
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+/** @defgroup WIFI_Exported_Types WIFI Exported Types
+* @{
+*/
+
+/** @addtogroup Enums
+   *@{
+   */
+
+/**
+ * @brief The enumeration lists band type
+ */
+enum band_type {
+	BAND_ON_24G	= 0,   /**< band is on 2.4G                          */
+	BAND_ON_5G	= 1,   /**< band is on 5G                          */
+	BAND_ON_6G	= 2,   /**< band is on 6G                          */
+	BAND_MAX,                  /**< max band                          */
+};
+
+/**
+ * @brief The enumeration lists wpa mode， size u8
+ */
+enum {
+	WPA_AUTO_MODE,  /**< wpa auto mode                       */
+	WPA_ONLY_MODE,   /**< wpa only mode                       */
+	WPA2_ONLY_MODE, /**< wpa2 only mode                       */
+	WPA3_ONLY_MODE, /**< wpa3 only mode                       */
+	WPA_WPA2_MIXED_MODE, /**< wpa and wpa2  mixed mode                       */
+	WPA2_WPA3_MIXED_MODE /**< wpa2 and wpa3  mixed mode                       */
+};
+
+
+/**
+ * @brief The enumeration lists the possible security types to set when connection.\n
+ *			Station mode supports OPEN, WEP, and WPA2.\n
+ *			AP mode support OPEN and WPA2.
+ */
+enum rtw_security {
+	RTW_SECURITY_OPEN               = 0,                                                            /**< Open security                           */
+	RTW_SECURITY_WEP_PSK            = (WEP_ENABLED),                                                /**< WEP Security with open authentication   */
+	RTW_SECURITY_WEP_SHARED         = (WEP_ENABLED | SHARED_ENABLED),                               /**< WEP Security with shared authentication */
+
+	RTW_SECURITY_WPA_TKIP_PSK       = (WPA_SECURITY | TKIP_ENABLED),                                /**< WPA Security with TKIP                  */
+	RTW_SECURITY_WPA_AES_PSK        = (WPA_SECURITY | AES_ENABLED),                                 /**< WPA Security with AES                   */
+	RTW_SECURITY_WPA_MIXED_PSK      = (WPA_SECURITY | AES_ENABLED | TKIP_ENABLED),                  /**< WPA Security with AES & TKIP            */
+	RTW_SECURITY_WPA2_TKIP_PSK		= (WPA2_SECURITY | TKIP_ENABLED),								/**< WPA2 Security with TKIP				 */
+	RTW_SECURITY_WPA2_AES_PSK       = (WPA2_SECURITY | AES_ENABLED),                                /**< WPA2 Security with AES                  */
+	RTW_SECURITY_WPA2_MIXED_PSK     = (WPA2_SECURITY | AES_ENABLED | TKIP_ENABLED),                 /**< WPA2 Security with AES & TKIP           */
+	RTW_SECURITY_WPA_WPA2_TKIP_PSK  = (WPA_SECURITY | WPA2_SECURITY | TKIP_ENABLED),                /**< WPA/WPA2 Security with TKIP             */
+	RTW_SECURITY_WPA_WPA2_AES_PSK   = (WPA_SECURITY | WPA2_SECURITY | AES_ENABLED),                 /**< WPA/WPA2 Security with AES              */
+	RTW_SECURITY_WPA_WPA2_MIXED_PSK = (WPA_SECURITY  | WPA2_SECURITY | TKIP_ENABLED | AES_ENABLED), /**< WPA/WPA2 Security with AES & TKIP       */
+	RTW_SECURITY_WPA3_AES_PSK	 = (WPA3_SECURITY | AES_ENABLED),				/**< WPA3-SAE with AES security			   */
+	RTW_SECURITY_WPA3_OWE	 = (WPA3_SECURITY | OWE_ENABLED | AES_ENABLED),				/**< WPA3-OWE with AES security			   */
+	RTW_SECURITY_WPA2_WPA3_MIXED = (WPA2_SECURITY | WPA3_SECURITY | AES_ENABLED), /**< WPA3-SAE/WPA2 with AES security		   */
+	RTW_SECURITY_WPA2_AES_CMAC      = (WPA2_SECURITY | AES_CMAC_ENABLED),                           /**< WPA2 Security with AES and Management Frame Protection */
+};
+
+/**
+  * @brief The enumeration lists the BIT 7 HT Rate.
+  */
+enum {
+	MGN_1M		= 0x02,     /**< 0x02 */
+	MGN_2M		= 0x04,     /**< 0x04 */
+	MGN_5_5M	= 0x0B,     /**< 0x0B */
+	MGN_6M		= 0x0C,     /**< 0x0C */
+	MGN_9M		= 0x12,     /**< 0x12 */
+	MGN_11M 	= 0x16,     /**< 0x16 */
+	MGN_12M = 0x18,      /**< 0x18 */
+	MGN_18M = 0x24,      /**< 0x24 */
+	MGN_24M = 0x30,      /**< 0x30 */
+	MGN_36M = 0x48,      /**< 0x48 */
+	MGN_48M = 0x60,      /**< 0x60 */
+	MGN_54M = 0x6C,      /**< 0x6C */
+	MGN_MCS32	= 0x7F,  /**< 0x7f */
+	MGN_MCS0,   /**< 0x80 */
+	MGN_MCS1,   /**< 0x81 */
+	MGN_MCS2,   /**< 0x82 */
+	MGN_MCS3,   /**< 0x83 */
+	MGN_MCS4,   /**< 0x84 */
+	MGN_MCS5,   /**< 0x85 */
+	MGN_MCS6,
+	MGN_MCS7,
+	MGN_MCS8,
+	MGN_MCS9,
+	MGN_MCS10,
+	MGN_MCS11,
+	MGN_MCS12,
+	MGN_MCS13,
+	MGN_MCS14,
+	MGN_MCS15,
+	MGN_MCS16,
+	MGN_MCS17,
+	MGN_MCS18,
+	MGN_MCS19,
+	MGN_MCS20,
+	MGN_MCS21,
+	MGN_MCS22,
+	MGN_MCS23,
+	MGN_MCS24,
+	MGN_MCS25,
+	MGN_MCS26,
+	MGN_MCS27,
+	MGN_MCS28,
+	MGN_MCS29,
+	MGN_MCS30,
+	MGN_MCS31,
+	MGN_VHT1SS_MCS0,
+	MGN_VHT1SS_MCS1,
+	MGN_VHT1SS_MCS2,
+	MGN_VHT1SS_MCS3,
+	MGN_VHT1SS_MCS4,
+	MGN_VHT1SS_MCS5,
+	MGN_VHT1SS_MCS6,
+	MGN_VHT1SS_MCS7,
+	MGN_VHT1SS_MCS8,
+	MGN_VHT1SS_MCS9,
+	MGN_VHT2SS_MCS0,
+	MGN_VHT2SS_MCS1,
+	MGN_VHT2SS_MCS2,
+	MGN_VHT2SS_MCS3,
+	MGN_VHT2SS_MCS4,
+	MGN_VHT2SS_MCS5,
+	MGN_VHT2SS_MCS6,
+	MGN_VHT2SS_MCS7,
+	MGN_VHT2SS_MCS8,
+	MGN_VHT2SS_MCS9,
+	MGN_VHT3SS_MCS0,
+	MGN_VHT3SS_MCS1,
+	MGN_VHT3SS_MCS2,
+	MGN_VHT3SS_MCS3,
+	MGN_VHT3SS_MCS4,
+	MGN_VHT3SS_MCS5,
+	MGN_VHT3SS_MCS6,
+	MGN_VHT3SS_MCS7,
+	MGN_VHT3SS_MCS8,
+	MGN_VHT3SS_MCS9,
+	MGN_VHT4SS_MCS0,
+	MGN_VHT4SS_MCS1,
+	MGN_VHT4SS_MCS2,
+	MGN_VHT4SS_MCS3,
+	MGN_VHT4SS_MCS4,
+	MGN_VHT4SS_MCS5,
+	MGN_VHT4SS_MCS6,
+	MGN_VHT4SS_MCS7,
+	MGN_VHT4SS_MCS8,
+	MGN_VHT4SS_MCS9,
+	MGN_HE1SS_MCS0 = 0xd0,   /**< 0xd0 */
+	MGN_HE1SS_MCS1,
+	MGN_HE1SS_MCS2,
+	MGN_HE1SS_MCS3,
+	MGN_HE1SS_MCS4,
+	MGN_HE1SS_MCS5,
+	MGN_HE1SS_MCS6,
+	MGN_HE1SS_MCS7,
+	MGN_HE1SS_MCS8,
+	MGN_HE1SS_MCS9,
+	MGN_HE1SS_MCS10,
+	MGN_HE1SS_MCS11,
+	MGN_HE2SS_MCS0,
+	MGN_HE2SS_MCS1,
+	MGN_HE2SS_MCS2,
+	MGN_HE2SS_MCS3,
+	MGN_HE2SS_MCS4,
+	MGN_HE2SS_MCS5,
+	MGN_HE2SS_MCS6,
+	MGN_HE2SS_MCS7,
+	MGN_HE2SS_MCS8,
+	MGN_HE2SS_MCS9,
+	MGN_HE2SS_MCS10,
+	MGN_HE2SS_MCS11,
+	MGN_HE3SS_MCS0,
+	MGN_HE3SS_MCS1,
+	MGN_HE3SS_MCS2,
+	MGN_HE3SS_MCS3,
+	MGN_HE3SS_MCS4,
+	MGN_HE3SS_MCS5,
+	MGN_HE3SS_MCS6,
+	MGN_HE3SS_MCS7,
+	MGN_HE3SS_MCS8,
+	MGN_HE3SS_MCS9,
+	MGN_HE3SS_MCS10,
+	MGN_HE3SS_MCS11,
+	MGN_HE4SS_MCS0,
+	MGN_HE4SS_MCS1,
+	MGN_HE4SS_MCS2,
+	MGN_HE4SS_MCS3,
+	MGN_HE4SS_MCS4,
+	MGN_HE4SS_MCS5,
+	MGN_HE4SS_MCS6,
+	MGN_HE4SS_MCS7,
+	MGN_HE4SS_MCS8,
+	MGN_HE4SS_MCS9,
+	MGN_HE4SS_MCS10,
+	MGN_HE4SS_MCS11 = 0xff,  /**< 0xff */
+	MGN_UNKNOWN
+};
+
+/**
+  * @brief csi trig management frame subtype.
+  */
+enum {
+	CSI_TRIG_ASSOCREQ   = BIT(0),
+	CSI_TRIG_ASSOCRSP   = BIT(1),
+	CSI_TRIG_REASSOCREQ = BIT(2),
+	CSI_TRIG_REASSOCRSP = BIT(3),
+	CSI_TRIG_PROBEREQ   = BIT(4),
+	CSI_TRIG_PROBERSP   = BIT(5),
+	CSI_TRIG_BEACON     = BIT(8),
+	CSI_TRIG_ATIM       = BIT(9),
+	CSI_TRIG_DISASSOC   = BIT(10),
+	CSI_TRIG_AUTH       = BIT(11),
+	CSI_TRIG_DEAUTH     = BIT(12),
+	CSI_TRIG_ACTION     = BIT(13)
+};
+
+/**
+  * @brief csi trig control frame subtype.
+  */
+enum {
+	CSI_TRIG_TRIGGER     = BIT(2),
+	CSI_TRIG_BA          = BIT(9),
+	CSI_TRIG_PSPOLL      = BIT(10),
+	CSI_TRIG_RTS         = BIT(11),
+	CSI_TRIG_CTS         = BIT(12),
+	CSI_TRIG_ACK         = BIT(13),
+	CSI_TRIG_CFEND       = BIT(14),
+	CSI_TRIG_CFEND_CFACK = BIT(15)
+};
+
+/**
+  * @brief csi trig data frame subtype.
+  */
+enum {
+	CSI_TRIG_DATA           = BIT(0),
+	CSI_TRIG_DATA_CFACK     = BIT(1),
+	CSI_TRIG_DATA_CFPOLL    = BIT(2),
+	CSI_TRIG_DATA_CFACKPOLL = BIT(3),
+	CSI_TRIG_DATA_NULL      = BIT(4),
+	CSI_TRIG_CF_ACK         = BIT(5),
+	CSI_TRIG_CF_POLL        = BIT(6),
+	CSI_TRIG_CF_ACKPOLL     = BIT(7),
+	CSI_TRIG_QOS_DATA       = BIT(8),
+	CSI_TRIG_QOS_DATA_NULL	= BIT(12)
+};
+
+/**
+  * @brief csi enable or config
+  */
+enum {
+	CSI_ACT_EN,    /**< enable or disable csi func */
+	CSI_ACT_CFG,  /**< config csi parameters */
+	CSI_ACT_MAX
+};
+
+/**
+  * @brief csi group num
+  */
+enum {
+	CSI_GROUP_NUM_1 = 0,  /**< per tone */
+	CSI_GROUP_NUM_2,         /**< per 2tone */
+	CSI_GROUP_NUM_4,        /**< per 4tone */
+	CSI_GROUP_NUM_16,     /**< per 16tone */
+	CSI_GROUP_NUM_MAX
+};
+
+/**
+  * @brief csi mode
+  */
+enum {
+	CSI_MODE_NORMAL = 0,   ///<   normal mode
+	CSI_MODE_NDP,                ///<   ndp mode
+	CSI_MODE_RX_RESP,         ///<    rx rsp mode
+	CSI_MODE_MAX,                 ///<    max mode
+};
+
+/**
+  * @brief csi accuracy.
+  */
+enum {
+	CSI_ACCU_1BYTE = 0, /**< CSI_ACCU_1BYTE: S(8,4) */
+	CSI_ACCU_2BYTES,  /**< CSI_ACCU_2BYTE: S(16,12) */
+	CSI_ACCU_MAX
+};
+
+/**
+  * @brief csi alg_opt.
+  */
+enum {
+	CSI_ALG_LS = 0,  /**< ls algo */
+	CSI_ALG_SMOTHING, /**< smothing algo */
+	CSI_ALG_MAX            /**< other algo */
+};
+
+/**
+  * @brief csi ch_opt.
+  */
+enum {
+	CSI_CH_LEGACY = 0, /**< legacy part(L-LTF) channel estmation result */
+	CSI_CH_NON_LEGACY,  /**< non-legacy(HT-LTF) part */
+	CSI_CH_MAX
+};
+
+/**
+  * @brief csi play_role for sta mode.
+  */
+enum {
+	CSI_OP_ROLE_TRX = 0,  /**< both trx */
+	CSI_OP_ROLE_TX  = 1,  /**< only tx csi triggering frame */
+	CSI_OP_ROLE_RX  = 2,  /**< only rx csi triggering frame for fetching csi report */
+	CSI_OP_ROLE_MAX
+};
+
+/**
+  * @brief Power Mgnt
+  */
+enum power_mgnt_mode {
+	PS_MODE_ACTIVE	= 0	, ///< active mode
+	PS_MODE_LEGACY		,       ///< legacy mode
+	PS_MODE_UAPSD_WMM	, ///< uapsd wmm mode
+};
+
+/**
+* @brief The enumeration lists the trp tis types.
+*/
+enum rtw_trp_tis_mode {
+	RTW_TRP_TIS_DISABLE = 0,
+	RTW_TRP_TIS_NORMAL = 1,
+	RTW_TRP_TIS_DYNAMIC = 3,					///< enable dynamic mechanism
+	RTW_TRP_TIS_FIX_ACK_RATE = 5,			///< fix ack rate to 6M
+	RTW_TRP_TIS_FIX_PHY_ACK_HIGH_RATE = 9	///< fix phy ack rate to RATE_54M | RATE_48M | RATE_36M | RATE_24M | RATE_18M | RATE_12M | RATE_9M | RATE_6M
+};
+
+/**
+* @brief The enumeration lists the edcca mode types.
+*/
+enum rtw_edcca_mode {
+	RTW_EDCCA_NORM	= 0, /* normal */
+	RTW_EDCCA_ADAPT	= 1, /* adaptivity */
+	RTW_EDCCA_CS	= 2, /* carrier sense */
+	RTW_EDCCA_DISABLE	= 9, /* disable */
+};
+
+/**
+* @brief The enumeration lists the antdiv mode types.
+*/
+enum rtw_antdiv_mode {
+	RTW_ANTDIV_AUTO     = 0,    /* auto antdiv */
+	RTW_ANTDIV_FIX_MAIN = 1,    /* fix main ant */
+	RTW_ANTDIV_FIX_AUX  = 2,    /* fix aux ant */
+	RTW_ANTDIV_DISABLE  = 0xF,  /* disable antdiv*/
+};
+
+/**
+* @brief The enumeration lists band types, size u8
+*/
+enum {
+	RTW_802_11_BAND_5GHZ   = 0, /**< Denotes 5GHz radio band */
+	RTW_802_11_BAND_2_4GHZ = 1,  /**< Denotes 2.4GHz radio band */
+};
+
+/**
+  * @brief  The enumeration lists the bss types. size u8
+  */
+enum {
+	RTW_BSS_TYPE_INFRASTRUCTURE 	= 0, /**< Denotes infrastructure network                  */
+	RTW_BSS_TYPE_WTN_HELPER          		= 1, /**< Denotes an wtn helper network           */
+	RTW_BSS_TYPE_UNKNOWN
+};
+
+/**
+  * @brief  The enumeration lists the scan options.
+  */
+enum {
+	RTW_SCAN_NOUSE			= 0x00,  /**< default value */
+	RTW_SCAN_ACTIVE              	= 0x01,     /**< active scan */
+	RTW_SCAN_PASSIVE             	= 0x02,    /**< passive scan*/
+	RTW_SCAN_NO_HIDDEN_SSID	= 0x04, /**< Filter hidden ssid APs*/
+	RTW_SCAN_REPORT_EACH	= 0x08,    /**< report each */
+	RTW_SCAN_WITH_P2P		= 0x10    /**< for P2P usage */
+};
+
+/**
+  * @brief  The enumeration lists the WPS types.
+  */
+enum {
+	RTW_WPS_TYPE_DEFAULT 		    		= 0,	/**< default type */
+	RTW_WPS_TYPE_USER_SPECIFIED 		= 1,	/**< user specified type */
+	RTW_WPS_TYPE_MACHINE_SPECIFIED   	= 2,	/**< machine specified type */
+	RTW_WPS_TYPE_REKEY 			        	= 3,	/**< retry key type */
+	RTW_WPS_TYPE_PUSHBUTTON 		    	= 4,	/**< push button type */
+	RTW_WPS_TYPE_REGISTRAR_SPECIFIED 	= 5,	/**< register specified type */
+	RTW_WPS_TYPE_NONE                   		= 6, 	/**< none */
+	RTW_WPS_TYPE_WSC                    		= 7,	/**< wsc type */
+};
+
+/**
+  * @brief The enumeration lists the supported operation mode by WIFI driver,
+  *			including station and AP mode.
+  */
+enum {
+	RTW_MODE_NONE	= 0,		///<none
+	RTW_MODE_STA		= 1,	///<sta mode
+	RTW_MODE_AP		= 2,	///<ap mode
+	RTW_MODE_NAN		= 3,	///<nan mode
+	RTW_MODE_MAX
+};
+
+/**
+  * @brief  The enumeration lists the supported autoreconnect mode by WIFI driver.
+  */
+enum rtw_autoreconnect_mode {
+	RTW_AUTORECONNECT_DISABLE,  ///< disable auto reconnect
+	RTW_AUTORECONNECT_FINITE,    ///< finite auto reconnect
+	RTW_AUTORECONNECT_INFINITE ///< infinite auto reconnect
+};
+
+/* For freertos, core, hal, rf, halbb. */
+enum phl_phy_idx {
+	HW_PHY_0,
+	HW_PHY_1,
+	HW_PHY_MAX
+};
+
+/**
+  * @brief  only internal used events.
+  */
+enum  {
+	/* only internal used */
+	WIFI_EVENT_INTERNAL_BASE		 	= 100,
+	WIFI_EVENT_RX_MGNT					= 101,
+	WIFI_EVENT_RX_MGNT_AP				= 102,
+	WIFI_EVENT_EXTERNAL_AUTH_REQ		= 103,
+
+	WIFI_EVENT_WPA_STA_4WAY_START		= 104,
+	WIFI_EVENT_WPA_AP_4WAY_START		= 105,
+	WIFI_EVENT_WPA_STA_4WAY_RECV		= 106,
+	WIFI_EVENT_WPA_AP_4WAY_RECV			= 107,
+	WIFI_EVENT_WPA_SET_PSK_INFO			= 108,
+
+	WIFI_EVENT_OWE_START_CALC			= 109,
+	WIFI_EVENT_OWE_PEER_KEY_RECV		= 110,
+
+#if defined(CONFIG_IEEE80211V) || defined(CONFIG_IEEE80211K) || defined(CONFIG_IEEE80211R)
+	WIFI_EVENT_KVR_CAP_UPDATE			= 111,
+#if defined(CONFIG_IEEE80211V) || defined(CONFIG_IEEE80211K)
+	WIFI_EVENT_NB_RESP_RECV				= 112,
+#endif
+#ifdef CONFIG_IEEE80211V
+	WIFI_EVENT_BTM_REQ_RECV				= 113,
+	WIFI_EVENT_BTM_DEBUG_CMD			= 114,
+#endif
+#ifdef CONFIG_IEEE80211R
+	WIFI_EVENT_FT_AUTH_START			= 115,
+	WIFI_EVENT_FT_RX_MGNT				= 116,
+#endif
+#endif
+
+	WIFI_EVENT_DEAUTH_INFO_FLASH		= 117,
+	WIFI_EVENT_INTERNAL_MAX,
+};
+/**
+  * The enumeration lists the flash operation status.
+  */
+enum flash_operation_type {
+	FLASH_READ = 0,   /**< read  flash                       */
+	FLASH_WRITE,       /**< write  flash                       */
+};
+
+/**
+  * The enumeration lists the power save status.
+  */
+enum {
+	IPS_WIFI_OFF = 0,
+	IPS_WIFI_PG,
+	IPS_LEVEL_MAX,
+};
+
+/**
+  * The enumeration lists the p2p role type.
+  */
+enum rtw_p2p_role {
+	P2P_ROLE_DISABLE = 0,
+	P2P_ROLE_DEVICE = 1,
+	P2P_ROLE_CLIENT = 2,
+	P2P_ROLE_GO = 3
+};
+
+enum gen_ie_type {
+	P2PWPS_PROBE_REQ_IE = 0,
+	P2PWPS_PROBE_RSP_IE,
+	P2PWPS_BEACON_IE,
+	P2PWPS_ASSOC_REQ_IE,
+	P2PWPS_ASSOC_RSP_IE
+};
+
+enum UAPSD_MAX_SP {
+	NO_LIMIT,
+	TWO_MSDU,
+	FOUR_MSDU,
+	SIX_MSDU
+};
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif
diff --git a/ameba/common/wifi/source/wifi_feature_dis_antdiv.c b/ameba/common/wifi/source/wifi_feature_dis_antdiv.c
new file mode 100644
index 00000000..32d0082f
--- /dev/null
+++ b/ameba/common/wifi/source/wifi_feature_dis_antdiv.c
@@ -0,0 +1,99 @@
+/*
+ * Copyright (c) 2024 Realtek Semiconductor Corp.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define __WIFI_FEATURE_DIS_ANTDIV_C__
+#include <stdbool.h>
+#include <stdint.h>
+
+#define UNUSED(a)		(void)a
+
+#if defined(CONFIG_SINGLE_CORE_WIFI)
+
+void wifi_hal_antdiv_training_timer_init(void *a)
+{
+	UNUSED(a);
+}
+
+void wifi_hal_antdiv_init(void *a)
+{
+	UNUSED(a);
+}
+
+void wifi_hal_antdiv_watchdog(void *a)
+{
+	UNUSED(a);
+}
+
+void wifi_hal_antdiv_get_rssi_info(bool a, uint8_t b, uint8_t c)
+{
+	UNUSED(a);
+	UNUSED(b);
+	UNUSED(c);
+}
+
+void wifi_hal_antdiv_get_rate_info(bool a, uint8_t b, uint8_t c)
+{
+	UNUSED(a);
+	UNUSED(b);
+	UNUSED(c);
+}
+
+void wifi_hal_antdiv_get_evm_info(bool a, uint8_t b)
+{
+	UNUSED(a);
+	UNUSED(b);
+}
+
+void rtw_wnm_dbg_cmd(uint8_t *buf, int32_t buf_len, int32_t flags, void *userdata)
+{
+	UNUSED(buf);
+	UNUSED(buf_len);
+	UNUSED(flags);
+	UNUSED(userdata);
+}
+
+#else
+void rtw_wnm_dbg_cmd(uint8_t *buf, int32_t buf_len, int32_t flags, void *userdata)
+{
+	UNUSED(buf);
+	UNUSED(buf_len);
+	UNUSED(flags);
+	UNUSED(userdata);
+}
+#endif
+void eap_disconnected_hdl(void)
+{
+}
+
+int get_eap_phase(void)
+{
+	return 0;
+}
+
+void eap_eapol_start_hdl(uint8_t *evt_info)
+{
+	UNUSED(evt_info);
+}
+
+void eap_eapol_recvd_hdl(uint8_t *buf, int32_t buf_len)
+{
+	UNUSED(buf);
+	UNUSED(buf_len);
+}
+
+int rtk_diag_event_add(uint8_t evt_level, uint16_t evt_type, const uint8_t *evt_info, uint16_t evt_len)
+{
+	UNUSED(evt_level);
+	UNUSED(evt_type);
+	UNUSED(evt_info);
+	UNUSED(evt_len);
+	return 0;
+}
+
+void eap_autoreconnect_hdl(uint8_t method_id)
+{
+	UNUSED(method_id);
+}
\ No newline at end of file
diff --git a/ameba/common/wifi/source/wifi_init_zephyr.c b/ameba/common/wifi/source/wifi_init_zephyr.c
new file mode 100644
index 00000000..e1e528b0
--- /dev/null
+++ b/ameba/common/wifi/source/wifi_init_zephyr.c
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2024 Realtek Semiconductor Corp.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "ameba_soc.h"
+#include <zephyr/kernel.h>
+
+#ifdef CONFIG_SOC_SERIES_AMEBAD
+extern u32 wifi_hal_dma_interrupt(void *data);
+
+void wlan_int_enable(void)
+{
+	IRQ_CONNECT(WL_DMA_IRQ, 0, wifi_hal_dma_interrupt, NULL, 0);
+	irq_enable(WL_DMA_IRQ);
+
+	IRQ_CONNECT(WL_PROTOCOL_IRQ, 0, wifi_hal_dma_interrupt, NULL, 0);
+	irq_enable(WL_PROTOCOL_IRQ);
+
+}
+
+#else
+void wlan_int_enable(void)
+{
+	return;
+}
+#endif
diff --git a/ameba/common/wifi/source/wifi_intf_drv_to_app_basic.h b/ameba/common/wifi/source/wifi_intf_drv_to_app_basic.h
new file mode 100644
index 00000000..33ee7e43
--- /dev/null
+++ b/ameba/common/wifi/source/wifi_intf_drv_to_app_basic.h
@@ -0,0 +1,79 @@
+/*
+ * Copyright (c) 2024 Realtek Semiconductor Corp.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __WIFI_CONF_BASIC_H
+#define __WIFI_CONF_BASIC_H
+
+/** @defgroup WIFI_API
+ *  @brief      WIFI_API module
+ *  @{
+ */
+#include "basic_types.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define INIC_MAX_SSID_LENGTH (33)
+
+#pragma pack(1)
+/**
+  * @brief  The structure is used to describe the SSID.
+  */
+struct _rtw_ssid_t {
+	unsigned char		len;     /**< SSID length */
+	unsigned char		val[INIC_MAX_SSID_LENGTH]; /**< SSID name (AP name)  */
+};
+
+/**
+  * @brief  The structure is used to describe the unique 6-byte MAC address.
+  */
+struct _rtw_mac_t {
+	unsigned char		octet[6]; /**< Unique 6-byte MAC address */
+};
+
+
+/**
+  * @brief  The structure is used to describe the scan result of the AP.
+  */
+struct rtw_scan_result {
+	struct _rtw_ssid_t              SSID;             /**< Service Set Identification (i.e. Name of Access Point)                    */
+	struct _rtw_mac_t               BSSID;            /**< Basic Service Set Identification (i.e. MAC address of Access Point)       */
+	signed short		                  signal_strength;  /**< Receive Signal Strength Indication in dBm. <-90=Very poor, >-30=Excellent */
+	u8          			   bss_type;         /**< val: RTW_BSS_TYPE_INFRASTRUCTURE, RTW_BSS_TYPE_WTN_HELPER*/
+	u32					       security;         /**< val: RTW_SECURITY_OPEN, RTW_SECURITY_WEP_PSK...*/
+	u8        				   wps_type;         /**< val: RTW_WPS_TYPE_DEFAULT, RTW_WPS_TYPE_USER_SPECIFIED...*/
+	unsigned int               channel;          /**< Radio channel that the AP beacon was received on                          */
+	u8					       band;             /**< val: RTW_802_11_BAND_5GHZ, RTW_802_11_BAND_2_4GHZ*/
+	char	country_code[2];
+	u8		rom_rsvd[4];
+};
+
+#pragma pack()
+
+int wifi_on(u8 mode);
+int wifi_is_running(unsigned char wlan_idx);
+int wifi_disconnect(void);
+
+int wifi_stop_ap(void);
+int _wifi_on_ap(void);
+int _wifi_off_ap(void);
+
+int wifi_scan_networks_zephyr(u32 call_back);
+s32 wifi_get_join_status(u8 *join_status);
+int wifi_connect_zephyr(u8 *ssid, u8 ssid_len, u8 *psk, u8 psk_len, u8 channel);
+
+int wifi_is_connected_to_ap(void);
+void rtw_psk_wpa_deinit(u8 port);
+void rtw_wakelock_timeout(uint32_t timeoutms);
+void wifi_event_init(void);
+void wifi_indication(unsigned int event, char *buf, int buf_len, int flags);
+void rtw_psk_disconnect_hdl(char *buf, int buf_len, int flags, void *userdata);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __WIFI_API_H
\ No newline at end of file
diff --git a/ameba/common/wifi/source/wifi_intf_drv_to_bt.h b/ameba/common/wifi/source/wifi_intf_drv_to_bt.h
new file mode 100644
index 00000000..8fae25c3
--- /dev/null
+++ b/ameba/common/wifi/source/wifi_intf_drv_to_bt.h
@@ -0,0 +1,65 @@
+/*
+ * Copyright (c) 2024 Realtek Semiconductor Corp.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __BT_INTF_H__
+#define __BT_INTF_H__
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+enum pta_host_role {
+	PTA_HOST_WIFI			= 0,
+	PTA_HOST_BT				= 1
+};
+
+enum pta_process_action {
+	COMMON_ACTION			= 0,
+	CALIBRATION_START		= 1,
+	CALIBRATION_STOP		= 2
+};
+
+enum pta_type {
+	PTA_AUTO            = 0,
+	PTA_WIFI			= 1,
+	PTA_BT				= 2,
+	PTA_DISABLE		    = 0xFF,
+};
+
+enum bt_rfk_type {
+	BT_RX_DCK       = 0,
+	BT_LOK             = 1,
+	BT_LOK_RES      = 2,
+	BT_DAC_DCK     = 3,
+	BT_ADC_DCK     = 4,
+};
+
+struct bt_rfk_param {
+	enum bt_rfk_type type;
+	uint8_t  rfk_data1;
+	uint8_t  rfk_data2;
+	uint8_t  rfk_data3;
+	uint8_t  rfk_data4;
+};
+
+struct rtk_coex_vendor_info {
+	uint8_t  vendor_id;
+	uint8_t  product_id;
+};
+
+//----- ------------------------------------------------------------------
+// Coex Interface opened for upper layer
+//----- ------------------------------------------------------------------
+void rltk_coex_set_gnt_bt(enum pta_type gnt_bt, u8 role, u8 process);
+void rltk_coex_set_gnt_bt_with_clk_source(enum pta_type gnt_bt, u8 role, u8 process);
+int rltk_coex_bt_rfk(struct bt_rfk_param *rfk_param);
+void rltk_coex_bt_hci_notify(u8 type, u8 *pdata, u16 len);
+void rltk_coex_vendor_info_set(void *p_vendor_info, u8 length);
+#ifdef	__cplusplus
+}
+#endif
+
+#endif //#ifndef __BT_INTF_H__
diff --git a/ameba/scripts/flash.py b/ameba/scripts/flash.py
new file mode 100644
index 00000000..e984a617
--- /dev/null
+++ b/ameba/scripts/flash.py
@@ -0,0 +1,224 @@
+#! /usr/bin/env python
+# -*- coding: utf-8 -*-
+
+# Copyright (c) 2024 Realtek Semiconductor Corp.
+# SPDX-License-Identifier: Apache-2.0
+
+import sys
+import argparse
+import base64
+import json
+import subprocess
+import shutil
+import logging
+from enum import IntEnum
+from pathlib import Path
+
+# Configure logging
+logging.basicConfig(level=logging.INFO, format='%(asctime)s - %(levelname)s - %(message)s')
+logger = logging.getLogger(__name__)
+
+# Path constants definition
+THIS_DIR = Path(__file__).resolve().parent
+BLOBS_ROOT = (THIS_DIR / "../../zephyr/blobs/ameba").resolve()
+
+# Tool paths
+DEFAULT_FLASH_TOOL = (THIS_DIR / 'flash' / 'AmebaFlash.py').resolve()
+PROFILES_PATH = (THIS_DIR / "flash" / "Devices" / "Profiles").resolve()
+FLOADERS_DEST = (THIS_DIR / "flash" / "Devices" / "Floaders").resolve()
+
+class MemoryType(IntEnum):
+    RAM = 0
+    NOR = 1
+    NAND = 2
+
+# Device configuration mapping
+DEVICE_MAP = {
+    "amebag2": {
+        "profile": "RTL8721F_NOR.rdev",
+        "floader": "amebag2/bin/floader_amebagreen2.bin"
+    },
+    "amebadplus": {
+        "profile": "RTL8721Dx.rdev",
+        "floader": "amebadplus/bin/floader_amebadplus.bin"
+    }
+}
+
+def prepare_flash_environment(device: str) -> str:
+    """
+    Validate device, copy necessary bootloader (floader), and return Profile file path.
+    """
+    if not device:
+        raise ValueError("Device argument must not be empty.")
+
+    key = device.lower()
+    if key not in DEVICE_MAP:
+        valid_options = ", ".join(sorted(DEVICE_MAP.keys()))
+        raise ValueError(f"Unsupported device: '{device}'. Valid options: {valid_options}")
+
+    config = DEVICE_MAP[key]
+
+    # 1. Determine Profile path
+    profile_path = PROFILES_PATH / config["profile"]
+    if not profile_path.is_file():
+        raise FileNotFoundError(f"Profile file not found: {profile_path}")
+
+    # 2. Handle Floader copy
+    floader_src = BLOBS_ROOT / config["floader"]
+    if not floader_src.is_file():
+        raise FileNotFoundError(f"Floader file for {key} not found at: {floader_src}")
+
+    FLOADERS_DEST.mkdir(parents=True, exist_ok=True)
+
+    # Copy file (overwrite to ensure correctness)
+    try:
+        shutil.copy2(floader_src, FLOADERS_DEST)
+    except Exception as e:
+        logger.error(f"Failed to copy floader: {e}")
+        raise
+
+    return str(profile_path)
+
+def validate_tool_path(tool_path: str) -> Path:
+    """Validate if the flash tool path exists."""
+    path = Path(tool_path).resolve()
+    if not path.is_file():
+        raise FileNotFoundError(f"Flash tool not found: {path}")
+    return path
+
+def setup_parser(parser: argparse.ArgumentParser) -> None:
+    parser.add_argument('--tool-path', help='Path to flash.py (absolute or relative)')
+    parser.add_argument('--device', required=True, help='Device type (e.g., amebag2)')
+    parser.add_argument('--image-dir', required=True, type=Path, help="Directory containing image files")
+
+    # Serial configuration
+    parser.add_argument('--port', action='append', required=True,
+                        help='Serial port (repeatable), e.g. --port COM3')
+    parser.add_argument('--baudrate', default='1500000', help='Serial baudrate (default: 1500000)')
+
+    # Memory and addressing
+    parser.add_argument('--memory-type', choices=['nor', 'nand', 'ram'], default='nor',
+                        help='Memory type (default: nor)')
+    parser.add_argument('--images', nargs=3, action='append', metavar=('image-name', 'start-address', 'end-address'),
+                        help="User defined image layout: name start_addr end_addr")
+
+    # Erase control
+    parser.add_argument('--chip-erase', action='store_true', help='Perform Chip Erase (NOR only)')
+
+    # Logging and remote
+    parser.add_argument('--log-level', default='info', choices=['info', 'debug', 'warn', 'error'], help='Log level')
+    parser.add_argument('--log-file', help='Log file path')
+    parser.add_argument('--remote-server', help='Remote serial server IP')
+    parser.add_argument('--remote-password', help='Remote serial server password')
+
+def build_partition_table(image_dir: Path, images: list, memory_type_str: str) -> str:
+    """
+    Build partition table and encode in Base64.
+    """
+    partition_table = []
+
+    # Map memory type string to Enum value
+    mem_type_map = {
+        "nor": MemoryType.NOR,
+        "nand": MemoryType.NAND,
+        "ram": MemoryType.RAM
+    }
+    mem_type_val = mem_type_map.get(memory_type_str, MemoryType.NOR)
+
+    for img_name, start_addr_str, end_addr_str in images:
+        full_image_path = (image_dir / img_name).resolve()
+
+        # Pre-check if file exists to provide friendlier error
+        if not full_image_path.is_file():
+             raise FileNotFoundError(f"Image file not found: {full_image_path}")
+
+        try:
+            start_addr = int(start_addr_str, 16)
+            end_addr = int(end_addr_str, 16)
+        except ValueError as e:
+            raise ValueError(f"Invalid address format for image {img_name}: {e}")
+
+        partition_table.append({
+            "ImageName": str(full_image_path),
+            "StartAddress": start_addr,
+            "EndAddress": end_addr,
+            "FullErase": False,
+            "MemoryType": int(mem_type_val),
+            "Mandatory": True,
+            "Description": img_name
+        })
+
+    # Serialize -> Encode -> Base64
+    json_bytes = json.dumps(partition_table).encode('utf-8')
+    return base64.b64encode(json_bytes).decode('utf-8')
+
+def main(args):
+    # 1. Prepare environment (Profile & Floader)
+    try:
+        profile_path = prepare_flash_environment(args.device)
+    except Exception as e:
+        logger.error(str(e))
+        sys.exit(1)
+
+    # 2. Determine tool path
+    tool_path_str = args.tool_path if args.tool_path else str(DEFAULT_FLASH_TOOL)
+    try:
+        tool_path = validate_tool_path(tool_path_str)
+    except FileNotFoundError as e:
+        logger.error(str(e))
+        sys.exit(1)
+
+    # 3. Build base command
+    cmd = [sys.executable, str(tool_path), '--download', '--profile', profile_path]
+
+    # Add serial port arguments
+    cmd.append('--port')
+    cmd.extend(args.port) # args.port is already a list
+    cmd.extend(['--baudrate', args.baudrate])
+    cmd.extend(['--memory-type', args.memory_type])
+    cmd.extend(['--log-level', args.log_level])
+
+    # 4. Optional arguments
+    if args.log_file:
+        cmd.extend(['--log-file', args.log_file])
+
+    if args.remote_server:
+        cmd.extend(['--remote-server', args.remote_server])
+        if args.remote_password:
+            cmd.extend(['--remote-password', str(args.remote_password)])
+
+    if args.chip_erase:
+        cmd.extend(['--chip-erase'])
+
+    # 5. Image and partition handling
+    if not args.images:
+        # Simple mode: pass directory directly
+        if not args.image_dir.is_dir():
+            logger.error(f"Image directory does not exist: {args.image_dir}")
+            sys.exit(1)
+        cmd.extend(['--image-dir', str(args.image_dir)])
+    else:
+        # Advanced mode: custom partition table
+        try:
+            b64_table = build_partition_table(args.image_dir, args.images, args.memory_type)
+            cmd.extend(['--partition-table', b64_table])
+        except Exception as e:
+            logger.error(f"Failed to build partition table: {e}")
+            sys.exit(1)
+
+    # 6. Execute command
+    logger.info(f"Executing flash tool: {' '.join(cmd)}")
+    try:
+        subprocess.check_call(cmd)
+    except subprocess.CalledProcessError as e:
+        logger.error(f"Flash tool exited with error code {e.returncode}")
+        sys.exit(e.returncode)
+    except KeyboardInterrupt:
+        logger.warning("\nOperation cancelled by user.")
+        sys.exit(130)
+
+if __name__ == "__main__":
+    parser = argparse.ArgumentParser(description='Realtek Ameba Flash Wrapper')
+    setup_parser(parser)
+    args = parser.parse_args()
+    main(args)
diff --git a/ameba/scripts/flash/AmebaFlash.py b/ameba/scripts/flash/AmebaFlash.py
new file mode 100755
index 00000000..e8173698
--- /dev/null
+++ b/ameba/scripts/flash/AmebaFlash.py
@@ -0,0 +1,499 @@
+#! /usr/bin/env python
+# -*- coding: utf-8 -*-
+
+# Copyright (c) 2024 Realtek Semiconductor Corp.
+# SPDX-License-Identifier: Apache-2.0
+
+import os
+import sys
+import argparse
+import base64
+import re
+import threading
+from copy import deepcopy
+
+from base import *
+import version_info
+
+MinSupportedDeviceProfileMajorVersion = 1
+MinSupportedDeviceProfileMinorVersion = 1
+setting_file = "Settings.json"
+
+
+def convert_mingw_path_to_windows(mingw_path):
+    drive_match = re.match(r'^/([a-zA-Z])/', mingw_path)
+    if drive_match:
+        drive_letter = drive_match.group(1).upper() + ":\\"
+        windows_path_tail = mingw_path[3:]
+    else:
+        drive_letter = ""
+        windows_path_tail = mingw_path
+
+    windows_path_tail = windows_path_tail.replace('/', '\\')
+
+    windows_path = drive_letter + windows_path_tail
+
+    return windows_path
+
+
+def sys_exit(logger, status, ret):
+    if status:
+        logger.info(f"Finished PASS")  # customized, do not modify
+        sys.exit(0)
+    else:
+        logger.error(f"Finished FAIL: {ret}")  # customized, do not modify
+        sys.exit(1)
+
+
+def decoder_partition_string(partition_table_base64):
+    try:
+        if partition_table_base64 is None:
+            return None
+        partition_value = base64.b64decode(partition_table_base64).decode("utf-8")
+        partition_list = json.loads(partition_value)
+        return partition_list
+    except Exception as err:
+        raise argparse.ArgumentTypeError("Invalid partition table format with base64") from err
+
+
+# --- add remote server params ---
+def flash_process_entry(profile_info, serial_port, serial_baudrate, image_dir, settings, images_info,
+                        chip_erase,
+                        memory_type, memory_info, download,
+                        log_level, log_f,
+                        read_wifimac=False,
+                        remote_server=None, remote_port=None, remote_password=None):
+    logger = create_logger(serial_port, log_level=log_level, file=log_f)
+
+    ameba = Ameba(profile_info, serial_port, serial_baudrate, image_dir, settings, logger,
+                  download_img_info=images_info,
+                  chip_erase=chip_erase,
+                  memory_type=memory_type,
+                  erase_info=memory_info,
+                  remote_server=remote_server,
+                  remote_port=remote_port,
+                  remote_password=remote_password)
+    if download:
+        # download
+        if not ameba.check_protocol_for_download():
+            ret = ErrType.SYS_PROTO
+            sys_exit(logger, False, ret)
+
+        if memory_type == MemoryInfo.MEMORY_TYPE_NOR:
+            ret, is_reburn = ameba.check_supported_flash_size()
+            if ret != ErrType.OK:
+                logger.error(f"Check supported flash size fail")
+                sys_exit(logger, False, ret)
+
+            if is_reburn:
+                ameba.clean_up()
+                # reset with remote params
+                ameba = Ameba(profile_info, serial_port, serial_baudrate, image_dir, settings, logger,
+                              download_img_info=images_info,
+                              chip_erase=chip_erase,
+                              memory_type=memory_type,
+                              erase_info=memory_info,
+                              remote_server=remote_server,
+                              remote_port=remote_port,
+                              remote_password=remote_password)
+
+                logger.info(f"Re-prepare for reburn...")
+                ret = ameba.prepare()
+                if ret != ErrType.OK:
+                    logger.error("Download prepare fail")
+                    sys_exit(logger, False, ret)
+            else:
+                ret = ameba.show_device_info()
+                if ret != ErrType.OK:
+                    sys_exit(logger, False, ret)
+        else:
+            logger.info(f"Prepare for download...")
+            ret = ameba.prepare()
+            if ret != ErrType.OK:
+                logger.error("Download prepare fail")
+                sys_exit(logger, False, ret)
+
+        ret = ameba.verify_images()
+        if ret != ErrType.OK:
+            sys_exit(logger, False, ret)
+
+        if not ameba.is_all_ram:
+            ret = ameba.post_verify_images()
+            if ret != ErrType.OK:
+                sys_exit(logger, False, ret)
+
+        if not ameba.is_all_ram:
+            flash_status = FlashBPS()
+            ret = ameba.check_and_process_flash_lock(flash_status)
+            if ret != ErrType.OK:
+                logger.error("Download image fail")
+                sys_exit(logger, False, ret)
+
+        logger.info(f"Image download start...")  # customized, do not modify
+        ret = ameba.download_images()
+        if ret != ErrType.OK:
+            logger.error("Download image fail")
+            sys_exit(logger, False, ret)
+
+        if (not ameba.is_all_ram) and flash_status.need_unlock:
+            logger.info("Restore the flash block protection...")
+            ret = ameba.lock_flash(flash_status.protection)
+            if ret != ErrType.OK:
+                logger.error(f"Fail to restore the flash block protection")
+                sys_exit(logger, False, ret)
+
+        ret = ameba.post_process()
+        if ret != ErrType.OK:
+            logger.error("Post process fail")
+            sys_exit(logger, False, ret)
+    elif read_wifimac:
+        # read wifi mac
+        ret = ameba.prepare(show_device_info=False)
+        if ret != ErrType.OK:
+            logger.error("Prepare for read wifi-mac fail")
+            sys_exit(logger, False, ret)
+
+        logger.info(f'WiFiMAC: {ameba.device_info.get_wifi_mac_text()}')
+    else:
+        # erase
+        ret = ameba.prepare()
+        if ret != ErrType.OK:
+            logger.error("Erase prepare fail")
+            sys_exit(logger, False, ret)
+
+        if chip_erase:
+            ret = ameba.erase_flash_chip()
+            if ret != ErrType.OK:
+                logger.error("Chip erase fail")
+                sys_exit(logger, False, ret)
+            sys_exit(logger, True, ret)
+
+        ret = ameba.validate_config_for_erase()
+        if ret != ErrType.OK:
+            sys_exit(logger, False, ret)
+
+        ret = ameba.post_validate_config_for_erase()
+        if ret != ErrType.OK:
+            sys_exit(logger, False, ret)
+
+        if (not profile_info.is_ram_address(memory_info.start_address)):
+            flash_status = FlashBPS()
+            ret = ameba.check_and_process_flash_lock(flash_status)
+            if ret != ErrType.OK:
+                logger.error("Erase fail")
+                sys_exit(logger, False, ret)
+
+        ret = ameba.erase_flash()
+        if ret != ErrType.OK:
+            logger.error(f"Erase {memory_type} failed")
+            sys_exit(logger, False, ret)
+
+        if (not profile_info.is_ram_address(memory_info.start_address)) and flash_status.need_unlock:
+            logger.info("Restore the flash block protection...")
+            ret = ameba.lock_flash(flash_status.protection)
+            if ret != ErrType.OK:
+                logger.error(f"Fail to restore the flash block protection")
+                sys_exit(logger, False, ret)
+
+    ameba.clean_up()
+
+    sys_exit(logger, True, ret)
+
+
+def main(argc, argv):
+    parser = argparse.ArgumentParser(description=None)
+    parser.add_argument('-d', '--download', action='store_true', help='download images')
+    parser.add_argument('-f', '--profile', type=str, help='device profile')
+    parser.add_argument('-p', '--port', nargs="+", help='serial port')
+    parser.add_argument('-b', '--baudrate', type=int, help='serial port baud rate')
+    parser.add_argument('-i', '--image', type=str, help='single image')
+    parser.add_argument('-r', '--image-dir', type=str, help='image directory')
+    parser.add_argument('-a', '--start-address', type=str, help='start address, hex')
+    parser.add_argument('-n', '--end-address', type=str, help='end address, hex')
+    parser.add_argument('-z', '--size', type=int, help='size in KB')
+    parser.add_argument('-m', '--memory-type', choices=['nor', 'nand', 'ram'], default="nor",
+                        help='specified memory type')
+    parser.add_argument('-e', '--erase', action='store_true', help='erase flash')
+    parser.add_argument('-o', '--log-file', type=str, help='output log file with path')
+    parser.add_argument('-v', '--version', action='version', version=f'%(prog)s {version_info.version}')
+
+    parser.add_argument('--chip-erase', action='store_true', help='chip erase')
+    parser.add_argument('--log-level', default='info', help='log level')
+    parser.add_argument('--partition-table', help="layout info, list")
+    parser.add_argument('--read-wifimac', action='store_true', help="read wifi mac")
+
+    parser.add_argument('--remote-server', type=str, help='remote serial server IP address')
+    parser.add_argument('--remote-password', type=str, help='remote serial server validation password')
+    parser.add_argument('--no-reset', action='store_true', help='do not reset after flashing finished')
+
+    args = parser.parse_args()
+    download = args.download
+    profile = args.profile
+    image = args.image
+    image_dir = args.image_dir
+    chip_erase = args.chip_erase
+    serial_ports = args.port
+    serial_baudrate = args.baudrate
+    log_level = args.log_level.upper()
+    log_file = args.log_file
+    erase = args.erase
+    start_addr = args.start_address
+    end_addr = args.end_address
+    size = args.size
+    mem_t = args.memory_type
+    partition_table = decoder_partition_string(args.partition_table)
+    read_wifimac = args.read_wifimac
+
+    remote_server = args.remote_server
+    remote_port = 58916
+    remote_password = args.remote_password
+    no_reset = args.no_reset
+
+    if mem_t is not None:
+        if mem_t == "nand":
+            memory_type = MemoryInfo.MEMORY_TYPE_NAND
+        elif mem_t == "ram":
+            memory_type = MemoryInfo.MEMORY_TYPE_RAM
+        else:
+            memory_type = MemoryInfo.MEMORY_TYPE_NOR
+    else:
+        memory_type = None
+
+    if log_file is not None:
+        log_path = os.path.dirname(log_file)
+        if log_path:
+            if not os.path.exists(log_path):
+                os.makedirs(log_path, exist_ok=True)
+            log_f = log_file
+        else:
+            log_f = os.path.join(os.getcwd(), log_file)
+    else:
+        log_f = None
+    logger = create_logger("main", log_level=log_level, file=log_f)
+    if log_file is not None:
+        logger.info(f"Log file: {log_file}")
+
+    logger.info(f"AmebaFlash Version: {version_info.version}")
+
+    if remote_server:
+        logger.info(f"Using remote serial server: {remote_server}:{remote_port}")
+
+    if profile is None:
+        logger.error('Invalid arguments, no device profile specified')
+        parser.print_usage()
+        sys.exit(1)
+
+    if not os.path.exists(profile):
+        logger.error("Device profile '" + profile + "' does not exist")
+        sys.exit(1)
+    logger.info(f'Device profile: {profile}')
+
+    if serial_ports is None:
+        logger.error('Invalid arguments, no serial port specified')
+        parser.print_usage()
+        sys.exit(1)
+    logger.info(f'Serial port: {serial_ports}')
+
+    if serial_baudrate is None:
+        logger.error('Invalid arguments, no serial baudrate specified')
+        parser.print_usage()
+        sys.exit(1)
+    logger.info(f'Baudrate: {serial_baudrate}')
+
+    if all([download, erase]):
+        logger.warning("Download and erase are set true, only do image download ")
+    elif not (download or erase or chip_erase or read_wifimac):
+        logger.error("Download or erase or chip-erase or read-wifimac should be set")
+        sys.exit(1)
+
+    memory_info = None
+    images_info = None
+    if download:
+        # download
+        if (image is None) and (image_dir is None) and (partition_table is None):
+            logger.error('Invalid arguments, no image or image_dir input')
+            parser.print_usage()
+            sys.exit(1)
+
+        if image is not None:
+            download_img_info = ImageInfo()
+            if not os.path.exists(image):
+                logger.error(f"Image {image} does not exist")
+                sys.exit(1)
+            download_img_info.image_name = image
+            download_img_info.description = os.path.basename(image)
+
+            if memory_type is None:
+                logger.error(f"Memory type is required for single image download")
+                sys.exit(1)
+
+            if start_addr is None:
+                logger.error(f"Start address is required for single image download")
+                sys.exit(1)
+
+            try:
+                start_address = int(start_addr, 16)
+            except Exception as err:
+                logger.error(f"Start address is invalid: {err}")
+                sys.exit(1)
+            download_img_info.start_address = start_address
+
+            if memory_type == MemoryInfo.MEMORY_TYPE_NAND:
+                if end_addr is None:
+                    logger.error(f"End address is required for nand flash download")
+                    sys.exit(1)
+
+                try:
+                    end_address = int(end_addr, 16)
+                except Exception as err:
+                    logger.error(f"End address is invalid: {err}")
+                    sys.exit(1)
+            else:
+                end_address = start_address + os.path.getsize(image)
+
+            download_img_info.end_address = end_address
+            download_img_info.memory_type = memory_type
+            download_img_info.mandatory = True
+            images_info = [download_img_info]
+        elif partition_table is not None:
+            images_info = []
+            for img_info in partition_table:
+                img_json = ImageInfo(** img_info)
+                if sys.platform == "win32":
+                    img_p = convert_mingw_path_to_windows(img_json.image_name)
+                    img_json.image_name = img_p
+                img_json.description = os.path.basename(img_json.image_name)
+                images_info.append(img_json)
+        else:
+            images_info = None
+            if not os.path.exists(image_dir):
+                logger.error(f"Image directory {image_dir} does not exist")
+                sys.exit(1)
+
+            logger.info(f'Image dir: {image_dir}')
+        if images_info:
+            logger.info(f'Image info:')
+            for img_info in images_info:
+                for key, value in img_info.__repr__().items():
+                    if key == "ImageName":
+                        key = "Image"
+                    logger.info(f'> {key}: {value}')
+    elif read_wifimac:
+        # profile, port, baudrate, memory-type
+        pass
+    else:
+        # erase
+        if all([chip_erase, erase]):
+            logger.warning(f"Both chip erase and erase are enabled, do chip erase only")
+        if not chip_erase:
+            memory_info = MemoryInfo()
+            if start_addr is None:
+                logger.error(f"Start address is required for erase flash")
+                sys.exit(1)
+
+            try:
+                start_address = int(start_addr, 16)
+            except Exception as err:
+                logger.error(f"Start address is invalid: {err}")
+                sys.exit(1)
+            memory_info.start_address = start_address
+
+            if memory_type is None:
+                logger.error("Memory type is required for erase")
+                sys.exit(1)
+
+            memory_info.memory_type = memory_type
+
+            if memory_type == MemoryInfo.MEMORY_TYPE_NAND:
+                if end_addr is None:
+                    logger.error(f"End address is required for nand flash download")
+                    sys.exit(1)
+            else:
+                if size is None:
+                    logger.error(f"Erase size is required")
+                    sys.exit(1)
+
+            if end_addr:
+                try:
+                    end_address = int(end_addr, 16)
+                except Exception as err:
+                    logger.error(f"End address is invalid: {err}")
+                    sys.exit(1)
+            else:
+                end_address = 0
+
+            memory_info.size_in_kbyte = size
+
+            if end_address == 0:
+                end_address = start_address + size
+            memory_info.end_address = end_address
+
+    if not read_wifimac:
+        if chip_erase:
+            logger.info(f"Chip erase: {chip_erase}")
+            if memory_type is None:
+                logger.warning("Memory type is required for chip erase")
+                sys.exit(1)
+            if memory_type != MemoryInfo.MEMORY_TYPE_NOR:
+                logger.warning("Memory type should be 'nor' for chip erase")
+        else:
+            logger.info(f"Chip erase: False")
+
+    # check device profile
+    try:
+        profile_json = JsonUtils.load_from_file(profile)
+        if profile_json is None:
+            logger.error(f"Fail to load device profile {profile}")
+            sys.exit(1)
+        profile_info = RtkDeviceProfile(**profile_json)
+        ver = profile_info.get_version()
+        if ver.major >= MinSupportedDeviceProfileMajorVersion and ver.minor >= MinSupportedDeviceProfileMinorVersion and profile_info.device_id != 0:
+            logger.info(f"Device profile {profile} loaded")
+        else:
+            logger.error(f"Fail to load device profile {profile}, unsupported version {ver.__repr__()}")
+            sys.exit(1)
+    except Exception as err:
+        logger.error(f"Load device profile {profile} exception: {err}")
+        sys.exit(1)
+
+    # load settings
+    setting_path = os.path.realpath(os.path.join(RtkUtils.get_executable_root_path(), setting_file))
+    logger.info(f"Settings path: {setting_path}")
+    try:
+        if os.path.exists(setting_path):
+            dt = JsonUtils.load_from_file(setting_path, need_decrypt=False)
+            settings = RtSettings(** dt)
+        else:
+            logger.debug(f"{setting_file} not exists!")
+            settings = RtSettings(**{})
+    except Exception as err:
+        logger.error(f"Load settings exception: {err}")
+        settings = RtSettings(** {})
+    # save Setting.json
+    try:
+        if no_reset:
+            settings.post_process = "NONE"
+        else:
+            settings.post_process = "RESET"
+        JsonUtils.save_to_file(setting_path, settings.__repr__())
+    except Exception as err:
+        logger.debug(f"save {setting_file} exception: {err}")
+
+    threads_list = []
+
+    for sp in serial_ports:
+        flash_thread = threading.Thread(target=flash_process_entry, args=(
+        profile_info, sp, serial_baudrate, image_dir, settings, deepcopy(images_info), chip_erase,
+        memory_type, memory_info, download, log_level, log_f, read_wifimac:=read_wifimac,
+        remote_server, remote_port, remote_password))
+        threads_list.append(flash_thread)
+        flash_thread.start()
+
+    for thred in threads_list:
+        thred.join()
+
+    logger.info(f"All flash threads have completed")
+
+
+if __name__ == "__main__":
+    main(len(sys.argv), sys.argv[1:])
diff --git a/ameba/scripts/flash/Devices/Profiles/RTL8721Dx.rdev b/ameba/scripts/flash/Devices/Profiles/RTL8721Dx.rdev
new file mode 100644
index 00000000..b6392ba5
--- /dev/null
+++ b/ameba/scripts/flash/Devices/Profiles/RTL8721Dx.rdev
@@ -0,0 +1 @@
+mAP70iCZE2Fb02bAfyGBm9Vj1Dbag3Sa2kx5Vy34Bb6qqI92T5SU6hizYeL7adpFnPU7mqiBXH7dRbUS66HAm+j1N4tt3bRjbARBcagKl5PVN4kQlvj/2/xC6C1mkc97+zPIJiVvZawgMlr8gnsZMVYNolQ8T55Tp/JJpYv/bH7gOaq957XoJRr2po1FCaONsEiHdxUiohE9qLlIDxoRsT5dtkCDhJ+eymGFTk6YdC3yBD3YxMrJWrq0iLr/J5Yd5O/W3VwEhKZZpG2gqYQOBuAaUaihwUZCfrZYkHUmy3OFJ7EeWg4a3RPASt1KzZaDvUl4tmesB1groyqxIrgCRBl6CzSTtnSyx3siAJtd+PhCpeF77/BeyQimECzQ5+eY6jFCrkYD6JN9EgwZLxZpvZw3QE0gHcwzLgOnVixu/rLuTq1eBfUCIfKDEmwe5ckH4bzuntPCQgtsNp9JKEMZdAtI+ccAU1UiVgx5jF3KYwnksdmL0TdcTY+kDZJt8cRjUHh9/7fXwUSeoZbVgOUWT+IbMn/phWPGg7b40inTfHZ+l2QvOIQHT47Ypl81YSO3Mw+lyml5WPAD3Qf8N2X/xXV7fFPTinqy8t66P4/WjEiSfKq4o2o65O/yT8+WO3Q0fbXaVa50ofFKqzVYu0UyzWHqZzqq7+XO0Z0EDxa96gmDmPqS4LvWK49X3YcH4Aj6VHWjzvc0Pu4Du3yux9iqpPQTdDuSeEaeCPB3D4QznpoqfgkFrfJPqketOQd8dvS/xi2z2xSkjM78DEwnNu2ay4QkwYqdUbJjH9+RnkbMj5/0CwGR9gLFwNG8Al8RyNqvo3U4nWVTaFqVTIsr0OQqskhEtBnDEUEQvdzG/MTkX2GIkp2WvUs0sFj0eM27M4A6AjcMY8c9Nra1pgMPS7QpxvtJnGxnyPE3Am+UE3NzmTiSEJp3PqV3TYoJ9CiZaam3JS5JpApzqi/Bus71N9zDhpZ02lErX3Z0Vbws7U8CD4Se7qtVqGgkRFlpijauMaWd+jmt3PBSlD4J78248/NYoAkLKJpwVmJAOsPTkR7m2t3PVCzSBCHkvSMquMuNFiJIw/0MbWQmj/TYgd/gcaPwvxN7BpvDrMokxzMOlaaSNZb5Y1oanBiYqt87agLyoNVmnjRoyzUgXDWrE7eVH/og2wE0IzVuUWqFnSOFPajqUYTcMKDg8/tOVwSNyzkitUciefeyksO3F9sJjEZhwxyR5BbOP2o2bwVVkiTjmMDc46J9n16C/L9ailaKfoThakAXKQAAmvR53XenLsXj4MWUpYOtogsxGldtMiFryYU12zJxHGV+G/6jSn415jE/w0rctD8lDIgA4WVKiVouCGPj/fnoPTkpqwznR76IaY2GciMPBX+RqZ7xoA==
diff --git a/ameba/scripts/flash/Devices/Profiles/RTL8721F_NAND.rdev b/ameba/scripts/flash/Devices/Profiles/RTL8721F_NAND.rdev
new file mode 100644
index 00000000..aa1ad970
--- /dev/null
+++ b/ameba/scripts/flash/Devices/Profiles/RTL8721F_NAND.rdev
@@ -0,0 +1 @@
+mAP70iCZE2Fb02bAfyGBm9Vj1Dbag3Sa2kx5Vy34Bb6qqI92T5SU6kuepO/BAVr4QjfPYNMvMKFYhMG+if6e3wTg3mCaHJfzdQ1ZUna4Udz10afX1UpN5DSLcPexqTI1LymZfWGouCSVwNXQqeT3m1qFIqNhh8Nv/9nzIuwjXfFOrNo/qkzYqJycZUztJfqlfjwF7apmdrkXM5DsOzjsfu8TnrWs40O0lJErb4xc0kMCXcDRXEcdcS2iah1Ms37pKQi+at/II39ySIkWtFRbM1yEZaHGGOXjCyapkJKvNEfPIcc0FZxeHPF0VNt+eGnnmVpoVLtPepaQpr2AbLhI8ozwN8g/H5eBqVLAv7JezZKzND7/FjhsEZDnmU5IqQG57pnlcbnB2DDp+NeR7o2/9iHydeQ1qQFAr6yB7XBElj5X3oKnsNw3+sM3TEDK/IBBacd3oSA2wKSejD+MgaOHeW05SozyNlVOohZuNc9xX2mCAJuz0VP+TcICIWmpOgQ0856FZC4anzAAGWTS8RjokSeC2f9CcB5h6gE/QzewbQMkxKLk+NbJ/DSdHEbZ1s9FeTUqK3pjw+GPdPrcw3Wb6bYJO8MXBzfyRtyREaDnhOl4D77fJ93sEoiNLw6exb/O+YeVtXpCGLc0QVlPlu2Cjq7W+L5pQZdbP1OnK9MTjEw0BAeieA4f1PIcCCwdzO0X1p/zyClzW34Srq2xRGLVhwuCYDgj8lIkqZ8AAJAXPs1ujSGU57xs6/SP2+KvUDseARduzSR5PUKLMWXQjK7hWxT2AEXbMjP8ZfjMS17R9b2zcU6cIM/N88O58WSoDrzckPQ9eJ7zQMBcHl4CWFOUiST+Zqb5iQKZvuGG3hKbT/JRN7wNjyUpD/ovvKJmy30GbAgoJK+MdLQbrgKvg2K/YZfa76kWM/89mYHzUC64nU8eFzEVS5Ymt3rRaZ89MR0Hjkiwvz9QcOUiavTkgNlIsX3tFlzGsXwuDPjyo7rhBUuEyJdzz0k93CsEsPPabrhWlNtxUJmzGrcjRHh6pHk0HYhAbFdCaqRfoeNLY7pP2JLOs0sjE5tIm84F6UGah3RQZqANpPc8E32DpoYlRyTdl2vlP8IYQA7gaerYX0A4I2Jg3uYkN1yCF1SmP+n+xeKt0W3HEEgyVJ0r6M2HOr3OoxKOKJSHkcEasZvloGsldj4ODdoGWxvhqnAyFOIl5okakbxGSxGfJGnVsRFA4NTxKXy+JHqWYmBOpdX0StR7eEWJQs5ZykztLqi2O2vf5lSCX3vuyX+qHPrS4HuDg9Wwxmqr37EPyCDqGmKv7BxV4CSeIlUV2Udr55YLjOcwqokzql4HUxLNb+RyN07Y4nn15A==
diff --git a/ameba/scripts/flash/Devices/Profiles/RTL8721F_NOR.rdev b/ameba/scripts/flash/Devices/Profiles/RTL8721F_NOR.rdev
new file mode 100644
index 00000000..e0cd5178
--- /dev/null
+++ b/ameba/scripts/flash/Devices/Profiles/RTL8721F_NOR.rdev
@@ -0,0 +1 @@
+mAP70iCZE2Fb02bAfyGBm9Vj1Dbag3Sa2kx5Vy34Bb6qqI92T5SU6kuepO/BAVr4QjfPYNMvMKFYhMG+if6e3wTg3mCaHJfzdQ1ZUna4Udz10afX1UpN5LeXridnZb0qODD2FO9udVBnUG+pLVkv32NgVap9HNalypBYOcnJK0iZJ3sfc+aWOc5N8JMRiI2tuqDKTBiN4nbtigBLNArX3tmOd4PRjDbmXjEBj4Gxg34gCv6x0Jw9Ey+1Bdy4mHnj0EegtdhctI9pmoSX6lcoMqz5Sf0MD+6HBHkv60gNZBKk0QvJ4nryRxwJ1njUXTXm51ua5RyhI8k+oBy6DN9ubFmLKYYmuy3FTuz8ygRbG6npQu7sRcyGrr1JuLXBMxhIRxlCurPzJttego/p845WnuNGOfofMA8dJEN5qk5c06rzHFsUPsUA9KCc8IlMo1GRLM/IfQtJEswh58hJEYMjew2sqWyWLe9+O/aR+HcL2XgallHgHSJU9ss1s+oMuxXn963q44BO315YnJDxKIVcf5Po6CVuJKKJ2fbNPassYcyJiEeP+j1yQ+kLXOyJ22drdjFteIjZ4EmYSFleCSZX5yQ55v1NqdD942K8SrDFDtqjhMLHDS+DAR0G3lNSCK8p2L8Rvyefghn5Fu3lg0oAgBkskLgguVmH6fuzXujenVqXWJCwvBhdCWDqKJW1g2tTnnnCYgJNDONPLlsFhfBRefPDzM9JwcVqpqmHDL5GTqToVUPIk5na8a3FL+SFx6gZGS4u5mWd+nBX9Kdwxjr/8ZuF1aXEu7X0pvbIyIged/g1cHyOTK6JTEgf9yFbaqW4QOdt5b4iKLyCcpTwMabLwSebs2LPw8Yu66SID3vBIGPgkVQHpMhGWuADg4aW457Cj4/YYJxf0DOkF6gGK7jfoDx1uL9/0/FX74HnMIJzqNYqTbckC3W9VC6H/lsRSWo9tReaz+Y8w7vNAgYTjJ0nSJLIUKE9tSQ9YLMv9QO5xoou/KC5MCpMsvMWqcaz2ysLf74UiKXxs1KRER3LuSr0gC9MuZe5A4xArom1DUwdyYhDYxPm+UrcFA1sJw3Lsl6K5I7OTXrCmR1P+mAAUJFXRm27mZ0eMjw9SXZnPS6rhcvgAuYV81SV0wODThvO7V0pdlQ4IYDRrnr5kCjpTg+sxfbfH8v4YurrFvLeP0D3n4Muhl01aIBqxhVwVIGFnAgYTBOIAzAkeFs76ld8G08pTA==
diff --git a/ameba/scripts/flash/Settings.json b/ameba/scripts/flash/Settings.json
new file mode 100644
index 00000000..f47de1af
--- /dev/null
+++ b/ameba/scripts/flash/Settings.json
@@ -0,0 +1,27 @@
+{
+  "SensePacketCount": 32,
+  "RequestRetryCount": 3,
+  "RequestRetryIntervalInMillisecond": 10,
+  "AsyncResponseTimeoutInMilliseccond": 1000,
+  "SyncResponseTimeoutInMillisecond": 1000,
+  "BaudrateSwitchDelayInMillisecond": 200,
+  "RomBootDelayInMillisecond": 100,
+  "UsbRomBootDelayInMillisecond": 1000,
+  "UsbFloaderBootDelayInMillisecond": 1000,
+  "SerialInitialReadTimeoutInMillisecond": 20,
+  "SwitchBaudrateAtFloader": 0,
+  "WriteResponseTimeoutInMillisecond": 2000,
+  "FloaderBootDelayInMillisecond": 1000,
+  "AutoSwitchToDownloadModeWithDtrRts": 0,
+  "AutoResetDeviceWithDtrRts": 0,
+  "FlashProtectionProcess": 0,
+  "EraseByBlock": 0,
+  "ProgramConfig1": 0,
+  "ProgramConfig2": 0,
+  "DisableNandAccessWithUart": 0,
+  "RamDownloadPaddingByte": 0,
+  "AutoProgramSpicAddrMode4Byte": 0,
+  "AutoSwitchToDownloadModeWithDtrRtsTimingFile": "Reburn.cfg",
+  "AutoResetDeviceWithDtrRtsTimingFile": "Reset.cfg",
+  "PostProcess": "RESET"
+}
diff --git a/ameba/scripts/flash/base/__init__.py b/ameba/scripts/flash/base/__init__.py
new file mode 100644
index 00000000..9bd9b9eb
--- /dev/null
+++ b/ameba/scripts/flash/base/__init__.py
@@ -0,0 +1,3 @@
+from .download_handler import *
+from .rtk_logging import *
+from .rt_settings import *
diff --git a/ameba/scripts/flash/base/config_utils.py b/ameba/scripts/flash/base/config_utils.py
new file mode 100644
index 00000000..a658b820
--- /dev/null
+++ b/ameba/scripts/flash/base/config_utils.py
@@ -0,0 +1,30 @@
+#! /usr/bin/env python
+# -*- coding: utf-8 -*-
+
+# Copyright (c) 2024 Realtek Semiconductor Corp.
+# SPDX-License-Identifier: Apache-2.0
+
+import os
+
+
+class ConfigUtils:
+    @staticmethod
+    def get_key_value_pairs(logger, file_path):
+        result = []
+        with open(file_path, 'r') as file:
+            for line in file:
+                line = line.strip()
+                if not line:
+                    continue
+
+                parts = line.split("=", 1)
+                if len(parts) == 2:
+                    key, value = parts
+                    try:
+                        result.append({key: int(value)})
+                    except ValueError:
+                        logger.warning(f"Skipping line with non-integer value: {line}")
+                else:
+                    logger.warning(f"Skipping improperly formatted line: {line}")
+
+        return result
diff --git a/ameba/scripts/flash/base/device_info.py b/ameba/scripts/flash/base/device_info.py
new file mode 100644
index 00000000..5ff0a025
--- /dev/null
+++ b/ameba/scripts/flash/base/device_info.py
@@ -0,0 +1,42 @@
+#! /usr/bin/env python
+# -*- coding: utf-8 -*-
+
+# Copyright (c) 2024 Realtek Semiconductor Corp.
+# SPDX-License-Identifier: Apache-2.0
+
+from .rtk_flash_type import *
+from .memory_info import *
+
+
+class DeviceInfo(object):
+    def __init__(self):
+        self.did = 0
+        self.image_type = 0
+        self.cmd_set_version = 0
+        self.wifi_mac = None
+        self.memory_type = None
+        self.flash_mid = None
+        self.flash_did = None
+        self.flash_mfg = ""
+        self.flash_model = ""
+        self.flash_page_size = 0
+        self.flash_oob_size = 0
+        self.flash_pages_per_block = 0
+        self.flash_blocks_per_lun = 0
+        self.flash_luns_per_target = None
+        self.flash_max_bad_block_per_lun = 0
+        self.flash_req_host_ecc_level = None
+        self.flash_targets = None
+        self.flash_capacity = 0
+
+    def get_wifi_mac_text(self):
+        mac_list = []
+        for chr in self.wifi_mac:
+            mac_list.append(hex(chr)[2:].zfill(2).upper())
+        return ":".join(mac_list)
+
+    def flash_block_size(self):
+        return self.flash_page_size * self.flash_pages_per_block
+
+    def is_boot_from_nand(self):
+        return self.memory_type == MemoryInfo.MEMORY_TYPE_NAND
diff --git a/ameba/scripts/flash/base/device_profile.py b/ameba/scripts/flash/base/device_profile.py
new file mode 100644
index 00000000..05969239
--- /dev/null
+++ b/ameba/scripts/flash/base/device_profile.py
@@ -0,0 +1,79 @@
+#! /usr/bin/env python
+# -*- coding: utf-8 -*-
+
+# Copyright (c) 2024 Realtek Semiconductor Corp.
+# SPDX-License-Identifier: Apache-2.0
+
+from .image_info import *
+from .efuse_data import *
+from .version import *
+
+
+class RtkDeviceProfile():
+    DEFAULT_FLASH_START_ADDR = 0x08000000
+    DEFAULT_RAM_START_ADDR = 0x20000000
+    DEVICE_ID_AMEBAD = 0x6548
+    DEVICE_ID_AMEBAZ = 0x6547
+
+    def __init__(self, **kwargs):
+        self.version = kwargs.get("Version", "1.1.1")
+        self.device_name = kwargs.get("DeviceName", "")
+        self.device_id = kwargs.get("DeviceID", 0)
+        self.memory_type = kwargs.get("MemoryType", 0)
+        self.support_usb_download = kwargs.get("SupportUsbDownload", False)
+        self.flash_start_address = kwargs.get("FlashStartAddress", self.DEFAULT_FLASH_START_ADDR)
+        self.ram_start_address = kwargs.get("RamStartAddress", self.DEFAULT_RAM_START_ADDR)
+        self.floader = kwargs.get("Floader", "")
+        self.floader_address = kwargs.get("FloaderAddress", 0)
+        self.handshake_baudrate = kwargs.get("HandshakeBaudrate", 0)
+        self.log_baudrate = kwargs.get("LogBaudrate", 0)
+        self.logical_efuse_len = kwargs.get("LogicalEfuseLen", 0)
+        self.physical_efuse_len = kwargs.get("PhysicalEfuseLen", 0)
+        self.images = []
+        self.default_efuse_map = []
+        for image_info in kwargs.get("Images", []):
+            self.images.append(ImageInfo(**image_info))
+
+        for efuse_data in kwargs.get("DefaultEfuseMap", []):
+            self.default_efuse_map.append(EfuseData(**efuse_data))
+
+    def is_amebad(self):
+        return (self.device_id == self.DEVICE_ID_AMEBAD)
+
+    def is_amebaz(self):
+        return (self.device_id == self.DEVICE_ID_AMEBAZ)
+
+    def is_ram_address(self, address):
+        return (address >= self.DEFAULT_RAM_START_ADDR)
+
+    def is_flash_address(self, address):
+        return (address >= self.DEFAULT_FLASH_START_ADDR)
+
+    def get_version(self):
+        if self.version:
+            return Version(self.version)
+        else:
+            return Version("1.0.0")
+
+    def __repr__(self):
+        image_info_list = [ii.__repr__() for ii in self.images]
+        efuse_data_list = [ed.__repr__() for ed in self.default_efuse_map]
+        profile_dict = {
+            "Images": image_info_list,
+            "DefaultEfuseMap": efuse_data_list,
+            "Version": f"{self.version}",
+            "DeviceName": self.device_name,
+            "DeviceID": self.device_id,
+            "MemoryType": self.memory_type.value,
+            "SupportUsbDownload": self.support_usb_download,
+            "FlashStartAddress": self.flash_start_address,
+            "RamStartAddress": self.ram_start_address,
+            "Floader": self.floader,
+            "FloaderAddress": self.floader_address,
+            "HandshakeBaudrate": self.handshake_baudrate,
+            "LogBaudrate": self.log_baudrate,
+            "LogicalEfuseLen": self.logical_efuse_len,
+            "PhysicalEfuseLen": self.physical_efuse_len
+        }
+
+        return profile_dict
diff --git a/ameba/scripts/flash/base/download_handler.py b/ameba/scripts/flash/base/download_handler.py
new file mode 100644
index 00000000..7df2bd87
--- /dev/null
+++ b/ameba/scripts/flash/base/download_handler.py
@@ -0,0 +1,1490 @@
+#! /usr/bin/env python
+# -*- coding: utf-8 -*-
+
+# Copyright (c) 2024 Realtek Semiconductor Corp.
+# SPDX-License-Identifier: Apache-2.0
+
+from serial.tools.list_ports import comports
+import serial
+import struct
+import serial.tools.list_ports
+from datetime import datetime
+
+from .rom_handler import *
+from .floader_handler import *
+from .flash_utils import *
+from .device_profile import *
+from .json_utils import *
+from .rt_settings import *
+from .spic_addr_mode import *
+from .memory_info import *
+from .config_utils import *
+from .remote_serial import RemoteSerial
+from typing import Optional, Dict, Any
+
+_RTK_USB_VID = "0BDA"
+
+CmdEsc = b'\x1b\r\n'
+CmdSetBackupRegister = bytes("EW 0x480003C0 0x200\r\n", encoding="utf-8")
+CmdResetIntoDownloadMode = bytes("reboot uartburn\r\n", encoding="utf-8")
+
+OtpSpicAddrModeAddr = 0x02
+OtpSpicAddrModeMask = 0x02
+OtpSpicAddrModePos = 1
+OtpSpicAddrMode4Byte = (1 << OtpSpicAddrModePos)
+OtpSpicAddrMode3Byte = (0 << OtpSpicAddrModePos)
+
+OtpSpicAddrModeAddrForAmebaD = 0x0E
+OtpSpicAddrModeMaskForAmebaD = 0x40
+OtpSpicAddrModePosForAmebaD = 6
+OtpSpicAddrMode4ByteForAmebaD = (1 << OtpSpicAddrModePosForAmebaD)
+OtpSpicAddrMode3ByteForAmebaD = (0 << OtpSpicAddrModePosForAmebaD)
+
+
+class Ameba(object):
+    def __init__(self,
+                 profile: RtkDeviceProfile,
+                 serial_port: serial.Serial,
+                 baudrate: int,
+                 image_path: str,
+                 setting: RtSettings,
+                 logger,
+                 download_img_info=None,
+                 chip_erase=False,
+                 memory_type=None,
+                 erase_info=None,
+                 remote_server: Optional[str] = None,
+                 remote_port: Optional[int] = None,
+                 remote_password: Optional[str] = None):
+        self.logger = logger
+        self.setting = setting
+        self.profile_info = profile
+        self.serial_port = None
+        self.serial_port_name = serial_port
+        self.remote_server = remote_server
+        self.remote_port = remote_port
+        self.remote_password = remote_password
+        self.is_usb = self.is_realtek_usb() if not remote_server else False
+        self.initial_serial_port()
+        self.baudrate = baudrate
+        self.image_path = image_path
+        self.download_img_info = download_img_info
+        self.chip_erase = chip_erase
+        self.memory_type = memory_type
+        self.device_info = None
+        self.erase_info = erase_info
+        self.is_all_ram = True
+
+        self.rom_handler = RomHandler(self)
+        self.floader_handler = FloaderHandler(self)
+
+    def __del__(self):
+        if self.serial_port:
+            if self.is_open():
+                try:
+                    self.logger.info(f"close {self.serial_port.port}...")
+                    self.serial_port.close()
+                    self.logger.info(f"{self.serial_port.port} close done")
+                except Exception as e:
+                    self.logger.error(f"close error: {e}", exc_info=True)
+            self.serial_port = None
+
+    def clean_up(self):
+        if self.serial_port:
+            try:
+                if self.serial_port.is_open:
+                    self.logger.info(f"close {self.serial_port.port}...")
+                    self.serial_port.close()
+                while self.serial_port.is_open:
+                    pass
+                self.logger.info(f"{self.serial_port.port} closed.")
+            except Exception as err:
+                self.logger.error(f"close error: {err}", exc_info=True)
+
+            self.serial_port = None
+
+    def initial_serial_port(self):
+        # initial serial port
+        try:
+            # determine whether to use a remote serial port
+            self.logger.debug(f"Remote server: self.logger type={type(self.logger)}, value={self.logger}")
+            if self.remote_server and self.remote_port:
+                self.logger.info(f"Connect to remote serial server: {self.remote_server}:{self.remote_port} (Serial port: {self.serial_port_name})")
+                # initialize remote serial port
+                self.serial_port = RemoteSerial(
+                    remote_server=self.remote_server,
+                    remote_port=self.remote_port,
+                    port=self.serial_port_name,
+                    baudrate=self.profile_info.handshake_baudrate,
+                    logger=self.logger
+                )
+                if self.remote_password:
+                    self.logger.debug("Remote server: password set, will send validate command")
+                    self.serial_port.validate(self.remote_password)
+                self.serial_port.open()
+            else:
+                # initialize local serial port
+                if self.is_usb:
+                    self.serial_port = serial.Serial(self.serial_port_name,
+                                                     baudrate=self.profile_info.handshake_baudrate,
+                                                     parity=serial.PARITY_NONE,
+                                                     stopbits=serial.STOPBITS_ONE,
+                                                     timeout=self.setting.serial_initial_read_timeout_in_second,
+                                                     bytesize=serial.EIGHTBITS)
+                else:
+                    self.serial_port = serial.Serial()
+                    self.serial_port.port = self.serial_port_name
+                    self.serial_port.baudrate = self.profile_info.handshake_baudrate
+                    self.serial_port.parity = serial.PARITY_NONE
+                    self.serial_port.stopbits = serial.STOPBITS_ONE
+                    self.serial_port.bytesize = serial.EIGHTBITS
+                    self.serial_port.timeout = self.setting.serial_initial_read_timeout_in_second
+                    self.serial_port.dtr = False
+                    self.serial_port.rts = False
+                    self.serial_port.open()
+        except Exception as err:
+            self.logger.error(f"Initialize serial port failed: {err}")
+            sys.exit(1)
+
+    # --- check if serial port is open (remote/local compatible) ---
+    def is_open(self) -> bool:
+        if isinstance(self.serial_port, RemoteSerial):
+            return self.serial_port.is_open
+        elif isinstance(self.serial_port, serial.Serial):
+            return self.serial_port.is_open
+        return False
+
+    def switch_baudrate(self, baud, delay_s, force=False):
+        ret = ErrType.OK
+
+        if (baud == self.serial_port.baudrate) and (not force):
+            self.logger.debug(f"Don't need to switch baudrate: {baud}")
+            return ret
+
+        self.logger.debug(f"Switch baudrate: {self.serial_port.baudrate} -> {baud}")
+
+        try:
+            # remote serial port: close and reopen (no dynamic switching supported yet)
+            if isinstance(self.serial_port, RemoteSerial):
+                self.serial_port.close()
+                #time.sleep(delay_s)
+                self.serial_port.baudrate = baud
+                self.serial_port.open()
+            else:
+                # local serial port
+                if self.is_usb:
+                    for retry in range(10):
+                        try:
+                            if self.serial_port.is_open:
+                                self.serial_port.close()
+                            while self.serial_port.is_open:
+                                pass
+                            ret = ErrType.OK
+                            break
+                        except:
+                            ret = ErrType.SYS_IO
+                        time.sleep(0.1)
+                    if ret != ErrType.OK:
+                        self.logger.warning(f"Close serial port failed")
+
+                if self.serial_port.baudrate != baud:
+                    self.serial_port.baudrate = baud
+                    time.sleep(delay_s)
+
+                if self.is_usb:
+                    for rty in range(10):
+                        try:
+                            self.serial_port.open()
+                            ret = ErrType.OK
+                            break
+                        except:
+                            ret = ErrType.SYS_IO
+                        time.sleep(0.1)
+        except Exception as e:
+            self.logger.error(f"An exception occurs when switching baudrate: {str(e)}")
+            ret = ErrType.SYS_IO
+
+        if ret == ErrType.OK:
+            self.logger.debug(f"Switch baudrate success: {baud}")
+        else:
+            self.logger.debug(f"Switch baudrate failed")
+
+        return ret
+
+    def read_bytes(self, timeout_seconds, size=1):
+        ret = ErrType.OK
+        read_ch = None
+
+        try:
+            start_time = time.monotonic()
+            data_buffer = bytearray()
+
+            while len(data_buffer) < size:
+                if (time.monotonic() - start_time) > timeout_seconds:
+                    return ErrType.DEV_TIMEOUT, bytes(data_buffer) if data_buffer else None
+
+                needed = size - len(data_buffer)
+                chunk = self.serial_port.read(needed)
+
+                if chunk:
+                    data_buffer.extend(chunk)
+
+                if self.remote_server:
+                    time.sleep(0.001)  # avoid waiting idly and improve efficiency.
+
+            ret, read_ch = ErrType.OK, bytes(data_buffer)
+        except Exception as err:
+            self.logger.error(f"read bytes err: {err}")
+            ret = ErrType.SYS_IO
+
+        return ret, read_ch
+
+    def write_bytes(self, data_bytes):
+        self.serial_port.write(data_bytes)
+
+    def write_string(self, string):
+        bytes_array = string.encode("utf-8")
+        self.serial_port.write(bytes_array)
+
+    def is_realtek_usb(self):
+        if self.remote_server:
+            return False
+        ports = serial.tools.list_ports.comports()
+        for port, desc, hvid in sorted(ports):
+            if port == self.serial_port_name:
+                # hvid: USB VID:PID=0BDA:8722 SER=5 LOCATION=1-1
+                if _RTK_USB_VID in hvid:
+                    return True
+        else:
+            return False
+
+    def switch_baudrate_old(self, baud, delay_s, force=False):
+        ret = ErrType.OK
+
+        if (baud == self.serial_port.baudrate) and (not force):
+            self.logger.debug(f"Reactive port {self.serial_port.port} ignored, baudrate no change")
+            return ret
+
+        if baud != self.serial_port.baudrate:
+            self.logger.debug(
+                f"Reactive port {self.serial_port.port} with baudrate from {self.serial_port.baudrate} to {baud}")
+        else:
+            self.logger.debug(
+                f"Reactive port {self.serial_port.port} with baudrate {baud}")
+
+        # if uart dtr/rts enable, should skip close/reopen operation
+        # if USB port, should close/reopen port when switch baudrate
+        if self.is_usb:
+            # check if already activated
+            for retry in range(10):
+                try:
+                    if self.serial_port.is_open:
+                        self.serial_port.close()
+
+                    while self.serial_port.is_open:
+                        pass
+                    ret = ErrType.OK
+                except:
+                    ret = ErrType.SYS_IO
+
+                if ret == ErrType.OK:
+                    break
+
+                time.sleep(0.1)
+
+            if ret != ErrType.OK:
+                self.logger.warning(f"Failed to close {self.serial_port.port} when reactive it.")
+
+            time.sleep(delay_s)
+
+        if self.serial_port.baudrate != baud:
+            self.serial_port.baudrate = baud
+
+        if self.is_usb:
+            ret = ErrType.OK
+            for rty in range(10):
+                try:
+                    self.serial_port.open()
+                    ret = ErrType.OK
+                except:
+                    ret = ErrType.SYS_IO
+
+                if ret == ErrType.OK:
+                    break
+
+                time.sleep(0.1)
+
+        if ret == ErrType.OK:
+            self.logger.debug(f"Reactive port {self.serial_port.port} ok")
+        else:
+            self.logger.debug(f"Reactive port {self.serial_port.port} fail")
+
+        return ret
+
+    def check_download_mode(self):
+        ret = ErrType.SYS_IO
+        is_floader = False
+        boot_delay = self.setting.usb_rom_boot_delay_in_second if self.profile_info.support_usb_download else self.setting.rom_boot_delay_in_second
+
+        self.logger.debug(f"Check download mode with baudrate {self.serial_port.baudrate}")
+        retry = 0
+        while retry < 3:
+            retry += 1
+            try:
+                self.logger.debug(f"Check whether in rom download mode")
+                ret = self.rom_handler.handshake()
+                if ret == ErrType.OK:
+                    self.logger.debug(f"Handshake ok, device in rom download mode")
+                    break
+
+                if not self.is_usb:
+                    self.logger.debug(
+                        f'Assume in application or ROM normal mode with baudrate {self.profile_info.log_baudrate}')
+                    self.switch_baudrate(self.profile_info.log_baudrate, self.setting.baudrate_switch_delay_in_second)
+
+                    self.logger.debug("Try to reset device...")
+
+                    self.serial_port.flushOutput()
+
+                    self.write_bytes(CmdEsc)
+                    time.sleep(0.02)
+
+                    if self.profile_info.is_amebad():
+                        self.serial_port.flushOutput()
+                        self.write_bytes(CmdSetBackupRegister)
+                        time.sleep(0.02)
+
+                    self.serial_port.flushOutput()
+                    self.write_bytes(CmdResetIntoDownloadMode)
+                    time.sleep(0.02)  # wait for cmd tx to device successfully when in lower baudrate
+
+                    self.switch_baudrate(self.profile_info.handshake_baudrate, boot_delay, True)
+                    self.serial_port.flushInput()
+                    time.sleep(0.05)
+
+                    self.logger.debug(
+                        f'Check whether reset in ROM download mode with baudrate {self.profile_info.handshake_baudrate}')
+
+                    ret = self.rom_handler.handshake()
+                    if ret == ErrType.OK:
+                        self.logger.debug("Handshake ok, device in ROM download mode")
+                        break
+                    else:
+                        self.logger.debug("Handshake fail, cannot enter UART download mode")
+
+                    self.switch_baudrate(self.baudrate, self.setting.baudrate_switch_delay_in_second, True)
+
+                self.logger.debug(f"Check whether in floader with baudrate {self.baudrate}")
+                ret, status = self.floader_handler.sense(self.setting.sync_response_timeout_in_second)
+                if ret == ErrType.OK:
+                    # do not reset floader
+                    is_floader = True
+                    self.logger.debug("Floader handshake ok")
+                    break
+                else:
+                    self.logger.debug(f"Floader handshake fail: {ret}")
+            except Exception as err:
+                self.logger.error(f"Check download mode exception: {err}")
+
+        return ret, is_floader
+
+    def show_device_info(self):
+        ret = ErrType.OK
+
+        self.logger.info("Device info:")
+        self.logger.info(f'* DID: {hex(self.device_info.did)}')
+        self.logger.info(f'* ImageType: 0x{format(self.device_info.image_type, "04x")}')
+        self.logger.info(
+            f'* CmdSetVersion: {(self.device_info.cmd_set_version >> 8) & 0xFF}.{self.device_info.cmd_set_version & 0xFF}')
+        if self.device_info.is_boot_from_nand():
+            self.logger.info(f'* MemoryType: NAND')
+            self.logger.info(f'* FlashMID: 0x{format(self.device_info.flash_mid, "02X")}')  # customized, do not modify
+            if self.device_info.flash_mid == FlashUtils.NandMfgMicron:
+                self.logger.info(f'* FlashDID: 0x{format(self.device_info.flash_did, "04X")}')
+            else:
+                self.logger.info(f'* FlashDID: 0x{format(self.device_info.flash_did, "02X")}')
+            self.logger.info(f'* FlashMFG: {self.device_info.flash_mfg}')
+            self.logger.info(f'* FlashModel: {self.device_info.flash_model}')
+            self.logger.info(
+                f'* FlashCapacity: {self.device_info.flash_capacity // 1024 // 1024 // (1024 // 8)}Gb/{self.device_info.flash_capacity // 1024 // 1024}MB')
+            self.logger.info(f'* FlashBlockSize: {self.device_info.flash_block_size() // 1024}KB')
+            self.logger.info(f'* FlashPageSize: {self.device_info.flash_page_size}B')
+            self.logger.info(f'* FlashOobSize: {self.device_info.flash_oob_size}B')
+            self.logger.info(f'* FlashPagesPerBlock: {self.device_info.flash_pages_per_block}')
+            self.logger.info(f'* FlashBlocksPerLun: {self.device_info.flash_blocks_per_lun}')
+            self.logger.info(f'* FlashLunsPerTarget: {self.device_info.flash_luns_per_target}')
+            self.logger.info(f'* FlashTargets: {self.device_info.flash_targets}')
+            self.logger.info(f'* FlashMaxBadBlocksPerLun: {self.device_info.flash_max_bad_block_per_lun}')
+            self.logger.info(f'* FlashReqHostEccLevel: {self.device_info.flash_req_host_ecc_level}')
+        else:
+            self.logger.info(f'* MemoryType: NOR')
+            self.logger.info(f'* FlashMID: {hex(self.device_info.flash_mid)}')
+            self.logger.info(f'* FlashDID: {hex(self.device_info.flash_did)}')
+            self.logger.info(
+                f'* FlashCapacity: {self.device_info.flash_capacity // 1024 // (1024 // 8)}Mb/{self.device_info.flash_capacity // 1024 // 1024}MB')
+            self.logger.info(f'* FlashPageSize: {self.device_info.flash_page_size}B')
+
+        self.logger.info(f'* WiFiMAC: {self.device_info.get_wifi_mac_text()}')
+
+        if (self.device_info.did != self.profile_info.device_id) and (self.device_info.did != 0xFFFF):
+            self.logger.error("Device ID mismatch:")
+            self.logger.error(f'* Device: {hex(self.device_info.did)}')
+            self.logger.error(f'* Device Profile: {hex(self.profile_info.device_id)}')
+            return ErrType.SYS_PARAMETER
+
+        if self.device_info.memory_type != self.profile_info.memory_type:
+            self.logger.error("Flash type mismatch:")
+            self.logger.error(f'* Device: {self.device_info.memory_type}')
+            self.logger.error(f'* Device Profile: {self.profile_info.memory_type}')
+            return ErrType.SYS_PARAMETER
+
+        if self.device_info.is_boot_from_nand():
+            if self.device_info.flash_req_host_ecc_level > 0:
+                self.logger.error(f"Unsupported NAND flash model without internal ECC")
+                return ErrType.SYS_IO
+            if self.device_info.flash_pages_per_block != FlashUtils.NandDefaultPagePerBlock.value:
+                self.logger.error(
+                    f"Unsupported NAND flash model with {self.device_info.flash_pages_per_block} pages per block")
+                return ErrType.SYS_IO
+
+        program_param1 = self.setting.program_config1.to_bytes(8, byteorder="little")
+        program_param2 = self.setting.program_config2.to_bytes(8, byteorder="little")
+        param = [program_param1, program_param2]
+        ret = self.floader_handler.config(param)
+        if ret != ErrType.OK:
+            self.logger.error(f"Config device fail: {ret}")
+
+        return ret
+
+    def prepare(self, show_device_info=True):
+        ret = ErrType.OK
+        floader_init_baud = self.baudrate if self.is_usb else (self.profile_info.handshake_baudrate if
+                                                               (self.setting.switch_baudrate_at_floader == 1) else self.baudrate)
+        boot_delay = self.setting.usb_floader_boot_delay_in_second if self.profile_info.support_usb_download else self.setting.floader_boot_delay_in_second
+
+        if (not self.is_usb) and (self.setting.auto_switch_to_download_mode_with_dtr_rts != 0):
+            ret = self.auto_enter_download_mode()
+            if ret != ErrType.OK:
+                self.logger.error(f"Enter download mode by DTR/RTS fail: {ret}")
+                return ret
+
+        ret, is_floader = self.check_download_mode()
+        if ret != ErrType.OK:
+            self.logger.error(f"Enter download mode fail: {ret}")
+            return ret
+
+        if not is_floader:
+            # download flashloader to RAM
+            ret = self.rom_handler.download_floader()
+            if ret != ErrType.OK:
+                self.rom_handler.abort()
+                self.logger.error(f"Flashloader download fail: {ret}")
+                return ret
+
+            ret = self.switch_baudrate(floader_init_baud, boot_delay, True)
+            if ret != ErrType.OK:
+                self.logger.error(f"Flashloader boot fail: {ret}")
+                return ret
+
+            ret = self.floader_handler.handshake(self.baudrate)
+            if ret != ErrType.OK:
+                self.logger.error(f"Flashloader handshake fail: {ret}")
+                return ret
+
+        ret, self.device_info = self.floader_handler.query()
+        if ret != ErrType.OK:
+            self.logger.error(f"Query fail: {ret}")
+            return ret
+
+        if not show_device_info:
+            return ret
+
+        ret = self.show_device_info()
+
+        return ret
+
+    def check_flash_lock(self, flash_status):
+        ret = ErrType.OK
+
+        if self.device_info.is_boot_from_nand():
+            cmd = FlashUtils.NandCmdGetFeatures.value
+            address = FlashUtils.NandRegProtection.value
+            bp_mask = FlashUtils.NandRegProtectionBpMask.value
+            if self.device_info.flash_mid == FlashUtils.NandMfgWinbond or self.device_info.flash_mid == FlashUtils.NandMfgMicron:
+                bp_mask = FlashUtils.NandRegProtectionBpMaskWinbondMicron
+        else:
+            cmd = FlashUtils.NorCmdReadStatusReg1.value
+            address = 0
+            bp_mask = FlashUtils.NorStatusReg1BpMask.value
+
+        ret, protection = self.read_flash_status_register(cmd, address)
+        flash_status.protection = protection
+        if ret == ErrType.OK:
+            if (protection & bp_mask) != 0:
+                flash_status.is_locked = True
+
+        return ret
+
+    def check_and_process_flash_lock(self, flash_status):
+        follow_up_action = self.setting.flash_protection_process
+
+        ret = self.check_flash_lock(flash_status)
+        if ret != ErrType.OK:
+            self.logger.error(f"Flash protection check fail: {ret}")
+
+        if flash_status.is_locked:
+            self.logger.warning("Flash block protection detected")
+
+            if follow_up_action == RtSettings.FLASH_PROTECTION_PROCESS_PROMPT:
+                self.logger.info(f"Follow-up Actions:")
+                self.logger.info(f"1: Try operation with block protected(may fail)")
+                self.logger.info(f"2: Remove the protection and restore the protection after operation")
+                self.logger.info(f"3: Abort the operation")
+                retry = 0
+                while retry < 3:
+                    try:
+                        follow_up_action = int(input("Please Input the selected action index: ").strip())
+                        if RtSettings.FLASH_PROTECTION_PROCESS_PROMPT < follow_up_action <= RtSettings.FLASH_PROTECTION_PROCESS_ABORT:
+                            break
+                        else:
+                            self.logger.info(f"{follow_up_action} is invalid")
+                    except Exception as err:
+                        self.logger.error(f"Input is invalid: {err}")
+                        continue
+                else:
+                    return ErrType.SYS_PARAMETER
+
+            if follow_up_action == RtSettings.FLASH_PROTECTION_PROCESS_UNLOCK:
+                flash_status.need_unlock = True
+                self.logger.info("Remove the flash block protection...")
+                ret = self.unlock_flash()
+                if ret != ErrType.OK:
+                    self.logger.error(f"Fail to remove the flash lock protection: {ret}")
+                    return ret
+            elif follow_up_action == RtSettings.FLASH_PROTECTION_PROCESS_ABORT:
+                self.logger.warning(f"Operation aborted for block protection")
+                return ErrType.SYS_CANCEL
+            else:
+                self.logger.warning(f"Trying to operate with block protection")
+                return ErrType.SYS_PARAMETER
+
+        return ret
+
+    def unlock_flash(self):
+        return self.lock_flash(0)
+
+    def lock_flash(self, protection):
+        if self.device_info.is_boot_from_nand():
+            cmd = FlashUtils.NandCmdSetFeatures.value
+            address = FlashUtils.NandRegProtection.value
+        else:
+            cmd = FlashUtils.NorCmdWriteStatusReg1.value
+            address = 0
+
+        ret = self.write_flash_status_register(cmd, address, protection)
+
+        return ret
+
+    def read_flash_status_register(self, cmd, address):
+        return self.floader_handler.read_status_register(cmd, address)
+
+    def write_flash_status_register(self, cmd, address, status):
+        return self.floader_handler.write_status_register(cmd, address, status)
+
+    def dtr_rts_timing_mapping(self, timing_list):
+        ret = ErrType.OK
+
+        if not self.serial_port.is_open:
+            return ErrType.SYS_IO
+
+        dtr = self.serial_port.dtr
+        rts = self.serial_port.rts
+
+        for key_val in timing_list:
+            for key, val in key_val.items():
+                if key.upper() == "DTR":
+                    self.serial_port.dtr = (val != 0)
+                elif key.upper() == "RTS":
+                    self.serial_port.rts = (val != 0)
+                elif key.upper() == "DELAY":
+                    time.sleep(val / 1000)
+                else:
+                    self.logger.error(f"Unsupport DTR/RTS timing type: [{key}: {val}]")
+
+        self.serial_port.dtr = dtr
+        self.serial_port.rts = rts
+
+        return ret
+
+    def auto_enter_download_mode(self):
+        ret = ErrType.OK
+
+        if not self.serial_port.is_open:
+            return ErrType.SYS_IO
+
+        reburn_timing_file = os.path.join(RtkUtils.get_executable_root_path(), self.setting.auto_switch_to_download_mode_with_dtr_rts_file)
+        if os.path.exists(reburn_timing_file):
+            reburn_timing = ConfigUtils.get_key_value_pairs(self.logger, reburn_timing_file)
+            try:
+                if reburn_timing:
+                    ret = self.dtr_rts_timing_mapping(reburn_timing)
+            except Exception as err:
+                self.logger.error(f"Fail to auto enter download mode: {err}")
+                ret = ErrType.SYS_IO
+        else:
+            self.logger.debug(f"{reburn_timing_file} is not exists!")
+
+        return ret
+
+    def auto_reset_device(self):
+        ret = ErrType.OK
+
+        if not self.serial_port.is_open:
+            return ErrType.SYS_IO
+
+        reset_timing_file = os.path.join(RtkUtils.get_executable_root_path(), self.setting.auto_reset_device_with_dtr_rts_file)
+        if os.path.exists(reset_timing_file):
+            reset_timing = ConfigUtils.get_key_value_pairs(self.logger, reset_timing_file)
+            try:
+                if reset_timing:
+                    ret = self.dtr_rts_timing_mapping(reset_timing)
+            except Exception as err:
+                self.logger.error(f"Fail to reset device: {err}")
+                ret = ErrType.SYS_IO
+        else:
+            self.logger.debug(f"{reset_timing_file} is not exists!")
+
+        return ret
+
+    def post_process(self):
+        ret = ErrType.OK
+
+        post_process_str = self.setting.post_process.strip().upper()
+        try:
+            next_op = NextOpType[post_process_str]
+            self.logger.debug(f"Next option: {next_op}")
+        except KeyError:
+            self.logger.error(f"No matching enum found for {post_process_str}")
+            next_op = NextOpType.NONE
+
+        if next_op != NextOpType.NONE:
+            if (next_op == NextOpType.RESET) and (not self.is_usb) and (self.setting.auto_reset_device_with_dtr_rts != 0):
+                self.logger.debug(f"Reset device with DTR/RTS...")
+                ret = self.auto_reset_device()
+                if ret != ErrType.OK:
+                    self.logger.warning(f"Reset device with DTR/RTS fail: {ret}")
+            else:
+                if next_op == NextOpType.RESET:
+                    self.logger.info(f"Reset device without DTR/RTS")
+
+                ret = self.floader_handler.next_operation(next_op, 0)
+                if ret != ErrType.OK:
+                    self.logger.warning(f"Next option {next_op} fail: {ret}")
+
+        return ret
+
+    def check_protocol(self):
+        ret = True
+
+        if (not self.is_usb) and self.setting.disable_nand_access_with_uart == 1:
+            self.logger.warning(
+                f"NAND access via UART is not allowed, please check the COM port and make sure the device profile matches the attached device!")
+            ret = False
+
+        return ret
+
+    def check_protocol_for_download(self):
+        ret = True
+        has_nand = False
+
+        for image_info in self.profile_info.images:
+            if (image_info.memory_type == MemoryInfo.MEMORY_TYPE_NAND):
+                has_nand = True
+                break
+
+        if has_nand:
+            ret = self.check_protocol()
+
+        return ret
+
+    def _process_image(self, img_name):
+        if img_name.strip().startswith(("A:", "B:")):
+            img_name = img_name.split(":")[1].split("(")[0].strip()
+        if img_name.endswith(".dtb"):
+            img_path_files = os.listdir(self.image_path)
+            for img_f in img_path_files:
+                self.logger.debug(img_f)
+                if img_f.endswith(".dtb") and os.path.isfile(os.path.join(self.image_path, img_f)):
+                    img_name = img_f
+                    break
+            else:
+                img_name = None
+
+        return img_name
+
+    def verify_images(self):
+        ret = ErrType.OK
+        image_selected = False
+
+        all_images = self.profile_info.images
+        if self.download_img_info:
+            all_images = self.download_img_info
+
+        for image_info in all_images:
+            if not image_info.mandatory:
+                continue
+            if not self.download_img_info:
+                image_name = self._process_image(image_info.image_name)
+                if image_name is None:
+                    self.logger.error(f"Cannot find a valid {image_name} for download")
+                    ret = ErrType.SYS_PARAMETER
+                    break
+                image_path = os.path.realpath(os.path.join(self.image_path, image_name))
+            else:
+                image_name = os.path.basename(image_info.image_name)
+                image_path = image_info.image_name
+
+            if not os.path.exists(image_path):
+                self.logger.error(f"Image file {image_name} dose not exist: {image_path}")
+                ret = ErrType.SYS_PARAMETER
+                break
+
+            if image_info.start_address < 0:
+                self.logger.error(f"Start address is not valid specified for image {image_name}")
+                ret = ErrType.SYS_PARAMETER
+                break
+            if image_info.end_address < 0:
+                self.logger.error(f"End address is not valid specified for image {image_name}")
+                ret = ErrType.SYS_PARAMETER
+                break
+            if image_info.start_address >= image_info.end_address:
+                self.logger.error(
+                    f"Invalid address range {image_info.start_address}-{image_info.end_address} for {image_name}")
+                ret = ErrType.SYS_PARAMETER
+                break
+            image_size = os.path.getsize(image_path)
+            if image_size > (image_info.end_address - image_info.start_address):
+                self.logger.error(
+                    f"Image file {image_path} is too large for {image_name}, please adjust the memory layout")
+                ret = ErrType.SYS_PARAMETER
+                break
+
+            is_start_address_in_ram = self.profile_info.is_ram_address(image_info.start_address)
+            is_end_address_in_ram = self.profile_info.is_ram_address(image_info.end_address)
+            if (((self.memory_type == MemoryInfo.MEMORY_TYPE_RAM) and (
+                    (not is_start_address_in_ram) or (not is_end_address_in_ram))) or
+                    ((self.memory_type == MemoryInfo.MEMORY_TYPE_NOR) and (
+                            is_start_address_in_ram or is_end_address_in_ram))):
+                self.logger.error(
+                    f"Invalid address range {image_info.start_address}-{image_info.end_address} for {image_name}")
+                ret = ErrType.SYS_PARAMETER
+                break
+            if not is_start_address_in_ram:
+                self.is_all_ram = False
+
+            image_selected = True
+        else:
+            if not image_selected:
+                self.logger.warning(f"No image selected!")
+                ret = ErrType.SYS_PARAMETER
+
+        return ret
+
+    def post_verify_images(self):
+        ret = ErrType.OK
+
+        max_addr = self.profile_info.flash_start_address + self.device_info.flash_capacity
+        image_dowload_list = self.download_img_info if self.download_img_info else self.profile_info.images
+        for image_info in image_dowload_list:
+            is_ram = self.profile_info.is_ram_address(image_info.start_address)
+            if not is_ram:
+                if (image_info.start_address > max_addr) or (image_info.end_address > max_addr):
+                    self.logger.error(f"Invalid layout, image {image_info.image_name} address overflow")
+                    ret = ErrType.SYS_OVERRANGE
+                    break
+                if (self.device_info.is_boot_from_nand() and
+                        (((image_info.start_address % self.device_info.flash_block_size()) != 0) or
+                         ((image_info.end_address % self.device_info.flash_block_size()) != 0))):
+                    self.logger.error(f"{image_info.image_name} address range not aligned")
+                    ret = ErrType.SYS_PARAMETER
+                    break
+        return ret
+
+    def validate_config_for_erase(self):
+        ret = ErrType.OK
+
+        if self.erase_info:
+            if ((self.profile_info.memory_type == MemoryInfo.MEMORY_TYPE_NAND) and (
+                    self.memory_type == MemoryInfo.MEMORY_TYPE_NOR)) or \
+                    ((self.profile_info.memory_type == MemoryInfo.MEMORY_TYPE_NOR) and (
+                            self.memory_type == MemoryInfo.MEMORY_TYPE_NAND)):
+                self.logger.error("Unsupported memory type.")
+                ret = ErrType.SYS_PARAMETER
+                return ret
+
+            if (self.memory_type == MemoryInfo.MEMORY_TYPE_RAM) and (not self.profile_info.is_ram_address(self.erase_info.start_address)):
+                self.logger.error(f"Invalid RAM start address: {self.erase_info.start_address}")
+                ret = ErrType.SYS_PARAMETER
+                return ret
+            elif (self.memory_type != MemoryInfo.MEMORY_TYPE_RAM) and \
+                    (not ((self.profile_info.memory_type == MemoryInfo.MEMORY_TYPE_NAND) or self.profile_info.is_flash_address(self.erase_info.start_address))):
+                self.logger.error(f"Invalid start address: {self.erase_info.start_address}")
+                ret = ErrType.SYS_PARAMETER
+                return ret
+
+            if (self.memory_type == MemoryInfo.MEMORY_TYPE_NOR):
+                if not self.is_address_block_aligned(self.erase_info.start_address):
+                    self.logger.warning(f"NOR flash start address should be aligned to {FlashUtils.NorDefaultBlockSize.value}B.")
+                    ret = ErrType.SYS_PARAMETER
+                    return ret
+                if (self.erase_info.size_in_kbyte != 0xFFFFFFFF) and (not self.is_address_block_aligned(self.erase_info.size_in_byte())):
+                    self.logger.warning(f"NOR flash erase size should be aligned to {FlashUtils.NorDefaultBlockSize.value}B.")
+                    ret = ErrType.SYS_PARAMETER
+                    return ret
+                self.logger.info(f"NOR flash erase: start address={hex(self.erase_info.start_address)}, size={self.erase_info.size_in_kbyte}KB.")
+            else:
+                if not self.is_address_block_aligned(self.erase_info.start_address):
+                    self.logger.warning(f"NAND flash start address should be block size aligned!")
+                    ret = ErrType.SYS_PARAMETER
+                    return ret
+                if not self.is_address_block_aligned(self.erase_info.end_address):
+                    self.logger.warning(f"NAND flash end address should be block size aligned!")
+                    ret = ErrType.SYS_PARAMETER
+                    return ret
+                if (self.erase_info.end_address <= self.erase_info.start_address):
+                    self.logger.warning(f"NAND flash start address should be less than end address!")
+                    ret = ErrType.SYS_PARAMETER
+                    return ret
+
+                self.logger.info(f"NAND flash erase: start address={hex(self.erase_info.start_address)}, end address={hex(self.erase_info.end_address)}")
+
+        return ret
+
+    def check_protocol_for_erase(self):
+        ret = True
+
+        if (not self.is_usb) and (self.erase_info.memory_type == MemoryInfo.MEMORY_TYPE_NAND) and (
+                self.setting.disable_nand_access_with_uart == 1):
+            ret = False
+            self.logger.warning(
+                f"NAND access via UART is not allowed, please check the COM port and make sure the device profile matches the attached device!")
+        return ret
+
+    def is_address_block_aligned(self, address):
+        ret = False
+
+        if self.device_info:
+            block_size = self.device_info.flash_block_size()
+            ret = ((address % block_size) == 0)
+
+        return ret
+
+    def post_validate_config_for_erase(self):
+        ret = ErrType.OK
+
+        if self.erase_info and (not self.profile_info.is_ram_address(self.erase_info.start_address)):
+            if not self.is_address_block_aligned(self.erase_info.start_address):
+                ret = ErrType.SYS_PARAMETER
+                self.logger.warning(
+                    f"Flash start address should be aligned to block size {self.device_info.flash_block_size()}KB")
+            if self.erase_info.memory_type == MemoryInfo.MEMORY_TYPE_NAND and (
+                    not self.is_address_block_aligned(self.erase_info.end_address)):
+                ret = ErrType.SYS_PARAMETER
+                self.logger.warning(
+                    f"Flash end address should be aligned to block size {self.device_info.flash_block_size()}KB")
+            if self.erase_info.memory_type == MemoryInfo.MEMORY_TYPE_NOR and (
+                    not self.is_address_block_aligned(self.erase_info.size_in_byte())):
+                ret = ErrType.SYS_PARAMETER
+                self.logger.warning(
+                    f"Flash size should be aligned to block size {self.device_info.flash_block_size()}KB")
+        return ret
+
+    def calculate_checksum(self, image):
+        with open(image, 'rb') as stream:
+            img_content = stream.read()
+        img_len = len(img_content)
+        img_arr = list(img_content)
+        chksum = 0
+        offset = 0
+        while (img_len - offset) > 3:
+            chksum += (img_arr[offset + 0] | (img_arr[offset + 1] << 8) | (img_arr[offset + 2] << 16) | (
+                    img_arr[offset + 3] << 24))
+            offset += 4
+
+        tmp = 0
+        while (img_len - offset - tmp) > 0:
+            chksum += img_arr[offset + tmp] << (8 * tmp)
+            tmp += 1
+
+        chksum = chksum & 0xffffffff
+        return chksum
+
+    def erase_flash_chip(self):
+        self.logger.info(f"Chip erase start")  # customized, do not modify
+        ret = self.floader_handler.erase_flash(MemoryInfo.MEMORY_TYPE_NOR, RtkDeviceProfile.DEFAULT_FLASH_START_ADDR,
+                                               0, 0xFFFFFFFF,
+                                               nor_erase_timeout_in_second(0xFFFFFFFF),
+                                               sense=True, force=False)
+        self.logger.info(f"Chip erase end")
+        return ret
+
+    def download_images(self):
+        ret = ErrType.OK
+
+        # support chip erase
+        if self.chip_erase and (self.memory_type == MemoryInfo.MEMORY_TYPE_NOR):
+            ret = self.erase_flash_chip()
+            if ret != ErrType.OK:
+                self.logger.error(f"Chip erase fail")
+                return ret
+
+        if self.download_img_info:
+            for image_info in self.download_img_info:
+                img_path = image_info.image_name
+                img_name = os.path.basename(img_path)
+                image_info.image_name = img_name
+
+                self.logger.info(f"{img_name} download...")
+                ret = self._download_image(img_path, image_info)
+                if ret != ErrType.OK:
+                    self.logger.info(f"{img_name} download fail: {ret}")
+                    break
+        else:
+            is_area_A = False
+            is_area_B = False
+            for image_info in self.profile_info.images:
+                is_mandatory = image_info.mandatory
+                if not is_mandatory:
+                    continue
+                img_name = image_info.image_name
+                self.logger.info(f"{img_name} download...")
+                if img_name.strip().startswith(("A:", "a_")):
+                    is_area_A = True
+                elif img_name.strip().startswith(("B:", "b_")):
+                    is_area_B = True
+
+                if is_area_A and is_area_B:
+                    self.logger.error(f"NOT support both A and B download at the same time")
+                    ret = ErrType.SYS_PARAMETER
+                    break
+
+                img_name = self._process_image(img_name)
+                img_path = os.path.realpath(os.path.join(self.image_path, img_name))
+                ret = self._download_image(img_path, image_info)
+                if ret != ErrType.OK:
+                    self.logger.info(f"{img_name} download fail: {ret}")
+                    break
+
+        if ret == ErrType.OK:
+            self.logger.info("All images download done")
+
+        return ret
+
+    def get_page_alligned_size(self, size, page_size):
+        result = size
+
+        if (size % page_size) != 0:
+            result = (size // page_size + 1) * page_size
+
+        return result
+
+    def _download_image(self, image_path, image_info):
+        ret = ErrType.OK
+
+        page_size = self.device_info.flash_page_size
+        block_size = self.device_info.flash_block_size()
+        pages_per_block = self.device_info.flash_pages_per_block
+        last_erase_addr = 0
+        next_erase_addr = 0
+        checksum = 0
+        write_timeout = 0
+        is_ram = (image_info.memory_type == MemoryInfo.MEMORY_TYPE_RAM)
+        padding_byte_val = self.setting.ram_download_padding_byte if is_ram else FlashUtils.FlashWritePaddingData.value
+        padding_char = padding_byte_val.to_bytes(1, byteorder="little")
+
+        start_time = datetime.now()
+
+        try:
+            img_length = os.path.getsize(image_path)
+        except OSError as e:
+            self.logger.error(f"Failed to get file size: {e}")
+            return ErrType.SYS_PARAMETER
+
+        aligned_img_length = self.get_page_alligned_size(img_length, page_size)
+
+        self.logger.debug(
+            f"Image download size={aligned_img_length}({img_length}), start_addr={hex(image_info.start_address)}, "
+            f"end_addr={hex(image_info.end_address)}")
+
+        addr = image_info.start_address
+        tx_sum = 0
+
+        with open(image_path, 'rb') as file_stream:
+            if ((image_info.memory_type == MemoryInfo.MEMORY_TYPE_NAND) or (
+                    is_ram and (self.profile_info.memory_type == MemoryInfo.MEMORY_TYPE_NAND))):
+
+                write_timeout = nand_program_timeout_in_second(block_size,
+                                                               page_size) + FlashUtils.NandBlockEraseTimeoutInSeconds.value
+
+                is_last_page = False
+                progress_int = 0
+
+                while not is_last_page:
+                    if addr >= image_info.end_address:
+                        self.logger.debug(f"Overrange target={hex(addr)}, end={hex(image_info.end_address)}")
+                        ret = ErrType.SYS_OVERRANGE
+                        break
+
+                    ret = self.floader_handler.erase_flash(image_info.memory_type, addr, addr + block_size, block_size,
+                                                           nand_erase_timeout_in_second(block_size, block_size),
+                                                           sense=(not is_ram))
+                    if ret == ErrType.DEV_NAND_BAD_BLOCK.value or ret == ErrType.DEV_NAND_WORN_BLOCK.value:
+                        self.logger.info(
+                            f"{'Bad' if ret == ErrType.DEV_NAND_BAD_BLOCK else 'Worn'} block: 0x{format(addr, '08X')}")
+                        addr += self.device_info.flash_block_size()
+                        next_erase_addr = addr
+                        continue
+                    elif ret != ErrType.OK:
+                        break
+
+                    next_erase_addr = addr + self.device_info.flash_block_size()
+
+                    i = 0
+                    while i < pages_per_block:
+                        chunk_data = file_stream.read(page_size)
+                        read_len = len(chunk_data)
+
+                        if read_len <= 0:
+                            is_last_page = True
+                        else:
+                            if read_len < page_size:
+                                is_last_page = True
+                                chunk_data += padding_char * (page_size - read_len)
+
+                            if tx_sum + page_size >= aligned_img_length:
+                                is_last_page = True
+
+                            need_sense = (is_last_page or (i == pages_per_block - 1))
+
+                            ret = self.floader_handler.write(image_info.memory_type, chunk_data,
+                                                             page_size, addr, write_timeout, need_sense=need_sense)
+                            if ret == ErrType.OK:
+                                # 新的极速计算方式 (利用 C 语言层加速)
+                                # '<' 代表小端模式，'I' 代表 unsigned int (4字节)
+                                # len(chunk_data)//4 计算出有多少个整数
+                                fmt = f'<{len(chunk_data) // 4}I'
+                                checksum = (checksum + sum(struct.unpack(fmt, chunk_data))) & 0xFFFFFFFF
+
+                                addr += page_size
+                                tx_sum += page_size
+                            else:
+                                self.logger.error(f"Write to addr={format(addr, '08x')}, size={page_size} fail: {ret}")
+                                break
+
+                        if is_last_page:
+                            break
+
+                        i += 1
+
+                    progress = int((tx_sum / aligned_img_length) * 100)
+                    if int((progress) / 10) != progress_int:
+                        progress_int += 1
+                        self.logger.info(f"Programming progress: {progress}%")
+
+                    if ret != ErrType.OK:
+                        break
+
+                if ret == ErrType.OK:
+                    if image_info.full_erase and (next_erase_addr < image_info.end_address):
+                        self.logger.debug(
+                            f"Erase extra address range: {hex(next_erase_addr)}-{hex(image_info.end_address)}")
+                        ret = self.floader_handler.erase_flash(image_info.memory_type, next_erase_addr,
+                                                               image_info.end_address,
+                                                               (image_info.end_address - next_erase_addr),
+                                                               nand_erase_timeout_in_second(
+                                                                   (image_info.end_address - next_erase_addr),
+                                                                   block_size),
+                                                               sense=True)
+                        if ret == ErrType.DEV_NAND_BAD_BLOCK.value or ret == ErrType.DEV_NAND_WORN_BLOCK.value:
+                            self.logger.debug(
+                                f"{'Bad' if ret == ErrType.DEV_NAND_BAD_BLOCK else 'Worn'} block: {hex(addr)}")
+                            ret = ErrType.OK
+                        elif ret != ErrType.OK:
+                            self.logger.error(f"Fail to erase block {hex(addr)}:{ret}")
+
+                    if tx_sum >= aligned_img_length:
+                        if aligned_img_length < 1024:
+                            self.logger.debug(f"Image download done: {aligned_img_length}bytes")
+                        elif aligned_img_length < 1024 * 1024:
+                            self.logger.debug(f"Image download done: {aligned_img_length // 1024}KB")
+                        else:
+                            self.logger.debug(
+                                f"Image download done: {round(aligned_img_length / 1024 / 1024, 2)}MB")
+                    else:
+                        self.logger.warning(f"Image download uncompleted: {tx_sum}/{aligned_img_length}")
+
+                    elapse_ms = round((datetime.now() - start_time).total_seconds() * 1000, 0)
+                    kbps = aligned_img_length * 8 // elapse_ms
+                    size_kb = aligned_img_length // 1024
+
+                    if self.is_usb:
+                        self.logger.info(
+                            f"{image_info.image_name} download done: {size_kb}KB / {elapse_ms}ms / {kbps / 1000}Mbps")
+                    else:
+                        self.logger.info(
+                            f"{image_info.image_name} download done: {size_kb}KB / {elapse_ms}ms / {kbps}Kbps")
+            else:
+                write_pages = 0
+                progress_int = 0
+
+                chunk_data = file_stream.read(page_size)
+                read_len = len(chunk_data)
+
+                if read_len < page_size:
+                    chunk_data += padding_char * (page_size - read_len)
+
+                while read_len > 0:
+                    if write_pages == 0:
+                        if (addr % (64 * FlashUtils.NorDefaultPageSize.value)) == 0 and \
+                                ((aligned_img_length - tx_sum >= 64 * FlashUtils.NorDefaultPageSize.value)):
+                            block_size = 64 * FlashUtils.NorDefaultPageSize.value
+                        elif (addr % (32 * FlashUtils.NorDefaultPageSize.value)) == 0 and \
+                                ((aligned_img_length - tx_sum >= 32 * FlashUtils.NorDefaultPageSize.value)):
+                            block_size = 32 * FlashUtils.NorDefaultPageSize.value
+                        else:
+                            block_size = 4 * FlashUtils.NorDefaultPageSize.value
+
+                        pages_per_block = block_size // page_size
+                        erase_addr = addr
+                        write_timeout = FlashUtils.NorPageProgramTimeoutInSeconds.value * int(
+                            max(self.setting.sense_packet_count, pages_per_block)) + nor_erase_timeout_in_second(
+                            divide_then_round_up(block_size, 1024))
+
+                        if erase_addr != last_erase_addr:
+                            if self.chip_erase:
+                                erase_size = 0
+                            else:
+                                erase_size = block_size
+                            if (not is_ram) and (erase_addr % block_size) != 0:
+                                self.logger.error(
+                                    f"Flash erase address align error: addr {hex(erase_addr)} not aligned to block size {hex(block_size)}")
+                                ret = ErrType.SYS_PARAMETER
+                                break
+
+                            ret = self.floader_handler.erase_flash(image_info.memory_type, erase_addr,
+                                                                   erase_addr + block_size, erase_size,
+                                                                   nor_erase_timeout_in_second(
+                                                                       divide_then_round_up(block_size, 1024)))
+                            if ret != ErrType.OK:
+                                break
+
+                            last_erase_addr = erase_addr
+                            next_erase_addr = erase_addr + block_size
+
+                    need_sense = ((((write_pages + 1) % self.setting.sense_packet_count) == 0) or
+                                  (write_pages + 1 >= pages_per_block) or
+                                  (tx_sum + page_size >= aligned_img_length))
+
+                    # 写入
+                    ret = self.floader_handler.write(image_info.memory_type, chunk_data,
+                                                     page_size, addr, write_timeout, need_sense=need_sense)
+                    if ret != ErrType.OK:
+                        self.logger.debug(f"Write to addr={hex(addr)} size={page_size} fail: {ret}")
+                        break
+
+                    write_pages += 1
+                    if write_pages >= pages_per_block:
+                        write_pages = 0
+
+                    # 计算 Checksum
+                    # '<' 代表小端模式，'I' 代表 unsigned int (4字节)
+                    # len(chunk_data)//4 计算出有多少个整数
+                    fmt = f'<{len(chunk_data) // 4}I'
+                    checksum = (checksum + sum(struct.unpack(fmt, chunk_data))) & 0xFFFFFFFF
+
+                    addr += page_size
+                    tx_sum += page_size
+
+                    progress = int((tx_sum / aligned_img_length) * 100)
+                    if int((progress) / 10) != progress_int:
+                        progress_int += 1
+                        self.logger.info(f"Programming progress: {progress}%")
+
+                    if tx_sum >= aligned_img_length:
+                        if self.chip_erase:
+                            erase_size = 0
+                        else:
+                            erase_size = image_info.end_address - next_erase_addr
+
+                        if image_info.full_erase and (next_erase_addr < image_info.end_address):
+                            self.logger.debug(
+                                f"Erase extra address range: {hex(next_erase_addr)}-{hex(image_info.end_address)}")
+                            ret = self.floader_handler.erase_flash(image_info.memory_type, next_erase_addr,
+                                                                   image_info.end_address,
+                                                                   erase_size,
+                                                                   nor_erase_timeout_in_second(divide_then_round_up(
+                                                                       (image_info.end_address - next_erase_addr), 1024)),
+                                                                   sense=True)
+                            if ret != ErrType.OK:
+                                self.logger.warning(
+                                    f"Fail to extra address range {hex(next_erase_addr)}-{hex(image_info.end_address)}")
+
+                        if aligned_img_length < 1024:
+                            self.logger.debug(f"Image download done: {aligned_img_length}bytes")
+                        elif aligned_img_length < 1024 * 1024:
+                            self.logger.debug(f"Image download done: {aligned_img_length // 1024}KB")
+                        else:
+                            self.logger.debug(f"Image download done: {round(aligned_img_length / 1024 / 1024, 2)}MB")
+
+                        elapse_ms = round((datetime.now() - start_time).total_seconds() * 1000, 0)
+                        kbps = aligned_img_length * 8 // elapse_ms
+                        size_kb = aligned_img_length // 1024
+
+                        if self.is_usb:
+                            self.logger.info(
+                                f"{image_info.image_name} download done: {size_kb}KB / {elapse_ms}ms / {kbps / 1000}Mbps")
+                        else:
+                            self.logger.info(f"{image_info.image_name} download done: {size_kb}KB / {elapse_ms}ms / {kbps}Kbps")
+
+                        break
+
+                    chunk_data = file_stream.read(page_size)
+                    read_len = len(chunk_data)
+
+                    if read_len < page_size:
+                        chunk_data += padding_char * (page_size - read_len)
+
+            file_stream.close()
+
+        if ret == ErrType.OK:
+            cal_checksum = 0
+            if image_info.memory_type == MemoryInfo.MEMORY_TYPE_NAND:
+                checksum_timeout = nand_checksum_timeout_in_second(aligned_img_length, None)
+            else:
+                checksum_timeout = nor_checksum_timeout_in_second(aligned_img_length)
+            ret, cal_checksum = self.floader_handler.checksum(image_info.memory_type, image_info.start_address,
+                                                              image_info.end_address, aligned_img_length,
+                                                              checksum_timeout)
+            if ret == ErrType.OK:
+                if cal_checksum != checksum:
+                    self.logger.debug(f"Checksum fail: expect {hex(checksum)} get {hex(cal_checksum)}")
+                    ret = ErrType.SYS_CHECKSUM
+
+        return ret
+
+    def erase_flash(self):
+        ret = ErrType.OK
+
+        if self.erase_info.memory_type == MemoryInfo.MEMORY_TYPE_NAND:
+            erase_total_size = self.erase_info.end_address - self.erase_info.start_address
+            erase_size = 0
+            addr = self.erase_info.start_address
+            while addr < self.erase_info.end_address:
+                ret = self.floader_handler.erase_flash(self.erase_info.memory_type,
+                                                       addr,
+                                                       addr + self.device_info.flash_block_size(),
+                                                       self.device_info.flash_block_size(),
+                                                       nand_erase_timeout_in_second(self.device_info.flash_block_size(),
+                                                                                    self.device_info.flash_block_size()),
+                                                       sense=True)
+                if ret == ErrType.OK:
+                    erase_size += self.device_info.flash_block_size()
+                    # TODO：update erase progress
+                    # self.logger.info(f"Erase progress: {int()}")
+                    self.logger.debug(
+                        f"NAND erase address  ={hex(addr)}, size = {self.device_info.flash_block_size() / 1024}KB OK")
+                elif ret == ErrType.DEV_NAND_BAD_BLOCK:
+                    self.logger.warning(
+                        f"NAND erase address = {hex(addr)} size = {self.device_info.flash_block_size() / 1024}KB skipped: bad block")
+                    ret = ErrType.OK
+                elif ret == ErrType.DEV_NAND_WORN_BLOCK:
+                    self.logger.warning(
+                        f"NAND erase address = {hex(addr)} size = {self.device_info.flash_block_size() / 1024}KB failed: mark warning block")
+                    ret = ErrType.OK
+                else:
+                    self.logger.warning(
+                        f"NAND erase address = {hex(addr)} size = {self.device_info.flash_block_size() / 1024}KB failed: {ret}")
+                    break
+                addr += self.device_info.flash_block_size()
+
+            if ret == ErrType.OK:
+                self.logger.info(f"Erase nand done")
+        elif self.erase_info.memory_type == MemoryInfo.MEMORY_TYPE_NOR:
+            if self.setting.erase_by_block != 0:
+                addr = self.erase_info.start_address
+                size_erased = 0
+                while size_erased < self.erase_info.size_in_byte():
+                    if ((addr % (64 * FlashUtils.NorDefaultPageSize.value)) == 0) and \
+                            ((
+                                     self.erase_info.size_in_byte() - size_erased) >= 64 * FlashUtils.NorDefaultPageSize.value):
+                        block_size = 64 * FlashUtils.NorDefaultPageSize.value
+                    elif ((addr % (32 * FlashUtils.NorDefaultPageSize.value)) == 0) and \
+                            ((
+                                     self.erase_info.size_in_byte() - size_erased) >= 32 * FlashUtils.NorDefaultPageSize.value):
+                        block_size = 32 * FlashUtils.NorDefaultPageSize.value
+                    else:
+                        block_size = 4 * FlashUtils.NorDefaultPageSize.value
+
+                    need_sense = ((size_erased + block_size) >= self.erase_info.size_in_byte())
+                    ret = self.floader_handler.erase_flash(self.erase_info.memory_type, addr, addr + block_size,
+                                                           block_size,
+                                                           nor_erase_timeout_in_second(
+                                                               divide_then_round_up(block_size, 1024)),
+                                                           sense=need_sense)
+                    if ret != ErrType.OK:
+                        break
+
+                    addr += block_size
+                    size_erased += block_size
+                    # TODO：update erase progress
+                    # self.logger.info(f"Erase Progress: {}")
+            else:
+                ret = self.floader_handler.erase_flash(self.erase_info.memory_type,
+                                                       self.erase_info.start_address,
+                                                       self.erase_info.end_address,
+                                                       self.erase_info.size_in_kbyte,
+                                                       nor_erase_timeout_in_second(
+                                                           divide_then_round_up(self.erase_info.size_in_byte(), 1024)),
+                                                       sense=True)
+                if ret == ErrType.OK:
+                    self.logger.info(f"Erase nor done")
+        elif self.erase_info.memory_type == MemoryInfo.MEMORY_TYPE_RAM:
+            # memset 16MB ram, cost time: 0.01s
+            ret = self.floader_handler.erase_flash(self.erase_info.memory_type,
+                                                   self.erase_info.start_address,
+                                                   self.erase_info.end_address,
+                                                   self.erase_info.size_in_byte(),
+                                                   self.setting.sync_response_timeout_in_second,
+                                                   sense=True)
+            if ret == ErrType.OK:
+                self.logger.info("Erase ram done")
+        else:
+            # TBD
+            pass
+
+        return ret
+
+    def set_spic_address_mode(self, mode):
+        ret = ErrType.OK
+        is_amebad = self.profile_info.is_amebad()
+        otp_spic_addr_mode_addr = OtpSpicAddrModeAddrForAmebaD if is_amebad else OtpSpicAddrModeAddr
+        otp_spic_addr_mode_mask = OtpSpicAddrModeMask if is_amebad else OtpSpicAddrModeMask
+        otp_spic_addr_mode_pos = OtpSpicAddrModePosForAmebaD if is_amebad else OtpSpicAddrModePos
+
+        if self.device_info.is_boot_from_nand():
+            return ret
+
+        ret, buf = self.floader_handler.otp_read_logical_map(0, self.profile_info.logical_efuse_len)
+        if ret != ErrType.OK:
+            self.logger.error(f"Fail to read eFuse: {ret}")
+            return
+
+        cfg = buf[otp_spic_addr_mode_addr]
+        if cfg != 0xFF:
+            if ((cfg & otp_spic_addr_mode_mask) >> otp_spic_addr_mode_pos) == mode:
+                self.logger.info(f"No need to change supported flash size")
+                return ErrType.OK
+
+            cfg &= (~otp_spic_addr_mode_mask)
+            cfg |= ((mode << otp_spic_addr_mode_pos) & otp_spic_addr_mode_mask)
+        else:
+            if mode == SpicAddrMode.FOUR_BYTE_MODE.value:
+                cfg = OtpSpicAddrMode4Byte
+            else:
+                self.logger.info(f"No need to change default supported flash size")
+                return ErrType.OK
+
+        # buf[otp_spic_addr_mode_addr] = cfg
+        buf_array = bytearray(buf)
+        buf_array[otp_spic_addr_mode_addr] = cfg
+        buf = bytes(buf_array)
+        self.logger.info(f"Program eFuse to change supported flash size {'>' if (mode == SpicAddrMode.FOUR_BYTE_MODE.value) else '<='}16MB")
+
+        ret = self.floader_handler.otp_write_logical_map(otp_spic_addr_mode_addr, 1, buf)
+        if ret != ErrType.OK:
+            self.logger.error(f"Fail to program eFuse[{otp_spic_addr_mode_addr}]: {ret}")
+            return ret
+        time.sleep(0.01)
+
+        ret, buf = self.floader_handler.otp_read_logical_map(0, self.profile_info.logical_efuse_len)
+        if ret != ErrType.OK:
+            self.logger.error(f"Fail to read eFuse: {ret}")
+            return ret
+
+        cfg = buf[otp_spic_addr_mode_addr]
+        if ((cfg & otp_spic_addr_mode_mask) >> otp_spic_addr_mode_pos) == mode:
+            self.logger.info(f"Program eFuse done")
+            return ErrType.OK
+        else:
+            self.logger.error(f"Fail to verify eFuse[{otp_spic_addr_mode_addr}]")
+            self.logger.error(f"Fail to program eFuse")
+            return ErrType.SYS_CHECKSUM
+
+    def get_spic_address_mode(self):
+        ret = ErrType.OK
+        is_amebad = self.profile_info.is_amebad()
+        otp_spic_addr_mode_addr = OtpSpicAddrModeAddrForAmebaD if is_amebad else OtpSpicAddrModeAddr
+        otp_spic_addr_mode_mask = OtpSpicAddrModeMask if is_amebad else OtpSpicAddrModeMask
+        otp_spic_addr_mode_4byte = OtpSpicAddrMode4ByteForAmebaD if is_amebad else OtpSpicAddrMode4Byte
+        mode = SpicAddrMode.THREE_BYTE_MODE.value
+
+        if self.device_info.is_boot_from_nand():
+            return ret, mode
+
+        ret, buf = self.floader_handler.otp_read_logical_map(0, self.profile_info.logical_efuse_len)
+        if ret != ErrType.OK:
+            self.logger.error(f"Fail to read eFuse: {ret}")
+            return ret, mode
+
+        cfg = buf[otp_spic_addr_mode_addr]
+        if cfg != 0xFF:
+            if (cfg & otp_spic_addr_mode_mask) == otp_spic_addr_mode_4byte:
+                mode = SpicAddrMode.FOUR_BYTE_MODE.value
+                self.logger.info(f"Current supported flash size >16MB")
+            else:
+                self.logger.info(f"Current supported flash size <=16MB")
+        else:
+            self.logger.info(f"Current supported flash size <=16MB as default")
+
+        return ret, mode
+
+    def check_supported_flash_size(self):
+        ret = ErrType.OK
+        reset_system = False
+
+        self.logger.info(f"Check supported flash size...")
+        ret = self.prepare(show_device_info=False)
+        if ret != ErrType.OK:
+            self.logger.error("Prepare for check supported flash size fail")
+            return ret, reset_system
+
+        ret, mode = self.get_spic_address_mode()
+        if ret != ErrType.OK:
+            return ret, reset_system
+
+        flash_size = self.device_info.flash_capacity // 1024 // 1024  # MB
+        if self.setting.auto_program_spic_addr_mode_4byte == 0:
+            if (mode == SpicAddrMode.THREE_BYTE_MODE.value) and (flash_size > 16):
+                self.logger.warning(f"Flash size: {flash_size}MB, OTP supported flash size <= 16MB")
+                ret = ErrType.SYS_CANCEL
+            if (mode == SpicAddrMode.FOUR_BYTE_MODE.value) and (flash_size <= 16):
+                self.logger.warning(f"Flash size: {flash_size}MB, OTP supported flash size >16MB")
+                ret = ErrType.SYS_CANCEL
+        else:
+            if mode == SpicAddrMode.THREE_BYTE_MODE.value and flash_size > 16:
+                self.logger.warning(f"OTP supports flash size <=16MB, tool will program OTP to support flash size >16MB")
+                ret = self.set_spic_address_mode(SpicAddrMode.FOUR_BYTE_MODE.value)
+                reset_system = True
+            elif mode == SpicAddrMode.FOUR_BYTE_MODE.value and flash_size <= 16:
+                self.logger.warning(f"OTP supports flash size >16MB, tool will program OTP to support flash size <=16MB")
+                ret = self.set_spic_address_mode(SpicAddrMode.THREE_BYTE_MODE.value)
+                reset_system = True
+
+            if reset_system:
+                boot_delay = self.setting.usb_rom_boot_delay_in_second if self.profile_info.support_usb_download else self.setting.rom_boot_delay_in_second
+                # reset floader with next option
+                self.floader_handler.next_operation(NextOpType.REBURN, 0)
+                self.logger.info(f"Reburn delay {boot_delay}s")
+                time.sleep(boot_delay)
+
+        return ret, reset_system
diff --git a/ameba/scripts/flash/base/efuse_data.py b/ameba/scripts/flash/base/efuse_data.py
new file mode 100644
index 00000000..7419aa79
--- /dev/null
+++ b/ameba/scripts/flash/base/efuse_data.py
@@ -0,0 +1,20 @@
+#! /usr/bin/env python
+# -*- coding: utf-8 -*-
+
+# Copyright (c) 2024 Realtek Semiconductor Corp.
+# SPDX-License-Identifier: Apache-2.0
+
+class EfuseData():
+    def __init__(self, **kwargs):
+        self.length = 16
+
+        self.offset = kwargs.get("Offset", 0)
+        self.value = kwargs.get("Value", [0] * self.length)
+
+    def __repr__(self):
+        efuse_data_dict = {
+            "Value": self.value,
+            "Offset": self.offset
+        }
+
+        return efuse_data_dict
diff --git a/ameba/scripts/flash/base/errno.py b/ameba/scripts/flash/base/errno.py
new file mode 100644
index 00000000..42c963e3
--- /dev/null
+++ b/ameba/scripts/flash/base/errno.py
@@ -0,0 +1,40 @@
+#! /usr/bin/env python
+# -*- coding: utf-8 -*-
+
+# Copyright (c) 2024 Realtek Semiconductor Corp.
+# SPDX-License-Identifier: Apache-2.0
+
+import enum
+
+_DEV_ERR_BASE = 0X00E0
+_SYS_ERR_BASE = 0x0100
+
+
+class ErrType(enum.Enum):
+    OK = 0X00
+
+    DEV_ERR_BASE = _DEV_ERR_BASE
+
+    DEV_BUSY = _DEV_ERR_BASE + 0X1  # Busy
+    DEV_TIMEOUT = _DEV_ERR_BASE + 0X2  # Operation timeout
+    DEV_FULL = _DEV_ERR_BASE + 0X4  # Operation timeout
+    DEV_INVALID = _DEV_ERR_BASE + 0x5  # device invalid
+    DEV_LENGTH = _DEV_ERR_BASE + 0x6  # device length
+    DEV_CHECKSUM = _DEV_ERR_BASE + 0x7  # device checksum
+    DEV_ADDRESS = _DEV_ERR_BASE + 0x8  # device address
+    DEV_NAND_BAD_BLOCK = _DEV_ERR_BASE + 0x9  # device nand bad block
+    DEV_NAND_WORN_BLOCK = _DEV_ERR_BASE + 0xA   # device nand worn block
+    DEV_NAND_BIT_FLIP_WARNING = _DEV_ERR_BASE + 0xB  # device nand bit flip warning
+    DEV_NAND_BIT_FLIP_ERROR = _DEV_ERR_BASE + 0xC  # device nand bit flip error
+    DEV_NAND_BIT_FLIP_FATAL = _DEV_ERR_BASE + 0xD  # device nand bit flip fatal
+
+    SYS_ERR_BASE = _SYS_ERR_BASE
+    SYS_TIMEOUT = _SYS_ERR_BASE + 0x02  # Operation timeout
+    SYS_PARAMETER = _SYS_ERR_BASE + 0X3  # Invalid parameter
+    SYS_IO = _SYS_ERR_BASE + 0x05  # IO error
+    SYS_NAK = _SYS_ERR_BASE + 0x15  # Device NAK
+    SYS_PROTO = _SYS_ERR_BASE + 0x22  # Protocol error
+    SYS_CHECKSUM = _SYS_ERR_BASE + 0x23  # checksum error
+    SYS_OVERRANGE = _SYS_ERR_BASE + 0x24  # operation overrange
+    SYS_CANCEL = _SYS_ERR_BASE + 0x30  # Operation cancelled
+    SYS_UNKNOWN = _SYS_ERR_BASE + 0xEE  # Unknown error
diff --git a/ameba/scripts/flash/base/flash_utils.py b/ameba/scripts/flash/base/flash_utils.py
new file mode 100644
index 00000000..52e7896d
--- /dev/null
+++ b/ameba/scripts/flash/base/flash_utils.py
@@ -0,0 +1,145 @@
+#! /usr/bin/env python
+# -*- coding: utf-8 -*-
+
+# Copyright (c) 2024 Realtek Semiconductor Corp.
+# SPDX-License-Identifier: Apache-2.0
+
+from enum import Enum
+from .sys_utils import *
+
+
+class FlashBPS:
+    def __init__(self):
+        self.need_unlock = False
+        self.protection = 0
+        self.is_locked = False
+
+
+class FlashUtils(Enum):
+    # NAND Flash MID
+    NandMfgDosilicon = 0xE5
+    NandMfgGigadevice = 0xC8
+    NandMfgMacronix = 0xC2
+    NandMfgMicron = 0x2C
+    NandMfgWinbond = 0xEF
+
+    # NAND Flash commands
+    NandCmdGetFeatures = 0x0F
+    NandCmdSetFeatures = 0x1F
+
+    # NAND Flash registers
+    NandRegProtection = 0xA0
+    NandRegFeature = 0xB0
+    NandRegStatus = 0xC0
+    NandRegProtectionBpMask = 0x38
+    NandRegProtectionBpMaskWinbondMicron = 0x78
+
+    # NOR Flash command & registers
+    NorCmdReadStatusReg1 = 0x05
+    NorCmdWriteStatusReg1 = 0x01
+    NorStatusReg1BpMask = 0x3C
+
+    # NOR Flash default page/block size
+    NorDefaultPageSize = 1024
+    NorDefaultPagePerBlock = 4
+    NorDefaultBlockSize = (NorDefaultPageSize * NorDefaultPagePerBlock)
+
+    # NAND Flash default page/block size
+    NandDefaultPageSize = 2048
+    NandDefaultPagePerBlock = 64
+    NandDefaultBlockSize = (NandDefaultPageSize * NandDefaultPagePerBlock)
+
+    # Flash write padding data
+    FlashWritePaddingData = 0xFF
+
+    MinFlashProcessTimeoutInSecond = 1
+
+    # NOR Flash program / read / erase timeout
+    # Max page program time: typical 0.5ms for GD25Q128E, max 3ms for W25Q256JV
+    # Take 0.5ms * 10 = 5ms
+    NorPageProgramTimeoutInSeconds = 0.005
+    # Max 4KB sector erase time: typical 70ms for GD25Q256D, max 400ms for GD25Q256D
+    # Take(400ms * 2) > (70ms * 10 = 700ms)
+    Nor4kSectorEraseTimeoutInSenonds = 0.8
+    # Max 32KB block erase time: typical 0.16s for GD25Q128E, max 1.6s for W25Q256JV
+    # Take 2s > 0.16s * 10 = 1.6s
+    Nor32kBlockEraseTimeoutInSeconds = 2  # larger than max
+    # Max 64KB block erase time: typical 0.25s for GD25Q128E, max 1.6s for GD25Q128E
+    # Take 0.25s * 10 = 2.5s
+    Nor64kBlockEraseTimeoutInSeconds = 2.5
+    # Max chip erase time: typical 150s for W25Q256JV, max 400s for W25Q256JV
+    # Take 1000s > 400s * 2 = 800s
+    NorChipEraseTimeoutInSeconds = 1000
+    # Read flash with 1IO @ 10MHz(10Mbps)
+    NorRead1KiBTimeoutInSecond = 0.001
+    # NOR calculate checksum with 1.5MB / s, test data(15.8MB / 8s)
+    NorCalculate1KiBChecksumTimeoutInSeconds = 0.001
+
+    # NAND Flash 4KB page size read / program / block erase timeout
+    # Page size read from Array with ECC(900us) + page size(4KB) read from cache with 1IO @ 10MHz(4KB / 10Mbps=3.2ms)
+    # Max read from array with ECC: 90us for MT29F4G01ABBF, max 170us for MT29F4G01ABBF
+    # Take 90us * 10 = 900us + 3.2ms
+    NandPageReadTimeoutInSeconds = 0.004
+    # page program with ECC(4ms) + page size(4KB) load with 1IO @ 10MHz(4KB / 10Mbps=3.2ms)
+    # Max page program with ECC: 400us for MX35LF4GE4AD, max 800us for MX35LF4GE4AD
+    # Take 400us * 10 = 4ms + 3.2ms
+    NandPageProgramTimeoutInSeconds = 0.007
+    # Max block erase time: typical 4ms for MX35LFxG24AD, max 10ms for MT29F2G01ABAG
+    # Take 4ms * 10 = 40ms
+    NandBlockEraseTimeoutInSeconds = 0.04
+    # NAND calculate checksum with 1.5MB / s, test data(2KB / 4KB:47MB / 23s)
+    NandCalculate1KiBChecksumTimeoutInSeconds = 0.001
+
+
+def nor_read_timeout_in_second(size_in_byte):
+    return int(max(divide_then_round_up(size_in_byte, 1024) * FlashUtils.NorRead1KiBTimeoutInSecond.value,
+                   FlashUtils.MinFlashProcessTimeoutInSecond.value))
+
+
+def nor_erase_timeout_in_second(size_in_kbyte):
+    if size_in_kbyte == 0xFFFFFFFF:
+        return int(max(FlashUtils.NorChipEraseTimeoutInSeconds.value,
+                       FlashUtils.MinFlashProcessTimeoutInSecond.value))
+    elif size_in_kbyte == 4:
+        return int(max(FlashUtils.Nor4kSectorEraseTimeoutInSenonds.value,
+                       FlashUtils.MinFlashProcessTimeoutInSecond.value))
+    elif size_in_kbyte == 32:
+        return int(max(FlashUtils.Nor32kBlockEraseTimeoutInSeconds.value,
+                       FlashUtils.MinFlashProcessTimeoutInSecond.value))
+    elif size_in_kbyte == 64:
+        return int(max(FlashUtils.Nor64kBlockEraseTimeoutInSeconds.value,
+                       FlashUtils.MinFlashProcessTimeoutInSecond.value))
+    else:
+        return int(
+            max(divide_then_round_up(size_in_kbyte, 4) * FlashUtils.Nor4kSectorEraseTimeoutInSenonds.value,
+                FlashUtils.MinFlashProcessTimeoutInSecond.value))
+
+
+def nor_checksum_timeout_in_second(size_in_byte):
+    return int(max(divide_then_round_up(size_in_byte,
+                                        1024) * FlashUtils.NorCalculate1KiBChecksumTimeoutInSeconds.value,
+                   FlashUtils.MinFlashProcessTimeoutInSecond.value))
+
+
+def nand_read_timeout_in_second(size_in_byte, page_size):
+    return int(max(
+        divide_then_round_up(size_in_byte, page_size) * FlashUtils.NandPageReadTimeoutInSeconds.value,
+        FlashUtils.MinFlashProcessTimeoutInSecond.value))
+
+
+def nand_program_timeout_in_second(size_in_byte, page_size):
+    return int(max(
+        divide_then_round_up(size_in_byte, page_size) * FlashUtils.NandPageProgramTimeoutInSeconds.value,
+        FlashUtils.MinFlashProcessTimeoutInSecond.value))
+
+
+def nand_erase_timeout_in_second(size_in_byte, block_size):
+    return int(max(
+        divide_then_round_up(size_in_byte, block_size) * FlashUtils.NandBlockEraseTimeoutInSeconds.value,
+        FlashUtils.MinFlashProcessTimeoutInSecond.value))
+
+
+def nand_checksum_timeout_in_second(size_in_byte, page_size):
+    return int(max(
+        divide_then_round_up(size_in_byte, 1024) * FlashUtils.NandCalculate1KiBChecksumTimeoutInSeconds.value,
+        FlashUtils.MinFlashProcessTimeoutInSecond.value))
diff --git a/ameba/scripts/flash/base/floader_handler.py b/ameba/scripts/flash/base/floader_handler.py
new file mode 100644
index 00000000..095013ad
--- /dev/null
+++ b/ameba/scripts/flash/base/floader_handler.py
@@ -0,0 +1,646 @@
+#! /usr/bin/env python
+# -*- coding: utf-8 -*-
+
+# Copyright (c) 2024 Realtek Semiconductor Corp.
+# SPDX-License-Identifier: Apache-2.0
+
+import time
+import ctypes
+
+from .sense_status import *
+from .device_info import *
+from .next_op import *
+from .flash_utils import *
+
+BAUDSET = 0x81
+QUERY = 0x02
+CONFIG = 0x83
+WRITE = 0x84
+READ = 0x05
+CHKSM = 0x06
+SENSE = 0x07
+NEXTOP = 0x08
+
+FS_ERASE = 0xA0
+FS_RDSTS = 0x21
+FS_WTSTS = 0xA2
+FS_MKBAD = 0xA3
+FS_CHKMAP = 0x24
+FS_CHKBAD = 0x25
+FS_CHKBLK = 0x26
+
+OTP_RRAW = 0x40
+OTP_WRAW = 0xC1
+OTP_RMAP = 0x42
+OTP_WMAP = 0xC3
+
+ACK_BUF_EMPTY = 0xB0
+ACK_BUF_FULL = 0xB1
+
+NP_EXIT = 0x01
+NP_BAUDRATE_RECOVER = 0x02
+
+SOF = 0xA5
+
+QUERY_DATA_OFFSET_DID = 0
+QUERY_DATA_OFFSET_IMAGE_TYPE = 2
+QUERY_DATA_OFFSET_CMD_SET_VERSION = 4
+QUERY_DATA_OFFSET_MEMORY_TYPE = 6
+QUERY_DATA_OFFSET_FLASH_MID = 7
+QUERY_DATA_OFFSET_FLASH_DID = 8
+QUERY_DATA_OFFSET_FLASH_MFG = 10
+QUERY_DATA_OFFSET_FLASH_MODEL = 22
+QUERY_DATA_OFFSET_FLASH_PAGE_SIZE = 42
+QUERY_DATA_OFFSET_FLASH_OOB_SIZE = 46
+QUERY_DATA_OFFSET_FLASH_PAGES_PER_BLOCK = 48
+QUERY_DATA_OFFSET_FLASH_BLOCKS_PER_LUN = 52
+QUERY_DATA_OFFSET_FLASH_LUNS_PER_TARGET = 56
+QUERY_DATA_OFFSET_FLASH_MAX_BAD_BLOCKS_PER_LUN = 57
+QUERY_DATA_OFFSET_FLASH_REQ_HOST_ECC_LEVEL = 59
+QUERY_DATA_OFFSET_FLASH_TARGETS = 60
+QUERY_DATA_OFFSET_FLASH_CAPACITY = 61
+QUERY_DATA_OFFSET_WIFI_MAC = 65
+
+# Read otp logical map time:26ms, physical map time: 170ms
+# Program otp logical map time: 7ms
+OTP_READ_TIMEOUT_IN_SECONDS = 10
+
+
+class FloaderHandler(object):
+    def __init__(self, ameba_obj):
+        self.ameba = ameba_obj
+        self.serial_port = ameba_obj.serial_port
+        self.profile = ameba_obj.profile_info
+        self.logger = ameba_obj.logger
+        self.setting = ameba_obj.setting
+        super().__init__()
+
+    def send_request(self, request, length, timeout, is_sync=True):
+        ret = ErrType.SYS_UNKNOWN
+        response_bytes = None
+
+        len_l = length & 0xFF
+        len_h = (length >> 8) & 0xFF
+
+        frame_data = [(SOF)]
+        frame_data.append(len_l)
+        frame_data.append(len_h)
+        frame_data.append((len_l ^ len_h) & 0xFF)
+
+        frame_bytes = bytearray(frame_data)
+        frame_bytes += request[:length]
+        checksum = sum(request)
+
+        frame_bytes += (checksum & 0xFF).to_bytes(1, byteorder="little")
+
+        try:
+            retry = 0
+            while retry < self.setting.request_retry_count:
+                retry += 1
+
+                self.serial_port.flushInput()
+                self.serial_port.flushOutput()
+
+                self.ameba.write_bytes(frame_bytes)
+                self.logger.debug(f"Request: len={length}, payload={request.hex()}")
+
+                ret, ret_byte = self.ameba.read_bytes(timeout)
+                if ret != ErrType.OK:
+                    self.logger.debug(f"Response error: {ret}, timeout:{timeout}")
+                    continue
+                if is_sync:
+                    if ret_byte[0] == SOF:
+                        ret, ret_bytes = self.ameba.read_bytes(timeout, size=3)
+                        if ret == ErrType.OK:
+                            len_l = ret_bytes[0]
+                            len_h = ret_bytes[1]
+                            len_xor = ret_bytes[2]
+                            response_len = (len_h << 8) + len_l
+                            if len_xor == (len_l ^ len_h):
+                                ret, response_bytes = self.ameba.read_bytes(self.setting.async_response_timeout_in_second,
+                                                                            size=response_len + 1)
+                                if ret == ErrType.OK:
+                                    if response_len >= len(response_bytes) - 1:
+                                        self.logger.debug(
+                                            f"Response: len={response_len}, payload={response_bytes.hex()}")
+                                        checksm = sum(response_bytes[:response_len]) % 256
+                                        if checksm == response_bytes[response_len]:
+                                            self.logger.debug(f"Checksum={checksm}({hex(checksm)}), ok")
+                                            break
+                                        else:
+                                            self.logger.debug(
+                                                f"Response checksum error: expect {hex(checksm)}, get {hex(response_bytes[response_len + 1])}")
+                                            ret = ErrType.SYS_CHECKSUM
+                                    else:
+                                        ret = ErrType.SYS_PROTO
+                                        self.logger.debug(
+                                            f"Response length error:  expect {len_xor}, get {len_l ^ len_h}")
+                                else:
+                                    self.logger.debug(f"Read response payload error: {ret}")
+                            else:
+                                ret = ErrType.SYS_PROTO
+                                self.logger.debug(f"Response length check error:  {ret_bytes.hex()}")
+                        else:
+                            ret = ErrType.SYS_PROTO
+                            self.logger.error(f"Read response length error: {ret}")
+                    elif ret_byte[0] >= ErrType.DEV_ERR_BASE.value:
+                        ret = ret_byte
+                        self.logger.debug(f"Negative response 0x{ret_byte.hex()}: ")
+                        if ret_byte[0] == ErrType.DEV_FULL.value:
+                            time.sleep(self.setting.request_retry_interval_second)
+                    else:
+                        ret = ErrType.SYS_PROTO
+                        self.logger.debug(f"Unexpected response opcode {ret_byte.hex()}")
+                else:
+                    if ret_byte[0] == ACK_BUF_FULL:
+                        self.logger.debug(f"ACK: Rx buffer full, wait {self.setting.request_retry_interval_second}s")
+                        time.sleep(self.setting.request_retry_interval_second)
+                        ret = ErrType.OK
+                    elif ret_byte[0] == ACK_BUF_EMPTY:
+                        self.logger.debug(f"Response: ACK")
+                        ret = ErrType.OK
+                        break
+                    elif ret_byte[0] >= ErrType.DEV_ERR_BASE.value:
+                        ret = ret_byte
+                        self.logger.debug(f"Negative response: {ret_byte}")
+                        if ret_byte[0] == ErrType.DEV_FULL.value or ErrType.DEV_BUSY.value:
+                            time.sleep(self.setting.request_retry_interval_second)
+                    else:
+                        ret = ErrType.SYS_PROTO
+                        self.logger.debug(f"Unexpected response {ret_byte}")
+
+                if ret == ErrType.OK or ret == ErrType.SYS_CANCEL:
+                    break
+                else:
+                    time.sleep(self.setting.request_retry_interval_second)
+        except Exception as err:
+            self.logger.debug(f"Response exception: {err}")
+            ret = ErrType.SYS_IO
+
+        return ret, response_bytes
+
+    def sense(self, timeout, op_code=None, data=None):
+        self.logger.debug(f"Sense...")
+        ret, sense_ack = self.send_request(SENSE.to_bytes(1, byteorder="little"), length=1, timeout=timeout)
+        if ret == ErrType.OK:
+            sense_status = SenseStatus()
+            self.logger.debug(f"Sense response raw data: {sense_ack.hex()}")
+            if sense_ack[0] == (SENSE):
+                ret = sense_status.parse(sense_ack, 1)
+                if ret == ErrType.OK:
+                    self.logger.debug(
+                        f"Sense response: opcode={hex(sense_status.op_code)}, status=0x{format(sense_status.status, '02x')}, data={hex(sense_status.data)}")
+                    if sense_status.status != ErrType.OK.value:
+                        ret = sense_status.status
+                        self.logger.warning(
+                            f"Sense fail: opcode={hex(sense_status.op_code)}, data={sense_status.data}, status={ret}")
+                    elif (op_code is not None) and (sense_status.op_code != op_code):
+                        ret = ErrType.SYS_PROTO
+                        self.logger.error(
+                            f"Sense protocol error: expect opcode-data {op_code.hex()}-{hex(data)}, get {hex(sense_status.op_code)}-{hex(sense_status.data)}")
+                    else:
+                        if (data is not None) and sense_status.data != data:
+                            self.logger.debug(
+                                f"Sense protocol warning: opcode {op_code} expect data {data}, get {sense_status.data}, ignored")
+                        self.logger.debug("Sense ok")
+                else:
+                    self.logger.debug(f"Sense fail to parse sense response")
+            else:
+                self.logger.debug(f"Sense fail: unexpected opcode {sense_ack[0]}")
+        else:
+            self.logger.debug(f"Sense fail: {ret}")
+        return ret, sense_ack
+
+    def handshake(self, baudrate):
+        ret = ErrType.SYS_UNKNOWN
+
+        self.logger.debug(f"Floader handshake start")
+        try:
+            if self.serial_port.baudrate != baudrate and self.setting.switch_baudrate_at_floader == 1:
+                baudset = [BAUDSET]
+
+                baudset.extend(list(baudrate.to_bytes(4, byteorder="little")))
+
+                self.logger.debug(f"BAUDSET {baudrate}")
+
+                baudset_bytes = bytearray(baudset)
+                ret, _ = self.send_request(baudset_bytes, len(baudset_bytes), self.setting.async_response_timeout_in_second,
+                                           is_sync=False)
+                if ret != ErrType.OK:
+                    self.logger.debug(f"BAUDSET fail: {ret}")
+                    return ret
+                ret = self.ameba.switch_baudrate(baudrate, self.setting.baudrate_switch_delay_in_second, True)
+                if ret != ErrType.OK:
+                    self.logger.error(f"Fail to switch baudrate to {baudrate}: {ret}")
+                    return ret
+
+            for retry in range(3):
+                if retry > 0:
+                    self.logger.debug(f"Sense retry {retry}#")
+                else:
+                    self.logger.debug("Sense")
+
+                ret, resp = self.sense(self.setting.sync_response_timeout_in_second)
+                if ret == ErrType.OK:
+                    break
+                else:
+                    self.logger.debug(f"Sense failed: {ret}")
+                    time.sleep(self.setting.request_retry_interval_second)
+                    continue
+
+            if ret == ErrType.OK:
+                self.logger.debug(f"Floader handshake done")
+            else:
+                self.logger.error(f"Floader handshake timeout")
+        except Exception as err:
+            self.logger.error(f"Floader handshake exception: {err}")
+
+        return ret
+
+    def query(self):
+        device_info = DeviceInfo()
+        self.logger.debug(f"QUERY...")
+        ret, resp = self.send_request(QUERY.to_bytes(1, byteorder="little"), length=1,
+                                      timeout=self.setting.sync_response_timeout_in_second)
+        if ret == ErrType.OK:
+            if resp[0] == (QUERY):
+                device_info.did = resp[QUERY_DATA_OFFSET_DID + 1] + (resp[QUERY_DATA_OFFSET_DID + 2] << 8)
+                device_info.image_type = resp[QUERY_DATA_OFFSET_IMAGE_TYPE + 1] + (
+                            resp[QUERY_DATA_OFFSET_IMAGE_TYPE + 2] << 8)
+                device_info.cmd_set_version = resp[QUERY_DATA_OFFSET_CMD_SET_VERSION + 1] + (
+                            resp[QUERY_DATA_OFFSET_CMD_SET_VERSION + 2] << 8)
+                device_info.wifi_mac = resp[QUERY_DATA_OFFSET_WIFI_MAC + 1: QUERY_DATA_OFFSET_WIFI_MAC + 1 + 6]
+                device_info.memory_type = resp[QUERY_DATA_OFFSET_MEMORY_TYPE + 1]
+                device_info.flash_mid = resp[QUERY_DATA_OFFSET_FLASH_MID + 1]
+                device_info.flash_did = resp[QUERY_DATA_OFFSET_FLASH_DID + 1] + (
+                            resp[QUERY_DATA_OFFSET_FLASH_DID + 2] << 8)
+                device_info.flash_mfg = resp[
+                                        QUERY_DATA_OFFSET_FLASH_MFG + 1: QUERY_DATA_OFFSET_FLASH_MFG + 1 + 12].decode("utf-8")
+                device_info.flash_model = resp[
+                                          QUERY_DATA_OFFSET_FLASH_MODEL + 1: QUERY_DATA_OFFSET_FLASH_MODEL + 1 + 20].decode("utf-8")
+                device_info.flash_page_size = (resp[QUERY_DATA_OFFSET_FLASH_PAGE_SIZE + 1]
+                                               + (resp[QUERY_DATA_OFFSET_FLASH_PAGE_SIZE + 2] << 8)
+                                               + (resp[QUERY_DATA_OFFSET_FLASH_PAGE_SIZE + 3] << 16)
+                                               + (resp[QUERY_DATA_OFFSET_FLASH_PAGE_SIZE + 4] << 24))
+                device_info.flash_oob_size = (resp[QUERY_DATA_OFFSET_FLASH_OOB_SIZE + 1] + (
+                            resp[QUERY_DATA_OFFSET_FLASH_OOB_SIZE + 2] << 8))
+                device_info.flash_pages_per_block = (resp[QUERY_DATA_OFFSET_FLASH_PAGES_PER_BLOCK + 1]
+                                                     + (resp[QUERY_DATA_OFFSET_FLASH_PAGES_PER_BLOCK + 2] << 8)
+                                                     + (resp[QUERY_DATA_OFFSET_FLASH_PAGES_PER_BLOCK + 3] << 16)
+                                                     + (resp[QUERY_DATA_OFFSET_FLASH_PAGES_PER_BLOCK + 4] << 24))
+                device_info.flash_blocks_per_lun = (resp[QUERY_DATA_OFFSET_FLASH_BLOCKS_PER_LUN + 1]
+                                                    + (resp[QUERY_DATA_OFFSET_FLASH_BLOCKS_PER_LUN + 2] << 8)
+                                                    + (resp[QUERY_DATA_OFFSET_FLASH_BLOCKS_PER_LUN + 3] << 16)
+                                                    + (resp[QUERY_DATA_OFFSET_FLASH_BLOCKS_PER_LUN + 4] << 24))
+                device_info.flash_luns_per_target = resp[QUERY_DATA_OFFSET_FLASH_LUNS_PER_TARGET + 1]
+                device_info.flash_max_bad_block_per_lun = (resp[QUERY_DATA_OFFSET_FLASH_MAX_BAD_BLOCKS_PER_LUN + 1]
+                                                           + (resp[
+                                                                  QUERY_DATA_OFFSET_FLASH_MAX_BAD_BLOCKS_PER_LUN + 2] << 8))
+                device_info.flash_req_host_ecc_level = resp[QUERY_DATA_OFFSET_FLASH_REQ_HOST_ECC_LEVEL + 1]
+                device_info.flash_targets = resp[QUERY_DATA_OFFSET_FLASH_TARGETS + 1]
+                device_info.flash_capacity = (resp[QUERY_DATA_OFFSET_FLASH_CAPACITY + 1]
+                                              + (resp[QUERY_DATA_OFFSET_FLASH_CAPACITY + 2] << 8)
+                                              + (resp[QUERY_DATA_OFFSET_FLASH_CAPACITY + 3] << 16)
+                                              + (resp[QUERY_DATA_OFFSET_FLASH_CAPACITY + 4] << 24))
+            else:
+                self.logger.debug(f"Query: unexpected response: {resp[0]}")
+                ret = ErrType.SYS_PROTO
+
+        return ret, device_info
+
+    def config(self, configs):
+        config_data = [(CONFIG)]
+
+        config_data.append(configs[0][0])
+        config_data.append(configs[0][1])
+        config_data.append(configs[0][2])
+        config_data.append(configs[0][3])
+        config_data.append(configs[0][4])
+        config_data.append(configs[0][5])
+        config_data.append(configs[0][6])
+        config_data.append(configs[0][7])
+
+        config_data.append(configs[1][0])
+        config_data.append(configs[1][1])
+        config_data.append(configs[1][2])
+        config_data.append(configs[1][3])
+        config_data.append(configs[1][4])
+        config_data.append(configs[1][5])
+        config_data.append(configs[1][6])
+        config_data.append(configs[1][7])
+
+        request_bytes = bytearray(config_data)
+        self.logger.debug(f"CONFIG: {configs[0].hex()} {configs[1].hex()}")
+        ret, _ = self.send_request(request_bytes, len(request_bytes), self.setting.async_response_timeout_in_second, is_sync=False)
+
+        return ret
+
+    def next_operation(self, opcode, operand):
+        request_data = [NEXTOP]
+
+        request_data.append((opcode.value) & 0xFF)
+        request_data.extend(list(operand.to_bytes(4, byteorder="little")))
+
+        self.logger.debug(f"NEXTOTP: opecode={opcode}, operand={operand}")
+
+        request_bytes = bytearray(request_data)
+
+        ret, _ = self.send_request(request_bytes, len(request_bytes), self.setting.sync_response_timeout_in_second, is_sync=False)
+
+        return ret
+
+    def reset_in_download_mode(self):
+        self.logger.debug(f"Reset in download mode")
+        return self.next_operation(NextOpType.REBURN, 0)
+
+    def write(self, mem_type, src, size, addr, timeout, need_sense=False):
+        sense_status = SenseStatus()
+
+        write_data = [WRITE]
+        write_data.append(mem_type&0xFF)
+        write_data.extend(list(addr.to_bytes(4, byteorder="little")))
+
+        write_array = bytearray(write_data)
+        write_array += src[:size]
+
+        self.logger.debug(f"WRITE: addr={hex(addr)}, size={size}, mem_type={mem_type}, need_sense={need_sense}")
+        ret, _ = self.send_request(write_array, len(write_array), self.setting.write_response_timeout_in_second, is_sync=False)
+        if ret == ErrType.OK:
+            if need_sense:
+                ret, sense_ack = self.sense(timeout, op_code=WRITE, data=addr)
+                if ret != ErrType.OK:
+                    self.logger.error(f"WRITE addr={hex(addr)} fail: {ret}")
+
+        return ret
+
+    def read(self, mem_type, addr, size, timeout):
+        resp = None
+
+        read_data = [READ]
+        read_data.append((mem_type & 0xFF))
+        read_data.extend(list(addr.to_bytes(4, byteorder="little")))
+        read_data.extend(list(size.to_bytes(4, byteorder="little")))
+
+        self.logger.debug(f"READ: addr={hex(addr)}, size={size}, mem_type={mem_type}")
+        read_bytes = bytearray(read_data)
+        ret, resp_ack = self.send_request(read_bytes, len(read_bytes), timeout)
+        if ret == ErrType.OK:
+            if resp_ack[0] == READ:
+                resp = resp_ack[1:]
+            else:
+                self.logger.debug(f"READ got unexpected response {hex(resp_ack[0])}")
+                ret = ErrType.SYS_PROTO
+        else:
+            self.logger.debug(f"READ fail: {ret}")
+
+        return ret
+
+    def checksum(self, mem_type,  start_addr, end_addr, size, timeout):
+        chk_rest = 0
+        request_data = [CHKSM]
+        request_data.append((mem_type & 0xFF))
+        request_data.extend(list(start_addr.to_bytes(4, byteorder='little')))
+
+        request_data.extend(list(end_addr.to_bytes(4, byteorder='little')))
+
+        request_data.extend(list(size.to_bytes(4, byteorder='little')))
+
+        self.logger.debug(f"CHKSM: start={hex(start_addr)}, end={hex(end_addr)}, size={size}, mem_type={mem_type}")
+        request_bytes = bytearray(request_data)
+        ret, resp = self.send_request(request_bytes, len(request_bytes), timeout)
+        if ret == ErrType.OK:
+            if resp[0] == int(CHKSM):
+                chk_rest = resp[1] + (resp[2] << 8) + (resp[3] << 16) + (resp[4] << 24)
+                self.logger.debug(f"CHKSM: result={hex(chk_rest)}")
+            else:
+                self.logger.debug(f"CHKSM: unexpected response {resp[0]}")
+                ret = ErrType.SYS_PROTO
+        else:
+            self.logger.error(f"CHKSM fail: {ret}")
+
+        return ret, chk_rest
+
+    def erase_flash(self, mem_type, start_addr, end_addr, size, timeout, sense=False, force=False):
+        self.logger.debug(f"Erase flash: start_addr={hex(start_addr)}, end_addr={hex(end_addr)} size={size}")
+        request_data = [FS_ERASE]
+        request_data.append((mem_type & 0xFF))
+        request_data.append(1 if force else 0)
+
+        request_data.extend(list(start_addr.to_bytes(4, byteorder="little")))
+        request_data.extend(list((end_addr & 0xFFFFFFFF).to_bytes(4, byteorder="little")))
+
+        request_data.extend(list((size & 0xFFFFFFFF).to_bytes(4, byteorder="little")))
+
+        if force:
+            self.logger.warning(f"FS_ERASE: start_addr={hex(start_addr)}, end_addr={hex(end_addr)}, size={size}, mem_type={mem_type} force")
+        else:
+            self.logger.debug(f"FS_ERASE: start_addr={hex(start_addr)}, end_addr={hex(end_addr)}, size={size}, mem_type={mem_type}")
+
+        request_bytes = bytearray(request_data)
+        ret, _ = self.send_request(request_bytes, len(request_bytes), self.setting.async_response_timeout_in_second, is_sync=False)
+        if ret != ErrType.OK:
+            self.logger.warning(f"FS_ERASE start_addr={hex(start_addr)}, end_addr={hex(end_addr)}, size={size}, force={force}, fail:{ret}")
+            return ret
+
+        if sense:
+            ret, sense_status = self.sense(timeout, op_code=FS_ERASE, data=start_addr)
+            if ret != ErrType.OK:
+                self.logger.error(f"FS_ERASE start_addr={hex(start_addr)}, size={size} force={force} fail: {ret}")
+
+        return ret
+
+    def read_status_register(self, cmd, address):
+        status = None
+
+        request_data = [FS_RDSTS]
+        request_data.append(cmd)
+        request_data.append(address)
+
+        self.logger.debug(f"FS_RDSTS: cmd={cmd}, address={address}")
+
+        request_bytes = bytearray(request_data)
+        ret, resp = self.send_request(request_bytes, len(request_bytes), self.setting.sync_response_timeout_in_second)
+        if ret == ErrType.OK:
+            if resp[0] == FS_RDSTS:
+                status = resp[1]
+                self.logger.debug(f"FS_RDSTS: status={status}")
+            else:
+                self.logger.debug(f"FS_RDSTS: got unexpected response, {resp[0]}")
+                ret = ErrType.SYS_PROTO
+        else:
+            self.logger.debug(f"FS_RDSTS failed: {ret}")
+
+        return ret, status
+
+    def write_status_register(self, cmd, addr, value):
+        request_data = [FS_WTSTS]
+        request_data.append(cmd)
+        request_data.append(addr)
+        request_data.append(value)
+
+        self.logger.debug(f"FS_WTSTS: cmd={hex(cmd)}, addr={hex(addr)}, value={hex(value)}")
+
+        request_bytes = bytearray(request_data)
+        ret, _ = self.send_request(request_bytes, len(request_bytes), self.setting.async_response_timeout_in_second, is_sync=False)
+
+        return ret
+
+    def mark_bad_block(self, address):
+        request_data = [FS_MKBAD]
+
+        request_data.extend(list(address.to_bytes(4, byteorder="little")))
+        request_bytes = bytearray(request_data)
+        self.logger.debug(f"FS_MKBAD: addr={format(address, '08x')}")
+        return self.send_request(request_bytes, len(request_bytes), self.setting.async_response_timeout_in_second, is_sync=False)
+
+    def check_bad_block(self, address):
+        ret = ErrType.OK
+        status = None
+
+        request_data = [FS_CHKBAD]
+
+        request_data.extend(list(address.to_bytes(4, byteorder="little")))
+        request_bytes = bytearray(request_data)
+        self.logger.debug(f"FS_CHKBAD: addr={format(address, '08x')}")
+
+        ret, resp = self.send_request(request_bytes, len(request_bytes), self.setting.sync_response_timeout_in_second)
+        if ret == ErrType.OK:
+            if resp[0] == FS_CHKBAD:
+                status = resp[1]
+            else:
+                self.logger.debug(f"FS_CHKBAD got unexpected response {hex(resp[0])}")
+                ret = ErrType.SYS_PROTO
+        else:
+            self.logger.debug(f"FS_CHKBAD fail: {ret}")
+
+        return ret, status
+
+    def check_block_status(self, address):
+        ret = ErrType.OK
+        block_status = 0
+        page_status = [0, 0]
+
+        request_data = [FS_CHKBLK]
+
+        request_data.extend(list(address.to_bytes(4, byteorder="little")))
+        request_bytes = bytearray(request_data)
+        self.logger.debug(f"FS_CHKBLK: addr={format(address, '08x')}")
+
+        ret, resp = self.send_request(request_bytes, len(request_bytes), self.setting.sync_response_timeout_in_second)
+        if ret == ErrType.OK:
+            if resp[0] == FS_CHKBLK:
+                block_status = resp[1]
+                page_status[0] = ctypes.c_uint64(resp[2] + (resp[3] << 8) + (resp[4] << 16) +
+                                                 (resp[5] << 24) + (resp[6] << 32) + (resp[7] << 40) +
+                                                 (resp[8] << 48) + (resp[9] << 56)).value
+                page_status[1] = ctypes.c_uint64(resp[10] + (resp[11] << 8) + (resp[12] << 16) +
+                                                 (resp[13] << 24) + (resp[14] << 32) + (resp[15] << 40) +
+                                                 (resp[16] << 48) + (resp[17] << 56)).value
+
+                self.logger.debug(
+                    f"FS_CHKBLK: block_status={hex(block_status)}, page status={format(page_status[0], '16x')} {format(page_status[1], '16x')}")
+        else:
+            self.logger.debug(f"FS_CHKBLK fail: {ret}")
+
+        return ret, block_status
+
+    def check_map_status(self, address):
+        ret = ErrType.OK
+
+        status = 0
+        request_data = [FS_CHKMAP]
+        request_data.extend(list(address.to_bytes(4, byteorder="little")))
+        request_bytes = bytearray(request_data)
+        self.logger.debug(f"FS_CHKMAP: addr={format(address, '08x')}")
+
+        ret, resp = self.send_request(request_bytes, len(request_bytes), self.setting.sync_response_timeout_in_second)
+        if ret == ErrType.OK:
+            if resp[0] == FS_CHKMAP:
+                status = (resp[1] + (resp[2] << 8) + (resp[3] << 16) + (resp[4] << 24)) & 0xFFFFFFFF
+                self.logger.debug(f"FS_CHKMAP: status={format(status, '08x')}")
+        else:
+            self.logger.debug(f"FS_CHKMAP fail: {ret}")
+
+        return ret, status
+
+    def otp_read_map(self, cmd, address, size):
+        request_data = [cmd]
+
+        request_data.extend(list(address.to_bytes(4, byteorder="little")))
+
+        request_data.extend(list(size.to_bytes(4, byteorder="little")))
+
+        request_bytes = bytearray(request_data)
+
+        ret, buf = self.send_request(request_bytes, len(request_bytes), OTP_READ_TIMEOUT_IN_SECONDS)
+        if ret == ErrType.OK:
+            if buf[0] == cmd:
+                self.logger.debug(f"Otp read: {buf[0]}")
+                return ret, buf[1:-1]
+            else:
+                self.logger.debug(f"Otp read fail: unexpected response {buf[0]}")
+                ret = ErrType.SYS_PROTO
+
+        return ret, buf
+
+    def otp_write_map(self, cmd, address, size, data):
+        request_data = [cmd]
+
+        request_data.extend(list(address.to_bytes(4, byteorder="little")))
+
+        request_data.extend(list(size.to_bytes(4, byteorder="little")))
+
+        for idx in range(size):
+            request_data.append(data[address + idx])
+
+        request_bytes = bytearray(request_data)
+
+        ret, _ = self.send_request(request_bytes, len(request_bytes), self.setting.async_response_timeout_in_second, is_sync=False)
+
+        return ret
+
+    def otp_read_physical_map(self, address, size):
+        self.logger.debug(f"OTP_RRAW: addr={hex(address)}, size={size}")
+
+        ret, buf = self.otp_read_map(OTP_RRAW, address, size)
+        if ret == ErrType.OK:
+            self.logger.debug(f"OTP_RRAW: {buf}")
+            self.logger.debug("OTP_RRAW done")
+        else:
+            self.logger.debug(f"OTP_RRAW fail: {ret}")
+
+        return ret, buf
+
+    def otp_write_physical_map(self, address, size, data):
+        self.logger.debug(f"OTP_WRAW: addr={hex(address)}, size={size}, data={data}")
+
+        ret = self.otp_write_map(OTP_WMAP, address, size, data)
+        if ret == ErrType.OK:
+            self.logger.debug("OTP_WRAW done")
+        else:
+            self.logger.debug(f"OTP_WRAW fail: {ret}")
+
+        return ret
+
+    def otp_read_logical_map(self, address, size):
+        self.logger.debug(f"OTP_RMAP: addr={hex(address)}, size={size}")
+
+        ret, buf = self.otp_read_map(OTP_RMAP, address, size)
+        if ret == ErrType.OK:
+            self.logger.debug(f"OTP_RMAP: {buf}")
+            self.logger.debug("OTP_RMAP done")
+        else:
+            self.logger.debug(f"OTP_RMAP fail: {ret}")
+
+        return ret, buf
+
+    def otp_write_logical_map(self, address, size, data):
+        self.logger.debug(f"OTP_WMAP: addr={hex(address)}, size={size}, data={data}")
+
+        ret = self.otp_write_map(OTP_WMAP, address, size, data)
+        if ret == ErrType.OK:
+            self.logger.debug("OTP_WMAP done")
+        else:
+            self.logger.debug(f"OTP_WMAP fail: {ret}")
+
+        return ret
diff --git a/ameba/scripts/flash/base/image_info.py b/ameba/scripts/flash/base/image_info.py
new file mode 100644
index 00000000..037cc593
--- /dev/null
+++ b/ameba/scripts/flash/base/image_info.py
@@ -0,0 +1,28 @@
+#! /usr/bin/env python
+# -*- coding: utf-8 -*-
+
+# Copyright (c) 2024 Realtek Semiconductor Corp.
+# SPDX-License-Identifier: Apache-2.0
+
+class ImageInfo():
+    def __init__(self, **kwargs):
+        self.image_name = kwargs.get("ImageName", "")
+        self.start_address = kwargs.get("StartAddress", 0)
+        self.end_address = kwargs.get("EndAddress", 0)
+        self.memory_type = kwargs.get("MemoryType", 0)
+        self.full_erase = kwargs.get("FullErase", False)
+        self.mandatory = kwargs.get("Mandatory", False)
+        self.description = kwargs.get("Description", "")
+
+    def __repr__(self):
+        image_info_dict = {
+            "ImageName": self.image_name,
+            "StartAddress": self.start_address,
+            "EndAddress": self.end_address,
+            "MemoryType": self.memory_type,
+            "FullErase": self.full_erase,
+            "Mandatory": self.mandatory,
+            "Description": self.description
+        }
+
+        return image_info_dict
diff --git a/ameba/scripts/flash/base/json_utils.py b/ameba/scripts/flash/base/json_utils.py
new file mode 100644
index 00000000..715a0ee9
--- /dev/null
+++ b/ameba/scripts/flash/base/json_utils.py
@@ -0,0 +1,48 @@
+#! /usr/bin/env python
+# -*- coding: utf-8 -*-
+
+# Copyright (c) 2024 Realtek Semiconductor Corp.
+# SPDX-License-Identifier: Apache-2.0
+
+import os
+import json
+import base64
+from pyDes import *
+
+_DES_KEY = "574C414E"  # 0x574C414E, WLAN
+_DES_IV = [0x40, 0x52, 0x65, 0x61, 0x6C, 0x73, 0x69, 0x6C]  # @Realsil
+
+
+class JsonUtils:
+    @staticmethod
+    def load_from_file(file_path, need_decrypt=True):
+        result = None
+        if os.path.exists(file_path):
+            with open(file_path, 'r', encoding='utf-8') as f:
+                f_content = f.read()
+
+            if need_decrypt:
+                k = des(_DES_KEY, CBC, _DES_IV, padmode=PAD_PKCS5)
+                des_k = k.decrypt(base64.b64decode(f_content))
+                profile_str = des_k.decode("utf-8")
+                result = json.loads(profile_str)
+            else:
+                result = json.loads(f_content)
+
+        return result
+
+    @staticmethod
+    def save_to_file(file_path, data, need_encrypt=False):
+        path_dir = os.path.dirname(file_path)
+        os.makedirs(path_dir, exist_ok=True)
+        if need_encrypt:
+            ek = des(_DES_KEY.encode("utf-8"), CBC, _DES_IV, pad=None, padmode=PAD_PKCS5)
+            en_bytes = ek.encrypt(json.dumps(data).encode("utf-8"))
+            save_data = base64.b64encode(en_bytes)
+            with open(file_path, "wb") as json_file:
+                json_file.write(save_data)
+        else:
+            save_data = data
+
+            with open(file_path, "w") as json_file:
+                json.dump(save_data, json_file, indent=2)
diff --git a/ameba/scripts/flash/base/memory_info.py b/ameba/scripts/flash/base/memory_info.py
new file mode 100644
index 00000000..efaf2e39
--- /dev/null
+++ b/ameba/scripts/flash/base/memory_info.py
@@ -0,0 +1,24 @@
+#! /usr/bin/env python
+# -*- coding: utf-8 -*-
+
+# Copyright (c) 2024 Realtek Semiconductor Corp.
+# SPDX-License-Identifier: Apache-2.0
+
+
+class MemoryInfo:
+    MEMORY_TYPE_RAM = 0
+    MEMORY_TYPE_NOR = 1
+    MEMORY_TYPE_NAND = 2
+    MEMORY_TYPE_VENDOR = 3
+    MEMORY_TYPE_HYBRID = 4
+    MAX_PARTITION_MEMORY_TYPE = MEMORY_TYPE_VENDOR
+    MAX_DEVICE_MEMORY_TYPE = MEMORY_TYPE_HYBRID
+
+    def __init__(self):
+        self.start_address = 0
+        self.end_address = 0
+        self.memory_type = self.MEMORY_TYPE_RAM
+        self.size_in_kbyte = 0
+
+    def size_in_byte(self):
+        return self.size_in_kbyte * 1024
diff --git a/ameba/scripts/flash/base/next_op.py b/ameba/scripts/flash/base/next_op.py
new file mode 100644
index 00000000..4d562920
--- /dev/null
+++ b/ameba/scripts/flash/base/next_op.py
@@ -0,0 +1,15 @@
+#! /usr/bin/env python
+# -*- coding: utf-8 -*-
+
+# Copyright (c) 2024 Realtek Semiconductor Corp.
+# SPDX-License-Identifier: Apache-2.0
+
+from enum import Enum
+
+
+class NextOpType(Enum):
+    NONE = 0  # Do nothing, hold on in download mode
+    INDICATION = 1  # Indicate download result via PWM/GPIO
+    RESET = 2  # Exit download mode
+    BOOT = 3  # Jump to Ram
+    REBURN = 4  # Reset into download mode again
diff --git a/ameba/scripts/flash/base/remote_serial.py b/ameba/scripts/flash/base/remote_serial.py
new file mode 100644
index 00000000..d123e0ab
--- /dev/null
+++ b/ameba/scripts/flash/base/remote_serial.py
@@ -0,0 +1,371 @@
+#! /usr/bin/env python
+# -*- coding: utf-8 -*-
+
+# Copyright (c) 2024 Realtek Semiconductor Corp.
+# SPDX-License-Identifier: Apache-2.0
+
+import socket
+import json
+import time
+import threading
+import base64
+from typing import Optional, Dict, Any
+import serial
+from serial.serialutil import SerialException, SerialTimeoutException
+from datetime import datetime
+
+
+class RemoteSerial:
+    def __init__(self, logger, remote_server: str, remote_port: int, port: str, baudrate: int = 9600):
+        """
+        Initialize remote serial proxy
+        :param logger: logger object (external input, for unified log format)
+        :param remote_server: remote serial server IP
+        :param remote_port: remote serial server port
+        :param port: remote serial port name (e.g. "COM3", "/dev/ttyUSB0")
+        :param baudrate: serial baud rate
+        """
+        self.logger = logger
+        self.remote_server = remote_server
+        self.remote_port = remote_port
+        self.port = port
+        self.baudrate = baudrate
+
+        # Core state variables
+        self.tcp_socket: Optional[socket.socket] = None
+        self.receive_buffer = b""  # Binary receive buffer
+        self.receive_thread: Optional[threading.Thread] = None
+        self.is_open = False  # Whether serial is open (TCP connected + serial command succeeds)
+        self.response_event = threading.Event()  # Command response synchronization event
+        self.last_response: Dict[str, Any] = {}  # Last command response
+
+        # Initialize logger
+        self.logger.debug(
+            f"[RemoteSerial][{self.port}] Initialize remote serial proxy - "
+            f"Server: {self.remote_server}:{self.remote_port}, baudrate: {self.baudrate}"
+        )
+        # 1. Establish TCP connection (just connect, not start the receive thread)
+        self._connect_tcp()
+        self.receive_thread = threading.Thread(
+            target=self._receive_loop,
+            daemon=True,
+            name=f"RemoteSerialRecv-{self.port}"
+        )
+        self.receive_thread.start()
+        self.logger.debug(f"[RemoteSerial][{self.port}] Receive thread started: {self.receive_thread.name}")
+
+    def _connect_tcp(self) -> bool:
+        """
+        Establish TCP connection with remote serial server
+        :return: Returns True if connected successfully, raises SerialException on failure
+        """
+        self.logger.debug(f"[RemoteSerial][{self.port}] Trying TCP connection: {self.remote_server}:{self.remote_port}")
+        try:
+            self.tcp_socket = socket.socket(socket.AF_INET, socket.SOCK_STREAM)
+            # self.tcp_socket.settimeout(10)  # TCP connect timeout 10s
+            self.tcp_socket.setsockopt(socket.IPPROTO_TCP, socket.TCP_NODELAY, 1)
+            self.logger.debug(f"[RemoteSerial][{self.port}] TCP_NODELAY set")
+            self.tcp_socket.connect((self.remote_server, self.remote_port))
+            self.logger.debug(f"[RemoteSerial][{self.port}] TCP connection succeeded")
+            return True
+        except socket.timeout:
+            raise SerialException(f"[RemoteSerial][{self.port}] TCP connection timed out (10s)- {self.remote_server}:{self.remote_port}")
+        except ConnectionRefusedError:
+            raise SerialException(f"[RemoteSerial][{self.port}] TCP connection refused - server not started or wrong port")
+        except Exception as e:
+            raise SerialException(f"[RemoteSerial][{self.port}] TCP connection failed: {str(e)}")
+
+    def _receive_loop(self):
+        """
+        Core logic of receive thread: continuously read TCP data, parse into buffer or trigger response
+        """
+        self.logger.debug(f"[RemoteSerial][{self.port}] Receive thread running")
+        buffer = ""
+        while self.tcp_socket:
+            try:
+                # Read TCP data (as text, as server sends JSON+newline-delimited)
+                data = self.tcp_socket.recv(4096).decode('utf-8', errors='strict')
+                if not data:
+                    self.logger.error(f"[RemoteSerial][{self.port}] Server closed connection, recv returned empty data")
+                    raise ConnectionAbortedError("Server closed connection")
+
+                buffer += data
+
+                # Split by newline for complete messages (handle sticky packets)
+                while '\n' in buffer:
+                    msg_str, buffer = buffer.split('\n', 1)
+                    msg_str = msg_str.strip()
+                    if not msg_str:
+                        continue
+                    self._parse_message(msg_str)
+            except ConnectionResetError as e:
+                self.logger.error(f"[RemoteSerial][{self.port}] Connection reset: {str(e)}")
+                break
+            except ConnectionAbortedError as e:
+                self.logger.error(f"[RemoteSerial][{self.port}] Receive thread exception: {str(e)}")
+                break
+            except Exception as e:
+                self.logger.error(f"[RemoteSerial][{self.port}] Receive thread exception: {str(e)}", exc_info=True)
+                break
+
+        self.is_open = False
+        if self.tcp_socket:
+            self.tcp_socket.close()
+        self.logger.info(f"[RemoteSerial][{self.port}] Receive thread exited")
+
+    def _parse_message(self, msg_str: str):
+        """
+        Parse JSON message from server
+        :param msg_str: Complete JSON string (without newline)
+        """
+        try:
+            msg = json.loads(msg_str)
+            msg_type = msg.get("type")
+
+            if msg_type == "command_response":
+                self.last_response = msg
+                self.logger.debug(
+                    f"[RemoteSerial][{self.port}] Received command response - "
+                    f"Success: {msg.get('success')}, message: {msg.get('message', '无')}"
+                )
+                self.response_event.set()
+
+            elif msg_type == "serial_data":
+                if msg.get("port") != self.port:
+                    self.logger.warning(f"[RemoteSerial][{self.port}] Received data from other port (ignored): {msg.get('port')}")
+                    return
+
+                base64_data = msg.get("data", "")
+                if not base64_data:
+                    self.logger.warning(f"[RemoteSerial][{self.port}] Serial data empty (Base64)")
+                    return
+
+                try:
+                    raw_data = base64.b64decode(base64_data, validate=True)
+                    self.receive_buffer += raw_data
+                except base64.binascii.Error as e:
+                    self.logger.error(f"[RemoteSerial][{self.port}] Base64 decode failed: {str(e)}, data: {base64_data[:100]}...")
+
+            else:
+                self.logger.warning(f"[RemoteSerial][{self.port}] Unknown message type: {msg_type}, message: {msg_str[:200]}...")
+
+        except json.JSONDecodeError as e:
+            self.logger.error(f"[RemoteSerial][{self.port}] JSON parse failed: {str(e)}, raw: {msg_str[:200]}...")
+
+    def _send_command(self, cmd: Dict[str, Any], timeout: float = 5.0) -> Dict[str, Any]:
+        """
+        Send command to remote server and wait for response
+        :param cmd: command dict (will be converted to JSON)
+        :param timeout: response timeout (seconds)
+        :return: server response dict
+        """
+        if not self.is_open or not self.tcp_socket:
+            raise SerialException(f"[RemoteSerial][{self.port}] Send command failed: serial not open")
+
+        self.response_event.clear()
+        self.last_response = {}
+        cmd_str = json.dumps(cmd) + "\n"
+
+        try:
+            self.logger.debug(f"[RemoteSerial][{self.port}] Sending command (timeout {timeout}s): {cmd_str.strip()[:300]}...")
+            self.tcp_socket.sendall(cmd_str.encode('utf-8'))
+
+            # Wait for response or timeout
+            if self.response_event.wait(timeout):
+                return self.last_response
+            else:
+                raise SerialTimeoutException(
+                    f"[RemoteSerial][{self.port}] Command response timeout ({timeout}s) - Command: {cmd.get('type')}"
+                )
+        except Exception as e:
+            raise SerialException(f"[RemoteSerial][{self.port}] Send command exception: {str(e)}")
+
+    def validate(self, password):
+        try:
+            validate_cmd = {
+                "type": "validate",
+                "password": password
+            }
+            self.is_open = True
+            resp = self._send_command(validate_cmd, timeout=10.0)
+
+            if not resp.get("success", False):
+                self.logger.debug(f"[RemoteSerial][{self.port}] Validate failed")
+                raise SerialException(f"[RemoteSerial][{self.port}] Remote serial validate failed: Wrong password")
+            self.is_open = False
+            self.logger.debug(f"[RemoteSerial][{self.port}] Remote serial port validate successfully")
+        except Exception as e:
+            self.close()
+            raise SerialException(f"[RemoteSerial][{self.port}] Validate serial failed: {str(e)}")
+
+    def open(self):
+        if self.is_open:
+            self.logger.debug(f"[RemoteSerial][{self.port}] Serial already opened, skip")
+            return
+        self.logger.debug(f"[RemoteSerial][{self.port}] Trying to open serial")
+        try:
+            self.is_open = True
+            open_cmd = {
+                "type": "open_port",
+                "port": self.port,
+                "options": {
+                    "baudRate": self.baudrate,
+                    "dataBits": 8,
+                    "stopBits": 1,
+                    "parity": "none",
+                    "timeout": 0.1
+                }
+            }
+            resp = self._send_command(open_cmd, timeout=10.0)
+
+            if not resp.get("success", False):
+                self.logger.debug(f"[RemoteSerial][{self.port}] Open failed")
+                self.is_open = False
+                err_msg = resp.get("message", "Unknown error")
+                raise SerialException(f"[RemoteSerial][{self.port}] Remote serial open failed: {err_msg}")
+
+            # set is_open and start receive thread
+            self.is_open = True
+
+            self.logger.debug(f"[RemoteSerial][{self.port}] Remote serial port opened successfully (baudrate: {self.baudrate})")
+        except Exception as e:
+            self.close()
+            raise SerialException(f"[RemoteSerial][{self.port}] Open serial failed: {str(e)}")
+
+    def close(self):
+        """
+        Close remote serial: send close_port command + cleanup TCP and thread
+        """
+        self.logger.debug(f"[RemoteSerial][{self.port}] Start closing remote serial")
+
+        # 1. Mark state as closed (end receive thread loop)
+        if not self.is_open:
+            self.logger.debug(f"[RemoteSerial][{self.port}] Serial already closed, skip")
+            return
+        # 2. Send close serial command (try even if TCP error)
+        try:
+            if self.tcp_socket:
+                close_cmd = {"type": "close_port", "port": self.port}
+                resp = self._send_command(close_cmd, timeout=3.0)
+                if resp.get("success", False):
+                    self.logger.debug(f"[RemoteSerial][{self.port}] Remote serial close command succeeded")
+                else:
+                    self.logger.warning(f"[RemoteSerial][{self.port}] Remote serial close command failed: {resp.get('message', 'No response')}")
+        except Exception as e:
+            self.logger.error(f"[RemoteSerial][{self.port}] Send close command exception: {str(e)}")
+
+        self.is_open = False
+        self.receive_buffer = b""
+        self.logger.debug(f"[RemoteSerial][{self.port}] Remote serial closed")
+
+    def write(self, data: bytes):
+        """
+        Write binary data to remote serial (Base64 encode first)
+        :param data: binary data to send
+        """
+        if not self.is_open:
+            raise SerialException(f"[RemoteSerial][{self.port}] Write failed: serial not open")
+        if not data:
+            self.logger.debug(f"[RemoteSerial][{self.port}] Write empty data (ignored)")
+            return
+
+        try:
+            base64_data = base64.b64encode(data).decode('utf-8')
+            write_cmd = {
+                "type": "write_data",
+                "port": self.port,
+                "data": base64_data
+            }
+
+            self.logger.debug(
+                f"[RemoteSerial][{self.port}] Write data - "
+                f"Raw length: {len(data)}B, Base64 length: {len(base64_data)}B"
+            )
+            resp = self._send_command(write_cmd, timeout=10.0)
+
+            if not resp.get("success", False):
+                raise SerialException(f"[RemoteSerial][{self.port}] Write data failed: {resp.get('message', 'Unknown error')}")
+            self.logger.debug(f"[RemoteSerial][{self.port}] Write data succeeded")
+        except Exception as e:
+            raise SerialException(f"[RemoteSerial][{self.port}] Write exception: {str(e)}")
+
+    def read(self, size: int = 1) -> bytes:
+        """
+        Read specified length of binary data from receive buffer
+        :param size: length to read (bytes)
+        :return: binary data read (returns actual length if less than size)
+        """
+        if not self.is_open:
+            raise SerialException(f"[RemoteSerial][{self.port}] Read failed: serial not open")
+
+        # Get data from buffer
+        read_data = self.receive_buffer[:size]
+        self.receive_buffer = self.receive_buffer[size:]
+        self.logger.debug(
+            f"[RemoteSerial][{self.port}] Read data - "
+            f"Requested: {size}B, Read: {len(read_data)}B, Buffer left: {len(self.receive_buffer)}B"
+        )
+        return read_data
+
+    def inWaiting(self) -> int:
+        """
+        Return number of bytes waiting in receive buffer
+        :return: buffer length
+        """
+        if not self.is_open:
+            raise SerialException(f"[RemoteSerial][{self.port}] Read failed: serial not open")
+        waiting = len(self.receive_buffer)
+        return waiting
+
+    def flushInput(self):
+        """
+        Clear receive buffer (local only, no server interaction)
+        """
+        old_len = len(self.receive_buffer)
+        self.receive_buffer = b""
+        self.logger.debug(f"[RemoteSerial][{self.port}] Cleared receive buffer - old length: {old_len}B")
+
+    def flushOutput(self):
+        """
+        Flush output buffer (no local output buffer for remote serial, just for serial.Serial API compatibility)
+        """
+        self.logger.debug(f"[RemoteSerial][{self.port}] flushOutput: No action required for remote serial (no local output buffer)")
+
+    # ------------------------------
+    # Simulate serial.Serial's DTR/RTS properties
+    # ------------------------------
+    @property
+    def dtr(self):
+        self.logger.debug(f"[RemoteSerial][{self.port}] Get DTR: not supported, return False")
+        return False
+
+    @dtr.setter
+    def dtr(self, value):
+        self.logger.debug(f"[RemoteSerial][{self.port}] Set DTR: not supported, ignored value={value}")
+
+    @property
+    def rts(self):
+        self.logger.debug(f"[RemoteSerial][{self.port}] Get RTS: not supported, return False")
+        return False
+
+    @rts.setter
+    def rts(self, value):
+        self.logger.debug(f"[RemoteSerial][{self.port}] Set RTS: not supported, ignored value={value}")
+    # ------------------------------
+    # Context manager support (with statement)
+    # ------------------------------
+    def __enter__(self):
+        self.open()
+        return self
+
+    def __exit__(self, exc_type, exc_val, exc_tb):
+        self.close()
+        self.logger.info(f"[RemoteSerial][{self.port}] __exit__ close")
+        if exc_type:
+            self.logger.error(f"[RemoteSerial][{self.port}] Context manager exception: {exc_type.__name__}: {exc_val}")
+
+    def __del__(self):
+        """Destructor: make sure to close resource"""
+        if self.is_open:
+            self.logger.debug(f"[RemoteSerial][{self.port}] Destructor: closing unreleased remote serial")
+            self.close()
diff --git a/ameba/scripts/flash/base/rom_handler.py b/ameba/scripts/flash/base/rom_handler.py
new file mode 100644
index 00000000..fe257455
--- /dev/null
+++ b/ameba/scripts/flash/base/rom_handler.py
@@ -0,0 +1,333 @@
+#! /usr/bin/env python
+# -*- coding: utf-8 -*-
+
+# Copyright (c) 2024 Realtek Semiconductor Corp.
+# SPDX-License-Identifier: Apache-2.0
+
+import io
+import os
+import sys
+import time
+
+from .errno import *
+from .rtk_utils import *
+
+STX = 0x02  # Transfer data
+EOT = 0x04  # End of transfer
+BAUDSET = 0x05  # For handshake
+BAUDCHK = 0x07  # For handshake, only for UART
+ACK = 0x06  # Acknowledge
+NAK = 0x15  # Negativ acknowledge
+CAN = 0x18  # Cancel transfer, only for UART
+ESC = 0x1B  # Cancel transfer
+
+STX_BASE_LEN = 8
+STX_UART_RAM_DATA_LEN = 1024
+STX_USB_RAM_DATA_LEN = 2048
+STX_MAX_LEN = STX_BASE_LEN + STX_USB_RAM_DATA_LEN
+FloaderSizeLimit = 1024 * 1024  # 1MB
+
+StxBaseLen = 1024
+StxUartDataLen = 1024
+StxUsbDataLen = 2048
+StxMaxDataLen = StxBaseLen + StxUsbDataLen
+DEFAULT_TIMEOUT = 0.5
+STX_TIMEOUT = 1
+
+FloaderDictionary = "Devices/Floaders"
+
+
+class RomHandler(object):
+    def __init__(self, ameba_obj, padding="FF"):
+        self.ameba = ameba_obj
+        self.serial_port = ameba_obj.serial_port
+        self.logger = ameba_obj.logger
+        self.profile = ameba_obj.profile_info
+        self.baudrate = ameba_obj.baudrate
+        self.is_usb = ameba_obj.is_usb
+        self.stx_packet_no = 1
+        self.padding = padding
+        self.setting = ameba_obj.setting
+
+    def get_baudrate_idx(self, rate):
+        ''' rom built-in rate table '''
+        return {
+            110: 0,
+            300: 1,
+            600: 2,
+            1200: 3,
+            2400: 4,
+            4800: 5,
+            9600: 6,
+            14400: 7,
+            19200: 8,
+            28800: 9,
+            38400: 10,
+            57600: 11,
+            76800: 12,
+            115200: 13,
+            128000: 14,
+            153600: 15,
+            230400: 16,
+            380400: 17,
+            460800: 18,
+            500000: 19,
+            921600: 20,
+            1000000: 21,
+            1382400: 22,
+            1444400: 23,
+            1500000: 24,
+            1843200: 25,
+            2000000: 26,
+            2100000: 27,
+            2764800: 28,
+            3000000: 29,
+            3250000: 30,
+            3692300: 31,
+            3750000: 32,
+            4000000: 33,
+            6000000: 34
+        }.get(rate, 13)
+
+    def send_request(self, request, length, timeout):
+        ret = ErrType.SYS_UNKNOWN
+        response = []
+
+        try:
+            for retry in range(2):
+                if retry > 0:
+                    self.logger.debug(f"Request retry {retry}#: len={length}, payload={request.hex()}")
+                else:
+                    self.logger.debug(f"Request: len={length}, payload={request.hex()}")
+
+                self.serial_port.flushInput()
+                self.serial_port.flushOutput()
+
+                self.ameba.write_bytes(request)
+
+                for resp_retry in range(3):
+                    ret, ch = self.ameba.read_bytes(timeout)
+                    if ret != ErrType.OK:
+                        self.logger.debug(f"Reponse error: {ret}")
+                        break
+
+                    if ch[0] == ACK:
+                        self.logger.debug(f"Response ACK")
+                        break
+                    elif ch[0] == NAK:
+                        ret = ErrType.SYS_NAK
+                        self.logger.debug(f"Response NAK")
+                        continue
+                    elif ch[0] == CAN:
+                        ret = ErrType.SYS_CANCEL
+                        self.logger.debug(f"Response CAN")
+                        break
+                    elif ch[0] == ErrType.DEV_LENGTH.value:
+                        ret = ErrType.DEV_LENGTH
+                        self.logger.debug(f"Response ErrType.DEV_LENGTH")
+                        break
+                    else:
+                        ret = ErrType.SYS_PROTO
+                        self.logger.debug(f"Unexpected reponse: 0x{ch.hex()}")
+                        continue
+
+                if ret == ErrType.OK or ret == ErrType.SYS_CANCEL or ret == ErrType.DEV_LENGTH:
+                    break
+                else:
+                    time.sleep(self.setting.request_retry_interval_second)
+        except Exception as err:
+            self.logger.error(f"Send request exception: {err}")
+            ret = ErrType.SYS_IO
+
+        return ret
+
+    def reset(self):
+        self.stx_packet_no = 1
+
+    def handshake(self):
+        ret = ErrType.OK
+        self.logger.debug(f"Handshake:{'USB' if self.is_usb else 'UART'}")
+        index = self.get_baudrate_idx(self.baudrate)
+
+        if not self.is_usb:
+            ret = self.check_alive()
+            if ret != ErrType.OK:
+                self.logger.debug(f"Handshake fail: device not alive")
+                return ret
+
+        retry = 0
+        while retry < 2:
+            if retry > 0:
+                self.logger.debug(f"Handshake retry {retry}#")
+
+            retry += 1
+
+            if self.setting.switch_baudrate_at_floader == 0:
+                self.logger.debug(f"BAUDSET: {index} ({self.baudrate})")
+                _bytes = [BAUDSET]
+                _bytes.append(index)
+                cmd = bytearray(_bytes)
+
+                ret = self.send_request(cmd, 2, DEFAULT_TIMEOUT)
+                if ret == ErrType.OK:
+                    self.logger.debug(f"BAUDSET ok")
+                elif ret == ErrType.DEV_LENGTH:
+                    self.logger.debug(f"Device not in rom download mode")
+                    break
+                else:
+                    self.logger.debug(f"BAUDSET fail: {ret}")
+                    continue
+
+                if self.is_usb:
+                    break
+
+                ret = self.ameba.switch_baudrate(self.baudrate, self.setting.baudrate_switch_delay_in_second)
+                if ret != ErrType.OK:
+                    continue
+
+                self.logger.debug(f"BAUDCHK")
+                ret = self.send_request(BAUDCHK.to_bytes(1, byteorder="little"), 1, DEFAULT_TIMEOUT)
+                if ret == ErrType.OK:
+                    self.logger.debug("BAUDCHK ok")
+                    break
+                else:
+                    self.logger.error(f"BAUDCHK fail: {ret}")
+            else:
+                if self.is_usb:
+                    self.logger.debug(f"BAUDSET")
+                    _bytes = [BAUDSET]
+                    _bytes.append(index)
+                    cmd = bytearray(_bytes)
+                    ret = self.send_request(cmd, 2, DEFAULT_TIMEOUT)
+                    if ret == ErrType.OK:
+                        self.logger.debug(f"Baudset ok")
+                        break
+                    elif ret == ErrType.DEV_LENGTH:
+                        self.logger.debug(f"Device not in rom download mode")
+                        break
+                    else:
+                        self.logger.debug(f"Baudset fail: {ret}")
+                else:
+                    self.logger.debug("BAUDCHK")
+                    ret = self.send_request(BAUDCHK.to_bytes(1, byteorder="little"), 1, DEFAULT_TIMEOUT)
+                    if ret == ErrType.OK:
+                        self.logger.debug(f"Baudchk ok")
+                        break
+                    else:
+                        self.logger.debug(f"Baudchk fail: {ret}")
+
+        if ret == ErrType.OK or ret == ErrType.DEV_LENGTH:
+            self.logger.debug("Handshake done")
+        else:
+            self.logger.debug(f"Handshake fail: {ret}")
+
+        return ret
+
+    def check_alive(self):
+        ret, ch = self.ameba.read_bytes(DEFAULT_TIMEOUT)
+        if ret == ErrType.OK:
+            if ch[0] != NAK:
+                self.logger.debug(f"Check alive error,expect NAK, get 0x{ch.hex()}")
+                ret = ErrType.SYS_PROTO
+        else:
+            self.logger.debug(f"Check alive error: {ret}")
+
+        return ret
+
+    def transfer(self, address, data_bytes):
+        self.logger.debug(f"STX {self.stx_packet_no}#: addr={hex(address)}")
+        stx_data = [STX]
+        stx_data.append(self.stx_packet_no & 0xFF)
+        stx_data.append((~self.stx_packet_no) & 0xFF)
+
+        stx_data.extend(list(address.to_bytes(4, byteorder='little')))
+
+        stx_bytes = bytearray(stx_data)
+        stx_bytes += data_bytes
+
+        checksum = sum(stx_bytes[3:]) % 256
+        stx_bytes += checksum.to_bytes(1, byteorder="little")
+
+        ret = self.send_request(stx_bytes, len(stx_bytes), STX_TIMEOUT)
+        if ret == ErrType.OK:
+            self.logger.debug(f"STX {self.stx_packet_no}# done")
+            self.stx_packet_no += 1
+        else:
+            self.logger.debug(f"STX {self.stx_packet_no}# fail: {ret}")
+
+        return ret
+
+    def end_transfer(self):
+        self.logger.debug(f"EOT")
+        return self.send_request(EOT.to_bytes(1, byteorder="little"), 1, DEFAULT_TIMEOUT)
+
+    def abort(self):
+        self.logger.debug(f"ESC")
+        self.send_request(ESC.to_bytes(1, byteorder="little"), 1, DEFAULT_TIMEOUT)
+
+    def get_page_aligned_size(self, size, page_size):
+        result = size
+
+        if (size % page_size) != 0:
+            result = (size // page_size + 1) * page_size
+
+        return result
+
+    def get_floader_path(self):
+        floader_path = None
+
+        if self.profile.floader:
+            floader_path = os.path.realpath(os.path.join(RtkUtils.get_executable_root_path(), FloaderDictionary, self.profile.floader))
+
+        if floader_path is None:
+            self.logger.error("Flashloader not specified in device profile")
+        elif not os.path.exists(floader_path):
+            self.logger.error(f"Flashloader not exists: {floader_path}")
+
+        return floader_path
+
+    def download_floader(self):
+        ret = ErrType.OK
+        page_size = StxUsbDataLen if self.is_usb else StxUartDataLen
+        self.reset()
+
+        floader = self.get_floader_path()
+        if floader is None:
+            return ErrType.SYS_PARAMETER
+        with open(floader, 'rb') as stream:
+            floader_content = stream.read()
+
+        floader_size = len(floader_content)
+        if floader_size > FloaderSizeLimit:
+            self.logger.error(f"Invalid floader {floader} with too large size: {floader_size}")
+            return ErrType.SYS_OVERRANGE
+
+        _baud_bytes = self.serial_port.baudrate.to_bytes(4, byteorder='little')
+
+        floader_aligned_size = self.get_page_aligned_size(floader_size, page_size)
+        datas = io.BytesIO(floader_content)
+        data_bytes = datas.read(floader_size)
+
+        data_bytes += _baud_bytes
+
+        data_bytes = data_bytes.ljust(floader_aligned_size, b"\x00")
+
+        idx = 0
+        floader_addr = self.profile.floader_address
+        while idx < floader_aligned_size:
+            trans_data = data_bytes[idx:idx+page_size]
+            ret = self.transfer(floader_addr, trans_data)
+            if ret != ErrType.OK:
+                return ret
+            idx += page_size
+            floader_addr += page_size
+
+        ret = self.end_transfer()
+        if ret != ErrType.OK:
+            if self.profile.is_amebaz():
+                # AmebaZ would tx ACK after rx EOT but would not wait tx ACK done, so in low baudrate(115200...),
+                # ACK will not be received
+                # This issue has been fixed after AmebaD
+                ret = ErrType.OK
+
+        return ret
diff --git a/ameba/scripts/flash/base/rt_settings.py b/ameba/scripts/flash/base/rt_settings.py
new file mode 100644
index 00000000..7652a168
--- /dev/null
+++ b/ameba/scripts/flash/base/rt_settings.py
@@ -0,0 +1,74 @@
+#! /usr/bin/env python
+# -*- coding: utf-8 -*-
+
+# Copyright (c) 2024 Realtek Semiconductor Corp.
+# SPDX-License-Identifier: Apache-2.0
+
+
+class RtSettings():
+    MIN_ROM_BOOT_DELAY_IN_MILLISECOND = 50
+    MIN_USB_ROM_BOOT_DELAY_IN_MILLISECOND = 200
+    MIN_USB_FLOADER_BOOT_DELAY_IN_MILLISECOND = 200
+
+    FLASH_PROTECTION_PROCESS_PROMPT = 0
+    FLASH_PROTECTION_PROCESS_TRY = 1
+    FLASH_PROTECTION_PROCESS_UNLOCK = 2
+    FLASH_PROTECTION_PROCESS_ABORT = 3
+
+    def __init__(self, **kwargs):
+        self.sense_packet_count = kwargs.get("SensePacketCount", 32)
+        self.request_retry_count = kwargs.get("RequestRetryCount", 3)
+        self.request_retry_interval_second = round(kwargs.get("RequestRetryIntervalInMillisecond", 10) / 1000, 2)
+        self.async_response_timeout_in_second = round(kwargs.get("AsyncResponseTimeoutInMilliseccond", 1000) / 1000, 2)
+        self.sync_response_timeout_in_second = round(kwargs.get("SyncResponseTimeoutInMillisecond", 1000) / 1000, 2)
+        self.baudrate_switch_delay_in_second = round(kwargs.get("BaudrateSwitchDelayInMillisecond", 200) / 1000, 2)
+        self.rom_boot_delay_in_second = round(max(kwargs.get("RomBootDelayInMillisecond", 100), self.MIN_ROM_BOOT_DELAY_IN_MILLISECOND) / 1000, 2)
+        self.usb_rom_boot_delay_in_second = round(max(kwargs.get("UsbRomBootDelayInMillisecond", 1000), self.MIN_USB_ROM_BOOT_DELAY_IN_MILLISECOND) / 1000, 2)
+        self.usb_floader_boot_delay_in_second = round(max(kwargs.get("UsbFloaderBootDelayInMillisecond", 1000), self.MIN_USB_FLOADER_BOOT_DELAY_IN_MILLISECOND) / 1000, 2)
+        self.switch_baudrate_at_floader = kwargs.get("SwitchBaudrateAtFloader", 0)
+        self.write_response_timeout_in_second = round(kwargs.get("WriteResponseTimeoutInMillisecond", 2000) / 1000, 2)
+        self.floader_boot_delay_in_second = round(kwargs.get("FloaderBootDelayInMillisecond", 1000) / 1000, 2)
+        self.auto_switch_to_download_mode_with_dtr_rts = kwargs.get("AutoSwitchToDownloadModeWithDtrRts", 0)
+        self.auto_reset_device_with_dtr_rts = kwargs.get("AutoResetDeviceWithDtrRts", 0)
+        self.flash_protection_process = kwargs.get("FlashProtectionProcess", self.FLASH_PROTECTION_PROCESS_PROMPT)
+        self.erase_by_block = kwargs.get("EraseByBlock", 0)
+        self.program_config1 = kwargs.get("ProgramConfig1", 0)
+        self.program_config2 = kwargs.get("ProgramConfig2", 0)
+        self.disable_nand_access_with_uart = kwargs.get("DisableNandAccessWithUart", 0)
+        self.ram_download_padding_byte = kwargs.get("RamDownloadPaddingByte", 0x00)
+        self.auto_program_spic_addr_mode_4byte = kwargs.get("AutoProgramSpicAddrMode4Byte", 0)
+        self.auto_switch_to_download_mode_with_dtr_rts_file = kwargs.get("AutoSwitchToDownloadModeWithDtrRtsTimingFile", "Reburn.cfg")
+        self.auto_reset_device_with_dtr_rts_file = kwargs.get("AutoResetDeviceWithDtrRtsTimingFile", "Reset.cfg")
+        self.post_process = kwargs.get("PostProcess", "RESET")
+        self.serial_initial_read_timeout_in_second = round(kwargs.get("SerialInitialReadTimeoutInMillisecond", 20) / 1000, 2)
+
+    def __repr__(self):
+        profile_dict = {
+            "SensePacketCount": self.sense_packet_count,
+            "RequestRetryCount": self.request_retry_count,
+            "RequestRetryIntervalInMillisecond": int(self.request_retry_interval_second * 1000),
+            "AsyncResponseTimeoutInMilliseccond": int(self.async_response_timeout_in_second * 1000),
+            "SyncResponseTimeoutInMillisecond": int(self.sync_response_timeout_in_second * 1000),
+            "BaudrateSwitchDelayInMillisecond": int(self.baudrate_switch_delay_in_second * 1000),
+            "RomBootDelayInMillisecond": int(self.rom_boot_delay_in_second * 1000),
+            "UsbRomBootDelayInMillisecond": int(self.usb_rom_boot_delay_in_second * 1000),
+            "UsbFloaderBootDelayInMillisecond": int(self.usb_floader_boot_delay_in_second * 1000),
+            "SerialInitialReadTimeoutInMillisecond": int(self.serial_initial_read_timeout_in_second * 1000),
+            "SwitchBaudrateAtFloader": self.switch_baudrate_at_floader,
+            "WriteResponseTimeoutInMillisecond": int(self.write_response_timeout_in_second * 1000),
+            "FloaderBootDelayInMillisecond": int(self.floader_boot_delay_in_second * 1000),
+            "AutoSwitchToDownloadModeWithDtrRts": self.auto_switch_to_download_mode_with_dtr_rts,
+            "AutoResetDeviceWithDtrRts": self.auto_reset_device_with_dtr_rts,
+            "FlashProtectionProcess": self.flash_protection_process,
+            "EraseByBlock": self.erase_by_block,
+            "ProgramConfig1": self.program_config1,
+            "ProgramConfig2": self.program_config2,
+            "DisableNandAccessWithUart": self.disable_nand_access_with_uart,
+            "RamDownloadPaddingByte": self.ram_download_padding_byte,
+            "AutoProgramSpicAddrMode4Byte": self.auto_program_spic_addr_mode_4byte,
+            "AutoSwitchToDownloadModeWithDtrRtsTimingFile": self.auto_switch_to_download_mode_with_dtr_rts_file,
+            "AutoResetDeviceWithDtrRtsTimingFile": self.auto_reset_device_with_dtr_rts_file,
+            "PostProcess": self.post_process
+        }
+
+        return profile_dict
diff --git a/ameba/scripts/flash/base/rtk_flash_type.py b/ameba/scripts/flash/base/rtk_flash_type.py
new file mode 100644
index 00000000..fc66df60
--- /dev/null
+++ b/ameba/scripts/flash/base/rtk_flash_type.py
@@ -0,0 +1,12 @@
+#! /usr/bin/env python
+# -*- coding: utf-8 -*-
+
+# Copyright (c) 2024 Realtek Semiconductor Corp.
+# SPDX-License-Identifier: Apache-2.0
+
+from enum import Enum
+
+
+class RtkFlashType(Enum):
+    NOR = 0
+    NAND = 1
diff --git a/ameba/scripts/flash/base/rtk_logging.py b/ameba/scripts/flash/base/rtk_logging.py
new file mode 100644
index 00000000..977acbff
--- /dev/null
+++ b/ameba/scripts/flash/base/rtk_logging.py
@@ -0,0 +1,49 @@
+#! /usr/bin/env python
+# -*- coding: utf-8 -*-
+
+# Copyright (c) 2024 Realtek Semiconductor Corp.
+# SPDX-License-Identifier: Apache-2.0
+
+import sys
+import logging
+from colorama import Fore, Style, init
+
+# init Colorama
+init(autoreset=True)
+
+
+def create_logger(name, log_level="INFO", stream=sys.stdout, file=None):
+    if log_level == "DEBUG":
+        level = logging.DEBUG
+    elif log_level == "WARNING":
+        level = logging.WARNING
+    elif log_level == "ERROR":
+        level = logging.ERROR
+    elif log_level == "FATAL":
+        level = logging.FATAL
+    else:
+        level = logging.INFO
+
+    logger = logging.getLogger(name)
+    if not logger.handlers:
+        formatter = logging.Formatter(
+            fmt=f'[%(asctime)s.%(msecs)03d][%(levelname)s] [{name}]%(message)s',
+            datefmt='%Y-%m-%d %H:%M:%S')
+
+        logging.addLevelName(logging.DEBUG, f"D")
+        logging.addLevelName(logging.INFO, f"I")
+        logging.addLevelName(logging.WARNING, f"{Fore.YELLOW}W{Style.RESET_ALL}")
+        logging.addLevelName(logging.ERROR, f"{Fore.RED}E{Style.RESET_ALL}")
+        logging.addLevelName(logging.FATAL, f"{Fore.RED}{Style.BRIGHT}F{Style.RESET_ALL}")
+        consoleHandler = logging.StreamHandler(stream)
+        consoleHandler.setFormatter(formatter)
+        logger.addHandler(consoleHandler)
+
+        if file is not None:
+            fileHandler = logging.FileHandler(file, mode='a')
+            fileHandler.setFormatter(formatter)
+            logger.addHandler(fileHandler)
+
+        logger.propagate = False  # Prevent logging from propagating to the root logger
+        logger.setLevel(level)
+    return logger
diff --git a/ameba/scripts/flash/base/rtk_utils.py b/ameba/scripts/flash/base/rtk_utils.py
new file mode 100644
index 00000000..8568b357
--- /dev/null
+++ b/ameba/scripts/flash/base/rtk_utils.py
@@ -0,0 +1,21 @@
+#! /usr/bin/env python
+# -*- coding: utf-8 -*-
+
+# Copyright (c) 2024 Realtek Semiconductor Corp.
+# SPDX-License-Identifier: Apache-2.0
+
+import os
+import sys
+
+
+class RtkUtils:
+    @staticmethod
+    def get_executable_root_path():
+        if getattr(sys, 'frozen', False):  # judge if frozen as exe
+            # get exe dir
+            executable_root = os.path.dirname(os.path.abspath(sys.executable))
+        else:
+            # get py dir
+            executable_root = os.path.dirname(os.path.dirname(os.path.abspath(__file__)))
+
+        return executable_root
diff --git a/ameba/scripts/flash/base/sense_status.py b/ameba/scripts/flash/base/sense_status.py
new file mode 100644
index 00000000..bb678c70
--- /dev/null
+++ b/ameba/scripts/flash/base/sense_status.py
@@ -0,0 +1,24 @@
+#! /usr/bin/env python
+# -*- coding: utf-8 -*-
+
+# Copyright (c) 2024 Realtek Semiconductor Corp.
+# SPDX-License-Identifier: Apache-2.0
+
+from .errno import *
+
+
+class SenseStatus:
+    def __init__(self):
+        self.op_code = None
+        self.status = None
+        self.data = None
+
+    def parse(self, data, offset):
+        ret = ErrType.SYS_OVERRANGE
+        if len(data) >= offset + 6:
+            self.op_code = data[offset]
+            self.status = data[offset + 1]
+            self.data = data[offset+2] + (data[offset+3]<<8) + (data[offset+4]<<16) + (data[offset+5]<<24)
+            ret = ErrType.OK
+
+        return ret
diff --git a/ameba/scripts/flash/base/spic_addr_mode.py b/ameba/scripts/flash/base/spic_addr_mode.py
new file mode 100644
index 00000000..81f5d228
--- /dev/null
+++ b/ameba/scripts/flash/base/spic_addr_mode.py
@@ -0,0 +1,12 @@
+#! /usr/bin/env python
+# -*- coding: utf-8 -*-
+
+# Copyright (c) 2024 Realtek Semiconductor Corp.
+# SPDX-License-Identifier: Apache-2.0
+
+from enum import Enum
+
+
+class SpicAddrMode(Enum):
+    THREE_BYTE_MODE = 0
+    FOUR_BYTE_MODE = 1
diff --git a/ameba/scripts/flash/base/sys_utils.py b/ameba/scripts/flash/base/sys_utils.py
new file mode 100644
index 00000000..2abc7524
--- /dev/null
+++ b/ameba/scripts/flash/base/sys_utils.py
@@ -0,0 +1,9 @@
+#! /usr/bin/env python
+# -*- coding: utf-8 -*-
+
+# Copyright (c) 2024 Realtek Semiconductor Corp.
+# SPDX-License-Identifier: Apache-2.0
+
+
+def divide_then_round_up(dividend, divisor):
+    return int((dividend + divisor - 1) / divisor)
diff --git a/ameba/scripts/flash/base/version.py b/ameba/scripts/flash/base/version.py
new file mode 100644
index 00000000..4c4917f7
--- /dev/null
+++ b/ameba/scripts/flash/base/version.py
@@ -0,0 +1,16 @@
+#! /usr/bin/env python
+# -*- coding: utf-8 -*-
+
+# Copyright (c) 2024 Realtek Semiconductor Corp.
+# SPDX-License-Identifier: Apache-2.0
+
+class Version:
+    def __init__(self, version_str):
+        # parser version_str with pattern major.minor.micro
+        parts = version_str.split(".")
+        self.major = int(parts[0])
+        self.minor = int(parts[1] if len(parts) > 1 else 0)
+        self.micro = int(parts[2] if len(parts) > 2 else 0)
+
+    def __repr__(self):
+        return f"{self.major}.{self.minor}.{self.micro}"
diff --git a/ameba/scripts/flash/version_info.py b/ameba/scripts/flash/version_info.py
new file mode 100644
index 00000000..a1739b4e
--- /dev/null
+++ b/ameba/scripts/flash/version_info.py
@@ -0,0 +1,7 @@
+#! /usr/bin/env python
+# -*- coding: utf-8 -*-
+
+# Copyright (c) 2024 Realtek Semiconductor Corp.
+# SPDX-License-Identifier: Apache-2.0
+
+version = "1.1.4.0"
diff --git a/ameba/scripts/image_process/ameba_enums.py b/ameba/scripts/image_process/ameba_enums.py
index 1cd5e298..0337b794 100644
--- a/ameba/scripts/image_process/ameba_enums.py
+++ b/ameba/scripts/image_process/ameba_enums.py
@@ -54,4 +54,4 @@ def __str__(self):
 
     @staticmethod
     def success(message = ''):
-        return Error(ErrorType.SUCCESS, message)
\ No newline at end of file
+        return Error(ErrorType.SUCCESS, message)
diff --git a/ameba/scripts/image_process/manifest_manager.py b/ameba/scripts/image_process/manifest_manager.py
index 63fc11b8..4e11e502 100644
--- a/ameba/scripts/image_process/manifest_manager.py
+++ b/ameba/scripts/image_process/manifest_manager.py
@@ -7,6 +7,9 @@
 from enum import Enum, unique
 from typing import Union, List
 import copy
+from cryptography.hazmat.primitives.asymmetric import ed25519
+from cryptography.hazmat.primitives.asymmetric import ec
+from cryptography.hazmat.primitives import serialization
 
 from ameba_enums import *
 from context import Context
@@ -115,16 +118,15 @@ def __init__(self, config: dict, image_type:ImageType) -> None:
         #SBOOT:
         if image_type in [ImageType.IMAGE1, ImageType.IMAGE2, ImageType.CERT]:  #image3 is not required
             self.sboot_enable:bool = config.get("sboot_enable", config.get("secure_boot_en", False))
-            if self.sboot_enable:
-                self.sboot_algorithm:str = config["sboot_algorithm"] if "sboot_algorithm" in config else config["algorithm"]
-                self.sboot_hash_alg:str = config["sboot_hash_alg"] if "sboot_hash_alg" in config else config["hash_alg"]
-                if "sboot_hmac_key" in config:
-                    self.sboot_hmac_key:str = config[config["sboot_hmac_key"]] if config["sboot_hmac_key"] in config else config["sboot_hmac_key"]
-                else:
-                    self.sboot_hmac_key:str = config["hmac_key"]
-                self.sboot_private_key:str = config["sboot_private_key"] if "sboot_private_key" in config else config["private_key"]
-                self.sboot_public_key:str = config["sboot_public_key"] if "sboot_public_key" in config else config["public_key"]
-            self.sboot_public_key_hash:str = config["sboot_public_key_hash"] if "sboot_public_key_hash" in config else config["public_key_hash"]
+            self.sboot_algorithm:str = config["sboot_algorithm"] if "sboot_algorithm" in config else config.get("algorithm", "")
+            self.sboot_hash_alg:str = config["sboot_hash_alg"] if "sboot_hash_alg" in config else config.get("hash_alg", "")
+            if "sboot_hmac_key" in config:
+                self.sboot_hmac_key:str = config[config["sboot_hmac_key"]] if config["sboot_hmac_key"] in config else config["sboot_hmac_key"]
+            else:
+                self.sboot_hmac_key:str = config.get("hmac_key", "")
+            self.sboot_private_key:str = config["sboot_private_key"] if "sboot_private_key" in config else config.get("private_key", "")
+            self.sboot_public_key:str = config["sboot_public_key"] if "sboot_public_key" in config else config.get("public_key", "")
+            self.sboot_public_key_hash:str = config["sboot_public_key_hash"] if "sboot_public_key_hash" in config else config.get("public_key_hash", "")
 
 class ManifestManager(ABC):
     valid_algorithm = importlib.import_module('security').secure_boot.valid_algorithm
@@ -139,23 +141,7 @@ def __init__(self, context: Context) -> None:
         self.lib_security = importlib.import_module('security')
         self.sboot = self.lib_security.secure_boot()
 
-        self.new_json_data = copy.deepcopy(self.origin_json_data)
-        # Add key from outside(global config) of image part if key not in image part
-        for img in ['image1', 'image2', 'image3', 'cert']:
-            if img not in self.new_json_data:
-                context.logger.info(f"manifest file does not contains {img}")
-                continue
-            #优先级: image内部直接定义>inherit_from>外部的全局定义
-            if "inherit_from" in self.new_json_data[img]:
-                for key, value in self.new_json_data[self.new_json_data[img]["inherit_from"]].items():
-                    if key not in self.new_json_data[img]:
-                        self.new_json_data[img][key] = value
-            for key, value in self.origin_json_data.items():
-                if isinstance(value, dict): continue
-
-                if key not in self.new_json_data[img]:
-                    self.new_json_data[img][key] = value
-
+        self.new_json_data = manifest_preprocess(self.origin_json_data)
         if not self.validate_config(self.new_json_data):
             raise ValueError(f"Invalid JSON format")
 
@@ -473,3 +459,65 @@ def create_keypair(context:Context, output_file:str, algorithm:str) -> Error:
         with open(output_file, 'w') as f:
             json.dump(key_info, f, indent=2)
         return Error.success()
+
+    def transform_to_pem(self, output_file:str, algorithm:str, image_type) -> Error:
+        supportted_alg = ['ed25519', 'secp256r1']
+        if algorithm not in supportted_alg:
+            self.context.logger.error(f"not support algorithm: {algorithm}, support: {supportted_alg}")
+            return Error(ErrorType.INVALID_ARGS, "not support algorithm")
+        image_config = self.get_image_config(image_type)
+        private_key = bytes.fromhex(image_config.sboot_private_key)
+        public_key = bytes.fromhex(image_config.sboot_public_key)
+        public_key_hash_hex = image_config.sboot_public_key_hash
+        final_priv = None
+        if algorithm == 'ed25519':
+            seed = private_key[:32]
+            expected_pk = public_key
+            priv = ed25519.Ed25519PrivateKey.from_private_bytes(seed)
+            pub = priv.public_key()
+            pub_raw = pub.public_bytes(
+                encoding=serialization.Encoding.Raw,
+                format=serialization.PublicFormat.Raw
+            )
+            if pub_raw == expected_pk:
+                final_priv = priv
+            calc_hash = hashlib.sha256(pub_raw).hexdigest().upper()
+            json_hash_upper = public_key_hash_hex.upper()
+            if calc_hash != json_hash_upper:
+                self.context.logger.warning(f"hash not match: {json_hash_upper} vs {calc_hash}")
+        elif algorithm == 'secp256r1':
+            private_value = int.from_bytes(private_key, byteorder='big')
+            final_priv = ec.derive_private_key(private_value, ec.SECP256R1())
+            pub = final_priv.public_key()
+            pub_raw = pub.public_bytes(
+                encoding=serialization.Encoding.X962,
+                format=serialization.PublicFormat.UncompressedPoint
+            )
+            expected_pk = public_key
+            pub_to_compare = pub_raw
+            if len(expected_pk) == 64 and len(pub_raw) == 65:
+                pub_to_compare = pub_raw[1:]
+
+            if pub_to_compare != expected_pk:
+                self.context.logger.warning(
+                    f"Public key mismatch! Config: {expected_pk.hex()[:10]}... Derived: {pub_to_compare.hex()[:10]}..."
+                )
+            calc_hash = hashlib.sha256(pub_raw).hexdigest().upper()
+            json_hash_upper = public_key_hash_hex.upper()
+
+            if calc_hash != json_hash_upper:
+                calc_hash_no_header = hashlib.sha256(pub_raw[1:]).hexdigest().upper()
+                if calc_hash_no_header == json_hash_upper:
+                    pass
+                else:
+                    self.context.logger.warning(f"hash not match: {json_hash_upper} vs {calc_hash}")
+
+        enc = serialization.NoEncryption()
+        pem_pkcs8 = final_priv.private_bytes(
+            encoding=serialization.Encoding.PEM,
+            format=serialization.PrivateFormat.PKCS8,
+            encryption_algorithm=enc
+        )
+        with open(output_file, "wb") as f:
+            f.write(pem_pkcs8)
+        return Error.success()
diff --git a/ameba/scripts/image_process/op_base.py b/ameba/scripts/image_process/op_base.py
index 06c04f20..0fc3126c 100644
--- a/ameba/scripts/image_process/op_base.py
+++ b/ameba/scripts/image_process/op_base.py
@@ -47,3 +47,17 @@ def require_manifest_file(context:Context) -> bool:...
     @staticmethod
     @abstractmethod
     def require_layout_file(context:Context) -> bool:...
+
+class OperationEmpty(OperationBase):
+    cmd_help_msg = 'Internal using for create Context'
+
+    def __init__(self, context:Context) -> None:
+        super().__init__(context)
+
+    @staticmethod
+    def require_manifest_file(context:Context) -> bool:
+        return True
+
+    @staticmethod
+    def require_layout_file(context:Context) -> bool:
+        return True
diff --git a/ameba/scripts/image_process/op_cut.py b/ameba/scripts/image_process/op_cut.py
index 740c5a40..68f198c8 100644
--- a/ameba/scripts/image_process/op_cut.py
+++ b/ameba/scripts/image_process/op_cut.py
@@ -3,6 +3,7 @@
 from op_base import OperationBase
 from context import Context
 from ameba_enums import *
+from utility import BasedIntParamType
 
 class Cut(OperationBase):
     cmd_help_msg = 'Cut a file to remove the given length'
@@ -14,9 +15,9 @@ def __init__(self, context:Context) -> None:
     def register_args(parser) -> None:
         parser.add_argument('-i', '--input-file', help='Input file to be processed', required=True)
         parser.add_argument('-o', '--output-file', help='Output file', required=True)
-        parser.add_argument('-l', '--length', type=int, help='Length in bytes to remove', required=True)
+        parser.add_argument('-l', '--length', type=BasedIntParamType(), help='Length in bytes to remove', required=True)
         parser.add_argument('-B', '--backward', action='store_true', help='Cut from the end of the file', default=False)
-        parser.add_argument('-O', '--offset', type=int, help='Offset bytes from the cutting direction, default=0', default=0)
+        parser.add_argument('-O', '--offset', type=BasedIntParamType(), help='Offset bytes from the cutting direction, default=0', default=0)
 
     @staticmethod
     def require_manifest_file(context:Context) -> bool:
diff --git a/ameba/scripts/image_process/op_encrypt.py b/ameba/scripts/image_process/op_encrypt.py
index 40be5d57..629cb08d 100644
--- a/ameba/scripts/image_process/op_encrypt.py
+++ b/ameba/scripts/image_process/op_encrypt.py
@@ -40,6 +40,12 @@ def register_args(parser) -> None:
         sub.add_argument('-a', '--algorithm', type=str, choices=ManifestManager.valid_algorithm, help='Algorithm to generate key pair', required=True)
         sub.add_argument('-o', '--output-file', help='Output key pair file', required=True)
 
+        #NOTE: args for topem
+        sub = subparsers.add_parser('topem', help='Transform to pem format')
+        sub.add_argument('-o', '--output-file', help='Output pem file', required=True)
+        sub.add_argument('-a', '--algorithm', type=str, choices=ManifestManager.valid_algorithm, help='Algorithm to generate key pair', required=True)
+        sub.add_argument('-m', '--image', choices=['image1', 'image2'], help='Output pem file', required=True)
+
     @staticmethod
     def require_manifest_file(context:Context) -> bool:
         return context.args.sub_operation != "keypair"
@@ -72,6 +78,12 @@ def process(self) -> Error:
                 self.context.args.output_file,
                 self.context.args.algorithm
             )
+        elif self.context.args.sub_operation == "topem":
+            return self.transform_to_pem(
+                self.context.args.output_file,
+                self.context.args.algorithm,
+                self.context.args.image
+            )
         else:
             return Error(ErrorType.INVALID_INPUT)
 
@@ -97,3 +109,8 @@ def create_sboot(self, output_file:str, input_file:str) -> Error:
     def create_keypair(self, output_file:str, algorithm:str) -> Error:
         self.logger.info(f"create keypair file for {algorithm}")
         return ManifestManager.create_keypair(self.context, output_file, algorithm)
+
+    @exit_on_failure(catch_exception=True)
+    def transform_to_pem(self, output_file:str, algorithm:str, image:str) -> Error:
+        self.logger.info(f"transform to pem {algorithm}")
+        return self.manifest_manager.transform_to_pem(output_file, algorithm, ImageType[image.upper()])
diff --git a/ameba/scripts/image_process/op_helper.py b/ameba/scripts/image_process/op_helper.py
new file mode 100644
index 00000000..0eebe850
--- /dev/null
+++ b/ameba/scripts/image_process/op_helper.py
@@ -0,0 +1,48 @@
+import json
+
+from op_base import OperationBase
+from context import Context
+from ameba_enums import *
+from utility import *
+
+class Helper(OperationBase):
+    cmd_help_msg = 'Common helpers'
+
+    def __init__(self, context:Context) -> None:
+        super().__init__(context)
+
+    @staticmethod
+    def register_args(parser) -> None:
+        subparsers = parser.add_subparsers(dest='sub_operation', help='Available operations for helper', required=True)
+
+        #NOTE: args for cert
+        sub = subparsers.add_parser('manifest-fmt', help='Format manifest file from json5 to json format')
+        sub.add_argument('-o', '--output-file', help='Output certificate file', required=True)
+
+    @staticmethod
+    def require_manifest_file(context:Context) -> bool:
+        return True
+
+    @staticmethod
+    def require_layout_file(context:Context) -> bool:
+        return False
+
+    def pre_process(self) -> Error:
+        return Error.success()
+
+    def process(self) -> Error:
+        if self.context.args.sub_operation == "manifest-fmt":
+            return self.manifest_format(
+                self.context.args.output_file,
+            )
+        else:
+            return Error(ErrorType.INVALID_INPUT)
+
+    def post_process(self) -> Error:
+        return Error.success()
+
+    @exit_on_failure(catch_exception=True)
+    def manifest_format(self, output_file:str) -> Error:
+        with open(output_file, "w") as f:
+            json.dump(manifest_preprocess(self.context.manifest_data), f, indent=2)
+        return Error.success()
diff --git a/ameba/scripts/image_process/op_ota_prepend_header.py b/ameba/scripts/image_process/op_ota_prepend_header.py
index 14f7e556..f06f03b9 100644
--- a/ameba/scripts/image_process/op_ota_prepend_header.py
+++ b/ameba/scripts/image_process/op_ota_prepend_header.py
@@ -94,4 +94,4 @@ def update_header(self, image_file:str, image_id:int) -> None:
         if image_id != 0xFF:
             self.header += struct.pack('>I', self.ota_sign)
             self.header += struct.pack('<IIIII', self.header_length, self.check_sum, image_size, self.offset, image_id)
-        self.offset += image_size
\ No newline at end of file
+        self.offset += image_size
diff --git a/ameba/scripts/image_process/op_pad.py b/ameba/scripts/image_process/op_pad.py
index b6f61784..0fbd08ec 100644
--- a/ameba/scripts/image_process/op_pad.py
+++ b/ameba/scripts/image_process/op_pad.py
@@ -1,4 +1,5 @@
 import os
+import click
 
 from op_base import OperationBase
 from context import Context
@@ -6,15 +7,31 @@
 from utility import *
 
 class Pad(OperationBase):
-    cmd_help_msg = 'Pad binary file to align a given length'
+    cmd_help_msg = 'BIN File Padding Tool: Pad specified hex value to the head/tail of a BIN file, supporting two padding length rules (alignment/fixed length)'
 
     def __init__(self, context:Context) -> None:
         super().__init__(context)
 
     @staticmethod
     def register_args(parser) -> None:
-        parser.add_argument('-l', '--length', type=int, help='Pad length in bytes', required=True)
-        parser.add_argument('-i', '--input-file', help='Input file to be process', required=True)
+        parser.add_argument('-l', '--length', type=BasedIntParamType(),
+                            help='Base padding length in bytes, works with --align to determine final file length rule',
+                            required=True)
+        parser.add_argument('-i', '--input-file',
+                            help='Path to the BIN file to be processed (required)',
+                            required=True)
+        parser.add_argument('-v', '--value', type=BasedIntParamType(),
+                            help='Padding value in hexadecimal, default 0xFF',
+                            default="0xFF")
+        parser.add_argument('-s', '--from-head', action='store_true',
+                            help='Pad from the head of the file (default from tail)',
+                            default=False)
+        parser.add_argument('--no-align', action='store_true',
+                            help='Donot align total file length to --length value after padding (enabled by default); enable to insert exactly --length bytes',
+                            default=False)
+        parser.add_argument('-o', '--output-file',
+                            help='Path to the output file (optional). If specified, padded content is written to this file (original file remains unchanged); if not specified, modify the input file in-place',
+                            default=None)
 
     @staticmethod
     def require_manifest_file(context:Context) -> bool:
@@ -26,17 +43,44 @@ def require_layout_file(context:Context) -> bool:
 
     # @exit_on_failure(catch_exception=True)
     @staticmethod
-    def execute(context:Context, input_file:str, length:int):
+    def execute(context:Context, input_file:str, length:int, value:int = 0xFF, from_head:bool = False, no_align:bool = False, output_file = None):
         context.logger.info("process pad file")
         file_size = os.path.getsize(input_file)
-        if file_size == 0:
-            pad_count = 0
+        if no_align:
+            pad_count = length
         else:
-            new_size = ((file_size - 1) // length + 1) * length
-            pad_count = new_size - file_size
+            if file_size == 0:
+                pad_count = 0
+            else:
+                new_size = ((file_size - 1) // length + 1) * length
+                pad_count = new_size - file_size
 
-        with open(input_file, "ab+") as file:
-            file.write(b'\xFF' * pad_count)
+        if pad_count <= 0:
+            return Error.success()
+
+        pad_byte = bytes([value & 0xFF])
+        pad_data = pad_byte * pad_count
+        if from_head:
+            with open(input_file, "rb") as f:
+                original_data = f.read()
+            if output_file:
+                with open(output_file, "wb") as f:
+                    f.write(pad_data)
+                    f.write(original_data)
+            else:
+                with open(input_file, "wb") as f:
+                    f.write(pad_data)
+                    f.write(original_data)
+        else:
+            if output_file:
+                with open(input_file, "rb") as f:
+                    original_data = f.read()
+                with open(output_file, "wb") as f:
+                    f.write(original_data)
+                    f.write(pad_data)
+            else:
+                with open(input_file, "ab+") as f:
+                    f.write(pad_data)
         return Error.success()
 
     def pre_process(self) -> Error:
@@ -48,7 +92,8 @@ def pre_process(self) -> Error:
         return Error.success()
 
     def process(self) -> Error:
-        return Pad.execute(self.context, self.context.args.input_file, self.context.args.length)
+        return Pad.execute(self.context, self.context.args.input_file, self.context.args.length, self.context.args.value,
+                           self.context.args.from_head, self.context.args.no_align, self.context.args.output_file)
 
     def post_process(self) -> Error:
         return Error.success()
diff --git a/ameba/scripts/image_process/op_rsip.py b/ameba/scripts/image_process/op_rsip.py
index 5d671433..6e6859bb 100644
--- a/ameba/scripts/image_process/op_rsip.py
+++ b/ameba/scripts/image_process/op_rsip.py
@@ -18,7 +18,9 @@ def __init__(self, context:Context) -> None:
     def register_args(parser) -> None:
         parser.add_argument('-i', '--input-file', help='Input file to be process', required=True)
         parser.add_argument('-o', '--output-file', help='Output encrypted file', required=True)
-        parser.add_argument('-s', '--section', help='Section in layout file', required=True)
+        parser.add_argument('-s', '--section', help='Section in layout file', required=False)
+        parser.add_argument('--address', type = BasedIntParamType(), default = 0, help='Section address', required=False)
+        parser.add_argument('-t', '--type', help='Image type', default = 'UNKNOWN',required=False)
 
     @staticmethod
     def require_manifest_file(context:Context) -> bool:
@@ -30,7 +32,7 @@ def require_layout_file(context:Context) -> bool:
 
     # @exit_on_failure(catch_exception=True)
     @staticmethod
-    def execute(context:Context, output_file:str, input_file:str, section:str, image_type:ImageType = ImageType.UNKNOWN):
+    def execute(context:Context, output_file:str, input_file:str, section:str, address = 0x0, image_type:ImageType = ImageType.UNKNOWN):
         context.logger.info("process rsip file")
         layout_file = context.layout_file
 
@@ -40,10 +42,13 @@ def execute(context:Context, output_file:str, input_file:str, section:str, image
             image_type = parse_image_type(input_file)
         image_config = manifest_manager.get_image_config(image_type)
         if image_config.rsip_enable:
-            section_addr = get_layout_address(layout_file, section, "ORIGIN")
-            if section_addr == '':
-                context.logger.fatal(f"Failed to parse addr for {section} in {layout_file}")
-                return Error(ErrorType.INVALID_ARGS, f"Failed to parse addr for {section} in {layout_file}")
+            if section:
+                section_addr = get_layout_address(layout_file, section, "ORIGIN")
+                if section_addr == '':
+                    context.logger.fatal(f"Failed to parse addr for {section} in {layout_file}")
+                    return Error(ErrorType.INVALID_ARGS, f"Failed to parse addr for {section} in {layout_file}")
+            else:
+                section_addr = hex(address)
             lib_security = importlib.import_module('security')
             rsip = lib_security.RSIP(output_file, input_file, section_addr, image_config)
             if context.soc_project == "amebad":
@@ -60,10 +65,20 @@ def pre_process(self) -> Error:
         if not os.path.exists(layout_file):
             self.logger.fatal(f"layout file not exist: {layout_file}")
             return Error(ErrorType.FILE_NOT_FOUND, layout_file)
+        if self.context.args.section and self.context.args.address:
+            self.logger.fatal(f"Use only --section or --address: {self.context.args.section}, {self.context.args.address}")
+            return Error(ErrorType.INVALID_ARGS)
         return Error.success()
 
     def process(self) -> Error:
-        return Rsip.execute(self.context, self.context.args.output_file, self.context.args.input_file, self.context.args.section)
+        return Rsip.execute(
+            self.context,
+            self.context.args.output_file,
+            self.context.args.input_file,
+            self.context.args.section,
+            self.context.args.address,
+            ImageType[f'{self.context.args.type.upper()}']
+        )
 
     def post_process(self) -> Error:
         return Error.success()
diff --git a/ameba/scripts/image_process/security.py b/ameba/scripts/image_process/security.py
old mode 100644
new mode 100755
diff --git a/ameba/scripts/image_process/utility.py b/ameba/scripts/image_process/utility.py
index 9fcad210..8fec55f4 100644
--- a/ameba/scripts/image_process/utility.py
+++ b/ameba/scripts/image_process/utility.py
@@ -7,6 +7,8 @@
 from typing import Callable, Union
 import traceback
 import hashlib
+import click
+import copy
 
 from ameba_enums import *
 
@@ -242,7 +244,7 @@ def parse_map_file(file_path:str, symbol:str) -> tuple:
         with open(file_path, 'r') as file:
             for line in file:
                 columns = line.strip().split()
-                if columns[2] == symbol:
+                if len(columns) >= 3 and columns[2] == symbol:
                     return tuple(columns)
     return ('0', '?', symbol)
 
@@ -301,3 +303,33 @@ def get_file_md5sum(file_path):
 
 def get_file_dir(file_path):
     return os.path.dirname(os.path.abspath(file_path))
+
+def manifest_preprocess(origin_data):
+    new_data = copy.deepcopy(origin_data)
+    # Add key from outside(global config) of image part if key not in image part
+    for img in ['image1', 'image2', 'image3', 'cert']:
+        if img not in new_data:
+            default_logger.info(f"manifest file does not contains {img}")
+            continue
+        #优先级: image内部直接定义>inherit_from>外部的全局定义
+        if "inherit_from" in new_data[img]:
+            for key, value in new_data[new_data[img]["inherit_from"]].items():
+                if key not in new_data[img]:
+                    new_data[img][key] = value
+        for key, value in origin_data.items():
+            if isinstance(value, dict): continue
+
+            if key not in new_data[img]:
+                new_data[img][key] = value
+    return new_data
+
+class BasedIntParamType(click.ParamType):
+    name = 'integer'
+
+    def convert(self, value, param, ctx):
+        try:
+            return int(value, 0)
+        except ValueError:
+            self.fail('%s is not a valid integer. Please use code literals '
+                      'prefixed with 0b/0B, 0o/0O, or 0x/0X as necessary.'
+                      % value, param, ctx)
diff --git a/ameba/scripts/merge_bin.py b/ameba/scripts/merge_bin.py
index 52ff8982..4a37aeb0 100644
--- a/ameba/scripts/merge_bin.py
+++ b/ameba/scripts/merge_bin.py
@@ -1,323 +1,410 @@
 #!/usr/bin/env python3
+# -*- coding: utf-8 -*-
+
 import os
 import sys
 import shutil
 import argparse
 import subprocess
+import logging
 from pathlib import Path
+from dataclasses import dataclass
+
+# --- Import Internal Modules ---
+THIS_DIR = Path(__file__).resolve().parent
+sys.path.append(str(THIS_DIR / 'image_process'))
+
+try:
+    from image_process.context import Context
+    from image_process.op_base import OperationEmpty
+    from image_process.op_cut import Cut as op_cut
+    from image_process.op_prepend_header import PrependHeader as op_prepend_header
+    from image_process.op_pad import Pad as op_pad
+    from image_process.utility import parse_map_file
+except ImportError:
+    print("Error: Failed to import 'image_process' modules.")
+    sys.exit(1)
+
+# --- Logging & Constants ---
+logging.basicConfig(level=logging.INFO, format='[%(levelname)s] %(message)s')
+logger = logging.getLogger(__name__)
+
+AXF2BIN_SCRIPT = THIS_DIR / 'axf2bin.py'
+
+@dataclass
+class ToolchainConfig:
+    objdump: Path
+    strip: Path
+    objcopy: Path
+
+# --- Infrastructure Class ---
+
+class FirmwarePacker:
+    """
+    Helper class providing tools, paths, and context management.
+    Also provides high-level helpers for common patterns (extract/pad/header).
+    """
+    def __init__(self, args, soc_name):
+        self.args = args
+        self.soc_name = soc_name
+        self.zephyr_bin = Path(args.bin_file).resolve()
+        self.out_dir = Path(args.out_dir).resolve()
+        self.module_dir = Path(args.module_dir).resolve()
+
+        # Map external SoC names to internal directory names
+        internal_map = {"amebag2": "amebagreen2"}
+        self.internal_name = internal_map.get(soc_name, soc_name.lower())
+
+        self.target_dir = self.out_dir / f'{self.internal_name}_gcc_project'
+        self.image_dir = self.out_dir / 'images'
+
+        # 1. Setup Toolchain first (independent)
+        self.tools = self._setup_toolchain()
+
+        # 2. Prepare Workspace IMMEDIATELY (Create dirs and copy manifest)
+        # NOTE: Context initialization DEPENDS on manifest.json5 existing in target_dir
+        self._prepare_workspace_internal()
+
+        # 3. Setup Context (Now safe because manifest exists)
+        self.context = self._setup_context()
+
+    def _setup_toolchain(self) -> ToolchainConfig:
+        variant = os.environ.get("ZEPHYR_TOOLCHAIN_VARIANT")
+        if not variant:
+            sys.exit("Error: ZEPHYR_TOOLCHAIN_VARIANT not set")
+
+        toolchain_path = None
+        prefix = None
+
+        if variant == "zephyr":
+            prefix = "arm-zephyr-eabi"
+            sdk_dir = os.environ.get("ZEPHYR_SDK_INSTALL_DIR")
+            if not sdk_dir:
+                sys.exit("Error: ZEPHYR_SDK_INSTALL_DIR not set")
+            toolchain_path = Path(sdk_dir) / "arm-zephyr-eabi" / "bin"
+        elif variant == "gnuarmemb":
+            prefix = "arm-none-eabi"
+            gnu_path = os.environ.get("GNUARMEMB_TOOLCHAIN_PATH")
+            if not gnu_path:
+                sys.exit("Error: GNUARMEMB_TOOLCHAIN_PATH not set")
+            toolchain_path = Path(gnu_path) / "bin"
+        else:
+            sys.exit(f"Unsupported toolchain variant: {variant}")
+
+        return ToolchainConfig(
+            objdump=toolchain_path / f"{prefix}-objdump",
+            strip=toolchain_path / f"{prefix}-strip",
+            objcopy=toolchain_path / f"{prefix}-objcopy"
+        )
+
+    def _prepare_workspace_internal(self):
+        """Internal setup: Create dirs and copy config files."""
+        if self.image_dir.exists():
+            shutil.rmtree(self.image_dir)
+        self.image_dir.mkdir(parents=True, exist_ok=True)
+        self.target_dir.mkdir(parents=True, exist_ok=True)
+
+        # Critical: Copy manifest BEFORE Context init
+        for f in ['manifest.json5', 'ameba_layout.ld']:
+            src = self.module_dir / 'ameba' / self.soc_name / f
+            if src.exists():
+                shutil.copy(src, self.target_dir)
+            else:
+                logger.warning(f"Warning: {f} not found at {src}")
+
+    def _setup_context(self) -> Context:
+        setattr(self.args, "post_build_dir", self.target_dir)
+        setattr(self.args, "log_level", 'WARNING')
+        setattr(self.args, "mp", 'n')
+        setattr(self.args, "extern_dir", None)
+        return Context(self.args, OperationEmpty)
+
+    def run_cmd(self, cmd: list):
+        cmd_str = [str(c) for c in cmd]
+        try:
+            subprocess.check_call(cmd_str, stdout=subprocess.DEVNULL)
+        except subprocess.CalledProcessError as e:
+            logger.error(f"Command failed: {' '.join(cmd_str)}")
+            sys.exit(e.returncode)
+
+    def axf2bin_run(self, mode, *args):
+        cmd = [sys.executable, str(AXF2BIN_SCRIPT)]
+        if mode == 'fw_pack':
+             cmd.extend(['--post-build-dir', str(self.target_dir)])
+        cmd.append(mode)
+        cmd.extend([str(a) for a in args])
+        self.run_cmd(cmd)
+
+    def concat_files(self, inputs: list, output: Path):
+        with open(output, 'wb') as outfile:
+            for f in inputs:
+                if f.exists():
+                    with open(f, 'rb') as infile:
+                        shutil.copyfileobj(infile, outfile)
+
+    def copy_blob(self, blob_name: str, dest_path: Path, optional=False):
+        blob_path = self.module_dir / 'zephyr' / 'blobs' / 'ameba' / self.soc_name / 'bin' / blob_name
+        if blob_path.exists():
+            shutil.copy(blob_path, dest_path)
+        elif not optional:
+            logger.error(f"Required blob not found: {blob_path}")
+            sys.exit(1)
+
+    def finalize_output(self, boot_bin: Path, app_bin: Path):
+        if app_bin.exists():
+            shutil.move(str(boot_bin), str(self.image_dir))
+            shutil.move(str(app_bin), str(self.image_dir))
+            logger.info(f"========== {self.soc_name} Image Done ==========")
+        else:
+            logger.error("Failed to generate application binary")
+            sys.exit(1)
+
+    # --- High Level Helpers (Standard Logic) ---
+
+    def standard_process_img2(self, entry_symbol: str) -> Path:
+        """
+        Standard flow for AmebaD/G2:
+        1. Strip AXF -> Extract XIP/SRAM/PSRAM
+        2. Pad all 3 binaries
+        3. Prepend Header (using provided entry_symbol for SRAM)
+        4. Concatenate
+        Returns: Path to the combined image2 binary
+        """
+        td = self.target_dir
+        axf = td / 'target_pure_img2.axf'
+        map_file = td / 'target_img2.map'
+
+        # Output bin names
+        xip_bin = td / 'xip_image2.bin'
+        sram_bin = td / 'sram_2.bin'
+        psram_bin = td / 'psram_2.bin'
+
+        # 1. Initial Copy & Extract
+        shutil.copy(self.zephyr_bin.with_suffix('.elf'), axf)
+        shutil.copy(self.zephyr_bin.with_suffix('.raw.map'), map_file)
+        shutil.copy(self.zephyr_bin, xip_bin)
+
+        self.run_cmd([self.tools.strip, axf])
+        self.run_cmd([self.tools.objcopy, '-j', '.ram_image2.entry', '-Obinary', axf, sram_bin])
+        self.run_cmd([self.tools.objcopy, '-j', '.null.empty', '-Obinary', axf, psram_bin])
+
+        # 2. Pad
+        self.axf2bin_run('pad', '-i', xip_bin, '-l', 32)
+        self.axf2bin_run('pad', '-i', sram_bin, '-l', 32)
+        self.axf2bin_run('pad', '-i', psram_bin, '-l', 32)
+
+        # 3. Prepend Header
+        xip_pre = td / 'xip_image2_prepend.bin'
+        sram_pre = td / 'sram_2_prepend.bin'
+        psram_pre = td / 'psram_2_prepend.bin'
+
+        self.axf2bin_run('prepend_header', '-o', sram_pre, '-i', sram_bin, '-s', entry_symbol, '-m', map_file)
+        self.axf2bin_run('prepend_header', '-o', psram_pre, '-i', psram_bin, '-s', '__rom_start_address', '-m', map_file)
+        self.axf2bin_run('prepend_header', '-o', xip_pre, '-i', xip_bin, '-s', '__rom_start_address', '-m', map_file)
+
+        # 4. Concat
+        # Determine prefix based on internal name for output file
+        prefix = "km4tz" if "amebagreen2" in self.internal_name else "km4"
+        img2_all = td / f'{prefix}_image2_all.bin'
+        self.concat_files([xip_pre, sram_pre, psram_pre], img2_all)
+
+        return img2_all
+
+
+# --- Specific Logic per SoC ---
+
+def handle_amebadplus(p: FirmwarePacker):
+    """
+    Handle AmebaDplus specific logic.
+    Note: Has a separate 'entry.bin' section, so it doesn't use the standard helper.
+    """
+    td = p.target_dir
+    axf = td / 'target_pure_img2.axf'
+    map_file = td / 'target_img2.map'
+
+    # 1. Custom Extract
+    shutil.copy(p.zephyr_bin.with_suffix('.elf'), axf)
+    shutil.copy(p.zephyr_bin.with_suffix('.raw.map'), map_file)
+    xip_bin = td / 'xip_image2.bin'
+    shutil.copy(p.zephyr_bin, xip_bin)
+
+    p.run_cmd([p.tools.strip, axf])
+    # Dplus specific: Extract entry section separately
+    p.run_cmd([p.tools.objcopy, '-j', '.ram_image2.entry', '-Obinary', axf, td / 'entry.bin'])
+    p.run_cmd([p.tools.objcopy, '-j', '.null.empty', '-Obinary', axf, td / 'sram_2.bin'])
+    p.run_cmd([p.tools.objcopy, '-j', '.null.empty', '-Obinary', axf, td / 'psram_2.bin'])
+
+    p.axf2bin_run('pad', '-i', xip_bin, '-l', 32)
+
+    # 2. Header & Concat
+    entry_pre = td / 'entry_prepend.bin'
+    xip_pre = td / 'xip_image2_prepend.bin'
+    sram_pre = td / 'sram_2_prepend.bin'
+    psram_pre = td / 'psram_2_prepend.bin'
+
+    p.axf2bin_run('prepend_header', '-o', entry_pre, '-i', td / 'entry.bin', '-s', '__KM4_IMG2_ENTRY_start', '-m', map_file)
+    p.axf2bin_run('prepend_header', '-o', sram_pre, '-i', td / 'sram_2.bin', '-s', '_image_ram_start', '-m', map_file)
+    p.axf2bin_run('prepend_header', '-o', psram_pre, '-i', td / 'psram_2.bin', '-s', '__rom_start_address', '-m', map_file)
+    p.axf2bin_run('prepend_header', '-o', xip_pre, '-i', xip_bin, '-s', '__rom_start_address', '-m', map_file)
+
+    km4_img2 = td / 'km4_image2_all.bin'
+    p.concat_files([xip_pre, sram_pre, psram_pre, entry_pre], km4_img2)
+
+    # 3. Blobs & Pack
+    km4_boot = td / 'km4_boot_all.bin'
+    p.copy_blob('km4_boot_all.bin', km4_boot)
+
+    km0_blob_name = 'km0_image2_all_coex.bin' if p.args.bt_coexist else 'km0_image2_all.bin'
+    km0_img2 = td / km0_blob_name
+    p.copy_blob(km0_blob_name, km0_img2)
+    km4_img3 = td / 'km4_image3_all.bin'
+    p.copy_blob('km4_image3_all.bin', km4_img3, optional=True)
 
-AXF2BIN_SCRIPT = os.path.join(os.path.dirname(os.path.abspath(__file__)), 'axf2bin.py')
-
-GCC_OBJDUMP = None
-GCC_STRIP = None
-GCC_FROMELF = None
-
-def cmd_exec(cmd, cwd=None, shell=False):
-    return subprocess.check_call(cmd, cwd=cwd, shell=shell)
-
-def axf2bin_pad(input_file, length):
-    cmd = [sys.executable, AXF2BIN_SCRIPT, 'pad', '-i', input_file, '-l', str(length)]
-    cmd_exec(cmd)
-
-def axf2bin_prepend_head(output_file, input_file, symbol, map_file):
-    cmd = [sys.executable, AXF2BIN_SCRIPT, "prepend_header",
-           '-o', output_file,
-           '-i', input_file,
-           '-s', symbol,
-           '-m', map_file]
-    cmd_exec(cmd)
-
-def ameba_axf2bin_fw_pack(target_dir, output_file, *input_files):
-    cmd = [sys.executable, AXF2BIN_SCRIPT, '--post-build-dir', target_dir,
-           'fw_pack', '-o', output_file, *input_files]
-    cmd_exec(cmd)
-
-def concatenate_files(input_files, output_file):
-    with open(output_file, 'wb') as outfile:
-        for file in input_files:
-            with open(file, 'rb') as infile:
-                shutil.copyfileobj(infile, outfile)
-
-def copy_file_if_exists(src, dst):
-    src_path = Path(src)
-    if src_path.exists():
-        shutil.copy(src_path, dst)
-    else:
-        pass
-
-def copy_bin_file(src, dst):
-    src_path = Path(src)
-    if not src_path.is_file():
-        raise FileNotFoundError(f"Source file does not exist: {src_path}, run `west blobs fetch hal_realtek`")
-    shutil.copy(src_path, dst)
-
-def path_leaf(path):
-    p = Path(path)
-    return p.name if p.name else p.parent.name
-
-def get_toolchain_config():
-    global GCC_OBJDUMP, GCC_STRIP, GCC_FROMELF
-
-    variant = os.environ.get("ZEPHYR_TOOLCHAIN_VARIANT")
-    if not variant:
-        sys.exit("Error: ZEPHYR_TOOLCHAIN_VARIANT environment variable is not set")
-
-    if variant == "zephyr":
-        toolchain_prefix = "arm-zephyr-eabi"
-        sdk_dir = os.environ.get("ZEPHYR_SDK_INSTALL_DIR")
-        if not sdk_dir:
-            sys.exit("Error: ZEPHYR_SDK_INSTALL_DIR is not set for 'zephyr' toolchain")
-        toolchain_path = os.path.join(sdk_dir, "arm-zephyr-eabi", "bin")
-
-    elif variant == "gnuarmemb":
-        toolchain_prefix = "arm-none-eabi"
-        gnuarmemb_path = os.environ.get("GNUARMEMB_TOOLCHAIN_PATH")
-        if not gnuarmemb_path:
-            sys.exit("Error: GNUARMEMB_TOOLCHAIN_PATH is not set for 'gnuarmemb' toolchain")
-        toolchain_path = os.path.join(gnuarmemb_path, "bin")
-
-    else:
-        sys.exit(f"Unsupported ZEPHYR_TOOLCHAIN_VARIANT: {variant}")
-
-    GCC_OBJDUMP = os.path.join(toolchain_path, toolchain_prefix + "-objdump")
-    GCC_FROMELF = os.path.join(toolchain_path, toolchain_prefix + "-objcopy")
-    GCC_STRIP = os.path.join(toolchain_path, toolchain_prefix + "-strip")
-
-def if_enable_config(config_file, target_str):
-    with open(config_file, 'r') as infile:
-        for line in infile:
-            if target_str in line:
-                return True
-    return False
-
-def amebadplus_bin_handle(bt_coexist):
-    target_dir = Path(out_dir) / 'amebadplus_gcc_project'
-    target_dir.mkdir(parents=True, exist_ok=True)
-
-    entry_bin = target_dir / 'entry.bin'
-    xip_image2_bin = target_dir / 'xip_image2.bin'
-    sram_2_bin = target_dir / 'sram_2.bin'
-    psram_2_bin = target_dir / 'psram_2.bin'
-
-    target_pure_img2_axf = target_dir / 'target_pure_img2.axf'
-    target_img2_map = target_dir / 'target_img2.map'
-
-    if bt_coexist:
-        km0_image2_all_bin = target_dir / 'km0_image2_all_coex.bin'
-    else:
-        km0_image2_all_bin = target_dir / 'km0_image2_all.bin'
-    km4_image2_all_bin = target_dir / 'km4_image2_all.bin'
-    km4_image3_all_bin = target_dir / 'km4_image3_all.bin'
-
-    km4_boot_all_bin = target_dir / 'km4_boot_all.bin'
-    km0_km4_app_bin = target_dir / 'km0_km4_app.bin'
+    boot_cut = td / 'km4_boot.bin'
+    p.axf2bin_run('cut', '-o', boot_cut, '-i', km4_boot, '-l', 4096)
+    p.axf2bin_run('fw_pack', '-o', km4_boot, '--image1', boot_cut)
 
-    shutil.copy(Path(zephyr_bin).with_suffix('.elf'), target_pure_img2_axf)
-    shutil.copy(Path(zephyr_bin).with_suffix('.raw.map'), target_img2_map)
-    shutil.copy(zephyr_bin, xip_image2_bin)
+    app_bin = td / 'km0_km4_app.bin'
+    pack_args = ['-o', app_bin, '--image2', km0_img2, km4_img2]
+    if km4_img3.exists(): pack_args.extend(['--image3', km4_img3])
 
-    cmd_exec((GCC_STRIP, target_pure_img2_axf))
-    cmd_exec((GCC_FROMELF, '-j', '.ram_image2.entry', '-Obinary', target_pure_img2_axf, entry_bin))
-    cmd_exec((GCC_FROMELF, '-j', '.null.empty', '-Obinary', target_pure_img2_axf, sram_2_bin))
-    cmd_exec((GCC_FROMELF, '-j', '.null.empty', '-Obinary', target_pure_img2_axf, psram_2_bin))
+    p.axf2bin_run('fw_pack', *pack_args)
+    p.finalize_output(km4_boot, app_bin)
 
-    axf2bin_pad(xip_image2_bin, 32)
 
-    entry_prepend_bin = target_dir / 'entry_prepend.bin'
-    xip_image2_prepend_bin = target_dir / 'xip_image2_prepend.bin'
-    sram_2_prepend_bin = target_dir / 'sram_2_prepend.bin'
-    psram_2_prepend_bin = target_dir / 'psram_2_prepend.bin'
+def handle_amebad(p: FirmwarePacker):
+    # 1. Standard Image2 Processing
+    km4_img2 = p.standard_process_img2(entry_symbol='__KM4_IMG2_ENTRY_start')
 
-    axf2bin_prepend_head(entry_prepend_bin, entry_bin, '__KM4_IMG2_ENTRY_start', target_img2_map)
-    axf2bin_prepend_head(sram_2_prepend_bin, sram_2_bin, '_image_ram_start', target_img2_map)
-    axf2bin_prepend_head(psram_2_prepend_bin, psram_2_bin, '__rom_start_address', target_img2_map)
-    axf2bin_prepend_head(xip_image2_prepend_bin, xip_image2_bin, '__rom_start_address', target_img2_map)
+    # 2. Blobs
+    boot_all = p.target_dir / 'bootloader_all.bin'
+    p.copy_blob('bootloader_all.bin', boot_all)
 
-    input_files = [xip_image2_prepend_bin, sram_2_prepend_bin, psram_2_prepend_bin, entry_prepend_bin]
-    concatenate_files(input_files, km4_image2_all_bin)
+    km0_img2 = p.target_dir / 'km0_image2_all.bin'
+    p.copy_blob('km0_image2_all.bin', km0_img2)
 
-    blobs_dir = Path(module_dir) / 'zephyr' / 'blobs' / soc_name / 'bin'
-    copy_bin_file(blobs_dir / path_leaf(km4_boot_all_bin), km4_boot_all_bin)
-    copy_bin_file(blobs_dir / path_leaf(km0_image2_all_bin), km0_image2_all_bin)
-    copy_file_if_exists(blobs_dir / path_leaf(km4_image3_all_bin), km4_image3_all_bin)
-    shutil.copy(os.path.join(module_dir, 'ameba', soc_name, 'manifest.json5'), target_dir)
-    shutil.copy(os.path.join(module_dir, 'ameba', soc_name, 'ameba_layout.ld'), target_dir)
+    km4_img3 = p.target_dir / 'km4_image3_all.bin'
+    p.copy_blob('km4_image3_all.bin', km4_img3, optional=True)
 
-    cmd_exec((sys.executable, AXF2BIN_SCRIPT, 'cut', '-o', target_dir / 'km4_boot.bin', '-i', km4_boot_all_bin, '-l', '4096'))
-    ameba_axf2bin_fw_pack(target_dir.resolve(), km4_boot_all_bin, '--image1', target_dir / 'km4_boot.bin')
+    # 3. Pack
+    app_bin = p.target_dir / 'km0_km4_app.bin'
+    pack_args = ['-o', app_bin, '--image2', km0_img2, km4_img2, '--sboot-for-image', '1']
+    if km4_img3.exists(): pack_args.extend(['--image3', km4_img3])
 
-    if os.path.exists(km4_image3_all_bin):
-        ameba_axf2bin_fw_pack(target_dir.resolve(), km0_km4_app_bin, '--image2', km0_image2_all_bin, km4_image2_all_bin, '--image3', km4_image3_all_bin)
-    else:
-        ameba_axf2bin_fw_pack(target_dir.resolve(), km0_km4_app_bin, '--image2', km0_image2_all_bin, km4_image2_all_bin)
-
-    if os.path.exists(km0_km4_app_bin):
-        shutil.move(km4_boot_all_bin, image_dir)
-        shutil.move(km0_km4_app_bin, image_dir)
-        print('========== Image manipulating done ==========')
-    else:
-        print('Error: Fail to manipulate images')
-        sys.exit(1)
+    p.axf2bin_run('fw_pack', *pack_args)
+    p.finalize_output(boot_all, app_bin)
 
-def amebad_bin_handle():
-    target_dir = Path(out_dir) / 'amebad_gcc_project'
-    target_dir.mkdir(parents=True, exist_ok=True)
 
-    xip_image2_bin = target_dir / 'xip_image2.bin'
-    sram_2_bin = target_dir / 'sram_2.bin'
-    psram_2_bin = target_dir / 'psram_2.bin'
+def handle_amebaG2(p: FirmwarePacker):
+    # 1. Standard Image2 Processing
+    km4tz_img2 = p.standard_process_img2(entry_symbol='__KM4TZ_IMG2_ENTRY_start')
 
-    target_pure_img2_axf = target_dir / 'target_pure_img2.axf'
-    target_img2_map = target_dir / 'target_img2.map'
+    # 2. Blobs
+    boot_bin = p.target_dir / 'amebagreen2_boot.bin'
+    p.copy_blob('amebagreen2_boot.bin', boot_bin)
 
-    km0_image2_all_bin = target_dir / 'km0_image2_all.bin'
-    km4_image2_all_bin = target_dir / 'km4_image2_all.bin'
-    km4_image3_all_bin = target_dir / 'km4_image3_all.bin'
+    km4ns_blob_name = 'km4ns_image2_all_coex.bin' if p.args.bt_coexist else 'km4ns_image2_all.bin'
+    km4ns_img2 = p.target_dir / km4ns_blob_name
+    p.copy_blob(km4ns_blob_name, km4ns_img2)
 
-    bootloader_all_bin = Path(target_dir) / 'bootloader_all.bin'
-    km0_km4_app_bin = target_dir / 'km0_km4_app.bin'
+    km4tz_img3 = p.target_dir / 'km4tz_image3_all.bin'
+    p.copy_blob('km4tz_image3_all.bin', km4tz_img3, optional=True)
 
-    shutil.copy(Path(zephyr_bin).with_suffix('.elf'), target_pure_img2_axf)
-    shutil.copy(Path(zephyr_bin).with_suffix('.raw.map'), target_img2_map)
-    shutil.copy(zephyr_bin, xip_image2_bin)
+    # 3. Pack
+    boot_cut = p.target_dir / 'km4tz_boot.bin'
+    p.axf2bin_run('cut', '-o', boot_cut, '-i', boot_bin, '-l', 4096)
+    p.axf2bin_run('fw_pack', '-o', boot_bin, '--image1', boot_cut)
 
-    cmd_exec((GCC_STRIP, target_pure_img2_axf))
-    cmd_exec((GCC_FROMELF, '-j', '.ram_image2.entry', '-Obinary', target_pure_img2_axf, sram_2_bin))
-    cmd_exec((GCC_FROMELF, '-j', '.null.empty', '-Obinary', target_pure_img2_axf, psram_2_bin))
+    app_bin = p.target_dir / 'amebagreen2_app.bin'
+    pack_args = ['-o', app_bin, '--image2', km4ns_img2, km4tz_img2]
+    if km4tz_img3.exists(): pack_args.extend(['--image3', km4tz_img3])
 
-    axf2bin_pad(xip_image2_bin, 32)
-    axf2bin_pad(sram_2_bin, 32)
-    axf2bin_pad(psram_2_bin, 32)
+    p.axf2bin_run('fw_pack', *pack_args)
+    p.finalize_output(boot_bin, app_bin)
 
-    xip_image2_prepend_bin = target_dir / 'xip_image2_prepend.bin'
-    sram_2_prepend_bin = target_dir / 'sram_2_prepend.bin'
-    psram_2_prepend_bin = target_dir / 'psram_2_prepend.bin'
 
-    axf2bin_prepend_head(sram_2_prepend_bin, sram_2_bin, '__KM4_IMG2_ENTRY_start', target_img2_map)
-    axf2bin_prepend_head(psram_2_prepend_bin, psram_2_bin, '__rom_start_address', target_img2_map)
-    axf2bin_prepend_head(xip_image2_prepend_bin, xip_image2_bin, '__rom_start_address', target_img2_map)
+def handle_amebaG2_mcuboot(p: FirmwarePacker):
+    td = p.target_dir
+    raw_map_file = p.zephyr_bin.parent.parent / 'zephyr' / 'zephyr.raw.map'
 
-    input_files = [xip_image2_prepend_bin, sram_2_prepend_bin, psram_2_prepend_bin]
-    concatenate_files(input_files, km4_image2_all_bin)
+    pad_start = parse_map_file(str(raw_map_file), "__rom_region_start")
+    pad_end = parse_map_file(str(raw_map_file), "__km4tz_boot_text_start__")
 
-    blobs_dir = Path(module_dir) / 'zephyr' / 'blobs' / soc_name / 'bin'
-    copy_bin_file(blobs_dir / path_leaf(bootloader_all_bin), bootloader_all_bin)
-    copy_bin_file(blobs_dir / path_leaf(km0_image2_all_bin), km0_image2_all_bin)
-    copy_file_if_exists(blobs_dir / path_leaf(km4_image3_all_bin), km4_image3_all_bin)
-    shutil.copy(os.path.join(module_dir, 'ameba', soc_name, 'manifest.json5'), target_dir)
-    shutil.copy(os.path.join(module_dir, 'ameba', soc_name, 'ameba_layout.ld'), target_dir)
+    if not pad_start or not pad_end:
+        sys.exit("Error: Symbols missing in map file for MCUBoot")
 
-    if os.path.exists(km4_image3_all_bin):
-        ameba_axf2bin_fw_pack(target_dir.resolve(), km0_km4_app_bin, '--image2', km0_image2_all_bin, km4_image2_all_bin, '--image3', km4_image3_all_bin, '--sboot-for-image', '1')
-    else:
-        ameba_axf2bin_fw_pack(target_dir.resolve(), km0_km4_app_bin, '--image2', km0_image2_all_bin, km4_image2_all_bin, '--sboot-for-image', '1')
+    pad_len = int(pad_end[0], 16) - int(pad_start[0], 16)
+    xip_boot = td / 'xip_boot.bin'
 
-    if os.path.exists(km0_km4_app_bin):
-        shutil.move(bootloader_all_bin, image_dir)
-        shutil.move(km0_km4_app_bin, image_dir)
-        print('========== Image manipulating done ==========')
+    if pad_len > 0:
+        op_cut.execute(p.context, str(p.zephyr_bin), str(xip_boot), pad_len)
     else:
-        print('Error: Fail to manipulate images')
-        sys.exit(1)
+        shutil.copy(p.zephyr_bin, xip_boot)
 
-def amebaG2_bin_handle(bt_coexist):
-    target_dir = Path(out_dir) / 'amebagreen2_gcc_project'
-    target_dir.mkdir(parents=True, exist_ok=True)
+    op_pad.execute(p.context, str(xip_boot), 32)
 
-    xip_image2_bin = target_dir / 'xip_image2.bin'
-    sram_2_bin = target_dir / 'sram_2.bin'
-    psram_2_bin = target_dir / 'psram_2.bin'
+    xip_boot_pre = td / 'xip_boot_prepend.bin'
+    op_prepend_header.execute(p.context, str(xip_boot_pre), str(xip_boot), str(raw_map_file), "__km4tz_boot_text_start__", 0x01010101)
 
-    target_pure_img2_axf = target_dir / 'target_pure_img2.axf'
-    target_img2_map = target_dir / 'target_img2.map'
-
-    if bt_coexist:
-        km4ns_image2_all_bin = target_dir / 'km4ns_image2_all_coex.bin'
-    else:
-        km4ns_image2_all_bin = target_dir / 'km4ns_image2_all.bin'
-    km4tz_image2_all_bin = target_dir / 'km4tz_image2_all.bin'
-    km4tz_image3_all_bin = target_dir / 'km4tz_image3_all.bin'
+    ram_1_pre = td / 'ram_1_prepend.bin'
+    # Create empty file
+    with open(td / 'ram_1.bin', "wb"): pass
+    op_prepend_header.execute(p.context, str(ram_1_pre), str(td / 'ram_1.bin'), str(raw_map_file), "__km4tz_boot_text_start__")
 
-    amebagreen2_boot_bin = target_dir / 'amebagreen2_boot.bin'
-    amebagreen2_app_bin = target_dir / 'amebagreen2_app.bin'
+    km4tz_boot = td / 'km4tz_boot.bin'
+    p.concat_files([xip_boot_pre, ram_1_pre], km4tz_boot)
 
-    shutil.copy(Path(zephyr_bin).with_suffix('.elf'), target_pure_img2_axf)
-    shutil.copy(Path(zephyr_bin).with_suffix('.raw.map'), target_img2_map)
-    shutil.copy(zephyr_bin, xip_image2_bin)
+    final_boot = td / 'amebagreen2_boot.bin'
+    p.axf2bin_run('fw_pack', '-o', final_boot, '--image1', km4tz_boot)
 
-    cmd_exec((GCC_STRIP, target_pure_img2_axf))
-    cmd_exec((GCC_FROMELF, '-j', '.ram_image2.entry', '-Obinary', target_pure_img2_axf, sram_2_bin))
-    cmd_exec((GCC_FROMELF, '-j', '.null.empty', '-Obinary', target_pure_img2_axf, psram_2_bin))
-
-    axf2bin_pad(xip_image2_bin, 32)
-    axf2bin_pad(sram_2_bin, 32)
-    axf2bin_pad(psram_2_bin, 32)
-
-    xip_image2_prepend_bin = target_dir / 'xip_image2_prepend.bin'
-    sram_2_prepend_bin = target_dir / 'sram_2_prepend.bin'
-    psram_2_prepend_bin = target_dir / 'psram_2_prepend.bin'
-
-    axf2bin_prepend_head(sram_2_prepend_bin, sram_2_bin, '__KM4TZ_IMG2_ENTRY_start', target_img2_map)
-    axf2bin_prepend_head(psram_2_prepend_bin, psram_2_bin, '__rom_start_address', target_img2_map)
-    axf2bin_prepend_head(xip_image2_prepend_bin, xip_image2_bin, '__rom_start_address', target_img2_map)
-
-    input_files = [xip_image2_prepend_bin, sram_2_prepend_bin, psram_2_prepend_bin]
-    concatenate_files(input_files, km4tz_image2_all_bin)
-
-    blobs_dir = Path(module_dir) / 'zephyr' / 'blobs' / soc_name / 'bin'
-    copy_bin_file(blobs_dir / path_leaf(amebagreen2_boot_bin), amebagreen2_boot_bin)
-    if if_enable_config(Path(zephyr_bin).parent / ".config", 'CONFIG_AMEBAGREEN2_A_CUT=y'):
-        copy_bin_file(blobs_dir / 'a-cut' / path_leaf(km4ns_image2_all_bin), km4ns_image2_all_bin)
+    if final_boot.exists():
+        shutil.copy(final_boot, p.image_dir)
+        logger.info("========== MCUBoot Image Done ==========")
     else:
-        copy_bin_file(blobs_dir / path_leaf(km4ns_image2_all_bin), km4ns_image2_all_bin)
-
-    copy_file_if_exists(blobs_dir / path_leaf(km4tz_image3_all_bin), km4tz_image3_all_bin)
-    shutil.copy(os.path.join(module_dir, 'ameba', soc_name, 'manifest.json5'), target_dir)
-    shutil.copy(os.path.join(module_dir, 'ameba', soc_name, 'ameba_layout.ld'), target_dir)
-
-    cmd_exec((sys.executable, AXF2BIN_SCRIPT, 'cut', '-o', target_dir / 'km4tz_boot.bin', '-i', amebagreen2_boot_bin, '-l', '4096'))
-    ameba_axf2bin_fw_pack(target_dir.resolve(), amebagreen2_boot_bin, '--image1', target_dir / 'km4tz_boot.bin')
-
-    if os.path.exists(km4tz_image3_all_bin):
-        ameba_axf2bin_fw_pack(target_dir.resolve(), amebagreen2_app_bin, '--image2', km4ns_image2_all_bin, km4tz_image2_all_bin, '--image3', km4tz_image3_all_bin)
-    else:
-        ameba_axf2bin_fw_pack(target_dir.resolve(), amebagreen2_app_bin, '--image2', km4ns_image2_all_bin, km4tz_image2_all_bin)
-
-    if os.path.exists(amebagreen2_app_bin):
-        shutil.move(amebagreen2_boot_bin, image_dir)
-        shutil.move(amebagreen2_app_bin, image_dir)
-        print('========== Image manipulating done ==========')
-    else:
-        print('Error: Fail to manipulate images')
+        logger.error("Failed to generate MCUBoot image")
         sys.exit(1)
 
-if __name__ == "__main__":
+# --- Main ---
+
+def main():
     parser = argparse.ArgumentParser()
-    parser.add_argument("--soc", required=True, help="SoC name (e.g., amebadplus)")
-    parser.add_argument("--bin-file", required=True, help="Path to the kernel binary file")
-    parser.add_argument("--out-dir", required=True, help="Output directory for generated files")
-    parser.add_argument("--module-dir", required=True, help="hal realtek module directory")
-    parser.add_argument("--bt-coexist", action="store_true", help="Enable Bluetooth coexistence features")
+    parser.add_argument("--soc", required=True)
+    parser.add_argument("--bin-file", required=True)
+    parser.add_argument("--out-dir", required=True)
+    parser.add_argument("--module-dir", required=True)
+    parser.add_argument("--bt-coexist", action="store_true")
+    parser.add_argument("--mcuboot", action="store_true")
+    parser.add_argument("--sign-version")
     args = parser.parse_args()
 
-    zephyr_bin = args.bin_file
-    soc_name = args.soc
-    out_dir = args.out_dir
-    module_dir = args.module_dir
-
-    image_dir = Path(out_dir) / 'images'
-    if image_dir.exists():
-        shutil.rmtree(image_dir)
-    image_dir.mkdir(parents=True, exist_ok=True)
-
-    get_toolchain_config()
+    try:
+        # Initialize packer (this will automatically prepare workspace and context)
+        packer = FirmwarePacker(args, args.soc)
+    except Exception:
+        logger.exception("Initialization failed")
+        sys.exit(1)
 
-    if (soc_name == 'amebadplus'):
-        amebadplus_bin_handle(args.bt_coexist)
-    elif (soc_name == 'amebad'):
-        amebad_bin_handle()
-    elif (soc_name == 'amebaG2'):
-        amebaG2_bin_handle(args.bt_coexist)
-    else:
-        print(f"Error: Unsupported SoC name '{soc_name}'")
+    try:
+        if args.mcuboot:
+            if args.soc == "amebag2":
+                handle_amebaG2_mcuboot(packer)
+            else:
+                logger.error(f"MCUBoot not supported for {args.soc}")
+                sys.exit(1)
+        else:
+            if args.soc == "amebadplus":
+                handle_amebadplus(packer)
+            elif args.soc == "amebad":
+                handle_amebad(packer)
+            elif args.soc == "amebag2":
+                handle_amebaG2(packer)
+            else:
+                logger.error(f"Unsupported SoC: {args.soc}")
+                sys.exit(1)
+
+    except Exception:
+        logger.exception("Firmware processing failed")
         sys.exit(1)
+
+if __name__ == "__main__":
+    main()
diff --git a/ameba/scripts/requirements.txt b/ameba/scripts/requirements.txt
new file mode 100644
index 00000000..dbf4dd85
--- /dev/null
+++ b/ameba/scripts/requirements.txt
@@ -0,0 +1,17 @@
+# General cryptographic primitives and key handling
+cryptography
+
+# AES and other symmetric crypto algorithms
+pycryptodome
+
+# DES / 3DES encryption support
+pyDes
+
+# JSON5 configuration / manifest parsing
+json5
+
+# Extra crypto helper library required by Ameba image tools
+sslcrypto
+
+# ECDSA signing / verification helper library
+ecdsa
diff --git a/ameba/scripts/update_blobs.py b/ameba/scripts/update_blobs.py
index a6e030b9..ec6b71d9 100644
--- a/ameba/scripts/update_blobs.py
+++ b/ameba/scripts/update_blobs.py
@@ -4,6 +4,7 @@
 # SPDX-License-Identifier: Apache-2.0
 
 import os
+import re
 import subprocess
 import shutil
 import argparse
@@ -20,41 +21,39 @@
 logger: logging.Logger = logging.getLogger(__name__)
 logging.basicConfig(level=logging.INFO)
 
-socs = ["amebadplus"]
-
-module_yaml = """\
-name: hal_realtek
-build:
-  cmake: .
-  kconfig: Kconfig
-blobs:"""
+# Default SOC list - all supported SOCs (in folder order: amebad, amebadplus, amebag2)
+DEFAULT_SOCS = ["amebad", "amebadplus", "amebag2"]
 
 lib_item = '''
-  - path: {SOC}/lib/{FILENAME}
+  - path: ameba/{SOC}/lib/{RELPATH}
     sha256: {SHA256}
     type: lib
     version: '1.0'
     license-path: LICENSE
-    url: {URL}/raw/{REV}/{SOC}/lib/{FILENAME}
-    description: "Binary libraries supporting the Ameba series RF subsystems"
-    doc-url: {URL_BASE}'''
+    url: {URL}/raw/{REV}/{SOC}/lib/{RELPATH}
+    description: "{DESCRIPTION}"
+    doc-url: {URL_BASE}
+'''
 
 img_item = '''
-  - path: {SOC}/bin/{FILENAME}
+  - path: ameba/{SOC}/bin/{RELPATH}
     sha256: {SHA256}
     type: img
     version: '1.0'
     license-path: LICENSE
-    url: {URL}/raw/{REV}/{SOC}/bin/{FILENAME}
-    description: "Binary libraries supporting the Ameba series RF subsystems"
-    doc-url: {URL_BASE}'''
+    url: {URL}/raw/{REV}/{SOC}/bin/{RELPATH}
+    description: "{DESCRIPTION}"
+    doc-url: {URL_BASE}
+'''
 
 
 def cmd_exec(cmd, cwd=None, shell=False):
+    """Execute a shell command."""
     return subprocess.check_call(cmd, cwd=cwd, shell=shell)
 
 
 def download_repositories(git_rev: str) -> None:
+    """Download and checkout the specified revision of the repository."""
     path = os.path.dirname(os.path.abspath(__file__))
 
     folder = Path(path, "temp")
@@ -67,71 +66,250 @@ def download_repositories(git_rev: str) -> None:
 
 
 def clean_up():
-    print("deleted temporary files..")
+    """Remove temporary files."""
+    print("Deleted temporary files..")
     path = os.path.dirname(os.path.abspath(__file__))
     folder = Path(path, "temp")
     shutil.rmtree(folder)
 
 
 def path_leaf(path):
+    """Extract the filename from a path."""
     p = Path(path)
     return p.name if p.name else p.parent.name
 
 
 def get_file_sha256(path):
+    """Calculate SHA256 hash of a file."""
     with open(path,"rb") as f:
         f_byte = f.read()
         result = hashlib.sha256(f_byte)
         return result.hexdigest()
 
 
-def generate_blob_list(output_path: str, git_rev: str) -> None:
-    file_out = module_yaml
+def get_relative_path(file_path: Path, base_folder: Path) -> str:
+    """Get relative path from base folder.
+
+    Args:
+        file_path: Full path to the file
+        base_folder: Base folder (e.g., lib/ or bin/)
+
+    Returns:
+        Relative path string (e.g., 'coex/lib_wifi.a' or 'lib_wifi.a')
+    """
+    try:
+        return str(file_path.relative_to(base_folder))
+    except ValueError:
+        return file_path.name
+
+
+def get_description(filename: str) -> str:
+    """Generate appropriate description based on filename.
+
+    Args:
+        filename: The name of the binary file
+
+    Returns:
+        Description string for the binary
+    """
+    filename_lower = filename.lower()
+
+    # Check for Wi-Fi related files
+    if 'wifi' in filename_lower or 'wlan' in filename_lower:
+        return "Binary libraries supporting the Ameba series Wi-Fi subsystems"
+
+    # Check for Bluetooth related files
+    if 'bt' in filename_lower or 'bluetooth' in filename_lower or 'ble' in filename_lower:
+        return "Binary libraries supporting the Ameba series Bluetooth subsystems"
+
+    # Check for RF related files
+    if 'rf' in filename_lower or 'radio' in filename_lower:
+        return "Binary libraries supporting the Ameba series RF subsystems"
+
+    # Check for WPA related files
+    if 'wpa' in filename_lower or 'wps' in filename_lower:
+        return "Binary libraries supporting the Ameba series Wi-Fi subsystems"
+
+    # Check for coex related files
+    if 'coex' in filename_lower:
+        return "Binary libraries supporting the Ameba series Wi-Fi subsystems"
+
+    # Check for rtw related files
+    if 'rtw' in filename_lower:
+        return "Binary libraries supporting the Ameba series Wi-Fi subsystems"
+
+    # Check for USB related files
+    if 'usb' in filename_lower:
+        return "Binary libraries supporting the Ameba series USB subsystems"
+
+    # Check for bootloader related files
+    if 'boot' in filename_lower or 'loader' in filename_lower:
+        return "Binary images for the Ameba series bootloader"
+
+    # Check for chipinfo related files
+    if 'chip' in filename_lower:
+        return "Binary libraries supporting the Ameba series chip information"
+
+    # Check for PMC related files
+    if 'pmc' in filename_lower:
+        return "Binary libraries supporting the Ameba series power management"
+
+    # Default description
+    return "Binary libraries supporting the Ameba series subsystems"
+
+
+def sort_socs(socs: list) -> list:
+    """Sort SOC list based on predefined order (DEFAULT_SOCS)."""
+    return sorted(socs, key=lambda x: DEFAULT_SOCS.index(x) if x in DEFAULT_SOCS else 999)
+
+
+def read_existing_module_yml(path: str) -> tuple:
+    """Read existing module.yml and extract header and bee blobs.
+
+    Returns:
+        tuple: (header_content, bee_blobs_content)
+    """
+    with open(path, 'r') as f:
+        content = f.read()
+
+    # Split into header (name, package-managers, build) and blobs section
+    # Find "blobs:" line and keep everything up to and including it
+    lines = content.split('\n')
+    header_lines = []
+    blobs_started = False
+    for line in lines:
+        header_lines.append(line)
+        if line.strip() == 'blobs:':
+            blobs_started = True
+            break
+
+    header = '\n'.join(header_lines)
+
+    # Extract bee bins section (capture from comment line, preserving blank lines before it)
+    bee_match = re.search(r'(\n  # ===== bee bins =====.*)', content, re.DOTALL)
+    bee_blobs = bee_match.group(1) if bee_match else ""
+
+    return header, bee_blobs
+
+
+def generate_blob_list(output_path: str, git_rev: str, socs: list) -> None:
+    """Generate blob list for specified SOCs in module.yml format."""
+    # Read existing module.yml to preserve header and bee blobs
+    header_content, bee_blobs_content = read_existing_module_yml(output_path)
+
+    file_out = header_content + "\n"
 
     path = os.path.dirname(os.path.abspath(__file__))
 
-    for s in socs:
+    # Sort SOC list according to predefined order
+    sorted_socs = sort_socs(socs)
+
+    print("Processing SOCs in order: {}".format(', '.join(sorted_socs)))
+
+    for s in sorted_socs:
         folder = Path(path, "temp", s)
+
+        if not folder.exists():
+            logger.warning("Folder not found: {}, skipping SOC: {}".format(folder, s))
+            continue
+
+        print("\nProcessing SOC: {}".format(s))
+
+        # Process binary files (.bin) first
+        print("  Processing binaries (.bin) for {}...".format(s))
+
+        # Add separator comment for bins (with preceding blank line)
+        file_out += "\n  # ===== {} bins =====\n".format(s)
+
+        # Search recursively in bin/ directory
+        bin_folder = Path(folder, "bin")
         pathlist = []
-        pathlist.extend(Path(folder).glob('**/*.a'))
-        for item in pathlist:
+        if bin_folder.exists():
+            pathlist.extend(bin_folder.glob('**/*.bin'))
+        else:
+            logger.warning("Binary folder not found: {}".format(bin_folder))
+
+        # Remove duplicates by relative path (keep files in different subdirs)
+        seen_paths = set()
+        unique_pathlist = []
+        for item in sorted(pathlist, key=lambda x: str(x)):
+            rel_path = get_relative_path(item, bin_folder)
+
+            if rel_path not in seen_paths:
+                seen_paths.add(rel_path)
+                unique_pathlist.append(item)
+                logger.debug("Added: {} -> {}".format(rel_path, item))
+            else:
+                # This should rarely happen (exact duplicate path)
+                logger.warning("Skipping exact duplicate path: {}".format(item))
+
+        for item in unique_pathlist:
             logger.debug(item)
             path_in_str = str(item)
+            rel_path = get_relative_path(item, bin_folder)
             filename = path_leaf(path_in_str)
             sha256 = get_file_sha256(path_in_str)
-            file_out += lib_item.format(SOC=s,
-                                         FILENAME=filename,
+            description = get_description(filename)
+            file_out += img_item.format(SOC=s,
+                                         RELPATH=rel_path,
                                          SHA256=sha256,
                                          URL=git_url,
                                          REV=git_rev,
-                                         URL_BASE=git_url)
+                                         URL_BASE=git_url,
+                                         DESCRIPTION=description)
+
+        # Process library files (.a) second
+        print("  Processing libraries (.a) for {}...".format(s))
 
+        # Add separator comment for libs (with preceding blank line)
+        file_out += "\n  # ===== {} libs =====\n".format(s)
+
+        # Search recursively in lib/ directory (to include coex subfolder)
+        lib_folder = Path(folder, "lib")
         pathlist = []
-        pathlist.extend(Path(folder).glob('**/*.bin'))
-        for item in pathlist:
+        if lib_folder.exists():
+            pathlist.extend(lib_folder.glob('**/*.a'))
+        else:
+            logger.warning("Library folder not found: {}".format(lib_folder))
+
+        # Remove duplicates by relative path (keep files in different subdirs)
+        seen_paths = set()
+        unique_pathlist = []
+        for item in sorted(pathlist, key=lambda x: str(x)):
+            rel_path = get_relative_path(item, lib_folder)
+
+            if rel_path not in seen_paths:
+                seen_paths.add(rel_path)
+                unique_pathlist.append(item)
+                logger.debug("Added: {} -> {}".format(rel_path, item))
+            else:
+                # This should rarely happen (exact duplicate path)
+                logger.warning("Skipping exact duplicate path: {}".format(item))
+
+        for item in unique_pathlist:
             logger.debug(item)
             path_in_str = str(item)
+            rel_path = get_relative_path(item, lib_folder)
             filename = path_leaf(path_in_str)
             sha256 = get_file_sha256(path_in_str)
-            file_out += img_item.format(SOC=s,
-                                         FILENAME=filename,
+            description = get_description(filename)
+            file_out += lib_item.format(SOC=s,
+                                         RELPATH=rel_path,
                                          SHA256=sha256,
                                          URL=git_url,
                                          REV=git_rev,
-                                         URL_BASE=git_url)
-
-    file_out += "\r\n"
+                                         URL_BASE=git_url,
+                                         DESCRIPTION=description)
 
-    try:
-        os.remove(output_path)
-    except OSError:
-        pass
+    # Add bee blobs section if exists (preserve original indentation)
+    if bee_blobs_content:
+        file_out += bee_blobs_content
 
-    with open(output_path, "w+") as f:
+    with open(output_path, "w") as f:
         f.write(file_out)
-        f.close()
 
-    print("module.yml updated!")
+    print("\nmodule.yml updated successfully!")
+
 
 def main() -> None:
     parser: argparse.ArgumentParser = argparse.ArgumentParser(
@@ -149,6 +327,12 @@ def main() -> None:
         required=True,
         help="The latest commit SHA for the nuwa_lib repository.",
     )
+    parser.add_argument(
+        "-s",
+        "--socs",
+        default=",".join(DEFAULT_SOCS),
+        help="Comma-separated list of SOCs to process (e.g., 'amebad,amebadplus,amebag2'). Default: all SOCs ({})".format(','.join(DEFAULT_SOCS)),
+    )
     parser.add_argument(
         "-d", "--debug", action="store_true", help="Enable debug logging."
     )
@@ -158,8 +342,17 @@ def main() -> None:
     if args.debug:
         logger.setLevel(logging.DEBUG)
 
+    # Parse SOC list from comma-separated string
+    socs = [s.strip() for s in args.socs.split(",") if s.strip()]
+
+    if not socs:
+        logger.error("No valid SOCs specified!")
+        return
+
+    print("Target SOCs: {}".format(', '.join(socs)))
+
     download_repositories(args.commit)
-    generate_blob_list(args.output, args.commit)
+    generate_blob_list(args.output, args.commit, socs)
     clean_up()
 
 if __name__ == '__main__':
diff --git a/ameba/usrcfg/amebad/include/ameba_usrcfg.h b/ameba/usrcfg/amebad/include/ameba_usrcfg.h
index d9753b2d..317b61d4 100644
--- a/ameba/usrcfg/amebad/include/ameba_usrcfg.h
+++ b/ameba/usrcfg/amebad/include/ameba_usrcfg.h
@@ -17,4 +17,6 @@
 // #include "ameba_sleepcfg.h"
 
 
+/* wifi configuration*/
+#include "ameba_wificfg_common.h"
 #endif /* _AMEBA_USRCFG_H_ */
diff --git a/ameba/usrcfg/amebag2/CMakeLists.txt b/ameba/usrcfg/amebag2/CMakeLists.txt
new file mode 100644
index 00000000..4a9540b9
--- /dev/null
+++ b/ameba/usrcfg/amebag2/CMakeLists.txt
@@ -0,0 +1,4 @@
+# Copyright (c) 2024 Realtek Semiconductor Corp.
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_include_directories(include)
diff --git a/ameba/usrcfg/amebaG2/include/ameba_audio_hw_usrcfg.h b/ameba/usrcfg/amebag2/include/ameba_audio_hw_usrcfg.h
similarity index 100%
rename from ameba/usrcfg/amebaG2/include/ameba_audio_hw_usrcfg.h
rename to ameba/usrcfg/amebag2/include/ameba_audio_hw_usrcfg.h
diff --git a/ameba/usrcfg/amebaG2/include/ameba_boot_trustzonecfg.h b/ameba/usrcfg/amebag2/include/ameba_boot_trustzonecfg.h
similarity index 100%
rename from ameba/usrcfg/amebaG2/include/ameba_boot_trustzonecfg.h
rename to ameba/usrcfg/amebag2/include/ameba_boot_trustzonecfg.h
diff --git a/ameba/usrcfg/amebaG2/include/ameba_bootcfg.h b/ameba/usrcfg/amebag2/include/ameba_bootcfg.h
similarity index 100%
rename from ameba/usrcfg/amebaG2/include/ameba_bootcfg.h
rename to ameba/usrcfg/amebag2/include/ameba_bootcfg.h
diff --git a/ameba/usrcfg/amebaG2/include/ameba_flashcfg.h b/ameba/usrcfg/amebag2/include/ameba_flashcfg.h
similarity index 100%
rename from ameba/usrcfg/amebaG2/include/ameba_flashcfg.h
rename to ameba/usrcfg/amebag2/include/ameba_flashcfg.h
diff --git a/ameba/usrcfg/amebaG2/include/ameba_intfcfg.h b/ameba/usrcfg/amebag2/include/ameba_intfcfg.h
similarity index 100%
rename from ameba/usrcfg/amebaG2/include/ameba_intfcfg.h
rename to ameba/usrcfg/amebag2/include/ameba_intfcfg.h
diff --git a/ameba/usrcfg/amebaG2/include/ameba_pinmapcfg.h b/ameba/usrcfg/amebag2/include/ameba_pinmapcfg.h
similarity index 100%
rename from ameba/usrcfg/amebaG2/include/ameba_pinmapcfg.h
rename to ameba/usrcfg/amebag2/include/ameba_pinmapcfg.h
diff --git a/ameba/usrcfg/amebaG2/include/ameba_sleepcfg.h b/ameba/usrcfg/amebag2/include/ameba_sleepcfg.h
similarity index 100%
rename from ameba/usrcfg/amebaG2/include/ameba_sleepcfg.h
rename to ameba/usrcfg/amebag2/include/ameba_sleepcfg.h
diff --git a/ameba/usrcfg/amebaG2/include/ameba_userheapcfg.h b/ameba/usrcfg/amebag2/include/ameba_userheapcfg.h
similarity index 100%
rename from ameba/usrcfg/amebaG2/include/ameba_userheapcfg.h
rename to ameba/usrcfg/amebag2/include/ameba_userheapcfg.h
diff --git a/ameba/usrcfg/amebaG2/include/ameba_usrcfg.h b/ameba/usrcfg/amebag2/include/ameba_usrcfg.h
similarity index 85%
rename from ameba/usrcfg/amebaG2/include/ameba_usrcfg.h
rename to ameba/usrcfg/amebag2/include/ameba_usrcfg.h
index bf540ee1..bdd071df 100644
--- a/ameba/usrcfg/amebaG2/include/ameba_usrcfg.h
+++ b/ameba/usrcfg/amebag2/include/ameba_usrcfg.h
@@ -18,5 +18,7 @@
 #include "ameba_intfcfg.h"
 
 /* wifi configuration*/
-// #include "ameba_wificfg_common.h"
-#endif /* _AMEBA_USRCFG_H_ */
+#include "ameba_wificfg_common.h"
+
+#endif
+
diff --git a/ameba/usrcfg/common/ameba_wificfg_common.h b/ameba/usrcfg/common/ameba_wificfg_common.h
new file mode 100644
index 00000000..81f28381
--- /dev/null
+++ b/ameba/usrcfg/common/ameba_wificfg_common.h
@@ -0,0 +1,280 @@
+/*
+ * Copyright (c) 2024 Realtek Semiconductor Corp.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _AMEBA_WIFICFG_COMMON_H_
+#define _AMEBA_WIFICFG_COMMON_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @addtogroup WIFI_API Wi-Fi APIs
+ *  @brief      WIFI_API module
+ *  @{
+ */
+/** @addtogroup WIFI_Exported_Types Wi-Fi Exported Types
+* @{
+*/
+/** @addtogroup WIFI_Exported_Structure_Types Structure Type
+ * @{
+ */
+/**
+  * @brief  The structure is used to describe the wifi user configuration, can be configured in ameba_wificfg.c.
+  */
+struct wifi_user_conf {
+	/*!	This effects EDCCA threshold, wifi won't TX if detected energy exceeds threshold.
+		- \b RTW_EDCCA_NORM: Adjust EDCCA threshold dynamically;
+		- \b RTW_EDCCA_ADAPT: For ESTI or SRRC;
+		- \b RTW_EDCCA_CS: For japan;
+		- \b RTW_EDCCA_DISABLE: Ingore EDCCA. */
+	u8 rtw_edcca_mode;
+
+	/*! For power by rate and power by limit table selection, refer to Ameba Wi-Fi TX Power and Country Code Setup Guideline.pdf.
+		- 0: Disable power by limit, enable power by rate;
+		- 1: Enable both power by limit and power by rate;
+		- 2: Depend on efuse (flash). */
+	u8 tx_pwr_table_selection;
+
+	/*!	Enabled during TRP TIS certification. */
+	u8 rtw_trp_tis_cert_en;
+
+	/*!	Force wpa mode:
+		- \b RTW_WPA_AUTO_MODE: Auto mode, follow AP;
+		- \b RTW_WPA_ONLY_MODE: Wpa only;
+		- \b RTW_WPA2_ONLY_MODE: Wpa2 only;
+		- \b RTW_WPA3_ONLY_MODE: Wpa3 only;
+		- \b RTW_WPA_WPA2_MIXED_MODE: Wpa and wpa2 mixed;
+		- \b RTW_WPA2_WPA3_MIXED_MODE: Wpa2 and wpa3 mixed.*/
+	u8 wifi_wpa_mode_force;
+
+	/*!	TDMA DIG affects the range of RX, when enabled, both near and distant devices can be received.\n
+		0: TDMA DIG off, 1: TDMA DIG on. */
+	u8 tdma_dig_enable;
+
+	/*!	Antdiv mode:
+		- \b RTW_ANTDIV_AUTO: Auto antdiv;
+		- \b RTW_ANTDIV_FIX_MAIN: Fix main ant;
+		- \b RTW_ANTDIV_FIX_AUX: Fix aux ant;
+		- \b RTW_ANTDIV_DISABLE: Antdiv disable. */
+	u8 antdiv_mode;
+
+	/*!	The maximum number of STAs connected to the softap should not exceed the num specified in notes of func wifi_set_user_config(). */
+	u8 ap_sta_num;
+
+	/*!	IPS(Inactive power save), If disconnected for more than 2 seconds, WIFI will be powered off. */
+	u8 ips_enable;
+
+	/*!	Power save status:
+		- \b RTW_IPS_WIFI_OFF: The WIFI is powered off during the IPS;
+		- \b RTW_IPS_WIFI_PG: The WIFI enters the PG state during the IPS, and therefore it exits the IPS faster. Only dplus support this status. */
+	u8 ips_level;
+
+	/*!	The driver does not enter the IPS due to 2s disconnection. Instead, API wifi_set_ips_internal() controls the IPS.\n
+		0: API wifi_set_ips_internal() control ips enable/disable, 1: Control ips enter/leave. */
+	u8 ips_ctrl_by_usr;
+
+	/*!	LPS(Legacy power save). After connection, with low traffic, part of WIFI can be powered off and woken up upon packet interaction.\n
+		There are two power save modes: legacy power save and uapsd mode. Can only enable one of them.\n
+		0: Disable legacy power save, 1: Enable. */
+	u8 lps_enable;
+
+	/*!	In LPS, the sta wakes up every lps_listen_interval * 102.4ms to receive beacon.*/
+	u8 lps_listen_interval;
+
+	/*! Enable or disable rx broadcast in tickless wowlan mode,
+		1 means disable rx broadcast in tickless wowlan mode, 0 means enable(default) rx broadcast in tickless wowlan mode.*/
+	u8 wowlan_rx_bcmc_dis;
+
+	/*!	U-APSD WMM power save mode. After connection, with low traffic, part of WIFI can be powered off and woken up upon packet interaction.\n
+		There are two power save modes: legacy power save and uapsd mode. Can only enable one of them.
+		0: Disable uapsd mode, 1: Enable. */
+	u8 uapsd_enable;
+
+	/*!	0: RTW_UAPSD_NO_LIMIT, 1: RTW_UAPSD_TWO_MSDU, 2: RTW_UAPSD_FOUR_MSDU, 3: RTW_UAPSD_SIX_MSDU. */
+	u8 uapsd_max_sp_len;
+
+	/*!	BIT0: AC_VO UAPSD, BIT1: AC_VI UAPSD, BIT2: AC_BK UAPSD, BIT3: AC_BE UAPSD. */
+	u8 uapsd_ac_enable;
+
+	/*!	0: Disable ampdu rx, 1: Enable ampdu rx. */
+	u8 ampdu_rx_enable;
+
+	/*!	0: Disable ampdu tx, 1: Enable ampdu tx. */
+	u8 ampdu_tx_enable;
+
+	/*!	0: If the pkt's destination address doesn't match, it won't be dropped, 1: If the pkt's destination address doesn't match, it will be dropped. */
+	u8 check_dest_address_en;
+
+	/*!	The ap_compatibilty_enabled is used to configure the wlan settings, each bit controls one aspect.
+		- <b>bit 0:</b> 0: follow 802.11 spec, do not issue deauth, 1(default): issue deauth in 1st REAUTH_TO to be compatible with ap;
+		- <b>bit 1:</b> 0: do not check beacon info to connect with AP with multiple SSID, 1(default): check beacon info;
+		- <b>bit 2:</b> 0(default): do not issue deauth at start of auth, 1: issue deauth at start of auth;
+		- <b>bit 3:</b> 0: do not switch WEP auth algo unless WLAN_STATUS_NOT_SUPPORTED_AUTH_ALG, 1(default): switch WEP auth algo from shared key to open system in 1st REAUTH_TO;
+		- <b>other bits:</b> reserved */
+	u8 ap_compatibilty_enabled;
+
+	/*!	0: API wifi_set_channel() does not trigger RFK;
+		1: API wifi_set_channel() triggers RFK. */
+	u8 set_channel_api_do_rfk;
+
+	/*!	0: Do not limit the peak current of DPD;
+		1: Limit the peak current of DPD. */
+	u8 dpk_peak_limit;
+
+	/*!	RF calibration is triggered during WIFI initialization and channel switch to calibrate TRX to optimal performance,\n
+		but it takes a long time (around 100ms), so some applications can sacrifice performance so that WIFI initializes and switches faster.\n
+		- \b Bit0: RTW_RFK_DIS_DPK;
+		- <b>Other bits:</b> reserved.*/
+	u16 rf_calibration_disable;
+
+	/*! The maximum number of roaming attempts triggered by BTM.*/
+	u8 max_roaming_times;
+
+	/*!	AP periodically sends null pkt to check whether the STA is offline, not support right now.*/
+	u8 ap_polling_sta;
+
+	/*!	Refer to ameba_wifi_country_code_table_usrcfg.c, e.g. China: country_code[0] = 'C', country_code[1] = 'N'.\n
+		Specical value: country_code[0]~[1] = 0x0000: follow efuse; country_code[0]='0', country_code[1]='0' : WORLDWIDE. */
+	u8 country_code[2];
+
+	/*!	Bandwidth 40MHz, some IC hardware does not support.*/
+	u8 bw_40_enable;
+
+	/*!	Support frequency band types, some IC hardware does not support 5 GHz.
+		- @ref RTW_SUPPORT_BAND_2_4G : Only support 2.4 GHz band;
+		- @ref RTW_SUPPORT_BAND_5G : Only support 5 GHz band
+		- @ref RTW_SUPPORT_BAND_2_4G_5G_BOTH : Support both 2.4 GHz and 5 GHz bands;
+		- @ref RTW_SUPPORT_BAND_MAX : Default types supported by IC hardware. */
+	u8 freq_band_support;
+
+	/*!	Refe to 802.11d spec, obtain the country code information from beacon, and set the pwr limit and channel plan.*/
+	u8 rtw_802_11d_en;
+
+	/*!	When booting the STA, it automatically reconnects to previously connected AP*/
+	u8 fast_reconnect_en;
+
+	/*!	When disconnection, STA automatically reconnects.*/
+	u8 auto_reconnect_en;
+
+	/*!	When disconnection, STA automatically reconnects, and auto_reconnect_count is the number of attempts.
+		Specical value: 0xff means infinite retry count*/
+	u8 auto_reconnect_count;
+
+	/*!	auto_reconnect_interval is Automatic reconnection interval, unit s.*/
+	u8 auto_reconnect_interval;
+
+	/*!	no_beacon_disconnect_time is the disconnect time when no beacon occurs, unit 2s.*/
+	u8 no_beacon_disconnect_time;
+
+	/*!	skb_num_np is wifi driver's trx buffer number, each buffer occupies about 1.8K bytes of heap, a little difference between different chips.\n
+		These buffer are used for all traffics except tx data in INIC mode, and all traffics in single core mode.\n
+		For higher throughput or a large number of STAs connected to softap, skb_num_np can be increased.\n
+		Minimum: 7 (3 for Ameba lite). Default: 10.*/
+	s32 skb_num_np;
+
+	/*!	These buffer are used for tx data packtes in INIC mode, not used in single core mode.\n
+		For higher throughput or a large number of STAs connected to softap, skb_num_ap can be increased. */
+	s32 skb_num_ap;
+
+	/*!	Specify the trx buffer size of each skb.\n
+		Cache size(32 for amebadplus&amebalite and 64 for amebasmart)alignment will be applied to the input size.\n
+		Considering the length field of L-SIG is 12 bits, the max PSDU size is 4095 bytes, so skb_buf_size is suggested not exceed 4k.\n
+		ps1:.If the trx buffer is specified through skb_buf_size, the actual rx_pkt_size <= skb_buf_size - WLAN_HW_INFO_LEN.\n
+		ps2:.If the skb_buf_size is a larger value, it is necessary to consider whether the heap of cores is sufficient?(amebaxxx_layout.ld may need to be modified).\n
+		0: use default size. */
+	u32 skb_buf_size;
+
+	/*!	Every data tx is forced to start with cts2self. */
+	u8 force_cts2self;
+
+	/*!	Multi Channel Concurrent mode, STA and Softap can work on different channels via TDMA.
+		@note Mcc performance has limitations, please contact Realtek before use to clarify your requirements. */
+	u8 en_mcc;
+
+	/*!	Used for configuring mcc port1 slot ratio by user: optional values:[12,80] */
+	unsigned char mcc_force_p1_slot_ratio;
+
+	/*!	Simplify transmit pathway for faster data frame handling. */
+	u8 tx_shortcut_enable;
+
+	/*!	Simplify receive pathway for faster data frame handling. */
+	u8 rx_shortcut_enable;
+
+	/*!	0: No probe request will be sent on passive channel;
+		1: A unicast probe request will be sent when a null-SSID beacon is received on passive channel to obtain the ssid of the AP */
+	u8 probe_hidden_ap_on_passive_ch;
+
+	/*! For concurrent mode:
+	    - \b 0: STA or SoftAP only at any time, The MAC address of TA or Softap is the MAC address of chip;
+		- \b 1: STA and SoftAP may run at the same time, Softap's mac address depends on softap_addr_offset_idx. */
+	u8 concurrent_enabled;
+
+	/*!	It is valid only when concurrent_enabled =1. The range is 0~5.The lowest bit of mac[0] is 1, which represents the multicast address,
+		therefore, the mac[0] of softap is incremented by 2, others is incremented by 1.
+		- e.g. softap_addr_offset_idx = 0, chip's mac = 00:e0:4c:01:02:03, softap's mac = 02:e0:4c:01:02:03;
+		- e.g. softap_addr_offset_idx = 1, chip's mac = 00:e0:4c:01:02:03, softap's mac = 00:e1:4c:01:02:03;
+		- e.g. softap_addr_offset_idx = 5, chip's mac = 00:e0:4c:01:02:03, softap's mac = 00:e0:4c:01:02:04.*/
+	u8 softap_addr_offset_idx;
+
+	/*!	The number of ampdu that Recipient claims to Originator for RX, it can be any value less than 64.\n
+		skb_num_np needs to be adjusted simultaneously.*/
+	u8 rx_ampdu_num;
+
+	/*!	Linux Fullmac architecture, ignore in RTOS.*/
+	u8 cfg80211;
+
+	/*!	WPS. */
+	u8 wps_retry_count;
+
+	/*!	Unit: ms. */
+	u32 wps_retry_interval;
+
+	/*!	For wifi speaker configuration.\n
+		BIT0: Main switch, BIT1: Enable tsf interrupt, BIT2: Enable audio tsf. */
+	u8 wifi_speaker_feature;
+
+	/*! STA mode will periodically send null packet to AP to keepalive, unit: second. */
+	u8 keepalive_interval;
+
+	/*! 0: Disable R-mesh function, 1: Enable R-mesh function.*/
+	u8 wtn_en;
+
+	/*! R-mesh AP strong RSSI thresh, when AP rssi larger than this thresh, will try to switch to AP.*/
+	s8 wtn_strong_rssi_thresh;
+
+	/*! R-mesh father refresh timeout, when not receive beacon from father for this timeout, will switch to other node, unit: millisecond.*/
+	u16 wtn_father_refresh_timeout;
+
+	/*! R-mesh child refresh timeout, when not receive beacon from child for this timeout, will delete this child, unit: millisecond.*/
+	u16 wtn_child_refresh_timeout;
+
+	/*! 0: Disable R-mesh NAT feature, 1: Enable R-mesh NAT feature.*/
+	u8 wtn_rnat_en;
+
+	/*! 0: Determine whether to become RNAT node based on the rssi to AP, 1: Become RNAT node regardless of the rssi to AP.*/
+	u8 wtn_fixed_rnat_node;
+
+	/*! 0: This device can connect to R-Mesh group or R-NAT group, 1: this device will only connect to R-NAT group.*/
+	u8 wtn_connect_only_to_rnat;
+
+	/*! Max node number in R-mesh network, this is used for decide each node's beacon window.*/
+	u16 wtn_max_node_num;
+};
+
+/** @} End of WIFI_Exported_Structure_Types group*/
+/** @} End of WIFI_Exported_Types group*/
+/** @} End of WIFI_API group */
+
+extern struct wifi_user_conf wifi_user_config __attribute__((aligned(64)));
+
+void wifi_set_user_config(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
diff --git a/bee/CMakeLists.txt b/bee/CMakeLists.txt
new file mode 100644
index 00000000..61ad01cd
--- /dev/null
+++ b/bee/CMakeLists.txt
@@ -0,0 +1,11 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+add_subdirectory(boot)
+add_subdirectory(drivers)
+add_subdirectory(ld)
+add_subdirectory(logging)
+add_subdirectory(memory)
+add_subdirectory(soc)
+add_subdirectory(sys)
+add_subdirectory(util)
diff --git a/bee/Kconfig b/bee/Kconfig
new file mode 100644
index 00000000..d6fd2ab4
--- /dev/null
+++ b/bee/Kconfig
@@ -0,0 +1,4 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+rsource "drivers/Kconfig"
diff --git a/bee/boot/CMakeLists.txt b/bee/boot/CMakeLists.txt
new file mode 100644
index 00000000..101c1fb5
--- /dev/null
+++ b/bee/boot/CMakeLists.txt
@@ -0,0 +1,8 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_include_directories_ifdef(CONFIG_SOC_SERIES_RTL87X2G inc/rtl87x2g)
+zephyr_include_directories_ifdef(CONFIG_SOC_SERIES_RTL87X2J inc/rtl87x2j)
+zephyr_include_directories_ifdef(CONFIG_SOC_SERIES_RTL8752H inc/rtl8752h)
+
+add_subdirectory_ifdef(CONFIG_SOC_SERIES_RTL8752H src/rtl8752h)
diff --git a/bee/boot/inc/rtl8752h/image_check.h b/bee/boot/inc/rtl8752h/image_check.h
new file mode 100644
index 00000000..05e36fd6
--- /dev/null
+++ b/bee/boot/inc/rtl8752h/image_check.h
@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _IMAGE_CHECK_H_
+#define _IMAGE_CHECK_H_
+
+#include <stdbool.h>
+#include <stdint.h>
+#include <image_header.h>
+
+/*============================================================================*
+  *                                   Types
+  *============================================================================*/
+
+typedef enum
+{
+    IMG_CHECK_PASS,
+    IMG_CHECK_ERR_HEADER_ADDR,
+    IMG_CHECK_ERR_NOT_READY,
+    IMG_CHECK_ERR_ROM_UUID,
+    IMG_CHECK_ERR_MAGIC_PATTERN,
+    IMG_CHECK_ERR_SIZE,
+    IMG_CHECK_ERR_ID,
+    IMG_CHECK_ERR_ENTRY_RETURN,
+    IMG_CHECK_ERR_VERIFY,
+    IMG_CHECK_ERR_EXE_BASE,
+    IMG_CHECK_ERR_IC_TYPE,
+    IMG_CHECK_ERR_MAX,
+} IMG_CHECK_ERR_TYPE;
+
+/*============================================================================*
+  *                                   Functions
+ *============================================================================*/
+
+/**
+ * @brief  Check the validity of the specified image
+ *
+ * @param[in]  image_id Specify the image
+ * @param[in]  header_addr Specify image header address
+ *
+ * @return Check result
+ * @retval IMG_CHECK_PASS If image check passes
+ * @retval fail Otherwise
+*/
+extern IMG_CHECK_ERR_TYPE check_header_valid(uint32_t header_addr, T_IMG_ID image_id);
+
+extern IMG_CHECK_ERR_TYPE image_entry_check(T_ROM_HEADER_FORMAT *rom_header,
+                                            T_ROM_HEADER_FORMAT *patch_header);
+
+#endif /* _IMAGE_CHECK_H_ */
diff --git a/bee/boot/inc/rtl8752h/image_header.h b/bee/boot/inc/rtl8752h/image_header.h
new file mode 100644
index 00000000..19dcb3da
--- /dev/null
+++ b/bee/boot/inc/rtl8752h/image_header.h
@@ -0,0 +1,272 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _IMAGE_HEADER_H_
+#define _IMAGE_HEADER_H_
+
+#include <stdbool.h>
+#include <stdint.h>
+
+/*============================================================================*
+  *                                   Constants
+  *============================================================================*/
+#define DEFAULT_HEADER_SIZE           (0x400)
+#define CMAC_BYTE_SIZE                (16)
+#define RSA_2048_PUBLIC_KEY_BYTE_SIZE (256)
+#define RSA_2048_SIGNATURE_BYTE_SIZE  (RSA_2048_PUBLIC_KEY_BYTE_SIZE)
+#define RSA_3072_PUBLIC_KEY_BYTE_SIZE (384)
+#define RSA_3072_SIGNATURE_BYTE_SIZE  (RSA_3072_PUBLIC_KEY_BYTE_SIZE)
+#define SHA256_BYTE_SIZE              (32)
+#define SIGNATURE_APP_CB              0x0e85d101 /**< patch callback app signature definition*/
+#define UUID_SIZE                     16
+
+#define IMG_IC_TYPE          0x10
+
+#define DFU_HEADER_SIZE          12  /*currently, first 12 byte only will be treated as image header*/
+#define IMG_HEADER_SIZE          1024
+#define OTA_HEADER_SIZE          (4 * 1024)
+#define DECODE_OFFSET            (sizeof(T_COMPRESS_IMG_HEADER_FORMAT))
+
+#define FSBL_EXT_PATTERN         0x736c
+
+#define UP_ALIGN(size, align)    (((size) + (align) - 1) & ~(align - 1))
+
+#define SYS_CFG_SIGNATURE           0x12345bb3
+#define FLASH_TABLE_MAGIC_PATTERN   (0x5A5A12A5)
+
+/*============================================================================*
+  *                                   Types
+  *============================================================================*/
+
+typedef enum
+{
+    IMAGE_FIRST = 0x278D,
+    SCCD        = 0x278D,
+    OCCD        = 0x278E,
+    FactoryCode = 0x278F,
+    OTA         = 0x2790, /**< OTA header */
+    SecureBoot  = 0x2791,
+    RomPatch    = 0x2792,
+    AppPatch    = 0x2793,
+    AppData1    = 0x2794,
+    AppData2    = 0x2795,
+    AppData3    = 0x2796,
+    AppData4    = 0x2797,
+    AppData5    = 0x2798,
+    AppConfigFile = 0x2799,
+    UpperStack  = 0x279a,
+    IMG_BT_STACKPATCH = 0x279b,
+    IMAGE_MAX,
+
+    IMAGE_USER_DATA2 = 0xFFFD,  /**< the image only supports unsafe single bank OTA */
+    IMAGE_USER_DATA = 0xFFFE,  /**< the image only supports unsafe single bank OTA */
+} T_IMG_ID;
+
+typedef enum
+{
+    ENC_KEY_SCEK = 0,
+    ENC_KEY_SCEK_WITH_RTKCONST,
+    ENC_KEY_OCEK,
+    ENC_KEY_OCEK_WITH_OEMCONST,
+    ENC_KEY_ON_FLASH,
+    ENC_KEY_MAX,
+} T_ENC_KEY_SELECT;
+
+typedef struct
+{
+    union
+    {
+        struct
+        {
+            uint8_t N[RSA_2048_PUBLIC_KEY_BYTE_SIZE];
+            uint8_t E[4];
+        } rsa_2048_pub_key;
+
+        struct
+        {
+            uint8_t N[RSA_3072_PUBLIC_KEY_BYTE_SIZE];
+            uint8_t E[4];
+        } rsa_3072_pub_key;
+    };
+
+} T_RSA_PUBLIC_KEY;
+
+typedef enum _APP_IMAGE_TYPE
+{
+    IMAGE_NORMAL              = 0,
+    IMAGE_COMPRESSED          = 1,
+    //2-7 are reserved
+} T_IMAGE_TYPE;
+
+typedef struct _IMG_CTRL_HEADER_FORMAT
+{
+    uint16_t crc16;
+    uint8_t ic_type;
+    uint8_t secure_version;
+    union
+    {
+        uint16_t value;
+        struct
+        {
+            uint16_t xip: 1; // payload is executed on flash
+            uint16_t enc: 1; // all the payload is encrypted
+            uint16_t load_when_boot: 1; // load image when boot
+            uint16_t enc_load: 1; // encrypt load part or not
+            uint16_t enc_key_select: 3; // referenced to ENC_KEY_SELECT
+            uint16_t not_ready: 1; // for copy image in OTA
+            uint16_t not_obsolete: 1; // for copy image in OTA
+            uint16_t integrity_check_en_in_boot: 1; // enable image integrity check in boot flow
+            uint16_t compressed_not_ready: 1;
+            uint16_t compressed_not_obsolete: 1;
+            uint16_t rsvd: 1;
+            uint16_t image_type: 3; /* for app 000b: normal image, 001b:compressed image, other for more types
+            for patch in temp bank consist of 001b: patch+fsbl, 010b: patch+app, 011b: patch+fsbl+app*/
+        } flag_value;
+    } ctrl_flag;
+    uint16_t image_id;
+    uint32_t payload_len;
+} T_IMG_CTRL_HEADER_FORMAT;
+
+typedef struct _COMPRESS_IMG_HEADER_FORMAT //96 bytes
+{
+    T_IMG_CTRL_HEADER_FORMAT ctrl_header; //12 bytes
+    uint8_t uuid[16];
+    uint32_t version;
+    uint32_t compress_algo;
+    uint8_t sha256[32];
+    uint8_t reserved[28];
+} T_COMPRESS_IMG_HEADER_FORMAT;
+
+typedef struct
+{
+    union
+    {
+        uint32_t version;
+        struct
+        {
+            uint32_t _version_reserve: 8;   //!< reserved
+            uint32_t _version_revision: 8; //!< revision version
+            uint32_t _version_minor: 8;     //!< minor version
+            uint32_t _version_major: 8;     //!< major version
+        } header_sub_version; //!< ota header sub version
+        struct
+        {
+            uint32_t _version_major: 4;     //!< major version
+            uint32_t _version_minor: 8;     //!< minor version
+            uint32_t _version_revision: 15; //!< revision version
+            uint32_t _version_reserve: 5;   //!< reserved
+        } img_sub_version; //!< other image sub version including patch, app, app data 1-6
+
+    } ver_info;
+} T_IMAGE_VERSION;
+
+typedef struct
+{
+    union
+    {
+        uint32_t version;
+        struct
+        {
+            uint32_t _version_major: 4;     //!< major version
+            uint32_t _version_minor: 8;     //!< minor version
+            uint32_t _version_revision: 15; //!< revision version
+            uint32_t _version_reserve: 5;   //!< reserved
+        } sub_version;
+    } ver_info;
+    uint32_t _version_commitid;     //!< git commit id
+    uint8_t _customer_name[8];      //!< branch name for customer patch
+} T_VERSION_FORMAT;
+
+typedef struct _AUTH_HEADER_FORMAT
+{
+    uint8_t image_mac[CMAC_BYTE_SIZE];
+    union
+    {
+        uint8_t rsa_image_2048_signature[RSA_2048_SIGNATURE_BYTE_SIZE];
+        uint8_t rsa_image_3072_signature[RSA_3072_SIGNATURE_BYTE_SIZE];
+    } sig;
+    uint8_t image_hash[SHA256_BYTE_SIZE];
+} T_AUTH_HEADER_FORMAT;
+
+typedef union
+{
+    uint8_t bytes[24];
+    struct
+    {
+        uint32_t itcm_heap_addr;
+        uint32_t app_ram_data_size;
+        uint32_t app_heap_data_on_size;
+    } app_ram_info;
+} T_EXTRA_INFO_FORMAT;
+
+typedef struct _FLASH_SEC_FORMAT
+{
+    union
+    {
+        uint32_t value;
+        struct
+        {
+            uint32_t enable: 1;
+            uint32_t mode: 2; // gcm mode:0b00, ctr mode:0b01, mix mode:0b10
+            uint32_t key_select: 3;
+            uint32_t rsvd: 26;
+        };
+    } ctrl_flag;
+    uint32_t base_addr;
+    uint32_t region_size;
+    uint8_t iv_high[4];
+    uint8_t iv_low[4];
+} T_FLASH_SEC_FORMAT;
+
+typedef union _IMG_HEADER_FORMAT
+{
+    uint8_t bytes[DEFAULT_HEADER_SIZE];
+    struct
+    {
+        T_AUTH_HEADER_FORMAT auth;   //16 +384 +32
+        T_IMG_CTRL_HEADER_FORMAT ctrl_header;
+        uint8_t uuid[16];
+        uint32_t exe_base;
+        uint32_t load_src;
+        uint32_t load_len;
+        uint32_t image_base;
+        uint16_t dev_id; // for AMZN
+        uint16_t flash_layout_size_4k; // ex. 1MB flash used size => flash_layout_size_4k = 1MB/4KB = 256
+        uint32_t magic_pattern;
+        uint8_t dec_key[16];
+        uint32_t load_dst;
+        T_EXTRA_INFO_FORMAT ex_info;
+        T_VERSION_FORMAT git_ver;
+        T_RSA_PUBLIC_KEY PubKey;
+        union
+        {
+            uint8_t reserved_data[92];
+            struct
+            {
+                uint32_t ver_val;
+                uint32_t image_info[(IMAGE_MAX - SecureBoot) * 2];
+            };
+            struct __attribute__((packed))
+            {
+                uint16_t tool_version;
+                uint32_t timestamp;
+                T_FLASH_SEC_FORMAT flash_sec_cfg;
+                uint16_t fsbl_ext_img_id;
+                uint16_t fsbl_ext_load_pattern;
+                uint8_t reserved1[62];
+            };
+        };
+    };
+} T_IMG_HEADER_FORMAT;
+
+typedef struct _ROM_HEADER_FORMAT
+{
+    uint8_t uuid[UUID_SIZE];
+    void *init_ptr;
+    void *entry_ptr;
+} T_ROM_HEADER_FORMAT;
+
+#endif /* _IMAGE_HEADER_H_ */
diff --git a/bee/boot/inc/rtl8752h/image_info.h b/bee/boot/inc/rtl8752h/image_info.h
new file mode 100644
index 00000000..46f41dee
--- /dev/null
+++ b/bee/boot/inc/rtl8752h/image_info.h
@@ -0,0 +1,206 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _PATCH_HEADER_CHECK_H_
+#define _PATCH_HEADER_CHECK_H_
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "rtl876x.h"
+#include "flash_nor_device.h"
+#include "image_header.h"
+#include "image_check.h"
+
+/*============================================================================*
+  *                                   Functions
+ *============================================================================*/
+
+/**
+ * @brief  Get image address in OTA header
+ *
+ * @param[in]  ota_addr: valid OTA header address
+ * @param[in]  image_id: image ID
+ *
+ * @return Image address in OTA header
+*/
+extern uint32_t *get_image_addr_in_bank(uint32_t ota_addr, T_IMG_ID image_id);
+
+/**
+ * @brief  Get image size in OTA header
+ *
+ * @param[in]  ota_addr: valid OTA header address
+ * @param[in]  image_id: image ID
+ *
+ * @return Image size in OTA header
+*/
+extern uint32_t *get_image_size_in_bank(uint32_t ota_addr, T_IMG_ID image_id);
+
+/**
+ * @brief  Get start address of active OTA bank
+ *
+ * @return Start address of active OTA bank
+*/
+extern uint32_t get_active_ota_bank_addr(void);
+
+/**
+ * @brief  Check configured flash layout support bank switch
+ *
+ * @return Check result
+ * @retval true Support bank switch
+ * @retval false Otherwise
+*/
+extern bool is_ota_support_bank_switch(void);
+
+/**
+ * @brief  Calculate checksum (CRC16 or SHA256 determined by image) over the image, and compare
+ *         with given checksum value.
+ *
+ * @param  p_header Image header info of the given image.
+ *
+ * @return Check result
+ * @retval true If image integrity check passes via checksum compare
+ * @retval false Otherwise
+*/
+extern bool check_image_chksum(T_IMG_HEADER_FORMAT *p_header);
+
+/**
+ * @brief  Get specified image header address in active bank
+ *
+ * @param[in]  image_id Specify the image
+ *
+ * @return Specified image header address
+*/
+extern uint32_t get_header_addr_by_img_id(T_IMG_ID image_id);
+
+/**
+ * @brief  Get image size of specified image which is located in OTA active bank
+ *
+ * @param[in]  image_id Specify the image which is located in OTA active bank
+ * @return Image size of specified image which is located in OTA active bank
+*/
+extern uint32_t get_active_bank_image_size_by_img_id(T_IMG_ID image_id);
+/**
+ * @brief  Get start address of specified image which is located in OTA temp bank
+ *
+ * @param[in]  image_id Specify the image
+ * @return Start address of specified image which is located in OTA temp bank
+*/
+static uint32_t get_temp_ota_bank_addr_by_img_id(T_IMG_ID image_id);
+
+/**
+ * @brief  Get the size of the specified image located in the OTA temp bank.
+ *
+ * @param[in]  image_id Specify the image.
+ * @return The size of the specified image located in the OTA temp bank.
+*/
+static uint32_t get_temp_ota_bank_size_by_img_id(T_IMG_ID image_id);
+
+/**
+ * @brief  Get version info of the specified image located in the active bank.
+ *
+ * @param[in]  image_id Specify the image.
+ * @return Version info of the specified image located in the active bank.
+*/
+extern bool get_active_bank_image_version(T_IMG_ID image_id, T_IMAGE_VERSION *p_image_version);
+
+static inline uint32_t get_temp_ota_bank_addr_by_img_id(T_IMG_ID image_id)
+{
+    uint32_t image_addr = 0;
+    if (image_id < OTA || ((image_id >= IMAGE_MAX)))
+    {
+        return image_addr;
+    }
+    if (!is_ota_support_bank_switch())
+    {
+        if (image_id == OTA)
+        {
+            return 0;
+        }
+        image_addr = flash_nor_get_bank_addr(FLASH_OTA_TMP);
+    }
+    else
+    {
+        uint32_t ota_bank0_addr = flash_nor_get_bank_addr(FLASH_OTA_BANK_0);
+        uint32_t temp_bank_addr;
+        if (ota_bank0_addr == get_active_ota_bank_addr())
+        {
+            temp_bank_addr = flash_nor_get_bank_addr(FLASH_OTA_BANK_1);
+        }
+        else
+        {
+            temp_bank_addr = ota_bank0_addr;
+        }
+        if (image_id == OTA)
+        {
+            image_addr = temp_bank_addr;
+        }
+        else if (image_id >= SecureBoot && image_id < IMAGE_MAX)
+        {
+            if (IMG_CHECK_PASS != check_header_valid(temp_bank_addr, OTA))
+            {
+                return 0;
+            }
+            image_addr = *get_image_addr_in_bank(temp_bank_addr, image_id);
+        }
+    }
+    if (image_addr == 0xffffffff)
+    {
+        return 0;
+    }
+    return image_addr;
+}
+
+static inline uint32_t get_temp_ota_bank_size_by_img_id(T_IMG_ID image_id)
+{
+    uint32_t image_size = 0;
+
+    if (image_id < OTA || ((image_id >= IMAGE_MAX)))
+    {
+        return image_size;
+    }
+
+    if (!is_ota_support_bank_switch())
+    {
+        if (image_id == OTA)
+        {
+            return 0;
+        }
+
+        image_size = flash_nor_get_bank_size(FLASH_OTA_TMP);
+    }
+    else
+    {
+        uint32_t ota_bank0_addr = flash_nor_get_bank_addr(FLASH_OTA_BANK_0);
+        uint32_t temp_bank_addr;
+
+        if (ota_bank0_addr == get_active_ota_bank_addr())
+        {
+            temp_bank_addr = flash_nor_get_bank_addr(FLASH_OTA_BANK_1);
+        }
+        else
+        {
+            temp_bank_addr = ota_bank0_addr;
+        }
+
+        if (image_id == OTA)
+        {
+            image_size = OTA_HEADER_SIZE;
+        }
+        else if (image_id >= SecureBoot && image_id < IMAGE_MAX)
+        {
+            if (IMG_CHECK_PASS != check_header_valid(temp_bank_addr, OTA))
+            {
+                return 0;
+            }
+
+            image_size = *get_image_size_in_bank(temp_bank_addr, image_id);
+        }
+    }
+
+    return image_size;
+}
+
+#endif /* _PATCH_HEADER_CHECK_H_ */
diff --git a/bee/boot/inc/rtl8752h/rtl_boot_record.h b/bee/boot/inc/rtl8752h/rtl_boot_record.h
new file mode 100644
index 00000000..933c19b5
--- /dev/null
+++ b/bee/boot/inc/rtl8752h/rtl_boot_record.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *                      Define to prevent recursive inclusion
+ *============================================================================*/
+#ifndef _RTL_BOOT_RECORD_H_
+#define _RTL_BOOT_RECORD_H_
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*============================================================================*
+ *                      Headers
+ *============================================================================*/
+
+enum STAGE_INDEXES{
+	START_PLATFORM_INIT = 1,
+	/* alway execution */
+	AON_BOOT_DONE = 2,
+	/* post execution */
+	PON_BOOT_DONE = 3,
+};
+
+/*============================================================================*
+ *                      Functions
+ *============================================================================*/
+void rtl_boot_stage_record(uint8_t index);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTL_BOOT_RECORD_H_ */
diff --git a/bee/boot/inc/rtl8752h/system_rtl876x.h b/bee/boot/inc/rtl8752h/system_rtl876x.h
new file mode 100644
index 00000000..5cae77ec
--- /dev/null
+++ b/bee/boot/inc/rtl8752h/system_rtl876x.h
@@ -0,0 +1,125 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *                      Define to prevent recursive inclusion
+ *============================================================================*/
+#ifndef SYSTEM_RTL876X_H
+#define SYSTEM_RTL876X_H
+
+/*============================================================================*
+ *                      Headers
+ *============================================================================*/
+#include <stdint.h>
+#include <stdbool.h>
+#include <string.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup SYSTEM_RTL876X  System RTL876X
+  * @brief System Level API sets for RTL876x Device Series
+  * @{
+  */
+
+/*============================================================================*
+ *                      Types
+ *============================================================================*/
+/** @defgroup SYSTEM_RTL876X_Exported_Types System RTL876X Exported Types
+  * @{
+  */
+
+typedef enum
+{
+    LOG_TIMESTAMP_OS        = 0,
+    LOG_TIMESTAMP_HW_TIMER  = 1,
+    LOG_TIMESTAMP_RSVD      = 2,
+    LOG_TIMESTAMP_MAX       = 3
+} T_LOG_TIMESTAMP_TYPE;
+
+typedef bool (*APP_MAIN_FUNC)();
+typedef void (*USER_CALL_BACK)();
+
+/** @} */ /* End of group SYSTEM_RTL876X_Exported_types */
+
+/*============================================================================*
+ *                      Variables
+ *============================================================================*/
+/** @defgroup SYSTEM_RTL876X_Exported_Variables System RTL876X Exported Variables
+    * @brief
+    * @{
+    */
+extern APP_MAIN_FUNC upperstack_entry;
+extern APP_MAIN_FUNC app_pre_main;
+extern APP_MAIN_FUNC app_main;
+extern USER_CALL_BACK app_pre_main_cb;
+/** @} */ /* End of group SYSTEM_RTL876X_Exported_Variables */
+
+/*============================================================================*
+ *                      Functions
+ *============================================================================*/
+/** @defgroup SYSTEM_RTL876X_Exported_Functions System RTL876X Exported Functions
+    * @brief
+    * @{
+    */
+
+/**
+ * @brief  Call the system service.
+ * @param  opcode: operation code.
+ * @param  parm: parameter.
+ * @return none
+ */
+extern void SystemCall(uint32_t opcode, uint32_t parm);
+
+/**
+ * @brief  update ram layout for app.
+ * @param  app_global_size: app global ram size.
+ * @param  data_heap_size: data on heap total size.
+ * @param  share_cache_ram_size: the size of share cache to ram.
+ * @return none
+ */
+extern void update_ram_layout(uint32_t app_global_size, uint32_t data_heap_size,
+                              uint32_t share_cache_ram_size);
+
+/**
+ * @brief  Call the system service by stack.
+ * @param  opcode: operation code.
+ * @param  parm: parameter.
+ * @return none
+ */
+extern void SystemCall_Stack(uint32_t opcode, ...);
+
+/* RTL8752H SoC Initialization Functions */
+extern void (*si_flow_data_init)(void);
+extern void (*ft_paras_apply)(void);
+extern void hal_setup_hardware(void);
+extern void hal_setup_cpu(void);
+extern void share_cache_ram(void);
+extern bool check_hci_mode_flag(void);
+extern void set_hci_mode_flag(bool enable);
+extern void log_buffer_optimise_enable(void);
+extern bool hw_aes_create_mutex(void);
+extern void (*phy_hw_control_init)(bool dlps_flow);
+extern void (*phy_init)(uint8_t dlps_flow);
+extern void report_cache_info(void);
+extern void (*pmu_apply_voltage_tune)(void);
+extern void (*pmu_power_on_sequence_restart)(void);
+extern void (*si_flow_after_power_on_sequence_restart)(void);
+extern void (*platform_rtc_aon_init)(void);
+extern void (*platform_pm_init)(void);
+extern void (*power_manager_master_init)(void);
+extern void (*power_manager_slave_init)(void);
+
+/** @} */ /* End of group SYSTEM_RTL876X_Exported_Functions */
+
+/** @} */ /* End of group SYSTEM_RTL876X */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SYSTEM_RTL876X_H */
diff --git a/bee/boot/inc/rtl87x2g/image_check.h b/bee/boot/inc/rtl87x2g/image_check.h
new file mode 100644
index 00000000..4c8a3bca
--- /dev/null
+++ b/bee/boot/inc/rtl87x2g/image_check.h
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _IMAGE_CHECK_H_
+#define _IMAGE_CHECK_H_
+#include <stdbool.h>
+#include <stdint.h>
+#include <image_info.h>
+
+typedef enum
+{
+    IMG_CHECK_PASS,
+    IMG_CHECK_ERR_HEADER_ADDR,
+    IMG_CHECK_ERR_NOT_READY,
+    IMG_CHECK_ERR_ROM_UUID,
+    IMG_CHECK_ERR_MAGIC_PATTERN,
+    IMG_CHECK_ERR_SIZE,
+    IMG_CHECK_ERR_ID,
+    IMG_CHECK_ERR_ENTRY_RETURN,
+    IMG_CHECK_ERR_VERIFY,
+    IMG_CHECK_ERR_EXE_BASE,
+    IMG_CHECK_ERR_IC_TYPE,
+    IMG_CHECK_ERR_MAX,
+} IMG_CHECK_ERR_TYPE;
+
+typedef struct _ROM_HEADER_FORMAT
+{
+    uint8_t uuid[UUID_SIZE];
+    void *init_ptr;
+    void *entry_ptr;
+} T_ROM_HEADER_FORMAT;
+
+/*************************************************************************************************
+*                          functions
+*************************************************************************************************/
+IMG_CHECK_ERR_TYPE image_entry(uint16_t image_id, uint32_t image_addr);
+
+IMG_CHECK_ERR_TYPE image_entry_check(T_ROM_HEADER_FORMAT *rom_header,
+                                     T_ROM_HEADER_FORMAT *patch_header);
+
+#endif // _IMAGE_CHECK_H_
diff --git a/bee/boot/inc/rtl87x2g/image_info.h b/bee/boot/inc/rtl87x2g/image_info.h
new file mode 100644
index 00000000..2c6fac0c
--- /dev/null
+++ b/bee/boot/inc/rtl87x2g/image_info.h
@@ -0,0 +1,338 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _IMAGE_INFO_H_
+#define _IMAGE_INFO_H_
+#include <stdbool.h>
+#include <stdint.h>
+
+/*============================================================================*
+  *                                   Constants
+  *============================================================================*/
+#define OTA_HEADER_SIZE                     0x1000
+#define UUID_SIZE                           16
+#define DEFAULT_HEADER_SIZE                 (0x400 + 256)
+
+#define IMG_IC_TYPE                         0xF
+#define FLASH_NOR_TABLE_MAGIC_PATTERN       (0x5A5A12A5)
+
+#define CMAC_BYTE_SIZE                      (16)
+
+#define RSA_PUBLIC_KEY_BYTE_SIZE            (384)
+
+#define ECDSA_PUBLIC_KEY_BYTE_SIZE          (32)
+// ecdsa uncompressed key len = (public key byte len * 2) + 1
+#define ECDSA_UNCOMPRESSED_PUBLIC_KEY_LEN   (65)
+
+#define ED25519_PUBLIC_KEY_BYTE_SIZE        (32)
+
+#define SHA256_BYTE_SIZE                    (32)
+
+#define RSA_SIGNATURE_BYTE_SIZE             (RSA_PUBLIC_KEY_BYTE_SIZE)
+// *INDENT-OFF*
+#define RTK_MBEDTLS_ECDSA_MAX_SIG_LEN( bits )                               \
+        ( /*T,L of SEQUENCE*/ ( ( bits ) >= 61 * 8 ? 3 : 2 ) +              \
+          /*T,L of r,s*/        2 * ( ( ( bits ) >= 127 * 8 ? 3 : 2 ) +     \
+          /*V of r,s*/                ( ( bits ) + 8 ) / 8 ) )
+
+#define ECDSA_SIGNATURE_BYTE_SIZE           (RTK_MBEDTLS_ECDSA_MAX_SIG_LEN(ECDSA_PUBLIC_KEY_BYTE_SIZE << 3))
+
+#define ED25519_SIGNATURE_BYTE_SIZE         (ED25519_PUBLIC_KEY_BYTE_SIZE * 2)
+
+#define VP_PARTITION_NAME "VP"
+
+/*
+        - signature range   = hash + header content + payload
+        - hash range        = header content + payload
+*/
+#define SIGNATURE_RANGE(header)     (((T_IMG_HEADER_FORMAT *)(header))->ctrl_header.payload_len + header_size_rom - RSA_SIGNATURE_BYTE_SIZE)
+
+#define HASH_RANGE(header)          (((T_IMG_HEADER_FORMAT *)(header))->ctrl_header.payload_len + header_size_rom - RSA_SIGNATURE_BYTE_SIZE - SHA256_SIZE)
+
+#define GET_SIGNATURE(auth_type)    ((auth_type == AUTH_ECDSA) ?   header->auth.ecdsa_image_signature :   \
+                                     (auth_type == AUTH_ED25519) ? header->auth.ed25519_image_signature : \
+                                                                   header->auth.rsa_image_signature)
+
+#define GET_COMPUTE_PUBLIC_KEY_HASH_LEN(auth_type)                                   \
+                ((auth_type == AUTH_ECDSA) ?   (ECDSA_UNCOMPRESSED_PUBLIC_KEY_LEN) : \
+                 (auth_type == AUTH_ED25519) ? (ED25519_PUBLIC_KEY_BYTE_SIZE) :      \
+                                               (RSA_PUBLIC_KEY_BYTE_SIZE + 4))
+// *INDENT-ON*
+#define SYS_CFG_SIGNATURE           0x12345bb3
+/* Config Format: offset(2 bytes) + length(1 byte) + data(1 byte) + mask(1 byte)*/
+#define MIN_ENTRY_SIZE              5
+
+#define IMG_VER_TO_LITTLE_ENDIAN(git_ver)       (((git_ver & 0xf) << 28 ) + (((git_ver & 0xff0) >> 4) << 20) + (((git_ver & 0x07fff000) >> 12) << 5) + ((git_ver & 0xf8000000) >> 27))
+
+
+typedef enum
+{
+    IMG_SCCD             = 0x379D,
+    IMG_OCCD             = 0x379E,
+    IMG_BOOTPATCH        = 0x379F,          /*!< KM4 boot patch */
+    IMG_DFU_FIRST        = IMG_BOOTPATCH,
+    IMG_OTA              = 0x37A0,          /*!< OTA header */
+    IMG_SECUREMCUAPP     = 0x37A2,          /*!< KM4 secure app */
+    IMG_SECUREMCUAPPDATA = 0x37A3,          /*!< KM4 secure app data */
+    IMG_BT_STACKPATCH    = 0x37A6,          /*!< BT stack patch */
+    IMG_BANK_FIRST       = IMG_BT_STACKPATCH,
+    IMG_MCUPATCH         = 0x37A7,          /*!< KM4 non-secure rom patch */
+    IMG_UPPERSTACK       = 0x37A8,          /*!< KM4 non-secure Upperstack */
+    IMG_MCUAPP           = 0x37A9,          /*!< KM4 non-secure app */
+    IMG_MCUAPPDATA1      = 0x37AE,
+    IMG_MCUAPPDATA2      = 0x37AF,
+    IMG_MCUAPPDATA3      = 0x37B0,
+    IMG_MCUAPPDATA4      = 0x37B1,
+    IMG_MCUAPPDATA5      = 0x37B2,
+    IMG_MCUAPPDATA6      = 0x37B3,
+    IMG_ZIGBEESTACK      = 0x37B4,          /*!< KM4 Zigbee stack */
+    IMG_MAX              = 0x37B5,
+    IMG_DFU_MAX          = IMG_MAX,
+
+    IMG_RO_DATA1         = 0x3A81,  /*!< FOR vp */
+    IMG_RO_DATA2         = 0x3A82,
+    IMG_RO_DATA3         = 0x3A83,
+    IMG_RO_DATA4         = 0x3A84,
+    IMG_RO_DATA5         = 0x3A85,
+    IMG_RO_DATA6         = 0x3A86,
+
+    IMG_USER_DATA8       = 0xFFF7,    /*!< the image data only support unsafe single bank ota */
+    IMG_USER_DATA_FIRST  = IMG_USER_DATA8,
+    IMG_USER_DATA7       = 0xFFF8,    /*!< the image data only support unsafe single bank ota */
+    IMG_USER_DATA6       = 0xFFF9,    /*!< the image data only support unsafe single bank ota */
+    IMG_USER_DATA5       = 0xFFFA,    /*!< the image data only support unsafe single bank ota */
+    IMG_USER_DATA4       = 0xFFFB,    /*!< the image data only support unsafe single bank ota */
+    IMG_USER_DATA3       = 0xFFFC,    /*!< the image data only support unsafe single bank ota */
+    IMG_USER_DATA2       = 0xFFFD,    /*!< the image data only support unsafe single bank ota */
+    IMG_USER_DATA1       = 0xFFFE,    /*!< the image data only support unsafe single bank ota */
+    IMG_USER_DATA_MAX    = 0xFFFF,    /*!< the image data only support unsafe single bank ota */
+} IMG_ID;
+
+typedef enum _ENC_KEY_SELECT
+{
+    ENC_KEY_SCEK = 0,
+    ENC_KEY_SCEK_WITH_RTKCONST,
+    ENC_KEY_OCEK,
+    ENC_KEY_OCEK_WITH_OEMCONST,
+    ENC_KEY_ON_FLASH,
+    ENC_KEY_MAX,
+} ENC_KEY_SELECT;
+
+typedef union _PUBLIC_KEY
+{
+    struct
+    {
+        uint8_t N[RSA_PUBLIC_KEY_BYTE_SIZE];
+        uint8_t E[4];
+    };
+
+    struct
+    {
+        uint8_t ecdsa_key[ECDSA_UNCOMPRESSED_PUBLIC_KEY_LEN];
+    };
+
+    struct
+    {
+        uint8_t eddsa_key[ED25519_PUBLIC_KEY_BYTE_SIZE];
+    };
+
+} PUBLIC_KEY;
+
+typedef struct _IMG_CTRL_HEADER_FORMAT
+{
+    uint16_t crc16;
+    uint8_t ic_type;
+    uint8_t secure_version;
+    union
+    {
+        uint16_t value;
+        struct
+        {
+            uint16_t xip: 1; // payload is executed on flash
+            uint16_t enc: 1; // all the payload is encrypted
+            uint16_t load_when_boot: 1; // load image when boot
+            uint16_t enc_load: 1; // encrypt load part or not
+            uint16_t enc_key_select: 3; // referenced to ENC_KEY_SELECT
+            uint16_t not_ready: 1; //for copy image in ota
+            uint16_t not_obsolete: 1; //for copy image in ota
+            uint16_t integrity_check_en_in_boot: 1; // enable image integrity check in boot flow
+            uint16_t compressed_not_ready: 1;
+            uint16_t compressed_not_obsolete: 1;
+            uint16_t rsvd: 1;
+            uint16_t image_type: 3; /*for app 000b: normal image, 001b:compressed image, other for more types
+            for patch in temp bank consist of 001b: patch+fsbl, 010b: patch+app, 011b: patch+fsbl+app*/
+        };
+    } ctrl_flag;
+    uint16_t image_id;
+    uint32_t payload_len;
+} T_IMG_CTRL_HEADER_FORMAT;
+
+typedef struct
+{
+    union
+    {
+        uint32_t version;
+        struct
+        {
+            uint32_t _version_reserve: 8;   //!< reserved
+            uint32_t _version_revision: 8; //!< revision version
+            uint32_t _version_minor: 8;     //!< minor version
+            uint32_t _version_major: 8;     //!< major version
+        } header_sub_version; //!< ota header sub version
+        struct
+        {
+            uint32_t _version_major: 4;     //!< major version
+            uint32_t _version_minor: 8;     //!< minor version
+            uint32_t _version_revision: 15; //!< revision version
+            uint32_t _version_reserve: 5;   //!< reserved
+        } img_sub_version; //!< other image sub version including patch, app, app data1-6
+
+    } ver_info;
+} T_IMAGE_VERSION;
+
+typedef struct
+{
+    union
+    {
+        uint32_t version;
+        struct
+        {
+            uint32_t _version_major: 4;     //!< major version
+            uint32_t _version_minor: 8;     //!< minor version
+            uint32_t _version_revision: 15; //!< revision version
+            uint32_t _version_reserve: 5;   //!< reserved
+        } sub_version;
+    } ver_info;
+    uint32_t _version_commitid;     //!< git commit id
+    uint8_t _customer_name[8];      //!< branch name for customer patch
+} T_VERSION_FORMAT;
+
+typedef union
+{
+    uint8_t bytes[24];
+    struct
+    {
+        uint32_t app_ram_data_addr;
+        uint32_t app_ram_data_size;
+        uint32_t app_heap_data_on_size;
+        uint32_t ext_data_sram_size;
+        uint32_t rsvd[2];
+    } app_ram_info;
+} T_EXTRA_INFO_FORMAT;
+
+typedef struct _AUTH_HEADER_FORMAT
+{
+    union
+    {
+        uint8_t image_mac[CMAC_BYTE_SIZE];
+        uint8_t rsa_image_signature[RSA_SIGNATURE_BYTE_SIZE];
+        struct
+        {
+            uint8_t ecdsa_image_signature[ECDSA_SIGNATURE_BYTE_SIZE];
+            uint8_t ecdsa_image_signature_len;
+        };
+        uint8_t ed25519_image_signature[ED25519_SIGNATURE_BYTE_SIZE];
+    };
+    uint8_t image_hash[SHA256_BYTE_SIZE];
+} T_AUTH_HEADER_FORMAT;
+
+typedef struct _FLASH_SEC_FORMAT
+{
+    union
+    {
+        uint32_t value;
+        struct
+        {
+            uint32_t enable: 1;
+            uint32_t mode: 2; // gcm mode:0b00, ctr mode:0b01, mix mode:0b10
+            uint32_t key_select: 3;
+            uint32_t rsvd: 26;
+        };
+    } ctrl_flag;
+    uint32_t base_addr;
+    uint32_t region_size;
+    uint8_t iv_high[4];
+    uint8_t iv_low[4];
+} T_FLASH_SEC_FORMAT;
+
+/* image_info[] is used to record image address and size in OTA bank
+ * ex. non-secure patch's addr = image_info[(IMG_MCUPATCH - IMG_OTA - 1)*2 + 0]
+ *     non-secure patch's size = image_info[(IMG_MCUPATCH - IMG_OTA - 1)*2 + 1]
+ *     ...
+ *  => image_id's addr = image_info[(image_id - IMG_OTA - 1)*2 + 0]
+ *     image_id's size = image_info[(image_id - IMG_OTA - 1)*2 + 1]
+ */
+typedef union _IMG_HEADER_FORMAT
+{
+    uint8_t bytes[DEFAULT_HEADER_SIZE];
+    struct
+    {
+        T_AUTH_HEADER_FORMAT auth;
+        T_IMG_CTRL_HEADER_FORMAT ctrl_header;
+        uint8_t uuid[16];
+        uint32_t exe_base;
+        uint32_t load_src;
+        uint32_t load_len;
+        uint32_t image_base;
+        uint16_t dev_id; // for AMZN
+        uint16_t flash_layout_size_4k; // ex. 1MB flash used size => flash_layout_size_4k = 1MB/4KB = 256
+        uint32_t magic_pattern;
+        uint8_t dec_key[16];
+        uint32_t load_dst;
+        T_EXTRA_INFO_FORMAT ex_info;
+        T_VERSION_FORMAT git_ver;
+        PUBLIC_KEY PubKey;
+        T_FLASH_SEC_FORMAT flash_sec_cfg;
+        union
+        {
+            uint8_t reserved_data[344];
+            struct
+            {
+                uint32_t ver_val;
+                uint32_t image_info[(IMG_MAX - IMG_OTA - 1) * 2];
+                uint32_t reserved0[45];
+            };
+            struct __attribute__((packed))
+            {
+                uint32_t tool_version;
+                uint32_t timestamp;
+                uint16_t reserved1[168];
+            };
+        };
+    };
+} T_IMG_HEADER_FORMAT;
+
+/*************************************************************************************************
+*                          functions
+*************************************************************************************************/
+
+bool is_ota_support_bank_switch(void);
+
+uint32_t get_img_header_format_size(void);
+
+T_EXTRA_INFO_FORMAT *get_extra_info(void);
+
+uint32_t get_active_ota_bank_addr(void);
+
+uint32_t get_header_addr_by_img_id(IMG_ID image_id);
+
+uint32_t get_active_bank_image_size_by_img_id(IMG_ID image_id);
+
+uint32_t get_active_ota_bank_size(void);
+
+uint32_t get_temp_ota_bank_size(void);
+
+uint32_t get_temp_ota_bank_img_addr_by_img_id(IMG_ID image_id);
+
+uint32_t get_temp_ota_bank_img_size_by_img_id(IMG_ID image_id);
+
+bool get_ota_bank_image_version(bool is_active_bank, IMG_ID image_id,
+                                T_IMAGE_VERSION *p_image_version);
+
+bool get_ota_header_item(bool is_active_bank, uint32_t offset, uint32_t *data);
+
+
+#endif // _IMAGE_INFO_H_
diff --git a/bee/boot/inc/rtl87x2g/system_init_ns.h b/bee/boot/inc/rtl87x2g/system_init_ns.h
new file mode 100644
index 00000000..cb3cf408
--- /dev/null
+++ b/bee/boot/inc/rtl87x2g/system_init_ns.h
@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *                      Define to prevent recursive inclusion
+ *============================================================================*/
+#ifndef SYSTEM_INIT_NS_H
+#define SYSTEM_INIT_NS_H
+
+/*============================================================================*
+ *                      Headers
+ *============================================================================*/
+#include <stdint.h>
+#include <stdbool.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*============================================================================*
+ *                      Variables
+ *============================================================================*/
+
+extern uint32_t SystemCoreClock;
+extern void (*hal_setup_hardware)(void);
+extern void (*hal_setup_cpu)(void);
+extern void (*hal_setup_fpu)(void);
+extern bool (*mpu_setup)(void);
+extern void (*system_restore)(void);
+extern void (*dvfs_init)(void);
+extern void (*phy_hw_control_init)(bool);
+extern void (*phy_init)(uint8_t);
+extern void (*thermal_tracking_timer_init)(void);
+extern void (*ft_paras_apply)(void);
+extern void (*si_flow_data_init)(void);
+extern void (*secure_os_func_ptr_init)(void);
+extern void secure_os_func_ptr_init_rom(void);
+extern void (*secure_platform_func_ptr_init)(void);
+extern bool (*log_buffer_init)(void);
+extern void (*log_gdma_init)(void);
+extern void (*platform_rtc_aon_init)(void);
+extern void (*power_manager_master_init)(void);
+extern void (*power_manager_slave_init)(void);
+extern void (*platform_pm_init)(void);
+extern void (*pmu_power_on_sequence_restart)(void);
+extern void (*pmu_apply_voltage_tune)(void);
+extern void hw_aes_mutex_init(void);
+extern void os_queue_func_init(void);
+extern bool (*os_register_pm_excluded_handle)(void **pp_handle, int type);
+extern bool (*os_unregister_pm_excluded_handle)(void **pp_handle, int type);
+extern bool os_register_pm_excluded_handle_imp(void **handle, int type);
+extern bool os_unregister_pm_excluded_handle_imp(void **handle, int type);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SYSTEM_INIT_NS_H */
diff --git a/bee/boot/inc/rtl87x2j/image_check.h b/bee/boot/inc/rtl87x2j/image_check.h
new file mode 100755
index 00000000..89d9efc2
--- /dev/null
+++ b/bee/boot/inc/rtl87x2j/image_check.h
@@ -0,0 +1,79 @@
+/**
+  ******************************************************************************
+  * @file    image_check.h
+  * @author
+  * @version V1.0
+  * @date    2024-03
+  * @brief
+  ******************************************************************************
+  * Copyright(c) 2024, Realtek Semiconductor Corporation. All rights reserved.
+  ******************************************************************************
+  */
+
+#ifndef _IMAGE_CHECK_H_
+#define _IMAGE_CHECK_H_
+#include <stdbool.h>
+#include <stdint.h>
+#include "image_info.h"
+
+
+/*============================================================================*
+  *                                   Constants
+  *============================================================================*/
+
+
+/*============================================================================*
+  *                                   Types
+  *============================================================================*/
+typedef enum
+{
+    IMG_CHECK_PASS,
+    IMG_CHECK_ERR_HEADER_ADDR,
+    IMG_CHECK_ERR_NOT_READY,
+    IMG_CHECK_ERR_ROM_UUID,
+    IMG_CHECK_ERR_MAGIC_PATTERN,
+    IMG_CHECK_ERR_SIZE,
+    IMG_CHECK_ERR_ID,
+    IMG_CHECK_ERR_ENTRY_RETURN,
+    IMG_CHECK_ERR_VERIFY,
+    IMG_CHECK_ERR_EXE_BASE,
+    IMG_CHECK_ERR_ID_MISMATCH,
+    IMG_CHECK_ERR_MAX,
+} IMG_CHECK_ERR_TYPE;
+
+typedef struct _ROM_HEADER_FORMAT
+{
+    uint8_t uuid[UUID_SIZE];
+    void *init_ptr;
+    void *entry_ptr;
+} T_ROM_HEADER_FORMAT;
+
+/*************************************************************************************************
+*                          functions
+*************************************************************************************************/
+/**
+ * @brief check specified signature image start address
+ * @param header image header info of the given image.
+ * @param signature signature to specify which image
+ * @return image address
+*/
+
+extern bool (*image_integrity_check)(uint32_t img_addr, IMG_ID img_id);
+
+uint32_t check_image_header(T_IMG_HEADER_FORMAT *header, uint16_t image_id);
+
+IMG_CHECK_ERR_TYPE check_header_valid(uint32_t header_addr, IMG_ID image_id);
+
+bool check_image_crc16(T_IMG_HEADER_FORMAT *p_header);
+
+bool check_image_sha256(T_IMG_HEADER_FORMAT *p_header);
+
+IMG_CHECK_ERR_TYPE image_entry(uint16_t image_id, uint32_t image_addr);
+
+IMG_CHECK_ERR_TYPE image_entry_check(T_ROM_HEADER_FORMAT *rom_header,
+                                     T_ROM_HEADER_FORMAT *patch_header);
+
+IMG_CHECK_ERR_TYPE stack_patch_check_entry(void);
+
+
+#endif // _IMAGE_CHECK_H_
diff --git a/bee/boot/inc/rtl87x2j/image_info.h b/bee/boot/inc/rtl87x2j/image_info.h
new file mode 100755
index 00000000..0c701448
--- /dev/null
+++ b/bee/boot/inc/rtl87x2j/image_info.h
@@ -0,0 +1,537 @@
+/*
+  ******************************************************************************
+  * @file    image_info.h
+  * @author  Grace
+  * @version V0.0.1
+  * @date    2025-07-29
+  * @brief   This file contains all the functions regarding patch header check.
+  ******************************************************************************
+  * @attention
+  *
+  * This module is a confidential and proprietary property of RealTek and
+  * possession or use of this module requires written permission of RealTek.
+  *
+  * Copyright(c) 2025, Realtek Semiconductor Corporation. All rights reserved.
+  ******************************************************************************
+  */
+
+#ifndef _IMAGE_INFO_H_
+#define _IMAGE_INFO_H_
+#include <stdbool.h>
+#include <stdint.h>
+
+/** @addtogroup  FLASH_DEVICE    Flash Device
+    * @{
+    */
+/*============================================================================*
+  *                                   Constants
+  *============================================================================*/
+// *INDENT-ON*
+#define DEFAULT_HEADER_SIZE                 (0x400)
+#define CMAC_BYTE_SIZE                      (16)
+#define RSA_PUBLIC_KEY_BYTE_SIZE            (384)
+#define ECDSA_PUBLIC_KEY_BYTE_SIZE          (32)
+// ecdsa uncompressed key len = (public key byte len * 2) + 1
+#define ECDSA_UNCOMPRESSED_PUBLIC_KEY_LEN   (65)
+#define ED25519_PUBLIC_KEY_BYTE_SIZE        (32)
+#define SHA256_BYTE_SIZE                    (32)
+
+#define RSA_SIGNATURE_BYTE_SIZE             (RSA_PUBLIC_KEY_BYTE_SIZE)
+#define ECDSA_SIGNATURE_BYTE_SIZE           (ECDSA_PUBLIC_KEY_BYTE_SIZE * 2)
+#define ED25519_SIGNATURE_BYTE_SIZE         (ED25519_PUBLIC_KEY_BYTE_SIZE * 2)
+
+/*
+        - mac range         = signature + hash + header content + payload
+        - signature range   = hash + header content + payload
+        - hash range        = header content + payload
+*/
+#define OUT_OF_CMAC_RANGE           (offsetof(T_IMG_HEADER_FORMAT, auth) + offsetof(T_AUTH_HEADER_FORMAT, image_signature))
+#define OUT_OF_SIGN_RANGE           (offsetof(T_IMG_HEADER_FORMAT, auth) + offsetof(T_AUTH_HEADER_FORMAT, image_hash))
+#define OUT_OF_HASH_RANGE           (offsetof(T_IMG_HEADER_FORMAT, auth) + offsetof(T_AUTH_HEADER_FORMAT, PubKey))
+
+#define MAC_RANGE(header)           (((T_IMG_HEADER_FORMAT *)(header))->ctrl_header.payload_len + image_header_size_get() - OUT_OF_CMAC_RANGE)
+
+#define SIGNATURE_RANGE(header)     (((T_IMG_HEADER_FORMAT *)(header))->ctrl_header.payload_len + image_header_size_get() - OUT_OF_SIGN_RANGE)
+
+#define HASH_RANGE(header)          (((T_IMG_HEADER_FORMAT *)(header))->ctrl_header.payload_len + image_header_size_get() - OUT_OF_HASH_RANGE)
+
+
+/*IC Type refer to WIKI: https://wiki.realtek.com/display/Bee1/BT+SOC+IC+Type*/
+#define IMG_IC_TYPE                  18
+
+#define UUID_SIZE                    16
+
+#define DFU_HEADER_SIZE              16 //sizeof(T_IMG_CTRL_HEADER_FORMAT)
+
+#define IMG_HEADER_SIZE              1024
+#define OTA_HEADER_SIZE              0x400
+
+#define IMG_DFU_FIRST                (IMG_MCUPATCH)
+#define IMG_DFU_MAX                  (IMG_MAX)
+
+#define UP_ALIGN(size, align)        (((size) + (align) - 1) & ~(align - 1))
+
+#define SYS_CFG_SIGNATURE            0x12345bb3
+#define FLASH_TABLE_MAGIC_PATTERN    (0x5A5A12A5)
+
+#define GOLDEN_PATTERN_WORD_LEN  (20)
+#define GOLDEN_PATTERN_SIZE      (sizeof(uint32_t) * GOLDEN_PATTERN_WORD_LEN)
+
+#if defined (CONFIG_SOC_SERIES_RTL87X2J)
+#define CONFIG_IMG_BT_CONTROLLER_BOOT
+#define CONFIG_IMG_BT_HOST_BOOT
+
+#define PRE_IMG_PARTITION_FIRST   (IMG_PARTITION_BT_CONTROLLER)
+#endif
+
+/*============================================================================*
+  *                                   Types
+  *============================================================================*/
+/** @defgroup FLASH_DEVICE_Exported_Types Flash Device Exported Types
+  * @brief
+  * @{
+  */
+typedef enum
+{
+    IMAGE_FIRST       = 0x278D,
+    IMG_SCCD          = 0x278D,
+    IMG_OCCD          = 0x278E,
+    IMG_BOOTPATCH     = 0x278F,
+    IMG_OTA           = 0x2790, /**< OTA header */
+    IMG_RSVD          = 0x2791,
+    IMG_BANK_FIRST    = IMG_RSVD,
+    IMG_MCUPATCH      = 0x2792,
+    IMG_MCUAPP        = 0x2793,
+    IMG_MCUAPPDATA1   = 0x2794,
+    IMG_MCUAPPDATA2   = 0x2795,
+    IMG_MCUAPPDATA3   = 0x2796,
+    IMG_MCUAPPDATA4   = 0x2797,
+    IMG_MCUAPPDATA5   = 0x2798,
+    IMG_MCUCFGDATA    = 0x2799,
+    IMG_BT_HOST_PATCH       = 0x279a,
+    IMG_BT_CONTROLLER_PATCH = 0x279b,
+    IMG_MAX,
+
+    PRE_IMAGE_FIRST       = 0x27a2,
+    PRE_IMG_BT_CONTROLLER = PRE_IMAGE_FIRST,
+    PRE_IMG_BT_HOST       = 0x27a3,
+    PRE_IMG_MAX,
+
+    IMG_USER_DATA8       = 0xFFF7,    /*!< the image data only support unsafe single bank ota */
+    IMG_USER_DATA_FIRST  = IMG_USER_DATA8,
+    IMG_USER_DATA7       = 0xFFF8,    /*!< the image data only support unsafe single bank ota */
+    IMG_USER_DATA6       = 0xFFF9,    /*!< the image data only support unsafe single bank ota */
+    IMG_USER_DATA5       = 0xFFFA,    /*!< the image data only support unsafe single bank ota */
+    IMG_USER_DATA4       = 0xFFFB,    /*!< the image data only support unsafe single bank ota */
+    IMG_USER_DATA3       = 0xFFFC,    /*!< the image data only support unsafe single bank ota */
+    IMG_USER_DATA2       = 0xFFFD,    /*!< the image data only support unsafe single bank ota */
+    IMG_USER_DATA1       = 0xFFFE,    /*!< the image data only support unsafe single bank ota */
+    IMG_USER_DATA_MAX    = 0xFFFF,    /*!< the image data only support unsafe single bank ota */
+} IMG_ID;
+
+typedef enum
+{
+    IMG_PARTITION_OCCD,
+    IMG_PARTITION_BOOT_PATCH,
+#ifdef CONFIG_IMG_PLATFORM_BOOT
+    IMG_PARTITION_PLATFORM,
+#endif
+#ifdef CONFIG_IMG_BT_CONTROLLER_BOOT
+    IMG_PARTITION_BT_CONTROLLER,
+#endif
+#ifdef CONFIG_IMG_BT_HOST_BOOT
+    IMG_PARTITION_BT_HOST,
+#endif
+    IMG_PARTITION_OTA_BANK_0,
+    IMG_PARTITION_OTA_BANK_1,
+    IMG_PARTITION_BKP_DATA1,
+    IMG_PARTITION_BKP_DATA2,
+    IMG_PARTITION_OTA_TMP,
+    IMG_PARTITION_FTL,
+    IMG_PARTITION_TOTAL,
+} T_IMG_PARTITION_NAME;
+
+typedef enum _ENC_KEY_SELECT
+{
+    ENC_KEY_SCEK = 0,
+    ENC_KEY_SCEK_WITH_RTKCONST,
+    ENC_KEY_OCEK,
+    ENC_KEY_OCEK_WITH_OEMCONST,
+    ENC_KEY_ON_FLASH,
+    ENC_KEY_MAX,
+} ENC_KEY_SELECT;
+
+typedef enum _IMG_ENC_TYPE
+{
+    IMG_ENC_TYPE_NORMAL_AES       = 1,
+    IMG_ENC_TYPE_ON_THE_FLY       = 2,
+    IMG_ENC_TYPE_MAX
+} IMG_ENC_TYPE;
+
+typedef union
+{
+    uint8_t d8[ECDSA_UNCOMPRESSED_PUBLIC_KEY_LEN];
+    struct
+    {
+        uint8_t flag; /*04 for uncompressed public key*/
+        uint8_t x[ECDSA_PUBLIC_KEY_BYTE_SIZE];
+        uint8_t y[ECDSA_PUBLIC_KEY_BYTE_SIZE];
+    } ecdsa_pb_key;
+} PUBLIC_KEY;
+
+typedef enum _APP_IMAGE_TYPE
+{
+    IMAGE_NORMAL              = 0,
+    IMAGE_COMPRESSED          = 1,
+    //2-7 are reserved
+} T_IMAGE_TYPE;
+
+typedef struct _IMG_CTRL_HEADER_FORMAT
+{
+    union
+    {
+        uint32_t value;
+        struct
+        {
+            uint32_t header_version: 8;
+            uint32_t device_type: 4; /* eflash: 4; nor: 3; nand: 2; sd: 1; emmc: 0;
+                                      * nand\sd\emmc: 14, whatever: 15 */
+            uint32_t integrity_check_en_in_boot: 1; // enable image integrity check in boot flow
+            uint32_t load_when_boot: 1; // load image when boot
+            uint32_t not_ready: 1; //for copy image in ota
+            uint32_t not_obsolete: 1; //for copy image in ota
+            uint32_t compressed_not_ready: 1;
+            uint32_t compressed_not_obsolete: 1;
+            uint32_t compressed_image_type: 3;
+            uint32_t ctrl_flag_reserved: 11;
+        };
+    } ctrl_flag;
+    uint8_t ic_type;
+    uint8_t secure_version;
+    uint16_t image_id;
+    uint32_t header_len;
+    uint32_t payload_len;
+} T_IMG_CTRL_HEADER_FORMAT;
+
+typedef struct
+{
+    union
+    {
+        uint64_t version;
+        struct
+        {
+            uint64_t _version_reserve: 32;   //!< reserved
+            uint64_t _version_revision: 16; //!< revision version
+            uint64_t _version_minor: 8;     //!< minor version
+            uint64_t _version_major: 8;     //!< major version
+        } img_sub_version;
+    } ver_info;
+} __attribute__((packed)) T_IMAGE_VERSION;
+
+typedef struct
+{
+    union
+    {
+        uint64_t version;
+        struct
+        {
+            uint64_t _version_reserve: 32;   //!< reserved
+            uint64_t _version_revision: 16; //!< revision version
+            uint64_t _version_minor: 8;     //!< minor version
+            uint64_t _version_major: 8;     //!< major version
+        } sub_version;
+    };
+    uint32_t _version_commitid;     //!< git commit id
+    uint8_t _customer_name[8];      //!< branch name for customer patch
+    uint8_t version_reserved[4];
+} __attribute__((packed)) T_VERSION_FORMAT;
+
+typedef struct _AUTH_HEADER_FORMAT
+{
+    uint8_t img_string[6];// "IMGHDR"
+    uint16_t auth_length;
+    uint8_t auth_type;
+    uint8_t auth_reserved[7]; //for cmac 16bytes align
+    uint8_t cmac[CMAC_BYTE_SIZE];
+    uint8_t image_signature[ECDSA_SIGNATURE_BYTE_SIZE];
+    uint8_t image_hash[SHA256_BYTE_SIZE];
+    PUBLIC_KEY PubKey;
+    uint8_t auth_reserved1[3];
+} T_AUTH_HEADER_FORMAT; // 196 bytes
+
+typedef union
+{
+    uint8_t bytes[12];
+    struct
+    {
+        uint32_t app_ram_data_addr;
+        uint32_t app_ram_data_size;
+        uint32_t app_heap_data_on_size;
+    } app_ram_info;
+} T_EXTRA_INFO_FORMAT;
+
+typedef struct
+{
+    union
+    {
+        uint32_t value;
+        struct
+        {
+            uint32_t enc: 1;
+            uint32_t enc_type: 3; // 1: normal AES 2: on the fly
+            uint32_t mode: 4; // gcm mode:0b00, ctr mode:0b01, mix mode:0b10
+            uint32_t key_select: 4;
+            uint32_t is_encrypted: 1;
+            uint32_t rsvd: 19;
+        };
+    } ctrl_flag;
+    uint32_t encryption_load_addr; // load base  nor: flash address nand/sd/emmc: psram
+    uint32_t encryption_size;  // load size
+    uint32_t encryption_exe_addr;  // exe base  nor: ram address nand/sd/emmc: psram
+    uint8_t dec_key[16];
+    union
+    {
+        uint8_t iv[16];
+        struct
+        {
+            uint8_t  iv_high[4];
+            uint8_t  iv_low[4];
+            uint8_t  iv_reserved[8];
+        };
+    };
+
+} T_ENCRYPT_FORMAT; //48bytes
+
+typedef struct
+{
+    uint32_t  image_load_base;
+    uint32_t  image_load_size;
+    uint32_t  image_exe_base;
+    uint32_t  image_exe_size;
+} T_IMAGE_INFO;
+
+typedef union
+{
+    uint8_t  common_reserved[64];
+    struct
+    {
+        uint8_t  common_reserved1[5];
+        uint8_t  dev_id_valid;
+        uint16_t dev_id;
+        uint8_t  image_feature[16];         // used for image feature string
+        uint64_t image_release_version;     //used for image release version
+    };
+} T_COMMON_EXTRA_INFO_FORMAT;
+
+typedef union _IMG_HEADER_FORMAT
+{
+    uint8_t bytes[DEFAULT_HEADER_SIZE];
+    struct
+    {
+        T_AUTH_HEADER_FORMAT auth;   //196 bytes
+        T_IMG_CTRL_HEADER_FORMAT ctrl_header; //16 bytes
+        T_ENCRYPT_FORMAT encrypt_header; //48bytes
+        uint8_t uuid[16]; //16bytes
+        uint32_t magic_pattern; //4 bytes
+        T_VERSION_FORMAT git_ver;  //24bytes
+        T_COMMON_EXTRA_INFO_FORMAT extra_info; //64 bytes
+        union //656bytes
+        {
+            struct  // data 8bytes
+            {
+                uint16_t reserved[1];
+                uint16_t tool_version;
+                uint32_t timestamp;
+                uint8_t  data_reserved[648];
+            };
+
+            struct // image_header
+            {
+                uint32_t exe_entry;
+                uint32_t image_base; //image begin: nor:flash address   nand/sd/emmc: psram address
+                uint32_t ram_load_src; // ram code load base
+                uint32_t ram_load_len; // ram code load size
+                uint32_t ram_load_dst; // ram code exe base
+                union
+                {
+                    uint8_t  exe_image_reserved[636]; //T_EXTRA_INFO_FORMAT ex_info; //uint8_t comiple_stamp[16];
+                    struct // boot patch image_header 148
+                    {
+                        uint32_t resv_golden_pattern[GOLDEN_PATTERN_WORD_LEN];
+                        uint32_t pre_image_num;
+                        T_IMAGE_INFO ext_image_excute_info[(PRE_IMG_MAX - PRE_IMAGE_FIRST)]; //3x4
+                        uint8_t boot_patch_header_reserved[504];
+                    };
+                    struct
+                    {
+                        T_EXTRA_INFO_FORMAT ex_info;
+                        uint8_t app_header_reserved[624];
+                    };
+                };
+            };
+            struct   // ota header 264
+            {
+                uint32_t layout_size; // K
+                uint32_t ota_image_num;
+                T_IMAGE_INFO image_excute_info[(IMG_MAX - IMG_BANK_FIRST)];  //11x4
+                uint8_t  ota_header_reserved[452];
+            };
+        };
+    };
+}  __attribute__((packed)) T_IMG_HEADER_FORMAT;
+
+typedef struct _COMP_IMG_CTRL_HEADER_FORMAT
+{
+    uint8_t img_string[3]; //"COM"
+    union
+    {
+        uint16_t value;
+        struct
+        {
+            uint16_t not_ready: 1;
+            uint16_t not_obsolete: 1;
+            uint16_t integrity_check_en_in_boot: 1; // enable image integrity check in boot flow
+            uint16_t rsvd: 13;
+        };
+    } ctrl_flag;
+    uint8_t ic_type;
+    uint16_t image_id;
+    uint32_t payload_len;
+} __attribute__((packed)) T_COMP_IMG_CTRL_HEADER_FORMAT;
+
+
+typedef struct _COMP_IMG_HEADER_FORMAT //128 bytes
+{
+    T_COMP_IMG_CTRL_HEADER_FORMAT ctrl_header; //12bytes
+    uint8_t uuid[16];
+    uint64_t version;
+    uint8_t uncompressed_image_hash[32];
+    uint8_t compressed_image_hash[32];
+    uint32_t compress_algo;
+    uint8_t reverved[24];
+} __attribute__((packed)) T_COMP_IMG_HEADER_FORMAT;
+
+
+/*************************************************************************************************
+*                          Image info functions
+*************************************************************************************************/
+#define get_active_bank_image_addr_by_img_id image_addr_get //todo: remove after btc port
+
+/**
+ * @brief  Get the image header size
+ * @return uint32_t - Size of the image header in bytes
+ */
+uint32_t image_header_size_get(void);
+
+/**
+ * @brief  Get pointer to the extra image information
+ * @return T_EXTRA_INFO_FORMAT* - Pointer to the extra info structure
+ */
+T_EXTRA_INFO_FORMAT *image_extra_info_get(void);
+
+/**
+ * @brief  Get the version information for a specific image
+ * @param  image_id - ID of the image to query
+ * @return T_IMAGE_VERSION* - Pointer to the version structure
+ */
+T_IMAGE_VERSION *image_version_get(IMG_ID image_id);
+
+/**
+ * @brief  Get the base address of a specific image
+ * @param  image_id - ID of the image to query
+ * @return uint32_t - Base address of the image
+ */
+uint32_t image_addr_get(IMG_ID image_id);
+
+/**
+ * @brief  Get the size of a specific image
+ * @param  image_id - ID of the image to query
+ * @return uint32_t - Size of the image in bytes
+ */
+uint32_t image_size_get(IMG_ID image_id);
+
+/**
+ * @brief  Get the image payload addr
+ * @param  image_id - ID of the image to query
+ * @return uint32_t - Base address of the image payload
+ */
+uint32_t image_payload_addr_get(IMG_ID image_id);
+
+/**
+ * @brief  Get the image payload size
+ * @param  image_id - ID of the image to query
+ * @return uint32_t - Size of the image payload
+ */
+uint32_t image_payload_size_get(IMG_ID image_id);
+
+/**
+ * @brief  Get the load address of a specific image
+ * @param  image_id - ID of the image to query
+ * @return uint32_t - Load address of the image
+ */
+uint32_t image_load_addr_get(IMG_ID image_id);
+
+/**
+ * @brief  Get the load size of a specific image
+ * @param  image_id - ID of the image to query
+ * @return uint32_t - Load size of the image in bytes
+ */
+uint32_t image_load_size_get(IMG_ID image_id);
+
+/*************************************************************************************************
+*                          image info functions for DFU
+*************************************************************************************************/
+/**
+ * @brief  Check if dual bank OTA is enabled
+ * @return bool - true if dual bank OTA is enabled, false otherwise
+ */
+bool ota_dual_bank_enable(void);
+
+/**
+ * @brief  Get the base address of OTA bank
+ * @return uint32_t - Base address of the OTA bank
+ */
+uint32_t ota_bank_addr_get(void);
+
+/**
+ * @brief  Get the temporary address for image during DFU
+ * @param  image_id - ID of the image to query
+ * @return uint32_t - Temporary address for the image
+ */
+uint32_t image_temp_addr_get(IMG_ID image_id);
+
+/**
+ * @brief  Get the temporary size for image during DFU
+ * @param  image_id - ID of the image to query
+ * @return uint32_t - Temporary size for the image in bytes
+ */
+uint32_t image_temp_size_get(IMG_ID image_id);
+
+/**
+ * @brief  Get the base address of a specific image partition
+ * @param  name - Name of the partition to query
+ * @return uint32_t - Base address of the partition
+ */
+uint32_t image_partition_addr_get(T_IMG_PARTITION_NAME name);
+
+/**
+ * @brief  Get the size of a specific image partition
+ * @param  name - Name of the partition to query
+ * @return uint32_t - Size of the partition in bytes
+ */
+uint32_t image_partition_size_get(T_IMG_PARTITION_NAME name);
+
+/**
+ * @brief  entry the specific image
+ * @param  image_id - Id of the image to entry
+ */
+void image_entry_validation(IMG_ID image_id);
+
+/**
+ * @brief  Get the customer name of a specific image partition
+ * @param  image_id - Id of the image to entry
+ * @return uint8_t* - Address of image customer name
+ */
+uint8_t *image_customer_name_get(IMG_ID image_id);
+
+#endif // _IMAGE_INFO_H_
diff --git a/bee/boot/inc/rtl87x2j/system_init.h b/bee/boot/inc/rtl87x2j/system_init.h
new file mode 100644
index 00000000..4531687d
--- /dev/null
+++ b/bee/boot/inc/rtl87x2j/system_init.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+extern bool (*patch_ram_vector_table_update)(int irqn, IRQ_Fun isr_handler, bool *ret);
+extern void default_handler(void);
+
+extern void (*wakeup_init)(void);
+extern void (*power_manager_init)(void);
+extern void (*platform_pm_init)(void);
+extern void (*thermal_meter_init)(void);
+extern void phy_hw_control_init(bool);
+extern void (*phy_init)(bool);
+extern void (*thermal_tracking_init)(void);
+extern void (*amu_script_init)(void);
+extern void (*amu_init)(void);
diff --git a/bee/boot/src/rtl8752h/CMakeLists.txt b/bee/boot/src/rtl8752h/CMakeLists.txt
new file mode 100644
index 00000000..7d3e80f9
--- /dev/null
+++ b/bee/boot/src/rtl8752h/CMakeLists.txt
@@ -0,0 +1,4 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_sources(rtl_boot_record.c)
diff --git a/bee/boot/src/rtl8752h/rtl_boot_record.c b/bee/boot/src/rtl8752h/rtl_boot_record.c
new file mode 100644
index 00000000..8c39726a
--- /dev/null
+++ b/bee/boot/src/rtl8752h/rtl_boot_record.c
@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *                        Header Files
+ *============================================================================*/
+#include <rtl876x.h>
+#include <rtl876x_aon_reg.h>
+#include <rtl_boot_record.h>
+
+/*============================================================================*
+ *                         Types
+ *============================================================================*/
+enum {
+	START_TO_RUN_C_CODE = 3,
+	AFTER_CHECK_PAD_BOOT_FROM_FLASH_I = 4,
+	AFTER_LOAD_PATCH = 5,
+	AFTER_SET_SECURE_REG = 6,
+};
+
+/*============================================================================*
+ *                          Private Macros
+ *============================================================================*/
+#define BOOT_STAGE_RECORD(x) btaon_fast_update(AON_FAST_REG_REG0X_FW_GENERAL, 1 << (x), 1 << (x))
+
+/*============================================================================*
+ *                           Public Functions
+ *============================================================================*/
+void rtl_boot_stage_record(uint8_t index)
+{
+    AON_FAST_REG_REG0X_FW_GENERAL_TYPE aon_fast_reg_0x0 = {};
+    switch (index)
+    {
+    case START_PLATFORM_INIT:
+        BOOT_STAGE_RECORD(AFTER_LOAD_PATCH);
+        break;
+    case AON_BOOT_DONE:
+        aon_fast_reg_0x0.d16 = btaon_fast_read(AON_FAST_REG_REG0X_FW_GENERAL);
+        aon_fast_reg_0x0.aon_boot_done = 1;
+        btaon_fast_write(AON_FAST_REG_REG0X_FW_GENERAL, aon_fast_reg_0x0.d16);
+        break;
+    case PON_BOOT_DONE:
+        aon_fast_reg_0x0.d16 = btaon_fast_read(AON_FAST_REG_REG0X_FW_GENERAL);
+        aon_fast_reg_0x0.pon_boot_done = 1;
+        btaon_fast_write(AON_FAST_REG_REG0X_FW_GENERAL, aon_fast_reg_0x0.d16);
+        break;
+    default:
+        break;
+    }
+}
+
diff --git a/bee/drivers/CMakeLists.txt b/bee/drivers/CMakeLists.txt
new file mode 100644
index 00000000..65455053
--- /dev/null
+++ b/bee/drivers/CMakeLists.txt
@@ -0,0 +1,69 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+# Macro to add device IC sources and include directories
+# Usage: add_soc_series_subdir(rtl8752h)
+#        add_soc_series_subdir(rtl87x2g)
+#
+# If IC directory contains a CMakeLists.txt, use add_subdirectory.
+# Otherwise, auto-add source files and include directories.
+function(add_soc_series_subdir ic_name)
+    string(TOUPPER ${ic_name} ic_name_upper)
+    set(config_name "CONFIG_SOC_SERIES_${ic_name_upper}")
+    set(ic_dir "${CMAKE_CURRENT_SOURCE_DIR}/${ic_name}")
+
+    if(EXISTS "${ic_dir}/CMakeLists.txt")
+        # Use subdirectory's CMakeLists.txt
+        if(${config_name})
+            add_subdirectory(${ic_dir} ${ic_name}_binary)
+        endif()
+    else()
+        # Auto-add sources and include directories
+        file(GLOB ic_sources "${ic_dir}/*.c")
+
+        if(${config_name})
+            if(ic_sources)
+                zephyr_library_sources(${ic_sources})
+            endif()
+        endif()
+
+        if(EXISTS ${ic_dir})
+            zephyr_include_directories(${ic_dir})
+        endif()
+    endif()
+endfunction()
+
+add_subdirectory(adc)
+add_subdirectory_ifdef(CONFIG_REALTEK_BEE_BT bluetooth)
+add_subdirectory(can)
+add_subdirectory(codec)
+add_subdirectory(clock)
+add_subdirectory(crypto)
+add_subdirectory(debug)
+add_subdirectory(dma)
+add_subdirectory(entropy)
+add_subdirectory(fmc)
+add_subdirectory(gpio)
+add_subdirectory(gtc)
+add_subdirectory(i2c)
+add_subdirectory(i2s)
+add_subdirectory(ir)
+add_subdirectory(irq)
+add_subdirectory(keyscan)
+add_subdirectory_ifdef(CONFIG_REALTEK_BEE_MAC_802154 mac_802154)
+add_subdirectory(pinmux)
+add_subdirectory(pm)
+add_subdirectory(pwm)
+add_subdirectory(qdec)
+add_subdirectory(rcc)
+add_subdirectory(rtc)
+add_subdirectory(sdhc)
+add_subdirectory(spi)
+add_subdirectory(timer)
+add_subdirectory(uart)
+add_subdirectory(usb)
+if (CONFIG_REALTEK_BEE_CORE_WDT OR CONFIG_REALTEK_BEE_AON_WDT)
+    add_subdirectory(wdt)
+endif()
+
+zephyr_include_directories(.)
diff --git a/bee/drivers/Kconfig b/bee/drivers/Kconfig
new file mode 100644
index 00000000..f9f92217
--- /dev/null
+++ b/bee/drivers/Kconfig
@@ -0,0 +1,182 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+menu "HAL Realtek Bee Drivers"
+orsource "adc/Kconfig"
+orsource "bluetooth/Kconfig"
+orsource "can/Kconfig"
+orsource "codec/Kconfig"
+orsource "dma/Kconfig"
+orsource "gpio/Kconfig"
+orsource "i2c/Kconfig"
+orsource "i2s/Kconfig"
+orsource "ir/Kconfig"
+orsource "irq/Kconfig"
+orsource "keyscan/Kconfig"
+orsource "mac_802154/Kconfig"
+orsource "pinmux/Kconfig"
+orsource "pwm/Kconfig"
+orsource "qdec/Kconfig"
+orsource "rcc/Kconfig"
+orsource "rtc/Kconfig"
+orsource "sdhc/Kconfig"
+orsource "spi/Kconfig"
+orsource "timer/Kconfig"
+orsource "uart/Kconfig"
+orsource "usb/Kconfig"
+orsource "wdt/Kconfig"
+endmenu
+
+config REALTEK_BEE_COMMON_DRIVER
+	bool
+	default y
+	depends on !(SOC_SERIES_RTL8752H || SOC_SERIES_RTL87X2G)
+
+config WRAP_REALTEK_BEE_ADC
+	bool
+	default y
+	depends on HAL_REALTEK_BEE_ADC
+	select REALTEK_BEE_ADC
+
+config WRAP_REALTEK_BEE_CAN
+	bool
+	default y
+	depends on HAL_REALTEK_BEE_CAN
+	select REALTEK_BEE_CAN
+
+config WRAP_REALTEK_BEE_CODEC
+	bool
+	default y
+	depends on HAL_REALTEK_BEE_CODEC
+	select REALTEK_BEE_CODEC
+
+config WRAP_REALTEK_BEE_DMA
+	bool
+	default y
+	depends on HAL_REALTEK_BEE_DMA
+	select REALTEK_BEE_DMA
+
+config WRAP_REALTEK_BEE_GPIO
+	bool
+	default y
+	depends on HAL_REALTEK_BEE_GPIO
+	select REALTEK_BEE_GPIO
+
+config WRAP_REALTEK_BEE_GRTC
+	bool
+	default y
+	depends on HAL_REALTEK_BEE_GRTC
+	select REALTEK_BEE_GRTC
+
+config WRAP_REALTEK_BEE_I2C
+	bool
+	default y
+	depends on HAL_REALTEK_BEE_I2C
+	select REALTEK_BEE_I2C
+
+config WRAP_REALTEK_BEE_I2S
+	bool
+	default y
+	depends on HAL_REALTEK_BEE_I2S
+	select REALTEK_BEE_I2S
+
+config WRAP_REALTEK_BEE_IR
+	bool
+	default y
+	depends on HAL_REALTEK_BEE_IR
+	select REALTEK_BEE_IR
+
+config WRAP_REALTEK_BEE_KEYSCAN
+	bool
+	default y
+	depends on HAL_REALTEK_BEE_KEYSCAN
+	select REALTEK_BEE_KEYSCAN
+
+config WRAP_REALTEK_BEE_NVIC
+	bool
+	default y
+	select REALTEK_BEE_NVIC
+
+config WRAP_REALTEK_BEE_PINMUX
+	bool
+	default y
+	depends on HAL_REALTEK_BEE_PINMUX
+	select REALTEK_BEE_PINMUX
+
+config WRAP_REALTEK_BEE_AON_QDEC
+	bool
+	default y
+	depends on HAL_REALTEK_BEE_AON_QDEC
+	select REALTEK_BEE_AON_QDEC
+
+config WRAP_REALTEK_BEE_QDEC
+	bool
+	default y
+	depends on HAL_REALTEK_BEE_QDEC
+	select REALTEK_BEE_QDEC
+
+config WRAP_REALTEK_BEE_LPQDEC
+	bool
+	default y
+	depends on HAL_REALTEK_BEE_LPQDEC
+	select REALTEK_BEE_LPQDEC
+
+config WRAP_REALTEK_BEE_RCC
+	bool
+	default y
+	depends on HAL_REALTEK_BEE_RCC
+	select REALTEK_BEE_RCC
+
+config WRAP_REALTEK_BEE_RTC
+	bool
+	default y
+	depends on HAL_REALTEK_BEE_RTC
+	select REALTEK_BEE_RTC
+
+config WRAP_REALTEK_BEE_SDHC
+	bool
+	default y
+	depends on HAL_REALTEK_BEE_SDHC
+	select REALTEK_BEE_SDHC
+
+config WRAP_REALTEK_BEE_SPI
+	bool
+	default y
+	depends on HAL_REALTEK_BEE_SPI
+	select REALTEK_BEE_SPI
+
+config WRAP_REALTEK_BEE_TIM
+	bool
+	default y
+	depends on HAL_REALTEK_BEE_TIM
+	select REALTEK_BEE_TIMER
+
+config WRAP_REALTEK_BEE_ENHTIM
+	bool
+	default y
+	depends on HAL_REALTEK_BEE_ENHTIM
+	select REALTEK_BEE_ENHTIMER
+
+config WRAP_REALTEK_BEE_UART
+	bool
+	default y
+	depends on HAL_REALTEK_BEE_UART
+	select REALTEK_BEE_UART
+
+config WRAP_REALTEK_BEE_USB
+	bool
+	default y
+	depends on HAL_REALTEK_BEE_USB
+	select REALTEK_BEE_USB
+
+config WRAP_REALTEK_BEE_AON_WDT
+	bool
+	default y
+	depends on HAL_REALTEK_BEE_AON_WDT
+	select REALTEK_BEE_AON_WDT
+
+config WRAP_REALTEK_BEE_CORE_WDT
+	bool
+	default y
+	depends on HAL_REALTEK_BEE_CORE_WDT
+	select REALTEK_BEE_CORE_WDT
diff --git a/bee/drivers/adc/CMakeLists.txt b/bee/drivers/adc/CMakeLists.txt
new file mode 100644
index 00000000..ec5040d2
--- /dev/null
+++ b/bee/drivers/adc/CMakeLists.txt
@@ -0,0 +1,8 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+if(CONFIG_REALTEK_BEE_COMMON_DRIVER)
+    zephyr_include_directories(inc)
+endif()
+
+add_subdirectory_ifdef(CONFIG_REALTEK_BEE_ADC src)
diff --git a/bee/drivers/adc/Kconfig b/bee/drivers/adc/Kconfig
new file mode 100644
index 00000000..a5dbf6e4
--- /dev/null
+++ b/bee/drivers/adc/Kconfig
@@ -0,0 +1,8 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config REALTEK_BEE_ADC
+	bool "Realtek Bee ADC driver"
+	default n
+	help
+	  This option enables the ADC driver for Realtek Bee.
diff --git a/bee/drivers/adc/inc/rtl_adc.h b/bee/drivers/adc/inc/rtl_adc.h
new file mode 100644
index 00000000..4b41f87b
--- /dev/null
+++ b/bee/drivers/adc/inc/rtl_adc.h
@@ -0,0 +1,1073 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *               Define to prevent recursive inclusion
+ *============================================================================*/
+#ifndef RTL_ADC_H
+#define RTL_ADC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*============================================================================*
+ *                        Header Files
+ *============================================================================*/
+#include "utils/rtl_utils.h"
+#if defined (CONFIG_SOC_SERIES_RTL87X2G)
+#include "adc/src/device/rtl87x2g/rtl_adc_def.h"
+#elif defined (CONFIG_SOC_SERIES_RTL87X3E)
+#include "adc/src/device/rtl87x3e/rtl_adc_def.h"
+#elif defined (CONFIG_SOC_SERIES_RTL87X3D)
+#include "adc/src/device/rtl87x3d/rtl_adc_def.h"
+#elif defined (CONFIG_SOC_SERIES_RTL87X2J)
+#include "adc/src/device/rtl87x2j/rtl_adc_def.h"
+#elif defined (CONFIG_SOC_SERIES_RTL87X3J)
+#include "adc/src/device/rtl87x3j/rtl_adc_def.h"
+#endif
+
+/** \defgroup ADC         ADC
+  * \brief
+  * \{
+  */
+
+/*============================================================================*
+ *                         Constants
+ *============================================================================*/
+/** \defgroup ADC_Exported_Constants ADC Exported Constants
+  * \brief
+  * \{
+  */
+
+/**
+ * \defgroup    ADC_Channel_Index ADC Channel Index
+ * \{
+ * \ingroup     ADC_Exported_Constants
+ */
+#define ADC_Channel_Index_0           0
+#define ADC_Channel_Index_1           1
+#define ADC_Channel_Index_2           2
+#define ADC_Channel_Index_3           3
+#define ADC_Channel_Index_4           4
+#if (CHIP_ADC_CHANNEL_NUM > 4)
+#define ADC_Channel_Index_5           5
+#define ADC_Channel_Index_6           6
+#define ADC_Channel_Index_7           7
+#endif
+#if (CHIP_ADC_CHANNEL_NUM > 8)
+#define ADC_Channel_Index_8           8
+#define ADC_Channel_Index_9           9
+#define ADC_Channel_Index_10          10
+#define ADC_Channel_Index_11          11
+#define ADC_Channel_Index_12          12
+#define ADC_Channel_Index_13          13
+#define ADC_Channel_Index_14          14
+#define ADC_Channel_Index_15          15
+#endif
+#define IS_ADC_CHANNEL(ch)      ((ch) < CHIP_ADC_CHANNEL_NUM)
+
+/** End of ADC_Channel_Index
+  * \}
+  */
+
+/**
+ * \defgroup    ADC_Schedule_Index ADC Schedule Index
+ * \{
+ * \ingroup     ADC_Exported_Constants
+ */
+#define ADC_Schedule_Index_0          0
+#define ADC_Schedule_Index_1          1
+#define ADC_Schedule_Index_2          2
+#define ADC_Schedule_Index_3          3
+#define ADC_Schedule_Index_4          4
+#define ADC_Schedule_Index_5          5
+#define ADC_Schedule_Index_6          6
+#define ADC_Schedule_Index_7          7
+#define ADC_Schedule_Index_8          8
+#define ADC_Schedule_Index_9          9
+#define ADC_Schedule_Index_10         10
+#define ADC_Schedule_Index_11         11
+#define ADC_Schedule_Index_12         12
+#define ADC_Schedule_Index_13         13
+#define ADC_Schedule_Index_14         14
+#define ADC_Schedule_Index_15         15
+#if (CHIP_ADC_SCHEDULE_NUM > 16)
+#define ADC_Schedule_Index_16         16
+#define ADC_Schedule_Index_17         17
+#define ADC_Schedule_Index_18         18
+#define ADC_Schedule_Index_19         19
+#endif
+#define IS_ADC_SCH_INDEX(IDEX) ((IDEX) < CHIP_ADC_SCHEDULE_NUM)
+
+/** End of ADC_Schedule_Index
+  * \}
+  */
+
+/**
+ * \defgroup    ADC_Schedule_Table ADC Channel and Mode
+ * \{
+ * \ingroup     ADC_Exported_Constants
+ */
+#define SCHEDULE_TABLE(Index)         (Index)
+#define EXT_SINGLE_ENDED(Index)       ((uint16_t)((ADC_MODE_SINGLE_ENDED_VALUE << CHIP_ADC_MODE_OFFSET) | ADC_MODE_EXTERNAL_CH_NUM(Index)))
+#define EXT_DIFFERENTIAL(Index)       ((uint16_t)((ADC_MODE_DIFFERENTIAL_VALUE << CHIP_ADC_MODE_OFFSET) | ADC_MODE_EXTERNAL_CH_NUM(Index)))
+
+#define INTERNAL_VBAT_MODE            ((uint16_t)((ADC_MODE_INTERNAL_VALUE << CHIP_ADC_MODE_OFFSET) | ADC_MODE_INTERNAL_VBAT_CH_NUM))
+#if ADC_SUPPORT_VADPIN_MODE
+#define INTERNAL_VADPIN_MODE          ((uint16_t)((ADC_MODE_INTERNAL_VALUE << CHIP_ADC_MODE_OFFSET) | ADC_MODE_INTERNAL_VADPIN_CH_NUM))
+#endif
+
+
+#if ADC_SUPPORT_VADPIN_MODE
+#define IS_ADC_SCHEDULE_INDEX_CONFIG(CONFIG) (((CONFIG) & (0xffff << 2 << CHIP_ADC_MODE_OFFSET)) == 0 && \
+                                              ((IS_ADC_SCH_INDEX((CONFIG) & (~(0xffff << CHIP_ADC_MODE_OFFSET))) && \
+                                                (CONFIG & BIT(CHIP_ADC_MODE_OFFSET + 1) == 0)) || \
+                                               (CONFIG) == INTERNAL_VBAT_MODE || \
+                                               (CONFIG) == INTERNAL_VADPIN_MODE))
+#else
+#define IS_ADC_SCHEDULE_INDEX_CONFIG(CONFIG) (((CONFIG) & (0xffff << 2 << CHIP_ADC_MODE_OFFSET)) == 0 && \
+                                              ((IS_ADC_SCH_INDEX((CONFIG) & (~(0xffff << CHIP_ADC_MODE_OFFSET))) && \
+                                                (CONFIG & BIT(CHIP_ADC_MODE_OFFSET + 1) == 0)) || \
+                                               (CONFIG) == INTERNAL_VBAT_MODE))
+#endif
+
+/** End of ADC_Schedule_Table
+  * \}
+  */
+
+/**
+ * \defgroup    ADC_Convert_Time ADC Convert Time
+ * \{
+ * \ingroup     ADC_Exported_Constants
+ */
+typedef enum
+{
+    ADC_CONVERT_TIME,
+} ADCConvertTime_TypeDef;
+
+/** End of ADC_Convert_Time
+  * \}
+  */
+
+/**
+ * \defgroup    ADC_Data_Latch ADC Data Latch
+ * \{
+ * \ingroup     ADC_Exported_Constants
+ */
+typedef enum
+{
+    ADC_DATA_LATCH_POSITIVE,
+    ADC_DATA_LATCH_NEGATIVE,
+} ADCDataLatch_TypeDef;
+
+#define IS_ADC_DATA_LATCH(DATA_LATCH) (((DATA_LATCH) == ADC_DATA_LATCH_POSITIVE) || ((MODE) == ADC_DATA_LATCH_NEGATIVE))
+
+/** End of ADC_Data_Latch
+  * \}
+  */
+
+/**
+ * \defgroup    ADC_Data_Align ADC Data Align
+ * \{
+ * \ingroup     ADC_Exported_Constants
+ */
+typedef enum
+{
+    ADC_DATA_ALIGN_LSB,
+    ADC_DATA_ALIGN_MSB,
+} ADCDataAlign_TypeDef;
+
+#define IS_ADC_DATA_ALIGN(DATA_ALIGN) (((DATA_ALIGN) == ADC_DATA_ALIGN_LSB) || ((DATA_ALIGN) == ADC_DATA_ALIGN_MSB))
+
+/** End of ADC_Data_Align
+  * \}
+  */
+
+
+/**
+ * \defgroup    ADC_Data_Average ADC Data Average
+ * \{
+ * \ingroup     ADC_Exported_Constants
+ */
+typedef enum
+{
+    ADC_DATA_AVERAGE_OF_2,
+    ADC_DATA_AVERAGE_OF_4,
+    ADC_DATA_AVERAGE_OF_8,
+    ADC_DATA_AVERAGE_OF_16,
+    ADC_DATA_AVERAGE_OF_32,
+    ADC_DATA_AVERAGE_OF_64,
+    ADC_DATA_AVERAGE_OF_128,
+    ADC_DATA_AVERAGE_OF_256,
+    ADC_DATA_AVERAGE_MAX,
+} ADCDataAverage_TypeDef;
+
+#define IS_ADC_DATA_AVERAGE(_DATA_AVERAGE) (((_DATA_AVERAGE) == ADC_DATA_AVERAGE_OF_2) || \
+                                            ((_DATA_AVERAGE) == ADC_DATA_AVERAGE_OF_4) || \
+                                            ((_DATA_AVERAGE) == ADC_DATA_AVERAGE_OF_8) || \
+                                            ((_DATA_AVERAGE) == ADC_DATA_AVERAGE_OF_16) || \
+                                            ((_DATA_AVERAGE) == ADC_DATA_AVERAGE_OF_32) || \
+                                            ((_DATA_AVERAGE) == ADC_DATA_AVERAGE_OF_64) || \
+                                            ((_DATA_AVERAGE) == ADC_DATA_AVERAGE_OF_128) || \
+                                            ((_DATA_AVERAGE) == ADC_DATA_AVERAGE_OF_256))
+
+/** End of ADC_Data_Average
+  * \}
+  */
+
+
+/**
+ * \defgroup    ADC_FIFO_Threshold ADC FIFO Threshold
+ * \{
+ * \ingroup     ADC_Exported_Constants
+ */
+#define IS_ADC_FIFO_THRESHOLD(THD) ((THD) <= 0x3F)
+
+/** End of ADC_FIFO_Threshold
+  * \}
+  */
+
+/**
+ * \defgroup    ADC_Burst_Size ADC Burst Size
+ * \{
+ * \ingroup     ADC_Exported_Constants
+ */
+#define IS_ADC_BURST_SIZE(SIZE) ((SIZE) <= 0x3F)
+
+/** End of ADC_Burst_Size
+  * \}
+  */
+
+/**
+ * \defgroup    ADC_Operation_Mode ADC Operation Mode
+ * \{
+ * \ingroup     ADC_Exported_Constants
+ */
+typedef enum
+{
+    ADC_CONTINUOUS_MODE,
+    ADC_ONE_SHOT_MODE,
+} ADCOperationMode_TypeDef;
+
+#define IS_ADC_OPERATION_MODE(MODE) (((MODE) == ADC_CONTINUOUS_MODE) || ((MODE) == ADC_ONE_SHOT_MODE))
+
+/** End of ADC_Operation_Mode
+  * \}
+  */
+
+/**
+ * \defgroup    ADC_Power_On_Mode  ADC Power On Mode
+ * \{
+ * \ingroup     ADC_Exported_Constants
+ */
+typedef enum
+{
+    ADC_POWER_ON_AUTO,
+#ifdef ADC_POWER_MODE_CTRL_EN
+    ADC_POWER_ON_MANUAL,
+#endif
+} ADCPowerOnMode_TypeDef;
+
+#define IS_ADC_POWER_ON_MODE(MODE) (((MODE) == ADC_POWER_ON_AUTO) || ((MODE) == ADC_POWER_ON_MANUAL))
+
+/** End of ADC_Power_On_Mode
+  * \}
+  */
+
+/**
+ * \defgroup    ADC_Interrupts_Definition ADC Interrupts Definition
+ * \{
+ * \ingroup     ADC_Exported_Constants
+ */
+#define ADC_INT_FIFO_RD_REQ           ((uint32_t)(1 << 0))
+#define ADC_INT_FIFO_RD_ERR           ((uint32_t)(1 << 1))
+#define ADC_INT_FIFO_THD              ((uint32_t)(1 << 2))
+#define ADC_INT_ONE_SHOT_DONE         ((uint32_t)(1 << 4))
+#if (ADC_SUPPORT_INT_FIFO_FULL == 1)
+#define ADC_INT_FIFO_FULL             ((uint32_t)(1 << 3))
+#define ADC_INT_FIFO_OVERFLOW         ((uint32_t)(1 << 5))
+#else
+#define ADC_INT_FIFO_OVERFLOW         ((uint32_t)(1 << 3))
+#endif
+
+#define IS_ADC_INT(INT) (((INT) == ADC_INT_FIFO_RD_REQ) || \
+                         ((INT) == ADC_INT_FIFO_RD_ERR) || \
+                         ((INT) == ADC_INT_FIFO_THD) || \
+                         ((INT) == ADC_INT_FIFO_OVERFLOW) || \
+                         ((INT) == ADC_INT_ONE_SHOT_DONE) || \
+                         ((INT) == ADC_INT_FIFO_FULL))
+
+/** End of ADC_Interrupts_Definition
+  * \}
+  */
+
+#if (ADC_SUPPORT_RAP_FUNCTION == 1)
+/**
+ * \defgroup    ADC_Action ADC Action
+ * \{
+ * \ingroup     ADC_Exported_Constants
+ */
+typedef enum
+{
+    ADC_ACTION_ONE_SHOT_SAMPLE = 0,
+} ADCAction_TypeDef;
+
+/** End of ADC_Action
+  * \}
+  */
+#endif
+
+/** End of ADC_Exported_Constants
+  * \}
+  */
+
+/*============================================================================*
+ *                         Types
+ *============================================================================*/
+/** \defgroup ADC_Exported_Types ADC Exported Types
+  * \brief
+  * \{
+  */
+
+/**
+ * \brief       ADC init structure definition.
+ *
+ * \ingroup     ADC_Exported_Types
+ */
+typedef struct
+{
+    uint16_t ADC_SampleTime;                /*!< Specifies the ADC Sample clock. (n+1) cycles of 10MHz (19~16383).*/
+
+    ADCConvertTime_TypeDef ADC_ConvertTime; /**< Specifies the ADC Sample convert time.*/
+
+    FunctionalState ADC_DataWriteToFIFO;    /*!< Write ADC one shot mode data into fifo.*/
+
+    uint8_t ADC_FIFOThdLevel;               /*!< Specifies the ADC fifo threshold to trigger interrupt ADC_INT_FIFO_TH.
+                                                 This parameter can be a value of 0 to 31. */
+
+    uint8_t ADC_WaterLevel;                 /*!< Specifies the ADC fifo Burst Size to trigger DMA.
+                                                 This parameter can be a value of 0 to 31. */
+
+    FunctionalState ADC_FIFOOverWriteEn;    /*!< Specifies if Over Write fifo when fifo overflow.*/
+
+#if (ADC_SUPPORT_DMA_EN == 1)
+    FunctionalState ADC_DMAEn;              /*!< Specifies if DMA enable.*/
+#endif
+
+    uint16_t ADC_SchIndex[CHIP_ADC_SCHEDULE_NUM]; /*!< Specifies ADC mode and channel for schedule table.*/
+
+    uint32_t ADC_Bitmap;                    /*!< Specifies the schedule table channel map.
+                                                 This parameter can be a value of 16Bits map. */
+
+    FunctionalState ADC_TimerTriggerEn;     /*!< Enable ADC one-shot mode when tim7 toggles. */
+
+    ADCDataAlign_TypeDef ADC_DataAlign;     /*!< ADC Data MSB or LSB aligned. */
+
+#if (ADC_SUPPORT_DATAMINUS==1)
+    FunctionalState ADC_DataMinusEn;        /**< Enable or disable function that adc data latched
+                                                 minus the given offset before writes to reg/FIFO. */
+
+    uint16_t ADC_DataMinusOffset;           /**< Offset to be minused from adc data latched.
+                                                 This parameter can be a value of 0 to 4095. */
+#endif
+
+    ADCDataAverage_TypeDef ADC_DataAverage; /**< Number of data for calculate average. */
+
+    uint8_t ADC_DataAverageEn;              /**< Enable the calculation for average result of the one shot data. */
+
+    FunctionalState ADC_FIFOStopWriteEn;    /*!< Stop fifo from writing data. This bit will be asserted
+                                                 automatically as fifo overflow, (not automatically when
+                                                 ADC_FIFO_OVER_WRITE_ENABLE), need to be cleared in order
+                                                 to write data again. This will not stop overwrite mode.*/
+#ifdef ADC_POWER_MODE_CTRL_EN
+    ADCPowerOnMode_TypeDef ADC_PowerOnMode; /**< Specifies ADC power on mode.
+                                                 This parameter can be a value of \ref ADC_Power_On_Mode. */
+#endif
+
+
+    FunctionalState ADC_PowerAlwaysOnEn;    /*!< Specifies the power always on. */
+
+#if (ADC_SUPPORT_POWER_ON_DELAY ==1 )
+    FunctionalState ADC_PowerOnDlyEn;       /*!< Enable or Disable ADC 8ms delay after adc power on. */
+#endif
+
+#if (ADC_SUPPORT_DATA_CLIP ==1 )
+    FunctionalState ADC_DataClippingEn;     /*!< Enable or Disable ADC data clipping ,the controller to
+                                                 clipping the data with gain/offset mapping when the data value (ouput code) over 4095*/
+#endif
+} ADC_InitTypeDef;
+
+/** End of ADC_Exported_Types
+  * \}
+  */
+
+/*============================================================================*
+ *                         Functions
+ *============================================================================*/
+/** \defgroup ADC_Exported_Functions ADC Exported Functions
+  * \brief
+  * \{
+  */
+
+/**
+ * \brief   Deinitializes the ADC peripheral registers to their
+ *          default reset values(turn off ADC clock).
+ *
+ * \param[in] ADCx: Specify ADC peripheral, can only be ADC.
+ *
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_adc_init(void)
+ * {
+ *    ADC_DeInit(ADC);
+ * }
+ * \endcode
+ */
+void ADC_DeInit(ADC_TypeDef *ADCx);
+
+/**
+ * \brief Initializes the ADC peripheral according to the specified parameters in the ADC_InitStruct.
+ *
+ * \param[in]  ADCx: selected ADC peripheral.
+ * \param[in]  ADC_InitStruct: pointer to a ADC_InitTypeDef structure that contains the configuration information for the specified ADC peripheral.
+ *
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_adc_init(void)
+ * {
+ *    //Turn on the clock.
+ *    RCC_ClockCmd(ADC_CLOCK, ENABLE);
+
+ *    ADC_InitTypeDef ADC_InitStruct;
+ *    ADC_StructInit(&ADC_InitStruct);
+ *    ADC_InitStruct.ADC_SchIndex[0] = EXT_SINGLE_ENDED(0);
+ *    ADC_InitStruct.ADC_SchIndex[1] = EXT_SINGLE_ENDED(1);
+ *    ADC_InitStruct.ADC_Bitmap = 0x03;
+ *    //Add other initialization parameters that need to be configured here.
+ *    ADC_Init(ADC, &ADC_InitStruct);
+ * }
+ * \endcode
+ */
+void ADC_Init(ADC_TypeDef *ADCx, ADC_InitTypeDef *ADC_InitStruct);
+
+/**
+ * \brief   Fills each ADC_InitStruct member with its default value.
+ *
+ * \param[in] ADC_InitStruct: Pointer to an ADC_InitTypeDef structure which will be initialized.
+ *
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_adc_init(void)
+ * {
+ *    //Turn on the clock.
+ *    RCC_ClockCmd(ADC_CLOCK, ENABLE);
+
+ *    ADC_InitTypeDef ADC_InitStruct;
+ *    ADC_StructInit(&ADC_InitStruct);
+ *    ADC_InitStruct.ADC_SchIndex[0] = EXT_SINGLE_ENDED(0);
+ *    ADC_InitStruct.ADC_SchIndex[1] = EXT_SINGLE_ENDED(1);
+ *    ADC_InitStruct.ADC_Bitmap = 0x03;
+ *    //Add other initialization parameters that need to be configured here.
+ *    ADC_Init(ADC, &ADC_InitStruct);
+ * }
+ * \endcode
+ * \callgraph
+ *
+ */
+void ADC_StructInit(ADC_InitTypeDef *ADC_InitStruct);
+
+/**
+ * \brief   Enables or disables the ADC peripheral.
+ *
+ * \param[in]  ADCx: Specify ADC peripheral.
+ * \param[in]  ADCMode: ADC operation mode selection.
+ *             This parameter can be one of the following values:
+ *             \arg ADC_ONE_SHOT_MODE: One shot mode.
+ *             \arg ADC_CONTINUOUS_MODE: Continuous sampling mode.
+ * \param[in]  NewState: New state of the ADC peripheral.
+ *              This parameter can be: ENABLE or DISABLE.
+ *
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void board_adc_init(void)
+ * {
+ *     Pad_Config(P2_0, PAD_SW_MODE, PAD_IS_PWRON, PAD_PULL_NONE, PAD_OUT_DISABLE,
+ *                PAD_OUT_LOW);
+ *
+ *     Pad_Config(P2_1, PAD_SW_MODE, PAD_IS_PWRON, PAD_PULL_NONE, PAD_OUT_DISABLE,
+ *                PAD_OUT_LOW);
+ * }
+ *
+ * void driver_adc_init(void)
+ * {
+ *    //open clock
+ *    RCC_ClockCmd(ADC_CLOCK, ENABLE);
+ *
+ *    ADC_InitTypeDef ADC_InitStruct;
+ *    ADC_StructInit(&ADC_InitStruct);
+ *    ADC_InitStruct.ADC_SchIndex[0] = EXT_SINGLE_ENDED(0);
+ *    ADC_InitStruct.ADC_SchIndex[1] = EXT_SINGLE_ENDED(1);
+ *    ADC_InitStruct.ADC_Bitmap = 0x03;
+ *    //Add other initialization parameters here.
+ *    ADC_Init(ADC, &ADC_InitStruct);
+ *
+ *    ADC_INTConfig(ADC, ADC_INT_ONE_SHOT_DONE, ENABLE);
+ * }
+ *
+ * void adc_demo(void)
+ * {
+ *    board_adc_init();
+ *    driver_adc_init();
+ *    ADC_Cmd(ADC, ADC_ONE_SHOT_MODE, ENABLE);
+ * }
+ * \endcode
+ */
+void ADC_Cmd(ADC_TypeDef *ADCx, ADCOperationMode_TypeDef ADCMode, FunctionalState NewState);
+
+/**
+ * \brief   Enables or disables the specified ADC interrupts.
+ *
+ * \param[in]  ADCx: Specify ADC peripheral.
+ * \param[in]  ADC_INT: Specify the ADC interrupts sources to be enabled or disabled.
+ *             This parameter can be any combination of the following values:
+ *             \arg ADC_INT_FIFO_RD_REQ : FIFO read request.
+ *             \arg ADC_INT_FIFO_RD_ERR : FIFO read error.
+ *             \arg ADC_INT_FIFO_THD : ADC FIFO size > thd.
+ *             \arg ADC_INT_FIFO_OVERFLOW : ADC FIFO overflow.
+ *             \arg ADC_INT_ONE_SHOT_DONE : ADC one shot mode done.
+ * \param[in]  NewState: New state of the specified ADC interrupt.
+ *             This parameter can be: ENABLE or DISABLE.
+ *
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_adc_init(void)
+ * {
+ *    //open clock
+ *    RCC_ClockCmd(ADC_CLOCK, ENABLE);
+ *
+ *    ADC_InitTypeDef ADC_InitStruct;
+ *    ADC_StructInit(&ADC_InitStruct);
+ *    ADC_InitStruct.ADC_SchIndex[0] = EXT_SINGLE_ENDED(0);
+ *    ADC_InitStruct.ADC_SchIndex[1] = EXT_SINGLE_ENDED(1);
+ *    ADC_InitStruct.ADC_Bitmap = 0x03;
+ *    //Add other initialization parameters here.
+ *    ADC_Init(ADC, &ADC_InitStruct);
+ *
+ *    ADC_INTConfig(ADC, ADC_INT_FIFO_RD_ERR, ENABLE);
+ *    ADC_INTConfig(ADC, ADC_INT_ONE_SHOT_DONE, ENABLE);
+ * }
+ * \endcode
+ *
+ */
+void ADC_INTConfig(ADC_TypeDef *ADCx, uint32_t ADC_INT, FunctionalState NewState);
+
+/**
+ * \brief  Check whether the specified ADC interrupt flag is set.
+ *
+ * \param[in]  ADCx: selected ADC peripheral.
+ * \param[in]  ADC_INT_FLAG: Specifies the interrupt flag to check.
+ *             This parameter can be one of the following values:
+ *             \arg ADC_INT_ONE_SHOT_DONE: ADC once convert end interrupt.
+ *             \arg ADC_INT_FIFO_OVERFLOW: ADC FIFO overflow interrupt.
+ *             \arg ADC_INT_FIFO_THD: FIFO larger than threshold interrupt.
+ *             \arg ADC_INT_FIFO_RD_ERR: ADC read FIFO error interrupt.
+ *             \arg ADC_INT_FIFO_RD_REQ: ADC read FIFO request interrupt.
+ *
+ * \return The new state of ADC_INT (SET or RESET).
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void adc_demo(void)
+ * {
+ *     ITStatus int_status = RESET;
+ *     int_status = ADC_GetINTStatus(ADC,ADC_INT_FIFO_OVERFLOW);
+ * }
+ * \endcode
+ */
+ITStatus ADC_GetINTStatus(ADC_TypeDef *ADCx, uint32_t ADC_INT);
+
+/**
+ * \brief   Get all adc interrupt flag status.
+ *
+ * \param[in] ADCx: Specify ADC peripheral.
+ *
+ * \return  All ADC interrupt status.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void adc_demo(void)
+ * {
+ *   uint8_t all_flag_status = 0;
+ *   all_flag_status = ADC_GetAllFlagStatus(ADC);
+ * }
+ * \endcode
+ *
+ */
+uint8_t ADC_GetAllFlagStatus(ADC_TypeDef *ADCx);
+
+/**
+ * \brief  Clear the ADC interrupt pending bit.
+ *
+ * \param[in] ADCx: Specify ADC peripheral.
+ * \param[in] ADC_INT: Specifies the interrupt pending bit to clear.
+ *            This parameter can be any combination of the following values:
+ *            \arg ADC_INT_ONE_SHOT_DONE: ADC once convert end interrupt.
+ *            \arg ADC_INT_FIFO_OVERFLOW: ADC FIFO overflow interrupt.
+ *            \arg ADC_INT_FIFO_THD: FIFO larger than threshold interrupt.
+ *            \arg ADC_INT_FIFO_RD_ERR: ADC read FIFO error interrupt.
+ *            \arg ADC_INT_FIFO_RD_REQ: ADC read FIFO request interrupt.
+ *
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void adc_demo(void)
+ * {
+ *   ADC_ClearINTPendingBit(ADC,ADC_INT_FIFO_OVERFLOW);
+ * }
+ * \endcode
+ */
+void ADC_ClearINTPendingBit(ADC_TypeDef *ADCx, uint32_t ADC_INT);
+
+/**
+ * \brief      Read ADC data according to specific channel.
+ *
+ * \param[in]  ADCx: Specify ADC peripheral.
+ * \param[in]  Index: Can be 0 to 15.
+ *
+ * \return     The 12-bit converted ADC raw data.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void board_adc_init(void)
+ * {
+ *     Pad_Config(P2_0, PAD_SW_MODE, PAD_IS_PWRON, PAD_PULL_NONE, PAD_OUT_DISABLE,
+ *                PAD_OUT_LOW);
+ *
+ *     Pad_Config(P2_1, PAD_SW_MODE, PAD_IS_PWRON, PAD_PULL_NONE, PAD_OUT_DISABLE,
+ *                PAD_OUT_LOW);
+ * }
+ *
+ * void driver_adc_init(void)
+ * {
+ *    //open clock
+ *    RCC_ClockCmd(ADC_CLOCK, ENABLE);
+ *
+ *    ADC_InitTypeDef ADC_InitStruct;
+ *    ADC_StructInit(&ADC_InitStruct);
+ *    ADC_InitStruct.ADC_SchIndex[0] = EXT_SINGLE_ENDED(0);
+ *    ADC_InitStruct.ADC_SchIndex[1] = EXT_SINGLE_ENDED(1);
+ *    ADC_InitStruct.ADC_Bitmap = 0x03;
+ *    //Add other initialization parameters here.
+ *    ADC_Init(ADC, &ADC_InitStruct);
+ *
+ *    ADC_INTConfig(ADC, ADC_INT_ONE_SHOT_DONE, ENABLE);
+ * }
+ *
+ * void adc_demo(void)
+ * {
+ *    board_adc_init();
+ *    driver_adc_init();
+ *    ADC_Cmd(ADC, ADC_ONE_SHOT_MODE, ENABLE);
+ *    while(ADC_GetINTStatus(ADC, ADC_INT_ONE_SHOT_DONE) == RESET);
+ *    uint16_t raw_data_0 = ADC_ReadRawData(ADC, 0);
+ *    uint16_t raw_data_1 = ADC_ReadRawData(ADC, 1);
+ * }
+ * \endcode
+ */
+ADCDataWidth ADC_ReadRawData(ADC_TypeDef *ADCx, uint8_t Index);
+
+/**
+ * \brief   Get ADC average data from ADC schedule table0.
+ *
+ * \param[in]  ADCx: Specify ADC peripheral.
+ * \param[out] OutBuf: Buffer to save data read from ADC FIFO.
+ *
+ * \return  The 12-bit converted ADC raw data.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void board_adc_init(void)
+ * {
+ *     Pad_Config(P2_0, PAD_SW_MODE, PAD_IS_PWRON, PAD_PULL_NONE, PAD_OUT_DISABLE,
+ *                PAD_OUT_LOW);
+ * }
+ *
+ * void driver_adc_init(void)
+ * {
+ *    //open clock
+ *    RCC_ClockCmd(ADC_CLOCK, ENABLE);
+ *
+ *    ADC_InitTypeDef ADC_InitStruct;
+ *    ADC_StructInit(&ADC_InitStruct);
+ *    ADC_InitStruct.ADC_SchIndex[0] = EXT_SINGLE_ENDED(0);
+ *    ADC_InitStruct.ADC_Bitmap = 0x01;
+ *    ADC_InitStruct.ADC_DataAvgEn  = ADC_DATA_AVERAGE_ENABLE;
+ *    ADC_InitStruct.ADC_DataAvgSel = ADC_DATA_AVERAGE_OF_2;
+ *    //Add other initialization parameters here.
+ *    ADC_Init(ADC, &ADC_InitStruct);
+ *
+ *    ADC_INTConfig(ADC, ADC_INT_ONE_SHOT_DONE, ENABLE);
+ * }
+ *
+ * void adc_demo(void)
+ * {
+ *    board_adc_init();
+ *    driver_adc_init();
+ *    ADC_Cmd(ADC, ADC_ONE_SHOT_MODE, ENABLE);
+ *    while(ADC_GetINTStatus(ADC, ADC_INT_ONE_SHOT_DONE) == RESET);
+ *    uint16_t raw_data = 0;
+ *    raw_data = ADC_ReadAvgRawData(ADC);
+ * }
+ * \endcode
+ *
+ */
+ADCDataWidth ADC_ReadAvgRawData(ADC_TypeDef *ADCx);
+
+/**
+ * \brief  Read one byte data from ADC FIFO.
+ *
+ * \param[in]  ADCx: selected ADC peripheral.
+ *
+ * \return ADC FIFO data.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void board_adc_init(void)
+ * {
+ *     Pad_Config(P2_0, PAD_SW_MODE, PAD_IS_PWRON, PAD_PULL_NONE, PAD_OUT_DISABLE,
+ *                PAD_OUT_LOW);
+ * }
+ *
+ * void driver_adc_init(void)
+ * {
+ *    //open clock
+ *    RCC_ClockCmd(ADC_CLOCK, ENABLE);
+ *
+ *    ADC_InitTypeDef ADC_InitStruct;
+ *    ADC_StructInit(&ADC_InitStruct);
+ *    ADC_InitStruct.ADC_SchIndex[0] = EXT_SINGLE_ENDED(0);
+ *    ADC_InitStruct.ADC_Bitmap = 0x01;
+ *    ADC_InitStruct.ADC_DataWriteToFIFO = ADC_DATA_WRITE_TO_FIFO_DISABLE;
+ *    ADC_Init(ADC, &ADC_InitStruct);
+ *
+ *    ADC_INTConfig(ADC, ADC_INT_ONE_SHOT_DONE, ENABLE);
+ * }
+ *
+ * void adc_demo(void)
+ * {
+ *    board_adc_init();
+ *    driver_adc_init();
+ *    ADC_Cmd(ADC, ADC_ONE_SHOT_MODE, ENABLE);
+ *    while(ADC_GetINTStatus(ADC, ADC_INT_ONE_SHOT_DONE) == RESET);
+ *    uint16_t raw_data = 0;
+ *    raw_data = ADC_ReadFIFO(ADC);
+ * }
+ * \endcode
+ */
+ADCDataWidth ADC_ReadFIFO(ADC_TypeDef *ADCx);
+
+/**
+ * \brief   Get data from ADC FIFO.
+ *
+ * \param[in]  ADCx: Specify ADC peripheral.
+ * \param[out] outBuf: Buffer to save data read from ADC FIFO.
+ * \param[in]  Num: Number of data to be read.
+ *
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void adc_demo(void)
+ * {
+ *    //ADC already start
+ *    uint16_t raw_data[32] = {0};
+ *    uint8_t data_len = ADC_GetFIFODataLen(ADC);
+ *    ADC_ReadFIFOData(ADC,raw_data,data_len);
+ * }
+ * \endcode
+ *
+ */
+void ADC_ReadFIFOData(ADC_TypeDef *ADCx, ADCDataWidth *outBuf, uint16_t Num);
+
+/**
+ * \brief   Get ADC fifo data number.
+ *
+ * \param[in] ADCx: selected ADC peripheral.
+ *
+ * \return  Current data number in ADC FIFO.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void adc_demo(void)
+ * {
+ *    //ADC already start
+ *    uint16_t raw_data[32] = {0};
+ *    uint8_t data_len = ADC_GetFIFODataLen(ADC);
+ *    ADC_ReadFIFOData(ADC,raw_data,data_len);
+ * }
+ * \endcode
+ *
+ */
+uint8_t ADC_GetFIFODataLen(ADC_TypeDef *ADCx);
+
+/**
+ * \brief   Config ADC schedule table.
+ *
+ * \param[in]  ADCx: Specify ADC peripheral.
+ * \param[in]  ADCMode: ADC operation mode.
+ *             This parameter can be one of the following values:
+ *             \arg EXT_SINGLE_ENDED(index)
+ *             \arg EXT_DIFFERENTIAL(index)
+ *             \arg INTERNAL_VBAT_MODE
+ * \param[in]  Index: Schedule table index.
+ *
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void adc_demo(void)
+ * {
+ *   ADC_SchIndexConfig(ADC,INTERNAL_VBAT_MODE,0);
+ * }
+ * \endcode
+ *
+ */
+void ADC_SchIndexConfig(ADC_TypeDef *ADCx, uint8_t ADCMode, uint16_t Index);
+
+/**
+ * \brief   Config adc schedule table.
+ *
+ * \param[in]  ADCx: Specify ADC peripheral.
+ * \param[in]  BitMap: ADC bit map.
+ * \param[in]  NewState: New state of the ADC peripheral.
+ *             This parameter can be: ENABLE or DISABLE.
+ *
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void adc_demo(void)
+ * {
+ *   uint16_t bit_map = 0x03;
+ *   ADC_BitMapConfig(ADC,bit_map,ENABLE);
+ * }
+ * \endcode
+ */
+void ADC_BitMapConfig(ADC_TypeDef *ADCx, uint16_t BitMap);
+
+/**
+ * \brief   Enbale or disable stop FIFO from writing data.
+ *
+ * \param[in]  ADCx: Specify ADC peripheral.
+ * \param[in]  NewState: New state of the ADC FIFO write.
+ *             This parameter can be: ENABLE or DISABLE.
+ *
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void adc_demo(void)
+ * {
+ *   ADC_WriteFIFOCmd(ADC, ENABLE);
+ * }
+ * \endcode
+ */
+void ADC_WriteFIFOCmd(ADC_TypeDef *ADCx, FunctionalState NewState);
+
+/**
+ * \brief     Config ADC bypass resistor.
+ *
+ * \param[in] channelNum: External channel number, can be 0~7.
+ * \param[in] NewState: Specifies whether the channel enables bypass mode.
+ *            This parameter can be: ENABLE or DISABLE.
+ *
+ * \return    None.
+ *
+ * \attention The input voltage of channel pin using bypass mode cannot exceed 0.9V!
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void adc_demo(void)
+ * {
+ *   ADC_BypassCmd(0,ENABLE);
+ * }
+ * \endcode
+ */
+void ADC_BypassCmd(uint8_t ChannelNum, FunctionalState NewState);
+
+/**
+ * \brief   Clear ADC FIFO.
+ *
+ * \param[in] ADCx: Specify ADC peripheral.
+ *
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void adc_demo(void)
+ * {
+ *   ADC_ClearFIFO(ADC);
+ * }
+ * \endcode
+ */
+void ADC_ClearFIFO(ADC_TypeDef *ADCx);
+
+/**
+  * \brief  Enables or disables the ADC power always on.
+  *
+  * \param  ADCx: selected ADC peripheral.
+  * \param  NewState: new state of the specified ADC power always on.
+  *         This parameter can be: ENABLE or DISABLE.
+  *
+  * \return None
+  *
+  * <b>Example usage</b>
+  * \code{.c}
+  *
+  * void adc_demo(void)
+  * {
+  *   ADC_PowerAlwaysOnCmd(ADC, ENABLE);
+  * }
+  * \endcode
+  */
+void ADC_PowerAlwaysOnCmd(ADC_TypeDef *ADCx, FunctionalState NewState);
+
+#if (ADC_SUPPORT_RAP_FUNCTION == 1)
+/**
+  * \brief  Enables or disables RAP Mode.
+  *
+  * \param[in]  ADCx: Pointer to the selected ADC peripheral. \ref ADC Declaration
+  * \param[in]  NewState: New state of the RAP mode.
+  *             This parameter can be: ENABLE or DISABLE.
+  *
+  * \return None
+  *
+  * <b>Example usage</b>
+  * \code{.c}
+  *
+  * void adc_demo(void)
+  * {
+  *   ADC_RAPModeCmd(ADC, ENABLE);
+  * }
+  * \endcode
+  */
+void ADC_RAPModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState);
+
+/**
+  * \brief  Trigger an task which special of by firmware.
+  *
+  * \param[in]  ADCx: Pointer to the selected ADC peripheral. \ref ADC Declaration
+  * \param[in]  Action: ADC task to be trigger. \ref ADC_Action.
+  *
+  * \return None
+  *
+  * <b>Example usage</b>
+  * \code{.c}
+  *
+  * void adc_demo(void)
+  * {
+  *   ADC_ActionTrigger(ADC, ADC_ACTION_ONE_SHOT_SAMPLE);
+  * }
+  * \endcode
+  */
+void ADC_ActionTrigger(ADC_TypeDef *ADCx, uint32_t Action);
+
+#endif
+
+#if (ADC_SUPPORT_AUTO_CLOCK == 1)
+/**
+  * \brief  Enable or disable ADC auto mode.
+  *
+  * \param[in]  ADCx: Pointer to the selected ADC peripheral. \ref ADC Declaration
+  * \param[in]  NewState: New state of the RAP mode. This parameter can be:
+  *             \ENABLE:  Enable ADC auto mode which ADC can auto clolk gating.
+  *             \DISABLE: Disable ADC auto mode which ADC clock is always on.
+  *
+  * \return None
+  *
+  * <b>Example usage</b>
+  * \code{.c}
+  *
+  * void adc_demo(void)
+  * {
+  *   ADC_ClockAutoModeCmd(ADC, ENABLE);
+  * }
+  * \endcode
+  */
+void ADC_ClockAutoModeCmd(ADC_TypeDef *ADCx, FunctionalState Newstate);
+
+#endif
+#if (ADC_SUPPORT_GET_VOTAGE_API == 1)
+/**
+  * \brief  Converts ADC sample data to voltage based on the selected sampling mode.
+  *
+  * \param[in]  SampleMode: ADC sampling mode that determines the voltage conversion formula
+  *             This parameter can bethe values, please refer to \ref ADC_Constant_Private
+  * \param[in]  SampleData: ADC raw sample data to be converted
+  * \param[in]  ErrorStatus: Pointer to an variable to store error information. \ref ADCStatus_TypeDef
+  *
+  * \return Converted voltage value in millivolts (mV).
+  *
+  * <b>Example usage</b>
+  * \code{.c}
+  *
+  * void adc_demo(void)
+  * {
+  *      ADCStatus_TypeDef adc_error = 0;
+  *      float adc_voltage = ADC_GetVoltage(ADC, ADC_SAMPLE_DIVIDE_SINGLE_MODE, &adc_error);
+  * }
+  * \endcode
+  */
+
+float ADC_GetVoltage(const ADCSampleMode_TypeDef SampleMode, ADCDataWidth SampleData,
+                     ADCStatus_TypeDef *ErrorStatus);
+#endif
+
+/** End of ADC_Exported_Functions
+  * \}
+  */
+
+/** End of ADC
+  * \}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RTL_ADC_H */
+
+
diff --git a/bee/drivers/adc/src/CMakeLists.txt b/bee/drivers/adc/src/CMakeLists.txt
new file mode 100644
index 00000000..dd5e359a
--- /dev/null
+++ b/bee/drivers/adc/src/CMakeLists.txt
@@ -0,0 +1,4 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+add_subdirectory(device)
diff --git a/bee/drivers/adc/src/device/CMakeLists.txt b/bee/drivers/adc/src/device/CMakeLists.txt
new file mode 100644
index 00000000..390b5305
--- /dev/null
+++ b/bee/drivers/adc/src/device/CMakeLists.txt
@@ -0,0 +1,11 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+if(CONFIG_REALTEK_BEE_COMMON_DRIVER)
+    file(GLOB BEE_DRIVER_COMMON_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/rtl_common/*.c")
+    zephyr_library_sources(${BEE_DRIVER_COMMON_SOURCES})
+endif()
+
+add_soc_series_subdir(rtl8752h)
+add_soc_series_subdir(rtl87x2g)
+add_soc_series_subdir(rtl87x2j)
diff --git a/bee/drivers/adc/src/device/rtl8752h/adc_lib.h b/bee/drivers/adc/src/device/rtl8752h/adc_lib.h
new file mode 100644
index 00000000..787983cb
--- /dev/null
+++ b/bee/drivers/adc/src/device/rtl8752h/adc_lib.h
@@ -0,0 +1,137 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __ADC_K_LIB_H
+#define __ADC_K_LIB_H
+
+/*============================================================================*
+ *                         Includes
+ *============================================================================*/
+#include <stdbool.h>
+#include <stdint.h>
+
+/*============================================================================*
+ *                         Defines
+ *============================================================================*/
+#define SOC_VERSION_CHECK               1
+
+#define ADC_K_VERSION_N2                1
+//#define ADC_K_VERSION_N1                1
+//#define ADC_K_VERSION_0                 1
+#define ADC_K_VERSION_P1                1
+
+#define USE_ADC_DIVIDE_SINGLE_MODE      1
+#define USE_ADC_BYPASS_SINGLE_MODE      1
+#define USE_ADC_DIVIDE_DIFF_MODE        1
+#define USE_ADC_BYPASS_DIFF_MODE        1
+
+/**
+ * \addtogroup  IO          Peripheral Drivers
+ * \defgroup    ADC         ADC
+ *
+ * \brief       Manage the ADC peripheral functions.
+ *
+ * \ingroup     IO
+ */
+/*============================================================================*
+ *                         Constants
+ *============================================================================*/
+/**
+ * \defgroup    ADC_Exported_Constants  ADC Exported Constants
+ *
+ * \ingroup     ADC
+ */
+
+/**
+ * \defgroup    ADC_SampleMode  ADC SampleMode
+ * \{
+ * \ingroup     ADC_Exported_Constants
+ */
+typedef enum
+{
+    DIVIDE_SINGLE_MODE = 1,
+    BYPASS_SINGLE_MODE = 2,
+    DIVIDE_DIFFERENTIAL_MODE = 3,
+    BYPASS_DIFFERENTIAL_MODE = 4,
+} ADC_SampleMode;
+/** \} */
+
+/**
+ * \defgroup    ADC_ErrorStatus  ADC ErrorStatus
+ * \{
+ * \ingroup     ADC_Exported_Constants
+ */
+typedef enum
+{
+    NO_ERROR = 0,
+    PARAMETER_ERROR = -1,
+    RAM_DATA_ERROR = -2,
+    NO_CALIBRATION = -3,
+    VERSION_ERROR = -4,
+} ADC_ErrorStatus;
+/** \} */
+
+extern int8_t ADC_K_Version;
+extern uint16_t ADC_Resistance_Value;
+
+/** End of ADC_Exported_Constants
+  * \}
+  */
+
+/*============================================================================*
+ *                         Functions
+ *============================================================================*/
+/** \defgroup    ADC_Exported_Functions ADC Exported Functions
+  * \{
+  * \ingroup     ADC
+  */
+
+/**
+ * adc_lib.h
+ * \brief       Initialize the voltage conversion.
+ * \param[in]   None.
+ * \return      true/false.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * bool adc_k_status = false;
+ * adc_k_status = ADC_CalibrationInit();
+ * \endcode
+ */
+bool ADC_CalibrationInit(void);
+
+/**
+ * adc_lib.h
+ * \brief       Obtain the actual voltage value.
+ * \param[in]   vSampleMode: ADC operation mode.
+ * \param[in]   vSampleData: ADC sample data.
+ * \param[in]   pErrorStatus: This parameter can be a value of ADC_ErrorStatus.
+ * \return      actual voltage value.
+ */
+float ADC_GetVoltage(const ADC_SampleMode vSampleMode, int32_t vSampleData,
+                     ADC_ErrorStatus *pErrorStatus);
+
+/**
+ * adc_lib.h
+ * \brief       Obtain the actual resistance value.
+ * \param[in]   None.
+ * \return      resistance value.
+ */
+uint16_t ADC_GetResistance(void);
+
+/** End of ADC_Exported_Functions
+  * \}
+  */
+
+/** End of ADC
+  * \}
+  */
+
+#endif /* __ADC_K_LIB_H */
+
+
+/******************* (C) COPYRIGHT 2024 Realtek Semiconductor *****END OF FILE****/
diff --git a/bee/drivers/adc/src/device/rtl8752h/rtl876x_adc.c b/bee/drivers/adc/src/device/rtl8752h/rtl876x_adc.c
new file mode 100644
index 00000000..3e220063
--- /dev/null
+++ b/bee/drivers/adc/src/device/rtl8752h/rtl876x_adc.c
@@ -0,0 +1,689 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "rtl876x_rcc.h"
+#include "rtl876x_adc.h"
+#include "app_section.h"
+
+#define EFUSE_ON_RAM_BASE             0x00200f81UL
+#define EFUSE_FT_VER_OFFSET              0x1C8
+
+extern void SystemCall(uint32_t opcode, uint32_t parm);
+extern volatile void (*platform_delay_ms)(uint32_t t);
+
+/**
+  * @brief  Deinitializes the ADC peripheral registers to their default reset values(turn off ADC clock).
+  *
+  * @param  ADCx: selected ADC peripheral.
+  * @return None.
+  */
+void ADC_DeInit(ADC_TypeDef *ADCx)
+{
+    assert_param(IS_ADC_PERIPH(ADCx));
+
+    /* ADC PowerOff */
+    SystemCall(0x0A, DISABLE);
+
+    RCC_PeriphClockCmd(APBPeriph_ADC, APBPeriph_ADC_CLOCK, DISABLE);
+
+    return;
+}
+
+/**
+  * @brief  Initializes the ADC peripheral according to the specified
+  *         parameters in the ADC_InitStruct
+  * @param  ADCx: selected ADC peripheral.
+  * @param  ADC_InitStruct: pointer to a ADCInitTypeDef structure that
+  *         contains the configuration information for the specified ADC peripheral
+  * @return None.
+  */
+void ADC_Init(ADC_TypeDef *ADCx, ADC_InitTypeDef *ADC_InitStruct)
+{
+    assert_param(IS_ADC_PERIPH(ADCx));
+    assert_param(IS_ADC_DATA_WRITE_TO_FIFO_CMD(ADC_InitStruct->ADC_DataWriteToFifo));
+    assert_param(IS_ADC_FIFO_THRESHOLD(ADC_InitStruct->ADC_FifoThdLevel));
+    assert_param(IS_ADC_WATER_LEVEL_CONFIG(ADC_InitStruct->ADC_WaterLevel));
+    assert_param(IS_ADC_OVERWRITE_MODE(ADC_InitStruct->ADC_FifoOverWriteEn));
+    assert_param(IS_ADC_LATCH_DATA_EDGE(ADC_InitStruct->ADC_DataLatchEdge));
+    assert_param(IS_ADC_DATA_AVG_NUM(ADC_InitStruct->ADC_DataAvgSel));
+    assert_param(IS_ADC_DATA_AVG_EN(ADC_InitStruct->ADC_DataAvgEn));
+    assert_param(IS_ADC_POWER_ON_MODE(ADC_InitStruct->ADC_PowerOnMode));
+    assert_param(IS_ADC_RG2X_0_DELAY_TIME(ADC_InitStruct->ADC_RG2X0Dly));
+    assert_param(IS_ADC_RG0X_1_DELAY_TIME(ADC_InitStruct->ADC_RG0X1Dly));
+    assert_param(IS_ADC_RG0X_0_DELAY_TIME(ADC_InitStruct->ADC_RG0X0Dly));
+    assert_param(IS_ADC_DATA_MINUS_CMD(ADC_InitStruct->ADC_DataMinusEn));
+    assert_param(IS_ADC_DATA_ALIGN(ADC_InitStruct->ADC_DataAlign));
+    assert_param(IS_ADC_TIMER_TRIGGER_CMD(ADC_InitStruct->ADC_TimerTriggerEn));
+    assert_param(IS_ADC_POWER_ALWAYS_ON(ADC_InitStruct->ADC_PowerAlwaysOnEn));
+    assert_param(IS_ADC_CONVERT_TIME(ADC_InitStruct->ADC_ConvertTime));
+
+#if ADC_UNSUPPORT_P2_6
+    for (uint8_t index = 0; index < MAX_ADC_SCH_NUM; index++)
+    {
+        ASSERT(IS_SCHEDULE_TABLE(ADC_InitStruct->ADC_SchIndex[index]));
+    }
+#endif
+
+#if 1
+
+    /* Added to stabilize the power supply! */
+    uint16_t reg_value = 0;
+
+    /* ref=1.05V */
+    reg_value = btaon_fast_read_safe(0x116);
+    btaon_fast_write(0x116, reg_value | BIT(4) | BIT(5));
+
+    /* enable cmp low noise for 3 bit */
+    reg_value = btaon_fast_read_safe(0x116);
+    btaon_fast_write(0x116, reg_value | BIT(10));
+
+#endif
+
+    if (*((volatile uint8_t *)(EFUSE_ON_RAM_BASE + EFUSE_FT_VER_OFFSET)) >=  0x02)
+    {
+        reg_value = btaon_fast_read_safe(0x116);
+        reg_value |= BIT12;
+        reg_value &= ~BIT13;
+        btaon_fast_write(0x116, reg_value);
+
+        reg_value = btaon_fast_read_safe(0x110);
+        reg_value |= BIT12 | BIT13 | BIT15;
+        reg_value &= ~BIT14;
+        btaon_fast_write(0x110, reg_value);
+    }
+
+    /*Disable all interrupt.*/
+    ADCx->INTCR &= (~0x3f);
+
+    if (ADC_InitStruct->ADC_PowerOnMode == ADC_POWER_ON_AUTO)
+    {
+        ADCx->PWRDLY |= (ADC_InitStruct->ADC_RG2X0Dly \
+                         | ADC_InitStruct->ADC_RG0X1Dly \
+                         | ADC_InitStruct->ADC_RG0X0Dly);
+    }
+
+    /* hw_pd of LDO, for low leakage purpose */
+    SystemCall(0x0A, ENABLE);
+
+    /* Set power mode first */
+    ADCx->PWRDLY |= (((ADC_InitStruct->ADC_DataLatchDly & 0x7) << 6)  |
+                     ADC_InitStruct->ADC_PowerOnMode);
+
+    ADCx->PWRDLY |= ADC_InitStruct->ADC_PowerAlwaysOnEn;
+
+    if (ADC_InitStruct->ADC_PowerOnDlyEn == ENABLE &&
+        ADC_InitStruct->ADC_PowerAlwaysOnEn == ADC_POWER_ALWAYS_ON_ENABLE)
+    {
+        /* After the ADC is powered up, there is a re-settle time of about 8ms,
+        during which the voltage acquired by the ADC has an error of about 0-10mV higher.
+        This error can be avoided by turning on this delay.
+        This delay is only effective when ADC_PowerAlwaysOnEn is set to ENABLE. */
+        platform_delay_ms(8);
+    }
+
+    if (ADC_InitStruct->ADC_DataAvgEn == ADC_DATA_AVERAGE_ENABLE)
+    {
+        ADCx->PWRDLY |= (ADC_InitStruct->ADC_DataAvgEn | ADC_InitStruct->ADC_DataAvgSel);
+        /* Disable schedule table */
+        ADCx->SCHCR &= (~0xffff);
+        /* Set schedule table */
+        ADCx->SCHTAB0 = ADC_InitStruct->ADC_SchIndex[0];
+        ADCx->SCHCR |= (uint16_t)0x0001;
+    }
+    else
+    {
+        /* Disable schedule table */
+        ADCx->SCHCR &= (~0xffff);
+
+        /* Set schedule table */
+        for (uint8_t index = 0; index < MAX_ADC_SCH_NUM; index++)
+        {
+            *(__IO uint32_t *)((uint32_t *)(&ADCx->SCHTAB0) + index) = ((ADC_InitStruct->ADC_SchIndex[index * 2]
+                                                                         & 0x1F)
+                                                                        | ((ADC_InitStruct->ADC_SchIndex[index * 2 + 1] & 0x1F) << 16));
+        }
+        ADCx->SCHCR = ADC_InitStruct->ADC_Bitmap;
+    }
+
+    /* Set ADC mode */
+    ADCx->CR = ((ADC_InitStruct->ADC_DataWriteToFifo)
+                | ((ADC_InitStruct->ADC_FifoThdLevel & 0x3F) << 20)
+                | ((ADC_InitStruct->ADC_WaterLevel & 0x3F) << 14)
+                | (ADC_InitStruct->ADC_FifoOverWriteEn)
+                | (ADC_InitStruct->ADC_DataLatchEdge));
+
+    ADCx->DATCLK = ((ADC_InitStruct->ADC_DataMinusEn)
+                    | (ADC_InitStruct->ADC_DataAlign)
+                    | (ADC_InitStruct->ADC_TimerTriggerEn)
+                    | ((ADC_InitStruct->ADC_DataMinusOffset & 0xFFF) << 16));
+
+    ADCx->ANACTL |= (0x03 << 10);
+
+    ADCx->SAMTIM = ((ADC_InitStruct->ADC_ConvertTime)
+                    | (ADC_InitStruct->ADC_SampleTime & 0x3FFF));
+
+    /*clear adc fifo*/
+    ADCx->CR |= BIT26;
+
+    /*clear all interrupt*/
+    ADCx->INTCR |= (0x3f << 8);
+
+    return;
+}
+
+/**
+  * @brief  Fills each ADC_InitStruct member with its default value.
+  * @param  ADC_InitStruct: pointer to an ADC_InitTypeDef structure which will be initialized.
+  * @retval None
+  */
+void ADC_StructInit(ADC_InitTypeDef *ADC_InitStruct)
+{
+    ADC_InitStruct->ADC_SampleTime      = 255;  /* (n + 1) cycle of 10MHz, n = 0~16383 */
+    ADC_InitStruct->ADC_ConvertTime     = ADC_CONVERT_TIME_500NS;
+
+    ADC_InitStruct->ADC_DataWriteToFifo = ADC_DATA_WRITE_TO_FIFO_DISABLE;
+    ADC_InitStruct->ADC_FifoThdLevel    = 0x0A;
+    ADC_InitStruct->ADC_WaterLevel      = 0x1;
+    ADC_InitStruct->ADC_FifoOverWriteEn = ADC_FIFO_OVER_WRITE_ENABLE;
+    ADC_InitStruct->ADC_DataLatchEdge   = ADC_LATCH_DATA_Positive;
+
+    ADC_InitStruct->ADC_SchIndex[0]     = 0;
+    ADC_InitStruct->ADC_SchIndex[1]     = 0;
+    ADC_InitStruct->ADC_SchIndex[2]     = 0;
+    ADC_InitStruct->ADC_SchIndex[3]     = 0;
+    ADC_InitStruct->ADC_SchIndex[4]     = 0;
+    ADC_InitStruct->ADC_SchIndex[5]     = 0;
+    ADC_InitStruct->ADC_SchIndex[6]     = 0;
+    ADC_InitStruct->ADC_SchIndex[7]     = 0;
+    ADC_InitStruct->ADC_SchIndex[8]     = 0;
+    ADC_InitStruct->ADC_SchIndex[9]     = 0;
+    ADC_InitStruct->ADC_SchIndex[10]    = 0;
+    ADC_InitStruct->ADC_SchIndex[11]    = 0;
+    ADC_InitStruct->ADC_SchIndex[12]    = 0;
+    ADC_InitStruct->ADC_SchIndex[13]    = 0;
+    ADC_InitStruct->ADC_SchIndex[14]    = 0;
+    ADC_InitStruct->ADC_SchIndex[15]    = 0;
+    ADC_InitStruct->ADC_Bitmap          = 0x0;
+
+    ADC_InitStruct->ADC_TimerTriggerEn  = ADC_TIMER_TRIGGER_DISABLE;
+    ADC_InitStruct->ADC_DataAlign       = ADC_DATA_ALIGN_LSB;
+    ADC_InitStruct->ADC_DataMinusEn     = ADC_DATA_MINUS_DISABLE;
+    ADC_InitStruct->ADC_DataMinusOffset = 0;
+
+    ADC_InitStruct->ADC_DataAvgEn       = ADC_DATA_AVERAGE_DISABLE;
+    ADC_InitStruct->ADC_DataAvgSel      = ADC_DATA_AVERAGE_OF_2;
+    /* Reserved parameter, please do not change values*/
+    ADC_InitStruct->ADC_PowerOnMode     = ADC_POWER_ON_AUTO;
+    ADC_InitStruct->ADC_PowerAlwaysOnEn = ADC_POWER_ALWAYS_ON_ENABLE;
+    ADC_InitStruct->ADC_DataLatchDly    = 0x1;
+    ADC_InitStruct->ADC_RG2X0Dly        = ADC_RG2X_0_DELAY_40_US;
+    ADC_InitStruct->ADC_RG0X1Dly        = ADC_RG0X_1_DELAY_40_US;
+    ADC_InitStruct->ADC_RG0X0Dly        = ADC_RG0X_0_DELAY_30_US;
+    ADC_InitStruct->ADC_PowerOnDlyEn    = DISABLE;
+
+    return;
+}
+
+/**
+  * @brief  Enables or disables the ADC peripheral.
+  * @param  ADCx: selected ADC peripheral.
+  * @param  adcMode: adc mode select.
+        This parameter can be one of the following values:
+  *     @arg ADC_ONE_SHOT_MODE: one shot mode.
+  *     @arg ADC_CONTINUOUS_MODE: continuous mode.
+  * @param  NewState: new state of the ADC peripheral.
+  *     This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ADC_Cmd(ADC_TypeDef *ADCx, uint8_t adcMode, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_ADC_PERIPH(ADCx));
+    assert_param(IS_ADC_SAMPLE_MODE(adcMode));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (NewState == ENABLE)
+    {
+        /* In case manual mode */
+        if (ADCx->PWRDLY  & ADC_POWER_ON_MANUAL)
+        {
+//            ADCx->PWRDLY  |= 0x3C00;
+////            ADC_DelayUs(80);
+//            platform_delay_us(80);
+//            ADCx->PWRDLY  |= (BIT14 | BIT15);
+////            ADC_DelayUs(320);
+//            platform_delay_us(320);
+//            ADCx->PWRDLY  |= (BIT16 | BIT17);
+////            ADC_DelayUs(240);
+//            platform_delay_us(240);
+//            ADCx->PWRDLY  |= BIT18;
+        }
+        /* Reset ADC mode first */
+        ADCx->CR &= ~0x03;
+        /* Enable ADC */
+        ADCx->CR |= adcMode;
+    }
+    else
+    {
+        ADCx->CR &= ~0x03;
+    }
+
+    return;
+}
+
+/**
+  * @brief  Enables or disables the specified ADC interrupts.
+  * @param  ADCx: selected ADC peripheral.
+  * @param  ADC_INT: specifies the ADC interrupts sources to be enabled or disabled.
+  *         This parameter can be any combination of the following values:
+  *         @arg ADC_INT_FIFO_RD_REQ :ADC FIFO size>=burst size interrupt.
+  *         @arg ADC_INT_FIFO_RD_ERR :ADC FIFO underflow interrupt.
+  *         @arg ADC_INT_FIFO_THD :ADC FIFO size > thd interrupt.
+  *         @arg ADC_INT_FIFO_FULL :ADC FIFO overflow interrupt.
+  *         @arg ADC_INT_ONE_SHOT_DONE :ADC one shot mode done interrupt.
+  * @param  NewState: new state of the specified ADC interrupts.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ADC_INTConfig(ADC_TypeDef *ADCx, uint32_t ADC_INT, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_ADC_PERIPH(ADCx));
+    assert_param(IS_ADC_INT(ADC_INT));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (NewState != DISABLE)
+    {
+        /* Enable the selected ADC interrupts */
+        ADCx->INTCR |= ADC_INT;
+    }
+    else
+    {
+        /* Disable the selected ADC interrupts */
+        ADCx->INTCR &= (uint32_t)~ADC_INT;
+    }
+}
+
+/**
+  * @brief  Read ADC data according to specific channel.
+  * @param  ADCx: selected ADC peripheral.
+  * @param  index: can be 0 to 15
+  * @retval The 10-bit converted ADC data.
+  */
+uint16_t ADC_ReadRawData(ADC_TypeDef *ADCx, uint8_t index)
+{
+    /* Check the parameters */
+    assert_param(IS_ADC_PERIPH(ADCx));
+    assert_param(index < 16);
+
+    if (index & BIT(0))
+    {
+        return ((*(uint32_t *)((uint32_t *)(&ADCx->SCHD0) + (index >> 1))) >> 16);
+    }
+    else
+    {
+        return (*(uint32_t *)((uint32_t *)(&ADCx->SCHD0) + (index >> 1)));
+    }
+}
+
+/**
+  * @brief  Read ADC average data from ADC schedule table0.
+  * @param  ADCx: selected ADC peripheral.
+  * @param[out]  OutBuf: buffer to save data read from ADC FIFO.
+  * @retval The The 10bits integer data + 2bits fractional ADC raw data.
+  */
+uint16_t ADC_ReadAvgRawData(ADC_TypeDef *ADCx)
+{
+    /* Check the parameters */
+    assert_param(IS_ADC_PERIPH(ADCx));
+
+    uint16_t data = 0;
+    data = (uint16_t)ADCx->SCHD0;
+
+    return data;
+}
+
+/**
+  * @brief  Get raw data from ADC FIFO.
+  * @param  ADCx: selected ADC peripheral.
+  * @retval adc FIFO data.
+  */
+uint16_t ADC_ReadFIFO(ADC_TypeDef *ADCx)
+{
+    /* Check the parameters */
+    assert_param(IS_ADC_PERIPH(ADCx));
+
+    return (uint16_t)((ADCx->FIFO) & 0xFFF);
+}
+
+/**
+  * @brief  Read data from ADC FIFO.
+  * @param  ADCx: selected ADC peripheral.
+  * @param[out]  outBuf: buffer to save data read from ADC FIFO.
+  * @param  num: number of data to be read.
+  * @retval None
+  */
+void ADC_ReadFIFOData(ADC_TypeDef *ADCx, uint16_t *outBuf, uint16_t num)
+{
+    /* Check the parameters */
+    assert_param(IS_ADC_PERIPH(ADCx));
+
+    while (num--)
+    {
+        *outBuf++ = (uint16_t)ADCx->FIFO;
+    }
+
+    return;
+}
+
+/**
+  * @brief  Get ADC fifo data number.
+  * @param  ADCx: selected ADC peripheral.
+  * @retval current data number in adc fifo.
+  */
+uint8_t ADC_GetFIFODataLen(ADC_TypeDef *ADCx)
+{
+    /* Check the parameters */
+    assert_param(IS_ADC_PERIPH(ADCx));
+
+    return ((uint8_t)(((ADCx->SCHCR) >> 16) & 0x3F));
+}
+
+/**
+  * @brief  Config ADC schedule table.
+  * @param  ADCx: selected ADC peripheral.
+  * @param  adcMode: ADC mode.
+  *     This parameter can be one of the following values:
+  *     @arg EXT_SINGLE_ENDED(index)
+  *     @arg EXT_DIFFERENTIAL(index)
+  *     @arg INTERNAL_VBAT_MODE
+  * @param  Index: Schedule table index.
+  * @return none.
+  */
+void ADC_SchIndexConfig(ADC_TypeDef *ADCx, uint8_t adcMode, uint16_t index)
+{
+    /* Check the parameters */
+    assert_param(IS_ADC_PERIPH(ADCx));
+    assert_param(IS_ADC_SCHEDULE_INDEX_CONFIG(adcMode));
+
+    if (index & BIT0)
+    {
+        *(uint32_t *)((uint32_t *)(&ADCx->SCHTAB0) + (index >> 1)) |= (adcMode << 16);
+    }
+    else
+    {
+        *(uint32_t *)((uint32_t *)(&ADCx->SCHTAB0) + (index >> 1)) |= adcMode;
+    }
+
+    return;
+}
+
+/**
+  * @brief  Same as function ADC_SchIndexConfig,this function is version RTL8762C.
+  * @param  ADCx: selected ADC peripheral.
+  * @param  adcMode: ADC mode.
+  *     This parameter can be one of the following values:
+  *     @arg EXT_SINGLE_ENDED(index)
+  *     @arg EXT_DIFFERENTIAL(index)
+  *     @arg INTERNAL_VBAT_MODE
+  * @param  Index: Schedule table index.
+  * @return none.
+  */
+void ADC_SchTableConfig(ADC_TypeDef *ADCx, uint16_t Index, uint8_t adcMode)
+{
+    /* Check the parameters */
+    assert_param(IS_ADC_PERIPH(ADCx));
+    assert_param(IS_ADC_SCHEDULE_INDEX_CONFIG(adcMode));
+
+    if (Index & BIT0)
+    {
+        *(uint32_t *)((uint32_t *)(&ADCx->SCHTAB0) + (Index >> 1)) |= (adcMode << 16);
+    }
+    else
+    {
+        *(uint32_t *)((uint32_t *)(&ADCx->SCHTAB0) + (Index >> 1)) |= adcMode;
+    }
+
+    return;
+}
+
+/**
+  * @brief  Set adc schedule table.
+  * @param  ADCx: selected ADC peripheral.
+  * @param  channelMap: ADC channel map.
+  * @param  NewState: new state of the ADC peripheral.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @return none.
+  */
+void ADC_BitMapConfig(ADC_TypeDef *ADCx, uint16_t bitMap)
+{
+    /* Check the parameters */
+    assert_param(IS_ADC_PERIPH(ADCx));
+
+    ADCx->SCHCR = bitMap;
+
+    return;
+}
+
+/**
+  * @brief  Power on ADC manually.
+  * @param  ADCx: selected ADC peripheral.
+  * @param  NewState: new state of the ADC power on.
+  *     This parameter can be: ENABLE or DISABLE.
+  *     @note If enable, ADC power will always on.
+  * @retval None
+  */
+void ADC_ManualPowerOnCmd(ADC_TypeDef *ADCx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_ADC_PERIPH(ADCx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (NewState != DISABLE)
+    {
+        ADCx->PWRDLY |= BIT19;
+    }
+    else
+    {
+        ADCx->PWRDLY &= ~(BIT19);
+    }
+}
+
+/**
+  * @brief  Enbale or disable stop fifo from writing data.
+  * @param  ADCx: selected ADC peripheral.
+  * @param  NewState: new state of the ADC fifo write.
+  *     This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ADC_WriteFIFOCmd(ADC_TypeDef *ADCx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_ADC_PERIPH(ADCx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (NewState == DISABLE)
+    {
+        ADCx->PWRDLY |= BIT21;
+    }
+    else
+    {
+        ADCx->PWRDLY &= ~(BIT21);
+    }
+}
+
+/**
+  * @brief  Config ADC bypass resistor.Attention!!!Channels using bypass mode cannot over 0.9V!!!!
+  * @param  channelNum: external channel number, can be 0~7.
+  * @param  NewState: ENABLE or DISABLE.
+  * @retval None
+  */
+void ADC_BypassCmd(uint8_t ChannelNum, FunctionalState NewState)
+{
+    assert_param(ChannelNum <= 3);
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    uint16_t reg_value = 0;
+
+    if (NewState != DISABLE)
+    {
+        reg_value = btaon_fast_read_safe(0x118);
+        reg_value |= BIT(ChannelNum);
+        btaon_fast_write(0x118, reg_value);
+    }
+    else
+    {
+        reg_value = btaon_fast_read_safe(0x118);
+        reg_value &= ~BIT(ChannelNum);
+        btaon_fast_write(0x118, reg_value);
+    }
+}
+
+/**
+  * @brief  Checks whether the specified ADC interrupt status flag is set or not.
+  * @param  ADCx: selected ADC peripheral.
+  * @param  ADC_INT_FLAG: specifies the interrupt status flag to check.
+  *     This parameter can be one of the following values:
+  *     @arg ADC_INT_FIFO_OVERFLOW: ADC FIFO overflow interrupt.
+  *     @arg ADC_INT_ONE_SHOT_DONE: ADC once convert end interrupt.
+  *     @arg ADC_INT_FIFO_FULL: ADC FIFO full interrupt.
+  *     @arg ADC_INT_FIFO_THD: fifo larger than threshold interrupt.
+  *     @arg ADC_INT_FIFO_RD_ERR: ADC FIFO underflow interrupt.
+  *     @arg ADC_INT_FIFO_RD_REQ: ADC FIFO size>=burst size interrupt.
+  * @retval The new state of ADC_INT (SET or RESET).
+  */
+ITStatus ADC_GetINTStatus(ADC_TypeDef *ADCx, uint32_t ADC_INT)
+{
+    /* Check the parameters */
+    assert_param(IS_ADC_PERIPH(ADCx));
+    assert_param(IS_ADC_INT(ADC_INT));
+
+    FlagStatus bitstatus = RESET;
+
+    if ((ADCx->INTCR & (ADC_INT << 16)) != 0)
+    {
+        bitstatus = SET;
+    }
+
+    return bitstatus;
+}
+
+/**
+  * @brief  Clear the ADC interrupt pending bit.
+  * @param  ADCx: selected ADC peripheral.
+  * @param  ADC_INT: specifies the interrupt pending bit to clear.
+  *     This parameter can be any combination of the following values:
+  *     @arg ADC_INT_FIFO_OVERFLOW: ADC FIFO overflow interrupt.
+  *     @arg ADC_INT_ONE_SHOT_DONE: ADC once convert end interrupt.
+  *     @arg ADC_INT_FIFO_FULL: ADC FIFO full interrupt.
+  *     @arg ADC_INT_FIFO_THD: fifo larger than threshold interrupt.
+  *     @arg ADC_INT_FIFO_RD_ERR: ADC FIFO underflow interrupt.
+  *     @arg ADC_INT_FIFO_RD_REQ: ADC FIFO size>=burst size interrupt.
+  * @retval None
+  */
+void ADC_ClearINTPendingBit(ADC_TypeDef *ADCx, uint32_t ADC_INT)
+{
+    /* Check the parameters */
+    assert_param(IS_ADC_PERIPH(ADCx));
+    assert_param(IS_ADC_INT(ADC_INT));
+
+    ADCx->INTCR |= (ADC_INT << 8);
+
+    return;
+}
+
+
+/**
+  * \brief  Store ADC register values when system enter DLPS.
+  * \param  PeriReg: Specifies to select the ADC peripheral.
+  * \param  StoreBuf: Store buffer to store ADC register data.
+  * \return None.
+  */
+DATA_RAM_FUNCTION
+void ADC_DLPSEnter(void *PeriReg, void *StoreBuf)
+{
+    ADCStoreReg_TypeDef *store_buf = (ADCStoreReg_TypeDef *)StoreBuf;
+
+    /*Open 10M clock source*/
+    SYSBLKCTRL->u_20C.PERION_REG_SYS_CLK_SEL_2 |= BIT26;
+    SYSBLKCTRL->u_20C.PERION_REG_SYS_CLK_SEL_2 |= BIT28;
+
+    RCC_PeriphClockCmd(APBPeriph_ADC, APBPeriph_ADC_CLOCK, ENABLE);
+
+    store_buf->adc_reg[0]        = ADC->CR;          //0x04
+    store_buf->adc_reg[1]        = ADC->SCHCR;       //0x08
+    store_buf->adc_reg[2]        = ADC->INTCR;       //0x0C
+    store_buf->adc_schtab_reg[0] = ADC->SCHTAB0;     //0x10
+    store_buf->adc_schtab_reg[1] = ADC->SCHTAB1;     //0x14
+    store_buf->adc_schtab_reg[2] = ADC->SCHTAB2;     //0x18
+    store_buf->adc_schtab_reg[3] = ADC->SCHTAB3;     //0x1C
+    store_buf->adc_schtab_reg[4] = ADC->SCHTAB4;     //0x20
+    store_buf->adc_schtab_reg[5] = ADC->SCHTAB5;     //0x24
+    store_buf->adc_schtab_reg[6] = ADC->SCHTAB6;     //0x28
+    store_buf->adc_schtab_reg[7] = ADC->SCHTAB7;     //0x2C
+    store_buf->adc_reg[3]        = ADC->PWRDLY;
+    store_buf->adc_reg[4]        = ADC->DATCLK;
+    store_buf->adc_reg[5]        = ADC->ANACTL;
+    store_buf->adc_reg[6]        = ADC->SAMTIM;
+    store_buf->aon_reg[0]        = btaon_fast_read_safe(0x110);
+
+    return;
+}
+
+/**
+  * \brief  Restore ADC register values when system exit DLPS.
+  * \param  PeriReg: Specifies to select the ADC peripheral.
+  * \param  StoreBuf: Restore buffer to restore ADC register data.
+  * \return None
+  */
+DATA_RAM_FUNCTION
+void ADC_DLPSExit(void *PeriReg, void *StoreBuf)
+{
+    ADCStoreReg_TypeDef *store_buf = (ADCStoreReg_TypeDef *)StoreBuf;
+
+    /*Open 10M clock source*/
+    SYSBLKCTRL->u_20C.PERION_REG_SYS_CLK_SEL_2 |= BIT26;
+    SYSBLKCTRL->u_20C.PERION_REG_SYS_CLK_SEL_2 |= BIT28;
+
+    RCC_PeriphClockCmd(APBPeriph_ADC, APBPeriph_ADC_CLOCK, ENABLE);
+
+    /*Disable all interrupt.*/
+    ADC->INTCR &= (~0x1f);
+
+    /* Set power mode first */
+    ADC->PWRDLY = store_buf->adc_reg[3];
+
+    /* Disable schedule table */
+    ADC->SCHCR &= (~0xffff);
+
+    ADC->SCHTAB0 = store_buf->adc_schtab_reg[0];
+    ADC->SCHTAB1 = store_buf->adc_schtab_reg[1];
+    ADC->SCHTAB2 = store_buf->adc_schtab_reg[2];
+    ADC->SCHTAB3 = store_buf->adc_schtab_reg[3];
+    ADC->SCHTAB4 = store_buf->adc_schtab_reg[4];
+    ADC->SCHTAB5 = store_buf->adc_schtab_reg[5];
+    ADC->SCHTAB6 = store_buf->adc_schtab_reg[6];
+    ADC->SCHTAB7 = store_buf->adc_schtab_reg[7];
+    ADC->SCHCR   = store_buf->adc_reg[1];
+    ADC->CR = (store_buf->adc_reg[0] & (~((uint32_t)0x03)));
+    ADC->DATCLK  = store_buf->adc_reg[4];
+    ADC->ANACTL  = store_buf->adc_reg[5];
+    ADC->SAMTIM  = store_buf->adc_reg[6];
+
+    /*Clear ADC FIFO */
+    ADC->CR |= BIT26;
+    /* Clear all interrupt */
+    ADC->INTCR |= (0x1f << 8);
+
+    /* Restore specify interrupt */
+    ADC->INTCR = store_buf->adc_reg[2];
+
+    btaon_fast_write(0x110, store_buf->aon_reg[0]);
+
+    return;
+}
+
+
diff --git a/bee/drivers/adc/src/device/rtl8752h/rtl876x_adc.h b/bee/drivers/adc/src/device/rtl8752h/rtl876x_adc.h
new file mode 100644
index 00000000..25764af5
--- /dev/null
+++ b/bee/drivers/adc/src/device/rtl8752h/rtl876x_adc.h
@@ -0,0 +1,999 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _RTL876X_ADC_H_
+#define _RTL876X_ADC_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup  IO          Peripheral Drivers
+ * \defgroup    ADC         ADC
+ *
+ * \brief       Manage the ADC peripheral functions.
+ *
+ * \ingroup     IO
+ */
+
+/*============================================================================*
+ *                         Includes
+ *============================================================================*/
+#include "rtl876x.h"
+#include "rtl876x_alias.h"
+#include "adc_lib.h"
+#include "trace.h"
+
+/*============================================================================*
+ *                         Types
+ *============================================================================*/
+#define ADC_UNSUPPORT_P2_6              0x1
+
+#if ADC_UNSUPPORT_P2_6
+#define ASSERT(e) \
+    do { \
+        if(!(e)) { \
+            DBG_DIRECT("(" #e ") assert failed! Func: %s. Line: %d.", __func__, __LINE__); \
+            DBG_DIRECT("(" #e ") assert failed! Func: %s. Line: %d.", __func__, __LINE__); \
+            *(volatile int *)0x1 = 0; \
+        } \
+    } while(0)
+#else
+#define ASSERT(e) ((void)0)
+#endif // NDEBUG
+/**
+ * \defgroup    ADC_Exported_Types  ADC Exported Types
+ * \{
+ * \ingroup     ADC
+ */
+
+/**
+ * \brief       ADC init structure definition.
+ *
+ * \ingroup     ADC_Exported_Types
+ */
+typedef struct
+{
+    uint32_t ADC_SampleTime;        /**< Specify the ADC sample clock, adc_sample_period = (n+1) cycles from 10MHz.
+                                            This parameter can be a value of 19 to 16383. */
+    uint32_t ADC_ConvertTime;       /**< Specify the ADC Sample convert time.
+                                            This parameter can be a value of \ref ADC_Convert_Time. */
+    uint32_t ADC_DataWriteToFifo;   /**< Enable or disable writing ADC sampling data to FIFO in one shot mode.
+                                            This parameter can be a value of \ref ADC_Data_Write_To_FIFO. */
+    uint32_t ADC_FifoThdLevel;      /**< Specify the ADC FIFO threshold to trigger \ref ADC_INT_FIFO_THD interrupt.
+                                            This parameter can be a value of 0 to 31. */
+    uint32_t ADC_WaterLevel;        /**< Specify the ADC FIFO burst size to trigger GDMA.
+                                            This parameter can be a value of 0 to 31. */
+    uint32_t ADC_FifoOverWriteEn;   /**< Specify if over write FIFO when FIFO overflow.
+                                            This parameter can be a value of \ref ADC_Over_Write_Enable. */
+    uint32_t ADC_DataLatchEdge;     /**< Specify ADC data latch edge.
+                                            This parameter can be a value of \ref ADC_Latch_Data_Edge. */
+    uint16_t ADC_SchIndex[16];      /**< Specify ADC mode and channel for schedule table.
+                                            This parameter can be a value of \ref ADC_Schedule_Table. */
+    uint16_t ADC_Bitmap;            /**< Specify the schedule table channel map.
+                                            This parameter can be a value of 16-bit map. */
+    uint32_t ADC_TimerTriggerEn;    /**< Enable ADC one-shot mode when tim7 toggles. */
+    uint32_t ADC_DataAlign;         /**< ADC data MSB or LSB aligned. */
+    uint32_t ADC_DataMinusEn;       /**< Enable or disable function that adc data latched minus the given offset before writes to reg or FIFO. */
+    uint32_t ADC_DataMinusOffset;   /**< Offset to be minused from adc data latched. */
+    uint32_t ADC_DataAvgSel;        /**< Number of data for calculate average.
+                                            This parameter can be a value of \ref ADC_Data_Avg_Num. */
+    uint32_t ADC_DataAvgEn;         /**< Enable the calculation for average result of the one-shot data.
+                                            This parameter can be a value of \ref ADC_Data_Avg_En. */
+    uint32_t ADC_PowerOnMode;       /**< Specify ADC power on mode.
+                                            This parameter can be a value of \ref ADC_Power_On_Mode. */
+    uint32_t ADC_PowerAlwaysOnEn;   /**< Specify the power always on.
+                                            This parameter can be a value of \ref ADC_Power_Always_On_Cmd. */
+    uint32_t ADC_DataLatchDly;      /**< Specify delay of ck_ad to latch data.*/
+    uint32_t ADC_RG2X0Dly;          /**< Specify the power on delay time selection of RG2X_AUXADC[0].
+                                            This parameter can be a value of \ref ADC_RG2X_0_Delay_Time */
+    uint32_t ADC_RG0X1Dly;          /**< Specify the power on delay time selection of RG0X_AUXADC[1].
+                                            This parameter can be a value of \ref ADC_RG0X_1_Delay_Time */
+    uint32_t ADC_RG0X0Dly;          /**< Specify the power on delay time selection of RG0X_AUXADC[0].
+                                            This parameter can be a value of \ref ADC_RG0X_0_Delay_Time */
+    uint32_t ADC_PowerOnDlyEn;      /**< Enable or Disable ADC 8ms delay after adc power on. */
+} ADC_InitTypeDef;
+
+/** End of ADC_Exported_Types
+  * \}
+  */
+
+/*============================================================================*
+ *                         Constants
+ *============================================================================*/
+/**
+ * \defgroup    ADC_Exported_Constants  ADC Exported Constants
+ *
+ * \ingroup     ADC
+ */
+
+/**
+ * \defgroup    ADC_Config  ADC Config
+ * \{
+ * \ingroup     ADC_Exported_Constants
+ */
+#define ADC_FIFO_LENGTH   32
+
+#define ADC_FIFO_WIDTH    16
+
+#define MAX_ADC_SCH_NUM             8
+
+#define IS_ADC_PERIPH(PERIPH) ((PERIPH) == ADC)
+/** \} */
+
+/**
+ * \defgroup    ADC_Data_Write_To_FIFO  ADC Data Write To FIFO
+ * \{
+ * \ingroup     ADC_Exported_Constants
+ */
+#define ADC_DATA_WRITE_TO_FIFO_DISABLE              ((uint32_t)(0 << 27))
+#define ADC_DATA_WRITE_TO_FIFO_ENABLE               ((uint32_t)(1 << 27))
+
+#define IS_ADC_DATA_WRITE_TO_FIFO_CMD(CMD) (((CMD) == ADC_DATA_WRITE_TO_FIFO_DISABLE) || ((CMD) == ADC_DATA_WRITE_TO_FIFO_ENABLE))
+/** \} */
+
+/**
+ * \defgroup    ADC_FIFO_Threshold  ADC FIFO Threshold
+ * \{
+ * \ingroup     ADC_Exported_Constants
+ */
+#define IS_ADC_FIFO_THRESHOLD(THD) ((THD) <= 0x3F)
+/** \} */
+
+/**
+ * \defgroup    ADC_Burst_Size  ADC Burst Size
+ * \{
+ * \ingroup     ADC_Exported_Constants
+ */
+#define IS_ADC_WATER_LEVEL_CONFIG(CONFIG) ((CONFIG) <= 0x3F)
+/** \} */
+
+/**
+ * \defgroup    ADC_Over_Write_Enable ADC FIFO Over Write
+ * \{
+ * \ingroup     ADC_Exported_Constants
+ */
+#define ADC_FIFO_OVER_WRITE_DISABLE                 ((uint32_t)(0 << 13))
+#define ADC_FIFO_OVER_WRITE_ENABLE                  ((uint32_t)(1 << 13))
+
+#define IS_ADC_OVERWRITE_MODE(MODE) (((MODE) == ADC_FIFO_OVER_WRITE_DISABLE) || ((MODE) == ADC_FIFO_OVER_WRITE_ENABLE))
+/** \} */
+
+/**
+ * \defgroup    ADC_Latch_Data_Edge ADC Latch Data Edge
+ * \{
+ * \ingroup     ADC_Exported_Constants
+ */
+#define ADC_LATCH_DATA_Positive                     ((uint32_t)(0 << 2))
+#define ADC_LATCH_DATA_Negative                     ((uint32_t)(1 << 2))
+
+#define IS_ADC_LATCH_DATA_EDGE(EDGE) (((EDGE) == ADC_LATCH_DATA_Positive) || ((EDGE) == ADC_LATCH_DATA_Negative))
+/** \} */
+
+/**
+ * \defgroup    ADC_Operation_Mode ADC Operation Mode
+ * \{
+ * \ingroup     ADC_Exported_Constants
+ */
+#define ADC_CONTINUOUS_MODE                         ((uint32_t)(1 << 0))
+#define ADC_ONE_SHOT_MODE                           ((uint32_t)(1 << 1))
+
+#define IS_ADC_SAMPLE_MODE(MODE) (((MODE) == ADC_CONTINUOUS_MODE) || ((MODE) == ADC_ONE_SHOT_MODE))
+/** \} */
+
+/**
+ * \defgroup    ADC_Interrupts_Definition ADC Interrupts Definition
+ * \{
+ * \ingroup     ADC_Exported_Constants
+ */
+#define ADC_INT_FIFO_RD_REQ                         ((uint32_t)(1 << 0))
+#define ADC_INT_FIFO_RD_ERR                         ((uint32_t)(1 << 1))
+#define ADC_INT_FIFO_THD                            ((uint32_t)(1 << 2))
+#define ADC_INT_FIFO_FULL                           ((uint32_t)(1 << 3))
+#define ADC_INT_ONE_SHOT_DONE                       ((uint32_t)(1 << 4))
+#define ADC_INT_FIFO_OVERFLOW                       ((uint32_t)(1 << 5))
+
+#define IS_ADC_INT(INT) (((INT) == ADC_INT_FIFO_RD_REQ) || ((INT) == ADC_INT_FIFO_RD_ERR)\
+                         || ((INT) == ADC_INT_FIFO_THD) || ((INT) == ADC_INT_FIFO_FULL)\
+                         || ((INT) == ADC_INT_ONE_SHOT_DONE) || ((INT) == ADC_INT_FIFO_OVERFLOW))
+/** \} */
+
+/**
+ * \defgroup    ADC_Schedule_Table ADC Channel and Mode
+ * \{
+ * \ingroup     ADC_Exported_Constants
+ */
+#define EXT_SINGLE_ENDED(index)                     ((uint16_t)((0x00 << 3) | (index)))
+#define EXT_DIFFERENTIAL(index)                     ((uint16_t)((0x01 << 3) | (index)))
+#define INTERNAL_VBAT_MODE                          ((uint16_t)((0x02 << 3) | 0x00))
+#define EXT_CTC(index)                              ((uint16_t)((0x03 << 3) | (index)))
+
+#if ADC_UNSUPPORT_P2_6
+#define IS_SCHEDULE_TABLE(CONFIG)  ((((CONFIG) & 0xF) != 0x6) && ((CONFIG) != 0xF))
+#endif
+
+#define SCHEDULE_TABLE(index)                       (index)
+#define IS_ADC_SCHEDULE_INDEX_CONFIG(CONFIG) ((((CONFIG) & 0xFFE0) == 0) && ((((~(CONFIG)) & (0x18)) != 0)\
+                                                                             || ((CONFIG) == INTERNAL_VBAT_MODE)))
+/** \} */
+
+/**
+ * \defgroup    ADC_Data_Avg_Num ADC Data Average Num
+ * \brief       Number of raw data for calculate average.
+ * \{
+ * \ingroup     ADC_Exported_Constants
+ */
+#define ADC_DATA_AVERAGE_OF_2                       ((uint32_t)(0 << 25))
+#define ADC_DATA_AVERAGE_OF_4                       ((uint32_t)(1 << 25))
+#define ADC_DATA_AVERAGE_OF_8                       ((uint32_t)(2 << 25))
+#define ADC_DATA_AVERAGE_OF_16                      ((uint32_t)(3 << 25))
+#define ADC_DATA_AVERAGE_OF_32                      ((uint32_t)(4 << 25))
+#define ADC_DATA_AVERAGE_OF_64                      ((uint32_t)(5 << 25))
+#define ADC_DATA_AVERAGE_OF_128                     ((uint32_t)(6 << 25))
+#define ADC_DATA_AVERAGE_OF_256                     ((uint32_t)(7 << 25))
+
+#define IS_ADC_DATA_AVG_NUM(NUM) (((NUM) == ADC_DATA_AVERAGE_OF_2) ||\
+                                  ((NUM) == ADC_DATA_AVERAGE_OF_4) ||\
+                                  ((NUM) == ADC_DATA_AVERAGE_OF_8) ||\
+                                  ((NUM) == ADC_DATA_AVERAGE_OF_16) ||\
+                                  ((NUM) == ADC_DATA_AVERAGE_OF_32) ||\
+                                  ((NUM) == ADC_DATA_AVERAGE_OF_64) ||\
+                                  ((NUM) == ADC_DATA_AVERAGE_OF_128) ||\
+                                  ((NUM) == ADC_DATA_AVERAGE_OF_256))
+/** \} */
+
+/**
+ * \defgroup    ADC_Data_Avg_En ADC Data Average Enable
+ * \brief       Enable the calculation for average result of the one-shot mode.
+ * \{
+ * \ingroup     ADC_Exported_Constants
+ */
+#define ADC_DATA_AVERAGE_DISABLE                    ((uint32_t)(0 << 24))
+#define ADC_DATA_AVERAGE_ENABLE                     ((uint32_t)(1 << 24))
+
+#define IS_ADC_DATA_AVG_EN(CMD) (((CMD) == ADC_DATA_AVERAGE_DISABLE) || ((CMD) == ADC_DATA_AVERAGE_ENABLE))
+/** \} */
+
+/**
+ * \defgroup    ADC_Power_On_Mode ADC Power On Mode
+ * \{
+ * \ingroup     ADC_Exported_Constants
+ */
+#define ADC_POWER_ON_AUTO                           ((uint32_t)(0 << 19))
+#define ADC_POWER_ON_MANUAL                         ((uint32_t)(1 << 19))
+
+#define IS_ADC_POWER_ON_MODE(MODE) (((MODE) == ADC_POWER_ON_AUTO) || ((MODE) == ADC_POWER_ON_MANUAL))
+/** \} */
+
+/**
+ * \defgroup    ADC_RG2X_0_Delay_Time ADC RG2X_0 Delay Time
+ * \{
+ * \ingroup     ADC_Exported_Constants
+ */
+#define ADC_RG2X_0_DELAY_10_US                      ((uint32_t)(0 << 4))
+#define ADC_RG2X_0_DELAY_20_US                      ((uint32_t)(1 << 4))
+#define ADC_RG2X_0_DELAY_40_US                      ((uint32_t)(2 << 4))
+#define ADC_RG2X_0_DELAY_80_US                      ((uint32_t)(3 << 4))
+
+#define IS_ADC_RG2X_0_DELAY_TIME(TIME) (((TIME) == ADC_RG2X_0_DELAY_10_US) || ((TIME) == ADC_RG2X_0_DELAY_20_US)\
+                                        || ((TIME) == ADC_RG2X_0_DELAY_40_US) || ((TIME) == ADC_RG2X_0_DELAY_80_US))
+/** \} */
+
+/**
+ * \defgroup    ADC_RG0X_1_Delay_Time ADC RG0X_1 Delay Time
+ * \{
+ * \ingroup     ADC_Exported_Constants
+ */
+#define ADC_RG0X_1_DELAY_20_US                      ((uint32_t)(0 << 2))
+#define ADC_RG0X_1_DELAY_40_US                      ((uint32_t)(1 << 2))
+#define ADC_RG0X_1_DELAY_80_US                      ((uint32_t)(2 << 2))
+#define ADC_RG0X_1_DELAY_160_US                     ((uint32_t)(3 << 2))
+
+#define IS_ADC_RG0X_1_DELAY_TIME(TIME) (((TIME) == ADC_RG0X_1_DELAY_20_US) || ((TIME) == ADC_RG0X_1_DELAY_40_US)\
+                                        || ((TIME) == ADC_RG0X_1_DELAY_80_US) || ((TIME) == ADC_RG0X_1_DELAY_160_US))
+/** \} */
+
+/**
+ * \defgroup    ADC_RG0X_0_Delay_Time ADC RG0X_0 Delay Time
+ * \{
+ * \ingroup     ADC_Exported_Constants
+ */
+#define ADC_RG0X_0_DELAY_30_US                      ((uint32_t)(0 << 0))
+#define ADC_RG0X_0_DELAY_60_US                      ((uint32_t)(1 << 0))
+#define ADC_RG0X_0_DELAY_120_US                     ((uint32_t)(2 << 0))
+#define ADC_RG0X_0_DELAY_240_US                     ((uint32_t)(3 << 0))
+
+#define IS_ADC_RG0X_0_DELAY_TIME(TIME) (((TIME) == ADC_RG0X_0_DELAY_30_US) || ((TIME) == ADC_RG0X_0_DELAY_60_US)\
+                                        || ((TIME) == ADC_RG0X_0_DELAY_120_US) || ((TIME) == ADC_RG0X_0_DELAY_240_US))
+/** \} */
+
+/**
+ * \defgroup    ADC_Data_Minus_En ADC Data Minus Enable
+ * \{
+ * \ingroup     ADC_Exported_Constants
+ */
+#define ADC_DATA_MINUS_DISABLE                      (uint32_t)(0 << 31)
+#define ADC_DATA_MINUS_ENABLE                       (uint32_t)(1 << 31)
+
+#define IS_ADC_DATA_MINUS_CMD(CMD) (((CMD) == ADC_DATA_MINUS_DISABLE) || ((CMD) == ADC_DATA_MINUS_ENABLE))
+/** \} */
+
+/**
+ * \defgroup    ADC_Data_Align ADC Data Align
+ * \{
+ * \ingroup     ADC_Exported_Constants
+ */
+#define ADC_DATA_ALIGN_LSB                          (uint32_t)(0 << 30)
+#define ADC_DATA_ALIGN_MSB                          (uint32_t)(1 << 30)
+
+#define IS_ADC_DATA_ALIGN(DATA_ALIGN) (((DATA_ALIGN) == ADC_DATA_ALIGN_LSB) || ((DATA_ALIGN) == ADC_DATA_ALIGN_MSB))
+/** \} */
+
+/**
+ * \defgroup    ADC_Timer_Trigger_En ADC Timer Trigger Enable
+ * \brief       Enable ADC trigger one-shot mode with TIM7.
+ * \{
+ * \ingroup     ADC_Exported_Constants
+ */
+#define ADC_TIMER_TRIGGER_DISABLE                   ((uint32_t)(0 << 29))
+#define ADC_TIMER_TRIGGER_ENABLE                    ((uint32_t)(1 << 29))
+
+#define IS_ADC_TIMER_TRIGGER_CMD(CMD) (((CMD) == ADC_TIMER_TRIGGER_DISABLE) || ((CMD) == ADC_TIMER_TRIGGER_ENABLE))
+/** \} */
+
+/**
+ * \defgroup    ADC_Power_Always_On_Cmd ADC Power Always On Cmd
+ * \{
+ * \ingroup     ADC_Exported_Constants
+ */
+#define ADC_POWER_ALWAYS_ON_DISABLE                 ((uint32_t)(0 << 15))
+#define ADC_POWER_ALWAYS_ON_ENABLE                  ((uint32_t)(1 << 15))
+
+#define IS_ADC_POWER_ALWAYS_ON(CMD) (((CMD) == ADC_POWER_ALWAYS_ON_DISABLE) || ((CMD) == ADC_POWER_ALWAYS_ON_ENABLE))
+/** \} */
+
+/**
+ * \defgroup    ADC_Convert_Time ADC Convert Time
+ * \{
+ * \ingroup     ADC_Exported_Constants
+ */
+#define    ADC_CONVERT_TIME_500NS                      ((uint32_t)(0 << 30))
+#define    ADC_CONVERT_TIME_700NS                      ((uint32_t)(1 << 30))
+#define    ADC_CONVERT_TIME_900NS                      ((uint32_t)(2 << 30))
+#define    ADC_CONVERT_TIME_1100NS                     ((uint32_t)(3 << 30))
+
+#define IS_ADC_CONVERT_TIME(TIME) (((TIME) == ADC_CONVERT_TIME_500NS) || \
+                                   ((TIME) == ADC_CONVERT_TIME_700NS) || \
+                                   ((TIME) == ADC_CONVERT_TIME_900NS) || \
+                                   ((TIME) == ADC_CONVERT_TIME_1100NS))
+/** \} */
+
+/** End of ADC_Exported_Constants
+  * \}
+  */
+
+/*============================================================================*
+ *                         Functions
+ *============================================================================*/
+/** \defgroup    ADC_Exported_Functions ADC Exported Functions
+  * \{
+  * \ingroup     ADC
+  */
+
+/**
+ * rtl876x_adc.h
+ *
+ * \brief   Deinitialize the ADC peripheral registers to their
+ *          default reset values (turn off ADC clock).
+ * \details
+ * \param[in] ADCx: Specify ADC peripheral, can only be ADC.
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_adc_init(void)
+ * {
+ *    // Turn off the clock.
+ *    ADC_DeInit(ADC);
+ * }
+ * \endcode
+ */
+void ADC_DeInit(ADC_TypeDef *ADCx);
+
+/**
+ * rtl876x_adc.h
+ *
+ * \brief Initialize the ADC peripheral according to the specified
+ *     parameters in the ADC_InitStruct
+ * \param[in]  ADCx: selected ADC peripheral.
+ * \param[in]  ADC_InitStruct: pointer to an ADC_InitTypeDef structure that
+ *     contains the configuration information for the specified ADC peripheral
+ * \return      None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_adc_init(void)
+ * {
+ *    // Turn on the clock.
+ *    RCC_PeriphClockCmd(APBPeriph_ADC, APBPeriph_ADC_CLOCK, ENABLE);
+
+ *    ADC_InitTypeDef ADC_InitStruct;
+ *    ADC_StructInit(&ADC_InitStruct);
+ *    ADC_InitStruct.ADC_SchIndex[0] = EXT_SINGLE_ENDED(0);
+ *    ADC_InitStruct.ADC_SchIndex[1] = EXT_SINGLE_ENDED(1);
+ *    ADC_InitStruct.ADC_Bitmap = 0x03;
+ *    // Add other initialization parameters that need to be configured here.
+ *    ADC_Init(ADC, &ADC_InitStruct);
+ * }
+ * \endcode
+ */
+void ADC_Init(ADC_TypeDef *ADCx, ADC_InitTypeDef *ADC_InitStruct);
+
+/**
+ * rtl876x_adc.h
+ *
+ * \brief   Fill each ADC_InitStruct member with its default value.
+ * \param[in] ADC_InitStruct: Pointer to an ADC_InitTypeDef structure which will be initialized.
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_adc_init(void)
+ * {
+ *    // Turn on the clock.
+ *    RCC_PeriphClockCmd(APBPeriph_ADC, APBPeriph_ADC_CLOCK, ENABLE);
+
+ *    ADC_InitTypeDef ADC_InitStruct;
+ *    ADC_StructInit(&ADC_InitStruct);
+ *    ADC_InitStruct.ADC_SchIndex[0] = EXT_SINGLE_ENDED(0);
+ *    ADC_InitStruct.ADC_SchIndex[1] = EXT_SINGLE_ENDED(1);
+ *    ADC_InitStruct.ADC_Bitmap = 0x03;
+ *    // Add other initialization parameters that need to be configured here.
+ *    ADC_Init(ADC, &ADC_InitStruct);
+ * }
+ * \endcode
+ * \callgraph
+ *
+ */
+void ADC_StructInit(ADC_InitTypeDef *ADC_InitStruct);
+
+/**
+ * rtl876x_adc.h
+ *
+ * \brief   Enable or disable the ADC peripheral.
+ * \param[in]  ADCx: Specify ADC peripheral.
+ * \param[in]  adcMode: ADC operation mode selection.
+        This parameter can be one of the following values, which refer to \ref ADC_Operation_Mode.
+ *     \arg ADC_ONE_SHOT_MODE: One shot mode.
+ *     \arg ADC_CONTINUOUS_MODE: Continuous sampling mode.
+ * \param[in]  NewState: New state of the ADC peripheral.
+ *     This parameter can be: ENABLE or DISABLE.
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void board_adc_init(void)
+ * {
+ *     Pad_Config(P2_0, PAD_SW_MODE, PAD_IS_PWRON, PAD_PULL_NONE, PAD_OUT_DISABLE,
+ *                PAD_OUT_LOW);
+ *
+ *     Pad_Config(P2_1, PAD_SW_MODE, PAD_IS_PWRON, PAD_PULL_NONE, PAD_OUT_DISABLE,
+ *                PAD_OUT_LOW);
+ * }
+ *
+ * void driver_adc_init(void)
+ * {
+ *    // Open clock
+ *    RCC_PeriphClockCmd(APBPeriph_ADC, APBPeriph_ADC_CLOCK, ENABLE);
+ *
+ *    ADC_InitTypeDef ADC_InitStruct;
+ *    ADC_StructInit(&ADC_InitStruct);
+ *    ADC_InitStruct.ADC_SchIndex[0] = EXT_SINGLE_ENDED(0);
+ *    ADC_InitStruct.ADC_SchIndex[1] = EXT_SINGLE_ENDED(1);
+ *    ADC_InitStruct.ADC_Bitmap = 0x03;
+ *    // Add other initialization parameters here.
+ *    ADC_Init(ADC, &ADC_InitStruct);
+ *
+ *    ADC_INTConfig(ADC, ADC_INT_ONE_SHOT_DONE, ENABLE);
+ * }
+ *
+ * void adc_demo(void)
+ * {
+ *    board_adc_init();
+ *    driver_adc_init();
+ *    ADC_Cmd(ADC, ADC_ONE_SHOT_MODE, ENABLE);
+ * }
+ * \endcode
+ */
+void ADC_Cmd(ADC_TypeDef *ADCx, uint8_t adcMode, FunctionalState NewState);
+
+/**
+ * rtl876x_adc.h
+ *
+ * \brief   Enable or disable the specified ADC interrupts.
+ * \param[in]  ADCx: Specify ADC peripheral.
+ * \param[in]  ADC_INT: Specify the ADC interrupt sources to be enabled or disabled.
+ *     This parameter can be any combination of the following values, which refer to \ref ADC_Interrupts_Definition.
+ *     \arg ADC_INT_FIFO_RD_REQ : ADC FIFO size >= burst size interrupt.
+ *     \arg ADC_INT_FIFO_RD_ERR : ADC FIFO underflow interrupt.
+ *     \arg ADC_INT_FIFO_THD : ADC FIFO size > thd interrupt.
+ *     \arg ADC_INT_FIFO_FULL : ADC FIFO full interrupt.
+ *     \arg ADC_INT_ONE_SHOT_DONE : ADC one shot mode done interrupt.
+ *     \arg ADC_INT_FIFO_OVERFLOW : ADC FIFO overflow interrupt.
+ * \param[in]  NewState: New state of the specified ADC interrupt.
+ *     This parameter can be: ENABLE or DISABLE.
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_adc_init(void)
+ * {
+ *    // Open clock
+ *    RCC_PeriphClockCmd(APBPeriph_ADC, APBPeriph_ADC_CLOCK, ENABLE);
+ *
+ *    ADC_InitTypeDef ADC_InitStruct;
+ *    ADC_StructInit(&ADC_InitStruct);
+ *    ADC_InitStruct.ADC_SchIndex[0] = EXT_SINGLE_ENDED(0);
+ *    ADC_InitStruct.ADC_SchIndex[1] = EXT_SINGLE_ENDED(1);
+ *    ADC_InitStruct.ADC_Bitmap = 0x03;
+ *    // Add other initialization parameters here.
+ *    ADC_Init(ADC, &ADC_InitStruct);
+ *
+ *    ADC_INTConfig(ADC, ADC_INT_FIFO_RD_ERR, ENABLE);
+ *    ADC_INTConfig(ADC, ADC_INT_ONE_SHOT_DONE, ENABLE);
+ * }
+ * \endcode
+ *
+ */
+void ADC_INTConfig(ADC_TypeDef *ADCx, uint32_t ADC_INT, FunctionalState NewState);
+
+/**
+ * rtl876x_adc.h
+ *
+ * \brief      Read ADC data according to specific channel.
+ * \param[in]  ADCx: Specify ADC peripheral.
+ * \param[in]  index: Can be 0 to 15.
+ * \return     The 12-bit converted ADC raw data.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void board_adc_init(void)
+ * {
+ *     Pad_Config(P2_0, PAD_SW_MODE, PAD_IS_PWRON, PAD_PULL_NONE, PAD_OUT_DISABLE,
+ *                PAD_OUT_LOW);
+ *
+ *     Pad_Config(P2_1, PAD_SW_MODE, PAD_IS_PWRON, PAD_PULL_NONE, PAD_OUT_DISABLE,
+ *                PAD_OUT_LOW);
+ * }
+ *
+ * void driver_adc_init(void)
+ * {
+ *    // Open clock
+ *    RCC_PeriphClockCmd(APBPeriph_ADC, APBPeriph_ADC_CLOCK, ENABLE);
+ *
+ *    ADC_InitTypeDef ADC_InitStruct;
+ *    ADC_StructInit(&ADC_InitStruct);
+ *    ADC_InitStruct.ADC_SchIndex[0] = EXT_SINGLE_ENDED(0);
+ *    ADC_InitStruct.ADC_SchIndex[1] = EXT_SINGLE_ENDED(1);
+ *    ADC_InitStruct.ADC_Bitmap = 0x03;
+ *    // Add other initialization parameters here.
+ *    ADC_Init(ADC, &ADC_InitStruct);
+ *
+ *    ADC_INTConfig(ADC, ADC_INT_ONE_SHOT_DONE, ENABLE);
+ * }
+ *
+ * void adc_demo(void)
+ * {
+ *    board_adc_init();
+ *    driver_adc_init();
+ *    ADC_Cmd(ADC, ADC_ONE_SHOT_MODE, ENABLE);
+ *    while(ADC_GetINTStatus(ADC, ADC_INT_ONE_SHOT_DONE) == RESET);
+ *    uint16_t raw_data_0 = ADC_ReadRawData(ADC, 0);
+ *    uint16_t raw_data_1 = ADC_ReadRawData(ADC, 1);
+ * }
+ * \endcode
+ */
+uint16_t ADC_ReadRawData(ADC_TypeDef *ADCx, uint8_t index);
+
+/**
+ * rtl876x_adc.h
+ *
+ * \brief   Get ADC average data from ADC schedule table 0.
+ * \param[in]  ADCx: Specify ADC peripheral.
+ * \return  The 10 bits integer data + 2 bits fractional ADC raw data.
+ * \callgraph
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void board_adc_init(void)
+ * {
+ *     Pad_Config(P2_0, PAD_SW_MODE, PAD_IS_PWRON, PAD_PULL_NONE, PAD_OUT_DISABLE,
+ *                PAD_OUT_LOW);
+ * }
+ *
+ * void driver_adc_init(void)
+ * {
+ *    // open clock
+ *    RCC_PeriphClockCmd(APBPeriph_ADC, APBPeriph_ADC_CLOCK, ENABLE);
+ *
+ *    ADC_InitTypeDef ADC_InitStruct;
+ *    ADC_StructInit(&ADC_InitStruct);
+ *    ADC_InitStruct.ADC_SchIndex[0] = EXT_SINGLE_ENDED(0);
+ *    ADC_InitStruct.ADC_Bitmap = 0x01;
+ *    ADC_InitStruct.ADC_DataAvgEn  = ADC_DATA_AVERAGE_ENABLE;
+ *    ADC_InitStruct.ADC_DataAvgSel = ADC_DATA_AVERAGE_OF_2;
+ *    // Add other initialization parameters here.
+ *    ADC_Init(ADC, &ADC_InitStruct);
+ *
+ *    ADC_INTConfig(ADC, ADC_INT_ONE_SHOT_DONE, ENABLE);
+ * }
+ *
+ * void adc_demo(void)
+ * {
+ *    board_adc_init();
+ *    driver_adc_init();
+ *    ADC_Cmd(ADC, ADC_ONE_SHOT_MODE, ENABLE);
+ *    while(ADC_GetINTStatus(ADC, ADC_INT_ONE_SHOT_DONE) == RESET);
+ *    uint16_t raw_data = 0;
+ *    raw_data = ADC_ReadAvgRawData(ADC);
+ * }
+ * \endcode
+ *
+ */
+uint16_t ADC_ReadAvgRawData(ADC_TypeDef *ADCx);
+
+/**
+ * rtl876x_adc.h
+ *
+ * \brief  Get raw data from ADC FIFO.
+ * \param[in]  ADCx: selected ADC peripheral.
+ * \return ADC FIFO data.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void board_adc_init(void)
+ * {
+ *     Pad_Config(P2_0, PAD_SW_MODE, PAD_IS_PWRON, PAD_PULL_NONE, PAD_OUT_DISABLE,
+ *                PAD_OUT_LOW);
+ * }
+ *
+ * void driver_adc_init(void)
+ * {
+ *    // open clock
+ *    RCC_PeriphClockCmd(APBPeriph_ADC, APBPeriph_ADC_CLOCK, ENABLE);
+ *
+ *    ADC_InitTypeDef ADC_InitStruct;
+ *    ADC_StructInit(&ADC_InitStruct);
+ *    ADC_InitStruct.ADC_SchIndex[0] = EXT_SINGLE_ENDED(0);
+ *    ADC_InitStruct.ADC_Bitmap = 0x01;
+ *    ADC_InitStruct.ADC_DataWriteToFifo = ADC_DATA_WRITE_TO_FIFO_DISABLE;
+ *    ADC_Init(ADC, &ADC_InitStruct);
+ *
+ *    ADC_INTConfig(ADC, ADC_INT_ONE_SHOT_DONE, ENABLE);
+ * }
+ *
+ * void adc_demo(void)
+ * {
+ *    board_adc_init();
+ *    driver_adc_init();
+ *    ADC_Cmd(ADC, ADC_ONE_SHOT_MODE, ENABLE);
+ *    while(ADC_GetINTStatus(ADC, ADC_INT_ONE_SHOT_DONE) == RESET);
+ *    uint16_t raw_data = 0;
+ *    raw_data = ADC_ReadFIFO(ADC);
+ * }
+ * \endcode
+ */
+uint16_t ADC_ReadFIFO(ADC_TypeDef *ADCx);
+
+/**
+ * rtl876x_adc.h
+ *
+ * \brief   Get data from ADC FIFO.
+ * \param[in]  ADCx: Specify ADC peripheral.
+ * \param[out] outBuf: Buffer to save data read from ADC FIFO.
+ * \param[in]  num: Number of data to be read.
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void adc_demo(void)
+ * {
+ *    // ADC already start
+ *    uint16_t raw_data[32] = {0};
+ *    uint8_t data_len = ADC_GetFIFODataLen(ADC);
+ *    ADC_ReadFIFOData(ADC, raw_data, data_len);
+ * }
+ * \endcode
+ *
+ */
+void ADC_ReadFIFOData(ADC_TypeDef *ADCx, uint16_t *outBuf, uint16_t num);
+
+/**
+ * rtl876x_adc.h
+ *
+ * \brief   Get ADC FIFO data number.
+ * \param[in] ADCx: selected ADC peripheral.
+ * \return  Current data number in ADC FIFO.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void adc_demo(void)
+ * {
+ *    // ADC already start
+ *    uint16_t raw_data[32] = {0};
+ *    uint8_t data_len = ADC_GetFIFODataLen(ADC);
+ *    ADC_ReadFIFOData(ADC, raw_data, data_len);
+ * }
+ * \endcode
+ *
+ */
+uint8_t ADC_GetFIFODataLen(ADC_TypeDef *ADCx);
+
+/**
+ * rtl876x_adc.h
+ *
+ * \brief   Config ADC schedule table index.
+ * \param[in]  ADCx: Specify ADC peripheral.
+ * \param[in]  adcMode: ADC operation mode.
+ *     This parameter can be one of the following values, which refer to \ref ADC_Schedule_Table.
+ *     \arg EXT_SINGLE_ENDED(index)
+ *     \arg EXT_DIFFERENTIAL(index)
+ *     \arg INTERNAL_VBAT_MODE
+ * \param[in]  Index: Schedule table index.
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void adc_demo(void)
+ * {
+ *   ADC_SchIndexConfig(ADC, INTERNAL_VBAT_MODE, 0);
+ * }
+ * \endcode
+ *
+ */
+void ADC_SchIndexConfig(ADC_TypeDef *ADCx, uint8_t adcMode, uint16_t Index);
+
+/**
+  * \brief  Config ADC schedule table.
+  * \param[in]  ADCx: selected ADC peripheral.
+  * \param[in]  Index: Schedule table index.
+  * \param[in]  adcMode: ADC mode.
+  *      This parameter can be one of the following values, which refer to \ref ADC_Schedule_Table.
+  *     \arg EXT_SINGLE_ENDED(index)
+  *     \arg EXT_DIFFERENTIAL(index)
+  *     \arg INTERNAL_VBAT_MODE
+  * \return none.
+  */
+void ADC_SchTableConfig(ADC_TypeDef *ADCx, uint16_t Index, uint8_t adcMode);
+
+/**
+ * rtl876x_adc.h
+ *
+ * \brief   Config ADC bit map.
+ * \param[in]  ADCx: Specify ADC peripheral.
+ * \param[in]  bitMap: ADC channel map.
+ * \param[in]  NewState: New state of the ADC peripheral.
+ *      This parameter can be: ENABLE or DISABLE.
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void adc_demo(void)
+ * {
+ *   uint16_t bit_map = 0x03;
+ *   ADC_BitMapConfig(ADC, bit_map);
+ * }
+ * \endcode
+ *
+ */
+void ADC_BitMapConfig(ADC_TypeDef *ADCx, uint16_t bitMap);
+
+/**
+ * rtl876x_adc.h
+ *
+ * \brief   Power on ADC manually.
+ * \param[in]  ADCx: Specify ADC peripheral.
+ * \param[in]  NewState: New state of the ADC power on.
+ *      This parameter can be: ENABLE or DISABLE. If enabled, ADC power will always be on until disabled.
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void adc_demo(void)
+ * {
+ *   ADC_ManualPowerOnCmd(ADC, ENABLE);
+ * }
+ * \endcode
+ *
+ */
+void ADC_ManualPowerOnCmd(ADC_TypeDef *ADCx, FunctionalState NewState);
+
+/**
+ * rtl876x_adc.h
+ *
+ * \brief   Enable or disable stop FIFO from writing data.
+ * \param[in]  ADCx: Specify ADC peripheral.
+ * \param[in]  NewState: New state of the ADC FIFO write.
+ *     This parameter can be: ENABLE or DISABLE.
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void adc_demo(void)
+ * {
+ *   ADC_WriteFIFOCmd(ADC, ENABLE);
+ * }
+ * \endcode
+ *
+ */
+void ADC_WriteFIFOCmd(ADC_TypeDef *ADCx, FunctionalState NewState);
+
+/**
+ * rtl876x_adc.h
+ *
+ * \brief  Config ADC bypass resistor.
+ * \param[in] ChannelNum: External channel number, can be 0~7.
+ * \param[in] NewState: Specify whether the channel enables bypass mode.
+ *     This parameter can be: ENABLE or DISABLE.
+ * \return  None.
+ * \note    The input voltage of channel pin using bypass mode cannot exceed 0.9V!
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void adc_demo(void)
+ * {
+ *   ADC_BypassCmd(0, ENABLE);
+ * }
+ * \endcode
+ *
+ */
+void ADC_BypassCmd(uint8_t ChannelNum, FunctionalState NewState);
+
+/**
+ * rtl876x_adc.h
+ *
+ * \brief  Check whether the specified ADC interrupt flag is set.
+ * \param[in]  ADCx: selected ADC peripheral.
+ * \param[in]  ADC_INT: Specify the interrupt flag to check.
+ *     This parameter can be one of the following values, which refer to \ref ADC_Interrupts_Definition.
+ *     \arg ADC_INT_FIFO_OVERFLOW: ADC FIFO overflow interrupt.
+ *     \arg ADC_INT_ONE_SHOT_DONE: ADC once convert end interrupt.
+ *     \arg ADC_INT_FIFO_FULL: ADC FIFO full interrupt.
+ *     \arg ADC_INT_FIFO_THD: FIFO larger than threshold interrupt.
+ *     \arg ADC_INT_FIFO_RD_ERR: ADC FIFO underflow interrupt.
+ *     \arg ADC_INT_FIFO_RD_REQ: ADC FIFO size >= burst size interrupt.
+ *
+ * \return The new state of ADC_INT (SET or RESET).
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void adc_demo(void)
+ * {
+ *     ITStatus int_status = RESET;
+ *     int_status = ADC_GetINTStatus(ADC, ADC_INT_FIFO_OVERFLOW);
+ * }
+ * \endcode
+ *
+ */
+ITStatus ADC_GetINTStatus(ADC_TypeDef *ADCx, uint32_t ADC_INT);
+
+/**
+ * rtl876x_adc.h
+ *
+ * \brief  Clear the ADC interrupt pending bit.
+ * \param[in] ADCx: Specify ADC peripheral.
+ * \param[in] ADC_INT: Specify the interrupt pending bit to clear.
+ *     This parameter can be any combination of the following values, which refer to \ref ADC_Interrupts_Definition.
+ *     \arg ADC_INT_FIFO_OVERFLOW: ADC FIFO overflow interrupt.
+ *     \arg ADC_INT_ONE_SHOT_DONE: ADC once convert end interrupt.
+ *     \arg ADC_INT_FIFO_FULL: ADC FIFO full interrupt.
+ *     \arg ADC_INT_FIFO_THD: FIFO larger than threshold interrupt.
+ *     \arg ADC_INT_FIFO_RD_ERR: ADC FIFO underflow interrupt.
+ *     \arg ADC_INT_FIFO_RD_REQ: ADC FIFO size >= burst size interrupt.
+ *
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void adc_demo(void)
+ * {
+ *   ADC_ClearINTPendingBit(ADC, ADC_INT_FIFO_OVERFLOW);
+ * }
+ * \endcode
+ *
+ */
+void ADC_ClearINTPendingBit(ADC_TypeDef *ADCx, uint32_t ADC_INT);
+
+/**
+ * rtl876x_adc.h
+ *
+ * \brief   Clear ADC FIFO.
+ * \param[in] ADCx: Specify ADC peripheral.
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void adc_demo(void)
+ * {
+ *   ADC_ClearFIFO(ADC);
+ * }
+ * \endcode
+ *
+ */
+__STATIC_INLINE void ADC_ClearFIFO(ADC_TypeDef *ADCx)
+{
+    /* Check the parameters */
+    assert_param(IS_ADC_PERIPH(ADCx));
+
+    ADCx->CR |= BIT26;
+}
+
+/**
+ * rtl876x_adc.h
+ *
+ * \brief   Get all ADC interrupt flag status.
+ * \param[in] ADCx: Specify ADC peripheral.
+ * \return  All ADC interrupt status. \ref ADC_Interrupts_Definition.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void adc_demo(void)
+ * {
+ *   uint8_t all_flag_status = 0;
+ *   all_flag_status = ADC_GetAllFlagStatus(ADC);
+ * }
+ * \endcode
+ *
+ */
+__STATIC_INLINE uint8_t ADC_GetAllFlagStatus(ADC_TypeDef *ADCx)
+{
+    /* Check the parameters */
+    assert_param(IS_ADC_PERIPH(ADCx));
+
+    return ((uint8_t)(((ADCx->INTCR) & (0x1f << 16)) >> 16));
+}
+
+/** End of ADC_Exported_Functions
+  * \}
+  */
+
+/** End of ADC
+  * \}
+  */
+
+typedef struct
+{
+    uint32_t adc_reg[7];
+    uint32_t adc_schtab_reg[8];
+    uint16_t aon_reg[1];
+} ADCStoreReg_TypeDef;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTL876X_ADC_H_ */
+
diff --git a/bee/drivers/adc/src/device/rtl87x2g/adc_lib.h b/bee/drivers/adc/src/device/rtl87x2g/adc_lib.h
new file mode 100644
index 00000000..922e70e2
--- /dev/null
+++ b/bee/drivers/adc/src/device/rtl87x2g/adc_lib.h
@@ -0,0 +1,113 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __ADC_K_LIB_H
+#define __ADC_K_LIB_H
+
+#include <stdbool.h>
+#include <stdint.h>
+
+/** \defgroup ADC_LIB        ADC LIB
+  * \brief
+  * \{
+  */
+/*============================================================================*
+ *                         Constants
+ *============================================================================*/
+/** \defgroup ADC_LIB_ADC_Exported_Constants ADC Exported Constants
+  * \brief
+  * \{
+  */
+
+/**
+ * \defgroup    ADC_Mode ADC Mode
+ * \{
+ * \ingroup     ADC_LIB_ADC_Exported_Constants
+ */
+#define USE_ADC_DIVIDE_SINGLE_MODE      1
+#define USE_ADC_BYPASS_SINGLE_MODE      1
+#define USE_ADC_DIVIDE_DIFF_MODE        1
+#define USE_ADC_BYPASS_DIFF_MODE        1
+/** End of ADC_Mode
+  * \}
+  */
+
+/**
+ * \defgroup   ADC_SampleMode ADC SampleMode
+ * \{
+ * \ingroup    ADC_LIB_ADC_Exported_Constants
+ */
+typedef enum
+{
+    DIVIDE_SINGLE_MODE = 1,
+    BYPASS_SINGLE_MODE = 2,
+    DIVIDE_DIFFERENTIAL_MODE = 3,
+    BYPASS_DIFFERENTIAL_MODE = 4,
+} ADC_SampleMode;
+/** End of ADC_SampleMode
+  * \}
+  */
+
+/**
+ * \defgroup    ADC_ErrorStatus ADC ErrorStatus
+ * \{
+ * \ingroup     ADC_LIB_ADC_Exported_Constants
+ */
+typedef enum
+{
+    NO_ERROR = 0,
+    PARAMETER_ERROR = -1,
+    RAM_DATA_ERROR = -2,
+    NO_CALIBRATION = -3,
+    VERSION_ERROR = -4,
+} ADC_ErrorStatus;
+/** End of ADC_ErrorStatus
+  * \}
+  */
+
+/** End of ADC_LIB_ADC_Exported_Constants
+  * \}
+  */
+
+/*============================================================================*
+ *                         Functions
+ *============================================================================*/
+/** \defgroup ADC_LIB_ADC_Exported_Functions ADC Exported Functions
+  * \brief
+  * \{
+  */
+
+/**
+  * @brief  Initialize the ADC calibration process.
+  * @return A boolean value indicating the success of the calibration operation.
+  */
+bool ADC_CalibrationInit(void);
+
+/**
+  * @brief  Retrieve the voltage value from an ADC conversion.
+  * @param[in]  vSampleMode  Specifies the mode of ADC operation.
+  * @param[in]  vSampleData  Represents the raw data obtained from the ADC.
+  * @param[in]  pErrorStatus Pointer to a variable where ADC error status will be stored.
+  * @return The voltage value calculated from the ADC data.
+  */
+float ADC_GetVoltage(const ADC_SampleMode vSampleMode, int32_t vSampleData,
+                     ADC_ErrorStatus *pErrorStatus);
+
+/**
+  * @brief  Retrieve the resistance value measured by the ADC.
+  * @return The ADC resistance value.
+  */
+uint16_t ADC_GetResistance(void);
+
+/** End of ADC_LIB_ADC_Exported_Functions
+  * \}
+  */
+
+/** End of ADC_LIB
+  * \}
+  */
+
+#endif /* ADC_LIB_H */
diff --git a/bee/drivers/adc/src/device/rtl87x2g/rtl87x2g_adc.c b/bee/drivers/adc/src/device/rtl87x2g/rtl87x2g_adc.c
new file mode 100644
index 00000000..bef3916e
--- /dev/null
+++ b/bee/drivers/adc/src/device/rtl87x2g/rtl87x2g_adc.c
@@ -0,0 +1,226 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *                        Header Files
+ *============================================================================*/
+#include "rtl_adc.h"
+#include "rtl_rcc.h"
+#include "stdbool.h"
+#include "app_section.h"
+
+/*============================================================================*
+ *                          Private Macros
+ *============================================================================*/
+#define AUXADC_AON_REG0X1B94                ((AON_NS_REG0X_AUX_V09_TYPE *)0x40001B94UL)
+#define AUXADC_AON_REG0X1B90                ((AON_NS_REG0X_LDO_TYPE *)0x40001B90UL)
+#define LPC_AON_AUXADC                      ((AON_NS_REG0X_SD_TYPE *)0x40001B98UL)
+#define PERI_ON_AUDIO_CLOCK_CTRL            *((volatile uint32_t *)PERIBLKCTRL_AUDIO_REG_BASE)
+
+typedef enum
+{
+    AUTO_SWITCH_TABLE0_IDLE_MODE            = 0,
+    AUTO_SWITCH_TABLE1_XTAL_MODE_TRANSITION = 1,
+    AUTO_SWITCH_TABLE2_TXAFE1_TRX_MODE      = 2,
+    AUTO_SWITCH_TABLE3_TXAFE2_TRX_MODE      = 3,
+    AUTO_SWITCH_TABLE4_TXAFE1_TX_4DBM_MODE  = 4,
+
+    AUTO_SWITCH_TABLE_MAX                   = 5,
+}
+AUTO_SWITCH_TABLE_TYPE;
+
+extern void (*pmu_auto_switch_map_force_base_level)(AUTO_SWITCH_TABLE_TYPE type, bool enable);
+
+void force_vddcore_1v2_for_auxadc(bool enable)
+{
+    static bool current_state = false;
+    if (current_state != enable)
+    {
+        pmu_auto_switch_map_force_base_level(AUTO_SWITCH_TABLE3_TXAFE2_TRX_MODE, enable);
+        current_state = enable;
+    }
+}
+/*============================================================================*
+ *                           Public Functions
+ *============================================================================*/
+void ADC_SISet(void)
+{
+    /*Added to stabilize the power supply!*/
+    /* set to LDO mode */
+    force_vddcore_1v2_for_auxadc(true);
+    AUXADC_AON_REG0X1B90->hw_pd = 0x0;
+    AUXADC_AON_REG0X1B90->SELLDO = 0x1;
+}
+
+void ADC_PowerOff(void)
+{
+    /*Power off control flow!*/
+
+    AUXADC_AON_REG0X1B94->pow = 0x0;
+    AUXADC_AON_REG0X1B94->pow_ref = 0x0;
+
+    uint32_t codec_clk_en = (PERI_ON_AUDIO_CLOCK_CTRL & BIT9) >> 9;
+
+    if (LPC_AON_AUXADC-> POW_SD_H != 0x1 && codec_clk_en != 1)
+    {
+        AUXADC_AON_REG0X1B90->anapar_pow_ad_2 = 0x0;
+        AUXADC_AON_REG0X1B90->anapar_pow_ad_1 = 0x0;
+        AUXADC_AON_REG0X1B90->hw_pd = 0x1;
+    }
+    force_vddcore_1v2_for_auxadc(false);
+
+}
+
+typedef enum
+{
+    ADC_POW_AD1_DELAY_10_US,
+    ADC_POW_AD1_DELAY_20_US,
+    ADC_POW_AD1_DELAY_40_US,
+    ADC_POW_AD1_DELAY_80_US,
+} ADCPowAD1Delay_TypeDef;
+
+typedef enum
+{
+    ADC_POW_AD2_DELAY_20_US,
+    ADC_POW_AD2_DELAY_40_US,
+    ADC_POW_AD2_DELAY_80_US,
+    ADC_POW_AD2_DELAY_160_US,
+} ADCPowAD2Delay_TypeDef;
+
+typedef enum
+{
+    ADC_POW_REF_DELAY_30_US,
+    ADC_POW_REF_DELAY_60_US,
+    ADC_POW_REF_DELAY_120_US,
+    ADC_POW_REF_DELAY_240_US,
+} ADCPowRefDelay_TypeDef;
+
+
+void ADC_DelayConfig(ADC_TypeDef *ADCx)
+{
+    ADC_POW_DATA_DLY_CTRL_TypeDef adc_0x50 = {.d32 = ADCx->ADC_POW_DATA_DLY_CTRL};
+
+    adc_0x50.b.adc_reg0x_ldo_1_delay_sel = ADC_POW_AD1_DELAY_10_US;
+    adc_0x50.b.adc_reg0x_ldo_2_delay_sel = ADC_POW_AD2_DELAY_20_US;
+    adc_0x50.b.adc_reg0x_aux_v09_1_delay_sel = ADC_POW_REF_DELAY_30_US;
+
+    ADCx->ADC_POW_DATA_DLY_CTRL = adc_0x50.d32;
+}
+
+void ADC_ManualModeConfig(void)
+{
+}
+
+void ADC_BypassRegConfig(uint8_t ChannelNum, FunctionalState NewState)
+{
+    if (NewState != DISABLE)
+    {
+        AUXADC_AON_REG0X1B94->bypassen_7_0 |= BIT(ChannelNum);
+    }
+    else
+    {
+        AUXADC_AON_REG0X1B94->bypassen_7_0 &= ~BIT(ChannelNum);
+    }
+}
+
+/**
+  * \brief  Store ADC register values when system enter DLPS.
+  * \param  PeriReg: Specifies to select the ADC peripheral.
+  * \param  StoreBuf: Store buffer to store ADC register data.
+  * \return None.
+  */
+RAM_FUNCTION
+void ADC_DLPSEnter(void *PeriReg, void *StoreBuf)
+{
+    ADCStoreReg_TypeDef *store_buf = (ADCStoreReg_TypeDef *)StoreBuf;
+
+    /*Open 10M clock source*/
+    RCC_PeriphClockCmd(APBPeriph_ADC, APBPeriph_ADC_CLOCK, ENABLE);
+
+    store_buf->adc_reg[0]         =  ADC->ADC_DIG_CTRL;         //0x04
+    store_buf->adc_reg[1]         =  ADC->ADC_SCHED_CTRL;       //0x08
+    store_buf->adc_reg[2]         =  ADC->ADC_CTRL_INT;         //0x0C
+
+    store_buf->adc_schtab_reg[0]  =  ADC->ADC_SCHTAB0;          //0x10
+    store_buf->adc_schtab_reg[1]  =  ADC->ADC_SCHTAB1;
+    store_buf->adc_schtab_reg[2]  =  ADC->ADC_SCHTAB2;          //0x14
+    store_buf->adc_schtab_reg[3]  =  ADC->ADC_SCHTAB3;
+    store_buf->adc_schtab_reg[4]  =  ADC->ADC_SCHTAB4;          //0x18
+    store_buf->adc_schtab_reg[5]  =  ADC->ADC_SCHTAB5;
+    store_buf->adc_schtab_reg[6]  =  ADC->ADC_SCHTAB6;          //0x1C
+    store_buf->adc_schtab_reg[7]  =  ADC->ADC_SCHTAB7;
+    store_buf->adc_schtab_reg[8]  =  ADC->ADC_SCHTAB8;          //0x20
+    store_buf->adc_schtab_reg[9]  =  ADC->ADC_SCHTAB9;
+    store_buf->adc_schtab_reg[10] =  ADC->ADC_SCHTAB10;         //0x24
+    store_buf->adc_schtab_reg[11] =  ADC->ADC_SCHTAB11;
+    store_buf->adc_schtab_reg[12] =  ADC->ADC_SCHTAB12;         //0x28
+    store_buf->adc_schtab_reg[13] =  ADC->ADC_SCHTAB13;
+    store_buf->adc_schtab_reg[14] =  ADC->ADC_SCHTAB14;         //0x2C
+    store_buf->adc_schtab_reg[15] =  ADC->ADC_SCHTAB15;
+
+    store_buf->adc_reg[3]         =  ADC->ADC_POW_DATA_DLY_CTRL;//0x50
+    store_buf->adc_reg[4]         =  ADC->ADC_DATA_CLK_CTRL;    //0x54
+    store_buf->adc_reg[5]         =  ADC->ADC_TIME_PERIOD;      //0x5C
+
+    return;
+}
+
+/**
+  * \brief  Restore ADC register values when system enter DLPS.
+  * \param  PeriReg: Specifies to select the ADC peripheral.
+  * \param  StoreBuf: Restore buffer to restore ADC register data.
+  * \return None
+  */
+RAM_FUNCTION
+void ADC_DLPSExit(void *PeriReg, void *StoreBuf)
+{
+    ADCStoreReg_TypeDef *store_buf = (ADCStoreReg_TypeDef *)StoreBuf;
+
+    /*Open 10M clock source*/
+    RCC_PeriphClockCmd(APBPeriph_ADC, APBPeriph_ADC_CLOCK, ENABLE);
+
+    /*Disable all interrupt.*/
+    ADC->ADC_CTRL_INT &= (~0x1f);
+
+    /* Set power mode first */
+    ADC->ADC_POW_DATA_DLY_CTRL = store_buf->adc_reg[3];
+
+    /* Disable schedule table */
+    ADC->ADC_SCHED_CTRL &= (~0xffff);
+
+    *(__IO uint32_t *)((uint32_t *)(&ADC->ADC_SCHTAB0))  = store_buf->adc_schtab_reg[0] |
+                                                           (store_buf->adc_schtab_reg[1] << 16);
+    *(__IO uint32_t *)((uint32_t *)(&ADC->ADC_SCHTAB2))  = store_buf->adc_schtab_reg[2] |
+                                                           (store_buf->adc_schtab_reg[3] << 16);
+    *(__IO uint32_t *)((uint32_t *)(&ADC->ADC_SCHTAB4))  = store_buf->adc_schtab_reg[4] |
+                                                           (store_buf->adc_schtab_reg[5] << 16);
+    *(__IO uint32_t *)((uint32_t *)(&ADC->ADC_SCHTAB6))  = store_buf->adc_schtab_reg[6] |
+                                                           (store_buf->adc_schtab_reg[7] << 16);
+    *(__IO uint32_t *)((uint32_t *)(&ADC->ADC_SCHTAB8))  = store_buf->adc_schtab_reg[8] |
+                                                           (store_buf->adc_schtab_reg[9] << 16);
+    *(__IO uint32_t *)((uint32_t *)(&ADC->ADC_SCHTAB10))  = store_buf->adc_schtab_reg[10] |
+                                                            (store_buf->adc_schtab_reg[11] << 16);
+    *(__IO uint32_t *)((uint32_t *)(&ADC->ADC_SCHTAB12))  = store_buf->adc_schtab_reg[12] |
+                                                            (store_buf->adc_schtab_reg[13] << 16);
+    *(__IO uint32_t *)((uint32_t *)(&ADC->ADC_SCHTAB14))  = store_buf->adc_schtab_reg[14] |
+                                                            (store_buf->adc_schtab_reg[15] << 16);
+
+    ADC->ADC_SCHED_CTRL     = store_buf->adc_reg[1];
+    ADC->ADC_DIG_CTRL       = (store_buf->adc_reg[0] & (~((uint32_t)0x03)));
+    ADC->ADC_DATA_CLK_CTRL  = store_buf->adc_reg[4];
+    ADC->ADC_TIME_PERIOD    = store_buf->adc_reg[5];
+
+    /*Clear ADC FIFO */
+    ADC->ADC_DIG_CTRL |= BIT26;
+    /* Clear all interrupt */
+    ADC->ADC_CTRL_INT |= (0x1f << 8);
+
+    /* Restore specify interrupt */
+    ADC->ADC_CTRL_INT = store_buf->adc_reg[2];
+
+    return;
+}
+
diff --git a/bee/drivers/adc/src/device/rtl87x2g/rtl_adc.c b/bee/drivers/adc/src/device/rtl87x2g/rtl_adc.c
new file mode 100644
index 00000000..e3c2b89a
--- /dev/null
+++ b/bee/drivers/adc/src/device/rtl87x2g/rtl_adc.c
@@ -0,0 +1,630 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *                        Header Files
+ *============================================================================*/
+#include "rtl_adc.h"
+#include "rtl_rcc.h"
+#if ADC_SUPPORT_POWER_ON_DELAY
+#include "utils.h"
+#endif
+
+/*============================================================================*
+ *                          Private Functions
+ *============================================================================*/
+extern void ADC_SISet(void);
+extern void ADC_DelayConfig(ADC_TypeDef *ADCx, ADC_InitTypeDef *ADC_InitStruct);
+extern void ADC_BypassRegConfig(uint8_t ChannelNum, FunctionalState NewState);
+extern void ADC_ManualModeConfig(void);
+extern void ADC_PowerOff(void);
+extern void ADC_ManualModePowerOn(void);
+extern void ADC_ManualModePowerOff(void);
+
+/*============================================================================*
+ *                           Public Functions
+ *============================================================================*/
+/**
+  * \brief  Deinitializes the ADC peripheral registers to their default reset values.
+  * \param  ADCx: selected ADC peripheral.
+  * \return None.
+  */
+void ADC_DeInit(ADC_TypeDef *ADCx)
+{
+    /* Check the parameters */
+    assert_param(IS_ADC_PERIPH(ADCx));
+
+#if ADC_SUPPORT_POWER_OFF
+    ADC_PowerOff();
+#endif
+
+    RCC_PeriphClockCmd(APBPeriph_ADC, APBPeriph_ADC_CLOCK, DISABLE);
+}
+
+/**
+  * \brief Initializes the ADC peripheral according to the specified
+  *   parameters in the ADC_InitStruct
+  * \param  ADCx: selected ADC peripheral.
+  * \param  ADC_InitStruct: pointer to a ADCInitTypeDef structure that
+  *   contains the configuration information for the specified ADC peripheral
+  * \return None
+  */
+void ADC_Init(ADC_TypeDef *ADCx, ADC_InitTypeDef *ADC_InitStruct)
+{
+    /* Check the parameters */
+    assert_param(IS_ADC_PERIPH(ADCx));
+    assert_param(IS_ADC_LATCH_MODE(ADC_InitStruct->ADC_DataLatchEdge));
+    assert_param(IS_ADC_POWER_MODE(ADC_InitStruct->ADC_PowerOnMode));
+    assert_param(IS_ADC_RG2X_0_DELAY_TIME(ADC_InitStruct->ADC_RG2X0Dly));
+    assert_param(IS_ADC_RG0X_1_DELAY_TIME(ADC_InitStruct->ADC_RG0X1Dly));
+    assert_param(IS_ADC_RG0X_0_DELAY_TIME(ADC_InitStruct->ADC_RG0X0Dly));
+    assert_param(IS_ADC_BURST_SIZE_CONFIG(ADC_InitStruct->ADC_WaterLevel));
+    assert_param(IS_ADC_FIFO_THRESHOLD(ADC_InitStruct->ADC_FifoThdLevel));
+
+    uint8_t index = 0;
+    uint32_t sch_ind = 0;
+    if (ADC_InitStruct->ADC_DataAvgEn == DISABLE)
+    {
+        ADC_InitStruct->ADC_DataAvgSel = 0x0;
+    }
+
+    /* Set SI */
+    ADC_SISet();
+
+    /* Disable all interrupt */
+    ADCx->ADC_CTRL_INT &= (~0x1f);
+
+    /* Set power mode first */
+    ADC_POW_DATA_DLY_CTRL_TypeDef adc_0x50 = {.d32 = ADCx->ADC_POW_DATA_DLY_CTRL};
+    adc_0x50.b.adc_poweron_select = 0x1; // bit 10
+#if ADC_SUPPORT_POWER_MODE_CTRL
+    adc_0x50.b.adc_manual_poweron = ADC_InitStruct->ADC_PowerOnMode; //default auto power mode
+#endif
+    adc_0x50.b.adc_poweron_only_en = ADC_InitStruct->ADC_PowerAlwaysOnEn;
+    adc_0x50.b.adc_data_delay =  ADC_InitStruct->ADC_DataLatchDly;
+    adc_0x50.b.adc_fifo_stop_wr = ADC_InitStruct->ADC_FifoStopWriteEn;
+    adc_0x50.b.adc_data_avg_en = ADC_InitStruct->ADC_DataAvgEn;
+    adc_0x50.b.adc_data_avg_sel = ADC_InitStruct->ADC_DataAvgSel;
+    ADCx->ADC_POW_DATA_DLY_CTRL = adc_0x50.d32;
+    ADC_DelayConfig(ADCx, ADC_InitStruct);
+
+#if ADC_SUPPORT_POWER_ON_DELAY
+    if (ADC_InitStruct->ADC_PowerOnDlyEn == ENABLE && ADC_InitStruct->ADC_PowerAlwaysOnEn == ENABLE)
+    {
+        /* After the ADC is powered up, there is a re-settle time of about 8ms,
+        during which the voltage acquired by the ADC has an error of about 0-10mV higher.
+        This error can be avoided by turning on this delay.
+        This delay is only effective when ADC_PowerAlwaysOnEn is set to ENABLE. */
+        platform_delay_ms(8);
+    }
+#endif
+
+    /* Set schedule table */
+
+    for (index = 0; index < 8; index++)
+    {
+        sch_ind = (ADC_InitStruct->ADC_SchIndex[index * 2]) | \
+                  (ADC_InitStruct->ADC_SchIndex[index * 2 + 1] << 16);
+        *(__IO uint32_t *)((uint32_t *)(&ADCx->ADC_SCHTAB0) + index) = sch_ind;
+    }
+#if CHIP_ADC_SCHEDULE_NUM > 16
+    for (Index = 0; index < 4; index++)
+    {
+        sch_ind = (ADC_InitStruct->ADC_SchIndex[16 + index] << 16);
+        *(__IO uint32_t *)((uint32_t *)(&ADCx->ADC_SCHTABD16) + index) = sch_ind;
+    }
+#endif
+
+    ADC_SCHED_CTRL_TypeDef adc_0x08 = {.d32 = ADCx->ADC_SCHED_CTRL};
+    adc_0x08.b.adc_schedule_idx_sel =  ADC_InitStruct->ADC_Bitmap;
+    ADCx->ADC_SCHED_CTRL = adc_0x08.d32;
+
+    /* Set ADC mode */
+    ADC_DIG_CTRL_TypeDef adc_0x04 = {.d32 = ADCx->ADC_DIG_CTRL};
+    adc_0x04.b.adc_one_shot_fifo = ADC_InitStruct->ADC_DataWriteToFifo;
+    adc_0x04.b.adc_fifo_thd = ADC_InitStruct->ADC_FifoThdLevel & 0x1F;
+    adc_0x04.b.adc_burst_size = ADC_InitStruct->ADC_WaterLevel;
+    adc_0x04.b.adc_fifo_overwrite = ADC_InitStruct->ADC_FifoOverWriteEn;
+#if ADC_SUPPORT_DMA_EN
+    adc_0x04.b.dma_mode = ADC_InitStruct->ADC_DmaEn;
+#endif
+    ADCx->ADC_DIG_CTRL = adc_0x04.d32;
+
+    ADC_DATA_CLK_CTRL_TypeDef adc_0x54 = {.d32 = ADCx->ADC_DATA_CLK_CTRL};
+    adc_0x54.b.adc_timer_trigger_en = ADC_InitStruct-> ADC_TimerTriggerEn;
+    adc_0x54.b.adc_data_align_msb = ADC_InitStruct->ADC_DataAlign;
+    adc_0x54.b.adc_data_offset_en = ADC_InitStruct->ADC_DataMinusEn;
+    adc_0x54.b.adc_data_offset = ADC_InitStruct->ADC_DataMinusOffset;
+    ADCx->ADC_DATA_CLK_CTRL = adc_0x54.d32;
+
+    ADC_TIME_PERIOD_TypeDef adc_0x5C = {.d32 = ADCx->ADC_TIME_PERIOD};
+    if (ADC_InitStruct->ADC_SampleTime >= 0x3FFF)
+    {
+        ADC_InitStruct->ADC_SampleTime = 0x3FFF;
+    }
+
+    adc_0x5C.b.adc_convert_time_period_sel = ADC_InitStruct->ADC_ConvertTime;
+    adc_0x5C.b.adc_sample_time_period = ADC_InitStruct->ADC_SampleTime;
+    ADCx->ADC_TIME_PERIOD = adc_0x5C.d32;
+
+    /*clear adc fifo*/
+    adc_0x04.b.adc_fifo_clr = 0x1;
+    ADCx->ADC_DIG_CTRL = adc_0x04.d32;
+
+    /*clear all interrupt*/
+    ADCx->ADC_CTRL_INT |= (0x1f << 8);
+
+    return;
+}
+
+/**
+  * \brief  Fills each ADC_InitStruct member with its default value.
+  * \param  ADC_InitStruct: pointer to an ADC_InitTypeDef structure which will be initialized.
+  * \return None
+  */
+void ADC_StructInit(ADC_InitTypeDef *ADC_InitStruct)
+{
+    ADC_InitStruct->ADC_SampleTime      = 0x3E7;
+    ADC_InitStruct->ADC_ConvertTime     = ADC_CONVERT_TIME_500NS;
+    ADC_InitStruct->ADC_DataWriteToFifo = DISABLE;
+    ADC_InitStruct->ADC_FifoThdLevel    = 0x06;
+    ADC_InitStruct->ADC_WaterLevel      = 0x1;
+    ADC_InitStruct->ADC_FifoOverWriteEn = ENABLE;
+    for (uint8_t i = 0; i < CHIP_ADC_SCHEDULE_NUM; ++i)
+    {
+        ADC_InitStruct->ADC_SchIndex[i] = 0;
+    }
+    ADC_InitStruct->ADC_Bitmap          = 0x0;
+    ADC_InitStruct->ADC_TimerTriggerEn  = DISABLE;
+    ADC_InitStruct->ADC_DataAlign       = ADC_DATA_ALIGN_LSB;
+    ADC_InitStruct->ADC_DataMinusEn     = DISABLE;
+    ADC_InitStruct->ADC_DataMinusOffset = 0;
+#if ADC_SUPPORT_DMA_EN
+    ADC_InitStruct->ADC_DmaEn           = DISABLE;
+#endif
+    ADC_InitStruct->ADC_FifoStopWriteEn = DISABLE;
+    ADC_InitStruct->ADC_DataAvgEn       = DISABLE;
+    ADC_InitStruct->ADC_DataAvgSel      = ADC_DATA_AVERAGE_OF_2;
+
+    /*Reserved parameter, please do not change values*/
+    ADC_InitStruct->ADC_PowerAlwaysOnEn = DISABLE;
+    ADC_InitStruct->ADC_DataLatchDly    = 0x1;
+#if ADC_SUPPORT_POWER_ON_DELAY
+    ADC_InitStruct->ADC_PowerOnDlyEn    = DISABLE;
+#endif
+#if ADC_SUPPORT_POWER_MODE_CTRL
+    ADC_InitStruct->ADC_PowerOnMode     = ADC_POWER_ON_AUTO;
+#endif
+    return;
+}
+
+/**
+  * \brief  Enable or disable the ADC peripheral.
+  * \param  ADCx: selected ADC peripheral.
+  * \param  AdcMode: adc mode select.
+  *         This parameter can be one of the following values:
+  *         \arg ADC_ONE_SHOT_MODE: one shot mode.
+  *         \arg ADC_CONTINUOUS_MODE: continuous mode.
+  * \param  NewState: new state of the ADC peripheral.
+  *         This parameter can be: ENABLE or DISABLE.
+  * \return None
+  */
+void ADC_Cmd(ADC_TypeDef *ADCx, ADCOperationMode_TypeDef AdcMode, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_ADC_PERIPH(ADCx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+    assert_param(IS_ADC_MODE(adcMode));
+
+    ADC_DIG_CTRL_TypeDef adc_0x04 = {.d32 = ADCx->ADC_DIG_CTRL};
+    if (NewState == ENABLE)
+    {
+#if ADC_SUPPORT_POWER_MODE_CTRL
+        ADC_POW_DATA_DLY_CTRL_TypeDef adc_0x50 = {.d32 = ADCx->ADC_POW_DATA_DLY_CTRL};
+        if (adc_0x50.b.adc_manual_poweron  == ADC_POWER_ON_MANUAL)
+        {
+            ADC_ManualModePowerOn();
+        }
+#endif
+        if (AdcMode == ADC_ONE_SHOT_MODE)
+        {
+            adc_0x04.b.en_adc_one_shot_mode = 1;
+            adc_0x04.b.en_adc_continous_mode = 0;
+        }
+        else
+        {
+            adc_0x04.b.en_adc_one_shot_mode = 0;
+            adc_0x04.b.en_adc_continous_mode = 1;
+        }
+    }
+    else
+    {
+#if ADC_SUPPORT_POWER_MODE_CTRL
+        ADC_POW_DATA_DLY_CTRL_TypeDef adc_0x50 = {.d32 = ADCx->ADC_POW_DATA_DLY_CTRL};
+        if (adc_0x50.b.adc_manual_poweron  == ADC_POWER_ON_MANUAL)
+        {
+            ADC_ManualModePowerOff();
+        }
+#endif
+        adc_0x04.b.en_adc_one_shot_mode = 0;
+        adc_0x04.b.en_adc_continous_mode = 0;
+    }
+    ADCx->ADC_DIG_CTRL = adc_0x04.d32;
+
+    return;
+}
+
+/**
+  * \brief  Enable or disable the specified ADC interrupts.
+  * \param  ADCx: selected ADC peripheral.
+  * \param  ADC_IT: specifies the ADC interrupts sources to be enabled or disabled.
+  *         This parameter can be any combination of the following values:
+  *         \arg ADC_INT_FIFO_RD_REQ :FIFO read request
+  *         \arg ADC_INT_FIFO_RD_ERR :FIFO read error
+  *         \arg ADC_INT_FIFO_THD :ADC FIFO size > thd
+  *         \arg ADC_INT_FIFO_FULL :ADC FIFO overflow
+  *         \arg ADC_INT_ONE_SHOT_DONE :ADC one shot mode done
+  * \param  NewState: new state of the specified ADC interrupts.
+  *         This parameter can be: ENABLE or DISABLE.
+  * \return None
+  */
+void ADC_INTConfig(ADC_TypeDef *ADCx, uint32_t ADC_IT, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_ADC_PERIPH(ADCx));
+    assert_param(IS_ADC_IT(ADC_IT));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (NewState != DISABLE)
+    {
+        ADCx->ADC_CTRL_INT |= ADC_IT;
+    }
+    else
+    {
+        ADCx->ADC_CTRL_INT &= (uint32_t)~ADC_IT;
+    }
+}
+
+/**
+  * \brief  Read ADC data according to specific channel.
+  * \param  ADCx: selected ADC peripheral.
+  * \param  Index: can be 0 to 15.
+  * \return The 12-bit converted ADC data.
+  */
+uint16_t ADC_ReadRawData(ADC_TypeDef *ADCx, uint8_t Index)
+{
+    /* Check the parameters */
+    assert_param(IS_ADC_PERIPH(ADCx));
+    assert_param(Index < CHIP_ADC_SCHEDULE_NUM);
+
+#if CHIP_ADC_SCHEDULE_NUM > 16
+    if (Index >= 16)
+    {
+        return (*(uint32_t *)((uint32_t *)(&ADCx->ADC_SCHTABD16) + Index - 16));
+    }
+#endif
+
+    if (Index & BIT(0))
+    {
+        return ((*(uint32_t *)((uint32_t *)(&ADCx->ADC_SCHD0) + (Index >> 1))) >> 16);
+    }
+    else
+    {
+        return (*(uint32_t *)((uint32_t *)(&ADCx->ADC_SCHD0) + (Index >> 1)));
+    }
+}
+
+/**
+  * \brief  Read ADC average data from ADC schedule table0.
+  * \param  ADCx: selected ADC peripheral.
+  * \param[out]  OutBuf: buffer to save data read from ADC FIFO.
+  * \return The 12-bit converted ADC data.
+  */
+uint16_t ADC_ReadAvgRawData(ADC_TypeDef *ADCx)
+{
+    /* Check the parameters */
+    assert_param(IS_ADC_PERIPH(ADCx));
+
+    return (uint16_t)(ADCx->ADC_SCHD0);
+}
+
+/**
+  * \brief  Get one data from ADC FIFO.
+  * \param  ADCx: selected ADC peripheral.
+  * \return Adc FIFO data.
+  */
+uint16_t ADC_ReadFIFO(ADC_TypeDef *ADCx)
+{
+    /* Check the parameters */
+    assert_param(IS_ADC_PERIPH(ADCx));
+
+    return (uint16_t)((ADCx->ADC_FIFO_READ) & 0xFFF);
+}
+
+/**
+  * \brief  Read data from ADC FIFO.
+  * \param  ADCx: selected ADC peripheral.
+  * \param[out]  outBuf: buffer to save data read from ADC FIFO.
+  * \param  Num: number of data to be read.
+  * \return None
+  */
+void ADC_ReadFIFOData(ADC_TypeDef *ADCx, uint16_t *outBuf, uint16_t Num)
+{
+    /* Check the parameters */
+    assert_param(IS_ADC_PERIPH(ADCx));
+
+    while (Num--)
+    {
+        *outBuf++ = (uint16_t)ADCx->ADC_FIFO_READ;
+    }
+
+    return;
+}
+
+/**
+  * \brief  Get ADC fifo data number.
+  * \param  ADCx: selected ADC peripheral.
+  * \return current data number in adc fifo.
+  */
+uint8_t ADC_GetFIFODataLen(ADC_TypeDef *ADCx)
+{
+    /* Check the parameters */
+    assert_param(IS_ADC_PERIPH(ADCx));
+
+    return ((uint8_t)(((ADCx->ADC_SCHED_CTRL) >> CHIP_ADC_SCHEDULE_NUM) & 0x3F));
+}
+
+
+void ADC_SchIndexConfig(ADC_TypeDef *ADCx, uint8_t AdcMode, uint16_t Index)
+{
+    /* Check the parameters */
+    assert_param(IS_ADC_PERIPH(ADCx));
+    assert_param(IS_ADC_SCHEDULE_INDEX_CONFIG(adcMode));
+
+#if CHIP_ADC_SCHEDULE_NUM > 16
+    if (index >= 16)
+    {
+        *(uint32_t *)((uint32_t *)(&ADCx->ADC_SCHTABD16) + Index - 16) |= (AdcMode << 16);
+    }
+#endif
+
+    if (Index & BIT0)
+    {
+        *(uint32_t *)((uint32_t *)(&ADCx->ADC_SCHTAB0) + (Index >> 1)) |= (AdcMode << 16);
+    }
+    else
+    {
+        *(uint32_t *)((uint32_t *)(&ADCx->ADC_SCHTAB0) + (Index >> 1)) |= AdcMode;
+    }
+
+    return;
+}
+
+/**
+  * \brief  Set adc schedule table.
+  * \param  ADCx: selected ADC peripheral.
+  * \param  BitMap: ADC bit map.
+  * \param  NewState: new state of the ADC peripheral.
+  *   This parameter can be: ENABLE or DISABLE.
+  * \return none.
+  */
+void ADC_BitMapConfig(ADC_TypeDef *ADCx, uint16_t BitMap)
+{
+    /* Check the parameters */
+    assert_param(IS_ADC_PERIPH(ADCx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    ADC_SCHED_CTRL_TypeDef adc_0x08 = {.d32 = ADCx->ADC_SCHED_CTRL};
+    adc_0x08.b.adc_schedule_idx_sel = BitMap;
+    ADCx->ADC_SCHED_CTRL = adc_0x08.d32;
+
+    return;
+}
+
+/**
+  * \brief  Enbale or disable write data to FIFO.
+  * \param  ADCx: selected ADC peripheral.
+  * \param  NewState: new state of the ADC fifo write.
+  *     This parameter can be: ENABLE or DISABLE.
+  * \return None
+  */
+void ADC_WriteFIFOCmd(ADC_TypeDef *ADCx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_ADC_PERIPH(ADCx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    ADC_DIG_CTRL_TypeDef adc_0x04 = {.d32 = ADCx->ADC_DIG_CTRL};
+    adc_0x04.b.adc_one_shot_fifo = NewState;
+    ADCx->ADC_DIG_CTRL = adc_0x04.d32;
+
+    return;
+}
+
+/**
+  * \brief  Config ADC bypass resistor.Attention!!!Channels using bypass mode cannot over 0.9V!!!!
+  * \param  ChannelNum: external channel number, can be 0~15.
+  * \param  NewState: ENABLE or DISABLE.
+  * \return None
+  */
+void ADC_BypassCmd(uint8_t ChannelNum, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(ChannelNum <= 16);
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    ADC_BypassRegConfig(ChannelNum, NewState);
+}
+
+/**
+  * \brief  Checks whether the specified ADC interrupt status flag is set or not.
+  * \param  ADCx: selected ADC peripheral.
+  * \param  ADC_INT_FLAG: specifies the interrupt status flag to check.
+  *     This parameter can be one of the following values:
+  *     \arg ADC_INT_ONE_SHOT_DONE: ADC once convert end interrupt
+  *     \arg ADC_INT_FIFO_OVERFLOW: ADC FIFO overflow interrupt
+  *     \arg ADC_INT_FIFO_THD: fifo larger than threshold
+  *     \arg ADC_INT_FIFO_RD_ERR: ADC read FIFO error interrupt
+  *     \arg ADC_INT_FIFO_RD_REQ: ADC read FIFO request interrupt
+  * \return The new state of ADC_INT (SET or RESET).
+  */
+ITStatus ADC_GetINTStatus(ADC_TypeDef *ADCx, uint32_t ADC_INT)
+{
+    /* Check the parameters */
+    assert_param(IS_ADC_PERIPH(ADCx));
+    assert_param(IS_ADC_INT(ADC_INT));
+
+    return ((ADCx->ADC_CTRL_INT & (ADC_INT << 16)) != 0);
+}
+
+/**
+  * \brief  Clear the ADC interrupt pending bit.
+  * \param  ADCx: selected ADC peripheral.
+  * \param  ADC_INT: specifies the interrupt pending bit to clear.
+  *         This parameter can be any combination of the following values:
+  *         \arg ADC_INT_ONE_SHOT_DONE: ADC once convert end interrupt
+  *         \arg ADC_INT_FIFO_OVERFLOW: ADC FIFO overflow interrupt
+  *         \arg ADC_INT_FIFO_THD: fifo larger than threshold
+  *         \arg ADC_INT_FIFO_RD_ERR: ADC read FIFO error interrupt
+  *         \arg ADC_INT_FIFO_RD_REQ: ADC read FIFO request interrupt
+  * \return None
+  */
+void ADC_ClearINTPendingBit(ADC_TypeDef *ADCx, uint32_t ADC_INT)
+{
+    /* Check the parameters */
+    assert_param(IS_ADC_PERIPH(ADCx));
+    assert_param(IS_ADC_INT(ADC_INT));
+
+    ADCx->ADC_CTRL_INT |= (ADC_INT << 8);
+
+    return;
+}
+
+/**
+  * \brief  Clear ADC FIFO.
+  * \param  ADCx: Specify ADC peripheral.
+  * \return None
+  */
+void ADC_ClearFIFO(ADC_TypeDef *ADCx)
+{
+    /* Check the parameters */
+    assert_param(IS_ADC_PERIPH(ADCx));
+
+    ADC_DIG_CTRL_TypeDef adc_0x04 = {.d32 = ADCx->ADC_DIG_CTRL};
+    adc_0x04.b.adc_fifo_clr = 0x1;
+    ADCx->ADC_DIG_CTRL = adc_0x04.d32;
+
+    return;
+}
+
+/**
+  * \brief  Get all adc interrupt flag status.
+  * \param  ADCx: Specify ADC peripheral.
+  * \return All ADC interrupt status.
+  */
+uint8_t ADC_GetAllFlagStatus(ADC_TypeDef *ADCx)
+{
+    /* Check the parameters */
+    assert_param(IS_ADC_PERIPH(ADCx));
+
+    return ((uint8_t)(((ADCx->ADC_CTRL_INT) & (0x1f << 16)) >> 16));
+}
+
+/**
+  * \brief  Clear ADC_FIFO_STOP_WRITE status. For ADC_FIFO_STOP_WRITE bit will be asserted automatically
+  *         as fifo overflow, need to be cleared in order to write data again.
+  * \param  ADCx: Specify ADC peripheral.
+  * \return All ADC interrupt status.
+  */
+void ADC_StopwriteFifoStatusClear(ADC_TypeDef *ADCx)
+{
+    /* Check the parameters */
+    assert_param(IS_ADC_PERIPH(ADCx));
+
+    ADC_POW_DATA_DLY_CTRL_TypeDef adc_0x50 = {.d32 = ADCx->ADC_POW_DATA_DLY_CTRL};
+    adc_0x50.b.adc_fifo_stop_wr = 0;
+    ADCx->ADC_POW_DATA_DLY_CTRL = adc_0x50.d32;
+
+    return;
+}
+
+/**
+  * \brief  Get the index state of ADC controller.
+  * \param  ADCx: Specify ADC peripheral.
+  * \return BIT[15:0] stores the data in the fifo, BIT[31:28] stores the index of the data.
+  */
+uint32_t ADC_ReadScheduleIndexandFifoData(ADC_TypeDef *ADCx)
+{
+    /* Check the parameters */
+    assert_param(IS_ADC_PERIPH(ADCx));
+
+    return ADCx->ADC_FIFO_READ ;
+}
+
+#if (ADC_SUPPORT_RAP_FUNCTION == 1)
+
+void ADC_RAPModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_ADC_ALL_PERIPH(ADCx));
+
+    ADC_TASK_CTRL_TypeDef adc_0x64 = {.d32 = ADCx->ADC_TASK_CTRL};
+    adc_0x64.b.adc_rap_mode = NewState;
+    ADCx->ADC_TASK_CTRL = adc_0x64.d32;
+
+    return;
+}
+
+void ADC_TaskTrigger(ADC_TypeDef *ADCx, uint32_t Task)
+{
+    /* Check the parameters */
+    assert_param(IS_ADC_ALL_PERIPH(ADCx));
+
+    ADC_TASK_CTRL_TypeDef adc_0x64 = {.d32 = ADCx->ADC_TASK_CTRL};
+    if (Task == ADC_TASK_ONE_SHOT_SAMPLE)
+    {
+        adc_0x64.b.adc_fw_task_one_shot_sample = 0x1;
+    }
+    ADCx->ADC_TASK_CTRL = adc_0x64.d32;
+
+    return;
+}
+
+void ADC_RAPICGCtrl(ADC_TypeDef *ADCx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_ADC_ALL_PERIPH(ADCx));
+
+    ADC_QACTIVE_CTRL_TypeDef adc_0x68 = {.d32 = ADCx->ADC_QACTIVE_CTRL};
+    adc_0x68.b.qact_pclk_icg_en = NewState;
+    ADCx->ADC_QACTIVE_CTRL = adc_0x68.d32;
+
+    return;
+}
+
+void ADC_RAPQactiveCtrl(ADC_TypeDef *ADCx, uint32_t Qactive, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_ADC_ALL_PERIPH(ADCx));
+
+    ADC_QACTIVE_CTRL_TypeDef adc_0x68 = {.d32 = ADCx->ADC_QACTIVE_CTRL};
+    if (Qactive == ADC_QACTIVE_FW_SCLK_FORCE)
+    {
+        adc_0x68.b.qact_sclk_force_en = NewState;
+    }
+    if (Qactive == ADC_QACTIVE_FW_PCLK_FORCE)
+    {
+        adc_0x68.b.qact_pclk_force_en = NewState;
+    }
+    if (Qactive == ADC_QACTIVE_FW_PCLK_ICG)
+    {
+        adc_0x68.b.qact_pclk_icg_en = NewState;
+    }
+    ADCx->ADC_QACTIVE_CTRL = adc_0x68.d32;
+
+    return;
+}
+#endif
diff --git a/bee/drivers/adc/src/device/rtl87x2g/rtl_adc.h b/bee/drivers/adc/src/device/rtl87x2g/rtl_adc.h
new file mode 100644
index 00000000..f3e5b567
--- /dev/null
+++ b/bee/drivers/adc/src/device/rtl87x2g/rtl_adc.h
@@ -0,0 +1,953 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *               Define to prevent recursive inclusion
+ *============================================================================*/
+#ifndef RTL_ADC_H
+#define RTL_ADC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*============================================================================*
+ *                        Header Files
+ *============================================================================*/
+#include "utils/rtl_utils.h"
+#include "rtl_adc_def.h"
+#include "adc_lib.h"
+
+/** \defgroup ADC         ADC
+  * \brief
+  * \{
+  */
+
+/*============================================================================*
+ *                         Constants
+ *============================================================================*/
+/** \defgroup ADC_Exported_Constants ADC Exported Constants
+  * \brief
+  * \{
+  */
+
+/**
+ * \defgroup    ADC_Channel_Index ADC Channel Index
+ * \{
+ * \ingroup     ADC_Exported_Constants
+ */
+#define ADC_Channel_Index_0           0   //!< ADC channel 0.
+#define ADC_Channel_Index_1           1   //!< ADC channel 1.
+#define ADC_Channel_Index_2           2   //!< ADC channel 2.
+#define ADC_Channel_Index_3           3   //!< ADC channel 3.
+#define ADC_Channel_Index_4           4   //!< ADC channel 4.
+#if (CHIP_ADC_CHANNEL_NUM > 4)
+#define ADC_Channel_Index_5           5   //!< ADC channel 5.
+#define ADC_Channel_Index_6           6   //!< ADC channel 6.
+#define ADC_Channel_Index_7           7   //!< ADC channel 7.
+#endif
+#if (CHIP_ADC_CHANNEL_NUM > 8)
+#define ADC_Channel_Index_8           8   //!< ADC channel 8.
+#define ADC_Channel_Index_9           9   //!< ADC channel 9.
+#define ADC_Channel_Index_10          10  //!< ADC channel 10.
+#define ADC_Channel_Index_11          11  //!< ADC channel 11.
+#define ADC_Channel_Index_12          12  //!< ADC channel 12.
+#define ADC_Channel_Index_13          13  //!< ADC channel 13.
+#define ADC_Channel_Index_14          14  //!< ADC channel 14.
+#define ADC_Channel_Index_15          15  //!< ADC channel 15.
+#endif
+#define IS_ADC_CHANNEL(ch)      ((ch) < CHIP_ADC_CHANNEL_NUM) //!< Specify the maximum ADC channel number.
+
+/** End of ADC_Channel_Index
+  * \}
+  */
+
+/**
+ * \defgroup    ADC_Schedule_Index ADC Schedule Index
+ * \{
+ * \ingroup     ADC_Exported_Constants
+ */
+#define ADC_Schedule_Index_0          0    //!< ADC schedule index 0.
+#define ADC_Schedule_Index_1          1    //!< ADC schedule index 1.
+#define ADC_Schedule_Index_2          2    //!< ADC schedule index 2.
+#define ADC_Schedule_Index_3          3    //!< ADC schedule index 3.
+#define ADC_Schedule_Index_4          4    //!< ADC schedule index 4.
+#define ADC_Schedule_Index_5          5    //!< ADC schedule index 5.
+#define ADC_Schedule_Index_6          6    //!< ADC schedule index 6.
+#define ADC_Schedule_Index_7          7    //!< ADC schedule index 7.
+#define ADC_Schedule_Index_8          8    //!< ADC schedule index 8.
+#define ADC_Schedule_Index_9          9    //!< ADC schedule index 9.
+#define ADC_Schedule_Index_10         10   //!< ADC schedule index 10.
+#define ADC_Schedule_Index_11         11   //!< ADC schedule index 11.
+#define ADC_Schedule_Index_12         12   //!< ADC schedule index 12.
+#define ADC_Schedule_Index_13         13   //!< ADC schedule index 13.
+#define ADC_Schedule_Index_14         14   //!< ADC schedule index 14.
+#define ADC_Schedule_Index_15         15   //!< ADC schedule index 15.
+#if (CHIP_ADC_SCHEDULE_NUM > 16)
+#define ADC_Schedule_Index_16         16   //!< ADC schedule index 16.
+#define ADC_Schedule_Index_17         17   //!< ADC schedule index 17.
+#define ADC_Schedule_Index_18         18   //!< ADC schedule index 18.
+#define ADC_Schedule_Index_19         19   //!< ADC schedule index 19.
+#endif
+#define IS_ADC_SCH_INDEX(IDEX) ((IDEX) < CHIP_ADC_SCHEDULE_NUM) //!< Specify the maximum ADC schedule number.
+
+/** End of ADC_Schedule_Index
+  * \}
+  */
+
+/**
+ * \defgroup    ADC_Schedule_Table ADC Channel and Mode
+ * \{
+ * \ingroup     ADC_Exported_Constants
+ */
+#define SCHEDULE_TABLE(Index)         (Index) //!< ADC schedule table index.
+#define EXT_SINGLE_ENDED(Index)       ((uint16_t)((ADC_MODE_SINGLE_ENDED_VALUE << CHIP_ADC_MODE_OFFSET) | (Index))) //!< External single-ended mode. Index can be  refered to \ref ADC_Channel_Index. 
+#define EXT_DIFFERENTIAL(Index)       ((uint16_t)((ADC_MODE_DIFFERENTIAL_VALUE << CHIP_ADC_MODE_OFFSET) | (Index))) //!< External differential mode. Index can be  refered to \ref ADC_Channel_Index.
+
+#define INTERNAL_VBAT_MODE            ((uint16_t)((ADC_MODE_INTERNAL_VALUE << CHIP_ADC_MODE_OFFSET) | 0x00)) //!< Internal VBAT mode.
+#if ADC_SUPPORT_VADPIN_MODE
+#define INTERNAL_VADPIN_MODE          ((uint16_t)((ADC_MODE_INTERNAL_VALUE << CHIP_ADC_MODE_OFFSET) | 0x01)) //!< Internal VADPIN mode.
+#endif
+
+
+#if ADC_SUPPORT_VADPIN_MODE
+#define IS_ADC_SCHEDULE_INDEX_CONFIG(CONFIG) (((CONFIG) & (0xffff << 2 << CHIP_ADC_MODE_OFFSET)) == 0 && \
+                                              ((IS_ADC_SCH_INDEX((CONFIG) & (~(0xffff << CHIP_ADC_MODE_OFFSET))) && \
+                                                (CONFIG & BIT(CHIP_ADC_MODE_OFFSET + 1) == 0)) || \
+                                               (CONFIG) == INTERNAL_VBAT_MODE || \
+                                               (CONFIG) == INTERNAL_VADPIN_MODE)) //!< Check if the input parameter is valid.
+#else
+#define IS_ADC_SCHEDULE_INDEX_CONFIG(CONFIG) (((CONFIG) & (0xffff << 2 << CHIP_ADC_MODE_OFFSET)) == 0 && \
+                                              ((IS_ADC_SCH_INDEX((CONFIG) & (~(0xffff << CHIP_ADC_MODE_OFFSET))) && \
+                                                (CONFIG & BIT(CHIP_ADC_MODE_OFFSET + 1) == 0)) || \
+                                               (CONFIG) == INTERNAL_VBAT_MODE)) //!< Check if the input parameter is valid.
+#endif
+
+/** End of ADC_Schedule_Table
+  * \}
+  */
+
+/**
+ * \defgroup    ADC_Convert_Time ADC Convert Time
+ * \{
+ * \ingroup     ADC_Exported_Constants
+ */
+typedef enum
+{
+    ADC_CONVERT_TIME_500NS,  //!< ADC Convert time is 500ns.
+    ADC_CONVERT_TIME_700NS,  //!< ADC Convert time is 700ns.
+    ADC_CONVERT_TIME_900NS,  //!< ADC Convert time is 900ns.
+    ADC_CONVERT_TIME_1100NS, //!< ADC Convert time is 1100ns.
+} ADCConvertTim_TypeDef;
+
+#define IS_ADC_CONVERT_TIME(TIME) (((TIME) == ADC_CONVERT_TIME_500NS) || \
+                                   ((TIME) == ADC_CONVERT_TIME_700NS) || \
+                                   ((TIME) == ADC_CONVERT_TIME_900NS) || \
+                                   ((TIME) == ADC_CONVERT_TIME_1100NS)) //!< Check if the input parameter is valid.
+
+/** End of ADC_Convert_Time
+  * \}
+  */
+
+/**
+ * \defgroup    ADC_Latch_Data_Edge ADC Latch Data Edge
+ * \{
+ * \ingroup     ADC_Exported_Constants
+ */
+typedef enum
+{
+    ADC_LATCH_DATA_Positive, //!< ADC latch data at positive clock edge.
+    ADC_LATCH_DATA_Negative, //!< ADC latch data at negative clock edge.
+} ADCDataLatchEdge_TypeDef;
+
+#define IS_ADC_LATCH_MODE(MODE) (((MODE) == ADC_LATCH_DATA_Positive) || ((MODE) == ADC_LATCH_DATA_Negative)) //!< Check if the input parameter is valid.
+
+/** End of ADC_Latch_Data_Edge
+  * \}
+  */
+
+/**
+ * \defgroup    ADC_Data_Align ADC Data Align
+ * \{
+ * \ingroup     ADC_Exported_Constants
+ */
+typedef enum
+{
+    ADC_DATA_ALIGN_LSB, //!< ADC data storage format is LSB.
+    ADC_DATA_ALIGN_MSB, //!< ADC data storage format is MSB.
+} ADCAlign_TypeDef;
+
+#define IS_ADC_DATA_ALIGN(DATA_ALIGN) (((DATA_ALIGN) == ADC_DATA_ALIGN_LSB) || ((DATA_ALIGN) == ADC_DATA_ALIGN_MSB)) //!< Check if the input parameter is valid.
+
+/** End of ADC_Data_Align
+  * \}
+  */
+
+/**
+ * \defgroup    ADC_Raw_Data_Average ADC Raw Data Average
+ * \{
+ * \ingroup     ADC_Exported_Constants
+ */
+typedef enum
+{
+    ADC_DATA_AVERAGE_OF_2,    //!< 2 data used to calculate average.
+    ADC_DATA_AVERAGE_OF_4,    //!< 4 data used to calculate average.
+    ADC_DATA_AVERAGE_OF_8,    //!< 8 data used to calculate average.
+    ADC_DATA_AVERAGE_OF_16,   //!< 16 data used to calculate average.
+    ADC_DATA_AVERAGE_OF_32,   //!< 32 data used to calculate average.
+    ADC_DATA_AVERAGE_OF_64,   //!< 64 data used to calculate average.
+    ADC_DATA_AVERAGE_OF_128,  //!< 128 data used to calculate average.
+    ADC_DATA_AVERAGE_OF_256,  //!< 256 data used to calculate average.
+    ADC_DATA_AVERAGE_MAX,     //!< The largest enumeration value.
+} ADCDataAvgSel_TypeDef;
+
+#define IS_ADC_DATA_AVG_NUM(NUM) (((NUM) == ADC_DATA_AVERAGE_OF_2) || \
+                                  ((NUM) == ADC_DATA_AVERAGE_OF_4) || \
+                                  ((NUM) == ADC_DATA_AVERAGE_OF_8) || \
+                                  ((NUM) == ADC_DATA_AVERAGE_OF_16) || \
+                                  ((NUM) == ADC_DATA_AVERAGE_OF_32) || \
+                                  ((NUM) == ADC_DATA_AVERAGE_OF_64) || \
+                                  ((NUM) == ADC_DATA_AVERAGE_OF_128) || \
+                                  ((NUM) == ADC_DATA_AVERAGE_OF_256)) //!< Check if the input parameter is valid.
+
+/** End of ADC_Data_Average
+  * \}
+  */
+
+
+/**
+ * \defgroup    ADC_FIFO_Threshold ADC FIFO Threshold
+ * \{
+ * \ingroup     ADC_Exported_Constants
+ */
+#define IS_ADC_FIFO_THRESHOLD(THD) ((THD) <= 0x3F) //!< ADC FIFO threshold is between 0 and 0x3F.
+
+/** End of ADC_FIFO_Threshold
+  * \}
+  */
+
+/**
+ * \defgroup    ADC_Burst_Size ADC Burst Size
+ * \{
+ * \ingroup     ADC_Exported_Constants
+ */
+#define IS_ADC_BURST_SIZE_CONFIG(CONFIG) ((CONFIG) <= 0x3F) //!< ADC burst size is between 0 and 0x3F.
+
+/** End of ADC_Burst_Size
+  * \}
+  */
+
+/**
+ * \defgroup    ADC_Operation_Mode ADC Operation Mode
+ * \{
+ * \ingroup     ADC_Exported_Constants
+ */
+typedef enum
+{
+    ADC_CONTINUOUS_MODE, //!< ADC continuous mode.
+    ADC_ONE_SHOT_MODE,   //!< ADC one shot mode.
+} ADCOperationMode_TypeDef;
+
+#define IS_ADC_MODE(MODE) (((MODE) == ADC_CONTINUOUS_MODE) || ((MODE) == ADC_ONE_SHOT_MODE)) //!< Check if the input parameter is valid.
+
+/** End of ADC_Operation_Mode
+  * \}
+  */
+
+/**
+ * \defgroup    ADC_Power_Mode  ADC Power Mode
+ * \{
+ * \ingroup     ADC_Exported_Constants
+ */
+typedef enum
+{
+    ADC_POWER_ON_AUTO,     //!< The power mode of ADC is auto mode.
+    ADC_POWER_ON_MANUAL,   //!< The power mode of ADC is manual mode.
+} ADCPowerMode_TypeDef;
+
+#define IS_ADC_POWER_MODE(MODE) (((MODE) == ADC_POWER_ON_AUTO) || ((MODE) == ADC_POWER_ON_MANUAL)) //!< Check if the input parameter is valid.
+
+/** End of ADC_Power_Mode
+  * \}
+  */
+
+/**
+ * \defgroup    ADC_Interrupts_Definition ADC Interrupts Definition
+ * \{
+ * \ingroup     ADC_Exported_Constants
+ */
+#define ADC_INT_FIFO_RD_REQ           ((uint32_t)(1 << 0)) //!< ADC GDMA request interrupt. When FIFO data level achieve the GDMA threshold level (ADC_WaterLevel), this interrupt is triggered.
+#define ADC_INT_FIFO_RD_ERR           ((uint32_t)(1 << 1)) //!< ADC FIFO read error interrupt. When read the empty FIFO, this interrupt is triggered.
+#define ADC_INT_FIFO_THD              ((uint32_t)(1 << 2)) //!< ADC FIFO threshold interrupt. When FIFO data number is more than or equal to the threshold level (ADC_FifoThdLevel), this interrupt is triggered.
+#if ADC_SUPPORT_INT_FIFO_FULL
+#define ADC_INT_FIFO_FULL             ((uint32_t)(1 << 3)) //!< ADC FIFO full interrupt. When FIFO full, this interrupt is triggered.
+#else
+#define ADC_INT_FIFO_OVERFLOW         ((uint32_t)(1 << 3)) //!< ADC FIFO overflow interrupt. When FIFO overflow, this interrupt is triggered.
+#endif
+#define ADC_INT_ONE_SHOT_DONE         ((uint32_t)(1 << 4)) //!< ADC one shot mode done interrupt. When ADC conversion done, this interrupt is triggered.
+#if ADC_SUPPORT_INT_FIFO_FULL
+#define ADC_INT_FIFO_OVERFLOW         ((uint32_t)(1 << 5)) //!< ADC FIFO overflow interrupt. When FIFO overflow, this interrupt is triggered.
+#endif
+
+#if ADC_SUPPORT_INT_FIFO_FULL
+#define IS_ADC_INT(INT) (((INT) == ADC_INT_FIFO_RD_REQ) || \
+                         ((INT) == ADC_INT_FIFO_RD_ERR) || \
+                         ((INT) == ADC_INT_FIFO_THD) || \
+                         ((INT) == ADC_INT_FIFO_OVERFLOW) || \
+                         ((INT) == ADC_INT_ONE_SHOT_DONE) || \
+                         ((INT) == ADC_INT_FIFO_FULL))     //!< Check if the input parameter is valid.
+#else
+#define IS_ADC_INT(INT) (((INT) == ADC_INT_FIFO_RD_REQ) || \
+                         ((INT) == ADC_INT_FIFO_RD_ERR) || \
+                         ((INT) == ADC_INT_FIFO_THD) || \
+                         ((INT) == ADC_INT_FIFO_OVERFLOW) || \
+                         ((INT) == ADC_INT_ONE_SHOT_DONE)) //!< Check if the input parameter is valid.
+#endif
+
+/** End of ADC_Interrupts_Definition
+  * \}
+  */
+
+#if (ADC_SUPPORT_RAP_FUNCTION == 1)
+
+/**
+ * \defgroup    ADC_Qactive_Force TIM Qactive Force
+ * \{
+ * \ingroup     ADC_Exported_Constants
+ */
+typedef enum
+{
+    ADC_QACTIVE_FW_SCLK_FORCE = 0x0,
+    ADC_QACTIVE_FW_PCLK_FORCE = 0x1,
+    ADC_QACTIVE_FW_PCLK_ICG = 0x1,
+} ADCQactiveForce_TypeDef;
+
+/** End of ADC_Qactive_Force
+  * \}
+  */
+
+/**
+ * \defgroup    ADC_Task TIM Task
+ * \{
+ * \ingroup     ADC_Exported_Constants
+ */
+typedef enum
+{
+    ADC_TASK_ONE_SHOT_SAMPLE = 0,
+} ADCTask_TypeDef;
+
+/** End of ADC_Task
+  * \}
+  */
+
+#endif
+
+
+/** End of ADC_Exported_Constants
+  * \}
+  */
+
+/*============================================================================*
+ *                         Types
+ *============================================================================*/
+/** \defgroup ADC_Exported_Types ADC Exported Types
+  * \brief
+  * \{
+  */
+
+/**
+ * \brief       ADC init structure definition.
+ *
+ * \ingroup     ADC_Exported_Types
+ */
+typedef struct
+{
+    uint16_t ADC_SampleTime;                /*!< Specify the ADC Sample clock. (ADC_SampleTime+1) cycles of 10MHz.
+                                                 This parameter can be a value of 19 to 16383. */
+
+    ADCConvertTim_TypeDef ADC_ConvertTime;  /**< Specify the ADC Sample convert time.
+                                                 This parameter can be a value of \ref ADC_Convert_Time. */
+
+    FunctionalState ADC_DataWriteToFifo;    /*!< Write ADC one shot mode data into FIFO.
+                                                 This parameter can be a value of DISABLE or ENABLE. */
+
+    uint8_t ADC_FifoThdLevel;               /*!< Specify the ADC FIFO threshold to trigger interrupt ADC_INT_FIFO_TH.
+                                                 This parameter can be a value of 0 to 31. */
+
+    uint8_t ADC_WaterLevel;                 /*!< Specify the ADC FIFO Burst Size to trigger GDMA.
+                                                 This parameter can be a value of 0 to 31. */
+
+    FunctionalState ADC_FifoOverWriteEn;    /*!< Specify if over write FIFO when FIFO overflow.
+                                                 This parameter can be a value of DISABLE or ENABLE. */
+
+#if ADC_SUPPORT_DMA_EN
+    FunctionalState ADC_DmaEn;              /*!< Enable or disable the DMA function of ADC.
+                                                 This parameter can be a value of DISABLE or ENABLE. */
+#endif
+
+    uint16_t ADC_SchIndex[CHIP_ADC_SCHEDULE_NUM]; /*!< Specify ADC mode and channel for schedule table.*/
+
+    uint32_t ADC_Bitmap;                    /*!< Specify the schedule table channel map.
+                                                 This parameter can be a value of 16Bits map. */
+
+    FunctionalState ADC_TimerTriggerEn;     /*!< Enable or disable ADC one-shot mode when tim7 toggles.
+                                                 This parameter can be a value of DISABLE or ENABLE. */
+
+    ADCAlign_TypeDef ADC_DataAlign;         /*!< ADC Data MSB or LSB aligned.
+                                                 This parameter can be a value of \ref ADC_Data_Align. */
+
+    FunctionalState ADC_DataMinusEn;        /**< Enable or disable function that adc data latched
+                                                 minus the given offset before writes to reg/FIFO. */
+
+    uint16_t ADC_DataMinusOffset;           /**< Offset to be minused from adc data latched.
+                                                 This parameter can be a value of 0 to 4095. */
+
+    ADCDataAvgSel_TypeDef ADC_DataAvgSel;   /**< Number of data for calculate average.
+                                                 This parameter can be a value of \ref ADC_Raw_Data_Average. */
+
+    uint8_t ADC_DataAvgEn;                  /**< Enable or disable the calculation for average result of the one shot data.
+                                                 This parameter can be a value of DISABLE or ENABLE. */
+
+    uint8_t ADC_DataLatchDly;               /*!< Specify specify the number of the beginning data from ADC output to be discarded. */
+
+    FunctionalState ADC_FifoStopWriteEn;    /*!< Stop fifo from writing data. This bit will be asserted
+                                                 automatically as fifo overflow, (not automatically when
+                                                 ADC_FIFO_OVER_WRITE_ENABLE), need to be cleared in order
+                                                 to write data again. This will not stop overwrite mode. */
+
+    ADCPowerMode_TypeDef ADC_PowerOnMode;   /**< Specify ADC power on mode.
+                                                 This parameter can be a value of \ref ADC_Power_Mode. */
+
+    FunctionalState ADC_PowerAlwaysOnEn;    /*!< Enable or disable the power always on.
+                                                 This parameter can be a value of DISABLE or ENABLE. */
+
+#if ADC_SUPPORT_POWER_ON_DELAY
+    FunctionalState ADC_PowerOnDlyEn;       /*!< Enable or disable ADC 8ms delay after adc power on.
+                                                 This parameter can be a value of DISABLE or ENABLE. */
+#endif
+} ADC_InitTypeDef;
+
+/** End of ADC_Exported_Types
+  * \}
+  */
+
+/*============================================================================*
+ *                         Functions
+ *============================================================================*/
+/** \defgroup ADC_Exported_Functions ADC Exported Functions
+  * \brief
+  * \{
+  */
+
+/**
+ * \brief   Deinitialize the ADC peripheral registers to their
+ *          default reset values(turn off ADC clock).
+ *
+ * \param[in] ADCx  Specify ADC peripheral, can only be ADC.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_adc_init(void)
+ * {
+ *     //Turn off the clock.
+ *     ADC_DeInit(ADC);
+ * }
+ * \endcode
+ */
+void ADC_DeInit(ADC_TypeDef *ADCx);
+
+/**
+ * \brief Initialize the ADC peripheral according to the specified parameters in the ADC_InitStruct
+ *
+ * \param[in]  ADCx            Select ADC peripheral.
+ * \param[in]  ADC_InitStruct  Pointer to a ADC_InitTypeDef structure which will be initialized.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_adc_init(void)
+ * {
+ *     //Turn on the clock.
+ *     RCC_PeriphClockCmd(APBPeriph_ADC, APBPeriph_ADC_CLOCK, ENABLE);
+
+ *     ADC_InitTypeDef ADC_InitStruct;
+ *     ADC_StructInit(&ADC_InitStruct);
+ *     ADC_InitStruct.ADC_SchIndex[0] = EXT_SINGLE_ENDED(0);
+ *     ADC_InitStruct.ADC_SchIndex[1] = EXT_SINGLE_ENDED(1);
+ *     ADC_InitStruct.ADC_Bitmap = 0x03;
+ *     //Add other initialization parameters that need to be configured here.
+ *     ADC_Init(ADC, &ADC_InitStruct);
+ * }
+ * \endcode
+ */
+void ADC_Init(ADC_TypeDef *ADCx, ADC_InitTypeDef *ADC_InitStruct);
+
+/**
+ * \brief   Fill each ADC_InitStruct member with its default value.
+ *
+ * \note   The default settings for the ADC_InitStruct member are shown in the following table:
+ *         | ADC_InitStruct member   | Default value                   |
+ *         |:-----------------------:|:-------------------------------:|
+ *         | ADC_SampleTime          | 0x3E7                           |
+ *         | ADC_ConvertTime         | \ref ADC_CONVERT_TIME_500NS     |
+ *         | ADC_DataWriteToFifo     | DISABLE                         |
+ *         | ADC_FifoThdLevel        | 0x06                            |
+ *         | ADC_WaterLevel          | 0x1                             |
+ *         | ADC_FifoOverWriteEn     | ENABLE                          |
+ *         | ADC_SchIndex[16]        | 0                               |
+ *         | ADC_Bitmap              | 0x0                             |
+ *         | ADC_TimerTriggerEn      | DISABLE                         |
+ *         | ADC_DataAlign           | \ref ADC_DATA_ALIGN_LSB         |
+ *         | ADC_DataMinusEn         | DISABLE                         |
+ *         | ADC_DataMinusOffset     | 0                               |
+ *         | ADC_FifoStopWriteEn     | DISABLE                         |
+ *         | ADC_DataAvgEn           | DISABLE                         |
+ *         | ADC_DataAvgSel          | \ref ADC_DATA_AVERAGE_OF_2      |
+ *         | ADC_PowerAlwaysOnEn     | DISABLE                         |
+ *         | ADC_DataLatchDly        | 0x1                             |
+ *         | ADC_PowerOnDlyEn        | DISABLE                         |
+ *
+ * \param[in] ADC_InitStruct  Pointer to an ADC_InitTypeDef structure which will be initialized.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_adc_init(void)
+ * {
+ *     //Turn on the clock.
+ *     RCC_PeriphClockCmd(APBPeriph_ADC, APBPeriph_ADC_CLOCK, ENABLE);
+
+ *     ADC_InitTypeDef ADC_InitStruct;
+ *     ADC_StructInit(&ADC_InitStruct);
+ *     ADC_InitStruct.ADC_SchIndex[0] = EXT_SINGLE_ENDED(0);
+ *     ADC_InitStruct.ADC_SchIndex[1] = EXT_SINGLE_ENDED(1);
+ *     ADC_InitStruct.ADC_Bitmap = 0x03;
+ *     //Add other initialization parameters that need to be configured here.
+ *     ADC_Init(ADC, &ADC_InitStruct);
+ * }
+ * \endcode
+ * \callgraph
+ *
+ */
+void ADC_StructInit(ADC_InitTypeDef *ADC_InitStruct);
+
+/**
+ * \brief   Enable or disable the ADC peripheral.
+ *
+ * \param[in] ADCx      Specify ADC peripheral.
+ * \param[in] AdcMode   ADC operation mode selection.
+ *                      This parameter can be one of the following values:
+ *                      \arg ADC_ONE_SHOT_MODE: One shot mode.
+ *                      \arg ADC_CONTINUOUS_MODE: Continuous sampling mode.
+ * \param[in] NewState  New state of the ADC peripheral.
+ *                      This parameter can be one of the following values:
+ *                      - ENABLE: Enable the specified ADC peripheral.
+ *                      - DISABLE: Disable the specified ADC peripheral.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void board_adc_init(void)
+ * {
+ *     Pad_Config(P2_0, PAD_SW_MODE, PAD_IS_PWRON, PAD_PULL_NONE, PAD_OUT_DISABLE,
+ *                PAD_OUT_LOW);
+ *
+ *     Pad_Config(P2_1, PAD_SW_MODE, PAD_IS_PWRON, PAD_PULL_NONE, PAD_OUT_DISABLE,
+ *                PAD_OUT_LOW);
+ * }
+ *
+ * void driver_adc_init(void)
+ * {
+ *     //open clock
+ *     RCC_PeriphClockCmd(APBPeriph_ADC, APBPeriph_ADC_CLOCK, ENABLE);
+ *
+ *     ADC_InitTypeDef ADC_InitStruct;
+ *     ADC_StructInit(&ADC_InitStruct);
+ *     ADC_InitStruct.ADC_SchIndex[0] = EXT_SINGLE_ENDED(0);
+ *     ADC_InitStruct.ADC_SchIndex[1] = EXT_SINGLE_ENDED(1);
+ *     ADC_InitStruct.ADC_Bitmap = 0x03;
+ *     //Add other initialization parameters here.
+ *     ADC_Init(ADC, &ADC_InitStruct);
+ *
+ *     ADC_INTConfig(ADC, ADC_INT_ONE_SHOT_DONE, ENABLE);
+ * }
+ *
+ * void adc_demo(void)
+ * {
+ *     board_adc_init();
+ *     driver_adc_init();
+ *     ADC_Cmd(ADC, ADC_ONE_SHOT_MODE, ENABLE);
+ * }
+ * \endcode
+ */
+void ADC_Cmd(ADC_TypeDef *ADCx, ADCOperationMode_TypeDef AdcMode, FunctionalState NewState);
+
+/**
+ * \brief   Enable or disable the specified ADC interrupts.
+ *
+ * \param[in] ADCx      Specify ADC peripheral.
+ * \param[in] ADC_IT    Specify the ADC interrupts sources to be enabled or disabled.
+ *                      This parameter can be any combination of the following values.
+ *                      Refer to \ref ADC_Interrupts_Definition.
+ *                      \arg ADC_INT_FIFO_RD_REQ : FIFO read request.
+ *                      \arg ADC_INT_FIFO_RD_ERR : FIFO read error.
+ *                      \arg ADC_INT_FIFO_THD : ADC FIFO size > thd.
+ *                      \arg ADC_INT_FIFO_OVERFLOW : ADC FIFO overflow.
+ *                      \arg ADC_INT_ONE_SHOT_DONE : ADC one shot mode done.
+ * \param[in] NewState  New state of the specified ADC interrupt.
+ *                      This parameter can be one of the following values:
+ *                      - ENABLE: Enable the specified ADC interrupts.
+ *                      - DISABLE: Disable the specified ADC interrupts.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_adc_init(void)
+ * {
+ *     //open clock
+ *     RCC_PeriphClockCmd(APBPeriph_ADC, APBPeriph_ADC_CLOCK, ENABLE);
+ *
+ *     ADC_InitTypeDef ADC_InitStruct;
+ *     ADC_StructInit(&ADC_InitStruct);
+ *     ADC_InitStruct.ADC_SchIndex[0] = EXT_SINGLE_ENDED(0);
+ *     ADC_InitStruct.ADC_SchIndex[1] = EXT_SINGLE_ENDED(1);
+ *     ADC_InitStruct.ADC_Bitmap = 0x03;
+ *     //Add other initialization parameters here.
+ *     ADC_Init(ADC, &ADC_InitStruct);
+ *
+ *     ADC_INTConfig(ADC, ADC_INT_FIFO_RD_ERR, ENABLE);
+ *     ADC_INTConfig(ADC, ADC_INT_ONE_SHOT_DONE, ENABLE);
+ * }
+ * \endcode
+ *
+ */
+void ADC_INTConfig(ADC_TypeDef *ADCx, uint32_t ADC_INT, FunctionalState NewState);
+
+/**
+ * \brief      Read ADC data according to specific channel.
+ *
+ * \param[in]  ADCx   Specify ADC peripheral.
+ * \param[in]  Index  Can be 0 to 15.
+ *
+ * \return     The 12-bit converted ADC raw data.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void adc_demo(void)
+ * {
+ *     board_adc_init();
+ *     driver_adc_init();
+ *     ADC_Cmd(ADC, ADC_ONE_SHOT_MODE, ENABLE);
+ *     while(ADC_GetINTStatus(ADC, ADC_INT_ONE_SHOT_DONE) == RESET);
+ *     uint16_t raw_data_0 = ADC_ReadRawData(ADC, 0);
+ *     uint16_t raw_data_1 = ADC_ReadRawData(ADC, 1);
+ * }
+ * \endcode
+ */
+uint16_t ADC_ReadRawData(ADC_TypeDef *ADCx, uint8_t Index);
+
+/**
+ * \brief   Get ADC average data from ADC schedule table0.
+ *
+ * \param[in]  ADCx  Specify ADC peripheral.
+ *
+ * \return  The 12-bit converted ADC raw data.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void adc_demo(void)
+ * {
+ *     board_adc_init();
+ *     driver_adc_init();
+ *     ADC_Cmd(ADC, ADC_ONE_SHOT_MODE, ENABLE);
+ *     while(ADC_GetINTStatus(ADC, ADC_INT_ONE_SHOT_DONE) == RESET);
+ *     uint16_t raw_data = 0;
+ *     raw_data = ADC_ReadAvgRawData(ADC);
+ * }
+ * \endcode
+ *
+ */
+uint16_t ADC_ReadAvgRawData(ADC_TypeDef *ADCx);
+
+/**
+ * \brief  Read one byte data from ADC FIFO.
+ *
+ * \param[in]  ADCx  Select ADC peripheral.
+ *
+ * \return ADC FIFO data.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void adc_demo(void)
+ * {
+ *     board_adc_init();
+ *     driver_adc_init();
+ *     ADC_Cmd(ADC, ADC_ONE_SHOT_MODE, ENABLE);
+ *     while(ADC_GetINTStatus(ADC, ADC_INT_ONE_SHOT_DONE) == RESET);
+ *     uint16_t raw_data = 0;
+ *     raw_data = ADC_ReadFIFO(ADC);
+ * }
+ * \endcode
+ */
+uint16_t ADC_ReadFIFO(ADC_TypeDef *ADCx);
+
+/**
+ * \brief   Get data from ADC FIFO.
+ *
+ * \param[in]  ADCx    Specify ADC peripheral.
+ * \param[out] outBuf  Buffer to save data read from ADC FIFO.
+ * \param[in]  Num     Number of data to be read.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void adc_demo(void)
+ * {
+ *     //ADC already start
+ *     uint16_t raw_data[32] = {0};
+ *     uint8_t data_len = ADC_GetFIFODataLen(ADC);
+ *     ADC_ReadFIFOData(ADC,raw_data,data_len);
+ * }
+ * \endcode
+ *
+ */
+void ADC_ReadFIFOData(ADC_TypeDef *ADCx, uint16_t *outBuf, uint16_t Num);
+
+/**
+ * \brief   Get ADC FIFO data number.
+ *
+ * \param[in] ADCx  Select ADC peripheral.
+ *
+ * \return  Current data number in ADC FIFO.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void adc_demo(void)
+ * {
+ *     //ADC already start
+ *     uint16_t raw_data[32] = {0};
+ *     uint8_t data_len = ADC_GetFIFODataLen(ADC);
+ *     ADC_ReadFIFOData(ADC,raw_data,data_len);
+ * }
+ * \endcode
+ *
+ */
+uint8_t ADC_GetFIFODataLen(ADC_TypeDef *ADCx);
+
+/**
+ * \brief   Config ADC schedule table.
+ *
+ * \param[in] ADCx     Specify ADC peripheral.
+ * \param[in] AdcMode  ADC operation mode.
+ *                     This parameter can be one of the following values:
+ *                     \arg EXT_SINGLE_ENDED(index): Single-ended mode, the input is external channel index.
+ *                     \arg EXT_DIFFERENTIAL(index): Differential mode, the positive input is external channel index,
+ *                     the negative input external channel index1.
+ *                     \arg INTERNAL_VBAT_MODE: The input is internal battery voltage detection channel.
+ * \param[in] Index:   Schedule table index.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void adc_demo(void)
+ * {
+ *     ADC_SchIndexConfig(ADC,INTERNAL_VBAT_MODE,0);
+ * }
+ * \endcode
+ *
+ */
+void ADC_SchIndexConfig(ADC_TypeDef *ADCx, uint8_t AdcMode, uint16_t Index);
+
+/**
+ * \brief   Config ADC bit map.
+ *
+ * \param[in]  ADCx      Specify ADC peripheral.
+ * \param[in]  BitMap    ADC bit map.
+ * \param[in]  NewState  New state of the ADC peripheral.
+ *                       This parameter can be one of the following values:
+ *                       - ENABLE: Enable ADC bit map.
+ *                       - DISABLE: Disable ADC bit map.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void adc_demo(void)
+ * {
+ *     uint16_t bit_map = 0x03;
+ *     ADC_BitMapConfig(ADC,bit_map);
+ * }
+ * \endcode
+ */
+void ADC_BitMapConfig(ADC_TypeDef *ADCx, uint16_t BitMap);
+
+/**
+ * \brief   Enbale or disable write data to FIFO.
+ *
+ * \param[in] ADCx      Specify ADC peripheral.
+ * \param[in] NewState  New state of the ADC FIFO write.
+ *                      This parameter can be one of the following values:
+ *                      - ENABLE: Enable the stop of FIFO writing data.
+ *                      - DISABLE: Disable the stop of FIFO writing data.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void adc_demo(void)
+ * {
+ *     ADC_WriteFIFOCmd(ADC, ENABLE);
+ * }
+ * \endcode
+ */
+void ADC_WriteFIFOCmd(ADC_TypeDef *ADCx, FunctionalState NewState);
+
+/**
+ * \brief     Config ADC bypass resistor.
+ *
+ * \param[in] channelNum  External channel number, can be 0~7.
+ * \param[in] NewState    Specify whether the channel enables bypass mode.
+ *                        This parameter can be one of the following values:
+ *                        - ENABLE: Enable ADC bypass function.
+ *                        - DISABLE: Disable ADC bypass function.
+ *
+ * \attention The input voltage of channel pin using bypass mode cannot exceed 0.9V!
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void adc_demo(void)
+ * {
+ *     ADC_BypassCmd(0,ENABLE);
+ * }
+ * \endcode
+ */
+void ADC_BypassCmd(uint8_t ChannelNum, FunctionalState NewState);
+
+/**
+ * \brief  Get the specified ADC interrupt flag status.
+ *
+ * \param[in]  ADCx          Select ADC peripheral.
+ * \param[in]  ADC_INT_FLAG  Specify the interrupt flag to check.
+ *                           This parameter can be one of the following values.
+ *                           Refer to \ref ADC_Interrupts_Definition.
+ *                           \arg ADC_INT_ONE_SHOT_DONE: ADC once convert end interrupt.
+ *                           \arg ADC_INT_FIFO_OVERFLOW: ADC FIFO overflow interrupt.
+ *                           \arg ADC_INT_FIFO_THD: FIFO larger than threshold interrupt.
+ *                           \arg ADC_INT_FIFO_RD_ERR: ADC read FIFO error interrupt.
+ *                           \arg ADC_INT_FIFO_RD_REQ: ADC read FIFO request interrupt.
+ *
+ * \return The status of ADC interrupt.
+ *         - SET: The ADC interrupt status is set.
+ *         - RESET: The ADC interrupt status is reset.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void adc_demo(void)
+ * {
+ *     ITStatus int_status = RESET;
+ *     int_status = ADC_GetINTStatus(ADC,ADC_INT_FIFO_OVERFLOW);
+ * }
+ * \endcode
+ */
+ITStatus ADC_GetINTStatus(ADC_TypeDef *ADCx, uint32_t ADC_INT);
+
+/**
+ * \brief  Clear the ADC interrupt pending bit.
+ *
+ * \param[in] ADCx     Specify ADC peripheral.
+ * \param[in] ADC_INT  Specify the interrupt pending bit to clear.
+ *                     This parameter can be any combination of the following values.
+ *                     Refer to \ref ADC_Interrupts_Definition.
+ *                     - ADC_INT_ONE_SHOT_DONE: ADC once convert end interrupt.
+ *                     - ADC_INT_FIFO_OVERFLOW: ADC FIFO overflow interrupt.
+ *                     - ADC_INT_FIFO_THD: FIFO larger than threshold interrupt.
+ *                     - ADC_INT_FIFO_RD_ERR: ADC read FIFO error interrupt.
+ *                     - ADC_INT_FIFO_RD_REQ: ADC read FIFO request interrupt.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void adc_demo(void)
+ * {
+ *     ADC_ClearINTPendingBit(ADC,ADC_INT_FIFO_OVERFLOW);
+ * }
+ * \endcode
+ */
+void ADC_ClearINTPendingBit(ADC_TypeDef *ADCx, uint32_t ADC_INT);
+
+/**
+ * \brief   Clear ADC FIFO.
+ *
+ * \param[in] ADCx  Specify ADC peripheral.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void adc_demo(void)
+ * {
+ *     ADC_ClearFIFO(ADC);
+ * }
+ * \endcode
+ */
+void ADC_ClearFIFO(ADC_TypeDef *ADCx);
+
+/**
+ * \brief   Get all adc interrupt flag status.
+ *
+ * \param[in] ADCx  Specify ADC peripheral.
+ *
+ * \return  All ADC interrupt status.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void adc_demo(void)
+ * {
+ *     uint8_t all_flag_status = 0;
+ *     all_flag_status = ADC_GetAllFlagStatus(ADC);
+ * }
+ * \endcode
+ *
+ */
+uint8_t ADC_GetAllFlagStatus(ADC_TypeDef *ADCx);
+
+/**
+ * \brief  Get the index state of ADC controller.
+ *
+ * \param[in]  ADCx  Specify ADC peripheral.
+ *
+ * \return BIT[15:0] stores the data in the FIFO, BIT[31:28] stores the index of the data.
+ */
+uint32_t ADC_ReadScheduleIndexandFifoData(ADC_TypeDef *ADCx);
+
+#if (ADC_SUPPORT_RAP_FUNCTION == 1)
+
+void ADC_RAPModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState);
+
+void ADC_RAPQactiveCtrl(ADC_TypeDef *ADCx, uint32_t Qactive, FunctionalState NewState);
+
+void ADC_TaskTrigger(ADC_TypeDef *ADCx, uint32_t Task);
+
+#endif
+
+/** End of ADC_Exported_Functions
+  * \}
+  */
+
+/** End of ADC
+  * \}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RTL_ADC_H */
diff --git a/bee/drivers/adc/src/device/rtl87x2g/rtl_adc_def.h b/bee/drivers/adc/src/device/rtl87x2g/rtl_adc_def.h
new file mode 100644
index 00000000..697a1ff0
--- /dev/null
+++ b/bee/drivers/adc/src/device/rtl87x2g/rtl_adc_def.h
@@ -0,0 +1,428 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef RTL_ADC_DEF_H
+#define RTL_ADC_DEF_H
+
+#include "utils/rtl_utils.h"
+#include "address_map.h"
+#include "aon_reg.h"
+
+#ifdef  __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/*============================================================================*
+ *                         ADC Defines
+ *============================================================================*/
+/** \defgroup ADC         ADC
+  * \brief
+  * \{
+  */
+
+/** \defgroup ADC_Exported_Constants ADC Exported Constants
+  * \brief
+  * \{
+  */
+
+/**
+ * \defgroup ADC_Defines ADC Defines
+ * \{
+ * \ingroup  ADC_Exported_Constants
+ */
+#define CHIP_ADC_CHANNEL_NUM                           (8) //!< The chip supports 8 ADC channel.
+#define CHIP_ADC_SCHEDULE_NUM                          (16)//!< The chip supports 16 ADC schedule index.
+#define CHIP_ADC_MODE_OFFSET                           (3) //!< The chip supports 3 ADC mode
+#define ADC_SUPPORT_DMA_EN                             (0) //!< The function is not supported.
+#define ADC_SUPPORT_INT_FIFO_FULL                      (0) //!< The function is not supported.
+#define ADC_SUPPORT_VADPIN_MODE                        (0) //!< The function is not supported.
+#define ADC_SUPPORT_POWER_OFF                          (1) //!< The chip supports power off
+#define ADC_SUPPORT_POWER_ON_DELAY                     (1) //!< The chip supports power on delay
+
+/** End of ADC_Defines
+  * \}
+  */
+
+/** End of ADC_Exported_Constants
+  * \}
+  */
+
+/** End of ADC
+  * \}
+  */
+/*============================================================================*
+ *                         ADC Registers Memory Map
+ *============================================================================*/
+typedef struct
+{
+    __I  uint32_t ADC_FIFO_READ;              /*!< 0x00 */
+    __IO uint32_t ADC_DIG_CTRL;               /*!< 0x04 */
+    __IO uint32_t ADC_SCHED_CTRL;             /*!< 0x08 */
+    __IO uint32_t ADC_CTRL_INT;               /*!< 0x0C */
+    __IO uint16_t ADC_SCHTAB0;                /*!< 0x10 */
+    __IO uint16_t ADC_SCHTAB1;
+    __IO uint16_t ADC_SCHTAB2;                /*!< 0x14 */
+    __IO uint16_t ADC_SCHTAB3;
+    __IO uint16_t ADC_SCHTAB4;                /*!< 0x18 */
+    __IO uint16_t ADC_SCHTAB5;
+    __IO uint16_t ADC_SCHTAB6;                /*!< 0x1C */
+    __IO uint16_t ADC_SCHTAB7;
+    __IO uint16_t ADC_SCHTAB8;                /*!< 0x20 */
+    __IO uint16_t ADC_SCHTAB9;
+    __IO uint16_t ADC_SCHTAB10;               /*!< 0x24 */
+    __IO uint16_t ADC_SCHTAB11;
+    __IO uint16_t ADC_SCHTAB12;               /*!< 0x28 */
+    __IO uint16_t ADC_SCHTAB13;
+    __IO uint16_t ADC_SCHTAB14;               /*!< 0x2C */
+    __IO uint16_t ADC_SCHTAB15;
+    __I  uint16_t ADC_SCHD0;                  /*!< 0x30 */
+    __I  uint16_t ADC_SCHD1;
+    __I  uint16_t ADC_SCHD2;                  /*!< 0x34 */
+    __I  uint16_t ADC_SCHD3;
+    __I  uint16_t ADC_SCHD4;                  /*!< 0x38 */
+    __I  uint16_t ADC_SCHD5;
+    __I  uint16_t ADC_SCHD6;                  /*!< 0x3C */
+    __I  uint16_t ADC_SCHD7;
+    __I  uint16_t ADC_SCHD8;                  /*!< 0x40 */
+    __I  uint16_t ADC_SCHD9;
+    __I  uint16_t ADC_SCHD10;                 /*!< 0x44 */
+    __I  uint16_t ADC_SCHD11;
+    __I  uint16_t ADC_SCHD12;                 /*!< 0x48 */
+    __I  uint16_t ADC_SCHD13;
+    __I  uint16_t ADC_SCHD14;                 /*!< 0x4C */
+    __I  uint16_t ADC_SCHD15;
+    __IO uint32_t ADC_POW_DATA_DLY_CTRL;      /*!< 0x50 */
+    __IO uint32_t ADC_DATA_CLK_CTRL;          /*!< 0x54 */
+    __IO uint32_t RSVD1;                      /*!< 0x58 */
+    __IO uint32_t ADC_TIME_PERIOD;            /*!< 0x5C */
+    __IO uint32_t RSVD2;                      /*!< 0x60 */
+} ADC_TypeDef;
+
+/*============================================================================*
+ *                         ADC Declaration
+ *============================================================================*/
+#define ADC                     ((ADC_TypeDef *) SAR_ADC_REG_BASE)
+#define IS_ADC_PERIPH(PERIPH)   ((PERIPH) == ADC)
+/*============================================================================*
+ *                         ADC Private Types
+ *============================================================================*/
+typedef struct
+{
+    uint32_t adc_reg[6];
+    uint32_t adc_schtab_reg[16];
+} ADCStoreReg_TypeDef;
+
+/*============================================================================*
+ *                         ADC Registers and Field Descriptions
+ *============================================================================*/
+/**
+* @brief Analog to digital converter. (ADC)
+*/
+/* 0x00
+    11:0    R      adc_fifo_data_out               12'h0
+    15:12   R      reserved_dummy00_15_12          4'h0
+    27:16   R      reserved_dummy00_27_16          12'h0
+    31:28   R      adc_schedule_index              4'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        const uint32_t adc_fifo_data_out: 12;
+        const uint32_t reserved_1: 4;
+        const uint32_t reserved_0: 12;
+        const uint32_t adc_schedule_index: 4;
+    } b;
+} ADC_FIFO_READ_TypeDef;
+
+
+
+/* 0x04
+    0       R/W    en_adc_continous_mode           1'h0
+    1       W1C    en_adc_one_shot_mode            1'h0
+    2       R/W    reserved_dummy04_02             1'h0
+    7:3     R      adc_fifo_wpt                    5'h0
+    12:8    R      adc_fifo_rpt                    5'h0
+    13      R/W    adc_fifo_overwrite              1'h0
+    19:14   R/W    adc_burst_size                  6'h0
+    25:20   R/W    adc_fifo_thd                    6'h0
+    26      W1C    adc_fifo_clr                    1'h0
+    27      R/W    adc_one_shot_fifo               1'h0
+    29:28   R      reserved_dummy04_29_28          2'h0
+    31:30   R/W    adc_dbg_sel                     2'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t en_adc_continous_mode: 1;
+        uint32_t en_adc_one_shot_mode: 1;
+        const uint32_t reserved_1: 1;
+        const uint32_t adc_fifo_wpt: 5;
+        const uint32_t adc_fifo_rpt: 5;
+        uint32_t adc_fifo_overwrite: 1;
+        uint32_t adc_burst_size: 6;
+        uint32_t adc_fifo_thd: 6;
+        uint32_t adc_fifo_clr: 1;
+        uint32_t adc_one_shot_fifo: 1;
+        const uint32_t reserved_0: 2;
+        uint32_t adc_dbg_sel: 2;
+    } b;
+} ADC_DIG_CTRL_TypeDef;
+
+
+
+/* 0x08
+    16:0    R/W    adc_schedule_idx_sel            16'h0
+    16:20   R      adc_fifo_data_level             6'h0
+    31:22   R      reserved_dummy08_31_22          19'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t adc_schedule_idx_sel: 16;
+        const uint32_t adc_fifo_data_level: 6;
+        const uint32_t reserved_0: 10;
+    } b;
+} ADC_SCHED_CTRL_TypeDef;
+
+
+
+/* 0x0C
+    0       R/W    en_adc_fifio_rd_req_interrupt   1'h0
+    1       R/W    en_adc_fifo_rd_error_interrupt  1'h0
+    2       R/W    en_adc_fifo_thd_interrupt       1'h0
+    3       R/W    en_adc_fifo_overflow_interrupt  1'h0
+    4       R/W    en_adc_one_shot_done_interrupt  1'h0
+    7:5     R      reserved_dummy0c_7_5            3'h0
+    8       W1C    clr_adc_fifio_rd_req_interrupt  1'h0
+    9       W1C    clr_adc_fifo_rd_error_interrupt 1'h0
+    10      W1C    clr_adc_fifo_thd_interrupt      1'h0
+    11      W1C    clr_adc_fifo_overflow_interrupt 1'h0
+    12      W1C    clr_adc_one_shot_done_interrupt 1'h0
+    15:13   R      reserved_dummy0c_15_13          3'h0
+    16      R      st_adc_fifio_rd_req_interrupt   1'h0
+    17      R      st_adc_fifo_rd_error_interrupt  1'h0
+    18      R      st_adc_fifo_thd_interrupt       1'h0
+    19      R      st_adc_fifo_overflow_interrupt  1'h0
+    20      R      st_adc_one_shot_done_interrupt  1'h0
+    31:21   R      reserved_dummy0c_31_21          11'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t en_adc_fifio_rd_req_interrupt: 1;
+        uint32_t en_adc_fifo_rd_error_interrupt: 1;
+        uint32_t en_adc_fifo_thd_interrupt: 1;
+        uint32_t en_adc_fifo_overflow_interrupt: 1;
+        uint32_t en_adc_one_shot_done_interrupt: 1;
+        const uint32_t reserved_2: 3;
+        uint32_t clr_adc_fifio_rd_req_interrupt: 1;
+        uint32_t clr_adc_fifo_rd_error_interrupt: 1;
+        uint32_t clr_adc_fifo_thd_interrupt: 1;
+        uint32_t clr_adc_fifo_overflow_interrupt: 1;
+        uint32_t clr_adc_one_shot_done_interrupt: 1;
+        const uint32_t reserved_1: 3;
+        const uint32_t st_adc_fifio_rd_req_interrupt: 1;
+        const uint32_t st_adc_fifo_rd_error_interrupt: 1;
+        const uint32_t st_adc_fifo_thd_interrupt: 1;
+        const uint32_t st_adc_fifo_overflow_interrupt: 1;
+        const uint32_t st_adc_one_shot_done_interrupt: 1;
+        const uint32_t reserved_0: 11;
+    } b;
+} ADC_CTRL_INT_TypeDef;
+
+
+
+/* 0x10-0x2C
+    3:0     R/W    ch_num_idx0                     4'h0
+    5:4     R/W    adc_mode_idx0                   2'h0
+    15:6    R      reserved_dummy10_15_5           10'h0
+*/
+typedef union
+{
+    uint32_t d16;
+    uint8_t d8[2];
+    struct
+    {
+        uint32_t ch_num_idx: 4;
+        uint32_t adc_mode_idx: 2;
+        const uint32_t reserved: 10;
+    } b;
+} ADC_SCHED_TAB_IDX_TypeDef;
+
+
+/* 0x30-0x4c
+    11:0    R      adc_idx_output_data            12'h0
+    15:12   R      reserved_dummy30_15_12          4'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        const uint32_t adc_idx_output_data: 12;
+        const uint32_t reserved_1: 4;
+    } b;
+} ADC_IDX_OUTPUT_DATA_TypeDef;
+
+
+/* 0x50
+    1:0     R/W    adc_reg0x_aux_v09_1_delay_sel   2'h0
+    3:2     R/W    adc_reg0x_ldo_2_delay_sel       2'h0
+    5:4     R/W    adc_reg0x_ldo_1_delay_sel       2'h0
+    8:6     R/W    adc_data_delay                  3'h1
+    9       R      reserved_dummy50_9              1'h0
+    14:10   R/W    adc_poweron_select              5'h0
+    15      R/W    adc_poweron_only_en             1'h0
+    18:16   R      reserved_dummy50_18_16          3'h0
+    19      R/W    adc_manual_poweron              1'h0
+    20      R      reserved_dummy50_20             1'h0
+    21      R/W    adc_fifo_stop_wr                1'h0
+    23:22   R      reserved_dummy50_23_22          2'h0
+    24      R/W    adc_data_avg_en                 1'h0
+    27:25   R/W    adc_data_avg_sel                3'h0
+    30:28   R      reserved_dummy50_30_28          3'h0
+    31      R/W    reserved_dummy50_31             1'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t adc_reg0x_aux_v09_1_delay_sel: 2;
+        uint32_t adc_reg0x_ldo_2_delay_sel: 2;
+        uint32_t adc_reg0x_ldo_1_delay_sel: 2;
+        uint32_t adc_data_delay: 3;
+        const uint32_t reserved_5: 1;
+        uint32_t adc_poweron_select: 5;
+        uint32_t adc_poweron_only_en: 1;
+        const uint32_t reserved_4: 3;
+        uint32_t adc_manual_poweron: 1;
+        const uint32_t reserved_3: 1;
+        uint32_t adc_fifo_stop_wr: 1;
+        const uint32_t reserved_2: 2;
+        uint32_t adc_data_avg_en: 1;
+        uint32_t adc_data_avg_sel: 3;
+        const uint32_t reserved_1: 3;
+        uint32_t reserved_0: 1;
+    } b;
+} ADC_POW_DATA_DLY_CTRL_TypeDef;
+
+
+
+/* 0x54
+    7:0     R      reserved_dummy54_7_0            8'h0
+    8       R/W    adc_keep_ck_ad_high             1'h0
+    10:9    R      reserved_dummy54_10_9           2'h0
+    12:11   R/W    adc_delay_tune_sel              2'h0
+    15:13   R      reserved_dummy54_15_13          3'h0
+    27:16   R/W    adc_data_offset                 12'h0
+    28      R      reserved_dummy54_28             1'h0
+    29      R/W    adc_timer_trigger_en            1'h0
+    30      R/W    adc_data_align_msb              1'h0
+    31      R/W    adc_data_offset_en              1'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        const uint32_t reserved_3: 8;
+        uint32_t adc_keep_ck_ad_high: 1;
+        const uint32_t reserved_2: 2;
+        uint32_t adc_delay_tune_sel: 2;
+        const uint32_t reserved_1: 3;
+        uint32_t adc_data_offset: 12;
+        const uint32_t reserved_0: 1;
+        uint32_t adc_timer_trigger_en: 1;
+        uint32_t adc_data_align_msb: 1;
+        uint32_t adc_data_offset_en: 1;
+    } b;
+} ADC_DATA_CLK_CTRL_TypeDef;
+
+/* 0x5C
+    13:0    R/W    adc_sample_time_period          14'h3E7
+    29:14   R      reserved_dummy5c_29_14          16'h0
+    31:30   R/W    adc_convert_time_period_sel     2'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t adc_sample_time_period: 14;
+        const uint32_t reserved_0: 16;
+        uint32_t adc_convert_time_period_sel: 2;
+    } b;
+} ADC_TIME_PERIOD_TypeDef;
+
+
+/*============================================================================*
+ *                          ADC MODE Wrappers
+ *============================================================================*/
+/** \defgroup ADC        ADC
+  * \brief
+  * \{
+  */
+
+/** \defgroup ADC_Exported_Constants ADC Exported Constants
+  * \brief
+  * \{
+  */
+
+/**
+ * \defgroup ADC_Constant_Wrapper ADC Constant Wrapper
+ * \{
+ * \ingroup  ADC_Exported_Constants
+ */
+#define ADC_MODE_SINGLE_ENDED_VALUE     0x0 //!< ADC single ended value
+#define ADC_MODE_DIFFERENTIAL_VALUE     0x1 //!< ADC differential value
+#define ADC_MODE_INTERNAL_VALUE         0x2 //!< ADC internal value
+#define ADC_MODE_RESERVED_VALUE         0x3 //!< ADC reserved value
+
+/** End of ADC_Constant_Wrapper
+  * \}
+  */
+
+/**
+ * \defgroup ADC_Function_Wrapper ADC Function Wrapper
+ * \{
+ * \ingroup  ADC_Exported_Constants
+ */
+#define ADC_SchTableConfig(ADCx, Index, AdcMode) ADC_SchIndexConfig(ADCx, AdcMode, Index) //!< The macro is a wrapper for ADC_SchIndexConfig(ADCx, AdcMode, Index).
+
+/** End of ADC_Function_Wrapper
+  * \}
+  */
+
+/** End of ADC_Exported_Constants
+  * \}
+  */
+
+/** End of ADC
+  * \}
+  */
+
+#ifdef  __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* RTL_ADC_DEF_H */
diff --git a/bee/drivers/adc/src/device/rtl87x2j/rtl87x2j_adc.c b/bee/drivers/adc/src/device/rtl87x2j/rtl87x2j_adc.c
new file mode 100644
index 00000000..8e9a1eeb
--- /dev/null
+++ b/bee/drivers/adc/src/device/rtl87x2j/rtl87x2j_adc.c
@@ -0,0 +1,145 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *                           Header Files
+ *============================================================================*/
+#include "rtl_adc.h"
+#include "rtl_rcc.h"
+#include "utils.h"
+
+/*============================================================================*
+ *                           Private Macros
+ *============================================================================*/
+#define ADC_CLOCK_AUTO_MODE_CONFIG_AUTOMATIC       (0x00)
+#define ADC_CLOCK_AUTO_MODE_CONFIG_ALWAYSRUN       (0x7E)//Force off 0x54
+
+extern uint16_t adc_bypass_status;
+
+/*============================================================================*
+ *                           Public Functions
+ *============================================================================*/
+
+void ADC_PowerOff(void)
+{
+    /*Power off control flow!*/
+}
+
+void ADC_SampleTimeConfig(ADC_InitTypeDef *ADC_InitStruct)
+{
+    uint8_t adc_divide_mode = 0;
+    uint8_t adc_bitnum = 0;
+    uint8_t adc_sch_table = 0;
+    uint8_t adc_mode = 0;
+    uint8_t adc_channel;
+    uint16_t adc_bitmap = ADC->ADC_SCHED_CTRL & 0xFFFF;
+
+    while (adc_bitmap)
+    {
+        adc_bitnum = __builtin_ffs(adc_bitmap) - 1;
+        adc_bitmap &= ~BIT(adc_bitnum);
+        adc_sch_table = (adc_bitnum & 0x1) ? \
+                        ((*((volatile uint32_t *)(&ADC->ADC_SCHTAB0) + (adc_bitnum >> 1))) >> 16) :
+                        (*((volatile uint32_t *)(&ADC->ADC_SCHTAB0) + (adc_bitnum >> 1))) ;
+        adc_mode = (adc_sch_table >> 3) & 0x3;
+        adc_channel = adc_sch_table & 0x7;
+
+        if (adc_mode == ADC_MODE_INTERNAL_VALUE)
+        {
+            adc_divide_mode = 1;
+            break;
+        }
+
+        if ((BIT(adc_channel) & adc_bypass_status) != BIT(adc_channel))
+        {
+            adc_divide_mode = 1;
+            break;
+        }
+    }
+
+    uint16_t min_time = adc_divide_mode ? 18 : 3;
+    uint16_t max_time = 0x3FFF;
+
+    if (ADC_InitStruct->ADC_SampleTime < min_time)
+    {
+        ADC_InitStruct->ADC_SampleTime = min_time;
+    }
+    else if (ADC_InitStruct->ADC_SampleTime > max_time)
+    {
+        ADC_InitStruct->ADC_SampleTime = max_time;
+    }
+}
+
+void ADC_BypassDisable(void)
+{
+    if (adc_bypass_status)
+    {
+        REG0X_AUX_TypeDef adc_reg0x_aux = {.d32 = ADC->REG0X_AUX};
+        adc_reg0x_aux.b.bypassen &= ~adc_bypass_status;
+        ADC->REG0X_AUX = adc_reg0x_aux.d32;
+    }
+}
+
+void ADC_BypassEnable(void)
+{
+    if (adc_bypass_status)
+    {
+        uint8_t adc_bitnum = 0;
+        uint8_t adc_sch_table = 0;
+        uint8_t adc_mode = 0;
+        uint8_t adc_channel = 0;
+        uint16_t adc_bitmap = ADC->ADC_SCHED_CTRL & 0xFFFF;
+        REG0X_AUX_TypeDef adc_reg0x_aux = {.d32 = ADC->REG0X_AUX};
+
+        while (adc_bitmap)
+        {
+            adc_bitnum = __builtin_ffs(adc_bitmap) - 1;
+            adc_bitmap &= ~BIT(adc_bitnum);
+            adc_sch_table = (adc_bitnum & 0x1) ?
+                            ((*((volatile uint32_t *)(&ADC->ADC_SCHTAB0) + (adc_bitnum >> 1))) >> 16) :
+                            (*((volatile uint32_t *)(&ADC->ADC_SCHTAB0) + (adc_bitnum >> 1))) ;
+            adc_mode = (adc_sch_table >> 3) & 0x3;
+            adc_channel = adc_sch_table & 0x7;
+
+            if ((adc_mode >= ADC_MODE_SINGLE_ENDED_VALUE) &&
+                (adc_mode <= ADC_MODE_DIFFERENTIAL_VALUE) &&
+                (BIT(adc_channel) & adc_bypass_status))
+            {
+                adc_reg0x_aux.b.bypassen |= BIT(adc_channel);
+                if (adc_mode == ADC_MODE_DIFFERENTIAL_VALUE)
+                {
+                    adc_channel = (adc_channel & 0x1) ? (adc_channel - 1) : (adc_channel + 1);
+                    if (BIT(adc_channel) & adc_bypass_status)
+                    {
+                        adc_reg0x_aux.b.bypassen |= BIT(adc_channel);
+                    }
+                }
+            }
+        }
+
+        ADC->REG0X_AUX = adc_reg0x_aux.d32;
+    }
+}
+
+void ADC_ClockAutoModeCmd(ADC_TypeDef *ADCx, FunctionalState Newstate)
+{
+    /* Check the parameters */
+    assert_param(IS_ADC_ALL_PERIPH(ADCx));
+
+    if (Newstate == ENABLE)
+    {
+        ADCx->ADC_QACTIVE_CTRL = ADC_CLOCK_AUTO_MODE_CONFIG_AUTOMATIC;
+    }
+    else
+    {
+        ADCx->ADC_QACTIVE_CTRL = ADC_CLOCK_AUTO_MODE_CONFIG_ALWAYSRUN;
+    }
+
+    return;
+}
+
+
+
diff --git a/bee/drivers/adc/src/device/rtl87x2j/rtl_adc_def.h b/bee/drivers/adc/src/device/rtl87x2j/rtl_adc_def.h
new file mode 100644
index 00000000..ea73ebfb
--- /dev/null
+++ b/bee/drivers/adc/src/device/rtl87x2j/rtl_adc_def.h
@@ -0,0 +1,542 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef RTL_ADC_DEF_H
+#define RTL_ADC_DEF_H
+
+#include "utils/rtl_utils.h"
+#include "address_map.h"
+#include "aon_reg.h"
+
+#ifdef  __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/*============================================================================*
+ *                          ADC Defines
+ *============================================================================*/
+/** \defgroup ADC         ADC
+  * \brief
+  * \{
+  */
+
+/** \defgroup ADC_Exported_Constants ADC Exported Constants
+  * \brief
+  * \{
+  */
+
+/**
+ * \defgroup ADC_Defines ADC Defines
+ * \{
+ * \ingroup  ADC_Exported_Constants
+ */
+#define CHIP_ADC_CHANNEL_NUM                           (8)
+#define CHIP_ADC_SCHEDULE_NUM                          (16)
+#define CHIP_ADC_MODE_OFFSET                           (3)
+#define ADC_SUPPORT_DMA_EN                             (1)
+#define ADC_SUPPORT_INT_FIFO_FULL                      (1)
+#define ADC_SUPPORT_VADPIN_MODE                        (0)
+#define ADC_SUPPORT_DATAMINUS                          (0)
+#define ADC_SUPPORT_POWER_OFF                          (1)
+#define ADC_SUPPORT_POWER_ON_DELAY                     (1)
+#define ADC_SUPPORT_RAP_FUNCTION                       (1)
+#define ADC_SUPPORT_AUTO_CLOCK                         (1)
+#define ADC_SUPPORT_18BIT_RAW_DATA                     (1)
+#define ADC_SUPPORT_DATA_CLIP                          (1)
+#define ADC_SUPPORT_HW_MAPPING                         (1)
+#define ADC_SUPPORT_BYPASS_AUTO_REVERT                 (0)
+#define ADC_SUPPORT_SAMPLE_RATE_GUARDTIME              (1)
+#define ADC_SUPPORT_TIMER_TRIGGER                      (0)
+#define ADC_SUPPORT_AUTO_BOOT_PROTECT                  (1)
+#define ADC_SUPPORT_GET_VOTAGE_API                     (1)
+//#define ADC_POWER_MODE_CTRL_EN                      (0)  //if you need to configure the power mode, you can predefine this macro in the project settings.
+/** End of ADC_Defines
+  * \}
+  */
+
+/** End of ADC_Exported_Constants
+  * \}
+  */
+
+/** End of ADC
+  * \}
+  */
+/*============================================================================*
+ *                          ADC Registers Memory Map
+ *============================================================================*/
+typedef struct
+{
+    __IO uint32_t ADC_FIFO;                         /*!< 0x00 */
+    __IO uint32_t ADC_CTRL;                         /*!< 0x04 */
+    __IO uint32_t ADC_SCHED_CTRL;                   /*!< 0x08 */
+    __IO uint32_t ADC_INT;                          /*!< 0x0C */
+    __IO uint16_t ADC_SCHTAB0;                      /*!< 0x10 */
+    __IO uint16_t ADC_SCHTAB1;
+    __IO uint16_t ADC_SCHTAB2;                      /*!< 0x14 */
+    __IO uint16_t ADC_SCHTAB3;
+    __IO uint16_t ADC_SCHTAB4;                      /*!< 0x18 */
+    __IO uint16_t ADC_SCHTAB5;
+    __IO uint16_t ADC_SCHTAB6;                      /*!< 0x1C */
+    __IO uint16_t ADC_SCHTAB7;
+    __IO uint16_t ADC_SCHTAB8;                      /*!< 0x20 */
+    __IO uint16_t ADC_SCHTAB9;
+    __IO uint16_t ADC_SCHTAB10;                     /*!< 0x24 */
+    __IO uint16_t ADC_SCHTAB11;
+    __IO uint16_t ADC_SCHTAB12;                     /*!< 0x28 */
+    __IO uint16_t ADC_SCHTAB13;
+    __IO uint16_t ADC_SCHTAB14;                     /*!< 0x2C */
+    __IO uint16_t ADC_SCHTAB15;
+    __I  uint32_t ADC_DATA0;                        /*!< 0x30 */
+    __I  uint32_t ADC_DATA1;                        /*!< 0x34 */
+    __I  uint32_t ADC_DATA2;                        /*!< 0x38 */
+    __I  uint32_t ADC_DATA3;                        /*!< 0x3C */
+    __I  uint32_t ADC_DATA4;                        /*!< 0x40 */
+    __I  uint32_t ADC_DATA5;                        /*!< 0x44 */
+    __I  uint32_t ADC_DATA6;                        /*!< 0x48 */
+    __I  uint32_t ADC_DATA7;                        /*!< 0x4C */
+    __I  uint32_t ADC_DATA8;                        /*!< 0x50 */
+    __I  uint32_t ADC_DATA9;                        /*!< 0x54 */
+    __I  uint32_t ADC_DATA10;                       /*!< 0x58 */
+    __I  uint32_t ADC_DATA11;                       /*!< 0x5C */
+    __I  uint32_t ADC_DATA12;                       /*!< 0x60 */
+    __I  uint32_t ADC_DATA13;                       /*!< 0x64 */
+    __I  uint32_t ADC_DATA14;                       /*!< 0x68 */
+    __I  uint32_t ADC_DATA15;                       /*!< 0x6C */
+    __IO uint32_t ADC_POW_DATA_DLY_CTRL;            /*!< 0x70 */
+    __IO uint32_t ADC_DATA_CLK_CTRL;                /*!< 0x74 */
+    __IO uint32_t ADC_TIME_PERIOD;                  /*!< 0x78 */
+    __IO uint32_t ADC_RTL_VERSION;                  /*!< 0x7C */
+    __IO uint32_t ADC_TASK_CTRL;                    /*!< 0x80 */
+    __IO uint32_t ADC_QACTIVE_CTRL;                 /*!< 0x84 */
+    __IO uint32_t REG0X_LDO;                        /*!< 0x88 */
+    __IO uint32_t REG0X_AUX;                        /*!< 0x8C */
+    __IO uint32_t ADC_SING_DIV_CAL_PAR;             /*!< 0x90 */
+    __IO uint32_t ADC_SING_BYP_CAL_PAR;             /*!< 0x94 */
+    __IO uint32_t ADC_DIFF_DIV_CAL_PAR;             /*!< 0x98 */
+    __IO uint32_t ADC_DIFF_BYP_CAL_PAR;             /*!< 0x9C */
+    __IO uint32_t ADC_INT_VBAT_CAL_PAR;             /*!< 0xA0 */
+    __IO uint32_t ADC_INT_VDDIO_CAL_PAR;            /*!< 0xA4 */
+    __IO uint32_t ADC_INT_VDDCORE_CAL_PAR;          /*!< 0xA8 */
+    __IO uint32_t ADC_INT_VCORE1_CAL_PAR;           /*!< 0xAC */
+} ADC_TypeDef;
+
+/*============================================================================*
+ *                          ADC Declaration
+ *============================================================================*/
+#define ADC                     ((ADC_TypeDef *) AUX_ADC_BASE)
+
+#define IS_ADC_PERIPH(PERIPH)   ((PERIPH) == ADC)
+
+/** \defgroup ADC_Convert_Time LPC Convert Time
+  * \{
+  * \ingroup  ADC_Exported_Constants
+  */
+
+#define ADC_CONVERT_TIME \
+    ADC_CONVERT_TIME_600NS =          0x0, \
+                                      ADC_CONVERT_TIME_800NS =          0x1, \
+                                                                        ADC_CONVERT_TIME_1000NS =         0x2, \
+                                                                                ADC_CONVERT_TIME_1200NS =         0x3
+
+/** End of ADC_Convert_Time
+  * \}
+  */
+
+/*============================================================================*
+ *                          ADC Private Types
+ *============================================================================*/
+
+/*============================================================================*
+ *                          ADC Registers and Field Descriptions
+ *============================================================================*/
+/* 0x00
+   31:0    R      adc_fifo_data_out               32'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t adc_fifo_data_out: 32;
+    } b;
+} ADC_FIFO_TypeDef;
+
+
+/* 0x04
+   0       R/W    en_adc_continuous_mode          1'h0
+   1       R/WAC  en_adc_one_shot_mode            1'h0
+   2       R/W    reserved_mask                   1'h0
+   7:3     R      reserved_mask                   5'h0
+   12:8    R      reserved_mask                   5'h0
+   13      R/W    adc_fifo_overwrite              1'h0
+   19:14   R/W    adc_burst_size                  6'h0
+   25:20   R/W    adc_fifo_thd                    6'h0
+   26      R/WAC  adc_fifo_clr                    1'h0
+   27      R/W    adc_one_shot_fifo               1'h0
+   28      R/W    adc_dma_mode                    1'h0
+   29      R      reserved04_29                   1'h0
+   31:30   R/W    reserved_mask                   2'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t en_adc_continuous_mode: 1;
+        uint32_t en_adc_one_shot_mode: 1;
+        uint32_t reserved_4: 1;
+        const uint32_t reserved_3: 5;
+        const uint32_t reserved_2: 5;
+        uint32_t adc_fifo_overwrite: 1;
+        uint32_t adc_burst_size: 6;
+        uint32_t adc_fifo_thd: 6;
+        uint32_t adc_fifo_clr: 1;
+        uint32_t adc_one_shot_fifo: 1;
+        uint32_t adc_dma_mode: 1;
+        const uint32_t reserved_1: 1;
+        uint32_t reserved_0: 2;
+    } b;
+} ADC_CTRL_TypeDef;
+
+
+/* 0x08
+   15:0    R/W    adc_schedule_idx_sel            16'h0
+   21:16   R      adc_fifo_data_level             6'h0
+   27:22   R      reserved08_27_22                6'h0
+   31:28   R      adc_schedule_index              4'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t adc_schedule_idx_sel: 16;
+        const uint32_t adc_fifo_data_level: 6;
+        const uint32_t reserved_0: 6;
+        const uint32_t adc_schedule_index: 4;
+    } b;
+} ADC_SCHED_CTRL_TypeDef;
+
+
+/* 0x0C
+   0       R/W    en_adc_fifo_rd_req_interrupt    1'h0
+   1       R/W    en_adc_fifo_rd_error_interrupt  1'h0
+   2       R/W    en_adc_fifo_thd_interrupt       1'h0
+   3       R/W    en_adc_fifo_full_interrupt      1'h0
+   4       R/W    en_adc_one_shot_done_interrupt  1'h0
+   5       R/W    en_adc_fifo_overflow_interrupt  1'h0
+   7:6     R      reserved0c_7_6                  2'h0
+   8       R/W1C  clr_adc_fifo_rd_req_interrupt   1'h0
+   9       R/W1C  clr_adc_fifo_rd_error_interrupt 1'h0
+   10      R/W1C  clr_adc_fifo_thd_interrupt      1'h0
+   11      R/W1C  clr_adc_fifo_full_interrupt     1'h0
+   12      R/W1C  clr_adc_one_shot_done_interrupt 1'h0
+   13      R/W1C  clr_adc_fifo_overflow_interrupt 1'h0
+   15:14   R      reserved0c_15_14                2'h0
+   16      R      st_adc_fifo_rd_req_interrupt    1'h0
+   17      R      st_adc_fifo_rd_error_interrupt  1'h0
+   18      R      st_adc_fifo_thd_interrupt       1'h0
+   19      R      st_adc_fifo_full_interrupt      1'h0
+   20      R      st_adc_one_shot_done_interrupt  1'h0
+   21      R      st_adc_fifo_overflow_interrupt  1'h0
+   31:22   R      reserved0c_31_20                10'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t en_adc_fifo_rd_req_interrupt: 1;
+        uint32_t en_adc_fifo_rd_error_interrupt: 1;
+        uint32_t en_adc_fifo_thd_interrupt: 1;
+        uint32_t en_adc_fifo_full_interrupt: 1;
+        uint32_t en_adc_one_shot_done_interrupt: 1;
+        uint32_t en_adc_fifo_overflow_interrupt: 1;
+        const uint32_t reserved_2: 2;
+        uint32_t clr_adc_fifo_rd_req_interrupt: 1;
+        uint32_t clr_adc_fifo_rd_error_interrupt: 1;
+        uint32_t clr_adc_fifo_thd_interrupt: 1;
+        uint32_t clr_adc_fifo_full_interrupt: 1;
+        uint32_t clr_adc_one_shot_done_interrupt: 1;
+        uint32_t clr_adc_fifo_overflow_interrupt: 1;
+        const uint32_t reserved_1: 2;
+        const uint32_t st_adc_fifo_rd_req_interrupt: 1;
+        const uint32_t st_adc_fifo_rd_error_interrupt: 1;
+        const uint32_t st_adc_fifo_thd_interrupt: 1;
+        const uint32_t st_adc_fifo_full_interrupt: 1;
+        const uint32_t st_adc_one_shot_done_interrupt: 1;
+        const uint32_t st_adc_fifo_overflow_interrupt: 1;
+        const uint32_t reserved_0: 10;
+    } b;
+} ADC_INT_TypeDef;
+
+
+/* 0x10-0x2C
+   2:0     R/W    ch_num_idx                      3'h0
+   4:3     R/W    adc_mode_idx                    2'h0
+   15:5    R      reserved10_15_5                 11'h0
+*/
+typedef union
+{
+    uint32_t d16;
+    struct
+    {
+        uint32_t ch_num_idx: 3;
+        uint32_t adc_mode_idx: 2;
+        const uint32_t reserved_1: 11;
+    } b;
+} ADC_SCHED_TAB_IDX_TypeDef;
+
+
+/* 0x30 - 0x6C
+   31:0    R      adc_idx_output_data            32'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t adc_idx_output_data: 32;
+    } b;
+} ADC_DATA_TypeDef;
+
+
+/* 0x70
+   1:0     R/W    reserved_mask                   2'h0
+   3:2     R/W    reserved_mask                   2'h0
+   5:4     R/W    reserved_mask                   2'h0
+   8:6     R/W    reserved_mask                   3'h2
+   9       R      reserved70_9                    1'h0
+   10      R/W    reserved_mask                   1'h0
+   14:11   R      reserved70_14_11                4'h0
+   15      R/W    adc_poweron_only_en             1'h0
+   16      R/W    adc_data_clipping_en            1'h0
+   18:17   R      reserved70_18_17                2'h0
+   19      R/W    reserved_mask                   1'h0
+   20      R      reserved70_23_20                1'h0
+   21      R/W    adc_fifo_stop_wr                1'h0
+   23:22   R      reserved70_23_22                2'h0
+   24      R/W    adc_data_avg_en                 1'h0
+   27:25   R/W    adc_data_avg_sel                3'h0
+   30:28   R      reserved70_30_28                3'h0
+   31      R/W    reserved_mask                   1'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t reserved_12: 2;
+        uint32_t reserved_11: 2;
+        uint32_t reserved_10: 2;
+        uint32_t reserved_9: 3;
+        const uint32_t reserved_8: 1;
+        uint32_t reserved_7: 1;
+        const uint32_t reserved_6: 4;
+        uint32_t adc_poweron_only_en: 1;
+        uint32_t adc_data_clipping_en: 1;
+        const uint32_t reserved_5: 2;
+        uint32_t adc_manual_poweron: 1;
+        const uint32_t reserved_3: 1;
+        uint32_t adc_fifo_stop_wr: 1;
+        const uint32_t reserved_2: 2;
+        uint32_t adc_data_avg_en: 1;
+        uint32_t adc_data_avg_sel: 3;
+        const uint32_t reserved_1: 3;
+        uint32_t reserved_0: 1;
+    } b;
+} ADC_POW_DATA_DLY_CTRL_TypeDef;
+
+
+/* 0x74
+   6:0     R      reserved74_6_0                  7'h0
+   7       R/W    reserved_mask                   1'h0
+   8       R/W    reserved_mask                   1'h0
+   10:9    R      reserved74_10_9                 2'h0
+   12:11   R/W    reserved_mask                   2'h0
+   28:13   R      reserved74_28_13                16'h0
+   29      R/W    reserved_mask                   1'h0
+   30      R/W    adc_data_align_msb              1'h0
+   31      R/W    reserved_mask                   1'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t reserved_7: 7;
+        uint32_t reserved_6: 1;
+        uint32_t reserved_5: 1;
+        const uint32_t reserved_4: 2;
+        uint32_t reserved_3: 2;
+        const uint32_t reserved_2: 16;
+        uint32_t reserved_1: 1;
+        uint32_t adc_data_align_msb: 1;
+        uint32_t reserved_0: 1;
+    } b;
+} ADC_DATA_CLK_CTRL_TypeDef;
+
+
+/* 0x78
+   13:0    R/W    adc_sample_time_period          14'h270f
+   29:14   R      reserved78_29_14                16'h0
+   31:30   R/W    adc_convert_time_period_sel     2'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t adc_sample_time_period: 14;
+        const uint32_t reserved_0: 16;
+        uint32_t adc_convert_time_period_sel: 2;
+    } b;
+} ADC_TIME_PERIOD_TypeDef;
+
+
+
+/* 0x80
+   0       R/W    adc_rap_mode                    1'h0
+   1       R/WAC  adc_fw_task_one_shot_sample     1'h0
+   31:2    R      reserved80_31_2                 30'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t adc_rap_mode: 1;
+        uint32_t adc_fw_task_one_shot_sample: 1;
+        const uint32_t reserved_0: 30;
+    } b;
+} ADC_TASK_CTRL_TypeDef;
+
+
+
+/* 0x8C
+   0       R/W    reserved_mask                   1'h0
+   1       R/W    reserved_mask                   1'h0
+   2       R/W    reserved_mask                   1'h0
+   3       R/W    reserved_mask                   1'h0
+   5:4     R/W    reserved_mask                   2'h1
+   6       R/W    reserved_mask                   1'h0
+   8:7     R/W    reserved_mask                   2'h0
+   9       R/W    reserved_mask                   1'h0
+   10      R/W    reserved_mask                   1'h0
+   11      R/W    reserved_mask                   1'h1
+   13:12   R/W    reserved_mask                   2'h1
+   21:14   R/W    bypassen                        8'h0
+   22      R/W    reserved_mask                   1'h1
+   26:23   R/W    reserved_mask                   4'h0
+   31:27   R      reserved8c_31_27                5'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t reserved_13: 1;
+        uint32_t reserved_12: 1;
+        uint32_t reserved_11: 1;
+        uint32_t reserved_10: 1;
+        uint32_t reserved_9: 2;
+        uint32_t reserved_8: 1;
+        uint32_t reserved_7: 2;
+        uint32_t reserved_6: 1;
+        uint32_t reserved_5: 1;
+        uint32_t reserved_4: 1;
+        uint32_t reserved_3: 2;
+        uint32_t bypassen: 8;
+        uint32_t reserved_2: 1;
+        uint32_t reserved_1: 4;
+        const uint32_t reserved_0: 5;
+    } b;
+} REG0X_AUX_TypeDef;
+
+
+
+/*============================================================================*
+ *                          ADC MODE Wrappers
+ *============================================================================*/
+/** \defgroup ADC        ADC
+  * \brief
+  * \{
+  */
+
+/** \defgroup ADC_Exported_Constants ADC Exported Constants
+  * \brief
+  * \{
+  */
+
+/**
+ * \defgroup ADC_Constant_Private ADC Constant Private
+ * \{
+ * \ingroup  ADC_Exported_Constants
+ */
+#define ADC_MODE_SINGLE_ENDED_VALUE     0x1
+#define ADC_MODE_DIFFERENTIAL_VALUE     0x2
+#define ADC_MODE_INTERNAL_VALUE         0x3
+#define ADC_MODE_RESERVED_VALUE         0x0
+
+#define ADC_MODE_EXTERNAL_CH_NUM(Index)   (Index)
+#define ADC_MODE_INTERNAL_VBAT_CH_NUM   0x0
+#define ADC_MODE_INTERNAL_VADPIN_CH_NUM   0x1
+
+#define ADCDataWidth                    uint32_t
+
+#define  ADC_DATA_LATCH_DELAY           0x2
+
+
+/**
+ * \defgroup    ADC_Sample_Mode ADC Sample Mode
+ * \{
+ * \ingroup     ADC_Exported_Constants
+ */
+typedef enum
+{
+    ADC_SAMPLE_DIVIDE_SINGLE_MODE = 1,
+    ADC_SAMPLE_BYPASS_SINGLE_MODE = 2,
+    ADC_SAMPLE_DIVIDE_DIFFERENTIAL_MODE = 3,
+    ADC_SAMPLE_BYPASS_DIFFERENTIAL_MODE = 4,
+    ADC_SAMPLE_INT_VBAT_MODE = 5,
+} ADCSampleMode_TypeDef;
+
+/** End of ADC_Sample_Mode
+  * \}
+  */
+
+/**
+ * \defgroup    ADC_Status ADC Status
+ * \{
+ * \ingroup     ADC_Exported_Constants
+ */
+typedef enum
+{
+    ADC_SUCCESS = 0,
+    ADC_ERROR_PARAMETER = -1,
+} ADCStatus_TypeDef;
+
+/** End of ADC_Status
+  * \}
+  */
+
+/** End of ADC_Constant_Private
+  * \}
+  */
+
+/** End of ADC_Exported_Constants
+  * \}
+  */
+
+/** End of ADC
+  * \}
+  */
+
+#ifdef  __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* RTL_ADC_DEF_H */
diff --git a/bee/drivers/adc/src/device/rtl_common/rtl_adc.c b/bee/drivers/adc/src/device/rtl_common/rtl_adc.c
new file mode 100644
index 00000000..c605eb70
--- /dev/null
+++ b/bee/drivers/adc/src/device/rtl_common/rtl_adc.c
@@ -0,0 +1,658 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *                           Header Files
+ *============================================================================*/
+#include "rtl_adc.h"
+#include "rtl_rcc.h"
+
+#if (ADC_SUPPORT_POWER_ON_DELAY == 1)
+#include "utils.h"
+#endif
+
+/*============================================================================*
+ *                           Private Functions
+ *============================================================================*/
+extern void ADC_SISet(void);
+extern void ADC_DelayConfig(ADC_InitTypeDef *ADC_InitStruct);
+extern void ADC_SampleTimeConfig(ADC_InitTypeDef *ADC_InitStruct);
+extern void ADC_PowerOff(void);
+extern void ADC_ManualModePowerOn(void);
+extern void ADC_ManualModePowerOff(void);
+extern void ADC_BypassDisable(void);
+extern void ADC_BypassEnable(void);
+extern void ADC_AnalogControlCmd(void);
+extern void ADC_HWMappingEnable(void);
+
+uint16_t adc_bypass_status = 0;
+
+/*============================================================================*
+ *                           Public Functions
+ *============================================================================*/
+/**
+  * \brief  Deinitializes the ADC peripheral registers to their default reset values.
+  * \param  ADCx: selected ADC peripheral.
+  * \return None.
+  */
+void ADC_DeInit(ADC_TypeDef *ADCx)
+{
+    /* Check the parameters */
+    assert_param(IS_ADC_PERIPH(ADCx));
+
+#if (ADC_SUPPORT_POWER_OFF == 1)
+    ADC_PowerOff();
+#endif
+
+    RCC_ClockCmd(ADC_CLOCK, DISABLE);
+}
+
+/**
+  * \brief Initializes the ADC peripheral according to the specified
+  *   parameters in the ADC_InitStruct
+  * \param  ADCx: selected ADC peripheral.
+  * \param  ADC_InitStruct: pointer to a ADCInitTypeDef structure that
+  *   contains the configuration information for the specified ADC peripheral
+  * \return None
+  */
+void ADC_Init(ADC_TypeDef *ADCx, ADC_InitTypeDef *ADC_InitStruct)
+{
+    /* Check the parameters */
+    assert_param(IS_ADC_PERIPH(ADCx));
+    assert_param(IS_ADC_LATCH_MODE(ADC_InitStruct->ADC_DataLatchEdge));
+    assert_param(IS_ADC_POWER_MODE(ADC_InitStruct->ADC_PowerOnMode));
+    assert_param(IS_ADC_RG2X_0_DELAY_TIME(ADC_InitStruct->ADC_RG2X0Dly));
+    assert_param(IS_ADC_RG0X_1_DELAY_TIME(ADC_InitStruct->ADC_RG0X1Dly));
+    assert_param(IS_ADC_RG0X_0_DELAY_TIME(ADC_InitStruct->ADC_RG0X0Dly));
+    assert_param(IS_ADC_BURST_SIZE_CONFIG(ADC_InitStruct->ADC_WaterLevel));
+    assert_param(IS_ADC_FIFO_THRESHOLD(ADC_InitStruct->ADC_FIFOThdLevel));
+
+    /* Set SI */
+    ADC_SISet();
+
+    /* Disable all interrupts */
+    ADCx->ADC_INT &= (~0x1f);
+
+    /* ---------- Configure Power Mode ---------- */
+    ADC_POW_DATA_DLY_CTRL_TypeDef adc_pow_data_dly_ctrl = {.d32 = ADCx->ADC_POW_DATA_DLY_CTRL};
+    adc_pow_data_dly_ctrl.b.adc_poweron_only_en  = ADC_InitStruct->ADC_PowerAlwaysOnEn;
+    adc_pow_data_dly_ctrl.b.adc_fifo_stop_wr     = ADC_InitStruct->ADC_FIFOStopWriteEn;
+    adc_pow_data_dly_ctrl.b.adc_data_avg_en      = ADC_InitStruct->ADC_DataAverageEn;
+    adc_pow_data_dly_ctrl.b.adc_data_avg_sel     = (ADC_InitStruct->ADC_DataAverageEn == ENABLE) ?
+                                                   ADC_InitStruct->ADC_DataAverage : 0;
+#ifdef ADC_POWER_MODE_CTRL_EN
+    adc_pow_data_dly_ctrl.b.adc_manual_poweron   = ADC_InitStruct->ADC_PowerOnMode;
+#endif
+#if (ADC_SUPPORT_DATA_CLIP == 1)
+    adc_pow_data_dly_ctrl.b.adc_data_clipping_en = ADC_InitStruct->ADC_DataClippingEn;
+#endif
+    ADCx->ADC_POW_DATA_DLY_CTRL = adc_pow_data_dly_ctrl.d32;
+
+    /* Configure ADC auto power on delay parameters */
+    ADC_DelayConfig(ADC_InitStruct);
+
+#if (ADC_SUPPORT_POWER_ON_DELAY == 1)
+    if (ADC_InitStruct->ADC_PowerOnDlyEn == ENABLE && ADC_InitStruct->ADC_PowerAlwaysOnEn == ENABLE)
+    {
+        /* After ADC power on, there is a re-settle time about 8ms,
+         * during which the acquired voltage may be 0-10mV higher than actual.
+         * Enable this delay to avoid such error, only effective when
+         * ADC_PowerAlwaysOnEn is set to ENABLE.
+         */
+        platform_delay_ms(8);
+    }
+#endif
+
+    /* ---------- Configure Schedule Table ---------- */
+    uint32_t sch_index = 0;
+    for (uint8_t index = 0; index < 8; index++)
+    {
+        sch_index = (ADC_InitStruct->ADC_SchIndex[index * 2]) |
+                    (ADC_InitStruct->ADC_SchIndex[index * 2 + 1] << 16);
+        *((volatile uint32_t *)(&ADCx->ADC_SCHTAB0) + index) = sch_index;
+    }
+#if (CHIP_ADC_SCHEDULE_NUM > 16)
+    for (uint8_t index = 0; index < 4; index++)
+    {
+        sch_ind = (ADC_InitStruct->ADC_SchIndex[16 + index] << 16);
+        *((volatile uint32_t *)(&ADCx->ADC_SCHTABD16) + index) = sch_ind;
+    }
+#endif
+
+    /* Configure schedule control register */
+    ADC_SCHED_CTRL_TypeDef adc_sched_ctrl = {.d32 = ADCx->ADC_SCHED_CTRL};
+    adc_sched_ctrl.b.adc_schedule_idx_sel = ADC_InitStruct->ADC_Bitmap;
+    ADCx->ADC_SCHED_CTRL = adc_sched_ctrl.d32;
+
+    /* ---------- Configure ADC Mode ---------- */
+    ADC_CTRL_TypeDef adc_ctrl = {.d32 = ADCx->ADC_CTRL};
+    adc_ctrl.b.adc_one_shot_fifo   = ADC_InitStruct->ADC_DataWriteToFIFO;
+    adc_ctrl.b.adc_fifo_thd        = ADC_InitStruct->ADC_FIFOThdLevel & 0x1F;
+    adc_ctrl.b.adc_burst_size      = ADC_InitStruct->ADC_WaterLevel;
+    adc_ctrl.b.adc_fifo_overwrite  = ADC_InitStruct->ADC_FIFOOverWriteEn;
+#if (ADC_SUPPORT_DMA_EN == 1)
+    adc_ctrl.b.adc_dma_mode        = ADC_InitStruct->ADC_DMAEn;
+#endif
+    ADCx->ADC_CTRL = adc_ctrl.d32;
+
+    /* Configure data clock control register */
+    ADC_DATA_CLK_CTRL_TypeDef adc_data_clk_ctrl = { .d32 = ADCx->ADC_DATA_CLK_CTRL };
+#if ADC_SUPPORT_TIMER_TRIGGER
+    adc_data_clk_ctrl.b.adc_timer_trigger_en = ADC_InitStruct->ADC_TimerTriggerEn;
+#endif
+    adc_data_clk_ctrl.b.adc_data_align_msb = ADC_InitStruct->ADC_DataAlign;
+#if (ADC_SUPPORT_DATAMINUS == 1)
+    adc_data_clk_ctrl.b.adc_data_offset_en   = ADC_InitStruct->ADC_DataMinusEn;
+    adc_data_clk_ctrl.b.adc_data_offset      = ADC_InitStruct->ADC_DataMinusOffset;
+#endif
+    ADCx->ADC_DATA_CLK_CTRL = adc_data_clk_ctrl.d32;
+
+#if (ADC_SUPPORT_HW_MAPPING ==1)
+    ADC_HWMappingEnable();
+#endif
+
+    /* ---------- Configure Sample Time ---------- */
+    ADC_TIME_PERIOD_TypeDef adc_time_period = {.d32 = ADCx->ADC_TIME_PERIOD};
+    ADC_SampleTimeConfig(ADC_InitStruct);
+    adc_time_period.b.adc_convert_time_period_sel = ADC_InitStruct->ADC_ConvertTime;
+    adc_time_period.b.adc_sample_time_period      = ADC_InitStruct->ADC_SampleTime & 0x3FFF;
+    ADCx->ADC_TIME_PERIOD = adc_time_period.d32;
+
+    /* Clear ADC FIFO */
+    adc_ctrl.b.adc_fifo_clr = 0x1;
+    ADCx->ADC_CTRL = adc_ctrl.d32;
+
+    /* Clear all interrupt flags */
+    ADCx->ADC_INT |= (0x1f << 8);
+
+    return;
+}
+
+/**
+  * \brief  Fills each ADC_InitStruct member with its default value.
+  * \param  ADC_InitStruct: pointer to an ADC_InitTypeDef structure which will be initialized.
+  * \return None
+  */
+void ADC_StructInit(ADC_InitTypeDef *ADC_InitStruct)
+{
+    ADC_InitStruct->ADC_SampleTime      = 0x3E7;
+#if (ADC_SUPPORT_SAMPLE_RATE_GUARDTIME == 1)
+    ADC_InitStruct->ADC_ConvertTime     = ADC_CONVERT_TIME_600NS;
+#else
+    ADC_InitStruct->ADC_ConvertTime     = ADC_CONVERT_TIME_500NS;
+#endif
+    ADC_InitStruct->ADC_DataWriteToFIFO = DISABLE;
+    ADC_InitStruct->ADC_FIFOThdLevel    = 0x06;
+    ADC_InitStruct->ADC_WaterLevel      = 0x1;
+    ADC_InitStruct->ADC_FIFOOverWriteEn = ENABLE;
+    for (uint8_t i = 0; i < CHIP_ADC_SCHEDULE_NUM; ++i)
+    {
+        ADC_InitStruct->ADC_SchIndex[i] = 0;
+    }
+    ADC_InitStruct->ADC_Bitmap          = 0x0;
+#if ADC_SUPPORT_TIMER_TRIGGER
+    ADC_InitStruct->ADC_TimerTriggerEn  = DISABLE;
+#endif
+    ADC_InitStruct->ADC_DataAlign       = ADC_DATA_ALIGN_LSB;
+#if (ADC_SUPPORT_DATAMINUS==1)
+    ADC_InitStruct->ADC_DataMinusEn     = DISABLE;
+    ADC_InitStruct->ADC_DataMinusOffset = 0;
+#endif
+#if (ADC_SUPPORT_DMA_EN == 1)
+    ADC_InitStruct->ADC_DMAEn           = DISABLE;
+#endif
+    ADC_InitStruct->ADC_FIFOStopWriteEn = DISABLE;
+    ADC_InitStruct->ADC_DataAverageEn   = DISABLE;
+    ADC_InitStruct->ADC_DataAverage     = ADC_DATA_AVERAGE_OF_2;
+
+    /*Reserved parameter, please do not change values*/
+    ADC_InitStruct->ADC_PowerAlwaysOnEn = DISABLE;
+#if (ADC_SUPPORT_POWER_ON_DELAY == 1)
+    ADC_InitStruct->ADC_PowerOnDlyEn    = DISABLE;
+#endif
+#ifdef ADC_POWER_MODE_CTRL_EN
+    ADC_InitStruct->ADC_PowerOnMode     = ADC_POWER_ON_AUTO;
+#endif
+
+#if (ADC_SUPPORT_DATA_CLIP ==1 )
+    ADC_InitStruct->ADC_DataClippingEn  = ENABLE;
+#endif
+    return;
+}
+
+/**
+  * \brief  Enables or disables the ADC peripheral.
+  * \param  ADCx: selected ADC peripheral.
+  * \param  AdcMode: adc mode select.
+  *         This parameter can be one of the following values:
+  *         \arg ADC_ONE_SHOT_MODE: one shot mode.
+  *         \arg ADC_CONTINUOUS_MODE: continuous mode.
+  * \param  NewState: new state of the ADC peripheral.
+  *         This parameter can be: ENABLE or DISABLE.
+  * \return None
+  */
+void ADC_Cmd(ADC_TypeDef *ADCx, ADCOperationMode_TypeDef AdcMode, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_ADC_PERIPH(ADCx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+    assert_param(IS_ADC_MODE(AdcMode));
+
+    ADC_CTRL_TypeDef adc_ctrl = {.d32 = ADCx->ADC_CTRL};
+    ADC_POW_DATA_DLY_CTRL_TypeDef adc_pow_data_dly_ctrl = {.d32 = ADCx->ADC_POW_DATA_DLY_CTRL};
+
+    if (NewState == ENABLE)
+    {
+        ADC_BypassEnable();
+#ifdef ADC_POWER_MODE_CTRL_EN
+        if (adc_pow_data_dly_ctrl.b.adc_manual_poweron == ADC_POWER_ON_MANUAL)
+        {
+            ADC_ManualModePowerOn();
+        }
+#endif
+        if (AdcMode == ADC_ONE_SHOT_MODE)
+        {
+            adc_ctrl.b.en_adc_one_shot_mode = 1;
+            adc_ctrl.b.en_adc_continuous_mode = 0;
+        }
+        else
+        {
+            adc_ctrl.b.en_adc_one_shot_mode = 0;
+            adc_ctrl.b.en_adc_continuous_mode = 1;
+        }
+        ADCx->ADC_CTRL = adc_ctrl.d32;
+    }
+    else
+    {
+#ifdef ADC_POWER_MODE_CTRL_EN
+        if (adc_pow_data_dly_ctrl.b.adc_manual_poweron == ADC_POWER_ON_MANUAL)
+        {
+            ADC_ManualModePowerOff();
+        }
+#endif
+        adc_ctrl.b.en_adc_one_shot_mode = 0;
+        adc_ctrl.b.en_adc_continuous_mode = 0;
+        ADCx->ADC_CTRL = adc_ctrl.d32;
+#if (ADC_SUPPORT_BYPASS_AUTO_REVERT == 0)
+        ADC_BypassDisable();
+#endif
+    }
+
+    return;
+}
+
+/**
+  * \brief  Enables or disables the specified ADC interrupts.
+  * \param  ADCx: selected ADC peripheral.
+  * \param  ADC_INT: specifies the ADC interrupts sources to be enabled or disabled.
+  *         This parameter can be any combination of the following values:
+  *         \arg ADC_INT_FIFO_RD_REQ :FIFO read request
+  *         \arg ADC_INT_FIFO_RD_ERR :FIFO read error
+  *         \arg ADC_INT_FIFO_THD :ADC FIFO size > thd
+  *         \arg ADC_INT_FIFO_FULL :ADC FIFO overflow
+  *         \arg ADC_INT_ONE_SHOT_DONE :ADC one shot mode done
+  * \param  NewState: new state of the specified ADC interrupts.
+  *         This parameter can be: ENABLE or DISABLE.
+  * \return None
+  */
+void ADC_INTConfig(ADC_TypeDef *ADCx, uint32_t ADC_INT, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_ADC_PERIPH(ADCx));
+    assert_param(IS_ADC_INT(ADC_INT));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (NewState != DISABLE)
+    {
+        ADCx->ADC_INT |= ADC_INT;
+    }
+    else
+    {
+        ADCx->ADC_INT &= ~ADC_INT;
+    }
+}
+
+/**
+  * \brief  Checks whether the specified ADC interrupt status flag is set or not.
+  * \param  ADCx: selected ADC peripheral.
+  * \param  ADC_INT_FLAG: specifies the interrupt status flag to check.
+  *     This parameter can be one of the following values:
+  *     \arg ADC_INT_ONE_SHOT_DONE: ADC once convert end interrupt
+  *     \arg ADC_INT_FIFO_OVERFLOW: ADC FIFO overflow interrupt
+  *     \arg ADC_INT_FIFO_THD: fifo larger than threshold
+  *     \arg ADC_INT_FIFO_RD_ERR: ADC read FIFO error interrupt
+  *     \arg ADC_INT_FIFO_RD_REQ: ADC read FIFO request interrupt
+  * \return The new state of ADC_INT (SET or RESET).
+  */
+ITStatus ADC_GetINTStatus(ADC_TypeDef *ADCx, uint32_t ADC_INT)
+{
+    /* Check the parameters */
+    assert_param(IS_ADC_PERIPH(ADCx));
+    assert_param(IS_ADC_INT(ADC_INT));
+
+    return (ITStatus)((ADCx->ADC_INT & (ADC_INT << 16)) != 0);
+}
+
+/**
+  * \brief  Get all adc interrupt flag status.
+  * \param  ADCx: Specify ADC peripheral.
+  * \return All ADC interrupt status.
+  */
+uint8_t ADC_GetAllFlagStatus(ADC_TypeDef *ADCx)
+{
+    /* Check the parameters */
+    assert_param(IS_ADC_PERIPH(ADCx));
+
+    return ((uint8_t)(((ADCx->ADC_INT) & (0x1F << 16)) >> 16));
+}
+
+/**
+  * \brief  Clear the ADC interrupt pending bit.
+  * \param  ADCx: selected ADC peripheral.
+  * \param  ADC_INT: specifies the interrupt pending bit to clear.
+  *         This parameter can be any combination of the following values:
+  *         \arg ADC_INT_ONE_SHOT_DONE: ADC once convert end interrupt
+  *         \arg ADC_INT_FIFO_OVERFLOW: ADC FIFO overflow interrupt
+  *         \arg ADC_INT_FIFO_THD: fifo larger than threshold
+  *         \arg ADC_INT_FIFO_RD_ERR: ADC read FIFO error interrupt
+  *         \arg ADC_INT_FIFO_RD_REQ: ADC read FIFO request interrupt
+  * \return None
+  */
+void ADC_ClearINTPendingBit(ADC_TypeDef *ADCx, uint32_t ADC_INT)
+{
+    /* Check the parameters */
+    assert_param(IS_ADC_PERIPH(ADCx));
+    assert_param(IS_ADC_INT(ADC_INT));
+
+    ADCx->ADC_INT |= (ADC_INT << 8);
+
+    return;
+}
+
+/**
+  * \brief  Read ADC data according to specific channel.
+  * \param  ADCx: selected ADC peripheral.
+  * \param  Index: can be 0 to 15.
+  * \return The 12-bit converted ADC data.
+  */
+ADCDataWidth ADC_ReadRawData(ADC_TypeDef *ADCx, uint8_t Index)
+{
+    /* Check the parameters */
+    assert_param(IS_ADC_PERIPH(ADCx));
+    assert_param(Index < CHIP_ADC_SCHEDULE_NUM);
+
+#if(ADC_SUPPORT_18BIT_RAW_DATA == 1)
+    return (*((volatile uint32_t *)(&ADCx->ADC_DATA0) + Index));
+#else
+#if (CHIP_ADC_SCHEDULE_NUM > 16)
+    if (Index >= 16)
+    {
+        return (*((volatile uint32_t *)(&ADCx->ADC_SCHTABD16) + Index - 16));
+    }
+#endif
+
+    if (Index & BIT(0))
+    {
+        return ((*((volatile uint32_t *)(&ADCx->ADC_SCHD0) + (Index >> 1))) >> 16);
+    }
+    else
+    {
+        return (*((volatile uint32_t *)(&ADCx->ADC_SCHD0) + (Index >> 1)));
+    }
+#endif
+}
+
+/**
+  * \brief  Read ADC average data from ADC schedule table0.
+  * \param  ADCx: selected ADC peripheral.
+  * \param[out]  OutBuf: buffer to save data read from ADC FIFO.
+  * \return The 12-bit converted ADC data.
+  */
+ADCDataWidth ADC_ReadAvgRawData(ADC_TypeDef *ADCx)
+{
+    /* Check the parameters */
+    assert_param(IS_ADC_PERIPH(ADCx));
+
+#if(ADC_SUPPORT_18BIT_RAW_DATA == 1)
+    return (ADCx->ADC_DATA0);
+#else
+    return (uint16_t)(ADCx->ADC_SCHD0);
+#endif
+}
+
+/**
+  * \brief  Get one data from ADC FIFO.
+  * \param  ADCx: selected ADC peripheral.
+  * \return Adc FIFO data.
+  */
+ADCDataWidth ADC_ReadFIFO(ADC_TypeDef *ADCx)
+{
+    /* Check the parameters */
+    assert_param(IS_ADC_PERIPH(ADCx));
+
+#if(ADC_SUPPORT_18BIT_RAW_DATA == 1)
+    return ((ADCx->ADC_FIFO));
+#else
+    return (uint16_t)((ADCx->ADC_FIFO_READ) & 0xFFF);
+#endif
+}
+
+/**
+  * \brief  Read data from ADC FIFO.
+  * \param  ADCx: selected ADC peripheral.
+  * \param[out]  OutBuf: buffer to save data read from ADC FIFO.
+  * \param  Num: number of data to be read.
+  * \return None
+  */
+void ADC_ReadFIFOData(ADC_TypeDef *ADCx, ADCDataWidth *OutBuf, uint16_t Num)
+{
+    /* Check the parameters */
+    assert_param(IS_ADC_PERIPH(ADCx));
+
+    while (Num--)
+    {
+#if(ADC_SUPPORT_18BIT_RAW_DATA == 1)
+        *OutBuf++ = ADCx->ADC_FIFO;
+#else
+        *OutBuf++ = (uint16_t)ADCx->ADC_FIFO_READ;
+#endif
+    }
+
+    return;
+}
+
+/**
+  * \brief  Get ADC fifo data number.
+  * \param  ADCx: selected ADC peripheral.
+  * \return current data number in adc fifo.
+  */
+uint8_t ADC_GetFIFODataLen(ADC_TypeDef *ADCx)
+{
+    /* Check the parameters */
+    assert_param(IS_ADC_PERIPH(ADCx));
+
+    ADC_SCHED_CTRL_TypeDef adc_sched_ctrl = {.d32 = ADCx->ADC_SCHED_CTRL};
+    return ((uint8_t) adc_sched_ctrl.b.adc_fifo_data_level);
+}
+
+/**
+ * \brief  Config ADC schedule table.
+ * \param  ADCx: Specify ADC peripheral.
+ * \param  ADCMode: ADC operation mode.
+ * \return  None.
+
+ */
+void ADC_SchIndexConfig(ADC_TypeDef *ADCx, uint8_t ADCMode, uint16_t Index)
+{
+    /* Check the parameters */
+    assert_param(IS_ADC_PERIPH(ADCx));
+    assert_param(IS_ADC_SCHEDULE_INDEX_CONFIG(AdcMode));
+
+#if (CHIP_ADC_SCHEDULE_NUM > 16)
+    if (index >= 16)
+    {
+        *((volatile uint32_t *)(&ADCx->ADC_SCHTABD16) + Index - 16) |= (AdcMode << 16);
+    }
+#endif
+
+    if (Index & BIT0)
+    {
+        *((volatile uint32_t *)(&ADCx->ADC_SCHTAB0) + (Index >> 1)) |= (ADCMode << 16);
+    }
+    else
+    {
+        *((volatile uint32_t *)(&ADCx->ADC_SCHTAB0) + (Index >> 1)) |= ADCMode;
+    }
+
+    return;
+}
+
+/**
+  * \brief  Set adc schedule table.
+  * \param  ADCx: selected ADC peripheral.
+  * \param  BitMap: ADC bit map.
+  * \param  NewState: new state of the ADC peripheral.
+  *   This parameter can be: ENABLE or DISABLE.
+  * \return none.
+  */
+void ADC_BitMapConfig(ADC_TypeDef *ADCx, uint16_t BitMap)
+{
+    /* Check the parameters */
+    assert_param(IS_ADC_PERIPH(ADCx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    ADC_SCHED_CTRL_TypeDef adc_sched_ctrl = {.d32 = ADCx->ADC_SCHED_CTRL};
+    adc_sched_ctrl.b.adc_schedule_idx_sel = BitMap;
+    ADCx->ADC_SCHED_CTRL = adc_sched_ctrl.d32;
+
+    return;
+}
+
+/**
+  * \brief  Enbale or disable stop fifo from writing data.
+  * \param  ADCx: selected ADC peripheral.
+  * \param  NewState: new state of the ADC fifo write.
+  *     This parameter can be: ENABLE or DISABLE.
+  * \return None
+  */
+void ADC_WriteFIFOCmd(ADC_TypeDef *ADCx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_ADC_PERIPH(ADCx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    ADC_CTRL_TypeDef adc_ctrl = {.d32 = ADCx->ADC_CTRL};
+    adc_ctrl.b.adc_one_shot_fifo = NewState;
+    ADCx->ADC_CTRL = adc_ctrl.d32;
+
+    return;
+}
+
+/**
+  * \brief  Config ADC bypass resistor.Attention!!!Channels using bypass mode cannot over 0.9V!!!!
+  * \param  ChannelNum: external channel number, can be 0~15.
+  * \param  NewState: ENABLE or DISABLE.
+  * \return None
+  */
+void ADC_BypassCmd(uint8_t ChannelNum, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(ChannelNum <= CHIP_ADC_CHANNEL_NUM);
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (!IS_ADC_CHANNEL(ChannelNum))
+    {
+        return;
+    }
+
+    if (NewState != DISABLE)
+    {
+        adc_bypass_status |= BIT(ChannelNum);
+    }
+    else
+    {
+        adc_bypass_status &= ~BIT(ChannelNum);
+    }
+}
+
+/**
+  * \brief  Clear ADC FIFO.
+  * \param  ADCx: Specify ADC peripheral.
+  * \return None
+  */
+void ADC_ClearFIFO(ADC_TypeDef *ADCx)
+{
+    /* Check the parameters */
+    assert_param(IS_ADC_PERIPH(ADCx));
+
+    ADC_CTRL_TypeDef adc_ctrl = {.d32 = ADCx->ADC_CTRL};
+    adc_ctrl.b.adc_fifo_clr = 0x1;
+    ADCx->ADC_CTRL = adc_ctrl.d32;
+
+    return;
+}
+
+/**
+  * \brief  Enables or disables the ADC power always on.
+  * \param  ADCx: selected ADC peripheral.
+  * \param  NewState: new state of the specified ADC power always on.
+  *         This parameter can be: ENABLE or DISABLE.
+  * \return None
+  */
+void ADC_PowerAlwaysOnCmd(ADC_TypeDef *ADCx, FunctionalState NewState)
+{
+    ADC_POW_DATA_DLY_CTRL_TypeDef adc_pow_data_dly_ctrl = {.d32 = ADCx->ADC_POW_DATA_DLY_CTRL};
+    adc_pow_data_dly_ctrl.b.adc_poweron_only_en = NewState;
+    ADCx->ADC_POW_DATA_DLY_CTRL =  adc_pow_data_dly_ctrl.d32;
+
+#if(ADC_SUPPORT_AUTO_POWER_ON_PROTECT == 1)
+    ADC_AnalogControlCmd();
+#endif
+}
+
+#if (ADC_SUPPORT_RAP_FUNCTION == 1)
+/**
+  * \brief  Enables or disables RAP Mode.
+  * \param  ADCx: Pointer to the selected ADC peripheral. \ref ADC Declaration
+  * \param  NewState: New state of the RAP mode.
+  *         This parameter can be: ENABLE or DISABLE.
+  * \return None
+  */
+void ADC_RAPModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_ADC_ALL_PERIPH(ADCx));
+
+    ADC_TASK_CTRL_TypeDef adc_task_ctrl = {.d32 = ADCx->ADC_TASK_CTRL};
+    adc_task_ctrl.b.adc_rap_mode = NewState;
+    ADCx->ADC_TASK_CTRL = adc_task_ctrl.d32;
+
+    return;
+}
+
+/**
+  * \brief  Trigger an task which special of by firmware.
+  * \param  ADCx: Pointer to the selected ADC peripheral. \ref ADC Declaration
+  * \param  Action: ADC task to be trigger. \ref ADC_Action.
+  * \return None
+  */
+void ADC_ActionTrigger(ADC_TypeDef *ADCx, uint32_t Action)
+{
+    /* Check the parameters */
+    assert_param(IS_ADC_ALL_PERIPH(ADCx));
+
+    ADC_TASK_CTRL_TypeDef adc_task_ctrl = {.d32 = ADCx->ADC_TASK_CTRL};
+    if (Action == ADC_ACTION_ONE_SHOT_SAMPLE)
+    {
+        adc_task_ctrl.b.adc_fw_task_one_shot_sample = 0x1;
+    }
+    ADCx->ADC_TASK_CTRL = adc_task_ctrl.d32;
+
+    return;
+}
+#endif
+
+
diff --git a/bee/drivers/bluetooth/CMakeLists.txt b/bee/drivers/bluetooth/CMakeLists.txt
new file mode 100644
index 00000000..329920e8
--- /dev/null
+++ b/bee/drivers/bluetooth/CMakeLists.txt
@@ -0,0 +1,6 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_include_directories(inc)
+
+add_subdirectory(src)
diff --git a/bee/drivers/bluetooth/Kconfig b/bee/drivers/bluetooth/Kconfig
new file mode 100644
index 00000000..98a6f960
--- /dev/null
+++ b/bee/drivers/bluetooth/Kconfig
@@ -0,0 +1,10 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config REALTEK_BEE_BT
+	bool "Realtek Bee MCU bluetooth driver"
+	default y
+	depends on HAL_REALTEK_BEE_BT
+	help
+	  This option enables the bluetooth driver for Realtek Bee family of
+	  processors.
diff --git a/bee/drivers/bluetooth/inc/rtl_bt_hci.h b/bee/drivers/bluetooth/inc/rtl_bt_hci.h
new file mode 100644
index 00000000..8c7ec669
--- /dev/null
+++ b/bee/drivers/bluetooth/inc/rtl_bt_hci.h
@@ -0,0 +1,366 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _RTK_BT_HCI_H_
+#define _RTK_BT_HCI_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*============================================================================*
+ *                        Header Files
+ *============================================================================*/
+#include <stdint.h>
+#include <stdbool.h>
+
+/** @addtogroup RTK_BT_HCI REALTEK BT HCI Transport
+  * @brief REALTEK BT HCI Transport
+  * @details
+
+    REALTEK BT HCI Transport exposes interfaces to external BT host.
+
+    External BT Host shall initialize BT HCI pool and register callback using @ref rtl_bt_hci_open function.
+
+    External BT Host shall handle the callback message registered by @ref rtl_bt_hci_open. When REALTEK controller needs send HCI packet to BT Host,
+    REALTEK controller will call the callback to send message BT_HCI_EVT_DATA_IND.
+
+    External BT Host allocates buffers for HCI commands and ACL data from BT HCI pool using @ref rtl_bt_hci_h2c_buf_alloc. BT Host copies the HCI packet to the buffer using @ref rtl_bt_hci_h2c_buf_add.
+    Then External BT Host sends HCI packet to controller using @ref rtl_bt_hci_send.
+
+
+
+  * @{
+  */
+/*============================================================================*
+ *                         Macros
+ *============================================================================*/
+/** @defgroup RTK_BT_HCI_Exported_Macros REALTEK BT HCI Transport Exported Macros
+  * @{
+  */
+
+/** @defgroup RTK_BT_HCI_TYPE HCI packet types
+ * @{
+ */
+#define H4_CMD  0x01 /**< HCI Command packet. */
+#define H4_ACL  0x02 /**< HCI ACL Data packet. */
+#define H4_SCO  0x03 /**< HCI Synchronous Data packet. */
+#define H4_EVT  0x04 /**< HCI Event packet. */
+#define H4_ISO  0x05 /**< HCI ISO Data packet. */
+/**
+  * @}
+  */
+
+/** End of RTK_BT_HCI_Exported_Macros
+  * @}
+  */
+
+/*============================================================================*
+ *                         Types
+ *============================================================================*/
+/** @defgroup RTK_BT_HCI_Exported_Types REALTEK BT HCI Transport Exported Types
+  * @brief
+  * @{
+  */
+typedef enum
+{
+    BT_HCI_EVT_OPENED,     /**< BT HCI open completed. */
+    BT_HCI_EVT_DATA_IND,   /**< BT HCI packet from Controller to Host. */
+} T_RTL_BT_HCI_EVT;
+
+/** @brief  BT HCI buffer.*/
+typedef struct
+{
+    uint8_t                  *p_h2c_buf;
+    uint16_t                  h2c_buf_size;
+    uint16_t                  h2c_buf_size_max;
+} T_RTL_BT_HCI_BUF;
+
+/**
+  * @brief Callback for controller to host
+  * @param[in] evt       Event type @ref T_RTL_BT_HCI_EVT.
+  * @param[in] status    The status of the event.
+  * @param[in] p_c2h_buf Point to callback data.
+  * @param[in] len       The length of callback data.
+  * @retval true         If the packet can be sent to host.
+  * @retval false        If the packet needs to be dropped.
+  */
+typedef bool (*P_RTL_BT_HCI_CALLBACK)(T_RTL_BT_HCI_EVT evt, bool status, uint8_t *p_c2h_buf,
+                                      uint32_t len);
+
+/** End of RTK_BT_HCI_Exported_Types
+  * @}
+  */
+
+/*============================================================================*
+ *                         Functions
+ *============================================================================*/
+/**
+ * @defgroup RTK_BT_HCI_Exported_Functions REALTEK BT HCI Transport Exported Functions
+ *
+ * @{
+ */
+
+/**
+ * @brief Initialize host to controller data pool.
+ *
+ *   NOTE: This function shall be called before @ref rtl_bt_hci_open is invoked.
+ *
+ * @param[in] pool_size Initialize pool size.
+ * @retval true Success.
+ * @retval false Failed.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+    bool test(void)
+    {
+        if (rtl_bt_hci_h2c_pool_init(F_RTK_BT_HCI_H2C_POOL_SIZE))
+        {
+            if (rtl_bt_hci_open(bt_recv_cb))
+            {
+                return true;
+            }
+        }
+        return false;
+    }
+ * \endcode
+ */
+bool rtl_bt_hci_h2c_pool_init(uint32_t pool_size);
+
+/**
+ * @brief  Allocate BT HCI buffer from data pool.
+ * @param[in,out] p_hci_buf The BT HCI buffer that used to save HCI packet.
+ * @param[in] h4_type       The packet type @RTK_BT_HCI_TYPE.
+ * @param[in] data_size     The data length without packet type.
+ * @retval true Success.
+ * @retval false Failed.
+ */
+bool rtl_bt_hci_h2c_buf_alloc(T_RTL_BT_HCI_BUF *p_hci_buf, uint8_t h4_type, uint16_t data_size);
+
+/**
+ * @brief  Copies the given number of bytes to the end of the BT HCI buffer.
+ * @param[in] p_hci_buf The BT HCI buffer that used to copy HCI packet.
+ * @param[in] p_data    Point to the data to be added.
+ * @param[in] data_size Length of data to be added.
+ * @retval true Success.
+ * @retval false Failed.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+    bool test(uint8_t h4_type, uint8_t *p_hci_data_buf, uint16_t hci_data_size)
+    {
+        T_RTL_BT_HCI_BUF hci_buf = {0};
+
+        if (rtl_bt_hci_h2c_buf_alloc(&hci_buf, h4_type, hci_data_size) == false)
+        {
+            return false;
+        }
+
+        if (rtl_bt_hci_h2c_buf_add(&hci_buf, p_hci_data_buf, hci_data_size) == false)
+        {
+            rtl_bt_hci_h2c_buf_rel(hci_buf);
+            return false;
+        }
+
+        if (rtl_bt_hci_send(hci_buf) == false)
+        {
+            rtl_bt_hci_h2c_buf_rel(hci_buf);
+            return false;
+        }
+
+        return true;
+    }
+ * \endcode
+ */
+bool rtl_bt_hci_h2c_buf_add(T_RTL_BT_HCI_BUF *p_hci_buf, uint8_t *p_data, uint16_t data_size);
+
+/**
+ * @brief  Release BT HCI buffer.
+ * @param[in] hci_buf The BT HCI buffer that need to release.
+ * @retval true Success.
+ * @retval false Failed.
+ */
+bool rtl_bt_hci_h2c_buf_rel(T_RTL_BT_HCI_BUF hci_buf);
+
+/**
+ * @brief  Open controller BT HCI interface.
+ *
+ *   NOTE: This function shall be called after @ref rtl_bt_hci_h2c_pool_init is invoked.
+ *
+ * @param[in] p_cb Callback function: @ref P_RTL_BT_HCI_CALLBACK.
+ * @retval true Success.
+ * @retval false Failed.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+    bool bt_recv_cb(T_RTL_BT_HCI_EVT evt, bool status, uint8_t *p_buf, uint32_t len)
+    {
+        int ret = 0;
+
+        switch (evt)
+        {
+        case BT_HCI_EVT_OPENED:
+            {
+                if (status == false)
+                {
+                    //Failed to open BT HCI.
+                }
+            }
+            break;
+
+        case BT_HCI_EVT_DATA_IND:
+            {
+                switch (p_buf[0])   // First byte is packet type
+                {
+                case H4_EVT:
+                    {
+                        uint8_t event = p_buf[1]; //Event Code
+                        uint8_t length = p_buf[2];//Parameter Total Length
+                        //Send HCI event packet to BT Host
+                    }
+                    break;
+
+                case H4_ACL:
+                    {
+                        uint16_t handle;  //Connection_Handle
+                        uint16_t length;  //Data Total Length
+                        memcpy(&handle, &p_buf[1], 2);
+                        memcpy(&length, &p_buf[3], 2);
+                        //Send HCI ACL Data packet to BT Host
+                    }
+                    break;
+
+                default:
+                    break;
+                }
+                rtl_bt_hci_ack(p_buf);
+            }
+            break;
+
+        default:
+            break;
+        }
+
+        return true;
+    }
+
+    bool test(void)
+    {
+        if (rtl_bt_hci_h2c_pool_init(F_RTK_BT_HCI_H2C_POOL_SIZE))
+        {
+            if (rtl_bt_hci_open(bt_recv_cb))
+            {
+                return true;
+            }
+        }
+        return false;
+    }
+ * \endcode
+ */
+bool rtl_bt_hci_open(P_RTL_BT_HCI_CALLBACK p_cb);
+
+/**
+ * @brief  Send packet from host to controller.
+ *
+ * BT HCI driver should use this function to send packet to controller.
+ *
+ * @param[in] hci_buf The BT HCI buffer that used to send packet to controller.
+ * @retval true Success.
+ * @retval false Failed.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+    bool test(uint8_t h4_type, uint8_t *p_hci_data_buf, uint16_t hci_data_size)
+    {
+        T_RTL_BT_HCI_BUF hci_buf = {0};
+
+        if (rtl_bt_hci_h2c_buf_alloc(&hci_buf, h4_type, hci_data_size) == false)
+        {
+            return false;
+        }
+
+        if (rtl_bt_hci_h2c_buf_add(&hci_buf, p_hci_data_buf, hci_data_size) == false)
+        {
+            rtl_bt_hci_h2c_buf_rel(hci_buf);
+            return false;
+        }
+
+        if (rtl_bt_hci_send(hci_buf) == false)
+        {
+            rtl_bt_hci_h2c_buf_rel(hci_buf);
+            return false;
+        }
+
+        return true;
+    }
+ * \endcode
+ */
+bool rtl_bt_hci_send(T_RTL_BT_HCI_BUF hci_buf);
+
+/**
+ * @brief  Send packet acknowledgment response from BT Host to Controller.
+ *
+ * When BT Host has handled the message BT_HCI_EVT_DATA_IND,
+ * BT Host should use this function to ACK packet successfully received from Controller.
+ *
+ * @param[in] p_buf Point to the buffer that need to ack.
+ * @retval true Success.
+ * @retval false Failed.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+    bool bt_recv_cb(T_RTL_BT_HCI_EVT evt, bool status, uint8_t *p_buf, uint32_t len)
+    {
+        int ret = 0;
+
+        switch (evt)
+        {
+        case BT_HCI_EVT_DATA_IND:
+            {
+                switch (p_buf[0])   // First byte is packet type
+                {
+                case H4_EVT:
+                    {
+                        uint8_t event = p_buf[1]; //Event Code
+                        uint8_t length = p_buf[2];//Parameter Total Length
+                        //Send HCI event packet to BT Host
+                    }
+                    break;
+
+                case H4_ACL:
+                    {
+                        uint16_t handle;  //Connection_Handle
+                        uint16_t length;  //Data Total Length
+                        memcpy(&handle, &p_buf[1], 2);
+                        memcpy(&length, &p_buf[3], 2);
+                        //Send HCI ACL Data packet to BT Host
+                    }
+                    break;
+
+                default:
+                    break;
+                }
+                rtl_bt_hci_ack(p_buf);
+            }
+            break;
+
+        default:
+            break;
+        }
+
+        return true;
+    }
+ * \endcode
+ */
+void rtl_bt_hci_ack(uint8_t *p_buf);
+/** @} */ /* End of group RTK_BT_HCI_Exported_Functions */
+/** @} */ /* End of group RTK_BT_HCI */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTK_BT_HCI_H_ */
diff --git a/bee/drivers/bluetooth/src/CMakeLists.txt b/bee/drivers/bluetooth/src/CMakeLists.txt
new file mode 100644
index 00000000..b0128b06
--- /dev/null
+++ b/bee/drivers/bluetooth/src/CMakeLists.txt
@@ -0,0 +1,4 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_library_sources(rtl_bt_hci.c)
diff --git a/bee/drivers/bluetooth/src/rtl_bt_hci.c b/bee/drivers/bluetooth/src/rtl_bt_hci.c
new file mode 100644
index 00000000..9ac1f266
--- /dev/null
+++ b/bee/drivers/bluetooth/src/rtl_bt_hci.c
@@ -0,0 +1,707 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <string.h>
+#include "rtl_bt_hci.h"
+#include "mem_types.h"
+#include "os_mem.h"
+#include "os_sync.h"
+#if defined(CONFIG_SOC_SERIES_RTL87X2J)
+#include "soc_log.h"
+#define BT_SNOOP_UP(length, snoop)   BT_SNOOP_UP_TRACE(0, length, snoop)
+#define BT_SNOOP_DOWN(length, snoop) BT_SNOOP_DOWN_TRACE(0, length, snoop)
+#else
+#include "trace.h"
+#define BT_SNOOP_UP(length, snoop)   BT_SNOOP_UP_TRACE(length, snoop)
+#define BT_SNOOP_DOWN(length, snoop) BT_SNOOP_DOWN_TRACE(length, snoop)
+#endif
+
+#define F_RTK_BT_HCI_H2C_POOL_DEBUG_LOG 0
+#define F_RTK_BT_HCI_DRIVER_DEBUG_LOG   0
+
+#if defined(CONFIG_SOC_SERIES_RTL87X2J)
+#define RTK_BT_VHCI_VERSION 3
+#define HCI_CMD_BUF_OFFSET              7
+#define HCI_TX_ACL_RSVD_SIZE            19
+#define HCI_TX_ISO_RSVD_SIZE            19
+#else
+#define RTK_BT_VHCI_VERSION 2
+#define HCI_RX_ACL_BUF_OFFSET           19
+#define HCI_RX_ISO_BUF_OFFSET           19
+#define HCI_CMD_BUF_OFFSET              0
+#define HCI_TX_ACL_RSVD_SIZE            8
+#define HCI_TX_ISO_RSVD_SIZE            8
+#endif
+
+#if (RTK_BT_VHCI_VERSION == 3)
+typedef enum
+{
+    HCI_IF_EVT_OPEN_CMPL    = 0x00, /* hci I/F open completed */
+    HCI_IF_EVT_CLOSE_CMPL   = 0x01, /* hci I/F close completed */
+    HCI_IF_EVT_DATA_IND     = 0x02, /* hci I/F rx data indicated */
+    HCI_IF_EVT_DATA_XMIT    = 0x03, /* hci I/F tx data transmitted */
+    HCI_IF_EVT_ERROR        = 0x04, /* hci I/F error occurred */
+    HCI_IF_EVT_OPEN_FAIL    = 0x05, /* hci I/F open failed */
+    HCI_IF_EVT_CLOSE_FAIL   = 0x06, /* hci I/F close failed */
+} T_HCI_IF_EVT;
+
+typedef uint8_t (*P_HCI_IF_CALLBACK_V3)(T_HCI_IF_EVT  evt,
+    uint8_t      *p_buf,
+    uint32_t      offset,
+    uint32_t      len);
+extern bool (*vhci_open)(P_HCI_IF_CALLBACK_V3 p_callback);
+extern bool (*vhci_send)(void *p_buf, uint32_t offset, uint32_t len);
+#else
+typedef enum
+{
+    HCI_IF_EVT_OPENED = 0,     /* hci I/F open completed */
+    HCI_IF_EVT_DATA_IND = 2,   /* hci I/F rx data indicated */
+    HCI_IF_EVT_DATA_XMIT = 3,  /* hci I/F tx data transmitted */
+    HCI_IF_EVT_ERROR = 4,      /* hci I/F error occurred */
+} T_HCI_IF_EVT;
+
+typedef bool (*P_HCI_IF_CALLBACK)(T_HCI_IF_EVT evt, bool status, uint8_t *p_buf, uint32_t len);
+extern bool (*vhci_open)(P_HCI_IF_CALLBACK p_callback);
+extern bool (*vhci_send)(void *p_buf, uint32_t len);
+#endif
+extern bool (*vhci_ack)(void *p_buf);
+
+P_RTL_BT_HCI_CALLBACK p_rtl_bt_hci_cb = NULL;
+
+typedef struct t_bt_hci_buffer
+{
+    struct t_bt_hci_buffer   *p_next;     /* next free pool buffer */
+    uint32_t                  size  : 16; /* buffer size */
+    uint32_t                  flags : 3;  /* buffer flags */
+} T_BT_HCI_BUFFER;
+
+typedef struct t_bt_hci_pool
+{
+    T_BT_HCI_BUFFER   pool_start;
+    T_BT_HCI_BUFFER  *p_pool_end;
+    void             *p_start_boundary;
+    void             *p_end_boundary;
+
+    uint32_t          heap_size_unused;
+    uint16_t          buf_num_used;
+} T_BT_HCI_POOL;
+
+/* BT HCI Pool Bit Mask */
+#define BT_HCI_FLAG_BUFFER_ALLOCATED   0x01
+#define BT_HCI_POOL_HDR_SIZE           sizeof(T_BT_HCI_BUFFER)
+#define BT_HCI_POOL_BUFFER_ADDR_MASK   (sizeof(void *) - 1)
+#define BT_HCI_POOL_BUFFER_ALIGN_SIZE  (1 << 4)
+#define BT_HCI_POOL_BUFFER_ALIGN_MASK  (BT_HCI_POOL_BUFFER_ALIGN_SIZE - 1)
+#define BT_HCI_POOL_BUFFER_MINI_SIZE   (BT_HCI_POOL_BUFFER_ALIGN_SIZE << 1)
+
+T_BT_HCI_POOL hci_if_pool;
+
+bool rtl_bt_hci_h2c_pool_init(uint32_t pool_size)
+{
+    if (hci_if_pool.p_start_boundary == NULL)
+    {
+        uint8_t      *p_heap;
+        uint8_t      *p_heap_start;
+        uint8_t      *p_heap_end;
+        uint32_t      heap_size;
+        T_BT_HCI_BUFFER *p_buf;
+
+        hci_if_pool.buf_num_used = 0;
+
+        heap_size = pool_size;
+
+        p_heap = os_mem_zalloc(RAM_TYPE_BUFFER_ON, heap_size);
+        if (p_heap == NULL)
+        {
+            DBG_DIRECT("[POOL] init: alloc failed, size %d", heap_size);
+            return false;
+        }
+
+        p_heap_start = p_heap;
+
+        /* make pool heap start address alignment */
+
+        if ((size_t)p_heap_start & BT_HCI_POOL_BUFFER_ALIGN_MASK)
+        {
+            p_heap_start += BT_HCI_POOL_BUFFER_ALIGN_SIZE - 1;
+            p_heap_start  = (uint8_t *)((size_t)p_heap_start &
+                                        ~BT_HCI_POOL_BUFFER_ALIGN_MASK);
+            heap_size    -= (size_t)p_heap_start - (size_t)p_heap;
+        }
+
+        hci_if_pool.pool_start.p_next = (void *)p_heap_start;
+        hci_if_pool.pool_start.size   = 0;
+
+        /* make pool heap end address alignment */
+
+        p_heap_end  = p_heap_start + heap_size - BT_HCI_POOL_HDR_SIZE;
+        p_heap_end  = (uint8_t *)((size_t)p_heap_end &
+                                  ~BT_HCI_POOL_BUFFER_ALIGN_MASK);
+
+        hci_if_pool.p_pool_end          = (T_BT_HCI_BUFFER *)p_heap_end;
+        hci_if_pool.p_pool_end->p_next  = NULL;
+        hci_if_pool.p_pool_end->size    = 0;
+
+        p_buf           = (T_BT_HCI_BUFFER *)p_heap_start;
+        p_buf->p_next   = (T_BT_HCI_BUFFER *)p_heap_end;
+        p_buf->size     = (size_t)p_heap_end - (size_t)p_heap_start;
+
+        hci_if_pool.heap_size_unused = p_buf->size;
+
+        hci_if_pool.p_start_boundary = hci_if_pool.pool_start.p_next;
+        hci_if_pool.p_end_boundary   = hci_if_pool.p_pool_end;
+#if F_RTK_BT_HCI_H2C_POOL_DEBUG_LOG
+        DBG_DIRECT("[POOL] init: pool_size %d, p_heap %p, heap_size_unused %d, boundary(%p - %p)",
+                   pool_size, p_heap,
+                   hci_if_pool.heap_size_unused, hci_if_pool.p_start_boundary,
+                   hci_if_pool.p_end_boundary);
+#endif
+        return true;
+    }
+    DBG_DIRECT("[POOL] init: failed");
+    return false;
+}
+
+#if F_RTK_BT_HCI_H2C_POOL_DEBUG_LOG
+void rtl_bt_hci_dump(void)
+{
+    T_BT_HCI_BUFFER  *p_hdr;
+    uint32_t       s;
+
+    s = os_lock();
+
+    DBG_DIRECT("[POOL] dump: heap_size_unused %d, buf_num_used %d",
+               hci_if_pool.heap_size_unused,  hci_if_pool.buf_num_used);
+
+    p_hdr = hci_if_pool.pool_start.p_next;
+
+    while (p_hdr != NULL)
+    {
+        DBG_DIRECT("[POOL] dump: free list hdr %p, next %p, size %d, flags 0x%01x",
+                   p_hdr, p_hdr->p_next, p_hdr->size, p_hdr->flags);
+
+        p_hdr = p_hdr->p_next;
+    }
+
+    os_unlock(s);
+}
+#endif
+
+bool rtl_bt_hci_h2c_buf_alloc(T_RTL_BT_HCI_BUF *p_hci_buf, uint8_t h4_type, uint16_t data_size)
+{
+    uint8_t         *p_buf = NULL;
+    T_BT_HCI_BUFFER *p_prev_hdr;
+    T_BT_HCI_BUFFER *p_curr_hdr;
+    uint16_t         buf_size;
+    uint8_t          pkt_offset = (sizeof(void *));
+    uint8_t          err_idx = 0;
+    uint32_t         s;
+
+    s = os_lock();
+
+    if (p_hci_buf == NULL || data_size == 0)
+    {
+        err_idx = 1;
+        goto FAILED;
+    }
+
+    if (h4_type == H4_ACL)
+    {
+        buf_size = data_size + pkt_offset + 1 + HCI_TX_ACL_RSVD_SIZE;
+    }
+    else if (h4_type == H4_ISO)
+    {
+        buf_size = data_size + pkt_offset + 1 + HCI_TX_ISO_RSVD_SIZE;
+    }
+    else if (h4_type == H4_CMD)
+    {
+        buf_size = data_size + pkt_offset + 1 + HCI_CMD_BUF_OFFSET;
+    }
+    else
+    {
+        err_idx = 2;
+        goto FAILED;
+    }
+
+    buf_size += BT_HCI_POOL_HDR_SIZE;
+
+    if (buf_size & BT_HCI_POOL_BUFFER_ALIGN_MASK)
+    {
+        buf_size = (buf_size + BT_HCI_POOL_BUFFER_ALIGN_SIZE - 1) &
+                   ~BT_HCI_POOL_BUFFER_ALIGN_MASK;
+    }
+
+    if (buf_size > hci_if_pool.heap_size_unused)
+    {
+        err_idx = 3;
+        goto FAILED;
+    }
+
+    p_prev_hdr = &hci_if_pool.pool_start;
+    p_curr_hdr = hci_if_pool.pool_start.p_next;
+
+    while (p_curr_hdr->size < buf_size && p_curr_hdr->p_next != NULL)
+    {
+        p_prev_hdr = p_curr_hdr;
+        p_curr_hdr = p_curr_hdr->p_next;
+    }
+
+    if (p_curr_hdr == hci_if_pool.p_pool_end)
+    {
+        err_idx = 4;
+        goto FAILED;
+    }
+
+    p_buf = (uint8_t *)p_prev_hdr->p_next + BT_HCI_POOL_HDR_SIZE;
+
+    if (p_curr_hdr->size - buf_size >= BT_HCI_POOL_BUFFER_MINI_SIZE)
+    {
+        T_BT_HCI_BUFFER *p_tmp_hdr;
+
+        p_tmp_hdr = (T_BT_HCI_BUFFER *)((uint8_t *)p_prev_hdr->p_next +
+                                        buf_size);
+        p_tmp_hdr->p_next = p_curr_hdr->p_next;
+        p_tmp_hdr->size   = p_curr_hdr->size - buf_size;
+        p_tmp_hdr->flags  = 0;
+
+        p_prev_hdr->p_next = p_tmp_hdr;
+        p_curr_hdr->size   = buf_size;
+
+        hci_if_pool.heap_size_unused -= buf_size;
+    }
+    else
+    {
+        p_prev_hdr->p_next = p_curr_hdr->p_next;
+
+        hci_if_pool.heap_size_unused -= p_curr_hdr->size;
+    }
+
+    p_curr_hdr->p_next     = NULL;
+    p_curr_hdr->flags      = BT_HCI_FLAG_BUFFER_ALLOCATED;
+
+    p_hci_buf->p_h2c_buf      = p_buf + pkt_offset;
+    p_hci_buf->h2c_buf_size   = 1;
+    p_hci_buf->h2c_buf_size_max = data_size + 1;
+
+    memcpy(p_buf + pkt_offset, &h4_type, 1);
+    if (h4_type == H4_ACL)
+    {
+        p_hci_buf->h2c_buf_size   += HCI_TX_ACL_RSVD_SIZE;
+        p_hci_buf->h2c_buf_size_max += HCI_TX_ACL_RSVD_SIZE;
+        memcpy(p_buf + pkt_offset + HCI_TX_ACL_RSVD_SIZE, &h4_type, 1);
+    }
+    else if (h4_type == H4_ISO)
+    {
+        p_hci_buf->h2c_buf_size   += HCI_TX_ISO_RSVD_SIZE;
+        p_hci_buf->h2c_buf_size_max += HCI_TX_ISO_RSVD_SIZE;
+        memcpy(p_buf + pkt_offset + HCI_TX_ISO_RSVD_SIZE, &h4_type, 1);
+    }
+    else if (h4_type == H4_CMD && HCI_CMD_BUF_OFFSET != 0)
+    {
+        p_hci_buf->h2c_buf_size   += HCI_CMD_BUF_OFFSET;
+        p_hci_buf->h2c_buf_size_max += HCI_CMD_BUF_OFFSET;
+        memcpy(p_buf + pkt_offset + HCI_CMD_BUF_OFFSET, &h4_type, 1);
+    }
+
+    memcpy(p_buf + pkt_offset - sizeof(p_buf), &p_buf, sizeof(p_buf));
+
+    hci_if_pool.buf_num_used++;
+
+    os_unlock(s);
+
+#if F_RTK_BT_HCI_H2C_POOL_DEBUG_LOG
+    DBG_DIRECT("[POOL] alloc: buf_size %d, p_buf %p",
+               buf_size, p_buf);
+#endif
+
+    return true;
+FAILED:
+    os_unlock(s);
+    DBG_DIRECT("[POOL] alloc: failed, err_idx %d", err_idx);
+    return false;
+}
+
+bool rtl_bt_hci_h2c_buf_add(T_RTL_BT_HCI_BUF *p_hci_buf, uint8_t *p_data, uint16_t data_size)
+{
+    uint32_t      s;
+
+    s = os_lock();
+    if (p_hci_buf != NULL && p_data != NULL && data_size != 0)
+    {
+        if (p_hci_buf->p_h2c_buf &&
+            (p_hci_buf->h2c_buf_size + data_size) <= p_hci_buf->h2c_buf_size_max)
+        {
+            memcpy(p_hci_buf->p_h2c_buf + p_hci_buf->h2c_buf_size, p_data, data_size);
+            p_hci_buf->h2c_buf_size   += data_size;
+            os_unlock(s);
+            return true;
+        }
+    }
+    os_unlock(s);
+    DBG_DIRECT("[POOL] add: failed, data_size %d", data_size);
+    return false;
+}
+
+bool rtl_bt_hci_h2c_buf_release(uint8_t *p_h2c_buf)
+{
+    T_BT_HCI_BUFFER          *p_hdr;
+    T_BT_HCI_BUFFER          *p_curr_hdr;
+    void                     *p_buf = NULL;
+    uint32_t                  s;
+    uint8_t                   err_idx = 0;
+
+    s = os_lock();
+
+    if (p_h2c_buf == NULL)
+    {
+        err_idx = 1;
+        goto FAILED;
+    }
+
+    memcpy(&p_buf, p_h2c_buf - sizeof(p_buf), sizeof(p_buf));
+
+    if ((p_buf == NULL) || ((size_t)p_buf & BT_HCI_POOL_BUFFER_ADDR_MASK))
+    {
+        err_idx = 2;
+        goto FAILED;
+    }
+
+    if (hci_if_pool.p_start_boundary > p_buf ||
+        hci_if_pool.p_end_boundary < p_buf)
+    {
+        err_idx = 3;
+        goto FAILED;
+    }
+
+    p_hdr = (void *)((uint8_t *)p_buf - BT_HCI_POOL_HDR_SIZE);
+
+    if (!(p_hdr->flags & BT_HCI_FLAG_BUFFER_ALLOCATED))
+    {
+        err_idx = 4;
+        goto FAILED;
+    }
+
+    p_hdr->flags = 0;
+
+    hci_if_pool.heap_size_unused += p_hdr->size;
+
+    hci_if_pool.buf_num_used--;
+
+    p_curr_hdr = &hci_if_pool.pool_start;
+    while (p_curr_hdr->p_next < p_hdr)
+    {
+        p_curr_hdr = p_curr_hdr->p_next;
+    }
+
+    /* merge left contiguous buffers */
+
+    if ((uint8_t *)p_curr_hdr + p_curr_hdr->size == (uint8_t *)p_hdr)
+    {
+        p_curr_hdr->size += p_hdr->size;
+        p_hdr = p_curr_hdr;
+    }
+
+    /* merge right contiguous buffers */
+
+    if ((uint8_t *)p_hdr + p_hdr->size == (uint8_t *)p_curr_hdr->p_next)
+    {
+        if (p_curr_hdr->p_next != hci_if_pool.p_pool_end)
+        {
+            p_hdr->size   += p_curr_hdr->p_next->size;
+            p_hdr->p_next  = p_curr_hdr->p_next->p_next;
+        }
+        else
+        {
+            p_hdr->p_next = hci_if_pool.p_pool_end;
+        }
+    }
+    else
+    {
+        p_hdr->p_next = p_curr_hdr->p_next;
+    }
+
+    /* no left merge */
+
+    if (p_curr_hdr != p_hdr)
+    {
+        p_curr_hdr->p_next = p_hdr;
+    }
+
+    os_unlock(s);
+
+#if F_RTK_BT_HCI_H2C_POOL_DEBUG_LOG
+    DBG_DIRECT("[POOL] release: p_buf %p", p_buf);
+    rtl_bt_hci_dump();
+#endif
+
+    return true;
+FAILED:
+    os_unlock(s);
+    DBG_DIRECT("[POOL] release: failed, p_buf %p", p_buf);
+    return false;
+}
+
+bool rtl_bt_hci_h2c_buf_rel(T_RTL_BT_HCI_BUF hci_buf)
+{
+    return rtl_bt_hci_h2c_buf_release(hci_buf.p_h2c_buf);
+}
+
+#if (RTK_BT_VHCI_VERSION == 3)
+uint8_t rtl_bt_hci_cb(T_HCI_IF_EVT evt, uint8_t *p_buf, uint32_t offset, uint32_t len)
+{
+    bool result = true;
+
+#if F_RTK_BT_HCI_DRIVER_DEBUG_LOG
+    DBG_DIRECT("[BT] c2h cb v3: evt %d, p_buf %p, offset %d, len %d", evt, (void *)p_buf, offset, len);
+#endif
+
+    switch (evt)
+    {
+    case HCI_IF_EVT_OPEN_CMPL:
+        {
+            if (p_rtl_bt_hci_cb)
+            {
+                result = (*p_rtl_bt_hci_cb)(BT_HCI_EVT_OPENED, true, NULL, 0);
+            }
+        }
+        break;
+
+    case HCI_IF_EVT_OPEN_FAIL:
+        {
+            if (p_rtl_bt_hci_cb)
+            {
+                result = (*p_rtl_bt_hci_cb)(BT_HCI_EVT_OPENED, false, NULL, 0);
+            }
+        }
+        break;
+
+    case HCI_IF_EVT_DATA_IND:
+        {
+            uint8_t *p_c2h_buf;
+            uint16_t buf_offset;
+            offset -= 1;
+            len    += 1;
+            p_buf[offset] = p_buf[0];
+            p_c2h_buf = p_buf + offset;
+            buf_offset = offset;
+
+            if (p_buf[0] == H4_EVT || p_buf[0] == H4_ACL || p_buf[0] == H4_ISO)
+            {
+                if (p_rtl_bt_hci_cb)
+                {
+                    BT_SNOOP_UP(len, p_c2h_buf);
+
+                    memcpy(p_c2h_buf - sizeof(buf_offset), &buf_offset, sizeof(buf_offset));
+                    result = (*p_rtl_bt_hci_cb)(BT_HCI_EVT_DATA_IND, true, p_c2h_buf, len);
+                    break;
+                }
+            }
+            else
+            {
+                DBG_DIRECT("[BT] c2h cb v3: unknown pkt type %d", p_buf[0]);
+                result = false;
+            }
+#if F_RTK_BT_HCI_DRIVER_DEBUG_LOG
+            DBG_DIRECT("[BT] c2h v3: type %d, vhci_ack %p", p_buf[0], p_buf);
+#endif
+            vhci_ack(p_buf);
+        }
+        break;
+
+    case HCI_IF_EVT_DATA_XMIT:
+        {
+            rtl_bt_hci_h2c_buf_release(p_buf);
+        }
+        break;
+
+    default:
+        result = false;
+        break;
+    }
+#if F_RTK_BT_HCI_DRIVER_DEBUG_LOG
+    //DBG_DIRECT("[BT] c2h cb v3: end, p_buf %p", p_buf);
+#endif
+    return 0;
+}
+#else
+bool rtl_bt_hci_cb(T_HCI_IF_EVT evt, bool status, uint8_t *p_buf, uint32_t len)
+{
+    bool result = true;
+
+#if F_RTK_BT_HCI_DRIVER_DEBUG_LOG
+    DBG_DIRECT("[BT] c2h cb: evt %d, status %d, p_buf %p, len %d", evt, status, (void *)p_buf, len);
+#endif
+
+    switch (evt)
+    {
+    case HCI_IF_EVT_OPENED:
+        {
+            if (p_rtl_bt_hci_cb)
+            {
+                result = (*p_rtl_bt_hci_cb)(BT_HCI_EVT_OPENED, status, NULL, 0);
+            }
+        }
+        break;
+
+    case HCI_IF_EVT_DATA_IND:
+        {
+            if (p_buf[0] == H4_EVT)
+            {
+                if (p_rtl_bt_hci_cb)
+                {
+                    BT_SNOOP_UP(len, p_buf);
+
+                    result = (*p_rtl_bt_hci_cb)(BT_HCI_EVT_DATA_IND, status, p_buf, len);
+                    break;
+                }
+            }
+            else if (p_buf[0] == H4_ACL)
+            {
+                if (p_rtl_bt_hci_cb)
+                {
+                    if (len > HCI_RX_ACL_BUF_OFFSET)
+                    {
+                        p_buf[HCI_RX_ACL_BUF_OFFSET] = H4_ACL;
+                        BT_SNOOP_UP(len - HCI_RX_ACL_BUF_OFFSET, p_buf + HCI_RX_ACL_BUF_OFFSET);
+
+                        result = (*p_rtl_bt_hci_cb)(BT_HCI_EVT_DATA_IND, status, p_buf + HCI_RX_ACL_BUF_OFFSET,
+                                                    len - HCI_RX_ACL_BUF_OFFSET);
+                        break;
+                    }
+
+                }
+            }
+            else if (p_buf[0] == H4_ISO)
+            {
+                if (p_rtl_bt_hci_cb)
+                {
+                    if (len > HCI_RX_ISO_BUF_OFFSET)
+                    {
+                        p_buf[HCI_RX_ISO_BUF_OFFSET] = H4_ISO;
+                        BT_SNOOP_UP(len - HCI_RX_ISO_BUF_OFFSET, p_buf + HCI_RX_ISO_BUF_OFFSET);
+
+                        result = (*p_rtl_bt_hci_cb)(BT_HCI_EVT_DATA_IND, status, p_buf + HCI_RX_ISO_BUF_OFFSET,
+                                                    len - HCI_RX_ISO_BUF_OFFSET);
+                        break;
+                    }
+
+                }
+            }
+            else
+            {
+                DBG_DIRECT("[BT] c2h cb: unknown pkt type %d", p_buf[0]);
+                result = false;
+            }
+#if F_RTK_BT_HCI_DRIVER_DEBUG_LOG
+            DBG_DIRECT("[BT] c2h: type %d, vhci_ack %p", p_buf[0], p_buf);
+#endif
+            vhci_ack(p_buf);
+        }
+        break;
+
+    case HCI_IF_EVT_DATA_XMIT:
+        {
+            rtl_bt_hci_h2c_buf_release(p_buf);
+        }
+        break;
+
+    default:
+        result = false;
+        break;
+    }
+#if F_RTK_BT_HCI_DRIVER_DEBUG_LOG
+    //DBG_DIRECT("[BT] c2h cb: end, p_buf %p", p_buf);
+#endif
+    return result;
+}
+#endif
+
+bool rtl_bt_hci_open(P_RTL_BT_HCI_CALLBACK p_callback)
+{
+    p_rtl_bt_hci_cb = p_callback;
+    return vhci_open(rtl_bt_hci_cb);
+}
+
+bool rtl_bt_hci_send(T_RTL_BT_HCI_BUF hci_buf)
+{
+    if (hci_buf.p_h2c_buf)
+    {
+        uint8_t pkt_offset;
+        if (hci_buf.p_h2c_buf[0] == H4_CMD)
+        {
+            pkt_offset = HCI_CMD_BUF_OFFSET;
+        }
+        else if (hci_buf.p_h2c_buf[0] == H4_ACL)
+        {
+            pkt_offset = HCI_TX_ACL_RSVD_SIZE;
+        }
+        else if (hci_buf.p_h2c_buf[0] == H4_ISO)
+        {
+            pkt_offset = HCI_TX_ISO_RSVD_SIZE;
+        }
+        else
+        {
+            return false;
+        }
+        BT_SNOOP_DOWN(hci_buf.h2c_buf_size - pkt_offset,
+            hci_buf.p_h2c_buf + pkt_offset);
+#if F_RTK_BT_HCI_DRIVER_DEBUG_LOG
+        DBG_DIRECT("[BT] h2c data: p_buf %p, len %d, pkt_offset %d, type %d", hci_buf.p_h2c_buf,
+                   hci_buf.h2c_buf_size, pkt_offset, hci_buf.p_h2c_buf[0]);
+#endif
+
+#if (RTK_BT_VHCI_VERSION == 3)
+        pkt_offset++;
+        if (vhci_send(hci_buf.p_h2c_buf, pkt_offset, hci_buf.h2c_buf_size - pkt_offset))
+#else
+        if (vhci_send(hci_buf.p_h2c_buf, hci_buf.h2c_buf_size))
+#endif
+        {
+            return true;
+        }
+    }
+    return false;
+}
+
+void rtl_bt_hci_ack(uint8_t *p_buf)
+{
+    if (p_buf)
+    {
+#if (RTK_BT_VHCI_VERSION == 3)
+        uint8_t *p_controller_buf;
+        uint16_t buf_offset;
+
+        memcpy(&buf_offset, p_buf - sizeof(buf_offset), sizeof(buf_offset));
+        p_controller_buf = p_buf - buf_offset;
+#if F_RTK_BT_HCI_DRIVER_DEBUG_LOG
+        DBG_DIRECT("[BT] event vhci_ack %p, buf_offset %d", p_controller_buf, buf_offset);
+#endif
+        vhci_ack(p_controller_buf);
+#else
+        if (p_buf[0] == H4_EVT)
+        {
+#if F_RTK_BT_HCI_DRIVER_DEBUG_LOG
+            DBG_DIRECT("[BT] event vhci_ack %p", p_buf);
+#endif
+            vhci_ack(p_buf);
+        }
+        else if (p_buf[0] == H4_ACL)
+        {
+#if F_RTK_BT_HCI_DRIVER_DEBUG_LOG
+            DBG_DIRECT("[BT] acl vhci_ack %p", p_buf - HCI_RX_ACL_BUF_OFFSET);
+#endif
+            vhci_ack(p_buf - HCI_RX_ACL_BUF_OFFSET);
+        }
+        else if (p_buf[0] == H4_ISO)
+        {
+#if F_RTK_BT_HCI_DRIVER_DEBUG_LOG
+            DBG_DIRECT("[BT] iso vhci_ack %p", p_buf - HCI_RX_ISO_BUF_OFFSET);
+#endif
+            vhci_ack(p_buf - HCI_RX_ISO_BUF_OFFSET);
+        }
+#endif
+    }
+}
diff --git a/bee/drivers/can/CMakeLists.txt b/bee/drivers/can/CMakeLists.txt
new file mode 100644
index 00000000..7a95ba90
--- /dev/null
+++ b/bee/drivers/can/CMakeLists.txt
@@ -0,0 +1,8 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+if(CONFIG_REALTEK_BEE_COMMON_DRIVER)
+    zephyr_include_directories(inc)
+endif()
+
+add_subdirectory_ifdef(CONFIG_REALTEK_BEE_CAN src)
diff --git a/bee/drivers/can/Kconfig b/bee/drivers/can/Kconfig
new file mode 100644
index 00000000..e035245e
--- /dev/null
+++ b/bee/drivers/can/Kconfig
@@ -0,0 +1,8 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config REALTEK_BEE_CAN
+	bool "Realtek Bee CAN driver"
+	default n
+	help
+	  This option enables the CAN driver for Realtek Bee.
diff --git a/bee/drivers/can/inc/rtl_can.h b/bee/drivers/can/inc/rtl_can.h
new file mode 100644
index 00000000..ee99c596
--- /dev/null
+++ b/bee/drivers/can/inc/rtl_can.h
@@ -0,0 +1,1485 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *               Define to prevent recursive inclusion
+ *============================================================================*/
+#ifndef _RTL_CAN_H_
+#define _RTL_CAN_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*============================================================================*
+ *                        Header Files
+ *============================================================================*/
+#include "utils/rtl_utils.h"
+#if defined (CONFIG_SOC_SERIES_RTL87X2G)
+#include "can/src/device/rtl87x2g/rtl_can_def.h"
+#elif defined (CONFIG_SOC_SERIES_RTL87X3EP)
+#include "can/src/device/rtl87x3ep/rtl_can_def.h"
+#elif defined (CONFIG_SOC_SERIES_RTL87X2J)
+#include "can/src/device/rtl87x2j/rtl_can_def.h"
+#elif defined (CONFIG_SOC_SERIES_RTL87X3EU)
+#include "can/src/device/rtl87x3eu/rtl_can_def.h"
+#endif
+
+/*============================================================================*
+ *                          Private Macros
+ *============================================================================*/
+#define CAN_MESSAGE_BUFFER_MAX_CNT      16
+#define CAN_MESSAGE_BUFFER_MAX_INDEX    (CAN_MESSAGE_BUFFER_MAX_CNT - 1)
+#define CAN_MESSAGE_BUFFER_DEFAULT_LEN  20
+#define CAN_MESSAGE_FIFO_START_ID       12
+#define CAN_DEFAULT_ERR_WARN_TH         96
+#define CAN_STAND_DATA_MAX_LEN          8
+#define CAN_RAM_DATA_MAX_INDEX          1
+#define CAN_STD_FRAME_ID_POS            18
+#define CAN_EXT_FRAME_ID_POS            0
+#define CAN_RAM_ACC_DATA_POS            11
+#define CAN_STAND_FRAME_ID_MAX_VALUE    0x7FFUL
+#define CAN_EXTEND_FRAME_ID_MAX_VALUE   0x3FFFFUL
+#define CAN_FRAME_ID_MASK_MAX_VALUE     0x1FFFFFFFUL
+
+/** \defgroup CAN         CAN
+  * \brief
+  * \{
+  */
+/*============================================================================*
+ *                         Constants
+ *============================================================================*/
+/** \defgroup CAN_Exported_Constants CAN Exported Constants
+  * \brief
+  * \{
+  */
+
+/**
+ * \defgroup    CAN_DLC_Byte CAN DLC Byte
+ * \{
+ * \ingroup     CAN_Exported_Constants
+ */
+#define CAN_DLC_BYTES_0                 (0x0UL)     //!< Data length = 0 byte.
+#define CAN_DLC_BYTES_1                 (0x1UL)     //!< Data length = 1 byte.
+#define CAN_DLC_BYTES_2                 (0x2UL)     //!< Data length = 2 bytes.
+#define CAN_DLC_BYTES_3                 (0x3UL)     //!< Data length = 3 bytes.
+#define CAN_DLC_BYTES_4                 (0x4UL)     //!< Data length = 4 bytes.
+#define CAN_DLC_BYTES_5                 (0x5UL)     //!< Data length = 5 bytes.
+#define CAN_DLC_BYTES_6                 (0x6UL)     //!< Data length = 6 bytes.
+#define CAN_DLC_BYTES_7                 (0x7UL)     //!< Data length = 7 bytes.
+#define CAN_DLC_BYTES_8                 (0x8UL)     //!< Data length = 8 bytes.
+
+/** End of CAN_DLC_Byte
+  * \}
+  */
+
+/**
+ * \defgroup    CAN_Interrupt_Definition CAN Interrupt Definition
+ * \{
+ * \ingroup     CAN_Exported_Constants
+ */
+#define CAN_RAM_MOVE_DONE_INT                       BIT5    //!< Triggered when data move from register to CAN IP internal RAM finished.
+#define CAN_BUS_OFF_INT                             BIT4    //!< Triggered when the bus is off.
+#define CAN_WAKE_UP_INT                             BIT3    //!< Triggered when CAN awakened from low power mode.
+#define CAN_ERROR_INT                               BIT2    //!< Triggered by an error during transmission.
+#define CAN_RX_INT                                  BIT1    //!< Triggered when data is received.
+#define CAN_TX_INT                                  BIT0    //!< Triggered when sending is completed.
+
+#define IS_CAN_INT_CONFIG(CONFIG)     (((CONFIG) == CAN_RAM_MOVE_DONE_INT)  || \
+                                       ((CONFIG) == CAN_BUS_OFF_INT)        || \
+                                       ((CONFIG) == CAN_WAKE_UP_INT)        || \
+                                       ((CONFIG) == CAN_ERROR_INT)          || \
+                                       ((CONFIG) == CAN_RX_INT)             || \
+                                       ((CONFIG) == CAN_TX_INT))
+
+/** End of CAN_Interrupt_Definition
+  * \}
+  */
+
+/**
+ * \defgroup    CAN_Interrupt_Flag CAN Interrupt Flag
+ * \{
+ * \ingroup     CAN_Exported_Constants
+ */
+#define CAN_RAM_MOVE_DONE_INT_FLAG                  BIT5    //!< Triggered when data move from register to CAN IP internal RAM finished.
+#define CAN_BUS_OFF_INT_FLAG                        BIT4    //!< Triggered when the bus is off.
+#define CAN_WAKE_UP_INT_FLAG                        BIT3    //!< Triggered when CAN awakened from low power mode.
+#define CAN_ERROR_INT_FLAG                          BIT2    //!< Triggered by an error during transmission.
+#define CAN_RX_INT_FLAG                             BIT1    //!< Triggered when data is received.
+#define CAN_TX_INT_FLAG                             BIT0    //!< Triggered when sending is completed.
+
+#define IS_CAN_INT_FLAG(FLAG)         (((CONFIG) == CAN_RAM_MOVE_DONE_INT_FLAG) || \
+                                       ((CONFIG) == CAN_BUS_OFF_INT_FLAG)       || \
+                                       ((CONFIG) == CAN_WAKE_UP_INT_FLAG)       || \
+                                       ((CONFIG) == CAN_ERROR_INT_FLAG)         || \
+                                       ((CONFIG) == CAN_RX_INT_FLAG)            || \
+                                       ((CONFIG) == CAN_TX_INT_FLAG))
+
+/** End of CAN_Interrupt_Flag
+  * \}
+  */
+
+/**
+ * \defgroup    CAN_Error_Mask CAN Error Mask
+ * \{
+ * \ingroup     CAN_Exported_Constants
+ */
+#define CAN_ERROR_RX                                BIT9    //!< Receiving error occurred.
+#define CAN_ERROR_TX                                BIT8    //!< Sending error occurred.
+#define CAN_ERROR_ACK                               BIT5    //!< Ack error occurred.
+#define CAN_ERROR_STUFF                             BIT4    //!< Stuff error occurred.
+#define CAN_ERROR_CRC                               BIT3    //!< CRC error occurred.
+#define CAN_ERROR_FORM                              BIT2    //!< Form error occurred.
+#define CAN_ERROR_BIT1                              BIT1    //!< BIT1 error occurred.
+#define CAN_ERROR_BIT0                              BIT0    //!< BIT0 error occurred.
+
+#define IS_CAN_ERROR_STATUS(STATUS)   (((STATUS) == CAN_ERROR_RX)   || \
+                                       ((STATUS) == CAN_ERROR_TX)   || \
+                                       ((STATUS) == CAN_ERROR_ACK)  || \
+                                       ((STATUS) == CAN_ERROR_CRC)  || \
+                                       ((STATUS) == CAN_ERROR_FORM) || \
+                                       ((STATUS) == CAN_ERROR_BIT1) || \
+                                       ((STATUS) == CAN_ERROR_BIT0))
+
+/** End of CAN_Error_Mask
+  * \}
+  */
+
+/** End of CAN_Exported_Constants
+  * \}
+  */
+
+/*============================================================================*
+ *                         Types
+ *============================================================================*/
+/** \defgroup CAN_Exported_Types CAN Exported Types
+  * \brief
+  * \{
+  */
+
+/**
+ * \brief       CAN init structure definition.
+ *
+ * \ingroup     CAN_Exported_Types
+ */
+typedef struct
+{
+    uint8_t CAN_AutoReTxEn;                 /*!< Specifies Whether the auto re-transmission function is enable. */
+    uint8_t CAN_RxFifoEn;                   /*!< Specifies Whether the rx fifo function is enable. */
+    uint8_t CAN_RxDMAEn;                    /*!< Specifies Whether the rx dma function is enable. */
+    uint8_t CAN_TestModeSel;                /*!< Specifies the test mode of CAN.
+                                                        This parameter can be a value of @ref CANTestModeSel_TypeDef */
+    uint16_t CAN_ErrorWarnThd;              /*!< Specifies error counter warning threshold. */
+    CAN_0x0C_TYPE_TypeDef CAN_BitTiming;    /*!< Specifies the bit timing of CAN. */
+    CAN_0x40_TYPE_TypeDef CAN_TimeStamp;    /*!< Specifies the timestamp function of CAN. */
+} CAN_InitTypeDef;
+
+typedef enum
+{
+    CAN_BUS_STATE_OFF,          //!< CAN state on.
+    CAN_BUS_STATE_ON,           //!< CAN state off.
+} CANBusStateSel_TypeDef;
+
+typedef enum
+{
+    CAN_RAM_STATE_IDLE,         //!< CAN RAM is idle.
+    CAN_RAM_STATE_EXCHANGING,   //!< CAN RAM is exchanging.
+} CANRamStateSel_TypeDef;
+
+typedef enum
+{
+    CAN_TEST_MODE_SILENCE,          //!< Silence mode.
+#if CAN_SUPPORT_EXT_LOOPBACK
+    CAN_TEST_MODE_EXT_LOOPBACK,     //!< External loopback mode.
+#endif
+    CAN_TEST_MODE_INT_LOOPBACK,     //!< Internal loopback mode.
+    CAN_TEST_MODE_NONE,             //!< No test mode.
+} CANTestModeSel_TypeDef;
+
+typedef enum
+{
+    CAN_RTR_DATA_FRAME = 0,         //!< Data frame.
+    CAN_RTR_REMOTE_FRAME = 1,       //!< Remote frame.
+} CANRtrSel_TypeDef;
+
+typedef enum
+{
+    CAN_IDE_STANDARD_FORMAT = 0,    //!< Standard ID.
+    CAN_IDE_EXTEND_FORMAT = 1,      //!< Extend ID.
+} CANIdeSel_TypeDef;
+
+typedef enum
+{
+    CAN_EDL_STARDARD_FRAME = 0,     //!< Standard frame.
+} CANEdlSel_TypeDef;
+
+typedef enum
+{
+    CAN_INVALID_DATA_FRAME,             //!< Invalide data frame.
+    CAN_STD_DATA_FRAME,                 //!< Standard data frame.
+    CAN_EXT_DATA_FRAME,                 //!< Extend data frame.
+    CAN_STD_REMOTE_FRAME,               //!< Standard remote frame.
+    CAN_EXT_REMOTE_FRAME,               //!< Extend remote frame.
+} CANDataFrameSel_TypeDef;
+
+typedef enum
+{
+    CAN_NO_ERR = 0,                     //!< No error.
+    CAN_MSG_ID_ERR = 1,                 //!< Can message id error.
+    CAN_ID_ERR = 2,                     //!< Can frame id error.
+    CAN_DATA_LEN_ERR = 3,               //!< Can frame data length error.
+    CAN_TYPE_ERR = 4,                   //!< Can frame type error.
+    CAN_RAM_STATE_ERR = 5,              //!< Can frame ram status error.
+    CAN_TIMEOUT_ERR = 6,                //!< Can timeout error.
+} CANError_TypeDef;
+
+typedef struct
+{
+    uint8_t msg_buf_id;                 //!< Message buffer ID.
+    uint8_t auto_reply_bit;             //!< The auto reply bit of frame.
+    CANDataFrameSel_TypeDef frame_type; //!< The type of frame.
+    uint16_t standard_frame_id;         //!< The standard frame ID.
+    uint32_t extend_frame_id;           //!< The extend frame ID.
+} CANTxFrame_TypeDef;
+
+typedef struct
+{
+    uint8_t msg_buf_id;                         //!< Message buffer ID.
+    uint8_t rx_dma_en;                          //!< The dma enable bit of RX frame.
+    CANFrameRTRMask_TypeDef frame_rtr_mask;     //!< Can frame RTR mask.
+    CANFrameIDEMask_TypeDef frame_ide_mask;     //!< Can frame IDE mask.
+    uint32_t frame_id_mask;                     //!< Can frame ID mask.
+    uint8_t frame_rtr_bit;                      //!< Can frame RTR bit, determine DATA or REMOTE frame.
+    uint8_t frame_ide_bit;                      //!< Can frame IDE bit, determine standard or extend format.
+    uint8_t auto_reply_bit;                     //!< The auto reply bit of RX frame.
+    uint16_t standard_frame_id;                 //!< Standard frame ID.
+    uint32_t extend_frame_id;                   //!< Extend frame ID.
+    bool rx_msg_buf_enable;                     //!< Enable oor disable rx mst buffer.
+} CANRxFrame_TypeDef;
+
+typedef struct
+{
+    uint8_t rtr_mask;                   //!< The mask of rtr.
+    uint8_t ide_mask;                   //!< The mask of ide.
+    uint8_t id_mask;                    //!< The mask of id.
+    uint8_t esi_bit;                    //!< The mask of esi.
+    uint8_t auto_reply_bit;             //!< The auto reply bit.
+    uint8_t rxtx_bit;                   //!< The rxtx bit.
+    uint8_t rx_lost_bit;                //!< The rx lost bit.
+    uint8_t data_length;                //!< The data length.
+    uint8_t rx_dma_en;                  //!< The dma enable bit.
+    CANRtrSel_TypeDef rtr_bit;          //!< The rtr bit \ref CANRtrSel_TypeDef.
+    CANIdeSel_TypeDef ide_bit;          //!< The ide bit \ref CANIdeSel_TypeDef.
+    uint16_t rx_timestamp;              //!< The time stamp.
+    uint16_t standard_frame_id;         //!< Standard frame ID.
+    uint32_t extend_frame_id;           //!< Extend frame ID.
+} CANMsgBufInfo_TypeDef;
+
+typedef struct
+{
+    uint8_t fifo_msg_lvl;               //!< Indicates the number of message in fifo.
+    uint8_t fifo_msg_overflow;          //!< Indicates whether the fifo is overflow.
+    uint8_t fifo_msg_empty;             //!< Indicates whether the fifo is empty.
+    uint8_t fifo_msg_full;              //!< Indicates whether the fifo is full.
+} CANFifoStatus_TypeDef;
+
+typedef struct
+{
+    CAN_0x340_TYPE_TypeDef can_ram_arb;         //!< ARB
+    CAN_0x348_TYPE_TypeDef can_ram_cs;          //!< CS
+    uint8_t rx_dma_data[CAN_STAND_DATA_MAX_LEN];
+} CANRxDMAData_TypeDef;
+
+/** End of CAN_Exported_Types
+  * \}
+  */
+
+/*============================================================================*
+ *                         Functions
+ *============================================================================*/
+/** \defgroup CAN_Exported_Functions CAN Exported Functions
+  * \brief
+  * \{
+  */
+
+/**
+ * \brief   Deinitializes the CAN peripheral registers to their default values.
+ * \param[in] CANx: selected CAN peripheral.
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void can_driver_init(void)
+ * {
+ *     CAN_DeInit(CAN0);
+ * }
+ * \endcode
+ */
+void CAN_DeInit(CAN_TypeDef *CANx);
+/**
+ * \brief   Initializes the CAN peripheral according to the specified
+ *          parameters in the CAN_InitStruct
+ * \param[in] CANx: selected CAN peripheral.
+ * \param[in] CAN_InitStruct: Pointer to a CAN_InitTypeDef structure that
+ *            contains the configuration information for the specified CAN peripheral
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void can_driver_init(void)
+ * {
+ *     RCC_ClockCmd(CAN0_CLOCK, ENABLE);
+ *
+ *     CAN_InitTypeDef init_struct;
+ *
+ *     CAN_StructInit(&init_struct);
+ *     init_struct.CAN_AutoReTxEn = DISABLE;
+ *     init_struct.CAN_BitTiming.can_brp = 7;
+ *     init_struct.CAN_BitTiming.can_sjw = 3;
+ *     init_struct.CAN_BitTiming.can_tseg1 = 4;
+ *     init_struct.CAN_BitTiming.can_tseg2 = 3;
+ *
+ *     CAN_Init(CAN0, &init_struct);
+ *     CAN_Cmd(CAN0, ENABLE);
+ * }
+ * \endcode
+ */
+void CAN_Init(CAN_TypeDef *CANx, CAN_InitTypeDef *CAN_InitStruct);
+/**
+ * \brief   Fills each CAN_InitStruct member with its default value.
+ * \param[in] CAN_InitStruct: Pointer to an CAN_InitTypeDef structure which will be initialized.
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void can_driver_init(void)
+ * {
+ *     RCC_ClockCmd(CAN_CLOCK, ENABLE);
+ *
+ *     CAN_InitTypeDef init_struct;
+ *
+ *     CAN_StructInit(&init_struct);
+ *     init_struct.CAN_AutoReTxEn = DISABLE;
+ *     init_struct.CAN_BitTiming.can_brp = 7;
+ *     init_struct.CAN_BitTiming.can_sjw = 3;
+ *     init_struct.CAN_BitTiming.can_tseg1 = 4;
+ *     init_struct.CAN_BitTiming.can_tseg2 = 3;
+ *
+ *     CAN_Init(CAN0, &init_struct);
+ *     CAN_Cmd(CAN0, ENABLE);
+ * }
+ * \endcode
+ */
+void CAN_StructInit(CAN_InitTypeDef *CAN_InitStruct);
+/**
+ * \brief   Enable or disable the selected CAN mode.
+ * \param[in] CANx: selected CAN peripheral.
+ * \param[in] NewState: New state of the operation mode.
+ *      This parameter can be: ENABLE or DISABLE.
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void can_driver_init(void)
+ * {
+ *     RCC_ClockCmd(CAN0_CLOCK, ENABLE);
+ *
+ *     CAN_InitTypeDef init_struct;
+ *
+ *     CAN_StructInit(&init_struct);
+ *     init_struct.CAN_AutoReTxEn = DISABLE;
+ *     init_struct.CAN_BitTiming.can_brp = 7;
+ *     init_struct.CAN_BitTiming.can_sjw = 3;
+ *     init_struct.CAN_BitTiming.can_tseg1 = 4;
+ *     init_struct.CAN_BitTiming.can_tseg2 = 3;
+ *
+ *     CAN_Init(CAN0, &init_struct);
+ *     CAN_Cmd(CAN0, ENABLE);
+ * }
+ * \endcode
+ */
+void CAN_Cmd(CAN_TypeDef *CANx, FunctionalState NewState);
+/**
+ * \brief   Enable or disable the specified CAN interrupt source.
+ * \param[in] CANx: selected CAN peripheral.
+ * \param[in] CAN_INT: Specifies the CAN interrupt source to be enable or disable.
+ *      This parameter can be the following values:
+ *      \arg CAN_RAM_MOVE_DONE_INT: This bit is set to 1 when data move from register to CAN IP internal RAM finished.
+ *      \arg CAN_BUS_OFF_INT: This bit is set to 1 when the state of bus is off.
+ *      \arg CAN_WAKE_UP_INT: This bit is set to 1 when CAN awakened from low power mode.
+ *      \arg CAN_ERROR_INT: This bit is set to 1 when there is an error during transmission.
+ *      \arg CAN_RX_INT: This bit is set to 1 when data is received.
+ *      \arg CAN_TX_INT: This bit is set to 1 when sending is completed.
+ * \param[in]  NewState: New state of the specified CAN interrupt.
+ *      This parameter can be: ENABLE or DISABLE.
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void can_driver_init(void)
+ * {
+ *     CAN_INTConfig(CAN0, (CAN_RAM_MOVE_DONE_INT | CAN_BUS_OFF_INT | CAN_WAKE_UP_INT |
+ *                      CAN_ERROR_INT | CAN_RX_INT | CAN_TX_INT), ENABLE);
+ * }
+ * \endcode
+ */
+void CAN_INTConfig(CAN_TypeDef *CANx, uint32_t CAN_INT, FunctionalState newState);
+#if (CAN_SUPPORT_INT_MSK_STS == 1)
+/**
+ * \brief   Mask or unmask the specified CAN interrupt source.
+ * \param[in] CANx: selected CAN peripheral.
+ * \param[in] CAN_INT: Specifies the CAN interrupt source to be enable or disable.
+ *      This parameter can be the following values:
+ *      \arg CAN_RAM_MOVE_DONE_INT: This bit is set to 1 when data move from register to CAN IP internal RAM finished.
+ *      \arg CAN_BUS_OFF_INT: This bit is set to 1 when the state of bus is off.
+ *      \arg CAN_WAKE_UP_INT: This bit is set to 1 when CAN awakened from low power mode.
+ *      \arg CAN_ERROR_INT: This bit is set to 1 when there is an error during transmission.
+ *      \arg CAN_RX_INT: This bit is set to 1 when data is received.
+ *      \arg CAN_TX_INT: This bit is set to 1 when sending is completed.
+ * \param[in]  NewState: New state of the specified CAN interrupt.
+ *      This parameter can be: ENABLE or DISABLE.
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void can_driver_init(void)
+ * {
+ *     CAN_MaskINTConfig(CAN0, (CAN_RAM_MOVE_DONE_INT | CAN_BUS_OFF_INT | CAN_WAKE_UP_INT |
+ *                      CAN_ERROR_INT | CAN_RX_INT | CAN_TX_INT), ENABLE);
+ * }
+ * \endcode
+ */
+
+void CAN_MaskINTConfig(CAN_TypeDef *CANx, uint32_t CAN_INT_FLAG, FunctionalState NewState);
+#endif
+/**
+ * \brief   Get the specified CAN interrupt raw status.
+ * \param[in] CANx: selected CAN peripheral.
+ * \param[in] CAN_INT: the specified CAN interrupt.
+ *     This parameter can be one of the following values:
+ *     \arg CAN_RAM_MOVE_DONE_INT_FLAG: This bit is set to 1 when data move from register to CAN IP internal RAM finished.
+ *     \arg CAN_BUS_OFF_INT_FLAG: This bit is set to 1 when the state of bus is off.
+ *     \arg CAN_WAKE_UP_INT_FLAG: This bit is set to 1 when CAN awakened from low power mode.
+ *     \arg CAN_ERROR_INT_FLAG: This bit is set to 1 when there is an error during transmission.
+ *     \arg CAN_RX_INT_FLAG: This bit is set to 1 when data is received.
+ *     \arg CAN_TX_INT_FLAG: This bit is set to 1 when sending is completed.
+ * \return The new state of CAN_INT (SET or RESET).
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void CAN_Handler(void)
+ * {
+ *     if (SET == CAN_GetINTRawStatus(CAN0, CAN_RAM_MOVE_DONE_INT_FLAG))
+ *  {
+ *      DBG_DIRECT("[CAN] CAN_Handler CAN_RAM_MOVE_DONE_INT_FLAG");
+ *      CAN_ClearINTPendingBit(CAN0, CAN_RAM_MOVE_DONE_INT_FLAG);
+ *  }
+ * }
+ * \endcode
+ */
+ITStatus CAN_GetINTRawStatus(CAN_TypeDef *CANx, uint32_t CAN_INT_FLAG);
+/**
+ * \brief   Get the specified CAN interrupt status.
+ * \param[in] CANx: selected CAN peripheral.
+ * \param[in] CAN_INT: the specified CAN interrupt.
+ *     This parameter can be one of the following values:
+ *     \arg CAN_RAM_MOVE_DONE_INT_FLAG: This bit is set to 1 when data move from register to CAN IP internal RAM finished.
+ *     \arg CAN_BUS_OFF_INT_FLAG: This bit is set to 1 when the state of bus is off.
+ *     \arg CAN_WAKE_UP_INT_FLAG: This bit is set to 1 when CAN awakened from low power mode.
+ *     \arg CAN_ERROR_INT_FLAG: This bit is set to 1 when there is an error during transmission.
+ *     \arg CAN_RX_INT_FLAG: This bit is set to 1 when data is received.
+ *     \arg CAN_TX_INT_FLAG: This bit is set to 1 when sending is completed.
+ * \return The new state of CAN_INT (SET or RESET).
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void CAN_Handler(void)
+ * {
+ *     if (SET == CAN_GetINTStatus(CAN0, CAN_RAM_MOVE_DONE_INT_FLAG))
+ *  {
+ *      DBG_DIRECT("[CAN] CAN_Handler CAN_RAM_MOVE_DONE_INT_FLAG");
+ *      CAN_ClearINTPendingBit(CAN0, CAN_RAM_MOVE_DONE_INT_FLAG);
+ *  }
+ * }
+ * \endcode
+ */
+ITStatus CAN_GetINTStatus(CAN_TypeDef *CANx, uint32_t CAN_INT_FLAG);
+/**
+ * \brief  Clear the CAN interrupt pending bit.
+ * \param[in] CANx: selected CAN peripheral.
+ * \param[in] CAN_INT_FLAG: Specifies the interrupt pending bit to clear.
+ *     This parameter can be any combination of the following values:
+ *     \arg CAN_RAM_MOVE_DONE_INT_FLAG: This bit is set to 1 when data move from register to CAN IP internal RAM finished.
+ *     \arg CAN_BUS_OFF_INT_FLAG: This bit is set to 1 when the state of bus is off.
+ *     \arg CAN_WAKE_UP_INT_FLAG: This bit is set to 1 when CAN awakened from low power mode.
+ *     \arg CAN_ERROR_INT_FLAG: This bit is set to 1 when there is an error during transmission.
+ *     \arg CAN_RX_INT_FLAG: This bit is set to 1 when data is received.
+ *     \arg CAN_TX_INT_FLAG: This bit is set to 1 when sending is completed.
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void CAN_Handler(void)
+ * {
+ *     if (SET == CAN_GetINTStatus(CAN0, CAN_RAM_MOVE_DONE_INT_FLAG))
+ *     {
+ *      DBG_DIRECT("[CAN] CAN_Handler CAN_RAM_MOVE_DONE_INT_FLAG");
+ *      CAN_ClearINTPendingBit(CAN0, CAN_RAM_MOVE_DONE_INT_FLAG);
+ *     }
+ * }
+ * \endcode
+ */
+void CAN_ClearINTPendingBit(CAN_TypeDef *CANx, uint32_t CAN_INT_FLAG);
+/**
+ * \brief  Gets the specified CAN error status.
+ * \param[in] CANx: selected CAN peripheral.
+ * \param[in]  CAN_ERR_STAT: the specified CAN error.
+ *     This parameter can be one of the following values:
+ *     \arg CAN_ERROR_RX: This bit is set to 1 when an error occurred during the receiving process.
+ *     \arg CAN_ERROR_TX: This bit is set to 1 when an error occurred during the sending process.
+ *     \arg CAN_ERROR_ACK: This bit is set to 1 when the latest error is ack error.
+ *     \arg CAN_ERROR_STUFF: This bit is set to 1 when the latest error is stuff error.
+ *     \arg CAN_ERROR_CRC: This bit is set to 1 when the latest error is crc error.
+ *     \arg CAN_ERROR_FORM: This bit is set to 1 when the latest error is form error.
+ *     \arg CAN_ERROR_BIT1: This bit is set to 1 when the latest error is bit error, tx=1 but rx=0.
+ *     \arg CAN_ERROR_BIT0: This bit is set to 1 when the latest error is bit error, tx=0 but rx=1.
+ * \return The new state of CAN_INT (SET or RESET).
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void CAN_Handler(void)
+ * {
+ *     if (SET == CAN_GetErrorStatus(CAN0, CAN_ERROR_TX))
+ *     {
+ *          DBG_DIRECT("[CAN] CAN_ERROR_TX");
+ *          CAN_CLearErrorStatus(CAN0, CAN_ERROR_TX);
+ *     }
+ * }
+ * \endcode
+ */
+FlagStatus CAN_GetErrorStatus(CAN_TypeDef *CANx, uint32_t CAN_ERR_STAT);
+/**
+ * \brief  Clears the specified CAN error status.
+ * \param[in] CANx: selected CAN peripheral.
+ * \param[in]  CAN_ERR_STAT: the specified CAN error.
+ *     This parameter can be one of the following values:
+ *     \arg CAN_ERROR_RX: This bit is set to 1 when an error occurred during the receiving process.
+ *     \arg CAN_ERROR_TX: This bit is set to 1 when an error occurred during the sending process.
+ *     \arg CAN_ERROR_ACK: This bit is set to 1 when the latest error is ack error.
+ *     \arg CAN_ERROR_STUFF: This bit is set to 1 when the latest error is stuff error.
+ *     \arg CAN_ERROR_CRC: This bit is set to 1 when the latest error is crc error.
+ *     \arg CAN_ERROR_FORM: This bit is set to 1 when the latest error is form error.
+ *     \arg CAN_ERROR_BIT1: This bit is set to 1 when the latest error is bit error, tx=1 but rx=0.
+ *     \arg CAN_ERROR_BIT0: This bit is set to 1 when the latest error is bit error, tx=0 but rx=1.
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void CAN_Handler(void)
+ * {
+ *     if (SET == CAN_GetErrorStatus(CAN0, CAN_ERROR_TX))
+ *     {
+ *          DBG_DIRECT("[CAN] CAN_ERROR_TX");
+ *          CAN_CLearErrorStatus(CAN0, CAN_ERROR_TX);
+ *     }
+ * }
+ * \endcode
+ */
+void CAN_CLearErrorStatus(CAN_TypeDef *CANx, uint32_t CAN_ERR_STAT);
+/**
+ * \brief  Sets the CAN message buffer Tx mode.
+ * \param[in] CANx: selected CAN peripheral.
+ * \param[in]  p_tx_frame_params: the CAN frame parameter.
+ * \param[in]  p_frame_data: the specified CAN data.
+ * \param[in]  data_len: the length of CAN data to be sent.
+ * \return the state of set buffer @ref CANError_TypeDef.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * static void can_basic_tx(uint32_t buf_id, CANDataFrameSel_TypeDef frame_type, \
+ *                        uint16_t frame_id, uint32_t ext_id, uint8_t *tx_data, uint8_t data_len)
+ * {
+ *
+ *   CANError_TypeDef tx_error;
+ *
+ *   CANTxFrame_TypeDef tx_frame_type;
+ *
+ *   tx_frame_type.msg_buf_id = buf_id;
+ *   tx_frame_type.frame_type = frame_type;
+ *   tx_frame_type.standard_frame_id = frame_id;
+ *   tx_frame_type.auto_reply_bit = DISABLE;
+ *   tx_frame_type.extend_frame_id = 0;
+ *
+ *   switch (frame_type)
+ *   {
+ *   case CAN_EXT_DATA_FRAME:
+ *   case CAN_EXT_REMOTE_FRAME:
+ *       tx_frame_type.extend_frame_id = ext_id;
+ *   case CAN_STD_DATA_FRAME:
+ *   case CAN_STD_REMOTE_FRAME:
+ *       break;
+ *       break;
+ *   }
+ *
+ *   CAN_MBTxINTConfig(CAN0, tx_frame_type.msg_buf_id, ENABLE);
+ *   tx_error = CAN_SetMsgBufTxMode(CAN0, &tx_frame_type, tx_data, data_len);
+ *
+ *   while (CAN_GetRamState(CAN0) != CAN_RAM_STATE_IDLE);
+ *
+ *   if (tx_error != CAN_NO_ERR)
+ *   {
+ *       IO_PRINT_INFO1("can_basic_tx: tx error %d", tx_error);
+ *   }
+ *  }
+ * \endcode
+ */
+CANError_TypeDef CAN_SetMsgBufTxMode(CAN_TypeDef *CANx, CANTxFrame_TypeDef *p_tx_frame_params,
+                                     const uint8_t *p_frame_data,
+                                     uint8_t data_len);
+/**
+ * \brief  Sets the CAN message buffer Rx mode.
+ * \param[in] CANx: selected CAN peripheral.
+ * \param[in]  p_rx_frame_params: the CAN frame parameter.
+ * \return the state of set buffer @ref CANError_TypeDef.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * static void can_basic_rx(void)
+ * {
+ *     CANError_TypeDef rx_error;
+ *     CANRxFrame_TypeDef rx_frame_type;
+ *     rx_frame_type.msg_buf_id = 7;
+ *
+ *     rx_frame_type.extend_frame_id = 0;
+ *     rx_frame_type.standard_frame_id = 0;
+ *     rx_frame_type.frame_rtr_mask = CAN_RX_FRAME_MASK_RTR;
+ *     rx_frame_type.frame_ide_mask = CAN_RX_FRAME_MASK_IDE;
+ *     rx_frame_type.frame_id_mask = CAN_RX_FRAME_MASK_ID;
+ *     rx_frame_type.rx_dma_en = RESET;
+ *     rx_frame_type.auto_reply_bit = RESET;
+ *     rx_error = CAN_SetMsgBufRxMode(CAN0, &rx_frame_type);
+ *
+ *     CAN_MBRxINTConfig(CAN0, rx_frame_type.msg_buf_id, ENABLE);
+ *
+ *     while (CAN_GetRamState(CAN0) != CAN_RAM_STATE_IDLE);
+ *
+ *     if (rx_error != CAN_NO_ERR)
+ *     {
+ *         IO_PRINT_INFO1("can_basic_rx: rx error %d", rx_error);
+ *     }
+ *
+ *     IO_PRINT_INFO0("can_basic_rx: waiting for rx...");
+ * }
+ * \endcode
+ */
+CANError_TypeDef CAN_SetMsgBufRxMode(CAN_TypeDef *CANx, CANRxFrame_TypeDef *p_rx_frame_params);
+/**
+ * \brief  Gets message buffer information.
+ * \param[in] CANx: selected CAN peripheral.
+ * \param[in]  msg_buf_id: message buffer id.
+ * \param[out] p_mb_info: message buffer information.
+ * \return the state of get buffer information @ref CANError_TypeDef.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * static void can_get_msg_info(void)
+ * {
+ *     uint8_t index = 0
+ *     uint8_t rx_data[64];
+ *     CANMsgBufInfo_TypeDef mb_info;
+ *     CAN_GetMsgBufInfo(CAN0, index, &mb_info);
+ *     CAN_GetRamData(CAN0, mb_info.data_length, rx_data);
+ * }
+ * \endcode
+ */
+CANError_TypeDef CAN_GetMsgBufInfo(CAN_TypeDef *CANx, uint8_t msg_buf_id,
+                                   CANMsgBufInfo_TypeDef *p_mb_info);
+/**
+ * \brief  Gets the RAM data of message buffer.
+ * \param[in] CANx: selected CAN peripheral.
+ * \param[in]  data_len: the length of RAM data.
+ * \param[out] p_data: data buffer to be received.
+ * \return the state of get RAM data @ref CANError_TypeDef.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * static void can_get_ram_data(void)
+ * {
+ *     uint8_t index = 0
+ *     uint8_t rx_data[64];
+ *     CANMsgBufInfo_TypeDef mb_info;
+ *     CAN_GetMsgBufInfo(CAN0, index, &mb_info);
+ *     CAN_GetRamData(CAN0, mb_info.data_length, rx_data);
+ * }
+ * \endcode
+ */
+CANError_TypeDef CAN_GetRamData(CAN_TypeDef *CANx, uint8_t data_len, uint8_t *p_data);
+/**
+ * \brief  Check the type of frame.
+ * \param[in]  rtr_bit.
+ * \param[in]  ide_bit.
+ * \param[in]  edl_bit.
+ * \return the type of frame @ref CANDataFrameSel_TypeDef.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * static void can_get_ram_data(void)
+ * {
+ *     uint8_t index = 0
+ *     uint8_t rx_data[64];
+ *     CANMsgBufInfo_TypeDef mb_info;
+ *     CAN_GetMsgBufInfo(CAN0, index, &mb_info);
+ *     CANDataFrameSel_TypeDef frame_type = CAN_CheckFrameType(mb_info.rtr_bit, mb_info.ide_bit);
+ * }
+ * \endcode
+ */
+CANDataFrameSel_TypeDef CAN_CheckFrameType(uint8_t rtr_bit, uint8_t ide_bit);
+/**
+ * \brief  Config message buffer tx interrupt.
+ * \param[in] CANx: selected CAN peripheral.
+ * \param[in]  message_buffer_index: CAN message buffer index.
+ * \param[in]  newState: the tx state of message buffer.
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * static void can_basic_tx(uint32_t buf_id, CANDataFrameSel_TypeDef frame_type, \
+ *                        uint16_t frame_id, uint32_t ext_id, uint8_t *tx_data, uint8_t data_len)
+ * {
+ *
+ *   CANError_TypeDef tx_error;
+ *
+ *   CANTxFrame_TypeDef tx_frame_type;
+ *
+ *   tx_frame_type.msg_buf_id = buf_id;
+ *   tx_frame_type.frame_type = frame_type;
+ *   tx_frame_type.standard_frame_id = frame_id;
+ *   tx_frame_type.auto_reply_bit = DISABLE;
+ *   tx_frame_type.extend_frame_id = 0;
+ *
+ *   switch (frame_type)
+ *   {
+ *   case CAN_EXT_DATA_FRAME:
+ *   case CAN_EXT_REMOTE_FRAME:
+ *       tx_frame_type.extend_frame_id = ext_id;
+ *   case CAN_STD_DATA_FRAME:
+ *   case CAN_STD_REMOTE_FRAME:
+ *       break;
+ *       break;
+ *   }
+ *
+ *   CAN_MBTxINTConfig(CAN0, tx_frame_type.msg_buf_id, ENABLE);
+ *   tx_error = CAN_SetMsgBufTxMode(CAN0, &tx_frame_type, tx_data, data_len);
+ *
+ *   while (CAN_GetRamState(CAN0) != CAN_RAM_STATE_IDLE);
+ *
+ *   if (tx_error != CAN_NO_ERR)
+ *   {
+ *       IO_PRINT_INFO1("can_basic_tx: tx error %d", tx_error);
+ *   }
+ *  }
+ * \endcode
+ */
+void CAN_MBTxINTConfig(CAN_TypeDef *CANx, uint8_t message_buffer_index, FunctionalState newState);
+/**
+ * \brief  Config message buffer rx interrupt.
+ * \param[in] CANx: selected CAN peripheral.
+ * \param[in]  message_buffer_index: CAN message buffer index.
+ * \param[in]  newState: the rx state of message buffer.
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * static void can_basic_rx(void)
+ * {
+ *     CANError_TypeDef rx_error;
+ *     CANRxFrame_TypeDef rx_frame_type;
+ *     rx_frame_type.msg_buf_id = 7;
+ *
+ *     rx_frame_type.extend_frame_id = 0;
+ *     rx_frame_type.standard_frame_id = 0;
+ *     rx_frame_type.frame_rtr_mask = CAN_RX_FRAME_MASK_RTR;
+ *     rx_frame_type.frame_ide_mask = CAN_RX_FRAME_MASK_IDE;
+ *     rx_frame_type.frame_id_mask = CAN_RX_FRAME_MASK_ID;
+ *     rx_frame_type.rx_dma_en = RESET;
+ *     rx_frame_type.auto_reply_bit = RESET;
+ *     rx_error = CAN_SetMsgBufRxMode(CAN0, &rx_frame_type);
+ *
+ *     CAN_MBRxINTConfig(CAN0, rx_frame_type.msg_buf_id, ENABLE);
+ *
+ *     while (CAN_GetRamState(CAN0) != CAN_RAM_STATE_IDLE);
+ *
+ *     if (rx_error != CAN_NO_ERR)
+ *     {
+ *         IO_PRINT_INFO1("can_basic_rx: rx error %d", rx_error);
+ *     }
+ *
+ *     IO_PRINT_INFO0("can_basic_rx: waiting for rx...");
+ * }
+ * \endcode
+ */
+void CAN_MBRxINTConfig(CAN_TypeDef *CANx, uint8_t message_buffer_index, FunctionalState newState);
+/**
+ * \brief  Gets CAN FIFO status.
+ * \param[in] CANx: selected CAN peripheral.
+ * \param[out]  CAN_FifoStatus: the status of CAN FIFO.
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * static void can_get_fifo_status(void)
+ * {
+ *     CANFifoStatus_TypeDef fifo_status;
+ *     CAN_GetFifoStatus(CAN0, &fifo_status);
+ * }
+ * \endcode
+ */
+void CAN_GetFifoStatus(CAN_TypeDef *CANx, CANFifoStatus_TypeDef *CAN_FifoStatus);
+/**
+ * \brief  Sets tx message trigger by timestamp timer.
+ * \param[in] CANx: selected CAN peripheral.
+ * \param[in]  newState: the state of tx trigger.
+ * \param[in]  trigger_timestamp_begin: end of trigger time.
+ * \param[in]  close_offset: start of trigger time.
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * static void can_tx_trigger(void)
+ * {
+ *     uint16_t begin_ts = CAN_GetTimeStampCount(CAN0);
+ *     begin_ts += 1000;
+ *     CAN_TxTriggerConfig(CAN0, ENABLE, begin_ts, 100);
+ * }
+ * \endcode
+ */
+void CAN_TxTriggerConfig(CAN_TypeDef *CANx, FunctionalState newState,
+                         uint16_t trigger_timestamp_begin,
+                         uint16_t close_offset);
+/**
+ * \brief  Get can bus state.
+ * \param[in] CANx: selected CAN peripheral.
+ * \return The state of bus(CAN_BUS_STATE_ON or CAN_BUS_STATE_OFF).
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * static void can_get_bus_state(void)
+ * {
+ *     while (CAN_GetBusState(CAN0) != CAN_BUS_STATE_ON);
+ * }
+ * \endcode
+ */
+uint32_t CAN_GetBusState(CAN_TypeDef *CANx);
+/**
+ * \brief  Get message buffer ram state.
+ * \param[in] CANx: selected CAN peripheral.
+ * \return The state of message buffer ram(CAN_RAM_STATE_EXCHANGING or CAN_RAM_STATE_IDLE).
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * static void can_get_ram_state(void)
+ * {
+ *     while (CAN_GetRamState(CAN0) != CAN_RAM_STATE_IDLE);
+ * }
+ * \endcode
+ */
+uint32_t CAN_GetRamState(CAN_TypeDef *CANx);
+/**
+ * \brief  Get message buffer tx done flag.
+ * \param[in] CANx: selected CAN peripheral.
+ * \param[in]  message_buffer_index: CAN message buffer index.
+ * \return The flag of message buffer tx done.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * static void can_get_tx_done_flag(void)
+ * {
+ *     for (uint8_t index = 0; index < CAN_MESSAGE_BUFFER_MAX_CNT; index++)
+ *     {
+ *          if (SET == CAN_GetMBnTxDoneFlag(CAN0, index))
+ *          {
+ *              IO_PRINT_INFO1("can_trx_handler: MB_%d tx done", index);
+ *              CAN_ClearMBnTxDoneFlag(CAN0, index);
+ *          }
+ *      }
+ * }
+ * \endcode
+ */
+FlagStatus CAN_GetMBnTxDoneFlag(CAN_TypeDef *CANx, uint8_t message_buffer_index);
+/**
+ * \brief  Clear message buffer tx done flag.
+ * \param[in] CANx: selected CAN peripheral.
+ * \param[in]  message_buffer_index: CAN message buffer index.
+ * \return none.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * static void can_get_tx_done_flag(void)
+ * {
+ *     for (uint8_t index = 0; index < CAN_MESSAGE_BUFFER_MAX_CNT; index++)
+ *     {
+ *          if (SET == CAN_GetMBnTxDoneFlag(CAN0, index))
+ *          {
+ *              IO_PRINT_INFO1("can_trx_handler: MB_%d tx done", index);
+ *              CAN_ClearMBnTxDoneFlag(CAN0, index);
+ *          }
+ *      }
+ * }
+ * \endcode
+ */
+void CAN_ClearMBnTxDoneFlag(CAN_TypeDef *CANx, uint8_t message_buffer_index);
+/**
+ * \brief  Get message buffer tx error flag.
+ * \param[in] CANx: selected CAN peripheral.
+ * \param[in]  message_buffer_index: CAN message buffer index.
+ * \return The flag of message buffer tx error.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * static void can_get_tx_error_flag(void)
+ * {
+ *     for (uint8_t index = 0; index < CAN_MESSAGE_BUFFER_MAX_CNT; index++)
+ *     {
+ *          if (SET == CAN_GetMBnTxErrorFlag(CAN0, index))
+ *          {
+ *              IO_PRINT_INFO1("can_trx_handler: CAN ERROR TX MB_%d", index);
+ *              CAN_ClearMBnTxErrorFlag(CAN0, index);
+ *          }
+ *      }
+ * }
+ * \endcode
+ */
+FlagStatus CAN_GetMBnTxErrorFlag(CAN_TypeDef *CANx, uint8_t message_buffer_index);
+/**
+ * \brief  Clear message buffer tx error flag.
+ * \param[in] CANx: selected CAN peripheral.
+ * \param[in]  message_buffer_index: CAN message buffer index.
+ * \return none.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * static void can_get_tx_error_flag(void)
+ * {
+ *     for (uint8_t index = 0; index < CAN_MESSAGE_BUFFER_MAX_CNT; index++)
+ *     {
+ *          if (SET == CAN_GetMBnTxErrorFlag(CAN0, index))
+ *          {
+ *              IO_PRINT_INFO1("can_trx_handler: CAN ERROR TX MB_%d", index);
+ *              CAN_ClearMBnTxErrorFlag(CAN0, index);
+ *          }
+ *      }
+ * }
+ * \endcode
+ */
+void CAN_ClearMBnTxErrorFlag(CAN_TypeDef *CANx, uint8_t message_buffer_index);
+/**
+ * \brief  Get message buffer tx finish flag, it indicates the tx message in the message buffer finish sending.
+ * \param[in] CANx: selected CAN peripheral.
+ * \param[in]  message_buffer_index: CAN message buffer index.
+ * \return The flag of message buffer tx finish.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * static void can_get_tx_finish_flag(void)
+ * {
+ *     for (uint8_t index = 0; index < CAN_MESSAGE_BUFFER_MAX_CNT; index++)
+ *     {
+ *          if (SET == CAN_GetMBnStatusTxFinishFlag(CAN0, index))
+ *          {
+ *              IO_PRINT_INFO1("can_get_tx_finish_flag: TX finish MB_%d", index);
+ *          }
+ *      }
+ * }
+ * \endcode
+ */
+FlagStatus CAN_GetMBnStatusTxFinishFlag(CAN_TypeDef *CANx, uint8_t message_buffer_index);
+/**
+ * \brief  Get message buffer tx request flag, it indicates the tx message in buffer is pending for transmit.
+ * \param[in] CANx: selected CAN peripheral.
+ * \param[in]  message_buffer_index: CAN message buffer index.
+ * \return The flag of message buffer tx request.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * static void can_get_tx_req_flag(void)
+ * {
+ *     for (uint8_t index = 0; index < CAN_MESSAGE_BUFFER_MAX_CNT; index++)
+ *     {
+ *          if (SET == CAN_GetMBnStatusTxReqFlag(CAN0, index))
+ *          {
+ *              IO_PRINT_INFO1("can_get_tx_req_flag: TX pending MB_%d", index);
+ *          }
+ *      }
+ * }
+ * \endcode
+ */
+FlagStatus CAN_GetMBnStatusTxReqFlag(CAN_TypeDef *CANx, uint8_t message_buffer_index);
+/**
+ * \brief  Get message buffer rx done flag.
+ * \param[in] CANx: selected CAN peripheral.
+ * \param[in]  message_buffer_index: CAN message buffer index.
+ * \return The flag of message buffer rx done.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * static void can_get_rx_done_flag(void)
+ * {
+ *     for (uint8_t index = 0; index < CAN_MESSAGE_BUFFER_MAX_CNT; index++)
+ *     {
+ *          if (SET == CAN_GetMBnRxDoneFlag(CAN0, index))
+ *          {
+ *              IO_PRINT_INFO1("can_trx_handler: MB_%d rx done", index);
+ *              CAN_ClearMBnRxDoneFlag(CAN0, index);
+ *          }
+ *      }
+ * }
+ * \endcode
+ */
+FlagStatus CAN_GetMBnRxDoneFlag(CAN_TypeDef *CANx, uint8_t message_buffer_index);
+/**
+ * \brief  Clear message buffer rx done flag.
+ * \param[in] CANx: selected CAN peripheral.
+ * \param[in]  message_buffer_index: CAN message buffer index.
+ * \return none.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * static void can_clear_rx_done_flag(void)
+ * {
+ *     for (uint8_t index = 0; index < CAN_MESSAGE_BUFFER_MAX_CNT; index++)
+ *     {
+ *          if (SET == CAN_GetMBnRxDoneFlag(CAN0, index))
+ *          {
+ *              IO_PRINT_INFO1("can_trx_handler: MB_%d rx done", index);
+ *              CAN_ClearMBnRxDoneFlag(CAN0, index);
+ *          }
+ *      }
+ * }
+ * \endcode
+ */
+void CAN_ClearMBnRxDoneFlag(CAN_TypeDef *CANx, uint8_t message_buffer_index);
+/**
+ * \brief  Get message buffer rx valid flag, it indicates new message has been received in the message buffer.
+ * \param[in] CANx: selected CAN peripheral.
+ * \param[in]  message_buffer_index: CAN message buffer index.
+ * \return The flag of message buffer rx valid.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * static void can_get_rx_valid_flag(void)
+ * {
+ *     for (uint8_t index = 0; index < CAN_MESSAGE_BUFFER_MAX_CNT; index++)
+ *     {
+ *          if (SET == CAN_GetMBnStatusRxValidFlag(CAN0, index))
+ *          {
+ *              IO_PRINT_INFO1("can_get_rx_valid_flag: MB_%d rx valid", index);
+ *          }
+ *      }
+ * }
+ * \endcode
+ */
+FlagStatus CAN_GetMBnStatusRxValidFlag(CAN_TypeDef *CANx, uint8_t message_buffer_index);
+/**
+ * \brief  Get message buffer rx ready flag, it indicates the message buffer is ready for receiving a new message.
+ * \param[in] CANx: selected CAN peripheral.
+ * \param[in]  message_buffer_index: CAN message buffer index.
+ * \return The flag of message buffer rx ready.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * static void can_get_rx_ready_flag(void)
+ * {
+ *     for (uint8_t index = 0; index < CAN_MESSAGE_BUFFER_MAX_CNT; index++)
+ *     {
+ *          if (SET == CAN_GetMBnStatusRxReadyFlag(CAN0, index))
+ *          {
+ *              IO_PRINT_INFO1("can_get_rx_ready_flag: MB_%d rx ready", index);
+ *          }
+ *      }
+ * }
+ * \endcode
+ */
+FlagStatus CAN_GetMBnStatusRxReadyFlag(CAN_TypeDef *CANx, uint8_t message_buffer_index);
+/**
+ * \brief  Enable or disable can time stamp.
+ * \param[in] CANx: selected CAN peripheral.
+ * \param[in]  newState: New state of the time stamp.
+ * \return none.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * static void can_enable_timestamp(void)
+ * {
+ *     CAN_TimeStampConfig(CAN0, ENABLE);
+ * }
+ * \endcode
+ */
+void CAN_TimeStampConfig(CAN_TypeDef *CANx, FunctionalState newState);
+/**
+ * \brief  Get time stamp count.
+ * \param[in] CANx: selected CAN peripheral.
+ * \return Time stamp count.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * static void can_get_timestamp(void)
+ * {
+ *     uint16_t begin_ts = CAN_GetTimeStampCount(CAN0);
+ * }
+ * \endcode
+ */
+uint16_t CAN_GetTimeStampCount(CAN_TypeDef *CANx);
+/**
+ * \brief  Get rx dma block size(word).
+ * \param[in] CANx: selected CAN peripheral.
+ * \return Rx dma block size.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * static void can_get_dma_msize(void)
+ * {
+ *     uint32_t dma_buffer_size = CAN_GetRxDMAMsize(CAN0);
+ * }
+ * \endcode
+ */
+uint32_t CAN_GetRxDMAMsize(CAN_TypeDef *CANx);
+/**
+ * \brief  Get message buffer rx dma enable flag.
+ * \param[in] CANx: selected CAN peripheral.
+ * \param[in]  message_buffer_index: CAN message buffer index.
+ * \return The flag of message buffer rx dma enable.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * static void can_get_rx_dma_enable_flag(void)
+ * {
+ *     FlagStatus dma_en_flag = CAN_GetMBnRxDMAEnFlag(CAN0, index);
+ * }
+ * \endcode
+ */
+FlagStatus CAN_GetMBnRxDMAEnFlag(CAN_TypeDef *CANx, uint8_t message_buffer_index);
+/**
+ * \brief  Set message buffer rx dma enable.
+ * \param[in] CANx: selected CAN peripheral.
+ * \param[in]  message_buffer_index: CAN message buffer index.
+ * \param[in]  newState: New state of the message buffer rx dma enable.
+ * \return none.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * static void can_set_rx_dma_enable(void)
+ * {
+ *     CAN_SetMBnRxDMAEnFlag(CAN0, RX_DMA_BUF_ID, ENABLE);
+ * }
+ * \endcode
+ */
+void CAN_SetMBnRxDMAEnFlag(CAN_TypeDef *CANx, uint8_t message_buffer_index,
+                           FunctionalState newState);
+
+/**
+ * \brief  Config CAN clock source div.
+ * \param[in] CANx: selected CAN peripheral.
+ * \param[in]  div: CAN clock div @ref CANClockDiv_TypeDef.
+ * \return none.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * static void can_config_clock(void)
+ * {
+ *     CAN_SetClockDiv(CAN0, CAN_CLK_DIV_1);
+ * }
+ * \endcode
+ */
+void CAN_SetClockDiv(CAN_TypeDef *CANx, CANClockDiv_TypeDef div);
+
+/**
+ * \brief  Get CAN clock source.
+ * \param[out]  ClockSrc: CAN clock src.
+ * \param[out]  ClockDiv: CAN clock div.
+ * \return The status of get clock.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * static void can_get_clock(void)
+ * {
+ *     CANClockSrc_TypeDef clk_src;
+ *     CANClockDiv_TypeDef clk_div;
+ *     CAN_GetClock(CAN0, &clk_src, &clk_div);
+ * }
+ * \endcode
+ */
+bool CAN_GetClock(CAN_TypeDef *CANx, CANClockSrc_TypeDef *ClockSrc, CANClockDiv_TypeDef *ClockDiv);
+
+/**
+ * \brief  Set test mode.
+ * \param[in] CANx: selected CAN peripheral.
+ * \param[in] CAN_TestModeSel: Test mode to set @ref CANTestModeSel_TypeDef.
+ * \return none.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * static void can_set_test_mode(void)
+ * {
+ *     CAN_SetTestMode(CAN0, CAN_TEST_MODE_NONE);
+ * }
+ * \endcode
+ */
+void CAN_SetTestMode(CAN_TypeDef *CANx, uint8_t CAN_TestModeSel);
+
+/**
+ * \brief  Enable or disable CAN auto-re-tx function.
+ * \param[in] CANx: selected CAN peripheral.
+ * \param[in] newState: the state of CAN auto-re-tx function.
+ * \return none.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * static void can_enable_auto_retx(void)
+ * {
+ *     CAN_AutoReTxCmd(CAN0, ENABLE);
+ * }
+ * \endcode
+ */
+void CAN_AutoReTxCmd(CAN_TypeDef *CANx, FunctionalState NewState);
+
+/**
+ * \brief  Set can bit timing.
+ * \param[in] CANx: selected CAN peripheral.
+ * \param[in] CAN_BitTiming:  Pointer to a CAN_0x0C_TYPE_TypeDef structure that
+ *            contains the bit timing information for the specified CAN peripheral.
+ * \return none.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * static void can_set_timing(void)
+ * {
+ *     CAN_0x0C_TYPE_TypeDef CAN_BitTiming;
+ *     CAN_BitTiming.can_brp = 7;
+ *     CAN_BitTiming.can_sjw = 3;
+ *     CAN_BitTiming.can_tseg1 = 4;
+ *     CAN_BitTiming.can_tseg2 = 3;
+ *     CAN_SetTiming(CAN0, &CAN_BitTiming);
+ * }
+ * \endcode
+ */
+void CAN_SetTiming(CAN_TypeDef *CANx, CAN_0x0C_TYPE_TypeDef *CAN_BitTiming);
+
+/**
+ * \brief  Get error passive status.
+ * \param[in] CANx: selected CAN peripheral.
+ * \return The flag of error passive status.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * static FlagStatus can_get_error_passive_status(void)
+ * {
+ *     return CAN_GetErrorPassiveStatus(CAN0);
+ * }
+ * \endcode
+ */
+FlagStatus CAN_GetErrorPassiveStatus(CAN_TypeDef *CANx);
+
+/**
+ * \brief  Get error warning status.
+ * \param[in] CANx: selected CAN peripheral.
+ * \return The flag of error warning status.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * static FlagStatus can_get_error_warning_status(void)
+ * {
+ *     return CAN_GetErrorWarningStatus(CAN0);
+ * }
+ * \endcode
+ */
+FlagStatus CAN_GetErrorWarningStatus(CAN_TypeDef *CANx);
+
+/**
+ * \brief  Get tx error counter.
+ * \param[in] CANx: selected CAN peripheral.
+ * \return The counter of tx error.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * static int can_get_tx_error_cnt(void)
+ * {
+ *     return CAN_GetTxErrorCnt(CAN0);
+ * }
+ * \endcode
+ */
+int CAN_GetTxErrorCnt(CAN_TypeDef *CANx);
+
+/**
+ * \brief  Get rx error counter.
+ * \param[in] CANx: selected CAN peripheral.
+ * \return The counter of rx error.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * static int can_get_rx_error_cnt(void)
+ * {
+ *     return CAN_GetRxErrorCnt(CAN0);
+ * }
+ * \endcode
+ */
+int CAN_GetRxErrorCnt(CAN_TypeDef *CANx);
+
+#if (CAN_SUPPORT_SLEEP_MODE == 1)
+/**
+ * \brief  Check CAN sleep state.
+ * \param[in] CANx: selected CAN peripheral.
+ * \return The flag of CAN sleep state.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * static void can_check_sleep_status(void)
+ * {
+ *     FlagStatus status = CAN_CheckSleepStatus(CAN0);
+ * }
+ * \endcode
+ */
+FlagStatus CAN_CheckSleepStatus(CAN_TypeDef *CANx);
+
+/**
+ * \brief  Enable or disable CAN lower power clock.
+ * \param[in] CANx: selected CAN peripheral.
+ * \param[in] newState: Enable or disable CAN lower power clock.
+ * \param[in] div: Low power clock div @ref CANLowPowerClkDIV_TypeDef.
+ * \return none.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * static void can_enable_lower_power_clk(void)
+ * {
+ *     CAN_LowPowerClkCmd(CAN0, ENABLE, CAN_LOW_CLK_DIV_5);
+ *     CAN_SetWakeUpPinFltFunction(CAN0, ENABLE, 10);
+ *     CAN_RequestToSleepMode(CAN0);
+ * }
+ * \endcode
+ */
+void CAN_LowPowerClkCmd(CAN_TypeDef *CANx, FunctionalState newState, CANLowPowerClkDIV_TypeDef div);
+
+/**
+ * \brief  Config wake up pin fit function.
+ * \param[in] CANx: selected CAN peripheral.
+ * \param[in] newState: Enable or disable CAN wake up pin fit function.
+ * \param[in] flt_length: Config wake up pin fit length.
+ *                        minimu value is 1. The unit is low power clock period.
+ * \return none.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * static void can_config_wake_up_pin(void)
+ * {
+ *     CAN_LowPowerClkCmd(CAN0, ENABLE, CAN_LOW_CLK_DIV_5);
+ *     CAN_SetWakeUpPinFltFunction(CAN0, ENABLE, 10);
+ *     CAN_RequestToSleepMode(CAN0);
+ * }
+ * \endcode
+ */
+void CAN_SetWakeUpPinFltFunction(CAN_TypeDef *CANx, FunctionalState newState, uint8_t flt_length);
+/**
+ * \brief  Request CAN to sleep mode.
+ * \param[in] CANx: selected CAN peripheral.
+ * \return none.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * static void can_request_sleep(void)
+ * {
+ *     CAN_LowPowerClkCmd(CAN0, ENABLE, CAN_LOW_CLK_DIV_5);
+ *     CAN_SetWakeUpPinFltFunction(CAN0, ENABLE, 10);
+ *     CAN_RequestToSleepMode(CAN0);
+ * }
+ * \endcode
+ */
+void CAN_RequestToSleepMode(CAN_TypeDef *CANx);
+
+/**
+ * \brief  Manual wake up CAN.
+ * \param[in] CANx: selected CAN peripheral.
+ * \return none.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * static void can_manual_wake_up(void)
+ * {
+ *     CAN_ManualWakeup(CAN0);
+ * }
+ * \endcode
+ */
+void CAN_ManualWakeup(CAN_TypeDef *CANx);
+#endif
+
+#if (CAN_SUPPORT_AUTO_CLOCK == 1)
+
+void CAN_ClockAutoModeCmd(CAN_TypeDef *CANx, FunctionalState Newstate);
+
+#endif
+
+/** End of CAN_Exported_Functions
+  * \}
+  */
+/** End of CAN
+  * \}
+  */
+#ifdef __cplusplus
+}
+#endif
+#endif /* _RTL_CAN_H_ */
+
+
diff --git a/bee/drivers/can/src/CMakeLists.txt b/bee/drivers/can/src/CMakeLists.txt
new file mode 100644
index 00000000..dd5e359a
--- /dev/null
+++ b/bee/drivers/can/src/CMakeLists.txt
@@ -0,0 +1,4 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+add_subdirectory(device)
diff --git a/bee/drivers/can/src/device/CMakeLists.txt b/bee/drivers/can/src/device/CMakeLists.txt
new file mode 100644
index 00000000..d28db895
--- /dev/null
+++ b/bee/drivers/can/src/device/CMakeLists.txt
@@ -0,0 +1,5 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+add_soc_series_subdir(rtl87x2g)
+add_soc_series_subdir(rtl87x2j)
diff --git a/bee/drivers/can/src/device/rtl87x2g/rtl_can.h b/bee/drivers/can/src/device/rtl87x2g/rtl_can.h
new file mode 100644
index 00000000..b6fd0852
--- /dev/null
+++ b/bee/drivers/can/src/device/rtl87x2g/rtl_can.h
@@ -0,0 +1,1670 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *               Define to prevent recursive inclusion
+ *============================================================================*/
+#ifndef _RTL_CAN_H_
+#define _RTL_CAN_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*============================================================================*
+ *                        Header Files
+ *============================================================================*/
+#include "utils/rtl_utils.h"
+#include "rtl_can_def.h"
+
+/*============================================================================*
+ *                         Register Defines
+ *============================================================================*/
+
+
+/** \defgroup CAN         CAN
+  * \brief
+  * \{
+  */
+/*============================================================================*
+ *                         Constants
+ *============================================================================*/
+/** \defgroup CAN_Exported_Constants CAN Exported Constants
+  * \brief
+  * \{
+  */
+
+/**
+ * \defgroup    CAN_Private_Macros CAN Private Macros
+ * \{
+ * \ingroup     CAN_Exported_Constants
+ */
+#define CAN_MESSAGE_BUFFER_MAX_CNT      16              //!< The max count of message buffer.
+#define CAN_MESSAGE_BUFFER_MAX_INDEX    (CAN_MESSAGE_BUFFER_MAX_CNT - 1)     //!< The max index of message buffer.
+#define CAN_MESSAGE_BUFFER_DEFAULT_LEN  20              //!< The default length of message buffer.
+#define CAN_MESSAGE_FIFO_START_ID       12              //!< The start index of message buffer for CAN FIFO.
+#define CAN_DEFAULT_ERR_WARN_TH         96              //!< The threshold of CAN error count.
+#define CAN_STAND_DATA_MAX_LEN          8               //!< The max data length of standard CAN.
+#define CAN_RAM_DATA_MAX_INDEX          1               //!< The max index of RAM data.
+#define CAN_STD_FRAME_ID_POS            18              //!< The pos for CAN standard frame.
+#define CAN_EXT_FRAME_ID_POS            0               //!< The pos for CAN extend frame.
+#define CAN_RAM_ACC_DATA_POS            11              //!< The pos for CAN RAM ACC.
+#define CAN_STAND_FRAME_ID_MAX_VALUE    0x7FFUL         //!< The max id of standard frame.
+#define CAN_EXTEND_FRAME_ID_MAX_VALUE   0x3FFFFUL       //!< The max id of extend frame.
+#define CAN_FRAME_ID_MASK_MAX_VALUE     0x1FFFFFFFUL    //!< The mask of CAN frame ID.
+
+/** End of CAN_Private_Macros
+  * \}
+  */
+
+/**
+ * \defgroup    CAN_DLC_Byte CAN DLC Byte
+ * \{
+ * \ingroup     CAN_Exported_Constants
+ */
+#define CAN_DLC_BYTES_0                         (0x0UL)     //!< Data length = 0 byte.
+#define CAN_DLC_BYTES_1                         (0x1UL)     //!< Data length = 1 byte.
+#define CAN_DLC_BYTES_2                         (0x2UL)     //!< Data length = 2 byte.
+#define CAN_DLC_BYTES_3                         (0x3UL)     //!< Data length = 3 byte.
+#define CAN_DLC_BYTES_4                         (0x4UL)     //!< Data length = 4 byte.
+#define CAN_DLC_BYTES_5                         (0x5UL)     //!< Data length = 5 byte.
+#define CAN_DLC_BYTES_6                         (0x6UL)     //!< Data length = 6 byte.
+#define CAN_DLC_BYTES_7                         (0x7UL)     //!< Data length = 7 byte.
+#define CAN_DLC_BYTES_8                         (0x8UL)     //!< Data length = 8 byte.
+
+/** End of CAN_DLC_Byte
+  * \}
+  */
+
+/**
+ * \defgroup    CAN_Interrupt_Definition CAN Interrupt Definition
+ * \{
+ * \ingroup     CAN_Exported_Constants
+ */
+#define CAN_RAM_MOVE_DONE_INT                       BIT5        //!< Triggered when data move from register to CAN IP internal RAM finished.
+#define CAN_BUS_OFF_INT                             BIT4        //!< Triggered when the bus is off.
+#define CAN_WAKE_UP_INT                             BIT3        //!< Triggered by wake-up interrupt.
+#define CAN_ERROR_INT                               BIT2        //!< Triggered by an error during transmission.
+#define CAN_RX_INT                                  BIT1        //!< Triggered when data is received.
+#define CAN_TX_INT                                  BIT0        //!< Triggered when sending is completed.
+
+#define IS_CAN_INT_CONFIG(CONFIG)     (((CONFIG) == CAN_RAM_MOVE_DONE_INT)  || \
+                                       ((CONFIG) == CAN_BUS_OFF_INT)        || \
+                                       ((CONFIG) == CAN_WAKE_UP_INT)        || \
+                                       ((CONFIG) == CAN_ERROR_INT)          || \
+                                       ((CONFIG) == CAN_RX_INT)             || \
+                                       ((CONFIG) == CAN_TX_INT)) //!< Check if the input parameter is valid.
+
+/** End of CAN_Interrupt_Definition
+  * \}
+  */
+
+/**
+ * \defgroup    CAN_Interrupt_Flag CAN Interrupt Flag
+ * \{
+ * \ingroup     CAN_Exported_Constants
+ */
+#define CAN_RAM_MOVE_DONE_INT_FLAG                  BIT5    //!< Triggered when data move from register to CAN IP internal RAM finished.
+#define CAN_BUS_OFF_INT_FLAG                        BIT4    //!< Triggered when the bus is off.
+#define CAN_WAKE_UP_INT_FLAG                        BIT3    //!< Triggered by wake-up interrupt.
+#define CAN_ERROR_INT_FLAG                          BIT2    //!< Triggered by an error during transmission.
+#define CAN_RX_INT_FLAG                             BIT1    //!< Triggered when data is received.
+#define CAN_TX_INT_FLAG                             BIT0    //!< Triggered when sending is completed.
+
+#define IS_CAN_INT_FLAG(FLAG)         (((CONFIG) == CAN_RAM_MOVE_DONE_INT_FLAG) || \
+                                       ((CONFIG) == CAN_BUS_OFF_INT_FLAG)       || \
+                                       ((CONFIG) == CAN_WAKE_UP_INT_FLAG)       || \
+                                       ((CONFIG) == CAN_ERROR_INT_FLAG)         || \
+                                       ((CONFIG) == CAN_RX_INT_FLAG)            || \
+                                       ((CONFIG) == CAN_TX_INT_FLAG)) //!< Check if the input parameter is valid.
+
+/** End of CAN_Interrupt_Flag
+  * \}
+  */
+
+/**
+ * \defgroup    CAN_Error_Mask CAN Error Mask
+ * \{
+ * \ingroup     CAN_Exported_Constants
+ */
+#define CAN_ERROR_RX                                BIT9    //!< Receiving error occurred.
+#define CAN_ERROR_TX                                BIT8    //!< Sending error occurred.
+#define CAN_ERROR_ACK                               BIT5    //!< Ack error occurred.
+#define CAN_ERROR_STUFF                             BIT4    //!< Stuff error occurred.
+#define CAN_ERROR_CRC                               BIT3    //!< CRC error occurred.
+#define CAN_ERROR_FORM                              BIT2    //!< Form error occurred.
+#define CAN_ERROR_BIT1                              BIT1    //!< BIT1 error occurred.
+#define CAN_ERROR_BIT0                              BIT0    //!< BIT0 error occurred.
+
+#define IS_CAN_ERROR_STATUS(STATUS)   (((STATUS) == CAN_ERROR_RX)   || \
+                                       ((STATUS) == CAN_ERROR_TX)   || \
+                                       ((STATUS) == CAN_ERROR_ACK)  || \
+                                       ((STATUS) == CAN_ERROR_CRC)  || \
+                                       ((STATUS) == CAN_ERROR_FORM) || \
+                                       ((STATUS) == CAN_ERROR_BIT1) || \
+                                       ((STATUS) == CAN_ERROR_BIT0)) //!< Check if the input parameter is valid.
+
+/** End of CAN_Error_Mask
+  * \}
+  */
+
+/** End of CAN_Exported_Constants
+  * \}
+  */
+
+/*============================================================================*
+ *                         Types
+ *============================================================================*/
+/** \defgroup CAN_Exported_Types CAN Exported Types
+  * \brief
+  * \{
+  */
+
+/**
+ * \brief       CAN init structure definition.
+ *
+ * \ingroup     CAN_Exported_Types
+ */
+
+typedef union
+{
+    uint32_t d32;                   //!< The word member in the union.
+    uint8_t d8[4];                  //!< The four byte array members in the union.
+    struct
+    {
+        uint32_t can_tseg1: 8;      //!< The TSEG1 of CAN.
+        uint32_t can_tseg2: 8;      //!< The TSEG2 of CAN.
+        uint32_t can_sjw: 3;        //!< The SJW of CAN.
+        uint32_t RESERVED_0:  5;    //!< Reserved.
+        uint32_t can_brp: 8;        //!< The BRP of CAN.
+    } b;
+} CAN_BIT_TIMING_TYPE_TypeDef;
+
+typedef union
+{
+    uint32_t d32;                   //!< The word member in the union.
+    uint8_t d8[4];                  //!< The four byte array members in the union.
+    struct
+    {
+        const uint32_t can_time_stamp: 16;  //!< The time stamp of CAN.
+        uint32_t can_time_stamp_div: 8;     //!< The div of time stamp.
+        uint32_t RESERVED_0:  7;            //!< Reserved.
+        uint32_t can_time_stamp_en: 1;      //!< The enable bit of time stamp.
+    } b;
+} CAN_TIME_STAMP_TYPE_TypeDef;
+
+typedef union
+{
+    uint32_t d32;                   //!< The word member in the union.
+    uint8_t d8[4];                  //!< The four byte array members in the union.
+    struct
+    {
+        uint32_t can_ram_id: 29;    //!< The ID of CAN.
+        uint32_t can_ram_ide: 1;    //!< The IDE of CAN.
+        uint32_t can_ram_rtr: 1;    //!< The RTR of CAN.
+    } b;
+} CAN_RAM_ARB_TYPE_TypeDef;
+
+typedef union
+{
+    uint32_t d32;                   //!< The word member in the union.
+    uint8_t d8[4];                  //!< The four byte array members in the union.
+    struct
+    {
+        uint32_t can_ram_id_mask: 29;   //!< The mask of CAN ID.
+        uint32_t can_ram_ide_mask: 1;   //!< The mask of CAN IDE.
+        uint32_t can_ram_rtr_mask: 1;   //!< The mask of CAN RTR.
+    } b;
+} CAN_RAM_MASK_TYPE_TypeDef;
+
+typedef union
+{
+    uint32_t d32;                   //!< The word member in the union.
+    uint8_t d8[4];                  //!< The four byte array members in the union.
+    struct
+    {
+        uint32_t can_ram_dlc: 4;        //!< The data length.
+uint32_t can_ram_lost:
+        1;       //!< Value 1 indicates that data have lost in the read buffer, means more than one frame have beed received since last read.
+        uint32_t can_ram_rxtx: 1;       //!< Can frame RX or TX, 0 is for RX, 1 is for TX.
+        uint32_t can_ram_autoreply: 1;  //!< Set the message buffer with remote frame auto reply function.
+        uint32_t RESERVED_1:  1;        //!< Reserved.
+        uint32_t reset: 1;              //!< Reserved.
+        uint32_t RESERVED_2: 1;         //!< Reserved.
+        uint32_t can_ram_esi: 1;        //!< The ESI of CAN.
+        uint32_t RESERVED_0:  5;        //!< Reserved.
+        uint32_t can_ram_timestamp: 16; //!< The received message time stamp.
+    } b;
+} CAN_RAM_CS_TYPE_TypeDef;
+
+typedef union
+{
+    uint32_t d32;                       //!< The word member in the union.
+    uint8_t d8[4];                      //!< The four byte array members in the union.
+    struct
+    {
+        uint32_t can_ram_acc_num: 8;    //!< Access message buffer number.
+uint32_t can_ram_acc_mask:
+        1;   //!< Access CAN_RAM_MASK field, the field will exchange with RAM spaces.
+uint32_t can_ram_acc_cs:
+        1;     //!< Access CAN_RAM_CS field, the field will exchange with RAM space.
+uint32_t can_ram_acc_arb:
+        1;    //!< Access CAN_RAM_ARB field, the field will exchange with RAM space.
+uint32_t can_ram_acc_data:
+        16;  //!< Access CAN_RAM_DATA field, the field will exchange with RAM space.
+        uint32_t RESERVED_0:  2;        //!< Reserved.
+        uint32_t can_ram_buffer_en: 1;  //!< Enable the can_ram_acc_num specified message buffer for rx/tx.
+uint32_t can_ram_dir:
+        1;        //!< 0 is for read from RAM to CAN_RAM_* registers, 1 is for write from CAN_RAM_* to RAM.
+uint32_t can_ram_start:
+        1;      //!< start to exchange data with RAM, the bit will clear automatically after the data change is finshed.
+    } b;
+} CAN_RAM_CMD_TYPE_TypeDef;
+
+typedef union
+{
+    uint32_t d32;                        //!< The word member in the union.
+    uint8_t d8[4];                       //!< The four byte array members in the union.
+    struct
+    {
+        uint32_t can_ram_data0: 8;       //!< The data0 of CAN.
+        uint32_t can_ram_data1: 8;       //!< The data1 of CAN.
+        uint32_t can_ram_data2: 8;       //!< The data2 of CAN.
+        uint32_t can_ram_data3: 8;       //!< The data3 of CAN.
+    } b;
+} CAN_RAM_DATA_TYPE_TypeDef;
+
+/**
+ * \brief       CAN init structure definition.
+ *
+ * \ingroup     CAN_Exported_Types
+ */
+typedef struct
+{
+    uint8_t CAN_AutoReTxEn;                         /*!< Specify Whether the auto re-transmission function is enable.
+                                                         This parameter can be a value of ENABLE or DISABLE. */
+    uint8_t CAN_RxFifoEn;                           /*!< Specify Whether the RX FIFO function is enable.
+                                                         This parameter can be a value of ENABLE or DISABLE. */
+    uint8_t CAN_RxDmaEn;                            /*!< Specify Whether the RX DMA function is enable.
+                                                         This parameter can be a value of ENABLE or DISABLE. */
+    uint8_t CAN_TestModeSel;                        /*!< Specify the test mode of CAN.
+                                                         This parameter can be a value of @ref CANTestModeSel_TypeDef */
+    uint16_t CAN_ErrorWarnThd;                      /*!< Specify error counter warning threshold.
+                                                         This parameter can be set from 0x1 to 0x1ff. */
+    CAN_BIT_TIMING_TYPE_TypeDef
+    CAN_BitTiming;      /*!< Specify the bit timing of CAN. @ref CAN_BIT_TIMING_TYPE_TypeDef */
+    CAN_TIME_STAMP_TYPE_TypeDef
+    CAN_TimeStamp;      /*!< Specify the timestamp function of CAN. @ref CAN_TIME_STAMP_TYPE_TypeDef */
+} CAN_InitTypeDef;
+
+/**
+ * \brief       The state of CAN.
+ *
+ * \ingroup     CAN_Exported_Types
+ */
+typedef enum
+{
+    CAN_BUS_STATE_OFF,          //!< CAN state on.
+    CAN_BUS_STATE_ON,           //!< CAN state off.
+} CANBusStateSel_TypeDef;
+
+/**
+ * \brief       The state of CAN RAM.
+ *
+ * \ingroup     CAN_Exported_Types
+ */
+typedef enum
+{
+    CAN_RAM_STATE_IDLE,         //!< CAN RAM is idle.
+    CAN_RAM_STATE_EXCHANGING,   //!< CAN RAM is exchanging.
+} CANRamStateSel_TypeDef;
+
+/**
+ * \brief       The test mode of CAN.
+ *
+ * \ingroup     CAN_Exported_Types
+ */
+typedef enum
+{
+    CAN_TEST_MODE_SILENCE,          //!< Silence mode.
+#if CAN_SUPPORT_EXT_LOOPBACK
+    CAN_TEST_MODE_EXT_LOOPBACK,     //!< Internal loopback mode.
+#endif
+    CAN_TEST_MODE_INT_LOOPBACK,     //!< Internal loopback mode.
+    CAN_TEST_MODE_NONE,             //!< No test mode.
+} CANTestModeSel_TypeDef;
+
+/**
+ * \brief       The data type of CAN frame.
+ *
+ * \ingroup     CAN_Exported_Types
+ */
+typedef enum
+{
+    CAN_RTR_DATA_FRAME = 0,         //!< Data frame.
+    CAN_RTR_REMOTE_FRAME = 1,       //!< Remote frame.
+} CANRtrSel_TypeDef;
+
+/**
+ * \brief       The type of CAN ID.
+ *
+ * \ingroup     CAN_Exported_Types
+ */
+typedef enum
+{
+    CAN_IDE_STANDARD_FORMAT = 0,    //!< Standard ID.
+    CAN_IDE_EXTEND_FORMAT = 1,      //!< Extend ID.
+} CANIdeSel_TypeDef;
+
+/**
+ * \brief       The type of CAN frame ID.
+ *
+ * \ingroup     CAN_Exported_Types
+ */
+typedef enum
+{
+    CAN_EDL_STARDARD_FRAME = 0,     //!< Standard frame.
+} CANEdlSel_TypeDef;
+
+/**
+ * \brief       The type of CAN frame.
+ *
+ * \ingroup     CAN_Exported_Types
+ */
+typedef enum
+{
+    CAN_INVALID_DATA_FRAME,      //!< invalide data frame.
+    CAN_STD_DATA_FRAME,          //!< standard data frame.
+    CAN_EXT_DATA_FRAME,          //!< extend data frame.
+    CAN_STD_REMOTE_FRAME,        //!< standard remote frame.
+    CAN_EXT_REMOTE_FRAME,        //!< extend remote frame.
+} CANDataFrameSel_TypeDef;
+
+/**
+ * \brief       The error of CAN.
+ *
+ * \ingroup     CAN_Exported_Types
+ */
+typedef enum
+{
+    CAN_NO_ERR = 0,             //!< no error.
+    CAN_MSG_ID_ERR = 1,         //!< can message id error.
+    CAN_ID_ERR = 2,             //!< can frame id error.
+    CAN_DATA_LEN_ERR = 3,       //!< can frame data length error.
+    CAN_TYPE_ERR = 4,           //!< can frame type error.
+    CAN_RAM_STATE_ERR = 5,      //!< can frame ram status error.
+    CAN_TIMEOUT_ERR = 6,        //!< can timeout error.
+} CANError_TypeDef;
+
+/**
+ * \brief       The members of CAN frame.
+ *
+ * \ingroup     CAN_Exported_Types
+ */
+typedef struct
+{
+    uint8_t msg_buf_id;                 //!< Message buffer ID.
+    uint8_t auto_reply_bit;             //!< The auto reply bit of frame.
+    CANDataFrameSel_TypeDef frame_type; //!< The type of frame.
+    uint16_t standard_frame_id;         //!< The standard frame ID.
+    uint32_t extend_frame_id;           //!< The extend frame ID.
+} CANTxFrame_TypeDef;
+
+/**
+ * \brief       The members of CAN RX frame.
+ *
+ * \ingroup     CAN_Exported_Types
+ */
+typedef struct
+{
+    uint8_t msg_buf_id;            //!< Message buffer ID.
+    uint8_t rx_dma_en;             //!< The DMA enable bit of RX frame.
+    uint8_t frame_rtr_mask;        //!< can frame RTR mask, 1 means don't care, 0 means the bit should match.
+    uint8_t frame_ide_mask;        //!< can frame IDE mask, 1 means don't care, 0 means the bit should match.
+    uint32_t frame_id_mask;        //!< can frame ID mask, 1 means the ID bit in CAN_RAM_ARB don't care, 0 means the bit should match.
+    uint8_t frame_rtr_bit;         //!< can frame RTR bit, determine DATA or REMOTE frame.
+    uint8_t frame_ide_bit;         //!< can frame IDE bit, determine standard or extend format.
+    uint8_t auto_reply_bit;        //!< The auto reply bit of RX frame.
+    uint16_t standard_frame_id;    //!< Standard frame ID.
+    uint32_t extend_frame_id;      //!< Extend frame ID.
+    bool rx_msg_buf_enable;        //!< Message buffer enable.
+} CANRxFrame_TypeDef;
+
+/**
+ * \brief       The members of message buffer.
+ *
+ * \ingroup     CAN_Exported_Types
+ */
+typedef struct
+{
+    uint8_t rtr_mask;                   //!< The mask of rtr.
+    uint8_t ide_mask;                   //!< The mask of ide.
+    uint8_t id_mask;                    //!< The mask of id.
+    uint8_t esi_bit;                    //!< The mask of esi.
+    uint8_t auto_reply_bit;             //!< The auto reply bit.
+    uint8_t rxtx_bit;                   //!< The rxtx bit.
+    uint8_t rx_lost_bit;                //!< The RX lost bit.
+    uint8_t data_length;                //!< The data length.
+    uint8_t rx_dma_en;                  //!< The DMA enable bit.
+    CANRtrSel_TypeDef rtr_bit;          //!< The rtr bit \ref CANRtrSel_TypeDef.
+    CANIdeSel_TypeDef ide_bit;          //!< The ide bit \ref CANIdeSel_TypeDef.
+    uint16_t rx_timestamp;              //!< The time stamp.
+    uint16_t standard_frame_id;         //!< Standard frame ID.
+    uint32_t extend_frame_id;           //!< Extend frame ID.
+} CANMsgBufInfo_TypeDef;
+
+/**
+ * \brief       The status of CAN FIFO.
+ *
+ * \ingroup     CAN_Exported_Types
+ */
+typedef struct
+{
+    uint8_t fifo_msg_lvl;               //!< Indicates the number of message in FIFO.
+    uint8_t fifo_msg_overflow;          //!< Indicates whether the FIFO is overflow.
+    uint8_t fifo_msg_empty;             //!< Indicates whether the FIFO is empty.
+    uint8_t fifo_msg_full;              //!< Indicates whether the FIFO is full.
+} CANFifoStatus_TypeDef;
+
+/**
+ * \brief       The members of RX DMA data.
+ *
+ * \ingroup     CAN_Exported_Types
+ */
+typedef struct
+{
+    CAN_RAM_ARB_TYPE_TypeDef can_ram_arb;           //!< ARB
+    CAN_RAM_CS_TYPE_TypeDef can_ram_cs;             //!< CS
+    uint8_t rx_dma_data[CAN_STAND_DATA_MAX_LEN];    //!< Data
+} CANRxDmaData_TypeDef;
+
+/**
+ * \brief       The members of TX DMA data.
+ *
+ * \ingroup     CAN_Exported_Types
+ */
+typedef struct
+{
+    __IO uint32_t CAN_RAM_DATA[2];      //!< The data of CAN frame.
+
+    union
+    {
+        __IO uint32_t CAN_RAM_ARB;                          //!< The word member in the union.
+        __IO CAN_RAM_ARB_TYPE_TypeDef
+        CAN_RAM_ARB_BITS;     //!< The ARB of CAN. \ref CAN_RAM_ARB_TYPE_TypeDef
+    } u_CAN_RAM_ARB;
+
+    union
+    {
+        __IO uint32_t CAN_RAM_MASK;                         //!< The word member in the union.
+        __IO CAN_RAM_MASK_TYPE_TypeDef
+        CAN_RAM_MASK_BITS;   //!< The mask of CAN. \ref CAN_RAM_MASK_TYPE_TypeDef
+    } u_CAN_RAM_MASK;
+
+    union
+    {
+        __IO uint32_t CAN_RAM_CS;                           //!< The word member in the union.
+        __IO CAN_RAM_CS_TYPE_TypeDef CAN_RAM_CS_BITS;       //!< The CS of CAN. \ref CAN_RAM_CS_TYPE_TypeDef
+    } u_CAN_RAM_CS;
+
+    union
+    {
+        __IO uint32_t CAN_RAM_CMD;                          //!< The word member in the union.
+        __IO CAN_RAM_CMD_TYPE_TypeDef
+        CAN_RAM_CMD_BITS;     //!< The CMD of CAN. \ref CAN_RAM_CMD_TYPE_TypeDef
+    } u_CAN_RAM_CMD;
+} CAN_RAM_TypeDef;
+
+/** End of CAN_Exported_Types
+  * \}
+  */
+
+/*============================================================================*
+ *                         Functions
+ *============================================================================*/
+/** \defgroup CAN_Exported_Functions CAN Exported Functions
+  * \brief
+  * \{
+  */
+
+/**
+ * \brief   Deinitialize the CAN peripheral registers to their default values.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void can_driver_init(void)
+ * {
+ *     CAN_DeInit();
+ * }
+ * \endcode
+ */
+void CAN_DeInit();
+
+/**
+ * \brief   Initialize the CAN peripheral according to the specified
+ *          parameters in the CAN_InitStruct
+ *
+ * \param[in] CAN_InitStruct  Pointer to a CAN_InitTypeDef structure which will be initialized.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void can_driver_init(void)
+ * {
+ *     RCC_PeriphClockCmd(APBPeriph_CAN0, APBPeriph_CAN0_CLOCK, ENABLE);
+ *
+ *     CAN_InitTypeDef init_struct;
+ *
+ *     CAN_StructInit(&init_struct);
+ *     init_struct.CAN_AutoReTxEn = DISABLE;
+ *     init_struct.CAN_BitTiming.can_brp = 7;
+ *     init_struct.CAN_BitTiming.can_sjw = 3;
+ *     init_struct.CAN_BitTiming.can_tseg1 = 4;
+ *     init_struct.CAN_BitTiming.can_tseg2 = 3;
+ *
+ *     CAN_Init(&init_struct);
+ *     CAN_Cmd(ENABLE);
+ * }
+ * \endcode
+ */
+void CAN_Init(CAN_InitTypeDef *CAN_InitStruct);
+
+/**
+ * \brief   Fill each CAN_InitStruct member with its default value.
+ *
+ * \note   The default settings for the CAN_InitStruct member are shown in the following table:
+ *         | CAN_InitStruct member              | Default value                |
+ *         |:----------------------------------:|:----------------------------:|
+ *         | CAN_TriSampleEn                    | DISABLE                      |
+ *         | CAN_AutoReTxEn                     | ENABLE                       |
+ *         | CAN_RxFifoEn                       | DISABLE                      |
+ *         | CAN_RxDmaEn                        | DISABLE                      |
+ *         | CAN_TimeStamp.b.can_time_stamp_en  | DISABLE                      |
+ *         | CAN_TimeStamp.b.can_time_stamp_div | 0                            |
+ *         | CAN_ErrorWarnThd                   | \ref CAN_DEFAULT_ERR_WARN_TH |
+ *         | CAN_BitTiming.b.can_brp            | 7                            |
+ *         | CAN_BitTiming.b.can_sjw            | 3                            |
+ *         | CAN_BitTiming.b.can_tseg2          | 3                            |
+ *         | CAN_BitTiming.b.can_tseg1          | 4                            |
+ *         | CAN_TestModeSel                    | \ref CAN_TEST_MODE_NONE      |
+ *
+ * \param[in] CAN_InitStruct  Pointer to an CAN_InitTypeDef structure which will be initialized.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void can_driver_init(void)
+ * {
+ *     RCC_PeriphClockCmd(APBPeriph_CAN, APBPeriph_CAN_CLOCK, ENABLE);
+ *
+ *     CAN_InitTypeDef init_struct;
+ *
+ *     CAN_StructInit(&init_struct);
+ *     init_struct.CAN_AutoReTxEn = DISABLE;
+ *     init_struct.CAN_BitTiming.can_brp = 7;
+ *     init_struct.CAN_BitTiming.can_sjw = 3;
+ *     init_struct.CAN_BitTiming.can_tseg1 = 4;
+ *     init_struct.CAN_BitTiming.can_tseg2 = 3;
+ *
+ *     CAN_Init(&init_struct);
+ *     CAN_Cmd(ENABLE);
+ * }
+ * \endcode
+ */
+void CAN_StructInit(CAN_InitTypeDef *CAN_InitStruct);
+
+/**
+ * \brief   Enable or disable the selected CAN mode.
+ *
+ * \param[in] NewState  New state of the operation mode.
+ *                      This parameter can be one of the following values:
+ *                      - ENABLE: Enable the CAN.
+ *                      - DISABLE: Disable the CAN.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void can_driver_init(void)
+ * {
+ *     RCC_PeriphClockCmd(APBPeriph_CAN0, APBPeriph_CAN0_CLOCK, ENABLE);
+ *
+ *     CAN_InitTypeDef init_struct;
+ *
+ *     CAN_StructInit(&init_struct);
+ *     init_struct.CAN_AutoReTxEn = DISABLE;
+ *     init_struct.CAN_BitTiming.can_brp = 7;
+ *     init_struct.CAN_BitTiming.can_sjw = 3;
+ *     init_struct.CAN_BitTiming.can_tseg1 = 4;
+ *     init_struct.CAN_BitTiming.can_tseg2 = 3;
+ *
+ *     CAN_Init(&init_struct);
+ *     CAN_Cmd(ENABLE);
+ * }
+ * \endcode
+ */
+void CAN_Cmd(FunctionalState NewState);
+
+/**
+ * \brief   Enable or disable the specified CAN interrupt source.
+ *
+ * \param[in] CAN_INT   Specify the CAN interrupt source to be enable or disable.
+ *                      This parameter can be the following values:
+ *                      \arg CAN_RAM_MOVE_DONE_INT: data move from register to CAN IP internal RAM finished interupt.
+ *                      \arg CAN_BUS_OFF_INT: bus off interrupt.
+ *                      \arg CAN_WAKE_UP_INT: wakeup interrupt.
+ *                      \arg CAN_ERROR_INT: error interrupt.
+ *                      \arg CAN_RX_INT: RX interrupt.
+ *                      \arg CAN_TX_INT: TX interrupt.
+ * \param[in] NewState  New state of the specified CAN interrupt.
+ *                      This parameter can be one of the following values:
+ *                      - ENABLE: Enable the specified CAN interrupt.
+ *                      - DISABLE: Disable the specified CAN interrupt.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void can_driver_init(void)
+ * {
+ *     CAN_INTConfig((CAN_RAM_MOVE_DONE_INT | CAN_BUS_OFF_INT | CAN_WAKE_UP_INT |
+ *                    CAN_ERROR_INT | CAN_RX_INT | CAN_TX_INT), ENABLE);
+ * }
+ * \endcode
+ */
+void CAN_INTConfig(uint32_t CAN_INT, FunctionalState newState);
+
+#if (CAN_SUPPORT_INT_MSK_STS == 1)
+/**
+ * \brief   Mask or unmask the specified CAN interrupt source.
+ *
+ * \param[in] CAN_INT   Specify the CAN interrupt source to be enable or disable.
+ *                      This parameter can be the following values:
+ *                      \arg CAN_RAM_MOVE_DONE_INT: data move from register to CAN IP internal RAM finished interupt.
+ *                      \arg CAN_BUS_OFF_INT: bus off interrupt.
+ *                      \arg CAN_WAKE_UP_INT: wakeup interrupt.
+ *                      \arg CAN_ERROR_INT: error interrupt.
+ *                      \arg CAN_RX_INT: RX interrupt.
+ *                      \arg CAN_TX_INT: TX interrupt.
+ * \param[in] NewState  New state of the specified CAN interrupt.
+ *                      This parameter can be one of the following values:
+ *                      - ENABLE: Mask the specified CAN interrupt.
+ *                      - DISABLE: Unmask the specified CAN interrupt.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void can_driver_init(void)
+ * {
+ *     CAN_MaskINTConfig((CAN_RAM_MOVE_DONE_INT | CAN_BUS_OFF_INT | CAN_WAKE_UP_INT |
+ *                      CAN_ERROR_INT | CAN_RX_INT | CAN_TX_INT), ENABLE);
+ * }
+ * \endcode
+ */
+
+void CAN_MaskINTConfig(uint32_t CAN_INT_FLAG, FunctionalState NewState);
+#endif
+
+/**
+ * \brief   Get the specified CAN interrupt raw status.
+ *
+ * \param[in] CAN_INT  The specified CAN interrupt.
+ *                     This parameter can be one of the following values:
+ *                     \arg CAN_RAM_MOVE_DONE_INT_FLAG: ram move done interrupt flag.
+ *                     \arg CAN_BUS_OFF_INT_FLAG: bus off interrupt flag.
+ *                     \arg CAN_WAKE_UP_INT_FLAG: wakeup interrupt flag.
+ *                     \arg CAN_ERROR_INT_FLAG: error interrupt flag.
+ *                     \arg CAN_RX_INT_FLAG: RX interrupt flag.
+ *                     \arg CAN_TX_INT_FLAG: Clear TX interrupt flag.
+ *
+ * \return  The new state of CAN_INT.
+ *         - SET: The interrupt raw status is set.
+ *         - RESET: The interrupt raw status is unset.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void CAN_Handler(void)
+ * {
+ *     if (SET == CAN_GetINTRawStatus(CAN_RAM_MOVE_DONE_INT_FLAG))
+ *  {
+ *      DBG_DIRECT("[CAN] CAN_Handler CAN_RAM_MOVE_DONE_INT_FLAG");
+ *      CAN_ClearINTPendingBit(CAN_RAM_MOVE_DONE_INT_FLAG);
+ *  }
+ * }
+ * \endcode
+ */
+ITStatus CAN_GetINTRawStatus(uint32_t CAN_INT_FLAG);
+
+/**
+ * \brief   Get the specified CAN interrupt status.
+ *
+ * \param[in] CAN_INT  The specified CAN interrupt.
+ *                     This parameter can be one of the following values:
+ *                     \arg CAN_RAM_MOVE_DONE_INT_FLAG: ram move done interrupt flag.
+ *                     \arg CAN_BUS_OFF_INT_FLAG: bus off interrupt flag.
+ *                     \arg CAN_WAKE_UP_INT_FLAG: wakeup interrupt flag.
+ *                     \arg CAN_ERROR_INT_FLAG: error interrupt flag.
+ *                     \arg CAN_RX_INT_FLAG: RX interrupt flag.
+ *                     \arg CAN_TX_INT_FLAG: Clear TX interrupt flag.
+ *
+ * \return The new state of CAN_INT.
+ *         - SET: The interrupt is set.
+ *         - RESET: The interrupt is unset.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void CAN_Handler(void)
+ * {
+ *     if (SET == CAN_GetINTStatus(CAN_RAM_MOVE_DONE_INT_FLAG))
+ *  {
+ *      DBG_DIRECT("[CAN] CAN_Handler CAN_RAM_MOVE_DONE_INT_FLAG");
+ *      CAN_ClearINTPendingBit(CAN_RAM_MOVE_DONE_INT_FLAG);
+ *  }
+ * }
+ * \endcode
+ */
+ITStatus CAN_GetINTStatus(uint32_t CAN_INT_FLAG);
+
+/**
+ * \brief  Clear the CAN interrupt pending bit.
+ *
+ * \param[in] CAN_INT_FLAG  Specify the interrupt pending bit to clear.
+ *                          This parameter can be any combination of the following values:
+ *                          - CAN_RAM_MOVE_DONE_INT_FLAG: ram move done interrupt flag.
+ *                          - CAN_BUS_OFF_INT_FLAG: bus off interrupt flag.
+ *                          - CAN_WAKE_UP_INT_FLAG: wakeup interrupt flag.
+ *                          - CAN_ERROR_INT_FLAG: error interrupt flag.
+ *                          - CAN_RX_INT_FLAG: RX interrupt flag.
+ *                          - CAN_TX_INT_FLAG: Clear TX interrupt flag.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void CAN_Handler(void)
+ * {
+ *     if (SET == CAN_GetINTStatus(CAN_RAM_MOVE_DONE_INT_FLAG))
+ *     {
+ *      DBG_DIRECT("[CAN] CAN_Handler CAN_RAM_MOVE_DONE_INT_FLAG");
+ *      CAN_ClearINTPendingBit(CAN_RAM_MOVE_DONE_INT_FLAG);
+ *     }
+ * }
+ * \endcode
+ */
+void CAN_ClearINTPendingBit(uint32_t CAN_INT_FLAG);
+
+/**
+ * \brief  Get the specified CAN error status.
+ *
+ * \param[in]  CAN_ERR_STAT  The specified CAN error.
+ *                           This parameter can be one of the following values:
+ *                           \arg CAN_ERROR_RX: can rx error flag
+ *                           \arg CAN_ERROR_TX: can tx error flag
+ *                           \arg CAN_ERROR_ACK: latest error is ack error
+ *                           \arg CAN_ERROR_STUFF: latest error is stuff error
+ *                           \arg CAN_ERROR_CRC: latest error is crc error
+ *                           \arg CAN_ERROR_FORM: latest error is form error
+ *                           \arg CAN_ERROR_BIT1: latest error is bit1 error, tx=1 but rx=0
+ *                           \arg CAN_ERROR_BIT0: latest error is bit0 error, tx=0 but rx=1
+ *
+ * \return The new state of CAN_INT.
+ *         - SET: The error state is set.
+ *         - RESET: The error state is unset.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void CAN_Handler(void)
+ * {
+ *     if (SET == CAN_GetErrorStatus(CAN_ERROR_TX))
+ *     {
+ *          DBG_DIRECT("[CAN] CAN_ERROR_TX");
+ *          CAN_CLearErrorStatus(CAN_ERROR_TX);
+ *     }
+ * }
+ * \endcode
+ */
+FlagStatus CAN_GetErrorStatus(uint32_t CAN_ERR_STAT);
+
+/**
+ * \brief  Clear the specified CAN error status.
+ *
+ * \param[in]  CAN_ERR_STAT  The specified CAN error.
+ *                           This parameter can be one of the following values:
+ *                           - CAN_ERROR_RX: can rx error flag
+ *                           - CAN_ERROR_TX: can tx error flag
+ *                           - CAN_ERROR_ACK: latest error is ack error
+ *                           - CAN_ERROR_STUFF: latest error is stuff error
+ *                           - CAN_ERROR_CRC: latest error is crc error
+ *                           - CAN_ERROR_FORM: latest error is form error
+ *                           - CAN_ERROR_BIT1: latest error is bit1 error, tx=1 but rx=0
+ *                           - CAN_ERROR_BIT0: latest error is bit0 error, tx=0 but rx=1
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void CAN_Handler(void)
+ * {
+ *     if (SET == CAN_GetErrorStatus(CAN_ERROR_TX))
+ *     {
+ *          DBG_DIRECT("[CAN] CAN_ERROR_TX");
+ *          CAN_CLearErrorStatus(CAN_ERROR_TX);
+ *     }
+ * }
+ * \endcode
+ */
+void CAN_CLearErrorStatus(uint32_t CAN_ERR_STAT);
+
+/**
+ * \brief  Set the CAN message buffer TX mode.
+ *
+ * \param[in]  p_tx_frame_params  The CAN frame parameter. \ref CANTxFrame_TypeDef
+ * \param[in]  p_frame_data       The specified CAN data.
+ * \param[in]  data_len           The length of CAN data to be sent. The range is 0 to 8.
+ *
+ * \return The state of set buffer \ref CANError_TypeDef.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * static void can_basic_tx(uint32_t buf_id, CANDataFrameSel_TypeDef frame_type, \
+ *                        uint16_t frame_id, uint32_t ext_id, uint8_t *tx_data, uint8_t data_len)
+ * {
+ *
+ *   CANError_TypeDef tx_error;
+ *
+ *   CANTxFrame_TypeDef tx_frame_type;
+ *
+ *   tx_frame_type.msg_buf_id = buf_id;
+ *   tx_frame_type.frame_type = frame_type;
+ *   tx_frame_type.standard_frame_id = frame_id;
+ *   tx_frame_type.auto_reply_bit = DISABLE;
+ *   tx_frame_type.extend_frame_id = 0;
+ *
+ *   switch (frame_type)
+ *   {
+ *   case CAN_EXT_DATA_FRAME:
+ *   case CAN_EXT_REMOTE_FRAME:
+ *       tx_frame_type.extend_frame_id = ext_id;
+ *   case CAN_STD_DATA_FRAME:
+ *   case CAN_STD_REMOTE_FRAME:
+ *       break;
+ *   }
+ *
+ *   CAN_MBTxINTConfig(tx_frame_type.msg_buf_id, ENABLE);
+ *   tx_error = CAN_SetMsgBufTxMode(&tx_frame_type, tx_data, data_len);
+ *
+ *   while (CAN_GetRamState() != CAN_RAM_STATE_IDLE);
+ *
+ *   if (tx_error != CAN_NO_ERR)
+ *   {
+ *       IO_PRINT_INFO1("can_basic_tx: TX error %d", tx_error);
+ *   }
+ *  }
+ * \endcode
+ */
+CANError_TypeDef CAN_SetMsgBufTxMode(CANTxFrame_TypeDef *p_tx_frame_params,
+                                     const uint8_t *p_frame_data,
+                                     uint8_t data_len);
+
+/**
+ * \brief  Set the CAN message buffer RX mode.
+ *
+ * \param[in]  p_rx_frame_params  The CAN frame parameter. \ref CANRxFrame_TypeDef
+ *
+ * \return The state of set buffer \ref CANError_TypeDef.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * static void can_basic_rx(void)
+ * {
+ *     CANError_TypeDef rx_error;
+ *     CANRxFrame_TypeDef rx_frame_type;
+ *     rx_frame_type.msg_buf_id = 7;
+ *
+ *     rx_frame_type.extend_frame_id = 0;
+ *     rx_frame_type.standard_frame_id = 0;
+ *     rx_frame_type.frame_rtr_mask = SET;
+ *     rx_frame_type.frame_ide_mask = SET;
+ *     rx_frame_type.frame_id_mask = CAN_FRAME_ID_MASK_MAX_VALUE;
+ *     rx_frame_type.rx_dma_en = RESET;
+ *     rx_frame_type.auto_reply_bit = RESET;
+ *     rx_error = CAN_SetMsgBufRxMode(&rx_frame_type);
+ *
+ *     CAN_MBRxINTConfig(rx_frame_type.msg_buf_id, ENABLE);
+ *
+ *     while (CAN_GetRamState() != CAN_RAM_STATE_IDLE);
+ *
+ *     if (rx_error != CAN_NO_ERR)
+ *     {
+ *         IO_PRINT_INFO1("can_basic_rx: RX error %d", rx_error);
+ *     }
+ *
+ *     IO_PRINT_INFO0("can_basic_rx: waiting for RX...");
+ * }
+ * \endcode
+ */
+CANError_TypeDef CAN_SetMsgBufRxMode(CANRxFrame_TypeDef *p_rx_frame_params);
+
+/**
+ * \brief  Get message buffer information.
+ *
+ * \param[in]  msg_buf_id  Message buffer id.
+ * \param[out] p_mb_info   Message buffer information. \ref CANMsgBufInfo_TypeDef
+ *
+ * \return The state of get buffer information \ref CANError_TypeDef.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * static void can_get_msg_info(void)
+ * {
+ *     uint8_t index = 0
+ *     uint8_t rx_data[64];
+ *     CANMsgBufInfo_TypeDef mb_info;
+ *     CAN_GetMsgBufInfo(index, &mb_info);
+ *     CAN_GetRamData(mb_info.data_length, rx_data);
+ * }
+ * \endcode
+ */
+CANError_TypeDef CAN_GetMsgBufInfo(uint8_t msg_buf_id,
+                                   CANMsgBufInfo_TypeDef *p_mb_info);
+
+/**
+ * \brief  Get the RAM data of message buffer.
+ *
+ * \param[in]  data_len  The length of RAM data.
+ * \param[out] p_data    Data buffer to be received.
+ *
+ * \return The state of get RAM data \ref CANError_TypeDef.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * static void can_get_ram_data(void)
+ * {
+ *     uint8_t index = 0
+ *     uint8_t rx_data[8];
+ *     CANMsgBufInfo_TypeDef mb_info;
+ *     CAN_GetMsgBufInfo(index, &mb_info);
+ *     CAN_GetRamData(mb_info.data_length, rx_data);
+ * }
+ * \endcode
+ */
+CANError_TypeDef CAN_GetRamData(uint8_t data_len, uint8_t *p_data);
+
+/**
+ * \brief  Check the type of frame.
+ *
+ * \param[in]  rtr_bit  Refer to \ref CANRtrSel_TypeDef.
+ * \param[in]  ide_bit  Refer to \ref CANIdeSel_TypeDef.
+ *
+ * \return The type of frame \ref CANDataFrameSel_TypeDef.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * static void can_get_ram_data(void)
+ * {
+ *     uint8_t index = 0
+ *     uint8_t rx_data[8];
+ *     CANMsgBufInfo_TypeDef mb_info;
+ *     CAN_GetMsgBufInfo(index, &mb_info);
+ *     CANDataFrameSel_TypeDef frame_type = CAN_CheckFrameType(mb_info.rtr_bit, mb_info.ide_bit);
+ * }
+ * \endcode
+ */
+CANDataFrameSel_TypeDef CAN_CheckFrameType(uint8_t rtr_bit, uint8_t ide_bit);
+
+/**
+ * \brief  Config message buffer TX interrupt.
+ *
+ * \param[in]  message_buffer_index  CAN message buffer index. The range is 0 to 15.
+ * \param[in]  newState              New state of the TX interrupt of message buffer.
+ *                                   This parameter can be one of the following values:
+ *                                   - ENABLE: Enable the TX interrupt of message buffer.
+ *                                   - DISABLE: Disable the TX interrupt of message buffer.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * static void can_basic_tx(uint32_t buf_id, CANDataFrameSel_TypeDef frame_type, \
+ *                        uint16_t frame_id, uint32_t ext_id, uint8_t *tx_data, uint8_t data_len)
+ * {
+ *
+ *   CANError_TypeDef tx_error;
+ *
+ *   CANTxFrame_TypeDef tx_frame_type;
+ *
+ *   tx_frame_type.msg_buf_id = buf_id;
+ *   tx_frame_type.frame_type = frame_type;
+ *   tx_frame_type.standard_frame_id = frame_id;
+ *   tx_frame_type.auto_reply_bit = DISABLE;
+ *   tx_frame_type.extend_frame_id = 0;
+ *
+ *   switch (frame_type)
+ *   {
+ *   case CAN_EXT_DATA_FRAME:
+ *   case CAN_EXT_REMOTE_FRAME:
+ *       tx_frame_type.extend_frame_id = ext_id;
+ *   case CAN_STD_DATA_FRAME:
+ *   case CAN_STD_REMOTE_FRAME:
+ *       break;
+ *   }
+ *
+ *   CAN_MBTxINTConfig(tx_frame_type.msg_buf_id, ENABLE);
+ *   tx_error = CAN_SetMsgBufTxMode(&tx_frame_type, tx_data, data_len);
+ *
+ *   while (CAN_GetRamState() != CAN_RAM_STATE_IDLE);
+ *
+ *   if (tx_error != CAN_NO_ERR)
+ *   {
+ *       IO_PRINT_INFO1("can_basic_tx: TX error %d", tx_error);
+ *   }
+ *  }
+ * \endcode
+ */
+void CAN_MBTxINTConfig(uint8_t message_buffer_index, FunctionalState newState);
+
+/**
+ * \brief  Config message buffer RX interrupt.
+ *
+ * \param[in]  message_buffer_index  CAN message buffer index. The range is 0 to 15.
+ * \param[in]  newState              New state of the RX interrupt of message buffer.
+ *                                   This parameter can be one of the following values:
+ *                                   - ENABLE: Enable the RX interrupt of message buffer.
+ *                                   - DISABLE: Disable the RX interrupt of message buffer.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * static void can_basic_rx(void)
+ * {
+ *     CANError_TypeDef rx_error;
+ *     CANRxFrame_TypeDef rx_frame_type;
+ *     rx_frame_type.msg_buf_id = 7;
+ *
+ *     rx_frame_type.extend_frame_id = 0;
+ *     rx_frame_type.standard_frame_id = 0;
+ *     rx_frame_type.frame_rtr_mask = SET;
+ *     rx_frame_type.frame_ide_mask = SET;
+ *     rx_frame_type.frame_id_mask = CAN_FRAME_ID_MASK_MAX_VALUE;
+ *     rx_frame_type.rx_dma_en = RESET;
+ *     rx_frame_type.auto_reply_bit = RESET;
+ *     rx_error = CAN_SetMsgBufRxMode(&rx_frame_type);
+ *
+ *     CAN_MBRxINTConfig(rx_frame_type.msg_buf_id, ENABLE);
+ *
+ *     while (CAN_GetRamState() != CAN_RAM_STATE_IDLE);
+ *
+ *     if (rx_error != CAN_NO_ERR)
+ *     {
+ *         IO_PRINT_INFO1("can_basic_rx: RX error %d", rx_error);
+ *     }
+ *
+ *     IO_PRINT_INFO0("can_basic_rx: waiting for RX...");
+ * }
+ * \endcode
+ */
+void CAN_MBRxINTConfig(uint8_t message_buffer_index, FunctionalState newState);
+
+/**
+ * \brief  Get CAN FIFO status.
+ *
+ * \param[in] CAN_FifoStatus  The status of CAN FIFO. \ref CANFifoStatus_TypeDef
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * static void can_get_fifo_status(void)
+ * {
+ *     CANFifoStatus_TypeDef fifo_status;
+ *     CAN_GetFifoStatus(&fifo_status);
+ * }
+ * \endcode
+ */
+void CAN_GetFifoStatus(CANFifoStatus_TypeDef *CAN_FifoStatus);
+
+/**
+ * \brief  Set TX message trigger by timestamp timer.
+ *
+ * \param[in]  newState                 New state of the TX trigger function.
+ *                                      This parameter can be one of the following values:
+ *                                      - ENABLE: Enable the TX trigger function.
+ *                                      - DISABLE: Disable the TX trigger function.
+ * \param[in]  trigger_timestamp_begin  End of trigger time.
+ * \param[in]  close_offset             Start of trigger time.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * static void can_tx_trigger(void)
+ * {
+ *     uint16_t begin_ts = CAN_GetTimeStampCount();
+ *     begin_ts += 1000;
+ *     CAN_TxTriggerConfig(ENABLE, begin_ts, 100);
+ * }
+ * \endcode
+ */
+void CAN_TxTriggerConfig(FunctionalState newState,
+                         uint16_t trigger_timestamp_begin,
+                         uint16_t close_offset);
+
+/**
+ * \brief  Get can bus state.
+ *
+ * \return The state of bus.
+ *         - CAN_BUS_STATE_ON: The bus is on.
+ *         - CAN_BUS_STATE_OFF: The bus is off.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * static void can_get_bus_state(void)
+ * {
+ *     while (CAN_GetBusState() != CAN_BUS_STATE_ON);
+ * }
+ * \endcode
+ */
+uint32_t CAN_GetBusState();
+
+/**
+ * \brief  Get message buffer RAM state.
+ *
+ * \return The state of message buffer RAM.
+ *         - CAN_RAM_STATE_EXCHANGING: CAN RAM is exchanging.
+ *         - CAN_RAM_STATE_IDLE: CAN RAM is idle.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * static void can_get_ram_state(void)
+ * {
+ *     while (CAN_GetRamState() != CAN_RAM_STATE_IDLE);
+ * }
+ * \endcode
+ */
+uint32_t CAN_GetRamState();
+
+/**
+ * \brief  Get message buffer TX done flag.
+ *
+ * \param[in] message_buffer_index  CAN message buffer index. The range is 0 to 15.
+ *
+ * \return The flag of message buffer TX done.
+ *         - SET: The TX done of message buffer is set.
+ *         - RESET: The TX done of message buffer is unset.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * static void can_get_tx_done_flag(void)
+ * {
+ *     for (uint8_t index = 0; index < CAN_MESSAGE_BUFFER_MAX_CNT; index++)
+ *     {
+ *          if (SET == CAN_GetMBnTxDoneFlag(index))
+ *          {
+ *              IO_PRINT_INFO1("can_trx_handler: MB_%d TX done", index);
+ *              CAN_ClearMBnTxDoneFlag(index);
+ *          }
+ *      }
+ * }
+ * \endcode
+ */
+FlagStatus CAN_GetMBnTxDoneFlag(uint8_t message_buffer_index);
+
+/**
+ * \brief  Clear message buffer TX done flag.
+ *
+ * \param[in]  message_buffer_index  CAN message buffer index. The range is 0 to 15.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * static void can_get_tx_done_flag(void)
+ * {
+ *     for (uint8_t index = 0; index < CAN_MESSAGE_BUFFER_MAX_CNT; index++)
+ *     {
+ *          if (SET == CAN_GetMBnTxDoneFlag(index))
+ *          {
+ *              IO_PRINT_INFO1("can_trx_handler: MB_%d TX done", index);
+ *              CAN_ClearMBnTxDoneFlag(index);
+ *          }
+ *      }
+ * }
+ * \endcode
+ */
+void CAN_ClearMBnTxDoneFlag(uint8_t message_buffer_index);
+
+/**
+ * \brief  Get message buffer TX error flag.
+ *
+ * \param[in] message_buffer_index  CAN message buffer index. The range is 0 to 15.
+ *
+ * \return The flag of message buffer TX error.
+ *         - SET: The TX error of message buffer is set.
+ *         - RESET: The TX error of message buffer is unset.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * static void can_get_tx_error_flag(void)
+ * {
+ *     for (uint8_t index = 0; index < CAN_MESSAGE_BUFFER_MAX_CNT; index++)
+ *     {
+ *          if (SET == CAN_GetMBnTxErrorFlag(index))
+ *          {
+ *              IO_PRINT_INFO1("can_trx_handler: CAN ERROR TX MB_%d", index);
+ *              CAN_ClearMBnTxErrorFlag(index);
+ *          }
+ *      }
+ * }
+ * \endcode
+ */
+FlagStatus CAN_GetMBnTxErrorFlag(uint8_t message_buffer_index);
+
+/**
+ * \brief  Clear message buffer TX error flag.
+ *
+ * \param[in]  message_buffer_index  CAN message buffer index. The range is 0 to 15.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * static void can_get_tx_error_flag(void)
+ * {
+ *     for (uint8_t index = 0; index < CAN_MESSAGE_BUFFER_MAX_CNT; index++)
+ *     {
+ *          if (SET == CAN_GetMBnTxErrorFlag(index))
+ *          {
+ *              IO_PRINT_INFO1("can_trx_handler: CAN ERROR TX MB_%d", index);
+ *              CAN_ClearMBnTxErrorFlag(index);
+ *          }
+ *      }
+ * }
+ * \endcode
+ */
+void CAN_ClearMBnTxErrorFlag(uint8_t message_buffer_index);
+
+/**
+ * \brief  Get message buffer TX finish flag, it indicates the TX message in the message buffer finish sending.
+ *
+ * \param[in]  message_buffer_index  CAN message buffer index. The range is 0 to 15.
+ *
+ * \return The flag of message buffer TX finish.
+ *         - SET: The TX finish of message buffer is set.
+ *         - RESET: The TX finish of message buffer is unset.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * static void can_get_tx_finish_flag(void)
+ * {
+ *     for (uint8_t index = 0; index < CAN_MESSAGE_BUFFER_MAX_CNT; index++)
+ *     {
+ *          if (SET == CAN_GetMBnStatusTxFinishFlag(index))
+ *          {
+ *              IO_PRINT_INFO1("can_get_tx_finish_flag: TX finish MB_%d", index);
+ *          }
+ *      }
+ * }
+ * \endcode
+ */
+FlagStatus CAN_GetMBnStatusTxFinishFlag(uint8_t message_buffer_index);
+
+/**
+ * \brief  Get message buffer TX request flag, it indicates the TX message in buffer is pending for transmit.
+ *
+ * \param[in]  message_buffer_index  CAN message buffer index. The range is 0 to 15.
+ *
+ * \return The flag of message buffer TX request.
+ *         - SET: The TX request of message buffer is set.
+ *         - RESET: The TX request of message buffer is unset.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * static void can_get_tx_req_flag(void)
+ * {
+ *     for (uint8_t index = 0; index < CAN_MESSAGE_BUFFER_MAX_CNT; index++)
+ *     {
+ *          if (SET == CAN_GetMBnStatusTxReqFlag(index))
+ *          {
+ *              IO_PRINT_INFO1("can_get_tx_req_flag: TX pending MB_%d", index);
+ *          }
+ *      }
+ * }
+ * \endcode
+ */
+FlagStatus CAN_GetMBnStatusTxReqFlag(uint8_t message_buffer_index);
+
+/**
+ * \brief  Get message buffer RX done flag.
+ *
+ * \param[in]  message_buffer_index  CAN message buffer index. The range is 0 to 15.
+ *
+ * \return The flag of message buffer RX done.
+ *         - SET: The RX done of message buffer is set.
+ *         - RESET: The RX done of message buffer is unset.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * static void can_get_rx_done_flag(void)
+ * {
+ *     for (uint8_t index = 0; index < CAN_MESSAGE_BUFFER_MAX_CNT; index++)
+ *     {
+ *          if (SET == CAN_GetMBnRxDoneFlag(index))
+ *          {
+ *              IO_PRINT_INFO1("can_trx_handler: MB_%d RX done", index);
+ *              CAN_ClearMBnRxDoneFlag(index);
+ *          }
+ *      }
+ * }
+ * \endcode
+ */
+FlagStatus CAN_GetMBnRxDoneFlag(uint8_t message_buffer_index);
+
+/**
+ * \brief  Clear message buffer RX done flag.
+ *
+ * \param[in]  message_buffer_index  CAN message buffer index. The range is 0 to 15.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * static void can_clear_rx_done_flag(void)
+ * {
+ *     for (uint8_t index = 0; index < CAN_MESSAGE_BUFFER_MAX_CNT; index++)
+ *     {
+ *          if (SET == CAN_GetMBnRxDoneFlag(index))
+ *          {
+ *              IO_PRINT_INFO1("can_trx_handler: MB_%d RX done", index);
+ *              CAN_ClearMBnRxDoneFlag(index);
+ *          }
+ *      }
+ * }
+ * \endcode
+ */
+void CAN_ClearMBnRxDoneFlag(uint8_t message_buffer_index);
+
+/**
+ * \brief  Get message buffer RX valid flag, it indicates new message has been received in the message buffer.
+ *
+ * \param[in]  message_buffer_index  CAN message buffer index. The range is 0 to 15.
+ *
+ * \return The flag of message buffer RX valid.
+ *         - SET: The RX valid of message buffer is set.
+ *         - RESET: The RX valid of message buffer is unset.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * static void can_get_rx_valid_flag(void)
+ * {
+ *     for (uint8_t index = 0; index < CAN_MESSAGE_BUFFER_MAX_CNT; index++)
+ *     {
+ *          if (SET == CAN_GetMBnStatusRxValidFlag(index))
+ *          {
+ *              IO_PRINT_INFO1("can_get_rx_valid_flag: MB_%d RX valid", index);
+ *          }
+ *      }
+ * }
+ * \endcode
+ */
+FlagStatus CAN_GetMBnStatusRxValidFlag(uint8_t message_buffer_index);
+
+/**
+ * \brief  Get message buffer RX ready flag, it indicates the message buffer is ready for receiving a new message.
+ *
+ * \param[in]  message_buffer_index  CAN message buffer index. The range is 0 to 15.
+ *
+ * \return The flag of message buffer RX ready.
+ *         - SET: The RX ready of message buffer is set.
+ *         - RESET: The RX ready of message buffer is unset.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * static void can_get_rx_ready_flag(void)
+ * {
+ *     for (uint8_t index = 0; index < CAN_MESSAGE_BUFFER_MAX_CNT; index++)
+ *     {
+ *          if (SET == CAN_GetMBnStatusRxReadyFlag(index))
+ *          {
+ *              IO_PRINT_INFO1("can_get_rx_ready_flag: MB_%d RX ready", index);
+ *          }
+ *      }
+ * }
+ * \endcode
+ */
+FlagStatus CAN_GetMBnStatusRxReadyFlag(uint8_t message_buffer_index);
+
+/**
+ * \brief  Enable or disable can time stamp.
+ *
+ * \param[in]  newState  New state of the time stamp.
+ *                       This parameter can be one of the following values:
+ *                       - ENABLE: Enable the time stamp.
+ *                       - DISABLE: Disable the time stamp.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * static void can_enable_timestamp(void)
+ * {
+ *     CAN_TimeStampConfig(ENABLE);
+ * }
+ * \endcode
+ */
+void CAN_TimeStampConfig(FunctionalState newState);
+
+/**
+ * \brief  Get time stamp count.
+ *
+ * \return Time stamp count.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * static void can_get_timestamp(void)
+ * {
+ *     uint16_t begin_ts = CAN_GetTimeStampCount();
+ * }
+ * \endcode
+ */
+uint16_t CAN_GetTimeStampCount();
+
+/**
+ * \brief  Get RX DMA block size(word).
+ *
+ * \return RX DMA block size.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * static void can_get_dma_msize(void)
+ * {
+ *     uint32_t dma_buffer_size = CAN_GetRxDmaMsize();
+ * }
+ * \endcode
+ */
+uint32_t CAN_GetRxDmaMsize();
+
+/**
+ * \brief  Get message buffer RX DMA enable flag.
+ *
+ * \param[in]  message_buffer_index  CAN message buffer index. The range is 0 to 15.
+ *
+ * \return The flag of message buffer RX DMA enable.
+ *         - SET: The RX dma enable of message buffer is set.
+ *         - RESET: The RX dma enable of message buffer is unset.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * static void can_get_rx_dma_enable_flag(void)
+ * {
+ *     FlagStatus dma_en_flag = CAN_GetMBnRxDmaEnFlag(index);
+ * }
+ * \endcode
+ */
+FlagStatus CAN_GetMBnRxDmaEnFlag(uint8_t message_buffer_index);
+
+/**
+ * \brief  Set message buffer RX DMA enable.
+ *
+ * \param[in] message_buffer_index  CAN message buffer index. The range is 0 to 15.
+ * \param[in] newState              New state of the message buffer RX DMA enable.
+ *                                  This parameter can be one of the following values:
+ *                                  - ENABLE: Enable the RX DMA of message buffer.
+ *                                  - DISABLE: Disable the RX DMA of message buffer.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * static void can_set_rx_dma_enable(void)
+ * {
+ *     CAN_SetMBnRxDmaEnFlag(RX_DMA_BUF_ID, ENABLE);
+ * }
+ * \endcode
+ */
+void CAN_SetMBnRxDmaEnFlag(uint8_t message_buffer_index,
+                           FunctionalState newState);
+
+/**
+ * \brief  Set test mode for CAN.
+ * \param[in] CANx: selected CAN peripheral.
+ * \param[in] CAN_TestModeSel: Test mode to set.
+ *      This parameter can the following values:
+ *      \arg CAN_TEST_MODE_NONE: Normal tx/rx mode.
+ *      \arg CAN_TEST_MODE_INT_LOOPBACK: Loopback mode.
+ *      \arg CAN_TEST_MODE_SILENCE: Silence mode.
+ * \return none.
+ */
+void CAN_SetTestMode(uint8_t CAN_TestModeSel);
+
+/**
+ * \brief  Enable or disable CAN auto-re-tx function.
+ * \param[in] CANx: selected CAN peripheral.
+ * \param[in] newState: the state of CAN auto-re-tx function.
+ * \return none.
+ */
+void CAN_AutoReTxCmd(FunctionalState NewState);
+
+/**
+ * \brief  Set can bit timing.
+ * \param[in] CANx: selected CAN peripheral.
+ * \param[in] CAN_BitTiming:  Pointer to a CAN_BIT_TIMING_TYPE_TypeDef structure that
+ *            contains the bit timing information for the specified CAN peripheral
+ * \return none.
+ */
+void CAN_SetTiming(CAN_BIT_TIMING_TYPE_TypeDef *CAN_BitTiming);
+
+/**
+ * \brief  Get error passive status.
+ * \param[in] CANx: selected CAN peripheral.
+ * \return The flag of error passive status.
+ */
+FlagStatus CAN_GetErrorPassiveStatus();
+
+/**
+ * \brief  Get error warning status.
+ * \param[in] CANx: selected CAN peripheral.
+ * \return The flag of error warning status.
+ */
+FlagStatus CAN_GetErrorWarningStatus();
+
+/**
+ * \brief  Get tx error counter.
+ * \param[in] CANx: selected CAN peripheral.
+ * \return The counter of tx error.
+ */
+int CAN_GetTxErrorCnt();
+
+/**
+ * \brief  Get rx error counter.
+ * \param[in] CANx: selected CAN peripheral.
+ * \return The counter of rx error.
+ */
+int CAN_GetRxErrorCnt();
+
+/**
+ * \brief  Config CAN clock source div.
+ *
+ * \param[in] div  CAN clock div. Refer to \ref CANClkDIV_TypeDef.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * static void can_config_clock(void)
+ * {
+ *     CAN_ClkDivConfig(CAN_CLK_DIV_1);
+ * }
+ * \endcode
+ */
+void CAN_ClkDivConfig(CANClockDiv_TypeDef div);
+
+/**
+ * \brief  Get CAN clock divider.
+ *
+ * \param[out] ClockSrc  CAN clock src.
+ * \param[out] ClockDiv  CAN clock div.
+ *
+ * \return The status of get clock.
+ */
+bool CAN_ClkGet(CANClockSrc_TypeDef *ClockSrc, CANClockDiv_TypeDef *ClockDiv);
+
+#if (CAN_SUPPORT_SLEEP_MODE == 1)
+/**
+ * \brief  Check CAN sleep state.
+ *
+ * \return The flag of CAN sleep state.
+ */
+FlagStatus CAN_CheckSleepStatus();
+
+/**
+ * \brief  Enable or disable CAN lower power clock.
+ *
+ * \param[in] newState  Enable or disable CAN lower power clock.
+ * \param[in] div       Low power clock div.
+ */
+void CAN_LowPowerClkCmd(FunctionalState newState, CANLowPowerClkDIV_TypeDef div);
+
+/**
+ * \brief  Config wake up pin fit function.
+ *
+ * \param[in] newState    Enable or disable CAN wake up pin fit function.
+ * \param[in] flt_length  Config wake up pin fit length.
+ *                        minimu value is 1. The unit is low power clock period.
+ */
+void CAN_SetWakeUpPinFltFunction(FunctionalState newState, uint8_t flt_length);
+/**
+ * \brief  Request CAN to sleep mode.
+ *
+ */
+void CAN_RequestToSleepMode();
+
+/**
+ * \brief  Manual wake up CAN.
+ *
+ * \return The flag of message buffer rx dma enable.
+ */
+void CAN_ManualWakeup();
+#endif
+
+/** End of CAN_Exported_Functions
+  * \}
+  */
+/** End of CAN
+  * \}
+  */
+#ifdef __cplusplus
+}
+#endif
+#endif /* _RTL_CAN_H_ */
+
diff --git a/bee/drivers/can/src/device/rtl87x2g/rtl_can_def.h b/bee/drivers/can/src/device/rtl87x2g/rtl_can_def.h
new file mode 100644
index 00000000..2d3bcb11
--- /dev/null
+++ b/bee/drivers/can/src/device/rtl87x2g/rtl_can_def.h
@@ -0,0 +1,142 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef RTL_CAN_DEF_H
+#define RTL_CAN_DEF_H
+
+#include "utils/rtl_utils.h"
+#include "address_map.h"
+
+#ifdef  __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/*============================================================================*
+ *                          CAN Features
+ *============================================================================*/
+#define CAN_SUPPORT_EXT_LOOPBACK                         (0) //!< The function is not supported.
+#define CAN_SUPPORT_INT_MSK_STS                          (0) //!< The function is not supported.
+#define CAN_SUPPORT_SLEEP_MODE                           (0) //!< The function is not supported.
+
+/*============================================================================*
+ *                         Types
+ *============================================================================*/
+/**
+* \brief       CAN clock divider definition.
+*
+* \ingroup     CAN_Exported_Types
+*/
+typedef enum
+{
+    CAN_CLOCK_DIVIDER_1 = 0,      //!< DVI = 1 (40M / 1).
+    CAN_CLOCK_DIVIDER_2 = 1,      //!< DVI = 2 (40M / 2).
+} CANClockDiv_TypeDef;
+
+#define IS_CAN_CLK_DIV(DIV)              (((DIV) == CAN_CLOCK_DIVIDER_1) || \
+                                          ((DIV) == CAN_CLOCK_DIVIDER_2)) //!< Check if the input parameter is valid.
+
+/**
+* \brief       CAN clock source definition.
+*
+* \ingroup     CAN_Exported_Types
+*/
+typedef enum
+{
+    CAN_CLOCK_SRC_40M,      //!< The clock source of can is 40MHz.
+} CANClockSrc_TypeDef;
+
+#define IS_SPI_CLK_SOURCE(PERIPH)     ((PERIPH) == CAN_CLOCK_SRC_40M) //!< Check if the input parameter is valid.
+
+/*============================================================================*
+ *                          CAN Registers Memory Map
+ *============================================================================*/
+typedef struct            /*!< CAN Structure */
+{
+    __IO uint32_t  CAN_CTL;              /*!< 0x00 */
+    __IO uint32_t  CAN_STS;              /*!< 0x04 */
+    __IO uint32_t  CAN_FIFO_STS;         /*!< 0x08 */
+    __IO uint32_t  CAN_BIT_TIMING;       /*!< 0x0C */
+    __IO uint32_t  CAN_RSVD_0X10;        /*!< 0x10 */
+    __IO uint32_t  CAN_RSVD_0X14;        /*!< 0x14 */
+    __IO uint32_t  CAN_INT_EN;           /*!< 0x18 */
+    __IO uint32_t  CAN_MB_RXINT_EN;      /*!< 0x1C */
+    __IO uint32_t  CAN_MB_TXINT_EN;      /*!< 0x20 */
+    __IO uint32_t  CAN_INT_FLAG;         /*!< 0x24 */
+    __IO uint32_t  CAN_ERR_STATUS;       /*!< 0x28 */
+    __IO uint32_t  CAN_ERR_CNT_CTL;      /*!< 0x2C */
+    __IO uint32_t  CAN_ERR_CNT_STS;      /*!< 0x30 */
+    __IO uint32_t  CAN_TX_ERROR_FLAG;    /*!< 0x34 */
+    __IO uint32_t  CAN_TX_DONE;          /*!< 0x38 */
+    __IO uint32_t  CAN_RX_DONE;          /*!< 0x3C */
+    __IO uint32_t  CAN_TIME_STAMP;       /*!< 0x40 */
+    __IO uint32_t  CAN_MB_TRIGGER;       /*!< 0x44 */
+    __IO uint32_t  CAN_RXDMA_MSIZE;      /*!< 0x48 */
+    __IO uint32_t  CAN_RX_DMA_DATA;      /*!< 0x4C */
+    __IO uint32_t  CAN_SLEEP_MODE;       /*!< 0x50 */
+    __IO uint32_t  CAN_TEST;             /*!< 0x54 */
+    uint32_t  CAN_RSVD[42];              /*!< 0x58:0xFC */
+    __IO uint32_t  CAN_MB0_15_STS[16];   /*!< 0x100:0x13C */
+    uint32_t  CAN_RSVD1[48];             /*!< 0x140:0x1FC */
+    __IO uint32_t  CAN_MB0_15_CTRL[16];  /*!< 0x200:0x23C */
+    uint32_t  CAN_RSVD2[44];             /*!< 0x240:0x2EC */
+    __IO uint32_t  CAN_MB_BA_END;        /*!< 0x2F0 */
+    uint32_t  CAN_RSVD3[3];              /*!< 0x2F4:0x2FC */
+    uint32_t  CAN_RSVD4[14];             /*!< 0x300:0x334 */
+    __IO uint32_t  CAN_RAM_DATA[2];      /*!< 0x338:0x33C */
+    __IO uint32_t  CAN_RAM_ARB;          /*!< 0x340 */
+    __IO uint32_t  CAN_RAM_MASK;         /*!< 0x344 */
+    __IO uint32_t  CAN_RAM_CS;           /*!< 0x348 */
+    __IO uint32_t  CAN_RAM_CMD;          /*!< 0x34C */
+} CAN_TypeDef;
+
+/*============================================================================*
+ *                          CAN Declaration
+ *============================================================================*/
+
+#define CAN0                       ((CAN_TypeDef *) CAN_REG_BASE)
+#define CAN                         CAN0
+
+/*============================================================================*
+ *                          CAN TYPE/API Wrappers
+ *============================================================================*/
+/** \defgroup CAN         CAN
+  * \brief
+  * \{
+  */
+
+/** \defgroup CAN_Exported_Constants CAN Exported Constants
+  * \brief
+  * \{
+  */
+
+/**
+* \brief       To be compatible with the previous driver.
+* \defgroup    CAN_Constants_Wrapper CAN Constants Wrapper
+* \{
+* \ingroup     CAN_Exported_Constants
+*/
+
+#define CAN_CLK_DIV_1              CAN_CLOCK_DIVIDER_1  //!< The macro is a wrapper for CAN_CLOCK_DIVIDER_1.
+#define CAN_CLK_DIV_2              CAN_CLOCK_DIVIDER_2  //!< The macro is a wrapper for CAN_CLOCK_DIVIDER_2.
+
+/** End of CAN Constants Wrapper
+  * \}
+  */
+
+/** End of CAN_Exported_Constants
+  * \}
+  */
+
+/** End of CAN
+  * \}
+  */
+
+#ifdef  __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* RTL_CAN_DEF_H */
+
diff --git a/bee/drivers/can/src/device/rtl87x2j/rtl_can_def.h b/bee/drivers/can/src/device/rtl87x2j/rtl_can_def.h
new file mode 100644
index 00000000..502c221e
--- /dev/null
+++ b/bee/drivers/can/src/device/rtl87x2j/rtl_can_def.h
@@ -0,0 +1,876 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef RTL_CAN_DEF_H
+#define RTL_CAN_DEF_H
+
+#include "utils/rtl_utils.h"
+#include "address_map.h"
+#include "pcc_reg.h"
+
+#ifdef  __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/*============================================================================*
+ *                          CAN Features
+ *============================================================================*/
+#define CAN_SUPPORT_EXT_LOOPBACK                         (1)
+#define CAN_SUPPORT_INT_MSK_STS                          (1)
+#define CAN_SUPPORT_SLEEP_MODE                           (1)
+#define CAN_SUPPORT_AUTO_CLOCK                           (1)
+
+/*============================================================================*
+ *                          CAN Registers Memory Map
+ *============================================================================*/
+typedef struct            /*!< CAN Structure */
+{
+    __IO uint32_t CAN_CTL;                      /*!< 0x00 */
+    __IO uint32_t CAN_STS;                      /*!< 0x04 */
+    __IO uint32_t CAN_FIFO_STS;                 /*!< 0x08 */
+    __IO uint32_t CAN_BIT_TIMING;               /*!< 0x0C */
+    __IO uint32_t CAN_FD_BIT_TIMING;            /*!< 0x10 */
+    __IO uint32_t CAN_FD_SSP_CAL;               /*!< 0x14 */
+    __IO uint32_t CAN_INT_EN;                   /*!< 0x18 */
+    __IO uint32_t CAN_MB_RXINT_EN;              /*!< 0x1C */
+    __IO uint32_t CAN_MB_TXINT_EN;              /*!< 0x20 */
+    __IO uint32_t CAN_INT_FLAG;                 /*!< 0x24 */
+    __IO uint32_t CAN_ERR_STATUS;               /*!< 0x28 */
+    __IO uint32_t CAN_ERR_CNT_CTL;              /*!< 0x2C */
+    __IO uint32_t CAN_ERR_CNT_STS;              /*!< 0x30 */
+    __IO uint32_t CAN_TX_ERROR_FLAG;            /*!< 0x34 */
+    __IO uint32_t CAN_TX_DONE;                  /*!< 0x38 */
+    __IO uint32_t CAN_RX_DONE;                  /*!< 0x3C */
+    __IO uint32_t CAN_TIME_STAMP;               /*!< 0x40 */
+    __IO uint32_t CAN_MB_TRIGGER;               /*!< 0x44 */
+    __IO uint32_t CAN_RXDMA_MSIZE;              /*!< 0x48 */
+    __IO uint32_t CAN_RX_DMA_DATA;              /*!< 0x4C */
+    __IO uint32_t CAN_SLEEP_MODE;               /*!< 0x50 */
+    __IO uint32_t CAN_TEST;                     /*!< 0x54 */
+    __IO uint32_t CAN_RSVD[42];                 /*!< 0x58 - 0xFC */
+    __IO uint32_t CAN_MB0_15_STS[16];           /*!< 0x100 - 0x13C */
+    __IO uint32_t CAN_RSVD1[48];                /*!< 0x140 - 0x1FC */
+    __IO uint32_t CAN_MB0_15_CTRL[16];          /*!< 0x200 - 0x23C */
+    __IO uint32_t CAN_RSVD2[44];                /*!< 0x240 - 0x2EC */
+    __IO uint32_t CAN_MB_BA_END;                /*!< 0x2F0 */
+    __IO uint32_t CAN_RSVD3[3];                 /*!< 0x2F4 - 0x2FC */
+    uint32_t  CAN_RAM_RSVD[14];                 /*!< 0x300:0x334 */
+    __IO uint32_t  CAN_RAM_DATA[2];             /*!< 0x338:0x33C */
+    __IO uint32_t CAN_RAM_ARB;                  /*!< 0x340 */
+    __IO uint32_t CAN_RAM_MASK;                 /*!< 0x344 */
+    __IO uint32_t CAN_RAM_CS;                   /*!< 0x348 */
+    __IO uint32_t CAN_RAM_CMD;                  /*!< 0x34C */
+    __IO uint32_t CAN_RSVD4[40];                /*!< 0x350 - 0x3EC */
+    __IO uint32_t CAN_QACTIVE_MANUAL_CTRL;      /*!< 0x3F0 */
+} CAN_TypeDef;
+
+/*============================================================================*
+ *                          CAN Declaration
+ *============================================================================*/
+#define CAN0                       ((CAN_TypeDef *) CAN_BASE)
+#define CAN                         CAN0
+
+/*============================================================================*
+ *                          CAN Registers and Field Descriptions
+ *============================================================================*/
+/* 0x00
+   0       R/W    can_en                      1'h0
+   1       R/W/ES bus_on_req                  1'h0
+   2       R/W    can_tri_sample              1'h0
+   3       R/W    auto_re_tx_en               1'h0
+   4       R/W    test_mode_en                1'h0
+   5       R/W    rx_fifo_en                  1'h0
+   6       R/W    can_fd_en                   1'h0
+   7       R/W    can_rxdma_en                1'h0
+   8       R/W    can_fd_crc_mode             1'h0
+   9       R/W    can_fd_ssp_auto             1'h0
+   31:10   R      reserved_dummy00_31_10      22'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t can_en: 1;
+        uint32_t bus_on_req: 1;
+        uint32_t can_tri_sample: 1;
+        uint32_t auto_re_tx_en: 1;
+        uint32_t test_mode_en: 1;
+        uint32_t rx_fifo_en: 1;
+        uint32_t can_fd_en: 1;
+        uint32_t can_rxdma_en: 1;
+        uint32_t can_fd_crc_mode: 1;
+        uint32_t can_fd_ssp_auto: 1;
+        const uint32_t reserved_0: 22;
+    } b;
+} CAN_0x00_TYPE_TypeDef;
+
+
+/* 0x04
+   0       R      bus_on_state                1'h0
+   31:1    R      reserved_dummy04_31_1       31'b0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t bus_on_state: 1;
+        const uint32_t reserved_0: 31;
+    } b;
+} CAN_0x04_TYPE_TypeDef;
+
+
+/* 0x08
+   0       R      fifo_msg_full               1'h0
+   1       R      fifo_msg_empty              1'h1
+   2       R      fifo_msg_overflow           1'h0
+   3       R      reserved_dummy08_8          1'h0
+   6:4     R      fifo_msg_lvl                3'h0
+   31:7    R      reserved_dummy08_31_7       25'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t fifo_msg_full: 1;
+        const uint32_t fifo_msg_empty: 1;
+        const uint32_t fifo_msg_overflow: 1;
+        const uint32_t reserved_1: 1;
+        const uint32_t fifo_msg_lvl: 3;
+        const uint32_t reserved_0: 25;
+    } b;
+} CAN_0x08_TYPE_TypeDef;
+
+
+/* 0x0C
+   7:0     R/W    can_tseg1                   8'h0
+   15:8    R/W    can_tseg2                   8'h0
+   18:16   R/W    can_sjw                     3'h0
+   23:19   R      reserved_dummy0c_23_19      5'h0
+   31:24   R/W    can_brp                     8'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t can_tseg1: 8;
+        uint32_t can_tseg2: 8;
+        uint32_t can_sjw: 3;
+        const uint32_t reserved_0: 5;
+        uint32_t can_brp: 8;
+    } b;
+} CAN_0x0C_TYPE_TypeDef;
+
+
+/* 0x10
+   7:0     R/W    can_fd_tseg1                8'h0
+   15:8    R/W    can_fd_tseg2                8'h0
+   18:16   R/W    can_fd_sjw                  3'h0
+   23:19   R      reserved_dummy10_23_19      5'h0
+   31:24   R/W    can_fd_brp                  8'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t can_fd_tseg1: 8;
+        uint32_t can_fd_tseg2: 8;
+        uint32_t can_fd_sjw: 3;
+        const uint32_t reserved_0: 5;
+        uint32_t can_fd_brp: 8;
+    } b;
+} CAN_0x10_TYPE_TypeDef;
+
+
+/* 0x14
+   7:0     R/W/ES can_fd_ssp                  8'h0
+   15:8    R/W    can_fd_ssp_min              8'h0
+   23:16   R/W    can_fd_ssp_dco              8'h0
+   31:24   R/W    can_fd_ssp_dco_2            8'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t can_fd_ssp: 8;
+        uint32_t can_fd_ssp_min: 8;
+        uint32_t can_fd_ssp_dco: 8;
+        uint32_t can_fd_ssp_dco_2: 8;
+    } b;
+} CAN_0x14_TYPE_TypeDef;
+
+
+/* 0x18
+   0       R/W    tx_int_en                   1'h0
+   1       R/W    rx_int_en                   1'h0
+   2       R/W    error_int_en                1'h0
+   3       R/W    wakeup_int_en               1'h0
+   4       R/W    busoff_int_en               1'h0
+   5       R/W    ram_move_done_int_en        1'h0
+   15:6    R      reserved_dummy18_15_6       10'h0
+   16      R/W    tx_int_mask                 1'h0
+   17      R/W    rx_int_mask                 1'h0
+   18      R/W    error_int_mask              1'h0
+   19      R/W    wakeup_int_mask             1'h0
+   20      R/W    busoff_int_mask             1'h0
+   21      R/W    ram_move_done_int_mask      1'h0
+   31:22   R      reserved_dummy18_31_6       10'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t tx_int_en: 1;
+        uint32_t rx_int_en: 1;
+        uint32_t error_int_en: 1;
+        uint32_t wakeup_int_en: 1;
+        uint32_t busoff_int_en: 1;
+        uint32_t ram_move_done_int_en: 1;
+        const uint32_t reserved_1: 10;
+        uint32_t tx_int_mask: 1;
+        uint32_t rx_int_mask: 1;
+        uint32_t error_int_mask: 1;
+        uint32_t wakeup_int_mask: 1;
+        uint32_t busoff_int_mask: 1;
+        uint32_t ram_move_done_int_mask: 1;
+        const uint32_t reserved_0: 10;
+    } b;
+} CAN_0x18_TYPE_TypeDef;
+
+
+/* 0x1C
+   15:0    R/W    can_mb_rxint_en             16'h0
+   31:16   R      reserved_dummy1c_31_16      16'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t can_mb_rxint_en: 16;
+        const uint32_t reserved_0: 16;
+    } b;
+} CAN_0x1C_TYPE_TypeDef;
+
+
+/* 0x20
+   15:0    R/W    can_mb_txint_en             16'h0
+   31:16   R      reserved_dummy20_31_16      16'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t can_mb_txint_en: 16;
+        const uint32_t reserved_0: 16;
+    } b;
+} CAN_0x20_TYPE_TypeDef;
+
+
+/* 0x24
+   0       R/W1C  tx_raw_int_flag             1'h0
+   1       R/W1C  rx_raw_int_flag             1'h0
+   2       R/W1C  error_raw_int_flag          1'h0
+   3       R/W1C  wakeup_raw_int_flag         1'h0
+   4       R/W1C  busoff_raw_int_flag         1'h0
+   5       R/W1C  ram_move_done_raw_int_flag  1'h0
+   15:6    R      reserved_dummy24_15_6       10'h0
+   16      R      tx_int_flag                 1'h0
+   17      R      rx_int_flag                 1'h0
+   18      R      error_int_flag              1'h0
+   19      R      wakeup_int_flag             1'h0
+   20      R      busoff_int_flag             1'h0
+   21      R      ram_move_done_int_flag      1'h0
+   31:22   R      reserved_dummy24_31_22      10'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t tx_raw_int_flag: 1;
+        uint32_t rx_raw_int_flag: 1;
+        uint32_t error_raw_int_flag: 1;
+        uint32_t wakeup_raw_int_flag: 1;
+        uint32_t busoff_raw_int_flag: 1;
+        uint32_t ram_move_done_raw_int_flag: 1;
+        const uint32_t reserved_1: 10;
+        const uint32_t tx_int_flag: 1;
+        const uint32_t rx_int_flag: 1;
+        const uint32_t error_int_flag: 1;
+        const uint32_t wakeup_int_flag: 1;
+        const uint32_t busoff_int_flag: 1;
+        const uint32_t ram_move_done_int_flag: 1;
+        const uint32_t reserved_0: 10;
+    } b;
+} CAN_0x24_TYPE_TypeDef;
+
+
+/* 0x28
+   0       R/W1C  can_error_bit0              1'h0
+   1       R/W1C  can_error_bit1              1'h0
+   2       R/W1C  can_error_form              1'h0
+   3       R/W1C  can_error_crc               1'h0
+   4       R/W1C  can_error_stuff             1'h0
+   5       R/W1C  can_error_ack               1'h0
+   7:6     R      reserved_dummy28_7_6        2'h0
+   8       R/W1C  can_error_tx                1'h0
+   9       R/W1C  can_error_rx                1'h0
+   31:10   R      reserved_dummy28_31_10      22'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t can_error_bit0: 1;
+        uint32_t can_error_bit1: 1;
+        uint32_t can_error_form: 1;
+        uint32_t can_error_crc: 1;
+        uint32_t can_error_stuff: 1;
+        uint32_t can_error_ack: 1;
+        const uint32_t reserved_1: 2;
+        uint32_t can_error_tx: 1;
+        uint32_t can_error_rx: 1;
+        const uint32_t reserved_0: 22;
+    } b;
+} CAN_0x28_TYPE_TypeDef;
+
+
+/* 0x2C
+   0       R/WAC  tx_err_cnt_clr              1'h0
+   1       R/WAC  rx_err_cnt_clr              1'h0
+   7:2     R      reserved_dummy28_7_2        6'h0
+   16:8    R/W    can_error_warn_th           9'h60
+   31:17   R      reserved_dummy2c_31_17      15'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t tx_err_cnt_clr: 1;
+        uint32_t rx_err_cnt_clr: 1;
+        const uint32_t reserved_1: 6;
+        uint32_t can_error_warn_th: 9;
+        const uint32_t reserved_0: 15;
+    } b;
+} CAN_0x2C_TYPE_TypeDef;
+
+
+/* 0x30
+   8:0     R      can_tec                     9'h0
+   15:9    R      reserved_dummy30_15_9       7'h0
+   24:16   R      can_rec                     9'h0
+   27:25   R      reserved_dummy30_27_25      3'h0
+   28      R      can_error_passive           1'h0
+   29      R      can_error_busoff            1'h0
+   30      R      can_error_warning           1'h0
+   31      R      reserved_dummy30_31         1'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t can_tec: 9;
+        const uint32_t reserved_2: 7;
+        const uint32_t can_rec: 9;
+        const uint32_t reserved_1: 3;
+        const uint32_t can_error_passive: 1;
+        const uint32_t can_error_busoff: 1;
+        const uint32_t can_error_warning: 1;
+        const uint32_t reserved_0: 1;
+    } b;
+} CAN_0x30_TYPE_TypeDef;
+
+
+/* 0x34
+   15:0    RW1CB  can_tx_error_flag           16'h0
+   31:16   R      reserved_dummy34_31_16      16'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t can_tx_error_flag: 16;
+        const uint32_t reserved_0: 16;
+    } b;
+} CAN_0x34_TYPE_TypeDef;
+
+
+/* 0x38
+   15:0    RW1CB  can_tx_done                 16'h0
+   31:16   R      reserved_dummy38_31_16      16'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t can_tx_done: 16;
+        const uint32_t reserved_0: 16;
+    } b;
+} CAN_0x38_TYPE_TypeDef;
+
+
+/* 0x3C
+   15:0    RW1CB  can_rx_done                 16'h0
+   31:16   R      reserved_dummy3c_31_16      16'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t can_rx_done: 16;
+        const uint32_t reserved_0: 16;
+    } b;
+} CAN_0x3C_TYPE_TypeDef;
+
+
+/* 0x40
+   15:0    R      can_time_stamp              16'h0
+   23:16   R/W    can_time_stamp_div          8'h0
+   30:24   R      reserved_dummy40_30_24      7'h0
+   31      R/W    can_time_stamp_en           1'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t can_time_stamp: 16;
+        uint32_t can_time_stamp_div: 8;
+        const uint32_t reserved_0: 7;
+        uint32_t can_time_stamp_en: 1;
+    } b;
+} CAN_0x40_TYPE_TypeDef;
+
+
+/* 0x44
+   15:0    R/W    tx_trigger_begin            16'h0
+   23:16   R/W    tx_trigger_close_offset     8'h0
+   24      R/W    tx_trigger_en               1'h0
+   31:25   R      reserved_dummy44_31_25      7'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t tx_trigger_begin: 16;
+        uint32_t tx_trigger_close_offset: 8;
+        uint32_t tx_trigger_en: 1;
+        const uint32_t reserved_0: 7;
+    } b;
+} CAN_0x44_TYPE_TypeDef;
+
+
+/* 0x48
+   13:0    R      can_rxdma_msize             14'h2
+   31:14   R      reserved_dummy48_31_14      18'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t can_rxdma_msize: 14;
+        const uint32_t reserved_0: 18;
+    } b;
+} CAN_0x48_TYPE_TypeDef;
+
+
+/* 0x4C
+   31:0    RP     can_rx_dma_data             32'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t can_rx_dma_data: 32;
+    } b;
+} CAN_0x4C_TYPE_TypeDef;
+
+
+/* 0x50
+   7:0     R/W    can_wakepin_flt_length      8'h1
+   8       R/W    can_wakepin_flt_en          1'h0
+   9       R/W    can_lp_ck_en                1'h0
+   15:10   R      reserved_dummy50_15_9       6'h0
+   16      R/WAC  can_sleep_req               1'h0
+   17      R      can_sleep_state             1'h0
+   19:18   R      reserved_dummy50_19_18      2'h0
+   20      R/WAC  can_manual_wakeup           1'h0
+   31:21   R      reserved_dummy50_31_21      11'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t can_wakepin_flt_length: 8;
+        uint32_t can_wakepin_flt_en: 1;
+        uint32_t can_lp_ck_en: 1;
+        const uint32_t reserved_2: 6;
+        uint32_t can_sleep_req: 1;
+        const uint32_t can_sleep_state: 1;
+        const uint32_t reserved_1: 2;
+        uint32_t can_manual_wakeup: 1;
+        const uint32_t reserved_0: 11;
+    } b;
+} CAN_0x50_TYPE_TypeDef;
+
+
+/* 0x54
+   1:0     R/W    can_test_cfg                2'h0
+   31:2    R      reserved_dummy54_31_2       30'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t can_test_cfg: 2;
+        const uint32_t reserved_0: 30;
+    } b;
+} CAN_0x54_TYPE_TypeDef;
+
+/* 0x100 - 0x13C
+   0       R      can_msg_tx_req              1'h0
+   1       R      can_msg_tx_done             1'h0
+   2       R      can_msg_rx_rdy              1'h0
+   3       R      can_msg_rx_vld              1'h0
+   31:4    R      reserved_dummy13c_31_4      28'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t can_msg_tx_req: 1;
+        const uint32_t can_msg_tx_done: 1;
+        const uint32_t can_msg_rx_rdy: 1;
+        const uint32_t can_msg_rx_vld: 1;
+        const uint32_t reserved_0: 28;
+    } b;
+} CAN_0x100_0x13C_TYPE_TypeDef;
+
+/* 0x200 - 0x23C
+   8:0     R/W    can_msg@_ba                 9'h0
+   23:9    R      reserved_dummy@_23_9        15'h0
+   24      R/W/ES can_msg@_rxdma_en           1'h0
+   31:25   R      reserved_dummy@_31_25       7'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t can_msg_ba: 9;
+        const uint32_t reserved_1: 15;
+        uint32_t can_msg_rxdma_en: 1;
+        const uint32_t reserved_0: 7;
+    } b;
+} CAN_0x200_0x23C_TYPE_TypeDef;
+
+
+/* 0x2F0
+   9:0     R/W    can_msg_ba_end              10'h140
+   31:10   R      reserved_dummy2f0_31_10     22'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t can_msg_ba_end: 10;
+        const uint32_t reserved_0: 22;
+    } b;
+} CAN_0x2F0_TYPE_TypeDef;
+
+/* 0x300 - 0x33C
+   7:0     R/W/ES can_ram_data0               8'h0
+   15:8    R/W/ES can_ram_data1               8'h0
+   23:16   R/W/ES can_ram_data2               8'h0
+   31:24   R/W/ES can_ram_data3               8'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t can_ram_data0: 8;
+        uint32_t can_ram_data1: 8;
+        uint32_t can_ram_data2: 8;
+        uint32_t can_ram_data3: 8;
+    } b;
+} CAN_0x300_0x33C_TYPE_TypeDef;
+
+
+/* 0x340
+   28:0    R/W/ES can_ram_id                  29'h0
+   29      R/W/ES can_ram_ide                 1'h0
+   30      R/W/ES can_ram_rtr                 1'h0
+   31      R      reserved_dummy340_31        1'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t can_ram_id: 29;
+        uint32_t can_ram_ide: 1;
+        uint32_t can_ram_rtr: 1;
+        const uint32_t reserved_0: 1;
+    } b;
+} CAN_0x340_TYPE_TypeDef;
+
+
+/* 0x344
+   28:0    R/W/ES can_ram_id_mask             29'h0
+   29      R/W/ES can_ram_ide_mask            1'h0
+   30      R/W/ES can_ram_rtr_mask            1'h0
+   31      R      reserved_dummy344_31        1'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t can_ram_id_mask: 29;
+        uint32_t can_ram_ide_mask: 1;
+        uint32_t can_ram_rtr_mask: 1;
+        const uint32_t reserved_0: 1;
+    } b;
+} CAN_0x344_TYPE_TypeDef;
+
+
+/* 0x348
+   3:0     R/W/ES can_ram_dlc                 4'h0
+   4       R/W/ES can_ram_lost                1'h0
+   5       R/W/ES can_ram_rxtx                1'h0
+   6       R/W/ES can_ram_autoreply           1'h0
+   7       R      reserved_dummy348_7         1'h0
+   8       R/W/ES can_ram_edl                 1'h0
+   9       R/W/ES can_ram_brs                 1'h0
+   10      R/W/ES can_ram_esi                 1'h0
+   15:11   R      reserved_dummy348_15_11     5'h0
+   31:16   R/W/ES can_ram_timestamp           16'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t can_ram_dlc: 4;
+        uint32_t can_ram_lost: 1;
+        uint32_t can_ram_rxtx: 1;
+        uint32_t can_ram_autoreply: 1;
+        const uint32_t reserved_1: 1;
+        uint32_t can_ram_edl: 1;
+        uint32_t can_ram_brs: 1;
+        uint32_t can_ram_esi: 1;
+        const uint32_t reserved_0: 5;
+        uint32_t can_ram_timestamp: 16;
+    } b;
+} CAN_0x348_TYPE_TypeDef;
+
+
+/* 0x34C
+   7:0     R/W    can_ram_acc_num             8'h0
+   8       R/W    can_ram_acc_mask            1'h0
+   9       R/W    can_ram_acc_cs              1'h0
+   10      R/W    can_ram_acc_arb             1'h0
+   11:26   R/W    can_ram_acc_data            16'h0
+   28:27   R      reserved_dummy34c_28_27     2'h0
+   29      R/W    can_ram_buffer_en           1'h0
+   30      R/W    can_ram_dir                 1'h0
+   31      R/W/ES can_ram_start               1'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t can_ram_acc_num: 8;
+        uint32_t can_ram_acc_mask: 1;
+        uint32_t can_ram_acc_cs: 1;
+        uint32_t can_ram_acc_arb: 1;
+        uint32_t can_ram_acc_data: 16;
+        const uint32_t reserved_0: 2;
+        uint32_t can_ram_buffer_en: 1;
+        uint32_t can_ram_dir: 1;
+        uint32_t can_ram_start: 1;
+    } b;
+} CAN_0x34C_TYPE_TypeDef;
+
+
+/* 0x3F0
+   0       R/W    clklpcan_qactive_man_data   1'h0
+   1       R/W    clklpcan_qactive_man_enable 1'h0
+   2       R/W    clkapbcan_qactive_man_data  1'h0
+   3       R/W    clkapbcan_qactive_man_enable1'h0
+   4       R/W    clkcan_qactive_man_data     1'h0
+   5       R/W    clkcan_qactive_man_enable   1'h0
+   15:6    R      reserved_dummy3f0_15_6      10'h0
+   16      R/W    pwr_qactive_man_data        1'h0
+   17      R/W    pwr_qactive_man_enable      1'h0
+   31:18   R      reserved_dummy3f0_31_18     14'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t clklpcan_qactive_man_data: 1;
+        uint32_t clklpcan_qactive_man_enable: 1;
+        uint32_t clkapbcan_qactive_man_data: 1;
+        uint32_t clkapbcan_qactive_man_enable: 1;
+        uint32_t clkcan_qactive_man_data: 1;
+        uint32_t clkcan_qactive_man_enable: 1;
+        const uint32_t reserved_1: 10;
+        uint32_t pwr_qactive_man_data: 1;
+        uint32_t pwr_qactive_man_enable: 1;
+        const uint32_t reserved_0: 14;
+    } b;
+} CAN_QACTIVE_MANUAL_CTRL_TypeDef;
+
+typedef struct
+{
+    __IO uint32_t  CAN_RAM_DATA[2];
+
+    union
+    {
+        __IO uint32_t CAN_RAM_ARB;
+        __IO CAN_0x340_TYPE_TypeDef BITS_340;
+    } u_340;
+
+    union
+    {
+        __IO uint32_t CAN_RAM_MASK;
+        __IO CAN_0x344_TYPE_TypeDef BITS_344;
+    } u_344;
+
+    union
+    {
+        __IO uint32_t CAN_RAM_CS;
+        __IO CAN_0x348_TYPE_TypeDef BITS_348;
+    } u_348;
+
+    union
+    {
+        __IO uint32_t CAN_RAM_CMD;
+        __IO CAN_0x34C_TYPE_TypeDef BITS_34C;
+    } u_34C;
+} CAN_RAM_TypeDef;
+
+/*============================================================================*
+ *                          CAN TYPE/API Wrappers
+ *============================================================================*/
+/** \defgroup CAN         CAN
+  * \brief
+  * \{
+  */
+
+/** \defgroup CAN_Exported_Constants CAN Exported Constants
+  * \brief
+  * \{
+  */
+
+typedef enum
+{
+    CAN_CLOCK_DIVIDER_1 = 0,      /* 40M / 1 */
+    CAN_CLOCK_DIVIDER_2 = 1,      /* 40M / 2 */
+} CANClockDiv_TypeDef;
+
+#define IS_CAN_CLK_DIV(DIV)              (((DIV) == CAN_CLOCK_DIVIDER_1) || \
+                                          ((DIV) == CAN_CLOCK_DIVIDER_2))
+
+typedef enum
+{
+    CAN_CLOCK_SRC_40M,
+} CANClockSrc_TypeDef;
+
+#define IS_SPI_CLK_SOURCE(PERIPH)     ((PERIPH) == CAN_CLOCK_SRC_40M)
+
+/**
+* \brief       To be compatible with the previous driver.
+* \defgroup    CAN_Constants_Wrapper CAN Constants Wrapper
+* \{
+* \ingroup     CAN_Exported_Constants
+*/
+
+#define CAN_CLK_DIV_1              CAN_CLOCK_DIVIDER_1
+#define CAN_CLK_DIV_2              CAN_CLOCK_DIVIDER_2
+
+/** End of CAN Constants Wrapper
+  * \}
+  */
+
+/** End of CAN_Exported_Constants
+  * \}
+  */
+
+/** End of CAN
+  * \}
+  */
+
+typedef enum
+{
+    CAN_RX_FRAME_IGNORE_IDE = 0,
+    CAN_RX_FRAME_MATCH_IDE = 1,
+} CANFrameIDEMask_TypeDef;
+
+typedef enum
+{
+    CAN_RX_FRAME_IGNORE_RTR = 0,
+    CAN_RX_FRAME_MATCH_RTR = 1,
+} CANFrameRTRMask_TypeDef;
+
+typedef enum
+{
+    CAN_RX_FRAME_IGNORE_ID = 0,
+    CAN_RX_FRAME_MATCH_ALL_ID = 0x1FFFFFFFUL,
+} CANFrameIDMask_TypeDef;
+
+#if (CAN_SUPPORT_SLEEP_MODE == 1)
+typedef enum
+{
+    CAN_LOW_CLK_DISABLE = 0,     /* Disable low power clock */
+    CAN_LOW_CLK_DIV_5 = 1,      /* 40M / 5 */
+    CAN_LOW_CLK_DIV_10 = 2,     /* 40M / 10 */
+    CAN_LOW_CLK_DIV_20 = 3,     /* 40M / 20 */
+} CANLowPowerClkDIV_TypeDef;
+
+#define IS_CAN_LOWER_CLK_DIV(DIV)       (((DIV) == CAN_LOW_CLK_DISABLE) || \
+                                         ((DIV) == CAN_LOW_CLK_DIV_5) || \
+                                         ((DIV) == CAN_LOW_CLK_DIV_10) || \
+                                         ((DIV) == CAN_LOW_CLK_DIV_20))
+#endif
+
+#define CAN_DFS_BIT_FIELD_FD_SSP_AUTO   can_reg_0x00.b.can_fd_ssp_auto
+#define CAN_DFS_BIT_FIELD_FD_SSP_DCO_2  can_reg_0x14.b.can_fd_ssp_dco_2
+
+#define CAN0_CLOCK                      CAN_CLOCK
+
+#ifdef  __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* RTL_CAN_DEF_H */
+
diff --git a/bee/drivers/clock/CMakeLists.txt b/bee/drivers/clock/CMakeLists.txt
new file mode 100644
index 00000000..842e942b
--- /dev/null
+++ b/bee/drivers/clock/CMakeLists.txt
@@ -0,0 +1,5 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_include_directories_ifdef(CONFIG_SOC_SERIES_RTL8752H inc/rtl8752h)
+zephyr_include_directories_ifdef(CONFIG_SOC_SERIES_RTL87X2G inc/rtl87x2g)
diff --git a/bee/drivers/clock/inc/rtl8752h/clock_manager.h b/bee/drivers/clock/inc/rtl8752h/clock_manager.h
new file mode 100644
index 00000000..6e350440
--- /dev/null
+++ b/bee/drivers/clock/inc/rtl8752h/clock_manager.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __CLOCK_MANAGER_H
+#define __CLOCK_MANAGER_H
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define CLOCK_40MHZ     40000000
+#define CLOCK_30MHZ     30000000
+#define CLOCK_20MHZ     20000000
+#define CLOCK_10MHZ     10000000
+#define CLOCK_8MHZ      8000000
+#define CLOCK_5MHZ      5000000
+#define CLOCK_4MHZ      4000000
+#define CLOCK_3P3MHZ    3333333
+#define CLOCK_2P5MHZ    2500000
+#define CLOCK_1P25MHZ   1250000
+#define CLOCK_625KHZ    625000
+
+extern void (*set_active_mode_clk_src)(void);
+extern void (*set_up_32k_clk_src)(void);
+extern void (*work_around_32k_power_glitch_after_restart)(void);
+extern void (*work_around_32k_power_glitch)(void);
+void init_osc_sdm_timer(void);
+
+#endif
diff --git a/bee/drivers/clock/inc/rtl87x2g/clock_manager.h b/bee/drivers/clock/inc/rtl87x2g/clock_manager.h
new file mode 100644
index 00000000..7200e157
--- /dev/null
+++ b/bee/drivers/clock/inc/rtl87x2g/clock_manager.h
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _CLOCK_MANAGER_H_
+#define _CLOCK_MANAGER_H_
+
+#include <stdint.h>
+#include <stdbool.h>
+
+/* ======================== Active clock func declaration ========================== */
+extern void (*set_active_mode_clk_src)(void);
+extern void (*set_lp_module_clk_info)(void);
+extern void (*set_up_32k_clk_src)(void);
+void init_osc_sdm_timer(void);
+/* ==================== End of Active clock func declaration ===============================*/
+
+#endif
diff --git a/bee/drivers/codec/CMakeLists.txt b/bee/drivers/codec/CMakeLists.txt
new file mode 100644
index 00000000..ff4fafa3
--- /dev/null
+++ b/bee/drivers/codec/CMakeLists.txt
@@ -0,0 +1,4 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+add_subdirectory_ifdef(CONFIG_REALTEK_BEE_CODEC src)
diff --git a/bee/drivers/codec/Kconfig b/bee/drivers/codec/Kconfig
new file mode 100644
index 00000000..c8577d0e
--- /dev/null
+++ b/bee/drivers/codec/Kconfig
@@ -0,0 +1,8 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config REALTEK_BEE_CODEC
+	bool "Realtek Bee CODEC driver"
+	default n
+	help
+	  This option enables the codec driver for Realtek Bee.
diff --git a/bee/drivers/codec/src/CMakeLists.txt b/bee/drivers/codec/src/CMakeLists.txt
new file mode 100644
index 00000000..dd5e359a
--- /dev/null
+++ b/bee/drivers/codec/src/CMakeLists.txt
@@ -0,0 +1,4 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+add_subdirectory(device)
diff --git a/bee/drivers/codec/src/device/CMakeLists.txt b/bee/drivers/codec/src/device/CMakeLists.txt
new file mode 100644
index 00000000..034df6a1
--- /dev/null
+++ b/bee/drivers/codec/src/device/CMakeLists.txt
@@ -0,0 +1,6 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+add_soc_series_subdir(rtl8752h)
+add_soc_series_subdir(rtl87x2g)
+add_soc_series_subdir(rtl87x2j)
diff --git a/bee/drivers/codec/src/device/rtl8752h/rtl876x_codec.c b/bee/drivers/codec/src/device/rtl8752h/rtl876x_codec.c
new file mode 100644
index 00000000..c4e16296
--- /dev/null
+++ b/bee/drivers/codec/src/device/rtl8752h/rtl876x_codec.c
@@ -0,0 +1,344 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "rtl876x_rcc.h"
+#include "rtl876x_codec.h"
+#include "platform_utils.h"
+#include "platform_utils.h"
+#include "app_section.h"
+
+/**
+  * @brief  Initialize the CODEC analog registers in AON area.
+  * @param  None.
+  * @retval None
+  */
+void CODEC_AnalogCircuitInit(void)
+{
+    uint16_t reg_value = 0;
+
+    /* Enable ADC 1V1 power cut */
+    reg_value = btaon_fast_read_safe(0x110);
+    btaon_fast_write(0x110, reg_value | 0x01);
+}
+
+/**
+  * @brief  Deinitialize the CODEC analog registers in AON area.
+  * @param  None.
+  * @retval None
+  */
+void CODEC_AnalogCircuitDeInit(void)
+{
+    uint16_t reg_value = 0;
+
+    /* Disable 1V1 power cut */
+    reg_value = btaon_fast_read_safe(0x110);
+    btaon_fast_write(0x110, reg_value & (~0x01));
+}
+
+/**
+  * @brief  Deinitializes the CODEC peripheral registers to their default reset values(turn off CODEC clock).
+  * @param  CODECx: selected CODEC peripheral.
+  * @retval None
+  */
+void CODEC_DeInit(CODEC_TypeDef *CODECx)
+{
+    /* Check the parameters */
+    assert_param(IS_CODEC_PERIPH(CODECx));
+
+    if (CODEC->ADC0_CTRL0 & CODEC_AMIC_DMIC_CH0_SEL_MSK)
+    {
+        CODEC_ANA->ANA_CR0 &= CODEC_DAC_ADDACK_POW_CLR;
+        CODEC_ANA->ANA_CR0 &= CODEC_ADC_ANA_POW_CLR;
+        CODEC_ANA->ANA_CR1 &= ~0x3000000;
+    }
+    else
+    {
+        CODEC->CLK_CR2 &= ~0x8;
+    }
+    CODEC_ANA->ANA_CR1 &= ~BIT15;
+    CODEC_ANA->ANA_CR1 &= ~BIT10;
+    CODEC->ANA_CR1 &= ~BIT3;
+    CODEC->CLK_CR1 &= ~0x3FFF;
+    CODEC->I2S_CTRL &= ~BIT0;
+    CODEC->CR0 &= ~BIT0;
+
+    RCC_PeriphClockCmd(APBPeriph_CODEC, APBPeriph_CODEC_CLOCK, DISABLE);
+    CODEC_AnalogCircuitDeInit();
+}
+
+/**
+  * @brief Initializes the CODEC peripheral according to the specified
+  *   parameters in the CODEC_InitStruct
+  * @param  CODECx: selected CODEC peripheral.
+  * @param  CODEC_InitStruct: pointer to a CODEC_InitTypeDef structure that
+  *   contains the configuration information for the specified CODEC peripheral
+  * @retval None
+  */
+void CODEC_Init(CODEC_TypeDef *CODECx, CODEC_InitTypeDef *CODEC_InitStruct)
+{
+    /* Check the parameters */
+    /* MIC initialization parameters for input */
+    assert_param(IS_CODEC_PERIPH(CODECx));
+    assert_param(IS_SAMPLE_RATE(CODEC_InitStruct->CODEC_SampleRate));
+    assert_param(IS_CODEC_I2S_DATA_FORMAT(CODEC_InitStruct->CODEC_I2SFormat));
+    assert_param(IS_CODEC_I2S_DATA_WIDTH(CODEC_InitStruct->CODEC_I2SDataWidth));
+    assert_param(IS_MICBIAS_CONFIG(CODEC_InitStruct->CODEC_MicBIAS));
+    assert_param(IS_MICBST_MODE(CODEC_InitStruct->CODEC_MicBstMode));
+    assert_param(IS_MICBST_GAIN(CODEC_InitStruct->CODEC_MicBstGain));
+    assert_param(IS_CODEC_DMIC_CLOCK(CODEC_InitStruct->CODEC_DmicClock));
+    /* MIC channel 0 initialization parameters */
+    assert_param(IS_CODEC_CH0_MIC_MUTE(CODEC_InitStruct->CODEC_Ch0Mute));
+    assert_param(IS_CODEC_CH0_MIC_TYPE(CODEC_InitStruct->CODEC_Ch0MicType));
+    assert_param(IS_DMIC_CH0_LATCH_EDGE(CODEC_InitStruct->CODEC_Ch0DmicDataLatch));
+    assert_param(IS_AD_GAIN(CODEC_InitStruct->CODEC_Ch0AdGain));
+    assert_param(IS_CH0_BOOST_GAIN(CODEC_InitStruct->CODEC_Ch0BoostGain));
+    assert_param(IS_CH0_ADC_ZERO_DET_TIMEOUT(CODEC_InitStruct->CODEC_Ch0ZeroDetTimeout));
+
+    /* Enable audio IP*/
+    CODECx->CR0 |= CODEC_AUDIO_IP_EN_MSK;
+    CODECx->I2S_CTRL |= CODEC_AUDIO_RST_N_MSK;
+
+    uint16_t reg_value = 0;
+
+    /* Smaller LDO BW for LDO PSRR improvement */
+    reg_value = btaon_fast_read_safe(0x112);
+    btaon_fast_write(0x112, reg_value & (~0x6000));
+
+    /* Enable Vref RC bypass mode */
+    reg_value = btaon_fast_read_safe(0x110);
+    btaon_fast_write(0x110, reg_value & (~(BIT5)));
+
+    /* Enable ADC 1V8 LDO current limit */
+    reg_value = btaon_fast_read_safe(0x110);
+    btaon_fast_write(0x110, reg_value | BIT3);
+
+    /* Enable 1.8V LDO Vref*/
+    reg_value = btaon_fast_read_safe(0x110);
+    btaon_fast_write(0x110, reg_value | BIT6);
+
+    /* Release ADC ISO*/
+    reg_value = btaon_fast_read_safe(0x110);
+    btaon_fast_write(0x110, reg_value & (~BIT7));
+
+    /* Enable ADC 1V8 LDO */
+    reg_value = btaon_fast_read_safe(0x110);
+    btaon_fast_write(0x110, reg_value | BIT2);
+
+    /*Turn on 1.1V power cut (for audio codec(ana) digital logic)*/
+    reg_value = btaon_fast_read_safe(0x110);
+    btaon_fast_write(0x110, reg_value | BIT0);
+
+    /* Delay 8 ms */
+    platform_delay_ms(8);
+
+    /* Disable ADC 1V8 LDO current limit */
+    reg_value = btaon_fast_read_safe(0x110);
+    btaon_fast_write(0x110, reg_value & (~(BIT3)));
+
+
+    /* Power on Vref */
+    CODEC_ANA->ANA_CR1 |= CODEC_MICBST_VREF_POW_MSK;
+
+    /* MICBIAS voltage selection (default 1.8V) */
+    CODEC_ANA->ANA_CR1 &= CODEC_MICBIAS_VSET_CLR;
+    CODEC_ANA->ANA_CR1 |= (3 << CODEC_MICBIAS_VSET_POS);
+
+    /* Delay 1.5 ms */
+    platform_delay_us(1500);
+
+    /* Power on MICBIAS & chopper */
+    CODEC_ANA->ANA_CR1 |= CODEC_MICBIAS_POW_MSK;
+    CODEC_ANA->ANA_CR1 |= CODEC_MICBIAS_ENCHX_MSK;
+
+    /* Enable ckx_micbias 312.5KHz */
+    CODECx->ANA_CR1 |= CODEC_CKX_MICBIAS_EN_MSK;
+
+    /* Enable codec clock control */
+    CODECx->CLK_CR1 &= ~0x3FFF;
+    CODECx->CLK_CR1 = 0x1C40;
+    platform_delay_ms(40);
+    /* Sample Rate selection to 16kHz (default 48KHz) */
+    CODECx->CLK_CR3 &= CODEC_SAMPLE_RATE_CLR;
+    CODECx->CLK_CR3 |= 0x5;
+
+    /* AD LPF clock 10M(default 5M) */
+    CODECx->CLK_CR3 &= CODEC_AD_LPF_CLK_SEL_CLR;
+
+    /* ADC HPF FC sel */
+    CODECx->ADC0_CTRL0 &= CODEC_ADC0_DCHPF_FC_SEL_CLR;
+
+    if (CODEC_InitStruct->CODEC_Ch0MicType == CODEC_CH0_AMIC)
+    {
+        /* Enable AD/DA clock and ADC analog power */
+        CODEC_ANA->ANA_CR0 = CODEC_DAC_ADDACK_POW_MSK   | \
+                             CODEC_ADC_ANA_POW_MSK      | \
+                             CODEC_DTSDM_CLK_EN_MSK;
+
+        CODEC_ANA->ANA_CR1 = CODEC_VREF_SEL_DEFALUT_MSK         | \
+                             CODEC_MICBST_POW_MSK;
+
+        CODEC_ANA->ANA_CR1 |= CODEC_MICBST_MUTE_MIC_MSK          | \
+                              CODEC_InitStruct->CODEC_MicBIAS    | \
+                              CODEC_InitStruct->CODEC_MicBstMode | \
+                              CODEC_MICBST_VREF_POW_MSK          | \
+                              CODEC_InitStruct->CODEC_MicBstGain | \
+                              CODEC_MICBIAS_POW_MSK              | \
+                              CODEC_MICBIAS_ENCHX_MSK;
+
+        CODEC_ANA->ANA_CR2 = CODEC_MICBIAS_POWSHDT_DEFALUT_MSK  | \
+                             CODEC_MICBIAS_OCSEL_DEFALUT_MSK    | \
+                             CODEC_MICBIAS_COUNT_DEFALUT_MSK;
+
+        if (CODEC_InitStruct->CODEC_MicBstMode == MICBST_Mode_Single)
+        {
+            CODEC_ANA->ANA_CR1 &= CODEC_MICBST_ENDFL_CLR;
+            reg_value = btaon_fast_read_safe(0x110);
+            btaon_fast_write(0x110, reg_value | (BIT4));
+        }
+        else if (CODEC_InitStruct->CODEC_MicBstMode == MICBST_Mode_Differential)
+        {
+            CODEC_ANA->ANA_CR1 |= CODEC_MICBST_ENDFL_MSK;
+            reg_value = btaon_fast_read_safe(0x110);
+            btaon_fast_write(0x110, reg_value & (~BIT4));
+        }
+        CODECx->ADC0_CTRL0 |= CODEC_ADC0_DCHPF_EN_MSK           | \
+                              CODEC_AMIC_DMIC_CH0_SEL_MSK;
+        CODECx->ADC0_CTRL0 &= CODEC_ADC_CH0_AD_MUTE_CLR;
+    }
+    else if (CODEC_InitStruct->CODEC_Ch0MicType == CODEC_CH0_DMIC)
+    {
+        CODECx->CLK_CR2 = CODEC_DMIC1_CLK_EN_MSK | \
+                          CODEC_InitStruct->CODEC_DmicClock;
+        CODECx->ADC0_CTRL0 |= CODEC_ADC0_DCHPF_EN_MSK;
+        CODECx->ADC0_CTRL0 &= CODEC_AMIC_DMIC_CH0_SEL_CLR & CODEC_ADC_CH0_AD_MUTE_CLR;
+        CODECx->ADC0_CTRL0 &= CODEC_ADC0_DMIC_SRC_SEL_CLR;
+    }
+
+    /* Configure I2S parameters */
+    CODECx->I2S_CTRL |= CODEC_InitStruct->CODEC_I2SChSequence | \
+                        CODEC_InitStruct->CODEC_I2SDataWidth  | \
+                        CODEC_InitStruct->CODEC_I2SFormat;
+
+    /* Configuer mic channel 0 parameters */
+    CODECx->ADC0_CTRL0 |= CODEC_InitStruct->CODEC_Ch0BoostGain;
+    CODECx->ADC0_CTRL1 |= CODEC_InitStruct->CODEC_Ch0AdGain;
+}
+
+/**
+  * @brief  Fills each CODEC_InitStruct member with its default value.
+  * @param  CODEC_InitStruct: pointer to an CODEC_InitTypeDef structure which will be initialized.
+  * @retval None
+  */
+void CODEC_StructInit(CODEC_InitTypeDef *CODEC_InitStruct)
+{
+    /* Basic parameters section */
+    CODEC_InitStruct->CODEC_SampleRate          = SAMPLE_RATE_16KHz;
+    CODEC_InitStruct->CODEC_I2SFormat           = CODEC_I2S_DataFormat_I2S;
+    CODEC_InitStruct->CODEC_I2SDataWidth        = CODEC_I2S_DataWidth_16Bits;
+    CODEC_InitStruct->CODEC_I2SChSequence       = CODEC_I2S_CH_L_L;
+    CODEC_InitStruct->CODEC_MicBIAS             = MICBIAS_VOLTAGE_1_8;
+    CODEC_InitStruct->CODEC_MicBstMode          = MICBST_Mode_Single;
+    CODEC_InitStruct->CODEC_MicBstGain          = MICBST_Gain_0dB;
+    CODEC_InitStruct->CODEC_DmicClock           = DMIC_Clock_2500KHz;
+    /* MIC channel 0 initialization parameters section */
+    CODEC_InitStruct->CODEC_Ch0MicType          = CODEC_CH0_AMIC;
+    CODEC_InitStruct->CODEC_Ch0BoostGain        = Ch0_Boost_Gain_0dB;
+    CODEC_InitStruct->CODEC_Ch0Mute             = CODEC_CH0_UNMUTE;
+    CODEC_InitStruct->CODEC_Ch0ZeroDetTimeout   = Ch0_ADC_Zero_DetTimeout_1024_32_Sample;
+    CODEC_InitStruct->CODEC_Ch0DmicDataLatch    = DMIC_Ch0_Rising_Latch;
+    CODEC_InitStruct->CODEC_Ch0AdGain           = 0x2F;
+}
+
+/**
+  * @brief  Enable or disable mic_bias output.
+  * @param  CODECx: selected CODEC peripheral.
+  * @param  NewState: new state of MICBIAS.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @return none.
+  */
+void CODEC_MICBIASCmd(CODEC_TypeDef *CODECx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_CODEC_PERIPH(CODECx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (NewState == ENABLE)
+    {
+        if (!(CODEC_ANA->ANA_CR1 & CODEC_MICBIAS_POW_MSK))
+        {
+            /* Analog initialization in AON register */
+            CODEC_AnalogCircuitInit();
+
+            /* MICBIAS power on */
+            CODEC_ANA->ANA_CR1 |= CODEC_MICBIAS_ENCHX_MSK       | \
+                                  CODEC_MICBST_VREF_POW_MSK     | \
+                                  CODEC_MICBIAS_POW_MSK;
+
+            /* Clock enable */
+            CODECx->ANA_CR1 = CODEC_CKX_MICBIAS_EN_MSK;
+        }
+    }
+    else
+    {
+        CODEC_ANA->ANA_CR1 &= CODEC_MICBIAS_POW_CLR;
+    }
+}
+
+/**
+  * \brief  Store CODEC register values when system enter DLPS.
+  * \param  PeriReg: Specifies to select the CODEC peripheral.
+  * \param  StoreBuf: Store buffer to store CODEC register data.
+  * \return None.
+  */
+DATA_RAM_FUNCTION
+void CODEC_DLPSEnter(void *PeriReg, void *StoreBuf)
+{
+    CODECStoreReg_TypeDef *store_buf = (CODECStoreReg_TypeDef *)StoreBuf;
+
+    RCC_PeriphClockCmd(APBPeriph_CODEC, APBPeriph_CODEC_CLOCK, ENABLE);
+
+    store_buf->codec_reg[0] = CODEC->CR0;
+    store_buf->codec_reg[1] = CODEC->ADC0_CTRL0;
+    store_buf->codec_reg[2] = CODEC->ADC0_CTRL1;
+    store_buf->codec_reg[3] = CODEC->ANA_CR1;
+    store_buf->codec_reg[4] = CODEC->CLK_CR1;
+    store_buf->codec_reg[5] = CODEC->CLK_CR2;
+    store_buf->codec_reg[6] = CODEC->CLK_CR3;
+    store_buf->codec_reg[7] = CODEC->I2S_CTRL;
+}
+
+/**
+  * \brief  Restore CODEC register values when system exit DLPS.
+  * \param  PeriReg: Specifies to select the CODEC peripheral.
+  * \param  StoreBuf: Restore buffer to restore CODEC register data.
+  * \return None
+  */
+DATA_RAM_FUNCTION
+void CODEC_DLPSExit(void *PeriReg, void *StoreBuf)
+{
+    CODECStoreReg_TypeDef *store_buf = (CODECStoreReg_TypeDef *)StoreBuf;
+
+    RCC_PeriphClockCmd(APBPeriph_CODEC, APBPeriph_CODEC_CLOCK, ENABLE);
+
+    /* Initialize CODEC */
+    if ((store_buf->codec_reg[3] & 0x900) == 0x900)
+    {
+        /* Configure AMIC parameters */
+        CODEC->CR0 = store_buf->codec_reg[0];
+    }
+
+    CODEC->ADC0_CTRL0 = store_buf->codec_reg[1];
+    CODEC->ADC0_CTRL1 = store_buf->codec_reg[2];
+    CODEC->ANA_CR1    = store_buf->codec_reg[3];
+    CODEC->CLK_CR1    = store_buf->codec_reg[4];
+    CODEC->CLK_CR2    = store_buf->codec_reg[5];
+    CODEC->CLK_CR3    = store_buf->codec_reg[6];
+    CODEC->I2S_CTRL   = store_buf->codec_reg[7];
+}
+
+
+
diff --git a/bee/drivers/codec/src/device/rtl8752h/rtl876x_codec.h b/bee/drivers/codec/src/device/rtl8752h/rtl876x_codec.h
new file mode 100644
index 00000000..f3a29d7d
--- /dev/null
+++ b/bee/drivers/codec/src/device/rtl8752h/rtl876x_codec.h
@@ -0,0 +1,758 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *               Define to prevent recursive inclusion
+ *============================================================================*/
+#ifndef _RTL876X_CODEC_H_
+#define _RTL876X_CODEC_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup  IO          Peripheral Drivers
+ * \defgroup    CODEC       CODEC
+ *
+ * \brief       Manage the CODEC peripheral functions.
+ *
+ * \ingroup     IO
+ */
+
+/*============================================================================*
+ *                         Includes
+ *============================================================================*/
+#include "rtl876x.h"
+
+/*============================================================================*
+ *                         Types
+ *============================================================================*/
+/**
+ * \defgroup    CODEC_Exported_Types    CODEC Exported Types
+ *
+ * \ingroup     CODEC
+ */
+
+/**
+ * \brief       CODEC initialize parameters.
+ *
+ * \ingroup     CODEC_Exported_Types
+ */
+typedef struct
+{
+    /* Basic parameters section */
+    uint32_t CODEC_SampleRate;          /*!< Specify the sample rate.
+                                                This parameter can be a value of \ref CODEC_Sample_Rate_Definition. */
+    uint32_t CODEC_DmicClock;           /*!< Specify the dmic clock.
+                                                This parameter can be a value of \ref CODEC_DMIC_Clock_Type. */
+    uint32_t CODEC_I2SFormat;           /*!< Specify the I2S Tx/Rx format of codec port.
+                                                This parameter can be a value of \ref CODEC_I2S_Data_Format. */
+    uint32_t CODEC_I2SDataWidth;        /*!< Specify the I2S Tx/Rx data width of codec port.
+                                                This parameter can be a value of \ref CODEC_I2S_Data_Width. */
+    uint32_t CODEC_I2SChSequence;       /*!< Specify the I2S Tx/Rx channel sequence.
+                                                This parameter can be a value of \ref CODEC_I2S_CH. */
+    uint32_t CODEC_MicBIAS;             /*!< Specify the MICBIAS voltage.
+                                                This parameter can be a value of \ref CODEC_MIC_BIAS_Config. */
+    uint32_t CODEC_MicBstGain;          /*!< Specify the MICBST gain.
+                                                This parameter can be a value of \ref CODEC_MICBST_Gain. */
+    uint32_t CODEC_MicBstMode;          /*!< Specify the MICBST mode.
+                                                This parameter can be a value of \ref CODEC_MICBST_Mode. */
+
+    /* MIC channel 0 initialization parameters section */
+    uint32_t CODEC_Ch0Mute;             /*!< Specify the channel 0 dmic mute status.
+                                                This parameter can be a value of \ref CODEC_Ch0_Mute. */
+    uint32_t CODEC_Ch0MicType;          /*!< Specify the channel 0 mic type, which can be dmic or amic.
+                                                This parameter can be a value of \ref CODEC_Ch0_Mic_Type. */
+    uint32_t CODEC_Ch0DmicDataLatch;    /*!< Specify the channel 0 dmic data latch type.
+                                                This parameter can be a value of \ref CODEC_DMIC_Data_Latch_Edge. */
+    uint32_t CODEC_Ch0AdGain;           /*!< Specify the channel 0 ADC digital volume. */
+    uint32_t CODEC_Ch0BoostGain;        /*!< Specify the channel 0 boost gain.
+                                                This parameter can be a value of \ref CODEC_Ch0_Boost_Gain. */
+    uint32_t CODEC_Ch0ZeroDetTimeout;   /*!< Specify the channel 0 zero detection timeout mode control.
+                                                This parameter can be a value of \ref CODEC_Ch0_ADC_Zero_Detection_Timeout. */
+
+} CODEC_InitTypeDef;
+
+/** End of CODEC_Exported_Types
+  * \}
+  */
+
+/*============================================================================*
+ *                         Register Defines
+ *============================================================================*/
+
+/* Peripheral: CODEC */
+/* Description: CODEC register defines */
+
+/* Register: ANA_CR0 ----------------------------------------------------------*/
+/* Description: Control register 0. Offset: 0x00. Address: 0x40022000UL. */
+
+/* ANA_CR0[10]: ADC_ANA_POW. 0x1: Powen on. 0x0: Power down. */
+#define CODEC_ADC_ANA_POW_POS               (10)
+#define CODEC_ADC_ANA_POW_MSK               (0x1 << CODEC_ADC_ANA_POW_POS)
+#define CODEC_ADC_ANA_POW_CLR               (~CODEC_ADC_ANA_POW_MSK)
+/* ANA_CR0[9]: DTSDM_CLK_EN. 0x1: Powen on. 0x0: Power down. */
+#define CODEC_DTSDM_CLK_EN_POS              (9)
+#define CODEC_DTSDM_CLK_EN_MSK              (0x1 << CODEC_DTSDM_CLK_EN_POS)
+#define CODEC_DTSDM_CLK_EN_CLR              (~CODEC_DTSDM_CLK_EN_MSK)
+/* ANA_CR0[0]: DAC_ADDACK_POW. 0x1: Powen on. 0x0: Power down. */
+#define CODEC_DAC_ADDACK_POW_POS            (0)
+#define CODEC_DAC_ADDACK_POW_MSK            (0x1 << CODEC_DAC_ADDACK_POW_POS)
+#define CODEC_DAC_ADDACK_POW_CLR            (~CODEC_DAC_ADDACK_POW_MSK)
+
+/* Register: ANA_CR1 ----------------------------------------------------------*/
+/* Description: Control register 1. Offset: 0x04. Address: 0x40022004UL. */
+
+/* ANA_CR1[27:26]: VREF_SEL. */
+#define CODEC_VREF_SEL_POS                  (26)
+#define CODEC_VREF_SEL_MSK                  (0x3 << CODEC_VREF_SEL_POS)
+#define CODEC_VREF_SEL_CLR                  (~CODEC_VREF_SEL_MSK)
+#define CODEC_VREF_SEL_DEFALUT_MSK          (0x2 << CODEC_VREF_SEL_POS)
+/* ANA_CR1[25]: MICBST_POW. */
+#define CODEC_MICBST_POW_POS                (25)
+#define CODEC_MICBST_POW_MSK                (0x1 << CODEC_MICBST_POW_POS)
+#define CODEC_MICBST_POW_CLR                (~CODEC_MICBST_POW_MSK)
+/* ANA_CR1[21:20]: MICBST_MUTE. */
+#define CODEC_MICBST_MUTE_POS               (20)
+#define CODEC_MICBST_MUTE_MSK               (0x3 << CODEC_MICBST_MUTE_POS)
+#define CODEC_MICBST_MUTE_CLR               (~CODEC_MICBST_MUTE_MSK)
+#define CODEC_MICBST_MUTE_MIC_MSK           (0x2 << CODEC_MICBST_MUTE_POS)
+/* ANA_CR1[17:16]: MICBST_GAIN. */
+#define CODEC_MICBST_GAIN_POS               (16)
+#define CODEC_MICBST_GAIN_MSK               (0x3 << CODEC_MICBST_GAIN_POS)
+#define CODEC_MICBST_GAIN_CLR               (~CODEC_MICBST_GAIN_MSK)
+/* ANA_CR1[15]: MICBST_VREF_POW. */
+#define CODEC_MICBST_VREF_POW_POS           (15)
+#define CODEC_MICBST_VREF_POW_MSK           (0x1 << CODEC_MICBST_VREF_POW_POS)
+#define CODEC_MICBST_VREF_POW_CLR           (~CODEC_MICBST_VREF_POW_MSK)
+/* ANA_CR1[14]: MICBST_ENDFL. */
+#define CODEC_MICBST_ENDFL_POS              (14)
+#define CODEC_MICBST_ENDFL_MSK              (0x1 << CODEC_MICBST_ENDFL_POS)
+#define CODEC_MICBST_ENDFL_CLR              (~CODEC_MICBST_ENDFL_MSK)
+/* ANA_CR1[13:11]: MICBIAS_VSET. */
+#define CODEC_MICBIAS_VSET_POS              (11)
+#define CODEC_MICBIAS_VSET_MSK              (0x7 << CODEC_MICBIAS_VSET_POS)
+#define CODEC_MICBIAS_VSET_CLR              (~CODEC_MICBIAS_VSET_MSK)
+/* ANA_CR1[10]: MICBIAS_POW. 0x1: Powen on. 0x0: Power down. */
+#define CODEC_MICBIAS_POW_POS               (10)
+#define CODEC_MICBIAS_POW_MSK               (0x1 << CODEC_MICBIAS_POW_POS)
+#define CODEC_MICBIAS_POW_CLR               (~CODEC_MICBIAS_POW_MSK)
+/* ANA_CR1[9]: MICBIAS_ENCHX. */
+#define CODEC_MICBIAS_ENCHX_POS             (9)
+#define CODEC_MICBIAS_ENCHX_MSK             (0x1 << CODEC_MICBIAS_ENCHX_POS)
+#define CODEC_MICBIAS_ENCHX_CLR             (~CODEC_MICBIAS_ENCHX_MSK)
+
+/* Register: ANA_CR2 ----------------------------------------------------------*/
+/* Description: Control register 2. Offset: 0x08. Address: 0x40022008UL. */
+
+/* ANA_CR2[15]: MICBIAS_LIMIT. */
+#define CODEC_MICBIAS_LIMIT_POS             (15)
+#define CODEC_MICBIAS_LIMIT_MSK             (0x1 << CODEC_MICBIAS_LIMIT_POS)
+#define CODEC_MICBIAS_LIMIT_CLR             (~CODEC_MICBIAS_LIMIT_MSK)
+#define CODEC_MICBIAS_LIMIT_DEFALUT_MSK     (0)
+
+/* ANA_CR2[14]: MICBIAS_POWSHDT. */
+#define CODEC_MICBIAS_POWSHDT_POS           (14)
+#define CODEC_MICBIAS_POWSHDT_MSK           (0x1 << CODEC_MICBIAS_POWSHDT_POS)
+#define CODEC_MICBIAS_POWSHDT_CLR           (~CODEC_MICBIAS_POWSHDT_MSK)
+#define CODEC_MICBIAS_POWSHDT_DEFALUT_MSK   (0)
+
+/* ANA_CR2[13:12]: MICBIAS_OCSEL. */
+#define CODEC_MICBIAS_OCSEL_POS             (12)
+#define CODEC_MICBIAS_OCSEL_MSK             (0x3 << CODEC_MICBIAS_OCSEL_POS)
+#define CODEC_MICBIAS_OCSEL_CLR             (~CODEC_MICBIAS_OCSEL_MSK)
+#define CODEC_MICBIAS_OCSEL_DEFALUT_MSK     (0x1 << CODEC_MICBIAS_OCSEL_POS)
+
+/* ANA_CR2[11:8]: MICBIAS_COUNT. */
+#define CODEC_MICBIAS_COUNT_POS             (8)
+#define CODEC_MICBIAS_COUNT_MSK             (0xF << CODEC_MICBIAS_COUNT_POS)
+#define CODEC_MICBIAS_COUNT_CLR             (~CODEC_MICBIAS_COUNT_MSK)
+#define CODEC_MICBIAS_COUNT_DEFALUT_MSK     (0x1 << CODEC_MICBIAS_COUNT_POS)
+
+/* Register: CR0 --------------------------------------------------------------*/
+/* Description: audio Control register. Offset: 0x100. Address: 0x4002_2100UL. */
+
+/* CR0[0]: AUDIO_IP_EN. */
+#define CODEC_AUDIO_IP_EN_POS               (0)
+#define CODEC_AUDIO_IP_EN_MSK               (0x1 << CODEC_AUDIO_IP_EN_POS)
+#define CODEC_AUDIO_IP_EN_CLR               (~CODEC_AUDIO_IP_EN_MSK)
+
+/* Register: ANA_CR1 -----------------------------------------------------------*/
+/* Description: analog Control register. Offset: 0x104. Address: 0x4002_2104UL. */
+
+/* ANA_CR1[3]: CKX_MICBIAS_EN. */
+#define CODEC_CKX_MICBIAS_EN_POS           (3)
+#define CODEC_CKX_MICBIAS_EN_MSK           (0x1 << CODEC_CKX_MICBIAS_EN_POS)
+#define CODEC_CKX_MICBIAS_EN_CLR           (~CODEC_CKX_MICBIAS_EN_MSK)
+
+/* Register: CLK_CR1 ----------------------------------------------------------*/
+/* Description: clock Control register. Offset: 0x108. Address: 0x4002_2108UL. */
+
+/* CLK_CR1[12]: AD_FILTER_CH0_CLK. 0x1: Enable clock. 0x0: Disable clock. */
+#define CODEC_AD_FILTER_CH0_CLK_POS         (12)
+#define CODEC_AD_FILTER_CH0_CLK_MSK         (0x1 << CODEC_AD_FILTER_CH0_CLK_POS)
+#define CODEC_AD_FILTER_CH0_CLK_CLR         (~CODEC_AD_FILTER_CH0_CLK_MSK)
+/* CLK_CR1[11]: AD_ANA_CLK_EN. 0x1: Enable ADC analog clock. 0x0: Disable ADC analog clock. */
+#define CODEC_AD_ANA_CLK_EN_POS             (11)
+#define CODEC_AD_ANA_CLK_EN_MSK             (0x1 << CODEC_AD_ANA_CLK_EN_POS)
+#define CODEC_AD_ANA_CLK_EN_CLR             (~CODEC_AD_ANA_CLK_EN_MSK)
+/* CLK_CR1[10]: AD_FIFO_CLK_EN. 0x1: Enable ADC FIFO clock. 0x0: Disable ADC FIFO clock. */
+#define CODEC_AD_FIFO_CLK_EN_POS            (10)
+#define CODEC_AD_FIFO_CLK_EN_MSK            (0x1 << CODEC_AD_FIFO_CLK_EN_POS)
+#define CODEC_AD_FIFO_CLK_EN_CLR            (~CODEC_AD_FIFO_CLK_EN_MSK)
+/* CLK_CR1[6]: AD_CH0_CLK. 0x1: Enable clock. 0x0: Disable clock. */
+#define CODEC_AD_CH0_CLK_POS                (6)
+#define CODEC_AD_CH0_CLK_MSK                (0x1 << CODEC_AD_CH0_CLK_POS)
+#define CODEC_AD_CH0_CLK_CLR                (~CODEC_AD_CH0_CLK_MSK)
+
+/* Register: CLK_CR2 ----------------------------------------------------------*/
+/* Description: clock Control register. Offset: 0x10C. Address: 0x4002_210CUL. */
+
+/* CLK_CR2[4]: DMIC1_CLK_SRC. 0x1: 8M. 0x0: 10M. */
+#define CODEC_DMIC1_CLK_SRC_POS             (4)
+#define CODEC_DMIC1_CLK_SRC_MSK             (0x1 << CODEC_DMIC1_CLK_SRC_POS)
+#define CODEC_DMIC1_CLK_SRC_CLR             (~CODEC_DMIC1_CLK_SRC_MSK)
+/* CLK_CR2[3]: DMIC1_CLK_EN. 0x1: Enable clock. 0x0: Disable clock. */
+#define CODEC_DMIC1_CLK_EN_POS              (3)
+#define CODEC_DMIC1_CLK_EN_MSK              (0x1 << CODEC_DMIC1_CLK_EN_POS)
+#define CODEC_DMIC1_CLK_EN_CLR              (~CODEC_DMIC1_CLK_EN_MSK)
+/* CLK_CR2[2:0]: DMIC1_CLK_SEL. */
+#define CODEC_DMIC1_CLK_SEL_POS             (0)
+#define CODEC_DMIC1_CLK_SEL_MSK             (0x7 << CODEC_DMIC1_CLK_SEL_POS)
+#define CODEC_DMIC1_CLK_SEL_CLR             (~CODEC_DMIC1_CLK_SEL_MSK)
+
+/* Register: CLK_CR3 ----------------------------------------------------------*/
+/* Description: clock Control register. Offset: 0x110. Address: 0x4002_2110UL. */
+
+/* CLK_CR3[13:12]: AD_LPF_CLK_SEL. */
+#define CODEC_AD_LPF_CLK_SEL_POS            (12)
+#define CODEC_AD_LPF_CLK_SEL_MSK            (0x3 << CODEC_AD_LPF_CLK_SEL_POS)
+#define CODEC_AD_LPF_CLK_SEL_CLR            (~CODEC_AD_LPF_CLK_SEL_MSK)
+//#define CODEC_AD_LPF_CLK_SEL_DEFAULT        (~CODEC_AD_LPF_CLK_SEL_MSK)
+
+/* CLK_CR3[10]: ADC_LATCH_PHASE. */
+#define CODEC_ADC_LATCH_PHASE_POS           (10)
+#define CODEC_ADC_LATCH_PHASE_MSK           (0x1 << CODEC_ADC_LATCH_PHASE_POS)
+#define CODEC_ADC_LATCH_PHASE_CLR           (~CODEC_ADC_LATCH_PHASE_MSK)
+
+/* CLK_CR3[9]: AD_ANA_CLK_SEL. */
+#define CODEC_AD_ANA_CLK_SEL_POS            (9)
+#define CODEC_AD_ANA_CLK_SEL_MSK            (0x1 << CODEC_AD_ANA_CLK_SEL_POS)
+#define CODEC_AD_ANA_CLK_SEL_CLR            (~CODEC_AD_ANA_CLK_SEL_MSK)
+
+/* CLK_CR3[8]: ANA_CLK_RATE. */
+#define CODEC_ANA_CLK_RATE_POS              (8)
+#define CODEC_ANA_CLK_RATE_MSK              (0x1 << CODEC_ANA_CLK_RATE_POS)
+#define CODEC_ANA_CLK_RATE_CLR              (~CODEC_ANA_CLK_RATE_MSK)
+
+/* CLK_CR3[3:0]: SAMPLE_RATE. */
+#define CODEC_SAMPLE_RATE_POS               (0)
+#define CODEC_SAMPLE_RATE_MSK               (0xF << CODEC_SAMPLE_RATE_POS)
+#define CODEC_SAMPLE_RATE_CLR               (~CODEC_SAMPLE_RATE_MSK)
+
+/* Register: I2S_CTRL -------------------------------------------------------*/
+/* Description: I2S Control register. Offset: 0x11C. Address: 0x4002_211CUL. */
+
+/* I2S_CTRL[19:18]: I2S_RX_CH. */
+#define CODEC_I2S_RX_CH_POS                 (18)
+#define CODEC_I2S_RX_CH_MSK                 (0x3 << CODEC_I2S_RX_CH_POS)
+#define CODEC_I2S_RX_CH_CLR                 (~CODEC_I2S_RX_CH_MSK)
+/* I2S_CTRL[15:14]: I2S_RX_DATA_LEN. */
+#define CODEC_I2S_RX_DATA_LEN_POS           (14)
+#define CODEC_I2S_RX_DATA_LEN_MSK           (0x3 << CODEC_I2S_RX_DATA_LEN_POS)
+#define CODEC_I2S_RX_DATA_LEN_CLR           (~CODEC_I2S_RX_DATA_LEN_MSK)
+/* I2S_CTRL[11:10]: I2S_RX_DATA_FORMAT. */
+#define CODEC_I2S_RX_DATA_FORMAT_POS        (10)
+#define CODEC_I2S_RX_DATA_FORMAT_MSK        (0x3 << CODEC_I2S_RX_DATA_FORMAT_POS)
+#define CODEC_I2S_RX_DATA_FORMAT_CLR        (~CODEC_I2S_RX_DATA_FORMAT_MSK)
+/* I2S_CTRL[2]: I2S_SELF_LPBK. */
+#define CODEC_I2S_SELF_LPBK_POS             (2)
+#define CODEC_I2S_SELF_LPBK_MSK             (0x1 << CODEC_I2S_SELF_LPBK_POS)
+#define CODEC_I2S_SELF_LPBK_CLR             (~CODEC_I2S_SELF_LPBK_MSK)
+/* I2S_CTRL[1]: I2S_INV_SCLK. */
+#define CODEC_I2S_INV_SCLK_POS              (1)
+#define CODEC_I2S_INV_SCLK_MSK              (0x1 << CODEC_I2S_INV_SCLK_POS)
+#define CODEC_I2S_INV_SCLK_CLR              (~CODEC_I2S_INV_SCLK_MSK)
+/* I2S_CTRL[0]: AUDIO_RST_N. 0x1: Power on. 0x0: Power down. */
+#define CODEC_AUDIO_RST_N_POS               (0)
+#define CODEC_AUDIO_RST_N_MSK               (0x1 << CODEC_AUDIO_RST_N_POS)
+#define CODEC_AUDIO_RST_N_CLR               (~CODEC_AUDIO_RST_N_MSK)
+
+/* Register: ADC0_CTRL0 -------------------------------------------------------*/
+/* Description: ADC0 Control register. Offset: 0x120. Address: 0x4002_2120UL. */
+
+/* ADC0_CTRL0[19:17]: ADC0_DCHPF_FC_SEL. */
+#define CODEC_ADC0_DCHPF_FC_SEL_POS         (17)
+#define CODEC_ADC0_DCHPF_FC_SEL_MSK         (0x7 << CODEC_ADC0_DCHPF_FC_SEL_POS)
+#define CODEC_ADC0_DCHPF_FC_SEL_CLR         (~CODEC_ADC0_DCHPF_FC_SEL_MSK)
+
+/* ADC0_CTRL0[16]: ADC0_DCHPF_EN. 0x1: enable. 0x0: disable. */
+#define CODEC_ADC0_DCHPF_EN_POS             (16)
+#define CODEC_ADC0_DCHPF_EN_MSK             (0x1 << CODEC_ADC0_DCHPF_EN_POS)
+#define CODEC_ADC0_DCHPF_EN_CLR             (~CODEC_ADC0_DCHPF_EN_MSK)
+
+/* ADC0_CTRL0[15]: AMIC_DMIC_CH0_SEL. 0x1: ADC path. 0x0: DMIC path. */
+#define CODEC_AMIC_DMIC_CH0_SEL_POS         (15)
+#define CODEC_AMIC_DMIC_CH0_SEL_MSK         (0x1 << CODEC_AMIC_DMIC_CH0_SEL_POS)
+#define CODEC_AMIC_DMIC_CH0_SEL_CLR         (~CODEC_AMIC_DMIC_CH0_SEL_MSK)
+
+/* ADC0_CTRL0[14:13]: ADC_CH0_BOOST_GAIN. */
+#define CODEC_ADC_CH0_BOOST_GAIN_POS        (13)
+#define CODEC_ADC_CH0_BOOST_GAIN_MSK        (0x3 << CODEC_ADC_CH0_BOOST_GAIN_POS)
+#define CODEC_ADC_CH0_BOOST_GAIN_CLR        (~CODEC_ADC_CH0_BOOST_GAIN_MSK)
+
+/* ADC0_CTRL0[12]: ADC_CH0_AD_MUTE. */
+#define CODEC_ADC_CH0_AD_MUTE_POS           (12)
+#define CODEC_ADC_CH0_AD_MUTE_MSK           (0x1 << CODEC_ADC_CH0_AD_MUTE_POS)
+#define CODEC_ADC_CH0_AD_MUTE_CLR           (~CODEC_ADC_CH0_AD_MUTE_MSK)
+
+/* ADC0_CTRL0[11:10]: ADC_CH0_ZDET_TOUT. */
+#define CODEC_ADC_CH0_ZDET_TOUT_POS         (10)
+#define CODEC_ADC_CH0_ZDET_TOUT_MSK         (0x3 << CODEC_ADC_CH0_ZDET_TOUT_POS)
+#define CODEC_ADC_CH0_ZDET_TOUT_CLR         (~CODEC_ADC_CH0_ZDET_TOUT_MSK)
+
+/* ADC0_CTRL0[9:8]: ADC_CH0_ZDET_FUN. 0x1: ADC path. 0x0: DMIC path. */
+#define CODEC_ADC_CH0_ZDET_FUN_POS          (8)
+#define CODEC_ADC_CH0_ZDET_FUN_MSK          (0x3 << CODEC_ADC_CH0_ZDET_FUN_POS)
+#define CODEC_ADC_CH0_ZDET_FUN_CLR          (~CODEC_ADC_CH0_ZDET_FUN_MSK)
+#define CODEC_ADC_CH0_ZDET_FUN_DEFAULT_MSK  (0x1 << CODEC_ADC_CH0_ZDET_FUN_POS)
+
+/* ADC0_CTRL0[7:6]: ADC0_AD_LPF1ST_FC_SEL. */
+#define CODEC_ADC0_AD_LPF1ST_FC_SEL_POS     (6)
+#define CODEC_ADC0_AD_LPF1ST_FC_SEL_MSK     (0x3 << CODEC_ADC0_AD_LPF1ST_FC_SEL_POS)
+#define CODEC_ADC0_AD_LPF1ST_FC_SEL_CLR     (~CODEC_ADC0_AD_LPF1ST_FC_SEL_MSK)
+
+/* ADC0_CTRL0[5]: ADC0_AD_LPF1ST_EN. 0x1: enable. 0x0: disable. */
+#define CODEC_ADC0_AD_LPF1ST_EN_POS         (5)
+#define CODEC_ADC0_AD_LPF1ST_EN_MSK         (0x1 << CODEC_ADC0_AD_LPF1ST_EN_POS)
+#define CODEC_ADC0_AD_LPF1ST_EN_CLR         (~CODEC_ADC0_AD_LPF1ST_EN_MSK)
+
+/* ADC0_CTRL0[4]: ADC0_AD_LPF2ND_EN. 0x1: enable. 0x0: disable. */
+#define CODEC_ADC0_AD_LPF2ND_EN_POS         (4)
+#define CODEC_ADC0_AD_LPF2ND_EN_MSK         (0x1 << CODEC_ADC0_AD_LPF2ND_EN_POS)
+#define CODEC_ADC0_AD_LPF2ND_EN_CLR         (~CODEC_ADC0_AD_LPF2ND_EN_MSK)
+
+/* ADC0_CTRL0[1:0]: ADC0_DMIC_SRC_SEL. */
+#define CODEC_ADC0_DMIC_SRC_SEL_POS         (0)
+#define CODEC_ADC0_DMIC_SRC_SEL_MSK         (0x3 << CODEC_ADC0_DMIC_SRC_SEL_POS)
+#define CODEC_ADC0_DMIC_SRC_SEL_CLR         (~CODEC_ADC0_DMIC_SRC_SEL_MSK)
+
+#define CODEC_ADC0_CTRL0_REG_DEFAULT_MSK    ((0x2 << 17) | (0x01 << 16) | (0x01 << 10) | (0x02 << 8) | (0x03 <<4))
+
+/*============================================================================*
+ *                         Constants
+ *============================================================================*/
+/**
+ * \defgroup    CODEC_Exported_Constants    CODEC Exported Constants
+ *
+ * \ingroup     CODEC
+ */
+
+#define IS_CODEC_PERIPH(PERIPH) ((PERIPH) == CODEC)
+
+/**
+ * \defgroup    CODEC_MICBST_Gain CODEC MICBST Gain
+ * \{
+ * \ingroup     CODEC_Exported_Constants
+ */
+#define MICBST_Gain_0dB                     ((uint32_t)(0x0))
+#define MICBST_Gain_20dB                    ((uint32_t)(0x1 << CODEC_MICBST_GAIN_POS))
+#define MICBST_Gain_30dB                    ((uint32_t)(0x2 << CODEC_MICBST_GAIN_POS))
+#define MICBST_Gain_40dB                    ((uint32_t)(0x3 << CODEC_MICBST_GAIN_POS))
+
+#define IS_MICBST_GAIN(GAIN) (((GAIN) == MICBST_Gain_0dB) || \
+                              ((GAIN) == MICBST_Gain_20dB) || \
+                              ((GAIN) == MICBST_Gain_30dB) || \
+                              ((GAIN) == MICBST_Gain_40dB))
+/** \} */
+
+/**
+ * \defgroup    CODEC_MICBST_Mode CODEC MICBST Mode
+ * \{
+ * \ingroup     CODEC_Exported_Constants
+ */
+#define MICBST_Mode_Single                  ((uint32_t)(0x0))
+#define MICBST_Mode_Differential            ((uint32_t)CODEC_MICBST_ENDFL_MSK)
+
+#define IS_MICBST_MODE(MODE) (((MODE) == MICBST_Mode_Single) || \
+                              ((MODE) == MICBST_Mode_Differential))
+/** \} */
+
+/**
+ * \defgroup    CODEC_MIC_BIAS_Config CODEC MIC BIAS Config
+ * \{
+ * \ingroup     CODEC_Exported_Constants
+ */
+#define MICBIAS_VOLTAGE_1_507               ((uint32_t)(0x00))
+#define MICBIAS_VOLTAGE_1_62                ((uint32_t)(0x01 << CODEC_MICBIAS_VSET_POS))
+#define MICBIAS_VOLTAGE_1_705               ((uint32_t)(0x02 << CODEC_MICBIAS_VSET_POS))
+#define MICBIAS_VOLTAGE_1_8                 ((uint32_t)(0x03 << CODEC_MICBIAS_VSET_POS))
+#define MICBIAS_VOLTAGE_1_906               ((uint32_t)(0x04 << CODEC_MICBIAS_VSET_POS))
+#define MICBIAS_VOLTAGE_2_025               ((uint32_t)(0x05 << CODEC_MICBIAS_VSET_POS))
+#define MICBIAS_VOLTAGE_2_16                ((uint32_t)(0x06 << CODEC_MICBIAS_VSET_POS))
+#define MICBIAS_VOLTAGE_2_314               ((uint32_t)(0x07 << CODEC_MICBIAS_VSET_POS))
+
+#define IS_MICBIAS_CONFIG(CONFIG) (((CONFIG) == MICBIAS_VOLTAGE_1_507) || ((CONFIG) == MICBIAS_VOLTAGE_1_62) || \
+                                   ((CONFIG) == MICBIAS_VOLTAGE_1_705) || ((CONFIG) == MICBIAS_VOLTAGE_1_8) || \
+                                   ((CONFIG) == MICBIAS_VOLTAGE_1_906) || ((CONFIG) == MICBIAS_VOLTAGE_2_025) || \
+                                   ((CONFIG) == MICBIAS_VOLTAGE_2_16) || ((CONFIG) == MICBIAS_VOLTAGE_2_314))
+/** \} */
+
+/**
+ * \defgroup    CODEC_Sample_Rate_Definition  CODEC Sample Rate Definition
+ * \{
+ * \ingroup     CODEC_Exported_Constants
+ */
+#define SAMPLE_RATE_16KHz                   ((uint32_t)(0x05 << CODEC_SAMPLE_RATE_POS))
+#define SAMPLE_RATE_8KHz                    ((uint32_t)(0x07 << CODEC_SAMPLE_RATE_POS))
+
+#define IS_SAMPLE_RATE(RATE) (((RATE) == SAMPLE_RATE_16KHz) || ((RATE) == SAMPLE_RATE_8KHz))
+/** \} */
+
+/**
+ * \defgroup    CODEC_I2S_CH CODEC I2S CH
+ * \{
+ * \ingroup     CODEC_Exported_Constants
+ */
+#define CODEC_I2S_CH_L_R                    ((uint32_t)(0x00))
+#define CODEC_I2S_CH_R_L                    ((uint32_t)(0x01 << CODEC_I2S_RX_CH_POS))
+#define CODEC_I2S_CH_L_L                    ((uint32_t)(0x02 << CODEC_I2S_RX_CH_POS))
+#define CODEC_I2S_CH_R_R                    ((uint32_t)(0x03 << CODEC_I2S_RX_CH_POS))
+
+#define IS_CODEC_I2S_CH(CH) (((CH) == CODEC_I2S_CH_L_R) || \
+                             ((CH) == CODEC_I2S_CH_R_L) || \
+                             ((CH) == CODEC_I2S_CH_L_L) || \
+                             ((CH) == CODEC_I2S_CH_R_R))
+/** \} */
+
+/**
+ * \defgroup    CODEC_I2S_Data_Width CODEC I2S Data Width
+ * \{
+ * \ingroup     CODEC_Exported_Constants
+ */
+#define CODEC_I2S_DataWidth_16Bits          ((uint32_t)(0x00))
+#define CODEC_I2S_DataWidth_24Bits          ((uint32_t)(0x02 << CODEC_I2S_RX_DATA_LEN_POS))
+#define CODEC_I2S_DataWidth_8Bits           ((uint32_t)(0x03 << CODEC_I2S_RX_DATA_LEN_POS))
+
+#define IS_CODEC_I2S_DATA_WIDTH(WIDTH) (((WIDTH) == CODEC_I2S_DataWidth_16Bits) || \
+                                        ((WIDTH) == CODEC_I2S_DataWidth_24Bits) || \
+                                        ((WIDTH) == CODEC_I2S_DataWidth_8Bits))
+/** \} */
+
+/**
+ * \defgroup    CODEC_I2S_Data_Format CODEC I2S Data Format
+ * \{
+ * \ingroup     CODEC_Exported_Constants
+ */
+#define CODEC_I2S_DataFormat_I2S            ((uint32_t)(0x00))
+#define CODEC_I2S_DataFormat_LeftJustified  ((uint32_t)(0x01 << CODEC_I2S_RX_DATA_FORMAT_POS))
+#define CODEC_I2S_DataFormat_PCM_A          ((uint32_t)(0x02 << CODEC_I2S_RX_DATA_FORMAT_POS))
+#define CODEC_I2S_DataFormat_PCM_B          ((uint32_t)(0x03 << CODEC_I2S_RX_DATA_FORMAT_POS))
+
+#define IS_CODEC_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == CODEC_I2S_DataFormat_I2S) || \
+                                          ((FORMAT) == CODEC_I2S_DataFormat_LeftJustified) || \
+                                          ((FORMAT) == CODEC_I2S_DataFormat_PCM_A) || \
+                                          ((FORMAT) == CODEC_I2S_DataFormat_PCM_B))
+/** \} */
+
+/**
+ * \defgroup    CODEC_DMIC_Clock_Type CODEC DMIC Clock Type
+ * \{
+ * \ingroup     CODEC_Exported_Constants
+ */
+#define DMIC_Clock_5MHz                     ((uint32_t)(0x0))
+#define DMIC_Clock_2500KHz                  ((uint32_t)(0x01 << CODEC_DMIC1_CLK_SEL_POS))
+#define DMIC_Clock_1250KHz                  ((uint32_t)(0x02 << CODEC_DMIC1_CLK_SEL_POS))
+#define DMIC_Clock_625KHz                   ((uint32_t)(0x03 << CODEC_DMIC1_CLK_SEL_POS))
+#define DMIC_Clock_312500Hz                 ((uint32_t)(0x04 << CODEC_DMIC1_CLK_SEL_POS))
+
+#define IS_CODEC_DMIC_CLOCK(CLOCK) (((CLOCK) == DMIC_Clock_5MHz) || ((CLOCK) == DMIC_Clock_2500KHz) || \
+                                    ((CLOCK) == DMIC_Clock_1250KHz) || ((CLOCK) == DMIC_Clock_625KHz) || \
+                                    ((CLOCK) == DMIC_Clock_312500Hz))
+/** \} */
+
+/**
+ * \defgroup    CODEC_Ch0_Mic_Type CODEC Ch0 Mic Type
+ * \{
+ * \ingroup     CODEC_Exported_Constants
+ */
+#define CODEC_CH0_AMIC                      (CODEC_AMIC_DMIC_CH0_SEL_MSK)
+#define CODEC_CH0_DMIC                      (0)
+
+#define IS_CODEC_CH0_MIC_TYPE(TYPE) (((TYPE) == CODEC_CH0_AMIC) || ((TYPE) == CODEC_CH0_DMIC))
+/** \} */
+
+/**
+ * \defgroup    CODEC_Ch0_Boost_Gain CODEC Ch0 Boost Gain
+ * \{
+ * \ingroup     CODEC_Exported_Constants
+ */
+#define Ch0_Boost_Gain_0dB                  ((uint32_t)(0x0))
+#define Ch0_Boost_Gain_12dB                 ((uint32_t)(0x1 << CODEC_ADC_CH0_BOOST_GAIN_POS))
+#define Ch0_Boost_Gain_24dB                 ((uint32_t)(0x2 << CODEC_ADC_CH0_BOOST_GAIN_POS))
+#define Ch0_Boost_Gain_36dB                 ((uint32_t)(0x3 << CODEC_ADC_CH0_BOOST_GAIN_POS))
+
+#define IS_CH0_BOOST_GAIN(GAIN) (((GAIN) == Ch0_Boost_Gain_0dB) || \
+                                 ((GAIN) == Ch0_Boost_Gain_12dB) || \
+                                 ((GAIN) == Ch0_Boost_Gain_24dB) || \
+                                 ((GAIN) == Ch0_Boost_Gain_36dB))
+/** \} */
+
+/**
+ * \defgroup    CODEC_Ch0_Mute CODEC Ch0 Mute
+ * \{
+ * \ingroup     CODEC_Exported_Constants
+ */
+#define CODEC_CH0_MUTE                      (CODEC_ADC_CH0_AD_MUTE_MSK)
+#define CODEC_CH0_UNMUTE                    (0)
+
+#define IS_CODEC_CH0_MIC_MUTE(MUTE) (((MUTE) == CODEC_CH0_MUTE) || ((MUTE) == CODEC_CH0_UNMUTE))
+/** \} */
+
+/**
+ * \defgroup    CODEC_Ch0_ADC_Zero_Detection_Timeout CODEC Ch0 ADC Zero Detection Timeout
+ * \{
+ * \ingroup     CODEC_Exported_Constants
+ */
+#define Ch0_ADC_Zero_DetTimeout_1024_16_Sample       ((uint32_t)(0x00))
+#define Ch0_ADC_Zero_DetTimeout_1024_32_Sample       ((uint32_t)(0x01 << CODEC_ADC_CH0_ZDET_TOUT_POS))
+#define Ch0_ADC_Zero_DetTimeout_1024_64_Sample       ((uint32_t)(0x02 << CODEC_ADC_CH0_ZDET_TOUT_POS))
+#define Ch0_ADC_Zero_DetTimeout_64_Sample            ((uint32_t)(0x03 << CODEC_ADC_CH0_ZDET_TOUT_POS))
+
+#define IS_CH0_ADC_ZERO_DET_TIMEOUT(TIMEOUT) (((TIMEOUT) == Ch0_ADC_Zero_DetTimeout_1024_16_Sample) || \
+                                              ((TIMEOUT) == Ch0_ADC_Zero_DetTimeout_1024_32_Sample) || \
+                                              ((TIMEOUT) == Ch0_ADC_Zero_DetTimeout_1024_64_Sample) || \
+                                              ((TIMEOUT) == Ch0_ADC_Zero_DetTimeout_64_Sample))
+/** \} */
+
+/**
+ * \defgroup    CODEC_DMIC_Data_Latch_Edge CODEC DMIC Data Latch Edge
+ * \{
+ * \ingroup     CODEC_Exported_Constants
+ */
+#define DMIC_Ch0_Falling_Latch              ((uint32_t)(0x01 << CODEC_ADC0_DMIC_SRC_SEL_MSK))
+#define DMIC_Ch0_Rising_Latch               ((uint32_t)(0x00))
+
+#define IS_DMIC_CH0_LATCH_EDGE(EDGE) (((EDGE) == DMIC_Ch0_Rising_Latch) || ((EDGE) == DMIC_Ch0_Falling_Latch))
+/** \} */
+
+/**
+ * \defgroup    CODEC_Ad_Gain Codec Ad Gain
+ * \{
+ * \ingroup     CODEC_Exported_Constants
+ */
+#define IS_AD_GAIN(GAIN) (((GAIN)<= 0x7F))
+/** \} */
+
+/**
+ * \defgroup    CODEC_Da_Gain Codec Da Gain
+ * \{
+ * \ingroup     CODEC_Exported_Constants
+ */
+#define IS_DA_GAIN(GAIN) (((GAIN)<= 0xFF))
+/** \} */
+
+/** End of CODEC_Exported_Constants
+  * \}
+  */
+
+/*============================================================================*
+ *                         Functions
+ *============================================================================*/
+/**
+ * \defgroup    CODEC_Exported_Functions CODEC Exported Functions
+ * \{
+ * \ingroup     CODEC
+ */
+
+/**
+ * \brief     Initialize the CODEC analog circuit.
+ * \return    None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * CODEC_AnalogCircuitInit();
+ * \endcode
+ *
+ */
+void CODEC_AnalogCircuitInit(void);
+
+/**
+ * \brief   Deinitialize the CODEC peripheral registers to their default reset values (turn off CODEC clock).
+ * \param[in] CODECx: CODEC peripheral selected.
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_codec_init(void)
+ * {
+ *     CODEC_DeInit(CODEC);
+ * }
+ * \endcode
+ *
+ */
+void CODEC_DeInit(CODEC_TypeDef *CODECx);
+
+/**
+ * \brief   Initialize the CODEC peripheral according to the specified
+ *          parameters in the CODEC_InitStruct.
+ * \param[in] CODECx: CODEC peripheral selected.
+ * \param[in] CODEC_InitStruct: Pointer to a CODEC_InitTypeDef structure that
+ *            contains the configuration information for the specified CODEC peripheral.
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_codec_init(void)
+ * {
+ *     RCC_PeriphClockCmd(APBPeriph_CODEC, APBPeriph_CODEC_CLOCK, ENABLE);
+ *
+ *     CODEC_InitTypeDef CODEC_InitStruct;
+
+ *     CODEC_StructInit(&CODEC_InitStruct);
+ *     CODEC_InitStruct.CODEC_Ch0MicType       = CODEC_CH0_AMIC;
+ *     CODEC_InitStruct.CODEC_MicBstMode       = MICBST_Mode_Differential;
+ *     CODEC_InitStruct.CODEC_SampleRate       = SAMPLE_RATE_16KHz;
+ *     CODEC_InitStruct.CODEC_I2SFormat        = CODEC_I2S_DataFormat_I2S;
+ *     CODEC_InitStruct.CODEC_I2SDataWidth     = CODEC_I2S_DataWidth_16Bits;
+ *     CODEC_Init(CODEC, &CODEC_InitStruct);
+ * }
+ * \endcode
+ *
+ */
+void CODEC_Init(CODEC_TypeDef *CODECx, CODEC_InitTypeDef *CODEC_InitStruct);
+
+/**
+ * \brief   Fill each CODEC_InitStruct member with its default value.
+ * \param[in] CODEC_InitStruct: Pointer to a CODEC_InitTypeDef structure which will be initialized.
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_codec_init(void)
+ * {
+ *     RCC_PeriphClockCmd(APBPeriph_CODEC, APBPeriph_CODEC_CLOCK, ENABLE);
+ *
+ *     CODEC_InitTypeDef CODEC_InitStruct;
+
+ *     CODEC_StructInit(&CODEC_InitStruct);
+ *     CODEC_InitStruct.CODEC_Ch0MicType       = CODEC_CH0_AMIC;
+ *     CODEC_InitStruct.CODEC_MicBstMode       = MICBST_Mode_Differential;
+ *     CODEC_InitStruct.CODEC_SampleRate       = SAMPLE_RATE_16KHz;
+ *     CODEC_InitStruct.CODEC_I2SFormat        = CODEC_I2S_DataFormat_I2S;
+ *     CODEC_InitStruct.CODEC_I2SDataWidth     = CODEC_I2S_DataWidth_16Bits;
+ *     CODEC_Init(CODEC, &CODEC_InitStruct);
+ * }
+ * \endcode
+ *
+ */
+void CODEC_StructInit(CODEC_InitTypeDef *CODEC_InitStruct);
+
+/**
+ * \brief  Enable or disable mic_bias output.
+ * \param[in] CODECx: CODEC peripheral selected.
+ * \param[in] NewState: New state of MICBIAS.
+ *      This parameter can be: ENABLE or DISABLE.
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void codec_demo(void)
+ * {
+ *     CODEC_MICBIASCmd(CODEC, ENABLE);
+ * }
+ * \endcode
+ *
+ */
+void CODEC_MICBIASCmd(CODEC_TypeDef *CODECx, FunctionalState NewState);
+
+/**
+ * \brief  Reset CODEC.
+ * \param[in] CODECx: CODEC peripheral selected.
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void codec_demo(void)
+ * {
+ *     CODEC_Reset(CODEC);
+ * }
+ * \endcode
+ *
+ */
+__STATIC_INLINE void CODEC_Reset(CODEC_TypeDef *CODECx)
+{
+    /* Check the parameters */
+    assert_param(IS_CODEC_PERIPH(CODECx));
+
+    /* CODEC IP reset */
+    CODECx->CR0 &= CODEC_AUDIO_IP_EN_CLR;
+    CODECx->CR0 = CODEC_AUDIO_IP_EN_MSK;
+}
+
+/**
+ * \brief   Config MIC BIAS Vref voltage.
+ * \param[in] CODECx: CODEC peripheral selected.
+ * \param[in] data: New value of MIC BIAS.
+ *   This parameter can be one of the following values, which refer to \ref CODEC_MIC_BIAS_Config.
+ *     \arg MICBIAS_VOLTAGE_1_507: Vref voltage is 1.507V.
+ *     \arg MICBIAS_VOLTAGE_1_62:  Vref voltage is 1.62V.
+ *     \arg MICBIAS_VOLTAGE_1_705: Vref voltage is 1.705V.
+ *     \arg MICBIAS_VOLTAGE_1_8: Vref voltage is 1.8V.
+ *     \arg MICBIAS_VOLTAGE_1_906: Vref voltage is 1.906V.
+ *     \arg MICBIAS_VOLTAGE_2_025:  Vref voltage is 2.025V.
+ *     \arg MICBIAS_VOLTAGE_2_16: Vref voltage is 2.16V.
+ *     \arg MICBIAS_VOLTAGE_2_314: Vref voltage is 2.314V.
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void codec_demo(void)
+ * {
+ *     CODEC_SetMICBIAS(CODEC, MICBIAS_VOLTAGE_1_507);
+ * }
+ * \endcode
+ *
+ */
+__STATIC_INLINE void CODEC_SetMICBIAS(CODEC_TypeDef *CODECx,  uint16_t data)
+
+{
+    /* Check the parameters */
+    assert_param(IS_CODEC_PERIPH(CODECx));
+    assert_param(IS_MICBIAS_CONFIG(data));
+
+    CODEC_ANA->ANA_CR1 &= CODEC_MICBIAS_POW_CLR;
+    CODEC_ANA->ANA_CR1 &= CODEC_MICBIAS_VSET_CLR;
+    CODEC_ANA->ANA_CR1 |= data;
+}
+
+/** End of CODEC_Exported_Functions
+  * \}
+  */
+
+/** End of CODEC
+  * \}
+  */
+
+typedef struct
+{
+    uint32_t codec_reg[8];
+} CODECStoreReg_TypeDef;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTL876X_CODEC_H_ */
+
diff --git a/bee/drivers/codec/src/device/rtl87x2g/rtl_codec.c b/bee/drivers/codec/src/device/rtl87x2g/rtl_codec.c
new file mode 100644
index 00000000..8dfc01ac
--- /dev/null
+++ b/bee/drivers/codec/src/device/rtl87x2g/rtl_codec.c
@@ -0,0 +1,497 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *                        Header Files
+ *============================================================================*/
+#include "rtl_codec.h"
+#include "rtl_rcc.h"
+#include "utils.h"
+
+/*============================================================================*
+ *                          Private Macros
+ *============================================================================*/
+#define AUXADC_AON_REG0X1B90              ((AON_NS_REG0X_LDO_TYPE *)0x40001B90UL)
+#define LPC_AON_AUXADC                      ((AON_NS_REG0X_SD_TYPE *)0x40001B98UL)
+#define PERI_ON_ADC_CLOCK_CTRL               *((volatile uint32_t *)0x4000231CUL)
+
+extern void force_vddcore_1v2_for_auxadc(bool enable);
+/*============================================================================*
+ *                           Public Functions
+ *============================================================================*/
+/**
+  * \brief  Initialize the CODEC analog registers in AON area.
+  * \param  None.
+  * \return None
+  */
+void CODEC_AnalogCircuitInit(void)
+{
+    /*Added to stabilize the power supply!*/
+    /* set to LDO mode */
+    force_vddcore_1v2_for_auxadc(true);
+    AUXADC_AON_REG0X1B90->hw_pd = 0x0;
+    AUXADC_AON_REG0X1B90->anapar_pow_ad_0 = 0x1;
+    platform_delay_us(10);
+    AUXADC_AON_REG0X1B90->EN_ILIMIT = 0x1;
+    AUXADC_AON_REG0X1B90->LDOBW  = 0x0;
+    AUXADC_AON_REG0X1B90->Power = 0x0;
+    AUXADC_AON_REG0X1B90->anapar_pow_ad_2 = 0x1;
+    AUXADC_AON_REG0X1B90->REG_LDO_TUNE_6_0 = 0x57; //  7'b1010111
+    AUXADC_AON_REG0X1B90->SELLDO = 0x1;
+    platform_delay_us(10);
+    AUXADC_AON_REG0X1B90->anapar_pow_ad_1 = 0x1;
+
+    if (AUXADC_AON_REG0X1B90->EN_ILIMIT == 0x0)
+    {
+        platform_delay_us(20);
+    }
+    else
+    {
+        platform_delay_us(15);
+        AUXADC_AON_REG0X1B90->EN_ILIMIT = 0x0;
+    }
+    platform_delay_us(2);
+
+}
+
+/**
+  * \brief  Deinitialize the CODEC analog registers in AON area.
+  * \param  None.
+  * \return None
+  */
+static void CODEC_AnalogCircuitDeInit(void)
+{
+    uint32_t adc_clk_en = (PERI_ON_ADC_CLOCK_CTRL & BIT1) >> 1;
+    if (LPC_AON_AUXADC->POW_SD_H != 1 && adc_clk_en != 1)
+    {
+        AUXADC_AON_REG0X1B90->anapar_pow_ad_2 = 0x0;
+        AUXADC_AON_REG0X1B90->anapar_pow_ad_0 = 0x0;
+        AUXADC_AON_REG0X1B90->anapar_pow_ad_1 = 0x0;
+        AUXADC_AON_REG0X1B90->hw_pd  = 0x1;
+    }
+    force_vddcore_1v2_for_auxadc(false);
+
+}
+
+/**
+  * \brief  Deinitializes the CODEC peripheral registers to their default reset values(turn off CODEC clock).
+  * \param  CODECx: selected CODEC peripheral.
+  * \return None
+  */
+void CODEC_DeInit(CODEC_TypeDef *CODECx)
+{
+    /* Check the parameters */
+    assert_param(IS_CODEC_PERIPH(CODECx));
+
+    RCC_PeriphClockCmd(APBPeriph_CODEC, APBPeriph_CODEC_CLOCK, DISABLE);
+
+    CODEC_AnalogCircuitDeInit();
+}
+
+
+/**
+  * \brief Initializes the CODEC peripheral according to the specified
+  *   parameters in the CODEC_InitStruct
+  * \param  CODECx: selected CODEC peripheral.
+  * \param  CODEC_InitStruct: pointer to a CODEC_InitTypeDef structure that
+  *   contains the configuration information for the specified CODEC peripheral
+  * \return None
+  */
+void CODEC_Init(CODEC_TypeDef *CODECx, CODEC_InitTypeDef *CODEC_InitStruct)
+{
+    /* Check the parameters */
+    /* MIC initialization parameters for input */
+    assert_param(IS_CODEC_PERIPH(CODECx));
+    assert_param(IS_SAMPLE_RATE(CODEC_InitStruct->CODEC_SampleRate));
+    assert_param(IS_CODEC_I2S_DATA_FORMAT(CODEC_InitStruct->CODEC_I2SFormat));
+    assert_param(IS_CODEC_I2S_DATA_WIDTH(CODEC_InitStruct->CODEC_I2SDataWidth));
+    assert_param(IS_MICBIAS_CONFIG(CODEC_InitStruct->CODEC_MicBIAS));
+    assert_param(IS_MICBST_MODE(CODEC_InitStruct->CODEC_MicBstMode));
+    assert_param(IS_MICBST_GAIN(CODEC_InitStruct->CODEC_MicBstGain));
+    assert_param(IS_CODEC_DMIC_CLOCK(CODEC_InitStruct->CODEC_DmicClock));
+    /* MIC channel 0 initialization parameters */
+    assert_param(IS_CODEC_CH0_MIC_MUTE(CODEC_InitStruct->CODEC_Ch0Mute));
+    assert_param(IS_CODEC_CH0_MIC_TYPE(CODEC_InitStruct->CODEC_Ch0MicType));
+    assert_param(IS_DMIC_CH0_LATCH_EDGE(CODEC_InitStruct->CODEC_Ch0DmicDataLatch));
+    assert_param(IS_AD_GAIN(CODEC_InitStruct->CODEC_Ch0AdGain));
+    /* MIC channel 1 initialization parameters */
+    assert_param(IS_CODEC_CH1_MIC_MUTE(CODEC_InitStruct->CODEC_Ch1Mute));
+    assert_param(IS_CODEC_CH1_MIC_TYPE(CODEC_InitStruct->CODEC_Ch1MicType));
+    assert_param(IS_DMIC_CH1_LATCH_EDGE(CODEC_InitStruct->CODEC_Ch1DmicDataLatch));
+    assert_param(IS_AD_GAIN(CODEC_InitStruct->CODEC_Ch1AdGain));
+    /* PDM initialization parameters */
+    assert_param(IS_DAC_MUTE(CODEC_InitStruct->CODEC_DaMute));
+    assert_param(IS_DA_GAIN(CODEC_InitStruct->CODEC_DaGain));
+
+    CODEC_ANA_00_BUS_t codec_0x000 = {.d32 = CODEC_ANA->CODEC_ANA_00_BUS};
+    CODEC_ANA_01_BUS_t codec_0x004 = {.d32 = CODEC_ANA->CODEC_ANA_01_BUS};
+    CODEC_ANA_02_BUS_t codec_0x008 = {.d32 = CODEC_ANA->CODEC_ANA_02_BUS};
+    CODEC_ANA_03_BUS_t codec_0x00C = {.d32 = CODEC_ANA->CODEC_ANA_03_BUS};
+
+    AUDIO_CONTROL_0_t codec_0x100 = {.d32 = CODEC->AUDIO_CONTROL_0};
+    AUDIO_CONTROL_1_t codec_0x104 = {.d32 = CODEC->AUDIO_CONTROL_1};
+    CLOCK_CONTROL_1_t codec_0x108 = {.d32 = CODEC->CLOCK_CONTROL_1};
+    CLOCK_CONTROL_3_t codec_0x110 = {.d32 = CODEC->CLOCK_CONTROL_3};
+    CLOCK_CONTROL_4_t codec_0x114 = {.d32 = CODEC->CLOCK_CONTROL_4};
+    CLOCK_CONTROL_7_t codec_0x118 = {.d32 = CODEC->CLOCK_CONTROL_7};
+    CLOCK_CONTROL_5_t codec_0x11C = {.d32 = CODEC->CLOCK_CONTROL_5};
+
+    I2S_0_CONTROL_t codec_0x148 = {.d32 = CODEC->I2S_0_CONTROL};
+
+    ADC_0_CONTROL_0_t codec_0x164 = {.d32 = CODEC->ADC_0_CONTROL_0};
+    ADC_0_CONTROL_1_t codec_0x168 = {.d32 = CODEC->ADC_0_CONTROL_1};
+    ADC_1_CONTROL_0_t codec_0x16C = {.d32 = CODEC->ADC_1_CONTROL_0};
+    ADC_1_CONTROL_1_t codec_0x170 = {.d32 = CODEC->ADC_1_CONTROL_1};
+
+    DAC_L_CONTROL_0_t codec_0x194 = {.d32 = CODEC->DAC_L_CONTROL_0};
+    DAC_L_CONTROL_1_t codec_0x198 = {.d32 = CODEC->DAC_L_CONTROL_1};
+
+    /* Enable audio IP*/
+    codec_0x100.b.audio_ip_en = ENABLE;
+
+    /* Clock configuration */
+    codec_0x108.b.ad_ana_clk_en      = ENABLE;
+    codec_0x108.b.ad_fifo_en      = ENABLE;
+
+    if (CODEC_InitStruct->CODEC_Ch0Mute == CODEC_UNMUTE)
+    {
+        codec_0x108.b.ad_0_en           = ENABLE;
+        codec_0x108.b.ad_ana_0_en       = ENABLE;
+
+    }
+    if (CODEC_InitStruct->CODEC_Ch1Mute == CODEC_UNMUTE)
+    {
+        codec_0x108.b.ad_1_en           = ENABLE;
+        codec_0x108.b.ad_ana_1_en       = ENABLE;
+    }
+    if (CODEC_InitStruct->CODEC_DaMute != CODEC_MUTE)
+    {
+        codec_0x108.b.da_ana_clk_en = ENABLE;
+        codec_0x108.b.da_fifo_en = ENABLE;  //dac fifo clock control
+        codec_0x108.b.da_l_en = ENABLE;
+        codec_0x108.b.mod_l_en = ENABLE;
+        codec_0x118.b.dac_fs_src_sel  = CODEC_InitStruct->CODEC_DaSampleRateSrc;
+        /* enable DAC power*/
+        codec_0x00C.b.CODEC_DAC_POW = 0x1;
+        codec_0x00C.b.CODEC_DAC_CK_POW = 0x1;
+
+    }
+    codec_0x11C.b.ad_asrc_en = 1;
+    codec_0x11C.b.da_asrc_en = 1;
+
+    /* DMIC clock configuration */
+    if (((CODEC_InitStruct->CODEC_Ch0Mute   == CODEC_UNMUTE) && \
+         (CODEC_InitStruct->CODEC_Ch0MicType == CODEC_CH_DMIC))  || \
+        ((CODEC_InitStruct->CODEC_Ch1Mute   == CODEC_UNMUTE) && \
+         (CODEC_InitStruct->CODEC_Ch1MicType == CODEC_CH_DMIC)))
+    {
+
+        codec_0x110.b.dmic1_clk_en = 0x1;
+        codec_0x110.b.dmic1_clk_sel = CODEC_InitStruct->CODEC_DmicClock;
+        codec_0x110.b.dmic1_src_clk_sel = 0x0; //digital MIC 1 clock soruce selection 1: 8MHz 0:10MHz
+        codec_0x118.b.adc_fs_src_sel  = CODEC_InitStruct->CODEC_AdSampleRateSrc;
+    }
+    /* Sample rate section */
+    codec_0x114.b.sample_rate_0        = CODEC_InitStruct->CODEC_SampleRate0;
+    codec_0x114.b.sample_rate_1        = CODEC_InitStruct->CODEC_SampleRate1;
+
+    /* MICBIAS Setting On*/
+    codec_0x004.b.MICBIAS_ENCHX = 0x1;
+    codec_0x004.b.MICBIAS_VSET = CODEC_InitStruct->CODEC_MicBIAS;
+    codec_0x104.b.ckx_micbias_en = 0x1;
+    codec_0x004.b.MICBIAS_POW = 0x1;
+
+    codec_0x008.b.MICBIAS_ILIMIT = 0x0;
+    codec_0x008.b.MICBIAS_POWSHDT = 0x0;
+    codec_0x008.b.MICBIAS_OCSEL = 0x1;
+    codec_0x008.b.MICBIAS_COUNT = 0x1;
+    codec_0x004.b.VREF_POW = 0x1;
+    /* Analog initialization */
+    if (((CODEC_InitStruct->CODEC_Ch0Mute   == CODEC_UNMUTE) && \
+         (CODEC_InitStruct->CODEC_Ch0MicType == CODEC_CH_AMIC))  || \
+        ((CODEC_InitStruct->CODEC_Ch1Mute   == CODEC_UNMUTE) && \
+         (CODEC_InitStruct->CODEC_Ch1MicType == CODEC_CH_AMIC)) || \
+        (CODEC_InitStruct->CODEC_DaMute   == CODEC_UNMUTE))
+    {
+        /* Analog initialization in AON register */
+        CODEC_AnalogCircuitInit();
+
+        /* Enable AD/DA clock and ADC analog power */
+        codec_0x000.b.DAC_ADDACK_POW = 0x1;
+        codec_0x000.b.DTSDM_CKXEN = 0x1;
+        codec_0x000.b.DTSDM_POW_L = 0x1;
+
+        codec_0x004.b.MICBST_GSELL = CODEC_InitStruct->CODEC_MicBstGain;
+        codec_0x004.b.MICBST_ENDFL = CODEC_InitStruct->CODEC_MicBstMode;
+        codec_0x004.b.VREF_VREFSEL = 0x2;
+        codec_0x004.b.MICBST_POW = 0x1;
+        codec_0x004.b.MICBST_MUTE_L = 0x2;
+
+
+        /* Clock enable */
+
+        codec_0x118.b.adc_fs_src_sel  = CODEC_InitStruct->CODEC_AdSampleRateSrc;
+        codec_0x118.b.dac_fs_src_sel  = CODEC_InitStruct->CODEC_DaSampleRateSrc;
+
+    }
+    /*default config*/
+    codec_0x104.b.sel_bb_ck_depop =
+        0x01; // 2'b00:40MHz/1024  2'b01:40MHz/2048 2'b10:40MHz/4096 2'b11:40MHz/8192
+    codec_0x104.b.pdm_ch_swap =
+        0x2;  // PDM DATA channel SWAP 2'b00: L/L 2'b01: L/R 2'b10: R/L 2'b11: R/R
+    codec_0x104.b.pdm_data_phase_sel = 0x1;  //add delay in PDM DATA
+    codec_0x104.b.pdm_gain_shift_en = 0x1;  //1: backoff 6 dB to prevent overloading for PDM
+    codec_0x104.b.i2s_data_rnd_en = 0x1;  //i2s data with rounding
+
+    /* Configure I2S parameters */
+    codec_0x148.b.i2s_0_rst_n = 1;
+    codec_0x148.b.i2s_0_inv_sclk = 0;
+    codec_0x148.b.i2s_0_self_lpbk_en = 0;
+    codec_0x148.b.i2s_0_same_lrc_en = CODEC_InitStruct->CODEC_I2SSameLrcEn;
+    codec_0x148.b.i2s_0_data_format_sel_tx = CODEC_InitStruct->CODEC_I2SFormat;
+    codec_0x148.b.i2s_0_data_format_sel_rx = CODEC_InitStruct->CODEC_I2SFormat;
+    codec_0x148.b.i2s_0_data_len_sel_tx = CODEC_InitStruct->CODEC_I2STxDataWidth;
+    codec_0x148.b.i2s_0_data_len_sel_rx = CODEC_InitStruct->CODEC_I2SRxDataWidth;
+    codec_0x148.b.i2s_0_ch_len_sel_tx = CODEC_InitStruct->CODEC_I2SChannelLen;
+    codec_0x148.b.i2s_0_ch_len_sel_rx = CODEC_InitStruct->CODEC_I2SChannelLen;
+    codec_0x148.b.i2s_0_data_ch_sel_tx = CODEC_InitStruct->CODEC_I2SChSequence;
+    codec_0x148.b.i2s_0_data_ch_sel_rx = CODEC_InitStruct->CODEC_I2SChSequence;
+
+    /* Configuer mic channel 0 parameters */
+    codec_0x164.b.adc_0_admic_sel = CODEC_InitStruct->CODEC_Ch0MicType;
+    codec_0x164.b.adc_0_dmic_src_sel = CODEC_InitStruct->CODEC_Ch0DmicDataLatch;
+    codec_0x164.b.adc_0_ad_src_sel = 0x0;
+    codec_0x164.b.adc_0_ad_mute = CODEC_InitStruct->CODEC_Ch0Mute;
+    codec_0x164.b.adc_0_dchpf_en = DISABLE;
+    codec_0x164.b.adc_0_dchpf_fc_sel = 0x4;  /*3'b000: high corner freq. ~ 3'b111: low corner freq.*/
+    codec_0x164.b.adc_0_ad_lpf1st_en = 0x1;
+    codec_0x164.b.adc_0_ad_lpf2nd_en = 0x1;
+    codec_0x164.b.adc_0_ad_zdet_func = 0X2;
+
+    codec_0x168.b.adc_0_ad_gain = CODEC_InitStruct->CODEC_Ch0AdGain;
+    codec_0x168.b.adc_0_depop_en = 0x0;
+
+    /* Configuer mic channel 1 parameters */
+    codec_0x16C.b.adc_1_admic_sel = CODEC_InitStruct->CODEC_Ch1MicType;
+    codec_0x16C.b.adc_1_dmic_src_sel = CODEC_InitStruct->CODEC_Ch1DmicDataLatch;
+    codec_0x16C.b.adc_1_ad_src_sel = 0x0;
+    codec_0x16C.b.adc_1_ad_mute = CODEC_InitStruct->CODEC_Ch1Mute;
+    codec_0x16C.b.adc_1_dchpf_en = 0x0;;
+    codec_0x16C.b.adc_1_dchpf_fc_sel = 0x4;  /*3'b000: high corner freq. ~ 3'b111: low corner freq.*/
+    codec_0x16C.b.adc_1_ad_lpf1st_en = 0x1;
+    codec_0x16C.b.adc_1_ad_lpf2nd_en = 0x1;
+    codec_0x16C.b.adc_1_ad_zdet_func =
+        0x2; //Channel 1 ADC path zero detection function select 2'b00 : immediate change 2'b01 : zero detection & immediate change 2'b10:zdet & step 2'b11: zdet&timeout step
+
+    codec_0x170.b.adc_1_ad_gain = CODEC_InitStruct->CODEC_Ch1AdGain;
+    codec_0x170.b.adc_1_depop_en = 0x0;
+
+    /* Configure PDM parametes */
+    codec_0x194.b.dac_l_da_gain = CODEC_InitStruct->CODEC_DaGain;   // da dvol gain
+    codec_0x198.b.dac_l_da_mute = (CODEC_InitStruct->CODEC_DaGain == 0x00);// -65.625 dB
+    codec_0x198.b.dac_l_da_dither_sel = DAC_DA_DITHER_LSB;
+    codec_0x198.b.dac_l_dmix_mute_da = DISABLE;
+    codec_0x198.b.dac_l_dmix_mute_dc = ENABLE;
+    codec_0x198.b.dac_l_pdm_en = 1;
+
+    codec_0x198.b.dac_l_sdm_dither_sel = DAC_DA_DITHER_DISABLE;
+    codec_0x198.b.dac_l_da_zdet_func =
+        0x2; //Channel L DAC path zero detection function select 2'b00 : immediate change 2'b01 : zero detection & immediate
+    codec_0x198.b.dac_l_hpf_fc_sel = 0x0;
+
+    CODEC_ANA->CODEC_ANA_00_BUS = codec_0x000.d32;
+    CODEC_ANA->CODEC_ANA_01_BUS = codec_0x004.d32;
+    CODEC_ANA->CODEC_ANA_02_BUS = codec_0x008.d32;
+    CODEC_ANA->CODEC_ANA_03_BUS = codec_0x00C.d32;
+
+    CODEC->AUDIO_CONTROL_0 = codec_0x100.d32;
+
+    CODEC->AUDIO_CONTROL_1 = codec_0x104.d32;
+    CODEC->CLOCK_CONTROL_1 = codec_0x108.d32;
+    CODEC->CLOCK_CONTROL_3 = codec_0x110.d32;
+    CODEC->CLOCK_CONTROL_4 = codec_0x114.d32;
+    CODEC->CLOCK_CONTROL_7 = codec_0x118.d32;
+    CODEC->CLOCK_CONTROL_5 = codec_0x11C.d32;
+    CODEC->I2S_0_CONTROL =  codec_0x148.d32;
+
+    CODEC->ADC_0_CONTROL_0 = codec_0x164.d32;
+    CODEC->ADC_0_CONTROL_1 = codec_0x168.d32;
+    CODEC->ADC_1_CONTROL_0 = codec_0x16C.d32;
+    CODEC->ADC_1_CONTROL_1 = codec_0x170.d32;
+
+    CODEC->DAC_L_CONTROL_0 = codec_0x194.d32;
+    CODEC->DAC_L_CONTROL_1 = codec_0x198.d32;
+}
+
+/**
+  * \brief Initializes the CODEC EQ module according to the specified
+  *   parameters in the CODEC_EQInitStruct
+  * \param  CODEC_EQx: the selected CODEC EQ channel.
+  *   which can be CODEC_CH0_EQ1~CODEC_CH0_EQ5, or CODEC_CH1_EQ1~CODEC_CH1_EQ5.
+  * \param  CODEC_EQInitStruct: pointer to a CODEC_EQInitTypeDef structure that
+  *   contains the configuration information for the specified CODEC EQ channel
+  * \return None
+  */
+void CODEC_EQInit(CODEC_EQTypeDef *CODEC_EQx, CODEC_EQInitTypeDef *CODEC_EQInitStruct)
+{
+    uint32_t bit_pos = 0;
+
+    CODEC_EQx->EQ_H0 = CODEC_EQInitStruct->CODEC_EQCoefH0;
+    CODEC_EQx->EQ_B1 = CODEC_EQInitStruct->CODEC_EQCoefB1;
+    CODEC_EQx->EQ_B2 = CODEC_EQInitStruct->CODEC_EQCoefB2;
+    CODEC_EQx->EQ_A1 = CODEC_EQInitStruct->CODEC_EQCoefA1;
+    CODEC_EQx->EQ_A2 = CODEC_EQInitStruct->CODEC_EQCoefA2;
+
+    if (((uint32_t)CODEC_EQx) <= CODEC_DAC_L_EQ9_REG_BASE)
+    {
+        bit_pos = ((uint32_t)CODEC_EQx -  CODEC_DAC_L_EQ0_REG_BASE) / 20;
+        if (CODEC_EQInitStruct->CODEC_EQChCmd != DISABLE)
+        {
+            CODEC_DAC_L_CR |= ENABLE << bit_pos;
+        }
+        else
+        {
+            CODEC_DAC_L_CR &= ~(ENABLE << bit_pos);
+        }
+    }
+    else if ((((uint32_t)CODEC_EQx) >= CODEC_ADC_CH0_CR_REG_BASE) &&
+             (((uint32_t)CODEC_EQx) <= CODEC_ADC_CH0_EQ4_REG_BASE))
+    {
+        bit_pos = ((uint32_t)CODEC_EQx -  CODEC_ADC_CH0_EQ0_REG_BASE) / 20;
+        if (CODEC_EQInitStruct->CODEC_EQChCmd != DISABLE)
+        {
+            CODEC_ADC_CH0_CR |= ENABLE << bit_pos;
+        }
+        else
+        {
+            CODEC_ADC_CH0_CR &= ~(ENABLE << bit_pos);
+        }
+    }
+    else if ((((uint32_t)CODEC_EQx) >= CODEC_ADC_CH1_EQ0_REG_BASE) &&
+             (((uint32_t)CODEC_EQx) <= CODEC_ADC_CH1_EQ4_REG_BASE))
+    {
+        bit_pos = ((uint32_t)CODEC_EQx -  CODEC_ADC_CH1_EQ0_REG_BASE) / 20;
+        if (CODEC_EQInitStruct->CODEC_EQChCmd != DISABLE)
+        {
+            CODEC_ADC_CH1_CR |= ENABLE << bit_pos;
+        }
+        else
+        {
+            CODEC_ADC_CH1_CR &= ~(ENABLE << bit_pos);
+        }
+    }
+}
+
+/**
+  * \brief  Fills each CODEC_InitStruct member with its default value.
+  * \param  CODEC_InitStruct: pointer to an CODEC_InitTypeDef structure which will be initialized.
+  * \return None
+  */
+void CODEC_StructInit(CODEC_InitTypeDef *CODEC_InitStruct)
+{
+    /* Basic parameters section */
+    CODEC_InitStruct->CODEC_AdSampleRateSrc = SAMPLE_RATE_SRC0;
+    CODEC_InitStruct->CODEC_DaSampleRateSrc = SAMPLE_RATE_SRC0;
+    CODEC_InitStruct->CODEC_SampleRate0 = SAMPLE_RATE_16KHz;
+    CODEC_InitStruct->CODEC_SampleRate1 = SAMPLE_RATE_16KHz;
+
+    CODEC_InitStruct->CODEC_I2SChSequence = CODEC_I2S_CH_L_R;
+    CODEC_InitStruct->CODEC_I2STxDataWidth = CODEC_I2S_Tx_DataWidth_16Bits;
+    CODEC_InitStruct->CODEC_I2SRxDataWidth = CODEC_I2S_Rx_DataWidth_16Bits;
+    CODEC_InitStruct->CODEC_I2SChannelLen = I2S_CHANNELLEN_32;
+    CODEC_InitStruct->CODEC_I2SFormat = CODEC_I2S_DataFormat_I2S;
+    CODEC_InitStruct->CODEC_I2SSameLrcEn = DISABLE;
+
+    CODEC_InitStruct->CODEC_MicBIAS = MICBIAS_VOLTAGE_1_8;
+    CODEC_InitStruct->CODEC_MicBstMode = MICBST_Mode_Single;
+    CODEC_InitStruct->CODEC_MicBstGain = MICBST_Gain_20dB;
+    CODEC_InitStruct->CODEC_DmicClock = DMIC_Clock_2500KHz;
+    /* MIC channel 0 initialization parameters section */
+    CODEC_InitStruct->CODEC_Ch0Mute = CODEC_UNMUTE;
+    CODEC_InitStruct->CODEC_Ch0MicType = CODEC_CH_AMIC;
+    CODEC_InitStruct->CODEC_Ch0DmicDataLatch = DMIC_Ch_Rising_Latch;
+    CODEC_InitStruct->CODEC_Ch0AdGain = 0x2F;
+    /* MIC channel 1 initialization parameters section */
+    CODEC_InitStruct->CODEC_Ch1Mute = CODEC_MUTE;
+    CODEC_InitStruct->CODEC_Ch1MicType = CODEC_CH_DMIC;
+    CODEC_InitStruct->CODEC_Ch1DmicDataLatch = DMIC_Ch_Falling_Latch;
+    CODEC_InitStruct->CODEC_Ch1AdGain  = 0x2F;
+    /* PDM initialization parameters section */
+    CODEC_InitStruct->CODEC_DaMute = CODEC_MUTE;
+    CODEC_InitStruct->CODEC_DaGain = 0xAF;
+    CODEC_InitStruct->CODEC_DaC_Dither = DAC_DA_DITHER_DISABLE;
+}
+
+
+/**
+  * \brief  Fills each CODEC_EQInitStruct member with its default value.
+  * \param  CODEC_EQInitStruct: pointer to an CODEC_EQInitTypeDef structure which will be initialized.
+  * \return None
+  */
+void CODEC_EQStructInit(CODEC_EQInitTypeDef *CODEC_EQInitStruct)
+{
+    CODEC_EQInitStruct->CODEC_EQChCmd   = DISABLE;
+    /*!< The following all parameters can be 0 to 0x7FFFF, whose physical meaning represents a range of -8 to 7.99 */
+    CODEC_EQInitStruct->CODEC_EQCoefH0  = 0;
+    CODEC_EQInitStruct->CODEC_EQCoefB1  = 0;
+    CODEC_EQInitStruct->CODEC_EQCoefB2  = 0;
+    CODEC_EQInitStruct->CODEC_EQCoefA1  = 0;
+    CODEC_EQInitStruct->CODEC_EQCoefA2  = 0;
+}
+
+/**
+  * \brief  Enable or disable mic_bias output.
+  * \param  CODECx: selected CODEC peripheral.
+  * \param  NewState: new state of MICBIAS.
+  *   This parameter can be: ENABLE or DISABLE.
+  * \return none.
+  */
+void CODEC_MICBIASCmd(CODEC_TypeDef *CODECx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_CODEC_PERIPH(CODECx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+    CODEC_ANA_00_BUS_t codec_0x000 = {.d32 = CODEC_ANA->CODEC_ANA_00_BUS};
+    CODEC_ANA_01_BUS_t codec_0x004 = {.d32 = CODEC_ANA->CODEC_ANA_01_BUS};
+    AUDIO_CONTROL_1_t codec_0x104 = {.d32 = CODEC->AUDIO_CONTROL_1};
+
+    if (NewState == ENABLE)
+    {
+        if (!(codec_0x004.b.MICBIAS_POW))
+        {
+            /* Analog initialization in AON register */
+            CODEC_AnalogCircuitInit();
+
+            /* MICBIAS power on */
+            codec_0x004.b.VREF_VREFSEL = 0x2;
+            codec_0x004.b.MICBST_POW = 0x1;
+            codec_0x004.b.VREF_POW = 0x1;
+            codec_0x004.b.MICBIAS_POW = 0x1;
+            codec_0x004.b.MICBIAS_ENCHX = 0x1;
+
+            codec_0x000.b.DAC_ADDACK_POW = 0x1;
+            codec_0x000.b.DTSDM_CKXEN = 0x1;
+            codec_0x000.b.DTSDM_POW_L = 0x1;
+
+            /* Clock enable */
+            codec_0x104.b.ckx_micbias_en = 0x1;
+        }
+    }
+    else
+    {
+        codec_0x000.b.DTSDM_POW_L = 0x0;
+        codec_0x000.b.DAC_ADDACK_POW = 0x0;
+        codec_0x000.b.DTSDM_CKXEN = 0x0;
+        codec_0x004.b.MICBST_POW = 0x0;
+        codec_0x004.b.MICBIAS_ENCHX = 0x0;
+        codec_0x004.b.VREF_POW = 0x0;
+        CODEC_AnalogCircuitDeInit();
+    }
+    CODEC_ANA->CODEC_ANA_01_BUS = codec_0x004.d32;
+    CODEC_ANA->CODEC_ANA_02_BUS = codec_0x000.d32;
+    CODEC->AUDIO_CONTROL_1 = codec_0x104.d32;
+}
+
diff --git a/bee/drivers/codec/src/device/rtl87x2g/rtl_codec.h b/bee/drivers/codec/src/device/rtl87x2g/rtl_codec.h
new file mode 100644
index 00000000..c45aa9da
--- /dev/null
+++ b/bee/drivers/codec/src/device/rtl87x2g/rtl_codec.h
@@ -0,0 +1,765 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *               Define to prevent recursive inclusion
+ *============================================================================*/
+#ifndef RTL_CODEC_H
+#define RTL_CODEC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*============================================================================*
+ *                        Header Files
+ *============================================================================*/
+#include "utils/rtl_utils.h"
+#include "rtl_codec_def.h"
+
+/** \defgroup CODEC       CODEC
+  * \brief
+  * \{
+  */
+
+/*============================================================================*
+ *                         Constants
+ *============================================================================*/
+/** \defgroup CODEC_Exported_Constants CODEC Exported Constants
+  * \brief
+  * \{
+  */
+
+/**
+ * \defgroup    I2S_Rx_Data_Width I2S Rx Data Width
+ * \{
+ * \ingroup     CODEC_Exported_Constants
+ */
+typedef enum
+{
+    CODEC_I2S_Rx_DataWidth_16Bits,          //!< The I2S Rx data width is 16 bits.
+    CODEC_I2S_Rx_DataWidth_8Bits = 0x3,     //!< The I2S Rx data width is 8 bits.
+} CodecI2SRxDatalenSel_TypeDef;
+
+/** End of I2S_Rx_Data_Width
+  * \}
+  */
+
+/**
+ * \defgroup    I2S_Tx_Data_Width I2S Tx Data Width
+ * \{
+ * \ingroup     CODEC_Exported_Constants
+ */
+typedef enum
+{
+    CODEC_I2S_Tx_DataWidth_16Bits,           //!< The I2S Tx data width is 16 bits.
+    CODEC_I2S_Tx_DataWidth_24Bits = 0x2,     //!< The I2S Tx data width is 24 bits.
+    CODEC_I2S_Tx_DataWidth_8Bits = 0x3,      //!< The I2S Tx data width is 8 bits.
+} CodecI2STxDatalenSel_TypeDef;
+
+/** End of I2S_Tx_Data_Width
+  * \}
+  */
+
+/**
+ * \defgroup    I2S_Channel_Lenth I2S Channel Lenth
+ * \{
+ * \ingroup     CODEC_Exported_Constants
+ */
+typedef enum
+{
+    I2S_CHANNELLEN_16,     //!< The I2S channel lenth is 16 bits.
+    I2S_CHANNELLEN_32,     //!< The I2S channel lenth is 32 bits.
+    I2S_CHANNELLEN_24,     //!< The I2S channel lenth is 24 bits.
+    I2S_CHANNELLEN_8,      //!< The I2S channel lenth is 8 bits.
+} CodecI2SChannellenSel_TypeDef;
+
+/** End of I2S_Channel_Lenth
+  * \}
+  */
+
+/**
+ * \defgroup    I2S_Data_Format I2S Data Format
+ * \{
+ * \ingroup     CODEC_Exported_Constants
+ */
+typedef enum
+{
+    CODEC_I2S_DataFormat_I2S,            //!< The I2S data format is I2S.
+    CODEC_I2S_DataFormat_LeftJustified,  //!< The I2S data format is left justified.
+    CODEC_I2S_DataFormat_PCM_A,          //!< The I2S data format is PCM mode A.
+    CODEC_I2S_DataFormat_PCM_B,          //!< The I2S data format is PCM mode B.
+} CodecI2SFormatSel_TypeDef;
+
+#define IS_CODEC_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == CODEC_I2S_DataFormat_I2S) || \
+                                          ((FORMAT) == CODEC_I2S_DataFormat_LeftJustified) || \
+                                          ((FORMAT) == CODEC_I2S_DataFormat_PCM_A) || \
+                                          ((FORMAT) == CODEC_I2S_DataFormat_PCM_B)) //!< Check if the input parameter is valid.
+
+/** End of I2S_Data_Format
+  * \}
+  */
+
+/**
+ * \defgroup    CODEC_DAC_Dither CODEC DAC Dither
+ * \{
+ * \ingroup     CODEC_Exported_Constants
+ */
+typedef enum
+{
+    DAC_DA_DITHER_DISABLE = 0,    //!< The SDM dither in the DAC path of the audio channel is disabled.
+    DAC_DA_DITHER_LSB = 1,        //!< The SDM dither in the DAC path of the audio channel is set to LSB.
+    DAC_DA_DITHER_LSB_PLUS_1 = 2, //!< The SDM dither in the DAC path of the audio channel is set to LSB+1.
+    DAC_DA_DITHER_LSB_PLUS_2 = 3, //!< The SDM dither in the DAC path of the audio channel is set to LSB+2.
+} CodecDacDADitherSel_TypeDef;
+
+/** End of CODEC_DAC_Dither
+  * \}
+  */
+
+/**
+ * \defgroup    CODEC_I2S_Channel_Sequence CODEC I2S Channel Sequence
+ * \{
+ * \ingroup     CODEC_Exported_Constants
+ */
+typedef enum
+{
+    CODEC_I2S_CH_L_R,        //!< I2S channel sequence from left to right.
+    CODEC_I2S_CH_R_L,        //!< I2S channel sequence from right to left.
+    CODEC_I2S_CH_L_L,        //!< I2S channel sequence from left to left.
+    CODEC_I2S_CH_R_R,        //!< I2S channel sequence from right to right.
+} CodecI2SCHSequenceSel_TypeDef;
+
+#define IS_CODEC_I2S_CH(CH)             (((CH) == CODEC_I2S_CH_L_R) || \
+                                         ((CH) == CODEC_I2S_CH_R_L) || \
+                                         ((CH) == CODEC_I2S_CH_L_L) || \
+                                         ((CH) == CODEC_I2S_CH_R_R)) //!< Check if the input parameter is valid.
+
+/** End of CODEC_I2S_CH
+  * \}
+  */
+
+/**
+ * \defgroup    Sample_Rate_Definition Sample Rate Definition
+ * \{
+ * \ingroup     CODEC_Exported_Constants
+ */
+typedef enum
+{
+    SAMPLE_RATE_48KHz,      //!< CODEC sample rate is 48KHz.
+    SAMPLE_RATE_96KHz,      //!< CODEC sample rate is 96KHz.
+    SAMPLE_RATE_192KHz,     //!< CODEC sample rate is 192KHz.
+    SAMPLE_RATE_32KHz,      //!< CODEC sample rate is 32KHz.
+    SAMPLE_RATE_176KHz,     //!< CODEC sample rate is 176.4KHz.
+    SAMPLE_RATE_16KHz,      //!< CODEC sample rate is 16KHz.
+    SAMPLE_RATE_RSV_1,      //!< This parameter is meaningless.
+    SAMPLE_RATE_8KHz,       //!< CODEC sample rate is 8KHz.
+    SAMPLE_RATE_44100Hz,    //!< CODEC sample rate is 44.1KHz.
+    SAMPLE_RATE_88200Hz,    //!< CODEC sample rate is 88.2KHz.
+    SAMPLE_RATE_24KHz,      //!< CODEC sample rate is 24KHz.
+    SAMPLE_RATE_12KHz,      //!< CODEC sample rate is 12KHz.
+    SAMPLE_RATE_22050Hz,    //!< CODEC sample rate is 22.05KHz.
+    SAMPLE_RATE_11025Hz,    //!< CODEC sample rate is 11.025KHz.
+} CodecSampleRate_TypeDef;
+
+#define IS_SAMPLE_RATE(RATE) (((RATE) == SAMPLE_RATE_48KHz)   || ((RATE) == SAMPLE_RATE_96KHz)   || \
+                              ((RATE) == SAMPLE_RATE_192KHz)   || ((RATE) == SAMPLE_RATE_176KHz)   || \
+                              ((RATE) == SAMPLE_RATE_32KHz)   || ((RATE) == SAMPLE_RATE_16KHz)   || \
+                              ((RATE) == SAMPLE_RATE_8KHz)    || ((RATE) == SAMPLE_RATE_44100Hz) || \
+                              ((RATE) == SAMPLE_RATE_88200Hz) || ((RATE) == SAMPLE_RATE_24KHz)   || \
+                              ((RATE) == SAMPLE_RATE_12KHz)   || ((RATE) == SAMPLE_RATE_22050Hz) || \
+                              ((RATE) == SAMPLE_RATE_11025Hz)) //!< Check if the input parameter is valid.
+
+/** End of Sample_Rate_Definition
+  * \}
+  */
+
+/**
+ * \defgroup    CODEC_Sample_Rate_SRC CODEC Sample Rate SRC
+ * \{
+ * \ingroup     CODEC_Exported_Constants
+ */
+typedef enum
+{
+    SAMPLE_RATE_SRC0 = 0,      //!< CODEC sample rate source is SRC0.
+    SAMPLE_RATE_SRC1 = 1,      //!< CODEC sample rate source is SRC1.
+    SAMPLE_RATE_SRC2 = 2,      //!< CODEC sample rate source is SRC2.
+    SAMPLE_RATE_SRC3_DA = 3,   //!< CODEC sample rate source is SRC3_DA.
+} CodecSampleRateSrc_TypeDef;
+
+/** End of CODEC_Sample_Rate_SRC
+  * \}
+  */
+
+/**
+ * \defgroup    DMIC_Clock_Type_Definition DMIC Clock Type Definition
+ * \{
+ * \ingroup     CODEC_Exported_Constants
+ */
+typedef enum
+{
+    DMIC_Clock_5MHz,         //!< CODEC DMIC clock source is 5MHz.
+    DMIC_Clock_2500KHz,      //!< CODEC DMIC clock source is 2500KHz.
+    DMIC_Clock_1250KHz,      //!< CODEC DMIC clock source is 1250KHz.
+    DMIC_Clock_625KHz,       //!< CODEC DMIC clock source is 625KHz.
+    DMIC_Clock_312500Hz,     //!< CODEC DMIC clock source is 312500Hz.
+} CodecDmicClkSel_TypeDef;
+
+#define IS_CODEC_DMIC_CLOCK(CLOCK) (((CLOCK) == DMIC_Clock_5MHz) || ((CLOCK) == DMIC_Clock_2500KHz) || \
+                                    ((CLOCK) == DMIC_Clock_1250KHz) || ((CLOCK) == DMIC_Clock_625KHz) || \
+                                    ((CLOCK) == DMIC_Clock_312500Hz)) //!< Check if the input parameter is valid.
+
+/** End of DMIC_Clock_Type_Definition
+  * \}
+  */
+
+/**
+ * \defgroup    CODEC_MIC_BIAS_Config CODEC MIC BIAS Config
+ * \{
+ * \ingroup     CODEC_Exported_Constants
+ */
+typedef enum
+{
+    MICBIAS_VOLTAGE_1_507,     //!< Vref voltage is 1.507V.
+    MICBIAS_VOLTAGE_1_62,      //!< Vref voltage is 1.62V.
+    MICBIAS_VOLTAGE_1_705,     //!< Vref voltage is 1.705V.
+    MICBIAS_VOLTAGE_1_8,       //!< Vref voltage is 1.8V.
+    MICBIAS_VOLTAGE_1_906,     //!< Vref voltage is 1.906V.
+    MICBIAS_VOLTAGE_2_025,     //!< Vref voltage is 2.025V.
+    MICBIAS_VOLTAGE_2_16,      //!< Vref voltage is 2.16V.
+    MICBIAS_VOLTAGE_2_314,     //!< Vref voltage is 2.314V.
+} MicbiasVoltageSel_TypeDef;
+
+#define IS_MICBIAS_CONFIG(CONFIG) (((CONFIG) == MICBIAS_VOLTAGE_1_507) || ((CONFIG) == MICBIAS_VOLTAGE_1_62) || \
+                                   ((CONFIG) == MICBIAS_VOLTAGE_1_705) || ((CONFIG) == MICBIAS_VOLTAGE_1_8) || \
+                                   ((CONFIG) == MICBIAS_VOLTAGE_1_906) || ((CONFIG) == MICBIAS_VOLTAGE_2_025) || \
+                                   ((CONFIG) == MICBIAS_VOLTAGE_2_16) || ((CONFIG) == MICBIAS_VOLTAGE_2_314)) //!< Check if the input parameter is valid.
+
+/** End of CODEC_MIC_BIAS_Config
+  * \}
+  */
+
+/**
+ * \defgroup    MICBST_Gain MICBST Gain
+ * \{
+ * \ingroup     CODEC_Exported_Constants
+ */
+typedef enum
+{
+    MICBST_Gain_0dB,     //!< MICBST Gain is 0dB.
+    MICBST_Gain_20dB,    //!< MICBST Gain is 20dB.
+    MICBST_Gain_30dB,    //!< MICBST Gain is 30dB.
+    MICBST_Gain_40dB,    //!< MICBST Gain is 40dB.
+} MicbiasGainSel_TypeDef;
+
+#define IS_MICBST_GAIN(GAIN)            (((GAIN) == MICBST_Gain_0dB) || \
+                                         ((GAIN) == MICBST_Gain_20dB) || \
+                                         ((GAIN) == MICBST_Gain_30dB) || \
+                                         ((GAIN) == MICBST_Gain_40dB)) //!< Check if the input parameter is valid.
+
+/** End of MICBST_Gain
+  * \}
+  */
+
+/**
+ * \defgroup    MICBST_Mode MICBST Mode
+ * \{
+ * \ingroup     CODEC_Exported_Constants
+ */
+typedef enum
+{
+    MICBST_Mode_Single,           //!< MICBST channel mode is single-ended mode.
+    MICBST_Mode_Differential,     //!< MICBST channel mode is differential mode.
+} MicbiasModeSel_TypeDef;
+
+#define IS_MICBST_MODE(MODE)            (((MODE) == MICBST_Mode_Single) || \
+                                         ((MODE) == MICBST_Mode_Differential)) //!< Check if the input parameter is valid.
+
+/** End of MICBST_Mode
+  * \}
+  */
+
+/**
+ * \defgroup    CODEC_Mute_Type CODEC Mute Type
+ * \{
+ * \ingroup     CODEC_Exported_Constants
+ */
+typedef enum
+{
+    CODEC_UNMUTE,    //!< The codec channel is un-muted.
+    CODEC_MUTE,      //!< The codec channel is muted.
+} CodecMuteSel_TypeDef;
+
+#define IS_CODEC_MIC_MUTE(MUTE) (((MUTE) == CODEC_MUTE) || ((MUTE) == CODEC_UNMUTE)) //!< Check if the input parameter is valid.
+
+/** End of CODEC_Mute_Type
+  * \}
+  */
+
+/**
+ * \defgroup    CODEC_Channel_Mic_Type CODEC Channel Mic Type
+ * \{
+ * \ingroup     CODEC_Exported_Constants
+ */
+typedef enum
+{
+    CODEC_CH_DMIC,      //!< Select the Digital Microphone.
+    CODEC_CH_AMIC,      //!< Select the Analog Microphone.
+} CodecCHMicSel_TypeDef;
+
+#define IS_CODEC_CH_MIC_TYPE(TYPE) (((TYPE) == CODEC_CH_AMIC) || ((TYPE) == CODEC_CH_DMIC)) //!< Check if the input parameter is valid.
+
+/** End of CODEC_Channel_Mic_Type
+  * \}
+  */
+
+/**
+ * \defgroup    DMIC_Data_Latch_Edge DMIC Data Latch Edge
+ * \{
+ * \ingroup     CODEC_Exported_Constants
+ */
+typedef enum
+{
+    DMIC_Ch_Rising_Latch,       //!< DMIC data latch is set to rising edge trigger.
+    DMIC_Ch_Falling_Latch,      //!< DMIC data latch is set to falling edge trigger.
+} CdecCHLatchEdgeSel_TypeDef;
+
+#define IS_DMIC_CH_LATCH_EDGE(EDGE) (((EDGE) == DMIC_Ch_Rising_Latch) || ((EDGE) == DMIC_Ch_Falling_Latch)) //!< Check if the input parameter is valid.
+
+/** End of DMIC_Data_Latch_Edge
+  * \}
+  */
+
+/**
+ * \defgroup    CODEC_Ad_Gain CODEC Ad Gain
+ * \{
+ * \ingroup     CODEC_Exported_Constants
+ */
+#define IS_AD_GAIN(GAIN)            (((GAIN)<= 0x10F))     //!< Codec Ad Gain. Ad Gain can be a value of 0x0 ~ 0x10f.
+
+/** End of CODEC_Ad_Gain
+  * \}
+  */
+
+/** End of CODEC_Exported_Constants
+  * \}
+  */
+
+/*============================================================================*
+ *                         Types
+ *============================================================================*/
+/** \defgroup CODEC_Exported_Types CODEC Exported Types
+  * \brief
+  * \{
+  */
+
+/**
+ * \brief       CODEC initialize parameters.
+ *
+ * \ingroup     CODEC_Exported_Types
+ */
+typedef struct
+{
+    /* Basic parameters section */
+    CodecSampleRateSrc_TypeDef CODEC_AdSampleRateSrc; /*!< Specify the AD path sample rate source.
+                                                           This parameter can be a value of \ref CODEC_Sample_Rate_SRC. */
+
+    CodecSampleRateSrc_TypeDef CODEC_DaSampleRateSrc; /*!< Specify the DA path sample rate source.
+                                                           This parameter can be a value of \ref CODEC_Sample_Rate_SRC. */
+
+    CodecSampleRate_TypeDef CODEC_SampleRate0;        /*!< Specify the sample rate 0.
+                                                           This parameter can be a value of \ref Sample_Rate_Definition. */
+
+    CodecSampleRate_TypeDef CODEC_SampleRate1;        /*!< Specify the sample rate 1.
+                                                           This parameter can be a value of \ref Sample_Rate_Definition. */
+
+    CodecDmicClkSel_TypeDef CODEC_DmicClock;          /*!< Specify the dmic clock.
+                                                           This parameter can be a value of \ref DMIC_Clock_Type_Definition. */
+
+    CodecI2SFormatSel_TypeDef CODEC_I2SFormat;        /*!< Specify the I2S Tx/Rx format of codec port.
+                                                           This parameter can be a value of \ref I2S_Data_Format. */
+    CodecI2STxDatalenSel_TypeDef
+    CODEC_I2STxDataWidth;                             /*!< Specify the I2S Tx data width of codec port.
+                                                           This parameter can be a value of \ref I2S_Tx_Data_Width. */
+
+    CodecI2SRxDatalenSel_TypeDef
+    CODEC_I2SRxDataWidth;                             /*!< Specify the I2S Rx data width of codec port.
+                                                           This parameter can be a value of \ref I2S_Rx_Data_Width. */
+
+    CodecI2SChannellenSel_TypeDef
+    CODEC_I2SChannelLen;                              /*!< Specify the I2S Tx/Rx channel width of codec port.
+                                                           This parameter can be a value of \ref I2S_Channel_Lenth. */
+
+    CodecI2SCHSequenceSel_TypeDef CODEC_I2SChSequence;/*!< Specify the I2S Tx/Rx channel sequence.
+                                                           This parameter can be a value of \ref CODEC_I2S_Channel_Sequence. */
+
+    uint8_t CODEC_I2SSameLrcEn;                       /*!< Enable or disable Tx and Rx using the same transmission mode.
+                                                           This parameter can be a value of DISABLE or ENABLE. */
+
+    MicbiasVoltageSel_TypeDef CODEC_MicBIAS;          /*!< Specify the MICBIAS voltage.
+                                                           This parameter can be a value of \ref CODEC_MIC_BIAS_Config */
+
+    MicbiasGainSel_TypeDef CODEC_MicBstGain;          /*!< Specify the MICBST gain.
+                                                           This parameter can be a value of \ref MICBST_Gain. */
+
+    MicbiasModeSel_TypeDef CODEC_MicBstMode;          /*!< Specify the MICBST mode.
+                                                           This parameter can be a value of \ref MICBST_Mode. */
+
+    /* MIC channel 0 initialization parameters section */
+    CodecMuteSel_TypeDef CODEC_Ch0Mute;               /*!< Specify the channel 0 dmic mute status.
+                                                           This parameter can be a value of \ref CODEC_Mute_Type. */
+
+    CodecCHMicSel_TypeDef
+    CODEC_Ch0MicType;                                 /*!< Specify the channel 0 mic type, which can be dmic or amic.
+                                                           This parameter can be a value of \ref CODEC_Channel_Mic_Type. */
+
+    CdecCHLatchEdgeSel_TypeDef
+    CODEC_Ch0DmicDataLatch;                           /*!< Specify the channel 0 dmic data latch type.
+                                                           This parameter can be a value of \ref DMIC_Data_Latch_Edge. */
+
+    uint32_t CODEC_Ch0AdGain;                         /*!< Specify the channel 0 AD gain control.
+                                                           This parameter can be a value of 0x0 ~ 0x10f. */
+
+    /* MIC channel 1 initialization parameters section */
+    CodecMuteSel_TypeDef CODEC_Ch1Mute;               /*!< Specify the channel 1 mic mute status.
+                                                           This parameter can be a value of \ref CODEC_Mute_Type. */
+    CodecCHMicSel_TypeDef
+    CODEC_Ch1MicType;                                 /*!< Specify the channel 1 mic type, which can be dmic or amic.
+                                                           This parameter can be a value of \ref CODEC_Channel_Mic_Type. */
+
+    CdecCHLatchEdgeSel_TypeDef
+    CODEC_Ch1DmicDataLatch;                           /*!< Specify the channel 1 dmic data latch type.
+                                                           This parameter can be a value of \ref DMIC_Data_Latch_Edge. */
+
+    uint32_t CODEC_Ch1AdGain;                         /*!< Specify the channel 1 AD gain control.
+                                                           This parameter can be a value of 0x0 ~ 0x10f. */
+
+    /* PDM initialization parameters section */
+    CodecMuteSel_TypeDef CODEC_DaMute;                /*!< Specify the DA mute status.
+                                                           This parameter can be a value of \ref CODEC_Mute_Type. */
+
+    uint32_t CODEC_DaGain;                            /*!< Specify the DA gain control.
+                                                           This parameter can be a value of 0x0 ~ 0xAF. */
+
+    CodecDacDADitherSel_TypeDef
+    CODEC_DaC_Dither;     /*!< Specify the SDM dither in the DAC path of the audio channel.
+                                                           This parameter can be a value of \ref CODEC_DAC_Dither. */
+} CODEC_InitTypeDef;
+
+
+/**
+ * \brief       CODEC EQ part initialize parameters.
+ *
+ * \ingroup     CODEC_Exported_Types
+ */
+typedef struct
+{
+    uint32_t CODEC_EQChCmd;             /*!< Specify the EQ channel status.
+                                             This parameter can be a value of DISABLE or ENABLE. */
+
+    uint32_t CODEC_EQCoefH0;            /*!< Specify the EQ coef.h0. This value can be 0 to 0x7FFFF,
+                                             whose physical meaning represents a range of-8 to 7.99. */
+
+    uint32_t CODEC_EQCoefB1;            /*!< Specify the EQ coef.b1. This value can be 0 to 0x7FFFF,
+                                             whose physical meaning represents a range of-8 to 7.99. */
+
+    uint32_t CODEC_EQCoefB2;            /*!< Specify the EQ coef.b2. This value can be 0 to 0x7FFFF,
+                                             whose physical meaning represents a range of-8 to 7.99. */
+
+    uint32_t CODEC_EQCoefA1;            /*!< Specify the EQ coef.a1. This value can be 0 to 0x7FFFF,
+                                             whose physical meaning represents a range of-8 to 7.99. */
+
+    uint32_t CODEC_EQCoefA2;            /*!< Specify the EQ coef.a2. This value can be 0 to 0x7FFFF,
+                                             whose physical meaning represents a range of-8 to 7.99. */
+} CODEC_EQInitTypeDef;
+
+/** End of CODEC_Exported_Types
+  * \}
+  */
+
+/*============================================================================*
+ *                         Functions
+ *============================================================================*/
+/** \defgroup CODEC_Exported_Functions CODEC Exported Functions
+  * \brief
+  * \{
+  */
+
+/**
+ * \brief   Deinitialize the CODEC peripheral registers to their default reset values(turn off CODEC clock).
+ *
+ * \param[in] CODECx  CODEC peripheral selected. Refer to \ref CODEC_Declaration.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_codec_init(void)
+ * {
+ *     CODEC_DeInit(CODEC);
+ * }
+ * \endcode
+ */
+void CODEC_DeInit(CODEC_TypeDef *CODECx);
+/**
+ * \brief    Initialize the CODEC analog registers in AON area.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_codec_init(void)
+ * {
+ *     RCC_PeriphClockCmd(APBPeriph_CODEC, APBPeriph_CODEC_CLOCK, ENABLE);
+ *     CODEC_AnalogCircuitInit();
+ *     CODEC_InitTypeDef CODEC_InitStruct;
+ *     CODEC_StructInit(&CODEC_InitStruct);
+ *     CODEC_InitStruct.CODEC_Ch0MicType       = CODEC_CH0_AMIC;
+ *     CODEC_InitStruct.CODEC_MicBstMode       = MICBST_Mode_Differential;
+ *     CODEC_InitStruct.CODEC_SampleRate       = SAMPLE_RATE_16KHz;
+ *     CODEC_InitStruct.CODEC_I2SFormat        = CODEC_I2S_DataFormat_I2S;
+ *     CODEC_InitStruct.CODEC_I2SDataWidth     = CODEC_I2S_DataWidth_16Bits;
+ *     CODEC_Init(CODEC, &CODEC_InitStruct);
+ * }
+ * \endcode
+ */
+void CODEC_AnalogCircuitInit(void);
+/**
+ * \brief   Initialize the CODEC peripheral according to the specified parameters in the CODEC_InitStruct.
+ *
+ * \param[in] CODECx            CODEC peripheral selected. Refer to \ref CODEC_Declaration.
+ * \param[in] CODEC_InitStruct  Pointer to a CODEC_InitTypeDef structure which will be initialized.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_codec_init(void)
+ * {
+ *     RCC_PeriphClockCmd(APBPeriph_CODEC, APBPeriph_CODEC_CLOCK, ENABLE);
+ *
+ *     CODEC_InitTypeDef CODEC_InitStruct;
+
+ *     CODEC_StructInit(&CODEC_InitStruct);
+ *     CODEC_InitStruct.CODEC_Ch0MicType       = CODEC_CH0_AMIC;
+ *     CODEC_InitStruct.CODEC_MicBstMode       = MICBST_Mode_Differential;
+ *     CODEC_InitStruct.CODEC_SampleRate       = SAMPLE_RATE_16KHz;
+ *     CODEC_InitStruct.CODEC_I2SFormat        = CODEC_I2S_DataFormat_I2S;
+ *     CODEC_InitStruct.CODEC_I2SDataWidth     = CODEC_I2S_DataWidth_16Bits;
+ *     CODEC_Init(CODEC, &CODEC_InitStruct);
+ * }
+ * \endcode
+ */
+void CODEC_Init(CODEC_TypeDef *CODECx, CODEC_InitTypeDef *CODEC_InitStruct);
+
+/**
+ * \brief   Fill each CODEC_InitStruct member with its default value.
+ *
+ * \note The default settings for the CODEC_InitTypeDef member are shown in the following table:
+ *       | CODEC_InitTypeDef member     | Default value                              |
+ *       |:----------------------------:|:------------------------------------------:|
+ *       | CODEC_AdSampleRateSrc        | \ref SAMPLE_RATE_SRC0                      |
+ *       | CODEC_DaSampleRateSrc        | \ref SAMPLE_RATE_SRC0                      |
+ *       | CODEC_SampleRate0            | \ref SAMPLE_RATE_16KHz                     |
+ *       | CODEC_SampleRate1            | \ref SAMPLE_RATE_16KHz                     |
+ *       | CODEC_I2SChSequence          | \ref CODEC_I2S_CH_L_R                      |
+ *       | CODEC_I2STxDataWidth         | \ref CODEC_I2S_Tx_DataWidth_16Bits         |
+ *       | CODEC_I2SRxDataWidth         | \ref CODEC_I2S_Rx_DataWidth_16Bits         |
+ *       | CODEC_I2SChannelLen          | \ref I2S_CHANNELLEN_32                     |
+ *       | CODEC_I2SFormat              | \ref CODEC_I2S_DataFormat_I2S              |
+ *       | CODEC_I2SSameLrcEn           | DISABLE                                    |
+ *       | CODEC_MicBIAS                | \ref MICBIAS_VOLTAGE_1_8                   |
+ *       | CODEC_MicBstMode             | \ref MICBST_Mode_Single                    |
+ *       | CODEC_MicBstGain             | \ref MICBST_Gain_20dB                      |
+ *       | CODEC_DmicClock              | \ref DMIC_Clock_2500KHz                    |
+ *       | CODEC_Ch0Mute                | \ref CODEC_UNMUTE                          |
+ *       | CODEC_Ch0MicType             | \ref CODEC_CH_AMIC                         |
+ *       | CODEC_Ch0DmicDataLatch       | \ref DMIC_Ch_Rising_Latch                  |
+ *       | CODEC_Ch0AdGain              | 0x2F                                       |
+ *       | CODEC_Ch1Mute                | \ref CODEC_MUTE                            |
+ *       | CODEC_Ch1MicType             | \ref CODEC_CH_DMIC                         |
+ *       | CODEC_Ch1DmicDataLatch       | \ref DMIC_Ch_Falling_Latch                 |
+ *       | CODEC_Ch1AdGain              | 0x2F                                       |
+ *       | CODEC_DaMute                 | \ref CODEC_MUTE                            |
+ *       | CODEC_DaGain                 | 0xAF                                       |
+ *       | CODEC_DaC_Dither             | \ref DAC_DA_DITHER_DISABLE                 |
+ *
+ * \param[in] CODEC_InitStruct  Pointer to a CODEC_InitTypeDef structure which will be initialized.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_codec_init(void)
+ * {
+ *     RCC_PeriphClockCmd(APBPeriph_CODEC, APBPeriph_CODEC_CLOCK, ENABLE);
+ *
+ *     CODEC_InitTypeDef CODEC_InitStruct;
+
+ *     CODEC_StructInit(&CODEC_InitStruct);
+ *     CODEC_InitStruct.CODEC_Ch0MicType       = CODEC_CH0_AMIC;
+ *     CODEC_InitStruct.CODEC_MicBstMode       = MICBST_Mode_Differential;
+ *     CODEC_InitStruct.CODEC_SampleRate       = SAMPLE_RATE_16KHz;
+ *     CODEC_InitStruct.CODEC_I2SFormat        = CODEC_I2S_DataFormat_I2S;
+ *     CODEC_InitStruct.CODEC_I2SDataWidth     = CODEC_I2S_DataWidth_16Bits;
+ *     CODEC_Init(CODEC, &CODEC_InitStruct);
+ * }
+ * \endcode
+ */
+void CODEC_StructInit(CODEC_InitTypeDef *CODEC_InitStruct);
+
+/**
+ * \brief   Initialize the CODEC EQ module according to the specified parameters in the CODEC_EQInitStruct.
+ *
+ * \param[in] CODEC_EQx           CODEC EQ channel selected.
+ * \param[in] CODEC_EQInitStruct  Pointer to a CODEC_EQInitTypeDef structure which will be initialized.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_codec_eq_init(void)
+ * {
+ *     CODEC_EQInitTypeDef  CODEC_EQInitStruct;
+ *     CODEC_StructInit(&CODEC_EQInitStruct);
+ *     CODEC_EQInitStruct. CODEC_EQChCmd    = EQ_CH_Cmd_ENABLE;
+ *     CODEC_EQInitStruct.CODEC_EQCoefH0    = 0xFF;
+ *     CODEC_EQInitStruct.CODEC_EQCoefB1    = 0xFF;
+ *     CODEC_EQInitStruct.CODEC_EQCoefB2    = 0xFF;
+ *     CODEC_EQInitStruct.CODEC_EQCoefA1    = 0xFF;
+ *     CODEC_EQInitStruct.CODEC_EQCoefA2    = 0xFF;
+ *     CODEC_EQInit(CODEC_EQ1, CODEC_EQInitStruct);
+ * }
+ * \endcode
+ */
+void CODEC_EQInit(CODEC_EQTypeDef *CODEC_EQx, CODEC_EQInitTypeDef *CODEC_EQInitStruct);
+
+/**
+ * \brief  Fill each CODEC_EQInitStruct member with its default value.
+ *
+ * \note The default settings for the CODEC_EQInitStruct member are shown in the following table:
+ *       | CODEC_EQInitStruct member    | Default value                              |
+ *       |:----------------------------:|:------------------------------------------:|
+ *       | CODEC_EQChCmd                | DISABLE                                    |
+ *       | CODEC_EQCoefH0               | 0                                          |
+ *       | CODEC_EQCoefB1               | 0                                          |
+ *       | CODEC_EQCoefB2               | 0                                          |
+ *       | CODEC_EQCoefA1               | 0                                          |
+ *       | CODEC_EQCoefA2               | 0                                          |
+ *
+ * \param[in] CODEC_EQInitStruct  Pointer to a CODEC_EQInitTypeDef structure which will be initialized.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_codec_eq_init(void)
+ * {
+ *     CODEC_EQInitTypeDef  CODEC_EQInitStruct;
+ *     CODEC_StructInit(&CODEC_EQInitStruct);
+ *     CODEC_EQInitStruct. CODEC_EQChCmd    = EQ_CH_Cmd_ENABLE;
+ *     CODEC_EQInitStruct.CODEC_EQCoefH0    = 0xFF;
+ *     CODEC_EQInitStruct.CODEC_EQCoefB1    = 0xFF;
+ *     CODEC_EQInitStruct.CODEC_EQCoefB2    = 0xFF;
+ *     CODEC_EQInitStruct.CODEC_EQCoefA1    = 0xFF;
+ *     CODEC_EQInitStruct.CODEC_EQCoefA2    = 0xFF;
+ *     CODEC_EQInit(CODEC_EQ1, CODEC_EQInitStruct);
+ * }
+ * \endcode
+ */
+void CODEC_EQStructInit(CODEC_EQInitTypeDef *CODEC_EQInitStruct);
+
+/**
+ * \brief  Enable or disable MIC BIAS output.
+ *
+ * \param[in] CODECx    CODEC peripheral selected. Refer to \ref CODEC_Declaration.
+ * \param[in] NewState  New state of MICBIAS.
+ *                      This parameter can be one of the following values:
+ *                      - ENABLE: Enable the MIC BIAS output.
+ *                      - DISABLE: Disable the MIC BIAS output.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void codec_demo(void)
+ * {
+ *     CODEC_MICBIASCmd(CODEC, ENABLE);
+ * }
+ * \endcode
+ */
+void CODEC_MICBIASCmd(CODEC_TypeDef *CODECx, FunctionalState NewState);
+
+/**
+ * \brief  Reset CODEC.
+ *
+ * \param[in] CODECx  CODEC peripheral selected. Refer to \ref CODEC_Declaration.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void codec_demo(void)
+ * {
+ *     CODEC_Reset(CODEC);
+ * }
+ * \endcode
+ */
+__STATIC_INLINE void CODEC_Reset(CODEC_TypeDef *CODECx)
+{
+    /* Check the parameters */
+    assert_param(IS_CODEC_PERIPH(CODECx));
+    AUDIO_CONTROL_0_t codec_0x100 = {.d32 = CODEC->AUDIO_CONTROL_0};
+
+    /* CODEC IP reset */
+    codec_0x100.b.audio_ip_en = 0;
+    CODEC->AUDIO_CONTROL_0 = codec_0x100.d32;
+    codec_0x100.b.audio_ip_en = 1;
+    CODEC->AUDIO_CONTROL_0 = codec_0x100.d32;
+}
+
+/**
+ * \brief   Config MIC BIAS Vref voltage.
+ *
+ * \param[in] CODECx  CODEC peripheral selected. Refer to \ref CODEC_Declaration.
+ * \param[in] data    New value of MIC BIAS.
+ *                    This parameter can be one of the following values, refer to \ref CODEC_MIC_BIAS_Config.
+ *                    - MICBIAS_VOLTAGE_1_507: Vref voltage is 1.507V.
+ *                    - MICBIAS_VOLTAGE_1_62:  Vref voltage is 1.62V.
+ *                    - MICBIAS_VOLTAGE_1_705: Vref voltage is 1.705V.
+ *                    - MICBIAS_VOLTAGE_1_8: Vref voltage is 1.8V.
+ *                    - MICBIAS_VOLTAGE_1_906: Vref voltage is 1.906V.
+ *                    - MICBIAS_VOLTAGE_2_025:  Vref voltage is 2.025V.
+ *                    - MICBIAS_VOLTAGE_2_16: Vref voltage is 2.16V.
+ *                    - MICBIAS_VOLTAGE_2_314: Vref voltage is 2.314V.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void codec_demo(void)
+ * {
+ *     CODEC_SetMICBIAS(CODEC, MICBIAS_VOLTAGE_1_507);
+ * }
+ * \endcode
+ */
+__STATIC_INLINE void CODEC_SetMICBIAS(CODEC_TypeDef *CODECx,  uint16_t data)
+
+{
+    /* Check the parameters */
+    assert_param(IS_CODEC_PERIPH(CODECx));
+    assert_param(IS_MICBIAS_CONFIG(data));
+    CODEC_ANA_01_BUS_t codec_0x004 = {.d32 = CODEC_ANA->CODEC_ANA_01_BUS};
+
+    codec_0x004.b.MICBIAS_VSET =  data;
+
+    CODEC_ANA->CODEC_ANA_01_BUS = codec_0x004.d32;
+}
+
+/** End of CODEC_Exported_Functions
+  * \}
+  */
+
+/** End of CODEC
+  * \}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RTL_CODEC_H */
diff --git a/bee/drivers/codec/src/device/rtl87x2g/rtl_codec_def.h b/bee/drivers/codec/src/device/rtl87x2g/rtl_codec_def.h
new file mode 100644
index 00000000..c72e7f4f
--- /dev/null
+++ b/bee/drivers/codec/src/device/rtl87x2g/rtl_codec_def.h
@@ -0,0 +1,897 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef RTL_CODEC_DEF_H
+#define RTL_CODEC_DEF_H
+
+#include "utils/rtl_utils.h"
+#include "address_map.h"
+#include "aon_reg.h"
+
+#ifdef  __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/*============================================================================*
+ *                         CODEC Registers Memory Map
+ *============================================================================*/
+typedef struct                  /*!< CODEC_ANA Structure */
+{
+    __IO uint32_t  CODEC_ANA_00_BUS;     /*!< 0x00 */
+    __IO uint32_t  CODEC_ANA_01_BUS;     /*!< 0x04 */
+    __IO uint32_t  CODEC_ANA_02_BUS;     /*!< 0x08 */
+    __IO uint32_t  CODEC_ANA_03_BUS;     /*!< 0x0C */
+    __IO uint32_t  CODEC_ANA_04_BUS;     /*!< 0x10 */
+    __IO uint32_t  PN_SWAP_CTRL;         /*!< 0x14 */
+} CODEC_ANA_TypeDef;
+
+typedef struct                  /*!< CODEC Structure */
+{
+    __IO uint32_t  AUDIO_CONTROL_0;      /*!< 0x100 */
+    __IO uint32_t  AUDIO_CONTROL_1;      /*!< 0x104 */
+    __IO uint32_t  CLOCK_CONTROL_1;      /*!< 0x108 */
+    __IO uint32_t  RSVD0;                /*!< 0x10C */
+    __IO uint32_t  CLOCK_CONTROL_3;      /*!< 0x110 */
+    __IO uint32_t  CLOCK_CONTROL_4;      /*!< 0x114 */
+    __IO uint32_t  CLOCK_CONTROL_7;      /*!< 0x118 */
+    __IO uint32_t  CLOCK_CONTROL_5;      /*!< 0x11C */
+    __IO uint32_t  ASRC_CONTROL_0;       /*!< 0x120 */
+    __IO uint32_t  RSVD1;                /*!< 0x124 */
+    __IO uint32_t  ASRC_CONTROL_RX0;     /*!< 0x128 */
+    __IO  uint32_t RSVD2[5];
+    __IO uint32_t  FS_CONTROL_1;         /*!< 0x140 */
+    __IO uint32_t  FS_CONTROL_3;         /*!< 0x144 */
+    __IO uint32_t  I2S_0_CONTROL;        /*!< 0x148 */
+    __IO  uint32_t RSVD3[6];
+    __IO uint32_t  ADC_0_CONTROL_0;      /*!< 0x164 */
+    __IO uint32_t  ADC_0_CONTROL_1;      /*!< 0x168 */
+    __IO uint32_t  ADC_1_CONTROL_0;      /*!< 0x16C */
+    __IO uint32_t  ADC_1_CONTROL_1;      /*!< 0x170 */
+    __IO  uint32_t RSVD4[8];
+    __IO uint32_t  DAC_L_CONTROL_0;      /*!< 0x194 */
+    __IO uint32_t  DAC_L_CONTROL_1;      /*!< 0x198 */
+    __IO uint32_t  DAC_L_CONTROL_2;      /*!< 0x19C */
+} CODEC_TypeDef;
+
+
+typedef struct
+{
+    __IO uint32_t EQ_H0;                 /*!< 0x40 */
+    __IO uint32_t EQ_B1;                 /*!< 0x44 */
+    __IO uint32_t EQ_B2;                 /*!< 0x48 */
+    __IO uint32_t EQ_A1;                 /*!< 0x4C */
+    __IO uint32_t EQ_A2;                 /*!< 0x50 */
+} CODEC_EQTypeDef;
+
+/*============================================================================*
+ *                          CODEC Declaration
+ *============================================================================*/
+/** \defgroup CODEC       CODEC
+  * \brief
+  * \{
+  */
+
+/** \defgroup CODEC_Exported_Constants CODEC Exported Constants
+  * \brief
+  * \{
+  */
+
+/** \defgroup CODEC_Declaration CODEC Declaration
+  * \{
+  * \ingroup  CODEC_Exported_Constants
+  */
+#define CODEC       ((CODEC_TypeDef     *)0x40022100UL)         //!< CODEC base address.
+#define CODEC_ANA   ((CODEC_ANA_TypeDef *)(SPI_CODEC_REG_BASE ))//!< CODEC analog base address.
+
+/** End of CODEC_Declaration
+  * \}
+  */
+
+/** End of CODEC_Exported_Constants
+  * \}
+  */
+
+/** End of CODEC
+  * \}
+  */
+/*============================================================================*
+ *                          CODEC Private Types
+ *============================================================================*/
+#define CODEC_DAC_L_CR_REG_BASE          0x40022300UL
+#define CODEC_DAC_L_EQ0_REG_BASE         0x40022304UL
+#define CODEC_DAC_L_EQ1_REG_BASE         0x40022318UL
+#define CODEC_DAC_L_EQ2_REG_BASE         0x4002232CUL
+#define CODEC_DAC_L_EQ3_REG_BASE         0x40022340UL
+#define CODEC_DAC_L_EQ4_REG_BASE         0x40022354UL
+#define CODEC_DAC_L_EQ5_REG_BASE         0x40022368UL
+#define CODEC_DAC_L_EQ6_REG_BASE         0x4002237CUL
+#define CODEC_DAC_L_EQ7_REG_BASE         0x40022390UL
+#define CODEC_DAC_L_EQ8_REG_BASE         0x400223A4UL
+#define CODEC_DAC_L_EQ9_REG_BASE         0x400223B8UL
+
+#define CODEC_ADC_CH0_CR_REG_BASE        0x40022500UL
+#define CODEC_ADC_CH0_EQ0_REG_BASE       0x40022504UL
+#define CODEC_ADC_CH0_EQ1_REG_BASE       0x40022518UL
+#define CODEC_ADC_CH0_EQ2_REG_BASE       0x4002252CUL
+#define CODEC_ADC_CH0_EQ3_REG_BASE       0x40022540UL
+#define CODEC_ADC_CH0_EQ4_REG_BASE       0x40022554UL
+
+#define CODEC_ADC_CH1_CR_REG_BASE        0x40022568UL
+#define CODEC_ADC_CH1_EQ0_REG_BASE       0x4002256CUL
+#define CODEC_ADC_CH1_EQ1_REG_BASE       0x40022580UL
+#define CODEC_ADC_CH1_EQ2_REG_BASE       0x40022594UL
+#define CODEC_ADC_CH1_EQ3_REG_BASE       0x400225A8UL
+#define CODEC_ADC_CH1_EQ4_REG_BASE       0x400225BCUL
+
+#define CODEC_DAC_L_CR                   (*((volatile uint32_t *)CODEC_DAC_L_CR_REG_BASE))
+#define CODEC_DAC_L_EQ0                  ((CODEC_EQTypeDef*) CODEC_DAC_L_EQ0_REG_BASE)
+#define CODEC_DAC_L_EQ1                  ((CODEC_EQTypeDef*) CODEC_DAC_L_EQ1_REG_BASE)
+#define CODEC_DAC_L_EQ2                  ((CODEC_EQTypeDef*) CODEC_DAC_L_EQ2_REG_BASE)
+#define CODEC_DAC_L_EQ3                  ((CODEC_EQTypeDef*) CODEC_DAC_L_EQ3_REG_BASE)
+#define CODEC_DAC_L_EQ4                  ((CODEC_EQTypeDef*) CODEC_DAC_L_EQ4_REG_BASE)
+#define CODEC_DAC_L_EQ5                  ((CODEC_EQTypeDef*) CODEC_DAC_L_EQ5_REG_BASE)
+#define CODEC_DAC_L_EQ6                  ((CODEC_EQTypeDef*) CODEC_DAC_L_EQ6_REG_BASE)
+#define CODEC_DAC_L_EQ7                  ((CODEC_EQTypeDef*) CODEC_DAC_L_EQ7_REG_BASE)
+#define CODEC_DAC_L_EQ8                  ((CODEC_EQTypeDef*) CODEC_DAC_L_EQ8_REG_BASE)
+#define CODEC_DAC_L_EQ9                  ((CODEC_EQTypeDef*) CODEC_DAC_L_EQ9_REG_BASE)
+
+#define CODEC_ADC_CH0_CR                 (*((volatile uint32_t *)CODEC_ADC_CH0_CR_REG_BASE))
+#define CODEC_ADC_CH0_EQ0                ((CODEC_EQTypeDef*) CODEC_ADC_CH0_EQ0_REG_BASE)
+#define CODEC_ADC_CH0_EQ1                ((CODEC_EQTypeDef*) CODEC_ADC_CH0_EQ1_REG_BASE)
+#define CODEC_ADC_CH0_EQ2                ((CODEC_EQTypeDef*) CODEC_ADC_CH0_EQ2_REG_BASE)
+#define CODEC_ADC_CH0_EQ3                ((CODEC_EQTypeDef*) CODEC_ADC_CH0_EQ3_REG_BASE)
+#define CODEC_ADC_CH0_EQ4                ((CODEC_EQTypeDef*) CODEC_ADC_CH0_EQ4_REG_BASE)
+
+#define CODEC_ADC_CH1_CR                 (*((volatile uint32_t *)CODEC_ADC_CH1_CR_REG_BASE))
+#define CODEC_ADC_CH1_EQ0                ((CODEC_EQTypeDef*) CODEC_ADC_CH1_EQ0_REG_BASE)
+#define CODEC_ADC_CH1_EQ1                ((CODEC_EQTypeDef*) CODEC_ADC_CH1_EQ1_REG_BASE)
+#define CODEC_ADC_CH1_EQ2                ((CODEC_EQTypeDef*) CODEC_ADC_CH1_EQ2_REG_BASE)
+#define CODEC_ADC_CH1_EQ3                ((CODEC_EQTypeDef*) CODEC_ADC_CH1_EQ3_REG_BASE)
+#define CODEC_ADC_CH1_EQ4                ((CODEC_EQTypeDef*) CODEC_ADC_CH1_EQ4_REG_BASE)
+
+
+/*============================================================================*
+ *                          CODEC Registers and Field Descriptions
+ *============================================================================*/
+//=== start of page0 0x00 ===
+/* 0x00
+    0       R/W    DAC_ADDACK_POW          1'h0
+    7:1     R/W    codec_ana_dummy         7'h0
+    8       R      RSVD                    1'h0
+    9       R/W    DTSDM_CKXEN             1'h1
+    10      R/W    DTSDM_POW_L             1'h0
+    31:11   R      RSVD                    21'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t DAC_ADDACK_POW: 1;
+        uint32_t codec_ana_dummy: 7;
+        const uint32_t reserved_1: 1;
+        uint32_t DTSDM_CKXEN: 1;
+        uint32_t DTSDM_POW_L: 1;
+        const uint32_t reserved_0: 21;
+    } b;
+} CODEC_ANA_00_BUS_t;
+
+
+
+/* 0x04
+    8:0     R/W    codec_ana_01_bus_rsvd   9'h0
+    9       R/W    MICBIAS_ENCHX           1'h1
+    10      R/W    MICBIAS_POW             1'h0
+    13:11   R/W    MICBIAS_VSET            3'h3
+    14      R/W    MICBST_ENDFL            1'h0
+    15      R/W    VREF_POW                1'h0
+    17:16   R/W    MICBST_GSELL            2'h0
+    19:18   R      RSVD                    2'h0
+    21:20   R/W    MICBST_MUTE_L           2'h2
+    24:22   R      RSVD                    3'h0
+    25      R/W    MICBST_POW              1'h0
+    27:26   R/W    VREF_VREFSEL            2'h2
+    31:28   R      RSVD                    4'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t codec_ana_01_bus_rsvd: 9;
+        uint32_t MICBIAS_ENCHX: 1;
+        uint32_t MICBIAS_POW: 1;
+        uint32_t MICBIAS_VSET: 3;
+        uint32_t MICBST_ENDFL: 1;
+        uint32_t VREF_POW: 1;
+        uint32_t MICBST_GSELL: 2;
+        const uint32_t reserved_2: 2;
+        uint32_t MICBST_MUTE_L: 2;
+        const uint32_t reserved_1: 3;
+        uint32_t MICBST_POW: 1;
+        uint32_t VREF_VREFSEL: 2;
+        const uint32_t reserved_0: 4;
+    } b;
+} CODEC_ANA_01_BUS_t;
+
+
+
+/* 0x08
+    7:0     R/W    codec_ana_02_bus_rsvd   8'h0
+    11:8    R/W    MICBIAS_COUNT           4'h1
+    13:12   R/W    MICBIAS_OCSEL           2'h1
+    14      R/W    MICBIAS_POWSHDT         1'h0
+    15      R/W    MICBIAS_ILIMIT          1'h0
+    31:16   R      RSVD                    16'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t codec_ana_02_bus_rsvd: 8;
+        uint32_t MICBIAS_COUNT: 4;
+        uint32_t MICBIAS_OCSEL: 2;
+        uint32_t MICBIAS_POWSHDT: 1;
+        uint32_t MICBIAS_ILIMIT: 1;
+        const uint32_t reserved_0: 16;
+    } b;
+} CODEC_ANA_02_BUS_t;
+
+
+
+/* 0x0C
+    0       R/W    CODEC_DAC_POW           1'h0
+    1       R/W    CODEC_DAC_CK_POW        1'h0
+    2       R/W    CODEC_DAC_CKXEN         1'h4
+    3       R/W    CODEC_DAC_CKXSEL        1'h4
+    4       R/W    CODEC_DAC_OFFSETP_EN    1'h0
+    5       R/W    CODEC_DAC_OFFSETN_EN    1'h0
+    31:6    R      RSVD                    26'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t CODEC_DAC_POW: 1;
+        uint32_t CODEC_DAC_CK_POW: 1;
+        uint32_t CODEC_DAC_CKXEN: 1;
+        uint32_t CODEC_DAC_CKXSEL: 1;
+        uint32_t CODEC_DAC_OFFSETP_EN: 1;
+        uint32_t CODEC_DAC_OFFSETN_EN: 1;
+        const uint32_t reserved_0: 26;
+    } b;
+} CODEC_ANA_03_BUS_t;
+
+
+
+/* 0x10
+    31:0    R/W    codec_RSVD              32'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t codec_RSVD: 32;
+    } b;
+} CODEC_ANA_04_BUS_t;
+
+
+
+/* 0x14
+    0       R/W    dac_l_sdm_inv           1'h0
+    3:1     R      RSVD                    3'h0
+    4       R/W    adc_1_3b_inv            1'h0
+    5       R/W    adc_2_3b_inv            1'h0
+    6       R/W    adc_3_3b_inv            1'h0
+    7       R/W    adc_4_3b_inv            1'h0
+    31:8    R      RSVD                    24'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t dac_l_sdm_inv: 1;
+        const uint32_t reserved_1: 3;
+        uint32_t adc_1_3b_inv: 1;
+        uint32_t adc_2_3b_inv: 1;
+        uint32_t adc_3_3b_inv: 1;
+        uint32_t adc_4_3b_inv: 1;
+        const uint32_t reserved_0: 24;
+    } b;
+} PN_SWAP_CTRL_t;
+//--- end of page 0x00 ---
+
+//=== start of page 0x01 ===
+/* 0x100
+    0       R/W    audio_ip_en                 1'h0
+    1       R/W    daad_lpbk_en                1'h0
+    2       R/W    adda_lpbk_en                1'h0
+    3       R/W    ext_adda_en                 1'h0
+    18:4    R      RSVD                        15'h0
+    23:19   R/W    audio_dbg_sel               5'h0
+    31:24   R      RSVD                        8'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t audio_ip_en: 1;
+        uint32_t daad_lpbk_en: 1;
+        uint32_t adda_lpbk_en: 1;
+        uint32_t ext_adda_en: 1;
+        const uint32_t reserved_1: 15;
+        uint32_t audio_dbg_sel: 5;
+        const uint32_t reserved_0: 8;
+    } b;
+} AUDIO_CONTROL_0_t;
+
+
+
+/* 0x104
+    1:0     R/W    sel_bb_ck_depop             2'h1
+    2       R/W    bb_ck_depop_en              1'h0
+    3       R/W    ckx_micbias_en              1'h0
+    4       R      RSVD                        1'h0
+    5       R/W    pdm_clk_double              1'h0
+    7:6     R/W    pdm_clk_sel                 2'h0
+    9:8     R/W    pdm_ch_swap                 2'h2
+    10      R/W    pdm_data_phase_sel          1'h1
+    11      R/W    pdm_gain_shift_en           1'h1
+    12      R/W    pdm_clk_inv_sel             1'h1
+    13      R/W    i2s_data_rnd_en             1'h1
+    31:14   R      RSVD                        18'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t sel_bb_ck_depop: 2;
+        uint32_t bb_ck_depop_en: 1;
+        uint32_t ckx_micbias_en: 1;
+        const uint32_t reserved_1: 1;
+        uint32_t pdm_clk_double: 1;
+        uint32_t pdm_clk_sel: 2;
+        uint32_t pdm_ch_swap: 2;
+        uint32_t pdm_data_phase_sel: 1;
+        uint32_t pdm_gain_shift_en: 1;
+        uint32_t pdm_clk_inv_sel: 1;
+        uint32_t i2s_data_rnd_en: 1;
+        const uint32_t reserved_0: 18;
+    } b;
+} AUDIO_CONTROL_1_t;
+
+
+
+/* 0x108
+    0       R/W    da_l_en                     1'h0
+    1       R      RSVD                        1'h0
+    2       R/W    mod_l_en                    1'h0
+    3       R      RSVD                        1'h0
+    4       R/W    da_ana_clk_en               1'h0
+    5       R/W    da_fifo_en                  1'h0
+    6       R/W    ad_0_en                     1'h0
+    7       R/W    ad_1_en                     1'h0
+    9:8     R      RSVD                        2'h0
+    10      R/W    ad_fifo_en                  1'h0
+    11      R/W    ad_ana_clk_en               1'h0
+    12      R/W    ad_ana_0_en                 1'h0
+    13      R/W    ad_ana_1_en                 1'h0
+    15:14   R      RSVD                        2'h0
+    16      R/W    ad_0_eq_en                  1'h0
+    17      R/W    ad_1_eq_en                  1'h0
+    19:18   R      RSVD                        2'h0
+    20      R/W    da_l_eq_en                  1'h0
+    31:21   R      RSVD                        11'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t da_l_en: 1;
+        const uint32_t reserved_5: 1;
+        uint32_t mod_l_en: 1;
+        const uint32_t reserved_4: 1;
+        uint32_t da_ana_clk_en: 1;
+        uint32_t da_fifo_en: 1;
+        uint32_t ad_0_en: 1;
+        uint32_t ad_1_en: 1;
+        const uint32_t reserved_3: 2;
+        uint32_t ad_fifo_en: 1;
+        uint32_t ad_ana_clk_en: 1;
+        uint32_t ad_ana_0_en: 1;
+        uint32_t ad_ana_1_en: 1;
+        const uint32_t reserved_2: 2;
+        uint32_t ad_0_eq_en: 1;
+        uint32_t ad_1_eq_en: 1;
+        const uint32_t reserved_1: 2;
+        uint32_t da_l_eq_en: 1;
+        const uint32_t reserved_0: 11;
+    } b;
+} CLOCK_CONTROL_1_t;
+
+// uint32_t RSVD_0X10C[1];
+
+
+
+/* 0x110
+    2:0     R/W    dmic1_clk_sel               3'h1
+    3       R/W    dmic1_clk_en                1'h0
+    4       R/W    dmic1_src_clk_sel           1'h0
+    31:5    R      RSVD                        27'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t dmic1_clk_sel: 3;
+        uint32_t dmic1_clk_en: 1;
+        uint32_t dmic1_src_clk_sel: 1;
+        const uint32_t reserved_0: 27;
+    } b;
+} CLOCK_CONTROL_3_t;
+
+
+
+/* 0x114
+    3:0     R/W    sample_rate_0               4'h0
+    7:4     R/W    sample_rate_1               4'h0
+    31:8    R      RSVD                        24'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t sample_rate_0: 4;
+        uint32_t sample_rate_1: 4;
+        const uint32_t reserved_0: 24;
+    } b;
+} CLOCK_CONTROL_4_t;
+
+
+
+/* 0x118
+    0       R/W    dac_fs_src_sel              1'h0
+    3:1     R      RSVD                        3'h0
+    4       R/W    adc_fs_src_sel              1'h0
+    31:5    R      RSVD                        27'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t dac_fs_src_sel: 1;
+        const uint32_t reserved_1: 3;
+        uint32_t adc_fs_src_sel: 1;
+        const uint32_t reserved_0: 27;
+    } b;
+} CLOCK_CONTROL_7_t;
+
+
+
+/* 0x11C
+    0       R/W    ad_asrc_en                  1'h0
+    5:1     R      RSVD                        5'h0
+    6       R/W    da_asrc_en                  1'h0
+    8:7     R      RSVD                        2'h0
+    9       R/W    da_ana_clk_sel              1'h0
+    10      R/W    ad_ana_clk_sel              1'h0
+    11      R/W    adc_latch_phase             1'h0
+    15:12   R      RSVD                        4'h0
+    16      R/W    ana_clk_rate_sel            1'h0
+    17      R      RSVD                        1'h0
+    19:18   R/W    ad_lpf_clk_sel              2'h0
+    31:20   R      RSVD                        12'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t ad_asrc_en: 1;
+        const uint32_t reserved_4: 5;
+        uint32_t da_asrc_en: 1;
+        const uint32_t reserved_3: 2;
+        uint32_t da_ana_clk_sel: 1;
+        uint32_t ad_ana_clk_sel: 1;
+        uint32_t adc_latch_phase: 1;
+        const uint32_t reserved_2: 4;
+        uint32_t ana_clk_rate_sel: 1;
+        const uint32_t reserved_1: 1;
+        uint32_t ad_lpf_clk_sel: 2;
+        const uint32_t reserved_0: 12;
+    } b;
+} CLOCK_CONTROL_5_t;
+
+
+
+/* 0x120
+    0       R/W    asrc_rate_sel_tx            1'h0
+    1       R      RSVD                        1'h0
+    3:2     R/W    asrc_gain_sel_tx            2'h3
+    4       R/W    asrc_auto_adjust_tx         1'h1
+    7:5     R      RSVD                        3'h0
+    31:8    R/W    asrc_sdm_inti_tx            24'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t asrc_rate_sel_tx: 1;
+        const uint32_t reserved_1: 1;
+        uint32_t asrc_gain_sel_tx: 2;
+        uint32_t asrc_auto_adjust_tx: 1;
+        const uint32_t reserved_0: 3;
+        uint32_t asrc_sdm_inti_tx: 24;
+    } b;
+} ASRC_CONTROL_0_t;
+
+
+/* 0x128
+    0       R/W    asrc_rate_sel_rx            1'h0
+    1       R      RSVD                        1'h0
+    3:2     R/W    asrc_gain_sel_rx            2'h3
+    4       R/W    asrc_auto_adjust_rx         1'h1
+    7:5     R      RSVD                        3'h0
+    31:8    R/W    asrc_sdm_inti_rx            24'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t asrc_rate_sel_rx: 1;
+        const uint32_t reserved_1: 1;
+        uint32_t asrc_gain_sel_rx: 2;
+        uint32_t asrc_auto_adjust_rx: 1;
+        const uint32_t reserved_0: 3;
+        uint32_t asrc_sdm_inti_rx: 24;
+    } b;
+} ASRC_CONTROL_RX0_t;
+
+// uint32_t RSVD_0X12C[5];
+
+
+
+/* 0x140
+    14:0    R/W    fs_frac_n_part              15'h13f
+    15      R      RSVD                        1'h0
+    31:16   R/W    fs_frac_m_part              16'h271
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t fs_frac_n_part: 15;
+        const uint32_t reserved_0: 1;
+        uint32_t fs_frac_m_part: 16;
+    } b;
+} FS_CONTROL_1_t;
+
+
+
+/* 0x144
+    23:0    R/W    fs_integ_part               24'h1d4951
+    24      R/W    fs_update                   1'h0
+    25      R/W    fs_i2s_sync_mode            1'h0
+    27:26   R      RSVD                        2'h0
+    28      R/W    dual_rate_mode              1'h0
+    29      R/W    qual_rate_mode              1'h0
+    31:30   R      RSVD                        2'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t fs_integ_part: 24;
+        uint32_t fs_update: 1;
+        uint32_t fs_i2s_sync_mode: 1;
+        const uint32_t reserved_1: 2;
+        uint32_t dual_rate_mode: 1;
+        uint32_t qual_rate_mode: 1;
+        const uint32_t reserved_0: 2;
+    } b;
+} FS_CONTROL_3_t;
+
+
+
+/* 0x148
+    0       R/W    i2s_0_rst_n                 1'h0
+    1       R/W    i2s_0_inv_sclk              1'h0
+    2       R/W    i2s_0_self_lpbk_en          1'h0
+    3       R/W    i2s_0_same_lrc_en           1'h0
+    5:4     R      RSVD                        2'h0
+    7:6     R/W    i2s_0_data_format_sel_tx    2'h0
+    9:8     R/W    i2s_0_data_format_sel_rx    2'h0
+    11:10   R/W    i2s_0_data_len_sel_tx       2'h0
+    13:12   R/W    i2s_0_data_len_sel_rx       2'h0
+    15:14   R/W    i2s_0_ch_len_sel_tx         2'h1
+    17:16   R/W    i2s_0_ch_len_sel_rx         2'h1
+    19:18   R/W    i2s_0_data_ch_sel_tx        2'h0
+    21:20   R/W    i2s_0_data_ch_sel_rx        2'h0
+    31:22   R      RSVD                        10'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t i2s_0_rst_n: 1;
+        uint32_t i2s_0_inv_sclk: 1;
+        uint32_t i2s_0_self_lpbk_en: 1;
+        uint32_t i2s_0_same_lrc_en: 1;
+        const uint32_t reserved_1: 2;
+        uint32_t i2s_0_data_format_sel_tx: 2;
+        uint32_t i2s_0_data_format_sel_rx: 2;
+        uint32_t i2s_0_data_len_sel_tx: 2;
+        uint32_t i2s_0_data_len_sel_rx: 2;
+        uint32_t i2s_0_ch_len_sel_tx: 2;
+        uint32_t i2s_0_ch_len_sel_rx: 2;
+        uint32_t i2s_0_data_ch_sel_tx: 2;
+        uint32_t i2s_0_data_ch_sel_rx: 2;
+        const uint32_t reserved_0: 10;
+    } b;
+} I2S_0_CONTROL_t;
+
+// uint32_t RSVD_0X14C[6];
+
+
+
+/* 0x164
+    1:0     R/W    adc_0_dmic_src_sel          2'h0
+    7:2     R      RSVD                        6'h0
+    9:8     R/W    adc_0_ad_src_sel            2'h0
+    10      R      RSVD                        1'h0
+    11      R/W    adc_0_ad_lpf2nd_en          1'h1
+    12      R/W    adc_0_ad_lpf1st_en          1'h1
+    14:13   R/W    adc_0_ad_lpf1st_fc_sel      2'h0
+    15      R/W    adc_0_admic_sel             1'h1
+    17:16   R/W    adc_0_ad_zdet_func          2'h2
+    19:18   R/W    adc_0_ad_zdet_tout          2'h0
+    20      R/W    adc_0_ad_mute               1'h0
+    23:21   R      RSVD                        3'h0
+    24      R/W    adc_0_dchpf_en              1'h0
+    27:25   R/W    adc_0_dchpf_fc_sel          3'h4
+    29:28   R/W    adc_0_dmic_lpf2nd_fc_sel    2'h1
+    31:30   R/W    adc_0_ad_lpf2nd_fc_sel      2'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t adc_0_dmic_src_sel: 2;
+        const uint32_t reserved_2: 6;
+        uint32_t adc_0_ad_src_sel: 2;
+        const uint32_t reserved_1: 1;
+        uint32_t adc_0_ad_lpf2nd_en: 1;
+        uint32_t adc_0_ad_lpf1st_en: 1;
+        uint32_t adc_0_ad_lpf1st_fc_sel: 2;
+        uint32_t adc_0_admic_sel: 1;
+        uint32_t adc_0_ad_zdet_func: 2;
+        uint32_t adc_0_ad_zdet_tout: 2;
+        uint32_t adc_0_ad_mute: 1;
+        const uint32_t reserved_0: 3;
+        uint32_t adc_0_dchpf_en: 1;
+        uint32_t adc_0_dchpf_fc_sel: 3;
+        uint32_t adc_0_dmic_lpf2nd_fc_sel: 2;
+        uint32_t adc_0_ad_lpf2nd_fc_sel: 2;
+    } b;
+} ADC_0_CONTROL_0_t;
+
+
+
+/* 0x168
+    8:0     R/W    adc_0_ad_gain               9'h2f
+    11:9    R/W    adc_0_rsvd                  3'h0
+    16:12   R      RSVD                        5'h0
+    17      R/W    adc_0_depop_en              1'h0
+    19:18   R/W    adc_0_depop_time_sel        2'h0
+    31:20   R      RSVD                        12'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t adc_0_ad_gain: 9;
+        uint32_t adc_0_rsvd: 3;
+        const uint32_t reserved_1: 5;
+        uint32_t adc_0_depop_en: 1;
+        uint32_t adc_0_depop_time_sel: 2;
+        const uint32_t reserved_0: 12;
+    } b;
+} ADC_0_CONTROL_1_t;
+
+
+
+/* 0x16C
+    1:0     R/W    adc_1_dmic_src_sel          2'h0
+    7:2     R      RSVD                        6'h0
+    9:8     R/W    adc_1_ad_src_sel            2'h0
+    10      R      RSVD                        1'h0
+    11      R/W    adc_1_ad_lpf2nd_en          1'h1
+    12      R/W    adc_1_ad_lpf1st_en          1'h1
+    14:13   R/W    adc_1_ad_lpf1st_fc_sel      2'h0
+    15      R/W    adc_1_admic_sel             1'h1
+    17:16   R/W    adc_1_ad_zdet_func          2'h2
+    19:18   R/W    adc_1_ad_zdet_tout          2'h0
+    20      R/W    adc_1_ad_mute               1'h0
+    23:21   R      RSVD                        3'h0
+    24      R/W    adc_1_dchpf_en              1'h0
+    27:25   R/W    adc_1_dchpf_fc_sel          3'h4
+    29:28   R/W    adc_1_dmic_lpf2nd_fc_sel    2'h1
+    31:30   R/W    adc_1_ad_lpf2nd_fc_sel      2'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t adc_1_dmic_src_sel: 2;
+        const uint32_t reserved_2: 6;
+        uint32_t adc_1_ad_src_sel: 2;
+        const uint32_t reserved_1: 1;
+        uint32_t adc_1_ad_lpf2nd_en: 1;
+        uint32_t adc_1_ad_lpf1st_en: 1;
+        uint32_t adc_1_ad_lpf1st_fc_sel: 2;
+        uint32_t adc_1_admic_sel: 1;
+        uint32_t adc_1_ad_zdet_func: 2;
+        uint32_t adc_1_ad_zdet_tout: 2;
+        uint32_t adc_1_ad_mute: 1;
+        const uint32_t reserved_0: 3;
+        uint32_t adc_1_dchpf_en: 1;
+        uint32_t adc_1_dchpf_fc_sel: 3;
+        uint32_t adc_1_dmic_lpf2nd_fc_sel: 2;
+        uint32_t adc_1_ad_lpf2nd_fc_sel: 2;
+    } b;
+} ADC_1_CONTROL_0_t;
+
+
+
+/* 0x170
+    8:0     R/W    adc_1_ad_gain               9'h2f
+    11:9    R/W    adc_1_rsvd                  3'h0
+    16:12   R      RSVD                        5'h0
+    17      R/W    adc_1_depop_en              1'h0
+    19:18   R/W    adc_1_depop_time_sel        2'h0
+    31:20   R      RSVD                        12'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t adc_1_ad_gain: 9;
+        uint32_t adc_1_rsvd: 3;
+        const uint32_t reserved_1: 5;
+        uint32_t adc_1_depop_en: 1;
+        uint32_t adc_1_depop_time_sel: 2;
+        const uint32_t reserved_0: 12;
+    } b;
+} ADC_1_CONTROL_1_t;
+
+// uint32_t RSVD_0X174[8];
+
+
+
+/* 0x194
+    7:0     R/W    dac_l_da_gain               8'haf
+    31:8    R      RSVD                        24'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t dac_l_da_gain: 8;
+        const uint32_t reserved_0: 24;
+    } b;
+} DAC_L_CONTROL_0_t;
+
+
+
+/* 0x198
+    1:0     R/W    dac_l_da_zdet_func          2'h2
+    3:2     R/W    dac_l_da_zdet_tout          2'h0
+    4       R/W    dac_l_da_mute               1'h0
+    5       R/W    dac_l_dahpf_en              1'h0
+    7:6     R/W    dac_l_da_dither_sel         2'h0
+    8       R/W    dac_l_dmix_mute_da          1'h0
+    9       R      RSVD                        1'h0
+    10      R/W    dac_l_dmix_mute_dc          1'h1
+    12:11   R      RSVD                        2'h0
+    13      R/W    dac_l_pdm_en                1'h0
+    15:14   R      RSVD                        2'h0
+    17:16   R/W    dac_l_sdm_dither_sel        2'h0
+    21:18   R      RSVD                        4'h0
+    23:22   R/W    dac_l_hpf_fc_sel            2'h1
+    31:24   R      RSVD                        8'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t dac_l_da_zdet_func: 2;
+        uint32_t dac_l_da_zdet_tout: 2;
+        uint32_t dac_l_da_mute: 1;
+        uint32_t dac_l_dahpf_en: 1;
+        uint32_t dac_l_da_dither_sel: 2;
+        uint32_t dac_l_dmix_mute_da: 1;
+        const uint32_t reserved_4: 1;
+        uint32_t dac_l_dmix_mute_dc: 1;
+        const uint32_t reserved_3: 2;
+        uint32_t dac_l_pdm_en: 1;
+        const uint32_t reserved_2: 2;
+        uint32_t dac_l_sdm_dither_sel: 2;
+        const uint32_t reserved_1: 4;
+        uint32_t dac_l_hpf_fc_sel: 2;
+        const uint32_t reserved_0: 8;
+    } b;
+} DAC_L_CONTROL_1_t;
+
+
+
+/* 0x19C
+    15:0    R/W    dac_l_dc_offset             16'h0
+    31:16   R      RSVD                        16'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t dac_l_dc_offset: 16;
+        const uint32_t reserved_0: 16;
+    } b;
+} DAC_L_CONTROL_2_t;
+
+
+
+#ifdef  __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* RTL_CODEC_DEF_H */
+
diff --git a/bee/drivers/codec/src/device/rtl87x2j/rtl_codec.c b/bee/drivers/codec/src/device/rtl87x2j/rtl_codec.c
new file mode 100644
index 00000000..c7dc1a1c
--- /dev/null
+++ b/bee/drivers/codec/src/device/rtl87x2j/rtl_codec.c
@@ -0,0 +1,467 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *                           Header Files
+ *============================================================================*/
+#include "rtl_codec.h"
+#include "rtl_rcc.h"
+#include "utils.h"
+/*============================================================================*
+ *                           Private Macros
+ *============================================================================*/
+#define AUXADC_AON_REG0X1B90              ((AON_NS_REG0X_LDO_TYPE *)0x40001B90UL)
+#define LPC_AON_AUXADC                    ((AON_NS_REG0X_SD_TYPE *)0x40001B98UL)
+#define PERI_ON_ADC_CLOCK_CTRL             *((volatile uint32_t *)0x4000231CUL)
+/*============================================================================*
+ *                           Public Functions
+ *============================================================================*/
+/**
+  * \brief  Initialize the CODEC analog registers in AON area.
+  * \param  None.
+  * \return None
+  */
+void CODEC_AnalogCircuitInit(void)
+{
+    /*Added to stabilize the power supply!*/
+    /* set to LDO mode */
+//    AUXADC_AON_REG0X1B90->hw_pd = 0x0;
+//    AUXADC_AON_REG0X1B90->anapar_pow_ad_0 = 0x1;
+//    platform_delay_us(10);
+//    AUXADC_AON_REG0X1B90->EN_ILIMIT = 0x1;
+//    AUXADC_AON_REG0X1B90->LDOBW  = 0x0;
+//    AUXADC_AON_REG0X1B90->Power = 0x0;
+//    AUXADC_AON_REG0X1B90->anapar_pow_ad_2 = 0x1;
+//    AUXADC_AON_REG0X1B90->REG_LDO_TUNE_6_0 = 0x57; //  7'b1010111
+//    AUXADC_AON_REG0X1B90->SELLDO = 0x1;
+//    platform_delay_us(10);
+//    AUXADC_AON_REG0X1B90->anapar_pow_ad_1 = 0x1;
+
+//    if (AUXADC_AON_REG0X1B90->EN_ILIMIT == 0x0)
+//    {
+//        platform_delay_us(20);
+//    }
+//    else
+//    {
+//        platform_delay_us(15);
+//        AUXADC_AON_REG0X1B90->EN_ILIMIT = 0x0;
+//    }
+//    platform_delay_us(2);
+
+}
+
+/**
+  * \brief  Deinitialize the CODEC analog registers in AON area.
+  * \param  None.
+  * \return None
+  */
+static void CODEC_POF(void)
+{
+    AUDIO_CLOCK_CONTROL_2_TypeDef codec_0x10C = {.d32 = CODEC->AUDIO_CLOCK_CONTROL_2};
+    if ((codec_0x10C.b.dmic1_clk_sel == CODEC_CH_AMIC))
+    {
+        AUDIO_PON_POF_TypeDef  codec_0x020 =  {.d32 = CODEC_ANA->AUDIO_PON_POF};
+        codec_0x020.b.audio_pof_en = 0x1;
+        CODEC_ANA->AUDIO_PON_POF =  codec_0x020.d32;
+        /* Polling audio pon ready init*/
+        while ((CODEC_ANA->AUDIO_INT_CONTROL & 0x2) == 0);
+        /* Clear Audio PON Ready interrupt */
+        CODEC_ANA->AUDIO_INT_CONTROL |= BIT1;
+    }
+    else  // DMIC
+    {
+        AUDIO_PON_POF_TypeDef  codec_0x020 =  {.d32 = CODEC_ANA->AUDIO_PON_POF};
+        codec_0x020.b.audio_pof_en = 0x1;
+        CODEC_ANA->AUDIO_PON_POF =  codec_0x020.d32;
+        /* Polling audio pof ready init*/
+        while ((CODEC_ANA->AUDIO_INT_CONTROL & 0x2) == 0);
+        /* Clear Audio PON Ready interrupt */
+        CODEC_ANA->AUDIO_INT_CONTROL |= BIT1;
+    }
+
+}
+
+/**
+  * \brief  Deinitializes the CODEC peripheral registers to their default reset values(turn off CODEC clock).
+  * \param  CODECx: selected CODEC peripheral.
+  * \return None
+  */
+void CODEC_DeInit(CODEC_TypeDef *CODECx)
+{
+    /* Check the parameters */
+    assert_param(IS_CODEC_PERIPH(CODECx));
+    CODEC_POF();
+    RCC_ClockCmd(CODEC_CLOCK, DISABLE);
+
+
+}
+
+/**
+  * \brief Initializes the CODEC peripheral according to the specified
+  *   parameters in the CODEC_InitStruct
+  * \param  CODECx: selected CODEC peripheral.
+  * \param  CODEC_InitStruct: pointer to a CODEC_InitTypeDef structure that
+  *   contains the configuration information for the specified CODEC peripheral
+  * \return None
+  */
+void CODEC_Init(CODEC_TypeDef *CODECx, CODEC_InitTypeDef *CODEC_InitStruct)
+{
+    /* Check the parameters */
+    /* MIC initialization parameters for input */
+    assert_param(IS_CODEC_PERIPH(CODECx));
+    assert_param(IS_SAMPLE_RATE(CODEC_InitStruct->CODEC_SampleRate));
+    assert_param(IS_CODEC_I2S_DATA_FORMAT(CODEC_InitStruct->CODEC_I2SDataFormat));
+    assert_param(IS_CODEC_I2S_DATA_WIDTH(CODEC_InitStruct->CODEC_I2SDataWidth));
+    assert_param(IS_MICBIAS_CONFIG(CODEC_InitStruct->CODEC_MicBIAS));
+    assert_param(IS_MICBST_MODE(CODEC_InitStruct->CODEC_MicBstMode));
+    assert_param(IS_MICBST_GAIN(CODEC_InitStruct->CODEC_MicBstGain));
+    assert_param(IS_CODEC_DMIC_CLOCK(CODEC_InitStruct->CODEC_DmicClock));
+    /* MIC channel 0 initialization parameters */
+    assert_param(IS_CODEC_CH0_MIC_MUTE(CODEC_InitStruct->CODEC_Ch0Mute));
+    assert_param(IS_CODEC_CH0_MIC_TYPE(CODEC_InitStruct->CODEC_Ch0MicType));
+    assert_param(IS_DMIC_CH0_LATCH_EDGE(CODEC_InitStruct->CODEC_Ch0DmicDataLatch));
+    assert_param(IS_AD_GAIN(CODEC_InitStruct->CODEC_Ch0AdGain));
+    /* MIC channel 1 initialization parameters */
+    assert_param(IS_CODEC_CH1_MIC_MUTE(CODEC_InitStruct->CODEC_Ch1Mute));
+    assert_param(IS_CODEC_CH1_MIC_TYPE(CODEC_InitStruct->CODEC_Ch1MicType));
+    assert_param(IS_DMIC_CH1_LATCH_EDGE(CODEC_InitStruct->CODEC_Ch1DmicDataLatch));
+    assert_param(IS_AD_GAIN(CODEC_InitStruct->CODEC_Ch1AdGain));
+    /* PDM initialization parameters */
+    assert_param(IS_DAC_MUTE(CODEC_InitStruct->CODEC_DaMute));
+    assert_param(IS_DA_GAIN(CODEC_InitStruct->CODEC_DaGain));
+    extern uint8_t (*pmu_get_va18_tune)(void);
+
+    /*get LDO318 form pmu */
+    REG8X_CODEC_ANA_TypeDef codec_0x010 = {.d32 = CODEC_ANA->REG8X_CODEC_ANA};
+    codec_0x010.b.ldo318_aud_tune = pmu_get_va18_tune();
+    CODEC_ANA->REG8X_CODEC_ANA = codec_0x010.d32;
+    
+    ADC_0_CONTROL_0_TypeDef codec_0x120 = {.d32 = CODEC->ADC_0_CONTROL_0};
+    codec_0x120.b.adc_0_admic_sel = CODEC_InitStruct->CODEC_Ch0Mic;
+    CODEC->ADC_0_CONTROL_0 =  codec_0x120.d32;
+
+    AUDIO_PON_POF_TypeDef  codec_0x020 =  {.d32 = CODEC_ANA->AUDIO_PON_POF}; 
+    
+    codec_0x020.b.pon_st1_delay_sel = 0x2;
+    codec_0x020.b.pon_st2_delay_sel = 0x0;
+    codec_0x020.b.pon_st3_delay_sel = 0x2;
+    
+    CODEC_ANA->AUDIO_PON_POF =  codec_0x020.d32;
+    
+    /*Analog performance dependency*/
+    REG6X_CODEC_ANA_TypeDef codec_0x006 = {.d32 = CODEC_ANA->REG6X_CODEC_ANA};
+
+
+    /* Analog initialization */
+    if (((CODEC_InitStruct->CODEC_Ch0Mute == CODEC_CH_UNMUTE) && \
+         (CODEC_InitStruct->CODEC_Ch0Mic == CODEC_CH_AMIC)))
+    {
+        codec_0x006.b.isel_micbias = 0x2;
+        codec_0x006.b.isel_dtsdm = 0x2;
+        codec_0x006.b.isel_micbst = 0x2;
+        CODEC_ANA->REG6X_CODEC_ANA = codec_0x006.d32;
+
+        codec_0x010.b.ldo318_aud_bw_sel = 0x1;
+        CODEC_ANA->REG8X_CODEC_ANA = codec_0x010.d32;
+
+        AUDIO_CLOCK_CONTROL_3_TypeDef codec_0x110 = {.d32 = CODEC->AUDIO_CLOCK_CONTROL_3};
+        codec_0x110.b.ana_clk_rate_sel = 0x1;
+        CODEC->AUDIO_CLOCK_CONTROL_3 = codec_0x110.d32;
+
+        REG2X_CODEC_ANA_TypeDef codec_0x004 = {.d32 = CODEC_ANA->REG2X_CODEC_ANA};
+        codec_0x004.b.micbst_gsel = CODEC_InitStruct->CODEC_MicBstGain;
+        codec_0x004.b.micbst_endf = CODEC_InitStruct->CODEC_MicBstMode;
+        CODEC_ANA->REG2X_CODEC_ANA = codec_0x004.d32;
+
+
+    }
+
+    REG4X_CODEC_ANA_TypeDef codec_0x008 = {.d32 = CODEC_ANA->REG4X_CODEC_ANA};
+    codec_0x008.b.micbias_vset = CODEC_InitStruct->CODEC_MicBiasVolt;
+    CODEC_ANA->REG4X_CODEC_ANA = codec_0x008.d32;
+
+    AUDIO_CLOCK_CONTROL_2_TypeDef codec_0x10C = {.d32 = CODEC->AUDIO_CLOCK_CONTROL_2};
+    /* DMIC clock configuration */
+    if (((CODEC_InitStruct->CODEC_Ch0Mute == CODEC_CH_UNMUTE) && \
+         (CODEC_InitStruct->CODEC_Ch0Mic == CODEC_CH_DMIC)))
+    {
+        codec_0x006.b.isel_micbias = 0x3;
+        CODEC_ANA->REG6X_CODEC_ANA = codec_0x006.d32;
+        codec_0x10C.b.dmic1_clk_sel = CODEC_InitStruct->CODEC_DmicClock;
+    }
+    CODEC->AUDIO_CLOCK_CONTROL_2 =  codec_0x10C.d32;
+
+    /* Configuer mic channel 0 parameters */
+
+    codec_0x120.b.adc_0_ad_mute = CODEC_InitStruct->CODEC_Ch0Mute;
+
+    codec_0x120.b.adc_0_dmic_src_sel = CODEC_InitStruct->CODEC_Ch0DmicDataLatch;
+    codec_0x120.b.adc_0_dchpf_fc_sel = 0x2;  /*3'b000: high corner freq. ~ 3'b111: low corner freq.*/
+    CODEC->ADC_0_CONTROL_0 =  codec_0x120.d32;
+
+    /* Sample rate section */
+    AUDIO_CLOCK_CONTROL_3_TypeDef codec_0x110 = {.d32 = CODEC->AUDIO_CLOCK_CONTROL_3};
+    codec_0x110.b.sample_rate_0 = CODEC_InitStruct->CODEC_SampleRate;
+    CODEC->AUDIO_CLOCK_CONTROL_3 = codec_0x110.d32;
+
+    I2S_0_CONTROL_0_TypeDef codec_0x11C = {.d32 = CODEC->I2S_0_CONTROL_0};
+    codec_0x11C.b.i2s_0_data_len_sel_rx = CODEC_InitStruct->CODEC_I2SDataWidth;
+    codec_0x11C.b.i2s_0_data_format_sel_rx = CODEC_InitStruct->CODEC_I2SDataFormat;
+    codec_0x11C.b.i2s_0_data_ch_sel_rx = CODEC_InitStruct->CODEC_I2SChSequence;
+    CODEC->I2S_0_CONTROL_0 = codec_0x11C.d32;
+
+    ADC_0_CONTROL_1_TypeDef codec_0x124 = {.d32 = CODEC->ADC_0_CONTROL_1};
+    codec_0x124.b.adc_0_ad_gain = CODEC_InitStruct->CODEC_Ch0AdGain;
+    CODEC->ADC_0_CONTROL_1 = codec_0x124.d32;
+
+
+    codec_0x020.b.audio_pon_en = 0x1;
+    CODEC_ANA->AUDIO_PON_POF =  codec_0x020.d32;
+
+    /* Polling audio pon ready init*/
+    while ((CODEC_ANA->AUDIO_INT_CONTROL & 0x1) == 0);
+    /* Clear Audio PON Ready interrupt */
+    CODEC_ANA->AUDIO_INT_CONTROL |= BIT0;
+
+
+}
+
+/**
+  * \brief Initializes the CODEC EQ module according to the specified
+  *   parameters in the CODEC_EQInitStruct
+  * \param  CODEC_EQx: the selected CODEC EQ channel.
+  *   which can be CODEC_CH0_EQ1~CODEC_CH0_EQ5, or CODEC_CH1_EQ1~CODEC_CH1_EQ5.
+  * \param  CODEC_EQInitStruct: pointer to a CODEC_EQInitTypeDef structure that
+  *   contains the configuration information for the specified CODEC EQ channel
+  * \return None
+  */
+void CODEC_EQInit(CODEC_EQTypeDef *CODEC_EQx, CODEC_EQInitTypeDef *CODEC_EQInitStruct)
+{
+    uint32_t bit_pos = 0;
+
+    CODEC_EQx->EQ_H0 = CODEC_EQInitStruct->CODEC_EQCoefH0;
+    CODEC_EQx->EQ_B1 = CODEC_EQInitStruct->CODEC_EQCoefB1;
+    CODEC_EQx->EQ_B2 = CODEC_EQInitStruct->CODEC_EQCoefB2;
+    CODEC_EQx->EQ_A1 = CODEC_EQInitStruct->CODEC_EQCoefA1;
+    CODEC_EQx->EQ_A2 = CODEC_EQInitStruct->CODEC_EQCoefA2;
+
+    if ((((uint32_t)CODEC_EQx) >= CODEC_ADC_CH0_CR_REG_BASE) &&
+        (((uint32_t)CODEC_EQx) <= CODEC_ADC_CH0_EQ4_REG_BASE))
+    {
+        bit_pos = ((uint32_t)CODEC_EQx -  CODEC_ADC_CH0_EQ0_REG_BASE) / 20;
+        if (CODEC_EQInitStruct->CODEC_EQChCmd != DISABLE)
+        {
+            CODEC_ADC_CH0_CR |= ENABLE << bit_pos;
+        }
+        else
+        {
+            CODEC_ADC_CH0_CR &= ~(ENABLE << bit_pos);
+        }
+    }
+}
+
+/**
+  * \brief  Fills each CODEC_InitStruct member with its default value.
+  * \param  CODEC_InitStruct: pointer to an CODEC_InitTypeDef structure which will be initialized.
+  * \return None
+  */
+void CODEC_StructInit(CODEC_InitTypeDef *CODEC_InitStruct)
+{
+    /* Basic parameters section */
+    CODEC_InitStruct->CODEC_SampleRate    = CODEC_SAMPLE_RATE_16KHz;
+    CODEC_InitStruct->CODEC_DmicClock     = CODEC_DMIC_CLOCK_2500KHz;
+
+    CODEC_InitStruct->CODEC_I2SChSequence = CODEC_I2S_CH_SEQ_L_R;
+    CODEC_InitStruct->CODEC_I2SDataWidth  = CODEC_I2S_DATA_WIDTH_16BITS;
+    CODEC_InitStruct->CODEC_I2SDataFormat = CODEC_I2S_DATA_FORMAT_I2S;
+
+    CODEC_InitStruct->CODEC_MicBiasVolt   = CODEC_MICBIAS_VOLTAGE_1_8;
+    CODEC_InitStruct->CODEC_MicBstMode    = CODEC_MICBST_MODE_DIFFERENTIAL;
+    CODEC_InitStruct->CODEC_MicBstGain    = CODEC_MICBST_GAIN_0dB;
+
+    /* MIC channel 0 initialization parameters section */
+    CODEC_InitStruct->CODEC_Ch0Mute          = CODEC_CH_UNMUTE;
+    CODEC_InitStruct->CODEC_Ch0Mic           = CODEC_CH_AMIC;
+    CODEC_InitStruct->CODEC_Ch0DmicDataLatch = CODEC_CH_DMIC_DATA_LATCH_RISING;
+    CODEC_InitStruct->CODEC_Ch0AdGain        = 0x7F;
+    CODEC_InitStruct->CODEC_Ch0DetTimeout    = CODEC_CH_DETTIMEOUT_1024_16_SAMPLE;
+}
+
+
+/**
+  * \brief  Fills each CODEC_EQInitStruct member with its default value.
+  * \param  CODEC_EQInitStruct: pointer to an CODEC_EQInitTypeDef structure which will be initialized.
+  * \return None
+  */
+void CODEC_EQStructInit(CODEC_EQInitTypeDef *CODEC_EQInitStruct)
+{
+    CODEC_EQInitStruct->CODEC_EQChCmd   = DISABLE;
+    /*!< The following all parameters can be 0 to 0x7FFFF, whose physical meaning represents a range of -8 to 7.99 */
+    CODEC_EQInitStruct->CODEC_EQCoefH0  = 0;
+    CODEC_EQInitStruct->CODEC_EQCoefB1  = 0;
+    CODEC_EQInitStruct->CODEC_EQCoefB2  = 0;
+    CODEC_EQInitStruct->CODEC_EQCoefA1  = 0;
+    CODEC_EQInitStruct->CODEC_EQCoefA2  = 0;
+}
+
+/**
+  * \brief  Enable or disable the specified CODEC interrupts.
+  * \param  CODEC: selected CODEC peripheral.
+  * \param  CODEC_INT: specifies the CODEC interrupts sources to be enable or disable.
+  *         This parameter can be the following values:
+  *         \arg CODEC_INT_POF_READY: CODEC power off ready interrupt.
+  *         \arg CODEC_INT_PON_READY: CODEC power on ready interrupt.
+  * \param  NewState: new state of the specified CODEC interrupts.
+  *   This parameter can be: ENABLE or DISABLE.
+  * \return None
+  */
+void CODEC_INTConfig(CODEC_TypeDef *CODECx, uint32_t CODEC_INT, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_CODEC_INT_CONFIG(CODEC_INT));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (NewState == ENABLE)
+    {
+        CODEC_ANA->AUDIO_INT_CONTROL |= CODEC_INT << 8;
+    }
+    else
+    {
+        CODEC_ANA->AUDIO_INT_CONTROL &= ~(CODEC_INT << 8);
+    }
+}
+
+/**
+  * \brief  Mask the specified CODEC interrupt
+  * \param  CODEC: selected CODEC peripheral.
+  * \param  CODEC_INT: specifies the CODEC interrupts sources to be enable or disable.
+  *         This parameter can be the following values:
+  *         \arg CODEC_INT_POF_READY: CODEC power off ready interrupt.
+  *         \arg CODEC_INT_PON_READY: CODEC power on ready interrupt.
+  * \param  NewState: new state of the specified CODEC interrupts.
+  *   This parameter can be: ENABLE or DISABLE.
+  * \return None
+  */
+void CODEC_MaskINTConfig(CODEC_TypeDef *CODECx, uint32_t CODEC_INT, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_CODEC_INT_CONFIG(CODEC_INT));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (NewState == ENABLE)
+    {
+        CODEC_ANA->AUDIO_INT_CONTROL |= CODEC_INT << 16;
+    }
+    else
+    {
+        CODEC_ANA->AUDIO_INT_CONTROL &= ~(CODEC_INT << 16);
+    }
+}
+
+/**
+  * \brief  Get the specified CODEC flag status.
+  * \param  CODEC: selected CODEC peripheral.
+  * \param  CODEC_INT: the specified CODEC interrupt.
+  *         This parameter can be one of the following values:
+  *         \arg CODEC_INT_POF_READY: CODEC power off ready interrupt.
+  *         \arg CODEC_INT_PON_READY: CODEC power on ready interrupt.
+  * \return The new state of FLAG (SET or RESET).
+  */
+ITStatus CODEC_GetINTStatus(CODEC_TypeDef *CODECx, uint32_t CODEC_INT)
+{
+    ITStatus bit_status = RESET;
+
+    /* Check the parameters */
+    assert_param(IS_CODEC_INT_CONFIG(CODEC_INT));
+
+    if ((CODEC_ANA->AUDIO_INT_CONTROL & (CODEC_INT & 0x3)))
+    {
+        bit_status = SET;
+    }
+
+    /* Return the I2S_INT status */
+    return  bit_status;
+}
+
+/**
+  * \brief  Clears the CODEC interrupt pending bits.
+  * \param  CODEC: selected CODEC peripheral.
+  * \param  CODEC_CLEAR_INT: specifies the interrupt pending bit to clear.
+  *         This parameter can be any combination of the following values:
+  *         This parameter can be the following values:
+  *         \arg CODEC_INT_POF_READY: CODEC power off ready interrupt.
+  *         \arg CODEC_INT_PON_READY: CODEC power on ready interrupt.
+  * \return None
+  */
+void CODEC_ClearINTPendingBit(CODEC_TypeDef *CODECx, uint32_t CODEC_CLEAR_INT)
+{
+    /* Check the parameters */
+    assert_param(IS_I2S_INT_CONFIG(I2S_CLEAR_INT));
+    CODEC_ANA->AUDIO_INT_CONTROL |= CODEC_CLEAR_INT;
+}
+/**
+  * \brief  Enable or disable mic_bias output.
+  * \param  CODECx: selected CODEC peripheral.
+  * \param  NewState: new state of MICBIAS.
+  *   This parameter can be: ENABLE or DISABLE.
+  * \return none.
+  */
+void CODEC_MicBiasCmd(CODEC_TypeDef *CODECx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_CODEC_PERIPH(CODECx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    REG4X_CODEC_ANA_TypeDef codec_0x008 = {.d32 = CODEC_ANA->REG4X_CODEC_ANA};
+    AUDIO_ANA_CONTROL_1_TypeDef codec_0x104 = {.d32 = CODEC->AUDIO_ANA_CONTROL_1};
+    if (NewState == ENABLE)
+    {
+        if (!(codec_0x008.b.micbias_pow))
+        {
+            /* Analog initialization in AON register */
+            CODEC_AnalogCircuitInit();
+
+            /* MICBIAS power on */
+            codec_0x008.b.micbias_pow = 0x1;
+            codec_0x008.b.micbias_enchx = 0x1;
+
+            /* Clock enable */
+            codec_0x104.b.ckx_micbias_en = 0x1;
+        }
+    }
+    else
+    {
+        codec_0x008.b.micbias_pow = 0x0;
+        codec_0x008.b.micbias_enchx = 0x0;
+    }
+    CODEC_ANA->REG4X_CODEC_ANA = codec_0x008.d32;
+    CODEC->AUDIO_ANA_CONTROL_1 = codec_0x104.d32;
+}
+
+void CODEC_Reset(CODEC_TypeDef *CODECx)
+{
+    /* Check the parameters */
+    assert_param(IS_CODEC_PERIPH(CODECx));
+
+    /* CODEC IP reset */
+    AUDIO_CONTROL_1_TypeDef codec_0x100 = {.d32 = CODEC->AUDIO_CONTROL_1};
+    codec_0x100.b.audio_ip_en = 0;
+    CODEC->AUDIO_CONTROL_1 = codec_0x100.d32;
+    codec_0x100.b.audio_ip_en = 1;
+    CODEC->AUDIO_CONTROL_1 = codec_0x100.d32;
+}
+
+void CODEC_SetMicBias(CODEC_TypeDef *CODECx, uint16_t Data)
+{
+    /* Check the parameters */
+    assert_param(IS_CODEC_PERIPH(CODECx));
+    assert_param(IS_MICBIAS_CONFIG(data));
+
+    REG4X_CODEC_ANA_TypeDef codec_0x008 = {.d32 = CODEC_ANA->REG4X_CODEC_ANA};
+    codec_0x008.b.micbias_vset = Data;
+    CODEC_ANA->REG4X_CODEC_ANA = codec_0x008.d32;
+}
+
diff --git a/bee/drivers/codec/src/device/rtl87x2j/rtl_codec.h b/bee/drivers/codec/src/device/rtl87x2j/rtl_codec.h
new file mode 100644
index 00000000..8962553c
--- /dev/null
+++ b/bee/drivers/codec/src/device/rtl87x2j/rtl_codec.h
@@ -0,0 +1,724 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *               Define to prevent recursive inclusion
+ *============================================================================*/
+#ifndef RTL_CODEC_H
+#define RTL_CODEC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*============================================================================*
+ *                        Header Files
+ *============================================================================*/
+#include "utils/rtl_utils.h"
+#if defined (CONFIG_SOC_SERIES_RTL87X2G)
+#include "codec/src/rtl87x2g/rtl_codec_def.h"
+#elif defined (CONFIG_SOC_SERIES_RTL87X2J)
+#include "codec/src/rtl87x2j/rtl_codec_def.h"
+#endif
+
+/** \defgroup CODEC       CODEC
+  * \brief
+  * \{
+  */
+
+/*============================================================================*
+ *                         Constants
+ *============================================================================*/
+/** \defgroup CODEC_Exported_Constants CODEC Exported Constants
+  * \brief
+  * \{
+  */
+
+/**
+ * \defgroup    CODEC_I2S_Data_Width CODEC I2S Data Width
+ * \{
+ * \ingroup     CODEC_Exported_Constants
+ */
+typedef enum
+{
+    CODEC_I2S_DATA_WIDTH_16BITS,
+    CODEC_I2S_DATA_WIDTH_24BITS = 0x2,
+    CODEC_I2S_DATA_WIDTH_8BITS = 0x3,
+    CODEC_I2S_DATA_WIDTH_MAX,
+} CODECI2SDataWidth_TypeDef;
+
+#define IS_CODEC_I2S_DATA_WIDTH(WIDTH) (((WIDTH) == CODEC_I2S_DATA_WIDTH_16BITS) || \
+                                        ((WIDTH) == CODEC_I2S_DATA_WIDTH_24BITS) || \
+                                        ((WIDTH) == CODEC_I2S_DATA_WIDTH_8BITS))
+
+
+/** End of CODEC_I2S_Data_Width
+  * \}
+  */
+
+/**
+ * \defgroup    CODEC_I2S_Data_Format CODEC I2S Data Format
+ * \{
+ * \ingroup     CODEC_Exported_Constants
+ */
+typedef enum
+{
+    CODEC_I2S_DATA_FORMAT_I2S,
+    CODEC_I2S_DATA_FORMAT_LEFT_JUSTIFIED,
+    CODEC_I2S_DATA_FORMAT_PCM_A,
+    CODEC_I2S_DATA_FORMAT_PCM_B,
+    CODEC_I2S_DATA_FORMAT_MAX,
+} CODECI2SDataFormat_TypeDef;
+
+#define IS_CODEC_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == CODEC_I2S_DATA_FORMAT_I2S) || \
+                                          ((FORMAT) == CODEC_I2S_DATA_FORMAT_LEFT_JUSTIFIED) || \
+                                          ((FORMAT) == CODEC_I2S_DATA_FORMAT_PCM_A) || \
+                                          ((FORMAT) == CODEC_I2S_DATA_FORMAT_PCM_B))
+
+/** End of CODEC_I2S_Data_Format
+  * \}
+  */
+
+\
+/**
+ * \defgroup    CODEC_I2S_Ch_Seq CODEC I2S Ch Seq
+ * \{
+ * \ingroup     CODEC_Exported_Constants
+ */
+typedef enum
+{
+    CODEC_I2S_CH_SEQ_L_R,
+    CODEC_I2S_CH_SEQ_R_L,
+    CODEC_I2S_CH_SEQ_L_L,
+    CODEC_I2S_CH_SEQ_R_R,
+    CODEC_I2S_CH_SEQ_SEL_MAX,
+} CODECI2SChSeq_TypeDef;
+
+#define IS_CODEC_I2S_CH_SEQ(CH) (((CH) == CODEC_I2S_CH_SEQ_L_R) || \
+                                 ((CH) == CODEC_I2S_CH_SEQ_R_L) || \
+                                 ((CH) == CODEC_I2S_CH_SEQ_L_L) || \
+                                 ((CH) == CODEC_I2S_CH_SEQ_R_R))
+
+/** End of CODEC_I2S_Ch_Seq
+  * \}
+  */
+
+/**
+ * \defgroup    CODEC_Sample_Rate CODEC Sample Rate
+ * \{
+ * \ingroup     CODEC_Exported_Constants
+ */
+typedef enum
+{
+    CODEC_SAMPLE_RATE_48KHz = 0,    // 0: 48KHz
+    CODEC_SAMPLE_RATE_32KHz = 3,    // 3: 32KHz
+    CODEC_SAMPLE_RATE_16KHz = 5,    // 5: 16KHz
+    CODEC_SAMPLE_RATE_8KHz = 7,     // 7: 8KHz
+    CODEC_SAMPLE_RATE_44100Hz = 8,  // 8: 44.1KHz
+    CODEC_SAMPLE_RATE_24KHz = 10,    // 10: 24KHz
+    CODEC_SAMPLE_RATE_12KHz = 11,    // 11: 12KHz
+    CODEC_SAMPLE_RATE_22050Hz = 12, // 12: 22.05KHz
+    CODEC_SAMPLE_RATE_11025Hz = 13, // 13: 11.025KHz
+    CODEC_SAMPLE_RATE_NUM,
+} CODECSampleRate_TypeDef;
+
+#define IS_SAMPLE_RATE(RATE) (((RATE) == CODEC_SAMPLE_RATE_48KHz)   ||((RATE) == CODEC_SAMPLE_RATE_32KHz)    || \
+                              ((RATE) == CODEC_SAMPLE_RATE_16KHz)   || ((RATE) == CODEC_SAMPLE_RATE_8KHz)   || \
+                              ((RATE) == CODEC_SAMPLE_RATE_44100Hz) || ((RATE) == CODEC_SAMPLE_RATE_24KHz) || \
+                              ((RATE) == CODEC_SAMPLE_RATE_12KHz)   || ((RATE) == CODEC_SAMPLE_RATE_22050Hz) || \
+                              ((RATE) == CODEC_SAMPLE_RATE_11025Hz))
+
+/** End of CODEC_Sample_Rate
+  * \}
+  */
+
+
+/**
+ * \defgroup    CODEC_DMIC_Clock CODEC DMIC Clock
+ * \{
+ * \ingroup     CODEC_Exported_Constants
+ */
+typedef enum
+{
+    CODEC_DMIC_CLOCK_5MHz,
+    CODEC_DMIC_CLOCK_2500KHz,
+    CODEC_DMIC_CLOCK_1250KHz,
+    CODEC_DMIC_CLOCK_625KHz,
+    CODEC_DMIC_CLOCK_312500Hz,
+    CODEC_DMIC_CLOCK_SEL_MAX,
+} CODECDmicClock_TypeDef;
+
+#define IS_CODEC_DMIC_CLOCK(CLOCK) (((CLOCK) == CODEC_DMIC_CLOCK_5MHz) || \
+                                    ((CLOCK) == CODEC_DMIC_CLOCK_2500KHz) || \
+                                    ((CLOCK) == CODEC_DMIC_CLOCK_1250KHz) || \
+                                    ((CLOCK) == CODEC_DMIC_CLOCK_625KHz) || \
+                                    ((CLOCK) == CODEC_DMIC_CLOCK_312500Hz))
+
+/** End of CODEC_DMIC_Clock
+  * \}
+  */
+
+/**
+ * \defgroup    CODEC_MicBias_Voltage CODEC MicBias Voltage
+ * \{
+ * \ingroup     CODEC_Exported_Constants
+ */
+typedef enum
+{
+    CODEC_MICBIAS_VOLTAGE_1_507,
+    CODEC_MICBIAS_VOLTAGE_1_62,
+    CODEC_MICBIAS_VOLTAGE_1_705,
+    CODEC_MICBIAS_VOLTAGE_1_8,
+    CODEC_MICBIAS_VOLTAGE_1_906,
+    CODEC_MICBIAS_VOLTAGE_2_025,
+    CODEC_MICBIAS_VOLTAGE_2_16,
+    CODEC_MICBIAS_VOLTAGE_2_314,
+} CODECMicBiasVoltage_TypeDef;
+
+#define IS_CODEC_MICBIAS_VOLTAGE(VOLTAGE) (((VOLTAGE) == CODEC_MICBIAS_VOLTAGE_1_507) || \
+                                           ((VOLTAGE) == CODEC_MICBIAS_VOLTAGE_1_62)  || \
+                                           ((VOLTAGE) == CODEC_MICBIAS_VOLTAGE_1_705) || \
+                                           ((VOLTAGE) == CODEC_MICBIAS_VOLTAGE_1_8)   || \
+                                           ((VOLTAGE) == CODEC_MICBIAS_VOLTAGE_1_906) || \
+                                           ((VOLTAGE) == CODEC_MICBIAS_VOLTAGE_2_025) || \
+                                           ((VOLTAGE) == CODEC_MICBIAS_VOLTAGE_2_16)  || \
+                                           ((VOLTAGE) == CODEC_MICBIAS_VOLTAGE_2_314))
+
+/** End of CODEC_MicBias_Voltage
+  * \}
+  */
+
+/**
+ * \defgroup    CODEC_MicBst_Gain CODEC MicBst Gain
+ * \{
+ * \ingroup     CODEC_Exported_Constants
+ */
+typedef enum
+{
+    CODEC_MICBST_GAIN_0dB,
+    CODEC_MICBST_GAIN_3dB,
+    CODEC_MICBST_GAIN_6dB,
+    CODEC_MICBST_GAIN_9dB,
+    CODEC_MICBST_GAIN_12dB,
+    CODEC_MICBST_GAIN_18dB,
+    CODEC_MICBST_GAIN_24dB,
+    CODEC_MICBST_GAIN_30dB,
+} CODECMicBstGain_TypeDef;
+
+#define IS_CODEC_MICBST_GAIN(GAIN) (((GAIN) == CODEC_MICBST_GAIN_0dB) || \
+                                    ((GAIN) == CODEC_MICBST_GAIN_3dB) || \
+                                    ((GAIN) == CODEC_MICBST_GAIN_6dB) || \
+                                    ((GAIN) == CODEC_MICBST_GAIN_9dB) || \
+                                    ((GAIN) == CODEC_MICBST_GAIN_12dB) || \
+                                    ((GAIN) == CODEC_MICBST_GAIN_18dB) || \
+                                    ((GAIN) == CODEC_MICBST_GAIN_24dB) || \
+                                    ((GAIN) == CODEC_MICBST_GAIN_30dB))
+
+/** End of CODEC_MicBst_Gain
+  * \}
+  */
+
+/**
+ * \defgroup    CODEC_Ch0_Boost_Gain CODEC Ch0 Boost Gain
+ * \{
+ * \ingroup     CODEC_Exported_Constants
+ */
+typedef enum
+{
+    CODEC_CH0_BOOST_GAIN_0dB,
+    CODEC_CH0_BOOST_GAIN_12dB,
+    CODEC_CH0_BOOST_GAIN_24dB,
+    CODEC_CH0_BOOST_GAIN_36dB,
+} CODECCH0_Boost_Gain_TypeDef;
+
+#define IS_CH0_BOOST_GAIN(GAIN) (((GAIN) == CODEC_CH0_BOOST_GAIN_0dB) || \
+                                 ((GAIN) == CODEC_CH0_BOOST_GAIN_12dB) || \
+                                 ((GAIN) == CODEC_CH0_BOOST_GAIN_24dB) || \
+                                 ((GAIN) == CODEC_CH0_BOOST_GAIN_36dB)))
+
+/** End of CODEC_MicBst_Gain
+  * \}
+  */
+/**
+ * \defgroup    CODEC_MicBst_Mode CODEC MicBst Mode
+ * \{
+ * \ingroup     CODEC_Exported_Constants
+ */
+typedef enum
+{
+    CODEC_MICBST_MODE_SINGLE,
+    CODEC_MICBST_MODE_DIFFERENTIAL,
+} CODECMicBstMode_TypeDef;
+
+#define IS_CODEC_MICBST_MODE(MODE) (((MODE) == CODEC_MICBST_MODE_SINGLE) || \
+                                    ((MODE) == CODEC_MICBST_MODE_DIFFERENTIAL))
+
+/** End of CODEC_MicBst_Mode
+  * \}
+  */
+
+/**
+ * \defgroup    CODEC_Ch_Mute CODEC Ch Mute
+ * \{
+ * \ingroup     CODEC_Exported_Constants
+ */
+typedef enum
+{
+    CODEC_CH_UNMUTE,
+    CODEC_CH_MUTE,
+} CODECChMute_TypeDef;
+
+#define IS_CODEC_CH_MUTE(MUTE) (((MUTE) == CODEC_CH_MUTE) || \
+                                ((MUTE) == CODEC_CH_UNMUTE))
+
+/** End of CODEC_Ch_Mute
+  * \}
+  */
+
+/**
+ * \defgroup    CODEC_Ch_Mic CODEC Ch Mic
+ * \{
+ * \ingroup     CODEC_Exported_Constants
+ */
+typedef enum
+{
+    CODEC_CH_DMIC,
+    CODEC_CH_AMIC,
+} CODECChMic_TypeDef;
+
+#define IS_CODEC_CH_MIC(MIC) (((MIC) == CODEC_CH_AMIC) || \
+                              ((MIC) == CODEC_CH_DMIC))
+
+/** End of CODEC_Ch_Mic
+  * \}
+  */
+
+/**
+ * \defgroup    CODEC_Ch_Dmic_Data_Latch Dmic Data Latch
+ * \{
+ * \ingroup     CODEC_Exported_Constants
+ */
+typedef enum
+{
+    CODEC_CH_DMIC_DATA_LATCH_RISING,
+    CODEC_CH_DMIC_DATA_LATCH_FALLING,
+} CODECChDmicDataLatch_TypeDef;
+
+#define IS_CODEC_DMIC_DATA_LATCh(EDGE) (((EDGE) == CODEC_CH_DMIC_DATA_LATCH_RISING) || \
+                                        ((EDGE) == CODEC_CH_DMIC_DATA_LATCH_FALLING))
+
+/** End of CODEC_Ch_Dmic_Data_Latch
+  * \}
+  */
+
+/**
+ * \defgroup    CODEC_Ch_Detection_Timeout CODEC Ch Detection Timeout
+ * \{
+ * \ingroup     CODEC_Exported_Constants
+ */
+typedef enum
+{
+    CODEC_CH_DETTIMEOUT_1024_16_SAMPLE,
+    CODEC_CH_DETTIMEOUT_1024_32_SAMPLE,
+    CODEC_CH_DETTIMEOUT_1024_64_SAMPLE,
+    CODEC_CH_DETTIMEOUT_64_SAMPLE,//??
+} CODECChDetTimeout_TypeDef;
+
+#define IS_CODEC_CH_DET_TIMEOUT(TIMEOUT) (((TIMEOUT) == CODEC_CH_DETTIMEOUT_1024_16_SAMPLE) || \
+                                          ((TIMEOUT) == CODEC_CH_DETTIMEOUT_1024_32_SAMPLE) || \
+                                          ((TIMEOUT) == CODEC_CH_DETTIMEOUT_1024_64_SAMPLE) || \
+                                          ((TIMEOUT) == CODEC_CH_DETTIMEOUT_64_SAMPLE))
+
+/** End of CODEC_Ch_Detection_Timeout
+  * \}
+  */
+
+/**
+ * \defgroup    CODEC_AD_Gain CODEC AD Gain
+ * \{
+ * \ingroup     CODEC_Exported_Constants
+ */
+#define IS_CODEC_AD_GAIN(GAIN)            (((GAIN)<= 0x7F))
+
+/** End of CODEC_Ad_Gain
+  * \}
+  */
+
+/**
+ * \defgroup    CODEC_Interrupt_Definition   CODEC Interrupt Definition
+ * \{
+ * \ingroup     CODEC_Exported_Constants
+ */
+#if CODEC_SUPPORT_INT
+#define CODEC_INT_POF_READY                            BIT1
+#define CODEC_INT_PON_READY                            BIT0
+
+#define IS_CODEC_INT_CONFIG(INT)          (((INT) == CODEC_INT_POF_READY) || ((INT) == CODEC_INT_POF_READY) )
+
+#endif
+/** End of CODEC_Interrupt_Definition
+  * \}
+  */
+
+/** End of CODEC_Exported_Constants
+  * \}
+  */
+
+/*============================================================================*
+ *                         Types
+ *============================================================================*/
+/** \defgroup CODEC_Exported_Types CODEC Exported Types
+  * \brief
+  * \{
+  */
+
+/**
+ * \brief       CODEC initialize parameters.
+ *
+ * \ingroup     CODEC_Exported_Types
+ */
+typedef struct
+{
+    /* Basic parameters section */
+    CODECSampleRate_TypeDef CODEC_SampleRate;       /*!< Specifies the sample rate . */
+
+    CODECDmicClock_TypeDef CODEC_DmicClock;         /*!< Specifies the dmic clock. */
+
+    CODECI2SDataFormat_TypeDef
+    CODEC_I2SDataFormat; /*!< Specifies the I2S Tx/Rx format of codec port. */
+
+    CODECI2SDataWidth_TypeDef CODEC_I2SDataWidth;   /*!< Specifies the I2Sdata width of codec port. */
+
+    CODECI2SChSeq_TypeDef CODEC_I2SChSequence; /*!< Specifies the I2S Tx/Rx channel sequence. */
+
+    CODECMicBiasVoltage_TypeDef CODEC_MicBiasVolt;  /*!< Specifies the MICBIAS voltage. */
+
+    CODECMicBstGain_TypeDef CODEC_MicBstGain;       /*!< Specifies the MicBst gain. */
+
+    CODECMicBstMode_TypeDef CODEC_MicBstMode;       /*!< Specifies the MicBst mode. */
+
+    /* MIC channel 0 initialization parameters section */
+    CODECChMute_TypeDef CODEC_Ch0Mute;              /*!< Specifies the channel 0 dmic mute status. */
+
+    CODECChMic_TypeDef
+    CODEC_Ch0Mic;                /*!< Specifies the channel 0 mic type, which can be dmic or amic. */
+
+    CODECChDmicDataLatch_TypeDef
+    CODEC_Ch0DmicDataLatch; /*!< Specifies the channel 0 dmic data latch type. */
+
+    uint32_t CODEC_Ch0AdGain;                       /*!< Specifies the channel 0 ADC digital volume. -17.625dB~+30dB in 0.375 dB step */
+
+    CODECChDetTimeout_TypeDef
+    CODEC_Ch0DetTimeout;  /*!< Specifies the channel 0 zero detection timeout mode control. */
+    CODECCH0_Boost_Gain_TypeDef CODEC_Ch0BoostGain;        /*!< Specify the channel 0 boost gain. */
+} CODEC_InitTypeDef;
+
+
+/**
+ * \brief       CODEC EQ part initialize parameters.
+ *
+ * \ingroup     CODEC_Exported_Types
+ */
+typedef struct
+{
+    uint32_t CODEC_EQChCmd;             /*!< Specifies the EQ channel status */
+
+    uint32_t CODEC_EQCoefH0;            /*!< Specifies the EQ coef.h0. This value can be 0 to 0x7FFFF,
+                                             whose physical meaning represents a range of-8 to 7.99 */
+
+    uint32_t CODEC_EQCoefB1;            /*!< Specifies the EQ coef.b1. This value can be 0 to 0x7FFFF,
+                                             whose physical meaning represents a range of-8 to 7.99 */
+
+    uint32_t CODEC_EQCoefB2;            /*!< Specifies the EQ coef.b2. This value can be 0 to 0x7FFFF,
+                                             whose physical meaning represents a range of-8 to 7.99 */
+
+    uint32_t CODEC_EQCoefA1;            /*!< Specifies the EQ coef.a1. This value can be 0 to 0x7FFFF,
+                                             whose physical meaning represents a range of-8 to 7.99 */
+
+    uint32_t CODEC_EQCoefA2;            /*!< Specifies the EQ coef.a2. This value can be 0 to 0x7FFFF,
+                                             whose physical meaning represents a range of-8 to 7.99 */
+} CODEC_EQInitTypeDef;
+
+/** End of CODEC_Exported_Types
+  * \}
+  */
+
+/*============================================================================*
+ *                         Functions
+ *============================================================================*/
+/** \defgroup CODEC_Exported_Functions CODEC Exported Functions
+  * \brief
+  * \{
+  */
+
+/**
+ * \brief   Deinitializes the CODEC peripheral registers to their default reset values(turn off CODEC clock).
+ * \param[in] CODECx: CODEC peripheral selected .
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_codec_init(void)
+ * {
+ *     CODEC_DeInit(CODEC);
+ * }
+ * \endcode
+ */
+void CODEC_DeInit(CODEC_TypeDef *CODECx);
+/**
+  * \brief    Initialize the CODEC analog registers in AON area.
+  * \param  None.
+  * \retval None
+*
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_codec_init(void)
+ * {
+ *     RCC_ClockCmd(CODEC_CLOCK, ENABLE);
+ *     CODEC_AnalogCircuitInit();
+ *     CODEC_InitTypeDef CODEC_InitStruct;
+
+ *     CODEC_StructInit(&CODEC_InitStruct);
+ *     CODEC_InitStruct.CODEC_Ch0MicType       = CODEC_Ch0_AMIC;
+ *     CODEC_InitStruct.CODEC_MicBstMode       = MICBST_Mode_Differential;
+ *     CODEC_InitStruct.CODEC_SampleRate       = SAMPLE_RATE_16KHz;
+ *     CODEC_InitStruct.CODEC_I2SDataFormat    = CODEC_I2S_DATA_FORMAT_I2S;
+ *     CODEC_InitStruct.CODEC_I2SDataWidth     = CODEC_I2S_DATA_WIDTH_16BITS;
+ *     CODEC_Init(CODEC, &CODEC_InitStruct);
+ * }
+ * \endcode
+ */
+void CODEC_AnalogCircuitInit(void);
+/**
+ * \brief   Initializes the CODEC peripheral according to the specified
+ *          parameters in the CODEC_InitStruct.
+ * \param[in] CODECx: CODEC peripheral selected.
+ * \param[in] CODEC_InitStruct: Pointer to a CODEC_InitTypeDef structure that
+ *            contains the configuration information for the specified CODEC peripheral
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_codec_init(void)
+ * {
+ *     RCC_ClockCmd(CODEC_CLOCK, ENABLE);
+ *
+ *     CODEC_InitTypeDef CODEC_InitStruct;
+
+ *     CODEC_StructInit(&CODEC_InitStruct);
+ *     CODEC_InitStruct.CODEC_Ch0MicType       = CODEC_Ch0_AMIC;
+ *     CODEC_InitStruct.CODEC_MicBstMode       = MICBST_Mode_Differential;
+ *     CODEC_InitStruct.CODEC_SampleRate       = SAMPLE_RATE_16KHz;
+ *     CODEC_InitStruct.CODEC_I2SDataFormat    = CODEC_I2S_DATA_FORMAT_I2S;
+ *     CODEC_InitStruct.CODEC_I2SDataWidth     = CODEC_I2S_DATA_WIDTH_16BITS;
+ *     CODEC_Init(CODEC, &CODEC_InitStruct);
+ * }
+ * \endcode
+ */
+void CODEC_Init(CODEC_TypeDef *CODECx, CODEC_InitTypeDef *CODEC_InitStruct);
+
+/**
+ * \brief   Fills each CODEC_InitStruct member with its default value.
+ * \param[in] CODEC_InitStruct: Pointer to a CODEC_InitTypeDef structure which will be initialized.
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_codec_init(void)
+ * {
+ *     RCC_ClockCmd(CODEC_CLOCK, ENABLE);
+ *
+ *     CODEC_InitTypeDef CODEC_InitStruct;
+
+ *     CODEC_StructInit(&CODEC_InitStruct);
+ *     CODEC_InitStruct.CODEC_Ch0MicType       = CODEC_Ch0_AMIC;
+ *     CODEC_InitStruct.CODEC_MicBstMode       = MICBST_Mode_Differential;
+ *     CODEC_InitStruct.CODEC_SampleRate       = SAMPLE_RATE_16KHz;
+ *     CODEC_InitStruct.CODEC_I2SDataFormat    = CODEC_I2S_DATA_FORMAT_I2S;
+ *     CODEC_InitStruct.CODEC_I2SDataWidth     = CODEC_I2S_DATA_WIDTH_16BITS;
+ *     CODEC_Init(CODEC, &CODEC_InitStruct);
+ * }
+ * \endcode
+ */
+void CODEC_StructInit(CODEC_InitTypeDef *CODEC_InitStruct);
+
+/**
+ * \brief   Initializes the CODEC EQ module according to the specified
+ *          parameters in the CODEC_EQInitStruct.
+ * \param[in] CODEC_EQx: CODEC EQ channel selected.
+ * \param[in] CODEC_EQInitStruct: Pointer to a CODEC_EQInitTypeDef structure that
+ *            contains the configuration information for the specified CODEC EQ channel.
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_codec_eq_init(void)
+ * {
+ *     CODEC_EQInitTypeDef  CODEC_EQInitStruct;
+ *     CODEC_StructInit(&CODEC_EQInitStruct);
+ *     CODEC_EQInitStruct. CODEC_EQChCmd    = EQ_Ch_Cmd_ENABLE;
+ *     CODEC_EQInitStruct.CODEC_EQCoefH0    = 0xFF;
+ *     CODEC_EQInitStruct.CODEC_EQCoefB1    = 0xFF;
+ *     CODEC_EQInitStruct.CODEC_EQCoefB2    = 0xFF;
+ *     CODEC_EQInitStruct.CODEC_EQCoefA1    = 0xFF;
+ *     CODEC_EQInitStruct.CODEC_EQCoefA2    = 0xFF;
+ *     CODEC_EQInit(CODEC_EQ1, CODEC_EQInitStruct);
+ * }
+ * \endcode
+ */
+void CODEC_EQInit(CODEC_EQTypeDef *CODEC_EQx, CODEC_EQInitTypeDef *CODEC_EQInitStruct);
+
+/**
+ * \brief  Fills each CODEC_EQInitStruct member with its default value.
+ * \param[in] CODEC_EQInitStruct: Pointer to a CODEC_EQInitTypeDef structure which will be initialized.
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_codec_eq_init(void)
+ * {
+ *     CODEC_EQInitTypeDef  CODEC_EQInitStruct;
+ *     CODEC_StructInit(&CODEC_EQInitStruct);
+ *     CODEC_EQInitStruct. CODEC_EQChCmd    = EQ_Ch_Cmd_ENABLE;
+ *     CODEC_EQInitStruct.CODEC_EQCoefH0    = 0xFF;
+ *     CODEC_EQInitStruct.CODEC_EQCoefB1    = 0xFF;
+ *     CODEC_EQInitStruct.CODEC_EQCoefB2    = 0xFF;
+ *     CODEC_EQInitStruct.CODEC_EQCoefA1    = 0xFF;
+ *     CODEC_EQInitStruct.CODEC_EQCoefA2    = 0xFF;
+ *     CODEC_EQInit(CODEC_EQ1, CODEC_EQInitStruct);
+ * }
+ * \endcode
+ */
+void CODEC_EQStructInit(CODEC_EQInitTypeDef *CODEC_EQInitStruct);
+
+/**
+ * \brief  Reset CODEC.
+ * \param[in] CODECx: CODEC peripheral selected.
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void codec_demo(void)
+ * {
+ *     CODEC_Reset(CODEC);
+ * }
+ * \endcode
+ */
+void CODEC_Reset(CODEC_TypeDef *CODECx);
+
+/**
+ * \brief   Config MIC BIAS Vref voltage.
+ * \param[in] CODECx: CODEC peripheral selected.
+ * \param[in] data: New value of MIC BIAS.
+ *   This parameter can be one of the following values:
+ *     \arg MICBIAS_VOLTAGE_1_507: Vref voltage is 1.507V.
+ *     \arg MICBIAS_VOLTAGE_1_62:  Vref voltage is 1.62V.
+ *     \arg MICBIAS_VOLTAGE_1_705: Vref voltage is 1.705V.
+ *     \arg MICBIAS_VOLTAGE_1_8: Vref voltage is 1.8V.
+ *     \arg MICBIAS_VOLTAGE_1_906: Vref voltage is 1.906V.
+ *     \arg MICBIAS_VOLTAGE_2_025:  Vref voltage is 2.025V.
+ *     \arg MICBIAS_VOLTAGE_2_16: Vref voltage is 2.16V.
+ *     \arg MICBIAS_VOLTAGE_2_314: Vref voltage is 2.314V.
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void codec_demo(void)
+ * {
+ *     CODEC_SetMICBIAS(CODEC, MICBIAS_VOLTAGE_1_507);
+ * }
+ * \endcode
+ */
+void CODEC_SetMicBias(CODEC_TypeDef *CODECx, uint16_t Data);
+
+/**
+ * \brief  Enable or disable mic_bias output.
+ * \param[in] CODECx: CODEC peripheral selected.
+ * \param[in] NewState: New state of MICBIAS.
+ *      This parameter can be: ENABLE or DISABLE.
+ * \return none.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void codec_demo(void)
+ * {
+ *     CODEC_MICBIASCmd(CODEC, ENABLE);
+ * }
+ * \endcode
+ */
+void CODEC_MicBiasCmd(CODEC_TypeDef *CODECx, FunctionalState NewState);
+
+/**
+  * \brief  Enable or disable the specified CODEC interrupts.
+  * \param[in]  CODEC: selected CODEC peripheral.
+  * \param[in]  CODEC_INT: specifies the CODEC interrupts sources to be enable or disable.
+  *         This parameter can be the following values:
+  *         \arg CODEC_INT_POF_READY: CODEC power off ready interrupt.
+  *         \arg CODEC_INT_PON_READY: CODEC power on ready interrupt.
+  * \param[in]  NewState: new state of the specified CODEC interrupts.
+  *   This parameter can be: ENABLE or DISABLE.
+  * \return None
+  */
+void CODEC_INTConfig(CODEC_TypeDef *CODECx, uint32_t CODEC_INT, FunctionalState NewState);
+
+/**
+  * \brief  Mask the specified CODEC interrupt
+  * \param[in]  CODEC: selected CODEC peripheral.
+  * \param[in]  CODEC_INT: specifies the CODEC interrupts sources to be enable or disable.
+  *         This parameter can be the following values:
+  *         \arg CODEC_INT_POF_READY: CODEC power off ready interrupt.
+  *         \arg CODEC_INT_PON_READY: CODEC power on ready interrupt.
+  * \param[in]  NewState: new state of the specified CODEC interrupts.
+  *   This parameter can be: ENABLE or DISABLE.
+  * \return None
+  */
+void CODEC_MaskINTConfig(CODEC_TypeDef *CODECx, uint32_t CODEC_INT, FunctionalState NewState);
+
+/**
+  * \brief  Get the specified CODEC flag status.
+  * \param[in]  CODEC: selected CODEC peripheral.
+  * \param[in]  CODEC_INT: the specified CODEC interrupt.
+  *         This parameter can be one of the following values:
+  *         \arg CODEC_INT_POF_READY: CODEC power off ready interrupt.
+  *         \arg CODEC_INT_PON_READY: CODEC power on ready interrupt.
+  * \return[in] The new state of FLAG (SET or RESET).
+  */
+ITStatus CODEC_GetINTStatus(CODEC_TypeDef *CODECx, uint32_t CODEC_INT);
+
+/**
+  * \brief  Clears the CODEC interrupt pending bits.
+  * \param[in]  CODEC: selected CODEC peripheral.
+  * \param[in]  CODEC_CLEAR_INT: specifies the interrupt pending bit to clear.
+  *         This parameter can be any combination of the following values:
+  *         This parameter can be the following values:
+  *         \arg CODEC_INT_POF_READY: CODEC power off ready interrupt.
+  *         \arg CODEC_INT_PON_READY: CODEC power on ready interrupt.
+  * \return None
+  */
+void CODEC_ClearINTPendingBit(CODEC_TypeDef *CODECx, uint32_t CODEC_CLEAR_INT);
+
+/** End of CODEC_Exported_Functions
+  * \}
+  */
+
+/** End of CODEC
+  * \}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RTL_CODEC_H */
diff --git a/bee/drivers/codec/src/device/rtl87x2j/rtl_codec_def.h b/bee/drivers/codec/src/device/rtl87x2j/rtl_codec_def.h
new file mode 100644
index 00000000..2d38254c
--- /dev/null
+++ b/bee/drivers/codec/src/device/rtl87x2j/rtl_codec_def.h
@@ -0,0 +1,533 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef RTL_CODEC_DEF_H
+#define RTL_CODEC_DEF_H
+
+#include "utils/rtl_utils.h"
+#include "address_map.h"
+#include "aon_reg.h"
+
+#ifdef  __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/*============================================================================*
+ *                          CODEC Defines
+ *============================================================================*/
+/** \defgroup CODEC         CODEC
+  * \brief
+  * \{
+  */
+
+/** \defgroup CODEC_Exported_Constants I2S Exported Constants
+  * \brief
+  * \{
+  */
+
+/**
+ * \defgroup CODEC_Defines I2S Defines
+ * \{
+ * \ingroup  CODEC_Exported_Constants
+ */
+#define CODEC_SUPPORT_INT                (1)
+/** End of CODEC_Defines
+  * \}
+  */
+
+/** End of CODEC_Exported_Constants
+  * \}
+  */
+
+/** End of CODEC
+  * \}
+  */
+
+/*============================================================================*
+ *                         CODEC Registers Memory Map
+ *============================================================================*/
+typedef struct                  /*!< CODEC_ANA Structure */
+{
+    __IO uint32_t REG0X_CODEC_ANA;              /*!< 0x00 */
+    __IO uint32_t REG2X_CODEC_ANA;              /*!< 0x04 */
+    __IO uint32_t REG4X_CODEC_ANA;              /*!< 0x08 */
+    __IO uint32_t REG6X_CODEC_ANA;              /*!< 0x0C */
+    __IO uint32_t REG8X_CODEC_ANA;              /*!< 0x10 */
+    __IO uint32_t RESERVED_0;                   /*!< 0x14 */
+    __IO uint32_t RESERVED_1;                   /*!< 0x18 */
+    __IO uint32_t RESERVED_2;                   /*!< 0x1C */
+    __IO uint32_t AUDIO_PON_POF;                /*!< 0x20 */
+    __IO uint32_t AUDIO_INT_CONTROL;            /*!< 0x24 */
+} CODEC_ANA_TypeDef;
+
+typedef struct                  /*!< CODEC Structure */
+{
+    __IO uint32_t AUDIO_CONTROL_1;              /*!< 0x100 */
+    __IO uint32_t AUDIO_ANA_CONTROL_1;          /*!< 0x104 */
+    __IO uint32_t AUDIO_CLOCK_CONTROL_1;        /*!< 0x108 */
+    __IO uint32_t AUDIO_CLOCK_CONTROL_2;        /*!< 0x10C */
+    __IO uint32_t AUDIO_CLOCK_CONTROL_3;        /*!< 0x110 */
+    __IO uint32_t RESERVED_0;                   /*!< 0x114 */
+    __IO uint32_t RESERVED_1;                   /*!< 0x118 */
+    __IO uint32_t I2S_0_CONTROL_0;              /*!< 0x11C */
+    __IO uint32_t ADC_0_CONTROL_0;              /*!< 0x120 */
+    __IO uint32_t ADC_0_CONTROL_1;              /*!< 0x124 */
+} CODEC_TypeDef;
+
+
+typedef struct
+{
+    __IO uint32_t EQ_H0;                 /*!< 0x40 */
+    __IO uint32_t EQ_B1;                 /*!< 0x44 */
+    __IO uint32_t EQ_B2;                 /*!< 0x48 */
+    __IO uint32_t EQ_A1;                 /*!< 0x4C */
+    __IO uint32_t EQ_A2;                 /*!< 0x50 */
+} CODEC_EQTypeDef;
+
+/*============================================================================*
+ *                          CODEC Declaration
+ *============================================================================*/
+#define CODEC       ((CODEC_TypeDef     *)(SPI_CODEC_BASE +0x100) )
+#define CODEC_ANA   ((CODEC_ANA_TypeDef *)(SPI_CODEC_BASE ))
+
+/*============================================================================*
+ *                          CODEC Private Types
+ *============================================================================*/
+
+#define CODEC_ADC_CH0_CR_REG_BASE        0x40026200UL
+#define CODEC_ADC_CH0_EQ0_REG_BASE       0x40026204UL
+#define CODEC_ADC_CH0_EQ1_REG_BASE       0x40026218UL
+#define CODEC_ADC_CH0_EQ2_REG_BASE       0x4002622CUL
+#define CODEC_ADC_CH0_EQ3_REG_BASE       0x40026240UL
+#define CODEC_ADC_CH0_EQ4_REG_BASE       0x40026254UL
+
+
+#define CODEC_ADC_CH0_CR                 (*((volatile uint32_t *)CODEC_ADC_CH0_CR_REG_BASE))
+#define CODEC_ADC_CH0_EQ0                ((CODEC_EQTypeDef*) CODEC_ADC_CH0_EQ0_REG_BASE)
+#define CODEC_ADC_CH0_EQ1                ((CODEC_EQTypeDef*) CODEC_ADC_CH0_EQ1_REG_BASE)
+#define CODEC_ADC_CH0_EQ2                ((CODEC_EQTypeDef*) CODEC_ADC_CH0_EQ2_REG_BASE)
+#define CODEC_ADC_CH0_EQ3                ((CODEC_EQTypeDef*) CODEC_ADC_CH0_EQ3_REG_BASE)
+#define CODEC_ADC_CH0_EQ4                ((CODEC_EQTypeDef*) CODEC_ADC_CH0_EQ4_REG_BASE)
+
+
+/*============================================================================*
+ *                          CODEC Registers and Field Descriptions
+ *============================================================================*/
+/* 0x00
+   0       R/W    dtsdm_pow               1'b0
+   1       R/W    dtsdm_ckxen             1'b1
+   7:2     R/W    codec_dummy_vcore       6'h0
+   31:8    R      reserved8               24'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t dtsdm_pow: 1;
+        uint32_t dtsdm_ckxen: 1;
+        uint32_t codec_dummy_vcore: 6;
+        const uint32_t reserved_0: 24;
+    } b;
+} REG0X_CODEC_ANA_TypeDef;
+
+
+/* 0x04
+   0       R/W    micbst_pow              1'b0
+   1       R      reserved1               1'b0
+   2       R/W    micbst_endf             1'b1
+   3       R      reserved3               1'b0
+   4       R/W    micbst_mute             1'b1
+   7:5     R      reserved5               3'h0
+   10:8    R/W    micbst_gsel             3'b000
+   31:11   R      reserved11              21'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t micbst_pow: 1;
+        const uint32_t reserved_3: 1;
+        uint32_t micbst_endf: 1;
+        const uint32_t reserved_2: 1;
+        uint32_t micbst_mute: 1;
+        const uint32_t reserved_1: 3;
+        uint32_t micbst_gsel: 3;
+        const uint32_t reserved_0: 21;
+    } b;
+} REG2X_CODEC_ANA_TypeDef;
+
+
+/* 0x08
+   0       R/W    micbias_pow             1'b0
+   1       R/W    micbias_enchx           1'b1
+   2       R/W    micbias_extcap          1'b1
+   4:3     R      reserved3               2'h0
+   7:5     R/W    micbias_vset            3'b011
+   9:8     R/W    micbias_count           2'b01
+   11:10   R      reserved10              2'h0
+   13:12   R/W    micbias_ocsel           2'b01
+   14      R/W    micbias_powshdt         1'b0
+   15      R/W    micbias_ilimit          1'b0
+   31:16   R      reserved16              16'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t micbias_pow: 1;
+        uint32_t micbias_enchx: 1;
+        uint32_t micbias_extcap: 1;
+        const uint32_t reserved_2: 2;
+        uint32_t micbias_vset: 3;
+        uint32_t micbias_count: 2;
+        const uint32_t reserved_1: 2;
+        uint32_t micbias_ocsel: 2;
+        uint32_t micbias_powshdt: 1;
+        uint32_t micbias_ilimit: 1;
+        const uint32_t reserved_0: 16;
+    } b;
+} REG4X_CODEC_ANA_TypeDef;
+
+
+/* 0x0C
+   1:0     R/W    isel_micbst             2'b11
+   3:2     R/W    isel_dtsdm              2'b11
+   7:4     R      reserved4               4'h0
+   9:8     R/W    isel_micbias            2'b11
+   31:10   R      reserved10              22'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t isel_micbst: 2;
+        uint32_t isel_dtsdm: 2;
+        const uint32_t reserved_1: 4;
+        uint32_t isel_micbias: 2;
+        const uint32_t reserved_0: 22;
+    } b;
+} REG6X_CODEC_ANA_TypeDef;
+
+
+/* 0x10
+   0       R/W    mbias_pow               1'b0
+   1       R/W    ldo318_aud_pow          1'b0
+   2       R/W    ldo318_aud_ilimit       1'b0
+   7:3     R/W    ldo318_aud_tune         5'b01111
+   9:8     R/W    ldo318_aud_bw_sel       2'b11
+   11:10   R/W    codec_dummy_ldo         2'b00
+   12      R/W    vref_bypass             1'b0
+   13      R/W    vref_extcap_en          1'b0
+   15:14   R/W    vref_sel                2'b10
+   31:16   R      reserved16              16'b0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t mbias_pow: 1;
+        uint32_t ldo318_aud_pow: 1;
+        uint32_t ldo318_aud_ilimit: 1;
+        uint32_t ldo318_aud_tune: 5;
+        uint32_t ldo318_aud_bw_sel: 2;
+        uint32_t codec_dummy_ldo: 2;
+        uint32_t vref_bypass: 1;
+        uint32_t vref_extcap_en: 1;
+        uint32_t vref_sel: 2;
+        const uint32_t reserved_0: 16;
+    } b;
+} REG8X_CODEC_ANA_TypeDef;
+
+
+
+
+/* 0x20
+   0       R/W    audio_pon_en            1'b0
+   1       R/W    audio_pof_en            1'b0
+   3:2     R      reserved2               2'h0
+   6:4     R/W    pon_st1_delay_sel       3'h1
+   7       R      reserved7               1'h0
+   10:8    R/W    pon_st2_delay_sel       3'h1
+   11      R      reserved7               1'h0
+   14:12   R/W    pon_st3_delay_sel       3'h1
+   15      R      reserved7               1'h0
+   18:16   R/W    pon_st4_delay_sel       3'h0
+   19      R      reserved7               1'h0
+   22:20   R/W    pon_st5_delay_sel       3'h1
+   23      R      reserved7               1'h0
+   26:24   R/W    pof_st1_delay_sel       3'h1
+   27      R      reserved7               1'h0
+   30:28   R/W    pof_st2_delay_sel       3'h1
+   31      R      reserved7               1'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t audio_pon_en: 1;
+        uint32_t audio_pof_en: 1;
+        const uint32_t reserved_7: 2;
+        uint32_t pon_st1_delay_sel: 3;
+        const uint32_t reserved_6: 1;
+        uint32_t pon_st2_delay_sel: 3;
+        const uint32_t reserved_5: 1;
+        uint32_t pon_st3_delay_sel: 3;
+        const uint32_t reserved_4: 1;
+        uint32_t pon_st4_delay_sel: 3;
+        const uint32_t reserved_3: 1;
+        uint32_t pon_st5_delay_sel: 3;
+        const uint32_t reserved_2: 1;
+        uint32_t pof_st1_delay_sel: 3;
+        const uint32_t reserved_1: 1;
+        uint32_t pof_st2_delay_sel: 3;
+        const uint32_t reserved_0: 1;
+    } b;
+} AUDIO_PON_POF_TypeDef;
+
+/* 0x24
+   0       R/W    audio_pon_ready_int            1'b0
+   1       R/W    audio_pof_ready_int            1'b0
+   7:2     R      reserved2                      6'h0
+   8       R/W    audio_pon_ready_int_en         1'h1
+   9       R/W    audio_pof_ready_int_en         1'h1
+   15:10   R      reserved10                     6'h0
+   16      R/W    audio_pon_ready_int_mask       1'h0
+   17      R/W    audio_pof_ready_int_mask       1'h0
+   31:18   R/W    reserved18                     14'h0
+
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t audio_pon_ready_int: 1;
+        uint32_t audio_pof_ready_int: 1;
+        const uint32_t reserved_2: 6;
+        uint32_t audio_pon_ready_int_en: 1;
+        uint32_t audio_pof_ready_int_en: 1;
+        const uint32_t reserved_10: 6;
+        uint32_t audio_pon_ready_int_mask: 1;
+        uint32_t audio_pof_ready_int_mask: 1;
+        const uint32_t reserved_18: 14;
+    } b;
+} AUDIO_INT_CONTROL_TypeDef;
+
+
+/* 0x100
+   0       R/W    audio_ip_en             1'h0
+   2:1     R/W    audio_control_dummy1    2'h0
+   7:3     R/W    audio_dbg_sel           5'h0
+   31:8    R      reserved8               24'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t audio_ip_en: 1;
+        uint32_t audio_control_dummy1: 2;
+        uint32_t audio_dbg_sel: 5;
+        const uint32_t reserved_0: 24;
+    } b;
+} AUDIO_CONTROL_1_TypeDef;
+
+
+/* 0x104
+   2:0     R/W    audio_ana_dummy1        3'h0
+   3       R/W    ckx_micbias_en          1'h0
+   31:4    R      reserved4               28'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t audio_ana_dummy1: 3;
+        uint32_t ckx_micbias_en: 1;
+        const uint32_t reserved_0: 28;
+    } b;
+} AUDIO_ANA_CONTROL_1_TypeDef;
+
+
+/* 0x108
+   5:0     R      reserved0               6'h0
+   6       R/W    ad_0_en                 1'h0
+   9:7     R      reserved7               3'h0
+   10      R/W    ad_fifo_en              1'h0
+   11      R/W    ad_ana_clk_en           1'h0
+   12      R/W    ad_ana_0_en             1'h0
+   31:13   R/W    reserved13              19'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t reserved_2: 6;
+        uint32_t ad_0_en: 1;
+        const uint32_t reserved_1: 3;
+        uint32_t ad_fifo_en: 1;
+        uint32_t ad_ana_clk_en: 1;
+        uint32_t ad_ana_0_en: 1;
+        uint32_t reserved_0: 19;
+    } b;
+} AUDIO_CLOCK_CONTROL_1_TypeDef;
+
+
+/* 0x10C
+   2:0     R/W    dmic1_clk_sel           3'h1
+   3       R/W    dmic1_clk_en            1'h0
+   4       R/W    dmic1_src_clk_sel       1'h0
+   31:5    R      reserved5               27'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t dmic1_clk_sel: 3;
+        uint32_t dmic1_clk_en: 1;
+        uint32_t dmic1_src_clk_sel: 1;
+        const uint32_t reserved_0: 27;
+    } b;
+} AUDIO_CLOCK_CONTROL_2_TypeDef;
+
+
+/* 0x110
+   3:0     R/W    sample_rate_0           4'h5
+   6:4     R      reserved4               3'h0
+   8:7     R/W    ana_clk_rate_sel        2'h2
+   9       R/W    ad_ana_clk_sel          1'h0
+   10      R/W    adc_latch_phase         1'h0
+   11      R      reserved11              1'h0
+   13:12   R/W    ad_lpf_clk_rate_sel     2'h0
+   31:14   R      reserved14              18'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t sample_rate_0: 4;
+        const uint32_t reserved_2: 3;
+        uint32_t ana_clk_rate_sel: 2;
+        uint32_t ad_ana_clk_sel: 1;
+        uint32_t adc_latch_phase: 1;
+        const uint32_t reserved_1: 1;
+        uint32_t ad_lpf_clk_rate_sel: 2;
+        const uint32_t reserved_0: 18;
+    } b;
+} AUDIO_CLOCK_CONTROL_3_TypeDef;
+
+
+
+/* 0x11C
+   0       R/W    i2s_0_rst_n_reg         1'h0
+   1       R/W    i2s_0_inv_sclk          1'h0
+   2       R/W    i2s_0_self_lpbk_en      1'h0
+   7:3     R      reserved3               5'h0
+   9:8     R      reserved8               2'h0
+   11:10   R/W    i2s_0_data_format_sel_rx2'h0
+   13:12   R      reserved12              2'h0
+   15:14   R/W    i2s_0_data_len_sel_rx   2'h0
+   17:16   R      reserved17              2'h0
+   19:18   R/W    i2s_0_data_ch_sel_rx    2'h0
+   31:20   R      reserved20              12'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t i2s_0_rst_n_reg: 1;
+        uint32_t i2s_0_inv_sclk: 1;
+        uint32_t i2s_0_self_lpbk_en: 1;
+        const uint32_t reserved_4: 5;
+        const uint32_t reserved_3: 2;
+        uint32_t i2s_0_data_format_sel_rx: 2;
+        const uint32_t reserved_2: 2;
+        uint32_t i2s_0_data_len_sel_rx: 2;
+        const uint32_t reserved_1: 2;
+        uint32_t i2s_0_data_ch_sel_rx: 2;
+        const uint32_t reserved_0: 12;
+    } b;
+} I2S_0_CONTROL_0_TypeDef;
+
+
+/* 0x120
+   1:0     R/W    adc_0_dmic_src_sel      2'h0
+   3:2     R/W    adc_0_control_dummy     2'h0
+   4       R/W    adc_0_ad_lpf2nd_en      1'h1
+   5       R/W    adc_0_ad_lpf1st_en      1'h1
+   7:6     R/W    adc_0_ad_lpf1st_fc_sel  2'h0
+   9:8     R/W    adc_0_ad_zdet_func      2'h2
+   11:10   R/W    adc_0_ad_zdet_tout      2'h1
+   12      R/W    adc_0_ad_mute           1'h0
+   14:13   R/W    adc_0_boost_gain        2'h0
+   15      R/W    adc_0_admic_sel         1'h1
+   16      R/W    adc_0_dchpf_en          1'h0
+   19:17   R/W    adc_0_dchpf_fc_sel      3'h2
+   29:20   R      reserved20              10'h0
+   31:30   R/W    adc_0_ad_lpf2nd_fc_sel  2'h1
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t adc_0_dmic_src_sel: 2;
+        uint32_t adc_0_control_dummy: 2;
+        uint32_t adc_0_ad_lpf2nd_en: 1;
+        uint32_t adc_0_ad_lpf1st_en: 1;
+        uint32_t adc_0_ad_lpf1st_fc_sel: 2;
+        uint32_t adc_0_ad_zdet_func: 2;
+        uint32_t adc_0_ad_zdet_tout: 2;
+        uint32_t adc_0_ad_mute: 1;
+        uint32_t adc_0_boost_gain: 2;
+        uint32_t adc_0_admic_sel: 1;
+        uint32_t adc_0_dchpf_en: 1;
+        uint32_t adc_0_dchpf_fc_sel: 3;
+        const uint32_t reserved_0: 10;
+        uint32_t adc_0_ad_lpf2nd_fc_sel: 2;
+    } b;
+} ADC_0_CONTROL_0_TypeDef;
+
+
+/* 0x124
+   6:0     R/W    adc_0_ad_gain           7'h2f
+   16:7    R      reserved7               10'h0
+   17      R/W    adc_0_depop_en          1'h1
+   19:18   R/W    adc_0_depop_time_sel    2'h0
+   31:20   R      reserved                12'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t adc_0_ad_gain: 7;
+        const uint32_t reserved_1: 10;
+        uint32_t adc_0_depop_en: 1;
+        uint32_t adc_0_depop_time_sel: 2;
+        const uint32_t reserved_0: 12;
+    } b;
+} ADC_0_CONTROL_1_TypeDef;
+
+
+
+#ifdef  __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* RTL_CODEC_DEF_H */
+
diff --git a/bee/drivers/crypto/CMakeLists.txt b/bee/drivers/crypto/CMakeLists.txt
new file mode 100644
index 00000000..a6ec4b73
--- /dev/null
+++ b/bee/drivers/crypto/CMakeLists.txt
@@ -0,0 +1,5 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_include_directories_ifdef(CONFIG_SOC_SERIES_RTL87X2G inc/rtl87x2g)
+zephyr_include_directories_ifdef(CONFIG_SOC_SERIES_RTL8752H inc/rtl8752h)
diff --git a/bee/drivers/crypto/inc/rtl8752h/aes.h b/bee/drivers/crypto/inc/rtl8752h/aes.h
new file mode 100644
index 00000000..74f8f8b7
--- /dev/null
+++ b/bee/drivers/crypto/inc/rtl8752h/aes.h
@@ -0,0 +1,552 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef MBEDTLS_AES_H
+#define MBEDTLS_AES_H
+#include "mbedtls/private_access.h"
+
+#include "mbedtls/build_info.h"
+
+#include <stddef.h>
+#include <stdint.h>
+
+/* padlock.c and aesni.c rely on these values! */
+#define MBEDTLS_AES_ENCRYPT     1 /**< AES encryption. */
+#define MBEDTLS_AES_DECRYPT     0 /**< AES decryption. */
+
+/* Error codes in range 0x0020-0x0022 */
+#define MBEDTLS_ERR_AES_INVALID_KEY_LENGTH                -0x0020  /**< Invalid key length. */
+#define MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH              -0x0022  /**< Invalid data input length. */
+
+/* Error codes in range 0x0021-0x0025 */
+#define MBEDTLS_ERR_AES_BAD_INPUT_DATA                    -0x0021  /**< Invalid input data. */
+
+#if ( defined(__ARMCC_VERSION) || defined(_MSC_VER) ) && \
+    !defined(inline) && !defined(__cplusplus)
+#define inline __inline
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if !defined(MBEDTLS_AES_ALT)
+// Regular implementation
+//
+
+/**
+ * \brief The AES context-type definition.
+ */
+typedef struct mbedtls_aes_context
+{
+    int MBEDTLS_PRIVATE(nr);                     /*!< The number of rounds. */
+    uint32_t *MBEDTLS_PRIVATE(rk);               /*!< AES round keys. */
+    uint32_t MBEDTLS_PRIVATE(buf)[68];           /*!< Unaligned data buffer. This buffer can
+                                     hold 32 extra Bytes, which can be used for
+                                     one of the following purposes:
+                                     <ul><li>Alignment if VIA padlock is
+                                             used.</li>
+                                     <li>Simplifying key expansion in the 256-bit
+                                         case by generating an extra round key.
+                                         </li></ul> */
+}
+mbedtls_aes_context;
+
+#if defined(MBEDTLS_CIPHER_MODE_XTS)
+/**
+ * \brief The AES XTS context-type definition.
+ */
+typedef struct mbedtls_aes_xts_context
+{
+    mbedtls_aes_context MBEDTLS_PRIVATE(crypt); /*!< The AES context to use for AES block
+                                        encryption or decryption. */
+    mbedtls_aes_context MBEDTLS_PRIVATE(tweak); /*!< The AES context used for tweak
+                                        computation. */
+} mbedtls_aes_xts_context;
+#endif /* MBEDTLS_CIPHER_MODE_XTS */
+
+#else  /* MBEDTLS_AES_ALT */
+#include "aes_alt.h"
+#endif /* MBEDTLS_AES_ALT */
+
+/**
+ * \brief          This function initializes the specified AES context.
+ *
+ *                 It must be the first API called before using
+ *                 the context.
+ *
+ * \param ctx      The AES context to initialize. This must not be \c NULL.
+ */
+void mbedtls_aes_init(mbedtls_aes_context *ctx);
+
+/**
+ * \brief          This function releases and clears the specified AES context.
+ *
+ * \param ctx      The AES context to clear.
+ *                 If this is \c NULL, this function does nothing.
+ *                 Otherwise, the context must have been at least initialized.
+ */
+void mbedtls_aes_free(mbedtls_aes_context *ctx);
+
+#if defined(MBEDTLS_CIPHER_MODE_XTS)
+/**
+ * \brief          This function initializes the specified AES XTS context.
+ *
+ *                 It must be the first API called before using
+ *                 the context.
+ *
+ * \param ctx      The AES XTS context to initialize. This must not be \c NULL.
+ */
+void mbedtls_aes_xts_init(mbedtls_aes_xts_context *ctx);
+
+/**
+ * \brief          This function releases and clears the specified AES XTS context.
+ *
+ * \param ctx      The AES XTS context to clear.
+ *                 If this is \c NULL, this function does nothing.
+ *                 Otherwise, the context must have been at least initialized.
+ */
+void mbedtls_aes_xts_free(mbedtls_aes_xts_context *ctx);
+#endif /* MBEDTLS_CIPHER_MODE_XTS */
+
+/**
+ * \brief          This function sets the encryption key.
+ *
+ * \param ctx      The AES context to which the key should be bound.
+ *                 It must be initialized.
+ * \param key      The encryption key.
+ *                 This must be a readable buffer of size \p keybits bits.
+ * \param keybits  The size of data passed in bits. Valid options are:
+ *                 <ul><li>128 bits</li>
+ *                 <li>192 bits</li>
+ *                 <li>256 bits</li></ul>
+ *
+ * \return         \c 0 on success.
+ * \return         #MBEDTLS_ERR_AES_INVALID_KEY_LENGTH on failure.
+ */
+int mbedtls_aes_setkey_enc(mbedtls_aes_context *ctx, const unsigned char *key,
+                           unsigned int keybits);
+
+/**
+ * \brief          This function sets the decryption key.
+ *
+ * \param ctx      The AES context to which the key should be bound.
+ *                 It must be initialized.
+ * \param key      The decryption key.
+ *                 This must be a readable buffer of size \p keybits bits.
+ * \param keybits  The size of data passed. Valid options are:
+ *                 <ul><li>128 bits</li>
+ *                 <li>192 bits</li>
+ *                 <li>256 bits</li></ul>
+ *
+ * \return         \c 0 on success.
+ * \return         #MBEDTLS_ERR_AES_INVALID_KEY_LENGTH on failure.
+ */
+int mbedtls_aes_setkey_dec(mbedtls_aes_context *ctx, const unsigned char *key,
+                           unsigned int keybits);
+
+#if defined(MBEDTLS_CIPHER_MODE_XTS)
+/**
+ * \brief          This function prepares an XTS context for encryption and
+ *                 sets the encryption key.
+ *
+ * \param ctx      The AES XTS context to which the key should be bound.
+ *                 It must be initialized.
+ * \param key      The encryption key. This is comprised of the XTS key1
+ *                 concatenated with the XTS key2.
+ *                 This must be a readable buffer of size \p keybits bits.
+ * \param keybits  The size of \p key passed in bits. Valid options are:
+ *                 <ul><li>256 bits (each of key1 and key2 is a 128-bit key)</li>
+ *                 <li>512 bits (each of key1 and key2 is a 256-bit key)</li></ul>
+ *
+ * \return         \c 0 on success.
+ * \return         #MBEDTLS_ERR_AES_INVALID_KEY_LENGTH on failure.
+ */
+int mbedtls_aes_xts_setkey_enc(mbedtls_aes_xts_context *ctx,
+                               const unsigned char *key,
+                               unsigned int keybits);
+
+/**
+ * \brief          This function prepares an XTS context for decryption and
+ *                 sets the decryption key.
+ *
+ * \param ctx      The AES XTS context to which the key should be bound.
+ *                 It must be initialized.
+ * \param key      The decryption key. This is comprised of the XTS key1
+ *                 concatenated with the XTS key2.
+ *                 This must be a readable buffer of size \p keybits bits.
+ * \param keybits  The size of \p key passed in bits. Valid options are:
+ *                 <ul><li>256 bits (each of key1 and key2 is a 128-bit key)</li>
+ *                 <li>512 bits (each of key1 and key2 is a 256-bit key)</li></ul>
+ *
+ * \return         \c 0 on success.
+ * \return         #MBEDTLS_ERR_AES_INVALID_KEY_LENGTH on failure.
+ */
+int mbedtls_aes_xts_setkey_dec(mbedtls_aes_xts_context *ctx,
+                               const unsigned char *key,
+                               unsigned int keybits);
+#endif /* MBEDTLS_CIPHER_MODE_XTS */
+
+/**
+ * \brief          This function performs an AES single-block encryption or
+ *                 decryption operation.
+ *
+ *                 It performs the operation defined in the \p mode parameter
+ *                 (encrypt or decrypt), on the input data buffer defined in
+ *                 the \p input parameter.
+ *
+ *                 mbedtls_aes_init(), and either mbedtls_aes_setkey_enc() or
+ *                 mbedtls_aes_setkey_dec() must be called before the first
+ *                 call to this API with the same context.
+ *
+ * \param ctx      The AES context to use for encryption or decryption.
+ *                 It must be initialized and bound to a key.
+ * \param mode     The AES operation: #MBEDTLS_AES_ENCRYPT or
+ *                 #MBEDTLS_AES_DECRYPT.
+ * \param input    The buffer holding the input data.
+ *                 It must be readable and at least \c 16 Bytes long.
+ * \param output   The buffer where the output data will be written.
+ *                 It must be writeable and at least \c 16 Bytes long.
+
+ * \return         \c 0 on success.
+ */
+int mbedtls_aes_crypt_ecb(mbedtls_aes_context *ctx,
+                          int mode,
+                          const unsigned char input[16],
+                          unsigned char output[16]);
+
+#if defined(MBEDTLS_CIPHER_MODE_CBC)
+/**
+ * \brief  This function performs an AES-CBC encryption or decryption operation
+ *         on full blocks.
+ *
+ *         It performs the operation defined in the \p mode
+ *         parameter (encrypt/decrypt), on the input data buffer defined in
+ *         the \p input parameter.
+ *
+ *         It can be called as many times as needed, until all the input
+ *         data is processed. mbedtls_aes_init(), and either
+ *         mbedtls_aes_setkey_enc() or mbedtls_aes_setkey_dec() must be called
+ *         before the first call to this API with the same context.
+ *
+ * \note   This function operates on full blocks, that is, the input size
+ *         must be a multiple of the AES block size of \c 16 Bytes.
+ *
+ * \note   Upon exit, the content of the IV is updated so that you can
+ *         call the same function again on the next
+ *         block(s) of data and get the same result as if it was
+ *         encrypted in one call. This allows a "streaming" usage.
+ *         If you need to retain the contents of the IV, you should
+ *         either save it manually or use the cipher module instead.
+ *
+ *
+ * \param ctx      The AES context to use for encryption or decryption.
+ *                 It must be initialized and bound to a key.
+ * \param mode     The AES operation: #MBEDTLS_AES_ENCRYPT or
+ *                 #MBEDTLS_AES_DECRYPT.
+ * \param length   The length of the input data in Bytes. This must be a
+ *                 multiple of the block size (\c 16 Bytes).
+ * \param iv       Initialization vector (updated after use).
+ *                 It must be a readable and writeable buffer of \c 16 Bytes.
+ * \param input    The buffer holding the input data.
+ *                 It must be readable and of size \p length Bytes.
+ * \param output   The buffer holding the output data.
+ *                 It must be writeable and of size \p length Bytes.
+ *
+ * \return         \c 0 on success.
+ * \return         #MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH
+ *                 on failure.
+ */
+int mbedtls_aes_crypt_cbc(mbedtls_aes_context *ctx,
+                          int mode,
+                          size_t length,
+                          unsigned char iv[16],
+                          const unsigned char *input,
+                          unsigned char *output);
+#endif /* MBEDTLS_CIPHER_MODE_CBC */
+
+#if defined(MBEDTLS_CIPHER_MODE_XTS)
+/**
+ * \brief      This function performs an AES-XTS encryption or decryption
+ *             operation for an entire XTS data unit.
+ *
+ *             AES-XTS encrypts or decrypts blocks based on their location as
+ *             defined by a data unit number. The data unit number must be
+ *             provided by \p data_unit.
+ *
+ *             NIST SP 800-38E limits the maximum size of a data unit to 2^20
+ *             AES blocks. If the data unit is larger than this, this function
+ *             returns #MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH.
+ *
+ * \param ctx          The AES XTS context to use for AES XTS operations.
+ *                     It must be initialized and bound to a key.
+ * \param mode         The AES operation: #MBEDTLS_AES_ENCRYPT or
+ *                     #MBEDTLS_AES_DECRYPT.
+ * \param length       The length of a data unit in Bytes. This can be any
+ *                     length between 16 bytes and 2^24 bytes inclusive
+ *                     (between 1 and 2^20 block cipher blocks).
+ * \param data_unit    The address of the data unit encoded as an array of 16
+ *                     bytes in little-endian format. For disk encryption, this
+ *                     is typically the index of the block device sector that
+ *                     contains the data.
+ * \param input        The buffer holding the input data (which is an entire
+ *                     data unit). This function reads \p length Bytes from \p
+ *                     input.
+ * \param output       The buffer holding the output data (which is an entire
+ *                     data unit). This function writes \p length Bytes to \p
+ *                     output.
+ *
+ * \return             \c 0 on success.
+ * \return             #MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH if \p length is
+ *                     smaller than an AES block in size (16 Bytes) or if \p
+ *                     length is larger than 2^20 blocks (16 MiB).
+ */
+int mbedtls_aes_crypt_xts(mbedtls_aes_xts_context *ctx,
+                          int mode,
+                          size_t length,
+                          const unsigned char data_unit[16],
+                          const unsigned char *input,
+                          unsigned char *output);
+#endif /* MBEDTLS_CIPHER_MODE_XTS */
+
+#if defined(MBEDTLS_CIPHER_MODE_CFB)
+/**
+ * \brief This function performs an AES-CFB128 encryption or decryption
+ *        operation.
+ *
+ *        It performs the operation defined in the \p mode
+ *        parameter (encrypt or decrypt), on the input data buffer
+ *        defined in the \p input parameter.
+ *
+ *        For CFB, you must set up the context with mbedtls_aes_setkey_enc(),
+ *        regardless of whether you are performing an encryption or decryption
+ *        operation, that is, regardless of the \p mode parameter. This is
+ *        because CFB mode uses the same key schedule for encryption and
+ *        decryption.
+ *
+ * \note  Upon exit, the content of the IV is updated so that you can
+ *        call the same function again on the next
+ *        block(s) of data and get the same result as if it was
+ *        encrypted in one call. This allows a "streaming" usage.
+ *        If you need to retain the contents of the
+ *        IV, you must either save it manually or use the cipher
+ *        module instead.
+ *
+ *
+ * \param ctx      The AES context to use for encryption or decryption.
+ *                 It must be initialized and bound to a key.
+ * \param mode     The AES operation: #MBEDTLS_AES_ENCRYPT or
+ *                 #MBEDTLS_AES_DECRYPT.
+ * \param length   The length of the input data in Bytes.
+ * \param iv_off   The offset in IV (updated after use).
+ *                 It must point to a valid \c size_t.
+ * \param iv       The initialization vector (updated after use).
+ *                 It must be a readable and writeable buffer of \c 16 Bytes.
+ * \param input    The buffer holding the input data.
+ *                 It must be readable and of size \p length Bytes.
+ * \param output   The buffer holding the output data.
+ *                 It must be writeable and of size \p length Bytes.
+ *
+ * \return         \c 0 on success.
+ */
+int mbedtls_aes_crypt_cfb128(mbedtls_aes_context *ctx,
+                             int mode,
+                             size_t length,
+                             size_t *iv_off,
+                             unsigned char iv[16],
+                             const unsigned char *input,
+                             unsigned char *output);
+
+/**
+ * \brief This function performs an AES-CFB8 encryption or decryption
+ *        operation.
+ *
+ *        It performs the operation defined in the \p mode
+ *        parameter (encrypt/decrypt), on the input data buffer defined
+ *        in the \p input parameter.
+ *
+ *        Due to the nature of CFB, you must use the same key schedule for
+ *        both encryption and decryption operations. Therefore, you must
+ *        use the context initialized with mbedtls_aes_setkey_enc() for
+ *        both #MBEDTLS_AES_ENCRYPT and #MBEDTLS_AES_DECRYPT.
+ *
+ * \note  Upon exit, the content of the IV is updated so that you can
+ *        call the same function again on the next
+ *        block(s) of data and get the same result as if it was
+ *        encrypted in one call. This allows a "streaming" usage.
+ *        If you need to retain the contents of the
+ *        IV, you should either save it manually or use the cipher
+ *        module instead.
+ *
+ *
+ * \param ctx      The AES context to use for encryption or decryption.
+ *                 It must be initialized and bound to a key.
+ * \param mode     The AES operation: #MBEDTLS_AES_ENCRYPT or
+ *                 #MBEDTLS_AES_DECRYPT
+ * \param length   The length of the input data.
+ * \param iv       The initialization vector (updated after use).
+ *                 It must be a readable and writeable buffer of \c 16 Bytes.
+ * \param input    The buffer holding the input data.
+ *                 It must be readable and of size \p length Bytes.
+ * \param output   The buffer holding the output data.
+ *                 It must be writeable and of size \p length Bytes.
+ *
+ * \return         \c 0 on success.
+ */
+int mbedtls_aes_crypt_cfb8(mbedtls_aes_context *ctx,
+                           int mode,
+                           size_t length,
+                           unsigned char iv[16],
+                           const unsigned char *input,
+                           unsigned char *output);
+#endif /*MBEDTLS_CIPHER_MODE_CFB */
+
+#if defined(MBEDTLS_CIPHER_MODE_OFB)
+/**
+ * \brief       This function performs an AES-OFB (Output Feedback Mode)
+ *              encryption or decryption operation.
+ *
+ *              For OFB, you must set up the context with
+ *              mbedtls_aes_setkey_enc(), regardless of whether you are
+ *              performing an encryption or decryption operation. This is
+ *              because OFB mode uses the same key schedule for encryption and
+ *              decryption.
+ *
+ *              The OFB operation is identical for encryption or decryption,
+ *              therefore no operation mode needs to be specified.
+ *
+ * \note        Upon exit, the content of iv, the Initialisation Vector, is
+ *              updated so that you can call the same function again on the next
+ *              block(s) of data and get the same result as if it was encrypted
+ *              in one call. This allows a "streaming" usage, by initialising
+ *              iv_off to 0 before the first call, and preserving its value
+ *              between calls.
+ *
+ *              For non-streaming use, the iv should be initialised on each call
+ *              to a unique value, and iv_off set to 0 on each call.
+ *
+ *              If you need to retain the contents of the initialisation vector,
+ *              you must either save it manually or use the cipher module
+ *              instead.
+ *
+ * \warning     For the OFB mode, the initialisation vector must be unique
+ *              every encryption operation. Reuse of an initialisation vector
+ *              will compromise security.
+ *
+ * \param ctx      The AES context to use for encryption or decryption.
+ *                 It must be initialized and bound to a key.
+ * \param length   The length of the input data.
+ * \param iv_off   The offset in IV (updated after use).
+ *                 It must point to a valid \c size_t.
+ * \param iv       The initialization vector (updated after use).
+ *                 It must be a readable and writeable buffer of \c 16 Bytes.
+ * \param input    The buffer holding the input data.
+ *                 It must be readable and of size \p length Bytes.
+ * \param output   The buffer holding the output data.
+ *                 It must be writeable and of size \p length Bytes.
+ *
+ * \return         \c 0 on success.
+ */
+int mbedtls_aes_crypt_ofb(mbedtls_aes_context *ctx,
+                          size_t length,
+                          size_t *iv_off,
+                          unsigned char iv[16],
+                          const unsigned char *input,
+                          unsigned char *output);
+
+#endif /* MBEDTLS_CIPHER_MODE_OFB */
+
+#if defined(MBEDTLS_CIPHER_MODE_CTR)
+/**
+ * \brief      This function performs an AES-CTR encryption or decryption
+ *             operation.
+ *
+ *             This function performs the operation defined in the \p mode
+ *             parameter (encrypt/decrypt), on the input data buffer
+ *             defined in the \p input parameter.
+ *
+ *             Due to the nature of CTR, you must use the same key schedule
+ *             for both encryption and decryption operations. Therefore, you
+ *             must use the context initialized with mbedtls_aes_setkey_enc()
+ *             for both #MBEDTLS_AES_ENCRYPT and #MBEDTLS_AES_DECRYPT.
+ *
+ * \warning    You must never reuse a nonce value with the same key. Doing so
+ *             would void the encryption for the two messages encrypted with
+ *             the same nonce and key.
+ *
+ *             There are two common strategies for managing nonces with CTR:
+ *
+ *             1. You can handle everything as a single message processed over
+ *             successive calls to this function. In that case, you want to
+ *             set \p nonce_counter and \p nc_off to 0 for the first call, and
+ *             then preserve the values of \p nonce_counter, \p nc_off and \p
+ *             stream_block across calls to this function as they will be
+ *             updated by this function.
+ *
+ *             With this strategy, you must not encrypt more than 2**128
+ *             blocks of data with the same key.
+ *
+ *             2. You can encrypt separate messages by dividing the \p
+ *             nonce_counter buffer in two areas: the first one used for a
+ *             per-message nonce, handled by yourself, and the second one
+ *             updated by this function internally.
+ *
+ *             For example, you might reserve the first 12 bytes for the
+ *             per-message nonce, and the last 4 bytes for internal use. In that
+ *             case, before calling this function on a new message you need to
+ *             set the first 12 bytes of \p nonce_counter to your chosen nonce
+ *             value, the last 4 to 0, and \p nc_off to 0 (which will cause \p
+ *             stream_block to be ignored). That way, you can encrypt at most
+ *             2**96 messages of up to 2**32 blocks each with the same key.
+ *
+ *             The per-message nonce (or information sufficient to reconstruct
+ *             it) needs to be communicated with the ciphertext and must be unique.
+ *             The recommended way to ensure uniqueness is to use a message
+ *             counter. An alternative is to generate random nonces, but this
+ *             limits the number of messages that can be securely encrypted:
+ *             for example, with 96-bit random nonces, you should not encrypt
+ *             more than 2**32 messages with the same key.
+ *
+ *             Note that for both stategies, sizes are measured in blocks and
+ *             that an AES block is 16 bytes.
+ *
+ * \warning    Upon return, \p stream_block contains sensitive data. Its
+ *             content must not be written to insecure storage and should be
+ *             securely discarded as soon as it's no longer needed.
+ *
+ * \param ctx              The AES context to use for encryption or decryption.
+ *                         It must be initialized and bound to a key.
+ * \param length           The length of the input data.
+ * \param nc_off           The offset in the current \p stream_block, for
+ *                         resuming within the current cipher stream. The
+ *                         offset pointer should be 0 at the start of a stream.
+ *                         It must point to a valid \c size_t.
+ * \param nonce_counter    The 128-bit nonce and counter.
+ *                         It must be a readable-writeable buffer of \c 16 Bytes.
+ * \param stream_block     The saved stream block for resuming. This is
+ *                         overwritten by the function.
+ *                         It must be a readable-writeable buffer of \c 16 Bytes.
+ * \param input            The buffer holding the input data.
+ *                         It must be readable and of size \p length Bytes.
+ * \param output           The buffer holding the output data.
+ *                         It must be writeable and of size \p length Bytes.
+ *
+ * \return                 \c 0 on success.
+ */
+int mbedtls_aes_crypt_ctr(mbedtls_aes_context *ctx,
+                          size_t length,
+                          size_t *nc_off,
+                          unsigned char nonce_counter[16],
+                          unsigned char stream_block[16],
+                          const unsigned char *input,
+                          unsigned char *output);
+#endif /* MBEDTLS_CIPHER_MODE_CTR */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* aes.h */
diff --git a/bee/drivers/crypto/inc/rtl8752h/aes_api.h b/bee/drivers/crypto/inc/rtl8752h/aes_api.h
new file mode 100644
index 00000000..a90884ba
--- /dev/null
+++ b/bee/drivers/crypto/inc/rtl8752h/aes_api.h
@@ -0,0 +1,155 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *               Define to prevent recursive inclusion
+ *============================================================================*/
+#ifndef _AES_API_H_
+#define _AES_API_H_
+
+/*============================================================================*
+ *                               Header Files
+*============================================================================*/
+#include <stdint.h>
+#include <stdbool.h>
+
+
+/** @defgroup AES_API AES
+  * @brief API sets for AES encryption implementation
+  * @{
+  */
+
+/*============================================================================*
+  *                                Functions
+  *============================================================================*/
+/** @defgroup AES_API_Exported_Functions AES Exported Functions
+    * @{
+    */
+
+/**
+    * @brief  128 bit AES ECB encryption on specified plaintext and keys
+    *
+    * @param[in] plaintext    specified plain text to be encrypted
+    * @param[in] key          keys to encrypt the plaintext
+    * @param[out] encrypted    output buffer to store encrypted data
+    *
+    * @return encryption results
+    * @retval true      successful
+    * @retval false     fail
+    *
+    * @note   least significant octet of encrypted data corresponds to encrypted[0]
+    */
+bool aes128_ecb_encrypt(uint8_t plaintext[16], const uint8_t key[16], uint8_t *encrypted);
+
+/**
+    * @brief  128 bit AES ECB decryption on specified encrypted data and keys
+    *
+    * @param[in] input    specified encrypted data to be decrypted
+    * @param[in] key          keys to decrypt the data
+    * @param[out] output    output buffer to store plain data
+    *
+    * @return decryption results
+    * @retval true      successful
+    * @retval false     fail
+    *
+    * @note   least significant octet of encrypted data corresponds to encrypted[0]
+*/
+bool aes128_ecb_decrypt(uint8_t *input, const uint8_t *key, uint8_t *output);
+
+/**
+    * @brief  128 bit AES ECB encryption on specified plaintext and keys
+    *
+    * @param[in]  plaintext    specified plain text to be encrypted
+    * @param[in]  key          keys to encrypt the plaintext
+    * @param[out]  encrypted    output buffer to store encrypted data
+    *
+    * @return encryption results
+    * @retval true      successful
+    * @retval false     fail
+    *
+    * @note   most significant octet of encrypted data corresponds to encrypted[0]
+    */
+bool aes128_ecb_encrypt_msb2lsb(uint8_t plaintext[16], const uint8_t key[16],
+                                uint8_t *encrypted);
+/**
+    * @brief  128 bit AES ECB decryption on specified encrypted data and keys
+    *
+    * @param[in]  input    specified encrypted data to be decrypted
+    * @param[in] key          keys to decrypt the data
+    * @param[out]  output    output buffer to store plain data
+    *
+    * @return decryption results
+    * @retval true      successful
+    * @retval false     fail
+    *
+    * @note   most significant octet of encrypted data corresponds to encrypted[0]
+*/
+bool aes128_ecb_decrypt_msb2lsb(uint8_t *input, const uint8_t *key, uint8_t *output);
+
+/**
+    * @brief  256 bit AES ECB encryption on specified plaintext and keys
+    *
+    * @param[in]  plaintext    specified plain text to be encrypted
+    * @param[in]  key          keys to encrypt the plaintext
+    * @param[out]  encrypted    output buffer to store encrypted data
+    *
+    * @return encryption results
+    * @retval true      successful
+    * @retval false     fail
+    *
+    * @note   least significant octet of encrypted data corresponds to encrypted[0]
+    */
+bool aes256_ecb_encrypt(uint8_t plaintext[16], const uint8_t key[32], uint8_t *encrypted);
+/**
+    * @brief  256 bit AES ECB decryption on specified encrypted data and keys
+    *
+    * @param[in]  input    specified encrypted data to be decrypted
+    * @param[in]  key          keys to decrypt the data
+    * @param[out]  output    output buffer to store plain data
+    *
+    * @return decryption results
+    * @retval true      successful
+    * @retval false     fail
+    *
+    * @note   least significant octet of encrypted data corresponds to encrypted[0]
+*/
+bool aes256_ecb_decrypt(uint8_t *input, const uint8_t *key, uint8_t *output);
+/**
+    * @brief  256 bit AES ECB encryption on specified plaintext and keys
+    *
+    * @param[in] plaintext    specified plain text to be encrypted
+    * @param[in]  key          keys to encrypt the plaintext
+    * @param[out]  encrypted    output buffer to store encrypted data
+    *
+    * @return encryption results
+    * @retval true      successful
+    * @retval false     fail
+    *
+    * @note   most significant octet of encrypted data corresponds to encrypted[0]
+    */
+bool aes256_ecb_encrypt_msb2lsb(uint8_t plaintext[16], const uint8_t key[32],
+                                uint8_t *encrypted);
+/**
+    * @brief  256 bit AES ECB decryption on specified encrypted data and keys
+    *
+    * @param[in]  input    specified encrypted data to be decrypted
+    * @param[in]  key          keys to decrypt the data
+    * @param[out]  output    output buffer to store plain data
+    *
+    * @return decryption results
+    * @retval true      successful
+    * @retval false     fail
+    *
+    * @note   most significant octet of encrypted data corresponds to encrypted[0]
+    */
+bool aes256_ecb_decrypt_msb2lsb(uint8_t *input, const uint8_t *key, uint8_t *output);
+
+/** @} */ /* End of group AES_API_Exported_Functions */
+
+/** @} */ /* End of group AES_API */
+
+
+#endif
diff --git a/bee/drivers/crypto/inc/rtl8752h/hw_aes.h b/bee/drivers/crypto/inc/rtl8752h/hw_aes.h
new file mode 100644
index 00000000..e11c25c8
--- /dev/null
+++ b/bee/drivers/crypto/inc/rtl8752h/hw_aes.h
@@ -0,0 +1,167 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *               Define to prevent recursive inclusion
+ *============================================================================*/
+#ifndef HW_AES_H
+#define HW_AES_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*============================================================================*
+ *                        Header Files
+ *============================================================================*/
+#include <stdint.h>
+#include <stdbool.h>
+
+/** @defgroup  HW_AES    Hardware AES
+    * @brief API sets for hardware AES engine
+    * @{
+    */
+
+
+/*============================================================================*
+  *                                   Types
+  *============================================================================*/
+/** @defgroup HW_AES_Exported_Types HW AES Exported Types
+  * @{
+  */
+
+/** @brief Encryption zone for image encryption feature. */
+typedef enum
+{
+    ZONE0,
+    ZONE1,
+    ZONE_NOT_USED
+} T_PROTECT_ZONE;
+
+/** @brief AES mode definition for HW AES. */
+typedef enum
+{
+    AES_MODE_NONE,
+    AES_MODE_CBC,
+    AES_MODE_ECB,
+    AES_MODE_CFB,
+    AES_MODE_OFB,
+    AES_MODE_CTR
+} T_HW_AES_MODE;
+
+/** End of HW_AES_Exported_Types
+  * @}
+  */
+
+/*============================================================================*
+  *                                Functions
+  *============================================================================*/
+/** @defgroup HW_AES_Exported_Functions HW AES Exported Functions
+    * @brief
+    * @{
+    */
+
+/**
+    * @brief  16 Bytes AES decryption on specified data
+    *
+    * @param[in]  input              specified encrypted data to be decrypted
+    * @param[out]  output            output buffer to store plain data
+    *
+    * @return decryption results
+    * @retval true      successful
+    * @retval false     fail
+    *
+    */
+extern bool hw_aes_decrypt_16byte(uint8_t *input, uint8_t *output);
+
+/**
+    * @brief  128 bit AES encryption via DMA on specified plain data and keys
+    *
+    * @param[in]  p_in              specified plain data to be encrypted
+    * @param[out]  p_out            output buffer to store encrypted data
+    * @param[in]  data_word_len     input buffer length
+    * @param[in]  key               key buffer
+    * @param[in]  iv                initialization vector for AES CBC mode
+    * @param[in]  mode              AES mode specified by @ref T_HW_AES_MODE
+    *
+    * @return encryption results
+    * @retval true      successful
+    * @retval false     fail
+    *
+    * @note   HWAES_DMA_RX_CH_NUM and HWAES_DMA_TX_CH_NUM DMA channels are occupied by this function
+    */
+bool hw_aes_encrypt128_use_dma(uint32_t *p_in, uint32_t *p_out, uint16_t data_word_len,
+                               uint32_t *key, uint32_t *iv, T_HW_AES_MODE mode);
+/**
+    * @brief  128 bit AES decryption via DMA on specified data and keys
+    * @param[in]  p_in              specified encrypted data to be decrypted
+    * @param[out]  p_out            output buffer to store plain data
+    * @param[in]  data_word_len     input buffer length
+    * @param[in]  key               key buffer
+    * @param[in]  iv                initialization vector for AES CBC mode
+    * @param[in]  mode              AES mode specified by @ref T_HW_AES_MODE
+    *
+    * @return encryption results
+    * @retval true      successful
+    * @retval false     fail
+    *
+    * @note   HWAES_DMA_RX_CH_NUM and HWAES_DMA_TX_CH_NUM DMA channels are occupied by this function
+    */
+bool hw_aes_decrypt128_use_dma(uint32_t *p_in, uint32_t *p_out, uint16_t data_word_len,
+                               uint32_t *key, uint32_t *iv, T_HW_AES_MODE mode);
+/**
+    * @brief  256 bit AES encryption via DMA on specified plain data and keys.
+    *
+    * @param[in]  p_in              specified plain data to be encrypted
+    * @param[out]  p_out            output buffer to store encrypted data
+    * @param[in]  data_word_len     input buffer length
+    * @param[in]  key               key buffer
+    * @param[in]  iv                initialization vector for AES CBC mode
+    * @param[in]  mode              AES mode specified by @ref T_HW_AES_MODE
+    *
+    * @return encryption results
+    * @retval true      successful
+    * @retval false     fail
+    *
+    * @note   HWAES_DMA_RX_CH_NUM and HWAES_DMA_TX_CH_NUM DMA channels are occupied by this function
+    */
+bool hw_aes_encrypt256_use_dma(uint32_t *p_in, uint32_t *p_out, uint16_t data_word_len,
+                               uint32_t *key, uint32_t *iv, T_HW_AES_MODE mode);
+/**
+    * @brief  256 bit AES decryption via DMA on specified data and keys.
+    *
+    * @param[in]  p_in              specified encrypted data to be decrypted
+    * @param[out]  p_out            output buffer to store plain data
+    * @param[in]  data_word_len     input buffer length
+    * @param[in]  key               key buffer
+    * @param[in]  iv                initialization vector for AES CBC mode
+    * @param[in]  mode              AES mode specified by @ref T_HW_AES_MODE
+    *
+    * @return encryption results
+    * @retval true      successful
+    * @retval false     fail
+    *
+    * @note   HWAES_DMA_RX_CH_NUM and HWAES_DMA_TX_CH_NUM DMA channels are occupied by this function
+    */
+bool hw_aes_decrypt256_use_dma(uint32_t *p_in, uint32_t *p_out, uint16_t data_word_len,
+                               uint32_t *key, uint32_t *iv, T_HW_AES_MODE mode);
+
+/**
+ * @brief swap src byte order to dst
+ *
+ * @param[in] src: input buffer
+ * @param[out] dst: output buffer
+ * @param[in] len: byte length that want to convert
+ */
+void swap_buf(const uint8_t *src, uint8_t *dst, uint32_t len);
+
+/** @} */ /* End of group HW_AES_Exported_Functions */
+/** @} */ /* End of group HW_AES */
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/bee/drivers/crypto/inc/rtl8752h/rtl876x_hw_sha256.h b/bee/drivers/crypto/inc/rtl8752h/rtl876x_hw_sha256.h
new file mode 100644
index 00000000..78b9501d
--- /dev/null
+++ b/bee/drivers/crypto/inc/rtl8752h/rtl876x_hw_sha256.h
@@ -0,0 +1,126 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *               Define to prevent recursive inclusion
+ *============================================================================*/
+#ifndef __RTL876X_HW_SHA256_H
+#define __RTL876X_HW_SHA256_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*============================================================================*
+ *                               Header Files
+*============================================================================*/
+#include <stdbool.h>
+#include "rtl876x.h"
+
+/** @defgroup  HW_SHA256 Hardware SHA256
+    * @brief APIs for Hardware SHA256
+    * @{
+    */
+
+/*============================================================================*
+ *                         Types
+ *============================================================================*/
+/** @defgroup HW_SHA256_Exported_Types Hardware SHA256 Exported Types
+  * @brief
+  * @{
+  */
+typedef struct
+{
+    uint32_t total[2];          /*!< The number of Bytes processed.  */
+    uint32_t state[8];          /*!< The intermediate digest state.  */
+    uint8_t buffer[64];         /*!< The data block being processed. */
+    int is224;                  /*!< unused, just align mbedtls structure */
+} HW_SHA256_CTX;
+
+typedef enum
+{
+    HW_SHA256_CPU_MODE,
+    HW_SHA256_DMA_MODE
+} HW_SHA256_ACCESS_MODE;
+
+
+/** End of HW_SHA256_Exported_Types
+  * @}
+  */
+
+/*============================================================================*
+ *                              Functions
+ *============================================================================*/
+/** @defgroup  HW_SHA256_Exported_Functions Hardware SHA256 Exported Functions
+    * @brief
+    * @{
+    */
+/**
+  * @brief   Wrapped interface to generate sha256 data.
+  *
+  * @param[in]  input input data
+  * @param[in]  byte_len data length
+  * @param[in]  result generated sha256 data
+  * @param[in]  mode cpu mode/dma mode
+  *
+  * @return status of generating sha256 data
+  * @retval true    successful
+  * @retval false   fail
+  *
+  */
+extern bool (*hw_sha256)(uint8_t *input, uint32_t byte_len, uint32_t *result, int mode);
+
+/**
+  * @brief  Enable the hw_sha256 module
+  */
+void hw_sha256_init(void);
+
+/**
+  * @brief  Initialize and configure the hw_sha256 module
+  *
+  * @param[in]  ctx sha256 configuration
+  * @param[in]  iv initial vector
+  *
+  */
+extern void (*hw_sha256_start)(HW_SHA256_CTX *ctx, uint32_t *iv);
+
+/**
+  * @brief   Use the hw_sha256 module to generate sha256 data.
+  *
+  * @param[in]  ctx sha256 configuration
+  * @param[in]  input input data
+  * @param[in]  byte_len data length
+  *
+  * @return status of generating sha256 data
+  * @retval true    successful
+  * @retval false   fail
+  *
+  */
+extern bool (*hw_sha256_cpu_update)(HW_SHA256_CTX *ctx, uint8_t *input, uint32_t byte_len);
+
+/**
+  * @brief  Process finishing operation of the hw_sha256 module
+  *
+  * @param[in]  ctx sha256 configuration
+  * @param[out]  result calculation result
+  *
+  * @return status of processing finishing operation
+  * @retval true    successful
+  * @retval false   fail
+  */
+extern bool (*hw_sha256_finish)(HW_SHA256_CTX *ctx, uint32_t *result);
+
+/** End of HW_SHA256_Exported_Functions
+  * @}
+  */
+
+/** End of HW_SHA256
+  * @}
+  */
+#ifdef __cplusplus
+}
+#endif
+#endif /*__RTL876X_HW_SHA256_H*/
diff --git a/bee/drivers/crypto/inc/rtl87x2g/aes_api.h b/bee/drivers/crypto/inc/rtl87x2g/aes_api.h
new file mode 100644
index 00000000..a5a5ac6d
--- /dev/null
+++ b/bee/drivers/crypto/inc/rtl87x2g/aes_api.h
@@ -0,0 +1,316 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *                      Define to prevent recursive inclusion
+ *============================================================================*/
+#ifndef _AES_API_H_
+#define _AES_API_H_
+
+/*============================================================================*
+ *                               Header Files
+*============================================================================*/
+#include <stdint.h>
+#include <stdbool.h>
+
+#define AES256 1
+#define ECB    1
+#define CBC    1
+/** @defgroup AES_API AES API Sets
+  * @brief API sets for aes encryption implementation
+  * @{
+  */
+
+/*============================================================================*
+  *                                Structures
+  *============================================================================*/
+/** @defgroup AES_API_Exported_Types AES API Sets Exported Types
+  * @brief
+  * @{
+  */
+typedef struct
+{
+    uint8_t *input;
+    uint8_t *iv;
+    uint32_t word_len;
+} AES_CBC_CTX;
+
+typedef enum
+{
+    CRYPTO_ERR_SUCCESS = 0,
+    CRYPTO_ERR_MODE_NOT_SUPPORT,
+    CRYPTO_ERR_KEY_IV_NOT_EXIST,
+    CRYPTO_ERR_KEY_LEN_MISMATCH,
+    CRYPTO_ERR_DATA_LEN_NOT_16B_ALIGNED,
+
+    CRYPTO_ERR_MAX = 0xFF
+} crypto_err_t;
+
+/** End of AES_API_Exported_Types
+  * @}
+  */
+
+/*============================================================================*
+  *                                Functions
+  *============================================================================*/
+/** @defgroup AES_API_Exported_Functions AES API Sets Exported Functions
+  * @{
+  */
+/**
+    * @brief  byte swap
+    * @param  src          source address
+    * @param  dst          destination address
+    * @param  len          swap size
+    */
+
+void swap_buf(const uint8_t *src, uint8_t *dst, uint16_t len);
+
+/**
+    * @brief  128 bit AES ECB encryption on speicified plaintext and keys
+    * @note   least significant octet of encrypted data corresponds to encypted[0]
+    * @param  plaintext    specifed plain text to be encypted
+    * @param  key          keys to encrypt the plaintext
+    * @param  encrypted    output buffer to store encrypted data
+    * @return encryption results
+    * @retval true      successful
+    * @retval false     fail
+    */
+bool aes128_ecb_encrypt(uint8_t plaintext[16], const uint8_t key[16], uint8_t *encrypted);
+/**
+    * @brief  128 bit AES ECB encryption on speicified plaintext and keys
+    * @note   most significant octet of encrypted data corresponds to encypted[0]
+    * @param  plaintext    specifed plain text to be encypted
+    * @param  key          keys to encrypt the plaintext
+    * @param  encrypted    output buffer to store encrypted data
+    * @return encryption results
+    * @retval true      successful
+    * @retval false     fail
+    */
+bool aes128_ecb_encrypt_msb2lsb(uint8_t plaintext[16], const uint8_t key[16],
+                                uint8_t *encrypted);
+
+/**
+    * @brief  128 bit AES ECB decryption on speicified encrypted data and keys
+    * @note   least significant octet of encrypted data corresponds to encypted[0]
+    * @param  input    specifed encypted data to be decypted
+    * @param  key          keys to decrypt the data
+    * @param  output    output buffer to store plain data
+    * @return decryption results
+    * @retval true      successful
+    * @retval false     fail
+    */
+bool aes128_ecb_decrypt(uint8_t *input, const uint8_t *key, uint8_t *output);
+/**
+    * @brief  128 bit AES ECB decryption on speicified encrypted data and keys
+    * @note   most significant octet of encrypted data corresponds to encypted[0]
+    * @param  input    specifed encypted data to be decypted
+    * @param  key          keys to decrypt the data
+    * @param  output    output buffer to store plain data
+    * @return decryption results
+    * @retval true      successful
+    * @retval false     fail
+    */
+bool aes128_ecb_decrypt_msb2lsb(uint8_t *input, const uint8_t *key, uint8_t *output);
+
+/**
+    * @brief  128 bit AES CBC encryption on speicified plaintext and keys
+    * @note   least significant octet of encrypted data corresponds to encypted[0]
+    * @param  cbc_ctx   specifed plain text to be encypted, iv and length in words
+    * @param  key          keys to decrypt the data
+    * @param  encrypted    output buffer to store encrypted data
+    * @return decryption results
+    * @retval true      successful
+    * @retval false     fail
+    */
+bool aes128_cbc_encrypt(AES_CBC_CTX *cbc_ctx, const uint8_t *key, uint8_t *encrypted);
+
+/**
+    * @brief  128 bit AES CBC decryption on speicified encrypted data and keys
+    * @note   least significant octet of encrypted data corresponds to encypted[0]
+    * @param  cbc_ctx   specifed encypted data to be decypted, iv and length in words
+    * @param  key       keys to decrypt the data
+    * @param  output    output buffer to store plain data
+    * @return decryption results
+    * @retval true      successful
+    * @retval false     fail
+    */
+bool aes128_cbc_decrypt(AES_CBC_CTX *cbc_ctx, const uint8_t *key, uint8_t *output);
+
+/**
+    * @brief  256 bit AES ECB encryption on speicified plaintext and keys
+    * @note   least significant octet of encrypted data corresponds to encypted[0]
+    * @param  plaintext    specifed plain text to be encypted
+    * @param  key          keys to encrypt the plaintext
+    * @param  encrypted    output buffer to store encrypted data
+    * @return encryption results
+    * @retval true      successful
+    * @retval false     fail
+    */
+bool aes256_ecb_encrypt(uint8_t plaintext[16], const uint8_t key[32], uint8_t *encrypted);
+/**
+    * @brief  256 bit AES ECB encryption on speicified plaintext and keys
+    * @note   most significant octet of encrypted data corresponds to encypted[0]
+    * @param  plaintext    specifed plain text to be encypted
+    * @param  key          keys to encrypt the plaintext
+    * @param  encrypted    output buffer to store encrypted data
+    * @return encryption results
+    * @retval true      successful
+    * @retval false     fail
+    */
+bool aes256_ecb_encrypt_msb2lsb(uint8_t plaintext[16], const uint8_t key[32],
+                                uint8_t *encrypted);
+/**
+    * @brief  256 bit AES ECB decryption on speicified encrypted data and keys
+    * @note   least significant octet of encrypted data corresponds to encypted[0]
+    * @param  input    specifed encypted data to be decypted
+    * @param  key          keys to decrypt the data
+    * @param  output    output buffer to store plain data
+    * @return decryption results
+    * @retval true      successful
+    * @retval false     fail
+    */
+bool aes256_ecb_decrypt(uint8_t *input, const uint8_t *key, uint8_t *output);
+/**
+    * @brief  256 bit AES ECB decryption on speicified encrypted data and keys
+    * @note   most significant octet of encrypted data corresponds to encypted[0]
+    * @param  input    specifed encypted data to be decypted
+    * @param  key          keys to decrypt the data
+    * @param  output    output buffer to store plain data
+    * @return decryption results
+    * @retval true      successful
+    * @retval false     fail
+    */
+bool aes256_ecb_decrypt_msb2lsb(uint8_t *input, const uint8_t *key, uint8_t *output);
+
+/**
+    * @brief  256 bit AES CBC encryption on speicified plaintext and keys
+    * @note   least significant octet of encrypted data corresponds to encypted[0]
+    * @param  cbc_ctx   specifed plain text to be encypted, iv and length in words
+    * @param  key          keys to decrypt the data
+    * @param  encrypted    output buffer to store encrypted data
+    * @return decryption results
+    * @retval true      successful
+    * @retval false     fail
+    */
+bool aes256_cbc_encrypt(AES_CBC_CTX *cbc_ctx, const uint8_t *key, uint8_t *encrypted);
+
+/**
+    * @brief  256 bit AES CBC decryption on speicified encrypted data and keys
+    * @note   least significant octet of encrypted data corresponds to encypted[0]
+    * @param  cbc_ctx   specifed encypted data to be decypted, iv and length in words
+    * @param  key       keys to decrypt the data
+    * @param  output    output buffer to store plain data
+    * @return decryption results
+    * @retval true      successful
+    * @retval false     fail
+    */
+bool aes256_cbc_decrypt(AES_CBC_CTX *cbc_ctx, const uint8_t *key, uint8_t *output);
+
+/**
+    * @brief  128 bit AES CTR encryption on speicified plaintext and load key id
+    * @note   least significant octet of encrypted data corresponds to data[0]
+    * @param  input    input buffer to store plain data
+    * @param  key_material_id   represents a key that is stored in the first 4KB of the flash, and it needs to be programmed using the MP Tool.
+    * @param  output    output buffer to store encrypted data
+    * @param  data_len    length of data
+    * @return crypto_err_t results
+    */
+crypto_err_t aes128_ctr_encrypt_with_load_key(const unsigned char *input, uint8_t key_material_id,
+                                              unsigned char *output, uint32_t data_len);
+
+/**
+    * @brief  128 bit AES CTR decryption on speicified encrypted data and load key id
+    * @note   least significant octet of encrypted data corresponds to data[0]
+    * @param  input    input buffer to store encrypted data
+    * @param  key_material_id   represents a key that is stored in the first 4KB of the flash, and it needs to be programmed using the MP Tool.
+    * @param  output    output buffer to store plain data
+    * @param  data_len    length of data
+    * @return crypto_err_t results
+    */
+crypto_err_t aes128_ctr_decrypt_with_load_key(const unsigned char *input, uint8_t key_material_id,
+                                              unsigned char *output, uint32_t data_len);
+
+/**
+    * @brief  256 bit AES CTR encryption on speicified plaintext and load key id
+    * @note   least significant octet of encrypted data corresponds to data[0]
+    * @param  input    input buffer to store plain data
+    * @param  key_material_id   represents a key that is stored in the first 4KB of the flash, and it needs to be programmed using the MP Tool.
+    * @param  output    output buffer to store encrypted data
+    * @param  data_len    length of data
+    * @return crypto_err_t results
+    */
+crypto_err_t aes256_ctr_encrypt_with_load_key(const unsigned char *input, uint8_t key_material_id,
+                                              unsigned char *output, uint32_t data_len);
+
+/**
+    * @brief  256 bit AES CTR decryption on speicified encrypted data and load key id
+    * @note   least significant octet of encrypted data corresponds to data[0]
+    * @param  input    input buffer to store encrypted data
+    * @param  key_material_id   represents a key that is stored in the first 4KB of the flash, and it needs to be programmed using the MP Tool.
+    * @param  output    output buffer to store plain data
+    * @param  data_len    length of data
+    * @return crypto_err_t results
+    */
+crypto_err_t aes256_ctr_decrypt_with_load_key(const unsigned char *input, uint8_t key_material_id,
+                                              unsigned char *output, uint32_t data_len);
+
+/**
+    * @brief  128 bit AES CBC encryption on speicified plaintext and load key id
+    * @note   least significant octet of encrypted data corresponds to data[0]
+    * @param  input    input buffer to store plain data
+    * @param  key_material_id   represents a key that is stored in the first 4KB of the flash, and it needs to be programmed using the MP Tool.
+    * @param  output    output buffer to store encrypted data
+    * @param  data_len    length of data which should be 16 bytes aligned
+    * @return crypto_err_t results
+    */
+crypto_err_t aes128_cbc_encrypt_with_load_key(const unsigned char *input, uint8_t key_material_id,
+                                              unsigned char *output, uint32_t data_len);
+
+/**
+    * @brief  128 bit AES CBC decryption on speicified encrypted data and load key id
+    * @note   least significant octet of encrypted data corresponds to data[0]
+    * @param  input    input buffer to store encrypted data
+    * @param  key_material_id   represents a key that is stored in the first 4KB of the flash, and it needs to be programmed using the MP Tool.
+    * @param  output    output buffer to store plain data
+    * @param  data_len    length of data which should be 16 bytes aligned
+    * @return crypto_err_t results
+    */
+crypto_err_t aes128_cbc_decrypt_with_load_key(const unsigned char *input, uint8_t key_material_id,
+                                              unsigned char *output, uint32_t data_len);
+
+/**
+    * @brief  256 bit AES CBC encryption on speicified plaintext and load key id
+    * @note   least significant octet of encrypted data corresponds to data[0]
+    * @param  input    input buffer to store plain data
+    * @param  key_material_id   represents a key that is stored in the first 4KB of the flash, and it needs to be programmed using the MP Tool.
+    * @param  output    output buffer to store encrypted data
+    * @param  data_len    length of data which should be 16 bytes aligned
+    * @return crypto_err_t results
+    */
+crypto_err_t aes256_cbc_encrypt_with_load_key(const unsigned char *input, uint8_t key_material_id,
+                                              unsigned char *output, uint32_t data_len);
+
+/**
+    * @brief  256 bit AES CBC decryption on speicified encrypted data and load key id
+    * @note   least significant octet of encrypted data corresponds to data[0]
+    * @param  input    input buffer to store encrypted data
+    * @param  key_material_id   represents a key that is stored in the first 4KB of the flash, and it needs to be programmed using the MP Tool.
+    * @param  output    output buffer to store plain data
+    * @param  data_len    length of data which should be 16 bytes aligned
+    * @return crypto_err_t results
+    */
+crypto_err_t aes256_cbc_decrypt_with_load_key(const unsigned char *input, uint8_t key_material_id,
+                                              unsigned char *output, uint32_t data_len);
+
+/** End of AES_API_Exported_Functions
+  * @}
+  */
+
+/** End of AES_API
+  * @}
+  */
+
+#endif
diff --git a/bee/drivers/crypto/inc/rtl87x2g/crypto_engine_nsc.h b/bee/drivers/crypto/inc/rtl87x2g/crypto_engine_nsc.h
new file mode 100644
index 00000000..1c60e07c
--- /dev/null
+++ b/bee/drivers/crypto/inc/rtl87x2g/crypto_engine_nsc.h
@@ -0,0 +1,153 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *                      Define to prevent recursive inclusion
+ *============================================================================*/
+#ifndef _CRYPTO_ENGINE_NSC_H_
+#define _CRYPTO_ENGINE_NSC_H_
+
+#include <stdint.h>
+#include <stdbool.h>
+
+/** @defgroup CRYPTO_ENGINE Crypto Engine
+  * @brief
+  * @{
+  */
+
+/*============================================================================*
+ *                              Types
+ *============================================================================*/
+/** @defgroup CRYPTO_ENGINE_Exported_Types Crypto Engine Exported Types
+  * @brief
+  * @{
+  */
+/* public key engine */
+typedef enum
+{
+    ERR_NONE            = 0x0,
+    ERR_PRIME           = 0x1,
+    ERR_R2_MOD_N        = 0x2,
+    ERR_ECC_ODD_POINT   = 0x4,
+    ERR_ECC_Z           = 0x8,
+    ERR_MODULAR_INV     = 0x10,
+    ERR_N_ST_INPUT      = 0x20,
+    ERR_NO_VALID_EXP    = 0x40,
+    ERR_INVALID_INPUT   = 0x80,
+} ERR_CODE;
+
+typedef enum
+{
+    ECC_PRIME_MODE       = 0,   // 3'b000
+    ECC_BINARY_MODE      = 1,   // 3'b001
+    RSA_MODE             = 2,   // 3'b010
+    ECC_EDWARDS_CURVE    = 3,   // 3'b011
+    ECC_MONTGOMERY_CURVE = 7,   // 3'b111
+} PKE_MODE;
+
+typedef struct
+{
+    uint32_t x[16];
+    uint32_t y[16];
+    uint32_t z[16];
+} ECC_POINT;
+
+typedef struct
+{
+    uint32_t *N;    // modular, also called p
+    uint32_t *A;    // curve parameter a
+    uint32_t *B;    // curve parameter b
+    uint32_t *n;    // order of G
+    ECC_POINT G;    // base point
+
+    uint32_t key_bits;
+    PKE_MODE mode;
+
+} ECC_GROUP;
+
+/* SHA2-256 */
+
+typedef enum
+{
+    HW_SHA256_CPU_MODE,
+    HW_SHA256_DMA_MODE
+} HW_SHA256_ACCESS_MODE;
+
+typedef struct
+{
+    uint32_t total[2];          /*!< The number of Bytes processed.  */
+    uint32_t state[8];          /*!< The intermediate digest state.  */
+    uint8_t buffer[64];         /*!< The data block being processed. */
+    int is224;                  /*!< unused, just align mbedtls structure */
+} HW_SHA256_CTX;
+/** End of CRYPTO_ENGINE_Exported_Types
+  * @}
+  */
+
+/*============================================================================*
+ *                              Functions
+ *============================================================================*/
+/** @defgroup CRYPTO_ENGINE_Exported_Functions Crypto Engine Exported Functions
+  * @brief
+  * @{
+  */
+/**
+    * @brief  hardware sha256 process
+    * @param  input input buffer pointer
+    * @param  byte_len    size
+    * @param  result      output buffer pointer
+    * @param  mode        hardware sha256 mode
+    * @return hardware sha256 results
+    * @retval true      successful
+    * @retval false     fail
+    */
+bool hw_sha256(uint8_t *input, uint32_t byte_len, uint32_t *result, int mode);
+
+/**
+    * @brief  hardware sha256 init
+    * @param  none
+    * @return void
+    */
+void hw_sha256_init(void);
+
+/**
+    * @brief  hardware sha256 start
+    * @param  ctx pointer of ctx
+    * @param  iv pointer of iv
+    * @return void
+    */
+void hw_sha256_start(HW_SHA256_CTX *ctx, uint32_t *iv);
+
+/**
+    * @brief  hardware sha256 cpu update
+    * @param  ctx pointer of ctx
+    * @param  input input buffer pointer
+    * @param  byte_len    size
+    * @return hardware sha256 update results
+    * @retval true      successful
+    * @retval false     fail
+    */
+bool hw_sha256_cpu_update(HW_SHA256_CTX *ctx, uint8_t *input, uint32_t byte_len);
+
+/**
+    * @brief  hardware sha256 finish
+    * @param  ctx pointer of ctx
+    * @param  result      output buffer pointer
+    * @return hardware sha256 finish results
+    * @retval true      successful
+    * @retval false     fail
+    */
+bool hw_sha256_finish(HW_SHA256_CTX *ctx, uint32_t *result);
+
+/** End of CRYPTO_ENGINE_Exported_Functions
+  * @}
+  */
+
+/** End of CRYPTO_ENGINE
+  * @}
+  */
+
+#endif
\ No newline at end of file
diff --git a/bee/drivers/debug/CMakeLists.txt b/bee/drivers/debug/CMakeLists.txt
new file mode 100644
index 00000000..4299d8a5
--- /dev/null
+++ b/bee/drivers/debug/CMakeLists.txt
@@ -0,0 +1,6 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+if(CONFIG_SOC_SERIES_RTL87X2J)
+    zephyr_include_directories(inc)
+endif()
diff --git a/bee/drivers/debug/inc/debug_port.h b/bee/drivers/debug/inc/debug_port.h
new file mode 100644
index 00000000..14a3139a
--- /dev/null
+++ b/bee/drivers/debug/inc/debug_port.h
@@ -0,0 +1,197 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: LicenseRef-Realtek-5-Clause
+ */
+
+/*============================================================================*
+ *                        Define to prevent recursive inclusion
+ *============================================================================*/
+#ifndef DEBUG_PORT_H
+#define DEBUG_PORT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*============================================================================*
+ *                        Header Files
+ *============================================================================*/
+#include "utils/rtl_utils.h"
+#if defined (CONFIG_SOC_SERIES_RTL87X3J)
+#include "debug/src/device/rtl87x3j/debug_port_def.h"
+#elif defined (CONFIG_SOC_SERIES_RTL87X2J)
+#include "debug/src/device/rtl87x2j/debug_port_def.h"
+#endif
+
+/*============================================================================*
+ *                        Constants
+ *============================================================================*/
+#define PIN_GROUP_TABLE_SIZE        8
+
+/**
+  * @brife Debug Mode Select Group Struct
+  * @notes User can select debug mode group for different source signals
+  */
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t mode_sel0: 4;
+        uint32_t mode_sel1: 4;
+        uint32_t mode_sel2: 4;
+        uint32_t mode_sel3: 4;
+        uint32_t src_sel0: 4;
+        uint32_t src_sel1: 4;
+        uint32_t src_sel2: 4;
+        uint32_t src_sel3: 4;
+    } b;
+} T_GROUP_CONFIG;
+
+/**
+  * @brife Debug Mode Select Platform Struct
+  * @notes User can select debug port in different platform
+  */
+typedef enum
+{
+    DEBUG_PORT_IN_PLATFORM,         //Config debug port in platform.
+#if (DEBUG_PORT_SUPPORT_MULTI_PLATFORM == 1)
+    DEBUG_PORT_IN_SHARE_PLATFORM,   //Config debug port in share platform.
+    DEBUG_PORT_IN_NETWORK,          //Config debug port in network.
+#endif
+} T_DEBUG_PORT_PLATFORM;
+
+typedef enum
+{
+    PCK600_QACTIVE_IDLE = 0,
+    PCK600_QACTIVE_ACTIVE = 1,
+    PCK600_QACTIVE_ERROR = 2,
+} PCK600_QACTIVE_STATUS_T;
+
+/*============================================================================*
+ *                         Functions
+ *============================================================================*/
+/**
+  * @brief  set debug mode on specific pin
+  * @param  pin_group_table: the pin group table pointer.
+  *         This parameter can be combinated by user himself.
+  *         For example pin_group_table can be following values:
+  *         uint8_t debug_pin_group[8] =
+  *         {
+  *            DBG_PIN_GROUP10,
+  *            DBG_PIN_GROUP11,
+  *            DBG_PIN_GROUP8,
+  *            DBG_PIN_GROUP7,
+  *            DBG_PIN_GROUP5,
+  *            DBG_PIN_GROUP0,
+  *            DBG_PIN_GROUP1,
+  *            DBG_PIN_GROUP2,
+  *         };
+  * @param  dbg_bitmap: the pin bitmap.
+  * @retval None
+  */
+void debug_port_set_pin_bit_map(uint8_t *pin_group_table, uint32_t dbg_bitmap);
+
+/**
+  * @brief  Open the debug port mode on specific pins
+  * @param  sel_group: select debug mode group from T_DEBUG_MODE
+  * @retval None
+  *
+  * <b>Example usage</b>
+  * \code{.c}
+  *
+  * const T_GROUP_CONFIG group_config =
+  * {
+  *     .b.mode_sel0 = DIGI_DBG_FWREG_CTRL,
+  *     .b.mode_sel1 = DIGI_DBG_FWREG_CTRL,
+  *     .b.mode_sel2 = DIGI_DBG_FWREG_CTRL,
+  *     .b.mode_sel3 = DIGI_DBG_FWREG_CTRL,
+  *     .b.src_sel0  = 0,
+  *     .b.src_sel1  = 1,
+  *     .b.src_sel2  = 2,
+  *     .b.src_sel3  = 3,
+  * };
+  * debug_port_open_rom(group_config);
+  * \endcode
+  */
+void debug_port_open(T_GROUP_CONFIG group_config);
+
+#if (DEBUG_PORT_SUPPORT_QACTIVE_STATUS == 1)
+/**
+  * @brief  set debug mode on specific pin
+  * @param  peripheral: can be /ref PINMUX_CORE_DEBUG_PORT.
+  * @param  pin_group_table: the pin group table pointer.
+  *         This parameter can be combinated by user himself.
+  *         For example pin_group_table can be following values:
+  *         uint8_t debug_pin_group[8] =
+  *         {
+  *            DBG_PIN_GROUP_INVALID,
+  *            DBG_PIN_GROUP1,
+  *            DBG_PIN_GROUP_INVALID,
+  *            DBG_PIN_GROUP_INVALID,
+  *            DBG_PIN_GROUP_INVALID,
+  *            DBG_PIN_GROUP2,
+  *            DBG_PIN_GROUP_INVALID,
+  *            DBG_PIN_GROUP_INVALID,
+  *         };
+  * @retval None
+    *
+    * <b>Example usage</b>
+  * \code{.c}
+  *
+  * void debug_port_sample(void)
+  * {
+  *     debug_port_pck600_qactive_output(PCK600_QACTIVE_CORE_DEVICE2, debug_pin_group);
+  * }
+  * \endcode
+  */
+void debug_port_pck600_qactive_output(uint32_t group, uint8_t *pin_group_table);
+
+uint64_t debug_port_pck600_qactive_get_device_mask(void);
+
+PCK600_QACTIVE_STATUS_T debug_port_pck600_qactive_get_device_status(PCK600_QACTIVE_DEVICE_T device);
+#endif
+
+#if (DEBUG_PORT_SUPPORT_AON_DEBUG == 1)
+/**
+  * @brief  set debug mode on specific pin
+  * @param  debug_select: can be /ref AON_DEBUG_PORT.
+  * @param  NewState: Newstate of the specified peripheral.
+  *
+  * @retval None
+    *
+    * <b>Example usage</b>
+  * \code{.c}
+  *
+  * void debug_port_sample(void)
+  * {
+  *     debug_port_aon(DEBUG_PCK600_OUTPUT_TO_VPON_PPU, ENABLE);
+  * }
+  * \endcode
+  */
+void debug_port_aon_output(AON_DEBUG_PORT debug_select, FunctionalState NewState);
+#endif
+
+#if (DEBUG_PORT_SUPPORT_MULTI_PLATFORM == 1)
+/**
+  * @brief  Config debug port in which platform.
+  * @param  platform: select platform from \ref T_DEBUG_PORT_PLATFORM.
+  *
+  * <b>Example usage</b>
+  * \code{.c}
+  *
+  * debug_port_set_platform(DEBUG_PORT_IN_PLATFORM);
+  * debug_port_open(group_config);
+  * debug_port_set_pin_bit_map(pin_group, 0xffffffff);
+  * \endcode
+  */
+void debug_port_set_platform(T_DEBUG_PORT_PLATFORM platform);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _DEBUG_PORT_H_ */
+
diff --git a/bee/drivers/debug/inc/pck600_snapshot.h b/bee/drivers/debug/inc/pck600_snapshot.h
new file mode 100644
index 00000000..c0e23ff1
--- /dev/null
+++ b/bee/drivers/debug/inc/pck600_snapshot.h
@@ -0,0 +1,94 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: LicenseRef-Realtek-5-Clause
+ */
+
+/*============================================================================*
+ *                        Define to prevent recursive inclusion
+ *============================================================================*/
+#ifndef PCK600_SNAPSHOT_H
+#define PCK600_SNAPSHOT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*============================================================================*
+ *                        Header Files
+ *============================================================================*/
+#include "utils/rtl_utils.h"
+#if defined (CONFIG_SOC_SERIES_RTL87X3J)
+#include "debug/src/device/rtl87x3j/pck600_snapshot_def.h"
+#elif defined (CONFIG_SOC_SERIES_RTL87X2J)
+#include "debug/src/device/rtl87x2j/pck600_snapshot_def.h"
+#endif
+
+/*============================================================================*
+ *                        Constants
+ *============================================================================*/
+
+typedef enum
+{
+    PCK600_SNAPSHOT_SUCCESS          = 0,
+    PCK600_SNAPSHOT_FAIL_KEEP_ACTIVE = 1,
+    PCK600_SNAPSHOT_FAIL_RE_WAKEUP   = 2,
+    PCK600_SNAPSHOT_FAIL_MAX         = 3,
+} PCK600_SNAPSHOT_STATUS_T;
+
+/*============================================================================*
+ *                         Functions
+ *============================================================================*/
+/**
+ * \brief  Get the status of all module when entering lpm.
+ *
+ * \retval The status of all module.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void debug_port_sample(void)
+ * {
+ *     uint64_t mask = pck600_snapshot_get_device_mask();
+ * }
+ * \endcode
+ */
+uint64_t pck600_snapshot_get_device_mask(void);
+
+/**
+ * \brief  Get the status of the specified module when entering lpm.
+ * \param  device: Can be \ref PCK600_SNAPSHOT_DEVICE_T.
+ *
+ * \retval The status of module \ref PCK600_SNAPSHOT_STATUS_T.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void debug_port_sample(void)
+ * {
+ *     pck600_snapshot_get_device_status(PCK600_SNAPSHOT_UART0);
+ * }
+ * \endcode
+ */
+PCK600_SNAPSHOT_STATUS_T pck600_snapshot_get_device_status(PCK600_SNAPSHOT_DEVICE_T device);
+
+/**
+ * \brief  Clear all the status of the qch.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void debug_port_sample(void)
+ * {
+ *     pck600_snapshot_clear_all_device_status();
+ * }
+ * \endcode
+ */
+void pck600_snapshot_clear_all_device_status(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PCK600_SNAPSHOT_H */
+
diff --git a/bee/drivers/debug/src/CMakeLists.txt b/bee/drivers/debug/src/CMakeLists.txt
new file mode 100644
index 00000000..4bcc9ef6
--- /dev/null
+++ b/bee/drivers/debug/src/CMakeLists.txt
@@ -0,0 +1,7 @@
+#
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+#
+# SPDX-License-Identifier: LicenseRef-Realtek-5-Clause
+#
+
+add_subdirectory(device)
diff --git a/bee/drivers/debug/src/device/rtl87x2j/debug_port_def.h b/bee/drivers/debug/src/device/rtl87x2j/debug_port_def.h
new file mode 100644
index 00000000..9bb631d3
--- /dev/null
+++ b/bee/drivers/debug/src/device/rtl87x2j/debug_port_def.h
@@ -0,0 +1,259 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: LicenseRef-Realtek-5-Clause
+ */
+
+#ifndef RTL_DEBUG_PORT_DEF_H
+#define RTL_DEBUG_PORT_DEF_H
+
+#ifdef  __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/*============================================================================*
+ *                        Header Files
+ *============================================================================*/
+#include "utils/rtl_utils.h"
+#include "pcc_reg.h"
+
+/*============================================================================*
+ *                          Debug Port Defines
+ *============================================================================*/
+#define DEBUG_PORT_SUPPORT_MULTI_PLATFORM            (0)
+#define DEBUG_PORT_SUPPORT_QACTIVE_STATUS            (1)
+#define DEBUG_PORT_SUPPORT_AON_DEBUG                 (1)
+
+/*============================================================================*
+ *                          Debug Port TYPE
+ *============================================================================*/
+typedef enum
+{
+    DBG_PIN_GROUP0,  //P0_0 P0_1 P0_2 P0_3
+    DBG_PIN_GROUP1,  //P0_4 P0_5 P0_6 P0_7,
+    DBG_PIN_GROUP2,  //P1_0 P1_1 P1_6 P1_7
+    DBG_PIN_GROUP3,  //P2_0 P2_1 P2_2 P2_3
+    DBG_PIN_GROUP4,  //P2_4 P2_5 P2_6 P2_7
+    DBG_PIN_GROUP5,  //P3_0 P3_1 P3_2 P3_3
+    DBG_PIN_GROUP6,  //P3_4 P3_5 P3_6 P4_0
+    DBG_PIN_GROUP7,  //P4_1 P4_2 P4_3 P5_0
+    DBG_PIN_GROUP8,  //P5_1 P5_2 P6_0 P6_1
+    DBG_PIN_GROUP9,  //P6_2 P6_3 P6_4 P6_5
+    DBG_PIN_GROUP10, //P6_6 P6_7 P7_0 P7_1
+    DBG_PIN_GROUP11, //P7_2 P7_3 P7_4 P7_5
+    DBG_PIN_GROUP_INVALID = 0xFF,
+} T_PIN_GROUP;
+
+typedef enum
+{
+    DIGI_DBG_SYSON,
+    DIGI_DBG_BT,
+    DIGI_DBG_PROC,
+    DIGI_DBG_ADC,
+    DIGI_DBG_RTC,
+    DIGI_DBG_SPORT0,
+    DIGI_DBG_SPORT1,
+    DIGI_DBG_AUDIO,
+    DIGI_DBG_CLK_RST_GEN,
+    DIGI_DBG_FWREG_CTRL,
+    DIGI_DBG_PCK600_VAON,
+    DIGI_DBG_PCK600_VPON,
+    DIGI_DBG_RAP_OUT,
+    DIGI_DBG_FWREG_INVERSE,
+    DIGI_DBG_PCK600_VCORE,
+} T_DEBUG_MODE;
+
+typedef enum
+{
+    PCK600_QACTIVE_CORE_DBG_TYPE = 0,
+    PCK600_QACTIVE_CORE_LPDQ_OSC_QREQ,
+    PCK600_QACTIVE_CORE_LPDQ_OSC_QACCEPT,
+    PCK600_QACTIVE_CORE_LPDQ_OSC_QACTIVE_1,
+    PCK600_QACTIVE_CORE_LPDQ_OSC_CG,
+    PCK600_QACTIVE_CORE_LPDQ_PLL1_1,
+    PCK600_QACTIVE_CORE_LPDQ_SDM_QREQ,
+    PCK600_QACTIVE_CORE_LPDQ_SDM_QACCEPT,
+    PCK600_QACTIVE_CORE_LPDQ_SDM_QACTIVE,
+    PCK600_QACTIVE_CORE_LPDQ_XTAL_QREQ,
+    PCK600_QACTIVE_CORE_LPDQ_XTAL_QACCEPT,
+    PCK600_QACTIVE_CORE_LPDQ_XTAL_QACTIVE_1,
+    PCK600_QACTIVE_CORE_LPDQ_XTAL_1,
+    PCK600_QACTIVE_CORE_LPDQ_PLATFORM,
+    PCK600_QACTIVE_CORE_LPDQ_PLATFORM_QACTIVE,
+    PCK600_QACTIVE_CORE_LPDQ_OSC1,
+    PCK600_QACTIVE_CORE_LPDQ_VCORE_QREQ,
+    PCK600_QACTIVE_CORE_LPDQ_VCORE_QACCEPT,
+    PCK600_QACTIVE_CORE_LPDQ_VCORE_QACTIVE_1,
+    PCK600_QACTIVE_CORE_LPDQ_VCORE_1_QREQ,
+    PCK600_QACTIVE_CORE_LPDQ_VCORE_1_QACCEPT,
+    PCK600_QACTIVE_CORE_LPDQ_VCORE_1_QACTIVE,
+    PCK600_QACTIVE_CORE_DEVICE2,
+    PCK600_QACTIVE_CORE_DEVICE3,
+    PCK600_QACTIVE_CORE_DEVICE4,
+    PCK600_QACTIVE_CORE_DEVICE5,
+    PCK600_QACTIVE_CORE_DEVICE6,
+    PCK600_QACTIVE_CORE_DEVICE7,
+    PCK600_QACTIVE_CORE_DEVICE_GROUP,
+    PCK600_QACTIVE_CORE_DEVICE_POW,
+    PCK600_QACTIVE_CORE_LPDQ_OSC,
+    PCK600_QACTIVE_CORE_LPDQ_OSC10M,
+    PCK600_QACTIVE_CORE_LPDQ_XTAL,
+    PCK600_QACTIVE_CORE_DEVICE1,
+    PCK600_QACTIVE_CORE_DEVICE0,
+    PCK600_QACTIVE_CORE_LPCQ_BT,
+    PCK600_QACTIVE_CORE_LPCQ_PLATFORM,
+    PCK600_QACTIVE_CORE_CLKCTRL_PPU_VCORE,
+
+    PCK600_QACTIVE_PON_DBG_TYPE = 0x100,
+    PCK600_QACTIVE_PON_PPU_VCORE,
+    PCK600_QACTIVE_PON_CLK_SOURCE,
+    PCK600_QACTIVE_PON_VPON_DEVICE,
+    PCK600_QACTIVE_PON_VPON_SCH_PLAN,
+    PCK600_QACTIVE_PON_PPU_VCORE_PCSM,
+    PCK600_QACTIVE_PON_LPDQ_PPU_VCORE,
+    PCK600_QACTIVE_PON_LPDQ_OSC128K_VPON,
+    PCK600_QACTIVE_PON_LPDQ_OSC10M_VPON,
+    PCK600_QACTIVE_PON_LPDQ_OSC10M_VPON_QACTIVE,
+    PCK600_QACTIVE_PON_LPDQ_OSC10M_VPON_HV,
+    PCK600_QACTIVE_PON_LPCQ_PLATFORM,
+    PCK600_QACTIVE_PON_CLKCTRL_PPU_VCORE,
+
+    PCK600_QACTIVE_AON_DBG_TYPE = 0x1000,
+    PCK600_QACTIVE_AON_PPU_VPON,
+    PCK600_QACTIVE_AON_PPU_VPON_PCSM,
+    PCK600_QACTIVE_AON_PPU_VPON_QACTIVE,
+    PCK600_QACTIVE_AON_LPDQ_VPON,
+    PCK600_QACTIVE_AON_LPDQ_VPON_QACTIVE_2,
+    PCK600_QACTIVE_AON_LPDQ_VPON_QACTIVE_1,
+    PCK600_QACTIVE_AON_LPDQ_VPON_QACTIVE_0,
+    PCK600_QACTIVE_AON_LPDQ_OSC10M,
+    PCK600_QACTIVE_AON_P2Q_OPMODE,
+    PCK600_QACTIVE_AON_P2Q_MEMOFF,
+    PCK600_QACTIVE_AON_P2Q_ON,
+    PCK600_QACTIVE_AON_CLK_SOURCE_VAON
+} PCK600_QACTIVE_GROUP_T;
+
+typedef enum
+{
+    PCK600_QACTIVE_I2S        = 0,
+    PCK600_QACTIVE_ADC        = 1,
+    PCK600_QACTIVE_UART3      = 2,
+    PCK600_QACTIVE_UART2      = 3,
+    PCK600_QACTIVE_UART1      = 4,
+    PCK600_QACTIVE_UART0      = 5,
+    PCK600_QACTIVE_TMETER     = 6,
+    PCK600_QACTIVE_TIMER1_CH8 = 7,
+    PCK600_QACTIVE_TIMER1_CH7 = 8,
+    PCK600_QACTIVE_TIMER1_CH6 = 9,
+    PCK600_QACTIVE_TIMER1_CH5 = 10,
+    PCK600_QACTIVE_TIMER1_CH4 = 11,
+    PCK600_QACTIVE_TIMER1_CH3 = 12,
+    PCK600_QACTIVE_TIMER1_CH2 = 13,
+    PCK600_QACTIVE_TIMER1_CH1 = 14,
+    PCK600_QACTIVE_TIMER1_CH0 = 15,
+    PCK600_QACTIVE_TIMER0_CH1 = 16,
+    PCK600_QACTIVE_TIMER0_CH0 = 17,
+    PCK600_QACTIVE_SPI3W      = 18,
+    PCK600_QACTIVE_SPI2       = 19,
+    PCK600_QACTIVE_SPI1       = 20,
+    PCK600_QACTIVE_SPI0       = 21,
+    PCK600_QACTIVE_KEYSCAN    = 22,
+    PCK600_QACTIVE_IR         = 23,
+    PCK600_QACTIVE_I2C1       = 24,
+    PCK600_QACTIVE_I2C0       = 25,
+    PCK600_QACTIVE_GPIO       = 26,
+    PCK600_QACTIVE_DMA        = 27,
+    PCK600_QACTIVE_TIMER2_CH0 = 28,
+    PCK600_QACTIVE_CAN        = 29,
+    PCK600_QACTIVE_USB        = 30,
+
+    PCK600_QACTIVE_RFC        = 31,
+    PCK600_QACTIVE_PRO24G     = 32,
+    PCK600_QACTIVE_PCC        = 33,
+    PCK600_QACTIVE_MODEM      = 34,
+    PCK600_QACTIVE_CAL80M     = 35,
+    PCK600_QACTIVE_CAL32K     = 36,
+    PCK600_QACTIVE_CAL10M     = 37,
+    PCK600_QACTIVE_BTMAC      = 38,
+    PCK600_QACTIVE_BT_VEN     = 39,
+    PCK600_QACTIVE_AUDIO      = 40,
+    PCK600_QACTIVE_AACK       = 41,
+    PCK600_QACTIVE_AES        = 42,
+    PCK600_QACTIVE_SHA256     = 43,
+    PCK600_QACTIVE_CPU        = 44, ??
+    PCK600_QACTIVE_SPIC0      = 45,
+    PCK600_QACTIVE_RNG       = 46,
+    PCK600_QACTIVE_VDREG     = 47,
+
+    PCK600_QACTIVE_DEVICE_MAX,
+
+} PCK600_QACTIVE_DEVICE_T;
+
+/**
+ *         DEBUG MUX            |          P4_0           |          P4_1           |          P4_2           |          MICBIAS        |          P2_1           |          P2_5           |          P2_6           |          P2_7           |
+ * -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+ * DEBUG_PCSM_STATE_A           | CLK_CTRL_OSC128K_PCSM   | CLK_CTRL_OSC128K_PCSM   | CLK_CTRL_OSC10_PCSM     | CLK_CTRL_OSC10_PCSM     | CLK_CTRL_OSC10_PCSM     | CLK_CTRL_OSC10_PCSM     | CLK_CTRL_OSC10_PCSM     | -                       |
+ * DEBUG_PCSM_STATE_B           | PPU_VPON_PCSM           | PPU_VPON_PCSM           | PPU_VPON_PCSM           | PPU_VPON_PCSM           | PPU_VPON_PCSM           | PPU_VPON_PCSM           | PPU_VPON_PCSM           | PPU_VPON_PCSM           |
+ * DEBUG_PCSM_STATE_C           | CLK_CTRL_OSC10_PON_PCSM | CLK_CTRL_OSC10_PON_PCSM | CLK_CTRL_OSC10_PON_PCSM | CLK_CTRL_XTAL40_PCSM    | CLK_CTRL_XTAL40_PCSM    | CLK_CTRL_XTAL40_PCSM    | CLK_CTRL_XTAL40_PCSM    | -                       |
+ * DEBUG_PCSM_STATE_D           | CLK_CTRL_OSC80_PCSM     | CLK_CTRL_OSC80_PCSM     | CLK_CTRL_OSC80_PCSM     | CLK_CTRL_OSC80_PCSM     | CLK_CTRL_OSC80_CG_PCSM  | CLK_CTRL_OSC80_CG_PCSM  | CLK_CTRL_OSC80_CG_PCSM  | CLK_CTRL_OSC80_CG_PCSM  |
+ * DEBUG_PCSM_STATE_E           | PPU_VCORE_PCSM          | PPU_VCORE_PCSM          | PPU_VCORE_PCSM          | PPU_VCORE_PCSM          | PPU_VCORE_PCSM          | -                       | -                       | -                       |
+ * DEBUG_PCSM_STATE_F           | CLK_CTRL_OSC10_PON_PCSM | CLK_CTRL_OSC10_PON_PCSM | CLK_CTRL_OSC10_PON_PCSM | CLK_CTRL_PLL1_PCSM      | CLK_CTRL_PLL1_PCSM      | CLK_CTRL_PLL1_PCSM      | CLK_CTRL_PLL1_PCSM      | CLK_CTRL_PLL1_PCSM      |
+ * DEBUG_PCSM_STATE_G           | CLK_CTRL_OSC10_PON_PCSM | CLK_CTRL_OSC10_PON_PCSM | CLK_CTRL_OSC10_PON_PCSM | CLK_CTRL_CORE_OP1_PCSM  | CLK_CTRL_CORE_OP1_PCSM  | CLK_CTRL_CORE_OP1_PCSM  | CLK_CTRL_CORE_OP1_PCSM  | CLK_CTRL_CORE_OP1_PCSM  |
+ * DEBUG_C_KOUT0X_SIMO          | AON_DBG_C_KOUT_SIMO_SEL | AON_DBG_C_KOUT_SIMO_SEL | AON_DBG_C_KOUT_SIMO_SEL | AON_DBG_C_KOUT_SIMO_SEL | AON_DBG_C_KOUT_SIMO_SEL | AON_DBG_C_KOUT_SIMO_SEL | AON_DBG_C_KOUT_SIMO_SEL | AON_DBG_C_KOUT_SIMO_SEL |
+ * DEBUG_C_KOUT0X_MBIAS_0_7     | C_KOUT0X_MBIAS [7:0]    | C_KOUT0X_MBIAS [7:0]    | C_KOUT0X_MBIAS [7:0]    | C_KOUT0X_MBIAS [7:0]    | C_KOUT0X_MBIAS [7:0]    | C_KOUT0X_MBIAS [7:0]    | C_KOUT0X_MBIAS [7:0]    | C_KOUT0X_MBIAS [7:0]    |
+ * DEBUG_C_KOUT0X_MBIAS_8_15    | C_KOUT0X_MBIAS [15:8]   | C_KOUT0X_MBIAS [15:8]   | C_KOUT0X_MBIAS [15:8]   | C_KOUT0X_MBIAS [15:8]   | C_KOUT0X_MBIAS [15:8]   | C_KOUT0X_MBIAS [15:8]   | C_KOUT0X_MBIAS [15:8]   | C_KOUT0X_MBIAS [15:8]   |
+ * DEBUG_C_KOUT0X_OSC128K10M    | C_KOUT0X_OSC128K10M [0] | C_KOUT0X_OSC128K10M [1] | OSC_DBG_CLK             | XTAL_CLK_OK             | C_KOUT0X_OSC80M [0]     | -                       | -                       | -                       |
+ * DEBUG_POS_OUTPUT_FLAG        | AON_DBG_C_KOUT_POS_SEL  | AON_DBG_C_KOUT_POS_SEL  | AON_DBG_C_KOUT_POS_SEL  | AON_DBG_C_KOUT_POS_SEL  | AON_DBG_C_KOUT_POS_SEL  | AON_DBG_C_KOUT_POS_SEL  | AON_DBG_C_KOUT_POS_SEL  | AON_DBG_C_KOUT_POS_SEL  |
+ * DEBUG_LPC_OUTPUT_FLAG        | LPC_DEB_SEL             | LPC_DEB_SEL             | LPC_DEB_SEL             | LPC_DEB_SEL             | LPC_DEB_SEL             | LPC_DEB_SEL             | LPC_DEB_SEL             | LPC_DEB_SEL             |
+ * DEBUG_SCH_PLAN_OUTPUT_FLAG   | AON_DBG_SCH_PLAN_SEL    | AON_DBG_SCH_PLAN_SEL    | AON_DBG_SCH_PLAN_SEL    | AON_DBG_SCH_PLAN_SEL    | AON_DBG_SCH_PLAN_SEL    | AON_DBG_SCH_PLAN_SEL    | AON_DBG_SCH_PLAN_SEL    | AON_DBG_SCH_PLAN_SEL    |
+ * DEBUG_POS_PCK600_OUTPUT_FLAG | AON_DBG_PCK600_SEL      | AON_DBG_PCK600_SEL      | AON_DBG_PCK600_SEL      | AON_DBG_PCK600_SEL      | AON_DBG_PCK600_SEL      | AON_DBG_PCK600_SEL      | AON_DBG_PCK600_SEL      | AON_DBG_PCK600_SEL      |
+ * DEBUG_PMU_WDT_OUTPUT_FLAG    | SIMO_WDT_REST_FLAG      | ENLDO_FLAG              | ENSIMO_FLAG_OUTPUT      | -                       | -                       | -                       | -                       | -                       |
+ * ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
+typedef enum
+{
+    DEBUG_PCSM_STATE_A                       = ((0 << 7)),
+    DEBUG_PCSM_STATE_B                       = ((1 << 7)),
+    DEBUG_PCSM_STATE_C                       = ((2 << 7)),
+    DEBUG_PCSM_STATE_D                       = ((3 << 7)),
+    DEBUG_PCSM_STATE_E                       = ((4 << 7)),
+    DEBUG_PCSM_STATE_F                       = ((5 << 7)),
+    DEBUG_PCSM_STATE_G                       = ((6 << 7)),
+    DEBUG_C_KOUT0X_SIMO_0_7                  = ((7 << 7) | 0),
+    DEBUG_C_KOUT0X_SIMO_8_15                 = ((7 << 7) | 1),
+    DEBUG_C_KOUT1X_SIMO_0_7                  = ((7 << 7) | 2),
+    DEBUG_C_KOUT1X_SIMO_8_15                 = ((7 << 7) | 3),
+    DEBUG_C_KOUT2X_SIMO_0_7                  = ((7 << 7) | 4),
+    DEBUG_C_KOUT2X_SIMO_8_15                 = ((7 << 7) | 5),
+    DEBUG_C_KOUT3X_SIMO_0_7                  = ((7 << 7) | 6),
+    DEBUG_C_KOUT3X_SIMO_8_15                 = ((7 << 7) | 7),
+    DEBUG_C_KOUT4X_SIMO_0_7                  = ((7 << 7) | 8),
+    DEBUG_C_KOUT4X_SIMO_8_15                 = ((7 << 7) | 9),
+    DEBUG_C_KOUT5X_SIMO_0_7                  = ((7 << 7) | 10),
+    DEBUG_C_KOUT5X_SIMO_8_15                 = ((7 << 7) | 11),
+    DEBUG_C_KOUT0X_MBIAS_0_7                 = ((8 << 7)),
+    DEBUG_C_KOUT0X_MBIAS_8_15                = ((9 << 7)),
+    DEBUG_C_KOUT0X_OSC128K10M                = ((10 << 7)),
+    DEBUG_POS_OUTPUT_TO_BUCK_BOOST_HV18      = ((11 << 7) | 0),
+    DEBUG_POS_OUTPUT_TO_BUCK_BOOST_VDDPA     = ((11 << 7) | 1),
+    DEBUG_POS_OUTPUT_TO_LDO_ANA              = ((11 << 7) | 2),
+    DEBUG_POS_OUTPUT_TO_LDO_PA               = ((11 << 7) | 3),
+    DEBUG_LPC_OUTPUT_TO_GROUP1               = ((12 << 7) | 0),
+    DEBUG_LPC_OUTPUT_TO_GROUP2               = ((12 << 7) | 1),
+    DEBUG_SCHPLAN_OUTPUT_TO_CM33_CLOCK       = ((13 << 7) | 0),
+    DEBUG_SCHPLAN_OUTPUT_TO_CM33_POWER       = ((13 << 7) | 1),
+    DEBUG_SCHPLAN_OUTPUT_TO_BZ_CLOCK         = ((13 << 7) | 2),
+    DEBUG_SCHPLAN_OUTPUT_TO_BZ_POWER         = ((13 << 7) | 3),
+    DEBUG_SCHPLAN_OUTPUT_TO_DEBUG_GROUP      = ((13 << 7) | 4),
+    DEBUG_PCK600_OUTPUT_TO_VPON_PPU          = ((14 << 7) | 0),
+    DEBUG_PCK600_OUTPUT_TO_VCORE_PPU         = ((14 << 7) | 1),
+    DEBUG_PCK600_OUTPUT_TO_WAKEUP_REASON     = ((14 << 7) | 2),
+    DEBUG_PCK600_OUTPUT_TO_CLOCK_CTRL_LVL321 = ((14 << 7) | 3),
+    DEBUG_PCK600_OUTPUT_TO_CLOCK_CTRL_LVL0   = ((14 << 7) | 4),
+    DEBUG_PMU_WDT_OUTPUT                     = ((15 << 7)),
+} AON_DEBUG_PORT;
+
+#ifdef  __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* RTL_DEBUG_PORT_DEF_H */
diff --git a/bee/drivers/debug/src/device/rtl87x2j/debug_port_def_release.h b/bee/drivers/debug/src/device/rtl87x2j/debug_port_def_release.h
new file mode 100644
index 00000000..0af1667d
--- /dev/null
+++ b/bee/drivers/debug/src/device/rtl87x2j/debug_port_def_release.h
@@ -0,0 +1,160 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: LicenseRef-Realtek-5-Clause
+ */
+
+#ifndef RTL_DEBUG_PORT_DEF_H
+#define RTL_DEBUG_PORT_DEF_H
+
+#ifdef  __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/*============================================================================*
+ *                        Header Files
+ *============================================================================*/
+#include "utils/rtl_utils.h"
+#include "pcc_reg.h"
+
+/*============================================================================*
+ *                          Debug Port Defines
+ *============================================================================*/
+#define DEBUG_PORT_SUPPORT_MULTI_PLATFORM            (0)
+#define DEBUG_PORT_SUPPORT_QACTIVE_STATUS            (1)
+#define DEBUG_PORT_SUPPORT_AON_DEBUG                 (1)
+
+/*============================================================================*
+ *                          Debug Port TYPE
+ *============================================================================*/
+typedef enum
+{
+    PCK600_QACTIVE_CORE_DBG_TYPE = 0,
+    PCK600_QACTIVE_CORE_LPDQ_OSC_QREQ,
+    PCK600_QACTIVE_CORE_LPDQ_OSC_QACCEPT,
+    PCK600_QACTIVE_CORE_LPDQ_OSC_QACTIVE_1,
+    PCK600_QACTIVE_CORE_LPDQ_OSC_CG,
+    PCK600_QACTIVE_CORE_LPDQ_PLL1_1,
+    PCK600_QACTIVE_CORE_LPDQ_SDM_QREQ,
+    PCK600_QACTIVE_CORE_LPDQ_SDM_QACCEPT,
+    PCK600_QACTIVE_CORE_LPDQ_SDM_QACTIVE,
+    PCK600_QACTIVE_CORE_LPDQ_XTAL_QREQ,
+    PCK600_QACTIVE_CORE_LPDQ_XTAL_QACCEPT,
+    PCK600_QACTIVE_CORE_LPDQ_XTAL_QACTIVE_1,
+    PCK600_QACTIVE_CORE_LPDQ_XTAL_1,
+    PCK600_QACTIVE_CORE_LPDQ_PLATFORM,
+    PCK600_QACTIVE_CORE_LPDQ_PLATFORM_QACTIVE,
+    PCK600_QACTIVE_CORE_LPDQ_OSC1,
+    PCK600_QACTIVE_CORE_LPDQ_VCORE_QREQ,
+    PCK600_QACTIVE_CORE_LPDQ_VCORE_QACCEPT,
+    PCK600_QACTIVE_CORE_LPDQ_VCORE_QACTIVE_1,
+    PCK600_QACTIVE_CORE_LPDQ_VCORE_1_QREQ,
+    PCK600_QACTIVE_CORE_LPDQ_VCORE_1_QACCEPT,
+    PCK600_QACTIVE_CORE_LPDQ_VCORE_1_QACTIVE,
+    PCK600_QACTIVE_CORE_DEVICE2,
+    PCK600_QACTIVE_CORE_DEVICE3,
+    PCK600_QACTIVE_CORE_DEVICE4,
+    PCK600_QACTIVE_CORE_DEVICE5,
+    PCK600_QACTIVE_CORE_DEVICE6,
+    PCK600_QACTIVE_CORE_DEVICE7,
+    PCK600_QACTIVE_CORE_DEVICE_GROUP,
+    PCK600_QACTIVE_CORE_DEVICE_POW,
+    PCK600_QACTIVE_CORE_LPDQ_OSC,
+    PCK600_QACTIVE_CORE_LPDQ_OSC10M,
+    PCK600_QACTIVE_CORE_LPDQ_XTAL,
+    PCK600_QACTIVE_CORE_DEVICE1,
+    PCK600_QACTIVE_CORE_DEVICE0,
+    PCK600_QACTIVE_CORE_LPCQ_BT,
+    PCK600_QACTIVE_CORE_LPCQ_PLATFORM,
+    PCK600_QACTIVE_CORE_CLKCTRL_PPU_VCORE,
+
+    PCK600_QACTIVE_PON_DBG_TYPE = 0x100,
+    PCK600_QACTIVE_PON_PPU_VCORE,
+    PCK600_QACTIVE_PON_CLK_SOURCE,
+    PCK600_QACTIVE_PON_VPON_DEVICE,
+    PCK600_QACTIVE_PON_VPON_SCH_PLAN,
+    PCK600_QACTIVE_PON_PPU_VCORE_PCSM,
+    PCK600_QACTIVE_PON_LPDQ_PPU_VCORE,
+    PCK600_QACTIVE_PON_LPDQ_OSC128K_VPON,
+    PCK600_QACTIVE_PON_LPDQ_OSC10M_VPON,
+    PCK600_QACTIVE_PON_LPDQ_OSC10M_VPON_QACTIVE,
+    PCK600_QACTIVE_PON_LPDQ_OSC10M_VPON_HV,
+    PCK600_QACTIVE_PON_LPCQ_PLATFORM,
+    PCK600_QACTIVE_PON_CLKCTRL_PPU_VCORE,
+
+    PCK600_QACTIVE_AON_DBG_TYPE = 0x1000,
+    PCK600_QACTIVE_AON_PPU_VPON,
+    PCK600_QACTIVE_AON_PPU_VPON_PCSM,
+    PCK600_QACTIVE_AON_PPU_VPON_QACTIVE,
+    PCK600_QACTIVE_AON_LPDQ_VPON,
+    PCK600_QACTIVE_AON_LPDQ_VPON_QACTIVE_2,
+    PCK600_QACTIVE_AON_LPDQ_VPON_QACTIVE_1,
+    PCK600_QACTIVE_AON_LPDQ_VPON_QACTIVE_0,
+    PCK600_QACTIVE_AON_LPDQ_OSC10M,
+    PCK600_QACTIVE_AON_P2Q_OPMODE,
+    PCK600_QACTIVE_AON_P2Q_MEMOFF,
+    PCK600_QACTIVE_AON_P2Q_ON,
+    PCK600_QACTIVE_AON_CLK_SOURCE_VAON
+} PCK600_QACTIVE_GROUP_T;
+
+typedef enum
+{
+    PCK600_QACTIVE_I2S        = 0,
+    PCK600_QACTIVE_ADC        = 1,
+    PCK600_QACTIVE_UART3      = 2,
+    PCK600_QACTIVE_UART2      = 3,
+    PCK600_QACTIVE_UART1      = 4,
+    PCK600_QACTIVE_UART0      = 5,
+    PCK600_QACTIVE_TMETER     = 6,
+    PCK600_QACTIVE_TIMER1_CH8 = 7,
+    PCK600_QACTIVE_TIMER1_CH7 = 8,
+    PCK600_QACTIVE_TIMER1_CH6 = 9,
+    PCK600_QACTIVE_TIMER1_CH5 = 10,
+    PCK600_QACTIVE_TIMER1_CH4 = 11,
+    PCK600_QACTIVE_TIMER1_CH3 = 12,
+    PCK600_QACTIVE_TIMER1_CH2 = 13,
+    PCK600_QACTIVE_TIMER1_CH1 = 14,
+    PCK600_QACTIVE_TIMER1_CH0 = 15,
+    PCK600_QACTIVE_TIMER0_CH1 = 16,
+    PCK600_QACTIVE_TIMER0_CH0 = 17,
+    PCK600_QACTIVE_SPI3W      = 18,
+    PCK600_QACTIVE_SPI2       = 19,
+    PCK600_QACTIVE_SPI1       = 20,
+    PCK600_QACTIVE_SPI0       = 21,
+    PCK600_QACTIVE_KEYSCAN    = 22,
+    PCK600_QACTIVE_IR         = 23,
+    PCK600_QACTIVE_I2C1       = 24,
+    PCK600_QACTIVE_I2C0       = 25,
+    PCK600_QACTIVE_GPIO       = 26,
+    PCK600_QACTIVE_DMA        = 27,
+    PCK600_QACTIVE_TIMER2_CH0 = 28,
+    PCK600_QACTIVE_CAN        = 29,
+    PCK600_QACTIVE_USB        = 30,
+
+    PCK600_QACTIVE_RFC        = 31,
+    PCK600_QACTIVE_PRO24G     = 32,
+    PCK600_QACTIVE_PCC        = 33,
+    PCK600_QACTIVE_MODEM      = 34,
+    PCK600_QACTIVE_CAL80M     = 35,
+    PCK600_QACTIVE_CAL32K     = 36,
+    PCK600_QACTIVE_CAL10M     = 37,
+    PCK600_QACTIVE_BTMAC      = 38,
+    PCK600_QACTIVE_BT_VEN     = 39,
+    PCK600_QACTIVE_AUDIO      = 40,
+    PCK600_QACTIVE_AACK       = 41,
+    PCK600_QACTIVE_AES        = 42,
+    PCK600_QACTIVE_SHA256     = 43,
+    PCK600_QACTIVE_CPU        = 44,
+    PCK600_QACTIVE_SPIC0      = 45,
+    PCK600_QACTIVE_RNG        = 46,
+    PCK600_QACTIVE_VDREG      = 47,
+
+    PCK600_QACTIVE_DEVICE_MAX,
+
+} PCK600_QACTIVE_DEVICE_T;
+
+#ifdef  __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* RTL_DEBUG_PORT_DEF_H */
diff --git a/bee/drivers/debug/src/device/rtl87x2j/debug_port_release.h b/bee/drivers/debug/src/device/rtl87x2j/debug_port_release.h
new file mode 100644
index 00000000..47e51a73
--- /dev/null
+++ b/bee/drivers/debug/src/device/rtl87x2j/debug_port_release.h
@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: LicenseRef-Realtek-5-Clause
+ */
+
+/*============================================================================*
+ *                        Define to prevent recursive inclusion
+ *============================================================================*/
+#ifndef DEBUG_PORT_H
+#define DEBUG_PORT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*============================================================================*
+ *                        Header Files
+ *============================================================================*/
+#include "utils/rtl_utils.h"
+#if defined (CONFIG_SOC_SERIES_RTL87X3J)
+#include "debug/src/device/rtl87x3j/debug_port_def.h"
+#elif defined (CONFIG_SOC_SERIES_RTL87X2J)
+#include "debug/src/device/rtl87x2j/debug_port_def.h"
+#endif
+
+/*============================================================================*
+ *                        Constants
+ *============================================================================*/
+typedef enum
+{
+    PCK600_QACTIVE_IDLE = 0,
+    PCK600_QACTIVE_ACTIVE = 1,
+    PCK600_QACTIVE_ERROR = 2,
+} PCK600_QACTIVE_STATUS_T;
+
+/*============================================================================*
+ *                         Functions
+ *============================================================================*/
+
+uint64_t debug_port_pck600_qactive_get_device_mask(void);
+
+PCK600_QACTIVE_STATUS_T debug_port_pck600_qactive_get_device_status(PCK600_QACTIVE_DEVICE_T device);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _DEBUG_PORT_H_ */
diff --git a/bee/drivers/debug/src/device/rtl87x2j/pck600_snapshot_def.h b/bee/drivers/debug/src/device/rtl87x2j/pck600_snapshot_def.h
new file mode 100644
index 00000000..ef7634bd
--- /dev/null
+++ b/bee/drivers/debug/src/device/rtl87x2j/pck600_snapshot_def.h
@@ -0,0 +1,84 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: LicenseRef-Realtek-5-Clause
+ */
+
+#ifndef PCK600_SNAPSHOT_DEF_H
+#define PCK600_SNAPSHOT_DEF_H
+
+#ifdef  __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/*============================================================================*
+ *                        Header Files
+ *============================================================================*/
+#include "utils/rtl_utils.h"
+#include "pcc_reg.h"
+
+/*============================================================================*
+ *                        PCK600 SNAPSHOT TYPE
+ *============================================================================*/
+
+typedef enum
+{
+    PCK600_SNAPSHOT_I2S        = 0,
+    PCK600_SNAPSHOT_ADC        = 1,
+    PCK600_SNAPSHOT_UART3      = 2,
+    PCK600_SNAPSHOT_UART2      = 3,
+    PCK600_SNAPSHOT_UART1      = 4,
+    PCK600_SNAPSHOT_UART0      = 5,
+    PCK600_SNAPSHOT_TMETER     = 6,
+    PCK600_SNAPSHOT_TIMER1_CH8 = 7,
+    PCK600_SNAPSHOT_TIMER1_CH7 = 8,
+    PCK600_SNAPSHOT_TIMER1_CH6 = 9,
+    PCK600_SNAPSHOT_TIMER1_CH5 = 10,
+    PCK600_SNAPSHOT_TIMER1_CH4 = 11,
+    PCK600_SNAPSHOT_TIMER1_CH3 = 12,
+    PCK600_SNAPSHOT_TIMER1_CH2 = 13,
+    PCK600_SNAPSHOT_TIMER1_CH1 = 14,
+    PCK600_SNAPSHOT_TIMER1_CH0 = 15,
+    PCK600_SNAPSHOT_TIMER0_CH1 = 16,
+    PCK600_SNAPSHOT_TIMER0_CH0 = 17,
+    PCK600_SNAPSHOT_SPI3W      = 18,
+    PCK600_SNAPSHOT_SPI2       = 19,
+    PCK600_SNAPSHOT_SPI1       = 20,
+    PCK600_SNAPSHOT_SPI0       = 21,
+    PCK600_SNAPSHOT_KEYSCAN    = 22,
+    PCK600_SNAPSHOT_IR         = 23,
+    PCK600_SNAPSHOT_I2C1       = 24,
+    PCK600_SNAPSHOT_I2C0       = 25,
+    PCK600_SNAPSHOT_GPIO       = 26,
+    PCK600_SNAPSHOT_DMA        = 27,
+    PCK600_SNAPSHOT_TIMER2_CH0 = 28,
+    PCK600_SNAPSHOT_CAN        = 29,
+    PCK600_SNAPSHOT_USB        = 30,
+
+    PCK600_SNAPSHOT_RFC        = 31,
+    PCK600_SNAPSHOT_PRO24G     = 32,
+    PCK600_SNAPSHOT_PCC        = 33,
+    PCK600_SNAPSHOT_MODEM      = 34,
+    PCK600_SNAPSHOT_CAL80M     = 35,
+    PCK600_SNAPSHOT_CAL32K     = 36,
+    PCK600_SNAPSHOT_CAL10M     = 37,
+    PCK600_SNAPSHOT_BTMAC      = 38,
+    PCK600_SNAPSHOT_BT_VEN     = 39,
+    PCK600_SNAPSHOT_AUDIO      = 40,
+    PCK600_SNAPSHOT_AACK       = 41,
+    PCK600_SNAPSHOT_AES        = 42,
+    PCK600_SNAPSHOT_SHA256     = 43,
+    PCK600_SNAPSHOT_CPU        = 44,
+    PCK600_SNAPSHOT_SPIC0      = 45,
+    PCK600_SNAPSHOT_RNG        = 46,
+    PCK600_SNAPSHOT_VDREG      = 47,
+
+    PCK600_SNAPSHOT_DEVICE_MAX,
+
+} PCK600_SNAPSHOT_DEVICE_T;
+
+#ifdef  __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* PCK600_SNAPSHOT_DEF_H */
diff --git a/bee/drivers/dma/CMakeLists.txt b/bee/drivers/dma/CMakeLists.txt
new file mode 100644
index 00000000..fc320b2c
--- /dev/null
+++ b/bee/drivers/dma/CMakeLists.txt
@@ -0,0 +1,8 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+if(CONFIG_REALTEK_BEE_COMMON_DRIVER)
+    zephyr_include_directories(inc)
+endif()
+
+add_subdirectory_ifdef(CONFIG_REALTEK_BEE_DMA src)
diff --git a/bee/drivers/dma/Kconfig b/bee/drivers/dma/Kconfig
new file mode 100644
index 00000000..49101bbc
--- /dev/null
+++ b/bee/drivers/dma/Kconfig
@@ -0,0 +1,8 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config REALTEK_BEE_DMA
+	bool "Realtek Bee DMA driver"
+	default n
+	help
+	  This option enables the DMA driver for Realtek Bee.
diff --git a/bee/drivers/dma/inc/rtl_dma.h b/bee/drivers/dma/inc/rtl_dma.h
new file mode 100644
index 00000000..8f0f73a7
--- /dev/null
+++ b/bee/drivers/dma/inc/rtl_dma.h
@@ -0,0 +1,1195 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *               Define to prevent recursive inclusion
+ *============================================================================*/
+#ifndef RTL_DMA_H
+#define RTL_DMA_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*============================================================================*
+ *                        Header Files
+ *============================================================================*/
+#include "utils/rtl_utils.h"
+#if defined (CONFIG_SOC_SERIES_RTL87X2G)
+#include "dma/src/device/rtl87x2g/rtl_dma_def.h"
+#elif defined (CONFIG_SOC_SERIES_RTL87X3E)
+#include "dma/src/device/rtl87x3e/rtl_dma_def.h"
+#elif defined (CONFIG_SOC_SERIES_RTL87X3D)
+#include "dma/src/device/rtl87x3d/rtl_dma_def.h"
+#elif defined (CONFIG_SOC_SERIES_RTL87X2J)
+#include "dma/src/device/rtl87x2j/rtl_dma_def.h"
+#elif defined (CONFIG_SOC_SERIES_RTL87X3EU)
+#include "dma/src/device/rtl87x3eu/rtl_dma_def.h"
+#elif defined (CONFIG_SOC_SERIES_RTL87X3J)
+#include "dma/src/device/rtl87x3j/rtl_dma_def.h"
+#endif
+
+/** \defgroup DMA        DMA
+  * \brief
+  * \{
+  */
+
+/*============================================================================*
+ *                         Constants
+ *============================================================================*/
+/** \defgroup DMA_Exported_Constants DMA Exported Constants
+  * \brief
+  * \{
+  */
+
+/**
+ * \defgroup    DMA_CHANNEL_NUM DMA CHANNEL NUM
+ * \{
+ * \ingroup     DMA_Exported_Constants
+ */
+
+#define DMA_CH_NUM0             (0)
+#define DMA_CH_NUM1             (1)
+#define DMA_CH_NUM2             (2)
+#define DMA_CH_NUM3             (3)
+#define DMA_CH_NUM4             (4)
+#define DMA_CH_NUM5             (5)
+#if (CHIP_DMA_CHANNEL_NUM >= 9)
+#define DMA_CH_NUM6             (6)
+#define DMA_CH_NUM7             (7)
+#define DMA_CH_NUM8             (8)
+#endif
+#if (CHIP_DMA_CHANNEL_NUM >= 10)
+#define DMA_CH_NUM9             (9)
+#endif
+#if (CHIP_DMA_CHANNEL_NUM >= 12)
+#define DMA_CH_NUM10            (10)
+#define DMA_CH_NUM11            (11)
+#endif
+#if (CHIP_DMA_CHANNEL_NUM >= 16)
+#define DMA_CH_NUM12            (12)
+#define DMA_CH_NUM13            (13)
+#define DMA_CH_NUM14            (14)
+#define DMA_CH_NUM15            (15)
+#endif
+#if (CHIP_DMA_CHANNEL_NUM >= 24)
+#define DMA_CH_NUM16            (16)
+#define DMA_CH_NUM17            (17)
+#define DMA_CH_NUM18            (18)
+#define DMA_CH_NUM19            (19)
+#define DMA_CH_NUM20            (20)
+#define DMA_CH_NUM21            (21)
+#define DMA_CH_NUM22            (22)
+#define DMA_CH_NUM23            (23)
+#endif
+#if (CHIP_DMA_CHANNEL_NUM >= 27)
+#define DMA_CH_NUM24            (24)
+#define DMA_CH_NUM25            (25)
+#define DMA_CH_NUM26            (26)
+#endif
+#if (CHIP_DMA_CHANNEL_NUM >= 33)
+#define DMA_CH_NUM27            (27)
+#define DMA_CH_NUM28            (28)
+#define DMA_CH_NUM29            (29)
+#define DMA_CH_NUM30            (30)
+#define DMA_CH_NUM31            (31)
+#define DMA_CH_NUM32            (32)
+#endif
+
+#define IS_DMA_ChannelNum(NUM)  ((NUM) < CHIP_DMA_CHANNEL_NUM)
+
+/** End of DMA_Define
+  * \}
+  */
+
+/**
+ * \defgroup   DMA_Data_Transfer_Direction DMA Data Transfer Direction
+ * \{
+ * \ingroup    DMA_Exported_Constants
+ */
+
+typedef enum
+{
+    DMA_DIR_MEMORY_TO_MEMORY = 0x0,
+    DMA_DIR_MEMORY_TO_PERIPHERAL = 0x1,
+    DMA_DIR_PERIPHERAL_TO_MEMORY = 0x2,
+    DMA_DIR_PERIPHERAL_TO_PERIPHERAL = 0x3,
+#if (DMA_SUPPORT_PERIPHERAL_FLOW_CONTROL == 1)
+    DMA_DIR_PERIPHERAL_TO_MEMORY_FLOW_CTRL = 0x4,
+    DMA_DIR_MEMORY_TO_PERIPHERAL_FLOW_CTRL = 0x6,
+#endif
+} DMADirection_TypeDef;
+
+#define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_MEMORY_TO_MEMORY) || \
+                         ((DIR) == DMA_DIR_MEMORY_TO_PERIPHERAL) || \
+                         ((DIR) == DMA_DIR_PERIPHERAL_TO_MEMORY) || \
+                         ((DIR) == DMA_DIR_PERIPHERAL_TO_PERIPHERAL) || \
+                         ((DIR) == DMA_DIR_PERIPHERAL_TO_MEMORY_FLOW_CTRL) || \
+                         ((DIR) == DMA_DIR_MEMORY_TO_PERIPHERAL_FLOW_CTRL))
+
+/** End of DMA_Data_Transfer_Direction
+  * \}
+  */
+
+/**
+ * \defgroup    DMA_Source_Mode DMA Source Mode
+ * \{
+ * \ingroup     DMA_Exported_Constants
+ */
+typedef enum
+{
+    DMA_SOURCE_INC = 0x0,
+#if (DMA_SUPPORT_ADDRESS_DECREASE == 1)
+    DMA_SOURCE_DEC = 0x1,
+#endif
+    DMA_SOURCE_FIX = 0x2,
+} DMASrcMode_TypeDef;
+
+#define IS_DMA_SOURCE_MODE(MODE) (((MODE) == DMA_SOURCE_INC) || \
+                                  ((MODE) == DMA_SOURCE_DEC) || \
+                                  ((MODE) == DMA_SOURCE_FIX))
+
+/** End of DMA_Source_Mode
+  * \}
+  */
+
+/**
+ * \defgroup    DMA_Destination_Mode DMA Destination Mode
+ * \{
+ * \ingroup     DMA_Exported_Constants
+ */
+typedef enum
+{
+    DMA_DESTINATION_INC = 0x0,
+#if (DMA_SUPPORT_ADDRESS_DECREASE == 1)
+    DMA_DESTINATION_DEC = 0x1,
+#endif
+    DMA_DESTINATION_FIX = 0x2,
+} DMADestMode_TypeDef;
+
+#define IS_DMA_DESTINATION_MODE(MODE) (((MODE) == DMA_DESTINATION_INC) || \
+                                       ((MODE) == DMA_DESTINATION_DEC) || \
+                                       ((MODE) == DMA_DESTINATION_FIX))
+
+/** End of DMA_Destination_Mode
+  * \}
+  */
+
+/**
+ * \defgroup    DMA_Data_Size DMA Data Size
+ * \{
+ * \ingroup     DMA_Exported_Constants
+ */
+typedef enum
+{
+    DMA_DATA_SIZE_BYTE           = 0x0,
+    DMA_DATA_SIZE_HALFWORD       = 0x1,
+    DMA_DATA_SIZE_WORD           = 0x2,
+#if (DMA_SUPPORT_DATA_SIZE_DOUBLE_WORD == 1)
+    DMA_DATA_SIZE_DOUBLEWORD     = 0x3,
+#endif
+    DMA_DATA_SIZE_MAX,
+} DMADataSize_TypeDef;
+
+#define IS_DMA_DATA_SIZE(SIZE) ((SIZE) < DMA_DATA_SIZE_MAX)
+
+/** End of DMA_Data_Size
+  * \}
+  */
+
+/**
+ * \defgroup    DMA_Msize DMA Msize
+ * \{
+ * \ingroup     DMA_Exported_Constants
+ */
+
+typedef enum
+{
+    DMA_MSIZE_1   = 0x0,
+    DMA_MSIZE_4   = 0x1,
+    DMA_MSIZE_8   = 0x2,
+    DMA_MSIZE_16  = 0x3,
+    DMA_MSIZE_32  = 0x4,
+#if (DMA_SUPPORT_MSIZE_64 == 1)
+    DMA_MSIZE_64  = 0x5,
+#endif
+#if (DMA_SUPPORT_MSIZE_128 == 1)
+    DMA_MSIZE_128 = 0x6,
+#endif
+#if (DMA_SUPPORT_MSIZE_256 == 1)
+    DMA_MSIZE_256 = 0x7,
+#endif
+    DMA_MSIZE_MAX,
+} DMAMSize_TypeDef;
+
+#define IS_DMA_MSIZE(SIZE) ((SIZE) < DMA_MSIZE_MAX)
+
+/** End of DMA_Msize
+  * \}
+  */
+
+#if (DMA_SUPPORT_AUTO_SLOW_CONFIG == 1)
+/**
+ * \defgroup    DMA_AutoSlow DMA Auto Slow
+ * \{
+ * \ingroup     DMA_Exported_Constants
+ */
+
+typedef enum
+{
+    DMA_NOT_ALLOW_AUTO_SLOW_WHEN_ENABLE  = 0x0,
+    DMA_ALLOW_AUTO_SLOW_WHEN_ENABLE = 0x1,
+} DMAAutoSlow_TypeDef;
+
+#define IS_DMA_AUTO_SLOW(MODE) (((MODE) == DMA_NOT_ALLOW_AUTO_SLOW_WHEN_ENABLE) || \
+                                ((MODE) == DMA_ALLOW_AUTO_SLOW_WHEN_ENABLE))
+
+/** End of DMA_AutoSlow
+  * \}
+  */
+#endif
+/**
+ * \defgroup    DMA_Interrupts  DMA Interrupts
+ * \{
+ * \ingroup     DMA_Exported_Constants
+ */
+
+#define DMA_INT_TRANSFER               (BIT0)
+#define DMA_INT_BLOCK                  (BIT1)
+#define DMA_INT_ERROR                  (BIT4)
+#if (DMA_SUPPORT_INT_HAIF_BLOCK == 1)
+#define DMA_INT_HALF_BLOCK             (BIT5)
+#endif
+#if (DMA_SUPPORT_BLOCK_COUNTER == 1)
+#define DMA_INT_BLOCK_COUNTER          (BIT6)
+#endif
+
+#define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFE0) == 0x00) && ((IT) != 0x00))
+
+/** End of DMA_Interrupts
+  * \}
+  */
+
+/**
+ * \defgroup    DMA_Multi-block_Mode DMA Multi-block Mode
+ * \{
+ * \ingroup     DMA_Exported_Constants
+ */
+#define AUTO_RELOAD_WITH_CONTIGUOUS_SAR (BIT31)
+#define AUTO_RELOAD_WITH_CONTIGUOUS_DAR (BIT30)
+#define AUTO_RELOAD_TRANSFER            (BIT30 | BIT31)
+#define LLI_WITH_CONTIGUOUS_SAR         (BIT27)
+#define LLI_WITH_AUTO_RELOAD_SAR        (BIT27 | BIT30)
+#define LLI_WITH_CONTIGUOUS_DAR         (BIT28)
+#define LLI_WITH_AUTO_RELOAD_DAR        (BIT28 | BIT31)
+#define LLI_TRANSFER                    (BIT27 | BIT28)
+
+#define IS_DMA_MULTIBLOCKMODE(MODE) (((MODE) == AUTO_RELOAD_WITH_CONTIGUOUS_SAR) || \
+                                     ((MODE) == AUTO_RELOAD_WITH_CONTIGUOUS_DAR) || \
+                                     ((MODE) == AUTO_RELOAD_TRANSFER) || \
+                                     ((MODE) == LLI_WITH_CONTIGUOUS_SAR) || \
+                                     ((MODE) == LLI_WITH_AUTO_RELOAD_SAR) || \
+                                     ((MODE) == LLI_WITH_CONTIGUOUS_DAR) || \
+                                     ((MODE) == LLI_WITH_AUTO_RELOAD_DAR) || \
+                                     ((MODE) == LLI_TRANSFER))
+
+/** End of DMA_Multi-block_Mode
+  * \}
+  */
+
+/**
+ * \defgroup    DMA_Multi-Block_Select_Bit DMA Multi-Block Select Bit
+ * \{
+ * \ingroup     DMA_Exported_Constants
+ */
+#define AUTO_RELOAD_SELECTED_BIT        (BIT30 | BIT31)
+#define LLP_SELECTED_BIT                (BIT27 | BIT28)
+
+/** End of DMA_Multi-Block_Select_Bit
+  * \}
+  */
+
+/** End of DMA_Exported_Constants
+  * \}
+  */
+
+/*============================================================================*
+ *                         Types
+ *============================================================================*/
+/** \defgroup DMA_Exported_Types DMA Exported Types
+  * \brief
+  * \{
+  */
+
+/**
+ * \brief       DMA init structure definition.
+ *
+ * \ingroup     DMA_Exported_Types
+ */
+
+typedef struct
+{
+    uint8_t DMA_ChannelNum;               /*!< Specifies channel number for DMA. */
+
+    DMADirection_TypeDef DMA_Direction;   /*!< Specifies transfer direction. */
+
+    uint32_t DMA_BufferSize;              /*!< Specifies the buffer size(RTL8762G <= 65535, RTL8772F: DMA1 is 65535 and DMA2 is 524287).
+                                               The data unit is equal to the configuration set in DMA_PeripheralDataSize
+                                               or DMA_MemoryDataSize members depending in the transfer direction. */
+
+    DMASrcMode_TypeDef DMA_SourceInc;     /*!< Specifies whether the source address
+                                               register is incremented or not. */
+
+    DMADestMode_TypeDef DMA_DestinationInc; /*!< Specifies whether the destination address
+                                                 register is incremented or not.*/
+
+    DMADataSize_TypeDef DMA_SourceDataSize; /*!< Specifies the source data width. */
+
+    DMADataSize_TypeDef DMA_DestinationDataSize; /*!< Specifies the destination data width. */
+
+    DMAMSize_TypeDef DMA_SourceMsize;     /*!< Specifies items number to be transferred. */
+
+    DMAMSize_TypeDef DMA_DestinationMsize;/*!< Specifies items number to be transferred. */
+
+    uint32_t DMA_SourceAddr;              /*!< Specifies the source base address for DMA Channelx. */
+
+    uint32_t DMA_DestinationAddr;         /*!< Specifies the destination base address for DMA Channelx. */
+
+    uint32_t DMA_ChannelPriority;         /*!< Specifies the software priority for the DMA Channelx.
+                                                This parameter can be a value of 0~9(RTL8762G); 0~7 for DMA1 and 0~15 for DMA2(RTL8772F). */
+
+    uint32_t DMA_MultiBlockMode;          /*!< Specifies the multi block transfer mode.
+                                                This parameter can be a value of \ref DMA_Multiblock_Mode. */
+
+    uint32_t DMA_MultiBlockStruct;      /*!< Pointer to the first struct of LLI. */
+
+    uint8_t DMA_MultiBlockEn;           /*!< Enable or disable multi-block function. */
+
+    uint8_t DMA_SourceHandshake;          /*!< Specifies the handshake index in source.
+                                               This parameter can be a value of \ref DMA_Handshake_Type. */
+
+    uint8_t DMA_DestHandshake;            /*!< Specifies the handshake index in Destination.
+                                               This parameter can be a value of \ref DMA_Handshake_Type. */
+
+#if (DMA_SUPPORT_SECURE_MODE == 1)
+    uint8_t DMA_SecureEn;                /*!< Enable or disable Secure function. */
+#endif
+
+#if (DMA_SUPPORT_GATHER_SCATTER_FUNCTION == 1)
+    uint8_t  DMA_GatherEn;               /*!< Enable or disable Gather function. NOTE:4 bytes ALIGN.*/
+    uint32_t DMA_GatherCount;             /*!< Specifies the GatherCount.NOTE:4 bytes ALIGN.*/
+    uint32_t DMA_GatherInterval;          /*!< Specifies the GatherInterval. */
+    uint8_t  DMA_ScatterEn;              /*!< Enable or disable Scatter function. */
+    uint32_t DMA_ScatterCount;            /*!< Specifies the ScatterCount. */
+    uint32_t DMA_ScatterInterval;         /*!< Specifies the ScatterInterval. */
+    uint32_t DMA_GatherCircularStreamingNum;  /*!< Specifies the GatherCircularStreamingNum. */
+    uint32_t DMA_ScatterCircularStreamingNum; /*!< Specifies the ScatterCircularStreamingNum. */
+#endif
+
+#if (DMA_SUPPORT_CONTINUOUS_BLOCK_ADDRESS == 1)
+    FunctionalState DMA_ContSarEn;        /**< Enable or disable DMA continuous source
+                                                address between single block interrupt. */
+
+    FunctionalState DMA_ContDarEn;        /**< Enable or disable DMA continuous destination
+                                                address between single block interrupt. */
+#endif
+
+#if (DMA_SUPPORT_BLOCK_COUNTER == 1)
+    uint32_t DMA_BlockCounter;            /*!< Specifies the block counter.
+                                                After each block transfer is completed, 1 is
+                                                subtracted from the block counter until it reaches
+                                                0, at which point it can no longer be reduced. */
+#endif
+
+} DMA_InitTypeDef;
+
+/**
+ * \brief       DMA link list item structure definition.
+ *
+ * \ingroup     DMA_Exported_Types
+ */
+
+typedef struct
+{
+    __IO uint32_t SAR;
+    __IO uint32_t DAR;
+    __IO uint32_t LLP;
+    __IO uint32_t CTL_LOW;
+    __IO uint32_t CTL_HIGH;
+} DMA_LLIDef;
+
+/** End of DMA_Exported_Types
+  * \}
+  */
+
+/*============================================================================*
+ *                         Functions
+ *============================================================================*/
+/** \defgroup DMA_Exported_Functions DMA Exported Functions
+  * \brief
+  * \{
+  */
+
+/**
+ * \brief     Deinitializes the DMA registers to their default reset
+ *            values.
+ *
+ * \param[in] None.
+ *
+ * \return    None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_dma_init(void)
+ * {
+ *     DMA_DeInit();
+ * }
+ * \endcode
+ */
+void DMA_DeInit(void);
+
+/**
+ * \brief     Initializes the DMA Channelx according to the specified
+ *            parameters in the DMA_InitStruct.
+ * \param[in] DMA_Channelx: Select the DMA peripheral. \ref DMA_Declaration
+ * \param[in] DMA_InitStruct: Pointer to a DMA_InitTypeDef structure that
+ *            contains the configuration information for the specified DMA Channel.
+ * \return    None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_dma_init(void)
+ * {
+ *     for (uint32_t i = 0; i < UART_TX_DMA_BUFFER_SIZE; i++)
+ *     {
+ *         DMA_SendData_Buffer[i] = 0x10 + i;
+ *     }
+ *
+ *     DMA_InitTypeDef DMA_InitStruct;
+ *     DMA_StructInit(&DMA_InitStruct);
+ *     DMA_InitStruct.DMA_ChannelNum      = 1;
+ *     DMA_InitStruct.DMA_Direction       = DMA_DIR_MEMORY_TO_PERIPHERAL;
+ *     DMA_InitStruct.DMA_BufferSize      = UART_TX_DMA_BUFFER_SIZE;//determine total transfer size
+ *     DMA_InitStruct.DMA_SourceInc       = DMA_SOURCEINC_INC;
+ *     DMA_InitStruct.DMA_DestinationInc  = DMA_DESTINATIONINC_FIX;
+ *     DMA_InitStruct.DMA_SourceDataSize  = DMA_DataSize_Byte;
+ *     DMA_InitStruct.DMA_DestinationDataSize = DMA_DataSize_Byte;
+ *     DMA_InitStruct.DMA_SourceMsize      = DMA_Msize_1;
+ *     DMA_InitStruct.DMA_DestinationMsize = DMA_Msize_1;
+ *     DMA_InitStruct.DMA_SourceAddr      = (uint32_t)DMA_SendData_Buffer;
+ *     DMA_InitStruct.DMA_DestinationAddr = (uint32_t)(&(UART0->UART_RBR_THR));
+ *     DMA_InitStruct.DMA_DestHandshake   = DMA0_Handshake_UART0_TX;
+ *     DMA_InitStruct.DMA_ChannelPriority = 2;
+ *     DMA_Init(UART_TX_DMA_CHANNEL, &DMA_InitStruct);
+ *
+ *     DMA_INTConfig(UART_TX_DMA_CHANNEL_NUM, DMA_INT_TRANSFER, ENABLE);
+ *
+ *     NVIC_InitTypeDef NVIC_InitStruct;
+ *     NVIC_InitStruct.NVIC_IRQChannel = UART_TX_DMA_CHANNEL_IRQN;
+ *     NVIC_InitStruct.NVIC_IRQChannelPriority = 3;
+ *     NVIC_InitStruct.NVIC_IRQChannelCmd = ENABLE;
+ *     NVIC_Init(&NVIC_InitStruct);
+ *
+ *     DMA_Cmd(UART_TX_DMA_CHANNEL_NUM, ENABLE);
+ * }
+ * \endcode
+ */
+void DMA_Init(DMA_ChannelTypeDef *DMA_Channelx, DMA_InitTypeDef *DMA_InitStruct);
+
+/**
+ * \brief     Fills each DMA_InitStruct member with its default value.
+ *
+ * \param[in] DMA_InitStruct : pointer to a DMA_InitTypeDef structure which will
+ *            be initialized.
+ *
+ * \return    None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_dma_init(void)
+ * {
+ *
+ *     for (uint32_t i = 0; i < UART_TX_DMA_BUFFER_SIZE; i++)
+ *     {
+ *         DMA_SendData_Buffer[i] = 0x10 + i;
+ *     }
+ *
+ *     DMA_InitTypeDef DMA_InitStruct;
+ *     DMA_StructInit(&DMA_InitStruct);
+ *     DMA_InitStruct.DMA_ChannelNum      = 1;
+ *     DMA_InitStruct.DMA_Direction       = DMA_DIR_MEMORY_TO_PERIPHERAL;
+ *     DMA_InitStruct.DMA_BufferSize      = UART_TX_DMA_BUFFER_SIZE;//determine total transfer size
+ *     DMA_InitStruct.DMA_SourceInc       = DMA_SOURCEINC_INC;
+ *     DMA_InitStruct.DMA_DestinationInc  = DMA_DESTINATIONINC_FIX;
+ *     DMA_InitStruct.DMA_SourceDataSize  = DMA_DataSize_Byte;
+ *     DMA_InitStruct.DMA_DestinationDataSize = DMA_DataSize_Byte;
+ *     DMA_InitStruct.DMA_SourceMsize      = DMA_Msize_1;
+ *     DMA_InitStruct.DMA_DestinationMsize = DMA_Msize_1;
+ *     DMA_InitStruct.DMA_SourceAddr      = (uint32_t)DMA_SendData_Buffer;
+ *     DMA_InitStruct.DMA_DestinationAddr = (uint32_t)(&(UART0->UART_RBR_THR));
+ *     DMA_InitStruct.DMA_DestHandshake   = DMA0_Handshake_UART0_TX;
+ *     DMA_InitStruct.DMA_ChannelPriority = 2;
+ *     DMA_Init(UART_TX_DMA_CHANNEL, &DMA_InitStruct);
+ *
+ * }
+ * \endcode
+ */
+void DMA_StructInit(DMA_InitTypeDef *DMA_InitStruct);
+
+/**
+ * \brief  Enables or disables the selected DMA channel.
+ *
+ * \param[in]  DMA_ChannelNum: Select the DMA channel number. \ref DMA_CHANNEL_NUM
+ * \param[in]  NewState: New state of the selected DMA channel.
+ *             This parameter can be: ENABLE or DISABLE.
+ *
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_dma_init(void)
+ * {
+ *
+ *     for (uint32_t i = 0; i < UART_TX_DMA_BUFFER_SIZE; i++)
+ *     {
+ *         DMA_SendData_Buffer[i] = 0x10 + i;
+ *     }
+ *
+ *     DMA_InitTypeDef DMA_InitStruct;
+ *     DMA_StructInit(&DMA_InitStruct);
+ *     DMA_InitStruct.DMA_ChannelNum      = 1;
+ *     DMA_InitStruct.DMA_Direction       = DMA_DIR_MEMORY_TO_PERIPHERAL;
+ *     DMA_InitStruct.DMA_BufferSize      = UART_TX_DMA_BUFFER_SIZE;//determine total transfer size
+ *     DMA_InitStruct.DMA_SourceInc       = DMA_SOURCEINC_INC;
+ *     DMA_InitStruct.DMA_DestinationInc  = DMA_DESTINATIONINC_FIX;
+ *     DMA_InitStruct.DMA_SourceDataSize  = DMA_DataSize_Byte;
+ *     DMA_InitStruct.DMA_DestinationDataSize = DMA_DataSize_Byte;
+ *     DMA_InitStruct.DMA_SourceMsize      = DMA_Msize_1;
+ *     DMA_InitStruct.DMA_DestinationMsize = DMA_Msize_1;
+ *     DMA_InitStruct.DMA_SourceAddr      = (uint32_t)DMA_SendData_Buffer;
+ *     DMA_InitStruct.DMA_DestinationAddr = (uint32_t)(&(UART0->UART_RBR_THR));
+ *     DMA_InitStruct.DMA_DestHandshake   = DMA0_Handshake_UART0_TX;
+ *     DMA_InitStruct.DMA_ChannelPriority = 2;
+ *     DMA_Init(UART_TX_DMA_CHANNEL, &DMA_InitStruct);
+ *
+ *     DMA_INTConfig(UART_TX_DMA_CHANNEL_NUM, DMA_INT_TRANSFER, ENABLE);
+ *
+ *     NVIC_InitTypeDef NVIC_InitStruct;
+ *     NVIC_InitStruct.NVIC_IRQChannel = UART_TX_DMA_CHANNEL_IRQN;
+ *     NVIC_InitStruct.NVIC_IRQChannelPriority = 3;
+ *     NVIC_InitStruct.NVIC_IRQChannelCmd = ENABLE;
+ *     NVIC_Init(&NVIC_InitStruct);
+ *
+ *     DMA_Cmd(UART_TX_DMA_CHANNEL_NUM, ENABLE);
+ * }
+ * \endcode
+ */
+void DMA_Cmd(uint8_t DMA_ChannelNum, FunctionalState NewState);
+
+/**
+ * \brief   Enables or disables the specified DMA channelx interrupt source.
+ * \param[in] DMA_Channel_Num: can be 0 to 9 to select the DMA Channel(for RTL8762G, 3 to 26 for RTL8772F).
+ * \param[in] DMA_IT: Specifies the DMA interrupt source to be enabled or disabled.
+ *            This parameter can be any combination of the following values:
+ *            \arg DMA_INT_TRANSFER: Transfer complete interrupt source.
+ *            \arg DMA_INT_Block: Block transfer interrupt source.
+ *            \arg DMA_INT_Error: Transfer error interrupt source.
+ *            \arg DMA_INT_Half_Block: Half Block transfer interrupt source.
+ * \param[in] NewState: New state of the specified DMA interrupt source.
+ *            This parameter can be: ENABLE or DISABLE.
+ *
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_dma_init(void)
+ * {
+ *
+ *     for (uint32_t i = 0; i < UART_TX_DMA_BUFFER_SIZE; i++)
+ *     {
+ *         DMA_SendData_Buffer[i] = 0x10 + i;
+ *     }
+ *
+ *     DMA_InitTypeDef DMA_InitStruct;
+ *     DMA_StructInit(&DMA_InitStruct);
+ *     DMA_InitStruct.DMA_ChannelNum      = 1;
+ *     DMA_InitStruct.DMA_Direction       = DMA_DIR_MEMORY_TO_PERIPHERAL;
+ *     DMA_InitStruct.DMA_BufferSize      = UART_TX_DMA_BUFFER_SIZE;//determine total transfer size
+ *     DMA_InitStruct.DMA_SourceInc       = DMA_SOURCEINC_INC;
+ *     DMA_InitStruct.DMA_DestinationInc  = DMA_DESTINATIONINC_FIX;
+ *     DMA_InitStruct.DMA_SourceDataSize  = DMA_DataSize_Byte;
+ *     DMA_InitStruct.DMA_DestinationDataSize = DMA_DataSize_Byte;
+ *     DMA_InitStruct.DMA_SourceMsize      = DMA_Msize_1;
+ *     DMA_InitStruct.DMA_DestinationMsize = DMA_Msize_1;
+ *     DMA_InitStruct.DMA_SourceAddr      = (uint32_t)DMA_SendData_Buffer;
+ *     DMA_InitStruct.DMA_DestinationAddr = (uint32_t)(&(UART0->UART_RBR_THR));
+ *     DMA_InitStruct.DMA_DestHandshake   = DMA0_Handshake_UART0_TX;
+ *     DMA_InitStruct.DMA_ChannelPriority = 2;
+ *     DMA_Init(UART_TX_DMA_CHANNEL, &DMA_InitStruct);
+ *
+ *     DMA_INTConfig(UART_TX_DMA_CHANNEL_NUM, DMA_INT_TRANSFER, ENABLE);
+ *
+ *     NVIC_InitTypeDef NVIC_InitStruct;
+ *     NVIC_InitStruct.NVIC_IRQChannel = UART_TX_DMA_CHANNEL_IRQN;
+ *     NVIC_InitStruct.NVIC_IRQChannelPriority = 3;
+ *     NVIC_InitStruct.NVIC_IRQChannelCmd = ENABLE;
+ *     NVIC_Init(&NVIC_InitStruct);
+ *
+ *     DMA_Cmd(UART_TX_DMA_CHANNEL_NUM, ENABLE);
+ * }
+ * \endcode
+ */
+void DMA_INTConfig(uint8_t DMA_ChannelNum, uint32_t DMA_IT, FunctionalState NewState);
+
+/**
+ * \brief     Check whether DMA Channel transfer interrupt is set.
+ *
+ * \param[in] DMA_Channel_Num: can be 0 to 9 to select the DMA Channel(for RTL8762G, 3 to 26 for RTL8772F).
+ *
+ * \return    Transfer interrupt status, SET or RESET.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void dma_demo(void)
+ * {
+ *     ITStatus int_status = DMA_GetTransferINTStatus(0);
+ * }
+ * \endcode
+ */
+ITStatus DMA_GetTransferINTStatus(uint8_t DMA_ChannelNum);
+
+/**
+  * \brief  Check whether DMA Channel block interrupt is set.
+  * \param  DMA_ChannelNum: Select the DMA channel number. \ref DMA_CHANNEL_NUM.
+  * \param  DMA_IT: specifies the DMA interrupts status to get.
+  *         This parameter can be any combination of the following values:
+  *         \arg DMA_INT_TRANSFER:  Transfer complete interrupt status.
+  *         \arg DMA_INT_BLOCK:  Block transfer interrupt status.
+  *         \arg DMA_INT_ERROR :  Transfer error interrupt status.
+  *         \arg DMA_INT_HALF_BLOCK: Half Block transfer interrupt status.
+  *         \arg DMA_INT_BLOCK_COUNTER: Block counter interrupt status.
+  * \return Block interrupt status, SET or RESET.
+  */
+ITStatus DMA_GetINTStatus(uint8_t DMA_ChannelNum, uint32_t DMA_IT);
+
+/**
+ * \brief  Clear the specified DMA channelx interrupt pending bit.
+ * \param[in] DMA_Channel_Num: can be 0 to 9 to select the DMA Channel(for RTL8762G, 3 to 26 for RTL8772F).
+ * \param[in] DMA_IT: Specifies the DMA interrupts sources to be enabled or disabled.
+ *            This parameter can be any combination of the following values:
+ *            \arg DMA_INT_TRANSFER: Transfer complete interrupt source.
+ *            \arg DMA_INT_Block: Block transfer interrupt source.
+ *            \arg DMA_INT_Error: Transfer error interrupt source.
+ *            \arg DMA_INT_Half_Block: Half Block transfer interrupt source.
+ *
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void dma_demo(void)
+ * {
+ *     driver_dma_init();
+ * }
+ *
+ * void UART_TX_DMA_Handler(void)
+ * {
+ *     DMA_ClearINTPendingBit(1, DMA_INT_TRANSFER);
+ *     //Add user code here.
+ * }
+ * \endcode
+ */
+void DMA_ClearINTPendingBit(uint8_t DMA_ChannelNum, uint32_t DMA_IT);
+
+/**
+ * \brief     Clear DMAx Channelx all type interrupt.
+ *
+ * \param[in]  DMA_ChannelNum: Select the DMA channel number. \ref DMA_CHANNEL_NUM
+ *
+ * \return    None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void dma_demo(void)
+ * {
+ *     DMA_ClearAllTypeINT(DMA2, 0);
+ * }
+ * \endcode
+ */
+void DMA_ClearAllTypeINT(uint8_t DMA_ChannelNum);
+
+/**
+ * \brief   Get selected DMA channel status.
+ *
+ * \param[in] DMA_Channel_Num: can be 0 to 9 to select the DMA Channel(for RTL8762G, 3 to 26 for RTL8772F).
+ *
+ * \return  DMA channel status.
+ * \retval  SET: Channel is be used
+ * \retval  RESET: Channel is free.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void dma_demo(void)
+ * {
+ *     FlagStatus flag_status = DMA_GetChannelStatus(3);
+ * }
+ * \endcode
+ */
+FlagStatus DMA_GetChannelStatus(uint8_t DMA_ChannelNum);
+
+/**
+ * \brief     Check DMA FIFO status.
+ *
+ * \param[in] DMA_Channelx: Select the DMA peripheral. \ref DMA_Declaration
+ *
+ * \return DMA FIFO status.
+ * \retval SET: FIFO empty.
+ * \retval RESET: FIFO not empty.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void dma_demo(void)
+ * {
+ *     FlagStatus flag_status = DMA_GetFIFOStatus(DMA2_Channel0);
+ * }
+ * \endcode
+ */
+FlagStatus DMA_GetFIFOStatus(DMA_ChannelTypeDef *DMA_Channelx);
+
+/**
+ * \brief      Suspend DMA transmission from the source.
+ *
+ * \param[in]  DMA_Channelx: Select the DMA peripheral. \ref DMA_Declaration
+ * \param[in]  NewState: New state of the DMAx Channelx.
+ *             This parameter can be: ENABLE or DISABLE.
+ *
+ * \return     None.
+ * \note       To prevent data loss, it is necessary to check whether FIFO data transmission is completed
+ *             after suspend, and judge by checking whether DMA FIFO is empty.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void dma_demo(void)
+ * {
+ *     DMA_SuspendCmd(DMA2_Channel0, ENABLE);
+ * }
+ * \endcode
+ */
+void DMA_SuspendCmd(DMA_ChannelTypeDef *DMA_Channelx, FunctionalState NewState);
+
+/**
+ * rtl_dma.h
+ *
+ * \brief  Suspend DMA transmission safe from the source. Please check DMA FIFO empty to guarnatee without losing data.
+ *
+ * \param[in] DMA_Channelx: Select the DMA peripheral. \ref DMA_Declaration
+ *
+ * \return The result of suspend DMA transmission.
+ * \retval true: suspend DMA transmission success.
+ * \retval false: suspend DMA transmission failed.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * uint8_t uart_rx_dma_ch_num = 0xa5;
+ * #define UART_RX_DMA_CHANNEL_NUM   uart_rx_dma_ch_num
+ * #define UART_RX_DMA_CHANNEL       DMA_CH_BASE(uart_rx_dma_ch_num)
+ *
+ * void dma_demo(void)
+ * {
+ *     DMA_SafeSuspend(UART_RX_DMA_CHANNEL);
+ *     //Add user code here.
+ * }
+ * \endcode
+ */
+bool DMA_SafeSuspend(DMA_ChannelTypeDef *DMA_Channelx);
+
+/**
+ * \brief      Set DMA transmission source address.
+ *
+ * \param[in] DMA_Channelx: Select the DMA peripheral. \ref DMA_Declaration
+ * \param[in]  Address: Source address.
+ *
+ * \return     None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void dma_demo(void)
+ * {
+ *     uint32_t data_buf[10] = {0};
+ *     DMA_SetSourceAddress(DMA2_Channel0,(uint32_t)data_buf);
+ * }
+ * \endcode
+ */
+void DMA_SetSourceAddress(DMA_ChannelTypeDef *DMA_Channelx, uint32_t Address);
+
+/**
+ * \brief     Set DMA transmission destination address.
+ *
+ * \param[in] DMA_Channelx: Select the DMA peripheral. \ref DMA_Declaration
+ * \param[in] Address: Destination address.
+ *
+ * \return    None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void dma_demo(void)
+ * {
+ *     uint32_t data_buf[10] = {0};
+ *     DMA_SetDestinationAddress(DMA_Channel0,(uint32_t)data_buf);
+ * }
+ * \endcode
+ */
+void DMA_SetDestinationAddress(DMA_ChannelTypeDef *DMA_Channelx,
+                               uint32_t Address);
+
+/**
+ * \brief     Set DMA LLP stucture address.
+ *
+ * \param[in] DMA_Channelx: Select the DMA peripheral. \ref DMA_Declaration
+ * \param[in] Address: LLP stucture address.
+ *
+ * \return    None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void dma_demo(void)
+ * {
+ *     DMA_LLIDef DMA_LLIStruct[4000];
+ *     DMA_SetLLPAddress(DMA2_Channel0,(uint32_t)DMA_LLIStruct);
+ * }
+ * \endcode
+ */
+void DMA_SetLLPAddress(DMA_ChannelTypeDef *DMA_Channelx, uint32_t Address);
+
+/**
+ * \brief     Set DMA buffer size.
+ *
+ * \param[in] DMA_Channelx: Select the DMA peripheral. \ref DMA_Declaration
+ * \param[in] buffer_size: Set DMA_BufferSize, max 65535 for RTL8762G (RTL8772F: DMA1 is 65535 and DMA2 is 524287).
+ *
+ * \return    None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void dma_demo(void)
+ * {
+ *     uint32_t data_buf_size = 4095;
+ *     DMA_SetBufferSize(DMA_Channel0,data_buf_size);
+ * }
+ * \endcode
+ */
+void DMA_SetBufferSize(DMA_ChannelTypeDef *DMA_Channelx, uint32_t buffer_size);
+
+/**
+ * \brief  Get DMA source address.
+ *
+ * \param[in] DMA_Channelx: Select the DMA peripheral. \ref DMA_Declaration
+ *
+ * \return Source address.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void dma_demo(void)
+ * {
+ *     uint32_t address = DMA_GetSrcTransferAddress(DMA2_Channel0);
+ * }
+ * \endcode
+ */
+uint32_t DMA_GetSrcTransferAddress(DMA_ChannelTypeDef *DMA_Channelx);
+
+/**
+ * \brief  Get DMA destination address.
+ *
+ * \param[in] DMA_Channelx: Select the DMA peripheral. \ref DMA_Declaration
+ *
+ * \return Destination address.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void dma_demo(void)
+ * {
+ *     uint32_t address = DMA_GetDstTransferAddress(DMA2_Channel0);
+ * }
+ * \endcode
+ */
+uint32_t DMA_GetDstTransferAddress(DMA_ChannelTypeDef *DMA_Channelx);
+/**
+ * \brief     Get DMA transfer data length.
+ *
+ * \param[in] DMA_Channelx: Select the DMA peripheral. \ref DMA_Declaration
+ *
+ * \return    DMA transfer data length.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void dma_demo(void)
+ * {
+ *     uint16_t data_len = DMA_GetTransferLen(DMA2_Channel0);
+ * }
+ * \endcode
+ */
+uint16_t DMA_GetTransferLen(DMA_ChannelTypeDef *DMA_Channelx);
+
+/**
+ * rtl876x_dma.h
+ *
+ * \brief  Update DMA LLP mode in multi-block.
+ *
+ * \param[in] DMA_Channelx: Select the DMA peripheral. \ref DMA_Declaration
+ * \param[in] DMA LLP mode
+ *
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void dma_demo(void)
+ * {
+ *     DMA_SetLLPMode(LLI_TRANSFER);
+ * }
+ * \endcode
+ */
+void DMA_SetLLPMode(DMA_ChannelTypeDef *DMA_Channelx, uint32_t mode);
+
+/**
+ * \brief     Get DMA Channelx of the specified DMA Channel Number.
+ *
+ * \param[in]  DMA_ChannelNum: Select the DMA channel number. \ref DMA_CHANNEL_NUM
+ *
+ * \return    DMA_Channelx.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_dma_init(void)
+ * {
+ *     uint8_t channel_num = DMA_ChannelNum;
+ *     DMA_ChannelTypeDef *DMA_Channelx = DMA_GetDMAChannelx(DMA_ChannelNum);
+ * }
+ * \endcode
+ */
+DMA_ChannelTypeDef *DMA_GetDMAChannelx(uint8_t DMA_ChannelNum);
+
+/**
+ * \brief     Get DMA IRQx of the specified DMA Channel Number.
+ *
+ * \param[in]  DMA_ChannelNum: Select the DMA channel number. \ref DMA_CHANNEL_NUM
+ *
+ * \return    DMA_IRQx.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_dma_init(void)
+ * {
+ *     IRQn_Type irqx;
+ *     IRQn_Type irqx = DMA_GetDMAIRQx(DMA_ChannelNum);
+ * }
+ * \endcode
+ */
+IRQn_Type DMA_GetDMAIRQx(uint8_t DMA_ChannelNum);
+
+/**
+ * \brief     Get DMA number by the specified DMA IRQx.
+ *
+ * \param[in]  irq: Select the DMA IRQx.
+ *
+ * \return    DMA number.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_dma_init(void)
+ * {
+ *     uint8_t dma_num;
+ *     dma_num = DMA_GetDMANumByIRQx(DMA1_CH0_IRQn);
+ * }
+ * \endcode
+ */
+uint8_t DMA_GetDMANumByIRQx(IRQn_Type irq);
+
+#if (DMA_SUPPORT_SECURE_MODE == 1)
+/**
+ * \brief     Enable or disable the specified DMA channel secure functions.
+ *
+ * \param[in] DMA_Channelx: Select the DMA peripheral. \ref DMA_Declaration
+ * \param[in] NewState: Specifies the DMA channel secure function to be enabled or disabled.
+ *            This parameter can be ENABLE or DISABLE.
+ *
+ * \return    None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void dma_demo(void)
+ * {
+ *     DMA_SecureCmd(DMA_Channel3, ENABLE);
+ * }
+ *
+ * \endcode
+ */
+void DMA_SecureCmd(DMA_ChannelTypeDef *DMA_Channelx, FunctionalState NewState);
+#endif
+
+#if (DMA_SUPPORT_OSW_OSR_CHANGE == 1)
+/**
+ * \brief     Set DMA OSW.
+ *
+ * \param[in]  DMA_ChannelNum: Select the DMA channel number. \ref DMA_CHANNEL_NUM
+ * \param[in] osw_count: outstanding write count.
+ *
+ * \return    None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void dma_demo(void)
+ * {
+ *     DMA_SetOSW(DMA_Channel0, 10);
+ * }
+ * \endcode
+ */
+void DMA_SetOSW(uint8_t DMA_ChannelNum, uint8_t osw_count);
+
+/**
+ * \brief  Set DMA OSR.
+ *
+ * \param[in]  DMA_ChannelNum: Select the DMA channel number. \ref DMA_CHANNEL_NUM
+ * \param[in] osr_count: outstanding read count.
+ *
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void dma_demo(void)
+ * {
+ *     DMA_SetOSR(DMA_Channel0, 10);
+ * }
+ * \endcode
+ */
+void DMA_SetOSR(uint8_t DMA_ChannelNum, uint8_t osr_count);
+
+/**
+ * \brief     Get DMA OSW.
+ *
+ * \param[in]  DMA_ChannelNum: Select the DMA channel number. \ref DMA_CHANNEL_NUM
+ *
+ * \return    osw_count: outstanding write count.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void dma_demo(void)
+ * {
+ *     uint32_t osw_count = DMA_GetOSWCount(DMA_Channel0);
+ * }
+ * \endcode
+ */
+uint8_t DMA_GetOSWCount(uint8_t DMA_ChannelNum);
+
+/**
+ * \brief     Get DMA OSR.
+ *
+ * \param[in]  DMA_ChannelNum: Select the DMA channel number. \ref DMA_CHANNEL_NUM
+ *
+ * \return    osr_count: outstanding read count.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void dma_demo(void)
+ * {
+ *     uint8_t osr_count = DMA_GetOSRCount(DMA_Channel0);
+ * }
+ * \endcode
+ */
+uint8_t DMA_GetOSRCount(uint8_t DMA_ChannelNum);
+#endif
+
+#if (DMA_SUPPORT_CONTINUOUS_BLOCK_ADDRESS == 1)
+
+void DMA_ContSarCmd(DMA_ChannelTypeDef *DMA_Channelx, FunctionalState NewState);
+
+void DMA_ContDarCmd(DMA_ChannelTypeDef *DMA_Channelx, FunctionalState NewState);
+
+#endif
+
+#if (DMA_SUPPORT_BLOCK_COUNTER == 1)
+
+void DMA_SetBlockCounter(DMA_ChannelTypeDef *DMA_Channelx, uint32_t block_counter);
+
+#endif
+
+#if (DMA_SUPPORT_RAP_FUNCTION == 1)
+
+bool DMA_RAPModeCmd(DMA_ChannelTypeDef *DMA_Channelx, FunctionalState NewState);
+
+#endif
+
+#if (DMA_SUPPORT_AUTO_CLOCK == 1)
+
+void DMA_ClockAutoModeCmd(DMA_ChannelTypeDef *DMA_Channelx, FunctionalState Newstate);
+
+#endif
+
+#if (DMA_SUPPORT_AUTO_SLOW_CONFIG == 1)
+/**
+ * \brief     DMA auto slow config.
+ *
+ * \param[in]  DMA_ChannelNum: Select the DMA channel number. \ref DMA_CHANNEL_NUM.
+ *
+ * \param[in]  AutoSlowMode: Select the DMA auto slow mode. \ref DMAAutoSlow_TypeDef.
+ *            This parameter can be any combination of the following values:
+ *            - DMA_NOT_ALLOW_AUTO_SLOW_WHEN_ENABLE: DMA not allow auto slow when DMA enable but in idle state.
+ *            - DMA_ALLOW_AUTO_SLOW_WHEN_ENABLE: DMA allow auto slow when DMA enable but in idle state.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void dma_demo(void)
+ * {
+ *     DMA_AutoSlowConfig(0, DMA_NOT_ALLOW_AUTO_SLOW_WHEN_ENABLE);
+ * }
+ * \endcode
+ */
+void DMA_AutoSlowConfig(uint8_t DMA_ChannelNum, DMAAutoSlow_TypeDef AutoSlowMode);
+#endif
+/** End of DMA_Exported_Functions
+  * \}
+  */
+
+/** End of DMA
+  * \}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RTL_DMA_H */
+
+
+
+
diff --git a/bee/drivers/dma/src/CMakeLists.txt b/bee/drivers/dma/src/CMakeLists.txt
new file mode 100644
index 00000000..dd5e359a
--- /dev/null
+++ b/bee/drivers/dma/src/CMakeLists.txt
@@ -0,0 +1,4 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+add_subdirectory(device)
diff --git a/bee/drivers/dma/src/device/CMakeLists.txt b/bee/drivers/dma/src/device/CMakeLists.txt
new file mode 100644
index 00000000..390b5305
--- /dev/null
+++ b/bee/drivers/dma/src/device/CMakeLists.txt
@@ -0,0 +1,11 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+if(CONFIG_REALTEK_BEE_COMMON_DRIVER)
+    file(GLOB BEE_DRIVER_COMMON_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/rtl_common/*.c")
+    zephyr_library_sources(${BEE_DRIVER_COMMON_SOURCES})
+endif()
+
+add_soc_series_subdir(rtl8752h)
+add_soc_series_subdir(rtl87x2g)
+add_soc_series_subdir(rtl87x2j)
diff --git a/bee/drivers/dma/src/device/rtl8752h/rtl876x_gdma.c b/bee/drivers/dma/src/device/rtl8752h/rtl876x_gdma.c
new file mode 100644
index 00000000..57d428d9
--- /dev/null
+++ b/bee/drivers/dma/src/device/rtl8752h/rtl876x_gdma.c
@@ -0,0 +1,401 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "rtl876x_rcc.h"
+#include "rtl876x_gdma.h"
+
+/*fifo depth*/
+#define UART_RX_FIFO_DEPTH      32
+#define UART_TX_FIFO_DEPTH      16
+#define SPI_RX_FIFO_DEPTH       36
+#define SPI_TX_FIFO_DEPTH       36
+#define I2C_RX_FIFO_DEPTH       16
+#define I2C_TX_FIFO_DEPTH       24
+
+#define REG_GDMA_TIMER          *((volatile uint32_t *)0x40006024UL)
+
+/**
+  * @brief  Deinitializes the GDMA registers to their default reset values.
+  * @param  None
+  * @return None
+  */
+void GDMA_DeInit(void)
+{
+    /* Disable GDMA block in REG_SOC_FUNC_EN */
+    RCC_PeriphClockCmd(APBPeriph_GDMA, APBPeriph_GDMA_CLOCK, DISABLE);
+}
+
+/**
+  * @brief  Initializes the GDMA Channelx according to the specified
+  *         parameters in the GDMA_InitStruct.
+  * @param  GDMA_Channelx: where x can be 0 to 3  to select the DMA Channel.
+  * @param  GDMA_InitStruct: pointer to a GDMA_InitTypeDef structure that
+  *         contains the configuration information for the specified DMA Channel.
+  * @return None
+  */
+void GDMA_Init(GDMA_ChannelTypeDef *GDMA_Channelx, GDMA_InitTypeDef *GDMA_InitStruct)
+{
+    uint32_t temp_bit = 0;
+    uint32_t autoreload_temp;
+    uint32_t llp_temp;
+
+    /* Check the parameters */
+    assert_param(IS_GDMA_ALL_PERIPH(GDMA_Channelx));
+    assert_param(IS_GDMA_ChannelNum(GDMA_InitStruct->GDMA_ChannelNum));
+    assert_param(IS_GDMA_DIR(GDMA_InitStruct->GDMA_DIR));
+    assert_param(IS_GDMA_SourceInc(GDMA_InitStruct->GDMA_SourceInc));
+    assert_param(IS_GDMA_DestinationInc(GDMA_InitStruct->GDMA_DestinationInc));
+    assert_param(IS_GDMA_DATA_SIZE(GDMA_InitStruct->GDMA_SourceDataSize));
+    assert_param(IS_GDMA_DATA_SIZE(GDMA_InitStruct->GDMA_DestinationDataSize));
+
+    /*------------------configure source and destination address of GDMA---------*/
+    /* program SARx register to set source address */
+    GDMA_Channelx->SAR = GDMA_InitStruct->GDMA_SourceAddr;
+    /* program DARx register to set destination address */
+    GDMA_Channelx->DAR = GDMA_InitStruct->GDMA_DestinationAddr;
+
+    /* Enable GDMA in DmaCfgReg*/
+    GDMA_BASE->DmaCfgReg = 0x01;
+
+    /* read ChEnReg to check channel is busy or not */
+    if (GDMA_BASE->ChEnReg & BIT(GDMA_InitStruct->GDMA_ChannelNum))
+    {
+        //channel is be used
+        //error handle code
+        //while (1);
+    }
+
+    /*--------------------------- GDMA Configuration -----------------*/
+    /* clear pending interrupts of corresponding GDMA channel */
+    temp_bit = BIT(GDMA_InitStruct->GDMA_ChannelNum);
+    GDMA_BASE->CLEAR_TFR = temp_bit;
+    GDMA_BASE->CLEAR_BLOCK = temp_bit;
+    GDMA_BASE->CLEAR_DST_TRAN = temp_bit;
+    GDMA_BASE->CLEAR_SRC_TRAN = temp_bit;
+    GDMA_BASE->CLEAR_ERR = temp_bit;
+
+    /* mask pending interrupts of corresponding GDMA channel */
+    temp_bit = BIT(GDMA_InitStruct->GDMA_ChannelNum + 8);
+    GDMA_BASE->MASK_TFR = temp_bit;
+    GDMA_BASE->MASK_BLOCK = temp_bit;
+    GDMA_BASE->MASK_DST_TRAN = temp_bit;
+    GDMA_BASE->MASK_SRC_TRAN = temp_bit;
+    GDMA_BASE->MASK_ERR = temp_bit;
+
+    /*---------------------------- configure CTL register --------------------------------*/
+
+    /* configure low 32 bit of CTL register */
+    GDMA_Channelx->CTL_LOW = BIT(0)
+                             | (GDMA_InitStruct->GDMA_DestinationDataSize << 1)
+                             | (GDMA_InitStruct->GDMA_SourceDataSize << 4)
+                             | (GDMA_InitStruct->GDMA_DestinationInc << 7)
+                             | (GDMA_InitStruct->GDMA_SourceInc << 9)
+                             | (GDMA_InitStruct->GDMA_DestinationMsize << 11)
+                             | (GDMA_InitStruct->GDMA_SourceMsize << 14)
+                             | (GDMA_InitStruct->GDMA_DIR << 20);
+    /* configure high 32 bit of CTL register */
+    GDMA_Channelx->CTL_HIGH = GDMA_InitStruct->GDMA_BufferSize;
+
+    /*---------------------------- configure CFG register --------------------------------*/
+
+    switch (GDMA_InitStruct->GDMA_DIR)
+    {
+    case GDMA_DIR_MemoryToMemory:
+        GDMA_Channelx->CFG_LOW = (0x03 << 10);
+        break;
+    case GDMA_DIR_MemoryToPeripheral:
+        GDMA_Channelx->CFG_LOW = BIT11;
+        break;
+    case GDMA_DIR_PeripheralToMemory:
+        GDMA_Channelx->CFG_LOW = BIT10;
+        break;
+    case GDMA_DIR_PeripheralToPeripheral:
+        GDMA_Channelx->CFG_LOW = 0;
+        break;
+    default:
+        GDMA_Channelx->CFG_LOW = 0;
+        break;
+    }
+
+    if (GDMA_InitStruct->GDMA_Multi_Block_En == 1 &&
+        ((GDMA_Channelx == GDMA_Channel0) | (GDMA_Channelx == GDMA_Channel1)))
+    {
+        /* Config multi-block mode */
+        GDMA_Channelx->CFG_LOW &= ~AUTO_RELOAD_SELECTED_BIT;
+        GDMA_Channelx->CTL_LOW &= ~LLP_SELECTED_BIT;
+        autoreload_temp = (GDMA_InitStruct->GDMA_Multi_Block_Mode & AUTO_RELOAD_SELECTED_BIT);
+        llp_temp = (GDMA_InitStruct->GDMA_Multi_Block_Mode & LLP_SELECTED_BIT);
+        if (llp_temp)
+        {
+            GDMA_Channelx->LLP = GDMA_InitStruct->GDMA_Multi_Block_Struct;
+            GDMA_Channelx->CTL_LOW |= llp_temp;
+        }
+        GDMA_Channelx->CFG_LOW |= autoreload_temp;
+    }
+
+    /* Set Vendor register about timer handshake */
+    if ((GDMA_InitStruct->GDMA_DestHandshake == GDMA_Handshake_ENH_TIM0) ||
+        (GDMA_InitStruct->GDMA_DestHandshake == GDMA_Handshake_ENH_TIM1))
+    {
+        REG_GDMA_TIMER |= BIT(GDMA_InitStruct->GDMA_DestHandshake + 20);
+    }
+    else if ((GDMA_InitStruct->GDMA_DestHandshake >= GDMA_Handshake_TIM0) &&
+             (GDMA_InitStruct->GDMA_DestHandshake <= GDMA_Handshake_TIM2))
+    {
+        REG_GDMA_TIMER |= BIT(GDMA_InitStruct->GDMA_DestHandshake - 8);
+    }
+    else if ((GDMA_InitStruct->GDMA_DestHandshake >= GDMA_Handshake_TIM3) &&
+             (GDMA_InitStruct->GDMA_DestHandshake <= GDMA_Handshake_TIM5))
+    {
+        REG_GDMA_TIMER |= BIT(GDMA_InitStruct->GDMA_DestHandshake - 10);
+    }
+
+    /* configure peripheral parameters and configure source or destination hardware handshaking interface */
+    GDMA_Channelx->CFG_HIGH &=  ~(0x03fff << 7);
+
+    GDMA_Channelx->CFG_HIGH |= (((((GDMA_InitStruct->GDMA_SourceHandshake) & 0x20) << 5) \
+                                 | (((GDMA_InitStruct->GDMA_SourceHandshake) & 0x10) << 4) \
+                                 | ((GDMA_InitStruct->GDMA_SourceHandshake) & 0x0f)) << 7);
+    GDMA_Channelx->CFG_HIGH |= (((((GDMA_InitStruct->GDMA_DestHandshake) & 0x20) << 2) \
+                                 | (((GDMA_InitStruct->GDMA_DestHandshake) & 0x10) << 1) \
+                                 | ((GDMA_InitStruct->GDMA_DestHandshake) & 0x0f)) << 11);
+
+    /* Enable FIFO mode and Flow control mode */
+    GDMA_Channelx->CFG_HIGH &= ~0x03;
+    GDMA_Channelx->CFG_HIGH |= 0x02;
+
+    /* ---------------clear pending interrupts of corresponding GDMA channel------------------ */
+    temp_bit = BIT(GDMA_InitStruct->GDMA_ChannelNum);
+    GDMA_BASE->CLEAR_TFR = temp_bit;
+    GDMA_BASE->CLEAR_BLOCK = temp_bit;
+    GDMA_BASE->CLEAR_DST_TRAN = temp_bit;
+    GDMA_BASE->CLEAR_SRC_TRAN = temp_bit;
+    GDMA_BASE->CLEAR_ERR = temp_bit;
+}
+
+/**
+  * @brief  Fills each GDMA_InitStruct member with its default value.
+  * @param  GDMA_InitStruct : pointer to a GDMA_InitTypeDef structure which will
+  *         be initialized.
+  * @return None
+  */
+void GDMA_StructInit(GDMA_InitTypeDef *GDMA_InitStruct)
+{
+    /*-------------- Reset DMA init structure parameters values ------------------*/
+    GDMA_InitStruct->GDMA_ChannelNum      = 0;
+    GDMA_InitStruct->GDMA_DIR             = GDMA_DIR_PeripheralToMemory;
+    GDMA_InitStruct->GDMA_BufferSize      = 200;
+    GDMA_InitStruct->GDMA_SourceInc       = DMA_SourceInc_Fix;
+    GDMA_InitStruct->GDMA_DestinationInc  = DMA_DestinationInc_Inc;
+    GDMA_InitStruct->GDMA_SourceDataSize  = GDMA_DataSize_Byte;
+    GDMA_InitStruct->GDMA_DestinationDataSize   = GDMA_DataSize_Byte;
+    GDMA_InitStruct->GDMA_SourceMsize           = GDMA_Msize_1;
+    GDMA_InitStruct->GDMA_DestinationMsize      = GDMA_Msize_1;
+    GDMA_InitStruct->GDMA_SourceAddr      = 0;
+    GDMA_InitStruct->GDMA_DestinationAddr = 0;
+    GDMA_InitStruct->GDMA_SourceHandshake = 0;
+    GDMA_InitStruct->GDMA_DestHandshake   = 0;
+    GDMA_InitStruct->GDMA_ChannelPriority = 0;
+
+    GDMA_InitStruct->GDMA_Multi_Block_En   = DISABLE;
+    GDMA_InitStruct->GDMA_Multi_Block_Mode = LLI_TRANSFER;
+}
+
+/**
+  * @brief  Enables or disables the specified GDMA Channelx.
+  * @param  GDMA_Channelx: x can be 0 to 3 to select the DMA Channel.
+  * @param  NewState: new state of the DMA Channelx.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @return None
+  */
+void GDMA_Cmd(uint8_t GDMA_ChannelNum, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_GDMA_ChannelNum(GDMA_ChannelNum));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    GDMA_ChannelTypeDef *GDMA_Channelx;
+    GDMA_Channelx = (GDMA_ChannelTypeDef *)DMA_CH_BASE(GDMA_ChannelNum);
+
+    uint8_t bit_need_set_times = 10;
+    uint8_t bit_need_check_times = 50;
+    uint8_t timeout = bit_need_check_times ;
+    uint8_t bit_set_time = 0;
+
+    if (NewState != DISABLE)
+    {
+        /* Enable the selected DMAy Channelx */
+        GDMA_BASE->ChEnReg |= BIT(GDMA_ChannelNum) | BIT(GDMA_ChannelNum + 8);
+    }
+    else
+    {
+        /*gdma transfor not finished */
+        if (GDMA_BASE->ChEnReg & BIT(GDMA_ChannelNum))
+            /* suspend gdma channel */
+        {
+            GDMA_Channelx->CFG_LOW |= GDMA_SUSPEND_TRANSMISSSION;
+        }
+        /* Disable the selected DMAy Channelx */
+        /* polling fifo empty */
+        while ((GDMA_GetSuspendChannelStatus(GDMA_Channelx) != SET) && --timeout);
+        /*cfg bit0 not set */
+        if (GDMA_GetSuspendChannelStatus(GDMA_Channelx) != SET)
+        {
+            timeout = bit_need_check_times;
+            /*polling cfg[1:2] 10 times set in 100timer check */
+            while (--timeout)
+            {
+                if ((GDMA_Channelx->CFG_LOW & BIT1) && (GDMA_Channelx->CFG_LOW & BIT2))
+                {
+                    bit_set_time++;
+                    if (bit_set_time >= bit_need_set_times)
+                    {
+                        break;
+                    }
+                }
+            }
+//              if (timeout == 0)
+//              {
+//                  /*abort disable dma return fail*/
+//                  return GDMA_DISABLE_FAIL;
+//              }
+        }
+
+        /* Disable the selected DMAy Channelx */
+        GDMA_BASE->ChEnReg = BIT(GDMA_ChannelNum + 8);
+        /* unsuspend dma channel */
+        GDMA_Channelx->CFG_LOW &= ~(GDMA_SUSPEND_TRANSMISSSION);
+    }
+}
+
+/**
+  * @brief  Enables or disables the specified DMA Channelx interrupts.
+  * @param  GDMA_Channelx: where x can be 0 to 3 to select the GDMA Channel.
+  * @param  GDMA_IT: specifies the GDMA interrupts sources to be enabled or disabled.
+  *         This parameter can be any combination of the following values:
+  *         @arg GDMA_INT_Transfer:  Transfer complete interrupt unmask
+  *         @arg GDMA_INT_Block:  Block transfer interrupt unmask
+  *         @arg GDMA_INT_SrcTransfer:  SourceTransfer interrupt unmask
+  *         @arg GDMA_INT_DstTransfer:  Destination Transfer interrupt unmask
+  *         @arg GDMA_INT_Error:  Transfer error interrupt unmask
+  * @param  NewState: new state of the specified DMA interrupts.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @return None
+  */
+void GDMA_INTConfig(uint8_t GDMA_ChannelNum, uint32_t GDMA_IT, FunctionalState NewState)
+{
+    uint32_t temp_bit = 0;
+
+    /* Check the parameters */
+    assert_param(IS_GDMA_ChannelNum(GDMA_ChannelNum));
+    assert_param(IS_GDMA_CONFIG_IT(GDMA_IT));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (NewState != DISABLE)
+    {
+        /* Enable the selected DMA interrupts */
+        temp_bit = BIT(GDMA_ChannelNum) | BIT(GDMA_ChannelNum + 8);
+
+        if (GDMA_IT & GDMA_INT_Transfer)
+        {
+            GDMA_BASE->MASK_TFR |= temp_bit;
+        }
+        if (GDMA_IT & GDMA_INT_Block)
+        {
+            GDMA_BASE->MASK_BLOCK |= temp_bit;
+        }
+        if (GDMA_IT & GDMA_INT_SrcTransfer)
+        {
+            GDMA_BASE->MASK_SRC_TRAN |= temp_bit;
+        }
+        if (GDMA_IT & GDMA_INT_DstTransfer)
+        {
+            GDMA_BASE->MASK_DST_TRAN |= temp_bit;
+        }
+        if (GDMA_IT & GDMA_INT_Error)
+        {
+            GDMA_BASE->MASK_ERR |= temp_bit;
+        }
+    }
+    else
+    {
+        /* Disable the selected DMA interrupts */
+        temp_bit = BIT(GDMA_ChannelNum + 8);
+        if (GDMA_IT & GDMA_INT_Transfer)
+        {
+            GDMA_BASE->MASK_TFR = temp_bit;
+        }
+        if (GDMA_IT & GDMA_INT_Block)
+        {
+            GDMA_BASE->MASK_BLOCK = temp_bit;
+        }
+        if (GDMA_IT & GDMA_INT_SrcTransfer)
+        {
+            GDMA_BASE->MASK_SRC_TRAN = temp_bit;
+        }
+        if (GDMA_IT & GDMA_INT_DstTransfer)
+        {
+            GDMA_BASE->MASK_DST_TRAN = temp_bit;
+        }
+        if (GDMA_IT & GDMA_INT_Error)
+        {
+            GDMA_BASE->MASK_ERR = temp_bit;
+        }
+    }
+}
+
+/**
+  * @brief  Enables or disables the specified DMA Channelx interrupts.
+  * @param  GDMA_Channelx: where x can be 0 to 3 to select the GDMA Channel.
+  * @param  GDMA_IT: specifies the GDMA interrupts sources to be enabled
+  *   or disabled.
+  *   This parameter can be any combination of the following values:
+  *     @arg GDMA_INT_Transfer:  clear transfer complete interrupt
+  *     @arg GDMA_INT_Block:  clear Block transfer interrupt
+  *     @arg GDMA_INT_SrcTransfer:  clear SourceTransfer interrupt
+  *     @arg GDMA_INT_DstTransfer:  clear Destination Transfer interrupt
+  *     @arg GDMA_INT_Error:  clear Transfer error interrupt
+  * @param  NewState: new state of the specified DMA interrupts.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @return None
+  */
+void GDMA_ClearINTPendingBit(uint8_t GDMA_ChannelNum, uint32_t GDMA_IT)
+{
+    uint32_t temp_bit = 0;
+
+    /* Check the parameters */
+    assert_param(IS_GDMA_ChannelNum(GDMA_ChannelNum));
+    assert_param(IS_GDMA_CONFIG_IT(GDMA_IT));
+
+    /* clear the selected DMA interrupts */
+    //temp_bit = BIT(GDMA_ChannelNum) | BIT(GDMA_ChannelNum + 8);
+    temp_bit = BIT(GDMA_ChannelNum);
+
+    if (GDMA_IT & GDMA_INT_Transfer)
+    {
+        GDMA_BASE->CLEAR_TFR = temp_bit;
+    }
+    if (GDMA_IT & GDMA_INT_Block)
+    {
+        GDMA_BASE->CLEAR_BLOCK = temp_bit;
+    }
+    if (GDMA_IT & GDMA_INT_SrcTransfer)
+    {
+        GDMA_BASE->CLEAR_SRC_TRAN = temp_bit;
+    }
+    if (GDMA_IT & GDMA_INT_DstTransfer)
+    {
+        GDMA_BASE->CLEAR_DST_TRAN = temp_bit;
+    }
+    if (GDMA_IT & GDMA_INT_Error)
+    {
+        GDMA_BASE->CLEAR_ERR = temp_bit;
+    }
+}
+
+
+
diff --git a/bee/drivers/dma/src/device/rtl8752h/rtl876x_gdma.h b/bee/drivers/dma/src/device/rtl8752h/rtl876x_gdma.h
new file mode 100644
index 00000000..0425f6ef
--- /dev/null
+++ b/bee/drivers/dma/src/device/rtl8752h/rtl876x_gdma.h
@@ -0,0 +1,982 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _RTL876X_GDMA_H_
+#define _RTL876X_GDMA_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup  IO          Peripheral Drivers
+ * \defgroup    GDMA        GDMA
+ *
+ * \brief       Manage the GDMA peripheral functions.
+ *
+ * \ingroup     IO
+ */
+
+/*============================================================================*
+ *                         Includes
+ *============================================================================*/
+#include "rtl876x.h"
+
+/*============================================================================*
+ *                         Types
+ *============================================================================*/
+/**
+ * \defgroup    GDMA_Exported_Types GDMA Exported Types
+ *
+ * \ingroup     GDMA
+ */
+
+/**
+ * \brief       GDMA init structure definition.
+ *
+ * \ingroup     GDMA_Exported_Types
+ */
+typedef struct
+{
+    uint8_t GDMA_ChannelNum;            /*!< Specify the channel number for GDMA, which can be 0 to 3. */
+    uint8_t GDMA_DIR;                   /*!< Specify if the peripheral is the source or destination.
+                                            This parameter can be a value of \ref GDMA_Data_Transfer_Direction. */
+    uint32_t GDMA_BufferSize;           /*!< Specify the buffer size (<=65535), in data units, of the specified channel.
+                                            The data unit is equal to the configuration set in DMA_PeripheralDataSize
+                                            or DMA_MemoryDataSize members depending on the transfer direction. */
+    uint8_t GDMA_SourceInc;             /*!< Specify whether the source address register is incremented or not.
+                                            This parameter can be a value of \ref GDMA_Source_Incremented_Mode. */
+    uint8_t GDMA_DestinationInc;        /*!< Specify whether the destination address register is incremented or not.
+                                            This parameter can be a value of \ref GDMA_Destination_Incremented_Mode. */
+    uint32_t GDMA_SourceDataSize;       /*!< Specify the source data width.
+                                            This parameter can be a value of \ref GDMA_Data_Size. */
+    uint32_t GDMA_DestinationDataSize;  /*!< Specify the destination memory data width.
+                                            This parameter can be a value of \ref GDMA_Data_Size. */
+    uint32_t GDMA_SourceMsize;          /*!< Specify the number of data items to be transferred.
+                                            This parameter can be a value of \ref GDMA_Msize. */
+    uint32_t GDMA_DestinationMsize;     /*!< Specify the number of data items to be transferred.
+                                            This parameter can be a value of \ref GDMA_Msize. */
+    uint32_t GDMA_SourceAddr;           /*!< Specify the source base address for GDMA channel. */
+    uint32_t GDMA_DestinationAddr;      /*!< Specify the destination base address for GDMA channel. */
+    uint32_t GDMA_ChannelPriority;      /*!< Specify the software priority for the GDMA channel. */
+    uint32_t GDMA_Multi_Block_Mode;     /*!< Specify the multi-block transfer mode.
+                                            This parameter can be a value of \ref GDMA_Multiblock_Mode. */
+    uint32_t GDMA_Multi_Block_Struct;   /*!< Pointer to the first struct of LLI. */
+    uint8_t  GDMA_Multi_Block_En;       /*!< Enable or disable multi-block function. */
+    uint8_t  GDMA_SourceHandshake;      /*!< Specify the handshake index in source.
+                                            This parameter can be a value of \ref GDMA_Handshake_Type. */
+    uint8_t  GDMA_DestHandshake;        /*!< Specify the handshake index in destination.
+                                            This parameter can be a value of \ref GDMA_Handshake_Type. */
+} GDMA_InitTypeDef;
+
+/**
+ * \brief       GDMA link list item structure definition.
+ *
+ * \ingroup     GDMA_Exported_Types
+ */
+typedef struct
+{
+    __IO uint32_t SAR;                  /*!< Specify the source address of link list item. */
+    __IO uint32_t DAR;                  /*!< Specify the destination address of link list item. */
+    __IO uint32_t LLP;                  /*!< Specify the address of the next linked item. */
+    __IO uint32_t CTL_LOW;              /*!< Specify the low 32 bit of CTL register. */
+    __IO uint32_t CTL_HIGH;             /*!< Specify the high 32 bit of CTL register. */
+} GDMA_LLIDef;
+
+/** End of GDMA_Exported_Types
+  * \}
+  */
+
+/*============================================================================*
+ *                         Constants
+ *============================================================================*/
+/**
+ * \defgroup    GDMA_Exported_Constants GDMA Exported Constants
+ *
+ * \ingroup     GDMA
+ */
+#define IS_GDMA_ALL_PERIPH(PERIPH) (((PERIPH) == GDMA_Channel0) || \
+                                    ((PERIPH) == GDMA_Channel1) || \
+                                    ((PERIPH) == GDMA_Channel2) || \
+                                    ((PERIPH) == GDMA_Channel3))
+
+#define GDMA_CH_NUM0            0
+#define GDMA_CH_NUM1            1
+#define GDMA_CH_NUM2            2
+#define GDMA_CH_NUM3            3
+#define GDMA_CH_NUM_MIN         GDMA_CH_NUM0
+
+#define IS_GDMA_ChannelNum(NUM) ((NUM) < 4)
+
+#define DMA_CH_IRQ(ChNum)       ((IRQn_Type)((GDMA0_Channel0_IRQn + (ChNum - GDMA_CH_NUM_MIN))))
+#define DMA_CH_VECTOR(ChNum)    ((VECTORn_Type)(GDMA0_Channel0_VECTORn + (ChNum - GDMA_CH_NUM_MIN)))
+#define DMA_CH_BASE(ChNum)      ((GDMA_ChannelTypeDef *)((ChNum >= GDMA_CH_NUM3) ? \
+                                                         (GDMA_Channel3_BASE + (ChNum - GDMA_CH_NUM3) * 0x0058) : \
+                                                         (GDMA_Channel0_BASE + (ChNum - GDMA_CH_NUM_MIN) * 0x0058)))
+
+/**
+ * \defgroup    GDMA_Handshake_Type GDMA Handshake Type
+ * \{
+ * \ingroup     GDMA_Exported_Constants
+ */
+#define GDMA_Handshake_UART1_TX         (0)
+#define GDMA_Handshake_UART1_RX         (1)
+#define GDMA_Handshake_ENH_TIM0         (2)
+#define GDMA_Handshake_ENH_TIM1         (3)
+#define GDMA_Handshake_SPI0_TX          (4)
+#define GDMA_Handshake_SPI0_RX          (5)
+#define GDMA_Handshake_SPI1_TX          (6)
+#define GDMA_Handshake_SPI1_RX          (7)
+#define GDMA_Handshake_I2C0_TX          (8)
+#define GDMA_Handshake_I2C0_RX          (9)
+#define GDMA_Handshake_I2C1_TX          (10)
+#define GDMA_Handshake_I2C1_RX          (11)
+#define GDMA_Handshake_ADC              (12)
+#define GDMA_Handshake_AES_TX           (13)
+#define GDMA_Handshake_AES_RX           (14)
+#define GDMA_Handshake_UART0_TX         (15)
+#define GDMA_Handshake_I2S0_TX          (16)
+#define GDMA_Handshake_I2S0_RX          (17)
+#define GDMA_Handshake_UART2_TX         (18)
+#define GDMA_Handshake_UART2_RX         (19)
+#define GDMA_Handshake_SPIC0_TX         (20)
+#define GDMA_Handshake_SPIC0_RX         (21)
+#define GDMA_Handshake_I8080_RX         (22)
+#define GDMA_Handshake_UART0_RX         (23)
+#define GDMA_Handshake_TIM0             (24)
+#define GDMA_Handshake_TIM1             (25)
+#define GDMA_Handshake_TIM2             (26)
+#define GDMA_Handshake_IR_TX            (27)
+#define GDMA_Handshake_IR_RX            (28)
+#define GDMA_Handshake_TIM3             (29)
+#define GDMA_Handshake_TIM4             (30)
+#define GDMA_Handshake_TIM5             (31)
+#define GDMA_Handshake_SPIC1_TX         (32)
+#define GDMA_Handshake_SPIC1_RX         (33)
+#define GDMA_Handshake_SHA256_TX        (35)
+/** \} */ /** End of Group GDMA_Handshake_Type */
+
+#define IS_GDMA_TransferType(Type) (((Type) == GDMA_Handshake_UART1_TX) || \
+                                    ((Type) == GDMA_Handshake_UART1_RX) || \
+                                    ((Type) == GDMA_Handshake_ENH_TIM0) || \
+                                    ((Type) == GDMA_Handshake_ENH_TIM1) || \
+                                    ((Type) == GDMA_Handshake_SPI0_TX) || \
+                                    ((Type) == GDMA_Handshake_SPI0_RX) || \
+                                    ((Type) == GDMA_Handshake_SPI1_TX) || \
+                                    ((Type) == GDMA_Handshake_SPI1_RX) || \
+                                    ((Type) == GDMA_Handshake_I2C0_TX) || \
+                                    ((Type) == GDMA_Handshake_I2C0_RX) || \
+                                    ((Type) == GDMA_Handshake_I2C1_TX) || \
+                                    ((Type) == GDMA_Handshake_I2C1_RX) || \
+                                    ((Type) == GDMA_Handshake_ADC) || \
+                                    ((Type) == GDMA_Handshake_AES_TX) || \
+                                    ((Type) == GDMA_Handshake_AES_RX) || \
+                                    ((Type) == GDMA_Handshake_UART0_TX) || \
+                                    ((Type) == GDMA_Handshake_I2S0_TX) || \
+                                    ((Type) == GDMA_Handshake_I2S0_RX) || \
+                                    ((Type) == GDMA_Handshake_UART2_TX) || \
+                                    ((Type) == GDMA_Handshake_UART2_RX) || \
+                                    ((Type) == GDMA_Handshake_SPIC0_TX) || \
+                                    ((Type) == GDMA_Handshake_SPIC0_RX) || \
+                                    ((Type) == GDMA_Handshake_I8080_RX)|| \
+                                    ((Type) == GDMA_Handshake_UART0_RX) || \
+                                    ((Type) == GDMA_Handshake_TIM0)|| \
+                                    ((Type) == GDMA_Handshake_TIM1)|| \
+                                    ((Type) == GDMA_Handshake_TIM2)|| \
+                                    ((Type) == GDMA_Handshake_IR_TX) || \
+                                    ((Type) == GDMA_Handshake_IR_RX) || \
+                                    ((Type) == GDMA_Handshake_TIM3)|| \
+                                    ((Type) == GDMA_Handshake_TIM4)|| \
+                                    ((Type) == GDMA_Handshake_TIM5)|| \
+                                    ((Type) == GDMA_Handshake_SPIC1_TX)|| \
+                                    ((Type) == GDMA_Handshake_SPIC1_RX)|| \
+                                    ((Type) == GDMA_Handshake_SHA256_TX)))
+
+/**
+ * \defgroup    GDMA_Data_Size GDMA Data Size
+ * \{
+ * \ingroup     GDMA_Exported_Constants
+ */
+#define GDMA_DataSize_Byte                  ((uint32_t)0x00000000)
+#define GDMA_DataSize_HalfWord              ((uint32_t)0x00000001)
+#define GDMA_DataSize_Word                  ((uint32_t)0x00000002)
+/** \} */
+
+#define IS_GDMA_DATA_SIZE(SIZE) (((SIZE) == GDMA_DataSize_Byte) || \
+                                 ((SIZE) == GDMA_DataSize_HalfWord) || \
+                                 ((SIZE) == GDMA_DataSize_Word))
+
+/**
+ * \defgroup    GDMA_Msize GDMA Msize
+ * \{
+ * \ingroup     GDMA_Exported_Constants
+ */
+#define GDMA_Msize_1                        ((uint32_t)0x00000000)
+#define GDMA_Msize_4                        ((uint32_t)0x00000001)
+#define GDMA_Msize_8                        ((uint32_t)0x00000002)
+#define GDMA_Msize_16                       ((uint32_t)0x00000003)
+#define GDMA_Msize_32                       ((uint32_t)0x00000004)
+#define GDMA_Msize_64                       ((uint32_t)0x00000005)
+#define GDMA_Msize_128                      ((uint32_t)0x00000006)
+#define GDMA_Msize_256                      ((uint32_t)0x00000007)
+/** \} */
+
+#define IS_GDMA_MSIZE(SIZE) (((SIZE) == GDMA_Msize_1) || \
+                             ((SIZE) == GDMA_Msize_4) || \
+                             ((SIZE) == GDMA_Msize_8) || \
+                             ((SIZE) == GDMA_Msize_16) || \
+                             ((SIZE) == GDMA_Msize_32) || \
+                             ((SIZE) == GDMA_Msize_64) || \
+                             ((SIZE) == GDMA_Msize_128) || \
+                             ((SIZE) == GDMA_Msize_256))
+
+/**
+ * \defgroup    GDMA_Data_Transfer_Direction GDMA Data Transfer Direction
+ * \{
+ * \ingroup     GDMA_Exported_Constants
+ */
+#define GDMA_DIR_MemoryToMemory             ((uint32_t)0x00000000)
+#define GDMA_DIR_MemoryToPeripheral         ((uint32_t)0x00000001)
+#define GDMA_DIR_PeripheralToMemory         ((uint32_t)0x00000002)
+#define GDMA_DIR_PeripheralToPeripheral     ((uint32_t)0x00000003)
+
+#define IS_GDMA_DIR(DIR) (((DIR) == GDMA_DIR_MemoryToMemory) || \
+                          ((DIR) == GDMA_DIR_MemoryToPeripheral) || \
+                          ((DIR) == GDMA_DIR_PeripheralToMemory) || \
+                          ((DIR) == GDMA_DIR_PeripheralToPeripheral))
+/** \} */
+
+/**
+ * \defgroup    GDMA_Source_Incremented_Mode GDMA Source Incremented Mode
+ * \{
+ * \ingroup     GDMA_Exported_Constants
+ */
+#define DMA_SourceInc_Inc                   ((uint32_t)0x00000000)
+#define DMA_SourceInc_Dec                   ((uint32_t)0x00000001)
+#define DMA_SourceInc_Fix                   ((uint32_t)0x00000002)
+
+#define IS_GDMA_SourceInc(STATE) (((STATE) == DMA_SourceInc_Inc) || \
+                                  ((STATE) == DMA_SourceInc_Dec) || \
+                                  ((STATE) == DMA_SourceInc_Fix))
+/** \} */
+
+/**
+ * \defgroup    GDMA_Destination_Incremented_Mode GDMA Destination Incremented Mode
+ * \{
+ * \ingroup     GDMA_Exported_Constants
+ */
+#define DMA_DestinationInc_Inc              ((uint32_t)0x00000000)
+#define DMA_DestinationInc_Dec              ((uint32_t)0x00000001)
+#define DMA_DestinationInc_Fix              ((uint32_t)0x00000002)
+
+#define IS_GDMA_DestinationInc(STATE) (((STATE) == DMA_DestinationInc_Inc) || \
+                                       ((STATE) == DMA_DestinationInc_Dec) || \
+                                       ((STATE) == DMA_DestinationInc_Fix))
+/** \} */
+
+/**
+ * \defgroup    GDMA_Interrupts_Definition GDMA Interrupts Definition
+ * \{
+ * \ingroup     GDMA_Exported_Constants
+ */
+#define GDMA_INT_Transfer                   ((uint32_t)0x00000001)
+#define GDMA_INT_Block                      ((uint32_t)0x00000002)
+#define GDMA_INT_SrcTransfer                ((uint32_t)0x00000004)
+#define GDMA_INT_DstTransfer                ((uint32_t)0x00000008)
+#define GDMA_INT_Error                      ((uint32_t)0x00000010)
+
+#define IS_GDMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFE00) == 0x00) && ((IT) != 0x00))
+/** \} */
+
+/**
+ * \defgroup    GDMA_Multiblock_Mode GDMA Multi-block Mode
+ * \{
+ * \ingroup     GDMA_Exported_Constants
+ */
+#define AUTO_RELOAD_WITH_CONTIGUOUS_SAR     (BIT31)
+#define AUTO_RELOAD_WITH_CONTIGUOUS_DAR     (BIT30)
+#define AUTO_RELOAD_TRANSFER                (BIT30 | BIT31)
+#define LLI_WITH_CONTIGUOUS_SAR             (BIT27)
+#define LLI_WITH_AUTO_RELOAD_SAR            (BIT27 | BIT30)
+#define LLI_WITH_CONTIGUOUS_DAR             (BIT28)
+#define LLI_WITH_AUTO_RELOAD_DAR            (BIT28 | BIT31)
+#define LLI_TRANSFER                        (BIT27 | BIT28)
+
+#define IS_GDMA_MULTIBLOCKMODE(MODE) (((MODE) == AUTO_RELOAD_WITH_CONTIGUOUS_SAR) || \
+                                      ((MODE) == AUTO_RELOAD_WITH_CONTIGUOUS_DAR) || \
+                                      ((MODE) == AUTO_RELOAD_TRANSFER) || \
+                                      ((MODE) == LLI_WITH_CONTIGUOUS_SAR) || \
+                                      ((MODE) == LLI_WITH_AUTO_RELOAD_SAR) || \
+                                      ((MODE) == LLI_WITH_CONTIGUOUS_DAR) || \
+                                      ((MODE) == LLI_WITH_AUTO_RELOAD_DAR) || \
+                                      ((MODE) == LLI_TRANSFER))
+/** \} */
+
+/**
+ * \defgroup    GDMA_Multiblock_Select_Bit GDMA Multiblock Select Bit
+ * \{
+ * \ingroup     GDMA_Exported_Constants
+ */
+#define AUTO_RELOAD_SELECTED_BIT            (uint32_t)(0xC0000000)
+#define LLP_SELECTED_BIT                    (uint32_t)(0x18000000)
+/** \} */
+
+/**
+ * \defgroup    GDMA_Suspend_Flag_Definition GDMA Suspend Flag Definition
+ * \{
+ * \ingroup     GDMA_Exported_Constants
+ */
+#define GDMA_FIFO_STATUS                    (BIT9)
+#define GDMA_SUSPEND_TRANSMISSSION          (BIT8)
+#define GDMA_SUSPEND_CMD_STATUS             (BIT2 | BIT1)
+#define GDMA_SUSPEND_CHANNEL_STATUS         (BIT0)
+/** \} */
+
+/** End of GDMA_Exported_Constants
+  * \}
+  */
+
+/*============================================================================*
+ *                         Functions
+ *============================================================================*/
+/**
+ * \defgroup    GDMA_Exported_Functions GDMA Exported Functions
+ * \{
+ * \ingroup     GDMA
+ */
+
+/**
+ * \brief  Deinitialize the GDMA registers to their default reset values.
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_gdma_init(void)
+ * {
+ *     GDMA_DeInit();
+ * }
+ * \endcode
+ */
+void GDMA_DeInit(void);
+
+/**
+ * \brief       Initialize the GDMA Channelx according to the specified parameters in the GDMA_InitStruct.
+ * \param[in]   GDMA_Channelx: Where x can be 0 to 3 to select the DMA Channel.
+ * \param[in]   GDMA_InitStruct: Pointer to a GDMA_InitTypeDef structure that contains the configuration information
+ *                               for the specified DMA Channel.
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_gdma_init(void)
+ * {
+ *
+ *     for (uint32_t i = 0; i < UART_TX_GDMA_BUFFER_SIZE; i++)
+ *     {
+ *         GDMA_SendData_Buffer[i] = 0x10 + i;
+ *     }
+
+ *     GDMA_InitTypeDef GDMA_InitStruct;
+ *     GDMA_StructInit(&GDMA_InitStruct);
+ *     GDMA_InitStruct.GDMA_ChannelNum      = 1;
+ *     GDMA_InitStruct.GDMA_DIR             = GDMA_DIR_MemoryToPeripheral;
+ *     GDMA_InitStruct.GDMA_BufferSize      = UART_TX_GDMA_BUFFER_SIZE; // determine total transfer size
+ *     GDMA_InitStruct.GDMA_SourceInc       = DMA_SourceInc_Inc;
+ *     GDMA_InitStruct.GDMA_DestinationInc  = DMA_DestinationInc_Fix;
+ *     GDMA_InitStruct.GDMA_SourceDataSize  = GDMA_DataSize_Byte;
+ *     GDMA_InitStruct.GDMA_DestinationDataSize = GDMA_DataSize_Byte;
+ *     GDMA_InitStruct.GDMA_SourceMsize     = GDMA_Msize_1;
+ *     GDMA_InitStruct.GDMA_DestinationMsize = GDMA_Msize_1;
+ *     GDMA_InitStruct.GDMA_SourceAddr      = (uint32_t)GDMA_SendData_Buffer;
+ *     GDMA_InitStruct.GDMA_DestinationAddr = (uint32_t)(&(UART0->RB_THR));
+ *     GDMA_InitStruct.GDMA_DestHandshake   = GDMA_Handshake_UART0_TX;
+ *     GDMA_InitStruct.GDMA_ChannelPriority = 2; // channel priority between 0 to 5
+ *     GDMA_Init(UART_TX_GDMA_CHANNEL, &GDMA_InitStruct);
+
+ *     GDMA_INTConfig(UART_TX_GDMA_CHANNEL_NUM, GDMA_INT_Transfer, ENABLE);
+
+ *     NVIC_InitTypeDef NVIC_InitStruct;
+ *     NVIC_InitStruct.NVIC_IRQChannel = UART_TX_GDMA_CHANNEL_IRQN;
+ *     NVIC_InitStruct.NVIC_IRQChannelPriority = 3;
+ *     NVIC_InitStruct.NVIC_IRQChannelCmd = ENABLE;
+ *     NVIC_Init(&NVIC_InitStruct);
+
+ *     GDMA_Cmd(UART_TX_GDMA_CHANNEL_NUM, ENABLE);
+ * }
+ * \endcode
+ */
+void GDMA_Init(GDMA_ChannelTypeDef *GDMA_Channelx, GDMA_InitTypeDef *GDMA_InitStruct);
+
+/**
+ * \brief  Fill each GDMA_InitStruct member with its default value.
+ * \param[in]  GDMA_InitStruct : Pointer to a GDMA_InitTypeDef structure which will be initialized.
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_gdma_init(void)
+ * {
+ *
+ *     for (uint32_t i = 0; i < UART_TX_GDMA_BUFFER_SIZE; i++)
+ *     {
+ *         GDMA_SendData_Buffer[i] = 0x10 + i;
+ *     }
+
+ *     GDMA_InitTypeDef GDMA_InitStruct;
+ *     GDMA_StructInit(&GDMA_InitStruct);
+ *     GDMA_InitStruct.GDMA_ChannelNum      = 1;
+ *     GDMA_InitStruct.GDMA_DIR             = GDMA_DIR_MemoryToPeripheral;
+ *     GDMA_InitStruct.GDMA_BufferSize      = UART_TX_GDMA_BUFFER_SIZE; // Determine total transfer size
+ *     GDMA_InitStruct.GDMA_SourceInc       = DMA_SourceInc_Inc;
+ *     GDMA_InitStruct.GDMA_DestinationInc  = DMA_DestinationInc_Fix;
+ *     GDMA_InitStruct.GDMA_SourceDataSize  = GDMA_DataSize_Byte;
+ *     GDMA_InitStruct.GDMA_DestinationDataSize = GDMA_DataSize_Byte;
+ *     GDMA_InitStruct.GDMA_SourceMsize      = GDMA_Msize_1;
+ *     GDMA_InitStruct.GDMA_DestinationMsize = GDMA_Msize_1;
+ *     GDMA_InitStruct.GDMA_SourceAddr      = (uint32_t)GDMA_SendData_Buffer;
+ *     GDMA_InitStruct.GDMA_DestinationAddr = (uint32_t)(&(UART0->RB_THR));
+ *     GDMA_InitStruct.GDMA_DestHandshake   = GDMA_Handshake_UART0_TX;
+ *     GDMA_InitStruct.GDMA_ChannelPriority = 2; // Channel priority between 0 to 5
+ *     GDMA_Init(UART_TX_GDMA_CHANNEL, &GDMA_InitStruct);
+ *
+ * }
+ * \endcode
+ */
+void GDMA_StructInit(GDMA_InitTypeDef *GDMA_InitStruct);
+
+/**
+ * \brief       Enable or disable the specified GDMA channel.
+ * \param[in]   GDMA_Channel_Num: GDMA channel number, can be 0 to 3.
+ * \param[in]   NewState: New state of the selected DMA channel.
+ *                       This parameter can be: ENABLE or DISABLE.
+ * \return      None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_gdma_init(void)
+ * {
+ *
+ *     for (uint32_t i = 0; i < UART_TX_GDMA_BUFFER_SIZE; i++)
+ *     {
+ *         GDMA_SendData_Buffer[i] = 0x10 + i;
+ *     }
+
+ *     GDMA_InitTypeDef GDMA_InitStruct;
+ *     GDMA_StructInit(&GDMA_InitStruct);
+ *     GDMA_InitStruct.GDMA_ChannelNum      = 1;
+ *     GDMA_InitStruct.GDMA_DIR             = GDMA_DIR_MemoryToPeripheral;
+ *     GDMA_InitStruct.GDMA_BufferSize      = UART_TX_GDMA_BUFFER_SIZE; // Determine total transfer size
+ *     GDMA_InitStruct.GDMA_SourceInc       = DMA_SourceInc_Inc;
+ *     GDMA_InitStruct.GDMA_DestinationInc  = DMA_DestinationInc_Fix;
+ *     GDMA_InitStruct.GDMA_SourceDataSize  = GDMA_DataSize_Byte;
+ *     GDMA_InitStruct.GDMA_DestinationDataSize = GDMA_DataSize_Byte;
+ *     GDMA_InitStruct.GDMA_SourceMsize      = GDMA_Msize_1;
+ *     GDMA_InitStruct.GDMA_DestinationMsize = GDMA_Msize_1;
+ *     GDMA_InitStruct.GDMA_SourceAddr      = (uint32_t)GDMA_SendData_Buffer;
+ *     GDMA_InitStruct.GDMA_DestinationAddr = (uint32_t)(&(UART0->RB_THR));
+ *     GDMA_InitStruct.GDMA_DestHandshake   = GDMA_Handshake_UART0_TX;
+ *     GDMA_InitStruct.GDMA_ChannelPriority = 2; // Channel priority between 0 to 5
+ *     GDMA_Init(UART_TX_GDMA_CHANNEL, &GDMA_InitStruct);
+
+ *     GDMA_INTConfig(UART_TX_GDMA_CHANNEL_NUM, GDMA_INT_Transfer, ENABLE);
+
+ *     NVIC_InitTypeDef NVIC_InitStruct;
+ *     NVIC_InitStruct.NVIC_IRQChannel = UART_TX_GDMA_CHANNEL_IRQN;
+ *     NVIC_InitStruct.NVIC_IRQChannelPriority = 3;
+ *     NVIC_InitStruct.NVIC_IRQChannelCmd = ENABLE;
+ *     NVIC_Init(&NVIC_InitStruct);
+
+ *     GDMA_Cmd(UART_TX_GDMA_CHANNEL_NUM, ENABLE);
+ * }
+ * \endcode
+ */
+void GDMA_Cmd(uint8_t GDMA_Channel_Num, FunctionalState NewState);
+
+/**
+ * \brief       Enable or disable the specified DMA channel interrupt source.
+ * \param[in]   GDMA_Channel_Num: GDMA channel number, can be 0 to 3.
+ * \param[in]   GDMA_IT: Specify the GDMA interrupt source to be enabled or disabled.
+ *                       This parameter can be any combination of the following values, which refer to \ref GDMA_Interrupts_Definition.
+ *                       \arg GDMA_INT_Transfer: Transfer complete interrupt source.
+ *                       \arg GDMA_INT_Block: Block transfer interrupt source.
+ *                       \arg GDMA_INT_SrcTransfer: Source Transfer interrupt source.
+ *                       \arg GDMA_INT_DstTransfer: Destination Transfer interrupt source.
+ *                       \arg GDMA_INT_Error: Transfer error interrupt source.
+ * \param[in]   NewState: New state of the specified DMA interrupt source.
+ *                       This parameter can be: ENABLE or DISABLE.
+ * \return      None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_gdma_init(void)
+ * {
+ *
+ *     for (uint32_t i = 0; i < UART_TX_GDMA_BUFFER_SIZE; i++)
+ *     {
+ *         GDMA_SendData_Buffer[i] = 0x10 + i;
+ *     }
+
+ *     GDMA_InitTypeDef GDMA_InitStruct;
+ *     GDMA_StructInit(&GDMA_InitStruct);
+ *     GDMA_InitStruct.GDMA_ChannelNum      = 1;
+ *     GDMA_InitStruct.GDMA_DIR             = GDMA_DIR_MemoryToPeripheral;
+ *     GDMA_InitStruct.GDMA_BufferSize      = UART_TX_GDMA_BUFFER_SIZE; // Determine total transfer size
+ *     GDMA_InitStruct.GDMA_SourceInc       = DMA_SourceInc_Inc;
+ *     GDMA_InitStruct.GDMA_DestinationInc  = DMA_DestinationInc_Fix;
+ *     GDMA_InitStruct.GDMA_SourceDataSize  = GDMA_DataSize_Byte;
+ *     GDMA_InitStruct.GDMA_DestinationDataSize = GDMA_DataSize_Byte;
+ *     GDMA_InitStruct.GDMA_SourceMsize     = GDMA_Msize_1;
+ *     GDMA_InitStruct.GDMA_DestinationMsize = GDMA_Msize_1;
+ *     GDMA_InitStruct.GDMA_SourceAddr      = (uint32_t)GDMA_SendData_Buffer;
+ *     GDMA_InitStruct.GDMA_DestinationAddr = (uint32_t)(&(UART0->RB_THR));
+ *     GDMA_InitStruct.GDMA_DestHandshake   = GDMA_Handshake_UART0_TX;
+ *     GDMA_InitStruct.GDMA_ChannelPriority = 2; // Channel priority between 0 to 5
+ *     GDMA_Init(UART_TX_GDMA_CHANNEL, &GDMA_InitStruct);
+
+ *     GDMA_INTConfig(UART_TX_GDMA_CHANNEL_NUM, GDMA_INT_Transfer, ENABLE);
+
+ *     NVIC_InitTypeDef NVIC_InitStruct;
+ *     NVIC_InitStruct.NVIC_IRQChannel = UART_TX_GDMA_CHANNEL_IRQN;
+ *     NVIC_InitStruct.NVIC_IRQChannelPriority = 3;
+ *     NVIC_InitStruct.NVIC_IRQChannelCmd = ENABLE;
+ *     NVIC_Init(&NVIC_InitStruct);
+
+ *     GDMA_Cmd(UART_TX_GDMA_CHANNEL_NUM, ENABLE);
+ * }
+ * \endcode
+ */
+void GDMA_INTConfig(uint8_t GDMA_Channel_Num, uint32_t GDMA_IT, FunctionalState NewState);
+
+/**
+ * \brief       Clear the specified DMA channel interrupt pending bit.
+ * \param[in]   GDMA_Channel_Num: GDMA channel number, can be 0 to 3.
+ * \param[in]   GDMA_IT: Specify the GDMA interrupts sources to be enabled or disabled.
+ *                       This parameter can be any combination of the following values, which refer to \ref GDMA_Interrupts_Definition.
+ *                       \arg GDMA_INT_Transfer: Transfer complete interrupt source.
+ *                       \arg GDMA_INT_Block: Block transfer interrupt source.
+ *                       \arg GDMA_INT_SrcTransfer: Source Transfer interrupt source.
+ *                       \arg GDMA_INT_DstTransfer: Destination Transfer interrupt source.
+ *                       \arg GDMA_INT_Error: Transfer error interrupt source.
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void gdma_demo(void)
+ * {
+ *     driver_gdma_init();
+ * }
+ *
+ * void UART_TX_GDMA_Handler(void)
+ * {
+ *     GDMA_ClearINTPendingBit(1, GDMA_INT_Transfer);
+ *     // Add user code here.
+ * }
+ * \endcode
+ */
+void GDMA_ClearINTPendingBit(uint8_t GDMA_Channel_Num, uint32_t GDMA_IT);
+
+/**
+ * \brief       Get the specified DMA channel status.
+ * \param[in]   GDMA_Channel_Num: GDMA channel number, can be 0 to 3.
+ * \return      GDMA channel status (SET or RESET).
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void gdma_demo(void)
+ * {
+ *     FlagStatus flag_status = GDMA_GetChannelStatus(0);
+ * }
+ * \endcode
+ */
+__STATIC_INLINE FlagStatus GDMA_GetChannelStatus(uint8_t GDMA_Channel_Num)
+{
+    FlagStatus bit_status = RESET;
+
+    /* Check the parameters */
+    assert_param(IS_GDMA_ChannelNum(GDMA_Channel_Num));
+
+    if ((GDMA_BASE->ChEnReg & BIT(GDMA_Channel_Num)) != (uint32_t)RESET)
+    {
+
+        bit_status = SET;
+    }
+
+    /* Return the selected channel status */
+    return bit_status;
+}
+
+/**
+ * \brief       Check whether the specified DMA channel transfer interrupt is set.
+ * \param[in]   GDMA_Channel_Num: GDMA channel number, can be 0 to 3.
+ * \return      Transfer interrupt status, SET or RESET.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void gdma_demo(void)
+ * {
+ *     ITStatus int_status = GDMA_GetTransferINTStatus(0);
+ * }
+ * \endcode
+ */
+__STATIC_INLINE ITStatus GDMA_GetTransferINTStatus(uint8_t GDMA_Channel_Num)
+{
+    ITStatus bit_status = RESET;
+
+    /* Check the parameters */
+    assert_param(IS_GDMA_ChannelNum(GDMA_Channel_Num));
+
+    if ((GDMA_BASE->STATUS_TFR & BIT(GDMA_Channel_Num)) != (uint32_t)RESET)
+    {
+        bit_status = SET;
+    }
+
+    /* Return the transfer interrupt status */
+    return bit_status;
+}
+
+/**
+ * \brief       Clear the specified DMA channel all interrupts.
+ * \param[in]   GDMA_Channel_Num: GDMA channel number, can be 0 to 3.
+ * \return      None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void gdma_demo(void)
+ * {
+ *     GDMA_ClearAllTypeINT(0);
+ * }
+ * \endcode
+ */
+__STATIC_INLINE void GDMA_ClearAllTypeINT(uint8_t GDMA_Channel_Num)
+{
+    /* Check the parameters */
+    assert_param(IS_GDMA_ChannelNum(GDMA_Channel_Num));
+
+    GDMA_BASE->CLEAR_TFR = BIT(GDMA_Channel_Num);
+    GDMA_BASE->CLEAR_BLOCK = BIT(GDMA_Channel_Num);
+    GDMA_BASE->CLEAR_DST_TRAN = BIT(GDMA_Channel_Num);
+    GDMA_BASE->CLEAR_SRC_TRAN = BIT(GDMA_Channel_Num);
+    GDMA_BASE->CLEAR_ERR = BIT(GDMA_Channel_Num);
+}
+
+/**
+ * \brief       Set GDMA transmission source address.
+ * \param[in]   GDMA_Channelx: Where x can be 0 to 3 to select the DMA channel.
+ * \param[in]   Address: Source address.
+ * \return      None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void gdma_demo(void)
+ * {
+ *     uint32_t data_buf[10] = {0};
+ *     GDMA_SetSourceAddress(GDMA_Channel0, (uint32_t)data_buf);
+ * }
+ * \endcode
+ */
+__STATIC_INLINE void GDMA_SetSourceAddress(GDMA_ChannelTypeDef *GDMA_Channelx, uint32_t Address)
+{
+    /* Check the parameters */
+    assert_param(IS_GDMA_ALL_PERIPH(GDMA_Channelx));
+
+    GDMA_Channelx->SAR = Address;
+}
+
+/**
+ * \brief       Set GDMA transmission destination address.
+ * \param[in]   GDMA_Channelx: Where x can be 0 to 3 to select the GDMA channel.
+ * \param[in]   Address: Destination address.
+ * \return      None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void gdma_demo(void)
+ * {
+ *     uint32_t data_buf[10] = {0};
+ *     GDMA_SetDestinationAddress(GDMA_Channel0, (uint32_t)data_buf);
+ * }
+ * \endcode
+ */
+__STATIC_INLINE void GDMA_SetDestinationAddress(GDMA_ChannelTypeDef *GDMA_Channelx,
+                                                uint32_t Address)
+{
+    /* Check the parameters */
+    assert_param(IS_GDMA_ALL_PERIPH(GDMA_Channelx));
+
+    GDMA_Channelx->DAR = Address;
+}
+
+/**
+ * \brief       Set GDMA buffer size.
+ * \param[in]   GDMA_Channelx: Where x can be 0 to 3 to select the GDMA channel.
+ * \param[in]   buffer_size: Set GDMA_BufferSize.
+ * \return      None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void gdma_demo(void)
+ * {
+ *     uint32_t data_buf_size = 65535; // Max
+ *     GDMA_SetBufferSize(GDMA_Channel0, data_buf_size);
+ * }
+ * \endcode
+ */
+__STATIC_INLINE void GDMA_SetBufferSize(GDMA_ChannelTypeDef *GDMA_Channelx, uint32_t buffer_size)
+{
+    /* Check the parameters */
+    assert_param(IS_GDMA_ALL_PERIPH(GDMA_Channelx));
+
+    /* Configure high 32 bits of CTL register */
+    GDMA_Channelx->CTL_HIGH = buffer_size;
+}
+
+/**
+ * \brief       Suspend GDMA transmission from the source.
+ * \param[in]   GDMA_Channelx: Where x can be 0 to 3 to select the GDMA channel.
+ * \param[in]   NewState: New state of the DMA channel.
+ *                       This parameter can be: ENABLE or DISABLE.
+ * \return      None.
+ * \note        To prevent data loss, it is necessary to check whether FIFO data transmission is completed
+ *              after suspending, which can be determined by checking whether the GDMA FIFO is empty.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void gdma_demo(void)
+ * {
+ *     GDMA_SuspendCmd(GDMA_Channel0, ENABLE);
+ * }
+ * \endcode
+ */
+__STATIC_INLINE void GDMA_SuspendCmd(GDMA_ChannelTypeDef *GDMA_Channelx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_GDMA_ALL_PERIPH(GDMA_Channelx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (NewState == DISABLE)
+    {
+        /* Do not suspend transmission*/
+        GDMA_Channelx->CFG_LOW &= ~(GDMA_SUSPEND_TRANSMISSSION);
+    }
+    else
+    {
+        /* Suspend transmission */
+        GDMA_Channelx->CFG_LOW |= GDMA_SUSPEND_TRANSMISSSION;
+    }
+}
+
+/**
+ * \brief       Get GDMA transfer data length.
+ * \param[in]   GDMA_Channelx: Where x can be 0 to 3 to select the GDMA channel.
+ * \return      GDMA transfer data length.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void gdma_demo(void)
+ * {
+ *     uint16_t data_len = GDMA_GetTransferLen(GDMA_Channel0);
+ * }
+ * \endcode
+ */
+__STATIC_INLINE uint16_t GDMA_GetTransferLen(GDMA_ChannelTypeDef *GDMA_Channelx)
+{
+    /* Check the parameters */
+    assert_param(IS_GDMA_ALL_PERIPH(GDMA_Channelx));
+
+    return (uint16_t)(GDMA_Channelx->CTL_HIGH & 0xFFFF);
+}
+
+/**
+ * \brief       Set GDMA LLP structure address.
+ * \param[in]   GDMA_Channelx: Where x can be 0 to 3 to select the GDMA channel.
+ * \param[in]   Address: LLP structure address.
+ * \return      None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void gdma_demo(void)
+ * {
+ *     GDMA_LLIDef GDMA_LLIStruct[4000];
+ *     GDMA_SetLLPAddress(GDMA_Channel0, (uint32_t)GDMA_LLIStruct);
+ * }
+ * \endcode
+ */
+__STATIC_INLINE void GDMA_SetLLPAddress(GDMA_ChannelTypeDef *GDMA_Channelx, uint32_t Address)
+{
+    /* Check the parameters */
+    assert_param(IS_GDMA_ALL_PERIPH(GDMA_Channelx));
+
+    if ((GDMA_Channelx == GDMA_Channel0) | (GDMA_Channelx == GDMA_Channel1) | \
+        (GDMA_Channelx == GDMA_Channel2) | (GDMA_Channelx == GDMA_Channel3))
+    {
+        GDMA_Channelx->LLP = Address;
+    }
+}
+
+/**
+ * \brief       Check GDMA suspend channel status.
+ * \param[in]   GDMA_Channelx: Where x can be 0 to 3 to select the GDMA channel.
+ * \return      GDMA suspend channel status, SET(Inactive) or RESET(Active).
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void gdma_demo(void)
+ * {
+ *     FlagStatus flag_status = GDMA_GetSuspendChannelStatus(GDMA_Channel0);
+ * }
+ * \endcode
+ */
+__STATIC_INLINE FlagStatus GDMA_GetSuspendChannelStatus(GDMA_ChannelTypeDef *GDMA_Channelx)
+{
+    FlagStatus bit_status = RESET;
+
+    /* Check the parameters */
+    assert_param(IS_GDMA_ALL_PERIPH(GDMA_Channelx));
+
+    if ((GDMA_Channelx->CFG_LOW & GDMA_SUSPEND_CHANNEL_STATUS) == GDMA_SUSPEND_CHANNEL_STATUS)
+    {
+        bit_status = SET;
+    }
+
+    /* Return the selected channel suspend status */
+    return bit_status;
+}
+
+/**
+ * \brief  Check the status of GDMA suspend command.
+ * \param[in]  GDMA_Channelx: Where x can be 0 to 3 to select the GDMA Channel.
+ * \return GDMA suspend command status, SET(Suspended) or RESET(Not suspended).
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void gdma_demo(void)
+ * {
+ *     FlagStatus flag_status = GDMA_GetSuspendCmdStatus(GDMA_Channel0);
+ * }
+ * \endcode
+ */
+__STATIC_INLINE FlagStatus GDMA_GetSuspendCmdStatus(GDMA_ChannelTypeDef *GDMA_Channelx)
+{
+    FlagStatus bit_status = RESET;
+
+    /* Check the parameters */
+    assert_param(IS_GDMA_ALL_PERIPH(GDMA_Channelx));
+
+    if ((GDMA_Channelx->CFG_LOW & GDMA_SUSPEND_CMD_STATUS) == GDMA_SUSPEND_CMD_STATUS)
+    {
+        bit_status = SET;
+    }
+
+    /* Return the selected channel suspend status */
+    return bit_status;
+}
+
+/**
+ * \brief       Check the status of GDMA FIFO.
+ * \param[in]   GDMA_Channelx: Where x can be 0 to 3 to select the GDMA Channel.
+ * \return      GDMA FIFO status, SET (FIFO empty) or RESET (FIFO not empty).
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void gdma_demo(void)
+ * {
+ *     FlagStatus flag_status = GDMA_GetFIFOStatus(GDMA_Channel0);
+ * }
+ * \endcode
+ */
+__STATIC_INLINE FlagStatus GDMA_GetFIFOStatus(GDMA_ChannelTypeDef *GDMA_Channelx)
+{
+    FlagStatus bit_status = RESET;
+
+    /* Check the parameters */
+    assert_param(IS_GDMA_ALL_PERIPH(GDMA_Channelx));
+
+    if ((GDMA_Channelx->CFG_LOW & GDMA_FIFO_STATUS) != (uint32_t)RESET)
+    {
+        bit_status = SET;
+    }
+
+    /* Return the selected channel FIFO status */
+    return bit_status;
+}
+
+/**
+ * \brief       Get GDMA source address.
+ * \param[in]   GDMA_Channelx: Where x can be 0 to 3 to select the GDMA Channel.
+ * \return      Source address.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void gdma_demo(void)
+ * {
+ *     uint32_t address = GDMA_GetSrcTransferAddress(GDMA_Channel0);
+ * }
+ * \endcode
+ */
+__STATIC_INLINE uint32_t GDMA_GetSrcTransferAddress(GDMA_ChannelTypeDef *GDMA_Channelx)
+{
+    /* Check the parameters */
+    assert_param(IS_GDMA_ALL_PERIPH(GDMA_Channelx));
+
+    uint32_t address = GDMA_Channelx->SAR;
+    return address;
+}
+
+/**
+ * \brief       Get GDMA destination address.
+ * \param[in]   GDMA_Channelx: Where x can be 0 to 3 to select the GDMA Channel.
+ * \return      Destination address.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void gdma_demo(void)
+ * {
+ *     uint32_t address = GDMA_GetDstTransferAddress(GDMA_Channel0);
+ * }
+ * \endcode
+ */
+__STATIC_INLINE uint32_t GDMA_GetDstTransferAddress(GDMA_ChannelTypeDef *GDMA_Channelx)
+{
+    /* Check the parameters */
+    assert_param(IS_GDMA_ALL_PERIPH(GDMA_Channelx));
+
+    uint32_t address = GDMA_Channelx->DAR;
+    return address;
+}
+
+/** End of GDMA_Exported_Functions
+  * \}
+  */
+
+/** End of GDMA
+  * \}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTL8762X_GDMA_H_ */
diff --git a/bee/drivers/dma/src/device/rtl87x2g/rtl87x2g_gdma.c b/bee/drivers/dma/src/device/rtl87x2g/rtl87x2g_gdma.c
new file mode 100644
index 00000000..b6344540
--- /dev/null
+++ b/bee/drivers/dma/src/device/rtl87x2g/rtl87x2g_gdma.c
@@ -0,0 +1,84 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *                        Header Files
+ *============================================================================*/
+#include "rtl_gdma.h"
+
+/*============================================================================*
+ *                           Public Functions
+ *============================================================================*/
+GDMA_TypeDef *GDMA_GetGDMAx(GDMA_ChannelTypeDef *GDMA_Channelx)
+{
+    /* Check the parameters */
+    assert_param(IS_GDMA_ALL_PERIPH(GDMA_Channelx));
+
+    GDMA_TypeDef *GDMAx = GDMA0;
+
+    return GDMAx;
+}
+
+GDMA_TypeDef *GDMA_GetGDMAxByCh(uint8_t GDMA_ChannelNum)
+{
+    /* Check the parameters */
+    assert_param(IS_GDMA_ChannelNum(GDMA_ChannelNum));
+
+    GDMA_TypeDef *GDMAx = GDMA0;
+
+    return GDMAx;
+}
+
+uint8_t GDMA_GetGDMAChannelNum(uint8_t GDMA_ChannelNum)
+{
+    /* Check the parameters */
+    assert_param(IS_GDMA_ChannelNum(GDMA_ChannelNum));
+
+    return GDMA_ChannelNum;
+}
+
+uint8_t GDMA_GetHandshakeNum(GDMA_ChannelTypeDef *GDMA_Channelx, uint8_t handshake)
+{
+    /* Check the parameters */
+    assert_param(IS_GDMA_ALL_PERIPH(GDMA_Channelx));
+
+    return handshake;
+}
+
+GDMA_ChannelTypeDef *GDMA_GetGDMAChannelx(uint8_t GDMA_ChannelNum)
+{
+    /* Check the parameters */
+    assert_param(IS_GDMA_ChannelNum(GDMA_ChannelNum));
+
+    GDMA_ChannelTypeDef *GDMA_Channelx = (GDMA_ChannelTypeDef *)(GDMA0_CHANNEL_REG_BASE +
+                                                                 GDMA_ChannelNum * 0x0058);;
+    if (GDMA_ChannelNum < 8)
+    {
+        GDMA_Channelx = (GDMA_ChannelTypeDef *)(GDMA0_CHANNEL_REG_BASE + GDMA_ChannelNum * 0x0058);
+    }
+    else
+    {
+        GDMA_Channelx = (GDMA_ChannelTypeDef *)(GDMA0_CHANNEL_REG_BASE + 0x0400 +
+                                                (GDMA_ChannelNum - 8) * 0x0058);
+    }
+
+    return GDMA_Channelx;
+}
+
+bool GDMA_IsValidHandshake(uint8_t handshake)
+{
+    return true;
+}
+
+bool GDMA_IsGatherScatterChannel(GDMA_ChannelTypeDef *GDMA_Channelx)
+{
+    return false;
+}
+
+bool GDMA_IsHalfBlcokChannel(GDMA_TypeDef *GDMAx)
+{
+    return false;
+}
diff --git a/bee/drivers/dma/src/device/rtl87x2g/rtl_gdma.c b/bee/drivers/dma/src/device/rtl87x2g/rtl_gdma.c
new file mode 100644
index 00000000..0bbcb2f5
--- /dev/null
+++ b/bee/drivers/dma/src/device/rtl87x2g/rtl_gdma.c
@@ -0,0 +1,855 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *                        Header Files
+ *============================================================================*/
+#include "rtl_gdma.h"
+#include "rtl_rcc.h"
+
+/*============================================================================*
+ *                        Private Defines
+ *============================================================================*/
+#define CHANNEL_BIT(ch)    ((ch < 8) ? BIT(ch) : BIT(ch + 8))
+#define CHANNEL_WE_BIT(ch) ((ch < 8) ? BIT(ch + 8) : BIT(ch + 16))
+
+/*============================================================================*
+ *                        Private Functions
+ *============================================================================*/
+extern uint8_t GDMA_GetHandshakeNum(GDMA_ChannelTypeDef *GDMA_Channelx, uint8_t handshake);
+extern uint8_t GDMA_GetGDMAChannelNum(uint8_t GDMA_ChannelNum);
+extern GDMA_TypeDef *GDMA_GetGDMAxByCh(uint8_t GDMA_ChannelNum);
+extern GDMA_TypeDef *GDMA_GetGDMAx(GDMA_ChannelTypeDef *GDMA_Channelx);
+extern bool GDMA_IsValidHandshake(uint8_t handshake);
+extern bool GDMA_IsGatherScatterChannel(GDMA_ChannelTypeDef *GDMA_Channelx);
+extern bool GDMA_IsHalfBlcokChannel(GDMA_TypeDef *GDMAx);
+FlagStatus GDMA_GetSuspendCmdStatus(GDMA_ChannelTypeDef *GDMA_Channelx);
+FlagStatus GDMA_GetSuspendChannelStatus(GDMA_ChannelTypeDef *GDMA_Channelx);
+
+/*============================================================================*
+ *                        Public Functions
+ *============================================================================*/
+/**
+  * \brief  Deinitializes the GDMA registers to their default reset values.
+  * \param  None
+  * \return None
+  */
+void GDMA_DeInit(void)
+{
+    /* Disable GDMA clock */
+#ifdef IS_GDMA_PERIPH
+    RCC_PeriphClockCmd(APBPeriph_GDMA, APBPeriph_GDMA_CLOCK, DISABLE);
+#endif
+#ifdef IS_GDMA1_PERIPH
+    RCC_PeriphClockCmd(APBPeriph_GDMA1, APBPeriph_GDMA1_CLOCK, DISABLE);
+#endif
+#ifdef IS_GDMA2_PERIPH
+    RCC_PeriphClockCmd(APBPeriph_GDMA2, APBPeriph_GDMA2_CLOCK, DISABLE);
+#endif
+}
+
+/**
+  * \brief  Initializes the GDMA Channelx according to the specified
+  *         parameters in the GDMA_InitStruct.
+  * \param  GDMA_Channelx: Select the GDMA peripheral. \ref GDMA_Declaration
+  * \param  GDMA_InitStruct: pointer to a GDMA_InitTypeDef structure that
+  *         contains the configuration information for the specified DMA Channel.
+  * \return None.
+  */
+void GDMA_Init(GDMA_ChannelTypeDef *GDMA_Channelx, GDMA_InitTypeDef *GDMA_InitStruct)
+{
+    /* Check the parameters */
+    assert_param(IS_GDMA_ALL_PERIPH(GDMA_Channelx));
+    assert_param(IS_GDMAx_ChannelNum(GDMA_InitStruct->GDMA_ChannelNum));
+    assert_param(IS_GDMA_DIR(GDMA_InitStruct->GDMA_DIR));
+    assert_param(IS_GDMA_SourceInc(GDMA_InitStruct->GDMA_SourceInc));
+    assert_param(IS_GDMA_DestinationInc(GDMA_InitStruct->GDMA_DestinationInc));
+    assert_param(IS_GDMA_DATA_SIZE(GDMA_InitStruct->GDMA_SourceDataSize));
+    assert_param(IS_GDMA_DATA_SIZE(GDMA_InitStruct->GDMA_DestinationDataSize));
+
+    GDMA_TypeDef *GDMAx = GDMA_GetGDMAx(GDMA_Channelx);
+    uint8_t channel_num = GDMA_GetGDMAChannelNum(GDMA_InitStruct->GDMA_ChannelNum);
+    uint8_t temp_hs_src = GDMA_GetHandshakeNum(GDMA_Channelx, GDMA_InitStruct->GDMA_SourceHandshake);
+    uint8_t temp_hs_dst = GDMA_GetHandshakeNum(GDMA_Channelx, GDMA_InitStruct->GDMA_DestHandshake);
+
+    /* ---------------- Configure source and destination address of GDMA ---------------- */
+    /* Program SARx register to set source address */
+    GDMA_Channelx->GDMA_SARx = GDMA_InitStruct->GDMA_SourceAddr;
+    /* Program DARx register to set destination address */
+    GDMA_Channelx->GDMA_DARx = GDMA_InitStruct->GDMA_DestinationAddr;
+
+    /* Enable GDMA in DmaCfgReg */
+    GDMAx->GDMA_DMACFGREG_L = 0x01;
+
+    /* ---------------- GDMA Configuration ---------------- */
+    /* Clear pending interrupts of corresponding GDMA channel */
+    uint32_t temp_bit = BIT(channel_num);
+    GDMAx->GDMA_CLEARTFR_L = temp_bit;
+    GDMAx->GDMA_CLEARBLOCK_L = temp_bit;
+#if (GDMA_SUPPORT_INT_HAIF_BLOCK == 1)
+    GDMAx->GDMA_CLEARBLOCK_H = temp_bit;
+#endif
+    GDMAx->GDMA_CLEARERR_L = temp_bit;
+
+    /* Mask pending interrupts of corresponding GDMA channel */
+    temp_bit = CHANNEL_WE_BIT(channel_num);
+    GDMAx->GDMA_MASKTFR_L = temp_bit;
+    GDMAx->GDMA_MASKBLOCK_L = temp_bit;
+#if (GDMA_SUPPORT_INT_HAIF_BLOCK == 1)
+    GDMAx->GDMA_MASKBLOCK_H = temp_bit;
+#endif
+    GDMAx->GDMA_MASKERR_L = temp_bit;
+
+    /* ---------------- Configure CTL register ---------------- */
+    /* Config low 32 bits of CTL register  */
+    GDMA_CTLx_L_TypeDef gdma_ctlxl = {.d32 = GDMA_Channelx->GDMA_CTLx_L};
+    gdma_ctlxl.b.int_en = ENABLE;
+    gdma_ctlxl.b.dst_tr_width = GDMA_InitStruct->GDMA_DestinationDataSize;
+    gdma_ctlxl.b.src_tr_width = GDMA_InitStruct->GDMA_SourceDataSize;
+    gdma_ctlxl.b.dinc = GDMA_InitStruct->GDMA_DestinationInc;
+    gdma_ctlxl.b.sinc = GDMA_InitStruct->GDMA_SourceInc;
+    gdma_ctlxl.b.dest_msize = GDMA_InitStruct->GDMA_DestinationMsize;
+    gdma_ctlxl.b.src_msize = GDMA_InitStruct->GDMA_SourceMsize;
+    gdma_ctlxl.b.tt_fc = GDMA_InitStruct->GDMA_DIR;
+    GDMA_Channelx->GDMA_CTLx_L = gdma_ctlxl.d32;
+
+    /* Config high 32 bits of CTL register */
+    GDMA_Channelx->GDMA_CTLx_H = GDMA_InitStruct->GDMA_BufferSize;
+
+    /* ---------------- Configure CFG register ---------------- */
+    GDMA_CFGx_L_TypeDef gdma_cfgxl = {.d32 = GDMA_Channelx->GDMA_CFGx_L};
+    switch (GDMA_InitStruct->GDMA_DIR)
+    {
+    case GDMA_DIR_MemoryToMemory:
+        gdma_cfgxl.b.hs_sel_dst = 0x1;
+        gdma_cfgxl.b.hs_sel_src = 0x1;
+        break;
+    case GDMA_DIR_MemoryToPeripheral:
+        gdma_cfgxl.b.hs_sel_dst = 0x0;
+        gdma_cfgxl.b.hs_sel_src = 0x1;
+        break;
+    case GDMA_DIR_PeripheralToMemory:
+        gdma_cfgxl.b.hs_sel_dst = 0x1;
+        gdma_cfgxl.b.hs_sel_src = 0x0;
+        break;
+    case GDMA_DIR_PeripheralToPeripheral:
+        gdma_cfgxl.b.hs_sel_dst = 0x0;
+        gdma_cfgxl.b.hs_sel_src = 0x0;
+        break;
+    default:
+        gdma_cfgxl.b.hs_sel_dst = 0x0;
+        gdma_cfgxl.b.hs_sel_src = 0x0;
+        break;
+    }
+    GDMA_Channelx->GDMA_CFGx_L = gdma_cfgxl.d32;
+
+    /* Set for secure mode */
+    GDMA_CFGx_H_TypeDef gdma_cfgxh = {.d32 = GDMA_Channelx->GDMA_CFGx_H};
+
+#if (GDMA_SUPPORT_SECURE_MODE == 1)
+    if (GDMA_InitStruct->GDMA_Secure_En == 1)
+    {
+        gdma_cfgxh.b.protctl = 0x0;
+    }
+    GDMA_Channelx->GDMA_CFGx_H = gdma_cfgxh.d32;
+#endif
+
+    /* Config multi-block mode */
+    if (GDMA_InitStruct->GDMA_Multi_Block_En == 1)
+    {
+        if (GDMA_InitStruct->GDMA_Multi_Block_Mode & LLP_SELECTED_BIT)
+        {
+            GDMA_Channelx->GDMA_LLPx_L = GDMA_InitStruct->GDMA_Multi_Block_Struct;
+            gdma_ctlxl.b.llp_dst_en = (GDMA_InitStruct->GDMA_Multi_Block_Mode & BIT27) >> 27;
+            gdma_ctlxl.b.llp_src_en = (GDMA_InitStruct->GDMA_Multi_Block_Mode & BIT28) >> 28;
+            GDMA_Channelx->GDMA_CTLx_L = gdma_ctlxl.d32;
+        }
+        gdma_cfgxl.b.reload_src = (GDMA_InitStruct->GDMA_Multi_Block_Mode & BIT30) >> 30;
+        gdma_cfgxl.b.reload_dst = (GDMA_InitStruct->GDMA_Multi_Block_Mode & BIT31) >> 31;
+        GDMA_Channelx->GDMA_CFGx_L = gdma_cfgxl.d32;
+    }
+    else
+    {
+        /* Clear automatic source/destination reload */
+        gdma_cfgxl.b.reload_src = 0x0;
+        gdma_cfgxl.b.reload_dst = 0x0;
+        GDMA_Channelx->GDMA_CFGx_L = gdma_cfgxl.d32;
+        /* Clear LLI for source/destination */
+        gdma_ctlxl.b.llp_dst_en = 0x0;
+        gdma_ctlxl.b.llp_src_en = 0x0;
+        GDMA_Channelx->GDMA_CTLx_L = gdma_ctlxl.d32;
+    }
+
+    /* ---------------- Set handshake ---------------- */
+    /* Configure peripheral parameters and configure source or destination hardware handshaking interface */
+    if (GDMA_IsValidHandshake(temp_hs_src) == true)
+    {
+        gdma_cfgxh.b.src_per = temp_hs_src & 0x0F;
+        gdma_cfgxh.b.extended_src_per1 = (temp_hs_src & 0x10) >> 4;
+        gdma_cfgxh.b.extended_src_per2 = (temp_hs_src & 0x20) >> 5;
+        gdma_cfgxh.b.extended_src_per3 = (temp_hs_src & 0x40) >> 6;
+
+        gdma_cfgxh.b.dest_per = temp_hs_dst & 0x0F;
+        gdma_cfgxh.b.extended_dest_per1 = (temp_hs_dst & 0x10) >> 4;
+        gdma_cfgxh.b.extended_dest_per2 = (temp_hs_dst & 0x20) >> 5;
+        gdma_cfgxh.b.extended_dest_per3 = (temp_hs_dst & 0x40) >> 6;
+
+        GDMA_Channelx->GDMA_CFGx_H = gdma_cfgxh.d32;
+    }
+
+    /* Set DMA channel priority level */
+    gdma_cfgxl.b.ch_prior = GDMA_InitStruct->GDMA_ChannelPriority;
+    GDMA_Channelx->GDMA_CFGx_L = gdma_cfgxl.d32;
+
+    /* ---------------- Configure scatter and gather ---------------- */
+#if (GDMA_SUPPORT_GATHER_SCATTER_FUNCTION == 1)
+    /* Set for gather */
+    if (GDMA_IsGatherScatterChannel(GDMA_Channelx))
+    {
+        gdma_ctlxl.b.src_gather_en = GDMA_InitStruct->GDMA_Gather_En;
+        GDMA_Channelx->GDMA_CTLx_L = gdma_ctlxl.d32;
+
+        if (GDMA_InitStruct->GDMA_Gather_En == 1)
+        {
+            GDMA_SGRx_L_TypeDef gdma_sgrxl = {.d32 = GDMA_Channelx->GDMA_SGRx_L};
+            gdma_sgrxl.b.sgi = GDMA_InitStruct->GDMA_GatherInterval & 0xFFFFF;
+            gdma_sgrxl.b.sgc = GDMA_InitStruct->GDMA_GatherCount & 0xFFF;
+            GDMA_Channelx->GDMA_SGRx_L = gdma_sgrxl.d32;
+
+            GDMA_SGRx_H_TypeDef gdma_sgrxh = {.d32 = GDMA_Channelx->GDMA_SGRx_H};
+            gdma_sgrxh.b.sgsn = GDMA_InitStruct->GDMA_GatherCircularStreamingNum;
+            GDMA_Channelx->GDMA_SGRx_H = gdma_sgrxh.d32;
+        }
+    }
+    /* Set for scatter */
+    if (GDMA_IsGatherScatterChannel(GDMA_Channelx))
+    {
+        gdma_ctlxl.b.dst_scatter_en = GDMA_InitStruct->GDMA_Scatter_En;
+        GDMA_Channelx->GDMA_CTLx_L = gdma_ctlxl.d32;
+
+        if ((GDMA_InitStruct->GDMA_Scatter_En == 1))
+        {
+            GDMA_DSRx_L_TypeDef gdma_dsrxl = {.d32 = GDMA_Channelx->GDMA_DSRx_L};
+            gdma_dsrxl.b.dsi = GDMA_InitStruct->GDMA_ScatterInterval & 0xFFFFF;
+            gdma_dsrxl.b.dsc = GDMA_InitStruct->GDMA_ScatterCount & 0xFFF;
+            GDMA_Channelx->GDMA_DSRx_L = gdma_dsrxl.d32;
+
+            GDMA_DSRx_H_TypeDef gdma_dsrxh = {.d32 = GDMA_Channelx->GDMA_DSRx_H};
+            gdma_dsrxh.b.dssn = GDMA_InitStruct->GDMA_ScatterCircularStreamingNum;
+            GDMA_Channelx->GDMA_DSRx_H = gdma_dsrxh.d32;
+        }
+    }
+#endif
+
+    /* Clear pending interrupts of corresponding GDMA channel */
+    temp_bit = BIT(channel_num);
+    GDMAx->GDMA_CLEARTFR_L = temp_bit;
+    GDMAx->GDMA_CLEARBLOCK_L = temp_bit;
+#if (GDMA_SUPPORT_INT_HAIF_BLOCK == 1)
+    GDMAx->GDMA_CLEARBLOCK_H = temp_bit;
+#endif
+    GDMAx->GDMA_CLEARERR_L = temp_bit;
+}
+
+/**
+  * \brief  Fills each GDMA_InitStruct member with its default value.
+  * \param  GDMA_InitStruct: pointer to a GDMA_InitTypeDef structure which will
+  *         be initialized.
+  * \return None.
+  */
+void GDMA_StructInit(GDMA_InitTypeDef *GDMA_InitStruct)
+{
+    /*-------------- Reset DMA init structure parameters values ------------------*/
+    GDMA_InitStruct->GDMA_ChannelNum            = 0;
+    GDMA_InitStruct->GDMA_DIR                   = GDMA_DIR_PeripheralToMemory;
+    GDMA_InitStruct->GDMA_BufferSize            = 200;
+    GDMA_InitStruct->GDMA_SourceInc             = DMA_SourceInc_Fix;
+    GDMA_InitStruct->GDMA_DestinationInc        = DMA_DestinationInc_Inc;
+    GDMA_InitStruct->GDMA_SourceDataSize        = GDMA_DataSize_Byte;
+    GDMA_InitStruct->GDMA_DestinationDataSize   = GDMA_DataSize_Byte;
+    GDMA_InitStruct->GDMA_SourceMsize           = GDMA_Msize_1;
+    GDMA_InitStruct->GDMA_DestinationMsize      = GDMA_Msize_1;
+    GDMA_InitStruct->GDMA_SourceAddr            = 0;
+    GDMA_InitStruct->GDMA_DestinationAddr       = 0;
+    GDMA_InitStruct->GDMA_SourceHandshake       = 0;
+    GDMA_InitStruct->GDMA_DestHandshake         = 0;
+    GDMA_InitStruct->GDMA_ChannelPriority       = 0;
+
+    GDMA_InitStruct->GDMA_Multi_Block_En        = DISABLE;
+    GDMA_InitStruct->GDMA_Multi_Block_Mode      = LLI_TRANSFER;
+    GDMA_InitStruct->GDMA_Multi_Block_Struct    = 0;
+
+#if (GDMA_SUPPORT_GATHER_SCATTER_FUNCTION == 1)
+    GDMA_InitStruct->GDMA_Gather_En             = DISABLE;
+    GDMA_InitStruct->GDMA_GatherCount           = 0;
+    GDMA_InitStruct->GDMA_GatherInterval        = 0;
+    GDMA_InitStruct->GDMA_Scatter_En            = DISABLE;
+    GDMA_InitStruct->GDMA_ScatterCount          = 0;
+    GDMA_InitStruct->GDMA_ScatterInterval       = 0;
+    GDMA_InitStruct->GDMA_GatherCircularStreamingNum = 0;
+    GDMA_InitStruct->GDMA_ScatterCircularStreamingNum = 0;
+#endif
+
+#if (GDMA_SUPPORT_SECURE_MODE == 1)
+    GDMA_InitStruct->GDMA_Secure_En             = ENABLE;
+#endif
+}
+
+/**
+  * \brief  Enable or disable the specified GDMA Channelx.
+  * \param  GDMA_ChannelNum: Select the GDMA channel number. \ref GDMA_CHANNEL_NUM
+  * \param  NewState: new state of the DMA Channelx.
+  *         This parameter can be: ENABLE or DISABLE.
+  * \return None.
+  */
+void GDMA_Cmd(uint8_t GDMA_ChannelNum, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_GDMA_ChannelNum(GDMA_ChannelNum));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    uint8_t bit_need_set_times = 10;
+    uint8_t bit_need_check_times = 50;
+    uint8_t timeout = bit_need_check_times ;
+    uint8_t bit_set_time = 0;
+
+    GDMA_TypeDef *GDMAx = GDMA_GetGDMAxByCh(GDMA_ChannelNum);
+    uint8_t channel_num = GDMA_GetGDMAChannelNum(GDMA_ChannelNum);
+    GDMA_ChannelTypeDef *GDMA_Channelx = GDMA_GetGDMAChannelx(GDMA_ChannelNum);
+
+    if (NewState == ENABLE)
+    {
+        /* Enable the selected DMA Channel */
+        GDMAx->GDMA_CHENREG_L = CHANNEL_BIT(channel_num) | CHANNEL_WE_BIT(channel_num);
+    }
+    else if (NewState == DISABLE)
+    {
+        /* Disable the selected DMA Channel */
+
+        /* GDMA transfer not finished */
+        if (GDMAx->GDMA_CHENREG_L & CHANNEL_BIT(channel_num))
+        {
+            /* suspend gdma channel */
+            GDMA_Channelx->GDMA_CFGx_L |= GDMA_SUSPEND_TRANSMISSSION;
+        }
+        /* Polling fifo empty */
+        while ((GDMA_GetSuspendChannelStatus(GDMA_Channelx) != SET) && --timeout);
+
+        /*cfg bit0 not set */
+        if (GDMA_GetSuspendChannelStatus(GDMA_Channelx) != SET)
+        {
+            timeout = bit_need_check_times;
+            /* Polling cfg[1:2] 10 times set in 100timer check */
+            while (--timeout)
+            {
+                if (GDMA_GetSuspendCmdStatus(GDMA_Channelx))
+                {
+                    bit_set_time++;
+                    if (bit_set_time >= bit_need_set_times)
+                    {
+                        break;
+                    }
+                }
+            }
+        }
+
+        /* Disable the selected DMAy Channelx */
+        GDMAx->GDMA_CHENREG_L = CHANNEL_WE_BIT(channel_num);
+
+        /* unsuspend dma channel */
+        GDMA_Channelx->GDMA_CFGx_L &= ~(GDMA_SUSPEND_TRANSMISSSION);
+    }
+}
+
+/**
+  * \brief  Enable or disable the specified DMA Channelx interrupts.
+  * \param  GDMA_ChannelNum: Select the GDMA channel number. \ref GDMA_CHANNEL_NUM
+  * \param  GDMA_IT: specifies the GDMA interrupts sources to be enabled or disabled.
+  *         This parameter can be any combination of the following values:
+  *         \arg GDMA_INT_Transfer:  Transfer complete interrupt unmask
+  *         \arg GDMA_INT_Block:  Block transfer interrupt unmask
+  *         \arg GDMA_INT_Error:  Transfer error interrupt unmask
+  *         \arg GDMA_INT_Half_Block: Half Block transfer interrupt unmask
+  * \param  NewState: new state of the specified DMA interrupts.
+  *         This parameter can be: ENABLE or DISABLE.
+  * \return None.
+  */
+void GDMA_INTConfig(uint8_t GDMA_ChannelNum, uint32_t GDMA_IT, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_GDMAx_ChannelNum(GDMA_ChannelNum));
+    assert_param(IS_GDMA_CONFIG_IT(GDMA_IT));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    GDMA_TypeDef *GDMAx = GDMA_GetGDMAxByCh(GDMA_ChannelNum);
+    uint8_t channel_num = GDMA_GetGDMAChannelNum(GDMA_ChannelNum);
+    uint32_t temp_bit = 0;
+
+    if (NewState == ENABLE)
+    {
+        /* Enable the selected DMA interrupts */
+        temp_bit = CHANNEL_BIT(channel_num) | CHANNEL_WE_BIT(channel_num);
+    }
+    else
+    {
+        /* Disable the selected DMA interrupts */
+        temp_bit = CHANNEL_WE_BIT(channel_num);
+    }
+
+    if (GDMA_IT & GDMA_INT_Transfer)
+    {
+        GDMAx->GDMA_MASKTFR_L = temp_bit;
+    }
+    if (GDMA_IT & GDMA_INT_Block)
+    {
+        GDMAx->GDMA_MASKBLOCK_L = temp_bit;
+    }
+#if (GDMA_SUPPORT_INT_HAIF_BLOCK == 1)
+    if ((GDMA_IT & GDMA_INT_Half_Block) && GDMA_IsHalfBlcokChannel(GDMAx))
+    {
+        GDMAx->GDMA_MASKBLOCK_H = temp_bit;
+    }
+#endif
+    if (GDMA_IT & GDMA_INT_Error)
+    {
+        GDMAx->GDMA_MASKERR_L = temp_bit;
+    }
+}
+
+/**
+  * \brief  Check whether GDMA Channel transfer interrupt is set.
+  * \param  GDMA_ChannelNum: Select the GDMA channel number. \ref GDMA_CHANNEL_NUM
+  * \return Transfer interrupt status, SET or RESET.
+  */
+ITStatus GDMA_GetTransferINTStatus(uint8_t GDMA_ChannelNum)
+{
+    /* Check the parameters */
+    assert_param(IS_GDMA_ChannelNum(GDMAx_Channel_Num));
+
+    GDMA_TypeDef *GDMAx = GDMA_GetGDMAxByCh(GDMA_ChannelNum);
+    uint8_t channel_num = GDMA_GetGDMAChannelNum(GDMA_ChannelNum);
+
+    if ((GDMAx->GDMA_STATUSTFR_L & BIT(channel_num)) != (uint32_t)RESET)
+    {
+        return SET;
+    }
+    return RESET;
+}
+
+/**
+  * \brief  Clear the specified DMA Channelx interrupts.
+  * \param  GDMA_ChannelNum: Select the GDMA channel number. \ref GDMA_CHANNEL_NUM
+  * \param  GDMA_IT: specifies the GDMA interrupts sources to be enabled
+  *         or disabled.
+  *         This parameter can be any combination of the following values:
+  *         \arg GDMA_INT_Transfer:  clear transfer complete interrupt.
+  *         \arg GDMA_INT_Block:  clear Block transfer interrupt.
+  *         \arg GDMA_INT_Error:  clear Transfer error interrupt.
+  *         \arg GDMA_INT_Half_Block:  clear Half Block transfer interrupt.
+  * \param  NewState: new state of the specified DMA interrupts.
+  *         This parameter can be: ENABLE or DISABLE.
+  * \return None.
+  */
+void GDMA_ClearINTPendingBit(uint8_t GDMA_ChannelNum, uint32_t GDMA_IT)
+{
+    /* Check the parameters */
+    assert_param(IS_GDMAx_ChannelNum(GDMAx_ChannelNum));
+    assert_param(IS_GDMA_CONFIG_IT(GDMA_IT));
+
+    GDMA_TypeDef *GDMAx = GDMA_GetGDMAxByCh(GDMA_ChannelNum);
+    uint8_t channel_num = GDMA_GetGDMAChannelNum(GDMA_ChannelNum);
+    uint32_t temp_bit = BIT(channel_num);
+
+    /* clear the selected DMA interrupts */
+    if (GDMA_IT & GDMA_INT_Transfer)
+    {
+        GDMAx->GDMA_CLEARTFR_L = temp_bit;
+    }
+    if (GDMA_IT & GDMA_INT_Block)
+    {
+        GDMAx->GDMA_CLEARBLOCK_L = temp_bit;
+    }
+#if (GDMA_SUPPORT_INT_HAIF_BLOCK == 1)
+    if ((GDMA_IT & GDMA_INT_Half_Block) && GDMA_IsHalfBlcokChannel(GDMAx))
+    {
+        GDMAx->GDMA_CLEARBLOCK_H = temp_bit;
+    }
+#endif
+    if (GDMA_IT & GDMA_INT_Error)
+    {
+        GDMAx->GDMA_CLEARERR_L = temp_bit;
+    }
+}
+
+/**
+  * \brief  Clear GDMAx Channelx all type interrupt.
+  * \param  GDMA_ChannelNum: Select the GDMA channel number. \ref GDMA_CHANNEL_NUM
+  * \return None.
+  */
+void GDMA_ClearAllTypeINT(uint8_t GDMA_ChannelNum)
+{
+    /* Check the parameters */
+    assert_param(IS_GDMA_Num(GDMAx));
+    assert_param(IS_GDMA_ChannelNum(GDMA_Channel_Num));
+
+    GDMA_TypeDef *GDMAx = GDMA_GetGDMAxByCh(GDMA_ChannelNum);
+    uint8_t channel_num = GDMA_GetGDMAChannelNum(GDMA_ChannelNum);
+    uint32_t temp_bit = BIT(channel_num);
+
+    GDMAx->GDMA_CLEARTFR_L = temp_bit;
+    GDMAx->GDMA_CLEARBLOCK_L = temp_bit;
+#if (GDMA_SUPPORT_INT_HAIF_BLOCK == 1)
+    GDMAx->GDMA_CLEARBLOCK_H = temp_bit;
+#endif
+    GDMAx->GDMA_CLEARERR_L = temp_bit;
+}
+
+/**
+  * \brief  Get selected GDMA channel status.
+  * \param  GDMA_ChannelNum: Select the GDMA channel number. \ref GDMA_CHANNEL_NUM
+  * \return GDMA channel status: can be SET or RESET.
+  * \return None.
+  */
+FlagStatus GDMA_GetChannelStatus(uint8_t GDMA_ChannelNum)
+{
+    /* Check the parameters */
+    assert_param(IS_GDMA_ChannelNum(GDMA_ChannelNum));
+
+    GDMA_TypeDef *GDMAx = GDMA_GetGDMAxByCh(GDMA_ChannelNum);
+    uint8_t channel_num = GDMA_GetGDMAChannelNum(GDMA_ChannelNum);
+
+    if ((GDMAx->GDMA_CHENREG_L & CHANNEL_BIT(channel_num)) != (uint32_t)RESET)
+    {
+        return SET;
+    }
+    return  RESET;
+}
+
+#if (GDMA_SUPPORT_SECURE_MODE == 1)
+/**
+  * \brief  Enable or disable the specified DMA channel secure functions.
+  * \param  GDMA_ChannelNum: Select the GDMA channel number. \ref GDMA_CHANNEL_NUM
+  * \param  NewState: Specifies the GDMA channel secure function to be enabled or disabled.
+  *         This parameter can be: ENABLE or DISABLE.
+  * \return None.
+  */
+void GDMA_SecureCmd(GDMA_ChannelTypeDef *GDMA_Channelx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_GDMA_ALL_PERIPH(GDMA_Channelx));
+
+    GDMA_CFGx_H_TypeDef gdma_cfgxh = {.d32 = GDMA_Channelx->GDMA_CFGx_H};
+    gdma_cfgxh.b.protctl = !NewState;
+    GDMA_Channelx->GDMA_CFGx_H = gdma_cfgxh.d32;
+}
+#endif
+
+#if (GDMA_SUPPORT_OSW_OSR_CHANGE == 1)
+/**
+  * \brief  Set GDMA OSW.
+  * \param  GDMA_ChannelNum: Select the GDMA channel number. \ref GDMA_CHANNEL_NUM
+  * \param  osw_count: outstanding write count.
+  * \return None.
+  */
+void GDMA_SetOSW(uint8_t GDMA_ChannelNum, uint8_t osw_count)
+{
+    /* Check the parameters */
+    assert_param(IS_GDMA_ALL_PERIPH(GDMA_Channelx));
+
+    GDMA_TypeDef *GDMAx = GDMA_GetGDMAxByCh(GDMA_ChannelNum);
+
+    GDMA_DMAOSNUM_L_TypeDef gdma_osnum = {.d32 = GDMAx->GDMA_DMAOSNUM_L};
+    gdma_osnum.b.osw = osw_count & 0xFF;
+    GDMAx->GDMA_DMAOSNUM_L = gdma_osnum.d32;
+}
+
+/**
+  * \brief  Set GDMA OSR.
+  * \param  GDMA_ChannelNum: Select the GDMA channel number. \ref GDMA_CHANNEL_NUM
+  * \param  osr_count: outstanding read count.
+  * \return None.
+  */
+void GDMA_SetOSR(uint8_t GDMA_ChannelNum, uint8_t osr_count)
+{
+    /* Check the parameters */
+    assert_param(IS_GDMA_ALL_PERIPH(GDMA_Channelx));
+
+    GDMA_TypeDef *GDMAx = GDMA_GetGDMAxByCh(GDMA_ChannelNum);
+
+    GDMA_DMAOSNUM_L_TypeDef gdma_osnum = {.d32 = GDMAx->GDMA_DMAOSNUM_L};
+    gdma_osnum.b.osr = osr_count & 0xFF;
+    GDMAx->GDMA_DMAOSNUM_L = gdma_osnum.d32;
+}
+
+/**
+  * \brief  Get GDMA OSW.
+  * \param  GDMA_ChannelNum: Select the GDMA channel number. \ref GDMA_CHANNEL_NUM
+  * \return osw_count: outstanding write count.
+  */
+uint8_t GDMA_GetOSWCount(uint8_t GDMA_ChannelNum)
+{
+    /* Check the parameters */
+    assert_param(IS_GDMA_ALL_PERIPH(GDMA_Channelx));
+
+    GDMA_TypeDef *GDMAx = GDMA_GetGDMAxByCh(GDMA_ChannelNum);
+
+    GDMA_DMAOSNUM_L_TypeDef gdma_osnum = {.d32 = GDMAx->GDMA_DMAOSNUM_L};
+
+    return gdma_osnum.b.osw & 0xFF;
+}
+
+/**
+  * \brief  Get GDMA OSR.
+  * \param  GDMA_ChannelNum: Select the GDMA channel number. \ref GDMA_CHANNEL_NUM
+  * \return osr_count: outstanding read count.
+  */
+uint8_t GDMA_GetOSRCount(uint8_t GDMA_ChannelNum)
+{
+    /* Check the parameters */
+    assert_param(IS_GDMA_ALL_PERIPH(GDMA_Channelx));
+
+    GDMA_TypeDef *GDMAx = GDMA_GetGDMAxByCh(GDMA_ChannelNum);
+
+    GDMA_DMAOSNUM_L_TypeDef gdma_osnum = {.d32 = GDMAx->GDMA_DMAOSNUM_L};
+
+    return gdma_osnum.b.osr & 0xFF;
+}
+#endif
+
+/**
+  * \brief  Suspend GDMA transmission safe from the source.Please check GDMA FIFO empty to guarnatee without losing data.
+  * \param  GDMA_Channelx: Select the GDMA peripheral. \ref GDMA_Declaration
+  * \return true: suspend success, false: suspend failed
+  */
+bool GDMA_SafeSuspend(GDMA_ChannelTypeDef *GDMA_Channelx)
+{
+    /* Check the parameters */
+    assert_param(IS_GDMA_ALL_PERIPH(GDMA_Channelx));
+
+    uint8_t bit_set_time = 0;
+    uint8_t bit_need_set_times = 10;
+    uint8_t bit_need_check_times = 50;
+    uint8_t timeout = bit_need_check_times;
+
+    /* Suspend transmission */
+    GDMA_Channelx->GDMA_CFGx_L |= GDMA_SUSPEND_TRANSMISSSION;
+
+    /* Disable the selected DMAy Channelx */
+    /* polling fifo empty */
+    while ((GDMA_GetSuspendChannelStatus(GDMA_Channelx) != SET) && timeout--);
+    if (GDMA_GetSuspendChannelStatus(GDMA_Channelx) != SET)
+    {
+        timeout = bit_need_check_times;
+        /*polling cfg[1:2] 10 times set in 100timer check */
+        while (--timeout)
+        {
+            if (GDMA_GetSuspendCmdStatus(GDMA_Channelx))
+            {
+                bit_set_time++;
+                if (bit_set_time >= bit_need_set_times)
+                {
+                    break;
+                }
+            }
+        }
+        if (timeout == 0)
+        {
+            /* unsuspend dma channel */
+            GDMA_Channelx->GDMA_CFGx_L &= ~(GDMA_SUSPEND_TRANSMISSSION);
+            return false;
+        }
+    }
+
+    return true;
+}
+
+/**
+ * \brief  Set GDMA transmission source address.
+  * \param  GDMA_Channelx: Select the GDMA peripheral. \ref GDMA_Declaration
+ * \param  Address: Source address.
+ * \return None.
+ */
+void GDMA_SetSourceAddress(GDMA_ChannelTypeDef *GDMA_Channelx, uint32_t Address)
+{
+    /* Check the parameters */
+    assert_param(IS_GDMA_ALL_PERIPH(GDMA_Channelx));
+
+    GDMA_Channelx->GDMA_SARx = Address;
+}
+
+/**
+ * \brief  Set GDMA transmission destination address.
+  * \param  GDMA_Channelx: Select the GDMA peripheral. \ref GDMA_Declaration
+ * \param  Address: Destination address.
+ * \return None.
+ */
+void GDMA_SetDestinationAddress(GDMA_ChannelTypeDef *GDMA_Channelx,
+                                uint32_t Address)
+{
+    /* Check the parameters */
+    assert_param(IS_GDMA_ALL_PERIPH(GDMA_Channelx));
+
+    GDMA_Channelx->GDMA_DARx = Address;
+}
+
+/**
+ * \brief  Set GDMA LLP stucture address.
+  * \param  GDMA_Channelx: Select the GDMA peripheral. \ref GDMA_Declaration
+ * \param  Address: LLP stucture address.
+ * \return None.
+ */
+void GDMA_SetLLPAddress(GDMA_ChannelTypeDef *GDMA_Channelx, uint32_t Address)
+{
+    /* Check the parameters */
+    assert_param(IS_GDMA_ALL_PERIPH(GDMA_Channelx));
+
+    GDMA_Channelx->GDMA_LLPx_L = Address & 0xFFFFFFFC;
+}
+
+/**
+ * \brief  Set GDMA buffer size.
+  * \param  GDMA_Channelx: Select the GDMA peripheral. \ref GDMA_Declaration
+ * \param  buffer_size: Set GDMA_BufferSize, max 65535.
+ * \return None.
+ */
+void GDMA_SetBufferSize(GDMA_ChannelTypeDef *GDMA_Channelx, uint32_t buffer_size)
+{
+    /* Check the parameters */
+    assert_param(IS_GDMA_ALL_PERIPH(GDMA_Channelx));
+
+    /* Configure high 32 bit of CTL register */
+    GDMA_Channelx->GDMA_CTLx_H = buffer_size;
+}
+
+/**
+ * \brief  Get GDMA source address.
+  * \param  GDMA_Channelx: Select the GDMA peripheral. \ref GDMA_Declaration
+ * \return Source address.
+ */
+uint32_t GDMA_GetSrcTransferAddress(GDMA_ChannelTypeDef *GDMA_Channelx)
+{
+    /* Check the parameters */
+    assert_param(IS_GDMA_ALL_PERIPH(GDMA_Channelx));
+
+    return GDMA_Channelx->GDMA_SARx;
+}
+
+/**
+ * \brief  Get GDMA destination address.
+  * \param  GDMA_Channelx: Select the GDMA peripheral. \ref GDMA_Declaration
+ * \return Destination address.
+ */
+uint32_t GDMA_GetDstTransferAddress(GDMA_ChannelTypeDef *GDMA_Channelx)
+{
+    /* Check the parameters */
+    assert_param(IS_GDMA_ALL_PERIPH(GDMA_Channelx));
+
+    return GDMA_Channelx->GDMA_DARx;
+}
+
+/**
+ * \brief  Get GDMA transfer data length.
+  * \param  GDMA_Channelx: Select the GDMA peripheral. \ref GDMA_Declaration
+ * \return GDMA transfer data length.
+ */
+uint16_t GDMA_GetTransferLen(GDMA_ChannelTypeDef *GDMA_Channelx)
+{
+    /* Check the parameters */
+    assert_param(IS_GDMA_ALL_PERIPH(GDMA_Channelx));
+
+    return (uint16_t)(GDMA_Channelx->GDMA_CTLx_H & 0xFFFFFFFF);
+}
+
+/**
+ * \brief  Check GDMA FIFO status.
+  * \param  GDMA_Channelx: Select the GDMA peripheral. \ref GDMA_Declaration
+ * \return GDMA FIFO status.
+ */
+FlagStatus GDMA_GetFIFOStatus(GDMA_ChannelTypeDef *GDMA_Channelx)
+{
+    /* Check the parameters */
+    assert_param(IS_GDMA_ALL_PERIPH(GDMA_Channelx));
+
+    if ((GDMA_Channelx->GDMA_CFGx_L & GDMA_FIFO_STATUS) != (uint32_t)RESET)
+    {
+        if (GDMA_GetSuspendCmdStatus(GDMA_Channelx))
+        {
+            return SET;
+        }
+    }
+    return  RESET;
+}
+
+/**
+ * \brief  Suspend GDMA transmission from the source.
+  * \param  GDMA_Channelx: Select the GDMA peripheral. \ref GDMA_Declaration
+ * \param  NewState: New state of the GDMAx Channelx.
+ * \return None.
+ */
+void GDMA_SuspendCmd(GDMA_ChannelTypeDef *GDMA_Channelx,
+                     FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_GDMA_ALL_PERIPH(GDMA_Channelx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (NewState == DISABLE)
+    {
+        /* Not suspend transmission*/
+        GDMA_Channelx->GDMA_CFGx_L &= ~(GDMA_SUSPEND_TRANSMISSSION);
+    }
+    else
+    {
+        /* Suspend transmission */
+        GDMA_Channelx->GDMA_CFGx_L |= GDMA_SUSPEND_TRANSMISSSION;
+    }
+}
+
+/**
+ * \brief  Check GDMA suspend command status.
+  * \param  GDMA_Channelx: Select the GDMA peripheral. \ref GDMA_Declaration
+ * \return GDMA suspend command status.
+ */
+FlagStatus GDMA_GetSuspendCmdStatus(GDMA_ChannelTypeDef *GDMA_Channelx)
+{
+    /* Check the parameters */
+    assert_param(IS_GDMA_ALL_PERIPH(GDMA_Channelx));
+
+    if ((GDMA_Channelx->GDMA_CFGx_L & GDMA_SUSPEND_CMD_STATUS) == GDMA_SUSPEND_CMD_STATUS)
+    {
+        return SET;
+    }
+    return  RESET;
+}
+
+/**
+ * \brief  Check GDMA suspend channel status.
+  * \param  GDMA_Channelx: Select the GDMA peripheral. \ref GDMA_Declaration
+ * \return GDMA suspend channel status.
+ */
+FlagStatus GDMA_GetSuspendChannelStatus(GDMA_ChannelTypeDef *GDMA_Channelx)
+{
+    /* Check the parameters */
+    assert_param(IS_GDMA_ALL_PERIPH(GDMA_Channelx));
+
+    if ((GDMA_Channelx->GDMA_CFGx_L & GDMA_SUSPEND_CHANNEL_STATUS) == GDMA_SUSPEND_CHANNEL_STATUS)
+    {
+        return SET;
+    }
+    return  RESET;
+}
+
+/**
+ * \brief  Update GDMA LLP mode in multi-block.
+  * \param  GDMA_Channelx: Select the GDMA peripheral. \ref GDMA_Declaration
+ * \param  GDMA LLP mode
+ * \return None.
+ */
+void GDMA_SetLLPMode(GDMA_ChannelTypeDef *GDMA_Channelx, uint32_t mode)
+{
+    GDMA_Channelx->GDMA_CTLx_L = ((GDMA_Channelx->GDMA_CTLx_L & (~LLI_TRANSFER)) | mode);
+}
+
diff --git a/bee/drivers/dma/src/device/rtl87x2g/rtl_gdma.h b/bee/drivers/dma/src/device/rtl87x2g/rtl_gdma.h
new file mode 100644
index 00000000..baa93839
--- /dev/null
+++ b/bee/drivers/dma/src/device/rtl87x2g/rtl_gdma.h
@@ -0,0 +1,1053 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *               Define to prevent recursive inclusion
+ *============================================================================*/
+#ifndef RTL_GDMA_H
+#define RTL_GDMA_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*============================================================================*
+ *                        Header Files
+ *============================================================================*/
+#include "utils/rtl_utils.h"
+#include "rtl_gdma_def.h"
+
+/** \defgroup GDMA        GDMA
+  * \brief
+  * \{
+  */
+
+/*============================================================================*
+ *                         Constants
+ *============================================================================*/
+/** \defgroup GDMA_Exported_Constants GDMA Exported Constants
+  * \brief
+  * \{
+  */
+
+/**
+ * \defgroup    GDMA_Channel_Num GDMA Channel Num
+ * \{
+ * \ingroup     GDMA_Exported_Constants
+ */
+
+#define GDMA_CH_NUM0             (0)       //!< GDMA channel number0.
+#define GDMA_CH_NUM1             (1)       //!< GDMA channel number1.
+#define GDMA_CH_NUM2             (2)       //!< GDMA channel number2.
+#define GDMA_CH_NUM3             (3)       //!< GDMA channel number3.
+#define GDMA_CH_NUM4             (4)       //!< GDMA channel number4.
+#define GDMA_CH_NUM5             (5)       //!< GDMA channel number5.
+#if (CHIP_GDMA_CHANNEL_NUM >= 9)
+#define GDMA_CH_NUM6             (6)       //!< GDMA channel number6.
+#define GDMA_CH_NUM7             (7)       //!< GDMA channel number7.
+#define GDMA_CH_NUM8             (8)       //!< GDMA channel number8.
+#endif
+#if (CHIP_GDMA_CHANNEL_NUM >= 10)
+#define GDMA_CH_NUM9             (9)       //!< GDMA channel number9.
+#endif
+#if (CHIP_GDMA_CHANNEL_NUM >= 12)
+#define GDMA_CH_NUM10            (10)       //!< GDMA channel number10.
+#define GDMA_CH_NUM11            (11)       //!< GDMA channel number11.
+#endif
+#if (CHIP_GDMA_CHANNEL_NUM >= 24)
+#define GDMA_CH_NUM12            (12)       //!< GDMA channel number12.
+#define GDMA_CH_NUM13            (13)       //!< GDMA channel number13.
+#define GDMA_CH_NUM14            (14)       //!< GDMA channel number14.
+#define GDMA_CH_NUM15            (15)       //!< GDMA channel number15.
+#define GDMA_CH_NUM16            (16)       //!< GDMA channel number16.
+#define GDMA_CH_NUM17            (17)       //!< GDMA channel number17.
+#define GDMA_CH_NUM18            (18)       //!< GDMA channel number18.
+#define GDMA_CH_NUM19            (19)       //!< GDMA channel number19.
+#define GDMA_CH_NUM20            (20)       //!< GDMA channel number20.
+#define GDMA_CH_NUM21            (21)       //!< GDMA channel number21.
+#define GDMA_CH_NUM22            (22)       //!< GDMA channel number22.
+#define GDMA_CH_NUM23            (23)       //!< GDMA channel number23.
+#endif
+#if (CHIP_GDMA_CHANNEL_NUM >= 33)
+#define GDMA_CH_NUM24            (24)       //!< GDMA channel number24.
+#define GDMA_CH_NUM25            (25)       //!< GDMA channel number25.
+#define GDMA_CH_NUM26            (26)       //!< GDMA channel number26.
+#define GDMA_CH_NUM27            (27)       //!< GDMA channel number27.
+#define GDMA_CH_NUM28            (28)       //!< GDMA channel number28.
+#define GDMA_CH_NUM29            (29)       //!< GDMA channel number29.
+#define GDMA_CH_NUM30            (30)       //!< GDMA channel number30.
+#define GDMA_CH_NUM31            (31)       //!< GDMA channel number31.
+#define GDMA_CH_NUM32            (32)       //!< GDMA channel number32.
+#endif
+
+#define IS_GDMA_ChannelNum(NUM)  ((NUM) < CHIP_GDMA_CHANNEL_NUM) //!< Specify the maximum GDMA channel number.
+
+/** End of GDMA_Channel_Num
+  * \}
+  */
+
+/**
+ * \defgroup   GDMA_Data_Transfer_Direction GDMA Data Transfer Direction
+ * \{
+ * \ingroup    GDMA_Exported_Constants
+ */
+
+typedef enum
+{
+    GDMA_DIR_MemoryToMemory = 0x0,             //!< Configure the direction of GDMA as memory to memory.
+    GDMA_DIR_MemoryToPeripheral = 0x1,         //!< Configure the direction of GDMA as memory to peripheral.
+    GDMA_DIR_PeripheralToMemory = 0x2,         //!< Configure the direction of GDMA as peripheral to memory.
+    GDMA_DIR_PeripheralToPeripheral = 0x3,     //!< Configure the direction of GDMA as peripheral to peripheral.
+} GDMADirection_TypeDef;
+
+#define IS_GDMA_DIR(DIR) (((DIR) == GDMA_DIR_MemoryToMemory) || \
+                          ((DIR) == GDMA_DIR_MemoryToPeripheral) || \
+                          ((DIR) == GDMA_DIR_PeripheralToMemory) || \
+                          ((DIR) == GDMA_DIR_PeripheralToPeripheral)) //!< Check if the input parameter is valid.
+
+/** End of GDMA_Data_Transfer_Direction
+  * \}
+  */
+
+/**
+ * \defgroup    GDMA_Source_Incremented_Mode GDMA Source Incremented Mode
+ * \{
+ * \ingroup     GDMA_Exported_Constants
+ */
+typedef enum
+{
+    DMA_SourceInc_Inc = 0x0,        //!< Configure the source address to increment.
+#if (GDMA_SUPPORT_ADDRESS_DEC == 1)
+    DMA_SourceInc_Dec = 0x1,        //!< Configure the source address to decrement.
+#endif
+    DMA_SourceInc_Fix = 0x2,        //!< Configure the source address to be fixed.
+} GDMASrcInc_TypeDef;
+
+#define IS_GDMA_SourceInc(STATE) (((STATE) == DMA_SourceInc_Inc) || \
+                                  ((STATE) == DMA_SourceInc_Dec) || \
+                                  ((STATE) == DMA_SourceInc_Fix)) //!< Check if the input parameter is valid.
+
+/** End of GDMA_Source_Incremented_Mode
+  * \}
+  */
+
+/**
+ * \defgroup    GDMA_Destination_Incremented_Mode GDMA Destination Incremented Mode
+ * \{
+ * \ingroup     GDMA_Exported_Constants
+ */
+typedef enum
+{
+    DMA_DestinationInc_Inc = 0x0,    //!< Configure the destination address to increment.
+#if (GDMA_SUPPORT_ADDRESS_DEC == 1)
+    DMA_DestinationInc_Dec = 0x1,    //!< Configure the destination address to decrement.
+#endif
+    DMA_DestinationInc_Fix = 0x2,    //!< Configure the destination address to be fixed.
+} GDMADestInc_TypeDef;
+
+#define IS_GDMA_DestinationInc(STATE) (((STATE) == DMA_DestinationInc_Inc) || \
+                                       ((STATE) == DMA_DestinationInc_Dec) || \
+                                       ((STATE) == DMA_DestinationInc_Fix)) //!< Check if the input parameter is valid.
+
+/** End of GDMA_Destination_Incremented_Mode
+  * \}
+  */
+
+/**
+ * \defgroup    GDMA_Data_Size GDMA Data Size
+ * \{
+ * \ingroup     GDMA_Exported_Constants
+ */
+typedef enum
+{
+    GDMA_DataSize_Byte     = 0x0,    //!< Configure the source or destination data size as byte.
+    GDMA_DataSize_HalfWord = 0x1,    //!< Configure the source or destination data size as half word.
+    GDMA_DataSize_Word     = 0x2,    //!< Configure the source or destination data size as word.
+} GDMADataSize_TypeDef;
+
+#define IS_GDMA_DATA_SIZE(SIZE) (((SIZE) == GDMA_DataSize_Byte) || \
+                                 ((SIZE) == GDMA_DataSize_HalfWord) || \
+                                 ((SIZE) == GDMA_DataSize_Word)) //!< Check if the input parameter is valid.
+
+/** End of GDMA_Data_Size
+  * \}
+  */
+
+/**
+ * \defgroup    GDMA_Msize GDMA Msize
+ * \{
+ * \ingroup     GDMA_Exported_Constants
+ */
+
+typedef enum
+{
+    GDMA_Msize_1   = 0x0,          //!< Configure the number of data items to be transferred as 1.
+    GDMA_Msize_4   = 0x1,          //!< Configure the number of data items to be transferred as 4.
+    GDMA_Msize_8   = 0x2,          //!< Configure the number of data items to be transferred as 8.
+    GDMA_Msize_16  = 0x3,          //!< Configure the number of data items to be transferred as 16.
+    GDMA_Msize_32  = 0x4,          //!< Configure the number of data items to be transferred as 32.
+    GDMA_Msize_64  = 0x5,          //!< Configure the number of data items to be transferred as 64.
+    GDMA_Msize_128 = 0x6,          //!< Configure the number of data items to be transferred as 128.
+    GDMA_Msize_256 = 0x7,          //!< Configure the number of data items to be transferred as 256.
+} GDMAMSize_TypeDef;
+
+#define IS_GDMA_MSIZE(SIZE) (((SIZE) == GDMA_Msize_1) || \
+                             ((SIZE) == GDMA_Msize_4) || \
+                             ((SIZE) == GDMA_Msize_8) || \
+                             ((SIZE) == GDMA_Msize_16) || \
+                             ((SIZE) == GDMA_Msize_32) || \
+                             ((SIZE) == GDMA_Msize_64) || \
+                             ((SIZE) == GDMA_Msize_128) || \
+                             ((SIZE) == GDMA_Msize_256)) //!< Check if the input parameter is valid.
+
+/** End of GDMA_Msize
+  * \}
+  */
+
+/**
+ * \defgroup    GDMA_Interrupts  GDMA Interrupts
+ * \{
+ * \ingroup     GDMA_Exported_Constants
+ */
+
+#define GDMA_INT_Transfer               (BIT0)  //!< The interrupt is generated on GDMA transfer completion to the destination.
+#define GDMA_INT_Block                  (BIT1)  //!< The interrupt is generated on GDMA block transfer completion to the destination.
+#define GDMA_INT_Error                  (BIT4)  //!< The interrupt is generated when an ERROR response is received from the slave on the SRESP bus during a GDMA transfer.
+#if (GDMA_SUPPORT_INT_HAIF_BLOCK == 1)
+#define GDMA_INT_Half_Block             (BIT5)  //!< The interrupt is generated on GDMA half block transfer completion to the destination.
+#endif
+
+#define IS_GDMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFE0) == 0x00) && ((IT) != 0x00)) //!< Check if the input parameter is valid.
+
+/** End of GDMA_Interrupts
+  * \}
+  */
+
+/**
+ * \defgroup    GDMA_Multi-block_Mode GDMA Multi-block Mode
+ * \{
+ * \ingroup     GDMA_Exported_Constants
+ */
+#define AUTO_RELOAD_WITH_CONTIGUOUS_SAR (BIT31)  //!< Configure the multi-block transfer mode with the source address set to continuous and the destination address set to auto-reload.
+#define AUTO_RELOAD_WITH_CONTIGUOUS_DAR (BIT30)  //!< Configure the multi-block transfer mode with the source address set to auto-reload and the destination address set to continuous.
+#define AUTO_RELOAD_TRANSFER            (BIT30 | BIT31)  //!< Configure the multi-block transfer mode with the source address set to auto-reload and the destination address set to auto-reload.
+#define LLI_WITH_CONTIGUOUS_SAR         (BIT27)  //!< Configure the multi-block transfer mode with the source address set to continuous and the destination address set to LLI.
+#define LLI_WITH_AUTO_RELOAD_SAR        (BIT27 | BIT30)  //!< Configure the multi-block transfer mode with the source address set to auto-reload and the destination address set to LLI.
+#define LLI_WITH_CONTIGUOUS_DAR         (BIT28)  //!< Configure the multi-block transfer mode with the source address set to LLI and the destination address set to continuous.
+#define LLI_WITH_AUTO_RELOAD_DAR        (BIT28 | BIT31)  //!< Configure the multi-block transfer mode with the source address set to LLI and the destination address set to auto-reload.
+#define LLI_TRANSFER                    (BIT27 | BIT28)  //!< Configure the multi-block transfer mode with the source address set to LLI and the destination address set to LLI.
+
+#define IS_GDMA_MULTIBLOCKMODE(MODE) (((MODE) == AUTO_RELOAD_WITH_CONTIGUOUS_SAR) || \
+                                      ((MODE) == AUTO_RELOAD_WITH_CONTIGUOUS_DAR) || \
+                                      ((MODE) == AUTO_RELOAD_TRANSFER) || \
+                                      ((MODE) == LLI_WITH_CONTIGUOUS_SAR) || \
+                                      ((MODE) == LLI_WITH_AUTO_RELOAD_SAR) || \
+                                      ((MODE) == LLI_WITH_CONTIGUOUS_DAR) || \
+                                      ((MODE) == LLI_WITH_AUTO_RELOAD_DAR) || \
+                                      ((MODE) == LLI_TRANSFER)) //!< Check if the input parameter is valid.
+
+/** End of GDMA_Multi-block_Mode
+  * \}
+  */
+
+/**
+ * \defgroup    GDMA_Multi-Block_Select_Bit GDMA Multi-Block Select Bit
+ * \{
+ * \ingroup     GDMA_Exported_Constants
+ */
+#define AUTO_RELOAD_SELECTED_BIT        (BIT30 | BIT31)   //!< The bit for GDMA auto-reload.
+#define LLP_SELECTED_BIT                (BIT27 | BIT28)   //!< The bit for GDMA LLI.
+
+/** End of GDMA_Multi-Block_Select_Bit
+  * \}
+  */
+
+/**
+ * \defgroup    GDMA_Suspend_Flag GDMA Suspend Flag
+ * \{
+ * \ingroup     GDMA_Exported_Constants
+ */
+#define GDMA_FIFO_STATUS                (BIT(9))                //!< The bit for GDMA fifo status.
+#define GDMA_SUSPEND_TRANSMISSSION      (BIT(8))                //!< The bit for GDMA suspend transmisssion.
+#define GDMA_SUSPEND_CMD_STATUS         (BIT(2) | BIT(1))       //!< The bit for GDMA suspend command.
+#define GDMA_SUSPEND_CHANNEL_STATUS     (BIT(0))                //!< The bit for GDMA suspend channel status.
+
+/** End of GDMA_Suspend_Flag
+  * \}
+  */
+
+/** End of GDMA_Exported_Constants
+  * \}
+  */
+
+/*============================================================================*
+ *                         Types
+ *============================================================================*/
+/** \defgroup GDMA_Exported_Types GDMA Exported Types
+  * \brief
+  * \{
+  */
+
+/**
+ * \brief       GDMA init structure definition.
+ *
+ * \ingroup     GDMA_Exported_Types
+ */
+
+typedef struct
+{
+    uint8_t GDMA_ChannelNum;                /*!< Specify the channel number for GDMA.
+                                                 This parameter can be set from 0 to 9. Refer to \ref GDMA_Channel_Num. */
+
+    GDMADirection_TypeDef GDMA_DIR;         /*!< Specify transfer direction.
+                                                 This parameter can be a value of \ref GDMA_Data_Transfer_Direction. */
+
+    uint32_t GDMA_BufferSize;               /*!< Specify the buffer size(RTL8762G <= 65535, RTL8772F: GDMA1 is 65535 and GDMA2 is 524287).
+                                                 The data unit is equal to the configuration set in DMA_PeripheralDataSize
+                                                 or DMA_MemoryDataSize members depending in the transfer direction. */
+
+    GDMASrcInc_TypeDef
+    GDMA_SourceInc;      /*!< Specify whether the source address register is incremented or not.
+                                                 This parameter can be a value of \ref GDMA_Source_Incremented_Mode. */
+
+    GDMADestInc_TypeDef
+    GDMA_DestinationInc; /*!< Specify whether the destination address register is incremented or not.
+                                                  This parameter can be a value of \ref GDMA_Destination_Incremented_Mode. */
+
+    GDMADataSize_TypeDef GDMA_SourceDataSize; /*!< Specify the source data width.
+                                                   This parameter can be a value of \ref GDMA_Data_Size. */
+
+    GDMADataSize_TypeDef GDMA_DestinationDataSize; /*!< Specify the destination data width.
+                                                        This parameter can be a value of \ref GDMA_Data_Size. */
+
+    GDMAMSize_TypeDef GDMA_SourceMsize;     /*!< Specify items number to be transferred.
+                                                 This parameter can be a value of \ref GDMA_Msize. */
+
+    GDMAMSize_TypeDef GDMA_DestinationMsize;/*!< Specify items number to be transferred.
+                                                 This parameter can be a value of \ref GDMA_Msize. */
+
+    uint32_t GDMA_SourceAddr;               /*!< Specify the source base address for GDMA Channelx. */
+
+    uint32_t GDMA_DestinationAddr;          /*!< Specify the destination base address for GDMA Channelx. */
+
+    uint32_t GDMA_ChannelPriority;          /*!< Specify the software priority for the GDMA Channelx.
+                                                 This parameter can be a value of 0~9(RTL8762G); 0~7 for GDMA1 and 0~15 for GDMA2(RTL8772F). */
+
+    uint32_t GDMA_Multi_Block_Mode;         /*!< Specify the multi block transfer mode. */
+
+    uint32_t GDMA_Multi_Block_Struct;       /*!< Pointer to the first struct of LLI. */
+
+    uint8_t GDMA_Multi_Block_En;            /*!< Enable or disable multi-block function.
+                                                 This parameter can be a value of DISABLE or ENABLE. */
+
+    uint8_t GDMA_SourceHandshake;           /*!< Specify the handshake index in source.
+                                                 This parameter can be a value of \ref GDMA_Handshake_Type. */
+
+    uint8_t GDMA_DestHandshake;             /*!< Specify the handshake index in Destination.
+                                                This parameter can be a value of \ref GDMA_Handshake_Type. */
+#if (GDMA_SUPPORT_SECURE_MODE == 1)
+    uint8_t GDMA_Secure_En;                 /*!< Enable or disable Secure function. */
+#endif
+
+#if (GDMA_SUPPORT_GATHER_SCATTER_FUNCTION == 1)
+    uint8_t  GDMA_Gather_En;                /*!< Enable or disable Gather function. NOTE:4 bytes ALIGN.*/
+    uint32_t GDMA_GatherCount;              /*!< Specify the GatherCount.NOTE:4 bytes ALIGN.*/
+    uint32_t GDMA_GatherInterval;           /*!< Specify the GatherInterval. */
+    uint8_t  GDMA_Scatter_En;               /*!< Enable or disable Scatter function. */
+    uint32_t GDMA_ScatterCount;             /*!< Specify the ScatterCount. */
+    uint32_t GDMA_ScatterInterval;          /*!< Specify the ScatterInterval. */
+    uint32_t GDMA_GatherCircularStreamingNum;  /*!< Specify the GatherCircularStreamingNum. */
+    uint32_t GDMA_ScatterCircularStreamingNum; /*!< Specify the ScatterCircularStreamingNum. */
+#endif
+
+} GDMA_InitTypeDef;
+
+/**
+ * \brief       GDMA link list item structure definition.
+ *
+ * \ingroup     GDMA_Exported_Types
+ */
+
+typedef struct
+{
+    __IO uint32_t SAR;          /*!< Specify the source base address for LLI. */
+    __IO uint32_t DAR;          /*!< Specify the destination base address for LLI. */
+    __IO uint32_t LLP;          /*!< Specify the next pointer to the struct of LLI. */
+    __IO uint32_t CTL_LOW;      /*!< Specify the CTL_LOW register for LLI. */
+    __IO uint32_t CTL_HIGH;     /*!< Specify the CTL_HIGH register for LLI. */
+} GDMA_LLIDef;
+
+/** End of GDMA_Exported_Types
+  * \}
+  */
+
+/*============================================================================*
+ *                         Functions
+ *============================================================================*/
+/** \defgroup GDMA_Exported_Functions GDMA Exported Functions
+  * \brief
+  * \{
+  */
+
+/**
+ * \brief     Deinitialize the GDMA registers to their default reset values.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_gdma_init(void)
+ * {
+ *     GDMA_DeInit();
+ * }
+ * \endcode
+ */
+void GDMA_DeInit(void);
+
+/**
+ * \brief     Initialize the GDMA Channelx according to the specified
+ *            parameters in the GDMA_InitStruct.
+ *
+ * \param[in] GDMA_Channelx    Select the GDMA peripheral. Refer to \ref GDMA_Declaration.
+ * \param[in] GDMA_InitStruct  Pointer to a GDMA_InitTypeDef structure which will be initialized.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_gdma_init(void)
+ * {
+ *     for (uint32_t i = 0; i < UART_TX_GDMA_BUFFER_SIZE; i++)
+ *     {
+ *         GDMA_SendData_Buffer[i] = 0x10 + i;
+ *     }
+ *
+ *     GDMA_InitTypeDef GDMA_InitStruct;
+ *     GDMA_StructInit(&GDMA_InitStruct);
+ *     GDMA_InitStruct.GDMA_ChannelNum      = 1;
+ *     GDMA_InitStruct.GDMA_DIR             = GDMA_DIR_MemoryToPeripheral;
+ *     GDMA_InitStruct.GDMA_BufferSize      = UART_TX_GDMA_BUFFER_SIZE;//determine total transfer size
+ *     GDMA_InitStruct.GDMA_SourceInc       = DMA_SourceInc_Inc;
+ *     GDMA_InitStruct.GDMA_DestinationInc  = DMA_DestinationInc_Fix;
+ *     GDMA_InitStruct.GDMA_SourceDataSize  = GDMA_DataSize_Byte;
+ *     GDMA_InitStruct.GDMA_DestinationDataSize = GDMA_DataSize_Byte;
+ *     GDMA_InitStruct.GDMA_SourceMsize      = GDMA_Msize_1;
+ *     GDMA_InitStruct.GDMA_DestinationMsize = GDMA_Msize_1;
+ *     GDMA_InitStruct.GDMA_SourceAddr      = (uint32_t)GDMA_SendData_Buffer;
+ *     GDMA_InitStruct.GDMA_DestinationAddr = (uint32_t)(&(UART0->UART_RBR_THR));
+ *     GDMA_InitStruct.GDMA_DestHandshake   = GDMA0_Handshake_UART0_TX;
+ *     GDMA_InitStruct.GDMA_ChannelPriority = 2;
+ *     GDMA_Init(UART_TX_GDMA_CHANNEL, &GDMA_InitStruct);
+ *
+ *     GDMA_INTConfig(UART_TX_GDMA_CHANNEL_NUM, GDMA_INT_Transfer, ENABLE);
+ *
+ *     NVIC_InitTypeDef NVIC_InitStruct;
+ *     NVIC_InitStruct.NVIC_IRQChannel = UART_TX_GDMA_CHANNEL_IRQN;
+ *     NVIC_InitStruct.NVIC_IRQChannelPriority = 3;
+ *     NVIC_InitStruct.NVIC_IRQChannelCmd = ENABLE;
+ *     NVIC_Init(&NVIC_InitStruct);
+ *
+ *     GDMA_Cmd(UART_TX_GDMA_CHANNEL_NUM, ENABLE);
+ * }
+ * \endcode
+ */
+void GDMA_Init(GDMA_ChannelTypeDef *GDMA_Channelx, GDMA_InitTypeDef *GDMA_InitStruct);
+
+/**
+ * \brief     Fill each GDMA_InitStruct member with its default value.
+ *
+ * \param[in] GDMA_InitStruct  Pointer to a GDMA_InitTypeDef structure which will be initialized.
+ *
+ * \note   The default settings for the GDMA_InitStruct member are shown in the following table:
+ *         | GDMA_InitStruct member      | Default value                      |
+ *         |:---------------------------:|:----------------------------------:|
+ *         | GDMA_ChannelNum             | \ref GDMA_CH_NUM0                 |
+ *         | GDMA_DIR                    | \ref GDMA_DIR_PeripheralToMemory   |
+ *         | GDMA_BufferSize             | 200                                |
+ *         | GDMA_SourceInc              | \ref DMA_SourceInc_Fix             |
+ *         | GDMA_DestinationInc         | \ref DMA_DestinationInc_Inc        |
+ *         | GDMA_SourceDataSize         | \ref GDMA_DataSize_Byte            |
+ *         | GDMA_DestinationDataSize    | \ref GDMA_DataSize_Byte            |
+ *         | GDMA_SourceMsize            | \ref GDMA_Msize_1                  |
+ *         | GDMA_DestinationMsize       | \ref GDMA_Msize_1                  |
+ *         | GDMA_SourceAddr             | 0                                  |
+ *         | GDMA_DestinationAddr        | 0                                  |
+ *         | GDMA_ChannelPriority        | 0                                  |
+ *         | GDMA_Multi_Block_Mode       | \ref LLI_TRANSFER                  |
+ *         | GDMA_SourceHandshake        | 0                                  |
+ *         | GDMA_DestHandshake          | 0                                  |
+ *         | GDMA_Multi_Block_En         | DISABLE                            |
+ *         | GDMA_Scatter_En             | DISABLE                            |
+ *         | GDMA_Gather_En              | DISABLE                            |
+ *         | GDMA_Source_Cir_Gather_Num  | 1                                  |
+ *         | GDMA_Dest_Cir_Sca_Num       | 1                                  |
+ *         | GDMA_Multi_Block_Struct     | 0                                  |
+ *         | GDMA_ScatterCount           | 0                                  |
+ *         | GDMA_ScatterInterval        | 0                                  |
+ *         | GDMA_GatherCount            | 0                                  |
+ *         | GDMA_GatherInterval         | 0                                  |
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_gdma_init(void)
+ * {
+ *
+ *     for (uint32_t i = 0; i < UART_TX_GDMA_BUFFER_SIZE; i++)
+ *     {
+ *         GDMA_SendData_Buffer[i] = 0x10 + i;
+ *     }
+ *
+ *     GDMA_InitTypeDef GDMA_InitStruct;
+ *     GDMA_StructInit(&GDMA_InitStruct);
+ *     GDMA_InitStruct.GDMA_ChannelNum      = 1;
+ *     GDMA_InitStruct.GDMA_DIR             = GDMA_DIR_MemoryToPeripheral;
+ *     GDMA_InitStruct.GDMA_BufferSize      = UART_TX_GDMA_BUFFER_SIZE;//determine total transfer size
+ *     GDMA_InitStruct.GDMA_SourceInc       = DMA_SourceInc_Inc;
+ *     GDMA_InitStruct.GDMA_DestinationInc  = DMA_DestinationInc_Fix;
+ *     GDMA_InitStruct.GDMA_SourceDataSize  = GDMA_DataSize_Byte;
+ *     GDMA_InitStruct.GDMA_DestinationDataSize = GDMA_DataSize_Byte;
+ *     GDMA_InitStruct.GDMA_SourceMsize      = GDMA_Msize_1;
+ *     GDMA_InitStruct.GDMA_DestinationMsize = GDMA_Msize_1;
+ *     GDMA_InitStruct.GDMA_SourceAddr      = (uint32_t)GDMA_SendData_Buffer;
+ *     GDMA_InitStruct.GDMA_DestinationAddr = (uint32_t)(&(UART0->UART_RBR_THR));
+ *     GDMA_InitStruct.GDMA_DestHandshake   = GDMA0_Handshake_UART0_TX;
+ *     GDMA_InitStruct.GDMA_ChannelPriority = 2;
+ *     GDMA_Init(UART_TX_GDMA_CHANNEL, &GDMA_InitStruct);
+ *
+ * }
+ * \endcode
+ */
+void GDMA_StructInit(GDMA_InitTypeDef *GDMA_InitStruct);
+
+/**
+ * \brief  Enable or disable the selected GDMA channel.
+ *
+ * \param[in]  GDMA_ChannelNum  Select the GDMA channel number. Refer to \ref GDMA_Channel_Num.
+ * \param[in]  NewState         New state of the selected DMA channel.
+ *                              This parameter can be one of the following values:
+ *                              - ENABLE: Enable the selected GDMA channel.
+ *                              - DISABLE: Disable the selected GDMA channel.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_gdma_init(void)
+ * {
+ *
+ *     for (uint32_t i = 0; i < UART_TX_GDMA_BUFFER_SIZE; i++)
+ *     {
+ *         GDMA_SendData_Buffer[i] = 0x10 + i;
+ *     }
+ *
+ *     GDMA_InitTypeDef GDMA_InitStruct;
+ *     GDMA_StructInit(&GDMA_InitStruct);
+ *     GDMA_InitStruct.GDMA_ChannelNum      = 1;
+ *     GDMA_InitStruct.GDMA_DIR             = GDMA_DIR_MemoryToPeripheral;
+ *     GDMA_InitStruct.GDMA_BufferSize      = UART_TX_GDMA_BUFFER_SIZE;//determine total transfer size
+ *     GDMA_InitStruct.GDMA_SourceInc       = DMA_SourceInc_Inc;
+ *     GDMA_InitStruct.GDMA_DestinationInc  = DMA_DestinationInc_Fix;
+ *     GDMA_InitStruct.GDMA_SourceDataSize  = GDMA_DataSize_Byte;
+ *     GDMA_InitStruct.GDMA_DestinationDataSize = GDMA_DataSize_Byte;
+ *     GDMA_InitStruct.GDMA_SourceMsize      = GDMA_Msize_1;
+ *     GDMA_InitStruct.GDMA_DestinationMsize = GDMA_Msize_1;
+ *     GDMA_InitStruct.GDMA_SourceAddr      = (uint32_t)GDMA_SendData_Buffer;
+ *     GDMA_InitStruct.GDMA_DestinationAddr = (uint32_t)(&(UART0->UART_RBR_THR));
+ *     GDMA_InitStruct.GDMA_DestHandshake   = GDMA0_Handshake_UART0_TX;
+ *     GDMA_InitStruct.GDMA_ChannelPriority = 2;
+ *     GDMA_Init(UART_TX_GDMA_CHANNEL, &GDMA_InitStruct);
+ *
+ *     GDMA_INTConfig(UART_TX_GDMA_CHANNEL_NUM, GDMA_INT_Transfer, ENABLE);
+ *
+ *     NVIC_InitTypeDef NVIC_InitStruct;
+ *     NVIC_InitStruct.NVIC_IRQChannel = UART_TX_GDMA_CHANNEL_IRQN;
+ *     NVIC_InitStruct.NVIC_IRQChannelPriority = 3;
+ *     NVIC_InitStruct.NVIC_IRQChannelCmd = ENABLE;
+ *     NVIC_Init(&NVIC_InitStruct);
+ *
+ *     GDMA_Cmd(UART_TX_GDMA_CHANNEL_NUM, ENABLE);
+ * }
+ * \endcode
+ */
+void GDMA_Cmd(uint8_t GDMA_ChannelNum, FunctionalState NewState);
+
+/**
+ * \brief   Enable or disable the specified DMA channelx interrupt source.
+ *
+ * \param[in] GDMA_ChannelNum  Select the GDMA channel number. Refer to \ref GDMA_Channel_Num.
+ * \param[in] GDMA_IT          Specify the GDMA interrupt source to be enabled or disabled.
+ *                             This parameter can be any combination of the following values.
+ *                             Refer to \ref GDMA_Interrupts.
+ *                             \arg GDMA_INT_Transfer: Transfer complete interrupt source.
+ *                             \arg GDMA_INT_Block: Block transfer interrupt source.
+ *                             \arg GDMA_INT_Error: Transfer error interrupt source.
+ *                             \arg GDMA_INT_Half_Block: Half Block transfer interrupt source.
+ * \param[in] NewState         New state of the specified DMA interrupt source.
+ *                             This parameter can be one of the following values:
+ *                             - ENABLE: Enable the specified GDMA channelx interrupt source.
+ *                             - DISABLE: Disable the specified GDMA channelx interrupt source.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_gdma_init(void)
+ * {
+ *
+ *     for (uint32_t i = 0; i < UART_TX_GDMA_BUFFER_SIZE; i++)
+ *     {
+ *         GDMA_SendData_Buffer[i] = 0x10 + i;
+ *     }
+ *
+ *     GDMA_InitTypeDef GDMA_InitStruct;
+ *     GDMA_StructInit(&GDMA_InitStruct);
+ *     GDMA_InitStruct.GDMA_ChannelNum      = 1;
+ *     GDMA_InitStruct.GDMA_DIR             = GDMA_DIR_MemoryToPeripheral;
+ *     GDMA_InitStruct.GDMA_BufferSize      = UART_TX_GDMA_BUFFER_SIZE;//determine total transfer size
+ *     GDMA_InitStruct.GDMA_SourceInc       = DMA_SourceInc_Inc;
+ *     GDMA_InitStruct.GDMA_DestinationInc  = DMA_DestinationInc_Fix;
+ *     GDMA_InitStruct.GDMA_SourceDataSize  = GDMA_DataSize_Byte;
+ *     GDMA_InitStruct.GDMA_DestinationDataSize = GDMA_DataSize_Byte;
+ *     GDMA_InitStruct.GDMA_SourceMsize      = GDMA_Msize_1;
+ *     GDMA_InitStruct.GDMA_DestinationMsize = GDMA_Msize_1;
+ *     GDMA_InitStruct.GDMA_SourceAddr      = (uint32_t)GDMA_SendData_Buffer;
+ *     GDMA_InitStruct.GDMA_DestinationAddr = (uint32_t)(&(UART0->UART_RBR_THR));
+ *     GDMA_InitStruct.GDMA_DestHandshake   = GDMA0_Handshake_UART0_TX;
+ *     GDMA_InitStruct.GDMA_ChannelPriority = 2;
+ *     GDMA_Init(UART_TX_GDMA_CHANNEL, &GDMA_InitStruct);
+ *
+ *     GDMA_INTConfig(UART_TX_GDMA_CHANNEL_NUM, GDMA_INT_Transfer, ENABLE);
+ *
+ *     NVIC_InitTypeDef NVIC_InitStruct;
+ *     NVIC_InitStruct.NVIC_IRQChannel = UART_TX_GDMA_CHANNEL_IRQN;
+ *     NVIC_InitStruct.NVIC_IRQChannelPriority = 3;
+ *     NVIC_InitStruct.NVIC_IRQChannelCmd = ENABLE;
+ *     NVIC_Init(&NVIC_InitStruct);
+ *
+ *     GDMA_Cmd(UART_TX_GDMA_CHANNEL_NUM, ENABLE);
+ * }
+ * \endcode
+ */
+void GDMA_INTConfig(uint8_t GDMA_ChannelNum, uint32_t GDMA_IT, FunctionalState NewState);
+
+/**
+ * \brief     Get the GDMA channel transfer interrupt status.
+ *
+ * \param[in] GDMA_ChannelNum  Select the GDMA channel number. Refer to \ref GDMA_Channel_Num.
+ *
+ * \return   Transfer interrupt status.
+ *          - SET: The GDMA channel transfer interrupt has been set.
+ *          - RESET: The GDMA channel transfer interrupt has been reset.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void gdma_demo(void)
+ * {
+ *     ITStatus int_status = GDMA_GetTransferINTStatus(GDMA_CH_NUM0);
+ * }
+ * \endcode
+ */
+ITStatus GDMA_GetTransferINTStatus(uint8_t GDMA_ChannelNum);
+
+/**
+ * \brief  Clear the specified DMA channelx interrupt pending bit.
+ *
+ * \param[in] GDMA_ChannelNum  Select the GDMA channel number. Refer to \ref GDMA_Channel_Num.
+ * \param[in] GDMA_IT          Specify the GDMA interrupts sources to be enabled or disabled.
+ *                             This parameter can be any combination of the following values.
+ *                             Refer to \ref GDMA_Interrupts.
+ *                             - GDMA_INT_Transfer: Transfer complete interrupt source.
+ *                             - GDMA_INT_Block: Block transfer interrupt source.
+ *                             - GDMA_INT_Error: Transfer error interrupt source.
+ *                             - GDMA_INT_Half_Block: Half Block transfer interrupt source.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void gdma_demo(void)
+ * {
+ *     driver_gdma_init();
+ * }
+ *
+ * void UART_TX_GDMA_Handler(void)
+ * {
+ *     GDMA_ClearINTPendingBit(GDMA_CH_NUM1, GDMA_INT_Transfer);
+ *     //Add user code here.
+ * }
+ * \endcode
+ */
+void GDMA_ClearINTPendingBit(uint8_t GDMA_ChannelNum, uint32_t GDMA_IT);
+
+/**
+ * \brief     Clear GDMAx Channelx all type interrupt.
+ *
+ * \param[in] GDMA_ChannelNum  Select the GDMA channel number. Refer to \ref GDMA_Channel_Num.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void gdma_demo(void)
+ * {
+ *     GDMA_ClearAllTypeINT(GDMA_CH_NUM2);
+ * }
+ * \endcode
+ */
+void GDMA_ClearAllTypeINT(uint8_t GDMA_ChannelNum);
+
+/**
+ * \brief   Get selected GDMA channel status.
+ *
+ * \param[in] GDMA_ChannelNum  Select the GDMA channel number. Refer to \ref GDMA_Channel_Num.
+ *
+ * \return  GDMA channel status.
+ *          -SET: Channel is be used
+ *          -RESET: Channel is free.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void gdma_demo(void)
+ * {
+ *     FlagStatus flag_status = GDMA_GetChannelStatus(GDMA_CH_NUM3);
+ * }
+ * \endcode
+ */
+FlagStatus GDMA_GetChannelStatus(uint8_t GDMA_ChannelNum);
+
+#if (GDMA_SUPPORT_SECURE_MODE == 1)
+/**
+ * \brief     Enable or disable the specified DMA channel secure function.
+ *
+ * \param[in] GDMA_Channelx  Select the GDMA peripheral. Refer to \ref GDMA_Declaration.
+ * \param[in] NewState       Specify the GDMA channel secure function.
+ *                           This parameter can be one of the following values:
+ *                           - ENABLE: Enable the specified DMA channel secure function.
+ *                           - DISABLE: Disable the specified DMA channel secure function.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void gdma_demo(void)
+ * {
+ *     GDMA_SecureCmd(GDMA_Channel3, ENABLE);
+ * }
+ *
+ * \endcode
+ */
+void GDMA_SecureCmd(GDMA_ChannelTypeDef *GDMA_Channelx, FunctionalState NewState);
+#endif
+
+#if (GDMA_SUPPORT_OSW_OSR_CHANGE == 1)
+/**
+ * \brief     Set GDMA OSW.
+ *
+ * \param[in] GDMA_ChannelNum  Select the GDMA channel number. Refer to \ref GDMA_Channel_Num.
+ * \param[in] osw_count        Outstanding write count.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void gdma_demo(void)
+ * {
+ *     GDMA_SetOSW(GDMA_CH_NUM0, 10);
+ * }
+ * \endcode
+ */
+void GDMA_SetOSW(uint8_t GDMA_ChannelNum, uint8_t osw_count);
+
+/**
+ * \brief  Set GDMA OSR.
+ *
+ * \param[in] GDMA_ChannelNum  Select the GDMA channel number. Refer to \ref GDMA_Channel_Num.
+ * \param[in] osr_count        Outstanding read count.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void gdma_demo(void)
+ * {
+ *     GDMA_SetOSR(GDMA_CH_NUM0, 10);
+ * }
+ * \endcode
+ */
+void GDMA_SetOSR(uint8_t GDMA_ChannelNum, uint8_t osr_count);
+
+/**
+ * \brief     Get GDMA OSW.
+ *
+ * \param[in] GDMA_ChannelNum  Select the GDMA channel number. Refer to \ref GDMA_Channel_Num.
+ *
+ * \return    osw_count: outstanding write count.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void gdma_demo(void)
+ * {
+ *     uint32_t osw_count = GDMA_GetOSWCount(GDMA_CH_NUM0);
+ * }
+ * \endcode
+ */
+uint8_t GDMA_GetOSWCount(uint8_t GDMA_ChannelNum);
+
+/**
+ * \brief     Get GDMA OSR.
+ *
+ * \param[in] GDMA_ChannelNum  Select the GDMA channel number. Refer to \ref GDMA_Channel_Num.
+ *
+ * \return    osr_count: outstanding read count.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void gdma_demo(void)
+ * {
+ *     uint8_t osr_count = GDMA_GetOSRCount(GDMA_CH_NUM0);
+ * }
+ * \endcode
+ */
+uint8_t GDMA_GetOSRCount(uint8_t GDMA_ChannelNum);
+#endif
+
+/**
+ * \brief     Set GDMA transmission source address.
+ *
+ * \param[in] GDMA_Channelx  Select the GDMA peripheral. Refer to \ref GDMA_Declaration.
+ * \param[in] Address        Source address.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void gdma_demo(void)
+ * {
+ *     uint32_t data_buf[10] = {0};
+ *     GDMA_SetSourceAddress(GDMA2_Channel0,(uint32_t)data_buf);
+ * }
+ * \endcode
+ */
+void GDMA_SetSourceAddress(GDMA_ChannelTypeDef *GDMA_Channelx, uint32_t Address);
+
+/**
+ * \brief     Set GDMA transmission destination address.
+ *
+ * \param[in] GDMA_Channelx  Select the GDMA peripheral. Refer to \ref GDMA_Declaration.
+ * \param[in] Address        Destination address.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void gdma_demo(void)
+ * {
+ *     uint32_t data_buf[10] = {0};
+ *     GDMA_SetDestinationAddress(GDMA_Channel0,(uint32_t)data_buf);
+ * }
+ * \endcode
+ */
+void GDMA_SetDestinationAddress(GDMA_ChannelTypeDef *GDMA_Channelx,
+                                uint32_t Address);
+
+/**
+ * \brief     Set GDMA LLP stucture address.
+ *
+ * \param[in] GDMA_Channelx  Select the GDMA peripheral. Refer to \ref GDMA_Declaration.
+ * \param[in] Address        LLP stucture address.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void gdma_demo(void)
+ * {
+ *     GDMA_LLIDef GDMA_LLIStruct[4000];
+ *     GDMA_SetLLPAddress(GDMA2_Channel0,(uint32_t)GDMA_LLIStruct);
+ * }
+ * \endcode
+ */
+void GDMA_SetLLPAddress(GDMA_ChannelTypeDef *GDMA_Channelx, uint32_t Address);
+
+/**
+ * \brief     Set GDMA buffer size.
+ *
+ * \param[in] GDMA_Channelx  Select the GDMA peripheral. Refer to \ref GDMA_Declaration.
+ * \param[in] buffer_size    Set GDMA_BufferSize, max 65535 for RTL8762G (RTL8772F: GDMA1 is 65535 and GDMA2 is 524287).
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void gdma_demo(void)
+ * {
+ *     uint32_t data_buf_size = 4095;
+ *     GDMA_SetBufferSize(GDMA_Channel0,data_buf_size);
+ * }
+ * \endcode
+ */
+void GDMA_SetBufferSize(GDMA_ChannelTypeDef *GDMA_Channelx, uint32_t buffer_size);
+
+/**
+ * \brief  Get GDMA source address.
+ *
+ * \param[in] GDMA_Channelx  Select the GDMA peripheral. Refer to \ref GDMA_Declaration.
+ *
+ * \return Source address.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void gdma_demo(void)
+ * {
+ *     uint32_t address = GDMA_GetSrcTransferAddress(GDMA2_Channel0);
+ * }
+ * \endcode
+ */
+uint32_t GDMA_GetSrcTransferAddress(GDMA_ChannelTypeDef *GDMA_Channelx);
+
+/**
+ * \brief  Get GDMA destination address.
+ *
+ * \param[in] GDMA_Channelx  Select the GDMA peripheral. Refer to \ref GDMA_Declaration.
+ *
+ * \return Destination address.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void gdma_demo(void)
+ * {
+ *     uint32_t address = GDMA_GetDstTransferAddress(GDMA2_Channel0);
+ * }
+ * \endcode
+ */
+uint32_t GDMA_GetDstTransferAddress(GDMA_ChannelTypeDef *GDMA_Channelx);
+/**
+ * \brief     Get GDMA transfer data length.
+ *
+ * \param[in] GDMA_Channelx  Select the GDMA peripheral. Refer to \ref GDMA_Declaration.
+ *
+ * \return    GDMA transfer data length.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void gdma_demo(void)
+ * {
+ *     uint16_t data_len = GDMA_GetTransferLen(GDMA2_Channel0);
+ * }
+ * \endcode
+ */
+uint16_t GDMA_GetTransferLen(GDMA_ChannelTypeDef *GDMA_Channelx);
+
+/**
+ * \brief     Check GDMA FIFO status.
+ *
+ * \param[in] GDMA_Channelx  Select the GDMA peripheral. Refer to \ref GDMA_Declaration.
+ *
+ * \return GDMA FIFO status.
+ *         - SET: FIFO empty.
+ *         - RESET: FIFO not empty.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void gdma_demo(void)
+ * {
+ *     FlagStatus flag_status = GDMA_GetFIFOStatus(GDMA2_Channel0);
+ * }
+ * \endcode
+ */
+FlagStatus GDMA_GetFIFOStatus(GDMA_ChannelTypeDef *GDMA_Channelx);
+
+/**
+ * \brief     Suspend GDMA transmission from the source.
+ *
+ * \param[in] GDMA_Channelx  Select the GDMA peripheral. Refer to \ref GDMA_Declaration.
+ * \param[in] NewState       New state of the GDMAx Channelx.
+ *                           This parameter can be one of the following values:
+ *                           - ENABLE: Enable suspend GDMA transmission.
+ *                           - DISABLE: Disable suspend GDMA transmission.
+ *
+ * \note       To prevent data loss, it is necessary to check whether FIFO data transmission is completed
+ *             after suspend, and judge by checking whether GDMA FIFO is empty.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void gdma_demo(void)
+ * {
+ *     GDMA_SuspendCmd(GDMA2_Channel0, ENABLE);
+ * }
+ * \endcode
+ */
+void GDMA_SuspendCmd(GDMA_ChannelTypeDef *GDMA_Channelx,
+                     FunctionalState NewState);
+
+/**
+ * \brief     Get GDMA Channelx of the specified DMA Channel Number.
+ *
+ * \param[in] GDMA_ChannelNum  Select the GDMA channel number. Refer to \ref GDMA_Channel_Num.
+ *
+ * \return    GDMA_Channelx.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_gdma_init(void)
+ * {
+ *     uint8_t channel_num = GDMA_CH_NUM0;
+ *     GDMA_ChannelTypeDef *GDMA_Channelx = GDMA_GetGDMAChannelx(channel_num);
+ * }
+ * \endcode
+ */
+GDMA_ChannelTypeDef *GDMA_GetGDMAChannelx(uint8_t GDMA_ChannelNum);
+
+/**
+ * \brief  Update GDMA LLP mode in multi-block.
+ *
+ * \param[in] GDMA_Channelx  Select the GDMA peripheral. Refer to \ref GDMA_Declaration.
+ * \param[in] mode           GDMA LLP mode.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void gdma_demo(void)
+ * {
+ *     GDMA_SetLLPMode(GDMA_Channel0, LLI_TRANSFER);
+ * }
+ * \endcode
+ */
+void GDMA_SetLLPMode(GDMA_ChannelTypeDef *GDMA_Channelx, uint32_t mode);
+
+/**
+ * \brief  Suspend GDMA transmission safe from the source. Please check GDMA FIFO empty to guarnatee without losing data.
+ *
+ * \param[in] GDMA_Channelx  Select the GDMA peripheral. Refer to \ref GDMA_Declaration.
+ *
+ * \return The result of suspend GDMA transmission.
+ *         - true: suspend GDMA transmission success.
+ *         - false: suspend GDMA transmission failed.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void gdma_demo(void)
+ * {
+ *     GDMA_SafeSuspend(GDMA_Channel0);
+ * }
+ * \endcode
+ */
+bool GDMA_SafeSuspend(GDMA_ChannelTypeDef *GDMA_Channelx);
+
+/** End of GDMA_Exported_Functions
+  * \}
+  */
+
+/** End of GDMA
+  * \}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RTL_GDMA_H */
+
+
diff --git a/bee/drivers/dma/src/device/rtl87x2g/rtl_gdma_def.h b/bee/drivers/dma/src/device/rtl87x2g/rtl_gdma_def.h
new file mode 100644
index 00000000..8271647c
--- /dev/null
+++ b/bee/drivers/dma/src/device/rtl87x2g/rtl_gdma_def.h
@@ -0,0 +1,796 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef RTL_GDMA_DEF_H
+#define RTL_GDMA_DEF_H
+
+#include "utils/rtl_utils.h"
+#include "address_map.h"
+
+#ifdef  __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/*============================================================================*
+ *                         GDMA Defines
+ *============================================================================*/
+/** \defgroup GDMA        GDMA
+  * \brief
+  * \{
+  */
+
+/** \defgroup GDMA_Exported_Constants GDMA Exported Constants
+  * \brief
+  * \{
+  */
+
+/**
+ * \defgroup GDMA_Defines GDMA Defines
+ * \{
+ * \ingroup  GDMA_Exported_Constants
+ */
+#define CHIP_GDMA_CHANNEL_NUM                        (10)     //!< The chip supports 10 GDMA channel.
+
+#define GDMA_SUPPORT_GATHER_SCATTER_FUNCTION         (0)      //!< The function is not supported.
+#define GDMA_SUPPORT_INT_HAIF_BLOCK                  (0)      //!< The function is not supported.
+#define GDMA_SUPPORT_SECURE_MODE                     (1)      //!< The chip supports secure mode.
+#define GDMA_SUPPORT_ADDRESS_DEC                     (1)      //!< The chip supports address decrease.
+#define GDMA_SUPPORT_OSW_OSR_CHANGE                  (1)      //!< The chip supports OSW or OSR function.
+
+/** End of GDMA_Defines
+  * \}
+  */
+
+/** End of GDMA_Exported_Constants
+  * \}
+  */
+
+/** End of GDMA
+  * \}
+  */
+
+/*============================================================================*
+ *                         GDMA Registers Memory Map
+ *============================================================================*/
+typedef struct
+{
+    __IO uint32_t GDMA_SARx;                    /*!< 0x00 */
+    __I  uint32_t GDMA_CURR_SARx;               /*!< 0x04 */
+    __IO uint32_t GDMA_DARx;                    /*!< 0x08 */
+    __I  uint32_t GDMA_CURR_DARx;               /*!< 0x0C */
+    __IO uint32_t GDMA_LLPx_L;                  /*!< 0x10 */
+    __IO uint32_t GDMA_RSVD;                    /*!< 0x14 */
+    __IO uint32_t GDMA_CTLx_L;                  /*!< 0x18 */
+    __IO uint32_t GDMA_CTLx_H;                  /*!< 0x1C */
+    __IO uint32_t GDMA_RSVD1[8];                /*!< 0x20 ~ 0x3C */
+    __IO uint32_t GDMA_CFGx_L;                  /*!< 0x40 */
+    __IO uint32_t GDMA_CFGx_H;                  /*!< 0x44 */
+    __IO uint32_t GDMA_RSVD2;                   /*!< 0x48 */
+    __IO uint32_t GDMA_RSVD3;                   /*!< 0x4C */
+    __IO uint32_t GDMA_RSVD4;                   /*!< 0x50 */
+    __IO uint32_t GDMA_RSVD5;                   /*!< 0x54 */
+} GDMA_ChannelTypeDef;
+
+typedef struct
+{
+    __IO uint32_t GDMA_RSVD[10];                /*!< 0x2C0 - 0x2E4 */
+
+    __I  uint32_t GDMA_STATUSTFR_L;             /*!< 0x2E8 */
+    __I  uint32_t GDMA_RSVD1;                   /*!< 0x2EC */
+    __I  uint32_t GDMA_STATUSBLOCK_L;           /*!< 0x2F0 */
+    __I  uint32_t GDMA_RSVD2;                   /*!< 0x2F4 */
+    __I  uint32_t GDMA_RSVD3;                   /*!< 0x2F8 */
+    __I  uint32_t GDMA_RSVD4;                   /*!< 0x2FC */
+    __I  uint32_t GDMA_RSVD5;                   /*!< 0x230 */
+    __I  uint32_t GDMA_RSVD6;                   /*!< 0x234 */
+    __I  uint32_t GDMA_STATUSERR_L;             /*!< 0x308 */
+    __I  uint32_t GDMA_RSVD7;                   /*!< 0x30C */
+
+    __IO uint32_t GDMA_MASKTFR_L;               /*!< 0x310 */
+    __IO uint32_t GDMA_RSVD8;                   /*!< 0x314 */
+    __IO uint32_t GDMA_MASKBLOCK_L;             /*!< 0x318 */
+    __IO uint32_t GDMA_RSVD9;                   /*!< 0x31C */
+    __IO uint32_t GDMA_RSVD10;                  /*!< 0x320 */
+    __IO uint32_t GDMA_RSVD11;                  /*!< 0x324 */
+    __IO uint32_t GDMA_RSVD12;                  /*!< 0x328 */
+    __IO uint32_t GDMA_RSVD13;                  /*!< 0x32C */
+    __IO uint32_t GDMA_MASKERR_L;               /*!< 0x330 */
+    __IO uint32_t GDMA_RSVD14;                  /*!< 0x32C */
+
+    __O  uint32_t GDMA_CLEARTFR_L;              /*!< 0x338 */
+    __O  uint32_t GDMA_RSVD15;                  /*!< 0x32C */
+    __O  uint32_t GDMA_CLEARBLOCK_L;            /*!< 0x340 */
+    __O  uint32_t GDMA_RSVD16;                  /*!< 0x344 */
+    __O  uint32_t GDMA_RSVD17;                  /*!< 0x348 */
+    __O  uint32_t GDMA_RSVD18;                  /*!< 0x34C */
+    __O  uint32_t GDMA_RSVD19;                  /*!< 0x350 */
+    __O  uint32_t GDMA_RSVD20;                  /*!< 0x354 */
+    __O  uint32_t GDMA_CLEARERR_L;              /*!< 0x358 */
+    __O  uint32_t GDMA_RSVD21;                  /*!< 0x354 */
+
+    __IO uint32_t GDMA_RSVD22[14];              /*!< 0x360 ~ 0x394 */
+
+    __IO uint32_t GDMA_DMACFGREG_L;             /*!< 0x398 */
+    __IO uint32_t GDMA_RSVD23;                  /*!< 0x39C */
+    __IO uint32_t GDMA_CHENREG_L;               /*!< 0x3A0 */
+    __IO uint32_t GDMA_RSVD24;                  /*!< 0x3A4 */
+
+    __IO uint32_t GDMA_RSVD25[4];               /*!< 0x3A8 ~ 0x3B4 */
+
+    __IO uint32_t GDMA_DMAOSNUM_L;              /*!< 0x3B8 */
+} GDMA_TypeDef;
+
+/*============================================================================*
+ *                         GDMA Declaration
+ *============================================================================*/
+#define GDMA0_CHANNEL_REG_BASE      (RXI350_DMAC0_CFG_REG_BASE)
+#define GDMA0_Channel0_BASE         (GDMA0_CHANNEL_REG_BASE + 0x0000)
+#define GDMA0_Channel1_BASE         (GDMA0_CHANNEL_REG_BASE + 0x0058)
+#define GDMA0_Channel2_BASE         (GDMA0_CHANNEL_REG_BASE + 0x00b0)
+#define GDMA0_Channel3_BASE         (GDMA0_CHANNEL_REG_BASE + 0x0108)
+#define GDMA0_Channel4_BASE         (GDMA0_CHANNEL_REG_BASE + 0x0160)
+#define GDMA0_Channel5_BASE         (GDMA0_CHANNEL_REG_BASE + 0x01b8)
+#define GDMA0_Channel6_BASE         (GDMA0_CHANNEL_REG_BASE + 0x0210)
+#define GDMA0_Channel7_BASE         (GDMA0_CHANNEL_REG_BASE + 0x0268)
+#define GDMA0_Channel8_BASE         (GDMA0_CHANNEL_REG_BASE + 0x0400)
+#define GDMA0_Channel9_BASE         (GDMA0_CHANNEL_REG_BASE + 0x0458)
+#define GDMA0_REG_BASE              (GDMA0_CHANNEL_REG_BASE + 0x02c0)
+
+/** \defgroup GDMA        GDMA
+  * \brief
+  * \{
+  */
+
+/** \defgroup GDMA_Exported_Constants GDMA Exported Constants
+  * \brief
+  * \{
+  */
+
+/** \defgroup GDMA_Declaration GDMA Declaration
+  * \brief
+  * \{
+  */
+
+#define GDMA0                       ((GDMA_TypeDef        *) GDMA0_REG_BASE)        //!< GDMA0 base address.
+#define GDMA_Channel0               ((GDMA_ChannelTypeDef *) GDMA0_Channel0_BASE)   //!< GDMA_Channel0 base address.
+#define GDMA_Channel1               ((GDMA_ChannelTypeDef *) GDMA0_Channel1_BASE)   //!< GDMA_Channel1 base address.
+#define GDMA_Channel2               ((GDMA_ChannelTypeDef *) GDMA0_Channel2_BASE)   //!< GDMA_Channel2 base address.
+#define GDMA_Channel3               ((GDMA_ChannelTypeDef *) GDMA0_Channel3_BASE)   //!< GDMA_Channel3 base address.
+#define GDMA_Channel4               ((GDMA_ChannelTypeDef *) GDMA0_Channel4_BASE)   //!< GDMA_Channel4 base address.
+#define GDMA_Channel5               ((GDMA_ChannelTypeDef *) GDMA0_Channel5_BASE)   //!< GDMA_Channel5 base address.
+#define GDMA_Channel6               ((GDMA_ChannelTypeDef *) GDMA0_Channel6_BASE)   //!< GDMA_Channel6 base address.
+#define GDMA_Channel7               ((GDMA_ChannelTypeDef *) GDMA0_Channel7_BASE)   //!< GDMA_Channel7 base address.
+#define GDMA_Channel8               ((GDMA_ChannelTypeDef *) GDMA0_Channel8_BASE)   //!< GDMA_Channel8 base address.
+#define GDMA_Channel9               ((GDMA_ChannelTypeDef *) GDMA0_Channel9_BASE)   //!< GDMA_Channel9 base address.
+
+#define IS_GDMA_PERIPH(PERIPH)      (((PERIPH) == GDMA_Channel0) || \
+                                     ((PERIPH) == GDMA_Channel1) || \
+                                     ((PERIPH) == GDMA_Channel2) || \
+                                     ((PERIPH) == GDMA_Channel3) || \
+                                     ((PERIPH) == GDMA_Channel4) || \
+                                     ((PERIPH) == GDMA_Channel5) || \
+                                     ((PERIPH) == GDMA_Channel6) || \
+                                     ((PERIPH) == GDMA_Channel7) || \
+                                     ((PERIPH) == GDMA_Channel8) || \
+                                     ((PERIPH) == GDMA_Channel9)) //!< Check if the input parameter is valid.
+
+#define IS_GDMA_ALL_PERIPH(PERIPH)  (IS_GDMA_PERIPH(PERIPH)) //!< Check if the input parameter is valid.
+
+/** End of GDMA_Declaration
+  * \}
+  */
+
+/** End of GDMA_Exported_Constants
+  * \}
+  */
+
+/** End of GDMA
+  * \}
+  */
+
+
+/*============================================================================*
+ *                         GDMA Registers and Field Descriptions
+ *============================================================================*/
+/* 0x00
+   31:0    R/W    sar                 undefined
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t sar: 32;
+    } b;
+} GDMA_SARx_TypeDef;
+
+
+/* 0x04
+   31:0    R      curr_sar            0x0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t curr_sar: 32;
+    } b;
+} GDMA_CURR_SARx_TypeDef;
+
+
+/* 0x08
+   31:0    R/W    dar                 undefined
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t dar: 32;
+    } b;
+} GDMA_DARx_TypeDef;
+
+
+/* 0x0C
+   31:0    R      curr_dar            0x0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t curr_dar: 32;
+    } b;
+} GDMA_CURR_DARx_TypeDef;
+
+
+/* 0x10
+   1:0     R/W    reserved13          0x0
+   31:2    R/W    loc                 0x0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t reserved_0: 2;
+        uint32_t loc: 30;
+    } b;
+} GDMA_LLPx_L_TypeDef;
+
+
+/* 0x18
+   0       R/W    int_en              0x1
+   3:1     R/W    dst_tr_width        0x0
+   6:4     R/W    src_tr_width        0x0
+   8:7     R/W    dinc                0x0
+   10:9    R/W    sinc                0x0
+   13:11   R/W    dest_msize          0x1
+   16:14   R/W    src_msize           0x1
+   17      R/W    reserved22          0x0
+   18      R/W    reserved21          0x0
+   19      R/W    reserved20          0x0
+   22:20   R/W    tt_fc               0x0
+   26:23   R      reserved18          0x0
+   27      R/W    llp_dst_en          0x0
+   28      R/W    llp_src_en          0x0
+   31:29   R      reserved15          0x0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t int_en: 1;
+        uint32_t dst_tr_width: 3;
+        uint32_t src_tr_width: 3;
+        uint32_t dinc: 2;
+        uint32_t sinc: 2;
+        uint32_t dest_msize: 3;
+        uint32_t src_msize: 3;
+        uint32_t reserved_4: 1;
+        uint32_t reserved_3: 1;
+        uint32_t reserved_2: 1;
+        uint32_t tt_fc: 3;
+        const uint32_t reserved_1: 4;
+        uint32_t llp_dst_en: 1;
+        uint32_t llp_src_en: 1;
+        const uint32_t reserved_0: 3;
+    } b;
+} GDMA_CTLx_L_TypeDef;
+
+
+
+/* 0x1C
+   31:0    R      trans_data_cnt          0x0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t trans_data_cnt: 32;
+    } b;
+} GDMA_CTLx_H_R_TypeDef;
+
+
+/* 0x1C
+   15:0    W      block_ts                0x2
+   31:16   W      reserved31              0x0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t block_ts: 16;
+        uint32_t reserved31: 16;
+    } b;
+} GDMA_CTLx_H_W_TypeDef;
+
+
+/* 0x40
+   0       R      inactive            0x1
+   1       R      reserved47          0x1
+   2       R      reserved46          0x1
+   3       R      reserved45          0x0
+   7:4     R/W    ch_prior            0x0
+   8       R/W    ch_susp             0x0
+   9       R      fifo_empty          0x1
+   10      R/W    hs_sel_dst          0x1
+   11      R/W    hs_sel_src          0x1
+   17:12   R      reserved39          0x0
+   18      R/W    reserved38          0x0
+   19      R/W    reserved37          0x0
+   29:20   R/W    reserved36          0x0
+   30      R/W    reload_src          0x0
+   31      R/W    reload_dst          0x0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t inactive: 1;
+        const uint32_t reserved_6: 1;
+        const uint32_t reserved_5: 1;
+        const uint32_t reserved_4: 1;
+        uint32_t ch_prior: 4;
+        uint32_t ch_susp: 1;
+        const uint32_t fifo_empty: 1;
+        uint32_t hs_sel_dst: 1;
+        uint32_t hs_sel_src: 1;
+        const uint32_t reserved_3: 6;
+        uint32_t reserved_2: 1;
+        uint32_t reserved_1: 1;
+        uint32_t reserved_0: 10;
+        uint32_t reload_src: 1;
+        uint32_t reload_dst: 1;
+    } b;
+} GDMA_CFGx_L_TypeDef;
+
+
+/* 0x44
+   0       R/W    reserved63          0x0
+   1       R/W    reserved62          0x0
+   2       R      reserved61          0x0
+   3       R/W    protctl             0x1
+   6:4     R      reserved59          0x0
+   10:7    R/W    src_per             0x0
+   14:11   R/W    dest_per            0x0
+   15      R/W    extended_src_per1   0x0
+   16      R/W    extended_dest_per1  0x0
+   17      R/W    extended_src_per2   0x0
+   18      R/W    extended_dest_per2  0x0
+   19      R/W    extended_src_per3   0x0
+   20      R/W    extended_dest_per3  0x0
+   31:21   R/W    reserved50          0x0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t reserved_4: 1;
+        uint32_t reserved_3: 1;
+        const uint32_t reserved_2: 1;
+        uint32_t protctl: 1;
+        const uint32_t reserved_1: 3;
+        uint32_t src_per: 4;
+        uint32_t dest_per: 4;
+        uint32_t extended_src_per1: 1;
+        uint32_t extended_dest_per1: 1;
+        uint32_t extended_src_per2: 1;
+        uint32_t extended_dest_per2: 1;
+        uint32_t extended_src_per3: 1;
+        uint32_t extended_dest_per3: 1;
+        uint32_t reserved_0: 11;
+    } b;
+} GDMA_CFGx_H_TypeDef;
+
+
+/* 0x2E8
+   31:0    R      status              0x0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t status: 32;
+    } b;
+} GDMA_STATUSTFR_L_TypeDef;
+
+
+/* 0x2F0
+   31:0    R      status              0x0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t status: 32;
+    } b;
+} GDMA_STATUSBLOCK_L_TypeDef;
+
+
+/* 0x308
+   31:0    R      status              0x0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t status: 32;
+    } b;
+} GDMA_STATUSERR_L_TypeDef;
+
+
+/* 0x310
+   7:0     R/W    int_mask_l          0x0
+   15:8    W      int_mask_we_l       0x0
+   17:16   R/W    int_mask_h          0x0
+   23:18   R/W    reserved71          0x0
+   25:24   W      int_mask_we_h       0x0
+   31:26   R      reserved69          0x0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t int_mask_l: 8;
+        uint32_t int_mask_we_l: 8;
+        uint32_t int_mask_h: 2;
+        uint32_t reserved_1: 6;
+        uint32_t int_mask_we_h: 2;
+        const uint32_t reserved_0: 6;
+    } b;
+} GDMA_MASKTFR_L_TypeDef;
+
+
+/* 0x318
+   7:0     R/W    int_mask_l          0x0
+   15:8    W      int_mask_we_l       0x0
+   17:16   R/W    int_mask_h          0x0
+   23:18   R/W    reserved78          0x0
+   25:24   W      int_mask_we_h       0x0
+   31:26   R      reserved76          0x0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t int_mask_l: 8;
+        uint32_t int_mask_we_l: 8;
+        uint32_t int_mask_h: 2;
+        uint32_t reserved_1: 6;
+        uint32_t int_mask_we_h: 2;
+        const uint32_t reserved_0: 6;
+    } b;
+} GDMA_MASKBLOCK_L_TypeDef;
+
+
+/* 0x330
+   7:0     R/W    int_mask_l          0x0
+   15:8    W      int_mask_we_l       0x0
+   17:16   R/W    int_mask_h          0x0
+   23:18   R/W    reserved85          0x0
+   25:24   W      int_mask_we_h       0x0
+   31:26   R      reserved83          0x0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t int_mask_l: 8;
+        uint32_t int_mask_we_l: 8;
+        uint32_t int_mask_h: 2;
+        uint32_t reserved_1: 6;
+        uint32_t int_mask_we_h: 2;
+        const uint32_t reserved_0: 6;
+    } b;
+} GDMA_MASKERR_L_TypeDef;
+
+
+/* 0x338
+   31:0    W      clear               0x0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t clear: 32;
+    } b;
+} GDMA_CLEARTFR_L_TypeDef;
+
+
+/* 0x340
+   31:0    W      clear               0x0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t clear: 32;
+    } b;
+} GDMA_CLEARBLOCK_L_TypeDef;
+
+
+/* 0x358
+   31:0    W      clear               0x0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t clear: 32;
+    } b;
+} GDMA_CLEARERR_L_TypeDef;
+
+
+/* 0x398
+   0       R/W    dmac_en             0x0
+   31:1    R      reserved96          0x0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t dmac_en: 1;
+        const uint32_t reserved_0: 31;
+    } b;
+} GDMA_DMACFGREG_L_TypeDef;
+
+
+/* 0x3A0
+   7:0     R/W    ch_en_l             0x0
+   15:8    W      ch_en_we_l          0x0
+   17:16   R/W    ch_en_h             0x0
+   23:18   R/W    reserved101         0x0
+   25:24   W      ch_en_we_h          0x0
+   31:26   R/W    reserved99          0x0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t ch_en_l: 8;
+        uint32_t ch_en_we_l: 8;
+        uint32_t ch_en_h: 2;
+        uint32_t reserved_1: 6;
+        uint32_t ch_en_we_h: 2;
+        uint32_t reserved_0: 6;
+    } b;
+} GDMA_CHENREG_L_TypeDef;
+
+
+
+/* 0x3B8
+   7:0     R/W    osr                 0x4
+   15:8    R/W    osw                 0x4
+   31:16   R      reserved106         0x0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t osr: 8;
+        uint32_t osw: 8;
+        const uint32_t reserved_0: 16;
+    } b;
+} GDMA_DMAOSNUM_L_TypeDef;
+
+
+/*============================================================================*
+ *                         GDMA Constants
+ *============================================================================*/
+/** \defgroup GDMA        GDMA
+  * \brief
+  * \{
+  */
+
+/** \defgroup GDMA_Exported_Constants GDMA Exported Constants
+  * \brief
+  * \{
+  */
+
+/**
+ * \defgroup GDMA_Channel_Type GDMA Channel Type
+ * \{
+ * \ingroup  GDMA_Exported_Constants
+ */
+#define GDMA_Channel0_IRQn              GDMA0_Channel0_IRQn      //!< The macro is a wrapper for GDMA0_Channel0_IRQn.
+#define GDMA_Channel1_IRQn              GDMA0_Channel1_IRQn      //!< The macro is a wrapper for GDMA0_Channel1_IRQn.
+#define GDMA_Channel2_IRQn              GDMA0_Channel2_IRQn      //!< The macro is a wrapper for GDMA0_Channel2_IRQn.
+#define GDMA_Channel3_IRQn              GDMA0_Channel3_IRQn      //!< The macro is a wrapper for GDMA0_Channel3_IRQn.
+#define GDMA_Channel4_IRQn              GDMA0_Channel4_IRQn      //!< The macro is a wrapper for GDMA0_Channel4_IRQn.
+#define GDMA_Channel5_IRQn              GDMA0_Channel5_IRQn      //!< The macro is a wrapper for GDMA0_Channel5_IRQn.
+#define GDMA_Channel6_IRQn              GDMA0_Channel6_IRQn      //!< The macro is a wrapper for GDMA0_Channel6_IRQn.
+#define GDMA_Channel7_IRQn              GDMA0_Channel7_IRQn      //!< The macro is a wrapper for GDMA0_Channel7_IRQn.
+#define GDMA_Channel8_IRQn              GDMA0_Channel8_IRQn      //!< The macro is a wrapper for GDMA0_Channel8_IRQn.
+#define GDMA_Channel9_IRQn              GDMA0_Channel9_IRQn      //!< The macro is a wrapper for GDMA0_Channel9_IRQn.
+
+#define GDMA_Channel0_Handler           GDMA0_Channel0_Handler   //!< The macro is a wrapper for GDMA0_Channel0_Handler.
+#define GDMA_Channel1_Handler           GDMA0_Channel1_Handler   //!< The macro is a wrapper for GDMA0_Channel1_Handler.
+#define GDMA_Channel2_Handler           GDMA0_Channel2_Handler   //!< The macro is a wrapper for GDMA0_Channel2_Handler.
+#define GDMA_Channel3_Handler           GDMA0_Channel3_Handler   //!< The macro is a wrapper for GDMA0_Channel3_Handler.
+#define GDMA_Channel4_Handler           GDMA0_Channel4_Handler   //!< The macro is a wrapper for GDMA0_Channel4_Handler.
+#define GDMA_Channel5_Handler           GDMA0_Channel5_Handler   //!< The macro is a wrapper for GDMA0_Channel5_Handler.
+#define GDMA_Channel6_Handler           GDMA0_Channel6_Handler   //!< The macro is a wrapper for GDMA0_Channel6_Handler.
+#define GDMA_Channel7_Handler           GDMA0_Channel7_Handler   //!< The macro is a wrapper for GDMA0_Channel7_Handler.
+#define GDMA_Channel8_Handler           GDMA0_Channel8_Handler   //!< The macro is a wrapper for GDMA0_Channel8_Handler.
+#define GDMA_Channel9_Handler           GDMA0_Channel9_Handler   //!< The macro is a wrapper for GDMA0_Channel9_Handler.
+
+/** End of GDMA_Channel_Type
+  * \}
+  */
+
+/**
+ * \defgroup    GDMA_Handshake_Type GDMA Handshake Type
+ * \{
+ * \ingroup     GDMA_Exported_Constants
+ */
+#define GDMA_Handshake_UART0_TX             (0)
+#define GDMA_Handshake_UART0_RX             (1)
+#define GDMA_Handshake_UART1_TX             (2)
+#define GDMA_Handshake_UART1_RX             (3)
+#define GDMA_Handshake_UART2_TX             (4)
+#define GDMA_Handshake_UART2_RX             (5)
+#define GDMA_Handshake_UART3_TX             (6)
+#define GDMA_Handshake_UART3_RX             (7)
+#define GDMA_Handshake_I2C0_TX              (8)
+#define GDMA_Handshake_I2C0_RX              (9)
+#define GDMA_Handshake_I2C1_TX              (10)
+#define GDMA_Handshake_I2C1_RX              (11)
+#define GDMA_Handshake_I2C2_TX              (12)
+#define GDMA_Handshake_I2C2_RX              (13)
+#define GDMA_Handshake_I2C3_TX              (14)
+#define GDMA_Handshake_I2C3_RX              (15)
+#define GDMA_Handshake_SPI0_TX              (16)
+#define GDMA_Handshake_SPI0_RX              (17)
+#define GDMA_Handshake_SPI1_TX              (18)
+#define GDMA_Handshake_SPI1_RX              (19)
+#define GDMA_Handshake_SPI_SLAVE_TX         (20)
+#define GDMA_Handshake_SPI_SLAVE_RX         (21)
+#define GDMA_Handshake_ENH_TIM0             (22)
+#define GDMA_Handshake_ENH_TIM1             (23)
+#define GDMA_Handshake_ENH_TIM2             (24)
+#define GDMA_Handshake_ENH_TIM3             (25)
+#define GDMA_Handshake_ADC_RX               (26)
+#define GDMA_Handshake_IDU_RX               (27)
+#define GDMA_Handshake_IDU_TX               (28)
+#define GDMA_Handshake_TIM5                 (29)
+#define GDMA_Handshake_TIM6                 (30)
+#define GDMA_Handshake_TIM7                 (31)
+#define GDMA_Handshake_CAN_BUS_RX           (32)
+#define GDMA_Handshake_SPIC0_TX             (33)
+#define GDMA_Handshake_SPIC0_RX             (34)
+#define GDMA_Handshake_SPIC1_TX             (35)
+#define GDMA_Handshake_SPIC1_RX             (36)
+#define GDMA_Handshake_SPIC2_TX             (37)
+#define GDMA_Handshake_SPIC2_RX             (38)
+#define GDMA_Handshake_IR_TX                (39)
+#define GDMA_Handshake_IR_RX                (40)
+#define GDMA_Handshake_I2S0_TDM0_TX         (41)
+#define GDMA_Handshake_I2S0_TDM0_RX         (42)
+#define GDMA_Handshake_I2S1_TDM0_TX         (43)
+#define GDMA_Handshake_I2S1_TDM0_RX         (44)
+#define GDMA_Handshake_SHA256_TX            (45)
+
+#define GDMA_Handshake_AES_TX               (47)
+#define GDMA_Handshake_AES_RX               (48)
+#define GDMA_Handshake_PUB_KEY_TX           (49)
+#define GDMA_Handshake_PUB_KEY_RX           (50)
+#define GDMA_Handshake_24BIT_ADC_RX         (51)
+#define GDMA_Handshake_UART4_TX             (52)
+#define GDMA_Handshake_UART4_RX             (53)
+#define GDMA_Handshake_UART5_TX             (54)
+#define GDMA_Handshake_UART5_RX             (55)
+
+#define IS_GDMA_TransferType(Type) (((Type) == GDMA_Handshake_UART0_TX)     || \
+                                    ((Type) == GDMA_Handshake_UART0_RX)     || \
+                                    ((Type) == GDMA_Handshake_UART1_TX)     || \
+                                    ((Type) == GDMA_Handshake_UART1_RX)     || \
+                                    ((Type) == GDMA_Handshake_UART2_TX)     || \
+                                    ((Type) == GDMA_Handshake_UART2_RX)     || \
+                                    ((Type) == GDMA_Handshake_UART3_TX)     || \
+                                    ((Type) == GDMA_Handshake_UART3_RX)     || \
+                                    ((Type) == GDMA_Handshake_I2C0_TX)      || \
+                                    ((Type) == GDMA_Handshake_I2C0_RX)      || \
+                                    ((Type) == GDMA_Handshake_I2C1_TX)      || \
+                                    ((Type) == GDMA_Handshake_I2C1_RX)      || \
+                                    ((Type) == GDMA_Handshake_I2C2_TX)      || \
+                                    ((Type) == GDMA_Handshake_I2C2_RX)      || \
+                                    ((Type) == GDMA_Handshake_I2C3_TX)      || \
+                                    ((Type) == GDMA_Handshake_I2C3_RX)      || \
+                                    ((Type) == GDMA_Handshake_SPI0_TX)      || \
+                                    ((Type) == GDMA_Handshake_SPI0_RX)      || \
+                                    ((Type) == GDMA_Handshake_SPI1_TX)      || \
+                                    ((Type) == GDMA_Handshake_SPI1_RX)      || \
+                                    ((Type) == GDMA_Handshake_SPI_SLAVE_TX) || \
+                                    ((Type) == GDMA_Handshake_SPI_SLAVE_RX) || \
+                                    ((Type) == GDMA_Handshake_ENH_TIM0)     || \
+                                    ((Type) == GDMA_Handshake_ENH_TIM1)     || \
+                                    ((Type) == GDMA_Handshake_ENH_TIM2)     || \
+                                    ((Type) == GDMA_Handshake_ENH_TIM3)     || \
+                                    ((Type) == GDMA_Handshake_ADC_RX)       || \
+                                    ((Type) == GDMA_Handshake_IDMC_RX)      || \
+                                    ((Type) == GDMA_Handshake_IDMC_TX)      || \
+                                    ((Type) == GDMA_Handshake_TIM5)         || \
+                                    ((Type) == GDMA_Handshake_TIM6)         || \
+                                    ((Type) == GDMA_Handshake_TIM7)         || \
+                                    ((Type) == GDMA_Handshake_CAN_BUS_RX)   || \
+                                    ((Type) == GDMA_Handshake_SPIC0_TX)     || \
+                                    ((Type) == GDMA_Handshake_SPIC0_RX)     || \
+                                    ((Type) == GDMA_Handshake_SPIC1_TX)     || \
+                                    ((Type) == GDMA_Handshake_SPIC1_RX)     || \
+                                    ((Type) == GDMA_Handshake_SPIC2_TX)     || \
+                                    ((Type) == GDMA_Handshake_SPIC2_RX)     || \
+                                    ((Type) == GDMA_Handshake_IR_TX)        || \
+                                    ((Type) == GDMA_Handshake_IR_RX)        || \
+                                    ((Type) == GDMA_Handshake_I2S0_TDM0_TX) || \
+                                    ((Type) == GDMA_Handshake_I2S0_TDM0_RX) || \
+                                    ((Type) == GDMA_Handshake_I2S1_TDM0_TX) || \
+                                    ((Type) == GDMA_Handshake_I2S1_TDM0_RX) || \
+                                    ((Type) == GDMA_Handshake_SHA256_TX)    || \
+                                    ((Type) == GDMA_Handshake_AES_TX)       || \
+                                    ((Type) == GDMA_Handshake_AES_RX)       || \
+                                    ((Type) == GDMA_Handshake_PUB_KEY_TX)   || \
+                                    ((Type) == GDMA_Handshake_PUB_KEY_RX)   || \
+                                    ((Type) == GDMA_Handshake_24BIT_ADC_RX) || \
+                                    ((Type) == GDMA_Handshake_UART4_TX)     || \
+                                    ((Type) == GDMA_Handshake_UART4_RX)     || \
+                                    ((Type) == GDMA_Handshake_UART5_TX)     || \
+                                    ((Type) == GDMA_Handshake_UART5_RX))
+
+/** End of GDMA_Handshake_Type
+  * \}
+  */
+
+/** End of GDMA_Exported_Constants
+  * \}
+  */
+
+/** End of GDMA
+  * \}
+  */
+
+#ifdef  __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* RTL_GDMA_DEF_H */
diff --git a/bee/drivers/dma/src/device/rtl87x2j/rtl87x2j_dma.c b/bee/drivers/dma/src/device/rtl87x2j/rtl87x2j_dma.c
new file mode 100644
index 00000000..b6a7b4e9
--- /dev/null
+++ b/bee/drivers/dma/src/device/rtl87x2j/rtl87x2j_dma.c
@@ -0,0 +1,146 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *                           Header Files
+ *============================================================================*/
+#include "rtl_dma.h"
+#include "rtl_rcc.h"
+
+/*============================================================================*
+ *                           Private Defines
+ *============================================================================*/
+
+/*============================================================================*
+ *                           Public Functions
+ *============================================================================*/
+DMA_TypeDef *DMA_GetDMAx(DMA_ChannelTypeDef *DMA_Channelx)
+{
+    /* Check the parameters */
+    assert_param(IS_DMA_ALL_PERIPH(DMA_Channelx));
+
+    return DMA;
+}
+
+DMA_TypeDef *DMA_GetDMAxByCh(uint8_t DMA_ChannelNum)
+{
+    /* Check the parameters */
+    assert_param(IS_DMA_ChannelNum(DMA_ChannelNum));
+
+    return DMA;
+}
+
+uint8_t DMA_GetDMAChNum(DMA_ChannelTypeDef *DMA_Channelx)
+{
+    /* Check the parameters */
+    assert_param(IS_DMA_ALL_PERIPH(DMA_Channelx));
+
+    return ((uint32_t)DMA_Channelx - (uint32_t)DMA_CH_REG_BASE) / 0x58;
+}
+
+uint8_t DMA_GetDMAChNumByCh(uint8_t DMA_ChannelNum)
+{
+    /* Check the parameters */
+    assert_param(IS_DMA_ChannelNum(DMA_ChannelNum));
+
+    return DMA_ChannelNum;
+}
+
+uint8_t DMA_GetHandshakeNum(DMA_ChannelTypeDef *DMA_Channelx, uint8_t handshake)
+{
+    /* Check the parameters */
+    assert_param(IS_DMA_ALL_PERIPH(DMA_Channelx));
+
+    return handshake;
+}
+
+DMA_ChannelTypeDef *DMA_GetDMAChannelx(uint8_t DMA_ChannelNum)
+{
+    /* Check the parameters */
+    assert_param(IS_DMA_ChannelNum(DMA_ChannelNum));
+
+    return ((DMA_ChannelTypeDef *)(DMA_CH_REG_BASE + DMA_ChannelNum * 0x0058));
+}
+
+IRQn_Type DMA_GetDMAIRQx(uint8_t DMA_ChannelNum)
+{
+    /* Check the parameters */
+    assert_param(IS_DMA_ChannelNum(DMA_ChannelNum));
+
+    return ((IRQn_Type)(DMA0_CH0_IRQn + DMA_ChannelNum));
+}
+
+uint8_t DMA_GetDMANumByIRQx(IRQn_Type irq)
+{
+    uint8_t dma_num = 0xff;
+
+    dma_num = irq - DMA0_CH0_IRQn;
+
+    return dma_num;
+}
+
+bool DMA_IsValidHandshake(uint8_t hs_src, uint8_t hs_dest)
+{
+    return true;
+}
+
+bool DMA_IsGatherScatterChannel(DMA_ChannelTypeDef *DMA_Channelx)
+{
+    return false;
+}
+
+bool DMA_IsHalfBlcokChannel(DMA_TypeDef *DMAx)
+{
+    return false;
+}
+
+bool DMA_IsSupportContinuousAddrChannel(DMA_ChannelTypeDef *DMA_Channelx)
+{
+    if (DMA_Channelx == DMA_CH3 || DMA_Channelx == DMA_CH4)
+    {
+        return true;
+    }
+    return false;
+}
+
+bool DMA_IsSupportBlockCounterChannel(DMA_ChannelTypeDef *DMA_Channelx)
+{
+    if (DMA_Channelx == DMA_CH3 || DMA_Channelx == DMA_CH4)
+    {
+        return true;
+    }
+    return false;
+}
+
+bool DMA_IsSupportRAPChannel(DMA_ChannelTypeDef *DMA_Channelx)
+{
+    if (DMA_Channelx == DMA_CH3 || DMA_Channelx == DMA_CH4)
+    {
+        return true;
+    }
+    return false;
+}
+
+void DMA_ClockAutoModeCmd(DMA_ChannelTypeDef *DMA_Channelx, FunctionalState Newstate)
+{
+    /* Check the parameters */
+    assert_param(IS_DMA_ALL_PERIPH(DMA_Channelx));
+
+    if (Newstate == ENABLE)
+    {
+        PCC_REG_WRITE_BITFIELD(PCC_REG_DMA, GDMA0_MANU_SEL, 0);
+        PCC_REG_WRITE_BITFIELD(PCC_REG_DMA, GDMA0_MANU_DAT, 0);
+    }
+    else
+    {
+        PCC_REG_WRITE_BITFIELD(PCC_REG_DMA, GDMA0_MANU_SEL, 1);
+        PCC_REG_WRITE_BITFIELD(PCC_REG_DMA, GDMA0_MANU_DAT, 1);
+    }
+
+    return;
+}
+
+
diff --git a/bee/drivers/dma/src/device/rtl87x2j/rtl_dma_def.h b/bee/drivers/dma/src/device/rtl87x2j/rtl_dma_def.h
new file mode 100644
index 00000000..2648072d
--- /dev/null
+++ b/bee/drivers/dma/src/device/rtl87x2j/rtl_dma_def.h
@@ -0,0 +1,768 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef RTL_DMA_DEF_H
+#define RTL_DMA_DEF_H
+
+#include "utils/rtl_utils.h"
+#include "address_map.h"
+#include "vector_table.h"
+
+#ifdef  __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/*============================================================================*
+ *                         DMA Defines
+ *============================================================================*/
+/** \defgroup DMA        DMA
+  * \brief
+  * \{
+  */
+
+/** \defgroup DMA_Exported_Constants DMA Exported Constants
+  * \brief
+  * \{
+  */
+
+/**
+ * \defgroup DMA_Defines DMA Defines
+ * \{
+ * \ingroup  DMA_Exported_Constants
+ */
+#define CHIP_DMA_CHANNEL_NUM                        (6)
+
+#define DMA_SUPPORT_GATHER_SCATTER_FUNCTION         (0)
+#define DMA_SUPPORT_INT_HAIF_BLOCK                  (0)
+#define DMA_SUPPORT_SECURE_MODE                     (0)
+#define DMA_SUPPORT_ADDRESS_DECREASE                (1)
+#define DMA_SUPPORT_OSW_OSR_CHANGE                  (0)
+#define DMA_SUPPORT_RAP_FUNCTION                    (1)
+#define DMA_SUPPORT_CONTINUOUS_BLOCK_ADDRESS        (1)
+#define DMA_SUPPORT_BLOCK_COUNTER                   (1)
+#define DMA_SUPPORT_AUTO_CLOCK                      (1)
+#define DMA_SUPPORT_DATA_SIZE_DOUBLE_WORD           (0)
+#define DMA_SUPPORT_MSIZE_64                        (1)
+#define DMA_SUPPORT_MSIZE_128                       (1)
+#define DMA_SUPPORT_MSIZE_256                       (1)
+#define DMA_SUPPORT_MSIZE_BIGGER_THAN_FIFO_DEPTH    (0)
+#define DMA_MEMORY_BARRIER_BEFORE_ENABLE            (0)
+#define DMA_READ_REG_AFTER_CLEAR                    (0)
+#define DMA_SUPPORT_PERIPHERAL_FLOW_CONTROL         (0)
+#define DMA_SUPPORT_AUTO_SLOW_CONFIG                (0)
+
+/** End of DMA_Defines
+  * \}
+  */
+
+/** End of DMA_Exported_Constants
+  * \}
+  */
+
+/** End of DMA
+  * \}
+  */
+
+/*============================================================================*
+ *                         DMA Registers Memory Map
+ *============================================================================*/
+typedef struct
+{
+    __IO uint32_t DMA_SARx;                    /*!< 0x00 */
+    __I  uint32_t DMA_CURR_SARx;               /*!< 0x04 */
+    __IO uint32_t DMA_DARx;                    /*!< 0x08 */
+    __I  uint32_t DMA_CURR_DARx;               /*!< 0x0C */
+    __IO uint32_t DMA_LLPx_L;                  /*!< 0x10 */
+    __IO uint32_t DMA_RSVD;                    /*!< 0x14 */
+    __IO uint32_t DMA_CTLx_L;                  /*!< 0x18 */
+    __IO uint32_t DMA_CTLx_H;                  /*!< 0x1C */
+    __IO uint32_t DMA_BLK_COUNTER_REGx;        /*!< 0x20 */
+    __IO uint32_t DMA_RSVD1[7];                /*!< 0x24 ~ 0x3C */
+    __IO uint32_t DMA_CFGx_L;                  /*!< 0x40 */
+    __IO uint32_t DMA_CFGx_H;                  /*!< 0x44 */
+    __IO uint32_t DMA_RSVD2;                   /*!< 0x48 */
+    __IO uint32_t DMA_RSVD3;                   /*!< 0x4C */
+    __IO uint32_t DMA_RSVD4;                   /*!< 0x50 */
+    __IO uint32_t DMA_RSVD5;                   /*!< 0x54 */
+} DMA_ChannelTypeDef;
+
+typedef struct
+{
+    __IO uint32_t DMA_RSVD[10];                /*!< 0x2C0 - 0x2E4 */
+
+    __I  uint32_t DMA_STATUSTFR_L;             /*!< 0x2E8 */
+    __I  uint32_t DMA_STATUSTFR_H;             /*!< 0x2EC */
+    __I  uint32_t DMA_STATUSBLOCK_L;           /*!< 0x2F0 */
+    __I  uint32_t DMA_RSVD2;                   /*!< 0x2F4 */
+    __I  uint32_t DMA_RSVD3;                   /*!< 0x2F8 */
+    __I  uint32_t DMA_RSVD4;                   /*!< 0x2FC */
+    __I  uint32_t DMA_RSVD5;                   /*!< 0x230 */
+    __I  uint32_t DMA_RSVD6;                   /*!< 0x234 */
+    __I  uint32_t DMA_STATUSERR_L;             /*!< 0x308 */
+    __I  uint32_t DMA_RSVD7;                   /*!< 0x30C */
+
+    __IO uint32_t DMA_MASKTFR_L;               /*!< 0x310 */
+    __IO uint32_t DMA_MASKTFR_H;               /*!< 0x314 */
+    __IO uint32_t DMA_MASKBLOCK_L;             /*!< 0x318 */
+    __IO uint32_t DMA_RSVD8;                   /*!< 0x31C */
+    __IO uint32_t DMA_RSVD9;                   /*!< 0x320 */
+    __IO uint32_t DMA_RSVD10;                  /*!< 0x324 */
+    __IO uint32_t DMA_RSVD11;                  /*!< 0x328 */
+    __IO uint32_t DMA_RSVD12;                  /*!< 0x32C */
+    __IO uint32_t DMA_MASKERR_L;               /*!< 0x330 */
+    __IO uint32_t DMA_RSVD13;                  /*!< 0x334 */
+
+    __O  uint32_t DMA_CLEARTFR_L;              /*!< 0x338 */
+    __O  uint32_t DMA_CLEARTFR_H;              /*!< 0x33C */
+    __O  uint32_t DMA_CLEARBLOCK_L;            /*!< 0x340 */
+    __O  uint32_t DMA_RSVD14;                  /*!< 0x344 */
+    __O  uint32_t DMA_RSVD15;                  /*!< 0x348 */
+    __O  uint32_t DMA_RSVD16;                  /*!< 0x34C */
+    __O  uint32_t DMA_RSVD17;                  /*!< 0x350 */
+    __O  uint32_t DMA_RSVD18;                  /*!< 0x354 */
+    __O  uint32_t DMA_CLEARERR_L;              /*!< 0x358 */
+    __O  uint32_t DMA_RSVD19;                  /*!< 0x35C */
+
+    __IO uint32_t DMA_RSVD20[14];              /*!< 0x360 ~ 0x394 */
+
+    __IO uint32_t DMA_DMACFGREG_L;              /*!< 0x398 */
+    __IO uint32_t DMA_RSVD21;                   /*!< 0x39C */
+    __IO uint32_t DMA_CHENREG_L;                /*!< 0x3A0 */
+    __IO uint32_t DMA_RSVD22;                   /*!< 0x3A4 */
+
+    __IO uint32_t DMA_RSVD23[6];                /*!< 0x3A8 ~ 0x3BC */
+} DMA_TypeDef;
+
+/*============================================================================*
+ *                         DMA Declaration
+ *============================================================================*/
+/** \defgroup DMA        DMA
+  * \brief
+  * \{
+  */
+
+/** \defgroup DMA_Exported_Constants DMA Exported Constants
+  * \brief
+  * \{
+  */
+
+/** \defgroup DMA_Declaration DMA Declaration
+  * \brief
+  * \{
+  */
+
+#define DMA_CH_REG_BASE             (RXI350_CFG_BASE)
+#define DMA_REG_BASE                (DMA_CH_REG_BASE + 0x02C0)
+#define DMA_CH0_BASE                (DMA_CH_REG_BASE + 0x0000)
+#define DMA_CH1_BASE                (DMA_CH_REG_BASE + 0x0058)
+#define DMA_CH2_BASE                (DMA_CH_REG_BASE + 0x00B0)
+#define DMA_CH3_BASE                (DMA_CH_REG_BASE + 0x0108)
+#define DMA_CH4_BASE                (DMA_CH_REG_BASE + 0x0160)
+#define DMA_CH5_BASE                (DMA_CH_REG_BASE + 0x01B8)
+
+#define DMA                         ((DMA_TypeDef        *) DMA_REG_BASE)
+#define DMA_CH0                     ((DMA_ChannelTypeDef *) DMA_CH0_BASE)
+#define DMA_CH1                     ((DMA_ChannelTypeDef *) DMA_CH1_BASE)
+#define DMA_CH2                     ((DMA_ChannelTypeDef *) DMA_CH2_BASE)
+#define DMA_CH3                     ((DMA_ChannelTypeDef *) DMA_CH3_BASE)
+#define DMA_CH4                     ((DMA_ChannelTypeDef *) DMA_CH4_BASE)
+#define DMA_CH5                     ((DMA_ChannelTypeDef *) DMA_CH5_BASE)
+
+#define IS_DMA_PERIPH(PERIPH)       (((PERIPH) == DMA_CH0) || \
+                                     ((PERIPH) == DMA_CH1) || \
+                                     ((PERIPH) == DMA_CH2) || \
+                                     ((PERIPH) == DMA_CH3) || \
+                                     ((PERIPH) == DMA_CH4) || \
+                                     ((PERIPH) == DMA_CH5))
+#define IS_DMA_ALL_PERIPH(PERIPH)   (IS_DMA1_PERIPH(PERIPH))
+
+/** End of DMA_Declaration
+  * \}
+  */
+
+/** End of DMA_Exported_Constants
+  * \}
+  */
+
+/** End of DMA
+  * \}
+  */
+
+
+/*============================================================================*
+ *                         DMA Registers and Field Descriptions
+ *============================================================================*/
+/* 0x00
+   31:0    R/W    sar                 0x0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t sar: 32;
+    } b;
+} DMA_SARx_TypeDef;
+
+
+/* 0x04
+   31:0    R      curr_sar            0x0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t curr_sar: 32;
+    } b;
+} DMA_CURR_SARx_TypeDef;
+
+
+/* 0x08
+   31:0    R/W    dar                 0x0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t dar: 32;
+    } b;
+} DMA_DARx_TypeDef;
+
+
+/* 0x0C
+   31:0    R      curr_dar            0x0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t curr_dar: 32;
+    } b;
+} DMA_CURR_DARx_TypeDef;
+
+
+/* 0x10
+   1:0     R/W    reserved14          0x0
+   31:2    R/W    loc                 0x0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t reserved_0: 2;
+        uint32_t loc: 30;
+    } b;
+} DMA_LLPx_L_TypeDef;
+
+
+/* 0x18
+   0       R/W    int_en              0x1
+   3:1     R/W    dst_tr_width        0x0
+   6:4     R/W    src_tr_width        0x0
+   8:7     R/W    dinc                0x0
+   10:9    R/W    sinc                0x0
+   13:11   R/W    dest_msize          0x1
+   16:14   R/W    src_msize           0x1
+   17      R/W    reserved25          0x0
+   18      R/W    reserved24          0x0
+   19      R/W    reserved23          0x0
+   23:20   R/W    tt_fc               0x0
+   26:24   R      reserved21          0x0
+   27      R/W    llp_dst_en          0x0
+   28      R/W    llp_src_en          0x0
+   31:29   R      reserved18          0x0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t int_en: 1;
+        uint32_t dst_tr_width: 3;
+        uint32_t src_tr_width: 3;
+        uint32_t dinc: 2;
+        uint32_t sinc: 2;
+        uint32_t dest_msize: 3;
+        uint32_t src_msize: 3;
+        uint32_t reserved_4: 1;
+        uint32_t reserved_3: 1;
+        uint32_t reserved_2: 1;
+        uint32_t tt_fc: 4;
+        const uint32_t reserved_1: 3;
+        uint32_t llp_dst_en: 1;
+        uint32_t llp_src_en: 1;
+        const uint32_t reserved_0: 3;
+    } b;
+} DMA_CTLx_L_TypeDef;
+
+
+/* 0x1C
+   31:0    R      trans_data_cnt          0x0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t trans_data_cnt: 32;
+    } b;
+} DMA_CTLx_H_R_TypeDef;
+
+
+/* 0x1C
+   15:0    W      block_ts                0x2
+   31:16   W      reserved31              0x0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t block_ts: 16;
+        uint32_t reserved31: 16;
+    } b;
+} DMA_CTLx_H_W_TypeDef;
+
+
+/* 0x20
+   15:0    R/W    blk_counter_reg     0x0
+   31:16   R      reserved37          0x0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t blk_counter_reg: 16;
+        const uint32_t reserved_0: 16;
+    } b;
+} DMA_BLK_COUNTER_REGx_TypeDef;
+
+
+/* 0x40
+   0       R      inactive            0x1
+   1       R      src_pctl_over       0x1
+   2       R      dst_pctl_over       0x1
+   3       R      reserved53          0x0
+   7:4     R/W    ch_prior            0x0
+   8       R/W    ch_susp             0x0
+   9       R      fifo_empty          0x1
+   10      R/W    hs_sel_dst          0x1
+   11      R/W    hs_sel_src          0x1
+   17:12   R      reserved47          0x0
+   18      R      dst_hs_pol          0x0
+   19      R      src_hs_pol          0x0
+   29:20   R      reserved44          0x0
+   30      R/W    reload_src          0x0
+   31      R/W    reload_dst          0x0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t inactive: 1;
+        const uint32_t src_pctl_over: 1;
+        const uint32_t dst_pctl_over: 1;
+        const uint32_t reserved_2: 1;
+        uint32_t ch_prior: 4;
+        uint32_t ch_susp: 1;
+        const uint32_t fifo_empty: 1;
+        uint32_t hs_sel_dst: 1;
+        uint32_t hs_sel_src: 1;
+        const uint32_t reserved_1: 6;
+        const uint32_t dst_hs_pol: 1;
+        const uint32_t src_hs_pol: 1;
+        const uint32_t reserved_0: 10;
+        uint32_t reload_src: 1;
+        uint32_t reload_dst: 1;
+    } b;
+} DMA_CFGx_L_TypeDef;
+
+
+/* 0x44
+   0       R/W    fcmode              0x0
+   1       R/W    reserved72          0x0
+   2       R      reserved71          0x0
+   3       R/W    reserved70          0x1
+   4       R/W    direct_ctl_en       0x0
+   5       R/W    cont_sar            0x0
+   6       R/W    cont_dar            0x0
+   10:7    R/W    src_per             0x0
+   14:11   R/W    dest_per            0x0
+   15      R/W    extended_src_per1   0x0
+   16      R/W    extended_dest_per1  0x0
+   17      R/W    extended_src_per2   0x0
+   18      R/W    extended_dest_per2  0x0
+   19      R/W    extended_src_per3   0x0
+   20      R/W    extended_dest_per3  0x0
+   31:21   R      reserved58          0x0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t fcmode: 1;
+        uint32_t reserved_5: 1;
+        const uint32_t reserved_4: 1;
+        uint32_t reserved_3: 1;
+        uint32_t direct_ctl_en: 1;
+        uint32_t cont_sar: 1;
+        uint32_t cont_dar: 1;
+        uint32_t src_per: 4;
+        uint32_t dest_per: 4;
+        uint32_t extended_src_per1: 1;
+        uint32_t extended_dest_per1: 1;
+        uint32_t extended_src_per2: 1;
+        uint32_t extended_dest_per2: 1;
+        uint32_t extended_src_per3: 1;
+        uint32_t extended_dest_per3: 1;
+        const uint32_t reserved_0: 11;
+    } b;
+} DMA_CFGx_H_TypeDef;
+
+
+/* 0x2E8
+   15:0    R      status_tfr          0x0
+   31:16   R      reserved108         0x0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t status_tfr: 16;
+        const uint32_t reserved_0: 16;
+    } b;
+} DMA_STATUSTFR_L_TypeDef;
+
+
+/* 0x2EC
+   15:0    R      status_tfr_h        0x0
+   31:16   R      reserved111         0x0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t status_tfr_h: 16;
+        const uint32_t reserved_0: 16;
+    } b;
+} DMA_STATUSTFR_H_TypeDef;
+
+
+/* 0x2F0
+   15:0    R      status_block        0x0
+   31:16   R      reserved114         0x0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t status_block: 16;
+        const uint32_t reserved_0: 16;
+    } b;
+} DMA_STATUSBLOCK_L_TypeDef;
+
+
+/* 0x308
+   15:0    R      status_err          0x0
+   31:16   R      reserved120         0x0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t status_err: 16;
+        const uint32_t reserved_0: 16;
+    } b;
+} DMA_STATUSERR_L_TypeDef;
+
+
+/* 0x310
+   7:0     R/W    int_mask            0x0
+   15:8    W      int_mask_we         0x0
+   23:16   R/W    int_mask            0x0
+   31:24   W      int_mask_we         0x0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t int_mask_2: 8;
+        uint32_t int_mask_we_2: 8;
+        uint32_t int_mask: 8;
+        uint32_t int_mask_we: 8;
+    } b;
+} DMA_MASKTFR_L_TypeDef;
+
+
+/* 0x314
+   7:0     R/W    int_mask            0x0
+   15:8    W      int_mask_we         0x0
+   23:16   R/W    int_mask            0x0
+   31:24   W      int_mask_we         0x0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t int_mask_2: 8;
+        uint32_t int_mask_we_2: 8;
+        uint32_t int_mask: 8;
+        uint32_t int_mask_we: 8;
+    } b;
+} DMA_MASKTFR_H_TypeDef;
+
+
+/* 0x318
+   7:0     R/W    int_mask            0x0
+   15:8    W      int_mask_we         0x0
+   23:16   R/W    int_mask            0x0
+   31:24   W      int_mask_we         0x0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t int_mask_2: 8;
+        uint32_t int_mask_we_2: 8;
+        uint32_t int_mask: 8;
+        uint32_t int_mask_we: 8;
+    } b;
+} DMA_MASKBLOCK_L_TypeDef;
+
+
+/* 0x330
+   7:0     R/W    int_mask            0x0
+   15:8    W      int_mask_we         0x0
+   23:16   R/W    int_mask            0x0
+   31:24   W      int_mask_we         0x0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t int_mask_2: 8;
+        uint32_t int_mask_we_2: 8;
+        uint32_t int_mask: 8;
+        uint32_t int_mask_we: 8;
+    } b;
+} DMA_MASKERR_L_TypeDef;
+
+
+/* 0x338
+   15:0    W1C    clear_tfr           0x0
+   31:16   R      reserved156         0x0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t clear_tfr: 16;
+        const uint32_t reserved_0: 16;
+    } b;
+} DMA_CLEARTFR_L_TypeDef;
+
+
+/* 0x33C
+   15:0    W1C    clear_tfr_h         0x0
+   31:16   R      reserved159         0x0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t clear_tfr_h: 16;
+        const uint32_t reserved_0: 16;
+    } b;
+} DMA_CLEARTFR_H_TypeDef;
+
+
+/* 0x340
+   15:0    W1C    clear_block         0x0
+   31:16   R      reserved162         0x0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t clear_block: 16;
+        const uint32_t reserved_0: 16;
+    } b;
+} DMA_CLEARBLOCK_L_TypeDef;
+
+
+/* 0x358
+   15:0    W1C    clear_protocolerror 0x0
+   31:16   R      reserved168         0x0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t clear_protocolerror: 16;
+        const uint32_t reserved_0: 16;
+    } b;
+} DMA_CLEARERR_L_TypeDef;
+
+
+/* 0x398
+   0       R/W    dma_en              0x1
+   31:1    R      reserved184         0x0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t dma_en: 1;
+        const uint32_t reserved_0: 31;
+    } b;
+} DMA_DMACFGREG_L_TypeDef;
+
+
+/* 0x3A0
+   5:0     R/W    ch_en               0x0
+   7:6     R      reserved191         0x0
+   13:8    W      ch_en_we            0x0
+   31:14   R      reserved189         0x0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t ch_en: 6;
+        const uint32_t reserved_1: 2;
+        uint32_t ch_en_we: 6;
+        const uint32_t reserved_0: 18;
+    } b;
+} DMA_CHENREG_L_TypeDef;
+
+
+/*============================================================================*
+ *                         DMA Constants
+ *============================================================================*/
+/** \defgroup DMA        DMA
+  * \brief
+  * \{
+  */
+
+/** \defgroup DMA_Exported_Constants DMA Exported Constants
+  * \brief
+  * \{
+  */
+
+/**
+ * \defgroup    DMA_HANDSHAKE DMA HANDSHAKE
+ * \{
+ * \ingroup     DMA_Exported_Constants
+ */
+#define DMA_HANDSHAKE_UART0_TX                                    (0)
+#define DMA_HANDSHAKE_UART0_RX                                    (1)
+#define DMA_HANDSHAKE_UART1_TX                                    (2)
+#define DMA_HANDSHAKE_UART1_RX                                    (3)
+#define DMA_HANDSHAKE_SPI0_TX                                     (4)
+#define DMA_HANDSHAKE_SPI0_RX                                     (5)
+#define DMA_HANDSHAKE_SPI1_TX                                     (6)
+#define DMA_HANDSHAKE_SPI1_RX                                     (7)
+#define DMA_HANDSHAKE_I2C0_TX                                     (8)
+#define DMA_HANDSHAKE_I2C0_RX                                     (9)
+#define DMA_HANDSHAKE_I2C1_TX                                     (10)
+#define DMA_HANDSHAKE_I2C1_RX                                     (11)
+#define DMA_HANDSHAKE_ADC_RX                                      (12)
+#define DMA_HANDSHAKE_AES_TX                                      (13)
+#define DMA_HANDSHAKE_AES_RX                                      (14)
+#define DMA_HANDSHAKE_SPIC0_TX                                    (15)
+#define DMA_HANDSHAKE_I2S0_TX                                     (16)
+#define DMA_HANDSHAKE_I2S0_RX                                     (17)
+#define DMA_HANDSHAKE_UART2_TX                                    (18)
+#define DMA_HANDSHAKE_UART2_RX                                    (19)
+#define DMA_HANDSHAKE_UART3_TX                                    (20)
+#define DMA_HANDSHAKE_UART3_RX                                    (21)
+#define DMA_HANDSHAKE_SPIC0_RX                                    (22)
+#define DMA_HANDSHAKE_TIMER2_TRX                                  (23)
+#define DMA_HANDSHAKE_SPI2_TX                                     (24)
+#define DMA_HANDSHAKE_SPI2_RX                                     (25)
+#define DMA_HANDSHAKE_IR_TX                                       (27)
+#define DMA_HANDSHAKE_IR_RX                                       (28)
+#define DMA_HANDSHAKE_CANBUS_RX                                   (29)
+#define DMA_HANDSHAKE_SHA256_TX                                   (30)
+#define DMA_HANDSHAKE_TIMER1_6_TRX                                (31)
+#define DMA_HANDSHAKE_TIMER1_7_TRX                                (32)
+#define DMA_HANDSHAKE_TIMER1_8_TRX                                (33)
+
+
+#define IS_DMA_TransferType(Type) (((Type) == DMA_HANDSHAKE_UART0_TX) || \
+                                   ((Type) == DMA_HANDSHAKE_UART0_RX) || \
+                                   ((Type) == DMA_HANDSHAKE_UART1_TX) || \
+                                   ((Type) == DMA_HANDSHAKE_UART1_RX) || \
+                                   ((Type) == DMA_HANDSHAKE_SPI0_TX) || \
+                                   ((Type) == DMA_HANDSHAKE_SPI0_RX) || \
+                                   ((Type) == DMA_HANDSHAKE_SPI1_TX) || \
+                                   ((Type) == DMA_HANDSHAKE_SPI1_RX) || \
+                                   ((Type) == DMA_HANDSHAKE_I2C0_TX) || \
+                                   ((Type) == DMA_HANDSHAKE_I2C0_RX) || \
+                                   ((Type) == DMA_HANDSHAKE_I2C1_TX) || \
+                                   ((Type) == DMA_HANDSHAKE_I2C1_RX) || \
+                                   ((Type) == DMA_HANDSHAKE_ADC_RX) || \
+                                   ((Type) == DMA_HANDSHAKE_AES_TX) || \
+                                   ((Type) == DMA_HANDSHAKE_AES_RX) || \
+                                   ((Type) == DMA_HANDSHAKE_SPIC0_TX) || \
+                                   ((Type) == DMA_HANDSHAKE_I2S0_TX) || \
+                                   ((Type) == DMA_HANDSHAKE_I2S0_RX) || \
+                                   ((Type) == DMA_HANDSHAKE_UART2_TX) || \
+                                   ((Type) == DMA_HANDSHAKE_UART2_RX) || \
+                                   ((Type) == DMA_HANDSHAKE_UART3_TX) || \
+                                   ((Type) == DMA_HANDSHAKE_UART3_RX) || \
+                                   ((Type) == DMA_HANDSHAKE_SPIC0_RX) || \
+                                   ((Type) == DMA_HANDSHAKE_TIMER2_TRX) || \
+                                   ((Type) == DMA_HANDSHAKE_SPI2_TX) || \
+                                   ((Type) == DMA_HANDSHAKE_SPI2_RX) || \
+                                   ((Type) == DMA_HANDSHAKE_IR_TX) || \
+                                   ((Type) == DMA_HANDSHAKE_IR_RX) || \
+                                   ((Type) == DMA_HANDSHAKE_CAN_RX) || \
+                                   ((Type) == DMA_HANDSHAKE_SHA256_TX) || \
+                                   ((Type) == DMA_HANDSHAKE_TIMER1_6_TRX) || \
+                                   ((Type) == DMA_HANDSHAKE_TIMER1_7_TRX) || \
+                                   ((Type) == DMA_HANDSHAKE_TIMER1_8_TRX))
+
+
+/** End of DMA_HANDSHAKE
+  * \}
+  */
+
+/** End of DMA_Exported_Constants
+  * \}
+  */
+
+/** End of DMA
+  * \}
+  */
+
+#ifdef  __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* RTL_DMA_DEF_H */
+
diff --git a/bee/drivers/dma/src/device/rtl_common/rtl_dma.c b/bee/drivers/dma/src/device/rtl_common/rtl_dma.c
new file mode 100644
index 00000000..fa733862
--- /dev/null
+++ b/bee/drivers/dma/src/device/rtl_common/rtl_dma.c
@@ -0,0 +1,1088 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *                           Header Files
+ *============================================================================*/
+#include "rtl_dma.h"
+#include "rtl_rcc.h"
+
+/*============================================================================*
+ *                           Private Defines
+ *============================================================================*/
+/* DMA Suspend Flag */
+#define DMA_FIFO_STATUS                 (BIT(9))
+#define DMA_SUSPEND_TRANSMISSSION       (BIT(8))
+#define DMA_SUSPEND_CMD_STATUS          (BIT(2) | BIT(1))
+#define DMA_SUSPEND_CHANNEL_STATUS      (BIT(0))
+
+/* DMA Channel Bit */
+#define CHANNEL_BIT(ch)                 ((ch < 8) ? BIT(ch) : BIT(ch + 8))
+#define CHANNEL_WE_BIT(ch)              ((ch < 8) ? BIT(ch + 8) : BIT(ch + 16))
+
+/*============================================================================*
+ *                           Private Functions
+ *============================================================================*/
+extern uint8_t DMA_GetDMAChNumByCh(uint8_t DMA_ChannelNum);
+extern DMA_TypeDef *DMA_GetDMAxByCh(uint8_t DMA_ChannelNum);
+extern DMA_TypeDef *DMA_GetDMAx(DMA_ChannelTypeDef *DMA_Channelx);
+extern uint8_t DMA_GetHandshakeNum(DMA_ChannelTypeDef *DMA_Channelx, uint8_t handshake);
+extern bool DMA_IsValidHandshake(uint8_t hs_src, uint8_t hs_dest);
+extern bool DMA_IsGatherScatterChannel(DMA_ChannelTypeDef *DMA_Channelx);
+extern bool DMA_IsHalfBlcokChannel(DMA_TypeDef *DMAx);
+extern bool DMA_IsSupportContinuousAddrChannel(DMA_ChannelTypeDef *DMA_Channelx);
+extern bool DMA_IsSupportBlockCounterChannel(DMA_ChannelTypeDef *DMA_Channelx);
+extern bool DMA_IsSupportRAPChannel(DMA_ChannelTypeDef *DMA_Channelx);
+FlagStatus DMA_GetSuspendCmdStatus(DMA_ChannelTypeDef *DMA_Channelx);
+FlagStatus DMA_GetSuspendChannelStatus(DMA_ChannelTypeDef *DMA_Channelx);
+#if (DMA_SUPPORT_MSIZE_BIGGER_THAN_FIFO_DEPTH == 1)
+extern void DMA_CheckDataSizeAndMsize(DMA_ChannelTypeDef *DMA_Channelx,
+                                      DMA_InitTypeDef *DMA_InitStruct);
+#endif
+/*============================================================================*
+ *                           Public Functions
+ *============================================================================*/
+/**
+  * \brief  Deinitializes the DMA registers to their default reset values.
+  * \param  None
+  * \return None
+  */
+void DMA_DeInit(void)
+{
+    /* Disable DMA clock */
+#ifdef IS_DMA_PERIPH
+    RCC_ClockCmd(DMA_CLOCK, DISABLE);
+#endif
+#ifdef IS_DMA1_PERIPH
+    RCC_ClockCmd(DMA1_CLOCK, DISABLE);
+#endif
+#ifdef IS_DMA2_PERIPH
+    RCC_ClockCmd(DMA2_CLOCK, DISABLE);
+#endif
+}
+
+/**
+  * \brief  Initializes the DMA Channelx according to the specified
+  *         parameters in the DMA_InitStruct.
+  * \param  DMA_Channelx: Select the DMA peripheral. \ref DMA_Declaration
+  * \param  DMA_InitStruct: pointer to a DMA_InitTypeDef structure that
+  *         contains the configuration information for the specified DMA Channel.
+  * \return None.
+  */
+void DMA_Init(DMA_ChannelTypeDef *DMA_Channelx, DMA_InitTypeDef *DMA_InitStruct)
+{
+    /* Check the parameters */
+    assert_param(IS_DMA_ALL_PERIPH(DMA_Channelx));
+    assert_param(IS_DMAx_ChannelNum(DMA_InitStruct->DMA_ChannelNum));
+    assert_param(IS_DMA_DIR(DMA_InitStruct->DMA_Direction));
+    assert_param(IS_DMA_SourceInc(DMA_InitStruct->DMA_SourceInc));
+    assert_param(IS_DMA_DestinationInc(DMA_InitStruct->DMA_DestinationInc));
+    assert_param(IS_DMA_DATA_SIZE(DMA_InitStruct->DMA_SourceDataSize));
+    assert_param(IS_DMA_DATA_SIZE(DMA_InitStruct->DMA_DestinationDataSize));
+
+    DMA_TypeDef *DMAx = DMA_GetDMAx(DMA_Channelx);
+    uint8_t channel_num = DMA_GetDMAChNumByCh(DMA_InitStruct->DMA_ChannelNum);
+    uint8_t temp_hs_src = DMA_GetHandshakeNum(DMA_Channelx, DMA_InitStruct->DMA_SourceHandshake);
+    uint8_t temp_hs_dst = DMA_GetHandshakeNum(DMA_Channelx, DMA_InitStruct->DMA_DestHandshake);
+
+    /* ---------------- Configure source and destination address of DMA ---------------- */
+    /* Program SARx register to set source address */
+    DMA_Channelx->DMA_SARx = DMA_InitStruct->DMA_SourceAddr;
+    /* Program DARx register to set destination address */
+    DMA_Channelx->DMA_DARx = DMA_InitStruct->DMA_DestinationAddr;
+
+    /* Enable DMA in DmaCfgReg */
+    DMAx->DMA_DMACFGREG_L = 0x01;
+
+    /* ---------------- DMA Configuration ---------------- */
+    /* Clear pending interrupts of corresponding DMA channel */
+    uint32_t temp_bit = BIT(channel_num);
+    DMAx->DMA_CLEARTFR_L = temp_bit;
+#if (DMA_SUPPORT_BLOCK_COUNTER == 1)
+    DMAx->DMA_CLEARTFR_H = temp_bit;
+#endif
+    DMAx->DMA_CLEARBLOCK_L = temp_bit;
+#if (DMA_SUPPORT_INT_HAIF_BLOCK == 1)
+    DMAx->DMA_CLEARBLOCK_H = temp_bit;
+#endif
+    DMAx->DMA_CLEARERR_L = temp_bit;
+
+    /* Mask pending interrupts of corresponding DMA channel */
+    temp_bit = CHANNEL_WE_BIT(channel_num);
+    DMAx->DMA_MASKTFR_L = temp_bit;
+#if (DMA_SUPPORT_BLOCK_COUNTER == 1)
+    DMAx->DMA_MASKTFR_H = temp_bit;
+#endif
+    DMAx->DMA_MASKBLOCK_L = temp_bit;
+#if (DMA_SUPPORT_INT_HAIF_BLOCK == 1)
+    DMAx->DMA_MASKBLOCK_H = temp_bit;
+#endif
+    DMAx->DMA_MASKERR_L = temp_bit;
+
+#if (DMA_SUPPORT_MSIZE_BIGGER_THAN_FIFO_DEPTH == 1)
+    DMA_CheckDataSizeAndMsize(DMA_Channelx, DMA_InitStruct);
+#endif
+
+    /* ---------------- Configure CTL register ---------------- */
+    /* Config low 32 bits of CTL register  */
+    DMA_CTLx_L_TypeDef dma_ctlxl = {.d32 = DMA_Channelx->DMA_CTLx_L};
+    dma_ctlxl.b.int_en = ENABLE;
+    dma_ctlxl.b.dst_tr_width = DMA_InitStruct->DMA_DestinationDataSize;
+    dma_ctlxl.b.src_tr_width = DMA_InitStruct->DMA_SourceDataSize;
+    dma_ctlxl.b.dinc = DMA_InitStruct->DMA_DestinationInc;
+    dma_ctlxl.b.sinc = DMA_InitStruct->DMA_SourceInc;
+    dma_ctlxl.b.dest_msize = DMA_InitStruct->DMA_DestinationMsize;
+    dma_ctlxl.b.src_msize = DMA_InitStruct->DMA_SourceMsize;
+    dma_ctlxl.b.tt_fc = DMA_InitStruct->DMA_Direction;
+    DMA_Channelx->DMA_CTLx_L = dma_ctlxl.d32;
+
+    /* Config high 32 bits of CTL register */
+    DMA_Channelx->DMA_CTLx_H = DMA_InitStruct->DMA_BufferSize;
+
+    /* ---------------- Configure CFG register ---------------- */
+    DMA_CFGx_L_TypeDef dma_cfgxl = {.d32 = DMA_Channelx->DMA_CFGx_L};
+    switch (DMA_InitStruct->DMA_Direction)
+    {
+    case DMA_DIR_MEMORY_TO_MEMORY:
+        dma_cfgxl.b.hs_sel_dst = 0x1;
+        dma_cfgxl.b.hs_sel_src = 0x1;
+        break;
+    case DMA_DIR_MEMORY_TO_PERIPHERAL:
+        dma_cfgxl.b.hs_sel_dst = 0x0;
+        dma_cfgxl.b.hs_sel_src = 0x1;
+        break;
+    case DMA_DIR_PERIPHERAL_TO_MEMORY:
+        dma_cfgxl.b.hs_sel_dst = 0x1;
+        dma_cfgxl.b.hs_sel_src = 0x0;
+        break;
+    case DMA_DIR_PERIPHERAL_TO_PERIPHERAL:
+        dma_cfgxl.b.hs_sel_dst = 0x0;
+        dma_cfgxl.b.hs_sel_src = 0x0;
+        break;
+    default:
+        dma_cfgxl.b.hs_sel_dst = 0x0;
+        dma_cfgxl.b.hs_sel_src = 0x0;
+        break;
+    }
+    DMA_Channelx->DMA_CFGx_L = dma_cfgxl.d32;
+
+    /* Set DMA channel priority level */
+    dma_cfgxl.b.ch_prior = DMA_InitStruct->DMA_ChannelPriority;
+    DMA_Channelx->DMA_CFGx_L = dma_cfgxl.d32;
+
+    /* Set for secure mode */
+    DMA_CFGx_H_TypeDef dma_cfgxh = {.d32 = DMA_Channelx->DMA_CFGx_H};
+
+#if (DMA_SUPPORT_SECURE_MODE == 1)
+    if (DMA_InitStruct->DMA_SecureEn == 1)
+    {
+        dma_cfgxh.b.protctl = 0x0;
+    }
+    DMA_Channelx->DMA_CFGx_H = dma_cfgxh.d32;
+#endif
+
+#if (DMA_SUPPORT_CONTINUOUS_BLOCK_ADDRESS == 1)
+    if (DMA_IsSupportContinuousAddrChannel(DMA_Channelx))
+    {
+        dma_cfgxh.b.cont_sar = DMA_InitStruct->DMA_ContSarEn;
+        dma_cfgxh.b.cont_dar = DMA_InitStruct->DMA_ContDarEn;
+        DMA_Channelx->DMA_CFGx_H = dma_cfgxh.d32;
+    }
+#endif
+
+#if (DMA_SUPPORT_BLOCK_COUNTER == 1)
+    if (DMA_IsSupportContinuousAddrChannel(DMA_Channelx))
+    {
+        DMA_Channelx->DMA_BLK_COUNTER_REGx = DMA_InitStruct->DMA_BlockCounter;
+    }
+#endif
+
+    /* Config multi-block mode */
+    if (DMA_InitStruct->DMA_MultiBlockEn == 1)
+    {
+        if (DMA_InitStruct->DMA_MultiBlockMode & LLP_SELECTED_BIT)
+        {
+            DMA_Channelx->DMA_LLPx_L = DMA_InitStruct->DMA_MultiBlockStruct;
+            dma_ctlxl.b.llp_dst_en = (DMA_InitStruct->DMA_MultiBlockMode & BIT27) >> 27;
+            dma_ctlxl.b.llp_src_en = (DMA_InitStruct->DMA_MultiBlockMode & BIT28) >> 28;
+            DMA_Channelx->DMA_CTLx_L = dma_ctlxl.d32;
+        }
+        dma_cfgxl.b.reload_src = (DMA_InitStruct->DMA_MultiBlockMode & BIT30) >> 30;
+        dma_cfgxl.b.reload_dst = (DMA_InitStruct->DMA_MultiBlockMode & BIT31) >> 31;
+        DMA_Channelx->DMA_CFGx_L = dma_cfgxl.d32;
+    }
+    else
+    {
+        /* Clear automatic source/destination reload */
+        dma_cfgxl.b.reload_src = 0x0;
+        dma_cfgxl.b.reload_dst = 0x0;
+        DMA_Channelx->DMA_CFGx_L = dma_cfgxl.d32;
+        /* Clear LLI for source/destination */
+        dma_ctlxl.b.llp_dst_en = 0x0;
+        dma_ctlxl.b.llp_src_en = 0x0;
+        DMA_Channelx->DMA_CTLx_L = dma_ctlxl.d32;
+    }
+
+    /* ---------------- Set handshake ---------------- */
+    /* Configure peripheral parameters and configure source or destination hardware handshaking interface */
+    if (DMA_IsValidHandshake(temp_hs_src, temp_hs_dst) == true)
+    {
+        dma_cfgxh.b.src_per = temp_hs_src & 0x0F;
+        dma_cfgxh.b.extended_src_per1 = (temp_hs_src & 0x10) >> 4;
+        dma_cfgxh.b.extended_src_per2 = (temp_hs_src & 0x20) >> 5;
+        dma_cfgxh.b.extended_src_per3 = (temp_hs_src & 0x40) >> 6;
+
+        dma_cfgxh.b.dest_per = temp_hs_dst & 0x0F;
+        dma_cfgxh.b.extended_dest_per1 = (temp_hs_dst & 0x10) >> 4;
+        dma_cfgxh.b.extended_dest_per2 = (temp_hs_dst & 0x20) >> 5;
+        dma_cfgxh.b.extended_dest_per3 = (temp_hs_dst & 0x40) >> 6;
+
+        DMA_Channelx->DMA_CFGx_H = dma_cfgxh.d32;
+    }
+
+    /* ---------------- Configure scatter and gather ---------------- */
+#if (DMA_SUPPORT_GATHER_SCATTER_FUNCTION == 1)
+    /* Set for gather */
+    if (DMA_IsGatherScatterChannel(DMA_Channelx))
+    {
+        dma_ctlxl.b.src_gather_en = DMA_InitStruct->DMA_GatherEn;
+        DMA_Channelx->DMA_CTLx_L = dma_ctlxl.d32;
+
+        if (DMA_InitStruct->DMA_GatherEn == 1)
+        {
+            DMA_SGRx_L_TypeDef dma_sgrxl = {.d32 = DMA_Channelx->DMA_SGRx_L};
+            dma_sgrxl.b.sgi = DMA_InitStruct->DMA_GatherInterval & 0xFFFFF;
+            dma_sgrxl.b.sgc = DMA_InitStruct->DMA_GatherCount & 0xFFF;
+            DMA_Channelx->DMA_SGRx_L = dma_sgrxl.d32;
+
+            DMA_SGRx_H_TypeDef dma_sgrxh = {.d32 = DMA_Channelx->DMA_SGRx_H};
+            dma_sgrxh.b.sgsn = DMA_InitStruct->DMA_GatherCircularStreamingNum;
+            DMA_Channelx->DMA_SGRx_H = dma_sgrxh.d32;
+        }
+    }
+    /* Set for scatter */
+    if (DMA_IsGatherScatterChannel(DMA_Channelx))
+    {
+        dma_ctlxl.b.dst_scatter_en = DMA_InitStruct->DMA_ScatterEn;
+        DMA_Channelx->DMA_CTLx_L = dma_ctlxl.d32;
+
+        if ((DMA_InitStruct->DMA_ScatterEn == 1))
+        {
+            DMA_DSRx_L_TypeDef dma_dsrxl = {.d32 = DMA_Channelx->DMA_DSRx_L};
+            dma_dsrxl.b.dsi = DMA_InitStruct->DMA_ScatterInterval & 0xFFFFF;
+            dma_dsrxl.b.dsc = DMA_InitStruct->DMA_ScatterCount & 0xFFF;
+            DMA_Channelx->DMA_DSRx_L = dma_dsrxl.d32;
+
+            DMA_DSRx_H_TypeDef dma_dsrxh = {.d32 = DMA_Channelx->DMA_DSRx_H};
+            dma_dsrxh.b.dssn = DMA_InitStruct->DMA_ScatterCircularStreamingNum;
+            DMA_Channelx->DMA_DSRx_H = dma_dsrxh.d32;
+        }
+    }
+#endif
+
+    /* Clear pending interrupts of corresponding DMA channel */
+    temp_bit = BIT(channel_num);
+    DMAx->DMA_CLEARTFR_L = temp_bit;
+#if (DMA_SUPPORT_BLOCK_COUNTER == 1)
+    DMAx->DMA_CLEARTFR_H = temp_bit;
+#endif
+    DMAx->DMA_CLEARBLOCK_L = temp_bit;
+#if (DMA_SUPPORT_INT_HAIF_BLOCK == 1)
+    DMAx->DMA_CLEARBLOCK_H = temp_bit;
+#endif
+    DMAx->DMA_CLEARERR_L = temp_bit;
+}
+
+/**
+  * \brief  Fills each DMA_InitStruct member with its default value.
+  * \param  DMA_InitStruct: pointer to a DMA_InitTypeDef structure which will
+  *         be initialized.
+  * \return None.
+  */
+void DMA_StructInit(DMA_InitTypeDef *DMA_InitStruct)
+{
+    /*-------------- Reset DMA init structure parameters values ------------------*/
+    DMA_InitStruct->DMA_ChannelNum            = 0;
+    DMA_InitStruct->DMA_Direction             = DMA_DIR_PERIPHERAL_TO_MEMORY;
+    DMA_InitStruct->DMA_BufferSize            = 200;
+    DMA_InitStruct->DMA_SourceInc             = DMA_SOURCE_FIX;
+    DMA_InitStruct->DMA_DestinationInc        = DMA_DESTINATION_INC;
+    DMA_InitStruct->DMA_SourceDataSize        = DMA_DATA_SIZE_BYTE;
+    DMA_InitStruct->DMA_DestinationDataSize   = DMA_DATA_SIZE_BYTE;
+    DMA_InitStruct->DMA_SourceMsize           = DMA_MSIZE_1;
+    DMA_InitStruct->DMA_DestinationMsize      = DMA_MSIZE_1;
+    DMA_InitStruct->DMA_SourceAddr            = 0;
+    DMA_InitStruct->DMA_DestinationAddr       = 0;
+    DMA_InitStruct->DMA_SourceHandshake       = 0;
+    DMA_InitStruct->DMA_DestHandshake         = 0;
+    DMA_InitStruct->DMA_ChannelPriority       = 4;
+
+    DMA_InitStruct->DMA_MultiBlockEn          = DISABLE;
+    DMA_InitStruct->DMA_MultiBlockMode        = LLI_TRANSFER;
+    DMA_InitStruct->DMA_MultiBlockStruct      = 0;
+
+#if (DMA_SUPPORT_GATHER_SCATTER_FUNCTION == 1)
+    DMA_InitStruct->DMA_GatherEn             = DISABLE;
+    DMA_InitStruct->DMA_GatherCount           = 0;
+    DMA_InitStruct->DMA_GatherInterval        = 0;
+    DMA_InitStruct->DMA_ScatterEn            = DISABLE;
+    DMA_InitStruct->DMA_ScatterCount          = 0;
+    DMA_InitStruct->DMA_ScatterInterval       = 0;
+    DMA_InitStruct->DMA_GatherCircularStreamingNum = 0;
+    DMA_InitStruct->DMA_ScatterCircularStreamingNum = 0;
+#endif
+
+#if (DMA_SUPPORT_SECURE_MODE == 1)
+    DMA_InitStruct->DMA_SecureEn             = ENABLE;
+#endif
+
+#if (DMA_SUPPORT_CONTINUOUS_BLOCK_ADDRESS == 1)
+    DMA_InitStruct->DMA_ContSarEn             = DISABLE;
+    DMA_InitStruct->DMA_ContDarEn             = DISABLE;
+#endif
+
+#if (DMA_SUPPORT_BLOCK_COUNTER == 1)
+    DMA_InitStruct->DMA_BlockCounter          = 0;
+#endif
+}
+
+/**
+  * \brief  Enables or disables the specified DMA Channelx.
+  * \param  DMA_ChannelNum: Select the DMA channel number. \ref DMA_CHANNEL_NUM
+  * \param  NewState: new state of the DMA Channelx.
+  *         This parameter can be: ENABLE or DISABLE.
+  * \return None.
+  */
+void DMA_Cmd(uint8_t DMA_ChannelNum, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_DMA_ChannelNum(DMA_ChannelNum));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    uint8_t bit_need_set_times = 10;
+    uint8_t bit_need_check_times = 50;
+    uint8_t timeout = bit_need_check_times ;
+    uint8_t bit_set_time = 0;
+
+    DMA_TypeDef *DMAx = DMA_GetDMAxByCh(DMA_ChannelNum);
+    uint8_t channel_num = DMA_GetDMAChNumByCh(DMA_ChannelNum);
+    DMA_ChannelTypeDef *DMA_Channelx = DMA_GetDMAChannelx(DMA_ChannelNum);
+
+    if (NewState == ENABLE)
+    {
+#if (DMA_MEMORY_BARRIER_BEFORE_ENABLE == 1)
+        __DSB();
+#endif
+        /* Enable the selected DMA Channel */
+        DMAx->DMA_CHENREG_L = CHANNEL_BIT(channel_num) | CHANNEL_WE_BIT(channel_num);
+    }
+    else if (NewState == DISABLE)
+    {
+        /* Disable the selected DMA Channel */
+
+        /* DMA transfer not finished */
+        if (DMAx->DMA_CHENREG_L & CHANNEL_BIT(channel_num))
+        {
+            /* suspend dma channel */
+            DMA_Channelx->DMA_CFGx_L |= DMA_SUSPEND_TRANSMISSSION;
+        }
+        /* Polling fifo empty */
+        while ((DMA_GetSuspendChannelStatus(DMA_Channelx) != SET) && --timeout);
+
+        /*cfg bit0 not set */
+        if (DMA_GetSuspendChannelStatus(DMA_Channelx) != SET)
+        {
+            timeout = bit_need_check_times;
+            /* Polling cfg[1:2] 10 times set in 100timer check */
+            while (--timeout)
+            {
+                if (DMA_GetSuspendCmdStatus(DMA_Channelx))
+                {
+                    bit_set_time++;
+                    if (bit_set_time >= bit_need_set_times)
+                    {
+                        break;
+                    }
+                }
+            }
+        }
+
+        /* Disable the selected DMAy Channelx */
+        DMAx->DMA_CHENREG_L = CHANNEL_WE_BIT(channel_num);
+
+        /* unsuspend dma channel */
+        DMA_Channelx->DMA_CFGx_L &= ~(DMA_SUSPEND_TRANSMISSSION);
+    }
+}
+
+/**
+  * \brief  Enables or disables the specified DMA Channelx interrupts.
+  * \param  DMA_ChannelNum: Select the DMA channel number. \ref DMA_CHANNEL_NUM
+  * \param  DMA_IT: specifies the DMA interrupts sources to be enabled or disabled.
+  *         This parameter can be any combination of the following values:
+  *         \arg DMA_INT_TRANSFER:  Transfer complete interrupt unmask
+  *         \arg DMA_INT_BLOCK:  Block transfer interrupt unmask
+  *         \arg DMA_INT_ERROR :  Transfer error interrupt unmask
+  *         \arg DMA_INT_HALF_BLOCK: Half Block transfer interrupt unmask
+  * \param  NewState: new state of the specified DMA interrupts.
+  *         This parameter can be: ENABLE or DISABLE.
+  * \return None.
+  */
+void DMA_INTConfig(uint8_t DMA_ChannelNum, uint32_t DMA_IT, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_DMAx_ChannelNum(DMA_ChannelNum));
+    assert_param(IS_DMA_CONFIG_IT(DMA_IT));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    DMA_TypeDef *DMAx = DMA_GetDMAxByCh(DMA_ChannelNum);
+    uint8_t channel_num = DMA_GetDMAChNumByCh(DMA_ChannelNum);
+    DMA_ChannelTypeDef *DMA_Channelx = DMA_GetDMAChannelx(DMA_ChannelNum);
+    uint32_t temp_bit = 0;
+
+    if (NewState == ENABLE)
+    {
+        /* Enable the selected DMA interrupts */
+        temp_bit = CHANNEL_BIT(channel_num) | CHANNEL_WE_BIT(channel_num);
+    }
+    else
+    {
+        /* Disable the selected DMA interrupts */
+        temp_bit = CHANNEL_WE_BIT(channel_num);
+    }
+
+    if (DMA_IT & DMA_INT_TRANSFER)
+    {
+        DMAx->DMA_MASKTFR_L = temp_bit;
+    }
+#if (DMA_SUPPORT_BLOCK_COUNTER == 1)
+    if ((DMA_IT & DMA_INT_BLOCK_COUNTER) && DMA_IsSupportBlockCounterChannel(DMA_Channelx))
+    {
+        DMAx->DMA_MASKTFR_H = temp_bit;
+    }
+#endif
+    if (DMA_IT & DMA_INT_BLOCK)
+    {
+        DMAx->DMA_MASKBLOCK_L = temp_bit;
+    }
+#if (DMA_SUPPORT_INT_HAIF_BLOCK == 1)
+    if ((DMA_IT & DMA_INT_HALF_BLOCK) && DMA_IsHalfBlcokChannel(DMAx))
+    {
+        DMAx->DMA_MASKBLOCK_H = temp_bit;
+    }
+#endif
+    if (DMA_IT & DMA_INT_ERROR)
+    {
+        DMAx->DMA_MASKERR_L = temp_bit;
+    }
+}
+
+/**
+  * \brief  Check whether DMA Channel transfer interrupt is set.
+  * \param  DMA_ChannelNum: Select the DMA channel number. \ref DMA_CHANNEL_NUM
+  * \return Transfer interrupt status, SET or RESET.
+  */
+ITStatus DMA_GetTransferINTStatus(uint8_t DMA_ChannelNum)
+{
+    /* Check the parameters */
+    assert_param(IS_DMA_ChannelNum(DMAx_Channel_Num));
+
+    DMA_TypeDef *DMAx = DMA_GetDMAxByCh(DMA_ChannelNum);
+    uint8_t channel_num = DMA_GetDMAChNumByCh(DMA_ChannelNum);
+
+    if ((DMAx->DMA_STATUSTFR_L & BIT(channel_num)) != (uint32_t)RESET)
+    {
+        return SET;
+    }
+    return RESET;
+}
+
+/**
+  * \brief  Check whether DMA Channel block interrupt is set.
+  * \param  DMA_ChannelNum: Select the DMA channel number. \ref DMA_CHANNEL_NUM.
+  * \param  DMA_IT: specifies the DMA interrupts status to get.
+  *         This parameter can be any combination of the following values:
+  *         \arg DMA_INT_TRANSFER:  Transfer complete interrupt status.
+  *         \arg DMA_INT_BLOCK:  Block transfer interrupt status.
+  *         \arg DMA_INT_ERROR :  Transfer error interrupt status.
+  *         \arg DMA_INT_HALF_BLOCK: Half Block transfer interrupt status.
+  *         \arg DMA_INT_BLOCK_COUNTER: Block counter interrupt status.
+  * \return Block interrupt status, SET or RESET.
+  */
+ITStatus DMA_GetINTStatus(uint8_t DMA_ChannelNum, uint32_t DMA_IT)
+{
+    /* Check the parameters */
+    assert_param(IS_DMA_ChannelNum(DMAx_Channel_Num));
+
+    DMA_TypeDef *DMAx = DMA_GetDMAxByCh(DMA_ChannelNum);
+    uint8_t channel_num = DMA_GetDMAChNumByCh(DMA_ChannelNum);
+
+    if (DMA_IT & DMA_INT_TRANSFER)
+    {
+        if ((DMAx->DMA_STATUSTFR_L & BIT(channel_num)) != (uint32_t)RESET)
+        {
+            return SET;
+        }
+    }
+
+#if (DMA_SUPPORT_BLOCK_COUNTER == 1)
+    DMA_ChannelTypeDef *DMA_Channelx = DMA_GetDMAChannelx(DMA_ChannelNum);
+    if ((DMA_IT & DMA_INT_BLOCK_COUNTER) && DMA_IsSupportBlockCounterChannel(DMA_Channelx))
+    {
+        if ((DMAx->DMA_STATUSTFR_H & BIT(channel_num)) != (uint32_t)RESET)
+        {
+            return SET;
+        }
+    }
+#endif
+
+    if (DMA_IT & DMA_INT_BLOCK)
+    {
+        if ((DMAx->DMA_STATUSBLOCK_L & BIT(channel_num)) != (uint32_t)RESET)
+        {
+            return SET;
+        }
+    }
+
+#if (DMA_SUPPORT_INT_HAIF_BLOCK == 1)
+    if ((DMA_IT & DMA_INT_HALF_BLOCK) && DMA_IsHalfBlcokChannel(DMAx))
+    {
+        if ((DMAx->DMA_STATUSBLOCK_H & BIT(channel_num)) != (uint32_t)RESET)
+        {
+            return SET;
+        }
+    }
+#endif
+
+    if (DMA_IT & DMA_INT_ERROR)
+    {
+        if ((DMAx->DMA_STATUSERR_L & BIT(channel_num)) != (uint32_t)RESET)
+        {
+            return SET;
+        }
+    }
+
+    return RESET;
+}
+
+/**
+  * \brief  Clear the specified DMA Channelx interrupts.
+  * \param  DMA_ChannelNum: Select the DMA channel number. \ref DMA_CHANNEL_NUM
+  * \param  DMA_IT: specifies the DMA interrupts sources to be enabled
+  *         or disabled.
+  *         This parameter can be any combination of the following values:
+  *         \arg DMA_INT_TRANSFER:  clear transfer complete interrupt.
+  *         \arg DMA_INT_BLOCK:  clear Block transfer interrupt.
+  *         \arg DMA_INT_ERROR  :  clear Transfer error interrupt.
+  *         \arg DMA_INT_HALF_BLOCK:  clear Half Block transfer interrupt.
+  * \param  NewState: new state of the specified DMA interrupts.
+  *         This parameter can be: ENABLE or DISABLE.
+  * \return None.
+  */
+void DMA_ClearINTPendingBit(uint8_t DMA_ChannelNum, uint32_t DMA_IT)
+{
+    /* Check the parameters */
+    assert_param(IS_DMAx_ChannelNum(DMAx_ChannelNum));
+    assert_param(IS_DMA_CONFIG_IT(DMA_IT));
+
+    DMA_TypeDef *DMAx = DMA_GetDMAxByCh(DMA_ChannelNum);
+    uint8_t channel_num = DMA_GetDMAChNumByCh(DMA_ChannelNum);
+    DMA_ChannelTypeDef *DMA_Channelx = DMA_GetDMAChannelx(DMA_ChannelNum);
+    uint32_t temp_bit = BIT(channel_num);
+
+    /* clear the selected DMA interrupts */
+    if (DMA_IT & DMA_INT_TRANSFER)
+    {
+        DMAx->DMA_CLEARTFR_L = temp_bit;
+#if (DMA_READ_REG_AFTER_CLEAR == 1)
+        DMAx->DMA_CLEARTFR_L;
+#endif
+    }
+#if (DMA_SUPPORT_BLOCK_COUNTER == 1)
+    if ((DMA_IT & DMA_INT_BLOCK_COUNTER) && DMA_IsSupportBlockCounterChannel(DMA_Channelx))
+    {
+        DMAx->DMA_CLEARTFR_H = temp_bit;
+#if (DMA_READ_REG_AFTER_CLEAR == 1)
+        DMAx->DMA_CLEARTFR_H;
+#endif
+    }
+#endif
+    if (DMA_IT & DMA_INT_BLOCK)
+    {
+        DMAx->DMA_CLEARBLOCK_L = temp_bit;
+#if (DMA_READ_REG_AFTER_CLEAR == 1)
+        DMAx->DMA_CLEARBLOCK_L;
+#endif
+    }
+#if (DMA_SUPPORT_INT_HAIF_BLOCK == 1)
+    if ((DMA_IT & DMA_INT_HALF_BLOCK) && DMA_IsHalfBlcokChannel(DMAx))
+    {
+        DMAx->DMA_CLEARBLOCK_H = temp_bit;
+#if (DMA_READ_REG_AFTER_CLEAR == 1)
+        DMAx->DMA_CLEARBLOCK_H;
+#endif
+    }
+#endif
+    if (DMA_IT & DMA_INT_ERROR)
+    {
+        DMAx->DMA_CLEARERR_L = temp_bit;
+#if (DMA_READ_REG_AFTER_CLEAR == 1)
+        DMAx->DMA_CLEARERR_L;
+#endif
+    }
+}
+
+/**
+  * \brief  Clear DMAx Channelx all type interrupt.
+  * \param  DMA_ChannelNum: Select the DMA channel number. \ref DMA_CHANNEL_NUM
+  * \return None.
+  */
+void DMA_ClearAllTypeINT(uint8_t DMA_ChannelNum)
+{
+    /* Check the parameters */
+    assert_param(IS_DMA_Num(DMAx));
+    assert_param(IS_DMA_ChannelNum(DMA_Channel_Num));
+
+    DMA_TypeDef *DMAx = DMA_GetDMAxByCh(DMA_ChannelNum);
+    uint8_t channel_num = DMA_GetDMAChNumByCh(DMA_ChannelNum);
+    uint32_t temp_bit = BIT(channel_num);
+
+    DMAx->DMA_CLEARTFR_L = temp_bit;
+#if (DMA_SUPPORT_BLOCK_COUNTER == 1)
+    DMAx->DMA_CLEARTFR_H = temp_bit;
+#endif
+    DMAx->DMA_CLEARBLOCK_L = temp_bit;
+#if (DMA_SUPPORT_INT_HAIF_BLOCK == 1)
+    DMAx->DMA_CLEARBLOCK_H = temp_bit;
+#endif
+    DMAx->DMA_CLEARERR_L = temp_bit;
+
+#if (DMA_READ_REG_AFTER_CLEAR == 1)
+    DMAx->DMA_CLEARTFR_L;
+#endif
+}
+
+/**
+  * \brief  Get selected DMA channel status.
+  * \param  DMA_ChannelNum: Select the DMA channel number. \ref DMA_CHANNEL_NUM
+  * \return DMA channel status: can be SET or RESET.
+  * \return None.
+  */
+FlagStatus DMA_GetChannelStatus(uint8_t DMA_ChannelNum)
+{
+    /* Check the parameters */
+    assert_param(IS_DMA_ChannelNum(DMA_ChannelNum));
+
+    DMA_TypeDef *DMAx = DMA_GetDMAxByCh(DMA_ChannelNum);
+    uint8_t channel_num = DMA_GetDMAChNumByCh(DMA_ChannelNum);
+
+    if ((DMAx->DMA_CHENREG_L & CHANNEL_BIT(channel_num)) != (uint32_t)RESET)
+    {
+        return SET;
+    }
+    return  RESET;
+}
+
+/**
+ * \brief  Check DMA FIFO status.
+ * \param  DMA_Channelx: Select the DMA peripheral. \ref DMA_Declaration
+ * \return DMA FIFO status.
+ */
+FlagStatus DMA_GetFIFOStatus(DMA_ChannelTypeDef *DMA_Channelx)
+{
+    /* Check the parameters */
+    assert_param(IS_DMA_ALL_PERIPH(DMA_Channelx));
+
+    if ((DMA_Channelx->DMA_CFGx_L & DMA_FIFO_STATUS) != (uint32_t)RESET)
+    {
+        if (DMA_GetSuspendCmdStatus(DMA_Channelx))
+        {
+            return SET;
+        }
+    }
+    return  RESET;
+}
+
+/**
+ * \brief  Check DMA suspend command status.
+ * \param  DMA_Channelx: Select the DMA peripheral. \ref DMA_Declaration
+ * \return DMA suspend command status.
+ */
+FlagStatus DMA_GetSuspendCmdStatus(DMA_ChannelTypeDef *DMA_Channelx)
+{
+    /* Check the parameters */
+    assert_param(IS_DMA_ALL_PERIPH(DMA_Channelx));
+
+    if ((DMA_Channelx->DMA_CFGx_L & DMA_SUSPEND_CMD_STATUS) == DMA_SUSPEND_CMD_STATUS)
+    {
+        return SET;
+    }
+    return  RESET;
+}
+
+/**
+ * \brief  Check DMA suspend channel status.
+ * \param  DMA_Channelx: Select the DMA peripheral. \ref DMA_Declaration
+ * \return DMA suspend channel status.
+ */
+FlagStatus DMA_GetSuspendChannelStatus(DMA_ChannelTypeDef *DMA_Channelx)
+{
+    /* Check the parameters */
+    assert_param(IS_DMA_ALL_PERIPH(DMA_Channelx));
+
+    if ((DMA_Channelx->DMA_CFGx_L & DMA_SUSPEND_CHANNEL_STATUS) == DMA_SUSPEND_CHANNEL_STATUS)
+    {
+        return SET;
+    }
+    return  RESET;
+}
+
+/**
+ * \brief  Suspend DMA transmission from the source.
+  * \param  DMA_Channelx: Select the DMA peripheral. \ref DMA_Declaration
+ * \param  NewState: New state of the DMAx Channelx.
+ * \return None.
+ */
+void DMA_SuspendCmd(DMA_ChannelTypeDef *DMA_Channelx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_DMA_ALL_PERIPH(DMA_Channelx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (NewState == DISABLE)
+    {
+        /* Not suspend transmission*/
+        DMA_Channelx->DMA_CFGx_L &= ~(DMA_SUSPEND_TRANSMISSSION);
+    }
+    else
+    {
+        /* Suspend transmission */
+        DMA_Channelx->DMA_CFGx_L |= DMA_SUSPEND_TRANSMISSSION;
+    }
+}
+
+/**
+  * \brief  Suspend DMA transmission safe from the source.Please check DMA FIFO empty to guarnatee without losing data.
+  * \param  DMA_Channelx: Select the DMA peripheral. \ref DMA_Declaration
+  * \return true: suspend success, false: suspend failed
+  */
+bool DMA_SafeSuspend(DMA_ChannelTypeDef *DMA_Channelx)
+{
+    /* Check the parameters */
+    assert_param(IS_DMA_ALL_PERIPH(DMA_Channelx));
+
+    uint8_t bit_set_time = 0;
+    uint8_t bit_need_set_times = 10;
+    uint8_t bit_need_check_times = 50;
+    uint8_t timeout = bit_need_check_times;
+
+    /* Suspend transmission */
+    DMA_Channelx->DMA_CFGx_L |= DMA_SUSPEND_TRANSMISSSION;
+
+    /* Disable the selected DMAy Channelx */
+    /* polling fifo empty */
+    while ((DMA_GetSuspendChannelStatus(DMA_Channelx) != SET) && timeout--);
+    if (DMA_GetSuspendChannelStatus(DMA_Channelx) != SET)
+    {
+        timeout = bit_need_check_times;
+        /*polling cfg[1:2] 10 times set in 100timer check */
+        while (--timeout)
+        {
+            if (DMA_GetSuspendCmdStatus(DMA_Channelx))
+            {
+                bit_set_time++;
+                if (bit_set_time >= bit_need_set_times)
+                {
+                    break;
+                }
+            }
+        }
+        if (timeout == 0)
+        {
+            /* unsuspend dma channel */
+            DMA_Channelx->DMA_CFGx_L &= ~(DMA_SUSPEND_TRANSMISSSION);
+            return false;
+        }
+    }
+
+    return true;
+}
+
+/**
+ * \brief  Set DMA transmission source address.
+  * \param  DMA_Channelx: Select the DMA peripheral. \ref DMA_Declaration
+ * \param  Address: Source address.
+ * \return None.
+ */
+void DMA_SetSourceAddress(DMA_ChannelTypeDef *DMA_Channelx, uint32_t Address)
+{
+    /* Check the parameters */
+    assert_param(IS_DMA_ALL_PERIPH(DMA_Channelx));
+
+    DMA_Channelx->DMA_SARx = Address;
+}
+
+/**
+ * \brief  Set DMA transmission destination address.
+  * \param  DMA_Channelx: Select the DMA peripheral. \ref DMA_Declaration
+ * \param  Address: Destination address.
+ * \return None.
+ */
+void DMA_SetDestinationAddress(DMA_ChannelTypeDef *DMA_Channelx,
+                               uint32_t Address)
+{
+    /* Check the parameters */
+    assert_param(IS_DMA_ALL_PERIPH(DMA_Channelx));
+
+    DMA_Channelx->DMA_DARx = Address;
+}
+
+/**
+ * \brief  Set DMA LLP stucture address.
+  * \param  DMA_Channelx: Select the DMA peripheral. \ref DMA_Declaration
+ * \param  Address: LLP stucture address.
+ * \return None.
+ */
+void DMA_SetLLPAddress(DMA_ChannelTypeDef *DMA_Channelx, uint32_t Address)
+{
+    /* Check the parameters */
+    assert_param(IS_DMA_ALL_PERIPH(DMA_Channelx));
+
+    DMA_Channelx->DMA_LLPx_L = Address & 0xFFFFFFFC;
+}
+
+/**
+ * \brief  Set DMA buffer size.
+  * \param  DMA_Channelx: Select the DMA peripheral. \ref DMA_Declaration
+ * \param  buffer_size: Set DMA_BufferSize, max 65535.
+ * \return None.
+ */
+void DMA_SetBufferSize(DMA_ChannelTypeDef *DMA_Channelx, uint32_t buffer_size)
+{
+    /* Check the parameters */
+    assert_param(IS_DMA_ALL_PERIPH(DMA_Channelx));
+
+    /* Configure high 32 bit of CTL register */
+    DMA_Channelx->DMA_CTLx_H = buffer_size;
+}
+
+/**
+ * \brief  Get DMA source address.
+  * \param  DMA_Channelx: Select the DMA peripheral. \ref DMA_Declaration
+ * \return Source address.
+ */
+uint32_t DMA_GetSrcTransferAddress(DMA_ChannelTypeDef *DMA_Channelx)
+{
+    /* Check the parameters */
+    assert_param(IS_DMA_ALL_PERIPH(DMA_Channelx));
+
+    return DMA_Channelx->DMA_SARx;
+}
+
+/**
+ * \brief  Get DMA destination address.
+  * \param  DMA_Channelx: Select the DMA peripheral. \ref DMA_Declaration
+ * \return Destination address.
+ */
+uint32_t DMA_GetDstTransferAddress(DMA_ChannelTypeDef *DMA_Channelx)
+{
+    /* Check the parameters */
+    assert_param(IS_DMA_ALL_PERIPH(DMA_Channelx));
+
+    return DMA_Channelx->DMA_DARx;
+}
+
+/**
+ * \brief  Get DMA transfer data length.
+  * \param  DMA_Channelx: Select the DMA peripheral. \ref DMA_Declaration
+ * \return DMA transfer data length.
+ */
+uint16_t DMA_GetTransferLen(DMA_ChannelTypeDef *DMA_Channelx)
+{
+    /* Check the parameters */
+    assert_param(IS_DMA_ALL_PERIPH(DMA_Channelx));
+
+    return (uint16_t)(DMA_Channelx->DMA_CTLx_H & 0xFFFFFFFF);
+}
+
+/**
+ * \brief  Update DMA LLP mode in multi-block.
+  * \param  DMA_Channelx: Select the DMA peripheral. \ref DMA_Declaration
+ * \param  DMA LLP mode
+ * \return None.
+ */
+void DMA_SetLLPMode(DMA_ChannelTypeDef *DMA_Channelx, uint32_t mode)
+{
+    DMA_Channelx->DMA_CTLx_L = ((DMA_Channelx->DMA_CTLx_L & (~LLI_TRANSFER)) | mode);
+}
+
+#if (DMA_SUPPORT_SECURE_MODE == 1)
+/**
+  * \brief  Enable or disable the specified DMA channel secure functions.
+  * \param  DMA_ChannelNum: Select the DMA channel number. \ref DMA_CHANNEL_NUM
+  * \param  NewState: Specifies the DMA channel secure function to be enabled or disabled.
+  *         This parameter can be: ENABLE or DISABLE.
+  * \return None.
+  */
+void DMA_SecureCmd(DMA_ChannelTypeDef *DMA_Channelx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_DMA_ALL_PERIPH(DMA_Channelx));
+
+    DMA_CFGx_H_TypeDef dma_cfgxh = {.d32 = DMA_Channelx->DMA_CFGx_H};
+    dma_cfgxh.b.protctl = !NewState;
+    DMA_Channelx->DMA_CFGx_H = dma_cfgxh.d32;
+}
+#endif
+
+#if (DMA_SUPPORT_OSW_OSR_CHANGE == 1)
+/**
+  * \brief  Set DMA OSW.
+  * \param  DMA_ChannelNum: Select the DMA channel number. \ref DMA_CHANNEL_NUM
+  * \param  osw_count: outstanding write count.
+  * \return None.
+  */
+void DMA_SetOSW(uint8_t DMA_ChannelNum, uint8_t osw_count)
+{
+    /* Check the parameters */
+    assert_param(IS_DMA_ALL_PERIPH(DMA_Channelx));
+
+    DMA_TypeDef *DMAx = DMA_GetDMAxByCh(DMA_ChannelNum);
+
+    DMA_DMAOSNUM_L_TypeDef dma_osnum = {.d32 = DMAx->DMA_DMAOSNUM_L};
+    dma_osnum.b.osw = osw_count & 0xFF;
+    DMAx->DMA_DMAOSNUM_L = dma_osnum.d32;
+}
+
+/**
+  * \brief  Set DMA OSR.
+  * \param  DMA_ChannelNum: Select the DMA channel number. \ref DMA_CHANNEL_NUM
+  * \param  osr_count: outstanding read count.
+  * \return None.
+  */
+void DMA_SetOSR(uint8_t DMA_ChannelNum, uint8_t osr_count)
+{
+    /* Check the parameters */
+    assert_param(IS_DMA_ALL_PERIPH(DMA_Channelx));
+
+    DMA_TypeDef *DMAx = DMA_GetDMAxByCh(DMA_ChannelNum);
+
+    DMA_DMAOSNUM_L_TypeDef dma_osnum = {.d32 = DMAx->DMA_DMAOSNUM_L};
+    dma_osnum.b.osr = osr_count & 0xFF;
+    DMAx->DMA_DMAOSNUM_L = dma_osnum.d32;
+}
+
+/**
+  * \brief  Get DMA OSW.
+  * \param  DMA_ChannelNum: Select the DMA channel number. \ref DMA_CHANNEL_NUM
+  * \return osw_count: outstanding write count.
+  */
+uint8_t DMA_GetOSWCount(uint8_t DMA_ChannelNum)
+{
+    /* Check the parameters */
+    assert_param(IS_DMA_ALL_PERIPH(DMA_Channelx));
+
+    DMA_TypeDef *DMAx = DMA_GetDMAxByCh(DMA_ChannelNum);
+
+    DMA_DMAOSNUM_L_TypeDef dma_osnum = {.d32 = DMAx->DMA_DMAOSNUM_L};
+
+    return dma_osnum.b.osw & 0xFF;
+}
+
+/**
+  * \brief  Get DMA OSR.
+  * \param  DMA_ChannelNum: Select the DMA channel number. \ref DMA_CHANNEL_NUM
+  * \return osr_count: outstanding read count.
+  */
+uint8_t DMA_GetOSRCount(uint8_t DMA_ChannelNum)
+{
+    /* Check the parameters */
+    assert_param(IS_DMA_ALL_PERIPH(DMA_Channelx));
+
+    DMA_TypeDef *DMAx = DMA_GetDMAxByCh(DMA_ChannelNum);
+
+    DMA_DMAOSNUM_L_TypeDef dma_osnum = {.d32 = DMAx->DMA_DMAOSNUM_L};
+
+    return dma_osnum.b.osr & 0xFF;
+}
+#endif
+
+#if (DMA_SUPPORT_CONTINUOUS_BLOCK_ADDRESS == 1)
+/**
+  * \brief  Continous source address.
+  * \param  DMA_ChannelNum: Select the DMA channel number. \ref DMA_CHANNEL_NUM
+  * \param  osw_count: outstanding write count.
+  * \return None.
+  */
+void DMA_ContSarCmd(DMA_ChannelTypeDef *DMA_Channelx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_DMA_ALL_PERIPH(DMA_Channelx));
+
+    if (DMA_IsSupportContinuousAddrChannel(DMA_Channelx) == 0)
+    {
+        return;
+    }
+
+    DMA_CFGx_H_TypeDef dma_cfgxh = {.d32 = DMA_Channelx->DMA_CFGx_H};
+    dma_cfgxh.b.cont_sar = NewState;
+    DMA_Channelx->DMA_CFGx_H = dma_cfgxh.d32;
+}
+
+void DMA_ContDarCmd(DMA_ChannelTypeDef *DMA_Channelx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_DMA_ALL_PERIPH(DMA_Channelx));
+
+    if (DMA_IsSupportContinuousAddrChannel(DMA_Channelx) == 0)
+    {
+        return;
+    }
+
+    DMA_CFGx_H_TypeDef dma_cfgxh = {.d32 = DMA_Channelx->DMA_CFGx_H};
+    dma_cfgxh.b.cont_dar = NewState;
+    DMA_Channelx->DMA_CFGx_H = dma_cfgxh.d32;
+}
+#endif
+
+#if (DMA_SUPPORT_BLOCK_COUNTER == 1)
+void DMA_SetBlockCounter(DMA_ChannelTypeDef *DMA_Channelx, uint32_t block_counter)
+{
+    /* Check the parameters */
+    assert_param(IS_DMA_ALL_PERIPH(DMA_Channelx));
+
+    if (DMA_IsSupportBlockCounterChannel(DMA_Channelx) == 0)
+    {
+        return;
+    }
+
+    DMA_Channelx->DMA_BLK_COUNTER_REGx = block_counter;
+}
+#endif
+
+#if (DMA_SUPPORT_RAP_FUNCTION == 1)
+
+bool DMA_RAPModeCmd(DMA_ChannelTypeDef *DMA_Channelx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_DMA_ALL_PERIPH(DMA_Channelx));
+
+    if (DMA_IsSupportRAPChannel(DMA_Channelx) == 0)
+    {
+        return false;
+    }
+
+    DMA_CFGx_H_TypeDef dma_cfgxh = {.d32 = DMA_Channelx->DMA_CFGx_H};
+    dma_cfgxh.b.direct_ctl_en = NewState;
+    DMA_Channelx->DMA_CFGx_H = dma_cfgxh.d32;
+
+    return true;
+}
+
+#endif
+
+
+
diff --git a/bee/drivers/entropy/CMakeLists.txt b/bee/drivers/entropy/CMakeLists.txt
new file mode 100644
index 00000000..f59bb32d
--- /dev/null
+++ b/bee/drivers/entropy/CMakeLists.txt
@@ -0,0 +1,4 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_include_directories_ifdef(CONFIG_SOC_FAMILY_REALTEK_BEE inc)
diff --git a/bee/drivers/entropy/inc/rng_interface.h b/bee/drivers/entropy/inc/rng_interface.h
new file mode 100644
index 00000000..8adb99af
--- /dev/null
+++ b/bee/drivers/entropy/inc/rng_interface.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __RNG_INTERFACE_H
+#define __RNG_INTERFACE_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+uint32_t platform_random(uint32_t max);
+
+#ifdef __cplusplus
+}
+#endif
+#endif /*__RNG_INTERFACE_H*/
diff --git a/bee/drivers/fmc/CMakeLists.txt b/bee/drivers/fmc/CMakeLists.txt
new file mode 100644
index 00000000..c3caed2a
--- /dev/null
+++ b/bee/drivers/fmc/CMakeLists.txt
@@ -0,0 +1,6 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_include_directories_ifdef(CONFIG_SOC_SERIES_RTL8752H inc/rtl8752h)
+zephyr_include_directories_ifdef(CONFIG_SOC_SERIES_RTL87X2G inc/rtl87x2g)
+zephyr_include_directories_ifdef(CONFIG_SOC_SERIES_RTL87X2J inc/rtl87x2j)
diff --git a/bee/drivers/fmc/inc/rtl8752h/flash_nor_device.h b/bee/drivers/fmc/inc/rtl8752h/flash_nor_device.h
new file mode 100644
index 00000000..e1c740d9
--- /dev/null
+++ b/bee/drivers/fmc/inc/rtl8752h/flash_nor_device.h
@@ -0,0 +1,451 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *               Define to prevent recursive inclusion
+ *============================================================================*/
+#ifndef _FLASH_NOR_DEVICE_H
+#define _FLASH_NOR_DEVICE_H
+
+/*============================================================================*
+ *                               Header Files
+*============================================================================*/
+#include <stdint.h>
+#include <stdbool.h>
+
+/** @defgroup  FLASH_DEVICE    Flash Device
+    * @brief Flash image layout and APIs
+    * @{
+    */
+
+/*============================================================================*
+  *                                   Variables
+ *============================================================================*/
+/** @defgroup FLASH_DEVICE_Exported_Variables Flash Device Exported Variables
+    * @brief
+    * @{
+    */
+typedef void (*FlashCB)(void);
+extern void *flash_sem;
+extern uint8_t *flash_nor_ioctl_buf;
+extern uint32_t flash_nor_ioctl_buf_len;
+
+/** End of FLASH_DEVICE_Exported_Variables
+  * @}
+  */
+
+/****************************************************************************************
+ * Nor Flash Macro
+ ****************************************************************************************/
+/** @defgroup FLASH_DEVICE_Exported_Macros Flash Device Exported Macros
+    * @brief
+    * @{
+    */
+
+#define FLASH_NOR_PAGE_SIZE                         (256)
+#define FLASH_NOR_SECTOR_SIZE                       (0x1000)
+#define FLASH_NOR_BLOCK_SIZE                        (0x10000)
+#define FLASH_NOR_BP_FIELDS_OFFSET                  (0x02)
+#define FLASH_NOR_STATUS_WIP_BIT                    (0x01)
+#define FLASH_NOR_STATUS_WEL_BIT                    (0x02)
+#define FLASH_NOR_IOCTL_MAX_BUF_LEN                 (0xFF)
+#define FLASH_NOR_TABLE_MAGIC_PATTERN               (0x5A5A12A5)
+#define FLASH_OFFSET_TO_NO_CACHE                    (0x01000000)
+#define IS_FLASH_SIZE_LARGER_THAN_16MB(size)        (size > (1 << 24))
+#define IS_SAME_FLASH_NOR_PAGE(addr0, addr1)        (((addr0) & 0xFFFFFF00) == ((addr1) & 0xFFFFFF00))
+#define CAL_ADDR                                    get_header_addr_by_img_id(OTA) + offsetof(T_IMG_HEADER_FORMAT, magic_pattern)
+#define IS_SPIC0_ADDR(addr)                         (((addr >= FMC_MAIN) && (addr < FMC_MAIN + SPIC0_SIZE)) || ((addr >= (FMC_MAIN | FLASH_OFFSET_TO_NO_CACHE)) && (addr < (FMC_MAIN | FLASH_OFFSET_TO_NO_CACHE) + SPIC0_SIZE)))
+
+/** End of FLASH_DEVICE_Exported_Macros
+  * @}
+  */
+
+/****************************************************************************************
+ * Nor Flash Enumeration
+ ****************************************************************************************/
+/** @defgroup FLASH_DEVICE_Exported_Types Flash Device Exported Types
+  * @brief
+  * @{
+  */
+
+typedef enum
+{
+    FLASH_NOR_ERASE_SECTOR  = 1,
+    FLASH_NOR_ERASE_BLOCK   = 2,
+    FLASH_NOR_ERASE_CHIP    = 4,
+} FLASH_NOR_ERASE_MODE;
+
+typedef enum
+{
+    FLASH_NOR_DMA_AUTO_F2R = 0,
+    FLASH_NOR_DMA_AUTO_R2F,
+    FLASH_NOR_DMA_USER_F2R,
+    FLASH_NOR_DMA_USER_R2F
+} FLASH_NOR_DMA_TYPE;
+
+typedef enum
+{
+    FLASH_NOR_IDX_SPIC0,            /* Nor flash controlled by SPIC0 */
+    FLASH_NOR_IDX_SPIC1,
+    FLASH_NOR_IDX_MAX
+} FLASH_NOR_IDX_TYPE;
+
+typedef struct
+{
+    // flash info
+    uint32_t  PageSize;
+    uint32_t  Main_Addr;
+    uint32_t  Spic_Cal_Addr;
+
+    // flash layout table
+    uint32_t  ota_bank0_addr;
+    uint32_t  ota_bank0_size;
+    uint32_t  ota_bank1_addr;
+    uint32_t  ota_bank1_size;
+    uint32_t  ftl_addr;
+    uint32_t  ftl_size;
+
+    uint32_t  ota_tmp_addr;
+    uint32_t  ota_tmp_size;
+
+    uint32_t  bkp_data1_addr;
+    uint32_t  bkp_data1_size;
+    uint32_t  bkp_data2_addr;
+    uint32_t  bkp_data2_size;
+
+    // only patch_addr is fixed
+    // other fields are changable
+    // app/ota/ftl/dsp dont need to be sequencial
+    // just beware of the size of them have no overlap condition
+
+    uint32_t  HardFault_Record_CFG;
+    // default value: 0x7
+    // [0]: 1, enable saving HardFault_Record
+    // [1]: reserved//1, 1 bit slow mode
+    // [2]: 1, dump HardFaultRecord in boot time
+    // [3]: 1, Clean up HardFaultRecord after dumping HardFault_Record
+    // [4]: 1, Clean up HardFaultRecord before saving HardFault_Record
+    uint32_t  HardFault_Record_BegAddr;
+    uint32_t  HardFault_Record_EndAddr;
+
+} T_FLASH_INFO_TBL;
+
+typedef enum
+{
+    FLASH_NOR_RET_UNKNOWN,
+    FLASH_NOR_RET_NOT_EXIST_BASIC_CMD,
+    FLASH_NOR_RET_NOT_EXIST_ADV_CMD,
+    FLASH_NOR_RET_NOT_EXIST_QUERY_INFO,
+    FLASH_NOR_RET_CMD_NOT_SUPPORT,
+    FLASH_NOR_RET_DEV_NOT_SUPPORT,
+    FLASH_NOR_RET_VENDOR_NOT_SUPPORT,
+    FLASH_NOR_RET_LOCK_FAILED,
+    FLASH_NOR_RET_UNLOCK_FAILED,
+    FLASH_NOR_RET_BIT_MODE_SET_FAILED,
+    FLASH_NOR_RET_BIT_MODE_NOT_SUPPORT,
+    FLASH_NOR_RET_ILLEGAL_OPERATION,
+    FLASH_NOR_RET_PARAM_INVALID,
+    FLASH_NOR_RET_WAIT_BUSY_FAILED,
+    FLASH_NOR_RET_IDX_OUT_OF_RANGE,
+    FLASH_NOR_RET_ADDR_OUT_OF_RANGE,
+    FLASH_NOR_RET_ADDR_LARGER_THAN_FLASH_SIZE,
+    FLASH_NOR_RET_CAL_IN_PHYSICAL_CYC_NOT_FOUND,
+    FLASH_NOR_RET_CAL_RD_DUMMY_LENGTH_NOT_FOUND,
+    FLASH_NOR_RET_CAL_FAILED,
+    FLASH_NOR_RET_MALLOC_FAILED,
+    FLASH_NOR_RET_HOOK_FUNC,
+    FLASH_NOR_RET_SUSPEND_UNNECCESSARY,
+    FLASH_NOR_RET_SET_4_BYTE_ADDRESS_MODE_FAILED,
+    FLASH_NOR_RET_SUCCESS
+} FLASH_NOR_RET_TYPE;
+
+typedef enum
+{
+    FLASH_NOR_1_BIT_MODE,
+    FLASH_NOR_2_BIT_MODE,
+    FLASH_NOR_4_BIT_MODE,
+    FLASH_NOR_8_BIT_MODE,
+} FLASH_NOR_BIT_MODE;
+
+typedef enum
+{
+    FLASH_SCCD,
+    FLASH_OCCD,
+    FLASH_OTA_BANK_0,
+    FLASH_OTA_BANK_1,
+    FLASH_OTA_TMP,
+    FLASH_BKP_DATA1,
+    FLASH_BKP_DATA2,
+    FLASH_FTL,
+    FLASH_HARDFAULT_RECORD,
+    FLASH_TOTAL,
+} FLASH_LAYOUT_NAME;
+
+typedef enum _FLASH_NOR_IOCTL_TYPE
+{
+    FLASH_NOR_GET_BASE                          = 0x0000,
+    FLASH_NOR_GET_ADDR_BASE,
+    FLASH_NOR_GET_RDID,
+    FLASH_NOR_GET_SIZE,
+    FLASH_NOR_GET_BP,
+    FLASH_NOR_GET_BP_TOP_BOTTOM,
+    FLASH_NOR_GET_WAIT_BUSY_CTR,
+    FLASH_NOR_GET_BIT_MODE,
+
+    FLASH_NOR_SET_BASE                          = 0x1000,
+    FLASH_NOR_SET_BP,
+    FLASH_NOR_SET_BP_TOP_BOTTOM,
+    FLASH_NOR_SET_BP_UNLOCK_BY_ADDR,
+    FLASH_NOR_SET_WAIT_BUSY_CTR,
+    FLASH_NOR_SET_SPIC_BAUD,
+    FLASH_NOR_SET_LOG_BITMAP,
+
+    FLASH_NOR_EXEC_BASE                         = 0x2000,
+    FLASH_NOR_EXEC_FLASH_INIT,
+    FLASH_NOR_EXEC_DP,
+    FLASH_NOR_EXEC_FLASH_SW_RESET,
+    FLASH_NOR_EXEC_QUERY_INFO_LOADING,
+    FLASH_NOR_EXEC_HIGH_SPEED_MODE,
+    FLASH_NOR_EXEC_FLASH_CAL,
+    FLASH_NOR_EXEC_FLASH_READ,
+    FLASH_NOR_EXEC_FLASH_WRITE,
+    FLASH_NOR_EXEC_FLASH_ERASE,
+
+    FLASH_NOR_BASE_MASK                         = 0xF000,
+} FLASH_NOR_IOCTL_TYPE;
+
+/* *INDENT-OFF* */
+/** End of FLASH_DEVICE_Exported_Types
+  * @}
+  */
+
+/****************************************************************************************
+ * Nor Flash Functions
+ ****************************************************************************************/
+/** @defgroup FLASH_DEVICE_Exported_Functions Flash Device Exported Functions
+    * @brief
+    * @{
+    */
+/**
+ * @brief set flash bit mode
+ * @param idx  specific nor flash
+ * @param bit_mode  wanted bit mode
+ * @return FLASH_NOR_RET_SUCCESS if success
+*/
+extern FLASH_NOR_RET_TYPE(*flash_nor_try_high_speed_mode)(FLASH_NOR_IDX_TYPE idx,
+                                                          FLASH_NOR_BIT_MODE bit_mode);
+
+/**
+ * @brief get flash base address
+ * @param idx  specific nor flash
+ * @return flash base address
+*/
+uint32_t flash_nor_get_addr_base(FLASH_NOR_IDX_TYPE idx);
+
+/**
+ * @brief check flash bp level before ota copy, if flash is locked, must unlock bp in NVRAM
+ * @param none
+ * @return none
+*/
+extern void (*check_flash_bp_before_ota_copy)(void);
+
+/**
+ * @brief read flash data via auto mode
+ * @param addr    address to read
+ * @return value in this address
+*/
+uint32_t flash_nor_auto_read(uint32_t addr);
+
+/**
+ * @brief init flash DMA read flow
+ * @param dma_type  read type, usually memory to memory
+ * @param flash_cb  call back function
+ * @param src_addr  read source
+ * @param dst_addr  read destination
+ * @param data_len  read length
+ * @return void
+*/
+void flash_nor_auto_dma_read(FLASH_NOR_DMA_TYPE dma_type, FlashCB flash_cb, uint32_t src_addr,
+                             uint32_t dst_addr, uint32_t data_len);
+
+/**
+ * @brief           dump spic & nor flash info
+ * @return          none
+ */
+void flash_nor_dump_flash_info(void);
+
+/**
+ * @brief           get nor flash layout member start address
+ * @param name      specify address of nor flash layout member
+ * @return          specific address of nor flash layout member
+ */
+uint32_t flash_nor_get_bank_addr(FLASH_LAYOUT_NAME name);
+
+/**
+ * @brief           get nor flash layout member size
+ * @param name      specify size of nor flash layout member
+ * @return          specific size of nor flash layout member
+ */
+uint32_t flash_nor_get_bank_size(FLASH_LAYOUT_NAME name);
+
+/**
+ * @brief           set specific nor flash commands and query info
+ * @param idx       specific nor flash
+ * @return          @ref FLASH_NOR_RET_TYPE result
+ */
+FLASH_NOR_RET_TYPE flash_nor_set_all_info(FLASH_NOR_IDX_TYPE idx);
+
+/**
+ * @brief           task-safe of @ref flash_nor_read
+ * @param addr      the ram address mapping of nor flash going to be read
+ * @param data      data buffer to be read into
+ * @param byte_len  read data length
+ * @return          @ref FLASH_NOR_RET_TYPE result
+ */
+extern FLASH_NOR_RET_TYPE(*flash_nor_read_locked)(uint32_t addr, uint8_t *data, uint32_t byte_len);
+
+/**
+ * @brief           task-safe of @ref flash_nor_write
+ * @param addr      the ram address mapping of nor flash going to be written
+ * @param data      data buffer to be write into
+ * @param byte_len  write data length
+ * @return          @ref FLASH_NOR_RET_TYPE result
+ */
+extern FLASH_NOR_RET_TYPE(*flash_nor_write_locked)(uint32_t addr, uint8_t *data, uint32_t byte_len);
+
+/**
+ * @brief           task-safe of @ref flash_nor_erase
+ * @param addr      the ram address mapping of nor flash going to be erased
+ * @param mode      erase mode defined as @ref FLASH_NOR_ERASE_MODE
+ * @return          @ref FLASH_NOR_RET_TYPE result
+ */
+extern FLASH_NOR_RET_TYPE(*flash_nor_erase_locked)(uint32_t addr, FLASH_NOR_ERASE_MODE mode);
+
+/**
+ * @brief           nor flash IO control entry
+ * @param cmd       @ref FLASH_NOR_IOCTL_TYPE cmd
+ * @param idx       specific nor flash
+ * @param p1        parameter 1 based on different @ref FLASH_NOR_IOCTL_TYPE cmd
+ * @param p2        parameter 2 based on different @ref FLASH_NOR_IOCTL_TYPE cmd
+ * @param p3        parameter 3 based on different @ref FLASH_NOR_IOCTL_TYPE cmd
+ * @return          @ref FLASH_NOR_RET_TYPE result
+ */
+extern FLASH_NOR_RET_TYPE flash_nor_ioctl(uint16_t cmd, uint16_t idx, uint32_t p1, uint32_t p2,
+                                          uint32_t p3);
+
+/**
+ * @brief              set top/bottom of block protect with lock
+ * @param idx          specific nor flash
+ * @param from_bottom  true if from bottom
+ * @return             @ref FLASH_NOR_RET_TYPE result
+ */
+extern FLASH_NOR_RET_TYPE(*flash_nor_set_tb_bit_locked)(FLASH_NOR_IDX_TYPE idx, bool from_bottom);
+
+/**
+ * @brief           set block protect level with lock
+ * @param idx       specific nor flash
+ * @param bp_lv     nor flash BP level
+ * @return          @ref FLASH_NOR_RET_TYPE result
+ */
+extern FLASH_NOR_RET_TYPE(*flash_nor_set_bp_lv_locked)(FLASH_NOR_IDX_TYPE idx, uint8_t bp_lv);
+
+/**
+ * @brief           get block protect level with lock
+ * @param idx       specific nor flash
+ * @param bp_lv     nor flash BP level
+ * @return          @ref FLASH_NOR_RET_TYPE result
+ */
+extern FLASH_NOR_RET_TYPE(*flash_nor_get_bp_lv_locked)(FLASH_NOR_IDX_TYPE idx, uint8_t *bp_lv);
+
+/**
+ * @brief           set sequential transfer function
+ * @param idx       specific nor flash
+ * @param enable    true if enable
+ * @return          @ref FLASH_NOR_RET_TYPE result
+ */
+FLASH_NOR_RET_TYPE flash_nor_set_seq_trans_enable(FLASH_NOR_IDX_TYPE idx, bool enable);
+
+/**
+ * @brief           get flash ID
+ * @param idx       specific nor flash
+ * @return          return flash ID
+ */
+uint32_t flash_nor_get_id(FLASH_NOR_IDX_TYPE idx);
+
+/**
+ * @brief           read 4 bytes flash with auto mode (addr should be 4 byte align)
+ * @param addr      specific nor flash
+ * @param data      read data
+ * @return          true if success
+ */
+bool flash_nor_auto_read_locked(uint32_t addr, uint32_t *data);
+
+/**
+ * @brief get flash default block protect level depend on different flash id and different flash layout
+ * @param none
+ * @return default set bp level
+*/
+extern uint8_t (*flash_nor_get_default_bp_lv)(void);
+
+/**
+ * @brief set flash bp level to 0
+ * @param pre_bp_lv  previous bp level
+ * @return @ref FLASH_NOR_RET_TYPE result
+*/
+extern FLASH_NOR_RET_TYPE(*flash_nor_unlock_bp_all)(uint8_t *pre_bp_lv);
+
+/**
+ * @brief set flash bp level to unlock specified address
+ * @param unlock_addr  specified address
+ * @param old_bp_lv    previous bp level
+ * @return @ref FLASH_NOR_RET_TYPE result
+*/
+extern FLASH_NOR_RET_TYPE(*flash_nor_unlock_bp_by_addr_locked)(uint32_t unlock_addr,
+                                                               uint8_t *old_bp_lv);
+
+/**
+ * @brief set flash sequential transfer
+ * @param idx       specific nor flash
+ * @param enable    enable or disable
+ * @return @ref FLASH_NOR_RET_TYPE result
+*/
+FLASH_NOR_RET_TYPE flash_nor_set_seq_trans(FLASH_NOR_IDX_TYPE idx, bool enable);
+
+
+/**
+ * @brief get flash current bit mode
+ * @param idx       specific nor flash
+ * @param mode      get bit mode
+ * @return @ref FLASH_NOR_RET_TYPE result
+*/
+extern FLASH_NOR_RET_TYPE(*flash_nor_get_bit_mode)(FLASH_NOR_IDX_TYPE idx,
+                                                   FLASH_NOR_BIT_MODE *mode);
+
+/**
+ * @brief get flash size
+ * @param idx       specific nor flash
+ * @return flash size
+*/
+extern uint32_t flash_nor_get_flash_size(FLASH_NOR_IDX_TYPE idx);
+
+typedef enum
+{
+    FLASH_NOR_EXIST_NONE        = 0,
+    FLASH_NOR_EXIST_BASIC_CMD   = 1,
+    FLASH_NOR_EXIST_ADV_CMD     = 2,
+    FLASH_NOR_EXIST_QUERY_INFO  = 4,
+    FLASH_NOR_EXIST_ALL         = 7,
+} FLASH_NOR_EXIST_LV;
+
+extern FLASH_NOR_RET_TYPE(*flash_nor_set_bp_lv)(FLASH_NOR_IDX_TYPE idx, uint8_t bp_lv);
+extern FLASH_NOR_RET_TYPE(*flash_nor_set_tb_bit)(FLASH_NOR_IDX_TYPE idx, bool from_bottom);
+FLASH_NOR_EXIST_LV flash_nor_get_exist(FLASH_NOR_IDX_TYPE idx);
+extern FLASH_NOR_RET_TYPE(*flash_nor_load_query_info)(FLASH_NOR_IDX_TYPE idx);
+
+/** @} */ /* End of group FLASH_DEVICE_Exported_Functions */
+/** @} */ /* End of group FLASH_DEVICE */
+
+#endif
diff --git a/bee/drivers/fmc/inc/rtl8752h/fmc_platform.h b/bee/drivers/fmc/inc/rtl8752h/fmc_platform.h
new file mode 100644
index 00000000..4800b278
--- /dev/null
+++ b/bee/drivers/fmc/inc/rtl8752h/fmc_platform.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _FMC_PLATFORM_H
+#define _FMC_PLATFORM_H
+
+#include "stdint.h"
+
+#define _PACKED_                __attribute__((packed))
+
+/****************************************************************************************
+ * Flexible Memory Controller Address Map
+ ****************************************************************************************/
+#define FMC_MAIN0_ADDR                                      (SPIC0_ADDR)
+#define FMC_MAIN0_SIZE                                      (SPIC0_SIZE)
+#define FMC_MAIN0_UNCACHEABLE_ADDR                          (FLASH_OFFSET_TO_NO_CACHE)
+#define FMC_MAIN0_NON_CACHE_ADDR(cache_addr)                ((cache_addr) & ~(FMC_MAIN0_ADDR) | (FMC_MAIN0_UNCACHEABLE_ADDR))
+
+/********************************FLASH_OFFSET_TO_NO_CACHE********************************************************
+ * Flexible Memory Controller Address Map Checking
+ ****************************************************************************************/
+#define FMC_IS_SPIC0_CACHEABLE_ADDR(addr)                   ((addr >= FMC_MAIN0_ADDR) && (addr < FMC_MAIN0_ADDR + FMC_MAIN0_SIZE))
+#define FMC_IS_SPIC0_UNCACHEABLE_ADDR(addr)                 ((addr >= FMC_MAIN0_UNCACHEABLE_ADDR) && (addr < FMC_MAIN0_UNCACHEABLE_ADDR + FMC_MAIN0_SIZE))
+#define FMC_IS_SPIC0_ADDR(addr)                             (FMC_IS_SPIC0_CACHEABLE_ADDR(addr) || FMC_IS_SPIC0_UNCACHEABLE_ADDR(addr))
+
+
+#endif /* _FMC_PLATFORM_H */
diff --git a/bee/drivers/fmc/inc/rtl87x2g/flash_nor_device.h b/bee/drivers/fmc/inc/rtl87x2g/flash_nor_device.h
new file mode 100644
index 00000000..63562d4d
--- /dev/null
+++ b/bee/drivers/fmc/inc/rtl87x2g/flash_nor_device.h
@@ -0,0 +1,298 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _FLASH_NOR_DEVICE_H
+#define _FLASH_NOR_DEVICE_H
+
+#include "fmc_platform.h"
+#include <stdint.h>
+#include <stdbool.h>
+
+/** @defgroup NOR_FLASH  Nor Flash
+  * @brief
+  * @{
+  */
+
+/****************************************************************************************
+ * Nor Flash Enumeration
+ ****************************************************************************************/
+/** @defgroup Nor_Flash_Exported_Types  Nor Flash Exported Types
+  * @ingroup  FLASH
+  * @brief
+  * @{
+  */
+
+/** @defgroup FLASH_NOR_IOCTL_TYPE  FLASH NOR IOCTL TYPE
+  * @ingroup  Nor_Flash_Exported_Types
+  * @brief
+  * @{
+  */
+typedef enum _FLASH_NOR_IOCTL_TYPE
+{
+    FLASH_NOR_GET_BASE                          = 0x0000,
+    FLASH_NOR_GET_ADDR_BASE,
+    FLASH_NOR_GET_RDID,
+    FLASH_NOR_GET_SIZE,
+    FLASH_NOR_GET_BP,
+    FLASH_NOR_GET_BP_TOP_BOTTOM,
+    FLASH_NOR_GET_WAIT_BUSY_CTR,
+    FLASH_NOR_GET_BIT_MODE,
+
+    FLASH_NOR_SET_BASE                          = 0x1000,
+    FLASH_NOR_SET_BP,
+    FLASH_NOR_SET_BP_TOP_BOTTOM,
+    FLASH_NOR_SET_BP_UNLOCK_BY_ADDR,
+    FLASH_NOR_SET_WAIT_BUSY_CTR,
+    FLASH_NOR_SET_SPIC_BAUD,
+    FLASH_NOR_SET_LOG_BITMAP,
+
+    FLASH_NOR_EXEC_BASE                         = 0x2000,
+    FLASH_NOR_EXEC_FLASH_INIT,
+    FLASH_NOR_EXEC_DP,
+    FLASH_NOR_EXEC_FLASH_SW_RESET,
+    FLASH_NOR_EXEC_QUERY_INFO_LOADING,
+    FLASH_NOR_EXEC_HIGH_SPEED_MODE,
+    FLASH_NOR_EXEC_FLASH_CAL,
+    FLASH_NOR_EXEC_FLASH_READ,
+    FLASH_NOR_EXEC_FLASH_WRITE,
+    FLASH_NOR_EXEC_FLASH_ERASE,
+
+    FLASH_NOR_BASE_MASK                         = 0xF000,
+} FLASH_NOR_IOCTL_TYPE;
+/** End of FLASH_NOR_IOCTL_TYPE
+  * @}
+  */
+
+/** @defgroup FLASH_LAYOUT_NAME  FLASH LAYOUT NAME
+  * @ingroup  Nor_Flash_Exported_Types
+  * @brief
+  * @{
+  */
+typedef enum
+{
+    FLASH_OCCD,
+    FLASH_BOOT_PATCH0,
+    FLASH_BOOT_PATCH1,
+    FLASH_OTA_BANK_0,
+    FLASH_OTA_BANK_1,
+    FLASH_SECURE_APP0,
+    FLASH_SECURE_APP1,
+    FLASH_SECURE_APP_DATA0,
+    FLASH_SECURE_APP_DATA1,
+    FLASH_RO_DATA1,
+    FLASH_RO_DATA2,
+    FLASH_RO_DATA3,
+    FLASH_RO_DATA4,
+    FLASH_RO_DATA5,
+    FLASH_RO_DATA6,
+    FLASH_BKP_DATA1,
+    FLASH_BKP_DATA2,
+    FLASH_OTA_TMP,
+    FLASH_FTL,
+
+#ifndef _IS_ASIC_
+    FLASH_FAKE_DSP_ROM,
+#endif
+
+    FLASH_TOTAL,
+} FLASH_LAYOUT_NAME;
+
+/** End of FLASH_LAYOUT_NAME
+  * @}
+  */
+
+/** End of Nor_Flash_Exported_Types
+  * @}
+  */
+
+/****************************************************************************************
+ * Nor Flash Function Prototype
+ ****************************************************************************************/
+/** @defgroup Nor_Flash_Exported_Functions  Nor Flash Exported Functions
+  * @brief
+  * @{
+  */
+
+extern uint8_t *flash_nor_ioctl_buf;
+extern uint32_t flash_nor_ioctl_buf_len;
+
+/**
+ * @brief           dump spic & nor flash info
+ * @return          none
+ */
+void flash_nor_dump_main_info(void);
+
+/**
+ * @brief           get nor flash layout member start address
+ * @param name      specify address of nor flash layout member
+ * @return          specific address of nor flash layout member
+ */
+uint32_t flash_nor_get_bank_addr(FLASH_LAYOUT_NAME name);
+
+/**
+ * @brief           get nor flash layout member size
+ * @param name      specify size of nor flash layout member
+ * @return          specific size of nor flash layout member
+ */
+uint32_t flash_nor_get_bank_size(FLASH_LAYOUT_NAME name);
+
+/**
+ * @brief           set specific nor flash commands and query info
+ * @param idx       specific nor flash
+ * @return          @ref FLASH_NOR_RET_TYPE result
+ */
+FLASH_NOR_RET_TYPE flash_nor_set_all_info(FLASH_NOR_IDX_TYPE idx);
+
+/**
+ * @brief           task-safe of @ref flash_nor_read
+ * @param addr      the ram address mapping of nor flash going to be read
+ * @param data      data buffer to be read into
+ * @param len       read data length
+ * @return          @ref FLASH_NOR_RET_TYPE result
+ */
+extern FLASH_NOR_RET_TYPE flash_nor_read_locked(uint32_t addr, uint8_t *data, uint32_t len);
+
+/**
+ * @brief           task-safe of @ref flash_nor_write
+ * @param addr      the ram address mapping of nor flash going to be written
+ * @param data      data buffer to be write into
+ * @param len       write data length
+ * @return          @ref FLASH_NOR_RET_TYPE result
+ */
+extern FLASH_NOR_RET_TYPE flash_nor_write_locked(uint32_t addr, uint8_t *data, uint32_t len);
+
+/**
+ * @brief           task-safe of @ref flash_nor_erase
+ * @param addr      the ram address mapping of nor flash going to be erased
+ * @param mode      erase mode defined as @ref FLASH_NOR_ERASE_MODE
+ * @return          @ref FLASH_NOR_RET_TYPE result
+ */
+extern FLASH_NOR_RET_TYPE flash_nor_erase_locked(uint32_t addr, FLASH_NOR_ERASE_MODE mode);
+
+/**
+ * @brief           task-safe nor flash auto dma read
+ * @param src       the ram address mapping of nor flash going to be read from
+ * @param dst       the ram address going to be written to
+ * @param len       dma data length
+ * @param cb        call back function which is to be executed when dma finishing
+ * @return          @ref FLASH_NOR_RET_TYPE result
+ */
+extern FLASH_NOR_RET_TYPE flash_nor_auto_dma_read_locked(uint32_t src, uint32_t dst, uint32_t len,
+                                                         FLASH_NOR_ASYNC_CB cb);
+
+/**
+ * @brief           task-safe nor flash auto dma read with sequential transaction enabled
+ * @param src       the ram address mapping of nor flash going to be read from
+ * @param dst       the ram address going to be written to
+ * @param len       dma data length
+ * @param cb        call back function which is to be executed when dma finishing
+ * @return          @ref FLASH_NOR_RET_TYPE result
+ */
+extern FLASH_NOR_RET_TYPE flash_nor_auto_seq_trans_dma_read_locked(uint32_t src, uint32_t dst,
+                                                                   uint32_t len, FLASH_NOR_ASYNC_CB cb);
+
+/**
+ * @brief           nor flash try high speed mode with bit mode configuration
+ * @param idx       specific nor flash
+ * @param bit_mode  nor flash bit mode
+ * @return          @ref FLASH_NOR_RET_TYPE result
+ */
+extern FLASH_NOR_RET_TYPE flash_nor_try_high_speed_mode(FLASH_NOR_IDX_TYPE idx,
+                                                        FLASH_NOR_BIT_MODE bit_mode);
+
+/**
+ * @brief           nor flash check busy status
+ * @param idx       specific nor flash
+ * @return          @ref FLASH_NOR_RET_TYPE result
+ */
+extern FLASH_NOR_RET_TYPE flash_nor_wait_busy(FLASH_NOR_IDX_TYPE idx);
+
+/**
+ * @brief           nor flash IO control entry
+ * @param cmd       @ref FLASH_NOR_IOCTL_TYPE cmd
+ * @param idx       specific nor flash
+ * @param p1        parameter 1 based on different @ref FLASH_NOR_IOCTL_TYPE cmd
+ * @param p2        parameter 2 based on different @ref FLASH_NOR_IOCTL_TYPE cmd
+ * @param p3        parameter 3 based on different @ref FLASH_NOR_IOCTL_TYPE cmd
+ * @return          @ref FLASH_NOR_RET_TYPE result
+ */
+extern FLASH_NOR_RET_TYPE flash_nor_ioctl(uint16_t cmd, uint16_t idx, uint32_t p1, uint32_t p2,
+                                          uint32_t p3);
+
+/**
+ * @brief           get flash exist level
+ * @param idx       specific nor flash
+ * @return          @ref FLASH_NOR_EXIST_LV result
+ */
+FLASH_NOR_EXIST_LV flash_nor_get_exist_nsc(FLASH_NOR_IDX_TYPE idx);
+
+/**
+ * @brief              set top/bottom of block protect with lock
+ * @param idx          specific nor flash
+ * @param from_bottom  true if from bottom
+ * @return             @ref FLASH_NOR_RET_TYPE result
+ */
+FLASH_NOR_RET_TYPE flash_nor_set_tb_bit_locked(FLASH_NOR_IDX_TYPE idx, bool from_bottom);
+
+/**
+ * @brief           set block protect level with lock
+ * @param idx       specific nor flash
+ * @param bp_lv     nor flash BP level
+ * @return          @ref FLASH_NOR_RET_TYPE result
+ */
+FLASH_NOR_RET_TYPE flash_nor_set_bp_lv_locked(FLASH_NOR_IDX_TYPE idx, uint8_t bp_lv);
+
+/**
+ * @brief           get block protect level with lock
+ * @param idx       specific nor flash
+ * @param bp_lv     nor flash BP level
+ * @return          @ref FLASH_NOR_RET_TYPE result
+ */
+FLASH_NOR_RET_TYPE flash_nor_get_bp_lv_locked(FLASH_NOR_IDX_TYPE idx, uint8_t *bp_lv);
+
+/**
+ * @brief           set sequential transfer function
+ * @param idx       specific nor flash
+ * @param enable    true if enable
+ * @return          @ref FLASH_NOR_RET_TYPE result
+ */
+FLASH_NOR_RET_TYPE flash_nor_set_seq_trans_enable(FLASH_NOR_IDX_TYPE idx, bool enable);
+
+/**
+ * @brief                 set flash address mode for flash >= 32M byte
+ * @param idx             specific nor flash
+ * @param is_4_byte_mode  true if set to 4 byte address mode
+ * @return                @ref FLASH_NOR_RET_TYPE result
+ */
+FLASH_NOR_RET_TYPE flash_nor_set_addr_mode(FLASH_NOR_IDX_TYPE idx, bool is_4_byte_mode);
+
+/**
+ * @brief           get flash ID
+ * @param idx       specific nor flash
+ * @return          return flash ID
+ */
+uint32_t flash_nor_get_id(FLASH_NOR_IDX_TYPE idx);
+
+/**
+ * @brief      init cmd list in rom non-secure
+ * @return     true if success
+ */
+bool flash_nor_cmd_list_init_nsc(void);
+
+/**
+ * @brief     init bp level in rom non-secure
+ * @return    void
+ */
+void flash_nor_init_bp_lv_nsc(void);
+
+/** End of Nor_Flash_Exported_Functions
+  * @}
+  */
+
+/** End of NOR_FLASH
+  * @}
+  */
+#endif
diff --git a/bee/drivers/fmc/inc/rtl87x2g/fmc_platform.h b/bee/drivers/fmc/inc/rtl87x2g/fmc_platform.h
new file mode 100644
index 00000000..f475242f
--- /dev/null
+++ b/bee/drivers/fmc/inc/rtl87x2g/fmc_platform.h
@@ -0,0 +1,204 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _FMC_PLATFORM_H
+#define _FMC_PLATFORM_H
+
+#include "stdint.h"
+
+/** @defgroup FMC  Flexible Memory Controller
+  * @brief
+  * @{
+  */
+
+/** @defgroup FMC_Exported_Constants  Flexible Memory Controller Exported Constants
+  * @brief
+  * @{
+  */
+/****************************************************************************************
+ * Flexible Memory Controller Address Map
+ ****************************************************************************************/
+/** @defgroup FMC_Exported_Address_Map  Flexible Memory Controller Exported Address Map
+  * @ingroup  FMC_Exported_Constants
+  * @brief
+  * @{
+  */
+#define SPIC0_ADDR            0x04000000
+#define SPIC0_SIZE            (64*1024*1024)
+
+#define FMC_MAIN0_ADDR                                      (SPIC0_ADDR)
+#define FMC_MAIN0_SIZE                                      (SPIC0_SIZE)
+
+/** End of FMC_Exported_Address_Map
+  * @}
+  */
+
+/****************************************************************************************
+ * Flexible Memory Controller Address Map Checking
+ ****************************************************************************************/
+/** @defgroup FMC_Address_Map_Checking  Flexible Memory Controller Address Map Checking
+  * @ingroup  FMC_Exported_Constants
+  * @brief
+  * @{
+  */
+#define FMC_IS_SPIC0_ADDR(addr)                             ((addr >= FMC_MAIN0_ADDR) && (addr < FMC_MAIN0_ADDR + FMC_MAIN0_SIZE))
+
+/** End of FMC_Address_Map_Checking
+  * @}
+  */
+
+/****************************************************************************************
+ * Flexible Memory Controller Calibration Definition
+ ****************************************************************************************/
+/** @defgroup FMC_Calibration_Definition  Flexible Memory Controller Calibration Definition
+  * @ingroup  FMC_Exported_Constants
+  * @brief
+  * @{
+  */
+#define FMC_CAL_PATTERN                                     (0x5A5A12A5)
+
+/** End of FMC_Calibration_Definition
+  * @}
+  */
+
+/****************************************************************************************
+ * SPIC Description
+ ****************************************************************************************/
+/** @defgroup SPIC_Exported_Description  SPIC Exported Description
+  * @ingroup  FMC_Exported_Constants
+  * @brief
+  * @{
+  */
+#define SPIC_NUM                                            (3)
+#define SPIC0_RX_FIFO_NUM                                   (64)
+#define SPIC0_TX_FIFO_NUM                                   (32)
+#define SPIC1_RX_FIFO_NUM                                   (64)
+#define SPIC1_TX_FIFO_NUM                                   (64)
+#define SPIC2_RX_FIFO_NUM                                   (64)
+#define SPIC2_TX_FIFO_NUM                                   (64)
+
+/** End of SPIC_Exported_Description
+  * @}
+  */
+/** End of FMC_Exported_Constants
+  * @}
+  */
+
+/****************************************************************************************
+ * FMC Enum Type
+ ****************************************************************************************/
+/** @defgroup FMC_Exported_Types  FMC Exported Types
+  * @brief
+  * @{
+  */
+typedef enum
+{
+    /* For SPIC1 PSRAM */
+    PSRAM_OPI_TYPE,
+} PSRAM_INTERFACE_TYPE;
+
+typedef enum
+{
+    FLASH_NOR_ERASE_SECTOR  = 1,
+    FLASH_NOR_ERASE_BLOCK   = 2,
+    FLASH_NOR_ERASE_CHIP    = 4,
+} FLASH_NOR_ERASE_MODE;
+
+typedef enum
+{
+    FLASH_NOR_RET_UNKNOWN,
+    FLASH_NOR_RET_NOT_EXIST_BASIC_CMD,
+    FLASH_NOR_RET_NOT_EXIST_ADV_CMD,
+    FLASH_NOR_RET_NOT_EXIST_QUERY_INFO,
+    FLASH_NOR_RET_CMD_NOT_SUPPORT,
+    FLASH_NOR_RET_DEV_NOT_SUPPORT,
+    FLASH_NOR_RET_VENDOR_NOT_SUPPORT,
+    FLASH_NOR_RET_LOCK_FAILED,
+    FLASH_NOR_RET_UNLOCK_FAILED,
+    FLASH_NOR_RET_BIT_MODE_SET_FAILED,
+    FLASH_NOR_RET_BIT_MODE_NOT_SUPPORT,
+    FLASH_NOR_RET_ILLEGAL_OPERATION,
+    FLASH_NOR_RET_PARAM_INVALID,
+    FLASH_NOR_RET_WAIT_BUSY_FAILED,
+    FLASH_NOR_RET_IDX_OUT_OF_RANGE,
+    FLASH_NOR_RET_ADDR_OUT_OF_RANGE,
+    FLASH_NOR_RET_ADDR_LARGER_THAN_FLASH_SIZE,
+    FLASH_NOR_RET_CAL_IN_PHYSICAL_CYC_NOT_FOUND,
+    FLASH_NOR_RET_CAL_RD_DUMMY_LENGTH_NOT_FOUND,
+    FLASH_NOR_RET_CAL_FAILED,
+    FLASH_NOR_RET_MALLOC_FAILED,
+    FLASH_NOR_RET_HOOK_FUNC,
+    FLASH_NOR_RET_SUSPEND_UNNECCESSARY,
+    FLASH_NOR_RET_SET_4_BYTE_ADDRESS_MODE_FAILED,
+    FLASH_NOR_RET_SUCCESS,
+    FLASH_NOR_RET_SET_RD_DUMMY_LENGTH_FAIL
+} FLASH_NOR_RET_TYPE;
+
+typedef enum
+{
+    FLASH_NOR_IDX_SPIC0,            /* Nor flash controlled by SPIC0 */
+    FLASH_NOR_IDX_SPIC1,
+    FLASH_NOR_IDX_SPIC2,
+    FLASH_NOR_IDX_SPIC3,
+    FLASH_NOR_IDX_MAX
+} FLASH_NOR_IDX_TYPE;
+
+typedef enum
+{
+    FLASH_NOR_1_BIT_MODE,
+    FLASH_NOR_2_BIT_MODE,
+    FLASH_NOR_4_BIT_MODE,
+    FLASH_NOR_DTR_4_BIT_MODE,
+    FLASH_NOR_8_BIT_MODE,
+} FLASH_NOR_BIT_MODE;
+
+typedef enum
+{
+    FLASH_NOR_REQ_NONE          = 0x00,
+    FLASH_NOR_REQ_READ          = 0x01,
+    FLASH_NOR_REQ_WRITE         = 0x02,
+    FLASH_NOR_REQ_RW_MASK       = 0x03,
+
+    FLASH_NOR_REQ_ERASE_SECTOR  = 0x04,
+    FLASH_NOR_REQ_ERASE_BLOCK   = 0x08,
+    FLASH_NOR_REQ_ERASE_CHIP    = 0x10,
+    FLASH_NOR_REQ_ERASE_MASK    = 0x1C,
+
+    FLASH_NOR_REQ_DMA_READ      = 0x20,
+    FLASH_NOR_REQ_DMA_WRITE     = 0x40,
+    FLASH_NOR_REQ_DMA_MASK      = 0x60,
+} FLASH_NOR_REQ_TYPE;
+
+typedef enum
+{
+    FLASH_NOR_EXIST_NONE        = 0,
+    FLASH_NOR_EXIST_BASIC_CMD   = 1,
+    FLASH_NOR_EXIST_ADV_CMD     = 2,
+    FLASH_NOR_EXIST_QUERY_INFO  = 4,
+    FLASH_NOR_EXIST_ALL         = 7,
+} FLASH_NOR_EXIST_LV;
+
+
+/****************************************************************************************
+ * Nor Flash Callback Definition
+ ****************************************************************************************/
+/** @defgroup FMC_Flash_Callback_Definition  FMC Flash Callback Definition
+  * @ingroup FMC_Exported_Types
+  * @brief
+  * @{
+  */
+typedef void (*FLASH_NOR_ASYNC_CB)(void);
+/** End of FMC_Flash_Callback_Definition
+  * @}
+  */
+/** End of FMC_Exported_Types
+  * @}
+  */
+/** End of FMC
+ * @}
+ */
+
+#endif
diff --git a/bee/drivers/fmc/inc/rtl87x2j/eflash.h b/bee/drivers/fmc/inc/rtl87x2j/eflash.h
new file mode 100644
index 00000000..68eedea3
--- /dev/null
+++ b/bee/drivers/fmc/inc/rtl87x2j/eflash.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef EFLASH_API_H
+#define EFLASH_API_H
+
+#include <stdlib.h>
+#include <stdbool.h>
+bool eflash_write(uint32_t addr, uint8_t *data, uint32_t len);
+bool eflash_read(uint32_t addr, uint8_t *data, uint32_t len);
+bool eflash_erase(uint32_t addr);
+#endif
diff --git a/bee/drivers/gpio/CMakeLists.txt b/bee/drivers/gpio/CMakeLists.txt
new file mode 100644
index 00000000..5298ae51
--- /dev/null
+++ b/bee/drivers/gpio/CMakeLists.txt
@@ -0,0 +1,8 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+if(CONFIG_REALTEK_BEE_COMMON_DRIVER)
+    zephyr_include_directories(inc)
+endif()
+
+add_subdirectory_ifdef(CONFIG_REALTEK_BEE_GPIO src)
diff --git a/bee/drivers/gpio/Kconfig b/bee/drivers/gpio/Kconfig
new file mode 100644
index 00000000..3dd6d780
--- /dev/null
+++ b/bee/drivers/gpio/Kconfig
@@ -0,0 +1,8 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config REALTEK_BEE_GPIO
+	bool "Realtek Bee GPIO driver"
+	default n
+	help
+	  This option enables the GPIO driver for Realtek Bee.
diff --git a/bee/drivers/gpio/inc/rtl_gpio.h b/bee/drivers/gpio/inc/rtl_gpio.h
new file mode 100644
index 00000000..23ff0067
--- /dev/null
+++ b/bee/drivers/gpio/inc/rtl_gpio.h
@@ -0,0 +1,1243 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *               Define to prevent recursive inclusion
+ *============================================================================*/
+#ifndef RTL_GPIO_H
+#define RTL_GPIO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*============================================================================*
+ *                        Header Files
+ *============================================================================*/
+#include "utils/rtl_utils.h"
+#if defined (CONFIG_SOC_SERIES_RTL87X2G)
+#include "gpio/src/device/rtl87x2g/rtl_gpio_def.h"
+#include "pinmux/inc/rtl87x2g/pin_def.h"
+#elif defined (CONFIG_SOC_SERIES_RTL87X3E)
+#include "gpio/src/device/rtl87x3e/rtl_gpio_def.h"
+#include "pinmux/inc/rtl87x3e/pin_def.h"
+#elif defined (CONFIG_SOC_SERIES_RTL87X3D)
+#include "gpio/src/device/rtl87x3d/rtl_gpio_def.h"
+#include "pinmux/inc/rtl87x3d/pin_def.h"
+#elif defined (CONFIG_SOC_SERIES_RTL87X2J)
+#include "gpio/src/device/rtl87x2j/rtl_gpio_def.h"
+#include "pinmux/inc/rtl87x2j/pin_def.h"
+#elif defined (CONFIG_SOC_SERIES_RTL87X3J)
+#include "gpio/src/device/rtl87x3j/rtl_gpio_def.h"
+#include "pinmux/inc/rtl87x3j/pin_def.h"
+#endif
+
+/** \defgroup GPIO        GPIO
+  * \brief
+  * \{
+  */
+
+/*============================================================================*
+ *                         Constants
+ *============================================================================*/
+/** \defgroup GPIO_Exported_Constants GPIO Exported Constants
+  * \brief
+  * \{
+  */
+
+/**
+ * \defgroup    GPIO_Number GPIO Number
+ * \{
+ * \ingroup     GPIO_Exported_Constants
+ */
+#ifdef GPIOA
+#define GPIOA0   0
+#define GPIOA1   1
+#define GPIOA2   2
+#define GPIOA3   3
+#define GPIOA4   4
+#define GPIOA5   5
+#define GPIOA6   6
+#define GPIOA7   7
+#define GPIOA8   8
+#define GPIOA9   9
+#define GPIOA10  10
+#define GPIOA11  11
+#define GPIOA12  12
+#define GPIOA13  13
+#define GPIOA14  14
+#define GPIOA15  15
+#define GPIOA16  16
+#define GPIOA17  17
+#define GPIOA18  18
+#define GPIOA19  19
+#define GPIOA20  20
+#define GPIOA21  21
+#define GPIOA22  22
+#define GPIOA23  23
+#define GPIOA24  24
+#define GPIOA25  25
+#define GPIOA26  26
+#define GPIOA27  27
+#define GPIOA28  28
+#define GPIOA29  29
+#define GPIOA30  30
+#define GPIOA31  31
+#endif
+#ifdef GPIOB
+#define GPIOB0   32
+#define GPIOB1   33
+#define GPIOB2   34
+#define GPIOB3   35
+#define GPIOB4   36
+#define GPIOB5   37
+#define GPIOB6   38
+#define GPIOB7   39
+#define GPIOB8   40
+#define GPIOB9   41
+#define GPIOB10  42
+#define GPIOB11  43
+#define GPIOB12  44
+#define GPIOB13  45
+#define GPIOB14  46
+#define GPIOB15  47
+#define GPIOB16  48
+#define GPIOB17  49
+#define GPIOB18  50
+#define GPIOB19  51
+#define GPIOB20  52
+#define GPIOB21  53
+#define GPIOB22  54
+#define GPIOB23  55
+#define GPIOB24  56
+#define GPIOB25  57
+#define GPIOB26  58
+#define GPIOB27  59
+#define GPIOB28  60
+#define GPIOB29  61
+#define GPIOB30  62
+#define GPIOB31  63
+#endif
+#ifdef GPIOC
+#define GPIOC0   64
+#define GPIOC1   65
+#define GPIOC2   66
+#define GPIOC3   67
+#define GPIOC4   68
+#define GPIOC5   69
+#define GPIOC6   70
+#define GPIOC7   71
+#define GPIOC8   72
+#define GPIOC9   73
+#define GPIOC10  74
+#define GPIOC11  75
+#define GPIOC12  76
+#define GPIOC13  77
+#define GPIOC14  78
+#define GPIOC15  79
+#define GPIOC16  80
+#define GPIOC17  81
+#define GPIOC18  82
+#define GPIOC19  83
+#define GPIOC20  84
+#define GPIOC21  85
+#define GPIOC22  86
+#define GPIOC23  87
+#define GPIOC24  88
+#define GPIOC25  89
+#define GPIOC26  90
+#define GPIOC27  91
+#define GPIOC28  92
+#define GPIOC29  93
+#define GPIOC30  94
+#define GPIOC31  95
+#endif
+#ifdef GPIOD
+#define GPIOD0   96
+#define GPIOD1   97
+#define GPIOD2   98
+#define GPIOD3   99
+#define GPIOD4   100
+#define GPIOD5   101
+#define GPIOD6   102
+#define GPIOD7   103
+#define GPIOD8   104
+#define GPIOD9   105
+#define GPIOD10  106
+#define GPIOD11  107
+#define GPIOD12  108
+#define GPIOD13  109
+#define GPIOD14  110
+#define GPIOD15  111
+#define GPIOD16  112
+#define GPIOD17  113
+#define GPIOD18  114
+#define GPIOD19  115
+#define GPIOD20  116
+#define GPIOD21  117
+#define GPIOD22  118
+#define GPIOD23  119
+#define GPIOD24  120
+#define GPIOD25  121
+#define GPIOD26  122
+#define GPIOD27  123
+#define GPIOD28  124
+#define GPIOD29  125
+#define GPIOD30  126
+#define GPIOD31  127
+#endif
+
+/** End of GPIO_Number
+  * \}
+  */
+
+/**
+ * \defgroup    GPIO_Pins_Define GPIO Pins Define
+ * \{
+ * \ingroup     GPIO_Exported_Constants
+ */
+#define GPIO_Pin_0                 (BIT0)   /*!< Pin 0 selected   */
+#define GPIO_Pin_1                 (BIT1)   /*!< Pin 1 selected   */
+#define GPIO_Pin_2                 (BIT2)   /*!< Pin 2 selected   */
+#define GPIO_Pin_3                 (BIT3)   /*!< Pin 3 selected   */
+#define GPIO_Pin_4                 (BIT4)   /*!< Pin 4 selected   */
+#define GPIO_Pin_5                 (BIT5)   /*!< Pin 5 selected   */
+#define GPIO_Pin_6                 (BIT6)   /*!< Pin 6 selected   */
+#define GPIO_Pin_7                 (BIT7)   /*!< Pin 7 selected   */
+#define GPIO_Pin_8                 (BIT8)   /*!< Pin 8 selected   */
+#define GPIO_Pin_9                 (BIT9)   /*!< Pin 9 selected   */
+#define GPIO_Pin_10                (BIT10)  /*!< Pin 10 selected  */
+#define GPIO_Pin_11                (BIT11)  /*!< Pin 11 selected  */
+#define GPIO_Pin_12                (BIT12)  /*!< Pin 12 selected  */
+#define GPIO_Pin_13                (BIT13)  /*!< Pin 13 selected  */
+#define GPIO_Pin_14                (BIT14)  /*!< Pin 14 selected  */
+#define GPIO_Pin_15                (BIT15)  /*!< Pin 15 selected  */
+#define GPIO_Pin_16                (BIT16)  /*!< Pin 16 selected  */
+#define GPIO_Pin_17                (BIT17)  /*!< Pin 17 selected  */
+#define GPIO_Pin_18                (BIT18)  /*!< Pin 18 selected  */
+#define GPIO_Pin_19                (BIT19)  /*!< Pin 19 selected  */
+#define GPIO_Pin_20                (BIT20)  /*!< Pin 20 selected  */
+#define GPIO_Pin_21                (BIT21)  /*!< Pin 21 selected  */
+#define GPIO_Pin_22                (BIT22)  /*!< Pin 22 selected  */
+#define GPIO_Pin_23                (BIT23)  /*!< Pin 23 selected  */
+#define GPIO_Pin_24                (BIT24)  /*!< Pin 24 selected  */
+#define GPIO_Pin_25                (BIT25)  /*!< Pin 25 selected  */
+#define GPIO_Pin_26                (BIT26)  /*!< Pin 26 selected  */
+#define GPIO_Pin_27                (BIT27)  /*!< Pin 27 selected  */
+#define GPIO_Pin_28                (BIT28)  /*!< Pin 28 selected  */
+#define GPIO_Pin_29                (BIT29)  /*!< Pin 29 selected  */
+#define GPIO_Pin_30                (BIT30)  /*!< Pin 30 selected  */
+#define GPIO_Pin_31                (BIT31)  /*!< Pin 31 selected  */
+#define GPIO_Pin_All               ((uint32_t)0xFFFFFFFF)  /*!< All pins selected */
+
+#define IS_GET_GPIO_PIN(PIN)       (((PIN) == GPIO_Pin_0) || \
+                                    ((PIN) == GPIO_Pin_1) || \
+                                    ((PIN) == GPIO_Pin_2) || \
+                                    ((PIN) == GPIO_Pin_3) || \
+                                    ((PIN) == GPIO_Pin_4) || \
+                                    ((PIN) == GPIO_Pin_5) || \
+                                    ((PIN) == GPIO_Pin_6) || \
+                                    ((PIN) == GPIO_Pin_7) || \
+                                    ((PIN) == GPIO_Pin_8) || \
+                                    ((PIN) == GPIO_Pin_9) || \
+                                    ((PIN) == GPIO_Pin_10) || \
+                                    ((PIN) == GPIO_Pin_11) || \
+                                    ((PIN) == GPIO_Pin_12) || \
+                                    ((PIN) == GPIO_Pin_13) || \
+                                    ((PIN) == GPIO_Pin_14) || \
+                                    ((PIN) == GPIO_Pin_15) || \
+                                    ((PIN) == GPIO_Pin_16) || \
+                                    ((PIN) == GPIO_Pin_17) || \
+                                    ((PIN) == GPIO_Pin_18) || \
+                                    ((PIN) == GPIO_Pin_19) || \
+                                    ((PIN) == GPIO_Pin_20) || \
+                                    ((PIN) == GPIO_Pin_21) || \
+                                    ((PIN) == GPIO_Pin_22) || \
+                                    ((PIN) == GPIO_Pin_23) || \
+                                    ((PIN) == GPIO_Pin_24) || \
+                                    ((PIN) == GPIO_Pin_25) || \
+                                    ((PIN) == GPIO_Pin_26) || \
+                                    ((PIN) == GPIO_Pin_27) || \
+                                    ((PIN) == GPIO_Pin_28) || \
+                                    ((PIN) == GPIO_Pin_29) || \
+                                    ((PIN) == GPIO_Pin_30) || \
+                                    ((PIN) == GPIO_Pin_31) || \
+                                    ((PIN) == GPIO_Pin_All))
+
+#define IS_GPIO_PIN(PIN)          ((PIN) != (uint32_t)0x00)
+
+/** End of GPIO_Pins_Define
+  * \}
+  */
+
+/**
+ * \defgroup    GPIO_Bit_Action GPIO Bit Action
+ * \{
+ * \ingroup     GPIO_Exported_Constants
+ */
+typedef enum
+{
+    Bit_RESET = 0,
+    Bit_SET
+} BitAction;
+
+#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET))
+
+/** End of GPIO_Bit_Action
+  * \}
+  */
+
+/**
+ * \defgroup    GPIO_direction GPIO direction
+ * \{
+ * \ingroup     GPIO_Exported_Constants
+ */
+typedef enum
+{
+    GPIO_DIR_IN   = 0x0, /**< GPIO Input direction */
+    GPIO_DIR_OUT  = 0x1, /**< GPIO Output direction */
+} GPIODir_TypeDef;
+
+#define IS_GPIO_DIR(DIR) (((DIR) == GPIO_DIR_IN) || ((DIR) == GPIO_DIR_OUT))
+
+/** End of GPIO_direction
+  * \}
+  */
+
+/**
+ * \defgroup    GPIO_output_mode GPIO output mode
+ * \{
+ * \ingroup     GPIO_Exported_Constants
+ */
+typedef enum
+{
+    GPIO_OUTPUT_PUSHPULL  = 0x0, /**< GPIO Output push-pull Mode */
+    GPIO_OUTPUT_OPENDRAIN = 0x1, /**< GPIO Output opendrain Mode */
+} GPIOOutputMode_TypeDef;
+
+#define IS_GPIO_OUTPUT_MODE(MODE) (((MODE) == GPIO_OUTPUT_PUSHPULL)|| ((MODE) == GPIO_OUTPUT_OPENDRAIN))
+
+/** End of GPIO_output_mode
+  * \}
+  */
+
+#if (GPIO_SUPPORT_SET_CONTROL_MODE == 1)
+/**
+ * \brief       GPIO control mode enumeration.
+ *
+ * \ingroup     GPIO_Exported_Constants
+ */
+typedef enum
+{
+    GPIO_SOFTWARE_MODE = 0x0, /**< Gpio Software mode(default) */
+    GPIO_HARDWARE_MODE  = 0x1, /**< Gpio Hardware control mode  */
+} GPIOControlMode_Typedef;
+
+#define IS_GPIO_CONTROL_MODDE(MODE) (((MODE) == GPIO_SOFTWARE_MODE) || \
+                                     ((MODE) == GPIO_HARDWARE_MODE))
+#endif
+
+/**
+ * \defgroup    GPIO_interrupt_trigger GPIO interrupt trigger
+ * \{
+ * \ingroup     GPIO_Exported_Constants
+ */
+typedef enum
+{
+    GPIO_TRIGGER_LEVEL = 0x0,     /**< This interrupt is level trigger. */
+    GPIO_TRIGGER_EDGE  = 0x1,     /**< This interrupt is edge trigger. */
+#if GPIO_SUPPORT_BOTHEDGE
+    GPIO_TRIGGER_BOTH_EDGE = 0x2, /**< This interrupt is both edge trigger. */
+#endif
+} GPIOTrigger_TypeDef;
+
+#define IS_GPIO_TRIGGER_TYPE(TYPE) (((TYPE) == GPIO_TRIGGER_LEVEL) || \
+                                    ((TYPE) == GPIO_TRIGGER_EDGE))
+
+/** End of GPIO_interrupt_trigger
+  * \}
+  */
+
+/**
+ * \defgroup    GPIO_interrupt_polarity GPIO interrupt polarity
+ * \{
+ * \ingroup     GPIO_Exported_Constants
+ */
+typedef enum
+{
+    GPIO_POLARITY_ACTIVE_LOW  = 0x0, /**< Setting interrupt to low active. */
+    GPIO_POLARITY_ACTIVE_HIGH = 0x1, /**< Setting interrupt to high active. */
+} GPIOPolarity_TypeDef;
+
+#define IS_GPIO_POLARITY_TYPE(TYPE) (((TYPE) == GPIO_POLARITY_ACTIVE_LOW) || \
+                                     ((TYPE) == GPIO_POLARITY_ACTIVE_HIGH))
+
+/** End of GPIO_interrupt_polarity
+  * \}
+  */
+
+#if (GPIO_SUPPORT_RAP_FUNCTION == 1)
+/**
+ * \defgroup    GPIO_Action GPIO Action
+ * \{
+ * \ingroup     GPIO_Exported_Constants
+ */
+typedef enum
+{
+    GPIO_ACTION_DRSET = 0,
+    GPIO_ACTION_DRCLR = 1,
+    GPIO_ACTION_DRTOGGLE = 2,
+} GPIOAction_TypeDef;
+
+/** End of GPIO_Action
+  * \}
+  */
+
+#endif
+
+/** End of GPIO_Exported_Constants
+  * \}
+  */
+
+/*============================================================================*
+ *                         Types
+ *============================================================================*/
+/** \defgroup GPIO_Exported_Types GPIO Exported Types
+  * \brief
+  * \{
+  */
+
+/**
+ * \brief       GPIO init structure definition.
+ *
+ * \ingroup     GPIO_Exported_Types
+ */
+typedef struct
+{
+
+    uint32_t                GPIO_Pin;           /**< Specifies the GPIO pins to be configured.
+                                                     This parameter can be any value of \ref GPIO_Pins_Define. */
+
+    GPIODir_TypeDef         GPIO_Dir;           /**< Specifies the GPIO direction. */
+
+#if (GPIO_SUPPORT_OUTPUT_MODE_SELECT == 1)
+    GPIOOutputMode_TypeDef  GPIO_OutPutMode;    /**< Specifies the GPIO output mode. */
+#endif
+
+#if (GPIO_SUPPORT_SET_CONTROL_MODE == 1)
+    GPIOControlMode_Typedef GPIO_ControlMode;   /**< Specifies the gpio mode. */
+#endif
+
+    FunctionalState         GPIO_INTEventEn;    /**< Enable or disable GPIO interrupt. */
+
+    GPIOTrigger_TypeDef     GPIO_Trigger;       /**< Specifies the GPIO interrupt trigger. */
+
+    GPIOPolarity_TypeDef    GPIO_Polarity;      /**< Specifies the GPIO interrupt polarity. */
+
+    FunctionalState         GPIO_DebounceEn;    /**< Enable or disable debounce for interrupt. */
+
+    GPIODebClockSrc_TypeDef GPIO_DebClockSrc;   /**< Select debounce count clk source. */
+
+    GPIODebClockDiv_TypeDef GPIO_DebClockDiv;   /**< Specifies the debounce divide. */
+
+    uint8_t                 GPIO_DebCountLimit; /**< Specifies the debounce Limit.
+                                                        Debounce_time = (CntLimit + 1) * DEB_CLK. */
+} GPIO_InitTypeDef;
+
+/** End of GPIO_Exported_Types
+  * \}
+  */
+
+/*============================================================================*
+ *                         Functions
+ *============================================================================*/
+/** \defgroup GPIO_Exported_Functions GPIO Exported Functions
+  * \brief
+  * \{
+  */
+
+/**
+ * \brief   Deinitializes the GPIO peripheral registers to their default reset values.
+ *
+ * \param[in] GPIOx: Select the GPIO peripheral. \ref GPIO_Declaration
+ *
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_gpio_init(void)
+ * {
+ *     GPIO_DeInit(GPIOA);
+ * }
+ * \endcode
+ */
+void GPIO_DeInit(GPIO_TypeDef *GPIOx);
+
+/**
+ * \brief  Initializes the GPIO peripheral according to the specified
+ *         parameters in the GPIO_InitStruct.
+ *
+ * \param[in] GPIOx: Select the GPIO peripheral. \ref GPIO_Declaration
+ * \param[in] GPIO_InitStruct: Pointer to a GPIO_InitTypeDef structure that
+ *            contains the configuration information for the specified GPIO peripheral.
+ *
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_gpio_init(void)
+ * {
+ *     RCC_ClockCmd(GPIOA_CLOCK, ENABLE);
+ *
+ *     GPIO_InitTypeDef GPIO_InitStruct;
+ *     GPIO_StructInit(&GPIO_InitStruct);
+ *     GPIO_InitStruct.GPIO_Pin         = GPIO_GetPinBit(P0_0);
+ *     GPIO_InitStruct.GPIO_Dir         = GPIO_DIR_IN;
+ *     GPIO_InitStruct.GPIO_OutPutMode  = GPIO_OUTPUT_PUSHPULL;
+ *     GPIO_InitStruct.GPIO_INTEventEn  = ENABLE;
+ *     GPIO_InitStruct.GPIO_Trigger     = GPIO_TRIGGER_EDGE;
+ *     GPIO_InitStruct.GPIO_Polarity    = GPIO_POLARITY_ACTIVE_LOW;
+ *     GPIO_InitStruct.GPIO_DebounceEn  = ENABLE;
+ *     GPIO_InitStruct.GPIO_DebClockSrc = GPIO_DEB_CLOCK_SRC_32K;
+ *     GPIO_InitStruct.GPIO_DebClockDiv = GPIO_DEB_CLOCK_DIV_1;
+ *     GPIO_InitStruct.GPIO_DebCountLimit = 20;
+ *     GPIO_Init(GPIOA, &GPIO_InitStruct);
+ *
+ *     NVIC_InitTypeDef NVIC_InitStruct;
+ *     NVIC_InitStruct.NVIC_IRQChannel = GPIOA0_IRQn;
+ *     NVIC_InitStruct.NVIC_IRQChannelPriority = 3;
+ *     NVIC_InitStruct.NVIC_IRQChannelCmd = ENABLE;
+ *     NVIC_Init(&NVIC_InitStruct);
+
+ *     GPIO_MaskINTConfig(GPIOA, GPIO_GetPinBit(P0_0), DISABLE);
+ *     GPIO_INTConfig(GPIOA, GPIO_GetPinBit(P0_0), ENABLE);
+ * }
+ * \endcode
+ */
+void GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_InitStruct);
+
+/**
+ * \brief    Fills each GPIO_InitStruct member with its default value.
+ *
+ * \param[in]  GPIO_InitStruct: Pointer to a GPIO_InitTypeDef structure which will be initialized.
+ *
+ * \return   None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_gpio_init(void)
+ * {
+ *     RCC_ClockCmd(GPIOA_CLOCK, ENABLE);
+ *
+ *     GPIO_InitTypeDef GPIO_InitStruct;
+ *     GPIO_StructInit(&GPIO_InitStruct);
+ *     GPIO_InitStruct.GPIO_Pin        = GPIO_GetPinBit(P0_0);
+ *     GPIO_InitStruct.GPIO_Dir        = GPIO_DIR_IN;
+ *     GPIO_InitStruct.GPIO_OutPutMode = GPIO_OUTPUT_PUSHPULL;
+ *     GPIO_InitStruct.GPIO_INTEventEn = ENABLE;
+ *     GPIO_InitStruct.GPIO_Trigger    = GPIO_TRIGGER_EDGE;
+ *     GPIO_InitStruct.GPIO_Polarity   = GPIO_POLARITY_ACTIVE_LOW;
+ *     GPIO_InitStruct.GPIO_DebounceEn = ENABLE;
+ *     GPIO_InitStruct.GPIO_DebClockSrc = GPIO_DEB_CLOCK_SRC_32K;
+ *     GPIO_InitStruct.GPIO_DebClockDiv = GPIO_DEB_CLOCK_DIV_1;
+ *     GPIO_InitStruct.GPIO_DebCountLimit = 20;
+ *     GPIO_Init(GPIOA, &GPIO_InitStruct);
+ * }
+ * \endcode
+ */
+void GPIO_StructInit(GPIO_InitTypeDef *GPIO_InitStruct);
+
+/**
+ * \brief   Enable the specified GPIO pin interrupt.
+ *
+ * \param[in] GPIOx: Select the GPIO peripheral. \ref GPIO_Declaration
+ * \param[in] GPIO_Pin: GPIO_Pin can be 0 or 31.
+ * \param[in] NewState: Enable or disable interrupt
+ *
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_gpio_init(void)
+ * {
+ *     RCC_ClockCmd(GPIOA_CLOCK, ENABLE);
+ *
+ *     GPIO_InitTypeDef GPIO_InitStruct;
+ *     GPIO_StructInit(&GPIO_InitStruct);
+ *     GPIO_InitStruct.GPIO_Pin         = GPIO_GetPinBit(P0_0);
+ *     GPIO_InitStruct.GPIO_Dir         = GPIO_DIR_IN;
+ *     GPIO_InitStruct.GPIO_OutPutMode  = GPIO_OUTPUT_PUSHPULL;
+ *     GPIO_InitStruct.GPIO_INTEventEn  = ENABLE;
+ *     GPIO_InitStruct.GPIO_Trigger     = GPIO_TRIGGER_EDGE;
+ *     GPIO_InitStruct.GPIO_Polarity    = GPIO_POLARITY_ACTIVE_LOW;
+ *     GPIO_InitStruct.GPIO_DebounceEn  = ENABLE;
+ *     GPIO_InitStruct.GPIO_DebClockSrc = GPIO_DEB_CLOCK_SRC_32K;
+ *     GPIO_InitStruct.GPIO_DebClockDiv = GPIO_DEB_CLOCK_DIV_1;
+ *     GPIO_InitStruct.GPIO_DebCountLimit = 20;
+ *     GPIO_Init(GPIOA, &GPIO_InitStruct);
+ *
+ *     NVIC_InitTypeDef NVIC_InitStruct;
+ *     NVIC_InitStruct.NVIC_IRQChannel = GPIOA0_IRQn;
+ *     NVIC_InitStruct.NVIC_IRQChannelPriority = 3;
+ *     NVIC_InitStruct.NVIC_IRQChannelCmd = ENABLE;
+ *     NVIC_Init(&NVIC_InitStruct);
+
+ *     GPIO_MaskINTConfig(GPIOA, GPIO_GetPinBit(P0_0), DISABLE);
+ *     GPIO_INTConfig(GPIOA, GPIO_GetPinBit(P0_0), ENABLE);
+ * }
+ * \endcode
+ */
+void GPIO_INTConfig(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin, FunctionalState NewState);
+
+
+/**
+ * \brief   Clear the specified GPIO pin interrupt pending bit.
+ *
+ * \param[in] GPIOx: Select the GPIO peripheral. \ref GPIO_Declaration
+ * \param[in] GPIO_Pin: GPIO_Pin can be 0 to 31.
+ *
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void gpio_demo(void)
+ * {
+ *     driver_gpio_init();
+ * }
+ *
+ * void GPIOA0_Handler(void)
+ * {
+ *     GPIO_INTConfig(GPIOA, GPIO_GetPinBit(P0_0), DISABLE);
+ *     GPIO_MaskINTConfig(GPIOA, GPIO_GetPinBit(P0_0), ENABLE);
+ *     //Add user code here.
+ *     GPIO_ClearINTPendingBit(GPIOA, GPIO_GetPinBit(P0_0));
+ *     GPIO_MaskINTConfig(GPIOA, GPIO_GetPinBit(P0_0), DISABLE);
+ *     GPIO_INTConfig(GPIOA, GPIO_GetPinBit(P0_0), ENABLE);
+}
+ * \endcode
+ */
+void GPIO_ClearINTPendingBit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin);
+
+
+/**
+ * \brief   Mask the specified GPIO pin interrupt.
+ *
+ * \param[in] GPIOx: Select the GPIO peripheral. \ref GPIO_Declaration
+ * \param[in] GPIO_Pin: GPIO_Pin can be 0 to 31.
+ * \param[in] NewState: Mask or unmask interrupt.
+ *
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ *
+ * void gpio_demo(void)
+ * {
+ *     driver_gpio_init();
+ * }
+ *
+ * void GPIOA0_Handler(void)
+ * {
+ *     GPIO_INTConfig(GPIOA, GPIO_GetPinBit(P0_0), DISABLE);
+ *     GPIO_MaskINTConfig(GPIOA, GPIO_GetPinBit(P0_0), ENABLE);
+ *
+ *     //Add user code here.
+ *
+ *     GPIO_ClearINTPendingBit(GPIOA, GPIO_GetPinBit(P0_0));
+ *     GPIO_MaskINTConfig(GPIOA, GPIO_GetPinBit(P0_0), DISABLE);
+ *     GPIO_INTConfig(GPIOA, GPIO_GetPinBit(P0_0), ENABLE);
+ * }
+ * \endcode
+ */
+void GPIO_MaskINTConfig(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin, FunctionalState NewState);
+
+/**
+ * \brief   Get GPIO GROUP through the given pad.
+ *
+ * \param[in] GPIOx: Select the GPIO peripheral. \ref GPIO_Declaration
+ *
+ * \return  GPIOx: GPIO peripheral. \ref GPIO_Declaration
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ *
+ * void gpio_demo(void)
+ * {
+ *      GPIO_TypeDef gpio_port = GPIO_GetPort(P0_0);
+ *      //result: gpio_port is GPIOA
+ * }
+ *
+ * \endcode
+ */
+GPIO_TypeDef *GPIO_GetPort(uint8_t Pin_num);
+
+/**
+ * \brief   Get the GPIO_Pin (GPIO0 ~ GPIO31) through the given PAD num.
+ *
+ * \param[in]  Pin_num: Pin number to be configured. \ref Pin_Number
+ *
+ * \return  GPIOx(x is 0~31) value.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void gpio_demo(void)
+ * {
+ *     uint32_t gpio_pin = GPIO_GetPinBit(P0_0);
+ *     //result: gpio_pin is GPIO_Pin_0
+ * }
+ * \endcode
+ */
+uint32_t GPIO_GetPinBit(uint8_t Pin_num);
+
+/**
+ * \brief   Get GPIO value ( \ref GPIO_Declaration ) through the given pad.
+ *
+ * \param[in] Pin_num: Pin number to be configured. \ref Pin_Number
+ *
+ * \return  GPIO value ( \ref GPIO_Declaration ).
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void gpio_demo(void)
+ * {
+ *     uint8_t gpio_num = GPIO_GetNum(P0_0);
+ *     //result: gpio_num = 0, i.e. GPIOA0.
+ * }
+ * \endcode
+ */
+uint8_t GPIO_GetNum(uint8_t Pin_num);
+
+/**
+ * \brief   Enable GPIO debounce clock.
+ *
+ * \param[in] GPIOx: Select the GPIO peripheral. \ref GPIO_Declaration
+ * \param[in] GPIO_Pin: GPIO_Pin can be 0 to 31.
+ * \param[in] NewState: Disable or enable debounce clock.
+ *
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void gpio_demo(void)
+ * {
+ *     GPIO_ExtDebCmd(GPIOA, GPIO_GetPinBit(P0_0), ENABLE);
+ * }
+ * \endcode
+ */
+void GPIO_ExtDebCmd(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin, FunctionalState NewState);
+
+/**
+ * \brief  Set GPIO debounce parameters.
+ *
+ * \param[in]  GPIOx: where x can be A to D to select the GPIO peripheral.
+ * \param[in]  GPIO_Pin: GPIO_Pin can be 0 to 31.
+ * \param[in]  GPIO_DebClockSrc: GPIO debounce clock source selection.
+ * \param[in]  GPIO_DebClockDiv: GPIO debounce clock divider selection.
+ * \param[in]  GPIO_DebCountLimit: debounce time can be calculated by count limit.
+ *
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void gpio_demo(void)
+ * {
+ *     GPIO_ExtDebUpdate(GPIOA, GPIO_GetPinBit(P0_0), GPIO_DEB_CLOCK_SRC_32K, GPIO_DEB_CLOCK_DIV_1, 20);
+ * }
+ * \endcode
+ */
+void GPIO_ExtDebUpdate(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin,
+                       GPIODebClockSrc_TypeDef GPIO_DebClockSrc,
+                       GPIODebClockDiv_TypeDef GPIO_DebClockDiv,
+                       uint8_t                 GPIO_DebCountLimit);
+
+/**
+ * \brief   Read the specified input port pin.
+ *
+ * \param[in] GPIOx: Select the GPIO peripheral. \ref GPIO_Declaration
+ * \param[in] GPIO_Pin: Specifies the port bit to read.
+ *            This parameter can be GPIO_Pin where can be 0~31.
+ *
+ * \return  The input port pin value.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void gpio_demo(void)
+ * {
+ *     uint8_t input_bit = GPIO_ReadInputDataBit(GPIOA, GPIO_GetPinBit(P0_0));
+ * }
+ * \endcode
+ */
+uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin);
+
+/**
+ * \brief  Read value of all GPIO input data port.
+ *
+ * \param[in] GPIOx: Select the GPIO peripheral. \ref GPIO_Declaration
+ *
+ * \return GPIO input data port value.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void gpio_demo(void)
+ * {
+ *     uint32_t input_data = GPIO_ReadInputData(GPIOA);
+ * }
+ * \endcode
+ */
+uint32_t GPIO_ReadInputData(GPIO_TypeDef *GPIOx);
+
+/**
+ * \brief   Read the specified output port pin.
+ *
+ * \param[in] GPIOx: Select the GPIO peripheral. \ref GPIO_Declaration
+ * \param[in] GPIO_Pin: Specifies the port bit to read.
+ *            This parameter can be GPIO_Pin where can be 0~31.
+ *
+ * \return The output port pin value.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void gpio_demo(void)
+ * {
+ *     uint8_t output_bit = GPIO_ReadOutputDataBit(GPIOA, GPIO_GetPinBit(P0_0));
+ * }
+ * \endcode
+ */
+uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin);
+
+/**
+ * \brief   Read value of all GPIO output data port.
+ *
+ * \param[in] GPIOx: Select the GPIO peripheral. \ref GPIO_Declaration
+ *
+ * \return  GPIO output data port value.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void gpio_demo(void)
+ * {
+ *     uint32_t output_data = GPIO_ReadOutputData(GPIOA);
+ * }
+ * \endcode
+ */
+uint32_t GPIO_ReadOutputData(GPIO_TypeDef *GPIOx);
+
+/**
+ * \brief   Sets the selected data port bit.
+ *
+ * \param[in] GPIOx: Select the GPIO peripheral. \ref GPIO_Declaration
+ * \param[in] GPIO_Pin: Specifies the port bit to be written.
+ *            This parameter can be GPIO_Pin_x where x can be 0~31 or GPIO_Pin_All.
+ *
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void gpio_demo(void)
+ * {
+ *     GPIO_SetBits(GPIOA, GPIO_GetPinBit(P0_0));
+ * }
+ * \endcode
+ */
+void GPIO_SetBits(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin);
+
+/**
+ * \brief   Reset the selected data port bit.
+ *
+ * \param[in] GPIOx: Select the GPIO peripheral. \ref GPIO_Declaration
+ * \param[in] GPIO_Pin: Specifies the port bits to be written.
+ *            This parameter can be GPIO_Pin_0 to GPIO_Pin_31 or GPIO_Pin_All.
+ *
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void gpio_demo(void)
+ * {
+ *     GPIO_ResetBits(GPIOA, GPIO_GetPinBit(P0_0));
+ * }
+ * \endcode
+ */
+void GPIO_ResetBits(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin);
+
+/**
+ * \brief  Set or clear the selected data port bit.
+ *
+ * \param[in] GPIOx: Select the GPIO peripheral. \ref GPIO_Declaration
+ * \param[in] GPIO_Pin: Specifies the port bit to be written.
+ *            This parameter can be one of GPIO_Pin where can be 0~31.
+ * \param[in] BitVal: specifies the value to be written to the selected bit.
+ *            This parameter can be one of the BitAction enum values:
+ *            \arg Bit_RESET: To clear the port pin.
+ *            \arg Bit_SET: To set the port pin.
+ *
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void gpio_demo(void)
+ * {
+ *     GPIO_WriteBit(GPIOA, GPIO_GetPinBit(P0_0), Bit_SET);
+ * }
+ * \endcode
+ */
+void GPIO_WriteBit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin, BitAction BitVal);
+
+/**
+ * \brief   Set or clear data port.
+ *
+ * \param[in] GPIOx: Select the GPIO peripheral. \ref GPIO_Declaration
+ * \param[in] PortVal: Specifies the value to be written to the selected bit.
+ *
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void gpio_demo(void)
+ * {
+ *     GPIO_Write(GPIOA, 0xFFFFFFFF);
+ * }
+ * \endcode
+ */
+void GPIO_Write(GPIO_TypeDef *GPIOx, uint32_t PortVal);
+
+
+/**
+ * \brief  Get GPIO interrupt status.
+ *
+ * \param[in] GPIOx: Select the GPIO peripheral. \ref GPIO_Declaration
+ * \param[in] GPIO_Pin: Specifies the port bit to be written.
+ *            This parameter can be one of GPIO_Pin where can be 0~31.
+ *
+ * \return The new state of GPIO_INT (SET or RESET).
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void gpio_demo(void)
+ * {
+ *     ITStatus int_status = GPIO_GetINTStatus(GPIOA, GPIO_GetPinBit(P0_0));
+ * }
+ * \endcode
+ */
+ITStatus GPIO_GetINTStatus(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin);
+
+/**
+ * rtl876x_gpio.h
+ *
+ * \brief  Specifies the direction for the selected pins.
+ *
+ * \param[in] GPIOx: Select the GPIO peripheral. \ref GPIO_Declaration
+ * \param[in] GPIO_PinBit: Specifies the GPIO pins to be configured, please refer to "GPIO_pins_define" part.
+ *            This parameter can be one of the following values:
+ *            \arg GPIO_Pin_x, where x can be 0 ~ 31.
+ * \param[in] GPIO_Dir: Set the GPIO direction.
+ *            This parameter can be one of the following values:
+ *            \arg GPIO_DIR_IN: The direction is input.
+ *            \arg GPIO_DIR_OUT: The direction is output.
+ *
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void gpio_demo(void)
+ * {
+ *     GPIO_SetDirection(GPIOA, GPIO_GetPinBit(P3_0), GPIO_DIR_IN);
+ * }
+ * \endcode
+ */
+void GPIO_SetDirection(GPIO_TypeDef *GPIOx, uint32_t GPIO_PinBit,
+                       GPIODir_TypeDef GPIO_Dir);
+
+#if (GPIO_SUPPORT_OUTPUT_MODE_SELECT == 1)
+/**
+ * \brief  Set GPIO Output mode.
+ *
+ * \param[in] GPIOx: Select the GPIO peripheral. \ref GPIO_Declaration
+ * \param[in] GPIO_Pin: Specifies the port bit to be written.
+ *            This parameter can be one of GPIO_Pin_x where x can be 0~31.
+ * \param[in] GPIO_OutputMode: Specifies the output mode to be set.
+ *            This parameter can be one of the GPIOOutputMode_TypeDef enum values:
+ *            \arg GPIO_OUTPUT_OPENDRAIN: Setting Output push-pull Mode.
+ *            \arg GPIO_OUTPUT_PUSHPULL: Setting Output open-drain Mode.
+ *
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void gpio_demo(void)
+ * {
+ *     GPIO_SetOutputMode(GPIOA, GPIO_GetPinBit(P0_0), GPIO_OUTPUT_OPENDRAIN);
+ * }
+ * \endcode
+ */
+void GPIO_SetOutputMode(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin,
+                        GPIOOutputMode_TypeDef GPIO_OutputMode);
+#endif
+
+/**
+ * \brief  Get GPIO pad status.
+ *
+ * \param[in] GPIO_Pin: Specifies the port bit to be written.
+ *            This parameter can be one of GPIO_Pin_x where x can be 0~31.
+ *
+ * \return The new state of GPIO_Pad (SET or RESET).
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void gpio_demo(void)
+ * {
+ *     FlagStatus int_status = GPIO_GetPadStatus(GPIOA, GPIO_GetPinBit(P0_0));
+ * }
+ * \endcode
+ */
+FlagStatus GPIO_GetPadStatus(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin);
+
+/**
+ * \brief  Set GPIO Int Polarity.
+ *
+ * \param[in] GPIOx: Select the GPIO peripheral. \ref GPIO_Declaration
+ * \param[in] GPIO_Pin: Specifies the port bit to be written.
+ *            This parameter can be one of GPIO_Pin_x where x can be 0~31.
+ * \param[in] int_type: Specifies the polarity type to be set.
+ *            This parameter can be one of the GPIOPolarity_TypeDef enum values:
+ *            \arg GPIO_POLARITY_ACTIVE_LOW: Setting interrupt to low active.
+ *            \arg GPIO_POLARITY_ACTIVE_HIGH: Setting interrupt to high active.
+ *
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void GPIO_Init(void)
+ * {
+ *     GPIO_SetPolarity(GPIOx, GPIO_Pin, GPIO_POLARITY_ACTIVE_LOW);
+ * }
+ * \endcode
+ */
+void GPIO_SetPolarity(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin, GPIOPolarity_TypeDef Polarity);
+
+#if (GPIO_SUPPORT_RAP_FUNCTION == 1)
+
+void GPIO_RAPModeCmd(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin, FunctionalState NewState);
+
+void GPIO_ActionTrigger(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin, uint32_t Action);
+
+#if (GPIO_SUPPORT_RAP_EVENT_CONTROL == 1)
+/**
+ * \brief  Enable or disable RAP event.
+ *
+ * \param[in] GPIOx: Select the GPIO peripheral. \ref GPIO_Declaration
+ * \param[in] GPIO_Pin: Specifies the port bit to be written.
+ *            This parameter can be one of GPIO_Pin_x where x can be 0~31.
+ * \param[in] NewState: Enable or disable RAP event.
+ *
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void GPIO_Init(void)
+ * {
+ *     GPIO_RAPEventCmd(GPIOx, GPIO_Pin, ENABLE);
+ * }
+ * \endcode
+ */
+void GPIO_RAPEventCmd(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin, FunctionalState NewState);
+#endif
+#endif
+
+#if (GPIO_SUPPORT_AUTO_CLOCK == 1)
+
+void GPIO_ClockAutoModeCmd(GPIO_TypeDef *GPIOx, FunctionalState Newstate);
+
+#endif
+
+#if (GPIO_SUPPORT_WAKE_UP_FUNCTION == 1)
+/**
+ * \brief   Enable the GPIO wake up function.
+ *
+ * \param[in] GPIOx: Select the GPIO peripheral. \ref GPIO_Declaration
+ * \param[in] GPIO_Pin: GPIO_Pin can be 0 to 31.
+ * \param[in] NewState: Enable or disable the wake up function.
+ *
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ *
+ * void gpio_demo(void)
+ * {
+ *     GPIO_WakeUpConfig(GPIOA, GPIO_GetPinBit(P0_0), ENABLE);
+ * }
+ *
+ * \endcode
+ */
+void GPIO_WakeUpConfig(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin, FunctionalState NewState);
+
+/**
+ * \brief   Check whether the specified input GPIO pin is in debounce.
+ *
+ * \param[in] GPIOx: Select the GPIO peripheral. \ref GPIO_Declaration
+ * \param[in] GPIO_Pin: GPIO_Pin can be 0 to 31.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ *
+ * void gpio_demo(void)
+ * {
+ *     FlagStatus flag = GPIO_GetDebStatusBit(GPIOA, GPIO_GetPinBit(P0_0));
+ * }
+ *
+ * \endcode
+ */
+FlagStatus GPIO_GetDebStatusBit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin);
+
+/**
+ * \brief   Check whether any pin under the GPIO is in debounce.
+ *
+ * \param[in] GPIOx: Select the GPIO peripheral. \ref GPIO_Declaration
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ *
+ * void gpio_demo(void)
+ * {
+ *     FlagStatus flag = GPIO_GetDebStatus(GPIOA);
+ * }
+ *
+ * \endcode
+ */
+FlagStatus GPIO_GetDebStatus(GPIO_TypeDef *GPIOx);
+#endif
+
+#if (GPIO_SUPPORT_SELF_TRIGGER_FUNCTION == 1)
+/**
+ * \brief   Enable the GPIO self-trigger function.
+ *
+ * \param[in] GPIOx: Select the GPIO peripheral. \ref GPIO_Declaration
+ * \param[in] GPIO_Pin: GPIO_Pin can be 0 to 31.
+ * \param[in] NewState: Enable or disable the self-trigger function.
+ *
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ *
+ * void gpio_demo(void)
+ * {
+ *     GPIO_SelfTriggerConfig(GPIOA, GPIO_GetPinBit(P0_0), ENABLE);
+ * }
+ *
+ * \endcode
+ */
+void GPIO_SelfTriggerConfig(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin, FunctionalState NewState);
+#endif
+
+#if (GPIO_SUPPORT_INPUT_GATE_FUNCTION == 1)
+/**
+ * \brief   Enable the GPIO input gate function.
+ *
+ * \param[in] GPIOx: Select the GPIO peripheral. \ref GPIO_Declaration
+ * \param[in] GPIO_Pin: GPIO_Pin can be 0 to 31.
+ * \param[in] NewState: Enable or disable the input gate function.
+ *
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ *
+ * void gpio_demo(void)
+ * {
+ *     GPIO_InputGateConfig(GPIOA, GPIO_GetPinBit(P0_0), DISABLE);
+ * }
+ *
+ * \endcode
+ */
+void GPIO_InputGateConfig(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin, FunctionalState NewState);
+
+/**
+ * \brief   Check whether input is gate.
+ *
+ * \param[in] GPIOx: Select the GPIO peripheral. \ref GPIO_Declaration
+ * \param[in] GPIO_Pin: GPIO_Pin can be 0 to 31.
+ *
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ *
+ * void gpio_demo(void)
+ * {
+ *     bool ret = GPIO_IsInputGate(GPIOA, GPIO_GetPinBit(P0_0));
+ * }
+ *
+ * \endcode
+ */
+FlagStatus GPIO_IsInputGate(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin);
+#endif
+
+#if (GPIO_SUPPORT_SET_CONTROL_MODE == 1)
+/**
+ * \brief   Get the GPIO hardware port address.
+ *
+ * \param[in] GPIOx: Select the GPIO peripheral. \ref GPIO_Declaration
+ *
+ * \return The GPIO hardware port address.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ *
+ * void gpio_demo(void)
+ * {
+ *     uint32_t address = GPIO_GetHWPortAddress(GPIOA);
+ * }
+ *
+ * \endcode
+ */
+uint32_t GPIO_GetHWPortAddress(GPIO_TypeDef *GPIOx);
+#endif
+/** End of GPIO_Exported_Functions
+  * \}
+  */
+
+/** End of GPIO
+  * \}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RTL_GPIO_H */
+
+
+
diff --git a/bee/drivers/gpio/src/CMakeLists.txt b/bee/drivers/gpio/src/CMakeLists.txt
new file mode 100644
index 00000000..dd5e359a
--- /dev/null
+++ b/bee/drivers/gpio/src/CMakeLists.txt
@@ -0,0 +1,4 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+add_subdirectory(device)
diff --git a/bee/drivers/gpio/src/device/CMakeLists.txt b/bee/drivers/gpio/src/device/CMakeLists.txt
new file mode 100644
index 00000000..390b5305
--- /dev/null
+++ b/bee/drivers/gpio/src/device/CMakeLists.txt
@@ -0,0 +1,11 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+if(CONFIG_REALTEK_BEE_COMMON_DRIVER)
+    file(GLOB BEE_DRIVER_COMMON_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/rtl_common/*.c")
+    zephyr_library_sources(${BEE_DRIVER_COMMON_SOURCES})
+endif()
+
+add_soc_series_subdir(rtl8752h)
+add_soc_series_subdir(rtl87x2g)
+add_soc_series_subdir(rtl87x2j)
diff --git a/bee/drivers/gpio/src/device/rtl8752h/rtl876x_gpio.c b/bee/drivers/gpio/src/device/rtl8752h/rtl876x_gpio.c
new file mode 100644
index 00000000..a7c25d31
--- /dev/null
+++ b/bee/drivers/gpio/src/device/rtl8752h/rtl876x_gpio.c
@@ -0,0 +1,343 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "rtl876x_rcc.h"
+#include "rtl876x_gpio.h"
+#include "app_section.h"
+
+#ifdef _IS_ASIC_
+#define GPIO_CLOCK_SOURCE         (40000000)
+#define GPIO_CLOCK_SOURCE_KHZ     (40000)
+#else
+#define GPIO_CLOCK_SOURCE         (20000000)
+#define GPIO_CLOCK_SOURCE_KHZ     (20000)
+#endif
+
+/**
+  * @brief  Deinitializes the GPIO peripheral registers to their default reset values.
+  * @param  None.
+  * @retval None.
+  */
+void GPIO_DeInit(void)
+{
+    RCC_PeriphClockCmd(APBPeriph_GPIO, APBPeriph_GPIO_CLOCK, DISABLE);
+}
+
+/**
+  * @brief  Initializes the GPIO peripheral according to the specified
+  *         parameters in the GPIO_InitStruct.
+  * @param  GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that
+  *         contains the configuration information for the specified GPIO peripheral.
+  * @retval None
+  */
+void GPIO_Init(GPIO_InitTypeDef *GPIO_InitStruct)
+{
+    /* Check the parameters */
+    assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin));
+    assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode));
+    assert_param(IS_GPIOIT_LEVEL_TYPE(GPIO_InitStruct->GPIO_ITTrigger));
+    assert_param(IS_GPIOIT_POLARITY_TYPE(GPIO_InitStruct->GPIO_ITPolarity));
+    assert_param(IS_GPIOIT_DEBOUNCE_TYPE(GPIO_InitStruct->GPIO_ITDebounce));
+
+    /* GPIO configure */
+    if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_OUT)
+    {
+        GPIO->DATADIR |= GPIO_InitStruct->GPIO_Pin;
+
+        if (GPIO_InitStruct->GPIO_ControlMode == GPIO_SOFTWARE_MODE)
+        {
+            /* Config GPIO control software mode */
+            GPIO->DATASRC &= (~GPIO_InitStruct->GPIO_Pin);
+        }
+        else
+        {
+            /* Config GPIO hardware control mode */
+            GPIO->DATASRC |= (GPIO_InitStruct->GPIO_Pin);
+        }
+
+    }
+    else
+    {
+        /*Configure GPIO input mode */
+        GPIO->DATADIR = GPIO->DATADIR & (~GPIO_InitStruct->GPIO_Pin);
+
+        if (GPIO_InitStruct->GPIO_ITCmd == ENABLE)
+        {
+
+            GPIO->INTMASK = ~GPIO_Pin_All;
+
+            /* configure GPIO interrupt trigger type */
+            if (GPIO_InitStruct->GPIO_ITTrigger == GPIO_INT_Trigger_LEVEL)
+            {
+                GPIO->INTBOTHEDGE &= ~GPIO_InitStruct->GPIO_Pin;
+                GPIO->INTTYPE = GPIO->INTTYPE & (~GPIO_InitStruct->GPIO_Pin);
+
+                /* Level-sensitive synchronization enable register */
+                GPIO->LSSYNC |= GPIO_InitStruct->GPIO_Pin;
+            }
+            else if (GPIO_InitStruct->GPIO_ITTrigger == GPIO_INT_Trigger_EDGE)
+            {
+                GPIO->INTBOTHEDGE &= ~GPIO_InitStruct->GPIO_Pin;
+                GPIO->INTTYPE = (GPIO->INTTYPE & (~GPIO_InitStruct->GPIO_Pin))
+                                | GPIO_InitStruct->GPIO_Pin;
+            }
+            else
+            {
+                GPIO->INTBOTHEDGE |= GPIO_InitStruct->GPIO_Pin;
+            }
+
+            /* configure Interrupt polarity register */
+            if (GPIO_InitStruct->GPIO_ITPolarity == GPIO_INT_POLARITY_ACTIVE_LOW)
+            {
+                GPIO->INTPOLARITY = GPIO->INTPOLARITY & (~GPIO_InitStruct->GPIO_Pin);
+            }
+            else
+            {
+                GPIO->INTPOLARITY = (GPIO->INTPOLARITY & (~GPIO_InitStruct->GPIO_Pin))
+                                    | GPIO_InitStruct->GPIO_Pin;
+            }
+            /* Configure Debounce enable register */
+            if (GPIO_InitStruct->GPIO_ITDebounce == GPIO_INT_DEBOUNCE_DISABLE)
+            {
+                GPIO->DEBOUNCE = GPIO->DEBOUNCE & (~GPIO_InitStruct->GPIO_Pin);
+            }
+            else
+            {
+                GPIO->DEBOUNCE = (GPIO->DEBOUNCE & (~GPIO_InitStruct->GPIO_Pin))
+                                 | GPIO_InitStruct->GPIO_Pin;
+
+#ifdef _IS_ASIC_
+                /* Config debounce time , default debounce DIV is 14*/
+                GPIO_DBCLK_DIV = (((0xd) << 8) | (1 << 12));
+                GPIO_DBCLK_DIV |= ((((GPIO_InitStruct->GPIO_DebounceTime) * (GPIO_CLOCK_SOURCE_KHZ) >>
+                                     (14)) - 1) & 0xff);
+#else
+                /* Config debounce time , default debounce DIV is 13*/
+                GPIO_DBCLK_DIV = (((0x3) << 10) | (1 << 12));
+                GPIO_DBCLK_DIV |= ((((GPIO_InitStruct->GPIO_DebounceTime) * (GPIO_CLOCK_SOURCE_KHZ) >>
+                                     (13)) - 1) & 0xff);
+#endif
+            }
+
+            /* Configure Interrupt enable register */
+            //GPIO->INTEN |= GPIO_InitStruct->GPIO_Pin;
+        }
+    }
+}
+
+/**
+  * @brief    Fills each GPIO_InitStruct member with its default value.
+  * @param  GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure which will
+  *    be initialized.
+  * @retval None
+  */
+void GPIO_StructInit(GPIO_InitTypeDef *GPIO_InitStruct)
+{
+    /* Reset GPIO init structure parameters values */
+    GPIO_InitStruct->GPIO_Pin  = GPIO_Pin_All;
+    GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN;
+    GPIO_InitStruct->GPIO_ITCmd = DISABLE;
+    GPIO_InitStruct->GPIO_ITTrigger = GPIO_INT_Trigger_LEVEL;
+    GPIO_InitStruct->GPIO_ITPolarity = GPIO_INT_POLARITY_ACTIVE_LOW;
+    GPIO_InitStruct->GPIO_ITDebounce = GPIO_INT_DEBOUNCE_DISABLE;
+    GPIO_InitStruct->GPIO_ControlMode = GPIO_SOFTWARE_MODE;
+    GPIO_InitStruct->GPIO_DebounceTime = 20;                 /* ms , can be 1~64 ms */
+}
+
+/**
+  * @brief enable the specified GPIO interrupt.
+  * @param  GPIO_Pin_x: where x can be 0 or 31.
+  * @retval None
+  */
+void GPIO_INTConfig(uint32_t GPIO_Pin, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_GPIO_PIN(GPIO_Pin));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (NewState != DISABLE)
+    {
+        /* Enable the selected GPIO pin interrupts */
+        GPIO->INTEN |= GPIO_Pin;
+    }
+    else
+    {
+        /* Disable the selected GPIO pin interrupts */
+        GPIO->INTEN &= ~GPIO_Pin;
+    }
+}
+
+/**
+  * @brief clear the specified GPIO interrupt.
+  * @param  GPIO_Pin_x: where x can be 0 or 31.
+  * @retval None
+  */
+void GPIO_ClearINTPendingBit(uint32_t GPIO_Pin)
+{
+    /* Check the parameters */
+    assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+    GPIO->INTCLR = GPIO_Pin;
+}
+
+/**
+  * @brief  mask the specified GPIO interrupt.
+  * @param  GPIO_Pin_x: where x can be 0 or 31.
+  * @retval None
+  */
+void GPIO_MaskINTConfig(uint32_t GPIO_Pin, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_GPIO_PIN(GPIO_Pin));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (NewState != DISABLE)
+    {
+        GPIO->INTMASK |= GPIO_Pin;
+    }
+    else
+    {
+        GPIO->INTMASK &= ~(GPIO_Pin);
+    }
+}
+
+/**
+ * \brief     Get the GPIO_Pin through the given PAD num.
+ * \param[in] Pin_num: Pad num which can be from P0_0 to P5_2, please refer to rtl876x.h "Pin_Number" part.
+ * \return    GPIO_Pin for GPIO initialization.
+ */
+uint32_t GPIO_GetPin(uint8_t Pin_num)
+{
+    /* Check the parameters */
+    assert_param(IS_PIN_NUM(Pin_num));
+
+    if (Pin_num <= P3_6)
+    {
+        return BIT(Pin_num);
+    }
+    else if (Pin_num == P4_0)
+    {
+        return BIT(13);
+    }
+    else if ((Pin_num <= P4_3) && (Pin_num >= P4_1))
+    {
+        return BIT(Pin_num - 4);
+    }
+    else if ((Pin_num <= P5_2) && (Pin_num >= H_0))
+    {
+        return BIT(Pin_num - 26);
+    }
+
+    return 0xFF;
+}
+
+/**
+ * \brief     Get GPIOx(x is 0~31) value through the given pad.
+ * \param[in] Pin_num: Pad num which can be from P0_0 to P5_2, please refer to rtl876x.h "Pin_Number" part.
+ * \return    GPIOx(x is 0~31) value.
+ */
+uint8_t GPIO_GetNum(uint8_t Pin_num)
+{
+    /* Check the parameters */
+    assert_param(IS_PIN_NUM(Pin_num));
+
+    if (Pin_num <= P3_6)
+    {
+        return (Pin_num);
+    }
+    else if (Pin_num == P4_0)
+    {
+        return 13;
+    }
+    else if ((Pin_num <= P4_3) && (Pin_num >= P4_1))
+    {
+        return (Pin_num - 4);
+    }
+    else if ((Pin_num <= P5_2) && (Pin_num >= H_0))
+    {
+        return (Pin_num - 26);
+    }
+
+    return 0xFF;
+}
+
+/**
+ * \brief   Enable GPIO debounce clock.
+ * \param[in] NewState: Disable or enable debounce clock.
+ * \return  None.
+ */
+void GPIO_DBClkCmd(FunctionalState NewState)
+{
+    if (NewState != DISABLE)
+    {
+        GPIO_DBCLK_DIV |= BIT12;
+    }
+    else
+    {
+        GPIO_DBCLK_DIV &= ~BIT12;
+    }
+}
+
+/**
+  * \brief  Store GPIO register values when system enter DLPS.
+  * \param  PeriReg: Specifies to select the GPIO peripheral.
+  * \param  StoreBuf: Store buffer to store GPIO register data.
+  * \return None.
+  */
+DATA_RAM_FUNCTION
+void GPIO_DLPSEnter(void *PeriReg, void *StoreBuf)
+{
+    GPIO_TypeDef *GPIOx = (GPIO_TypeDef *)PeriReg;
+    GPIOStoreReg_TypeDef *store_buf = (GPIOStoreReg_TypeDef *)StoreBuf;
+
+    RCC_PeriphClockCmd(APBPeriph_GPIO, APBPeriph_GPIO_CLOCK, ENABLE);
+
+    store_buf->gpio_reg[GPIO_DLPS_DR] = GPIOx->DATAOUT;
+    store_buf->gpio_reg[GPIO_DLPS_DDR] = GPIOx->DATADIR;
+    store_buf->gpio_reg[GPIO_DLPS_DSR] = GPIOx->DATASRC;
+    store_buf->gpio_reg[GPIO_DLPS_INTEN] = GPIOx->INTEN;
+    store_buf->gpio_reg[GPIO_DLPS_MASK] = GPIOx->INTMASK;
+    store_buf->gpio_reg[GPIO_DLPS_LEVEL] = GPIOx->INTTYPE;
+    store_buf->gpio_reg[GPIO_DLPS_POLARITY] = GPIOx->INTPOLARITY;
+    store_buf->gpio_reg[GPIO_DLPS_DEBEN] = GPIOx->DEBOUNCE;
+    store_buf->gpio_reg[GPIO_DLPS_DEBCFG] = *(__IO uint32_t *)(0x40000344UL);
+    store_buf->gpio_reg[GPIO_DLPS_BOTHEDGE] = GPIOx->INTBOTHEDGE;
+
+    return;
+}
+
+/**
+  * \brief  Restore GPIO register values when system exit DLPS.
+  * \param  PeriReg: Specifies to select the GPIO peripheral.
+  * \param  StoreBuf: Restore buffer to restore GPIO register data.
+  * \return None
+  */
+DATA_RAM_FUNCTION
+void GPIO_DLPSExit(void *PeriReg, void *StoreBuf)
+{
+    GPIO_TypeDef *GPIOx = (GPIO_TypeDef *)PeriReg;
+    GPIOStoreReg_TypeDef *store_buf = (GPIOStoreReg_TypeDef *)StoreBuf;
+
+    RCC_PeriphClockCmd(APBPeriph_GPIO, APBPeriph_GPIO_CLOCK, ENABLE);
+
+    GPIOx->DATADIR       = store_buf->gpio_reg[GPIO_DLPS_DDR];
+    GPIOx->DATASRC       = store_buf->gpio_reg[GPIO_DLPS_DSR];
+    GPIOx->INTMASK       = store_buf->gpio_reg[GPIO_DLPS_MASK];
+    GPIOx->INTTYPE       = store_buf->gpio_reg[GPIO_DLPS_LEVEL];
+    GPIOx->INTPOLARITY   = store_buf->gpio_reg[GPIO_DLPS_POLARITY];
+    GPIOx->DEBOUNCE      = store_buf->gpio_reg[GPIO_DLPS_DEBEN];
+    GPIOx->DATAOUT       = store_buf->gpio_reg[GPIO_DLPS_DR];
+    GPIOx->INTCLR        = ~(store_buf->gpio_reg[GPIO_DLPS_DDR]);
+    GPIOx->INTEN         = store_buf->gpio_reg[GPIO_DLPS_INTEN];
+    *(__IO uint32_t *)(0x40000344UL) = store_buf->gpio_reg[GPIO_DLPS_DEBCFG];
+    GPIOx->INTBOTHEDGE  = store_buf->gpio_reg[GPIO_DLPS_BOTHEDGE];
+
+    return;
+}
+
+
+
diff --git a/bee/drivers/gpio/src/device/rtl8752h/rtl876x_gpio.h b/bee/drivers/gpio/src/device/rtl8752h/rtl876x_gpio.h
new file mode 100644
index 00000000..650d421b
--- /dev/null
+++ b/bee/drivers/gpio/src/device/rtl8752h/rtl876x_gpio.h
@@ -0,0 +1,853 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _RTL876X_GPIO_H_
+#define _RTL876X_GPIO_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup  IO          Peripheral Drivers
+ * \defgroup    GPIO        GPIO
+ *
+ * \brief       Manage the GPIO peripheral functions.
+ *
+ * \ingroup     IO
+ */
+/*============================================================================*
+ *                         Includes
+ *============================================================================*/
+#include "rtl876x.h"
+
+/**
+ * \cond        private
+ * \defgroup    GPIO_Debounce_Register GPIO Debounce Register
+ * \{
+ */
+
+/**
+ * \brief GPIO Private Defines
+ */
+#define GPIO_DBCLK_DIV *((volatile uint32_t *)0x40000344UL)
+
+/**
+ * \}
+ * \endcond
+ */
+
+/*============================================================================*
+ *                         Constants
+ *============================================================================*/
+/**
+ * \defgroup    GPIO_Exported_Constants     GPIO Exported Constants
+ *
+ * \ingroup     GPIO
+ */
+
+/**
+ * \defgroup    GPIO_Number GPIO Number
+ * \{
+ * \ingroup     GPIO_Exported_Constants
+ */
+#define GPIO0   0
+#define GPIO1   1
+#define GPIO2   2
+#define GPIO3   3
+#define GPIO4   4
+#define GPIO5   5
+#define GPIO6   6
+#define GPIO7   7
+#define GPIO8   8
+#define GPIO9   9
+#define GPIO10  10
+#define GPIO11  11
+#define GPIO12  12
+#define GPIO13  13
+#define GPIO14  14
+#define GPIO15  15
+#define GPIO16  16
+#define GPIO17  17
+#define GPIO18  18
+#define GPIO19  19
+#define GPIO20  20
+#define GPIO21  21
+#define GPIO22  22
+#define GPIO23  23
+#define GPIO24  24
+#define GPIO25  25
+#define GPIO26  26
+#define GPIO27  27
+#define GPIO28  28
+#define GPIO29  29
+#define GPIO30  30
+#define GPIO31  31
+/** \} */
+
+/**
+ * \defgroup    GPIO_Pins_Define GPIO Pins Define
+ * \{
+ * \ingroup     GPIO_Exported_Constants
+ */
+#define GPIO_Pin_0                 ((uint32_t)0x00000001)  /*!< Pin 0 selected   */
+#define GPIO_Pin_1                 ((uint32_t)0x00000002)  /*!< Pin 1 selected   */
+#define GPIO_Pin_2                 ((uint32_t)0x00000004)  /*!< Pin 2 selected   */
+#define GPIO_Pin_3                 ((uint32_t)0x00000008)  /*!< Pin 3 selected   */
+#define GPIO_Pin_4                 ((uint32_t)0x00000010)  /*!< Pin 4 selected   */
+#define GPIO_Pin_5                 ((uint32_t)0x00000020)  /*!< Pin 5 selected   */
+#define GPIO_Pin_6                 ((uint32_t)0x00000040)  /*!< Pin 6 selected   */
+#define GPIO_Pin_7                 ((uint32_t)0x00000080)  /*!< Pin 7 selected   */
+#define GPIO_Pin_8                 ((uint32_t)0x00000100)  /*!< Pin 8 selected   */
+#define GPIO_Pin_9                 ((uint32_t)0x00000200)  /*!< Pin 9 selected   */
+#define GPIO_Pin_10                ((uint32_t)0x00000400)  /*!< Pin 10 selected  */
+#define GPIO_Pin_11                ((uint32_t)0x00000800)  /*!< Pin 11 selected  */
+#define GPIO_Pin_12                ((uint32_t)0x00001000)  /*!< Pin 12 selected  */
+#define GPIO_Pin_13                ((uint32_t)0x00002000)  /*!< Pin 13 selected  */
+#define GPIO_Pin_14                ((uint32_t)0x00004000)  /*!< Pin 14 selected  */
+#define GPIO_Pin_15                ((uint32_t)0x00008000)  /*!< Pin 15 selected  */
+#define GPIO_Pin_16                ((uint32_t)0x00010000)  /*!< Pin 16 selected   */
+#define GPIO_Pin_17                ((uint32_t)0x00020000)  /*!< Pin 17 selected   */
+#define GPIO_Pin_18                ((uint32_t)0x00040000)  /*!< Pin 18 selected   */
+#define GPIO_Pin_19                ((uint32_t)0x00080000)  /*!< Pin 19 selected   */
+#define GPIO_Pin_20                ((uint32_t)0x00100000)  /*!< Pin 20 selected   */
+#define GPIO_Pin_21                ((uint32_t)0x00200000)  /*!< Pin 21 selected   */
+#define GPIO_Pin_22                ((uint32_t)0x00400000)  /*!< Pin 22 selected   */
+#define GPIO_Pin_23                ((uint32_t)0x00800000)  /*!< Pin 23 selected   */
+#define GPIO_Pin_24                ((uint32_t)0x01000000)  /*!< Pin 24 selected   */
+#define GPIO_Pin_25                ((uint32_t)0x02000000)  /*!< Pin 25 selected   */
+#define GPIO_Pin_26                ((uint32_t)0x04000000)  /*!< Pin 26 selected  */
+#define GPIO_Pin_27                ((uint32_t)0x08000000)  /*!< Pin 27 selected  */
+#define GPIO_Pin_28                ((uint32_t)0x10000000)  /*!< Pin 28 selected  */
+#define GPIO_Pin_29                ((uint32_t)0x20000000)  /*!< Pin 29 selected  */
+#define GPIO_Pin_30                ((uint32_t)0x40000000)  /*!< Pin 30 selected  */
+#define GPIO_Pin_31                ((uint32_t)0x80000000)  /*!< Pin 31 selected  */
+#define GPIO_Pin_All               ((uint32_t)0xFFFFFFFF)  /*!< All pins selected */
+
+#define IS_PIN_NUM(NUM) ((NUM) <= (uint8_t)P4_1)
+
+#define IS_GPIO_PIN(PIN) ((PIN) != (uint32_t)0x00)
+
+#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \
+                              ((PIN) == GPIO_Pin_1) || \
+                              ((PIN) == GPIO_Pin_2) || \
+                              ((PIN) == GPIO_Pin_3) || \
+                              ((PIN) == GPIO_Pin_4) || \
+                              ((PIN) == GPIO_Pin_5) || \
+                              ((PIN) == GPIO_Pin_6) || \
+                              ((PIN) == GPIO_Pin_7) || \
+                              ((PIN) == GPIO_Pin_8) || \
+                              ((PIN) == GPIO_Pin_9) || \
+                              ((PIN) == GPIO_Pin_10) || \
+                              ((PIN) == GPIO_Pin_11) || \
+                              ((PIN) == GPIO_Pin_12) || \
+                              ((PIN) == GPIO_Pin_13) || \
+                              ((PIN) == GPIO_Pin_14) || \
+                              ((PIN) == GPIO_Pin_15) || \
+                              ((PIN) == GPIO_Pin_16) || \
+                              ((PIN) == GPIO_Pin_17) || \
+                              ((PIN) == GPIO_Pin_18) || \
+                              ((PIN) == GPIO_Pin_19) || \
+                              ((PIN) == GPIO_Pin_20) || \
+                              ((PIN) == GPIO_Pin_21) || \
+                              ((PIN) == GPIO_Pin_22) || \
+                              ((PIN) == GPIO_Pin_23) || \
+                              ((PIN) == GPIO_Pin_24) || \
+                              ((PIN) == GPIO_Pin_25) || \
+                              ((PIN) == GPIO_Pin_26) || \
+                              ((PIN) == GPIO_Pin_27) || \
+                              ((PIN) == GPIO_Pin_28) || \
+                              ((PIN) == GPIO_Pin_29) || \
+                              ((PIN) == GPIO_Pin_30) || \
+                              ((PIN) == GPIO_Pin_31))
+/** \} */
+
+/**
+ * \defgroup    GPIO_BitAction GPIO BitAction
+ * \{
+ * \ingroup     GPIO_Exported_Constants
+ */
+typedef enum
+{
+    Bit_RESET = 0,
+    Bit_SET
+} BitAction;
+
+#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET))
+/** \} */
+
+/**
+ * \defgroup    GPIO_Mode GPIO Mode
+ * \{
+ * \ingroup     GPIO_Exported_Constants
+ */
+typedef enum
+{
+    GPIO_Mode_IN   = 0x00, /**< GPIO Input Mode */
+    GPIO_Mode_OUT  = 0x01, /**< GPIO Output Mode */
+} GPIOMode_TypeDef;
+
+#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_IN)|| ((MODE) == GPIO_Mode_OUT))
+/** \} */
+
+/**
+ * \defgroup    GPIO_INT_Trigger_Level GPIO INT Trigger Level
+ * \{
+ * \ingroup     GPIO_Exported_Constants
+ */
+typedef enum
+{
+    GPIO_INT_Trigger_LEVEL = 0x0, /**< This interrupt is level trigger. */
+    GPIO_INT_Trigger_EDGE  = 0x1, /**< This interrupt is edge trigger. */
+    GPIO_INT_BOTH_EDGE = 0x2,     /**< This interrupt is both edge trigger. */
+} GPIOIT_LevelType;
+
+#define IS_GPIOIT_LEVEL_TYPE(TYPE) (((TYPE) == GPIO_INT_Trigger_LEVEL)\
+                                    || ((TYPE) == GPIO_INT_Trigger_EDGE)\
+                                    || ((TYPE) == GPIO_INT_BOTH_EDGE))
+/** \} */
+
+/**
+ * \defgroup    GPIO_INT_Polarity GPIO INT Polarity
+ * \{
+ * \ingroup     GPIO_Exported_Constants
+ */
+typedef enum
+{
+    GPIO_INT_POLARITY_ACTIVE_LOW  = 0x0, /**< Setting interrupt to low active. */
+    GPIO_INT_POLARITY_ACTIVE_HIGH = 0x1, /**< Setting interrupt to high active. */
+} GPIOIT_PolarityType;
+
+#define IS_GPIOIT_POLARITY_TYPE(TYPE) (((TYPE) == GPIO_INT_POLARITY_ACTIVE_LOW)\
+                                       || ((TYPE) == GPIO_INT_POLARITY_ACTIVE_HIGH))
+/** \} */
+
+/**
+ * \defgroup    GPIO_INT_Debounce GPIO INT Debounce
+ * \{
+ * \ingroup     GPIO_Exported_Constants
+ */
+typedef enum
+{
+    GPIO_INT_DEBOUNCE_DISABLE = 0x0, /**< Disable interrupt debounce. */
+    GPIO_INT_DEBOUNCE_ENABLE  = 0x1, /**< Enable interrupt debounce.  */
+} GPIOIT_DebounceType;
+
+#define IS_GPIOIT_DEBOUNCE_TYPE(TYPE) (((TYPE) == GPIO_INT_DEBOUNCE_DISABLE)\
+                                       || ((TYPE) == GPIO_INT_DEBOUNCE_ENABLE))
+/** \} */
+
+/**
+ * \defgroup    GPIO_Control_Mode GPIO Control Mode
+ * \{
+ * \ingroup     GPIO_Exported_Constants
+ */
+typedef enum
+{
+    GPIO_SOFTWARE_MODE = 0x0, /**< GPIO software mode (default). */
+    GPIO_HARDWARE_MODE  = 0x1, /**< GPIO hardware control mode. */
+} GPIOControlMode_Typedef;
+
+#define IS_GPIOIT_MODE(TYPE) (((TYPE) == GPIO_SOFTWARE_MODE)\
+                              || ((TYPE) == GPIO_HARDWARE_MODE))
+/** \} */
+
+/** End of GPIO_Exported_Constants
+  * \}
+  */
+
+/*============================================================================*
+ *                         Types
+ *============================================================================*/
+/**
+ * \defgroup    GPIO_Exported_Types GPIO Exported Types
+ * \{
+ * \ingroup     GPIO
+ */
+
+/**
+ * \brief       GPIO init structure definition.
+ *
+ * \ingroup     GPIO_Exported_Types
+ */
+typedef struct
+{
+    uint32_t                  GPIO_Pin;         /**< Specify the GPIO pins to be configured.
+                                                     This parameter can be any value of \ref GPIO_Pins_Define */
+    GPIOMode_TypeDef
+    GPIO_Mode;                                  /**< Specify the operating mode for the selected pins. */
+    FunctionalState           GPIO_ITCmd;       /**< Enable or disable GPIO interrupt.
+                                                     This parameter can be a value of DISABLE or ENABLE. */
+    GPIOIT_LevelType          GPIO_ITTrigger;   /**< Interrupt mode is level or edge trigger. */
+    GPIOIT_PolarityType       GPIO_ITPolarity;  /**< Interrupt mode is high or low active trigger. */
+    GPIOIT_DebounceType       GPIO_ITDebounce;  /**< Enable or disable de-bounce for interrupt. */
+    GPIOControlMode_Typedef   GPIO_ControlMode; /**< Specify the gpio control mode. */
+    uint32_t GPIO_DebounceTime;                 /**< Specify the gpio debounce time (ms). */
+} GPIO_InitTypeDef;
+
+/** End of GPIO_Exported_Types
+  * \}
+  */
+
+/*============================================================================*
+ *                         Functions
+ *============================================================================*/
+/**
+ * \defgroup   GPIO_Exported_Functions GPIO Exported Functions
+ * \{
+ * \ingroup    GPIO
+ */
+
+/**
+ * \brief   Deinitialize the GPIO peripheral registers to their default reset values.
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_gpio_init(void)
+ * {
+ *     GPIO_DeInit();
+ * }
+ * \endcode
+ */
+void GPIO_DeInit(void);
+
+/**
+ * \brief  Initialize the GPIO peripheral according to the specified
+ *         parameters in the GPIO_InitStruct.
+ * \param[in] GPIO_InitStruct: Pointer to a GPIO_InitTypeDef structure that
+ *            contains the configuration information for the specified GPIO peripheral.
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_gpio_init(void)
+ * {
+ *     RCC_PeriphClockCmd(APBPeriph_GPIO, APBPeriph_GPIO_CLOCK, ENABLE);
+ *
+ *     GPIO_InitTypeDef GPIO_InitStruct;
+ *     GPIO_StructInit(&GPIO_InitStruct);
+ *     GPIO_InitStruct.GPIO_Pin        = GPIO_GetPin(P4_0);
+ *     GPIO_InitStruct.GPIO_Mode       = GPIO_Mode_IN;
+ *     GPIO_InitStruct.GPIO_ITCmd      = ENABLE;
+ *     GPIO_InitStruct.GPIO_ITTrigger  = GPIO_INT_Trigger_EDGE;
+ *     GPIO_InitStruct.GPIO_ITPolarity = GPIO_INT_POLARITY_ACTIVE_LOW;
+ *     GPIO_InitStruct.GPIO_ITDebounce = GPIO_INT_DEBOUNCE_ENABLE;
+ *     GPIO_InitStruct.GPIO_DebounceTime = 10;
+ *     GPIO_Init(&GPIO_InitStruct);
+ *
+ *     NVIC_InitTypeDef NVIC_InitStruct;
+ *     NVIC_InitStruct.NVIC_IRQChannel = GPIO28_IRQn;
+ *     NVIC_InitStruct.NVIC_IRQChannelPriority = 3;
+ *     NVIC_InitStruct.NVIC_IRQChannelCmd = ENABLE;
+ *     NVIC_Init(&NVIC_InitStruct);
+
+ *     GPIO_MaskINTConfig(GPIO_PIN_INPUT, DISABLE);
+ *     GPIO_INTConfig(GPIO_PIN_INPUT, ENABLE);
+ * }
+ * \endcode
+ */
+void GPIO_Init(GPIO_InitTypeDef *GPIO_InitStruct);
+
+/**
+ * \brief    Fill each GPIO_InitStruct member with its default value.
+ * \param[in]  GPIO_InitStruct: Pointer to a GPIO_InitTypeDef structure which will
+ *             be initialized.
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_gpio_init(void)
+ * {
+ *     RCC_PeriphClockCmd(APBPeriph_GPIO, APBPeriph_GPIO_CLOCK, ENABLE);
+ *
+ *     GPIO_InitTypeDef GPIO_InitStruct;
+ *     GPIO_StructInit(&GPIO_InitStruct);
+ *     GPIO_InitStruct.GPIO_Pin        = GPIO_GetPin(P4_0);
+ *     GPIO_InitStruct.GPIO_Mode       = GPIO_Mode_IN;
+ *     GPIO_InitStruct.GPIO_ITCmd      = ENABLE;
+ *     GPIO_InitStruct.GPIO_ITTrigger  = GPIO_INT_Trigger_EDGE;
+ *     GPIO_InitStruct.GPIO_ITPolarity = GPIO_INT_POLARITY_ACTIVE_LOW;
+ *     GPIO_InitStruct.GPIO_ITDebounce = GPIO_INT_DEBOUNCE_ENABLE;
+ *     GPIO_InitStruct.GPIO_DebounceTime = 10;
+ *     GPIO_Init(&GPIO_InitStruct);
+ * }
+ * \endcode
+ */
+void GPIO_StructInit(GPIO_InitTypeDef *GPIO_InitStruct);
+
+/**
+ * \brief   Enable or disable the specified GPIO pin interrupt.
+ * \param[in]  GPIO_Pin: GPIO selected pin GPIO_Pin_x, where x can be 0 or 31,
+ *                       refer to \ref GPIO_Pins_Define.
+ * \param[in]  NewState: Enable or disable interrupt.
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_gpio_init(void)
+ * {
+ *     RCC_PeriphClockCmd(APBPeriph_GPIO, APBPeriph_GPIO_CLOCK, ENABLE);
+ *
+ *     GPIO_InitTypeDef GPIO_InitStruct;
+ *     GPIO_StructInit(&GPIO_InitStruct);
+ *     GPIO_InitStruct.GPIO_Pin        = GPIO_GetPin(P4_0);
+ *     GPIO_InitStruct.GPIO_Mode       = GPIO_Mode_IN;
+ *     GPIO_InitStruct.GPIO_ITCmd      = ENABLE;
+ *     GPIO_InitStruct.GPIO_ITTrigger  = GPIO_INT_Trigger_EDGE;
+ *     GPIO_InitStruct.GPIO_ITPolarity = GPIO_INT_POLARITY_ACTIVE_LOW;
+ *     GPIO_InitStruct.GPIO_ITDebounce = GPIO_INT_DEBOUNCE_ENABLE;
+ *     GPIO_InitStruct.GPIO_DebounceTime = 10;
+ *     GPIO_Init(&GPIO_InitStruct);
+ *
+ *     NVIC_InitTypeDef NVIC_InitStruct;
+ *     NVIC_InitStruct.NVIC_IRQChannel = GPIO28_IRQn;
+ *     NVIC_InitStruct.NVIC_IRQChannelPriority = 3;
+ *     NVIC_InitStruct.NVIC_IRQChannelCmd = ENABLE;
+ *     NVIC_Init(&NVIC_InitStruct);
+
+ *     GPIO_MaskINTConfig(GPIO_PIN_INPUT, DISABLE);
+ *     GPIO_INTConfig(GPIO_PIN_INPUT, ENABLE);
+ * }
+ * \endcode
+ */
+void GPIO_INTConfig(uint32_t GPIO_Pin, FunctionalState NewState);
+
+/**
+ * \brief   Clear the specified GPIO pin interrupt pending bit.
+ * \param[in] GPIO_Pin: GPIO selected pin GPIO_Pin_x, where x can be 0 or 31,
+ *                       refer to \ref GPIO_Pins_Define.
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void gpio_demo(void)
+ * {
+ *     driver_gpio_init();
+ * }
+ *
+ * void GPIO28_Handler(void)
+ * {
+ *     GPIO_INTConfig(GPIO_PIN_INPUT, DISABLE);
+ *     GPIO_MaskINTConfig(GPIO_PIN_INPUT, ENABLE);
+ *     //Add user code here.
+ *     GPIO_ClearINTPendingBit(GPIO_PIN_INPUT);
+ *     GPIO_MaskINTConfig(GPIO_PIN_INPUT, DISABLE);
+ *     GPIO_INTConfig(GPIO_PIN_INPUT, ENABLE);
+}
+ * \endcode
+ */
+void GPIO_ClearINTPendingBit(uint32_t GPIO_Pin);
+
+/**
+ * \brief   Mask the specified GPIO pin interrupt.
+ * \param[in] GPIO_Pin: GPIO selected pin GPIO_Pin_x, where x can be 0 or 31,
+ *                       refer to \ref GPIO_Pins_Define.
+ * \param[in] NewState: Disable or enable interrupt.
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ *
+ * void gpio_demo(void)
+ * {
+ *     driver_gpio_init();
+ * }
+ *
+ * void GPIO28_Handler(void)
+ * {
+ *     GPIO_INTConfig(GPIO_PIN_INPUT, DISABLE);
+ *     GPIO_MaskINTConfig(GPIO_PIN_INPUT, ENABLE);
+ *
+ *     //Add user code here.
+ *
+ *     GPIO_ClearINTPendingBit(GPIO_PIN_INPUT);
+ *     GPIO_MaskINTConfig(GPIO_PIN_INPUT, DISABLE);
+ *     GPIO_INTConfig(GPIO_PIN_INPUT, ENABLE);
+ * }
+ * \endcode
+ */
+void GPIO_MaskINTConfig(uint32_t GPIO_Pin, FunctionalState NewState);
+
+/**
+ * \brief   Get the GPIO_Pin through the given PAD num.
+ * \param[in]  Pin_num: Pad num which can be from P0_0 to H_2, please refer to rtl876x.h "Pin_Number" part.
+ * \return  GPIO_Pin_x for GPIO initialization, where x can be 0 or 31, refer to \ref GPIO_Pins_Define.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_gpio_init(void)
+ * {
+ *     uint32_t gpio_pin = GPIO_GetPin(P4_0);
+ *     //result: gpio_pin = GPIO_Pin_28
+ * }
+ * \endcode
+ */
+uint32_t GPIO_GetPin(uint8_t Pin_num);
+
+/**
+ * \brief   Get GPIOx(x is 0~31) value through the given pad.
+ * \param[in] Pin_num: Pad num which can be from P0_0 to H_2, please refer to rtl876x.h "Pin_Number" part.
+ * \return  GPIOx(x is 0~31) value, which refer to \ref GPIO_Number.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void gpio_demo(void)
+ * {
+ *     uint8_t gpio_num = GPIO_GetNum(P4_0);
+ *     //result: gpio_num = 28
+ * }
+ * \endcode
+ */
+uint8_t GPIO_GetNum(uint8_t Pin_num);
+
+/**
+ * \brief   Enable GPIO debounce clock.
+ * \param[in] NewState: New state of the debounce clock.
+ *     This parameter can be: ENABLE or DISABLE.
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void gpio_demo(void)
+ * {
+ *     GPIO_DBClkCmd(ENABLE);
+ * }
+ * \endcode
+ */
+void GPIO_DBClkCmd(FunctionalState NewState);
+
+/**
+ * \brief   Read the specified input port pin.
+ * \param[in] GPIO_Pin: Specify the port bit to read.
+ *      This parameter can be GPIO_Pin_x where x can be 0~31, refer to \ref GPIO_Pins_Define.
+ * \return  The input port pin value.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void gpio_demo(void)
+ * {
+ *     uint8_t input_bit = GPIO_ReadInputDataBit(GPIO_GetPin(P4_0));
+ * }
+ * \endcode
+ */
+__STATIC_INLINE uint8_t GPIO_ReadInputDataBit(uint32_t GPIO_Pin)
+{
+    uint8_t bitstatus = RESET;
+
+    (void)GPIO->DATAIN;
+
+    /* Check the parameters */
+    assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+    if (GPIO->DATAIN & GPIO_Pin)
+    {
+        bitstatus = (uint8_t)SET;
+    }
+
+    return bitstatus;
+}
+
+/**
+ * \brief  Read value of all GPIO input data port.
+ * \return GPIO input data port value.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void gpio_demo(void)
+ * {
+ *     uint32_t input_data = GPIO_ReadInputData();
+ * }
+ * \endcode
+ */
+__STATIC_INLINE uint32_t GPIO_ReadInputData(void)
+{
+    uint32_t data_in = GPIO->DATAIN;
+    data_in = GPIO->DATAIN;
+
+    return data_in;
+}
+
+/**
+ * \brief   Read the specified output port pin.
+ * \param[in] GPIO_Pin: Specify the port bit to read.
+ *      This parameter can be GPIO_Pin_x where x can be 0~31, refer to \ref GPIO_Pins_Define.
+ * \return The output port pin value.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void gpio_demo(void)
+ * {
+ *     uint8_t output_bit = GPIO_ReadOutputDataBit(GPIO_GetPin(P4_0));
+ * }
+ * \endcode
+ */
+__STATIC_INLINE uint8_t GPIO_ReadOutputDataBit(uint32_t GPIO_Pin)
+{
+    uint8_t bitstatus = RESET;
+
+    /* Check the parameters */
+    assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+    if (GPIO->DATAOUT & GPIO_Pin)
+    {
+        bitstatus = (uint8_t)SET;
+    }
+
+    return bitstatus;
+}
+
+/**
+ * \brief   Read value of all GPIO output data port.
+ * \return  GPIO output data port value.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void gpio_demo(void)
+ * {
+ *     uint32_t output_data = GPIO_ReadOutputData();
+ * }
+ * \endcode
+ */
+__STATIC_INLINE uint32_t GPIO_ReadOutputData(void)
+{
+    return ((uint32_t)GPIO->DATAOUT);
+}
+
+/**
+ * \brief   Set the selected data port bit.
+ * \param[in] GPIO_Pin: Specify the port bit to be written.
+ *      This parameter can be GPIO_Pin_x where x can be 0~31 or GPIO_Pin_All, refer to \ref GPIO_Pins_Define.
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void gpio_demo(void)
+ * {
+ *     GPIO_SetBits(GPIO_GetPin(P4_0));
+ * }
+ * \endcode
+ */
+__STATIC_INLINE void GPIO_SetBits(uint32_t GPIO_Pin)
+{
+    /* Check the parameters */
+    assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+    GPIO->DATAOUT |= GPIO_Pin;
+}
+
+/**
+ * \brief   Reset the selected data port bit.
+ * \param[in] GPIO_Pin: Specify the port bits to be written.
+ *      This parameter can be GPIO_Pin_x where x can be 0~31 or GPIO_Pin_All, refer to \ref GPIO_Pins_Define.
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void gpio_demo(void)
+ * {
+ *     GPIO_ResetBits(GPIO_GetPin(P4_0));
+ * }
+ * \endcode
+ */
+__STATIC_INLINE void GPIO_ResetBits(uint32_t GPIO_Pin)
+{
+    /* Check the parameters */
+    assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+    GPIO->DATAOUT &= ~(GPIO_Pin);
+}
+
+/**
+ * \brief  Set or clear the selected data port bit.
+ * \param[in] GPIO_Pin: Specify the port bit to be written.
+ *      This parameter can be one of GPIO_Pin_x where x can be 0~31, refer to \ref GPIO_Pins_Define.
+ * \param[in] BitVal: Specify the value to be written to the selected bit.
+ *      This parameter can be one of the BitAction enum values, which refer to \ref GPIO_BitAction.
+ *     \arg Bit_RESET: To clear the port pin.
+ *     \arg Bit_SET: To set the port pin.
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void gpio_demo(void)
+ * {
+ *     GPIO_WriteBit(GPIO_GetPin(P4_0), Bit_SET);
+ * }
+ * \endcode
+ */
+__STATIC_INLINE void GPIO_WriteBit(uint32_t GPIO_Pin, BitAction BitVal)
+{
+    /* Check the parameters */
+    assert_param(IS_GPIO_PIN(GPIO_Pin));
+    assert_param(IS_GPIO_BIT_ACTION(BitVal));
+
+    if (BitVal != Bit_RESET)
+    {
+        GPIO->DATAOUT |= GPIO_Pin;
+    }
+    else
+    {
+        GPIO->DATAOUT &= ~(GPIO_Pin);
+    }
+}
+
+/**
+ * \brief   Set or clear data port.
+ * \param[in] PortVal: Specify the value to be written to the selected bit.
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void gpio_demo(void)
+ * {
+ *     GPIO_Write(0xFFFFFFFF);
+ * }
+ * \endcode
+ */
+__STATIC_INLINE void GPIO_Write(uint32_t PortVal)
+{
+    GPIO->DATAOUT = PortVal;
+}
+
+/**
+ * \brief  Get GPIO interrupt status.
+ * \param[in] GPIO_Pin: Specify the port bit to be written.
+ *      This parameter can be one of GPIO_Pin_x where x can be 0~31, refer to \ref GPIO_Pins_Define.
+ * \return The new state of GPIO_IT (SET or RESET).
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void gpio_demo(void)
+ * {
+ *     ITStatus int_status = GPIO_GetINTStatus(GPIO_GetPin(P4_0));
+ * }
+ * \endcode
+ */
+__STATIC_INLINE ITStatus GPIO_GetINTStatus(uint32_t GPIO_Pin)
+{
+    /* Check the parameters */
+    assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+    if ((GPIO->INTSTATUS & GPIO_Pin) == GPIO_Pin)
+    {
+        return SET;
+    }
+    else
+    {
+        return RESET;
+    }
+}
+
+/**
+ * \brief  Set debounce time.
+ * \param[in] DebounceTime: Specify interrupt debounce time, the unit is ms.
+ *      This parameter can be 1 ~ 64.
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void gpio_demo(void)
+ * {
+ *     GPIO_Debounce_Time(10);
+ * }
+ * \endcode
+ */
+__STATIC_INLINE void GPIO_Debounce_Time(uint32_t DebounceTime)
+{
+    uint8_t count = 0;
+
+    if (DebounceTime < 1)
+    {
+        DebounceTime = 1;
+    }
+    if (DebounceTime > 64)
+    {
+        DebounceTime = 64;
+    }
+#ifdef _IS_ASIC_
+    //div = 14;//0xd  0b1101<<8
+    GPIO_DBCLK_DIV = ((0xd << 8) | (1 << 12));
+#else
+    //div = 13;//0xc  0b1100<<8
+    GPIO_DBCLK_DIV |= ((1 << 11) | (1 << 10) | (1 << 12));
+    GPIO_DBCLK_DIV &= (~((1 << 9) | (1 << 8)));
+#endif
+    count = (244 * DebounceTime) / 100 - 1;
+    GPIO_DBCLK_DIV &= (~((0xff << 0)));
+    GPIO_DBCLK_DIV = GPIO_DBCLK_DIV + count;
+}
+
+__STATIC_INLINE void GPIO_SetPolarity(uint32_t GPIO_Pin,
+                                      GPIOIT_PolarityType int_type)
+{
+    /* Check the parameters */
+    assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+    /* configure Interrupt polarity register */
+    if (int_type == GPIO_INT_POLARITY_ACTIVE_LOW)
+    {
+        GPIO->INTPOLARITY = GPIO->INTPOLARITY & (~GPIO_Pin);
+    }
+    else
+    {
+        GPIO->INTPOLARITY = (GPIO->INTPOLARITY & (~GPIO_Pin))
+                            | GPIO_Pin;
+    }
+}
+
+/** End of GPIO_Exported_Functions
+  * \}
+  */
+
+/** End of GPIO
+  * \}
+  */
+
+typedef enum
+{
+    GPIO_DLPS_DR   = 0x00,
+    GPIO_DLPS_DDR   = 0x01,
+    GPIO_DLPS_DSR   = 0x02,
+    GPIO_DLPS_INTEN   = 0x03,
+    GPIO_DLPS_MASK   = 0x04,
+    GPIO_DLPS_LEVEL   = 0x05,
+    GPIO_DLPS_POLARITY   = 0x06,
+    GPIO_DLPS_DEBEN   = 0x07,
+    GPIO_DLPS_DEBCFG   = 0x08,
+    GPIO_DLPS_BOTHEDGE   = 0x09,
+    GPIO_DLPS_MAX = 0xA0,
+} GPIODLPSREG_TypeDef;
+
+typedef struct
+{
+    uint32_t gpio_reg[GPIO_DLPS_MAX];
+} GPIOStoreReg_TypeDef;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTL876X_GPIO_H_ */
diff --git a/bee/drivers/gpio/src/device/rtl87x2g/rtl87x2g_gpio.c b/bee/drivers/gpio/src/device/rtl87x2g/rtl87x2g_gpio.c
new file mode 100644
index 00000000..06501c70
--- /dev/null
+++ b/bee/drivers/gpio/src/device/rtl87x2g/rtl87x2g_gpio.c
@@ -0,0 +1,301 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *                        Header Files
+ *============================================================================*/
+#include "rtl_gpio.h"
+#include "rtl_rcc.h"
+#include "app_section.h"
+
+/*============================================================================*
+ *                        Private Defines
+ *============================================================================*/
+#define IS_PIN_NUM(NUM) ((NUM) <= (uint8_t)P10_2)
+
+/*============================================================================*
+ *                           Public Functions
+ *============================================================================*/
+uint32_t GPIO_SwapDebPinBit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
+{
+    uint32_t temp_gpio_bit = GPIO_Pin;
+
+    if (GPIOx == GPIOA)
+    {
+        /* BIT12 <-> BIT27  BIT20 <-> BIT31 */
+        temp_gpio_bit &= ~BIT12;
+        temp_gpio_bit |= ((GPIO_Pin & BIT27) >> 27) << 12;
+
+        temp_gpio_bit &= ~BIT27;
+        temp_gpio_bit |= ((GPIO_Pin & BIT12) >> 12) << 27;
+
+        temp_gpio_bit &= ~BIT20;
+        temp_gpio_bit |= ((GPIO_Pin & BIT31) >> 31) << 20;
+
+        temp_gpio_bit &= ~BIT31;
+        temp_gpio_bit |= ((GPIO_Pin & BIT20) >> 20) << 31;
+    }
+    else
+    {
+        /* BIT1 <-> BIT8  BIT2 <-> BIT12  BIT3 <-> BIT16 */
+        temp_gpio_bit &= ~BIT1;
+        temp_gpio_bit |= ((GPIO_Pin & BIT8) >> 8) << 1;
+
+        temp_gpio_bit &= ~BIT8;
+        temp_gpio_bit |= ((GPIO_Pin & BIT1) >> 1) << 8;
+
+        temp_gpio_bit &= ~BIT2;
+        temp_gpio_bit |= ((GPIO_Pin & BIT12) >> 12) << 2;
+
+        temp_gpio_bit &= ~BIT12;
+        temp_gpio_bit |= ((GPIO_Pin & BIT2) >> 2) << 12;
+
+        temp_gpio_bit &= ~BIT3;
+        temp_gpio_bit |= ((GPIO_Pin & BIT16) >> 16) << 3;
+
+        temp_gpio_bit &= ~BIT16;
+        temp_gpio_bit |= ((GPIO_Pin & BIT3) >> 3) << 16;
+    }
+
+    return temp_gpio_bit;
+}
+
+
+GPIO_TypeDef *GPIO_GetPort(uint8_t Pin_num)
+{
+    if (((Pin_num >= P0_0) && (Pin_num <= P3_2)) || ((Pin_num >= MICBIAS) && (Pin_num <= DACN)))
+    {
+        return GPIOA;
+    }
+    else if (((Pin_num >= P3_3) && (Pin_num <= P7_4)) || ((Pin_num >= P9_0) && (Pin_num <= P10_2)))
+    {
+        return GPIOB;
+    }
+    return 0;
+}
+
+
+uint32_t GPIO_GetPinBit(uint8_t Pin_num)
+{
+    /* Check the parameters */
+    assert_param(IS_PIN_NUM(Pin_num));
+
+    if (Pin_num <= P1_7)
+    {
+        return BIT(Pin_num);
+    }
+    else if ((Pin_num >= P2_0) && (Pin_num <= P3_2))
+    {
+        return BIT(Pin_num + 5);
+    }
+    else if ((Pin_num >= P3_3) && (Pin_num <= P5_7))
+    {
+        return BIT(Pin_num - 27);
+    }
+    else if ((Pin_num >= P6_0) && (Pin_num <= P7_4))
+    {
+        return BIT(Pin_num - 29);
+    }
+    else if ((Pin_num >= MICBIAS) && (Pin_num <= DACN))
+    {
+        return BIT(Pin_num - 48);
+    }
+    else if ((Pin_num >= P9_0) && (Pin_num <= P10_2))
+    {
+        return BIT(Pin_num - 51);
+    }
+
+    return 0xFF;
+}
+
+
+uint8_t GPIO_GetNum(uint8_t Pin_num)
+{
+    /* Check the parameters */
+    assert_param(IS_PIN_NUM(Pin_num));
+
+    if (Pin_num <= P1_7)
+    {
+        return (Pin_num);
+    }
+    else if ((Pin_num >= P2_0) && (Pin_num <= P5_7))
+    {
+        return (Pin_num + 5);
+    }
+    else if ((Pin_num >= P6_0) && (Pin_num <= P7_4))
+    {
+        return (Pin_num + 3);
+    }
+    else if ((Pin_num >= MICBIAS) && (Pin_num <= DACN))
+    {
+        return (Pin_num - 48);
+    }
+    else if ((Pin_num >= P9_0) && (Pin_num <= P10_2))
+    {
+        return (Pin_num - 19);
+    }
+    return 0xFF;
+}
+
+
+void GPIO_ExtDebCmd(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin, FunctionalState NewState)
+{
+    uint32_t GPIO_Pin_Swap = GPIO_SwapDebPinBit(GPIOx, GPIO_Pin);
+
+    /* Configure Debounce register */
+    GPIO_Debounce_TypeDef *GPIOx_DEB = GPIOx == GPIOA ? GPIOA_DEB : GPIOB_DEB;
+
+    if (NewState == DISABLE)
+    {
+        GPIOx_DEB->GPIO_DEB_FUN_CTL &= (~GPIO_Pin_Swap);
+    }
+    else
+    {
+        for (uint8_t i = 0; i < 8; i++)
+        {
+            if ((GPIO_Pin_Swap & ((uint32_t)0x0F << i * 4)) != 0)
+            {
+                GPIOx_DEB->GPIO_DEB_FUN_CTL &= (~((uint32_t)0x0F << i * 4));
+                GPIOx_DEB->GPIO_DEB_FUN_CTL |= GPIO_Pin_Swap;
+
+                GPIO_DEB_CLK_CTL_TypeDef gpio_deb = {.d32 = GPIOx_DEB->GPIO_DEB_CLK_CTL[i / 2]};
+                if (i % 2)
+                {
+                    gpio_deb.b.GPIO_G_H_DEB_CNT_EN = ENABLE;
+                }
+                else
+                {
+                    gpio_deb.b.GPIO_G_L_DEB_CNT_EN = ENABLE;
+                }
+                GPIOx_DEB->GPIO_DEB_CLK_CTL[i / 2] = gpio_deb.d32;
+            }
+        }
+    }
+}
+
+
+void GPIO_ExtDebUpdate(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin,
+                       GPIODebounceSrc_TypeDef GPIO_DebounceClkSource,
+                       GPIODebounceDiv_TypeDef GPIO_DebounceClkDiv,
+                       uint8_t GPIO_DebounceCntLimit)
+{
+    uint32_t GPIO_Pin_Swap = GPIO_SwapDebPinBit(GPIOx, GPIO_Pin);
+
+    /* Configure Debounce register */
+    GPIO_Debounce_TypeDef *GPIOx_DEB = GPIOx == GPIOA ? GPIOA_DEB : GPIOB_DEB;
+
+    for (uint8_t i = 0; i < 8; i++)
+    {
+        if ((GPIO_Pin_Swap & ((uint32_t)0x0F << i * 4)) != 0)
+        {
+            GPIOx_DEB->GPIO_DEB_FUN_CTL &= (~((uint32_t)0x0F << i * 4));
+            GPIOx_DEB->GPIO_DEB_FUN_CTL |= GPIO_Pin_Swap;
+            GPIO_DEB_CLK_CTL_TypeDef gpio_deb = {.d32 = GPIOx_DEB->GPIO_DEB_CLK_CTL[i / 2]};
+            if (i % 2)
+            {
+                gpio_deb.b.GPIO_G_H_CNT_LIMIT = GPIO_DebounceCntLimit & 0xFF;
+                gpio_deb.b.GPIO_G_H_DEB_CLK_SEL = GPIO_DebounceClkSource;
+                gpio_deb.b.GPIO_G_H_DEB_CLK_DIV = GPIO_DebounceClkDiv;
+                gpio_deb.b.GPIO_G_H_DEB_CNT_EN = ENABLE;
+            }
+            else
+            {
+                gpio_deb.b.GPIO_G_L_CNT_LIMIT = GPIO_DebounceCntLimit & 0xFF;
+                gpio_deb.b.GPIO_G_L_DEB_CLK_SEL = GPIO_DebounceClkSource;
+                gpio_deb.b.GPIO_G_L_DEB_CLK_DIV = GPIO_DebounceClkDiv;
+                gpio_deb.b.GPIO_G_L_DEB_CNT_EN = ENABLE;
+            }
+            GPIOx_DEB->GPIO_DEB_CLK_CTL[i / 2] = gpio_deb.d32;
+        }
+    }
+}
+
+void GPIO_ExtPolarity(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin, GPIOITPolarity_TypeDef Int_Polarity)
+{
+    if (Int_Polarity == GPIO_INT_POLARITY_ACTIVE_LOW)
+    {
+        GPIOx->GPIO_EXT_DEB_POL_CTL &= (~GPIO_Pin);
+    }
+    else
+    {
+        GPIOx->GPIO_EXT_DEB_POL_CTL = (GPIOx->GPIO_EXT_DEB_POL_CTL & (~GPIO_Pin)) | GPIO_Pin;
+    }
+}
+
+
+RAM_FUNCTION
+void GPIO_DLPSEnter(void *PeriReg, void *StoreBuf)
+{
+    GPIO_TypeDef *GPIOx = (GPIO_TypeDef *)PeriReg;
+    GPIO_Debounce_TypeDef *GPIOx_DEB = GPIOx == GPIOA ? GPIOA_DEB : GPIOB_DEB;
+    GPIOStoreReg_Typedef *store_buf = (GPIOStoreReg_Typedef *)StoreBuf;
+
+    if (GPIOx == GPIOA)
+    {
+        RCC_PeriphClockCmd(APBPeriph_GPIOA, APBPeriph_GPIOA_CLOCK, ENABLE);
+    }
+    else if (GPIOx == GPIOB)
+    {
+        RCC_PeriphClockCmd(APBPeriph_GPIOB, APBPeriph_GPIOB_CLOCK, ENABLE);
+    }
+
+    store_buf->gpio_reg[0] = GPIOx->GPIO_DR;
+    store_buf->gpio_reg[1] = GPIOx->GPIO_DDR;
+    store_buf->gpio_reg[3] = GPIOx->GPIO_INT_EN;
+    store_buf->gpio_reg[4] = GPIOx->GPIO_INT_MASK;
+    store_buf->gpio_reg[5] = GPIOx->GPIO_INT_LV;
+    store_buf->gpio_reg[6] = GPIOx->GPIO_LS_SYNC;
+    store_buf->gpio_reg[7] = GPIOx->GPIO_OUT_MODE;
+    store_buf->gpio_reg[8] = GPIOx->GPIO_EXT_DEB_POL_CTL;
+
+    store_buf->gpio_reg[10] = GPIOx_DEB->GPIO_DEB_CLK_CTL[0];
+    store_buf->gpio_reg[11] = GPIOx_DEB->GPIO_DEB_CLK_CTL[1];
+    store_buf->gpio_reg[12] = GPIOx_DEB->GPIO_DEB_CLK_CTL[2];
+    store_buf->gpio_reg[13] = GPIOx_DEB->GPIO_DEB_CLK_CTL[3];
+    store_buf->gpio_reg[14] = GPIOx_DEB->GPIO_DEB_FUN_CTL;
+
+    return;
+}
+
+
+RAM_FUNCTION
+void GPIO_DLPSExit(void *PeriReg, void *StoreBuf)
+{
+    GPIO_TypeDef *GPIOx = (GPIO_TypeDef *)PeriReg;
+    GPIO_Debounce_TypeDef *GPIOx_DEB = GPIOx == GPIOA ? GPIOA_DEB : GPIOB_DEB;
+    GPIOStoreReg_Typedef *store_buf = (GPIOStoreReg_Typedef *)StoreBuf;
+
+    if (GPIOx == GPIOA)
+    {
+        RCC_PeriphClockCmd(APBPeriph_GPIOA, APBPeriph_GPIOA_CLOCK, ENABLE);
+    }
+    else if (GPIOx == GPIOB)
+    {
+        RCC_PeriphClockCmd(APBPeriph_GPIOB, APBPeriph_GPIOB_CLOCK, ENABLE);
+    }
+
+    GPIOx->GPIO_DDR               = store_buf->gpio_reg[1];
+    GPIOx->GPIO_OUT_MODE          = store_buf->gpio_reg[7];
+    GPIOx->GPIO_DR                = store_buf->gpio_reg[0];
+
+    GPIOx->GPIO_INT_MASK          = 0xFFFFFFFF;
+    GPIOx->GPIO_INT_LV            = store_buf->gpio_reg[5];
+    GPIOx->GPIO_LS_SYNC           = store_buf->gpio_reg[6];
+    GPIOx->GPIO_EXT_DEB_POL_CTL   = store_buf->gpio_reg[8];
+
+    GPIOx_DEB->GPIO_DEB_CLK_CTL[0] = store_buf->gpio_reg[10];
+    GPIOx_DEB->GPIO_DEB_CLK_CTL[1] = store_buf->gpio_reg[11];
+    GPIOx_DEB->GPIO_DEB_CLK_CTL[2] = store_buf->gpio_reg[12];
+    GPIOx_DEB->GPIO_DEB_CLK_CTL[3] = store_buf->gpio_reg[13];
+    GPIOx_DEB->GPIO_DEB_FUN_CTL   = store_buf->gpio_reg[14];
+
+    GPIOx->GPIO_INT_EN            = store_buf->gpio_reg[3];
+    GPIOx->GPIO_INT_CLR           = ~(store_buf->gpio_reg[1]);
+    GPIOx->GPIO_INT_MASK          = store_buf->gpio_reg[4];
+
+    return;
+}
+
diff --git a/bee/drivers/gpio/src/device/rtl87x2g/rtl_gpio.c b/bee/drivers/gpio/src/device/rtl87x2g/rtl_gpio.c
new file mode 100644
index 00000000..5d91d5cf
--- /dev/null
+++ b/bee/drivers/gpio/src/device/rtl87x2g/rtl_gpio.c
@@ -0,0 +1,484 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *                        Header Files
+ *============================================================================*/
+#include "rtl_gpio.h"
+#include "rtl_rcc.h"
+
+/*============================================================================*
+ *                          Private Macros
+ *============================================================================*/
+
+/*============================================================================*
+ *                          Private Functions
+ *============================================================================*/
+extern void GPIO_ExtPolarity(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin,
+                             GPIOITPolarity_TypeDef Int_Polarity);
+
+#if (GPIO_SUPPORT_SWAP_DEB_PINBIT == 1)
+extern uint32_t GPIO_SwapDebPinBit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin);
+#endif
+
+/*============================================================================*
+ *                           Public Functions
+ *============================================================================*/
+/**
+  * \brief  Deinitializes the GPIO peripheral registers to their default reset values.
+  * \param  GPIOx: Select the GPIO peripheral. \ref GPIO_Declaration
+  * \return None.
+  */
+void GPIO_DeInit(GPIO_TypeDef *GPIOx)
+{
+    switch ((uint32_t)GPIOx)
+    {
+#ifdef GPIOA
+    case (uint32_t)GPIOA:
+        RCC_PeriphClockCmd(APBPeriph_GPIOA, APBPeriph_GPIOA_CLOCK, DISABLE);
+        break;
+#endif
+#ifdef GPIOB
+    case (uint32_t)GPIOB:
+        RCC_PeriphClockCmd(APBPeriph_GPIOB, APBPeriph_GPIOB_CLOCK, DISABLE);
+        break;
+#endif
+#ifdef GPIOC
+    case (uint32_t)GPIOC:
+        RCC_PeriphClockCmd(APBPeriph_GPIOC, APBPeriph_GPIOC_CLOCK, DISABLE);
+        break;
+#endif
+#ifdef GPIOD
+    case (uint32_t)GPIOD:
+        RCC_PeriphClockCmd(APBPeriph_GPIOD, APBPeriph_GPIOD_CLOCK, DISABLE);
+        break;
+#endif
+
+    default:
+        break;
+    }
+}
+
+/**
+  * \brief  Initializes the GPIO peripheral according to the specified
+  *         parameters in the GPIO_InitStruct.
+  * \param  GPIOx: Select the GPIO peripheral. \ref GPIO_Declaration
+  * \param  GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that
+  *         contains the configuration information for the specified GPIO peripheral.
+  * \return None
+  */
+void GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_InitStruct)
+{
+    /* Check the parameters */
+    assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin));
+    assert_param(IS_GPIO_DIR(GPIO_InitStruct->GPIO_Dir));
+    assert_param(IS_GPIO_OUTPUT_MODE(GPIO_InitStruct->GPIO_OutPutMode));
+    assert_param(IS_GPIOIT_TRIGGER_TYPE(GPIO_InitStruct->GPIO_ITTrigger));
+    assert_param(IS_GPIOIT_POLARITY_TYPE(GPIO_InitStruct->GPIO_ITPolarity));
+    assert_param(IS_GPIOIT_DEBOUNCE_TYPE(GPIO_InitStruct->GPIO_ITDebounce));
+
+    /* GPIO configure */
+    if (GPIO_InitStruct->GPIO_Dir == GPIO_DIR_OUT)
+    {
+        GPIOx->GPIO_DDR |= GPIO_InitStruct->GPIO_Pin;
+
+        if (GPIO_InitStruct->GPIO_OutPutMode == GPIO_OUTPUT_OPENDRAIN)
+        {
+            GPIOx->GPIO_OUT_MODE |= GPIO_InitStruct->GPIO_Pin;
+        }
+        else
+        {
+            GPIOx->GPIO_OUT_MODE &= ~(GPIO_InitStruct->GPIO_Pin);
+        }
+
+#if (GPIO_SUPPORT_SET_CONTROL_MODE == 1)
+        if (GPIO_InitStruct->GPIO_ControlMode == GPIO_SOFTWARE_MODE)
+        {
+            /* Config GPIOx control software mode */
+            GPIOx->GPIO_SRC &= (~GPIO_InitStruct->GPIO_Pin);
+        }
+        else
+        {
+            /* Config GPIOx hardware control mode */
+            GPIOx->GPIO_SRC |= (GPIO_InitStruct->GPIO_Pin);
+        }
+#endif
+    }
+    else
+    {
+        /*Configure GPIO input mode */
+        GPIOx->GPIO_DDR = GPIOx->GPIO_DDR & (~GPIO_InitStruct->GPIO_Pin);
+
+        if (GPIO_InitStruct->GPIO_ITCmd == ENABLE)
+        {
+            GPIOx->GPIO_INT_MASK = ~GPIO_Pin_All;
+
+            /* configure GPIO interrupt trigger type */
+            if (GPIO_InitStruct->GPIO_ITTrigger == GPIO_INT_TRIGGER_LEVEL)
+            {
+                GPIOx->GPIO_INT_LV &= (~GPIO_InitStruct->GPIO_Pin);
+
+#if (GPIO_SUPPORT_LS_SYNC == 1)
+                /* Level-sensitive synchronization enable register */
+                GPIOx->GPIO_LS_SYNC = 0x1;
+#endif
+            }
+            else if (GPIO_InitStruct->GPIO_ITTrigger == GPIO_INT_TRIGGER_EDGE)
+            {
+                GPIOx->GPIO_INT_LV = (GPIOx->GPIO_INT_LV & (~GPIO_InitStruct->GPIO_Pin))
+                                     | GPIO_InitStruct->GPIO_Pin;
+            }
+#if GPIO_SUPPORT_INT_BOTHEDGE
+            else if (GPIO_InitStruct->GPIO_ITTrigger == GPIO_INT_TRIGGER_BOTH_EDGE)
+            {
+                GPIOx->GPIO_INT_BOTHEDGE |= GPIO_InitStruct->GPIO_Pin;
+            }
+#endif
+
+            /* configure Interrupt polarity register */
+            GPIO_ExtPolarity(GPIOx,
+#if (GPIO_SUPPORT_SWAP_DEB_PINBIT == 1)
+                             GPIO_SwapDebPinBit(GPIOx, GPIO_InitStruct->GPIO_Pin), GPIO_InitStruct->GPIO_ITPolarity);
+#else
+                             GPIO_InitStruct->GPIO_Pin, GPIO_InitStruct->GPIO_ITPolarity);
+#endif
+
+            /* configure Debounce enable register */
+            if (GPIO_InitStruct->GPIO_ITDebounce == GPIO_INT_DEBOUNCE_ENABLE)
+            {
+                GPIO_ExtDebUpdate(GPIOx, GPIO_InitStruct->GPIO_Pin,
+                                  GPIO_InitStruct->GPIO_DebounceClkSource,
+                                  GPIO_InitStruct->GPIO_DebounceClkDiv,
+                                  GPIO_InitStruct->GPIO_DebounceCntLimit);
+            }
+            GPIO_ExtDebCmd(GPIOx, GPIO_InitStruct->GPIO_Pin,
+                           (FunctionalState) GPIO_InitStruct->GPIO_ITDebounce);
+        }
+    }
+}
+
+/**
+  * \brief  Fills each GPIO_InitStruct member with its default value.
+  * \param  GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure which will be initialized.
+  * \return None
+  */
+void GPIO_StructInit(GPIO_InitTypeDef *GPIO_InitStruct)
+{
+    /* Reset GPIO init structure parameters values */
+    GPIO_InitStruct->GPIO_Pin        = GPIO_Pin_All;
+    GPIO_InitStruct->GPIO_Dir        = GPIO_DIR_IN;
+    GPIO_InitStruct->GPIO_OutPutMode = GPIO_OUTPUT_PUSHPULL;
+#if (GPIO_SUPPORT_SET_CONTROL_MODE == 1)
+    GPIO_InitStruct->GPIO_ControlMode = GPIO_SOFTWARE_MODE;
+#endif
+    GPIO_InitStruct->GPIO_ITCmd      = DISABLE;
+    GPIO_InitStruct->GPIO_ITTrigger  = GPIO_INT_TRIGGER_LEVEL;
+    GPIO_InitStruct->GPIO_ITPolarity = GPIO_INT_POLARITY_ACTIVE_LOW;
+    GPIO_InitStruct->GPIO_ITDebounce = GPIO_INT_DEBOUNCE_DISABLE;
+
+    /* Set GPIO doubonce parameters: set doubonce time is 1ms,
+     * debounce time = (CntLimit + 1) * DEB_CLK = 32 / 32000 = 1ms */
+    GPIO_InitStruct->GPIO_DebounceClkSource = GPIO_DEBOUNCE_32K;
+    GPIO_InitStruct->GPIO_DebounceClkDiv = GPIO_DEBOUNCE_DIVIDER_1;
+    GPIO_InitStruct->GPIO_DebounceCntLimit = 32;
+}
+
+/**
+  * \brief  Enable the specified GPIO interrupt.
+  * \param  GPIOx: Select the GPIO peripheral. \ref GPIO_Declaration
+  * \param  GPIO_Pin: GPIO_Pin can be 0 to 31.
+  * \param  Enable or disable interrupt
+  * \return None
+  */
+void GPIO_INTConfig(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_GPIO_PIN(GPIO_Pin));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (NewState != DISABLE)
+    {
+        /* Enable the selected GPIO pin interrupts */
+        GPIOx->GPIO_INT_EN |= GPIO_Pin;
+    }
+    else
+    {
+        /* Disable the selected GPIO pin interrupts */
+        GPIOx->GPIO_INT_EN &= ~GPIO_Pin;
+    }
+}
+
+/**
+  * \brief  Clear the specified GPIO interrupt.
+  * \param  GPIOx: Select the GPIO peripheral. \ref GPIO_Declaration
+  * \param  GPIO_Pin: GPIO_Pin can be 0 to 31.
+  * \return None
+  */
+void GPIO_ClearINTPendingBit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
+{
+    /* Check the parameters */
+    assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+    GPIOx->GPIO_INT_CLR = GPIO_Pin;
+}
+
+/**
+  * \brief  Mask the specified GPIO interrupt.
+  * \param  GPIOx: Select the GPIO peripheral. \ref GPIO_Declaration
+  * \param  GPIO_Pin: GPIO_Pin can be 0 to 31.
+  * \param  NewState: Mask or unmask gpio debounce clock.
+  * \return None
+  */
+void GPIO_MaskINTConfig(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_GPIO_PIN(GPIO_Pin));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (NewState != DISABLE)
+    {
+        GPIOx->GPIO_INT_MASK |= GPIO_Pin;
+    }
+    else
+    {
+        GPIOx->GPIO_INT_MASK &= ~(GPIO_Pin);
+    }
+}
+
+/**
+  * \brief  Set GPIO Output mode.
+  * \param  GPIOx: Select the GPIO peripheral. \ref GPIO_Declaration
+  * \param  GPIO_Pin: GPIO_Pin can be 0 to 31.
+  * \param  GPIO_OutputMode: Specifies the output mode to be set.
+  * \return None.
+  */
+void GPIO_SetOutputMode(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin,
+                        GPIOOutputMode_TypeDef GPIO_OutputMode)
+{
+    /* Check the parameters */
+    assert_param(IS_GPIO_OUTPUT_MODE(GPIO_OutputMode));
+
+    /* configure Interrupt polarity register */
+    if (GPIO_OutputMode == GPIO_OUTPUT_OPENDRAIN)
+    {
+        GPIOx->GPIO_OUT_MODE = (GPIOx->GPIO_OUT_MODE & (~GPIO_Pin)) | GPIO_Pin;
+    }
+    else
+    {
+        GPIOx->GPIO_OUT_MODE &= (~GPIO_Pin);
+    }
+}
+
+/**
+  * \brief  Read the specified input port pin.
+  * \param  GPIOx: Select the GPIO peripheral. \ref GPIO_Declaration
+  * \param  GPIO_Pin: Specifies the port bit to read.
+  * \return The input port pin value.
+  */
+uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
+{
+    /* Check the parameters */
+    assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
+
+    if (GPIOx->GPIO_PAD_STATE & GPIO_Pin)
+    {
+        return SET;
+    }
+    else
+    {
+        return RESET;
+    }
+}
+
+/**
+  * \brief  Read value of all GPIO input data port.
+  * \param  GPIOx: Select the GPIO peripheral. \ref GPIO_Declaration
+  * \return GPIO input data port value.
+  */
+uint32_t GPIO_ReadInputData(GPIO_TypeDef *GPIOx)
+{
+    return ((uint32_t)GPIOx->GPIO_PAD_STATE);
+}
+
+/**
+  * \brief  Read the specified output port pin.
+  * \param  GPIOx: Select the GPIO peripheral. \ref GPIO_Declaration
+  * \param  GPIO_Pin: Specifies the port bit to read.
+  * \return The output port pin value.
+  */
+uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
+{
+    /* Check the parameters */
+    assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
+
+    if (GPIOx->GPIO_DR & GPIO_Pin)
+    {
+        return SET;
+    }
+    else
+    {
+        return RESET;
+    }
+}
+
+/**
+  * \brief  Read value of all GPIO output data port.
+  * \param  GPIOx: Select the GPIO peripheral. \ref GPIO_Declaration
+  * \return GPIO output data port value.
+  */
+uint32_t GPIO_ReadOutputData(GPIO_TypeDef *GPIOx)
+{
+    return ((uint32_t)GPIOx->GPIO_DR);
+}
+
+/**
+  * \brief  Sets the selected data port bit.
+  * \param  GPIOx: Select the GPIO peripheral. \ref GPIO_Declaration
+  * \param  GPIO_Pin: Specifies the port bit to be written.
+  * \return None.
+  */
+void GPIO_SetBits(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
+{
+    /* Check the parameters */
+    assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+    GPIOx->GPIO_DR |= GPIO_Pin;
+}
+
+/**
+  * \brief  Reset the selected data port bit.
+  * \param  GPIOx: Select the GPIO peripheral. \ref GPIO_Declaration
+  * \param  GPIO_Pin: Specifies the port bits to be written.
+  * \return None.
+  */
+void GPIO_ResetBits(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
+{
+    /* Check the parameters */
+    assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+    GPIOx->GPIO_DR &= ~(GPIO_Pin);
+}
+
+/**
+  * \brief  Set or clear the selected data port bit.
+  * \param  GPIOx: Select the GPIO peripheral. \ref GPIO_Declaration
+  * \param  GPIO_Pin: Specifies the port bit to be written.
+  * \param  BitVal: specifies the value to be written to the selected bit.
+  * \return None.
+  */
+void GPIO_WriteBit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin, BitAction BitVal)
+{
+    /* Check the parameters */
+    assert_param(IS_GPIO_PIN(GPIO_Pin));
+    assert_param(IS_GPIO_BIT_ACTION(BitVal));
+
+    if (BitVal != Bit_RESET)
+    {
+        GPIOx->GPIO_DR |= GPIO_Pin;
+    }
+    else
+    {
+        GPIOx->GPIO_DR &= ~(GPIO_Pin);
+    }
+}
+
+/**
+  * \brief  Set or clear data port.
+  * \param  GPIOx: Select the GPIO peripheral. \ref GPIO_Declaration
+  * \param  PortVal: Specifies the value to be written to the selected bit.
+  * \return None.
+  */
+void GPIO_Write(GPIO_TypeDef *GPIOx, uint32_t PortVal)
+{
+    GPIOx->GPIO_DR = PortVal;
+}
+
+
+/**
+  * \brief  Get GPIO interrupt status.
+  * \param  GPIOx: Select the GPIO peripheral. \ref GPIO_Declaration
+  * \param  GPIO_Pin: Specifies the port bit to be written.
+  * \return The new state of GPIO_IT (SET or RESET).
+  */
+ITStatus GPIO_GetINTStatus(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
+{
+    /* Check the parameters */
+    assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
+
+    if ((GPIOx->GPIO_INT_STS & GPIO_Pin) == GPIO_Pin)
+    {
+        return SET;
+    }
+    else
+    {
+        return RESET;
+    }
+}
+
+/**
+  * \brief  Specifies the direction for the selected pins.
+  * \param  GPIOx: Select the GPIO peripheral. \ref GPIO_Declaration
+  * \param  GPIO_PinBit: Specifies the GPIO pins to be configured, please refer to "GPIO_pins_define" part.
+  * \param  GPIO_Dir: Set the GPIO direction.
+  * \return None.
+  */
+void GPIO_SetDirection(GPIO_TypeDef *GPIOx, uint32_t GPIO_PinBit,
+                       GPIODir_TypeDef GPIO_Dir)
+{
+    /* Check the parameters */
+    assert_param(IS_GPIO_PIN(GPIO_PinBit));
+
+    if (GPIO_Dir == GPIO_DIR_OUT)
+    {
+        GPIOx->GPIO_DDR |= GPIO_PinBit;
+    }
+    else
+    {
+        GPIOx->GPIO_DDR &= ~GPIO_PinBit;
+    }
+}
+
+/**
+  * \brief  Get GPIO pad status.
+  * \param  GPIO_Pin: Specifies the port bit to be written.
+  * \return The new state of GPIO_Pad (SET or RESET).
+  */
+FlagStatus GPIO_GetPadStatus(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
+{
+    /* Check the parameters */
+    assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
+
+    if ((GPIOx->GPIO_PAD_STATE & GPIO_Pin) == GPIO_Pin)
+    {
+        return SET;
+    }
+    else
+    {
+        return RESET;
+    }
+}
+
+/**
+  * \brief  Set GPIO Int Polarity.
+  * \param  GPIOx: Select the GPIO peripheral. \ref GPIO_Declaration
+  * \param  GPIO_Pin: GPIO_Pin can be 0 to 31.
+  * \param  int_type: Specifies the polarity type to be set.
+  * \return None.
+  */
+void GPIO_SetPolarity(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin,
+                      GPIOITPolarity_TypeDef int_type)
+{
+    /* Check the parameters */
+    assert_param(IS_GPIOIT_POLARITY_TYPE(int_type));
+
+    GPIO_ExtPolarity(GPIOx,
+#if (GPIO_SUPPORT_SWAP_DEB_PINBIT == 1)
+                     GPIO_SwapDebPinBit(GPIOx, GPIO_Pin), int_type);
+#else
+                     GPIO_Pin, int_type);
+#endif
+}
+
diff --git a/bee/drivers/gpio/src/device/rtl87x2g/rtl_gpio.h b/bee/drivers/gpio/src/device/rtl87x2g/rtl_gpio.h
new file mode 100644
index 00000000..8ce2bf9f
--- /dev/null
+++ b/bee/drivers/gpio/src/device/rtl87x2g/rtl_gpio.h
@@ -0,0 +1,1089 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *               Define to prevent recursive inclusion
+ *============================================================================*/
+#ifndef RTL_GPIO_H
+#define RTL_GPIO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*============================================================================*
+ *                        Header Files
+ *============================================================================*/
+#include "utils/rtl_utils.h"
+#include "rtl_gpio_def.h"
+#include "pin_def.h"
+
+/** \defgroup GPIO        GPIO
+  * \brief
+  * \{
+  */
+
+/*============================================================================*
+ *                         Constants
+ *============================================================================*/
+/** \defgroup GPIO_Exported_Constants GPIO Exported Constants
+  * \brief
+  * \{
+  */
+
+/**
+ * \defgroup    GPIO_Number GPIO Number
+ * \{
+ * \ingroup     GPIO_Exported_Constants
+ */
+#ifdef GPIOA
+#define GPIOA0   0     //!< GPIOA0 corresponding number is 0.
+#define GPIOA1   1     //!< GPIOA1 corresponding number is 1.
+#define GPIOA2   2     //!< GPIOA2 corresponding number is 2.
+#define GPIOA3   3     //!< GPIOA3 corresponding number is 3.
+#define GPIOA4   4     //!< GPIOA4 corresponding number is 4.
+#define GPIOA5   5     //!< GPIOA5 corresponding number is 5.
+#define GPIOA6   6     //!< GPIOA6 corresponding number is 6.
+#define GPIOA7   7     //!< GPIOA7 corresponding number is 7.
+#define GPIOA8   8     //!< GPIOA8 corresponding number is 8.
+#define GPIOA9   9     //!< GPIOA9 corresponding number is 9.
+#define GPIOA10  10    //!< GPIOA10 corresponding number is 10.
+#define GPIOA11  11    //!< GPIOA11 corresponding number is 11.
+#define GPIOA12  12    //!< GPIOA12 corresponding number is 12.
+#define GPIOA13  13    //!< GPIOA13 corresponding number is 13.
+#define GPIOA14  14    //!< GPIOA14 corresponding number is 14.
+#define GPIOA15  15    //!< GPIOA15 corresponding number is 15.
+#define GPIOA16  16    //!< GPIOA16 corresponding number is 16.
+#define GPIOA17  17    //!< GPIOA17 corresponding number is 17.
+#define GPIOA18  18    //!< GPIOA18 corresponding number is 18.
+#define GPIOA19  19    //!< GPIOA19 corresponding number is 19.
+#define GPIOA20  20    //!< GPIOA20 corresponding number is 20.
+#define GPIOA21  21    //!< GPIOA21 corresponding number is 21.
+#define GPIOA22  22    //!< GPIOA22 corresponding number is 22.
+#define GPIOA23  23    //!< GPIOA23 corresponding number is 23.
+#define GPIOA24  24    //!< GPIOA24 corresponding number is 24.
+#define GPIOA25  25    //!< GPIOA25 corresponding number is 25.
+#define GPIOA26  26    //!< GPIOA26 corresponding number is 26.
+#define GPIOA27  27    //!< GPIOA27 corresponding number is 27.
+#define GPIOA28  28    //!< GPIOA28 corresponding number is 28.
+#define GPIOA29  29    //!< GPIOA29 corresponding number is 29.
+#define GPIOA30  30    //!< GPIOA30 corresponding number is 30.
+#define GPIOA31  31    //!< GPIOA31 corresponding number is 31.
+#endif
+#ifdef GPIOB
+#define GPIOB0   32    //!< GPIOA32 corresponding number is 32.
+#define GPIOB1   33    //!< GPIOA33 corresponding number is 33.
+#define GPIOB2   34    //!< GPIOA34 corresponding number is 34.
+#define GPIOB3   35    //!< GPIOA35 corresponding number is 35.
+#define GPIOB4   36    //!< GPIOA36 corresponding number is 36.
+#define GPIOB5   37    //!< GPIOA37 corresponding number is 37.
+#define GPIOB6   38    //!< GPIOA38 corresponding number is 38.
+#define GPIOB7   39    //!< GPIOA39 corresponding number is 39.
+#define GPIOB8   40    //!< GPIOA40 corresponding number is 40.
+#define GPIOB9   41    //!< GPIOA41 corresponding number is 41.
+#define GPIOB10  42    //!< GPIOA42 corresponding number is 42.
+#define GPIOB11  43    //!< GPIOA43 corresponding number is 43.
+#define GPIOB12  44    //!< GPIOA44 corresponding number is 44.
+#define GPIOB13  45    //!< GPIOA45 corresponding number is 45.
+#define GPIOB14  46    //!< GPIOA46 corresponding number is 46.
+#define GPIOB15  47    //!< GPIOA47 corresponding number is 47.
+#define GPIOB16  48    //!< GPIOA48 corresponding number is 48.
+#define GPIOB17  49    //!< GPIOA49 corresponding number is 49.
+#define GPIOB18  50    //!< GPIOA50 corresponding number is 50.
+#define GPIOB19  51    //!< GPIOA51 corresponding number is 51.
+#define GPIOB20  52    //!< GPIOA52 corresponding number is 52.
+#define GPIOB21  53    //!< GPIOA53 corresponding number is 53.
+#define GPIOB22  54    //!< GPIOA54 corresponding number is 54.
+#define GPIOB23  55    //!< GPIOA55 corresponding number is 55.
+#define GPIOB24  56    //!< GPIOA56 corresponding number is 56.
+#define GPIOB25  57    //!< GPIOA57 corresponding number is 57.
+#define GPIOB26  58    //!< GPIOA58 corresponding number is 58.
+#define GPIOB27  59    //!< GPIOA59 corresponding number is 59.
+#define GPIOB28  60    //!< GPIOA60 corresponding number is 60.
+#define GPIOB29  61    //!< GPIOA61 corresponding number is 61.
+#define GPIOB30  62    //!< GPIOA62 corresponding number is 62.
+#define GPIOB31  63    //!< GPIOA63 corresponding number is 63.
+#endif
+#ifdef GPIOC
+#define GPIOC0   64    //!< GPIOA64 corresponding number is 64.
+#define GPIOC1   65    //!< GPIOA65 corresponding number is 65.
+#define GPIOC2   66    //!< GPIOA66 corresponding number is 66.
+#define GPIOC3   67    //!< GPIOA67 corresponding number is 67.
+#define GPIOC4   68    //!< GPIOA68 corresponding number is 68.
+#define GPIOC5   69    //!< GPIOA69 corresponding number is 69.
+#define GPIOC6   70    //!< GPIOA70 corresponding number is 70.
+#define GPIOC7   71    //!< GPIOA71 corresponding number is 71.
+#define GPIOC8   72    //!< GPIOA72 corresponding number is 72.
+#define GPIOC9   73    //!< GPIOA73 corresponding number is 73.
+#define GPIOC10  74    //!< GPIOA74 corresponding number is 74.
+#define GPIOC11  75    //!< GPIOA75 corresponding number is 75.
+#define GPIOC12  76    //!< GPIOA76 corresponding number is 76.
+#define GPIOC13  77    //!< GPIOA77 corresponding number is 77.
+#define GPIOC14  78    //!< GPIOA78 corresponding number is 78.
+#define GPIOC15  79    //!< GPIOA79 corresponding number is 79.
+#define GPIOC16  80    //!< GPIOA80 corresponding number is 80.
+#define GPIOC17  81    //!< GPIOA81 corresponding number is 81.
+#define GPIOC18  82    //!< GPIOA82 corresponding number is 82.
+#define GPIOC19  83    //!< GPIOA83 corresponding number is 83.
+#define GPIOC20  84    //!< GPIOA84 corresponding number is 84.
+#define GPIOC21  85    //!< GPIOA85 corresponding number is 85.
+#define GPIOC22  86    //!< GPIOA86 corresponding number is 86.
+#define GPIOC23  87    //!< GPIOA87 corresponding number is 87.
+#define GPIOC24  88    //!< GPIOA88 corresponding number is 88.
+#define GPIOC25  89    //!< GPIOA89 corresponding number is 89.
+#define GPIOC26  90    //!< GPIOA90 corresponding number is 90.
+#define GPIOC27  91    //!< GPIOA91 corresponding number is 91.
+#define GPIOC28  92    //!< GPIOA92 corresponding number is 92.
+#define GPIOC29  93    //!< GPIOA93 corresponding number is 93.
+#define GPIOC30  94    //!< GPIOA94 corresponding number is 94.
+#define GPIOC31  95    //!< GPIOA95 corresponding number is 95.
+#endif
+#ifdef GPIOD
+#define GPIOD0   96    //!< GPIOA96 corresponding number is 96.
+#define GPIOD1   97    //!< GPIOA97 corresponding number is 97.
+#define GPIOD2   98    //!< GPIOA98 corresponding number is 98.
+#define GPIOD3   99    //!< GPIOA99 corresponding number is 99.
+#define GPIOD4   100   //!< GPIOA100 corresponding number is 100.
+#define GPIOD5   101   //!< GPIOA101 corresponding number is 101.
+#define GPIOD6   102   //!< GPIOA102 corresponding number is 102.
+#define GPIOD7   103   //!< GPIOA103 corresponding number is 103.
+#define GPIOD8   104   //!< GPIOA104 corresponding number is 104.
+#define GPIOD9   105   //!< GPIOA105 corresponding number is 105.
+#define GPIOD10  106   //!< GPIOA106 corresponding number is 106.
+#define GPIOD11  107   //!< GPIOA107 corresponding number is 107.
+#define GPIOD12  108   //!< GPIOA108 corresponding number is 108.
+#define GPIOD13  109   //!< GPIOA109 corresponding number is 109.
+#define GPIOD14  110   //!< GPIOA110 corresponding number is 110.
+#define GPIOD15  111   //!< GPIOA111 corresponding number is 111.
+#define GPIOD16  112   //!< GPIOA112 corresponding number is 112.
+#define GPIOD17  113   //!< GPIOA113 corresponding number is 113.
+#define GPIOD18  114   //!< GPIOA114 corresponding number is 114.
+#define GPIOD19  115   //!< GPIOA115 corresponding number is 115.
+#define GPIOD20  116   //!< GPIOA116 corresponding number is 116.
+#define GPIOD21  117   //!< GPIOA117 corresponding number is 117.
+#define GPIOD22  118   //!< GPIOA118 corresponding number is 118.
+#define GPIOD23  119   //!< GPIOA119 corresponding number is 119.
+#define GPIOD24  120   //!< GPIOA120 corresponding number is 120.
+#define GPIOD25  121   //!< GPIOA121 corresponding number is 121.
+#define GPIOD26  122   //!< GPIOA122 corresponding number is 122.
+#define GPIOD27  123   //!< GPIOA123 corresponding number is 123.
+#define GPIOD28  124   //!< GPIOA124 corresponding number is 124.
+#define GPIOD29  125   //!< GPIOA125 corresponding number is 125.
+#define GPIOD30  126   //!< GPIOA126 corresponding number is 126.
+#define GPIOD31  127   //!< GPIOA127 corresponding number is 127.
+#endif
+
+/** End of GPIO_Number
+  * \}
+  */
+
+/**
+ * \defgroup    GPIO_Pins_Define GPIO Pins Define
+ * \{
+ * \ingroup     GPIO_Exported_Constants
+ */
+#define GPIO_Pin_0                 (BIT0)   //!< GPIO Pin 0 selected.
+#define GPIO_Pin_1                 (BIT1)   //!< GPIO Pin 1 selected.
+#define GPIO_Pin_2                 (BIT2)   //!< GPIO Pin 2 selected.
+#define GPIO_Pin_3                 (BIT3)   //!< GPIO Pin 3 selected.
+#define GPIO_Pin_4                 (BIT4)   //!< GPIO Pin 4 selected.
+#define GPIO_Pin_5                 (BIT5)   //!< GPIO Pin 5 selected.
+#define GPIO_Pin_6                 (BIT6)   //!< GPIO Pin 6 selected.
+#define GPIO_Pin_7                 (BIT7)   //!< GPIO Pin 7 selected.
+#define GPIO_Pin_8                 (BIT8)   //!< GPIO Pin 8 selected.
+#define GPIO_Pin_9                 (BIT9)   //!< GPIO Pin 9 selected.
+#define GPIO_Pin_10                (BIT10)  //!< GPIO Pin 10 selected.
+#define GPIO_Pin_11                (BIT11)  //!< GPIO Pin 11 selected.
+#define GPIO_Pin_12                (BIT12)  //!< GPIO Pin 12 selected.
+#define GPIO_Pin_13                (BIT13)  //!< GPIO Pin 13 selected.
+#define GPIO_Pin_14                (BIT14)  //!< GPIO Pin 14 selected.
+#define GPIO_Pin_15                (BIT15)  //!< GPIO Pin 15 selected.
+#define GPIO_Pin_16                (BIT16)  //!< GPIO Pin 16 selected.
+#define GPIO_Pin_17                (BIT17)  //!< GPIO Pin 17 selected.
+#define GPIO_Pin_18                (BIT18)  //!< GPIO Pin 18 selected.
+#define GPIO_Pin_19                (BIT19)  //!< GPIO Pin 19 selected.
+#define GPIO_Pin_20                (BIT20)  //!< GPIO Pin 20 selected.
+#define GPIO_Pin_21                (BIT21)  //!< GPIO Pin 21 selected.
+#define GPIO_Pin_22                (BIT22)  //!< GPIO Pin 22 selected.
+#define GPIO_Pin_23                (BIT23)  //!< GPIO Pin 23 selected.
+#define GPIO_Pin_24                (BIT24)  //!< GPIO Pin 24 selected.
+#define GPIO_Pin_25                (BIT25)  //!< GPIO Pin 25 selected.
+#define GPIO_Pin_26                (BIT26)  //!< GPIO Pin 26 selected.
+#define GPIO_Pin_27                (BIT27)  //!< GPIO Pin 27 selected.
+#define GPIO_Pin_28                (BIT28)  //!< GPIO Pin 28 selected.
+#define GPIO_Pin_29                (BIT29)  //!< GPIO Pin 29 selected.
+#define GPIO_Pin_30                (BIT30)  //!< GPIO Pin 30 selected.
+#define GPIO_Pin_31                (BIT31)  //!< GPIO Pin 31 selected.
+#define GPIO_Pin_All               ((uint32_t)0xFFFFFFFF)  //!< All pins selected.
+
+#define IS_GET_GPIO_PIN(PIN)       (((PIN) == GPIO_Pin_0) || \
+                                    ((PIN) == GPIO_Pin_1) || \
+                                    ((PIN) == GPIO_Pin_2) || \
+                                    ((PIN) == GPIO_Pin_3) || \
+                                    ((PIN) == GPIO_Pin_4) || \
+                                    ((PIN) == GPIO_Pin_5) || \
+                                    ((PIN) == GPIO_Pin_6) || \
+                                    ((PIN) == GPIO_Pin_7) || \
+                                    ((PIN) == GPIO_Pin_8) || \
+                                    ((PIN) == GPIO_Pin_9) || \
+                                    ((PIN) == GPIO_Pin_10) || \
+                                    ((PIN) == GPIO_Pin_11) || \
+                                    ((PIN) == GPIO_Pin_12) || \
+                                    ((PIN) == GPIO_Pin_13) || \
+                                    ((PIN) == GPIO_Pin_14) || \
+                                    ((PIN) == GPIO_Pin_15) || \
+                                    ((PIN) == GPIO_Pin_16) || \
+                                    ((PIN) == GPIO_Pin_17) || \
+                                    ((PIN) == GPIO_Pin_18) || \
+                                    ((PIN) == GPIO_Pin_19) || \
+                                    ((PIN) == GPIO_Pin_20) || \
+                                    ((PIN) == GPIO_Pin_21) || \
+                                    ((PIN) == GPIO_Pin_22) || \
+                                    ((PIN) == GPIO_Pin_23) || \
+                                    ((PIN) == GPIO_Pin_24) || \
+                                    ((PIN) == GPIO_Pin_25) || \
+                                    ((PIN) == GPIO_Pin_26) || \
+                                    ((PIN) == GPIO_Pin_27) || \
+                                    ((PIN) == GPIO_Pin_28) || \
+                                    ((PIN) == GPIO_Pin_29) || \
+                                    ((PIN) == GPIO_Pin_30) || \
+                                    ((PIN) == GPIO_Pin_31) || \
+                                    ((PIN) == GPIO_Pin_All)) //!< Check if the input parameter is valid.
+
+#define IS_GPIO_PIN(PIN)          ((PIN) != (uint32_t)0x00) //!< Check if the input parameter is valid.
+
+/** End of GPIO_Pins_Define
+  * \}
+  */
+
+/**
+ * \defgroup    GPIO_Bit_Action GPIO Bit Action
+ * \{
+ * \ingroup     GPIO_Exported_Constants
+ */
+typedef enum
+{
+    Bit_RESET = 0, //!< Reset the GPIO bit.
+    Bit_SET        //!< Set the GPIO bit.
+} BitAction;
+
+#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET)) //!< Check if the input parameter is valid.
+
+/** End of GPIO_Bit_Action
+  * \}
+  */
+
+/**
+ * \defgroup    GPIO_Direction GPIO Direction
+ * \{
+ * \ingroup     GPIO_Exported_Constants
+ */
+typedef enum
+{
+    GPIO_DIR_IN   = 0x0, //!< GPIO input direction.
+    GPIO_DIR_OUT  = 0x1, //!< GPIO output direction.
+} GPIODir_TypeDef;
+
+#define IS_GPIO_DIR(DIR) (((DIR) == GPIO_DIR_IN) || ((DIR) == GPIO_DIR_OUT)) //!< Check if the input parameter is valid.
+
+/** End of GPIO_Direction
+  * \}
+  */
+
+/**
+ * \defgroup    GPIO_Output_Mode GPIO Output Mode
+ * \{
+ * \ingroup     GPIO_Exported_Constants
+ */
+typedef enum
+{
+    GPIO_OUTPUT_PUSHPULL  = 0x0, //!< GPIO output push-pull mode.
+    GPIO_OUTPUT_OPENDRAIN = 0x1, //!< GPIO output open-drain mode.
+} GPIOOutputMode_TypeDef;
+
+#define IS_GPIO_OUTPUT_MODE(MODE) (((MODE) == GPIO_OUTPUT_PUSHPULL)|| ((MODE) == GPIO_OUTPUT_OPENDRAIN)) //!< Check if the input parameter is valid.
+
+/** End of GPIO_Output_Mode
+  * \}
+  */
+
+#if (GPIO_SUPPORT_SET_CONTROL_MODE == 1)
+/**
+ * \brief       GPIO control mode enumeration.
+ *
+ * \ingroup     GPIO_Exported_Constants
+ */
+typedef enum
+{
+    GPIO_SOFTWARE_MODE = 0x0,  //!< GPIO software control mode(default).
+    GPIO_HARDWARE_MODE  = 0x1, //!< GPIO hardware control mode.
+} GPIOControlMode_Typedef;
+
+#define IS_GPIOIT_MODDE(TYPE) (((TYPE) == GPIO_SOFTWARE_MODE)\
+                               || ((TYPE) == GPIO_HARDWARE_MODE)) //!< Check if the input parameter is valid.
+#endif
+
+/**
+ * \defgroup    GPIO_Interrupt_Trigger GPIO Interrupt Trigger
+ * \{
+ * \ingroup     GPIO_Exported_Constants
+ */
+typedef enum
+{
+    GPIO_INT_TRIGGER_LEVEL = 0x0,     //!< GPIO interrupt trigger mode is level trigger.
+    GPIO_INT_TRIGGER_EDGE  = 0x1,     //!< GPIO interrupt trigger mode is edge trigger.
+#if GPIO_SUPPORT_INT_BOTHEDGE
+    GPIO_INT_TRIGGER_BOTH_EDGE = 0x2, //!< GPIO interrupt trigger mode is both edge trigger.
+#endif
+} GPIOITTrigger_TypeDef;
+
+#define IS_GPIOIT_TRIGGER_TYPE(TYPE) (((TYPE) == GPIO_INT_TRIGGER_LEVEL) || \
+                                      ((TYPE) == GPIO_INT_TRIGGER_EDGE)) //!< Check if the input parameter is valid.
+
+/** End of GPIO_Interrupt_Trigger
+  * \}
+  */
+
+/**
+ * \defgroup    GPIO_Interrupt_Polarity GPIO Interrupt Polarity
+ * \{
+ * \ingroup     GPIO_Exported_Constants
+ */
+typedef enum
+{
+    GPIO_INT_POLARITY_ACTIVE_LOW  = 0x0, //!< GPIO interrupt interrupt Polarity is low active.
+    GPIO_INT_POLARITY_ACTIVE_HIGH = 0x1, //!< GPIO interrupt interrupt Polarity is high active.
+} GPIOITPolarity_TypeDef;
+
+#define IS_GPIOIT_POLARITY_TYPE(TYPE) (((TYPE) == GPIO_INT_POLARITY_ACTIVE_LOW) || \
+                                       ((TYPE) == GPIO_INT_POLARITY_ACTIVE_HIGH)) //!< Check if the input parameter is valid.
+
+/** End of GPIO_Interrupt_Polarity
+  * \}
+  */
+
+/**
+ * \defgroup    GPIO_Interrupt_Debounce GPIO Interrupt Debounce
+ * \{
+ * \ingroup     GPIO_Exported_Constants
+ */
+typedef enum
+{
+    GPIO_INT_DEBOUNCE_DISABLE = 0x0, //!< Disable interrupt debounce.
+    GPIO_INT_DEBOUNCE_ENABLE  = 0x1, //!< Enable interrupt debounce.
+} GPIODebounce_TypeDef;
+
+#define IS_GPIOIT_DEBOUNCE_TYPE(TYPE) (((TYPE) == GPIO_INT_DEBOUNCE_DISABLE) || \
+                                       ((TYPE) == GPIO_INT_DEBOUNCE_ENABLE)) //!< Check if the input parameter is valid.
+
+/** End of GPIO_Interrupt_Debounce
+  * \}
+  */
+
+#if (GPIO_SUPPORT_RAP_FUNCTION == 1)
+/**
+ * \defgroup    GPIO_Qactive_Force GPIO Qactive Force
+ * \{
+ * \ingroup     GPIO_Exported_Constants
+ */
+typedef enum
+{
+    GPIO_QACTIVE_PCLK_FORCE     = 0x0,
+    GPIO_QACTIVE_PCLKINTR_FORCE = 0x1,
+    GPIO_QACTIVE_CLK32K_FORCE   = 0x2,
+} GPIOQactiveForce_TypeDef;
+
+/** End of GPIO_Qactive_Force
+  * \}
+  */
+
+/**
+ * \defgroup    GPIO_Task GPIO Task
+ * \{
+ * \ingroup     GPIO_Exported_Constants
+ */
+typedef enum
+{
+    GPIO_TASK_DRSET = 0,
+    GPIO_TASK_DRCLR = 1,
+    GPIO_TASK_DRTOGGLE = 2,
+    GPIO_TASK_POLSET = 3,
+    GPIO_TASK_POLCLR = 4,
+    GPIO_TASK_POLTOGGLE = 5,
+    GPIO_TASK_DDRSET = 6,
+    GPIO_TASK_DDRCLR = 7,
+} GPIOTask_TypeDef;
+
+/** End of GPIO_Task
+  * \}
+  */
+
+
+#endif
+
+/** End of GPIO_Exported_Constants
+  * \}
+  */
+
+/*============================================================================*
+ *                         Types
+ *============================================================================*/
+/** \defgroup GPIO_Exported_Types GPIO Exported Types
+  * \brief
+  * \{
+  */
+
+/**
+ * \brief       GPIO init structure definition.
+ *
+ * \ingroup     GPIO_Exported_Types
+ */
+typedef struct
+{
+
+    uint32_t                GPIO_Pin;           /**< Specify the GPIO pins to be configured.
+                                                     This parameter can be a value of \ref GPIO_Pins_Define. */
+
+    GPIODir_TypeDef         GPIO_Dir;           /**< Specify the GPIO direction.
+                                                     This parameter can be a value of \ref GPIO_Direction */
+
+    GPIOOutputMode_TypeDef  GPIO_OutPutMode;    /**< Specify the GPIO output mode.
+                                                     This parameter can be a value of \ref GPIO_Output_Mode */
+
+#if (GPIO_SUPPORT_SET_CONTROL_MODE == 1)
+    GPIOControlMode_Typedef GPIO_ControlMode;   /**< Specify the GPIO mode. */
+#endif
+
+    FunctionalState         GPIO_ITCmd;         /**< Enable or disable GPIO interrupt.
+                                                     This parameter can be a value of ENABLE or DISABLE. */
+
+    GPIOITTrigger_TypeDef   GPIO_ITTrigger;     /**< Specify the GPIO interrupt trigger.
+                                                     This parameter can be a value of \ref GPIO_Interrupt_Trigger */
+
+    GPIOITPolarity_TypeDef  GPIO_ITPolarity;    /**< Specify the GPIO interrupt polarity.
+                                                     This parameter can be a value of \ref GPIO_Interrupt_Polarity */
+
+    GPIODebounce_TypeDef    GPIO_ITDebounce;    /**< Enable or disable debounce for interrupt.
+                                                     This parameter can be a value of \ref GPIO_Interrupt_Debounce */
+
+    GPIODebounceSrc_TypeDef GPIO_DebounceClkSource; /**< Select debounce count clock source.
+                                                         This parameter can be a value of \ref GPIO_Debounce_Clock_Source */
+
+    GPIODebounceDiv_TypeDef GPIO_DebounceClkDiv;    /**< Specify the debounce clock divider.
+                                                         This parameter can be a value of \ref GPIO_Debounce_Divider */
+
+    uint8_t
+    GPIO_DebounceCntLimit;  /**< Specify the debounce Limit. Debounce_time = (CntLimit + 1) * GPIO_DebounceClkSource/GPIO_DebounceClkDiv.
+                                                         This parameter leagel value range is from 0 ~ 255. */
+} GPIO_InitTypeDef;
+
+/** End of GPIO_Exported_Types
+  * \}
+  */
+
+/*============================================================================*
+ *                         Functions
+ *============================================================================*/
+/** \defgroup GPIO_Exported_Functions GPIO Exported Functions
+  * \brief
+  * \{
+  */
+
+/**
+ * \brief   Deinitialize the GPIO peripheral registers to their default reset values.
+ *
+ * \param[in] GPIOx  Select the GPIO peripheral. Refer to \ref GPIO_Declaration.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_gpio_init(void)
+ * {
+ *     GPIO_DeInit(GPIOA);
+ * }
+ * \endcode
+ */
+void GPIO_DeInit(GPIO_TypeDef *GPIOx);
+
+/**
+ * \brief  Initialize the GPIO peripheral according to the specified
+ *         parameters in the GPIO_InitStruct.
+ *
+ * \param[in] GPIOx            Select the GPIO peripheral. Refer to \ref GPIO_Declaration.
+ * \param[in] GPIO_InitStruct  Pointer to a GPIO_InitTypeDef structure which will be initialized.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_gpio_init(void)
+ * {
+ *     RCC_PeriphClockCmd(APBPeriph_GPIOA, APBPeriph_GPIOA_CLOCK, ENABLE);
+ *
+ *     GPIO_InitTypeDef GPIO_InitStruct;
+ *     GPIO_StructInit(&GPIO_InitStruct);
+ *     GPIO_InitStruct.GPIO_Pin         = GPIO_GetPinBit(P0_0);
+ *     GPIO_InitStruct.GPIO_Dir         = GPIO_DIR_IN;
+ *     GPIO_InitStruct.GPIO_OutPutMode  = GPIO_OUTPUT_PUSHPULL;
+ *     GPIO_InitStruct.GPIO_ITCmd       = ENABLE;
+ *     GPIO_InitStruct.GPIO_ITTrigger   = GPIO_INT_TRIGGER_EDGE;
+ *     GPIO_InitStruct.GPIO_ITPolarity  = GPIO_INT_POLARITY_ACTIVE_LOW;
+ *     GPIO_InitStruct.GPIO_ITDebounce  = GPIO_INT_DEBOUNCE_ENABLE;
+ *     GPIO_InitStruct.GPIO_DebounceClkSource = GPIO_DEBOUNCE_32K;
+ *     GPIO_InitStruct.GPIO_DebounceClkDiv    = GPIO_DEBOUNCE_DIVIDER_1;
+ *     GPIO_InitStruct.GPIO_DebounceCntLimit  = 20;
+ *     GPIO_Init(GPIOA, &GPIO_InitStruct);
+ *
+ *     NVIC_InitTypeDef NVIC_InitStruct;
+ *     NVIC_InitStruct.NVIC_IRQChannel = GPIOA0_IRQn;
+ *     NVIC_InitStruct.NVIC_IRQChannelPriority = 3;
+ *     NVIC_InitStruct.NVIC_IRQChannelCmd = ENABLE;
+ *     NVIC_Init(&NVIC_InitStruct);
+
+ *     GPIO_MaskINTConfig(GPIOA, GPIO_GetPinBit(P0_0), DISABLE);
+ *     GPIO_INTConfig(GPIOA, GPIO_GetPinBit(P0_0), ENABLE);
+ * }
+ * \endcode
+ */
+void GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_InitStruct);
+
+/**
+ * \brief    Fill each GPIO_InitStruct member with its default value.
+ *
+ * \note The default settings for the GPIO_InitStruct member are shown in the following table:
+ *       | GPIO_InitStruct member          | Default value                         |
+ *       |:-------------------------------:|:-------------------------------------:|
+ *       | GPIO_Pin                        | \ref GPIO_Pin_All                     |
+ *       | GPIO_Dir                        | \ref GPIO_DIR_IN                      |
+ *       | GPIO_OutPutMode                 | \ref GPIO_OUTPUT_PUSHPULL             |
+ *       | GPIO_ITCmd                      | DISABLE                               |
+ *       | GPIO_ITTrigger                  | \ref GPIO_INT_TRIGGER_LEVEL           |
+ *       | GPIO_ITPolarity                 | \ref GPIO_INT_POLARITY_ACTIVE_LOW     |
+ *       | GPIO_ITDebounce                 | \ref GPIO_INT_DEBOUNCE_DISABLE        |
+ *       | GPIO_DebounceClkSource          | \ref GPIO_DEBOUNCE_32K                |
+ *       | GPIO_DebounceClkDiv             | \ref GPIO_DEBOUNCE_DIVIDER_1          |
+ *       | GPIO_DebounceCntLimit           | 32                                    |
+ *
+ * \param[in] GPIO_InitStruct  Pointer to a GPIO_InitTypeDef structure which will be initialized.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_gpio_init(void)
+ * {
+ *     RCC_PeriphClockCmd(APBPeriph_GPIOA, APBPeriph_GPIOA_CLOCK, ENABLE);
+ *
+ *     GPIO_InitTypeDef GPIO_InitStruct;
+ *     GPIO_StructInit(&GPIO_InitStruct);
+ *     GPIO_InitStruct.GPIO_Pin        = GPIO_GetPinBit(P0_0);
+ *     GPIO_InitStruct.GPIO_Dir        = GPIO_DIR_IN;
+ *     GPIO_InitStruct.GPIO_OutPutMode = GPIO_OUTPUT_PUSHPULL;
+ *     GPIO_InitStruct.GPIO_ITCmd      = ENABLE;
+ *     GPIO_InitStruct.GPIO_ITTrigger  = GPIO_INT_TRIGGER_EDGE;
+ *     GPIO_InitStruct.GPIO_ITPolarity = GPIO_INT_POLARITY_ACTIVE_LOW;
+ *     GPIO_InitStruct.GPIO_ITDebounce  = GPIO_INT_DEBOUNCE_ENABLE;
+ *     GPIO_InitStruct.GPIO_DebounceClkSource = GPIO_DEBOUNCE_32K;
+ *     GPIO_InitStruct.GPIO_DebounceClkDiv    = GPIO_DEBOUNCE_DIVIDER_1;
+ *     GPIO_InitStruct.GPIO_DebounceCntLimit  = 20;
+ *     GPIO_Init(GPIOA, &GPIO_InitStruct);
+ * }
+ * \endcode
+ */
+void GPIO_StructInit(GPIO_InitTypeDef *GPIO_InitStruct);
+
+/**
+ * \brief   Enable or disable the specified GPIO pin interrupt.
+ *
+ * \param[in] GPIOx     Select the GPIO peripheral. Refer to \ref GPIO_Declaration.
+ * \param[in] GPIO_Pin  Specify the GPIO pins to be configured.
+ *                      This parameter can be one of GPIO_Pin where can be 0~31.
+ * \param[in] NewState  New state of the GPIOx interrupt.
+ *                      This parameter can be one of the following values:
+ *                      - ENABLE: Enable the interrupt of the specified GPIO pin.
+ *                      - DISABLE: Disable the interrupt of the specified GPIO pin.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_gpio_init(void)
+ * {
+ *     RCC_PeriphClockCmd(APBPeriph_GPIOA, APBPeriph_GPIOA_CLOCK, ENABLE);
+ *
+ *     GPIO_InitTypeDef GPIO_InitStruct;
+ *     GPIO_StructInit(&GPIO_InitStruct);
+ *     GPIO_InitStruct.GPIO_Pin         = GPIO_GetPinBit(P0_0);
+ *     GPIO_InitStruct.GPIO_Dir         = GPIO_DIR_IN;
+ *     GPIO_InitStruct.GPIO_OutPutMode  = GPIO_OUTPUT_PUSHPULL;
+ *     GPIO_InitStruct.GPIO_ITCmd       = ENABLE;
+ *     GPIO_InitStruct.GPIO_ITTrigger   = GPIO_INT_TRIGGER_EDGE;
+ *     GPIO_InitStruct.GPIO_ITPolarity  = GPIO_INT_POLARITY_ACTIVE_LOW;
+ *     GPIO_InitStruct.GPIO_ITDebounce  = GPIO_INT_DEBOUNCE_ENABLE;
+ *     GPIO_InitStruct.GPIO_DebounceClkSource = GPIO_DEBOUNCE_32K;
+ *     GPIO_InitStruct.GPIO_DebounceClkDiv    = GPIO_DEBOUNCE_DIVIDER_1;
+ *     GPIO_InitStruct.GPIO_DebounceCntLimit  = 20;
+ *     GPIO_Init(GPIOA, &GPIO_InitStruct);
+ *
+ *     NVIC_InitTypeDef NVIC_InitStruct;
+ *     NVIC_InitStruct.NVIC_IRQChannel = GPIOA0_IRQn;
+ *     NVIC_InitStruct.NVIC_IRQChannelPriority = 3;
+ *     NVIC_InitStruct.NVIC_IRQChannelCmd = ENABLE;
+ *     NVIC_Init(&NVIC_InitStruct);
+
+ *     GPIO_MaskINTConfig(GPIOA, GPIO_GetPinBit(P0_0), DISABLE);
+ *     GPIO_INTConfig(GPIOA, GPIO_GetPinBit(P0_0), ENABLE);
+ * }
+ * \endcode
+ */
+void GPIO_INTConfig(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin, FunctionalState NewState);
+
+
+/**
+ * \brief   Clear the specified GPIO pin interrupt pending bit.
+ *
+ * \param[in] GPIOx     Select the GPIO peripheral. Refer to \ref GPIO_Declaration.
+ * \param[in] GPIO_Pin  Specify the GPIO pins to be configured.
+ *                      This parameter can be one of GPIO_Pin where can be 0~31.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void gpio_demo(void)
+ * {
+ *     driver_gpio_init();
+ * }
+ *
+ * void GPIOA0_Handler(void)
+ * {
+ *     GPIO_INTConfig(GPIOA, GPIO_GetPinBit(P0_0), DISABLE);
+ *     GPIO_MaskINTConfig(GPIOA, GPIO_GetPinBit(P0_0), ENABLE);
+ *     //Add user code here.
+ *     GPIO_ClearINTPendingBit(GPIOA, GPIO_GetPinBit(P0_0));
+ *     GPIO_MaskINTConfig(GPIOA, GPIO_GetPinBit(P0_0), DISABLE);
+ *     GPIO_INTConfig(GPIOA, GPIO_GetPinBit(P0_0), ENABLE);
+}
+ * \endcode
+ */
+void GPIO_ClearINTPendingBit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin);
+
+
+/**
+ * \brief   Mask or unmask the specified GPIO pin interrupt.
+ *
+ * \param[in] GPIOx     Select the GPIO peripheral. Refer to \ref GPIO_Declaration.
+ * \param[in] GPIO_Pin  Specify the GPIO pins to be configured.
+ *                      This parameter can be one of GPIO_Pin where can be 0~31.
+ * \param[in] NewState  Mask or unmask interrupt.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ *
+ * void gpio_demo(void)
+ * {
+ *     driver_gpio_init();
+ * }
+ *
+ * void GPIOA0_Handler(void)
+ * {
+ *     GPIO_INTConfig(GPIOA, GPIO_GetPinBit(P0_0), DISABLE);
+ *     GPIO_MaskINTConfig(GPIOA, GPIO_GetPinBit(P0_0), ENABLE);
+ *
+ *     //Add user code here.
+ *
+ *     GPIO_ClearINTPendingBit(GPIOA, GPIO_GetPinBit(P0_0));
+ *     GPIO_MaskINTConfig(GPIOA, GPIO_GetPinBit(P0_0), DISABLE);
+ *     GPIO_INTConfig(GPIOA, GPIO_GetPinBit(P0_0), ENABLE);
+ * }
+ * \endcode
+ */
+void GPIO_MaskINTConfig(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin, FunctionalState NewState);
+
+/**
+ * \brief   Get GPIO group through the given pad.
+ *
+ * \param[in] Pin_num  Pin number to be configured. Refer to \ref Pin_Number.
+ *
+ * \return  GPIOx(x is 0~31) value. Refer to \ref GPIO_Declaration.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ *
+ * void gpio_demo(void)
+ * {
+ *      GPIO_TypeDef gpio_port = GPIO_GetPort(P0_0);
+ *      //result: gpio_port is GPIOA
+ * }
+ *
+ * \endcode
+ */
+GPIO_TypeDef *GPIO_GetPort(uint8_t Pin_num);
+
+/**
+ * \brief   Get the GPIO_Pin (GPIO0 ~ GPIO31) through the given PAD num.
+ *
+ * \param[in] Pin_num  Pin number to be configured. Refer to \ref Pin_Number.
+ *
+ * \return  GPIOx(x is 0~31) value. Refer to \ref GPIO_Declaration.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void gpio_demo(void)
+ * {
+ *     uint32_t gpio_pin = GPIO_GetPinBit(P0_0);
+ *     //result: gpio_pin is GPIO_Pin_0
+ * }
+ * \endcode
+ */
+uint32_t GPIO_GetPinBit(uint8_t Pin_num);
+
+/**
+ * \brief   Get GPIO value ( \ref GPIO_Declaration ) through the given pad.
+ *
+ * \param[in] Pin_num  Pin number to be configured. Refer to \ref Pin_Number.
+ *
+ * \return  GPIOx(x is 0~31) value.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void gpio_demo(void)
+ * {
+ *     uint8_t gpio_num = GPIO_GetNum(P0_0);
+ *     //result: gpio_num = 0, i.e. GPIOA0.
+ * }
+ * \endcode
+ */
+uint8_t GPIO_GetNum(uint8_t Pin_num);
+
+/**
+ * \brief   Enable or disable the debounce counter function and clock.
+ *
+ * \param[in] GPIOx     Select the GPIO peripheral. Refer to \ref GPIO_Declaration.
+ * \param[in] GPIO_Pin  Specify the GPIO pins to be configured.
+ *                      This parameter can be one of GPIO_Pin where can be 0~31..
+ * \param[in] NewState  NewState of GPIO debounce counter function and clock.
+ *                      - ENABLE: Enable debounce counter function and clock of the specified pin.
+ *                      - DISABLE: Reset the counter and output of external debounce.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void gpio_demo(void)
+ * {
+ *     GPIO_ExtDebCmd(GPIOA, GPIO_GetPinBit(P0_0), ENABLE);
+ * }
+ * \endcode
+ */
+void GPIO_ExtDebCmd(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin, FunctionalState NewState);
+
+/**
+ * \brief  Set GPIO debounce parameters.
+ *
+ * \param[in]  GPIOx                  where x can be A to D to select the GPIO peripheral.
+ * \param[in]  GPIO_Pin               Specify the GPIO pins to be configured.
+ *                                    This parameter can be one of GPIO_Pin where can be 0~31.
+ * \param[in]  GPIO_DebounceClkDiv    Debounce clock divider selection.
+ * \param[in]  GPIO_DebounceCntLimit  Debounce time can be calculated by count limit.
+ *                                    Debounce_time = (CntLimit + 1) * GPIO_DebounceClkSource/GPIO_DebounceClkDiv.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void gpio_demo(void)
+ * {
+ *     GPIO_ExtDebUpdate(GPIOA, GPIO_GetPinBit(P0_0), GPIO_DEBOUNCE_32K, GPIO_DEBOUNCE_DIVIDER_1, 20);
+ * }
+ * \endcode
+ */
+void GPIO_ExtDebUpdate(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin,
+                       GPIODebounceSrc_TypeDef GPIO_DebounceClkSource,
+                       GPIODebounceDiv_TypeDef GPIO_DebounceClkDiv, uint8_t GPIO_DebounceCntLimit);
+
+/**
+ * \brief   Read the specified input pin.
+ *
+ * \param[in] GPIOx     Select the GPIO peripheral. Refer to \ref GPIO_Declaration.
+ * \param[in] GPIO_Pin  Specify the port bit to read.
+ *                      This parameter can be \ref GPIO_Pin where can be 0~31.
+ *
+ * \return  GPIO input port pin value.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void gpio_demo(void)
+ * {
+ *     uint8_t input_bit = GPIO_ReadInputDataBit(GPIOA, GPIO_GetPinBit(P0_0));
+ * }
+ * \endcode
+ */
+uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin);
+
+/**
+ * \brief  Read value of all GPIO input data.
+ *
+ * \param[in] GPIOx  Select the GPIO peripheral. Refer to \ref GPIO_Declaration.
+ *
+ * \return GPIO input data port value.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void gpio_demo(void)
+ * {
+ *     uint32_t input_data = GPIO_ReadInputData(GPIOA);
+ * }
+ * \endcode
+ */
+uint32_t GPIO_ReadInputData(GPIO_TypeDef *GPIOx);
+
+/**
+ * \brief   Read the specified output port pin.
+ *
+ * \param[in] GPIOx     Select the GPIO peripheral. Refer to \ref GPIO_Declaration.
+ * \param[in] GPIO_Pin  Specify the port bit to read.
+ *                      This parameter can be GPIO_Pin where can be 0~31.
+ *
+ * \return GPIO output port pin value.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void gpio_demo(void)
+ * {
+ *     uint8_t output_bit = GPIO_ReadOutputDataBit(GPIOA, GPIO_GetPinBit(P0_0));
+ * }
+ * \endcode
+ */
+uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin);
+
+/**
+ * \brief   Read value of all GPIO output data port.
+ *
+ * \param[in] GPIOx  Select the GPIO peripheral. Refer to \ref GPIO_Declaration.
+ *
+ * \return  GPIO output data port value.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void gpio_demo(void)
+ * {
+ *     uint32_t output_data = GPIO_ReadOutputData(GPIOA);
+ * }
+ * \endcode
+ */
+uint32_t GPIO_ReadOutputData(GPIO_TypeDef *GPIOx);
+
+/**
+ * \brief   Set the selected data port bit.
+ *
+ * \param[in] GPIOx     Select the GPIO peripheral. Refer to \ref GPIO_Declaration.
+ * \param[in] GPIO_Pin  Specify the port bit to be written.
+ *                      This parameter can be GPIO_Pin_x where x can be 0~31 or GPIO_Pin_All.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void gpio_demo(void)
+ * {
+ *     GPIO_SetBits(GPIOA, GPIO_GetPinBit(P0_0));
+ * }
+ * \endcode
+ */
+void GPIO_SetBits(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin);
+
+/**
+ * \brief   Reset the selected data port bit.
+ *
+ * \param[in] GPIOx     Select the GPIO peripheral. Refer to \ref GPIO_Declaration.
+ * \param[in] GPIO_Pin  Specify the port bits to be written.
+ *                      This parameter can be GPIO_Pin_0 to GPIO_Pin_31 or GPIO_Pin_All.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void gpio_demo(void)
+ * {
+ *     GPIO_ResetBits(GPIOA, GPIO_GetPinBit(P0_0));
+ * }
+ * \endcode
+ */
+void GPIO_ResetBits(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin);
+
+/**
+ * \brief  Set or clear the selected data port bit.
+ *
+ * \param[in] GPIOx     Select the GPIO peripheral. Refer to \ref GPIO_Declaration.
+ * \param[in] GPIO_Pin  Specify the port bit to be written.
+ *                      This parameter can be one of GPIO_Pin where can be 0~31.
+ * \param[in] BitVal    Specify the value to be written to the selected bit.
+ *                      This parameter can be one of the BitAction enum values:
+ *                      - Bit_RESET: To clear the port pin.
+ *                      - Bit_SET: To set the port pin.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void gpio_demo(void)
+ * {
+ *     GPIO_WriteBit(GPIOA, GPIO_GetPinBit(P0_0), Bit_SET);
+ * }
+ * \endcode
+ */
+void GPIO_WriteBit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin, BitAction BitVal);
+
+/**
+ * \brief   Set or clear data port.
+ *
+ * \param[in] GPIOx    Select the GPIO peripheral. Refer to \ref GPIO_Declaration.
+ * \param[in] PortVal  Specify the value to be written to the selected bit.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void gpio_demo(void)
+ * {
+ *     GPIO_Write(GPIOA, 0xFFFFFFFF);
+ * }
+ * \endcode
+ */
+void GPIO_Write(GPIO_TypeDef *GPIOx, uint32_t PortVal);
+
+
+/**
+ * \brief  Get GPIO interrupt status.
+ *
+ * \param[in] GPIOx     Select the GPIO peripheral. Refer to \ref GPIO_Declaration.
+ * \param[in] GPIO_Pin  Specify the GPIO pins to be configured.
+ *                      This parameter can be one of GPIO_Pin where can be 0~31.
+ *
+ * \return The new state of interrupt status (SET or RESET).
+ *         - SET: The interrupt status is set.
+ *         - RESET: The interrupt status has not been set.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void gpio_demo(void)
+ * {
+ *     ITStatus int_status = GPIO_GetINTStatus(GPIOA, GPIO_GetPinBit(P0_0));
+ * }
+ * \endcode
+ */
+ITStatus GPIO_GetINTStatus(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin);
+
+/**
+ * \brief  Specify the direction for the selected pins.
+ *
+ * \param[in] GPIOx        Select the GPIO peripheral. Refer to \ref GPIO_Declaration.
+ * \param[in] GPIO_PinBit  Specify the GPIO pins to be configured, Refer to \ref GPIO_Pins_Define.
+ * \param[in] GPIO_Dir     Set the GPIO direction.
+ *                         This parameter can be one of the following values:
+ *                         - GPIO_DIR_IN: The direction is input.
+ *                         - GPIO_DIR_OUT: The direction is output.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void gpio_demo(void)
+ * {
+ *     GPIO_SetDirection(GPIOA, GPIO_GetPinBit(P3_0), GPIO_DIR_IN);
+ * }
+ * \endcode
+ */
+void GPIO_SetDirection(GPIO_TypeDef *GPIOx, uint32_t GPIO_PinBit,
+                       GPIODir_TypeDef GPIO_Dir);
+
+/**
+ * \brief  Set GPIO output mode.
+ *
+ * \param[in] GPIOx            Select the GPIO peripheral. Refer to \ref GPIO_Declaration.
+ * \param[in] GPIO_Pin         Specify the GPIO pins to be configured.Refer to \ref GPIO_Pins_Define.
+ * \param[in] GPIO_OutputMode  Specify the output mode to be set.
+ *                             This parameter can be one of the \ref GPIO_Output_Mode enum values:
+ *                             - GPIO_OUTPUT_OPENDRAIN: Setting Output push-pull Mode.
+ *                             - GPIO_OUTPUT_PUSHPULL: Setting Output open-drain Mode.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void gpio_demo(void)
+ * {
+ *     GPIO_SetOutputMode(GPIOA, GPIO_GetPinBit(P0_0), GPIO_OUTPUT_OPENDRAIN);
+ * }
+ * \endcode
+ */
+void GPIO_SetOutputMode(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin,
+                        GPIOOutputMode_TypeDef GPIO_OutputMode);
+
+/**
+ * \brief  Get GPIO pad status.
+ *
+ * \param[in] GPIO_Pin  Specify the GPIO pins to be configured.Refer to \ref GPIO_Pins_Define.
+ *
+ * \return  The new state of GPIO_Pad.
+ *          - SET: The GPIO pad has been set.
+ *          - RESET: Failed to set the GPIO pad.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void gpio_demo(void)
+ * {
+ *     FlagStatus status = GPIO_GetPadStatus(GPIOA, GPIO_GetPinBit(P0_0));
+ * }
+ * \endcode
+ */
+FlagStatus GPIO_GetPadStatus(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin);
+
+/**
+ * \brief  Set GPIO Interript Polarity.
+ *
+ * \param[in] GPIOx     Select the GPIO peripheral. Refer to \ref GPIO_Declaration.
+ * \param[in] GPIO_Pin  Specify the GPIO pins to be configured.Refer to \ref GPIO_Pins_Define.
+ * \param[in] int_type  Specify the polarity type to be set.
+ *                      This parameter can be one of the \ref GPIO_Interrupt_Polarity enum values:
+ *                      - GPIO_INT_POLARITY_ACTIVE_LOW: Setting interrupt to low active.
+ *                      - GPIO_INT_POLARITY_ACTIVE_HIGH: Setting interrupt to high active.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void GPIO_Init(void)
+ * {
+ *     GPIO_SetPolarity(GPIOx, GPIO_Pin, GPIO_INT_POLARITY_ACTIVE_LOW);
+ * }
+ * \endcode
+ */
+void GPIO_SetPolarity(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin,
+                      GPIOITPolarity_TypeDef int_type);
+
+#if (GPIO_SUPPORT_RAP_FUNCTION == 1)
+
+void GPIO_RAPQactiveCtrl(GPIO_TypeDef *GPIOx, uint32_t Qactive, FunctionalState NewState);
+
+void GPIO_RAPModeCmd(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin, FunctionalState NewState);
+
+void GPIO_TaskTrigger(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin, uint32_t Task);
+
+#endif
+
+/** End of GPIO_Exported_Functions
+  * \}
+  */
+
+/** End of GPIO
+  * \}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RTL_GPIO_H */
+
diff --git a/bee/drivers/gpio/src/device/rtl87x2g/rtl_gpio_def.h b/bee/drivers/gpio/src/device/rtl87x2g/rtl_gpio_def.h
new file mode 100644
index 00000000..4e1f3b71
--- /dev/null
+++ b/bee/drivers/gpio/src/device/rtl87x2g/rtl_gpio_def.h
@@ -0,0 +1,458 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef RTL_GPIO_DEF_H
+#define RTL_GPIO_DEF_H
+
+#include "utils/rtl_utils.h"
+#include "address_map.h"
+
+#ifdef  __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/*============================================================================*
+ *                          GPIO Defines
+ *============================================================================*/
+/** \defgroup GPIO        GPIO
+  * \brief
+  * \{
+  */
+
+/** \defgroup GPIO_Exported_Constants GPIO Exported Constants
+  * \brief
+  * \{
+  */
+
+/**
+ * \defgroup GPIO_Defines GPIO Defines
+ * \{
+ * \ingroup  GPIO_Exported_Constants
+ */
+#define GPIO_SUPPORT_SET_CONTROL_MODE                  (0) //!< The function is not supported.
+#define GPIO_SUPPORT_SWAP_DEB_PINBIT                   (1) //!< The function must be enabled when using GPIO debounce.
+#define GPIO_SUPPORT_LS_SYNC                           (1) //!< The function must be enabled when level-triggered interrupts occur.
+#define GPIO_SUPPORT_INT_BOTHEDGE                      (0) //!< The function is not supported.
+
+/** End of GPIO_Defines
+  * \}
+  */
+
+/** End of GPIO_Exported_Constants
+  * \}
+  */
+
+/** End of GPIO
+  * \}
+  */
+
+/*============================================================================*
+ *                         GPIO Registers Memory Map
+ *============================================================================*/
+typedef struct
+{
+    __IO uint32_t GPIO_DR;              /*!< 0x00 */
+    __IO uint32_t GPIO_DDR;             /*!< 0x04 */
+    __IO uint32_t RSVD[10];
+    __IO uint32_t GPIO_INT_EN;          /*!< 0x30 */
+    __IO uint32_t GPIO_INT_MASK;        /*!< 0x34 */
+    __IO uint32_t GPIO_INT_LV;          /*!< 0x38 */
+    __IO uint32_t RSVD1;
+    __I  uint32_t GPIO_INT_STS;         /*!< 0x40 */
+    __I  uint32_t GPIO_INT_RAW_STS;     /*!< 0x44 */
+    __IO uint32_t RSVD2;
+    __O  uint32_t GPIO_INT_CLR;         /*!< 0x4C */
+    __IO uint32_t RSVD3[4];
+    __IO uint32_t GPIO_LS_SYNC;         /*!< 0x60 */
+    __IO uint32_t RSVD4[39];
+    __IO uint32_t GPIO_OUT_MODE;        /*!< 0x100 */
+    __I  uint32_t GPIO_PAD_STATE;       /*!< 0x104 */
+    __IO uint32_t GPIO_EXT_DEB_POL_CTL; /*!< 0x108 */
+} GPIO_TypeDef;
+
+typedef struct
+{
+    __IO uint32_t GPIO_DEB_CLK_CTL[4];  /*!< 0x00 ~ 0x0C */
+    __IO uint32_t GPIO_DEB_FUN_CTL;     /*!< 0x10 */
+} GPIO_Debounce_TypeDef;
+
+/*============================================================================*
+ *                         GPIO Declaration
+ *============================================================================*/
+/** \defgroup GPIO        GPIO
+  * \brief
+  * \{
+  */
+
+/** \defgroup GPIO_Exported_Constants GPIO Exported Constants
+  * \brief
+  * \{
+  */
+
+/**
+ * \defgroup GPIO_Declaration GPIO Declaration
+ * \{
+ * \ingroup  GPIO_Exported_Constants
+ */
+
+#define GPIO               ((GPIO_TypeDef          *) GPIOA_REG_BASE)     //!< GPIO base address.
+#define GPIOA              ((GPIO_TypeDef          *) GPIOA_REG_BASE)     //!< GPIOA base address.
+#define GPIOB              ((GPIO_TypeDef          *) GPIOB_REG_BASE)     //!< GPIOB base address.
+#define GPIOA_DEB          ((GPIO_Debounce_TypeDef *) GPIOA_DEB_REG_BASE) //!< GPIOA_DEB base address.
+#define GPIOB_DEB          ((GPIO_Debounce_TypeDef *) GPIOB_DEB_REG_BASE) //!< GPIOB_DEB base address.
+
+/** End of GPIO_Declaration
+  * \}
+  */
+
+/** End of GPIO_Exported_Constants
+  * \}
+  */
+
+/** End of GPIO
+  * \}
+  */
+
+/*============================================================================*
+ *                         GPIO Private Types
+ *============================================================================*/
+typedef struct
+{
+    uint32_t gpio_reg[15];
+} GPIOStoreReg_Typedef;
+
+/*============================================================================*
+ *                         GPIO Registers and Field Descriptions
+ *============================================================================*/
+/* 0x00
+   31:0    R/W    gpio_swporta_dr         32'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t gpio_swporta_dr: 32;
+    } b;
+} GPIO_DR_TypeDef;
+
+
+
+/* 0x04
+   31:0    R/W    gpio_swporta_ddr        32'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t gpio_swporta_ddr: 32;
+    } b;
+} GPIO_DDR_TypeDef;
+
+
+/* 0x30
+   31:0    R/W    gpio_inten              32'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t gpio_inten: 32;
+    } b;
+} GPIO_INT_EN_TypeDef;
+
+
+
+/* 0x34
+   31:0    R/W    gpio_intmask            32'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t gpio_intmask: 32;
+    } b;
+} GPIO_INT_MASK_TypeDef;
+
+
+
+/* 0x38
+   31:0    R/W    gpio_inttype_level      32'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t gpio_inttype_level: 32;
+    } b;
+} GPIO_INT_LV_TypeDef;
+
+
+
+/* 0x40
+   31:0    R      gpio_intstatus          32'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        const uint32_t gpio_intstatus: 32;
+    } b;
+} GPIO_INT_STS_TypeDef;
+
+
+/* 0x44
+   31:0    R      gpio_raw_intstatus      32'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        const uint32_t gpio_raw_intstatus: 32;
+    } b;
+} GPIO_INT_RAW_STS_TypeDef;
+
+
+/* 0x4C
+   31:0    W      gpio_porta_eoi          32'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t gpio_porta_eoi: 32;
+    } b;
+} GPIO_INT_CLR_TypeDef;
+
+
+
+/* 0x60
+   0       R/W    gpio_ls_sync            1'h0
+   31:1    R/W    reserved                31'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t gpio_ls_sync: 1;
+        uint32_t reserved: 31;
+    } b;
+} GPIO_LS_SYNC_TypeDef;
+
+
+
+/* 0x100
+   31:0    R/W    gpio_output_mode        32'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t gpio_output_mode: 32;
+    } b;
+} GPIO_OUT_MODE_TypeDef;
+
+
+/* 0x104
+   31:0    R      gpio_pad_state          32'h0
+   31:0    R/W    gpio_external_porta     32'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        const uint32_t gpio_pad_state: 32;
+    } b;
+} GPIO_PAD_STATE_TypeDef;
+
+
+/* 0x108
+   31:0    R/W    gpio_polarity           32'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t gpio_polarity: 32;
+    } b;
+} GPIO_EXT_DEB_POL_CTL_TypeDef;
+
+/* 0x00 ~ 0x0C
+   7:0     R/W    GPIO_G_L_CNT_LIMIT      8'h1
+   8       R/W    GPIO_G_L_DEB_CLK_SEL    1'h0
+   11:9    R/W    GPIO_G_L_DEB_CLK_DIV    3'h0
+   12      R/W    GPIO_G_L_DEB_CNT_EN     1'b0
+   15:13   R/W    DUMMY                  3'h0
+   23:16   R/W    GPIO_G_H_CNT_LIMIT      8'h1
+   24      R/W    GPIO_G_H_DEB_CLK_SEL    1'h0
+   27:25   R/W    GPIO_G_H_DEB_CLK_DIV    3'h0
+   28      R/W    GPIO_G_H_DEB_CNT_EN     1'b0
+   31:29   R/W    DUMMY                  2'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t GPIO_G_L_CNT_LIMIT: 8;
+        uint32_t GPIO_G_L_DEB_CLK_SEL: 1;
+        uint32_t GPIO_G_L_DEB_CLK_DIV: 3;
+        uint32_t GPIO_G_L_DEB_CNT_EN: 1;
+        uint32_t reserved_1: 3;
+        uint32_t GPIO_G_H_CNT_LIMIT: 8;
+        uint32_t GPIO_G_H_DEB_CLK_SEL: 1;
+        uint32_t GPIO_G_H_DEB_CLK_DIV: 3;
+        uint32_t GPIO_G_H_DEB_CNT_EN: 1;
+        uint32_t reserved_0: 3;
+    } b;
+} GPIO_DEB_CLK_CTL_TypeDef;
+
+
+
+/* 0x10
+   31:0    R/W    GPIO_x_DEB_FUNC_EN     32'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t GPIO_x_DEB_FUNC_EN: 32;
+    } b;
+} GPIO_DEB_FUN_CTL_TypeDef;
+
+
+/*============================================================================*
+ *                          GPIO Constants
+ *============================================================================*/
+/** \defgroup GPIO        GPIO
+  * \brief
+  * \{
+  */
+
+/** \defgroup GPIO_Exported_Constants GPIO Exported Constants
+  * \brief
+  * \{
+  */
+
+
+/**
+ * \defgroup    GPIO_Debounce_Clock_Source GPIO Debounce Clock Source
+ * \{
+ * \ingroup     GPIO_Exported_Constants
+ */
+typedef enum
+{
+    GPIO_DEBOUNCE_32K = 0x0, //!< GPIO debounce clock source is 32KHz.
+    GPIO_DEBOUNCE_S11 = 0x1, //!< GPIO debounce clock source is S11_clk.
+} GPIODebounceSrc_TypeDef;
+
+#define IS_GPIO_DEBOUNCE_SRC_TYPE(TYPE) (((TYPE) == GPIO_DEBOUNCE_32K) || \
+                                         ((TYPE) == GPIO_DEBOUNCE_S11)) //!< Check if the input parameter is valid.
+
+/** End of GPIO_Debounce_Clock_Source
+  * \}
+  */
+
+/**
+ * \defgroup    GPIO_Debounce_Divider GPIO Debounce Divider
+ * \{
+ * \ingroup     GPIO_Exported_Constants
+ */
+typedef enum
+{
+    GPIO_DEBOUNCE_DIVIDER_1  = 0x0, //!< The debounce divider is 1.
+    GPIO_DEBOUNCE_DIVIDER_2  = 0x1, //!< The debounce divider is 2.
+    GPIO_DEBOUNCE_DIVIDER_4  = 0x2, //!< The debounce divider is 4.
+    GPIO_DEBOUNCE_DIVIDER_8  = 0x3, //!< The debounce divider is 8.
+    GPIO_DEBOUNCE_DIVIDER_16 = 0x4, //!< The debounce divider is 16.
+    GPIO_DEBOUNCE_DIVIDER_32 = 0x5, //!< The debounce divider is 32.
+    GPIO_DEBOUNCE_DIVIDER_40 = 0x6, //!< The debounce divider is 40.
+    GPIO_DEBOUNCE_DIVIDER_64 = 0x7, //!< The debounce divider is 64.
+} GPIODebounceDiv_TypeDef;
+
+#define IS_GPIO_DEBOUNCE_DIV_TYPE(TYPE) (((TYPE) == GPIO_DEBOUNCE_DIVIDER_1) || \
+                                         ((TYPE) == GPIO_DEBOUNCE_DIVIDER_2) || \
+                                         ((TYPE) == GPIO_DEBOUNCE_DIVIDER_4) || \
+                                         ((TYPE) == GPIO_DEBOUNCE_DIVIDER_8) || \
+                                         ((TYPE) == GPIO_DEBOUNCE_DIVIDER_16) || \
+                                         ((TYPE) == GPIO_DEBOUNCE_DIVIDER_32) || \
+                                         ((TYPE) == GPIO_DEBOUNCE_DIVIDER_40) || \
+                                         ((TYPE) == GPIO_DEBOUNCE_DIVIDER_64)) //!< Check if the input parameter is valid.
+
+/** End of GPIO_Debounce_Divider
+  * \}
+  */
+
+/**
+ * \defgroup GPIO_Constant_Wrapper GPIO Constant Wrapper
+ * \{
+ * \ingroup  GPIO_Exported_Constants
+ */
+#define GPIO_Mode               GPIO_Dir               //!< The macro is a wrapper for GPIO_Dir.
+#define GPIO_Mode_IN            GPIO_DIR_IN            //!< The macro is a wrapper for GPIO_DIR_IN.
+#define GPIO_Mode_OUT           GPIO_DIR_OUT           //!< The macro is a wrapper for GPIO_DIR_OUT.
+#define GPIO_MODE_IN            GPIO_DIR_IN            //!< The macro is a wrapper for GPIO_DIR_IN.
+#define GPIO_MODE_OUT           GPIO_DIR_OUT           //!< The macro is a wrapper for GPIO_DIR_OUT.
+#define GPIO_INT_Trigger_LEVEL  GPIO_INT_TRIGGER_LEVEL //!< The macro is a wrapper for GPIO_INT_TRIGGER_LEVEL.
+#define GPIO_INT_Trigger_EDGE   GPIO_INT_TRIGGER_EDGE  //!< The macro is a wrapper for GPIO_INT_TRIGGER_EDGE.
+
+/** End of GPIO_Constant_Wrapper
+  * \}
+  */
+
+/**
+ * \defgroup GPIO_API_Wrapper GPIO API Wrapper
+ * \{
+ * \ingroup  GPIO_Exported_Constants
+ */
+#define GPIO_GetPin             GPIO_GetPinBit         //!< The macro is a wrapper for GPIO_GetPinBit.
+#define GPIO_DBClkCmd           GPIO_ExtDebCmd         //!< The macro is a wrapper for GPIO_ExtDebCmd.
+#define GPIO_SetDebounceTime    GPIO_ExtDebUpdate      //!< The macro is a wrapper for GPIO_ExtDebUpdate.
+#define GPIO_SetITPolarity      GPIO_SetPolarity       //!< The macro is a wrapper for GPIO_SetPolarity.
+
+/** End of GPIO_API_Wrapper
+  * \}
+  */
+
+/** End of GPIO_Exported_Constants
+  * \}
+  */
+
+/** End of GPIO
+  * \}
+  */
+
+#ifdef  __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* RTL_GPIO_DEF_H */
diff --git a/bee/drivers/gpio/src/device/rtl87x2j/rtl87x2j_gpio.c b/bee/drivers/gpio/src/device/rtl87x2j/rtl87x2j_gpio.c
new file mode 100644
index 00000000..771235f4
--- /dev/null
+++ b/bee/drivers/gpio/src/device/rtl87x2j/rtl87x2j_gpio.c
@@ -0,0 +1,368 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *                           Header Files
+ *============================================================================*/
+#include "rtl_gpio.h"
+
+/*============================================================================*
+ *                           Private Defines
+ *============================================================================*/
+#define GPIO_CLOCK_AUTO_MODE_CONFIG_AUTOMATIC       (0x00)
+#define GPIO_CLOCK_AUTO_MODE_CONFIG_ALWAYSRUN       (0xFF)//Force off 0xAA
+
+/*============================================================================*
+ *                           Private Constant
+ *============================================================================*/
+const uint8_t gpio_mapping_table[TOTAL_PIN_NUM] =
+{
+    0,  1,  2,  3,      /*!< P0_0 P0_1 P0_2 P0_3 */
+    4,  5,  6,  7,      /*!< P0_4 P0_5 P0_6 P0_7 */
+    8,  9,  10, 11,     /*!< P1_0 P1_1 P1_6 P1_7 */
+    12, 13, 14, 15,     /*!< P2_0 P2_1 P2_2 P2_3 */
+    16, 17, 18, 19,     /*!< P2_4 P2_5 P2_6 P2_7 */
+    20, 21, 22, 23,     /*!< P3_0 P3_1 P3_2 P3_3 */
+    24, 25, 26, 27,     /*!< P3_4 P3_5 P3_6 P4_0 */
+    28, 29, 30, 31,     /*!< P4_1 P4_2 P4_3 MICBIAS */
+    32, 33, 34, 35,     /*!< P5_1 P5_2 P6_0 P6_1 */
+    36, 37, 38, 39,     /*!< P6_2 P6_3 P6_4 P6_5 */
+    40, 41, 42, 43,     /*!< P6_6 P6_7 P7_0 P7_1 */
+    44, 45, 46, 47,     /*!< SPIC_CSN SPIC_SCK SPIC_SI SPIC_SO */
+    48, 49,             /*!< SPIC_WEN SPIC_HOLDEN */
+};
+
+const uint32_t gpio_deb_table[13][4] =
+{
+    {BIT0,  BIT1,  BIT2,  BIT3},
+    {BIT4,  BIT8,  BIT9,  BIT7},
+    {BIT12, BIT13, BIT10, BIT11},
+    {BIT6,  BIT31, BIT14, BIT15},
+    {BIT16, BIT17, BIT18, BIT19},
+    {BIT20, BIT21, BIT22, BIT23},
+    {BIT24, BIT25, BIT26, BIT5},
+    {BIT28, BIT29, BIT30, BIT27},
+    {BIT0,  BIT1,  BIT2,  BIT3},
+    {BIT4,  BIT5,  BIT6,  BIT7},
+    {BIT8,  BIT9,  BIT10, BIT11},
+    {BIT12, BIT13, BIT14, BIT15},
+    {BIT16, BIT17, 0,       0}
+};
+/*============================================================================*
+ *                           Public Functions
+ *============================================================================*/
+uint32_t GPIO_SwapDebPinBit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
+{
+    uint32_t deb_bit = GPIO_Pin;
+
+#define SWAP_DEB_PIN_BIT(old_pin, new_pin) do {                       \
+        deb_bit &= ~BIT(new_pin);                                     \
+        deb_bit |= ((GPIO_Pin & BIT(old_pin)) >> old_pin) << new_pin; \
+    } while (0)
+
+    if (GPIOx == GPIOA)
+    {
+        SWAP_DEB_PIN_BIT(5,  27);
+        SWAP_DEB_PIN_BIT(6,  12);
+        SWAP_DEB_PIN_BIT(8,  5);
+        SWAP_DEB_PIN_BIT(9,  6);
+        SWAP_DEB_PIN_BIT(12, 8);
+        SWAP_DEB_PIN_BIT(13, 9);
+        SWAP_DEB_PIN_BIT(27, 31);
+        SWAP_DEB_PIN_BIT(31, 13);
+    }
+
+    return deb_bit;
+}
+
+/**
+  * \brief  Get GPIO GROUP through the given pad.
+  * \param  Pin_num: Pin number to be configured. \ref Pin_Number
+  * \return GPIOx: Select the GPIO peripheral. \ref GPIO_Declaration
+  */
+GPIO_TypeDef *GPIO_GetPort(uint8_t Pin_num)
+{
+    /* Check the parameters */
+    assert_param(IS_PIN_NUM(Pin_num));
+
+    uint8_t gpio_number = gpio_mapping_table[Pin_num];
+
+    if (gpio_number <= 31)
+    {
+        return GPIOA;
+    }
+    else if (gpio_number <= 63)
+    {
+        return GPIOB;
+    }
+    else
+    {
+        return 0;
+    }
+}
+
+/**
+  * \brief  Get the GPIO_Pin(GPIO0~GPIO31) through the given PAD num.
+  * \param  Pin_num: Pin number to be configured. \ref Pin_Number
+  * \return GPIOx(x is 0~31) value.
+  */
+uint32_t GPIO_GetPinBit(uint8_t Pin_num)
+{
+    /* Check the parameters */
+    assert_param(IS_PIN_NUM(Pin_num));
+
+    uint8_t gpio_number = gpio_mapping_table[Pin_num];
+
+    return BIT((gpio_number) & 0x1F);
+}
+
+
+/**
+  * \brief  Get GPIO value (GPIOA0 ~ GPIOB31) through the given pad.
+  * \param  Pin_num: Pin number to be configured. \ref Pin_Number
+  * \return GPIO value (GPIOA0 ~ GPIOB31).
+  */
+uint8_t GPIO_GetNum(uint8_t Pin_num)
+{
+    /* Check the parameters */
+    assert_param(IS_PIN_NUM(Pin_num));
+
+    return gpio_mapping_table[Pin_num];
+}
+
+/**
+  * \brief  Enable GPIO external debounce clock.
+  * \param  GPIOx: Select the GPIO peripheral. \ref GPIO_Declaration
+  * \param  GPIO_Pin: GPIO_Pin can be 0 to 31.
+  * \param  NewState: Disable or enable gpio debounce clock.
+  * \return None.
+  */
+void GPIO_ExtDebCmd(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin, FunctionalState NewState)
+{
+    uint8_t GPIO_Port_Offset = GPIOx == GPIOA ? 0 : 8;
+    uint32_t GPIO_Pin_Swap = GPIO_SwapDebPinBit(GPIOx, GPIO_Pin);
+
+    for (uint8_t i = 0; i < 8; i++)
+    {
+        if ((GPIO_Pin_Swap & ((uint32_t)0x0F << i * 4)) != 0)
+        {
+            if (NewState == ENABLE)
+            {
+                GPIOx->GPIO_EXT_DEB_FUNC_CTL &= ~(gpio_deb_table[i + GPIO_Port_Offset][0] |
+                                                  gpio_deb_table[i + GPIO_Port_Offset][1] |
+                                                  gpio_deb_table[i + GPIO_Port_Offset][2] |
+                                                  gpio_deb_table[i + GPIO_Port_Offset][3]);
+
+                for (uint8_t j = 0; j < 4; j++)
+                {
+                    if ((GPIO_Pin_Swap & (BIT(j) << (i * 4))) != 0)
+                    {
+                        GPIOx->GPIO_EXT_DEB_FUNC_CTL |= gpio_deb_table[i + GPIO_Port_Offset][j];
+                        break;
+                    }
+                }
+            }
+            else
+            {
+                for (uint8_t j = 0; j < 4; j++)
+                {
+                    if ((GPIO_Pin_Swap & (BIT(j) << (i * 4))) != 0)
+                    {
+                        GPIOx->GPIO_EXT_DEB_FUNC_CTL &= ~gpio_deb_table[i + GPIO_Port_Offset][j];
+                    }
+                }
+            }
+        }
+    }
+}
+
+/**
+  * \brief  Set GPIO debounce parameters.
+  * \param  GPIOx: Select the GPIO peripheral. \ref GPIO_Declaration
+  * \param  GPIO_Pin: GPIO_Pin can be 0 to 31.
+  * \param  GPIO_DebClockSrc: select debounce count clk source, can be S11 or 32KHz.
+  * \param  GPIO_DebClockDiv: divider selection.
+  * \param  GPIO_DebCountLimit: debounce time can be calculated by count limit.
+  * \return None.
+  */
+void GPIO_ExtDebUpdate(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin,
+                       GPIODebClockSrc_TypeDef GPIO_DebClockSrc,
+                       GPIODebClockDiv_TypeDef GPIO_DebClockDiv,
+                       uint8_t                 GPIO_DebCountLimit)
+{
+    uint32_t GPIO_Pin_Swap = GPIO_SwapDebPinBit(GPIOx, GPIO_Pin);
+
+    for (uint8_t i = 0; i < 8; i++)
+    {
+        if ((GPIO_Pin_Swap & ((uint32_t)0x0F << i * 4)) != 0)
+        {
+            GPIO_EXT_DEB_CLK_CTL_TypeDef gpio_deb = {.d32 = GPIOx->GPIO_EXT_DEB_CLK_CTL[i / 2]};
+            if (i % 2)
+            {
+                gpio_deb.b.gpio_h_cnt_limit = GPIO_DebCountLimit & 0xFF;
+                gpio_deb.b.gpio_h_deb_clk_div = GPIO_DebClockDiv;
+            }
+            else
+            {
+                gpio_deb.b.gpio_l_cnt_limit = GPIO_DebCountLimit & 0xFF;
+                gpio_deb.b.gpio_l_deb_clk_div = GPIO_DebClockDiv;
+            }
+            GPIOx->GPIO_EXT_DEB_CLK_CTL[i / 2] = gpio_deb.d32;
+        }
+    }
+}
+
+void GPIO_ExtPolarity(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin, GPIOPolarity_TypeDef Polarity)
+{
+    bool isRAPEnabled = ((GPIOx->GPIO_RAP_CTL & GPIO_Pin) == GPIO_Pin);
+
+    if (isRAPEnabled)
+    {
+        GPIO_RAPModeCmd(GPIOx, GPIO_Pin, DISABLE);
+    }
+    if (Polarity == GPIO_POLARITY_ACTIVE_LOW)
+    {
+        GPIOx->GPIO_EXT_DEB_POL_CTL &= (~GPIO_Pin);
+    }
+    else
+    {
+        GPIOx->GPIO_EXT_DEB_POL_CTL = GPIOx->GPIO_EXT_DEB_POL_CTL & (~GPIO_Pin) | GPIO_Pin;
+    }
+    if (isRAPEnabled)
+    {
+        GPIO_RAPModeCmd(GPIOx, GPIO_Pin, ENABLE);
+    }
+}
+
+void GPIO_ClockAutoModeCmd(GPIO_TypeDef *GPIOx, FunctionalState Newstate)
+{
+    if (Newstate == ENABLE)
+    {
+        GPIOx->GPIO_QACTIVE_MANUAL_CTRL = GPIO_CLOCK_AUTO_MODE_CONFIG_AUTOMATIC;
+    }
+    else
+    {
+        GPIOx->GPIO_QACTIVE_MANUAL_CTRL = GPIO_CLOCK_AUTO_MODE_CONFIG_ALWAYSRUN;
+    }
+
+    return;
+}
+
+void GPIO_DebounceTimeUs(uint32_t time_us, uint8_t *GPIO_DebounceCntLimit,
+                         uint8_t *GPIO_DebounceSrcDiv)
+{
+    uint8_t deb_div = 0;
+    for (deb_div = 0; deb_div <= 6 /* 0x7 is bypass divide */; deb_div++)
+    {
+        if (time_us <= ((1 << deb_div) * 8000))  /* (1 << 8) / (32000 / 1000 / 1000) = 8000 */
+        {
+            break;
+        }
+    }
+
+    *GPIO_DebounceCntLimit = time_us * 32 / 1000 / (1 << deb_div) - 1;
+    if (deb_div == 6)
+    {
+        deb_div = 7;
+    }
+    *GPIO_DebounceSrcDiv = deb_div;//deb_div;
+}
+
+/*============================================================================*
+ *                           EXTI Functions
+ *============================================================================*/
+static struct
+{
+    IRQ_Fun gpio_callback[64];
+} gpio_isr;
+
+static void GPIO_ISRUpdate(uint32_t irqn, IRQ_Fun isr_handler)
+{
+    gpio_isr.gpio_callback[irqn & 0xFF] = isr_handler;
+}
+
+void GPIOA_Handler(uint32_t mask)
+{
+    uint32_t real_interrupt_status = GPIOA->GPIO_INT_RAW_STS & mask ;
+    while (real_interrupt_status)
+    {
+        uint8_t idx = 31 - __builtin_clz(real_interrupt_status);
+        if (gpio_isr.gpio_callback[idx])
+        {
+            gpio_isr.gpio_callback[idx]();
+        }
+        real_interrupt_status &= ~BIT(idx);
+    }
+}
+
+void GPIOB_Handler(uint32_t mask)
+{
+    uint32_t real_interrupt_status = GPIOB->GPIO_INT_RAW_STS & mask;
+    while (real_interrupt_status)
+    {
+        uint8_t idx = 31 - __builtin_clz(real_interrupt_status);
+        if (gpio_isr.gpio_callback[idx + 32])
+        {
+            gpio_isr.gpio_callback[idx + 32]();
+        }
+        real_interrupt_status &= ~BIT(idx);
+    }
+}
+
+void GPIO0_7_ISR(void)
+{
+    GPIOA_Handler(0xFF);
+}
+
+void GPIO8_15_ISR(void)
+{
+    GPIOA_Handler(0xFF00);
+}
+
+void GPIO16_23_ISR(void)
+{
+    GPIOA_Handler(0xFF0000);
+}
+
+void GPIO24_31_ISR(void)
+{
+    GPIOA_Handler(0xFF000000);
+}
+
+void GPIO32_39_ISR(void)
+{
+    GPIOB_Handler(0xFF);
+}
+
+void GPIO40_47_ISR(void)
+{
+    GPIOB_Handler(0xFF00);
+}
+
+void GPIO48_55_ISR(void)
+{
+    GPIOB_Handler(0xFF0000);
+}
+
+void GPIO56_63_ISR(void)
+{
+    GPIOB_Handler(0xFF000000);
+}
+
+void GPIO_IRQInit(void)
+{
+    ram_vector_table_register(GPIOA0_7_IRQn, GPIO_ISRUpdate);
+    ram_vector_table_update(GPIOA0_7_IRQn,   GPIO0_7_ISR);
+    ram_vector_table_update(GPIOA8_15_IRQn,  GPIO8_15_ISR);
+    ram_vector_table_update(GPIOA16_23_IRQn, GPIO16_23_ISR);
+    ram_vector_table_update(GPIOA24_31_IRQn, GPIO24_31_ISR);
+    ram_vector_table_update(GPIOA32_39_IRQn, GPIO32_39_ISR);
+    ram_vector_table_update(GPIOA40_47_IRQn, GPIO40_47_ISR);
+    ram_vector_table_update(GPIOA48_55_IRQn, GPIO48_55_ISR);
+}
+
+
+
diff --git a/bee/drivers/gpio/src/device/rtl87x2j/rtl_gpio_def.h b/bee/drivers/gpio/src/device/rtl87x2j/rtl_gpio_def.h
new file mode 100644
index 00000000..d3d09e94
--- /dev/null
+++ b/bee/drivers/gpio/src/device/rtl87x2j/rtl_gpio_def.h
@@ -0,0 +1,630 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef RTL_GPIO_DEF_H
+#define RTL_GPIO_DEF_H
+
+#include "utils/rtl_utils.h"
+#include "address_map.h"
+#include "vector_table.h"
+
+#ifdef  __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/*============================================================================*
+ *                          GPIO Defines
+ *============================================================================*/
+/** \defgroup GPIO        GPIO
+  * \brief
+  * \{
+  */
+
+/** \defgroup GPIO_Exported_Constants GPIO Exported Constants
+  * \brief
+  * \{
+  */
+
+/**
+ * \defgroup GPIO_Defines GPIO Defines
+ * \{
+ * \ingroup  GPIO_Exported_Constants
+ */
+#define GPIO_SUPPORT_SET_CONTROL_MODE                  (0)
+#define GPIO_SUPPORT_LS_SYNC                           (0)
+#define GPIO_SUPPORT_BOTHEDGE                          (1)
+#define GPIO_SUPPORT_RAP_FUNCTION                      (1)
+#define GPIO_SUPPORT_AUTO_CLOCK                        (1)
+#define GPIO_SUPPORT_OUTPUT_MODE_SELECT                (1)
+
+/** End of GPIO_Defines
+  * \}
+  */
+
+/** End of GPIO_Exported_Constants
+  * \}
+  */
+
+/** End of GPIO
+  * \}
+  */
+
+/*============================================================================*
+ *                          GPIO Registers Memory Map
+ *============================================================================*/
+typedef struct
+{
+    __IO uint32_t GPIO_DR;                          /*!< 0x00 */
+    __IO uint32_t GPIO_DDR;                         /*!< 0x04 */
+    __IO uint32_t GPIO_SRC;                         /*!< 0x08 */
+    __IO uint32_t RSVD[9];
+    __IO uint32_t GPIO_INT_EN;                      /*!< 0x30 */
+    __IO uint32_t GPIO_INT_MASK;                    /*!< 0x34 */
+    __IO uint32_t GPIO_INT_LV;                      /*!< 0x38 */
+    __IO uint32_t RSVD1;
+    __I  uint32_t GPIO_INT_STS;                     /*!< 0x40 */
+    __I  uint32_t GPIO_INT_RAW_STS;                 /*!< 0x44 */
+    __IO uint32_t RSVD2;
+    __O  uint32_t GPIO_INT_CLR;                     /*!< 0x4C */
+    __IO uint32_t RSVD3[6];
+    __IO uint32_t GPIO_INT_BOTHEDGE;                /*!< 0x68 */
+    __IO uint32_t RSVD4[37];
+    __IO uint32_t GPIO_OUT_MODE;                    /*!< 0x100 */
+    __I  uint32_t GPIO_PAD_STATE;                   /*!< 0x104 */
+    __IO uint32_t GPIO_EXT_DEB_CLK_CTL[4];          /*!< 0x108 - 0x114*/
+    __IO uint32_t RSVD5[12];                        /*!< 0x118 - 0x144*/
+    __IO uint32_t GPIO_EXT_DEB_FUNC_CTL;            /*!< 0x148 */
+    __IO uint32_t GPIO_EXT_DEB_POL_CTL;             /*!< 0x14C */
+    __I  uint32_t GPIO_VERSION;                     /*!< 0x150 */
+    __IO uint32_t GPIO_RAP_CTL;                     /*!< 0x154 */
+    __O  uint32_t GPIO_RAP_TASK_DRSET;              /*!< 0x158 */
+    __O  uint32_t GPIO_RAP_TASK_DRCLR;              /*!< 0x15C */
+    __O  uint32_t GPIO_RAP_TASK_DRTOGGLE;           /*!< 0x160 */
+    __O  uint32_t RSVD6[5];                         /*!< 0x164 - 0x174*/
+    __IO uint32_t GPIO_QACTIVE_MANUAL_CTRL;         /*!< 0x178 */
+} GPIO_TypeDef;
+
+/*============================================================================*
+ *                          GPIO Declaration
+ *============================================================================*/
+/** \defgroup GPIO        GPIO
+  * \brief
+  * \{
+  */
+
+/** \defgroup GPIO_Exported_Constants GPIO Exported Constants
+  * \brief
+  * \{
+  */
+
+/** \defgroup GPIO_Declaration GPIO Declaration
+  * \brief
+  * \{
+  */
+#define GPIOA_REG_BASE     (GPIO0_BASE)
+#define GPIOB_REG_BASE     (GPIO0_BASE + 0x800)
+
+#define GPIO               ((GPIO_TypeDef *) GPIOA_REG_BASE)
+#define GPIOA              ((GPIO_TypeDef *) GPIOA_REG_BASE)
+#define GPIOB              ((GPIO_TypeDef *) GPIOB_REG_BASE)
+
+/** End of GPIO_Declaration
+  * \}
+  */
+
+/** \defgroup GPIO_IRQn GPIO IRQn
+  * \brief
+  * \{
+  */
+#ifdef GPIOA
+#define GPIOA0_IRQn         SUB_IRQ_DEF(GPIOA0_7_IRQn, 0)
+#define GPIOA1_IRQn         SUB_IRQ_DEF(GPIOA0_7_IRQn, 1)
+#define GPIOA2_IRQn         SUB_IRQ_DEF(GPIOA0_7_IRQn, 2)
+#define GPIOA3_IRQn         SUB_IRQ_DEF(GPIOA0_7_IRQn, 3)
+#define GPIOA4_IRQn         SUB_IRQ_DEF(GPIOA0_7_IRQn, 4)
+#define GPIOA5_IRQn         SUB_IRQ_DEF(GPIOA0_7_IRQn, 5)
+#define GPIOA6_IRQn         SUB_IRQ_DEF(GPIOA0_7_IRQn, 6)
+#define GPIOA7_IRQn         SUB_IRQ_DEF(GPIOA0_7_IRQn, 7)
+#define GPIOA8_IRQn         SUB_IRQ_DEF(GPIOA8_15_IRQn, 8)
+#define GPIOA9_IRQn         SUB_IRQ_DEF(GPIOA8_15_IRQn, 9)
+#define GPIOA10_IRQn        SUB_IRQ_DEF(GPIOA8_15_IRQn, 10)
+#define GPIOA11_IRQn        SUB_IRQ_DEF(GPIOA8_15_IRQn, 11)
+#define GPIOA12_IRQn        SUB_IRQ_DEF(GPIOA8_15_IRQn, 12)
+#define GPIOA13_IRQn        SUB_IRQ_DEF(GPIOA8_15_IRQn, 13)
+#define GPIOA14_IRQn        SUB_IRQ_DEF(GPIOA8_15_IRQn, 14)
+#define GPIOA15_IRQn        SUB_IRQ_DEF(GPIOA8_15_IRQn, 15)
+#define GPIOA16_IRQn        SUB_IRQ_DEF(GPIOA16_23_IRQn, 16)
+#define GPIOA17_IRQn        SUB_IRQ_DEF(GPIOA16_23_IRQn, 17)
+#define GPIOA18_IRQn        SUB_IRQ_DEF(GPIOA16_23_IRQn, 18)
+#define GPIOA19_IRQn        SUB_IRQ_DEF(GPIOA16_23_IRQn, 19)
+#define GPIOA20_IRQn        SUB_IRQ_DEF(GPIOA16_23_IRQn, 20)
+#define GPIOA21_IRQn        SUB_IRQ_DEF(GPIOA16_23_IRQn, 21)
+#define GPIOA22_IRQn        SUB_IRQ_DEF(GPIOA16_23_IRQn, 22)
+#define GPIOA23_IRQn        SUB_IRQ_DEF(GPIOA16_23_IRQn, 23)
+#define GPIOA24_IRQn        SUB_IRQ_DEF(GPIOA24_31_IRQn, 24)
+#define GPIOA25_IRQn        SUB_IRQ_DEF(GPIOA24_31_IRQn, 25)
+#define GPIOA26_IRQn        SUB_IRQ_DEF(GPIOA24_31_IRQn, 26)
+#define GPIOA27_IRQn        SUB_IRQ_DEF(GPIOA24_31_IRQn, 27)
+#define GPIOA28_IRQn        SUB_IRQ_DEF(GPIOA24_31_IRQn, 28)
+#define GPIOA29_IRQn        SUB_IRQ_DEF(GPIOA24_31_IRQn, 29)
+#define GPIOA30_IRQn        SUB_IRQ_DEF(GPIOA24_31_IRQn, 30)
+#define GPIOA31_IRQn        SUB_IRQ_DEF(GPIOA24_31_IRQn, 31)
+#endif
+#ifdef GPIOB
+#define GPIOB0_IRQn         SUB_IRQ_DEF(GPIOA32_39_IRQn, 32)
+#define GPIOB1_IRQn         SUB_IRQ_DEF(GPIOA32_39_IRQn, 33)
+#define GPIOB2_IRQn         SUB_IRQ_DEF(GPIOA32_39_IRQn, 34)
+#define GPIOB3_IRQn         SUB_IRQ_DEF(GPIOA32_39_IRQn, 35)
+#define GPIOB4_IRQn         SUB_IRQ_DEF(GPIOA32_39_IRQn, 36)
+#define GPIOB5_IRQn         SUB_IRQ_DEF(GPIOA32_39_IRQn, 37)
+#define GPIOB6_IRQn         SUB_IRQ_DEF(GPIOA32_39_IRQn, 38)
+#define GPIOB7_IRQn         SUB_IRQ_DEF(GPIOA32_39_IRQn, 39)
+#define GPIOB8_IRQn         SUB_IRQ_DEF(GPIOA40_47_IRQn, 40)
+#define GPIOB9_IRQn         SUB_IRQ_DEF(GPIOA40_47_IRQn, 41)
+#define GPIOB10_IRQn        SUB_IRQ_DEF(GPIOA40_47_IRQn, 42)
+#define GPIOB11_IRQn        SUB_IRQ_DEF(GPIOA40_47_IRQn, 43)
+#define GPIOB12_IRQn        SUB_IRQ_DEF(GPIOA40_47_IRQn, 44)
+#define GPIOB13_IRQn        SUB_IRQ_DEF(GPIOA40_47_IRQn, 45)
+#define GPIOB14_IRQn        SUB_IRQ_DEF(GPIOA40_47_IRQn, 46)
+#define GPIOB15_IRQn        SUB_IRQ_DEF(GPIOA40_47_IRQn, 47)
+#define GPIOB16_IRQn        SUB_IRQ_DEF(GPIOA48_55_IRQn, 48)
+#define GPIOB17_IRQn        SUB_IRQ_DEF(GPIOA48_55_IRQn, 49)
+#define GPIOB18_IRQn        SUB_IRQ_DEF(GPIOA48_55_IRQn, 50)
+#define GPIOB19_IRQn        SUB_IRQ_DEF(GPIOA48_55_IRQn, 51)
+#define GPIOB20_IRQn        SUB_IRQ_DEF(GPIOA48_55_IRQn, 52)
+#define GPIOB21_IRQn        SUB_IRQ_DEF(GPIOA48_55_IRQn, 53)
+#define GPIOB22_IRQn        SUB_IRQ_DEF(GPIOA48_55_IRQn, 54)
+#define GPIOB23_IRQn        SUB_IRQ_DEF(GPIOA48_55_IRQn, 55)
+#endif
+
+/** End of GPIO_IRQn
+  * \}
+  */
+
+/** End of GPIO_Exported_Constants
+  * \}
+  */
+
+/** End of GPIO
+  * \}
+  */
+
+/*============================================================================*
+ *                          GPIO Private Types
+ *============================================================================*/
+typedef struct
+{
+    uint32_t gpio_reg[15];
+} GPIOStoreReg_Typedef;
+
+/*============================================================================*
+ *                          GPIO Registers and Field Descriptions
+ *============================================================================*/
+/* 0x00
+   31:0    R/W    gpio_swporta_dr             32'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t gpio_swporta_dr: 32;
+    } b;
+} GPIO_DR_TypeDef;
+
+
+/* 0x04
+   31:0    R/W    gpio_swporta_ddr            32'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t gpio_swporta_ddr: 32;
+    } b;
+} GPIO_DDR_TypeDef;
+
+
+/* 0x08
+   31:0    R/W    gpio_swporta_ctl            32'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t gpio_swporta_ctl: 32;
+    } b;
+} GPIO_SRC_TypeDef;
+
+
+/* 0x30
+   31:0    R/W    gpio_inten                  32'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t gpio_inten: 32;
+    } b;
+} GPIO_INT_EN_TypeDef;
+
+
+/* 0x34
+   31:0    R/W    gpio_intmask                32'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t gpio_intmask: 32;
+    } b;
+} GPIO_INT_MASK_TypeDef;
+
+
+/* 0x38
+   31:0    R/W    gpio_inttype_level          32'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t gpio_inttype_level: 32;
+    } b;
+} GPIO_INT_LV_TypeDef;
+
+
+/* 0x40
+   31:0    R      gpio_intstatus              32'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t gpio_intstatus: 32;
+    } b;
+} GPIO_INT_STS_TypeDef;
+
+
+/* 0x44
+   31:0    R      gpio_raw_intstatus          32'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t gpio_raw_intstatus: 32;
+    } b;
+} GPIO_INT_RAW_STS_TypeDef;
+
+
+/* 0x4C
+   31:0    W      gpio_porta_eoi              32'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t gpio_porta_eoi: 32;
+    } b;
+} GPIO_INT_CLR_TypeDef;
+
+
+/* 0x68
+   31:0    R/W    gpio_int_bothedge           32'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t gpio_int_bothedge: 32;
+    } b;
+} GPIO_INT_BOTHEDGE_TypeDef;
+
+
+/* 0x100
+   31:0    R/W    gpio_output_mode            32'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t gpio_output_mode: 32;
+    } b;
+} GPIO_OUT_MODE_TypeDef;
+
+
+/* 0x104
+   31:0    R      gpio_pad_state              32'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t gpio_pad_state: 32;
+    } b;
+} GPIO_PAD_STATE_TypeDef;
+
+
+/* 0x108 - 0x114
+   7:0     R/W    gpio_l_cnt_limit   8'h1
+   8       R      reserved8          1'h0
+   11:9    R/W    gpio_l_deb_clk_div 3'h0
+   15:12   R      reserved15_12      4'h0
+   23:16   R/W    gpio_h_cnt_limit   8'h1
+   24      R      reserved24         1'h0
+   27:25   R/W    gpio_h_deb_clk_div 3'h0
+   31:28   R      reserved31_28      4'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t gpio_l_cnt_limit: 8;
+        const uint32_t reserved_3: 1;
+        uint32_t gpio_l_deb_clk_div: 3;
+        const uint32_t reserved_2: 4;
+        uint32_t gpio_h_cnt_limit: 8;
+        const uint32_t reserved_1: 1;
+        uint32_t gpio_h_deb_clk_div: 3;
+        const uint32_t reserved_0: 4;
+    } b;
+} GPIO_EXT_DEB_CLK_CTL_TypeDef;
+
+
+/* 0x148
+   31:0    R/W    gpio_x_deb_func_en          32'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t gpio_x_deb_func_en: 32;
+    } b;
+} GPIO_EXT_DEB_FUNC_CTL_TypeDef;
+
+
+/* 0x14C
+   31:0    R/W    gpio_polarity               32'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t gpio_polarity: 32;
+    } b;
+} GPIO_EXT_DEB_POL_CTL_TypeDef;
+
+
+/* 0x150
+   31:0    R      gpio_version                32'h2402210A
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t gpio_version: 32;
+    } b;
+} GPIO_VERSION_TypeDef;
+
+
+/* 0x154
+   31:0    R/W    gpio_rap_mode               32'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t gpio_rap_mode: 32;
+    } b;
+} GPIO_RAP_CTL_TypeDef;
+
+
+/* 0x158
+   31:0    WAC    gpio_task_drset             32'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t gpio_task_drset: 32;
+    } b;
+} GPIO_RAP_TASK_DRSET_TypeDef;
+
+
+/* 0x15C
+   31:0    WAC    gpio_task_drclr             32'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t gpio_task_drclr: 32;
+    } b;
+} GPIO_RAP_TASK_DRCLR_TypeDef;
+
+
+/* 0x160
+   31:0    WAC    gpio_task_drtoggle          32'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t gpio_task_drtoggle: 32;
+    } b;
+} GPIO_RAP_TASK_DRTOGGLE_TypeDef;
+
+
+/* 0x178
+   0       R/W    pclk_qactive_man_data       1'h0
+   1       R/W    pclk_qactive_man_enable     1'h0
+   2       R/W    gclkintr_qactive_man_data   1'h0
+   3       R/W    gclkintr_qactive_man_enable 1'h0
+   4       R/W    clk32k_qactive_man_data     1'h0
+   5       R/W    clk32k_qactive_man_enable   1'h0
+   6       R/W    gclk_qactive_man_data       1'h0
+   7       R/W    gclk_qactive_man_enable     1'h0
+   31:8    R      reserved178_31_8            24'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t pclk_qactive_man_data: 1;
+        uint32_t pclk_qactive_man_enable: 1;
+        uint32_t gclkintr_qactive_man_data: 1;
+        uint32_t gclkintr_qactive_man_enable: 1;
+        uint32_t clk32k_qactive_man_data: 1;
+        uint32_t clk32k_qactive_man_enable: 1;
+        uint32_t gclk_qactive_man_data: 1;
+        uint32_t gclk_qactive_man_enable: 1;
+        const uint32_t reserved_0: 24;
+    } b;
+} GPIO_QACTIVE_MANUAL_CTRL_TypeDef;
+
+
+
+/*============================================================================*
+ *                          GPIO Constants
+ *============================================================================*/
+/** \defgroup GPIO        GPIO
+  * \brief
+  * \{
+  */
+
+/** \defgroup GPIO_Exported_Constants GPIO Exported Constants
+  * \brief
+  * \{
+  */
+
+
+/**
+ * \defgroup    GPIO_Debounce_Source GPIO Debounce Dource
+ * \{
+ * \ingroup     GPIO_Exported_Constants
+ */
+typedef enum
+{
+    GPIO_DEB_CLOCK_SRC_32K = 0x0, /**< debounce clock source 32KHz. */
+} GPIODebClockSrc_TypeDef;
+
+#define IS_GPIO_DEBOUNCE_CLOCK_SRC(SRC) (((SRC) == GPIO_DEB_CLOCK_SRC_32K))
+
+/** End of GPIO_Debounce_Source
+  * \}
+  */
+
+/**
+ * \defgroup    GPIO_Debounce_Divide GPIO Debounce Divide
+ * \{
+ * \ingroup     GPIO_Exported_Constants
+ */
+typedef enum
+{
+    GPIO_DEB_CLOCK_DIV_1   = 0x0, /**< debounce clock divider 1. */
+    GPIO_DEB_CLOCK_DIV_2   = 0x1, /**< debounce clock divider 2. */
+    GPIO_DEB_CLOCK_DIV_4   = 0x2, /**< debounce clock divider 4. */
+    GPIO_DEB_CLOCK_DIV_8   = 0x3, /**< debounce clock divider 8. */
+    GPIO_DEB_CLOCK_DIV_16  = 0x4, /**< debounce clock divider 16. */
+    GPIO_DEB_CLOCK_DIV_32  = 0x5, /**< debounce clock divider 32. */
+    GPIO_DEB_CLOCK_DIV_64  = 0x6, /**< debounce clock divider 64. */
+} GPIODebClockDiv_TypeDef;
+
+#define IS_GPIO_DEBOUNCE_CLOCK_DIV(DIV) (((DIV) == GPIO_DEB_CLOCK_DIV_1) || \
+                                         ((DIV) == GPIO_DEB_CLOCK_DIV_2) || \
+                                         ((DIV) == GPIO_DEB_CLOCK_DIV_4) || \
+                                         ((DIV) == GPIO_DEB_CLOCK_DIV_8) || \
+                                         ((DIV) == GPIO_DEB_CLOCK_DIV_16) || \
+                                         ((DIV) == GPIO_DEB_CLOCK_DIV_32) || \
+                                         ((DIV) == GPIO_DEB_CLOCK_DIV_64))
+
+/** End of GPIO_Debounce_Divide
+  * \}
+  */
+
+/**
+ * \defgroup GPIO_Constant_Private GPIO Constant Private
+ * \{
+ * \ingroup  GPIO_Exported_Constants
+ */
+
+#define GPIO_DEFAULT_DEB_CLOCK_SRC      GPIO_DEB_CLOCK_SRC_32K
+/**
+ * \brief    GPIO API Wrapper
+ *
+ * \ingroup  GPIO_Exported_Constants
+ */
+#define GPIO_DBClkCmd           GPIO_ExtDebCmd
+#define GPIO_SetDebounceTime    GPIO_ExtDebUpdate
+#define GPIO_SetITPolarity      GPIO_SetPolarity
+
+#define GPIOIT_LevelType            GPIOTrigger_TypeDef
+#define GPIOIT_PolarityType         GPIOPolarity_TypeDef
+#define GPIOIT_DebounceType         GPIODebounce_TypeDef
+#define GPIO_PinBit                 GPIO_Pin
+#define GPIO_Mode                   GPIO_Dir
+#define GPIO_Mode_IN                GPIO_DIR_IN
+#define GPIO_Mode_OUT               GPIO_DIR_OUT
+#define GPIOMode_TypeDef            GPIODir_TypeDef
+#define GPIO_INT_Trigger_LEVEL      GPIO_TRIGGER_LEVEL
+#define GPIO_INT_Trigger_EDGE       GPIO_TRIGGER_EDGE
+
+#define GPIOx_DeInit                GPIO_DeInit
+#define GPIOx_Init                  GPIO_Init
+#define GPIOx_INTConfig             GPIO_INTConfig
+#define GPIOx_ClearINTPendingBit    GPIO_ClearINTPendingBit
+#define GPIOx_MaskINTConfig         GPIO_MaskINTConfig
+#define GPIOx_ReadInputDataBit      GPIO_ReadInputDataBit
+#define GPIOx_ReadInputData         GPIO_ReadInputData
+#define GPIOx_ReadOutputDataBit     GPIO_ReadOutputDataBit
+#define GPIOx_ReadOutputData        GPIO_ReadOutputData
+#define GPIOx_SetBits               GPIO_SetBits
+#define GPIOx_ResetBits             GPIO_ResetBits
+#define GPIOx_WriteBit              GPIO_WriteBit
+#define GPIOx_Write                 GPIO_Write
+#define GPIOx_GetINTStatus          GPIO_GetINTStatus
+#define GPIOx_ModeSet               GPIO_SetDirection
+#define GPIOx_ChangePolarity        GPIO_SetPolarity
+#define GPIOx_IntPolaritySet        GPIO_SetPolarity
+#define GPIO_GetPin                 GPIO_GetPinBit
+#define GPIO_ModeSet                GPIO_SetDirection
+/** End of GPIO_Constant_Private
+  * \}
+  */
+
+/** End of GPIO_Exported_Constants
+  * \}
+  */
+
+/** End of GPIO
+  * \}
+  */
+
+#ifdef  __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* RTL_GPIO_DEF_H */
diff --git a/bee/drivers/gpio/src/device/rtl_common/rtl_gpio.c b/bee/drivers/gpio/src/device/rtl_common/rtl_gpio.c
new file mode 100644
index 00000000..aba13176
--- /dev/null
+++ b/bee/drivers/gpio/src/device/rtl_common/rtl_gpio.c
@@ -0,0 +1,526 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *                           Header Files
+ *============================================================================*/
+#include "rtl_gpio.h"
+#include "rtl_rcc.h"
+
+/*============================================================================*
+ *                           Private Macros
+ *============================================================================*/
+
+/*============================================================================*
+ *                           Private Functions
+ *============================================================================*/
+extern void GPIO_ExtPolarity(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin, GPIOPolarity_TypeDef Polarity);
+
+/*============================================================================*
+ *                           Public Functions
+ *============================================================================*/
+/**
+  * \brief  Deinitializes the GPIO peripheral registers to their default reset values.
+  * \param  GPIOx: Select the GPIO peripheral. \ref GPIO_Declaration
+  * \return None.
+  */
+void GPIO_DeInit(GPIO_TypeDef *GPIOx)
+{
+#ifdef GPIOA
+    if (GPIOx == GPIOA)
+    {
+        RCC_ClockCmd(GPIOA_CLOCK, DISABLE);
+        return;
+    }
+#endif
+#ifdef GPIOB
+    if (GPIOx == GPIOB)
+    {
+        RCC_ClockCmd(GPIOB_CLOCK, DISABLE);
+        return;
+    }
+#endif
+#ifdef GPIOC
+    if (GPIOx == GPIOC)
+    {
+        RCC_ClockCmd(GPIOC_CLOCK, DISABLE);
+        return;
+    }
+#endif
+#ifdef GPIOD
+    if (GPIOx == GPIOD)
+    {
+        RCC_ClockCmd(GPIOD_CLOCK, DISABLE);
+        return;
+    }
+#endif
+}
+
+/**
+  * \brief  Initializes the GPIO peripheral according to the specified
+  *         parameters in the GPIO_InitStruct.
+  * \param  GPIOx: Select the GPIO peripheral. \ref GPIO_Declaration
+  * \param  GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that
+  *         contains the configuration information for the specified GPIO peripheral.
+  * \return None
+  */
+void GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_InitStruct)
+{
+    /* Check the parameters */
+    assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin));
+    assert_param(IS_GPIO_DIR(GPIO_InitStruct->GPIO_Dir));
+#if (GPIO_SUPPORT_OUTPUT_MODE_SELECT == 1)
+    assert_param(IS_GPIO_OUTPUT_MODE(GPIO_InitStruct->GPIO_OutPutMode));
+#endif
+    assert_param(IS_GPIOIT_TRIGGER_TYPE(GPIO_InitStruct->GPIO_Trigger));
+    assert_param(IS_GPIOIT_POLARITY_TYPE(GPIO_InitStruct->GPIO_Polarity));
+    assert_param(IS_GPIOIT_DEBOUNCE_TYPE(GPIO_InitStruct->GPIO_DebounceEn));
+
+    /* GPIO configure */
+    if (GPIO_InitStruct->GPIO_Dir == GPIO_DIR_OUT)
+    {
+        GPIOx->GPIO_DDR |= GPIO_InitStruct->GPIO_Pin;
+
+#if (GPIO_SUPPORT_OUTPUT_MODE_SELECT == 1)
+        if (GPIO_InitStruct->GPIO_OutPutMode == GPIO_OUTPUT_OPENDRAIN)
+        {
+            GPIOx->GPIO_OUT_MODE |= GPIO_InitStruct->GPIO_Pin;
+        }
+        else
+        {
+            GPIOx->GPIO_OUT_MODE &= ~(GPIO_InitStruct->GPIO_Pin);
+        }
+#endif
+
+#if (GPIO_SUPPORT_SET_CONTROL_MODE == 1)
+        if (GPIO_InitStruct->GPIO_ControlMode == GPIO_SOFTWARE_MODE)
+        {
+            /* Config GPIOx control software mode */
+            GPIOx->GPIO_SRC &= (~GPIO_InitStruct->GPIO_Pin);
+        }
+        else
+        {
+            /* Config GPIOx hardware control mode */
+            GPIOx->GPIO_SRC |= (GPIO_InitStruct->GPIO_Pin);
+        }
+#endif
+    }
+    else
+    {
+        /*Configure GPIO input mode */
+        GPIOx->GPIO_DDR = GPIOx->GPIO_DDR & (~GPIO_InitStruct->GPIO_Pin);
+
+        if (GPIO_InitStruct->GPIO_INTEventEn == ENABLE)
+        {
+            GPIOx->GPIO_INT_MASK = ~GPIO_Pin_All;
+
+            /* configure GPIO interrupt trigger type */
+#if GPIO_SUPPORT_BOTHEDGE
+            if (GPIO_InitStruct->GPIO_Trigger == GPIO_TRIGGER_BOTH_EDGE)
+            {
+                GPIOx->GPIO_INT_BOTHEDGE |= GPIO_InitStruct->GPIO_Pin;
+            }
+            else
+            {
+                GPIOx->GPIO_INT_BOTHEDGE &= ~GPIO_InitStruct->GPIO_Pin;
+            }
+#endif
+
+            if (GPIO_InitStruct->GPIO_Trigger == GPIO_TRIGGER_LEVEL)
+            {
+                GPIOx->GPIO_INT_LV &= ~GPIO_InitStruct->GPIO_Pin;
+
+#if (GPIO_SUPPORT_LS_SYNC == 1)
+                /* Level-sensitive synchronization enable register */
+                GPIOx->GPIO_LS_SYNC = 0x1;
+#endif
+            }
+            else if (GPIO_InitStruct->GPIO_Trigger == GPIO_TRIGGER_EDGE)
+            {
+                GPIOx->GPIO_INT_LV |= GPIO_InitStruct->GPIO_Pin;
+            }
+
+            /* configure Interrupt polarity register */
+            GPIO_ExtPolarity(GPIOx, GPIO_InitStruct->GPIO_Pin, GPIO_InitStruct->GPIO_Polarity);
+
+            /* configure Debounce enable register */
+            if (GPIO_InitStruct->GPIO_DebounceEn == ENABLE)
+            {
+                GPIO_ExtDebUpdate(GPIOx, GPIO_InitStruct->GPIO_Pin,
+                                  GPIO_InitStruct->GPIO_DebClockSrc,
+                                  GPIO_InitStruct->GPIO_DebClockDiv,
+                                  GPIO_InitStruct->GPIO_DebCountLimit);
+            }
+            GPIO_ExtDebCmd(GPIOx, GPIO_InitStruct->GPIO_Pin,
+                           (FunctionalState) GPIO_InitStruct->GPIO_DebounceEn);
+        }
+    }
+}
+
+/**
+  * \brief  Fills each GPIO_InitStruct member with its default value.
+  * \param  GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure which will be initialized.
+  * \return None
+  */
+void GPIO_StructInit(GPIO_InitTypeDef *GPIO_InitStruct)
+{
+    /* Reset GPIO init structure parameters values */
+    GPIO_InitStruct->GPIO_Pin         = GPIO_Pin_All;
+    GPIO_InitStruct->GPIO_Dir         = GPIO_DIR_IN;
+#if (GPIO_SUPPORT_OUTPUT_MODE_SELECT == 1)
+    GPIO_InitStruct->GPIO_OutPutMode  = GPIO_OUTPUT_PUSHPULL;
+#endif
+#if (GPIO_SUPPORT_SET_CONTROL_MODE == 1)
+    GPIO_InitStruct->GPIO_ControlMode = GPIO_SOFTWARE_MODE;
+#endif
+    GPIO_InitStruct->GPIO_INTEventEn  = DISABLE;
+    GPIO_InitStruct->GPIO_Trigger     = GPIO_TRIGGER_LEVEL;
+    GPIO_InitStruct->GPIO_Polarity    = GPIO_POLARITY_ACTIVE_LOW;
+
+    /* Set GPIO doubonce parameters: set doubonce time is 1ms,
+     * debounce time = (CntLimit + 1) * DEB_CLK = 32 / 32000 = 1ms */
+    GPIO_InitStruct->GPIO_DebounceEn  = DISABLE;
+    GPIO_InitStruct->GPIO_DebClockSrc = GPIO_DEFAULT_DEB_CLOCK_SRC;
+    GPIO_InitStruct->GPIO_DebClockDiv = GPIO_DEB_CLOCK_DIV_1;
+    GPIO_InitStruct->GPIO_DebCountLimit = 32;
+}
+
+/**
+  * \brief  Enable the specified GPIO interrupt.
+  * \param  GPIOx: Select the GPIO peripheral. \ref GPIO_Declaration
+  * \param  GPIO_Pin: GPIO_Pin can be 0 to 31.
+  * \param  Enable or disable interrupt
+  * \return None
+  */
+void GPIO_INTConfig(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_GPIO_PIN(GPIO_Pin));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (NewState != DISABLE)
+    {
+        /* Enable the selected GPIO pin interrupts */
+        GPIOx->GPIO_INT_EN |= GPIO_Pin;
+    }
+    else
+    {
+        /* Disable the selected GPIO pin interrupts */
+        GPIOx->GPIO_INT_EN &= ~GPIO_Pin;
+    }
+}
+
+/**
+  * \brief  Clear the specified GPIO interrupt.
+  * \param  GPIOx: Select the GPIO peripheral. \ref GPIO_Declaration
+  * \param  GPIO_Pin: GPIO_Pin can be 0 to 31.
+  * \return None
+  */
+void GPIO_ClearINTPendingBit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
+{
+    /* Check the parameters */
+    assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+    GPIOx->GPIO_INT_CLR = GPIO_Pin;
+}
+
+/**
+  * \brief  Mask the specified GPIO interrupt.
+  * \param  GPIOx: Select the GPIO peripheral. \ref GPIO_Declaration
+  * \param  GPIO_Pin: GPIO_Pin can be 0 to 31.
+  * \param  NewState: Mask or unmask gpio debounce clock.
+  * \return None
+  */
+void GPIO_MaskINTConfig(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_GPIO_PIN(GPIO_Pin));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (NewState != DISABLE)
+    {
+        GPIOx->GPIO_INT_MASK |= GPIO_Pin;
+    }
+    else
+    {
+        GPIOx->GPIO_INT_MASK &= ~(GPIO_Pin);
+    }
+}
+
+#if (GPIO_SUPPORT_OUTPUT_MODE_SELECT == 1)
+/**
+  * \brief  Set GPIO Output mode.
+  * \param  GPIOx: Select the GPIO peripheral. \ref GPIO_Declaration
+  * \param  GPIO_Pin: GPIO_Pin can be 0 to 31.
+  * \param  GPIO_OutputMode: Specifies the output mode to be set.
+  * \return None.
+  */
+void GPIO_SetOutputMode(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin,
+                        GPIOOutputMode_TypeDef GPIO_OutputMode)
+{
+    /* Check the parameters */
+    assert_param(IS_GPIO_OUTPUT_MODE(GPIO_OutputMode));
+
+    /* configure Interrupt polarity register */
+    if (GPIO_OutputMode == GPIO_OUTPUT_OPENDRAIN)
+    {
+        GPIOx->GPIO_OUT_MODE = (GPIOx->GPIO_OUT_MODE & (~GPIO_Pin)) | GPIO_Pin;
+    }
+    else
+    {
+        GPIOx->GPIO_OUT_MODE &= (~GPIO_Pin);
+    }
+}
+#endif
+
+/**
+  * \brief  Read the specified input port pin.
+  * \param  GPIOx: Select the GPIO peripheral. \ref GPIO_Declaration
+  * \param  GPIO_Pin: Specifies the port bit to read.
+  * \return The input port pin value.
+  */
+uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
+{
+    /* Check the parameters */
+    assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
+
+    if (GPIOx->GPIO_PAD_STATE & GPIO_Pin)
+    {
+        return SET;
+    }
+    else
+    {
+        return RESET;
+    }
+}
+
+/**
+  * \brief  Read value of all GPIO input data port.
+  * \param  GPIOx: Select the GPIO peripheral. \ref GPIO_Declaration
+  * \return GPIO input data port value.
+  */
+uint32_t GPIO_ReadInputData(GPIO_TypeDef *GPIOx)
+{
+    return ((uint32_t)GPIOx->GPIO_PAD_STATE);
+}
+
+/**
+  * \brief  Read the specified output port pin.
+  * \param  GPIOx: Select the GPIO peripheral. \ref GPIO_Declaration
+  * \param  GPIO_Pin: Specifies the port bit to read.
+  * \return The output port pin value.
+  */
+uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
+{
+    /* Check the parameters */
+    assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
+
+    if (GPIOx->GPIO_DR & GPIO_Pin)
+    {
+        return SET;
+    }
+    else
+    {
+        return RESET;
+    }
+}
+
+/**
+  * \brief  Read value of all GPIO output data port.
+  * \param  GPIOx: Select the GPIO peripheral. \ref GPIO_Declaration
+  * \return GPIO output data port value.
+  */
+uint32_t GPIO_ReadOutputData(GPIO_TypeDef *GPIOx)
+{
+    return ((uint32_t)GPIOx->GPIO_DR);
+}
+
+/**
+  * \brief  Sets the selected data port bit.
+  * \param  GPIOx: Select the GPIO peripheral. \ref GPIO_Declaration
+  * \param  GPIO_Pin: Specifies the port bit to be written.
+  * \return None.
+  */
+void GPIO_SetBits(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
+{
+    /* Check the parameters */
+    assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+    GPIOx->GPIO_DR |= GPIO_Pin;
+}
+
+/**
+  * \brief  Reset the selected data port bit.
+  * \param  GPIOx: Select the GPIO peripheral. \ref GPIO_Declaration
+  * \param  GPIO_Pin: Specifies the port bits to be written.
+  * \return None.
+  */
+void GPIO_ResetBits(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
+{
+    /* Check the parameters */
+    assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+    GPIOx->GPIO_DR &= ~(GPIO_Pin);
+}
+
+/**
+  * \brief  Set or clear the selected data port bit.
+  * \param  GPIOx: Select the GPIO peripheral. \ref GPIO_Declaration
+  * \param  GPIO_Pin: Specifies the port bit to be written.
+  * \param  BitVal: specifies the value to be written to the selected bit.
+  * \return None.
+  */
+void GPIO_WriteBit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin, BitAction BitVal)
+{
+    /* Check the parameters */
+    assert_param(IS_GPIO_PIN(GPIO_Pin));
+    assert_param(IS_GPIO_BIT_ACTION(BitVal));
+
+    if (BitVal != Bit_RESET)
+    {
+        GPIOx->GPIO_DR |= GPIO_Pin;
+    }
+    else
+    {
+        GPIOx->GPIO_DR &= ~(GPIO_Pin);
+    }
+}
+
+/**
+  * \brief  Set or clear data port.
+  * \param  GPIOx: Select the GPIO peripheral. \ref GPIO_Declaration
+  * \param  PortVal: Specifies the value to be written to the selected bit.
+  * \return None.
+  */
+void GPIO_Write(GPIO_TypeDef *GPIOx, uint32_t PortVal)
+{
+    GPIOx->GPIO_DR = PortVal;
+}
+
+
+/**
+  * \brief  Get GPIO interrupt status.
+  * \param  GPIOx: Select the GPIO peripheral. \ref GPIO_Declaration
+  * \param  GPIO_Pin: Specifies the port bit to be written.
+  * \return The new state of GPIO_INT (SET or RESET).
+  */
+ITStatus GPIO_GetINTStatus(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
+{
+    /* Check the parameters */
+    assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
+
+    if ((GPIOx->GPIO_INT_STS & GPIO_Pin) == GPIO_Pin)
+    {
+        return SET;
+    }
+    else
+    {
+        return RESET;
+    }
+}
+
+/**
+  * \brief  Specifies the direction for the selected pins.
+  * \param  GPIOx: Select the GPIO peripheral. \ref GPIO_Declaration
+  * \param  GPIO_PinBit: Specifies the GPIO pins to be configured, please refer to "GPIO_pins_define" part.
+  * \param  GPIO_Dir: Set the GPIO direction.
+  * \return None.
+  */
+void GPIO_SetDirection(GPIO_TypeDef *GPIOx, uint32_t GPIO_PinBit,
+                       GPIODir_TypeDef GPIO_Dir)
+{
+    /* Check the parameters */
+    assert_param(IS_GPIO_PIN(GPIO_PinBit));
+
+    if (GPIO_Dir == GPIO_DIR_OUT)
+    {
+        GPIOx->GPIO_DDR |= GPIO_PinBit;
+    }
+    else
+    {
+        GPIOx->GPIO_DDR &= ~GPIO_PinBit;
+    }
+}
+
+/**
+  * \brief  Get GPIO pad status.
+  * \param  GPIO_Pin: Specifies the port bit to be written.
+  * \return The new state of GPIO_Pad (SET or RESET).
+  */
+FlagStatus GPIO_GetPadStatus(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
+{
+    /* Check the parameters */
+    assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
+
+    if ((GPIOx->GPIO_PAD_STATE & GPIO_Pin) == GPIO_Pin)
+    {
+        return SET;
+    }
+    else
+    {
+        return RESET;
+    }
+}
+
+/**
+  * \brief  Set GPIO Int Polarity.
+  * \param  GPIOx: Select the GPIO peripheral. \ref GPIO_Declaration
+  * \param  GPIO_Pin: GPIO_Pin can be 0 to 31.
+  * \param  int_type: Specifies the polarity type to be set.
+  * \return None.
+  */
+void GPIO_SetPolarity(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin, GPIOPolarity_TypeDef Polarity)
+{
+    /* Check the parameters */
+    assert_param(IS_GPIO_POLARITY_TYPE(Polarity));
+
+    GPIO_ExtPolarity(GPIOx, GPIO_Pin, Polarity);
+}
+
+/*============================================================================*
+ *                        RAP Functions
+ *============================================================================*/
+#if (GPIO_SUPPORT_RAP_FUNCTION == 1)
+
+void GPIO_RAPModeCmd(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+    if (NewState != DISABLE)
+    {
+        GPIOx->GPIO_RAP_CTL |= GPIO_Pin;
+    }
+    else
+    {
+        GPIOx->GPIO_RAP_CTL &= ~GPIO_Pin;
+    }
+    return;
+}
+
+void GPIO_ActionTrigger(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin, uint32_t Action)
+{
+    /* Check the parameters */
+    assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+    if (Action == GPIO_ACTION_DRSET)
+    {
+        GPIOx->GPIO_RAP_TASK_DRSET |= GPIO_Pin;
+    }
+    else if (Action == GPIO_ACTION_DRCLR)
+    {
+        GPIOx->GPIO_RAP_TASK_DRCLR |= GPIO_Pin;
+    }
+    else if (Action == GPIO_ACTION_DRTOGGLE)
+    {
+        GPIOx->GPIO_RAP_TASK_DRTOGGLE |= GPIO_Pin;
+    }
+    return;
+}
+#endif
+
+
+
diff --git a/bee/drivers/gtc/CMakeLists.txt b/bee/drivers/gtc/CMakeLists.txt
new file mode 100644
index 00000000..15e21c7e
--- /dev/null
+++ b/bee/drivers/gtc/CMakeLists.txt
@@ -0,0 +1,7 @@
+#
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+add_subdirectory(inc)
diff --git a/bee/drivers/gtc/Kconfig b/bee/drivers/gtc/Kconfig
new file mode 100644
index 00000000..a3c73fc9
--- /dev/null
+++ b/bee/drivers/gtc/Kconfig
@@ -0,0 +1,5 @@
+config REALTEK_BEE_GTC
+	bool "Realtek Bee I2C driver"
+	default n
+	help
+	  This option enables the gtc driver for Realtek Bee.
diff --git a/bee/drivers/gtc/inc/CMakeLists.txt b/bee/drivers/gtc/inc/CMakeLists.txt
new file mode 100644
index 00000000..3127c50f
--- /dev/null
+++ b/bee/drivers/gtc/inc/CMakeLists.txt
@@ -0,0 +1,11 @@
+#
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if(DEFINED ZEPHYR_BASE)
+    zephyr_include_directories(${CMAKE_CURRENT_SOURCE_DIR})
+else()
+    register_module_include_directories(driver ${driver_public_type} ${CMAKE_CURRENT_SOURCE_DIR})
+endif()
\ No newline at end of file
diff --git a/bee/drivers/gtc/inc/rtl_gtc.h b/bee/drivers/gtc/inc/rtl_gtc.h
new file mode 100644
index 00000000..b2c00cf4
--- /dev/null
+++ b/bee/drivers/gtc/inc/rtl_gtc.h
@@ -0,0 +1,76 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *               Define to prevent recursive inclusion
+ *============================================================================*/
+#ifndef RTL_GTC_H
+#define RTL_GTC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*============================================================================*
+ *                        Header Files
+ *============================================================================*/
+#include "utils/rtl_utils.h"
+#include "utils.h"
+
+/** \defgroup GTC         GTC
+  * \brief
+  * \{
+  */
+
+/*============================================================================*
+ *                         Constants
+ *============================================================================*/
+
+/*============================================================================*
+ *                         Functions
+ *============================================================================*/
+/** \defgroup GTC_Exported_Functions GTC Exported Functions
+  * \brief
+  * \{
+  */
+
+/**
+ * \brief     Get the counter value of GTC.
+ *
+ * \param[in] None.
+ *
+ * \return    The counter value.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void gtc_demo(void)
+ * {
+ *     uint32_t counter = GTC_GetCounter();
+ * }
+ * \endcode
+ */
+uint32_t GTC_GetCounter(void);
+
+uint32_t GTC_CounterToUs(uint32_t Counter, RoundType round_type);
+
+uint32_t GTC_UsToCounter(uint32_t TimeUs, RoundType round_type);
+
+/** End of GTC_Exported_Functions
+  * \}
+  */
+
+/** End of GTC
+  * \}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RTL_GTC_H */
+
+
diff --git a/bee/drivers/i2c/CMakeLists.txt b/bee/drivers/i2c/CMakeLists.txt
new file mode 100644
index 00000000..3eb94b1d
--- /dev/null
+++ b/bee/drivers/i2c/CMakeLists.txt
@@ -0,0 +1,8 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+if(CONFIG_REALTEK_BEE_COMMON_DRIVER)
+    zephyr_include_directories(inc)
+endif()
+
+add_subdirectory_ifdef(CONFIG_REALTEK_BEE_I2C src)
diff --git a/bee/drivers/i2c/Kconfig b/bee/drivers/i2c/Kconfig
new file mode 100644
index 00000000..2585a992
--- /dev/null
+++ b/bee/drivers/i2c/Kconfig
@@ -0,0 +1,8 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config REALTEK_BEE_I2C
+	bool "Realtek Bee I2C driver"
+	default n
+	help
+	  This option enables the I2C driver for Realtek Bee.
diff --git a/bee/drivers/i2c/inc/rtl_i2c.h b/bee/drivers/i2c/inc/rtl_i2c.h
new file mode 100644
index 00000000..6cd401a8
--- /dev/null
+++ b/bee/drivers/i2c/inc/rtl_i2c.h
@@ -0,0 +1,1046 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *               Define to prevent recursive inclusion
+ *============================================================================*/
+#ifndef RTL_I2C_H
+#define RTL_I2C_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*============================================================================*
+ *                        Header Files
+ *============================================================================*/
+#include "utils/rtl_utils.h"
+#if defined (CONFIG_SOC_SERIES_RTL87X2G)
+#include "i2c/src/device/rtl87x2g/rtl_i2c_def.h"
+#elif defined (CONFIG_SOC_SERIES_RTL87X3E)
+#include "i2c/src/device/rtl87x3e/rtl_i2c_def.h"
+#elif defined (CONFIG_SOC_SERIES_RTL87X3D)
+#include "i2c/src/device/rtl87x3d/rtl_i2c_def.h"
+#elif defined (CONFIG_SOC_SERIES_RTL87X2J)
+#include "i2c/src/device/rtl87x2j/rtl_i2c_def.h"
+#elif defined (CONFIG_SOC_SERIES_RTL87X3J)
+#include "i2c/src/device/rtl87x3j/rtl_i2c_def.h"
+#endif
+
+/** \defgroup I2C         I2C
+  * \brief
+  * \{
+  */
+
+/*============================================================================*
+ *                         Constants
+ *============================================================================*/
+/** \defgroup I2C_Exported_Constants I2C Exported Constants
+  * \brief
+  * \{
+  */
+
+/**
+ * \defgroup    I2C_Clock_Speed I2C Clock Speed
+ * \{
+ * \ingroup     I2C_Exported_Constants
+ */
+#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) >= 0x01) && ((SPEED) <= I2C_CLOCK_MAX_SPEED))
+
+/** End of I2C_Clock_Speed
+  * \}
+  */
+
+/**
+ * \defgroup    I2C_Device_Mode I2C Device Mode
+ * \{
+ * \ingroup     I2C_Exported_Constants
+ */
+typedef enum
+{
+    I2C_DEVICE_MODE_SLAVE = 0x00,
+    I2C_DEVICE_MODE_MASTER = 0x01,
+} I2CDeviceMode_TypeDef;
+
+#define IS_I2C_DEVICE_MODE(MODE) (((MODE) == I2C_DEVICE_MODE_SLAVE) || ((MODE) == I2C_DEVICE_MODE_MASTER))
+
+/** End of I2C_Device_Mode
+  * \}
+  */
+
+/**
+ * \defgroup    I2C_Address_Mode I2C Address Mode
+ * \{
+ * \ingroup     I2C_Exported_Constants
+ */
+typedef enum
+{
+    I2C_ADDRESS_MODE_7BIT = 0x00,
+    I2C_ADDRESS_MODE_10BIT = 0x01,
+} I2CAddressMode_TypeDef;
+
+#define IS_I2C_ADDRESS_MODE(ADDR) (((ADDR) == I2C_ADDRESS_MODE_7BIT) || ((ADDR) == I2C_ADDRESS_MODE_10BIT))
+
+/** End of I2C_Address_Mode
+  * \}
+  */
+
+/**
+ * \defgroup    I2C_Send_Command I2C Send Command
+ * \{
+ * \ingroup     I2C_Exported_Constants
+ */
+typedef enum
+{
+    I2C_WRITE_CMD = 0x00,
+    I2C_READ_CMD = 0x01,
+} I2CSendCommend_TypeDef;
+
+#define IS_I2C_CMD(CMD) (((CMD) == I2C_WRITE_CMD) || ((CMD) == I2C_READ_CMD))
+
+/** End of I2C_Send_Command
+  * \}
+  */
+
+/**
+ * \defgroup    I2C_DMA_Requests I2C DMA Requests
+ * \{
+ * \ingroup     I2C_Exported_Constants
+ */
+typedef enum
+{
+    I2C_DMA_REQ_RX = 0x01,
+    I2C_DMA_REQ_TX = 0x02,
+} I2CDMARequests_TypeDef;
+
+#define IS_I2C_DMAREQ(DMAREQ) (((DMAREQ) == I2C_DMA_REQ_RX) || ((DMAREQ) == I2C_DMA_REQ_TX))
+
+/** End of I2C_DMA_Requests
+  * \}
+  */
+
+/**
+ * \defgroup    I2C_Status I2C Status
+ * \{
+ * \ingroup     I2C_Exported_Constants
+ */
+typedef enum
+{
+    I2C_SUCCESS,
+    I2C_ARB_LOST,
+    I2C_ABRT_MASTER_DIS,
+    I2C_ABRT_TXDATA_NOACK,
+    I2C_ABRT_10ADDR2_NOACK,
+    I2C_ABRT_10ADDR1_NOACK,
+    I2C_ABRT_7B_ADDR_NOACK,
+    I2C_ERR_TIMEOUT,
+} I2C_Status;
+
+/** End of I2C_Status
+  * \}
+  */
+
+/**
+ * \defgroup    I2C_Interrupts I2C Interrupts
+ * \{
+ * \ingroup     I2C_Exported_Constants
+ */
+
+#define I2C_INT_MST_ON_HOLD                     BIT13
+#define I2C_INT_GEN_CALL                        BIT11
+#define I2C_INT_START_DET                       BIT10
+#define I2C_INT_STOP_DET                        BIT9
+#define I2C_INT_ACTIVITY                        BIT8
+#define I2C_INT_RX_DONE                         BIT7
+#define I2C_INT_TX_ABRT                         BIT6
+#define I2C_INT_RD_REQ                          BIT5
+#define I2C_INT_TX_EMPTY                        BIT4
+#define I2C_INT_TX_OVER                         BIT3
+#define I2C_INT_RX_FULL                         BIT2
+#define I2C_INT_RX_OVER                         BIT1
+#define I2C_INT_RX_UNDER                        BIT0
+
+#define I2C_GET_INT(INT)    (((INT) == I2C_INT_GEN_CALL) || \
+                             ((INT) == I2C_INT_START_DET) || \
+                             ((INT) == I2C_INT_STOP_DET) || \
+                             ((INT) == I2C_INT_ACTIVITY) || \
+                             ((INT) == I2C_INT_RX_DONE)  || \
+                             ((INT) == I2C_INT_TX_ABRT) || \
+                             ((INT) == I2C_INT_RD_REQ)   || \
+                             ((INT) == I2C_INT_TX_EMPTY) || \
+                             ((INT) == I2C_INT_TX_OVER)  || \
+                             ((INT) == I2C_INT_RX_FULL) || \
+                             ((INT) == I2C_INT_RX_OVER)  || \
+                             ((INT) == I2C_INT_RX_UNDER) || \
+                             ((INT) == I2C_INT_MST_ON_HOLD))
+
+/** End of I2C_Interrupts
+  * \}
+  */
+
+/**
+ * \defgroup    I2C_Flags I2C Flags
+ * \{
+ * \ingroup     I2C_Exported_Constants
+ */
+
+#define I2C_FLAG_SLV_HOLD_RX_FIFO_FULL          BIT10
+#define I2C_FLAG_SLV_HOLD_TX_FIFO_EMPTY         BIT9
+#define I2C_FLAG_MST_HOLD_RX_FIFO_FULL          BIT8
+#define I2C_FLAG_MST_HOLD_TX_FIFO_EMPTY         BIT7
+#define I2C_FLAG_SLV_ACTIVITY                   BIT6
+#define I2C_FLAG_MST_ACTIVITY                   BIT5
+#define I2C_FLAG_RFF                            BIT4
+#define I2C_FLAG_RFNE                           BIT3
+#define I2C_FLAG_TFE                            BIT2
+#define I2C_FLAG_TFNF                           BIT1
+#define I2C_FLAG_ACTIVITY                       BIT0
+
+#define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_SLV_HOLD_RX_FIFO_FULL) || \
+                               ((FLAG) == I2C_FLAG_SLV_HOLD_TX_FIFO_EMPTY) || \
+                               ((FLAG) == I2C_FLAG_MST_HOLD_RX_FIFO_FULL) || \
+                               ((FLAG) == I2C_FLAG_MST_HOLD_TX_FIFO_EMPTY) || \
+                               ((FLAG) == I2C_FLAG_SLV_ACTIVITY) || \
+                               ((FLAG) == I2C_FLAG_MST_ACTIVITY) || \
+                               ((FLAG) == I2C_FLAG_RFF) || \
+                               ((FLAG) == I2C_FLAG_RFNE) || \
+                               ((FLAG) == I2C_FLAG_TFE) || \
+                               ((FLAG) == I2C_FLAG_TFNF) || \
+                               ((FLAG) == I2C_FLAG_ACTIVITY))
+
+/** End of I2C_Flags
+  * \}
+  */
+
+/**
+ * \defgroup    I2C_Transmit_Abort_Source I2C Transmit Abort Source
+ * \{
+ * \ingroup     I2C_Exported_Constants
+ */
+
+#define ABRT_SLVRD_INTX                         BIT15
+#define ABRT_SLV_ARBLOST                        BIT14
+#define ABRT_SLVFLUSH_TXFIFO                    BIT13
+#define ARB_LOST                                BIT12
+#define ABRT_MASTER_DIS                         BIT11
+#define ABRT_10B_RD_NORSTRT                     BIT10
+#define ABRT_SBYTE_NORSTRT                      BIT9
+#define ABRT_HS_NORSTRT                         BIT8
+#define ABRT_SBYTE_ACKDET                       BIT7
+#define ABRT_HS_ACKDET                          BIT6
+#define ABRT_GCALL_READ                         BIT5
+#define ABRT_GCALL_NOACK                        BIT4
+#define ABRT_TXDATA_NOACK                       BIT3
+#define ABRT_10ADDR2_NOACK                      BIT2
+#define ABRT_10ADDR1_NOACK                      BIT1
+#define ABRT_7B_ADDR_NOACK                      BIT0
+
+#define MS_ALL_ABORT                            (ARB_LOST | ABRT_MASTER_DIS | ABRT_TXDATA_NOACK | \
+                                                 ABRT_10ADDR2_NOACK | ABRT_10ADDR1_NOACK | ABRT_7B_ADDR_NOACK)
+
+#define IS_I2C_EVENT(EVENT) (((EVENT) == ABRT_SLVRD_INTX) || \
+                             ((EVENT) == ABRT_SLV_ARBLOST) || \
+                             ((EVENT) == ABRT_SLVFLUSH_TXFIFO) || \
+                             ((EVENT) == ARB_LOST) || \
+                             ((EVENT) == ABRT_MASTER_DIS) || \
+                             ((EVENT) == ABRT_10B_RD_NORSTRT) || \
+                             ((EVENT) == ABRT_SBYTE_NORSTRT) || \
+                             ((EVENT) == ABRT_HS_NORSTRT) || \
+                             ((EVENT) == ABRT_SBYTE_ACKDET) || \
+                             ((EVENT) == ABRT_HS_ACKDET) || \
+                             ((EVENT) == ABRT_GCALL_READ) || \
+                             ((EVENT) == ABRT_GCALL_NOACK) || \
+                             ((EVENT) == ABRT_TXDATA_NOACK) || \
+                             ((EVENT) == ABRT_10ADDR2_NOACK) || \
+                             ((EVENT) == ABRT_10ADDR1_NOACK) || \
+                             ((EVENT) == ABRT_7B_ADDR_NOACK))
+
+/** End of I2C_Transmit_Abort_Source
+  * \}
+  */
+
+#if (I2C_SUPPORT_WRAPPER_MODE == 1)
+/**
+ * \defgroup    I2C_Wrapper_Trans_Mode I2C Wrapper Trans Mode
+ * \{
+ * \ingroup     I2C_Exported_Constants
+ */
+
+typedef enum
+{
+    I2C_WRAPPER_TRANS_MODE_WRITE       = 0,
+    I2C_WRAPPER_TRANS_MODE_READ        = 1,
+    I2C_WRAPPER_TRANS_MODE_REPEAT_READ = 2,
+    I2C_WRAPPER_TRANS_MODE_DMA_READ    = 3,
+} I2CWrapperTransMode_TypeDef;
+
+/** End of I2C_Wrapper_Trans_Mode
+  * \}
+  */
+#endif
+
+#if (I2C_SUPPORT_RAP_FUNCTION == 1)
+/**
+ * \defgroup    I2C_Action I2C Action Number
+ * \{
+ * \ingroup     I2C_Exported_Constants
+ */
+
+typedef enum
+{
+    I2C_ACTION_START = 0,
+} I2CAction_TypeDef;
+
+/** End of I2C_Action
+  * \}
+  */
+
+#endif
+
+/** End of I2C_Exported_Constants
+  * \}
+  */
+
+/*============================================================================*
+ *                         Types
+ *============================================================================*/
+/** \defgroup I2C_Exported_Types I2C Exported Types
+  * \brief
+  * \{
+  */
+
+/**
+ * \brief       I2C Init structure definition.
+ *
+ * \ingroup     I2C_Exported_Types
+ */
+
+typedef struct
+{
+    uint32_t I2C_Clock;                    /*!< Specifies source clock frequency, default 40000000.
+                                                This parameter must be set with I2C clock div. */
+
+    uint32_t I2C_ClockSpeed;               /*!< Specifies SCK speed.
+                                                This parameter must be set to a value lower than 1MHz. */
+
+    I2CDeviceMode_TypeDef I2C_DeviceMode;  /*!< Specifies the I2C devie mode. */
+
+    I2CAddressMode_TypeDef I2C_AddressMode; /*!< Specifies the I2C address mode. */
+
+    uint16_t I2C_SlaveAddress;             /*!< Specifies the first device own address.
+                                                This parameter can be a 7-bit or 10-bit address. */
+
+    FunctionalState I2C_Ack;               /*!< Enables or disables the acknowledgement
+                                                only in slave mode.
+                                                This parameter can be a value of ENABLE or DISABLE. */
+
+    uint32_t I2C_TxThresholdLevel;         /* !< Specifies the transmit FIFO Threshold
+                                                 to trigger interrupt I2C_INT_TX_EMPTY.
+                                                 This parameter can be a value less than I2C_TX_FIFO_SIZE.*/
+
+    uint32_t I2C_RxThresholdLevel;         /* !<Specifies the receive FIFO Threshold
+                                                to trigger interrupt I2C_INT_RX_FULL.
+                                                This parameter can be a value less than I2C_RX_FIFO_SIZE.*/
+
+    FunctionalState I2C_TxDMAEn;           /*!< Specifies the Tx dma mode.
+                                                This parameter can be a value of ENABLE or DISABLE. */
+
+    FunctionalState I2C_RxDMAEn;           /*!< Specifies the Rx dma mode.
+                                                This parameter can be a value of ENABLE or DISABLE. */
+
+    uint8_t  I2C_TxWaterlevel;             /*!< Specifies the DMA tx water level.
+                                                The best value is I2C Tx fifo depth - Tx DMA MSize. */
+
+    uint8_t  I2C_RxWaterlevel;             /*!< Specifies the DMA rx water level.
+                                                The best value is I2C Rx DMA MSize. */
+
+    uint8_t  I2C_RisingTimeNs;            /*!< Specifies the I2C SDA/SCL rising time.
+                                                The unit is ns and must be an integer multiple of clock src period. */
+
+} I2C_InitTypeDef;
+
+/** End of GPIO_Exported_Types
+  * \}
+  */
+
+/*============================================================================*
+ *                         Functions
+ *============================================================================*/
+/** \defgroup I2C_Exported_Functions I2C Exported Functions
+  * \brief
+  * \{
+  */
+
+/**
+ * \brief   Deinitializes the I2Cx peripheral registers to their default reset values.
+ *
+ * \param[in] I2Cx: Select the I2C peripheral. \ref I2C_Declaration
+ *
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_i2c0_init(void)
+ * {
+ *     I2C_DeInit(I2C0);
+ * }
+ * \endcode
+ */
+void I2C_DeInit(I2C_TypeDef *I2Cx);
+
+/**
+ * \brief   Initializes the I2Cx peripheral according to the specified
+ *          parameters in the I2C_InitStruct.
+ *
+ * \param[in] I2Cx: Select the I2C peripheral. \ref I2C_Declaration
+ * \param[in] I2C_InitStruct: Pointer to a I2C_InitTypeDef structure that
+ *            contains the configuration information for the specified I2C peripheral.
+ *
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_i2c0_init(void)
+ * {
+ *     RCC_ClockCmd(I2C0_CLOCK, ENABLE);
+ *
+ *     I2C_InitTypeDef  I2C_InitStruct;
+ *     I2C_StructInit(&I2C_InitStruct);
+ *
+ *     I2C_InitStruct.I2C_ClockSpeed    = 100000;
+ *     I2C_InitStruct.I2C_DeviceMode    = I2C_DeviceMode_Master;
+ *     I2C_InitStruct.I2C_AddressMode   = I2C_AddressMode_7BIT;
+ *     I2C_InitStruct.I2C_SlaveAddress  = STK8321_ADDRESS;
+ *     I2C_InitStruct.I2C_Ack           = I2C_Ack_Enable;
+ *
+ *     I2C_Init(I2C0, &I2C_InitStruct);
+ *     I2C_Cmd(I2C0, ENABLE);
+ * }
+ * \endcode
+ */
+void I2C_Init(I2C_TypeDef *I2Cx, I2C_InitTypeDef *I2C_InitStruct);
+
+/**
+ * \brief  Enable or disable the specified I2C peripheral.
+ *
+ * \param[in] I2Cx: Select the I2C peripheral. \ref I2C_Declaration
+ * \param[in] NewState: New state of the I2Cx peripheral.
+ *            This parameter can be: ENABLE or DISABLE.
+ *
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_i2c0_init(void)
+ * {
+ *     RCC_ClockCmd(I2C0_CLOCK, ENABLE);
+ *
+ *     I2C_InitTypeDef  I2C_InitStruct;
+ *     I2C_StructInit(&I2C_InitStruct);
+ *
+ *     I2C_InitStruct.I2C_ClockSpeed    = 100000;
+ *     I2C_InitStruct.I2C_DeviceMode    = I2C_DeviceMode_Master;
+ *     I2C_InitStruct.I2C_AddressMode   = I2C_AddressMode_7BIT;
+ *     I2C_InitStruct.I2C_SlaveAddress  = STK8321_ADDRESS;
+ *     I2C_InitStruct.I2C_Ack           = I2C_Ack_Enable;
+ *
+ *     I2C_Init(I2C0, &I2C_InitStruct);
+ *     I2C_Cmd(I2C0, ENABLE);
+ * }
+ * \endcode
+ */
+void I2C_Cmd(I2C_TypeDef *I2Cx, FunctionalState NewState);
+
+/**
+ * \brief  Enable or disable the specified I2C peripheral.
+ *
+ * \param[in] I2Cx: Select the I2C peripheral. \ref I2C_Declaration
+ *
+ * \return I2C_Status: The status of I2Cx. \ref I2C_Status
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void i2c0_demo(void)
+ * {
+ *     I2C_CheckAbortStatus(I2C0);
+ * }
+ * \endcode
+ */
+I2C_Status I2C_CheckAbortStatus(I2C_TypeDef *I2Cx);
+
+/**
+ * \brief   Fills each I2C_InitStruct member with its default value.
+ *
+ * \param[in] I2C_InitStruct: Pointer to a I2C_InitTypeDef structure which will be initialized.
+ *
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_i2c0_init(void)
+ * {
+ *     RCC_ClockCmd(I2C0_CLOCK, ENABLE);
+ *
+ *     I2C_InitTypeDef  I2C_InitStruct;
+ *     I2C_StructInit(&I2C_InitStruct);
+ *
+ *     I2C_InitStruct.I2C_ClockSpeed    = 100000;
+ *     I2C_InitStruct.I2C_DeviceMode    = I2C_DeviceMode_Master;
+ *     I2C_InitStruct.I2C_AddressMode   = I2C_AddressMode_7BIT;
+ *     I2C_InitStruct.I2C_SlaveAddress  = STK8321_ADDRESS;
+ *     I2C_InitStruct.I2C_Ack           = I2C_Ack_Enable;
+ *
+ *     I2C_Init(I2C0, &I2C_InitStruct);
+ *     I2C_Cmd(I2C0, ENABLE);
+ * }
+ * \endcode
+ */
+void I2C_StructInit(I2C_InitTypeDef *I2C_InitStruct);
+
+/**
+ * \brief   Send data in master mode through the I2Cx peripheral.
+ *
+ * \param[in] I2Cx: Select the I2C peripheral. \ref I2C_Declaration
+ * \param[in] pBuf: Byte to be transmitted.
+ * \param[in] len: Data length to send.
+ *
+ * \return I2C_Status: The status of I2Cx.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void i2c0_demo(void)
+ * {
+ *     uint8_t data[10] = {0x01,x0x02,0x03,0x04};
+ *     I2C_MasterWrite(I2C0, data, 4);
+ * }
+ * \endcode
+ */
+I2C_Status I2C_MasterWrite(I2C_TypeDef *I2Cx, uint8_t *pBuf, uint16_t len);
+
+/**
+ * rtl876x_i2c.h
+ *
+ * \brief   Read data in master mode through the I2Cx peripheral.
+ *
+ * \param[in] I2Cx: Select the I2C peripheral. \ref I2C_Declaration
+ * \param[in] pBuf: Byte to be transmitted.
+ * \param[in] len: Data length to send.
+ * \param[in] pBuf2: Byte to be transmitted.
+ * \param[in] len2: Data length to send.
+ *
+ * \return I2C status, please refer to \ref I2C_Status.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void i2c0_demo(void)
+ * {
+ *     uint8_t data[10] = {0x01,x0x02,0x03,0x04};
+ *     uint8_t data1[10] = {0x01,x0x02,0x03,0x04};
+ *     I2C_MasterWriteDevice(I2C0, data, 4, data, 4);
+ * }
+ * \endcode
+ */
+I2C_Status I2C_MasterWriteDevice(I2C_TypeDef *I2Cx, uint8_t *pBuf, uint16_t len, uint8_t *pbuf2,
+                                 uint32_t len2);
+
+/**
+ * \brief   Read data in master mode through the I2Cx peripheral.
+ *
+ * \param[in] I2Cx: Select the I2C peripheral. \ref I2C_Declaration
+ * \param[in] pBuf: Data buffer to receive data.
+ * \param[in] len: Read data length.
+ *
+ * \return I2C_Status: The status of I2Cx.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void i2c0_demo(void)
+ * {
+ *     uint8_t data[10] = {0};
+ *     I2C_MasterRead(I2C0, data, 10);
+ * }
+ * \endcode
+ */
+I2C_Status I2C_MasterRead(I2C_TypeDef *I2Cx, uint8_t *pBuf, uint16_t len);
+
+/**
+ * \brief   Sends data and read data in master mode through the I2Cx peripheral.
+ *          Attention:Read data with time out mechanism.
+ *
+ * \param[in] I2Cx: Select the I2C peripheral. \ref I2C_Declaration
+ * \param[in] pWriteBuf: Data buffer to send before read.
+ * \param[in] Writelen: Send data length.
+ * \param[in] pReadBuf: Data buffer to receive.
+ * \param[in] Readlen: Receive data length.
+ *
+ * \return I2C_Status: The status of I2Cx.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void i2c0_demo(void)
+ * {
+ *     uint8_t tx_data[10] = {0x01,x0x02,0x03,0x04};
+ *     uint8_t rx_data[10] = {0};
+ *     I2C_RepeatRead(I2C0, tx_data, 4, rx_data, 10);
+ * }
+ * \endcode
+ */
+I2C_Status I2C_RepeatRead(I2C_TypeDef *I2Cx, uint8_t *pWriteBuf, uint16_t Writelen,
+                          uint8_t *pReadBuf, uint16_t Readlen);
+
+/**
+ * \brief Mask the specified I2C interrupt.
+ *
+ * \param[in] I2Cx: Select the I2C peripheral. \ref I2C_Declaration
+ * \param[in] I2C_IT: This parameter can be one of the following values:
+ *            \arg I2C_INT_MST_ON_HOLD: Indicates whether a master is holding the bus.
+ *            \arg I2C_INT_GEN_CALL: Set only when a General Call address is received and it is acknowledged.
+ *            \arg I2C_INT_START_DET: Indicates whether a START or RESTART condition has occurred on the I2C
+ *                 interface regardless of whether I2C is operating in slave or master mode.
+ *            \arg I2C_INT_STOP_DET: Indicates whether a STOP condition has occurred on the I2C interface regardless
+ *                 of whether I2C is operating in slave or master mode
+ *            \arg I2C_INT_ACTIVITY: This bit captures I2C activity and stays set until it is cleared.
+ *            \arg I2C_INT_RX_DONE: When the I2C is acting as a slave-transmitter, this bit is set to 1 if the
+ *                 master does not acknowledge a transmitted byte. This occurs on the last byte of the
+ *                 transmission, indicating that the transmission is done.
+ *            \arg I2C_INT_TX_ABRT: This bit indicates if I2C as an I2C transmitter, is unable to complete the
+ *                 intended actions on the contents of the transmit FIFO.
+ *            \arg I2C_INT_RD_REQ: This bit is set to 1 when acting as a slave and another I2C master is
+ *                 attempting to read data.
+ *            \arg I2C_INT_TX_EMPTY: This bit is set to 1 when the transmit buffer is at or below the threshold value set
+ *                 in the IC_TX_TL register.
+ *            \arg I2C_INT_TX_OVER: Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH and
+ *                 the processor attempts to issue another I2C command.
+ *            \arg I2C_INT_RX_FULL: Set when the receive buffer reaches or goes above the RX_TL threshold in the
+ *                 IC_RX_TL register
+ *            \arg I2C_INT_RX_OVER: Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and an
+ *                 additional byte is received from an external I2C device.
+ *            \arg I2C_INT_RX_UNDER: Set if the processor attempts to read the receive buffer when it is empty by reading.
+ * \param[in] NewState: Disable or enable I2C interrupt.
+ *
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void i2c0_demo(void)
+ * {
+ *     I2C_ClearINTPendingBit(I2C0, I2C_INT_STOP_DET);
+ *     I2C_INTConfig(I2C0, I2C_INT_STOP_DET, ENABLE);
+ *
+ *     NVIC_InitTypeDef NVIC_InitStruct;
+ *     NVIC_InitStruct.NVIC_IRQChannel = I2C0_IRQn;
+ *     NVIC_InitStruct.NVIC_IRQChannelPriority = 3;
+ *     NVIC_InitStruct.NVIC_IRQChannelCmd = ENABLE;
+ *     NVIC_Init(&NVIC_InitStruct);
+ * }
+ * \endcode
+ */
+void I2C_INTConfig(I2C_TypeDef *I2Cx, uint16_t I2C_IT, FunctionalState NewState);
+
+/**
+ * \brief   Clear the specified I2C interrupt pending bit.
+ *
+ * \param[in] I2Cx: Select the I2C peripheral. \ref I2C_Declaration
+ * \param[in] I2C_IT: This parameter can be one of the following values:
+ *            \arg I2C_INT_GEN_CALL: Set only when a General Call address is received and it is acknowledged.
+ *            \arg I2C_INT_START_DET: Indicates whether a START or RESTART condition has occurred on the I2C
+ *                 interface regardless of whether I2C is operating in slave or master mode.
+ *            \arg I2C_INT_STOP_DET: Indicates whether a STOP condition has occurred on the I2C interface regardless
+ *                 of whether I2C is operating in slave or master mode
+ *            \arg I2C_INT_ACTIVITY: This bit captures I2C activity and stays set until it is cleared.
+ *            \arg I2C_INT_RX_DONE: When the I2C is acting as a slave-transmitter, this bit is set to 1 if the
+ *                 master does not acknowledge a transmitted byte. This occurs on the last byte of the
+ *                 transmission, indicating that the transmission is done.
+ *            \arg I2C_INT_TX_ABRT: This bit indicates if I2C as an I2C transmitter, is unable to complete the
+ *                 intended actions on the contents of the transmit FIFO.
+ *            \arg I2C_INT_RD_REQ: This bit is set to 1 when acting as a slave and another I2C master is
+ *                 attempting to read data.
+ *            \arg I2C_INT_TX_EMPTY: This bit is set to 1 when the transmit buffer is at or below the threshold value set
+ *                 in the IC_TX_TL register.
+ *            \arg I2C_INT_TX_OVER: Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH and
+ *                 the processor attempts to issue another I2C command.
+ *            \arg I2C_INT_RX_FULL: Set when the receive buffer reaches or goes above the RX_TL threshold in the
+ *                 IC_RX_TL register
+ *            \arg I2C_INT_RX_OVER: Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and an
+ *                 additional byte is received from an external I2C device.
+ *            \arg I2C_INT_RX_UNDER: Set if the processor attempts to read the receive buffer when it is empty by reading.
+ *
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void I2C0_Handler(void)
+ * {
+ *     if (I2C_GetINTStatus(I2C0, I2C_INT_STOP_DET) == SET)
+ *     {
+ *         //Add user code here.
+ *         I2C_ClearINTPendingBit(I2C0, I2C_INT_STOP_DET);
+ *     }
+ * }
+ * \endcode
+ */
+void I2C_ClearINTPendingBit(I2C_TypeDef *I2Cx, uint16_t I2C_IT);
+
+/**
+ * \brief   Set slave device address.
+ *
+ * \param[in] I2Cx: Select the I2C peripheral. \ref I2C_Declaration
+ * \param[in] Address: Specifies the slave address which will be transmitte.
+ *
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void i2c0_demo(void)
+ * {
+ *     I2C_SetSlaveAddress(I2C0, 0x55);
+ * }
+ * \endcode
+ */
+void I2C_SetSlaveAddress(I2C_TypeDef *I2Cx, uint16_t Address);
+
+/**
+ * \brief   Write command through the I2Cx peripheral.
+ *
+ * \param[in] I2Cx: Select the I2C peripheral. \ref I2C_Declaration
+ * \param[in] command: Command of write or read.
+ *            \arg I2C_READ_CMD: Read command. Data which want to transmit can be 0 in this situation.
+ *            \arg I2C_WRITE_CMD: Write command.
+ * \param[in] data: Data which to be transmitted.
+ * \param[in] StopState: Whether send stop signal.
+ *            \arg ENABLE: Send stop signal.
+ *            \arg DISABLE: Do not send stop signal.
+ *
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void i2c0_demo(void)
+ * {
+ *     I2C_SendCmd(I2C0, 0x01, 0xAA, ENABLE);
+ * }
+ * \endcode
+ */
+void I2C_SendCmd(I2C_TypeDef *I2Cx, I2CSendCommend_TypeDef command, uint8_t data,
+                 FunctionalState StopState);
+
+/**
+ * \brief  Received data by the I2Cx peripheral.
+ *
+ * \param[in] I2Cx: Select the I2C peripheral. \ref I2C_Declaration
+ *
+ * \return Return the most recent received data.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void i2c0_demo(void)
+ * {
+ *     uint8_t data = I2C_ReceiveData(I2C0);
+ * }
+ * \endcode
+ */
+uint8_t I2C_ReceiveData(I2C_TypeDef *I2Cx);
+
+/**
+ * \brief   Get data length in Rx FIFO of the I2Cx peripheral.
+ *
+ * \param[in] I2Cx: Select the I2C peripheral. \ref I2C_Declaration
+ *
+ * \return  Current data number in Rx FIFO.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void i2c0_demo(void)
+ * {
+ *     uint8_t data_len = I2C_GetRxFIFOLen(I2C0);
+ * }
+ * \endcode
+ */
+uint8_t I2C_GetRxFIFOLen(I2C_TypeDef *I2Cx);
+
+/**
+ * \brief   Get data length in Tx FIFO of the I2Cx peripheral.
+ *
+ * \param[in] I2Cx: Select the I2C peripheral. \ref I2C_Declaration
+ *
+ * \return  Current data number in Tx FIFO.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void i2c0_demo(void)
+ * {
+ *     uint8_t data_len = I2C_GetTxFIFOLen(I2C0);
+ * }
+ * \endcode
+ */
+uint8_t I2C_GetTxFIFOLen(I2C_TypeDef *I2Cx);
+
+/**
+ * \brief   Clear all I2C interrupt.
+ *
+ * \param[in] I2Cx: Select the I2C peripheral. \ref I2C_Declaration
+ *
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void i2c0_demo(void)
+ * {
+ *     I2C_ClearAllINT(I2C0);
+ * }
+ * \endcode
+ */
+void I2C_ClearAllINT(I2C_TypeDef *I2Cx);
+
+/**
+ * \brief  Check whether the specified I2C flag is set.
+ *
+ * \param[in] I2Cx: Select the I2C peripheral. \ref I2C_Declaration
+ * \param[in] I2C_FLAG: Specifies the flag to check.
+ *            This parameter can be one of the following values:
+ *            \arg I2C_FLAG_SLV_HOLD_RX_FIFO_FULL: The BUS Hold in Slave mode due to the Rx FIFO being Full and an additional byte being received.
+ *            \arg I2C_FLAG_SLV_HOLD_TX_FIFO_EMPTY: The BUS Hold in Slave mode for the Read request when the Tx FIFO is empty.
+ *            \arg I2C_FLAG_MST_HOLD_RX_FIFO_FULL: The BUS Hold in Master mode due to Rx FIFO is full and additional byte has been received.
+ *            \arg I2C_FLAG_MST_HOLD_TX_FIFO_EMPTY: The BUS hold when the master holds the bus because of the Tx FIFO being empty.
+ *            \arg I2C_FLAG_SLV_ACTIVITY: Slave FSM activity status.
+ *            \arg I2C_FLAG_MST_ACTIVITY: Master FSM activity status.
+ *            \arg I2C_FLAG_RFF: Receive FIFO completely full.
+ *            \arg I2C_FLAG_RFNE: Receive FIFO not empty.
+ *            \arg I2C_FLAG_TFE: Transmit FIFO completely empty.
+ *            \arg I2C_FLAG_TFNF: Transmit FIFO not full.
+ *            \arg I2C_FLAG_ACTIVITY: I2C activity status.
+ *
+ * \return  The new state of I2C_FLAG (SET or RESET).
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void i2c0_demo(void)
+ * {
+ *     FlagStatus flag_status = I2C_GetFlagState(I2C0, I2C_FLAG_RFF);
+ * }
+ * \endcode
+ */
+FlagStatus I2C_GetFlagState(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG);
+
+/**
+ * \brief  Check whether the last I2Cx event is equal to the one passed as parameter.
+ *
+ * \param[in] I2Cx: Select the I2C peripheral. \ref I2C_Declaration
+ * \param[in] I2C_EVENT: specifies the event to be checked about I2C Transmit Abort Status Register.
+ *            This parameter can be one of the following values:
+ *            \arg ABRT_SLVRD_INTX: When the processor side responds to a slave mode request for data to be transmitted to a remote master and user send read command.
+ *            \arg ABRT_SLV_ARBLOST: Slave lost the bus while transmitting data to a remote master.
+ *            \arg ABRT_SLVFLUSH_TXFIFO: Slave has received a read command and some data exists in the TX FIFO so the slave issues a TX_ABRT interrupt to flush old data in TX FIFO.
+ *            \arg ARB_LOST: Master has lost arbitration or the slave transmitter has lost arbitration.
+ *            \arg ABRT_MASTER_DIS: User tries to initiate a Master operation with the Master mode disabled
+ *            \arg ABRT_10B_RD_NORSTRT: The restart is disabled and the master sends a read command in 10-bit addressing mode.
+ *            \arg ABRT_SBYTE_NORSTRT: The restart is disabled and the user is trying to send a START Byte.
+ *            \arg ABRT_HS_NORSTRT: The restart is disabled and the user is trying to use the master to transfer data in High Speed mode.
+ *            \arg ABRT_SBYTE_ACKDET: Master has sent a START Byte and the START Byte was acknowledged (wrong behavior).
+ *            \arg ABRT_HS_ACKDET: Master is in High Speed mode and the High Speed Master code was acknowledged (wrong behavior).
+ *            \arg ABRT_GCALL_READ: Sent a General Call but the user programmed the byte following the General Call to be a read from the bus.
+ *            \arg ABRT_GCALL_NOACK: Sent a General Call and no slave on the bus acknowledged the General Call.
+ *            \arg ABRT_TXDATA_NOACK: Master sent data byte(s) following the address, it did not receive an acknowledge from the remote slave.
+ *            \arg ABRT_10ADDR2_NOACK: Master is in 10-bit address mode and the second address byte of the 10-bit address was not acknowledged by any slave.
+ *            \arg ABRT_10ADDR1_NOACK: Master is in 10-bit address mode and the first 10-bit address byte was not acknowledged by any slave.
+ *            \arg ABRT_7B_ADDR_NOACK: Master is in 7-bit addressing mode and th address sent was not acknowledged by any slave.
+ *
+ * \return  An ErrorStatus enumeration value.
+ * \retval  SUCCESS: Last event is equal to the I2C_EVENT.
+ * \retval  ERROR: Last event is different from the I2C_EVENT.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void i2c0_demo(void)
+ * {
+ *     FlagStatus flag_status = I2C_CheckEvent(I2C0, ABRT_SLVRD_INTX);
+ * }
+ * \endcode
+ */
+FlagStatus I2C_CheckEvent(I2C_TypeDef *I2Cx, uint32_t I2C_EVENT);
+
+/**
+ * \brief   Get the specified I2C interrupt status.
+ *
+ * \param[in] I2Cx: Select the I2C peripheral. \ref I2C_Declaration
+ * \param[in] I2C_IT: This parameter can be one of the following values:
+ *            \arg I2C_INT_MST_ON_HOLD: Indicates whether a master is holding the bus.
+ *            \arg I2C_INT_GEN_CALL: Set only when a General Call address is received and it is acknowledged.
+ *            \arg I2C_INT_START_DET: Indicates whether a START or RESTART condition has occurred on the I2C
+ *                 interface regardless of whether DW_apb_i2c is operating in slave or master mode.
+ *            \arg I2C_INT_STOP_DET: Indicates whether a STOP condition has occurred on the I2C interface regardless
+ *                 of whether DW_apb_i2c is operating in slave or master mode
+ *            \arg I2C_INT_ACTIVITY: This bit captures DW_apb_i2c activity and stays set until it is cleared.
+ *            \arg I2C_INT_RX_DONE: When the DW_apb_i2c is acting as a slave-transmitter, this bit is set to 1 if the
+ *                 master does not acknowledge a transmitted byte. This occurs on the last byte of
+ *                 the transmission, indicating that the transmission is done.
+ *            \arg I2C_INT_TX_ABRT: This bit indicates if DW_apb_i2c, as an I2C transmitter, is unable to complete the
+ *                 intended actions on the contents of the transmit FIFO.
+ *            \arg I2C_INT_RD_REQ: This bit is set to 1 when acting as a slave and another I2C master
+ *                 is attempting to read data.
+ *            \arg I2C_INT_TX_EMPTY: This bit is set to 1 when the transmit buffer is at or below the threshold value set
+ *                 in the IC_TX_TL register.
+ *            \arg I2C_INT_TX_OVER: Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH and
+ *                 the processor attempts to issue another I2C command.
+ *            \arg I2C_INT_RX_FULL: Set when the receive buffer reaches or goes above the RX_TL threshold in the
+ *                 IC_RX_TL register
+ *            \arg I2C_INT_RX_OVER: Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and an
+ *                 additional byte is received from an external I2C device.
+ *            \arg I2C_INT_RX_UNDER: Set if the processor attempts to read the receive buffer when it is empty by reading.
+ *
+ * \return  The new state of I2C_IT (SET or RESET).
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void i2c0_demo(void)
+ * {
+ *     ITStatus int_status = I2C_GetINTStatus(I2C0, I2C_INT_RD_REQ);
+ * }
+ * \endcode
+ */
+ITStatus I2C_GetINTStatus(I2C_TypeDef *I2Cx, uint32_t I2C_IT);
+
+/**
+ * \brief   Enable or disable the I2Cx DMA interface.
+ *
+ * \param[in] I2Cx: Select the I2C peripheral. \ref I2C_Declaration
+ * \param[in] I2C_DMAReq: Specifies the I2C DMA transfer request to be enabled or disabled.
+ *            This parameter can be one of the following values:
+ *            \arg I2C_DMAReq_Tx: Tx buffer DMA transfer request.
+ *            \arg I2C_DMAReq_Rx: Rx buffer DMA transfer request.
+ * \param[in] NewState: New state of the selected I2C DMA transfer request.
+ *            This parameter can be: ENABLE or DISABLE.
+ *
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void i2c0_demo(void)
+ * {
+ *     I2C_DMACmd(I2C0, I2C_DMAReq_Tx, ENABLE);
+ * }
+ * \endcode
+ */
+void I2C_DMACmd(I2C_TypeDef *I2Cx, I2CDMARequests_TypeDef I2C_DMAReq,
+                FunctionalState NewState);
+
+/**
+ * \brief   Set the I2C clock speed, the function need to be called when I2C disabled.
+ *
+ * \param[in] I2Cx: Select the I2C peripheral. \ref I2C_Declaration
+ * \param[in] I2C_ClockSpeed: Secified the I2C interrupt sources.
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void i2c_demo(void)
+ * {
+ *     I2C_SetClockSpeed(I2C0, 400000);
+ * }
+ * \endcode
+ */
+void I2C_SetClockSpeed(I2C_TypeDef *I2Cx, uint32_t I2C_ClockSpeed);
+
+/**
+ * \brief  I2C clock divider config.
+ *
+ * \param[in] I2Cx: Select the I2C peripheral. \ref I2C_Declaration
+ * \param[in] ClockDiv: Specifies the I2C clock divider.
+ *            This parameter can be one of the following values:
+ *            \arg CLOCK_DIV_x: where x can refer to CLock Divider to select the specified clock divider
+ *
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_i2c_init(void)
+ * {
+ *     I2C_SetClock(I2C0, I2C_CLOCK_SRC_40M, I2C_CLOCK_DIV_1);
+ * }
+ * \endcode
+ */
+void I2C_SetClock(I2C_TypeDef *I2Cx, uint16_t ClockSrc, uint16_t ClockDiv);
+
+
+#if (I2C_SUPPORT_WRAPPER_MODE == 1)
+
+void I2C_WrapperModeCmd(I2C_TypeDef *I2Cx, FunctionalState NewState);
+
+bool I2C_WrapperSetTransMode(I2C_TypeDef *I2Cx, uint32_t mode);
+
+void I2C_WrapperSetWriteNum(I2C_TypeDef *I2Cx, uint8_t num);
+
+void I2C_WrapperSetWriteData(I2C_TypeDef *I2Cx, const uint8_t *buf, uint8_t num);
+
+uint8_t I2C_WrapperGetTxFIFOLen(I2C_TypeDef *I2Cx);
+
+void I2C_WrapperClearTxFIFO(I2C_TypeDef *I2Cx);
+
+void I2C_WrapperSetReadNum(I2C_TypeDef *I2Cx, uint16_t num);
+
+uint8_t I2C_WrapperReceiveData(I2C_TypeDef *I2Cx);
+
+uint8_t I2C_WrapperGetRxFIFOLen(I2C_TypeDef *I2Cx);
+
+void I2C_WrapperTransStart(I2C_TypeDef *I2Cx);
+
+bool I2C_WrapperBusyCheck(I2C_TypeDef *I2Cx);
+#endif
+
+#if (I2C_SUPPORT_RAP_FUNCTION == 1)
+
+void I2C_RAPModeCmd(I2C_TypeDef *I2Cx, FunctionalState NewState);
+
+void I2C_ActionTrigger(I2C_TypeDef *I2Cx, uint32_t Action);
+
+#endif
+
+#if (I2C_SUPPORT_AUTO_CLOCK == 1)
+
+void I2C_SetClockAutoMode(I2C_TypeDef *I2Cx, uint32_t AutoMode);
+
+#endif
+
+/** End of I2C_Exported_Functions
+  * \}
+  */
+
+/** End of I2C
+  * \}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*RTL_I2C_H*/
+
+
+
+
diff --git a/bee/drivers/i2c/src/CMakeLists.txt b/bee/drivers/i2c/src/CMakeLists.txt
new file mode 100644
index 00000000..dd5e359a
--- /dev/null
+++ b/bee/drivers/i2c/src/CMakeLists.txt
@@ -0,0 +1,4 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+add_subdirectory(device)
diff --git a/bee/drivers/i2c/src/device/CMakeLists.txt b/bee/drivers/i2c/src/device/CMakeLists.txt
new file mode 100644
index 00000000..390b5305
--- /dev/null
+++ b/bee/drivers/i2c/src/device/CMakeLists.txt
@@ -0,0 +1,11 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+if(CONFIG_REALTEK_BEE_COMMON_DRIVER)
+    file(GLOB BEE_DRIVER_COMMON_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/rtl_common/*.c")
+    zephyr_library_sources(${BEE_DRIVER_COMMON_SOURCES})
+endif()
+
+add_soc_series_subdir(rtl8752h)
+add_soc_series_subdir(rtl87x2g)
+add_soc_series_subdir(rtl87x2j)
diff --git a/bee/drivers/i2c/src/device/rtl8752h/rtl876x_i2c.c b/bee/drivers/i2c/src/device/rtl8752h/rtl876x_i2c.c
new file mode 100644
index 00000000..2d6dcc10
--- /dev/null
+++ b/bee/drivers/i2c/src/device/rtl8752h/rtl876x_i2c.c
@@ -0,0 +1,834 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "rtl876x_rcc.h"
+#include "rtl876x_i2c.h"
+#include "app_section.h"
+
+/* Private defines -----------------------------------------------------------*/
+/* I2C Data Cmd Mask */
+#define I2C_CMD_READ_BIT                             (BIT8)
+#define I2C_CMD_STOP_BIT                             (BIT9)
+#define I2C_CMD_RESTART_BIT                          (BIT10)
+
+/* SDA Setup Time */
+#define I2C_SDA_SETUP_TIME_VALUE                     (2)
+/* Rising Time */
+#define I2C_RISING_TIME_NS                           (50)
+/* SCL Low/High Period Time */
+#define I2C_SCL_HIGH_PERIOD_COMPENSATE               (7)
+#define I2C_SCL_LOW_PERIOD_COMPENSATE                (1)
+#define NS_PER_SECOND                                (1000000000)
+
+/* I2C SCL High/Low min period according to spec */
+#define I2C_FAST_MODE_PLUS_SCL_LOW_PERIOD_MIN_NS     (500)
+#define I2C_FAST_MODE_PLUS_SCL_HIGH_PERIOD_MIN_NS    (260)
+#define I2C_FAST_MODE_SCL_LOW_PERIOD_MIN_NS          (1300)
+#define I2C_FAST_MODE_SCL_HIGH_PERIOD_MIN_NS         (600)
+#define I2C_STANDARD_MODE_SCL_LOW_PERIOD_MIN_NS      (4700)
+#define I2C_STANDARD_MODE_SCL_HIGH_PERIOD_MIN_NS     (4000)
+/* SDA Hold Time */
+#define I2C_STANDARD_FAST_MODE_SDA_HOLD_TIME_NS      (600)
+#define I2C_FAST_MODE_PLUS_SDA_HOLD_TIME_NS          (300)
+
+#define ROUNDUP(a, b)                                (((a + b - 1) / b))
+
+uint32_t I2CSrcClk;
+uint32_t I2C_TimeOut = 0xFFF;
+void I2C_SetClockSpeed(I2C_TypeDef *I2Cx, uint32_t I2C_ClockSpeed);
+
+/**
+  * @brief  Initializes the I2Cx peripheral according to the specified
+  *   parameters in the I2C_InitStruct.
+  * @param  I2Cx: where x can be 0 or 1 to select the I2C peripheral.
+  * @param  I2C_InitStruct: pointer to a I2C_InitTypeDef structure that
+  *   contains the configuration information for the specified I2C peripheral.
+  * @retval None
+  */
+void I2C_Init(I2C_TypeDef *I2Cx, I2C_InitTypeDef *I2C_InitStruct)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+    assert_param(IS_I2C_CLOCK_SPEED(I2C_InitStruct->I2C_ClockSpeed));
+
+    I2CSrcClk = I2C_InitStruct->I2C_Clock;
+    /* Disable I2C device before change configuration */
+    I2Cx->IC_ENABLE &= ~0x0001;
+
+    /* Config sda tx hold time in different clock speed */
+    uint8_t sda_tx_hold = 0;
+    /* Tick of I2C clock source in ns. */
+    uint32_t tick_clksrc_ns = NS_PER_SECOND / I2CSrcClk;
+
+    switch (I2CSrcClk)
+    {
+    case 40000000:
+        if (I2C_InitStruct->I2C_ClockSpeed <= 400000)
+        {
+            sda_tx_hold = I2C_STANDARD_FAST_MODE_SDA_HOLD_TIME_NS / tick_clksrc_ns;
+        }
+        else
+        {
+            sda_tx_hold = I2C_FAST_MODE_PLUS_SDA_HOLD_TIME_NS / tick_clksrc_ns;
+        }
+        break;
+    case 20000000:
+        sda_tx_hold = I2C_STANDARD_FAST_MODE_SDA_HOLD_TIME_NS / tick_clksrc_ns;
+        break;
+    case 10000000:
+        sda_tx_hold = I2C_STANDARD_FAST_MODE_SDA_HOLD_TIME_NS / tick_clksrc_ns;
+        break;
+    case 5000000:
+        sda_tx_hold = I2C_STANDARD_FAST_MODE_SDA_HOLD_TIME_NS / tick_clksrc_ns;
+        break;
+    default:
+        break;
+    }
+
+    /* ------------------------------ Initialize I2C device ------------------------------*/
+    if (I2C_DeviveMode_Master == I2C_InitStruct->I2C_DeviveMode)
+    {
+        /*configure I2C device mode which can be selected for master or slave*/
+        I2Cx->IC_CON = I2C_InitStruct->I2C_DeviveMode | (I2C_InitStruct->I2C_AddressMode << 4) | BIT(5);
+
+        /*set target address*/
+        I2Cx->IC_TAR = (I2C_InitStruct->I2C_SlaveAddress & 0x3ff)
+                       | (I2C_InitStruct->I2C_AddressMode << 12);
+        /*set SDA hold time in master mode*/
+        I2Cx->IC_SDA_HOLD = (0x1 << 16) | (sda_tx_hold);
+
+        /* Configure I2C speed */
+        I2C_SetClockSpeed(I2Cx, I2C_InitStruct->I2C_ClockSpeed);
+    }
+    else
+    {
+        /* set to slave mode */
+        I2Cx->IC_CON = (I2C_InitStruct->I2C_DeviveMode) | (I2C_InitStruct->I2C_AddressMode << 3);
+        /* set Ack in slave mode */
+        I2Cx->IC_ACK_GENERAL_CALL &= I2C_InitStruct->I2C_Ack;
+        /* set slave address */
+        I2Cx->IC_SAR = I2C_InitStruct->I2C_SlaveAddress;
+        /* set SDA hold time in slave mode */
+        I2Cx->IC_SDA_HOLD = (0x08 << 16) | (sda_tx_hold);
+        /* set SDA setup time delay only in slave transmitter mode(greater than 2) ,delay time:[(IC_SDA_SETUP - 1) * (ic_clk_period)]*/
+        I2Cx->IC_SDA_SETUP = I2C_SDA_SETUP_TIME_VALUE;
+    }
+
+#if 1
+    /*set Tx empty level*/
+    I2Cx->IC_TX_TL = I2C_InitStruct->I2C_TxThresholdLevel;
+    /*set Rx full level*/
+    I2Cx->IC_RX_TL = I2C_InitStruct->I2C_RxThresholdLevel;
+#endif
+
+    /*Config I2C dma mode*/
+    I2Cx->IC_DMA_CR = ((I2C_InitStruct->I2C_RxDmaEn)\
+                       | ((I2C_InitStruct->I2C_TxDmaEn) << 1));
+
+    /*Config I2C waterlevel*/
+    I2Cx->IC_DMA_RDLR = I2C_InitStruct->I2C_RxWaterlevel;
+    I2Cx->IC_DMA_TDLR = I2C_InitStruct->I2C_TxWaterlevel;
+
+    I2Cx->IC_INTR_MASK = 0;
+}
+
+/**
+  * @brief  Deinitializes the I2Cx peripheral registers to their default reset values.
+  * @param  I2Cx: where x can be 0 or 1 to select the I2C peripheral.
+  * @retval None
+  */
+void I2C_DeInit(I2C_TypeDef *I2Cx)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+    /*Disable I2C IP*/
+    if (I2Cx == I2C0)
+    {
+        RCC_PeriphClockCmd(APBPeriph_I2C0, APBPeriph_I2C0_CLOCK, DISABLE);
+    }
+    else if (I2Cx == I2C1)
+    {
+        RCC_PeriphClockCmd(APBPeriph_I2C1, APBPeriph_I2C1_CLOCK, DISABLE);
+    }
+}
+
+/**
+  * @brief  Fills each I2C_InitStruct member with its default value.
+  * @param  I2C_InitStruct : pointer to a I2C_InitTypeDef structure which will be initialized.
+  * @retval None
+  */
+void I2C_StructInit(I2C_InitTypeDef *I2C_InitStruct)
+{
+    I2C_InitStruct->I2C_Clock             = 40000000;               /* depend on clock divider */
+    I2C_InitStruct->I2C_ClockSpeed        = 400000;
+    I2C_InitStruct->I2C_DeviveMode        = I2C_DeviveMode_Master;  /* Master mode */
+    I2C_InitStruct->I2C_AddressMode       = I2C_AddressMode_7BIT;   /* 7-bit address mode */
+    I2C_InitStruct->I2C_SlaveAddress      = 0;
+    I2C_InitStruct->I2C_Ack               = I2C_Ack_Enable;
+    I2C_InitStruct->I2C_TxThresholdLevel  = 0x00;                 /* tx fifo depth: 24 * 8bits */
+    I2C_InitStruct->I2C_RxThresholdLevel  = 0x00;                 /* rx fifo depth: 40 * 8bits */
+    I2C_InitStruct->I2C_TxDmaEn           = DISABLE;
+    I2C_InitStruct->I2C_RxDmaEn           = DISABLE;
+    I2C_InitStruct->I2C_RxWaterlevel      = 1;                    /* Best to equal GDMA Source MSize */
+    I2C_InitStruct->I2C_TxWaterlevel      = 15;                   /* Best to equal Tx fifo minus
+                                                                      GDMA Dest MSize */
+}
+
+
+/**
+  * @brief  Enables or disables the specified I2C peripheral.
+  * @param  I2Cx: where x can be 0 or 1 to select the I2C peripheral.
+  * @param  NewState: new state of the I2Cx peripheral.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_Cmd(I2C_TypeDef *I2Cx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (NewState != DISABLE)
+    {
+        /* Enable the selected I2C peripheral */
+        I2Cx->IC_ENABLE |= 0x0001;
+    }
+    else
+    {
+        /* Disable the selected I2C peripheral */
+        I2Cx->IC_ENABLE &= ~0x0001;
+    }
+}
+
+
+/**
+  * @brief  Checks whether the last I2Cx abort status.
+  * @param  I2Cx: where x can be 0 or 1 to select the I2C peripheral.
+  * @retval the status of I2Cx.
+  */
+I2C_Status I2C_CheckAbortStatus(I2C_TypeDef *I2Cx)
+{
+    uint32_t abort_status = 0;
+
+    /* Check the parameters */
+    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+    /* Get abort status */
+    abort_status = I2Cx->IC_TX_ABRT_SOURCE;
+
+    if (abort_status & MS_ALL_ABORT)
+    {
+        /* Clear abort status */
+        (void)I2Cx->IC_CLR_TX_ABRT;
+
+        /* Check abort type */
+        if (abort_status & ABRT_TXDATA_NOACK)
+        {
+            return I2C_ABRT_TXDATA_NOACK;
+        }
+
+        if (abort_status & ABRT_7B_ADDR_NOACK)
+        {
+            return I2C_ABRT_7B_ADDR_NOACK;
+        }
+
+        if (abort_status & ARB_LOST)
+        {
+            return I2C_ARB_LOST;
+        }
+
+        if (abort_status & ABRT_MASTER_DIS)
+        {
+            return I2C_ABRT_MASTER_DIS;
+        }
+
+        if (abort_status & ABRT_10ADDR1_NOACK)
+        {
+            return I2C_ABRT_10ADDR1_NOACK;
+        }
+
+        if (abort_status & ABRT_10ADDR2_NOACK)
+        {
+            return I2C_ABRT_10ADDR2_NOACK;
+        }
+    }
+
+    return I2C_Success;
+}
+
+
+I2C_Status I2C_WaitForFIFO(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG)
+{
+    uint32_t timeout = I2C_TimeOut;
+
+    /* Wait until the FIFO condition selected by I2C_FLAG becomes true:
+     * - TX: writable (TX FIFO Not Full, space available)
+     * - RX: readable (RX FIFO Not Empty, data available)
+     */
+    while (((I2Cx->IC_STATUS & I2C_FLAG) == 0) && (timeout != 0))
+    {
+        I2C_Status status = I2C_CheckAbortStatus(I2Cx);
+        if (status != I2C_Success)
+        {
+            return status;
+        }
+
+        if (--timeout == 0)
+        {
+            return I2C_ERR_TIMEOUT;
+        }
+    }
+
+    return I2C_CheckAbortStatus(I2Cx);
+}
+
+I2C_Status I2C_WaitTXIdle(I2C_TypeDef *I2Cx)
+{
+    uint32_t timeout = I2C_TimeOut;
+
+    /* Wait until the transmit is fully completed:
+     * - Bus becomes idle (ACTIVITY == 0)
+     * - TX FIFO is empty (TFE == 1)
+     */
+    while ((((I2Cx->IC_STATUS & I2C_FLAG_ACTIVITY) != 0) ||
+            ((I2Cx->IC_STATUS & I2C_FLAG_TFE) == 0)) &&
+           (timeout != 0))
+    {
+        I2C_Status status = I2C_CheckAbortStatus(I2Cx);
+        if (status != I2C_Success)
+        {
+            return status;
+        }
+
+        if (--timeout == 0)
+        {
+            return I2C_ERR_TIMEOUT;
+        }
+    }
+
+    return I2C_Success;
+}
+
+/**
+  * \brief  Send data in master mode through the I2Cx peripheral.
+  * \param  I2Cx: Select the I2C peripheral. \ref I2C_Declaration
+  * \param  pBuf: Byte to be transmitted.
+  * \param  len: Data length to send.
+  * \return I2C_Status: The status of I2Cx. \ref I2C_Status
+  */
+I2C_Status I2C_MasterWrite(I2C_TypeDef *I2Cx, uint8_t *pBuf, uint16_t len)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+    I2C_Status status = I2C_Success;
+
+    for (uint16_t i = 0; i < len; i++)
+    {
+        uint32_t cmd = *pBuf++;
+        if (i == (len - 1))
+        {
+            cmd |= I2C_CMD_STOP_BIT;
+        }
+        I2Cx->IC_DATA_CMD = cmd;
+
+        status = I2C_WaitForFIFO(I2Cx, I2C_FLAG_TFNF);
+        if (status != I2C_Success)
+        {
+            return status;
+        }
+    }
+
+    return I2C_WaitTXIdle(I2Cx);
+}
+
+/**
+  * \brief  Read data in master mode through the I2Cx peripheral.
+  * \param  I2Cx: Select the I2C peripheral. \ref I2C_Declaration
+  * \param  pBuf: Data buffer to receive data.
+  * \param  len: Read data length.
+  * \return I2C_Status: The status of I2Cx. \ref I2C_Status
+  */
+I2C_Status I2C_MasterRead(I2C_TypeDef *I2Cx, uint8_t *pBuf, uint16_t len)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+    I2C_Status status = I2C_Success;
+
+    if (len == 0)
+    {
+        return status;
+    }
+
+    /* Issue the first read cmd. If only one byte is requested, append STOP immediately. */
+    uint32_t cmd = 0x0 | I2C_CMD_READ_BIT;
+    if (len == 1)
+    {
+        cmd |= I2C_CMD_STOP_BIT;
+    }
+    I2Cx->IC_DATA_CMD = cmd;
+
+    for (uint16_t i = 1; i < len; i++)
+    {
+        /* Issue the remaining read cmd. */
+        cmd = 0x0 | I2C_CMD_READ_BIT;
+        if (i == (len - 1))
+        {
+            cmd |= I2C_CMD_STOP_BIT;
+        }
+        I2Cx->IC_DATA_CMD = cmd;
+
+        /* Read byte produced by the read. */
+        status = I2C_WaitForFIFO(I2Cx, I2C_FLAG_RFNE);
+        if (status != I2C_Success)
+        {
+            return status;
+        }
+        *pBuf++ = (uint8_t)I2Cx->IC_DATA_CMD;
+    }
+
+    /* Read the final byte produced by the last command. */
+    status = I2C_WaitForFIFO(I2Cx, I2C_FLAG_RFNE);
+    if (status != I2C_Success)
+    {
+        return status;
+    }
+    *pBuf = (uint8_t)I2Cx->IC_DATA_CMD;
+
+    return status;
+}
+
+/**
+  * \brief  Sends data and read data in master mode through the I2Cx peripheral.Attention:Read data with time out mechanism.
+  * \param  I2Cx: Select the I2C peripheral. \ref I2C_Declaration
+  * \param  pWriteBuf: Data buffer to send before read.
+  * \param  Writelen: Send data length.
+  * \param  pReadBuf: Data buffer to receive.
+  * \param  Readlen: Receive data length.
+  * \return I2C_Status: The status of I2Cx. \ref I2C_Status
+  */
+I2C_Status I2C_RepeatRead(I2C_TypeDef *I2Cx, uint8_t *pWriteBuf, uint16_t Writelen,
+                          uint8_t *pReadBuf, uint16_t Readlen)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+    I2C_Status status = I2C_Success;
+
+    for (uint16_t i = 0; i < Writelen; i++)
+    {
+        I2Cx->IC_DATA_CMD = *pWriteBuf++;
+
+        status = I2C_WaitForFIFO(I2Cx, I2C_FLAG_TFNF);
+        if (status != I2C_Success)
+        {
+            return status;
+        }
+    }
+
+    for (uint16_t i = 0; i < Readlen; i++)
+    {
+        /* Issue the read cmd. */
+        uint32_t cmd = 0x0 | I2C_CMD_READ_BIT;
+        if (i == (Readlen - 1))
+        {
+            cmd |= I2C_CMD_STOP_BIT;
+        }
+        I2Cx->IC_DATA_CMD = cmd;
+
+        /* Read byte produced by the read. */
+        status = I2C_WaitForFIFO(I2Cx, I2C_FLAG_RFNE);
+        if (status != I2C_Success)
+        {
+            return status;
+        }
+        *pReadBuf++ = (uint8_t)I2Cx->IC_DATA_CMD;
+    }
+
+
+    return status;
+}
+
+/**
+  * @brief mask the specified I2C interrupt.
+  * @param  I2Cx: where x can be 0 or 1 to select the I2C peripheral.
+  * @param  I2C_INT
+  * This parameter can be one of the following values:
+  *     @arg I2C_INT_GEN_CALL: When a General Call address is received and it is acknowledged.
+  *     @arg I2C_INT_START_DET: When a START or RESTART condition has occurred on the I2C interface
+  *                            regardless of whether I2C is operating in slave or master mode.
+  *     @arg I2C_INT_STOP_DET: When a STOP condition has occurred on the I2C interface
+  *                            regardless of whether I2C is operating in slave or master mode.
+  *     @arg I2C_INT_ACTIVITY: When I2C is activity on the bus. Stays set until it is cleared.
+  *     @arg I2C_INT_RX_DONE: When the I2C is acting as a slave-transmitter and the master does
+  *                           not acknowledge a transmitted byte.
+  *                           This occurs on the last byte of the transmission,
+  *                           indicating that the transmission is done.
+  *     @arg I2C_INT_TX_ABRT: When an I2C transmitter is unable to complete the intended actions
+  *                           on the contents of the transmit FIFO.
+  *     @arg I2C_INT_RD_REQ:  When I2C is acting as a slave and another I2C master is attempting to read data from I2C.
+  *     @arg I2C_INT_TX_EMPTY: When the transmit buffer is at or below the threshold value set in the REG_IC_TXFLR register.
+  *     @arg I2C_INT_TX_OVER: When transmit buffer is filled to IC_TX_BUFFER_DEPTH and
+  *                           the processor attempts to issue another I2C command by writing to the REG_IC_DATA_CMD register.
+  *     @arg I2C_INT_RX_FULL: When the receive buffer reaches or goes above the RX_TL threshold in the REG_IC_RX_TL register.
+  *                           A value of 0 sets the threshold for 1 entry, and a value of 255 sets the threshold for 256 entries.
+  *     @arg I2C_INT_RX_OVER: When the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and
+  *                           an additional byte is received from an external I2C device.
+  *     @arg I2C_INT_RX_UNDER: When the processor attempts to read the receive buffer
+  *                            when it is empty by reading from the REG_IC_DATA_CMD register.
+  * @retval None.
+  */
+void I2C_INTConfig(I2C_TypeDef *I2Cx, uint16_t I2C_INT, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+    assert_param(I2C_GET_INT(I2C_INT));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (NewState != DISABLE)
+    {
+        /* Enable the selected I2C interrupts */
+        I2Cx->IC_INTR_MASK |= I2C_INT;
+    }
+    else
+    {
+        /* Disable the selected I2C interrupts */
+        I2Cx->IC_INTR_MASK &= (uint16_t)~I2C_INT;
+    }
+}
+
+/**
+  * @brief Clear the specified I2C interrupt.
+  * @param  I2Cx: where x can be 0 or 1 to select the I2C peripheral.
+  * @param  I2C_INT
+  * This parameter can be one of the following values:
+  *     @arg I2C_INT_GEN_CALL: When a General Call address is received and it is acknowledged.
+  *     @arg I2C_INT_START_DET: When a START or RESTART condition has occurred on the I2C interface
+  *                            regardless of whether I2C is operating in slave or master mode.
+  *     @arg I2C_INT_STOP_DET: When a STOP condition has occurred on the I2C interface
+  *                            regardless of whether I2C is operating in slave or master mode.
+  *     @arg I2C_INT_ACTIVITY: When I2C is activity on the bus. Stays set until it is cleared.
+  *     @arg I2C_INT_RX_DONE: When the I2C is acting as a slave-transmitter and the master does
+  *                           not acknowledge a transmitted byte.
+  *                           This occurs on the last byte of the transmission,
+  *                           indicating that the transmission is done.
+  *     @arg I2C_INT_TX_ABRT: When an I2C transmitter is unable to complete the intended actions
+  *                           on the contents of the transmit FIFO.
+  *     @arg I2C_INT_RD_REQ:  When I2C is acting as a slave and another I2C master is attempting to read data from I2C.
+  *     @arg I2C_INT_TX_EMPTY: When the transmit buffer is at or below the threshold value set in the REG_IC_TXFLR register.
+  *     @arg I2C_INT_TX_OVER: When transmit buffer is filled to IC_TX_BUFFER_DEPTH and
+  *                           the processor attempts to issue another I2C command by writing to the REG_IC_DATA_CMD register.
+  *     @arg I2C_INT_RX_FULL: When the receive buffer reaches or goes above the RX_TL threshold in the REG_IC_RX_TL register.
+  *                           A value of 0 sets the threshold for 1 entry, and a value of 255 sets the threshold for 256 entries.
+  *     @arg I2C_INT_RX_OVER: When the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and
+  *                           an additional byte is received from an external I2C device.
+  *     @arg I2C_INT_RX_UNDER: When the processor attempts to read the receive buffer
+  *                            when it is empty by reading from the REG_IC_DATA_CMD register.
+  * @retval None.
+  */
+void I2C_ClearINTPendingBit(I2C_TypeDef *I2Cx, uint16_t I2C_IT)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+    assert_param(I2C_GET_INT(I2C_IT));
+
+    switch (I2C_IT)
+    {
+    case I2C_INT_RX_UNDER:
+        {
+            (void)I2Cx->IC_CLR_RX_UNDER;
+            break;
+        }
+    case I2C_INT_RX_OVER:
+        {
+            (void)I2Cx->IC_CLR_RX_OVER;
+            break;
+        }
+    case I2C_INT_TX_OVER:
+        {
+            (void)I2Cx->IC_CLR_TX_OVER;
+            break;
+        }
+    case I2C_INT_RD_REQ:
+        {
+            (void)I2Cx->IC_CLR_RD_REQ;
+            break;
+        }
+    case I2C_INT_TX_ABRT:
+        {
+            (void)I2Cx->IC_CLR_TX_ABRT;
+            break;
+        }
+    case I2C_INT_RX_DONE:
+        {
+            (void)I2Cx->IC_CLR_RX_DONE;
+            break;
+        }
+    case I2C_INT_ACTIVITY:
+        {
+            (void)I2Cx->IC_CLR_ACTIVITY;
+            break;
+        }
+    case I2C_INT_STOP_DET:
+        {
+            (void)I2Cx->IC_CLR_STOP_DET;
+            break;
+        }
+    case I2C_INT_START_DET:
+        {
+            (void)I2Cx->IC_CLR_START_DET;
+            break;
+        }
+    case I2C_INT_GEN_CALL:
+        {
+            (void)I2Cx->IC_CLR_GEN_CALL;
+            break;
+        }
+    default:
+        {
+            break;
+        }
+    }
+}
+
+/**
+  * \brief  Set Clock Speed through the I2Cx peripheral.
+  * \param  I2Cx: Select the I2C peripheral. \ref I2C_Declaration
+  * \param  I2C_ClockSpeed: CLock speed.
+  * \return None
+  */
+void I2C_SetClockSpeed(I2C_TypeDef *I2Cx, uint32_t I2C_ClockSpeed)
+{
+    uint32_t tick_clksrc_ns = 0;
+    uint32_t allowedSpeed = 0;
+    uint32_t spklen = 0;
+    uint32_t scl_low_period_spec_min_ns = 0;
+    uint32_t scl_high_period_spec_min_ns = 0;
+    uint32_t scl_lcnt_min = 0;
+    uint32_t scl_hcnt_min = 0;
+    uint32_t scl_low_period_min_ns = 0;
+    uint32_t scl_high_period_min_ns = 0;
+    uint32_t tick_clkspeed_ns = 0;
+    uint32_t total_period_ns = 0;
+    uint32_t total_hcnt_lcnt = 0;
+    int32_t remaining = 0;
+    uint32_t scl_lcnt = 0;
+    uint32_t scl_hcnt = 0;
+
+    /* Tick of I2C clock source in ns. */
+    tick_clksrc_ns = NS_PER_SECOND / I2CSrcClk;
+
+    /* Limit the maximum I2C speed according to the I2C clock source. */
+    if (I2CSrcClk == 40000000)
+    {
+        allowedSpeed = 1000000;
+    }
+    else if (I2CSrcClk == 20000000)
+    {
+        allowedSpeed = 400000;
+    }
+    else
+    {
+        allowedSpeed = 100000;
+    }
+    /* Set Max I2C Clock speed. */
+    I2C_ClockSpeed = (I2C_ClockSpeed > allowedSpeed) ? allowedSpeed : I2C_ClockSpeed;
+
+    /* Set the spike time according to SPEC */
+    /* For Standard mode, there is no limit on spike suppression time, use default value. */
+    if (I2C_ClockSpeed <= 100000)
+    {
+        spklen = 0x05;
+    }
+    /* For Fast mode (plus), the max spike suppression time is 50ns. */
+    else
+    {
+        spklen = 0x01;
+    }
+
+    /* Set suppression limit */
+    I2Cx->IC_FS_SPKLEN = spklen & 0xFFFF;
+
+    /******************* Calulate the SCL low high count based on SPEC *******************/
+    /* Get the minimum of scl low high period specified in the spec */
+    if (I2C_ClockSpeed <= 100000)
+    {
+        scl_low_period_spec_min_ns = I2C_STANDARD_MODE_SCL_LOW_PERIOD_MIN_NS;
+        scl_high_period_spec_min_ns = I2C_STANDARD_MODE_SCL_HIGH_PERIOD_MIN_NS;
+    }
+    else if (I2C_ClockSpeed <= 400000)
+    {
+        scl_low_period_spec_min_ns = I2C_FAST_MODE_SCL_LOW_PERIOD_MIN_NS;
+        scl_high_period_spec_min_ns = I2C_FAST_MODE_SCL_HIGH_PERIOD_MIN_NS;
+    }
+    else
+    {
+        scl_low_period_spec_min_ns = I2C_FAST_MODE_PLUS_SCL_LOW_PERIOD_MIN_NS;
+        scl_high_period_spec_min_ns = I2C_FAST_MODE_PLUS_SCL_HIGH_PERIOD_MIN_NS;
+    }
+
+
+    /* Calulate the minimum of scl low high period based on LCNT/HCNT specified in hardware:
+     *
+     * Firstly, get the minimum LCNT HCNT specified in hardware.
+     * - LCNT: IC_SS_SCL_LCNT and IC_FS_SCL_LCNT register values must be larger than IC_FS_SPKLEN + 7.
+     * - HCNT: IC_SS_SCL_HCNT and IC_FS_SCL_HCNT register values must be larger than IC_FS_SPKLEN + 5.
+     * Use +1 to enforce strictly greater with integer registers.
+     *
+     * Secondly, calulate the minimum of scl high/low period based on the LCNT/HCNT.
+     */
+
+    scl_lcnt_min = spklen + 7 + 1;
+    scl_hcnt_min = spklen + 5 + 1;
+    scl_low_period_min_ns = (scl_lcnt_min + I2C_SCL_LOW_PERIOD_COMPENSATE) * tick_clksrc_ns;
+    scl_high_period_min_ns = (scl_hcnt_min + spklen + I2C_SCL_HIGH_PERIOD_COMPENSATE) *
+                             tick_clksrc_ns;
+
+    /* Final minimum: satisfy both spec and hardware. */
+    scl_low_period_min_ns = (scl_low_period_min_ns > scl_low_period_spec_min_ns) ?
+                            scl_low_period_min_ns : scl_low_period_spec_min_ns;
+    scl_high_period_min_ns = (scl_high_period_min_ns > scl_high_period_spec_min_ns) ?
+                             scl_high_period_min_ns : scl_high_period_spec_min_ns;
+
+    scl_lcnt_min = ROUNDUP(scl_low_period_min_ns, tick_clksrc_ns) - I2C_SCL_LOW_PERIOD_COMPENSATE;
+    scl_hcnt_min = ROUNDUP(scl_high_period_min_ns,
+                           tick_clksrc_ns) - spklen - I2C_SCL_HIGH_PERIOD_COMPENSATE;
+
+    /*************** Calulate the SCL low high count based on I2C_Clock_Speed ***************/
+
+    /* Calculate target total (high+low) counter based on the desired frequency of I2C SCL.
+     * Firstly, calulate the total period: tick_clkspeed_ns minus I2C_RisingTimeNs.
+     *   - Notes: I2C_RisingTimeNs should be below the range.
+     * Secondly, total_period_ns div tick_clksrc_ns, round up.
+     * Then subtract SPKLEN and path compensations to get pure HCNT+LCNT sum.
+     */
+
+    tick_clkspeed_ns = NS_PER_SECOND / I2C_ClockSpeed;
+    total_period_ns = tick_clkspeed_ns - I2C_RISING_TIME_NS;
+    total_hcnt_lcnt = (ROUNDUP(total_period_ns, tick_clksrc_ns)
+                       - spklen - I2C_SCL_HIGH_PERIOD_COMPENSATE - I2C_SCL_LOW_PERIOD_COMPENSATE);
+
+    /***************** Distibute the remaining count to the SCL low high *****************/
+
+    /* Calculate the remaining as total_hcnt_lcnt - (scl_lcnt_min + scl_hcnt_min),
+     * distribute the remaining counts between low and high count.
+     */
+
+    remaining = total_hcnt_lcnt - scl_lcnt_min - scl_hcnt_min;
+    scl_lcnt = scl_lcnt_min;
+    scl_hcnt = scl_hcnt_min;
+    if (remaining > 0)
+    {
+        scl_lcnt = scl_lcnt_min + (uint32_t)(remaining / 2);
+        scl_hcnt = total_hcnt_lcnt - scl_lcnt;
+    }
+
+    /* Set speed mode and write counters to responsing registers */
+    if (I2C_ClockSpeed <= 100000)
+    {
+        /*Configure I2C speed in standard mode*/
+        I2Cx->IC_CON |= (0x3 << 1);
+        I2Cx->IC_CON &= 0xfffb;
+        I2Cx->IC_SS_SCL_LCNT = scl_lcnt & 0xFFFF;
+        I2Cx->IC_SS_SCL_HCNT = scl_hcnt & 0xFFFF;
+    }
+    else
+    {
+        /* Configure I2C speed in fast mode or fast mode plus*/
+        I2Cx->IC_CON |= (0x3 << 1);
+        I2Cx->IC_CON &= 0xfffd;
+        I2Cx->IC_FS_SCL_LCNT = scl_lcnt & 0xFFFF;
+        I2Cx->IC_FS_SCL_HCNT = scl_hcnt & 0xFFFF;
+    }
+}
+
+/**
+  * \brief  Store I2C register values when system enter DLPS.
+  * \param  PeriReg: Specifies to select the I2C peripheral.
+  * \param  StoreBuf: Store buffer to store I2C register data.
+  * \return None.
+  */
+DATA_RAM_FUNCTION
+void I2C_DLPSEnter(void *PeriReg, void *StoreBuf)
+{
+    I2C_TypeDef *I2Cx = (I2C_TypeDef *)PeriReg;
+    I2CStoreReg_TypeDef *store_buf = (I2CStoreReg_TypeDef *)StoreBuf;
+
+    if (I2Cx == I2C0)
+    {
+        RCC_PeriphClockCmd(APBPeriph_I2C0, APBPeriph_I2C0_CLOCK, ENABLE);
+    }
+    else if (I2Cx == I2C1)
+    {
+        RCC_PeriphClockCmd(APBPeriph_I2C1, APBPeriph_I2C1_CLOCK, ENABLE);
+    }
+
+    store_buf->i2c_reg[0]  = I2Cx->IC_CON;
+    store_buf->i2c_reg[1]  = I2Cx->IC_TAR;
+    store_buf->i2c_reg[2]  = I2Cx->IC_SAR;
+    store_buf->i2c_reg[3]  = I2Cx->IC_SS_SCL_HCNT;
+    store_buf->i2c_reg[4]  = I2Cx->IC_SS_SCL_LCNT;
+    store_buf->i2c_reg[5]  = I2Cx->IC_FS_SCL_HCNT;
+    store_buf->i2c_reg[6]  = I2Cx->IC_FS_SCL_LCNT;
+    store_buf->i2c_reg[7] = I2Cx->IC_INTR_MASK;
+    store_buf->i2c_reg[8] = I2Cx->IC_RX_TL;
+    store_buf->i2c_reg[9] = I2Cx->IC_TX_TL;
+    store_buf->i2c_reg[10] = I2Cx->IC_ENABLE;
+    store_buf->i2c_reg[11] = I2Cx->IC_SDA_HOLD;
+    store_buf->i2c_reg[12] = I2Cx->IC_SLV_DATA_NACK_ONLY;
+    store_buf->i2c_reg[13] = I2Cx->IC_DMA_CR;
+    store_buf->i2c_reg[14] = I2Cx->IC_DMA_TDLR;
+    store_buf->i2c_reg[15] = I2Cx->IC_DMA_RDLR;
+    store_buf->i2c_reg[16] = I2Cx->IC_SDA_SETUP;
+    store_buf->i2c_reg[17] = I2Cx->IC_FS_SPKLEN;
+}
+
+/**
+  * \brief  Restore I2C register values when system enter DLPS.
+  * \param  PeriReg: Specifies to select the I2C peripheral.
+  * \param  StoreBuf: Restore buffer to restore I2C register data.
+  * \return None
+  */
+DATA_RAM_FUNCTION
+void I2C_DLPSExit(void *PeriReg, void *StoreBuf)
+{
+    I2C_TypeDef *I2Cx = (I2C_TypeDef *)PeriReg;
+    I2CStoreReg_TypeDef *store_buf = (I2CStoreReg_TypeDef *)StoreBuf;
+
+    if (I2Cx == I2C0)
+    {
+        RCC_PeriphClockCmd(APBPeriph_I2C0, APBPeriph_I2C0_CLOCK, ENABLE);
+    }
+    else if (I2Cx == I2C1)
+    {
+        RCC_PeriphClockCmd(APBPeriph_I2C1, APBPeriph_I2C1_CLOCK, ENABLE);
+    }
+
+    I2Cx->IC_CON         = store_buf->i2c_reg[0];
+    I2Cx->IC_TAR         = store_buf->i2c_reg[1];
+    I2Cx->IC_SAR         = store_buf->i2c_reg[2];
+    I2Cx->IC_SS_SCL_HCNT = store_buf->i2c_reg[3];
+    I2Cx->IC_SS_SCL_LCNT = store_buf->i2c_reg[4];
+    I2Cx->IC_FS_SCL_HCNT = store_buf->i2c_reg[5];
+    I2Cx->IC_FS_SCL_LCNT = store_buf->i2c_reg[6];
+    I2Cx->IC_INTR_MASK   = store_buf->i2c_reg[7];
+    I2Cx->IC_RX_TL       = store_buf->i2c_reg[8];
+    I2Cx->IC_TX_TL       = store_buf->i2c_reg[9];
+    I2Cx->IC_SDA_HOLD    = store_buf->i2c_reg[11];
+    I2Cx->IC_SLV_DATA_NACK_ONLY = store_buf->i2c_reg[12];
+    I2Cx->IC_DMA_CR      = store_buf->i2c_reg[13];
+    I2Cx->IC_DMA_TDLR    = store_buf->i2c_reg[14];
+    I2Cx->IC_DMA_RDLR    = store_buf->i2c_reg[15];
+    I2Cx->IC_SDA_SETUP   = store_buf->i2c_reg[16];
+    I2Cx->IC_FS_SPKLEN   = store_buf->i2c_reg[17];
+    I2Cx->IC_ENABLE      = store_buf->i2c_reg[10];
+
+}
+
+
diff --git a/bee/drivers/i2c/src/device/rtl8752h/rtl876x_i2c.h b/bee/drivers/i2c/src/device/rtl8752h/rtl876x_i2c.h
new file mode 100644
index 00000000..14343a3c
--- /dev/null
+++ b/bee/drivers/i2c/src/device/rtl8752h/rtl876x_i2c.h
@@ -0,0 +1,884 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _RTL876X_I2C_H_
+#define _RTL876X_I2C_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup  IO          Peripheral Drivers
+ * \defgroup    I2C         I2C
+ *
+ * \brief       Manage the I2C peripheral functions.
+ *
+ * \ingroup     IO
+ */
+
+
+/*============================================================================*
+ *                         Includes
+ *============================================================================*/
+#include "rtl876x.h"
+
+/*============================================================================*
+ *                         Types
+ *============================================================================*/
+/**
+ * \defgroup    I2C_Exported_Types I2C Exported Types
+ * \{
+ * \ingroup     I2C
+ */
+
+/**
+ * \brief       I2C Init structure definition.
+ *
+ * \ingroup     I2C_Exported_Types
+ */
+
+typedef struct
+{
+    uint32_t I2C_Clock;             /*!< Specify the clock frequency, default 40000000.
+                                            This parameter must be set with I2C clock div. */
+    uint32_t I2C_ClockSpeed;        /*!< Specify the clock frequency.
+                                            This parameter must be set to a value lower than 1000000Hz. */
+    uint16_t I2C_DeviveMode;        /*!< Specify the I2C device mode.
+                                            This parameter can be a value of \ref I2C_Device_Mode. */
+    uint16_t I2C_AddressMode;       /*!< Specify the I2C address mode.
+                                            This parameter can be a value of \ref I2C_Address_Mode. */
+    uint16_t I2C_SlaveAddress;      /*!< Specify the slave device address.
+                                            This parameter can be a 7-bit or 10-bit address. */
+    uint16_t I2C_Ack;               /*!< Enable or disable the acknowledgement only in slave mode.
+                                            This parameter can be a value of \ref I2C_Acknowledgement. */
+    uint32_t I2C_TxThresholdLevel;  /* !< Specify the transmit FIFO Threshold to trigger interrupt I2C_INT_TX_EMPTY.
+                                            This parameter can be a value less than 24 */
+    uint32_t I2C_RxThresholdLevel;  /* !< Specify the receive FIFO Threshold to trigger interrupt I2C_INT_RX_FULL.
+                                            This parameter can be a value less than 40 */
+    uint16_t I2C_TxDmaEn;           /*!< Specify the Tx DMA mode.
+                                            This parameter can be a value of ENABLE or DISABLE. */
+    uint16_t I2C_RxDmaEn;           /*!< Specify the Rx DMA mode.
+                                            This parameter can be a value of ENABLE or DISABLE. */
+    uint8_t  I2C_TxWaterlevel;      /*!< Specify the DMA Tx water level.
+                                            Best to equal Tx FIFO minus GDMA Dest MSize. */
+    uint8_t  I2C_RxWaterlevel;      /*!< Specify the DMA Rx water level.
+                                            Best to equal GDMA Source MSize. */
+} I2C_InitTypeDef;
+
+/** End of I2C_Exported_Types
+  * \}
+  */
+
+/*============================================================================*
+ *                         Constants
+ *============================================================================*/
+/**
+ * \defgroup    I2C_Exported_Constants I2C Exported Constants
+ *
+ * \ingroup     I2C
+ */
+
+#define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C0) || \
+                                   ((PERIPH) == I2C1))
+
+/**
+ * \def         I2C_clock_speed I2C Clock Speed
+ */
+#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) >= 0x01) && ((SPEED) <= 1000000))
+
+/**
+ * \defgroup    I2C_Device_Mode I2C Device Mode
+ * \{
+ * \ingroup     I2C_Exported_Constants
+ */
+#define I2C_DeviveMode_Master                   ((uint16_t)0x0041)
+#define I2C_DeviveMode_Slave                    ((uint16_t)0x0000)
+/** \} */
+
+/**
+ * \defgroup    I2C_Address_Mode I2C Address Mode
+ * \{
+ * \ingroup     I2C_Exported_Constants
+ */
+#define I2C_AddressMode_7BIT                    ((uint16_t)0x0000)
+#define I2C_AddressMode_10BIT                   ((uint16_t)0x0001)
+/** \} */
+
+/**
+ * \defgroup    I2C_Acknowledgement I2C Acknowledgement
+ * \{
+ * \ingroup     I2C_Exported_Constants
+ */
+#define I2C_Ack_Enable                          ((uint16_t)0x0001)
+#define I2C_Ack_Disable                         ((uint16_t)0x0000)
+/** \} */
+
+/**
+ * \defgroup    I2C_Flags_Definition I2C Flags Definition
+ * \{
+ * \ingroup     I2C_Exported_Constants
+ */
+#define I2C_FLAG_SLV_ACTIVITY                   ((uint32_t)0x00000040)
+#define I2C_FLAG_MST_ACTIVITY                   ((uint32_t)0x00000020)
+#define I2C_FLAG_RFF                            ((uint32_t)0x00000010)
+#define I2C_FLAG_RFNE                           ((uint32_t)0x00000008)
+#define I2C_FLAG_TFE                            ((uint32_t)0x00000004)
+#define I2C_FLAG_TFNF                           ((uint32_t)0x00000002)
+#define I2C_FLAG_ACTIVITY                       ((uint32_t)0x00000001)
+
+#define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_SLV_ACTIVITY) || ((FLAG) == I2C_FLAG_MST_ACTIVITY) || \
+                               ((FLAG) == I2C_FLAG_RFF) || ((FLAG) == I2C_FLAG_RFNE) || \
+                               ((FLAG) == I2C_FLAG_TFE) || ((FLAG) == I2C_FLAG_TFNF) || \
+                               ((FLAG) == I2C_FLAG_ACTIVITY))
+/** \} */
+
+/**
+ * \defgroup    I2C_Transmit_Abort_Source I2C Transmit Abort Source
+ * \{
+ * \ingroup     I2C_Exported_Constants
+ */
+#define ABRT_SLVRD_INTX                         ((uint32_t)BIT(15))
+#define ABRT_SLV_ARBLOST                        ((uint32_t)BIT(14))
+#define ABRT_SLVFLUSH_TXFIFO                    ((uint32_t)BIT(13))
+#define ARB_LOST                                ((uint32_t)BIT(12))
+#define ABRT_MASTER_DIS                         ((uint32_t)BIT(11))
+#define ABRT_10B_RD_NORSTRT                     ((uint32_t)BIT(10))
+#define ABRT_SBYTE_NORSTRT                      ((uint32_t)BIT(9))
+#define ABRT_HS_NORSTRT                         ((uint32_t)BIT(8))
+#define ABRT_SBYTE_ACKDET                       ((uint32_t)BIT(7))
+#define ABRT_HS_ACKDET                          ((uint32_t)BIT(6))
+#define ABRT_GCALL_READ                         ((uint32_t)BIT(5))
+#define ABRT_GCALL_NOACK                        ((uint32_t)BIT(4))
+#define ABRT_TXDATA_NOACK                       ((uint32_t)BIT(3))
+#define ABRT_10ADDR2_NOACK                      ((uint32_t)BIT(2))
+#define ABRT_10ADDR1_NOACK                      ((uint32_t)BIT(1))
+#define ABRT_7B_ADDR_NOACK                      ((uint32_t)BIT(0))
+
+#define MS_ALL_ABORT                            (ARB_LOST | ABRT_MASTER_DIS | ABRT_TXDATA_NOACK |\
+                                                 ABRT_10ADDR2_NOACK | ABRT_10ADDR1_NOACK | ABRT_7B_ADDR_NOACK)
+
+#define IS_I2C_EVENT(EVENT) (((EVENT) == ABRT_SLVRD_INTX) || \
+                             ((EVENT) == ABRT_SLV_ARBLOST) || \
+                             ((EVENT) == ABRT_SLVFLUSH_TXFIFO) || \
+                             ((EVENT) == ARB_LOST) || \
+                             ((EVENT) == ABRT_MASTER_DIS) || \
+                             ((EVENT) == ABRT_10B_RD_NORSTRT) || \
+                             ((EVENT) == ABRT_SBYTE_NORSTRT) || \
+                             ((EVENT) == ABRT_HS_NORSTRT) || \
+                             ((EVENT) == ABRT_SBYTE_ACKDET) || \
+                             ((EVENT) == ABRT_HS_ACKDET) || \
+                             ((EVENT) == ABRT_GCALL_READ) || \
+                             ((EVENT) == ABRT_GCALL_NOACK) || \
+                             ((EVENT) == ABRT_TXDATA_NOACK) || \
+                             ((EVENT) == ABRT_10ADDR2_NOACK) || \
+                             ((EVENT) == ABRT_10ADDR1_NOACK) || \
+                             ((EVENT) == ABRT_7B_ADDR_NOACK))
+/** \} */
+
+/**
+ * \defgroup    I2C_Interrupts_Definition I2C Interrupts Definition
+ * \{
+ * \ingroup     I2C_Exported_Constants
+ */
+#define I2C_INT_GEN_CALL                        ((uint32_t)BIT(11))
+#define I2C_INT_START_DET                       ((uint32_t)BIT(10))
+#define I2C_INT_STOP_DET                        ((uint32_t)BIT(9))
+#define I2C_INT_ACTIVITY                        ((uint32_t)BIT(8))
+#define I2C_INT_RX_DONE                         ((uint32_t)BIT(7))
+#define I2C_INT_TX_ABRT                         ((uint32_t)BIT(6))
+#define I2C_INT_RD_REQ                          ((uint32_t)BIT(5))
+#define I2C_INT_TX_EMPTY                        ((uint32_t)BIT(4))
+#define I2C_INT_TX_OVER                         ((uint32_t)BIT(3))
+#define I2C_INT_RX_FULL                         ((uint32_t)BIT(2))
+#define I2C_INT_RX_OVER                         ((uint32_t)BIT(1))
+#define I2C_INT_RX_UNDER                        ((uint32_t)BIT(0))
+
+#define I2C_GET_INT(INT)    (((INT) == I2C_INT_GEN_CALL) || ((INT) == I2C_INT_START_DET) || \
+                             ((INT) == I2C_INT_STOP_DET) || ((INT) == I2C_INT_ACTIVITY) || \
+                             ((INT) == I2C_INT_RX_DONE)  || ((INT) == I2C_INT_TX_ABRT) || \
+                             ((INT) == I2C_INT_RD_REQ)   || ((INT) == I2C_INT_TX_EMPTY) || \
+                             ((INT) == I2C_INT_TX_OVER)  || ((INT) == I2C_INT_RX_FULL) || \
+                             ((INT) == I2C_INT_RX_OVER)  || ((INT) == I2C_INT_RX_UNDER))
+/** \} */
+
+/**
+ * \defgroup    I2C_GDMA_Transfer_Requests I2C GDMA transfer requests
+ * \{
+ * \ingroup     I2C_Exported_Constants
+ */
+#define I2C_GDMAReq_Tx                          ((uint16_t)0x0002)
+#define I2C_GDMAReq_Rx                          ((uint16_t)0x0001)
+
+#define IS_I2C_GDMAREQ(GDMAREQ) ((((GDMAREQ) & (uint16_t)0xFFFC) == 0x00) && ((GDMAREQ) != 0x00))
+/** \} */
+
+/**
+ * \defgroup    I2C_Send_Command I2C Send Command
+ * \{
+ * \ingroup     I2C_Exported_Constants
+ */
+#define I2C_WRITE_CMD                           0
+#define I2C_READ_CMD                            BIT(8)
+
+#define IS_I2C_CMD(CMD) (((CMD) == I2C_WRITE_CMD) || ((CMD) == I2C_READ_CMD))
+/** \} */
+
+/**
+ * \defgroup    I2C_Send_Stop   I2C Send Stop
+ * \{
+ * \ingroup     I2C_Exported_Constants
+ */
+
+#define I2C_STOP_ENABLE                         BIT(9)
+#define I2C_STOP_DISABLE                        0
+
+#define IS_I2C_STOP(CMD) (((CMD) == I2C_STOP_ENABLE) || ((CMD) == I2C_STOP_DISABLE))
+/** \} */
+
+/**
+ * \defgroup    I2C_Status I2C Status
+ * \{
+ * \ingroup     I2C_Exported_Constants
+ */
+typedef enum
+{
+    I2C_Success,
+    I2C_ARB_LOST,
+    I2C_ABRT_MASTER_DIS,
+    I2C_ABRT_TXDATA_NOACK,
+    I2C_ABRT_10ADDR2_NOACK,
+    I2C_ABRT_10ADDR1_NOACK,
+    I2C_ABRT_7B_ADDR_NOACK,
+    I2C_ERR_TIMEOUT
+} I2C_Status;
+/** \} */
+
+/** End of I2C_Exported_Constants
+  * \}
+  */
+
+/*============================================================================*
+ *                         Functions
+ *============================================================================*/
+
+/**
+ * \defgroup    I2C_Exported_Functions I2C Exported Functions
+ * \{
+ * \ingroup     I2C
+ */
+
+/**
+ * \brief   Deinitialize the I2Cx peripheral registers to their default reset values.
+ * \param[in]  I2Cx: Where x can be 0 or 1 to select the I2C peripheral.
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_i2c0_init(void)
+ * {
+ *     I2C_DeInit(I2C0);
+ * }
+ * \endcode
+ */
+void I2C_DeInit(I2C_TypeDef *I2Cx);
+
+/**
+ * \brief   Initialize the I2Cx peripheral according to the specified
+ *          parameters in the I2C_InitStruct.
+ * \param[in] I2Cx: Where x can be 0 or 1 to select the I2C peripheral.
+ * \param[in] I2C_InitStruct: Pointer to an I2C_InitTypeDef structure that
+ *            contains the configuration information for the specified I2C peripheral.
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_i2c0_init(void)
+ * {
+ *     RCC_PeriphClockCmd(APBPeriph_I2C0, APBPeriph_I2C0_CLOCK, ENABLE);
+ *
+ *     I2C_InitTypeDef  I2C_InitStruct;
+ *     I2C_StructInit(&I2C_InitStruct);
+ *
+ *     I2C_InitStruct.I2C_ClockSpeed    = 100000;
+ *     I2C_InitStruct.I2C_DeviveMode    = I2C_DeviveMode_Master;
+ *     I2C_InitStruct.I2C_AddressMode   = I2C_AddressMode_7BIT;
+ *     I2C_InitStruct.I2C_SlaveAddress  = STK8321_ADDRESS;
+ *     I2C_InitStruct.I2C_Ack           = I2C_Ack_Enable;
+ *
+ *     I2C_Init(I2C0, &I2C_InitStruct);
+ *     I2C_Cmd(I2C0, ENABLE);
+ * }
+ * \endcode
+ */
+void I2C_Init(I2C_TypeDef *I2Cx, I2C_InitTypeDef *I2C_InitStruct);
+
+/**
+ * \brief  Enable or disable the specified I2C peripheral.
+ * \param[in] I2Cx: Where x can be 0 or 1 to select the I2C peripheral.
+ * \param[in] NewState: New state of the I2Cx peripheral.
+ *      This parameter can be: ENABLE or DISABLE.
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_i2c0_init(void)
+ * {
+ *     RCC_PeriphClockCmd(APBPeriph_I2C0, APBPeriph_I2C0_CLOCK, ENABLE);
+ *
+ *     I2C_InitTypeDef  I2C_InitStruct;
+ *     I2C_StructInit(&I2C_InitStruct);
+ *
+ *     I2C_InitStruct.I2C_ClockSpeed    = 100000;
+ *     I2C_InitStruct.I2C_DeviveMode    = I2C_DeviveMode_Master;
+ *     I2C_InitStruct.I2C_AddressMode   = I2C_AddressMode_7BIT;
+ *     I2C_InitStruct.I2C_SlaveAddress  = STK8321_ADDRESS;
+ *     I2C_InitStruct.I2C_Ack           = I2C_Ack_Enable;
+ *
+ *     I2C_Init(I2C0, &I2C_InitStruct);
+ *     I2C_Cmd(I2C0, ENABLE);
+ * }
+ * \endcode
+ */
+void I2C_Cmd(I2C_TypeDef *I2Cx, FunctionalState NewState);
+
+/**
+ * \brief   Fill each I2C_InitStruct member with its default value.
+ * \param[in] I2C_InitStruct: Pointer to an I2C_InitTypeDef structure which will be initialized.
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_i2c0_init(void)
+ * {
+ *     RCC_PeriphClockCmd(APBPeriph_I2C0, APBPeriph_I2C0_CLOCK, ENABLE);
+ *
+ *     I2C_InitTypeDef  I2C_InitStruct;
+ *     I2C_StructInit(&I2C_InitStruct);
+ *
+ *     I2C_InitStruct.I2C_ClockSpeed    = 100000;
+ *     I2C_InitStruct.I2C_DeviveMode    = I2C_DeviveMode_Master;
+ *     I2C_InitStruct.I2C_AddressMode   = I2C_AddressMode_7BIT;
+ *     I2C_InitStruct.I2C_SlaveAddress  = STK8321_ADDRESS;
+ *     I2C_InitStruct.I2C_Ack           = I2C_Ack_Enable;
+ *
+ *     I2C_Init(I2C0, &I2C_InitStruct);
+ *     I2C_Cmd(I2C0, ENABLE);
+ * }
+ * \endcode
+ */
+void I2C_StructInit(I2C_InitTypeDef *I2C_InitStruct);
+
+/**
+ * \brief   Send data in master mode through the I2Cx peripheral.
+ * \param[in] I2Cx: Where x can be 0 or 1 to select the I2C peripheral.
+ * \param[in] pBuf: Bytes to be transmitted.
+ * \param[in] len: Data length to send.
+ * \return The status of I2Cx, which refers to \ref I2C_Status.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void i2c0_demo(void)
+ * {
+ *     uint8_t data[10] = {0x01,0x02,0x03,0x04};
+ *     I2C_MasterWrite(I2C0, data, 4);
+ * }
+ * \endcode
+ */
+I2C_Status I2C_MasterWrite(I2C_TypeDef *I2Cx, uint8_t *pBuf, uint16_t len);
+
+/**
+ * \brief   Read data in master mode through the I2Cx peripheral.
+ * \param[in] I2Cx: Where x can be 0 or 1 to select the I2C peripheral.
+ * \param[in] pBuf: Data buffer to receive data.
+ * \param[in] len: Read data length.
+ * \return The status of I2Cx, which refers to \ref I2C_Status.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void i2c0_demo(void)
+ * {
+ *     uint8_t data[10] = {0};
+ *     I2C_MasterRead(I2C0, data, 10);
+ * }
+ * \endcode
+ */
+I2C_Status I2C_MasterRead(I2C_TypeDef *I2Cx, uint8_t *pBuf, uint16_t len);
+
+/**
+ * \brief   Send data and read data in master mode through the I2Cx peripheral.
+ * \param[in] I2Cx: Where x can be 0 or 1 to select the I2C peripheral.
+ * \param[in] pWriteBuf: Data buffer to send before read.
+ * \param[in] Writelen: Send data length.
+ * \param[out] pReadBuf: Data buffer to receive.
+ * \param[in] Readlen: Receive data length.
+ * \return  The status of I2Cx, which refers to \ref I2C_Status.
+ * \note Attention: Read data with time-out mechanism.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void i2c0_demo(void)
+ * {
+ *     uint8_t tx_data[10] = {0x01,0x02,0x03,0x04};
+ *     uint8_t rx_data[10] = {0};
+ *     I2C_RepeatRead(I2C0, tx_data, 4, rx_data, 10);
+ * }
+ * \endcode
+ */
+I2C_Status I2C_RepeatRead(I2C_TypeDef *I2Cx, uint8_t *pWriteBuf, uint16_t Writelen,
+                          uint8_t *pReadBuf, uint16_t Readlen);
+
+/**
+ * \brief Enable or disable the specified I2C interrupt.
+ * \param[in] I2Cx: Where x can be 0 or 1.
+ * \param[in] I2C_IT: This parameter can be one of the following values, which refer to \ref I2C_Interrupts_Definition.
+ *      \arg I2C_INT_GEN_CALL: When a General Call address is received and it is acknowledged.
+ *      \arg I2C_INT_START_DET: When a START or RESTART condition has occurred on the I2C interface
+ *                            regardless of whether I2C is operating in slave or master mode.
+ *      \arg I2C_INT_STOP_DET: When a STOP condition has occurred on the I2C interface
+ *                            regardless of whether I2C is operating in slave or master mode.
+ *      \arg I2C_INT_ACTIVITY: When I2C is active on the bus. Stays set until it is cleared.
+ *      \arg I2C_INT_RX_DONE: When the I2C is acting as a slave-transmitter and the master does
+ *                            not acknowledge a transmitted byte.
+ *                            This occurs on the last byte of the transmission,
+ *                            indicating that the transmission is done.
+ *      \arg I2C_INT_TX_ABRT: When an I2C transmitter is unable to complete the intended actions
+ *                           on the contents of the transmit FIFO.
+ *      \arg I2C_INT_RD_REQ: When I2C is acting as a slave and another I2C master is attempting to read data from I2C.
+ *      \arg I2C_INT_TX_EMPTY: When the transmit buffer is at or below the threshold value set in the REG_IC_TXFLR register.
+ *      \arg I2C_INT_TX_OVER: When transmit buffer is filled to IC_TX_BUFFER_DEPTH and
+ *                           the processor attempts to issue another I2C command by writing to the REG_IC_DATA_CMD register.
+ *      \arg I2C_INT_RX_FULL: When the receive buffer reaches or goes above the RX_TL threshold in the REG_IC_RX_TL register.
+ *                           A value of 0 sets the threshold for 1 entry, and a value of 255 sets the threshold for 256 entries.
+ *      \arg I2C_INT_RX_OVER: When the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and
+ *                           an additional byte is received from an external I2C device.
+ *      \arg I2C_INT_RX_UNDER: When the processor attempts to read the receive buffer
+ *                            when it is empty by reading from the REG_IC_DATA_CMD register.
+ * \param[in]  NewState: New state of the I2C interrupt. This parameter can be: ENABLE or DISABLE.
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void i2c0_demo(void)
+ * {
+ *     I2C_ClearINTPendingBit(I2C0, I2C_INT_STOP_DET);
+ *     I2C_INTConfig(I2C0, I2C_INT_STOP_DET, ENABLE);
+ *
+ *     NVIC_InitTypeDef NVIC_InitStruct;
+ *     NVIC_InitStruct.NVIC_IRQChannel = I2C0_IRQn;
+ *     NVIC_InitStruct.NVIC_IRQChannelPriority = 3;
+ *     NVIC_InitStruct.NVIC_IRQChannelCmd = ENABLE;
+ *     NVIC_Init(&NVIC_InitStruct);
+ * }
+ * \endcode
+ */
+void I2C_INTConfig(I2C_TypeDef *I2Cx, uint16_t I2C_IT, FunctionalState NewState);
+
+/**
+ * \brief   Clear the specified I2C interrupt pending bit.
+ * \param[in] I2Cx: Where x can be 0 or 1.
+ * \param[in] I2C_IT
+ *      This parameter can be one of the following values, which refer to \ref I2C_Interrupts_Definition.
+ *      \arg I2C_INT_GEN_CALL: When a General Call address is received and it is acknowledged.
+ *      \arg I2C_INT_START_DET: When a START or RESTART condition has occurred on the I2C interface
+  *                            regardless of whether I2C is operating in slave or master mode.
+ *      \arg I2C_INT_STOP_DET: When a STOP condition has occurred on the I2C interface
+  *                            regardless of whether I2C is operating in slave or master mode.
+ *      \arg I2C_INT_ACTIVITY: When I2C is active on the bus. Stays set until it is cleared.
+ *      \arg I2C_INT_RX_DONE: When the I2C is acting as a slave-transmitter and the master does
+  *                           not acknowledge a transmitted byte.
+  *                           This occurs on the last byte of the transmission,
+  *                           indicating that the transmission is done.
+ *      \arg I2C_INT_TX_ABRT: When an I2C transmitter is unable to complete the intended actions
+  *                           on the contents of the transmit FIFO.
+ *      \arg I2C_INT_RD_REQ: When I2C is acting as a slave and another I2C master is attempting to read data from I2C.
+ *      \arg I2C_INT_TX_EMPTY: When the transmit buffer is at or below the threshold value set in the REG_IC_TXFLR register.
+ *      \arg I2C_INT_TX_OVER: When transmit buffer is filled to IC_TX_BUFFER_DEPTH and
+  *                           the processor attempts to issue another I2C command by writing to the REG_IC_DATA_CMD register.
+ *      \arg I2C_INT_RX_FULL: When the receive buffer reaches or goes above the RX_TL threshold in the REG_IC_RX_TL register.
+  *                           A value of 0 sets the threshold for 1 entry, and a value of 255 sets the threshold for 256 entries.
+ *      \arg I2C_INT_RX_OVER: When the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and
+  *                           an additional byte is received from an external I2C device.
+ *      \arg I2C_INT_RX_UNDER: When the processor attempts to read the receive buffer
+  *                            when it is empty by reading from the REG_IC_DATA_CMD register.
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void I2C0_Handler(void)
+ * {
+ *     if (I2C_GetINTStatus(I2C0, I2C_INT_STOP_DET) == SET)
+ *     {
+ *         //Add user code here.
+ *         I2C_ClearINTPendingBit(I2C0, I2C_INT_STOP_DET);
+ *     }
+ * }
+ * \endcode
+ */
+void I2C_ClearINTPendingBit(I2C_TypeDef *I2Cx, uint16_t I2C_IT);
+
+/**
+ * \brief   Set slave device address.
+ * \param[in] I2Cx: Where x can be 0 or 1 to select the I2C peripheral.
+ * \param[in] Address: Specify the slave address which will be transmitted.
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void i2c0_demo(void)
+ * {
+ *     I2C_SetSlaveAddress(I2C0, 0x55);
+ * }
+ * \endcode
+ */
+__STATIC_INLINE void I2C_SetSlaveAddress(I2C_TypeDef *I2Cx, uint16_t Address)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+    /* Mask target address */
+    I2Cx->IC_TAR &= ~((uint16_t)0x3ff);
+    /* Configure new target address */
+    I2Cx->IC_TAR |= Address & 0x3ff;
+}
+
+/**
+ * \brief   Write command through the I2Cx peripheral.
+ * \param[in] I2Cx: where x can be 0 or 1 to select the I2C peripheral.
+ * \param[in] command: command of write or read.
+ *      \arg I2C_READ_CMD: means this is a read command.
+ *      \arg I2C_WRITE_CMD: means this is a write command.
+ * \param[in] data: Data which is to be transmitted.
+ * \param[in] StopState: send stop signal or not.
+ *      \arg I2C_STOP_ENABLE: Send stop signal.
+ *      \arg I2C_STOP_DISABLE: Do not send stop signal.
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void i2c0_demo(void)
+ * {
+ *     I2C_SendCmd(I2C0, I2C_READ_CMD, 0xAA, I2C_STOP_ENABLE);
+ * }
+ * \endcode
+ */
+__STATIC_INLINE void I2C_SendCmd(I2C_TypeDef *I2Cx, uint16_t command, uint8_t data,
+                                 uint16_t StopState)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+    assert_param(IS_I2C_CMD(command));
+    assert_param(IS_I2C_STOP(StopState));
+
+    I2Cx->IC_DATA_CMD = data | command | StopState;
+}
+
+/**
+ * \brief  Received data by the I2Cx peripheral.
+ * \param[in] I2Cx: where x can be 0 or 1 to select the I2C peripheral.
+ * \return The most recent received data.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void i2c0_demo(void)
+ * {
+ *     uint8_t data = I2C_ReceiveData(I2C0);
+ * }
+ * \endcode
+ */
+__STATIC_INLINE uint8_t I2C_ReceiveData(I2C_TypeDef *I2Cx)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+    /* Return the data in the DR register */
+    return (uint8_t)I2Cx->IC_DATA_CMD;
+}
+
+/**
+ * \brief   Get data length in Rx FIFO of the I2Cx peripheral.
+ * \param[in] I2Cx: where x can be 0 or 1 to select the I2C peripheral.
+ * \return  The data length in Rx FIFO.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void i2c0_demo(void)
+ * {
+ *     uint8_t data_len = I2C_GetRxFIFOLen(I2C0);
+ * }
+ * \endcode
+ */
+__STATIC_INLINE uint8_t I2C_GetRxFIFOLen(I2C_TypeDef *I2Cx)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+    return (uint8_t)I2Cx->IC_RXFLR;
+}
+
+/**
+ * \brief   Get data length in Tx FIFO of the I2Cx peripheral.
+ * \param[in] I2Cx: where x can be 0 or 1 to select the I2C peripheral.
+ * \return  The data length in Tx FIFO.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void i2c0_demo(void)
+ * {
+ *     uint8_t data_len = I2C_GetTxFIFOLen(I2C0);
+ * }
+ * \endcode
+ */
+__STATIC_INLINE uint8_t I2C_GetTxFIFOLen(I2C_TypeDef *I2Cx)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+    return (uint8_t)I2Cx->IC_TXFLR;
+}
+
+/**
+ * \brief   Clear all I2C interrupts.
+ * \param[in] I2Cx: where x can be 0 or 1 to select the I2C peripheral.
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void i2c0_demo(void)
+ * {
+ *     I2C_ClearAllINT(I2C0);
+ * }
+ * \endcode
+ */
+__STATIC_INLINE void I2C_ClearAllINT(I2C_TypeDef *I2Cx)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+    I2Cx->IC_CLR_INTR;
+}
+
+/**
+ * \brief  Check whether the specified I2C flag is set.
+ * \param[in] I2Cx: Where x can be 0 or 1 to select the I2C peripheral.
+ * \param[in] I2C_FLAG: Specify the flag to check.
+ *      This parameter can be one of the following values, which refer to \ref I2C_Flags_Definition.
+ *      \arg I2C_FLAG_SLV_ACTIVITY: Slave FSM activity status.
+ *      \arg I2C_FLAG_MST_ACTIVITY: Master FSM activity status.
+ *      \arg I2C_FLAG_RFF: Receive FIFO completely full.
+ *      \arg I2C_FLAG_RFNE: Receive FIFO not empty.
+ *      \arg I2C_FLAG_TFE: Transmit FIFO completely empty.
+ *      \arg I2C_FLAG_TFNF: Transmit FIFO not full.
+ *      \arg I2C_FLAG_ACTIVITY: I2C activity status.
+ * \return  The new state of I2C_FLAG (SET or RESET).
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void i2c0_demo(void)
+ * {
+ *     FlagStatus flag_status = I2C_GetFlagState(I2C0, I2C_FLAG_RFF);
+ * }
+ * \endcode
+ */
+__STATIC_INLINE FlagStatus I2C_GetFlagState(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG)
+{
+    FlagStatus bit_status = RESET;
+
+    /* Check the parameters */
+    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+    assert_param(IS_I2C_GET_FLAG(I2C_FLAG));
+
+    if ((I2Cx->IC_STATUS & I2C_FLAG) != (uint32_t)RESET)
+    {
+        /* I2C_FLAG is set */
+        bit_status = SET;
+    }
+
+    /* Return the I2C_FLAG status */
+    return  bit_status;
+}
+
+/**
+ * \brief  Check whether the last I2Cx event is equal to the passed parameter.
+ * \param[in] I2Cx: Where x can be 0 or 1 to select the I2C peripheral.
+ * \param[in] I2C_EVENT: Specify the event to be checked about I2C Transmit Abort Status Register.
+ *      This parameter can be one of the following values, which refer to \ref I2C_Transmit_Abort_Source.
+ *      \arg ABRT_SLVRD_INTX: When the processor side responds to a slave mode request for data to be transmitted to a remote master and user send read command.
+ *      \arg ABRT_SLV_ARBLOST: Slave lost the bus while transmitting data to a remote master.
+ *      \arg ABRT_SLVFLUSH_TXFIFO: Slave has received a read command and some data exists in the TX FIFO so the slave issues a TX_ABRT interrupt to flush old data in TX FIFO.
+ *      \arg ARB_LOST: Master has lost arbitration or the slave transmitter has lost arbitration.
+ *      \arg ABRT_MASTER_DIS: User tries to initiate a Master operation with the Master mode disabled
+ *      \arg ABRT_10B_RD_NORSTRT: The restart is disabled and the master sends a read command in 10-bit addressing mode.
+ *      \arg ABRT_SBYTE_NORSTRT: The restart is disabled and the user is trying to send a START Byte.
+ *      \arg ABRT_HS_NORSTRT: The restart is disabled and the user is trying to use the master to transfer data in High Speed mode.
+ *      \arg ABRT_SBYTE_ACKDET: Master has sent a START Byte and the START Byte was acknowledged (wrong behavior).
+ *      \arg ABRT_HS_ACKDET: Master is in High Speed mode and the High Speed Master code was acknowledged (wrong behavior).
+ *      \arg ABRT_GCALL_READ: Sent a General Call but the user programmed the byte following the General Call to be a read from the bus.
+ *      \arg ABRT_GCALL_NOACK: Sent a General Call and no slave on the bus acknowledged the General Call.
+ *      \arg ABRT_TXDATA_NOACK: Master sent data byte(s) following the address, it did not receive an acknowledge from the remote slave.
+ *      \arg ABRT_10ADDR2_NOACK: Master is in 10-bit address mode and the second address byte of the 10-bit address was not acknowledged by any slave.
+ *      \arg ABRT_10ADDR1_NOACK: Master is in 10-bit address mode and the first 10-bit address byte was not acknowledged by any slave.
+ *      \arg ABRT_7B_ADDR_NOACK: Master is in 7-bit addressing mode and the address sent was not acknowledged by any slave.
+ * \return  An ErrorStatus enumeration value, SET(Last event is equal to the I2C_EVENT) or RESET(Last event is different from the I2C_EVENT).
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void i2c0_demo(void)
+ * {
+ *     FlagStatus flag_status = I2C_CheckEvent(I2C0, ABRT_SLVRD_INTX);
+ * }
+ * \endcode
+ */
+__STATIC_INLINE FlagStatus I2C_CheckEvent(I2C_TypeDef *I2Cx, uint32_t I2C_EVENT)
+{
+    FlagStatus bit_status = RESET;
+
+    /* Check the parameters */
+    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+    assert_param(IS_I2C_EVENT(I2C_EVENT));
+
+    if ((I2Cx->IC_TX_ABRT_SOURCE & I2C_EVENT) != (uint32_t)RESET)
+    {
+
+        bit_status = SET;
+    }
+
+    /* Return the I2C event status */
+    return  bit_status;
+}
+
+/**
+ * \brief   Get the specified I2C interrupt status.
+ * \param[in] I2Cx: Where x can be 0 or 1 to select the I2C peripheral.
+ * \param[in] I2C_IT
+ *      This parameter can be one of the following values, which refer to \ref I2C_Interrupts_Definition.
+ *      \arg I2C_INT_GEN_CALL: When a General Call address is received and it is acknowledged.
+ *      \arg I2C_INT_START_DET: When a START or RESTART condition has occurred on the I2C interface
+  *                            regardless of whether I2C is operating in slave or master mode.
+ *      \arg I2C_INT_STOP_DET: When a STOP condition has occurred on the I2C interface
+  *                            regardless of whether I2C is operating in slave or master mode.
+ *      \arg I2C_INT_ACTIVITY: When I2C is active on the bus. Stays set until it is cleared.
+ *      \arg I2C_INT_RX_DONE: When the I2C is acting as a slave-transmitter and the master does
+  *                           not acknowledge a transmitted byte.
+  *                           This occurs on the last byte of the transmission,
+  *                           indicating that the transmission is done.
+ *      \arg I2C_INT_TX_ABRT: When an I2C transmitter is unable to complete the intended actions
+  *                           on the contents of the transmit FIFO.
+ *      \arg I2C_INT_RD_REQ: When I2C is acting as a slave and another I2C master is attempting to read data from I2C.
+ *      \arg I2C_INT_TX_EMPTY: When the transmit buffer is at or below the threshold value set in the REG_IC_TXFLR register.
+ *      \arg I2C_INT_TX_OVER: When the transmit buffer is filled to IC_TX_BUFFER_DEPTH and
+  *                           the processor attempts to issue another I2C command by writing to the REG_IC_DATA_CMD register.
+ *      \arg I2C_INT_RX_FULL: When the receive buffer reaches or goes above the RX_TL threshold in the REG_IC_RX_TL register.
+  *                           A value of 0 sets the threshold for 1 entry, and a value of 255 sets the threshold for 256 entries.
+ *      \arg I2C_INT_RX_OVER: When the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and
+  *                           an additional byte is received from an external I2C device.
+ *      \arg I2C_INT_RX_UNDER: When the processor attempts to read the receive buffer
+  *                            when it is empty by reading from the REG_IC_DATA_CMD register.
+ * \return  The new state of I2C_IT (SET or RESET).
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void i2c0_demo(void)
+ * {
+ *     ITStatus int_status = I2C_GetINTStatus(I2C0, I2C_INT_RD_REQ);
+ * }
+ * \endcode
+ */
+__STATIC_INLINE ITStatus I2C_GetINTStatus(I2C_TypeDef *I2Cx, uint32_t I2C_IT)
+{
+    ITStatus bit_status = RESET;
+
+    /* Check the parameters */
+    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+    assert_param(I2C_GET_INT(I2C_IT));
+
+    if ((I2Cx->IC_INTR_STAT & I2C_IT) != (uint32_t)RESET)
+    {
+        bit_status = SET;
+    }
+
+    /* Return the I2C_IT status */
+    return  bit_status;
+}
+
+/**
+ * \brief   Enable or disable the I2Cx GDMA interface.
+ * \param[in] I2Cx: Where x can be 0 or 1 to select the I2C peripheral.
+ * \param[in] I2C_GDMAReq: Specify the I2C GDMA transfer request to be enabled or disabled.
+ *      This parameter can be one of the following values:
+ *      \arg I2C_GDMAReq_Tx: Tx buffer GDMA transfer request.
+ *      \arg I2C_GDMAReq_Rx: Rx buffer GDMA transfer request.
+ * \param[in] NewState: New state of the selected I2C GDMA transfer request.
+ *      This parameter can be: ENABLE or DISABLE.
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void i2c0_demo(void)
+ * {
+ *     I2C_GDMACmd(I2C0, I2C_GDMAReq_Tx, ENABLE);
+ * }
+ * \endcode
+ */
+__STATIC_INLINE void I2C_GDMACmd(I2C_TypeDef *I2Cx, uint16_t I2C_GDMAReq, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+    assert_param(IS_I2C_GDMAREQ(I2C_GDMAReq));
+
+    if (NewState != DISABLE)
+    {
+        /* Enable the selected I2C GDMA request */
+        I2Cx->IC_DMA_CR |= I2C_GDMAReq;
+    }
+    else
+    {
+        /* Disable the selected I2C GDMA request */
+        I2Cx->IC_DMA_CR &= (uint16_t)~(I2C_GDMAReq);
+    }
+}
+
+/** End of I2C_Exported_Functions
+  * \}
+  */
+
+/** End of I2C
+  * \}
+  */
+
+typedef struct
+{
+    uint32_t i2c_reg[18];
+} I2CStoreReg_TypeDef;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*_RTL8762X_I2C_H_*/
+
+
+
diff --git a/bee/drivers/i2c/src/device/rtl87x2g/rtl87x2g_i2c.c b/bee/drivers/i2c/src/device/rtl87x2g/rtl87x2g_i2c.c
new file mode 100644
index 00000000..242f9547
--- /dev/null
+++ b/bee/drivers/i2c/src/device/rtl87x2g/rtl87x2g_i2c.c
@@ -0,0 +1,212 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *                        Header Files
+ *============================================================================*/
+#include "rtl_i2c.h"
+#include "rtl_rcc.h"
+#include "app_section.h"
+
+/*============================================================================*
+ *                           Public Functions
+ *============================================================================*/
+uint8_t I2C_GetCompIndex(I2C_TypeDef *I2Cx)
+{
+    uint8_t compensate_index = 3;
+
+    if (I2Cx == I2C0)
+    {
+        compensate_index = PERIBLKCTRL_PERI_CLK->u_314.BITS_314.i2c0_div_sel;
+    }
+    else if (I2Cx == I2C1)
+    {
+        compensate_index = PERIBLKCTRL_PERI_CLK->u_314.BITS_314.i2c1_div_sel;
+    }
+    else if (I2Cx == I2C2)
+    {
+        compensate_index = PERIBLKCTRL_PERI_CLK->u_314.BITS_314.i2c2_div_sel;
+    }
+    else if (I2Cx == I2C3)
+    {
+        compensate_index = PERIBLKCTRL_PERI_CLK->u_314.BITS_314.i2c3_div_sel;
+    }
+
+    return compensate_index;
+}
+
+bool I2C_ClkGet(I2C_TypeDef *I2Cx, I2CClockSrc_TypeDef *ClockSrc, I2CClockDiv_TypeDef *ClockDiv)
+{
+    *ClockSrc = I2C_CLOCK_SRC_40M;
+    if (I2Cx == I2C0)
+    {
+        *ClockDiv = (PERIBLKCTRL_PERI_CLK->u_314.BITS_314.i2c0_div_en == 0) ? \
+                    0 : PERIBLKCTRL_PERI_CLK->u_314.BITS_314.i2c0_div_sel;
+    }
+    else if (I2Cx == I2C1)
+    {
+        *ClockDiv = (PERIBLKCTRL_PERI_CLK->u_314.BITS_314.i2c1_div_en == 0) ? \
+                    0 : PERIBLKCTRL_PERI_CLK->u_314.BITS_314.i2c1_div_sel;
+    }
+    else if (I2Cx == I2C2)
+    {
+        *ClockDiv = (PERIBLKCTRL_PERI_CLK->u_314.BITS_314.i2c2_div_en == 0) ? \
+                    0 : PERIBLKCTRL_PERI_CLK->u_314.BITS_314.i2c2_div_sel;
+    }
+    else if (I2Cx == I2C3)
+    {
+        *ClockDiv = (PERIBLKCTRL_PERI_CLK->u_314.BITS_314.i2c3_div_en == 0) ? \
+                    0 : PERIBLKCTRL_PERI_CLK->u_314.BITS_314.i2c3_div_sel;
+    }
+    else
+    {
+        return false;
+    }
+    return true;
+}
+
+/**
+  * \brief  I2C clock divider config.
+  * \param  I2Cx: Select the I2C peripheral. \ref I2C_Declaration
+  * \param  ClockDiv: specifies the APB peripheral to gates its clock. \ref Clock_Divider
+  * \return None
+  */
+void I2C_ClkDivConfig(I2C_TypeDef *I2Cx, I2CClockDiv_TypeDef ClockDiv)
+{
+    assert_param(IS_I2C_DIV(ClockDiv));
+
+    /* Config I2C clock divider */
+    if (I2Cx == I2C0)
+    {
+        PERIBLKCTRL_PERI_CLK->u_314.BITS_314.i2c0_div_en = 0;
+        PERIBLKCTRL_PERI_CLK->u_314.BITS_314.i2c0_div_sel = ClockDiv;
+        PERIBLKCTRL_PERI_CLK->u_314.BITS_314.i2c0_div_en = 1;
+    }
+    else if (I2Cx == I2C1)
+    {
+        PERIBLKCTRL_PERI_CLK->u_314.BITS_314.i2c1_div_en = 0;
+        PERIBLKCTRL_PERI_CLK->u_314.BITS_314.i2c1_div_sel = ClockDiv;
+        PERIBLKCTRL_PERI_CLK->u_314.BITS_314.i2c1_div_en = 1;
+    }
+    else if (I2Cx == I2C2)
+    {
+        PERIBLKCTRL_PERI_CLK->u_314.BITS_314.i2c2_div_en = 0;
+        PERIBLKCTRL_PERI_CLK->u_314.BITS_314.i2c2_div_sel = ClockDiv;
+        PERIBLKCTRL_PERI_CLK->u_314.BITS_314.i2c2_div_en = 1;
+    }
+    else if (I2Cx == I2C3)
+    {
+        PERIBLKCTRL_PERI_CLK->u_314.BITS_314.i2c3_div_en = 0;
+        PERIBLKCTRL_PERI_CLK->u_314.BITS_314.i2c3_div_sel = ClockDiv;
+        PERIBLKCTRL_PERI_CLK->u_314.BITS_314.i2c3_div_en = 1;
+    }
+    return;
+}
+
+/**
+  * \brief  Store I2C register values when system enter DLPS.
+  * \param  PeriReg: Specifies to select the I2C peripheral.
+  * \param  StoreBuf: Store buffer to store I2C register data.
+  * \return None.
+  */
+RAM_FUNCTION
+void I2C_DLPSEnter(void *PeriReg, void *StoreBuf)
+{
+    I2C_TypeDef *I2Cx = (I2C_TypeDef *)PeriReg;
+    I2CStoreReg_Typedef *store_buf = (I2CStoreReg_Typedef *)StoreBuf;
+
+    if (I2Cx == I2C0)
+    {
+        RCC_PeriphClockCmd(APBPeriph_I2C0, APBPeriph_I2C0_CLOCK, ENABLE);
+    }
+    else if (I2Cx == I2C1)
+    {
+        RCC_PeriphClockCmd(APBPeriph_I2C1, APBPeriph_I2C1_CLOCK, ENABLE);
+    }
+    else if (I2Cx == I2C2)
+    {
+        RCC_PeriphClockCmd(APBPeriph_I2C2, APBPeriph_I2C2_CLOCK, ENABLE);
+    }
+    else if (I2Cx == I2C3)
+    {
+        RCC_PeriphClockCmd(APBPeriph_I2C3, APBPeriph_I2C3_CLOCK, ENABLE);
+    }
+
+    store_buf->i2c_reg[0] = I2Cx->IC_CON;                 /*!< 0x00 */
+    store_buf->i2c_reg[1] = I2Cx->IC_TAR;                 /*!< 0x04 */
+    store_buf->i2c_reg[2] = I2Cx->IC_SAR;                 /*!< 0x08 */
+    store_buf->i2c_reg[3] = I2Cx->IC_FS_SPKLEN;           /*!< 0xA0 */
+
+    store_buf->i2c_reg[4] = I2Cx->IC_SS_SCL_HCNT;         /*!< 0x14 */
+    store_buf->i2c_reg[5] = I2Cx->IC_SS_SCL_LCNT;         /*!< 0x18 */
+    store_buf->i2c_reg[6] = I2Cx->IC_FS_SCL_HCNT;         /*!< 0x1C */
+    store_buf->i2c_reg[7] = I2Cx->IC_FS_SCL_LCNT;         /*!< 0x20 */
+
+    store_buf->i2c_reg[8] = I2Cx->IC_INTR_MASK;           /*!< 0x30 */
+    store_buf->i2c_reg[9] = I2Cx->IC_RX_TL;               /*!< 0x38 */
+    store_buf->i2c_reg[10] = I2Cx->IC_TX_TL;              /*!< 0x3C */
+    store_buf->i2c_reg[11] = I2Cx->IC_ENABLE;             /*!< 0x6C */
+    store_buf->i2c_reg[12] = I2Cx->IC_SDA_HOLD;           /*!< 0x7C */
+    store_buf->i2c_reg[13] = I2Cx->IC_SLV_DATA_NACK_ONLY; /*!< 0x84 */
+    store_buf->i2c_reg[14] = I2Cx->IC_DMA_CR;             /*!< 0x88 */
+    store_buf->i2c_reg[15] = I2Cx->IC_DMA_TDLR;           /*!< 0x8C */
+    store_buf->i2c_reg[16] = I2Cx->IC_DMA_RDLR;           /*!< 0x90 */
+
+    store_buf->i2c_reg[17] = I2Cx->IC_SDA_SETUP;          /*!< 0x94 */
+}
+
+/**
+  * \brief  Restore I2C register values when system enter DLPS.
+  * \param  PeriReg: Specifies to select the I2C peripheral.
+  * \param  StoreBuf: Restore buffer to restore I2C register data.
+  * \return None
+  */
+RAM_FUNCTION
+void I2C_DLPSExit(void *PeriReg, void *StoreBuf)
+{
+    I2C_TypeDef *I2Cx = (I2C_TypeDef *)PeriReg;
+    I2CStoreReg_Typedef *store_buf = (I2CStoreReg_Typedef *)StoreBuf;
+
+    if (I2Cx == I2C0)
+    {
+        RCC_PeriphClockCmd(APBPeriph_I2C0, APBPeriph_I2C0_CLOCK, ENABLE);
+    }
+    else if (I2Cx == I2C1)
+    {
+        RCC_PeriphClockCmd(APBPeriph_I2C1, APBPeriph_I2C1_CLOCK, ENABLE);
+    }
+    else if (I2Cx == I2C2)
+    {
+        RCC_PeriphClockCmd(APBPeriph_I2C2, APBPeriph_I2C2_CLOCK, ENABLE);
+    }
+    else if (I2Cx == I2C3)
+    {
+        RCC_PeriphClockCmd(APBPeriph_I2C3, APBPeriph_I2C3_CLOCK, ENABLE);
+    }
+
+    I2Cx->IC_CON         = store_buf->i2c_reg[0];
+    I2Cx->IC_TAR         = store_buf->i2c_reg[1];
+    I2Cx->IC_SAR         = store_buf->i2c_reg[2];
+    I2Cx->IC_FS_SPKLEN   = store_buf->i2c_reg[3];
+
+    I2Cx->IC_SS_SCL_HCNT = store_buf->i2c_reg[4];
+    I2Cx->IC_SS_SCL_LCNT = store_buf->i2c_reg[5];
+    I2Cx->IC_FS_SCL_HCNT = store_buf->i2c_reg[6];
+    I2Cx->IC_FS_SCL_LCNT = store_buf->i2c_reg[7];
+
+    I2Cx->IC_INTR_MASK   = store_buf->i2c_reg[8];
+    I2Cx->IC_RX_TL       = store_buf->i2c_reg[9];
+    I2Cx->IC_RX_TL       = store_buf->i2c_reg[10];
+    I2Cx->IC_ENABLE      = store_buf->i2c_reg[11];
+    I2Cx->IC_SDA_HOLD    = store_buf->i2c_reg[12];
+    I2Cx->IC_SLV_DATA_NACK_ONLY = store_buf->i2c_reg[13];
+    I2Cx->IC_DMA_CR      = store_buf->i2c_reg[14];
+    I2Cx->IC_DMA_TDLR    = store_buf->i2c_reg[15];
+    I2Cx->IC_DMA_RDLR    = store_buf->i2c_reg[16];
+
+    I2Cx->IC_SDA_SETUP   = store_buf->i2c_reg[17];
+}
+
diff --git a/bee/drivers/i2c/src/device/rtl87x2g/rtl_i2c.c b/bee/drivers/i2c/src/device/rtl87x2g/rtl_i2c.c
new file mode 100644
index 00000000..7ba7c107
--- /dev/null
+++ b/bee/drivers/i2c/src/device/rtl87x2g/rtl_i2c.c
@@ -0,0 +1,1253 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *                        Header Files
+ *============================================================================*/
+#include "rtl_i2c.h"
+#include "rtl_rcc.h"
+
+/*============================================================================*
+ *                           Private Functions
+ *============================================================================*/
+/* I2C Data Cmd Mask */
+#define I2C_CMD_READ_BIT                             (BIT8)
+#define I2C_CMD_STOP_BIT                             (BIT9)
+#define I2C_CMD_RESTART_BIT                          (BIT10)
+
+/* SDA Setup Time */
+#define I2C_SDA_SETUP_TIME_VALUE                     (2)
+
+/* SCL Low/High Period Time */
+#define I2C_SCL_HIGH_PERIOD_COMPENSATE                          (7)
+#define I2C_SCL_LOW_PERIOD_COMPENSATE                           (1)
+#define NS_PER_SECOND                                           (1000000000)
+/* I2C SCL High/Low min period according to spec */
+#define I2C_FAST_MODE_PLUS_SCL_LOW_PERIOD_MIN_NS                (500)
+#define I2C_FAST_MODE_PLUS_SCL_HIGH_PERIOD_MIN_NS               (260)
+#define I2C_FAST_MODE_SCL_LOW_PERIOD_MIN_NS                     (1300)
+#define I2C_FAST_MODE_SCL_HIGH_PERIOD_MIN_NS                    (600)
+#define I2C_STANDARD_MODE_SCL_LOW_PERIOD_MIN_NS                 (4700)
+#define I2C_STANDARD_MODE_SCL_HIGH_PERIOD_MIN_NS                (4000)
+/* SDA Hold Time */
+#define I2C_STANDARD_FAST_MODE_SDA_HOLD_TIME_NS                 (600)
+#define I2C_FAST_MODE_PLUS_SDA_HOLD_TIME_NS                     (300)
+
+#define ROUNDUP(a, b)                                (((a + b - 1) / b))
+
+uint32_t I2C_TimeOut = 0xFFF;
+static uint32_t I2C_RisingTimeNs;
+extern uint8_t I2C_GetCompIndex(I2C_TypeDef *I2Cx);
+
+/*============================================================================*
+ *                           Public Functions
+ *============================================================================*/
+/**
+  * \brief  Deinitializes the I2Cx peripheral registers to their default reset values.
+  * \param  I2Cx: Select the I2C peripheral. \ref I2C_Declaration
+  * \return None
+  */
+void I2C_DeInit(I2C_TypeDef *I2Cx)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+    /*Disable I2C IP*/
+    switch ((uint32_t)I2Cx)
+    {
+#ifdef I2C0
+    case (uint32_t)I2C0:
+        RCC_PeriphClockCmd(APBPeriph_I2C0, APBPeriph_I2C0_CLOCK, DISABLE);
+        break;
+#endif
+#ifdef I2C1
+    case (uint32_t)I2C1:
+        RCC_PeriphClockCmd(APBPeriph_I2C1, APBPeriph_I2C1_CLOCK, DISABLE);
+        break;
+#endif
+#ifdef I2C2
+    case (uint32_t)I2C2:
+        RCC_PeriphClockCmd(APBPeriph_I2C2, APBPeriph_I2C2_CLOCK, DISABLE);
+        break;
+#endif
+#ifdef I2C3
+    case (uint32_t)I2C3:
+        RCC_PeriphClockCmd(APBPeriph_I2C3, APBPeriph_I2C3_CLOCK, DISABLE);
+        break;
+#endif
+
+    default:
+        break;
+    }
+}
+
+/**
+  * \brief  Initializes the I2Cx peripheral according to the specified
+  *         parameters in the I2C_InitStruct.
+  * \param  I2Cx: Select the I2C peripheral. \ref I2C_Declaration
+  * \param  I2C_InitStruct: Pointer to a I2C_InitTypeDef structure that
+  *         contains the configuration information for the specified I2C peripheral.
+  * \return None
+  */
+void I2C_Init(I2C_TypeDef *I2Cx, I2C_InitTypeDef *I2C_InitStruct)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+    assert_param(IS_I2C_CLOCK_SPEED(I2C_InitStruct->I2C_ClockSpeed));
+
+    /* Disable I2C device before change configuration */
+    IC_ENABLE_TypeDef i2c_0x6c = {.d32 = I2Cx->IC_ENABLE};
+    i2c_0x6c.b.ic_enable = 0x0;
+    I2Cx->IC_ENABLE = i2c_0x6c.d32;
+
+    /* Config sda tx hold time in different clock speed */
+    uint8_t sda_tx_hold = 0;
+    uint8_t compensate_index = I2C_GetCompIndex(I2Cx);
+    uint32_t I2CSrcClk = 0;
+
+    if (compensate_index == 6)
+    {
+        I2CSrcClk = 1000000;
+    }
+    else if (compensate_index == 7)
+    {
+        I2CSrcClk = 625000;
+    }
+    else
+    {
+        I2CSrcClk = 40000000 / BIT(compensate_index);
+    }
+    uint32_t i2c_source_clock_ns = NS_PER_SECOND / I2CSrcClk;
+
+    if ((I2CSrcClk == 40000000) && (I2C_InitStruct->I2C_ClockSpeed > 400000))
+    {
+        sda_tx_hold = I2C_FAST_MODE_PLUS_SDA_HOLD_TIME_NS / i2c_source_clock_ns;
+    }
+    else
+    {
+        sda_tx_hold = (I2C_STANDARD_FAST_MODE_SDA_HOLD_TIME_NS / i2c_source_clock_ns == 0) ? 1 :
+                      (I2C_STANDARD_FAST_MODE_SDA_HOLD_TIME_NS / i2c_source_clock_ns);
+    }
+
+    /* ------------------------------ Initialize I2C device ------------------------------*/
+    if (I2C_DeviveMode_Master == I2C_InitStruct->I2C_DeviveMode)
+    {
+        /* Configure I2C device mode which can be selected for master or slave */
+        IC_CON_TypeDef i2c_0x00 = {.d32 = I2Cx->IC_CON};
+        i2c_0x00.b.master_mode = 0x1;
+        i2c_0x00.b.ic_slave_disable = 0x1;
+        i2c_0x00.b.ic_restart_en = 0x1;
+        I2Cx->IC_CON = i2c_0x00.d32;
+
+        /* Set target address */
+        IC_TAR_TypeDef i2c_0x04 = {.d32 = I2Cx->IC_TAR};
+        i2c_0x04.b.ic_10bitaddr_master = I2C_InitStruct->I2C_AddressMode;
+        i2c_0x04.b.ic_tar = I2C_InitStruct->I2C_SlaveAddress;
+        I2Cx->IC_TAR = i2c_0x04.d32;
+
+        /* Set SDA hold time in master mode */
+        IC_SDA_HOLD_TypeDef i2c_0x7c = {.d32 = I2Cx->IC_SDA_HOLD};
+        i2c_0x7c.b.ic_sda_tx_hold = sda_tx_hold;
+        i2c_0x7c.b.ic_sda_rx_hold = 0x1;
+        I2Cx->IC_SDA_HOLD = i2c_0x7c.d32;
+
+        I2C_RisingTimeNs = I2C_InitStruct->I2C_RisingTimeNs;
+        /* Configure I2C speed */
+        I2C_SetClockSpeed(I2Cx, I2C_InitStruct->I2C_ClockSpeed);
+    }
+    else
+    {
+        /* Set to slave mode */
+        IC_CON_TypeDef i2c_0x00 = {.d32 = I2Cx->IC_CON};
+        i2c_0x00.b.master_mode = 0x0;
+        i2c_0x00.b.ic_10bitaddr_slave = I2C_InitStruct->I2C_AddressMode;
+        i2c_0x00.b.ic_slave_disable = 0x0;
+        I2Cx->IC_CON = i2c_0x00.d32;
+
+        /* Set slave address */
+        IC_SAR_TypeDef i2c_0x08 = {.d32 = I2Cx->IC_SAR};
+        i2c_0x08.b.ic_sar = I2C_InitStruct->I2C_SlaveAddress;
+        I2Cx->IC_SAR = i2c_0x08.d32;
+
+        /* Set Ack in slave mode */
+        IC_ACK_GENERAL_CALL_TypeDef i2c_0x98 = {.d32 = I2Cx->IC_ACK_GENERAL_CALL};
+        i2c_0x98.b.ack_gen_call &= I2C_InitStruct->I2C_Ack;
+        I2Cx->IC_ACK_GENERAL_CALL = i2c_0x98.d32;
+
+        /* Set SDA hold time in slave mode */
+        IC_SDA_HOLD_TypeDef i2c_0x7c = {.d32 = I2Cx->IC_SDA_HOLD};
+        i2c_0x7c.b.ic_sda_tx_hold = sda_tx_hold;
+        i2c_0x7c.b.ic_sda_rx_hold = 0x08;
+        I2Cx->IC_SDA_HOLD = i2c_0x7c.d32;
+
+        /* Set SDA setup time delay only in slave transmitter mode(greater than 2) ,delay time:[(IC_SDA_SETUP - 1) * (ic_clk_period)]*/
+        IC_SDA_SETUP_TypeDef i2c_0x94 = {.d32 = I2Cx->IC_SDA_SETUP};
+        i2c_0x94.b.sda_setup = I2C_SDA_SETUP_TIME_VALUE;
+        I2Cx->IC_SDA_SETUP = i2c_0x94.d32;
+    }
+
+    /* Set Tx empty level */
+    IC_TX_TL_TypeDef i2c_0x3c = {.d32 = I2Cx->IC_TX_TL};
+    i2c_0x3c.b.tx_tl = I2C_InitStruct->I2C_TxThresholdLevel;
+    I2Cx->IC_TX_TL = i2c_0x3c.d32;
+
+    /*set Rx full level*/
+    IC_RX_TL_TypeDef i2c_0x40 = {.d32 = I2Cx->IC_RX_TL};
+    i2c_0x40.b.rx_tl = I2C_InitStruct->I2C_RxThresholdLevel;
+    I2Cx->IC_RX_TL = i2c_0x40.d32;
+
+    /* Config I2C dma mode */
+    IC_DMA_CR_TypeDef i2c_0x88 = {.d32 = I2Cx->IC_DMA_CR};
+    i2c_0x88.b.rdmae = I2C_InitStruct->I2C_RxDmaEn;
+    i2c_0x88.b.tdmae = I2C_InitStruct->I2C_TxDmaEn;
+    I2Cx->IC_DMA_CR = i2c_0x88.d32;
+
+    /* Config I2C waterlevel */
+    IC_DMA_TDLR_TypeDef i2c_0x8c = {.d32 = I2Cx->IC_DMA_TDLR};
+    IC_DMA_RDLR_TypeDef i2c_0x90 = {.d32 = I2Cx->IC_DMA_RDLR};
+    i2c_0x8c.b.dmatdl = I2C_InitStruct->I2C_TxWaterlevel;
+    i2c_0x90.b.dmardl = I2C_InitStruct->I2C_RxWaterlevel;
+    I2Cx->IC_DMA_TDLR = i2c_0x8c.d32;
+    I2Cx->IC_DMA_RDLR = i2c_0x90.d32;
+
+    /* Mask all interrupt */
+    I2Cx->IC_INTR_MASK = 0x0;
+}
+
+/**
+  * \brief  Fills each I2C_InitStruct member with its default value.
+  * \param  I2C_InitStruct : pointer to a I2C_InitTypeDef structure which will be initialized.
+  * \return None
+  */
+void I2C_StructInit(I2C_InitTypeDef *I2C_InitStruct)
+{
+    /* I2C source clock is 40MHz, depending on clock divider */
+    I2C_InitStruct->I2C_Clock             = 40000000;
+    /* I2C SCK freqency is 400KHz */
+    I2C_InitStruct->I2C_ClockSpeed        = 400000;
+    /* Master mode */
+    I2C_InitStruct->I2C_DeviveMode        = I2C_DeviveMode_Master;
+    /* 7-bit address mode */
+    I2C_InitStruct->I2C_AddressMode       = I2C_AddressMode_7BIT;
+    /* Set slave address */
+    I2C_InitStruct->I2C_SlaveAddress      = 0;
+    /* Enable acknowledge in slave mode */
+    I2C_InitStruct->I2C_Ack               = ENABLE;
+    /* Tx fifo depth: 24 * 8bits */
+    I2C_InitStruct->I2C_TxThresholdLevel  = 0;
+    /* Rx fifo depth: 24 * 8bits */
+    I2C_InitStruct->I2C_RxThresholdLevel  = 0;
+    /* Disable dma */
+    I2C_InitStruct->I2C_TxDmaEn           = DISABLE;
+    I2C_InitStruct->I2C_RxDmaEn           = DISABLE;
+    /* I2C Tx waterlevel, should be less than fifo threshold.
+       The best value is I2C FIFO Depth - GDMA Msize */
+    I2C_InitStruct->I2C_TxWaterlevel      = 23;
+    /* I2C Rx waterlevel, should be less than fifo threshold.
+       The best value is GDMA Msize */
+    I2C_InitStruct->I2C_RxWaterlevel      = 1;
+    /* Specify I2C scl rising time with 2.2K ohm pull up resistor, the unit is ns*/
+    I2C_InitStruct->I2C_RisingTimeNs     = 50;
+
+}
+
+/**
+  * \brief  Enable or disable the specified I2C peripheral.
+  * \param  I2Cx: Select the I2C peripheral. \ref I2C_Declaration
+  * \param  NewState: New state of the I2Cx peripheral.
+  *         This parameter can be: ENABLE or DISABLE.
+  * \return None
+  */
+void I2C_Cmd(I2C_TypeDef *I2Cx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    /* Enable or disable the selected I2C peripheral */
+    IC_ENABLE_TypeDef i2c_0x6c = {.d32 = I2Cx->IC_ENABLE};
+    i2c_0x6c.b.ic_enable = NewState;
+    I2Cx->IC_ENABLE = i2c_0x6c.d32;
+}
+
+
+/**
+  * \brief  Checks whether the last I2Cx abort status.
+  * \param  I2Cx: Select the I2C peripheral. \ref I2C_Declaration
+  * \return I2C_Status: The status of I2Cx. \ref I2C_Status
+  */
+I2C_Status I2C_CheckAbortStatus(I2C_TypeDef *I2Cx)
+{
+    uint32_t abort_status = 0;
+
+    /* Check the parameters */
+    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+    /* Get abort status */
+    abort_status = I2Cx->IC_TX_ABRT_SOURCE;
+
+    if (abort_status & MS_ALL_ABORT)
+    {
+        /* Clear abort status */
+        (void)I2Cx->IC_CLR_TX_ABRT;
+
+        /* Check abort type */
+        if (abort_status & ABRT_TXDATA_NOACK)
+        {
+            return I2C_ABRT_TXDATA_NOACK;
+        }
+
+        if (abort_status & ABRT_7B_ADDR_NOACK)
+        {
+            return I2C_ABRT_7B_ADDR_NOACK;
+        }
+
+        if (abort_status & ARB_LOST)
+        {
+            return I2C_ARB_LOST;
+        }
+
+        if (abort_status & ABRT_MASTER_DIS)
+        {
+            return I2C_ABRT_MASTER_DIS;
+        }
+
+        if (abort_status & ABRT_10ADDR1_NOACK)
+        {
+            return I2C_ABRT_10ADDR1_NOACK;
+        }
+
+        if (abort_status & ABRT_10ADDR2_NOACK)
+        {
+            return I2C_ABRT_10ADDR2_NOACK;
+        }
+    }
+
+    return I2C_Success;
+}
+
+I2C_Status I2C_WaitForFIFO(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG)
+{
+    uint32_t timeout = I2C_TimeOut;
+
+    /* Wait until the FIFO condition selected by I2C_FLAG becomes true:
+     * - TX: writable (TX FIFO Not Full, space available)
+     * - RX: readable (RX FIFO Not Empty, data available)
+     */
+    while (((I2Cx->IC_STATUS & I2C_FLAG) == 0) && (timeout != 0))
+    {
+        I2C_Status status = I2C_CheckAbortStatus(I2Cx);
+        if (status != I2C_Success)
+        {
+            return status;
+        }
+
+        if (--timeout == 0)
+        {
+            return I2C_ERR_TIMEOUT;
+        }
+    }
+
+    return I2C_CheckAbortStatus(I2Cx);
+}
+
+I2C_Status I2C_WaitTXIdle(I2C_TypeDef *I2Cx)
+{
+    uint32_t timeout = I2C_TimeOut;
+
+    /* Wait until the transmit is fully completed:
+     * - Bus becomes idle (ACTIVITY == 0)
+     * - TX FIFO is empty (TFE == 1)
+     */
+    while ((((I2Cx->IC_STATUS & I2C_FLAG_ACTIVITY) != 0) ||
+            ((I2Cx->IC_STATUS & I2C_FLAG_TFE) == 0)) &&
+           (timeout != 0))
+    {
+        I2C_Status status = I2C_CheckAbortStatus(I2Cx);
+        if (status != I2C_Success)
+        {
+            return status;
+        }
+
+        if (--timeout == 0)
+        {
+            return I2C_ERR_TIMEOUT;
+        }
+    }
+
+    return I2C_Success;
+}
+
+
+/**
+  * \brief  Send data in master mode through the I2Cx peripheral.
+  * \param  I2Cx: Select the I2C peripheral. \ref I2C_Declaration
+  * \param  pBuf: Byte to be transmitted.
+  * \param  len: Data length to send.
+  * \return I2C_Status: The status of I2Cx. \ref I2C_Status
+  */
+I2C_Status I2C_MasterWrite(I2C_TypeDef *I2Cx, uint8_t *pBuf, uint16_t len)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+    I2C_Status status = I2C_Success;
+
+    for (uint16_t i = 0; i < len; i++)
+    {
+        uint32_t cmd = *pBuf++;
+        if (i == (len - 1))
+        {
+            cmd |= I2C_CMD_STOP_BIT;
+        }
+        I2Cx->IC_DATA_CMD = cmd;
+
+        status = I2C_WaitForFIFO(I2Cx, I2C_FLAG_TFNF);
+        if (status != I2C_Success)
+        {
+            return status;
+        }
+    }
+
+    return I2C_WaitTXIdle(I2Cx);
+}
+
+/**
+  * \brief  Send device write data in master mode through the I2Cx peripheral.
+  * \param  I2Cx: Select the I2C peripheral. \ref I2C_Declaration
+  * \param  Data: Byte to be transmitted..
+  * \return None
+  */
+I2C_Status I2C_MasterWriteDevice(I2C_TypeDef *I2Cx, uint8_t *pBuf, uint16_t len, uint8_t *pbuf2,
+                                 uint32_t len2)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+    I2C_Status status = I2C_Success;
+
+    /* Write in the DR register the data to be sent */
+    for (uint16_t i = 0; i < len; i++)
+    {
+        I2Cx->IC_DATA_CMD = *pBuf++;
+
+        status = I2C_WaitForFIFO(I2Cx, I2C_FLAG_TFNF);
+        if (status != I2C_Success)
+        {
+            return status;
+        }
+    }
+
+    for (uint16_t i = 0; i < len2; i++)
+    {
+        uint32_t cmd = *pbuf2++;
+        if (i == (len2 - 1))
+        {
+            cmd |= I2C_CMD_STOP_BIT;
+        }
+        I2Cx->IC_DATA_CMD = cmd;
+
+        status = I2C_WaitForFIFO(I2Cx, I2C_FLAG_TFNF);
+        if (status != I2C_Success)
+        {
+            return status;
+        }
+    }
+
+    return I2C_WaitTXIdle(I2Cx);
+}
+
+/**
+  * \brief  Read data in master mode through the I2Cx peripheral.
+  * \param  I2Cx: Select the I2C peripheral. \ref I2C_Declaration
+  * \param  pBuf: Data buffer to receive data.
+  * \param  len: Read data length.
+  * \return I2C_Status: The status of I2Cx. \ref I2C_Status
+  */
+I2C_Status I2C_MasterRead(I2C_TypeDef *I2Cx, uint8_t *pBuf, uint16_t len)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+    I2C_Status status = I2C_Success;
+
+    if (len == 0)
+    {
+        return status;
+    }
+
+    /* Issue the first read cmd. If only one byte is requested, append STOP immediately. */
+    uint32_t cmd = 0x0 | I2C_CMD_READ_BIT;
+    if (len == 1)
+    {
+        cmd |= I2C_CMD_STOP_BIT;
+    }
+    I2Cx->IC_DATA_CMD = cmd;
+
+    for (uint16_t i = 1; i < len; i++)
+    {
+        /* Issue the remaining read cmd. */
+        cmd = 0x0 | I2C_CMD_READ_BIT;
+        if (i == (len - 1))
+        {
+            cmd |= I2C_CMD_STOP_BIT;
+        }
+        I2Cx->IC_DATA_CMD = cmd;
+
+        /* Read byte produced by the read. */
+        status = I2C_WaitForFIFO(I2Cx, I2C_FLAG_RFNE);
+        if (status != I2C_Success)
+        {
+            return status;
+        }
+        *pBuf++ = (uint8_t)I2Cx->IC_DATA_CMD;
+    }
+
+    /* Read the final byte produced by the last command. */
+    status = I2C_WaitForFIFO(I2Cx, I2C_FLAG_RFNE);
+    if (status != I2C_Success)
+    {
+        return status;
+    }
+    *pBuf = (uint8_t)I2Cx->IC_DATA_CMD;
+
+    return status;
+}
+
+/**
+  * \brief  Sends data and read data in master mode through the I2Cx peripheral.Attention:Read data with time out mechanism.
+  * \param  I2Cx: Select the I2C peripheral. \ref I2C_Declaration
+  * \param  pWriteBuf: Data buffer to send before read.
+  * \param  Writelen: Send data length.
+  * \param  pReadBuf: Data buffer to receive.
+  * \param  Readlen: Receive data length.
+  * \return I2C_Status: The status of I2Cx. \ref I2C_Status
+  */
+I2C_Status I2C_RepeatRead(I2C_TypeDef *I2Cx, uint8_t *pWriteBuf, uint16_t Writelen,
+                          uint8_t *pReadBuf, uint16_t Readlen)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+    I2C_Status status = I2C_Success;
+
+    for (uint16_t i = 0; i < Writelen; i++)
+    {
+        I2Cx->IC_DATA_CMD = *pWriteBuf++;
+
+        status = I2C_WaitForFIFO(I2Cx, I2C_FLAG_TFNF);
+        if (status != I2C_Success)
+        {
+            return status;
+        }
+    }
+
+    for (uint16_t i = 0; i < Readlen; i++)
+    {
+        /* Issue the read cmd. */
+        uint32_t cmd = 0x0 | I2C_CMD_READ_BIT;
+        if (i == (Readlen - 1))
+        {
+            cmd |= I2C_CMD_STOP_BIT;
+        }
+        I2Cx->IC_DATA_CMD = cmd;
+
+        /* Read byte produced by the read. */
+        status = I2C_WaitForFIFO(I2Cx, I2C_FLAG_RFNE);
+        if (status != I2C_Success)
+        {
+            return status;
+        }
+        *pReadBuf++ = (uint8_t)I2Cx->IC_DATA_CMD;
+    }
+
+
+    return status;
+}
+
+/**
+  * \brief Mask the specified I2C interrupt.
+  * \param  I2Cx: Select the I2C peripheral. \ref I2C_Declaration
+  * \param  I2C_INT: This parameter can be one of the following values:
+  *         \arg I2C_INT_MST_ON_HOLD: Indicates whether a master is holding the bus.
+  *         \arg I2C_INT_GEN_CALL: Set only when a General Call address is received and it is acknowledged.
+  *         \arg I2C_INT_START_DET: Indicates whether a START or RESTART condition has occurred on the I2C
+  *              interface regardless of whether I2C is operating in slave or master mode.
+  *         \arg I2C_INT_STOP_DET: Indicates whether a STOP condition has occurred on the I2C interface regardless
+  *              of whether I2C is operating in slave or master mode
+  *         \arg I2C_INT_ACTIVITY: This bit captures I2C activity and stays set until it is cleared.
+  *         \arg I2C_INT_RX_DONE: When the I2C is acting as a slave-transmitter, this bit is set to 1 if the
+  *              master does not acknowledge a transmitted byte. This occurs on the last byte of
+  *              the transmission, indicating that the transmission is done.
+  *         \arg I2C_INT_TX_ABRT: This bit indicates if I2C as an I2C transmitter, is unable to complete the
+  *              intended actions on the contents of the transmit FIFO.
+  *         \arg I2C_INT_RD_REQ: This bit is set to 1 when acting as a slave and another I2C master
+  *              is attempting to read data.
+  *         \arg I2C_INT_TX_EMPTY: This bit is set to 1 when the transmit buffer is at or below the threshold value set
+  *              in the IC_TX_TL register.
+  *         \arg I2C_INT_TX_OVER: Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH and
+  *              the processor attempts to issue another I2C command.
+  *         \arg I2C_INT_RX_FULL: Set when the receive buffer reaches or goes above the RX_TL threshold in the
+  *              IC_RX_TL register
+  *         \arg I2C_INT_RX_OVER: Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and an
+  *              additional byte is received from an external I2C device.
+  *         \arg I2C_INT_RX_UNDER: Set if the processor attempts to read the receive buffer when it is empty by reading.
+  * \return None.
+  */
+void I2C_INTConfig(I2C_TypeDef *I2Cx, uint16_t I2C_INT, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+    assert_param(I2C_GET_INT(I2C_INT));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (NewState != DISABLE)
+    {
+        /* Enable the selected I2C interrupts */
+        I2Cx->IC_INTR_MASK |= I2C_INT;
+    }
+    else
+    {
+        /* Disable the selected I2C interrupts */
+        I2Cx->IC_INTR_MASK &= (uint16_t)~I2C_INT;
+    }
+}
+
+/**
+  * \brief clear the specified I2C interrupt.
+  * \param  I2Cx: Select the I2C peripheral. \ref I2C_Declaration
+  * \param  I2C_INT: This parameter can be one of the following values:
+  *         \arg I2C_INT_GEN_CALL: Set only when a General Call address is received and it is acknowledged.
+  *         \arg I2C_INT_START_DET: Indicates whether a START or RESTART condition has occurred on the I2C
+  *              interface regardless of whether I2C is operating in slave or master mode.
+  *         \arg I2C_INT_STOP_DET: Indicates whether a STOP condition has occurred on the I2C interface regardless
+  *              of whether I2C is operating in slave or master mode
+  *         \arg I2C_INT_ACTIVITY: This bit captures I2C activity and stays set until it is cleared.
+  *         \arg I2C_INT_RX_DONE: When the I2C is acting as a slave-transmitter, this bit is set to 1 if the
+  *              master does not acknowledge a transmitted byte. This occurs on the last byte of
+  *              the transmission, indicating that the transmission is done.
+  *         \arg I2C_INT_TX_ABRT: This bit indicates if I2C as an I2C transmitter, is unable to complete the
+  *              intended actions on the contents of the transmit FIFO.
+  *         \arg I2C_INT_RD_REQ: This bit is set to 1 when acting as a slave and another I2C master
+  *              is attempting to read data.
+  *         \arg I2C_INT_TX_EMPTY: This bit is set to 1 when the transmit buffer is at or below the threshold value set
+  *              in the IC_TX_TL register.
+  *         \arg I2C_INT_TX_OVER: Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH and
+  *              the processor attempts to issue another I2C command.
+  *         \arg I2C_INT_RX_FULL: Set when the receive buffer reaches or goes above the RX_TL threshold in the
+  *              IC_RX_TL register
+  *         \arg I2C_INT_RX_OVER: Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and an
+  *              additional byte is received from an external I2C device.
+  *         \arg I2C_INT_RX_UNDER: Set if the processor attempts to read the receive buffer when it is empty by reading.
+  * \return None.
+  */
+void I2C_ClearINTPendingBit(I2C_TypeDef *I2Cx, uint16_t I2C_IT)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+    assert_param(I2C_GET_INT(I2C_IT));
+
+    switch (I2C_IT)
+    {
+    case I2C_INT_RX_UNDER:
+        {
+            (void)I2Cx->IC_CLR_RX_UNDER;
+            break;
+        }
+    case I2C_INT_RX_OVER:
+        {
+            (void)I2Cx->IC_CLR_RX_OVER;
+            break;
+        }
+    case I2C_INT_TX_OVER:
+        {
+            (void)I2Cx->IC_CLR_TX_OVER;
+            break;
+        }
+    case I2C_INT_RD_REQ:
+        {
+            (void)I2Cx->IC_CLR_RD_REQ;
+            break;
+        }
+    case I2C_INT_TX_ABRT:
+        {
+            (void)I2Cx->IC_CLR_TX_ABRT;
+            break;
+        }
+    case I2C_INT_RX_DONE:
+        {
+            (void)I2Cx->IC_CLR_RX_DONE;
+            break;
+        }
+    case I2C_INT_ACTIVITY:
+        {
+            (void)I2Cx->IC_CLR_ACTIVITY;
+            break;
+        }
+    case I2C_INT_STOP_DET:
+        {
+            (void)I2Cx->IC_CLR_STOP_DET;
+            break;
+        }
+    case I2C_INT_START_DET:
+        {
+            (void)I2Cx->IC_CLR_START_DET;
+            break;
+        }
+    case I2C_INT_GEN_CALL:
+        {
+            (void)I2Cx->IC_CLR_GEN_CALL;
+            break;
+        }
+    default:
+        {
+            break;
+        }
+    }
+}
+
+/**
+ * \brief   Set slave device address.
+ * \param   I2Cx: Select the I2C peripheral. \ref I2C_Declaration
+ * \param   Address: Specifies the slave address which will be transmitte.
+ * \return  None.
+ */
+void I2C_SetSlaveAddress(I2C_TypeDef *I2Cx, uint16_t Address)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+    /* Configure new target address */
+    IC_TAR_TypeDef i2c_0x04 = {.d32 = I2Cx->IC_TAR};
+    i2c_0x04.b.ic_tar = Address;
+    I2Cx->IC_TAR = i2c_0x04.d32;
+}
+
+/**
+ * \brief   Write command through the I2Cx peripheral.
+ * \param   I2Cx: Select the I2C peripheral. \ref I2C_Declaration
+ * \param   command: Command of write or read.
+ *          \arg I2C_READ_CMD: Read command. Data which want to transmit can be 0 in this situation.
+ *          \arg I2C_WRITE_CMD: Write command.
+ * \param   data: Data which to be transmitted.
+ * \param   StopState: Whether send stop signal.
+ *          \arg ENABLE: Send stop signal.
+ *          \arg DISABLE: Do not send stop signal.
+ * \return  None.
+ */
+void I2C_SendCmd(I2C_TypeDef *I2Cx, I2CSendCommend_TypeDef command, uint8_t data,
+                 FunctionalState StopState)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+    assert_param(IS_I2C_CMD(command));
+
+    IC_DATA_CMD_TypeDef i2c_0x10 = {.d32 = 0};
+    i2c_0x10.d32 = 0;
+    i2c_0x10.b.cmd = command;
+    i2c_0x10.b.stop = StopState;
+    i2c_0x10.b.dat = data;
+    I2Cx->IC_DATA_CMD = i2c_0x10.d32;
+}
+
+/**
+ * \brief   Received data by the I2Cx peripheral.
+ * \param   I2Cx: Select the I2C peripheral. \ref I2C_Declaration
+ * \return  Return the most recent received data.
+ */
+uint8_t I2C_ReceiveData(I2C_TypeDef *I2Cx)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+    /* Return the data in the DR register */
+    return (uint8_t)I2Cx->IC_DATA_CMD;
+}
+
+/**
+ * \brief   Get data length in Rx FIFO of the I2Cx peripheral.
+ * \param   I2Cx: Select the I2C peripheral. \ref I2C_Declaration
+ * \return  Current data number in Rx FIFO.
+ */
+uint8_t I2C_GetRxFIFOLen(I2C_TypeDef *I2Cx)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+    return (uint8_t)I2Cx->IC_RXFLR;
+}
+
+/**
+ * \brief   Get data length in Tx FIFO of the I2Cx peripheral.
+ * \param   I2Cx: Select the I2C peripheral. \ref I2C_Declaration
+ * \return  Current data number in Tx FIFO.
+ */
+uint8_t I2C_GetTxFIFOLen(I2C_TypeDef *I2Cx)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+    return (uint8_t)I2Cx->IC_TXFLR;
+}
+
+/**
+ * \brief   Clear all I2C interrupt.
+ * \param   I2Cx: Select the I2C peripheral. \ref I2C_Declaration
+ * \return  None.
+ */
+void I2C_ClearAllINT(I2C_TypeDef *I2Cx)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+    (void)I2Cx->IC_CLR_INTR;
+}
+
+/**
+ * \brief   Check whether the specified I2C flag is set.
+ * \param   I2Cx: Select the I2C peripheral. \ref I2C_Declaration
+ * \param   I2C_FLAG: Specifies the flag to check.
+ *          This parameter can be one of the following values:
+ *          \arg I2C_FLAG_SLV_HOLD_RX_FIFO_FULL: The BUS Hold in Slave mode due to the Rx FIFO being Full and an additional byte being received.
+ *          \arg I2C_FLAG_SLV_HOLD_TX_FIFO_EMPTY: The BUS Hold in Slave mode for the Read request when the Tx FIFO is empty.
+ *          \arg I2C_FLAG_MST_HOLD_RX_FIFO_FULL: The BUS Hold in Master mode due to Rx FIFO is full and additional byte has been received.
+ *          \arg I2C_FLAG_MST_HOLD_TX_FIFO_EMPTY: The BUS hold when the master holds the bus because of the Tx FIFO being empty.
+ *          \arg I2C_FLAG_SLV_ACTIVITY: Slave FSM activity status.
+ *          \arg I2C_FLAG_MST_ACTIVITY: Master FSM activity status.
+ *          \arg I2C_FLAG_RFF: Receive FIFO completely full.
+ *          \arg I2C_FLAG_RFNE: Receive FIFO not empty.
+ *          \arg I2C_FLAG_TFE: Transmit FIFO completely empty.
+ *          \arg I2C_FLAG_TFNF: Transmit FIFO not full.
+ *          \arg I2C_FLAG_ACTIVITY: I2C activity status.
+ */
+FlagStatus I2C_GetFlagState(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG)
+{
+    FlagStatus bit_status = RESET;
+
+    /* Check the parameters */
+    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+    assert_param(IS_I2C_GET_FLAG(I2C_FLAG));
+
+    if ((I2Cx->IC_STATUS & I2C_FLAG) != (uint32_t)RESET)
+    {
+        /* I2C_FLAG is set */
+        bit_status = SET;
+    }
+
+    /* Return the I2C_FLAG status */
+    return  bit_status;
+}
+
+/**
+ * \brief   Check whether the last I2Cx event is equal to the one passed as parameter.
+ * \param   I2Cx: Select the I2C peripheral. \ref I2C_Declaration
+ * \param   I2C_EVENT: specifies the event to be checked about I2C Transmit Abort Status Register.
+ *          This parameter can be one of the following values:
+ *          \arg ABRT_SLVRD_INTX: When the processor side responds to a slave mode request for data to be transmitted to a remote master and user send read command.
+ *          \arg ABRT_SLV_ARBLOST: Slave lost the bus while transmitting data to a remote master.
+ *          \arg ABRT_SLVFLUSH_TXFIFO: Slave has received a read command and some data exists in the TX FIFO so the slave issues a TX_ABRT interrupt to flush old data in TX FIFO.
+ *          \arg ARB_LOST: Master has lost arbitration or the slave transmitter has lost arbitration.
+ *          \arg ABRT_MASTER_DIS: User tries to initiate a Master operation with the Master mode disabled
+ *          \arg ABRT_10B_RD_NORSTRT: The restart is disabled and the master sends a read command in 10-bit addressing mode.
+ *          \arg ABRT_SBYTE_NORSTRT: The restart is disabled and the user is trying to send a START Byte.
+ *          \arg ABRT_HS_NORSTRT: The restart is disabled and the user is trying to use the master to transfer data in High Speed mode.
+ *          \arg ABRT_SBYTE_ACKDET: Master has sent a START Byte and the START Byte was acknowledged (wrong behavior).
+ *          \arg ABRT_HS_ACKDET: Master is in High Speed mode and the High Speed Master code was acknowledged (wrong behavior).
+ *          \arg ABRT_GCALL_READ: Sent a General Call but the user programmed the byte following the General Call to be a read from the bus.
+ *          \arg ABRT_GCALL_NOACK: Sent a General Call and no slave on the bus acknowledged the General Call.
+ *          \arg ABRT_TXDATA_NOACK: Master sent data byte(s) following the address, it did not receive an acknowledge from the remote slave.
+ *          \arg ABRT_10ADDR2_NOACK: Master is in 10-bit address mode and the second address byte of the 10-bit address was not acknowledged by any slave.
+ *          \arg ABRT_10ADDR1_NOACK: Master is in 10-bit address mode and the first 10-bit address byte was not acknowledged by any slave.
+ *          \arg ABRT_7B_ADDR_NOACK: Master is in 7-bit addressing mode and th address sent was not acknowledged by any slave.
+ * \return  An ErrorStatus enumeration value.
+ *          \retval  SUCCESS: Last event is equal to the I2C_EVENT.
+ *          \retval  ERROR: Last event is different from the I2C_EVENT.
+ */
+FlagStatus I2C_CheckEvent(I2C_TypeDef *I2Cx, uint32_t I2C_EVENT)
+{
+    FlagStatus bit_status = RESET;
+
+    /* Check the parameters */
+    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+    assert_param(IS_I2C_EVENT(I2C_EVENT));
+
+    if ((I2Cx->IC_TX_ABRT_SOURCE & I2C_EVENT) != (uint32_t)RESET)
+    {
+
+        bit_status = SET;
+    }
+
+    /* Return the I2C event status */
+    return  bit_status;
+}
+
+/**
+ * \brief   Get the specified I2C interrupt status.
+ * \param   I2Cx: Select the I2C peripheral. \ref I2C_Declaration
+ * \param   I2C_IT: This parameter can be one of the following values:
+ *          \arg I2C_INT_MST_ON_HOLD: Indicates whether a master is holding the bus.
+ *          \arg I2C_INT_GEN_CALL: Set only when a General Call address is received and it is acknowledged.
+ *          \arg I2C_INT_START_DET: Indicates whether a START or RESTART condition has occurred on the I2C
+ *               interface regardless of whether DW_apb_i2c is operating in slave or master mode.
+ *          \arg I2C_INT_STOP_DET: Indicates whether a STOP condition has occurred on the I2C interface regardless
+ *               of whether DW_apb_i2c is operating in slave or master mode
+ *          \arg I2C_INT_ACTIVITY: This bit captures DW_apb_i2c activity and stays set until it is cleared.
+ *          \arg I2C_INT_RX_DONE: When the DW_apb_i2c is acting as a slave-transmitter, this bit is set to 1 if the
+ *               master does not acknowledge a transmitted byte. This occurs on the last byte of
+ *               the transmission, indicating that the transmission is done.
+ *          \arg I2C_INT_TX_ABRT: This bit indicates if DW_apb_i2c, as an I2C transmitter, is unable to complete the
+ *               intended actions on the contents of the transmit FIFO.
+ *          \arg I2C_INT_RD_REQ: This bit is set to 1 when acting as a slave and another I2C master
+ *               is attempting to read data.
+ *          \arg I2C_INT_TX_EMPTY: This bit is set to 1 when the transmit buffer is at or below the threshold value set
+ *               in the IC_TX_TL register.
+ *          \arg I2C_INT_TX_OVER: Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH and
+ *               the processor attempts to issue another I2C command.
+ *          \arg I2C_INT_RX_FULL: Set when the receive buffer reaches or goes above the RX_TL threshold in the
+ *               IC_RX_TL register
+ *          \arg I2C_INT_RX_OVER: Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and an
+ *               additional byte is received from an external I2C device.
+ *          \arg I2C_INT_RX_UNDER: Set if the processor attempts to read the receive buffer when it is empty by reading.
+ * \return  The new state of I2C_IT (SET or RESET).
+ */
+ITStatus I2C_GetINTStatus(I2C_TypeDef *I2Cx, uint32_t I2C_IT)
+{
+    ITStatus bit_status = RESET;
+
+    /* Check the parameters */
+    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+    assert_param(I2C_GET_INT(I2C_IT));
+
+    if ((I2Cx->IC_INTR_STAT & I2C_IT) != (uint32_t)RESET)
+    {
+        bit_status = SET;
+    }
+
+    /* Return the I2C_IT status */
+    return  bit_status;
+}
+
+/**
+ * \brief   Enable or disable the I2Cx GDMA interface.
+ * \param   I2Cx: Select the I2C peripheral. \ref I2C_Declaration
+ * \param   I2C_GDMAReq: Specifies the I2C GDMA transfer request to be enabled or disabled.
+ *          This parameter can be one of the following values:
+ *          \arg I2C_GDMAReq_Tx: Tx buffer GDMA transfer request.
+ *          \arg I2C_GDMAReq_Rx: Rx buffer GDMA transfer request.
+ * \param   NewState: New state of the selected I2C GDMA transfer request.
+ *          This parameter can be: ENABLE or DISABLE.
+ * \return None.
+ */
+void I2C_GDMACmd(I2C_TypeDef *I2Cx, I2CGdmaTransferRequests_TypeDef I2C_GDMAReq,
+                 FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+    assert_param(IS_I2C_GDMAREQ(I2C_GDMAReq));
+
+    if (NewState != DISABLE)
+    {
+        /* Enable the selected I2C GDMA request */
+        I2Cx->IC_DMA_CR |= I2C_GDMAReq;
+    }
+    else
+    {
+        /* Disable the selected I2C GDMA request */
+        I2Cx->IC_DMA_CR &= (uint16_t)~(I2C_GDMAReq);
+    }
+}
+
+/**
+  * \brief  Set Clock Speed through the I2Cx peripheral.
+  * \param  I2Cx: Select the I2C peripheral. \ref I2C_Declaration
+  * \param  I2C_ClockSpeed: CLock speed.
+  * \return None
+  */
+void I2C_SetClockSpeed(I2C_TypeDef *I2Cx, uint32_t I2C_ClockSpeed)
+{
+    uint8_t compensate_index = 0;
+    uint32_t tick_clksrc_ns = 0;
+    uint32_t I2CSrcClk = 0;
+    uint32_t allowedSpeed = 0;
+    uint32_t spklen = 0;
+    uint32_t scl_low_period_spec_min_ns = 0;
+    uint32_t scl_high_period_spec_min_ns = 0;
+    uint32_t scl_lcnt_min = 0;
+    uint32_t scl_hcnt_min = 0;
+    uint32_t scl_low_period_min_ns = 0;
+    uint32_t scl_high_period_min_ns = 0;
+    uint32_t tick_clkspeed_ns = 0;
+    uint32_t total_period_ns = 0;
+    uint32_t total_hcnt_lcnt = 0;
+    int32_t remaining = 0;
+    uint32_t scl_lcnt = 0;
+    uint32_t scl_hcnt = 0;
+
+    /* Obtain the I2C Clock source based on the I2C divider. */
+    compensate_index = I2C_GetCompIndex(I2Cx);
+    if (compensate_index == 6)
+    {
+        I2CSrcClk = 1000000;
+    }
+    else if (compensate_index == 7)
+    {
+        I2CSrcClk = 625000;
+    }
+    else
+    {
+        I2CSrcClk = 40000000 / BIT(compensate_index);
+    }
+
+    /* Tick of I2C clock source in ns. */
+    tick_clksrc_ns = NS_PER_SECOND / I2CSrcClk;
+
+    /* Limit the maximum I2C speed according to the I2C clock source. */
+    if (I2CSrcClk == 40000000)
+    {
+        allowedSpeed = 1000000;
+    }
+    else if (I2CSrcClk == 20000000)
+    {
+        allowedSpeed = 400000;
+    }
+    else
+    {
+        allowedSpeed = 100000;
+    }
+    /* Set Max I2C Clock speed. */
+    I2C_ClockSpeed = (I2C_ClockSpeed > allowedSpeed) ? allowedSpeed : I2C_ClockSpeed;
+
+    /* Set the spike time according to SPEC */
+    /* For Standard mode, there is no limit on spike suppression time, use default value. */
+    if (I2C_ClockSpeed <= 100000)
+    {
+        spklen = 0x05;
+    }
+    /* For Fast mode (plus), the max spike suppression time is 50ns. */
+    else
+    {
+        spklen = 0x01;
+    }
+
+    /* Set suppression limit */
+    I2Cx->IC_FS_SPKLEN = spklen & 0xFFFF;
+
+
+    /******************* Calulate the SCL low high count based on SPEC *******************/
+    /* Get the minimum of scl low high period specified in the spec */
+    if (I2C_ClockSpeed <= 100000)
+    {
+        scl_low_period_spec_min_ns = I2C_STANDARD_MODE_SCL_LOW_PERIOD_MIN_NS;
+        scl_high_period_spec_min_ns = I2C_STANDARD_MODE_SCL_HIGH_PERIOD_MIN_NS;
+    }
+    else if (I2C_ClockSpeed <= 400000)
+    {
+        scl_low_period_spec_min_ns = I2C_FAST_MODE_SCL_LOW_PERIOD_MIN_NS;
+        scl_high_period_spec_min_ns = I2C_FAST_MODE_SCL_HIGH_PERIOD_MIN_NS;
+    }
+    else
+    {
+        scl_low_period_spec_min_ns = I2C_FAST_MODE_PLUS_SCL_LOW_PERIOD_MIN_NS;
+        scl_high_period_spec_min_ns = I2C_FAST_MODE_PLUS_SCL_HIGH_PERIOD_MIN_NS;
+    }
+
+    /* Calulate the minimum of scl low high period based on LCNT/HCNT specified in hardware:
+     *
+     * Firstly, get the minimum LCNT HCNT specified in hardware.
+     * - LCNT: IC_SS_SCL_LCNT and IC_FS_SCL_LCNT register values must be larger than IC_FS_SPKLEN + 7.
+     * - HCNT: IC_SS_SCL_HCNT and IC_FS_SCL_HCNT register values must be larger than IC_FS_SPKLEN + 5.
+     * Use +1 to enforce strictly greater with integer registers.
+     *
+     * Secondly, calulate the minimum of scl high/low period based on the LCNT/HCNT.
+     */
+
+    scl_lcnt_min = spklen + 7 + 1;
+    scl_hcnt_min = spklen + 5 + 1;
+    scl_low_period_min_ns = (scl_lcnt_min + I2C_SCL_LOW_PERIOD_COMPENSATE) * tick_clksrc_ns;
+    scl_high_period_min_ns = (scl_hcnt_min + spklen + I2C_SCL_HIGH_PERIOD_COMPENSATE) *
+                             tick_clksrc_ns;
+
+    /* Final minimum: satisfy both spec and hardware. */
+    scl_low_period_min_ns = (scl_low_period_min_ns > scl_low_period_spec_min_ns) ?
+                            scl_low_period_min_ns : scl_low_period_spec_min_ns;
+    scl_high_period_min_ns = (scl_high_period_min_ns > scl_high_period_spec_min_ns) ?
+                             scl_high_period_min_ns : scl_high_period_spec_min_ns;
+
+    scl_lcnt_min = ROUNDUP(scl_low_period_min_ns, tick_clksrc_ns) - I2C_SCL_LOW_PERIOD_COMPENSATE;
+    scl_hcnt_min = ROUNDUP(scl_high_period_min_ns,
+                           tick_clksrc_ns) - spklen - I2C_SCL_HIGH_PERIOD_COMPENSATE;
+
+    /*************** Calulate the SCL low high count based on I2C_Clock_Speed ***************/
+
+    /* Calculate target total (high+low) counter based on the desired frequency of I2C SCL.
+     * Firstly, calulate the total period: tick_clkspeed_ns minus I2C_RisingTimeNs.
+     *   - Notes: I2C_RisingTimeNs should be below the range.
+     * Secondly, total_period_ns div tick_clksrc_ns, round up.
+     * Then subtract SPKLEN and path compensations to get pure HCNT+LCNT sum.
+     */
+
+    tick_clkspeed_ns = NS_PER_SECOND / I2C_ClockSpeed;
+    total_period_ns = tick_clkspeed_ns - I2C_RisingTimeNs;
+    total_hcnt_lcnt = (ROUNDUP(total_period_ns, tick_clksrc_ns)
+                       - spklen - I2C_SCL_HIGH_PERIOD_COMPENSATE - I2C_SCL_LOW_PERIOD_COMPENSATE);
+
+    /***************** Distibute the remaining count to the SCL low high *****************/
+
+    /* Calculate the remaining as total_hcnt_lcnt - (scl_lcnt_min + scl_hcnt_min),
+     * distribute the remaining counts between low and high count.
+     */
+
+    remaining = total_hcnt_lcnt - scl_lcnt_min - scl_hcnt_min;
+    scl_lcnt = scl_lcnt_min;
+    scl_hcnt = scl_hcnt_min;
+    if (remaining > 0)
+    {
+        scl_lcnt = scl_lcnt_min + (uint32_t)(remaining / 2);
+        scl_hcnt = total_hcnt_lcnt - scl_lcnt;
+    }
+
+    /* Set speed mode and write counters to responsing registers */
+    IC_CON_TypeDef i2c_ctrl = {.d32 = I2Cx->IC_CON};
+    if (I2C_ClockSpeed <= 100000)
+    {
+        /*Configure I2C speed in standard mode*/
+        i2c_ctrl.b.speed = 0x1;
+        I2Cx->IC_CON = i2c_ctrl.d32;
+        I2Cx->IC_SS_SCL_LCNT = scl_lcnt & 0xFFFF;
+        I2Cx->IC_SS_SCL_HCNT = scl_hcnt & 0xFFFF;
+    }
+    else
+    {
+        /* Configure I2C speed in fast mode or fast mode plus*/
+        i2c_ctrl.b.speed = 0x2;
+        I2Cx->IC_CON = i2c_ctrl.d32;
+        I2Cx->IC_FS_SCL_LCNT = scl_lcnt & 0xFFFF;
+        I2Cx->IC_FS_SCL_HCNT = scl_hcnt & 0xFFFF;
+    }
+}
+
+#if (I2C_SUPPORT_RAP_FUNCTION == 1)
+
+void I2C_WrapperModeCmd(I2C_TypeDef *I2Cx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+    WRAP_CR_TypeDef i2c_0x10c = {.d32 = I2Cx->WRAP_CR};
+    i2c_0x10c.b.wrapper_clk_en = NewState;
+    I2Cx->WRAP_CR = i2c_0x10c.d32;
+}
+
+bool I2C_WrapperTransModeSet(I2C_TypeDef *I2Cx, uint32_t mode)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+    WRAP_CR_TypeDef i2c_0x10c = {.d32 = I2Cx->WRAP_CR};
+    i2c_0x10c.b.trans_mode = mode;
+    I2Cx->WRAP_CR = i2c_0x10c.d32;
+    return i2c_0x10c.b.wrapper_busy;
+}
+
+void I2C_WrapperWriteDataSet(I2C_TypeDef *I2Cx, uint8_t num, const uint8_t *buf)
+{
+    /* num should be less than 24 */
+    /* Check the parameters */
+    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+    I2Cx->RAP_WCMD_NUM = num - 1;
+
+    for (uint8_t i = 0; i < num; i++)
+    {
+        I2Cx->RAP_WCMD_DATA = *buf++;
+    }
+}
+
+uint8_t I2C_WrapperGetTxFIFOLen(I2C_TypeDef *I2Cx)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+    RAP_BUF_CR_TypeDef i2c_0x114 = {.d32 = I2Cx->RAP_BUF_CR};
+    return i2c_0x114.b.wrap_buf_amount;
+}
+
+void I2C_WrapperTxFIFOClear(I2C_TypeDef *I2Cx)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+    RAP_BUF_CR_TypeDef i2c_0x114 = {.d32 = I2Cx->RAP_BUF_CR};
+    i2c_0x114.b.wrap_buf_clear = 1;
+    I2Cx->RAP_BUF_CR = i2c_0x114.d32;
+}
+
+
+void I2C_WrapperReadNumSet(I2C_TypeDef *I2Cx, uint16_t num)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+    I2Cx->RAP_RCMD_NUM = num - 1;
+}
+
+
+uint8_t I2C_WrapperReceiveData(I2C_TypeDef *I2Cx)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+    /* Return the data in the DR register */
+    return I2C_ReceiveData(I2Cx);
+}
+
+uint8_t I2C_WrapperGetRxFIFOLen(I2C_TypeDef *I2Cx)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+    return I2C_GetRxFIFOLen(I2Cx);
+}
+
+
+void I2C_WrapperTransStart(I2C_TypeDef *I2Cx)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+    WRAP_CR_TypeDef i2c_0x10c = {.d32 = I2Cx->WRAP_CR};
+    i2c_0x10c.b.start_wrapper = 1;
+    I2Cx->WRAP_CR = i2c_0x10c.d32;
+}
+
+bool I2C_WrapperBusyCheck(I2C_TypeDef *I2Cx)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+    WRAP_CR_TypeDef i2c_0x10c = {.d32 = I2Cx->WRAP_CR};
+    return i2c_0x10c.b.wrapper_busy;
+}
+
+void I2C_RAPModeCmd(I2C_TypeDef *I2Cx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+    WRAP_CR_TypeDef i2c_0x10c = {.d32 = I2Cx->WRAP_CR};
+    i2c_0x10c.b.rap_mode = NewState;
+    I2Cx->WRAP_CR = i2c_0x10c.d32;
+}
+
+void I2C_TaskTrigger(I2C_TypeDef *I2Cx, uint32_t Task)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+    I2Cx->RAP_TASK |= BIT(Task);
+}
+
+#endif
diff --git a/bee/drivers/i2c/src/device/rtl87x2g/rtl_i2c.h b/bee/drivers/i2c/src/device/rtl87x2g/rtl_i2c.h
new file mode 100644
index 00000000..97cf738a
--- /dev/null
+++ b/bee/drivers/i2c/src/device/rtl87x2g/rtl_i2c.h
@@ -0,0 +1,1043 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *               Define to prevent recursive inclusion
+ *============================================================================*/
+#ifndef RTL_I2C_H
+#define RTL_I2C_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*============================================================================*
+ *                        Header Files
+ *============================================================================*/
+#include "utils/rtl_utils.h"
+#include "rtl_i2c_def.h"
+
+/** \defgroup I2C         I2C
+  * \brief
+  * \{
+  */
+
+/*============================================================================*
+ *                         Constants
+ *============================================================================*/
+/** \defgroup I2C_Exported_Constants I2C Exported Constants
+  * \brief
+  * \{
+  */
+
+/**
+ * \defgroup    I2C_Clock_Speed I2C Clock Speed
+ * \{
+ * \ingroup     I2C_Exported_Constants
+ */
+#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) >= 0x01) && ((SPEED) <= I2C_CLOCK_MAX_SPEED)) //!< Specify the maximum clock speed.
+
+/** End of I2C_Clock_Speed
+  * \}
+  */
+
+/**
+ * \defgroup    I2C_Device_Mode I2C Device Mode
+ * \{
+ * \ingroup     I2C_Exported_Constants
+ */
+typedef enum
+{
+    I2C_DeviveMode_Slave = 0x00,        //!< I2C slave device.
+    I2C_DeviveMode_Master = 0x01,       //!< I2C master device.
+} I2CDeviceMode_TypeDef;
+
+#define IS_I2C_DEVICE_MODE(MODE) (((MODE) == I2C_DeviveMode_Slave) || ((MODE) == I2C_DeviveMode_Master)) //!< Check if the input parameter is valid.
+
+/** End of I2C_Device_Mode
+  * \}
+  */
+
+/**
+ * \defgroup    I2C_Address_Mode I2C Address Mode
+ * \{
+ * \ingroup     I2C_Exported_Constants
+ */
+typedef enum
+{
+    I2C_AddressMode_7BIT = 0x00,        //!< I2C 7-bit address mode.
+    I2C_AddressMode_10BIT = 0x01,       //!< I2C 10-bit address mode.
+} I2CAddressMode_TypeDef;
+
+#define IS_I2C_ADDRESS_MODE(ADDR) (((ADDR) == I2C_AddressMode_7BIT) || ((ADDR) == I2C_AddressMode_10BIT)) //!< Check if the input parameter is valid.
+
+/** End of I2C_Address_Mode
+  * \}
+  */
+
+/**
+ * \defgroup    I2C_Send_Command I2C Send Command
+ * \{
+ * \ingroup     I2C_Exported_Constants
+ */
+typedef enum
+{
+    I2C_WRITE_CMD = 0x00,       //!< Data write command.
+    I2C_READ_CMD = 0x01,        //!< Data read command.
+} I2CSendCommend_TypeDef;
+
+#define IS_I2C_CMD(CMD) (((CMD) == I2C_WRITE_CMD) || ((CMD) == I2C_READ_CMD)) //!< Check if the input parameter is valid.
+
+/** End of I2C_Send_Command
+  * \}
+  */
+
+/**
+ * \defgroup    I2C_GDMA_Transfer_Requests I2C GDMA Transfer Requests
+ * \{
+ * \ingroup     I2C_Exported_Constants
+ */
+typedef enum
+{
+    I2C_GDMAReq_Rx = 0x01,      //!< GDMA transfer receiving request.
+    I2C_GDMAReq_Tx = 0x02,      //!< GDMA transfer sending request.
+} I2CGdmaTransferRequests_TypeDef;
+
+#define IS_I2C_GDMAREQ(GDMAREQ) (((GDMAREQ) == I2C_GDMAReq_Rx) || ((GDMAREQ) == I2C_GDMAReq_Tx)) //!< Check if the input parameter is valid.
+
+/** End of I2C_GDMA_Transfer_Requests
+  * \}
+  */
+
+/**
+ * \defgroup    I2C_Status I2C Status
+ * \{
+ * \ingroup     I2C_Exported_Constants
+ */
+typedef enum
+{
+    I2C_Success,                    //!< I2C transfer success.
+    I2C_ARB_LOST,                   //!< Master has lost arbitration or the slave transmitter has lost arbitration.
+    I2C_ABRT_MASTER_DIS,            //!< User tries to initiate a Master operation with the Master mode disabled.
+    I2C_ABRT_TXDATA_NOACK,          //!< Master sent data byte(s) following the address, it did not receive an acknowledge from the remote slave. Only for Master.
+    I2C_ABRT_10ADDR2_NOACK,         //!< Master is in 10-bit address mode and the second address byte of the 10-bit address was not acknowledged by any slave.
+    I2C_ABRT_10ADDR1_NOACK,         //!< Master is in 10-bit address mode and the first 10-bit address byte was not acknowledged by any slave.
+    I2C_ABRT_7B_ADDR_NOACK,         //!< Master is in 7-bit addressing mode and the address sent was not acknowledged by any slave.
+    I2C_ERR_TIMEOUT                 //!< I2C transfer time out error.
+} I2C_Status;
+
+/** End of I2C_Status
+  * \}
+  */
+
+/**
+ * \defgroup    I2C_Interrupts I2C Interrupts
+ * \{
+ * \ingroup     I2C_Exported_Constants
+ */
+
+#define I2C_INT_MST_ON_HOLD                     BIT13           //!< When Master TX FIFO is empty and no stop bit command is issued, master will hold the SCL low.
+#define I2C_INT_GEN_CALL                        BIT11           //!< Set only when a General Call address is received and it is acknowledged.
+#define I2C_INT_START_DET                       BIT10           //!< Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether I2C is operating in slave or master mode.
+#define I2C_INT_STOP_DET                        BIT9            //!< Indicates whether a STOP condition has occurred on the I2C interface regardless of whether I2C is operating in slave or master mode.
+#define I2C_INT_ACTIVITY                        BIT8            //!< This bit captures I2C activity and stays set until it is cleared.          
+#define I2C_INT_RX_DONE                         BIT7            //!< When the I2C is acting as a slave-transmitter, this bit is set to 1 if the master does not acknowledge a transmitted byte. This occurs on the last byte of the transmission, indicating that the transmission is done.
+#define I2C_INT_TX_ABRT                         BIT6            //!< This bit indicates if I2C as an I2C transmitter, is unable to complete the intended actions on the contents of the transmit FIFO.
+#define I2C_INT_RD_REQ                          BIT5            //!< This bit is set to 1 when acting as a slave and another I2C master is attempting to read data.
+#define I2C_INT_TX_EMPTY                        BIT4            //!< This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register.
+#define I2C_INT_TX_OVER                         BIT3            //!< Set during transmit if the transmit buffer is filled to TX FIFO depth and the processor attempts to issue another I2C command.
+#define I2C_INT_RX_FULL                         BIT2            //!< Set when the receive buffer reaches or goes above the RX_TL threshold in the IC_RX_TL register.
+#define I2C_INT_RX_OVER                         BIT1            //!< Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and an additional byte is received from an external I2C device.
+#define I2C_INT_RX_UNDER                        BIT0            //!< Set if the processor attempts to read the receive buffer when it is empty by reading.
+
+#define I2C_GET_INT(INT)    (((INT) == I2C_INT_GEN_CALL) || ((INT) == I2C_INT_START_DET) || \
+                             ((INT) == I2C_INT_STOP_DET) || ((INT) == I2C_INT_ACTIVITY) || \
+                             ((INT) == I2C_INT_RX_DONE)  || ((INT) == I2C_INT_TX_ABRT) || \
+                             ((INT) == I2C_INT_RD_REQ)   || ((INT) == I2C_INT_TX_EMPTY) || \
+                             ((INT) == I2C_INT_TX_OVER)  || ((INT) == I2C_INT_RX_FULL) || \
+                             ((INT) == I2C_INT_RX_OVER)  || ((INT) == I2C_INT_RX_UNDER) || ((INT) == I2C_INT_MST_ON_HOLD)) //!< Check if the input parameter is valid.
+
+/** End of I2C_Interrupts
+  * \}
+  */
+
+/**
+ * \defgroup    I2C_Flags I2C Flags
+ * \{
+ * \ingroup     I2C_Exported_Constants
+ */
+
+#define I2C_FLAG_SLV_HOLD_RX_FIFO_FULL          BIT10           //!< The BUS hold in Slave mode due to the RX FIFO being full and an additional byte being received.
+#define I2C_FLAG_SLV_HOLD_TX_FIFO_EMPTY         BIT9            //!< The BUS hold in Slave mode for the read request when the TX FIFO is empty.
+#define I2C_FLAG_MST_HOLD_RX_FIFO_FULL          BIT8            //!< The BUS hold in Master mode due to Rx FIFO is full and additional byte has been received.
+#define I2C_FLAG_MST_HOLD_TX_FIFO_EMPTY         BIT7            //!< The BUS hold when the master holds the bus because of the TX FIFO being empty.
+#define I2C_FLAG_SLV_ACTIVITY                   BIT6            //!< Slave FSM activity status.
+#define I2C_FLAG_MST_ACTIVITY                   BIT5            //!< Master FSM activity status.
+#define I2C_FLAG_RFF                            BIT4            //!< Receive FIFO completely full.
+#define I2C_FLAG_RFNE                           BIT3            //!< Receive FIFO not empty.
+#define I2C_FLAG_TFE                            BIT2            //!< Transmit FIFO completely empty.
+#define I2C_FLAG_TFNF                           BIT1            //!< Transmit FIFO not full.
+#define I2C_FLAG_ACTIVITY                       BIT0            //!< I2C activity status.
+
+#define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_SLV_HOLD_RX_FIFO_FULL) || ((FLAG) == I2C_FLAG_SLV_HOLD_TX_FIFO_EMPTY) || \
+                               ((FLAG) == I2C_FLAG_MST_HOLD_RX_FIFO_FULL) || ((FLAG) == I2C_FLAG_MST_HOLD_TX_FIFO_EMPTY) || \
+                               ((FLAG) == I2C_FLAG_SLV_ACTIVITY) || ((FLAG) == I2C_FLAG_MST_ACTIVITY) || \
+                               ((FLAG) == I2C_FLAG_RFF) || ((FLAG) == I2C_FLAG_RFNE) || \
+                               ((FLAG) == I2C_FLAG_TFE) || ((FLAG) == I2C_FLAG_TFNF) || \
+                               ((FLAG) == I2C_FLAG_ACTIVITY)) //!< Check if the input parameter is valid.
+
+/** End of I2C_Flags
+  * \}
+  */
+
+/**
+ * \defgroup    I2C_Transmit_Abort_Source I2C Transmit Abort Source
+ * \{
+ * \ingroup     I2C_Exported_Constants
+ */
+
+#define ABRT_SLVRD_INTX                         BIT15           //!< When the processor side responds to a slave mode request for data to be transmitted to a remote master and user send read command.
+#define ABRT_SLV_ARBLOST                        BIT14           //!< Slave lost the bus while transmitting data to a remote master.
+#define ABRT_SLVFLUSH_TXFIFO                    BIT13           //!< Slave has received a read command and some data exists in the TX FIFO so the slave issues a TX_ABRT interrupt to flush old data in TX FIFO.
+#define ARB_LOST                                BIT12           //!< Master has lost arbitration or the slave transmitter has lost arbitration.
+#define ABRT_MASTER_DIS                         BIT11           //!< User tries to initiate a Master operation with the Master mode disabled
+#define ABRT_10B_RD_NORSTRT                     BIT10           //!< The restart is disabled and the master sends a read command in 10-bit addressing mode.
+#define ABRT_SBYTE_NORSTRT                      BIT9            //!< The restart is disabled and the user is trying to send a START byte.
+#define ABRT_HS_NORSTRT                         BIT8            //!< The restart is disabled and the user is trying to use the master to transfer data in high speed mode.
+#define ABRT_SBYTE_ACKDET                       BIT7            //!< Master has sent a START Byte and the START Byte was acknowledged (wrong behavior).
+#define ABRT_HS_ACKDET                          BIT6            //!< Master is in High Speed mode and the High Speed Master code was acknowledged (wrong behavior).
+#define ABRT_GCALL_READ                         BIT5            //!< Sent a General Call but the user programmed the byte following the General Call to be a read from the bus.
+#define ABRT_GCALL_NOACK                        BIT4            //!< Sent a General Call and no slave on the bus acknowledged the General Call.
+#define ABRT_TXDATA_NOACK                       BIT3            //!< Master sent data byte(s) following the address, it did not receive an acknowledge from the remote slave.
+#define ABRT_10ADDR2_NOACK                      BIT2            //!< Master is in 10-bit address mode and the second address byte of the 10-bit address was not acknowledged by any slave.
+#define ABRT_10ADDR1_NOACK                      BIT1            //!< Master is in 10-bit address mode and the first 10-bit address byte was not acknowledged by any slave.
+#define ABRT_7B_ADDR_NOACK                      BIT0            //!< Master is in 7-bit addressing mode and th address sent was not acknowledged by any slave.
+
+#define MS_ALL_ABORT                            (ARB_LOST | ABRT_MASTER_DIS | ABRT_TXDATA_NOACK |\
+                                                 ABRT_10ADDR2_NOACK | ABRT_10ADDR1_NOACK | ABRT_7B_ADDR_NOACK) //!< All types of ABORT.
+
+#define IS_I2C_EVENT(EVENT) (((EVENT) == ABRT_SLVRD_INTX) || \
+                             ((EVENT) == ABRT_SLV_ARBLOST) || \
+                             ((EVENT) == ABRT_SLVFLUSH_TXFIFO) || \
+                             ((EVENT) == ARB_LOST) || \
+                             ((EVENT) == ABRT_MASTER_DIS) || \
+                             ((EVENT) == ABRT_10B_RD_NORSTRT) || \
+                             ((EVENT) == ABRT_SBYTE_NORSTRT) || \
+                             ((EVENT) == ABRT_HS_NORSTRT) || \
+                             ((EVENT) == ABRT_SBYTE_ACKDET) || \
+                             ((EVENT) == ABRT_HS_ACKDET) || \
+                             ((EVENT) == ABRT_GCALL_READ) || \
+                             ((EVENT) == ABRT_GCALL_NOACK) || \
+                             ((EVENT) == ABRT_TXDATA_NOACK) || \
+                             ((EVENT) == ABRT_10ADDR2_NOACK) || \
+                             ((EVENT) == ABRT_10ADDR1_NOACK) || \
+                             ((EVENT) == ABRT_7B_ADDR_NOACK)) //!< Check if the input parameter is valid.
+
+/** End of I2C_Transmit_Abort_Source
+  * \}
+  */
+
+/**
+ * \defgroup    I2C_Immediate_Number I2C Immediate Number
+ * \{
+ * \ingroup     I2C_Exported_Constants
+ */
+
+#define I2C_0X10_CMD         BIT8           //!< If the data is ORed with this immediate value, it indicates a master device read command.
+#define I2C_0X10_STOP        BIT9           //!< If the data is ORed with this immediate value, it indicates sending a stop bit.
+
+/** End of I2C_Immediate_Number
+  * \}
+  */
+
+#if (I2C_SUPPORT_RAP_FUNCTION == 1)
+/**
+ * \defgroup    I2C_Wrapper_Trans_Mode I2C Wrapper Trans Mode
+ * \{
+ * \ingroup     I2C_Exported_Constants
+ */
+
+typedef enum
+{
+    I2C_WRAPPER_TRANS_MODE_WRITE       = 0,
+    I2C_WRAPPER_TRANS_MODE_READ        = 1,
+    I2C_WRAPPER_TRANS_MODE_REPEAT_READ = 2,
+    I2C_WRAPPER_TRANS_MODE_DMA         = 3,
+} I2CWrapperTransMode_TypeDef;
+
+/** End of I2C_Wrapper_Trans_Mode
+  * \}
+  */
+
+/**
+ * \defgroup    I2C_Task I2C Task Number
+ * \{
+ * \ingroup     I2C_Exported_Constants
+ */
+
+typedef enum
+{
+    I2C_TASK_START = 0,
+} I2CTask_TypeDef;
+
+/** End of I2C_Task
+  * \}
+  */
+
+#endif
+
+/** End of I2C_Exported_Constants
+  * \}
+  */
+
+/*============================================================================*
+ *                         Types
+ *============================================================================*/
+/** \defgroup I2C_Exported_Types I2C Exported Types
+  * \brief
+  * \{
+  */
+
+/**
+ * \brief       I2C Init structure definition.
+ *
+ * \ingroup     I2C_Exported_Types
+ */
+
+typedef struct
+{
+    uint32_t I2C_Clock;                    /*!< Specify source clock frequency, default 40000000.
+                                                This parameter must be set with I2C clock div. */
+
+    uint32_t I2C_ClockSpeed;               /*!< Specify SCK speed on the I2C bus.
+                                                This parameter must be set to a value lower than 1MHz. */
+
+    I2CDeviceMode_TypeDef I2C_DeviveMode;  /*!< Specify the I2C devie mode.
+                                                This parameter can be a value of \ref I2C_Device_Mode. */
+
+    I2CAddressMode_TypeDef I2C_AddressMode;/*!< Specify the I2C address mode.
+                                                This parameter can be a value of \ref I2C_Address_Mode. */
+
+    uint16_t I2C_SlaveAddress;             /*!< Specify the first device own address.
+                                                This parameter can be a 7-bit or 10-bit address. */
+
+    FunctionalState
+    I2C_Ack;               /*!< Enable or disable the acknowledgement only in slave mode.
+                                                This parameter can be a value of ENABLE or DISABLE. */
+
+    uint32_t I2C_TxThresholdLevel;         /*!< Specify the transmit FIFO Threshold to trigger interrupt I2C_INT_TX_EMPTY.
+                                                This parameter can be a value less than I2C_TX_FIFO_SIZE.*/
+
+    uint32_t I2C_RxThresholdLevel;         /*!< Specify the receive FIFO Threshold to trigger interrupt I2C_INT_RX_FULL.
+                                                This parameter can be a value less than I2C_RX_FIFO_SIZE.*/
+
+    FunctionalState I2C_TxDmaEn;           /*!< Specify the Tx dma mode.
+                                                This parameter can be a value of ENABLE or DISABLE. */
+
+    FunctionalState I2C_RxDmaEn;           /*!< Specify the Rx dma mode.
+                                                This parameter can be a value of ENABLE or DISABLE. */
+
+    uint8_t  I2C_TxWaterlevel;             /*!< Specify the DMA tx water level.
+                                                The best value is I2C Tx fifo depth - Tx GDMA MSize. */
+
+    uint8_t  I2C_RxWaterlevel;             /*!< Specify the DMA rx water level.
+                                                The best value is I2C Rx GDMA MSize. */
+
+    uint8_t  I2C_RisingTimeNs;             /*!< Specify the I2C SDA/SCL rising time.
+                                                The unit is ns and must be an integer multiple of clock src period. */
+
+} I2C_InitTypeDef;
+
+/** End of GPIO_Exported_Types
+  * \}
+  */
+
+/*============================================================================*
+ *                         Functions
+ *============================================================================*/
+/** \defgroup I2C_Exported_Functions I2C Exported Functions
+  * \brief
+  * \{
+  */
+
+/**
+ * \brief   Deinitialize the I2Cx peripheral registers to their default reset values.
+ *
+ * \param[in] I2Cx  Select the I2C peripheral. Refer to \ref I2C_Declaration.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_i2c0_init(void)
+ * {
+ *     I2C_DeInit(I2C0);
+ * }
+ * \endcode
+ */
+void I2C_DeInit(I2C_TypeDef *I2Cx);
+
+/**
+ * \brief   Initialize the I2Cx peripheral according to the specified parameters in the I2C_InitStruct.
+ *
+ * \param[in] I2Cx            Select the I2C peripheral. Refer to \ref I2C_Declaration.
+ * \param[in] I2C_InitStruct  Pointer to a I2C_InitTypeDef structure which will be initialized.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_i2c0_init(void)
+ * {
+ *     RCC_PeriphClockCmd(APBPeriph_I2C0, APBPeriph_I2C0_CLOCK, ENABLE);
+ *
+ *     I2C_InitTypeDef  I2C_InitStruct;
+ *     I2C_StructInit(&I2C_InitStruct);
+ *
+ *     I2C_InitStruct.I2C_ClockSpeed    = 100000;
+ *     I2C_InitStruct.I2C_DeviveMode    = I2C_DeviveMode_Master;
+ *     I2C_InitStruct.I2C_AddressMode   = I2C_AddressMode_7BIT;
+ *     I2C_InitStruct.I2C_SlaveAddress  = STK8321_ADDRESS;
+ *     I2C_InitStruct.I2C_Ack           = I2C_Ack_Enable;
+ *
+ *     I2C_Init(I2C0, &I2C_InitStruct);
+ *     I2C_Cmd(I2C0, ENABLE);
+ * }
+ * \endcode
+ */
+void I2C_Init(I2C_TypeDef *I2Cx, I2C_InitTypeDef *I2C_InitStruct);
+
+/**
+ * \brief  Enable or disable the specified I2C peripheral.
+ *
+ * \param[in] I2Cx      Select the I2C peripheral. Refer to \ref I2C_Declaration.
+ * \param[in] NewState  New state of the I2Cx peripheral.
+ *                      This parameter can be one of the following values:
+ *                      - ENABLE: Enable the specified I2C peripheral.
+ *                      - DISABLE: Disable the specified I2C peripheral.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_i2c0_init(void)
+ * {
+ *     RCC_PeriphClockCmd(APBPeriph_I2C0, APBPeriph_I2C0_CLOCK, ENABLE);
+ *
+ *     I2C_InitTypeDef  I2C_InitStruct;
+ *     I2C_StructInit(&I2C_InitStruct);
+ *
+ *     I2C_InitStruct.I2C_ClockSpeed    = 100000;
+ *     I2C_InitStruct.I2C_DeviveMode    = I2C_DeviveMode_Master;
+ *     I2C_InitStruct.I2C_AddressMode   = I2C_AddressMode_7BIT;
+ *     I2C_InitStruct.I2C_SlaveAddress  = STK8321_ADDRESS;
+ *     I2C_InitStruct.I2C_Ack           = I2C_Ack_Enable;
+ *
+ *     I2C_Init(I2C0, &I2C_InitStruct);
+ *     I2C_Cmd(I2C0, ENABLE);
+ * }
+ * \endcode
+ */
+void I2C_Cmd(I2C_TypeDef *I2Cx, FunctionalState NewState);
+
+/**
+ * \brief  Enable or disable the specified I2C peripheral.
+ *
+ * \param[in] I2Cx  Select the I2C peripheral. Refer to \ref I2C_Declaration.
+ *
+ * \return The status of I2Cx. Refer to \ref I2C_Status.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void i2c0_demo(void)
+ * {
+ *     I2C_CheckAbortStatus(I2C0);
+ * }
+ * \endcode
+ */
+I2C_Status I2C_CheckAbortStatus(I2C_TypeDef *I2Cx);
+
+/**
+ * \brief   Fill each I2C_InitStruct member with its default value.
+ *
+ * \note   The default settings for the I2C_InitStruct member are shown in the following table:
+ *         | I2C_InitStruct member | Default value                    |
+ *         |:---------------------:|:--------------------------------:|
+ *         | I2C_Clock             | 40000000                         |
+ *         | I2C_ClockSpeed        | 400000                           |
+ *         | I2C_DeviveMode        | \ref I2C_DeviveMode_Master       |
+ *         | I2C_AddressMode       | \ref I2C_AddressMode_7BIT        |
+ *         | I2C_SlaveAddress      | 0                                |
+ *         | I2C_Ack               | ENABLE                           |
+ *         | I2C_TxThresholdLevel  | 0                                |
+ *         | I2C_RxThresholdLevel  | 0                                |
+ *         | I2C_TxDmaEn           | DISABLE                          |
+ *         | I2C_RxDmaEn           | DISABLE                          |
+ *         | I2C_TxWaterlevel      | 23                               |
+ *         | I2C_RxWaterlevel      | 1                                |
+ *         | I2C_RisingTimeNs      | 50                               |
+ *
+ * \param[in] I2C_InitStruct  Pointer to a I2C_InitTypeDef structure which will be initialized.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_i2c0_init(void)
+ * {
+ *     RCC_PeriphClockCmd(APBPeriph_I2C0, APBPeriph_I2C0_CLOCK, ENABLE);
+ *
+ *     I2C_InitTypeDef  I2C_InitStruct;
+ *     I2C_StructInit(&I2C_InitStruct);
+ *
+ *     I2C_InitStruct.I2C_ClockSpeed    = 100000;
+ *     I2C_InitStruct.I2C_DeviveMode    = I2C_DeviveMode_Master;
+ *     I2C_InitStruct.I2C_AddressMode   = I2C_AddressMode_7BIT;
+ *     I2C_InitStruct.I2C_SlaveAddress  = STK8321_ADDRESS;
+ *     I2C_InitStruct.I2C_Ack           = I2C_Ack_Enable;
+ *
+ *     I2C_Init(I2C0, &I2C_InitStruct);
+ *     I2C_Cmd(I2C0, ENABLE);
+ * }
+ * \endcode
+ */
+void I2C_StructInit(I2C_InitTypeDef *I2C_InitStruct);
+
+/**
+ * \brief   Send data in master mode through the I2Cx peripheral.
+ *
+ * \param[in] I2Cx  Select the I2C peripheral. Refer to \ref I2C_Declaration.
+ * \param[in] pBuf  Byte to be transmitted.
+ * \param[in] len   Data length to send.
+ *
+ * \return I2C_Status: The status of I2Cx.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void i2c0_demo(void)
+ * {
+ *     uint8_t data[10] = {0x01,x0x02,0x03,0x04};
+ *     I2C_MasterWrite(I2C0, data, 4);
+ * }
+ * \endcode
+ */
+I2C_Status I2C_MasterWrite(I2C_TypeDef *I2Cx, uint8_t *pBuf, uint16_t len);
+
+/**
+ * \brief   Read data in master mode through the I2Cx peripheral.
+ *
+ * \param[in] I2Cx   Select the I2C peripheral. Refer to \ref I2C_Declaration.
+ * \param[in] pBuf   Byte to be transmitted.
+ * \param[in] len    Data length to send.
+ * \param[in] pBuf2  Byte to be transmitted.
+ * \param[in] len2   Data length to send.
+ *
+ * \return I2C status: The status of I2Cx, refer to \ref I2C_Status.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void i2c0_demo(void)
+ * {
+ *     uint8_t data[10] = {0x01,x0x02,0x03,0x04};
+ *     uint8_t data1[10] = {0x01,x0x02,0x03,0x04};
+ *     I2C_MasterWriteDevice(I2C0, data, 4, data, 4);
+ * }
+ * \endcode
+ */
+I2C_Status I2C_MasterWriteDevice(I2C_TypeDef *I2Cx, uint8_t *pBuf, uint16_t len, uint8_t *pbuf2,
+                                 uint32_t len2);
+
+/**
+ * \brief   Read data in master mode through the I2Cx peripheral.
+ *
+ * \param[in] I2Cx   Select the I2C peripheral. Refer to \ref I2C_Declaration.
+ * \param[out] pBuf  Data buffer to receive data.
+ * \param[in] len    Read data length.
+ *
+ * \return I2C_Status: The status of I2Cx, refer to \ref I2C_Status.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void i2c0_demo(void)
+ * {
+ *     uint8_t data[10] = {0};
+ *     I2C_MasterRead(I2C0, data, 10);
+ * }
+ * \endcode
+ */
+I2C_Status I2C_MasterRead(I2C_TypeDef *I2Cx, uint8_t *pBuf, uint16_t len);
+
+/**
+ * \brief   Sends data and read data in master mode through the I2Cx peripheral.
+ *          Attention:Read data with time out mechanism.
+ *
+ * \param[in] I2Cx       Select the I2C peripheral. Refer to \ref I2C_Declaration.
+ * \param[in] pWriteBuf  Data buffer to send before read.
+ * \param[in] Writelen   Send data length.
+ * \param[out] pReadBuf  Data buffer to receive.
+ * \param[in] Readlen    Receive data length.
+ *
+ * \return I2C_Status: The status of I2Cx, refer to \ref I2C_Status.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void i2c0_demo(void)
+ * {
+ *     uint8_t tx_data[10] = {0x01,x0x02,0x03,0x04};
+ *     uint8_t rx_data[10] = {0};
+ *     I2C_RepeatRead(I2C0, tx_data, 4, rx_data, 10);
+ * }
+ * \endcode
+ */
+I2C_Status I2C_RepeatRead(I2C_TypeDef *I2Cx, uint8_t *pWriteBuf, uint16_t Writelen,
+                          uint8_t *pReadBuf, uint16_t Readlen);
+
+/**
+ * \brief Mask the specified I2C interrupt.
+ *
+ * \param[in] I2Cx      Select the I2C peripheral. Refer to \ref I2C_Declaration.
+ * \param[in] I2C_IT    This parameter can be one of the following values, refer to \ref I2C_Interrupts.
+ *                      \arg I2C_INT_MST_ON_HOLD: Indicates whether a master is holding the bus.
+ *                      \arg I2C_INT_GEN_CALL: Set only when a General Call address is received and it is acknowledged.
+ *                      \arg I2C_INT_START_DET: Indicates whether a START or RESTART condition has occurred on the I2C
+ *                           interface regardless of whether I2C is operating in slave or master mode.
+ *                      \arg I2C_INT_STOP_DET: Indicates whether a STOP condition has occurred on the I2C interface
+ *                           regardless of whether I2C is operating in slave or master mode
+ *                      \arg I2C_INT_ACTIVITY: This bit captures I2C activity and stays set until it is cleared.
+ *                      \arg I2C_INT_RX_DONE: When the I2C is acting as a slave-transmitter, this bit is set to 1 if the
+ *                           master does not acknowledge a transmitted byte. This occurs on the last byte of the
+ *                           transmission, indicating that the transmission is done.
+ *                      \arg I2C_INT_TX_ABRT: This bit indicates if I2C as an I2C transmitter, is unable to complete the
+ *                           intended actions on the contents of the transmit FIFO.
+ *                      \arg I2C_INT_RD_REQ: This bit is set to 1 when acting as a slave and another I2C master is
+ *                           attempting to read data.
+ *                      \arg I2C_INT_TX_EMPTY: This bit is set to 1 when the transmit buffer is at or below the threshold
+ *                            value set in the IC_TX_TL register.
+ *                      \arg I2C_INT_TX_OVER: Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH and
+ *                           the processor attempts to issue another I2C command.
+ *                      \arg I2C_INT_RX_FULL: Set when the receive buffer reaches or goes above the RX_TL threshold in the
+ *                           IC_RX_TL register
+ *                      \arg I2C_INT_RX_OVER: Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and an
+ *                           additional byte is received from an external I2C device.
+ *                      \arg I2C_INT_RX_UNDER: Set if the processor attempts to read the receive buffer when it is empty by reading.
+ * \param[in] NewState  Mask the specified I2C interrupt or not.
+ *                      This parameter can be one of the following values:
+ *                      - ENABLE: Mask the specified I2C interrupt.
+ *                      - DISABLE: Unmask the specified I2C interrupt.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void i2c0_demo(void)
+ * {
+ *     I2C_ClearINTPendingBit(I2C0, I2C_INT_STOP_DET);
+ *     I2C_INTConfig(I2C0, I2C_INT_STOP_DET, ENABLE);
+ *
+ *     NVIC_InitTypeDef NVIC_InitStruct;
+ *     NVIC_InitStruct.NVIC_IRQChannel = I2C0_IRQn;
+ *     NVIC_InitStruct.NVIC_IRQChannelPriority = 3;
+ *     NVIC_InitStruct.NVIC_IRQChannelCmd = ENABLE;
+ *     NVIC_Init(&NVIC_InitStruct);
+ * }
+ * \endcode
+ */
+void I2C_INTConfig(I2C_TypeDef *I2Cx, uint16_t I2C_IT, FunctionalState NewState);
+
+/**
+ * \brief   Clear the specified I2C interrupt pending bit.
+ *
+ * \param[in] I2Cx    Select the I2C peripheral. Refer to \ref I2C_Declaration.
+ * \param[in] I2C_IT  This parameter can be one of the following values, refer to \ref I2C_Interrupts.
+ *                    - I2C_INT_GEN_CALL: Set only when a General Call address is received and it is acknowledged.
+ *                    - I2C_INT_START_DET: Indicates whether a START or RESTART condition has occurred on the I2C
+ *                      interface regardless of whether I2C is operating in slave or master mode.
+ *                    - I2C_INT_STOP_DET: Indicates whether a STOP condition has occurred on the I2C interface regardless
+ *                      of whether I2C is operating in slave or master mode
+ *                    - I2C_INT_ACTIVITY: This bit captures I2C activity and stays set until it is cleared.
+ *                    - I2C_INT_RX_DONE: When the I2C is acting as a slave-transmitter, this bit is set to 1 if the
+ *                      master does not acknowledge a transmitted byte. This occurs on the last byte of the
+ *                      transmission, indicating that the transmission is done.
+ *                    - I2C_INT_TX_ABRT: This bit indicates if I2C as an I2C transmitter, is unable to complete the
+ *                      intended actions on the contents of the transmit FIFO.
+ *                    - I2C_INT_RD_REQ: This bit is set to 1 when acting as a slave and another I2C master is
+ *                      attempting to read data.
+ *                    - I2C_INT_TX_EMPTY: This bit is set to 1 when the transmit buffer is at or below the threshold value set
+ *                      in the IC_TX_TL register.
+ *                    - I2C_INT_TX_OVER: Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH and
+ *                      the processor attempts to issue another I2C command.
+ *                    - I2C_INT_RX_FULL: Set when the receive buffer reaches or goes above the RX_TL threshold in the
+ *                      IC_RX_TL register
+ *                    - I2C_INT_RX_OVER: Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and an
+ *                      additional byte is received from an external I2C device.
+ *                    - I2C_INT_RX_UNDER: Set if the processor attempts to read the receive buffer when it is empty by reading.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void I2C0_Handler(void)
+ * {
+ *     if (I2C_GetINTStatus(I2C0, I2C_INT_STOP_DET) == SET)
+ *     {
+ *         //Add user code here.
+ *         I2C_ClearINTPendingBit(I2C0, I2C_INT_STOP_DET);
+ *     }
+ * }
+ * \endcode
+ */
+void I2C_ClearINTPendingBit(I2C_TypeDef *I2Cx, uint16_t I2C_IT);
+
+/**
+ * \brief   Set slave device address.
+ *
+ * \param[in] I2Cx     Select the I2C peripheral. Refer to \ref I2C_Declaration.
+ * \param[in] Address  Specify the slave address which will be transmitte.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void i2c0_demo(void)
+ * {
+ *     I2C_SetSlaveAddress(I2C0, 0x55);
+ * }
+ * \endcode
+ */
+void I2C_SetSlaveAddress(I2C_TypeDef *I2Cx, uint16_t Address);
+
+/**
+ * \brief   Write command through the I2Cx peripheral.
+ *
+ * \param[in] I2Cx       Select the I2C peripheral. Refer to \ref I2C_Declaration.
+ * \param[in] command    Command of write or read.
+ *                       \arg I2C_READ_CMD: Read command. Data which want to transmit can be 0 in this situation.
+ *                       \arg I2C_WRITE_CMD: Write command.
+ * \param[in] data       Data which to be transmitted.
+ * \param[in] StopState  Whether to send a stop signal.
+ *                       - ENABLE: Send stop signal.
+ *                       - DISABLE: Do not send stop signal.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void i2c0_demo(void)
+ * {
+ *     I2C_SendCmd(I2C0, 0x01, 0xAA, ENABLE);
+ * }
+ * \endcode
+ */
+void I2C_SendCmd(I2C_TypeDef *I2Cx, I2CSendCommend_TypeDef command, uint8_t data,
+                 FunctionalState StopState);
+
+/**
+ * \brief  Received data by the I2Cx peripheral.
+ *
+ * \param[in] I2Cx  Select the I2C peripheral. Refer to \ref I2C_Declaration.
+ *
+ * \return Return the most recent received data.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void i2c0_demo(void)
+ * {
+ *     uint8_t data = I2C_ReceiveData(I2C0);
+ * }
+ * \endcode
+ */
+uint8_t I2C_ReceiveData(I2C_TypeDef *I2Cx);
+
+/**
+ * \brief   Get data length in Rx FIFO of the I2Cx peripheral.
+ *
+ * \param[in] I2Cx  Select the I2C peripheral. Refer to \ref I2C_Declaration.
+ *
+ * \return  Current data number in Rx FIFO.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void i2c0_demo(void)
+ * {
+ *     uint8_t data_len = I2C_GetRxFIFOLen(I2C0);
+ * }
+ * \endcode
+ */
+uint8_t I2C_GetRxFIFOLen(I2C_TypeDef *I2Cx);
+
+/**
+ * \brief   Get data length in Tx FIFO of the I2Cx peripheral.
+ *
+ * \param[in] I2Cx  Select the I2C peripheral. Refer to \ref I2C_Declaration.
+ *
+ * \return  Current data number in Tx FIFO.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void i2c0_demo(void)
+ * {
+ *     uint8_t data_len = I2C_GetTxFIFOLen(I2C0);
+ * }
+ * \endcode
+ */
+uint8_t I2C_GetTxFIFOLen(I2C_TypeDef *I2Cx);
+
+/**
+ * \brief   Clear all I2C interrupt.
+ *
+ * \param[in] I2Cx  Select the I2C peripheral. Refer to \ref I2C_Declaration.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void i2c0_demo(void)
+ * {
+ *     I2C_ClearAllINT(I2C0);
+ * }
+ * \endcode
+ */
+void I2C_ClearAllINT(I2C_TypeDef *I2Cx);
+
+/**
+ * \brief  Get the specified I2C flag status.
+ *
+ * \param[in] I2Cx      Select the I2C peripheral. Refer to \ref I2C_Declaration.
+ * \param[in] I2C_FLAG  Specify the flag to check.
+ *                      This parameter can be one of the following values, refer to \ref I2C_Flags.
+ *                      - I2C_FLAG_SLV_HOLD_RX_FIFO_FULL: The BUS hold in Slave mode due to the RX FIFO being Full and an additional byte being received.
+ *                      - I2C_FLAG_SLV_HOLD_TX_FIFO_EMPTY: The BUS hold in Slave mode for the read request when the TX FIFO is empty.
+ *                      - I2C_FLAG_MST_HOLD_RX_FIFO_FULL: The BUS hold in Master mode due to TX FIFO is full and additional byte has been received.
+ *                      - I2C_FLAG_MST_HOLD_TX_FIFO_EMPTY: The BUS hold when the master holds the bus because of the TX FIFO being empty.
+ *                      - I2C_FLAG_SLV_ACTIVITY: Slave FSM activity status.
+ *                      - I2C_FLAG_MST_ACTIVITY: Master FSM activity status.
+ *                      - I2C_FLAG_RFF: Receive FIFO completely full.
+ *                      - I2C_FLAG_RFNE: Receive FIFO not empty.
+ *                      - I2C_FLAG_TFE: Transmit FIFO completely empty.
+ *                      - I2C_FLAG_TFNF: Transmit FIFO not full.
+ *                      - I2C_FLAG_ACTIVITY: I2C activity status.
+ *
+ * \return  The status of I2C flag.
+ *          - SET: The I2C flag has been set.
+ *          - RESET: The I2C flag has been reset.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void i2c0_demo(void)
+ * {
+ *     FlagStatus flag_status = I2C_GetFlagState(I2C0, I2C_FLAG_RFF);
+ * }
+ * \endcode
+ */
+FlagStatus I2C_GetFlagState(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG);
+
+/**
+ * \brief  Check whether the last I2Cx event is equal to the one passed as parameter.
+ *
+ * \param[in] I2Cx       Select the I2C peripheral. Refer to \ref I2C_Declaration.
+ * \param[in] I2C_EVENT  Specify the event to be checked about I2C Transmit Abort Status Register.
+ *                       This parameter can be one of the following values, refer to \ref I2C_Transmit_Abort_Source.
+ *                       - ABRT_SLVRD_INTX: When the processor side responds to a slave mode request for data to be transmitted to a remote master and user send read command.
+ *                       - ABRT_SLV_ARBLOST: Slave lost the bus while transmitting data to a remote master.
+ *                       - ABRT_SLVFLUSH_TXFIFO: Slave has received a read command and some data exists in the TX FIFO so the slave issues a TX_ABRT interrupt to flush old data in TX FIFO.
+ *                       - ARB_LOST: Master has lost arbitration or the slave transmitter has lost arbitration.
+ *                       - ABRT_MASTER_DIS: User tries to initiate a Master operation with the Master mode disabled
+ *                       - ABRT_10B_RD_NORSTRT: The restart is disabled and the master sends a read command in 10-bit addressing mode.
+ *                       - ABRT_SBYTE_NORSTRT: The restart is disabled and the user is trying to send a START Byte.
+ *                       - ABRT_HS_NORSTRT: The restart is disabled and the user is trying to use the master to transfer data in High Speed mode.
+ *                       - ABRT_SBYTE_ACKDET: Master has sent a START Byte and the START Byte was acknowledged (wrong behavior).
+ *                       - ABRT_HS_ACKDET: Master is in High Speed mode and the High Speed Master code was acknowledged (wrong behavior).
+ *                       - ABRT_GCALL_READ: Sent a General Call but the user programmed the byte following the General Call to be a read from the bus.
+ *                       - ABRT_GCALL_NOACK: Sent a General Call and no slave on the bus acknowledged the General Call.
+ *                       - ABRT_TXDATA_NOACK: Master sent data byte(s) following the address, it did not receive an acknowledge from the remote slave.
+ *                       - ABRT_10ADDR2_NOACK: Master is in 10-bit address mode and the second address byte of the 10-bit address was not acknowledged by any slave.
+ *                       - ABRT_10ADDR1_NOACK: Master is in 10-bit address mode and the first 10-bit address byte was not acknowledged by any slave.
+ *                       - ABRT_7B_ADDR_NOACK: Master is in 7-bit addressing mode and the address sent was not acknowledged by any slave.
+ *
+ * \return  An ErrorStatus enumeration value.
+ *          - SUCCESS: Last event is equal to the I2C_EVENT.
+ *          - ERROR: Last event is different from the I2C_EVENT.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void i2c0_demo(void)
+ * {
+ *     FlagStatus flag_status = I2C_CheckEvent(I2C0, ABRT_SLVRD_INTX);
+ * }
+ * \endcode
+ */
+FlagStatus I2C_CheckEvent(I2C_TypeDef *I2Cx, uint32_t I2C_EVENT);
+
+/**
+ * \brief   Get the specified I2C interrupt status.
+ *
+ * \param[in] I2Cx    Select the I2C peripheral. Refer to \ref I2C_Declaration.
+ * \param[in] I2C_IT  This parameter can be one of the following values, refer to \ref I2C_Interrupts.
+ *                    \arg I2C_INT_MST_ON_HOLD: Indicates whether a master is holding the bus.
+ *                    \arg I2C_INT_GEN_CALL: Set only when a General Call address is received and it is acknowledged.
+ *                    \arg I2C_INT_START_DET: Indicates whether a START or RESTART condition has occurred on the I2C
+ *                         interface regardless of whether DW_apb_i2c is operating in slave or master mode.
+ *                    \arg I2C_INT_STOP_DET: Indicates whether a STOP condition has occurred on the I2C interface regardless
+ *                         of whether DW_apb_i2c is operating in slave or master mode
+ *                    \arg I2C_INT_ACTIVITY: This bit captures DW_apb_i2c activity and stays set until it is cleared.
+ *                    \arg I2C_INT_RX_DONE: When the DW_apb_i2c is acting as a slave-transmitter, this bit is set to 1 if the
+ *                         master does not acknowledge a transmitted byte. This occurs on the last byte of
+ *                         the transmission, indicating that the transmission is done.
+ *                    \arg I2C_INT_TX_ABRT: This bit indicates if DW_apb_i2c, as an I2C transmitter, is unable to complete the
+ *                         intended actions on the contents of the transmit FIFO.
+ *                    \arg I2C_INT_RD_REQ: This bit is set to 1 when acting as a slave and another I2C master
+ *                         is attempting to read data.
+ *                    \arg I2C_INT_TX_EMPTY: This bit is set to 1 when the transmit buffer is at or below the threshold value set
+ *                         in the IC_TX_TL register.
+ *                    \arg I2C_INT_TX_OVER: Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH and
+ *                         the processor attempts to issue another I2C command.
+ *                    \arg I2C_INT_RX_FULL: Set when the receive buffer reaches or goes above the RX_TL threshold in the
+ *                         IC_RX_TL register
+ *                    \arg I2C_INT_RX_OVER: Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and an
+ *                         additional byte is received from an external I2C device.
+ *                    \arg I2C_INT_RX_UNDER: Set if the processor attempts to read the receive buffer when it is empty by reading.
+ *
+ * \return  The status of I2C interrupt.
+ *          - SET: The I2C interrupt has been set.
+ *          - RESET: The I2C interrupt has been reset.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void i2c0_demo(void)
+ * {
+ *     ITStatus int_status = I2C_GetINTStatus(I2C0, I2C_INT_RD_REQ);
+ * }
+ * \endcode
+ */
+ITStatus I2C_GetINTStatus(I2C_TypeDef *I2Cx, uint32_t I2C_IT);
+
+/**
+ * \brief   Enable or disable the I2Cx GDMA interface.
+ *
+ * \param[in] I2Cx         Select the I2C peripheral. Refer to \ref I2C_Declaration.
+ * \param[in] I2C_GDMAReq  Specify the I2C GDMA transfer request to be enabled or disabled.
+ *                         This parameter can be one of the following values:
+ *                         \arg I2C_GDMAReq_Tx: Tx buffer GDMA transfer request.
+ *                         \arg I2C_GDMAReq_Rx: Rx buffer GDMA transfer request.
+ * \param[in] NewState     New state of the selected I2C GDMA transfer request.
+ *                         This parameter can be one of the following values:
+ *                         \arg ENABLE: Enable the I2Cx GDMA interface.
+ *                         \arg DISABLE: Disable the I2Cx GDMA interface.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void i2c0_demo(void)
+ * {
+ *     I2C_GDMACmd(I2C0, I2C_GDMAReq_Tx, ENABLE);
+ * }
+ * \endcode
+ */
+void I2C_GDMACmd(I2C_TypeDef *I2Cx, I2CGdmaTransferRequests_TypeDef I2C_GDMAReq,
+                 FunctionalState NewState);
+
+/**
+ * \brief   Set the I2C clock speed, the function need to be called when I2C disabled.
+ *
+ * \param[in] I2Cx            Select the I2C peripheral. Refer to \ref I2C_Declaration.
+ * \param[in] I2C_ClockSpeed  Specify the I2C clock speed.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void i2c_demo(void)
+ * {
+ *     I2C_SetClockSpeed(I2C0, 400000);
+ * }
+ * \endcode
+ */
+void I2C_SetClockSpeed(I2C_TypeDef *I2Cx, uint32_t I2C_ClockSpeed);
+
+/**
+ * \brief  I2C clock divider config.
+ *
+ * \param[in] I2Cx      Select the I2C peripheral. Refer to \ref I2C_Declaration.
+ * \param[in] ClockDiv  Specify the I2C clock divider.
+ *                      This parameter can refer to \ref I2C_Clock_Divider.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_i2c_init(void)
+ * {
+ *     I2C_ClkDivConfig(I2C0, I2C_CLOCK_DIVIDER_1);
+ * }
+ * \endcode
+ */
+void I2C_ClkDivConfig(I2C_TypeDef *I2Cx, I2CClockDiv_TypeDef ClockDiv);
+
+/**
+ * \brief  Get I2C clock divider.
+ *
+ * \param[in] I2Cx       Select the I2C peripheral. Refer to \ref I2C_Declaration.
+ * \param[out] ClockSrc  Specify the clock source to gates its clock.
+ * \param[out] ClockDiv  Specify the I2C clock divider.
+ *                       This parameter can refer to \ref I2C_Clock_Divider.
+ *
+ * \return The status of get clock.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_i2c_init(void)
+ * {
+ *     I2C_ClkGet(I2C0, I2C_CLOCK_SRC,I2C_CLOCK_DIVIDER_1);
+ * }
+ * \endcode
+ */
+bool I2C_ClkGet(I2C_TypeDef *I2Cx, I2CClockSrc_TypeDef *ClockSrc, I2CClockDiv_TypeDef *ClockDiv);
+
+
+#if (I2C_SUPPORT_RAP_FUNCTION == 1)
+void I2C_WrapperModeCmd(I2C_TypeDef *I2Cx, FunctionalState NewState);
+
+bool I2C_WrapperTransModeSet(I2C_TypeDef *I2Cx, uint32_t mode);
+
+void I2C_WrapperWriteDataSet(I2C_TypeDef *I2Cx, uint8_t num, const uint8_t *buf);
+
+uint8_t I2C_WrapperGetTxFIFOLen(I2C_TypeDef *I2Cx);
+
+void I2C_WrapperTxFIFOClear(I2C_TypeDef *I2Cx);
+
+void I2C_WrapperReadNumSet(I2C_TypeDef *I2Cx, uint16_t num);
+
+uint8_t I2C_WrapperReceiveData(I2C_TypeDef *I2Cx);
+
+uint8_t I2C_WrapperGetRxFIFOLen(I2C_TypeDef *I2Cx);
+
+void I2C_WrapperTransStart(I2C_TypeDef *I2Cx);
+
+bool I2C_WrapperBusyCheck(I2C_TypeDef *I2Cx);
+
+void I2C_RAPModeCmd(I2C_TypeDef *I2Cx, FunctionalState NewState);
+
+void I2C_TaskTrigger(I2C_TypeDef *I2Cx, uint32_t Task);
+
+#endif
+
+
+/** End of I2C_Exported_Functions
+  * \}
+  */
+
+/** End of I2C
+  * \}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*RTL_I2C_H*/
+
+
diff --git a/bee/drivers/i2c/src/device/rtl87x2g/rtl_i2c_def.h b/bee/drivers/i2c/src/device/rtl87x2g/rtl_i2c_def.h
new file mode 100644
index 00000000..b4d38a4d
--- /dev/null
+++ b/bee/drivers/i2c/src/device/rtl87x2g/rtl_i2c_def.h
@@ -0,0 +1,1030 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef RTL_I2C_DEF_H
+#define RTL_I2C_DEF_H
+
+#include "utils/rtl_utils.h"
+#include "address_map.h"
+
+#ifdef  __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/*============================================================================*
+ *                          I2C Defines
+ *============================================================================*/
+/** \defgroup I2C         I2C
+  * \brief
+  * \{
+  */
+
+/** \defgroup I2C_Exported_Constants I2C Exported Constants
+  * \brief
+  * \{
+  */
+
+/**
+ * \defgroup I2C_Defines I2C Defines
+ * \{
+ * \ingroup  I2C_Exported_Constants
+ */
+#define I2C_TX_FIFO_SIZE                               (24)             //!< I2C TX FIFO SIZE is 24.
+#define I2C_RX_FIFO_SIZE                               (24)             //!< I2C RX FIFO SIZE is 24.
+#define I2C_CLOCK_MAX_SPEED                            (1000000)        //!< The maximum frequency supported by I2C is 1MHz.
+/** End of I2C_Defines
+  * \}
+  */
+
+/** End of I2C_Exported_Constants
+  * \}
+  */
+
+/** End of I2C
+  * \}
+  */
+
+/*============================================================================*
+ *                         I2C Registers Memory Map
+ *============================================================================*/
+typedef struct
+{
+    __IO uint32_t  IC_CON;                      /*!< 0x00 */
+    __IO uint32_t  IC_TAR;                      /*!< 0x04 */
+    __IO uint32_t  IC_SAR;                      /*!< 0x08 */
+    __IO uint32_t  RSVD_0C;                     /*!< 0x0C */
+    __IO uint32_t  IC_DATA_CMD;                 /*!< 0x10 */
+    __IO uint32_t  IC_SS_SCL_HCNT;              /*!< 0x14 */
+    __IO uint32_t  IC_SS_SCL_LCNT;              /*!< 0x18 */
+    __IO uint32_t  IC_FS_SCL_HCNT;              /*!< 0x1C */
+    __IO uint32_t  IC_FS_SCL_LCNT;              /*!< 0x20 */
+    __IO uint32_t  RSVD_24[2];                  /*!< 0x24 - 0x28 */
+    __I  uint32_t  IC_INTR_STAT;                /*!< 0x2C */
+    __IO uint32_t  IC_INTR_MASK;                /*!< 0x30 */
+    __I  uint32_t  IC_RAW_INTR_STAT;            /*!< 0x34 */
+    __IO uint32_t  IC_RX_TL;                    /*!< 0x38 */
+    __IO uint32_t  IC_TX_TL;                    /*!< 0x3C */
+    __I  uint32_t  IC_CLR_INTR;                 /*!< 0x40 */
+    __I  uint32_t  IC_CLR_RX_UNDER;             /*!< 0x44 */
+    __I  uint32_t  IC_CLR_RX_OVER;              /*!< 0x48 */
+    __I  uint32_t  IC_CLR_TX_OVER;              /*!< 0x4C */
+    __I  uint32_t  IC_CLR_RD_REQ;               /*!< 0x50 */
+    __I  uint32_t  IC_CLR_TX_ABRT;              /*!< 0x54 */
+    __I  uint32_t  IC_CLR_RX_DONE;              /*!< 0x58 */
+    __I  uint32_t  IC_CLR_ACTIVITY;             /*!< 0x5C */
+    __I  uint32_t  IC_CLR_STOP_DET;             /*!< 0x60 */
+    __I  uint32_t  IC_CLR_START_DET;            /*!< 0x64 */
+    __I  uint32_t  IC_CLR_GEN_CALL;             /*!< 0x68 */
+    __IO uint32_t  IC_ENABLE;                   /*!< 0x6C */
+    __I  uint32_t  IC_STATUS;                   /*!< 0x70 */
+    __I  uint32_t  IC_TXFLR;                    /*!< 0x74 */
+    __I  uint32_t  IC_RXFLR;                    /*!< 0x78 */
+    __IO uint32_t  IC_SDA_HOLD;                 /*!< 0x7C */
+    __I  uint32_t  IC_TX_ABRT_SOURCE;           /*!< 0x80 */
+    __IO uint32_t  IC_SLV_DATA_NACK_ONLY;       /*!< 0x84 */
+    __IO uint32_t  IC_DMA_CR;                   /*!< 0x88 */
+    __IO uint32_t  IC_DMA_TDLR;                 /*!< 0x8C */
+    __IO uint32_t  IC_DMA_RDLR;                 /*!< 0x90 */
+    __IO uint32_t  IC_SDA_SETUP;                /*!< 0x94 */
+    __IO uint32_t  IC_ACK_GENERAL_CALL;         /*!< 0x98 */
+    __I  uint32_t  IC_ENABLE_STATUS;            /*!< 0x9C */
+    __IO uint32_t  IC_FS_SPKLEN;                /*!< 0xA0 */
+} I2C_TypeDef;
+
+/*============================================================================*
+ *                         I2C Declaration
+ *============================================================================*/
+/** \defgroup I2C         I2C
+  * \brief
+  * \{
+  */
+
+/** \defgroup I2C_Exported_Constants I2C Exported Constants
+  * \brief
+  * \{
+  */
+
+/** \defgroup I2C_Declaration I2C Declaration
+  * \{
+  * \ingroup  I2C_Exported_Constants
+  */
+
+#define I2C0               ((I2C_TypeDef *) I2C0_REG_BASE)   //!< I2C0 base address.
+#define I2C1               ((I2C_TypeDef *) I2C1_REG_BASE)   //!< I2C1 base address.
+#define I2C2               ((I2C_TypeDef *) I2C2_REG_BASE)   //!< I2C2 base address.
+#define I2C3               ((I2C_TypeDef *) I2C3_REG_BASE)   //!< I2C3 base address.
+
+#define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C0) || \
+                                   ((PERIPH) == I2C1) || \
+                                   ((PERIPH) == I2C2) || \
+                                   ((PERIPH) == I2C3)) //!< Check if the input parameter is valid.
+
+/** End of I2C_Declaration
+  * \}
+  */
+
+/** End of I2C_Exported_Constants
+  * \}
+  */
+
+/** End of I2C
+  * \}
+  */
+
+/*============================================================================*
+ *                         I2C Private Types
+ *============================================================================*/
+typedef struct
+{
+    uint32_t i2c_reg[18];
+} I2CStoreReg_Typedef;
+
+/*============================================================================*
+ *                         I2C Registers and Field Descriptions
+ *============================================================================*/
+/* 0x00
+    0       R/W    master_mode             1'h1
+    2:1     R/W    speed                   2'b11
+    3       R/W    ic_10bitaddr_slave      1'h1
+    4       R      ic_10bitaddr_master     1'h1
+    5       R/W    ic_restart_en           1'h1
+    6       R/W    ic_slave_disable        1'h1
+    7       R      reserved_dummy00_7      1'h0
+    8       R/W    tx_empty_ctrl           1'h0
+    9       R/W    reserved_dummy00_9      1'h0
+    31:10   R      reserved_dummy00_31_10  22'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t master_mode: 1;
+        uint32_t speed: 2;
+        uint32_t ic_10bitaddr_slave: 1;
+        const uint32_t ic_10bitaddr_master: 1;
+        uint32_t ic_restart_en: 1;
+        uint32_t ic_slave_disable: 1;
+        const uint32_t reserved_2: 1;
+        uint32_t tx_empty_ctrl: 1;
+        const uint32_t reserved_1: 1;
+        const uint32_t reserved_0: 22;
+    } b;
+} IC_CON_TypeDef;
+
+
+
+/* 0x04
+    9:0     R/W    ic_tar                  10'h055
+    10      R/W    gc_or_start             1'h0
+    11      R/W    special                 1'h0
+    12      R/W    ic_10bitaddr_master     1'h1
+    31:13   R      reserved_dummy04_31_13  19'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t ic_tar: 10;
+        uint32_t gc_or_start: 1;
+        uint32_t special: 1;
+        uint32_t ic_10bitaddr_master: 1;
+        const uint32_t reserved_0: 19;
+    } b;
+} IC_TAR_TypeDef;
+
+
+
+/* 0x08
+    9:0     R/W    ic_sar                  10'h055
+    31:10   R      reserved_dummy08_31_10  22'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t ic_sar: 10;
+        const uint32_t reserved_0: 22;
+    } b;
+} IC_SAR_TypeDef;
+
+
+
+/* 0x10
+    7:0     R/W    dat                     8'h0
+    8       W      cmd                     1'h0
+    9       W      stop                    1'h0
+    10      W      restart                 1'h0
+    31:11   R      reserved_dummy10_31_11  21'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t dat: 8;
+        uint32_t cmd: 1;
+        uint32_t stop: 1;
+        uint32_t restart: 1;
+        const uint32_t reserved_0: 21;
+    } b;
+} IC_DATA_CMD_TypeDef;
+
+
+
+/* 0x14
+    15:0    R/W    ic_ss_scl_hcnt          16'h0190
+    31:16   R      reserved_dummy14_31_16  16'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t ic_ss_scl_hcnt: 16;
+        const uint32_t reserved_0: 16;
+    } b;
+} IC_SS_SCL_HCNT_TypeDef;
+
+
+
+/* 0x18
+    15:0    R/W    ic_ss_scl_lcnt          16'h01d6
+    31:16   R      reserved_dummy18_31_16  16'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t ic_ss_scl_lcnt: 16;
+        const uint32_t reserved_0: 16;
+    } b;
+} IC_SS_SCL_LCNT_TypeDef;
+
+
+
+/* 0x1C
+    15:0    R/W    ic_fs_scl_hcnt          16'h003c
+    31:16   R      reserved_dummy1c_31_16  16'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t ic_fs_scl_hcnt: 16;
+        const uint32_t reserved_0: 16;
+    } b;
+} IC_FS_SCL_HCNT_TypeDef;
+
+
+
+/* 0x20
+    15:0    R/W    ic_fs_scl_lcnt          16'h0082
+    31:16   R      reserved_dummy20_31_16  16'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t ic_fs_scl_lcnt: 16;
+        const uint32_t reserved_0: 16;
+    } b;
+} IC_FS_SCL_LCNT_TypeDef;
+
+
+
+
+/* 0x2C
+    0       R      r_rx_under              1'h0
+    1       R      r_rx_over               1'h0
+    2       R      r_rx_full               1'h0
+    3       R      r_tx_over               1'h0
+    4       R      r_tx_empty              1'h0
+    5       R      r_rd_req                1'h0
+    6       R      r_tx_abrt               1'h0
+    7       R      r_rx_done               1'h0
+    8       R      r_activity              1'h0
+    9       R      r_stop_det              1'h0
+    10      R      r_start_det             1'h0
+    11      R      r_gen_call              1'h0
+    12      R      reserved_dummy2c_12     1'h0
+    13      R      r_mst_on_hold           1'h0
+    31:14   R      reserved_dummy2c_31_14  18'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        const uint32_t r_rx_under: 1;
+        const uint32_t r_rx_over: 1;
+        const uint32_t r_rx_full: 1;
+        const uint32_t r_tx_over: 1;
+        const uint32_t r_tx_empty: 1;
+        const uint32_t r_rd_req: 1;
+        const uint32_t r_tx_abrt: 1;
+        const uint32_t r_rx_done: 1;
+        const uint32_t r_activity: 1;
+        const uint32_t r_stop_det: 1;
+        const uint32_t r_start_det: 1;
+        const uint32_t r_gen_call: 1;
+        const uint32_t reserved_1: 1;
+        const uint32_t r_mst_on_hold: 1;
+        const uint32_t reserved_0: 18;
+    } b;
+} IC_INTR_STAT_TypeDef;
+
+
+
+/* 0x30
+    0       R/W    m_rx_under              1'h1
+    1       R/W    m_rx_over               1'h1
+    2       R/W    m_rx_full               1'h1
+    3       R/W    m_tx_over               1'h1
+    4       R/W    m_tx_empty              1'h1
+    5       R/W    m_rd_req                1'h1
+    6       R/W    m_tx_abrt               1'h1
+    7       R/W    m_rx_done               1'h1
+    8       R/W    m_activity              1'h0
+    9       R/W    m_stop_det              1'h0
+    10      R/W    m_start_det             1'h0
+    11      R/W    m_gen_call              1'h1
+    12      R      reserved_dummy30_12     1'h0
+    13      R/W    m_mst_on_hold           1'h0
+    31:14   R      reserved_dummy30_31_14  18'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t m_rx_under: 1;
+        uint32_t m_rx_over: 1;
+        uint32_t m_rx_full: 1;
+        uint32_t m_tx_over: 1;
+        uint32_t m_tx_empty: 1;
+        uint32_t m_rd_req: 1;
+        uint32_t m_tx_abrt: 1;
+        uint32_t m_rx_done: 1;
+        uint32_t m_activity: 1;
+        uint32_t m_stop_det: 1;
+        uint32_t m_start_det: 1;
+        uint32_t m_gen_call: 1;
+        const uint32_t reserved_1: 1;
+        uint32_t m_mst_on_hold: 1;
+        const uint32_t reserved_0: 18;
+    } b;
+} IC_INTR_MASK_TypeDef;
+
+
+
+/* 0x34
+    0       R      rx_under                1'h0
+    1       R      rx_over                 1'h0
+    2       R      rx_full                 1'h0
+    3       R      tx_over                 1'h0
+    4       R      tx_empty                1'h0
+    5       R      rd_req                  1'h0
+    6       R      tx_abrt                 1'h0
+    7       R      rx_done                 1'h0
+    8       R      activity                1'h0
+    9       R      stop_det                1'h0
+    10      R      start_det               1'h0
+    11      R      gen_call                1'h0
+    12      R      reserved_dummy34_12     1'h0
+    13      R      mst_on_hold             1'h0
+    31:14   R      reserved_dummy34_31_14  18'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        const uint32_t rx_under: 1;
+        const uint32_t rx_over: 1;
+        const uint32_t rx_full: 1;
+        const uint32_t tx_over: 1;
+        const uint32_t tx_empty: 1;
+        const uint32_t rd_req: 1;
+        const uint32_t tx_abrt: 1;
+        const uint32_t rx_done: 1;
+        const uint32_t activity: 1;
+        const uint32_t stop_det: 1;
+        const uint32_t start_det: 1;
+        const uint32_t gen_call: 1;
+        const uint32_t reserved_1: 1;
+        const uint32_t mst_on_hold: 1;
+        const uint32_t reserved_0: 18;
+    } b;
+} IC_RAW_INTR_STAT_TypeDef;
+
+
+
+/* 0x38
+    7:0     R/W    rx_tl                   8'h14
+    31:8    R      reserved_dummy38_31_8   24'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t rx_tl: 8;
+        const uint32_t reserved_0: 24;
+    } b;
+} IC_RX_TL_TypeDef;
+
+
+
+/* 0x3C
+    7:0     R/W    tx_tl                   8'h03
+    31:8    R      reserved_dummy3c_31_8   24'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t tx_tl: 8;
+        const uint32_t reserved_0: 24;
+    } b;
+} IC_TX_TL_TypeDef;
+
+
+
+/* 0x40
+    0       W1C    clr_intr                1'h0
+    31:1    R      reserved_dummy40_31_1   31'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t clr_intr: 1;
+        const uint32_t reserved_0: 31;
+    } b;
+} IC_CLR_INTR_TypeDef;
+
+
+
+/* 0x44
+    0       R      clr_rx_under            1'h0
+    31:1    R      reserved_dummy44_31_1   31'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        const uint32_t clr_rx_under: 1;
+        const uint32_t reserved_0: 31;
+    } b;
+} IC_CLR_RX_UNDER_TypeDef;
+
+
+
+/* 0x48
+    0       R      clr_rx_over             1'h0
+    31:1    R      reserved_dummy48_31_1   31'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        const uint32_t clr_rx_over: 1;
+        const uint32_t reserved_0: 31;
+    } b;
+} IC_CLR_RX_OVER_TypeDef;
+
+
+
+/* 0x4C
+    0       R      clr_tx_over             1'h0
+    31:1    R      reserved_dummy4c_31_1   31'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        const uint32_t clr_tx_over: 1;
+        const uint32_t reserved_0: 31;
+    } b;
+} IC_CLR_TX_OVER_TypeDef;
+
+
+
+/* 0x50
+    0       R      clr_rd_req              1'h0
+    31:1    R      reserved_dummy50_31_1   31'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        const uint32_t clr_rd_req: 1;
+        const uint32_t reserved_0: 31;
+    } b;
+} IC_CLR_RD_REQ_TypeDef;
+
+
+
+/* 0x54
+    0       R      clr_tx_abrt             1'h0
+    31:1    R      reserved_dummy54_31_1   31'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        const uint32_t clr_tx_abrt: 1;
+        const uint32_t reserved_0: 31;
+    } b;
+} IC_CLR_TX_ABRT_TypeDef;
+
+
+
+/* 0x58
+    0       R      clr_rx_done             1'h0
+    31:1    R      reserved_dummy58_31_1   31'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        const uint32_t clr_rx_done: 1;
+        const uint32_t reserved_0: 31;
+    } b;
+} IC_CLR_RX_DONE_TypeDef;
+
+
+
+/* 0x5C
+    0       R      clr_activity            1'h0
+    31:1    R      reserved_dummy5c_31_1   31'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        const uint32_t clr_activity: 1;
+        const uint32_t reserved_0: 31;
+    } b;
+} IC_CLR_ACTIVITY_TypeDef;
+
+
+
+/* 0x60
+    0       R      clr_stop_det            1'h0
+    31:1    R      reserved_dummy60_31_1   31'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        const uint32_t clr_stop_det: 1;
+        const uint32_t reserved_0: 31;
+    } b;
+} IC_CLR_STOP_DET_TypeDef;
+
+
+
+/* 0x64
+    0       R      clr_start_det           1'h0
+    31:1    R      reserved_dummy64_31_1   31'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        const uint32_t clr_start_det: 1;
+        const uint32_t reserved_0: 31;
+    } b;
+} IC_CLR_START_DET_TypeDef;
+
+
+
+/* 0x68
+    0       R      clr_gen_call            1'h0
+    31:1    R      reserved_dummy68_31_1   31'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        const uint32_t clr_gen_call: 1;
+        const uint32_t reserved_0: 31;
+    } b;
+} IC_CLR_GEN_CALL_TypeDef;
+
+
+
+/* 0x6C
+    0       R/W    ic_enable               1'h0
+    31:1    R      reserved_dummy6c_31_1   31'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t ic_enable: 1;
+        const uint32_t reserved_0: 31;
+    } b;
+} IC_ENABLE_TypeDef;
+
+
+
+/* 0x70
+    0       R      activity                1'h0
+    1       R      tfnf                    1'h1
+    2       R      tfe                     1'h1
+    3       R      rfne                    1'h0
+    4       R      rff                     1'h0
+    5       R      mst_activity            1'h0
+    6       R      slv_activity            1'h0
+    7       R      Reserved                1'h0
+    8       R      Reserved                1'h0
+    9       R      Reserved                1'h0
+    10      R      Reserved                1'h0
+    31:11   R      reserved_dummy70_31_11  21'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        const uint32_t activity: 1;
+        const uint32_t tfnf: 1;
+        const uint32_t tfe: 1;
+        const uint32_t rfne: 1;
+        const uint32_t rff: 1;
+        const uint32_t mst_activity: 1;
+        const uint32_t slv_activity: 1;
+        const uint32_t reserved_4: 1;
+        const uint32_t reserved_3: 1;
+        const uint32_t reserved_2: 1;
+        const uint32_t reserved_1: 1;
+        const uint32_t reserved_0: 21;
+    } b;
+} IC_STATUS_TypeDef;
+
+
+
+/* 0x74
+    6:0     R      txflr                   7'h0
+    31:7    R      reserved_dummy74_31_7   25'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        const uint32_t txflr: 7;
+        const uint32_t reserved_0: 25;
+    } b;
+} IC_TXFLR_TypeDef;
+
+
+
+/* 0x78
+    6:0     R      rxflr                   7'h0
+    31:7    R      reserved_dummy78_31_7   25'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        const uint32_t rxflr: 7;
+        const uint32_t reserved_0: 25;
+    } b;
+} IC_RXFLR_TypeDef;
+
+
+
+/* 0x7C
+    15:0    R/W    ic_sda_tx_hold          16'h1
+    23:16   R/W    ic_sda_rx_hold          8'h0
+    31:24   R      reserved_dummy7c_31_24  8'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t ic_sda_tx_hold: 16;
+        uint32_t ic_sda_rx_hold: 8;
+        const uint32_t reserved_0: 8;
+    } b;
+} IC_SDA_HOLD_TypeDef;
+
+
+
+/* 0x80
+    0       R      abrt_7b_addr_noack      1'h0
+    1       R      abrt_10addr1_noack      1'h0
+    2       R      abrt_10addr2_noack      1'h0
+    3       R      abrt_txdata_noack       1'h0
+    4       R      abrt_gcall_noack        1'h0
+    5       R      abrt_gcall_read         1'h0
+    6       R      reserved_dummy80_6      1'h0
+    7       R      abrt_sbyte_ackdet       1'h0
+    8       R      reserved_dummy80_8      1'h0
+    9       R      abrt_sbyte_norstrt      1'h0
+    10      R      abrt_10b_rd_norstrt     1'h0
+    11      R      abrt_master_dis         1'h0
+    12      R      arb_lost                1'h0
+    13      R      abrt_slvflush_txfifo    1'h0
+    14      R      abrt_slv_arblost        1'h0
+    15      R      abrt_slvrd_intx         1'h0
+    22:16   R      reserved_dummy80_22_16  7'h0
+    31:23   R      tx_flush_cnt            9'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        const uint32_t abrt_7b_addr_noack: 1;
+        const uint32_t abrt_10addr1_noack: 1;
+        const uint32_t abrt_10addr2_noack: 1;
+        const uint32_t abrt_txdata_noack: 1;
+        const uint32_t abrt_gcall_noack: 1;
+        const uint32_t abrt_gcall_read: 1;
+        const uint32_t reserved_2: 1;
+        const uint32_t abrt_sbyte_ackdet: 1;
+        const uint32_t reserved_1: 1;
+        const uint32_t abrt_sbyte_norstrt: 1;
+        const uint32_t abrt_10b_rd_norstrt: 1;
+        const uint32_t abrt_master_dis: 1;
+        const uint32_t arb_lost: 1;
+        const uint32_t abrt_slvflush_txfifo: 1;
+        const uint32_t abrt_slv_arblost: 1;
+        const uint32_t abrt_slvrd_intx: 1;
+        const uint32_t reserved_0: 7;
+        const uint32_t tx_flush_cnt: 9;
+    } b;
+} IC_TX_ABRT_SOURCE_TypeDef;
+
+
+
+/* 0x84
+    0       R/W    nack                    1'h0
+    31:1    R      reserved_dummy84_31_1   31'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t nack: 1;
+        const uint32_t reserved_0: 31;
+    } b;
+} IC_SLV_DATA_NACK_ONLY_TypeDef;
+
+
+
+/* 0x88
+    0       R/W    rdmae                   1'h0
+    1       R/W    tdmae                   1'h0
+    31:2    R      reserved_dummy88_31_2   30'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t rdmae: 1;
+        uint32_t tdmae: 1;
+        const uint32_t reserved_0: 30;
+    } b;
+} IC_DMA_CR_TypeDef;
+
+
+
+/* 0x8C
+    5:0     R/W    dmatdl                  6'h0
+    31:6    R      reserved_dummy8c_31_6   26'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t dmatdl: 6;
+        const uint32_t reserved_0: 26;
+    } b;
+} IC_DMA_TDLR_TypeDef;
+
+
+
+/* 0x90
+    5:0     R/W    dmardl                  6'h0
+    31:6    R      reserved_dummy90_31_6   26'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t dmardl: 6;
+        const uint32_t reserved_0: 26;
+    } b;
+} IC_DMA_RDLR_TypeDef;
+
+
+
+/* 0x94
+    7:0     R/W    sda_setup               8'h64
+    31:8    R      reserved_dummy94_31_8   24'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t sda_setup: 8;
+        const uint32_t reserved_0: 24;
+    } b;
+} IC_SDA_SETUP_TypeDef;
+
+
+
+/* 0x98
+    0       R/W    ack_gen_call            1'h1
+    31:1    R      reserved_dummy98_31_1   31'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t ack_gen_call: 1;
+        const uint32_t reserved_0: 31;
+    } b;
+} IC_ACK_GENERAL_CALL_TypeDef;
+
+
+
+/* 0x9C
+    0       R      ic_en                   1'h0
+    1       R      slv_disabled_while_busy 1'h0
+    2       R      slv_rx_data_lost        1'h0
+    31:3    R      reserved_dummy9c_31_3   29'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        const uint32_t ic_en: 1;
+        const uint32_t slv_disabled_while_busy: 1;
+        const uint32_t slv_rx_data_lost: 1;
+        const uint32_t reserved_0: 29;
+    } b;
+} IC_ENABLE_STATUS_TypeDef;
+
+
+
+/* 0xA0
+    7:0     R/W    ic_fs_spklen            8'h5
+    31:8    R      reserved_dummya0_31_8   24'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t ic_fs_spklen: 8;
+        const uint32_t reserved_0: 24;
+    } b;
+} IC_FS_SPKLEN_TypeDef;
+
+/* ================================================================================ */
+/* ================                   I2C  Constants               ================ */
+/* ================================================================================ */
+/** \defgroup I2C         I2C
+  * \brief
+  * \{
+  */
+
+/** \defgroup I2C_Exported_Constants I2C Exported Constants
+  * \brief
+  * \{
+  */
+
+/**
+ * \defgroup    I2C_Clock_Source I2C Clock Source
+ * \{
+ * \ingroup     I2C_Exported_Constants
+ */
+typedef enum
+{
+    I2C_CLOCK_SRC_40M,                  //!< I2C 40MHz clock srouce.
+} I2CClockSrc_TypeDef;
+
+#define IS_I2C_CLK_SOURCE(PERIPH)     ((PERIPH) == I2C_CLOCK_SRC_40M) //!< Check if the input parameter is valid.
+
+/** End of I2C_Clock_Source
+  * \}
+  */
+
+/**
+ * \defgroup    I2C_Clock_Divider I2C Clock Divider
+ * \{
+ * \ingroup     I2C_Exported_Constants
+ */
+typedef enum
+{
+    I2C_CLOCK_DIVIDER_1 = 0x0,          //!< The clock divider is 1.
+    I2C_CLOCK_DIVIDER_2 = 0x1,          //!< The clock divider is 2.
+    I2C_CLOCK_DIVIDER_4 = 0x2,          //!< The clock divider is 4.
+    I2C_CLOCK_DIVIDER_8 = 0x3,          //!< The clock divider is 8.
+    I2C_CLOCK_DIVIDER_16 = 0x4,         //!< The clock divider is 16.
+    I2C_CLOCK_DIVIDER_32 = 0x5,         //!< The clock divider is 32.
+    I2C_CLOCK_DIVIDER_40 = 0x6,         //!< The clock divider is 40.
+    I2C_CLOCK_DIVIDER_64 = 0x7,         //!< The clock divider is 64.
+} I2CClockDiv_TypeDef;
+
+#define IS_I2C_CLK_DIV(DIV) (((DIV) == I2C_CLOCK_DIVIDER_1) || \
+                             ((DIV) == I2C_CLOCK_DIVIDER_2) || \
+                             ((DIV) == I2C_CLOCK_DIVIDER_4) || \
+                             ((DIV) == I2C_CLOCK_DIVIDER_8) || \
+                             ((DIV) == I2C_CLOCK_DIVIDER_16) || \
+                             ((DIV) == I2C_CLOCK_DIVIDER_32) || \
+                             ((DIV) == I2C_CLOCK_DIVIDER_40) || \
+                             ((DIV) == I2C_CLOCK_DIVIDER_64)) //!< Check if the input parameter is valid.
+
+/** End of I2C_Clock_Divider
+  * \}
+  */
+
+/** End of I2C_Exported_Constants
+  * \}
+  */
+
+/** End of I2C
+  * \}
+  */
+
+#ifdef  __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* RTL_I2C_DEF_H */
diff --git a/bee/drivers/i2c/src/device/rtl87x2j/rtl87x2j_i2c.c b/bee/drivers/i2c/src/device/rtl87x2j/rtl87x2j_i2c.c
new file mode 100644
index 00000000..6b978958
--- /dev/null
+++ b/bee/drivers/i2c/src/device/rtl87x2j/rtl87x2j_i2c.c
@@ -0,0 +1,114 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *                           Header Files
+ *============================================================================*/
+#include "rtl_i2c.h"
+#include "rtl_rcc.h"
+
+/*============================================================================*
+ *                           Private Defines
+ *============================================================================*/
+#define I2C_CLOCK_AUTO_MODE_CONFIG_AUTOMATIC        (0x00000)
+#define I2C_CLOCK_AUTO_MODE_CONFIG_ALWAYSRUN        (0x3000F)//Force off 0x2000A
+
+/*============================================================================*
+ *                           Public Functions
+ *============================================================================*/
+
+uint8_t I2C_GetIndex(I2C_TypeDef *I2Cx)
+{
+    if (I2Cx == I2C0)
+    {
+        return 0;
+    }
+    else
+    {
+        return 1;
+    }
+}
+
+uint8_t I2C_GetCompIndex(I2C_TypeDef *I2Cx)
+{
+    uint8_t compensate_index = 3;
+
+    if (I2Cx == I2C0)
+    {
+        compensate_index = PCC_REG_READ_BITFIELD(PCC_REG_I2C0, R_I2C0_CLK_DIV_SEL);
+    }
+    else if (I2Cx == I2C1)
+    {
+        compensate_index = PCC_REG_READ_BITFIELD(PCC_REG_I2C1, R_I2C1_CLK_DIV_SEL);
+    }
+
+    return compensate_index;
+}
+
+
+/**
+  * \brief  I2C clock divider config.
+  * \param  I2Cx: Select the I2C peripheral. \ref I2C_Declaration
+  * \param  ClockDiv: specifies the APB peripheral to gates its clock. \ref Clock_Divider
+  * \return None
+  */
+void I2C_SetClock(I2C_TypeDef *I2Cx, uint16_t ClockSrc, uint16_t ClockDiv)
+{
+    assert_param(IS_I2C_DIV(ClockDiv));
+
+    /* Config I2C clock divider */
+    if (I2Cx == I2C0)
+    {
+        PCC_REG_WRITE_BITFIELD(PCC_REG_I2C0, R_I2C0_CLK_DIV_SEL, ClockDiv);
+    }
+    else if (I2Cx == I2C1)
+    {
+        PCC_REG_WRITE_BITFIELD(PCC_REG_I2C1, R_I2C1_CLK_DIV_SEL, ClockDiv);
+    }
+
+    return;
+}
+
+
+uint32_t I2C_GetClock(I2C_TypeDef *I2Cx)
+{
+    uint32_t I2CClkSrc = 0;
+    uint8_t compensate_index = I2C_GetCompIndex(I2Cx);
+    if (compensate_index == 6)
+    {
+        I2CClkSrc = 1000000;
+    }
+    else if (compensate_index == 7)
+    {
+        I2CClkSrc = 625000;
+    }
+    else
+    {
+        I2CClkSrc = 40000000 / BIT(compensate_index);
+    }
+
+    return I2CClkSrc;
+}
+
+void I2C_ClockAutoModeCmd(I2C_TypeDef *I2Cx, FunctionalState Newstate)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+    if (Newstate == ENABLE)
+    {
+        I2Cx->QACTIVE_MANUAL_CTRL = I2C_CLOCK_AUTO_MODE_CONFIG_AUTOMATIC;
+    }
+    else
+    {
+        I2Cx->QACTIVE_MANUAL_CTRL = I2C_CLOCK_AUTO_MODE_CONFIG_ALWAYSRUN;
+    }
+
+    return;
+}
+
+
+
diff --git a/bee/drivers/i2c/src/device/rtl87x2j/rtl_i2c_def.h b/bee/drivers/i2c/src/device/rtl87x2j/rtl_i2c_def.h
new file mode 100644
index 00000000..6bed7fd7
--- /dev/null
+++ b/bee/drivers/i2c/src/device/rtl87x2j/rtl_i2c_def.h
@@ -0,0 +1,1118 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef RTL_I2C_DEF_H
+#define RTL_I2C_DEF_H
+
+#include "utils/rtl_utils.h"
+#include "address_map.h"
+
+#ifdef  __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/*============================================================================*
+ *                          I2C Defines
+ *============================================================================*/
+/** \defgroup I2C         I2C
+  * \brief
+  * \{
+  */
+
+/** \defgroup I2C_Exported_Constants I2C Exported Constants
+  * \brief
+  * \{
+  */
+
+/**
+ * \defgroup I2C_Defines I2C Defines
+ * \{
+ * \ingroup  I2C_Exported_Constants
+ */
+#define CHIP_I2C_NUMBER                                (2)
+#define I2C_TX_FIFO_SIZE                               (24)
+#define I2C_RX_FIFO_SIZE                               (24)
+#define I2C_CLOCK_MAX_SPEED                            (1000000)
+#define I2C_SUPPORT_WRAPPER_MODE                       (1)
+#define I2C_SUPPORT_RAP_FUNCTION                       (1)
+#define I2C_SUPPORT_AUTO_CLOCK                         (1)
+
+/** End of I2C_Defines
+  * \}
+  */
+
+/** End of I2C_Exported_Constants
+  * \}
+  */
+
+/** End of I2C
+  * \}
+  */
+
+/*============================================================================*
+ *                          I2C Registers Memory Map
+ *============================================================================*/
+typedef struct
+{
+    __IO uint32_t IC_CON;                       /*!< 0x00 */
+    __IO uint32_t IC_TAR;                       /*!< 0x04 */
+    __IO uint32_t IC_SAR;                       /*!< 0x08 */
+    __IO uint32_t RSVD_0C;                      /*!< 0x0C */
+    __IO uint32_t IC_DATA_CMD;                  /*!< 0x10 */
+    __IO uint32_t IC_SS_SCL_HCNT;               /*!< 0x14 */
+    __IO uint32_t IC_SS_SCL_LCNT;               /*!< 0x18 */
+    __IO uint32_t IC_FS_SCL_HCNT;               /*!< 0x1C */
+    __IO uint32_t IC_FS_SCL_LCNT;               /*!< 0x20 */
+    __IO uint32_t RSVD_24[2];                   /*!< 0x24 - 0x28 */
+    __I  uint32_t IC_INTR_STAT;                 /*!< 0x2C */
+    __IO uint32_t IC_INTR_MASK;                 /*!< 0x30 */
+    __I  uint32_t IC_RAW_INTR_STAT;             /*!< 0x34 */
+    __IO uint32_t IC_RX_TL;                     /*!< 0x38 */
+    __IO uint32_t IC_TX_TL;                     /*!< 0x3C */
+    __I  uint32_t IC_CLR_INTR;                  /*!< 0x40 */
+    __I  uint32_t IC_CLR_RX_UNDER;              /*!< 0x44 */
+    __I  uint32_t IC_CLR_RX_OVER;               /*!< 0x48 */
+    __I  uint32_t IC_CLR_TX_OVER;               /*!< 0x4C */
+    __I  uint32_t IC_CLR_RD_REQ;                /*!< 0x50 */
+    __I  uint32_t IC_CLR_TX_ABRT;               /*!< 0x54 */
+    __I  uint32_t IC_CLR_RX_DONE;               /*!< 0x58 */
+    __I  uint32_t IC_CLR_ACTIVITY;              /*!< 0x5C */
+    __I  uint32_t IC_CLR_STOP_DET;              /*!< 0x60 */
+    __I  uint32_t IC_CLR_START_DET;             /*!< 0x64 */
+    __I  uint32_t IC_CLR_GEN_CALL;              /*!< 0x68 */
+    __IO uint32_t IC_ENABLE;                    /*!< 0x6C */
+    __I  uint32_t IC_STATUS;                    /*!< 0x70 */
+    __I  uint32_t IC_TXFLR;                     /*!< 0x74 */
+    __I  uint32_t IC_RXFLR;                     /*!< 0x78 */
+    __IO uint32_t IC_SDA_HOLD;                  /*!< 0x7C */
+    __I  uint32_t IC_TX_ABRT_SOURCE;            /*!< 0x80 */
+    __IO uint32_t IC_SLV_DATA_NACK_ONLY;        /*!< 0x84 */
+    __IO uint32_t IC_DMA_CR;                    /*!< 0x88 */
+    __IO uint32_t IC_DMA_TDLR;                  /*!< 0x8C */
+    __IO uint32_t IC_DMA_RDLR;                  /*!< 0x90 */
+    __IO uint32_t IC_SDA_SETUP;                 /*!< 0x94 */
+    __IO uint32_t IC_ACK_GENERAL_CALL;          /*!< 0x98 */
+    __I  uint32_t IC_ENABLE_STATUS;             /*!< 0x9C */
+    __IO uint32_t IC_FS_SPKLEN;                 /*!< 0xA0 */
+    __IO uint32_t RSVD_A4[23];                  /*!< 0xA4 - 0xFC */
+    __IO uint32_t RAP_TASK;                     /*!< 0x100 */
+    __IO uint32_t RAP_WCMD_NUM;                 /*!< 0x104 */
+    __IO uint32_t RAP_RCMD_NUM;                 /*!< 0x108 */
+    __IO uint32_t WRAP_CR;                      /*!< 0x10C */
+    __IO uint32_t RAP_WCMD_DATA;                /*!< 0x110 */
+    __IO uint32_t RAP_BUF_CR;                   /*!< 0x114 */
+    __I  uint32_t I2C_VERSION;                  /*!< 0x118 */
+    __IO uint32_t QACTIVE_MANUAL_CTRL;          /*!< 0x11C */
+} I2C_TypeDef;
+
+/*============================================================================*
+ *                          I2C Declaration
+ *============================================================================*/
+/** \defgroup I2C         I2C
+ * \brief
+ * \{
+ */
+
+/** \defgroup I2C_Exported_Constants I2C Exported Constants
+  * \brief
+  * \{
+  */
+
+/** \defgroup I2C_Declaration I2C Declaration
+  * \{
+  * \ingroup  I2C_Exported_Constants
+  */
+
+#define I2C0               ((I2C_TypeDef *) I2C0_BASE)
+#define I2C1               ((I2C_TypeDef *) I2C1_BASE)
+
+#define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C0) || \
+                                   ((PERIPH) == I2C1))
+
+/** End of I2C_Declaration
+  * \}
+  */
+
+/** End of I2C_Exported_Constants
+  * \}
+  */
+
+/** End of I2C
+  * \}
+  */
+
+/*============================================================================*
+ *                          I2C Private Types
+ *============================================================================*/
+typedef struct
+{
+    uint32_t i2c_reg[18];
+} I2CStoreReg_Typedef;
+
+/*============================================================================*
+ *                          I2C Registers and Field Descriptions
+ *============================================================================*/
+/* 0x00
+   0       R/W    master_mode             1'h1
+   2:1     R/W    speed                   2'b11
+   3       R/W    ic_10bitaddr_slave      1'h1
+   4       R      ic_10bitaddr_master     1'h1
+   5       R/W    ic_restart_en           1'h1
+   6       R/W    ic_slave_disable        1'h1
+   7       R      reserved_dummy00_7      1'h0
+   8       R/W    tx_empty_ctrl           1'h0
+   9       R/W    rx_fifo_full_hld_ctrl   1'h0
+   31:10   R      reserved_dummy00_31_10  22'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t master_mode: 1;
+        uint32_t speed: 2;
+        uint32_t ic_10bitaddr_slave: 1;
+        const uint32_t ic_10bitaddr_master: 1;
+        uint32_t ic_restart_en: 1;
+        uint32_t ic_slave_disable: 1;
+        const uint32_t reserved_1: 1;
+        uint32_t tx_empty_ctrl: 1;
+        uint32_t rx_fifo_full_hld_ctrl: 1;
+        const uint32_t reserved_0: 22;
+    } b;
+} IC_CON_TypeDef;
+
+
+/* 0x04
+   9:0     R/W    ic_tar                  10'h055
+   10      R/W    gc_or_start             1'h0
+   11      R/W    special                 1'h0
+   12      R/W    ic_10bitaddr_master     1'h1
+   31:13   R      reserved_dummy04_31_13  19'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t ic_tar: 10;
+        uint32_t gc_or_start: 1;
+        uint32_t special: 1;
+        uint32_t ic_10bitaddr_master: 1;
+        const uint32_t reserved_0: 19;
+    } b;
+} IC_TAR_TypeDef;
+
+
+/* 0x08
+   9:0     R/W    ic_sar                  10'h055
+   31:10   R      reserved_dummy08_31_10  22'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t ic_sar: 10;
+        const uint32_t reserved_0: 22;
+    } b;
+} IC_SAR_TypeDef;
+
+
+
+
+/* 0x10
+   7:0     R/W    dat                     8'h0
+   8       W      cmd                     1'h0
+   9       W      stop                    1'h0
+   10      W      restart                 1'h0
+   31:11   R      reserved_dummy10_31_11  21'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t dat: 8;
+        uint32_t cmd: 1;
+        uint32_t stop: 1;
+        uint32_t restart: 1;
+        const uint32_t reserved_0: 21;
+    } b;
+} IC_DATA_CMD_TypeDef;
+
+
+/* 0x14
+   15:0    R/W    ic_ss_scl_hcnt          16'h0190
+   31:16   R      reserved_dummy14_31_16  16'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t ic_ss_scl_hcnt: 16;
+        const uint32_t reserved_0: 16;
+    } b;
+} IC_SS_SCL_HCNT_TypeDef;
+
+
+/* 0x18
+   15:0    R/W    ic_ss_scl_lcnt          16'h01d6
+   31:16   R      reserved_dummy18_31_16  16'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t ic_ss_scl_lcnt: 16;
+        const uint32_t reserved_0: 16;
+    } b;
+} IC_SS_SCL_LCNT_TypeDef;
+
+
+/* 0x1C
+   15:0    R/W    ic_fs_scl_hcnt          16'h003c
+   31:16   R      reserved_dummy1c_31_16  16'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t ic_fs_scl_hcnt: 16;
+        const uint32_t reserved_0: 16;
+    } b;
+} IC_FS_SCL_HCNT_TypeDef;
+
+
+/* 0x20
+   15:0    R/W    ic_fs_scl_lcnt          16'h0082
+   31:16   R      reserved_dummy20_31_16  16'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t ic_fs_scl_lcnt: 16;
+        const uint32_t reserved_0: 16;
+    } b;
+} IC_FS_SCL_LCNT_TypeDef;
+
+
+
+
+/* 0x2C
+   0       R      r_rx_under              1'h0
+   1       R      r_rx_over               1'h0
+   2       R      r_rx_full               1'h0
+   3       R      r_tx_over               1'h0
+   4       R      r_tx_empty              1'h0
+   5       R      r_rd_req                1'h0
+   6       R      r_tx_abrt               1'h0
+   7       R      r_rx_done               1'h0
+   8       R      r_activity              1'h0
+   9       R      r_stop_det              1'h0
+   10      R      r_start_det             1'h0
+   11      R      r_gen_call              1'h0
+   12      R      reserved_dummy2c_12     1'h0
+   13      R      r_mst_on_hold           1'h0
+   31:14   R      reserved_dummy2c_31_14  18'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t r_rx_under: 1;
+        const uint32_t r_rx_over: 1;
+        const uint32_t r_rx_full: 1;
+        const uint32_t r_tx_over: 1;
+        const uint32_t r_tx_empty: 1;
+        const uint32_t r_rd_req: 1;
+        const uint32_t r_tx_abrt: 1;
+        const uint32_t r_rx_done: 1;
+        const uint32_t r_activity: 1;
+        const uint32_t r_stop_det: 1;
+        const uint32_t r_start_det: 1;
+        const uint32_t r_gen_call: 1;
+        const uint32_t reserved_1: 1;
+        const uint32_t r_mst_on_hold: 1;
+        const uint32_t reserved_0: 18;
+    } b;
+} IC_INTR_STAT_TypeDef;
+
+
+/* 0x30
+   0       R/W    m_rx_under              1'h1
+   1       R/W    m_rx_over               1'h1
+   2       R/W    m_rx_full               1'h1
+   3       R/W    m_tx_over               1'h1
+   4       R/W    m_tx_empty              1'h1
+   5       R/W    m_rd_req                1'h1
+   6       R/W    m_tx_abrt               1'h1
+   7       R/W    m_rx_done               1'h1
+   8       R/W    m_activity              1'h0
+   9       R/W    m_stop_det              1'h0
+   10      R/W    m_start_det             1'h0
+   11      R/W    m_gen_call              1'h1
+   12      R      reserved_dummy30_12     1'h0
+   13      R/W    m_mst_on_hold           1'h0
+   31:14   R      reserved_dummy30_31_14  18'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t m_rx_under: 1;
+        uint32_t m_rx_over: 1;
+        uint32_t m_rx_full: 1;
+        uint32_t m_tx_over: 1;
+        uint32_t m_tx_empty: 1;
+        uint32_t m_rd_req: 1;
+        uint32_t m_tx_abrt: 1;
+        uint32_t m_rx_done: 1;
+        uint32_t m_activity: 1;
+        uint32_t m_stop_det: 1;
+        uint32_t m_start_det: 1;
+        uint32_t m_gen_call: 1;
+        const uint32_t reserved_1: 1;
+        uint32_t m_mst_on_hold: 1;
+        const uint32_t reserved_0: 18;
+    } b;
+} IC_INTR_MASK_TypeDef;
+
+
+/* 0x34
+   0       R      rx_under                1'h0
+   1       R      rx_over                 1'h0
+   2       R      rx_full                 1'h0
+   3       R      tx_over                 1'h0
+   4       R      tx_empty                1'h0
+   5       R      rd_req                  1'h0
+   6       R      tx_abrt                 1'h0
+   7       R      rx_done                 1'h0
+   8       R      activity                1'h0
+   9       R      stop_det                1'h0
+   10      R      start_det               1'h0
+   11      R      gen_call                1'h0
+   12      R      reserved_dummy34_12     1'h0
+   13      R      mst_on_hold             1'h0
+   31:14   R      reserved_dummy34_31_14  18'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t rx_under: 1;
+        const uint32_t rx_over: 1;
+        const uint32_t rx_full: 1;
+        const uint32_t tx_over: 1;
+        const uint32_t tx_empty: 1;
+        const uint32_t rd_req: 1;
+        const uint32_t tx_abrt: 1;
+        const uint32_t rx_done: 1;
+        const uint32_t activity: 1;
+        const uint32_t stop_det: 1;
+        const uint32_t start_det: 1;
+        const uint32_t gen_call: 1;
+        const uint32_t reserved_1: 1;
+        const uint32_t mst_on_hold: 1;
+        const uint32_t reserved_0: 18;
+    } b;
+} IC_RAW_INTR_STAT_TypeDef;
+
+
+/* 0x38
+   7:0     R/W    rx_tl                   8'h14
+   31:8    R      reserved_dummy38_31_8   24'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t rx_tl: 8;
+        const uint32_t reserved_0: 24;
+    } b;
+} IC_RX_TL_TypeDef;
+
+
+/* 0x3C
+   7:0     R/W    tx_tl                   8'h03
+   31:8    R      reserved_dummy3c_31_8   24'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t tx_tl: 8;
+        const uint32_t reserved_0: 24;
+    } b;
+} IC_TX_TL_TypeDef;
+
+
+/* 0x40
+   0       R      clr_intr                1'h0
+   31:1    R      reserved_dummy40_31_1   31'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t clr_intr: 1;
+        const uint32_t reserved_0: 31;
+    } b;
+} IC_CLR_INTR_TypeDef;
+
+
+/* 0x44
+   0       R      clr_rx_under            1'h0
+   31:1    R      reserved_dummy44_31_1   31'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t clr_rx_under: 1;
+        const uint32_t reserved_0: 31;
+    } b;
+} IC_CLR_RX_UNDER_TypeDef;
+
+
+/* 0x48
+   0       R      clr_rx_over             1'h0
+   31:1    R      reserved_dummy48_31_1   31'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t clr_rx_over: 1;
+        const uint32_t reserved_0: 31;
+    } b;
+} IC_CLR_RX_OVER_TypeDef;
+
+
+/* 0x4C
+   0       R      clr_tx_over             1'h0
+   31:1    R      reserved_dummy4c_31_1   31'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t clr_tx_over: 1;
+        const uint32_t reserved_0: 31;
+    } b;
+} IC_CLR_TX_OVER_TypeDef;
+
+
+/* 0x50
+   0       R      clr_rd_req              1'h0
+   31:1    R      reserved_dummy50_31_1   31'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t clr_rd_req: 1;
+        const uint32_t reserved_0: 31;
+    } b;
+} IC_CLR_RD_REQ_TypeDef;
+
+
+/* 0x54
+   0       R      clr_tx_abrt             1'h0
+   31:1    R      reserved_dummy54_31_1   31'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t clr_tx_abrt: 1;
+        const uint32_t reserved_0: 31;
+    } b;
+} IC_CLR_TX_ABRT_TypeDef;
+
+
+/* 0x58
+   0       R      clr_rx_done             1'h0
+   31:1    R      reserved_dummy58_31_1   31'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t clr_rx_done: 1;
+        const uint32_t reserved_0: 31;
+    } b;
+} IC_CLR_RX_DONE_TypeDef;
+
+
+/* 0x5C
+   0       R      clr_activity            1'h0
+   31:1    R      reserved_dummy5c_31_1   31'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t clr_activity: 1;
+        const uint32_t reserved_0: 31;
+    } b;
+} IC_CLR_ACTIVITY_TypeDef;
+
+
+/* 0x60
+   0       R      clr_stop_det            1'h0
+   31:1    R      reserved_dummy60_31_1   31'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t clr_stop_det: 1;
+        const uint32_t reserved_0: 31;
+    } b;
+} IC_CLR_STOP_DET_TypeDef;
+
+
+/* 0x64
+   0       R      clr_start_det           1'h0
+   31:1    R      reserved_dummy64_31_1   31'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t clr_start_det: 1;
+        const uint32_t reserved_0: 31;
+    } b;
+} IC_CLR_START_DET_TypeDef;
+
+
+/* 0x68
+   0       R      clr_gen_call            1'h0
+   31:1    R      reserved_dummy68_31_1   31'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t clr_gen_call: 1;
+        const uint32_t reserved_0: 31;
+    } b;
+} IC_CLR_GEN_CALL_TypeDef;
+
+
+/* 0x6C
+   0       R/W    ic_enable               1'h0
+   31:1    R      reserved_dummy6c_31_1   31'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t ic_enable: 1;
+        const uint32_t reserved_0: 31;
+    } b;
+} IC_ENABLE_TypeDef;
+
+
+/* 0x70
+   0       R      activity                1'h0
+   1       R      tfnf                    1'h1
+   2       R      tfe                     1'h1
+   3       R      rfne                    1'h0
+   4       R      rff                     1'h0
+   5       R      mst_activity            1'h0
+   6       R      slv_activity            1'h0
+   7       R      mst_hold_tx_fifo_empty  1'h0
+   8       R      mst_hold_rx_fifo_full   1'h0
+   9       R      slv_hold_tx_fifo_empty  1'h0
+   10      R      slv_hold_rx_fifo_full   1'h0
+   31:11   R      reserved_dummy70_31_11  21'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t activity: 1;
+        const uint32_t tfnf: 1;
+        const uint32_t tfe: 1;
+        const uint32_t rfne: 1;
+        const uint32_t rff: 1;
+        const uint32_t mst_activity: 1;
+        const uint32_t slv_activity: 1;
+        const uint32_t mst_hold_tx_fifo_empty: 1;
+        const uint32_t mst_hold_rx_fifo_full: 1;
+        const uint32_t slv_hold_tx_fifo_empty: 1;
+        const uint32_t slv_hold_rx_fifo_full: 1;
+        const uint32_t reserved_0: 21;
+    } b;
+} IC_STATUS_TypeDef;
+
+
+/* 0x74
+   5:0     R      txflr                   6'h0
+   31:6    R      reserved_dummy74_31_7   26'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t txflr: 6;
+        const uint32_t reserved_0: 26;
+    } b;
+} IC_TXFLR_TypeDef;
+
+
+/* 0x78
+   5:0     R      rxflr                   6'h0
+   31:6    R      reserved_dummy78_31_7   26'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t rxflr: 6;
+        const uint32_t reserved_0: 26;
+    } b;
+} IC_RXFLR_TypeDef;
+
+
+/* 0x7C
+   15:0    R/W    ic_sda_tx_hold          16'h1
+   23:16   R/W    ic_sda_rx_hold          8'h0
+   31:24   R      reserved_dummy7c_31_24  8'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t ic_sda_tx_hold: 16;
+        uint32_t ic_sda_rx_hold: 8;
+        const uint32_t reserved_0: 8;
+    } b;
+} IC_SDA_HOLD_TypeDef;
+
+
+/* 0x80
+   0       R      abrt_7b_addr_noack      1'h0
+   1       R      abrt_10addr1_noack      1'h0
+   2       R      abrt_10addr2_noack      1'h0
+   3       R      abrt_txdata_noack       1'h0
+   4       R      abrt_gcall_noack        1'h0
+   5       R      abrt_gcall_read         1'h0
+   6       R      reserved_dummy80_6      1'h0
+   7       R      abrt_sbyte_ackdet       1'h0
+   8       R      reserved_dummy80_8      1'h0
+   9       R      abrt_sbyte_norstrt      1'h0
+   10      R      abrt_10b_rd_norstrt     1'h0
+   11      R      abrt_master_dis         1'h0
+   12      R      arb_lost                1'h0
+   13      R      abrt_slvflush_txfifo    1'h0
+   14      R      abrt_slv_arblost        1'h0
+   15      R      abrt_slvrd_intx         1'h0
+   22:16   R      reserved_dummy80_22_16  7'h0
+   31:23   R      tx_flush_cnt            9'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t abrt_7b_addr_noack: 1;
+        const uint32_t abrt_10addr1_noack: 1;
+        const uint32_t abrt_10addr2_noack: 1;
+        const uint32_t abrt_txdata_noack: 1;
+        const uint32_t abrt_gcall_noack: 1;
+        const uint32_t abrt_gcall_read: 1;
+        const uint32_t reserved_2: 1;
+        const uint32_t abrt_sbyte_ackdet: 1;
+        const uint32_t reserved_1: 1;
+        const uint32_t abrt_sbyte_norstrt: 1;
+        const uint32_t abrt_10b_rd_norstrt: 1;
+        const uint32_t abrt_master_dis: 1;
+        const uint32_t arb_lost: 1;
+        const uint32_t abrt_slvflush_txfifo: 1;
+        const uint32_t abrt_slv_arblost: 1;
+        const uint32_t abrt_slvrd_intx: 1;
+        const uint32_t reserved_0: 7;
+        const uint32_t tx_flush_cnt: 9;
+    } b;
+} IC_TX_ABRT_SOURCE_TypeDef;
+
+
+/* 0x84
+   0       R/W    nack                    1'h0
+   31:1    R      reserved_dummy84_31_1   31'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t nack: 1;
+        const uint32_t reserved_0: 31;
+    } b;
+} IC_SLV_DATA_NACK_ONLY_TypeDef;
+
+
+/* 0x88
+   0       R/W    rdmae                   1'h0
+   1       R/W    tdmae                   1'h0
+   31:2    R      reserved_dummy88_31_2   30'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t rdmae: 1;
+        uint32_t tdmae: 1;
+        const uint32_t reserved_0: 30;
+    } b;
+} IC_DMA_CR_TypeDef;
+
+
+/* 0x8C
+   4:0     R/W    dmatdl                  5'h0
+   31:5    R      reserved_dummy8c_31_6   27'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t dmatdl: 5;
+        const uint32_t reserved_0: 27;
+    } b;
+} IC_DMA_TDLR_TypeDef;
+
+
+/* 0x90
+   4:0     R/W    dmardl                  5'h0
+   31:5    R      reserved_dummy90_31_6   27'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t dmardl: 5;
+        const uint32_t reserved_0: 27;
+    } b;
+} IC_DMA_RDLR_TypeDef;
+
+
+/* 0x94
+   7:0     R/W    sda_setup               8'h64
+   31:8    R      reserved_dummy94_31_8   24'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t sda_setup: 8;
+        const uint32_t reserved_0: 24;
+    } b;
+} IC_SDA_SETUP_TypeDef;
+
+
+/* 0x98
+   0       R/W    ack_gen_call            1'h1
+   31:1    R      reserved_dummy98_31_1   31'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t ack_gen_call: 1;
+        const uint32_t reserved_0: 31;
+    } b;
+} IC_ACK_GENERAL_CALL_TypeDef;
+
+
+/* 0x9C
+   0       R      ic_en                   1'h0
+   1       R      slv_disabled_while_busy 1'h0
+   2       R      slv_rx_data_lost        1'h0
+   31:3    R      reserved_dummy9c_31_3   29'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t ic_en: 1;
+        const uint32_t slv_disabled_while_busy: 1;
+        const uint32_t slv_rx_data_lost: 1;
+        const uint32_t reserved_0: 29;
+    } b;
+} IC_ENABLE_STATUS_TypeDef;
+
+
+/* 0xA0
+   7:0     R/W    ic_fs_spklen            8'h5
+   31:8    R      reserved_dummya0_31_8   24'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t ic_fs_spklen: 8;
+        const uint32_t reserved_0: 24;
+    } b;
+} IC_FS_SPKLEN_TypeDef;
+
+
+
+
+/* 0x100
+   0       R/WAC  task_start              1'h0
+   31:1    R      reserved_dummy100_31_1  31'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t task_start: 1;
+        const uint32_t reserved_0: 31;
+    } b;
+} RAP_TASK_TypeDef;
+
+
+/* 0x104
+   4:0     R/W    wcmd_num                5'h0
+   31:5    R      reserved_dummy104_31_5  27'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t wcmd_num: 5;
+        const uint32_t reserved_0: 27;
+    } b;
+} RAP_WCMD_NUM_TypeDef;
+
+
+/* 0x108
+   15:0    R/W    rcmd_num                16'h0
+   31:16   R      reserved_dummy108_31_16 16'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t rcmd_num: 16;
+        const uint32_t reserved_0: 16;
+    } b;
+} RAP_RCMD_NUM_TypeDef;
+
+
+/* 0x10C
+   1:0     R/W    trans_mode              2'h0
+   3:2     R      reserved_dummy10c_3_2   2'h0
+   4       R/W    rap_mode                1'h0
+   5       R/WAC  start_wrapper           1'h0
+   7:6     R      reserved_dummy10c_7_6   2'h0
+   8       R/W    wrapper_clk_en          1'h0
+   15:9    R      reserved_dummy10c_15_9  7'h0
+   16      R      wrapper_busy            1'h0
+   31:17   R      reserved_dummy10c_31_17 15'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t trans_mode: 2;
+        const uint32_t reserved_3: 2;
+        uint32_t rap_mode: 1;
+        uint32_t start_wrapper: 1;
+        const uint32_t reserved_2: 2;
+        uint32_t wrapper_clk_en: 1;
+        const uint32_t reserved_1: 7;
+        const uint32_t wrapper_busy: 1;
+        const uint32_t reserved_0: 15;
+    } b;
+} WRAP_CR_TypeDef;
+
+
+/* 0x110
+   7:0     R/W    wrap_data               8'h0
+   31:8    R      reserved_dummy110_31_8  24'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t wrap_data: 8;
+        const uint32_t reserved_0: 24;
+    } b;
+} RAP_WCMD_DATA_TypeDef;
+
+
+/* 0x114
+   4:0     R      wrap_buf_amount         5'h0
+   15:5    R      reserved_dummy114_15_5  11'h0
+   16      R/W    wrap_buf_clear          1'h0
+   31:17   R      reserved_dummy114_31_17 15'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t wrap_buf_amount: 5;
+        const uint32_t reserved_1: 11;
+        uint32_t wrap_buf_clear: 1;
+        const uint32_t reserved_0: 15;
+    } b;
+} RAP_BUF_CR_TypeDef;
+
+
+/* 0x118
+   31:0    R      i2c_version             32'h2403010A
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t i2c_version: 32;
+    } b;
+} I2C_VERSION_TypeDef;
+
+
+/* 0x11C
+   0       R/W    icclk_qactive_man_data  1'h0
+   1       R/W    icclk_qactive_man_enable1'h0
+   2       R/W    pclk_qactive_man_data   1'h0
+   3       R/W    pclk_qactive_man_enable 1'h0
+   15:4    R      reserved_dummy11c_15_4  12'h0
+   16      R/W    pwr_qactive_man_data    1'h0
+   17      R/W    pwr_qactive_man_enable  1'h0
+   31:18   R      reserved_dummy11c_31_18 14'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t icclk_qactive_man_data: 1;
+        uint32_t icclk_qactive_man_enable: 1;
+        uint32_t pclk_qactive_man_data: 1;
+        uint32_t pclk_qactive_man_enable: 1;
+        const uint32_t reserved_1: 12;
+        uint32_t pwr_qactive_man_data: 1;
+        uint32_t pwr_qactive_man_enable: 1;
+        const uint32_t reserved_0: 14;
+    } b;
+} QACTIVE_MANUAL_CTRL_TypeDef;
+
+/*============================================================================*
+ *                          I2C Constants
+ *============================================================================*/
+/** \defgroup I2C         I2C
+  * \brief
+  * \{
+  */
+
+/** \defgroup I2C_Exported_Constants I2C Exported Constants
+  * \brief
+  * \{
+  */
+
+/**
+ * \defgroup    I2C_Clock_Source I2C Clock Source
+ * \{
+ * \ingroup     I2C_Exported_Constants
+ */
+typedef enum
+{
+    I2C_CLOCK_SRC_40M = 0x0,
+} I2CClockSrc_TypeDef;
+
+#define IS_I2C_CLOCK_SRC(CLOCK)     (((CLOCK) == I2C_CLOCK_SRC_40M))
+
+/** End of I2C_Clock_Source
+  * \}
+  */
+
+/**
+ * \defgroup    I2C_Clock_Divider I2C Clock Divider
+ * \{
+ * \ingroup     I2C_Exported_Constants
+ */
+typedef enum
+{
+    I2C_CLOCK_DIV_1 = 0x0,
+    I2C_CLOCK_DIV_2 = 0x1,
+    I2C_CLOCK_DIV_4 = 0x2,
+    I2C_CLOCK_DIV_8 = 0x3,
+    I2C_CLOCK_DIV_16 = 0x4,
+    I2C_CLOCK_DIV_32 = 0x5,
+    I2C_CLOCK_DIV_40 = 0x6,
+    I2C_CLOCK_DIV_64 = 0x7,
+} I2CClockDiv_TypeDef;
+
+#define IS_I2C_CLOCK_DIV(DIV) (((DIV) == I2C_CLOCK_DIV_1) || \
+                               ((DIV) == I2C_CLOCK_DIV_2) || \
+                               ((DIV) == I2C_CLOCK_DIV_4) || \
+                               ((DIV) == I2C_CLOCK_DIV_8) || \
+                               ((DIV) == I2C_CLOCK_DIV_16) || \
+                               ((DIV) == I2C_CLOCK_DIV_32) || \
+                               ((DIV) == I2C_CLOCK_DIV_40) || \
+                               ((DIV) == I2C_CLOCK_DIV_64))
+
+/** End of I2C_Clock_Divider
+  * \}
+  */
+
+/** End of I2C_Exported_Constants
+  * \}
+  */
+
+/** End of I2C
+  * \}
+  */
+
+#ifdef  __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* RTL_I2C_DEF_H */
diff --git a/bee/drivers/i2c/src/device/rtl_common/rtl_i2c.c b/bee/drivers/i2c/src/device/rtl_common/rtl_i2c.c
new file mode 100644
index 00000000..ded7a66a
--- /dev/null
+++ b/bee/drivers/i2c/src/device/rtl_common/rtl_i2c.c
@@ -0,0 +1,1262 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *                           Header Files
+ *============================================================================*/
+#include "rtl_i2c.h"
+#include "rtl_rcc.h"
+#include "timestamp.h"
+
+/*============================================================================*
+ *                           Private Functions
+ *============================================================================*/
+/* I2C Data Cmd Mask */
+#define I2C_CMD_READ_BIT                             (BIT8)
+#define I2C_CMD_STOP_BIT                             (BIT9)
+#define I2C_CMD_RESTART_BIT                          (BIT10)
+
+/* SDA Setup Time */
+#define I2C_SDA_SETUP_TIME_VALUE                     (2)
+
+/* SCL Low/High Period Time */
+#define I2C_SCL_HIGH_PERIOD_COMPENSATE               (7)
+#define I2C_SCL_LOW_PERIOD_COMPENSATE                (1)
+
+#define NS_PER_SECOND                                (1000000000)
+/* I2C SCL High/Low min period according to spec */
+#define I2C_FAST_MODE_PLUS_SCL_LOW_PERIOD_MIN_NS     (500)
+#define I2C_FAST_MODE_PLUS_SCL_HIGH_PERIOD_MIN_NS    (260)
+#define I2C_FAST_MODE_SCL_LOW_PERIOD_MIN_NS          (1300)
+#define I2C_FAST_MODE_SCL_HIGH_PERIOD_MIN_NS         (600)
+#define I2C_STANDARD_MODE_SCL_LOW_PERIOD_MIN_NS      (4700)
+#define I2C_STANDARD_MODE_SCL_HIGH_PERIOD_MIN_NS     (4000)
+/* SDA Hold Time */
+#define I2C_STANDARD_FAST_MODE_SDA_HOLD_TIME_NS      (600)
+#define I2C_FAST_MODE_PLUS_SDA_HOLD_TIME_NS          (300)
+#define I2C_TIMEOUT_SCALE                            (256)
+#define I2C_TIMEOUT_MIN_US                           (20000)
+
+#define ROUNDUP(a, b)                                (((a + b - 1) / b))
+
+/* I2C Abort Check timeout etc */
+uint32_t I2C_TimeOutUs[CHIP_I2C_NUMBER];
+
+static uint32_t I2C_RisingTimeNs;
+extern uint32_t I2C_GetClock(I2C_TypeDef *I2Cx);
+extern uint8_t I2C_GetIndex(I2C_TypeDef *I2Cx);
+
+/*============================================================================*
+ *                           Public Functions
+ *============================================================================*/
+/**
+  * \brief  Deinitializes the I2Cx peripheral registers to their default reset values.
+  * \param  I2Cx: Select the I2C peripheral. \ref I2C_Declaration
+  * \return None
+  */
+void I2C_DeInit(I2C_TypeDef *I2Cx)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+    /*Disable I2C IP*/
+#ifdef I2C0
+    if (I2Cx == I2C0)
+    {
+        RCC_ClockCmd(I2C0_CLOCK, DISABLE);
+        return;
+    }
+#endif
+#ifdef I2C1
+    if (I2Cx == I2C1)
+    {
+        RCC_ClockCmd(I2C1_CLOCK, DISABLE);
+        return;
+    }
+#endif
+#ifdef I2C2
+    if (I2Cx == I2C2)
+    {
+        RCC_ClockCmd(I2C2_CLOCK, DISABLE);
+        return;
+    }
+#endif
+#ifdef I2C3
+    if (I2Cx == I2C3)
+    {
+        RCC_ClockCmd(I2C3_CLOCK, DISABLE);
+        return;
+    }
+#endif
+}
+
+/**
+  * \brief  Initializes the I2Cx peripheral according to the specified
+  *         parameters in the I2C_InitStruct.
+  * \param  I2Cx: Select the I2C peripheral. \ref I2C_Declaration
+  * \param  I2C_InitStruct: Pointer to a I2C_InitTypeDef structure that
+  *         contains the configuration information for the specified I2C peripheral.
+  * \return None
+  */
+void I2C_Init(I2C_TypeDef *I2Cx, I2C_InitTypeDef *I2C_InitStruct)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+    assert_param(IS_I2C_CLOCK_SPEED(I2C_InitStruct->I2C_ClockSpeed));
+
+    /* Disable I2C device before change configuration */
+    IC_ENABLE_TypeDef i2c_0x6c = {.d32 = I2Cx->IC_ENABLE};
+    i2c_0x6c.b.ic_enable = 0x0;
+    I2Cx->IC_ENABLE = i2c_0x6c.d32;
+
+    /* Config sda tx hold time in different clock speed */
+    uint8_t sda_tx_hold = 0;
+    uint32_t I2CSrcClk = I2C_GetClock(I2Cx);
+    uint32_t i2c_source_clock_ns = NS_PER_SECOND / I2CSrcClk;
+
+    if ((I2CSrcClk == 40000000) && (I2C_InitStruct->I2C_ClockSpeed > 400000))
+    {
+        sda_tx_hold = I2C_FAST_MODE_PLUS_SDA_HOLD_TIME_NS / i2c_source_clock_ns;
+    }
+    else
+    {
+        sda_tx_hold = (I2C_STANDARD_FAST_MODE_SDA_HOLD_TIME_NS / i2c_source_clock_ns == 0) ? 1 :
+                      (I2C_STANDARD_FAST_MODE_SDA_HOLD_TIME_NS / i2c_source_clock_ns);
+    }
+
+    /* ------------------------------ Initialize I2C device ------------------------------*/
+    if (I2C_DEVICE_MODE_MASTER == I2C_InitStruct->I2C_DeviceMode)
+    {
+        /* Configure I2C device mode which can be selected for master or slave */
+        IC_CON_TypeDef i2c_0x00 = {.d32 = I2Cx->IC_CON};
+        i2c_0x00.b.master_mode = 0x1;
+        i2c_0x00.b.ic_slave_disable = 0x1;
+        i2c_0x00.b.ic_restart_en = 0x1;
+        I2Cx->IC_CON = i2c_0x00.d32;
+
+        /* Set target address */
+        IC_TAR_TypeDef i2c_0x04 = {.d32 = I2Cx->IC_TAR};
+        i2c_0x04.b.ic_10bitaddr_master = I2C_InitStruct->I2C_AddressMode;
+        i2c_0x04.b.ic_tar = I2C_InitStruct->I2C_SlaveAddress;
+        I2Cx->IC_TAR = i2c_0x04.d32;
+
+        /* Set SDA hold time in master mode */
+        IC_SDA_HOLD_TypeDef i2c_0x7c = {.d32 = I2Cx->IC_SDA_HOLD};
+        i2c_0x7c.b.ic_sda_tx_hold = sda_tx_hold;
+        i2c_0x7c.b.ic_sda_rx_hold = 0x1;
+        I2Cx->IC_SDA_HOLD = i2c_0x7c.d32;
+
+        I2C_RisingTimeNs = I2C_InitStruct->I2C_RisingTimeNs;
+        /* Configure I2C speed */
+        I2C_SetClockSpeed(I2Cx, I2C_InitStruct->I2C_ClockSpeed);
+    }
+    else
+    {
+        /* Set to slave mode */
+        IC_CON_TypeDef i2c_0x00 = {.d32 = I2Cx->IC_CON};
+        i2c_0x00.b.master_mode = 0x0;
+        i2c_0x00.b.ic_10bitaddr_slave = I2C_InitStruct->I2C_AddressMode;
+        i2c_0x00.b.ic_slave_disable = 0x0;
+        I2Cx->IC_CON = i2c_0x00.d32;
+
+        /* Set slave address */
+        IC_SAR_TypeDef i2c_0x08 = {.d32 = I2Cx->IC_SAR};
+        i2c_0x08.b.ic_sar = I2C_InitStruct->I2C_SlaveAddress;
+        I2Cx->IC_SAR = i2c_0x08.d32;
+
+        /* Set Ack in slave mode */
+        IC_ACK_GENERAL_CALL_TypeDef i2c_0x98 = {.d32 = I2Cx->IC_ACK_GENERAL_CALL};
+        i2c_0x98.b.ack_gen_call &= I2C_InitStruct->I2C_Ack;
+        I2Cx->IC_ACK_GENERAL_CALL = i2c_0x98.d32;
+
+        /* Set SDA hold time in slave mode */
+        IC_SDA_HOLD_TypeDef i2c_0x7c = {.d32 = I2Cx->IC_SDA_HOLD};
+        i2c_0x7c.b.ic_sda_tx_hold = sda_tx_hold;
+        i2c_0x7c.b.ic_sda_rx_hold = 0x08;
+        I2Cx->IC_SDA_HOLD = i2c_0x7c.d32;
+
+        /* Set SDA setup time delay only in slave transmitter mode(greater than 2) ,delay time:[(IC_SDA_SETUP - 1) * (ic_clk_period)]*/
+        IC_SDA_SETUP_TypeDef i2c_0x94 = {.d32 = I2Cx->IC_SDA_SETUP};
+        i2c_0x94.b.sda_setup = I2C_SDA_SETUP_TIME_VALUE;
+        I2Cx->IC_SDA_SETUP = i2c_0x94.d32;
+    }
+
+    /* Set Tx empty level */
+    IC_TX_TL_TypeDef i2c_0x3c = {.d32 = I2Cx->IC_TX_TL};
+    i2c_0x3c.b.tx_tl = I2C_InitStruct->I2C_TxThresholdLevel;
+    I2Cx->IC_TX_TL = i2c_0x3c.d32;
+
+    /*set Rx full level*/
+    IC_RX_TL_TypeDef i2c_0x40 = {.d32 = I2Cx->IC_RX_TL};
+    i2c_0x40.b.rx_tl = I2C_InitStruct->I2C_RxThresholdLevel;
+    I2Cx->IC_RX_TL = i2c_0x40.d32;
+
+    /* Config I2C dma mode */
+    IC_DMA_CR_TypeDef i2c_0x88 = {.d32 = I2Cx->IC_DMA_CR};
+    i2c_0x88.b.rdmae = I2C_InitStruct->I2C_RxDMAEn;
+    i2c_0x88.b.tdmae = I2C_InitStruct->I2C_TxDMAEn;
+    I2Cx->IC_DMA_CR = i2c_0x88.d32;
+
+    /* Config I2C waterlevel */
+    IC_DMA_TDLR_TypeDef i2c_0x8c = {.d32 = I2Cx->IC_DMA_TDLR};
+    IC_DMA_RDLR_TypeDef i2c_0x90 = {.d32 = I2Cx->IC_DMA_RDLR};
+    i2c_0x8c.b.dmatdl = I2C_InitStruct->I2C_TxWaterlevel;
+    i2c_0x90.b.dmardl = I2C_InitStruct->I2C_RxWaterlevel;
+    I2Cx->IC_DMA_TDLR = i2c_0x8c.d32;
+    I2Cx->IC_DMA_RDLR = i2c_0x90.d32;
+
+    /* Mask all interrupt */
+    I2Cx->IC_INTR_MASK = 0x0;
+
+    uint8_t index = I2C_GetIndex(I2Cx);
+    uint64_t timeout_us = (uint64_t)9000000 * I2C_TIMEOUT_SCALE / (I2C_InitStruct->I2C_ClockSpeed);
+    if (timeout_us < I2C_TIMEOUT_MIN_US)
+    {
+        timeout_us = I2C_TIMEOUT_MIN_US;
+    }
+    I2C_TimeOutUs[index] = (uint32_t)timeout_us;
+}
+
+/**
+  * \brief  Fills each I2C_InitStruct member with its default value.
+  * \param  I2C_InitStruct : pointer to a I2C_InitTypeDef structure which will be initialized.
+  * \return None
+  */
+void I2C_StructInit(I2C_InitTypeDef *I2C_InitStruct)
+{
+    /* I2C source clock is 40MHz, depending on clock divider */
+    I2C_InitStruct->I2C_Clock             = 40000000;
+    /* I2C SCK freqency is 400KHz */
+    I2C_InitStruct->I2C_ClockSpeed        = 400000;
+    /* Master mode */
+    I2C_InitStruct->I2C_DeviceMode        = I2C_DEVICE_MODE_MASTER;
+    /* 7-bit address mode */
+    I2C_InitStruct->I2C_AddressMode       = I2C_ADDRESS_MODE_7BIT;
+    /* Set slave address */
+    I2C_InitStruct->I2C_SlaveAddress      = 0;
+    /* Enable acknowledge in slave mode */
+    I2C_InitStruct->I2C_Ack               = ENABLE;
+    /* Tx fifo depth: 24 * 8bits */
+    I2C_InitStruct->I2C_TxThresholdLevel  = 0;
+    /* Rx fifo depth: 24 * 8bits */
+    I2C_InitStruct->I2C_RxThresholdLevel  = 0;
+    /* Disable dma */
+    I2C_InitStruct->I2C_TxDMAEn           = DISABLE;
+    I2C_InitStruct->I2C_RxDMAEn           = DISABLE;
+    /* I2C Tx waterlevel, should be less than fifo threshold.
+       The best value is I2C FIFO Depth - DMA Msize */
+    I2C_InitStruct->I2C_TxWaterlevel      = 23;
+    /* I2C Rx waterlevel, should be less than fifo threshold.
+       The best value is DMA Msize */
+    I2C_InitStruct->I2C_RxWaterlevel      = 1;
+    /* Specify I2C scl rising time with 2.2K ohm pull up resistor, the unit is ns*/
+    I2C_InitStruct->I2C_RisingTimeNs     = 50;
+
+}
+
+/**
+  * \brief  Enables or disables the specified I2C peripheral.
+  * \param  I2Cx: Select the I2C peripheral. \ref I2C_Declaration
+  * \param  NewState: New state of the I2Cx peripheral.
+  *         This parameter can be: ENABLE or DISABLE.
+  * \return None
+  */
+void I2C_Cmd(I2C_TypeDef *I2Cx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    /* Enable or disable the selected I2C peripheral */
+    IC_ENABLE_TypeDef i2c_0x6c = {.d32 = I2Cx->IC_ENABLE};
+    i2c_0x6c.b.ic_enable = NewState;
+    I2Cx->IC_ENABLE = i2c_0x6c.d32;
+}
+
+
+/**
+  * \brief  Checks whether the last I2Cx abort status.
+  * \param  I2Cx: Select the I2C peripheral. \ref I2C_Declaration
+  * \return I2C_Status: The status of I2Cx. \ref I2C_Status
+  */
+I2C_Status I2C_CheckAbortStatus(I2C_TypeDef *I2Cx)
+{
+    uint32_t abort_status = 0;
+
+    /* Check the parameters */
+    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+    /* Get abort status */
+    abort_status = I2Cx->IC_TX_ABRT_SOURCE;
+
+    if (abort_status & MS_ALL_ABORT)
+    {
+        /* Clear abort status */
+        (void)I2Cx->IC_CLR_TX_ABRT;
+
+        /* Check abort type */
+        if (abort_status & ABRT_TXDATA_NOACK)
+        {
+            return I2C_ABRT_TXDATA_NOACK;
+        }
+
+        if (abort_status & ABRT_7B_ADDR_NOACK)
+        {
+            return I2C_ABRT_7B_ADDR_NOACK;
+        }
+
+        if (abort_status & ARB_LOST)
+        {
+            return I2C_ARB_LOST;
+        }
+
+        if (abort_status & ABRT_MASTER_DIS)
+        {
+            return I2C_ABRT_MASTER_DIS;
+        }
+
+        if (abort_status & ABRT_10ADDR1_NOACK)
+        {
+            return I2C_ABRT_10ADDR1_NOACK;
+        }
+
+        if (abort_status & ABRT_10ADDR2_NOACK)
+        {
+            return I2C_ABRT_10ADDR2_NOACK;
+        }
+    }
+
+    return I2C_SUCCESS;
+}
+
+/**
+  * \brief Mask the specified I2C interrupt.
+  * \param  I2Cx: Select the I2C peripheral. \ref I2C_Declaration
+  * \param  I2C_INT: This parameter can be one of the following values:
+  *         \arg I2C_INT_MST_ON_HOLD: Indicates whether a master is holding the bus.
+  *         \arg I2C_INT_GEN_CALL: Set only when a General Call address is received and it is acknowledged.
+  *         \arg I2C_INT_START_DET: Indicates whether a START or RESTART condition has occurred on the I2C
+  *              interface regardless of whether I2C is operating in slave or master mode.
+  *         \arg I2C_INT_STOP_DET: Indicates whether a STOP condition has occurred on the I2C interface regardless
+  *              of whether I2C is operating in slave or master mode
+  *         \arg I2C_INT_ACTIVITY: This bit captures I2C activity and stays set until it is cleared.
+  *         \arg I2C_INT_RX_DONE: When the I2C is acting as a slave-transmitter, this bit is set to 1 if the
+  *              master does not acknowledge a transmitted byte. This occurs on the last byte of
+  *              the transmission, indicating that the transmission is done.
+  *         \arg I2C_INT_TX_ABRT: This bit indicates if I2C as an I2C transmitter, is unable to complete the
+  *              intended actions on the contents of the transmit FIFO.
+  *         \arg I2C_INT_RD_REQ: This bit is set to 1 when acting as a slave and another I2C master
+  *              is attempting to read data.
+  *         \arg I2C_INT_TX_EMPTY: This bit is set to 1 when the transmit buffer is at or below the threshold value set
+  *              in the IC_TX_TL register.
+  *         \arg I2C_INT_TX_OVER: Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH and
+  *              the processor attempts to issue another I2C command.
+  *         \arg I2C_INT_RX_FULL: Set when the receive buffer reaches or goes above the RX_TL threshold in the
+  *              IC_RX_TL register
+  *         \arg I2C_INT_RX_OVER: Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and an
+  *              additional byte is received from an external I2C device.
+  *         \arg I2C_INT_RX_UNDER: Set if the processor attempts to read the receive buffer when it is empty by reading.
+  * \return None.
+  */
+void I2C_INTConfig(I2C_TypeDef *I2Cx, uint16_t I2C_INT, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+    assert_param(I2C_GET_INT(I2C_INT));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (NewState != DISABLE)
+    {
+        /* Enable the selected I2C interrupts */
+        I2Cx->IC_INTR_MASK |= I2C_INT;
+    }
+    else
+    {
+        /* Disable the selected I2C interrupts */
+        I2Cx->IC_INTR_MASK &= (uint16_t)~I2C_INT;
+    }
+}
+
+/**
+  * \brief clear the specified I2C interrupt.
+  * \param  I2Cx: Select the I2C peripheral. \ref I2C_Declaration
+  * \param  I2C_INT: This parameter can be one of the following values:
+  *         \arg I2C_INT_GEN_CALL: Set only when a General Call address is received and it is acknowledged.
+  *         \arg I2C_INT_START_DET: Indicates whether a START or RESTART condition has occurred on the I2C
+  *              interface regardless of whether I2C is operating in slave or master mode.
+  *         \arg I2C_INT_STOP_DET: Indicates whether a STOP condition has occurred on the I2C interface regardless
+  *              of whether I2C is operating in slave or master mode
+  *         \arg I2C_INT_ACTIVITY: This bit captures I2C activity and stays set until it is cleared.
+  *         \arg I2C_INT_RX_DONE: When the I2C is acting as a slave-transmitter, this bit is set to 1 if the
+  *              master does not acknowledge a transmitted byte. This occurs on the last byte of
+  *              the transmission, indicating that the transmission is done.
+  *         \arg I2C_INT_TX_ABRT: This bit indicates if I2C as an I2C transmitter, is unable to complete the
+  *              intended actions on the contents of the transmit FIFO.
+  *         \arg I2C_INT_RD_REQ: This bit is set to 1 when acting as a slave and another I2C master
+  *              is attempting to read data.
+  *         \arg I2C_INT_TX_EMPTY: This bit is set to 1 when the transmit buffer is at or below the threshold value set
+  *              in the IC_TX_TL register.
+  *         \arg I2C_INT_TX_OVER: Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH and
+  *              the processor attempts to issue another I2C command.
+  *         \arg I2C_INT_RX_FULL: Set when the receive buffer reaches or goes above the RX_TL threshold in the
+  *              IC_RX_TL register
+  *         \arg I2C_INT_RX_OVER: Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and an
+  *              additional byte is received from an external I2C device.
+  *         \arg I2C_INT_RX_UNDER: Set if the processor attempts to read the receive buffer when it is empty by reading.
+  * \return None.
+  */
+void I2C_ClearINTPendingBit(I2C_TypeDef *I2Cx, uint16_t I2C_IT)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+    assert_param(I2C_GET_INT(I2C_IT));
+
+    switch (I2C_IT)
+    {
+    case I2C_INT_RX_UNDER:
+        {
+            (void)I2Cx->IC_CLR_RX_UNDER;
+            break;
+        }
+    case I2C_INT_RX_OVER:
+        {
+            (void)I2Cx->IC_CLR_RX_OVER;
+            break;
+        }
+    case I2C_INT_TX_OVER:
+        {
+            (void)I2Cx->IC_CLR_TX_OVER;
+            break;
+        }
+    case I2C_INT_RD_REQ:
+        {
+            (void)I2Cx->IC_CLR_RD_REQ;
+            break;
+        }
+    case I2C_INT_TX_ABRT:
+        {
+            (void)I2Cx->IC_CLR_TX_ABRT;
+            break;
+        }
+    case I2C_INT_RX_DONE:
+        {
+            (void)I2Cx->IC_CLR_RX_DONE;
+            break;
+        }
+    case I2C_INT_ACTIVITY:
+        {
+            (void)I2Cx->IC_CLR_ACTIVITY;
+            break;
+        }
+    case I2C_INT_STOP_DET:
+        {
+            (void)I2Cx->IC_CLR_STOP_DET;
+            break;
+        }
+    case I2C_INT_START_DET:
+        {
+            (void)I2Cx->IC_CLR_START_DET;
+            break;
+        }
+    case I2C_INT_GEN_CALL:
+        {
+            (void)I2Cx->IC_CLR_GEN_CALL;
+            break;
+        }
+    default:
+        {
+            break;
+        }
+    }
+}
+
+I2C_Status I2C_WaitForFIFO(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG)
+{
+    uint8_t index = I2C_GetIndex(I2Cx);
+    uint32_t time_out_us = I2C_TimeOutUs[index];
+    uint32_t start_timestamp_us = 0;
+    uint32_t now_timestamp_us = 0;
+
+    /* Wait until the FIFO condition selected by I2C_FLAG becomes true:
+     * - TX: writable (TX FIFO Not Full, space available)
+     * - RX: readable (RX FIFO Not Empty, data available)
+     */
+    start_timestamp_us = timestamp_get_us();
+    while ((I2Cx->IC_STATUS & I2C_FLAG) == 0)
+    {
+        I2C_Status status = I2C_CheckAbortStatus(I2Cx);
+        if (status != I2C_SUCCESS)
+        {
+            return status;
+        }
+
+        now_timestamp_us = timestamp_get_us();
+        if ((uint32_t)(now_timestamp_us - start_timestamp_us) >= time_out_us)
+        {
+            return I2C_ERR_TIMEOUT;
+        }
+    }
+
+    return I2C_CheckAbortStatus(I2Cx);
+}
+
+I2C_Status I2C_WaitTXIdle(I2C_TypeDef *I2Cx)
+{
+    uint8_t index = I2C_GetIndex(I2Cx);
+    uint32_t time_out_us = I2C_TimeOutUs[index];
+    uint32_t start_timestamp_us = 0;
+    uint32_t now_timestamp_us = 0;
+
+    /* Wait until the transmit is fully completed:
+     * - Bus becomes idle (ACTIVITY == 0)
+     * - TX FIFO is empty (TFE == 1)
+     */
+    start_timestamp_us = timestamp_get_us();
+    while (((I2Cx->IC_STATUS & I2C_FLAG_ACTIVITY) != 0) ||
+           ((I2Cx->IC_STATUS & I2C_FLAG_TFE) == 0))
+    {
+        I2C_Status status = I2C_CheckAbortStatus(I2Cx);
+        if (status != I2C_SUCCESS)
+        {
+            return status;
+        }
+
+        now_timestamp_us = timestamp_get_us();
+        if ((uint32_t)(now_timestamp_us - start_timestamp_us) >= time_out_us)
+        {
+            return I2C_ERR_TIMEOUT;
+        }
+    }
+
+    return I2C_SUCCESS;
+}
+
+
+/**
+  * \brief  Send data in master mode through the I2Cx peripheral.
+  * \param  I2Cx: Select the I2C peripheral. \ref I2C_Declaration
+  * \param  pBuf: Byte to be transmitted.
+  * \param  len: Data length to send.
+  * \return I2C_Status: The status of I2Cx. \ref I2C_Status
+  */
+I2C_Status I2C_MasterWrite(I2C_TypeDef *I2Cx, uint8_t *pBuf, uint16_t len)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+    I2C_Status status = I2C_SUCCESS;
+
+    for (uint16_t i = 0; i < len; i++)
+    {
+        uint32_t cmd = *pBuf++;
+        if (i == (len - 1))
+        {
+            cmd |= I2C_CMD_STOP_BIT;
+        }
+        I2Cx->IC_DATA_CMD = cmd;
+
+        status = I2C_WaitForFIFO(I2Cx, I2C_FLAG_TFNF);
+        if (status != I2C_SUCCESS)
+        {
+            return status;
+        }
+    }
+
+    return I2C_WaitTXIdle(I2Cx);
+}
+
+/**
+  * \brief  Send device write data in master mode through the I2Cx peripheral.
+  * \param  I2Cx: Select the I2C peripheral. \ref I2C_Declaration
+  * \param  Data: Byte to be transmitted..
+  * \return None
+  */
+I2C_Status I2C_MasterWriteDevice(I2C_TypeDef *I2Cx, uint8_t *pBuf, uint16_t len, uint8_t *pbuf2,
+                                 uint32_t len2)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+    I2C_Status status = I2C_SUCCESS;
+
+    /* Write in the DR register the data to be sent */
+    for (uint16_t i = 0; i < len; i++)
+    {
+        I2Cx->IC_DATA_CMD = *pBuf++;
+
+        status = I2C_WaitForFIFO(I2Cx, I2C_FLAG_TFNF);
+        if (status != I2C_SUCCESS)
+        {
+            return status;
+        }
+    }
+
+    for (uint16_t i = 0; i < len2; i++)
+    {
+        uint32_t cmd = *pbuf2++;
+        if (i == (len2 - 1))
+        {
+            cmd |= I2C_CMD_STOP_BIT;
+        }
+        I2Cx->IC_DATA_CMD = cmd;
+
+        status = I2C_WaitForFIFO(I2Cx, I2C_FLAG_TFNF);
+        if (status != I2C_SUCCESS)
+        {
+            return status;
+        }
+    }
+
+    return I2C_WaitTXIdle(I2Cx);
+}
+
+/**
+  * \brief  Read data in master mode through the I2Cx peripheral.
+  * \param  I2Cx: Select the I2C peripheral. \ref I2C_Declaration
+  * \param  pBuf: Data buffer to receive data.
+  * \param  len: Read data length.
+  * \return I2C_Status: The status of I2Cx. \ref I2C_Status
+  */
+I2C_Status I2C_MasterRead(I2C_TypeDef *I2Cx, uint8_t *pBuf, uint16_t len)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+    I2C_Status status = I2C_SUCCESS;
+
+    if (len == 0)
+    {
+        return status;
+    }
+
+    /* Issue the first read cmd. If only one byte is requested, append STOP immediately. */
+    uint32_t cmd = 0x0 | I2C_CMD_READ_BIT;
+    if (len == 1)
+    {
+        cmd |= I2C_CMD_STOP_BIT;
+    }
+    I2Cx->IC_DATA_CMD = cmd;
+
+    for (uint16_t i = 1; i < len; i++)
+    {
+        /* Issue the remaining read cmd. */
+        cmd = 0x0 | I2C_CMD_READ_BIT;
+        if (i == (len - 1))
+        {
+            cmd |= I2C_CMD_STOP_BIT;
+        }
+        I2Cx->IC_DATA_CMD = cmd;
+
+        /* Read byte produced by the read. */
+        status = I2C_WaitForFIFO(I2Cx, I2C_FLAG_RFNE);
+        if (status != I2C_SUCCESS)
+        {
+            return status;
+        }
+        *pBuf++ = (uint8_t)I2Cx->IC_DATA_CMD;
+    }
+
+    /* Read the final byte produced by the last command. */
+    status = I2C_WaitForFIFO(I2Cx, I2C_FLAG_RFNE);
+    if (status != I2C_SUCCESS)
+    {
+        return status;
+    }
+    *pBuf = (uint8_t)I2Cx->IC_DATA_CMD;
+
+    return status;
+}
+
+/**
+  * \brief  Sends data and read data in master mode through the I2Cx peripheral.Attention:Read data with time out mechanism.
+  * \param  I2Cx: Select the I2C peripheral. \ref I2C_Declaration
+  * \param  pWriteBuf: Data buffer to send before read.
+  * \param  Writelen: Send data length.
+  * \param  pReadBuf: Data buffer to receive.
+  * \param  Readlen: Receive data length.
+  * \return I2C_Status: The status of I2Cx. \ref I2C_Status
+  */
+I2C_Status I2C_RepeatRead(I2C_TypeDef *I2Cx, uint8_t *pWriteBuf, uint16_t Writelen,
+                          uint8_t *pReadBuf, uint16_t Readlen)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+    I2C_Status status = I2C_SUCCESS;
+
+    for (uint16_t i = 0; i < Writelen; i++)
+    {
+        I2Cx->IC_DATA_CMD = *pWriteBuf++;
+
+        status = I2C_WaitForFIFO(I2Cx, I2C_FLAG_TFNF);
+        if (status != I2C_SUCCESS)
+        {
+            return status;
+        }
+    }
+
+    for (uint16_t i = 0; i < Readlen; i++)
+    {
+        /* Issue the read cmd. */
+        uint32_t cmd = 0x0 | I2C_CMD_READ_BIT;
+        if (i == (Readlen - 1))
+        {
+            cmd |= I2C_CMD_STOP_BIT;
+        }
+        I2Cx->IC_DATA_CMD = cmd;
+
+        /* Read byte produced by the read. */
+        status = I2C_WaitForFIFO(I2Cx, I2C_FLAG_RFNE);
+        if (status != I2C_SUCCESS)
+        {
+            return status;
+        }
+        *pReadBuf++ = (uint8_t)I2Cx->IC_DATA_CMD;
+    }
+
+
+    return status;
+}
+
+/**
+ * \brief   Set slave device address.
+ * \param   I2Cx: Select the I2C peripheral. \ref I2C_Declaration
+ * \param   Address: Specifies the slave address which will be transmitte.
+ * \return  None.
+ */
+void I2C_SetSlaveAddress(I2C_TypeDef *I2Cx, uint16_t Address)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+    /* Configure new target address */
+    IC_TAR_TypeDef i2c_0x04 = {.d32 = I2Cx->IC_TAR};
+    i2c_0x04.b.ic_tar = Address;
+    I2Cx->IC_TAR = i2c_0x04.d32;
+}
+
+/**
+ * \brief   Write command through the I2Cx peripheral.
+ * \param   I2Cx: Select the I2C peripheral. \ref I2C_Declaration
+ * \param   command: Command of write or read.
+ *          \arg I2C_READ_CMD: Read command. Data which want to transmit can be 0 in this situation.
+ *          \arg I2C_WRITE_CMD: Write command.
+ * \param   data: Data which to be transmitted.
+ * \param   StopState: Whether send stop signal.
+ *          \arg ENABLE: Send stop signal.
+ *          \arg DISABLE: Do not send stop signal.
+ * \return  None.
+ */
+void I2C_SendCmd(I2C_TypeDef *I2Cx, I2CSendCommend_TypeDef command, uint8_t data,
+                 FunctionalState StopState)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+    assert_param(IS_I2C_CMD(command));
+    assert_param(IS_I2C_STOP(StopState));
+
+    IC_DATA_CMD_TypeDef i2c_0x10 = {.d32 = 0};
+    i2c_0x10.d32 = 0;
+    i2c_0x10.b.cmd = command;
+    i2c_0x10.b.stop = StopState;
+    i2c_0x10.b.dat = data;
+    I2Cx->IC_DATA_CMD = i2c_0x10.d32;
+}
+
+/**
+ * \brief   Received data by the I2Cx peripheral.
+ * \param   I2Cx: Select the I2C peripheral. \ref I2C_Declaration
+ * \return  Return the most recent received data.
+ */
+uint8_t I2C_ReceiveData(I2C_TypeDef *I2Cx)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+    /* Return the data in the DR register */
+    return (uint8_t)I2Cx->IC_DATA_CMD;
+}
+
+/**
+ * \brief   Get data length in Rx FIFO of the I2Cx peripheral.
+ * \param   I2Cx: Select the I2C peripheral. \ref I2C_Declaration
+ * \return  Current data number in Rx FIFO.
+ */
+uint8_t I2C_GetRxFIFOLen(I2C_TypeDef *I2Cx)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+    return (uint8_t)I2Cx->IC_RXFLR;
+}
+
+/**
+ * \brief   Get data length in Tx FIFO of the I2Cx peripheral.
+ * \param   I2Cx: Select the I2C peripheral. \ref I2C_Declaration
+ * \return  Current data number in Tx FIFO.
+ */
+uint8_t I2C_GetTxFIFOLen(I2C_TypeDef *I2Cx)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+    return (uint8_t)I2Cx->IC_TXFLR;
+}
+
+/**
+ * \brief   Clear all I2C interrupt.
+ * \param   I2Cx: Select the I2C peripheral. \ref I2C_Declaration
+ * \return  None.
+ */
+void I2C_ClearAllINT(I2C_TypeDef *I2Cx)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+    (void)I2Cx->IC_CLR_INTR;
+}
+
+/**
+ * \brief   Check whether the specified I2C flag is set.
+ * \param   I2Cx: Select the I2C peripheral. \ref I2C_Declaration
+ * \param   I2C_FLAG: Specifies the flag to check.
+ *          This parameter can be one of the following values:
+ *          \arg I2C_FLAG_SLV_HOLD_RX_FIFO_FULL: The BUS Hold in Slave mode due to the Rx FIFO being Full and an additional byte being received.
+ *          \arg I2C_FLAG_SLV_HOLD_TX_FIFO_EMPTY: The BUS Hold in Slave mode for the Read request when the Tx FIFO is empty.
+ *          \arg I2C_FLAG_MST_HOLD_RX_FIFO_FULL: The BUS Hold in Master mode due to Rx FIFO is full and additional byte has been received.
+ *          \arg I2C_FLAG_MST_HOLD_TX_FIFO_EMPTY: The BUS hold when the master holds the bus because of the Tx FIFO being empty.
+ *          \arg I2C_FLAG_SLV_ACTIVITY: Slave FSM activity status.
+ *          \arg I2C_FLAG_MST_ACTIVITY: Master FSM activity status.
+ *          \arg I2C_FLAG_RFF: Receive FIFO completely full.
+ *          \arg I2C_FLAG_RFNE: Receive FIFO not empty.
+ *          \arg I2C_FLAG_TFE: Transmit FIFO completely empty.
+ *          \arg I2C_FLAG_TFNF: Transmit FIFO not full.
+ *          \arg I2C_FLAG_ACTIVITY: I2C activity status.
+ */
+FlagStatus I2C_GetFlagState(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG)
+{
+    FlagStatus bit_status = RESET;
+
+    /* Check the parameters */
+    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+    assert_param(IS_I2C_GET_FLAG(I2C_FLAG));
+
+    if ((I2Cx->IC_STATUS & I2C_FLAG) != (uint32_t)RESET)
+    {
+        /* I2C_FLAG is set */
+        bit_status = SET;
+    }
+
+    /* Return the I2C_FLAG status */
+    return  bit_status;
+}
+
+/**
+ * \brief   Check whether the last I2Cx event is equal to the one passed as parameter.
+ * \param   I2Cx: Select the I2C peripheral. \ref I2C_Declaration
+ * \param   I2C_EVENT: specifies the event to be checked about I2C Transmit Abort Status Register.
+ *          This parameter can be one of the following values:
+ *          \arg ABRT_SLVRD_INTX: When the processor side responds to a slave mode request for data to be transmitted to a remote master and user send read command.
+ *          \arg ABRT_SLV_ARBLOST: Slave lost the bus while transmitting data to a remote master.
+ *          \arg ABRT_SLVFLUSH_TXFIFO: Slave has received a read command and some data exists in the TX FIFO so the slave issues a TX_ABRT interrupt to flush old data in TX FIFO.
+ *          \arg ARB_LOST: Master has lost arbitration or the slave transmitter has lost arbitration.
+ *          \arg ABRT_MASTER_DIS: User tries to initiate a Master operation with the Master mode disabled
+ *          \arg ABRT_10B_RD_NORSTRT: The restart is disabled and the master sends a read command in 10-bit addressing mode.
+ *          \arg ABRT_SBYTE_NORSTRT: The restart is disabled and the user is trying to send a START Byte.
+ *          \arg ABRT_HS_NORSTRT: The restart is disabled and the user is trying to use the master to transfer data in High Speed mode.
+ *          \arg ABRT_SBYTE_ACKDET: Master has sent a START Byte and the START Byte was acknowledged (wrong behavior).
+ *          \arg ABRT_HS_ACKDET: Master is in High Speed mode and the High Speed Master code was acknowledged (wrong behavior).
+ *          \arg ABRT_GCALL_READ: Sent a General Call but the user programmed the byte following the General Call to be a read from the bus.
+ *          \arg ABRT_GCALL_NOACK: Sent a General Call and no slave on the bus acknowledged the General Call.
+ *          \arg ABRT_TXDATA_NOACK: Master sent data byte(s) following the address, it did not receive an acknowledge from the remote slave.
+ *          \arg ABRT_10ADDR2_NOACK: Master is in 10-bit address mode and the second address byte of the 10-bit address was not acknowledged by any slave.
+ *          \arg ABRT_10ADDR1_NOACK: Master is in 10-bit address mode and the first 10-bit address byte was not acknowledged by any slave.
+ *          \arg ABRT_7B_ADDR_NOACK: Master is in 7-bit addressing mode and th address sent was not acknowledged by any slave.
+ * \return  An ErrorStatus enumeration value.
+ *          \retval  SUCCESS: Last event is equal to the I2C_EVENT.
+ *          \retval  ERROR: Last event is different from the I2C_EVENT.
+ */
+FlagStatus I2C_CheckEvent(I2C_TypeDef *I2Cx, uint32_t I2C_EVENT)
+{
+    FlagStatus bit_status = RESET;
+
+    /* Check the parameters */
+    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+    assert_param(IS_I2C_EVENT(I2C_EVENT));
+
+    if ((I2Cx->IC_TX_ABRT_SOURCE & I2C_EVENT) != (uint32_t)RESET)
+    {
+
+        bit_status = SET;
+    }
+
+    /* Return the I2C event status */
+    return  bit_status;
+}
+
+/**
+ * \brief   Get the specified I2C interrupt status.
+ * \param   I2Cx: Select the I2C peripheral. \ref I2C_Declaration
+ * \param   I2C_IT: This parameter can be one of the following values:
+ *          \arg I2C_INT_MST_ON_HOLD: Indicates whether a master is holding the bus.
+ *          \arg I2C_INT_GEN_CALL: Set only when a General Call address is received and it is acknowledged.
+ *          \arg I2C_INT_START_DET: Indicates whether a START or RESTART condition has occurred on the I2C
+ *               interface regardless of whether DW_apb_i2c is operating in slave or master mode.
+ *          \arg I2C_INT_STOP_DET: Indicates whether a STOP condition has occurred on the I2C interface regardless
+ *               of whether DW_apb_i2c is operating in slave or master mode
+ *          \arg I2C_INT_ACTIVITY: This bit captures DW_apb_i2c activity and stays set until it is cleared.
+ *          \arg I2C_INT_RX_DONE: When the DW_apb_i2c is acting as a slave-transmitter, this bit is set to 1 if the
+ *               master does not acknowledge a transmitted byte. This occurs on the last byte of
+ *               the transmission, indicating that the transmission is done.
+ *          \arg I2C_INT_TX_ABRT: This bit indicates if DW_apb_i2c, as an I2C transmitter, is unable to complete the
+ *               intended actions on the contents of the transmit FIFO.
+ *          \arg I2C_INT_RD_REQ: This bit is set to 1 when acting as a slave and another I2C master
+ *               is attempting to read data.
+ *          \arg I2C_INT_TX_EMPTY: This bit is set to 1 when the transmit buffer is at or below the threshold value set
+ *               in the IC_TX_TL register.
+ *          \arg I2C_INT_TX_OVER: Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH and
+ *               the processor attempts to issue another I2C command.
+ *          \arg I2C_INT_RX_FULL: Set when the receive buffer reaches or goes above the RX_TL threshold in the
+ *               IC_RX_TL register
+ *          \arg I2C_INT_RX_OVER: Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and an
+ *               additional byte is received from an external I2C device.
+ *          \arg I2C_INT_RX_UNDER: Set if the processor attempts to read the receive buffer when it is empty by reading.
+ * \return  The new state of I2C_IT (SET or RESET).
+ */
+ITStatus I2C_GetINTStatus(I2C_TypeDef *I2Cx, uint32_t I2C_IT)
+{
+    ITStatus bit_status = RESET;
+
+    /* Check the parameters */
+    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+    assert_param(I2C_GET_INT(I2C_IT));
+
+    if ((I2Cx->IC_INTR_STAT & I2C_IT) != (uint32_t)RESET)
+    {
+        bit_status = SET;
+    }
+
+    /* Return the I2C_IT status */
+    return  bit_status;
+}
+
+/**
+ * \brief   Enable or disable the I2Cx DMA interface.
+ * \param   I2Cx: Select the I2C peripheral. \ref I2C_Declaration
+ * \param   I2C_DMAReq: Specifies the I2C DMA transfer request to be enabled or disabled.
+ *          This parameter can be one of the following values:
+ *          \arg I2C_DMAReq_Tx: Tx buffer DMA transfer request.
+ *          \arg I2C_DMAReq_Rx: Rx buffer DMA transfer request.
+ * \param   NewState: New state of the selected I2C DMA transfer request.
+ *          This parameter can be: ENABLE or DISABLE.
+ * \return None.
+ */
+void I2C_DMACmd(I2C_TypeDef *I2Cx, I2CDMARequests_TypeDef I2C_DMAReq,
+                FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+    assert_param(IS_I2C_DMAREQ(I2C_DMAReq));
+
+    if (NewState != DISABLE)
+    {
+        /* Enable the selected I2C DMA request */
+        I2Cx->IC_DMA_CR |= I2C_DMAReq;
+    }
+    else
+    {
+        /* Disable the selected I2C DMA request */
+        I2Cx->IC_DMA_CR &= (uint16_t)~(I2C_DMAReq);
+    }
+}
+
+/**
+  * \brief  Set Clock Speed through the I2Cx peripheral.
+  * \param  I2Cx: Select the I2C peripheral. \ref I2C_Declaration
+  * \param  I2C_ClockSpeed: CLock speed.
+  * \return None
+  */
+void I2C_SetClockSpeed(I2C_TypeDef *I2Cx, uint32_t I2C_ClockSpeed)
+{
+    uint32_t I2CSrcClk = 0;
+    uint32_t tick_clksrc_ns = 0;
+    uint32_t allowedSpeed = 0;
+    uint32_t spklen = 0;
+    uint32_t scl_low_period_spec_min_ns = 0;
+    uint32_t scl_high_period_spec_min_ns = 0;
+    uint32_t scl_lcnt_min = 0;
+    uint32_t scl_hcnt_min = 0;
+    uint32_t scl_low_period_min_ns = 0;
+    uint32_t scl_high_period_min_ns = 0;
+    uint32_t tick_clkspeed_ns = 0;
+    uint32_t total_period_ns = 0;
+    uint32_t total_hcnt_lcnt = 0;
+    int32_t remaining = 0;
+    uint32_t scl_lcnt = 0;
+    uint32_t scl_hcnt = 0;
+
+    /* Obtain the I2C Clock source based on the I2C divider. */
+    I2CSrcClk = I2C_GetClock(I2Cx);
+
+    /* Tick of I2C clock source in ns. */
+    tick_clksrc_ns = NS_PER_SECOND / I2CSrcClk;
+
+    /* Limit the maximum I2C speed according to the I2C clock source. */
+    if (I2CSrcClk == 40000000)
+    {
+        allowedSpeed = 1000000;
+    }
+    else if (I2CSrcClk == 20000000)
+    {
+        allowedSpeed = 400000;
+    }
+    else
+    {
+        allowedSpeed = 100000;
+    }
+    /* Set Max I2C Clock speed. */
+    I2C_ClockSpeed = (I2C_ClockSpeed > allowedSpeed) ? allowedSpeed : I2C_ClockSpeed;
+
+    /* Set the spike time according to SPEC */
+    /* For Standard mode, there is no limit on spike suppression time, use default value. */
+    if (I2C_ClockSpeed <= 100000)
+    {
+        spklen = 0x05;
+    }
+    /* For Fast mode (plus), the max spike suppression time is 50ns. */
+    else
+    {
+        spklen = 0x01;
+    }
+
+    /* Set suppression limit */
+    I2Cx->IC_FS_SPKLEN = spklen & 0xFFFF;
+
+    /******************* Calulate the SCL low high count based on SPEC *******************/
+    /* Get the minimum of scl low high period specified in the spec */
+    if (I2C_ClockSpeed <= 100000)
+    {
+        scl_low_period_spec_min_ns = I2C_STANDARD_MODE_SCL_LOW_PERIOD_MIN_NS;
+        scl_high_period_spec_min_ns = I2C_STANDARD_MODE_SCL_HIGH_PERIOD_MIN_NS;
+    }
+    else if (I2C_ClockSpeed <= 400000)
+    {
+        scl_low_period_spec_min_ns = I2C_FAST_MODE_SCL_LOW_PERIOD_MIN_NS;
+        scl_high_period_spec_min_ns = I2C_FAST_MODE_SCL_HIGH_PERIOD_MIN_NS;
+    }
+    else
+    {
+        scl_low_period_spec_min_ns = I2C_FAST_MODE_PLUS_SCL_LOW_PERIOD_MIN_NS;
+        scl_high_period_spec_min_ns = I2C_FAST_MODE_PLUS_SCL_HIGH_PERIOD_MIN_NS;
+    }
+
+
+    /* Calulate the minimum of scl low high period based on LCNT/HCNT specified in hardware:
+     *
+     * Firstly, get the minimum LCNT HCNT specified in hardware.
+     * - LCNT: IC_SS_SCL_LCNT and IC_FS_SCL_LCNT register values must be larger than IC_FS_SPKLEN + 7.
+     * - HCNT: IC_SS_SCL_HCNT and IC_FS_SCL_HCNT register values must be larger than IC_FS_SPKLEN + 5.
+     * Use +1 to enforce strictly greater with integer registers.
+     *
+     * Secondly, calulate the minimum of scl high/low period based on the LCNT/HCNT.
+     */
+
+    scl_lcnt_min = spklen + 7 + 1;
+    scl_hcnt_min = spklen + 5 + 1;
+    scl_low_period_min_ns = (scl_lcnt_min + I2C_SCL_LOW_PERIOD_COMPENSATE) * tick_clksrc_ns;
+    scl_high_period_min_ns = (scl_hcnt_min + spklen + I2C_SCL_HIGH_PERIOD_COMPENSATE) *
+                             tick_clksrc_ns;
+
+    /* Final minimum: satisfy both spec and hardware. */
+    scl_low_period_min_ns = (scl_low_period_min_ns > scl_low_period_spec_min_ns) ?
+                            scl_low_period_min_ns : scl_low_period_spec_min_ns;
+    scl_high_period_min_ns = (scl_high_period_min_ns > scl_high_period_spec_min_ns) ?
+                             scl_high_period_min_ns : scl_high_period_spec_min_ns;
+
+    scl_lcnt_min = ROUNDUP(scl_low_period_min_ns, tick_clksrc_ns) - I2C_SCL_LOW_PERIOD_COMPENSATE;
+    scl_hcnt_min = ROUNDUP(scl_high_period_min_ns,
+                           tick_clksrc_ns) - spklen - I2C_SCL_HIGH_PERIOD_COMPENSATE;
+
+    /*************** Calulate the SCL low high count based on I2C_Clock_Speed ***************/
+
+    /* Calculate target total (high+low) counter based on the desired frequency of I2C SCL.
+     * Firstly, calulate the total period: tick_clkspeed_ns minus I2C_RisingTimeNs.
+     *   - Notes: I2C_RisingTimeNs should be below the range.
+     * Secondly, total_period_ns div tick_clksrc_ns, round up.
+     * Then subtract SPKLEN and path compensations to get pure HCNT+LCNT sum.
+     */
+
+    tick_clkspeed_ns = NS_PER_SECOND / I2C_ClockSpeed;
+    total_period_ns = tick_clkspeed_ns - I2C_RisingTimeNs;
+    total_hcnt_lcnt = (ROUNDUP(total_period_ns, tick_clksrc_ns)
+                       - spklen - I2C_SCL_HIGH_PERIOD_COMPENSATE - I2C_SCL_LOW_PERIOD_COMPENSATE);
+
+    /***************** Distibute the remaining count to the SCL low high *****************/
+
+    /* Calculate the remaining as total_hcnt_lcnt - (scl_lcnt_min + scl_hcnt_min),
+     * distribute the remaining counts between low and high count.
+     */
+
+    remaining = total_hcnt_lcnt - scl_lcnt_min - scl_hcnt_min;
+    scl_lcnt = scl_lcnt_min;
+    scl_hcnt = scl_hcnt_min;
+    if (remaining > 0)
+    {
+        scl_lcnt = scl_lcnt_min + (uint32_t)(remaining / 2);
+        scl_hcnt = total_hcnt_lcnt - scl_lcnt;
+    }
+
+    /* Set speed mode and write counters to responsing registers */
+    IC_CON_TypeDef i2c_ctrl = {.d32 = I2Cx->IC_CON};
+    if (I2C_ClockSpeed <= 100000)
+    {
+        /*Configure I2C speed in standard mode*/
+        i2c_ctrl.b.speed = 0x1;
+        I2Cx->IC_CON = i2c_ctrl.d32;
+        I2Cx->IC_SS_SCL_LCNT = scl_lcnt & 0xFFFF;
+        I2Cx->IC_SS_SCL_HCNT = scl_hcnt & 0xFFFF;
+    }
+    else
+    {
+        /* Configure I2C speed in fast mode or fast mode plus*/
+        i2c_ctrl.b.speed = 0x2;
+        I2Cx->IC_CON = i2c_ctrl.d32;
+        I2Cx->IC_FS_SCL_LCNT = scl_lcnt & 0xFFFF;
+        I2Cx->IC_FS_SCL_HCNT = scl_hcnt & 0xFFFF;
+    }
+
+}
+
+#if (I2C_SUPPORT_WRAPPER_MODE == 1)
+void I2C_WrapperModeCmd(I2C_TypeDef *I2Cx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+    WRAP_CR_TypeDef i2c_0x10c = {.d32 = I2Cx->WRAP_CR};
+    i2c_0x10c.b.wrapper_clk_en = NewState;
+    I2Cx->WRAP_CR = i2c_0x10c.d32;
+}
+
+bool I2C_WrapperSetTransMode(I2C_TypeDef *I2Cx, uint32_t mode)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+    WRAP_CR_TypeDef i2c_0x10c = {.d32 = I2Cx->WRAP_CR};
+    i2c_0x10c.b.trans_mode = mode;
+    I2Cx->WRAP_CR = i2c_0x10c.d32;
+    return i2c_0x10c.b.wrapper_busy;
+}
+
+void I2C_WrapperSetWriteNum(I2C_TypeDef *I2Cx, uint8_t num)
+{
+    /* num should be less than 24 */
+    /* Check the parameters */
+    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+    I2Cx->RAP_WCMD_NUM = num - 1;
+}
+
+void I2C_WrapperSetWriteData(I2C_TypeDef *I2Cx, const uint8_t *buf, uint8_t num)
+{
+    /* num should be less than 24 */
+    /* Check the parameters */
+    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+    for (uint8_t i = 0; i < num; i++)
+    {
+        I2Cx->RAP_WCMD_DATA = *buf++;
+    }
+}
+
+uint8_t I2C_WrapperGetTxFIFOLen(I2C_TypeDef *I2Cx)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+    RAP_BUF_CR_TypeDef i2c_0x114 = {.d32 = I2Cx->RAP_BUF_CR};
+    return i2c_0x114.b.wrap_buf_amount;
+}
+
+void I2C_WrapperClearTxFIFO(I2C_TypeDef *I2Cx)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+    RAP_BUF_CR_TypeDef i2c_0x114 = {.d32 = I2Cx->RAP_BUF_CR};
+    i2c_0x114.b.wrap_buf_clear = 1;
+    I2Cx->RAP_BUF_CR = i2c_0x114.d32;
+}
+
+void I2C_WrapperSetReadNum(I2C_TypeDef *I2Cx, uint16_t num)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+    I2Cx->RAP_RCMD_NUM = num - 1;
+}
+
+uint8_t I2C_WrapperReceiveData(I2C_TypeDef *I2Cx)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+    /* Return the data in the DR register */
+    return I2C_ReceiveData(I2Cx);
+}
+
+uint8_t I2C_WrapperGetRxFIFOLen(I2C_TypeDef *I2Cx)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+    return I2C_GetRxFIFOLen(I2Cx);
+}
+
+void I2C_WrapperTransStart(I2C_TypeDef *I2Cx)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+    WRAP_CR_TypeDef i2c_0x10c = {.d32 = I2Cx->WRAP_CR};
+    i2c_0x10c.b.start_wrapper = 1;
+    I2Cx->WRAP_CR = i2c_0x10c.d32;
+}
+
+bool I2C_WrapperBusyCheck(I2C_TypeDef *I2Cx)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+    WRAP_CR_TypeDef i2c_0x10c = {.d32 = I2Cx->WRAP_CR};
+    return i2c_0x10c.b.wrapper_busy;
+}
+#endif
+
+#if (I2C_SUPPORT_RAP_FUNCTION == 1)
+void I2C_RAPModeCmd(I2C_TypeDef *I2Cx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+    WRAP_CR_TypeDef i2c_0x10c = {.d32 = I2Cx->WRAP_CR};
+    i2c_0x10c.b.rap_mode = NewState;
+    I2Cx->WRAP_CR = i2c_0x10c.d32;
+}
+
+void I2C_ActionTrigger(I2C_TypeDef *I2Cx, uint32_t Action)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+    I2Cx->RAP_TASK |= BIT(Action);
+}
+
+#endif
+
+
+
diff --git a/bee/drivers/i2s/CMakeLists.txt b/bee/drivers/i2s/CMakeLists.txt
new file mode 100644
index 00000000..e6e1f14a
--- /dev/null
+++ b/bee/drivers/i2s/CMakeLists.txt
@@ -0,0 +1,8 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+if(CONFIG_REALTEK_BEE_COMMON_DRIVER)
+    zephyr_include_directories(inc)
+endif()
+
+add_subdirectory_ifdef(CONFIG_REALTEK_BEE_I2S src)
diff --git a/bee/drivers/i2s/Kconfig b/bee/drivers/i2s/Kconfig
new file mode 100644
index 00000000..a351d768
--- /dev/null
+++ b/bee/drivers/i2s/Kconfig
@@ -0,0 +1,8 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config REALTEK_BEE_I2S
+	bool "Realtek Bee I2S driver"
+	default n
+	help
+	  This option enables the I2S driver for Realtek Bee.
diff --git a/bee/drivers/i2s/inc/rtl_i2s.h b/bee/drivers/i2s/inc/rtl_i2s.h
new file mode 100644
index 00000000..ef4abfd7
--- /dev/null
+++ b/bee/drivers/i2s/inc/rtl_i2s.h
@@ -0,0 +1,977 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *               Define to prevent recursive inclusion
+ *============================================================================*/
+#ifndef RTL_I2S_H
+#define RTL_I2S_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*============================================================================*
+ *                        Header Files
+ *============================================================================*/
+#include "utils/rtl_utils.h"
+#if defined (CONFIG_SOC_SERIES_RTL87X2G)
+#include "i2s/src/device/rtl87x2g/rtl_i2s_def.h"
+#elif defined (CONFIG_SOC_SERIES_RTL87X2J)
+#include "i2s/src/device/rtl87x2j/rtl_i2s_def.h"
+#endif
+
+/** \defgroup I2S         I2S
+  * \brief
+  * \{
+  */
+
+/*============================================================================*
+ *                         Constants
+ *============================================================================*/
+/** \defgroup I2S_Exported_Constants I2S Exported Constants
+  * \brief
+  * \{
+  */
+
+
+#if I2S_SUPPORT_TRX_INDEPENDENT_CONTROL
+/**
+* \defgroup    I2S_Scheme  I2S Scheme
+* \{
+* \ingroup     I2S_Exported_Constants
+*/
+typedef enum
+{
+    I2S_SCHEME_SEPARATE,
+    I2S_SCHEME_DEPENDENT,
+} I2SScheme_TypeDef;
+
+#define IS_I2S_SCHEME(SCHEME) (((SCHEME) == I2S_SCHEME_SEPARATE) || \
+                               ((SCHEME) == I2S_SCHEME_DEPENDENT)))
+
+/** End of I2S_Scheme
+  * \}
+  */
+
+#endif
+
+/**
+ * \defgroup    I2S_DATA_Format  I2S Data Format
+ * \{
+ * \ingroup     I2S_Exported_Constants
+ */
+typedef enum
+{
+    I2S_DATA_FORMAT_I2S,
+    I2S_DATA_FORMAT_LEFT_JUSTIFIED,
+    I2S_DATA_FORMAT_PCM_A,
+    I2S_DATA_FORMAT_PCM_B,
+} I2SDataFormat_TypeDef;
+
+#define IS_I2S_DATA_FORMAT(FORMAT)      (((FORMAT) == I2S_DATA_FORMAT_I2S) || ((FORMAT) == I2S_DATA_FORMAT_LEFT_JUSTIFIED) || \
+                                         ((FORMAT) == I2S_DATA_FORMAT_PCM_A) || ((FORMAT) == I2S_DATA_FORMAT_PCM_B))
+
+/** End of I2S_DATA_Format
+  * \}
+  */
+
+/**
+ * \defgroup    I2S_Channel_Type I2S Channel Type
+ * \{
+ * \ingroup     I2S_Exported_Constants
+ */
+typedef enum
+{
+    I2S_CHANNEL_STEREO,
+    I2S_CHANNEL_MONO,
+} I2SChannelType_TypeDef;
+
+#define IS_I2S_CHANNEL_TYPE(TYPE)       (((TYPE) == I2S_CHANNEL_MONO) || ((TYPE) == I2S_CHANNEL_STEREO))
+
+/** End of I2S_Channel_Type
+  * \}
+  */
+
+/**
+ * \defgroup    I2S_Width I2S  Width
+ * \{
+ * \ingroup     I2S_Exported_Constants
+ */
+typedef enum
+{
+    I2S_WIDTH_16BITS = 0x00,
+    I2S_WIDTH_24BITS = 0x02,
+    I2S_WIDTH_8BITS = 0x03,
+#if I2S_SUPPORT_DATE_WIDTH_32BIT
+    I2S_WIDTH_20BITS = 0x01,
+    I2S_WIDTH_32BITS = 0x04,
+#endif
+} I2SWidth_TypeDef;
+
+#define IS_I2S_WIDTH(WIDTH)        (((WIDTH) == I2S_WIDTH_16BITS) || \
+                                    ((WIDTH) == I2S_WIDTH_8BITS)  || \
+                                    ((WIDTH) == I2S_WIDTH_24BITS) || \
+                                    ((WIDTH) == I2S_WIDTH_20BITS) || \
+                                    ((WIDTH) == I2S_WIDTH_32BITS))
+
+/** End of I2S_Data_Width
+  * \}
+  */
+
+/**
+ * \defgroup    I2S_Device_Mode I2S Device Mode
+ * \{
+ * \ingroup     I2S_Exported_Constants
+ */
+typedef enum
+{
+    I2S_DEVICE_MODE_MASTER,
+    I2S_DEVICE_MODE_SLAVE,
+} I2SDeviceMode_TypeDef;
+
+#define IS_I2S_DEVICE_MODE(DEVICE)      (((DEVICE) == I2S_DEVICE_MODE_MASTER) || ((DEVICE) == I2S_DEVICE_MODE_SLAVE))
+
+/** End of I2S_Device_Mode
+  * \}
+  */
+
+/**
+ * \defgroup    I2S_Ch_Seq I2S Ch Seq
+ * \{
+ * \ingroup     I2S_Exported_Constants
+ */
+typedef enum
+{
+    I2S_CH_SEQ_L_R,
+    I2S_CH_SEQ_R_L,
+    I2S_CH_SEQ_L_L,
+    I2S_CH_SEQ_R_R,
+} I2SChSeq_TypeDef;
+
+#define IS_I2S_CH_SEQ(SEQ)       (((SEQ) == I2S_CH_SEQ_L_R) || ((SEQ) == I2S_CH_SEQ_R_L) || \
+                                  ((SEQ) == I2S_CH_SEQ_L_L) || ((SEQ) == I2S_CH_SEQ_R_R))
+
+/** End of I2S_Ch_Seq
+  * \}
+  */
+
+/**
+ * \defgroup    I2S_Bit_Seq I2S Bit Seq
+ * \{
+ * \ingroup     I2S_Exported_Constants
+ */
+typedef enum
+{
+    I2S_MSB_FIRST,
+    I2S_LSB_FIRST,
+} I2SBitSeq_TypeDef;
+
+#define IS_I2S_BIT_SEQ(SEQ)      (((SEQ) == I2S_MSB_FIRST) || ((SEQ) == I2S_LSB_FIRST))
+
+/** End of I2S_Tx_Bit_Seq
+  * \}
+  */
+#if I2S_SUPPORT_TRX_FIFO
+/**
+ * \defgroup    I2S_FIFO_Sel I2S FIFO Sel
+ * \{
+ * \ingroup     I2S_Exported_Constants
+ */
+typedef enum
+{
+    I2S_FIFO_USE_0_REG_0 = BIT0,
+    I2S_FIFO_USE_0_REG_1 = BIT1,
+} I2SFIFOSel_TypeDef;
+
+/** End of I2S_FIFO_Sel
+  * \}
+  */
+#endif
+#if I2S_SUPPORT_MCLK_OUTPUT
+/**
+ * \defgroup    I2S_MCLK_Output I2S MCLK Output
+ * \{
+ * \ingroup     I2S_Exported_Constants
+ */
+
+typedef enum
+{
+    I2S_MCLK_128FS,
+    I2S_MCLK_256FS,
+} I2SMClkOutput_TypeDef;
+
+#define IS_I2S_MCLK_OUTPUT(TYPE)       (((TYPE) == I2S_MCLK_128FS) || ((TYPE) == I2S_MCLK_256FS))
+
+/** End of I2S_MCLK_Output
+  * \}
+  */
+
+#endif
+
+/**
+ * \defgroup    I2S_ERR_CLR I2S ERR CLR
+ * \{
+ * \ingroup     I2S_Exported_Constants
+ */
+/*  I2S_CLR_RX_ERR_CNT. */
+#define I2S_CLR_RX_ERR_CNT_MSK          (0x1 << 13)
+#define I2S_CLR_RX_ERR_CNT_CLR          (~I2S_CLR_RX_ERR_CNT_MSK)
+/* I2S_CLR_TX_ERR_CNT. */
+#define I2S_CLR_TX_ERR_CNT_MSK          (0x1 << 12)
+#define I2S_CLR_TX_ERR_CNT_CLR          (~I2S_CLR_TX_ERR_CNT_MSK)
+
+#define I2S_RX_FIFO_DEPTH_CNT_0_POS       (8)
+#define I2S_RX_ERR_CNT_POS                (15)
+#define I2S_MI_NI_UPDATE_MSK             ((uint32_t)0x1 << 31)
+
+#define I2S_FRAME_SYNC_OFFSET_DEFAULT    (0x81 )
+/** End of I2S_ERR_CLR
+  * \}
+  */
+
+/**
+ * \defgroup    I2S_Mode I2S Mode
+ * \{
+ * \ingroup     I2S_Exported_Constants
+ */
+typedef enum
+{
+    I2S_MODE_TX,
+    I2S_MODE_RX,
+} I2SMode_TypeDef;
+
+#define IS_I2S_MODE(MODE)      (((MODE) == I2S_MODE_TX) || ((MODE) == I2S_MODE_RX))
+
+/** End of I2S_Mode
+  * \}
+  */
+
+
+#if I2S_SUPPORT_TRX_FIFO
+/**
+ * \defgroup    I2S_Tx_FIFO_Sel I2S Tx FIFO Sel
+ * \{
+ * \ingroup     I2S_Exported_Constants
+ */
+typedef enum
+{
+    I2S_TX_FIFO_0_REG_0_L,                        // 0
+    I2S_TX_FIFO_0_REG_0_R,                        // 1
+    I2S_TX_FIFO_0_REG_1_L,                        // 2
+    I2S_TX_FIFO_0_REG_1_R,                        // 3
+    I2S_TX_SEL_MAX,
+} I2STxFIFOSel_TypeDef;
+
+#define IS_I2S_TX_FIFO_SEL(FIFO)       (((FIFO) == I2S_TX_FIFO_0_REG_0_L) || ((FIFO) == I2S_TX_FIFO_0_REG_0_R) || \
+                                        ((FIFO) == I2S_TX_FIFO_0_REG_1_L) || ((FIFO) == I2S_TX_FIFO_0_REG_1_R))
+
+/** End of I2S_Tx_FIFO_Sel
+  * \}
+  */
+
+/**
+ * \defgroup    I2S_Rx_Channel_Sel I2S Rx Channel Sel
+ * \{
+ * \ingroup     I2S_Exported_Constants
+ */
+typedef enum
+{
+    I2S_RX_CHANNEL_0,                             // 0
+    I2S_RX_CHANNEL_1,                             // 1
+    I2S_RX_CHANNEL_2,                             // 2
+    I2S_RX_CHANNEL_3,                             // 3
+    I2S_RX_SEL_MAX,
+} I2SRxChannel_TypeDef;
+
+#define IS_I2S_RX_CHANNEL(CHANNEL)       (((CHANNEL) == I2S_RX_CHANNEL_0) || ((CHANNEL) == I2S_RX_CHANNEL_1) || \
+                                          ((CHANNEL) == I2S_RX_CHANNEL_2) || ((CHANNEL) == I2S_RX_CHANNEL_3))
+/** End of I2S_Tx_FIFO_Sel
+  * \}
+  */
+
+#endif
+/** End of I2S_Exported_Constants
+  * \}
+  */
+/*============================================================================*
+ *                         Types
+ *============================================================================*/
+/** \defgroup I2S_Exported_Types I2S Exported Types
+ * \brief
+ * \{
+ */
+
+/**
+ * \brief       I2S initialize parameters.
+ *
+ * \ingroup     I2S_Exported_Types
+ */
+typedef struct
+{
+    I2SClockSrc_TypeDef I2S_ClockSource;          /*!< Specifies the I2S clock source.*/
+
+#if I2S_SUPPORT_TRX_INDEPENDENT_CONTROL
+    I2SScheme_TypeDef I2S_Scheme;               /*!< Specifies the I2S Scheme.*/
+
+    uint32_t I2S_TxBClockMi;                    /*!< Specifies the BLCK clock speed. BCLK = 40MHz*(I2S_BClockNi/I2S_BClockMi).
+                                                     This parameter must range from 1 to 0xffff. */
+
+    uint32_t I2S_TxBClockNi;                    /*!< Specifies the BLCK clock speed.
+                                                     This parameter must range from 1 to 0x7FFF. */
+
+    uint32_t I2S_TxBClockDiv;                   /*!< Specifies the BLCK clock divider.
+                                                     This parameter must range from 1 to 0xFF. */
+
+    uint32_t I2S_RxBClockMi;                    /*!< Specifies the BLCK clock speed. BCLK = 40MHz*(I2S_BClockNi/I2S_BClockMi).
+                                                     This parameter must range from 1 to 0xffff. */
+
+    uint32_t I2S_RxBClockNi;                    /*!< Specifies the BLCK clock speed.
+                                                     This parameter must range from 1 to 0x7FFF. */
+
+    uint32_t I2S_RxBClockDiv;                   /*!< Specifies the BLCK clock divider.
+                                                     This parameter must range from 1 to 0xFF. */
+
+    I2SChannelType_TypeDef I2S_TxChannelType;   /*!< Specifies the channel type.
+                                                     It is used for the I2S communication. */
+
+    I2SChannelType_TypeDef I2S_RxChannelType;   /*!< Specifies the channel type.
+                                                     It is used for the I2S communication. */
+
+    I2SDataFormat_TypeDef I2S_TxDataFormat;     /*!< Specifies the I2S Data format mode.*/
+
+    I2SDataFormat_TypeDef I2S_RxDataFormat;     /*!< Specifies the I2S Data format mode.*/
+
+    I2SWidth_TypeDef I2S_TxDataWidth;           /*!< Specifies the I2S Data width. */
+
+    I2SWidth_TypeDef I2S_RxDataWidth;           /*!< Specifies the I2S Data width. */
+
+    I2SWidth_TypeDef I2S_TxChannelWidth;        /*!< Specifies the I2S channle width.*/
+
+    I2SWidth_TypeDef I2S_RxChannelWidth;        /*!< Specifies the I2S channle width.*/
+
+    FunctionalState I2S_BClockFixEn;            /*!< Specifies the I2S BCLK fix.
+                                                     If ENABLE, BCLK is fixed as 40M/4.*/
+
+#else
+    uint32_t I2S_BClockMi;                      /*!< Specifies the BLCK clock speed. BCLK = 40MHz*(I2S_BClockNi/I2S_BClockMi).
+                                                     This parameter must range from 1 to 0xffff */
+
+    uint32_t I2S_BClockNi;                      /*!< Specifies the BLCK clock speed.
+                                                     This parameter must range from 1 to 0x7FFF */
+
+    I2SChannelType_TypeDef I2S_ChannelType;     /*!< Specifies the channel type.
+                                                     It is used for the I2S communication.
+                                                     This parameter can be a value of \ref I2S_Channel_Type */
+
+    I2SDataFormat_TypeDef I2S_DataFormat;       /*!< Specifies the I2S Data format mode.
+                                                     This parameter can be a value of \ref I2S_Format_Mode*/
+
+    I2SWidth_TypeDef I2S_DataWidth;             /*!< Specifies the I2S Data width.
+                                                     This parameter can be a value of \ref I2S_Data_Width */
+#endif
+
+#if I2S_SUPPORT_TRX_FIFO
+    I2SFIFOSel_TypeDef I2S_TxFIFOSel;           /*!< Specifies the I2S FIFO.*/
+
+    I2SFIFOSel_TypeDef I2S_RxFIFOSel;           /*!< Specifies the I2S FIFO.*/
+#endif
+
+    I2SDeviceMode_TypeDef I2S_DeviceMode;       /*!< Specifies the I2S device mode. */
+
+    I2SChSeq_TypeDef I2S_RxChannelSequence;     /*!< Specifies the receiving channel seqence.
+                                                     It is used for the I2S communication.*/
+
+    I2SChSeq_TypeDef I2S_TxChannelSequence;     /*!< Specifies the transmission channel seqence.
+                                                     It is used for the I2S communication.*/
+
+    I2SBitSeq_TypeDef I2S_TxBitSequence;        /*!< Specifies the I2S Data bits sequences.*/
+
+    I2SBitSeq_TypeDef I2S_RxBitSequence;        /*!< Specifies the I2S Data bits sequences.*/
+
+    uint32_t I2S_TxWaterlevel;                  /*!< Specifies the dma watermark level in transmit mode.
+                                                     This parameter must range from 1 to 63. */
+
+    uint32_t I2S_RxWaterlevel;                  /*!< Specifies the dma watermark level in receive mode.
+                                                     This parameter must range from 1 to 63. */
+
+#if I2S_SUPPORT_MCLK_OUTPUT
+    I2SMClkOutput_TypeDef I2S_MClockOutput;     /*!< Specifies the I2S MCLK output freqency.
+                                                     This parameter can be a value of \ref I2S_MCLK_Output */
+#endif
+} I2S_InitTypeDef;
+
+#if I2S_SUPPORT_TRX_FIFO
+/**
+ * \brief       I2S Data Sel
+ *
+ * \ingroup     I2S_Exported_Types
+ */
+typedef struct
+{
+    uint8_t tx_channel_map[4];
+    uint8_t rx_fifo_map[4];
+} I2S_DataSelTypeDef;
+#endif
+
+/** End of I2S_Exported_Types
+  * \}
+  */
+
+/*============================================================================*
+ *                         Constants
+ *============================================================================*/
+/** \defgroup I2S_Exported_Constants I2S Exported Constants
+  * \brief
+  * \{
+  */
+
+/**
+ * \defgroup    I2S_Interrupt_Definition   I2S Interrupt Definition
+ * \{
+ * \ingroup     I2S_Exported_Constants
+ */
+#if I2S_SUPPORT_INT_TX_VALID
+#define I2S_INT_TX_VALID                            BIT7//(I2S_TX_IDLE_MSK)
+#endif
+#define I2S_INT_TX_IDLE                             BIT6//(I2S_TX_IDLE_MSK)
+#define I2S_INT_RF_EMPTY                            BIT5//(I2S_RF_EMPTY_MSK)
+#define I2S_INT_TF_EMPTY                            BIT4// (I2S_TF_EMPTY_MSK)
+#define I2S_INT_RF_FULL                             BIT3// (I2S_RX_FULL_MSK)
+#define I2S_INT_TF_FULL                             BIT2// (I2S_TX_FULL_MSK)
+#define I2S_INT_RX_READY                            BIT1// (I2S_READY_TO_RX_MSK)
+#define I2S_INT_TX_READY                            BIT0// (I2S_READY_TO_TX_MSK)
+
+#define IS_I2S_INT_CONFIG(INT)          (((INT) == I2S_INT_TX_IDLE) || ((INT) == I2S_INT_RF_EMPTY) || \
+                                         ((INT) == I2S_INT_TF_EMPTY) || ((INT) == I2S_INT_RF_FULL) || \
+                                         ((INT) == I2S_INT_TF_FULL) || ((INT) == I2S_INT_RX_READY) || \
+                                         ((INT) == I2S_INT_TX_READY) )
+
+/** End of I2S_Interrupt_Definition
+  * \}
+  */
+
+/**
+ * \defgroup    I2S_Clear_Interrupt_Definition     I2S Clear Interrupt Definition
+ * \{
+ * \ingroup     I2S_Exported_Constants
+ */
+#define I2S_CLEAR_INT_TX_VALID                            BIT14//(I2S_TX_IDLE_MSK)
+#define I2S_CLEAR_INT_TX_IDLE                             BIT6//(I2S_TX_IDLE_MSK)
+#define I2S_CLEAR_INT_RF_EMPTY                            BIT5//(I2S_RF_EMPTY_MSK)
+#define I2S_CLEAR_INT_TF_EMPTY                            BIT4// (I2S_TF_EMPTY_MSK)
+#define I2S_CLEAR_INT_RF_FULL                             BIT3// (I2S_RX_FULL_MSK)
+#define I2S_CLEAR_INT_TF_FULL                             BIT2// (I2S_TX_FULL_MSK)
+#define I2S_CLEAR_INT_RX_READY                            BIT1// (I2S_READY_TO_RX_MSK)
+#define I2S_CLEAR_INT_TX_READY                            BIT0// (I2S_READY_TO_TX_MSK)
+
+#define IS_I2S_CLEAR_INT(CLEAR)          (((CLEAR) == I2S_CLEAR_INT_RX_READY) || \
+                                          ((CLEAR) == I2S_CLEAR_INT_TX_READY) || \
+                                          (CLEAR) == I2S_CLEAR_INT_RX_READY) || \
+((CLEAR) == I2S_CLEAR_INT_TX_READY) )
+
+/** End of I2S_Clear_Interrupt_Definition
+  * \}
+  */
+
+
+
+/*============================================================================*
+ *                         Functions
+ *============================================================================*/
+/** \defgroup I2S_Exported_Functions I2S Exported Functions
+  * \brief
+  * \{
+  */
+
+/**
+ * \brief   Deinitializes the I2S peripheral registers to their default values.
+ * \param   None.
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_i2s_init(void)
+ * {
+ *     I2S_DeInit(I2S0);
+ * }
+ * \endcode
+ */
+void I2S_DeInit(I2S_TypeDef *I2Sx);
+
+/**
+ * \brief   Initializes the I2S peripheral according to the specified
+ *          parameters in the I2S_InitStruct
+ * \param[in] I2Sx: Selected I2S peripheral.
+ * \param[in] I2S_InitStruct: Pointer to a I2S_InitTypeDef structure that
+ *            contains the configuration information for the specified I2S peripheral
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_i2s_init(void)
+ * {
+ *     RCC_ClockCmd(I2S_CLOCK, ENABLE);
+ *
+ *     I2S_InitTypeDef I2S_InitStruct;
+ *
+ *     I2S_StructInit(&I2S_InitStruct);
+ *     I2S_InitStruct.I2S_ClockSource      = I2S_CLK_40M;
+ *     I2S_InitStruct.I2S_BClockMi         = 0x271;
+ *     I2S_InitStruct.I2S_BClockNi         = 0x10;
+ *     I2S_InitStruct.I2S_DeviceMode       = I2S_DEVICE_MODE_MASTER;
+ *     I2S_InitStruct.I2S_ChannelType      = I2S_Channel_stereo;
+ *     I2S_InitStruct.I2S_DataWidth        = I2S_WIDTH_16BITS;
+ *     I2S_InitStruct.I2S_DataFormat       = I2S_DATA_FORMAT_I2S;
+ *     I2S_InitStruct.I2S_DMACmd           = I2S_DMA_DISABLE;
+ *     I2S_Init(I2S0, &I2S_InitStruct);
+ *     I2S_Cmd(I2S0, I2S_MODE_TX, ENABLE);
+ * }
+ * \endcode
+ */
+void I2S_Init(I2S_TypeDef *I2Sx, I2S_InitTypeDef *I2S_InitStruct);
+
+/**
+ * \brief   Fills each I2S_InitStruct member with its default value.
+ * \param[in] I2S_InitStruct: Pointer to an I2S_InitTypeDef structure which will be initialized.
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_i2s_init(void)
+ * {
+ *     RCC_ClockCmd(I2S_CLOCK, ENABLE);
+ *
+ *     I2S_InitTypeDef I2S_InitStruct;
+ *
+ *     I2S_StructInit(&I2S_InitStruct);
+ *     I2S_InitStruct.I2S_ClockSource      = I2S_CLOCK_SRC_40M;
+ *     I2S_InitStruct.I2S_BClockMi         = 0x271;
+ *     I2S_InitStruct.I2S_BClockNi         = 0x10;
+ *     I2S_InitStruct.I2S_DeviceMode       = I2S_DEVICE_MODE_MASTER;
+ *     I2S_InitStruct.I2S_ChannelType      = I2S_Channel_stereo;
+ *     I2S_InitStruct.I2S_DataWidth        = I2S_WIDTH_16BITS;
+ *     I2S_InitStruct.I2S_DataFormat       = I2S_DATA_FORMAT_I2S;
+ *     I2S_InitStruct.I2S_DMACmd           = I2S_DMA_DISABLE;
+ *     I2S_Init(I2S0, &I2S_InitStruct);
+ *     I2S_Cmd(I2S0, I2S_MODE_TX, ENABLE);
+ * }
+ * \endcode
+ */
+void I2S_StructInit(I2S_InitTypeDef *I2S_InitStruct);
+/**
+ * \brief   Enable or disable the selected I2S mode.
+ * \param[in] I2Sx: Selected I2S peripheral.
+ * \param[in] mode: Selected I2S operation mode.
+ *      This parameter can be the following values:
+ *      \arg I2S_MODE_TX: Transmission mode.
+ *      \arg I2S_MODE_RX: Receiving mode.
+ * \param[in] NewState: New state of the operation mode.
+ *      This parameter can be: ENABLE or DISABLE.
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_i2s_init(void)
+ * {
+ *     RCC_ClockCmd(I2S_CLOCK, ENABLE);
+ *
+ *     I2S_InitTypeDef I2S_InitStruct;
+ *
+ *     I2S_StructInit(&I2S_InitStruct);
+ *     I2S_InitStruct.I2S_ClockSource      = I2S_CLOCK_SRC_40M;
+ *     I2S_InitStruct.I2S_BClockMi         = 0x271;
+ *     I2S_InitStruct.I2S_BClockNi         = 0x10;
+ *     I2S_InitStruct.I2S_DeviceMode       = I2S_DEVICE_MODE_MASTER;
+ *     I2S_InitStruct.I2S_ChannelType      = I2S_CHANNEL_STEREO;
+ *     I2S_InitStruct.I2S_DataWidth        = I2S_WIDTH_16BITS;
+ *     I2S_InitStruct.I2S_DataFormat       = I2S_DATA_FORMAT_I2S;;
+ *     I2S_InitStruct.I2S_DMACmd           = I2S_DMA_DISABLE;
+ *     I2S_Init(I2S_NUM, &I2S_InitStruct);
+ *     I2S_Cmd(I2S_NUM, I2S_MODE_TX, ENABLE);
+ * }
+ * \endcode
+ */
+void I2S_Cmd(I2S_TypeDef *I2Sx, I2SMode_TypeDef I2S_Mode, FunctionalState NewState);
+
+/**
+ * \brief   Enable or disable the specified I2S interrupt source.
+ * \param[in] I2S_INT: Specifies the I2S interrupt source to be enable or disable.
+ *      This parameter can be the following values:
+ *      \arg I2S_INT_TX_IDLE: Transmit idle interrupt source.
+ *      \arg I2S_INT_RF_EMPTY: Receive FIFO empty interrupt source.
+ *      \arg I2S_INT_TF_EMPTY: Transmit FIFO empty interrupt source.
+ *      \arg I2S_INT_RF_FULL: Receive FIFO full interrupt source.
+ *      \arg I2S_INT_TF_FULL: Transmit FIFO full interrupt source.
+ *      \arg I2S_INT_RX_READY: Ready to receive interrupt source.
+ *      \arg I2S_INT_TX_READY: Ready to transmit interrupt source.
+ * \param[in]  NewState: New state of the specified I2S interrupt.
+ *      This parameter can be: ENABLE or DISABLE.
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void i2s_demo(void)
+ * {
+ *     I2S_INTConfig(I2S0, I2S_INT_TF_EMPTY, ENABLE);
+ * }
+ * \endcode
+ */
+void I2S_INTConfig(I2S_TypeDef *I2Sx, uint32_t I2S_INT, FunctionalState newState);
+/**
+ * \brief   Get the specified I2S interrupt status.
+ * \param[in] I2S_INT: the specified I2S interrupt.
+ *      This parameter can be one of the following values:
+ *      \arg I2S_INT_TX_IDLE: Transmit idle interrupt.
+ *      \arg I2S_INT_RF_EMPTY: Receive FIFO empty interrupt.
+ *      \arg I2S_INT_TF_EMPTY: Transmit FIFO empty interrupt.
+ *      \arg I2S_INT_RF_FULL: Receive FIFO full interrupt.
+ *      \arg I2S_INT_TF_FULL: Transmit FIFO full interrupt.
+ *      \arg I2S_INT_RX_READY: Ready to receive interrupt.
+ *      \arg I2S_INT_TX_READY: Ready to transmit interrupt.
+ * \retval The new state of I2S_INT (SET or RESET).
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void i2s_demo(void)
+ * {
+ *     ITStatus int_status = I2S_GetINTStatus(I2S0, I2S_INT_TF_EMPTY);
+ * }
+ * \endcode
+ */
+ITStatus I2S_GetINTStatus(I2S_TypeDef *I2Sx, uint32_t I2S_INT);
+
+/**
+ * \brief  Clear the I2S interrupt pending bit.
+ * \param[in] I2S_CLEAR_INT: Specifies the interrupt pending bit to clear.
+ *      This parameter can be any combination of the following values:
+ *      \arg I2S_CLEAR_INT_RX_READY: Clear ready to receive interrupt.
+ *      \arg I2S_CLEAR_INT_TX_READY: Clear ready to transmit interrupt.
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void i2s_demo(void)
+ * {
+ *     I2S_ClearINTPendingBit(I2S0, I2S_CLEAR_INT_RX_READY);
+ * }
+ * \endcode
+ */
+void I2S_ClearINTPendingBit(I2S_TypeDef *I2Sx, uint32_t I2S_CLEAR_INT);
+
+/**
+ * \brief   Transmits a data through the SPIx/I2Sx peripheral.
+ * \param[in] I2Sx: To select the I2Sx peripheral, x can be 0 or 1.
+ * \param[in] Data: Data to be transmitted.
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void i2s_demo(void)
+ * {
+ *     I2S_SendData(I2S0, 0x02);
+ * }
+ * \endcode
+ */
+void I2S_SendData(I2S_TypeDef *I2Sx, uint32_t Data);
+
+
+/**
+ * \brief  Received data by the I2Sx peripheral.
+ * \param[in] I2Sx: To select I2Sx peripheral, where x can be: 0 or 1.
+ * \return Return the most recent received data.
+ * \
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void i2s_demo(void)
+ * {
+ *     uint32_t data = I2S_ReceiveData(I2S0);
+ * }
+ * \endcode
+ */
+uint32_t I2S_ReceiveFIFOData(I2S_TypeDef *I2Sx);
+
+/**
+ * \brief   Get transmit FIFO free length by the I2Sx peripheral.
+ * \param[in] I2Sx: To select I2Sx peripheral, where x can be: 0 or 1.
+ * \retval  Return the transmit FIFO free length.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void i2s_demo(void)
+ * {
+ *     uint8_t data_len = I2S_GetTxFIFOFreeLen(I2S0);
+ * }
+ * \endcode
+ */
+uint8_t I2S_GetTxFIFOFreeLen(I2S_TypeDef *I2Sx);
+
+/**
+ * \brief   Get receive FIFO data length by the I2Sx peripheral.
+ * \param[in] I2Sx: To select I2Sx peripheral, where x can be: 0 or 1.
+ * \return  The data length of the receive FIFO.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void i2s_demo(void)
+ * {
+ *     uint8_t data_len = I2S_GetRxFIFOLen(I2S0);
+ * }
+ * \endcode
+ */
+uint8_t I2S_GetRxFIFOLen(I2S_TypeDef *I2Sx);
+
+/**
+ * \brief   Get the send error counter value by the I2Sx peripheral.
+ * \param[in]  I2Sx: To select I2Sx peripheral, where x can be: 0 or 1.
+ * \return  The send error counter value .
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void i2s_demo(void)
+ * {
+ *     uint8_t conter = I2S_GetTxErrCnt(I2S0);
+ * }
+ * \endcode
+ */
+uint8_t I2S_GetTxErrCnt(I2S_TypeDef *I2Sx);
+
+/**
+ * \brief  Get the reception error counter value by the I2Sx peripheral.
+ * \param[in] I2Sx: To select I2Sx peripheral, where x can be: 0 or 1.
+ * \retval  The reception error counter value .
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void i2s_demo(void)
+ * {
+ *     uint8_t conter = I2S_GetRxErrCnt(I2S0);
+ * }
+ * \endcode
+ */
+uint8_t I2S_GetRxErrCnt(I2S_TypeDef *I2Sx);
+
+/**
+ * \brief   Swap audio data bytes sequence which sent by the I2Sx peripheral.
+ * \param[in] I2Sx: To select I2Sx peripheral, where x can be: 0 or 1.
+ * \param[in] NewState: New state of the bytes sequence.
+ *      This parameter can be: ENABLE or DISABLE.
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void i2s_demo(void)
+ * {
+ *     I2S_SwapBytesForSend(I2S0, ENABLE);
+ * }
+ * \endcode
+ */
+void I2S_SwapBytesForSend(I2S_TypeDef *I2Sx, FunctionalState NewState);
+
+/**
+ * \brief   Swap audio data bytes sequence which read by the I2Sx peripheral.
+ * \param[in] I2Sx: To select I2Sx peripheral, where x can be: 0 or 1.
+ * \param[in] NewState: New state of the bytes sequence.
+ *      This parameter can be: ENABLE or DISABLE.
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void i2s_demo(void)
+ * {
+ *     I2S_SwapBytesForRead(I2S0, ENABLE);
+ * }
+ * \endcode
+ */
+void I2S_SwapBytesForRead(I2S_TypeDef *I2Sx, FunctionalState NewState);
+
+/**
+ * \brief  Swap audio channel data which sent by the I2Sx peripheral..
+ * \param[in] I2Sx: To select I2Sx peripheral, where x can be: 0 or 1.
+ * \param[in] NewState: New state of the left and right channel data sequence.
+ *      This parameter can be: ENABLE or DISABLE.
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void i2s_demo(void)
+ * {
+ *     I2S_SwapLRChDataForSend(I2S0, ENABLE);
+ * }
+ * \endcode
+ */
+void I2S_SwapLRChDataForSend(I2S_TypeDef *I2Sx, FunctionalState NewState);
+
+/**
+ * \brief   Swap audio channel data which read by the I2Sx peripheral.
+ * \param[in] I2Sx: To select I2Sx peripheral, where x can be: 0 or 1.
+ * \param[in] NewState: New state of the left and right channel data sequence.
+ *      This parameter can be: ENABLE or DISABLE.
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void i2s_demo(void)
+ * {
+ *     I2S_SwapLRChDataForRead(I2S0, ENABLE);
+ * }
+ * \endcode
+ */
+void I2S_SwapLRChDataForRead(I2S_TypeDef *I2Sx, FunctionalState NewState);
+
+/**
+ * \brief   MCLK output selection which can be from I2S0 or I2S1.
+ * \param[in] I2Sx: To select I2Sx peripheral, where x can be: 0 or 1.
+ * \param[in] NewState: New state of MCLK output.
+ *      This parameter can be: ENABLE or DISABLE.
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void i2s_demo(void)
+ * {
+ *     I2S_MCLKOutputSelectCmd(I2S0);
+ * }
+ * \endcode
+ */
+void I2S_MCLKOutputSelectCmd(I2S_TypeDef *I2Sx);
+
+/**
+ * \brief   I2S0 communication selection which can be from intrnal codec or external codec.
+ * \param[in] NewState: new state of I2S0 communication selection.
+ *      This parameter can be: ENABLE or DISABLE.
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void i2s_demo(void)
+ * {
+ *     I2S_WithExtCodecCmd(ENABLE);
+ * }
+ * \endcode
+ */
+void I2S_WithExtCodecCmd(I2S_TypeDef *I2Sx, FunctionalState NewState);
+
+
+/**
+ * \brief   Config BClk clock.
+ * \param[in] I2Sx: To select I2Sx peripheral, where x can be: 0 or 1.
+ * \param[in] I2S_BClockMi: Mi parameter.
+ * \param[in] I2S_BClockNi: Ni parameter.
+ * \return  Execution status.
+ * \retval  SET: Success.
+ * \retval  RESET: Failure.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void i2s_demo(void)
+ * {
+ *     FlagStatus status = I2S_UpdateBClk(I2S0, 0x271, 0x10);
+ * }
+ * \endcode
+ */
+void I2S_UpdateBClk(I2S_TypeDef *I2Sx, uint32_t dir, uint16_t I2S_BClockMi,
+                    uint16_t I2S_BClockNi);
+#if I2S_SUPPORT_TRX_INDEPENDENT_CONTROL
+/**
+ * \brief   Get BClk clock status.
+ * \param[in] I2Sx: To select I2Sx peripheral, where x can be: 0 or 1.
+ * \return  Execution status.
+ * \retval  SET: BLCK is updating.
+ * \retval  RESET: BLCK update is done.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void i2s_demo(void)
+ * {
+ *     FlagStatus status = I2S_GetTxBClkStatus(I2S0);
+ * }
+ * \endcode
+ */
+FlagStatus I2S_GetTxBClkStatus(I2S_TypeDef *I2Sx);
+
+/**
+ * \brief   Get BClk clock status.
+ * \param[in] I2Sx: To select I2Sx peripheral, where x can be: 0 or 1.
+ * \return  Execution status.
+ * \retval  SET: BLCK is updating.
+ * \retval  RESET: BLCK update is done.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void i2s_demo(void)
+ * {
+ *     FlagStatus status = I2S_GeRxBClkStatus(I2S0);
+ * }
+ * \endcode
+ */
+FlagStatus I2S_GetRxBClkStatus(I2S_TypeDef *I2Sx);
+
+#else
+/**
+ * \brief   Get BClk clock status.
+ * \param[in] I2Sx: To select I2Sx peripheral, where x can be: 0 or 1.
+ * \return  Execution status.
+ * \retval  SET: BLCK is updating.
+ * \retval  RESET: BLCK update is done.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void i2s_demo(void)
+ * {
+ *     FlagStatus status = I2S_GeRxBClkStatus(I2S0);
+ * }
+ * \endcode
+ */
+FlagStatus I2S_GetBClkStatus(I2S_TypeDef *I2Sx);
+
+
+#if (I2S_SUPPORT_AUTO_CLOCK == 1)
+void I2S_ClockAutoModeCmd(I2S_TypeDef *I2Sx, FunctionalState Newstate);
+#endif
+
+
+#endif
+/** End of I2S_Exported_Functions
+  * \}
+  */
+
+/** End of I2S
+  * \}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RTL_I2S_H */
+
+
+
+
diff --git a/bee/drivers/i2s/src/CMakeLists.txt b/bee/drivers/i2s/src/CMakeLists.txt
new file mode 100644
index 00000000..dd5e359a
--- /dev/null
+++ b/bee/drivers/i2s/src/CMakeLists.txt
@@ -0,0 +1,4 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+add_subdirectory(device)
diff --git a/bee/drivers/i2s/src/device/CMakeLists.txt b/bee/drivers/i2s/src/device/CMakeLists.txt
new file mode 100644
index 00000000..034df6a1
--- /dev/null
+++ b/bee/drivers/i2s/src/device/CMakeLists.txt
@@ -0,0 +1,6 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+add_soc_series_subdir(rtl8752h)
+add_soc_series_subdir(rtl87x2g)
+add_soc_series_subdir(rtl87x2j)
diff --git a/bee/drivers/i2s/src/device/rtl8752h/rtl876x_i2s.c b/bee/drivers/i2s/src/device/rtl8752h/rtl876x_i2s.c
new file mode 100644
index 00000000..00c84f0d
--- /dev/null
+++ b/bee/drivers/i2s/src/device/rtl8752h/rtl876x_i2s.c
@@ -0,0 +1,263 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "rtl876x_rcc.h"
+#include "rtl876x_i2s.h"
+#include "app_section.h"
+
+/**
+  * @brief Initializes the I2S peripheral according to the specified
+  *   parameters in the I2S_InitStruct
+  * @param  I2S: selected I2S peripheral.
+  * @param  I2S_InitStruct: pointer to a I2S_InitTypeDef structure that
+  *   contains the configuration information for the specified I2S peripheral
+  * @retval None
+  */
+void I2S_Init(I2S_TypeDef *I2Sx, I2S_InitTypeDef *I2S_InitStruct)
+{
+    /* Check the parameters */
+    assert_param(IS_I2S_ALL_PERIPH(I2Sx));
+    assert_param(IS_I2S_CLK_SOURCE(I2S_InitStruct->I2S_ClockSource));
+    assert_param(IS_I2S_DEVICE_MODE(I2S_InitStruct->I2S_DeviceMode));
+    assert_param(IS_I2S_CHANNEL_TYPE(I2S_InitStruct->I2S_ChannelType));
+    assert_param(IS_I2S_DATA_FORMAT(I2S_InitStruct->I2S_DataFormat));
+    assert_param(IS_I2S_DATA_WIDTH(I2S_InitStruct->I2S_DataWidth));
+    assert_param(IS_I2S_MCLK_OUTPUT_TYPE(I2S_InitStruct->I2S_MCLKOutput));
+    assert_param(IS_I2S_DMA_CMD(I2S_InitStruct->I2S_DMACmd));
+
+    /* Reset I2S module */
+    I2Sx->CTRL0 |= I2S_RESET_MSK;
+    I2Sx->CTRL0 &= I2S_RESET_CLR;
+
+    /* Configure BCLK parameters */
+    I2Sx->BCLK_DIV = I2S_InitStruct->I2S_BClockMi | (I2S_InitStruct->I2S_BClockNi << I2S_BCLK_NI_POS) |
+                     I2S_MI_NI_UPDATE_MSK;
+
+    /* Configure I2S initialization parameters */
+    I2Sx->CTRL0 = I2S_InitStruct->I2S_MCLKOutput | I2S_InitStruct->I2S_TxChSequence | I2S_RX_DISABLE_MSK
+                  | \
+                  I2S_InitStruct->I2S_RxBitSequence | I2S_InitStruct->I2S_TxBitSequence | \
+                  I2S_InitStruct->I2S_RxChSequence | I2S_TX_DISABLE_MSK | \
+                  I2S_InitStruct->I2S_DataWidth | I2S_InitStruct->I2S_ChannelType | \
+                  I2S_InitStruct->I2S_DataFormat | I2S_InitStruct->I2S_DeviceMode | I2S_InitStruct->I2S_DMACmd;
+
+    /* Configure I2S Clock Source parameters */
+    I2Sx->CTRL1 = I2S_InitStruct->I2S_ClockSource | I2S_CLR_RX_ERR_CNT_MSK | \
+                  I2S_CLR_TX_ERR_CNT_MSK | I2S_FRAME_SYNC_OFFSET_DEFAULT;
+    /* Clear error counter */
+    I2Sx->CTRL1 &= I2S_CLR_RX_ERR_CNT_CLR & I2S_CLR_TX_ERR_CNT_CLR;
+
+    /* Configure GDMA burst size */
+    I2Sx->DMA_TRDLR = (I2S_InitStruct->I2S_RxWaterlevel << I2S_RX_DMA_BURST_SIZE_POS) | \
+                      (I2S_InitStruct->I2S_TxWaterlevel << I2S_TX_DMA_BURST_SIZE_POS);
+}
+
+/**
+  * @brief  Deinitializes the I2S peripheral registers to their default values.
+  * @param  None.
+  * @retval None
+  */
+void I2S_DeInit(I2S_TypeDef *I2Sx)
+{
+    if (I2Sx == I2S0)
+    {
+        RCC_PeriphClockCmd(APBPeriph_I2S0, APBPeriph_I2S0_CLOCK, DISABLE);
+    }
+}
+
+/**
+  * @brief  Fills each I2S_InitStruct member with its default value.
+  * @param  I2S_InitStruct: pointer to an I2S_InitTypeDef structure which will be initialized.
+  * @retval None
+  */
+void I2S_StructInit(I2S_InitTypeDef *I2S_InitStruct)
+{
+    I2S_InitStruct->I2S_ClockSource     = I2S_CLK_40M;
+    I2S_InitStruct->I2S_BClockMi        = 0x271;/* <!BCLK = 16K */
+    I2S_InitStruct->I2S_BClockNi        = 0x10;
+    I2S_InitStruct->I2S_DeviceMode      = I2S_DeviceMode_Master;
+    I2S_InitStruct->I2S_ChannelType     = I2S_Channel_Mono;
+    I2S_InitStruct->I2S_TxChSequence    = I2S_TX_CH_L_R;
+    I2S_InitStruct->I2S_RxChSequence    = I2S_RX_CH_L_R;
+    I2S_InitStruct->I2S_DataFormat      = I2S_Mode;
+    I2S_InitStruct->I2S_TxBitSequence   = I2S_TX_MSB_First;
+    I2S_InitStruct->I2S_RxBitSequence   = I2S_RX_MSB_First;
+    I2S_InitStruct->I2S_DataWidth       = I2S_Width_16Bits;
+    I2S_InitStruct->I2S_MCLKOutput      = I2S_MCLK_128fs;
+    I2S_InitStruct->I2S_DMACmd          = I2S_DMA_ENABLE;
+    I2S_InitStruct->I2S_TxWaterlevel    = 1;
+    I2S_InitStruct->I2S_RxWaterlevel    = 1;
+}
+
+/**
+  * @brief   Enable or disable the selected I2S mode.
+  * @param  I2S: selected I2S peripheral.
+  * @param  mode: selected I2S operation mode.
+  *   This parameter can be the following values:
+  *     @arg I2S_MODE_TX: transmission mode.
+  *     @arg I2S_MODE_RX: receiving mode.
+  * @param  NewState: new state of the operation mode.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2S_Cmd(I2S_TypeDef *I2Sx, uint32_t mode, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_I2S_ALL_PERIPH(I2Sx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (NewState == ENABLE)
+    {
+        if (mode & I2S_MODE_TX)
+        {
+            I2Sx->CTRL0 &= I2S_TX_DISABLE_CLR;
+        }
+
+        if (mode & I2S_MODE_RX)
+        {
+            I2Sx->CTRL0 &= I2S_RX_DISABLE_CLR;
+        }
+        I2Sx->CTRL0 |= mode;
+    }
+    else
+    {
+        if (mode & I2S_MODE_TX)
+        {
+            I2Sx->CTRL0 |= I2S_TX_DISABLE_MSK;
+        }
+
+        if (mode & I2S_MODE_RX)
+        {
+            I2Sx->CTRL0 |= I2S_RX_DISABLE_MSK;
+        }
+        I2Sx->CTRL0 &= ~(mode);
+    }
+}
+
+/**
+  * @brief  Enable or disable the specified I2S interrupts.
+  * @param  I2S_INT: specifies the I2S interrupts sources to be enable or disable.
+  *   This parameter can be the following values:
+  *     @arg I2S_INT_TX_IDLE: Transmit idle interrupt.
+  *     @arg I2S_INT_RF_EMPTY: Receive FIFO empty interrupt.
+  *     @arg I2S_INT_TF_EMPTY: Transmit FIFO empty interrupt.
+  *     @arg I2S_INT_RF_FULL: Receive FIFO full interrupt.
+  *     @arg I2S_INT_TF_FULL: Transmit FIFO full interrupt.
+  *     @arg I2S_INT_RX_READY: Ready to receive interrupt.
+  *     @arg I2S_INT_TX_READY: Ready to transmit interrupt.
+  * @param  NewState: new state of the specified I2S interrupts.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2S_INTConfig(I2S_TypeDef *I2Sx, uint32_t I2S_INT, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_I2S_INT_CONFIG(I2S_INT));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (NewState == ENABLE)
+    {
+        I2Sx->CTRL1 |= I2S_INT;
+    }
+    else
+    {
+        I2Sx->CTRL1 &= ~(I2S_INT);
+    }
+}
+
+/**
+  * @brief Get the specified I2S flag status.
+  * @param  I2S_INT: the specified I2S interrupt.
+  * This parameter can be one of the following values:
+  *   This parameter can be the following values:
+  *     @arg I2S_INT_TX_IDLE: Transmit idle interrupt.
+  *     @arg I2S_INT_RF_EMPTY: Receive FIFO empty interrupt.
+  *     @arg I2S_INT_TF_EMPTY: Transmit FIFO empty interrupt.
+  *     @arg I2S_INT_RF_FULL: Receive FIFO full interrupt.
+  *     @arg I2S_INT_TF_FULL: Transmit FIFO full interrupt.
+  *     @arg I2S_INT_RX_READY: Ready to receive interrupt.
+  *     @arg I2S_INT_TX_READY: Ready to transmit interrupt.
+  * @retval The new state of LCD_FLAG (SET or RESET).
+  */
+ITStatus I2S_GetINTStatus(I2S_TypeDef *I2Sx, uint32_t I2S_INT)
+{
+    ITStatus bit_status = RESET;
+
+    /* Check the parameters */
+    assert_param(IS_I2S_INT_CONFIG(I2S_INT));
+
+    if (I2Sx->SR & (I2S_INT >> I2S_READY_TO_TX_POS))
+    {
+        bit_status = SET;
+    }
+
+    /* Return the I2S_INT status */
+    return  bit_status;
+}
+
+/**
+  * @brief  Clears the I2S interrupt pending bits.
+  * @param  I2S_CLEAR_INT: specifies the interrupt pending bit to clear.
+  *   This parameter can be any combination of the following values:
+  *     @arg I2S_CLEAR_INT_RX_READY: Clear ready to receive interrupt.
+  *     @arg I2S_CLEAR_INT_TX_READY: Clear ready to transmit interrupt.
+  * @retval None
+  */
+void I2S_ClearINTPendingBit(I2S_TypeDef *I2Sx, uint32_t I2S_CLEAR_INT)
+{
+    /* Check the parameters */
+    assert_param(IS_I2S_INT_CONFIG(I2S_CLEAR_INT));
+
+    I2Sx->DSP_INT_CR |= I2S_CLEAR_INT;
+    I2Sx->DSP_INT_CR &= ~I2S_CLEAR_INT;
+}
+
+/**
+  * \brief  Store I2S register values when system enter DLPS.
+  * \param  PeriReg: Specifies to select the I2S peripheral.
+  * \param  StoreBuf: Store buffer to store I2S register data.
+  * \return None.
+  */
+DATA_RAM_FUNCTION
+void I2S_DLPSEnter(void *PeriReg, void *StoreBuf)
+{
+    I2SStoreReg_TypeDef *store_buf = (I2SStoreReg_TypeDef *)StoreBuf;
+
+    RCC_PeriphClockCmd(APBPeriph_I2S0, APBPeriph_I2S0_CLOCK, ENABLE);
+
+    store_buf->i2s_reg[0] = I2S0->BCLK_DIV;
+    store_buf->i2s_reg[1] = I2S0->CTRL0;
+    store_buf->i2s_reg[2] = I2S0->CTRL1;
+    store_buf->i2s_reg[3] = I2S0->DMA_TRDLR;
+}
+
+/**
+  * \brief  Restore I2S register values when system exit DLPS.
+  * \param  PeriReg: Specifies to select the I2S peripheral.
+  * \param  StoreBuf: Restore buffer to restore I2S register data.
+  * \return None
+  */
+DATA_RAM_FUNCTION
+void I2S_DLPSExit(void *PeriReg, void *StoreBuf)
+{
+    I2SStoreReg_TypeDef *store_buf = (I2SStoreReg_TypeDef *)StoreBuf;
+
+    RCC_PeriphClockCmd(APBPeriph_I2S0, APBPeriph_I2S0_CLOCK, ENABLE);
+
+    /* Reset I2S0 module */
+    I2S0->CTRL0 |= 1 << 0;
+    I2S0->CTRL0 &= ~(1 << 0);
+
+    /* Initialize I2S0 */
+    I2S0->BCLK_DIV  = store_buf->i2s_reg[0];
+    I2S0->CTRL1     = store_buf->i2s_reg[2];
+    I2S0->DMA_TRDLR = store_buf->i2s_reg[3];
+    I2S0->CTRL0     = store_buf->i2s_reg[1];
+}
+
+
+
diff --git a/bee/drivers/i2s/src/device/rtl8752h/rtl876x_i2s.h b/bee/drivers/i2s/src/device/rtl8752h/rtl876x_i2s.h
new file mode 100644
index 00000000..8a0e2c03
--- /dev/null
+++ b/bee/drivers/i2s/src/device/rtl8752h/rtl876x_i2s.h
@@ -0,0 +1,1132 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *               Define to prevent recursive inclusion
+ *============================================================================*/
+#ifndef _RTL876x_I2S_H
+#define _RTL876x_I2S_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*============================================================================*
+ *                         Includes
+ *============================================================================*/
+#include "rtl876x.h"
+
+/*============================================================================*
+ *                    I2S register defines
+ *============================================================================*/
+
+/* Register: CTRL0 -------------------------------------------------------*/
+/* Description: Control register 0. Offset: 0x04. */
+
+/* CTRL0[30]: I2S_MCLK_SEL. */
+#define I2S_MCLK_SEL_POS                (30)
+#define I2S_MCLK_SEL_MSK                (0x1 << I2S_MCLK_SEL_POS)
+#define I2S_MCLK_SEL_CLR                (~I2S_MCLK_SEL_MSK)
+/* CTRL0[29:28]: I2S_RX_CH_SEQ. */
+#define I2S_RX_CH_SEQ_POS               (28)
+#define I2S_RX_CH_SEQ_MSK               (0x1 << I2S_RX_CH_SEQ_POS)
+#define I2S_RX_CH_SEQ_CLR               (~I2S_RX_CH_SEQ_MSK)
+/* CTRL0[25]: I2S_START_RX. */
+#define I2S_START_RX_POS                (25)
+#define I2S_START_RX_MSK                (0x1 << I2S_START_RX_POS)
+#define I2S_START_RX_CLR                (~I2S_START_RX_MSK)
+/* CTRL0[24]: I2S_RX_DISABLE. */
+#define I2S_RX_DISABLE_POS              (24)
+#define I2S_RX_DISABLE_MSK              (0x1 << I2S_RX_DISABLE_POS)
+#define I2S_RX_DISABLE_CLR              (~I2S_RX_DISABLE_MSK)
+/* CTRL0[23]: I2S_RX_LSB_FIRST. */
+#define I2S_RX_LSB_FIRST_POS            (23)
+#define I2S_RX_LSB_FIRST_MSK            (0x1 << I2S_RX_LSB_FIRST_POS)
+#define I2S_RX_LSB_FIRST_CLR            (~I2S_RX_LSB_FIRST_MSK)
+/* CTRL0[22]: I2S_TX_LSB_FIRST. */
+#define I2S_TX_LSB_FIRST_POS            (22)
+#define I2S_TX_LSB_FIRST_MSK            (0x1 << I2S_TX_LSB_FIRST_POS)
+#define I2S_TX_LSB_FIRST_CLR            (~I2S_TX_LSB_FIRST_MSK)
+/* CTRL0[21:20]: I2S_TX_CH_SEQ. */
+#define I2S_TX_CH_SEQ_POS               (20)
+#define I2S_TX_CH_SEQ_MSK               (0x1 << I2S_TX_CH_SEQ_POS)
+#define I2S_TX_CH_SEQ_CLR               (~I2S_TX_CH_SEQ_MSK)
+/* CTRL0[17]: I2S_START_TX. */
+#define I2S_START_TX_POS                (17)
+#define I2S_START_TX_MSK                (0x1 << I2S_START_TX_POS)
+#define I2S_START_TX_CLR                (~I2S_START_TX_MSK)
+/* CTRL0[16]: I2S_TX_DISABLE. */
+#define I2S_TX_DISABLE_POS              (16)
+#define I2S_TX_DISABLE_MSK              (0x1 << I2S_TX_DISABLE_POS)
+#define I2S_TX_DISABLE_CLR              (~I2S_TX_DISABLE_MSK)
+/* CTRL0[13:12]: I2S_DATA_WIDTH. */
+#define I2S_DATA_WIDTH_POS              (12)
+#define I2S_DATA_WIDTH_MSK              (0x3 << I2S_DATA_WIDTH_POS)
+#define I2S_DATA_WIDTH_CLR              (~I2S_DATA_WIDTH_MSK)
+/* CTRL0[11]: I2S_CHANNEL_TYPE. */
+#define I2S_CHANNEL_TYPE_POS            (11)
+#define I2S_CHANNEL_TYPE_MSK            (0x1 << I2S_CHANNEL_TYPE_POS)
+#define I2S_CHANNEL_TYPE_CLR            (~I2S_CHANNEL_TYPE_MSK)
+/* CTRL0[9:8]: I2S_DATA_FORMAT. */
+#define I2S_DATA_FORMAT_POS             (8)
+#define I2S_DATA_FORMAT_MSK             (0x3 << I2S_DATA_FORMAT_POS)
+#define I2S_DATA_FORMAT_CLR             (~I2S_DATA_FORMAT_MSK)
+/* CTRL0[7]: I2S_CTRL_MODE. */
+#define I2S_CTRL_MODE_POS              (7)
+#define I2S_CTRL_MODE_MSK              (0x1 << I2S_CTRL_MODE_POS)
+#define I2S_CTRL_MODE_CLR              (~I2S_CTRL_MODE_MSK)
+/* CTRL0[4]: I2S_SLAVE_DATA_SEL. */
+#define I2S_SLAVE_DATA_SEL_POS          (4)
+#define I2S_SLAVE_DATA_SEL_MSK          (0x1 << I2S_SLAVE_DATA_SEL_POS)
+#define I2S_SLAVE_DATA_SEL_CLR          (~I2S_SLAVE_DATA_SEL_MSK)
+/* CTRL0[3]: I2S_SLAVE_CLK_SEL. */
+#define I2S_SLAVE_CLK_SEL_POS           (3)
+#define I2S_SLAVE_CLK_SEL_MSK           (0x1 << I2S_SLAVE_CLK_SEL_POS)
+#define I2S_SLAVE_CLK_SEL_CLR           (~I2S_SLAVE_CLK_SEL_MSK)
+/* CTRL0[0]: I2S_RESET. */
+#define I2S_RESET_POS                   (0)
+#define I2S_RESET_MSK                   (0x1 << I2S_RESET_POS)
+#define I2S_RESET_CLR                   (~I2S_RESET_MSK)
+
+/* Register: CTRL1 -------------------------------------------------------*/
+/* Description: Control register 1. Offset: 0x08. */
+
+/* CTRL1[30]: I2S_TX_IDLE. */
+#define I2S_TX_IDLE_POS                 (30)
+#define I2S_TX_IDLE_MSK                 (0x1 << I2S_TX_IDLE_POS)
+#define I2S_TX_IDLE_CLR                 (~I2S_TX_IDLE_MSK)
+/* CTRL1[29]: I2S_RF_EMPTY. */
+#define I2S_RF_EMPTY_POS                (29)
+#define I2S_RF_EMPTY_MSK                (0x1 << I2S_RF_EMPTY_POS)
+#define I2S_RF_EMPTY_CLR                (~I2S_RF_EMPTY_MSK)
+/* CTRL1[28]: I2S_TF_EMPTY. */
+#define I2S_TF_EMPTY_POS                (28)
+#define I2S_TF_EMPTY_MSK                (0x1 << I2S_TF_EMPTY_POS)
+#define I2S_TF_EMPTY_CLR                (~I2S_TF_EMPTY_MSK)
+/* CTRL1[27]: I2S_RX_FULL. */
+#define I2S_RX_FULL_POS                 (27)
+#define I2S_RX_FULL_MSK                 (0x1 << I2S_RX_FULL_POS)
+#define I2S_RX_FULL_CLR                 (~I2S_RX_FULL_MSK)
+/* CTRL1[26]: I2S_TX_FULL. */
+#define I2S_TX_FULL_POS                 (26)
+#define I2S_TX_FULL_MSK                 (0x1 << I2S_TX_FULL_POS)
+#define I2S_TX_FULL_CLR                 (~I2S_TX_FULL_MSK)
+/* CTRL1[25]: I2S_READY_TO_RX. */
+#define I2S_READY_TO_RX_POS             (25)
+#define I2S_READY_TO_RX_MSK             (0x1 << I2S_READY_TO_RX_POS)
+#define I2S_READY_TO_RX_CLR             (~I2S_READY_TO_RX_MSK)
+/* CTRL1[24]: I2S_READY_TO_TX. */
+#define I2S_READY_TO_TX_POS             (24)
+#define I2S_READY_TO_TX_MSK             (0x1 << I2S_READY_TO_TX_POS)
+#define I2S_READY_TO_TX_CLR             (~I2S_READY_TO_TX_MSK)
+
+/* CTRL1[23]: I2S_RX_SNK_LR_SWAP. */
+#define I2S_RX_SNK_LR_SWAP_POS          (23)
+#define I2S_RX_SNK_LR_SWAP_MSK          (0x1 << I2S_RX_SNK_LR_SWAP_POS)
+#define I2S_RX_SNK_LR_SWAP_CLR          (~I2S_RX_SNK_LR_SWAP_MSK)
+/* CTRL1[22]: I2S_RX_SNK_BYTE_SWAP. */
+#define I2S_RX_SNK_BYTE_SWAP_POS        (22)
+#define I2S_RX_SNK_BYTE_SWAP_MSK        (0x1 << I2S_RX_SNK_BYTE_SWAP_POS)
+#define I2S_RX_SNK_BYTE_SWAP_CLR        (~I2S_RX_SNK_BYTE_SWAP_MSK)
+/* CTRL1[21]: I2S_TX_SRC_LR_SWAP. */
+#define I2S_TX_SRC_LR_SWAP_POS          (21)
+#define I2S_TX_SRC_LR_SWAP_MSK          (0x1 << I2S_TX_SRC_LR_SWAP_POS)
+#define I2S_TX_SRC_LR_SWAP_CLR          (~I2S_TX_SRC_LR_SWAP_MSK)
+/* CTRL1[20]: I2S_TX_SRC_BYTE_SWAP. */
+#define I2S_TX_SRC_BYTE_SWAP_POS        (20)
+#define I2S_TX_SRC_BYTE_SWAP_MSK        (0x1 << I2S_TX_SRC_BYTE_SWAP_POS)
+#define I2S_TX_SRC_BYTE_SWAP_CLR        (~I2S_TX_SRC_BYTE_SWAP_MSK)
+/* CTRL1[17]: I2S_CLK_128FS. */
+#define I2S_CLK_128FS_POS               (17)
+#define I2S_CLK_128FS_MSK               (0x1 << I2S_CLK_128FS_POS)
+#define I2S_CLK_128FS_CLR               (~I2S_CLK_128FS_MSK)
+/* CTRL1[16]: I2S_CLK_40M. */
+#define I2S_CLK_128_FS_POS              (16)
+#define I2S_CLK_128_FS_MSK              (0x1 << I2S_CLK_128_FS_POS)
+#define I2S_CLK_128_FS_CLR              (~I2S_CLK_128_FS_MSK)
+/* CTRL1[13]: I2S_CLR_RX_ERR_CNT. */
+#define I2S_CLR_RX_ERR_CNT_POS          (13)
+#define I2S_CLR_RX_ERR_CNT_MSK          (0x1 << I2S_CLR_RX_ERR_CNT_POS)
+#define I2S_CLR_RX_ERR_CNT_CLR          (~I2S_CLR_RX_ERR_CNT_MSK)
+/* CTRL1[12]: I2S_CLR_TX_ERR_CNT. */
+#define I2S_CLR_TX_ERR_CNT_POS          (12)
+#define I2S_CLR_TX_ERR_CNT_MSK          (0x1 << I2S_CLR_TX_ERR_CNT_POS)
+#define I2S_CLR_TX_ERR_CNT_CLR          (~I2S_CLR_TX_ERR_CNT_MSK)
+/* CTRL1[7:0]: I2S_FRAME_SYNC_OFFSET. */
+#define I2S_FRAME_SYNC_OFFSET_POS       (0)
+#define I2S_FRAME_SYNC_OFFSET_MSK       (0xFF << I2S_FRAME_SYNC_OFFSET_POS)
+#define I2S_FRAME_SYNC_OFFSET_CLR       (~I2S_FRAME_SYNC_OFFSET_MSK)
+#define I2S_FRAME_SYNC_OFFSET_DEFAULT   (0x81 << I2S_FRAME_SYNC_OFFSET_POS)
+
+/* Register: DSP_INT_CR -------------------------------------------------------*/
+/* Description: Interrupt clear register. Offset: 0x0C. */
+
+/* DSP_INT_CR[1]: I2S_RX_CLEAR_INT. */
+#define I2S_RX_CLEAR_INT_POS            (1)
+#define I2S_RX_CLEAR_INT_MSK            (0x1 << I2S_RX_CLEAR_INT_POS)
+#define I2S_RX_CLEAR_INT_CLR            (~I2S_RX_CLEAR_INT_MSK)
+/* DSP_INT_CR[0]: I2S_TX_CLEAR_INT. */
+#define I2S_TX_CLEAR_INT_POS            (0)
+#define I2S_TX_CLEAR_INT_MSK            (0x1 << I2S_TX_CLEAR_INT_POS)
+#define I2S_TX_CLEAR_INT_CLR            (~I2S_TX_CLEAR_INT_MSK)
+
+/* Register: FIFO_SR -------------------------------------------------------*/
+/* Description: FIFO status register. Offset: 0x14. */
+
+/* FIFO_SR[13:8]: I2S_RX_FIFO_DEPTH_CNT. */
+#define I2S_RX_FIFO_DEPTH_CNT_POS       (8)
+#define I2S_RX_FIFO_DEPTH_CNT_MSK       (0x3F << I2S_RX_FIFO_DEPTH_CNT_POS)
+#define I2S_RX_FIFO_DEPTH_CNT_CLR       (~I2S_RX_FIFO_DEPTH_CNT_MSK)
+/* FIFO_SR[5:0]: I2S_TX_FIFO_DEPTH_CNT. */
+#define I2S_TX_FIFO_DEPTH_CNT_POS       (0)
+#define I2S_TX_FIFO_DEPTH_CNT_MSK       (0x3F << I2S_TX_FIFO_DEPTH_CNT_POS)
+#define I2S_TX_FIFO_DEPTH_CNT_CLR       (~I2S_TX_FIFO_DEPTH_CNT_MSK)
+
+/* Register: ERROR_CNT_SR -------------------------------------------------------*/
+/* Description: Error counter status register. Offset: 0x18. */
+
+/* ERROR_CNT_SR[15:8]: I2S_RX_ERR_CNT. */
+#define I2S_RX_ERR_CNT_POS              (8)
+#define I2S_RX_ERR_CNT_MSK              (0xFF << I2S_RX_ERR_CNT_POS)
+#define I2S_RX_ERR_CNT_CLR              (~I2S_RX_ERR_CNT_MSK)
+/* ERROR_CNT_SR[7:0]: I2S_TX_ERR_CNT. */
+#define I2S_TX_ERR_CNT_POS              (0)
+#define I2S_TX_ERR_CNT_MSK              (0xFF << I2S_TX_ERR_CNT_POS)
+#define I2S_TX_ERR_CNT_CLR              (~I2S_TX_ERR_CNT_MSK)
+
+/* Register: BCLK_DIV -------------------------------------------------------*/
+/* Description: BCLK divider register. Offset: 0x1C. */
+
+/* BCLK_DIV[31]: I2S_MI_NI_UPDATE. */
+#define I2S_MI_NI_UPDATE_POS        (31)
+#define I2S_MI_NI_UPDATE_MSK        ((uint32_t)0x1 << I2S_MI_NI_UPDATE_POS)
+#define I2S_MI_NI_UPDATE_CLR        (~I2S_MI_NI_UPDATE_MSK)
+/* BCLK_DIV[30:16]: I2S_BCLK_NI. */
+#define I2S_BCLK_NI_POS             (16)
+#define I2S_BCLK_NI_MSK             (0x7FFF << I2S_BCLK_NI_POS)
+#define I2S_BCLK_NI_CLR             (~I2S_BCLK_NI_MSK)
+/* BCLK_DIV[15:0]: I2S_BCLK_MI. */
+#define I2S_BCLK_MI_POS             (0)
+#define I2S_BCLK_MI_MSK             (0xFFFF << I2S_BCLK_MI_POS)
+#define I2S_BCLK_MI_CLR             (~I2S_BCLK_MI_MSK)
+
+/* Register: DMA_TRDLR -------------------------------------------------------*/
+/* Description: DMA transmit receive data level register. Offset: 0x20. */
+
+/* DMA_TRDLR[5:0]: I2S_TX_DMA_BURST_SIZE. */
+#define I2S_TX_DMA_BURST_SIZE_POS   (0)
+#define I2S_TX_DMA_BURST_SIZE_MSK   (0x3F << I2S_TX_DMA_BURST_SIZE_POS)
+#define I2S_TX_DMA_BURST_SIZE_CLR   (~I2S_TX_DMA_BURST_SIZE_MSK)
+/* DMA_TRDLR[13:8]: I2S_RX_DMA_BURST_SIZE. */
+#define I2S_RX_DMA_BURST_SIZE_POS   (8)
+#define I2S_RX_DMA_BURST_SIZE_MSK   (0x3F << I2S_RX_DMA_BURST_SIZE_POS)
+#define I2S_RX_DMA_BURST_SIZE_CLR   (~I2S_RX_DMA_BURST_SIZE_MSK)
+
+/* Register: PERIPH_AUDIO_CLK_224 -------------------------------------------------------*/
+/* Description: peri on register. address: 0x40000224. */
+#define PERIPH_AUDIO_CLK_224        0x40000224
+/* PERIPH_AUDIO_CLK_224[3]: I2S0_EXT_CODEC. */
+#define I2S0_EXT_CODEC_POS         (3)
+#define I2S0_EXT_CODEC_MSK         (0x1 << I2S0_EXT_CODEC_POS)
+#define I2S0_EXT_CODEC_CLR         (~I2S0_EXT_CODEC_MSK)
+
+/* Register: PERIPH_AUDIO_CLK_228 -------------------------------------------------------*/
+/* Description: peri on register. address: 0x40000228. */
+#define PERIPH_AUDIO_CLK_228        0x40000228
+/* PERIPH_AUDIO_CLK_228[4]: I2S_MCLK_OUTPUT. */
+#define I2S_MCLK_OUTPUT_POS         (4)
+#define I2S_MCLK_OUTPUT_MSK         (0x1 << I2S_MCLK_OUTPUT_POS)
+#define I2S_MCLK_OUTPUT_CLR         (~I2S_MCLK_OUTPUT_MSK)
+
+/**
+ * \addtogroup  IO          Peripheral Drivers
+ * \defgroup    I2S         I2S
+ *
+ * \brief       Manage the I2S peripheral functions.
+ *
+ * \ingroup     IO
+ */
+
+/*============================================================================*
+ *                         Types
+ *============================================================================*/
+/**
+ * \defgroup    I2S_Exported_Types I2S Exported Types
+ * \{
+ * \ingroup     I2S
+ */
+
+/**
+ * \brief       I2S initialize parameters.
+ *
+ * \ingroup     I2S_Exported_Types
+ */
+typedef struct
+{
+    uint32_t I2S_ClockSource;           /*!< Specify the I2S clock source.
+                                        This parameter can be a value of \ref I2S_clock_Source. */
+    uint32_t I2S_BClockMi;              /*!< Specify the BLCK clock speed. BCLK = 40MHz*(I2S_BClockNi/I2S_BClockMi).
+                                        This parameter must range from 1 to 0xffff. */
+    uint32_t I2S_BClockNi;              /*!< Specify the BLCK clock speed.
+                                        This parameter must range from 1 to 0x7FFF. */
+    uint32_t I2S_DeviceMode;            /*!< Specify the I2S device mode.
+                                        This parameter can be a value of \ref I2S_device_mode. */
+    uint32_t I2S_ChannelType;           /*!< Specify the channel type used for the I2S communication.
+                                        This parameter can be a value of \ref I2S_Channel_Type. */
+    uint32_t I2S_TxChSequence;          /*!< Specify the transmission channel sequence used for the I2S communication.
+                                        This parameter can be a value of \ref I2S_Tx_Ch_Sequence. */
+    uint32_t I2S_RxChSequence;          /*!< Specify the receiving channel sequence used for the I2S communication.
+                                        This parameter can be a value of \ref I2S_Rx_Ch_Sequence. */
+    uint32_t I2S_DataFormat;            /*!< Specify the I2S data format mode.
+                                        This parameter can be a value of \ref I2S_Format_Mode.*/
+    uint32_t I2S_TxBitSequence;         /*!< Specify the I2S data bits sequences.
+                                        This parameter can be a value of \ref I2S_Tx_Bit_Sequence.*/
+    uint32_t I2S_RxBitSequence;         /*!< Specify the I2S data bits sequences.
+                                        This parameter can be a value of \ref I2S_Rx_Bit_Sequence.*/
+    uint32_t I2S_DataWidth;             /*!< Specify the I2S data width.
+                                        This parameter can be a value of \ref I2S_Data_Width. */
+    uint32_t I2S_MCLKOutput;            /*!< Specify the I2S MCLK output frequency.
+                                        This parameter can be a value of \ref I2S_MCLK_Output. */
+    uint32_t I2S_DMACmd;                 /*!< Specify the I2S DMA control.
+                                        This parameter can be a value of \ref FunctionalState. */
+    uint32_t I2S_TxWaterlevel;          /*!< Specify the DMA watermark level in transmit mode.
+                                        This parameter must range from 1 to 63.  */
+    uint32_t I2S_RxWaterlevel;          /*!< Specify the DMA watermark level in receive mode.
+                                        This parameter must range from 1 to 63.  */
+} I2S_InitTypeDef;
+
+/** End of I2S_Exported_Types
+  * \}
+  */
+
+/*============================================================================*
+ *                         Constants
+ *============================================================================*/
+/**
+ * \defgroup    I2S_Exported_Constants I2S Exported Constants
+ *
+ * \ingroup     I2S
+ */
+
+#define IS_I2S_ALL_PERIPH(PERIPH) (((PERIPH) == I2S0) || \
+                                   ((PERIPH) == I2S1))
+
+/**
+ * \defgroup    I2S_clock_Source  I2S Clock Source
+ * \{
+ * \ingroup     I2S_Exported_Constants
+ */
+
+#define I2S_CLK_40M                                 (I2S_CLK_128_FS_MSK)
+#define I2S_CLK_128fs                               (I2S_CLK_128FS_MSK)
+#define I2S_CLK_256fs                               ((uint32_t)(0x00))
+
+#define IS_I2S_CLK_SOURCE(CLK)          (((CLK) == I2S_CLK_40M) || \
+                                         ((CLK) == I2S_CLK_128fs) || \
+                                         ((CLK) == I2S_CLK_256fs))
+/** \} */
+
+/**
+ * \defgroup    I2S_device_mode I2S Device Mode
+ * \{
+ * \ingroup     I2S_Exported_Constants
+ */
+#define I2S_DeviceMode_Master                       ((uint32_t)0x00)
+#define I2S_DeviceMode_Slave                        (I2S_SLAVE_DATA_SEL_MSK) //| I2S_SLAVE_CLK_SEL_MSK)
+
+#define IS_I2S_DEVICE_MODE(DEVICE)      (((DEVICE) == I2S_DeviceMode_Master) || ((DEVICE) == I2S_DeviceMode_Slave))
+/** \} */
+
+/**
+ * \defgroup    I2S_Mode I2S Mode
+ * \{
+ * \ingroup     I2S_Exported_Constants
+ */
+#define I2S_MODE_TX                                 (I2S_START_TX_MSK)
+#define I2S_MODE_RX                                 (I2S_START_RX_MSK)
+
+#define IS_I2S_MODE(MODE)               (((MODE) == I2S_MODE_TX) || ((MODE) == I2S_MODE_RX))
+/** \} */
+
+/**
+ * \defgroup    I2S_Channel_Type I2S Channel Type
+ * \{
+ * \ingroup     I2S_Exported_Constants
+ */
+#define I2S_Channel_Mono                            (I2S_CHANNEL_TYPE_MSK)
+#define I2S_Channel_stereo                          ((uint32_t)(0x0))
+
+#define IS_I2S_CHANNEL_TYPE(TYPE)       (((TYPE) == I2S_Channel_Mono) || ((TYPE) == I2S_Channel_stereo))
+/** \} */
+
+/**
+ * \defgroup    I2S_Tx_Ch_Sequence I2S Transmission Channel Sequence
+ * \{
+ * \ingroup     I2S_Exported_Constants
+ */
+#define I2S_TX_CH_L_R                           (0)
+#define I2S_TX_CH_R_L                           ((uint32_t)0x01 << I2S_TX_CH_SEQ_POS)
+#define I2S_TX_CH_L_L                           ((uint32_t)0x02 << I2S_TX_CH_SEQ_POS)
+#define I2S_TX_CH_R_R                           ((uint32_t)0x03 << I2S_TX_CH_SEQ_POS)
+
+#define IS_I2S_TX_CH_SEQ(SEQ)       (((SEQ) == I2S_TX_CH_L_R) || ((SEQ) == I2S_TX_CH_R_L) || \
+                                     ((SEQ) == I2S_TX_CH_L_L) || ((SEQ) == I2S_TX_CH_R_R))
+/** \} */
+
+/**
+ * \defgroup    I2S_Rx_Ch_Sequence I2S Receiving Channel Sequence
+ * \{
+ * \ingroup     I2S_Exported_Constants
+ */
+#define I2S_RX_CH_L_R                           (0)
+#define I2S_RX_CH_R_L                           ((uint32_t)0x01 << I2S_RX_CH_SEQ_POS)
+#define I2S_RX_CH_L_L                           ((uint32_t)0x02 << I2S_RX_CH_SEQ_POS)
+#define I2S_RX_CH_R_R                           ((uint32_t)0x03 << I2S_RX_CH_SEQ_POS)
+/** \} */
+
+#define IS_I2S_RX_CH_SEQ(SEQ)       (((SEQ) == I2S_RX_CH_L_R) || ((SEQ) == I2S_RX_CH_R_L) || \
+                                     ((SEQ) == I2S_RX_CH_L_L) || ((SEQ) == I2S_RX_CH_R_R))
+
+/**
+ * \defgroup    I2S_Format_Mode I2S Format Mode
+ * \{
+ * \ingroup     I2S_Exported_Constants
+ */
+#define I2S_Mode                                    ((uint32_t)(0x00 << I2S_DATA_FORMAT_POS))
+#define Left_Justified_Mode                         ((uint32_t)(0x01 << I2S_DATA_FORMAT_POS))
+#define PCM_Mode_A                                  ((uint32_t)(0x02 << I2S_DATA_FORMAT_POS))
+#define PCM_Mode_B                                  ((uint32_t)(0x03 << I2S_DATA_FORMAT_POS))
+
+#define IS_I2S_DATA_FORMAT(FORMAT)      (((FORMAT) == I2S_Mode) || ((FORMAT) == Left_Justified_Mode) || \
+                                         ((FORMAT) == PCM_Mode_A) || ((FORMAT) == PCM_Mode_B))
+/** \} */
+
+/**
+ * \defgroup    I2S_Tx_Bit_Sequence I2S Tx Bit Sequence
+ * \{
+ * \ingroup     I2S_Exported_Constants
+ */
+#define I2S_TX_MSB_First                            ((uint32_t)0x0)
+#define I2S_TX_LSB_First                            (I2S_TX_LSB_FIRST_MSK)
+
+#define IS_I2S_TX_BIT_SEQ(SEQ)      (((SEQ) == I2S_TX_MSB_First) || ((SEQ) == I2S_TX_LSB_First))
+/** \} */
+
+/**
+ * \defgroup    I2S_Rx_Bit_Sequence I2S Rx Bit Sequence
+ * \{
+ * \ingroup     I2S_Exported_Constants
+ */
+#define I2S_RX_MSB_First                            ((uint32_t)0x0)
+#define I2S_RX_LSB_First                            (I2S_RX_LSB_FIRST_MSK)
+
+#define IS_I2S_RX_BIT_SEQ(SEQ)      (((SEQ) == I2S_RX_MSB_First) || ((SEQ) == I2S_RX_LSB_First))
+/** \} */
+
+/**
+ * \defgroup    I2S_Data_Width I2S Data Width
+ * \{
+ * \ingroup     I2S_Exported_Constants
+ */
+#define I2S_Width_16Bits                            ((uint32_t)(0x00 << I2S_DATA_WIDTH_POS))
+#define I2S_Width_24Bits                            ((uint32_t)(0x02 << I2S_DATA_WIDTH_POS))
+#define I2S_Width_8Bits                             ((uint32_t)(0x03 << I2S_DATA_WIDTH_POS))
+
+#define IS_I2S_DATA_WIDTH(WIDTH)        (((WIDTH) == I2S_Width_16Bits) || \
+                                         ((WIDTH) == I2S_Width_24Bits) || \
+                                         ((WIDTH) == I2S_Width_8Bits))
+/** \} */
+
+/**
+ * \defgroup    I2S_MCLK_Output I2S MCLK Output
+ * \{
+ * \ingroup     I2S_Exported_Constants
+ */
+#define I2S_MCLK_128fs                              ((uint32_t)0x0)
+#define I2S_MCLK_256fs                              (I2S_MCLK_SEL_MSK)
+
+#define IS_I2S_MCLK_OUTPUT_TYPE(TYPE)       (((TYPE) == I2S_MCLK_128fs) || ((TYPE) == I2S_MCLK_256fs))
+/** \} */
+
+/**
+ * \defgroup    I2S_DMA_Cmd I2S DMA Cmd
+ * \{
+ * \ingroup     I2S_Exported_Constants
+ */
+#define I2S_DMA_ENABLE                              ((uint32_t)0x0)
+#define I2S_DMA_DISABLE                             (I2S_CTRL_MODE_MSK)
+
+#define IS_I2S_DMA_CMD(CMD)       (((CMD) == I2S_DMA_ENABLE) || ((CMD) == I2S_DMA_DISABLE))
+/** \} */
+
+/**
+ * \defgroup    I2S_Interrupts_Definition I2S Interrupts Definition
+ * \{
+ * \ingroup     I2S_Exported_Constants
+ */
+#define I2S_INT_TX_IDLE                             (I2S_TX_IDLE_MSK)
+#define I2S_INT_RF_EMPTY                            (I2S_RF_EMPTY_MSK)
+#define I2S_INT_TF_EMPTY                            (I2S_TF_EMPTY_MSK)
+#define I2S_INT_RF_FULL                             (I2S_RX_FULL_MSK)
+#define I2S_INT_TF_FULL                             (I2S_TX_FULL_MSK)
+#define I2S_INT_RX_READY                            (I2S_READY_TO_RX_MSK)
+#define I2S_INT_TX_READY                            (I2S_READY_TO_TX_MSK)
+
+#define IS_I2S_INT_CONFIG(INT)          (((INT) == I2S_INT_TX_IDLE) || ((INT) == I2S_INT_RF_EMPTY) || \
+                                         ((INT) == I2S_INT_TF_EMPTY) || ((INT) == I2S_INT_RF_FULL) || \
+                                         ((INT) == I2S_INT_TF_FULL) || ((INT) == I2S_INT_RX_READY) || \
+                                         ((INT) == I2S_INT_TX_READY) )
+/** \} */
+
+/**
+ * \defgroup    I2S_Clear_Interrupts_Definition I2S Clear Interrupts Definition
+ * \{
+ * \ingroup     I2S_Exported_Constants
+ */
+#define I2S_CLEAR_INT_RX_READY                      (I2S_RX_CLEAR_INT_MSK)
+#define I2S_CLEAR_INT_TX_READY                      (I2S_TX_CLEAR_INT_MSK)
+
+#define IS_I2S_CLEAR_INT(CLEAR)          (((CLEAR) == I2S_CLEAR_INT_RX_READY) || \
+                                          ((CLEAR) == I2S_CLEAR_INT_TX_READY) )
+/** \} */
+
+/** End of I2S_Exported_Constants
+  * \}
+  */
+
+/*============================================================================*
+ *                         Functions
+ *============================================================================*/
+
+/**
+ * \defgroup    I2S_Exported_Functions I2S Exported Functions
+ * \{
+ * \ingroup     I2S
+ */
+
+/**
+ * \brief Initialize the I2S peripheral according to the specified
+ *   parameters in the I2S_InitStruct
+ * \param[in]  I2Sx: selected I2S peripheral.
+ * \param[in]  I2S_InitStruct: pointer to an I2S_InitTypeDef structure that
+ *   contains the configuration information for the specified I2S peripheral
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_i2s_init(void)
+ * {
+ *     RCC_PeriphClockCmd(APB_I2S, APB_I2S_CLOCK, ENABLE);
+ *
+ *     I2S_InitTypeDef I2S_InitStruct;
+ *
+ *     I2S_StructInit(&I2S_InitStruct);
+ *     I2S_InitStruct.I2S_ClockSource      = I2S_CLK_40M;
+ *
+ *     I2S_InitStruct.I2S_BClockMi         = 0x271;
+ *     I2S_InitStruct.I2S_BClockNi         = 0x10;
+ *     I2S_InitStruct.I2S_DeviceMode       = I2S_DeviceMode_Master;
+ *     I2S_InitStruct.I2S_ChannelType      = I2S_Channel_stereo;
+ *     I2S_InitStruct.I2S_DataWidth        = I2S_Width_16Bits;
+ *     I2S_InitStruct.I2S_DataFormat       = I2S_Mode;
+ *     I2S_InitStruct.I2S_DMACmd           = I2S_DMA_DISABLE;
+ *     I2S_Init(I2S_NUM, &I2S_InitStruct);
+ *     I2S_Cmd(I2S_NUM, I2S_MODE_TX, ENABLE);
+ * }
+ * \endcode
+ */
+void I2S_Init(I2S_TypeDef *I2Sx, I2S_InitTypeDef *I2S_InitStruct);
+
+/**
+ * \brief  Deinitialize the I2S peripheral registers to their default values.
+ * \param[in]  I2Sx: selected I2S peripheral.
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_i2s_init(void)
+ * {
+ *     I2S_DeInit(I2S0);
+ * }
+ * \endcode
+ */
+void I2S_DeInit(I2S_TypeDef *I2Sx);
+
+/**
+ * \brief  Fill each I2S_InitStruct member with its default value.
+ * \param[in]  I2S_InitStruct: pointer to an I2S_InitTypeDef structure which will be initialized.
+ * \return None
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_i2s_init(void)
+ * {
+ *     RCC_PeriphClockCmd(APB_I2S, APB_I2S_CLOCK, ENABLE);
+ *
+ *     I2S_InitTypeDef I2S_InitStruct;
+ *
+ *     I2S_StructInit(&I2S_InitStruct);
+ *     I2S_InitStruct.I2S_ClockSource      = I2S_CLK_40M;
+ *
+ *     I2S_InitStruct.I2S_BClockMi         = 0x271;
+ *     I2S_InitStruct.I2S_BClockNi         = 0x10;
+ *     I2S_InitStruct.I2S_DeviceMode       = I2S_DeviceMode_Master;
+ *     I2S_InitStruct.I2S_ChannelType      = I2S_Channel_stereo;
+ *     I2S_InitStruct.I2S_DataWidth        = I2S_Width_16Bits;
+ *     I2S_InitStruct.I2S_DataFormat       = I2S_Mode;
+ *     I2S_InitStruct.I2S_DMACmd           = I2S_DMA_DISABLE;
+ *     I2S_Init(I2S_NUM, &I2S_InitStruct);
+ *     I2S_Cmd(I2S_NUM, I2S_MODE_TX, ENABLE);
+ * }
+ * \endcode
+ */
+void I2S_StructInit(I2S_InitTypeDef *I2S_InitStruct);
+
+/**
+ * \brief   Enable or disable the selected I2S mode.
+ * \param[in]  I2Sx: selected I2S peripheral.
+ * \param[in]  mode: selected I2S operation mode.
+ *   This parameter can be the following values:
+ *     \arg I2S_MODE_TX: transmission mode.
+ *     \arg I2S_MODE_RX: receiving mode.
+ * \param[in]  NewState: new state of the operation mode.
+ *   This parameter can be: ENABLE or DISABLE.
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_i2s_init(void)
+ * {
+ *     RCC_PeriphClockCmd(APB_I2S, APB_I2S_CLOCK, ENABLE);
+ *
+ *     I2S_InitTypeDef I2S_InitStruct;
+ *
+ *     I2S_StructInit(&I2S_InitStruct);
+ *     I2S_InitStruct.I2S_ClockSource      = I2S_CLK_40M;
+ *
+ *     I2S_InitStruct.I2S_BClockMi         = 0x271;
+ *     I2S_InitStruct.I2S_BClockNi         = 0x10;
+ *     I2S_InitStruct.I2S_DeviceMode       = I2S_DeviceMode_Master;
+ *     I2S_InitStruct.I2S_ChannelType      = I2S_Channel_stereo;
+ *     I2S_InitStruct.I2S_DataWidth        = I2S_Width_16Bits;
+ *     I2S_InitStruct.I2S_DataFormat       = I2S_Mode;
+ *     I2S_InitStruct.I2S_DMACmd           = I2S_DMA_DISABLE;
+ *     I2S_Init(I2S_NUM, &I2S_InitStruct);
+ *     I2S_Cmd(I2S_NUM, I2S_MODE_TX, ENABLE);
+ * }
+ * \endcode
+ */
+void I2S_Cmd(I2S_TypeDef *I2Sx, uint32_t mode, FunctionalState NewState);
+
+/**
+ * \brief  Enable or disable the specified I2S interrupts.
+ * \param[in]  I2S_INT: Specify the I2S interrupt sources to be enable or disable.
+ *   This parameter can be the following values:
+ *     \arg I2S_INT_TX_IDLE: Transmit idle interrupt.
+ *     \arg I2S_INT_RF_EMPTY: Receive FIFO empty interrupt.
+ *     \arg I2S_INT_TF_EMPTY: Transmit FIFO empty interrupt.
+ *     \arg I2S_INT_RF_FULL: Receive FIFO full interrupt.
+ *     \arg I2S_INT_TF_FULL: Transmit FIFO full interrupt.
+ *     \arg I2S_INT_RX_READY: Ready to receive interrupt.
+ *     \arg I2S_INT_TX_READY: Ready to transmit interrupt.
+ * \param[in]  NewState: new state of the specified I2S interrupts.
+ *   This parameter can be: ENABLE or DISABLE.
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void i2s_demo(void)
+ * {
+ *     I2S_INTConfig(I2S_NUM, I2S_INT_RX_READY, ENABLE);
+ *
+ *     NVIC_InitTypeDef NVIC_InitStruct;
+ *     NVIC_InitStruct.NVIC_IRQChannel = I2S0_RX_IRQn;
+ *     NVIC_InitStruct.NVIC_IRQChannelPriority = 3;
+ *     NVIC_InitStruct.NVIC_IRQChannelCmd = ENABLE;
+ *     NVIC_Init(&NVIC_InitStruct);
+ * }
+ * \endcode
+ */
+void I2S_INTConfig(I2S_TypeDef *I2Sx, uint32_t I2S_INT, FunctionalState newState);
+
+/**
+ * \brief Get the specified I2S flag status.
+ * \param[in]  I2S_INT: the specified I2S interrupt.
+ * This parameter can be one of the following values, which refers to \ref I2S_Interrupts_Definition.
+ *     \arg I2S_INT_TX_IDLE: Transmit idle interrupt.
+ *     \arg I2S_INT_RF_EMPTY: Receive FIFO empty interrupt.
+ *     \arg I2S_INT_TF_EMPTY: Transmit FIFO empty interrupt.
+ *     \arg I2S_INT_RF_FULL: Receive FIFO full interrupt.
+ *     \arg I2S_INT_TF_FULL: Transmit FIFO full interrupt.
+ *     \arg I2S_INT_RX_READY: Ready to receive interrupt.
+ *     \arg I2S_INT_TX_READY: Ready to transmit interrupt.
+ * \return The new state of I2S_FLAG (SET or RESET).
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void I2S0_RX_Handler(void)
+ * {
+ *     ITStatus int_status = I2S_GetINTStatus(I2S0, I2S_INT_RX_READY);
+ * }
+ * \endcode
+ */
+ITStatus I2S_GetINTStatus(I2S_TypeDef *I2Sx, uint32_t I2S_INT);
+
+/**
+ * \brief  Clear the I2S interrupt pending bits.
+ * \param[in]  I2S_CLEAR_INT: Specify the interrupt pending bit to clear.
+ *   This parameter can be any combination of the following values, which refers to \ref I2S_Clear_Interrupts_Definition.
+ *     \arg I2S_CLEAR_INT_RX_READY: Clear ready to receive interrupt.
+ *     \arg I2S_CLEAR_INT_TX_READY: Clear ready to transmit interrupt.
+ * \return None
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void I2S0_RX_Handler(void)
+ * {
+ *     I2S_ClearINTPendingBit(I2S0, I2S_INT_RX_READY);
+ * }
+ * \endcode
+ */
+void I2S_ClearINTPendingBit(I2S_TypeDef *I2Sx, uint32_t I2S_CLEAR_INT);
+
+/**
+ * \brief  Transmit data through the SPIx/I2Sx peripheral.
+ * \param[in]  I2Sx: To select the I2Sx peripheral, x can be 0 or 1.
+ * \param[in]  Data: Data to be transmitted.
+ * \return None
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void i2s_demo(void)
+ * {
+ *     I2S_SendData(I2S0, 0x12348800);
+ * }
+ * \endcode
+ */
+__STATIC_INLINE void I2S_SendData(I2S_TypeDef *I2Sx, uint32_t Data)
+{
+    /* Check the parameters */
+    assert_param(IS_I2S_ALL_PERIPH(I2Sx));
+
+    I2Sx->TX_DR = Data;
+}
+
+/**
+ * \brief  Return the most recent received data by the I2Sx peripheral.
+ * \param[in]  I2Sx: To select I2Sx peripheral, where x can be: 0 or 1.
+ * \return The value of the received data.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void i2s_demo(void)
+ * {
+ *     uint32_t data = I2S_ReceiveData(I2S0);
+ * }
+ * \endcode
+ */
+__STATIC_INLINE uint32_t I2S_ReceiveData(I2S_TypeDef *I2Sx)
+{
+    /* Check the parameters */
+    assert_param(IS_I2S_ALL_PERIPH(I2Sx));
+
+    return I2Sx->RX_DR;
+}
+
+/**
+ * \brief  Return the transmit FIFO free length of the I2Sx peripheral.
+ * \param[in]  I2Sx: To select I2Sx peripheral, where x can be: 0 or 1.
+ * \return The free length of the transmit FIFO.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void i2s_demo(void)
+ * {
+ *     if (I2S_GetTxFIFOFreeLen(I2S0))
+ *     {
+ *         I2S_SendData(I2S0, i++);
+ *     }
+ * }
+ * \endcode
+ */
+__STATIC_INLINE uint8_t I2S_GetTxFIFOFreeLen(I2S_TypeDef *I2Sx)
+{
+    /* Check the parameters */
+    assert_param(IS_I2S_ALL_PERIPH(I2Sx));
+
+    return ((I2Sx->FIFO_SR & I2S_TX_FIFO_DEPTH_CNT_MSK) >> I2S_TX_FIFO_DEPTH_CNT_POS);
+}
+
+/**
+ * \brief  Return the receive FIFO data length of the I2Sx peripheral.
+ * \param[in]  I2Sx: To select I2Sx peripheral, where x can be: 0 or 1.
+ * \return The data length of the receive FIFO.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void i2s_demo(void)
+ * {
+ *     uint8_t len = I2S_GetRxFIFOLen(I2S0);
+ * }
+ * \endcode
+ */
+__STATIC_INLINE uint8_t I2S_GetRxFIFOLen(I2S_TypeDef *I2Sx)
+{
+    /* Check the parameters */
+    assert_param(IS_I2S_ALL_PERIPH(I2Sx));
+
+    return ((I2Sx->FIFO_SR & I2S_RX_FIFO_DEPTH_CNT_MSK) >> I2S_RX_FIFO_DEPTH_CNT_POS);
+}
+
+/**
+ * \brief  Return the send error counter value of the I2Sx peripheral.
+ * \param[in]  I2Sx: To select I2Sx peripheral, where x can be: 0 or 1.
+ * \return The send error counter value.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void i2s_demo(void)
+ * {
+ *     uint8_t len = I2S_GetTxErrCnt(I2S0);
+ * }
+ * \endcode
+ */
+__STATIC_INLINE uint8_t I2S_GetTxErrCnt(I2S_TypeDef *I2Sx)
+{
+    /* Check the parameters */
+    assert_param(IS_I2S_ALL_PERIPH(I2Sx));
+
+    return ((I2Sx->ERROR_CNT_SR & I2S_TX_ERR_CNT_MSK) >> I2S_TX_ERR_CNT_POS);
+}
+
+/**
+ * \brief  Return the reception error counter value of the I2Sx peripheral.
+ * \param[in]  I2Sx: To select I2Sx peripheral, where x can be: 0 or 1.
+ * \return The reception error counter value.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void i2s_demo(void)
+ * {
+ *     uint8_t len = I2S_GetRxErrCnt(I2S0);
+ * }
+ * \endcode
+ */
+__STATIC_INLINE uint8_t I2S_GetRxErrCnt(I2S_TypeDef *I2Sx)
+{
+    /* Check the parameters */
+    assert_param(IS_I2S_ALL_PERIPH(I2Sx));
+
+    return ((I2Sx->ERROR_CNT_SR & I2S_RX_ERR_CNT_MSK) >> I2S_RX_ERR_CNT_POS);
+}
+
+/**
+ * \brief   Swap audio data byte sequence sent by the I2Sx peripheral.
+ * \param[in]  I2Sx: To select I2Sx peripheral, where x can be: 0 or 1.
+ * \param[in]  NewState: New state of the byte sequence.
+ *   This parameter can be: ENABLE or DISABLE.
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void i2s_demo(void)
+ * {
+ *     I2S_SwapBytesForSend(I2S0, ENABLE);
+ * }
+ * \endcode
+ */
+__STATIC_INLINE void I2S_SwapBytesForSend(I2S_TypeDef *I2Sx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_I2S_ALL_PERIPH(I2Sx));
+
+    if (NewState == ENABLE)
+    {
+        I2Sx->CTRL1 |= I2S_TX_SRC_BYTE_SWAP_MSK;
+    }
+    else
+    {
+        I2Sx->CTRL1 &= I2S_TX_SRC_BYTE_SWAP_CLR;
+    }
+}
+
+/**
+ * \brief  Swap audio data byte sequence read by the I2Sx peripheral.
+ * \param[in]  I2Sx: To select I2Sx peripheral, where x can be: 0 or 1.
+ * \param[in]  NewState: New state of the byte sequence.
+ *   This parameter can be: ENABLE or DISABLE.
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void i2s_demo(void)
+ * {
+ *     I2S_SwapBytesForRead(I2S0, ENABLE);
+ * }
+ * \endcode
+ */
+__STATIC_INLINE void I2S_SwapBytesForRead(I2S_TypeDef *I2Sx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_I2S_ALL_PERIPH(I2Sx));
+
+    if (NewState == ENABLE)
+    {
+        I2Sx->CTRL1 |= I2S_RX_SNK_BYTE_SWAP_MSK;
+    }
+    else
+    {
+        I2Sx->CTRL1 &= I2S_RX_SNK_BYTE_SWAP_CLR;
+    }
+}
+
+/**
+ * \brief  Swap audio channel data sent by the I2Sx peripheral.
+ * \param[in]  I2Sx: To select I2Sx peripheral, where x can be: 0 or 1.
+ * \param[in]  NewState: New state of the left and right channel data sequence.
+ *   This parameter can be: ENABLE or DISABLE.
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void i2s_demo(void)
+ * {
+ *     I2S_SwapLRChDataForSend(I2S0, ENABLE);
+ * }
+ * \endcode
+ */
+__STATIC_INLINE void I2S_SwapLRChDataForSend(I2S_TypeDef *I2Sx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_I2S_ALL_PERIPH(I2Sx));
+
+    if (NewState == ENABLE)
+    {
+        I2Sx->CTRL1 |= I2S_TX_SRC_LR_SWAP_MSK;
+    }
+    else
+    {
+        I2Sx->CTRL1 &= I2S_TX_SRC_LR_SWAP_CLR;
+    }
+}
+
+/**
+ * \brief Swap audio channel data read by the I2Sx peripheral.
+ * \param[in]  I2Sx: To select I2Sx peripheral, where x can be: 0 or 1.
+ * \param[in]  NewState: New state of the left and right channel data sequence.
+ *   This parameter can be: ENABLE or DISABLE.
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void i2s_demo(void)
+ * {
+ *     I2S_SwapLRChDataForRead(I2S0, ENABLE);
+ * }
+ * \endcode
+ */
+__STATIC_INLINE void I2S_SwapLRChDataForRead(I2S_TypeDef *I2Sx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_I2S_ALL_PERIPH(I2Sx));
+
+    if (NewState == ENABLE)
+    {
+        I2Sx->CTRL1 |= I2S_RX_SNK_LR_SWAP_MSK;
+    }
+    else
+    {
+        I2Sx->CTRL1 &= I2S_RX_SNK_LR_SWAP_CLR;
+    }
+}
+
+/**
+ * \brief MCLK output selection, only I2S0 can be selected.
+ * \param[in]  I2Sx: To select I2Sx peripheral, only I2S0 can be selected.
+ * \param[in]  NewState: New state of MCLK output.
+ *   This parameter can be: ENABLE or DISABLE.
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void i2s_demo(void)
+ * {
+ *     I2S_MCLKOutputSelectCmd(I2S0);
+ * }
+ * \endcode
+ */
+__STATIC_INLINE void I2S_MCLKOutputSelectCmd(I2S_TypeDef *I2Sx)
+{
+    /* Check the parameters */
+    assert_param(IS_I2S_ALL_PERIPH(I2Sx));
+
+    if (I2Sx == I2S0)
+    {
+        *((volatile uint32_t *)PERIPH_AUDIO_CLK_228) |= I2S_MCLK_OUTPUT_MSK;
+    }
+//    else
+//    {
+//        if (I2Sx == I2S1)
+//        {
+//            *((volatile uint32_t *)PERIPH_AUDIO_CLK_228) &= I2S_MCLK_OUTPUT_CLR;
+//        }
+//    }
+}
+
+/**
+ * \brief I2S0 communication selection which can be from internal codec or external codec.
+ * \param[in]  NewState: New state of I2S0 communication selection.
+ *   This parameter can be: ENABLE or DISABLE.
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void i2s_demo(void)
+ * {
+ *     I2S0_WithExtCodecCmd(ENABLE);
+ * }
+ * \endcode
+ */
+__STATIC_INLINE void I2S0_WithExtCodecCmd(FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (NewState == ENABLE)
+    {
+        *((volatile uint32_t *) PERIPH_AUDIO_CLK_224) |= I2S0_EXT_CODEC_MSK;
+    }
+    else
+    {
+        *((volatile uint32_t *) PERIPH_AUDIO_CLK_224) &= I2S0_EXT_CODEC_CLR;
+    }
+}
+
+/**
+ * \brief Update BClk clock parameter.
+ * \param[in]  I2Sx: To select I2Sx peripheral, where x can be: 0 or 1.
+ * \param[in]  I2S_BClockMi: Mi parameter.
+ * \param[in]  I2S_BClockNi: Ni parameter.
+ * \return  Execution status: SET: success, RESET: failure.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void i2s_demo(void)
+ * {
+ *     uint16_t I2S_BClockMi = 0x271;
+ *     uint16_t I2S_BClockNi = 0x10;
+ *     I2S_UpdateBClk(I2S0, I2S_BClockMi, I2S_BClockNi);
+ * }
+ * \endcode
+ */
+__STATIC_INLINE FlagStatus I2S_UpdateBClk(I2S_TypeDef *I2Sx, uint16_t I2S_BClockMi,
+                                          uint16_t I2S_BClockNi)
+{
+    /* Check the parameters */
+    assert_param(IS_I2S_ALL_PERIPH(I2Sx));
+
+    if (!(I2Sx->BCLK_DIV & I2S_MI_NI_UPDATE_MSK))
+    {
+        I2Sx->BCLK_DIV = I2S_BClockMi | (I2S_BCLK_NI_MSK & (I2S_BClockNi << I2S_BCLK_NI_POS)) |
+                         I2S_MI_NI_UPDATE_MSK;
+        return SET;
+    }
+
+    return RESET;
+}
+
+/**
+ * \brief Get BClk clock status.
+ * \param[in]  I2Sx: To select I2Sx peripheral, where x can be: 0 or 1.
+ * \return Execution status: SET: BLCK is updating, RESET: BLCK update is done.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void i2s_demo(void)
+ * {
+ *     FlagStatus status = I2S_GetBClkStatus(I2S0);
+ * }
+ * \endcode
+ */
+__STATIC_INLINE FlagStatus I2S_GetBClkStatus(I2S_TypeDef *I2Sx)
+{
+    /* Check the parameters */
+    assert_param(IS_I2S_ALL_PERIPH(I2Sx));
+
+    if (I2Sx->BCLK_DIV & I2S_MI_NI_UPDATE_MSK)
+    {
+        return SET;
+    }
+
+    return RESET;
+}
+
+/**
+ * \brief Configure Channel parameter.
+ * \param[in]  I2Sx: To select I2Sx peripheral, where x can be: 0 or 1.
+ * \param[in]  I2S_ChannelType: The channel type used for the I2S communication.
+ *      This parameter can be one of the following values, which refers to \ref I2S_Channel_Type.
+ *      \arg I2S_Channel_Mono: Mono channel.
+ *      \arg I2S_Channel_stereo: Stereo channel.
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void i2s_demo(void)
+ * {
+ *     I2S_ConfigChannelType(I2S0, I2S_Channel_stereo);
+ * }
+ * \endcode
+ */
+__STATIC_INLINE void I2S_ConfigChannelType(I2S_TypeDef *I2Sx, uint32_t I2S_ChannelType)
+{
+    I2Sx->CTRL0 &= I2S_CHANNEL_TYPE_CLR;
+    I2Sx->CTRL0 |= I2S_ChannelType;
+}
+
+/** End of I2S_Exported_Functions
+  * \}
+  */
+
+/** End of I2S
+  * \}
+  */
+
+typedef struct
+{
+    uint32_t i2s_reg[4];
+} I2SStoreReg_TypeDef;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTL876x_I2S_H */
+
+
+
diff --git a/bee/drivers/i2s/src/device/rtl87x2g/rtl_i2s.c b/bee/drivers/i2s/src/device/rtl87x2g/rtl_i2s.c
new file mode 100644
index 00000000..fc432b28
--- /dev/null
+++ b/bee/drivers/i2s/src/device/rtl87x2g/rtl_i2s.c
@@ -0,0 +1,678 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *                        Header Files
+ *============================================================================*/
+#include "rtl_i2s.h"
+#include "rtl_rcc.h"
+/*============================================================================*
+ *                           Public Functions
+ *============================================================================*/
+/**
+  * \brief Initializes the I2S peripheral according to the specified
+  *   parameters in the I2S_InitStruct
+  * \param  I2S: selected I2S peripheral.
+  * \param  I2S_InitStruct: pointer to a I2S_InitTypeDef structure that
+  *   contains the configuration information for the specified I2S peripheral
+  * \return None
+  */
+void I2S_Init(I2S_TypeDef *I2Sx, I2S_InitTypeDef *I2S_InitStruct)
+{
+    /* Check the parameters */
+    assert_param(IS_I2S_ALL_PERIPH(I2Sx));
+    assert_param(IS_I2S_DEVICE_MODE(I2S_InitStruct->I2S_DeviceMode));
+    assert_param(IS_I2S_CHANNEL_TYPE(I2S_InitStruct->I2S_ChannelType));
+    assert_param(IS_I2S_DATA_FORMAT(I2S_InitStruct->I2S_DataFormat));
+    assert_param(IS_I2S_DATA_WIDTH(I2S_InitStruct->I2S_DataWidth));
+    assert_param(IS_I2S_MCLK_OUTPUT_TYPE(I2S_InitStruct->I2S_MCLKOutput));
+    assert_param(IS_I2S_DMA_CMD(I2S_InitStruct->I2S_DMACmd));
+
+    /* set clk to 40M  echo todo*/
+    if (I2Sx == I2S0)
+    {
+        if (I2S_InitStruct->I2S_ClockSource == I2S_CLK_40M)
+        {
+            /*
+               SYSBLKCTRL->u_220.BITS_220.r_PON_FEN_SPORT0 = is_enable;
+               SYSBLKCTRL->u_220.BITS_220.r_CLK_EN_SPORT0 = is_enable;
+               SYSBLKCTRL->u_220.BITS_220.r_CLK_EN_SPORT_40M = 1;
+               SYSBLKCTRL->u_224.BITS_224.r_SPORT0_PLL_CLK_SEL = 4;
+            */
+            PERIBLKCTRL_AUDIO->u_700.BITS_700.r_CLK_EN_SPORT_40M = 0x1;
+            PERIBLKCTRL_AUDIO->u_700.BITS_700.sp0_dsp_clk_sel = 0x4;
+            PERIBLKCTRL_AUDIO->u_700.BITS_700.r_sport_pll2_ck_en = 0x0;
+        }
+        else
+        {
+            PERIBLKCTRL_AUDIO->u_700.BITS_700.r_CLK_EN_SPORT_40M = 0x0;
+            PERIBLKCTRL_AUDIO->u_700.BITS_700.sp0_dsp_clk_sel = 0x0;
+            PERIBLKCTRL_AUDIO->u_700.BITS_700.r_sport_pll2_ck_en = 0x1;
+        }
+
+    }
+
+    else if (I2Sx == I2S1)
+    {
+        if (I2S_InitStruct->I2S_ClockSource == I2S_CLK_40M)
+        {
+            /*
+               SYSBLKCTRL->u_220.BITS_220.r_PON_FEN_SPORT0 = is_enable;
+               SYSBLKCTRL->u_220.BITS_220.r_CLK_EN_SPORT0 = is_enable;
+               SYSBLKCTRL->u_220.BITS_220.r_CLK_EN_SPORT_40M = 1;
+               SYSBLKCTRL->u_224.BITS_224.r_SPORT0_PLL_CLK_SEL = 4;
+            */
+            PERIBLKCTRL_AUDIO->u_700.BITS_700.r_CLK_EN_SPORT_40M = 0x1;
+            PERIBLKCTRL_AUDIO->u_700.BITS_700.sp1_dsp_clk_sel = 0x4;
+            PERIBLKCTRL_AUDIO->u_700.BITS_700.r_sport_pll2_ck_en = 0x0;
+        }
+        else
+        {
+            PERIBLKCTRL_AUDIO->u_700.BITS_700.r_CLK_EN_SPORT_40M = 0x0;
+            PERIBLKCTRL_AUDIO->u_700.BITS_700.sp1_dsp_clk_sel = 0x0;
+            PERIBLKCTRL_AUDIO->u_700.BITS_700.r_sport_pll2_ck_en = 0x1;
+        }
+    }
+
+
+    I2S_CTRL_TypeDef i2s_reg_0x04 = {.d32 = I2Sx->I2S_CTRL};
+    I2S_FIFO_EN_CLK_CON_TypeDef i2s_reg_0x08 = {.d32 = I2Sx->I2S_FIFO_EN_CLK_CON};
+    I2S_TX_FRA_DIV_TypeDef i2s_reg_0x1c = {.d32 = I2Sx->I2S_TX_FRA_DIV};
+    I2S_LRCK_FIFO_TH_CON_TypeDef i2s_reg_0x20 = {.d32 = I2Sx->I2S_LRCK_FIFO_TH_CON};
+    I2S_FORM_CON_TypeDef i2s_reg_0x28 = {.d32 = I2Sx->I2S_FORM_CON};
+    I2S_RX_FRA_DIV_TypeDef i2s_reg_0x2c = {.d32 = I2Sx->I2S_RX_FRA_DIV};
+
+    /* Reset I2S module */
+    I2Sx->I2S_CTRL |= BIT0;
+    I2Sx->I2S_CTRL &= ~BIT0;
+
+
+    //trx_parameter_set
+    i2s_reg_0x28.b.trx_same_fs = ((I2S_InitStruct->I2S_TxBClockMi == I2S_InitStruct->I2S_RxBClockMi) &&
+                                  (I2S_InitStruct->I2S_TxBClockNi == I2S_InitStruct->I2S_RxBClockNi) &&
+                                  (I2S_InitStruct->I2S_TxBClockDiv == I2S_InitStruct->I2S_RxBClockDiv));
+
+    i2s_reg_0x28.b.trx_same_ch = I2S_InitStruct->I2S_TxChannelType == I2S_InitStruct->I2S_RxChannelType;
+    i2s_reg_0x28.b.trx_same_length = I2S_InitStruct->I2S_TxDataWidth == I2S_InitStruct->I2S_RxDataWidth;
+    i2s_reg_0x28.b.trx_same_ch_len = I2S_InitStruct->I2S_TxChannelWidth ==
+                                     I2S_InitStruct->I2S_RxChannelWidth;
+
+    /* I2S  Set data format*/
+    i2s_reg_0x28.b.sp_data_format_sel_rx =  I2S_InitStruct->I2S_RxDataFormat;
+    i2s_reg_0x04.b.sp_data_format_sel_tx =  I2S_InitStruct->I2S_TxDataFormat;
+
+    /* set rx config only if it's different from the corresponding tx setting */
+    i2s_reg_0x28.b.sp_en_i2s_mono_rx =  I2S_InitStruct->I2S_RxChannelType;
+    i2s_reg_0x04.b.sp_en_i2s_mono_tx =  I2S_InitStruct->I2S_TxChannelType;
+
+    i2s_reg_0x28.b.sp_data_len_sel_rx = I2S_InitStruct->I2S_RxDataWidth;
+    i2s_reg_0x04.b.sp_data_len_sel_tx = I2S_InitStruct->I2S_TxDataWidth;
+
+    i2s_reg_0x28.b.sp_ch_len_sel_tx = I2S_InitStruct->I2S_TxChannelWidth;
+    i2s_reg_0x28.b.sp_ch_len_sel_rx = I2S_InitStruct->I2S_RxChannelWidth;
+
+    /* Configure I2S initialization parameters */
+    i2s_reg_0x04.b.slave_data_sel = I2S_InitStruct->I2S_DeviceMode;
+    i2s_reg_0x04.b.sp_sel_i2s_rx_ch = I2S_InitStruct->I2S_RxChSequence;
+    i2s_reg_0x04.b.sp_sel_i2s_tx_ch = I2S_InitStruct->I2S_TxChSequence;
+    i2s_reg_0x04.b.rx_lsb_first = I2S_InitStruct->I2S_RxBitSequence;
+    i2s_reg_0x04.b.tx_lsb_first = I2S_InitStruct->I2S_TxBitSequence;
+
+    if (I2S_InitStruct->I2S_DeviceMode == I2S_DeviceMode_Slave)
+    {
+        i2s_reg_0x28.b.trx_same_lrc = 1;
+    }
+    /* Disable I2S tx rx */
+    i2s_reg_0x04.b.sp_tx_disable = 1;
+    i2s_reg_0x04.b.sp_rx_disable = 1;
+
+    /* Clear error counter */
+    I2Sx->I2S_FIFO_EN_CLK_CON |=  I2S_CLR_RX_ERR_CNT_MSK | I2S_CLR_TX_ERR_CNT_MSK ;
+    /* Clear error counter */
+    I2Sx->I2S_FIFO_EN_CLK_CON &= I2S_CLR_RX_ERR_CNT_CLR & I2S_CLR_TX_ERR_CNT_CLR;
+
+    /* Set fifo config */
+    i2s_reg_0x08.b.tx_fifo_0_reg_0_en = I2S_InitStruct->I2S_TxFifoUsed & I2S_FIFO_USE_0_REG_0;
+    i2s_reg_0x08.b.tx_fifo_0_reg_1_en = (I2S_InitStruct->I2S_TxFifoUsed & I2S_FIFO_USE_0_REG_1) >> 1;
+    i2s_reg_0x08.b.rx_fifo_0_reg_0_en = I2S_InitStruct->I2S_RxFifoUsed & I2S_FIFO_USE_0_REG_0;
+    i2s_reg_0x08.b.rx_fifo_0_reg_1_en = (I2S_InitStruct->I2S_RxFifoUsed & I2S_FIFO_USE_0_REG_1) >> 1;
+    /* Configure GDMA burst size */
+    i2s_reg_0x20.b.rxdma_burstsize =  I2S_InitStruct->I2S_RxWaterlevel;
+    i2s_reg_0x20.b.txdma_burstsize =  I2S_InitStruct->I2S_TxWaterlevel;
+
+    /* Configure I2S LRCLK, LRCLK=BCLK/BCLK_DIV */
+    if (I2S_InitStruct->I2S_TxBClockDiv >= 255)
+    {
+        I2S_InitStruct->I2S_TxBClockDiv = 255;
+    }
+    if (I2S_InitStruct->I2S_RxBClockDiv >= 255)
+    {
+        I2S_InitStruct->I2S_RxBClockDiv = 255;
+    }
+    if (i2s_reg_0x28.b.trx_same_fs == ENABLE)
+    {
+        i2s_reg_0x28.b.fixed_bclk = 0;
+        i2s_reg_0x08.b.enable_mclk  = 0;
+    }
+    else
+    {
+        i2s_reg_0x28.b.fixed_bclk = 1;
+        i2s_reg_0x08.b.enable_mclk  = 1;
+    }
+
+    i2s_reg_0x20.b.tx_bclk_div_ratio = I2S_InitStruct->I2S_TxBClockDiv;
+    i2s_reg_0x20.b.rx_bclk_div_ratio = I2S_InitStruct->I2S_RxBClockDiv;
+    /* Configure I2S BCLK */
+    i2s_reg_0x1c.b.tx_mi =  I2S_InitStruct->I2S_TxBClockMi;
+    i2s_reg_0x1c.b.tx_ni =  I2S_InitStruct->I2S_TxBClockNi;
+    i2s_reg_0x1c.b.tx_mi_ni_update = 1;
+    i2s_reg_0x2c.b.rx_mi =  I2S_InitStruct->I2S_RxBClockMi;
+    i2s_reg_0x2c.b.rx_ni =  I2S_InitStruct->I2S_RxBClockNi;
+    i2s_reg_0x2c.b.rx_mi_ni_update = 1;
+
+
+    I2Sx->I2S_CTRL =  i2s_reg_0x04.d32;
+    I2Sx->I2S_FIFO_EN_CLK_CON = i2s_reg_0x08.d32;
+    I2Sx->I2S_TX_FRA_DIV = i2s_reg_0x1c.d32 ;
+    I2Sx->I2S_LRCK_FIFO_TH_CON = i2s_reg_0x20.d32;
+    I2Sx->I2S_FORM_CON = i2s_reg_0x28.d32;
+    I2Sx->I2S_RX_FRA_DIV = i2s_reg_0x2c.d32;
+
+}
+
+/**
+  * \brief  Deinitializes the I2S peripheral registers to their default values.
+  * \param  I2S: selected I2S peripheral.
+  * \return None
+  */
+void I2S_DeInit(I2S_TypeDef *I2Sx)
+{
+    I2S_CTRL_TypeDef i2s_reg_0x04 = {.d32 = I2Sx->I2S_CTRL};
+    i2s_reg_0x04.b.sp_reset = 1;
+    I2Sx->I2S_CTRL =    i2s_reg_0x04.d32;
+
+    if (I2Sx == I2S0)
+    {
+        RCC_PeriphClockCmd(APBPeriph_I2S0, APBPeriph_I2S0_CLOCK, DISABLE);
+    }
+    else  if (I2Sx == I2S1)
+    {
+        RCC_PeriphClockCmd(APBPeriph_I2S1, APBPeriph_I2S1_CLOCK, DISABLE);
+    }
+
+}
+
+/**
+  * \brief  Fills each I2S_InitStruct member with its default value.
+  * \param  I2S_InitStruct: pointer to an I2S_InitTypeDef structure which will be initialized.
+  * \return None
+  */
+void I2S_StructInit(I2S_InitTypeDef *I2S_InitStruct)
+{
+    I2S_InitStruct->I2S_ClockSource      = I2S_CLK_40M;
+    I2S_InitStruct->I2S_TxBClockMi       = 0x271;/* <!BCLK = 16K */
+    I2S_InitStruct->I2S_TxBClockNi       = 0x10;
+    I2S_InitStruct->I2S_TxBClockDiv      = 0x3F;
+    I2S_InitStruct->I2S_RxBClockMi       = 0x271;/* <!BCLK = 16K */
+    I2S_InitStruct->I2S_RxBClockNi       = 0x10;
+    I2S_InitStruct->I2S_RxBClockDiv      = 0x3F;
+    I2S_InitStruct->I2S_DeviceMode       = I2S_DeviceMode_Master;
+    I2S_InitStruct->I2S_TxChannelType    = I2S_Channel_Mono;
+    I2S_InitStruct->I2S_RxChannelType    = I2S_Channel_Mono;
+    I2S_InitStruct->I2S_TxChSequence     = I2S_CH_L_R;
+    I2S_InitStruct->I2S_RxChSequence     = I2S_CH_L_R;
+    I2S_InitStruct->I2S_TxDataFormat     = I2S_Mode;
+    I2S_InitStruct->I2S_RxDataFormat     = I2S_Mode;
+    I2S_InitStruct->I2S_TxBitSequence    = I2S_MSB_First;
+    I2S_InitStruct->I2S_RxBitSequence    = I2S_MSB_First;
+    I2S_InitStruct->I2S_TxDataWidth      = I2S_Width_16Bits;
+    I2S_InitStruct->I2S_RxDataWidth      = I2S_Width_16Bits;
+    I2S_InitStruct->I2S_TxChannelWidth   = I2S_Width_32Bits;
+    I2S_InitStruct->I2S_RxChannelWidth   = I2S_Width_32Bits;
+    I2S_InitStruct->I2S_TxFifoUsed       = I2S_FIFO_USE_0_REG_0;
+    I2S_InitStruct->I2S_RxFifoUsed       = I2S_FIFO_USE_0_REG_0;
+    I2S_InitStruct->I2S_TxWaterlevel     = 16;
+    I2S_InitStruct->I2S_RxWaterlevel     = 16;
+}
+
+/**
+  * \brief  Fills each I2S_DataSelect member with its default value.
+  * \param  I2S_DataSelect: pointer to an I2S_DataSelTypeDef structure which will be initialized.
+  * \return None
+  */
+void I2S_DataSelStructInit(I2S_DataSelTypeDef *I2S_DataSelect)
+{
+
+    I2S_DataSelect->tx_channel_map[0] = I2S_TX_FIFO_0_REG_0_L;
+    I2S_DataSelect->tx_channel_map[1] = I2S_TX_FIFO_0_REG_0_R;
+    I2S_DataSelect->tx_channel_map[2] = I2S_TX_FIFO_0_REG_1_L;
+    I2S_DataSelect->tx_channel_map[3] = I2S_TX_FIFO_0_REG_1_R;
+
+    I2S_DataSelect->rx_fifo_map[0] = I2S_RX_CHANNEL_0;
+    I2S_DataSelect->rx_fifo_map[1] = I2S_RX_CHANNEL_1;
+    I2S_DataSelect->rx_fifo_map[2] = I2S_RX_CHANNEL_2;
+    I2S_DataSelect->rx_fifo_map[3] = I2S_RX_CHANNEL_3;
+}
+/**
+  * \brief  Enable or disable the selected I2S mode.
+  * \param  I2S: selected I2S peripheral.
+  * \param  mode: selected I2S operation mode.
+  *         This parameter can be the following values:
+  *         \arg I2S_MODE_TX: transmission mode.
+  *         \arg I2S_MODE_RX: receiving mode.
+  * \param  NewState: new state of the operation mode.
+  *   This parameter can be: ENABLE or DISABLE.
+  * \return None
+  */
+void I2S_Cmd(I2S_TypeDef *I2Sx, uint32_t mode, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_I2S_ALL_PERIPH(I2Sx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    I2S_CTRL_TypeDef i2s_reg_0x04 = {.d32 = I2Sx->I2S_CTRL};
+
+    if (mode == I2S_MODE_TX)
+    {
+        i2s_reg_0x04.b.sp_start_tx = NewState;
+        i2s_reg_0x04.b.sp_tx_disable = !NewState;
+    }
+
+    if (mode == I2S_MODE_RX)
+    {
+        i2s_reg_0x04.b.sp_start_rx = NewState;
+        i2s_reg_0x04.b.sp_rx_disable = !NewState;
+    }
+
+    I2Sx->I2S_CTRL = i2s_reg_0x04.d32;
+}
+
+
+/**
+  * \brief  Enable or disable the specified I2S interrupts.
+  * \param  I2S: selected I2S peripheral.
+  * \param  I2S_INT: specifies the I2S interrupts sources to be enable or disable.
+  *         This parameter can be the following values:
+  *         \arg I2S_INT_TX_IDLE: Transmit idle interrupt.
+  *         \arg I2S_INT_RF_EMPTY: Receive FIFO empty interrupt.
+  *         \arg I2S_NT_TF_EMPTY: Transmit FIFO empty interrupt.
+  *         \arg I2S_INT_RF_FULL: Receive FIFO full interrupt.
+  *         \arg I2S_INT_TF_FULL: Transmit FIFO full interrupt.
+  *         \arg I2S_INT_RX_READY: Ready to receive interrupt.
+  *         \arg I2S_INT_TX_READY: Ready to transmit interrupt.
+  *         \arg I2S_INT_TX_VALID: Tx_fifo_data_valid_interrupt.
+  * \param  NewState: new state of the specified I2S interrupts.
+  *   This parameter can be: ENABLE or DISABLE.
+  * \return None
+  */
+void I2S_INTConfig(I2S_TypeDef *I2Sx, uint32_t I2S_INT, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_I2S_MCU_INT_CONFIG(I2S_MCU_INT));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    /* Enable Interrupt */
+    I2S_CTRL_TypeDef i2s_reg_0x04 = {.d32 = I2Sx->I2S_CTRL};
+    i2s_reg_0x04.b.dsp_ctl_mode = 1;
+    I2Sx->I2S_CTRL = i2s_reg_0x04.d32;
+
+    if (NewState == ENABLE)
+    {
+
+        I2Sx->I2S_INTR_CON |= I2S_INT << 16;
+    }
+    else
+    {
+        I2Sx->I2S_INTR_CON &= ~(I2S_INT << 16);
+    }
+}
+
+
+/**
+  * \brief  Get the specified I2S flag status.
+  * \param  I2S: selected I2S peripheral.
+  * \param  I2S_INT: the specified I2S interrupt.
+  *         This parameter can be one of the following values:
+  *         \arg I2S_INT_TX_IDLE: Transmit idle interrupt.
+  *         \arg I2S_INT_RF_EMPTY: Receive FIFO empty interrupt.
+  *         \arg I2S_INT_TF_EMPTY: Transmit FIFO empty interrupt.
+  *         \arg I2S_INT_RF_FULL: Receive FIFO full interrupt.
+  *         \arg I2S_INT_TF_FULL: Transmit FIFO full interrupt.
+  *         \arg I2S_INT_RX_READY: Ready to receive interrupt.
+  *         \arg I2S_INT_TX_READY: Ready to transmit interrupt.
+  *         \arg I2S_INT_TX_VALID: Tx_fifo_data_valid_interrupt.
+  * \return The new state of LCD_FLAG (SET or RESET).
+  */
+ITStatus I2S_GetINTStatus(I2S_TypeDef *I2Sx, uint32_t I2S_INT)
+{
+    ITStatus bit_status = RESET;
+
+    /* Check the parameters */
+    assert_param(IS_I2S_INT_CONFIG(I2S_INT));
+
+    if ((I2Sx->I2S_FIFO_STA & BIT16) || (I2Sx->I2S_FIFO_STA & (I2S_INT & 0x3F)))
+    {
+        bit_status = SET;
+    }
+
+    /* Return the I2S_INT status */
+    return  bit_status;
+}
+
+
+/**
+  * \brief  Clears the I2S interrupt pending bits.
+  * \param  I2S: selected I2S peripheral.
+  * \param  I2S_CLEAR_INT: specifies the interrupt pending bit to clear.
+  *         This parameter can be any combination of the following values:
+  *         \arg I2S_CLEAR_INT_RX_READY: Clear ready to receive interrupt.
+  *         \arg I2S_CLEAR_INT_TX_READY: Clear ready to transmit interrupt.
+  * \return None
+  */
+void I2S_ClearINTPendingBit(I2S_TypeDef *I2Sx, uint32_t I2S_CLEAR_INT)
+{
+    /* Check the parameters */
+    assert_param(IS_I2S_INT_CONFIG(I2S_CLEAR_INT));
+    I2Sx->I2S_INTR_CON |= I2S_CLEAR_INT;
+    I2Sx->I2S_INTR_CON &= I2S_CLEAR_INT;
+}
+
+/**
+ * \brief   I2S communication selection which can be from intrnal codec or external codec.
+ * \param   NewState: new state of I2S0 communication selection.
+ *          This parameter can be: ENABLE or DISABLE.
+ * \return  None.
+ */
+void I2S_WithExtCodecCmd(I2S_TypeDef *I2Sx, FunctionalState NewState)
+{
+
+    if (I2Sx == I2S0)
+    {
+        PERIBLKCTRL_AUDIO->u_708.BITS_708.r_SPORT0_EXT_CODEC = NewState;
+
+    }
+    if (I2Sx == I2S1)
+    {
+        PERIBLKCTRL_AUDIO->u_708.BITS_708.r_SPORT1_EXT_CODEC = NewState;
+    }
+}
+
+/**
+ * \brief   Transmits a data through the SPIx/I2Sx peripheral.
+ * \param[in] I2Sx: To select the I2Sx peripheral, x can be 0 or 1.
+ * \param[in] Data: Data to be transmitted.
+ * \return None.
+ */
+void I2S_SendData(I2S_TypeDef *I2Sx, uint32_t Data)
+{
+    /* Check the parameters */
+    assert_param(IS_I2S_ALL_PERIPH(I2Sx));
+    I2Sx->I2S_TX_FIFO_WR_ADDR = Data;
+}
+
+
+/**
+ * \brief  Received data by the I2Sx peripheral.
+ * \param[in] I2Sx: To select I2Sx peripheral, where x can be: 0 or 1.
+ * \return Return the most recent received data.
+ */
+uint32_t I2S_ReceiveFIFOData(I2S_TypeDef *I2Sx)
+{
+    /* Check the parameters */
+    assert_param(IS_I2S_ALL_PERIPH(I2Sx));
+
+    return  I2Sx->I2S_RX_FIFO_RD_ADDR;
+
+}
+
+/**
+ * \brief   Get transmit FIFO free length by the I2Sx peripheral.
+ * \param[in] I2Sx: To select I2Sx peripheral, where x can be: 0 or 1.
+ * \retval  Return the transmit FIFO free length.
+ */
+uint8_t I2S_GetTxFIFOFreeLen(I2S_TypeDef *I2Sx)
+{
+    /* Check the parameters */
+    assert_param(IS_I2S_ALL_PERIPH(I2Sx));
+
+    return I2Sx->I2S_FIFO_CNT_STA & 0x3F ;
+}
+
+/**
+ * \brief   Get receive FIFO data length by the I2Sx peripheral.
+ * \param[in] I2Sx: To select I2Sx peripheral, where x can be: 0 or 1.
+ * \return  The data length of the receive FIFO.
+ */
+uint8_t I2S_GetRxFIFOLen(I2S_TypeDef *I2Sx)
+{
+    /* Check the parameters */
+    assert_param(IS_I2S_ALL_PERIPH(I2Sx));
+
+    return ((I2Sx->I2S_FIFO_CNT_STA & 0x3F00) >> I2S_RX_FIFO_DEPTH_CNT_0_POS);
+}
+
+/**
+ * \brief   Get the send error counter value by the I2Sx peripheral.
+ * \param[in]  I2Sx: To select I2Sx peripheral, where x can be: 0 or 1.
+ * \return  The send error counter value .
+ */
+uint8_t I2S_GetTxErrCnt(I2S_TypeDef *I2Sx)
+{
+    /* Check the parameters */
+    assert_param(IS_I2S_ALL_PERIPH(I2Sx));
+
+    return I2Sx->I2S_TX_RX_ERR_STA & 0xFF;
+}
+
+/**
+ * \brief  Get the reception error counter value by the I2Sx peripheral.
+ * \param[in] I2Sx: To select I2Sx peripheral, where x can be: 0 or 1.
+ * \retval  The reception error counter value .
+ */
+uint8_t I2S_GetRxErrCnt(I2S_TypeDef *I2Sx)
+{
+    /* Check the parameters */
+    assert_param(IS_I2S_ALL_PERIPH(I2Sx));
+
+    return ((I2Sx->I2S_TX_RX_ERR_STA & 0xFFFF) >> I2S_RX_ERR_CNT_POS);
+}
+
+/**
+ * \brief   Swap audio data bytes sequence which sent by the I2Sx peripheral.
+ * \param[in] I2Sx: To select I2Sx peripheral, where x can be: 0 or 1.
+ * \param[in] NewState: New state of the bytes sequence.
+ *      This parameter can be: ENABLE or DISABLE.
+ * \return None.
+ */
+void I2S_SwapBytesForSend(I2S_TypeDef *I2Sx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_I2S_ALL_PERIPH(I2Sx));
+    I2S_FIFO_EN_CLK_CON_TypeDef i2s_reg_0x08 = {.d32 = I2Sx->I2S_FIFO_EN_CLK_CON};
+    i2s_reg_0x08.b.tx_src_byte_swap = NewState;
+    I2Sx->I2S_FIFO_EN_CLK_CON =  i2s_reg_0x08.d32;
+}
+
+/**
+ * \brief   Swap audio data bytes sequence which read by the I2Sx peripheral.
+ * \param[in] I2Sx: To select I2Sx peripheral, where x can be: 0 or 1.
+ * \param[in] NewState: New state of the bytes sequence.
+ *      This parameter can be: ENABLE or DISABLE.
+ * \return  None.
+ */
+void I2S_SwapBytesForRead(I2S_TypeDef *I2Sx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_I2S_ALL_PERIPH(I2Sx));
+
+    I2S_FIFO_EN_CLK_CON_TypeDef i2s_reg_0x08 = {.d32 = I2Sx->I2S_FIFO_EN_CLK_CON};
+    i2s_reg_0x08.b.rx_snk_byte_swap = NewState;
+    I2Sx->I2S_FIFO_EN_CLK_CON =  i2s_reg_0x08.d32;
+}
+
+/**
+ * \brief  Swap audio channel data which sent by the I2Sx peripheral..
+ * \param[in] I2Sx: To select I2Sx peripheral, where x can be: 0 or 1.
+ * \param[in] NewState: New state of the left and right channel data sequence.
+ *      This parameter can be: ENABLE or DISABLE.
+ * \return  None.
+ */
+void I2S_SwapLRChDataForSend(I2S_TypeDef *I2Sx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_I2S_ALL_PERIPH(I2Sx));
+
+    I2S_FIFO_EN_CLK_CON_TypeDef i2s_reg_0x08 = {.d32 = I2Sx->I2S_FIFO_EN_CLK_CON};
+    i2s_reg_0x08.b.tx_src_lr_swap = NewState;
+    I2Sx->I2S_FIFO_EN_CLK_CON =  i2s_reg_0x08.d32;
+}
+
+/**
+ * \brief   Swap audio channel data which read by the I2Sx peripheral.
+ * \param[in] I2Sx: To select I2Sx peripheral, where x can be: 0 or 1.
+ * \param[in] NewState: New state of the left and right channel data sequence.
+ *      This parameter can be: ENABLE or DISABLE.
+ * \return None.
+ */
+void I2S_SwapLRChDataForRead(I2S_TypeDef *I2Sx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_I2S_ALL_PERIPH(I2Sx));
+
+    I2S_FIFO_EN_CLK_CON_TypeDef i2s_reg_0x08 = {.d32 = I2Sx->I2S_FIFO_EN_CLK_CON};
+    i2s_reg_0x08.b.rx_snk_lr_swap = NewState;
+    I2Sx->I2S_FIFO_EN_CLK_CON =  i2s_reg_0x08.d32;
+}
+
+/**
+ * \brief   MCLK output selection which can be from I2S0 or I2S1.
+ * \param[in] I2Sx: To select I2Sx peripheral, where x can be: 0 or 1.
+ * \param[in] NewState: New state of MCLK output.
+ *      This parameter can be: ENABLE or DISABLE.
+ * \return  None.
+ */
+void I2S_MCLKOutputSelectCmd(I2S_TypeDef *I2Sx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_I2S_ALL_PERIPH(I2Sx));
+
+    if (I2Sx == I2S0)
+    {
+        if (NewState == ENABLE)
+        {
+            /*Enable mclk mux */
+            PERIBLKCTRL_AUDIO->u_708.BITS_708.r_SPORT0_MCLK_OUT = 0x1;
+            PERIBLKCTRL_AUDIO->u_70C.BITS_70C.mclk2_pmux_sel = 0x1;
+        }
+        else
+        {
+            PERIBLKCTRL_AUDIO->u_708.BITS_708.r_SPORT0_MCLK_OUT = 0x0;
+            PERIBLKCTRL_AUDIO->u_70C.BITS_70C.mclk2_pmux_sel = 0x0;
+        }
+    }
+    else
+    {
+        if (I2Sx == I2S1)
+        {
+            if (NewState == ENABLE)
+            {
+                /*Enable mclk mux */
+                PERIBLKCTRL_AUDIO->u_708.BITS_708.r_SPORT1_MCLK_OUT = 0x1;
+                PERIBLKCTRL_AUDIO->u_70C.BITS_70C.mclk2_pmux_sel = 0x1;
+            }
+            else
+            {
+                /*Enable mclk mux */
+                PERIBLKCTRL_AUDIO->u_708.BITS_708.r_SPORT1_MCLK_OUT = 0x0;
+                PERIBLKCTRL_AUDIO->u_70C.BITS_70C.mclk2_pmux_sel = 0x0;
+            }
+        }
+    }
+}
+
+/**
+ * \brief   I2S0 communication selection which can be from intrnal codec or external codec.
+ * \param[in] NewState: new state of I2S0 communication selection.
+ *      This parameter can be: ENABLE or DISABLE.
+ * \return  None.
+ */
+void I2S_WithExtCodecCmd(I2S_TypeDef *I2Sx, FunctionalState NewState);
+
+
+/**
+ * \brief   Config BClk clock.
+ * \param[in] I2Sx: To select I2Sx peripheral, where x can be: 0 or 1.
+ * \param[in] I2S_BClockMi: Mi parameter.
+ * \param[in] I2S_BClockNi: Ni parameter.
+ * \return  Execution status.
+ * \retval  SET: Success.
+ * \retval  RESET: Failure.
+ */
+void I2S_UpdateBClk(I2S_TypeDef *I2Sx, uint32_t dir, uint16_t I2S_BClockMi,
+                    uint16_t I2S_BClockNi)
+{
+    /* Check the parameters */
+    assert_param(IS_I2S_ALL_PERIPH(I2Sx));
+    I2S_TX_FRA_DIV_TypeDef i2s_reg_0x1c = {.d32 = I2Sx->I2S_TX_FRA_DIV};
+    I2S_RX_FRA_DIV_TypeDef i2s_reg_0x2c = {.d32 = I2Sx->I2S_RX_FRA_DIV};
+    if (dir == I2S_MODE_TX)
+    {
+        /* Configure I2S BCLK */
+        i2s_reg_0x1c.b.tx_mi =  I2S_BClockMi;
+        i2s_reg_0x1c.b.tx_ni =  I2S_BClockNi;
+        i2s_reg_0x1c.b.tx_mi_ni_update = 1;
+    }
+    else if (dir == I2S_MODE_RX)
+    {
+        i2s_reg_0x2c.b.rx_mi =  I2S_BClockMi;
+        i2s_reg_0x2c.b.rx_ni =  I2S_BClockNi;
+        i2s_reg_0x2c.b.rx_mi_ni_update = 1;
+    }
+    I2Sx->I2S_TX_FRA_DIV =  i2s_reg_0x1c.d32;
+    I2Sx->I2S_RX_FRA_DIV =  i2s_reg_0x2c.d32;
+    return;
+}
+
+/**
+ * \brief   Get BClk clock status.
+ * \param[in] I2Sx: To select I2Sx peripheral, where x can be: 0 or 1.
+ * \return  Execution status.
+ * \retval  SET: BLCK is updating.
+ * \retval  RESET: BLCK update is done.
+ */
+FlagStatus I2S_GetTxBClkStatus(I2S_TypeDef *I2Sx)
+{
+    /* Check the parameters */
+    assert_param(IS_I2S_ALL_PERIPH(I2Sx));
+
+    if (I2Sx->I2S_TX_FRA_DIV & I2S_MI_NI_UPDATE_MSK)
+    {
+        return SET;
+    }
+
+    return RESET;
+}
+
+/**
+ * \brief   Get BClk clock status.
+ * \param[in] I2Sx: To select I2Sx peripheral, where x can be: 0 or 1.
+ * \return  Execution status.
+ * \retval  SET: BLCK is updating.
+ * \retval  RESET: BLCK update is done.
+ */
+FlagStatus I2S_GetRxBClkStatus(I2S_TypeDef *I2Sx)
+{
+    /* Check the parameters */
+    assert_param(IS_I2S_ALL_PERIPH(I2Sx));
+
+    if (I2Sx->I2S_RX_FRA_DIV & I2S_MI_NI_UPDATE_MSK)
+    {
+        return SET;
+    }
+
+    return RESET;
+}
+
diff --git a/bee/drivers/i2s/src/device/rtl87x2g/rtl_i2s.h b/bee/drivers/i2s/src/device/rtl87x2g/rtl_i2s.h
new file mode 100644
index 00000000..e14874e9
--- /dev/null
+++ b/bee/drivers/i2s/src/device/rtl87x2g/rtl_i2s.h
@@ -0,0 +1,1029 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *               Define to prevent recursive inclusion
+ *============================================================================*/
+#ifndef RTL_I2S_H
+#define RTL_I2S_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*============================================================================*
+ *                        Header Files
+ *============================================================================*/
+#include "utils/rtl_utils.h"
+#include "rtl_i2s_def.h"
+
+/** \defgroup I2S         I2S
+  * \brief
+  * \{
+  */
+
+/*============================================================================*
+ *                         Constants
+ *============================================================================*/
+/** \defgroup I2S_Exported_Constants I2S Exported Constants
+  * \brief
+  * \{
+  */
+
+/**
+ * \defgroup    I2S_Clock_Source I2S Clock Source
+ * \{
+ * \ingroup     I2S_Exported_Constants
+ */
+typedef enum
+{
+    I2S_CLK_40M,      //!< I2S Clock Source is 40MHz.
+#if I2S_SUPPORT_PLL_CLK
+    I2S_CLK_PLL2,     //!< I2S Clock Source is PLL2.
+#else
+    I2S_CLK_128fs,    //!< I2S Clock Source is 128fs.
+    I2S_CLK_256fs,    //!< I2S Clock Source is 256fs.
+#endif
+} I2SSrcClk_TypeDef;
+
+#if I2S_SUPPORT_PLL_CLK
+#define IS_I2S_CLK_SOURCE(CLK) (((CLK) == I2S_CLK_40M) || \
+                                ((CLK) == I2S_CLK_PLL2))) //!< Check if the input parameter is valid.
+#else
+#define IS_I2S_CLK_SOURCE(CLK) (((CLK) == I2S_CLK_40M) || \
+                                ((CLK) == I2S_CLK_128fs) || \
+                                ((CLK) == I2S_CLK_256fs)) //!< Check if the input parameter is valid.
+#endif
+/** End of I2S_Clock_Source
+  * \}
+  */
+
+/**
+ * \defgroup    I2S_Format_Mode I2S Format Mode
+ * \{
+ * \ingroup     I2S_Exported_Constants
+ */
+typedef enum
+{
+    I2S_Mode,                   //!< I2S mode.
+    Left_Justified_Mode,        //!< Left justified mode.
+    PCM_Mode_A,                 //!< PCM mode A.
+    PCM_Mode_B,                 //!< PCM mode B.
+} I2SDataFormat_TypeDef;
+
+#define IS_I2S_DATA_FORMAT(FORMAT)      (((FORMAT) == I2S_Mode) || ((FORMAT) == Left_Justified_Mode) || \
+                                         ((FORMAT) == PCM_Mode_A) || ((FORMAT) == PCM_Mode_B)) //!< Check if the input parameter is valid.
+
+/** End of I2S_Format_Mode
+  * \}
+  */
+
+/**
+ * \defgroup    I2S_Channel_Type I2S Channel Type
+ * \{
+ * \ingroup     I2S_Exported_Constants
+ */
+typedef enum
+{
+    I2S_Channel_stereo,      //!< The channel format of the I2S is stereo.
+    I2S_Channel_Mono,        //!< The channel format of the I2S is mono.
+} I2SChannelType_TypeDef;
+
+#define IS_I2S_CHANNEL_TYPE(TYPE)       (((TYPE) == I2S_Channel_Mono) || ((TYPE) == I2S_Channel_stereo)) //!< Check if the input parameter is valid.
+
+/** End of I2S_Channel_Type
+  * \}
+  */
+
+/**
+ * \defgroup    I2S_Data_Width I2S Data Width
+ * \{
+ * \ingroup     I2S_Exported_Constants
+ */
+typedef enum
+{
+    I2S_Width_16Bits = 0x00,      //!< The I2S data width is 16 bits.
+    I2S_Width_24Bits = 0x02,      //!< The I2S data width is 24 bits.
+    I2S_Width_8Bits = 0x03,       //!< The I2S data width is 8 bits.
+#if I2S_SUPPORT_DATE_WIDTH_32BIT
+    I2S_Width_20Bits = 0x01,      //!< The I2S data width is 20 bits.
+    I2S_Width_32Bits = 0x04,      //!< The I2S data width is 32 bits.
+#endif
+} I2SDataWidth_TypeDef;
+
+#define IS_I2S_DATA_WIDTH(WIDTH)        (((WIDTH) == I2S_Width_16Bits) || \
+                                         ((WIDTH) == I2S_Width_8Bits)) || \
+((WIDTH) == I2S_Width_24Bits) || \
+((WIDTH) == I2S_Width_20Bits) || \
+((WIDTH) == I2S_Width_32Bits)) //!< Check if the input parameter is valid.
+
+
+/** End of I2S_Data_Width
+  * \}
+  */
+
+/**
+ * \defgroup    I2S_Device_Mode I2S Device Mode
+ * \{
+ * \ingroup     I2S_Exported_Constants
+ */
+typedef enum
+{
+    I2S_DeviceMode_Master,      //!< I2S master mode.
+    I2S_DeviceMode_Slave,       //!< I2S slave mode.
+} I2SDeviceMode_TypeDef;
+
+#define IS_I2S_DEVICE_MODE(DEVICE)      (((DEVICE) == I2S_DeviceMode_Master) || ((DEVICE) == I2S_DeviceMode_Slave)) //!< Check if the input parameter is valid.
+
+/** End of I2S_Device_Mode
+  * \}
+  */
+
+/**
+ * \defgroup    I2S_Channel_Sequence I2S Channel Sequence
+ * \{
+ * \ingroup     I2S_Exported_Constants
+ */
+typedef enum
+{
+    I2S_CH_L_R,      //!< I2S channel sequence from left to right.
+    I2S_CH_R_L,      //!< I2S channel sequence from right to left.
+    I2S_CH_L_L,      //!< I2S channel sequence from left to left.
+    I2S_CH_R_R,      //!< I2S channel sequence from right to right.
+} I2SCHSeq_TypeDef;
+
+#define IS_I2S_CH_SEQ(SEQ)       (((SEQ) == I2S_CH_L_R) || ((SEQ) == I2S_CH_R_L) || \
+                                  ((SEQ) == I2S_CH_L_L) || ((SEQ) == I2S_CH_R_R)) //!< Check if the input parameter is valid.
+
+/** End of I2S_Transmission_Channel_Sequence
+  * \}
+  */
+
+/**
+ * \defgroup    I2S_Bit_Sequence I2S Bit Sequence
+ * \{
+ * \ingroup     I2S_Exported_Constants
+ */
+typedef enum
+{
+    I2S_MSB_First,      //!< I2S Bit_Sequence MSB first.
+    I2S_LSB_First,      //!< I2S Bit_Sequence LSB first.
+} I2SBitSeq_TypeDef;
+
+#define IS_I2S_BIT_SEQ(SEQ)      (((SEQ) == I2S_MSB_First) || ((SEQ) == I2S_LSB_First)) //!< Check if the input parameter is valid.
+
+/** End of I2S_Bit_Sequence
+  * \}
+  */
+#if I2S_SUPPORT_TRX_FIFO
+/**
+ * \defgroup    I2S_FIFO_USE I2S FIFO USE
+ * \{
+ * \ingroup     I2S_Exported_Constants
+ */
+typedef enum t_sport_fifo_use
+{
+    I2S_FIFO_USE_0_REG_0 = BIT0,      //!< Enable first two channel of I2S FIFO.
+    I2S_FIFO_USE_0_REG_1 = BIT1,      //!< Enable last two channel of I2S FIFO.
+} I2SFifoUse_TypeDef;
+
+/** End of I2S_FIFO_USE
+  * \}
+  */
+#endif
+
+#if I2S_SUPPORT_MCLK_OUTPUT_SEL
+/**
+ * \defgroup    I2S_MCLK_Output I2S MCLK Output
+ * \{
+ * \ingroup     I2S_Exported_Constants
+ */
+
+typedef enum
+{
+    I2S_MCLK_128fs,    //!< I2S MCLK output 128fs.
+    I2S_MCLK_256fs,    //!< I2S MCLK output 256fs.
+} I2SMClkSel;
+
+#define IS_I2S_MCLK_OUTPUT_TYPE(TYPE)       (((TYPE) == I2S_MCLK_128fs) || ((TYPE) == I2S_MCLK_256fs)) //!< Check if the input parameter is valid.
+
+/** End of I2S_MCLK_Output
+  * \}
+  */
+#endif
+
+/**
+ * \defgroup    I2S_Mode I2S Mode
+ * \{
+ * \ingroup     I2S_Exported_Constants
+ */
+#define I2S_MODE_TX                                 (0x0)     //!< I2S TX mode.
+#define I2S_MODE_RX                                 (0x1)     //!< I2S RX mode.
+
+#define IS_I2S_MODE(MODE)      (((MODE) == I2S_MODE_TX) || ((MODE) == I2S_MODE_RX)) //!< Check if the input parameter is valid.
+
+/** End of I2S_Mode
+  * \}
+  */
+
+/** End of I2S_Exported_Constants
+  * \}
+  */
+
+/*============================================================================*
+ *                         Types
+ *============================================================================*/
+/** \defgroup I2S_Exported_Types I2S Exported Types
+  * \brief
+  * \{
+  */
+
+/**
+ * \brief       I2S initialize parameters.
+ *
+ * \ingroup     I2S_Exported_Types
+ */
+typedef struct
+{
+    I2SSrcClk_TypeDef I2S_ClockSource;        /*!< Specify the I2S clock source.
+                                                   This parameter can be a value of \ref I2S_Clock_Source */
+#if I2S_SUPPORT_TRX_INDEPENDENT_CONTROL
+
+
+    uint32_t I2S_TxBClockMi;                  /*!< Specify the BLCK clock speed. BCLK = 40MHz*(I2S_BClockNi/I2S_BClockMi).
+                                                   This parameter must range from 1 to 0xffff. */
+
+    uint32_t I2S_TxBClockNi;                  /*!< Specify the BLCK clock speed.
+                                                   This parameter must range from 1 to 0x7FFF. */
+
+    uint32_t I2S_TxBClockDiv;                 /*!< Specify the BLCK clock divider. The actual BCLK clock divider = I2S_TxBClockDiv + 1.
+                                                   This parameter must range from 1 to 0xFF. */
+
+    uint32_t I2S_RxBClockMi;                  /*!< Specify the BLCK clock speed. BCLK = 40MHz*(I2S_BClockNi/I2S_BClockMi).
+                                                   This parameter must range from 1 to 0xffff. */
+
+    uint32_t I2S_RxBClockNi;                  /*!< Specify the BLCK clock speed.
+                                                   This parameter must range from 1 to 0x7FFF. */
+
+    uint32_t I2S_RxBClockDiv;                 /*!< Specify the BLCK clock divider. The actual BCLK clock divider = I2S_RxBClockDiv + 1.
+                                                   This parameter must range from 1 to 0xFF. */
+
+    I2SChannelType_TypeDef
+    I2S_TxChannelType;                        /*!< Specify the channel type used for the I2S communication.
+                                                   This parameter can be a value of \ref I2S_Channel_Type. */
+    I2SChannelType_TypeDef
+    I2S_RxChannelType;                        /*!< Specify the channel type used for the I2S communication.
+                                                   This parameter can be a value of \ref I2S_Channel_Type. */
+
+    I2SDataFormat_TypeDef I2S_TxDataFormat;   /*!< Specify the I2S Data format mode.
+                                                   This parameter can be a value of \ref I2S_Format_Mode. */
+
+    I2SDataFormat_TypeDef I2S_RxDataFormat;   /*!< Specify the I2S Data format mode.
+                                                   This parameter can be a value of \ref I2S_Format_Mode. */
+
+    I2SDataWidth_TypeDef I2S_TxDataWidth;     /*!< Specify the I2S Tx Data width.
+                                                   This parameter can be a value of \ref I2S_Data_Width. */
+
+    I2SDataWidth_TypeDef I2S_RxDataWidth;     /*!< Specify the I2S Rx Data width.
+                                                   This parameter can be a value of \ref I2S_Data_Width. */
+
+    I2SDataWidth_TypeDef I2S_TxChannelWidth;  /*!< Specify the I2S Tx channel width.
+                                                   This parameter can be a value of \ref I2S_Data_Width. */
+
+    I2SDataWidth_TypeDef I2S_RxChannelWidth;  /*!< Specify the I2S Rx channel width.
+                                                   This parameter can be a value of \ref I2S_Data_Width. */
+#else
+    uint32_t I2S_BClockMi;                    /*!< Specify the BLCK clock speed. BCLK = 40MHz*(I2S_BClockNi/I2S_BClockMi).
+                                                   This parameter must range from 1 to 0xffff. */
+
+    uint32_t I2S_BClockNi;                    /*!< Specify the BLCK clock speed.
+                                                   This parameter must range from 1 to 0x7FFF. */
+    I2SChannelType_TypeDef
+    I2S_ChannelType;                          /*!< Specify the channel type used for the I2S communication.
+                                                   This parameter can be a value of \ref I2S_Channel_Type. */
+
+    I2SDataFormat_TypeDef I2S_DataFormat;     /*!< Specify the I2S Data format mode.
+                                                   This parameter can be a value of \ref I2S_Format_Mode. */
+
+    I2SDataWidth_TypeDef I2S_DataWidth;       /*!< Specify the I2S Data width.
+                                                   This parameter can be a value of \ref I2S_Data_Width. */
+#endif
+
+#if I2S_SUPPORT_TRX_FIFO
+    I2SFifoUse_TypeDef I2S_TxFifoUsed;        /*!< Specify the I2S Tx FIFO.
+                                                   This parameter can be a value of \ref I2S_FIFO_USE. */
+
+    I2SFifoUse_TypeDef I2S_RxFifoUsed;        /*!< Specify the I2S Rx FIFO.
+                                                   This parameter can be a value of \ref I2S_FIFO_USE. */
+#endif
+    I2SDeviceMode_TypeDef I2S_DeviceMode;     /*!< Specify the I2S device mode.
+                                                   This parameter can be a value of \ref I2S_Device_Mode. */
+
+    I2SCHSeq_TypeDef
+    I2S_RxChSequence;        /*!< Specify the Rx channel seqence used for the I2S communication.
+                                  This parameter can be a value of \ref I2S_Channel_Sequence. */
+
+    I2SCHSeq_TypeDef
+    I2S_TxChSequence;        /*!< Specify the Tx channel seqence used for the I2S communication.
+                                  This parameter can be a value of \ref I2S_Channel_Sequence. */
+
+    I2SBitSeq_TypeDef I2S_TxBitSequence;      /*!< Specify the I2S Tx Data bits sequences.
+                                                   This parameter can be a value of \ref I2S_Bit_Sequence. */
+
+    I2SBitSeq_TypeDef I2S_RxBitSequence;      /*!< Specify the I2S Rx Data bits sequences.
+                                                   This parameter can be a value of \ref I2S_Bit_Sequence. */
+
+    uint32_t I2S_TxWaterlevel;                /*!< Specify the dma watermark level in Tx mode.
+                                                   This parameter must range from 1 to 63. */
+
+    uint32_t I2S_RxWaterlevel;                /*!< Specify the dma watermark level in Rx mode.
+                                                   This parameter must range from 1 to 63. */
+#if I2S_SUPPORT_MCLK_OUTPUT_SEL
+    uint32_t I2S_MCLKOutput;                  /*!< Specify the I2S MCLK output freqency.
+                                                   This parameter can be a value of \ref I2S_MCLK_Output. */
+#endif
+
+} I2S_InitTypeDef;
+
+#if I2S_SUPPORT_TRX_FIFO
+/**
+ * \brief       I2S Data Select
+ *
+ * \ingroup     I2S_Exported_Types
+ */
+typedef struct
+{
+    uint8_t tx_channel_map[4];     //!< I2S Tx channel map.
+    uint8_t rx_fifo_map[4];        //!< I2S Rx fifo map.
+} I2S_DataSelTypeDef;
+
+#endif
+
+/** End of I2S_Exported_Types
+  * \}
+  */
+
+/*============================================================================*
+ *                         Constants
+ *============================================================================*/
+/** \defgroup I2S_Exported_Constants I2S Exported Constants
+  * \brief
+  * \{
+  */
+
+/**
+ * \defgroup    I2S_All_Periph   I2S All Periph
+ * \{
+ * \ingroup     I2S_Exported_Constants
+ */
+#define IS_I2S_ALL_PERIPH(PERIPH) (((PERIPH) == I2S0) || \
+                                   ((PERIPH) == I2S1))     //!< I2S all peripheral.
+
+/** End of I2S_All_Periph
+  * \}
+  */
+
+/**
+ * \defgroup    I2S_Interrupt_Definition   I2S Interrupt Definition
+ * \{
+ * \ingroup     I2S_Exported_Constants
+ */
+#if I2S_SUPPORT_INT_TX_VALID
+#define I2S_INT_TX_VALID                           BIT7  //!< The I2S interrupt for TX valid.
+#endif
+#define I2S_INT_TX_IDLE                            BIT6  //!< The I2S interrupt for TX is working, but FIFO_0 is empty.
+#define I2S_INT_RF_EMPTY                           BIT5  //!< The I2S interrupt for RX FIFO_0 is empty (MIC path).
+#define I2S_INT_TF_EMPTY                           BIT4  //!< The I2S interrupt for TX FIFO_0 is empty (SPK path).
+#define I2S_INT_RF_FULL                            BIT3  //!< The I2S interrupt for RX FIFO_0 is full (MIC path).
+#define I2S_INT_TF_FULL                            BIT2  //!< The I2S interrupt for TX FIFO_0 is full (SPK path).
+#define I2S_INT_RX_READY                           BIT1  //!< The I2S interrupt is ready to receive data (MIC path).
+#define I2S_INT_TX_READY                           BIT0  //!< The I2S interrupt is ready to send data out (SPK path).
+
+#define IS_I2S_INT_CONFIG(INT)          (((INT) == I2S_INT_TX_IDLE) || ((INT) == I2S_INT_RF_EMPTY) || \
+                                         ((INT) == I2S_INT_TF_EMPTY) || ((INT) == I2S_INT_RF_FULL) || \
+                                         ((INT) == I2S_INT_TF_FULL) || ((INT) == I2S_INT_RX_READY) || \
+                                         ((INT) == I2S_INT_TX_READY) )
+
+/** End of I2S_Interrupt_Definition
+  * \}
+  */
+
+/**
+ * \defgroup    I2S_Clear_Interrupt_Definition     I2S Clear Interrupt Definition
+ * \{
+ * \ingroup     I2S_Exported_Constants
+ */
+#define I2S_CLEAR_INT_TX_VALID                      BIT14 //!< Clear the I2S interrupt for TX valid.
+#define I2S_CLEAR_INT_TX_IDLE                       BIT6  //!< Clear the I2S interrupt for TX is working, but FIFO_0 is empty.
+#define I2S_CLEAR_INT_RF_EMPTY                      BIT5  //!< Clear the I2S interrupt for RX FIFO_0 is empty (MIC path).
+#define I2S_CLEAR_INT_TF_EMPTY                      BIT4  //!< Clear the I2S interrupt for TX FIFO_0 is empty (SPK path).
+#define I2S_CLEAR_INT_RF_FULL                       BIT3  //!< Clear the I2S interrupt for RX FIFO_0 is full (MIC path).
+#define I2S_CLEAR_INT_TF_FULL                       BIT2  //!< Clear the I2S interrupt for TX FIFO_0 is full (SPK path).
+#define I2S_CLEAR_INT_RX_READY                      BIT1  //!< Clear the I2S interrupt is ready to receive data (MIC path).
+#define I2S_CLEAR_INT_TX_READY                      BIT0  //!< Clear the I2S interrupt is ready to send data out (SPK path).
+
+#define IS_I2S_CLEAR_INT(CLEAR)          (((CLEAR) == I2S_CLEAR_INT_RX_READY) || \
+                                          ((CLEAR) == I2S_CLEAR_INT_TX_READY) || \
+                                          ((CLEAR) == I2S_CLEAR_INT_RX_READY) || \
+                                          ((CLEAR) == I2S_CLEAR_INT_TX_READY))
+
+/** End of I2S_Clear_Interrupt_Definition
+  * \}
+  */
+
+/**
+ * \defgroup    I2S_TX_Selection I2S TX Selection
+ * \{
+ * \ingroup     I2S_Exported_Constants
+ */
+typedef enum
+{
+    I2S_TX_FIFO_0_REG_0_L,                        //!< I2S left channel FIFO data storage selects the REG_0 register.
+    I2S_TX_FIFO_0_REG_0_R,                        //!< I2S right channel FIFO data storage selects the REG_0 register.
+    I2S_TX_FIFO_0_REG_1_L,                        //!< I2S left channel FIFO data storage selects the REG_1 register.
+    I2S_TX_FIFO_0_REG_1_R,                        //!< I2S right channel FIFO data storage selects the REG_1 register.
+    I2S_TX_SEL_MAX,                               //!< Maximum I2S TX selection.
+} I2STxSel_TypeDef;
+
+/** End of I2S_TX_Selection
+  * \}
+  */
+
+/**
+ * \defgroup    I2S_RX_Channel_Selection I2S RX Channel Selection
+ * \{
+ * \ingroup     I2S_Exported_Constants
+ */
+typedef enum
+{
+    I2S_RX_CHANNEL_0,                             //!< I2S RX channel 0.
+    I2S_RX_CHANNEL_1,                             //!< I2S RX channel 1.
+    I2S_RX_CHANNEL_2,                             //!< I2S RX channel 2.
+    I2S_RX_CHANNEL_3,                             //!< I2S RX channel 3.
+    I2S_RX_SEL_MAX,                               //!< Maximum I2S RX channel selection.
+} I2SRxSel_TypeDef;
+
+/** End of I2S_RX_Channel_Selection
+  * \}
+  */
+
+/** End of I2S_Exported_Constants
+  * \}
+  */
+
+/*============================================================================*
+ *                         Functions
+ *============================================================================*/
+/** \defgroup I2S_Exported_Functions I2S Exported Functions
+  * \brief
+  * \{
+  */
+
+/**
+ * \brief   Deinitialize the I2S peripheral registers to their default values.
+ *
+ * \param[in] I2Sx  Selected I2S peripheral. Refer to \ref I2S_Declaration.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_i2s_init(void)
+ * {
+ *     I2S_DeInit(I2S0);
+ * }
+ * \endcode
+ */
+void I2S_DeInit(I2S_TypeDef *I2Sx);
+
+/**
+ * \brief   Initialize the I2S peripheral according to the specified parameters in the I2S_InitStruct.
+ *
+ * \param[in] I2Sx            Selected I2S peripheral. Refer to \ref I2S_Declaration.
+ * \param[in] I2S_InitStruct  Pointer to a I2S_InitTypeDef structure which will be initialized.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_i2s_init(void)
+ * {
+ *     RCC_PeriphClockCmd(APB_I2S, APB_I2S_CLOCK, ENABLE);
+ *
+ *     I2S_InitTypeDef I2S_InitStruct;
+ *
+ *     I2S_StructInit(&I2S_InitStruct);
+ *     I2S_InitStruct.I2S_ClockSource      = I2S_CLK_40M;
+ *     I2S_InitStruct.I2S_BClockMi         = 0x271;
+ *     I2S_InitStruct.I2S_BClockNi         = 0x10;
+ *     I2S_InitStruct.I2S_DeviceMode       = I2S_DeviceMode_Master;
+ *     I2S_InitStruct.I2S_ChannelType      = I2S_Channel_stereo;
+ *     I2S_InitStruct.I2S_DataWidth        = I2S_Width_16Bits;
+ *     I2S_InitStruct.I2S_DataFormat       = I2S_Mode;
+ *     I2S_InitStruct.I2S_DMACmd           = I2S_DMA_DISABLE;
+ *     I2S_Init(I2S0, &I2S_InitStruct);
+ *     I2S_Cmd(I2S0, I2S_MODE_TX, ENABLE);
+ * }
+ * \endcode
+ */
+void I2S_Init(I2S_TypeDef *I2Sx, I2S_InitTypeDef *I2S_InitStruct);
+
+/**
+ * \brief   Fill each I2S_InitStruct member with its default value.
+ *
+ * \note The default settings for the I2S_InitStruct member are shown in the following table:
+ *       | I2S_InitStruct member        | Default value                        |
+ *       |:----------------------------:|:------------------------------------:|
+ *       | I2S_ClockSource              | \ref I2S_CLK_40M                     |
+ *       | I2S_Scheme                   | \ref I2S_SCHEME_SEPARATE             |
+ *       | I2S_TxBClockMi               | 0x271                                |
+ *       | I2S_TxBClockNi               | 0x10                                 |
+ *       | I2S_TxBClockDiv              | 0x3F                                 |
+ *       | I2S_RxBClockMi               | 0x271                                |
+ *       | I2S_RxBClockNi               | 0x10                                 |
+ *       | I2S_RxBClockDiv              | 0x3F                                 |
+ *       | I2S_DeviceMode               | \ref I2S_DeviceMode_Master           |
+ *       | I2S_TxChannelType            | \ref I2S_Channel_Mono                |
+ *       | I2S_RxChannelType            | \ref I2S_Channel_Mono                |
+ *       | I2S_TxChSequence             | \ref I2S_CH_L_R                      |
+ *       | I2S_RxChSequence             | \ref I2S_CH_L_R                      |
+ *       | I2S_TxDataFormat             | \ref I2S_Mode                        |
+ *       | I2S_RxDataFormat             | \ref I2S_Mode                        |
+ *       | I2S_TxBitSequence            | \ref I2S_MSB_First                   |
+ *       | I2S_RxBitSequence            | \ref I2S_MSB_First                   |
+ *       | I2S_TxDataWidth              | \ref I2S_Width_16Bits                |
+ *       | I2S_RxDataWidth              | \ref I2S_Width_16Bits                |
+ *       | I2S_TxChannelWidth           | \ref I2S_Width_32Bits                |
+ *       | I2S_RxChannelWidth           | \ref I2S_Width_32Bits                |
+ *       | I2S_TxFifoUsed               | \ref I2S_FIFO_USE_0_REG_0            |
+ *       | I2S_RxFifoUsed               | \ref I2S_FIFO_USE_0_REG_0            |
+ *       | I2S_TxWaterlevel             | 16                                   |
+ *       | I2S_RxWaterlevel             | 16                                   |
+ *       | I2S_BClockFixEn              | DISABLE                              |
+ *
+ * \param[in] I2S_InitStruct  Pointer to an I2S_InitTypeDef structure which will be initialized.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_i2s_init(void)
+ * {
+ *     RCC_PeriphClockCmd(APB_I2S, APB_I2S_CLOCK, ENABLE);
+ *
+ *     I2S_InitTypeDef I2S_InitStruct;
+ *
+ *     I2S_StructInit(&I2S_InitStruct);
+ *     I2S_InitStruct.I2S_ClockSource      = I2S_CLK_40M;
+ *     I2S_InitStruct.I2S_TxBClockMi         = 0x271;
+ *     I2S_InitStruct.I2S_TxBClockNi         = 0x10;
+ *     I2S_InitStruct.I2S_DeviceMode       = I2S_DeviceMode_Master;
+ *     I2S_InitStruct.I2S_TxChannelType      = I2S_Channel_stereo;
+ *     I2S_InitStruct.I2S_TxDataWidth        = I2S_Width_16Bits;
+ *     I2S_InitStruct.I2S_TxDataFormat       = I2S_Mode;
+ *     I2S_InitStruct.I2S_DMACmd           = I2S_DMA_DISABLE;
+ *     I2S_Init(I2S0, &I2S_InitStruct);
+ *     I2S_Cmd(I2S0, I2S_MODE_TX, ENABLE);
+ * }
+ * \endcode
+ */
+void I2S_StructInit(I2S_InitTypeDef *I2S_InitStruct);
+/**
+ * \brief   Enable or disable the selected I2S mode.
+ *
+ * \param[in] I2Sx      Selected I2S peripheral. Refer to \ref I2S_Declaration.
+ * \param[in] mode      Selected I2S operation mode.
+ *                      This parameter can be the following values:
+ *                      \arg I2S_MODE_TX: Transmission mode.
+ *                      \arg I2S_MODE_RX: Receiving mode.
+ * \param[in] NewState  New state of the operation mode.
+ *                      - ENABLE: Enable the specified mode of I2S.
+ *                      - DISABLE: Disable the specified mode of I2S.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_i2s_init(void)
+ * {
+ *     RCC_PeriphClockCmd(APB_I2S, APB_I2S_CLOCK, ENABLE);
+ *
+ *     I2S_InitTypeDef I2S_InitStruct;
+ *
+ *     I2S_StructInit(&I2S_InitStruct);
+ *     I2S_InitStruct.I2S_ClockSource      = I2S_CLK_40M;
+ *     I2S_InitStruct.I2S_TxBClockMi         = 0x271;
+ *     I2S_InitStruct.I2S_TxBClockNi         = 0x10;
+ *     I2S_InitStruct.I2S_DeviceMode       = I2S_DeviceMode_Master;
+ *     I2S_InitStruct.I2S_TxChannelType      = I2S_Channel_stereo;
+ *     I2S_InitStruct.I2S_TxDataWidth        = I2S_Width_16Bits;
+ *     I2S_InitStruct.I2S_TxDataFormat       = I2S_Mode;
+ *     I2S_InitStruct.I2S_DMACmd           = I2S_DMA_DISABLE;
+ *     I2S_Init(I2S_NUM, &I2S_InitStruct);
+ *     I2S_Cmd(I2S_NUM, I2S_MODE_TX, ENABLE);
+ * }
+ * \endcode
+ */
+void I2S_Cmd(I2S_TypeDef *I2Sx, uint32_t mode, FunctionalState NewState);
+
+/**
+ * \brief   Enable or disable the specified I2S interrupt source.
+ *
+ * \param[in] I2Sx      Selected I2S peripheral. Refer to \ref I2S_Declaration.
+ * \param[in] I2S_INT   Specify the specified interrupt of I2S.
+ *                      This parameter can be the following values, refer to \ref I2S_Interrupt_Definition.
+ *                      \arg I2S_INT_TX_IDLE: Transmit idle interrupt source.
+ *                      \arg I2S_INT_RF_EMPTY: Receive FIFO empty interrupt source.
+ *                      \arg I2S_INT_TF_EMPTY: Transmit FIFO empty interrupt source.
+ *                      \arg I2S_INT_RF_FULL: Receive FIFO full interrupt source.
+ *                      \arg I2S_INT_TF_FULL: Transmit FIFO full interrupt source.
+ *                      \arg I2S_INT_RX_READY: Ready to receive interrupt source.
+ *                      \arg I2S_INT_TX_READY: Ready to transmit interrupt source.
+ * \param[in] newState  New state of the specified I2S interrupt.
+ *                      - ENABLE: Enable the specified interrupt of I2S.
+ *                      - DISABLE: Disable the specified interrupt of I2S.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void i2s_demo(void)
+ * {
+ *     I2S_INTConfig(I2S0, I2S_INT_TF_EMPTY, ENABLE);
+ * }
+ * \endcode
+ */
+void I2S_INTConfig(I2S_TypeDef *I2Sx, uint32_t I2S_INT, FunctionalState newState);
+
+/**
+ * \brief   Get the specified I2S interrupt status.
+ *
+ * \param[in] I2Sx     Selected I2S peripheral. Refer to \ref I2S_Declaration.
+ * \param[in] I2S_INT  Specify the specified interrupt of I2S.
+ *                     This parameter can be one of the following values, refer to \ref I2S_Interrupt_Definition.
+ *                     \arg I2S_INT_TX_IDLE: Transmit idle interrupt.
+ *                     \arg I2S_INT_RF_EMPTY: Receive FIFO empty interrupt.
+ *                     \arg I2S_INT_TF_EMPTY: Transmit FIFO empty interrupt.
+ *                     \arg I2S_INT_RF_FULL: Receive FIFO full interrupt.
+ *                     \arg I2S_INT_TF_FULL: Transmit FIFO full interrupt.
+ *                     \arg I2S_INT_RX_READY: Ready to receive interrupt.
+ *                     \arg I2S_INT_TX_READY: Ready to transmit interrupt.
+ *
+ * \return The status of I2S specified interrupt.
+ *         - SET: The interrupt status of I2S is set.
+ *         - RESET: The interrupt status of I2S has not been set.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void i2s_demo(void)
+ * {
+ *     ITStatus int_status = I2S_GetINTStatus(I2S0, I2S_INT_TF_EMPTY);
+ * }
+ * \endcode
+ */
+ITStatus I2S_GetINTStatus(I2S_TypeDef *I2Sx, uint32_t I2S_INT);
+
+/**
+ * \brief  Clear the I2S interrupt pending bit.
+ *
+ * \param[in] I2Sx           Selected I2S peripheral. Refer to \ref I2S_Declaration.
+ * \param[in] I2S_CLEAR_INT  Specify the interrupt pending bit to clear.
+ *                           This parameter can be any combination of the following values:
+ *                           - I2S_CLEAR_INT_RX_READY: Clear ready to receive interrupt.
+ *                           - I2S_CLEAR_INT_TX_READY: Clear ready to transmit interrupt.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void i2s_demo(void)
+ * {
+ *     I2S_ClearINTPendingBit(I2S0, I2S_CLEAR_INT_RX_READY);
+ * }
+ * \endcode
+ */
+void I2S_ClearINTPendingBit(I2S_TypeDef *I2Sx, uint32_t I2S_CLEAR_INT);
+
+/**
+ * \brief   Transmits a data through the I2Sx peripheral.
+ *
+ * \param[in] I2Sx  Selected I2S peripheral. Refer to \ref I2S_Declaration.
+ * \param[in] Data  Data to be transmitted.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void i2s_demo(void)
+ * {
+ *     I2S_SendData(I2S0, 0x02);
+ * }
+ * \endcode
+ */
+void I2S_SendData(I2S_TypeDef *I2Sx, uint32_t Data);
+
+
+/**
+ * \brief  Received data by the I2Sx peripheral.
+ *
+ * \param[in] I2Sx  Selected I2S peripheral. Refer to \ref I2S_Declaration.
+ *
+ * \return Return the most recent received data.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void i2s_demo(void)
+ * {
+ *     uint32_t data = I2S_ReceiveData(I2S0);
+ * }
+ * \endcode
+ */
+uint32_t I2S_ReceiveFIFOData(I2S_TypeDef *I2Sx);
+
+/**
+ * \brief   Get transmit FIFO free length by the I2Sx peripheral.
+ *
+ * \param[in] I2Sx  Selected I2S peripheral. Refer to \ref I2S_Declaration.
+ *
+ * \return  The free length of transmit FIFO .
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void i2s_demo(void)
+ * {
+ *     uint8_t data_len = I2S_GetTxFIFOFreeLen(I2S0);
+ * }
+ * \endcode
+ */
+uint8_t I2S_GetTxFIFOFreeLen(I2S_TypeDef *I2Sx);
+
+/**
+ * \brief   Get receive FIFO data length by the I2Sx peripheral.
+ *
+ * \param[in] I2Sx  Selected I2S peripheral. Refer to \ref I2S_Declaration.
+ *
+ * \return  The data length of the receive FIFO.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void i2s_demo(void)
+ * {
+ *     uint8_t data_len = I2S_GetRxFIFOLen(I2S0);
+ * }
+ * \endcode
+ */
+uint8_t I2S_GetRxFIFOLen(I2S_TypeDef *I2Sx);
+
+/**
+ * \brief   Get the send error counter value by the I2Sx peripheral.
+ *
+ * \param[in] I2Sx  Selected I2S peripheral. Refer to \ref I2S_Declaration.
+ *
+ * \return  The send error counter value.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void i2s_demo(void)
+ * {
+ *     uint8_t conter = I2S_GetTxErrCnt(I2S0);
+ * }
+ * \endcode
+ */
+uint8_t I2S_GetTxErrCnt(I2S_TypeDef *I2Sx);
+
+/**
+ * \brief  Get the reception error counter value by the I2Sx peripheral.
+ *
+ * \param[in] I2Sx  Selected I2S peripheral. Refer to \ref I2S_Declaration.
+ *
+ * \return  The reception error counter value.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void i2s_demo(void)
+ * {
+ *     uint8_t conter = I2S_GetRxErrCnt(I2S0);
+ * }
+ * \endcode
+ */
+uint8_t I2S_GetRxErrCnt(I2S_TypeDef *I2Sx);
+
+/**
+ * \brief   Swap audio data bytes sequence that is sent by the I2Sx peripheral.
+ *
+ * \param[in] I2Sx      Selected I2S peripheral. Refer to \ref I2S_Declaration.
+ * \param[in] NewState  New state of the bytes sequence.
+ *                      - ENABLE: Enable swapping of the sent audio data byte sequence.
+ *                      - DISABLE: Disable swapping of the sent audio data byte sequence.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void i2s_demo(void)
+ * {
+ *     I2S_SwapBytesForSend(I2S0, ENABLE);
+ * }
+ * \endcode
+ */
+void I2S_SwapBytesForSend(I2S_TypeDef *I2Sx, FunctionalState NewState);
+
+/**
+ * \brief   Swap audio data bytes sequence that is read by the I2Sx peripheral.
+ *
+ * \param[in] I2Sx      Selected I2S peripheral. Refer to \ref I2S_Declaration.
+ * \param[in] NewState  New state of the bytes sequence.
+ *                      - ENABLE: Enable the swapping of the audio data byte sequence that is read.
+ *                      - DISABLE: Disable the swapping of the audio data byte sequence that is read.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void i2s_demo(void)
+ * {
+ *     I2S_SwapBytesForRead(I2S0, ENABLE);
+ * }
+ * \endcode
+ */
+void I2S_SwapBytesForRead(I2S_TypeDef *I2Sx, FunctionalState NewState);
+
+/**
+ * \brief  Swap audio channel data that is sent by the I2Sx peripheral.
+ *
+ * \param[in] I2Sx      Selected I2S peripheral. Refer to \ref I2S_Declaration.
+ * \param[in] NewState  New state of the left and right channel data sequence.
+ *                      - ENABLE: Enable swapping of the sent audio channel data sequence.
+ *                      - DISABLE: Disable swapping of the sent audio channel data sequence.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void i2s_demo(void)
+ * {
+ *     I2S_SwapLRChDataForSend(I2S0, ENABLE);
+ * }
+ * \endcode
+ */
+void I2S_SwapLRChDataForSend(I2S_TypeDef *I2Sx, FunctionalState NewState);
+
+/**
+ * \brief   Swap audio channel data that is read by the I2Sx peripheral.
+ *
+ * \param[in] I2Sx      Selected I2S peripheral. Refer to \ref I2S_Declaration.
+ * \param[in] NewState  New state of the left and right channel data sequence.
+ *                      - ENABLE: Enable the swapping of the audio channel data sequence that is read.
+ *                      - DISABLE: Disable the swapping of the audio channel data sequence that is read.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void i2s_demo(void)
+ * {
+ *     I2S_SwapLRChDataForRead(I2S0, ENABLE);
+ * }
+ * \endcode
+ */
+void I2S_SwapLRChDataForRead(I2S_TypeDef *I2Sx, FunctionalState NewState);
+
+/**
+ * \brief   Enable or disable the MCLK output selection.
+ *
+ * \param[in] I2Sx      Selected I2S peripheral. Refer to \ref I2S_Declaration.
+ * \param[in] NewState  New state of MCLK output.
+ *                      - ENABLE: Enable the MCLK output selection.
+ *                      - DISABLE: Disable the MCLK output selection.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void i2s_demo(void)
+ * {
+ *     I2S_MCLKOutputSelectCmd(I2S0);
+ * }
+ * \endcode
+ */
+void I2S_MCLKOutputSelectCmd(I2S_TypeDef *I2Sx, FunctionalState NewState);
+
+/**
+ * \brief   I2S0 communication selection which can be from internal codec or external codec.
+ *
+ * \param[in] I2Sx      Selected I2S peripheral. Refer to \ref I2S_Declaration.
+ * \param[in] NewState  New state of I2S0 communication selection.
+ *                      - ENABLE: I2S communication selects the internal codec.
+ *                      - DISABLE: I2S communication selects the external codec.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void i2s_demo(void)
+ * {
+ *     I2S_WithExtCodecCmd(ENABLE);
+ * }
+ * \endcode
+ */
+void I2S_WithExtCodecCmd(I2S_TypeDef *I2Sx, FunctionalState NewState);
+
+
+/**
+ * \brief   Configure BCLK clock.
+ *
+ * \param[in] I2Sx          Selected I2S peripheral. Refer to \ref I2S_Declaration.
+ * \param[in] dir           Selected I2S operation mode.
+ *                          This parameter can be the following values:
+ *                          \arg I2S_MODE_TX: Transmission mode.
+ *                          \arg I2S_MODE_RX: Receiving mode.
+ * \param[in] I2S_BClockMi  Mi parameter.
+ * \param[in] I2S_BClockNi  Ni parameter.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void i2s_demo(void)
+ * {
+ *     I2S_UpdateBClk(I2S0, 0x271, 0x10);
+ * }
+ * \endcode
+ */
+void I2S_UpdateBClk(I2S_TypeDef *I2Sx, uint32_t dir, uint16_t I2S_BClockMi,
+                    uint16_t I2S_BClockNi);
+
+#if I2S_SUPPORT_TRX_INDEPENDENT_CONTROL
+/**
+ * \brief   Get Tx BCLK clock status.
+ *
+ * \param[in] I2Sx  Selected I2S peripheral. Refer to \ref I2S_Declaration.
+ *
+ * \return  Execution status.
+ *          - SET: BLCK is updating.
+ *          - RESET: BLCK update is done.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void i2s_demo(void)
+ * {
+ *     FlagStatus status = I2S_GetTxBClkStatus(I2S0);
+ * }
+ * \endcode
+ */
+FlagStatus I2S_GetTxBClkStatus(I2S_TypeDef *I2Sx);
+
+/**
+ * \brief   Get Rx BCLK clock status.
+ *
+ * \param[in] I2Sx  Selected I2S peripheral. Refer to \ref I2S_Declaration.
+ *
+ * \return  Execution status.
+ *          - SET: BLCK is updating.
+ *          - RESET: BLCK update is done.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void i2s_demo(void)
+ * {
+ *     FlagStatus status = I2S_GeRxBClkStatus(I2S0);
+ * }
+ * \endcode
+ */
+FlagStatus I2S_GetRxBClkStatus(I2S_TypeDef *I2Sx);
+
+#else
+/**
+ * \brief   Get BCLK clock status.
+ *
+ * \param[in] I2Sx  Selected I2S peripheral. Refer to \ref I2S_Declaration.
+ *
+ * \return  Execution status.
+ *          - SET: BLCK is updating.
+ *          - RESET: BLCK update is done.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void i2s_demo(void)
+ * {
+ *     FlagStatus status = I2S_GeRxBClkStatus(I2S0);
+ * }
+ * \endcode
+ */
+FlagStatus I2S_GetBClkStatus(I2S_TypeDef *I2Sx);
+
+#endif
+/** End of I2S_Exported_Functions
+  * \}
+  */
+
+/** End of I2S
+  * \}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RTL_I2S_H */
+
+
+
diff --git a/bee/drivers/i2s/src/device/rtl87x2g/rtl_i2s_def.h b/bee/drivers/i2s/src/device/rtl87x2g/rtl_i2s_def.h
new file mode 100644
index 00000000..a5b4c7f6
--- /dev/null
+++ b/bee/drivers/i2s/src/device/rtl87x2g/rtl_i2s_def.h
@@ -0,0 +1,716 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef RTL_I2S_DEF_H
+#define RTL_I2S_DEF_H
+
+#include "utils/rtl_utils.h"
+#include "address_map.h"
+
+#ifdef  __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+
+/*============================================================================*
+ *                          I2S Defines
+ *============================================================================*/
+/** \defgroup I2S         I2S
+  * \brief
+  * \{
+  */
+
+/** \defgroup I2S_Exported_Constants I2S Exported Constants
+  * \brief
+  * \{
+  */
+
+/**
+ * \defgroup I2S_Defines I2S Defines
+ * \{
+ * \ingroup  I2S_Exported_Constants
+ */
+
+#define I2S_SUPPORT_TRX_INDEPENDENT_CONTROL (1) //!< The chip supports TX&RX independent control of data format.
+#define I2S_SUPPORT_TRX_FIFO                (1) //!< The chip supports TX&RX FIFO.
+#define I2S_SUPPORT_INT_TX_VALID            (1) //!< The chip supports TX valid interrupt.
+#define I2S_SUPPORT_PLL_CLK                 (1) //!< The chip supports PLL clock.
+#define I2S_SUPPORT_DATE_WIDTH_32BIT        (1) //!< The chip supports 32bit data format.
+#define I2S_SUPPORT_MCLK_OUTPUT_SEL         (0) //!< The function is not supported.
+
+/** End of I2S_Defines
+  * \}
+  */
+
+/** End of I2S_Exported_Constants
+  * \}
+  */
+
+/** End of I2S
+  * \}
+  */
+
+/*============================================================================*
+ *                         I2S Private Defines
+ *============================================================================*/
+/*  I2S_CLR_RX_ERR_CNT. */
+#define I2S_CLR_RX_ERR_CNT_MSK        (0x1 << 13)
+#define I2S_CLR_RX_ERR_CNT_CLR        (~I2S_CLR_RX_ERR_CNT_MSK)
+/* I2S_CLR_TX_ERR_CNT. */
+#define I2S_CLR_TX_ERR_CNT_MSK        (0x1 << 12)
+#define I2S_CLR_TX_ERR_CNT_CLR        (~I2S_CLR_TX_ERR_CNT_MSK)
+
+#define I2S_RX_FIFO_DEPTH_CNT_0_POS   (8)
+#define I2S_RX_ERR_CNT_POS            (15)
+#define I2S_MI_NI_UPDATE_MSK          ((uint32_t)0x1 << 31)
+
+#define I2S_FRAME_SYNC_OFFSET_DEFAULT (0x81)
+
+
+/*============================================================================*
+ *                          APB_I2S Registers Memory Map
+ *============================================================================*/
+typedef struct
+{
+    __IO uint32_t I2S_TX_FIFO_WR_ADDR;          /*!< 0x00 */
+    __IO uint32_t I2S_CTRL;                     /*!< 0x04 */
+    __IO uint32_t I2S_FIFO_EN_CLK_CON;          /*!< 0x08 */
+    __IO uint32_t I2S_INTR_CON;                 /*!< 0x0C */
+    __IO uint32_t I2S_RX_FIFO_RD_ADDR;          /*!< 0x10 */
+    __IO uint32_t I2S_FIFO_CNT_STA;             /*!< 0x14 */
+    __IO uint32_t I2S_TX_RX_ERR_STA;            /*!< 0x18 */
+    __IO uint32_t I2S_TX_FRA_DIV;               /*!< 0x1C */
+    __IO uint32_t I2S_LRCK_FIFO_TH_CON;         /*!< 0x20 */
+    __IO uint32_t I2S_FIFO_STA;                 /*!< 0x24 */
+    __IO uint32_t I2S_FORM_CON;                 /*!< 0x28 */
+    __IO uint32_t I2S_RX_FRA_DIV;               /*!< 0x2C */
+    __IO uint32_t I2S_TX_CNT_CTRL;              /*!< 0x30 */
+    __IO uint32_t I2S_TX_CNT_VAL;               /*!< 0x34 */
+    __IO uint32_t I2S_TX_CH_DATA_MIX;           /*!< 0x38 */
+    __IO uint32_t I2S_TX_CH_DATA_SEL;           /*!< 0x3C */
+    __IO uint32_t RSVD_0;                       /**< 0x40 */
+    __IO uint32_t RSVD_1;                       /**< 0x44 */
+    __IO uint32_t RSVD_2;                       /**< 0x48 */
+    __IO uint32_t RSVD_3;                       /**< 0x4C */
+    __IO uint32_t RSVD_4;                       /**< 0x50 */
+    __IO uint32_t I2S_I2S_RX_FIFO_REG0;         /*!< 0x54 */
+    __IO uint32_t RSVD_5;                       /**< 0x58 */
+    __IO uint32_t I2S_RX_CNT_CTRL;              /*!< 0x5C */
+    __IO uint32_t I2S_RX_CNT_VAL;               /*!< 0x60 */
+    __IO uint32_t I2S_TX_VAL_CNT;               /*!< 0x64 */
+    __IO uint32_t I2S_FIFO_CNT_LATCH;           /*!< 0x68 */
+} I2S_TypeDef;
+
+/*============================================================================*
+ *                          I2S Declaration
+ *============================================================================*/
+/** \defgroup I2S         I2S
+  * \brief
+  * \{
+  */
+
+/** \defgroup I2S_Exported_Constants I2S Exported Constants
+  * \brief
+  * \{
+  */
+
+/** \defgroup I2S_Declaration I2S Declaration
+  * \{
+  * \ingroup  I2S_Exported_Constants
+  */
+#define I2S0                ((I2S_TypeDef *) I2S0_REG_BASE)   //!< I2S0 base address.
+#define I2S1                ((I2S_TypeDef *) I2S1_REG_BASE)   //!< I2S1 base address.
+
+#define IS_I2S_PERIPH(PERIPH)     (((PERIPH) == I2S0) || \
+                                   ((PERIPH) == I2S1)) //!< Check if the input parameter is valid.
+
+/** End of I2S_Declaration
+  * \}
+  */
+
+/** End of I2S_Exported_Constants
+  * \}
+  */
+
+/** End of I2S
+  * \}
+  */
+
+/*============================================================================*
+ *                         I2S Registers and Field Descriptions
+ *============================================================================*/
+/* 0x00
+   31:0    W      TX_FIFO_WR_ADDR             32'b0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t TX_FIFO_WR_ADDR: 32;
+    } b;
+} I2S_TX_FIFO_WR_ADDR_TypeDef;
+
+/* 0x04
+   0       R/W    sp_reset                    1'b0
+   1       R/W    tx_inv_i2s_sclk             1'b0
+   2       R/W    rx_inv_i2s_sclk             1'b0
+   3       R/W    slave_clk_sel               1'b0
+   4       R/W    slave_data_sel              1'b0
+   5       R/W    sp_wclk_tx_inverse          1'h0
+   6       R/W   sp_loopback                 1'b0
+   7       R/W    dsp_ctl_mode                1'b0
+   9:8     R/W    sp_data_format_sel_tx       2'b00
+   10      R/W    sp_inv_i2s_sclk             1'b0
+   11      R/W    sp_en_i2s_mono_tx           1'b0
+   14:12   R/W    sp_data_len_sel_tx          3'b00
+   15      R/W    sp_i2s_self_lpbk_en         1'b0
+   16      R/W    sp_tx_disable               1'b1
+   17      R/W    sp_start_tx                 1'b0
+   19:18   R/W    reserved15                  2'b00
+   21:20   R/W    reserved14                  2'b00
+   22      R/W    tx_lsb_first                1'b0
+   23      R/W    rx_lsb_first                1'b0
+   24      R/W    sp_rx_disable               1'b1
+   25      R/W    sp_start_rx                 1'b0
+   27:26   R/W    sp_sel_i2s_tx_ch            2'b00
+   29:28   R/W    sp_sel_i2s_rx_ch            2'b00
+   30      R/W    mclk_sel                    1'b0
+   31      R/W    reserved6                   1'b1
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t sp_reset: 1;
+        uint32_t tx_inv_i2s_sclk: 1;
+        uint32_t rx_inv_i2s_sclk: 1;
+        uint32_t slave_clk_sel: 1;
+        uint32_t slave_data_sel: 1;
+        uint32_t sp_wclk_tx_inverse: 1;
+        uint32_t sp_loopback: 1;
+        uint32_t dsp_ctl_mode: 1;
+        uint32_t sp_data_format_sel_tx: 2;
+        uint32_t sp_inv_i2s_sclk: 1;
+        uint32_t sp_en_i2s_mono_tx: 1;
+        uint32_t sp_data_len_sel_tx: 3;
+        uint32_t sp_i2s_self_lpbk_en: 1;
+        uint32_t sp_tx_disable: 1;
+        uint32_t sp_start_tx: 1;
+        uint32_t reserved_2: 2;
+        uint32_t reserved_1: 2;
+        uint32_t tx_lsb_first: 1;
+        uint32_t rx_lsb_first: 1;
+        uint32_t sp_rx_disable: 1;
+        uint32_t sp_start_rx: 1;
+        uint32_t sp_sel_i2s_tx_ch: 2;
+        uint32_t sp_sel_i2s_rx_ch: 2;
+        uint32_t mclk_sel: 1;
+        uint32_t reserved_0: 1;
+    } b;
+} I2S_CTRL_TypeDef;
+
+/* 0x08
+   4:0     R/W    reserved51                  5'h0
+   5       R/W    bclk_reset                  1'b0
+   7:6     R/W    reserved49                  2'b0
+   10:8    R/W    debug_bus_sel               3'h0
+   11      R/W    enable_mclk                 1'b0
+   12      R/W    clear_tx_err_cnt            1'b0
+   13      R/W    clear_rx_err_cnt            1'b0
+   15:14   R/W    i2s_clk_sel                 2'h0
+   16      R/W    err_cnt_sat_set             1'b0
+   19:17   R/W    reserved42                  3'h0
+   20      R/W    tx_src_byte_swap            1'b0
+   21      R/W    tx_src_lr_swap              1'b0
+   22      R/W    rx_snk_byte_swap            1'b0
+   23      R/W    rx_snk_lr_swap              1'b0
+   24      R/W    tx_fifo_0_reg_0_en          1'b1
+   25      R/W    tx_fifo_0_reg_1_en          1'b0
+   27:26   R/W    reserved35                  2'h0
+   28      R/W    rx_fifo_0_reg_0_en          1'b1
+   29      R/W    rx_fifo_0_reg_1_en          1'b0
+   31:30   R/W    reserved32                  2'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t reserved_4: 5;
+        uint32_t bclk_reset: 1;
+        uint32_t reserved_3: 2;
+        uint32_t debug_bus_sel: 3;
+        uint32_t enable_mclk: 1;
+        uint32_t clear_tx_err_cnt: 1;
+        uint32_t clear_rx_err_cnt: 1;
+        uint32_t i2s_clk_sel: 2;
+        uint32_t err_cnt_sat_set: 1;
+        uint32_t reserved_2: 3;
+        uint32_t tx_src_byte_swap: 1;
+        uint32_t tx_src_lr_swap: 1;
+        uint32_t rx_snk_byte_swap: 1;
+        uint32_t rx_snk_lr_swap: 1;
+        uint32_t tx_fifo_0_reg_0_en: 1;
+        uint32_t tx_fifo_0_reg_1_en: 1;
+        uint32_t reserved_1: 2;
+        uint32_t rx_fifo_0_reg_0_en: 1;
+        uint32_t rx_fifo_0_reg_1_en: 1;
+        uint32_t reserved_0: 2;
+    } b;
+} I2S_FIFO_EN_CLK_CON_TypeDef;
+
+/* 0x0C
+   0       R/W    tx_dsp_clear_int_0          1'b0
+   1       R/W    rx_dsp_clear_int_0          1'b0
+   6:2     R/W    intr_clr_0                  5'h0
+   13:7    R/W    reserved57                  7'h0
+   14      R/W    tx_fifo_data_valid_intr_clr 1'b0
+   15      R/W    reserved55                  1'b0
+   23:16   R/W    int_enable_dsp_0            8'h0
+   31:24   R/W    reserved53                  8'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t tx_dsp_clear_int_0: 1;
+        uint32_t rx_dsp_clear_int_0: 1;
+        uint32_t intr_clr_0: 5;
+        uint32_t reserved_2: 7;
+        uint32_t tx_fifo_data_valid_intr_clr: 1;
+        uint32_t reserved_1: 1;
+        uint32_t int_enable_dsp_0: 8;
+        uint32_t reserved_0: 8;
+    } b;
+} I2S_INTR_CON_TypeDef;
+
+/* 0x10
+   31:0    R      RX_FIFO_RD_ADDR             32'b0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t RX_FIFO_RD_ADDR: 32;
+    } b;
+} I2S_RX_FIFO_RD_ADDR_TypeDef;
+
+/* 0x14
+   5:0     R      tx_depth_cnt_0              6'h20
+   7:6     R      dummy67                     2'b00
+   13:8    R      rx_depth_cnt_0              6'h0
+   30:14   R      dummy65                     17'h0
+   31      R      dummy64                     1'b0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t tx_depth_cnt_0: 6;
+        const uint32_t dummy67: 2;
+        const uint32_t rx_depth_cnt_0: 6;
+        const uint32_t dummy65: 17;
+        const uint32_t dummy64: 1;
+    } b;
+} I2S_FIFO_CNT_STA_TypeDef;
+
+/* 0x18
+   15:0    R      tx_err_cnt                  16'h0
+   31:16   R      rx_err_cnt                  16'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t tx_err_cnt: 16;
+        const uint32_t rx_err_cnt: 16;
+    } b;
+} I2S_TX_RX_ERR_STA_TypeDef;
+
+/* 0x1C
+   15:0    R/W    tx_mi                       16'h625
+   30:16   R/W    tx_ni                       15'h48
+   31      R/W    tx_mi_ni_update             1'b0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t tx_mi: 16;
+        uint32_t tx_ni: 15;
+        uint32_t tx_mi_ni_update: 1;
+    } b;
+} I2S_TX_FRA_DIV_TypeDef;
+
+/* 0x20
+   5:0     R/W    txdma_burstsize             6'h10
+   7:6     R/W    reserved81                  2'h0
+   13:8    R/W    rxdma_burstsize             6'h10
+   15:14   R/W    reserved79                  2'h0
+   23:16   R/W    tx_bclk_div_ratio           8'h40
+   31:24   R/W    rx_bclk_div_ratio           8'h40
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t txdma_burstsize: 6;
+        uint32_t reserved_1: 2;
+        uint32_t rxdma_burstsize: 6;
+        uint32_t reserved_0: 2;
+        uint32_t tx_bclk_div_ratio: 8;
+        uint32_t rx_bclk_div_ratio: 8;
+    } b;
+} I2S_LRCK_FIFO_TH_CON_TypeDef;
+
+/* 0x24
+   0       R      sp_ready_to_tx              1'b0
+   1       R      sp_ready_to_rx              1'b0
+   2       R      tx_fifo_full_intr           1'b0
+   3       R      rx_fifo_full_intr           1'b0
+   4       R      tx_fifo_empty_intr          1'b0
+   5       R      rx_fifo_empty_intr          1'b0
+   6       R      tx_i2s_idle                 1'b0
+   15:7    R      dummy90                     9'b0
+   16      R      tx_fifo_data_valid_intr     1'b0
+   27:17   R      dummy88                     11'b0
+   28      R      tx_fifo_full_0              1'b0
+   29      R      rx_fifo_full_0              1'b0
+   30      R      tx_fifo_empty_0             1'b1
+   31      R      rx_fifo_empty_0             1'b1
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t sp_ready_to_tx: 1;
+        const uint32_t sp_ready_to_rx: 1;
+        const uint32_t tx_fifo_full_intr: 1;
+        const uint32_t rx_fifo_full_intr: 1;
+        const uint32_t tx_fifo_empty_intr: 1;
+        const uint32_t rx_fifo_empty_intr: 1;
+        const uint32_t tx_i2s_idle: 1;
+        const uint32_t dummy90: 9;
+        const uint32_t tx_fifo_data_valid_intr: 1;
+        const uint32_t dummy88: 11;
+        const uint32_t tx_fifo_full_0: 1;
+        const uint32_t rx_fifo_full_0: 1;
+        const uint32_t tx_fifo_empty_0: 1;
+        const uint32_t rx_fifo_empty_0: 1;
+    } b;
+} I2S_FIFO_STA_TypeDef;
+
+/* 0x28
+   0       R/W    trx_same_fs                 1'h1
+   1       R/W    trx_same_ch                 1'h1
+   2       R/W    trx_same_length             1'h1
+   3       R/W    sck_out_inverse             1'h0
+   4       R/W    reserved111                 1'h0
+   5       R/W    sp_wclk_rx_inverse          1'h0
+   6       R/W    fixed_bclk_sel              1'h0
+   7       R/W    fixed_bclk                  1'h0
+   9:8     R/W    sp_data_format_sel_rx       2'h0
+   10      R/W    trx_same_lrc                1'h0
+   11      R/W    sp_en_i2s_mono_rx           1'h0
+   14:12   R/W    sp_data_len_sel_rx          3'h0
+   23:15   R/W    reserved103                 9'h0
+   26:24   R/W    sp_ch_len_sel_tx            3'b100
+   27      R/W    reserved101                 1'h0
+   30:28   R/W    sp_ch_len_sel_rx            3'b100
+   31      R/W    trx_same_ch_len             1'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t trx_same_fs: 1;
+        uint32_t trx_same_ch: 1;
+        uint32_t trx_same_length: 1;
+        uint32_t sck_out_inverse: 1;
+        uint32_t reserved_2: 1;
+        uint32_t sp_wclk_rx_inverse: 1;
+        uint32_t fixed_bclk_sel: 1;
+        uint32_t fixed_bclk: 1;
+        uint32_t sp_data_format_sel_rx: 2;
+        uint32_t trx_same_lrc: 1;
+        uint32_t sp_en_i2s_mono_rx: 1;
+        uint32_t sp_data_len_sel_rx: 3;
+        uint32_t reserved_1: 9;
+        uint32_t sp_ch_len_sel_tx: 3;
+        uint32_t reserved_0: 1;
+        uint32_t sp_ch_len_sel_rx: 3;
+        uint32_t trx_same_ch_len: 1;
+    } b;
+} I2S_FORM_CON_TypeDef;
+
+/* 0x2C
+   15:0    R/W    rx_mi                       16'h625
+   30:16   R/W    rx_ni                       15'h48
+   31      R/W    rx_mi_ni_update             1'b0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t rx_mi: 16;
+        uint32_t rx_ni: 15;
+        uint32_t rx_mi_ni_update: 1;
+    } b;
+} I2S_RX_FRA_DIV_TypeDef;
+
+/* 0x30
+   26:0    R/W    tx_i2s_compare_val          27'h64
+   28:27   R/W    reserved124                 2'h0
+   29      W1C    en_fs_phase_latch           1'h0
+   30      R/W    en_tx_i2s_interrupt         1'h0
+   31      W1C    clr_tx_i2s_rdy              1'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t tx_i2s_compare_val: 27;
+        uint32_t reserved_0: 2;
+        uint32_t en_fs_phase_latch: 1;
+        uint32_t en_tx_i2s_interrupt: 1;
+        uint32_t clr_tx_i2s_rdy: 1;
+    } b;
+} I2S_TX_CNT_CTRL_TypeDef;
+
+/* 0x34
+   4:0     R      tx_fs_phase_rpt             5'h0
+   31:5    R      tx_i2s_counter              27'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t tx_fs_phase_rpt: 5;
+        const uint32_t tx_i2s_counter: 27;
+    } b;
+} I2S_TX_CNT_VAL_TypeDef;
+
+
+/* 0x38
+   14:0    R/W    reserved136                 15'h0
+   15      R/W    tx_ch0_mix_sat_set          1'b0
+   18:16   R/W    reserved134                 3'b0
+   19      R/W    tx_ch1_mix_sat_set          1'b0
+   20      R/W    tx_ch0_mix_en               1'b0
+   21      R/W    tx_ch1_mix_en               1'b0
+   31:22   R/W    reserved130                 10'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t reserved_2: 15;
+        uint32_t tx_ch0_mix_sat_set: 1;
+        uint32_t reserved_1: 3;
+        uint32_t tx_ch1_mix_sat_set: 1;
+        uint32_t tx_ch0_mix_en: 1;
+        uint32_t tx_ch1_mix_en: 1;
+        uint32_t reserved_0: 10;
+    } b;
+} I2S_TX_CH_DATA_MIX_TypeDef;
+
+/* 0x3C
+   1:0     R/W    tx_ch0_data_sel             2'h0
+   3:2     R/W    reserved144                 2'h0
+   5:4     R/W    tx_ch1_data_sel             2'h1
+   7:6     R/W    reserved142                 2'h0
+   9:8     R/W    tx_ch2_data_sel             2'h2
+   11:10   R/W    reserved140                 2'h0
+   13:12   R/W    tx_ch3_data_sel             2'h3
+   31:14   R/W    reserved138                 18'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t tx_ch0_data_sel: 2;
+        uint32_t reserved_3: 2;
+        uint32_t tx_ch1_data_sel: 2;
+        uint32_t reserved_2: 2;
+        uint32_t tx_ch2_data_sel: 2;
+        uint32_t reserved_1: 2;
+        uint32_t tx_ch3_data_sel: 2;
+        uint32_t reserved_0: 18;
+    } b;
+} I2S_TX_CH_DATA_SEL_TypeDef;
+
+/* 0x54
+   1:0     R/W    rx_fifo_0_reg_0_l_sel       2'h0
+   7:2     R/W    reserved153                 6'h0
+   9:8     R/W    rx_fifo_0_reg_0_r_sel       2'h1
+   15:10   R/W    reserved151                 6'h0
+   17:16   R/W    rx_fifo_0_reg_1_l_sel       2'h2
+   23:18   R/W    reserved149                 6'h0
+   25:24   R/W    rx_fifo_0_reg_1_r_sel       2'h3
+   31:26   R/W    reserved147                 6'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t rx_fifo_0_reg_0_l_sel: 2;
+        uint32_t reserved_3: 6;
+        uint32_t rx_fifo_0_reg_0_r_sel: 2;
+        uint32_t reserved_2: 6;
+        uint32_t rx_fifo_0_reg_1_l_sel: 2;
+        uint32_t reserved_1: 6;
+        uint32_t rx_fifo_0_reg_1_r_sel: 2;
+        uint32_t reserved_0: 6;
+    } b;
+} I2S_RX_FIFO_REG0_TypeDef;
+
+/* 0x5C
+   26:0    R/W    rx_i2s_compare_val          27'h64
+   29:27   R/W    reserved158                 3'h0
+   30      R/W    en_rx_i2s_interrupt         1'h0
+   31      W1C    clr_rx_i2s_rdy              1'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t rx_i2s_compare_val: 27;
+        uint32_t reserved_0: 3;
+        uint32_t en_rx_i2s_interrupt: 1;
+        uint32_t clr_rx_i2s_rdy: 1;
+    } b;
+} I2S_RX_CNT_CTRL_TypeDef;
+
+/* 0x60
+   4:0     R      rx_fs_phase_rpt             5'h0
+   31:5    R      rx_i2s_counter              27'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t rx_fs_phase_rpt: 5;
+        const uint32_t rx_i2s_counter: 27;
+    } b;
+} I2S_RX_CNT_VAL_TypeDef;
+
+/* 0x64
+   4:0     R      reserved165                 5'h0
+   31:5    R      tx_data_valid_fs_counter_rpt27'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t reserved_0: 5;
+        const uint32_t tx_data_valid_fs_counter_rpt: 27;
+    } b;
+} I2S_TX_VAL_CNT_TypeDef;
+
+/* 0x68
+   5:0     R      tx_depth_cnt_latch          6'h0
+   7:6     R      dummy169                    2'b0
+   13:8    R      rx_depth_cnt_latch          6'h0
+   31:14   R      dummy167                    18'b0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t tx_depth_cnt_latch: 6;
+        const uint32_t dummy169: 2;
+        const uint32_t rx_depth_cnt_latch: 6;
+        const uint32_t dummy167: 18;
+    } b;
+} I2S_FIFO_CNT_LATCH_TypeDef;
+
+typedef union t_soc_0x220_type
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t r_PON_FEN_AUDIO: 1;            // [0]
+        uint32_t r_PON_FEN_SPORT0: 1;           // [1]
+        uint32_t r_PON_FEN_SPORT1: 1;           // [2]
+        uint32_t rsvd0: 1;                      // [3]
+        uint32_t r_CLK_EN_AUDIO: 1;             // [4]
+        uint32_t r_CLK_EN_SPORT0: 1;            // [5]
+        uint32_t r_CLK_EN_SPORT1: 1;            // [6]
+        uint32_t rsvd1: 1;                      // [7]
+        uint32_t r_CLK_EN_SPORT_40M: 1;         // [8]
+        uint32_t r_CLK_EN_AUDIO_REG: 1;         // [9]
+        uint32_t r_PON_FEN_SPORT2: 1;           // [10]
+        uint32_t rsvd2: 1;                      // [11]
+        uint32_t r_CLK_EN_SPORT2: 1;            // [12]
+        uint32_t rsvd3: 19;                     // [31:13]
+    };
+} T_SOC_0x220_TYPE;
+
+typedef union t_soc_0x224_type
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t r_SPORT0_PLL_CLK_SEL: 3;       // [2:0]
+        uint32_t r_SPORT0_EXT_CODEC: 1;         // [3]
+        uint32_t r_SPORT1_PLL_CLK_SEL: 3;       // [6:4]
+        uint32_t r_CODEC_STANDALONE: 1;         // [7]
+        uint32_t r_PLL_DIV0_SETTING: 8;         // [15:8]
+        uint32_t r_PLL_DIV1_SETTING: 8;         // [23:16]
+        uint32_t r_PLL_DIV2_SETTING: 8;         // [31:24]
+    };
+} T_SOC_0x224_TYPE;
+
+typedef union t_soc_0x228_type
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t rsvd0: 3;                      // [2:0]
+        uint32_t r_SPORT0_MCLK_OUT: 1;          // [3]
+        uint32_t r_SPORT1_MCLK_OUT: 1;          // [4]
+        uint32_t r_SPORT2_MCLK_OUT: 1;          // [5]
+        uint32_t rsvd1: 1;                      // [6]
+        uint32_t r_AUDIO_CLK_FROM_PLL: 1;       // [7]
+        uint32_t r_SPORT1_EXT_CODEC: 1;         // [8]
+        uint32_t rsvd2: 4;                      // [12:9]
+        uint32_t r_SPORT2_PLL_CLK_SEL: 3;       // [15:13]
+        uint32_t rsvd3: 3;                      // [18:16]
+        uint32_t r_SPORT2_EXT_CODEC: 1;         // [19]
+        uint32_t rsvd4: 12;                     // [31:20]
+    };
+} T_SOC_0x228_TYPE;
+
+
+#ifdef  __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* RTL_I2S_DEF_H */
+
diff --git a/bee/drivers/i2s/src/device/rtl87x2j/rtl_i2s.c b/bee/drivers/i2s/src/device/rtl87x2j/rtl_i2s.c
new file mode 100644
index 00000000..8a78fd00
--- /dev/null
+++ b/bee/drivers/i2s/src/device/rtl87x2j/rtl_i2s.c
@@ -0,0 +1,519 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *                        Header Files
+ *============================================================================*/
+#include "rtl_i2s.h"
+#include "rtl_rcc.h"
+
+/*============================================================================*
+ *                           Public Functions
+ *============================================================================*/
+/**
+  * \brief Initializes the I2S peripheral according to the specified
+  *   parameters in the I2S_InitStruct
+  * \param  I2S: selected I2S peripheral.
+  * \param  I2S_InitStruct: pointer to a I2S_InitTypeDef structure that
+  *   contains the configuration information for the specified I2S peripheral
+  * \return None
+  */
+void I2S_Init(I2S_TypeDef *I2Sx, I2S_InitTypeDef *I2S_InitStruct)
+{
+    /* Check the parameters */
+    assert_param(IS_I2S_ALL_PERIPH(I2Sx));
+    assert_param(IS_I2S_DEVICE_MODE(I2S_InitStruct->I2S_DeviceMode));
+    assert_param(IS_I2S_CHANNEL_TYPE(I2S_InitStruct->I2S_ChannelType));
+    assert_param(IS_I2S_DATA_FORMAT(I2S_InitStruct->I2S_DataFormat));
+    assert_param(IS_I2S_DATA_WIDTH(I2S_InitStruct->I2S_DataWidth));
+    assert_param(IS_I2S_MCLK_OUTPUT_TYPE(I2S_InitStruct->I2S_MClockOutput));
+    assert_param(IS_I2S_DMA_CMD(I2S_InitStruct->I2S_DMACmd));
+
+    I2S_CTRL_TypeDef i2s_reg_0x04 = {.d32 = I2Sx->I2S_CTRL};
+    I2S_FIFO_EN_CLK_CON_TypeDef i2s_reg_0x08 = {.d32 = I2Sx->I2S_FIFO_EN_CLK_CON};
+    I2S_TX_FRA_DIV_TypeDef i2s_reg_0x1c = {.d32 = I2Sx->I2S_TX_FRA_DIV};
+    I2S_LRCK_FIFO_TH_CON_TypeDef i2s_reg_0x20 = {.d32 = I2Sx->I2S_LRCK_FIFO_TH_CON};
+    I2S_QACTIVE_CON_TypeDef i2s_reg_0x68 = {.d32 = I2Sx->I2S_QACTIVE_CON};
+
+    /* Reset I2S module */
+    I2Sx->I2S_CTRL |= BIT0;
+    I2Sx->I2S_CTRL &= ~BIT0;
+
+    /* Open I2S qactive function */
+    i2s_reg_0x68.b.sport_func_en = ENABLE;
+    I2Sx->I2S_QACTIVE_CON = i2s_reg_0x68.d32;
+
+    /* I2S Set data format*/
+    i2s_reg_0x04.b.sp_data_format_sel_tx =  I2S_InitStruct->I2S_DataFormat;
+    i2s_reg_0x04.b.sp_en_i2s_mono_tx =  I2S_InitStruct->I2S_ChannelType;
+    i2s_reg_0x04.b.sp_data_len_sel_tx = I2S_InitStruct->I2S_DataWidth;
+
+    /* Configure I2S initialization parameters */
+    i2s_reg_0x04.b.mclk_sel = I2S_InitStruct->I2S_MClockOutput;
+    i2s_reg_0x04.b.slave_data_sel = I2S_InitStruct->I2S_DeviceMode;
+    i2s_reg_0x04.b.sp_sel_i2s_rx_ch = I2S_InitStruct->I2S_RxChannelSequence;
+    i2s_reg_0x04.b.sp_sel_i2s_tx_ch = I2S_InitStruct->I2S_TxChannelSequence;
+    i2s_reg_0x04.b.rx_lsb_first = I2S_InitStruct->I2S_RxBitSequence;
+    i2s_reg_0x04.b.tx_lsb_first = I2S_InitStruct->I2S_TxBitSequence;
+    i2s_reg_0x04.b.dsp_ctl_mode = 0x1; // DSP and SPORT1 handshaking is enabled.
+    /* Disable I2S tx rx */
+    i2s_reg_0x04.b.sp_tx_disable = 1;
+    i2s_reg_0x04.b.sp_rx_disable = 1;
+
+    /* Configure I2S Clock Source parameters */
+    if (I2S_InitStruct->I2S_ClockSource == I2S_CLOCK_SRC_40M)
+    {
+        i2s_reg_0x08.b.mode_40mhz = 0x1;
+        i2s_reg_0x08.b.mode_128fs = 0x0;
+    }
+    else if (I2S_InitStruct->I2S_ClockSource == I2S_CLOCK_SRC_128FS)
+    {
+        i2s_reg_0x08.b.mode_128fs = 0x1;
+        i2s_reg_0x08.b.mode_40mhz = 0x0;
+    }
+    else if (I2S_InitStruct->I2S_ClockSource == I2S_CLOCK_SRC_256FS)
+    {
+        i2s_reg_0x08.b.mode_128fs = 0x0;
+        i2s_reg_0x08.b.mode_40mhz = 0x0;
+    }
+
+    i2s_reg_0x08.b.frame_sync_offset = I2S_FRAME_SYNC_OFFSET_DEFAULT;
+
+    /* Configure DMA burst size */
+    i2s_reg_0x20.b.rxdma_burstsize =  I2S_InitStruct->I2S_RxWaterlevel;
+    i2s_reg_0x20.b.txdma_burstsize =  I2S_InitStruct->I2S_TxWaterlevel;
+
+    /* Configure I2S BCLK */
+    i2s_reg_0x1c.b.tx_mi =  I2S_InitStruct->I2S_BClockMi;
+    i2s_reg_0x1c.b.tx_ni =  I2S_InitStruct->I2S_BClockNi;
+    i2s_reg_0x1c.b.tx_mi_ni_update = 1;
+
+    I2Sx->I2S_CTRL =  i2s_reg_0x04.d32;
+    I2Sx->I2S_FIFO_EN_CLK_CON = i2s_reg_0x08.d32;
+
+    /* Clear error counter */
+    I2Sx->I2S_FIFO_EN_CLK_CON |=  I2S_CLR_RX_ERR_CNT_MSK | I2S_CLR_TX_ERR_CNT_MSK ;
+    I2Sx->I2S_FIFO_EN_CLK_CON &= I2S_CLR_RX_ERR_CNT_CLR & I2S_CLR_TX_ERR_CNT_CLR;
+
+    I2Sx->I2S_TX_FRA_DIV = i2s_reg_0x1c.d32 ;
+    I2Sx->I2S_LRCK_FIFO_TH_CON = i2s_reg_0x20.d32;
+
+}
+
+/**
+  * \brief  Deinitializes the I2S peripheral registers to their default values.
+  * \param  I2S: selected I2S peripheral.
+  * \return None
+  */
+void I2S_DeInit(I2S_TypeDef *I2Sx)
+{
+    I2S_CTRL_TypeDef i2s_reg_0x04 = {.d32 = I2Sx->I2S_CTRL};
+    i2s_reg_0x04.b.sp_reset = 1;
+    I2Sx->I2S_CTRL =    i2s_reg_0x04.d32;
+
+    if (I2Sx == I2S0)
+    {
+        RCC_ClockCmd(I2S_CLOCK, DISABLE);
+    }
+}
+
+/**
+  * \brief  Fills each I2S_InitStruct member with its default value.
+  * \param  I2S_InitStruct: pointer to an I2S_InitTypeDef structure which will be initialized.
+  * \return None
+  */
+void I2S_StructInit(I2S_InitTypeDef *I2S_InitStruct)
+{
+    I2S_InitStruct->I2S_ClockSource      = I2S_CLOCK_SRC_40M;
+    I2S_InitStruct->I2S_BClockMi         = 0x271;/* <!BCLK = 16K */
+    I2S_InitStruct->I2S_BClockNi         = 0x10;
+    I2S_InitStruct->I2S_DeviceMode       = I2S_DEVICE_MODE_MASTER;
+    I2S_InitStruct->I2S_ChannelType      = I2S_CHANNEL_MONO;
+    I2S_InitStruct->I2S_TxChannelSequence     = I2S_CH_SEQ_L_R;
+    I2S_InitStruct->I2S_RxChannelSequence     = I2S_CH_SEQ_L_R;
+    I2S_InitStruct->I2S_DataFormat       = I2S_DATA_FORMAT_I2S;
+    I2S_InitStruct->I2S_TxBitSequence    = I2S_MSB_FIRST;
+    I2S_InitStruct->I2S_RxBitSequence    = I2S_MSB_FIRST;
+    I2S_InitStruct->I2S_DataWidth        = I2S_WIDTH_16BITS ;
+    I2S_InitStruct->I2S_TxWaterlevel     = 16;
+    I2S_InitStruct->I2S_RxWaterlevel     = 16;
+    I2S_InitStruct->I2S_MClockOutput       = I2S_MCLK_128FS;
+}
+
+/**
+  * \brief  Enable or disable the selected I2S mode.
+  * \param  I2S: selected I2S peripheral.
+  * \param  I2S_Mode: selected I2S operation mode.
+  *         This parameter can be the following values:
+  *         \arg I2S_MODE_TX: transmission mode.
+  *         \arg I2S_MODE_RX: receiving mode.
+  * \param  NewState: new state of the operation mode.
+  *   This parameter can be: ENABLE or DISABLE.
+  * \return None
+  */
+void I2S_Cmd(I2S_TypeDef *I2Sx, I2SMode_TypeDef I2S_Mode, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_I2S_ALL_PERIPH(I2Sx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    I2S_CTRL_TypeDef i2s_reg_0x04 = {.d32 = I2Sx->I2S_CTRL};
+
+    if (I2S_Mode == I2S_MODE_TX)
+    {
+        i2s_reg_0x04.b.sp_start_tx = NewState;
+        i2s_reg_0x04.b.sp_tx_disable = !NewState;
+    }
+
+    if (I2S_Mode == I2S_MODE_RX)
+    {
+        i2s_reg_0x04.b.sp_start_rx = NewState;
+        i2s_reg_0x04.b.sp_rx_disable = !NewState;
+    }
+
+    I2Sx->I2S_CTRL = i2s_reg_0x04.d32;
+}
+
+
+/**
+  * \brief  Enable or disable the specified I2S interrupts.
+  * \param  I2S: selected I2S peripheral.
+  * \param  I2S_INT: specifies the I2S interrupts sources to be enable or disable.
+  *         This parameter can be the following values:
+  *         \arg I2S_INT_TX_IDLE: Transmit idle interrupt.
+  *         \arg I2S_INT_RF_EMPTY: Receive FIFO empty interrupt.
+  *         \arg I2S_NT_TF_EMPTY: Transmit FIFO empty interrupt.
+  *         \arg I2S_INT_RF_FULL: Receive FIFO full interrupt.
+  *         \arg I2S_INT_TF_FULL: Transmit FIFO full interrupt.
+  *         \arg I2S_INT_RX_READY: Ready to receive interrupt.
+  *         \arg I2S_INT_TX_READY: Ready to transmit interrupt.
+  * \param  NewState: new state of the specified I2S interrupts.
+  *   This parameter can be: ENABLE or DISABLE.
+  * \return None
+  */
+void I2S_INTConfig(I2S_TypeDef *I2Sx, uint32_t I2S_INT, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_I2S_MCU_INT_CONFIG(I2S_MCU_INT));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    /* Enable Interrupt */
+    I2S_CTRL_TypeDef i2s_reg_0x04 = {.d32 = I2Sx->I2S_CTRL};
+    i2s_reg_0x04.b.dsp_ctl_mode = 1;
+    I2Sx->I2S_CTRL = i2s_reg_0x04.d32;
+
+    if (NewState == ENABLE)
+    {
+
+        I2Sx->I2S_FIFO_EN_CLK_CON |= I2S_INT << 24;
+    }
+    else
+    {
+        I2Sx->I2S_FIFO_EN_CLK_CON &= ~(I2S_INT << 24);
+    }
+}
+
+
+/**
+  * \brief  Get the specified I2S flag status.
+  * \param  I2S: selected I2S peripheral.
+  * \param  I2S_INT: the specified I2S interrupt.
+  *         This parameter can be one of the following values:
+  *         \arg I2S_INT_TX_IDLE: Transmit idle interrupt.
+  *         \arg I2S_INT_RF_EMPTY: Receive FIFO empty interrupt.
+  *         \arg I2S_INT_TF_EMPTY: Transmit FIFO empty interrupt.
+  *         \arg I2S_INT_RF_FULL: Receive FIFO full interrupt.
+  *         \arg I2S_INT_TF_FULL: Transmit FIFO full interrupt.
+  *         \arg I2S_INT_RX_READY: Ready to receive interrupt.
+  *         \arg I2S_INT_TX_READY: Ready to transmit interrupt.
+  * \return The new state of LCD_FLAG (SET or RESET).
+  */
+ITStatus I2S_GetINTStatus(I2S_TypeDef *I2Sx, uint32_t I2S_INT)
+{
+    ITStatus bit_status = RESET;
+
+    /* Check the parameters */
+    assert_param(IS_I2S_INT_CONFIG(I2S_INT));
+
+    if ((I2Sx->I2S_FIFO_STA & (I2S_INT & 0x7F)))
+    {
+        bit_status = SET;
+    }
+
+    /* Return the I2S_INT status */
+    return  bit_status;
+}
+
+
+/**
+  * \brief  Clears the I2S interrupt pending bits.
+  * \param  I2S: selected I2S peripheral.
+  * \param  I2S_CLEAR_INT: specifies the interrupt pending bit to clear.
+  *         This parameter can be any combination of the following values:
+  *         \arg I2S_CLEAR_INT_RX_READY: Clear ready to receive interrupt.
+  *         \arg I2S_CLEAR_INT_TX_READY: Clear ready to transmit interrupt.
+  * \return None
+  */
+void I2S_ClearINTPendingBit(I2S_TypeDef *I2Sx, uint32_t I2S_CLEAR_INT)
+{
+    /* Check the parameters */
+    assert_param(IS_I2S_INT_CONFIG(I2S_CLEAR_INT));
+    I2Sx->I2S_INTR_CON |= I2S_CLEAR_INT;
+    I2Sx->I2S_INTR_CON &= I2S_CLEAR_INT;
+}
+
+/**
+ * \brief   I2S communication selection which can be from intrnal codec or external codec.
+ * \param   NewState: new state of I2S0 communication selection.
+ *          This parameter can be: ENABLE or DISABLE.
+ * \return  None.
+ */
+void I2S_WithExtCodecCmd(I2S_TypeDef *I2Sx, FunctionalState NewState)
+{
+    if (NewState == 0x1)
+    {
+        SPORT_EXT_CODEC_REG |= BIT27;
+    }
+    else
+    {
+        SPORT_EXT_CODEC_REG &= ~BIT27;
+    }
+}
+
+/**
+ * \brief   Transmits a data through the SPIx/I2Sx peripheral.
+ * \param[in] I2Sx: To select the I2Sx peripheral, x can be 0 or 1.
+ * \param[in] Data: Data to be transmitted.
+ * \return None.
+ */
+void I2S_SendData(I2S_TypeDef *I2Sx, uint32_t Data)
+{
+    /* Check the parameters */
+    assert_param(IS_I2S_ALL_PERIPH(I2Sx));
+    I2Sx->I2S_TX_FIFO_WR_ADDR = Data;
+}
+
+
+/**
+ * \brief  Received data by the I2Sx peripheral.
+ * \param[in] I2Sx: To select I2Sx peripheral, where x can be: 0 or 1.
+ * \return Return the most recent received data.
+ */
+uint32_t I2S_ReceiveFIFOData(I2S_TypeDef *I2Sx)
+{
+    /* Check the parameters */
+    assert_param(IS_I2S_ALL_PERIPH(I2Sx));
+
+    return  I2Sx->I2S_RX_FIFO_RD_ADDR;
+
+}
+
+/**
+ * \brief   Get transmit FIFO free length by the I2Sx peripheral.
+ * \param[in] I2Sx: To select I2Sx peripheral, where x can be: 0 or 1.
+ * \retval  Return the transmit FIFO free length.
+ */
+uint8_t I2S_GetTxFIFOFreeLen(I2S_TypeDef *I2Sx)
+{
+    /* Check the parameters */
+    assert_param(IS_I2S_ALL_PERIPH(I2Sx));
+
+    return I2Sx->I2S_FIFO_CNT_STA & 0x3F ;
+}
+
+/**
+ * \brief   Get receive FIFO data length by the I2Sx peripheral.
+ * \param[in] I2Sx: To select I2Sx peripheral, where x can be: 0 or 1.
+ * \return  The data length of the receive FIFO.
+ */
+uint8_t I2S_GetRxFIFOLen(I2S_TypeDef *I2Sx)
+{
+    /* Check the parameters */
+    assert_param(IS_I2S_ALL_PERIPH(I2Sx));
+
+    return ((I2Sx->I2S_FIFO_CNT_STA & 0x3F00) >> I2S_RX_FIFO_DEPTH_CNT_0_POS);
+}
+
+/**
+ * \brief   Get the send error counter value by the I2Sx peripheral.
+ * \param[in]  I2Sx: To select I2Sx peripheral, where x can be: 0 or 1.
+ * \return  The send error counter value .
+ */
+uint8_t I2S_GetTxErrCnt(I2S_TypeDef *I2Sx)
+{
+    /* Check the parameters */
+    assert_param(IS_I2S_ALL_PERIPH(I2Sx));
+
+    return I2Sx->I2S_TX_RX_ERR_STA & 0xFF;
+}
+
+/**
+ * \brief  Get the reception error counter value by the I2Sx peripheral.
+ * \param[in] I2Sx: To select I2Sx peripheral, where x can be: 0 or 1.
+ * \retval  The reception error counter value .
+ */
+uint8_t I2S_GetRxErrCnt(I2S_TypeDef *I2Sx)
+{
+    /* Check the parameters */
+    assert_param(IS_I2S_ALL_PERIPH(I2Sx));
+
+    return ((I2Sx->I2S_TX_RX_ERR_STA & 0xFFFF) >> I2S_RX_ERR_CNT_POS);
+}
+
+/**
+ * \brief   Swap audio data bytes sequence which sent by the I2Sx peripheral.
+ * \param[in] I2Sx: To select I2Sx peripheral, where x can be: 0 or 1.
+ * \param[in] NewState: New state of the bytes sequence.
+ *      This parameter can be: ENABLE or DISABLE.
+ * \return None.
+ */
+void I2S_SwapBytesForSend(I2S_TypeDef *I2Sx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_I2S_ALL_PERIPH(I2Sx));
+    I2S_FIFO_EN_CLK_CON_TypeDef i2s_reg_0x08 = {.d32 = I2Sx->I2S_FIFO_EN_CLK_CON};
+    i2s_reg_0x08.b.tx_src_byte_swap = NewState;
+    I2Sx->I2S_FIFO_EN_CLK_CON =  i2s_reg_0x08.d32;
+}
+
+/**
+ * \brief   Swap audio data bytes sequence which read by the I2Sx peripheral.
+ * \param[in] I2Sx: To select I2Sx peripheral, where x can be: 0 or 1.
+ * \param[in] NewState: New state of the bytes sequence.
+ *      This parameter can be: ENABLE or DISABLE.
+ * \return  None.
+ */
+void I2S_SwapBytesForRead(I2S_TypeDef *I2Sx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_I2S_ALL_PERIPH(I2Sx));
+
+    I2S_FIFO_EN_CLK_CON_TypeDef i2s_reg_0x08 = {.d32 = I2Sx->I2S_FIFO_EN_CLK_CON};
+    i2s_reg_0x08.b.rx_snk_byte_swap = NewState;
+    I2Sx->I2S_FIFO_EN_CLK_CON =  i2s_reg_0x08.d32;
+}
+
+/**
+ * \brief  Swap audio channel data which sent by the I2Sx peripheral..
+ * \param[in] I2Sx: To select I2Sx peripheral, where x can be: 0 or 1.
+ * \param[in] NewState: New state of the left and right channel data sequence.
+ *      This parameter can be: ENABLE or DISABLE.
+ * \return  None.
+ */
+void I2S_SwapLRChDataForSend(I2S_TypeDef *I2Sx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_I2S_ALL_PERIPH(I2Sx));
+
+    I2S_FIFO_EN_CLK_CON_TypeDef i2s_reg_0x08 = {.d32 = I2Sx->I2S_FIFO_EN_CLK_CON};
+    i2s_reg_0x08.b.tx_src_lr_swap = NewState;
+    I2Sx->I2S_FIFO_EN_CLK_CON =  i2s_reg_0x08.d32;
+}
+
+/**
+ * \brief   Swap audio channel data which read by the I2Sx peripheral.
+ * \param[in] I2Sx: To select I2Sx peripheral, where x can be: 0 or 1.
+ * \param[in] NewState: New state of the left and right channel data sequence.
+ *      This parameter can be: ENABLE or DISABLE.
+ * \return None.
+ */
+void I2S_SwapLRChDataForRead(I2S_TypeDef *I2Sx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_I2S_ALL_PERIPH(I2Sx));
+
+    I2S_FIFO_EN_CLK_CON_TypeDef i2s_reg_0x08 = {.d32 = I2Sx->I2S_FIFO_EN_CLK_CON};
+    i2s_reg_0x08.b.rx_snk_lr_swap = NewState;
+    I2Sx->I2S_FIFO_EN_CLK_CON =  i2s_reg_0x08.d32;
+}
+
+/**
+ * \brief   MCLK output selection which can be from I2S0 or I2S1.
+ * \param[in] I2Sx: To select I2Sx peripheral, where x can be: 0 or 1.
+ * \param[in] NewState: New state of MCLK output.
+ *      This parameter can be: ENABLE or DISABLE.
+ * \return  None.
+ */
+void I2S_MCLKOutputSelectCmd(I2S_TypeDef *I2Sx)
+{
+    /* Check the parameters */
+    assert_param(IS_I2S_ALL_PERIPH(I2Sx));
+
+    if (I2Sx == I2S0)
+    {
+//        /*Enable mclk mux */
+//        PERIBLKCTRL_AUDIO->u_708.BITS_708.r_SPORT0_MCLK_OUT = 0x1;
+//        PERIBLKCTRL_AUDIO->u_70C.BITS_70C.mclk2_pmux_sel = 0x1;
+    }
+}
+
+
+/**
+ * \brief   Config BClk clock.
+ * \param[in] I2Sx: To select I2Sx peripheral, where x can be: 0 or 1.
+ * \param[in] I2S_BClockMi: Mi parameter.
+ * \param[in] I2S_BClockNi: Ni parameter.
+ * \return  Execution status.
+ * \retval  SET: Success.
+ * \retval  RESET: Failure.
+ */
+void I2S_UpdateBClk(I2S_TypeDef *I2Sx, uint32_t dir, uint16_t I2S_BClockMi,
+                    uint16_t I2S_BClockNi)
+{
+    /* Check the parameters */
+    assert_param(IS_I2S_ALL_PERIPH(I2Sx));
+    I2S_TX_FRA_DIV_TypeDef i2s_reg_0x1c = {.d32 = I2Sx->I2S_TX_FRA_DIV};
+
+    /* Configure I2S BCLK */
+    i2s_reg_0x1c.b.tx_mi =  I2S_BClockMi;
+    i2s_reg_0x1c.b.tx_ni =  I2S_BClockNi;
+    i2s_reg_0x1c.b.tx_mi_ni_update = 1;
+
+    I2Sx->I2S_TX_FRA_DIV =  i2s_reg_0x1c.d32;
+    return;
+}
+
+/**
+ * \brief   Get BClk clock status.
+ * \param[in] I2Sx: To select I2Sx peripheral, where x can be: 0 or 1.
+ * \return  Execution status.
+ * \retval  SET: BLCK is updating.
+ * \retval  RESET: BLCK update is done.
+ */
+FlagStatus I2S_GetBClkStatus(I2S_TypeDef *I2Sx)
+{
+    /* Check the parameters */
+    assert_param(IS_I2S_ALL_PERIPH(I2Sx));
+
+    if (I2Sx->I2S_TX_FRA_DIV & I2S_MI_NI_UPDATE_MSK)
+    {
+        return SET;
+    }
+
+    return RESET;
+}
+
+#if (I2S_SUPPORT_AUTO_CLOCK == 1)
+void I2S_ClockAutoModeCmd(I2S_TypeDef *I2Sx, FunctionalState Newstate)
+{
+    /* Check the parameters */
+    assert_param(IS_I2S_ALL_PERIPH(I2Sx));
+
+    if (Newstate == ENABLE)
+    {
+        I2Sx->I2S_QACTIVE_CON = I2S_CLOCK_AUTO_MODE_CONFIG_AUTOMATIC;
+    }
+    else
+    {
+        I2Sx->I2S_QACTIVE_CON = I2S_CLOCK_AUTO_MODE_CONFIG_ALWAYSRUN;
+    }
+
+    return;
+}
+#endif
+
+
+
diff --git a/bee/drivers/i2s/src/device/rtl87x2j/rtl_i2s_def.h b/bee/drivers/i2s/src/device/rtl87x2j/rtl_i2s_def.h
new file mode 100644
index 00000000..520b37a8
--- /dev/null
+++ b/bee/drivers/i2s/src/device/rtl87x2j/rtl_i2s_def.h
@@ -0,0 +1,396 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef RTL_I2S_DEF_H
+#define RTL_I2S_DEF_H
+
+#include "utils/rtl_utils.h"
+#include "address_map.h"
+
+#ifdef  __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+
+/*============================================================================*
+ *                          I2S Defines
+ *============================================================================*/
+/** \defgroup I2S         I2S
+  * \brief
+  * \{
+  */
+
+/** \defgroup I2S_Exported_Constants I2S Exported Constants
+  * \brief
+  * \{
+  */
+
+/**
+ * \defgroup I2S_Defines I2S Defines
+ * \{
+ * \ingroup  I2S_Exported_Constants
+ */
+#define CHIP_I2S_CHANNEL_NUM                (1)
+
+#define I2S_SUPPORT_TRX_INDEPENDENT_CONTROL (0)
+#define I2S_SUPPORT_TRX_FIFO                (0)
+#define I2S_SUPPORT_INT_TX_VALID            (0)
+#define I2S_SUPPORT_PLL_CLK                 (0)
+#define I2S_SUPPORT_DATE_WIDTH_32BIT        (0)
+#define I2S_SUPPORT_MCLK_OUTPUT             (1)
+#define I2S_SUPPORT_AUTO_CLOCK              (1)
+/** End of I2S_Defines
+  * \}
+  */
+
+/** End of I2S_Exported_Constants
+  * \}
+  */
+
+/** End of I2S
+  * \}
+  */
+/*============================================================================*
+ *                          APB_I2S Registers Memory Map
+ *============================================================================*/
+typedef struct
+{
+    __IO uint32_t I2S_TX_FIFO_WR_ADDR;          /*!< 0x00 */
+    __IO uint32_t I2S_CTRL;                     /*!< 0x04 */
+    __IO uint32_t I2S_FIFO_EN_CLK_CON;          /*!< 0x08 */
+    __IO uint32_t I2S_INTR_CON;                 /*!< 0x0C */
+    __IO uint32_t I2S_RX_FIFO_RD_ADDR;          /*!< 0x10 */
+    __IO uint32_t I2S_FIFO_CNT_STA;             /*!< 0x14 */
+    __IO uint32_t I2S_TX_RX_ERR_STA;            /*!< 0x18 */
+    __IO uint32_t I2S_TX_FRA_DIV;               /*!< 0x1C */
+    __IO uint32_t I2S_LRCK_FIFO_TH_CON;         /*!< 0x20 */
+    __IO uint32_t I2S_FIFO_STA;                 /*!< 0x24 */
+    __I  uint32_t I2S_RESV[16];                 /*!< 0x28-0X64 */
+    __IO uint32_t I2S_QACTIVE_CON;              /*!< 0x68 */
+
+} I2S_TypeDef;
+
+/*============================================================================*
+ *                          I2S Declaration
+ *============================================================================*/
+#define I2S0                ((I2S_TypeDef *) I2S0_BASE)
+#define SPORT_EXT_CODEC_REG    (*(volatile uint32_t *)0x40000240)
+
+#define IS_I2S_PERIPH(PERIPH)     (((PERIPH) == I2S0))
+/*============================================================================*
+ *                         I2S Private Types
+ *============================================================================*/
+//#define PERIPH_REG_BASE     0x40002000UL
+
+#define I2S_CLOCK_AUTO_MODE_CONFIG_AUTOMATIC       0x00
+#define I2S_CLOCK_AUTO_MODE_CONFIG_ALWAYSRUN       0x8000000FUL
+
+/**
+ * \defgroup    I2S_Clock_Source I2S Clock Source
+ * \{
+ * \ingroup     I2S_Exported_Constants
+ */
+typedef enum
+{
+    I2S_CLOCK_SRC_40M,
+    I2S_CLOCK_SRC_128FS,
+    I2S_CLOCK_SRC_256FS,
+} I2SClockSrc_TypeDef;
+
+#define IS_I2S_CLOCK_SRC(CLOCK) (((CLOCK) == I2S_CLOCK_SRC_40M) || \
+                                 ((CLOCK) == I2S_CLOCK_SRC_128FS) || \
+                                 ((CLOCK) == I2S_CLOCK_SRC_256FS))
+
+/** End of I2S_Clock_Source
+  * \}
+  */
+
+
+/**
+ * \defgroup    I2S_All_Periph   I2S All Periph
+ * \{
+ * \ingroup     I2S_Exported_Constants
+ */
+#define IS_I2S_ALL_PERIPH(PERIPH) ((PERIPH) == I2S0)
+
+/** End of I2S_All_Periph
+  * \}
+  */
+
+/*============================================================================*
+ *                         I2S Registers and Field Descriptions
+ *============================================================================*/
+/* 0x00
+   31:0    W      TX_FIFO_WR_ADDR             32'b0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t TX_FIFO_WR_ADDR: 32;
+    } b;
+} I2S_TX_FIFO_WR_ADDR_TypeDef;
+
+/* 0x04
+   0       R/W    sp_reset                    1'b0
+   1       R/W    tx_inv_i2s_sclk             1'b0
+   2       R/W    rx_inv_i2s_sclk             1'b0
+   3       R/W    slave_clk_sel               1'b0
+   4       R/W    slave_data_sel              1'b0
+   5       R/W    sp_wclk_tx_inverse          1'h0
+   6       R/W    sp_loopback                 1'b0
+   7       R/W    dsp_ctl_mode                1'b0
+   9:8     R/W    sp_data_format_sel_tx       2'b00
+   10      R/W    reserved0                   1'b0
+   11      R/W    sp_en_i2s_mono_tx           1'b0
+   13:12   R/W    sp_data_len_sel_tx          2'b00
+   14      R/W    sp_inv_i2s_sclk             1'b0
+   15      R/W    sp_i2s_self_lpbk_en         1'b0
+   16      R/W    sp_tx_disable               1'b1
+   17      R/W    sp_start_tx                 1'b0
+   19:18   R/W    reserved1                   2'b00
+   21:20   R/W    sp_sel_i2s_tx_ch            2'b00
+   22      R/W    tx_lsb_first                1'b0
+   23      R/W    rx_lsb_first                1'b0
+   24      R/W    sp_rx_disable               1'b1
+   25      R/W    sp_start_rx                 1'b0
+   27:26   R/W    reserved2                   2'b00
+   29:28   R/W    sp_sel_i2s_rx_ch            2'b00
+   30      R/W    mclk_sel                    1'b0
+   31      R/W    long_frame_sync             1'b1
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t sp_reset: 1;
+        uint32_t tx_inv_i2s_sclk: 1;
+        uint32_t rx_inv_i2s_sclk: 1;
+        uint32_t slave_clk_sel: 1;
+        uint32_t slave_data_sel: 1;
+        uint32_t sp_wclk_tx_inverse: 1;
+        uint32_t sp_loopback: 1;
+        uint32_t dsp_ctl_mode: 1;
+        uint32_t sp_data_format_sel_tx: 2;
+        uint32_t reserved0: 1;
+        uint32_t sp_en_i2s_mono_tx: 1;
+        uint32_t sp_data_len_sel_tx: 2;
+        uint32_t sp_inv_i2s_sclk: 1;
+        uint32_t sp_i2s_self_lpbk_en: 1;
+        uint32_t sp_tx_disable: 1;
+        uint32_t sp_start_tx: 1;
+        uint32_t reserved_1: 2;
+        uint32_t sp_sel_i2s_tx_ch: 2;
+        uint32_t tx_lsb_first: 1;
+        uint32_t rx_lsb_first: 1;
+        uint32_t sp_rx_disable: 1;
+        uint32_t sp_start_rx: 1;
+        uint32_t reserved2: 2;
+        uint32_t sp_sel_i2s_rx_ch: 2;
+        uint32_t mclk_sel: 1;
+        uint32_t long_frame_sync: 1;
+    } b;
+} I2S_CTRL_TypeDef;
+
+/* 0x08
+   7:0     R/W    frame_sync_offset           8'h0
+   10:8    R/W    debug_bus_sel               3'h0
+   11      R/W    reserved0                   1'b0
+   12      R/W    clear_tx_err_cnt            1'b0
+   13      R/W    clear_rx_err_cnt            1'b0
+   15:14   R/W    i2s_clk_sel                 2'h0
+   16      R/W    mode_40mhz                  1'b0
+   17      R/W    mode_128fs                  1'h0
+   19:18   R/W    reserved1                   2'b0
+   20      R/W    tx_src_byte_swap            1'b0
+   21      R/W    tx_src_lr_swap              1'b0
+   22      R/W    rx_snk_byte_swap            1'b0
+   23      R/W    rx_snk_lr_swap              1'b0
+   29:24   R/W    int_enable                  6'b0
+   31:30   R/W    reserved2                   2'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t frame_sync_offset: 8;
+        uint32_t debug_bus_sel: 3;
+        uint32_t reserved0: 1;
+        uint32_t clear_tx_err_cnt: 1;
+        uint32_t clear_rx_err_cnt: 1;
+        uint32_t i2s_clk_sel: 2;
+        uint32_t mode_40mhz: 1;
+        uint32_t mode_128fs: 1;
+        uint32_t reserved_1: 2;
+        uint32_t tx_src_byte_swap: 1;
+        uint32_t tx_src_lr_swap: 1;
+        uint32_t rx_snk_byte_swap: 1;
+        uint32_t rx_snk_lr_swap: 1;
+        uint32_t int_enable: 6;
+        uint32_t reserved_2: 2;
+    } b;
+} I2S_FIFO_EN_CLK_CON_TypeDef;
+
+/* 0x0C
+   0       R/W    tx_dsp_clear_int_0          1'b0
+   1       R/W    rx_dsp_clear_int_0          1'b0
+   17:2    R/W    reserved_0                  16'h0
+   18      R/W    tx_dma_single_low           1'b0
+   19      R/W    tx_dma_single_low           1'b0
+   31:20   R/W    reserved_1                  12'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t tx_dsp_clear_int_0: 1;
+        uint32_t rx_dsp_clear_int_0: 1;
+        uint32_t reserved_0: 16;
+        uint32_t tx_dma_single_low: 1;
+        uint32_t rx_dma_single_low: 1;
+        uint32_t reserved_1: 12;
+    } b;
+} I2S_INTR_CON_TypeDef;
+
+/* 0x10
+   31:0    R      RX_FIFO_RD_ADDR             32'b0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t RX_FIFO_RD_ADDR: 32;
+    } b;
+} I2S_RX_FIFO_RD_ADDR_TypeDef;
+
+/* 0x14
+   5:0     R      tx_depth_cnt_0              6'h20
+   7:6     R      dummy67                     2'b00
+   13:8    R      rx_depth_cnt_0              6'h0
+   30:14   R      dummy65                     17'h0
+   31      R      dummy64                     1'b0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t tx_depth_cnt_0: 6;
+        const uint32_t dummy67: 2;
+        const uint32_t rx_depth_cnt_0: 6;
+        const uint32_t dummy65: 17;
+        const uint32_t dummy64: 1;
+    } b;
+} I2S_FIFO_CNT_STA_TypeDef;
+
+/* 0x18
+   15:0    R      tx_err_cnt                  16'h0
+   31:16   R      rx_err_cnt                  16'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t tx_err_cnt: 16;
+        const uint32_t rx_err_cnt: 16;
+    } b;
+} I2S_TX_RX_ERR_STA_TypeDef;
+
+/* 0x1C
+   15:0    R/W    tx_mi                       16'h625
+   30:16   R/W    tx_ni                       15'h48
+   31      R/W    tx_mi_ni_update             1'b0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t tx_mi: 16;
+        uint32_t tx_ni: 15;
+        uint32_t tx_mi_ni_update: 1;
+    } b;
+} I2S_TX_FRA_DIV_TypeDef;
+
+/* 0x20
+   5:0     R/W    txdma_burstsize             6'h10
+   7:6     R/W    reserved81                  2'h0
+   13:8    R/W    rxdma_burstsize             6'h10
+   31:14   R/W    reserved79                  18'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t txdma_burstsize: 6;
+        uint32_t reserved_1: 2;
+        uint32_t rxdma_burstsize: 6;
+        uint32_t reserved_0: 18;
+    } b;
+} I2S_LRCK_FIFO_TH_CON_TypeDef;
+
+/* 0x24
+   0       R      sp_ready_to_tx              1'b0
+   1       R      sp_ready_to_rx              1'b0
+   2       R      tx_fifo_full_intr           1'b0
+   3       R      rx_fifo_full_intr           1'b0
+   4       R      tx_fifo_empty_intr          1'b0
+   5       R      rx_fifo_empty_intr          1'b0
+   6       R      tx_i2s_idle                 1'b0
+   31:7    R      reserved_0                  25'b0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t sp_ready_to_tx: 1;
+        const uint32_t sp_ready_to_rx: 1;
+        const uint32_t tx_fifo_full_intr: 1;
+        const uint32_t rx_fifo_full_intr: 1;
+        const uint32_t tx_fifo_empty_intr: 1;
+        const uint32_t rx_fifo_empty_intr: 1;
+        const uint32_t tx_i2s_idle: 1;
+        const uint32_t reserved_0: 25;
+    } b;
+} I2S_FIFO_STA_TypeDef;
+
+/* 0x68
+   0       R/W    sclk_qactive_man_data       0x0
+   1       R/W    sclk_qactive_man_enable     0x0
+   2       R/W    pclk_qactive_man_data       0x0
+   3       R/W    pclk_qactive_man_enable     0x0
+   30:4    R      reserved_0                  0x0
+   31      R/W    sport_func_en               0x0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t sclk_qactive_man_data: 1;
+        uint32_t sclk_qactive_man_enable: 1;
+        uint32_t pclk_qactive_man_data: 1;
+        uint32_t pclk_qactive_man_enable: 1;
+        uint32_t reserved_0: 27;
+        uint32_t sport_func_en: 1;
+    } b;
+} I2S_QACTIVE_CON_TypeDef;
+
+
+#ifdef  __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* RTL_I2S_DEF_H */
+
diff --git a/bee/drivers/ir/CMakeLists.txt b/bee/drivers/ir/CMakeLists.txt
new file mode 100644
index 00000000..e2eef27b
--- /dev/null
+++ b/bee/drivers/ir/CMakeLists.txt
@@ -0,0 +1,8 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+if(CONFIG_REALTEK_BEE_COMMON_DRIVER)
+    zephyr_include_directories(inc)
+endif()
+
+add_subdirectory_ifdef(CONFIG_REALTEK_BEE_IR src)
diff --git a/bee/drivers/ir/Kconfig b/bee/drivers/ir/Kconfig
new file mode 100644
index 00000000..8f7e2cbe
--- /dev/null
+++ b/bee/drivers/ir/Kconfig
@@ -0,0 +1,8 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config REALTEK_BEE_IR
+	bool "Realtek Bee IR driver"
+	default n
+	help
+	  This option enables the IR driver for Realtek Bee.
diff --git a/bee/drivers/ir/inc/rtl_ir.h b/bee/drivers/ir/inc/rtl_ir.h
new file mode 100644
index 00000000..33c01734
--- /dev/null
+++ b/bee/drivers/ir/inc/rtl_ir.h
@@ -0,0 +1,1163 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *                        Define to prevent recursive inclusion
+ *============================================================================*/
+#ifndef RTL_IR_H
+#define RTL_IR_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*============================================================================*
+ *                        Header Files
+ *============================================================================*/
+#include "utils/rtl_utils.h"
+#if defined (CONFIG_SOC_SERIES_RTL87X2G)
+#include "ir/src/device/rtl87x2g/rtl_ir_def.h"
+#elif defined (CONFIG_SOC_SERIES_RTL87X3E)
+#include "ir/src/device/rtl87x3e/rtl_ir_def.h"
+#elif defined (CONFIG_SOC_SERIES_RTL87X3D)
+#include "ir/src/device/rtl87x3d/rtl_ir_def.h"
+#elif defined (CONFIG_SOC_SERIES_RTL87X2J)
+#include "ir/src/device/rtl87x2j/rtl_ir_def.h"
+#elif defined (CONFIG_SOC_SERIES_RTL87X3J)
+#include "ir/src/device/rtl87x3j/rtl_ir_def.h"
+#endif
+
+/** \defgroup IR          IR
+  * \brief
+  * \{
+  */
+
+/*============================================================================*
+ *                        Constants
+ *============================================================================*/
+/** \defgroup IR_Exported_Constants IR Exported Constants
+  * \brief
+  * \{
+  */
+
+/**
+ * \defgroup    IR_FIFO_SIZE IR FIFO SIZE
+ * \{
+ * \ingroup     IR_Exported_Constants
+ */
+#define IR_TX_FIFO_SIZE                   32
+#define IR_RX_FIFO_SIZE                   32
+
+/** End of IR_FIFO_SIZE
+  * \}
+  */
+
+/**
+ * \defgroup    IR_Mode IR Mode
+ * \{
+ * \ingroup     IR_Exported_Constants
+ */
+typedef enum
+{
+    IR_MODE_TX = 0x00,
+    IR_MODE_RX = 0x01,
+} IRMode_TypeDef;
+
+#define IS_IR_MODE(MODE) (((MODE) == IR_MODE_TX) || ((MODE) == IR_MODE_RX))
+
+/** End of IR_Mode
+  * \}
+  */
+
+/**
+ * \defgroup    IR_Idle_Status IR Idle Status
+ * \{
+ * \ingroup     IR_Exported_Constants
+ */
+typedef enum
+{
+    IR_IDLE_OUTPUT_LOW = 0x00,
+    IR_IDLE_OUTPUT_HIGH = 0x01,
+} IRIdleStatus_TypeDef;
+
+#define IS_IR_IDLE_STATUS(LEVEL) (((LEVEL) == IR_IDLE_OUTPUT_HIGH) || ((LEVEL) == IR_IDLE_OUTPUT_LOW))
+
+/** End of IR_Idle_Status
+  * \}
+  */
+
+/**
+ * \defgroup    IR_TX_Data IR TX Data
+ * \{
+ * \ingroup     IR_Exported_Constants
+ */
+typedef enum
+{
+    IR_TX_DATA_NORMAL = 0x00,
+    IR_TX_DATA_INVERSE = 0x01,
+} IRTxData_TypeDef;
+
+#define IS_IR_TX_DATA(TYPE) (((TYPE) == IR_TX_DATA_NORMAL) || ((TYPE) == IR_TX_DATA_INVERSE))
+
+/** End of IR_TX_Data
+  * \}
+  */
+
+/**
+ * \defgroup    IR_Threshold IR Threshold
+ * \{
+ * \ingroup     IR_Exported_Constants
+ */
+#define IS_IR_TX_THRESHOLD(THD)  ((THD) <= IR_TX_FIFO_SIZE)
+#define IS_IR_RX_THRESHOLD(THD) ((THD) <= IR_RX_FIFO_SIZE)
+
+/** End of IR_Threshold
+  * \}
+  */
+
+/**
+ * \defgroup    RX_Start_Mode RX Start Mode
+ * \{
+ * \ingroup     IR_Exported_Constants
+ */
+typedef enum
+{
+    IR_RX_MANUAL_MODE = 0x00,
+    IR_RX_AUTO_MODE = 0x01,
+} IRRxStartMode_TypeDef;
+
+#define IS_RX_START_MODE(MODE) (((MODE) == IR_RX_AUTO_MODE) || ((MODE) == IR_RX_MANUAL_MODE))
+
+/** End of RX_Start_Mode
+  * \}
+  */
+
+/**
+ * \defgroup    IR_RX_FIFO_Discard_Setting IR RX FIFO Discard Setting
+ * \{
+ * \ingroup     IR_Exported_Constants
+ */
+typedef enum
+{
+    IR_RX_FIFO_FULL_DISCARD_NEWEST = 0x00,
+    IR_RX_FIFO_FULL_DISCARD_OLDEST = 0x01,
+} IRRxFIFODiscard_TypeDef;
+
+#define IS_IR_RX_FIFO_FULL_DISCARD(CTRL)  (((CTRL) == IR_RX_FIFO_FULL_DISCARD_NEWEST) || ((CTRL) == IR_RX_FIFO_FULL_DISCARD_OLDEST))
+
+/** End of IR_RX_FIFO_Discard_Setting
+  * \}
+  */
+
+/**
+ * \defgroup    RX_Trigger_Mode RX Trigger Mode
+ * \{
+ * \ingroup     IR_Exported_Constants
+ */
+typedef enum
+{
+    IR_RX_FALL_EDGE = 0x00,
+    IR_RX_RISING_EDGE = 0x01,
+    IR_RX_DOUBLE_EDGE = 0x02,
+} IRRxTriggerMode_TypeDef;
+
+#define IS_RX_RX_TRIGGER_EDGE(EDGE) (((EDGE) == IR_RX_FALL_EDGE) || ((EDGE) == IR_RX_RISING_EDGE) || ((EDGE) == IR_RX_DOUBLE_EDGE))
+
+/** End of RX_Trigger_Mode
+  * \}
+  */
+
+/**
+ * \defgroup    RX_Filter_Time RX Filter Time
+ * \{
+ * \ingroup     IR_Exported_Constants
+ */
+typedef enum
+{
+    IR_RX_FILTER_TIME_50NS  = 0x00,
+    IR_RX_FILTER_TIME_75NS  = 0x01,
+    IR_RX_FILTER_TIME_100NS = 0x02,
+    IR_RX_FILTER_TIME_125NS = 0x03,
+    IR_RX_FILTER_TIME_150NS = 0x04,
+    IR_RX_FILTER_TIME_175NS = 0x05,
+    IR_RX_FILTER_TIME_200NS = 0x06,
+    IR_RX_FILTER_TIME_225NS = 0x07,
+} IRRxFilterTime_TypeDef;
+
+#define IS_IR_RX_FILTER_TIME_CTRL(CTRL)  (((CTRL) == IR_RX_FILTER_TIME_50NS) || \
+                                          ((CTRL) == IR_RX_FILTER_TIME_75NS) || \
+                                          ((CTRL) == IR_RX_FILTER_TIME_100NS) || \
+                                          ((CTRL) == IR_RX_FILTER_TIME_125NS) || \
+                                          ((CTRL) == IR_RX_FILTER_TIME_150NS) || \
+                                          ((CTRL) == IR_RX_FILTER_TIME_175NS) || \
+                                          ((CTRL) == IR_RX_FILTER_TIME_200NS) || \
+                                          ((CTRL) == IR_RX_FILTER_TIME_225NS))
+
+/** End of RX_Filter_Time
+  * \}
+  */
+
+/**
+ * \defgroup    IR_RX_Count_Polarity IR RX Count Polarity
+ * \{
+ * \ingroup     IR_Exported_Constants
+ */
+typedef enum
+{
+    IR_RX_COUNT_LOW_LEVEL  = 0x00,
+    IR_RX_COUNT_HIGH_LEVEL  = 0x01,
+} IRRxCountPol_TypeDef;
+
+#define IS_IR_RX_COUNT_POLARITY(CTRL)  (((CTRL) == IR_RX_COUNT_LOW_LEVEL) || ((CTRL) == IR_RX_COUNT_HIGH_LEVEL))
+
+/** End of IR_RX_Count_Polarity
+  * \}
+  */
+
+/**
+ * \defgroup    IR_Compensation_Flag IR Compensation Flag
+ * \{
+ * \ingroup     IR_Exported_Constants
+ */
+typedef enum
+{
+    IR_COMPEN_FLAG_1_2_CARRIER = BIT28,
+    IR_COMPEN_FLAG_1_4_CARRIER = BIT29,
+    IR_COMPEN_FLAG_1_N_SYSTEM_CLK = BIT28 | BIT29,
+} IRTxCompen_TypeDef;
+
+/** End of IR_Compensation_Flag
+  * \}
+  */
+
+#if IR_SUPPORT_TX_MODE_CONFIG
+/**
+ * \defgroup    IR_TxOutputMode IR TX Output Mode
+ * \{
+ * \ingroup     IR_Exported_Constants
+ */
+typedef enum
+{
+    IR_TX_PUSH_PULL,
+    IR_TX_OPEN_DRAIN,
+} IRTXMode_TypeDef;
+
+/** End of IR_TxOutputMode
+  * \}
+  */
+#endif
+
+/**
+ * \defgroup    IR_RX_Counter_Threshold IR RX Counter Threshold
+ * \{
+ * \ingroup     IR_Exported_Constants
+ */
+#define IS_IR_RX_COUNTER_THRESHOLD(THD) ((THD) <= 0x7fffffffUL)
+
+/** End of IR_RX_Counter_Threshold
+  * \}
+  */
+
+/**
+ * \defgroup    IR_Interrupt IR Interrupt
+ * \{
+ * \ingroup     IR_Exported_Constants
+ */
+/* All interrupts in transmission mode */
+#define IR_INT_TF_EMPTY                             BIT0
+#define IR_INT_TF_LEVEL                             BIT1
+#define IR_INT_TF_OF                                BIT4
+#if (IR_SUPPORT_TX_FINISH_INTERRUPT == 1)
+#define IR_INT_TX_FINISH                            BIT5
+#endif
+
+/* All interrupts in receiving mode */
+#define IR_INT_RF_FULL                              BIT0
+#define IR_INT_RF_LEVEL                             BIT1
+#define IR_INT_RX_CNT_OF                            BIT2
+#define IR_INT_RF_OF                                BIT3
+#define IR_INT_RX_CNT_THR                           BIT4
+#define IR_INT_RF_ERROR                             BIT5
+#define IR_INT_FALLING_EDGE                         BIT6
+#define IR_INT_RISING_EDGE                          BIT7
+
+
+#if (IR_SUPPORT_TX_FINISH_INTERRUPT == 1)
+#define IS_IR_TX_INT_CONFIG(CONFIG)   (((CONFIG) == IR_INT_TF_EMPTY)   || \
+                                       ((CONFIG) == IR_INT_TF_LEVEL)   || \
+                                       ((CONFIG) == IR_INT_TF_OF)      || \
+                                       ((CONFIG) == IR_INT_TX_FINISH))
+#else
+#define IS_IR_TX_INT_CONFIG(CONFIG)   (((CONFIG) == IR_INT_TF_EMPTY)   || \
+                                       ((CONFIG) == IR_INT_TF_LEVEL)   || \
+                                       ((CONFIG) == IR_INT_TF_OF)))
+#endif
+
+#define IS_IR_RX_INT_CONFIG(CONFIG)   (((CONFIG) == IR_INT_RF_FULL)     || \
+                                       ((CONFIG) == IR_INT_RF_LEVEL)   || \
+                                       ((CONFIG) == IR_INT_RX_CNT_OF)  || \
+                                       ((CONFIG) == IR_INT_RF_OF)      || \
+                                       ((CONFIG) == IR_INT_RX_CNT_THR) || \
+                                       ((CONFIG) == IR_INT_RF_ERROR)      || \
+                                       ((CONFIG) == IR_INT_RISING_EDGE) || \
+                                       ((CONFIG) == IR_INT_FALLING_EDGE))
+#define IS_IR_INT_CONFIG(CONFIG)      (IS_IR_TX_INT_CONFIG(CONFIG) || IS_IR_RX_INT_CONFIG(CONFIG))
+
+/** End of IR_Interrupt
+  * \}
+  */
+
+/**
+ * \defgroup    IR_Interrupts_Clear_Flag IR Interrupts Clear Flag
+ * \{
+ * \ingroup     IR_Exported_Constants
+ */
+/* Clear all interrupts in transmission mode */
+#define IR_TF_CLR                                   BIT0
+#define IR_INT_TF_EMPTY_CLR                         BIT1
+#define IR_INT_TF_LEVEL_CLR                         BIT2
+#define IR_INT_TF_OF_CLR                            BIT3
+#if (IR_SUPPORT_TX_FINISH_INTERRUPT == 1)
+#define IR_INT_TX_FINISH_CLR                        BIT4
+#endif
+
+#if (IR_SUPPORT_TX_FINISH_INTERRUPT == 1)
+#define IR_TX_INT_ALL_CLR                  (IR_INT_TF_EMPTY_CLR | \
+                                            IR_INT_TF_LEVEL_CLR | \
+                                            IR_INT_TF_OF_CLR    | \
+                                            IR_INT_TX_FINISH_CLR)
+#else
+#define IR_TX_INT_ALL_CLR                  (IR_INT_TF_EMPTY_CLR | \
+                                            IR_INT_TF_LEVEL_CLR | \
+                                            IR_INT_TF_OF_CLR)
+#endif
+
+/* Clear all interrupts in receiving mode */
+#define IR_INT_RF_FULL_CLR                         BIT0
+#define IR_INT_RF_LEVEL_CLR                        BIT1
+#define IR_INT_RX_CNT_OF_CLR                       BIT2
+#define IR_INT_RF_OF_CLR                           BIT3
+#define IR_INT_RX_CNT_THR_CLR                      BIT4
+#define IR_INT_RF_ERROR_CLR                        BIT5
+#define IR_INT_RX_FALLING_EDGE_CLR                 BIT6
+#define IR_INT_RX_RISING_EDGE_CLR                  BIT7
+#define IR_RF_CLR                                  BIT8
+
+#define IR_RX_INT_ALL_CLR                (IR_INT_RF_FULL_CLR | IR_INT_RF_LEVEL_CLR | \
+                                          IR_INT_RX_CNT_OF_CLR | IR_INT_RF_OF_CLR | \
+                                          IR_INT_RX_CNT_THR_CLR | IR_INT_RF_ERROR_CLR | \
+                                          IR_INT_RX_RISING_EDGE_CLR|IR_INT_RX_FALLING_EDGE_CLR)
+
+#if (IR_SUPPORT_TX_FINISH_INTERRUPT == 1)
+#define IS_IR_INT_CLEAR(INT)            (((INT) == IR_INT_TF_EMPTY_CLR) || ((INT) == IR_INT_TF_LEVEL_CLR) || \
+                                         ((INT) == IR_INT_TF_OF_CLR) || ((INT) == IR_INT_TX_FINISH_CLR) || ((INT) == IR_INT_RF_FULL_CLR) || \
+                                         ((INT) == IR_INT_RF_LEVEL_CLR) || ((INT) == IR_INT_RX_CNT_OF_CLR) || \
+                                         ((INT) == IR_INT_RF_OF_CLR) || ((INT) == IR_INT_RX_CNT_THR_CLR) || \
+                                         ((INT) == IR_INT_RX_RISING_EDGE_CLR) || ((INT) == IR_INT_RX_FALLING_EDGE_CLR) || \
+                                         ((INT) == IR_INT_RF_ERROR_CLR))
+#else
+#define IS_IR_INT_CLEAR(INT)            (((INT) == IR_INT_TF_EMPTY_CLR) || ((INT) == IR_INT_TF_LEVEL_CLR) || \
+                                         ((INT) == IR_INT_TF_OF_CLR) || ((INT) == IR_INT_RF_FULL_CLR) || \
+                                         ((INT) == IR_INT_RF_LEVEL_CLR) || ((INT) == IR_INT_RX_CNT_OF_CLR) || \
+                                         ((INT) == IR_INT_RF_OF_CLR) || ((INT) == IR_INT_RX_CNT_THR_CLR) || \
+                                         ((INT) == IR_INT_RX_RISING_EDGE_CLR) || ((INT) == IR_INT_RX_FALLING_EDGE_CLR) || \
+                                         ((INT) == IR_INT_RF_ERROR_CLR))
+#endif
+
+/** End of IR_Interrupts_Clear_Flag
+  * \}
+  */
+
+/**
+ * \defgroup    IR_Flag IR Flag
+ * \{
+ * \ingroup     IR_Exported_Constants
+ */
+#define IR_FLAG_TF_EMPTY                       BIT15
+#define IR_FLAG_TF_FULL                        BIT14
+#define IR_FLAG_TX_RUN                         BIT4
+#define IR_FLAG_RF_EMPTY                       BIT17
+#define IR_FLAG_RF_FULL                        BIT16
+#define IR_FLAG_RX_RUN                         BIT7
+
+#define IS_IR_FLAG(FLAG)                (((FLAG) == IR_FLAG_TF_EMPTY) || ((FLAG) == IR_FLAG_TF_FULL) || \
+                                         ((FLAG) == IR_FLAG_TX_RUN) || ((FLAG) == IR_FLAG_RF_EMPTY) || \
+                                         ((FLAG) == IR_FLAG_RF_FULL) || ((FLAG) == IR_FLAG_RX_RUN))
+
+/** End of IR_Flag
+  * \}
+  */
+
+#if (IR_SUPPORT_RAP_FUNCTION == 1)
+/**
+ * \defgroup    IR_Qactive_Force IR Qactive Force
+ * \{
+ * \ingroup     IR_Exported_Constants
+ */
+typedef enum
+{
+    IR_QACTIVE_ICG_PCLK = 0x0,
+    IR_QACTIVE_FW_FORCE_SCLK = 0x1,
+    IR_QACTIVE_FW_FORCE_PCLK = 0x2,
+} IRQactive_TypeDef;
+
+/** End of IR_Qactive_Force
+  * \}
+  */
+
+/**
+ * \defgroup    IR_Action IR Action
+ * \{
+ * \ingroup     IR_Exported_Constants
+ */
+typedef enum
+{
+    IR_ACTION_START_RX = 0,
+    IR_ACTION_START_TX = 1,
+} IRAction_TypeDef;
+
+/** End of IR_Action
+  * \}
+  */
+#endif
+
+/** End of IR_Exported_Constants
+  * \}
+  */
+
+/*============================================================================*
+ *                         Types
+ *============================================================================*/
+/** \defgroup IR_Exported_Types IR Exported Types
+  * \brief
+  * \{
+  */
+
+/**
+ * \brief       IR init structure definition.
+ *
+ * \ingroup     IR_Exported_Types
+ */
+typedef struct
+{
+    IRClock_TypeDef IR_Clock;                 /*!< Specifies the source clock frequency. */
+
+    uint32_t IR_Freq;                         /*!< Specifies the clock frequency.
+                                                   This parameter is IR carrier freqency whose unit is Hz. */
+
+    float IR_DutyCycle;                       /*!< Specifies the IR duty cycle. */
+
+    IRMode_TypeDef IR_Mode;                   /*!< Specifies the IR mode. */
+
+    IRIdleStatus_TypeDef IR_TxIdleLevel;      /*!< Specifies the IR output level in Tx mode. */
+
+    IRTxData_TypeDef IR_TxInverse;            /*!< Specifies inverse FIFO data or not in TX mode. */
+
+    uint32_t IR_TxFIFOThrLevel;               /*!< Specifies TX FIFO interrupt threshold in TX mode.
+                                                   When TX FIFO depth <= threshold value, trigger interrupt.
+                                                   This parameter can be a value of 1 ~ 32.
+                                                   This parameter can be a value of \ref IR_Tx_Threshold. */
+
+    IRRxStartMode_TypeDef IR_RxStartMode;     /*!< Specifies Start mode in RX mode. */
+
+    uint32_t IR_RxFIFOThrLevel;               /*!< Specifies RX FIFO interrupt threshold in RX mode.
+                                                   When RX FIFO depth > threshold value, trigger interrupt.
+                                                   This parameter can be a value of 1 ~ 32.
+                                                   This parameter can be a value of \ref IR_Rx_Threshold. */
+
+    IRRxFIFODiscard_TypeDef IR_RxFIFOFullCtrl; /*!< Specifies data discard mode
+                                                           in RX mode when RX FIFO is full and receiving new data. */
+
+    IRRxTriggerMode_TypeDef IR_RxTriggerMode; /*!< Specifies trigger in RX mode. */
+
+    IRRxFilterTime_TypeDef IR_RxFilterTime;   /*!< Specifies filter time in RX mode. */
+
+    IRRxCountPol_TypeDef IR_RxCntThrType;     /*!< Specifies counter level type
+                                                           when trigger IR_INT_RX_CNT_THR interrupt in RX mode. */
+
+    uint32_t IR_RxCntThr;                     /*!< Specifies counter threshold value
+                                                   when trigger IR_INT_RX_CNT_THR interrupt in RX mode. */
+
+    FunctionalState IR_TxDMAEn;               /*!< Specifies the Tx dma mode.
+                                                   This parameter must be a value of DISABLE and ENABLE. */
+
+    uint8_t IR_TxWaterLevel;                  /*!< Specifies the DMA tx water level.
+                                                   This parameter must range from 0 to 32.*/
+
+    FunctionalState IR_RxDMAEn;               /*!< Specifies the Rx dma mode.
+                                                   This parameter must be a value of DISABLE and ENABLE. */
+
+    uint8_t IR_RxWaterLevel;                  /*!< Specifies the DMA rx water level.
+                                                   This parameter must range from 0 to 32.*/
+
+#if IR_SUPPORT_TX_MODE_CONFIG
+    IRTXMode_TypeDef IR_TxOutputMode;         /*!< Specifies the IR Tx output mode.
+                                                   This parameter can be a value of \ref IR_TxOutputMode. */
+#endif
+
+} IR_InitTypeDef;
+
+/** End of IR_Exported_Types
+  * \}
+  */
+
+/*============================================================================*
+ *                         Functions
+ *============================================================================*/
+/** \defgroup IR_Exported_Functions IR Exported Functions
+  * \brief
+  * \{
+  */
+
+/**
+ * \brief Deinitializes the IR peripheral registers to their default values.
+ *
+ * \param[in] None.
+ *
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_ir_init(void)
+ * {
+ *     IR_DeInit();
+ * }
+ * \endcode
+ */
+void IR_DeInit(void);
+
+/**
+ * \brief   Initializes the IR peripheral according to the specified
+ *          parameters in IR_InitStruct.
+ *
+ * \param[in] IR_InitStruct: Pointer to a IR_InitTypeDef structure that
+ *            contains the configuration information for the specified IR peripheral.
+ *
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_ir_init(void)
+ * {
+ *     RCC_ClockCmd(IR_CLOCK, ENABLE);
+ *
+ *     IR_InitTypeDef IR_InitStruct;
+ *     IR_StructInit(&IR_InitStruct);
+ *
+ *     IR_InitStruct.IR_Freq               = 38000;
+ *     IR_InitStruct.IR_Mode               = IR_MODE_RX;
+ *     IR_InitStruct.IR_RxStartMode        = IR_RX_AUTO_MODE;
+ *     IR_InitStruct.IR_RxFIFOThrLevel     = IR_RX_FIFO_THR_LEVEL;
+ *     IR_InitStruct.IR_RxFIFOFullCtrl     = IR_RX_FIFO_FULL_DISCARD_NEWEST;
+ *     IR_InitStruct.IR_RxFilterTime       = IR_RX_FILTER_TIME_50NS;
+ *     IR_InitStruct.IR_RxTriggerMode      = IR_RX_FALL_EDGE;
+ *     IR_InitStruct.IR_RxCntThrType       = IR_RX_Count_High_Level;
+ *     IR_InitStruct.IR_RxCntThr           = 0x1F40;
+ *     IR_Init(&IR_InitStruct);
+ *     IR_Cmd(IR_MODE_RX, ENABLE);
+ *     IR_ClearRxFIFO();
+ * }
+ * \endcode
+ */
+void IR_Init(IR_InitTypeDef *IR_InitStruct);
+
+/**
+ * \brief  Fills each IR_InitStruct member with its default value.
+ *
+ * \param[in] IR_InitStruct: Pointer to an IR_InitTypeDef structure which will be initialized.
+ *
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_ir_init(void)
+ * {
+ *     RCC_ClockCmd(IR_CLOCK, ENABLE);
+ *
+ *     IR_InitTypeDef IR_InitStruct;
+ *     IR_StructInit(&IR_InitStruct);
+ *
+ *     IR_InitStruct.IR_Freq               = 38000;
+ *     IR_InitStruct.IR_Mode               = IR_MODE_RX;
+ *     IR_InitStruct.IR_RxStartMode        = IR_RX_AUTO_MODE;
+ *     IR_InitStruct.IR_RxFIFOThrLevel     = IR_RX_FIFO_THR_LEVEL;
+ *     IR_InitStruct.IR_RxFIFOFullCtrl     = IR_RX_FIFO_FULL_DISCARD_NEWEST;
+ *     IR_InitStruct.IR_RxFilterTime       = IR_RX_FILTER_TIME_50NS;
+ *     IR_InitStruct.IR_RxTriggerMode      = IR_RX_FALL_EDGE;
+ *     IR_InitStruct.IR_RxCntThrType       = IR_RX_Count_High_Level;
+ *     IR_InitStruct.IR_RxCntThr           = 0x1F40;
+ *     IR_Init(&IR_InitStruct);
+ *     IR_Cmd(IR_MODE_RX, ENABLE);
+ *     IR_ClearRxFIFO();
+ * }
+ * \endcode
+ */
+void IR_StructInit(IR_InitTypeDef *IR_InitStruct);
+
+/**
+ * \brief   Enable or disable the selected IR mode.
+ *
+ * \param[in] mode: Selected IR operation mode.
+ *            This parameter can be one of the following values:
+ *            \arg IR_MODE_TX: Transmission mode.
+ *            \arg IR_MODE_RX: Receiving mode.
+ * \param[in] NewState: New state of the operation mode.
+ *            This parameter can be: ENABLE or DISABLE.
+ *
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_ir_init(void)
+ * {
+ *     RCC_ClockCmd(IR_CLOCK, ENABLE);
+ *
+ *     IR_InitTypeDef IR_InitStruct;
+ *     IR_StructInit(&IR_InitStruct);
+ *
+ *     IR_InitStruct.IR_Freq               = 38000;
+ *     IR_InitStruct.IR_Mode               = IR_MODE_RX;
+ *     IR_InitStruct.IR_RxStartMode        = IR_RX_AUTO_MODE;
+ *     IR_InitStruct.IR_RxFIFOThrLevel     = IR_RX_FIFO_THR_LEVEL;
+ *     IR_InitStruct.IR_RxFIFOFullCtrl     = IR_RX_FIFO_FULL_DISCARD_NEWEST;
+ *     IR_InitStruct.IR_RxFilterTime       = IR_RX_FILTER_TIME_50NS;
+ *     IR_InitStruct.IR_RxTriggerMode      = IR_RX_FALL_EDGE;
+ *     IR_InitStruct.IR_RxCntThrType       = IR_RX_Count_High_Level;
+ *     IR_InitStruct.IR_RxCntThr           = 0x1F40;
+ *     IR_Init(&IR_InitStruct);
+ *     IR_Cmd(IR_MODE_RX, ENABLE);
+ *     IR_ClearRxFIFO();
+ * }
+ * \endcode
+ */
+void IR_Cmd(uint32_t mode, FunctionalState NewState);
+
+/**
+ * \brief Start trigger receive, only in manual receive mode.
+ *
+ * \param[in] None.
+ *
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void ir_demo(void)
+ * {
+ *     IR_StartManualRxTrigger();
+ * }
+ * \endcode
+ */
+void IR_StartManualRxTrigger(void);
+
+/**
+ * \brief   Config counter threshold value in receiving mode.You can use it to stop receiving IR data.
+ *
+ * \param[in] IR_RxCntThrType: Count threshold type.
+ *            This parameter can be the following values:
+ *            \arg IR_RX_Count_Low_Level: Low level counter value >= IR_RxCntThr, trigger IR_INT_RX_CNT_THR interrupt.
+ *            \arg IR_RX_Count_High_Level: High level counter value >= IR_RxCntThr, trigger IR_INT_RX_CNT_THR interrupt.
+ * \param[in] IR_RxCntThr: Configure IR Rx counter threshold value which can be 0 to 0x7fffffffUL.
+ *
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void ir_demo(void)
+ * {
+ *     IR_SetRxCounterThreshold(IR_RX_Count_Low_Level, 0x100);
+ * }
+ * \endcode
+ */
+void IR_SetRxCounterThreshold(uint32_t IR_RxCntThrType, uint32_t IR_RxCntThr);
+
+/**
+ * \brief   Send data.
+ *
+ * \param[in] pBuf: Data buffer to send.
+ * \param[in] len: Send data length.
+ * \param[in] IsLastPacket: Is it the last package of data.
+ *            This parameter can be one of the following values:
+ *            \arg ENABLE: The last data in IR packet and there is no continuous data.In other words, an infrared data transmission is completed.
+ *            \arg DISABLE: There is data to be transmitted continuously.
+ *
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void ir_demo(void)
+ * {
+ *     uint32_t data_buf[80] = {0};
+ *     IR_SendBuf(data_buf, 68, DISABLE);
+ * }
+ * \endcode
+ */
+void IR_SendBuf(uint32_t *pBuf, uint32_t len, FunctionalState IsLastPacket);
+
+/**
+ * \brief  Send compensation data.
+ *
+ * \param[in] comp_type: Compensation data type.
+ *            This parameter can be one of the following values:
+ *            \arg IR_COMPEN_FLAG_1_2_CARRIER: 1/2 carrier freqency.
+ *            \arg IR_COMPEN_FLAG_1_4_CARRIER: 1/4 carrier freqency.
+ *            \arg IR_COMPEN_FLAG_1_N_SYSTEM_CLK: MOD((0x48[27:16]+0x00[11:0]), 4095)/40MHz.
+ *            User can call function of IR_ConfigCompParam to configure 0x48[27:16].
+ * \param[in] buf: Data buffer to send.
+ * \param[in] length: Data length.
+ * \param[in] IsLastPacket: Is it the last package of data.
+ *            This parameter can be the following values:
+ *            \arg ENABLE: The last data in IR packet and there is no continuous data.In other words, an infrared data transmission is completed.
+ *            \arg DISABLE: There is data to be transmitted continuously.
+ *
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void ir_demo(void)
+ * {
+ *     uint32_t data_buf[80] = {0};
+ *     IR_SendCompenBuf(IR_COMPEN_FLAG_1_2_CARRIER, data_buf, 68, DISABLE);
+ * }
+ * \endcode
+ */
+void IR_SendCompenBuf(IRTxCompen_TypeDef comp_type, uint32_t *pBuf, uint32_t len,
+                      FunctionalState IsLastPacket);
+
+/**
+ * \brief   Read data From RX FIO.
+ *
+ * \param[in] pBuf: Buffer address to receive data.
+ * \param[in] length: Read data length.
+ *
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void ir_demo(void)
+ * {
+ *     uint32_t data_buf[80] = {0};
+ *     IR_ReceiveBuf(data_buf, 68);
+ * }
+ * \endcode
+ */
+void IR_ReceiveBuf(uint32_t *pBuf, uint32_t length);
+
+/**
+ * \brief     Enables or disables the specified IR interrupt source.
+ *
+ * \param[in] IR_INT: Specifies the IR interrupt source to be enabled or disabled.
+ *            This parameter can be oen of the following values:
+ *            \arg IR_INT_TF_EMPTY: TX FIFO empty interrupt source.
+ *            \arg IR_INT_TF_LEVEL: TX FIFO threshold interrupt source.
+ *            \arg IR_INT_TF_OF: TX FIFO overflow interrupt source.
+ *            \arg IR_INT_RF_FULL: RX FIFO  full interrupt source.
+ *            \arg IR_INT_RF_LEVEL: RX FIFO threshold interrupt source.
+ *            \arg IR_INT_RX_CNT_OF: RX counter overflow interrupt source.
+ *            \arg IR_INT_RF_OF: RX FIFO overflow interrupt source.
+ *            \arg IR_INT_RX_CNT_THR: RX counter threshold interrupt source.
+ *            \arg IR_INT_RF_ERROR: RX FIFO error read interrupt source. Trigger when RX FIFO empty and read RX FIFO.
+ *            \arg IR_INT_RISING_EDGE: IR RX Rising edge interrupt.
+ *            \arg IR_INT_FALLING_EDGE: IR RX Falling edge interrupt.
+ * \param[in] NewState: New state of the specified IR interrupt.
+ *            This parameter can be: ENABLE or DISABLE.
+ *
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void ir_demo(void)
+ * {
+ *     IR_INTConfig(IR_INT_TF_EMPTY, ENABLE);
+ * }
+ * \endcode
+ */
+void IR_INTConfig(uint32_t IR_INT, FunctionalState NewState);
+
+/**
+ * \brief     Mask or unmask the specified IR interrupt source.
+ *
+ * \param[in] IR_INT: Specifies the IR interrupts sources to be mask or unmask.
+ *            This parameter can be the following values:
+ *            \arg IR_INT_TF_EMPTY: TX FIFO empty interrupt.
+ *            \arg IR_INT_TF_LEVEL: TX FIFO threshold interrupt.
+ *            \arg IR_INT_TF_OF: TX FIFO overflow interrupt.
+ *            \arg IR_INT_RF_FULL: RX FIFO  full interrupt.
+ *            \arg IR_INT_RF_LEVEL: RX FIFO threshold interrupt.
+ *            \arg IR_INT_RX_CNT_OF: RX counter overflow interrupt.
+ *            \arg IR_INT_RF_OF: RX FIFO overflow interrupt.
+ *            \arg IR_INT_RX_CNT_THR: RX counter threshold interrupt.
+ *            \arg IR_INT_RF_ERROR: RX FIFO error read interrupt. Trigger when RX FIFO empty and read RX FIFO.
+ *            \arg IR_INT_RISING_EDGE: IR RX Rising edge interrupt.
+ *            \arg IR_INT_FALLING_EDGE: IR RX Falling edge interrupt.
+ * \param[in] NewState: New state of the specified IR interrupts.
+ *            This parameter can be: ENABLE or DISABLE.
+ *
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void ir_demo(void)
+ * {
+ *     IR_MaskINTConfig(IR_INT_TF_EMPTY, ENABLE);
+ * }
+ * \endcode
+ */
+void IR_MaskINTConfig(uint32_t IR_INT, FunctionalState NewState);
+
+/**
+ * \brief     Get the specified IR interrupt status.
+ *
+ * \param[in] IR_INT: The specified IR interrupts.
+ *            This parameter can be one of the following values:
+ *            \arg IR_INT_TF_EMPTY: TX FIFO empty interrupt.
+ *            \arg IR_INT_TF_LEVEL: TX FIFO threshold interrupt.
+ *            \arg IR_INT_TF_OF: TX FIFO overflow interrupt.
+ *            \arg IR_INT_RF_FULL: RX FIFO  full interrupt.
+ *            \arg IR_INT_RF_LEVEL: RX FIFO threshold interrupt.
+ *            \arg IR_INT_RX_CNT_OF: RX counter overflow interrupt.
+ *            \arg IR_INT_RF_OF: RX FIFO overflow interrupt.
+ *            \arg IR_INT_RX_CNT_THR: RX counter threshold interrupt.
+ *            \arg IR_INT_RF_ERROR: RX FIFO error read interrupt. Trigger when RX FIFO empty and read RX FIFO.
+ *            \arg IR_INT_RISING_EDGE: IR RX Rising edge interrupt.
+ *            \arg IR_INT_FALLING_EDGE: IR RX Falling edge interrupt.
+ *
+ * \return  The new state of IR_INT (SET or RESET).
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void ir_demo(void)
+ * {
+ *     ITStatus int_status = IR_GetINTStatus(IR_INT_TF_EMPTY);
+ * }
+ * \endcode
+ */
+ITStatus IR_GetINTStatus(uint32_t IR_INT);
+
+/**
+ * \brief     Clear the IR interrupt pending bit.
+ *
+ * \param[in] IR_CLEAR_INT: specifies the interrupt pending bit to clear.
+ *            This parameter can be any combination of the following values:
+ *            \arg IR_INT_TF_EMPTY_CLR: Clear TX FIFO empty interrupt.
+ *            \arg IR_INT_TF_LEVEL_CLR: Clear TX FIFO threshold interrupt.
+ *            \arg IR_INT_TF_OF_CLR: Clear TX FIFO overflow interrupt.
+ *            \arg IR_INT_RF_FULL_CLR: Clear RX FIFO  full interrupt.
+ *            \arg IR_INT_RF_LEVEL_CLR: Clear RX FIFO threshold interrupt.
+ *            \arg IR_INT_RX_CNT_OF_CLR: Clear RX counter overflow interrupt.
+ *            \arg IR_INT_RF_OF_CLR: Clear RX FIFO overflow interrupt.
+ *            \arg IR_INT_RX_CNT_THR_CLR: Clear RX counter threshold interrupt.
+ *            \arg IR_INT_RF_ERROR_CLR: Clear RX FIFO error read interrupt. Trigger when RX FIFO empty and read RX FIFO.
+ *            \arg IR_INT_RX_RISING_EDGE_CLR: Clear RX Rising edge interrupt.
+ *            \arg IR_INT_RX_FALLING_EDGE_CLR: Clear RX Falling edge interrupt.
+ *
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void ir_demo(void)
+ * {
+ *     IR_ClearINTPendingBit(IR_INT_RX_CNT_OF_CLR);
+ * }
+ * \endcode
+ */
+void IR_ClearINTPendingBit(uint32_t IR_CLEAR_INT);
+
+/**
+ * \brief Get free size of TX FIFO.
+ *
+ * \param[in] None.
+ *
+ * \return The free size of TX FIFO.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void ir_demo(void)
+ * {
+ *     uint16_t data_len = IR_GetTxFIFOFreeLen();
+ * }
+ * \endcode
+ */
+uint16_t IR_GetTxFIFOFreeLen(void);
+
+/**
+ * \brief Get data size in RX FIFO.
+ *
+ * \param[in] None.
+ *
+ * \return Current data size in RX FIFO.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void ir_demo(void)
+ * {
+ *     uint16_t data_len = IR_GetRxDataLen();
+ * }
+ * \endcode
+ */
+uint16_t IR_GetRxDataLen(void);
+
+/**
+ * \brief   Send one data.
+ *
+ * \param[in] data: Send data.
+ *
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void ir_demo(void)
+ * {
+ *     IR_SendData(0x80000100);
+ * }
+ * \endcode
+ */
+void IR_SendData(uint32_t data);
+
+/**
+ * \brief Read one data.
+ *
+ * \param[in] None.
+ *
+ * \return Data which read from RX FIFO.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void ir_demo(void)
+ * {
+ *     uint32_t data = IR_ReceiveData();
+ * }
+ * \endcode
+ */
+uint32_t IR_ReceiveData(void);
+
+/**
+ * \brief  Set tx threshold, when TX FIFO depth <= threshold value trigger interrupt.
+ *
+ * \param[in] thd: Tx threshold.
+ *
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void ir_demo(void)
+ * {
+ *     IR_SetTxThreshold(30);
+ * }
+ * \endcode
+ */
+void IR_SetTxThreshold(uint8_t thd);
+
+/**
+ * \brief   Set tx threshold, when RX FIFO depth >= threshold value trigger interrupt.
+ *
+ * \param[in] thd: Rx threshold.
+ *
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void ir_demo(void)
+ * {
+ *     IR_SetRxThreshold(2);
+ * }
+ * \endcode
+ */
+void IR_SetRxThreshold(uint8_t thd);
+
+/**
+ * \brief Get IR RX current count.
+ *
+ * \param[in] None.
+ *
+ * \return Current counter.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void ir_demo(void)
+ * {
+ *     uint32_t count = IR_GetRxCurrentCount();
+ * }
+ * \endcode
+ */
+uint32_t IR_GetRxCurrentCount(void);
+
+/**
+ * \brief Clear IR TX FIFO.
+ *
+ * \param[in] None.
+ *
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void ir_demo(void)
+ * {
+ *     IR_ClearTxFIFO();
+ * }
+ * \endcode
+ */
+void IR_ClearTxFIFO(void);
+
+/**
+ * \brief Clear IR RX FIFO.
+ *
+ * \param[in] None.
+ *
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void ir_demo(void)
+ * {
+ *     IR_ClearRxFIFO();
+ * }
+ * \endcode
+ */
+void IR_ClearRxFIFO(void);
+
+/**
+ * \brief Check whether the specified IR flag is set.
+ *
+ * \param[in] IR_FLAG: Specifies the flag to check.
+ *            This parameter can be one of the following values:
+ *            \arg IR_FLAG_TF_EMPTY: TX FIFO empty or not. If SET, TX FIFO is empty.
+ *            \arg IR_FLAG_TF_FULL: TX FIFO full or not. If SET, TX FIFO is full.
+ *            \arg IR_FLAG_TX_RUN: TX run or not. If SET, TX is running.
+ *            \arg IR_FLAG_RF_EMPTY: RX FIFO empty or not. If SET, RX FIFO is empty.
+ *            \arg IR_FLAG_RF_FULL: RX FIFO full or not. If SET, RX FIFO is full.
+ *            \arg IR_FLAG_RX_RUN: RX run or not. If SET, RX is running.
+ *
+ * \return The new state of IR_FLAG (SET or RESET).
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void ir_demo(void)
+ * {
+ *     FlagStatus flag_status = IR_GetFlagStatus(IR_FLAG_TF_EMPTY);
+ * }
+ * \endcode
+ */
+FlagStatus IR_GetFlagStatus(uint32_t IR_FLAG);
+
+/**
+ * \brief   Set or reset tx data inverse.
+ *
+ * \param[in] NewState: This parameter can be: ENABLE or DISABLE.
+ *
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void ir_demo(void)
+ * {
+ *     IR_TxWaveDefInverseCmd(ENABLE);
+ * }
+ * \endcode
+ */
+void IR_TxWaveDefInverseCmd(FunctionalState NewState);
+
+/**
+ * \brief  Enbale TX output inverse or not.
+ *
+ * \param[in] NewState: This parameter can be: ENABLE or DISABLE.
+ *
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void ir_demo(void)
+ * {
+ *     IR_TxPolarityInverseCmd(ENABLE);
+ * }
+ * \endcode
+ */
+void IR_TxPolarityInverseCmd(FunctionalState NewState);
+
+/**
+ * \brief Get IR RX Level.
+ *
+ * \param[in] None.
+ *
+ * \return Current Level.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void ir_demo(void)
+ * {
+ *     uint32_t level = IR_GetRxCurrentLevel();
+ * }
+ * \endcode
+ */
+uint32_t IR_GetRxCurrentLevel(void);
+
+#if (IR_SUPPORT_CLOCK_SOURCE_DIV_CONFIG == 1)
+/**
+  * \brief  IR clock config.
+  * \param  ClockSrc: specifies the clock source to gates its clock.
+  * \param  ClockDiv: specifies the clock divide to gates its clock.
+  * \return None
+  */
+void IR_SetClock(IRClockSrc_TypeDef ClockSrc, IRClockDiv_TypeDef ClockDiv);
+#endif
+
+#if (IR_SUPPORT_RAP_FUNCTION == 1)
+
+void IR_RAPModeCmd(FunctionalState NewState);
+
+void IR_ActionTrigger(uint32_t Action);
+
+#endif
+
+#if (IR_SUPPORT_AUTO_CLOCK == 1)
+
+void IR_ClockAutoModeCmd(FunctionalState Newstate);
+
+#endif
+
+/** End of IR_Exported_Functions
+  * \}
+  */
+
+/** End of IR
+  * \}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RTL_IR_H */
+
+
+
+
+
diff --git a/bee/drivers/ir/src/CMakeLists.txt b/bee/drivers/ir/src/CMakeLists.txt
new file mode 100644
index 00000000..dd5e359a
--- /dev/null
+++ b/bee/drivers/ir/src/CMakeLists.txt
@@ -0,0 +1,4 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+add_subdirectory(device)
diff --git a/bee/drivers/ir/src/device/CMakeLists.txt b/bee/drivers/ir/src/device/CMakeLists.txt
new file mode 100644
index 00000000..390b5305
--- /dev/null
+++ b/bee/drivers/ir/src/device/CMakeLists.txt
@@ -0,0 +1,11 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+if(CONFIG_REALTEK_BEE_COMMON_DRIVER)
+    file(GLOB BEE_DRIVER_COMMON_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/rtl_common/*.c")
+    zephyr_library_sources(${BEE_DRIVER_COMMON_SOURCES})
+endif()
+
+add_soc_series_subdir(rtl8752h)
+add_soc_series_subdir(rtl87x2g)
+add_soc_series_subdir(rtl87x2j)
diff --git a/bee/drivers/ir/src/device/rtl8752h/rtl876x_ir.c b/bee/drivers/ir/src/device/rtl8752h/rtl876x_ir.c
new file mode 100644
index 00000000..339626b1
--- /dev/null
+++ b/bee/drivers/ir/src/device/rtl8752h/rtl876x_ir.c
@@ -0,0 +1,666 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "rtl876x_rcc.h"
+#include "rtl876x_ir.h"
+#include "app_section.h"
+
+/**
+  * @brief  Deinitializes the IR peripheral registers to their default values.
+  * @param  None
+  * @retval None
+  */
+void IR_DeInit(void)
+{
+    RCC_PeriphClockCmd(APBPeriph_IR, APBPeriph_IR_CLOCK, DISABLE);
+}
+
+/**
+  * @brief Initializes the IR peripheral according to the specified
+  *   parameters in the IR_InitStruct
+  * @param  IRx: selected IR peripheral.
+  * @param  IR_InitStruct: pointer to a IR_InitTypeDef structure that
+  *   contains the configuration information for the specified IR peripheral
+  * @retval None
+  */
+void IR_Init(IR_InitTypeDef *IR_InitStruct)
+{
+    /* Check the parameters */
+    assert_param(IS_IR_CLOCK(IR_InitStruct->IR_Clock));
+
+    if (IR_InitStruct->IR_Clock == 40000000)
+    {
+        assert_param(IS_IR_FREQUENCY_40M(IR_InitStruct->IR_Freq));
+    }
+    else if (IR_InitStruct->IR_Clock == 90000000)
+    {
+        assert_param(IS_IR_FREQUENCY_90M(IR_InitStruct->IR_Freq));
+    }
+    else if (IR_InitStruct->IR_Clock == 100000000)
+    {
+        assert_param(IS_IR_FREQUENCY_100M(IR_InitStruct->IR_Freq));
+    }
+    assert_param(IS_IR_MODE(IR_InitStruct->IR_Mode));
+
+    /* Configure IR clock divider. Formula: IR_CLK = IO_CLK/(1+IR_CLK_DIV) */
+    uint32_t ir_clk_div_num = (IR_InitStruct->IR_Clock / IR_InitStruct->IR_Freq) - 1;
+    uint32_t duty_cycle_num = ((double)(ir_clk_div_num + 1.0)) / (IR_InitStruct->IR_DutyCycle);
+
+    IR->CLK_DIV = ir_clk_div_num;
+    if (IR_InitStruct->IR_Mode == IR_MODE_TX)
+    {
+        /* Check the parameters in TX mode */
+        assert_param(IS_IR_IDLE_STATUS(IR_InitStruct->IR_TxIdleLevel));
+        assert_param(IS_IR_TX_DATA_TYPE(IR_InitStruct->IR_TxInverse));
+        assert_param(IS_IR_TX_THRESHOLD(IR_InitStruct->IR_TxFIFOThrLevel));
+
+        /* Configure TX mode parameters and disable all TX interrupt */
+        IR->TX_CONFIG = (IR_InitStruct->IR_Mode) | \
+                        (IR_InitStruct->IR_TxIdleLevel) | \
+                        (IR_InitStruct->IR_TxInverse) | \
+                        ((IR_InitStruct->IR_TxFIFOThrLevel) << IR_TX_FIFO_THRESHOLD_Pos) | \
+                        ((duty_cycle_num & 0x3FFF) << IR_TX_DUTY_NUM_Pos);
+        /* Clear all TX interrupt and TX FIFO */
+        IR->TX_INT_CLR = IR_INT_ALL_CLR | IR_TX_FIFO_CLR_Msk;
+
+        if (IR_InitStruct->IR_TxDmaEn != DISABLE)
+        {
+            IR->DMA_CONFIG = ((IR_InitStruct->IR_TxDmaEn << IR_TX_DMA_EN_Pos) & IR_TX_DMA_EN_Msk) | \
+                             ((IR_InitStruct->IR_TxWaterLevel << IR_TX_WATER_LEVEL_Pos) & IR_TX_WATER_LEVEL_Msk);
+        }
+        else
+        {
+            IR->DMA_CONFIG = ((IR_InitStruct->IR_TxDmaEn << IR_TX_DMA_EN_Pos) & IR_TX_DMA_EN_CLR) | \
+                             ((IR_InitStruct->IR_TxWaterLevel << IR_TX_WATER_LEVEL_Pos) & IR_TX_WATER_LEVEL_CLR);
+        }
+    }
+    else
+    {
+        /* Check the parameters in RX mode */
+        assert_param(IS_RX_START_MODE(IR_InitStruct->IR_RxStartMode));
+        assert_param(IS_IR_RX_THRESHOLD(IR_InitStruct->IR_RxFIFOThrLevel));
+        assert_param(IS_IR_RX_FIFO_FULL_CTRL(IR_InitStruct->IR_RxFIFOFullCtrl));
+        assert_param(IS_RX_RX_TRIGGER_EDGE(IR_InitStruct->IR_RxTriggerMode));
+        assert_param(IS_IR_RX_FILTER_TIME_CTRL(IR_InitStruct->IR_RxFilterTime));
+        assert_param(IS_IR_RX_COUNT_LEVEL_CTRL(IR_InitStruct->IR_RxCntThrType));
+        assert_param(IS_IR_RX_COUNTER_THRESHOLD(IR_InitStruct->IR_RxCntThr));
+
+        /* Enable RX mode */
+        IR->TX_CONFIG |= (IR_InitStruct->IR_Mode);
+        /* Configure RX mode parameters and disable all RX interrupt */
+        IR->RX_CONFIG = (IR_InitStruct->IR_RxStartMode) | \
+                        (IR_InitStruct->IR_RxTriggerMode)  | \
+                        (IR_InitStruct->IR_RxFilterTime)   | \
+                        (IR_InitStruct->IR_RxFIFOFullCtrl) | \
+                        (IR_InitStruct->IR_RxFIFOThrLevel << IR_RX_FIFO_LEVEL_Pos);
+        /* Configure IR RX counter threshold parameters */
+        IR->RX_CNT_INT_SEL = (IR_InitStruct->IR_RxCntThrType) | (IR_InitStruct->IR_RxCntThr);
+        /* Clear all RX interrupt and RX FIFO */
+        IR->RX_INT_CLR = IR_RX_INT_ALL_CLR | IR_RX_FIFO_CLR_Msk;
+//        IR->RX_EX_INT |= IR_RX_RISING_EDGE_INT_CLR_Msk | IR_RX_FALLING_EDGE_INT_CLR_Msk;
+
+        if (IR_InitStruct->IR_RxDmaEn != DISABLE)
+        {
+            IR->DMA_CONFIG = ((IR_InitStruct->IR_RxDmaEn << IR_RX_DMA_EN_Pos) & IR_RX_DMA_EN_Msk) | \
+                             ((IR_InitStruct->IR_RxWaterLevel << IR_RX_WATER_LEVEL_Pos) & IR_RX_WATER_LEVEL_Msk);
+        }
+        else
+        {
+            IR->DMA_CONFIG = ((IR_InitStruct->IR_RxDmaEn << IR_RX_DMA_EN_Pos) & IR_RX_DMA_EN_CLR) | \
+                             ((IR_InitStruct->IR_RxWaterLevel << IR_RX_WATER_LEVEL_Pos) & IR_RX_WATER_LEVEL_CLR);
+        }
+    }
+}
+
+/**
+  * @brief  Fills each IR_InitStruct member with its default value.
+  * @param  IR_InitStruct: pointer to an IR_InitTypeDef structure which will be initialized.
+  * @retval None
+  */
+void IR_StructInit(IR_InitTypeDef *IR_InitStruct)
+{
+    IR_InitStruct->IR_Clock             = IR_CLOCK_40M;
+    IR_InitStruct->IR_Freq              = 38000;
+    IR_InitStruct->IR_DutyCycle         = 3;
+    IR_InitStruct->IR_Mode              = IR_MODE_TX;
+    IR_InitStruct->IR_TxIdleLevel       = IR_IDLE_OUTPUT_LOW;
+    IR_InitStruct->IR_TxInverse         = IR_TX_DATA_NORMAL;
+    IR_InitStruct->IR_TxFIFOThrLevel    = 0;
+    IR_InitStruct->IR_RxStartMode       = IR_RX_AUTO_MODE;
+    IR_InitStruct->IR_RxFIFOThrLevel    = 0;
+    IR_InitStruct->IR_RxFIFOFullCtrl    = IR_RX_FIFO_FULL_DISCARD_NEWEST;
+    IR_InitStruct->IR_RxTriggerMode     = IR_RX_FALL_EDGE;
+    IR_InitStruct->IR_RxFilterTime      = IR_RX_FILTER_TIME_50ns;
+    IR_InitStruct->IR_RxCntThrType      = IR_RX_Count_Low_Level;
+    IR_InitStruct->IR_RxCntThr          = 0x23a; /* This value can be 0 to 0x7fffffff */
+    IR_InitStruct->IR_TxDmaEn           = DISABLE;
+    IR_InitStruct->IR_TxWaterLevel      = 15;
+    IR_InitStruct->IR_RxDmaEn           = DISABLE;
+    IR_InitStruct->IR_RxWaterLevel      = 0;
+}
+
+/**
+  * @brief   Enable or disable the selected IR mode.
+  * @param  mode: selected IR operation mode.
+  *   This parameter can be the following values:
+  *     @arg IR_MODE_TX: Transmission mode.
+  *     @arg IR_MODE_RX: Receiving mode.
+  * @param  NewState: new state of the operation mode.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void IR_Cmd(uint32_t mode, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_IR_MODE(mode));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (NewState != DISABLE)
+    {
+        if (mode == IR_MODE_TX)
+        {
+            /* Start Transmission mode */
+            IR->TX_CONFIG |= IR_TX_START_Msk;
+        }
+        else
+        {
+            /* Start Receiving mode */
+            IR->RX_CONFIG |= IR_RX_START_Msk;
+        }
+    }
+    else
+    {
+        if (mode == IR_MODE_TX)
+        {
+            /* Stop Transmission mode */
+            IR->TX_CONFIG &= IR_TX_START_CLR;
+        }
+        else
+        {
+            /* Stop Receiving mode */
+            IR->RX_CONFIG &= IR_RX_START_CLR;
+        }
+    }
+}
+
+/**
+  * @brief  Mask or unmask the specified IR interrupts.
+  * @param  IR_INT: specifies the IR interrupts sources to be mask or unmask.
+  *         This parameter can be the following values:
+  *     @arg IR_INT_TF_EMPTY: When TX FIFO is empty, TX FIFO Empty Interrupt will be triggered.
+  *     @arg IR_INT_TF_LEVEL: When TX FIFO offset <= threshold value, trigger TX FIFO Level Interrupt.
+  *     @arg IR_INT_TF_OF: When TX FIFO is full, data continues to be wrote to TX FIFO, TX FIFO Over interrupt will be triggered.
+  *     @arg IR_INT_TX_FINISH: When TX finished, TX Finish Interrupt will be triggered.
+  *     @arg IR_INT_RF_FULL: When RX FIFO offset = 32, RX FIFO Full Interrupt will be triggered.
+  *     @arg IR_INT_RF_LEVEL: When RX FIFO offset > threshold value, trigger RX FIFO Level Interrupt.
+  *     @arg IR_INT_RX_CNT_OF: When RX counter is overflow, RX counter overflow interrupt will be triggered.
+  *     @arg IR_INT_RF_OF: When RX FIFO is full and continue to be wrote, RX FIFO overflow interrupt will be triggered.
+  *     @arg IR_INT_RX_CNT_THR: When RX counter >= IR_RX_CNT_THR, RX Counter Threshold Interrupt will be triggered.
+  *     @arg IR_INT_RF_ERROR: When RX FIFO is empty and continue to be read, RX FIFO error read interrupt will be triggered.
+  *     @arg IR_INT_RISING_EDGE: When RX FIFO receives a low to high pulse, RX Rising Edge Interrupt will be triggered.
+  *     @arg IR_INT_FALLING_EDGE: When RX FIFO receives a high to low pulse, RX Falling Edge Interrupt will be triggered.
+  * @param  NewState: new state of the specified IR interrupts.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void IR_MaskINTConfig(uint32_t IR_INT, FunctionalState newState)
+{
+    /* Check the parameters */
+    assert_param(IS_IR_INT_CONFIG(IR_INT));
+    assert_param(IS_FUNCTIONAL_STATE(newState));
+
+    if (newState == ENABLE)
+    {
+        if ((IR->TX_CONFIG) & IR_MODE_SEL_Msk)
+        {
+            /* Enable the selected IR interrupts in RX mode */
+            if (IR_INT & IR_RX_EXTENSION_INT)
+            {
+                IR->RX_EX_INT |= (IR_INT & 0x03) << 2;
+            }
+            else
+            {
+                IR->RX_CONFIG |= (IR_INT << IR_RX_MSK_TO_EN_Pos);
+            }
+        }
+        else
+        {
+            /* Enable the selected IR interrupts in TX mode */
+            if (IR_INT == IR_INT_TF_OF)
+            {
+                IR->TX_CONFIG |= (IR_INT << IR_TX_FIFO_OVER_MSK_TO_EN_Pos);
+            }
+            else if (IR_INT == IR_INT_TX_FINISH)
+            {
+                IR->TX_SR |= IR_INT << 1;
+            }
+            else
+            {
+                IR->TX_CONFIG |= (IR_INT << IR_TX_MSK_TO_EN_Pos);
+            }
+        }
+    }
+    else
+    {
+        if ((IR->TX_CONFIG) & IR_MODE_SEL_Msk)
+        {
+            /* Disable the selected IR interrupts in RX mode */
+            if (IR_INT & IR_RX_EXTENSION_INT)
+            {
+                IR->RX_EX_INT &= ~((IR_INT & 0x03) << 2);
+            }
+            else
+            {
+                IR->RX_CONFIG &= (~(IR_INT << IR_RX_MSK_TO_EN_Pos));
+            }
+        }
+        else
+        {
+            /* Disable the selected IR interrupts in TX mode */
+            if (IR_INT == IR_INT_TF_OF)
+            {
+                IR->TX_CONFIG &= (~(IR_INT << IR_TX_FIFO_OVER_MSK_TO_EN_Pos));
+            }
+            else if (IR_INT == IR_INT_TX_FINISH)
+            {
+                IR->TX_SR &= (~(IR_INT << 1));
+            }
+            else
+            {
+                IR->TX_CONFIG &= (~(IR_INT << IR_TX_MSK_TO_EN_Pos));
+            }
+        }
+    }
+}
+
+/**
+  * @brief  Enables or disables the specified IR interrupts.
+  * @param  IR_INT: specifies the IR interrupts sources to be enabled or disabled.
+  *   This parameter can be the following values:
+  *     @arg IR_INT_TF_EMPTY: When TX FIFO is empty, TX FIFO Empty Interrupt will be triggered.
+  *     @arg IR_INT_TF_LEVEL: When TX FIFO offset <= threshold value, trigger TX FIFO Level Interrupt.
+  *     @arg IR_INT_TF_OF: When TX FIFO is full, data continues to be wrote to TX FIFO, TX FIFO Over interrupt will be triggered.
+  *     @arg IR_INT_TX_FINISH: When TX finished, TX Finish Interrupt will be triggered.
+  *     @arg IR_INT_RF_FULL: When RX FIFO offset = 32, RX FIFO Full Interrupt will be triggered.
+  *     @arg IR_INT_RF_LEVEL: When RX FIFO offset > threshold value, trigger RX FIFO Level Interrupt.
+  *     @arg IR_INT_RX_CNT_OF: When RX counter is overflow, RX counter overflow interrupt will be triggered.
+  *     @arg IR_INT_RF_OF: When RX FIFO is full and continue to be wrote, RX FIFO overflow interrupt will be triggered.
+  *     @arg IR_INT_RX_CNT_THR: When RX counter >= IR_RX_CNT_THR, RX Counter Threshold Interrupt will be triggered.
+  *     @arg IR_INT_RF_ERROR: When RX FIFO is empty and continue to be read, RX FIFO error read interrupt will be triggered.
+  *     @arg IR_INT_RISING_EDGE: When RX FIFO receives a low to high pulse, RX Rising Edge Interrupt will be triggered.
+  *     @arg IR_INT_FALLING_EDGE: When RX FIFO receives a high to low pulse, RX Falling Edge Interrupt will be triggered.
+  * @param  NewState: new state of the specified IR interrupts.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void IR_INTConfig(uint32_t IR_INT, FunctionalState newState)
+{
+    /* Check the parameters */
+    assert_param(IS_IR_INT_CONFIG(IR_INT));
+    assert_param(IS_FUNCTIONAL_STATE(newState));
+
+    if (newState == ENABLE)
+    {
+        if (IR->TX_CONFIG & IR_MODE_SEL_Msk)
+        {
+            /* Enable the selected IR interrupts in RX mode */
+            if (IR_INT & IR_RX_EXTENSION_INT)
+            {
+                IR->RX_EX_INT |= IR_INT & (~IR_RX_EXTENSION_INT);
+            }
+            else
+            {
+                IR->RX_CONFIG |= IR_INT;
+            }
+        }
+        else
+        {
+            if (IR_INT == IR_INT_TX_FINISH)
+            {
+                IR->TX_SR |= IR_INT;
+            }
+            else
+            {
+                /* Enable the selected IR interrupts in TX mode */
+                IR->TX_CONFIG |= IR_INT;
+            }
+        }
+    }
+    else
+    {
+        if (IR->TX_CONFIG & IR_MODE_SEL_Msk)
+        {
+            /* Disable the selected IR interrupts in RX mode */
+            if (IR_INT & IR_RX_EXTENSION_INT)
+            {
+                IR->RX_EX_INT &= ~(IR_INT & 0x03);
+            }
+            else
+            {
+                IR->RX_CONFIG &= (~IR_INT);
+            }
+        }
+        else
+        {
+            if (IR_INT == IR_INT_TX_FINISH)
+            {
+                IR->TX_SR &= (~IR_INT);
+            }
+            else
+            {
+                /* Disable the selected IR interrupts in TX mode */
+                IR->TX_CONFIG &= (~IR_INT);
+            }
+        }
+    }
+}
+
+/**
+  * @brief   Start trigger only in manual receive mode.
+  * @param  None.
+  * @retval None
+  */
+void IR_StartManualRxTrigger(void)
+{
+    /* Start Rx manual mode */
+    IR->RX_CONFIG |= IR_RX_MAN_START_Msk;
+}
+
+/**
+  * @brief   Configure counter threshold value in receiving mode.You can use it to stop receiving IR data.
+  * @param  IR_RxCntThrType:
+  *   This parameter can be the following values:
+  *     @arg IR_RX_Count_Low_Level: Low level counter value >= IR_RxCntThr, trigger IR_INT_RX_CNT_THR interrupt.
+  *     @arg IR_RX_Count_High_Level: High level counter value >= IR_RxCntThr, trigger IR_INT_RX_CNT_THR interrupt.
+  * @param  IR_RxCntThr: Configure IR Rx counter threshold value which can be 0 to 0x7fffffffUL.
+  * @retval None
+  */
+void IR_SetRxCounterThreshold(uint32_t IR_RxCntThrType, uint32_t IR_RxCntThr)
+{
+    /* Check the parameters */
+    assert_param(IS_IR_RX_COUNT_LEVEL_CTRL(IR_RxCntThrType));
+    assert_param(IS_IR_RX_COUNTER_THRESHOLD(IR_RxCntThr));
+
+    /* Configure IR RX counter threshold parameters */
+    IR->RX_CNT_INT_SEL = (IR_RxCntThrType) | (IR_RxCntThr);
+}
+
+/**
+  * @brief  Send data.
+  * @param  buf: data buffer to send.
+  * @param  length: buffer length.
+  * @param IsLastPacket:
+  *   This parameter can be the following values:
+  *     @arg ENABLE: The last data in IR packet and there is no continous data.In other words, an infrared data transmission is completed.
+  *     @arg DISABLE: There is data to be transmitted continuously.
+  * @retval None
+  */
+void IR_SendBuf(const uint32_t *pBuf, uint32_t len, FunctionalState IsLastPacket)
+{
+    uint32_t i = 0;
+
+    /* Check the parameters */
+    assert_param(IS_FUNCTIONAL_STATE(IsLastPacket));
+
+    if (len > 0)
+    {
+        i = len - 1;
+        while (i--)
+        {
+            IR->TX_FIFO = *pBuf++;
+        }
+
+        /* If send the last IR packet, SET the following bit */
+        if (IsLastPacket == ENABLE)
+        {
+            IR->TX_FIFO = (IR_TX_LAST_PACKEET_Msk | *pBuf);
+        }
+        else
+        {
+            IR->TX_FIFO = *pBuf;
+        }
+    }
+}
+
+/**
+  * @brief  Send compensation data.
+  * @param  comp_type: Compensation data type.
+  *     @arg IR_COMPEN_FLAG_1_2_CARRIER: 1/2 carrier freqency.
+  *     @arg IR_COMPEN_FLAG_1_4_CARRIER: 1/4 carrier freqency.
+  *     @arg IR_COMPEN_FLAG_1_N_SYSTEM_CLK: MOD((0x48[27:16]+0x00[11:0]), 4095)/40MHz.
+         User can call function of IR_ConfigCompParam to configure 0x48[27:16].
+  * @param  buf: data buffer to send.
+  * @param  length: buffer length.
+  * @param IsLastPacket:
+  *   This parameter can be the following values:
+  *     @arg ENABLE: The last data in IR packet and there is no continous data.In other words, an infrared data transmission is completed.
+  *     @arg DISABLE: There is data to be transmitted continuously.
+  * @retval None
+  */
+void IR_SendCompenBuf(IR_TX_COMPEN_TYPE comp_type, uint32_t *pBuf, uint32_t len,
+                      FunctionalState IsLastPacket)
+{
+    uint32_t i = 0;
+
+    /* Check the parameters */
+    assert_param(IS_FUNCTIONAL_STATE(IsLastPacket));
+
+    if (len > 0)
+    {
+        i = len - 1;
+        while (i--)
+        {
+            if (*pBuf & IR_DATA_TYPE_Msk)
+            {
+                IR->TX_FIFO = *pBuf++;
+            }
+            else
+            {
+                IR->TX_FIFO = *pBuf++ | comp_type;
+            }
+        }
+
+        /* If send the last IR packet, SET the following bit */
+        if (IsLastPacket == ENABLE)
+        {
+            if (*pBuf & IR_DATA_TYPE_Msk)
+            {
+                IR->TX_FIFO = (IR_TX_LAST_PACKEET_Msk | *pBuf);
+            }
+            else
+            {
+                IR->TX_FIFO = (IR_TX_LAST_PACKEET_Msk | *pBuf | comp_type);
+            }
+        }
+        else
+        {
+            if (*pBuf & IR_DATA_TYPE_Msk)
+            {
+                IR->TX_FIFO = *pBuf;
+            }
+            else
+            {
+                IR->TX_FIFO = *pBuf | comp_type;
+            }
+        }
+    }
+}
+
+/**
+  * @brief  Read data From RX FIO.
+  * @param  buf: buffer address to receive data.
+  * @param  length: read data length.
+  * @retval None
+  */
+void IR_ReceiveBuf(uint32_t *pBuf, uint32_t len)
+{
+    while (len--)
+    {
+        *pBuf++ = IR->RX_FIFO;
+    }
+}
+
+/**
+  * @brief Get the specified IR interrupt status.
+  * @param  IR_INT: the specified IR interrupts.
+  * This parameter can be one of the following values:
+  *     @arg IR_INT_TF_EMPTY: TX FIFO empty interrupt.
+  *     @arg IR_INT_TF_LEVEL: TX FIFO threshold interrupt.
+  *     @arg IR_INT_TF_OF: TX FIFO overflow interrupt.
+  *     @arg IR_INT_RF_FULL: RX FIFO  full interrupt.
+  *     @arg IR_INT_RF_LEVEL: RX FIFO threshold interrupt.
+  *     @arg IR_INT_RX_CNT_OF: RX counter overflow interrupt.
+  *     @arg IR_INT_RF_OF: RX FIFO overflow interrupt.
+  *     @arg IR_INT_RX_CNT_THR: RX counter threshold interrupt.
+  *     @arg IR_INT_RF_ERROR: RX FIFO error read interrupt. Trigger when RX FIFO empty and read RX FIFO.
+  *     @arg IR_INT_RISING_EDGE: IR RX Rising edge interrupt.
+  *     @arg IR_INT_FALLING_EDGE: IR RX Falling edge interrupt.
+  * @retval The new state of IR_INT (SET or RESET).
+  */
+ITStatus IR_GetINTStatus(uint32_t IR_INT)
+{
+    ITStatus bit_status = RESET;
+
+    /* Check the parameters */
+    assert_param(IS_IR_INT_CONFIG(IR_INT));
+
+    if (IR->TX_CONFIG & IR_MODE_SEL_Msk)
+    {
+        /* Get the selected IR interrupts in RX mode */
+        if (IR_INT & IR_RX_EXTENSION_INT)
+        {
+            if ((IR->RX_EX_INT & ((IR_INT & 0x03) << 4)) != (uint32_t)RESET)
+            {
+                bit_status = SET;
+            }
+        }
+        else
+        {
+            if ((IR->RX_SR & IR_INT) != (uint32_t)RESET)
+            {
+                bit_status = SET;
+            }
+        }
+    }
+    else
+    {
+        /* Get the selected IR interrupts in TX mode */
+        if (IR_INT != IR_INT_TF_OF && IR_INT != IR_INT_TX_FINISH)
+        {
+            if ((IR->TX_SR & IR_INT) != (uint32_t)RESET)
+            {
+                bit_status = SET;
+            }
+        }
+        else
+        {
+            if ((IR->TX_SR & (IR_INT >> IR_TX_STATUS_TO_EN_Pos)) != (uint32_t)RESET)
+            {
+                bit_status = SET;
+            }
+        }
+    }
+
+    /* Return the IR_INT status */
+    return  bit_status;
+}
+
+/**
+  * @brief  Clears the IR interrupt pending bits.
+  * @param  IR_IT: specifies the interrupt pending bit to clear.
+  *   This parameter can be any combination of the following values:
+  *     @arg IR_INT_TF_EMPTY_CLR: Clear TX FIFO empty interrupt.
+  *     @arg IR_INT_TF_LEVEL_CLR: Clear TX FIFO threshold interrupt.
+  *     @arg IR_INT_TF_OF_CLR: Clear TX FIFO overflow interrupt.
+  *     @arg IR_INT_RF_FULL_CLR: Clear RX FIFO  full interrupt.
+  *     @arg IR_INT_RF_LEVEL_CLR: Clear RX FIFO threshold interrupt.
+  *     @arg IR_INT_RX_CNT_OF_CLR: Clear RX counter overflow interrupt.
+  *     @arg IR_INT_RF_OF_CLR: Clear RX FIFO overflow interrupt.
+  *     @arg IR_INT_RX_CNT_THR_CLR: Clear RX counter threshold interrupt.
+  *     @arg IR_INT_RF_ERROR_CLR: Clear RX FIFO error read interrupt. Trigger when RX FIFO empty and read RX FIFO.
+  *     @arg IR_INT_RX_RISING_EDGE_CLR: Clear RX Rising edge interrupt.
+  *     @arg IR_INT_RX_FALLING_EDGE_CLR: Clear RX Falling edge interrupt.
+  * @retval None
+  */
+void IR_ClearINTPendingBit(uint32_t IR_CLEAR_INT)
+{
+    /* Check the parameters */
+    assert_param(IS_IR_INT_CLEAR(IR_CLEAR_INT));
+
+    if (IR->TX_CONFIG & IR_MODE_SEL_Msk)
+    {
+        /* Clear the selected IR interrupts in RX mode */
+//        if (IR_CLEAR_INT & IR_RX_EXTENSION_INT)
+//        {
+//            IR->RX_EX_INT |= (IR_CLEAR_INT & 0xC0);
+//        }
+//        else
+//        {
+        IR->RX_INT_CLR |= IR_CLEAR_INT;
+//        }
+    }
+    else
+    {
+        /* Clear the selected IR interrupts in TX mode */
+        IR->TX_INT_CLR |= IR_CLEAR_INT;
+    }
+}
+
+/**
+  * \brief  Store IR register values when system enter DLPS.
+  * \param  PeriReg: Specifies to select the IR peripheral.
+  * \param  StoreBuf: Store buffer to store IR register data.
+  * \return None.
+  */
+DATA_RAM_FUNCTION
+void IR_DLPSEnter(void *PeriReg, void *StoreBuf)
+{
+    IRStoreReg_TypeDef *store_buf = (IRStoreReg_TypeDef *)StoreBuf;
+
+    RCC_PeriphClockCmd(APBPeriph_IR, APBPeriph_IR_CLOCK, ENABLE);
+
+    store_buf->ir_reg[0] = IR->CLK_DIV;
+    store_buf->ir_reg[1] = IR->TX_CONFIG;
+    store_buf->ir_reg[2] = IR->RX_CONFIG;
+    store_buf->ir_reg[3] = IR->RX_CNT_INT_SEL;
+
+    return;
+}
+
+/**
+  * \brief  Restore IR register values when system exit DLPS.
+  * \param  PeriReg: Specifies to select the IR peripheral.
+  * \param  StoreBuf: Restore buffer to restore IR register data.
+  * \return None
+  */
+DATA_RAM_FUNCTION
+void IR_DLPSExit(void *PeriReg, void *StoreBuf)
+{
+    IRStoreReg_TypeDef *store_buf = (IRStoreReg_TypeDef *)StoreBuf;
+
+    RCC_PeriphClockCmd(APBPeriph_IR, APBPeriph_IR_CLOCK, ENABLE);
+
+    IR->CLK_DIV = store_buf->ir_reg[0];
+    if (store_buf->ir_reg[1] & BIT31)
+    {
+        /* RX MODE */
+        IR->TX_CONFIG       = store_buf->ir_reg[1];
+        IR->RX_CONFIG       = store_buf->ir_reg[2];
+        IR->RX_CNT_INT_SEL  = store_buf->ir_reg[3];
+    }
+    else
+    {
+        /* TX MODE */
+        IR->TX_CONFIG  = store_buf->ir_reg[1];
+        /* If IR TX mode is idle, must write one data firstly */
+        IR->TX_FIFO = 0;
+    }
+
+    return;
+}
+
+
diff --git a/bee/drivers/ir/src/device/rtl8752h/rtl876x_ir.h b/bee/drivers/ir/src/device/rtl8752h/rtl876x_ir.h
new file mode 100644
index 00000000..32083208
--- /dev/null
+++ b/bee/drivers/ir/src/device/rtl8752h/rtl876x_ir.h
@@ -0,0 +1,1373 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *               Define to prevent recursive inclusion
+ *============================================================================*/
+#ifndef _RTL876x_IR_H_
+#define _RTL876x_IR_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup  IO          Peripheral Drivers
+ * \defgroup    IR          IR
+ *
+ * \brief       Manage the IR peripheral functions.
+ *
+ * \ingroup     IO
+ */
+
+/*============================================================================*
+ *                        Includes
+ *============================================================================*/
+#include "rtl876x.h"
+
+/*============================================================================*
+ *                         Types
+ *============================================================================*/
+/**
+ * \defgroup    IR_Exported_Types   IR Exported Types
+ * \{
+ * \ingroup     IR
+ */
+
+/**
+ * \brief       IR init structure definition.
+ *
+ * \ingroup     IR_Exported_Types
+ */
+typedef struct
+{
+    uint32_t IR_Clock;              /*!< Specify the source clock frequency, the unit is Hz. */
+    uint32_t IR_Freq;               /*!< Specify the IR carrier frequency, the unit is Hz. */
+    float    IR_DutyCycle;          /*!< Specify the IR duty cycle. */
+    uint32_t IR_Mode;               /*!< Specify the IR mode.
+                                              This parameter can be a value of \ref IR_Mode */
+    uint32_t IR_TxIdleLevel;        /*!< Specify the IR output level in Tx mode
+                                              This parameter can be a value of \ref IR_Idle_Status */
+    uint32_t IR_TxInverse;          /*!< Specify inverse FIFO data or not in TX mode
+                                              This parameter can be a value of \ref IR_TX_Data_Type */
+    uint32_t IR_TxFIFOThrLevel;     /*!< Specify TX FIFO interrupt threshold in TX mode. When TX FIFO depth <= threshold value, trigger interrupt.
+                                              This parameter can be a value of 0 ~ 31. */
+    uint32_t IR_RxStartMode;        /*!< Specify Start mode in RX mode
+                                              This parameter can be a value of \ref IR_Rx_Start_Mode. */
+    uint32_t IR_RxFIFOThrLevel;     /*!< Specify RX FIFO interrupt threshold in RX mode. When RX FIFO depth > threshold value, trigger interrupt.
+                                              This parameter can be a value of 0 ~ 31. */
+    uint32_t IR_RxFIFOFullCtrl;     /*!< Specify data discard mode in RX mode when RX FIFO is full and receiving new data.
+                                              This parameter can be a value of \ref IR_RX_FIFO_DISCARD_SETTING. */
+    uint32_t IR_RxTriggerMode;      /*!< Specify trigger mode in RX mode
+                                              This parameter can be a value of \ref IR_RX_Trigger_Mode. */
+    uint32_t IR_RxFilterTime;       /*!< Specify filter time in RX mode
+                                              This parameter can be a value of \ref IR_RX_Filter_Time. */
+    uint32_t IR_RxCntThrType;       /*!< Specify counter level type when trigger IR_INT_RX_CNT_THR interrupt in RX mode.
+                                              This parameter can be a value of \ref IR_RX_COUNTER_THRESHOLD_TYPE. */
+    uint32_t IR_RxCntThr;           /*!< Specify counter threshold value when trigger IR_INT_RX_CNT_THR interrupt in RX mode. */
+    uint8_t IR_TxDmaEn;             /*!< Specify the TX DMA mode.
+                                              This parameter must be a value of DISABLE and ENABLE. */
+    uint8_t IR_TxWaterLevel;        /*!< Specify the DMA TX water level.
+                                              This parameter must range from 0 to 32.*/
+    uint8_t IR_RxDmaEn;             /*!< Specify the RX DMA mode.
+                                              This parameter must be a value of DISABLE and ENABLE. */
+    uint8_t IR_RxWaterLevel;        /*!< Specify the DMA RX water level.
+                                              This parameter must range from 0 to 32.*/
+} IR_InitTypeDef;
+
+/** End of IR_Exported_Types
+  * \}
+  */
+
+/*============================================================================*
+ *                         Register Defines
+ *============================================================================*/
+
+/* Peripheral: IR */
+/* Description: IR register defines */
+
+/* Register: TX_CONFIG -------------------------------------------------------*/
+/* Description: IR TX CONFIG register. Offset: 0x04. Address: 0x40015804. */
+
+/* TX_CONFIG[31] :IR_MODE_SEL. 0x1: RX mode. 0x0: TX mode. */
+#define IR_MODE_SEL_Pos                 (31UL)
+#define IR_MODE_SEL_Msk                 (0x1UL << IR_MODE_SEL_Pos)
+#define IR_MODE_SEL_CLR                 (~IR_MODE_SEL_Msk)
+/* TX_CONFIG[30] :IR_TX_START. 0x1: Start TX. 0x0: Stop TX. */
+#define IR_TX_START_Pos                 (30UL)
+#define IR_TX_START_Msk                 (0x1UL << IR_TX_START_Pos)
+#define IR_TX_START_CLR                 (~IR_TX_START_Msk)
+/* TX_CONFIG[16] :IR_TX_DUTY_NUM. Duty cycle setting for modulation frequency. */
+/* Example : for 1/3 duty cycle, IR_DUTY_NUM = (IR_DIV_NUM+1)/3 -1. */
+#define IR_TX_DUTY_NUM_Pos              (16UL)
+#define IR_TX_DUTY_NUM_Msk              (0x1FFFUL << IR_TX_DUTY_NUM_Pos)
+/* TX_CONFIG[14] :IR_OUTPUT_INVERSE. 0x1: Inverse  active output. 0x0: Not inverse active output. */
+#define IR_OUTPUT_INVERSE_Pos           (14UL)
+#define IR_OUTPUT_INVERSE_Msk           (0x1UL << IR_OUTPUT_INVERSE_Pos)
+#define IR_OUTPUT_INVERSE_CLR           (~IR_OUTPUT_INVERSE_Msk)
+/* TX_CONFIG[13] :IR_FIFO_INVERSE. 0x1: Inverse FIFO define. 0x0: Not inverse FIFO define. */
+#define IR_FIFO_INVERSE_Pos             (13UL)
+#define IR_FIFO_INVERSE_Msk             (0x1UL << IR_FIFO_INVERSE_Pos)
+#define IR_FIFO_INVERSE_CLR             (~IR_FIFO_INVERSE_Msk)
+/* TX_CONFIG[8] :IR_TX_FIFO_THRESHOLD. TX FIFO interrupt threshold. when TX FIFO depth <= threshold value, trigger interrupt. */
+#define IR_TX_FIFO_THRESHOLD_Pos        (8UL)
+#define IR_TX_FIFO_THRESHOLD_Msk        (0x1fUL << IR_TX_FIFO_THRESHOLD_Pos)
+#define IR_TX_FIFO_THRESHOLD_CLR        (~IR_TX_FIFO_THRESHOLD_Msk)
+/* TX_CONFIG[6] :IR_TX_IDLE_STATE. TX output State in idle. 0x1: High. 0x0: Low. */
+#define IR_TX_IDLE_STATE_Pos            (6UL)
+#define IR_TX_IDLE_STATE_Msk            (0x1UL << IR_TX_IDLE_STATE_Pos)
+#define IR_TX_IDLE_STATE_CLR            (~IR_TX_IDLE_STATE_Msk)
+/* TX_CONFIG[5] :IR_TX_FIFO_OVER_INT_MASK. TX FIFO empty Interrupt. 0x1: Mask. 0x0: Unmask. */
+#define IR_TX_FIFO_OVER_INT_MASK_Pos    (5UL)
+#define IR_TX_FIFO_OVER_INT_MASK_Msk    (0x1UL << IR_TX_FIFO_OVER_INT_MASK_Pos)
+#define IR_TX_FIFO_OVER_INT_MASK_CLR    (~IR_TX_FIFO_OVER_INT_MASK_Msk)
+/* TX_CONFIG[4] :IR_TX_FIFO_OVER_INT_EN. TX FIFO overflow Interrupt. 0x1: Enable. 0x0: Disable. */
+#define IR_TX_FIFO_OVER_INT_EN_Pos      (4UL)
+#define IR_TX_FIFO_OVER_INT_EN_Msk      (0x1UL << IR_TX_FIFO_OVER_INT_EN_Pos)
+#define IR_TX_FIFO_OVER_INT_EN_CLR      (~IR_TX_FIFO_OVER_INT_EN_Msk)
+#define IR_TX_FIFO_OVER_MSK_TO_EN_Pos   (IR_TX_FIFO_OVER_INT_MASK_Pos - IR_TX_FIFO_OVER_INT_EN_Pos)
+/* TX_CONFIG[3] :IR_TX_FIFO_LEVEL_INT_MASK. TX FIFO threshold Interrupt. 0x1: Mask. 0x0: Unmask. */
+#define IR_TX_FIFO_LEVEL_INT_MASK_Pos   (3UL)
+#define IR_TX_FIFO_LEVEL_INT_MASK_Msk   (0x1UL << IR_TX_FIFO_LEVEL_INT_MASK_Pos)
+#define IR_TX_FIFO_LEVEL_INT_MASK_CLR   (~IR_TX_FIFO_LEVEL_INT_MASK_Msk)
+/* TX_CONFIG[2] :IR_TX_FIFO_EMPTY_INT_MASK. TX FIFO empty Interrupt. 0x1: Mask. 0x0: Unmask. */
+#define IR_TX_FIFO_EMPTY_INT_MASK_Pos   (2UL)
+#define IR_TX_FIFO_EMPTY_INT_MASK_Msk   (0x1UL << IR_TX_FIFO_EMPTY_INT_MASK_Pos)
+#define IR_TX_FIFO_EMPTY_INT_MASK_CLR   (~IR_TX_FIFO_EMPTY_INT_MASK_Msk)
+/* TX_CONFIG[1] :IR_TX_FIFO_LEVEL_INT_EN. TX FIFO threshold Interrupt. 0x1: Enable. 0x0: Disable. */
+#define IR_TX_FIFO_LEVEL_INT_EN_Pos     (1UL)
+#define IR_TX_FIFO_LEVEL_INT_EN_Msk     (0x1UL << IR_TX_FIFO_LEVEL_INT_EN_Pos)
+#define IR_TX_FIFO_LEVEL_INT_EN_CLR     (~IR_TX_FIFO_LEVEL_INT_EN_Msk)
+/* TX_CONFIG[0] :IR_TX_FIFO_EMPTY_INT_EN. TX FIFO empty Interrupt. 0x1: Enable. 0x0: Disable. */
+#define IR_TX_FIFO_EMPTY_INT_EN_Pos     (0UL)
+#define IR_TX_FIFO_EMPTY_INT_EN_Msk     (0x1UL << IR_TX_FIFO_EMPTY_INT_EN_Pos)
+#define IR_TX_FIFO_EMPTY_INT_EN_CLR     (~IR_TX_FIFO_EMPTY_INT_EN_Msk)
+#define IR_TX_MSK_TO_EN_Pos             (IR_TX_FIFO_EMPTY_INT_MASK_Pos - IR_TX_FIFO_EMPTY_INT_EN_Pos)
+#define IR_TX_STATUS_TO_EN_Pos          (IR_TX_FIFO_OVER_INT_EN_Pos - IR_TX_FIFO_EMPTY_INT_MASK_Pos)
+
+/* TX_CONFIG[] :IR_TX_FINISH_INT_EN. TX Finish Interrupt. 0x1: Enable. 0x0: Disable. */
+#define IR_TX_FINISH_INT_EN_Pos     (5UL)
+#define IR_TX_FINISH_INT_EN_Msk     (0x1UL << IR_TX_FINISH_INT_EN_Pos)
+#define IR_TX_FINISH_INT_EN_CLR     (~IR_TX_FINISH_INT_EN_Msk)
+
+/* Register: TX_SR -----------------------------------------------------------*/
+/* Description: TX_SR register. Offset: 0x08. Address: 0x40015808. */
+
+/* TX_SR[15] :IR_TX_FIFO_EMPTY. 0x1: empty. 0x0: not empty. */
+#define IR_TX_FIFO_EMPTY_Pos            (15UL)
+#define IR_TX_FIFO_EMPTY_Msk            (0x1UL << IR_TX_FIFO_EMPTY_Pos)
+/* TX_SR[14] :IR_TX_FIFO_FULL. 0x1: full. 0x0: not full. */
+#define IR_TX_FIFO_FULL_Pos             (14UL)
+#define IR_TX_FIFO_FULL_Msk             (0x1UL << IR_TX_FIFO_FULL_Pos)
+/* TX_SR[13:8] :IR_TX_FIFO_OFFSET. */
+#define IR_TX_FIFO_OFFSET_Pos           (8UL)
+#define IR_TX_FIFO_OFFSET_Msk           (0x7fUL << IR_TX_FIFO_OFFSET_Pos)
+/* TX_SR[4] :IR_TX_STATUS. */
+#define IR_TX_STATUS_Pos                (4UL)
+#define IR_TX_STATUS_Msk                (0x1UL << IR_TX_STATUS_Pos)
+/* TX_SR[2] :IR_TX_FIFO_OVER_INT_STATUS. */
+#define IR_TX_FIFO_OVER_INT_STATUS_Pos  (2UL)
+#define IR_TX_FIFO_OVER_INT_STATUS_Msk  (0x1UL << IR_TX_FIFO_OVER_INT_STATUS_Pos)
+/* TX_SR[1] :IR_TX_FIFO_LEVEL_INT_STATUS. */
+#define IR_TX_FIFO_LEVEL_INT_STATUS_Pos (1UL)
+#define IR_TX_FIFO_LEVEL_INT_STATUS_Msk (0x1UL << IR_TX_FIFO_LEVEL_INT_STATUS_Pos)
+/* TX_SR[0] :IR_TX_FIFO_EMPTY_INT_STATUS. */
+#define IR_TX_FIFO_EMPTY_INT_STATUS_Pos (0UL)
+#define IR_TX_FIFO_EMPTY_INT_STATUS_Msk (0x1UL << IR_TX_FIFO_EMPTY_INT_STATUS_Pos)
+
+/* Register: TX_INT_CLR -----------------------------------------------------------*/
+/* Description: TX_INT_CLR register. Offset: 0x10. Address: 0x40015810. */
+/* TX_INT_CLR[4] :IR_TX_FINISH_CLR. Write 1 clear. */
+#define IR_TX_FINISH_INT_CLR_Pos     (4UL)
+#define IR_TX_FINISH_INT_CLR_Msk     (0x1UL << IR_TX_FINISH_INT_CLR_Pos)
+/* TX_INT_CLR[3] :IR_TX_FIFO_OVER_INT_CLR. Write 1 clear. */
+#define IR_TX_FIFO_OVER_INT_CLR_Pos     (3UL)
+#define IR_TX_FIFO_OVER_INT_CLR_Msk     (0x1UL << IR_TX_FIFO_OVER_INT_CLR_Pos)
+/* TX_INT_CLR[2] :IR_TX_FIFO_LEVEL_INT_CLR. Write 1 clear. */
+#define IR_TX_FIFO_LEVEL_INT_CLR_Pos    (2UL)
+#define IR_TX_FIFO_LEVEL_INT_CLR_Msk    (0x1UL << IR_TX_FIFO_LEVEL_INT_CLR_Pos)
+/* TX_INT_CLR[1] :IR_TX_FIFO_EMPTY_INT_CLR. Write 1 clear. */
+#define IR_TX_FIFO_EMPTY_INT_CLR_Pos    (1UL)
+#define IR_TX_FIFO_EMPTY_INT_CLR_Msk    (0x1UL << IR_TX_FIFO_EMPTY_INT_CLR_Pos)
+/* TX_INT_CLR[0] :IR_TX_FIFO_CLR. Write 1 clear. */
+#define IR_TX_FIFO_CLR_Pos              (0UL)
+#define IR_TX_FIFO_CLR_Msk              (0x1UL << IR_TX_FIFO_CLR_Pos)
+
+#define IR_INT_ALL_CLR                  (IR_TX_FIFO_OVER_INT_CLR_Msk | \
+                                         IR_TX_FIFO_LEVEL_INT_CLR_Msk | \
+                                         IR_TX_FIFO_EMPTY_INT_CLR_Msk)
+
+/* Register: TX_FIFO ---------------------------------------------------------*/
+/* Description: TX_FIFO register. Offset: 0x14. Address: 0x40015814. */
+
+/* TX_FIFO[31] :IR_DATA_TYPE. 0x1: active carrier. 0x0: incative carrier. */
+#define IR_DATA_TYPE_Pos                (31UL)
+#define IR_DATA_TYPE_Msk                (0x1UL << IR_DATA_TYPE_Pos)
+#define IR_DATA_TYPE_CLR                (~IR_DATA_TYPE_Msk)
+/* TX_FIFO[30] :IR_TX_LAST_PACKEET. 0x1: last packet. 0x0: normal packet. */
+#define IR_TX_LAST_PACKEET_Pos          (30UL)
+#define IR_TX_LAST_PACKEET_Msk          (0x1UL << IR_TX_LAST_PACKEET_Pos)
+#define IR_TX_LAST_PACKEET_CLR          (~IR_TX_LAST_PACKEET_Msk)
+/* TX_FIFO[29:28] :IR_LOW_PERIOD_COMPENSATION */
+#define IR_LOW_PERIOD_COMPENSATION_Pos  (28UL)
+#define IR_LOW_PERIOD_COMPENSATION_Msk  (0x3UL << IR_LOW_PERIOD_COMPENSATION_Pos)
+#define IR_LOW_PERIOD_COMPENSATION_CLR  (~IR_LOW_PERIOD_COMPENSATION_Msk)
+
+/* Register: RX_CONFIG ------------------------------------------------------*/
+/* Description: IR RX CONFIG register. Offset: 0x18. Address: 0x40015818. */
+
+/* RX_CONFIG[28] :IR_RX_START. 0x1: Run. 0x0: Stop. */
+#define IR_RX_START_Pos                 (28UL)
+#define IR_RX_START_Msk                 (0x1UL << IR_RX_START_Pos)
+#define IR_RX_START_CLR                 (~IR_RX_START_Msk)
+/* RX_CONFIG[27] :IR_RX_START_MODE. 0x1: auto mode. 0x0: manual mode. */
+#define IR_RX_START_MODE_Pos            (27UL)
+#define IR_RX_START_MODE_Msk            (0x1UL << IR_RX_START_MODE_Pos)
+#define IR_RX_START_MODE_CLR            (~IR_RX_START_MODE_Msk)
+/* RX_CONFIG[26] :IR_RX_MAN_START. 0x1: Start check waveform. */
+#define IR_RX_MAN_START_Pos             (26UL)
+#define IR_RX_MAN_START_Msk             (0x1UL << IR_RX_MAN_START_Pos)
+#define IR_RX_MAN_START_CLR             (~IR_RX_MAN_START_Msk)
+/* RX_CONFIG[24] :IR_TRIGGER_MODE. 0x1: Run. */
+/* 0x0: high->low  trigger. 0x1: low->high trigger. 0x02: high->low  or low->high trigger. */
+#define IR_TRIGGER_MODE_Pos             (24UL)
+#define IR_TRIGGER_MODE_Msk             (0x3UL << IR_TRIGGER_MODE_Pos)
+#define IR_TRIGGER_MODE_CLR             (~IR_TRIGGER_MODE_Msk)
+/* RX_CONFIG[21] :IR_FILTER_TIME. */
+#define IR_FILTER_TIME_Pos              (21UL)
+#define IR_FILTER_TIME_Msk              (0x3UL << IR_FILTER_TIME_Pos)
+#define IR_FILTER_TIME_CLR              (~IR_FILTER_TIME_Msk)
+/* RX_CONFIG[19] :IR_RX_FIFO_ERROR_MASK_INT. 0x1: mask. 0x0: unmask.*/
+#define IR_RX_FIFO_ERROR_MASK_INT_Pos   (19UL)
+#define IR_RX_FIFO_ERROR_MASK_INT_Msk   (0x1UL << IR_RX_FIFO_ERROR_MASK_INT_Pos)
+#define IR_RX_FIFO_ERROR_MASK_INT_CLR   (~IR_RX_FIFO_ERROR_MASK_INT_Msk)
+/* RX_CONFIG[18] :IR_RX_CNT_THR_MASK_INT. 0x1: enable. 0x0: disable.*/
+#define IR_RX_CNT_THR_MASK_INT_Pos      (18UL)
+#define IR_RX_CNT_THR_MASK_INT_Msk      (0x1UL << IR_RX_CNT_THR_MASK_INT_Pos)
+#define IR_RX_CNT_THR_MASK_INT_CLR      (~IR_RX_CNT_THR_MASK_INT_Msk)
+/* RX_CONFIG[17] :IR_RX_FIFO_OF_MASK_INT. 0x1: enable. 0x0: disable.*/
+#define IR_RX_FIFO_OF_MASK_INT_Pos      (17UL)
+#define IR_RX_FIFO_OF_MASK_INT_Msk      (0x1UL << IR_RX_FIFO_OF_MASK_INT_Pos)
+#define IR_RX_FIFO_OF_MASK_INT_CLR      (~IR_RX_FIFO_OF_MASK_INT_Msk)
+/* RX_CONFIG[16] :IR_RX_CNT_OF_MASK_INT. 0x1: enable. 0x0: disable.*/
+#define IR_RX_CNT_OF_MASK_INT_Pos       (16UL)
+#define IR_RX_CNT_OF_MASK_INT_Msk       (0x1UL << IR_RX_CNT_OF_MASK_INT_Pos)
+#define IR_RX_CNT_OF_MASK_INT_CLR       (~IR_RX_CNT_OF_MASK_INT_Msk)
+/* RX_CONFIG[15] :IR_RX_FIFO_LEVEL_MASK_INT. 0x1: enable. 0x0: disable.*/
+#define IR_RX_FIFO_LEVEL_MASK_INT_Pos   (15UL)
+#define IR_RX_FIFO_LEVEL_MASK_INT_Msk   (0x1UL << IR_RX_FIFO_LEVEL_MASK_INT_Pos)
+#define IR_RX_FIFO_LEVEL_MASK_INT_CLR   (~IR_RX_FIFO_LEVEL_MASK_INT_Msk)
+/* RX_CONFIG[14] :IR_RX_FIFO_FULL_MASK_INT. 0x1: enable. 0x0: disable.*/
+#define IR_RX_FIFO_FULL_MASK_INT_Pos    (14UL)
+#define IR_RX_FIFO_FULL_MASK_INT_Msk    (0x1UL << IR_RX_FIFO_FULL_MASK_INT_Pos)
+#define IR_RX_FIFO_FULL_MASK_INT_CLR    (~IR_RX_FIFO_FULL_MASK_INT_Msk)
+/* RX_CONFIG[13] :IR_RX_FIFO_DISCARD_SET. 0x1: reject new data send to FIFO. 0x0: discard oldest data in FIFO.*/
+#define IR_RX_FIFO_DISCARD_SET_Pos      (13UL)
+#define IR_RX_FIFO_DISCARD_SET_Msk      (0x1UL << IR_RX_FIFO_DISCARD_SET_Pos)
+#define IR_RX_FIFO_DISCARD_SET_CLR      (~IR_RX_FIFO_DISCARD_SET_Msk)
+/* RX_CONFIG[7] :IR_RX_FIFO_LEVE. */
+#define IR_RX_FIFO_LEVEL_Pos            (8UL)
+#define IR_RX_FIFO_LEVEL_Msk            (0x1fUL << IR_RX_FIFO_LEVEL_Pos)
+#define IR_RX_FIFO_LEVEL_CLR            (~IR_RX_FIFO_LEVEL_Msk)
+/* RX_CONFIG[5] :IR_RX_FIFO_ERROR_INT. 0x1: enable. 0x0: disable.*/
+#define IR_RX_FIFO_ERROR_INT_Pos        (5UL)
+#define IR_RX_FIFO_ERROR_INT_Msk        (0x1UL << IR_RX_FIFO_ERROR_INT_Pos)
+#define IR_RX_FIFO_ERROR_INT_CLR        (~IR_RX_FIFO_ERROR_INT_Msk)
+/* RX_CONFIG[4] :IR_RX_CNT_THR_INT. 0x1: enable. 0x0: disable.*/
+#define IR_RX_CNT_THR_INT_Pos           (4UL)
+#define IR_RX_CNT_THR_INT_Msk           (0x1UL << IR_RX_CNT_THR_INT_Pos)
+#define IR_RX_CNT_THR_INT_CLR           (~IR_RX_CNT_THR_INT_Msk)
+/* RX_CONFIG[3] :IR_RX_FIFO_OF_INT. 0x1: enable. 0x0: disable.*/
+#define IR_RX_FIFO_OF_INT_Pos           (3UL)
+#define IR_RX_FIFO_OF_INT_Msk           (0x1UL << IR_RX_FIFO_OF_INT_Pos)
+#define IR_RX_FIFO_OF_INT_CLR           (~IR_RX_FIFO_OF_INT_Msk)
+/* RX_CONFIG[2] :IR_RX_CNT_OF_INT. 0x1: enable. 0x0: disable.*/
+#define IR_RX_CNT_OF_INT_Pos            (2UL)
+#define IR_RX_CNT_OF_INT_Msk            (0x1UL << IR_RX_CNT_OF_INT_Pos)
+#define IR_RX_CNT_OF_INT_CLR            (~IR_RX_CNT_OF_INT_Msk)
+/* RX_CONFIG[1] :IR_RX_FIFO_LEVEL_INT. 0x1: enable. 0x0: disable.*/
+#define IR_RX_FIFO_LEVEL_INT_Pos        (1UL)
+#define IR_RX_FIFO_LEVEL_INT_Msk        (0x1UL << IR_RX_FIFO_LEVEL_INT_Pos)
+#define IR_RX_FIFO_LEVEL_INT_CLR        (~IR_RX_FIFO_LEVEL_INT_Msk)
+/* RX_CONFIG[0] :IR_RX_FIFO_FULL_INT. 0x1: enable. 0x0: disable.*/
+#define IR_RX_FIFO_FULL_INT_Pos         (0UL)
+#define IR_RX_FIFO_FULL_INT_Msk         (0x1UL << IR_RX_FIFO_FULL_INT_Pos)
+#define IR_RX_FIFO_FULL_INT_CLR         (~IR_RX_FIFO_FULL_INT_Msk)
+#define IR_RX_MSK_TO_EN_Pos             (IR_RX_FIFO_FULL_MASK_INT_Pos - IR_RX_FIFO_FULL_INT_Pos)
+
+#define IR_RX_MASK_ALL_INT              (IR_RX_FIFO_ERROR_MASK_INT_Msk | IR_RX_CNT_THR_MASK_INT_Msk | \
+                                         IR_RX_FIFO_OF_MASK_INT_Msk | IR_RX_CNT_OF_MASK_INT_Msk | \
+                                         IR_RX_FIFO_LEVEL_MASK_INT_Msk | IR_RX_FIFO_FULL_MASK_INT_Msk)
+
+/* Register: RX_SR -----------------------------------------------------------*/
+/* Description: RX_SR register. Offset: 0x1C. Address: 0x4001581C. */
+
+/* RX_SR[17] :IR_TX_FIFO_EMPTY. 0x1: empty. 0x0: not empty. */
+#define IR_RX_FIFO_EMPTY_Pos            (17UL)
+#define IR_RX_FIFO_EMPTY_Msk            (0x1UL << IR_RX_FIFO_EMPTY_Pos)
+/* RX_SR[16] :IR_TX_FIFO_FULL. 0x1: full. 0x0: not full. */
+#define IR_RX_FIFO_FULL_Pos            (16UL)
+#define IR_RX_FIFO_FULL_Msk            (0x1UL << IR_RX_FIFO_FULL_Pos)
+/* RX_SR[8] :IR_RX_FIFO_OFFSET. */
+#define IR_RX_FIFO_OFFSET_Pos           (8UL)
+#define IR_RX_FIFO_OFFSET_Msk           (0x7fUL << IR_RX_FIFO_OFFSET_Pos)
+#define IR_RX_FIFO_OFFSET_CLR           (~IR_RX_FIFO_OFFSET_Msk)
+/* RX_SR[7] :IR_RX_STATUS. */
+#define IR_RX_STATUS_Pos                (7UL)
+#define IR_RX_STATUS_Msk                (0x1UL << IR_RX_STATUS_Pos)
+
+/* Register: RX_INT_CLR -----------------------------------------------------------*/
+/* Description: RX_INT_CLR register. Offset: 0x20. Address: 0x40015820. */
+
+/* RX_INT_CLR[8] :IR_RX_FIFO_CLR. Write 1 clear. */
+#define IR_RX_FIFO_CLR_Pos              (8UL)
+#define IR_RX_FIFO_CLR_Msk              (0x1UL << IR_RX_FIFO_CLR_Pos)
+/* RX_INT_CR[7] :IR_RX_RISING_EDGE_INT_CLR. */
+#define IR_RX_RISING_EDGE_INT_CLR_Pos       (7UL)
+#define IR_RX_RISING_EDGE_INT_CLR_Msk       (0x1UL << IR_RX_RISING_EDGE_INT_CLR_Pos)
+#define IR_RX_RISING_EDGE_INT_CLR_CLR       (~IR_RX_RISING_EDGE_INT_CLR_Msk)
+/* RX_INT_CR[6] :IR_RX_FALLING_EDGE_INT_CLR. */
+#define IR_RX_FALLING_EDGE_INT_CLR_Pos      (6UL)
+#define IR_RX_FALLING_EDGE_INT_CLR_Msk      (0x1UL << IR_RX_FALLING_EDGE_INT_CLR_Pos)
+#define IR_RX_FALLING_EDGE_INT_CLR_CLR      (~IR_RX_FALLING_EDGE_INT_CLR_Msk)
+/* RX_INT_CLR[5] :IR_RX_FIFO_ERROR_INT_CLR. Write 1 clear. */
+#define IR_RX_FIFO_ERROR_INT_CLR_Pos    (5UL)
+#define IR_RX_FIFO_ERROR_INT_CLR_Msk    (0x1UL << IR_RX_FIFO_ERROR_INT_CLR_Pos)
+/* RX_INT_CLR[4] :IR_RX_CNT_THR_INT_CLR. Write 1 clear. */
+#define IR_RX_CNT_THR_INT_CLR_Pos       (4UL)
+#define IR_RX_CNT_THR_INT_CLR_Msk       (0x1UL << IR_RX_CNT_THR_INT_CLR_Pos)
+/* RX_INT_CLR[3] :IR_RX_FIFO_OF_INT_CLR. Write 1 clear. */
+#define IR_RX_FIFO_OF_INT_CLR_Pos       (3UL)
+#define IR_RX_FIFO_OF_INT_CLR_Msk       (0x1UL << IR_RX_FIFO_OF_INT_CLR_Pos)
+/* RX_INT_CLR[2] :IR_RX_CNT_OF_INT_CLR. Write 1 clear. */
+#define IR_RX_CNT_OF_INT_CLR_Pos        (2UL)
+#define IR_RX_CNT_OF_INT_CLR_Msk        (0x1UL << IR_RX_CNT_OF_INT_CLR_Pos)
+/* RX_INT_CLR[1] :IR_RX_FIFO_LEVEL_INT_CLR. Write 1 clear. */
+#define IR_RX_FIFO_LEVEL_INT_CLR_Pos    (1UL)
+#define IR_RX_FIFO_LEVEL_INT_CLR_Msk    (0x1UL << IR_RX_FIFO_LEVEL_INT_CLR_Pos)
+/* RX_INT_CLR[0] :IR_RX_FIFO_FULL_INT_CLR. Write 1 clear. */
+#define IR_RX_FIFO_FULL_INT_CLR_Pos     (0UL)
+#define IR_RX_FIFO_FULL_INT_CLR_Msk     (0x1UL << IR_RX_FIFO_FULL_INT_CLR_Pos)
+
+#define IR_RX_INT_ALL_CLR               (IR_RX_FIFO_CLR_Msk | IR_RX_FIFO_ERROR_INT_CLR_Msk | \
+                                         IR_RX_CNT_THR_INT_CLR_Msk | IR_RX_FIFO_OF_INT_CLR_Msk | \
+                                         IR_RX_CNT_OF_INT_CLR_Msk | IR_RX_FIFO_LEVEL_INT_CLR_Msk | \
+                                         IR_RX_FIFO_FULL_INT_CLR_Msk|IR_RX_RISING_EDGE_INT_CLR_Msk|IR_RX_FALLING_EDGE_INT_CLR_Msk)
+
+/* Register: RX_CNT_INT_SEL -------------------------------------------------*/
+/* Description: IR RX counter interrupt setting register. Offset: 0x24. Address: 0x40015824. */
+
+/* RX_CNT_INT_SEL[31] :IR_RX_CNT_THR_TRIGGER_LV. */
+/* 0x1: high level couner >= threshlod trigger interrupt. 0x0: low level couner >= threshlod trigger interrupt. */
+#define IR_RX_CNT_THR_TYPE_Pos          (31UL)
+#define IR_RX_CNT_THR_TYPE_Msk          (0x1UL << IR_RX_CNT_THR_TYPE_Pos)
+#define IR_RX_CNT_THR_TYPE_CLR          (~IR_RX_CNT_THR_TYPE_Msk)
+/* RX_CNT_INT_SEL[30:0] :IR_RX_CNT_THR. */
+#define IR_RX_CNT_THR_Pos               (0UL)
+#define IR_RX_CNT_THR_Msk               (0x7fffffffUL << IR_RX_CNT_THR_Pos)
+#define IR_RX_CNT_THR_CLR               (~IR_RX_CNT_THR_Msk)
+
+/* Register: RX_INT_CR -------------------------------------------------*/
+/* Description: IR RX interrupt config register. Offset: 0x34. Address: 0x40015834. */
+
+/* RX_INT_CR[5] :IR_RX_RISING_EDGE_INT_STATUS. */
+#define IR_RX_RISING_EDGE_INT_STATUS_Pos    (5UL)
+#define IR_RX_RISING_EDGE_INT_STATUS_Msk    (0x1UL << IR_RX_RISING_EDGE_INT_STATUS_Pos)
+#define IR_RX_RISING_EDGE_INT_STATUS_CLR    (~IR_RX_RISING_EDGE_INT_STATUS_Msk)
+/* RX_INT_CR[4] :IR_RX_FALLING_EDGE_INT_STATUS. */
+#define IR_RX_FALLING_EDGE_INT_STATUS_Pos   (4UL)
+#define IR_RX_FALLING_EDGE_INT_STATUS_Msk   (0x1UL << IR_RX_FALLING_EDGE_INT_STATUS_Pos)
+#define IR_RX_FALLING_EDGE_INT_STATUS_CLR   (~IR_RX_FALLING_EDGE_INT_STATUS_Msk)
+/* RX_INT_CR[3] :IR_RX_RISING_EDGE_INT_MASK. */
+#define IR_RX_RISING_EDGE_INT_MASK_Pos      (3UL)
+#define IR_RX_RISING_EDGE_INT_MASK_Msk      (0x1UL << IR_RX_RISING_EDGE_INT_MASK_Pos)
+#define IR_RX_RISING_EDGE_INT_MASK_CLR      (~IR_RX_RISING_EDGE_INT_MASK_Msk)
+/* RX_INT_CR[2] :IR_RX_FALLING_EDGE_INT_MASK. */
+#define IR_RX_FALLING_EDGE_INT_MASK_Pos     (2UL)
+#define IR_RX_FALLING_EDGE_INT_MASK_Msk     (0x1UL << IR_RX_FALLING_EDGE_INT_MASK_Pos)
+#define IR_RX_FALLING_EDGE_INT_MASK_CLR     (~IR_RX_FALLING_EDGE_INT_MASK_Msk)
+/* RX_INT_CR[1] :IR_RX_RISING_EDGE_INT_EN. */
+#define IR_RX_RISING_EDGE_INT_EN_Pos        (1UL)
+#define IR_RX_RISING_EDGE_INT_EN_Msk        (0x1UL << IR_RX_RISING_EDGE_INT_EN_Pos)
+#define IR_RX_RISING_EDGE_INT_EN_CLR        (~IR_RX_RISING_EDGE_INT_EN_Msk)
+/* RX_INT_CR[0] :IR_RX_FALLING_EDGE_INT_EN. */
+#define IR_RX_FALLING_EDGE_INT_EN_Pos       (0UL)
+#define IR_RX_FALLING_EDGE_INT_EN_Msk       (0x1UL << IR_RX_FALLING_EDGE_INT_EN_Pos)
+#define IR_RX_FALLING_EDGE_INT_EN_CLR       (~IR_RX_FALLING_EDGE_INT_EN_Msk)
+
+#define IR_RX_EXTENSION_INT                 0x8000
+
+/* Register: DMA_CONFIG -------------------------------------------------*/
+/* Description: IR dma config register. Offset: 0x50. Address: 0x40015850. */
+
+/* DMA_CONFIG[0] : IR_TX_DMA_ENABLE. */
+#define IR_TX_DMA_EN_Pos                (0UL)
+#define IR_TX_DMA_EN_Msk                (0x1UL << IR_TX_DMA_EN_Pos)
+#define IR_TX_DMA_EN_CLR                (~IR_TX_DMA_EN_Msk)
+/* DMA_CONFIG[6:1] : IR_TX_WATER_LEVEL. */
+#define IR_TX_WATER_LEVEL_Pos           (1UL)
+#define IR_TX_WATER_LEVEL_Msk           (0x3FUL << IR_TX_WATER_LEVEL_Pos)
+#define IR_TX_WATER_LEVEL_CLR           (~IR_TX_WATER_LEVEL_Msk)
+/* DMA_CONFIG[8] : IR_RX_DMA_ENABLE. */
+#define IR_RX_DMA_EN_Pos                (8UL)
+#define IR_RX_DMA_EN_Msk                (0x1UL << IR_RX_DMA_EN_Pos)
+#define IR_RX_DMA_EN_CLR                (~IR_RX_DMA_EN_Msk)
+/* DMA_CONFIG[14:9] : IR_RX_WATER_LEVEL. */
+#define IR_RX_WATER_LEVEL_Pos           (9UL)
+#define IR_RX_WATER_LEVEL_Msk           (0x3FUL << IR_RX_WATER_LEVEL_Pos)
+#define IR_RX_WATER_LEVEL_CLR           (~IR_RX_WATER_LEVEL_Msk)
+
+
+/*============================================================================*
+ *                         Constants
+ *============================================================================*/
+/**
+ * \defgroup    IR_Exported_Constants   IR Exported Constants
+ * \{
+ * \ingroup     IR
+ */
+
+/**
+ * \defgroup    IR_Config    IR Config
+ * \{
+ * \ingroup     IR_Exported_Constants
+ */
+#define IS_IR_PERIPH(PERIPH) ((PERIPH) == IR)
+/** \} */
+
+/**
+ * \defgroup    IR_FIFO_SIZE    IR FIFO SIZE
+ * \{
+ * \ingroup     IR_Exported_Constants
+ */
+#define IR_TX_FIFO_SIZE                   32
+#define IR_RX_FIFO_SIZE                   32
+/** \} */
+
+/**
+ * \defgroup    IR_Clock    IR Clock
+ * \{
+ * \ingroup     IR_Exported_Constants
+ */
+#define IR_CLOCK_40M                                (40000000)
+#define IR_CLOCK_90M                                (90000000)
+#define IR_CLOCK_100M                               (100000000)
+
+#define IS_IR_CLOCK(CLK) (((CLK) == IR_CLOCK_40M)\
+                          || ((CLK) == IR_CLOCK_90M)\
+                          || ((CLK) == IR_CLOCK_100M))
+
+#define IS_IR_FREQUENCY_40M(F) (((F) >= 2442) && ((F) <= 2000000))
+#define IS_IR_FREQUENCY_90M(F) (((F) >= 5494) && ((F) <= 2000000))
+#define IS_IR_FREQUENCY_100M(F) (((F) >= 6104) && ((F) <= 2000000))
+/** \} */
+
+/**
+ * \defgroup    IR_Mode IR Mode
+ * \{
+ * \ingroup     IR_Exported_Constants
+ */
+#define IR_MODE_TX                                  ((uint32_t)((uint32_t)0x0 << IR_MODE_SEL_Pos))
+#define IR_MODE_RX                                  ((uint32_t)((uint32_t)0x1 << IR_MODE_SEL_Pos))
+
+#define IS_IR_MODE(MODE) (((MODE) == IR_MODE_TX) || ((MODE) == IR_MODE_RX))
+/** \} */
+
+/**
+ * \defgroup    IR_Idle_Status IR Idle Status
+ * \{
+ * \ingroup     IR_Exported_Constants
+ */
+
+#define IR_IDLE_OUTPUT_HIGH                         ((uint32_t)(0x01 << IR_TX_IDLE_STATE_Pos))
+#define IR_IDLE_OUTPUT_LOW                          ((uint32_t)(0x00 << IR_TX_IDLE_STATE_Pos))
+
+#define IS_IR_IDLE_STATUS(LEVEL) (((LEVEL) == IR_IDLE_OUTPUT_HIGH) || ((LEVEL) == IR_IDLE_OUTPUT_LOW))
+/** \} */
+
+/**
+ * \defgroup    IR_TX_Data_Type IR TX Data Type
+ * \{
+ * \ingroup     IR_Exported_Constants
+ */
+
+#define IR_TX_DATA_NORMAL                           ((uint32_t)(0 << IR_FIFO_INVERSE_Pos))
+#define IR_TX_DATA_INVERSE                          ((uint32_t)(1 << IR_FIFO_INVERSE_Pos))
+
+#define IS_IR_TX_DATA_TYPE(TYPE) (((TYPE) == IR_TX_DATA_NORMAL) || ((TYPE) == IR_TX_DATA_INVERSE))
+/** \} */
+
+/**
+ * \defgroup     IR_TX_Threshold IR TX Threshold
+ * \{
+ * \ingroup     IR_Exported_Constants
+ */
+#define IS_IR_TX_THRESHOLD(THD)  ((THD) < IR_TX_FIFO_SIZE)
+/** \} */
+
+/**
+ * \defgroup     IR_RX_Threshold IR RX Threshold
+ * \{
+ * \ingroup     IR_Exported_Constants
+ */
+#define IS_IR_RX_THRESHOLD(THD) ((THD) < IR_RX_FIFO_SIZE)
+/** \} */
+
+/**
+ * \defgroup    IR_RX_Start_Mode IR RX Start Mode
+ * \{
+ * \ingroup     IR_Exported_Constants
+ */
+#define IR_RX_AUTO_MODE                             ((uint32_t)((0x1) << IR_RX_START_MODE_Pos))
+#define IR_RX_MANUAL_MODE                           ((uint32_t)((0x0) << IR_RX_START_MODE_Pos))
+
+#define IS_RX_START_MODE(MODE) (((MODE) == IR_RX_AUTO_MODE) || ((MODE) == IR_RX_MANUAL_MODE))
+/** \} */
+
+/**
+ * \defgroup    IR_RX_Trigger_Mode IR RX Trigger Mode
+ * \{
+ * \ingroup     IR_Exported_Constants
+ */
+#define IR_RX_FALL_EDGE                             ((uint32_t)((0x0) << IR_TRIGGER_MODE_Pos))
+#define IR_RX_RISING_EDGE                           ((uint32_t)((0x1) << IR_TRIGGER_MODE_Pos))
+#define IR_RX_DOUBLE_EDGE                           ((uint32_t)((0x2) << IR_TRIGGER_MODE_Pos))
+
+#define IS_RX_RX_TRIGGER_EDGE(EDGE) (((EDGE) == IR_RX_FALL_EDGE) || ((EDGE) == IR_RX_RISING_EDGE) || ((EDGE) == IR_RX_DOUBLE_EDGE))
+/** \} */
+
+/**
+ * \defgroup    IR_RX_FIFO_DISCARD_SETTING IR RX FIFO Discard Setting
+ * \{
+ * \ingroup     IR_Exported_Constants
+ */
+
+#define IR_RX_FIFO_FULL_DISCARD_NEWEST              ((uint32_t)(0 << IR_RX_FIFO_DISCARD_SET_Pos))
+#define IR_RX_FIFO_FULL_DISCARD_OLDEST              ((uint32_t)(1 << IR_RX_FIFO_DISCARD_SET_Pos))
+
+#define IS_IR_RX_FIFO_FULL_CTRL(CTRL)  (((CTRL) == IR_RX_FIFO_FULL_DISCARD_NEWEST) || ((CTRL) == IR_RX_FIFO_FULL_DISCARD_OLDEST))
+/** \} */
+
+/**
+ * \defgroup    IR_RX_Filter_Time IR RX Filter Time
+ * \{
+ * \ingroup     IR_Exported_Constants
+ */
+#define IR_RX_FILTER_TIME_50ns                      ((uint32_t)((0x0) << IR_FILTER_TIME_Pos))
+#define IR_RX_FILTER_TIME_75ns                      ((uint32_t)((0x2) << IR_FILTER_TIME_Pos))
+#define IR_RX_FILTER_TIME_100ns                     ((uint32_t)((0x3) << IR_FILTER_TIME_Pos))
+#define IR_RX_FILTER_TIME_125ns                     ((uint32_t)((0x4) << IR_FILTER_TIME_Pos))
+#define IR_RX_FILTER_TIME_150ns                     ((uint32_t)((0x5) << IR_FILTER_TIME_Pos))
+#define IR_RX_FILTER_TIME_175ns                     ((uint32_t)((0x6) << IR_FILTER_TIME_Pos))
+#define IR_RX_FILTER_TIME_200ns                     ((uint32_t)((0x7) << IR_FILTER_TIME_Pos))
+
+#define IS_IR_RX_FILTER_TIME_CTRL(CTRL)  (((CTRL) == IR_RX_FILTER_TIME_50ns) || \
+                                          ((CTRL) == IR_RX_FILTER_TIME_75ns) || \
+                                          ((CTRL) == IR_RX_FILTER_TIME_100ns) || \
+                                          ((CTRL) == IR_RX_FILTER_TIME_125ns) || \
+                                          ((CTRL) == IR_RX_FILTER_TIME_150ns) || \
+                                          ((CTRL) == IR_RX_FILTER_TIME_175ns) || \
+                                          ((CTRL) == IR_RX_FILTER_TIME_200ns))
+/** \} */
+
+/**
+ * \defgroup    IR_RX_COUNTER_THRESHOLD_TYPE IR RX Counter Threshold Type
+ * \{
+ * \ingroup     IR_Exported_Constants
+ */
+
+#define IR_RX_Count_Low_Level                       ((uint32_t)0 << IR_RX_CNT_THR_TYPE_Pos)
+#define IR_RX_Count_High_Level                      ((uint32_t)1 << IR_RX_CNT_THR_TYPE_Pos)
+
+#define IS_IR_RX_COUNT_LEVEL_CTRL(CTRL)  (((CTRL) == IR_RX_Count_Low_Level) || ((CTRL) == IR_RX_Count_High_Level))
+/** \} */
+
+/**
+ * \defgroup    IR_RX_Counter_Threshold IR RX Counter Threshold
+ * \{
+ * \ingroup     IR_Exported_Constants
+ */
+#define IS_IR_RX_COUNTER_THRESHOLD(THD) ((THD) <= IR_RX_CNT_THR_Msk)
+/** \} */
+
+/**
+ * \defgroup    IR_Interrupt_Definition IR Interrupt Definition
+ * \{
+ * \ingroup     IR_Exported_Constants
+ */
+/* All interrupts in transmission mode */
+#define IR_INT_TF_EMPTY                             ((uint32_t)IR_TX_FIFO_EMPTY_INT_EN_Msk)
+#define IR_INT_TF_LEVEL                             ((uint32_t)IR_TX_FIFO_LEVEL_INT_EN_Msk)
+#define IR_INT_TF_OF                                ((uint32_t)IR_TX_FIFO_OVER_INT_EN_Msk)
+#define IR_INT_TX_FINISH                            ((uint32_t)IR_TX_FINISH_INT_EN_Msk)
+/* All interrupts in receiving mode */
+#define IR_INT_RF_FULL                              ((uint32_t)IR_RX_FIFO_FULL_INT_Msk)
+#define IR_INT_RF_LEVEL                             ((uint32_t)IR_RX_FIFO_LEVEL_INT_Msk)
+#define IR_INT_RX_CNT_OF                            ((uint32_t)IR_RX_CNT_OF_INT_Msk)
+#define IR_INT_RF_OF                                ((uint32_t)IR_RX_FIFO_OF_INT_Msk)
+#define IR_INT_RX_CNT_THR                           ((uint32_t)IR_RX_CNT_THR_INT_Msk)
+#define IR_INT_RF_ERROR                             ((uint32_t)IR_RX_FIFO_ERROR_INT_Msk)
+#define IR_INT_RISING_EDGE                          ((uint32_t)(IR_RX_EXTENSION_INT | IR_RX_RISING_EDGE_INT_EN_Msk))
+#define IR_INT_FALLING_EDGE                         ((uint32_t)(IR_RX_EXTENSION_INT | IR_RX_FALLING_EDGE_INT_EN_Msk))
+
+#define IS_IR_TX_INT_CONFIG(CONFIG)   (((CONFIG) == IR_INT_TF_EMPTY)   || \
+                                       ((CONFIG) == IR_INT_TF_LEVEL)   || \
+                                       ((CONFIG) == IR_INT_TF_OF)      || \
+                                       ((CONFIG) == IR_INT_TX_FINISH))
+
+#define IS_IR_RX_INT_CONFIG(CONFIG)   (((CONFIG) == IR_INT_RF_FULL)     || \
+                                       ((CONFIG) == IR_INT_RF_LEVEL)   || \
+                                       ((CONFIG) == IR_INT_RX_CNT_OF)  || \
+                                       ((CONFIG) == IR_INT_RF_OF)      || \
+                                       ((CONFIG) == IR_INT_RX_CNT_THR) || \
+                                       ((CONFIG) == IR_INT_RF_OF)      || \
+                                       ((CONFIG) == IR_INT_RISING_EDGE) || \
+                                       ((CONFIG) == IR_INT_FALLING_EDGE))
+#define IS_IR_INT_CONFIG(CONFIG)      (IS_IR_TX_INT_CONFIG(CONFIG) || IS_IR_RX_INT_CONFIG(CONFIG))
+/** \} */
+
+/**
+ * \defgroup   IR_Interrupts_Clear_Flag IR Interrupts Clear Flag
+ * \{
+ * \ingroup    IR_Exported_Constants
+ */
+/* Clear all interrupts in transmission mode */
+#define IR_INT_TF_EMPTY_CLR                                 ((uint32_t)IR_TX_FIFO_EMPTY_INT_CLR_Msk)
+#define IR_INT_TF_LEVEL_CLR                                 ((uint32_t)IR_TX_FIFO_LEVEL_INT_CLR_Msk)
+#define IR_INT_TF_OF_CLR                                    ((uint32_t)IR_TX_FIFO_OVER_INT_CLR_Msk)
+#define IR_INT_TX_FINISH_CLR                                ((uint32_t)IR_TX_FINISH_INT_CLR_Msk)
+/* Clear all interrupts in receiving mode */
+#define IR_INT_RF_FULL_CLR                                  ((uint32_t)IR_RX_FIFO_FULL_INT_CLR_Msk)
+#define IR_INT_RF_LEVEL_CLR                                 ((uint32_t)IR_RX_FIFO_LEVEL_INT_CLR_Msk)
+#define IR_INT_RX_CNT_OF_CLR                                ((uint32_t)IR_RX_CNT_OF_INT_CLR_Msk)
+#define IR_INT_RF_OF_CLR                                    ((uint32_t)IR_RX_FIFO_OF_INT_CLR_Msk)
+#define IR_INT_RX_CNT_THR_CLR                               ((uint32_t)IR_RX_CNT_THR_INT_CLR_Msk)
+#define IR_INT_RF_ERROR_CLR                                 ((uint32_t)IR_RX_FIFO_ERROR_INT_CLR_Msk)
+#define IR_INT_RX_RISING_EDGE_CLR                           ((uint32_t)IR_RX_RISING_EDGE_INT_CLR_Msk)
+#define IR_INT_RX_FALLING_EDGE_CLR                          ((uint32_t)IR_RX_FALLING_EDGE_INT_CLR_Msk)
+#define IR_RF_CLR                                           ((uint32_t)IR_RX_FIFO_CLR_Msk)
+
+#define IS_IR_INT_CLEAR(INT)            (((INT) == IR_INT_TF_EMPTY_CLR) || ((INT) == IR_INT_TF_LEVEL_CLR) || \
+                                         ((INT) == IR_INT_TF_OF_CLR) || ((INT) == IR_INT_RF_FULL_CLR) || \
+                                         ((INT) == IR_INT_RF_LEVEL_CLR) || ((INT) == IR_INT_RX_CNT_OF_CLR) || \
+                                         ((INT) == IR_INT_RF_OF_CLR) || ((INT) == IR_INT_RX_CNT_THR_CLR) || \
+                                         ((INT) == IR_INT_RX_RISING_EDGE_CLR) || ((INT) == IR_INT_RX_FALLING_EDGE_CLR) || \
+                                         ((INT) == IR_INT_RF_ERROR_CLR) || (INT) == IR_INT_TX_FINISH_CLR)
+/** \} */
+
+/**
+ * \defgroup    IR_Flag IR Flag
+ * \{
+ * \ingroup     IR_Exported_Constants
+ */
+#define IR_FLAG_TF_EMPTY                                    ((uint32_t)IR_TX_FIFO_EMPTY_Msk)
+#define IR_FLAG_TF_FULL                                     ((uint32_t)IR_TX_FIFO_FULL_Msk)
+#define IR_FLAG_TX_RUN                                      ((uint32_t)IR_TX_STATUS_Msk)
+#define IR_FLAG_RF_EMPTY                                    ((uint32_t)IR_RX_FIFO_EMPTY_Msk)
+#define IR_FLAG_RF_FULL                                     ((uint32_t)IR_RX_FIFO_FULL_Msk)
+#define IR_FLAG_RX_RUN                                      ((uint32_t)IR_RX_STATUS_Msk)
+
+#define IS_IR_FLAG(FLAG)                (((FLAG) == IR_FLAG_TF_EMPTY) || ((FLAG) == IR_FLAG_TF_FULL) || \
+                                         ((FLAG) == IR_FLAG_TX_RUN) || ((FLAG) == IR_FLAG_RF_EMPTY) || \
+                                         ((FLAG) == IR_FLAG_RF_FULL) || ((FLAG) == IR_FLAG_RX_RUN))
+/** \} */
+
+/**
+ * \defgroup    IR_Compensation_Flag IR Compensation Flag
+ * \{
+ * \ingroup     IR_Exported_Constants
+ */
+typedef enum
+{
+    IR_COMPEN_FLAG_1_2_CARRIER = ((uint32_t)(1 << IR_LOW_PERIOD_COMPENSATION_Pos)),
+    IR_COMPEN_FLAG_1_4_CARRIER = ((uint32_t)(2 << IR_LOW_PERIOD_COMPENSATION_Pos)),
+    IR_COMPEN_FLAG_1_N_SYSTEM_CLK = ((uint32_t)(3 << IR_LOW_PERIOD_COMPENSATION_Pos)),
+} IR_TX_COMPEN_TYPE;
+/** \} */
+
+/** End of IR_Exported_Constants
+  * \}
+  */
+/*============================================================================*
+ *                         Functions
+ *============================================================================*/
+/**
+ * \defgroup    IR_Exported_Functions   IR Exported Functions
+ * \{
+ * \ingroup     IR
+ */
+
+/**
+ * \brief  Deinitialize the IR peripheral registers to their default values.
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_ir_init(void)
+ * {
+ *     IR_DeInit();
+ * }
+ * \endcode
+ */
+void IR_DeInit(void);
+
+/**
+ * \brief   Initialize the IR peripheral according to the specified
+ *          parameters in IR_InitStruct.
+ * \param[in] IR_InitStruct: Pointer to an IR_InitTypeDef structure that
+ *            contains the configuration information for the specified IR peripheral.
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_ir_init(void)
+ * {
+ *     RCC_PeriphClockCmd(APBPeriph_IR, APBPeriph_IR_CLOCK, ENABLE);
+
+ *     IR_InitTypeDef IR_InitStruct;
+ *     IR_StructInit(&IR_InitStruct);
+
+ *     IR_InitStruct.IR_Freq               = 38000;// IR carrier frequency is 38KHz
+ *     IR_InitStruct.IR_Mode               = IR_MODE_RX;// IR receiving mode
+ *     IR_InitStruct.IR_RxStartMode        = IR_RX_AUTO_MODE;
+ *     IR_InitStruct.IR_RxFIFOThrLevel     =
+         IR_RX_FIFO_THR_LEVEL; // Configure RX FIFO threshold level to trigger IR_INT_RF_LEVEL interrupt
+ *     IR_InitStruct.IR_RxFIFOFullCtrl     =
+ *         IR_RX_FIFO_FULL_DISCARD_NEWEST;// Discard the latest received data if RX FIFO is full
+ *     IR_InitStruct.IR_RxFilterTime       =
+        IR_RX_FILTER_TIME_50ns;// If high to low or low to high transition time <= 50ns, filter it out.
+ *     IR_InitStruct.IR_RxTriggerMode      = IR_RX_FALL_EDGE;// Configure trigger type
+ *     IR_InitStruct.IR_RxCntThrType       =
+        IR_RX_Count_High_Level;// IR_RX_Count_High_Level is counting high level
+ *     IR_InitStruct.IR_RxCntThr           =
+        0x1F40;// Configure RX counter threshold. This can be used to decide when to stop receiving IR data
+ *     IR_Init(&IR_InitStruct);
+ *     IR_Cmd(IR_MODE_RX, ENABLE);
+ *     IR_ClearRxFIFO();
+ * }
+ * \endcode
+ */
+void IR_Init(IR_InitTypeDef *IR_InitStruct);
+
+/**
+ * \brief  Fill each IR_InitStruct member with its default value.
+ * \param[in] IR_InitStruct: Pointer to an IR_InitTypeDef structure which will be initialized.
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_ir_init(void)
+ * {
+ *     RCC_PeriphClockCmd(APBPeriph_IR, APBPeriph_IR_CLOCK, ENABLE);
+
+ *     IR_InitTypeDef IR_InitStruct;
+ *     IR_StructInit(&IR_InitStruct);
+
+ *     IR_InitStruct.IR_Freq               = 38000;// IR carrier frequency is 38KHz
+ *     IR_InitStruct.IR_Mode               = IR_MODE_RX;// IR receiving mode
+ *     IR_InitStruct.IR_RxStartMode        = IR_RX_AUTO_MODE;
+ *     IR_InitStruct.IR_RxFIFOThrLevel     =
+         IR_RX_FIFO_THR_LEVEL; // Configure RX FIFO threshold level to trigger IR_INT_RF_LEVEL interrupt
+ *     IR_InitStruct.IR_RxFIFOFullCtrl     =
+ *         IR_RX_FIFO_FULL_DISCARD_NEWEST;// Discard the latest received data if RX FIFO is full
+ *     IR_InitStruct.IR_RxFilterTime       =
+        IR_RX_FILTER_TIME_50ns;// If high to low or low to high transition time <= 50ns, filter it out.
+ *     IR_InitStruct.IR_RxTriggerMode      = IR_RX_FALL_EDGE;// Configure trigger type
+ *     IR_InitStruct.IR_RxCntThrType       =
+        IR_RX_Count_High_Level;// IR_RX_Count_High_Level is counting high level
+ *     IR_InitStruct.IR_RxCntThr           =
+        0x1F40;// Configure RX counter threshold. This can be used to decide when to stop receiving IR data
+ *     IR_Init(&IR_InitStruct);
+ *     IR_Cmd(IR_MODE_RX, ENABLE);
+ *     IR_ClearRxFIFO();
+ * }
+ * \endcode
+ */
+void IR_StructInit(IR_InitTypeDef *IR_InitStruct);
+
+/**
+ * \brief   Enable or disable the selected IR mode.
+ * \param[in] mode: Selected IR operation mode.
+ *      This parameter can be one of the following values, which refers to \ref IR_Mode.
+ *      \arg IR_MODE_TX: Transmission mode.
+ *      \arg IR_MODE_RX: Receiving mode.
+ * \param[in] NewState: New state of the operation mode.
+ *      This parameter can be: ENABLE or DISABLE.
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_ir_init(void)
+ * {
+ *     RCC_PeriphClockCmd(APBPeriph_IR, APBPeriph_IR_CLOCK, ENABLE);
+
+ *     IR_InitTypeDef IR_InitStruct;
+ *     IR_StructInit(&IR_InitStruct);
+
+ *     IR_InitStruct.IR_Freq               = 38000;// IR carrier frequency is 38KHz
+ *     IR_InitStruct.IR_Mode               = IR_MODE_RX;// IR receiving mode
+ *     IR_InitStruct.IR_RxStartMode        = IR_RX_AUTO_MODE;
+ *     IR_InitStruct.IR_RxFIFOThrLevel     =
+         IR_RX_FIFO_THR_LEVEL; // Configure RX FIFO threshold level to trigger IR_INT_RF_LEVEL interrupt
+ *     IR_InitStruct.IR_RxFIFOFullCtrl     =
+ *         IR_RX_FIFO_FULL_DISCARD_NEWEST;// Discard the latest received data if RX FIFO is full
+ *     IR_InitStruct.IR_RxFilterTime       =
+        IR_RX_FILTER_TIME_50ns;// If high to low or low to high transition time <= 50ns, filter it out.
+ *     IR_InitStruct.IR_RxTriggerMode      = IR_RX_FALL_EDGE;// Configure trigger type
+ *     IR_InitStruct.IR_RxCntThrType       =
+        IR_RX_Count_High_Level;// IR_RX_Count_High_Level is counting high level
+ *     IR_InitStruct.IR_RxCntThr           =
+        0x1F40;// Configure RX counter threshold. This can be used to decide when to stop receiving IR data
+ *     IR_Init(&IR_InitStruct);
+ *     IR_Cmd(IR_MODE_RX, ENABLE);
+ *     IR_ClearRxFIFO();
+ * }
+ * \endcode
+ */
+void IR_Cmd(uint32_t mode, FunctionalState NewState);
+
+/**
+ * \brief   Start trigger receive, only in manual receive mode.
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void ir_demo(void)
+ * {
+ *     IR_StartManualRxTrigger();
+ * }
+ * \endcode
+ */
+void IR_StartManualRxTrigger(void);
+
+/**
+ * \brief   Config counter threshold value in receiving mode. It can be used to stop receiving IR data.
+ * \param[in] IR_RxCntThrType: Count threshold type.
+ *      This parameter can be the following values, which refers to \ref IR_RX_COUNTER_THRESHOLD_TYPE.
+ *      \arg IR_RX_Count_Low_Level: Low level counter value >= IR_RxCntThr, trigger IR_INT_RX_CNT_THR interrupt.
+ *      \arg IR_RX_Count_High_Level: High level counter value >= IR_RxCntThr, trigger IR_INT_RX_CNT_THR interrupt.
+ * \param[in] IR_RxCntThr: Configure IR Rx counter threshold value which can be 0 to 0x7fffffff.
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void ir_demo(void)
+ * {
+ *     IR_SetRxCounterThreshold(IR_RX_Count_Low_Level, 0x100);
+ * }
+ * \endcode
+ */
+void IR_SetRxCounterThreshold(uint32_t IR_RxCntThrType, uint32_t IR_RxCntThr);
+
+/**
+ * \brief   Send data buffer.
+ * \param[in] pBuf: Data buffer to send.
+ * \param[in] len: Send data length.
+ * \param[in] IsLastPacket: Is it the last package of data.
+ *      This parameter can be one of the following values:
+ *      \arg ENABLE: The last data in IR packet and there is no continuous data. In other words, an infrared data transmission is completed.
+ *      \arg DISABLE: There is data to be transmitted continuously.
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void ir_demo(void)
+ * {
+ *     uint32_t data_buf[80] = {0};
+ *     IR_SendBuf(data_buf, 68, DISABLE);
+ * }
+ * \endcode
+ */
+void IR_SendBuf(const uint32_t *pBuf, uint32_t len, FunctionalState IsLastPacket);
+
+/**
+ * \brief  Send compensation data.
+ * \param[in] comp_type: Compensation data type.
+ *      This parameter can be one of the following values, which refers to \ref IR_Compensation_Flag.
+ *     \arg IR_COMPEN_FLAG_1_2_CARRIER: 1/2 carrier frequency.
+ *     \arg IR_COMPEN_FLAG_1_4_CARRIER: 1/4 carrier frequency.
+ *     \arg IR_COMPEN_FLAG_1_N_SYSTEM_CLK: MOD((0x48[27:16]+0x00[11:0]), 4095)/40MHz.
+            User can call function of IR_ConfigCompParam to configure 0x48[27:16].
+ * \param[in] buf: Data buffer to send.
+ * \param[in] length: Data length.
+ * \param[in] IsLastPacket: Is it the last package of data.
+ *      This parameter can be the following values:
+ *     \arg ENABLE: The last data in IR packet and there is no continuous data. In other words, an infrared data transmission is completed.
+ *     \arg DISABLE: There is data to be transmitted continuously.
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void ir_demo(void)
+ * {
+ *     uint32_t data_buf[80] = {0};
+ *     IR_SendCompenBuf(IR_COMPEN_FLAG_1_2_CARRIER, data_buf, 68, DISABLE);
+ * }
+ * \endcode
+ */
+void IR_SendCompenBuf(IR_TX_COMPEN_TYPE comp_type, uint32_t *pBuf, uint32_t len,
+                      FunctionalState IsLastPacket);
+
+/**
+ * \brief   Read data From RX FIO.
+ * \param[out] pBuf: Buffer address to receive data.
+ * \param[in] length: Read data length.
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void ir_demo(void)
+ * {
+ *     uint32_t data_buf[80] = {0};
+ *     IR_ReceiveBuf(data_buf, 68);
+ * }
+ * \endcode
+ */
+void IR_ReceiveBuf(uint32_t *pBuf, uint32_t length);
+
+/**
+ * \brief     Enable or disable the specified IR interrupt source.
+ * \param[in] IR_INT: Specify the IR interrupt source to be enabled or disabled.
+ *            This parameter can be one of the following values, which refers to \ref IR_Interrupt_Definition.
+ *            \arg IR_INT_TF_EMPTY: When TX FIFO is empty, TX FIFO Empty Interrupt will be triggered.
+ *            \arg IR_INT_TF_LEVEL: When TX FIFO offset <= threshold value, trigger TX FIFO Level Interrupt.
+ *            \arg IR_INT_TF_OF: When TX FIFO is full, data continues to be written to TX FIFO, TX FIFO overflow interrupt will be triggered.
+ *            \arg IR_INT_TX_FINISH: When TX finished, TX Finish Interrupt will be triggered.
+ *            \arg IR_INT_RF_FULL: When RX FIFO offset = 32, RX FIFO Full Interrupt will be triggered.
+ *            \arg IR_INT_RF_LEVEL: When RX FIFO offset > threshold value, trigger RX FIFO Level Interrupt.
+ *            \arg IR_INT_RX_CNT_OF: When RX counter overflows, RX counter overflow interrupt will be triggered.
+ *            \arg IR_INT_RF_OF: When RX FIFO is full and continues to be written, RX FIFO overflow interrupt will be triggered.
+ *            \arg IR_INT_RX_CNT_THR: When RX counter >= IR_RX_CNT_THR, RX Counter Threshold Interrupt will be triggered.
+ *            \arg IR_INT_RF_ERROR: When RX FIFO is empty and continues to be read, RX FIFO error read interrupt will be triggered.
+ *            \arg IR_INT_RISING_EDGE: When RX FIFO receives a low to high pulse, RX Rising Edge Interrupt will be triggered.
+ *            \arg IR_INT_FALLING_EDGE: When RX FIFO receives a high to low pulse, RX Falling Edge Interrupt will be triggered.
+ * \param[in]  newState: New state of the specified IR interrupt.
+ *      This parameter can be: ENABLE or DISABLE.
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void ir_demo(void)
+ * {
+ *     IR_INTConfig(IR_INT_TF_EMPTY, ENABLE);
+ * }
+ * \endcode
+ */
+void IR_INTConfig(uint32_t IR_INT, FunctionalState newState);
+
+/**
+ * \brief     Mask or unmask the specified IR interrupt source.
+ * \param[in] IR_INT: Specify the IR interrupts sources to be masked or unmasked.
+ *            This parameter can be the following values, which refers to \ref IR_Interrupt_Definition.
+ *            \arg IR_INT_TF_EMPTY: When TX FIFO is empty, TX FIFO Empty Interrupt will be triggered.
+ *            \arg IR_INT_TF_LEVEL: When TX FIFO offset <= threshold value, trigger TX FIFO Level Interrupt.
+ *            \arg IR_INT_TF_OF: When TX FIFO is full, data continues to be written to TX FIFO, TX FIFO Overflow interrupt will be triggered.
+ *            \arg IR_INT_TX_FINISH: When TX finished, TX Finish Interrupt will be triggered.
+ *            \arg IR_INT_RF_FULL: When RX FIFO offset = 32, RX FIFO Full Interrupt will be triggered.
+ *            \arg IR_INT_RF_LEVEL: When RX FIFO offset > threshold value, trigger RX FIFO Level Interrupt.
+ *            \arg IR_INT_RX_CNT_OF: When RX counter overflows, RX counter overflow interrupt will be triggered.
+ *            \arg IR_INT_RF_OF: When RX FIFO is full and continues to be written, RX FIFO overflow interrupt will be triggered.
+ *            \arg IR_INT_RX_CNT_THR: When RX counter >= IR_RX_CNT_THR, RX Counter Threshold Interrupt will be triggered.
+ *            \arg IR_INT_RF_ERROR: When RX FIFO is empty and continues to be read, RX FIFO error read interrupt will be triggered.
+ *            \arg IR_INT_RISING_EDGE: When RX FIFO receives a low to high pulse, RX Rising Edge Interrupt will be triggered.
+ *            \arg IR_INT_FALLING_EDGE: When RX FIFO receives a high to low pulse, RX Falling Edge Interrupt will be triggered.
+ * \param[in] newState: New state of the specified IR interrupts.
+ *            This parameter can be: ENABLE or DISABLE.
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void ir_demo(void)
+ * {
+ *     IR_MaskINTConfig(IR_INT_TF_EMPTY, ENABLE);
+ * }
+ * \endcode
+ */
+void IR_MaskINTConfig(uint32_t IR_INT, FunctionalState newState);
+
+/**
+ * \brief     Get the specified IR interrupt status.
+ * \param[in] IR_INT: the specified IR interrupts.
+ *            This parameter can be one of the following values, which refers to \ref IR_Interrupt_Definition.
+ *            \arg IR_INT_TF_EMPTY: When TX FIFO is empty, TX FIFO Empty Interrupt will be triggered.
+ *            \arg IR_INT_TF_LEVEL: When TX FIFO offset <= threshold value, trigger TX FIFO Level Interrupt.
+ *            \arg IR_INT_TF_OF: When TX FIFO is full, data continues to be written to TX FIFO, TX FIFO Overflow interrupt will be triggered.
+ *            \arg IR_INT_TX_FINISH: When TX finished, TX Finish Interrupt will be triggered.
+ *            \arg IR_INT_RF_FULL: When RX FIFO offset = 32, RX FIFO Full Interrupt will be triggered.
+ *            \arg IR_INT_RF_LEVEL: When RX FIFO offset > threshold value, trigger RX FIFO Level Interrupt.
+ *            \arg IR_INT_RX_CNT_OF: When RX counter overflows, RX counter overflow interrupt will be triggered.
+ *            \arg IR_INT_RF_OF: When RX FIFO is full and continues to be written, RX FIFO overflow interrupt will be triggered.
+ *            \arg IR_INT_RX_CNT_THR: When RX counter >= IR_RX_CNT_THR, RX Counter Threshold Interrupt will be triggered.
+ *            \arg IR_INT_RF_ERROR: When RX FIFO is empty and continues to be read, RX FIFO error read interrupt will be triggered.
+ *            \arg IR_INT_RISING_EDGE: When RX FIFO receives a low to high pulse, RX Rising Edge Interrupt will be triggered.
+ *            \arg IR_INT_FALLING_EDGE: When RX FIFO receives a high to low pulse, RX Falling Edge Interrupt will be triggered.
+ * \return  The new state of IR_INT (SET or RESET).
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void ir_demo(void)
+ * {
+ *     ITStatus int_status = IR_GetINTStatus(IR_INT_TF_EMPTY);
+ * }
+ * \endcode
+ */
+ITStatus IR_GetINTStatus(uint32_t IR_INT);
+
+/**
+ * \brief     Clear the IR interrupt pending bit.
+ * \param[in] IR_CLEAR_INT: Specify the interrupt pending bit to clear.
+ *      This parameter can be any combination of the following values, which refers to \ref IR_Interrupts_Clear_Flag.
+ *      \arg IR_INT_TF_EMPTY_CLR: Clear TX FIFO empty interrupt.
+ *      \arg IR_INT_TF_LEVEL_CLR: Clear TX FIFO threshold interrupt.
+ *      \arg IR_INT_TF_OF_CLR: Clear TX FIFO overflow interrupt.
+ *      \arg IR_INT_TX_FINISH_CLR: Clear TX finish interrupt.
+ *      \arg IR_INT_RF_FULL_CLR: Clear RX FIFO full interrupt.
+ *      \arg IR_INT_RF_LEVEL_CLR: Clear RX FIFO threshold interrupt.
+ *      \arg IR_INT_RX_CNT_OF_CLR: Clear RX counter overflow interrupt.
+ *      \arg IR_INT_RF_OF_CLR: Clear RX FIFO overflow interrupt.
+ *      \arg IR_INT_RX_CNT_THR_CLR: Clear RX counter threshold interrupt.
+ *      \arg IR_INT_RF_ERROR_CLR: Clear RX FIFO error read interrupt. Trigger when RX FIFO empty and read RX FIFO.
+ *      \arg IR_INT_RX_RISING_EDGE_CLR: Clear RX Rising edge interrupt.
+ *      \arg IR_INT_RX_FALLING_EDGE_CLR: Clear RX Falling edge interrupt.
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void ir_demo(void)
+ * {
+ *     IR_ClearINTPendingBit(IR_INT_RX_CNT_OF_CLR);
+ * }
+ * \endcode
+ */
+void IR_ClearINTPendingBit(uint32_t IR_CLEAR_INT);
+
+/**
+ * \brief  Get free size of TX FIFO.
+ * \return The free size of TX FIFO.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void ir_demo(void)
+ * {
+ *     uint16_t data_len = IR_GetTxFIFOFreeLen();
+ * }
+ * \endcode
+ */
+__STATIC_INLINE uint16_t IR_GetTxFIFOFreeLen(void)
+{
+    return (uint16_t)(IR_TX_FIFO_SIZE - ((IR->TX_SR & (IR_TX_FIFO_OFFSET_Msk)) >>
+                                         IR_TX_FIFO_OFFSET_Pos));
+}
+
+/**
+ * \brief   Get data size in RX FIFO.
+ * \return  Current data size in RX FIFO.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void ir_demo(void)
+ * {
+ *     uint16_t data_len = IR_GetRxDataLen();
+ * }
+ * \endcode
+ */
+__STATIC_INLINE uint16_t IR_GetRxDataLen(void)
+{
+    return ((uint16_t)(((IR->RX_SR) & IR_RX_FIFO_OFFSET_Msk) >> IR_RX_FIFO_OFFSET_Pos));
+}
+
+/**
+ * \brief   Send one data.
+ * \param[in] data: Send data.
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void ir_demo(void)
+ * {
+ *     IR_SendData(0x80000100);
+ * }
+ * \endcode
+ */
+__STATIC_INLINE void IR_SendData(uint32_t data)
+{
+    IR->TX_FIFO = data;
+}
+
+/**
+ * \brief   Read one data.
+ * \return  Data which is read from RX FIFO.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void ir_demo(void)
+ * {
+ *     uint32_t data = IR_ReceiveData();
+ * }
+ * \endcode
+ */
+__STATIC_INLINE uint32_t IR_ReceiveData(void)
+{
+    return IR->RX_FIFO;
+}
+
+/**
+ * \brief  Set tx threshold, when TX FIFO depth <= threshold value, trigger interrupt.
+ * \param[in] thd: Tx threshold.
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void ir_demo(void)
+ * {
+ *     IR_SetTxThreshold(30);
+ * }
+ * \endcode
+ */
+__STATIC_INLINE void IR_SetTxThreshold(uint8_t thd)
+{
+    IR->TX_CONFIG &= IR_TX_FIFO_THRESHOLD_CLR;
+    IR->TX_CONFIG |= (thd << IR_TX_FIFO_THRESHOLD_Pos);
+}
+
+/**
+ * \brief   Set rx threshold, when RX FIFO depth > threshold value, trigger interrupt.
+ * \param[in] thd: Rx threshold.
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void ir_demo(void)
+ * {
+ *     IR_SetRxThreshold(2);
+ * }
+ * \endcode
+ */
+__STATIC_INLINE void IR_SetRxThreshold(uint8_t thd)
+{
+    IR->RX_CONFIG &= IR_RX_FIFO_LEVEL_CLR;
+    IR->RX_CONFIG |= (thd << IR_RX_FIFO_LEVEL_Pos);
+}
+
+/**
+ * \brief  Get IR RX current count.
+ * \return Current counter.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void ir_demo(void)
+ * {
+ *     uint32_t count = IR_GetRxCurrentCount();
+ * }
+ * \endcode
+ */
+__STATIC_INLINE uint32_t IR_GetRxCurrentCount(void)
+{
+    return IR->RX_CUR_CNT ;
+}
+
+/**
+ * \brief  Clear IR TX FIFO.
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void ir_demo(void)
+ * {
+ *     IR_ClearTxFIFO();
+ * }
+ * \endcode
+ */
+__STATIC_INLINE void IR_ClearTxFIFO(void)
+{
+    IR->TX_INT_CLR = IR_TX_FIFO_CLR_Msk;
+}
+
+/**
+ * \brief   Clear IR RX FIFO.
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void ir_demo(void)
+ * {
+ *     IR_ClearRxFIFO();
+ * }
+ * \endcode
+ */
+__STATIC_INLINE void IR_ClearRxFIFO(void)
+{
+    IR->RX_INT_CLR = IR_RX_FIFO_CLR_Msk;
+}
+
+/**
+ * \brief  Check whether the specified IR flag is set.
+ * \param[in]  IR_FLAG: Specify the flag to check.
+ *      This parameter can be one of the following values, which refer to \ref IR_Flag.
+ *      \arg IR_FLAG_TF_EMPTY: TX FIFO empty or not. If SET, TX FIFO is empty.
+ *      \arg IR_FLAG_TF_FULL: TX FIFO full or not. If SET, TX FIFO is full.
+ *      \arg IR_FLAG_TX_RUN: TX run or not. If SET, TX is running.
+ *      \arg IR_FLAG_RF_EMPTY: RX FIFO empty or not. If SET, RX FIFO is empty.
+ *      \arg IR_FLAG_RF_FULL: RX FIFO full or not. If SET, RX FIFO is full.
+ *      \arg IR_FLAG_RX_RUN: RX run or not. If SET, RX is running.
+ * \return  The new state of IR_FLAG (SET or RESET).
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void ir_demo(void)
+ * {
+ *     FlagStatus flag_status = IR_GetFlagStatus(IR_FLAG_TF_EMPTY);
+ * }
+ * \endcode
+ */
+__STATIC_INLINE FlagStatus IR_GetFlagStatus(uint32_t IR_FLAG)
+{
+    FlagStatus bitstatus = RESET;
+
+    /* Check the parameters */
+    assert_param(IS_IR_FLAG(IR_FLAG));
+
+    if (IR->TX_CONFIG & IR_MODE_SEL_Msk)
+    {
+        if (IR->RX_SR & IR_FLAG)
+        {
+            bitstatus = SET;
+        }
+        return bitstatus;
+    }
+    else
+    {
+        if (IR->TX_SR & IR_FLAG)
+        {
+            bitstatus = SET;
+        }
+        return bitstatus;
+    }
+}
+
+/**
+ * \brief  Enable TX FIFO inverse or not.
+ * \param[in] NewState: This parameter can be: ENABLE or DISABLE.
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void ir_demo(void)
+ * {
+ *     IR_SetTxInverse(ENABLE);
+ * }
+ * \endcode
+ */
+__STATIC_INLINE void IR_SetTxInverse(FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (NewState == ENABLE)
+    {
+        IR->TX_CONFIG |= IR_FIFO_INVERSE_Msk;
+    }
+    else
+    {
+        IR->TX_CONFIG &= IR_FIFO_INVERSE_CLR;
+    }
+}
+
+/**
+ * \brief  Enable TX active output inverse or not.
+ * \param[in] NewState: This parameter can be: ENABLE or DISABLE.
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void ir_demo(void)
+ * {
+ *     IR_TxOutputInverse(ENABLE);
+ * }
+ * \endcode
+ */
+__STATIC_INLINE void IR_TxOutputInverse(FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (NewState == ENABLE)
+    {
+        IR->TX_CONFIG |= IR_OUTPUT_INVERSE_Msk;
+    }
+    else
+    {
+        IR->TX_CONFIG &= IR_OUTPUT_INVERSE_CLR;
+    }
+}
+
+/**
+ * \brief  Get IR RX Level.
+ * \return Current Level.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void ir_demo(void)
+ * {
+ *     uint32_t level = IR_GetRxCurrentLevel();
+ * }
+ * \endcode
+ */
+__STATIC_INLINE uint32_t IR_GetRxCurrentLevel(void)
+{
+    /* Check the parameters */
+    return (IR->IR_RX_LEVEL);
+
+}
+
+/** End of IR_Exported_Functions
+  * \}
+  */
+
+/** End of IR
+  * \}
+  */
+
+typedef struct
+{
+    uint32_t ir_reg[4];
+} IRStoreReg_TypeDef;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTL876x_IR_H_ */
+
+
+
+
diff --git a/bee/drivers/ir/src/device/rtl87x2g/rtl87x2g_ir.c b/bee/drivers/ir/src/device/rtl87x2g/rtl87x2g_ir.c
new file mode 100644
index 00000000..fc305407
--- /dev/null
+++ b/bee/drivers/ir/src/device/rtl87x2g/rtl87x2g_ir.c
@@ -0,0 +1,115 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *                        Header Files
+ *============================================================================*/
+#include "rtl_ir.h"
+#include "rtl_rcc.h"
+#include "app_section.h"
+
+/*============================================================================*
+ *                           Public Functions
+ *============================================================================*/
+/**
+  * \brief  IR clock config.
+  * \param  ClockSrc: specifies the clock source to gates its clock.
+  * \param  ClockDiv: specifies the clock divide to gates its clock.
+  * \return None
+  */
+void IR_ClkConfig(IRClockSrc_TypeDef ClockSrc, IRClockDiv_TypeDef ClockDiv)
+{
+    if (ClockSrc == IR_CLOCK_SRC_40M)
+    {
+        PERIBLKCTRL_PERI_CLK->u_320.BITS_320.r_sclk_ir_src_sel = 0;
+    }
+    else
+    {
+        PERIBLKCTRL_PERI_CLK->u_320.BITS_320.r_sclk_ir_src_sel = 1;
+        PERIBLKCTRL_PERI_CLK->u_320.BITS_320.r_pll_ir_div_sel = ClockDiv;
+        if (ClockSrc == IR_CLOCK_SRC_PLL1)
+        {
+            PERIBLKCTRL_PERI_CLK->u_320.BITS_320.r_pll_ir_src_sel = 0;
+        }
+        else if (ClockSrc == IR_CLOCK_SRC_PLL2)
+        {
+            PERIBLKCTRL_PERI_CLK->u_320.BITS_320.r_pll_ir_src_sel = 1;
+        }
+    }
+
+    return;
+}
+
+bool IR_ClkGet(IRClockSrc_TypeDef *ClockSrc, IRClockDiv_TypeDef *ClockDiv)
+{
+    if (PERIBLKCTRL_PERI_CLK->u_320.BITS_320.r_sclk_ir_src_sel == 0)
+    {
+        *ClockSrc = IR_CLOCK_SRC_40M;
+        *ClockDiv = IR_CLOCK_DIVIDER_1;
+    }
+    else
+    {
+        *ClockDiv = (IRClockDiv_TypeDef)PERIBLKCTRL_PERI_CLK->u_320.BITS_320.r_pll_ir_div_sel;
+        *ClockSrc = (PERIBLKCTRL_PERI_CLK->u_320.BITS_320.r_pll_ir_src_sel == 0) ? \
+                    IR_CLOCK_SRC_PLL1 : IR_CLOCK_SRC_PLL2;
+    }
+
+    return true;
+}
+
+/**
+  * \brief  Store IR register values when system enter DLPS.
+  * \param  PeriReg: Specifies to select the IR peripheral.
+  * \param  StoreBuf: Store buffer to store IR register data.
+  * \return None.
+  */
+RAM_FUNCTION
+void IR_DLPSEnter(void *PeriReg, void *StoreBuf)
+{
+    IRStoreReg_Typedef *store_buf = (IRStoreReg_Typedef *)StoreBuf;
+
+    RCC_PeriphClockCmd(APBPeriph_IR, APBPeriph_IR_CLOCK, ENABLE);
+
+    store_buf->ir_reg[0] = IR->IR_CLK_DIV;
+    store_buf->ir_reg[1] = IR->IR_TX_CONFIG;
+    store_buf->ir_reg[2] = IR->IR_RX_CONFIG;
+    store_buf->ir_reg[3] = IR->IR_RX_CNT_INT_SEL;
+
+    return;
+}
+
+/**
+  * \brief  Restore IR register values when system enter DLPS.
+  * \param  PeriReg: Specifies to select the IR peripheral.
+  * \param  StoreBuf: Restore buffer to restore IR register data.
+  * \return None
+  */
+RAM_FUNCTION
+void IR_DLPSExit(void *PeriReg, void *StoreBuf)
+{
+    IRStoreReg_Typedef *store_buf = (IRStoreReg_Typedef *)StoreBuf;
+
+    RCC_PeriphClockCmd(APBPeriph_IR, APBPeriph_IR_CLOCK, ENABLE);
+
+    IR->IR_CLK_DIV = store_buf->ir_reg[0];
+    if (store_buf->ir_reg[1] & BIT31)
+    {
+        /* RX MODE */
+        IR->IR_TX_CONFIG  = store_buf->ir_reg[1];
+        IR->IR_RX_CONFIG  = store_buf->ir_reg[2];
+        IR->IR_RX_CNT_INT_SEL  = store_buf->ir_reg[3];
+    }
+    else
+    {
+        /* TX MODE */
+        IR->IR_TX_CONFIG  = store_buf->ir_reg[1];
+        /* If IR TX mode is idle, must write one data firstly */
+        IR->IR_TX_FIFO = 0;
+    }
+
+    return;
+}
+
diff --git a/bee/drivers/ir/src/device/rtl87x2g/rtl_ir.c b/bee/drivers/ir/src/device/rtl87x2g/rtl_ir.c
new file mode 100644
index 00000000..6e1a3dcd
--- /dev/null
+++ b/bee/drivers/ir/src/device/rtl87x2g/rtl_ir.c
@@ -0,0 +1,891 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *                        Header Files
+ *============================================================================*/
+#include "rtl_ir.h"
+#include "rtl_rcc.h"
+
+/*============================================================================*
+ *                           Public Functions
+ *============================================================================*/
+/**
+  * \brief  Deinitializes the IR peripheral registers to their default values.
+  * \param  None
+  * \return None
+  */
+void IR_DeInit(void)
+{
+    RCC_PeriphClockCmd(APBPeriph_IR, APBPeriph_IR_CLOCK, DISABLE);
+}
+
+/**
+  * \brief  Initializes the IR peripheral according to the specified
+  *         parameters in the IR_InitStruct
+  * \param  IR_InitStruct: Pointer to a IR_InitTypeDef structure that
+  *         contains the configuration information for the specified IR peripheral
+  * \return None
+  */
+void IR_Init(IR_InitTypeDef *IR_InitStruct)
+{
+    /* Check the parameters */
+    assert_param(IS_IR_CLOCK(IR_InitStruct->IR_Clock));
+
+    if (IR_InitStruct->IR_Clock == 40000000)
+    {
+        assert_param(IS_IR_FREQUENCY_40M(IR_InitStruct->IR_Freq));
+    }
+#if  IR_SUPPORT_CLOCK_SOURCE_80M
+    else if (IR_InitStruct->IR_Clock == 80000000)
+    {
+        assert_param(IS_IR_FREQUENCY_80M(IR_InitStruct->IR_Freq));
+    }
+#endif
+#if IR_SUPPORT_CLOCK_SOURCE_90M
+    else if (IR_InitStruct->IR_Clock == 90000000)
+    {
+        assert_param(IS_IR_FREQUENCY_90M(IR_InitStruct->IR_Freq));
+    }
+#endif
+#if  IR_SUPPORT_CLOCK_SOURCE_100M
+    else if (IR_InitStruct->IR_Clock == 100000000)
+    {
+        assert_param(IS_IR_FREQUENCY_100M(IR_InitStruct->IR_Freq));
+    }
+#endif
+    assert_param(IS_IR_MODE(IR_InitStruct->IR_Mode));
+
+
+    /* Configure IR clock divider. Formula: IR_CLK = IO_CLK/(1+IR_CLK_DIV) */
+    uint32_t ir_clk_div_num = (IR_InitStruct->IR_Clock / IR_InitStruct->IR_Freq) - 1;
+    uint32_t duty_cycle_num = ((double)(ir_clk_div_num + 1.0)) / (IR_InitStruct->IR_DutyCycle);
+
+    IR_CLK_DIV_TypeDef ir_0x00 = {.d32 = IR->IR_CLK_DIV};
+    ir_0x00.b.ir_clk_div = ir_clk_div_num;
+    IR->IR_CLK_DIV = ir_0x00.d32;
+    if (IR_InitStruct->IR_Mode == IR_MODE_TX)
+    {
+        /* Check the parameters in TX mode */
+        assert_param(IS_IR_IDLE_STATUS(IR_InitStruct->IR_TxIdleLevel));
+        assert_param(IS_IR_TX_DATA_TYPE(IR_InitStruct->IR_TxInverse));
+        assert_param(IS_IR_TX_THRESHOLD(IR_InitStruct->IR_TxFIFOThrLevel));
+
+        /* Stop Transmission mode */
+        IR_TX_CONFIG_TypeDef ir_0x04 = {.d32 = IR->IR_TX_CONFIG};
+        ir_0x04.b.ir_tx_start = 0;
+
+        /* Configure TX mode parameters and disable all TX interrupt */
+        ir_0x04.b.ir_mode_sel = IR_InitStruct->IR_Mode;
+        ir_0x04.b.ir_tx_idel_state = IR_InitStruct->IR_TxIdleLevel;
+        ir_0x04.b.ir_tx_de_inverse = IR_InitStruct->IR_TxInverse;
+        ir_0x04.b.ir_tx_fifo_level_th = IR_InitStruct->IR_TxFIFOThrLevel;
+        ir_0x04.b.ir_tx_duty_num = duty_cycle_num & 0x3FFF;
+        IR->IR_TX_CONFIG = ir_0x04.d32;
+
+        /* Clear all TX interrupt and TX FIFO */
+        IR->IR_TX_INT_CLR = IR_TX_INT_ALL_CLR | IR_TF_CLR;
+
+        /* Config dma tx */
+        IR_DMA_CONFIG_TypeDef ir_0x50 = {.d32 = IR->IR_DMA_CONFIG};
+        ir_0x50.d32 = 0;
+        ir_0x50.b.reg_dma_tx_en = IR_InitStruct->IR_TxDmaEn;
+        ir_0x50.b.reg_dma_tx_fifo_th = IR_InitStruct->IR_TxWaterLevel;
+        IR->IR_DMA_CONFIG = ir_0x50.d32;
+    }
+    else
+    {
+        /* Check the parameters in RX mode */
+        assert_param(IS_RX_START_MODE(IR_InitStruct->IR_RxStartMode));
+        assert_param(IS_IR_RX_THRESHOLD(IR_InitStruct->IR_RxFIFOThrLevel));
+        assert_param(IS_IR_RX_FIFO_FULL_CTRL(IR_InitStruct->IR_RxFIFOFullCtrl));
+        assert_param(IS_RX_RX_TRIGGER_EDGE(IR_InitStruct->IR_RxTriggerMode));
+        assert_param(IS_IR_RX_FILTER_TIME_CTRL(IR_InitStruct->IR_RxFilterTime));
+        assert_param(IS_IR_RX_COUNT_LEVEL_CTRL(IR_InitStruct->IR_RxCntThrType));
+        assert_param(IS_IR_RX_COUNTER_THRESHOLD(IR_InitStruct->IR_RxCntThr));
+
+        /* Stop Receiving mode */
+        IR_RX_CONFIG_TypeDef ir_0x18 = {.d32 = IR->IR_RX_CONFIG};
+        ir_0x18.b.ir_rx_start = 0;
+        IR->IR_RX_CONFIG = ir_0x18.d32;
+
+        /* Enable RX mode */
+        IR_TX_CONFIG_TypeDef ir_0x04 = {.d32 = IR->IR_TX_CONFIG};
+        ir_0x04.b.ir_mode_sel = IR_InitStruct->IR_Mode;
+        IR->IR_TX_CONFIG = ir_0x04.d32;
+
+        /* Configure RX mode parameters and disable all RX interrupt */
+        ir_0x18.b.ir_rx_start_mode = IR_InitStruct->IR_RxStartMode;
+        ir_0x18.b.ir_rx_trigger_mode = IR_InitStruct->IR_RxTriggerMode;
+        ir_0x18.b.ir_rx_filter_stage = IR_InitStruct->IR_RxFilterTime;
+        ir_0x18.b.ir_rx_fifo_discard_set = IR_InitStruct->IR_RxFIFOFullCtrl;
+        ir_0x18.b.ir_rx_fifo_level_th = IR_InitStruct->IR_RxFIFOThrLevel;
+        IR->IR_RX_CONFIG = ir_0x18.d32;
+
+        /* Configure IR RX counter threshold parameters */
+        IR_RX_CNT_INT_SEL_TypeDef ir_0x24 = {.d32 = IR->IR_RX_CNT_INT_SEL};
+        ir_0x24.b.ir_rx_cnt_thr_trigger_lv = IR_InitStruct->IR_RxCntThrType;
+        ir_0x24.b.ir_rx_cnt_thr = IR_InitStruct->IR_RxCntThr;
+        IR->IR_RX_CNT_INT_SEL = ir_0x24.d32;
+
+        /* Clear all RX interrupt and RX FIFO */
+        IR->IR_RX_INT_CLR = IR_RX_INT_ALL_CLR | IR_RF_CLR;
+
+        /* Config dma rx */
+        IR_DMA_CONFIG_TypeDef ir_0x50 = {.d32 = IR->IR_DMA_CONFIG};
+        ir_0x50.b.reg_dma_rx_en = IR_InitStruct->IR_RxDmaEn;
+        ir_0x50.b.reg_dma_rx_fifo_th = IR_InitStruct->IR_RxWaterLevel;
+        IR->IR_DMA_CONFIG = ir_0x50.d32;
+    }
+}
+
+/**
+  * \brief  Fills each IR_InitStruct member with its default value.
+  * \param  IR_InitStruct: Pointer to an IR_InitTypeDef structure which will be initialized.
+  * \return None
+  */
+void IR_StructInit(IR_InitTypeDef *IR_InitStruct)
+{
+    /* IR source clock is 40MHz */
+    IR_InitStruct->IR_Clock             = IR_CLOCK_40M;
+    /* IR carrier freqency is 38KHz */
+    IR_InitStruct->IR_Freq              = 38000;
+    IR_InitStruct->IR_DutyCycle         = 3;
+    /* IR transmitting mode */
+    IR_InitStruct->IR_Mode              = IR_MODE_TX;
+    /* Tx pin output low when tx is idle */
+    IR_InitStruct->IR_TxIdleLevel       = IR_IDLE_OUTPUT_LOW;
+    /* Do not inverse tx data */
+    IR_InitStruct->IR_TxInverse         = IR_TX_DATA_NORMAL;
+    /* Configure RX FIFO threshold level to trigger IR_INT_RF_LEVEL interrupt */
+    /* Tx fifo depth: 32 bytes */
+    IR_InitStruct->IR_TxFIFOThrLevel    = 0;
+    /* Rx auto start */
+    IR_InitStruct->IR_RxStartMode       = IR_RX_AUTO_MODE;
+    /* Rx fifo depth: 32 bytes */
+    IR_InitStruct->IR_RxFIFOThrLevel    = 0;
+    /* Discard the oldest received dta if RX FIFO is full */
+    IR_InitStruct->IR_RxFIFOFullCtrl    = IR_RX_FIFO_FULL_DISCARD_NEWEST;
+    /* Falling edge will trigger rx */
+    IR_InitStruct->IR_RxTriggerMode     = IR_RX_FALL_EDGE;
+    /* If high to low or low to high transition time <= 50ns,Filter out it. */
+    IR_InitStruct->IR_RxFilterTime      = IR_RX_FILTER_TIME_50ns;
+    /* Configure trigger type */
+    IR_InitStruct->IR_RxCntThrType      = IR_RX_Count_Low_Level;
+    /* Configure RX counter threshold.You can use it to decide to stop receiving IR data
+       This value can be 0 to 0x7fffffff */
+    IR_InitStruct->IR_RxCntThr          = 0x23a;
+    /* Disable tx dma */
+    IR_InitStruct->IR_TxDmaEn           = DISABLE;
+    /* IR Tx waterlevel, should be less than fifo threshold.
+       The best value is IR FIFO Depth - GDMA Msize */
+    IR_InitStruct->IR_TxWaterLevel      = 31;
+    /* Disable rx dma */
+    IR_InitStruct->IR_RxDmaEn           = DISABLE;
+    /* IR Rx waterlevel, should be less than fifo threshold.
+       The best value is GDMA Msize */
+    IR_InitStruct->IR_RxWaterLevel      = 1;
+}
+
+/**
+  * \brief  Enable or disable the selected IR mode.
+  * \param  mode: Selected IR operation mode.
+  *         This parameter can be the following values:
+  *         \arg IR_MODE_TX: Transmission mode.
+  *         \arg IR_MODE_RX: Receiving mode.
+  * \param  NewState: New state of the operation mode.
+  *         This parameter can be: ENABLE or DISABLE.
+  * \return None
+  */
+void IR_Cmd(uint32_t mode, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_IR_MODE(mode));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+    if (mode == IR_MODE_TX)
+    {
+        /* Start or stop Transmission mode */
+        IR_TX_CONFIG_TypeDef ir_0x04 = {.d32 = IR->IR_TX_CONFIG};
+        ir_0x04.b.ir_tx_start = NewState;
+        IR->IR_TX_CONFIG = ir_0x04.d32;
+    }
+    else
+    {
+        /* Start or stop Receiving mode */
+        IR_RX_CONFIG_TypeDef ir_0x18 = {.d32 = IR->IR_RX_CONFIG};
+        ir_0x18.b.ir_rx_start = NewState;
+        IR->IR_RX_CONFIG = ir_0x18.d32;
+    }
+}
+
+/**
+  * \brief  Mask or unmask the specified IR interrupts.
+  * \param  IR_INT: Specifies the IR interrupts sources to be mask or unmask.
+  *         This parameter can be the following values:
+  *         \arg IR_INT_TF_EMPTY: TX FIFO empty interrupt.
+  *         \arg IR_INT_TF_LEVEL: TX FIFO threshold interrupt.
+  *         \arg IR_INT_TF_OF: TX FIFO overflow interrupt.
+  *         \arg IR_INT_TF_FINISH: TX finish interrupt.
+  *         \arg IR_INT_RF_FULL: RX FIFO  full interrupt.
+  *         \arg IR_INT_RF_LEVEL: RX FIFO threshold interrupt.
+  *         \arg IR_INT_RX_CNT_OF: RX counter overflow interrupt.
+  *         \arg IR_INT_RF_OF: RX FIFO overflow interrupt.
+  *         \arg IR_INT_RX_CNT_THR: RX counter threshold interrupt.
+  *         \arg IR_INT_RF_ERROR: RX FIFO error read interrupt. Trigger when RX FIFO empty and read RX FIFO.
+  *         \arg IR_INT_RISING_EDGE: IR RX Rising edge interrupt.
+  *         \arg IR_INT_FALLING_EDGE: IR RX Falling edge interrupt.
+  * \param  NewState: New state of the specified IR interrupts.
+  *         This parameter can be: ENABLE or DISABLE.
+  * \return None
+  */
+void IR_MaskINTConfig(uint32_t IR_INT, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_IR_INT_CONFIG(IR_INT));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    IR_TX_CONFIG_TypeDef ir_0x04 = {.d32 = IR->IR_TX_CONFIG};
+    if (NewState == ENABLE)
+    {
+        if (ir_0x04.b.ir_mode_sel)
+        {
+            /* Enable the selected IR interrupts in RX mode */
+            if (IR_INT & IR_RX_EXTENSION_INT)
+            {
+                IR->IR_RX_EX_INT |= (IR_INT & (~IR_RX_EXTENSION_INT)) << 2;
+            }
+            else
+            {
+                IR->IR_RX_CONFIG |= (IR_INT << IR_RX_MSK_TO_EN_Pos);
+            }
+        }
+        else
+        {
+            /* Enable the selected IR interrupts in TX mode */
+            if (IR_INT == IR_INT_TF_OF)
+            {
+                IR->IR_TX_CONFIG |= (IR_INT << IR_TX_FIFO_OVER_MSK_TO_EN_Pos);
+            }
+#if (IR_SUPPORT_TX_FINISH_INTERRUPT == 1)
+            else if (IR_INT == IR_INT_TX_FINISH)
+            {
+                IR->IR_TX_SR |= IR_INT << 1;
+            }
+#endif
+            else
+            {
+                IR->IR_TX_CONFIG |= (IR_INT << IR_TX_MSK_TO_EN_Pos);
+            }
+        }
+    }
+    else
+    {
+        if (ir_0x04.b.ir_mode_sel)
+        {
+            /* Disable the selected IR interrupts in RX mode */
+            if (IR_INT & IR_RX_EXTENSION_INT)
+            {
+                IR->IR_RX_EX_INT &= ~((IR_INT & (~IR_RX_EXTENSION_INT)) << 2);
+            }
+            else
+            {
+                IR->IR_RX_CONFIG &= (~(IR_INT << IR_RX_MSK_TO_EN_Pos));
+            }
+        }
+        else
+        {
+            /* Disable the selected IR interrupts in TX mode */
+            if (IR_INT == IR_INT_TF_OF)
+            {
+                IR->IR_TX_CONFIG &= (~(IR_INT << IR_TX_FIFO_OVER_MSK_TO_EN_Pos));
+            }
+#if (IR_SUPPORT_TX_FINISH_INTERRUPT == 1)
+            else if (IR_INT == IR_INT_TX_FINISH)
+            {
+                IR->IR_TX_SR &= ~(IR_INT << 1);
+            }
+#endif
+            else
+            {
+                IR->IR_TX_CONFIG &= (~(IR_INT << IR_TX_MSK_TO_EN_Pos));
+            }
+        }
+    }
+}
+
+/**
+  * \brief  Enable or disable the specified IR interrupts.
+  * \param  IR_INT: Specifies the IR interrupts sources to be enabled or disabled.
+  *         This parameter can be the following values:
+  *         \arg IR_INT_TF_EMPTY: TX FIFO empty interrupt.
+  *         \arg IR_INT_TF_LEVEL: TX FIFO threshold interrupt.
+  *         \arg IR_INT_TF_OF: TX FIFO overflow interrupt.
+  *         \arg IR_INT_TF_FINISH: TX finish interrupt.
+  *         \arg IR_INT_RF_FULL: RX FIFO  full interrupt.
+  *         \arg IR_INT_RF_LEVEL: RX FIFO threshold interrupt.
+  *         \arg IR_INT_RX_CNT_OF: RX counter overflow interrupt.
+  *         \arg IR_INT_RF_OF: RX FIFO overflow interrupt.
+  *         \arg IR_INT_RX_CNT_THR: RX counter threshold interrupt.
+  *         \arg IR_INT_RF_ERROR: RX FIFO error read interrupt. Trigger when RX FIFO empty and read RX FIFO.
+  *         \arg IR_INT_RISING_EDGE: IR RX Rising edge interrupt.
+  *         \arg IR_INT_FALLING_EDGE: IR RX Falling edge interrupt.
+  * \param  NewState: New state of the specified IR interrupts.
+  *         This parameter can be: ENABLE or DISABLE.
+  * \return None
+  */
+void IR_INTConfig(uint32_t IR_INT, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_IR_INT_CONFIG(IR_INT));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    IR_TX_CONFIG_TypeDef ir_0x04 = {.d32 = IR->IR_TX_CONFIG};
+    if (NewState == ENABLE)
+    {
+        if (ir_0x04.b.ir_mode_sel)
+        {
+            /* Enable the selected IR interrupts in RX mode */
+            if (IR_INT & IR_RX_EXTENSION_INT)
+            {
+                IR->IR_RX_EX_INT |= IR_INT & (~IR_RX_EXTENSION_INT);
+            }
+            else
+            {
+                IR->IR_RX_CONFIG |= IR_INT;
+            }
+        }
+        else
+        {
+#if (IR_SUPPORT_TX_FINISH_INTERRUPT == 1)
+            if (IR_INT == IR_INT_TX_FINISH)
+            {
+                IR->IR_TX_SR |= IR_INT;
+            }
+            else
+            {
+                /* Enable the selected IR interrupts in TX mode */
+                IR->IR_TX_CONFIG |= IR_INT;
+            }
+#else
+            /* Enable the selected IR interrupts in TX mode */
+            IR->IR_TX_CONFIG |= IR_INT;
+#endif
+        }
+    }
+    else
+    {
+        if (ir_0x04.b.ir_mode_sel)
+        {
+            /* Disable the selected IR interrupts in RX mode */
+            if (IR_INT & IR_RX_EXTENSION_INT)
+            {
+                IR->IR_RX_EX_INT &= ~(IR_INT & (~IR_RX_EXTENSION_INT));
+            }
+            else
+            {
+                IR->IR_RX_CONFIG &= (~IR_INT);
+            }
+        }
+        else
+        {
+#if (IR_SUPPORT_TX_FINISH_INTERRUPT == 1)
+            if (IR_INT == IR_INT_TX_FINISH)
+            {
+                IR->IR_TX_SR &= (~IR_INT);
+            }
+            else
+            {
+                /* Disable the selected IR interrupts in TX mode */
+                IR->IR_TX_CONFIG &= (~IR_INT);
+            }
+#else
+            /* Disable the selected IR interrupts in TX mode */
+            IR->IR_TX_CONFIG &= (~IR_INT);
+#endif
+        }
+    }
+}
+
+/**
+  * \brief   Start trigger only in manual receive mode.
+  * \param  None.
+  * \return None
+  */
+void IR_StartManualRxTrigger(void)
+{
+    /* Start Rx manual mode */
+    IR_RX_CONFIG_TypeDef ir_0x18 = {.d32 = IR->IR_RX_CONFIG};
+    ir_0x18.b.ir_rx_man_start = 0x01;
+    IR->IR_RX_CONFIG = ir_0x18.d32;
+}
+
+/**
+  * \brief  Configure counter threshold value in receiving mode.You can use it to stop receiving IR data.
+  * \param  IR_RxCntThrType: This parameter can be the following values:
+  *         \arg IR_RX_Count_Low_Level: Low level counter value >= IR_RxCntThr, trigger IR_INT_RX_CNT_THR interrupt.
+  *         \arg IR_RX_Count_High_Level: High level counter value >= IR_RxCntThr, trigger IR_INT_RX_CNT_THR interrupt.
+  * \param  IR_RxCntThr: Configure IR Rx counter threshold value which can be 0 to 0x7fffffffUL.
+  * \return None
+  */
+void IR_SetRxCounterThreshold(uint32_t IR_RxCntThrType, uint32_t IR_RxCntThr)
+{
+    /* Check the parameters */
+    assert_param(IS_IR_RX_COUNT_LEVEL_CTRL(IR_RxCntThrType));
+    assert_param(IS_IR_RX_COUNTER_THRESHOLD(IR_RxCntThr));
+
+    /* Configure IR RX counter threshold parameters */
+    IR_RX_CNT_INT_SEL_TypeDef ir_0x24 = {.d32 = IR->IR_RX_CNT_INT_SEL};
+    ir_0x24.b.ir_rx_cnt_thr = IR_RxCntThr;
+    ir_0x24.b.ir_rx_cnt_thr_trigger_lv = IR_RxCntThrType;
+    IR->IR_RX_CNT_INT_SEL = ir_0x24.d32;
+}
+
+/**
+  * \brief  Send data.
+  * \param  pBuf: data buffer to send.
+  * \param  len: buffer length.
+  * \param  IsLastPacket: Is it the last package of data.
+  *         This parameter can be the following values:
+  *         \arg ENABLE: The last data in IR packet and there is no continous data.In other words, An infrared data transmission is completed.
+  *         \arg DISABLE: There is data to be transmitted continuously.
+  * \return None
+  */
+void IR_SendBuf(uint32_t *pBuf, uint32_t len, FunctionalState IsLastPacket)
+{
+    /* Check the parameters */
+    assert_param(IS_FUNCTIONAL_STATE(IsLastPacket));
+
+    uint32_t i = 0;
+    if (len > 0)
+    {
+        i = len - 1;
+        while (i--)
+        {
+            IR->IR_TX_FIFO = *pBuf++;
+        }
+
+        /* If send the last IR packet, SET the following bit */
+        if (IsLastPacket == ENABLE)
+        {
+            IR->IR_TX_FIFO = (IR_TX_LAST_PACKEET_Msk | *pBuf);
+        }
+        else
+        {
+            IR->IR_TX_FIFO = *pBuf;
+        }
+    }
+}
+
+/**
+ * \brief  Send compensation data.
+ * \param  comp_type: Compensation data type.
+ *         \arg IR_COMPEN_FLAG_1_2_CARRIER: 1/2 carrier freqency.
+ *         \arg IR_COMPEN_FLAG_1_4_CARRIER: 1/4 carrier freqency.
+ *         \arg IR_COMPEN_FLAG_1_N_SYSTEM_CLK: MOD((0x48[27:16]+0x00[11:0]), 4095)/40MHz.
+ *         User can call function of IR_ConfigCompParam to configure 0x48[27:16].
+ * \param  buf: data buffer to send.
+ * \param  length: buffer length.
+ * \param  IsLastPacket: This parameter can be the following values:
+ *         \arg ENABLE: The last data in IR packet and there is no continous data.In other words, An infrared data transmission is completed.
+ *         \arg DISABLE: There is data to be transmitted continuously.
+ * \return None
+ */
+void IR_SendCompenBuf(IRTxCompen_TypeDef comp_type, uint32_t *pBuf, uint32_t len,
+                      FunctionalState IsLastPacket)
+{
+    /* Check the parameters */
+    assert_param(IS_FUNCTIONAL_STATE(IsLastPacket));
+
+    uint32_t i = 0;
+    uint32_t temp = 0;
+    if (len > 0)
+    {
+        i = len - 1;
+        while (i--)
+        {
+            if (*pBuf & IR_DATA_TYPE_Msk)
+            {
+                IR->IR_TX_FIFO = *pBuf++;
+            }
+            else
+            {
+                IR->IR_TX_FIFO = *pBuf++ | comp_type;
+            }
+        }
+
+        /* If send the last IR packet, SET the following bit */
+        if (IsLastPacket == ENABLE)
+        {
+            temp = IR_TX_LAST_PACKEET_Msk;
+        }
+
+        if (*pBuf & IR_DATA_TYPE_Msk)
+        {
+            IR->IR_TX_FIFO = (temp | *pBuf);
+        }
+        else
+        {
+            IR->IR_TX_FIFO = (temp | *pBuf | comp_type);
+        }
+    }
+}
+
+/**
+  * \brief  Read data From RX FIO.
+  * \param  pBuf: Buffer address to receive data.
+  * \param  len: Read data length.
+  * \return None
+  */
+void IR_ReceiveBuf(uint32_t *pBuf, uint32_t len)
+{
+    while (len--)
+    {
+        *pBuf++ = IR->IR_RX_FIFO;
+    }
+}
+
+/**
+  * \brief Get the specified IR interrupt status.
+  * \param  IR_INT: The specified IR interrupts.
+  *         This parameter can be one of the following values:
+  *         \arg IR_INT_TF_EMPTY: TX FIFO empty interrupt.
+  *         \arg IR_INT_TF_LEVEL: TX FIFO threshold interrupt.
+  *         \arg IR_INT_TF_OF: TX FIFO overflow interrupt.
+  *         \arg IR_INT_TF_FINISH: TX finish interrupt.
+  *         \arg IR_INT_RF_FULL: RX FIFO  full interrupt.
+  *         \arg IR_INT_RF_LEVEL: RX FIFO threshold interrupt.
+  *         \arg IR_INT_RX_CNT_OF: RX counter overflow interrupt.
+  *         \arg IR_INT_RF_OF: RX FIFO overflow interrupt.
+  *         \arg IR_INT_RX_CNT_THR: RX counter threshold interrupt.
+  *         \arg IR_INT_RF_ERROR: RX FIFO error read interrupt. Trigger when RX FIFO empty and read RX FIFO.
+  *         \arg IR_INT_RISING_EDGE: IR RX Rising edge interrupt.
+  *         \arg IR_INT_FALLING_EDGE: IR RX Falling edge interrupt.
+  * \return The new state of IR_INT (SET or RESET).
+  */
+ITStatus IR_GetINTStatus(uint32_t IR_INT)
+{
+    /* Check the parameters */
+    assert_param(IS_IR_INT_CONFIG(IR_INT));
+
+    ITStatus bit_status = RESET;
+
+    IR_TX_CONFIG_TypeDef ir_0x04 = {.d32 = IR->IR_TX_CONFIG};
+    if (ir_0x04.b.ir_mode_sel)
+    {
+        /* Get the selected IR interrupts in RX mode */
+        if (IR_INT & IR_RX_EXTENSION_INT)
+        {
+            if (IR->IR_RX_EX_INT & ((IR_INT & (~IR_RX_EXTENSION_INT)) << 4))
+            {
+                bit_status = SET;
+            }
+        }
+        else
+        {
+            if (IR->IR_RX_SR & IR_INT)
+            {
+                bit_status = SET;
+            }
+        }
+    }
+    else
+    {
+#if (IR_SUPPORT_TX_FINISH_INTERRUPT == 1)
+        if (IR_INT != IR_INT_TF_OF && IR_INT != IR_INT_TX_FINISH)
+#else
+        /* Get the selected IR interrupts in TX mode */
+        if (IR_INT != IR_INT_TF_OF)
+#endif
+        {
+            if (IR->IR_TX_SR & IR_INT)
+            {
+                bit_status = SET;
+            }
+        }
+        else
+        {
+            if (IR->IR_TX_SR & (IR_INT >> IR_TX_STATUS_TO_EN_Pos))
+            {
+                bit_status = SET;
+            }
+        }
+    }
+
+    /* Return the IR_INT status */
+    return  bit_status;
+}
+
+/**
+  * \brief  Clears the IR interrupt pending bits.
+  * \param  IR_IT: Specifies the interrupt pending bit to clear.
+  *         This parameter can be any combination of the following values:
+  *         \arg IR_INT_TF_EMPTY_CLR: Clear TX FIFO empty interrupt.
+  *         \arg IR_INT_TF_LEVEL_CLR: Clear TX FIFO threshold interrupt.
+  *         \arg IR_INT_TF_OF_CLR: Clear TX FIFO overflow interrupt.
+  *         \arg IR_INT_TX_FINISH_CLR: Clear TX finish interrupt.
+  *         \arg IR_INT_RF_FULL_CLR: Clear RX FIFO  full interrupt.
+  *         \arg IR_INT_RF_LEVEL_CLR: Clear RX FIFO threshold interrupt.
+  *         \arg IR_INT_RX_CNT_OF_CLR: Clear RX counter overflow interrupt.
+  *         \arg IR_INT_RF_OF_CLR: Clear RX FIFO overflow interrupt.
+  *         \arg IR_INT_RX_CNT_THR_CLR: Clear RX counter threshold interrupt.
+  *         \arg IR_INT_RF_ERROR_CLR: Clear RX FIFO error read interrupt. Trigger when RX FIFO empty and read RX FIFO.
+  *         \arg IR_INT_RX_RISING_EDGE_CLR: Clear RX Rising edge interrupt.
+  *         \arg IR_INT_RX_FALLING_EDGE_CLR: Clear RX Falling edge interrupt.
+  * \return None
+  */
+void IR_ClearINTPendingBit(uint32_t IR_CLEAR_INT)
+{
+    /* Check the parameters */
+    assert_param(IS_IR_INT_CLEAR(IR_CLEAR_INT));
+    IR_TX_CONFIG_TypeDef ir_0x04 = {.d32 = IR->IR_TX_CONFIG};
+
+    if (ir_0x04.b.ir_mode_sel)
+    {
+        /* Clear the selected IR interrupts in RX mode */
+//        if (IR_CLEAR_INT & IR_RX_EXTENSION_INT)
+//        {
+//            IR->IR_RX_EX_INT |= (IR_CLEAR_INT & 0xC0);
+//        }
+//        else
+//        {
+        IR->IR_RX_INT_CLR |= IR_CLEAR_INT;
+//        }
+    }
+    else
+    {
+        /* Clear the selected IR interrupts in TX mode */
+        IR->IR_TX_INT_CLR |= IR_CLEAR_INT;
+    }
+}
+
+/**
+  * \brief Get free size of TX FIFO.
+  * \param None.
+  * \return The free size of TX FIFO.
+  */
+uint16_t IR_GetTxFIFOFreeLen(void)
+{
+    IR_TX_SR_TypeDef ir_0x08 = {.d32 = IR->IR_TX_SR};
+    return (uint16_t)(IR_TX_FIFO_SIZE - ir_0x08.b.ir_tx_fifo_offset);
+}
+
+/**
+  * \brief Get data size in RX FIFO.
+  * \param None.
+  * \return Current data size in RX FIFO.
+  */
+uint16_t IR_GetRxDataLen(void)
+{
+    IR_RX_SR_TypeDef ir_0x1c = {.d32 = IR->IR_RX_SR};
+    return ((uint16_t)(ir_0x1c.b.ir_rx_fifo_offset));
+}
+
+/**
+  * \brief   Send one data.
+  * \param data: Send data.
+  * \return  None.
+  */
+void IR_SendData(uint32_t data)
+{
+    IR->IR_TX_FIFO = data;
+}
+
+/**
+  * \brief Read one data.
+  * \param None.
+  * \return Data which read from RX FIFO.
+  */
+uint32_t IR_ReceiveData(void)
+{
+    return IR->IR_RX_FIFO;
+}
+
+/**
+  * \brief  Set tx threshold, when TX FIFO depth <= threshold value trigger interrupt.
+  * \param thd: Tx threshold.
+  * \return None.
+  */
+void IR_SetTxThreshold(uint8_t thd)
+{
+    IR_TX_CONFIG_TypeDef ir_0x04 = {.d32 = IR->IR_TX_CONFIG};
+    ir_0x04.b.ir_tx_fifo_level_th = thd;
+    IR->IR_TX_CONFIG = ir_0x04.d32;
+}
+
+/**
+  * \brief   Set tx threshold, when RX FIFO depth >= threshold value trigger interrupt.
+  * \param thd: Rx threshold.
+  * \return  None.
+  */
+void IR_SetRxThreshold(uint8_t thd)
+{
+    IR_RX_CONFIG_TypeDef ir_0x18 = {.d32 = IR->IR_RX_CONFIG};
+    ir_0x18.b.ir_rx_fifo_level_th = thd;
+    IR->IR_RX_CONFIG = ir_0x18.d32;
+}
+
+/**
+  * \brief Get IR RX current count.
+  * \param None.
+  * \return Current counter.
+  */
+uint32_t IR_GetRxCurrentCount(void)
+{
+    IR_RX_CUR_CNT_TypeDef ir_0x30 = {.d32 = IR->IR_RX_CUR_CNT};
+    return ir_0x30.b.ir_rx_cur_cnt;
+}
+
+/**
+  * \brief Clear IR TX FIFO.
+  * \param None.
+  * \return None.
+  */
+void IR_ClearTxFIFO(void)
+{
+    IR_TX_INT_CLR_TypeDef ir_0x10 = {.d32 = IR->IR_TX_INT_CLR};
+    ir_0x10.b.ir_tx_fifo_clr = 0x01;
+    IR->IR_TX_INT_CLR = ir_0x10.d32;
+}
+
+/**
+  * \brief Clear IR RX FIFO.
+  * \param None.
+  * \return  None.
+  */
+void IR_ClearRxFIFO(void)
+{
+    IR_RX_INT_CLR_TypeDef ir_0x20 = {.d32 = IR->IR_RX_INT_CLR};
+    ir_0x20.b.ir_rx_fifo_clr = 0x01;
+    IR->IR_RX_INT_CLR = ir_0x20.d32;
+}
+
+/**
+  * \brief Check whether the specified IR flag is set.
+  * \param IR_FLAG: Specifies the flag to check.
+  *        This parameter can be one of the following values:
+  *        \arg IR_FLAG_TF_EMPTY: TX FIFO empty or not. If SET, TX FIFO is empty.
+  *        \arg IR_FLAG_TF_FULL: TX FIFO full or not. If SET, TX FIFO is full.
+  *        \arg IR_FLAG_TX_RUN: TX run or not. If SET, TX is running.
+  *        \arg IR_FLAG_RF_EMPTY: RX FIFO empty or not. If SET, RX FIFO is empty.
+  *        \arg IR_FLAG_RF_FULL: RX FIFO full or not. If SET, RX FIFO is full.
+  *        \arg IR_FLAG_RX_RUN: RX run or not. If SET, RX is running.
+  *
+  * \return The new state of IR_FLAG (SET or RESET).
+  */
+FlagStatus IR_GetFlagStatus(uint32_t IR_FLAG)
+{
+
+    /* Check the parameters */
+    assert_param(IS_IR_FLAG(IR_FLAG));
+
+    FlagStatus bitstatus = RESET;
+
+    IR_TX_CONFIG_TypeDef ir_0x04 = {.d32 = IR->IR_TX_CONFIG};
+    if (ir_0x04.b.ir_mode_sel)
+    {
+        if (IR->IR_RX_SR & IR_FLAG)
+        {
+            bitstatus = SET;
+        }
+        return bitstatus;
+    }
+    else
+    {
+        if (IR->IR_TX_SR & IR_FLAG)
+        {
+            bitstatus = SET;
+        }
+        return bitstatus;
+    }
+}
+
+/**
+  * \brief   Set or reset tx data inverse.
+  * \param NewState: This parameter can be: ENABLE or DISABLE.
+  * \return  None.
+  */
+void IR_SetTxInverse(FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    IR_TX_CONFIG_TypeDef ir_0x04 = {.d32 = IR->IR_TX_CONFIG};
+    ir_0x04.b.ir_tx_de_inverse = NewState;
+    IR->IR_TX_CONFIG = ir_0x04.d32;
+}
+
+/**
+  * \brief  Enbale TX output inverse or not.
+  * \param NewState: This parameter can be: ENABLE or DISABLE.
+  * \return None.
+  */
+void IR_TxOutputInverse(FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    IR_TX_CONFIG_TypeDef ir_0x04 = {.d32 = IR->IR_TX_CONFIG};
+    ir_0x04.b.ir_tx_output_inverse = NewState;
+    IR->IR_TX_CONFIG = ir_0x04.d32;
+}
+
+/**
+  * \brief Get IR RX Level.
+  * \param None.
+  * \return Current Level.
+  */
+uint32_t IR_GetRxCurrentLevel(void)
+{
+    return (IR->IR_RX_LEVEL);
+
+}
+#if IR_SUPPORT_RAP_FUNCTION
+void IR_RAPModeCmd(FunctionalState NewState)
+{
+    IR_TASK_CTRL_TypeDef ir_0x54 = {.d32 = IR->IR_TASK_CTRL};
+    ir_0x54.b.ir_rap_mode = NewState;
+    IR->IR_TASK_CTRL = ir_0x54.d32;
+
+    return;
+}
+
+void IR_TaskTrigger(uint32_t Task)
+{
+    IR_TASK_CTRL_TypeDef ir_0x54 = {.d32 = IR->IR_TASK_CTRL};
+    if (Task == IR_TASK_START_TX)
+    {
+        ir_0x54.b.ir_fw_task_start_tx = 0x1;
+    }
+    else if (Task == IR_TASK_START_RX)
+    {
+        ir_0x54.b.ir_fw_task_start_rx = 0x1;
+    }
+    IR->IR_TASK_CTRL = ir_0x54.d32;
+
+    return;
+}
+
+void IR_RAPQactiveCtrl(uint32_t Qactive, FunctionalState NewState)
+{
+    IR_QACTIVE_CTRL_TypeDef ir_0x58 = {.d32 = IR->IR_QACTIVE_CTRL};
+    if (Qactive == IR_QACTIVE_ICG_PCLK)
+    {
+        ir_0x58.b.qact_pclk_icg_en = NewState;
+    }
+    if (Qactive == IR_QACTIVE_FW_FORCE_SCLK)
+    {
+        ir_0x58.b.qact_sclk_force_en = NewState;
+    }
+    if (Qactive == IR_QACTIVE_FW_FORCE_PCLK)
+    {
+        ir_0x58.b.qact_pclk_force_en = NewState;
+    }
+    IR->IR_QACTIVE_CTRL = ir_0x58.d32;
+
+    return;
+}
+#endif
+
diff --git a/bee/drivers/ir/src/device/rtl87x2g/rtl_ir.h b/bee/drivers/ir/src/device/rtl87x2g/rtl_ir.h
new file mode 100644
index 00000000..768fc1de
--- /dev/null
+++ b/bee/drivers/ir/src/device/rtl87x2g/rtl_ir.h
@@ -0,0 +1,1137 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *               Define to prevent recursive inclusion
+ *============================================================================*/
+#ifndef RTL_IR_H
+#define RTL_IR_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*============================================================================*
+ *                        Header Files
+ *============================================================================*/
+#include "utils/rtl_utils.h"
+#include "rtl_ir_def.h"
+
+/** \defgroup IR          IR
+  * \brief
+  * \{
+  */
+
+/*============================================================================*
+ *                         Constants
+ *============================================================================*/
+/** \defgroup IR_Exported_Constants IR Exported Constants
+  * \brief
+  * \{
+  */
+
+/**
+ * \defgroup    IR_FIFO_Size IR FIFO Size
+ * \{
+ * \ingroup     IR_Exported_Constants
+ */
+#define IR_TX_FIFO_SIZE                   32  //!< I2C TX FIFO SIZE is 32.
+#define IR_RX_FIFO_SIZE                   32  //!< I2C RX FIFO SIZE is 32.
+
+/** End of IR_FIFO_Size
+  * \}
+  */
+
+/**
+ * \defgroup    IR_Mode IR Mode
+ * \{
+ * \ingroup     IR_Exported_Constants
+ */
+typedef enum
+{
+    IR_MODE_TX = 0x00, //!< IR TX mode.
+    IR_MODE_RX = 0x01, //!< IR RX mode.
+} IRMode_TypeDef;
+
+#define IS_IR_MODE(MODE) (((MODE) == IR_MODE_TX) || ((MODE) == IR_MODE_RX)) //!< Check if the input parameter is valid.
+
+/** End of IR_Mode
+  * \}
+  */
+
+/**
+ * \defgroup    IR_Idle_Status IR Idle Status
+ * \{
+ * \ingroup     IR_Exported_Constants
+ */
+typedef enum
+{
+    IR_IDLE_OUTPUT_LOW = 0x00,  //!< TX output high level in idle.
+    IR_IDLE_OUTPUT_HIGH = 0x01, //!< TX output low level in idle.
+} IRIdleStatus_TypeDef;
+
+#define IS_IR_IDLE_STATUS(LEVEL) (((LEVEL) == IR_IDLE_OUTPUT_HIGH) || ((LEVEL) == IR_IDLE_OUTPUT_LOW)) //!< Check if the input parameter is valid.
+
+/** End of IR_Idle_Status
+  * \}
+  */
+
+/**
+ * \defgroup    IR_TX_Data_Type IR TX Data Type
+ * \{
+ * \ingroup     IR_Exported_Constants
+ */
+typedef enum
+{
+    IR_TX_DATA_NORMAL = 0x00,  //!< Not inverse TX FIFO define.
+    IR_TX_DATA_INVERSE = 0x01, //!< Inverse TX FIFO define.
+} IRTxDataType_TypeDef;
+
+#define IS_IR_TX_DATA_TYPE(TYPE) (((TYPE) == IR_TX_DATA_NORMAL) || ((TYPE) == IR_TX_DATA_INVERSE)) //!< Check if the input parameter is valid.
+
+/** End of IR_TX_Data_Type
+  * \}
+  */
+
+/**
+ * \defgroup    IR_Threshold IR Threshold
+ * \{
+ * \ingroup     IR_Exported_Constants
+ */
+#define IS_IR_TX_THRESHOLD(THD)  ((THD) <= IR_TX_FIFO_SIZE) //!< IR TX Threshold must range from 0 to 32.
+#define IS_IR_RX_THRESHOLD(THD) ((THD) <= IR_RX_FIFO_SIZE)  //!< IR RX Threshold must range from 0 to 32.
+
+/** End of IR_Threshold
+  * \}
+  */
+
+/**
+ * \defgroup    IR_RX_Start_Mode IR RX Start Mode
+ * \{
+ * \ingroup     IR_Exported_Constants
+ */
+typedef enum
+{
+    IR_RX_MANUAL_MODE = 0x00, //!< Manual mode.
+    IR_RX_AUTO_MODE = 0x01,   //!< Auto mode.
+} IRRxStartMode_TypeDef;
+
+#define IS_RX_START_MODE(MODE) (((MODE) == IR_RX_AUTO_MODE) || ((MODE) == IR_RX_MANUAL_MODE)) //!< Check if the input parameter is valid.
+
+/** End of RX_Start_Mode
+  * \}
+  */
+
+/**
+ * \defgroup    IR_RX_FIFO_Discard_Setting IR RX FIFO Discard Setting
+ * \{
+ * \ingroup     IR_Exported_Constants
+ */
+typedef enum
+{
+    IR_RX_FIFO_FULL_DISCARD_NEWEST = 0x00, //!< Discard oldest data in FIFO when RX FIFO is full and new data send to FIFO.
+    IR_RX_FIFO_FULL_DISCARD_OLDEST = 0x01, //!< Reject new data data send to FIFO when RX FIFO is full.
+} IRRxFifoDiscardSetting_TypeDef;
+
+#define IS_IR_RX_FIFO_FULL_CTRL(CTRL)  (((CTRL) == IR_RX_FIFO_FULL_DISCARD_NEWEST) || ((CTRL) == IR_RX_FIFO_FULL_DISCARD_OLDEST)) //!< Check if the input parameter is valid.
+
+/** End of IR_RX_FIFO_Discard_Setting
+  * \}
+  */
+
+/**
+ * \defgroup    IR_RX_Trigger_Mode IR RX Trigger Mode
+ * \{
+ * \ingroup     IR_Exported_Constants
+ */
+typedef enum
+{
+    IR_RX_FALL_EDGE = 0x00,   //!< IR RX trigger mode is falling edge trigger.
+    IR_RX_RISING_EDGE = 0x01, //!< IR RX trigger mode is rising edge trigger.
+    IR_RX_DOUBLE_EDGE = 0x02, //!< IR RX trigger mode is double edge trigger.
+} IRRxTriggerMode_TypeDef;
+
+#define IS_RX_RX_TRIGGER_EDGE(EDGE) (((EDGE) == IR_RX_FALL_EDGE) || ((EDGE) == IR_RX_RISING_EDGE) || ((EDGE) == IR_RX_DOUBLE_EDGE)) //!< Check if the input parameter is valid.
+
+/** End of RX_Trigger_Mode
+  * \}
+  */
+
+/**
+ * \defgroup    IR_RX_Filter_Time IR RX Filter Time
+ * \{
+ * \ingroup     IR_Exported_Constants
+ */
+typedef enum
+{
+    IR_RX_FILTER_TIME_50ns  = 0x00, //!< IR RX filter time is 50ns.
+    IR_RX_FILTER_TIME_75ns  = 0x01, //!< IR RX filter time is 75ns.
+    IR_RX_FILTER_TIME_100ns = 0x02, //!< IR RX filter time is 100ns.
+    IR_RX_FILTER_TIME_125ns = 0x03, //!< IR RX filter time is 125ns.
+    IR_RX_FILTER_TIME_150ns = 0x04, //!< IR RX filter time is 150ns.
+    IR_RX_FILTER_TIME_175ns = 0x05, //!< IR RX filter time is 175ns.
+    IR_RX_FILTER_TIME_200ns = 0x06, //!< IR RX filter time is 200ns.
+    IR_RX_FILTER_TIME_225ns = 0x07, //!< IR RX filter time is 225ns.
+} IRRxFilterTime_TypeDef;
+
+#define IS_IR_RX_FILTER_TIME_CTRL(CTRL)  (((CTRL) == IR_RX_FILTER_TIME_50ns) || \
+                                          ((CTRL) == IR_RX_FILTER_TIME_75ns) || \
+                                          ((CTRL) == IR_RX_FILTER_TIME_100ns) || \
+                                          ((CTRL) == IR_RX_FILTER_TIME_125ns) || \
+                                          ((CTRL) == IR_RX_FILTER_TIME_150ns) || \
+                                          ((CTRL) == IR_RX_FILTER_TIME_175ns) || \
+                                          ((CTRL) == IR_RX_FILTER_TIME_200ns) || \
+                                          ((CTRL) == IR_RX_FILTER_TIME_225ns)) //!< Check if the input parameter is valid.
+
+/** End of RX_Filter_Time
+  * \}
+  */
+
+/**
+ * \defgroup    IR_RX_Counter_Level IR RX Counter Level
+ * \{
+ * \ingroup     IR_Exported_Constants
+ */
+typedef enum
+{
+    IR_RX_Count_Low_Level  = 0x00,  //!< RX level timeout interrupt is low level trigger.
+    IR_RX_Count_High_Level  = 0x01, //!< RX level timeout interrupt is high level trigger.
+} IRRxCounterThresholdType_TypeDef;
+
+#define IS_IR_RX_COUNT_LEVEL_CTRL(CTRL)  (((CTRL) == IR_RX_Count_Low_Level) || ((CTRL) == IR_RX_Count_High_Level)) //!< Check if the input parameter is valid.
+
+/** End of IR_RX_Counter_Level
+  * \}
+  */
+
+/**
+ * \defgroup    IR_Compensation_Flag IR Compensation Flag
+ * \{
+ * \ingroup     IR_Exported_Constants
+ */
+typedef enum
+{
+    IR_COMPEN_FLAG_1_2_CARRIER = BIT28,            //!< 1/2 carrier cycle.
+    IR_COMPEN_FLAG_1_4_CARRIER = BIT29,            //!< 1/4 carrier cycle.
+    IR_COMPEN_FLAG_1_N_SYSTEM_CLK = BIT28 | BIT29, //!< 1/N carrier cycle.
+} IRTxCompen_TypeDef;
+
+/** End of IR_Compensation_Flag
+  * \}
+  */
+
+#if IR_SUPPORT_TX_MODE_CONFIG
+/**
+ * \defgroup    IR_Compensation_Flag IR Compensation Flag
+ * \{
+ * \ingroup     IR_Exported_Constants
+ */
+typedef enum
+{
+    IR_TX_PUSH_PULL,
+    IR_TX_OPEN_DRAIN,
+} IRTxOutputMode_TypeDef;
+
+/** End of IR_Compensation_Flag
+  * \}
+  */
+#endif
+
+/**
+ * \defgroup    IR_RX_Counter_Threshold IR RX Counter Threshold
+ * \{
+ * \ingroup     IR_Exported_Constants
+ */
+#define IS_IR_RX_COUNTER_THRESHOLD(THD) ((THD) <= 0x7fffffffUL) //!< IR RX counter threshold value must range from 0x0 to 0x7FFFFFFF.
+
+/** End of IR_RX_Counter_Threshold
+  * \}
+  */
+
+/**
+ * \defgroup    IR_Interrupt IR Interrupt
+ * \{
+ * \ingroup     IR_Exported_Constants
+ */
+/* All interrupts in transmission mode */
+#define IR_INT_TF_EMPTY                             BIT0 //!< TX FIFO empty interrupt source.
+#define IR_INT_TF_LEVEL                             BIT1 //!< TX FIFO threshold interrupt source.
+#define IR_INT_TF_OF                                BIT4 //!< TX FIFO overflow interrupt source.
+#if (IR_SUPPORT_TX_FINISH_INTERRUPT == 1)
+#define IR_INT_TX_FINISH                            BIT5
+#endif
+
+/* All interrupts in receiving mode */
+#define IR_INT_RF_FULL                              BIT0 //!< RX FIFO full interrupt source.
+#define IR_INT_RF_LEVEL                             BIT1 //!< RX FIFO threshold interrupt source.
+#define IR_INT_RX_CNT_OF                            BIT2 //!< RX counter overflow interrupt source.
+#define IR_INT_RF_OF                                BIT3 //!< RX FIFO overflow interrupt source.
+#define IR_INT_RX_CNT_THR                           BIT4 //!< RX counter timeout interrupt source.
+#define IR_INT_RF_ERROR                             BIT5 //!< RX FIFO error read interrupt source. Trigger when RX FIFO empty and read RX FIFO.
+#define IR_INT_RISING_EDGE                          ((uint32_t)(IR_RX_EXTENSION_INT | BIT1)) //!< RX rising edge interrupt source.
+#define IR_INT_FALLING_EDGE                         ((uint32_t)(IR_RX_EXTENSION_INT | BIT0)) //!< RX falling edge interrupt source.
+
+#if (IR_SUPPORT_TX_FINISH_INTERRUPT == 1)
+#define IS_IR_TX_INT_CONFIG(CONFIG)   (((CONFIG) == IR_INT_TF_EMPTY)   || \
+                                       ((CONFIG) == IR_INT_TF_LEVEL)   || \
+                                       ((CONFIG) == IR_INT_TF_OF)      || \
+                                       ((CONFIG) == IR_INT_TX_FINISH)) //!< Check if the input parameter is valid.
+#else
+#define IS_IR_TX_INT_CONFIG(CONFIG)   (((CONFIG) == IR_INT_TF_EMPTY)   || \
+                                       ((CONFIG) == IR_INT_TF_LEVEL)   || \
+                                       ((CONFIG) == IR_INT_TF_OF))) //!< Check if the input parameter is valid.
+#endif
+
+#define IS_IR_RX_INT_CONFIG(CONFIG)   (((CONFIG) == IR_INT_RF_FULL)     || \
+                                       ((CONFIG) == IR_INT_RF_LEVEL)   || \
+                                       ((CONFIG) == IR_INT_RX_CNT_OF)  || \
+                                       ((CONFIG) == IR_INT_RF_OF)      || \
+                                       ((CONFIG) == IR_INT_RX_CNT_THR) || \
+                                       ((CONFIG) == IR_INT_RF_ERROR)      || \
+                                       ((CONFIG) == IR_INT_RISING_EDGE) || \
+                                       ((CONFIG) == IR_INT_FALLING_EDGE)) //!< Check if the input parameter is valid.
+#define IS_IR_INT_CONFIG(CONFIG)      (IS_IR_TX_INT_CONFIG(CONFIG) || IS_IR_RX_INT_CONFIG(CONFIG)) //!< Check if the input parameter is valid.
+
+/** End of IR_Interrupt
+  * \}
+  */
+
+/**
+ * \defgroup    IR_Interrupts_Clear_Flag IR Interrupts Clear Flag
+ * \{
+ * \ingroup     IR_Exported_Constants
+ */
+/* Clear all interrupts in transmission mode */
+#define IR_TF_CLR                                   BIT0  //!< Clear TX FIFO interrupt status.
+#define IR_INT_TF_EMPTY_CLR                         BIT1  //!< Clear TX FIFO empty interrupt status.
+#define IR_INT_TF_LEVEL_CLR                         BIT2  //!< Clear TX FIFO threshold interrupt status.
+#define IR_INT_TF_OF_CLR                            BIT3  //!< Clear TX FIFO overflow interrupt status.
+#if (IR_SUPPORT_TX_FINISH_INTERRUPT == 1)
+#define IR_INT_TX_FINISH_CLR                        BIT4
+#endif
+
+#if (IR_SUPPORT_TX_FINISH_INTERRUPT == 1)
+#define IR_TX_INT_ALL_CLR                  (IR_INT_TF_EMPTY_CLR | \
+                                            IR_INT_TF_LEVEL_CLR | \
+                                            IR_INT_TF_OF_CLR    | \
+                                            IR_INT_TX_FINISH_CLR) //!< Check if the input parameter is valid.
+#else
+#define IR_TX_INT_ALL_CLR                  (IR_INT_TF_EMPTY_CLR | \
+                                            IR_INT_TF_LEVEL_CLR | \
+                                            IR_INT_TF_OF_CLR) //!< Check if the input parameter is valid.
+#endif
+
+/* Clear all interrupts in receiving mode */
+#define IR_INT_RF_FULL_CLR                         BIT0  //!< Clear RX FIFO full interrupt status.
+#define IR_INT_RF_LEVEL_CLR                        BIT1  //!< Clear RX FIFO threshold interrupt status.
+#define IR_INT_RX_CNT_OF_CLR                       BIT2  //!< Clear RX counter overflow interrupt status.
+#define IR_INT_RF_OF_CLR                           BIT3  //!< Clear RX FIFO overflow interrupt status.
+#define IR_INT_RX_CNT_THR_CLR                      BIT4  //!< Clear RX counter timeout interrupt status.
+#define IR_INT_RF_ERROR_CLR                        BIT5  //!< Clear RX FIFO error read interrupt status.
+#define IR_INT_RX_FALLING_EDGE_CLR                 BIT6  //!< Clear RX falling edge interrupt status.
+#define IR_INT_RX_RISING_EDGE_CLR                  BIT7  //!< Clear RX rising edge interrupt status.
+#define IR_RF_CLR                                  BIT8  //!< Clear RX FIFO interrupt status.
+
+#define IR_RX_INT_ALL_CLR                (IR_INT_RF_FULL_CLR | IR_INT_RF_LEVEL_CLR | \
+                                          IR_INT_RX_CNT_OF_CLR | IR_INT_RF_OF_CLR | \
+                                          IR_INT_RX_CNT_THR_CLR | IR_INT_RF_ERROR_CLR | \
+                                          IR_INT_RX_RISING_EDGE_CLR|IR_INT_RX_FALLING_EDGE_CLR) //!< Check if the input parameter is valid.
+
+#if (IR_SUPPORT_TX_FINISH_INTERRUPT == 1)
+#define IS_IR_INT_CLEAR(INT)            (((INT) == IR_INT_TF_EMPTY_CLR) || ((INT) == IR_INT_TF_LEVEL_CLR) || \
+                                         ((INT) == IR_INT_TF_OF_CLR) || ((INT) == IR_INT_TX_FINISH_CLR) || ((INT) == IR_INT_RF_FULL_CLR) || \
+                                         ((INT) == IR_INT_RF_LEVEL_CLR) || ((INT) == IR_INT_RX_CNT_OF_CLR) || \
+                                         ((INT) == IR_INT_RF_OF_CLR) || ((INT) == IR_INT_RX_CNT_THR_CLR) || \
+                                         ((INT) == IR_INT_RX_RISING_EDGE_CLR) || ((INT) == IR_INT_RX_FALLING_EDGE_CLR) || \
+                                         ((INT) == IR_INT_RF_ERROR_CLR)) //!< Check if the input parameter is valid.
+#else
+#define IS_IR_INT_CLEAR(INT)            (((INT) == IR_INT_TF_EMPTY_CLR) || ((INT) == IR_INT_TF_LEVEL_CLR) || \
+                                         ((INT) == IR_INT_TF_OF_CLR) || ((INT) == IR_INT_RF_FULL_CLR) || \
+                                         ((INT) == IR_INT_RF_LEVEL_CLR) || ((INT) == IR_INT_RX_CNT_OF_CLR) || \
+                                         ((INT) == IR_INT_RF_OF_CLR) || ((INT) == IR_INT_RX_CNT_THR_CLR) || \
+                                         ((INT) == IR_INT_RX_RISING_EDGE_CLR) || ((INT) == IR_INT_RX_FALLING_EDGE_CLR) || \
+                                         ((INT) == IR_INT_RF_ERROR_CLR)) //!< Check if the input parameter is valid.
+#endif
+
+/** End of IR_Interrupts_Clear_Flag
+  * \}
+  */
+
+/**
+ * \defgroup    IR_Flag IR Flag
+ * \{
+ * \ingroup     IR_Exported_Constants
+ */
+#define IR_FLAG_TF_EMPTY                       BIT15 //!< TX FIFO is empty or not.
+#define IR_FLAG_TF_FULL                        BIT14 //!< TX FIFO is full or not.
+#define IR_FLAG_TX_RUN                         BIT4  //!< TX state is running or idle.
+#define IR_FLAG_RF_EMPTY                       BIT17 //!< RX FIFO is empty or not.
+#define IR_FLAG_RF_FULL                        BIT16 //!< RX FIFO is full or not.
+#define IR_FLAG_RX_RUN                         BIT7  //!< RX state is running or idle.
+
+#define IS_IR_FLAG(FLAG)                (((FLAG) == IR_FLAG_TF_EMPTY) || ((FLAG) == IR_FLAG_TF_FULL) || \
+                                         ((FLAG) == IR_FLAG_TX_RUN) || ((FLAG) == IR_FLAG_RF_EMPTY) || \
+                                         ((FLAG) == IR_FLAG_RF_FULL) || ((FLAG) == IR_FLAG_RX_RUN)) //!< Check if the input parameter is valid.
+
+/** End of IR_Flag
+  * \}
+  */
+
+#if (IR_SUPPORT_RAP_FUNCTION == 1)
+/**
+ * \defgroup    IR_Qactive_Force TIM Qactive Force
+ * \{
+ * \ingroup     IR_Exported_Constants
+ */
+typedef enum
+{
+    IR_QACTIVE_ICG_PCLK = 0x0,
+    IR_QACTIVE_FW_FORCE_SCLK = 0x1,
+    IR_QACTIVE_FW_FORCE_PCLK = 0x2,
+} IRQactive_TypeDef;
+
+/** End of IR_Qactive_Force
+  * \}
+  */
+
+/**
+ * \defgroup    IR_Task TIM Task
+ * \{
+ * \ingroup     IR_Exported_Constants
+ */
+typedef enum
+{
+    IR_TASK_START_RX = 0,
+    IR_TASK_START_TX = 1,
+} IRTask_TypeDef;
+
+/** End of IR_Task
+  * \}
+  */
+#endif
+
+/** End of IR_Exported_Constants
+  * \}
+  */
+
+/*============================================================================*
+ *                         Types
+ *============================================================================*/
+/** \defgroup IR_Exported_Types IR Exported Types
+  * \brief
+  * \{
+  */
+
+/**
+ * \brief       IR init structure definition.
+ *
+ * \ingroup     IR_Exported_Types
+ */
+typedef struct
+{
+    IRClock_TypeDef IR_Clock;                         /*!< Specify the source clock frequency.
+                                                           This parameter can be a value of \ref IR_Clock. */
+
+    uint32_t IR_Freq;                                 /*!< Specify the clock frequency.
+                                                           This parameter is IR carrier freqency whose unit is Hz. */
+
+    float IR_DutyCycle;                               /*!< Specify the IR duty cycle. */
+
+    IRMode_TypeDef IR_Mode;                           /*!< Specify the IR mode.
+                                                           This parameter can be a value of \ref IR_Mode. */
+
+    IRIdleStatus_TypeDef IR_TxIdleLevel;              /*!< Specify the IR output level in Tx mode.
+                                                           This parameter can be a value of \ref IR_Idle_Status. */
+
+    IRTxDataType_TypeDef
+    IR_TxInverse;                                     /*!< Specify inverse FIFO data or not in TX mode.
+                                                           This parameter can be a value of \ref IR_TX_Data_Type. */
+
+    uint32_t IR_TxFIFOThrLevel;                       /*!< Specify TX FIFO interrupt threshold in TX mode.
+                                                           When TX FIFO depth <= threshold value, trigger interrupt.
+                                                           This parameter can be a value of 1 ~ 32. */
+
+    IRRxStartMode_TypeDef IR_RxStartMode;             /*!< Specify Start mode in RX mode.
+                                                           This parameter can be a value of \ref IR_RX_Start_Mode. */
+
+    uint32_t IR_RxFIFOThrLevel;                       /*!< Specify RX FIFO interrupt threshold in RX mode.
+                                                           When RX FIFO depth > threshold value, trigger interrupt.
+                                                           This parameter can be a value of 1 ~ 32. */
+
+    IRRxFifoDiscardSetting_TypeDef
+    IR_RxFIFOFullCtrl; /*!< Specify data discard mode in RX mode when RX FIFO is full and receiving new data.
+                                                           This parameter can be a value of \ref IR_RX_FIFO_Discard_Setting. */
+
+    IRRxTriggerMode_TypeDef IR_RxTriggerMode;         /*!< Specify trigger in RX mode.
+                                                           This parameter can be a value of \ref IR_RX_Trigger_Mode. */
+
+    IRRxFilterTime_TypeDef IR_RxFilterTime;           /*!< Specify filter time in RX mode.
+                                                           This parameter can be a value of \ref IR_RX_Filter_Time. */
+
+    IRRxCounterThresholdType_TypeDef
+    IR_RxCntThrType; /*!< Specify counter level type when trigger IR_INT_RX_CNT_THR interrupt in RX mode.
+                                                           This parameter can be a value of \ref IR_RX_Counter_Level. */
+
+    uint32_t IR_RxCntThr;                             /*!< Specify counter threshold value
+                                                           when trigger IR_INT_RX_CNT_THR interrupt in RX mode. */
+
+    FunctionalState IR_TxDmaEn;                       /*!< Specify the Tx dma mode.
+                                                           This parameter must be a value of DISABLE and ENABLE. */
+
+    uint8_t IR_TxWaterLevel;                          /*!< Specify the DMA tx water level.
+                                                           This parameter must range from 0 to 32.*/
+
+    FunctionalState IR_RxDmaEn;                       /*!< Specify the Rx dma mode.
+                                                           This parameter must be a value of DISABLE and ENABLE. */
+
+    uint8_t IR_RxWaterLevel;                          /*!< Specify the DMA rx water level.
+                                                           This parameter must range from 0 to 32.*/
+
+#if IR_SUPPORT_TX_MODE_CONFIG
+    IRTxOutputMode_TypeDef
+    IR_TxOutputMode;                                  /*!< Specify the IR Tx output mode.
+                                                           This parameter can be a value of \ref IR_TxOutputMode. */
+#endif
+} IR_InitTypeDef;
+
+/** End of IR_Exported_Types
+  * \}
+  */
+
+/*============================================================================*
+ *                         Functions
+ *============================================================================*/
+/** \defgroup IR_Exported_Functions IR Exported Functions
+  * \brief
+  * \{
+  */
+
+/**
+ * \brief Deinitialize the IR peripheral registers to their default values.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_ir_init(void)
+ * {
+ *     IR_DeInit();
+ * }
+ * \endcode
+ */
+void IR_DeInit(void);
+
+/**
+ * \brief   Initialize the IR peripheral according to the specified
+ *          parameters in IR_InitStruct.
+ *
+ * \param[in] IR_InitStruct  Pointer to a IR_InitTypeDef structure which will be initialized.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_ir_init(void)
+ * {
+ *     RCC_PeriphClockCmd(APBPeriph_IR, APBPeriph_IR_CLOCK, ENABLE);
+ *
+ *     IR_InitTypeDef IR_InitStruct;
+ *     IR_StructInit(&IR_InitStruct);
+ *
+ *     IR_InitStruct.IR_Freq               = 38000;
+ *     IR_InitStruct.IR_Mode               = IR_MODE_RX;
+ *     IR_InitStruct.IR_RxStartMode        = IR_RX_AUTO_MODE;
+ *     IR_InitStruct.IR_RxFIFOThrLevel     = IR_RX_FIFO_THR_LEVEL;
+ *     IR_InitStruct.IR_RxFIFOFullCtrl     = IR_RX_FIFO_FULL_DISCARD_NEWEST;
+ *     IR_InitStruct.IR_RxFilterTime       = IR_RX_FILTER_TIME_50ns;
+ *     IR_InitStruct.IR_RxTriggerMode      = IR_RX_FALL_EDGE;
+ *     IR_InitStruct.IR_RxCntThrType       = IR_RX_Count_High_Level;
+ *     IR_InitStruct.IR_RxCntThr           = 0x1F40;
+ *     IR_Init(&IR_InitStruct);
+ *     IR_Cmd(IR_MODE_RX, ENABLE);
+ *     IR_ClearRxFIFO();
+ * }
+ * \endcode
+ */
+void IR_Init(IR_InitTypeDef *IR_InitStruct);
+
+/**
+ * \brief  Fills each IR_InitStruct member with its default value.
+ *
+ * \note   The default settings for the IR_InitStruct member are shown in the following table:
+ *         | IR_InitStruct member  | Default value                            |
+ *         |:---------------------:|:----------------------------------------:|
+ *         | IR_Clock              | \ref IR_CLOCK_40M                        |
+ *         | IR_Freq               | 38000                                    |
+ *         | IR_DutyCycle          | 3                                        |
+ *         | IR_Mode               | \ref IR_MODE_TX                          |
+ *         | IR_TxIdleLevel        | \ref IR_IDLE_OUTPUT_LOW                  |
+ *         | IR_TxInverse          | \ref IR_TX_DATA_NORMAL                   |
+ *         | IR_TxFIFOThrLevel     | 0                                        |
+ *         | IR_RxStartMode        | \ref IR_RX_AUTO_MODE                     |
+ *         | IR_RxFIFOThrLevel     | 0                                        |
+ *         | IR_RxFIFOFullCtrl     | \ref IR_RX_FIFO_FULL_DISCARD_NEWEST      |
+ *         | IR_RxTriggerMode      | \ref IR_RX_FALL_EDGE                     |
+ *         | IR_RxFilterTime       | \ref IR_RX_FILTER_TIME_50ns              |
+ *         | IR_RxCntThrType       | \ref IR_RX_Count_Low_Level               |
+ *         | IR_RxCntThr           | 0x23a                                    |
+ *         | IR_TxDmaEn            | DISABLE                                  |
+ *         | IR_TxWaterLevel       | 31                                       |
+ *         | IR_RxDmaEn            | DISABLE                                  |
+ *         | IR_RxWaterLevel       | 1                                        |
+ *
+ * \param[in] IR_InitStruct: Pointer to an IR_InitTypeDef structure which will be initialized.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_ir_init(void)
+ * {
+ *     RCC_PeriphClockCmd(APBPeriph_IR, APBPeriph_IR_CLOCK, ENABLE);
+ *
+ *     IR_InitTypeDef IR_InitStruct;
+ *     IR_StructInit(&IR_InitStruct);
+ *
+ *     IR_InitStruct.IR_Freq               = 38000;
+ *     IR_InitStruct.IR_Mode               = IR_MODE_RX;
+ *     IR_InitStruct.IR_RxStartMode        = IR_RX_AUTO_MODE;
+ *     IR_InitStruct.IR_RxFIFOThrLevel     = IR_RX_FIFO_THR_LEVEL;
+ *     IR_InitStruct.IR_RxFIFOFullCtrl     = IR_RX_FIFO_FULL_DISCARD_NEWEST;
+ *     IR_InitStruct.IR_RxFilterTime       = IR_RX_FILTER_TIME_50ns;
+ *     IR_InitStruct.IR_RxTriggerMode      = IR_RX_FALL_EDGE;
+ *     IR_InitStruct.IR_RxCntThrType       = IR_RX_Count_High_Level;
+ *     IR_InitStruct.IR_RxCntThr           = 0x1F40;
+ *     IR_Init(&IR_InitStruct);
+ *     IR_Cmd(IR_MODE_RX, ENABLE);
+ *     IR_ClearRxFIFO();
+ * }
+ * \endcode
+ */
+void IR_StructInit(IR_InitTypeDef *IR_InitStruct);
+
+/**
+ * \brief   Enable or disable the selected IR mode.
+ *
+ * \param[in] mode      Selected IR operation mode.
+ *                      This parameter can be one of the following values:
+ *                      \arg IR_MODE_TX: Transmission mode.
+ *                      \arg IR_MODE_RX: Receiving mode.
+ * \param[in] NewState  New state of the operation mode.
+ *                      This parameter can be one of the following values:
+ *                      - ENABLE: Enable the selected IR mode.
+ *                      - DISABLE: Disable the selected IR mode.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_ir_init(void)
+ * {
+ *     RCC_PeriphClockCmd(APBPeriph_IR, APBPeriph_IR_CLOCK, ENABLE);
+ *
+ *     IR_InitTypeDef IR_InitStruct;
+ *     IR_StructInit(&IR_InitStruct);
+ *
+ *     IR_InitStruct.IR_Freq               = 38000;
+ *     IR_InitStruct.IR_Mode               = IR_MODE_RX;
+ *     IR_InitStruct.IR_RxStartMode        = IR_RX_AUTO_MODE;
+ *     IR_InitStruct.IR_RxFIFOThrLevel     = IR_RX_FIFO_THR_LEVEL;
+ *     IR_InitStruct.IR_RxFIFOFullCtrl     = IR_RX_FIFO_FULL_DISCARD_NEWEST;
+ *     IR_InitStruct.IR_RxFilterTime       = IR_RX_FILTER_TIME_50ns;
+ *     IR_InitStruct.IR_RxTriggerMode      = IR_RX_FALL_EDGE;
+ *     IR_InitStruct.IR_RxCntThrType       = IR_RX_Count_High_Level;
+ *     IR_InitStruct.IR_RxCntThr           = 0x1F40;
+ *     IR_Init(&IR_InitStruct);
+ *     IR_Cmd(IR_MODE_RX, ENABLE);
+ *     IR_ClearRxFIFO();
+ * }
+ * \endcode
+ */
+void IR_Cmd(uint32_t mode, FunctionalState NewState);
+
+/**
+ * \brief Start trigger receive, only in manual receive mode.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void ir_demo(void)
+ * {
+ *     IR_StartManualRxTrigger();
+ * }
+ * \endcode
+ */
+void IR_StartManualRxTrigger(void);
+
+/**
+ * \brief   Config counter threshold value in receiving mode. You can use it to stop receiving IR data.
+ *
+ * \param[in] IR_RxCntThrType  Count threshold type.
+ *                             This parameter can be the following values:
+ *                             \arg IR_RX_Count_Low_Level: Low level counter value >= IR_RxCntThr, trigger IR_INT_RX_CNT_THR interrupt.
+ *                             \arg IR_RX_Count_High_Level: High level counter value >= IR_RxCntThr, trigger IR_INT_RX_CNT_THR interrupt.
+ * \param[in] IR_RxCntThr      Configure IR Rx counter threshold value which can be 0 to 0x7fffffffUL.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void ir_demo(void)
+ * {
+ *     IR_SetRxCounterThreshold(IR_RX_Count_Low_Level, 0x100);
+ * }
+ * \endcode
+ */
+void IR_SetRxCounterThreshold(uint32_t IR_RxCntThrType, uint32_t IR_RxCntThr);
+
+/**
+ * \brief   Send data.
+ *
+ * \param[in] pBuf          Data buffer to send.
+ * \param[in] len           Send data length.
+ * \param[in] IsLastPacket  Is it the last package of data.
+ *                          This parameter can be one of the following values:
+ *                          - ENABLE: The last data in IR packet and there is no continous data.
+ *                            In other words, an infrared data transmission is completed.
+ *                          - DISABLE: There is data to be transmitted continuously.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void ir_demo(void)
+ * {
+ *     uint32_t data_buf[80] = {0};
+ *     IR_SendBuf(data_buf, 68, DISABLE);
+ * }
+ * \endcode
+ */
+void IR_SendBuf(uint32_t *pBuf, uint32_t len, FunctionalState IsLastPacket);
+
+/**
+ * \brief  Send compensation data.
+ *
+ * \param[in] comp_type     Compensation data type.
+ *                          This parameter can be one of the following values:
+ *                          \arg IR_COMPEN_FLAG_1_2_CARRIER: 1/2 carrier freqency.
+ *                          \arg IR_COMPEN_FLAG_1_4_CARRIER: 1/4 carrier freqency.
+ *                          \arg IR_COMPEN_FLAG_1_N_SYSTEM_CLK: MOD((0x48[27:16]+0x00[11:0]), 4095)/40MHz.
+ *                          User can call function of IR_ConfigCompParam to configure 0x48[27:16].
+ * \param[in] buf           Data buffer to send.
+ * \param[in] length        Data length.
+ * \param[in] IsLastPacket  Is it the last package of data.
+ *                          This parameter can be the following values:
+ *                          - ENABLE: The last data in IR packet and there is no continous data.
+ *                            In other words, an infrared data transmission is completed.
+ *                          - DISABLE: There is data to be transmitted continuously.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void ir_demo(void)
+ * {
+ *     uint32_t data_buf[80] = {0};
+ *     IR_SendCompenBuf(IR_COMPEN_FLAG_1_2_CARRIER, data_buf, 68, DISABLE);
+ * }
+ * \endcode
+ */
+void IR_SendCompenBuf(IRTxCompen_TypeDef comp_type, uint32_t *pBuf, uint32_t len,
+                      FunctionalState IsLastPacket);
+
+/**
+ * \brief   Read data From RX FIO.
+ *
+ * \param[in] pBuf    Buffer address to receive data.
+ * \param[in] length  Read data length.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void ir_demo(void)
+ * {
+ *     uint32_t data_buf[80] = {0};
+ *     IR_ReceiveBuf(data_buf, 68);
+ * }
+ * \endcode
+ */
+void IR_ReceiveBuf(uint32_t *pBuf, uint32_t length);
+
+/**
+ * \brief     Enable or disable the specified IR interrupt source.
+ *
+ * \param[in] IR_INT    Specify the IR interrupt source to be enabled or disabled.
+ *                      This parameter can be oen of the following values, refer to \ref IR_Interrupt.
+ *                      \arg IR_INT_TF_EMPTY: TX FIFO empty interrupt source.
+ *                      \arg IR_INT_TF_LEVEL: TX FIFO threshold interrupt source.
+ *                      \arg IR_INT_TF_OF: TX FIFO overflow interrupt source.
+ *                      \arg IR_INT_RF_FULL: RX FIFO  full interrupt source.
+ *                      \arg IR_INT_RF_LEVEL: RX FIFO threshold interrupt source.
+ *                      \arg IR_INT_RX_CNT_OF: RX counter overflow interrupt source.
+ *                      \arg IR_INT_RF_OF: RX FIFO overflow interrupt source.
+ *                      \arg IR_INT_RX_CNT_THR: RX counter threshold interrupt source.
+ *                      \arg IR_INT_RF_ERROR: RX FIFO error read interrupt source. Trigger when RX FIFO empty and read RX FIFO.
+ *                      \arg IR_INT_RISING_EDGE: IR RX Rising edge interrupt.
+ *                      \arg IR_INT_FALLING_EDGE: IR RX Falling edge interrupt.
+ * \param[in] NewState  New state of the specified IR interrupt.
+ *                      This parameter can be one of the following values:
+ *                      - ENABLE: Enable the specified IR interrupt source.
+ *                      - DISABLE: Disable the specified IR interrupt source.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void ir_demo(void)
+ * {
+ *     IR_INTConfig(IR_INT_TF_EMPTY, ENABLE);
+ * }
+ * \endcode
+ */
+void IR_INTConfig(uint32_t IR_INT, FunctionalState NewState);
+
+/**
+ * \brief     Mask or unmask the specified IR interrupt source.
+ *
+ * \param[in] IR_INT    Specify the IR interrupts sources to be mask or unmask.
+ *                      This parameter can be the following values, refer to \ref IR_Interrupt.
+ *                      \arg IR_INT_TF_EMPTY: TX FIFO empty interrupt.
+ *                      \arg IR_INT_TF_LEVEL: TX FIFO threshold interrupt.
+ *                      \arg IR_INT_TF_OF: TX FIFO overflow interrupt.
+ *                      \arg IR_INT_RF_FULL: RX FIFO  full interrupt.
+ *                      \arg IR_INT_RF_LEVEL: RX FIFO threshold interrupt.
+ *                      \arg IR_INT_RX_CNT_OF: RX counter overflow interrupt.
+ *                      \arg IR_INT_RF_OF: RX FIFO overflow interrupt.
+ *                      \arg IR_INT_RX_CNT_THR: RX counter threshold interrupt.
+ *                      \arg IR_INT_RF_ERROR: RX FIFO error read interrupt. Trigger when RX FIFO empty and read RX FIFO.
+ *                      \arg IR_INT_RISING_EDGE: IR RX Rising edge interrupt.
+ *                      \arg IR_INT_FALLING_EDGE: IR RX Falling edge interrupt.
+ * \param[in] NewState  New state of the specified IR interrupts.
+ *                      This parameter can be one of the following values:
+ *                      - ENABLE: Mask the specified IR interrupt source.
+ *                      - DISABLE: Unmask the specified IR interrupt source.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void ir_demo(void)
+ * {
+ *     IR_MaskINTConfig(IR_INT_TF_EMPTY, ENABLE);
+ * }
+ * \endcode
+ */
+void IR_MaskINTConfig(uint32_t IR_INT, FunctionalState NewState);
+
+/**
+ * \brief     Get the specified IR interrupt status.
+ *
+ * \param[in] IR_INT  The specified IR interrupts.
+ *                    This parameter can be one of the following values, refer to \ref IR_Interrupt.
+ *                    \arg IR_INT_TF_EMPTY: TX FIFO empty interrupt.
+ *                    \arg IR_INT_TF_LEVEL: TX FIFO threshold interrupt.
+ *                    \arg IR_INT_TF_OF: TX FIFO overflow interrupt.
+ *                    \arg IR_INT_RF_FULL: RX FIFO  full interrupt.
+ *                    \arg IR_INT_RF_LEVEL: RX FIFO threshold interrupt.
+ *                    \arg IR_INT_RX_CNT_OF: RX counter overflow interrupt.
+ *                    \arg IR_INT_RF_OF: RX FIFO overflow interrupt.
+ *                    \arg IR_INT_RX_CNT_THR: RX counter threshold interrupt.
+ *                    \arg IR_INT_RF_ERROR: RX FIFO error read interrupt. Trigger when RX FIFO empty and read RX FIFO.
+ *                    \arg IR_INT_RISING_EDGE: IR RX Rising edge interrupt.
+ *                    \arg IR_INT_FALLING_EDGE: IR RX Falling edge interrupt.
+ *
+ * \return  The status of IR interrupt.
+ *          - SET: The IR interrupt status is set.
+ *          - RESET: The IR interrupt status is not set.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void ir_demo(void)
+ * {
+ *     ITStatus int_status = IR_GetINTStatus(IR_INT_TF_EMPTY);
+ * }
+ * \endcode
+ */
+ITStatus IR_GetINTStatus(uint32_t IR_INT);
+
+/**
+ * \brief     Clear the IR interrupt pending bit.
+ *
+ * \param[in] IR_CLEAR_INT  Specify the interrupt pending bit to clear.
+ *                          This parameter can be any combination of the following values, refer to \ref IR_Interrupts_Clear_Flag.
+ *                          - IR_INT_TF_EMPTY_CLR: Clear TX FIFO empty interrupt.
+ *                          - IR_INT_TF_LEVEL_CLR: Clear TX FIFO threshold interrupt.
+ *                          - IR_INT_TF_OF_CLR: Clear TX FIFO overflow interrupt.
+ *                          - IR_INT_RF_FULL_CLR: Clear RX FIFO  full interrupt.
+ *                          - IR_INT_RF_LEVEL_CLR: Clear RX FIFO threshold interrupt.
+ *                          - IR_INT_RX_CNT_OF_CLR: Clear RX counter overflow interrupt.
+ *                          - IR_INT_RF_OF_CLR: Clear RX FIFO overflow interrupt.
+ *                          - IR_INT_RX_CNT_THR_CLR: Clear RX counter threshold interrupt.
+ *                          - IR_INT_RF_ERROR_CLR: Clear RX FIFO error read interrupt. Trigger when RX FIFO empty and read RX FIFO.
+ *                          - IR_INT_RX_RISING_EDGE_CLR: Clear RX Rising edge interrupt.
+ *                          - IR_INT_RX_FALLING_EDGE_CLR: Clear RX Falling edge interrupt.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void ir_demo(void)
+ * {
+ *     IR_ClearINTPendingBit(IR_INT_RX_CNT_OF_CLR);
+ * }
+ * \endcode
+ */
+void IR_ClearINTPendingBit(uint32_t IR_CLEAR_INT);
+
+/**
+ * \brief Get free size of TX FIFO.
+ *
+ * \return The free size of TX FIFO.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void ir_demo(void)
+ * {
+ *     uint16_t data_len = IR_GetTxFIFOFreeLen();
+ * }
+ * \endcode
+ */
+uint16_t IR_GetTxFIFOFreeLen(void);
+
+/**
+ * \brief Get data size in RX FIFO.
+ *
+ * \return Current data size in RX FIFO.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void ir_demo(void)
+ * {
+ *     uint16_t data_len = IR_GetRxDataLen();
+ * }
+ * \endcode
+ */
+uint16_t IR_GetRxDataLen(void);
+
+/**
+ * \brief   Send one data.
+ *
+ * \param[in] data  Send data.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void ir_demo(void)
+ * {
+ *     IR_SendData(0x80000100);
+ * }
+ * \endcode
+ */
+void IR_SendData(uint32_t data);
+
+/**
+ * \brief Read one data.
+ *
+ * \return Data which read from RX FIFO.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void ir_demo(void)
+ * {
+ *     uint32_t data = IR_ReceiveData();
+ * }
+ * \endcode
+ */
+uint32_t IR_ReceiveData(void);
+
+/**
+ * \brief  Set tx threshold, when TX FIFO depth <= threshold value trigger interrupt.
+ *
+ * \param[in] thd  Tx threshold.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void ir_demo(void)
+ * {
+ *     IR_SetTxThreshold(30);
+ * }
+ * \endcode
+ */
+void IR_SetTxThreshold(uint8_t thd);
+
+/**
+ * \brief   Set tx threshold, when RX FIFO depth >= threshold value trigger interrupt.
+ *
+ * \param[in] thd  Rx threshold.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void ir_demo(void)
+ * {
+ *     IR_SetRxThreshold(2);
+ * }
+ * \endcode
+ */
+void IR_SetRxThreshold(uint8_t thd);
+
+/**
+ * \brief Get IR RX current count.
+ *
+ * \return Current counter.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void ir_demo(void)
+ * {
+ *     uint32_t count = IR_GetRxCurrentCount();
+ * }
+ * \endcode
+ */
+uint32_t IR_GetRxCurrentCount(void);
+
+/**
+ * \brief Clear IR TX FIFO.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void ir_demo(void)
+ * {
+ *     IR_ClearTxFIFO();
+ * }
+ * \endcode
+ */
+void IR_ClearTxFIFO(void);
+
+/**
+ * \brief Clear IR RX FIFO.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void ir_demo(void)
+ * {
+ *     IR_ClearRxFIFO();
+ * }
+ * \endcode
+ */
+void IR_ClearRxFIFO(void);
+
+/**
+ * \brief  Get the specified IR flag status.
+ *
+ * \param[in] IR_FLAG  Specify the flag to check.
+ *                     This parameter can be one of the following values, refer to \ref IR_Flag.
+ *                     \arg IR_FLAG_TF_EMPTY: TX FIFO empty or not. If SET, TX FIFO is empty.
+ *                     \arg IR_FLAG_TF_FULL: TX FIFO full or not. If SET, TX FIFO is full.
+ *                     \arg IR_FLAG_TX_RUN: TX run or not. If SET, TX is running.
+ *                     \arg IR_FLAG_RF_EMPTY: RX FIFO empty or not. If SET, RX FIFO is empty.
+ *                     \arg IR_FLAG_RF_FULL: RX FIFO full or not. If SET, RX FIFO is full.
+ *                     \arg IR_FLAG_RX_RUN: RX run or not. If SET, RX is running.
+ *
+ * \return  The status of IR flag.
+ *          - SET: The IR flag is set.
+ *          - RESET: The IR flag is reset.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void ir_demo(void)
+ * {
+ *     FlagStatus flag_status = IR_GetFlagStatus(IR_FLAG_TF_EMPTY);
+ * }
+ * \endcode
+ */
+FlagStatus IR_GetFlagStatus(uint32_t IR_FLAG);
+
+/**
+ * \brief   Set or reset tx data inverse.
+ *
+ * \param[in] NewState  This parameter can be: ENABLE or DISABLE.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void ir_demo(void)
+ * {
+ *     IR_SetTxInverse(ENABLE);
+ * }
+ * \endcode
+ */
+void IR_SetTxInverse(FunctionalState NewState);
+
+/**
+ * \brief  Enbale TX output inverse or not.
+ *
+ * \param[in] NewState  This parameter can be: ENABLE or DISABLE.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void ir_demo(void)
+ * {
+ *     IR_TxOutputInverse(ENABLE);
+ * }
+ * \endcode
+ */
+void IR_TxOutputInverse(FunctionalState NewState);
+
+/**
+ * \brief Get IR RX Level.
+ *
+ * \return Current Level.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void ir_demo(void)
+ * {
+ *     uint32_t level = IR_GetRxCurrentLevel();
+ * }
+ * \endcode
+ */
+uint32_t IR_GetRxCurrentLevel(void);
+
+/**
+ * \brief  IR clock config.
+ *
+ * \param[in]  ClockSrc  Specify the clock source to gates its clock.
+ * \param[in]  ClockDiv  Specify the clock divide to gates its clock.
+ */
+void IR_ClkConfig(IRClockSrc_TypeDef ClockSrc, IRClockDiv_TypeDef ClockDiv);
+
+/**
+ * \brief  Get IR clock config.
+ *
+ * \param[in]  ClockSrc  Specify the clock source to gates its clock.
+ * \param[in]  ClockDiv  Specify the clock divide to gates its clock.
+ *
+ * \return The status of get clock.
+ */
+bool IR_ClkGet(IRClockSrc_TypeDef *ClockSrc, IRClockDiv_TypeDef *ClockDiv);
+
+#if (IR_SUPPORT_RAP_FUNCTION == 1)
+void IR_RAPModeCmd(FunctionalState NewState);
+
+void IR_RAPQactiveCtrl(uint32_t Qactive, FunctionalState NewState);
+
+void IR_TaskTrigger(uint32_t Task);
+#endif
+
+/** End of IR_Exported_Functions
+  * \}
+  */
+
+/** End of IR
+  * \}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RTL_IR_H */
+
+
+
diff --git a/bee/drivers/ir/src/device/rtl87x2g/rtl_ir_def.h b/bee/drivers/ir/src/device/rtl87x2g/rtl_ir_def.h
new file mode 100644
index 00000000..382258ec
--- /dev/null
+++ b/bee/drivers/ir/src/device/rtl87x2g/rtl_ir_def.h
@@ -0,0 +1,648 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef RTL_IR_DEF_H
+#define RTL_IR_DEF_H
+
+#include "utils/rtl_utils.h"
+#include "address_map.h"
+
+#ifdef  __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/*============================================================================*
+ *                         IR Defines
+ *============================================================================*/
+/** \defgroup IR          IR
+  * \brief
+  * \{
+  */
+
+/** \defgroup IR_Exported_Constants IR Exported Constants
+  * \brief
+  * \{
+  */
+
+/**
+ * \defgroup IR_Defines IR Defines
+ * \{
+ * \ingroup  IR_Exported_Constants
+ */
+#define IR_SUPPORT_TX_FINISH_INTERRUPT                 (0)          //!< The function is not supported.
+#define IR_SUPPORT_CLOCK_SOURCE_80M                    (0)          //!< The function is not supported.
+#define IR_SUPPORT_CLOCK_SOURCE_90M                    (1)          //!< IR support clock 90M
+#define IR_SUPPORT_CLOCK_SOURCE_100M                   (1)          //!< IR support clock 100M
+#define IR_SUPPORT_RAP_FUNCTION                        (0)          //!< The function is not supported.
+
+
+/** End of IR_Defines
+  * \}
+  */
+
+/** End of IR_Exported_Constants
+  * \}
+  */
+
+/** End of IR
+  * \}
+  */
+
+/*============================================================================*
+ *                         IR Private Defines
+ *============================================================================*/
+#define IR_RX_EXTENSION_INT                         0x8000
+#define IR_RX_MSK_TO_EN_Pos                         14
+#define IR_TX_FIFO_OVER_MSK_TO_EN_Pos               1
+#define IR_TX_MSK_TO_EN_Pos                         2
+#define IR_TX_STATUS_TO_EN_Pos                      2
+
+#define IR_DATA_TYPE_Msk                          BIT31
+#define IR_TX_LAST_PACKEET_Msk                    BIT30
+
+/*============================================================================*
+ *                         IR Registers Memory Map
+ *============================================================================*/
+typedef struct
+{
+    __IO uint32_t  IR_CLK_DIV;          /*!< 0x00 */
+    __IO uint32_t  IR_TX_CONFIG;        /*!< 0x04 */
+    __IO uint32_t  IR_TX_SR;            /*!< 0x08 */
+    __IO uint32_t  RSVD_0C;             /*!< 0x0C */
+    __IO uint32_t  IR_TX_INT_CLR;       /*!< 0x10 */
+    __IO uint32_t  IR_TX_FIFO;          /*!< 0x14 */
+    __IO uint32_t  IR_RX_CONFIG;        /*!< 0x18 */
+    __IO uint32_t  IR_RX_SR;            /*!< 0x1C */
+    __IO uint32_t  IR_RX_INT_CLR;       /*!< 0x20 */
+    __IO uint32_t  IR_RX_CNT_INT_SEL;   /*!< 0x24 */
+    __I  uint32_t  IR_RX_FIFO;          /*!< 0x28 */
+    __I  uint32_t  IR_VERSION;          /*!< 0x2C */
+    __I  uint32_t  IR_RX_CUR_CNT;       /*!< 0x30 */
+    __IO uint32_t  IR_RX_EX_INT;        /*!< 0x34 */
+    __IO uint32_t  RSVD_38[4];          /*!< 0x38 */
+    __IO uint32_t  IR_TX_COMPE;         /*!< 0x48 */
+    __I  uint32_t  IR_RX_LEVEL;         /*!< 0x4C */
+    __IO uint32_t  IR_DMA_CONFIG;       /*!< 0x50 */
+} IR_TypeDef;
+
+/*============================================================================*
+ *                         IR Declaration
+ *============================================================================*/
+#define IR                      ((IR_TypeDef *) IR_RC_REG_BASE)
+
+#define IS_IR_PERIPH(PERIPH)    ((PERIPH) == IR)
+
+/*============================================================================*
+ *                         IR Private Types
+ *============================================================================*/
+typedef struct
+{
+    uint32_t ir_reg[6];
+} IRStoreReg_Typedef;
+
+/*============================================================================*
+ *                         IR Registers and Field Descriptions
+ *============================================================================*/
+/* 0x00
+    13:0    R/W    ir_clk_div                      14'h0
+    31:14   R      reserved31_13                   18'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t ir_clk_div: 14;
+        const uint32_t reserved_0: 18;
+    } b;
+} IR_CLK_DIV_TypeDef;
+
+
+
+/* 0x04
+    0       R/W    ir_tx_fifo_empty_int_en         1'h0
+    1       R/W    ir_tx_fifo_level_int_en         1'h0
+    2       R/W    ir_tx_fifo_empty_int_mask       1'h0
+    3       R/W    ir_tx_fifo_level_int_mask       1'h0
+    4       R/W    ir_tx_fifo_over_int_en          1'h0
+    5       R/W    ir_tx_fifo_over_int_mask        1'h0
+    6       R/W    ir_tx_idel_state                1'h0
+    7       R      reserved7                       1'h0
+    12:8    R/W    ir_tx_fifo_level_th             5'h0
+    13      R/W    ir_tx_de_inverse                1'h0
+    14      R/W    ir_tx_output_inverse            1'h0
+    15      R      reserved15                      1'h0
+    29:16   R/W    ir_tx_duty_num                  14'h0
+    30      R/W    ir_tx_start                     1'h0
+    31      R/W    ir_mode_sel                     1'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t ir_tx_fifo_empty_int_en: 1;
+        uint32_t ir_tx_fifo_level_int_en: 1;
+        uint32_t ir_tx_fifo_empty_int_mask: 1;
+        uint32_t ir_tx_fifo_level_int_mask: 1;
+        uint32_t ir_tx_fifo_over_int_en: 1;
+        uint32_t ir_tx_fifo_over_int_mask: 1;
+        uint32_t ir_tx_idel_state: 1;
+        const uint32_t reserved_1: 1;
+        uint32_t ir_tx_fifo_level_th: 5;
+        uint32_t ir_tx_de_inverse: 1;
+        uint32_t ir_tx_output_inverse: 1;
+        const uint32_t reserved_0: 1;
+        uint32_t ir_tx_duty_num: 14;
+        uint32_t ir_tx_start: 1;
+        uint32_t ir_mode_sel: 1;
+    } b;
+} IR_TX_CONFIG_TypeDef;
+
+
+
+/* 0x08
+    0       R      ir_tx_fifo_empty_int_status     1'h0
+    1       R      ir_tx_fifo_level_int_status     1'h0
+    2       R      ir_tx_fifo_over_int_status      1'h0
+    3       R      ir_tx_finish_int_status         1'h0
+    4       R      ir_tx_status                    1'h0
+    5       R/W    ir_tx_finish_int_en             1'h0
+    6       R/W    ir_tx_finish_int_mask           1'h0
+    7       R      reserved7                       1'h0
+    13:8    R      ir_tx_fifo_offset               7'h0
+    14      R      ir_tx_fifo_full                 1'h0
+    15      R      ir_tx_fifo_empty                1'h0
+    31:16   R      reserved31_16                   16'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        const uint32_t ir_tx_fifo_empty_int_status: 1;
+        const uint32_t ir_tx_fifo_level_int_status: 1;
+        const uint32_t ir_tx_fifo_over_int_status: 1;
+        const uint32_t ir_tx_finish_int_status: 1;
+        const uint32_t ir_tx_status: 1;
+        uint32_t ir_tx_finish_int_en: 1;
+        uint32_t ir_tx_finish_int_mask: 1;
+        const uint32_t reserved_1: 1;
+        const uint32_t ir_tx_fifo_offset: 6;
+        const uint32_t ir_tx_fifo_full: 1;
+        const uint32_t ir_tx_fifo_empty: 1;
+        const uint32_t reserved_0: 16;
+    } b;
+} IR_TX_SR_TypeDef;
+
+
+
+/* 0x10
+    0       W1C    ir_tx_fifo_clr                  1'h0
+    1       W1C    ir_tx_fifo_empty_int_clr        1'h0
+    2       W1C    ir_tx_fifo_level_int_clr        1'h0
+    3       W1C    ir_tx_fifo_over_int_clr         1'h0
+    4       W1C    ir_tx_finish_int_clr            1'h0
+    31:5    R      reserved31_5                    27'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t ir_tx_fifo_clr: 1;
+        uint32_t ir_tx_fifo_empty_int_clr: 1;
+        uint32_t ir_tx_fifo_level_int_clr: 1;
+        uint32_t ir_tx_fifo_over_int_clr: 1;
+        uint32_t ir_tx_finish_int_clr: 1;
+        const uint32_t reserved_0: 27;
+    } b;
+} IR_TX_INT_CLR_TypeDef;
+
+
+
+/* 0x14
+    31:0    W      ir_tx_fifo                      32'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t ir_tx_fifo: 32;
+    } b;
+} IR_TX_FIFO_TypeDef;
+
+
+
+/* 0x18
+    0       R/W    ir_rx_fifo_full_int_en          1'h0
+    1       R/W    ir_rx_fifo_levle_int_en         1'h0
+    2       R/W    ir_rx_cnt_of_int_en             1'h0
+    3       R/W    ir_rx_fifo_of_int_en            1'h0
+    4       R/W    ir_rx_cnt_thr_int_en            1'h0
+    5       R/W    ir_rx_fifo_error_int_en         1'h0
+    7:6     R      reserved7_6                     2'h0
+    12:8    R/W    ir_rx_fifo_level_th             5'h0
+    13      R/W    ir_rx_fifo_discard_set          1'h0
+    14      R/W    ir_rx_fifo_full_int_mask        1'h0
+    15      R/W    ir_rx_fifo_level_int_mask       1'h0
+    16      R/W    ir_rx_cnt_of_int_mask           1'h0
+    17      R/W    ir_rx_fifo_of_int_mask          1'h0
+    18      R/W    ir_rx_cnt_thr_int_mask          1'h0
+    19      R/W    ir_rx_fifo_error_int_mask       1'h0
+    20      R      reserved20                      1'h0
+    23:21   R/W    ir_rx_filter_stage              3'h0
+    25:24   R/W    ir_rx_trigger_mode              2'h0
+    26      R/W    ir_rx_man_start                 1'h0
+    27      R/W    ir_rx_start_mode                1'h0
+    28      R/W    ir_rx_start                     1'h0
+    31:29   R      reserved31_29                   3'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t ir_rx_fifo_full_int_en: 1;
+        uint32_t ir_rx_fifo_levle_int_en: 1;
+        uint32_t ir_rx_cnt_of_int_en: 1;
+        uint32_t ir_rx_fifo_of_int_en: 1;
+        uint32_t ir_rx_cnt_thr_int_en: 1;
+        uint32_t ir_rx_fifo_error_int_en: 1;
+        const uint32_t reserved_2: 2;
+        uint32_t ir_rx_fifo_level_th: 5;
+        uint32_t ir_rx_fifo_discard_set: 1;
+        uint32_t ir_rx_fifo_full_int_mask: 1;
+        uint32_t ir_rx_fifo_level_int_mask: 1;
+        uint32_t ir_rx_cnt_of_int_mask: 1;
+        uint32_t ir_rx_fifo_of_int_mask: 1;
+        uint32_t ir_rx_cnt_thr_int_mask: 1;
+        uint32_t ir_rx_fifo_error_int_mask: 1;
+        const uint32_t reserved_1: 1;
+        uint32_t ir_rx_filter_stage: 3;
+        uint32_t ir_rx_trigger_mode: 2;
+        uint32_t ir_rx_man_start: 1;
+        uint32_t ir_rx_start_mode: 1;
+        uint32_t ir_rx_start: 1;
+        const uint32_t reserved_0: 3;
+    } b;
+} IR_RX_CONFIG_TypeDef;
+
+
+
+/* 0x1C
+    0       R      ir_rx_fifo_full_int_status      1'h0
+    1       R      ir_rx_fifo_level_int_status     1'h0
+    2       R      ir_rx_cnt_of_int_status         1'h0
+    3       R      ir_rx_fifo_of_int_status        1'h0
+    4       R      ir_rx_cnt_thr_int_status        1'h0
+    5       R      ir_rx_fifo_error_int_status     1'h0
+    6       R      reserved6                       1'h0
+    7       R      ir_rx_state                     1'h0
+    13:8    R      ir_rx_fifo_offset               6'h0
+    15:14   R      reserved15_14                   2'h0
+    16      R/W    ir_rx_fifo_full                 1'h0
+    17      R      ir_rx_fifo_empty                1'h0
+    31:18   R      reserved31_18                   14'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        const uint32_t ir_rx_fifo_full_int_status: 1;
+        const uint32_t ir_rx_fifo_level_int_status: 1;
+        const uint32_t ir_rx_cnt_of_int_status: 1;
+        const uint32_t ir_rx_fifo_of_int_status: 1;
+        const uint32_t ir_rx_cnt_thr_int_status: 1;
+        const uint32_t ir_rx_fifo_error_int_status: 1;
+        const uint32_t reserved_2: 1;
+        const uint32_t ir_rx_state: 1;
+        const uint32_t ir_rx_fifo_offset: 6;
+        const uint32_t reserved_1: 2;
+        uint32_t ir_rx_fifo_full: 1;
+        const uint32_t ir_rx_fifo_empty: 1;
+        const uint32_t reserved_0: 14;
+    } b;
+} IR_RX_SR_TypeDef;
+
+
+
+/* 0x20
+    0       W1C    ir_rx_fifo_full_int_clr         1'h0
+    1       W1C    ir_rx_fifo_level_int_clr        1'h0
+    2       W1C    ir_rx_cnt_of_int_clr            1'h0
+    3       W1C    ir_rx_fifo_of_int_clr           1'h0
+    4       W1C    ir_rx_cnt_thr_int_clr           1'h0
+    5       W1C    ir_rx_fifo_error_int_clr        1'h0
+    6       W1C    ir_rx_falling_edge_int_clr      1'h0
+    7       W1C    ir_rx_rising_edge_int_clr       1'h0
+    8       W1C    ir_rx_fifo_clr                  1'h0
+    31:9    R      reserved31_9                    23'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t ir_rx_fifo_full_int_clr: 1;
+        uint32_t ir_rx_fifo_level_int_clr: 1;
+        uint32_t ir_rx_cnt_of_int_clr: 1;
+        uint32_t ir_rx_fifo_of_int_clr: 1;
+        uint32_t ir_rx_cnt_thr_int_clr: 1;
+        uint32_t ir_rx_fifo_error_int_clr: 1;
+        uint32_t ir_rx_falling_edge_int_clr: 1;
+        uint32_t ir_rx_rising_edge_int_clr: 1;
+        uint32_t ir_rx_fifo_clr: 1;
+        const uint32_t reserved_0: 23;
+    } b;
+} IR_RX_INT_CLR_TypeDef;
+
+
+
+/* 0x24
+    30:0    R/W    ir_rx_cnt_thr                   31'h0
+    31      R/W    ir_rx_cnt_thr_trigger_lv        1'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t ir_rx_cnt_thr: 31;
+        uint32_t ir_rx_cnt_thr_trigger_lv: 1;
+    } b;
+} IR_RX_CNT_INT_SEL_TypeDef;
+
+
+
+/* 0x28
+    31:0    R      ir_rx_fifo                      32'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        const uint32_t ir_rx_fifo: 32;
+    } b;
+} IR_RX_FIFO_TypeDef;
+
+
+
+/* 0x2C
+    31:0    R      rtl_version                     32'h20221214
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        const uint32_t rtl_version: 32;
+    } b;
+} IR_VERSION_TypeDef;
+
+
+
+/* 0x30
+    30:0    R      ir_rx_cur_cnt                   31'h0
+    31      R      ir_rx_cur_lv                    1'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        const uint32_t ir_rx_cur_cnt: 31;
+        const uint32_t ir_rx_cur_lv: 1;
+    } b;
+} IR_RX_CUR_CNT_TypeDef;
+
+
+
+/* 0x34
+    0       R/W    ir_rx_falling_edge_int_en       1'h0
+    1       R/W    ir_rx_rising_edge_int_en        1'h0
+    2       R/W    ir_rx_falling_edge_int_mask     1'h0
+    3       R/W    ir_rx_rising_edge_int_mask      1'h0
+    4       R/W    ir_rx_falling_edge_int_status   1'h0
+    5       R      ir_rx_rising_edge_int_status    1'h0
+    31:6    R      reserved31_6                    26'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t ir_rx_falling_edge_int_en: 1;
+        uint32_t ir_rx_rising_edge_int_en: 1;
+        uint32_t ir_rx_falling_edge_int_mask: 1;
+        uint32_t ir_rx_rising_edge_int_mask: 1;
+        uint32_t ir_rx_falling_edge_int_status: 1;
+        const uint32_t ir_rx_rising_edge_int_status: 1;
+        const uint32_t reserved_0: 26;
+    } b;
+} IR_RX_EX_INT_TypeDef;
+
+
+
+/* 0x48
+    15:0    R      reserved15_0                    16'h0
+    28:16   R/W    ir_tx_compesation               13'h0
+    31:29   R      reserved31_29                   3'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        const uint32_t reserved_1: 16;
+        uint32_t ir_tx_compesation: 13;
+        const uint32_t reserved_0: 3;
+    } b;
+} IR_TX_COMPE_TypeDef;
+
+
+
+/* 0x4C
+    0       R      ir_rx_level                     1'h0
+    31:1    R      reserved31_1                    31'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        const uint32_t ir_rx_level: 1;
+        const uint32_t reserved_0: 31;
+    } b;
+} IR_RX_LEVEL_TypeDef;
+
+
+
+/* 0x50
+    0       R/W    reg_dma_tx_en                   1'h0
+    6:1     R/W    reg_dma_tx_fifo_th              6'h0
+    7       R      reserved7                       1'h0
+    8       R/W    reg_dma_rx_en                   1'h0
+    14:9    R/W    reg_dma_rx_fifo_th              6'h0
+    31:15   R      reserved31_15                   17'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t reg_dma_tx_en: 1;
+        uint32_t reg_dma_tx_fifo_th: 6;
+        const uint32_t reserved_1: 1;
+        uint32_t reg_dma_rx_en: 1;
+        uint32_t reg_dma_rx_fifo_th: 6;
+        const uint32_t reserved_0: 17;
+    } b;
+} IR_DMA_CONFIG_TypeDef;
+
+/*============================================================================*
+ *                        IR Constants
+ *============================================================================*/
+/** \defgroup IR          IR
+  * \brief
+  * \{
+  */
+
+/** \defgroup IR_Exported_Constants IR Exported Constants
+  * \brief
+  * \{
+  */
+
+/**
+ * \defgroup    IR_Source_Clock IR Source Clock
+ * \{
+ * \ingroup     IR_Exported_Constants
+ */
+typedef enum
+{
+    IR_CLOCK_SRC_40M,     //!< The IR clock source is 40MHz.
+    IR_CLOCK_SRC_PLL1,    //!< The IR clock source is PLL1.
+    IR_CLOCK_SRC_PLL2,    //!< The IR clock source is PLL2.
+} IRClockSrc_TypeDef;
+
+#define IS_IR_SRC_CLOCK(CLK) (((CLK) == IR_CLOCK_SRC_40M) \
+                              || ((CLK) == IR_CLOCK_SRC_PLL1) \
+                              || ((CLK) == IR_CLOCK_SRC_PLL2)) //!< Check if the input parameter is valid.
+
+/** End of IR_Source_Clock
+  * \}
+  */
+
+/**
+ * \defgroup    IR_Clock_Divider IR Clock Divider
+ * \{
+ * \ingroup     IR_Exported_Constants
+ */
+typedef enum
+{
+    IR_CLOCK_DIVIDER_1 = 0x0,     //!< The clock divider is 1.
+    IR_CLOCK_DIVIDER_2 = 0x1,     //!< The clock divider is 2.
+} IRClockDiv_TypeDef;
+
+#define IS_IR_CLK_DIV(DIV) (((DIV) == IR_CLOCK_DIVIDER_1) || \
+                            ((DIV) == IR_CLOCK_DIVIDER_2)) //!< Check if the input parameter is valid.
+
+/** End of IR_Clock_Divider
+  * \}
+  */
+
+/**
+ * \defgroup    IR_Clock IR Clock
+ * \{
+ * \ingroup     IR_Exported_Constants
+ */
+typedef enum
+{
+    IR_CLOCK_40M = 40000000,     //!< The IR clock is 40MHz.
+    IR_CLOCK_90M = 90000000,     //!< The IR clock is 90MHz.
+    IR_CLOCK_100M = 100000000,   //!< The IR clock is 100MHz.
+} IRClock_TypeDef;
+
+#define IS_IR_CLOCK(CLK) (((CLK) == IR_CLOCK_40M)\
+                          || ((CLK) == IR_CLOCK_90M)\
+                          || ((CLK) == IR_CLOCK_100M)) //!< Check if the input parameter is valid.
+
+#define IS_IR_FREQUENCY_40M(F) (((F) >= 2442) && ((F) <= 2000000)) //!< Check if the input parameter is valid.
+#define IS_IR_FREQUENCY_90M(F) (((F) >= 5494) && ((F) <= 2000000)) //!< Check if the input parameter is valid.
+#define IS_IR_FREQUENCY_100M(F) (((F) >= 6104) && ((F) <= 2000000)) //!< Check if the input parameter is valid.
+
+/** End of IR_Clock
+  * \}
+  */
+
+/** End of IR_Exported_Constants
+  * \}
+  */
+
+/** End of IR
+  * \}
+  */
+
+/*============================================================================*
+ *                          IR TYPE/API Wrappers
+ *============================================================================*/
+/** \defgroup IR         IR
+  * \brief
+  * \{
+  */
+
+/** \defgroup IR_Exported_Constants IR Exported Constants
+  * \brief
+  * \{
+  */
+
+/**
+ * \brief       To be compatible with the previous clock src.
+ * \defgroup    IR_Constants_Wrapper IR Constants Wrapper
+ * \{
+ * \ingroup     IR_Exported_Constants
+ */
+#define IR_SRC_CLOCK_40M            IR_CLOCK_SRC_40M  //!< The macro is a wrapper for IR_CLOCK_SRC_40M
+#define IR_SRC_CLOCK_PLL1           IR_CLOCK_SRC_PLL1 //!< The macro is a wrapper for IR_CLOCK_SRC_PLL1
+#define IR_SRC_CLOCK_PLL2           IR_CLOCK_SRC_PLL2 //!< The macro is a wrapper for IR_CLOCK_SRC_PLL2
+
+/** End of IR_Constants_Wrapper
+  * \}
+  */
+
+/** End of IR_Exported_Constants
+  * \}
+  */
+
+/** End of IR
+  * \}
+  */
+
+
+#ifdef  __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* RTL_IR_DEF_H */
diff --git a/bee/drivers/ir/src/device/rtl87x2j/rtl87x2j_ir.c b/bee/drivers/ir/src/device/rtl87x2j/rtl87x2j_ir.c
new file mode 100644
index 00000000..7e1fdf30
--- /dev/null
+++ b/bee/drivers/ir/src/device/rtl87x2j/rtl87x2j_ir.c
@@ -0,0 +1,109 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *                           Header Files
+ *============================================================================*/
+#include "rtl_ir.h"
+#include "rtl_rcc.h"
+
+/*============================================================================*
+ *                           Private Defines
+ *============================================================================*/
+#define IR_CLOCK_AUTO_MODE_CONFIG_AUTOMATIC       (0x00)
+#define IR_CLOCK_AUTO_MODE_CONFIG_ALWAYSRUN       (0x7E)//Force off 0x54
+
+/*============================================================================*
+ *                           Public Functions
+ *============================================================================*/
+/**
+  * \brief  IR clock config.
+  * \param  ClockSrc: specifies the clock source to gates its clock.\ref IR_Source_Clock
+  * \param  ClockDiv: specifies the clock divide to gates its clock.
+  * \return None
+  */
+void IR_SetClock(IRClockSrc_TypeDef ClockSrc, IRClockDiv_TypeDef ClockDiv)
+{
+    PCC_REG_UPDATE(PCC_REG_IR,
+                   3 << PCC_REG_IR_R_SCLK_IRRC_SRC_SEL_0_Pos,
+                   ClockSrc << PCC_REG_IR_R_SCLK_IRRC_SRC_SEL_0_Pos);
+    return;
+}
+
+void IR_ClockAutoModeCmd(FunctionalState Newstate)
+{
+    /* Check the parameters */
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (Newstate == ENABLE)
+    {
+        // ir qactive auto gating
+        PCC_REG_WRITE_BITFIELD(PCC_REG_PERION_CLK_REG4X, FORCE_QACTIVE_IRRC, 0);
+    }
+    else
+    {
+        // ir qactive force on
+        PCC_REG_WRITE_BITFIELD(PCC_REG_PERION_CLK_REG4X, FORCE_QACTIVE_IRRC, 1);
+        // polling ir clk en ready
+        while (!PCC_REG_READ_BITFIELD(PCC_REG_PERION_CLK_REG0X, CLKEN_O_IRRC));
+    }
+
+    return;
+}
+
+/**
+  * \brief  Store IR register values when system enter DLPS.
+  * \param  PeriReg: Specifies to select the IR peripheral.
+  * \param  StoreBuf: Store buffer to store IR register data.
+  * \return None.
+  */
+void IR_DLPSEnter(void *PeriReg, void *StoreBuf)
+{
+//    IRStoreReg_Typedef *store_buf = (IRStoreReg_Typedef *)StoreBuf;
+
+//    RCC_PeriphClockCmd(APBPeriph_IR, APBPeriph_IR_CLOCK, ENABLE);
+
+//    store_buf->ir_reg[0] = IR->IR_CLK_DIV;
+//    store_buf->ir_reg[1] = IR->IR_TX_CONFIG;
+//    store_buf->ir_reg[2] = IR->IR_RX_CONFIG;
+//    store_buf->ir_reg[3] = IR->IR_RX_CNT_INT_SEL;
+
+    return;
+}
+
+/**
+  * \brief  Restore IR register values when system enter DLPS.
+  * \param  PeriReg: Specifies to select the IR peripheral.
+  * \param  StoreBuf: Restore buffer to restore IR register data.
+  * \return None
+  */
+void IR_DLPSExit(void *PeriReg, void *StoreBuf)
+{
+//    IRStoreReg_Typedef *store_buf = (IRStoreReg_Typedef *)StoreBuf;
+
+//    RCC_PeriphClockCmd(APBPeriph_IR, APBPeriph_IR_CLOCK, ENABLE);
+
+//    IR->IR_CLK_DIV = store_buf->ir_reg[0];
+//    if (store_buf->ir_reg[1] & BIT31)
+//    {
+//        /* RX MODE */
+//        IR->IR_TX_CONFIG  = store_buf->ir_reg[1];
+//        IR->IR_RX_CONFIG  = store_buf->ir_reg[2];
+//        IR->IR_RX_CNT_INT_SEL  = store_buf->ir_reg[3];
+//    }
+//    else
+//    {
+//        /* TX MODE */
+//        IR->IR_TX_CONFIG  = store_buf->ir_reg[1];
+//        /* If IR TX mode is idle, must write one data firstly */
+//        IR->IR_TX_FIFO = 0;
+//    }
+
+    return;
+}
+
+
+
diff --git a/bee/drivers/ir/src/device/rtl87x2j/rtl_ir_def.h b/bee/drivers/ir/src/device/rtl87x2j/rtl_ir_def.h
new file mode 100644
index 00000000..a6bffd7f
--- /dev/null
+++ b/bee/drivers/ir/src/device/rtl87x2j/rtl_ir_def.h
@@ -0,0 +1,672 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef RTL_IR_DEF_H
+#define RTL_IR_DEF_H
+
+#include "utils/rtl_utils.h"
+#include "address_map.h"
+
+#ifdef  __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/*============================================================================*
+ *                         IR Defines
+ *============================================================================*/
+/** \defgroup IR          IR
+  * \brief
+  * \{
+  */
+
+/** \defgroup IR_Exported_Constants IR Exported Constants
+  * \brief
+  * \{
+  */
+
+/**
+ * \defgroup IR_Defines IR Defines
+ * \{
+ * \ingroup  IR_Exported_Constants
+ */
+#define IR_SUPPORT_TX_FINISH_INTERRUPT                 (1)
+#define IR_SUPPORT_CLOCK_SOURCE_80M                    (1)
+#define IR_SUPPORT_CLOCK_SOURCE_90M                    (0)
+#define IR_SUPPORT_CLOCK_SOURCE_100M                   (0)
+#define IR_SUPPORT_TX_MODE_CONFIG                      (1)
+#define IR_SUPPORT_RAP_FUNCTION                        (1)
+#define IR_SUPPORT_CLOCK_SOURCE_DIV_CONFIG             (1)
+#define IR_SUPPORT_AUTO_CLOCK                          (1)
+
+/** End of IR_Defines
+  * \}
+  */
+
+/** End of IR_Exported_Constants
+  * \}
+  */
+
+/** End of IR
+  * \}
+  */
+
+/*============================================================================*
+ *                          IR Registers Memory Map
+ *============================================================================*/
+typedef struct
+{
+    __IO uint32_t IR_CLK_DIV;                   /*!< 0x00 */
+    __IO uint32_t IR_TX_CONFIG;                 /*!< 0x04 */
+    __IO uint32_t IR_TX_SR;                     /*!< 0x08 */
+    __IO uint32_t RSVD_0C;                      /*!< 0x0C */
+    __IO uint32_t IR_TX_INT_CLR;                /*!< 0x10 */
+    __IO uint32_t IR_TX_FIFO;                   /*!< 0x14 */
+    __IO uint32_t IR_RX_CONFIG;                 /*!< 0x18 */
+    __I  uint32_t IR_RX_SR;                     /*!< 0x1C */
+    __IO uint32_t IR_RX_INT_CLR;                /*!< 0x20 */
+    __IO uint32_t IR_RX_CNT_INT_SEL;            /*!< 0x24 */
+    __I  uint32_t IR_RX_FIFO;                   /*!< 0x28 */
+    __I  uint32_t IR_VERSION;                   /*!< 0x2C */
+    __I  uint32_t IR_RX_CUR_CNT;                /*!< 0x30 */
+    __IO uint32_t IR_RX_EX_INT;                 /*!< 0x34 */
+    __IO uint32_t RSVD_38[2];                   /*!< 0x38 */
+    __IO uint32_t IR_CTRL0;                     /*!< 0x40 */
+    __IO uint32_t IR_CTRL1;                     /*!< 0x44 */
+    __IO uint32_t IR_CTRL2;                     /*!< 0x48 */
+    __I  uint32_t IR_RX_LEVEL;                  /*!< 0x4C */
+    __IO uint32_t IR_DMA_CONFIG;                /*!< 0x50 */
+    __IO uint32_t IR_TASK_CTRL;                 /*!< 0x54 */
+    __IO uint32_t IR_QACTIVE_CTRL;              /*!< 0x58 */
+} IR_TypeDef;
+
+/*============================================================================*
+ *                          IR Declaration
+ *============================================================================*/
+#define IR                      ((IR_TypeDef *) IR_RC_BASE)
+
+#define IS_IR_PERIPH(PERIPH)    ((PERIPH) == IR)
+
+/*============================================================================*
+ *                          IR Private Types
+ *============================================================================*/
+typedef struct
+{
+    uint32_t ir_reg[6];
+} IRStoreReg_Typedef;
+
+/*============================================================================*
+ *                          IR Registers and Field Descriptions
+ *============================================================================*/
+/* 0x00
+   13:0    R/W    ir_clk_div                      14'h0
+   31:14   R      reserved31_13                   18'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t ir_clk_div: 14;
+        const uint32_t reserved_0: 18;
+    } b;
+} IR_CLK_DIV_TypeDef;
+
+
+/* 0x04
+   0       R/W    ir_tx_fifo_empty_int_en         1'h0
+   1       R/W    ir_tx_fifo_level_int_en         1'h0
+   2       R/W    ir_tx_fifo_empty_int_mask       1'h0
+   3       R/W    ir_tx_fifo_level_int_mask       1'h0
+   4       R/W    ir_tx_fifo_over_int_en          1'h0
+   5       R/W    ir_tx_fifo_over_int_mask        1'h0
+   6       R/W    ir_tx_idel_state                1'h0
+   7       R/W    ir_tx_output_mode               1'h0
+   12:8    R/W    ir_tx_fifo_level_th             5'h0
+   13      R/W    ir_tx_de_inverse                1'h0
+   14      R/W    ir_tx_output_inverse            1'h0
+   15      R/W    reg_flag_opt                    1'h0
+   29:16   R/W    ir_tx_duty_num                  14'h0
+   30      R/W    ir_tx_start                     1'h0
+   31      R/W    ir_mode_sel                     1'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t ir_tx_fifo_empty_int_en: 1;
+        uint32_t ir_tx_fifo_level_int_en: 1;
+        uint32_t ir_tx_fifo_empty_int_mask: 1;
+        uint32_t ir_tx_fifo_level_int_mask: 1;
+        uint32_t ir_tx_fifo_over_int_en: 1;
+        uint32_t ir_tx_fifo_over_int_mask: 1;
+        uint32_t ir_tx_idel_state: 1;
+        uint32_t ir_tx_output_mode: 1;
+        uint32_t ir_tx_fifo_level_th: 5;
+        uint32_t ir_tx_de_inverse: 1;
+        uint32_t ir_tx_output_inverse: 1;
+        uint32_t reg_flag_opt: 1;
+        uint32_t ir_tx_duty_num: 14;
+        uint32_t ir_tx_start: 1;
+        uint32_t ir_mode_sel: 1;
+    } b;
+} IR_TX_CONFIG_TypeDef;
+
+
+/* 0x08
+   0       R      ir_tx_fifo_empty_int_status     1'h0
+   1       R      ir_tx_fifo_level_int_status     1'h0
+   2       R      ir_tx_fifo_over_int_status      1'h0
+   3       R      ir_tx_finish_int_status         1'h0
+   4       R      ir_tx_status                    1'h0
+   5       R/W    ir_tx_finish_int_en             1'h0
+   6       R/W    ir_tx_finish_int_mask           1'h0
+   7       R      reserved7                       1'h0
+   13:8    R      ir_tx_fifo_offset               6'h0
+   14      R      ir_tx_fifo_full                 1'h0
+   15      R      ir_tx_fifo_empty                1'h0
+   31:16   R      reserved31_16                   16'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t ir_tx_fifo_empty_int_status: 1;
+        const uint32_t ir_tx_fifo_level_int_status: 1;
+        const uint32_t ir_tx_fifo_over_int_status: 1;
+        const uint32_t ir_tx_finish_int_status: 1;
+        const uint32_t ir_tx_status: 1;
+        uint32_t ir_tx_finish_int_en: 1;
+        uint32_t ir_tx_finish_int_mask: 1;
+        const uint32_t reserved_1: 1;
+        const uint32_t ir_tx_fifo_offset: 6;
+        const uint32_t ir_tx_fifo_full: 1;
+        const uint32_t ir_tx_fifo_empty: 1;
+        const uint32_t reserved_0: 16;
+    } b;
+} IR_TX_SR_TypeDef;
+
+
+
+
+/* 0x10
+   0       R/WAC  ir_tx_fifo_clr                  1'h0
+   1       R/W1C  ir_tx_fifo_empty_int_clr        1'h0
+   2       R/W1C  ir_tx_fifo_level_int_clr        1'h0
+   3       R/W1C  ir_tx_fifo_over_int_clr         1'h0
+   4       R/W1C  ir_tx_finish_int_clr            1'h0
+   31:5    R      reserved31_5                    27'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t ir_tx_fifo_clr: 1;
+        uint32_t ir_tx_fifo_empty_int_clr: 1;
+        uint32_t ir_tx_fifo_level_int_clr: 1;
+        uint32_t ir_tx_fifo_over_int_clr: 1;
+        uint32_t ir_tx_finish_int_clr: 1;
+        const uint32_t reserved_0: 27;
+    } b;
+} IR_TX_INT_CLR_TypeDef;
+
+
+/* 0x14
+   31:0    W      ir_tx_fifo                      32'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t ir_tx_fifo: 32;
+    } b;
+} IR_TX_FIFO_TypeDef;
+
+
+/* 0x18
+   0       R/W    ir_rx_fifo_full_int_en          1'h0
+   1       R/W    ir_rx_fifo_levle_int_en         1'h0
+   2       R/W    ir_rx_cnt_of_int_en             1'h0
+   3       R/W    ir_rx_fifo_of_int_en            1'h0
+   4       R/W    ir_rx_cnt_thr_int_en            1'h0
+   5       R/W    ir_rx_fifo_error_int_en         1'h0
+   7:6     R      reserved7_6                     2'h0
+   12:8    R/W    ir_rx_fifo_level_th             5'h0
+   13      R/W    ir_rx_fifo_discard_set          1'h0
+   14      R/W    ir_rx_fifo_full_int_mask        1'h0
+   15      R/W    ir_rx_fifo_level_int_mask       1'h0
+   16      R/W    ir_rx_cnt_of_int_mask           1'h0
+   17      R/W    ir_rx_fifo_of_int_mask          1'h0
+   18      R/W    ir_rx_cnt_thr_int_mask          1'h0
+   19      R/W    ir_rx_fifo_error_int_mask       1'h0
+   20      R      reserved20                      1'h0
+   23:21   R/W    ir_rx_filter_stage              3'h0
+   25:24   R/W    ir_rx_trigger_mode              2'h0
+   26      R/W    ir_rx_man_start                 1'h0
+   27      R/W    ir_rx_start_mode                1'h0
+   28      R/W    ir_rx_start                     1'h0
+   31:29   R      reserved31_29                   3'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t ir_rx_fifo_full_int_en: 1;
+        uint32_t ir_rx_fifo_levle_int_en: 1;
+        uint32_t ir_rx_cnt_of_int_en: 1;
+        uint32_t ir_rx_fifo_of_int_en: 1;
+        uint32_t ir_rx_cnt_thr_int_en: 1;
+        uint32_t ir_rx_fifo_error_int_en: 1;
+        const uint32_t reserved_2: 2;
+        uint32_t ir_rx_fifo_level_th: 5;
+        uint32_t ir_rx_fifo_discard_set: 1;
+        uint32_t ir_rx_fifo_full_int_mask: 1;
+        uint32_t ir_rx_fifo_level_int_mask: 1;
+        uint32_t ir_rx_cnt_of_int_mask: 1;
+        uint32_t ir_rx_fifo_of_int_mask: 1;
+        uint32_t ir_rx_cnt_thr_int_mask: 1;
+        uint32_t ir_rx_fifo_error_int_mask: 1;
+        const uint32_t reserved_1: 1;
+        uint32_t ir_rx_filter_stage: 3;
+        uint32_t ir_rx_trigger_mode: 2;
+        uint32_t ir_rx_man_start: 1;
+        uint32_t ir_rx_start_mode: 1;
+        uint32_t ir_rx_start: 1;
+        const uint32_t reserved_0: 3;
+    } b;
+} IR_RX_CONFIG_TypeDef;
+
+
+/* 0x1C
+   0       R      ir_rx_fifo_full_int_status      1'h0
+   1       R      ir_rx_fifo_level_int_status     1'h0
+   2       R      ir_rx_cnt_of_int_status         1'h0
+   3       R      ir_rx_fifo_of_int_status        1'h0
+   4       R      ir_rx_cnt_thr_int_status        1'h0
+   5       R      ir_rx_fifo_error_int_status     1'h0
+   6       R      reserved6                       1'h0
+   7       R      ir_rx_state                     1'h0
+   13:8    R      ir_rx_fifo_offset               6'h0
+   15:14   R      reserved15_14                   2'h0
+   16      R      ir_rx_fifo_full                 1'h0
+   17      R      ir_rx_fifo_empty                1'h0
+   31:18   R      reserved31_18                   14'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t ir_rx_fifo_full_int_status: 1;
+        const uint32_t ir_rx_fifo_level_int_status: 1;
+        const uint32_t ir_rx_cnt_of_int_status: 1;
+        const uint32_t ir_rx_fifo_of_int_status: 1;
+        const uint32_t ir_rx_cnt_thr_int_status: 1;
+        const uint32_t ir_rx_fifo_error_int_status: 1;
+        const uint32_t reserved_2: 1;
+        const uint32_t ir_rx_state: 1;
+        const uint32_t ir_rx_fifo_offset: 6;
+        const uint32_t reserved_1: 2;
+        const uint32_t ir_rx_fifo_full: 1;
+        const uint32_t ir_rx_fifo_empty: 1;
+        const uint32_t reserved_0: 14;
+    } b;
+} IR_RX_SR_TypeDef;
+
+
+/* 0x20
+   0       R/W1C  ir_rx_fifo_full_int_clr         1'h0
+   1       R/W1C  ir_rx_fifo_level_int_clr        1'h0
+   2       R/W1C  ir_rx_cnt_of_int_clr            1'h0
+   3       R/W1C  ir_rx_fifo_of_int_clr           1'h0
+   4       R/W1C  ir_rx_cnt_thr_int_clr           1'h0
+   5       R/W1C  ir_rx_fifo_error_int_clr        1'h0
+   6       R/W1C  ir_rx_falling_edge_int_clr      1'h0
+   7       R/W1C  ir_rx_rising_edge_int_clr       1'h0
+   8       R/WAC  ir_rx_fifo_clr                  1'h0
+   31:9    R      reserved31_9                    23'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t ir_rx_fifo_full_int_clr: 1;
+        uint32_t ir_rx_fifo_level_int_clr: 1;
+        uint32_t ir_rx_cnt_of_int_clr: 1;
+        uint32_t ir_rx_fifo_of_int_clr: 1;
+        uint32_t ir_rx_cnt_thr_int_clr: 1;
+        uint32_t ir_rx_fifo_error_int_clr: 1;
+        uint32_t ir_rx_falling_edge_int_clr: 1;
+        uint32_t ir_rx_rising_edge_int_clr: 1;
+        uint32_t ir_rx_fifo_clr: 1;
+        const uint32_t reserved_0: 23;
+    } b;
+} IR_RX_INT_CLR_TypeDef;
+
+
+/* 0x24
+   30:0    R/W    ir_rx_cnt_thr                   31'h0
+   31      R/W    ir_rx_cnt_thr_trigger_lv        1'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t ir_rx_cnt_thr: 31;
+        uint32_t ir_rx_cnt_thr_trigger_lv: 1;
+    } b;
+} IR_RX_CNT_INT_SEL_TypeDef;
+
+
+/* 0x28
+   31:0    R      ir_rx_fifo                      32'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t ir_rx_fifo: 32;
+    } b;
+} IR_RX_FIFO_TypeDef;
+
+
+/* 0x2C
+   31:0    R      rtl_version                     32'h20240226
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t rtl_version: 32;
+    } b;
+} IR_VERSION_TypeDef;
+
+
+/* 0x30
+   30:0    R      ir_rx_cur_cnt                   31'h0
+   31      R      ir_rx_cur_lv                    1'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t ir_rx_cur_cnt: 31;
+        const uint32_t ir_rx_cur_lv: 1;
+    } b;
+} IR_RX_CUR_CNT_TypeDef;
+
+
+/* 0x34
+   0       R/W    ir_rx_falling_edge_int_en       1'h0
+   1       R/W    ir_rx_rising_edge_int_en        1'h0
+   2       R/W    ir_rx_falling_edge_int_mask     1'h0
+   3       R/W    ir_rx_rising_edge_int_mask      1'h0
+   4       R      ir_rx_falling_edge_int_status   1'h0
+   5       R      ir_rx_rising_edge_int_status    1'h0
+   31:6    R      reserved31_6                    26'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t ir_rx_falling_edge_int_en: 1;
+        uint32_t ir_rx_rising_edge_int_en: 1;
+        uint32_t ir_rx_falling_edge_int_mask: 1;
+        uint32_t ir_rx_rising_edge_int_mask: 1;
+        const uint32_t ir_rx_falling_edge_int_status: 1;
+        const uint32_t ir_rx_rising_edge_int_status: 1;
+        const uint32_t reserved_0: 26;
+    } b;
+} IR_RX_EX_INT_TypeDef;
+
+
+
+
+/* 0x40
+   7:0     R      tx_time                         8'h0
+   13:8    R      tx_num                          6'h0
+   14      R      tx_int_n                        1'h1
+   15      R/W    reserved15                      1'h0
+   31:16   R/W    reg_div_1ms_num                 16'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t tx_time: 8;
+        const uint32_t tx_num: 6;
+        const uint32_t tx_int_n: 1;
+        uint32_t reserved_0: 1;
+        uint32_t reg_div_1ms_num: 16;
+    } b;
+} IR_CTRL0_TypeDef;
+
+
+/* 0x44
+   7:0     R      rx_time                         8'h0
+   19:8    R      rx_num                          12'h0
+   20      R/W    reg_rx_inv                      1'h0
+   21      R      rx_int_n                        1'h1
+   31:22   R      reserved31_22                   10'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t rx_time: 8;
+        const uint32_t rx_num: 12;
+        uint32_t reg_rx_inv: 1;
+        const uint32_t rx_int_n: 1;
+        const uint32_t reserved_0: 10;
+    } b;
+} IR_CTRL1_TypeDef;
+
+
+/* 0x48
+   1:0     R/W    reg_dbg_sel                     2'h0
+   2       R/W    reg_dbg_tx_data                 1'h0
+   3       R/W    reg_dbg_tx_man                  1'h0
+   4       R/W    reg_dbg_rx_fifo_sel             1'h0
+   5       R/W    reg_dbg_tx_fifo_sel             1'h0
+   15:6    R/W    reserved15_6                    10'h0
+   29:16   R/W    reg_tx_dummy_num                14'h0
+   31:30   R/W    reserved31_30                   2'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t reg_dbg_sel: 2;
+        uint32_t reg_dbg_tx_data: 1;
+        uint32_t reg_dbg_tx_man: 1;
+        uint32_t reg_dbg_rx_fifo_sel: 1;
+        uint32_t reg_dbg_tx_fifo_sel: 1;
+        uint32_t reserved_1: 10;
+        uint32_t reg_tx_dummy_num: 14;
+        uint32_t reserved_0: 2;
+    } b;
+} IR_CTRL2_TypeDef;
+
+
+/* 0x4C
+   0       R      ir_rx_level                     1'h0
+   31:1    R      reserved31_1                    31'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t ir_rx_level: 1;
+        const uint32_t reserved_0: 31;
+    } b;
+} IR_RX_LEVEL_TypeDef;
+
+
+/* 0x50
+   0       R/W    reg_dma_tx_en                   1'h0
+   6:1     R/W    reg_dma_tx_fifo_th              6'h0
+   7       R      reserved7                       1'h0
+   8       R/W    reg_dma_rx_en                   1'h0
+   14:9    R/W    reg_dma_rx_fifo_th              6'h0
+   31:15   R      reserved31_15                   17'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t reg_dma_tx_en: 1;
+        uint32_t reg_dma_tx_fifo_th: 6;
+        const uint32_t reserved_1: 1;
+        uint32_t reg_dma_rx_en: 1;
+        uint32_t reg_dma_rx_fifo_th: 6;
+        const uint32_t reserved_0: 17;
+    } b;
+} IR_DMA_CONFIG_TypeDef;
+
+
+/* 0x54
+   0       R/W    ir_rap_mode                     1'h0
+   1       R/WAC  ir_fw_task_start_tx             1'h0
+   2       R/WAC  ir_fw_task_start_rx             1'h0
+   31:3    R      reserved31_3                    29'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t ir_rap_mode: 1;
+        uint32_t ir_fw_task_start_tx: 1;
+        uint32_t ir_fw_task_start_rx: 1;
+        const uint32_t reserved_0: 29;
+    } b;
+} IR_TASK_CTRL_TypeDef;
+
+
+/* 0x58
+   0       R/W    qact_pclk_icg_en                1'h0
+   1       R/W    qact_sclk_man_data              1'h0
+   2       R/W    qact_sclk_man_en                1'h0
+   3       R/W    qact_pclk_man_data              1'h0
+   4       R/W    qact_pclk_man_en                1'h0
+   5       R/W    qact_pwr_man_data               1'h0
+   6       R/W    qact_pwr_man_en                 1'h0
+   31:7    R      reserved31_7                    25'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t qact_pclk_icg_en: 1;
+        uint32_t qact_sclk_man_data: 1;
+        uint32_t qact_sclk_man_en: 1;
+        uint32_t qact_pclk_man_data: 1;
+        uint32_t qact_pclk_man_en: 1;
+        uint32_t qact_pwr_man_data: 1;
+        uint32_t qact_pwr_man_en: 1;
+        const uint32_t reserved_0: 25;
+    } b;
+} IR_QACTIVE_CTRL_TypeDef;
+
+
+/*============================================================================*
+ *                         Constants
+ *============================================================================*/
+/** \defgroup IR          IR
+  * \brief
+  * \{
+  */
+
+/** \defgroup IR_Exported_Constants IR Exported Constants
+  * \brief
+  * \{
+  */
+
+/**
+ * \defgroup    IR_Clock_Source IR Clock Source
+ * \{
+ * \ingroup     IR_Exported_Constants
+ */
+typedef enum
+{
+    IR_CLOCK_SRC_OSC40M,
+    IR_CLOCK_SRC_XTAL40M,
+    IR_CLOCK_SRC_PPL1,
+} IRClockSrc_TypeDef;
+
+#define IS_IR_CLOCK_SRC(CLOCK)    (((CLOCK) == IR_CLOCK_SRC_OSC40M) || \
+                                   ((CLOCK) == IR_CLOCK_SRC_XTAL40M) || \
+                                   ((CLOCK) == IR_CLOCK_SRC_PPL1))
+
+/** End of IR_Clock_Source
+  * \}
+  */
+
+/**
+ * \defgroup    IR_Clock_Divider IR Clock Divider
+ * \{
+ * \ingroup     IR_Exported_Constants
+ */
+typedef enum
+{
+    IR_CLOCK_DIV_1 = 0x0,
+} IRClockDiv_TypeDef;
+
+#define IS_IR_CLOCK_DIV(DIV) (((DIV) == IR_CLOCK_DIV_1))
+
+/** End of IR_Clock_Divider
+  * \}
+  */
+
+
+/**
+ * \defgroup    IR_Clock IR Clock
+ * \{
+ * \ingroup     IR_Exported_Constants
+ */
+typedef enum
+{
+    IR_CLOCK_40M = 40000000,
+    IR_CLOCK_80M = 80000000,
+} IRClock_TypeDef;
+
+#define IS_IR_CLOCK(CLOCK)     (((CLOCK) == IR_CLOCK_40M) || ((CLOCK) == IR_CLOCK_80M))
+#define IS_IR_FREQUENCY_40M(F) (((F) >= 2442) && ((F) <= 2000000))
+#define IS_IR_FREQUENCY_80M(F) (((F) >= 4882) && ((F) <= 2000000))
+
+/** End of IR_Clock
+  * \}
+  */
+
+/** End of IR_Exported_Constants
+  * \}
+  */
+
+/** End of IR
+  * \}
+  */
+
+#ifdef  __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* RTL_IR_DEF_H */
diff --git a/bee/drivers/ir/src/device/rtl_common/rtl_ir.c b/bee/drivers/ir/src/device/rtl_common/rtl_ir.c
new file mode 100644
index 00000000..e488d654
--- /dev/null
+++ b/bee/drivers/ir/src/device/rtl_common/rtl_ir.c
@@ -0,0 +1,937 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *                           Header Files
+ *============================================================================*/
+#include "rtl_ir.h"
+#include "rtl_rcc.h"
+
+/*============================================================================*
+ *                           Private Functions
+ *============================================================================*/
+/* IR Immediate Number */
+#define IR_RX_EXTENSION_INT_OFFSET                  6
+#define IR_RX_EXTENSION_MASK_INT_OFFSET             4
+#define IR_RX_EXTENSION_INT_STS_OFFSET              2
+#define IR_RX_MSK_TO_EN_POS                         14
+#define IR_TX_FIFO_OVER_MSK_TO_EN_POS               1
+#define IR_TX_FINISH_MSK_TO_EN_POS                  1
+#define IR_TX_MSK_TO_EN_POS                         2
+#define IR_TX_STATUS_TO_EN_POS                      2
+
+#define IR_DATA_TYPE_MSK                            BIT31
+#define IR_TX_LAST_PACKEET_MSK                      BIT30
+
+/*============================================================================*
+ *                           Public Functions
+ *============================================================================*/
+/**
+  * \brief  Deinitializes the IR peripheral registers to their default values.
+  * \param  None
+  * \return None
+  */
+void IR_DeInit(void)
+{
+    RCC_ClockCmd(IR_CLOCK, DISABLE);
+}
+
+/**
+  * \brief  Initializes the IR peripheral according to the specified
+  *         parameters in the IR_InitStruct
+  * \param  IR_InitStruct: Pointer to a IR_InitTypeDef structure that
+  *         contains the configuration information for the specified IR peripheral
+  * \return None
+  */
+void IR_Init(IR_InitTypeDef *IR_InitStruct)
+{
+    /* Check the parameters */
+    assert_param(IS_IR_CLOCK(IR_InitStruct->IR_Clock));
+
+    if (IR_InitStruct->IR_Clock == 40000000)
+    {
+        assert_param(IS_IR_FREQUENCY_40M(IR_InitStruct->IR_Freq));
+    }
+#if  IR_SUPPORT_CLOCK_SOURCE_80M
+    else if (IR_InitStruct->IR_Clock == 80000000)
+    {
+        assert_param(IS_IR_FREQUENCY_80M(IR_InitStruct->IR_Freq));
+    }
+#endif
+#if IR_SUPPORT_CLOCK_SOURCE_90M
+    else if (IR_InitStruct->IR_Clock == 90000000)
+    {
+        assert_param(IS_IR_FREQUENCY_90M(IR_InitStruct->IR_Freq));
+    }
+#endif
+#if  IR_SUPPORT_CLOCK_SOURCE_100M
+    else if (IR_InitStruct->IR_Clock == 100000000)
+    {
+        assert_param(IS_IR_FREQUENCY_100M(IR_InitStruct->IR_Freq));
+    }
+#endif
+    assert_param(IS_IR_MODE(IR_InitStruct->IR_Mode));
+
+
+    /* Configure IR clock divider. Formula: IR_CLK = IO_CLK/(1+IR_CLK_DIV) */
+    uint32_t ir_clk_div_num = (IR_InitStruct->IR_Clock / IR_InitStruct->IR_Freq) - 1;
+    uint32_t duty_cycle_num = ((double)(ir_clk_div_num + 1.0)) / (IR_InitStruct->IR_DutyCycle);
+
+    IR_CLK_DIV_TypeDef ir_0x00 = {.d32 = IR->IR_CLK_DIV};
+    ir_0x00.b.ir_clk_div = ir_clk_div_num;
+    IR->IR_CLK_DIV = ir_0x00.d32;
+    if (IR_InitStruct->IR_Mode == IR_MODE_TX)
+    {
+        /* Check the parameters in TX mode */
+        assert_param(IS_IR_IDLE_STATUS(IR_InitStruct->IR_TxIdleLevel));
+        assert_param(IS_IR_TX_DATA_TYPE(IR_InitStruct->IR_TxInverse));
+        assert_param(IS_IR_TX_THRESHOLD(IR_InitStruct->IR_TxFIFOThrLevel));
+
+        /* Stop Transmission mode */
+        IR_TX_CONFIG_TypeDef ir_0x04 = {.d32 = IR->IR_TX_CONFIG};
+        ir_0x04.b.ir_tx_start = 0;
+
+        /* Configure TX mode parameters and disable all TX interrupt */
+        ir_0x04.b.ir_mode_sel = IR_InitStruct->IR_Mode;
+        ir_0x04.b.ir_tx_idel_state = IR_InitStruct->IR_TxIdleLevel;
+        ir_0x04.b.ir_tx_de_inverse = IR_InitStruct->IR_TxInverse;
+        ir_0x04.b.ir_tx_fifo_level_th = IR_InitStruct->IR_TxFIFOThrLevel;
+        ir_0x04.b.ir_tx_duty_num = duty_cycle_num & 0x3FFF;
+#if IR_SUPPORT_TX_MODE_CONFIG
+        ir_0x04.b.ir_tx_output_mode = IR_InitStruct->IR_TxOutputMode;
+#endif
+        IR->IR_TX_CONFIG = ir_0x04.d32;
+
+        /* Clear all TX interrupt and TX FIFO */
+        IR->IR_TX_INT_CLR = IR_TX_INT_ALL_CLR | IR_TF_CLR;
+
+        /* Config dma tx */
+        IR_DMA_CONFIG_TypeDef ir_0x50 = {.d32 = IR->IR_DMA_CONFIG};
+        ir_0x50.d32 = 0;
+        ir_0x50.b.reg_dma_tx_en = IR_InitStruct->IR_TxDMAEn;
+        ir_0x50.b.reg_dma_tx_fifo_th = IR_InitStruct->IR_TxWaterLevel;
+        IR->IR_DMA_CONFIG = ir_0x50.d32;
+    }
+    else
+    {
+        /* Check the parameters in RX mode */
+        assert_param(IS_RX_START_MODE(IR_InitStruct->IR_RxStartMode));
+        assert_param(IS_IR_RX_THRESHOLD(IR_InitStruct->IR_RxFIFOThrLevel));
+        assert_param(IS_IR_RX_FIFO_FULL_CTRL(IR_InitStruct->IR_RxFIFOFullCtrl));
+        assert_param(IS_RX_RX_TRIGGER_EDGE(IR_InitStruct->IR_RxTriggerMode));
+        assert_param(IS_IR_RX_FILTER_TIME_CTRL(IR_InitStruct->IR_RxFilterTime));
+        assert_param(IS_IR_RX_COUNT_LEVEL_CTRL(IR_InitStruct->IR_RxCntThrType));
+        assert_param(IS_IR_RX_COUNTER_THRESHOLD(IR_InitStruct->IR_RxCntThr));
+
+        /* Stop Receiving mode */
+        IR_RX_CONFIG_TypeDef ir_0x18 = {.d32 = IR->IR_RX_CONFIG};
+        ir_0x18.b.ir_rx_start = 0;
+        IR->IR_RX_CONFIG = ir_0x18.d32;
+
+        /* Enable RX mode */
+        IR_TX_CONFIG_TypeDef ir_0x04 = {.d32 = IR->IR_TX_CONFIG};
+        ir_0x04.b.ir_mode_sel = IR_InitStruct->IR_Mode;
+        IR->IR_TX_CONFIG = ir_0x04.d32;
+
+        /* Configure RX mode parameters and disable all RX interrupt */
+        ir_0x18.b.ir_rx_start_mode = IR_InitStruct->IR_RxStartMode;
+        ir_0x18.b.ir_rx_trigger_mode = IR_InitStruct->IR_RxTriggerMode;
+        ir_0x18.b.ir_rx_filter_stage = IR_InitStruct->IR_RxFilterTime;
+        ir_0x18.b.ir_rx_fifo_discard_set = IR_InitStruct->IR_RxFIFOFullCtrl;
+        ir_0x18.b.ir_rx_fifo_level_th = IR_InitStruct->IR_RxFIFOThrLevel;
+        IR->IR_RX_CONFIG = ir_0x18.d32;
+
+        /* Configure IR RX counter threshold parameters */
+        IR_RX_CNT_INT_SEL_TypeDef ir_0x24 = {.d32 = IR->IR_RX_CNT_INT_SEL};
+        ir_0x24.b.ir_rx_cnt_thr_trigger_lv = IR_InitStruct->IR_RxCntThrType;
+        ir_0x24.b.ir_rx_cnt_thr = IR_InitStruct->IR_RxCntThr;
+        IR->IR_RX_CNT_INT_SEL = ir_0x24.d32;
+
+        /* Clear all RX interrupt and RX FIFO */
+        IR->IR_RX_INT_CLR = IR_RX_INT_ALL_CLR | IR_RF_CLR;
+
+        /* Config dma rx */
+        IR_DMA_CONFIG_TypeDef ir_0x50 = {.d32 = IR->IR_DMA_CONFIG};
+        ir_0x50.b.reg_dma_rx_en = IR_InitStruct->IR_RxDMAEn;
+        ir_0x50.b.reg_dma_rx_fifo_th = IR_InitStruct->IR_RxWaterLevel;
+        IR->IR_DMA_CONFIG = ir_0x50.d32;
+    }
+}
+
+/**
+  * \brief  Fills each IR_InitStruct member with its default value.
+  * \param  IR_InitStruct: Pointer to an IR_InitTypeDef structure which will be initialized.
+  * \return None
+  */
+void IR_StructInit(IR_InitTypeDef *IR_InitStruct)
+{
+    /* IR source clock is 40MHz */
+    IR_InitStruct->IR_Clock             = IR_CLOCK_40M;
+    /* IR carrier freqency is 38KHz */
+    IR_InitStruct->IR_Freq              = 38000;
+    IR_InitStruct->IR_DutyCycle         = 3;
+    /* IR transmitting mode */
+    IR_InitStruct->IR_Mode              = IR_MODE_TX;
+    /* Tx pin output low when tx is idle */
+    IR_InitStruct->IR_TxIdleLevel       = IR_IDLE_OUTPUT_LOW;
+    /* Do not inverse tx data */
+    IR_InitStruct->IR_TxInverse         = IR_TX_DATA_NORMAL;
+    /* Configure RX FIFO threshold level to trigger IR_INT_RF_LEVEL interrupt */
+    /* Tx fifo depth: 32 bytes */
+    IR_InitStruct->IR_TxFIFOThrLevel    = 0;
+    /* Rx auto start */
+    IR_InitStruct->IR_RxStartMode       = IR_RX_AUTO_MODE;
+    /* Rx fifo depth: 32 bytes */
+    IR_InitStruct->IR_RxFIFOThrLevel    = 0;
+    /* Discard the oldest received dta if RX FIFO is full */
+    IR_InitStruct->IR_RxFIFOFullCtrl    = IR_RX_FIFO_FULL_DISCARD_NEWEST;
+    /* Falling edge will trigger rx */
+    IR_InitStruct->IR_RxTriggerMode     = IR_RX_FALL_EDGE;
+    /* If high to low or low to high transition time <= 50ns,Filter out it. */
+    IR_InitStruct->IR_RxFilterTime      = IR_RX_FILTER_TIME_50NS;
+    /* Configure trigger type */
+    IR_InitStruct->IR_RxCntThrType      = IR_RX_COUNT_LOW_LEVEL;
+    /* Configure RX counter threshold.You can use it to decide to stop receiving IR data
+       This value can be 0 to 0x7fffffff */
+    IR_InitStruct->IR_RxCntThr          = 0x23a;
+    /* Disable tx dma */
+    IR_InitStruct->IR_TxDMAEn           = DISABLE;
+    /* IR Tx waterlevel, should be less than fifo threshold.
+       The best value is IR FIFO Depth - DMA Msize */
+    IR_InitStruct->IR_TxWaterLevel      = 31;
+    /* Disable rx dma */
+    IR_InitStruct->IR_RxDMAEn           = DISABLE;
+    /* IR Rx waterlevel, should be less than fifo threshold.
+       The best value is DMA Msize */
+    IR_InitStruct->IR_RxWaterLevel      = 1;
+
+#if IR_SUPPORT_TX_MODE_CONFIG
+    IR_InitStruct->IR_TxOutputMode      = IR_TX_PUSH_PULL;
+#endif
+}
+
+/**
+  * \brief  Enable or disable the selected IR mode.
+  * \param  mode: Selected IR operation mode.
+  *         This parameter can be the following values:
+  *         \arg IR_MODE_TX: Transmission mode.
+  *         \arg IR_MODE_RX: Receiving mode.
+  * \param  NewState: New state of the operation mode.
+  *         This parameter can be: ENABLE or DISABLE.
+  * \return None
+  */
+void IR_Cmd(uint32_t mode, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_IR_MODE(mode));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+    if (mode == IR_MODE_TX)
+    {
+        /* Start or stop Transmission mode */
+        IR_TX_CONFIG_TypeDef ir_0x04 = {.d32 = IR->IR_TX_CONFIG};
+        ir_0x04.b.ir_tx_start = NewState;
+        IR->IR_TX_CONFIG = ir_0x04.d32;
+    }
+    else
+    {
+        /* Start or stop Receiving mode */
+        IR_RX_CONFIG_TypeDef ir_0x18 = {.d32 = IR->IR_RX_CONFIG};
+        ir_0x18.b.ir_rx_start = NewState;
+        IR->IR_RX_CONFIG = ir_0x18.d32;
+    }
+}
+
+/**
+  * \brief  Mask or unmask the specified IR interrupts.
+  * \param  IR_INT: Specifies the IR interrupts sources to be mask or unmask.
+  *         This parameter can be the following values:
+  *         \arg IR_INT_TF_EMPTY: TX FIFO empty interrupt.
+  *         \arg IR_INT_TF_LEVEL: TX FIFO threshold interrupt.
+  *         \arg IR_INT_TF_OF: TX FIFO overflow interrupt.
+  *         \arg IR_INT_TF_FINISH: TX finish interrupt.
+  *         \arg IR_INT_RF_FULL: RX FIFO  full interrupt.
+  *         \arg IR_INT_RF_LEVEL: RX FIFO threshold interrupt.
+  *         \arg IR_INT_RX_CNT_OF: RX counter overflow interrupt.
+  *         \arg IR_INT_RF_OF: RX FIFO overflow interrupt.
+  *         \arg IR_INT_RX_CNT_THR: RX counter threshold interrupt.
+  *         \arg IR_INT_RF_ERROR: RX FIFO error read interrupt. Trigger when RX FIFO empty and read RX FIFO.
+  *         \arg IR_INT_RISING_EDGE: IR RX Rising edge interrupt.
+  *         \arg IR_INT_FALLING_EDGE: IR RX Falling edge interrupt.
+  * \param  NewState: New state of the specified IR interrupts.
+  *         This parameter can be: ENABLE or DISABLE.
+  * \return None
+  */
+void IR_MaskINTConfig(uint32_t IR_INT, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_IR_INT_CONFIG(IR_INT));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    IR_TX_CONFIG_TypeDef ir_0x04 = {.d32 = IR->IR_TX_CONFIG};
+    if (NewState == ENABLE)
+    {
+        /* Enable the selected IR interrupts in RX mode */
+        if (ir_0x04.b.ir_mode_sel)
+        {
+            /* Handle RX Edge Interrupts (Rising/Falling) specifically */
+            if (IR_INT & (IR_INT_RISING_EDGE | IR_INT_FALLING_EDGE))
+            {
+                IR->IR_RX_EX_INT |= ((IR_INT & (IR_INT_RISING_EDGE | IR_INT_FALLING_EDGE)) >>
+                                     IR_RX_EXTENSION_MASK_INT_OFFSET);
+            }
+            /* Handle Normal RX Interrupts. Exclude edge interrupts to avoid incorrect bit shifting into IR_RX_CONFIG */
+            if ((IR_INT & (~(IR_INT_RISING_EDGE | IR_INT_FALLING_EDGE))) != 0)
+            {
+                IR->IR_RX_CONFIG |= ((IR_INT & (~(IR_INT_RISING_EDGE | IR_INT_FALLING_EDGE))) <<
+                                     IR_RX_MSK_TO_EN_POS);
+            }
+        }
+        /* Enable the selected IR interrupts in TX mode */
+        else
+        {
+            /* Handle TX FIFO Overflow independently. TF_OF has a unique bit shift position regardless of other settings */
+            if (IR_INT & IR_INT_TF_OF)
+            {
+                IR->IR_TX_CONFIG |= ((IR_INT & IR_INT_TF_OF) << IR_TX_FIFO_OVER_MSK_TO_EN_POS);
+            }
+#if (IR_SUPPORT_TX_FINISH_INTERRUPT == 1)
+            /* Handle TX Finish Interrupt */
+            if (IR_INT & IR_INT_TX_FINISH)
+            {
+                IR->IR_TX_SR |= ((IR_INT & IR_INT_TX_FINISH) << IR_TX_FINISH_MSK_TO_EN_POS);
+            }
+            /* Handle Remaining TX Interrupts. Exclude IR_INT_TF_OF and IR_INT_TX_FINISH as they are already handled above */
+            if ((IR_INT & (~(IR_INT_TF_OF | IR_INT_TX_FINISH))) != 0)
+            {
+                IR->IR_TX_CONFIG |= ((IR_INT & (~(IR_INT_TF_OF | IR_INT_TX_FINISH))) << IR_TX_MSK_TO_EN_POS);
+            }
+#else
+            /* Handle Remaining TX Interrupts. Exclude IR_INT_TF_OF to prevent double configuration with incorrect shift */
+            if ((IR_INT & (~IR_INT_TF_OF)) != 0)
+            {
+                IR->IR_TX_CONFIG |= ((IR_INT & (~IR_INT_TF_OF)) << IR_TX_MSK_TO_EN_POS);
+            }
+#endif
+        }
+    }
+    else
+    {
+        /* Disable the selected IR interrupts in RX mode */
+        if (ir_0x04.b.ir_mode_sel)
+        {
+            /* Disable RX Edge Interrupts */
+            if (IR_INT & (IR_INT_RISING_EDGE | IR_INT_FALLING_EDGE))
+            {
+                IR->IR_RX_EX_INT &= ~((IR_INT & (IR_INT_RISING_EDGE | IR_INT_FALLING_EDGE)) >>
+                                      IR_RX_EXTENSION_MASK_INT_OFFSET);
+            }
+            /* Disable Normal RX Interrupts */
+            if ((IR_INT & (~(IR_INT_RISING_EDGE | IR_INT_FALLING_EDGE))) != 0)
+            {
+                IR->IR_RX_CONFIG &= ~((IR_INT & (~(IR_INT_RISING_EDGE | IR_INT_FALLING_EDGE))) <<
+                                      IR_RX_MSK_TO_EN_POS);
+            }
+        }
+        /* Disable the selected IR interrupts in TX mode */
+        else
+        {
+            /* Disable TX FIFO Overflow */
+            if (IR_INT & IR_INT_TF_OF)
+            {
+                IR->IR_TX_CONFIG &= (~((IR_INT & IR_INT_TF_OF) << IR_TX_FIFO_OVER_MSK_TO_EN_POS));
+            }
+#if (IR_SUPPORT_TX_FINISH_INTERRUPT == 1)
+            /* Disable TX Finish Interrupt */
+            if (IR_INT & IR_INT_TX_FINISH)
+            {
+                IR->IR_TX_SR &= ~((IR_INT & IR_INT_TX_FINISH) << IR_TX_FINISH_MSK_TO_EN_POS);
+            }
+            /* Disable Remaining TX Interrupts */
+            if ((IR_INT & (~(IR_INT_TF_OF | IR_INT_TX_FINISH))) != 0)
+            {
+                IR->IR_TX_CONFIG &= ~((IR_INT & (~(IR_INT_TF_OF | IR_INT_TX_FINISH))) << IR_TX_MSK_TO_EN_POS);
+            }
+#else
+            /* Disable Remaining TX Interrupts. Exclude IR_INT_TF_OF to avoid writing it to the wrong register. */
+            if ((IR_INT & (~IR_INT_TF_OF)) != 0)
+            {
+                IR->IR_TX_CONFIG &= (~((IR_INT & (~IR_INT_TF_OF)) << IR_TX_MSK_TO_EN_POS));
+            }
+#endif
+        }
+    }
+}
+
+/**
+  * \brief  Enables or disables the specified IR interrupts.
+  * \param  IR_INT: Specifies the IR interrupts sources to be enabled or disabled.
+  *         This parameter can be the following values:
+  *         \arg IR_INT_TF_EMPTY: TX FIFO empty interrupt.
+  *         \arg IR_INT_TF_LEVEL: TX FIFO threshold interrupt.
+  *         \arg IR_INT_TF_OF: TX FIFO overflow interrupt.
+  *         \arg IR_INT_TF_FINISH: TX finish interrupt.
+  *         \arg IR_INT_RF_FULL: RX FIFO  full interrupt.
+  *         \arg IR_INT_RF_LEVEL: RX FIFO threshold interrupt.
+  *         \arg IR_INT_RX_CNT_OF: RX counter overflow interrupt.
+  *         \arg IR_INT_RF_OF: RX FIFO overflow interrupt.
+  *         \arg IR_INT_RX_CNT_THR: RX counter threshold interrupt.
+  *         \arg IR_INT_RF_ERROR: RX FIFO error read interrupt. Trigger when RX FIFO empty and read RX FIFO.
+  *         \arg IR_INT_RISING_EDGE: IR RX Rising edge interrupt.
+  *         \arg IR_INT_FALLING_EDGE: IR RX Falling edge interrupt.
+  * \param  NewState: New state of the specified IR interrupts.
+  *         This parameter can be: ENABLE or DISABLE.
+  * \return None
+  */
+void IR_INTConfig(uint32_t IR_INT, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_IR_INT_CONFIG(IR_INT));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    IR_TX_CONFIG_TypeDef ir_0x04 = {.d32 = IR->IR_TX_CONFIG};
+    if (NewState == ENABLE)
+    {
+        /* Enable the selected IR interrupts in RX mode */
+        if (ir_0x04.b.ir_mode_sel)
+        {
+            /* Handle RX Edge Interrupts (Rising/Falling), require specific offset shifting*/
+            if (IR_INT & (IR_INT_RISING_EDGE | IR_INT_FALLING_EDGE))
+            {
+                IR->IR_RX_EX_INT |= ((IR_INT & (IR_INT_RISING_EDGE | IR_INT_FALLING_EDGE)) >>
+                                     IR_RX_EXTENSION_INT_OFFSET);
+            }
+            /* Handle Normal RX Interrupts. Exclude edge interrupts to prevent writing incorrect bits to this register. */
+            if ((IR_INT & (~(IR_INT_RISING_EDGE | IR_INT_FALLING_EDGE))) != 0)
+            {
+                IR->IR_RX_CONFIG |= (IR_INT & (~(IR_INT_RISING_EDGE | IR_INT_FALLING_EDGE)));
+            }
+        }
+        /* Enable the selected IR interrupts in TX mode */
+        else
+        {
+#if (IR_SUPPORT_TX_FINISH_INTERRUPT == 1)
+            /* Handle TX Finish Interrupt */
+            if (IR_INT & IR_INT_TX_FINISH)
+            {
+                IR->IR_TX_SR |= IR_INT_TX_FINISH;
+            }
+            /* Handle Normal TX Interrupts. Exclude IR_INT_TX_FINISH to avoid writing it to the wrong register. */
+            if ((IR_INT & (~IR_INT_TX_FINISH)) != 0)
+            {
+                /* Enable the selected IR interrupts in TX mode */
+                IR->IR_TX_CONFIG |= (IR_INT & (~IR_INT_TX_FINISH));
+            }
+#else
+            /* Handle TX Interrupts. */
+            IR->IR_TX_CONFIG |= IR_INT;
+#endif
+        }
+    }
+    else
+    {
+        /* Disable the selected IR interrupts in RX mode */
+        if (ir_0x04.b.ir_mode_sel)
+        {
+            /* Disable RX Edge Interrupts */
+            if (IR_INT & (IR_INT_RISING_EDGE | IR_INT_FALLING_EDGE))
+            {
+                IR->IR_RX_EX_INT &= ~((IR_INT & (IR_INT_RISING_EDGE | IR_INT_FALLING_EDGE)) >>
+                                      IR_RX_EXTENSION_INT_OFFSET);
+            }
+            /* Disable Normal RX Interrupts. Exclude edge interrupts before writing to IR_RX_CONFIG */
+            if ((IR_INT & (~(IR_INT_RISING_EDGE | IR_INT_FALLING_EDGE))) != 0)
+            {
+                IR->IR_RX_CONFIG &= ~(IR_INT & (~(IR_INT_RISING_EDGE | IR_INT_FALLING_EDGE)));
+            }
+        }
+        /* Disable the selected IR interrupts in TX mode */
+        else
+        {
+#if (IR_SUPPORT_TX_FINISH_INTERRUPT == 1)
+            /* Disable TX Finish Interrupt */
+            if (IR_INT & IR_INT_TX_FINISH)
+            {
+                IR->IR_TX_SR &= ~IR_INT_TX_FINISH;
+            }
+            /* Disable/Clear Normal TX Interrupts. Exclude IR_INT_TX_FINISH before writing to IR_TX_CONFIG */
+            if ((IR_INT & (~IR_INT_TX_FINISH)) != 0)
+            {
+                IR->IR_TX_CONFIG &= ~(IR_INT & (~IR_INT_TX_FINISH));
+            }
+#else
+            /* Disable TX Interrupts */
+            IR->IR_TX_CONFIG &= (~IR_INT);
+#endif
+        }
+    }
+}
+
+/**
+  * \brief   Start trigger only in manual receive mode.
+  * \param  None.
+  * \return None
+  */
+void IR_StartManualRxTrigger(void)
+{
+    /* Start Rx manual mode */
+    IR_RX_CONFIG_TypeDef ir_0x18 = {.d32 = IR->IR_RX_CONFIG};
+    ir_0x18.b.ir_rx_man_start = 0x01;
+    IR->IR_RX_CONFIG = ir_0x18.d32;
+}
+
+/**
+  * \brief  Configure counter threshold value in receiving mode.You can use it to stop receiving IR data.
+  * \param  IR_RxCntThrType: This parameter can be the following values:
+  *         \arg IR_RX_Count_Low_Level: Low level counter value >= IR_RxCntThr, trigger IR_INT_RX_CNT_THR interrupt.
+  *         \arg IR_RX_Count_High_Level: High level counter value >= IR_RxCntThr, trigger IR_INT_RX_CNT_THR interrupt.
+  * \param  IR_RxCntThr: Configure IR Rx counter threshold value which can be 0 to 0x7fffffffUL.
+  * \return None
+  */
+void IR_SetRxCounterThreshold(uint32_t IR_RxCntThrType, uint32_t IR_RxCntThr)
+{
+    /* Check the parameters */
+    assert_param(IS_IR_RX_COUNT_LEVEL_CTRL(IR_RxCntThrType));
+    assert_param(IS_IR_RX_COUNTER_THRESHOLD(IR_RxCntThr));
+
+    /* Configure IR RX counter threshold parameters */
+    IR_RX_CNT_INT_SEL_TypeDef ir_0x24 = {.d32 = IR->IR_RX_CNT_INT_SEL};
+    ir_0x24.b.ir_rx_cnt_thr = IR_RxCntThr;
+    ir_0x24.b.ir_rx_cnt_thr_trigger_lv = IR_RxCntThrType;
+    IR->IR_RX_CNT_INT_SEL = ir_0x24.d32;
+}
+
+/**
+  * \brief  Send data.
+  * \param  pBuf: data buffer to send.
+  * \param  len: buffer length.
+  * \param  IsLastPacket: Is it the last package of data.
+  *         This parameter can be the following values:
+  *         \arg ENABLE: The last data in IR packet and there is no continuous data.In other words, An infrared data transmission is completed.
+  *         \arg DISABLE: There is data to be transmitted continuously.
+  * \return None
+  */
+void IR_SendBuf(uint32_t *pBuf, uint32_t len, FunctionalState IsLastPacket)
+{
+    /* Check the parameters */
+    assert_param(IS_FUNCTIONAL_STATE(IsLastPacket));
+
+    uint32_t i = 0;
+    if (len > 0)
+    {
+        i = len - 1;
+        while (i--)
+        {
+            IR->IR_TX_FIFO = *pBuf++;
+        }
+
+        /* If send the last IR packet, SET the following bit */
+        if (IsLastPacket == ENABLE)
+        {
+            IR->IR_TX_FIFO = (IR_TX_LAST_PACKEET_MSK | *pBuf);
+        }
+        else
+        {
+            IR->IR_TX_FIFO = *pBuf;
+        }
+    }
+}
+
+/**
+ * \brief  Send compensation data.
+ * \param  comp_type: Compensation data type.
+ *         \arg IR_COMPEN_FLAG_1_2_CARRIER: 1/2 carrier freqency.
+ *         \arg IR_COMPEN_FLAG_1_4_CARRIER: 1/4 carrier freqency.
+ *         \arg IR_COMPEN_FLAG_1_N_SYSTEM_CLK: MOD((0x48[27:16]+0x00[11:0]), 4095)/40MHz.
+ *         User can call function of IR_ConfigCompParam to configure 0x48[27:16].
+ * \param  buf: data buffer to send.
+ * \param  length: buffer length.
+ * \param  IsLastPacket: This parameter can be the following values:
+ *         \arg ENABLE: The last data in IR packet and there is no continuous data.In other words, An infrared data transmission is completed.
+ *         \arg DISABLE: There is data to be transmitted continuously.
+ * \return None
+ */
+void IR_SendCompenBuf(IRTxCompen_TypeDef comp_type, uint32_t *pBuf, uint32_t len,
+                      FunctionalState IsLastPacket)
+{
+    /* Check the parameters */
+    assert_param(IS_FUNCTIONAL_STATE(IsLastPacket));
+
+    uint32_t i = 0;
+    uint32_t temp = 0;
+    if (len > 0)
+    {
+        i = len - 1;
+        while (i--)
+        {
+            if (*pBuf & IR_DATA_TYPE_MSK)
+            {
+                IR->IR_TX_FIFO = *pBuf++;
+            }
+            else
+            {
+                IR->IR_TX_FIFO = *pBuf++ | comp_type;
+            }
+        }
+
+        /* If send the last IR packet, SET the following bit */
+        if (IsLastPacket == ENABLE)
+        {
+            temp = IR_TX_LAST_PACKEET_MSK;
+        }
+
+        if (*pBuf & IR_DATA_TYPE_MSK)
+        {
+            IR->IR_TX_FIFO = (temp | *pBuf);
+        }
+        else
+        {
+            IR->IR_TX_FIFO = (temp | *pBuf | comp_type);
+        }
+    }
+}
+
+/**
+  * \brief  Read data From RX FIO.
+  * \param  pBuf: Buffer address to receive data.
+  * \param  len: Read data length.
+  * \return None
+  */
+void IR_ReceiveBuf(uint32_t *pBuf, uint32_t len)
+{
+    while (len--)
+    {
+        *pBuf++ = IR->IR_RX_FIFO;
+    }
+}
+
+/**
+  * \brief Get the specified IR interrupt status.
+  * \param  IR_INT: The specified IR interrupts.
+  *         This parameter can be one of the following values:
+  *         \arg IR_INT_TF_EMPTY: TX FIFO empty interrupt.
+  *         \arg IR_INT_TF_LEVEL: TX FIFO threshold interrupt.
+  *         \arg IR_INT_TF_OF: TX FIFO overflow interrupt.
+  *         \arg IR_INT_TF_FINISH: TX finish interrupt.
+  *         \arg IR_INT_RF_FULL: RX FIFO  full interrupt.
+  *         \arg IR_INT_RF_LEVEL: RX FIFO threshold interrupt.
+  *         \arg IR_INT_RX_CNT_OF: RX counter overflow interrupt.
+  *         \arg IR_INT_RF_OF: RX FIFO overflow interrupt.
+  *         \arg IR_INT_RX_CNT_THR: RX counter threshold interrupt.
+  *         \arg IR_INT_RF_ERROR: RX FIFO error read interrupt. Trigger when RX FIFO empty and read RX FIFO.
+  *         \arg IR_INT_RISING_EDGE: IR RX Rising edge interrupt.
+  *         \arg IR_INT_FALLING_EDGE: IR RX Falling edge interrupt.
+  * \return The new state of IR_INT (SET or RESET).
+  */
+ITStatus IR_GetINTStatus(uint32_t IR_INT)
+{
+    /* Check the parameters */
+    assert_param(IS_IR_INT_CONFIG(IR_INT));
+
+    ITStatus bit_status = RESET;
+
+    IR_TX_CONFIG_TypeDef ir_0x04 = {.d32 = IR->IR_TX_CONFIG};
+    if (ir_0x04.b.ir_mode_sel)
+    {
+        /* Get the selected IR interrupts in RX mode */
+        if (IR_INT & (IR_INT_RISING_EDGE | IR_INT_FALLING_EDGE))
+        {
+            if (IR->IR_RX_EX_INT & (IR_INT >> IR_RX_EXTENSION_INT_STS_OFFSET))
+            {
+                bit_status = SET;
+            }
+        }
+        else
+        {
+            if (IR->IR_RX_SR & IR_INT)
+            {
+                bit_status = SET;
+            }
+        }
+    }
+    /* Get the selected IR interrupts in TX mode */
+    else
+    {
+#if (IR_SUPPORT_TX_FINISH_INTERRUPT == 1)
+        /* Check Normal TX Interrupts (TF_EMPTY, TF_LEVEL) */
+        if (IR_INT != IR_INT_TF_OF && IR_INT != IR_INT_TX_FINISH)
+#else
+        if (IR_INT != IR_INT_TF_OF)
+#endif
+        {
+            if (IR->IR_TX_SR & IR_INT)
+            {
+                bit_status = SET;
+            }
+        }
+        /* Check Special TX Interrupts */
+        else
+        {
+            if (IR->IR_TX_SR & (IR_INT >> IR_TX_STATUS_TO_EN_POS))
+            {
+                bit_status = SET;
+            }
+        }
+    }
+
+    /* Return the IR_INT status */
+    return  bit_status;
+}
+
+/**
+  * \brief  Clears the IR interrupt pending bits.
+  * \param  IR_IT: Specifies the interrupt pending bit to clear.
+  *         This parameter can be any combination of the following values:
+  *         \arg IR_INT_TF_EMPTY_CLR: Clear TX FIFO empty interrupt.
+  *         \arg IR_INT_TF_LEVEL_CLR: Clear TX FIFO threshold interrupt.
+  *         \arg IR_INT_TF_OF_CLR: Clear TX FIFO overflow interrupt.
+  *         \arg IR_INT_TX_FINISH_CLR: Clear TX finish interrupt.
+  *         \arg IR_INT_RF_FULL_CLR: Clear RX FIFO  full interrupt.
+  *         \arg IR_INT_RF_LEVEL_CLR: Clear RX FIFO threshold interrupt.
+  *         \arg IR_INT_RX_CNT_OF_CLR: Clear RX counter overflow interrupt.
+  *         \arg IR_INT_RF_OF_CLR: Clear RX FIFO overflow interrupt.
+  *         \arg IR_INT_RX_CNT_THR_CLR: Clear RX counter threshold interrupt.
+  *         \arg IR_INT_RF_ERROR_CLR: Clear RX FIFO error read interrupt. Trigger when RX FIFO empty and read RX FIFO.
+  *         \arg IR_INT_RX_RISING_EDGE_CLR: Clear RX Rising edge interrupt.
+  *         \arg IR_INT_RX_FALLING_EDGE_CLR: Clear RX Falling edge interrupt.
+  * \return None
+  */
+void IR_ClearINTPendingBit(uint32_t IR_CLEAR_INT)
+{
+    /* Check the parameters */
+    assert_param(IS_IR_INT_CLEAR(IR_CLEAR_INT));
+    IR_TX_CONFIG_TypeDef ir_0x04 = {.d32 = IR->IR_TX_CONFIG};
+
+    if (ir_0x04.b.ir_mode_sel)
+    {
+        /* Clear the selected IR interrupts in RX mode */
+//        if (IR_CLEAR_INT & IR_RX_EXTENSION_INT)
+//        {
+//            IR->IR_RX_EX_INT |= (IR_CLEAR_INT & 0xC0);
+//        }
+//        else
+//        {
+        IR->IR_RX_INT_CLR |= IR_CLEAR_INT;
+//        }
+    }
+    else
+    {
+        /* Clear the selected IR interrupts in TX mode */
+        IR->IR_TX_INT_CLR |= IR_CLEAR_INT;
+    }
+}
+
+/**
+  * \brief Get free size of TX FIFO.
+  * \param None.
+  * \return The free size of TX FIFO.
+  */
+uint16_t IR_GetTxFIFOFreeLen(void)
+{
+    IR_TX_SR_TypeDef ir_0x08 = {.d32 = IR->IR_TX_SR};
+    return (uint16_t)(IR_TX_FIFO_SIZE - ir_0x08.b.ir_tx_fifo_offset);
+}
+
+/**
+  * \brief Get data size in RX FIFO.
+  * \param None.
+  * \return Current data size in RX FIFO.
+  */
+uint16_t IR_GetRxDataLen(void)
+{
+    IR_RX_SR_TypeDef ir_0x1c = {.d32 = IR->IR_RX_SR};
+    return ((uint16_t)(ir_0x1c.b.ir_rx_fifo_offset));
+}
+
+/**
+  * \brief   Send one data.
+  * \param data: Send data.
+  * \return  None.
+  */
+void IR_SendData(uint32_t data)
+{
+    IR->IR_TX_FIFO = data;
+}
+
+/**
+  * \brief Read one data.
+  * \param None.
+  * \return Data which read from RX FIFO.
+  */
+uint32_t IR_ReceiveData(void)
+{
+    return IR->IR_RX_FIFO;
+}
+
+/**
+  * \brief  Set tx threshold, when TX FIFO depth <= threshold value trigger interrupt.
+  * \param thd: Tx threshold.
+  * \return None.
+  */
+void IR_SetTxThreshold(uint8_t thd)
+{
+    IR_TX_CONFIG_TypeDef ir_0x04 = {.d32 = IR->IR_TX_CONFIG};
+    ir_0x04.b.ir_tx_fifo_level_th = thd;
+    IR->IR_TX_CONFIG = ir_0x04.d32;
+}
+
+/**
+  * \brief   Set tx threshold, when RX FIFO depth >= threshold value trigger interrupt.
+  * \param thd: Rx threshold.
+  * \return  None.
+  */
+void IR_SetRxThreshold(uint8_t thd)
+{
+    IR_RX_CONFIG_TypeDef ir_0x18 = {.d32 = IR->IR_RX_CONFIG};
+    ir_0x18.b.ir_rx_fifo_level_th = thd;
+    IR->IR_RX_CONFIG = ir_0x18.d32;
+}
+
+/**
+  * \brief Get IR RX current count.
+  * \param None.
+  * \return Current counter.
+  */
+uint32_t IR_GetRxCurrentCount(void)
+{
+    IR_RX_CUR_CNT_TypeDef ir_0x30 = {.d32 = IR->IR_RX_CUR_CNT};
+    return ir_0x30.b.ir_rx_cur_cnt;
+}
+
+/**
+  * \brief Clear IR TX FIFO.
+  * \param None.
+  * \return None.
+  */
+void IR_ClearTxFIFO(void)
+{
+    IR_TX_INT_CLR_TypeDef ir_0x10 = {.d32 = IR->IR_TX_INT_CLR};
+    ir_0x10.b.ir_tx_fifo_clr = 0x01;
+    IR->IR_TX_INT_CLR = ir_0x10.d32;
+}
+
+/**
+  * \brief Clear IR RX FIFO.
+  * \param None.
+  * \return  None.
+  */
+void IR_ClearRxFIFO(void)
+{
+    IR_RX_INT_CLR_TypeDef ir_0x20 = {.d32 = IR->IR_RX_INT_CLR};
+    ir_0x20.b.ir_rx_fifo_clr = 0x01;
+    IR->IR_RX_INT_CLR = ir_0x20.d32;
+}
+
+/**
+  * \brief Check whether the specified IR flag is set.
+  * \param IR_FLAG: Specifies the flag to check.
+  *        This parameter can be one of the following values:
+  *        \arg IR_FLAG_TF_EMPTY: TX FIFO empty or not. If SET, TX FIFO is empty.
+  *        \arg IR_FLAG_TF_FULL: TX FIFO full or not. If SET, TX FIFO is full.
+  *        \arg IR_FLAG_TX_RUN: TX run or not. If SET, TX is running.
+  *        \arg IR_FLAG_RF_EMPTY: RX FIFO empty or not. If SET, RX FIFO is empty.
+  *        \arg IR_FLAG_RF_FULL: RX FIFO full or not. If SET, RX FIFO is full.
+  *        \arg IR_FLAG_RX_RUN: RX run or not. If SET, RX is running.
+  *
+  * \return The new state of IR_FLAG (SET or RESET).
+  */
+FlagStatus IR_GetFlagStatus(uint32_t IR_FLAG)
+{
+
+    /* Check the parameters */
+    assert_param(IS_IR_FLAG(IR_FLAG));
+
+    FlagStatus bitstatus = RESET;
+
+    IR_TX_CONFIG_TypeDef ir_0x04 = {.d32 = IR->IR_TX_CONFIG};
+    if (ir_0x04.b.ir_mode_sel)
+    {
+        if (IR->IR_RX_SR & IR_FLAG)
+        {
+            bitstatus = SET;
+        }
+        return bitstatus;
+    }
+    else
+    {
+        if (IR->IR_TX_SR & IR_FLAG)
+        {
+            bitstatus = SET;
+        }
+        return bitstatus;
+    }
+}
+
+/**
+  * \brief   Set or reset tx data inverse.
+  * \param NewState: This parameter can be: ENABLE or DISABLE.
+  * \return  None.
+  */
+void IR_TxWaveDefInverseCmd(FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    IR_TX_CONFIG_TypeDef ir_0x04 = {.d32 = IR->IR_TX_CONFIG};
+    ir_0x04.b.ir_tx_de_inverse = NewState;
+    IR->IR_TX_CONFIG = ir_0x04.d32;
+}
+
+/**
+  * \brief  Enbale TX output inverse or not.
+  * \param NewState: This parameter can be: ENABLE or DISABLE.
+  * \return None.
+  */
+void IR_TxPolarityInverseCmd(FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    IR_TX_CONFIG_TypeDef ir_0x04 = {.d32 = IR->IR_TX_CONFIG};
+    ir_0x04.b.ir_tx_output_inverse = NewState;
+    IR->IR_TX_CONFIG = ir_0x04.d32;
+}
+
+/**
+  * \brief Get IR RX Level.
+  * \param None.
+  * \return Current Level.
+  */
+uint32_t IR_GetRxCurrentLevel(void)
+{
+    return (IR->IR_RX_LEVEL);
+
+}
+
+#if (IR_SUPPORT_RAP_FUNCTION == 1)
+void IR_RAPModeCmd(FunctionalState NewState)
+{
+    IR_TASK_CTRL_TypeDef ir_0x54 = {.d32 = IR->IR_TASK_CTRL};
+    ir_0x54.b.ir_rap_mode = NewState;
+    IR->IR_TASK_CTRL = ir_0x54.d32;
+
+    return;
+}
+
+void IR_ActionTrigger(uint32_t Action)
+{
+    IR_TASK_CTRL_TypeDef ir_0x54 = {.d32 = IR->IR_TASK_CTRL};
+    if (Action == IR_ACTION_START_TX)
+    {
+        ir_0x54.b.ir_fw_task_start_tx = 0x1;
+    }
+    else if (Action == IR_ACTION_START_RX)
+    {
+        ir_0x54.b.ir_fw_task_start_rx = 0x1;
+    }
+    IR->IR_TASK_CTRL = ir_0x54.d32;
+
+    return;
+}
+
+#endif
+
+
+
diff --git a/bee/drivers/irq/CMakeLists.txt b/bee/drivers/irq/CMakeLists.txt
new file mode 100644
index 00000000..e2a912c3
--- /dev/null
+++ b/bee/drivers/irq/CMakeLists.txt
@@ -0,0 +1,8 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+if(CONFIG_REALTEK_BEE_COMMON_DRIVER)
+    zephyr_include_directories(inc)
+endif()
+
+add_subdirectory_ifdef(CONFIG_REALTEK_BEE_NVIC src)
diff --git a/bee/drivers/irq/Kconfig b/bee/drivers/irq/Kconfig
new file mode 100644
index 00000000..e12f194e
--- /dev/null
+++ b/bee/drivers/irq/Kconfig
@@ -0,0 +1,8 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config REALTEK_BEE_NVIC
+	bool "Realtek Bee IRQ driver"
+	default n
+	help
+	  This option enables the IRQ driver for Realtek Bee.
diff --git a/bee/drivers/irq/inc/rtl_nvic.h b/bee/drivers/irq/inc/rtl_nvic.h
new file mode 100644
index 00000000..e8e8daee
--- /dev/null
+++ b/bee/drivers/irq/inc/rtl_nvic.h
@@ -0,0 +1,110 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *               Define to prevent recursive inclusion
+ *============================================================================*/
+#ifndef RTL_NVIC_H
+#define RTL_NVIC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*============================================================================*
+ *                        Header Files
+ *============================================================================*/
+#include "utils/rtl_utils.h"
+#if defined (CONFIG_SOC_SERIES_RTL87X2G)
+#include "irq/src/device/rtl87x2g/rtl_nvic_def.h"
+#elif defined (CONFIG_SOC_SERIES_RTL87X2J)
+#include "irq/src/device/rtl87x2j/rtl_nvic_def.h"
+#elif defined (CONFIG_SOC_SERIES_RTL87X3E)
+#include "irq/src/device/rtl87x3e/rtl_nvic_def.h"
+#elif defined (CONFIG_SOC_SERIES_RTL87X3D)
+#include "irq/src/device/rtl87x3d/rtl_nvic_def.h"
+#elif defined (CONFIG_SOC_SERIES_RTL87X3J)
+#include "irq/src/device/rtl87x3j/rtl_nvic_def.h"
+#endif
+
+/** \defgroup NVIC        NVIC
+  * \brief
+  * \{
+  */
+/*============================================================================*
+ *                         Types
+ *============================================================================*/
+/** \defgroup NVIC_Exported_Types NVIC Exported Types
+  * \brief
+  * \{
+  */
+
+/**
+ * \brief       NVIC init structure definition
+ *
+ * \ingroup     NVIC_Exported_Types
+ */
+
+typedef struct
+{
+    int NVIC_IRQChannel;                    /*!< Specifies the IRQ channel.
+                                                 This parameter can be a value of \ref IRQn_Type and \ref GPIO_IRQn. */
+    uint32_t NVIC_IRQChannelPriority;       /*!< Specifies the priority for the IRQ channel.
+                                                 This parameter can be a value between 0 and x as described in the table.*/
+    FunctionalState NVIC_IRQChannelCmd;     /*!< Specifies the IRQ channel to be enabled or disabled.*/
+} NVIC_InitTypeDef;
+
+/** End of NVIC_Exported_Types
+  * \}
+  */
+
+/*============================================================================*
+ *                         Functions
+ *============================================================================*/
+/** \defgroup NVIC_Exported_Functions NVIC Exported Functions
+  * \brief
+  * \{
+  */
+
+/**
+ * \brief   Initializes the NVIC peripheral according to the specified
+ *          parameters in NVIC_InitStruct.
+ *
+ * \param[in]   NVIC_InitStruct: Pointer to a NVIC_InitTypeDef structure that contains
+ *              the configuration information for the specified NVIC peripheral.
+ *
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void nvic_config(void)
+ * {
+ *     NVIC_InitTypeDef NVIC_InitStruct;
+ *     NVIC_InitStruct.NVIC_IRQChannel = RTC_IRQn;
+ *     NVIC_InitStruct.NVIC_IRQChannelPriority = 3;
+ *     NVIC_InitStruct.NVIC_IRQChannelCmd = ENABLE;
+ *     NVIC_Init(&NVIC_InitStruct);
+ * }
+ * \endcode
+ */
+void NVIC_Init(NVIC_InitTypeDef *NVIC_InitStruct);
+
+/** End of NVIC_Exported_Functions
+  * \}
+  */
+
+/** End of NVIC
+  * \}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RTL_NVIC_H */
+
+
diff --git a/bee/drivers/irq/src/CMakeLists.txt b/bee/drivers/irq/src/CMakeLists.txt
new file mode 100644
index 00000000..dd5e359a
--- /dev/null
+++ b/bee/drivers/irq/src/CMakeLists.txt
@@ -0,0 +1,4 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+add_subdirectory(device)
diff --git a/bee/drivers/irq/src/device/CMakeLists.txt b/bee/drivers/irq/src/device/CMakeLists.txt
new file mode 100644
index 00000000..034df6a1
--- /dev/null
+++ b/bee/drivers/irq/src/device/CMakeLists.txt
@@ -0,0 +1,6 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+add_soc_series_subdir(rtl8752h)
+add_soc_series_subdir(rtl87x2g)
+add_soc_series_subdir(rtl87x2j)
diff --git a/bee/drivers/irq/src/device/rtl8752h/rtl876x_nvic.c b/bee/drivers/irq/src/device/rtl8752h/rtl876x_nvic.c
new file mode 100644
index 00000000..a8a51fe8
--- /dev/null
+++ b/bee/drivers/irq/src/device/rtl8752h/rtl876x_nvic.c
@@ -0,0 +1,82 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "rtl876x_nvic.h"
+
+/**
+  * @brief  Initializes the NVIC peripheral according to the specified
+  *         parameters in the NVIC_InitStruct.
+  * @param  NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains
+  *         the configuration information for the specified NVIC peripheral.
+  * @retval None
+  */
+void NVIC_Init(NVIC_InitTypeDef *NVIC_InitStruct)
+{
+    /* Check the parameters */
+    assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd));
+
+    if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)
+    {
+        if (NVIC_InitStruct->NVIC_IRQChannel >= Peripheral_First_IRQn)
+        {
+            PERIPHINT->EN |= BIT(NVIC_InitStruct->NVIC_IRQChannel - Peripheral_First_IRQn);
+            NVIC_InitStruct->NVIC_IRQChannel = Peripheral_IRQn;
+        }
+
+        NVIC_ClearPendingIRQ(NVIC_InitStruct->NVIC_IRQChannel);
+        NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel,
+                         NVIC_InitStruct->NVIC_IRQChannelPriority);
+        NVIC_EnableIRQ(NVIC_InitStruct->NVIC_IRQChannel);
+    }
+    else
+    {
+        if (NVIC_InitStruct->NVIC_IRQChannel >= Peripheral_First_IRQn)
+        {
+            PERIPHINT->EN &= ~BIT(NVIC_InitStruct->NVIC_IRQChannel - Peripheral_First_IRQn);
+
+            if (PERIPHINT->EN == 0)
+            {
+                /* Disable Peripheral IRQ Channel */
+                NVIC_DisableIRQ(Peripheral_IRQn);
+            }
+        }
+        else
+        {
+            /* Disable the Selected IRQ Channels */
+            NVIC_DisableIRQ(NVIC_InitStruct->NVIC_IRQChannel);
+        }
+    }
+}
+
+/**
+  * @brief  Clear Pending Interrupt. This api is valid for both primary and secondary interrupt.
+  * @param  IRQn  External interrupt number. Value cannot be negative.
+  * @retval None
+  */
+void NVIC_ClearPendingIRQ_Generic(IRQn_Type IRQn)
+{
+    if (IRQn > WDT_IRQn)
+    {
+        return;
+    }
+    else if (IRQn >= Peripheral_First_IRQn)
+    {
+        //write 1 to clear certain secondary interrupt pending bit
+        uint32_t pending_bit = BIT(IRQn - Peripheral_First_IRQn);
+        HAL_WRITE32(PERI_INT_REG_BASE, 0, pending_bit);
+
+        //clear primary interrupt pending bit
+        NVIC_ClearPendingIRQ(Peripheral_IRQn);
+    }
+    else
+    {
+        NVIC_ClearPendingIRQ(IRQn);
+    }
+
+}
+
+
diff --git a/bee/drivers/irq/src/device/rtl8752h/rtl876x_nvic.h b/bee/drivers/irq/src/device/rtl8752h/rtl876x_nvic.h
new file mode 100644
index 00000000..e9e2917d
--- /dev/null
+++ b/bee/drivers/irq/src/device/rtl8752h/rtl876x_nvic.h
@@ -0,0 +1,125 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _RTL876X_NVIC_H_
+#define _RTL876X_NVIC_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup  IO          Peripheral Drivers
+ * \defgroup    NVIC        NVIC
+ * \brief       Manage the NVIC peripheral functions.
+ * \ingroup     IO
+ */
+
+/*============================================================================*
+ *                         Includes
+ *============================================================================*/
+#include "rtl876x.h"
+
+/*============================================================================*
+ *                         Types
+ *============================================================================*/
+/**
+ * \defgroup    NVIC_Exported_Types NVIC Exported Types
+ *
+ * \ingroup     NVIC
+ * \{
+ */
+
+/**
+ * \brief       NVIC initialization structure definition
+ *
+ * \ingroup     NVIC_Exported_Types
+ */
+typedef struct
+{
+    IRQn_Type NVIC_IRQChannel;              /*!< Specify the IRQ channel to be enabled or disabled.
+                                                 This parameter can be a value of \ref IRQn_Type defined in rtl876x.h. */
+    uint32_t NVIC_IRQChannelPriority;       /*!< Specify the priority for the IRQ channel.
+                                                 This parameter can be a value between 0 and the maximum priority value. */
+    FunctionalState
+    NVIC_IRQChannelCmd;     /*!< Specify whether to enable or disable the IRQ channel. */
+} NVIC_InitTypeDef;
+
+/** End of NVIC_Exported_Types
+  * \}
+  */
+
+/*============================================================================*
+ *                         Functions
+ *============================================================================*/
+/**
+ * \defgroup    NVIC_Exported_Functions NVIC Exported Functions
+ * \{
+ * \ingroup     NVIC
+ */
+
+/**
+ * \brief     Initialize the NVIC peripheral according to the specified parameters
+ *            in the NVIC_InitStruct.
+ * \param[in] NVIC_InitStruct: Pointer to a NVIC_InitTypeDef structure that contains
+ *            the configuration information for the NVIC peripheral.
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void nvic_config(void)
+ * {
+ *     NVIC_InitTypeDef NVIC_InitStruct;
+ *     NVIC_InitStruct.NVIC_IRQChannel = RTC_IRQn;
+ *     NVIC_InitStruct.NVIC_IRQChannelPriority = 3;
+ *     NVIC_InitStruct.NVIC_IRQChannelCmd = ENABLE;
+ *     NVIC_Init(&NVIC_InitStruct);
+ * }
+ * \endcode
+ */
+void NVIC_Init(NVIC_InitTypeDef *NVIC_InitStruct);
+
+/**
+ * \brief     Clear a pending interrupt. This function is applicable to both primary and secondary interrupts.
+ * \param[in] IRQn - External interrupt number. This value cannot be negative.
+ * \return    None.
+ *
+ * <b>Example usage</b>
+ *
+ * To clear the pending bit of a secondary interrupt (e.g., Qdecode, KeyScan, WatchDog, etc.),
+ * use NVIC_ClearPendingIRQ_Generic instead of the CMSIS original API NVIC_ClearPendingIRQ.
+ *
+ * To clear the pending bit of a primary interrupt (e.g., System, UART0, GDMA0_Channel0, etc.),
+ * use the CMSIS original API NVIC_ClearPendingIRQ.
+ *
+ * \note The IRQ number for a secondary interrupt is not less than Peripheral_First_IRQn.
+ *       Refer to rtl876x.h for more details about primary and secondary interrupts.
+ *
+ * \code{.c}
+ *
+ * void nvic_clear_pending_demo(void)
+ * {
+ *     NVIC_ClearPendingIRQ_Generic(WDT_IRQn);  // WDT_IRQn is a secondary interrupt.
+ * }
+ * \endcode
+ */
+void NVIC_ClearPendingIRQ_Generic(IRQn_Type IRQn);
+
+/** End of NVIC_Exported_Functions
+  * \}
+  */
+
+/** End of NVIC
+  * \}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTL876X_NVIC_H_ */
+
diff --git a/bee/drivers/irq/src/device/rtl87x2g/rtl_nvic.c b/bee/drivers/irq/src/device/rtl87x2g/rtl_nvic.c
new file mode 100644
index 00000000..8e8c446c
--- /dev/null
+++ b/bee/drivers/irq/src/device/rtl87x2g/rtl_nvic.c
@@ -0,0 +1,65 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *                        Header Files
+ *============================================================================*/
+#include "rtl_nvic.h"
+#include "app_section.h"
+
+/*============================================================================*
+ *                           Public Functions
+ *============================================================================*/
+/**
+  * \brief  Initializes the NVIC peripheral according to the specified
+  *         parameters in the NVIC_InitStruct.
+  * \param  NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains
+  *         the configuration information for the specified NVIC peripheral.
+  * \return None
+  */
+RAM_FUNCTION
+void NVIC_Init(NVIC_InitTypeDef *NVIC_InitStruct)
+{
+    /* Check the parameters */
+    assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd));
+
+    if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)
+    {
+        if (NVIC_InitStruct->NVIC_IRQChannel >= Peripheral_First_IRQn &&
+            NVIC_InitStruct->NVIC_IRQChannel <= Peripheral_Last_IRQn)
+        {
+            SoC_VENDOR->u_00C.REG_LOW_PRI_INT_EN |= BIT(NVIC_InitStruct->NVIC_IRQChannel -
+                                                        Peripheral_First_IRQn);
+            NVIC_InitStruct->NVIC_IRQChannel = Peripheral_IRQn;
+        }
+
+        NVIC_ClearPendingIRQ(NVIC_InitStruct->NVIC_IRQChannel);
+        NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel,
+                         NVIC_InitStruct->NVIC_IRQChannelPriority);
+        NVIC_EnableIRQ(NVIC_InitStruct->NVIC_IRQChannel);
+    }
+    else
+    {
+        if (NVIC_InitStruct->NVIC_IRQChannel >= Peripheral_First_IRQn &&
+            NVIC_InitStruct->NVIC_IRQChannel <= Peripheral_Last_IRQn)
+        {
+            SoC_VENDOR->u_00C.REG_LOW_PRI_INT_EN &= ~BIT(NVIC_InitStruct->NVIC_IRQChannel -
+                                                         Peripheral_First_IRQn);
+
+            if (SoC_VENDOR->u_00C.REG_LOW_PRI_INT_EN == 0)
+            {
+                /* Disable Peripheral IRQ Channel */
+                NVIC_DisableIRQ(Peripheral_IRQn);
+            }
+        }
+        else
+        {
+            /* Disable the Selected IRQ Channels */
+            NVIC_DisableIRQ(NVIC_InitStruct->NVIC_IRQChannel);
+        }
+    }
+}
+
diff --git a/bee/drivers/irq/src/device/rtl87x2g/rtl_nvic.h b/bee/drivers/irq/src/device/rtl87x2g/rtl_nvic.h
new file mode 100644
index 00000000..9bac4739
--- /dev/null
+++ b/bee/drivers/irq/src/device/rtl87x2g/rtl_nvic.h
@@ -0,0 +1,98 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *               Define to prevent recursive inclusion
+ *============================================================================*/
+#ifndef RTL_NVIC_H
+#define RTL_NVIC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*============================================================================*
+ *                        Header Files
+ *============================================================================*/
+#include "utils/rtl_utils.h"
+#include "rtl_nvic_def.h"
+
+/** \defgroup NVIC        NVIC
+  * \brief
+  * \{
+  */
+/*============================================================================*
+ *                         Types
+ *============================================================================*/
+/** \defgroup NVIC_Exported_Types NVIC Exported Types
+  * \brief
+  * \{
+  */
+
+/**
+ * \brief       NVIC init structure definition
+ *
+ * \ingroup     NVIC_Exported_Types
+ */
+
+typedef struct
+{
+    int NVIC_IRQChannel;                    /*!< Specify the IRQ channel.
+                                                 This parameter can be a value of \ref IRQn_Type */
+
+    uint32_t NVIC_IRQChannelPriority;       /*!< Specify the priority for the IRQ channel.
+                                                 This parameter can be a value between 0 and x as described in the table.*/
+
+    FunctionalState NVIC_IRQChannelCmd;     /*!< Specify the IRQ channel to be enabled or disabled.*/
+} NVIC_InitTypeDef;
+
+/** End of NVIC_Exported_Types
+  * \}
+  */
+
+/*============================================================================*
+ *                         Functions
+ *============================================================================*/
+/** \defgroup NVIC_Exported_Functions NVIC Exported Functions
+  * \brief
+  * \{
+  */
+
+/**
+ * \brief   Initialize the NVIC peripheral according to the specified
+ *          parameters in NVIC_InitStruct.
+ *
+ * \param[in] NVIC_InitStruct  Pointer to a NVIC_InitTypeDef structure which will be initialized.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void nvic_config(void)
+ * {
+ *     NVIC_InitTypeDef NVIC_InitStruct;
+ *     NVIC_InitStruct.NVIC_IRQChannel = RTC_IRQn;
+ *     NVIC_InitStruct.NVIC_IRQChannelPriority = 3;
+ *     NVIC_InitStruct.NVIC_IRQChannelCmd = ENABLE;
+ *     NVIC_Init(&NVIC_InitStruct);
+ * }
+ * \endcode
+ */
+void NVIC_Init(NVIC_InitTypeDef *NVIC_InitStruct);
+
+/** End of NVIC_Exported_Functions
+  * \}
+  */
+
+/** End of NVIC
+  * \}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RTL_NVIC_H */
+
diff --git a/bee/drivers/irq/src/device/rtl87x2g/rtl_nvic_def.h b/bee/drivers/irq/src/device/rtl87x2g/rtl_nvic_def.h
new file mode 100644
index 00000000..8ce555c0
--- /dev/null
+++ b/bee/drivers/irq/src/device/rtl87x2g/rtl_nvic_def.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef RTL_NVIC_DEF_H
+#define RTL_NVIC_DEF_H
+
+#include "utils/rtl_utils.h"
+#include "address_map.h"
+#include "platform_reg.h"
+#include "vector_table.h"
+
+#ifdef  __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/*============================================================================*
+ *                         NVIC Defines
+ *============================================================================*/
+
+/*============================================================================*
+ *                         NVIC Private Defines
+ *============================================================================*/
+
+/*============================================================================*
+ *                         NVIC Constants
+ *============================================================================*/
+
+#ifdef  __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* RTL_NVIC_DEF_H */
diff --git a/bee/drivers/irq/src/device/rtl87x2j/rtl_nvic.c b/bee/drivers/irq/src/device/rtl87x2j/rtl_nvic.c
new file mode 100644
index 00000000..93d733d8
--- /dev/null
+++ b/bee/drivers/irq/src/device/rtl87x2j/rtl_nvic.c
@@ -0,0 +1,75 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *                           Header Files
+ *============================================================================*/
+#include "rtl_nvic.h"
+#include "section.h"
+
+/*============================================================================*
+ *                           Private Defines
+ *============================================================================*/
+#define PLATFORM_REG_LPIE *((volatile uint32_t *)(SOC_VENDOR_REG_BASE + PLATFORM_REG_LOW_PRI_INT_MODE))
+
+/*============================================================================*
+ *                           Public Functions
+ *============================================================================*/
+/**
+  * \brief  Initializes the NVIC peripheral according to the specified
+  *         parameters in the NVIC_InitStruct.
+  * \param  NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains
+  *         the configuration information for the specified NVIC peripheral.
+  * \return None
+  */
+RAM_TEXT_SECTION
+void NVIC_Init(NVIC_InitTypeDef *NVIC_InitStruct)
+{
+    /* Check the parameters */
+    assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd));
+
+    if ((NVIC_InitStruct->NVIC_IRQChannel >= PeriphGPIO_First_IRQn &&
+         NVIC_InitStruct->NVIC_IRQChannel <= PeriphGPIO_Last_IRQn) ||
+        (NVIC_InitStruct->NVIC_IRQChannel >= PeriphTIMER_First_IRQn &&
+         NVIC_InitStruct->NVIC_IRQChannel <= PeriphTIMER_Last_IRQn))
+    {
+        NVIC_InitStruct->NVIC_IRQChannel = GET_FIRST_IRQn(NVIC_InitStruct->NVIC_IRQChannel);
+    }
+
+    if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)
+    {
+        if (NVIC_InitStruct->NVIC_IRQChannel >= Peripheral_First_IRQn &&
+            NVIC_InitStruct->NVIC_IRQChannel <= Peripheral_Last_IRQn)
+        {
+            PLATFORM_REG_LPIE |= BIT(NVIC_InitStruct->NVIC_IRQChannel - Peripheral_First_IRQn);
+            NVIC_InitStruct->NVIC_IRQChannel = PERIPHERAL_ISR_IRQn;
+        }
+
+        NVIC_ClearPendingIRQ(NVIC_InitStruct->NVIC_IRQChannel);
+        NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, NVIC_InitStruct->NVIC_IRQChannelPriority);
+        NVIC_EnableIRQ(NVIC_InitStruct->NVIC_IRQChannel);
+    }
+    else
+    {
+        if (NVIC_InitStruct->NVIC_IRQChannel >= Peripheral_First_IRQn &&
+            NVIC_InitStruct->NVIC_IRQChannel <= Peripheral_Last_IRQn)
+        {
+            PLATFORM_REG_LPIE &= ~BIT(NVIC_InitStruct->NVIC_IRQChannel - Peripheral_First_IRQn);
+            if (PLATFORM_REG_LPIE == 0)
+            {
+                /* Disable Peripheral IRQ Channel */
+                NVIC_DisableIRQ(PERIPHERAL_ISR_IRQn);
+            }
+        }
+        else
+        {
+            /* Disable the Selected IRQ Channels */
+            NVIC_DisableIRQ(NVIC_InitStruct->NVIC_IRQChannel);
+        }
+    }
+}
+
+
diff --git a/bee/drivers/irq/src/device/rtl87x2j/rtl_nvic_def.h b/bee/drivers/irq/src/device/rtl87x2j/rtl_nvic_def.h
new file mode 100644
index 00000000..759922f0
--- /dev/null
+++ b/bee/drivers/irq/src/device/rtl87x2j/rtl_nvic_def.h
@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef RTL_NVIC_DEF_H
+#define RTL_NVIC_DEF_H
+
+#include "utils/rtl_utils.h"
+#include "address_map.h"
+#include "platform_reg.h"
+#include "vector_table.h"
+
+#ifdef  __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/*============================================================================*
+ *                         NVIC Defines
+ *============================================================================*/
+
+/*============================================================================*
+ *                         NVIC Private Defines
+ *============================================================================*/
+#define Peripheral_First_IRQn    PERIPHERAL_ISR_IRQn //TODO BERT
+#define Peripheral_Last_IRQn     PERIPHERAL_ISR_IRQn //TODO BERT
+
+#define PeriphGPIO_First_IRQn    SUB_IRQ_DEF(GPIOA0_7_IRQn, 0)
+#define PeriphGPIO_Last_IRQn     SUB_IRQ_DEF(GPIOA48_55_IRQn, 55)
+
+#define PeriphTIMER_First_IRQn   SUB_IRQ_DEF(TIMER0_CH0_CH1_IRQn, 0)
+#define PeriphTIMER_Last_IRQn    SUB_IRQ_DEF(TIMER0_CH0_CH1_IRQn, 1)
+
+/*============================================================================*
+ *                         NVIC Constants
+ *============================================================================*/
+
+#ifdef  __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* RTL_NVIC_DEF_H */
diff --git a/bee/drivers/keyscan/CMakeLists.txt b/bee/drivers/keyscan/CMakeLists.txt
new file mode 100644
index 00000000..9ec999ac
--- /dev/null
+++ b/bee/drivers/keyscan/CMakeLists.txt
@@ -0,0 +1,8 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+if(CONFIG_REALTEK_BEE_COMMON_DRIVER)
+    zephyr_include_directories(inc)
+endif()
+
+add_subdirectory_ifdef(CONFIG_REALTEK_BEE_KEYSCAN src)
diff --git a/bee/drivers/keyscan/Kconfig b/bee/drivers/keyscan/Kconfig
new file mode 100644
index 00000000..2a7c6596
--- /dev/null
+++ b/bee/drivers/keyscan/Kconfig
@@ -0,0 +1,8 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config REALTEK_BEE_KEYSCAN
+	bool "Realtek Bee KEYSCAN driver"
+	default n
+	help
+	  This option enables the KEYSCAN driver for Realtek Bee.
diff --git a/bee/drivers/keyscan/inc/rtl_keyscan.h b/bee/drivers/keyscan/inc/rtl_keyscan.h
new file mode 100644
index 00000000..2adf1fac
--- /dev/null
+++ b/bee/drivers/keyscan/inc/rtl_keyscan.h
@@ -0,0 +1,733 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *               Define to prevent recursive inclusion
+ *============================================================================*/
+#ifndef RTL_KEYSCAN_H
+#define RTL_KEYSCAN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*============================================================================*
+ *                        Header Files
+ *============================================================================*/
+#include "utils/rtl_utils.h"
+#if defined (CONFIG_SOC_SERIES_RTL87X2G)
+#include "keyscan/src/device/rtl87x2g/rtl_keyscan_def.h"
+#elif defined (CONFIG_SOC_SERIES_RTL87X3E)
+#include "keyscan/src/device/rtl87x3e/rtl_keyscan_def.h"
+#elif defined (CONFIG_SOC_SERIES_RTL87X3D)
+#include "keyscan/src/device/rtl87x3d/rtl_keyscan_def.h"
+#elif defined (CONFIG_SOC_SERIES_RTL87X2J)
+#include "keyscan/src/device/rtl87x2j/rtl_keyscan_def.h"
+#elif defined (CONFIG_SOC_SERIES_RTL87X3J)
+#include "keyscan/src/device/rtl87x3j/rtl_keyscan_def.h"
+#endif
+
+/** \defgroup KEYSCAN     KEYSCAN
+  * \brief
+  * \{
+  */
+
+/*============================================================================*
+ *                         Constants
+ *============================================================================*/
+/** \defgroup KEYSCAN_Exported_Constants KEYSCAN Exported Constants
+  * \brief
+  * \{
+  */
+
+/**
+ * \defgroup    KEYSCAN_FIFO_Depth KEYSCAN FIFO Depth
+ * \{
+ * \ingroup     KEYSCAN_Exported_Constants
+ */
+#define KEYSCAN_FIFO_DEPTH              26
+
+/** End of KEYSCAN_FIFO_Depth
+  * \}
+  */
+
+/**
+ * \defgroup    KEYSCAN_Row_Number KEYSCAN Row Number
+ * \{
+ * \ingroup     KEYSCAN_Exported_Constants
+ */
+#define IS_KEYSCAN_ROW_NUM(ROW) ((ROW) <= 12)
+
+/** End of KEYSCAN_Row_Number
+  * \}
+  */
+
+/**
+ * \defgroup    KEYSCAN_Column_Number KEYSCAN Column Number
+ * \{
+ * \ingroup     KEYSCAN_Exported_Constants
+ */
+#define IS_KEYSCAN_COL_NUM(COL) ((COL) <= 20)
+
+/** End of KEYSCAN_Column_Number
+  * \}
+  */
+
+/**
+ * \defgroup    KEYSCAN_Scan_mode KEYSCAN Scan mode
+ * \{
+ * \ingroup     KEYSCAN_Exported_Constants
+ */
+typedef enum
+{
+    KEYSCAN_MANUAL_SCAN_MODE = 0x00,
+    KEYSCAN_AUTO_SCAN_MODE = 0x01,
+} KEYSCANScanMode_TypeDef;
+
+#define IS_KEYSCAN_SCAN_MODE(MODE)  (((MODE) == KEYSCAN_MANUAL_SCAN_MODE) || ((MODE) == KEYSCAN_AUTO_SCAN_MODE))
+
+/** End of KEYSCAN_Scan_mode
+  * \}
+  */
+
+/**
+ * \defgroup    KEYSCAN_Detect_Mode KEYSCAN Detect Mode
+ * \{
+ * \ingroup     KEYSCAN_Exported_Constants
+ */
+typedef enum
+{
+    KEYSCAN_DETECT_MODE_EDGE = 0x00,
+    KEYSCAN_DETECT_MODE_LEVEL = 0x01,
+} KEYSCANDetectMode_TypeDef;
+
+#define IS_KEYSCAN_DETECT_MODE(MODE)    (((MODE) == KEYSCAN_DETECT_MODE_EDGE) || ((MODE) == KEYSCAN_DETECT_MODE_LEVEL))
+
+/** End of KEYSCAN_Detect_Mode
+  * \}
+  */
+
+/**
+ * \defgroup    KEYSCAN_FIFO_Overflow_Control KEYSCAN FIFO Overflow Control
+ * \{
+ * \ingroup     KEYSCAN_Exported_Constants
+ */
+typedef enum
+{
+    KEYSCAN_FIFO_OVFL_CTRL_DIS_NEWEST = 0x00,
+    KEYSCAN_FIFO_OVFL_CTRL_DIS_OLDEST = 0x01,
+} KEYSCANFIFOvflCtl_TypeDef;
+
+#define IS_KEYSCAN_FIFO_OVFL_CTRL(CTRL)  (((CTRL) == KEYSCAN_FIFO_OVFL_CTRL_DIS_NEWEST) || ((CTRL) == KEYSCAN_FIFO_OVFL_CTRL_DIS_OLDEST))
+
+/** End of KEYSCAN_FIFO_Overflow_Control
+  * \}
+  */
+
+/**
+ * \defgroup    KEYSCAN_Manual_Sel KEYSCAN Manual Sel
+ * \{
+ * \ingroup     KEYSCAN_Exported_Constants
+ */
+typedef enum
+{
+    KEYSCAN_MANUAL_SEL_BIT = 0x00,
+    KEYSCAN_MANUAL_SEL_KEY = 0x01,
+} KEYSCANManualSel_TypeDef;
+
+#define IS_KEYSCAN_MANUAL_SELECT(SEL)  (((SEL) == KEYSCAN_MANUAL_SEL_BIT) || ((SEL) == KEYSCAN_MANUAL_SEL_KEY))
+
+/** End of KEYSCAN_Manual_Sel
+  * \}
+  */
+
+#if (KEYSCAN_SUPPORT_RAP_FUNCTION == 1)
+/**
+ * \defgroup    KEYSCAN_Action KEYSCAN Action
+ * \{
+ * \ingroup     KEYSCAN_Exported_Constants
+ */
+typedef enum
+{
+    KEYSCAN_ACTION_MANUAL = 0,
+} KEYSCANAction_TypeDef;
+
+/** End of KEYSCAN_Action
+  * \}
+  */
+#endif
+
+/**
+ * \defgroup    KEYSCAN_Key_Limit KEYSCAN Key Limit
+ * \{
+ * \ingroup     KEYSCAN_Exported_Constants
+ */
+#define IS_KEYSCAN_KEY_LIMIT(DATA_NUM) ((DATA_NUM) <= KEYSCAN_FIFO_DEPTH) //0 means no limit
+
+/** End of KEYSCAN_Key_Limit
+  * \}
+  */
+
+/**
+ * \defgroup    KEYSCAN_Interrupt KEYSCAN Interrupt
+ * \{
+ * \ingroup     KEYSCAN_Exported_Constants
+ */
+#define KEYSCAN_INT_THRESHOLD                    BIT4
+#define KEYSCAN_INT_OVER_READ                    BIT3
+#define KEYSCAN_INT_SCAN_END                     BIT2
+#define KEYSCAN_INT_FIFO_NOT_EMPTY               BIT1
+#define KEYSCAN_INT_ALL_RELEASE                  BIT0
+#define IS_KEYSCAN_CONFIG_INT(INT) ((((INT) & (uint32_t)0xFFF8) == 0x00) && ((INT) != 0x00))
+
+/** End of KEYSCAN_Interrupt
+  * \}
+  */
+
+/**
+ * \defgroup    KEYSCAN_Flag KEYSCAN Flag
+ * \{
+ * \ingroup     KEYSCAN_Exported_Constants
+ */
+#define KEYSCAN_FLAG_FIFOLIMIT                       BIT20
+#define KEYSCAN_INT_FLAG_THRESHOLD                   BIT19
+#define KEYSCAN_INT_FLAG_OVER_READ                   BIT18
+#define KEYSCAN_INT_FLAG_SCAN_END                    BIT17
+#define KEYSCAN_INT_FLAG_FIFO_NOT_EMPTY              BIT16
+#define KEYSCAN_INT_FLAG_ALL_RELEASE                 BIT15
+#define KEYSCAN_FLAG_DATAFILTER                      BIT3
+#define KEYSCAN_FLAG_OVR                             BIT2
+#define KEYSCAN_FLAG_FULL                            BIT1
+#define KEYSCAN_FLAG_EMPTY                           BIT0
+#define IS_KEYSCAN_FLAG(FLAG)       ((((FLAG) & (uint32_t)0x01FF) == 0x00) && ((FLAG) != (uint32_t)0x00))
+#define IS_KEYSCAN_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0x00C0) == 0x00) && ((FLAG) != (uint32_t)0x00))
+
+/** End of KEYSCAN_Flag
+  * \}
+  */
+
+/** End of KEYSCAN_Exported_Constants
+  * \}
+  */
+
+/*============================================================================*
+ *                         Types
+ *============================================================================*/
+/** \defgroup KEYSCAN_Exported_Types KEYSCAN Exported Types
+  * \brief
+  * \{
+  */
+
+/**
+ * \brief       KEYSCAN initialize parameters
+ *
+ * \ingroup     KEYSCAN_Exported_Types
+ */
+typedef struct
+{
+    uint16_t KEYSCAN_RowSize;                 /*!< Specifies KEYSCAN Row Size.
+                                                   This parameter can be a value <=12. */
+
+    uint16_t KEYSCAN_ColSize;                 /*!< Specifies KEYSCAN Column Size.
+                                                   This parameter can be a value <=20. */
+
+    uint16_t KEYSCAN_ClockDiv;                /*!< Specifies KEYSCAN clock divider.
+                                                   scan clock = system clock/(SCAN_DIV+1). */
+
+    uint8_t KEYSCAN_ClockDelayDiv;            /*!< Specifies KEYSCAN clock delay divider.
+                                                   delay clock = scan clock/(DELAY_DIV+1). */
+
+    FunctionalState KEYSCAN_DebounceEn;       /*!< Enable or disable debounce. */
+
+    FunctionalState KEYSCAN_ScanTimerEn;      /*!< Enable or disable scan timer. */
+
+    FunctionalState KEYSCAN_DetectTimerEn;    /*!< Enable or disable detect timer. */
+
+    uint16_t KEYSCAN_DebounceCnt;             /*!< Specifies KEYSCAN Debounce time. */
+
+    uint16_t KEYSCAN_ScanInterval;            /*!< Specifies KEYSCAN release time. */
+
+    uint16_t KEYSCAN_ReleaseCnt;              /*!< Specifies KEYSCAN release time. */
+
+    KEYSCANScanMode_TypeDef KEYSCAN_ScanMode; /*!< Specifies KEYSCAN mode. */
+
+    KEYSCANDetectMode_TypeDef KEYSCAN_DetectMode; /*!< Specifies Key Detect mode. */
+
+    uint16_t KEYSCAN_FIFOTriggerLevel;        /*!< Specifies KEYSCAN fifo threshold
+                                                   to trigger interrupt KEYSCAN_INT_THRESHOLD. */
+
+    KEYSCANFIFOvflCtl_TypeDef KEYSCAN_FIFOOvflCtrl; /*!< Specifies KEYSCAN fifo over flow control. */
+
+    uint8_t KEYSCAN_KeyLimit;                 /*!< Specifies max scan data allowable in each scan. */
+
+    KEYSCANManualSel_TypeDef KEYSCAN_ManualSel; /*!< Specifies trigger mode in manual mode. */
+
+    uint8_t KEYSCAN_PreGuardCnt;              /*!< Specifies KEYSCAN preguard time. */
+
+    uint8_t KEYSCAN_PostGuardCnt;             /*!< Specifies KEYSCAN postguard time. */
+
+#if KEYSCAN_SUPPORT_ROW_LEVEL_CONFIGURE
+    FunctionalState KEYSCAN_RowPullHighEn;
+#endif
+
+#if KEYSCAN_SUPPORT_COLUNM_LEVEL_CONFIGURE
+    FunctionalState KEYSCAN_ColunmOutputHighEn;
+#endif
+
+} KEYSCAN_InitTypeDef;
+
+/** End of KEYSCAN_Exported_Types
+  * \}
+  */
+
+/*============================================================================*
+ *                         Functions
+ *============================================================================*/
+/** \defgroup KEYSCAN_Exported_Functions KEYSCAN Exported Functions
+  * \brief
+  * \{
+  */
+
+/**
+ * \brief  Deinitializes the KEYSCAN peripheral registers to their default reset values(turn off KEYSCAN clock).
+ *
+ * \param[in]  KEYSCANx: Selected KEYSCAN peripheral.
+ *
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_keyscan_init(void)
+ * {
+ *     KEYSCAN_DeInit(KEYSCAN);
+ * }
+ * \endcode
+ */
+void KEYSCAN_DeInit(KEYSCAN_TypeDef *KEYSCANx);
+
+/**
+ * \brief   Initializes the KEYSCAN peripheral according to the specified
+ *          parameters in the KEYSCAN_InitStruct
+ *
+ * \param[in]  KEYSCANx: Selected KEYSCAN peripheral.
+ * \param[in]  KEYSCAN_InitStruct: Pointer to a KEYSCAN_InitTypeDef structure that
+ *             contains the configuration information for the specified KEYSCAN peripheral
+ *
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_keyscan_init(void)
+ * {
+ *     RCC_ClockCmd(KEYSCAN_CLOCK, ENABLE);
+
+ *     KEYSCAN_InitTypeDef KEYSCAN_InitStruct;
+ *     KEYSCAN_StructInit(&KEYSCAN_InitStruct);
+
+ *     KEYSCAN_InitStruct.rowSize  = KEYBOARD_ROW_SIZE;
+ *     KEYSCAN_InitStruct.colSize  = KEYBOARD_COLUMN_SIZE;
+ *     KEYSCAN_InitStruct.scanmode     = KEYSCAN_Manual_Scan_Mode;
+ *     KEYSCAN_InitStruct.debounceEn   = KEYSCAN_Debounce_Enable;
+
+ *     KEYSCAN_Init(KEYSCAN, &KEYSCAN_InitStruct);
+
+ *     KEYSCAN_INTConfig(KEYSCAN, KEYSCAN_INT_SCAN_END, ENABLE);
+ *     KEYSCAN_ClearINTPendingBit(KEYSCAN, KEYSCAN_INT_SCAN_END);
+ *     KEYSCAN_INTMask(KEYSCAN, KEYSCAN_INT_SCAN_END, DISABLE);  // Unmask keyscan interrupt
+ *     KEYSCAN_Cmd(KEYSCAN, ENABLE);
+ * }
+ * \endcode
+ */
+void KEYSCAN_Init(KEYSCAN_TypeDef *KEYSCANx, KEYSCAN_InitTypeDef *KEYSCAN_InitStruct);
+
+/**
+ * \brief  Fills each KEYSCAN_InitStruct member with its default value.
+ *
+ * \param[in]  KEYSCAN_InitStruct: Pointer to a KEYSCAN_InitTypeDef structure which will be initialized.
+ *
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_keyscan_init(void)
+ * {
+ *     RCC_ClockCmd(KEYSCAN_CLOCK, ENABLE);
+
+ *     KEYSCAN_InitTypeDef KEYSCAN_InitStruct;
+ *     KEYSCAN_StructInit(&KEYSCAN_InitStruct);
+
+ *     KEYSCAN_InitStruct.rowSize  = KEYBOARD_ROW_SIZE;
+ *     KEYSCAN_InitStruct.colSize  = KEYBOARD_COLUMN_SIZE;
+ *     KEYSCAN_InitStruct.scanmode     = KEYSCAN_Manual_Scan_Mode;
+ *     KEYSCAN_InitStruct.debounceEn   = KEYSCAN_Debounce_Enable;
+
+ *     KEYSCAN_Init(KEYSCAN, &KEYSCAN_InitStruct);
+
+ *     KEYSCAN_INTConfig(KEYSCAN, KEYSCAN_INT_SCAN_END, ENABLE);
+ *     KEYSCAN_ClearINTPendingBit(KEYSCAN, KEYSCAN_INT_SCAN_END);
+ *     KEYSCAN_INTMask(KEYSCAN, KEYSCAN_INT_SCAN_END, DISABLE);  // Unmask keyscan interrupt
+ *     KEYSCAN_Cmd(KEYSCAN, ENABLE);
+ * }
+ * \endcode
+ */
+void KEYSCAN_StructInit(KEYSCAN_InitTypeDef *KEYSCAN_InitStruct);
+
+/**
+ * \brief  Enables or disables the specified KEYSCAN interrupt.
+ *
+ * \param[in] KEYSCANx: Selected KEYSCAN peripheral.
+ * \param[in] KEYSCAN_INT: Specifies the KEYSCAN interrupts sources to be enabled or disabled.
+ *            This parameter can be any combination of the following values:
+ *            \arg KEYSCAN_INT_THRESHOLD: Kescan FIFO data over threshold interrupt.
+ *            \arg KEYSCAN_INT_OVER_READ: KEYSCAN over read interrupt.
+ *            \arg KEYSCAN_INT_SCAN_END: KEYSCAN scan end interrupt.
+ *            \arg KEYSCAN_INT_FIFO_NOT_EMPTY: KEYSCAN FIFO not empty interrupt.
+ *            \arg KEYSCAN_INT_ALL_RELEASE: KEYSCAN all key release interrupt.
+ * \param[in] NewState: New state of the specified KEYSCAN interrupts.
+ *            This parameter can be: ENABLE or DISABLE.
+ *
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void keyscan_demo(void)
+ * {
+ *     KEYSCAN_INTMask(KEYSCAN, KEYSCAN_INT_SCAN_END, ENABLE);
+ *     KEYSCAN_INTConfig(KEYSCAN, KEYSCAN_INT_SCAN_END, ENABLE);
+ *     KEYSCAN_INTMask(KEYSCAN, KEYSCAN_INT_SCAN_END, DISABLE);
+ * }
+ * \endcode
+ */
+void KEYSCAN_INTConfig(KEYSCAN_TypeDef *KEYSCANx, uint32_t KEYSCAN_INT,
+                       FunctionalState NewState);
+
+/**
+ * \brief  Mask the specified KEYSCAN interrupt.
+ *
+ * \param[in] KEYSCANx: Selected KEYSCAN peripheral.
+ * \param[in] KEYSCAN_INT: Specifies the KEYSCAN interrupts sources to be enabled or disabled.
+ *            This parameter can be any combination of the following values:
+ *            \arg KEYSCAN_INT_THRESHOLD: Kescan FIFO data over threshold interrupt.
+ *            \arg KEYSCAN_INT_OVER_READ: KEYSCAN over read interrupt.
+ *            \arg KEYSCAN_INT_SCAN_END: KEYSCAN scan end interrupt.
+ *            \arg KEYSCAN_INT_FIFO_NOT_EMPTY: KEYSCAN FIFO not empty interrupt.
+ *            \arg KEYSCAN_INT_ALL_RELEASE: KEYSCAN all key release interrupt.
+ * \param[in] NewState: New state of the specified KEYSCAN interrupts mask.
+ *            This parameter can be: ENABLE or DISABLE.
+ *
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void keyscan_demo(void)
+ * {
+ *     KEYSCAN_INTMask(KEYSCAN, KEYSCAN_INT_SCAN_END, ENABLE);
+ * }
+ * \endcode
+ */
+void KEYSCAN_INTMask(KEYSCAN_TypeDef *KEYSCANx, uint32_t KEYSCAN_INT,
+                     FunctionalState NewState);
+
+/**
+ * \brief  Read data from KEYSCAN FIFO.
+ *
+ * \param[in]  KEYSCANx: Selected KEYSCAN peripheral.
+ * \param[out] outBuf: Buffer to save data read from KEYSCAN FIFO.
+ * \param[in]  count: Data length to be read.
+ *
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void keyscan_demo(void)
+ * {
+ *     uint16_t data[3] = {0};
+ *     KEYSCAN_Read(KEYSCAN, data, 3);
+ * }
+ * \endcode
+ */
+void KEYSCAN_Read(KEYSCAN_TypeDef *KEYSCANx, uint16_t *outBuf, uint16_t count);
+
+/**
+ * \brief   Enable or disable the KEYSCAN peripheral.
+ *
+ * \param[in] KEYSCANx: Selected KEYSCAN peripheral.
+ * \param[in] NewState: New state of the KEYSCAN peripheral.
+ *            This parameter can be: ENABLE or DISABLE.
+ *
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void keyscan_demo(void)
+ * {
+ *     KEYSCAN_Cmd(KEYSCAN, ENABLE);
+ * }
+ * \endcode
+ */
+void KEYSCAN_Cmd(KEYSCAN_TypeDef *KEYSCANx, FunctionalState NewState);
+
+/**
+ * \brief   Set filter data.
+ *
+ * \param[in] KEYSCANx: Selected KEYSCAN peripheral.
+ * \param[in] data: Config the data to be filtered.
+ *            This parameter should not be more than 9 bits.
+ * \param[in] NewState: New state of the KEYSCAN peripheral.
+ *            This parameter can be: ENABLE or DISABLE.
+ *
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void keyscan_demo(void)
+ * {
+ *     KEYSCAN_FilterDataConfig(KEYSCAN, 0x01, ENABLE);
+ *
+ * }
+ * \endcode
+ */
+void KEYSCAN_FilterDataConfig(KEYSCAN_TypeDef *KEYSCANx, uint16_t data,
+                              FunctionalState NewState);
+
+/**
+ * \brief   KEYSCAN debounce time config.
+ *
+ * \param[in] KEYSCANx: selected KEYSCAN peripheral.
+ * \param[in] time: KEYSCAN hardware debounce time.
+ * \param[in] NewState: New state of the KEYSCAN debounce function.
+ *            This parameter can be: ENABLE or DISABLE.
+ *
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void keyscan_demo(void)
+ * {
+ *     KEYSCAN_debounceConfig(KEYSCAN, 10, ENABLE);
+ *
+ * }
+ * \endcode
+ */
+void KEYSCAN_DebounceConfig(KEYSCAN_TypeDef *KEYSCANx, uint16_t time,
+                            FunctionalState NewState);
+
+/**
+ * \brief   Get KEYSCAN FIFO data num.
+ *
+ * \param[in]  KEYSCANx: Selected KEYSCAN peripheral.
+ *
+ * \return  Data length in FIFO.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void keyscan_demo(void)
+ * {
+ *     uint16_t data_len = KEYSCAN_GetFIFODataNum(KEYSCAN);
+ * }
+ * \endcode
+ */
+uint16_t KEYSCAN_GetFIFODataNum(KEYSCAN_TypeDef *KEYSCANx);
+
+/**
+ * \brief  Clear the KEYSCAN interrupt pending bit.
+ *
+ * \param[in] KEYSCANx: selected KEYSCAN peripheral.
+ * \param[in] KEYSCAN_INT: specifies the interrupt pending bit to clear.
+ *            This parameter can be any combination of the following values:
+ *            \arg KEYSCAN_INT_THRESHOLD: Kescan FIFO data over threshold interrupt.
+ *            \arg KEYSCAN_INT_OVER_READ: KEYSCAN over read interrupt.
+ *            \arg KEYSCAN_INT_SCAN_END: KEYSCAN scan end interrupt.
+ *            \arg KEYSCAN_INT_FIFO_NOT_EMPTY: KEYSCAN FIFO not empty interrupt.
+ *            \arg KEYSCAN_INT_ALL_RELEASE: KEYSCAN all key release interrupt.
+ *
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void keyscan_demo(void)
+ * {
+ *     KEYSCAN_ClearINTPendingBit(KEYSCAN, KEYSCAN_INT_SCAN_END);
+ * }
+ * \endcode
+ */
+void KEYSCAN_ClearINTPendingBit(KEYSCAN_TypeDef *KEYSCANx, uint32_t KEYSCAN_INT);
+
+/**
+ * \brief   Clear the specified KEYSCAN flag.
+ *
+ * \param[in] KEYSCANx: Selected KEYSCAN peripheral.
+ * \param[in] KEYSCAN_FLAG: Specifies the flag to clear.
+ *            This parameter can be one of the following values:
+ *            \arg KEYSCAN_FLAG_FIFOLIMIT
+ *            \arg KEYSCAN_FLAG_DATAFILTER
+ *            \arg KEYSCAN_FLAG_OVR
+ *
+ * \return  None.
+ * \note    KEYSCAN_FLAG_FULL and KEYSCAN_FLAG_EMPTY can't be cleared manually.
+ *          They are cleared by hardware automatically.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void keyscan_demo(void)
+ * {
+ *     KEYSCAN_ClearFlags(KEYSCAN, KEYSCAN_FLAG_FIFOLIMIT);
+ * }
+ * \endcode
+ */
+void KEYSCAN_ClearFlags(KEYSCAN_TypeDef *KEYSCANx, uint32_t KEYSCAN_FLAG);
+
+/**
+ * \brief   Check whether the specified KEYSCAN flag is set.
+ *
+ * \param[in] KEYSCANx: Selected KEYSCAN peripheral.
+ * \param[in] KEYSCAN_FLAG: Specifies the flag to check.
+ *            This parameter can be one of the following values:
+ *            \arg KEYSCAN_FLAG_FIFOLIMIT:
+ *            \arg KEYSCAN_FLAG_THRESHOLD:
+ *            \arg KEYSCAN_FLAG_OVER_READ:
+ *            \arg KEYSCAN_FLAG_SCAN_END:
+ *            \arg KEYSCAN_FLAG_FIFO_NOT_EMPTY:
+ *            \arg KEYSCAN_FLAG_ALL_RELEASE:
+ *            \arg KEYSCAN_FLAG_DATAFILTER:
+ *            \arg KEYSCAN_FLAG_OVR:
+ *            \arg KEYSCAN_FLAG_FULL:
+ *            \arg KEYSCAN_FLAG_EMPTY:
+ *
+ * \return  The new state of KEYSCAN_FLAG (SET or RESET).
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void keyscan_demo(void)
+ * {
+ *     FlagStatus flag_status = KEYSCAN_GetFlagState(KEYSCAN, KEYSCAN_FLAG_OVR);
+ *
+ * }
+ * \endcode
+ */
+FlagStatus KEYSCAN_GetFlagState(KEYSCAN_TypeDef *KEYSCANx, uint32_t KEYSCAN_FLAG);
+
+/**
+ * \brief  Read FIFO data.
+ *
+ * \param[in] KEYSCANx: Selected KEYSCAN peripheral.
+ *
+ * \return KEYSCAN FIFO data.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void keyscan_demo(void)
+ * {
+ *     uint16_t data = KEYSCAN_ReadFIFOData(KEYSCAN);
+ * }
+ * \endcode
+ */
+uint16_t KEYSCAN_ReadFIFOData(KEYSCAN_TypeDef *KEYSCANx);
+
+/**
+ * \brief  Set manual scan trigger mode. This function is only effective when keyscan is manual scan mode.
+ *
+ * \param[in] KEYSCANx: Selected KEYSCAN peripheral.
+ * \param[in] manual_sel: Specifies the KEYSCAN manual trigger mode.
+ *                        This parameter can be one of the following values:
+ *                        \arg KEYSCAN_MANUAL_SEL_BIT: scan trigger by register (Call API KEYSCAN_Cmd).
+ *                        \arg KEYSCAN_MANUAL_SEL_KEY: scan trigger by key.
+ *
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void keyscan_demo(void)
+ * {
+ *     KEYSCAN_SetManualSelect(KEYSCAN, KEYSCAN_MANUAL_SEL_BIT);
+ * }
+ * \endcode
+ */
+void KEYSCAN_SetManualSelect(KEYSCAN_TypeDef *KEYSCANx, KEYSCANManualSel_TypeDef manual_sel);
+
+/**
+ * \brief  Set preguard time. Preguard time = preguard_cnt * scan clock.
+ *
+ * \param[in] KEYSCANx: Selected KEYSCAN peripheral.
+ * \param[in] preguard_cnt: Specifies the preguard count. This parameter can be configured from 0 to 7.
+ *
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void keyscan_demo(void)
+ * {
+ *     KEYSCAN_SetPreGuardTime(KEYSCAN, 3);
+ * }
+ * \endcode
+ */
+void KEYSCAN_SetPreGuardTime(KEYSCAN_TypeDef *KEYSCANx, uint8_t preguard_cnt);
+
+/**
+ * \brief  Set postguard time. Postguard time = postguard_cnt * scan clock.
+ *
+ * \param[in] KEYSCANx: Selected KEYSCAN peripheral.
+ * \param[in] postguard_cnt: Specifies the postguard count. This parameter can be configured from 0 to 7.
+ *
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void keyscan_demo(void)
+ * {
+ *     KEYSCAN_SetPostGuardTime(KEYSCAN, 3);
+ * }
+ * \endcode
+ */
+void KEYSCAN_SetPostGuardTime(KEYSCAN_TypeDef *KEYSCANx, uint8_t postguard_cnt);
+
+#if (KEYSCAN_SUPPORT_RAP_FUNCTION == 1)
+
+void KEYSCAN_RAPModeCmd(KEYSCAN_TypeDef *KEYSCANx, FunctionalState NewState);
+
+void KEYSCAN_ActionTrigger(KEYSCAN_TypeDef *KEYSCANx, uint32_t Action);
+
+#endif
+
+#if (KEYSCAN_SUPPORT_AUTO_CLOCK == 1)
+
+void KEYSCAN_SetClockAutoMode(KEYSCAN_TypeDef *KEYSCANx, uint32_t AutoMode);
+
+#endif
+
+/** End of KEYSCAN_Exported_Functions
+  * \}
+  */
+
+/** End of KEYSCAN
+  * \}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RTL_KEYSCAN_H */
+
+
+
diff --git a/bee/drivers/keyscan/src/CMakeLists.txt b/bee/drivers/keyscan/src/CMakeLists.txt
new file mode 100644
index 00000000..dd5e359a
--- /dev/null
+++ b/bee/drivers/keyscan/src/CMakeLists.txt
@@ -0,0 +1,4 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+add_subdirectory(device)
diff --git a/bee/drivers/keyscan/src/device/CMakeLists.txt b/bee/drivers/keyscan/src/device/CMakeLists.txt
new file mode 100644
index 00000000..390b5305
--- /dev/null
+++ b/bee/drivers/keyscan/src/device/CMakeLists.txt
@@ -0,0 +1,11 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+if(CONFIG_REALTEK_BEE_COMMON_DRIVER)
+    file(GLOB BEE_DRIVER_COMMON_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/rtl_common/*.c")
+    zephyr_library_sources(${BEE_DRIVER_COMMON_SOURCES})
+endif()
+
+add_soc_series_subdir(rtl8752h)
+add_soc_series_subdir(rtl87x2g)
+add_soc_series_subdir(rtl87x2j)
diff --git a/bee/drivers/keyscan/src/device/rtl8752h/rtl876x_keyscan.c b/bee/drivers/keyscan/src/device/rtl8752h/rtl876x_keyscan.c
new file mode 100644
index 00000000..f15f3c33
--- /dev/null
+++ b/bee/drivers/keyscan/src/device/rtl8752h/rtl876x_keyscan.c
@@ -0,0 +1,336 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "rtl876x_rcc.h"
+#include "rtl876x_keyscan.h"
+#include "app_section.h"
+
+/**
+  * @brief Initializes the KeyScan peripheral according to the specified
+  *   parameters in the KeyScan_InitStruct
+  * @param  KeyScan: selected KeyScan peripheral.
+  * @param  KeyScan_InitStruct: pointer to a KEYSCAN_InitTypeDef structure that
+  *   contains the configuration information for the specified KeyScan peripheral
+  * @retval None
+  */
+void KeyScan_Init(KEYSCAN_TypeDef *KeyScan, KEYSCAN_InitTypeDef *KeyScan_InitStruct)
+{
+    assert_param(IS_KeyScan_PERIPH(KeyScan));
+    assert_param(IS_KEYSCAN_ROW_NUM(KeyScan_InitStruct->rowSize));
+    assert_param(IS_KEYSCAN_COL_NUM(KeyScan_InitStruct->colSize));
+    assert_param(IS_KEYSCAN_DEBOUNCE_EN(KeyScan_InitStruct->debounceEn));
+    assert_param(IS_KEYSCAN_DETECT_MODE(KeyScan_InitStruct->detectMode));
+    assert_param(IS_KEYSCAN_FIFO_OVR_CTRL(KeyScan_InitStruct->fifoOvrCtrl));
+    assert_param(IS_KEYSCAN_MAX_SCAN_DATA(KeyScan_InitStruct->maxScanData));
+
+    /* Set FSM to idle state */
+    KeyScan->CR &= ~BIT31;
+
+    /* Mask all keyscan interrupt */
+    KeyScan->INTMASK |= 0x1f;
+
+    /* clock divider config */
+    KeyScan->CLKDIV &= ~((0x7FF << 8) | 0x1F);
+    KeyScan->CLKDIV |= ((KeyScan_InitStruct->clockdiv << 8)\
+                        | (KeyScan_InitStruct->delayclk));
+
+    /* Config scan mode and detect mode*/
+    KeyScan->CR = (KeyScan_InitStruct-> scanmode | KeyScan_InitStruct-> detectMode |
+                   KeyScan_InitStruct-> manual_sel | KeyScan_InitStruct->fifoOvrCtrl);
+    /* fifo threshol setting */
+    KeyScan->CR &= ~(0x1F << 5);
+    KeyScan->CR |= (KeyScan_InitStruct ->fifotriggerlevel << 5);
+    /* key limit setting */
+    KeyScan->CR |= (KeyScan_InitStruct ->keylimit << 23);
+
+    /* time config */
+    KeyScan->TIMERCR = ((KeyScan_InitStruct ->debounceEn)\
+                        | (KeyScan_InitStruct->detecttimerEn)\
+                        | (KeyScan_InitStruct->scantimerEn));
+    /* time count config */
+    KeyScan->TIMERCR |= (((KeyScan_InitStruct->debouncecnt & 0x1FF) << 18)\
+                         | ((KeyScan_InitStruct->scanInterval & 0x1FF) << 9)\
+                         | (KeyScan_InitStruct->releasecnt & 0x1FF));
+
+    /* Set col map, config which col to work */
+    KeyScan->COLCR = ((((1 << KeyScan_InitStruct->colSize) - 1) << 8) \
+                      | (KeyScan_InitStruct->colSize - 1));
+
+    /* Set col map, config which col to work */
+    KeyScan->ROWCR = ((KeyScan_InitStruct->rowSize - 1) << 16\
+                      | ((1 << KeyScan_InitStruct->rowSize) - 1));
+
+    /* clear all interrupt status and status flag */
+    KeyScan->INTCLR |= 0xff;
+    /* Unmask all keyscan interrupt */
+    KeyScan->INTMASK &= ~0x1f;
+
+    return;
+}
+
+/**
+  * @brief  Deinitializes the Keyscan peripheral registers to their default reset values(turn off keyscan clock).
+  * @param  KeyScan: selected KeyScan peripheral.
+  * @retval None
+  */
+void KeyScan_DeInit(KEYSCAN_TypeDef *KeyScan)
+{
+    /* Check the parameters */
+    assert_param(IS_KeyScan_PERIPH(KeyScan));
+
+    RCC_PeriphClockCmd(APBPeriph_KEYSCAN, APBPeriph_KEYSCAN_CLOCK, DISABLE);
+
+    return;
+}
+
+
+/**
+  * @brief  Fills each I2C_InitStruct member with its default value.
+  * @param  KeyScan_InitStruct: pointer to an KEYSCAN_InitTypeDef structure which will be initialized.
+  * @retval None
+  */
+void KeyScan_StructInit(KEYSCAN_InitTypeDef *KeyScan_InitStruct)
+{
+    KeyScan_InitStruct->colSize          = 2;
+    KeyScan_InitStruct->rowSize          = 2;
+
+    KeyScan_InitStruct->scanmode         = KeyScan_Auto_Scan_Mode;
+    KeyScan_InitStruct->detectMode       = KeyScan_Detect_Mode_Level;
+    KeyScan_InitStruct->clockdiv         = 0x1f8;
+    KeyScan_InitStruct->delayclk         = 0x01;
+    KeyScan_InitStruct->fifotriggerlevel = 1;
+    KeyScan_InitStruct->fifoOvrCtrl      = KeyScan_FIFO_OVR_CTRL_DIS_LAST;
+
+    KeyScan_InitStruct->debounceEn       = KeyScan_Debounce_Enable;
+    KeyScan_InitStruct->scantimerEn      = KeyScan_ScanInterval_Enable;
+    KeyScan_InitStruct->detecttimerEn    = KeyScan_Release_Detect_Enable;
+
+    KeyScan_InitStruct->scanInterval     = 0x10;
+    KeyScan_InitStruct->debouncecnt      = 0x10;
+    KeyScan_InitStruct->releasecnt       = 0x1;
+
+    KeyScan_InitStruct->keylimit         = 0x03;
+    KeyScan_InitStruct->manual_sel       = KeyScan_Manual_Sel_Bit;
+
+    return;
+}
+
+/**
+  * @brief  Enables or disables the specified KeyScan interrupts.
+  * @param  KeyScan: selected KeyScan peripheral.
+  * @param  KeyScan_IT: specifies the KeyScan interrupts sources to be enabled or disabled.
+  *   This parameter can be any combination of the following values:
+  *     @arg KEYSCAN_INT_THRESHOLD: The interrupt is triggered when FIFO data size equal to threshold level.
+  *     @arg KEYSCAN_INT_OVER_READ: The interrupt is triggered when reading an empty FIFO to prevent over-reading.
+  *     @arg KEYSCAN_INT_SCAN_END: The interrupt is triggered after the Scan key matrix is completed.
+  *     @arg KEYSCAN_INT_FIFO_NOT_EMPTY: The interrupt is triggered when there is data in the FIFO,
+  *                                      and it can be cleared automatically after the FIFO reads empty.
+  *     @arg KEYSCAN_INT_ALL_RELEASE: The interrupt is triggered if no key is pressed
+  *                                   before the release time counter equal to the set value.
+  * @param  NewState: new state of the specified KeyScan interrupts.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void KeyScan_INTConfig(KEYSCAN_TypeDef *KeyScan, uint32_t KeyScan_IT, FunctionalState newState)
+{
+    /* Check the parameters */
+    assert_param(IS_KeyScan_PERIPH(KeyScan));
+    assert_param(IS_FUNCTIONAL_STATE(newState));
+    assert_param(IS_KEYSCAN_CONFIG_IT(KeyScan_IT));
+
+    if (newState == ENABLE)
+    {
+        /* Enable the selected KeyScan interrupts */
+        KeyScan->CR |= KeyScan_IT;
+    }
+    else
+    {
+        /* Disable the selected KeyScan interrupts */
+        KeyScan->CR &= (uint32_t)~KeyScan_IT;
+    }
+}
+
+/**
+  * @brief  Enables or disables the specified KeyScan interrupts mask.
+  * @param  KeyScan: selected KeyScan peripheral.
+  * @param  KeyScan_IT: specifies the KeyScan interrupts sources to be enabled or disabled.
+  *   This parameter can be any combination of the following values:
+  *     @arg KEYSCAN_INT_THRESHOLD: The interrupt is triggered when FIFO data size equal to threshold level.
+  *     @arg KEYSCAN_INT_OVER_READ: The interrupt is triggered when reading an empty FIFO to prevent over-reading.
+  *     @arg KEYSCAN_INT_SCAN_END: The interrupt is triggered after the Scan key matrix is completed.
+  *     @arg KEYSCAN_INT_FIFO_NOT_EMPTY: The interrupt is triggered when there is data in the FIFO,
+  *                                      and it can be cleared automatically after the FIFO reads empty.
+  *     @arg KEYSCAN_INT_ALL_RELEASE: The interrupt is triggered if no key is pressed
+  *                                   before the release time counter equal to the set value.
+  * @param  NewState: new state of the specified KeyScan interrupts mask.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void KeyScan_INTMask(KEYSCAN_TypeDef *KeyScan, uint32_t KeyScan_IT, FunctionalState newState)
+{
+    /* Check the parameters */
+    assert_param(IS_KeyScan_PERIPH(KeyScan));
+    assert_param(IS_FUNCTIONAL_STATE(newState));
+    assert_param(IS_KEYSCAN_CONFIG_IT(KeyScan_IT));
+
+    if (newState == ENABLE)
+    {
+        /* mask KeyScan interrupts */
+        KeyScan->INTMASK |= KeyScan_IT;
+    }
+    else
+    {
+        /* enable KeyScan interrupts */
+        KeyScan->INTMASK &= (~KeyScan_IT);
+    }
+}
+
+/**
+  * @brief  Read data from keyscan FIFO.
+  * @param  KeyScan: selected KeyScan peripheral.
+  * @param[out]  outBuf: buffer to save data read from KeyScan FIFO.
+  * @param  count: number of data to be read.
+  * @retval None
+  */
+void KeyScan_Read(KEYSCAN_TypeDef *KeyScan, uint16_t *outBuf, uint16_t count)
+{
+    /* Check the parameters */
+    assert_param(IS_KeyScan_PERIPH(KeyScan));
+
+    uint16_t i = 0;
+
+    for (i = 0; i < count; i++)
+    {
+        *outBuf++ = (uint16_t)KeyScan->FIFODATA;
+    }
+
+    return;
+}
+
+/**
+  * @brief  Enables or disables the KeyScan peripheral.
+  * @param  KeyScan: selected KeyScan peripheral.
+  * @param  NewState: new state of the KeyScan peripheral.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void KeyScan_Cmd(KEYSCAN_TypeDef *KeyScan, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_KeyScan_PERIPH(KeyScan));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (NewState != DISABLE)
+    {
+        /* Enable the selected KeyScan peripheral */
+        /* In manual mode, bit22 must be write 1 to trigger scan,
+        and will be clear to 0 automatically after scan finish */
+        if (((KeyScan->CR & BIT30) == 0) && ((KeyScan->CR & BIT11) == 0))
+        {
+            KeyScan->CR |= BIT22;
+        }
+
+        KeyScan->CR |= BIT31;
+    }
+    else
+    {
+        /* Disable the selected KeyScan peripheral */
+        KeyScan->CR &= ~BIT31;
+    }
+}
+
+/**
+  * @brief  Set filter data.
+  * @param  KeyScan: selected KeyScan peripheral.
+  * @param  data: config the data to be filtered.
+  *   This parameter should not be more than 9 bits
+  * @param  NewState: new state of the data filter.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval none.
+  */
+void KeyScan_FilterDataConfig(KEYSCAN_TypeDef *KeyScan, uint16_t data, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_KeyScan_PERIPH(KeyScan));
+
+    if (NewState == ENABLE)
+    {
+        KeyScan->CR &= ~BIT21;
+
+        KeyScan->CR &= ~(0x1ff << 12);
+        KeyScan->CR |= ((data & 0x1ff) << 12);
+
+        KeyScan->CR |= BIT21;
+    }
+    else
+    {
+        KeyScan->CR &= ~BIT21;
+
+        KeyScan->CR &= ~(0x1ff << 12);
+        KeyScan->CR |= ((data & 0x1ff) << 12);
+    }
+
+    return;
+}
+
+/**
+  * \brief  Store KEYSCAN register values when system enter DLPS.
+  * \param  PeriReg: Specifies to select the KEYSCAN peripheral.
+  * \param  StoreBuf: Store buffer to store KEYSCAN register data.
+  * \return None.
+  */
+DATA_RAM_FUNCTION
+void KEYSCAN_DLPSEnter(void *PeriReg, void *StoreBuf)
+{
+    KEYSCANStoreReg_TypeDef *store_buf = (KEYSCANStoreReg_TypeDef *)StoreBuf;
+
+    /*Open 5M clock source*/
+    SYSBLKCTRL->u_20C.PERION_REG_SYS_CLK_SEL_2 |= BIT26;
+    SYSBLKCTRL->u_20C.PERION_REG_SYS_CLK_SEL_2 |= BIT29;
+
+    RCC_PeriphClockCmd(APBPeriph_KEYSCAN, APBPeriph_KEYSCAN_CLOCK, ENABLE);
+
+    store_buf->keyscan_reg[0] = KEYSCAN->CLKDIV;               /* 0x00 */
+    store_buf->keyscan_reg[1] = KEYSCAN->TIMERCR;              /* 0x04 */
+    store_buf->keyscan_reg[2] = KEYSCAN->CR;                   /* 0x08 */
+    store_buf->keyscan_reg[3] = KEYSCAN->COLCR;                /* 0x0C */
+    store_buf->keyscan_reg[4] = KEYSCAN->ROWCR;                /* 0x10 */
+    store_buf->keyscan_reg[6] = KEYSCAN->INTMASK;              /* 0x18 */
+
+    return;
+}
+
+/**
+  * \brief  Restore KEYSCAN register values when system exit DLPS.
+  * \param  PeriReg: Specifies to select the KEYSCAN peripheral.
+  * \param  StoreBuf: Restore buffer to restore KEYSCAN register data.
+  * \return None
+  */
+DATA_RAM_FUNCTION
+void KEYSCAN_DLPSExit(void *PeriReg, void *StoreBuf)
+{
+    KEYSCANStoreReg_TypeDef *store_buf = (KEYSCANStoreReg_TypeDef *)StoreBuf;
+
+    /*Open 5M clock source*/
+    SYSBLKCTRL->u_20C.PERION_REG_SYS_CLK_SEL_2 |= BIT26;
+    SYSBLKCTRL->u_20C.PERION_REG_SYS_CLK_SEL_2 |= BIT29;
+
+    RCC_PeriphClockCmd(APBPeriph_KEYSCAN, APBPeriph_KEYSCAN_CLOCK, ENABLE);
+
+    /* Set FSM to idle state */
+    KEYSCAN->CR      &= ~BIT31;
+    KEYSCAN->CLKDIV  = store_buf->keyscan_reg[0];
+    KEYSCAN->CR      = (store_buf->keyscan_reg[2] & (~(BIT31)));
+    KEYSCAN->TIMERCR = store_buf->keyscan_reg[1];
+    KEYSCAN->COLCR   = store_buf->keyscan_reg[3];
+    KEYSCAN->ROWCR   = store_buf->keyscan_reg[4];
+    KEYSCAN->INTMASK = store_buf->keyscan_reg[6];
+    KEYSCAN->CR      |= (store_buf->keyscan_reg[2] & ((BIT31)));
+
+    return;
+}
+
+
diff --git a/bee/drivers/keyscan/src/device/rtl8752h/rtl876x_keyscan.h b/bee/drivers/keyscan/src/device/rtl8752h/rtl876x_keyscan.h
new file mode 100644
index 00000000..a4334734
--- /dev/null
+++ b/bee/drivers/keyscan/src/device/rtl8752h/rtl876x_keyscan.h
@@ -0,0 +1,670 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *               Define to prevent recursive inclusion
+ *============================================================================*/
+#ifndef _RTL876X_KEYSCAN_H_
+#define _RTL876X_KEYSCAN_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup  IO          Peripheral Drivers
+ * \defgroup    KEYSCAN     KEYSCAN
+ *
+ * \brief       Manage the KEYSCAN peripheral functions.
+ *
+ * \ingroup     IO
+ */
+
+/*============================================================================*
+ *                         Includes
+ *============================================================================*/
+#include "rtl876x.h"
+
+
+/*============================================================================*
+ *                         Types
+ *============================================================================*/
+/**
+ * \defgroup    KEYSCAN_Exported_Types  KEYSCAN Exported Types
+ *
+ * \ingroup     KEYSCAN
+ */
+
+/**
+ * \brief       KEYSCAN initialize parameters
+ *
+ * \ingroup     KEYSCAN_Exported_Types
+ */
+typedef struct
+{
+    uint16_t rowSize;           /*!< Specify Keyscan Row Size.
+                                        This parameter can be a value <=12. */
+    uint16_t colSize;           /*!< Specify Keyscan Column Size.
+                                        This parameter can be a value <=20. */
+    uint32_t detectPeriod;      /*!< <b>Deprecated</b> */
+    uint16_t timeout;           /*!< <b>Deprecated</b> */
+    uint16_t scanInterval;      /*!< Specify Keyscan scan interval. scan interval = delay clock * scanInterval*/
+    uint32_t debounceEn;        /*!< Enable or disable debounce.
+                                     This parameter can be a value of \ref KEYSCAN_Debounce_Config. */
+    uint32_t scantimerEn;       /*!< Enable or disable scan timer.
+                                     This parameter can be a value of \ref KEYSCAN_Scan_Interval_En. */
+    uint32_t detecttimerEn;     /*!< Enable or disable detect timer.
+                                     This parameter can be a value of \ref KEYSCAN_Release_Detect_Timer_En. */
+    uint16_t debounceTime;      /*!< <b>Deprecated</b> */
+    uint32_t detectMode;        /*!< Specify Key Detect mode.
+                                     This parameter can be a value of \ref KEYSCAN_Press_Detect_Mode */
+    uint32_t fifoOvrCtrl;       /*!< Specify Keyscan fifo over flow control.
+                                     This parameter can be a value of \ref KEYSCAN_FIFO_Overflow_Control */
+    uint16_t maxScanData;       /*!< <b>Deprecated</b> */
+    uint32_t scanmode;          /*!< Specify Keyscan mode.
+                                     This parameter can be a value of \ref KEYSCAN_Scan_Mode. */
+    uint16_t clockdiv;          /*!< Specify Keyscan clock divider. scan clock = system clock/(clockdiv+1). */
+    uint8_t delayclk;           /*!< Specify Keyscan delay clock divider. delay clock = scan clock/(delayclk+1)*/
+    uint16_t fifotriggerlevel;  /*!< Specify Keyscan fifo threshold to trigger interrupt KEYSCAN_INT_THRESHOLD.*/
+    uint16_t debouncecnt;        /*!< Specify Keyscan debounce time, debounce time = delay clock * debouncecnt. */
+    uint16_t releasecnt;         /*!< Specify Keyscan release time, release time = delay clock * releasecnt. */
+    uint8_t keylimit;           /*!< Specify max scan data allowable in each scan. 0 means no limit. */
+    uint32_t manual_sel;        /*!< Specify trigger mode in manual mode.
+                                     This parameter can be a value of \ref KEYSCAN_Manual_Mode. */
+} KEYSCAN_InitTypeDef;
+
+/** End of KEYSCAN_Exported_Types
+  * \}
+  */
+
+/*============================================================================*
+ *                         Constants
+ *============================================================================*/
+/**
+ * \defgroup    KEYSCAN_Exported_Constants  KEYSCAN Exported Constants
+ *
+ * \ingroup     KEYSCAN
+ */
+
+/**
+ * \defgroup    KEYSCAN_Config KEYSCAN Config
+ * \{
+ * \ingroup     KEYSCAN_Exported_Constants
+ */
+#define IS_KeyScan_PERIPH(PERIPH) ((PERIPH) == KEYSCAN)
+/** \} */
+
+/**
+ * \defgroup    KEYSCAN_Row_Number KEYSCAN Row Number
+ * \{
+ * \ingroup     KEYSCAN_Exported_Constants
+ */
+#define IS_KEYSCAN_ROW_NUM(ROW) ((ROW) <= 12)
+/** \} */
+
+/**
+ * \defgroup    KEYSCAN_Column_Number KEYSCAN Column Number
+ * \{
+ * \ingroup     KEYSCAN_Exported_Constants
+ */
+#define IS_KEYSCAN_COL_NUM(COL) ((COL) <= 20)
+/** \} */
+
+/**
+ * \defgroup    KEYSCAN_Debounce_Time KEYSCAN Debounce Time
+ * \{
+ * \ingroup     KEYSCAN_Exported_Constants
+ */
+#define IS_KEYSCAN_MAX_SCAN_DATA(DATA_NUM) ((DATA_NUM) <= 26) //0 means no limit
+/** \} */
+
+/**
+ * \defgroup    KEYSCAN_Scan_Mode KEYSCAN Scan Mode
+ * \{
+ * \ingroup     KEYSCAN_Exported_Constants
+ */
+#define KeyScan_Manual_Scan_Mode        ((uint32_t)(0x0 << 30))
+#define KeyScan_Auto_Scan_Mode          ((uint32_t)(0x1 << 30))
+
+#define IS_KEYSCAN_SCAN_MODE(MODE)    (((MODE) == KeyScan_Detect_Mode_Edge) || ((MODE) == KeyScan_Detect_Mode_Level))
+/** \} */
+
+/**
+ * \defgroup    KEYSCAN_Manual_Mode KEYSCAN Manual Mode
+ * \{
+ * \ingroup     KEYSCAN_Exported_Constants
+ */
+#define KeyScan_Manual_Sel_Bit          ((uint32_t)(0x0 << 11))
+#define KeyScan_Manual_Sel_Key          ((uint32_t)(0x1 << 11))
+/** \} */
+
+/**
+ * \defgroup    KEYSCAN_FIFO_Overflow_Control KEYSCAN FIFO Overflow Control
+ * \{
+ * \ingroup     KEYSCAN_Exported_Constants
+ */
+
+#define KeyScan_FIFO_OVR_CTRL_DIS_ALL   ((uint32_t)(0x0 << 28))   //discard all the new scan data when FIFO is full
+#define KeyScan_FIFO_OVR_CTRL_DIS_LAST  ((uint32_t)(0x1 << 28))   //discard the oldest scan data when FIFO is full
+
+#define IS_KEYSCAN_FIFO_OVR_CTRL(CTRL)  (((CTRL) == KeyScan_FIFO_OVR_CTRL_DIS_ALL) || ((CTRL) == KeyScan_FIFO_OVR_CTRL_DIS_LAST))
+/** \} */
+
+/**
+ * \defgroup    KEYSCAN_Debounce_Config KEYSCAN Debounce Config
+ * \{
+ * \ingroup     KEYSCAN_Exported_Constants
+ */
+#define KeyScan_Debounce_Enable              ((uint32_t)0x1 << 31)
+#define KeyScan_Debounce_Disable             ((uint32_t)0x0 << 31)
+
+#define IS_KEYSCAN_DEBOUNCE_EN(EN) (((EN) == KeyScan_Debounce_Enable) || ((EN) == KeyScan_Debounce_Disable))    //0 means no limit
+/** \} */
+
+/**
+ * \defgroup    KEYSCAN_Scan_Interval_En   KEYSCAN Scan Interval Enable
+ * \{
+ * \ingroup     KEYSCAN_Exported_Constants
+ */
+#define KeyScan_ScanInterval_Enable              ((uint32_t)(0x1 << 30))
+#define KeyScan_ScanInterval_Disable             ((uint32_t)(0x0 << 30))
+
+#define IS_KEYSCAN_SCANINTERVAL_EN(EN) (((EN) == KeyScan_ScanInterval_Enable) || ((EN) == KeyScan_ScanInterval_Disable))    //0 means no limit
+/** \} */
+
+/**
+ * \defgroup    KEYSCAN_Release_Detect_Timer_En     KEYSCAN Release Detect Timer Enable
+ * \{
+ * \ingroup     KEYSCAN_Exported_Constants
+ */
+#define KeyScan_Release_Detect_Enable              ((uint32_t)(0x1 << 29))
+#define KeyScan_Release_Detect_Disable             ((uint32_t)(0x0 << 29))
+
+#define IS_KEYSCAN_RELEASE_DETECT_EN(EN) (((EN) == KeyScan_Release_Detect_Enable) || ((EN) == KeyScan_Release_Detect_Disable))    //0 means no limit
+/** \} */
+
+/**
+ * \defgroup    KEYSCAN_Press_Detect_Mode KEYSCAN Press Detect Mode
+ * \{
+ * \ingroup     KEYSCAN_Exported_Constants
+ */
+
+#define KeyScan_Detect_Mode_Edge        ((uint32_t)(0x0 << 29))
+#define KeyScan_Detect_Mode_Level       ((uint32_t)(0x1 << 29))
+
+#define IS_KEYSCAN_DETECT_MODE(MODE)    (((MODE) == KeyScan_Detect_Mode_Edge) || ((MODE) == KeyScan_Detect_Mode_Level))
+/** \} */
+
+/**
+ * \defgroup    KEYSCAN_Interrupt_Definition    KEYSCAN Interrupt Definition
+ * \{
+ * \ingroup     KEYSCAN_Exported_Constants
+ */
+#define KEYSCAN_INT_THRESHOLD                    ((uint16_t)(0x1 << 4))
+#define KEYSCAN_INT_OVER_READ                    ((uint16_t)(0x1 << 3))
+#define KEYSCAN_INT_SCAN_END                     ((uint16_t)(0x1 << 2))
+#define KEYSCAN_INT_FIFO_NOT_EMPTY               ((uint16_t)(0x1 << 1))
+#define KEYSCAN_INT_ALL_RELEASE                  ((uint16_t)(0x1 << 0))
+
+#define IS_KEYSCAN_CONFIG_IT(IT) (((IT) == KEYSCAN_INT_ALL_RELEASE) || \
+                                  ((IT) == KEYSCAN_INT_FIFO_NOT_EMPTY) || \
+                                  ((IT) == KEYSCAN_INT_SCAN_END) || \
+                                  ((IT) == KEYSCAN_INT_OVER_READ) || \
+                                  ((IT) == KEYSCAN_INT_THRESHOLD))
+/** \} */
+
+/**
+ * \defgroup    KEYSCAN_Flag_Definition   KEYSCAN Flag Definition
+ * \{
+ * \ingroup     KEYSCAN_Exported_Constants
+ */
+#define KEYSCAN_FLAG_FIFOLIMIT                       ((uint32_t)(0x1 << 20))
+#define KEYSCAN_INT_FLAG_THRESHOLD                   ((uint32_t)(0x1 << 19))
+#define KEYSCAN_INT_FLAG_OVER_READ                   ((uint32_t)(0x1 << 18))
+#define KEYSCAN_INT_FLAG_SCAN_END                    ((uint32_t)(0x1 << 17))
+#define KEYSCAN_INT_FLAG_FIFO_NOT_EMPTY              ((uint32_t)(0x1 << 16))
+#define KEYSCAN_INT_FLAG_ALL_RELEASE                 ((uint32_t)(0x1 << 15))
+#define KEYSCAN_FLAG_DATAFILTER                      ((uint32_t)(0x1 << 3))
+#define KEYSCAN_FLAG_OVR                             ((uint32_t)(0x1 << 2))
+#define KEYSCAN_FLAG_FULL                            ((uint32_t)(0x1 << 1))
+#define KEYSCAN_FLAG_EMPTY                           ((uint32_t)(0x1 << 0))
+
+#define IS_KEYSCAN_FLAG(FLAG)       ((((FLAG) & (~(uint32_t)0x1F800F)) == 0x00) && ((FLAG) != (uint32_t)0x00))
+#define IS_KEYSCAN_CLEAR_FLAG(FLAG) (((FLAG) == KEYSCAN_FLAG_FIFOLIMIT) || \
+                                     ((FLAG) == KEYSCAN_FLAG_DATAFILTER) || \
+                                     ((FLAG) == KEYSCAN_FLAG_OVR))
+/** \} */
+
+/**
+ * \defgroup    KEYSCAN_FIFO_Available_Mask KEYSCAN FIFO Available Mask
+ * \{
+ * \ingroup     KEYSCAN_Exported_Constants
+ */
+#define STATUS_FIFO_DATA_NUM_MASK           ((uint32_t)(0x3F << 4))
+/** \} */
+
+/** End of KEYSCAN_Exported_Constants
+  * \}
+  */
+
+/*============================================================================*
+ *                         Functions
+ *============================================================================*/
+/**
+ * \defgroup    KEYSCAN_Exported_Functions KEYSCAN Exported Functions
+ * \{
+ * \ingroup     KEYSCAN
+ */
+
+/**
+ * \brief  Deinitialize the Keyscan peripheral registers to their default reset values(turn off keyscan clock).
+ * \param[in]  KeyScan: SSelected KeyScan peripheral.
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_keyscan_init(void)
+ * {
+ *     KeyScan_DeInit(KEYSCAN);
+ * }
+ * \endcode
+ */
+void KeyScan_DeInit(KEYSCAN_TypeDef *KeyScan);
+
+/**
+ * \brief   Initialize the KeyScan peripheral according to the specified
+ *          parameters in the KeyScan_InitStruct
+ * \param[in]  KeyScan: Selected KeyScan peripheral.
+ * \param[in]  KeyScan_InitStruct: Pointer to a KEYSCAN_InitTypeDef structure that
+ *             contains the configuration information for the specified KeyScan peripheral
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_keyscan_init(void)
+ * {
+ *     RCC_PeriphClockCmd(APBPeriph_KEYSCAN, APBPeriph_KEYSCAN_CLOCK, ENABLE);
+
+ *     KEYSCAN_InitTypeDef KEYSCAN_InitStruct;
+ *     KeyScan_StructInit(&KEYSCAN_InitStruct);
+
+ *     KEYSCAN_InitStruct.rowSize  = 2;
+ *     KEYSCAN_InitStruct.colSize  = 2;
+ *     KEYSCAN_InitStruct.scanmode     = KeyScan_Manual_Scan_Mode;
+
+ *     KeyScan_Init(KEYSCAN, &KEYSCAN_InitStruct);
+
+ *     KeyScan_INTConfig(KEYSCAN, KEYSCAN_INT_SCAN_END, ENABLE);
+ *     KeyScan_ClearINTPendingBit(KEYSCAN, KEYSCAN_INT_SCAN_END);
+ *     KeyScan_INTMask(KEYSCAN, KEYSCAN_INT_SCAN_END, DISABLE);  // Unmask keyscan interrupt
+ *     KeyScan_Cmd(KEYSCAN, ENABLE);
+ * }
+ * \endcode
+ */
+void KeyScan_Init(KEYSCAN_TypeDef *KeyScan, KEYSCAN_InitTypeDef *KeyScan_InitStruct);
+
+/**
+ * \brief  Fill each KeyScan_InitStruct member with its default value.
+ * \param[in]  KeyScan_InitStruct: Pointer to a KEYSCAN_InitTypeDef structure which will be initialized.
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_keyscan_init(void)
+ * {
+ *     RCC_PeriphClockCmd(APBPeriph_KEYSCAN, APBPeriph_KEYSCAN_CLOCK, ENABLE);
+
+ *     KEYSCAN_InitTypeDef KEYSCAN_InitStruct;
+ *     KeyScan_StructInit(&KEYSCAN_InitStruct);
+
+ *     KEYSCAN_InitStruct.rowSize  = 2;
+ *     KEYSCAN_InitStruct.colSize  = 2;
+ *     KEYSCAN_InitStruct.scanmode     = KeyScan_Manual_Scan_Mode;
+
+ *     KeyScan_Init(KEYSCAN, &KEYSCAN_InitStruct);
+
+ *     KeyScan_INTConfig(KEYSCAN, KEYSCAN_INT_SCAN_END, ENABLE);
+ *     KeyScan_ClearINTPendingBit(KEYSCAN, KEYSCAN_INT_SCAN_END);
+ *     KeyScan_INTMask(KEYSCAN, KEYSCAN_INT_SCAN_END, DISABLE);  // Unmask keyscan interrupt
+ *     KeyScan_Cmd(KEYSCAN, ENABLE);
+ * }
+ * \endcode
+ */
+void KeyScan_StructInit(KEYSCAN_InitTypeDef *KeyScan_InitStruct);
+
+/**
+ * \brief  Enable or disable the specified KeyScan interrupt.
+ * \param[in]  KeyScan: Selected KeyScan peripheral.
+ * \param[in]  KeyScan_IT: Specify the KeyScan interrupt sources to be enabled or disabled.
+ *      This parameter can be any combination of the following values, which refer to \ref KEYSCAN_Interrupt_Definition.
+ *      \arg KEYSCAN_INT_THRESHOLD: The interrupt is triggered when FIFO data size equals the threshold level.
+ *      \arg KEYSCAN_INT_OVER_READ: The interrupt is triggered when reading an empty FIFO to prevent over-reading.
+ *      \arg KEYSCAN_INT_SCAN_END: The interrupt is triggered after the Scan key matrix is completed.
+ *      \arg KEYSCAN_INT_FIFO_NOT_EMPTY: The interrupt is triggered when there is data in the FIFO,
+ *                                       and it can be cleared automatically after the FIFO reads empty.
+ *      \arg KEYSCAN_INT_ALL_RELEASE: The interrupt is triggered if no key is pressed
+ *                                    before the release time counter equals the set value.
+ * \param[in] newState: New state of the specified KeyScan interrupts.
+ *      This parameter can be: ENABLE or DISABLE.
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void keyscan_demo(void)
+ * {
+ *     KeyScan_INTMask(KEYSCAN, KEYSCAN_INT_SCAN_END, ENABLE);
+ *     KeyScan_INTConfig(KEYSCAN, KEYSCAN_INT_SCAN_END, ENABLE);
+ *     KeyScan_INTMask(KEYSCAN, KEYSCAN_INT_SCAN_END, DISABLE);
+ * }
+ * \endcode
+ */
+void KeyScan_INTConfig(KEYSCAN_TypeDef *KeyScan, uint32_t KeyScan_IT,
+                       FunctionalState newState);
+
+/**
+ * \brief  Mask the specified KeyScan interrupt.
+ * \param[in]  KeyScan: Selected KeyScan peripheral.
+ * \param[in]  KeyScan_IT: Specify the KeyScan interrupt sources to be enabled or disabled.
+ *      This parameter can be any combination of the following values, which refer to \ref KEYSCAN_Interrupt_Definition.
+ *      \arg KEYSCAN_INT_THRESHOLD: The interrupt is triggered when FIFO data size equals the threshold level.
+ *      \arg KEYSCAN_INT_OVER_READ: The interrupt is triggered when reading an empty FIFO to prevent over-reading.
+ *      \arg KEYSCAN_INT_SCAN_END: The interrupt is triggered after the Scan key matrix is completed.
+ *      \arg KEYSCAN_INT_FIFO_NOT_EMPTY: The interrupt is triggered when there is data in the FIFO,
+ *                                       and it can be cleared automatically after the FIFO reads empty.
+ *      \arg KEYSCAN_INT_ALL_RELEASE: The interrupt is triggered if no key is pressed
+ *                                    before the release time counter equals the set value.
+ * \param[in] newState: New state of the specified KeyScan interrupts mask.
+ *      This parameter can be: ENABLE or DISABLE.
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void keyscan_demo(void)
+ * {
+ *     KeyScan_INTMask(KEYSCAN, KEYSCAN_INT_SCAN_END, ENABLE);
+ *     KeyScan_INTConfig(KEYSCAN, KEYSCAN_INT_SCAN_END, ENABLE);
+ *     KeyScan_INTMask(KEYSCAN, KEYSCAN_INT_SCAN_END, DISABLE);
+ * }
+ * \endcode
+ */
+void KeyScan_INTMask(KEYSCAN_TypeDef *KeyScan, uint32_t KeyScan_IT,
+                     FunctionalState newState);
+
+/**
+ * \brief  Read data from keyscan FIFO.
+ * \param[in]  KeyScan: Selected KeyScan peripheral.
+ * \param[out] outBuf: Buffer to save data read from KeyScan FIFO.
+ * \param[in]  count: Data length to be read.
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void keyscan_demo(void)
+ * {
+ *     uint16_t data[3] = {0};
+ *     KeyScan_Read(KEYSCAN, data, 3);
+ * }
+ * \endcode
+ */
+void KeyScan_Read(KEYSCAN_TypeDef *KeyScan, uint16_t *outBuf, uint16_t count);
+
+/**
+ * \brief   Enable or disable the KeyScan peripheral.
+ * \param[in] KeyScan: Selected KeyScan peripheral.
+ * \param[in] NewState: New state of the KeyScan peripheral.
+ *      This parameter can be: ENABLE or DISABLE.
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void keyscan_demo(void)
+ * {
+ *     KeyScan_Cmd(KEYSCAN, ENABLE);
+ * }
+ * \endcode
+ */
+void KeyScan_Cmd(KEYSCAN_TypeDef *KeyScan, FunctionalState NewState);
+
+/**
+ * \brief   Set filter data.
+ * \param[in] KeyScan: Selected KeyScan peripheral.
+ * \param[in] data: Configure the data to be filtered.
+ *      This parameter should not be more than 9 bits.
+ * \param[in] NewState: New state of the data filter.
+ *      This parameter can be: ENABLE or DISABLE.
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void keyscan_demo(void)
+ * {
+ *     KeyScan_FilterDataConfig(KEYSCAN, 0x01, ENABLE);
+ *
+ * }
+ * \endcode
+ */
+void KeyScan_FilterDataConfig(KEYSCAN_TypeDef *KeyScan, uint16_t data,
+                              FunctionalState NewState);
+
+/**
+ * \brief   KeyScan debounce time config.
+ * \param[in] KeyScan: Selected KeyScan peripheral.
+ * \param[in] time: Keyscan hardware debounce time. debounce time = delay clock * time.
+ * \param[in] NewState: New state of the KeyScan debounce function.
+ *      This parameter can be: ENABLE or DISABLE.
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void keyscan_demo(void)
+ * {
+ *     KeyScan_debounceConfig(KEYSCAN, 10, ENABLE);
+ *
+ * }
+ * \endcode
+ */
+__STATIC_INLINE void KeyScan_debounceConfig(KEYSCAN_TypeDef *KeyScan, uint16_t time,
+                                            FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_KeyScan_PERIPH(KeyScan));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    KeyScan->TIMERCR &= ~((0x1ff << 18) | BIT31);
+    KeyScan->TIMERCR |= ((NewState << 31) | (time & 0x1FF) << 18);
+
+}
+
+/**
+ * \brief   Get KeyScan FIFO data num.
+ * \param[in]  KeyScan: Selected KeyScan peripheral.
+ * \return  Data length in FIFO.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void keyscan_demo(void)
+ * {
+ *     uint16_t data_len = KeyScan_GetFifoDataNum(KEYSCAN);
+ * }
+ * \endcode
+ */
+__STATIC_INLINE uint16_t KeyScan_GetFifoDataNum(KEYSCAN_TypeDef *KeyScan)
+{
+    assert_param(IS_KeyScan_PERIPH(KeyScan));
+
+    return (uint16_t)((KeyScan->STATUS & STATUS_FIFO_DATA_NUM_MASK) >> 4);
+}
+
+/**
+ * \brief  Clear the KeyScan interrupt pending bit.
+ * \param[in]  KeyScan: Selected KeyScan peripheral.
+ * \param[in]  KeyScan_IT: Specify the interrupt pending bit to clear.
+ *      This parameter can be any combination of the following values, which refer to \ref KEYSCAN_Interrupt_Definition.
+ *      \arg KEYSCAN_INT_THRESHOLD: The interrupt is triggered when FIFO data size equals the threshold level.
+ *      \arg KEYSCAN_INT_OVER_READ: The interrupt is triggered when reading an empty FIFO to prevent over-reading.
+ *      \arg KEYSCAN_INT_SCAN_END: The interrupt is triggered after the Scan key matrix is completed.
+ *      \arg KEYSCAN_INT_FIFO_NOT_EMPTY: The interrupt is triggered when there is data in the FIFO,
+ *                                       and it can be cleared automatically after the FIFO reads empty.
+ *      \arg KEYSCAN_INT_ALL_RELEASE: The interrupt is triggered if no key is pressed
+ *                                    before the release time counter equals the set value.
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void keyscan_demo(void)
+ * {
+ *     KeyScan_ClearINTPendingBit(KEYSCAN, KEYSCAN_INT_SCAN_END);
+ * }
+ * \endcode
+ */
+__STATIC_INLINE void KeyScan_ClearINTPendingBit(KEYSCAN_TypeDef *KeyScan, uint32_t KeyScan_IT)
+{
+    /* Check the parameters */
+    assert_param(IS_KeyScan_PERIPH(KeyScan));
+    assert_param(IS_KEYSCAN_CONFIG_IT(KeyScan_IT));
+
+    KeyScan->INTCLR |= KeyScan_IT;
+
+    return;
+}
+
+/**
+ * \brief   Clear the specified KeyScan flag.
+ * \param[in]  KeyScan: Selected KeyScan peripheral.
+ * \param[in]  KeyScan_FLAG: Specify the flag to clear.
+ *      This parameter can be one of the following values, which refer to \ref KEYSCAN_Flag_Definition.
+ *      \arg KEYSCAN_FLAG_FIFOLIMIT: Overflow FIFO limit in one scan
+ *      \arg KEYSCAN_FLAG_DATAFILTER: FIFO filter status
+ *      \arg KEYSCAN_FLAG_OVR: The flag to indicate FIFO is overflow
+ * \return  None.
+ * \note    KEYSCAN_FLAG_FULL and KEYSCAN_FLAG_EMPTY can't be cleared manually.
+ *          They are cleared by hardware automatically.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void keyscan_demo(void)
+ * {
+ *     KeyScan_ClearFlags(KEYSCAN, KEYSCAN_FLAG_FIFOLIMIT);
+ * }
+ * \endcode
+ */
+__STATIC_INLINE void KeyScan_ClearFlags(KEYSCAN_TypeDef *KeyScan, uint32_t KeyScan_FLAG)
+{
+    /* Check the parameters */
+    assert_param(IS_KeyScan_PERIPH(KeyScan));
+    assert_param(IS_KEYSCAN_CLEAR_FLAG(KeyScan_FLAG));
+
+    if (KeyScan_FLAG & KEYSCAN_FLAG_FIFOLIMIT)
+    {
+        KeyScan->INTCLR |= BIT8;
+    }
+    if (KeyScan_FLAG & KEYSCAN_FLAG_DATAFILTER)
+    {
+        KeyScan->INTCLR |= BIT7;
+    }
+    if (KeyScan_FLAG & KEYSCAN_FLAG_OVR)
+    {
+        KeyScan->INTCLR |= BIT5;
+    }
+
+    return;
+}
+
+/**
+ * \brief   Check whether the specified KeyScan flag is set.
+ * \param[in]  KeyScan: Selected KeyScan peripheral.
+ * \param[in]  KeyScan_FLAG: Specify the flag to check.
+ *      This parameter can be one of the following values, which refer to \ref KEYSCAN_Flag_Definition.
+ *      \arg KEYSCAN_FLAG_FIFOLIMIT: Overflow FIFO limit in one scan
+ *      \arg KEYSCAN_INT_FLAG_THRESHOLD: FIFO threshold interrupt status
+ *      \arg KEYSCAN_INT_FLAG_OVER_READ: FIFO over read interrupt status
+ *      \arg KEYSCAN_INT_FLAG_SCAN_END: Scan finish interrupt status
+ *      \arg KEYSCAN_INT_FLAG_FIFO_NOT_EMPTY: FIFO not empty interrupt status
+ *      \arg KEYSCAN_INT_FLAG_ALL_RELEASE: Release interrupt status
+ *      \arg KEYSCAN_FLAG_DATAFILTER: FIFO filter status
+ *      \arg KEYSCAN_FLAG_OVR: The flag to indicate FIFO is overflow
+ *      \arg KEYSCAN_FLAG_FULL: The flag to indicate FIFO is full
+ *      \arg KEYSCAN_FLAG_EMPTY: The flag to indicate FIFO is empty
+ * \return  The new state of KeyScan_FLAG (SET or RESET).
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void keyscan_demo(void)
+ * {
+ *     FlagStatus flag_status = KeyScan_GetFlagState(KEYSCAN, KEYSCAN_FLAG_OVR);
+ *
+ * }
+ * \endcode
+ */
+__STATIC_INLINE FlagStatus KeyScan_GetFlagState(KEYSCAN_TypeDef *KeyScan, uint32_t KeyScan_FLAG)
+{
+    FlagStatus bitstatus = RESET;
+
+    /* Check the parameters */
+    assert_param(IS_KeyScan_PERIPH(KeyScan));
+    assert_param(IS_KEYSCAN_FLAG(KeyScan_FLAG));
+
+    if ((KeyScan->STATUS & KeyScan_FLAG) != 0)
+    {
+        bitstatus = SET;
+    }
+
+    return bitstatus;
+}
+
+/**
+ * \brief  Read FIFO data.
+ * \param[in] KeyScan: Selected KeyScan peripheral.
+ * \return Keyscan FIFO data.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void keyscan_demo(void)
+ * {
+ *     uint16_t data = KeyScan_ReadFifoData(KEYSCAN);
+ * }
+ * \endcode
+ */
+__STATIC_INLINE uint16_t KeyScan_ReadFifoData(KEYSCAN_TypeDef *KeyScan)
+{
+    /* Check the parameters */
+    assert_param(IS_KeyScan_PERIPH(KeyScan));
+
+    return (uint16_t)(KeyScan->FIFODATA);
+}
+
+/** End of KEYSCAN_Exported_Functions
+  * \}
+  */
+
+/** End of KEYSCAN
+  * \}
+  */
+
+typedef struct
+{
+    uint32_t keyscan_reg[7];
+} KEYSCANStoreReg_TypeDef;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTL876X_KEYSCAN_H_ */
diff --git a/bee/drivers/keyscan/src/device/rtl87x2g/rtl87x2g_keyscan.c b/bee/drivers/keyscan/src/device/rtl87x2g/rtl87x2g_keyscan.c
new file mode 100644
index 00000000..4d293f5b
--- /dev/null
+++ b/bee/drivers/keyscan/src/device/rtl87x2g/rtl87x2g_keyscan.c
@@ -0,0 +1,65 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *                        Header Files
+ *============================================================================*/
+#include "rtl_keyscan.h"
+#include "rtl_rcc.h"
+#include "app_section.h"
+
+/*============================================================================*
+ *                           Public Functions
+ *============================================================================*/
+/**
+  * \brief  Store KEYSCAN register values when system enter DLPS.
+  * \param  PeriReg: Specifies to select the KEYSCAN peripheral.
+  * \param  StoreBuf: Store buffer to store KEYSCAN register data.
+  * \return None.
+  */
+RAM_FUNCTION
+void KEYSCAN_DLPSEnter(void *PeriReg, void *StoreBuf)
+{
+    KEYSCANStoreReg_Typedef *store_buf = (KEYSCANStoreReg_Typedef *)StoreBuf;
+
+    RCC_PeriphClockCmd(APBPeriph_KEYSCAN, APBPeriph_KEYSCAN_CLOCK, ENABLE);
+
+    store_buf->keyscan_reg[0] = KEYSCAN->KEYSCAN_CLK_DIV;         /* 0x00 */
+    store_buf->keyscan_reg[1] = KEYSCAN->KEYSCAN_CONFIG1;         /* 0x04 */
+    store_buf->keyscan_reg[2] = KEYSCAN->KEYSCAN_CONFIG2;         /* 0x08 */
+    store_buf->keyscan_reg[3] = KEYSCAN->KEYSCAN_COLUMN_CONFIG;   /* 0x0C */
+    store_buf->keyscan_reg[4] = KEYSCAN->KEYSCAN_ROW_CONFIG;      /* 0x10 */
+    store_buf->keyscan_reg[6] = KEYSCAN->KEYSCAN_INT_MASK;        /* 0x18 */
+
+    return;
+}
+
+/**
+  * \brief  Restore KEYSCAN register values when system enter DLPS.
+  * \param  PeriReg: Specifies to select the KEYSCAN peripheral.
+  * \param  StoreBuf: Restore buffer to restore KEYSCAN register data.
+  * \return None
+  */
+RAM_FUNCTION
+void KEYSCAN_DLPSExit(void *PeriReg, void *StoreBuf)
+{
+    KEYSCANStoreReg_Typedef *store_buf = (KEYSCANStoreReg_Typedef *)StoreBuf;
+
+    RCC_PeriphClockCmd(APBPeriph_KEYSCAN, APBPeriph_KEYSCAN_CLOCK, ENABLE);
+
+    /* Set FSM to idle state */
+    KEYSCAN->KEYSCAN_CONFIG2 &= ~BIT31;
+    KEYSCAN->KEYSCAN_CLK_DIV = store_buf->keyscan_reg[0];
+    KEYSCAN->KEYSCAN_CONFIG2 = (store_buf->keyscan_reg[2] & (~(BIT31)));
+    KEYSCAN->KEYSCAN_CONFIG1 = store_buf->keyscan_reg[1];
+    KEYSCAN->KEYSCAN_COLUMN_CONFIG = store_buf->keyscan_reg[3];
+    KEYSCAN->KEYSCAN_ROW_CONFIG = store_buf->keyscan_reg[4];
+    KEYSCAN->KEYSCAN_INT_MASK = store_buf->keyscan_reg[6];
+    KEYSCAN->KEYSCAN_CONFIG2 |= (store_buf->keyscan_reg[2] & ((BIT31)));
+
+    return;
+}
+
diff --git a/bee/drivers/keyscan/src/device/rtl87x2g/rtl_keyscan.c b/bee/drivers/keyscan/src/device/rtl87x2g/rtl_keyscan.c
new file mode 100644
index 00000000..17df7e7d
--- /dev/null
+++ b/bee/drivers/keyscan/src/device/rtl87x2g/rtl_keyscan.c
@@ -0,0 +1,455 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *                        Header Files
+ *============================================================================*/
+#include "rtl_keyscan.h"
+#include "rtl_rcc.h"
+
+/*============================================================================*
+ *                           Public Functions
+ *============================================================================*/
+/**
+  * \brief  Deinitializes the Keyscan peripheral registers to their default reset values(turn off keyscan clock).
+  * \param  KeyScan: Selected KeyScan peripheral.
+  * \return None
+  */
+void KeyScan_DeInit(KEYSCAN_TypeDef *KeyScan)
+{
+    /* Check the parameters */
+    assert_param(IS_KeyScan_PERIPH(KeyScan));
+
+    RCC_PeriphClockCmd(APBPeriph_KEYSCAN, APBPeriph_KEYSCAN_CLOCK, DISABLE);
+}
+
+/**
+  * \brief  Initializes the KeyScan peripheral according to the specified
+  *         parameters in the KeyScan_InitStruct
+  * \param  KeyScan: Selected KeyScan peripheral.
+  * \param  KeyScan_InitStruct: Pointer to a KEYSCAN_InitTypeDef structure that
+  *         contains the configuration information for the specified KeyScan peripheral
+  * \return None
+  */
+void KeyScan_Init(KEYSCAN_TypeDef *KeyScan, KEYSCAN_InitTypeDef *KeyScan_InitStruct)
+{
+    assert_param(IS_KeyScan_PERIPH(KeyScan));
+    assert_param(IS_KEYSCAN_ROW_NUM(KeyScan_InitStruct->rowSize));
+    assert_param(IS_KEYSCAN_COL_NUM(KeyScan_InitStruct->colSize));
+    assert_param(IS_KEYSCAN_DEBOUNCE_EN(KeyScan_InitStruct->debounceEn));
+    assert_param(IS_KEYSCAN_SCANINTERVAL_EN(KeyScan_InitStruct->scantimerEn));
+    assert_param(IS_KEYSCAN_RELEASE_DETECT_EN(KeyScan_InitStruct->detecttimerEn));
+    assert_param(IS_KEYSCAN_DETECT_MODE(KeyScan_InitStruct->detectMode));
+    assert_param(IS_KEYSCAN_FIFO_OVR_CTRL(KeyScan_InitStruct->fifoOvrCtrl));
+    assert_param(IS_KEYSCAN_SCAN_MODE(KeyScan_InitStruct->scanmode));
+    assert_param(IS_KEYSCAN_KEY_LIMIT(KeyScan_InitStruct->keylimit));
+
+    /* Mask all keyscan interrupt */
+    KeyScan->KEYSCAN_INT_MASK |= 0x1f;
+    /* Set FSM to idle state */
+    KEYSCAN_CONFIG2_TypeDef keyscan_0x08 = {.d32 = KeyScan->KEYSCAN_CONFIG2};
+    keyscan_0x08.b.keyscan_run_enable = 0;
+    keyscan_0x08.b.keyscan_manual_sel = KeyScan_InitStruct->manual_sel;
+    KeyScan->KEYSCAN_CONFIG2 = keyscan_0x08.d32;
+
+    KEYSCAN_CLK_DIV_TypeDef keyscan_0x00 = {.d32 = KeyScan->KEYSCAN_CLK_DIV};
+    KEYSCAN_CONFIG1_TypeDef keyscan_0x04 = {.d32 = KeyScan->KEYSCAN_CONFIG1};
+    KEYSCAN_COLUMN_CONFIG_TypeDef keyscan_0x0c = {.d32 = KeyScan->KEYSCAN_COLUMN_CONFIG};
+    KEYSCAN_ROW_CONFIG_TypeDef keyscan_0x10 = {.d32 = KeyScan->KEYSCAN_ROW_CONFIG};
+    /* Clock divider config */
+    keyscan_0x00.b.keyscan_clk_div = KeyScan_InitStruct->clockdiv;
+    keyscan_0x00.b.keyscan_delay_div = KeyScan_InitStruct->delayclk;
+    /* Config scan mode and detect mode*/
+    keyscan_0x08.b.keyscan_work_mode = KeyScan_InitStruct->scanmode;
+    keyscan_0x08.b.keyscan_trig_sel = KeyScan_InitStruct->detectMode;
+    keyscan_0x08.b.keyscan_fifo_ov_ctrl = KeyScan_InitStruct->fifoOvrCtrl;
+    /* fifo threshol setting */
+    keyscan_0x08.b.keyscan_fifo_th_level = KeyScan_InitStruct->fifotriggerlevel;
+    /* Key limit setting */
+    keyscan_0x08.b.keyscan_fifo_limit = KeyScan_InitStruct->keylimit;
+
+    /* Time config */
+    keyscan_0x04.b.keyscan_deb_timer_en = KeyScan_InitStruct->debounceEn;
+    keyscan_0x04.b.keyscan_interval_timer_en = KeyScan_InitStruct->scantimerEn;
+    keyscan_0x04.b.keyscan_release_timer_en = KeyScan_InitStruct->detecttimerEn;
+    /* Time count config */
+    keyscan_0x04.b.keyscan_deb_timer_cnt = KeyScan_InitStruct->debouncecnt;
+    keyscan_0x04.b.keyscan_interval_timer_cnt = KeyScan_InitStruct->scanInterval;
+    keyscan_0x04.b.keyscan_release_timer_cnt = KeyScan_InitStruct->releasecnt;
+#if KEYSCAN_SUPPORT_ROW_LEVEL_CONFIGURE
+    keyscan_0x04.b.keyscan_row_pull_high_en = KeyScan_InitStruct->rowpullhighEn;
+#endif
+#if KEYSCAN_SUPPORT_COLUNM_LEVEL_CONFIGURE
+    keyscan_0x04.b.keyscan_column_output_high_en = KeyScan_InitStruct->colunmoutputhighEn;
+#endif
+    /* Set col map, config which col to work */
+    keyscan_0x0c.b.keyscan_col_num = KeyScan_InitStruct->colSize - 1;
+    keyscan_0x0c.b.keyscan_col_sel = (1 << KeyScan_InitStruct->colSize) - 1;
+    /* Set col map, config which col to work */
+    keyscan_0x10.b.keyscan_row_num = KeyScan_InitStruct->rowSize - 1;
+    keyscan_0x10.b.keyscan_row_sel = (1 << KeyScan_InitStruct->rowSize) - 1;
+
+    KeyScan->KEYSCAN_CLK_DIV = keyscan_0x00.d32;
+    KeyScan->KEYSCAN_CONFIG2 = keyscan_0x08.d32;
+    KeyScan->KEYSCAN_CONFIG1 = keyscan_0x04.d32;
+    KeyScan->KEYSCAN_COLUMN_CONFIG = keyscan_0x0c.d32;
+    KeyScan->KEYSCAN_ROW_CONFIG = keyscan_0x10.d32;
+    /* Clear all interrupt status and status flag */
+    KeyScan->KEYSCAN_INT_CLR |= 0x1ff;
+    /* Unmask all keyscan interrupt */
+    KeyScan->KEYSCAN_INT_MASK &= ~0x1f;
+    return;
+}
+
+/**
+  * \brief  Fills each I2C_InitStruct member with its default value.
+  * \param  KeyScan_InitStruct: Pointer to a KEYSCAN_InitTypeDef structure which will be initialized.
+  * \return None
+  */
+void KeyScan_StructInit(KEYSCAN_InitTypeDef *KeyScan_InitStruct)
+{
+    KeyScan_InitStruct->colSize          = 2;
+    KeyScan_InitStruct->rowSize          = 2;
+
+    KeyScan_InitStruct->clockdiv         = 0x1f8;
+    KeyScan_InitStruct->delayclk         = 0x01;
+
+    KeyScan_InitStruct->debounceEn       = ENABLE;
+    KeyScan_InitStruct->scantimerEn      = ENABLE;
+    KeyScan_InitStruct->detecttimerEn    = ENABLE;
+
+    KeyScan_InitStruct->debouncecnt      = 0x10;
+    KeyScan_InitStruct->scanInterval     = 0x10;
+    KeyScan_InitStruct->releasecnt       = 0x1;
+
+    KeyScan_InitStruct->scanmode         = KeyScan_Auto_Scan_Mode;
+    KeyScan_InitStruct->detectMode       = KeyScan_Detect_Mode_Level;
+    KeyScan_InitStruct->manual_sel       = KeyScan_Manual_Sel_Key;
+
+    KeyScan_InitStruct->fifotriggerlevel = 1;
+    KeyScan_InitStruct->fifoOvrCtrl      = KeyScan_FIFO_OVR_CTRL_DIS_LAST;
+    KeyScan_InitStruct->keylimit         = 0x03;
+
+#if KEYSCAN_SUPPORT_ROW_LEVEL_CONFIGURE
+    KeyScan_InitStruct->rowpullhighEn    = ENABLE;
+#endif
+#if KEYSCAN_SUPPORT_COLUNM_LEVEL_CONFIGURE
+    KeyScan_InitStruct->colunmoutputhighEn  = DISABLE;
+#endif
+    return;
+}
+
+/**
+  * \brief  Enable or disable the specified KeyScan interrupt.
+  * \param  KeyScan: Selected KeyScan peripheral.
+  * \param  KeyScan_IT: Specifies the KeyScan interrupts sources to be enabled or disabled.
+  *         This parameter can be any combination of the following values:
+  *         \arg KEYSCAN_INT_THRESHOLD: Kescan FIFO data over threshold interrupt.
+  *         \arg KEYSCAN_INT_OVER_READ: KeyScan over read interrupt.
+  *         \arg KEYSCAN_INT_SCAN_END: KeyScan scan end interrupt.
+  *         \arg KEYSCAN_INT_FIFO_NOT_EMPTY: KeyScan FIFO not empty interrupt.
+  *         \arg KEYSCAN_INT_ALL_RELEASE: KeyScan all key release interrupt.
+  * \param  NewState: New state of the specified KeyScan interrupts.
+  *         This parameter can be: ENABLE or DISABLE.
+  * \return None
+  */
+void KeyScan_INTConfig(KEYSCAN_TypeDef *KeyScan, uint32_t KeyScan_IT, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_KeyScan_PERIPH(KeyScan));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+    assert_param(IS_KEYSCAN_CONFIG_IT(KeyScan_IT));
+
+    if (NewState == ENABLE)
+    {
+        /* Enable the selected KeyScan interrupts */
+        KeyScan->KEYSCAN_CONFIG2 |= KeyScan_IT;
+    }
+    else
+    {
+        /* Disable the selected KeyScan interrupts */
+        KeyScan->KEYSCAN_CONFIG2 &= (uint32_t)~KeyScan_IT;
+    }
+}
+
+/**
+  * \brief  Enable or disable the specified KeyScan interrupts mask.
+  * \param  KeyScan: Selected KeyScan peripheral.
+  * \param  NewState: New state of the specified KeyScan interrupts mask.
+  *         This parameter can be: ENABLE or DISABLE.
+  * \return None
+  */
+void KeyScan_INTMask(KEYSCAN_TypeDef *KeyScan, uint32_t KeyScan_IT, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_KeyScan_PERIPH(KeyScan));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (NewState == ENABLE)
+    {
+        /* Mask KeyScan interrupts */
+        KeyScan->KEYSCAN_INT_MASK |= KeyScan_IT;
+    }
+    else
+    {
+        /* Enable KeyScan interrupts */
+        KeyScan->KEYSCAN_INT_MASK &= (~KeyScan_IT);
+    }
+}
+
+/**
+  * \brief  Read data from keyscan FIFO.
+  * \param  KeyScan: selected KeyScan peripheral.
+  * \param  outBuf: buffer to save data read from KeyScan FIFO.
+  * \param  count: number of data to be read.
+  * \return None
+  */
+void KeyScan_Read(KEYSCAN_TypeDef *KeyScan, uint16_t *outBuf, uint16_t count)
+{
+    /* Check the parameters */
+    assert_param(IS_KeyScan_PERIPH(KeyScan));
+
+    uint16_t i = 0;
+
+    for (i = 0; i < count; i++)
+    {
+        *outBuf++ = (uint16_t)KeyScan->KEYSCAN_FIFO_ENTRY;
+    }
+
+    return;
+}
+
+/**
+  * \brief  Enable or disable the KeyScan peripheral.
+  * \param  KeyScan: Selected KeyScan peripheral.
+  * \param  NewState: New state of the KeyScan peripheral.
+  *         This parameter can be: ENABLE or DISABLE.
+  * \return None
+  */
+void KeyScan_Cmd(KEYSCAN_TypeDef *KeyScan, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_KeyScan_PERIPH(KeyScan));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+    KEYSCAN_CONFIG2_TypeDef keyscan_0x08 = {.d32 = KeyScan->KEYSCAN_CONFIG2};
+    keyscan_0x08.b.keyscan_run_enable = NewState;
+    keyscan_0x08.b.keyscan_manual_trigger = NewState && (!keyscan_0x08.b.keyscan_work_mode)
+                                            && (!keyscan_0x08.b.keyscan_manual_sel);
+    KeyScan->KEYSCAN_CONFIG2 = keyscan_0x08.d32;
+}
+
+/**
+  * \brief  Set filter data.
+  * \param  KeyScan: Selected KeyScan peripheral.
+  * \param  data: Config the data to be filtered.
+  *         This parameter should not be more than 9 bits
+  * \param  NewState: New state of the KeyScan peripheral.
+  * \return none.
+  */
+void KeyScan_FilterDataConfig(KEYSCAN_TypeDef *KeyScan, uint16_t data, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_KeyScan_PERIPH(KeyScan));
+
+    if (NewState == ENABLE)
+    {
+        KeyScan->KEYSCAN_CONFIG2 &= ~BIT21;
+
+        KeyScan->KEYSCAN_CONFIG2 &= ~(0x1ff << 12);
+        KeyScan->KEYSCAN_CONFIG2 |= ((data & 0x1ff) << 12);
+
+        KeyScan->KEYSCAN_CONFIG2 |= BIT21;
+    }
+    else
+    {
+        KeyScan->KEYSCAN_CONFIG2 &= ~BIT21;
+
+        KeyScan->KEYSCAN_CONFIG2 &= ~(0x1ff << 12);
+        KeyScan->KEYSCAN_CONFIG2 |= ((data & 0x1ff) << 12);
+    }
+
+    return;
+}
+
+/**
+  * \brief  KeyScan debounce time config.
+  * \param  KeyScan: Selected KeyScan peripheral.
+  * \param  time: Keyscan hardware debounce time.
+  * \param  NewState: New state of the KeyScan debounce function.
+  *         This parameter can be: ENABLE or DISABLE.
+  * \return none.
+  */
+void KeyScan_debounceConfig(KEYSCAN_TypeDef *KeyScan, uint16_t time,
+                            FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_KeyScan_PERIPH(KeyScan));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+    KEYSCAN_CONFIG1_TypeDef keyscan_0x04 = {.d32 = KeyScan->KEYSCAN_CONFIG1};
+    keyscan_0x04.b.keyscan_deb_timer_en = NewState;
+    keyscan_0x04.b.keyscan_deb_timer_cnt = time;
+    KeyScan->KEYSCAN_CONFIG1 = keyscan_0x04.d32;
+}
+
+/**
+  * \brief  Get KeyScan FIFO data num.
+  * \param  KeyScan: Selected KeyScan peripheral.
+  * \return Data length in FIFO.
+  */
+uint16_t KeyScan_GetFifoDataNum(KEYSCAN_TypeDef *KeyScan)
+{
+    assert_param(IS_KeyScan_PERIPH(KeyScan));
+    KEYSCAN_INT_STS_TypeDef keyscan_0x20 = {.d32 = KeyScan->KEYSCAN_INT_STS};
+    return (uint16_t)(keyscan_0x20.b.keyscan_fifo_data_level);
+}
+
+/**
+  * \brief  Clear the KeyScan interrupt pending bit.
+  * \param  KeyScan: Selected KeyScan peripheral.
+  * \param  KeyScan_IT: Specifies the KeyScan interrupts sources to be enabled or disabled.
+  *         This parameter can be any combination of the following values:
+  *         \arg KEYSCAN_INT_THRESHOLD: Kescan FIFO data over threshold interrupt.
+  *         \arg KEYSCAN_INT_OVER_READ: KeyScan over read interrupt.
+  *         \arg KEYSCAN_INT_SCAN_END: KeyScan scan end interrupt.
+  *         \arg KEYSCAN_INT_FIFO_NOT_EMPTY: KeyScan FIFO not empty interrupt.
+  *         \arg KEYSCAN_INT_ALL_RELEASE: KeyScan all key release interrupt.
+  * \return none.
+  */
+void KeyScan_ClearINTPendingBit(KEYSCAN_TypeDef *KeyScan, uint32_t KeyScan_IT)
+{
+    /* Check the parameters */
+    assert_param(IS_KeyScan_PERIPH(KeyScan));
+    assert_param(IS_KEYSCAN_CONFIG_IT(KeyScan_IT));
+
+    KeyScan->KEYSCAN_INT_CLR |= KeyScan_IT;
+
+    return;
+}
+
+/**
+  * \brief  Clear the specified KeyScan flag.
+  * \param  KeyScan: Selected KeyScan peripheral.
+  * \param  KeyScan_FLAG: Specifies the flag to clear.
+  *         This parameter can be any combination of the following values:
+  *         \arg KEYSCAN_FLAG_FIFOLIMIT
+  *         \arg KEYSCAN_FLAG_DATAFILTER
+  *         \arg KEYSCAN_FLAG_OVR
+  * \return none.
+  */
+void KeyScan_ClearFlags(KEYSCAN_TypeDef *KeyScan, uint32_t KeyScan_FLAG)
+{
+    /* Check the parameters */
+    assert_param(IS_KeyScan_PERIPH(KeyScan));
+    assert_param(IS_KEYSCAN_CLEAR_FLAG(KeyScan_FLAG));
+    KEYSCAN_INT_CLR_TypeDef keyscan_0x1c = {.d32 = KeyScan->KEYSCAN_INT_CLR};
+    if (KeyScan_FLAG & KEYSCAN_FLAG_FIFOLIMIT)
+    {
+        keyscan_0x1c.b.keyscan_fifo_limit_st_clr = 0x01;
+    }
+    if (KeyScan_FLAG & KEYSCAN_FLAG_DATAFILTER)
+    {
+        keyscan_0x1c.b.keyscan_fifo_datafilter_st_clr = 0x01;
+    }
+    if (KeyScan_FLAG & KEYSCAN_FLAG_OVR)
+    {
+        keyscan_0x1c.b.keyscan_fifo_ov_st_clr = 0x01;
+    }
+    KeyScan->KEYSCAN_INT_CLR = keyscan_0x1c.d32;
+    return;
+}
+
+/**
+  * \brief  Check whether the specified KeyScan flag is set.
+  * \param  KeyScan: Selected KeyScan peripheral.
+  * \param  KeyScan_FLAG: Specifies the flag to clear.
+  *         This parameter can be any combination of the following values:
+  *         \arg KEYSCAN_FLAG_FIFOLIMIT:
+  *         \arg KEYSCAN_FLAG_THRESHOLD:
+  *         \arg KEYSCAN_FLAG_OVER_READ:
+  *         \arg KEYSCAN_FLAG_SCAN_END:
+  *         \arg KEYSCAN_FLAG_FIFO_NOT_EMPTY:
+  *         \arg KEYSCAN_FLAG_ALL_RELEASE:
+  *         \arg KEYSCAN_FLAG_DATAFILTER:
+  *         \arg KEYSCAN_FLAG_OVR:
+  *         \arg KEYSCAN_FLAG_FULL:
+  *         \arg KEYSCAN_FLAG_EMPTY:
+  * \return none.
+  */
+FlagStatus KeyScan_GetFlagState(KEYSCAN_TypeDef *KeyScan, uint32_t KeyScan_FLAG)
+{
+    FlagStatus bitstatus = RESET;
+
+    /* Check the parameters */
+    assert_param(IS_KeyScan_PERIPH(KeyScan));
+    assert_param(IS_KEYSCAN_FLAG(KeyScan_FLAG));
+
+    if ((KeyScan->KEYSCAN_INT_STS & KeyScan_FLAG) != 0)
+    {
+        bitstatus = SET;
+    }
+
+    return bitstatus;
+}
+
+/**
+  * \brief  Read FIFO data.
+  * \param  KeyScan: Selected KeyScan peripheral.
+  * \return Keyscan FIFO data.
+  */
+uint16_t KeyScan_ReadFifoData(KEYSCAN_TypeDef *KeyScan)
+{
+    /* Check the parameters */
+    assert_param(IS_KeyScan_PERIPH(KeyScan));
+
+    return (uint16_t)(KeyScan->KEYSCAN_FIFO_ENTRY);
+}
+#if (KEYSCAN_SUPPORT_RAP_FUNCTION == 1)
+void KeyScan_RAPModeCmd(KEYSCAN_TypeDef *KeyScan, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_KeyScan_PERIPH(KeyScan));
+
+    KEYSCAN_TASK_CTRL_TypeDef keyscan_0x38 = {.d32 = KeyScan->KEYSCAN_TASK_CTRL};
+    keyscan_0x38.b.rap_mode = NewState;
+    KeyScan->KEYSCAN_TASK_CTRL = keyscan_0x38.d32;
+
+    return;
+}
+
+void KEYSCAN_TaskTrigger(KEYSCAN_TypeDef *KeyScan, uint32_t Task)
+{
+    /* Check the parameters */
+    assert_param(IS_ADC_ALL_PERIPH(KeyScan));
+
+    KEYSCAN_TASK_CTRL_TypeDef keyscan_0x38 = {.d32 = KeyScan->KEYSCAN_TASK_CTRL};
+    if (Task == KEYSCAN_TASK_MANUAL)
+    {
+        keyscan_0x38.b.task_manual = 0x1;
+    }
+    KeyScan->KEYSCAN_TASK_CTRL = keyscan_0x38.d32;
+
+    return;
+}
+
+void KeyScan_RAPQactiveCtrl(KEYSCAN_TypeDef *KeyScan, uint32_t Qactive, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_ADC_ALL_PERIPH(KeyScan));
+
+    KEYSCAN_QACTIVE_CTRL_TypeDef keyscan_0x3C = {.d32 = KeyScan->KEYSCAN_QACTIVE_CTRL};
+    if (Qactive == KEYSCAN_QACTIVE_FW_FORCE)
+    {
+        keyscan_0x3C.b.qact_clk_force_en = NewState;
+    }
+    if (Qactive == KEYSCAN_QACTIVE_FW_FORCE_PCLK)
+    {
+        keyscan_0x3C.b.qact_pclk_force_en = NewState;
+    }
+    KeyScan->KEYSCAN_QACTIVE_CTRL = keyscan_0x3C.d32;
+
+    return;
+}
+#endif
diff --git a/bee/drivers/keyscan/src/device/rtl87x2g/rtl_keyscan.h b/bee/drivers/keyscan/src/device/rtl87x2g/rtl_keyscan.h
new file mode 100644
index 00000000..1f609da7
--- /dev/null
+++ b/bee/drivers/keyscan/src/device/rtl87x2g/rtl_keyscan.h
@@ -0,0 +1,730 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *               Define to prevent recursive inclusion
+ *============================================================================*/
+#ifndef RTL_KEYSCAN_H
+#define RTL_KEYSCAN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*============================================================================*
+ *                        Header Files
+ *============================================================================*/
+#include "utils/rtl_utils.h"
+#include "rtl_keyscan_def.h"
+
+/** \defgroup KEYSCAN     KEYSCAN
+  * \brief
+  * \{
+  */
+
+/*============================================================================*
+ *                         Constants
+ *============================================================================*/
+/** \defgroup KEYSCAN_Exported_Constants KEYSCAN Exported Constants
+  * \brief
+  * \{
+  */
+
+/**
+ * \defgroup    KEYSCAN_FIFO_Depth KEYSCAN FIFO Depth
+ * \{
+ * \ingroup     KEYSCAN_Exported_Constants
+ */
+#define KEYSCAN_FIFO_DEPTH              26   //!< The FIFO depth of the KEYSCAN is 26.
+
+/** End of KEYSCAN_FIFO_Depth
+  * \}
+  */
+
+/**
+ * \defgroup    KEYSCAN_Row_Number KEYSCAN Row Number
+ * \{
+ * \ingroup     KEYSCAN_Exported_Constants
+ */
+#define IS_KEYSCAN_ROW_NUM(ROW) ((ROW) <= 12)   //!< The row number of the KEYSCAN need less than or equal to 12.
+
+/** End of KEYSCAN_Row_Number
+  * \}
+  */
+
+/**
+ * \defgroup    KEYSCAN_Column_Number KEYSCAN Column Number
+ * \{
+ * \ingroup     KEYSCAN_Exported_Constants
+ */
+#define IS_KEYSCAN_COL_NUM(COL) ((COL) <= 20)   //!< The column number of the KEYSCAN need less than or equal to 20.
+
+/** End of KEYSCAN_Column_Number
+  * \}
+  */
+
+/**
+ * \defgroup    KEYSCAN_Debounce_Config KEYSCAN Debounce Config
+ * \{
+ * \ingroup     KEYSCAN_Exported_Constants
+ */
+#define IS_KEYSCAN_DEBOUNCE_EN(EN) (((EN) == ENABLE) || ((EN) == DISABLE))   //!< The debounce config of the KEYSCAN can be ENABLE or DISABLE  
+
+/** End of KEYSCAN_Debounce_Config
+  * \}
+  */
+
+/**
+ * \defgroup    KEYSCAN_Scan_Interval_Enable KEYSCAN Scan Interval Enable
+ * \{
+ * \ingroup     KEYSCAN_Exported_Constants
+ */
+#define IS_KEYSCAN_SCANINTERVAL_EN(EN) (((EN) == ENABLE) || ((EN) == DISABLE))   //!< The scan interval of the KEYSCAN can be ENABLE or DISABLE
+
+/** End of KEYSCAN_Scan_Interval_Enable
+  * \}
+  */
+
+/**
+ * \defgroup    KEYSCAN_Release_Detect_Timer_Enable KEYSCAN Release Detect Timer Enable
+ * \{
+ * \ingroup     KEYSCAN_Exported_Constants
+ */
+#define IS_KEYSCAN_RELEASE_DETECT_EN(EN) (((EN) == ENABLE) || ((EN) == DISABLE))   //!< The release detect timer of the KEYSCAN can be ENABLE or DISABLE
+
+/** End of KEYSCAN_Release_Detect_Timer_Enable
+  * \}
+  */
+
+/**
+ * \defgroup    KEYSCAN_Scan_Mode KEYSCAN Scan Mode
+ * \{
+ * \ingroup     KEYSCAN_Exported_Constants
+ */
+typedef enum
+{
+    KeyScan_Manual_Scan_Mode = 0x00,   //!< The KEYSCAN manual scan mode.
+    KeyScan_Auto_Scan_Mode = 0x01,     //!< The KEYSCAN auto scan mode.
+} KEYSCANScanMode_TypeDef;
+
+#define IS_KEYSCAN_SCAN_MODE(MODE)  (((MODE) == KeyScan_Manual_Scan_Mode) || ((MODE) == KeyScan_Auto_Scan_Mode)) //!< Check if the input parameter is valid.
+
+/** End of KEYSCAN_Scan_Mode
+  * \}
+  */
+
+/**
+ * \defgroup    KEYSCAN_Press_Detect_Mode KEYSCAN Press Detect Mode
+ * \{
+ * \ingroup     KEYSCAN_Exported_Constants
+ */
+typedef enum
+{
+    KeyScan_Detect_Mode_Edge = 0x00,    //!< The key detection mode is edge-triggered.
+    KeyScan_Detect_Mode_Level = 0x01,   //!< The key detection mode is level-triggered.
+} KEYSCANPressDetectMode_TypeDef;
+
+#define IS_KEYSCAN_DETECT_MODE(MODE)    (((MODE) == KeyScan_Detect_Mode_Edge) || ((MODE) == KeyScan_Detect_Mode_Level)) //!< Check if the input parameter is valid.
+
+/** End of KEYSCAN_Press_Detect_Mode
+  * \}
+  */
+
+/**
+ * \defgroup    KEYSCAN_FIFO_Overflow_Control KEYSCAN FIFO Overflow Control
+ * \{
+ * \ingroup     KEYSCAN_Exported_Constants
+ */
+typedef enum
+{
+    KeyScan_FIFO_OVR_CTRL_DIS_ALL = 0x00,     //!< Discard the new scan data when FIFO is full.
+    KeyScan_FIFO_OVR_CTRL_DIS_LAST = 0x01,    //!< Discard the oldest scan data when FIFO is full.
+} KEYSCANFifoOverflowControl_TypeDef;
+
+#define IS_KEYSCAN_FIFO_OVR_CTRL(CTRL)  (((CTRL) == KeyScan_FIFO_OVR_CTRL_DIS_ALL) || ((CTRL) == KeyScan_FIFO_OVR_CTRL_DIS_LAST)) //!< Check if the input parameter is valid.
+
+/** End of KEYSCAN_FIFO_Overflow_Control
+  * \}
+  */
+
+/**
+ * \defgroup    KEYSCAN_Manual_Sel_Mode KEYSCAN Manual Sel Mode
+ * \{
+ * \ingroup     KEYSCAN_Exported_Constants
+ */
+typedef enum
+{
+    KeyScan_Manual_Sel_Bit = 0x00,     //!< KEYSCAN manual trigger register (Call API Keyscan_Cmd)
+    KeyScan_Manual_Sel_Key = 0x01,     //!< KEYSCAN manual trigger by key.
+} KEYSCANManualMode_TypeDef;
+
+/** End of KEYSCAN_Manual_Sel_Mode
+  * \}
+  */
+
+#if (KEYSCAN_SUPPORT_RAP_FUNCTION == 1)
+/**
+ * \defgroup    KEYSCAN_Qactive_Force KEYSCAN Qactive Force
+ * \{
+ * \ingroup     KEYSCAN_Exported_Constants
+ */
+typedef enum
+{
+    KEYSCAN_QACTIVE_FW_FORCE = 0x0,
+    KEYSCAN_QACTIVE_FW_FORCE_PCLK = 0x1,
+} KeyScanQactiveForce_TypeDef;
+
+/** End of KEYSCAN_Qactive_Force
+  * \}
+  */
+
+/**
+ * \defgroup    KEYSCAN_Task KEYSCAN Task
+ * \{
+ * \ingroup     KEYSCAN_Exported_Constants
+ */
+typedef enum
+{
+    KEYSCAN_TASK_MANUAL = 0,
+} KEYSCANTask_TypeDef;
+
+/** End of KEYSCAN_Task
+  * \}
+  */
+#endif
+
+/**
+ * \defgroup    KEYSCAN_Key_Limit KEYSCAN Key Limit
+ * \{
+ * \ingroup     KEYSCAN_Exported_Constants
+ */
+#define IS_KEYSCAN_KEY_LIMIT(DATA_NUM) ((DATA_NUM) <= KEYSCAN_FIFO_DEPTH) //!< The key limit of the KEYSCAN need less than or equal to KEYSCAN_FIFO_DEPTH.
+
+/** End of KEYSCAN_Key_Limit
+  * \}
+  */
+
+/**
+ * \defgroup    KEYSCAN_Interrupt KEYSCAN Interrupt
+ * \{
+ * \ingroup     KEYSCAN_Exported_Constants
+ */
+#define KEYSCAN_INT_THRESHOLD                    BIT4     //!< KEYSCAN FIFO data over threshold interrupt.
+#define KEYSCAN_INT_OVER_READ                    BIT3     //!< KEYSCAN over read interrupt.
+#define KEYSCAN_INT_SCAN_END                     BIT2     //!< KEYSCAN scan end interrupt.
+#define KEYSCAN_INT_FIFO_NOT_EMPTY               BIT1     //!< KEYSCAN FIFO not empty interrupt.
+#define KEYSCAN_INT_ALL_RELEASE                  BIT0     //!< KEYSCAN all key release interrupt.
+#define IS_KEYSCAN_CONFIG_IT(IT) ((((IT) & (uint32_t)0xFFF8) == 0x00) && ((IT) != 0x00))     //!< KEYSCAN all interrupt configurations.
+
+/** End of KEYSCAN_Interrupt
+  * \}
+  */
+
+/**
+ * \defgroup    KEYSCAN_Flag KEYSCAN Flag
+ * \{
+ * \ingroup     KEYSCAN_Exported_Constants
+ */
+#define KEYSCAN_FLAG_FIFOLIMIT                       BIT20     //!< When data filtering occurs, this bit will be set to 1.
+#define KEYSCAN_INT_FLAG_THRESHOLD                   BIT19     //!< FIFO threshold interrupt status.
+#define KEYSCAN_INT_FLAG_OVER_READ                   BIT18     //!< FIFO over read interrupt status.
+#define KEYSCAN_INT_FLAG_SCAN_END                    BIT17     //!< Scan finish interrupt status.
+#define KEYSCAN_INT_FLAG_FIFO_NOT_EMPTY              BIT16     //!< FIFO not empty interrupt status.
+#define KEYSCAN_INT_FLAG_ALL_RELEASE                 BIT15     //!< All release interrupt status.
+#define KEYSCAN_FLAG_DATAFILTER                      BIT3      //!< FIFO data filter status.
+#define KEYSCAN_FLAG_OVR                             BIT2      //!< FIFO overflow status.
+#define KEYSCAN_FLAG_FULL                            BIT1      //!< FIFO full status.
+#define KEYSCAN_FLAG_EMPTY                           BIT0      //!< FIFO empty status.
+#define IS_KEYSCAN_FLAG(FLAG)       ((((FLAG) & (uint32_t)0x01FF) == 0x00) && ((FLAG) != (uint32_t)0x00))     //!< KEYSCAN all interrupt flags.
+#define IS_KEYSCAN_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0x00C0) == 0x00) && ((FLAG) != (uint32_t)0x00))     //!< KEYSCAN all clear flags.
+
+/** End of KEYSCAN_Flag
+  * \}
+  */
+
+/** End of KEYSCAN_Exported_Constants
+  * \}
+  */
+
+/*============================================================================*
+ *                         Types
+ *============================================================================*/
+/** \defgroup KEYSCAN_Exported_Types KEYSCAN Exported Types
+  * \brief
+  * \{
+  */
+
+/**
+ * \brief       KEYSCAN initialize parameters
+ *
+ * \ingroup     KEYSCAN_Exported_Types
+ */
+typedef struct
+{
+    uint16_t rowSize;                               /*!< Specify KEYSCAN Row Size.
+                                                         This parameter can be set to a value of 12 or less. */
+
+    uint16_t colSize;                               /*!< Specify KEYSCAN Column Size.
+                                                         This parameter can be set to a value of 20 or less. */
+
+    uint16_t clockdiv;                              /*!< Specify KEYSCAN clock divider.
+                                                         scan clock = system clock/(SCAN_DIV+1). */
+
+    uint8_t delayclk;                               /*!< Specify KEYSCAN delay clock divider.
+                                                         delay clock = scan clock/(delayclk+1). */
+
+    FunctionalState debounceEn;                     /*!< Enable or disable debounce.
+                                                         This parameter can be a value of DISABLE or ENABLE. */
+
+    FunctionalState scantimerEn;                    /*!< Enable or disable scan timer.
+                                                         This parameter can be a value of DISABLE or ENABLE. */
+
+    FunctionalState detecttimerEn;                  /*!< Enable or disable detect timer.
+                                                         This parameter can be a value of DISABLE or ENABLE. */
+
+    uint16_t debouncecnt;                           /*!< Specify KEYSCAN debounce timer.
+                                                         debounce time = delay clock * debouncecnt.
+                                                         This parameter can be a value of 0 ~ 0x1FF. */
+
+    uint16_t scanInterval;                          /*!< Specify KEYSCAN scan interval.
+                                                         scan interval time = delay clock * scanInterval.
+                                                         This parameter can be a value of 0 ~ 0x1FF. */
+
+    uint16_t releasecnt;                            /*!< Specify KEYSCAN release time.
+                                                         release time = delay clock * releasecnt.
+                                                         This parameter can be a value of 0 ~ 0x1FF. */
+
+    KEYSCANScanMode_TypeDef scanmode;               /*!< Specify KEYSCAN scan mode.
+                                                         This parameter can be a value of \ref KEYSCAN_Scan_Mode. */
+
+    KEYSCANPressDetectMode_TypeDef detectMode;      /*!< Specify key detection mode of KEYSCAN.
+                                                         This parameter can be a value of \ref KEYSCAN_Press_Detect_Mode. */
+
+    uint16_t fifotriggerlevel;                      /*!< Specify KEYSCAN FIFO threshold to trigger interrupt.
+                                                         This parameter can be a value of 0 ~ 26. */
+
+    KEYSCANFifoOverflowControl_TypeDef
+    fifoOvrCtrl;                                    /*!< Specify KEYSCAN fifo over flow control.
+                                                         This parameter can be a value of \ref KEYSCAN_FIFO_Overflow_Control. */
+
+    uint8_t keylimit;                               /*!< Specify the maximum allowable scan data for each scan.
+                                                         This parameter can be a value of 0 ~ 26. */
+
+    KEYSCANManualMode_TypeDef
+    manual_sel;                                     /*!< Specify trigger mode in manual scan mode.
+                                                         This parameter can be a value of \ref KEYSCAN_Manual_Sel_Mode. */
+
+#if KEYSCAN_SUPPORT_ROW_LEVEL_CONFIGURE
+    FunctionalState
+    rowpullhighEn;                  /*!< Enable or disable the function of row pull high.
+                                                         This parameter can be a value of DISABLE or ENABLE. */
+#endif
+#if KEYSCAN_SUPPORT_COLUNM_LEVEL_CONFIGURE
+    FunctionalState colunmoutputhighEn;
+#endif
+} KEYSCAN_InitTypeDef;
+
+/** End of KEYSCAN_Exported_Types
+  * \}
+  */
+
+/*============================================================================*
+ *                         Functions
+ *============================================================================*/
+/** \defgroup KEYSCAN_Exported_Functions KEYSCAN Exported Functions
+  * \brief
+  * \{
+  */
+
+/**
+ * \brief  Deinitialize the KEYSCAN peripheral registers to their default reset values(turn off keyscan clock).
+ *
+ * \param[in]  KeyScan  Select KeyScan peripheral. Refer to \ref KEYSCAN_Declaration.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_keyscan_init(void)
+ * {
+ *     KeyScan_DeInit(KEYSCAN);
+ * }
+ * \endcode
+ */
+void KeyScan_DeInit(KEYSCAN_TypeDef *KeyScan);
+
+/**
+ * \brief   Initialize the KeyScan peripheral according to the specified
+ *          parameters in the KeyScan_InitStruct
+ *
+ * \param[in]  KeyScan             Select KeyScan peripheral. Refer to \ref KEYSCAN_Declaration.
+ * \param[in]  KeyScan_InitStruct  Pointer to a KEYSCAN_InitTypeDef structure which will be initialized.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_keyscan_init(void)
+ * {
+ *     RCC_PeriphClockCmd(APBPeriph_KEYSCAN, APBPeriph_KEYSCAN_CLOCK, ENABLE);
+
+ *     KEYSCAN_InitTypeDef KEYSCAN_InitStruct;
+ *     KeyScan_StructInit(&KEYSCAN_InitStruct);
+
+ *     KEYSCAN_InitStruct.rowSize  = KEYBOARD_ROW_SIZE;
+ *     KEYSCAN_InitStruct.colSize  = KEYBOARD_COLUMN_SIZE;
+ *     KEYSCAN_InitStruct.scanmode     = KeyScan_Manual_Scan_Mode;
+ *     KEYSCAN_InitStruct.debounceEn   = KeyScan_Debounce_Enable;
+
+ *     KeyScan_Init(KEYSCAN, &KEYSCAN_InitStruct);
+
+ *     KeyScan_INTConfig(KEYSCAN, KEYSCAN_INT_SCAN_END, ENABLE);
+ *     KeyScan_ClearINTPendingBit(KEYSCAN, KEYSCAN_INT_SCAN_END);
+ *     KeyScan_INTMask(KEYSCAN, KEYSCAN_INT_SCAN_END, DISABLE);  // Unmask keyscan interrupt
+ *     KeyScan_Cmd(KEYSCAN, ENABLE);
+ * }
+ * \endcode
+ */
+void KeyScan_Init(KEYSCAN_TypeDef *KeyScan, KEYSCAN_InitTypeDef *KeyScan_InitStruct);
+
+/**
+ * \brief  Fill each KEYSCAN_InitStruct member with its default value.
+ *
+ * \note The default settings for the KeyScan_InitStruct member are shown in the following table:
+ *       | KeyScan_InitStruct member    | Default value                        |
+ *       |:----------------------------:|:------------------------------------:|
+ *       | colSize                      | 2                                    |
+ *       | rowSize                      | 2                                    |
+ *       | clockdiv                     | 0x1f8                                |
+ *       | delayclk                     | 0x01                                 |
+ *       | debounceEn                   | ENABLE                               |
+ *       | scantimerEn                  | ENABLE                               |
+ *       | detecttimerEn                | ENABLE                               |
+ *       | debouncecnt                  | 0x10                                 |
+ *       | scanInterval                 | 0x10                                 |
+ *       | releasecnt                   | 0x1                                  |
+ *       | scanmode                     | \ref KeyScan_Auto_Scan_Mode          |
+ *       | detectMode                   | \ref KeyScan_Detect_Mode_Level       |
+ *       | manual_sel                   | \ref KeyScan_Manual_Sel_Key          |
+ *       | fifotriggerlevel             | 1                                    |
+ *       | fifoOvrCtrl                  | \ref KeyScan_FIFO_OVR_CTRL_DIS_LAST  |
+ *       | keylimit                     | 0x03                                 |
+ *       | rowpullhighEn                | ENABLE                               |
+ *
+ * \param[in] KeyScan_InitStruct  Pointer to a KEYSCAN_InitTypeDef structure which will be initialized.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_keyscan_init(void)
+ * {
+ *     RCC_PeriphClockCmd(APBPeriph_KEYSCAN, APBPeriph_KEYSCAN_CLOCK, ENABLE);
+
+ *     KEYSCAN_InitTypeDef KEYSCAN_InitStruct;
+ *     KeyScan_StructInit(&KEYSCAN_InitStruct);
+
+ *     KEYSCAN_InitStruct.rowSize  = KEYBOARD_ROW_SIZE;
+ *     KEYSCAN_InitStruct.colSize  = KEYBOARD_COLUMN_SIZE;
+ *     KEYSCAN_InitStruct.scanmode     = KeyScan_Manual_Scan_Mode;
+ *     KEYSCAN_InitStruct.debounceEn   = KeyScan_Debounce_Enable;
+
+ *     KeyScan_Init(KEYSCAN, &KEYSCAN_InitStruct);
+
+ *     KeyScan_INTConfig(KEYSCAN, KEYSCAN_INT_SCAN_END, ENABLE);
+ *     KeyScan_ClearINTPendingBit(KEYSCAN, KEYSCAN_INT_SCAN_END);
+ *     KeyScan_INTMask(KEYSCAN, KEYSCAN_INT_SCAN_END, DISABLE);  // Unmask keyscan interrupt
+ *     KeyScan_Cmd(KEYSCAN, ENABLE);
+ * }
+ * \endcode
+ */
+void KeyScan_StructInit(KEYSCAN_InitTypeDef *KeyScan_InitStruct);
+
+/**
+ * \brief  Enable or disable the specified KeyScan interrupt.
+ *
+ * \param[in] KeyScan     Select KeyScan peripheral. Refer to \ref KEYSCAN_Declaration.
+ * \param[in] KeyScan_IT  Specify the KeyScan interrupts sources to be enabled or disabled. Refer to \ref KEYSCAN_Interrupt.
+ *                        This parameter can be any combination of the following values:
+ *                        \arg KEYSCAN_INT_THRESHOLD: Keyscan FIFO data over threshold interrupt.
+ *                        \arg KEYSCAN_INT_OVER_READ: KeyScan over read interrupt.
+ *                        \arg KEYSCAN_INT_SCAN_END: KeyScan scan end interrupt.
+ *                        \arg KEYSCAN_INT_FIFO_NOT_EMPTY: KeyScan FIFO not empty interrupt.
+ *                        \arg KEYSCAN_INT_ALL_RELEASE: KeyScan all key release interrupt.
+ * \param[in] NewState    New state of the specified KeyScan interrupts.
+ *                        This parameter can be one of the following values:
+ *                        - ENABLE: Enable the interrupt of KeyScan.
+ *                        - DISABLE: Disable the interrupt of KeyScan.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void keyscan_demo(void)
+ * {
+ *     KeyScan_INTMask(KEYSCAN, KEYSCAN_INT_SCAN_END, ENABLE);
+ *     KeyScan_INTConfig(KEYSCAN, KEYSCAN_INT_SCAN_END, ENABLE);
+ *     KeyScan_INTMask(KEYSCAN, KEYSCAN_INT_SCAN_END, DISABLE);
+ * }
+ * \endcode
+ */
+void KeyScan_INTConfig(KEYSCAN_TypeDef *KeyScan, uint32_t KeyScan_IT,
+                       FunctionalState NewState);
+
+/**
+ * \brief  Mask the specified KeyScan interrupt.
+ *
+ * \param[in] KeyScan     Select KeyScan peripheral. Refer to \ref KEYSCAN_Declaration.
+ * \param[in] KeyScan_IT  Specify the KeyScan interrupts sources to be enabled or disabled. Refer to \ref KEYSCAN_Interrupt.
+ *                        This parameter can be any combination of the following values:
+ *                        \arg KEYSCAN_INT_THRESHOLD: Keyscan FIFO data over threshold interrupt.
+ *                        \arg KEYSCAN_INT_OVER_READ: KeyScan over read interrupt.
+ *                        \arg KEYSCAN_INT_SCAN_END: KeyScan scan end interrupt.
+ *                        \arg KEYSCAN_INT_FIFO_NOT_EMPTY: KeyScan FIFO not empty interrupt.
+ *                        \arg KEYSCAN_INT_ALL_RELEASE: KeyScan all key release interrupt.
+ * \param[in] NewState    New state of the specified KeyScan interrupt mask.
+ *                        This parameter can be one of the following values:
+ *                        - ENABLE: Enable the interrupt mask of KeyScan.
+ *                        - DISABLE: Disable the interrupt mask of KeyScan.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void keyscan_demo(void)
+ * {
+ *     KeyScan_INTMask(KEYSCAN, KEYSCAN_INT_SCAN_END, ENABLE);
+ * }
+ * \endcode
+ */
+void KeyScan_INTMask(KEYSCAN_TypeDef *KeyScan, uint32_t KeyScan_IT,
+                     FunctionalState NewState);
+
+/**
+ * \brief  Read data from keyscan FIFO.
+ *
+ * \param[in]  KeyScan  Select KeyScan peripheral. Refer to \ref KEYSCAN_Declaration.
+ * \param[out] outBuf   Buffer to save data read from KeyScan FIFO.
+ * \param[in]  count    Data length to be read.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void keyscan_demo(void)
+ * {
+ *     uint16_t data[3] = {0};
+ *     KeyScan_Read(KEYSCAN, data, 3);
+ * }
+ * \endcode
+ */
+void KeyScan_Read(KEYSCAN_TypeDef *KeyScan, uint16_t *outBuf, uint16_t count);
+
+/**
+ * \brief   Enable or disable the KeyScan peripheral.
+ *
+ * \param[in] KeyScan   Select KeyScan peripheral. Refer to \ref KEYSCAN_Declaration.
+ * \param[in] NewState  New state of the KeyScan peripheral.
+ *                      This parameter can be one of the following values:
+ *                      - ENABLE: Enable KEYSCAN scanning. When an external key is pressed,
+ *                        it will trigger the keyscan scanning. When configured in manual scan mode and bit trigger,
+ *                        calling this API will immediately execute the keyscan scanning.
+ *                      - DISABLE: Disable KEYSCAN scanning.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void keyscan_demo(void)
+ * {
+ *     KeyScan_Cmd(KEYSCAN, ENABLE);
+ * }
+ * \endcode
+ */
+void KeyScan_Cmd(KEYSCAN_TypeDef *KeyScan, FunctionalState NewState);
+
+/**
+ * \brief   Set filter data.
+ *
+ * \param[in] KeyScan   Select KeyScan peripheral. Refer to \ref KEYSCAN_Declaration.
+ * \param[in] data      Config the data to be filtered.
+ *                      This parameter should not be more than 9 bits.
+ * \param[in] NewState  New state of the KeyScan filtering.
+ *                      This parameter can be one of the following values:
+ *                      - ENABLE: Enable data filtering.
+ *                      - DISABLE: Disable data filtering.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void keyscan_demo(void)
+ * {
+ *     KeyScan_FilterDataConfig(KEYSCAN, 0x01, ENABLE);
+ *
+ * }
+ * \endcode
+ */
+void KeyScan_FilterDataConfig(KEYSCAN_TypeDef *KeyScan, uint16_t data,
+                              FunctionalState NewState);
+
+/**
+ * \brief   KeyScan debounce time config.
+ *
+ * \param[in] KeyScan   Select KeyScan peripheral. Refer to \ref KEYSCAN_Declaration.
+ * \param[in] time      KEYSCAN hardware debounce time. debounce time = delay clock * time.
+ * \param[in] NewState  New state of the KeyScan debounce function.
+ *                      This parameter can be one of the following values:
+ *                      - ENABLE: Enable KeyScan debounce function.
+ *                      - DISABLE: Disable KeyScan debounce function.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void keyscan_demo(void)
+ * {
+ *     KeyScan_debounceConfig(KEYSCAN, 10, ENABLE);
+ *
+ * }
+ * \endcode
+ */
+void KeyScan_debounceConfig(KEYSCAN_TypeDef *KeyScan, uint16_t time,
+                            FunctionalState NewState);
+
+/**
+ * \brief   Get KeyScan FIFO data num.
+ *
+ * \param[in]  KeyScan  Select KeyScan peripheral. Refer to \ref KEYSCAN_Declaration.
+ *
+ * \return  Data length in FIFO.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void keyscan_demo(void)
+ * {
+ *     uint16_t data_len = KeyScan_GetFifoDataNum(KEYSCAN);
+ * }
+ * \endcode
+ */
+uint16_t KeyScan_GetFifoDataNum(KEYSCAN_TypeDef *KeyScan);
+
+/**
+ * \brief  Clear the KeyScan interrupt pending bit.
+ *
+ * \param[in] KeyScan     Select KeyScan peripheral. Refer to \ref KEYSCAN_Declaration.
+ * \param[in] KeyScan_IT  Specify the interrupt pending bit to clear. Refer to \ref KEYSCAN_Interrupt.
+ *                        This parameter can be any combination of the following values:
+ *                        - KEYSCAN_INT_THRESHOLD: Keyscan FIFO data over threshold interrupt.
+ *                        - KEYSCAN_INT_OVER_READ: KeyScan over read interrupt.
+ *                        - KEYSCAN_INT_SCAN_END: KeyScan scan end interrupt.
+ *                        - KEYSCAN_INT_FIFO_NOT_EMPTY: KeyScan FIFO not empty interrupt.
+ *                        - KEYSCAN_INT_ALL_RELEASE: KeyScan all key release interrupt.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void keyscan_demo(void)
+ * {
+ *     KeyScan_ClearINTPendingBit(KEYSCAN, KEYSCAN_INT_SCAN_END);
+ * }
+ * \endcode
+ */
+void KeyScan_ClearINTPendingBit(KEYSCAN_TypeDef *KeyScan, uint32_t KeyScan_IT);
+
+/**
+ * \brief   Clear the specified KeyScan flag.
+ *
+ * \param[in] KeyScan       Select KeyScan peripheral. Refer to \ref KEYSCAN_Declaration.
+ * \param[in] KeyScan_FLAG  Specify the flag to clear.
+ *                          This parameter can be one of the following values, refer to \ref KEYSCAN_Flag.
+ *                          \arg KEYSCAN_FLAG_FIFOLIMIT: When data filtering occurs, this bit will be set to 1.
+ *                          \arg KEYSCAN_FLAG_DATAFILTER: FIFO data filter status.
+ *                          \arg KEYSCAN_FLAG_OVR: FIFO overflow status.
+ *
+ * \note    KEYSCAN_FLAG_FULL and KEYSCAN_FLAG_EMPTY can't be cleared manually.
+ *          They are cleared by hardware automatically.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void keyscan_demo(void)
+ * {
+ *     KeyScan_ClearFlags(KEYSCAN, KEYSCAN_FLAG_FIFOLIMIT);
+ * }
+ * \endcode
+ */
+void KeyScan_ClearFlags(KEYSCAN_TypeDef *KeyScan, uint32_t KeyScan_FLAG);
+
+/**
+ * \brief   Get the specified KeyScan flag status.
+ *
+ * \param[in] KeyScan       Select KeyScan peripheral. Refer to \ref KEYSCAN_Declaration.
+ * \param[in] KeyScan_FLAG  Specify the flag to check.
+ *                          This parameter can be one of the following values, refer to \ref KEYSCAN_Flag.
+ *                          \arg KEYSCAN_FLAG_FIFOLIMIT: When data filtering occurs, this bit will be set to 1.
+ *                          \arg KEYSCAN_FLAG_THRESHOLD: FIFO threshold interrupt status.
+ *                          \arg KEYSCAN_FLAG_OVER_READ: FIFO over read interrupt status.
+ *                          \arg KEYSCAN_FLAG_SCAN_END: Scan finish interrupt status.
+ *                          \arg KEYSCAN_FLAG_FIFO_NOT_EMPTY: FIFO not empty interrupt status.
+ *                          \arg KEYSCAN_FLAG_ALL_RELEASE: All release interrupt status.
+ *                          \arg KEYSCAN_FLAG_DATAFILTER: FIFO data filter status.
+ *                          \arg KEYSCAN_FLAG_OVR: FIFO overflow status.
+ *                          \arg KEYSCAN_FLAG_FULL: FIFO full status.
+ *                          \arg KEYSCAN_FLAG_EMPTY: FIFO empty status.
+ *
+ * \return  The status of KeyScan flag.
+ *          - SET: The specified KeyScan flag has been set.
+ *          - RESET: The specified KeyScan flag bit has not been set.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void keyscan_demo(void)
+ * {
+ *     FlagStatus flag_status = KeyScan_GetFlagState(KEYSCAN, KEYSCAN_FLAG_OVR);
+ *
+ * }
+ * \endcode
+ */
+FlagStatus KeyScan_GetFlagState(KEYSCAN_TypeDef *KeyScan, uint32_t KeyScan_FLAG);
+
+/**
+ * \brief  Read keyscan FIFO data.
+ *
+ * \param[in] KeyScan  Select KeyScan peripheral. Refer to \ref KEYSCAN_Declaration.
+ *
+ * \return KEYSCAN FIFO data.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void keyscan_demo(void)
+ * {
+ *     uint16_t data = KeyScan_ReadFifoData(KEYSCAN);
+ * }
+ * \endcode
+ */
+uint16_t KeyScan_ReadFifoData(KEYSCAN_TypeDef *KeyScan);
+
+
+#if (KEYSCAN_SUPPORT_RAP_FUNCTION == 1)
+
+void KeyScan_RAPModeCmd(KEYSCAN_TypeDef *KeyScan, FunctionalState NewState);
+
+void KEYSCAN_TaskTrigger(KEYSCAN_TypeDef *KeyScan, uint32_t Task);
+
+void KeyScan_RAPQactiveCtrl(KEYSCAN_TypeDef *KeyScan, uint32_t Qactive, FunctionalState NewState);
+
+#endif
+
+/** End of KEYSCAN_Exported_Functions
+  * \}
+  */
+
+/** End of KEYSCAN
+  * \}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RTL_KEYSCAN_H */
+
+
diff --git a/bee/drivers/keyscan/src/device/rtl87x2g/rtl_keyscan_def.h b/bee/drivers/keyscan/src/device/rtl87x2g/rtl_keyscan_def.h
new file mode 100644
index 00000000..9f4e9177
--- /dev/null
+++ b/bee/drivers/keyscan/src/device/rtl87x2g/rtl_keyscan_def.h
@@ -0,0 +1,410 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef RTL_KEYSCAN_DEF_H
+#define RTL_KEYSCAN_DEF_H
+
+#include "utils/rtl_utils.h"
+#include "address_map.h"
+
+#ifdef  __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+/*============================================================================*
+ *                         KEYSCAN Defines
+ *============================================================================*/
+/** \defgroup KEYSCAN         KEYSCAN
+  * \brief
+  * \{
+  */
+
+/** \defgroup KEYSCAN_Exported_Constants KEYSCAN Exported Constants
+  * \brief
+  * \{
+  */
+
+/**
+ * \defgroup KEYSCAN_Defines KEYSCAN Defines
+ * \{
+ * \ingroup  KEYSCAN_Exported_Constants
+ */
+#define KEYSCAN_SUPPORT_COLUNM_LEVEL_CONFIGURE (0) //!< The function is not supported.
+#define KEYSCAN_SUPPORT_ROW_LEVEL_CONFIGURE    (1) //!< The definition supports row level configure.
+#define KEYSCAN_SUPPORT_RAP_FUNCTION           (0) //!< The function is not supported.
+
+/** End of KEYSCAN_Defines
+  * \}
+  */
+
+/** End of KEYSCAN_Exported_Constants
+  * \}
+  */
+
+/** End of KEYSCAN
+  * \}
+  */
+
+/*============================================================================*
+ *                         KEYSCAN Registers Memory Map
+ *============================================================================*/
+typedef struct
+{
+    __IO uint32_t  KEYSCAN_CLK_DIV;         /*!< 0x00 */
+    __IO uint32_t  KEYSCAN_CONFIG1;         /*!< 0x04 */
+    __IO uint32_t  KEYSCAN_CONFIG2;         /*!< 0x08 */
+    __IO uint32_t  KEYSCAN_COLUMN_CONFIG;   /*!< 0x0C */
+    __IO uint32_t  KEYSCAN_ROW_CONFIG;      /*!< 0x10 */
+    __I  uint32_t  KEYSCAN_FIFO_ENTRY;      /*!< 0x14 */
+    __IO uint32_t  KEYSCAN_INT_MASK;        /*!< 0x18 */
+    __IO uint32_t  KEYSCAN_INT_CLR;         /*!< 0x1C */
+    __I  uint32_t  KEYSCAN_INT_STS;         /*!< 0x20 */
+    __I  uint32_t  RSVD0[3];                /*!< 0x24 - 0x2C */
+    __I  uint32_t  KEYSCAN_DBG1;            /*!< 0x30 */
+    __IO uint32_t  KEYSCAN_DBG2;            /*!< 0x34 */
+} KEYSCAN_TypeDef;
+
+/*============================================================================*
+ *                         KEYSCAN Declaration
+ *============================================================================*/
+/** \defgroup KEYSCAN     KEYSCAN
+  * \brief
+  * \{
+  */
+
+/** \defgroup KEYSCAN_Exported_Constants KEYSCAN Exported Constants
+  * \brief
+  * \{
+  */
+
+/** \defgroup KEYSCAN_Declaration KEYSCAN Declaration
+  * \{
+  * \ingroup  KEYSCAN_Exported_Constants
+  */
+#define KEYSCAN        ((KEYSCAN_TypeDef *) KEYSCAN_REG_BASE)  //!< KEYSCAN base address.
+
+#define IS_KeyScan_PERIPH(PERIPH)   ((PERIPH) == KEYSCAN) //!< Check if the input parameter is valid.
+
+/** End of KEYSCAN_Declaration
+  * \}
+  */
+
+/** End of KEYSCAN_Exported_Constants
+  * \}
+  */
+
+/** End of KEYSCAN
+  * \}
+  */
+/*============================================================================*
+ *                         KEYSCAN Private Types
+ *============================================================================*/
+typedef struct
+{
+    uint32_t keyscan_reg[7];
+} KEYSCANStoreReg_Typedef;
+
+/*============================================================================*
+ *                         KEYSCAN Registers and Field Descriptions
+ *============================================================================*/
+/* 0x00
+    5:0     R/W    keyscan_delay_div                   6'h1
+    7:6     R/W    reserved_dummy00_7_6                2'h0
+    18:8    R/W    keyscan_clk_div                     11'h26
+    23:19   R      reserved_dummy00_23_19              5'h0
+    25:24   R/W    keyscan_clk_sel                     2'h0
+    28:26   R/W    keyscan_gt_pre_sel                  3'h3
+    31:29   R/W    keyscan_gt_post_sel                 3'h3
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t keyscan_delay_div: 6;
+        uint32_t reserved_1: 2;
+        uint32_t keyscan_clk_div: 11;
+        const uint32_t reserved_0: 5;
+        uint32_t keyscan_clk_sel: 2;
+        uint32_t keyscan_gt_pre_sel: 3;
+        uint32_t keyscan_gt_post_sel: 3;
+    } b;
+} KEYSCAN_CLK_DIV_TypeDef;
+
+
+
+/* 0x04
+    8:0     R/W    keyscan_release_timer_cnt           9'h10
+    17:9    R/W    keyscan_interval_timer_cnt          9'h10
+    26:18   R/W    keyscan_deb_timer_cnt               9'h10
+    27      R      reserved_dummy04_27                 1'h0
+    28      R/W    keyscan_row_pull_high_en            1'h1
+    29      R/W    keyscan_release_timer_en            1'h0
+    30      R/W    keyscan_interval_timer_en           1'h1
+    31      R/W    keyscan_deb_timer_en                1'h1
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t keyscan_release_timer_cnt: 9;
+        uint32_t keyscan_interval_timer_cnt: 9;
+        uint32_t keyscan_deb_timer_cnt: 9;
+        const uint32_t reserved_0: 1;
+        uint32_t keyscan_row_pull_high_en: 1;
+        uint32_t keyscan_release_timer_en: 1;
+        uint32_t keyscan_interval_timer_en: 1;
+        uint32_t keyscan_deb_timer_en: 1;
+    } b;
+} KEYSCAN_CONFIG1_TypeDef;
+
+
+
+/* 0x08
+    0       R/W    keyscan_all_release_int_en          1'h0
+    1       R/W    keyscan_fifo_notempty_int_en        1'h0
+    2       R/W    keyscan_scan_finish_int_en          1'h0
+    3       R/W    keyscan_fifo_or_int_en              1'h0
+    4       R/W    keyscan_fifo_th_int_en              1'h0
+    9:5     R/W    keyscan_fifo_th_level               5'h1a
+    10      R      reserved_dummy08_10                 1'h0
+    11      R/W    keyscan_manual_sel                  1'h0
+    20:12   R/W    keyscan_fifo_filter_data            9'h0
+    21      R/W    keyscan_fifo_data_filter_en         1'h0
+    22      R/W    keyscan_manual_trigger              1'h0
+    27:23   R/W    keyscan_fifo_limit                  5'h0
+    28      R/W    keyscan_fifo_ov_ctrl                1'h1
+    29      R/W    keyscan_trig_sel                    1'h1
+    30      R/W    keyscan_work_mode                   1'h1
+    31      R/W    keyscan_run_enable                  1'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t keyscan_all_release_int_en: 1;
+        uint32_t keyscan_fifo_notempty_int_en: 1;
+        uint32_t keyscan_scan_finish_int_en: 1;
+        uint32_t keyscan_fifo_or_int_en: 1;
+        uint32_t keyscan_fifo_th_int_en: 1;
+        uint32_t keyscan_fifo_th_level: 5;
+        const uint32_t reserved_0: 1;
+        uint32_t keyscan_manual_sel: 1;
+        uint32_t keyscan_fifo_filter_data: 9;
+        uint32_t keyscan_fifo_data_filter_en: 1;
+        uint32_t keyscan_manual_trigger: 1;
+        uint32_t keyscan_fifo_limit: 5;
+        uint32_t keyscan_fifo_ov_ctrl: 1;
+        uint32_t keyscan_trig_sel: 1;
+        uint32_t keyscan_work_mode: 1;
+        uint32_t keyscan_run_enable: 1;
+    } b;
+} KEYSCAN_CONFIG2_TypeDef;
+
+
+
+/* 0x0C
+    4:0     R/W    keyscan_col_num                     5'h0
+    7:5     R      reserved_dummy0c_7_5                3'h0
+    27:8    R/W    keyscan_col_sel                     20'h0
+    31:28   R      reserved_dummy0c_31_28              4'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t keyscan_col_num: 5;
+        const uint32_t reserved_1: 3;
+        uint32_t keyscan_col_sel: 20;
+        const uint32_t reserved_0: 4;
+    } b;
+} KEYSCAN_COLUMN_CONFIG_TypeDef;
+
+
+
+/* 0x10
+    11:0    R/W    keyscan_row_sel                     12'h0
+    15:12   R      reserved_dummy10_15_12              4'h0
+    19:16   R/W    keyscan_row_num                     4'h0
+    31:20   R      reserved_dummy10_31_20              12'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t keyscan_row_sel: 12;
+        const uint32_t reserved_1: 4;
+        uint32_t keyscan_row_num: 4;
+        const uint32_t reserved_0: 12;
+    } b;
+} KEYSCAN_ROW_CONFIG_TypeDef;
+
+
+
+/* 0x14
+    8:0     R      keyscan_fifo_entry                  9'h0
+    31:9    R      reserved_dummy14_31_9               23'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        const uint32_t keyscan_fifo_entry: 9;
+        const uint32_t reserved_0: 23;
+    } b;
+} KEYSCAN_FIFO_ENTRY_TypeDef;
+
+
+
+/* 0x18
+    0       R/W    keyscan_all_release_int_mask        1'h0
+    1       R/W    keyscan_fifo_notempty_int_mask      1'h0
+    2       R/W    keyscan_scan_finish_int_mask        1'h0
+    3       R/W    keyscan_fifo_or_int_mask            1'h0
+    4       R/W    keyscan_fifo_th_int_mask            1'h0
+    31:5    R      reserved_dummy18_31_5               27'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t keyscan_all_release_int_mask: 1;
+        uint32_t keyscan_fifo_notempty_int_mask: 1;
+        uint32_t keyscan_scan_finish_int_mask: 1;
+        uint32_t keyscan_fifo_or_int_mask: 1;
+        uint32_t keyscan_fifo_th_int_mask: 1;
+        const uint32_t reserved_0: 27;
+    } b;
+} KEYSCAN_INT_MASK_TypeDef;
+
+
+
+/* 0x1C
+    0       W1C    keyscan_all_release_int_clr         1'h0
+    1       W1C    keyscan_fifo_notempty_int_clr       1'h0
+    2       W1C    keyscan_scan_finish_int_clr         1'h0
+    3       W1C    keyscan_fifo_or_int_clr             1'h0
+    4       W1C    keyscan_fifo_th_int_clr             1'h0
+    5       W1C    keyscan_fifo_ov_st_clr              1'h0
+    6       W1C    keyscan_fifo_clr                    1'h0
+    7       W1C    keyscan_fifo_datafilter_st_clr      1'h0
+    8       W1C    keyscan_fifo_limit_st_clr           1'h0
+    31:9    R      reserved_dummy1c_31_9               23'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t keyscan_all_release_int_clr: 1;
+        uint32_t keyscan_fifo_notempty_int_clr: 1;
+        uint32_t keyscan_scan_finish_int_clr: 1;
+        uint32_t keyscan_fifo_or_int_clr: 1;
+        uint32_t keyscan_fifo_th_int_clr: 1;
+        uint32_t keyscan_fifo_ov_st_clr: 1;
+        uint32_t keyscan_fifo_clr: 1;
+        uint32_t keyscan_fifo_datafilter_st_clr: 1;
+        uint32_t keyscan_fifo_limit_st_clr: 1;
+        const uint32_t reserved_0: 23;
+    } b;
+} KEYSCAN_INT_CLR_TypeDef;
+
+
+
+/* 0x20
+    0       R      keyscan_fifo_empty                  1'h0
+    1       R      keyscan_fifo_full                   1'h0
+    2       R      keyscan_fifo_ov_status              1'h0
+    3       R      keyscan_fifo_datafilter_status      1'h0
+    9:4     R      keyscan_fifo_data_level             6'h0
+    14:10   R      reserved_dummy20_14_10              5'h0
+    15      R      keyscan_all_release_int_status      1'h0
+    16      R      keyscan_fifo_notempty_int_status    1'h0
+    17      R      keyscan_scan_finish_int_status      1'h0
+    18      R      keyscan_fifo_or_int_status          1'h0
+    19      R      keyscan_fifo_th_int_status          1'h0
+    20      R      keyscan_fifo_limit_status           1'h0
+    31:21   R      reserved_dummy20_31_21              11'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        const uint32_t keyscan_fifo_empty: 1;
+        const uint32_t keyscan_fifo_full: 1;
+        const uint32_t keyscan_fifo_ov_status: 1;
+        const uint32_t keyscan_fifo_datafilter_status: 1;
+        const uint32_t keyscan_fifo_data_level: 6;
+        const uint32_t reserved_1: 5;
+        const uint32_t keyscan_all_release_int_status: 1;
+        const uint32_t keyscan_fifo_notempty_int_status: 1;
+        const uint32_t keyscan_scan_finish_int_status: 1;
+        const uint32_t keyscan_fifo_or_int_status: 1;
+        const uint32_t keyscan_fifo_th_int_status: 1;
+        const uint32_t keyscan_fifo_limit_status: 1;
+        const uint32_t reserved_0: 11;
+    } b;
+} KEYSCAN_INT_STS_TypeDef;
+
+
+
+/* 0x30
+    31:0    R      rtl_version                         32'h20221011
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        const uint32_t rtl_version: 32;
+    } b;
+} KEYSCAN_DBG1_TypeDef;
+
+
+
+/* 0x34
+    2:0     R/W    dbg_sel                             3'h0
+    3       R/W    reg_speedup_mode                    1'h0
+    6:4     R      current_state                       3'h0
+    30:7    R      reserved_dummy34_30_7               24'h0
+    31      R/W    force_512k                          1'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t dbg_sel: 3;
+        uint32_t reg_speedup_mode: 1;
+        const uint32_t current_state: 3;
+        const uint32_t reserved_0: 24;
+        uint32_t force_512k: 1;
+    } b;
+} KEYSCAN_DBG2_TypeDef;
+
+
+#ifdef  __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* RTL_KEYSCAN_DEF_H */
diff --git a/bee/drivers/keyscan/src/device/rtl87x2j/rtl87x2j_keyscan.c b/bee/drivers/keyscan/src/device/rtl87x2j/rtl87x2j_keyscan.c
new file mode 100644
index 00000000..23513079
--- /dev/null
+++ b/bee/drivers/keyscan/src/device/rtl87x2j/rtl87x2j_keyscan.c
@@ -0,0 +1,99 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *                           Header Files
+ *============================================================================*/
+#include "rtl_keyscan.h"
+
+/*============================================================================*
+ *                           Private Defines
+ *============================================================================*/
+#define KEYSCAN_CLOCK_AUTO_MODE_CONFIG_AUTOMATIC       (0x00)
+#define KEYSCAN_CLOCK_AUTO_MODE_CONFIG_ALWAYSRUN       (0x0F)
+
+/*============================================================================*
+ *                           Public Functions
+ *============================================================================*/
+
+void KEYSCAN_ClockAutoModeCmd(KEYSCAN_TypeDef *KEYSCANx, FunctionalState Newstate)
+{
+    /* Check the parameters */
+    assert_param(IS_ADC_ALL_PERIPH(KEYSCANx));
+
+    if (Newstate == ENABLE)
+    {
+        KEYSCANx->KEYSCAN_QACTIVE_CTRL = KEYSCAN_CLOCK_AUTO_MODE_CONFIG_AUTOMATIC;
+    }
+    else
+    {
+        KEYSCANx->KEYSCAN_QACTIVE_CTRL = KEYSCAN_CLOCK_AUTO_MODE_CONFIG_ALWAYSRUN;
+    }
+
+    return;
+}
+
+void KEYSCAN_FIFOConfig(KEYSCAN_TypeDef *KEYSCANx, uint32_t FIFOTriggerLevel, uint32_t KeyLimit)
+{
+    KEYSCAN_CONFIG3_TypeDef keyscan_0x40 = {.d32 = KEYSCANx->KEYSCAN_CONFIG3};
+    /* fifo threshol setting */
+    keyscan_0x40.b.keyscan_fifo_th_level = FIFOTriggerLevel;
+    /* Key limit setting */
+    keyscan_0x40.b.keyscan_fifo_limit = KeyLimit;
+    KEYSCANx->KEYSCAN_CONFIG3 =  keyscan_0x40.d32;
+
+    return;
+}
+
+/**
+  * \brief  Store KEYSCAN register values when system enter DLPS.
+  * \param  PeriReg: Specifies to select the KEYSCAN peripheral.
+  * \param  StoreBuf: Store buffer to store KEYSCAN register data.
+  * \return None.
+  */
+void KEYSCAN_DLPSEnter(void *PeriReg, void *StoreBuf)
+{
+//    KEYSCANStoreReg_Typedef *store_buf = (KEYSCANStoreReg_Typedef *)StoreBuf;
+
+//    RCC_PeriphClockCmd(APBPeriph_KEYSCAN, APBPeriph_KEYSCAN_CLOCK, ENABLE);
+
+//    store_buf->keyscan_reg[0] = KEYSCAN->KEYSCAN_CLK_DIV;         /* 0x00 */
+//    store_buf->keyscan_reg[1] = KEYSCAN->KEYSCAN_CONFIG1;         /* 0x04 */
+//    store_buf->keyscan_reg[2] = KEYSCAN->KEYSCAN_CONFIG2;         /* 0x08 */
+//    store_buf->keyscan_reg[3] = KEYSCAN->KEYSCAN_COLUMN_CONFIG;   /* 0x0C */
+//    store_buf->keyscan_reg[4] = KEYSCAN->KEYSCAN_ROW_CONFIG;      /* 0x10 */
+//    store_buf->keyscan_reg[6] = KEYSCAN->KEYSCAN_INT_MASK;        /* 0x18 */
+
+    return;
+}
+
+/**
+  * \brief  Restore KEYSCAN register values when system enter DLPS.
+  * \param  PeriReg: Specifies to select the KEYSCAN peripheral.
+  * \param  StoreBuf: Restore buffer to restore KEYSCAN register data.
+  * \return None
+  */
+void KEYSCAN_DLPSExit(void *PeriReg, void *StoreBuf)
+{
+//    KEYSCANStoreReg_Typedef *store_buf = (KEYSCANStoreReg_Typedef *)StoreBuf;
+
+//    RCC_PeriphClockCmd(APBPeriph_KEYSCAN, APBPeriph_KEYSCAN_CLOCK, ENABLE);
+
+//    /* Set FSM to idle state */
+//    KEYSCAN->KEYSCAN_CONFIG2 &= ~BIT31;
+//    KEYSCAN->KEYSCAN_CLK_DIV = store_buf->keyscan_reg[0];
+//    KEYSCAN->KEYSCAN_CONFIG2 = (store_buf->keyscan_reg[2] & (~(BIT31)));
+//    KEYSCAN->KEYSCAN_CONFIG1 = store_buf->keyscan_reg[1];
+//    KEYSCAN->KEYSCAN_COLUMN_CONFIG = store_buf->keyscan_reg[3];
+//    KEYSCAN->KEYSCAN_ROW_CONFIG = store_buf->keyscan_reg[4];
+//    KEYSCAN->KEYSCAN_INT_MASK = store_buf->keyscan_reg[6];
+//    KEYSCAN->KEYSCAN_CONFIG2 |= (store_buf->keyscan_reg[2] & ((BIT31)));
+
+    return;
+}
+
+
+
diff --git a/bee/drivers/keyscan/src/device/rtl87x2j/rtl_keyscan_def.h b/bee/drivers/keyscan/src/device/rtl87x2j/rtl_keyscan_def.h
new file mode 100644
index 00000000..c98cc4a3
--- /dev/null
+++ b/bee/drivers/keyscan/src/device/rtl87x2j/rtl_keyscan_def.h
@@ -0,0 +1,426 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef RTL_KEYSCAN_DEF_H
+#define RTL_KEYSCAN_DEF_H
+
+#include "utils/rtl_utils.h"
+#include "address_map.h"
+
+#ifdef  __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+/*============================================================================*
+ *                         KEYSCAN Defines
+ *============================================================================*/
+/** \defgroup KEYSCAN         KEYSCAN
+  * \brief
+  * \{
+  */
+
+/** \defgroup KEYSCAN_Exported_Constants KEYSCAN Exported Constants
+  * \brief
+  * \{
+  */
+
+/**
+ * \defgroup KEYSCAN_Defines KEYSCAN Defines
+ * \{
+ * \ingroup  KEYSCAN_Exported_Constants
+ */
+#define KEYSCAN_SUPPORT_COLUNM_LEVEL_CONFIGURE (1)
+#define KEYSCAN_SUPPORT_ROW_LEVEL_CONFIGURE    (1)
+#define KEYSCAN_SUPPORT_RAP_FUNCTION           (1)
+#define KEYSCAN_SUPPORT_AUTO_CLOCK             (1)
+
+
+/** End of KEYSCAN_Defines
+  * \}
+  */
+
+/** End of KEYSCAN_Exported_Constants
+  * \}
+  */
+
+/** End of KEYSCAN
+  * \}
+  */
+
+/*============================================================================*
+ *                          KEYSCAN Registers Memory Map
+ *============================================================================*/
+typedef struct
+{
+    __IO uint32_t KEYSCAN_CLK_DIV;              /*!< 0x00 */
+    __IO uint32_t KEYSCAN_CONFIG1;              /*!< 0x04 */
+    __IO uint32_t KEYSCAN_CONFIG2;              /*!< 0x08 */
+    __IO uint32_t KEYSCAN_COLUMN_CONFIG;        /*!< 0x0C */
+    __IO uint32_t KEYSCAN_ROW_CONFIG;           /*!< 0x10 */
+    __I  uint32_t KEYSCAN_FIFO_ENTRY;           /*!< 0x14 */
+    __IO uint32_t KEYSCAN_INT_MASK;             /*!< 0x18 */
+    __IO uint32_t KEYSCAN_INT_CLR;              /*!< 0x1C */
+    __I  uint32_t KEYSCAN_INT_STS;              /*!< 0x20 */
+    __I  uint32_t RSVD0[3];                     /*!< 0x24 - 0x2C */
+    __I  uint32_t KEYSCAN_DBG1;                 /*!< 0x30 */
+    __IO uint32_t KEYSCAN_DBG2;                 /*!< 0x34 */
+    __IO uint32_t KEYSCAN_TASK_CTRL;            /*!< 0x38 */
+    __IO uint32_t KEYSCAN_QACTIVE_CTRL;         /*!< 0x3C */
+    __IO uint32_t KEYSCAN_CONFIG3;              /*!< 0x40 */
+} KEYSCAN_TypeDef;
+
+/*============================================================================*
+ *                          KEYSCAN Declaration
+ *============================================================================*/
+#define KEYSCAN                     ((KEYSCAN_TypeDef *) KEY_SCAN_BASE)
+
+#define IS_KeyScan_PERIPH(PERIPH)   ((PERIPH) == KEYSCAN)
+
+/*============================================================================*
+ *                          KEYSCAN Private Types
+ *============================================================================*/
+typedef struct
+{
+    uint32_t keyscan_reg[7];
+} KEYSCANStoreReg_Typedef;
+
+/*============================================================================*
+ *                          KEYSCAN Registers and Field Descriptions
+ *============================================================================*/
+/* 0x00
+   5:0     R/W    keyscan_delay_div               6'h1
+   7:6     R/W    reserved_dummy00_7_6            2'h0
+   18:8    R/W    keyscan_clk_div                 11'h26
+   23:19   R      reserved_dummy00_23_19          5'h0
+   25:24   R/W    keyscan_clk_sel                 2'h0
+   28:26   R/W    keyscan_gt_pre_sel              3'h3
+   31:29   R/W    keyscan_gt_post_sel             3'h3
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t keyscan_delay_div: 6;
+        uint32_t reserved_1: 2;
+        uint32_t keyscan_clk_div: 11;
+        const uint32_t reserved_0: 5;
+        uint32_t keyscan_clk_sel: 2;
+        uint32_t keyscan_gt_pre_sel: 3;
+        uint32_t keyscan_gt_post_sel: 3;
+    } b;
+} KEYSCAN_CLK_DIV_TypeDef;
+
+
+/* 0x04
+   8:0     R/W    keyscan_release_timer_cnt       9'h10
+   17:9    R/W    keyscan_interval_timer_cnt      9'h10
+   26:18   R/W    keyscan_deb_timer_cnt           9'h10
+   27      R/W    keyscan_column_output_high_en   1'h0
+   28      R/W    keyscan_pull_high_en            1'h1
+   29      R/W    keyscan_release_timer_en        1'h0
+   30      R/W    keyscan_interval_timer_en       1'h1
+   31      R/W    keyscan_deb_timer_en            1'h1
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t keyscan_release_timer_cnt: 9;
+        uint32_t keyscan_interval_timer_cnt: 9;
+        uint32_t keyscan_deb_timer_cnt: 9;
+        uint32_t keyscan_column_output_high_en: 1;
+        uint32_t keyscan_pull_high_en: 1;
+        uint32_t keyscan_release_timer_en: 1;
+        uint32_t keyscan_interval_timer_en: 1;
+        uint32_t keyscan_deb_timer_en: 1;
+    } b;
+} KEYSCAN_CONFIG1_TypeDef;
+
+
+/* 0x08
+   0       R/W    keyscan_all_release_int_en      1'h0
+   1       R/W    keyscan_fifo_notempty_int_en    1'h0
+   2       R/W    keyscan_scan_finish_int_en      1'h0
+   3       R/W    keyscan_fifo_or_int_en          1'h0
+   4       R/W    keyscan_fifo_th_int_en          1'h0
+   9:5     R      reserved_dummy08_9_5            5'h0
+   10      R/W    keyscan_manual_sel              1'h1
+   20:11   R/W    keyscan_fifo_filter_data        10'h0
+   21      R/W    keyscan_fifo_data_filter_en     1'h0
+   22      R/W    keyscan_manual_trigger          1'h0
+   27:23   R      reserved_dummy08_27_23          5'h0
+   28      R/W    keyscan_fifo_ov_ctrl            1'h1
+   29      R/W    keyscan_trig_sel                1'h1
+   30      R/W    keyscan_work_mode               1'h1
+   31      R/W    keyscan_run_enable              1'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t keyscan_all_release_int_en: 1;
+        uint32_t keyscan_fifo_notempty_int_en: 1;
+        uint32_t keyscan_scan_finish_int_en: 1;
+        uint32_t keyscan_fifo_or_int_en: 1;
+        uint32_t keyscan_fifo_th_int_en: 1;
+        const uint32_t reserved_1: 5;
+        uint32_t keyscan_manual_sel: 1;
+        uint32_t keyscan_fifo_filter_data: 10;
+        uint32_t keyscan_fifo_data_filter_en: 1;
+        uint32_t keyscan_manual_trigger: 1;
+        const uint32_t reserved_0: 5;
+        uint32_t keyscan_fifo_ov_ctrl: 1;
+        uint32_t keyscan_trig_sel: 1;
+        uint32_t keyscan_work_mode: 1;
+        uint32_t keyscan_run_enable: 1;
+    } b;
+} KEYSCAN_CONFIG2_TypeDef;
+
+
+/* 0x0C
+   4:0     R/W    keyscan_col_num                 5'h0
+   7:5     R      reserved_dummy0c_7_5            3'h0
+   27:8    R/W    keyscan_col_sel                 20'h0
+   31:28   R      reserved_dummy0c_31_28          4'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t keyscan_col_num: 5;
+        const uint32_t reserved_1: 3;
+        uint32_t keyscan_col_sel: 20;
+        const uint32_t reserved_0: 4;
+    } b;
+} KEYSCAN_COLUMN_CONFIG_TypeDef;
+
+
+/* 0x10
+   17:0    R/W    keyscan_row_sel                 18'h0
+   19:18   R      reserved_dummy10_19_18          2'h0
+   24:20   R/W    keyscan_row_num                 5'h0
+   31:25   R      reserved_dummy10_31_25          7'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t keyscan_row_sel: 18;
+        const uint32_t reserved_1: 2;
+        uint32_t keyscan_row_num: 5;
+        const uint32_t reserved_0: 7;
+    } b;
+} KEYSCAN_ROW_CONFIG_TypeDef;
+
+
+/* 0x14
+   9:0     R      keyscan_fifo_entry              10'h0
+   31:10   R      reserved_dummy14_31_10          22'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t keyscan_fifo_entry: 10;
+        const uint32_t reserved_0: 22;
+    } b;
+} KEYSCAN_FIFO_ENTRY_TypeDef;
+
+
+/* 0x18
+   0       R/W    keyscan_all_release_int_mask    1'h0
+   1       R/W    keyscan_fifo_notempty_int_mask  1'h0
+   2       R/W    keyscan_scan_finish_int_mask    1'h0
+   3       R/W    keyscan_fifo_or_int_mask        1'h0
+   4       R/W    keyscan_fifo_th_int_mask        1'h0
+   31:5    R      reserved_dummy18_31_5           27'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t keyscan_all_release_int_mask: 1;
+        uint32_t keyscan_fifo_notempty_int_mask: 1;
+        uint32_t keyscan_scan_finish_int_mask: 1;
+        uint32_t keyscan_fifo_or_int_mask: 1;
+        uint32_t keyscan_fifo_th_int_mask: 1;
+        const uint32_t reserved_0: 27;
+    } b;
+} KEYSCAN_INT_MASK_TypeDef;
+
+
+/* 0x1C
+   0       W1C    keyscan_all_release_int_clr     1'h0
+   1       W1C    keyscan_fifo_notempty_int_clr   1'h0
+   2       W1C    keyscan_scan_finish_int_clr     1'h0
+   3       W1C    keyscan_fifo_or_int_clr         1'h0
+   4       W1C    keyscan_fifo_th_int_clr         1'h0
+   5       W1C    keyscan_fifo_ov_st_clr          1'h0
+   6       W1C    keyscan_fifo_clr                1'h0
+   7       W1C    keyscan_fifo_data_filter_st_clr 1'h0
+   8       W1C    keyscan_fifo_limit_st_clr       1'h0
+   31:9    R      reserved_dummy1c_31_9           23'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t keyscan_all_release_int_clr: 1;
+        uint32_t keyscan_fifo_notempty_int_clr: 1;
+        uint32_t keyscan_scan_finish_int_clr: 1;
+        uint32_t keyscan_fifo_or_int_clr: 1;
+        uint32_t keyscan_fifo_th_int_clr: 1;
+        uint32_t keyscan_fifo_ov_st_clr: 1;
+        uint32_t keyscan_fifo_clr: 1;
+        uint32_t keyscan_fifo_data_filter_st_clr: 1;
+        uint32_t keyscan_fifo_limit_st_clr: 1;
+        const uint32_t reserved_0: 23;
+    } b;
+} KEYSCAN_INT_CLR_TypeDef;
+
+
+/* 0x20
+   0       R      keyscan_fifo_empty              1'h0
+   1       R      keyscan_fifo_full               1'h0
+   2       R      keyscan_fifo_ov_status          1'h0
+   3       R      keyscan_fifo_data_filter_status 1'h0
+   10:4    R      keyscan_fifo_data_level         7'h0
+   14:11   R      reserved_dummy20_14_11          4'h0
+   15      R      keyscan_all_release_int_status  1'h0
+   16      R      keyscan_fifo_notempty_int_status1'h0
+   17      R      keyscan_scan_finish_int_status  1'h0
+   18      R      keyscan_fifo_or_int_status      1'h0
+   19      R      keyscan_fifo_th_int_status      1'h0
+   20      R      keyscan_fifo_limit_status       1'h0
+   31:21   R      reserved_dummy20_31_21          11'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t keyscan_fifo_empty: 1;
+        const uint32_t keyscan_fifo_full: 1;
+        const uint32_t keyscan_fifo_ov_status: 1;
+        const uint32_t keyscan_fifo_data_filter_status: 1;
+        const uint32_t keyscan_fifo_data_level: 7;
+        const uint32_t reserved_1: 4;
+        const uint32_t keyscan_all_release_int_status: 1;
+        const uint32_t keyscan_fifo_notempty_int_status: 1;
+        const uint32_t keyscan_scan_finish_int_status: 1;
+        const uint32_t keyscan_fifo_or_int_status: 1;
+        const uint32_t keyscan_fifo_th_int_status: 1;
+        const uint32_t keyscan_fifo_limit_status: 1;
+        const uint32_t reserved_0: 11;
+    } b;
+} KEYSCAN_INT_STS_TypeDef;
+
+
+
+
+/* 0x30
+   31:0    R      rtl_version                     32'h20241025
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t rtl_version: 32;
+    } b;
+} KEYSCAN_DBG1_TypeDef;
+
+
+/* 0x34
+   2:0     R/W    dbg_sel                         3'h0
+   3       R/W    reg_speedup_mode                1'h0
+   6:4     R      current_state                   3'h0
+   30:7    R      reserved_dummy34_30_7           24'h0
+   31      R/W    force_512k                      1'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t dbg_sel: 3;
+        uint32_t reg_speedup_mode: 1;
+        const uint32_t current_state: 3;
+        const uint32_t reserved_0: 24;
+        uint32_t force_512k: 1;
+    } b;
+} KEYSCAN_DBG2_TypeDef;
+
+
+/* 0x38
+   0       R/W    rap_mode                        1'h0
+   1       WAC    task_manual                     1'h0
+   31:2    R      reserved31_2                    30'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t rap_mode: 1;
+        uint32_t task_manual: 1;
+        const uint32_t reserved_0: 30;
+    } b;
+} KEYSCAN_TASK_CTRL_TypeDef;
+
+
+/* 0x3C
+   0       R/W    clk_qactive_man_data            1'h0
+   1       R/W    clk_qactive_man_enable          1'h0
+   2       R/W    pclk_qactive_man_data           1'h0
+   3       R/W    pclk_qactive_man_enable         1'h0
+   31:4    R      reserved31_4                    28'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t clk_qactive_man_data: 1;
+        uint32_t clk_qactive_man_enable: 1;
+        uint32_t pclk_qactive_man_data: 1;
+        uint32_t pclk_qactive_man_enable: 1;
+        const uint32_t reserved_0: 28;
+    } b;
+} KEYSCAN_QACTIVE_CTRL_TypeDef;
+
+
+/* 0x40
+   6:0     R/W    keyscan_fifo_th_level           7'h6c
+   22:7    R      reserved_dummy40_22_7           16'h0
+   29:23   R/W    keyscan_fifo_limit              7'h0
+   31:30   R      reserved_dummy40_31_30          2'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t keyscan_fifo_th_level: 7;
+        const uint32_t reserved_1: 16;
+        uint32_t keyscan_fifo_limit: 7;
+        const uint32_t reserved_0: 2;
+    } b;
+} KEYSCAN_CONFIG3_TypeDef;
+
+
+#ifdef  __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* RTL_KEYSCAN_DEF_H */
diff --git a/bee/drivers/keyscan/src/device/rtl_common/rtl_keyscan.c b/bee/drivers/keyscan/src/device/rtl_common/rtl_keyscan.c
new file mode 100644
index 00000000..cd330dc6
--- /dev/null
+++ b/bee/drivers/keyscan/src/device/rtl_common/rtl_keyscan.c
@@ -0,0 +1,548 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *                           Header Files
+ *============================================================================*/
+#include "rtl_keyscan.h"
+#include "rtl_rcc.h"
+
+/*============================================================================*
+ *                           Private Functions
+ *============================================================================*/
+extern void KEYSCAN_FIFOConfig(KEYSCAN_TypeDef *KeyScan, uint32_t FIFOTriggerLevel,
+                               uint32_t KeyLimit);
+
+/*============================================================================*
+ *                           Public Functions
+ *============================================================================*/
+/**
+  * \brief  Deinitializes the KEYSCAN peripheral registers to their default reset values(turn off keyscan clock).
+  * \param  KEYSCANx: Selected KEYSCAN peripheral.
+  * \return None
+  */
+void KEYSCAN_DeInit(KEYSCAN_TypeDef *KEYSCANx)
+{
+    /* Check the parameters */
+    assert_param(IS_KEYSCAN_PERIPH(KEYSCANx));
+
+    RCC_ClockCmd(KEYSCAN_CLOCK, DISABLE);
+}
+
+/**
+  * \brief  Initializes the KEYSCAN peripheral according to the specified
+  *         parameters in the KEYSCAN_InitStruct
+  * \param  KEYSCANx: Selected KEYSCAN peripheral.
+  * \param  KEYSCAN_InitStruct: Pointer to a KEYSCAN_InitTypeDef structure that
+  *         contains the configuration information for the specified KEYSCAN peripheral
+  * \return None
+  */
+void KEYSCAN_Init(KEYSCAN_TypeDef *KEYSCANx, KEYSCAN_InitTypeDef *KEYSCAN_InitStruct)
+{
+    assert_param(IS_KEYSCAN_PERIPH(KEYSCAN));
+    assert_param(IS_KEYSCAN_ROW_NUM(KEYSCAN_InitStruct->rowSize));
+    assert_param(IS_KEYSCAN_COL_NUM(KEYSCAN_InitStruct->colSize));
+    assert_param(IS_KEYSCAN_DEBOUNCE_EN(KEYSCAN_InitStruct->debounceEn));
+    assert_param(IS_KEYSCAN_SCANINTERVAL_EN(KEYSCAN_InitStruct->scantimerEn));
+    assert_param(IS_KEYSCAN_RELEASE_DETECT_EN(KEYSCAN_InitStruct->detecttimerEn));
+    assert_param(IS_KEYSCAN_DETECT_MODE(KEYSCAN_InitStruct->detectMode));
+    assert_param(IS_KEYSCAN_FIFO_OVR_CTRL(KEYSCAN_InitStruct->fifoOvrCtrl));
+    assert_param(IS_KEYSCAN_SCAN_MODE(KEYSCAN_InitStruct->scanmode));
+    assert_param(IS_KEYSCAN_KEY_LIMIT(KEYSCAN_InitStruct->keylimit));
+
+    /* Mask all keyscan interrupt */
+    KEYSCAN->KEYSCAN_INT_MASK |= 0x1f;
+
+    /* Set FSM to idle state */
+    KEYSCAN_CONFIG2_TypeDef keyscan_0x08 = {.d32 = KEYSCAN->KEYSCAN_CONFIG2};
+    keyscan_0x08.b.keyscan_run_enable = 0;
+    /* Auto scan mode should set manual_sel to 1(key trigger) */
+    if (KEYSCAN_InitStruct->KEYSCAN_ScanMode == KEYSCAN_AUTO_SCAN_MODE)
+    {
+        keyscan_0x08.b.keyscan_manual_sel = KEYSCAN_MANUAL_SEL_KEY;
+    }
+    else
+    {
+        keyscan_0x08.b.keyscan_manual_sel = KEYSCAN_InitStruct->KEYSCAN_ManualSel;
+    }
+
+    KEYSCAN->KEYSCAN_CONFIG2 = keyscan_0x08.d32;
+
+    /* Clock divider config */
+    KEYSCAN_CLK_DIV_TypeDef keyscan_0x00 = {.d32 = KEYSCAN->KEYSCAN_CLK_DIV};
+    keyscan_0x00.b.keyscan_clk_div = KEYSCAN_InitStruct->KEYSCAN_ClockDiv;
+    keyscan_0x00.b.keyscan_delay_div = KEYSCAN_InitStruct->KEYSCAN_ClockDelayDiv;
+    /* preguard time and postguard time config */
+    keyscan_0x00.b.keyscan_gt_pre_sel = KEYSCAN_InitStruct->KEYSCAN_PreGuardCnt;
+    keyscan_0x00.b.keyscan_gt_post_sel = KEYSCAN_InitStruct->KEYSCAN_PostGuardCnt;
+    KEYSCAN->KEYSCAN_CLK_DIV = keyscan_0x00.d32;
+
+    /* Config scan mode and detect mode*/
+    keyscan_0x08.b.keyscan_work_mode = KEYSCAN_InitStruct->KEYSCAN_ScanMode;
+    keyscan_0x08.b.keyscan_trig_sel = KEYSCAN_InitStruct->KEYSCAN_DetectMode;
+    keyscan_0x08.b.keyscan_fifo_ov_ctrl = KEYSCAN_InitStruct->KEYSCAN_FIFOOvflCtrl;
+    KEYSCAN->KEYSCAN_CONFIG2 = keyscan_0x08.d32;
+
+    /* Config fifo threshol and key limit */
+    KEYSCAN_FIFOConfig(KEYSCAN,
+                       KEYSCAN_InitStruct->KEYSCAN_FIFOTriggerLevel,
+                       KEYSCAN_InitStruct->KEYSCAN_KeyLimit);
+    /* Time config */
+    KEYSCAN_CONFIG1_TypeDef keyscan_0x04 = {.d32 = KEYSCAN->KEYSCAN_CONFIG1};
+    keyscan_0x04.b.keyscan_deb_timer_en = KEYSCAN_InitStruct->KEYSCAN_DebounceEn;
+    keyscan_0x04.b.keyscan_interval_timer_en = KEYSCAN_InitStruct->KEYSCAN_ScanTimerEn;
+    keyscan_0x04.b.keyscan_release_timer_en = KEYSCAN_InitStruct->KEYSCAN_DetectTimerEn;
+    /* Time count config */
+    keyscan_0x04.b.keyscan_deb_timer_cnt = KEYSCAN_InitStruct->KEYSCAN_DebounceCnt;
+    keyscan_0x04.b.keyscan_interval_timer_cnt = KEYSCAN_InitStruct->KEYSCAN_ScanInterval;
+    keyscan_0x04.b.keyscan_release_timer_cnt = KEYSCAN_InitStruct->KEYSCAN_ReleaseCnt;
+#if KEYSCAN_SUPPORT_ROW_LEVEL_CONFIGURE
+    keyscan_0x04.b.keyscan_pull_high_en = KEYSCAN_InitStruct->KEYSCAN_RowPullHighEn;
+#endif
+#if KEYSCAN_SUPPORT_COLUNM_LEVEL_CONFIGURE
+    keyscan_0x04.b.keyscan_column_output_high_en = KEYSCAN_InitStruct->KEYSCAN_ColunmOutputHighEn;
+#endif
+    KEYSCAN->KEYSCAN_CONFIG1 = keyscan_0x04.d32;
+
+    /* Set column map, config which column to work */
+    KEYSCAN_COLUMN_CONFIG_TypeDef keyscan_0x0c = {.d32 = KEYSCAN->KEYSCAN_COLUMN_CONFIG};
+    keyscan_0x0c.b.keyscan_col_num = KEYSCAN_InitStruct->KEYSCAN_ColSize - 1;
+    keyscan_0x0c.b.keyscan_col_sel = (1 << KEYSCAN_InitStruct->KEYSCAN_ColSize) - 1;
+    KEYSCAN->KEYSCAN_COLUMN_CONFIG = keyscan_0x0c.d32;
+
+    /* Set row map, config which col row work */
+    KEYSCAN_ROW_CONFIG_TypeDef keyscan_0x10 = {.d32 = KEYSCAN->KEYSCAN_ROW_CONFIG};
+    keyscan_0x10.b.keyscan_row_num = KEYSCAN_InitStruct->KEYSCAN_RowSize - 1;
+    keyscan_0x10.b.keyscan_row_sel = (1 << KEYSCAN_InitStruct->KEYSCAN_RowSize) - 1;
+    KEYSCAN->KEYSCAN_ROW_CONFIG = keyscan_0x10.d32;
+
+    /* Clear all interrupt status and status flag */
+    KEYSCAN->KEYSCAN_INT_CLR |= 0x1ff;
+    /* Unmask all keyscan interrupt */
+    KEYSCAN->KEYSCAN_INT_MASK &= ~0x1f;
+
+    return;
+}
+
+/**
+  * \brief  Fills each I2C_InitStruct member with its default value.
+  * \param  KEYSCAN_InitStruct: Pointer to a KEYSCAN_InitTypeDef structure which will be initialized.
+  * \return None
+  */
+void KEYSCAN_StructInit(KEYSCAN_InitTypeDef *KEYSCAN_InitStruct)
+{
+    KEYSCAN_InitStruct->KEYSCAN_ColSize       = 2;
+    KEYSCAN_InitStruct->KEYSCAN_RowSize       = 2;
+
+    KEYSCAN_InitStruct->KEYSCAN_ClockDiv      = 0x1f8;
+    KEYSCAN_InitStruct->KEYSCAN_ClockDelayDiv = 0x01;
+
+    KEYSCAN_InitStruct->KEYSCAN_DebounceEn    = ENABLE;
+    KEYSCAN_InitStruct->KEYSCAN_ScanTimerEn   = ENABLE;
+    KEYSCAN_InitStruct->KEYSCAN_DetectTimerEn = ENABLE;
+
+    KEYSCAN_InitStruct->KEYSCAN_DebounceCnt   = 0x10;
+    KEYSCAN_InitStruct->KEYSCAN_ScanInterval  = 0x10;
+    KEYSCAN_InitStruct->KEYSCAN_ReleaseCnt    = 0x1;
+
+    KEYSCAN_InitStruct->KEYSCAN_ScanMode      = KEYSCAN_AUTO_SCAN_MODE;
+    KEYSCAN_InitStruct->KEYSCAN_DetectMode    = KEYSCAN_DETECT_MODE_EDGE;
+    KEYSCAN_InitStruct->KEYSCAN_ManualSel     = KEYSCAN_MANUAL_SEL_KEY;
+
+    KEYSCAN_InitStruct->KEYSCAN_FIFOTriggerLevel = 1;
+    KEYSCAN_InitStruct->KEYSCAN_FIFOOvflCtrl     = KEYSCAN_FIFO_OVFL_CTRL_DIS_OLDEST;
+    KEYSCAN_InitStruct->KEYSCAN_KeyLimit         = 0x03;
+
+    KEYSCAN_InitStruct->KEYSCAN_PreGuardCnt    = 3;
+    KEYSCAN_InitStruct->KEYSCAN_PostGuardCnt   = 3;
+
+#if KEYSCAN_SUPPORT_ROW_LEVEL_CONFIGURE
+    KEYSCAN_InitStruct->KEYSCAN_RowPullHighEn      = ENABLE;
+#endif
+#if KEYSCAN_SUPPORT_COLUNM_LEVEL_CONFIGURE
+    KEYSCAN_InitStruct->KEYSCAN_ColunmOutputHighEn = DISABLE;
+#endif
+    return;
+}
+
+/**
+  * \brief  Enables or disables the specified KEYSCAN interrupt.
+  * \param  KEYSCANx: Selected KEYSCAN peripheral.
+  * \param  KEYSCAN_INT: Specifies the KEYSCAN interrupts sources to be enabled or disabled.
+  *         This parameter can be any combination of the following values:
+  *         \arg KEYSCAN_INT_THRESHOLD: Kescan FIFO data over threshold interrupt.
+  *         \arg KEYSCAN_INT_OVER_READ: KEYSCAN over read interrupt.
+  *         \arg KEYSCAN_INT_SCAN_END: KEYSCAN scan end interrupt.
+  *         \arg KEYSCAN_INT_FIFO_NOT_EMPTY: KEYSCAN FIFO not empty interrupt.
+  *         \arg KEYSCAN_INT_ALL_RELEASE: KEYSCAN all key release interrupt.
+  * \param  NewState: New state of the specified KEYSCAN interrupts.
+  *         This parameter can be: ENABLE or DISABLE.
+  * \return None
+  */
+void KEYSCAN_INTConfig(KEYSCAN_TypeDef *KEYSCANx, uint32_t KEYSCAN_INT, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_KEYSCAN_PERIPH(KEYSCAN));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+    assert_param(IS_KEYSCAN_CONFIG_INT(KEYSCAN_INT));
+
+    if (NewState == ENABLE)
+    {
+        /* Enable the selected KEYSCAN interrupts */
+        KEYSCAN->KEYSCAN_CONFIG2 |= KEYSCAN_INT;
+    }
+    else
+    {
+        /* Disable the selected KEYSCAN interrupts */
+        KEYSCAN->KEYSCAN_CONFIG2 &= (uint32_t)~KEYSCAN_INT;
+    }
+}
+
+/**
+  * \brief  Enables or disables the specified KEYSCAN interrupts mask.
+  * \param  KEYSCANx: Selected KEYSCAN peripheral.
+  * \param  NewState: New state of the specified KEYSCAN interrupts mask.
+  *         This parameter can be: ENABLE or DISABLE.
+  * \return None
+  */
+void KEYSCAN_INTMask(KEYSCAN_TypeDef *KEYSCANx, uint32_t KEYSCAN_INT, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_KEYSCAN_PERIPH(KEYSCAN));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (NewState == ENABLE)
+    {
+        /* Mask KEYSCAN interrupts */
+        KEYSCAN->KEYSCAN_INT_MASK |= KEYSCAN_INT;
+    }
+    else
+    {
+        /* Enable KEYSCAN interrupts */
+        KEYSCAN->KEYSCAN_INT_MASK &= (~KEYSCAN_INT);
+    }
+}
+
+/**
+  * \brief  Read data from keyscan FIFO.
+  * \param  KEYSCANx: selected KEYSCAN peripheral.
+  * \param  outBuf: buffer to save data read from KEYSCAN FIFO.
+  * \param  count: number of data to be read.
+  * \return None
+  */
+void KEYSCAN_Read(KEYSCAN_TypeDef *KEYSCANx, uint16_t *outBuf, uint16_t count)
+{
+    /* Check the parameters */
+    assert_param(IS_KEYSCAN_PERIPH(KEYSCAN));
+
+    for (uint16_t i = 0; i < count; i++)
+    {
+        *outBuf++ = (uint16_t)KEYSCAN->KEYSCAN_FIFO_ENTRY;
+    }
+
+    return;
+}
+
+/**
+  * \brief  Enables or disables the KEYSCAN peripheral.
+  * \param  KEYSCANx: Selected KEYSCAN peripheral.
+  * \param  NewState: New state of the KEYSCAN peripheral.
+  *         This parameter can be: ENABLE or DISABLE.
+  * \return None
+  */
+void KEYSCAN_Cmd(KEYSCAN_TypeDef *KEYSCANx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_KEYSCAN_PERIPH(KEYSCAN));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    KEYSCAN_CONFIG2_TypeDef keyscan_0x08 = {.d32 = KEYSCAN->KEYSCAN_CONFIG2};
+    keyscan_0x08.b.keyscan_run_enable = NewState;
+    keyscan_0x08.b.keyscan_manual_trigger = NewState &&
+                                            (!keyscan_0x08.b.keyscan_work_mode) &&
+                                            (!keyscan_0x08.b.keyscan_manual_sel);
+    KEYSCAN->KEYSCAN_CONFIG2 = keyscan_0x08.d32;
+}
+
+/**
+  * \brief  Set filter data.
+  * \param  KEYSCANx: Selected KEYSCAN peripheral.
+  * \param  data: Config the data to be filtered.
+  *         This parameter should not be more than 9 bits
+  * \param  NewState: New state of the KEYSCAN peripheral.
+  * \return none.
+  */
+void KEYSCAN_FilterDataConfig(KEYSCAN_TypeDef *KEYSCANx, uint16_t data, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_KEYSCAN_PERIPH(KEYSCAN));
+
+    if (NewState == ENABLE)
+    {
+        KEYSCAN_CONFIG2_TypeDef keyscan_0x08 = {.d32 = KEYSCAN->KEYSCAN_CONFIG2};
+        keyscan_0x08.b.keyscan_fifo_data_filter_en = 0;
+        KEYSCAN->KEYSCAN_CONFIG2 = keyscan_0x08.d32;
+
+        keyscan_0x08.b.keyscan_fifo_filter_data = data;
+        keyscan_0x08.b.keyscan_fifo_data_filter_en = 1;
+        KEYSCAN->KEYSCAN_CONFIG2 = keyscan_0x08.d32;
+    }
+    else
+    {
+        KEYSCAN_CONFIG2_TypeDef keyscan_0x08 = {.d32 = KEYSCAN->KEYSCAN_CONFIG2};
+        keyscan_0x08.b.keyscan_fifo_data_filter_en = 0;
+        KEYSCAN->KEYSCAN_CONFIG2 = keyscan_0x08.d32;
+    }
+
+    return;
+}
+
+/**
+  * \brief  KEYSCAN debounce time config.
+  * \param  KEYSCANx: Selected KEYSCAN peripheral.
+  * \param  time: KEYSCAN hardware debounce time.
+  * \param  NewState: New state of the KEYSCAN debounce function.
+  *         This parameter can be: ENABLE or DISABLE.
+  * \return none.
+  */
+void KEYSCAN_DebounceConfig(KEYSCAN_TypeDef *KEYSCANx, uint16_t time,
+                            FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_KEYSCAN_PERIPH(KEYSCAN));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    KEYSCAN_CONFIG1_TypeDef keyscan_0x04 = {.d32 = KEYSCAN->KEYSCAN_CONFIG1};
+    keyscan_0x04.b.keyscan_deb_timer_en = NewState;
+    keyscan_0x04.b.keyscan_deb_timer_cnt = time;
+    KEYSCAN->KEYSCAN_CONFIG1 = keyscan_0x04.d32;
+}
+
+/**
+  * \brief  Get KEYSCAN FIFO data num.
+  * \param  KEYSCANx: Selected KEYSCAN peripheral.
+  * \return Data length in FIFO.
+  */
+uint16_t KEYSCAN_GetFIFODataNum(KEYSCAN_TypeDef *KEYSCANx)
+{
+    /* Check the parameters */
+    assert_param(IS_KEYSCAN_PERIPH(KEYSCAN));
+
+    KEYSCAN_INT_STS_TypeDef keyscan_0x20 = {.d32 = KEYSCAN->KEYSCAN_INT_STS};
+    return (uint16_t)(keyscan_0x20.b.keyscan_fifo_data_level);
+}
+
+/**
+  * \brief  Clear the KEYSCAN interrupt pending bit.
+  * \param  KEYSCANx: Selected KEYSCAN peripheral.
+  * \param  KEYSCAN_INT: Specifies the KEYSCAN interrupts sources to be enabled or disabled.
+  *         This parameter can be any combination of the following values:
+  *         \arg KEYSCAN_INT_THRESHOLD: Kescan FIFO data over threshold interrupt.
+  *         \arg KEYSCAN_INT_OVER_READ: KEYSCAN over read interrupt.
+  *         \arg KEYSCAN_INT_SCAN_END: KEYSCAN scan end interrupt.
+  *         \arg KEYSCAN_INT_FIFO_NOT_EMPTY: KEYSCAN FIFO not empty interrupt.
+  *         \arg KEYSCAN_INT_ALL_RELEASE: KEYSCAN all key release interrupt.
+  * \return none.
+  */
+void KEYSCAN_ClearINTPendingBit(KEYSCAN_TypeDef *KEYSCANx, uint32_t KEYSCAN_INT)
+{
+    /* Check the parameters */
+    assert_param(IS_KEYSCAN_PERIPH(KEYSCAN));
+    assert_param(IS_KEYSCAN_CONFIG_INT(KEYSCAN_INT));
+
+    KEYSCAN->KEYSCAN_INT_CLR |= KEYSCAN_INT;
+
+    return;
+}
+
+/**
+  * \brief  Clear the specified KEYSCAN flag.
+  * \param  KEYSCANx: Selected KEYSCAN peripheral.
+  * \param  KEYSCAN_FLAG: Specifies the flag to clear.
+  *         This parameter can be any combination of the following values:
+  *         \arg KEYSCAN_FLAG_FIFOLIMIT
+  *         \arg KEYSCAN_FLAG_DATAFILTER
+  *         \arg KEYSCAN_FLAG_OVR
+  * \return none.
+  */
+void KEYSCAN_ClearFlags(KEYSCAN_TypeDef *KEYSCANx, uint32_t KEYSCAN_FLAG)
+{
+    /* Check the parameters */
+    assert_param(IS_KEYSCAN_PERIPH(KEYSCAN));
+    assert_param(IS_KEYSCAN_CLEAR_FLAG(KEYSCAN_FLAG));
+
+    KEYSCAN_INT_CLR_TypeDef keyscan_0x1c = {.d32 = KEYSCAN->KEYSCAN_INT_CLR};
+    if (KEYSCAN_FLAG & KEYSCAN_FLAG_FIFOLIMIT)
+    {
+        keyscan_0x1c.b.keyscan_fifo_limit_st_clr = 0x01;
+    }
+    if (KEYSCAN_FLAG & KEYSCAN_FLAG_DATAFILTER)
+    {
+        keyscan_0x1c.b.keyscan_fifo_data_filter_st_clr = 0x01;
+    }
+    if (KEYSCAN_FLAG & KEYSCAN_FLAG_OVR)
+    {
+        keyscan_0x1c.b.keyscan_fifo_ov_st_clr = 0x01;
+    }
+    KEYSCAN->KEYSCAN_INT_CLR = keyscan_0x1c.d32;
+
+    return;
+}
+
+/**
+  * \brief  Check whether the specified KEYSCAN flag is set.
+  * \param  KEYSCANx: Selected KEYSCAN peripheral.
+  * \param  KEYSCAN_FLAG: Specifies the flag to clear.
+  *         This parameter can be any combination of the following values:
+  *         \arg KEYSCAN_FLAG_FIFOLIMIT:
+  *         \arg KEYSCAN_FLAG_THRESHOLD:
+  *         \arg KEYSCAN_FLAG_OVER_READ:
+  *         \arg KEYSCAN_FLAG_SCAN_END:
+  *         \arg KEYSCAN_FLAG_FIFO_NOT_EMPTY:
+  *         \arg KEYSCAN_FLAG_ALL_RELEASE:
+  *         \arg KEYSCAN_FLAG_DATAFILTER:
+  *         \arg KEYSCAN_FLAG_OVR:
+  *         \arg KEYSCAN_FLAG_FULL:
+  *         \arg KEYSCAN_FLAG_EMPTY:
+  * \return none.
+  */
+FlagStatus KEYSCAN_GetFlagState(KEYSCAN_TypeDef *KEYSCANx, uint32_t KEYSCAN_FLAG)
+{
+    /* Check the parameters */
+    assert_param(IS_KEYSCAN_PERIPH(KEYSCAN));
+    assert_param(IS_KEYSCAN_FLAG(KEYSCAN_FLAG));
+
+    if ((KEYSCAN->KEYSCAN_INT_STS & KEYSCAN_FLAG) != 0)
+    {
+        return SET;
+    }
+    return RESET;
+}
+
+/**
+  * \brief  Read FIFO data.
+  * \param  KEYSCANx: Selected KEYSCAN peripheral.
+  * \return KEYSCAN FIFO data.
+  */
+uint16_t KEYSCAN_ReadFIFOData(KEYSCAN_TypeDef *KEYSCANx)
+{
+    /* Check the parameters */
+    assert_param(IS_KEYSCAN_PERIPH(KEYSCAN));
+
+    return (uint16_t)(KEYSCAN->KEYSCAN_FIFO_ENTRY);
+}
+
+/**
+ * \brief  Set manual scan trigger mode. This function is only effective when keyscan is manual scan mode.
+ *
+ * \param[in] KEYSCANx: Selected KEYSCAN peripheral.
+ * \param[in] manual_sel: Specifies the KEYSCAN manual trigger mode.
+ *                        This parameter can be one of the following values:
+ *                        \arg KEYSCAN_MANUAL_SEL_BIT: scan trigger by register (Call API KEYSCAN_Cmd).
+ *                        \arg KEYSCAN_MANUAL_SEL_KEY: scan trigger by key.
+ *
+ * \return None.
+ * \endcode
+ */
+void KEYSCAN_SetManualSelect(KEYSCAN_TypeDef *KEYSCANx, KEYSCANManualSel_TypeDef manual_sel)
+{
+    assert_param(IS_KEYSCAN_PERIPH(KEYSCAN));
+    assert_param(IS_KEYSCAN_MANUAL_SELECT(manual_sel));
+
+    KEYSCAN_CONFIG2_TypeDef keyscan_0x08 = {.d32 = KEYSCAN->KEYSCAN_CONFIG2};
+
+    /* Only manual mode can change manual select */
+    if (keyscan_0x08.b.keyscan_work_mode == KEYSCAN_MANUAL_SCAN_MODE)
+    {
+        keyscan_0x08.b.keyscan_manual_sel = manual_sel;
+        KEYSCAN->KEYSCAN_CONFIG2 = keyscan_0x08.d32;
+    }
+
+}
+
+/**
+ * \brief  Set preguard time. Preguard time = preguard_cnt * scan clock.
+ *
+ * \param[in] KEYSCANx: Selected KEYSCAN peripheral.
+ * \param[in] preguard_cnt: Specifies the preguard count. This parameter can be configured from 0 to 7.
+ *
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void keyscan_demo(void)
+ * {
+ *     KEYSCAN_SetPreGuardTime(KEYSCAN, 3);
+ * }
+ * \endcode
+ */
+void KEYSCAN_SetPreGuardTime(KEYSCAN_TypeDef *KEYSCANx, uint8_t preguard_cnt)
+{
+    assert_param(IS_KEYSCAN_PERIPH(KEYSCAN));
+
+    KEYSCAN_CLK_DIV_TypeDef keyscan_0x00 = {.d32 = KEYSCAN->KEYSCAN_CLK_DIV};
+    keyscan_0x00.b.keyscan_gt_pre_sel = preguard_cnt;
+    KEYSCAN->KEYSCAN_CLK_DIV = keyscan_0x00.d32;
+}
+
+/**
+ * \brief  Set postguard time. Postguard time = postguard_cnt * scan clock.
+ *
+ * \param[in] KEYSCANx: Selected KEYSCAN peripheral.
+ * \param[in] postguard_cnt: Specifies the postguard count. This parameter can be configured from 0 to 7.
+ *
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void keyscan_demo(void)
+ * {
+ *     KEYSCAN_SetPostGuardTime(KEYSCAN, 3);
+ * }
+ * \endcode
+ */
+void KEYSCAN_SetPostGuardTime(KEYSCAN_TypeDef *KEYSCANx, uint8_t postguard_cnt)
+{
+    assert_param(IS_KEYSCAN_PERIPH(KEYSCAN));
+
+    KEYSCAN_CLK_DIV_TypeDef keyscan_0x00 = {.d32 = KEYSCAN->KEYSCAN_CLK_DIV};
+    keyscan_0x00.b.keyscan_gt_post_sel = postguard_cnt;
+    KEYSCAN->KEYSCAN_CLK_DIV = keyscan_0x00.d32;
+}
+
+#if (KEYSCAN_SUPPORT_RAP_FUNCTION == 1)
+void KEYSCAN_RAPModeCmd(KEYSCAN_TypeDef *KEYSCANx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_KEYSCAN_PERIPH(KEYSCAN));
+
+    KEYSCAN_TASK_CTRL_TypeDef keyscan_0x38 = {.d32 = KEYSCAN->KEYSCAN_TASK_CTRL};
+    keyscan_0x38.b.rap_mode = NewState;
+    KEYSCAN->KEYSCAN_TASK_CTRL = keyscan_0x38.d32;
+
+    return;
+}
+
+void KEYSCAN_ActionTrigger(KEYSCAN_TypeDef *KEYSCANx, uint32_t Action)
+{
+    /* Check the parameters */
+    assert_param(IS_ADC_ALL_PERIPH(KEYSCAN));
+
+    KEYSCAN_TASK_CTRL_TypeDef keyscan_0x38 = {.d32 = KEYSCAN->KEYSCAN_TASK_CTRL};
+    if (Action == KEYSCAN_ACTION_MANUAL)
+    {
+        keyscan_0x38.b.task_manual = 0x1;
+    }
+    KEYSCAN->KEYSCAN_TASK_CTRL = keyscan_0x38.d32;
+
+    return;
+}
+
+#endif
+
+
diff --git a/bee/drivers/mac_802154/CMakeLists.txt b/bee/drivers/mac_802154/CMakeLists.txt
new file mode 100644
index 00000000..2383a901
--- /dev/null
+++ b/bee/drivers/mac_802154/CMakeLists.txt
@@ -0,0 +1,9 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_include_directories(rom)
+zephyr_include_directories(rom/portable/rtl87x2g)
+zephyr_include_directories(inc)
+zephyr_library_sources(src/mac_802154_frame_parser.c)
+zephyr_library_sources(src/mac_802154_xip.c)
+zephyr_code_relocate(FILES src/mac_802154_xip.c LOCATION ITCM)
diff --git a/bee/drivers/mac_802154/Kconfig b/bee/drivers/mac_802154/Kconfig
new file mode 100644
index 00000000..5d32e056
--- /dev/null
+++ b/bee/drivers/mac_802154/Kconfig
@@ -0,0 +1,8 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config REALTEK_BEE_MAC_802154
+	bool "Realtek Bee MCU mac 802154 driver"
+	default n
+	help
+	  This option enables the mac 802154 driver for Realtek Bee MCU.
diff --git a/bee/drivers/mac_802154/inc/mac_802154_frame_parser.h b/bee/drivers/mac_802154/inc/mac_802154_frame_parser.h
new file mode 100644
index 00000000..7a103479
--- /dev/null
+++ b/bee/drivers/mac_802154/inc/mac_802154_frame_parser.h
@@ -0,0 +1,412 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef MAC_802154_FRAME_PARSER_H
+#define MAC_802154_FRAME_PARSER_H
+
+#include <stdbool.h>
+#include <stdint.h>
+
+#define ACK_HEADER_WITH_PENDING      0x12                                         ///< The first byte of an ACK frame containing a pending bit.
+#define ACK_HEADER_WITHOUT_PENDING   0x02                                         ///< The first byte of an ACK frame without a pending bit.
+
+#define ACK_REQUEST_OFFSET           1                                            ///< Byte containing the ACK request bit (+1 for the frame length byte).
+#define ACK_REQUEST_BIT              (1 << 5)                                     ///< ACK request bit.
+
+#define DEST_ADDR_TYPE_OFFSET        2                                            ///< Byte containing the destination address type (+1 for the frame length byte).
+#define DEST_ADDR_TYPE_MASK          0x0c                                         ///< Mask of bits containing the destination address type.
+#define DEST_ADDR_TYPE_EXTENDED      0x0c                                         ///< Bits containing the extended destination address type.
+#define DEST_ADDR_TYPE_NONE          0x00                                         ///< Bits containing a not-present destination address type.
+#define DEST_ADDR_TYPE_SHORT         0x08                                         ///< Bits containing the short destination address type.
+#define DEST_ADDR_OFFSET             6                                            ///< Offset of the destination address in the Data frame (+1 for the frame length byte).
+
+#define DSN_OFFSET                   3                                            ///< Byte containing the DSN value (+1 for the frame length byte).
+#define DSN_SUPPRESS_OFFSET          2                                            ///< Byte containing the DSN suppression field.
+#define DSN_SUPPRESS_BIT             0x01                                         ///< Bits containing the DSN suppression field.
+
+#define FRAME_COUNTER_SUPPRESS_BIT   0x20                                         ///< Bit containing the Frame Counter Suppression field.
+
+#define FRAME_PENDING_OFFSET         1                                            ///< Byte containing a pending bit (+1 for the frame length byte).
+#define FRAME_PENDING_BIT            (1 << 4)                                     ///< Pending bit.
+
+#define FRAME_TYPE_OFFSET            1                                            ///< Byte containing the frame type bits (+1 for the frame length byte).
+#define FRAME_TYPE_MASK              0x07                                         ///< Mask of bits containing the frame type.
+#define FRAME_TYPE_ACK               0x02                                         ///< Bits containing the ACK frame type.
+#define FRAME_TYPE_BEACON            0x00                                         ///< Bits containing the Beacon frame type.
+#define FRAME_TYPE_COMMAND           0x03                                         ///< Bits containing the Command frame type.
+#define FRAME_TYPE_DATA              0x01                                         ///< Bits containing the Data frame type.
+#define FRAME_TYPE_EXTENDED          0x07                                         ///< Bits containing the Extended frame type.
+#define FRAME_TYPE_FRAGMENT          0x06                                         ///< Bits containing the Fragment or the Frak frame type.
+#define FRAME_TYPE_MULTIPURPOSE      0x05                                         ///< Bits containing the Multipurpose frame type.
+
+#define FRAME_VERSION_OFFSET         2                                            ///< Byte containing the frame version bits (+1 for the frame length byte).
+#define FRAME_VERSION_MASK           0x30                                         ///< Mask of bits containing the frame version.
+#define FRAME_VERSION_0              0x00                                         ///< Bits containing the frame version 0b00.
+#define FRAME_VERSION_1              0x10                                         ///< Bits containing the frame version 0b01.
+#define FRAME_VERSION_2              0x20                                         ///< Bits containing the frame version 0b10.
+#define FRAME_VERSION_3              0x30                                         ///< Bits containing the frame version 0b11.
+
+#define IE_HEADER_LENGTH_MASK        0x3f                                         ///< Mask of bits containing the length of an IE header content.
+#define IE_PRESENT_OFFSET            2                                            ///< Byte containing the IE Present bit.
+#define IE_PRESENT_BIT               0x02                                         ///< Bits containing the IE Present field.
+
+#define KEY_ID_MODE_MASK             0x18                                         ///< Mask of bits containing Key Identifier Mode in the Security Control field.
+#define KEY_ID_MODE_0                0                                            ///< Bits containing the 0x00 Key Identifier Mode.
+#define KEY_ID_MODE_1                0x08                                         ///< Bits containing the 0x01 Key Identifier Mode.
+#define KEY_ID_MODE_2                0x10                                         ///< Bits containing the 0x10 Key Identifier Mode.
+#define KEY_ID_MODE_3                0x18                                         ///< Bits containing the 0x11 Key Identifier Mode.
+
+#define MAC_CMD_ASSOC_REQ            0x01                                         ///< Command frame identifier for MAC Association request.
+#define MAC_CMD_ASSOC_RESP           0x02                                         ///< Command frame identifier for MAC Association response.
+#define MAC_CMD_DISASSOC_NOTIFY      0x03                                         ///< Command frame identifier for MAC Disaccociation notification.
+#define MAC_CMD_DATA_REQ             0x04                                         ///< Command frame identifier for MAC Data Requests.
+#define MAC_CMD_PANID_CONFLICT       0x05                                         ///< Command frame identifier for MAC PAN ID conflict notification.
+#define MAC_CMD_ORPHAN_NOTIFY        0x06                                         ///< Command frame identifier for MAC Orphan notification.
+#define MAC_CMD_BEACON_REQ           0x07                                         ///< Command frame identifier for MAC Beacon.
+#define MAC_CMD_COORD_REALIGN        0x08                                         ///< Command frame identifier for MAC Coordinator realignment.
+#define MAC_CMD_GTS_REQUEST          0x09                                         ///< Command frame identifier for MAC GTS request.
+
+#define PAN_ID_COMPR_OFFSET          1                                            ///< Byte containing the PAN ID compression bit (+1 for the frame length byte).
+#define PAN_ID_COMPR_MASK            0x40                                         ///< PAN ID compression bit.
+
+#define PAN_ID_OFFSET                4                                            ///< Offset of PAN ID in the Data frame (+1 for the frame length byte).
+
+#define PHR_OFFSET                   0                                            ///< Offset of the PHY header in a frame.
+
+#define SECURITY_ENABLED_OFFSET      1                                            ///< Byte containing the Security Enabled bit.
+#define SECURITY_ENABLED_BIT         0x08                                         ///< Bits containing the Security Enabled field.
+#define SECURITY_LEVEL_MASK          0x07                                         ///< Mask of bits containing the Security level field.
+#define SECURITY_LEVEL_MIC_32        0x01                                         ///< Bits containing the 32-bit Message Integrity Code (0b001).
+#define SECURITY_LEVEL_MIC_64        0x02                                         ///< Bits containing the 64-bit Message Integrity Code (0b010).
+#define SECURITY_LEVEL_MIC_128       0x03                                         ///< Bits containing the 128-bit Message Integrity Code (0b011).
+#define SECURITY_LEVEL_ENC_MIC_32    0x05                                         ///< Bits containing the 32-bit Encrypted Message Integrity Code (0b101).
+#define SECURITY_LEVEL_ENC_MIC_64    0x06                                         ///< Bits containing the 64-bit Encrypted Message Integrity Code (0b110).
+#define SECURITY_LEVEL_ENC_MIC_128   0x07                                         ///< Bits containing the 128-bit Encrypted Message Integrity Code (0b111).
+
+#define SRC_ADDR_TYPE_EXTENDED       0xc0                                         ///< Bits containing the extended source address type.
+#define SRC_ADDR_TYPE_NONE           0x00                                         ///< Bits containing a not-present source address type.
+#define SRC_ADDR_TYPE_MASK           0xc0                                         ///< Mask of bits containing the source address type.
+#define SRC_ADDR_TYPE_OFFSET         2                                            ///< Byte containing the source address type (+1 for the frame length byte).
+#define SRC_ADDR_TYPE_SHORT          0x80                                         ///< Bits containing the short source address type.
+
+#define SRC_ADDR_OFFSET_SHORT_DST    8                                            ///< Offset of the source address in the Data frame if the destination address is short.
+#define SRC_ADDR_OFFSET_EXTENDED_DST 14                                           ///< Offset of the source address in the Data frame if the destination address is extended.
+
+#define DSN_SIZE                     1                                            ///< Size of the Sequence Number field.
+#define FCF_SIZE                     2                                            ///< Size of the FCF field.
+#define FCS_SIZE                     2                                            ///< Size of the FCS field.
+#define FRAME_COUNTER_SIZE           4                                            ///< Size of the Frame Counter field.
+#define IE_HEADER_SIZE               4                                            ///< Size of the obligatory IE Header field elements, including the header termination.
+#define IMM_ACK_LENGTH               5                                            ///< Length of the ACK frame.
+#define KEY_ID_MODE_1_SIZE           1                                            ///< Size of the 0x01 Key Identifier Mode field.
+#define KEY_ID_MODE_2_SIZE           5                                            ///< Size of the 0x10 Key Identifier Mode field.
+#define KEY_ID_MODE_3_SIZE           9                                            ///< Size of the 0x11 Key Identifier Mode field.
+#define MAX_PACKET_SIZE              127                                          ///< Maximum size of the radio packet.
+#define MIC_32_SIZE                  4                                            ///< Size of MIC with the MIC-32 and ENC-MIC-32 security attributes.
+#define MIC_64_SIZE                  8                                            ///< Size of MIC with the MIC-64 and ENC-MIC-64 security attributes.
+#define MIC_128_SIZE                 16                                           ///< Size of MIC with the MIC-128 and ENC-MIC-128 security attributes.
+#define PAN_ID_SIZE                  2                                            ///< Size of the PAN ID.
+#define PHR_SIZE                     1                                            ///< Size of the PHR field.
+#define SECURITY_CONTROL_SIZE        1                                            ///< Size of the Security Control field.
+
+#define EXTENDED_ADDRESS_SIZE        8                                            ///< Size of the Extended Mac Address.
+#define SHORT_ADDRESS_SIZE           2                                            ///< Size of the Short Mac Address.
+
+#define TURNAROUND_TIME              192UL                                        ///< RX-to-TX or TX-to-RX turnaround time (aTurnaroundTime), in microseconds (us).
+#define CCA_TIME                     128UL                                        ///< Time required to perform CCA detection (aCcaTime), in microseconds (us).
+#define UNIT_BACKOFF_PERIOD          (TURNAROUND_TIME + CCA_TIME)                 ///< Number of symbols in the basic time period used by CSMA-CA algorithm (aUnitBackoffPeriod), in (us).
+
+#define PHY_US_PER_SYMBOL            16                                           ///< Duration of a single symbol in microseconds (us).
+#define PHY_SYMBOLS_PER_OCTET        2                                            ///< Number of symbols in a single byte (octet).
+#define PHY_SHR_SYMBOLS              10                                           ///< Number of symbols in the Synchronization Header (SHR).
+
+#define ED_RESULT_MAX                0xff                                         ///< Maximal ED result.
+
+#define BROADCAST_ADDRESS            ((uint8_t[SHORT_ADDRESS_SIZE]) {0xff, 0xff}) ///< Broadcast short address.
+
+#define MIN_SIFS_PERIOD_US           192                                          ///< Minimum Short IFS period default value in us.
+#define MIN_LIFS_PERIOD_US           640                                          ///< Minimum Long IFS period default value in us.
+#define MAX_SIFS_FRAME_SIZE          18                                           ///< Maximum frame length which can be followed by the Short Interframe Space.
+
+#define MAC_802154_FRAME_PARSER_INVALID_OFFSET 0xff
+
+/**
+ * @brief Structure that contains pointers to parts of MHR and details of MHR structure.
+ */
+typedef struct
+{
+    const uint8_t
+    *p_dst_panid;            ///< Pointer to the destination PAN ID field, or NULL if missing.
+    const uint8_t
+    *p_dst_addr;             ///< Pointer to the destination address field, or NULL if missing.
+    const uint8_t *p_src_panid;            ///< Pointer to the source PAN ID field, or NULL if missing.
+    const uint8_t *p_src_addr;             ///< Pointer to the source address field, or NULL if missing.
+    const uint8_t
+    *p_sec_ctrl;             ///< Pointer to the security control field, or NULL if missing.
+    uint8_t         dst_addr_size;         ///< Size of the destination address field.
+    uint8_t         src_addr_size;         ///< Size of the source address field.
+    uint8_t         addressing_end_offset; ///< Offset of the first byte following addressing fields.
+} mac_802154_frame_parser_mhr_data_t;
+
+/**
+ * @brief Determines if the destination address is extended.
+ *
+ * @param[in]   p_frame   Pointer to a frame to be checked.
+ *
+ * @retval  true   Destination address is extended.
+ * @retval  false  Destination address is not extended.
+ */
+bool mac_802154_frame_parser_dst_addr_is_extended(const uint8_t *p_frame);
+
+/**
+ * @brief Gets the destination address from the provided frame.
+ *
+ * @param[in]   p_frame             Pointer to a frame.
+ * @param[out]  p_dst_addr_extended Pointer to a value, which is true if the destination address
+ *                                  is extended. Otherwise, it is false.
+ *
+ * @returns  Pointer to the first byte of the destination address in @p p_frame.
+ *           NULL if the destination address cannot be retrieved.
+ */
+const uint8_t *mac_802154_frame_parser_dst_addr_get(const uint8_t *p_frame,
+                                                    bool           *p_dst_addr_extended);
+
+/**
+ * @brief Gets the offset of the destination address field in the provided frame.
+ *
+ * @param[in]   p_frame  Pointer to a frame.
+ *
+ * @returns  Offset in bytes of the destination address field, including one byte
+ *           of the frame length.
+ * @returns  Zero if the destination address cannot be retrieved.
+ *
+ */
+uint8_t mac_802154_frame_parser_dst_addr_offset_get(const uint8_t *p_frame);
+
+/**
+ * @brief Gets the destination PAN ID from the provided frame.
+ *
+ * @param[in]   p_frame  Pointer to a frame.
+ *
+ * @returns  Pointer to the first byte of the destination PAN ID in @p p_frame.
+ * @returns  NULL if the destination PAN ID cannot be retrieved.
+ *
+ */
+const uint8_t *mac_802154_frame_parser_dst_panid_get(const uint8_t *p_frame);
+
+/**
+ * @brief Gets the offset of the destination PAN ID field in the provided frame.
+ *
+ * @param[in]   p_frame  Pointer to a frame.
+ *
+ * @returns  Offset in bytes of the destination PAN ID field, including one byte
+ *           of the frame length.
+ * @returns  Zero in case the destination PAN ID cannot be retrieved.
+ *
+ */
+uint8_t mac_802154_frame_parser_dst_panid_offset_get(const uint8_t *p_frame);
+
+/**
+ * @brief Gets the offset of the end of the destination address fields.
+ *
+ * @param[in]   p_frame  Pointer to a frame.
+ *
+ * @returns  Offset of the first byte following the destination addressing fields in the MHR.
+ */
+uint8_t mac_802154_frame_parser_dst_addr_end_offset_get(const uint8_t *p_frame);
+
+/**
+ * @brief Determines if the source address is extended.
+ *
+ * @param[in]   p_frame   Pointer to a frame to check.
+ *
+ * @retval  true   The source address is extended.
+ * @retval  false  The source address is not extended.
+ *
+ */
+bool mac_802154_frame_parser_src_addr_is_extended(const uint8_t *p_frame);
+
+/**
+ * @brief Determines if the source address is short.
+ *
+ * @param[in]   p_frame   Pointer to a frame to check.
+ *
+ * @retval  true   The source address is short.
+ * @retval  false  The source address is not short.
+ *
+ */
+bool mac_802154_frame_parser_src_addr_is_short(const uint8_t *p_frame);
+
+/**
+ * @brief Gets the source address from the provided frame.
+ *
+ * @param[in]   p_frame             Pointer to a frame.
+ * @param[out]  p_src_addr_extended Pointer to a value, which is true if source address is extended.
+ *                                  Otherwise, it is false.
+ *
+ * @returns  Pointer to the first byte of the source address in @p p_frame.
+ * @returns  NULL if the source address cannot be retrieved.
+ *
+ */
+const uint8_t *mac_802154_frame_parser_src_addr_get(const uint8_t *p_frame,
+                                                    bool           *p_src_addr_extended);
+
+/**
+ * @brief Gets the offset of the source address field in the provided frame.
+ *
+ * @param[in]   p_frame  Pointer to a frame.
+ *
+ * @returns  Offset in bytes of the source address field, including one byte of the frame length.
+ * @returns  Zero if the source address cannot be retrieved.
+ *
+ */
+uint8_t mac_802154_frame_parser_src_addr_offset_get(const uint8_t *p_frame);
+
+/**
+ * @brief Gets the source PAN ID from the provided frame.
+ *
+ * @param[in]   p_frame   Pointer to a frame.
+ *
+ * @returns  Pointer to the first byte of the source PAN ID in @p p_frame.
+ * @returns  NULL if the source PAN ID cannot be retrieved or if it is compressed.
+ *
+ */
+const uint8_t *mac_802154_frame_parser_src_panid_get(const uint8_t *p_frame);
+
+/**
+ * @brief Gets the offset of the source PAN ID field in the provided frame.
+ *
+ * @param[in]   p_frame  Pointer to a frame.
+ *
+ * @returns  Offset in bytes of the source PAN ID field, including one byte of the frame length.
+ * @returns  Zero if the source PAN ID cannot be retrieved or is compressed.
+ *
+ */
+uint8_t mac_802154_frame_parser_src_panid_offset_get(const uint8_t *p_frame);
+
+/**
+ * @brief Gets the pointer and the details of MHR parts of a given frame.
+ *
+ * @param[in]  p_frame   Pointer to a frame to parse.
+ * @param[out] p_fields  Pointer to a structure that contains pointers and details
+ *                       of the parsed frame.
+ *
+ * @retval true   Frame parsed correctly.
+ * @retval false  Parse error. @p p_fields values are invalid.
+ *
+ */
+bool mac_802154_frame_parser_mhr_parse(const uint8_t                       *p_frame,
+                                       mac_802154_frame_parser_mhr_data_t *p_fields);
+
+/**
+ * @brief Gets the security control field in the provided frame.
+ *
+ * @param[in]   p_frame  Pointer to a frame.
+ *
+ * @returns  Pointer to the first byte of the security control field in @p p_frame.
+ * @returns  NULL if the security control cannot be retrieved (that is, security is not enabled).
+ *
+ */
+const uint8_t *mac_802154_frame_parser_sec_ctrl_get(const uint8_t *p_frame);
+
+/**
+ * @brief Gets the offset of the first byte after the addressing fields in MHR.
+ *
+ * @param[in]   p_frame  Pointer to a frame.
+ *
+ * @returns  Offset in bytes of the first byte after the addressing fields in MHR.
+ */
+uint8_t mac_802154_frame_parser_addressing_end_offset_get(const uint8_t *p_frame);
+
+/**
+ * @brief Gets the offset of the security control field in the provided frame.
+ *
+ * @param[in]   p_frame  Pointer to a frame.
+ *
+ * @returns  Offset in bytes of the security control field, including one byte of the frame length.
+ * @returns  Zero if the security control cannot be retrieved (that is, security is not enabled).
+ *
+ */
+uint8_t mac_802154_frame_parser_sec_ctrl_offset_get(const uint8_t *p_frame);
+
+/**
+ * @brief Gets the key identifier field in the provided frame.
+ *
+ * @param[in]   p_frame  Pointer to a frame.
+ *
+ * @returns  Pointer to the first byte of the key identifier field in @p p_frame.
+ * @returns  NULL if the key identifier cannot be retrieved (that is, security is not enabled).
+ *
+ */
+const uint8_t *mac_802154_frame_parser_key_id_get(const uint8_t *p_frame);
+
+/**
+ * @brief Gets the offset of the key identifier field in the provided frame.
+ *
+ * @param[in]   p_frame  Pointer to a frame.
+ *
+ * @returns  Offset in bytes of the key identifier field, including one byte of the frame length.
+ * @returns  Zero if the key identifier cannot be retrieved (that is, security is not enabled).
+ *
+ */
+uint8_t mac_802154_frame_parser_key_id_offset_get(const uint8_t *p_frame);
+
+/**
+ * @brief Determines if the sequence number suppression bit is set.
+ *
+ * @param[in]   p_frame  Pointer to a frame.
+ *
+ * @retval  true   Sequence number suppression bit is set.
+ * @retval  false  Sequence number suppression bit is not set.
+ *
+ */
+bool mac_802154_frame_parser_dsn_suppress_bit_is_set(const uint8_t *p_frame);
+
+/**
+ * @brief Determines if the IE present bit is set.
+ *
+ * @param[in]   p_frame  Pointer to a frame.
+ *
+ * @retval  true   IE present bit is set.
+ * @retval  false  IE present bit is not set.
+ *
+ */
+bool mac_802154_frame_parser_ie_present_bit_is_set(const uint8_t *p_frame);
+
+/**
+ * @brief Determines if the Ack Request (AR) bit is set.
+ *
+ * @param[in]   p_frame  Pointer to a frame.
+ *
+ * @retval  true   AR bit is set.
+ * @retval  false  AR bit is not set.
+ *
+ */
+bool mac_802154_frame_parser_ar_bit_is_set(const uint8_t *p_frame);
+
+/**
+ * @brief Gets the IE header field in the provided frame.
+ *
+ * @param[in]   p_frame  Pointer to a frame.
+ *
+ * @returns  Pointer to the first byte of the IE header field in @p p_frame.
+ * @returns  NULL if the IE header cannot be retrieved (that is, the IE header is not present).
+ *
+ */
+const uint8_t *mac_802154_frame_parser_ie_header_get(const uint8_t *p_frame);
+
+/**
+ * @brief Gets the offset of the IE header field in the provided frame.
+ *
+ * @param[in]   p_frame  Pointer to a frame.
+ *
+ * @returns  Offset in bytes of the IE header field, including one byte of the frame length.
+ * @returns  Zero if the IE header cannot be retrieved (that is, the IE header is not present).
+ *
+ */
+uint8_t mac_802154_frame_parser_ie_header_offset_get(const uint8_t *p_frame);
+
+#endif // MAC_802154_FRAME_PARSER_H
diff --git a/bee/drivers/mac_802154/rom/frame_802154.h b/bee/drivers/mac_802154/rom/frame_802154.h
new file mode 100644
index 00000000..f77923a1
--- /dev/null
+++ b/bee/drivers/mac_802154/rom/frame_802154.h
@@ -0,0 +1,108 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**************************************************************************//**
+ * @file     frame_802154.h
+ * @brief    Inter-Processor communication definition for IEEE802.15.4 MAC/PHY
+ *           control cross platorm.
+ *
+ * @version  V1.00
+ * @date     2023-05-31
+ *
+ * @note
+ *
+ ******************************************************************************/
+
+#ifndef _FRAME_802154_H_
+#define _FRAME_802154_H_
+
+/**
+  \brief  Defines MAC Frame Type
+*/
+enum mac_frame_type_e
+{
+    FRAME_TYPE_BEACON           = 0,
+    FRAME_TYPE_DATA             = 1,
+    FRAME_TYPE_ACK              = 2,
+    FRAME_TYPE_COMMAND          = 3,
+    FRAME_TYPE_RESERVED         = 4,
+    FRAME_TYPE_MULTIPURPOSE     = 6,
+    FRAME_TYPE_FRAGMENT         = 6,
+    FRAME_TYPE_EXTENDED         = 7,
+};
+
+/**
+  \brief  Defines Destination Addressing Mode and Source Addressing Mode fields Type
+*/
+enum mac_addr_mode_e
+{
+    ADDR_MODE_NONE              = 0,
+    ADDR_MODE_RESERVED          = 1,
+    ADDR_MODE_SHORT             = 2,
+    ADDR_MODE_LONG              = 3,
+};
+
+/**
+  \brief  Defines Frame Version field
+*/
+enum mac_frame_version_e
+{
+    FRAME_VER_2003              = 0,
+    FRAME_VER_2006              = 1,
+    FRAME_VER_2015              = 2,
+    FRAME_VER_RESERVED          = 3,
+};
+
+/**
+  \brief  Defines Security levels
+*/
+enum mac_security_level_e
+{
+    SEC_LEVEL_NONE              = 0,
+    SEC_LEVEL_MIC32             = 1,
+    SEC_LEVEL_MIC64             = 2,
+    SEC_LEVEL_MIC128            = 3,
+    SEC_LEVEL_ENC               = 4,
+    SEC_LEVEL_ENC_MIC32         = 5,
+    SEC_LEVEL_ENC_MIC64         = 6,
+    SEC_LEVEL_ENC_MIC128        = 7,
+};
+
+/**
+  \brief  Defines Key Identifier Mode
+*/
+enum mac_key_id_mode_e
+{
+    KEY_ID_MODE_IMPLICIT        = 0,
+    KEY_ID_MODE_1B              = 1,
+    KEY_ID_MODE_5B              = 2,
+    KEY_ID_MODE_9B              = 3,
+};
+
+#define SEC_KEY_LEN             (16)
+#define SEC_NONCE_LEN           (13)
+
+typedef union
+{
+    uint8_t bytes[2]; /*!< frame control data in byte */
+
+    struct
+    {
+        uint16_t frm_type : 3; /*!< [0..2] Transmit frame type */
+        uint16_t sec_en : 1; /*!< [3..3] security enabled */
+        uint16_t frm_pending : 1; /*!< [4..4] frame pending */
+        uint16_t ack_req : 1;  /*!< [5..5] ACK request */
+        uint16_t panid_comp : 1; /*!< [6..6] PANID compression */
+        uint16_t reserved1 : 1; /*!< [7..7] reserved */
+        uint16_t sn_suppr : 1; /*!< [8..8] sequence number suppression */
+        uint16_t ie_present : 1; /*!< [9..9] IE present */
+        uint16_t dest_addr_mode : 2; /*!< [11..10] destination address mode */
+        uint16_t frm_ver : 2; /*!< [13..12] frame version */
+        uint16_t src_addr_mode : 2; /*!< [15..14] source address mode */
+    } bits;  /*!< bit fields for frame control */
+} frame_control_t, *pframe_control_t;
+
+#endif /* _FRAME_802154_H_ */
diff --git a/bee/drivers/mac_802154/rom/mac_data_type.h b/bee/drivers/mac_802154/rom/mac_data_type.h
new file mode 100644
index 00000000..c0e1c2b6
--- /dev/null
+++ b/bee/drivers/mac_802154/rom/mac_data_type.h
@@ -0,0 +1,600 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**************************************************************************//**
+ * @file     mac_data_type.h
+ * @brief    IEEE802.15.4 MAC/PHY driver data structure type definition.
+ *
+ * @version  V1.00
+ * @date     2023-06-12
+ *
+ * @note
+ *
+ ******************************************************************************/
+
+#ifndef _MAC_DATA_TYPE_H_
+#define _MAC_DATA_TYPE_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "stdint.h"
+#include "string.h"
+#include "zb_section.h"
+
+#define MAC_ENTRY_PRIO_MIN          (-1)
+
+#define MAC_ENTRY_PRIO_NORMAL       (0)
+
+#define MAC_ENTRY_PRIO_CSL          (512)
+
+#define MAC_DEFAULT_CHANNEL         (14)  // the default channel after MAC is initialized
+#define MAX_CHANNEL_NUM             (16)  // max supported channel number (CH11 ~ CH26)
+
+/**
+  \brief RX Frame type filter reset value, accept Beacon, Data and Command frame type
+*/
+#define MAC_RXFRMTYPE_RSTVAL        (0x0b)
+
+/**
+  \brief RX Frame type filter reset value, accept Enh-Beacon, Enh-Ack, Enh-Data and Enh-Command frame type
+*/
+#define MAC_RXENHFRMTYPE_RSTVAL     (0x0f)
+
+/**
+  \brief Default aMinLIFSPeriod value
+*/
+#define MAC_MINLIFS_RSTVAL          (0x21)
+
+#define MAC_NONCE_LENGTH            (13)
+#define MAC_KEY_LENGTH              (16)
+
+/**
+  \brief  MAC Frame parameters related definition
+*/
+#define MAC_MAX_TX_FRM_LEN          (125)     // Maximum length(byte) of a TX frame
+#define MAC_MIN_TX_FRM_LEN          (1)       // Minimum length(byte) of a TX frame
+
+/**
+  \brief  Security Key buffer base address
+*/
+#define KEYBUF_OFFSET_NORMAL        (0)
+#define KEYBUF_OFFSET_GTS1          (0x10)
+#define KEYBUF_OFFSET_GTS2_BCN      (0x20)
+#define KEYBUF_OFFSET_RX            (0x30)
+
+#define MAC_NORMAL_KEY              (MAC_KEY_FIFO_BASE_ADDR + KEYBUF_OFFSET_NORMAL)
+#define MAC_GTS1_KEY                (MAC_KEY_FIFO_BASE_ADDR + KEYBUF_OFFSET_GTS1)
+#define MAC_GTS2_BCN_KEY            (MAC_KEY_FIFO_BASE_ADDR + KEYBUF_OFFSET_GTS2_BCN)
+#define MAC_RX_KEY                  (MAC_KEY_FIFO_BASE_ADDR + KEYBUF_OFFSET_RX)
+
+/**
+  \brief  TX Normal FIFO related definition
+*/
+#define MAC_TX_FIFO_SIZE            (127)
+
+// TODO
+#define MAC_TXN_HLEN_IDX            (0x00) //header length offset
+#define MAC_TXN_FLEN_IDX            (0x01) //frame length offset
+#define MAC_TXN_FRM_IDX             (0x02)
+
+#define MAC_TXN_HLEN                (MAC_TXN_BASE_ADDR + MAC_TXN_HLEN_IDX)
+#define MAC_TXN_FLEN                (MAC_TXN_BASE_ADDR + MAC_TXN_FLEN_IDX)
+#define MAC_TXN_FRM                 (MAC_TXN_BASE_ADDR + MAC_TXN_FRM_IDX)
+
+/**
+  \brief  TX Beacon FIFO related definition
+*/
+#define MAC_TXB_FIFO_SIZE           (127)
+
+#define MAC_TXB_HLEN_IDX            (0x00) //header length
+#define MAC_TXB_FLEN_IDX            (0x01) //frame length
+#define MAC_TXB_FRM_IDX             (0x02)
+
+#define MAC_TXB_HLEN                (MAC_TXB_BASE_ADDR + MAC_TXB_HLEN_IDX)
+#define MAC_TXB_FLEN                (MAC_TXB_BASE_ADDR + MAC_TXB_FLEN_IDX)
+#define MAC_TXB_FRM                 (MAC_TXB_BASE_ADDR + MAC_TXB_FRM_IDX)
+
+/**
+  \brief  GTS1 TX FIFO related definition
+*/
+#define MAC_TXG1_FIFO_SIZE          (127)
+
+#define MAC_TXG1_HLEN_IDX           (0x00) //header length
+#define MAC_TXG1_FLEN_IDX           (0x01) //frame length
+#define MAC_TXG1_FRM_IDX            (0x02)
+
+#define MAC_TXG1_HLEN               (MAC_TXG1_BASE_ADDR + MAC_TXG1_HLEN_IDX)
+#define MAC_TXG1_FLEN               (MAC_TXG1_BASE_ADDR + MAC_TXG1_FLEN_IDX)
+#define MAC_TXG1_FRM                (MAC_TXG1_BASE_ADDR + MAC_TXG1_FRM_IDX)
+
+/**
+  \brief  GTS2 TX FIFO related definition
+*/
+#define MAC_TXG2_FIFO_SIZE          (127)
+
+#define MAC_TXG2_HLEN_IDX           (0x00)
+#define MAC_TXG2_FLEN_IDX           (0x01)
+#define MAC_TXG2_FRM_IDX            (0x02)
+
+#define MAC_TXG2_HLEN               (MAC_TXG2_BASE_ADDR + MAC_TXG2_HLEN_IDX)
+#define MAC_TXG2_FLEN               (MAC_TXG2_BASE_ADDR + MAC_TXG2_FLEN_IDX)
+#define MAC_TXG2_FRM                (MAC_TXG2_BASE_ADDR + MAC_TXG2_FRM_IDX)
+
+/**
+  \brief  RX FIFO related definition
+*/
+#define MAC_RX_FIFO_SIZE            (144)
+
+#define MAC_RX_FLEN_IDX             (0x00)
+#define MAC_RX_FRM_IDX              (0x01)
+
+#define MAC_RX_FLEN                 (MAC_RX_BASE_ADDR + MAC_RX_FLEN_IDX)
+#define MAC_RX_FRM                  (MAC_RX_BASE_ADDR + MAC_RX_FRM_IDX)
+
+/**
+  \brief  BT Slot Time
+*/
+#define BT_SLOT_TIME_US             (625)
+#define MAX_BT_CLOCK_COUNTER        (0x400000UL * BT_SLOT_TIME_US)  // 22-bits BT slot counter
+
+/**
+  \brief  PHY Timing Paramters
+*/
+#define PHY_SYMBOL_TIME_US          (16)    /* 1 symbol time in us */
+#define PHY_CCA_RXON_DELAY_US       (166)   /* CCA RX ON PHY settle down delay in us,
+                                               controlled by MAC.phy_trx_dly_b.rxon_delay  */
+#define PHY_RXON2CCADT_DELAY_US     (10)    /* RX ON to CCADT delay in us, controlled by
+                                               MAC.rx_set1_b.rxon2ccadt_dly */
+#define PHY_CCACHKPT_SYMB           (9)     /* CCA check duration takes in Symbol time,
+                                               controlled by MAC.txprm_b.ccachkp */
+#define PHY_TXON_DELAY_US           (122)   /* RX to TX turnaround time is us, controlled by
+                                               MAC.phy_trx_dly_b.txon_delay */
+#define PHY_RX_TO_TX_DELAY_US       (120)   /* RX On to TX On delay time is us, controlled by
+                                               MAC.phy_to_dly_b.rx2tx_delay */
+#define PHY_HDR_SYMBOL_TIME_US      (PHY_SYMBOL_TIME_US*12)
+#define PREAMBLE_TO_RX_TSTAMP_US    (PHY_SYMBOL_TIME_US*11) /* the time offset from the preamble of RX frame to
+                                                               the RX Time stamp is latched */
+#define PHY_TX_LATENCY_US           (3)     /* MAC TX to RF TX latency */
+#define PHY_RX_LATENCY_US           (23)    /* RF RX to MAC RX latency */
+#define PHY_GNT_PREPARE_TIME_BTCLK  (3)     /* request a high prio grant request as least 3 btclk */
+
+#define ED_SCAN_RNDDUR_8SYMB        (120)   /* how many 8-symbols for a ED scan round duration */
+#define ED_SCAN_RNDDUR_US           (ED_SCAN_RNDDUR_8SYMB * 8 * 16) /* the duration, in us, of each ED Scan round */
+#define ED_SCAN_INVALID_RET         (128)  /* indicates an invalid ED level return value */
+#define ED_SCAN_ERR_MASK            (MAC_ed_scan_ctrl0_ed_scan_encounter_tx_trig_sts_Msk |\
+                                     MAC_ed_scan_ctrl0_scan_fw_cancel_sts_Msk |\
+                                     MAC_ed_scan_ctrl0_scan_gnt_deassert_sts_Msk |\
+                                     MAC_ed_scan_ctrl0_scan_ed_vld_tmo_sts_Msk)
+#define ED_SCAN_ERR_RESOURCE        (0x80)
+
+#define BT_CLK_OVFLW_WATCH_TIMER    (3)     /* BT clock timer source for BT Clock counter overflow watching */
+
+#define MAC_INVALID_TIMER_ID        (0xFF)  /* to indicate an invalid Timer ID */
+#define MAC_TIMER_HW_SRC            (2)     /* BT clock timer source for MAC software timer */
+
+#define SHORT_SRC_ADDR_MATCH_ENTRY_NUM  (32)  /* define the number of short address match entry of source
+                                                 address match filter */
+#define EXT_SRC_ADDR_MATCH_ENTRY_NUM    (16)  /* define the number of short address match entry of
+                                                 source address match filter */
+
+#define EPOCH_32BIT_US              (1ULL << 32)
+#define EPOCH_FROM_TIME(time)       ((time) & ((uint64_t)UINT32_MAX << 32))
+
+#define MILLI_SECOND_PER_8US        (125)
+#define GNT_FAILED_RETRY_MAXCNT     (4)
+
+#define PTA_TICK_TIME_US_MAX        (0x1000)  /* max time of a PTA duty control tick, in us */
+#define PTA_DUTY_TIME_TICKS_MAX     (0x100)   /* max time of a PTA high/low duty time period, in unit of ticks */
+
+#define MAC_MASK_ALL_INTERRUPT      (0x0000FFFFUL)    /* to mask all MAC interrupt */
+
+typedef uint8_t bool_t;
+
+/**
+  \brief TX FIFO data structure
+*/
+typedef struct mac_tx_fifo_s
+{
+    uint8_t hdr_len;    /* header length, this length indicating the plan-text data length for a frame security operation */
+    uint8_t frm_len;    /* frame length, indicating the total length of PHY payload, CRC is not included */
+    uint8_t payload[MAC_MAX_TX_FRM_LEN];  /* PHY payload */
+} mac_txfifo_t, *pmac_txfifo_t;
+
+/**
+  \brief RX FIFO data structure
+*/
+typedef struct mac_rxfifo_s
+{
+    uint8_t frm_len;    /* frame length, indicating the total length of PHY payload, CRC is not included */
+    uint8_t payload[MAC_RX_FIFO_SIZE - 1];  /* PHY payload */
+} mac_rxfifo_t, *pmac_rxfifo_t;
+
+/**
+  \brief TX/RX Time Stamp (BT Native clock[21:1] + Clock Counter) data structure
+*/
+typedef struct mac_bt_clk_s
+{
+    uint32_t bt_clk_counter: 10;    /*!< [9..0] BT clock counter in 1 us unit */
+    uint32_t bt_native_clk: 22;     /*!< [31..10] BT native clock[21:1] in unit of BT slot */
+} mac_bt_clk_t, *pmac_bt_clk_t;
+
+typedef struct __attribute__((packed)) mac_rxfifo_tail_s
+{
+    uint8_t lqi;    /*!< the Link Quality index of this received frame report from modem */
+    uint16_t rssi;  /*!< the radio signal strength index of this received frame report from modem */
+    union
+    {
+        mac_bt_clk_t bt_time;
+        uint32_t mac_time;
+    };
+    uint8_t sf_count[3];  /* Superframe counter */
+} mac_rxfifo_tail_t, *pmac_rxfifo_tail_t;
+
+/**
+  \brief Security Control of Auxiliary security header data structure
+*/
+typedef struct aux_security_ctrl_s
+{
+    uint8_t sec_lv: 3;          /*!< [2..0] Security Level */
+    uint8_t key_id_mod: 2;      /*!< [4..3] Key Identifier Mode */
+    uint8_t frm_ctr_suprs: 1;   /*!< [5..5] Frame Counter Suppression */
+    uint8_t : 2;
+} aux_security_ctrl_t, *paux_security_ctrl_t;
+
+/**
+  \brief Auxiliary security header data structure
+*/
+typedef struct __attribute__((packed)) aux_security_hdr_s
+{
+    union
+    {
+        uint8_t security_ctrl;    /*!< Security Control */
+        aux_security_ctrl_t security_ctrl_b;
+    };
+    uint32_t frm_ctr;           /*!< Frame Counter */
+    uint8_t key_id[9];           /*!< Key Identifier */
+} aux_security_hdr_t, *paux_security_hdr_t;
+
+typedef void (*mac_callback_t)(void *parg);
+
+/**
+  \brief MAC Software Timer handler structure
+*/
+typedef struct mac_timer_handle_s
+{
+    mac_callback_t timer_callback;  /* callback function on timeout event */
+    void *callback_arg; /* argument of callback function */
+    uint32_t timeout; /* the timestamp (in us format of BT clock) to trigger timeout */
+    void *pnext;  /* next timer handle */
+    struct
+    {
+        uint32_t timer_id: 8;    /*!< [7..0] Timer index of this timer */
+        uint32_t is_free: 1;    /*!< [8..8] is this timer handle free */
+        uint32_t is_start: 1;   /*!< [9..9] is this timer running */
+        uint32_t is_timeout: 1; /*!< [10..10] is this timer timeout triggered */
+    } timer_ctrl;
+} mac_timer_handle_t, *pmac_timer_handle_t;
+
+/**
+  \brief flags of RX frame early interrupt processing
+*/
+typedef struct mac_rx_early_sts_s
+{
+    uint8_t enh_ack_tx_penging: 1;    /*!< [0..0] enh-ack tx is pending (on GTS FIFO) */
+    uint8_t : 7;     /*!< [7..1] reserved */
+} mac_rx_early_sts_t, *pmac_rx_early_sts_t;
+
+/**
+  \brief  Defines ED Scan State
+*/
+typedef enum mac_ed_scan_state_e
+{
+    MAC_EDS_STOPPED = 0x00,
+    MAC_EDS_PENDING = 0x01,
+    MAC_EDS_RUNNING = 0x02
+} mac_ed_scan_state_t;
+
+/**
+  \brief  Defines MAC/PHY State
+*/
+typedef enum mac_radio_state_e
+{
+    MAC_RADIO_STATE_DISABLED = 0x00,  // disabled (initial)
+    MAC_RADIO_STATE_INACTIVE = 0x01,  // not active
+    MAC_RADIO_STATE_W4PHYGNT = 0x02,  // waiting for PHY grant
+    MAC_RADIO_STATE_RX = 0x03,        // Receiving
+    MAC_RADIO_STATE_TX = 0x04,        // Transmitting
+    MAC_RADIO_STATE_SCAN = 0x05,      // ED Scanning
+} mac_radio_state_t;
+
+/**
+  \brief  Defines BT Clock Timer ID
+*/
+typedef enum mac_bt_timer_id_e
+{
+    MAC_BT_TIMER0 = 0,
+    MAC_BT_TIMER1 = 1,
+    MAC_BT_TIMER2 = 2,
+    MAC_BT_TIMER3 = 3,
+
+    MAC_BT_TIMER_NUM = 4
+} mac_bt_timer_id_t;
+
+typedef struct tx_pending_sts_s
+{
+    uint8_t txn: 1;           /*!< [0..0] TX Normal FIFO trigger pending */
+    uint8_t tgs1: 1;          /*!< [1..1] TX GTS1 FIFO trigger pending */
+    uint8_t tgs2: 1;          /*!< [2..2] TX GTS2 FIFO trigger pending */
+    uint8_t txb: 1;           /*!< [3..3] TX Beacon FIFO trigger pending */
+    uint8_t : 4;
+} tx_pending_sts_t;
+
+typedef void (*mac_ed_scan_callback_t)(int8_t peak_ed_level, int8_t avrg_ed_level, uint8_t status);
+/**
+  \brief Energy Scan States structure
+*/
+typedef struct mac_ed_scan_states_s
+{
+    uint8_t state;    /* current state of ED scan */
+    uint8_t channel;  /* channel for ED scan */
+    uint8_t peak_ed_level;  /* the peak ED level of each ED scan round during
+                               the whole ED scan process */
+    uint32_t duration_us;   /* duration (unit of us) for ED scan */
+    uint32_t ed_level_sum;  /* sum of ED level for each ED scan round */
+    uint32_t ed_scan_rounds;  /* ED scan round counter */
+    mac_ed_scan_callback_t callback;  /* the callback function for ED scan done */
+} mac_ed_scan_states_t, *pmac_ed_scan_states_t;
+
+/**
+  \brief  Defines RF transceiver state
+*/
+enum mac_transceiver_state_e
+{
+    TRANSCEIVER_TRX_AUTO = 0,
+    TRANSCEIVER_RX_ON = 1,
+    TRANSCEIVER_TX_ON = 2,
+    TRANSCEIVER_TRX_OFF = 3,
+
+    TRANSCEIVER_STATE_MAX = 4
+};
+
+/**
+  \brief  Defines MAC Security level of version 2006
+*/
+enum mac_security_level_2006_e
+{
+    AES_NONE            = 0,
+    AES_MIC_32          = 1,
+    AES_MIC_64          = 2,
+    AES_MIC_128         = 3,
+    AES_ENC             = 4,
+    AES_ENC_MIC_32      = 5,
+    AES_ENC_MIC_64      = 6,
+    AES_ENC_MIC_128     = 7,
+
+    MAX_SEC_LEVEL       = 8
+};
+
+/**
+  \brief  Defines MAC Security level of version 2003
+*/
+enum mac_security_level_2003_e
+{
+    AES_CTR             = 1,
+    AES_CCM_128         = 2,
+    AES_CCM_64          = 3,
+    AES_CCM_32          = 4,
+    AES_CBC_MAC_128     = 5,
+    AES_CBC_MAC_64      = 6,
+    AES_CBC_MAC_32      = 7
+};
+
+/**
+  \brief  Defines MAC function execution result
+*/
+typedef enum mac_status_e
+{
+    MAC_STS_SUCCESS = 0x00,
+    MAC_STS_FAILURE = 0x01,
+    MAC_STS_CHANNEL_BUSY = 0x02,
+    MAC_STS_RETRY_EXCEED = 0x03,
+    MAC_STS_DATA_LEN_ERROR = 0x04,
+    MAC_STS_UNSUPPORT_SECURITY_MODE = 0x05,
+    MAC_STS_INVALID_PARAMETER = 0x6,
+    MAC_STS_SECURITY_FAILED = 0x7,
+    MAC_STS_TEMPORARY_UNAVAILABLE = 0x8,
+    MAC_STS_TRANSMISSION_TIME_NOT_ENOUGH = 0x9,
+    MAC_STS_FREQUENCY_NOT_SUPPORT = 0xa,
+    MAC_STS_PHY_GRANT_FAILED = 0xb,
+    MAC_STS_TIMEOUT = 0x0c,
+    MAC_STS_CANCELED = 0x0d,
+    MAC_STS_PENDING = 0x0e,
+    MAC_STS_HW_LIMIT = 0x0f
+} mac_status_t;
+
+/**
+  \brief  Defines MAC Power saving mode
+*/
+typedef enum mac_power_mode_e
+{
+    MAC_STANDBY_MODE = 0x00,
+    MAC_DEEP_SLEEP_MODE = 0x01,
+    MAC_POWER_DOWN_MODE = 0x03
+} mac_power_mode_t;
+
+/**
+  \brief  Defines MAC CCA mode
+*/
+typedef enum mac_cca_mode_e
+{
+    MAC_CCA_NONE = 0,
+    MAC_CCA_ED = 1,
+    MAC_CCA_CS = 2,
+    MAC_CCA_CS_ED = 3,
+
+    MAC_CCA_CS_ED_AND = 4,
+} mac_cca_mode_t;
+
+/**
+  \brief  Defines ZB MAC control RF mode selection
+*/
+typedef enum mac_rf_mode_e
+{
+    RF_IQM = 0,
+    RF_TPM = 1,
+
+    RF_MODE_NUM
+} mac_rf_mode_t;
+
+/**
+  \brief  Defines RX Frame Filter
+*/
+typedef enum mac_rx_frame_filter_e
+{
+    MAC_RX_DROP_ALL = 0x00,
+    MAC_RX_ACCEPT_BEACON = 0x01,
+    MAC_RX_ACCEPT_DATA = 0x02,
+    MAC_RX_ACCEPT_ACK = 0x04,
+    MAC_RX_ACCEPT_COMMAND = 0x08
+} mac_rx_frame_filter_t;
+
+/**
+  \brief  Defines RX Frame Source Address mode
+*/
+typedef enum mac_rx_frame_sadr_mode_e
+{
+    MAC_RX_SADR_MODE_RSV0 = 0,
+    MAC_RX_SADR_MODE_RSV1 = 1,
+    MAC_RX_SADR_MODE_SHORT = 2,
+    MAC_RX_SADR_MODE_LONG = 3
+} mac_rx_frame_sadr_mode_t;
+
+/**
+  \brief  Defines MAC TX/RX Timestamp timer
+*/
+typedef enum mac_timestamp_tid_e
+{
+    TIMER_ID_MAC = 0,    /* the 16-bits MAC free-run downcounter in 8us unit */
+    TIMER_ID_BT = 1,     /* the BT clock: 27-bits native clock in 625us unit +
+                         10-bits clock counter in 1us unit */
+    TIMER_ID_INV = 2     // invalid timestamp timer
+} mac_timestamp_tid_t;
+
+/**
+  \brief  Defines the mode of auto set pending bit of Imm-Ack
+*/
+typedef enum mac_auto_ack_pending_bit_mode_e
+{
+    AUTO_ACK_PENDING_MODE_ZIGBEE = 0,
+    AUTO_ACK_PENDING_MODE_THREAD = 1,
+} mac_auto_ack_pending_bit_mode_t;
+
+/**
+  \brief  Source Address Match entry type
+*/
+typedef enum mac_src_addr_match_entry_type_e
+{
+    SRC_MATCH_SHORT = 0,    /* Short address match filter entry type */
+    SRC_MATCH_LONG = 1,     /* Long address match filter entry type */
+} mac_src_addr_match_entry_type_t;
+
+/**
+  \brief  The ACK type for the TXM
+*/
+typedef enum mac_ack_type_e
+{
+    MAC_IMM_ACK = 0,    /* Imm-Ack (frame version = 0/1) */
+    MAC_ENH_ACK = 1,    /* Enk-Ack (frame version = 2) */
+} mac_ack_type_t;
+
+/**
+  \brief  FIFO ID
+*/
+typedef enum mac_fifo_id_e
+{
+    TXN_FIFO_ID = 0,    /* Normal TX FIFO */
+    TXB_FIFO_ID = 1,    /* Beacon TX FIFO */
+    TXG1_FIFO_ID = 2,   /* GTS1 TX FIFO */
+    TXG2_FIFO_ID = 3,   /* GTS2 TX FIFO */
+    KEY_FIFO_ID = 4,    /* Key FIFO */
+    RX_FIFO_ID = 5,     /* RX FIFO */
+
+    INVALID_FIFO_ID = 6,    /* Invalid FIFO ID */
+} mac_fifo_id_t;
+
+/**
+  \brief  Defines MAC Initialize attribute
+*/
+typedef struct
+{
+    uint32_t int_mask;
+    struct
+    {
+        uint32_t rx_pingpong_en : 1;        /*!< RX ping-pong FIFO enable control:
+                                                 0: disable, 1: enable                */
+        uint32_t rf_early_term : 1;         /*!< RX PHY early term enable control:
+                                                 0: disable, 1: enable                */
+        uint32_t frm06_rx_early : 1;        /*!< RX early interrrupt for frame version
+                                                 06 enable control: 0: disable,
+                                                 1: enable                            */
+        uint32_t rx_timestamp_select : 1;   /*!< RX timestamp timer selection:
+                                                 0: MAC timer, 1: BT Native clock     */
+        uint32_t cca_mode : 3;              /*!< CCA mode selection:
+                                                 00b: disable; 01b: ED mode; 10b:
+                                                 CS mode; 11b: ED + CS combination
+                                                 mode */
+        uint32_t anch_jump_val : 4;         /*!< Anchor point jump for PHY
+                                                 arbitration retry                   */
+        uint32_t default_channel : 5;       /*!< default channel                     */
+
+        uint32_t rxon2ccadt_delay : 4;      /*!< rxon to csma_state==CCADT delay     */
+        uint32_t ccachkp : 4;               /*!< The number of symbol for CCA check point */
+        uint32_t phy_tx_latency : 5;        /*!< MAC TX to PHY TX latency            */
+        uint32_t disdec : 1;                /*!< is disable RX decryption            */
+        uint32_t no_backoff_retx : 1;       /*!< is enable no-backoff for TX re-trigger due to
+                                                 PHY re-grant  */
+        uint32_t reserved1 : 1;
+    } mac_cfg;
+
+    struct
+    {
+        uint32_t tx_rf_mode : 2;            /*!< RF mode for TX     */
+        uint32_t rx_rf_mode : 2;            /*!< RF mode for RX     */
+        uint32_t lna_en : 1;                /*!< is RX LNA enabled  */
+        uint32_t phy_gnt_slot_offset : 5;   /*!< slot number offset from current to Grant PHY */
+        uint32_t reserved : 22;
+    } phy_cfg;
+
+    uint8_t phy_arbitration_en;             /*!< PHY arbitration enable control:
+                                                0: disable; 1: enable                */
+    uint8_t cca_ed_threshold;
+    uint8_t rx2tx_delay;                    /*!< RX to TX delay for wait RF ready    */
+    uint8_t cca_rxon_delay;                 /*!< normal RX to CCA RX delay           */
+    uint8_t rx2tx_immack_delay;
+    uint8_t txagc;
+    uint8_t txon_delay;                     /*!< MAC initial TX to PHY TX ready delay */
+    /* MAC driver configuration */
+    struct
+    {
+        uint8_t sw_backup_mac_reg : 1;     /*!< is backup MAC reg by software     */
+        uint8_t sw_backup_sa_filter : 1;   /*!< is backup MAC source address match
+                                                 filetr by software */
+        uint8_t hci_rst_backup_mac : 1;    /*!< is backup whole MAC register by
+                                                 software for BT HCI reset */
+        uint8_t reserved : 5;
+    } driver_cfg;
+
+    /* gain table per channel, in unit of 0.5dBm */
+    const int8_t *ptx_gain_tbl;
+} mac_attribute_t;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif    // end of #ifndef _MAC_DATA_TYPE_H_
diff --git a/bee/drivers/mac_802154/rom/mac_driver.h b/bee/drivers/mac_802154/rom/mac_driver.h
new file mode 100644
index 00000000..2a637bd4
--- /dev/null
+++ b/bee/drivers/mac_802154/rom/mac_driver.h
@@ -0,0 +1,2782 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**************************************************************************//**
+ * @file     mac_driver.h
+ * @brief    IEEE802.15.4 MAC/PHY driver header file.
+ *
+ * @version  V1.00
+ * @date     2021-09-24
+ *
+ * @note
+ *
+ ******************************************************************************/
+
+#ifndef _MAC_DRIVER_H_
+#define _MAC_DRIVER_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "stdint.h"
+#include "string.h"
+#include "zb_section.h"
+#include "mac_reg_mask.h"
+#include "mac_data_type.h"
+
+/**
+  \brief  Define TX/RX FIFO and Key buffer base address
+*/
+#define MAC_TXN_BASE_ADDR             ((uint32_t)mac_FIFO_BaseAddr(TXN_FIFO_ID))
+#define MAC_TXB_BASE_ADDR             ((uint32_t)mac_FIFO_BaseAddr(TXB_FIFO_ID))
+#define MAC_TXG1_BASE_ADDR            ((uint32_t)mac_FIFO_BaseAddr(TXG1_FIFO_ID))
+#define MAC_TXG2_BASE_ADDR            ((uint32_t)mac_FIFO_BaseAddr(TXG2_FIFO_ID))
+#define MAC_KEY_FIFO_BASE_ADDR        ((uint32_t)mac_FIFO_BaseAddr(KEY_FIFO_ID))
+#define MAC_RX_BASE_ADDR              ((uint32_t)mac_FIFO_BaseAddr(RX_FIFO_ID))
+
+// Base address of extend addr
+uint8_t *MAC_EADR_BASE_ADDR(void);
+
+/**
+  \brief  Defines type for MAC 8-bits register retention list
+*/
+typedef struct retention_8b_reg_s
+{
+    __IOM uint8_t *const reg_addr;
+    uint8_t mask;
+} retention_8b_reg_t, *pretention_8b_reg_t;
+
+/**
+  \brief  Defines MAC callback function
+*/
+typedef void (*mac_intr_callback_t)(uint32_t int_sts);
+typedef int32_t (*mac_edscan_lv2dbm_callback_t)(int32_t level);
+typedef void (*mac_gnt_entry_callback_t)(uint16_t prio, uint16_t prio_min);
+typedef void (*modem_cca_comb_callback_t)(uint8_t comb);
+
+/**
+  \brief  Defines MAC Driver ROM code patch functions entry table
+*/
+typedef struct mac_driver_rom_patch_s
+{
+    // util
+    void *(*memcpy)(void *dest, const void *src, uint32_t len);
+    void (*porting_init)(void);
+
+    //ISR
+    void (*edscan_handler)(void);
+    void (*swtimer_handler)(void);
+
+    // Interrupt
+    void (*enter_critical)(void);
+    void (*exit_critical)(void);
+
+    // Reset
+    void (*reset)(void);
+
+    // BT Clk Timer
+    uint32_t (*btclk2us)(mac_bt_clk_t bt_clk);
+    uint32_t (*curr_btus)(void);
+    void (*set_btus_int)(uint32_t tid, uint32_t time_us);
+
+    // radio
+    void (*reset_rf)(void);
+    void (*set_radio_state)(mac_radio_state_t new_state);
+    mac_radio_state_t (*get_radio_state)(void);
+
+    // cca and edscan
+    void (*enable_txn_csmacca)(void);
+    void (*disable_txn_csmacca)(void);
+
+    // software timer
+    void (*swtimer_init)(mac_timer_handle_t *ptmr_entities, uint8_t tmr_num);
+    void (*swtimer_stop)(pmac_timer_handle_t pstop_tmr);
+    void (*swtimer_free)(pmac_timer_handle_t pmac_tmr);
+
+    // rx
+    uint8_t (*rx)(uint8_t *RxFIFO);
+} mac_driver_rom_patch_t, *pmac_driver_rom_patch_t;
+
+/**
+  \brief MAC driver state flags.
+*/
+typedef union
+{
+    uint8_t w;
+
+    struct
+    {
+        uint8_t rf_rst_pending    : 1;          /*!< is RF reset pending  */
+        uint8_t hci_rst_backup_buf_alloc : 1;   /*!< is MAC reg backup buffer is allocated */
+        uint8_t   : 6;
+    } b;                                        /*!< bit fields for MAC driver state flags */
+} mac_state_flag_t, *pmac_state_flag_t;
+
+typedef union
+{
+    uint32_t w;
+    struct
+    {
+        uint32_t txnif      : 1;
+        uint32_t txg1if     : 1;
+        uint32_t txg2if     : 1;
+        uint32_t txnterrif  : 1;
+        uint32_t rxelyif    : 1;
+        uint32_t secif      : 1;
+        uint32_t rxif       : 1;
+        uint32_t mactmrif   : 1;
+        uint32_t btcmp0if   : 1;
+        uint32_t btcmp1if   : 1;
+        uint32_t gntif      : 1;
+        uint32_t edscanif   : 1;
+        uint32_t sfstartif  : 1;
+        uint32_t sfendif    : 1;
+        uint32_t btcmp2if   : 1;
+        uint32_t btcmp3if   : 1;
+        uint32_t            : 16;
+    } b; /*!< bit fields for isrsts */
+} isrsts_t, *pisrsts_t;
+
+typedef union
+{
+    uint32_t w; /*!< Interrupt Mask Control Register */
+    struct
+    {
+        uint32_t txnmsk     : 1;
+        uint32_t txg1msk    : 1;
+        uint32_t txg2msk    : 1;
+        uint32_t txnterrmsk : 1;
+        uint32_t rxelymsk   : 1;
+        uint32_t secmsk     : 1;
+        uint32_t rxmsk      : 1;
+        uint32_t mactmrmsk  : 1;
+        uint32_t btcmp0msk  : 1;
+        uint32_t btcmp1msk  : 1;
+        uint32_t gntmsk     : 1;
+        uint32_t edscanmsk  : 1;
+        uint32_t sfstartmsk : 1;
+        uint32_t sfendmsk   : 1;
+        uint32_t btcmp2msk  : 1;
+        uint32_t btcmp3msk  : 1;
+        uint32_t            : 16;
+    } b; /*!< bit fields for mac_intmsk */
+} intmsk_t, *pintmsk_t;
+
+typedef union
+{
+    uint8_t w; /*!< Normal TX FIFO Trigger Control Register */
+
+    struct
+    {
+        uint8_t txntrig     : 1;
+        uint8_t txnsecen    : 1;
+        uint8_t txnackreq   : 1;
+        uint8_t ack_type    : 1;
+        uint8_t             : 1;
+        uint8_t txnfrmtry   : 3;
+    } b; /*!< bit fields for mac_txn_trig */
+} txn_trig_t, *ptxn_trig_t;
+
+typedef union
+{
+    uint32_t w; /*!< BT Time Comparator for TX Trigger Time Control Register */
+
+    struct
+    {
+        uint32_t txn_nclk   : 18;
+        uint32_t txn_ckc    : 10;
+        uint32_t schtxnocca : 1;
+        uint32_t            : 2;
+        uint32_t txntmren   : 1;
+    } b; /*!< bit fields for mac_tx_given_time_set */
+} tx_given_time_set_t, *ptx_given_time_set_t;
+
+typedef union
+{
+    uint32_t w;  /*!< MAC/PHY RX backup register 2 */
+
+    struct
+    {
+        uint32_t rx_bkprg2_pg_addr : 8;
+        uint32_t channel           : 7;
+        uint32_t opt_cca_ed_or     : 1;
+        uint32_t bkrpt0_reg_addr   : 8;
+        uint32_t bkrpt0_en         : 1;
+        uint32_t                   : 7;
+    } b; /*!< bit fields for mac_rx_prg_reg_2w */
+} rx_prg_reg_2w_t, *prx_prg_reg_2w_t;
+
+typedef union
+{
+    uint32_t w; /*!< PHY RX backup register 0 */
+
+    struct
+    {
+        uint32_t bkrpt2_reg_addr : 8;
+        uint32_t bkrpt2_en       : 1;
+        uint32_t                 : 7;
+        uint32_t bkrpt1_reg_addr : 8;
+        uint32_t bkrpt1_en       : 1;
+        uint32_t                 : 7;
+    } b; /*!< bit fields for mac_rx_bkrpt0w */
+} rx_bkrpt0w_t, *prx_bkrpt0w_t;
+
+typedef union
+{
+    uint32_t w; /*!< PHY RX backup register 1 */
+
+    struct
+    {
+        uint32_t bkrpt4_reg_addr : 8;
+        uint32_t bkrpt4_en       : 1;
+        uint32_t                 : 7;
+        uint32_t bkrpt3_reg_addr : 8;
+        uint32_t bkrpt3_en       : 1;
+        uint32_t                 : 7;
+    } b; /*!< bit fields for mac_rx_bkrpt1w */
+} rx_bkrpt1w_t, *prx_bkrpt1w_t;
+
+typedef struct mac_driver_s
+{
+    volatile isrsts_t IntIn;
+    volatile isrsts_t IntProc;
+    volatile intmsk_t IntMask;
+
+    mac_radio_state_t mac_radio_state;
+    union
+    {
+        tx_pending_sts_t tx_trig_pend;
+        uint8_t tx_trig_pend_w;
+    };
+    tx_pending_sts_t tx_pend_secen;
+    volatile txn_trig_t txntrig_saved;
+    uint8_t gnt_failed_retry;
+
+    uint8_t tx_at_time_pending;
+
+    uint8_t DualRxFlag;
+
+    uint8_t TransceiverState;   /*!< RF Transceiver state */
+    uint8_t cca_mode;           /*!< selected CCA mode of CSMA-CA */
+    mac_state_flag_t state_flg;
+    uint16_t CurrentFrequency;
+    uint16_t tagt_no_cca_trig_tim;   /*!< the period from MAC TX trigger to
+                                          the PHY start TX for TX at given time without CCA */
+    uint16_t tagt_trig_tim;     /*!< the period from MAC TX trigger to
+                                     the PHY start TX for TX at given time with CCA */
+
+    tx_given_time_set_t tx_given_time_set_saved;
+    pmac_timer_handle_t mac_timer_free_list;
+    union
+    {
+        pmac_timer_handle_t mac_timer_running_list;
+        pmac_timer_handle_t mac_timer_running_head;
+    };
+
+    mac_ed_scan_states_t ed_scan_state;
+    /* for back up the latest value write to these registers,
+       R/W to these registers map to different register internaly */
+    volatile rx_prg_reg_2w_t rx_prg_reg_2w;
+    volatile rx_bkrpt0w_t rx_bkrpt0w;
+    volatile rx_bkrpt1w_t rx_bkrpt1w;
+
+    /* call back functions */
+    mac_intr_callback_t mac_intr_cb;
+    mac_edscan_lv2dbm_callback_t mac_edscan_lv2dbm_cb;
+    mac_gnt_entry_callback_t mac_gnt_entry_cb;
+    modem_cca_comb_callback_t modem_cca_comb_cb;
+
+    /* MAC driver attributes */
+    mac_attribute_t mac_attribute;
+
+    /* Reg list for MAC register retention by SW */
+    const uint32_t **preten_reg32b_list;
+    const uint16_t **preten_reg16b_list;
+    const retention_8b_reg_t *preten_reg8b_list;
+
+    /* ROM code patch function pointers */
+    pmac_driver_rom_patch_t rcp;
+
+    // MAC register backup buffer
+    /* the buffer for backup the MAC registers. when entering DLPS or doing MAC reset the MAC
+       registers may need to be backup and re-store */
+    void *preg_backup_buf;
+
+    uint32_t reserved[3];
+} mac_driver_t, *pmac_driver_t;
+
+/**
+  \brief  Defines MAC stubs function
+*/
+typedef struct
+{
+    // from phy
+    int8_t (*get_rssi_from_raw)(uint16_t rssi_raw, uint8_t channel);
+    // util
+    void *(*memcpy)(void *dest, const void *src, uint32_t len);
+    void (*hal_delay_us)(uint32_t delay_us);
+    uint8_t (*hal_is_timeout)(uint32_t timeout);
+    // isr
+    void (*swtimer_handler)(void);
+    void (*edscan_handler)(void);
+    // interrupt
+    void (*enter_critical)(void);
+    void (*exit_critical)(void);
+    void (*disable_interrupt)(void);
+    void (*resume_interrupt)(void);
+    // reset
+    void (*reset)(void);
+    void (*enable)(void);
+    void (*disable)(void);
+    // bt native clock
+    void (*curr_btclk)(mac_bt_clk_t *pbt_clk);
+    uint32_t (*btclk2us)(mac_bt_clk_t bt_clk);
+    uint32_t (*curr_btus)(void);
+    uint64_t (*curr_mactime)(void);
+    void (*set_btclk_int)(uint32_t tid, mac_bt_clk_t *pbt_clk);
+    void (*set_btus_int)(uint32_t tid, uint32_t time_us);
+    // radio
+    void (*reset_rf)(void);
+    void (*radio_on)(void);
+    void (*radio_off)(void);
+    void (*set_radio_state)(mac_radio_state_t new_state);
+    mac_radio_state_t (*get_radio_state)(void);
+    uint8_t (*set_trx_state)(uint8_t state);
+    uint8_t (*get_trx_state)(void);
+    uint8_t (*set_channel)(uint8_t ch);
+    uint8_t (*get_channel)(void);
+    uint8_t (*set_tx_power)(int8_t tx_dbm);
+    // PIB
+    // rx filter
+    // cca and edscan
+    void (*enable_txn_csmacca)(void);
+    void (*disable_txn_csmacca)(void);
+    void (*set_ccamode)(mac_cca_mode_t cca_mode);
+    uint8_t (*edscan_ext)(uint32_t scan_duration, int8_t *ed_peak_lev, int8_t *ed_avrg_lev);
+    uint8_t (*edscan_schedule)(uint32_t scan_duration, mac_ed_scan_callback_t callback);
+    void (*edscan_cancel)(void);
+    // software timer
+    void (*swtimer_init)(mac_timer_handle_t *ptmr_entities, uint8_t tmr_num);
+    pmac_timer_handle_t (*swtimer_alloc)(void);
+    void (*swtimer_free)(pmac_timer_handle_t pmac_tmr);
+    void (*swtimer_start)(pmac_timer_handle_t pstart_tmr, uint32_t timeout, void *pcallback, void *arg);
+    void (*swtimer_stop)(pmac_timer_handle_t pstop_tmr);
+    // tx
+    uint8_t (*trig_txn)(uint8_t ackreq, uint8_t secreq);
+    void (*update_pretrig_time)(void);
+    uint8_t (*trig_txn_at)(uint8_t aclreq, uint8_t secreq, uint8_t docca, mac_bt_clk_t txtime);
+    uint8_t (*trig_txenhack)(uint8_t early, uint8_t secreq);
+    void (*trig_upperenc)(void);
+    void (*trig_upperdec)(void);
+    // rx
+    uint8_t (*rx)(uint8_t *RxFIFO);
+    uint8_t (*rxfifo)(uint8_t *RxFIFO, uint8_t *MorePkt);
+    // addr match filter
+    void (*set_addr_matchmode)(uint8_t mode);
+    uint8_t (*add_short_match)(uint16_t short_addr, uint16_t panid);
+    uint8_t (*del_short_match)(uint16_t short_addr, uint16_t panid);
+    void (*del_short_match_all)(void);
+    uint8_t (*add_ext_match)(uint8_t *pext_addr);
+    uint8_t (*del_ext_match)(uint8_t *pext_addr);
+    void (*del_ext_match_all)(void);
+    // security
+    uint8_t (*upper_cipher)(uint8_t sec_mode, uint8_t *sec_key, uint8_t *sec_nonce);
+    uint8_t (*upper_decipher)(uint8_t sec_mode, uint8_t *sec_key, uint8_t *sec_nonce);
+    // Callback function hook
+    void (*interrupt_callback_hook)(mac_intr_callback_t intr_cb);
+    void (*lv2dbm_callback_hook)(mac_edscan_lv2dbm_callback_t lv2dbm_cb);
+    void (*phy_gnt_entry_callback_hook)(mac_gnt_entry_callback_t gnt_entry_cb);
+    void (*modem_cca_comb_callback_hook)(modem_cca_comb_callback_t cca_comb_cb);
+
+    // Register SW retention functions
+    uint32_t (*get_retention_reg_size)(void);
+    void *(*backup_reten_reg)(uint8_t *preten_buf);
+    void *(*restore_reten_reg)(uint8_t *preten_buf);
+
+    // PTA control
+    void (*pta_duty_set_ratio)(uint32_t high_ticks, uint32_t low_ticks);
+
+    // Initialization
+    void (*mac_init_attribute)(mac_attribute_t *attribute);
+    void (*mac_init)(mac_driver_t *ptr_drv, mac_attribute_t *attribute);
+
+    // ROM Table
+    const uint8_t *secmode_06to03;
+    const uint8_t *secmode_mic_len;
+
+    //callback for BT
+    void (*bt_hci_reset_start)(void);
+    void (*bt_hci_reset_end)(void);
+
+    // added after RTL87X2G B-Cut
+    void (*grant_phy_req)(uint8_t slot_offset);
+    uint32_t (*fifo_base_addr)(mac_fifo_id_t fifo_id);
+    uint8_t (*LoadTxNPayload)(uint8_t HdrL, uint8_t FrmL, uint8_t *TxFIFO);
+    void (*SetPANId)(uint16_t pid);
+    uint16_t (*GetPANId)(void);
+    void (*SetShortAddress)(uint16_t sadr);
+    void (*SetLongAddress)(uint8_t  *ladr);
+    void (*SetCoordinatorShortAddress)(uint16_t sadr);
+    void (*SetCoordinatorLongAddress)(uint8_t  *ladr);
+    void (*SetGroupAddress)(uint8_t *gpadr);
+    uint8_t (*SetTxNMaxRetry)(uint8_t max_retry);
+    void (*SetTXGain)(uint8_t tx_gain);
+    uint8_t (*GetTXGain)(void);
+    void (*SetMaxCSMABackoffs)(uint8_t MaxCSMABackoffs);
+    uint32_t (*GetTxNStatus)(void);
+    uint32_t (*GetTxTermedStatus)(void);
+    uint8_t (*GetTxNRetryTimes)(void);
+    void (*SetPromiscuous)(uint8_t en);
+    uint8_t (*GetPromiscuous)(void);
+    void (*SetScanMode)(uint8_t en);
+    uint8_t (*GetScanMode)(void);
+    uint8_t (*GetRxFrmSeq)(void);
+    uint8_t (*GetRxFrmAckReq)(void);
+    uint8_t (*GetRxFrmType)(void);
+    uint8_t (*GetRxFrmVersion)(void);
+    uint8_t (*GetRxFrmPanidCompress)(void);
+    uint8_t (*GetRxFrmSecEn)(void);
+    uint8_t (*GetRxFrmSecLevel)(void);
+    uint8_t (*GetRxFrmSecKeyIdMode)(void);
+    uint8_t (*GetRxFrmSecKeyId)(void);
+    uint8_t (*GetRxFrmSrcAddrMode)(void);
+    uint16_t (*GetRxFrmShortAddr)(void);
+    uint64_t (*GetRxFrmLongAddr)(void);
+    int8_t (*GetCcaEDThreshold)(void);
+    void (*SetTxEnhAckPending)(uint8_t len);
+    uint8_t (*GetTxEnhAckPending)(void);
+    void (*RxFlush)(void);
+    uint8_t (*GetSrcMatchStatus)(void);
+    void (*ClrSrcMatchStatus)(void);
+    void (*SetNonce)(uint8_t *nonce);
+    void (*SetKey)(uint8_t *key_buf, uint8_t *key);
+    void (*LoadNonce)(uint8_t *nonce);
+    void (*LoadTxNKey)(uint8_t *key);
+    void (*SetTxNChiper)(uint8_t level);
+    void (*LoadTxEnhAckKey)(uint8_t *key);
+    void (*SetTxEnhAckChiper)(uint8_t level);
+    uint8_t (*GetSecHLEN)(void);
+    void (*SetSecHLEN)(uint8_t val);
+    void (*SetRxChiper)(uint8_t level);
+    void (*TrigRxDecryption)(void);
+    void (*IgnoreRxDec)(void);
+    void (*PTA_Enable)(uint8_t enable);
+    void (*PTA_PrityDutyEnable)(uint8_t enable);
+    void (*PTA_LoRXReq_Enable)(uint8_t enable);
+    void (*PTA_ShareLNA)(uint8_t is_share_lan);
+    void (*PTA_CCAReq_Enable)(uint8_t enable);
+    void (*PTA_TXReq_Pri)(uint8_t hi_priority);
+    void (*PTA_DutySetTick)(uint32_t tick_us);
+    void (*DisBTClkTmr)(uint32_t tid);
+} mac_adapter_t;
+
+/*
+  rom exported symbol
+*/
+extern uint32_t (*mac_GetZBArbitrationWindow)(int16_t *prio, int16_t *prio_min);
+extern const mac_adapter_t mac_adapter;
+
+static __inline uint32_t mac_FIFO_BaseAddr(mac_fifo_id_t fifo_id)
+{
+    return mac_adapter.fifo_base_addr(fifo_id);
+}
+
+/*
+  Init
+*/
+/**
+*
+* @fn void mac_InitAttribute(mac_attribute_t* attr)
+*
+* @brief Initialize mac_attribute_t structure with default value.
+*
+* @param attr the mac_attribute_t pointer to be initialized
+*
+* @return None
+*
+*/
+static __inline void mac_InitAttribute(mac_attribute_t *attribute)
+{
+    mac_adapter.mac_init_attribute(attribute);
+}
+
+/**
+*
+* @fn void mac_RegisterCallback(mac_intr_callback_t intr_cb, mac_edscan_lv2dbm_callback_t lv2dbm_cb,
+*                               mac_gnt_entry_callback_t gnt_entry_cb)
+*
+* @brief Register mac callback function
+*
+* @param intr_cb interrupt handler callback function
+*
+* @param lv2dbm_cb translate EDScan level to dbm callback function
+*
+* @param gnt_entry_cb set gnt entry priority callback function
+*
+* @return None
+*
+*/
+static __inline void mac_RegisterCallback(mac_intr_callback_t intr_cb,
+                                          mac_edscan_lv2dbm_callback_t lv2dbm_cb,
+                                          mac_gnt_entry_callback_t gnt_entry_cb,
+                                          modem_cca_comb_callback_t cca_comb_cb)
+{
+    mac_adapter.interrupt_callback_hook(intr_cb);
+    mac_adapter.lv2dbm_callback_hook(lv2dbm_cb);
+    mac_adapter.phy_gnt_entry_callback_hook(gnt_entry_cb);
+    mac_adapter.modem_cca_comb_callback_hook(cca_comb_cb);
+}
+
+/**
+*
+* @fn void mac_Initialize(mac_driver_t *ptr_drv, mac_attribute_t *attribute)
+*
+* @brief Initialize mac layer with attributes
+*
+* @param ptr_drv the mac_driver_t pointer to be initialized, mac_driver_t should be defined in data section
+*
+* @param attribute the mac_attribute_t pointer point to structure with default value
+*
+* @return None
+*
+*/
+static __inline void mac_Initialize(mac_driver_t *ptr_drv, mac_attribute_t *attribute)
+{
+    mac_adapter.mac_init(ptr_drv, attribute);
+}
+
+/**
+*
+* @fn mac_Initialize_Additional()
+*
+* @brief Additional initialize step
+*
+* @param None
+*
+*/
+void mac_Initialize_Additional(void);
+
+/**
+*
+* @fn void mac_EnterDLPS(void *reg_retention_buf)
+*
+* @brief Let MAC enter the deep sleep power saving mode
+*
+* @param reg_retention_buf the buffer for MAC register backup before it entring sleep mode,
+*                          if this buffer is NULL then no register will be backup. The buffer
+*                          size must be big enough to backup registers in the backup list.
+*
+* @return None
+*
+*/
+void mac_EnterDLPS(void *reg_retention_buf);
+
+/**
+*
+* @fn void mac_ExitDLSP(void *reg_retention_buf)
+*
+* @brief Resume the MAC from deep sleep power saving mode
+*
+* @param reg_retention_buf the buffer for MAC register backup, which is used to restore MAC register.
+*                          if this buffer is NULL then no register will be restored.
+*
+* @return None
+*
+*/
+void mac_ExitDLPS(void *reg_retention_buf);
+
+/*
+  Interrupt
+*/
+/**
+*
+* @fn void mac_EnterCritical (void)
+*
+* @brief Enter MAC layer driver critical section (no MAC interrupt)
+*
+* @param None
+*
+* @return None
+*
+*/
+static __inline void mac_EnterCritical(void)
+{
+    mac_adapter.enter_critical();
+}
+
+/**
+*
+* @fn void mac_EnterCritical (void)
+*
+* @brief Leave MAC layer driver critical section (MAC interrupt resume)
+*
+* @param None
+*
+* @return None
+*
+*/
+static __inline void mac_ExitCritical(void)
+{
+    mac_adapter.exit_critical();
+}
+
+/**
+*
+* @fn void mac_DisableInterrupt(void)
+*
+* @brief disable MAC interrupt (store current interrupt mask
+*        and then mask all interrupt)
+*
+* @param Mode
+*
+* @return None
+*
+*/
+static __inline void mac_DisableInterrupt(void)
+{
+    mac_adapter.disable_interrupt();
+}
+
+/**
+*
+* @fn void mac_ResumeInterrupt(void)
+*
+* @brief resume MAC interrupt (restore interrupt mask)
+*
+* @param Mode
+*
+* @return None
+*
+*/
+static __inline void mac_ResumeInterrupt(void)
+{
+    mac_adapter.resume_interrupt();
+}
+
+/*
+  Reset
+*/
+/**
+*
+* @fn mac_Reset()
+*
+* @brief Software reset MAC
+*
+* @param None
+*
+*/
+static __inline void mac_Reset(void)
+{
+    mac_adapter.reset();
+}
+
+/**
+*
+* @fn mac_Enable()
+*
+* @brief Enable MAC clock
+*
+* @param None
+*
+*/
+static __inline void mac_Enable(void)
+{
+    mac_adapter.enable();
+}
+
+/**
+*
+* @fn mac_Disable()
+*
+* @brief Disable MAC clock
+*
+* @param None
+*
+*/
+static __inline void mac_Disable(void)
+{
+    mac_adapter.disable();
+}
+
+/*
+  BT native clock
+*/
+/**
+*
+* @fn void mac_GetCurrentBTClk(mac_bt_clk_t *pbt_clk)
+*
+* @brief Get current BT native clock and clock counter vaule
+*
+*
+* @param pbt_clk the pointer of return BT clock data structure
+*
+* @return None
+*
+*/
+static __inline void mac_GetCurrentBTClk(mac_bt_clk_t *pbt_clk)
+{
+    mac_adapter.curr_btclk(pbt_clk);
+}
+
+/**
+*
+* @fn uint32_t mac_BTClkToUs(mac_bt_clk_t bt_clk)
+*
+* @brief Convert a BT clock value to a time value with unit of 1us.
+*
+* @param bt_clk the BT clock value to be converted
+*
+* @return the converted time value with unit of 1us
+*
+*/
+static __inline uint32_t mac_BTClkToUS(mac_bt_clk_t bt_clk)
+{
+    return mac_adapter.btclk2us(bt_clk);
+}
+
+/**
+*
+* @fn uint32_t mac_GetCurrentBTUS(void)
+*
+* @brief Get current BT native clock and clock counter vaule and convert
+*        it as micro-second
+*
+* @return current BT clock counter in micro-second format
+*
+*/
+static __inline uint32_t mac_GetCurrentBTUS(void)
+{
+    return mac_adapter.curr_btus();
+}
+
+/**
+*
+* @fn void mac_USToBTClk(uint32_t time_us, mac_bt_clk_t *pbt_clk)
+*
+* @brief Convert a time value of 1us to a BT clock value
+*
+* @param time_us the time value with 1us unit to be converted
+*
+* @param pbt_clk the pointer of the converted BT clock
+*
+* @return None
+*
+*/
+static __inline void mac_USToBTClk(uint32_t time_us, mac_bt_clk_t *pbt_clk)
+{
+    uint32_t native_clk;
+    uint32_t clk_cntr;
+
+    if (time_us >= MAX_BT_CLOCK_COUNTER)
+    {
+        time_us -= MAX_BT_CLOCK_COUNTER;
+    }
+
+    native_clk = time_us / 625;
+    clk_cntr = time_us - (native_clk * 625);
+    pbt_clk->bt_native_clk = native_clk & 0x3FFFFF;
+    if (clk_cntr > 0)
+    {
+        pbt_clk->bt_clk_counter = 625 - clk_cntr;
+    }
+    else
+    {
+        pbt_clk->bt_clk_counter = 0;
+    }
+}
+
+/**
+*
+* @fn uint64_t mac_GetCurrentMACTime(void)
+*
+* @brief Get current MAC time in us, based on BT clock counter
+*
+* @return current MAC time
+*
+*/
+static __inline uint64_t mac_GetCurrentMACTime(void)
+{
+    return mac_adapter.curr_mactime();
+}
+
+/**
+*
+* @fn void mac_SetBTClkInt(uint32_t tid, mac_bt_long_clk_t *pbt_clk)
+*
+* @brief Setup a BT clock interrupt
+*
+* @param tid the ID of BT clock timer to be set
+*
+* @param pbt_clk the given BT clock value to trigger the interrupt
+*
+* @return None
+*
+*/
+static __inline void mac_SetBTClkInt(uint32_t tid, mac_bt_clk_t *pbt_clk)
+{
+    mac_adapter.set_btclk_int(tid, pbt_clk);
+}
+
+/**
+*
+* @fn void mac_SetBTClkUSInt(uint32_t tid, uint32_t time_us)
+*
+* @brief Setup a BT clock interrupt by a time format in micro-second
+*
+* @param tid the ID of BT clock timer to be set
+*
+* @param time_us the given BT clock value in us format to trigger the interrupt
+*
+* @return None
+*
+*/
+static __inline void mac_SetBTClkUSInt(uint32_t tid, uint32_t time_us)
+{
+    mac_adapter.set_btus_int(tid, time_us);
+}
+
+/**
+*
+* @fn uint64_t mac_ConvertT0AndDtTo64BitTime(uint32_t aT0, uint32_t aDt, const uint64_t *aNow)
+*
+* @brief Convert 32bit T0 and Dt to 64bit time
+*
+* @return 64bit time
+*
+*/
+static __inline uint64_t mac_ConvertT0AndDtTo64BitTime(uint32_t aT0, uint32_t aDt,
+                                                       const uint64_t *aNow)
+{
+    uint64_t now;
+    now = *aNow;
+
+    if (((uint32_t)now < aT0) && ((aT0 - (uint32_t)now) > (UINT32_MAX / 2)))
+    {
+        now -= EPOCH_32BIT_US;
+    }
+    else if (((uint32_t)now > aT0) && (((uint32_t)now) - aT0 > (UINT32_MAX / 2)))
+    {
+        now += EPOCH_32BIT_US;
+    }
+
+    return (EPOCH_FROM_TIME(now)) + aT0 + aDt;
+}
+
+/*
+  Util
+*/
+/**
+*
+* @fn void hal_delay_us(uint32_t delay_us)
+*
+* @brief Busy wait delay by pooling BT clock timer
+*
+* @param delay_us the delay time period, in micro-sec
+*
+* @return None
+*
+*/
+static __inline void hal_delay_us(uint32_t delay_us)
+{
+    mac_adapter.hal_delay_us(delay_us);
+}
+
+/**
+*
+* @fn uint8_t HAL_Is_Timeout(uint32_t timeout)
+*
+* @brief check whether current MAC time (BT clock based) is later than the specified timeout time
+*
+* @param timeout the timeout for checking, in micro-secand
+*
+* @return None
+*
+*/
+static __inline uint8_t hal_is_timeout(uint32_t timeout)
+{
+    return mac_adapter.hal_is_timeout(timeout);
+}
+
+/**
+*
+* @fn void *mac_memcpy(void *dest, const void *src, uint32_t len)
+*
+* @brief internal memcpy
+*
+* @param None
+*
+* @return None
+*
+*/
+static __inline void *mac_memcpy(void *dest, const void *src, uint32_t len)
+{
+    return mac_memcpy_rom(dest, src, len);
+}
+
+/*
+  Radio
+*/
+/**
+*
+* @fn mac_RstRF(Level)
+*
+* @brief Software reset RF part only then turns RF to RX mode
+*
+* @param None
+*
+* @return None
+*
+*/
+static __inline void mac_RstRF(void)
+{
+    mac_adapter.reset_rf();
+}
+
+/**
+*
+* @fn void mac_RadioOn(void)
+*
+* @brief To request for PHY grant for MAC TX/RX
+*
+* @return None
+*
+*/
+static __inline void mac_RadioOn(void)
+{
+    mac_adapter.radio_on();
+}
+
+/**
+*
+* @fn void mac_RadioOff(void)
+*
+* @brief To release PHY grant, no TX/RX is allowed after release PHY grant
+*
+* @return None
+*
+*/
+static __inline void mac_RadioOff(void)
+{
+    mac_adapter.radio_off();
+}
+
+/**
+*
+* @fn void mac_SetRadioState(mac_radio_state_t new_state)
+*
+* @brief To set the Radio(PHY arbitration) state
+*
+* @param new_state the new radio state to be set
+*
+* @return None
+*
+*/
+static __inline void mac_SetRadioState(mac_radio_state_t new_state)
+{
+    mac_adapter.set_radio_state(new_state);
+}
+
+/**
+*
+* @fn mac_radio_state_t mac_GetRadioState(void)
+*
+* @brief To get current Radio(PHY arbitration) state
+*
+* @return Current radio state
+*
+*/
+static __inline mac_radio_state_t mac_GetRadioState(void)
+{
+    return mac_adapter.get_radio_state();
+}
+
+/**
+*
+* @fn uint8_t  mac_SetMACTRXState(uint8_t  state)
+*
+* @brief User can use this function to control the RF state of the RF (analog) part only.
+*        The state includes TX, RX, TRX auto switch and TRX off.
+*
+* @param state The RF state.
+*        TRANSCEIVER_TRX_AUTO   TRX auto switch
+*        TRANSCEIVER_RX_ON      RX only
+*        TRANSCEIVER_TX_ON      TX only
+*        TRANSCEIVER_TRX_OFF    TRX off
+*
+* @return The function result.
+* @retval MAC_STS_SUCCESS change RF state successfully.
+* @retval MAC_STS_INVALID_PARAMETER RF state is unkonwn.
+*
+*/
+static __inline uint8_t mac_SetMACTRXState(uint8_t state)
+{
+    return mac_adapter.set_trx_state(state);
+}
+
+/**
+*
+* @fn uint8_t  mac_GetMACTRXState(void)
+*
+* @brief User can use this function to get current the RF state.
+*        The state includes TX, RX, TRX auto switch and TRX off.
+*
+* @param None
+*
+* @return The current RF state.
+* @retval TRANSCEIVER_TRX_AUTO TRX auto switch
+* @retval TRANSCEIVER_RX_ON RX only
+* @retval TRANSCEIVER_TX_ON TX only
+* @retval TRANSCEIVER_TRX_OFF TRX off
+*
+*/
+static __inline uint8_t mac_GetMACTRXState(void)
+{
+    return mac_adapter.get_trx_state();
+}
+
+/**
+*
+* @fn uint8_t  mac_SetChannel(uint8_t  channel)
+*
+* @brief This function is used to change RF channel between 11 ~ 26.
+*
+* @param channel Channel number. Value range is 11~26.
+*
+* @return The result of changing channel.
+* @retval MAC_STS_SUCCESS Set channel successfully.
+* @retval MAC_STS_INVALID_PARAMETER The channel number is out of range.
+*
+*/
+static __inline uint8_t mac_SetChannel(uint8_t ch)
+{
+    return mac_adapter.set_channel(ch);
+}
+
+/**
+*
+* @fn uint8_t mac_SetTXPower(int8_t tx_dbm)
+*
+* @brief This function is used to set the RF TX power.
+*
+* @param tx_dbm the TX power in 0.5dBm unit
+*
+* @return The TX gain index for this TX power setting.
+*
+*/
+static __inline uint8_t mac_SetTXPower(int8_t tx_dbm)
+{
+#ifdef ROM_PATCH_SETTXPOWER
+    extern uint8_t mac_SetTXPower_patch(int8_t tx_dbm);
+    return mac_SetTXPower_patch(tx_dbm);
+#else
+    return mac_adapter.set_tx_power(tx_dbm);
+#endif
+}
+
+/**
+*
+* @fn uint8_t  mac_GetChannel(void)
+*
+* @brief Read current RF channel
+*
+* @param None
+*
+* @return RF channel, range 11-26
+*
+*/
+static __inline uint8_t mac_GetChannel(void)
+{
+    return mac_adapter.get_channel();
+}
+
+/**
+*
+* @fn int8_t mac_GetRSSIFromRaw(uint16_t rssi_raw, uint8_t channel)
+*
+* @brief Get RSSI value from current raw data
+*
+* @param rssi_raw RSSI raw data from phy layer
+*
+* @param channel Channel number. Value range is 11~26.
+*
+* @return RSSI value (dbm)
+*
+*/
+static __inline int8_t mac_GetRSSIFromRaw(uint16_t rssi_raw, uint8_t channel)
+{
+    return mac_adapter.get_rssi_from_raw(rssi_raw, channel);
+}
+
+/*
+  PIB
+*/
+/**
+*
+* @fn void mac_SetPANId(uint16_t  pid)
+*
+* @brief Set IEEE 802.15.4 destination PAN id
+*
+* @param pid 16 bits length PAN identifier
+*
+* @return None
+*
+*/
+static __inline void mac_SetPANId(uint16_t pid)
+{
+    mac_adapter.SetPANId(pid);
+}
+
+/**
+*
+* @fn void mac_GetPANId(uint16_t  pid)
+*
+* @brief Get IEEE 802.15.4 destination PAN id
+*
+* @return 16 bits length PAN identifier
+*
+*/
+static __inline uint16_t mac_GetPANId(void)
+{
+    return mac_adapter.GetPANId();
+}
+
+/**
+*
+* @fn void mac_SetShortAddress(uint16_t  sadr)
+*
+* @brief Set IEEE 802.15.4 destination network(short) address
+*
+* @param sadr 16 bits length network(short) address
+*
+* @return None
+*
+*/
+static __inline void mac_SetShortAddress(uint16_t sadr)
+{
+    mac_adapter.SetShortAddress(sadr);
+}
+
+/**
+*
+* @fn void mac_SetLongAddress(uint8_t  *ladr)
+*
+* @brief Set IEEE 802.15.4 destination extend(long) address
+*
+* @param *ladr 64 bits extend(long) address pointer
+*
+* @return None
+*
+
+*/
+static __inline void mac_SetLongAddress(uint8_t  *ladr)
+{
+    mac_adapter.SetLongAddress(ladr);
+}
+
+/**
+*
+* @fn void mac_SetCoordinatorShortAddress(uint16_t  sadr)
+*
+* @brief Set associated coordinator short address for slotted network synchronization.
+*
+* @param sadr Associated coordinator short address.
+*
+* @return None
+*
+*/
+static __inline void mac_SetCoordinatorShortAddress(uint16_t sadr)
+{
+    mac_adapter.SetCoordinatorShortAddress(sadr);
+}
+
+/**
+*
+* @fn void mac_SetCoordinatorLongAddress(uint8_t  *ladr)
+*
+* @brief Set associated coordinator long address for slotted network synchronization.
+*
+* @param *ladr 64 bits extend(long) address pointer
+*
+* @return None
+*
+*/
+static __inline void mac_SetCoordinatorLongAddress(uint8_t  *ladr)
+{
+    mac_adapter.SetCoordinatorLongAddress(ladr);
+}
+
+/**
+*
+* @fn void mac_SetGroupAddress(uint8_t  *gpadr)
+*
+* @brief Set EUI-64 group address of this device is belong to.
+*
+* @param *gpadr 64 bits EUI-64 group address pointer
+*
+* @return None
+*
+*/
+static __inline void mac_SetGroupAddress(uint8_t *gpadr)
+{
+    mac_adapter.SetGroupAddress(gpadr);
+}
+
+/**
+*
+* @fn uint8_t mac_SetTXNMaxRetry(uint8_t max_retry)
+*
+* @brief Set the maximum retry count of the Normal FIFO transmission.
+*
+* @param max_retry the maximum retry count
+*
+* @return Status
+* @retval MAC_STS_SUCCESS Maximum retry set OK
+*
+*/
+static __inline uint8_t mac_SetTxNMaxRetry(uint8_t max_retry)
+{
+    return mac_adapter.SetTxNMaxRetry(max_retry);
+}
+
+/**
+*
+* @fn void  mac_SetTXGain(uint8_t tx_gain)
+*
+* @brief Set RF TX power index
+*
+* @param tx_gain the TX gain to set
+*
+* @return None
+*
+*/
+static __inline void mac_SetTXGain(uint8_t tx_gain)
+{
+    mac_adapter.SetTXGain(tx_gain);
+}
+
+/**
+*
+* @fn uint8_t  mac_GetTXGain(void)
+*
+* @brief Get current TX gain index setting value
+*
+* @return current TX gain control register value
+*
+*/
+static __inline uint8_t mac_GetTXGain(void)
+{
+    return mac_adapter.GetTXGain();
+}
+
+/**
+*
+* @fn void mac_SetMaxCSMABackoffs(uint8_t MaxCSMABackoffs)
+*
+* @brief This function sets the maximum value of BACKOFF parameter of the TX CSMACA algorithm.
+*        The paramater effects only TX normal FIFO.
+*
+* @param MaxCSMABackoffs the max BACKOFF numbers. The value range is 0 ~ 7.
+*
+* @return None
+*
+*/
+static __inline void mac_SetMaxCSMABackoffs(uint8_t MaxCSMABackoffs)
+{
+    mac_adapter.SetMaxCSMABackoffs(MaxCSMABackoffs);
+}
+
+/**
+*
+* @fn uint32_t mac_GetTxNStatus(void)
+*
+* @brief Get latese TX error status
+*
+* @return the latest TX error status:
+*         bit0: Normal FIFO TX status
+*         bit1: GTS1 FIFO TX status
+*         bit2: GTS2 FIFO TX status
+*         bit3: GTS1 TX slot time not enough
+*         bit4: GTS2 TX slot time not enough
+*         bit5: CCA status
+*
+*/
+static __inline uint32_t mac_GetTxNStatus(void)
+{
+    return mac_adapter.GetTxNStatus();
+}
+
+/**
+*
+* @fn uint32_t mac_GetTxTermedStatus(void)
+*
+* @brief Get latese TX termed status
+*
+* @return the latest TX error status:
+*         bit0: GTS2 FIFO TX termed
+*         bit1: GTS1 FIFO TX termed
+*         bit2: Normal FIFO TX termed
+*         bit3: Beacon FIFO Tx termed
+*
+*/
+static __inline uint32_t mac_GetTxTermedStatus(void)
+{
+    return mac_adapter.GetTxTermedStatus();
+}
+
+/**
+*
+* @fn uint8_t  mac_GetTxNRetryTimes(void)
+*
+* @brief Get last TxN retry times
+*
+* @param None
+*
+* @return Last TxN retry times 0-3
+*
+*/
+static __inline uint8_t mac_GetTxNRetryTimes(void)
+{
+    return mac_adapter.GetTxNRetryTimes();
+}
+
+/*
+  RX filter
+*/
+/**
+*
+* @fn void mac_SetPromiscuous(uint8_t en)
+*
+* @brief Set promiscuous mode stauts
+*
+* @param en Disable 0/Enable 1
+*
+* @return None
+*
+*/
+static __inline void mac_SetPromiscuous(uint8_t en)
+{
+    mac_adapter.SetPromiscuous(en);
+}
+
+/**
+*
+* @fn uint8_t  mac_GetPromiscuous(void)
+*
+* @brief Get promiscuous mode status
+*
+* @param None
+*
+* @return Disable 0/Enable 1
+*
+*/
+static __inline uint8_t mac_GetPromiscuous(void)
+{
+    return mac_adapter.GetPromiscuous();
+}
+
+/**
+*
+* @fn void mac_SetScanMode(uint8_t en)
+*
+* @brief Set scan mode stauts
+*
+* @param en Disable 0/Enable 1
+*
+* @return None
+*
+*/
+static __inline void mac_SetScanMode(uint8_t en)
+{
+    mac_adapter.SetScanMode(en);
+}
+
+/**
+*
+* @fn uint8_t  mac_GetScanMode(void)
+*
+* @brief Get scan mode status
+*
+* @param None
+*
+* @return Disable 0/Enable 1
+*
+*/
+static __inline uint8_t mac_GetScanMode(void)
+{
+    return mac_adapter.GetScanMode();
+}
+
+/**
+*
+* @fn uint8_t  mac_GetRxFrmSeq(void)
+*
+* @brief Get Rx frame sequence number
+*
+* @param None
+*
+* @return rx frame sequence number
+*
+*/
+static __inline uint8_t mac_GetRxFrmSeq(void)
+{
+    return mac_adapter.GetRxFrmSeq();
+}
+
+/**
+*
+* @fn uint8_t  mac_GetRxFrmAckReq(void)
+*
+* @brief Check Rx frame with ack request
+*
+* @param None
+*
+* @return Disable 0/Enable 1
+*
+*/
+static __inline uint8_t mac_GetRxFrmAckReq(void)
+{
+    return mac_adapter.GetRxFrmAckReq();
+}
+
+/**
+*
+* @fn uint8_t  mac_GetRxFrmType(void)
+*
+* @brief Get Rx frame type
+*
+* @param None
+*
+* @retval 0x0 Beacon
+*         0x1 Data
+*         0x2 Ack
+*         0x3 MAC command
+*         0x4 Reserved
+*         0x5 Multiple
+*         0x6 Fragment
+*         0x7 Extended
+*
+*/
+static __inline uint8_t mac_GetRxFrmType(void)
+{
+    return mac_adapter.GetRxFrmType();
+}
+
+/**
+*
+* @fn uint8_t  mac_GetRxFrmVersion(void)
+*
+* @brief Get Rx frame version
+*
+* @param None
+*
+* @retval 0x0 IEEE 802.15.4 2003
+*         0x1 IEEE 802.15.4 2006
+*         0x2 IEEE 802.15.4 2015
+*         0x3 Resrved
+*
+*/
+static __inline uint8_t mac_GetRxFrmVersion(void)
+{
+    return mac_adapter.GetRxFrmVersion();
+}
+
+/**
+*
+* @fn uint8_t  mac_GetRxFrmPanidCompress(void)
+*
+* @brief Check Rx frame with panid compress
+*
+* @param None
+*
+* @return Disable 0/Enable 1
+*
+*/
+static __inline uint8_t mac_GetRxFrmPanidCompress(void)
+{
+    return mac_adapter.GetRxFrmPanidCompress();
+}
+
+/**
+*
+* @fn uint8_t  mac_GetRxFrmSecEn(void)
+*
+* @brief Check Rx frame with security
+*
+* @param None
+*
+* @return Disable 0/Enable 1
+*
+*/
+static __inline uint8_t mac_GetRxFrmSecEn(void)
+{
+    return mac_adapter.GetRxFrmSecEn();
+}
+
+/**
+*
+* @fn uint8_t  mac_GetRxFrmSecLevel(void)
+*
+* @brief Get Rx frame security level
+*
+* @param None
+*
+* @retval 0x0 None
+*         0x1 MIC-32
+*         0x2 MIC-64
+*         0x3 MIC-128
+*         0x4 ENC
+*         0x5 ENC-MIC-32
+*         0x6 ENC-MIC-64
+*         0x7 ENC-MIC-128
+*
+*/
+static __inline uint8_t mac_GetRxFrmSecLevel(void)
+{
+    return mac_adapter.GetRxFrmSecLevel();
+}
+
+/**
+*
+* @fn uint8_t  mac_GetRxFrmSecKeyIdMode(void)
+*
+* @brief Get Rx frame security key id mode
+*
+* @param None
+*
+* @retval 0x0~0x03
+*
+*/
+static __inline uint8_t mac_GetRxFrmSecKeyIdMode(void)
+{
+    return mac_adapter.GetRxFrmSecKeyIdMode();
+}
+
+/**
+*
+* @fn uint8_t  mac_GetRxFrmSecKeyId(void)
+*
+* @brief Get Rx frame security key id
+*
+* @param None
+*
+* @return security key id
+*
+*/
+static __inline uint8_t mac_GetRxFrmSecKeyId(void)
+{
+    return mac_adapter.GetRxFrmSecKeyId();
+}
+
+/**
+*
+* @fn uint8_t  mac_GetRxFrmSrcAddrMode(void)
+*
+* @brief Get Rx frame source address mode
+*
+* @param None
+*
+* @retval 0x0 Not present
+*         0x1 Reserved
+*         0x2 short
+*         0x3 extended
+*
+*/
+static __inline uint8_t mac_GetRxFrmSrcAddrMode(void)
+{
+    return mac_adapter.GetRxFrmSrcAddrMode();
+}
+
+/**
+*
+* @fn uint16_t  mac_GetRxFrmShortAddr(void)
+*
+* @brief Get Rx frame short address
+*
+* @param None
+*
+* @return short address
+*
+*/
+static __inline uint16_t mac_GetRxFrmShortAddr(void)
+{
+    return mac_adapter.GetRxFrmShortAddr();
+}
+
+/**
+*
+* @fn uint8_t  mac_GetRxFrmLongAddr(void)
+*
+* @brief Get Rx frame extended address
+*
+* @param None
+*
+* @return extended address
+*
+*/
+static __inline uint64_t mac_GetRxFrmLongAddr(void)
+{
+    return mac_adapter.GetRxFrmLongAddr();
+}
+
+/*
+  CCA and EDScan
+*/
+/**
+*
+* @fn void mac_EnTxNCsmacaCca(void)
+*
+* @brief Enable CSMA/CA function for TxN FIFO.
+*
+* @param None
+*
+* @return None
+*
+*/
+static __inline void mac_EnTxNCsmacaCca(void)
+{
+    mac_adapter.enable_txn_csmacca();
+}
+
+/**
+*
+* @fn void mac_DisTxNCsmacaCca(void)
+*
+* @brief Disable CSMA/CA function for TxN FIFO.
+*
+* @param None
+*
+* @return None
+*
+*/
+static __inline void mac_DisTxNCsmacaCca(void)
+{
+    mac_adapter.disable_txn_csmacca();
+}
+
+/**
+*
+* @fn void mac_SetCcaMode(mac_cca_mode_t cca_mode)
+*
+* @brief Select the CCA mode of CSMA-CA for frame TX.
+*
+* @param cca_mode the selected CCA mode
+*               MAC_CCA_NONE(0)   disable CCA
+*               MAC_CCA_ED(1)     Energy Detection mode
+*               MAC_CCA_CS(2)     Carrier Sense mode
+*               MAC_CCA_CS_ED(3)  CS or ED combination mode
+*               MAC_CCA_CS_ED_AND(4)  CS and ED combination mode
+*
+* @return None
+*
+*/
+static __inline void mac_SetCcaMode(mac_cca_mode_t cca_mode)
+{
+    mac_adapter.set_ccamode(cca_mode);
+}
+
+/**
+*
+* @fn int8_t mac_GetCcaEDThreshold(void)
+*
+* @brief Get CCA ED mode threshold.
+*
+* @return CCA ED mode threshold
+*
+*/
+static inline int8_t mac_GetCcaEDThreshold(void)
+{
+    return mac_adapter.GetCcaEDThreshold();
+}
+
+/**
+*
+* @fn uint8_t mac_EDScanExt(uint32_t scan_duration, int8_t *ed_peak_lev, int8_t *ed_avrg_lev)
+*
+* @brief To do a energy detection scan for a given duration on current channel and
+*        report the maximum energy level detected during this scan.
+*
+* @param scan_duration the duration of this ED scan, in unit of us.
+*
+* @param ed_peak_lev to return the peak energy level of this ED scan.
+*
+* @param ed_avrg_lev to return the average energy level of this ED scan.
+*
+* @return The function result.
+* @retval MAC_STS_SUCCESS ED scan successfully.
+* @retval MAC_STS_INVALID_PARAMETER ED level return buffer is NULL.
+* @retval MAC_STS_CANCELED ED scan is canceled by FW or FW trigger TXN
+* @retval MAC_STS_PHY_GRANT_FAILED ED scan is failed due to PHY grant failed
+* @retval MAC_STS_TIMEOUT ED scan is failed due to wait PHY report timeout
+*
+*/
+static __inline uint8_t mac_EDScanExt(uint32_t scan_duration, int8_t *ed_peak_lev,
+                                      int8_t *ed_avrg_lev)
+{
+    return mac_adapter.edscan_ext(scan_duration, ed_peak_lev, ed_avrg_lev);
+}
+
+/**
+*
+* @fn uint8_t mac_EDScanSchedule(uint32_t scan_duration, mac_ed_scan_callback_t callback)
+*
+* @brief To start a scheduled ED scan (non-blocking ED scan) procedure.
+*
+* @param scan_duration the duration of this ED scan, in unit of us.
+*
+* @param callback the callback function for ED scan done event.
+*
+* @return The function result.
+* @retval MAC_STS_SUCCESS Scheduled ED scan start successfully.
+* @retval MAC_STS_INVALID_PARAMETER call this function with invalid arguments.
+* @retval MAC_STS_TEMPORARY_UNAVAILABLE previous scheduled ED scan process is not finished yet.
+*
+*/
+static __inline uint8_t mac_EDScanSchedule(uint32_t scan_duration, mac_ed_scan_callback_t callback)
+{
+    return mac_adapter.edscan_schedule(scan_duration, callback);
+}
+
+/**
+*
+* @fn void mac_EDScanScheduleCancel(void)
+*
+* @brief To cancel a started scheduled ED scan process.
+*
+* @return None
+*
+*/
+static __inline void mac_EDScanScheduleCancel(void)
+{
+    mac_adapter.edscan_cancel();
+}
+
+/*
+  Software Timer
+*/
+/**
+*
+* @fn void mac_SoftwareTimer_Init(mac_timer_handle_t *ptmr_entities, uint8_t tmr_num)
+*
+* @brief Initial MAC driver software timer handler.
+*
+* @param ptmr_entities the software timer handler entities list
+*
+* @param tmr_num number of software timer handler in the entities list
+*
+* @return None
+*
+*/
+static __inline void mac_SoftwareTimer_Init(mac_timer_handle_t *ptmr_entities, uint8_t tmr_num)
+{
+    mac_adapter.swtimer_init(ptmr_entities, tmr_num);
+}
+
+/**
+*
+* @fn uint8_t mac_SoftwareTimer_Alloc(void *pcallback, void *parg)
+*
+* @brief Allocate a MAC software handler from free timer handler pool.
+*
+* @return the allocated timer handler
+*
+*/
+static __inline pmac_timer_handle_t mac_SoftwareTimer_Alloc(void)
+{
+    return mac_adapter.swtimer_alloc();
+}
+
+/**
+*
+* @fn void mac_SoftwareTimer_Free(pmac_timer_handle_t pmac_tmr)
+*
+* @brief Free a MAC timer handler
+*
+* @param pmac_tmr the MAC timer handler to be free
+*
+* @return None
+*
+*/
+static __inline void mac_SoftwareTimer_Free(pmac_timer_handle_t pmac_tmr)
+{
+    mac_adapter.swtimer_free(pmac_tmr);
+}
+
+/**
+*
+* @fn void mac_SoftwareTimer_Start(pmac_timer_handle_t pmac_tmr, mac_bt_clk_t bt_clk)
+*
+* @brief Start a MAC timer with a given time stamp (BT clock) of timeout event be triggered.
+*
+* @param pmac_tmr the MAC timer handler to be started
+*
+* @param timeout the time stamp (base on BT clock) to trigger timeout
+*
+* @param pcallback the callback function for timeout event which will be called in timer
+*                  interrupt handler
+*
+* @param arg the argument of the timeout callback function
+*
+* @return None
+*
+*/
+static __inline void mac_SoftwareTimer_Start(pmac_timer_handle_t pstart_tmr, uint32_t timeout,
+                                             void *pcallback, void *arg)
+{
+    mac_adapter.swtimer_start(pstart_tmr, timeout, pcallback, arg);
+}
+
+/**
+*
+* @fn void mac_SoftwareTimer_Stop(pmac_timer_handle_t pstop_tmr)
+*
+* @brief To stop a running MAC timer.
+*
+* @param pstop_tmr the MAC timer to be stopped
+*
+* @return None
+*
+*/
+static __inline void mac_SoftwareTimer_Stop(pmac_timer_handle_t pstop_tmr)
+{
+    mac_adapter.swtimer_stop(pstop_tmr);
+}
+
+/*
+  TX
+*/
+/**
+*
+* @fn uint8_t  mac_LoadTxNPayload(uint8_t HdrL, uint8_t FrmL, uint8_t *TxFIFO)
+*
+* @brief Load frame into Tx normal fifo
+*
+* @param *TxFIFO The tx fifo structure which user wants to transmit.
+*
+*        +---------+---------+-----------+
+*        | 1 byte  | 1 byte  | 125 bytes |
+*        +---------+---------+-----------+
+*        | HDR LEN | FRM LEN | USER DATA |
+*        +---------+---------+-----------+
+*
+* @return The process status.
+* @retval MAC_STS_SUCCESS The TX transmission is successful
+* @retval MAC_STS_DATA_LEN_ERROR the frame length is larger than 125 bytes
+*
+*/
+static __inline uint8_t  mac_LoadTxNPayload(uint8_t HdrL, uint8_t FrmL, uint8_t *TxFIFO)
+{
+    return mac_adapter.LoadTxNPayload(HdrL, FrmL, TxFIFO);
+}
+
+/**
+*
+* @fn uint8_t  mac_TrigTxN(bool_t AckReq, bool_t SecReq)
+*
+* @brief Set if require ack, security process, then trigger Tx normal FIFO.
+*
+* @param AckReq Require Tx waitting an ack frame.
+* @param SecReq Trigger Tx outgoing security process.
+*
+* @return Status
+* @retval MAC_STS_SUCCESS TxN is triggered.
+*
+*/
+static __inline uint8_t mac_TrigTxN(uint8_t ackreq, uint8_t secreq)
+{
+    return mac_adapter.trig_txn(ackreq, secreq);
+}
+
+/**
+*
+* @fn void mac_UpdatePreTrigTime(void)
+*
+* @brief To update the pre-trigger time for TX at given time. Once
+*        any PHY delay time setting is modified, this function should
+*        be called to recalculate the pre-trigger time.
+*
+* @param AckReq Require Tx waitting an ack frame.
+* @param SecReq Trigger Tx outgoing security process.
+*
+* @return Status
+* @retval MAC_STS_SUCCESS TxN is triggered.
+*
+*/
+static __inline void mac_UpdatePreTrigTime(void)
+{
+    mac_adapter.update_pretrig_time();
+}
+
+/**
+* @fn uint8_t  mac_TrigTxNAtTime(bool_t AckReq, mac_bt_clk_t tx_time)
+*
+* @brief Set if require ack, then enable normal FIFO TX with a specified
+*        trigger time.
+*
+* @param AckReq Require Tx waitting an ack frame.
+* @param DoCCA Require to do CCA before TX.
+* @param TxTime The time to trigger Tx.
+*
+* @return Status
+* @retval MAC_STS_SUCCESS TxN is triggered.
+* @retval MAC_STS_TRANSMISSION_TIME_NOT_ENOUGH the specified TXN trigger time is past.
+*
+*/
+static __inline uint8_t mac_TrigTxNAtTime(uint8_t ackreq, uint8_t secreq, uint8_t docca,
+                                          mac_bt_clk_t txtime)
+{
+    return mac_adapter.trig_txn_at(ackreq, secreq, docca, txtime);
+}
+
+/**
+*
+* @fn void mac_SetTxEnhAckPending (uint8_t len)
+*
+* @brief Set the pending enhanced ack frame length
+*
+* @param len
+*
+* @return None
+*
+*/
+static __inline void mac_SetTxEnhAckPending(uint8_t len)
+{
+    mac_adapter.SetTxEnhAckPending(len);
+}
+
+/**
+*
+* @fn uint8_t mac_GetTxEnhAckPending (void)
+*
+* @brief Set the pending enhanced ack frame length
+*
+* @param None
+*
+* @return pending enhanced ack frame length
+*
+*/
+static __inline uint8_t mac_GetTxEnhAckPending(void)
+{
+    return mac_adapter.GetTxEnhAckPending();
+}
+
+/**
+*
+* @fn uint8_t  mac_LoadTxEnhAckPayload(uint8_t HdrL, uint8_t FrmL, uint8_t *TxFIFO)
+*
+* @brief Load frame into Tx G1 fifo
+*
+* @param *TxFIFO The tx fifo structure which user wants to transmit.
+*
+*        +---------+---------+-----------+
+*        | 1 byte  | 1 byte  | 125 bytes |
+*        +---------+---------+-----------+
+*        | HDR LEN | FRM LEN | USER DATA |
+*        +---------+---------+-----------+
+*
+* @return The process status.
+* @retval MAC_STS_SUCCESS The TX transmission is successful
+* @retval MAC_STS_DATA_LEN_ERROR the frame length is larger than 125 bytes
+*
+*/
+static __inline uint8_t mac_LoadTxEnhAckPayload(uint8_t HdrL, uint8_t FrmL, uint8_t *TxFIFO)
+{
+    pmac_txfifo_t pTxG1FIFO = (pmac_txfifo_t)MAC_TXG1_BASE_ADDR;
+
+    // max data length is 125
+    if ((FrmL > MAC_MAX_TX_FRM_LEN) || (FrmL < MAC_MIN_TX_FRM_LEN))
+    {
+        return MAC_STS_DATA_LEN_ERROR;
+    }
+
+    pTxG1FIFO->hdr_len = HdrL; //write header length into tx normal fifo
+    pTxG1FIFO->frm_len = FrmL; //write frame length into tx normal fifo
+    mac_memcpy_rom((void *)pTxG1FIFO->payload, TxFIFO, FrmL); //write data into tx normal fifo
+
+    return MAC_STS_SUCCESS;
+}
+
+/**
+*
+* @fn uint8_t  mac_TrigTxEnhAck(uint8_t early, uint8_t secreq)
+*
+* @brief Set if require ack, security process, then trigger Tx normal FIFO.
+*
+* @param early Trigger Tx enhack in rx early interrupt
+* @param secreq Trigger Tx enhack outgoing security process.
+*
+* @return Status
+* @retval MAC_STS_SUCCESS Tx enhack is triggered.
+*
+*/
+static __inline uint8_t mac_TrigTxEnhAck(uint8_t early, uint8_t secreq)
+{
+    return mac_adapter.trig_txenhack(early, secreq);
+}
+
+/**
+*
+* @fn void mac_TrigUpperEnc(void)
+*
+* @brief Trigger upper layer encrypt process
+*
+* @param None
+*
+* @return None
+*
+*/
+static __inline void mac_TrigUpperEnc(void)
+{
+    mac_adapter.trig_upperenc();
+}
+
+/**
+*
+* @fn void mac_TrigUpperDec(void)
+*
+* @brief Trigger upper layer decrypt process
+*
+* @param None
+*
+* @return None
+*
+*/
+static __inline void mac_TrigUpperDec(void)
+{
+    mac_adapter.trig_upperdec();
+}
+
+/*
+  RX
+*/
+/**
+*
+* @fn uint8_t  mac_Rx(uint8_t  *RxFIFO)
+*
+* @brief Read received packet from RX FIFO.
+*
+* @param *RxFIFO User data buffer pointer. The packet length will be put in the start address of buffer
+*
+*        +---------+-----------+------------------+--------------+------------+
+*        | 1 byte  | 125 bytes | 1 byte | 2 bytes |  4/2 bytes   |  3 bytes   |
+*        +---------+-----------+------------------+--------------+------------+
+*        | FRM LEN | USER DATA |   LQI  |  RSSI   |  TimeStamp   | SF Count   |
+*        +---------+-----------+------------------+--------------+------------+
+*
+* @return Rx status
+* @retval MAC_STS_FAILURE There is no received packet.
+* @retval MAC_STS_SUCCESS Retrived one packet
+*
+*/
+static __inline uint8_t mac_Rx(uint8_t *RxFIFO)
+{
+    return mac_adapter.rx(RxFIFO);
+}
+
+/**
+*
+* @fn void mac_RxFlush(void)
+*
+* @brief Flush rx fifo
+*
+* @return None
+*
+*/
+static __inline void mac_RxFlush(void)
+{
+    mac_adapter.RxFlush();
+}
+
+/**
+*
+* @fn uint8_t mac_RxFIFO(uint8_t *RxFIFO, uint8_t *MorePkt)
+*
+* @brief Check RX FIFO Full status and read received packet from RX FIFO.
+*
+* @param *RxFIFO User data buffer pointer.
+*
+* @param *MorePkt to report if more packet is ready in RX FIFO.
+*                 *MorePkt = false: no more new RX packet in FIFO
+*                 *MorePkt = true: there is more new RX packet in FIFO
+*
+* @return Rx status
+* @retval MAC_STS_FAILURE There is no received packet.
+* @retval MAC_STS_SUCCESS Retrived one packet
+*
+*/
+static __inline uint8_t mac_RxFIFO(uint8_t *RxFIFO, uint8_t *MorePkt)
+{
+    return mac_adapter.rxfifo(RxFIFO, MorePkt);
+}
+
+/*
+  Addr Match Filter
+*/
+/**
+*
+* @fn void mac_GetSrcMatchStatus(void)
+*
+* @brief Get source match filter status
+*
+* @return source match filter status
+*
+*/
+static __inline uint8_t mac_GetSrcMatchStatus(void)
+{
+    return mac_adapter.GetSrcMatchStatus();
+}
+
+/**
+*
+* @fn void mac_ClrSrcMatchStatus(void)
+*
+* @brief Clear source match filter status
+*
+* @return None
+*
+*/
+static __inline void mac_ClrSrcMatchStatus(void)
+{
+    mac_adapter.ClrSrcMatchStatus();
+}
+
+/**
+*
+* @fn void mac_SetAddrMatchMode(uint8_t mode)
+*
+* @brief config the mode of auto set frame pending bit for Ack frame
+*
+* @param mode AUTO_ACK_PENDING_MODE_ZIGBEE: set the pending bit as IEEE802.15.4 Spec;
+*             AUTO_ACK_PENDING_MODE_THREAD: set the pending bit as Thread Spec;
+*
+* @return None
+*
+*/
+static __inline void mac_SetAddrMatchMode(uint8_t mode)
+{
+    mac_adapter.set_addr_matchmode(mode);
+}
+
+/**
+*
+* @fn uint8_t mac_AddSrcShortAddrMatch(uint16_t short_addr, uint16_t panid)
+*
+* @brief To add a short address and panid pair to a entry of Source Address Match Filter.
+*
+* @param short_addr the short address to be added into the Source Address Match Filter.
+*
+* @param panid the panid to be added into the Source Address Match Filter.
+*
+* @return The function result.
+* @retval MAC_STS_SUCCESS add a new short address entry successfully.
+* @retval MAC_STS_HW_LIMIT no free address match entry.
+*
+*/
+static __inline uint8_t mac_AddSrcShortAddrMatch(uint16_t short_addr, uint16_t panid)
+{
+    return mac_adapter.add_short_match(short_addr, panid);
+}
+
+/**
+*
+* @fn uint8_t mac_DelSrcShortAddrMatch(uint16_t short_addr, uint16_t panid)
+*
+* @brief To disable a short address match entry by a given short address and panid pair.
+*
+* @param short_addr the short address of the short address match entry to be disabled
+*
+* @param panid the panidof the short address match entry to be disabled
+*
+* @return The function result.
+* @retval MAC_STS_SUCCESS disable a short address entry successfully.
+* @retval MAC_STS_FAILURE the short address match entry is not found.
+*
+*/
+static __inline uint8_t mac_DelSrcShortAddrMatch(uint16_t short_addr, uint16_t panid)
+{
+    return mac_adapter.del_short_match(short_addr, panid);
+}
+
+/**
+*
+* @fn void mac_DelAllSrcShortAddrMatch(void)
+*
+* @brief To disable all short address match entries.
+*
+* @return None
+*
+*/
+static __inline void mac_DelAllSrcShortAddrMatch(void)
+{
+    mac_adapter.del_short_match_all();
+}
+
+/**
+*
+* @fn uint8_t mac_AddSrcExtAddrMatch(uint8_t *pext_addr)
+*
+* @brief To add an extended address match entry of Source Address Match Filter.
+*
+* @param pext_addr the extended address to be added into the Source Address Match Filter.
+*
+* @return The function result.
+* @retval MAC_STS_SUCCESS add a new short address entry successfully.
+* @retval MAC_STS_HW_LIMIT no free address match entry.
+*
+*/
+static __inline uint8_t mac_AddSrcExtAddrMatch(uint8_t *pext_addr)
+{
+    return mac_adapter.add_ext_match(pext_addr);
+}
+
+/**
+*
+* @fn uint8_t mac_DelSrcExtAddrMatch(uint8_t *pext_addr)
+*
+* @brief To disable an extended address match entry by a given extended address.
+*
+* @param pext_addr the extended address of the extended address match entry to be disabled
+*
+* @return The function result.
+* @retval MAC_STS_SUCCESS disable a short address entry successfully.
+* @retval MAC_STS_FAILURE the short address match entry is not found.
+*
+*/
+static __inline uint8_t mac_DelSrcExtAddrMatch(uint8_t *pext_addr)
+{
+    return mac_adapter.del_ext_match(pext_addr);
+}
+
+/**
+*
+* @fn void mac_DelAllSrcExtAddrMatch(void)
+*
+* @brief To disable all extended address match entries.
+*
+* @return None
+*
+*/
+static __inline void mac_DelAllSrcExtAddrMatch(void)
+{
+    mac_adapter.del_ext_match_all();
+}
+
+/*
+  Security
+*/
+
+/**
+*
+* @fn void mac_SetNonce(uint8_t *nonce)
+*
+* @brief Set nonce into MAC.
+*
+* @param nonce the nonce structure to be loaded.
+*
+* @return None
+*
+*/
+static __inline void mac_SetNonce(uint8_t *nonce)
+{
+    mac_adapter.SetNonce(nonce);
+}
+
+/**
+*
+* @fn void mac_SetKey(uint8_t *key)
+*
+* @brief Load key into TxN key fifo.
+*
+* @param key_buf the key_buf to be loaded.
+*
+* @param key the key to be loaded.
+*
+* @return None
+*
+*/
+static __inline void mac_SetKey(uint8_t *key_buf, uint8_t *key)
+{
+    mac_adapter.SetKey(key_buf, key);
+}
+
+/**
+*
+* @fn void mac_LoadNonce(uint8_t *nonce)
+*
+* @brief Load nonce into MAC.
+*
+* @param nonce the nonce structure to be loaded.
+*
+* @return None
+*
+*/
+static __inline void mac_LoadNonce(uint8_t *nonce)
+{
+    mac_adapter.LoadNonce(nonce);
+}
+
+/**
+*
+* @fn void mac_LoadTxNKey(uint8_t *key)
+*
+* @brief Load key into TxN key fifo.
+*
+* @param key the TxN key to be loaded.
+*
+* @return None
+*
+*/
+static __inline void mac_LoadTxNKey(uint8_t *key)
+{
+    mac_adapter.LoadTxNKey(key);
+}
+
+/**
+*
+* @fn void mac_SetTxNChiper(uint8_t level)
+*
+* @brief config the security level of Normal FIFO cipher
+*
+* @param level the security level(as the defination in IEEE802.15.4 MAC Spec.)
+*
+* @return None
+*
+*/
+static __inline void mac_SetTxNChiper(uint8_t level)
+{
+    mac_adapter.SetTxNChiper(level);
+}
+
+/**
+*
+* @fn void mac_LoadTxEnhAckKey(uint8_t *key)
+*
+* @brief Load key into TxG1 key fifo.
+*
+* @param key the TxG1 key to be loaded.
+*
+* @return None
+*
+*/
+static __inline void mac_LoadTxEnhAckKey(uint8_t *key)
+{
+    mac_adapter.LoadTxEnhAckKey(key);
+}
+
+/**
+*
+* @fn void mac_SetTxEnhAckChiper(uint8_t level)
+*
+* @brief config the security level of GTS1 FIFO cipher
+*
+* @param level the security level(as the defination in IEEE802.15.4 MAC Spec.)
+*
+* @return None
+*
+*/
+static __inline void mac_SetTxEnhAckChiper(uint8_t level)
+{
+    mac_adapter.SetTxEnhAckChiper(level);
+}
+
+/**
+*
+* @fn uint8_t mac_GetSecMICLEN(uint8_t level)
+*
+* @brief Get the length of current security level.
+*
+* @param level the security level(as the defination in IEEE802.15.4 MAC Spec.)
+*
+* @return the MIC length of current security level.
+*
+*/
+static __inline uint8_t mac_GetSecMICLEN(uint8_t level)
+{
+    return mac_adapter.secmode_mic_len[level];
+}
+
+/**
+*
+* @fn uint8_t mac_GetSecHLEN(void)
+*
+* @brief Get the length of current receiving frame header
+*
+* @param None
+*
+* @return the frame header length of current receiving frame
+*
+*/
+static __inline uint8_t mac_GetSecHLEN(void)
+{
+    return mac_adapter.GetSecHLEN();
+}
+
+/**
+*
+* @fn void mac_SetSecHLEN(uint8_t val)
+*
+* @brief Set the frame header length for frame decryption in RX FIFO
+*
+* @param val the secure frame header length
+*
+*/
+static __inline void mac_SetSecHLEN(uint8_t val)
+{
+    mac_adapter.SetSecHLEN(val);
+}
+
+/**
+*
+* @fn void mac_SetRxChiper(uint8_t level)
+*
+* @brief config the security level of RX FIFO cipher
+*
+* @param level the security level(as the defination in IEEE802.15.4 MAC Spec.)
+*
+* @return None
+*
+*/
+static __inline void mac_SetRxChiper(uint8_t level)
+{
+    mac_adapter.SetRxChiper(level);
+}
+
+/**
+*
+* @fn void mac_TrigRxDecryption(void)
+*
+* @brief Trigger the received secure frame decryption process,
+*        MAC HW will issue RX done interrupt when decryption is finished.
+*        RX FIFO decryption finish status is indicated by rxnif
+*        (RX done interrupt).
+*        The MIC error status is indicated by MAC->rxm_sts_b.secdecerr once
+*        the decryption is done.
+*
+* @param None
+*
+* @return None
+*
+*/
+static __inline void mac_TrigRxDecryption(void)
+{
+    mac_adapter.TrigRxDecryption();
+}
+
+/**
+*
+* @fn void mac_IgnoreRxDec(void)
+*
+* @brief Ignore the received secure frame decryption process.
+*
+* @param None
+*
+* @return None
+*
+*/
+static __inline void mac_IgnoreRxDec(void)
+{
+    mac_adapter.IgnoreRxDec();
+}
+
+/**
+*
+* @fn uint8_t  mac_UpperCipher(uint8_t  SecMode, uint8_t  *SecKey, uint8_t  *SecNonce)
+*
+* @brief Using TX normal FIFO to do upper cipher encryption. The data to be encrypted
+*        should be filled into the TX Normal FIFO before calling this function. It should follow
+*        the structure of the TX FIFO format.
+*        The encrypted data will be stored to the TX Normal FIFO and replace the origional data.
+*
+* @param SecMode Security mode.
+* @param *SecKey Security key pointer, security key is 16 bytes.
+* @param SecNonce Security nonce, nonce is 13 bytes
+*
+* @return Process status.
+* @retval MAC_STS_SUCCESS Encryption success.
+* @retval MAC_STS_UNSUPPORT_SECURITY_MODE
+* @retval MAC_STS_DATA_LEN_ERROR
+* @retval MAC_STS_SECURITY_FAILED
+*
+*/
+static __inline uint8_t mac_UpperCipher(uint8_t SecMode, uint8_t *SecKey, uint8_t *SecNonce)
+{
+    return mac_adapter.upper_cipher(SecMode, SecKey, SecNonce);
+}
+
+/**
+*
+* @fn uint8_t  mac_UpperDecipher(uint8_t  *TxFIFO, uint8_t  SecMode, uint8_t  *SecKey, uint8_t  *SecNonce)
+*
+* @brief Using TX normal FIFO to do upper cipher decryption. The data to be decrypted
+*        should be filled into the TX Normal FIFO before calling this function. It should follow
+*        the structure of the TX FIFO format.
+*        The decrypted data will be stored to the TX Normal FIFO and replace the origional data.
+*
+* @param SecMode Security mode.
+* @param *SecKey Security key pointer, security key is 16 bytes.
+* @param SecNonce Security nonce, nonce is 13 bytes
+*
+* @return Process status.
+* @retval MAC_STS_SUCCESS Encryption success.
+* @retval MAC_STS_UNSUPPORT_SECURITY_MODE
+* @retval MAC_STS_DATA_LEN_ERROR
+* @retval MAC_STS_SECURITY_FAILED
+*
+*/
+static __inline uint8_t mac_UpperDecipher(uint8_t SecMode, uint8_t *SecKey, uint8_t *SecNonce)
+{
+    return mac_adapter.upper_decipher(SecMode, SecKey, SecNonce);
+}
+
+/**
+*
+* @fn uint32_t mac_GetRetentionRegSize(void)
+*
+* @brief To get the required buffer size for default registers backup list.
+*
+* @param None
+*
+* @return the required buffer size, in byte, for registers backup
+*
+*/
+static __inline uint32_t mac_GetRetentionRegSize(void)
+{
+    return mac_adapter.get_retention_reg_size();
+}
+
+/**
+*
+* @fn *mac_BackupRetenReg(uint8_t *preten_buf)
+*
+* @brief To backup MAC registers before entring sleep mode.
+*        the registers to backup are listed in preten_reg32b_list,
+*        preten_reg16b_list, preten_reg8b_list
+*
+* @param preten_buf the buffer for registers backup. It can be NULL if
+*                   no register backup is required.
+*
+* @return point to the end of register stored memory
+*
+*/
+static __inline void *mac_BackupRetenReg(uint8_t *preten_buf)
+{
+    return mac_adapter.backup_reten_reg(preten_buf);
+}
+
+/**
+*
+* @fn void *mac_RestoreRetenReg(uint8_t *preten_buf)
+*
+* @brief To restore MAC registers after resume from sleep mode.
+*
+* @param preten_buf the buffer for registers backup. this function
+*                   will get register backup value from this buffer
+*                   for restoring.
+*
+* @return point to the end of register stored memory
+*
+*/
+static __inline void *mac_RestoreRetenReg(uint8_t *preten_buf)
+{
+    return mac_adapter.restore_reten_reg(preten_buf);
+}
+
+/**
+*
+* @fn void mac_PTA_Enable(uint8_t enable)
+*
+* @brief Enable or disable MAC PTA control function.
+*        if PTA is enabled, MAC will send PTA request to grant
+*        antenna when packets TX/RX.
+*
+* @param enable PTA enable: 1: enable; 0: disable
+*
+* @return None
+*
+*/
+static __inline void mac_PTA_Enable(uint8_t enable)
+{
+    mac_adapter.PTA_Enable(enable);
+}
+
+/**
+*
+* @fn void mac_PTA_PrityDutyEnable(uint8_t enable)
+*
+* @brief Enable or disable PTA priority duty control function.
+*        If PTA priority duty control is enabled, MAC will send PTA request
+*        to grant antenna for idle RX periodically.
+*
+* @param enable 1: enable; 0: disable
+*
+* @return None
+*
+*/
+static __inline void mac_PTA_PrityDutyEnable(uint8_t enable)
+{
+    mac_adapter.PTA_PrityDutyEnable(enable);
+}
+
+/**
+*
+* @fn void mac_PTA_LoRXReq_Enable(uint8_t enable)
+*
+* @brief Enable or disable issue PTA request for low priority RX.
+*        Control of whether to issue a low priority RX PTA request for
+*        802.15.4 idle RX. Default is enabled.
+*
+* @param enable enable to issue low priority RX PTA request
+*
+* @return None
+*
+*/
+static __inline void mac_PTA_LoRXReq_Enable(uint8_t enable)
+{
+    mac_adapter.PTA_LoRXReq_Enable(enable);
+}
+
+/**
+*
+* @fn void mac_PTA_ShareLNA(uint8_t is_share_lan)
+*
+* @brief To setup whether the 802.15.4 PHY share the same LNA with WLan.
+*        802.15.4 PHY PTA should be configured accorrding to whether the RF
+*        share the same LNA with WLan. If it's sharing the LNA, the 802.15.4
+*        PTA should not issue high priority RX PTA request for RX hit.
+*
+* @param is_share_lna indicate to PTA hardware for whether RF is sharing
+*                     LNA with WLan, default is 'true'
+*
+* @return None
+*
+*/
+static __inline void mac_PTA_ShareLNA(uint8_t is_share_lna)
+{
+    mac_adapter.PTA_ShareLNA(is_share_lna);
+}
+
+/**
+*
+* @fn void mac_PTA_CCAReq_Enable(uint8_t enable)
+*
+* @brief To configure whether issue a RX PTA request for the CCA
+*        of a packet TX.
+*
+* @param enable 0: no dedicated RX PTA Req for CCA, only a TX PTA Req
+*                  for CCA and packet TX. (default)
+*               1: a separate RX PTA Req for CCA, another TX PTA Req
+*                  for packet TX.
+*
+* @return None
+*
+*/
+static __inline void mac_PTA_CCAReq_Enable(uint8_t enable)
+{
+    mac_adapter.PTA_CCAReq_Enable(enable);
+}
+
+/**
+*
+* @fn void mac_PTA_TXReq_Pri(uint8_t priority)
+*
+* @brief To configure the priority of TX PTA request for a packet TX.
+*
+* @param hi_priority 0: low priority (default)
+*                 1: high priority
+*
+* @return None
+*
+*/
+static __inline void mac_PTA_TXReq_Pri(uint8_t hi_priority)
+{
+    mac_adapter.PTA_TXReq_Pri(hi_priority);
+}
+
+/**
+*
+* @fn void mac_PTA_DutySetTick(uint32_t tick_us)
+*
+* @brief Set the tick time of PTA duty interval control, in us unit.
+*        the PTA high/low priority period setting is based on this tick time.
+*
+* @param tick_us time for a tick, in micro-second.
+*
+* @return None
+*
+*/
+static __inline void mac_PTA_DutySetTick(uint32_t tick_us)
+{
+    mac_adapter.PTA_DutySetTick(tick_us);
+}
+
+/**
+*
+* @fn void mac_PTA_DutySetRatio(uint32_t high_ticks, uint32_t low_ticks)
+*
+* @brief Set the time period of PTA high/low priority duty, in unit of PTA ticks.
+*        the MAC will issue a high priority PTA request at start of every high priority
+*        duty interval.
+*
+* @param high_ticks the time period of PTA high priority duty, in unit of PTA ticks
+*
+* @param low_ticks the time period of PTA low priority duty, in unit of PTA ticks
+*
+* @return None
+*
+*/
+static __inline void mac_PTA_DutySetRatio(uint32_t high_ticks, uint32_t low_ticks)
+{
+    mac_adapter.pta_duty_set_ratio(high_ticks, low_ticks);
+}
+
+/**
+*
+* @fn void mac_DisBTClkTmr(uint32_t tid)
+*
+* @brief Disable a BT clock timer if it is running (enabled)
+*
+* @param tid the ID of BT clock timer to be disable
+*
+* @return None
+*
+*/
+static __inline void mac_DisBTClkTmr(uint32_t tid)
+{
+    mac_adapter.DisBTClkTmr(tid);
+}
+
+static __inline void BT_HCIRstStart_Callback(void)
+{
+    mac_adapter.bt_hci_reset_start();
+}
+
+static __inline void BT_HCIRstEnd_Callback(void)
+{
+    mac_adapter.bt_hci_reset_end();
+}
+
+/**
+*
+* @fn void mac_GrantPHYReq(uint8_t slot_num)
+*
+* @brief Request to grant the PHY
+*
+* @param slot_offset the number of slot offset from current BT slot number to grant the PHY
+*
+* @return None
+*
+*/
+
+static __inline void mac_GrantPHYReq(uint8_t slot_offset)
+{
+    mac_adapter.grant_phy_req(slot_offset);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif    // end of #ifndef _MAC_DRIVER_H_
diff --git a/bee/drivers/mac_802154/rom/mac_drv_rom_patch.h b/bee/drivers/mac_802154/rom/mac_drv_rom_patch.h
new file mode 100644
index 00000000..aa670e55
--- /dev/null
+++ b/bee/drivers/mac_802154/rom/mac_drv_rom_patch.h
@@ -0,0 +1,71 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**************************************************************************//**
+ * @file     mac_drv_rom_patch.h
+ * @brief    Define MAC driver ROM code patch macros.
+ *
+ * @version  V1.00
+ * @date     2022-10-03
+ *
+ * @note
+ *
+ ******************************************************************************/
+
+#ifndef _MAC_DRV_ROM_PATCH_H_
+#define _MAC_DRV_ROM_PATCH_H_
+
+#if !defined(MAC_ROM_PATCH)
+#define MAC_ROM_PATCH 1 // if enable ROM code patch
+#endif
+
+extern pmac_driver_t pmac_driver;
+
+#define MAC_ROM_PATCH_FUNC_EXIST(func) ((pmac_driver != NULL) && (pmac_driver->rcp != NULL) && (pmac_driver->rcp->func != NULL))
+#define MAC_ROM_PATCH_FUNC(func) (pmac_driver->rcp->func)
+
+#define mac_memcpy_patch_exist()                MAC_ROM_PATCH_FUNC_EXIST(memcpy)
+#define mac_porting_init_patch_exist()          MAC_ROM_PATCH_FUNC_EXIST(porting_init)
+#define mac_SoftwareTimer_IntrHandler_patch_exist()\
+    MAC_ROM_PATCH_FUNC_EXIST(swtimer_handler)
+#define mac_EDScanProcess_patch_exist()         MAC_ROM_PATCH_FUNC_EXIST(edscan_handler)
+#define mac_EnterCritical_patch_exist()         MAC_ROM_PATCH_FUNC_EXIST(enter_critical)
+#define mac_ExitCritical_patch_exist()          MAC_ROM_PATCH_FUNC_EXIST(exit_critical)
+#define mac_Reset_patch_exist()                 MAC_ROM_PATCH_FUNC_EXIST(reset)
+#define mac_GetCurrentBTUS_patch_exist()        MAC_ROM_PATCH_FUNC_EXIST(curr_btus)
+#define mac_BTClkToUS_patch_exist()             MAC_ROM_PATCH_FUNC_EXIST(btclk2us)
+#define mac_SetBTClkUSInt_patch_exist()         MAC_ROM_PATCH_FUNC_EXIST(set_btus_int)
+#define mac_RstRF_patch_exist()                 MAC_ROM_PATCH_FUNC_EXIST(reset_rf)
+#define mac_SetRadioState_patch_exist()         MAC_ROM_PATCH_FUNC_EXIST(set_radio_state)
+#define mac_GetRadioState_patch_exist()         MAC_ROM_PATCH_FUNC_EXIST(get_radio_state)
+#define mac_EnTxNCsmacaCca_patch_exist()        MAC_ROM_PATCH_FUNC_EXIST(enable_txn_csmacca)
+#define mac_DisTxNCsmacaCca_patch_exist()       MAC_ROM_PATCH_FUNC_EXIST(disable_txn_csmacca)
+#define mac_SoftwareTimer_Init_patch_exist()    MAC_ROM_PATCH_FUNC_EXIST(swtimer_init)
+#define mac_SoftwareTimer_Free_patch_exist()    MAC_ROM_PATCH_FUNC_EXIST(swtimer_free)
+#define mac_SoftwareTimer_Stop_patch_exist()    MAC_ROM_PATCH_FUNC_EXIST(swtimer_stop)
+#define mac_Rx_patch_exist()                    MAC_ROM_PATCH_FUNC_EXIST(rx)
+
+#define mac_memcpy_patch                        MAC_ROM_PATCH_FUNC(memcpy)
+#define mac_porting_init_patch                  MAC_ROM_PATCH_FUNC(porting_init)
+#define mac_SoftwareTimer_IntrHandler_patch     MAC_ROM_PATCH_FUNC(swtimer_handler)
+#define mac_EDScanProcess_patch                 MAC_ROM_PATCH_FUNC(edscan_handler)
+#define mac_EnterCritical_patch                 MAC_ROM_PATCH_FUNC(enter_critical)
+#define mac_ExitCritical_patch                  MAC_ROM_PATCH_FUNC(exit_critical)
+#define mac_Reset_patch                         MAC_ROM_PATCH_FUNC(reset)
+#define mac_GetCurrentBTUS_patch                MAC_ROM_PATCH_FUNC(curr_btus)
+#define mac_BTClkToUS_patch                     MAC_ROM_PATCH_FUNC(btclk2us)
+#define mac_SetBTClkUSInt_patch                 MAC_ROM_PATCH_FUNC(set_btus_int)
+#define mac_RstRF_patch                         MAC_ROM_PATCH_FUNC(reset_rf)
+#define mac_SetRadioState_patch                 MAC_ROM_PATCH_FUNC(set_radio_state)
+#define mac_GetRadioState_patch                 MAC_ROM_PATCH_FUNC(get_radio_state)
+#define mac_EnTxNCsmacaCca_patch                MAC_ROM_PATCH_FUNC(enable_txn_csmacca)
+#define mac_DisTxNCsmacaCca_patch               MAC_ROM_PATCH_FUNC(disable_txn_csmacca)
+#define mac_SoftwareTimer_Init_patch            MAC_ROM_PATCH_FUNC(swtimer_init)
+#define mac_SoftwareTimer_Free_patch            MAC_ROM_PATCH_FUNC(swtimer_free)
+#define mac_SoftwareTimer_Stop_patch            MAC_ROM_PATCH_FUNC(swtimer_stop)
+#define mac_Rx_patch                            MAC_ROM_PATCH_FUNC(rx)
+
+#endif  /* _MAC_DRV_ROM_PATCH_H_ */
diff --git a/bee/drivers/mac_802154/rom/mac_reg.h b/bee/drivers/mac_802154/rom/mac_reg.h
new file mode 100644
index 00000000..07771451
--- /dev/null
+++ b/bee/drivers/mac_802154/rom/mac_reg.h
@@ -0,0 +1,4075 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*
+ *
+ * @file     mac_reg.h
+ * @brief    CMSIS HeaderFile
+ * @version  1.0
+ * @date     12. July 2023
+ * @note     Generated by SVDConv V3.3.35 on Wednesday, 12.07.2023 18:31:32
+ *           from File 'rtl87x2g_mac_fpga_remap.svd',
+ *           last modified on Wednesday, 12.07.2023 10:30:41
+ */
+
+/** @addtogroup Realtek Semiconductor Corp.
+  * @{
+  */
+
+
+/** @addtogroup rtl87x2g
+  * @{
+  */
+
+
+#ifndef MAC_REG_H
+#define MAC_REG_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/** @addtogroup Configuration_of_CMSIS
+  * @{
+  */
+
+
+
+
+/** @} */ /* End of group Configuration_of_CMSIS */
+
+#include "mac_port_macro.h"
+
+#ifndef __IM                                    /*!< Fallback for older CMSIS versions                                         */
+#define __IM   __I
+#endif
+#ifndef __OM                                    /*!< Fallback for older CMSIS versions                                         */
+#define __OM   __O
+#endif
+#ifndef __IOM                                   /*!< Fallback for older CMSIS versions                                         */
+#define __IOM  __IO
+#endif
+
+
+/* ========================================  Start of section using anonymous unions  ======================================== */
+#if defined (__CC_ARM)
+#pragma push
+#pragma anon_unions
+#elif defined (__ICCARM__)
+#pragma language=extended
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang diagnostic push
+#pragma clang diagnostic ignored "-Wc11-extensions"
+#pragma clang diagnostic ignored "-Wreserved-id-macro"
+#pragma clang diagnostic ignored "-Wgnu-anonymous-struct"
+#pragma clang diagnostic ignored "-Wnested-anon-types"
+#elif defined (__GNUC__)
+/* anonymous unions are enabled by default */
+#elif defined (__TMS470__)
+/* anonymous unions are enabled by default */
+#elif defined (__TASKING__)
+#pragma warning 586
+#elif defined (__CSMC__)
+/* anonymous unions are enabled by default */
+#else
+#warning Not supported compiler type
+#endif
+
+
+/* =========================================================================================================================== */
+/* ================                            Device Specific Peripheral Section                             ================ */
+/* =========================================================================================================================== */
+
+
+/** @addtogroup Device_Peripheral_peripherals
+  * @{
+  */
+
+
+
+/* =========================================================================================================================== */
+/* ================                                            MAC                                            ================ */
+/* =========================================================================================================================== */
+
+
+/**
+  * @brief IEEE802.15.4 MAC (MAC)
+  */
+
+typedef struct                                  /*!< (@ 0x40055000) MAC Structure                                              */
+{
+
+    union
+    {
+        __IOM uint32_t
+        device_ctrl;                 /*!< (@ 0x00000000) MAC Device Control Register                                */
+
+        struct
+        {
+__IOM uint32_t coord      :
+            1;            /*!< [0..0] Coordinator: 0: (default) Device is not set as coordinator;
+                                                     1: Set device as coordinator                                              */
+__IOM uint32_t pancoord   :
+            1;            /*!< [1..1] PAN Coordinator: 0: (default) Device is not set as PAN
+                                                     coordinator; 1: Set device as PAN coordinator                             */
+__IOM uint32_t mac_lpbk   :
+            1;            /*!< [2..2] MAC loopback function enable                                       */
+__IOM uint32_t noackrsp   :
+            1;            /*!< [3..3] Automatic Acknowledgement Response: 0: (default) Enables
+                                                     automatic acknowledgement response; 1: Disables automatic
+                                                     acknowledgement response                                                  */
+            uint32_t            : 1;
+__IOM uint32_t nocrc      :
+            1;            /*!< [5..5] No CRC data appended with normal fifo                              */
+__IOM uint32_t fifoen     :
+            1;            /*!< [6..6] The TXFIFO and RXFIFO output enable control: 0: The TXFIFO
+                                                     and RXFIFO are always output enabled; 1: The enabled signal
+                                                     for the TXFIFO and RXFIFO output is controlled by the internal
+                                                     state machine                                                             */
+            uint32_t            : 1;
+__IOM uint32_t split_irq  :
+            1;            /*!< [8..8] Split security IRQ with normal IRQ                                 */
+__IOM uint32_t irqpol     :
+            1;            /*!< [9..9] Interrupt Edge Polarity: 0: (default) Falling edge; 1:
+                                                     Rising edge                                                               */
+            uint32_t            : 6;
+__IOM uint32_t tickp      :
+            9;            /*!< [24..16] Ticks period representing a symbol.Unit in system clock
+                                                     (20MHz). Default a symbol time is 16us. Tickp = 16/(1/20)
+                                                     = 320d = 140H                                                             */
+            uint32_t            : 7;
+        } device_ctrl_b;
+    } ;
+
+    union
+    {
+        __IOM uint16_t
+        panid;                       /*!< (@ 0x00000004) PAN ID Configuration Register                              */
+
+        struct
+        {
+__IOM uint16_t panid      :
+            16;           /*!< [15..0] 16-bits PAN identifier of this device                             */
+        } panid_b;
+    } ;
+
+    union
+    {
+        __IOM uint16_t
+        sadr;                        /*!< (@ 0x00000006) Short Address Configuration Register                       */
+
+        struct
+        {
+__IOM uint16_t sadr       :
+            16;           /*!< [15..0] 16-bits Short Address of this device                              */
+        } sadr_b;
+    } ;
+
+    union
+    {
+        __IOM uint32_t
+        eadr_l;                      /*!< (@ 0x00000008) Extended Address Lower Bytes Register                      */
+
+        struct
+        {
+__IOM uint32_t eadr_l     :
+            32;           /*!< [31..0] Bits[31:0] of Extended Address of this device                     */
+        } eadr_l_b;
+    } ;
+
+    union
+    {
+        __IOM uint32_t
+        eadr_h;                      /*!< (@ 0x0000000C) Extended Address Higher Bytes Register                     */
+
+        struct
+        {
+__IOM uint32_t eadr_h     :
+            32;           /*!< [31..0] Bits[63:32] of Extended Address of this device                    */
+        } eadr_h_b;
+    } ;
+
+    union
+    {
+        __IOM uint32_t
+        clk_ctrl;                    /*!< (@ 0x00000010) Clock Gated Control Register                               */
+
+        struct
+        {
+__IOM uint32_t ctrl_sec   :
+            1;            /*!< [0..0] Security clock controller                                          */
+__IOM uint32_t en_sec     :
+            1;            /*!< [1..1] Security clock enable/disable when CTRL_SEC is '1'                 */
+__IOM uint32_t entxm      :
+            1;            /*!< [2..2] TX MAC Clock Enable: 0: (default) Disable; 1: Enable               */
+__IOM uint32_t engts      :
+            1;            /*!< [3..3] GTS FIFO Clock: 0: (default) Disable; 1: Enable                    */
+__IOM uint32_t enrxm      :
+            1;            /*!< [4..4] RX MAC Clock Enable: 0: (default) Disable; 1: Enable               */
+__IOM uint32_t txn_off    :
+            1;            /*!< [5..5] TXNFIFO clock always off                                           */
+__IOM uint32_t txb_on     :
+            1;            /*!< [6..6] Beacon FIFO clock always on                                        */
+__IOM uint32_t ffidle     :
+            1;            /*!< [7..7] Force Clock Enable (Rx / Source Match Filter / GTS FIFO
+                                                     / TX Normal)0: (default) Disable1: Enable                                 */
+__IOM uint32_t ed_scan_clkon :
+            1;         /*!< [8..8] Force enable clock of ED scan block0: (default) Disable,
+                                                     clock is auto-gated1: Enable                                              */
+__IOM uint32_t phy_arb_clkon :
+            1;         /*!< [9..9] Force enable clock of PHY arbitration block0: (default)
+                                                     Disable, clock is auto-gated1: Enable                                     */
+__IOM uint32_t fifo_clkon :
+            1;            /*!< [10..10] Force enable Beacon / Normal / GTS / RX / SEC KEY FIFO
+                                                     Clock:0: (default) Disable1: Enable                                       */
+__IOM uint32_t dbg_clkon  :
+            1;            /*!< [11..11] Force enable Debug counter circuit clock:0: (default)
+                                                     Disable1: Enable                                                          */
+            uint32_t            : 20;
+        } clk_ctrl_b;
+    } ;
+
+    union
+    {
+        __IOM uint32_t
+        mac_timer;                   /*!< (@ 0x00000014) MAC Timer Control Register                                 */
+
+        struct
+        {
+__OM  uint32_t mactmr_l   :
+            8;            /*!< [7..0] 16-Bit MAC Timer, Low Byte                                         */
+__OM  uint32_t mactmr_h   :
+            8;            /*!< [15..8] 16-Bit MAC Timer, High Byte. Unit: 8us. FW writing this
+                                                     field will trigger MAC timer start to count down                          */
+__IOM uint32_t mactmrfr   :
+            1;            /*!< [16..16] MAC Timer Free Run: 0: (default) Disable; 1: Enable.
+                                                     If the free-run value of MAC timer is selected to be attached
+                                                     to every received packet behind RSSI, this MAC timer free
+                                                     run should be enabled.                                                    */
+            uint32_t            : 7;
+__OM  uint32_t btcmp0_dis :
+            1;            /*!< [24..24] BT-MAC Timer (BT Clock comparator) 0 disable.0: (default)
+                                                     malfunction1: Disable BT-MAC timer comparator function.
+                                                     FW can write this bit as 1 to stop the BT-MAC timer 0 if
+                                                     it is running.This bit is cleared to '0' by hardware automatically.       */
+__OM  uint32_t btcmp1_dis :
+            1;            /*!< [25..25] BT-MAC Timer (BT Clock comparator) 1 disable.0: (default)
+                                                     malfunction1: Disable BT-MAC timer comparator function.
+                                                     FW can write this bit as 1 to stop the BT-MAC timer 1 if
+                                                     it is running.This bit is cleared to '0' by hardware automatically
+                                                     .                                                                         */
+__OM  uint32_t btcmp2_dis :
+            1;            /*!< [26..26] BT-MAC Timer (BT Clock comparator) 2 disable.0: (default)
+                                                     malfunction1: Disable BT-MAC timer comparator function.
+                                                     FW can write this bit as 1 to stop the BT-MAC timer 2 if
+                                                     it is running.This bit is cleared to '0' by hardware automatically
+                                                     .                                                                         */
+__OM  uint32_t btcmp3_dis :
+            1;            /*!< [27..27] BT-MAC Timer (BT Clock comparator) 3 disable.0: (default)
+                                                     malfunction1: Disable BT-MAC timer comparator function.
+                                                     FW can write this bit as 1 to stop the BT-MAC timer 3 if
+                                                     it is running.This bit is cleared to '0' by hardware automatically
+                                                     .                                                                         */
+            uint32_t            : 4;
+        } mac_timer_b;
+    } ;
+
+    union
+    {
+        __IOM uint32_t
+        rst_ctrl;                    /*!< (@ 0x00000018) MAC Reset Control Register                                 */
+
+        struct
+        {
+            uint32_t            : 16;
+__OM  uint32_t rstmac     :
+            1;            /*!< [16..16] MAC and Registers Reset: 1: Reset MAC circuitry and
+                                                     all registers. Initialization is needed after RSTMAC reset.
+                                                     Bit is automatically cleared to '0' by hardware                           */
+            uint32_t            : 15;
+        } rst_ctrl_b;
+    } ;
+
+    union
+    {
+        __IOM uint32_t
+        rx_frm_length;               /*!< (@ 0x0000001C) RX Decryption Header Length Control Register               */
+
+        struct
+        {
+__IOM uint32_t hlen       :
+            7;            /*!< [6..0] Header Length for Decryption Process in RX FIFO. Header
+                                                     length of the received packet including frame control field,
+                                                     sequence number and address information. If a user-defined
+                                                     header length (including auxiliary header length) is used,
+                                                     user shall update the length value by writing HLEN[5:0]
+                                                     back after security interrupt received. 000000: (default)                 */
+            uint32_t            : 1;
+__IM  uint32_t flen       :
+            7;            /*!< [14..8] Internal frame length                                             */
+            uint32_t            : 17;
+        } rx_frm_length_b;
+    } ;
+
+    union
+    {
+        __IOM uint32_t
+        intmsk;                      /*!< (@ 0x00000020) Interrupt Mask Control Register                            */
+
+        struct
+        {
+__IOM uint32_t txnmsk     :
+            1;            /*!< [0..0] TX Normal FIFO Transmission Interrupt Mask: 0: Enable
+                                                     the TX Normal FIFO transmission interrupt; 1: (default)
+                                                     Disable the TX Normal FIFO transmission interrupt                         */
+__IOM uint32_t txg1msk    :
+            1;            /*!< [1..1] TX GTS1 FIFO Transmission Interrupt Mask: 0: Enable the
+                                                     TX GTS1 FIFO transmission interrupt; 1: (default) Disable
+                                                     the TX GTS1 FIFO transmission interrupt                                   */
+__IOM uint32_t txg2msk    :
+            1;            /*!< [2..2] TX GTS2 FIFO Transmission Interrupt Mask: 0: Enable the
+                                                     TX GTS2 FIFO transmission interrupt; 1: (default) Disable
+                                                     the TX GTS2 FIFO transmission interrupt                                   */
+__IOM uint32_t txnterrmsk :
+            1;            /*!< [3..3] TX at given time error Interrupt Mask: 0: Enable the
+                                                     TX at given time error interrupt; 1: (default) Disable
+                                                     the TX at given time error interrupt TX at given time error
+                                                     interrupt is triggered when a Normal FIFO TX at a scheduled
+                                                     TX time error is occurred. This error could be caused by
+                                                     an invalid TX time or CCA failure                                         */
+__IOM uint32_t rxelymsk   :
+            1;            /*!< [4..4] RX eraly Interrupt Mask: 0: Enable the RX eraly interrupt;
+                                                     1: (default) Disable the RX eraly interrupt RX early interrupt
+                                                     is triggered when on the receiving of an incoming frame
+                                                     and its MAC header and Secure AUX Header (if present) are
+                                                     received complete and pass the RX filter check                            */
+__IOM uint32_t secmsk     :
+            1;            /*!< [5..5] Security Key Request Interrupt Mask: 0: Enable security
+                                                     key request interrupt; 1: (default) Disable the security
+                                                     key request interrupt                                                     */
+__IOM uint32_t rxmsk      :
+            1;            /*!< [6..6] RX FIFO Reception Interrupt Mask: 0: Enable the RX FIFO
+                                                     reception interrupt; 1: (default) Disable the RX FIFO reception
+                                                     interrupt                                                                 */
+__IOM uint32_t mactmrmsk  :
+            1;            /*!< [7..7] MAC Timer Interrupt Mask: 0: Enable the MAC timer interrupt;
+                                                     1: (default) Disable the MAC timer interrupt                              */
+__IOM uint32_t btcmp0msk  :
+            1;            /*!< [8..8] BT-MAC timer 0 Interrupt Mask: 0: Enable the BT-MAC timer
+                                                     interrupt; 1: (default) Disable the BT-MAC timer interrupt
+                                                     BT-MAC timer interrupt is triggered when the counter value
+                                                     of the free run BT-MAC timer is matched with the BT-MAC
+                                                     timer comparator value.                                                   */
+__IOM uint32_t btcmp1msk  :
+            1;            /*!< [9..9] BT-MAC timer 1 Interrupt Mask: 0: Enable the BT-MAC timer
+                                                     interrupt; 1: (default) Disable the BT-MAC timer interrupt
+                                                     BT-MAC timer interrupt is triggered when the counter value
+                                                     of the free run BT-MAC timer is matched with the BT-MAC
+                                                     timer comparator value.                                                   */
+__IOM uint32_t gntmsk     :
+            1;            /*!< [10..10] PHY grant update Interrupt Mask: 0: Enable PHY grant
+                                                     update interrupt; 1: (default) Disable the PHY grant update
+                                                     interrupt PHY grant update interrupt is triggered when
+                                                     the PHY grant request success or failed, or PHY grant is
+                                                     de-asserted by Arbitration Coordinator.                                   */
+__IOM uint32_t edscanmsk  :
+            1;            /*!< [11..11] ED scan done Interrupt Mask: 0: Enable ED scan done
+                                                     interrupt; 1: (default) Disable the ED scan done interrupt
+                                                     ED scan done interrupt is triggered when an ED scan procedure
+                                                     is done                                                                   */
+__IOM uint32_t sfstartmsk :
+            1;            /*!< [12..12] Slotted enable Superframe start Interrupt Mask: 0:
+                                                     Enable the superframe start interrupt; 1: (default) Disable
+                                                     the superframe start interrupt                                            */
+__IOM uint32_t sfendmsk   :
+            1;            /*!< [13..13] Slotted enable Superframe end Interrupt Mask: 0: Enable
+                                                     the superframe end interrupt; 1: (default) Disable the
+                                                     superframe end interrupt                                                  */
+__IOM uint32_t btcmp2msk  :
+            1;            /*!< [14..14] BT-MAC timer 2 Interrupt Mask: 0: Enable the BT-MAC
+                                                     timer interrupt; 1: (default) Disable the BT-MAC timer
+                                                     interrupt BT-MAC timer interrupt is triggered when the
+                                                     counter value of the free run BT-MAC timer is matched with
+                                                     the BT-MAC timer comparator value.                                        */
+__IOM uint32_t btcmp3msk  :
+            1;            /*!< [15..15] BT-MAC timer 3 Interrupt Mask: 0: Enable the BT-MAC
+                                                     timer interrupt; 1: (default) Disable the BT-MAC timer
+                                                     interrupt BT-MAC timer interrupt is triggered when the
+                                                     counter value of the free run BT-MAC timer is matched with
+                                                     the BT-MAC timer comparator value.                                        */
+            uint32_t            : 16;
+        } intmsk_b;
+    } ;
+
+    union
+    {
+        __IOM uint32_t
+        isrsts;                      /*!< (@ 0x00000024) Interrupt Status Register                                  */
+
+        struct
+        {
+__IOM uint32_t txnif      :
+            1;            /*!< [0..0] TX Normal FIFO Transmission Interrupt: 0: (default) No
+                                                     TX Normal FIFO transmission interrupt occurred; 1: TX Normal
+                                                     FIFO transmission interrupt occurred, Write 1 clear                       */
+__IOM uint32_t txg1if     :
+            1;            /*!< [1..1] TX GTS1 FIFO Transmission Interrupt: 0: (default) No
+                                                     TX GTS1 FIFO transmission interrupt occurred; 1: A TX GTS1
+                                                     FIFO transmission interrupt occurred, Write 1 clear                       */
+__IOM uint32_t txg2if     :
+            1;            /*!< [2..2] TX GTS2 FIFO Transmission Interrupt: 0: (default) No
+                                                     TX GTS2 FIFO transmission interrupt occurred; 1: A TX GTS2
+                                                     FIFO transmission interrupt occurred, Write 1 clear                       */
+__IOM uint32_t txnterrif  :
+            1;            /*!< [3..3] TX at given time error Interrupt status: 0: (default)
+                                                     no TX at given time error interrupt occurred; 1: the TX
+                                                     at given time error interrupt is occurred. TX at given
+                                                     time error interrupt is triggered when a Normal FIFO TX
+                                                     at a scheduled TX time error is occurred. This error could
+                                                     be caused by an invalid TX time or CCA failure. Write 1
+                                                     clear.                                                                    */
+__IOM uint32_t rxelyif    :
+            1;            /*!< [4..4] RX eraly Interrupt status: 0: (default)no RX eraly interrupt
+                                                     occurred; 1: the RX eraly interrupt is occurred. RX early
+                                                     interrupt is triggered when on the receiving of an incoming
+                                                     frame and its MAC header and Secure AUX Header (if present)
+                                                     are received complete and pass the RX filter check. Write
+                                                     1 clear.                                                                  */
+__IOM uint32_t secif      :
+            1;            /*!< [5..5] Security Key Request Interrupt: 0: (default) No security
+                                                     key request interrupt occurred; 1: A security key request
+                                                     interrupt occurred, Write 1 clear                                         */
+__IOM uint32_t rxif       :
+            1;            /*!< [6..6] RX FIFO Reception Interrupt: 0: (default) No RX FIFO
+                                                     reception interrupt occurred; 1: An RX FIFO reception interrupt
+                                                     occurred, Write 1 clear                                                   */
+__IOM uint32_t mactmrif   :
+            1;            /*!< [7..7] MAC timer Interrupt: 0: (default) No MAC timer interrupt
+                                                     occurred; 1: A MAC timer interrupt occurred, Write 1 clear                */
+__IOM uint32_t btcmp0if   :
+            1;            /*!< [8..8] BT-MAC timer 0 Interrupt status: 0: (default) no BT-MAC
+                                                     timer interrupt occurred; 1: the BT-MAC timer interrupt
+                                                     is occurred. BT-MAC timer interrupt is triggered when the
+                                                     counter value of the free run BT-MAC timer is matched with
+                                                     the BT-MAC timer comparator value. Write 1 clear.                         */
+__IOM uint32_t btcmp1if   :
+            1;            /*!< [9..9] BT-MAC timer 1 Interrupt status: 0: (default) no BT-MAC
+                                                     timer interrupt occurred; 1: the BT-MAC timer interrupt
+                                                     is occurred. BT-MAC timer interrupt is triggered when the
+                                                     counter value of the free run BT-MAC timer is matched with
+                                                     the BT-MAC timer comparator value. Write 1 clear.                         */
+__IOM uint32_t gntif      :
+            1;            /*!< [10..10] PHY grant update Interrupt status: 0: no PHY grant
+                                                     update interrupt is occurred; 1: PHY grant update interrupt
+                                                     is occurred. PHY grant update interrupt is triggered when
+                                                     the PHY grant request success or failed, or PHY grant is
+                                                     de-asserted by Arbitration Coordinator.                                   */
+__IOM uint32_t edscanif   :
+            1;            /*!< [11..11] ED scan done Interrupt status: 0: no ED scan done interrupt
+                                                     occurred; 1: the ED scan done interrupt is occurred ED
+                                                     scan done interrupt is triggered when an ED scan procedure
+                                                     is done                                                                   */
+__IOM uint32_t sfstartif  :
+            1;            /*!< [12..12] Slotted enable Superframe start Interrupt status: 0:
+                                                     no superframe start interrupt is pending; 1: the superframe
+                                                     start interrupt is occurred and pending                                   */
+__IOM uint32_t sfendif    :
+            1;            /*!< [13..13] Slotted enable Superframe end Interrupt status: 0:
+                                                     no superframe end interrupt is pending; 1: the superframe
+                                                     end interrupt is occurred and pending                                     */
+__IOM uint32_t btcmp2if   :
+            1;            /*!< [14..14] BT-MAC timer 2 Interrupt status: 0: (default) no BT-MAC
+                                                     timer interrupt occurred; 1: the BT-MAC timer interrupt
+                                                     is occurred. BT-MAC timer interrupt is triggered when the
+                                                     counter value of the free run BT-MAC timer is matched with
+                                                     the BT-MAC timer comparator value. Write 1 clear.                         */
+__IOM uint32_t btcmp3if   :
+            1;            /*!< [15..15] BT-MAC timer 3 Interrupt status: 0: (default) no BT-MAC
+                                                     timer interrupt occurred; 1: the BT-MAC timer interrupt
+                                                     is occurred. BT-MAC timer interrupt is triggered when the
+                                                     counter value of the free run BT-MAC timer is matched with
+                                                     the BT-MAC timer comparator value. Write 1 clear.                         */
+            uint32_t            : 16;
+        } isrsts_b;
+    } ;
+
+    union
+    {
+        __IOM uint32_t
+        bt_clk_cmp0;                 /*!< (@ 0x00000028) BT Clock Comparator 0 Register                             */
+
+        struct
+        {
+__IOM uint32_t bt_ckc     :
+            10;           /*!< [9..0] The clock counter value of the BT-MAC timer comparator.When
+                                                     the (BT NativeClock[22:1] || ClockCounter[9:0]) timer value
+                                                     is matched with (bt_nclk || bt_ckc) then trigger the BT-MAC
+                                                     timer comparator0 interrupt.                                              */
+__IOM uint32_t bt_nclk    :
+            22;           /*!< [31..10] The native clock value of the BT-MAC timer comparator.
+                                                     When the (BT NativeClock[22:1] || ClockCounter[9:0]) value
+                                                     is matched with (bt_nclk || bt_ckc) then trigger the BT-MAC
+                                                     timer comparator interrupt.                                               */
+        } bt_clk_cmp0_b;
+    } ;
+
+    union
+    {
+        __IOM uint32_t
+        bt_clk_cmp1;                 /*!< (@ 0x0000002C) BT Clock Comparator 1 Register                             */
+
+        struct
+        {
+__IOM uint32_t bt_ckc     :
+            10;           /*!< [9..0] The clock counter value of the BT-MAC timer comparator.When
+                                                     the (BT NativeClock[22:1] || ClockCounter[9:0]) timer value
+                                                     is matched with (bt_nclk || bt_ckc) then trigger the BT-MAC
+                                                     timer comparator1 interrupt.                                              */
+__IOM uint32_t bt_nclk    :
+            22;           /*!< [31..10] The native clock value of the BT-MAC timer comparator.
+                                                     When the (BT NativeClock[22:1] || ClockCounter[9:0]) value
+                                                     is matched with (bt_nclk || bt_ckc) then trigger the BT-MAC
+                                                     timer comparator interrupt.                                               */
+        } bt_clk_cmp1_b;
+    } ;
+
+    union
+    {
+        __IOM uint32_t
+        bt_clk_cmp2;                 /*!< (@ 0x00000030) BT Clock Comparator 2 Register                             */
+
+        struct
+        {
+__IOM uint32_t bt_ckc     :
+            10;           /*!< [9..0] The clock counter value of the BT-MAC timer comparator.When
+                                                     the (BT NativeClock[22:1] || ClockCounter[9:0]) timer value
+                                                     is matched with (bt_nclk || bt_ckc) then trigger the BT-MAC
+                                                     timer comparator2 interrupt.                                              */
+__IOM uint32_t bt_nclk    :
+            22;           /*!< [31..10] The native clock value of the BT-MAC timer comparator.
+                                                     When the (BT NativeClock[22:1] || ClockCounter[9:0]) value
+                                                     is matched with (bt_nclk || bt_ckc) then trigger the BT-MAC
+                                                     timer comparator interrupt.                                               */
+        } bt_clk_cmp2_b;
+    } ;
+
+    union
+    {
+        __IOM uint32_t
+        bt_clk_cmp3;                 /*!< (@ 0x00000034) BT Clock Comparator 3 Register                             */
+
+        struct
+        {
+__IOM uint32_t bt_ckc     :
+            10;           /*!< [9..0] The clock counter value of the BT-MAC timer comparator.When
+                                                     the (BT NativeClock[22:1] || ClockCounter[9:0]) timer value
+                                                     is matched with (bt_nclk || bt_ckc) then trigger the BT-MAC
+                                                     timer comparator3 interrupt.                                              */
+__IOM uint32_t bt_nclk    :
+            22;           /*!< [31..10] The native clock value of the BT-MAC timer comparator.
+                                                     When the (BT NativeClock[22:1] || ClockCounter[9:0]) value
+                                                     is matched with (bt_nclk || bt_ckc) then trigger the BT-MAC
+                                                     timer comparator interrupt.                                               */
+        } bt_clk_cmp3_b;
+    } ;
+
+    union
+    {
+        __IOM uint32_t
+        ed_scan_ctrl0;               /*!< (@ 0x00000038) ED Scan Control Register 0                                 */
+
+        struct
+        {
+__IOM uint32_t scan_enable :
+            1;           /*!< [0..0] write this bit to start or stop ED scan procedure: 1:
+                                                     trigger the ED scan start; 0: cancel a running ED scan;
+                                                     HW will clear this bit when ED scan procedure is done.
+                                                     The ED scan status is updated in bits[29:26] and ED level
+                                                     is updated in peak_value (bits[21:14])                                    */
+__IOM uint32_t scan_round :
+            13;           /*!< [13..1] set the round of symbols (default 8 symbols) ED scan
+                                                     to run for a whole ED scan procedure. Scan round = ed_scan_round
+                                                     + 1, ed_scan_round valid value is 0 ~ 8191.                               */
+__IM  uint32_t peak_value :
+            8;            /*!< [21..14] keep the peak value of ED scan result                            */
+__IOM uint32_t scan_symbol :
+            4;           /*!< [25..22] number of symbol for a round of ED scan, default a
+                                                     round scan 8 symbols                                                      */
+__IM  uint32_t ed_scan_encounter_tx_trig_sts :
+            1;/*!< [26..26] indicates ED scan is canceled due to conflict with
+                                                     TX trigger.                                                               */
+__IM  uint32_t scan_fw_cancel_sts :
+            1;    /*!< [27..27] indicates the ED scan procedure is finished due to
+                                                     FW cancel                                                                 */
+__IM  uint32_t scan_gnt_deassert_sts :
+            1; /*!< [28..28] indicates the ED scan procedure is finished due to
+                                                     PHY grant is de-asserted                                                  */
+__IM  uint32_t scan_ed_vld_tmo_sts :
+            1;   /*!< [29..29] indicates the ED scan procedure is finished due to
+                                                     wait PHY report valid timeout                                             */
+__IM  uint32_t scan_finish_sts :
+            1;       /*!< [30..30] ed scan finish status:1: ED scan is finished normally            */
+__IOM uint32_t scan_done  :
+            1;            /*!< [31..31] MAC HW set this bit to indicates current ED scan is
+                                                     done. Once this bit is set, bits [30:27] indicates the
+                                                     ED scan status. This bit is cleaned by write 1.                           */
+        } ed_scan_ctrl0_b;
+    } ;
+
+    union
+    {
+        __IOM uint32_t
+        ed_scan_ctrl1;               /*!< (@ 0x0000003C) ED Scan Control Register 1                                 */
+
+        struct
+        {
+__IM  uint32_t scan_cnt   :
+            14;           /*!< [13..0] indicates how many round of ED symbols scan has ran               */
+__IOM uint32_t scan_vld_tmo_cnt_limit :
+            6;/*!< [19..14] set the timeout for PHY scan report valid waitting.
+                                                     Unit is 1T (0.05us for 20MHz)                                             */
+__IOM uint32_t scan_first_ed_scan_symbol :
+            4;/*!< [23..20] Timing adjustment before of the 1st round of ED symbols
+                                                     scan. Unit is symbol. Timing adjustment = symbol + cnt.                   */
+__IOM uint32_t scan_first_ed_scan_cnt :
+            8;/*!< [31..24] Timing adjustment before of the 1st round of ED symbols
+                                                     scan. Unit is 1 clock (0.05us for 20MHz).                                 */
+        } ed_scan_ctrl1_b;
+    } ;
+
+    union
+    {
+        __IM  uint32_t
+        ed_scan_dbg;                 /*!< (@ 0x00000040) ED Scan Status Register for Debugging                      */
+
+        struct
+        {
+__IM  uint32_t ed_scan_cst :
+            4;           /*!< [3..0] ED scan current state for debugging.                               */
+            uint32_t            : 28;
+        } ed_scan_dbg_b;
+    } ;
+
+    union
+    {
+        __IOM uint32_t
+        phy_arb_ctrl;                /*!< (@ 0x00000044) PHY Arbitration Control Register                           */
+
+        struct
+        {
+__IOM uint32_t fw_active_entry :
+            1;       /*!< [0..0] this bit is controlled by FW to indicates whether the
+                                                     MAC FW intend to use PHY and active the meu_zb_fsm HW to
+                                                     issue PHY request: 1: FW intend to use PHY for RX/TX, active
+                                                     the men_zb_fsm to request PHY; 0: FW write 0 to this bit
+                                                     when it no need to use PHY (ex. entering sleep mode), the
+                                                     men_zb_fsm will issue 'term' signal to Arbitration Coordinator.           */
+__IOM uint32_t zb_only    :
+            1;            /*!< [1..1] to control whether to disable ZB MAC PHY grant mechanism
+                                                     and MAC assume that it always own the PHY: 0: PHY is shared
+                                                     by multiple protocol (BLE/ZB concurrent); 1: PHY is used
+                                                     by ZB MAC only, no concurrent multiple protocol                           */
+__IOM uint32_t anchor_point :
+            18;         /*!< [19..2] the anchor point (in unit of slot, 625us) for PHY grant
+                                                     request.                                                                  */
+__IOM uint32_t anch_pt_jump_value :
+            4;    /*!< [23..20] the anchor point jump value (in unit of slot, 625us)
+                                                     for auto PHY request. HW will auto retry the PHY grant
+                                                     request with current BT slot + anch_pt_jump_value                         */
+__IM  uint32_t zbrf_gnt_deassert_sts :
+            1; /*!< [24..24] Indicates the status of PHY grant for ZB MAC: 1: MAC
+                                                     lost the PHY grant. This is caused by PHY is granted to
+                                                     BLE or FW set the fw_active_entry to low and HW has sent
+                                                     term signal to Arbitration Coordinator; 0: MAC still own
+                                                     the PHY grant.                                                            */
+__IM  uint32_t zbrf_gnt_fail_sts :
+            1;     /*!< [25..25] Indicates the PHY grant request execution result: 1:
+                                                     PHY is not granted at the assigned anchor point(BT Clock);
+                                                     0: PHY grant successfully                                                 */
+__IM  uint32_t zbrf_gnt_sts :
+            1;          /*!< [26..26] Indicates the PHY grant status when the grant interrupt
+                                                     is asserted: 1: PHY is granted; 0: PHY is not granted (grant
+                                                     failed or lost PHY grant)                                                 */
+            uint32_t            : 5;
+        } phy_arb_ctrl_b;
+    } ;
+
+    union
+    {
+        __IM  uint32_t
+        phy_arb_status;              /*!< (@ 0x00000048) PHY Arbitration Status Register                            */
+
+        struct
+        {
+__IM  uint32_t zbrf_meu_cs :
+            2;           /*!< [1..0] current state of men_zb_fsm, for debugging                         */
+__IM  uint32_t zbrf_meu_anchor_point :
+            18;/*!< [19..2] the current anchor point of meu_zb_fsm requesting PHY
+                                                     grant                                                                     */
+            uint32_t            : 12;
+        } phy_arb_status_b;
+    } ;
+
+    union
+    {
+        __IOM uint32_t
+        bt_clk_latch_ctrl;           /*!< (@ 0x0000004C) BT Clock Latch Control Register                            */
+
+        struct
+        {
+__IM  uint32_t bt_timer_native_h :
+            5;     /*!< [4..0] latched BT native clock value bits[27:23]                          */
+            uint32_t            : 26;
+__IOM uint32_t bt_timer_latch :
+            1;        /*!< [31..31] Write 1 to this bit will trigger the MAC HW to latch
+                                                     BT free run timer(BT native clock and clock counter) value
+                                                     and store them in BT_CLK_LATCH register. HW will auto-clear
+                                                     this bit when BT timer value latch is done.                               */
+        } bt_clk_latch_ctrl_b;
+    } ;
+
+    union
+    {
+        __IM  uint32_t
+        bt_clk_latch;                /*!< (@ 0x00000050) BT Clock Latch Value                                       */
+
+        struct
+        {
+__IM  uint32_t bt_timer_cgn :
+            10;         /*!< [9..0] latched BT clock counter value                                     */
+__IM  uint32_t bt_timer_native :
+            22;      /*!< [31..10] latched BT native clock value bits[22:1]                         */
+        } bt_clk_latch_b;
+    } ;
+
+    union
+    {
+        __IM  uint32_t
+        mac_version;                 /*!< (@ 0x00000054) MAC HW Version Number                                      */
+
+        struct
+        {
+__IM  uint32_t version    :
+            32;           /*!< [31..0] MAC HW version number                                             */
+        } mac_version_b;
+    } ;
+
+    union
+    {
+        __IM  uint32_t
+        rssi;                        /*!< (@ 0x00000058) Base Band RSSI Value Register                              */
+
+        struct
+        {
+__IM  uint32_t rssi       :
+            16;           /*!< [15..0] The BB RSSI value                                                 */
+            uint32_t            : 16;
+        } rssi_b;
+    } ;
+
+    union
+    {
+        __IM  uint32_t
+        tx_term_sts;                 /*!< (@ 0x0000005C) TX Termed (Lost PHY Grant) Status Register                 */
+
+        struct
+        {
+__IM  uint32_t zbrf_gts2_tx_termed :
+            1;   /*!< [0..0] to indicates the GTS2 FIFO TX is finished due to PHY
+                                                     grant is terminated (PHY is granted to BLE)                               */
+__IM  uint32_t zbrf_gts1_tx_termed :
+            1;   /*!< [1..1] to indicates the GTS1 FIFO TX is finished due to PHY
+                                                     grant is terminated (PHY is granted to BLE) or due to the
+                                                     header length is 0 for a secure TX                                        */
+__IM  uint32_t zbrf_normal_tx_termed :
+            1; /*!< [2..2] to indicates the Normal FIFO TX is finished due to PHY
+                                                     grant is terminated (PHY is granted to BLE) or due to the
+                                                     header length is 0 for a secure TX                                        */
+__IM  uint32_t zbrf_beacon_tx_termed :
+            1; /*!< [3..3] to indicates the Beacon FIFO TX is finished due to PHY
+                                                     grant is terminated (PHY is granted to BLE)                               */
+            uint32_t            : 28;
+        } tx_term_sts_b;
+    } ;
+
+    union
+    {
+        __IOM uint32_t
+        rfctl;                       /*!< (@ 0x00000060) RF Mode Control Register                                   */
+
+        struct
+        {
+__IOM uint32_t rfrxmode   :
+            1;            /*!< [0..0] Force RX Mode: 0: (default) Normal operation of RX mode;
+                                                     1: RF state machine is forced to RX mode;                                 */
+__IOM uint32_t rftxmode   :
+            1;            /*!< [1..1] Force TX Mode: 0: (default) Normal operation of TX mode;
+                                                     1: RF state machine is forced to TX mode;                                 */
+__IOM uint32_t rfrst      :
+            1;            /*!< [2..2] RF State Machine Reset: 0: Normal operation of RF state
+                                                     machine; 1: (default) Hold RF state machine in Reset;                     */
+            uint32_t            : 29;
+        } rfctl_b;
+    } ;
+
+    union
+    {
+        __IOM uint32_t
+        wakeup_remaincnt;            /*!< (@ 0x00000064) Wakeup Remain Counter Register                             */
+
+        struct
+        {
+__IOM uint32_t remcnt     :
+            16;           /*!< [15..0] In the system wakeup procedure, the Remain Counter to
+                                                     wait to switch to high speed clock                                        */
+__IOM uint32_t wakecnt    :
+            9;            /*!< [24..16] System Clock Recovery Time. The time to wait system
+                                                     resume from sleep.                                                        */
+            uint32_t            : 7;
+        } wakeup_remaincnt_b;
+    } ;
+
+    union
+    {
+        __IOM uint32_t
+        wakeup_maincnt;              /*!< (@ 0x00000068) Wakeup Main Counter Control Register                       */
+
+        struct
+        {
+__IOM uint32_t maincnt    :
+            26;           /*!< [25..0] Main Counter. Main counter is a 26-bit counter for sleep
+                                                     time counting. Units: Sleep Clock Period                                  */
+__OM  uint32_t startcnt   :
+            1;            /*!< [26..26] Start Sleep Counters. 1 = Trigger sleep for Non-beacon
+                                                     mode (BO = 0b1111 and Slotted = 0b0). Bit is automatically
+                                                     cleared to '0' by hardware                                                */
+__IOM uint32_t regwake    :
+            1;            /*!< [27..27] Register Triggered Wake-up Signal: 1: To wake up MAC.
+                                                     Bit is automatically cleared to '0' by hardware.                          */
+__IOM uint32_t immwake    :
+            1;            /*!< [28..28] Immediate Wake-up Mode Enable: 0: (default) Disable
+                                                     Immediate Wake-up mode; 1: Enable Immediate Wake-up mode                  */
+            uint32_t            : 2;
+__OM  uint32_t slpack     :
+            1;            /*!< [31..31] Sleep Acknowledgement. Place the MAC to Power Saving
+                                                     Mode. Bit is automatically cleared to '0' by hardware                     */
+        } wakeup_maincnt_b;
+    } ;
+
+    union
+    {
+        __IOM uint32_t
+        wakeup_waketime;             /*!< (@ 0x0000006C) Wakeup Time Match Register                                 */
+
+        struct
+        {
+__IOM uint32_t waketime   :
+            11;           /*!< [10..0] Wake Time Match Value: WAKETIME is an 11-bit value.
+                                                     In sleep mode, when the Main Counter is down counting to
+                                                     the value of WAKETIME, the 32 MHz main oscillator will
+                                                     start to be recovered. Note that the value of WAKETIME
+                                                     has to be greater than that of WAKECNT.                                   */
+            uint32_t            : 21;
+        } wakeup_waketime_b;
+    } ;
+    __IM  uint32_t  RESERVED[8];
+
+    union
+    {
+        __IOM uint32_t
+        dbgport_sel;                 /*!< (@ 0x00000090) TX/RX Machine Debug Port Selection Control Register        */
+
+        struct
+        {
+__IOM uint32_t gr_dbg_sel_o :
+            4;          /*!< [3..0] Debug Port mux sel: 0: zb_rf_debug_out; 1: txm_fc_debug_out;
+                                                     2: rxm_debug_out; 3: src_debug_out; 4: secure; 5: TXM CSMA;
+                                                     6: reserved; 7: short register; 8: txm_gts; 9 ~ 15 : Reserved             */
+__IOM uint32_t gr_dbg_rxm_sel_o :
+            1;      /*!< [4..4] Debug Rxm mux sel, 0: dbg_rxm_fifo; 1: dbg_rxm_fsm                 */
+__IOM uint32_t gr_dbg_cnt_reset_o :
+            1;    /*!< [5..5] FW can write 1 this bit to reset all debug counter as
+                                                     0. HW will automatically clear this bit.                                  */
+__IOM uint32_t gr_dbg_src_sel_o :
+            1;      /*!< [6..6] Debug Src Match filter mux sel: 0: dbg_src_ctrl; 1: dbg_src_entry  */
+            uint32_t            : 25;
+        } dbgport_sel_b;
+    } ;
+
+    union
+    {
+        __IM  uint32_t
+        dbg_reg0;                    /*!< (@ 0x00000094) Debug Register 0                                           */
+
+        struct
+        {
+            uint32_t            : 8;
+__IM  uint32_t sh_back    :
+            8;            /*!< [15..8] the backoff random number of TXM. FW can get pseudo
+                                                     random number from this register for a SW level TX backoff
+                                                     or key generation.                                                        */
+__IM  uint32_t dbg_rxm_frm_end_cnt :
+            16;  /*!< [31..16] number of times a Frame end occurs for debugging                 */
+        } dbg_reg0_b;
+    } ;
+
+    union
+    {
+        __IM  uint32_t
+        rxm_dbg;                     /*!< (@ 0x00000098) RXM Debug Register                                         */
+
+        struct
+        {
+__IM  uint32_t dbg_crc_ok_cnt :
+            16;       /*!< [15..0] number of times of received frame with CRC OK occurs
+                                                     for debugging                                                             */
+__IM  uint32_t dbg_discard_cnt :
+            16;      /*!< [31..16] number of times of receiving pkt discarded occurs for
+                                                     debugging                                                                 */
+        } rxm_dbg_b;
+    } ;
+    __IM  uint32_t  RESERVED1[153];
+
+    union
+    {
+        __IOM uint8_t
+        sf_order_ctrl;                /*!< (@ 0x00000300) Superframe Order Control Register                          */
+
+        struct
+        {
+__IOM uint8_t so          :
+            4;            /*!< [3..0] Superframe Order (macSuperframeOrder), Specifies the
+                                                     length of the active portion of the superframe, including
+                                                     the beacon frame: 0000: 0;  ... 1110: 14; 1111: (default);
+                                                     The superframe will not be active following the beacon.
+                                                     (i.e., no active portion in the superframe)                               */
+__IOM uint8_t bo          :
+            4;            /*!< [7..4] Beacon Order (macBeaconOrder), Specifies how often the
+                                                     coordinator will transmit a beacon: 0000: 0;  ... 1110:
+                                                     14; 1111: (default) The coordinator will not transmit a
+                                                     beacon and the Superframe Order (SO)                                      */
+        } sf_order_ctrl_b;
+    } ;
+
+    union
+    {
+        __IOM uint8_t
+        min_lifs;                     /*!< (@ 0x00000301) Minimum LIFS Configuration Register                        */
+
+        struct
+        {
+__IOM uint8_t milp        :
+            6;            /*!< [5..0] aMinLIFSPeriod, 40 symbols, need to take care txpe turn
+                                                     on period (max. 7 symbols). For unslotted CSMA-CA and GTS
+                                                     to guarantee IFS period.                                                  */
+            uint8_t             : 2;
+        } min_lifs_b;
+    } ;
+
+    union
+    {
+        __IOM uint16_t
+        ifs_ctrl;                    /*!< (@ 0x00000302) Inter Frame Space Control Register                         */
+
+        struct
+        {
+__IOM uint16_t misp       :
+            4;            /*!< [3..0] Minimum Short Interframe Spacing: 0101: (default - Do
+                                                     Not Change)                                                               */
+__IOM uint16_t txpet      :
+            4;            /*!< [7..4] VCO Settling Time: 0101: (default - Do Not Change);                */
+__IOM uint16_t ccachkp    :
+            4;            /*!< [11..8] The time for CCA check point Ccachkp 0x8 is recommended           */
+__IOM uint16_t aturn      :
+            4;            /*!< [15..12] ACK turnaround time after receiving a packet. Minimum
+                                                     value is 0x2. In unit of 16us (a symbol time)                             */
+        } ifs_ctrl_b;
+    } ;
+
+    union
+    {
+        __IOM uint32_t
+        tx_ctrl;                     /*!< (@ 0x00000304) TX Control Register                                        */
+
+        struct
+        {
+            uint32_t            : 16;
+__IOM uint32_t pend       :
+            1;            /*!< [16..16] Pending bit in ACK header                                        */
+__IOM uint32_t indirect   :
+            1;            /*!< [17..17] Activate Indirect Transmission bit (coordinator only):
+                                                     0: (default) Indirect transmission disabled; 1: Indirect
+                                                     transmission enabled                                                      */
+            uint32_t            : 6;
+__IOM uint32_t mawd       :
+            7;            /*!< [30..24] The maximum number of symbols to wait for an acknowledgment
+                                                     frame to arrive following a transmitted data frame. This
+                                                     value is dependent on the currently selected logical channel
+                                                     For 0 <= phyCurrentChannel <= 10, this value is equal to
+                                                     120. For 11 <= phyCurrentChannel <= 26, this value is equal
+                                                     to 54.Consider the timing align issue, suggest use 0x39                   */
+            uint32_t            : 1;
+        } tx_ctrl_b;
+    } ;
+
+    union
+    {
+        __IOM uint32_t
+        beacon_ctrl;                 /*!< (@ 0x00000308) Beacon Control Register                                    */
+
+        struct
+        {
+__IOM uint32_t intl       :
+            6;            /*!< [5..0] Interval to Start Beacon: The timing interval between
+                                                     slotted mode triggered (set by REG0x300[7:4]) and the first
+                                                     time to send beacon frame: 000000: 0 (default); 000011:
+                                                     3 (optimized - Do Not Change); in unit of symbol time                     */
+            uint32_t            : 10;
+__IOM uint32_t aoffset    :
+            8;            /*!< [23..16] Offset to Align Beacon Boundary. Superframe counter
+                                                     offset to align with beacon boundary. Alignment will happen
+                                                     whenever a beacon is received. Only for device mode: 00000000:
+                                                     (default); 00010101: (optimized - Do Not Change) in unit
+                                                     of symbol time                                                            */
+            uint32_t            : 8;
+        } beacon_ctrl_b;
+    } ;
+
+    union
+    {
+        __IM  uint32_t
+        txm_state;                   /*!< (@ 0x0000030C) TX State Machine Status Register                           */
+
+        struct
+        {
+__IM  uint32_t txm_mac_state :
+            5;         /*!< [4..0] txm_mac_state: MAC state machine for debug use                     */
+__IM  uint32_t txm_busn_state :
+            2;        /*!< [6..5] Normal packet fifo bus state for debug use                         */
+__IM  uint32_t txm_busb_state :
+            2;        /*!< [8..7] Beacon fifo bus state for debug use                                */
+__IM  uint32_t txm_busg1_state :
+            2;       /*!< [10..9] GTS fifo1 bus state for debug use                                 */
+__IM  uint32_t txm_busg2_state :
+            2;       /*!< [12..11] GTS fifo2 bus state for debug use                                */
+__IM  uint32_t cfp_state  :
+            3;            /*!< [15..13] GTS state in CFP for debug use                                   */
+__IM  uint32_t csma_state :
+            5;            /*!< [20..16] TXM CSMA state for debug use                                     */
+__IM  uint32_t sf_state   :
+            3;            /*!< [23..21] superframe structure state for debug use                         */
+__IM  uint32_t rf_mode_state :
+            4;         /*!< [27..24] RF mode state for debug use                                      */
+__IM  uint32_t gts_state  :
+            4;            /*!< [31..28] GTS state machine for debug use                                  */
+        } txm_state_b;
+    } ;
+
+    union
+    {
+        __IOM uint8_t
+        txb_trig;                     /*!< (@ 0x00000310) Beacon TX FIFO Trigger Control Register                    */
+
+        struct
+        {
+__IOM uint8_t txbcntrig   :
+            1;            /*!< [0..0] Transmit Frame in TX Beacon FIFO bit: 1: Transmit the
+                                                     frame in the TX Beacon FIFO; bit is automatically cleared
+                                                     by hardware.                                                              */
+__IOM uint8_t txbsecen    :
+            1;            /*!< [1..1] TX Beacon FIFO Security Enabled bit: 0: (default) Security
+                                                     disabled; 1: Security enabled                                             */
+            uint8_t             : 6;
+        } txb_trig_b;
+    } ;
+
+    union
+    {
+        __IOM uint8_t
+        txn_trig;                     /*!< (@ 0x00000311) Normal TX FIFO Trigger Control Register                    */
+
+        struct
+        {
+__IOM uint8_t txntrig     :
+            1;            /*!< [0..0] Transmit Frame in TX Normal FIFO bit: 1: Transmit the
+                                                     frame in the TX Normal FIFO. Bit is automatically cleared
+                                                     to '0' by hardware.                                                       */
+__IOM uint8_t txnsecen    :
+            1;            /*!< [1..1] TX Normal FIFO Security Enabled bit: 0: (default) Security
+                                                     disabled; 1: Security enabled;                                            */
+__IOM uint8_t txnackreq   :
+            1;            /*!< [2..2] TX Normal FIFO Acknowledgement Request bit. Transmit
+                                                     a packet with Acknowledgement request. If Acknowledgement
+                                                     is not received, theMAC HW retransmits up to TXNFRMTRY
+                                                     times: 0: (default) No Acknowledgement packet requested;
+                                                     1: Acknowledgement packet requested                                       */
+__IOM uint8_t ack_type    :
+            1;            /*!< [3..3] the ACK frame version for the TXM should wait: 0: (default)
+                                                     Imm-Ack; 1: Enh-Ack; The firmware should according to the
+                                                     frame version of the frame is going to be transmitted to
+                                                     fill this bit's value                                                     */
+            uint8_t             : 1;
+__IOM uint8_t txnfrmtry   :
+            3;            /*!< [7..5] normal fifo max retry times                                        */
+        } txn_trig_b;
+    } ;
+
+    union
+    {
+        __IOM uint8_t
+        txg1_trig;                    /*!< (@ 0x00000312) GTS1 TX FIFO Trigger Control Register                      */
+
+        struct
+        {
+__IOM uint8_t txg1trig    :
+            1;            /*!< [0..0] Transmit Frame in TX GTS1 FIFO: 1: Transmit the frame
+                                                     in the TX GTS1 FIFO. Bit is automatically cleared to '0'
+                                                     by hardware                                                               */
+__IOM uint8_t txg1secen   :
+            1;            /*!< [1..1] TX GTS1 FIFO Security Enabled: 0: (default) Security
+                                                     disabled; 1: Security enabled                                             */
+__IOM uint8_t txg1ackreq  :
+            1;            /*!< [2..2] TX GTS1 FIFO Acknowledgement Request. Transmit a packet
+                                                     with Acknowledgement request. If Acknowledgement is not
+                                                     received, theMAC HW retransmits up to the times set by
+                                                     txg1ifetry(Reg 0x312[7:6]): 0: (default) Acknowledgement
+                                                     Request disabled; 1: Acknowledgement Request enabled                      */
+__IOM uint8_t txg1slot    :
+            3;            /*!< [5..3] GTS Slot that GTS1 FIFO Occupies: 000: 0 (default);
+                                                     ... 111: 7                                                                */
+__IOM uint8_t txg1ifetry  :
+            2;            /*!< [7..6] GTS1 FIFO Retry Times. Set the limit of retry times of
+                                                     the packet: 00: 0;  ... 11: 3 (default)                                   */
+        } txg1_trig_b;
+    } ;
+
+    union
+    {
+        __IOM uint8_t
+        txg2_trig;                    /*!< (@ 0x00000313) GTS2 TX FIFO Trigger Control Register                      */
+
+        struct
+        {
+__IOM uint8_t txg2trig    :
+            1;            /*!< [0..0] Transmit Frame in TX GTS2 FIFO: 1: Transmit the frame
+                                                     in the TX GTS2 FIFO. Bit is automatically cleared to '0'
+                                                     by hardware                                                               */
+__IOM uint8_t txg2secen   :
+            1;            /*!< [1..1] TX GTS2 FIFO Security Enabled: 0: (default) Security
+                                                     disabled; 1: Security enabled;                                            */
+__IOM uint8_t txg2ackreq  :
+            1;            /*!< [2..2] TX GTS2 FIFO Acknowledgement Request. Transmit a packet
+                                                     with Acknowledgement request. If Acknowledgement is not
+                                                     received, the MAC HW retransmits up to the times set by
+                                                     txg2ifetry (Reg 0x313[7:6]) 0: (default) Acknowledgement
+                                                     Request disabled; 1: Acknowledgement Request enabled;                     */
+__IOM uint8_t txg2slot    :
+            3;            /*!< [5..3] GTS Slot that GTS2 FIFO Occupies: 000: 0 (default);
+                                                     ... 111: 7                                                                */
+__IOM uint8_t txg2ifetry  :
+            2;            /*!< [7..6] GTS2 FIFO Retry Times. Set the limit of retry times of
+                                                     the packet: 00: 0;  ... 11: 3 (default)                                   */
+        } txg2_trig_b;
+    } ;
+
+    union
+    {
+        __IM  uint32_t
+        txm_status;                  /*!< (@ 0x00000314) TX Machine Status Register                                 */
+
+        struct
+        {
+__IM  uint32_t sfcntr     :
+            24;           /*!< [23..0] Superframe counter value                                          */
+__IM  uint32_t txg1retryn :
+            2;            /*!< [25..24] The number of retry times of the latest successfully
+                                                     transmitted packet on GTS1 FIFO.                                          */
+__IM  uint32_t txg2retryn :
+            2;            /*!< [27..26] The number of retry times of the latest successfully
+                                                     transmitted packet on GTS2 FIFO.                                          */
+__IM  uint32_t pendack    :
+            1;            /*!< [28..28] Frame Pending Status bit. Status of the frame pending
+                                                     bit in the received Acknowledgement frame: 0: (default)
+                                                     Frame pending bit = 0; 1: Frame pending bit = 1                           */
+            uint32_t            : 3;
+        } txm_status_b;
+    } ;
+
+    union
+    {
+        __IOM uint32_t
+        gts_ctrl;                    /*!< (@ 0x00000318) GTS FIFO TX Control Register                               */
+
+        struct
+        {
+__IOM uint32_t enh_ack_trig :
+            1;          /*!< [0..0] Enh-Ack TX trigger. FW set this bit to trigger the Enh-Ack
+                                                     frame which is prepared in the GTS1 TX FIFO. MAC HW will
+                                                     start the Enh-Ack frame transmission at the time of rxif
+                                                     + gts_enh_ack_timer + rx2tx_enh_ack_delay. To prevent the
+                                                     FW set this bit too late or at inproper time, this bit
+                                                     is available to write only in the time window from rxif
+                                                     to (rxif + gts_enh_ack_timer)                                             */
+__IOM uint32_t sec_enh_ack :
+            1;           /*!< [1..1] enable the encryption of Enh-Ack frame. The value of
+                                                     this bit will be copied to txg1secen when the Enh-Ack frame
+                                                     (GTS1) TX is triggered.                                                   */
+__IOM uint32_t gtsswitch  :
+            1;            /*!< [2..2] Continue TX GTS FIFO Switch: 0: (default) GTS1 and GTS2
+                                                     FIFO will stop toggling with each other if the transmission
+                                                     fails; 1: GTS1 and GTS2 FIFO will toggle with each other                  */
+__IOM uint32_t nocsmag    :
+            1;            /*!< [3..3] Carrier Sense Multiple Access with Collision Avoidance
+                                                     (CSMA-CA) for TX GTS FIFO: 0: (default) Enable CSMA-CA
+                                                     for TX GTS FIFO; 1: Disable CSMA-CA for TX GTS FIFO;                      */
+__IOM uint32_t cap        :
+            4;            /*!< [7..4] End Slot of Contention Access Period (CAP): 0000: 0 (default);
+                                                     ... 1111: 15                                                              */
+__IOM uint32_t gts1       :
+            4;            /*!< [11..8] End Slot of 1st GTS: 0000: 0 (default);  ... 1111: 15             */
+__IOM uint32_t gts2       :
+            4;            /*!< [15..12] End Slot of 2nd GTS: 0000: 0 (default);  ... 1111:
+                                                     15;                                                                       */
+__IOM uint32_t gts3       :
+            4;            /*!< [19..16] End Slot of 3rd GTS: 0000: 0 (default) ;  ... 1111:
+                                                     15;                                                                       */
+__IOM uint32_t gts4       :
+            4;            /*!< [23..20] End Slot of 4th GTS: 0000: 0 (default);  ... 1111:
+                                                     15;                                                                       */
+__IOM uint32_t gts5       :
+            4;            /*!< [27..24] End Slot of 5th GTS: 0000: 0 (default);  ... 1111:
+                                                     15;                                                                       */
+__IOM uint32_t gts6       :
+            4;            /*!< [31..28] End Slot of 6th GTS: 0000: 0 (default);  ... 1111:
+                                                     15; If 7th GTS exists, the end slot must be 15.                           */
+        } gts_ctrl_b;
+    } ;
+
+    union
+    {
+        __IOM uint32_t
+        csma_ctrl;                   /*!< (@ 0x0000031C) CSMA Control and Status Register                           */
+
+        struct
+        {
+__IM  uint32_t csma_cw    :
+            2;            /*!< [1..0] the contention window length in the CSMA-CA algorithm              */
+__IM  uint32_t csma_be    :
+            4;            /*!< [5..2] the backoff exponent in the CSMA-CA algorithm                      */
+__IM  uint32_t csma_nb    :
+            4;            /*!< [9..6] the number of times required to backoff in the CSMA-CA
+                                                     algorithm                                                                 */
+__IM  uint32_t txretry    :
+            3;            /*!< [12..10] TX Normal FIFO Retry Times. Number of retrys of the
+                                                     most recent TX Normal FIFO transmission: 00: 0 (default);
+                                                     ... 111: 7;                                                               */
+            uint32_t            : 2;
+__IOM uint32_t nocsman    :
+            1;            /*!< [15..15] Carrier Sense Multiple Access with Collision Avoidance
+                                                     (CSMA-CA) for TX Normal FIFO: 0: (default) Enable CSMA-CA
+                                                     for TX normal FIFO; 1: Disable CSMA-CA for TX normal FIFO                 */
+__IOM uint32_t macminbe   :
+            4;            /*!< [19..16] MAC Minimum Backoff Exponent (macMinBE). The minimum
+                                                     value of the backoff exponent in the CSMA-CA algorithm:
+                                                     0000: Collision avoidance is disabled; 0011: 3 (default)                  */
+__IOM uint32_t macmaxbe   :
+            4;            /*!< [23..20] MAC Maximal Backoff Exponent (macMaxBE). The maximal
+                                                     value of the backoff exponent in the CSMA-CA algorithm:
+                                                     0000: Collision avoidance is disabled; 0101: 5 (default)                  */
+__IOM uint32_t csmabf     :
+            4;            /*!< [27..24] Maximum CSMA Backoff (macMaxCSMABackoff). The maximum
+                                                     number of backoffs the CSMA-CA algorithm will attempt before
+                                                     declaring a hannel access failure, default value is 4.                    */
+__IOM uint32_t slotted    :
+            1;            /*!< [28..28] Slotted CSMA-CA Mode: 0: (default) Disable Slotted
+                                                     CSMA-CA mode; 1: Enable Slotted CSMA-CA mode;                             */
+__IOM uint32_t batlifeext :
+            1;            /*!< [29..29] Battery Life Extention Mode: 0: (default) Disable Battery
+                                                     Life Extention Mode; 1: Enable Battery Life Extention Mode                */
+__IOM uint32_t backoff_nb_gain :
+            2;       /*!< [31..30] Gain of csma_nb for next backoff periods increas, the
+                                                     new(next) backoff periods is backoff_p + backoff_nb_gain
+                                                     * csma_nb, backoff_p = (random(2^be -1); 00: periods is
+                                                     backoff_p; 01: periods is backoff_p + csma_nb; 10: periods
+                                                     is backoff_p + 2*csma_nb; 11: periods is backoff_p + 3*csma_nb;           */
+        } csma_ctrl_b;
+    } ;
+
+    union
+    {
+        __IOM uint32_t
+        tx_settle_ctrl;              /*!< (@ 0x00000320) TX Settling Time Control Register                          */
+
+        struct
+        {
+__IOM uint32_t txont      :
+            9;            /*!< [8..0] TX Settling Time 0. Transmitter settling time to begin
+                                                     packet transmission. TXONT is a 9-bit value. 0101000: (default
+                                                     - Do Not Change)                                                          */
+__IOM uint32_t txonts     :
+            4;            /*!< [12..9] TX Settling Time 1. Transmitter settling time to begin
+                                                     packet transmission:0010: (default); 0101: (optimized -
+                                                     Do Not Change)                                                            */
+            uint32_t            : 3;
+__IOM uint32_t pacont     :
+            9;            /*!< [24..16] Power Amplifier Settling Time 0. Power amplifier settling
+                                                     time to begin packet transmission. PACONT is a 9-bit value.
+                                                     00101001: (default - Do Not Change)                                       */
+__IOM uint32_t paonts     :
+            4;            /*!< [28..25] Power Amplifier Settling Time 1. Power amplifier settling
+                                                     time to begin packet transmission: 0001: (default); 0100:
+                                                     (optimized - Do Not Change)                                               */
+            uint32_t            : 3;
+        } tx_settle_ctrl_b;
+    } ;
+
+    union
+    {
+        __IM  uint32_t
+        tx_frm_len_err;              /*!< (@ 0x00000324) TX Frame Length Error Status Register                      */
+
+        struct
+        {
+__IM  uint32_t txg2lerr   :
+            1;            /*!< [0..0] Indicates the error of packet in GTSFIFO2 with the frame
+                                                     length is zero for TX or the header length is 0 for encryption            */
+__IM  uint32_t txg1lerr   :
+            1;            /*!< [1..1] Indicates the error of packet in GTSFIFO1 with the frame
+                                                     length is zero for TX or the header length is 0 for encryption            */
+__IM  uint32_t txnlerr    :
+            1;            /*!< [2..2] Indicates the error of packet in TX Normal FIFO with
+                                                     the frame length is zero for TX or the header length is
+                                                     0 for encryption                                                          */
+__IM  uint32_t txblerr    :
+            1;            /*!< [3..3] Indicates the error of packet in Beacon FIFO with the
+                                                     frame length is zero for TX or the header length is 0 for
+                                                     encryption                                                                */
+            uint32_t            : 28;
+        } tx_frm_len_err_b;
+    } ;
+
+    union
+    {
+        __IM  uint32_t
+        txsr;                        /*!< (@ 0x00000328) TX Status Register                                         */
+
+        struct
+        {
+__IM  uint32_t txns       :
+            1;            /*!< [0..0] Normal FIFO Release Status: 0: (default) Succeeded; 1:
+                                                     Fail, retry count exceed or TX is termed (lost PHY grant)                 */
+__IM  uint32_t txg1s      :
+            1;            /*!< [1..1] GTS1 FIFO Release Status: 0: (default) Succeeded; 1:
+                                                     Fail, retry count exceed or TX is termed (lost PHY grant)                 */
+__IM  uint32_t txg2s      :
+            1;            /*!< [2..2] GTS2 FIFO Release Status: 0: (default) Succeeded; 1:
+                                                     Fail, retry count exceed or TX is termed(lost PHY grant)                  */
+__IM  uint32_t txg1fnt    :
+            1;            /*!< [3..3] GTS1 FIFO Transmission Status: 0: (default) Succeeded;
+                                                     1: Fail, no enough time to transmit before the end of a
+                                                     GTS or TX is termed (lost PHY grant)                                      */
+__IM  uint32_t txg2fnt    :
+            1;            /*!< [4..4] GTS2 FIFO Transmission Status: 0: (default) Succeeded;
+                                                     1: Fail, no enough time to transmit before the end of a
+                                                     GTS or TX is termed (loat PHY grant)                                      */
+__IM  uint32_t ccafail    :
+            1;            /*!< [5..5] Clear Channel Assessment (CCA) Status of Last Transmission:
+                                                     0: (default) Channel Idle; 1: Channel busy                                */
+            uint32_t            : 26;
+        } txsr_b;
+    } ;
+    __IM  uint32_t  RESERVED2;
+
+    union
+    {
+        __IM  uint32_t
+        tx_time_stamp;               /*!< (@ 0x00000330) Frame TX Timestamp Register                                */
+
+        struct
+        {
+__IM  uint32_t txm_tx_timestmp_clk :
+            22;  /*!< [21..0] the BT native clock(BT NativeClock[22:1]) of TX timestamp,
+                                                     which is latched at the 1st symbol of the MAC Header (Frame
+                                                     Control) transmitting is started                                          */
+__IM  uint32_t txm_tx_timestmp_cntr :
+            10; /*!< [31..22] the BT clock counter of TX timestamp, which is latched
+                                                     at the 1st symbol of the MAC Header (Frame Control) transmitting
+                                                     is started                                                                */
+        } tx_time_stamp_b;
+    } ;
+
+    union
+    {
+        __IOM uint32_t
+        tx_given_time_set;           /*!< (@ 0x00000334) BT Time Comparator for TX Trigger Time Control
+                                                                    Register                                                   */
+
+        struct
+        {
+__IOM uint32_t txn_nclk   :
+            18;           /*!< [17..0] The native clock value of the BT-MAC timer comparator
+                                                     for FW to setup the MAC time to trigger the normal TX FIFO
+                                                     transmission. When the (BT NativeClock[18:1] || ClockCounter[9:0])
+                                                     value is matched with (txn_nclk || txn_ckc) then trigger
+                                                     the normal TX FIFO transmission.                                          */
+__IOM uint32_t txn_ckc    :
+            10;           /*!< [27..18] The clock counter value of the BT-MAC timer comparator
+                                                     for FW to setup the MAC time to trigger the normal TX FIFO
+                                                     transmission. When the BT-MAC timer value is matched with
+                                                     (txn_nclk || txn_ckc) then trigger the normal TX FIFO transmission.       */
+__IOM uint32_t schtxnocca :
+            1;            /*!< [28..28] To indicate whether the MAC TX machine should do CCA
+                                                     to acquire the channel for Schedule TX mode transmissions:
+                                                     0: The MAC TX machine should do CCA for the Scheduled TX
+                                                     mode transmission; 1: The MAC TX machine do NOT do CCA
+                                                     for the Scheduled TX mode transmission. The HW should re-latch
+                                                     this bit on txntmren is set.                                              */
+            uint32_t            : 2;
+__IOM uint32_t txntmren   :
+            1;            /*!< [31..31] BT-MAC Timer comparator for normal FIFO TX time enable
+                                                     control: 0: Disable the BT-MAC Timer comparator which will
+                                                     trigger the normal FIFO transmission; 1: Enable the BT-MAC
+                                                     Timer comparator which will trigger the normal FIFO transmission.The
+                                                     FW should fill the normal TX FIFO with the frame to be
+                                                     transmitted, setup the TX Time comparator value and the
+                                                     TX option (with CCA or not) before enable this Timer comparator.The
+                                                     TX machine should clear this bit once the BT-MAC timer
+                                                     value is matched with (txn_                                               */
+        } tx_given_time_set_b;
+    } ;
+
+    union
+    {
+        __IM  uint32_t
+        tx_given_time_status;        /*!< (@ 0x00000338) Given Time TX Status Register                              */
+
+        struct
+        {
+__IM  uint32_t zbrf_tx_given_time_encoun_tx :
+            1;/*!< [0..0] to report the TX at given time procedure is conflict
+                                                     with another TX process. 1 means this conflict is happened.               */
+__IM  uint32_t zbrf_tx_given_time_encoun_rx :
+            1;/*!< [1..1] to report the TX at given time procedure is conflict
+                                                     with a RX process. 1 means this conflict is happened.                     */
+__IM  uint32_t zbrf_tx_given_time_obsolete :
+            1;/*!< [2..2] to report the TX at given time procedure is failed due
+                                                     to the specified TX trigger time is past or it has no enough
+                                                     time to settle PHY.                                                       */
+__IM  uint32_t zbrf_tx_given_time_not_gnt :
+            1;/*!< [3..3] to report the TX at given time procedure is failed due
+                                                     to the PHY is not granted at the specified TX trigger time.               */
+__IM  uint32_t zbrf_tx_given_time_not_in_recv :
+            1;/*!< [4..4] to report the TX at given time procedure is failed due
+                                                     to the PHY is not ready (in RX state) at the specified
+                                                     TX trigger time. This case normaly is caused by the scheduled
+                                                     TX is triggered when the PHY is re-granted and still in
+                                                     PHY re-initialization.                                                    */
+            uint32_t            : 27;
+        } tx_given_time_status_b;
+    } ;
+
+    union
+    {
+        __IOM uint32_t
+        gts_slot_cfg;                /*!< (@ 0x0000033C) GTS Slots Configuration Register                           */
+
+        struct
+        {
+__IOM uint32_t gts_slot_en :
+            7;           /*!< [6..0] GTS slot enable control, bit 0 ~ 6 correspond to GTS
+                                                     slot 1 ~7: 0: disable the corresponding GTS slot (default)1:
+                                                     enable the corresponding GTS slot                                         */
+            uint32_t            : 1;
+__IOM uint32_t gts_slot_trx :
+            7;          /*!< [14..8] GTS slot TX/RX configuration, bit 0 ~ 6 correspond to
+                                                     GTS slot 1 ~7: 0: configure the corresponding GTS slot
+                                                     for RX1: configure the corresponding GTS slot for TX                      */
+            uint32_t            : 17;
+        } gts_slot_cfg_b;
+    } ;
+    __IM  uint32_t  RESERVED3[16];
+
+    union
+    {
+        __IOM uint32_t
+        rx_fltr_ctrl;                /*!< (@ 0x00000380) RX Filter Control Register                                 */
+
+        struct
+        {
+__IOM uint32_t promi      :
+            1;            /*!< [0..0] Accept all packets with CRC OK                                     */
+__IOM uint32_t errpkt     :
+            1;            /*!< [1..1] Accept all kinds of pkt(including CRC error)                       */
+__IOM uint32_t scanmode   :
+            1;            /*!< [2..2] enable RX Filter scan mode. When scan mode is enabled,
+                                                     only Beacon frame with FCS correct will be accepted by
+                                                     RX filter.                                                                */
+__IOM uint32_t group_rxmode :
+            1;          /*!< [3..3] macGroupRxMode Enable. When group RX mode is enabled,
+                                                     frames with EUI-64 group address as its destination address
+                                                     are accepted by RX filter.                                                */
+__IOM uint32_t implicit_broadcast :
+            1;    /*!< [4..4] RX Filter macImplicitBroadcast Enable. When implicit
+                                                     broadcast mode is enabled, frames without destination address
+                                                     are accepted by RX filter                                                 */
+__IOM uint32_t rf_early_term :
+            1;         /*!< [5..5] Enable the PHY RX early term for RX packet discard:1:
+                                                     enable the PHY RX early term for power saving. The RX will
+                                                     be truned off for the period of RX discarded frame transmission;
+                                                     0: disable the PHY RX early term                                          */
+__IOM uint32_t frm06_rx_early :
+            1;        /*!< [6..6] Enable the RX early interrupt for non-secure 2006 frame:
+                                                     0 : RX early interrupt will be asserted for receiving 2006
+                                                     Security Frame or all 2015 Frame excluding ack frame type;
+                                                     1 : RX early interrupt will be asserted for all receiving
+                                                     frame, including 2006 non-secure frame, excluding ack frame
+                                                     type                                                                      */
+            uint32_t            : 1;
+__IOM uint32_t rxm_force_crc :
+            1;         /*!< [8..8] Force RXM Received CRC result is error: 0: (default)
+                                                     Force CRC error disabled; 1: Force CRC error enabled For
+                                                     MAC function test purpose                                                 */
+            uint32_t            : 23;
+        } rx_fltr_ctrl_b;
+    } ;
+
+    union
+    {
+        __IOM uint32_t
+        rxfrmtype;                   /*!< (@ 0x00000384) RX Frame Type Filter Control Register                      */
+
+        struct
+        {
+__IOM uint32_t rxftype    :
+            8;            /*!< [7..0] RX Frame Type Filter. 00001011: (default - Do Not Change)Packet
+                                                     type field in Frame control byte of IEEE802.15.4 is 3 bits,
+                                                     meaning 8 types of packets. Each bit of RXFRM_TYPE correlated
+                                                     to the 8 types. When correlated bit is '1', RXMAC receives
+                                                     the type of packet without filtering out. bit 0 : 000 (beacon);
+                                                     bit 1 : 001 (data); bit 2 : 010 (ack); bit 3 : 011 (command);
+                                                     bit 4 : (reserved)bit 5: 101 (multipurpose): bit 6~7 :
+                                                     (reserved)                                                                */
+__IOM uint32_t rxftype15  :
+            8;            /*!< [15..8] RX Frame Type Filter for IEEE802.15.4 version2015. 00001111:
+                                                     (default)Packet type field in Frame control byte of IEEE802.15.4
+                                                     is 3 bits, meaning 8 types of packets. Each bit of RXFRM_TYPE
+                                                     correlated to the 8 types. When correlated bit is '1',
+                                                     RXMAC receives the type of packet without filtering out.
+                                                     bit 0 : 000 (beacon); bit 1 : 001 (data); bit 2 : 010 (ack);
+                                                     bit 3 : 011 (command); bit 4~5 : (reserved); bit 6: 110
+                                                     (Fragement or Frak): bit 7: 111 (Extended):                               */
+            uint32_t            : 16;
+        } rxfrmtype_b;
+    } ;
+
+    union
+    {
+        __IOM uint32_t
+        group_eadr_l;                /*!< (@ 0x00000388) Group Extended Address Lower Bytes                         */
+
+        struct
+        {
+__IOM uint32_t group_ext_addr_l :
+            32;     /*!< [31..0] EUI-64 group address lower bits (bits[31:0])                      */
+        } group_eadr_l_b;
+    } ;
+
+    union
+    {
+        __IOM uint32_t
+        group_eadr_h;                /*!< (@ 0x0000038C) Group Extended Address Higher Bytes                        */
+
+        struct
+        {
+__IOM uint32_t group_ext_addr_h :
+            32;     /*!< [31..0] EUI-64 group address higher bits (bits[63:32])                    */
+        } group_eadr_h_b;
+    } ;
+
+    union
+    {
+        __IOM uint32_t
+        assoc_eadr_l;                /*!< (@ 0x00000390) Associated Coordinator Extended Address Lower
+                                                                    Bytes                                                      */
+
+        struct
+        {
+__IOM uint32_t assoeadr_l :
+            32;           /*!< [31..0] Lower bits(bits[31:0]) of Associated Coordinator's 64-Bit
+                                                     Extended Address                                                          */
+        } assoc_eadr_l_b;
+    } ;
+
+    union
+    {
+        __IOM uint32_t
+        assoc_eadr_h;                /*!< (@ 0x00000394) Associated Coordinator Extended Address Higher
+                                                                    Bytes                                                      */
+
+        struct
+        {
+__IOM uint32_t assoeadr_h :
+            32;           /*!< [31..0] Higher bits(bits[63:32]) of Associated Coordinator's
+                                                     64-Bit Extended Address                                                   */
+        } assoc_eadr_h_b;
+    } ;
+
+    union
+    {
+        __IOM uint32_t
+        assoc_sadr;                  /*!< (@ 0x00000398) Associated Coordinator Short Address Low Byte              */
+
+        struct
+        {
+__IOM uint32_t assosadr   :
+            16;           /*!< [15..0] 16-Bits Short Address of Associated Coordinator                   */
+            uint32_t            : 16;
+        } assoc_sadr_b;
+    } ;
+
+    union
+    {
+        __IOM uint32_t
+        assoc_bcn_ctrl;              /*!< (@ 0x0000039C) Association Beacon Source Address Control Register         */
+
+        struct
+        {
+__IOM uint32_t abctrl     :
+            1;            /*!< [0..0] Associate beacon source address enable. 1: disable; 0:
+                                                     enable                                                                    */
+            uint32_t            : 31;
+        } assoc_bcn_ctrl_b;
+    } ;
+
+    union
+    {
+        __IM  uint32_t
+        rxm_fch;                     /*!< (@ 0x000003A0) Received Frame Control Fields Store Register               */
+
+        struct
+        {
+__IM  uint32_t frame_type :
+            3;            /*!< [2..0] the frame type of the latest received frame, for debug             */
+__IM  uint32_t sec_en     :
+            1;            /*!< [3..3] the security enable bit of the latest received frame,
+                                                     for debug                                                                 */
+__IM  uint32_t pend       :
+            1;            /*!< [4..4] the frame pending bit of the latest received frame, for
+                                                     debug                                                                     */
+__IM  uint32_t ack_req    :
+            1;            /*!< [5..5] the ACK request bit of the latest received frame, for
+                                                     debug                                                                     */
+__IM  uint32_t panid_comp :
+            1;            /*!< [6..6] the PAN ID compressed bit of the latest received frame,
+                                                     for debug                                                                 */
+            uint32_t            : 1;
+__IM  uint32_t seq_comp   :
+            1;            /*!< [8..8] the sequence number compressed bit of the latest received
+                                                     frame, for debug                                                          */
+__IM  uint32_t ie_exist   :
+            1;            /*!< [9..9] the IE present bit of the latest received frame, for
+                                                     debug                                                                     */
+__IM  uint32_t dst_adr_mode :
+            2;          /*!< [11..10] the destination address mode of the latest received
+                                                     frame, for debug00: None; 01: Reserved; 10: 16-bit short
+                                                     address; 11: 64-bit extended address                                      */
+__IM  uint32_t frm_ver    :
+            2;            /*!< [13..12] the frame version of the latest received frame, for
+                                                     debug                                                                     */
+__IM  uint32_t src_adr_mode :
+            2;          /*!< [15..14] the source address mode of the latest received frame:00:
+                                                     None; 01: Reserved; 10: 16-bit short address; 11: 64-bit
+                                                     extended address                                                          */
+__IM  uint32_t mp_frame_type :
+            3;         /*!< [18..16] the frame type of the latest received frame, for debug           */
+__IM  uint32_t mp_long_frm :
+            1;           /*!< [19..19] the Long Frame bit of the latest received MP frame,
+                                                     for debug                                                                 */
+__IM  uint32_t mp_dst_adr_mode :
+            2;       /*!< [21..20] the destination address mode of the latest received
+                                                     MP frame, for debug00: None; 01: Reserved; 10: 16-bit short
+                                                     address; 11: 64-bit extended address                                      */
+__IM  uint32_t mp_src_adr_mode :
+            2;       /*!< [23..22] the source address mode of the latest received MP frame,
+                                                     for debug00: None; 01: Reserved; 10: 16-bit short address;
+                                                     11: 64-bit extended address                                               */
+__IM  uint32_t mp_panid_exist :
+            1;        /*!< [24..24] indicates whether the PAN ID is present in received
+                                                     MP frame, for debug                                                       */
+__IM  uint32_t mp_sec_en  :
+            1;            /*!< [25..25] the security enable bit of the latest received MP frame,
+                                                     for debug                                                                 */
+__IM  uint32_t mp_seq_comp :
+            1;           /*!< [26..26] the Sequence Number Suppression bit of the latest received
+                                                     MP frame, for debug                                                       */
+__IM  uint32_t mp_frm_pend :
+            1;           /*!< [27..27] the Frame Pending bit of the latest received MP frame,
+                                                     for debug                                                                 */
+__IM  uint32_t mp_frm_ver :
+            2;            /*!< [29..28] the frame version of the latest received MP frame,
+                                                     for debug                                                                 */
+__IM  uint32_t mp_ack_req :
+            1;            /*!< [30..30] the ACK request bit of the latest received MP frame,
+                                                     for debug                                                                 */
+__IM  uint32_t rxm_fchmp_ie_exist :
+            1;    /*!< [31..31] the IE present bit of the latest received mp frame,
+                                                     for debug                                                                 */
+        } rxm_fch_b;
+    } ;
+
+    union
+    {
+        __IM  uint32_t
+        rx_sn_ie_update;             /*!< (@ 0x000003A4) Received Frame's Sequence Number and IE Updated
+                                                                    Status                                                     */
+
+        struct
+        {
+__IM  uint32_t seq_num    :
+            8;            /*!< [7..0] the sequence number of the latest received frame, for
+                                                     debug                                                                     */
+__IM  uint32_t hdr_ie_term :
+            1;           /*!< [8..8] MAC HW set this bit to indicated the Header IEs parsing
+                                                     is finished (Header Termination IE is detected).                          */
+__IM  uint32_t csl_update :
+            1;            /*!< [9..9] CSL IE Parser have been update in the transaction which
+                                                     will be set to 1. Auto Clear when next Rx reception starts                */
+__IM  uint32_t tc_update  :
+            1;            /*!< [10..10] Time Correction IE have been update in the transaction
+                                                     which will be set to 1. Auto Clear when next Rx reception
+                                                     starts.                                                                   */
+            uint32_t            : 21;
+        } rx_sn_ie_update_b;
+    } ;
+
+    union
+    {
+        __IM  uint32_t
+        rx_csl_ie;                   /*!< (@ 0x000003A8) CSL IE In Received Frame                                   */
+
+        struct
+        {
+__IM  uint32_t csl_period :
+            16;           /*!< [15..0] the CSL period of the CSL IE in received frame                    */
+__IM  uint32_t csl_phase  :
+            16;           /*!< [31..16] the CSL phase of the CSL IE in received frame                    */
+        } rx_csl_ie_b;
+    } ;
+
+    union
+    {
+        __IM  uint32_t
+        rx_tmcor_ie;                 /*!< (@ 0x000003AC) Time Correction IE In Received Frame                       */
+
+        struct
+        {
+__IM  uint32_t tm_sync_info :
+            16;         /*!< [15..0] the Time Sync Info of the Time Correction IE in received
+                                                     frame                                                                     */
+            uint32_t            : 16;
+        } rx_tmcor_ie_b;
+    } ;
+
+    union
+    {
+        __IM  uint32_t
+        rx_aux_sec_hdr;              /*!< (@ 0x000003B0) RX Security Aux Header Information Register                */
+
+        struct
+        {
+__IM  uint32_t rxm_sec_level :
+            3;         /*!< [2..0] 'the Security Level field of the received Aux security
+                                                     header. Value of this field indicates the security level
+                                                     (method) of the received secured frame: 0: none; 1: MIC-32;
+                                                     2: MIC-64; 3: MIC-128; 4: AES; 5: AES-MIC-32; 6: AES-MIC-64;
+                                                     7: AES-MIC-128;                                                           */
+__IM  uint32_t rxm_keyid_mode :
+            2;        /*!< [4..3] 'the Key Indetifier Mode field of the received Aux security
+                                                     header. Value of this field indicates how many of bis of
+                                                     rxm_keyid is valid.                                                       */
+__IM  uint32_t rxm_sec_frm_cnt_comp :
+            1;  /*!< [5..5] the Frame Counter Suppression bit of the Security Control
+                                                     field in the Aux Security header of the latest received
+                                                     frame                                                                     */
+__IM  uint32_t rxm_sec_asn_nonce :
+            1;     /*!< [6..6] the 'ASN in Nonce' bit of the Security Control field
+                                                     in the Aux Security header of the latest received frame                   */
+            uint32_t            : 1;
+__IM  uint32_t rxm_key_index :
+            8;         /*!< [15..8] the key index of the key identifier in the Aux security
+                                                     header of received incoming frame. This field is valid
+                                                     only when the rxm_keyid_mode != 0                                         */
+            uint32_t            : 16;
+        } rx_aux_sec_hdr_b;
+    } ;
+
+    union
+    {
+        __IM  uint32_t
+        rx_aux_frmcnt;               /*!< (@ 0x000003B4) RX Security Aux Header Frame Counter Information
+                                                                    Register                                                   */
+
+        struct
+        {
+__IM  uint32_t rxm_sec_frm_cnt :
+            32;      /*!< [31..0] the frame counter field in the Aux security header of
+                                                     the latest received security frame                                        */
+        } rx_aux_frmcnt_b;
+    } ;
+
+    union
+    {
+        __IM  uint32_t
+        rx_aux_key_src_l;            /*!< (@ 0x000003B8) RX Security Aux Key Source Lower Bytes Register            */
+
+        struct
+        {
+__IM  uint32_t rxm_key_src_l :
+            32;        /*!< [31..0] the bits [31:0] of the Key source field of the received
+                                                     Aux security header. The number of valid bits of the Key
+                                                     source is depends on the Key Identifier Mode: 0: key identifier
+                                                     size is 0, ignore the value of rxm_key_index and rxm_key_src;
+                                                     1: key identifier size is 1 byte, only rxm_key_index is
+                                                     valid; 2: key identifier size is 5 bytes, only rxm_key_indx
+                                                     and rxm_key_src[31:0] are valid; 3: key identifier size
+                                                     is 9 bytes, the rxm_key_indx and whole rxm_key_src are
+                                                     valid;                                                                    */
+        } rx_aux_key_src_l_b;
+    } ;
+
+    union
+    {
+        __IM  uint32_t
+        rx_aux_key_src_h;            /*!< (@ 0x000003BC) RX Security Aux Key Source Higher Bytes Register           */
+
+        struct
+        {
+__IM  uint32_t rxm_key_src_h :
+            32;        /*!< [31..0] the bits [63:32] of the Key source field of the received
+                                                     Aux security header. The number of valid bits of the Key
+                                                     source is depends on the Key Identifier Mode: 0: key identifier
+                                                     size is 0, ignore the value of rxm_key_index and rxm_key_src;
+                                                     1: key identifier size is 1 byte, only rxm_key_index is
+                                                     valid; 2: key identifier size is 5 bytes, only rxm_key_indx
+                                                     and rxm_key_src[31:0] are valid; 3: key identifier size
+                                                     is 9 bytes, the rxm_key_indx and whole rxm_key_src are
+                                                     valid;                                                                    */
+        } rx_aux_key_src_h_b;
+    } ;
+
+    union
+    {
+        __IOM uint32_t
+        rx_fifo_ctrl;                /*!< (@ 0x000003C0) RX FIFO Control Register                                   */
+
+        struct
+        {
+__IOM uint32_t rxfifo2    :
+            1;            /*!< [0..0] RX Ping-pong FIFO Enable: 0: (default) Disable; 1: Enable          */
+            uint32_t            : 1;
+__IOM uint32_t rxffwr     :
+            1;            /*!< [2..2] enable FW to access RX FIFO: 1: RX FIFO is owned by FW
+                                                     and FW can read/wrire RX FIFO; 0: RX FIFO is owned by MAC
+                                                     HW, FW cannot access RX FIFO                                              */
+            uint32_t            : 5;
+__IOM uint32_t rxflush    :
+            1;            /*!< [8..8] Flush the RX FIFO: 1: Flush RX FIFO. RX FIFO data is
+                                                     not modified. If Ping-pong FIFO is enabled (rxfifo2 = 1),
+                                                     both FIFOs are flushed at the same time. Bit is automatically
+                                                     cleared to '0' by hardware                                                */
+            uint32_t            : 23;
+        } rx_fifo_ctrl_b;
+    } ;
+
+    union
+    {
+        __IOM uint32_t
+        rx_early_fw_sts;             /*!< (@ 0x000003C4) RX early interrupt FW process status                       */
+
+        struct
+        {
+__IOM uint32_t rx_early_sts :
+            8;          /*!< [7..0] for FW to store the RX early interrupt process status
+                                                     to assist the incoming frame receiving pre-processing.
+                                                     MAC HW will clear this field on every start of a new incoming
+                                                     frame receiving.                                                          */
+            uint32_t            : 24;
+        } rx_early_fw_sts_b;
+    } ;
+
+    union
+    {
+        __IOM uint32_t
+        bt_clk_sel;                  /*!< (@ 0x000003C8) RX Timestamp Timer Selection Control Register              */
+
+        struct
+        {
+__IOM uint32_t rx_tim_sel :
+            1;            /*!< [0..0] Controls the RX machine to select the time for RX timestamp
+                                                     latching: 0 : Used 16 bits MAC down count timer; 1 : Used
+                                                     10 bits BT clock counter and BT Native clock[22:1] value                  */
+            uint32_t            : 31;
+        } bt_clk_sel_b;
+    } ;
+
+    union
+    {
+        __IOM uint32_t
+        rxm_sts;                     /*!< (@ 0x000003CC) RX Machine Status Register                                 */
+
+        struct
+        {
+__IOM uint32_t pidconflict :
+            1;           /*!< [0..0] PAN ID conflict. Write '1' to clear                                */
+__IM  uint32_t rxm_hdr_rdy :
+            1;           /*!< [1..1] RX Header ready, this bit is set to indicates the MAC
+                                                     header (includes Security Aux. header if present) of the
+                                                     incoming frame is received. It is cleared automatically
+                                                     when a new frame receiving is started.                                    */
+__IM  uint32_t sec_dec_err :
+            1;           /*!< [2..2] Security MIC check Error (incorrect): 0: (default) Security
+                                                     decryption and MIC is correct; 1: Security decryption done
+                                                     and MIC is inclrrect this bit is set when use the Security
+                                                     engine to do the RX FIFO secure frame decryption and the
+                                                     result of MIC check is error                                              */
+__IM  uint32_t rxm_crc_err :
+            1;           /*!< [3..3] RX CRC Error: 0: (default) RX CRC correct; 1: RX CRC
+                                                     error this bit is set when an incoming frame receiving
+                                                     is finished and the FCS check result is error                             */
+__IM  uint32_t rxfifo_overflow :
+            1;       /*!< [4..4] RX FIFO Overflow: 0: (default) Not overflow; 1: Overflow
+                                                     RX FIFO overflow is occurred when RX FIFO is full and a
+                                                     new incoming frame is attempts to be stored into RX FIFO.                 */
+__IM  uint32_t sec_dec_ignored :
+            1;       /*!< [5..5] rx decryption is ignored for the latest received secure
+                                                     frame, this bit is valid only when the ping-pong FIFO mode
+                                                     is enabled0 : RX decryption is not ignored (start decryption
+                                                     is triggered)1 : RX decryption is ignored                                 */
+            uint32_t            : 1;
+__IM  uint32_t rxfifo_full :
+            1;           /*!< [7..7] RX FIFO Full: 0: (default) RX FIFO available for data
+                                                     receiving; 1: RX FIFO not available for data receiving
+                                                     for single RX FIFO operation mode, RX FIFO full is occurred
+                                                     when a received frame is stored into RX FIFO. RX FIFO full
+                                                     status is cleared once the FW read frame data from the
+                                                     RX FIFO. for ping-pong RX FIFO operation mode. RX FIFO
+                                                     full is occurred when 2 received frames are stored into
+                                                     RX FIFO seprately and FW cannot read RX FIFO in time. the
+                                                     RX FIFO full status is cleared once FW read one fr                        */
+__IM  uint32_t rdff1      :
+            1;            /*!< [8..8] RX FIFO read selection flag for RX FIFO Reading: 0: (default)
+                                                     Read data from RX FIFO 0; 1: Read data from RX FIFO 1 if
+                                                     the RX FIFO operation mode is single RX FIFO, this flag
+                                                     always is 0; if the RX FIFO operation mode is ping-pong
+                                                     RX FIFO, this flag will toggle for every RX FIFO read.                    */
+__IM  uint32_t wrff1      :
+            1;            /*!< [9..9] RX FIFO write selection flag for PHY to select the RX
+                                                     FIFO to store received frame: 0: write data to RX FIFO
+                                                     0; 1: write data to RX FIFO 1 if the RX FIFO operation
+                                                     mode is single RX FIFO, this flag always is 0; if the RX
+                                                     FIFO operation mode is ping-pong RX FIFO, this flag will
+                                                     toggle for every RX FIFO write.                                           */
+            uint32_t            : 15;
+__IM  uint32_t last_rxm_hdr_rdy :
+            1;      /*!< [25..25] the latched value of rxm_hdr_rdy bit. It keep update
+                                                     the latched value during RXM state is busy and hold the
+                                                     latest latched value when RXM state is idle                               */
+            uint32_t            : 1;
+__IM  uint32_t last_rxm_crc_err :
+            1;      /*!< [27..27] the latched value of rxm_crc_err bit. It keep update
+                                                     the latched value during RXM state is busy and hold the
+                                                     latest latched value when RXM state is idle                               */
+__IM  uint32_t last_rxfifo_overflow :
+            1;  /*!< [28..28] the latched value of rxfifo_overflow bit. It keep update
+                                                     the latched value during RXM state is busy and hold the
+                                                     latest latched value when RXM state is idle                               */
+            uint32_t            : 1;
+__IM  uint32_t lwrff1     :
+            1;            /*!< [30..30] the latched value of wrff1 bit. It keep update the
+                                                     latched value during RXM state is busy and hold the latest
+                                                     latched value when RXM state is idle                                      */
+__IM  uint32_t last_rxfifo_full :
+            1;      /*!< [31..31] the latched value of rxfifo_full bit. It keep update
+                                                     the latched value during RXM state is busy and hold the
+                                                     latest latched value when RXM state is idle                               */
+        } rxm_sts_b;
+    } ;
+
+    union
+    {
+        __IM  uint32_t
+        rx_src_addr_l;               /*!< (@ 0x000003D0) RX Source Address Lower Bytes Register                     */
+
+        struct
+        {
+__IM  uint32_t srcadr_l   :
+            32;           /*!< [31..0] Received Packet Source Address lower bits [31:0]                  */
+        } rx_src_addr_l_b;
+    } ;
+
+    union
+    {
+        __IM  uint32_t
+        rx_src_addr_h;               /*!< (@ 0x000003D4) RX Source Address Higher Bytes Register                    */
+
+        struct
+        {
+__IM  uint32_t srcadr_h   :
+            32;           /*!< [31..0] Received Packet Source Address higher bits [63:32]                */
+        } rx_src_addr_h_b;
+    } ;
+
+    union
+    {
+        __IOM uint32_t
+        rxmbcnt_fsm;                 /*!< (@ 0x000003D8) RX Machine Received Byte Count and RXM State
+                                                                    Register                                                   */
+
+        struct
+        {
+__IM  uint32_t rxmbytecnt :
+            8;            /*!< [7..0] RXM receiving byte counter, used to make sure 'superframe
+                                                     specification' of beacon frame is in RXFIFO. It is for
+                                                     decryption of beacon frame                                                */
+__IOM uint32_t frm_cs     :
+            6;            /*!< [13..8] RXM frame current state                                           */
+            uint32_t            : 2;
+__IM  uint32_t frm_ack_cs :
+            3;            /*!< [18..16] RXM ACK frame current state, for debug                           */
+            uint32_t            : 13;
+        } rxmbcnt_fsm_b;
+    } ;
+    __IM  uint32_t  RESERVED4[9];
+
+    union
+    {
+        __IOM uint32_t
+        src_addr_filter_ctrl;        /*!< (@ 0x00000400) Source Address Match Filter Control Register               */
+
+        struct
+        {
+__IOM uint32_t enh_frmpend_en :
+            1;        /*!< [0..0] enable the enhanced frame pending mechanism (defined
+                                                     by Thread 1.2 Spec.) of auto frame pending bit fill in
+                                                     the Frame Control of Imm-Ack. 0: enhanced frame pending
+                                                     is disabled. The source address match filter HW will set
+                                                     the Frame Pending bit of a Imm-Ack frame which response
+                                                     to a Data Request command frame. 1: enhanced frame pending
+                                                     is enabled. The source address match filter HW will set
+                                                     the Frame Pending bit of Imm-Ack frames those response
+                                                     to Data frames or Command frames.                                         */
+__IOM uint32_t pending_ack :
+            1;           /*!< [1..1] the pending bit value of Imm-Ack to response to an incoming
+                                                     MAC frame other than Data Request command and its source
+                                                     address does not match to any Source Address Match Filter
+                                                     entry.                                                                    */
+__IOM uint32_t datreq_cmd_pending_ack :
+            1;/*!< [2..2] the pending bit value of Imm-Ack to response to a Data
+                                                     Request command frame and its source address do not match
+                                                     to any Source Address Match Filter entry.                                 */
+            uint32_t            : 29;
+        } src_addr_filter_ctrl_b;
+    } ;
+
+    union
+    {
+        __IOM uint32_t
+        src_ext_match_entry_en;      /*!< (@ 0x00000404) Extended Address Entries of Source Address Match
+                                                                    Filter Enable Control Register                             */
+
+        struct
+        {
+__IOM uint32_t ext_entry_en :
+            16;         /*!< [15..0] enable control of each extended address entry of source
+                                                     address match filter. Bit 0 ~ bit 15 control entry 0 ~
+                                                     entry15 corresponding.                                                    */
+            uint32_t            : 16;
+        } src_ext_match_entry_en_b;
+    } ;
+
+    union
+    {
+        __IOM uint32_t
+        src_short_match_entry_en;    /*!< (@ 0x00000408) Short Address Entries of Source Address Match
+                                                                    Filter Enable Control Register                             */
+
+        struct
+        {
+__IOM uint32_t ext_entry_en :
+            32;         /*!< [31..0] enable control of each short address entry of source
+                                                     address match filter. Bit 0 ~ bit 31 control entry 0 ~
+                                                     entry31 corresponding.                                                    */
+        } src_short_match_entry_en_b;
+    } ;
+
+    union
+    {
+        __IOM uint32_t
+        src_addr_match_sts;          /*!< (@ 0x0000040C) Source Address Match Filter Status Register                */
+
+        struct
+        {
+__IOM uint32_t src_match_entry_id :
+            5;    /*!< [4..0] Indicates the entry index of Source Address Match Filter
+                                                     of the latest matched result.                                             */
+__IOM uint32_t src_match_entry_type :
+            1;  /*!< [5..5] Indicates the entry type of Source Address Match Filter
+                                                     of the latest matched result. 0: match to a short address
+                                                     entry; 1: match to a extended address entry;                              */
+__IOM uint32_t src_match_status_update :
+            1;/*!< [6..6] indicates the source address of an incoming RX frame
+                                                     is matched with one of entry of source address filter.
+                                                     FW write 1 to clear.                                                      */
+            uint32_t            : 25;
+        } src_addr_match_sts_b;
+    } ;
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t
+            src_short_match0;          /*!< (@ 0x00000410) Short Source Address Match Filter Entry 0                  */
+
+            struct
+            {
+__IOM uint32_t addr     :
+                16;           /*!< [15..0] the short address of short address match entry 0                  */
+__IOM uint32_t panid    :
+                16;           /*!< [31..16] the PAN ID of short address match entry 0                        */
+            } src_short_match0_b;
+        } ;
+
+        union
+        {
+            __IOM uint32_t
+            src_ext_match0_l;          /*!< (@ 0x00000410) Lower 4-bytes of Extended Source Address Match
+                                                                    Filter Entry 0                                             */
+
+            struct
+            {
+__IOM uint32_t ext_addr_l :
+                32;         /*!< [31..0] the lower 4-bytes of extended address of extended address
+                                                     match entry 0                                                             */
+            } src_ext_match0_l_b;
+        } ;
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t
+            src_short_match1;          /*!< (@ 0x00000414) Short Source Address Match Filter Entry 1                  */
+
+            struct
+            {
+__IOM uint32_t addr     :
+                16;           /*!< [15..0] the short address of short address match entry 1                  */
+__IOM uint32_t panid    :
+                16;           /*!< [31..16] the PAN ID of short address match entry 1                        */
+            } src_short_match1_b;
+        } ;
+
+        union
+        {
+            __IOM uint32_t
+            src_ext_match0_h;          /*!< (@ 0x00000414) Higher 4-bytes of Extended Source Address Match
+                                                                    Filter Entry 0                                             */
+
+            struct
+            {
+__IOM uint32_t ext_addr_h :
+                32;         /*!< [31..0] the higher 4-bytes of extended address of extended address
+                                                     match entry 0                                                             */
+            } src_ext_match0_h_b;
+        } ;
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t
+            src_short_match2;          /*!< (@ 0x00000418) Short Source Address Match Filter Entry 2                  */
+
+            struct
+            {
+__IOM uint32_t addr     :
+                16;           /*!< [15..0] the short address of short address match entry 2                  */
+__IOM uint32_t panid    :
+                16;           /*!< [31..16] the PAN ID of short address match entry 2                        */
+            } src_short_match2_b;
+        } ;
+
+        union
+        {
+            __IOM uint32_t
+            src_ext_match1_l;          /*!< (@ 0x00000418) Lower 4-bytes of Extended Source Address Match
+                                                                    Filter Entry 1                                             */
+
+            struct
+            {
+__IOM uint32_t ext_addr_l :
+                32;         /*!< [31..0] the lower 4-bytes of extended address of extended address
+                                                     match entry 1                                                             */
+            } src_ext_match1_l_b;
+        } ;
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t
+            src_short_match3;          /*!< (@ 0x0000041C) Short Source Address Match Filter Entry 3                  */
+
+            struct
+            {
+__IOM uint32_t addr     :
+                16;           /*!< [15..0] the short address of short address match entry 3                  */
+__IOM uint32_t panid    :
+                16;           /*!< [31..16] the PAN ID of short address match entry 3                        */
+            } src_short_match3_b;
+        } ;
+
+        union
+        {
+            __IOM uint32_t
+            src_ext_match1_h;          /*!< (@ 0x0000041C) Higher 4-bytes of Extended Source Address Match
+                                                                    Filter Entry 1                                             */
+
+            struct
+            {
+__IOM uint32_t ext_addr_h :
+                32;         /*!< [31..0] the higher 4-bytes of extended address of extended address
+                                                     match entry 1                                                             */
+            } src_ext_match1_h_b;
+        } ;
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t
+            src_short_match4;          /*!< (@ 0x00000420) Short Source Address Match Filter Entry 4                  */
+
+            struct
+            {
+__IOM uint32_t addr     :
+                16;           /*!< [15..0] the short address of short address match entry 4                  */
+__IOM uint32_t panid    :
+                16;           /*!< [31..16] the PAN ID of short address match entry 4                        */
+            } src_short_match4_b;
+        } ;
+
+        union
+        {
+            __IOM uint32_t
+            src_ext_match2_l;          /*!< (@ 0x00000420) Lower 4-bytes of Extended Source Address Match
+                                                                    Filter Entry 2                                             */
+
+            struct
+            {
+__IOM uint32_t ext_addr_l :
+                32;         /*!< [31..0] the lower 4-bytes of extended address of extended address
+                                                     match entry 2                                                             */
+            } src_ext_match2_l_b;
+        } ;
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t
+            src_short_match5;          /*!< (@ 0x00000424) Short Source Address Match Filter Entry 5                  */
+
+            struct
+            {
+__IOM uint32_t addr     :
+                16;           /*!< [15..0] the short address of short address match entry 5                  */
+__IOM uint32_t panid    :
+                16;           /*!< [31..16] the PAN ID of short address match entry 5                        */
+            } src_short_match5_b;
+        } ;
+
+        union
+        {
+            __IOM uint32_t
+            src_ext_match2_h;          /*!< (@ 0x00000424) Higher 4-bytes of Extended Source Address Match
+                                                                    Filter Entry 2                                             */
+
+            struct
+            {
+__IOM uint32_t ext_addr_h :
+                32;         /*!< [31..0] the higher 4-bytes of extended address of extended address
+                                                     match entry 2                                                             */
+            } src_ext_match2_h_b;
+        } ;
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t
+            src_short_match6;          /*!< (@ 0x00000428) Short Source Address Match Filter Entry 6                  */
+
+            struct
+            {
+__IOM uint32_t addr     :
+                16;           /*!< [15..0] the short address of short address match entry 6                  */
+__IOM uint32_t panid    :
+                16;           /*!< [31..16] the PAN ID of short address match entry 6                        */
+            } src_short_match6_b;
+        } ;
+
+        union
+        {
+            __IOM uint32_t
+            src_ext_match3_l;          /*!< (@ 0x00000428) Lower 4-bytes of Extended Source Address Match
+                                                                    Filter Entry 3                                             */
+
+            struct
+            {
+__IOM uint32_t ext_addr_l :
+                32;         /*!< [31..0] the lower 4-bytes of extended address of extended address
+                                                     match entry 3                                                             */
+            } src_ext_match3_l_b;
+        } ;
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t
+            src_short_match7;          /*!< (@ 0x0000042C) Short Source Address Match Filter Entry 7                  */
+
+            struct
+            {
+__IOM uint32_t addr     :
+                16;           /*!< [15..0] the short address of short address match entry 7                  */
+__IOM uint32_t panid    :
+                16;           /*!< [31..16] the PAN ID of short address match entry 7                        */
+            } src_short_match7_b;
+        } ;
+
+        union
+        {
+            __IOM uint32_t
+            src_ext_match3_h;          /*!< (@ 0x0000042C) Higher 4-bytes of Extended Source Address Match
+                                                                    Filter Entry 3                                             */
+
+            struct
+            {
+__IOM uint32_t ext_addr_h :
+                32;         /*!< [31..0] the higher 4-bytes of extended address of extended address
+                                                     match entry 3                                                             */
+            } src_ext_match3_h_b;
+        } ;
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t
+            src_short_match8;          /*!< (@ 0x00000430) Short Source Address Match Filter Entry 8                  */
+
+            struct
+            {
+__IOM uint32_t addr     :
+                16;           /*!< [15..0] the short address of short address match entry 8                  */
+__IOM uint32_t panid    :
+                16;           /*!< [31..16] the PAN ID of short address match entry 8                        */
+            } src_short_match8_b;
+        } ;
+
+        union
+        {
+            __IOM uint32_t
+            src_ext_match4_l;          /*!< (@ 0x00000430) Lower 4-bytes of Extended Source Address Match
+                                                                    Filter Entry 4                                             */
+
+            struct
+            {
+__IOM uint32_t ext_addr_l :
+                32;         /*!< [31..0] the lower 4-bytes of extended address of extended address
+                                                     match entry 4                                                             */
+            } src_ext_match4_l_b;
+        } ;
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t
+            src_short_match9;          /*!< (@ 0x00000434) Short Source Address Match Filter Entry 9                  */
+
+            struct
+            {
+__IOM uint32_t addr     :
+                16;           /*!< [15..0] the short address of short address match entry 9                  */
+__IOM uint32_t panid    :
+                16;           /*!< [31..16] the PAN ID of short address match entry 9                        */
+            } src_short_match9_b;
+        } ;
+
+        union
+        {
+            __IOM uint32_t
+            src_ext_match4_h;          /*!< (@ 0x00000434) Higher 4-bytes of Extended Source Address Match
+                                                                    Filter Entry 4                                             */
+
+            struct
+            {
+__IOM uint32_t ext_addr_h :
+                32;         /*!< [31..0] the higher 4-bytes of extended address of extended address
+                                                     match entry 4                                                             */
+            } src_ext_match4_h_b;
+        } ;
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t
+            src_short_match10;         /*!< (@ 0x00000438) Short Source Address Match Filter Entry 10                 */
+
+            struct
+            {
+__IOM uint32_t addr     :
+                16;           /*!< [15..0] the short address of short address match entry 10                 */
+__IOM uint32_t panid    :
+                16;           /*!< [31..16] the PAN ID of short address match entry 10                       */
+            } src_short_match10_b;
+        } ;
+
+        union
+        {
+            __IOM uint32_t
+            src_ext_match5_l;          /*!< (@ 0x00000438) Lower 4-bytes of Extended Source Address Match
+                                                                    Filter Entry 5                                             */
+
+            struct
+            {
+__IOM uint32_t ext_addr_l :
+                32;         /*!< [31..0] the lower 4-bytes of extended address of extended address
+                                                     match entry 5                                                             */
+            } src_ext_match5_l_b;
+        } ;
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t
+            src_short_match11;         /*!< (@ 0x0000043C) Short Source Address Match Filter Entry 11                 */
+
+            struct
+            {
+__IOM uint32_t addr     :
+                16;           /*!< [15..0] the short address of short address match entry 11                 */
+__IOM uint32_t panid    :
+                16;           /*!< [31..16] the PAN ID of short address match entry 11                       */
+            } src_short_match11_b;
+        } ;
+
+        union
+        {
+            __IOM uint32_t
+            src_ext_match5_h;          /*!< (@ 0x0000043C) Higher 4-bytes of Extended Source Address Match
+                                                                    Filter Entry 5                                             */
+
+            struct
+            {
+__IOM uint32_t ext_addr_h :
+                32;         /*!< [31..0] the higher 4-bytes of extended address of extended address
+                                                     match entry 5                                                             */
+            } src_ext_match5_h_b;
+        } ;
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t
+            src_short_match12;         /*!< (@ 0x00000440) Short Source Address Match Filter Entry 12                 */
+
+            struct
+            {
+__IOM uint32_t addr     :
+                16;           /*!< [15..0] the short address of short address match entry 12                 */
+__IOM uint32_t panid    :
+                16;           /*!< [31..16] the PAN ID of short address match entry 12                       */
+            } src_short_match12_b;
+        } ;
+
+        union
+        {
+            __IOM uint32_t
+            src_ext_match6_l;          /*!< (@ 0x00000440) Lower 4-bytes of Extended Source Address Match
+                                                                    Filter Entry 6                                             */
+
+            struct
+            {
+__IOM uint32_t ext_addr_l :
+                32;         /*!< [31..0] the lower 4-bytes of extended address of extended address
+                                                     match entry 6                                                             */
+            } src_ext_match6_l_b;
+        } ;
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t
+            src_short_match13;         /*!< (@ 0x00000444) Short Source Address Match Filter Entry 13                 */
+
+            struct
+            {
+__IOM uint32_t addr     :
+                16;           /*!< [15..0] the short address of short address match entry 13                 */
+__IOM uint32_t panid    :
+                16;           /*!< [31..16] the PAN ID of short address match entry 13                       */
+            } src_short_match13_b;
+        } ;
+
+        union
+        {
+            __IOM uint32_t
+            src_ext_match6_h;          /*!< (@ 0x00000444) Higher 4-bytes of Extended Source Address Match
+                                                                    Filter Entry 6                                             */
+
+            struct
+            {
+__IOM uint32_t ext_addr_h :
+                32;         /*!< [31..0] the higher 4-bytes of extended address of extended address
+                                                     match entry 6                                                             */
+            } src_ext_match6_h_b;
+        } ;
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t
+            src_short_match14;         /*!< (@ 0x00000448) Short Source Address Match Filter Entry 14                 */
+
+            struct
+            {
+__IOM uint32_t addr     :
+                16;           /*!< [15..0] the short address of short address match entry 14                 */
+__IOM uint32_t panid    :
+                16;           /*!< [31..16] the PAN ID of short address match entry 14                       */
+            } src_short_match14_b;
+        } ;
+
+        union
+        {
+            __IOM uint32_t
+            src_ext_match7_l;          /*!< (@ 0x00000448) Lower 4-bytes of Extended Source Address Match
+                                                                    Filter Entry 7                                             */
+
+            struct
+            {
+__IOM uint32_t ext_addr_l :
+                32;         /*!< [31..0] the lower 4-bytes of extended address of extended address
+                                                     match entry 7                                                             */
+            } src_ext_match7_l_b;
+        } ;
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t
+            src_short_match15;         /*!< (@ 0x0000044C) Short Source Address Match Filter Entry 15                 */
+
+            struct
+            {
+__IOM uint32_t addr     :
+                16;           /*!< [15..0] the short address of short address match entry 15                 */
+__IOM uint32_t panid    :
+                16;           /*!< [31..16] the PAN ID of short address match entry 15                       */
+            } src_short_match15_b;
+        } ;
+
+        union
+        {
+            __IOM uint32_t
+            src_ext_match7_h;          /*!< (@ 0x0000044C) Higher 4-bytes of Extended Source Address Match
+                                                                    Filter Entry 7                                             */
+
+            struct
+            {
+__IOM uint32_t ext_addr_h :
+                32;         /*!< [31..0] the higher 4-bytes of extended address of extended address
+                                                     match entry 7                                                             */
+            } src_ext_match7_h_b;
+        } ;
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t
+            src_short_match16;         /*!< (@ 0x00000450) Short Source Address Match Filter Entry 16                 */
+
+            struct
+            {
+__IOM uint32_t addr     :
+                16;           /*!< [15..0] the short address of short address match entry 16                 */
+__IOM uint32_t panid    :
+                16;           /*!< [31..16] the PAN ID of short address match entry 16                       */
+            } src_short_match16_b;
+        } ;
+
+        union
+        {
+            __IOM uint32_t
+            src_ext_match8_l;          /*!< (@ 0x00000450) Lower 4-bytes of Extended Source Address Match
+                                                                    Filter Entry 8                                             */
+
+            struct
+            {
+__IOM uint32_t ext_addr_l :
+                32;         /*!< [31..0] the lower 4-bytes of extended address of extended address
+                                                     match entry 8                                                             */
+            } src_ext_match8_l_b;
+        } ;
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t
+            src_short_match17;         /*!< (@ 0x00000454) Short Source Address Match Filter Entry 17                 */
+
+            struct
+            {
+__IOM uint32_t addr     :
+                16;           /*!< [15..0] the short address of short address match entry 17                 */
+__IOM uint32_t panid    :
+                16;           /*!< [31..16] the PAN ID of short address match entry 17                       */
+            } src_short_match17_b;
+        } ;
+
+        union
+        {
+            __IOM uint32_t
+            src_ext_match8_h;          /*!< (@ 0x00000454) Higher 4-bytes of Extended Source Address Match
+                                                                    Filter Entry 8                                             */
+
+            struct
+            {
+__IOM uint32_t ext_addr_h :
+                32;         /*!< [31..0] the higher 4-bytes of extended address of extended address
+                                                     match entry 7                                                             */
+            } src_ext_match8_h_b;
+        } ;
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t
+            src_short_match18;         /*!< (@ 0x00000458) Short Source Address Match Filter Entry 18                 */
+
+            struct
+            {
+__IOM uint32_t addr     :
+                16;           /*!< [15..0] the short address of short address match entry 18                 */
+__IOM uint32_t panid    :
+                16;           /*!< [31..16] the PAN ID of short address match entry 18                       */
+            } src_short_match18_b;
+        } ;
+
+        union
+        {
+            __IOM uint32_t
+            src_ext_match9_l;          /*!< (@ 0x00000458) Lower 4-bytes of Extended Source Address Match
+                                                                    Filter Entry 9                                             */
+
+            struct
+            {
+__IOM uint32_t ext_addr_l :
+                32;         /*!< [31..0] the lower 4-bytes of extended address of extended address
+                                                     match entry 9                                                             */
+            } src_ext_match9_l_b;
+        } ;
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t
+            src_short_match19;         /*!< (@ 0x0000045C) Short Source Address Match Filter Entry 19                 */
+
+            struct
+            {
+__IOM uint32_t addr     :
+                16;           /*!< [15..0] the short address of short address match entry 19                 */
+__IOM uint32_t panid    :
+                16;           /*!< [31..16] the PAN ID of short address match entry 19                       */
+            } src_short_match19_b;
+        } ;
+
+        union
+        {
+            __IOM uint32_t
+            src_ext_match9_h;          /*!< (@ 0x0000045C) Higher 4-bytes of Extended Source Address Match
+                                                                    Filter Entry 9                                             */
+
+            struct
+            {
+__IOM uint32_t ext_addr_h :
+                32;         /*!< [31..0] the higher 4-bytes of extended address of extended address
+                                                     match entry 9                                                             */
+            } src_ext_match9_h_b;
+        } ;
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t
+            src_short_match20;         /*!< (@ 0x00000460) Short Source Address Match Filter Entry 20                 */
+
+            struct
+            {
+__IOM uint32_t addr     :
+                16;           /*!< [15..0] the short address of short address match entry 20                 */
+__IOM uint32_t panid    :
+                16;           /*!< [31..16] the PAN ID of short address match entry 20                       */
+            } src_short_match20_b;
+        } ;
+
+        union
+        {
+            __IOM uint32_t
+            src_ext_match10_l;         /*!< (@ 0x00000460) Lower 4-bytes of Extended Source Address Match
+                                                                    Filter Entry 10                                            */
+
+            struct
+            {
+__IOM uint32_t ext_addr_l :
+                32;         /*!< [31..0] the lower 4-bytes of extended address of extended address
+                                                     match entry 10                                                            */
+            } src_ext_match10_l_b;
+        } ;
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t
+            src_short_match21;         /*!< (@ 0x00000464) Short Source Address Match Filter Entry 21                 */
+
+            struct
+            {
+__IOM uint32_t addr     :
+                16;           /*!< [15..0] the short address of short address match entry 21                 */
+__IOM uint32_t panid    :
+                16;           /*!< [31..16] the PAN ID of short address match entry 21                       */
+            } src_short_match21_b;
+        } ;
+
+        union
+        {
+            __IOM uint32_t
+            src_ext_match10_h;         /*!< (@ 0x00000464) Higher 4-bytes of Extended Source Address Match
+                                                                    Filter Entry 10                                            */
+
+            struct
+            {
+__IOM uint32_t ext_addr_h :
+                32;         /*!< [31..0] the higher 4-bytes of extended address of extended address
+                                                     match entry 10                                                            */
+            } src_ext_match10_h_b;
+        } ;
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t
+            src_short_match22;         /*!< (@ 0x00000468) Short Source Address Match Filter Entry 22                 */
+
+            struct
+            {
+__IOM uint32_t addr     :
+                16;           /*!< [15..0] the short address of short address match entry 22                 */
+__IOM uint32_t panid    :
+                16;           /*!< [31..16] the PAN ID of short address match entry 22                       */
+            } src_short_match22_b;
+        } ;
+
+        union
+        {
+            __IOM uint32_t
+            src_ext_match11_l;         /*!< (@ 0x00000468) Lower 4-bytes of Extended Source Address Match
+                                                                    Filter Entry 11                                            */
+
+            struct
+            {
+__IOM uint32_t ext_addr_l :
+                32;         /*!< [31..0] the lower 4-bytes of extended address of extended address
+                                                     match entry 11                                                            */
+            } src_ext_match11_l_b;
+        } ;
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t
+            src_short_match23;         /*!< (@ 0x0000046C) Short Source Address Match Filter Entry 23                 */
+
+            struct
+            {
+__IOM uint32_t addr     :
+                16;           /*!< [15..0] the short address of short address match entry 23                 */
+__IOM uint32_t panid    :
+                16;           /*!< [31..16] the PAN ID of short address match entry 23                       */
+            } src_short_match23_b;
+        } ;
+
+        union
+        {
+            __IOM uint32_t
+            src_ext_match11_h;         /*!< (@ 0x0000046C) Higher 4-bytes of Extended Source Address Match
+                                                                    Filter Entry 11                                            */
+
+            struct
+            {
+__IOM uint32_t ext_addr_h :
+                32;         /*!< [31..0] the higher 4-bytes of extended address of extended address
+                                                     match entry 11                                                            */
+            } src_ext_match11_h_b;
+        } ;
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t
+            src_short_match24;         /*!< (@ 0x00000470) Short Source Address Match Filter Entry 24                 */
+
+            struct
+            {
+__IOM uint32_t addr     :
+                16;           /*!< [15..0] the short address of short address match entry 24                 */
+__IOM uint32_t panid    :
+                16;           /*!< [31..16] the PAN ID of short address match entry 24                       */
+            } src_short_match24_b;
+        } ;
+
+        union
+        {
+            __IOM uint32_t
+            src_ext_match12_l;         /*!< (@ 0x00000470) Lower 4-bytes of Extended Source Address Match
+                                                                    Filter Entry 12                                            */
+
+            struct
+            {
+__IOM uint32_t ext_addr_l :
+                32;         /*!< [31..0] the lower 4-bytes of extended address of extended address
+                                                     match entry 12                                                            */
+            } src_ext_match12_l_b;
+        } ;
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t
+            src_short_match25;         /*!< (@ 0x00000474) Short Source Address Match Filter Entry 25                 */
+
+            struct
+            {
+__IOM uint32_t addr     :
+                16;           /*!< [15..0] the short address of short address match entry 25                 */
+__IOM uint32_t panid    :
+                16;           /*!< [31..16] the PAN ID of short address match entry 25                       */
+            } src_short_match25_b;
+        } ;
+
+        union
+        {
+            __IOM uint32_t
+            src_ext_match12_h;         /*!< (@ 0x00000474) Higher 4-bytes of Extended Source Address Match
+                                                                    Filter Entry 12                                            */
+
+            struct
+            {
+__IOM uint32_t ext_addr_h :
+                32;         /*!< [31..0] the higher 4-bytes of extended address of extended address
+                                                     match entry 12                                                            */
+            } src_ext_match12_h_b;
+        } ;
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t
+            src_short_match26;         /*!< (@ 0x00000478) Short Source Address Match Filter Entry 26                 */
+
+            struct
+            {
+__IOM uint32_t addr     :
+                16;           /*!< [15..0] the short address of short address match entry 26                 */
+__IOM uint32_t panid    :
+                16;           /*!< [31..16] the PAN ID of short address match entry 26                       */
+            } src_short_match26_b;
+        } ;
+
+        union
+        {
+            __IOM uint32_t
+            src_ext_match13_l;         /*!< (@ 0x00000478) Lower 4-bytes of Extended Source Address Match
+                                                                    Filter Entry 13                                            */
+
+            struct
+            {
+__IOM uint32_t ext_addr_l :
+                32;         /*!< [31..0] the lower 4-bytes of extended address of extended address
+                                                     match entry 13                                                            */
+            } src_ext_match13_l_b;
+        } ;
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t
+            src_short_match27;         /*!< (@ 0x0000047C) Short Source Address Match Filter Entry 27                 */
+
+            struct
+            {
+__IOM uint32_t addr     :
+                16;           /*!< [15..0] the short address of short address match entry 27                 */
+__IOM uint32_t panid    :
+                16;           /*!< [31..16] the PAN ID of short address match entry 27                       */
+            } src_short_match27_b;
+        } ;
+
+        union
+        {
+            __IOM uint32_t
+            src_ext_match13_h;         /*!< (@ 0x0000047C) Higher 4-bytes of Extended Source Address Match
+                                                                    Filter Entry 13                                            */
+
+            struct
+            {
+__IOM uint32_t ext_addr_h :
+                32;         /*!< [31..0] the higher 4-bytes of extended address of extended address
+                                                     match entry 13                                                            */
+            } src_ext_match13_h_b;
+        } ;
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t
+            src_short_match28;         /*!< (@ 0x00000480) Short Source Address Match Filter Entry 28                 */
+
+            struct
+            {
+__IOM uint32_t addr     :
+                16;           /*!< [15..0] the short address of short address match entry 28                 */
+__IOM uint32_t panid    :
+                16;           /*!< [31..16] the PAN ID of short address match entry 28                       */
+            } src_short_match28_b;
+        } ;
+
+        union
+        {
+            __IOM uint32_t
+            src_ext_match14_l;         /*!< (@ 0x00000480) Lower 4-bytes of Extended Source Address Match
+                                                                    Filter Entry 14                                            */
+
+            struct
+            {
+__IOM uint32_t ext_addr_l :
+                32;         /*!< [31..0] the lower 4-bytes of extended address of extended address
+                                                     match entry 14                                                            */
+            } src_ext_match14_l_b;
+        } ;
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t
+            src_short_match29;         /*!< (@ 0x00000484) Short Source Address Match Filter Entry 29                 */
+
+            struct
+            {
+__IOM uint32_t addr     :
+                16;           /*!< [15..0] the short address of short address match entry 29                 */
+__IOM uint32_t panid    :
+                16;           /*!< [31..16] the PAN ID of short address match entry 29                       */
+            } src_short_match29_b;
+        } ;
+
+        union
+        {
+            __IOM uint32_t
+            src_ext_match14_h;         /*!< (@ 0x00000484) Higher 4-bytes of Extended Source Address Match
+                                                                    Filter Entry 14                                            */
+
+            struct
+            {
+__IOM uint32_t ext_addr_h :
+                32;         /*!< [31..0] the higher 4-bytes of extended address of extended address
+                                                     match entry 14                                                            */
+            } src_ext_match14_h_b;
+        } ;
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t
+            src_short_match30;         /*!< (@ 0x00000488) Short Source Address Match Filter Entry 30                 */
+
+            struct
+            {
+__IOM uint32_t addr     :
+                16;           /*!< [15..0] the short address of short address match entry 30                 */
+__IOM uint32_t panid    :
+                16;           /*!< [31..16] the PAN ID of short address match entry 30                       */
+            } src_short_match30_b;
+        } ;
+
+        union
+        {
+            __IOM uint32_t
+            src_ext_match15_l;         /*!< (@ 0x00000488) Lower 4-bytes of Extended Source Address Match
+                                                                    Filter Entry 15                                            */
+
+            struct
+            {
+__IOM uint32_t ext_addr_l :
+                32;         /*!< [31..0] the lower 4-bytes of extended address of extended address
+                                                     match entry 15                                                            */
+            } src_ext_match15_l_b;
+        } ;
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t
+            src_short_match31;         /*!< (@ 0x0000048C) Short Source Address Match Filter Entry 31                 */
+
+            struct
+            {
+__IOM uint32_t addr     :
+                16;           /*!< [15..0] the short address of short address match entry 31                 */
+__IOM uint32_t panid    :
+                16;           /*!< [31..16] the PAN ID of short address match entry 31                       */
+            } src_short_match31_b;
+        } ;
+
+        union
+        {
+            __IOM uint32_t
+            src_ext_match15_h;         /*!< (@ 0x0000048C) Higher 4-bytes of Extended Source Address Match
+                                                                    Filter Entry 15                                            */
+
+            struct
+            {
+__IOM uint32_t ext_addr_h :
+                32;         /*!< [31..0] the higher 4-bytes of extended address of extended address
+                                                     match entry 15                                                            */
+            } src_ext_match15_h_b;
+        } ;
+    };
+    __IM  uint32_t  RESERVED5[28];
+
+    union
+    {
+        __IOM uint32_t
+        seccr0;                      /*!< (@ 0x00000500) Security Engine Control Register 0                         */
+
+        struct
+        {
+__IOM uint32_t txncipher  :
+            3;            /*!< [2..0] TX Normal FIFO Security Suite Select: 000: (default)
+                                                     Undefined; 001: AES-ENC; 010: AES-ENC-MIC-128; 011: AES-ENC-MIC-64;
+                                                     100: AES-ENC-MIC-32; 101: AES-MIC-128; 110: AES-MIC-64;
+                                                     111: AES-MIC-32;                                                          */
+__IOM uint32_t rxcipher   :
+            3;            /*!< [5..3] RX FIFO Security Suite Select: 000: (default) Undefined;
+                                                     001: AES-ENC; 010: AES-ENC-MIC-128; 011: AES-ENC-MIC-64;
+                                                     100: AES-ENC-MIC-32; 101: AES-MIC-128; 110: AES-MIC-64;
+                                                     111: AES-MIC-32;                                                          */
+__OM  uint32_t secstart   :
+            1;            /*!< [6..6] RX Security Decryption Start: 1: Start decryption process.
+                                                     Bit is automatically cleared to '0' by hardware                           */
+__OM  uint32_t secignore  :
+            1;            /*!< [7..7] RX Security Decryption Ignore: 1: Ignore decryption process.
+                                                     Bit is automatically cleared to '0' by hardware                           */
+__IOM uint32_t disenc     :
+            1;            /*!< [8..8] Disable Encryption Function: 0: (default) Enable encryption
+                                                     function; 1: Disable the encryption process. The MAC TXM
+                                                     does not encrypt the data, even if the TX security is enabled             */
+__IOM uint32_t disdec     :
+            1;            /*!< [9..9] Disable Decryption Function: 0: (default) Enable decryption
+                                                     process; 1: Disable the decryption process. The MAC RXM
+                                                     does not generate a security interrupt, even if 'security'
+                                                     bit in the MAC header is detected                                         */
+            uint32_t            : 6;
+__IOM uint32_t txbcipher  :
+            3;            /*!< [18..16] TXBCIPHER: TX Beacon FIFO Security Suite Select: 000:
+                                                     (default) Undefined; 001: AES-ENC; 010: AES-ENC-MIC-128;
+                                                     011: AES-ENC-MIC-64; 100: AES-ENC-MIC-32; 101: AES-MIC-128;
+                                                     110: AES-MIC-64; 111: AES-MIC-32;                                         */
+            uint32_t            : 5;
+__IOM uint32_t txg1cipher :
+            3;            /*!< [26..24] TX GTS1 FIFO Security Suite Select: 000: (default)
+                                                     Undefined; 001: AES-ENC; 010: AES-ENC-MIC-128; 011: AES-ENC-MIC-64;
+                                                     100: AES-ENC-MIC-32; 101: AES-MIC-128; 110: AES-MIC-64;
+                                                     111: AES-MIC-32;                                                          */
+__IOM uint32_t txg2cipher :
+            3;            /*!< [29..27] TX GTS2 FIFO Security Suite Select: 000: (default)
+                                                     Undefined; 001: AES-ENC; 010: AES-ENC-MIC-128; 011: AES-ENC-MIC-64;
+                                                     100: AES-ENC-MIC-32; 101: AES-MIC-128; 110: AES-MIC-64;
+                                                     111: AES-MIC-32;                                                          */
+            uint32_t            : 2;
+        } seccr0_b;
+    } ;
+
+    union
+    {
+        __IOM uint32_t
+        seccr1;                      /*!< (@ 0x00000504) Security Engine Control Register 1                         */
+
+        struct
+        {
+__IOM uint32_t usrflag    :
+            1;            /*!< [0..0] User Defined Flag and initial Counter: 0: (default) Disable;
+                                                     1: Enable; User-defined flag is defined in ENCFLG(0x004[15:8])
+                                                     and AUTFLG(0x004[23:16]). User-defined counter is defined
+                                                     in LREG0x27A and LREG0x27B.                                               */
+__IOM uint32_t sec_2006   :
+            1;            /*!< [1..1] Enable IEEE802.15.4-2006-compliant Block Cipher Mode:
+                                                     0: (default) Disable; 1: Enable                                           */
+__IOM uint32_t aes_only   :
+            1;            /*!< [2..2] Trigger AES only mode. SW should set it '0' to come back.
+                                                     Trigger when '0' to '1'                                                   */
+            uint32_t            : 5;
+__IOM uint32_t encflg     :
+            8;            /*!< [15..8] Encryption Flag. User-defined flag for encryption in
+                                                     CCM/CCM* mode of Upper Cipher operation. Only works when
+                                                     USRFLAG (0x504[0]) = '1'. 00000000: (default)                             */
+__IOM uint32_t autflg     :
+            8;            /*!< [23..16] Authentication Flag. User-defined flag for authentication
+                                                     in CBC-MAC mode of Upper Cipher operation. Only works when
+                                                     USRFLAG (0x504[0]) = '1'. 00000000: (default)                             */
+            uint32_t            : 8;
+        } seccr1_b;
+    } ;
+
+    union
+    {
+        __IOM uint32_t
+        sec_upper_ctrl;              /*!< (@ 0x00000508) Upper Layer Security Control Register                      */
+
+        struct
+        {
+__IOM uint32_t upenc      :
+            1;            /*!< [0..0] Upper Layer Security Encryption Mode: 1: Perform upper
+                                                     layer encryption using TX Normal FIFO. Bit is automatically
+                                                     cleared to '0' by hardware.                                               */
+__IOM uint32_t updec      :
+            1;            /*!< [1..1] Upper Layer Security Decryption Mode: 1: Perform upper
+                                                     layer decryption using TX Normal FIFO. Bit is automatically
+                                                     cleared to '0' by hardware.                                               */
+            uint32_t            : 30;
+        } sec_upper_ctrl_b;
+    } ;
+
+    union
+    {
+        __IOM uint32_t
+        sec_proc_sts;                /*!< (@ 0x0000050C) Security Process Status Register                           */
+
+        struct
+        {
+__IOM uint32_t sec_enc_done :
+            1;          /*!< [0..0] security engine process done indicator, write 1 clear:
+                                                     0: (default) Security engine process is not started or
+                                                     not done yet; 1: security engine process is done; FW write
+                                                     1 to clear this bit before start a new security engine
+                                                     process                                                                   */
+__IOM uint32_t upsecerr   :
+            1;            /*!< [1..1] MIC Error in Upper Layer Security Mode: 0: (default)
+                                                     MIC error did not occur; 1: MIC error occurred. Write '1'
+                                                     to clear                                                                  */
+            uint32_t            : 6;
+__IM  uint32_t txsecdone  :
+            1;            /*!< [8..8] Tx frame encryption process done status: 0: data encryption
+                                                     process is running; 1: data encryption is done (or data
+                                                     encryption is not triggered). FW can know whether the security
+                                                     HW engine is doing data encryption or not by read this
+                                                     bit. Ex. A secure frame transmission is failed due to the
+                                                     PHY grant is lost, FW can re-trigger the transmission when
+                                                     PHY is re-granted if the frame data encryption is done.                   */
+__IM  uint32_t secdecerr  :
+            1;            /*!< [9..9] Security decryption error. Security engine set this bit
+                                                     as 1 to indicate the RX decryption is finished with MIC
+                                                     check error.                                                              */
+__IM  uint32_t sec_upper_enclerr :
+            1;     /*!< [10..10] Security engine will set this bit as 1 to indicate
+                                                     the error of Frame length or Header length is 0 when doing
+                                                     upper layer encryption                                                    */
+            uint32_t            : 5;
+__IM  uint32_t aes_only_rdy :
+            1;          /*!< [16..16] AES only mode complete. Setting AES_ONLY bit clears
+                                                     the status. Report '1' when complete AES process                          */
+            uint32_t            : 15;
+        } sec_proc_sts_b;
+    } ;
+
+    union
+    {
+        __IM  uint32_t
+        sec_sts_stccmp;              /*!< (@ 0x00000510) Security State and Status Register                         */
+
+        struct
+        {
+__IM  uint32_t scu_cs     :
+            3;            /*!< [2..0] Security current state                                             */
+__IM  uint32_t parse_cs   :
+            3;            /*!< [5..3] Parser current state                                               */
+__IM  uint32_t key_sr_cs  :
+            2;            /*!< [7..6] Key search current state                                           */
+__IM  uint32_t st_ccmp    :
+            4;            /*!< [11..8] CTR/CCM/CBC-MAC current state                                     */
+            uint32_t            : 20;
+        } sec_sts_stccmp_b;
+    } ;
+
+    union
+    {
+        __IOM uint32_t
+        sec_par_order;               /*!< (@ 0x00000514) Security Parameters Bytes Order Control Register           */
+
+        struct
+        {
+__IOM uint32_t extadr_odr :
+            1;            /*!< [0..0] For security, device's extension address order setting.
+                                                     Setting this bit reverses extension address byte order                    */
+__IOM uint32_t rxmadr_odr :
+            1;            /*!< [1..1] For security, receiver extension address order. Setting
+                                                     this bit reverses extension address byte order                            */
+__IOM uint32_t frmctr_odr :
+            1;            /*!< [2..2] For security, frame counter field order. Setting this
+                                                     bit reverses frame counter byte order                                     */
+            uint32_t            : 29;
+        } sec_par_order_b;
+    } ;
+
+    union
+    {
+        __IOM uint32_t
+        upnonce_0_3;                 /*!< (@ 0x00000518) Upper Security Nonce Bytes 0 ~ 3                           */
+
+        struct
+        {
+__IOM uint32_t upnonce    :
+            32;           /*!< [31..0] bits[31:0] of 104-Bit Upper NONCE Value                           */
+        } upnonce_0_3_b;
+    } ;
+
+    union
+    {
+        __IOM uint32_t
+        upnonce_4_7;                 /*!< (@ 0x0000051C) Upper Security Nonce Bytes 4 ~ 7                           */
+
+        struct
+        {
+__IOM uint32_t upnonce    :
+            32;           /*!< [31..0] bits[63:32] of 104-Bit Upper NONCE Value                          */
+        } upnonce_4_7_b;
+    } ;
+
+    union
+    {
+        __IOM uint32_t
+        upnonce_8_11;                /*!< (@ 0x00000520) Upper Security Nonce Bytes 8 ~ 11                          */
+
+        struct
+        {
+__IOM uint32_t upnonce    :
+            32;           /*!< [31..0] bits[95:64] of 104-Bit Upper NONCE Value                          */
+        } upnonce_8_11_b;
+    } ;
+
+    union
+    {
+        __IOM uint32_t
+        upnonce_12;                  /*!< (@ 0x00000524) Upper Security Nonce Byte 12                               */
+
+        struct
+        {
+__IOM uint32_t upnonce    :
+            8;            /*!< [7..0] bits[103:96] of 104-Bit Upper NONCE Value                          */
+            uint32_t            : 24;
+        } upnonce_12_b;
+    } ;
+
+    union
+    {
+        __IOM uint32_t
+        sec_initcntl;                /*!< (@ 0x00000528) Security Engine AES-CBC Initial Counter Value              */
+
+        struct
+        {
+__IOM uint32_t initcnt    :
+            16;           /*!< [15..0] User defined Frame Counter Initial value. User-defined
+                                                     initial counter for Upper Cipher operation. Only works
+                                                     when USRFLAG (0x004[0]) = '1'.                                            */
+            uint32_t            : 16;
+        } sec_initcntl_b;
+    } ;
+    __IM  uint32_t  RESERVED6[21];
+
+    union
+    {
+        __IOM uint32_t
+        tx_set;                      /*!< (@ 0x00000580) PHY TX Set Control Register                                */
+
+        struct
+        {
+__IOM uint32_t txagc      :
+            8;            /*!< [7..0] TX Gain ControlTBD: output power mapping table                     */
+__IOM uint32_t sel_tpm    :
+            1;            /*!< [8..8] TX pattern format before TX On:1: TPM modulation0: IQM
+                                                     modulation                                                                */
+__IOM uint32_t lna_en     :
+            1;            /*!< [9..9] enable external LNA for Zigbee                                     */
+            uint32_t            : 2;
+__IOM uint32_t en_early_txon_tgl :
+            1;     /*!< [12..12] TX pattern format before TX On:1: 10b0: tail of previous
+                                                     TX packet                                                                 */
+__IOM uint32_t radio_off  :
+            1;            /*!< [13..13] radio off indication: 0: radio on; 1(default): radio
+                                                     off, FW use this bit to indicate MAC HW that the RF is
+                                                     un-accessable due to the RF is under certen condition,
+                                                     like RF calibration                                                       */
+__IOM uint32_t prestby_dly_zb :
+            3;        /*!< [16..14] the time delay for PHY entering standby state from
+                                                     idle state, in 1us, this field is valid when prestdby_dly_en
+                                                     = 1                                                                       */
+__IOM uint32_t preturnon_delay_zb :
+            5;    /*!< [21..17] the time delay for PHY entering turn-on state from
+                                                     standby state, in 1us                                                     */
+__IOM uint32_t rampstby_delay_zb :
+            5;     /*!< [26..22] the time delay for PHY entering standby state, in 1us            */
+__IOM uint32_t sd_pos_delay_zb :
+            4;       /*!< [30..27] the time delay for PHY TX Turning off entering PHY
+                                                     Off state, in unit of 1us                                                 */
+__IOM uint32_t tx_bkprg0_en :
+            1;          /*!< [31..31] TX backup0 programming enable                                    */
+        } tx_set_b;
+    } ;
+
+    union
+    {
+        __IOM uint32_t
+        rx_set;                      /*!< (@ 0x00000584) PHY RX Set Control Register                                */
+
+        struct
+        {
+__IOM uint32_t dis_rf_ps  :
+            1;            /*!< [0..0] disable RF shut-down power saving: RF do not enter shout-down
+                                                     mode and keep in standby mode when idle                                   */
+__IOM uint32_t prestby_dly_en :
+            1;        /*!< [1..1] enable time delay for PHY entering standby state                   */
+__IOM uint32_t cca_threshold :
+            4;         /*!< [5..2] CCA CS mode threashold for channel busy detection, not
+                                                     use currently (FW will write the threshold value to the
+                                                     BB register directly)                                                     */
+__IOM uint32_t cca_ed_threshold :
+            8;      /*!< [13..6] CCA energy detection mode threashold for channel busy
+                                                     detection, not use currently (FW will write the threshold
+                                                     value to the BB register directly)                                        */
+            uint32_t            : 2;
+__IOM uint32_t txon_early :
+            6;            /*!< [21..16] the time between RIF_TX_ON and TX_PKT                            */
+__IOM uint32_t cca_mode   :
+            2;            /*!< [23..22] Clear Channel Assessment (CCA) Mode Select: 00: Disable
+                                                     CCA mode(normal data RX); 01: Energy detection (ED) mode,
+                                                     which detects in-band signals; 10: Carrier sense (CS) mode,
+                                                     which detects IEEE 802.15.4 signals; 11: Combination of
+                                                     carrier sense mode and energy detection mode;                             */
+__IOM uint32_t standby_pg_adress :
+            8;     /*!< [31..24] register address for resume register programing                  */
+        } rx_set_b;
+    } ;
+
+    union
+    {
+        __IOM uint32_t
+        phy_trx_dly;                 /*!< (@ 0x00000588) PHY TX/RX Delay Control Register                           */
+
+        struct
+        {
+__IOM uint32_t txon_delay :
+            8;            /*!< [7..0] when txrx_timing is from initial to initial tx(such as
+                                                     tx beacon), the wait time for tx rfup                                     */
+__IOM uint32_t rxon_delay :
+            8;            /*!< [15..8] when txrx_timing is from initial to initial rx or from
+                                                     tx to received-ack rx, the wait time for rx rfup. In unit
+                                                     of 1us.                                                                   */
+__IOM uint32_t cca_rxon_delay :
+            8;        /*!< [23..16] when txrx_timing is from rx to cca rx, the wait time
+                                                     for cca rx rfup. In unit of 1us                                           */
+__IOM uint32_t rx2rx_delay :
+            8;           /*!< [31..24] when txrx_timing is from rx to rx, the wait time for
+                                                     rx rfup. In unit of 1us.                                                  */
+        } phy_trx_dly_b;
+    } ;
+
+    union
+    {
+        __IOM uint32_t
+        phy_to_dly;                  /*!< (@ 0x0000058C) PHY Timeout and Delay Control Register                     */
+
+        struct
+        {
+__IOM uint32_t rx_timeout_delay :
+            8;      /*!< [7..0] when txrx_timing is in normal rx(rx on for receiving
+                                                     packet), the timeout for rx on, reserved for future                       */
+__IOM uint32_t cca_rx_timeout_delay :
+            8;  /*!< [15..8] when txrx_timing is in cca rx, the timeout for cca processing,
+                                                     reserved for future                                                       */
+__IOM uint32_t rx2tx_delay :
+            8;           /*!< [23..16] when txrx_timing is from rx to tx, the wait time for
+                                                     tx rfup                                                                   */
+__IOM uint32_t tx2rx_delay :
+            8;           /*!< [31..24] when txrx_timing is from tx to rx, the wait time for
+                                                     rx rfup                                                                   */
+        } phy_to_dly_b;
+    } ;
+
+    union
+    {
+        __IOM uint32_t
+        tx_prg_reg_0;                /*!< (@ 0x00000590) MAC TX backup register 0                                   */
+
+        struct
+        {
+__IOM uint32_t standby_pg_data :
+            16;      /*!< [15..0] the PHY register programming data when PHY enternign
+                                                     standby state                                                             */
+__IOM uint32_t tx_bkprg0_pg_data :
+            16;    /*!< [31..16] PHY 'TX register backup 0 programming data                       */
+        } tx_prg_reg_0_b;
+    } ;
+
+    union
+    {
+        __IOM uint32_t
+        tx_prg_reg_1;                /*!< (@ 0x00000594) MAC TX backup register 1                                   */
+
+        struct
+        {
+__IOM uint32_t tx_bkprg2_pg_data :
+            16;    /*!< [15..0] PHY 'TX register backup 2 programming data                        */
+__IOM uint32_t tx_bkprg1_pg_data :
+            16;    /*!< [31..16] PHY 'TX register backup 1 programming data                       */
+        } tx_prg_reg_1_b;
+    } ;
+
+    union
+    {
+        __IOM uint32_t
+        tx_prg_reg_2;                /*!< (@ 0x00000598) MAC TX backup register 2                                   */
+
+        struct
+        {
+__IOM uint32_t tx_bkprg0_pg_addr :
+            8;     /*!< [7..0] PHY TX register backup 0 programming address                       */
+__IOM uint32_t tx_bkprg1_pg_addr :
+            8;     /*!< [15..8] PHY TX register backup 1 programming address                      */
+__IOM uint32_t tx_bkprg2_pg_addr :
+            8;     /*!< [23..16] PHY TX register backup 2 programming address                     */
+__IOM uint32_t tx_bkprg1_en :
+            1;          /*!< [24..24] tx backup programming1 enable; it programmed start
+                                                     from radio GAIN state in order(bkprg0 first, and bkprg1/2
+                                                     as following) by HW:0: disable; 1:enable                                  */
+__IOM uint32_t tx_bkprg2_en :
+            1;          /*!< [25..25] tx backup programming2 enable; it programmed start
+                                                     from radio GAIN state in order(bkprg0->bkprg1->bkprg2)
+                                                     by HW: 0: disable; 1:enable                                               */
+__IOM uint32_t rx_bkprg0_en :
+            1;          /*!< [26..26] rx backup programming0 enable; it programmed in order(bkprg0->bkprg1-
+                                                     bkprg2) by HW:0: disable; 1:enable                                        */
+__IOM uint32_t rx_bkprg1_en :
+            1;          /*!< [27..27] rx backup programming1 enable; it programmed in order(bkprg0
+                                                     first, and bkprg1/2 as following) by HW: 0: disable; 1:enable             */
+__IOM uint32_t rx_bkprg2_en :
+            1;          /*!< [28..28] rx backup programming2 enable; it programmed in order(bkprg0
+                                                     first, and bkprg1/2 as following) by HW: 0: disable; 1:enable             */
+__IOM uint32_t rx_bkprg0_mode_en :
+            1;     /*!< [29..29] rx backup programming0 mode enable;mode enable indicator
+                                                     the programming setting is before RECV or after RECV state;
+                                                     0: before RECV; 1: after RECV                                             */
+__IOM uint32_t rx_bkprg1_mode_en :
+            1;     /*!< [30..30] rx backup programming1 mode enable;mode enable indicator
+                                                     the programming setting is before RECV or after RECV state;0:
+                                                     before RECV; 1: after RECV                                                */
+__IOM uint32_t rx_bkprg2_mode_en :
+            1;     /*!< [31..31] rx backup programming2 mode enable;mode enable indicator
+                                                     the programming setting is before RECV or after RECV state;
+                                                     0: before RECV; 1: after RECV                                             */
+        } tx_prg_reg_2_b;
+    } ;
+
+    union
+    {
+        __IOM uint32_t
+        rx_prg_reg_0;                /*!< (@ 0x0000059C) MAC RX backup register 0                                   */
+
+        struct
+        {
+__IOM uint32_t rx_bkprg0_pg_data :
+            16;    /*!< [15..0] PHY RX register backup 0 programming data                         */
+__IOM uint32_t rx_bkprg1_pg_data :
+            16;    /*!< [31..16] PHY RX register backup 1 programming data                        */
+        } rx_prg_reg_0_b;
+    } ;
+
+    union
+    {
+        __IOM uint32_t
+        rx_prg_reg_1;                /*!< (@ 0x000005A0) MAC RX backup register 1                                   */
+
+        struct
+        {
+__IOM uint32_t rx_bkprg2_pg_data :
+            16;    /*!< [15..0] PHY RX register backup 2 programming data                         */
+__IOM uint32_t rx_bkprg0_pg_addr :
+            8;     /*!< [23..16] PHY RX register backup 0 programming address                     */
+__IOM uint32_t rx_bkprg1_pg_addr :
+            8;     /*!< [31..24] PHY RX register backup 1 programming address                     */
+        } rx_prg_reg_1_b;
+    } ;
+
+    union
+    {
+        union
+        {
+            __IM  uint32_t
+            rx_prg_reg_2r;             /*!< (@ 0x000005A4) MAC/PHY RX backup register 2                               */
+
+            struct
+            {
+__IM  uint32_t rx_bkprg2_pg_addr :
+                8;   /*!< [7..0] PHY RX register backup 2 programming address                       */
+__IM  uint32_t channel  :
+                7;            /*!< [14..8] Channel Number: IEEE 802.15.4 2.4GHz band channels:
+                                                     Channel Frq. = 2402 MHz + channel (MHz)                                   */
+__IM  uint32_t opt_cca_ed_or :
+                1;       /*!< [15..15] 1: use phy_cca_busy equals ed_busy or cca busy when
+                                                     cca_mode equals 3 ; 0 : use phy_cca_busy equals ed_busy
+                                                     and cca busy when cca_mode equals 3                                       */
+__IM  uint32_t bkrpt0_read_data :
+                16;   /*!< [31..16] PHY register report 0 read data                                  */
+            } rx_prg_reg_2r_b;
+        } ;
+
+        union
+        {
+            __OM  uint32_t
+            rx_prg_reg_2w;             /*!< (@ 0x000005A4) MAC/PHY RX backup register 2                               */
+
+            struct
+            {
+__OM  uint32_t rx_bkprg2_pg_addr :
+                8;   /*!< [7..0] PHY RX register backup 2 programming address                       */
+__OM  uint32_t channel  :
+                7;            /*!< [14..8] Channel Number: IEEE 802.15.4 2.4GHz band channels:
+                                                     Channel Frq. = 2402 MHz + channel (MHz)                                   */
+__OM  uint32_t opt_cca_ed_or :
+                1;       /*!< [15..15] 1: use phy_cca_busy equals ed_busy or cca busy when
+                                                     cca_mode equals 3 ; 0 : use phy_cca_busy equals ed_busy
+                                                     and cca busy when cca_mode equals 3                                       */
+__OM  uint32_t bkrpt0_reg_addr :
+                8;     /*!< [23..16] PHY register report 0 address. Set bit 7 = 0 for register
+                                                     read                                                                      */
+__OM  uint32_t bkrpt0_en :
+                1;           /*!< [24..24] rx backup report0 enable; it programmed only after
+                                                     RECV and report it in order(bkrpt0 first, and bkrpt1/2/3/4
+                                                     as following) by HW: 0: disable; 1:enable                                 */
+                uint32_t          : 7;
+            } rx_prg_reg_2w_b;
+        } ;
+    };
+
+    union
+    {
+        union
+        {
+            __IM  uint32_t
+            rx_bkrpt0r;                /*!< (@ 0x000005A8) PHY RX backup register 0                                   */
+
+            struct
+            {
+__IM  uint32_t bkrpt2_read_data :
+                16;   /*!< [15..0] PHY register report 2 read data                                   */
+__IM  uint32_t bkrpt1_read_data :
+                16;   /*!< [31..16] PHY register report 1 read data                                  */
+            } rx_bkrpt0r_b;
+        } ;
+
+        union
+        {
+            __OM  uint32_t
+            rx_bkrpt0w;                /*!< (@ 0x000005A8) PHY RX backup register 0                                   */
+
+            struct
+            {
+__OM  uint32_t bkrpt2_reg_addr :
+                8;     /*!< [7..0] PHY register report 2 address. Set bit 7 = 0 for register
+                                                     read.                                                                     */
+__OM  uint32_t bkrpt2_en :
+                1;           /*!< [8..8] rx backup report2 enable; it programmed only after RECV
+                                                     and report it in order(bkrpt0 first, and bkrpt1/2/3/4 as
+                                                     following) by HW:0: disable; 1:enable                                     */
+                uint32_t          : 7;
+__OM  uint32_t bkrpt1_reg_addr :
+                8;     /*!< [23..16] PHY register report 1 address. Set bit 7 = 0 for register
+                                                     read.                                                                     */
+__OM  uint32_t bkrpt1_en :
+                1;           /*!< [24..24] rx backup report1 enable; it programmed only after
+                                                     RECV and report it in order(bkrpt0 first, and bkrpt1/2/3/4
+                                                     as following) by HW:0: disable; 1:enable                                  */
+                uint32_t          : 7;
+            } rx_bkrpt0w_b;
+        } ;
+    };
+
+    union
+    {
+        union
+        {
+            __IM  uint32_t
+            rx_bkrpt1r;                /*!< (@ 0x000005AC) PHY RX backup register 1                                   */
+
+            struct
+            {
+__IM  uint32_t bkrpt4_read_data :
+                16;   /*!< [15..0] PHY register report 4 read data                                   */
+__IM  uint32_t bkrpt3_read_data :
+                16;   /*!< [31..16] PHY register report 3 read data                                  */
+            } rx_bkrpt1r_b;
+        } ;
+
+        union
+        {
+            __OM  uint32_t
+            rx_bkrpt1w;                /*!< (@ 0x000005AC) PHY RX backup register 1                                   */
+
+            struct
+            {
+__OM  uint32_t bkrpt4_reg_addr :
+                8;     /*!< [7..0] PHY register report 4 address. Set bit 7 = 0 for register
+                                                     read.                                                                     */
+__OM  uint32_t bkrpt4_en :
+                1;           /*!< [8..8] rx backup report4 enable; it programmed only after RECV
+                                                     and report it in order(bkrpt0 first, and bkrpt1/2/3/4 as
+                                                     following) by HW:0: disable; 1:enable                                     */
+                uint32_t          : 7;
+__OM  uint32_t bkrpt3_reg_addr :
+                8;     /*!< [23..16] PHY register report 3 address. Set bit 7 = 0 for register
+                                                     read.                                                                     */
+__OM  uint32_t bkrpt3_en :
+                1;           /*!< [24..24] rx backup report3 enable; it programmed only after
+                                                     RECV and report it in order(bkrpt0 first, and bkrpt1/2/3/4
+                                                     as following) by HW:0: disable; 1:enable                                  */
+                uint32_t          : 7;
+            } rx_bkrpt1w_b;
+        } ;
+    };
+
+    union
+    {
+        __IOM uint32_t
+        phy_early_afe;               /*!< (@ 0x000005B0) PHY Early Analog Fron End On Time Control Register         */
+
+        struct
+        {
+__IOM uint32_t rxon_early_afe :
+            8;        /*!< [7..0] time to eraly trun on RF before entering RX ON state               */
+__IOM uint32_t txon_early_afe :
+            8;        /*!< [15..8] time to eraly trun on RF before entering TX ON state              */
+__IOM uint32_t rampdown_delay_zb :
+            6;     /*!< [21..16] the time delay for PHY entering ramp-standby state
+                                                     from TRAN state, in 1us                                                   */
+            uint32_t            : 10;
+        } phy_early_afe_b;
+    } ;
+
+    union
+    {
+        __IOM uint32_t
+        mac_rf_state;                /*!< (@ 0x000005B4) RF State Indication Register for MAC-PHY interface         */
+
+        struct
+        {
+__IM  uint32_t txrx_cst   :
+            5;            /*!< [4..0] TX/RX current state                                                */
+__IM  uint32_t radio_cst  :
+            5;            /*!< [9..5] Radio current state0: IDLE; 6: PRETURNON; 7: RECV;                 */
+__IOM uint32_t dbg_sel    :
+            4;            /*!< [13..10] debug port selection bit[3:0], bit[4] at REG0x5B4[24]zb_rf_debug
+                                                     port select: 0: tx/rx state machine debug port 0 1: tx/rx
+                                                     state machine debug port 1 2: radio state machine debug
+                                                     port 0 3: radio state machine debug port 1 4: radio state
+                                                     machine debug port 2 5: radio state machine debug port
+                                                     3                                                                         */
+__IM  uint32_t zb_rx_hit_flg :
+            1;         /*!< [14..14] latch zb_rx_hit , and be cleared when leave RX state(for
+                                                     debug)                                                                    */
+__IM  uint32_t rxframe    :
+            1;            /*!< [15..15] latch rxm enable(for debug)                                      */
+__IM  uint32_t rxlength   :
+            7;            /*!< [22..16] the frame length of receiving frame, it will be cleared
+                                                     on next RXON (for debug)                                                  */
+__IM  uint32_t zb_rx_full_and_hit_flg :
+            1;/*!< [23..23] latch zb_rx_hit and rxfifo_full2(for debug)                      */
+__IOM uint32_t dbg_sel_b4 :
+            1;            /*!< [24..24] bit4 of dbg_sel                                                  */
+__IM  uint32_t zb_lut_state :
+            2;          /*!< [26..25] PHY arbitration state with BT BR/EDR concurrent (for
+                                                     debug)when PHY is granted, TXM/RXM/Radio state will wait
+                                                     le_block = 0                                                              */
+            uint32_t            : 5;
+        } mac_rf_state_b;
+    } ;
+
+    union
+    {
+        __IM  uint32_t
+        dbg_sig;                     /*!< (@ 0x000005B8) Signal Latch for Debug                                     */
+
+        struct
+        {
+__IM  uint32_t zb_rx_hit_cnt :
+            16;        /*!< [15..0] zb_rx_hit count, increase 1 on every zb_rx_hit. Write
+                                                     1 to gr_dbg_cnt_reset_o (reg 0x90[5]) to clear this count.                */
+            uint32_t            : 16;
+        } dbg_sig_b;
+    } ;
+
+    union
+    {
+        __IM  uint32_t
+        cca_dbg;                     /*!< (@ 0x000005BC) CCA Machine signal latch for debug register                */
+
+        struct
+        {
+__IM  uint32_t zb_cca_rpt :
+            4;            /*!< [3..0] latch zb_cca_rpt for debugging                                     */
+__IM  uint32_t zb_ed_rpt  :
+            8;            /*!< [11..4] latch zb_ed_rpt for debugging                                     */
+__IM  uint32_t rx_cca_duration :
+            1;       /*!< [12..12] latch rx_cca_duration for debugging                              */
+__IM  uint32_t not_cca_turn_tx :
+            1;       /*!< [13..13] latch not_cca_trun_tx for debugging                              */
+__IM  uint32_t not_cca_turn_rx :
+            1;       /*!< [14..14] latch not_cca_trun_rx for debugging                              */
+__IM  uint32_t phy_cca_i  :
+            1;            /*!< [15..15] latch phy_cca_i for debugging                                    */
+__IM  uint32_t txm_txpe   :
+            1;            /*!< [16..16] latch txm_txpe for debugging                                     */
+__IM  uint32_t no_cca_vld_flg :
+            1;        /*!< [17..17] latch no_cca_vld_flg for debugging                               */
+            uint32_t            : 14;
+        } cca_dbg_b;
+    } ;
+
+    union
+    {
+        __IM  uint32_t
+        cca_dbg1;                    /*!< (@ 0x000005C0) CCA Machine signal latch for debug register                */
+
+        struct
+        {
+__IM  uint32_t zb_rx_cca_cnt :
+            16;        /*!< [15..0] CCA process count, increase 1 on every CCA process start.
+                                                     Write 1 to reg 0x63[6] to clear this count.                               */
+__IM  uint32_t zb_cca_vld_cnt :
+            16;       /*!< [31..16] zb_cca_vld count, increase 1 on every zb_cca_vld. Write
+                                                     1 to reg 0x63[6] to clear this count.                                     */
+        } cca_dbg1_b;
+    } ;
+
+    union
+    {
+        __IOM uint32_t
+        rx_set1;                     /*!< (@ 0x000005C4) PHY RX Setup Control Register1                             */
+
+        struct
+        {
+__IOM uint32_t rx_min_len :
+            3;            /*!< [2..0] set the minimum frame length of RX Filter. Frame_length
+                                                     < rx_min_len will not be received.                                        */
+__IOM uint32_t rxon_off_dly :
+            7;          /*!< [9..3] in us, last phy_rxrdy to rxm_frm end time duration and
+                                                     add a little delay                                                        */
+__IOM uint32_t rxon2ccadt_dly :
+            4;        /*!< [13..10] in us, means rxon to csma_state==CCADT delay, used
+                                                     in scheduled TX mode.                                                     */
+            uint32_t            : 2;
+__IOM uint32_t ed_scan_rxon_delay :
+            8;    /*!< [23..16] in us, means rxon to ED Scan start delay                         */
+__IOM uint32_t rx2tx_imm_ack_delay :
+            8;   /*!< [31..24] in us, RX to TX delay for Imm-Ack TX.                            */
+        } rx_set1_b;
+    } ;
+
+    union
+    {
+        __IOM uint32_t
+        tx_enh_ack_ctrl;             /*!< (@ 0x000005C8) Enhance Ack(GTS1) TX Control Register                      */
+
+        struct
+        {
+__IOM uint32_t gts_enh_ack_timer :
+            8;     /*!< [7..0] the time window, in unit of us, for FW to set the Enh-Ack
+                                                     TX trigger. The time window is opened when the rxif is
+                                                     asserted and the received frame is a 2015 version frame
+                                                     with ACK request, if the Enh-Ack frame for this response
+                                                     is ready the the FW need to set the GTS FIFO TX trigger
+                                                     during this time window.                                                  */
+__IOM uint32_t rx2tx_enh_ack_delay :
+            8;   /*!< [15..8] in us, the time delay for the trunning of PHY from RX
+                                                     to TX to transmite Enh-Ack frame (in GTS1 FIFO)                           */
+__IM  uint32_t gts_enh_ack_trig_en :
+            1;   /*!< [16..16] indicates whether the time window is opened and the
+                                                     Enh-Ack TX trigger is available. 0: the time windows is
+                                                     closed (it's too late to trigger the Enh-Ack TX); 1: the
+                                                     time windows is opened, set the Enh-Ack TX trigger is available.          */
+__IOM uint32_t alt_gts_enh_ack_mask :
+            1;  /*!< [17..17] FW set this bit to select the timer value for the RXM
+                                                     to apply to the GTS Enh-Ack timer.0: use gts_enh_ack_timer
+                                                     value; 1: use alt_gts_enh_ack_timer value;Normally, FW
+                                                     set this bit to select a different time window for the
+                                                     Enh-Ack trigger bit writting. Ex. the FW select a wider
+                                                     time window when it will write the Enh-Ack TX trigger bit
+                                                     in RX done interrupt handler rather than in RX early interrupt
+                                                     handler. The RXM will latch this bit value when it starting
+                                                     the Enh-Ack timer. So the FW should set this                              */
+            uint32_t            : 6;
+__IOM uint32_t alt_gts_enh_ack_timer :
+            8; /*!< [31..24] an alternate timer window, in unit of us, for FW to
+                                                     set the timer for Enh-Ack TX trigger. The time window is
+                                                     opened when the rxif is asserted and the received frame
+                                                     is a 2015 version frame with ACK request, if the Enh-Ack
+                                                     frame for this response is ready the the FW need to set
+                                                     the GTS FIFO TX trigger during this time window. The GTS
+                                                     TX FIFO encryption will takes time depends on the frame
+                                                     length to encrypt, so the FW may need to adjust the timer
+                                                     value to make the Enh-Ack frame TX at a proper time to
+                                                     have a                                                                    */
+        } tx_enh_ack_ctrl_b;
+    } ;
+    __IM  uint32_t  RESERVED7[11];
+
+    union
+    {
+        __IOM uint32_t
+        pta_ctrl1;                   /*!< (@ 0x000005F8) PTA Control Register 1                                     */
+
+        struct
+        {
+__IOM uint32_t pta_en     :
+            1;            /*!< [0..0] PTA (packet transmission arbitration) for WIFI + 802.15.4
+                                                     function enable control:0: disable PTA function (default),
+                                                     ignore PTA WL_ACT signal and no abort TX/RX1: enable PTA
+                                                     function, abort TX/RX when PTA WL_ACT is high                             */
+__IOM uint32_t pta_share_lna :
+            1;         /*!< [1..1] FW use this bit to indicate the PTA HW whether BT PHY
+                                                     share LAN with WIFI: 1: wifi/BT share LNA. 0: wifi/BT dedicated
+                                                     LNA and zigbee acc hit will trigger high priority request
+                                                     if original RX PTA priority is low                                        */
+__IOM uint32_t cca_req    :
+            1;            /*!< [2..2] Dedicated PTA request for the CCA of a packet TX: 0:
+                                                     no dedicated PTA request for CCA. Only issue 1 PTA request
+                                                     for CCA + TX. 1: issue a RX PTA request for CCA and then
+                                                     another PTA request for TX. The priority of the PTA request
+                                                     for CCA follows the priority setting of TX PTA request
+                                                     (tx_priority).                                                            */
+__IOM uint32_t tx_priority :
+            1;           /*!< [3..3] The priority of PTA request for a packet TX: 0: issue
+                                                     low priority PTA request for packet TX (include its CCA).
+                                                     1: issue high priority PTA request for packet TX (include
+                                                     its CCA).                                                                 */
+            uint32_t            : 28;
+        } pta_ctrl1_b;
+    } ;
+
+    union
+    {
+        __IOM uint32_t
+        pta_ctrl0;                   /*!< (@ 0x000005FC) PTA Control Register 0                                     */
+
+        struct
+        {
+__IOM uint32_t pta_duty_en :
+            1;           /*!< [0..0] enable PTA priority duty control function. When this
+                                                     function is enabled, MAC will send high priority PTA request
+                                                     for idle RX periodically. 0: disable PTA priority duty
+                                                     control function (default); 1: enable PTA priority duty
+                                                     control function the PTA duty interval will start with
+                                                     high priority period when PTA priority duty control is
+                                                     enabled.                                                                  */
+__IOM uint32_t dis_lo_rx_req :
+            1;         /*!< [1..1] disable low priority PTA request: 0: when RX is low priority,
+                                                     issue a low priority PTA request. 1: when RX is low priority,
+                                                     do not issue PTA request and ignore PTA WL_ACT signal.                    */
+            uint32_t            : 2;
+__IOM uint32_t pta_tick_ctrl :
+            12;        /*!< [15..4] this field set the unit, in us, of a tick for the PTA
+                                                     priority duty control function. The duty ratio of the PTA
+                                                     with high priority control is based on this tick counting.
+                                                     Time of a tick = 1 + the value of this field, in unit of
+                                                     us. Example, set this field as 1 means time of a tick is
+                                                     2us. default value is 1000us (1ms).                                       */
+__IOM uint32_t pta_low_duty_tick :
+            8;     /*!< [23..16] this field is used to set the time period of the low
+                                                     priority part in a PTA priority duty control interval,
+                                                     in unit of a tick. Low priority period = (1 + value of
+                                                     this filed)* (tick time). Example, set this filed value
+                                                     as 1 means the time period of low priority is 2 ticks time.
+                                                     default value is 100 ticks (100ms).                                       */
+__IOM uint32_t pta_high_duty_tick :
+            8;    /*!< [31..24] this field is used to set the time period of the high
+                                                     priority part in a PTA priority duty control interval,
+                                                     in unit of a tick. High priority period = (1 + value of
+                                                     this filed)* (tick time). Example, set this filed value
+                                                     as 3 means the time period of high priority is 4 ticks
+                                                     time. default value is 100 ticks (100ms).                                 */
+        } pta_ctrl0_b;
+    } ;
+
+    __IOM uint8_t
+    txn_fifo[128];                  /*!< (@ 0x00000600) TX Normal FIFO                                             */
+
+    __IOM uint8_t
+    txb_fifo[128];                  /*!< (@ 0x00000680) TX Beacon FIFO                                             */
+
+    __IOM uint8_t
+    txg1_fifo[128];                 /*!< (@ 0x00000700) TX GTS1 FIFO                                               */
+
+    __IOM uint8_t
+    txg2_fifo[128];                 /*!< (@ 0x00000780) TX GTS2 FIFO                                               */
+
+    __IOM uint8_t
+    rx_fifo[144];                   /*!< (@ 0x00000800) RX FIFO                                                    */
+
+    __IM  uint32_t  RESERVED28[60];
+
+    __IOM uint8_t
+    sec_key_buf[64];                /*!< (@ 0x00000980) Security Key Buffer                                        */
+} MAC_Type;                                     /*!< Size = 2496 (0x9c0)                                                       */
+
+
+/** @} */ /* End of group Device_Peripheral_peripherals */
+
+
+/* =========================================================================================================================== */
+/* ================                          Device Specific Peripheral Address Map                           ================ */
+/* =========================================================================================================================== */
+
+
+/** @addtogroup Device_Peripheral_peripheralAddr
+  * @{
+  */
+
+#define MAC_BASE                    ZIGBEE_REG_BASE
+
+/** @} */ /* End of group Device_Peripheral_peripheralAddr */
+
+
+/* =========================================================================================================================== */
+/* ================                                  Peripheral declaration                                   ================ */
+/* =========================================================================================================================== */
+
+
+/** @addtogroup Device_Peripheral_declaration
+  * @{
+  */
+
+#define MAC                         ((MAC_Type*)               MAC_BASE)
+
+/** @} */ /* End of group Device_Peripheral_declaration */
+
+
+/* =========================================  End of section using anonymous unions  ========================================= */
+#if defined (__CC_ARM)
+#pragma pop
+#elif defined (__ICCARM__)
+/* leave anonymous unions enabled */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang diagnostic pop
+#elif defined (__GNUC__)
+/* anonymous unions are enabled by default */
+#elif defined (__TMS470__)
+/* anonymous unions are enabled by default */
+#elif defined (__TASKING__)
+#pragma warning restore
+#elif defined (__CSMC__)
+/* anonymous unions are enabled by default */
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* MAC_REG_H */
+
+
+/** @} */ /* End of group rtl87x2g */
+
+/** @} */ /* End of group Realtek Semiconductor Corp. */
diff --git a/bee/drivers/mac_802154/rom/mac_reg_mask.h b/bee/drivers/mac_802154/rom/mac_reg_mask.h
new file mode 100644
index 00000000..f9c35b1a
--- /dev/null
+++ b/bee/drivers/mac_802154/rom/mac_reg_mask.h
@@ -0,0 +1,1330 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*
+ *
+ * @file     mac_reg_mask.h
+ * @brief    CMSIS HeaderFile
+ * @version  1.0
+ * @date     12. July 2023
+ * @note     Generated by SVDConv V3.3.35 on Wednesday, 12.07.2023 18:32:50
+ *           from File 'rtl87x2g_mac_fpga_remap.svd',
+ *           last modified on Wednesday, 12.07.2023 10:30:41
+ */
+
+/** @addtogroup Realtek Semiconductor Corp.
+  * @{
+  */
+
+
+/** @addtogroup rtl87x2g
+  * @{
+  */
+
+
+#ifndef MAC_REG_MASK_H
+#define MAC_REG_MASK_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/** @addtogroup Configuration_of_CMSIS
+  * @{
+  */
+
+/* =========================================================================================================================== */
+/* ================                                Pos/Mask Peripheral Section                                ================ */
+/* =========================================================================================================================== */
+
+
+/** @addtogroup PosMask_peripherals
+  * @{
+  */
+
+
+
+/* =========================================================================================================================== */
+/* ================                                            MAC                                            ================ */
+/* =========================================================================================================================== */
+
+/* ======================================================  device_ctrl  ====================================================== */
+#define MAC_device_ctrl_coord_Pos         (0UL)                     /*!< coord (Bit 0)                                         */
+#define MAC_device_ctrl_coord_Msk         (0x1UL)                   /*!< coord (Bitfield-Mask: 0x01)                           */
+#define MAC_device_ctrl_pancoord_Pos      (1UL)                     /*!< pancoord (Bit 1)                                      */
+#define MAC_device_ctrl_pancoord_Msk      (0x2UL)                   /*!< pancoord (Bitfield-Mask: 0x01)                        */
+#define MAC_device_ctrl_mac_lpbk_Pos      (2UL)                     /*!< mac_lpbk (Bit 2)                                      */
+#define MAC_device_ctrl_mac_lpbk_Msk      (0x4UL)                   /*!< mac_lpbk (Bitfield-Mask: 0x01)                        */
+#define MAC_device_ctrl_noackrsp_Pos      (3UL)                     /*!< noackrsp (Bit 3)                                      */
+#define MAC_device_ctrl_noackrsp_Msk      (0x8UL)                   /*!< noackrsp (Bitfield-Mask: 0x01)                        */
+#define MAC_device_ctrl_nocrc_Pos         (5UL)                     /*!< nocrc (Bit 5)                                         */
+#define MAC_device_ctrl_nocrc_Msk         (0x20UL)                  /*!< nocrc (Bitfield-Mask: 0x01)                           */
+#define MAC_device_ctrl_fifoen_Pos        (6UL)                     /*!< fifoen (Bit 6)                                        */
+#define MAC_device_ctrl_fifoen_Msk        (0x40UL)                  /*!< fifoen (Bitfield-Mask: 0x01)                          */
+#define MAC_device_ctrl_split_irq_Pos     (8UL)                     /*!< split_irq (Bit 8)                                     */
+#define MAC_device_ctrl_split_irq_Msk     (0x100UL)                 /*!< split_irq (Bitfield-Mask: 0x01)                       */
+#define MAC_device_ctrl_irqpol_Pos        (9UL)                     /*!< irqpol (Bit 9)                                        */
+#define MAC_device_ctrl_irqpol_Msk        (0x200UL)                 /*!< irqpol (Bitfield-Mask: 0x01)                          */
+#define MAC_device_ctrl_tickp_Pos         (16UL)                    /*!< tickp (Bit 16)                                        */
+#define MAC_device_ctrl_tickp_Msk         (0x1ff0000UL)             /*!< tickp (Bitfield-Mask: 0x1ff)                          */
+/* =========================================================  panid  ========================================================= */
+#define MAC_panid_panid_Pos               (0UL)                     /*!< panid (Bit 0)                                         */
+#define MAC_panid_panid_Msk               (0xffffUL)                /*!< panid (Bitfield-Mask: 0xffff)                         */
+/* =========================================================  sadr  ========================================================== */
+#define MAC_sadr_sadr_Pos                 (0UL)                     /*!< sadr (Bit 0)                                          */
+#define MAC_sadr_sadr_Msk                 (0xffffUL)                /*!< sadr (Bitfield-Mask: 0xffff)                          */
+/* ========================================================  eadr_l  ========================================================= */
+#define MAC_eadr_l_eadr_l_Pos             (0UL)                     /*!< eadr_l (Bit 0)                                        */
+#define MAC_eadr_l_eadr_l_Msk             (0xffffffffUL)            /*!< eadr_l (Bitfield-Mask: 0xffffffff)                    */
+/* ========================================================  eadr_h  ========================================================= */
+#define MAC_eadr_h_eadr_h_Pos             (0UL)                     /*!< eadr_h (Bit 0)                                        */
+#define MAC_eadr_h_eadr_h_Msk             (0xffffffffUL)            /*!< eadr_h (Bitfield-Mask: 0xffffffff)                    */
+/* =======================================================  clk_ctrl  ======================================================== */
+#define MAC_clk_ctrl_ctrl_sec_Pos         (0UL)                     /*!< ctrl_sec (Bit 0)                                      */
+#define MAC_clk_ctrl_ctrl_sec_Msk         (0x1UL)                   /*!< ctrl_sec (Bitfield-Mask: 0x01)                        */
+#define MAC_clk_ctrl_en_sec_Pos           (1UL)                     /*!< en_sec (Bit 1)                                        */
+#define MAC_clk_ctrl_en_sec_Msk           (0x2UL)                   /*!< en_sec (Bitfield-Mask: 0x01)                          */
+#define MAC_clk_ctrl_entxm_Pos            (2UL)                     /*!< entxm (Bit 2)                                         */
+#define MAC_clk_ctrl_entxm_Msk            (0x4UL)                   /*!< entxm (Bitfield-Mask: 0x01)                           */
+#define MAC_clk_ctrl_engts_Pos            (3UL)                     /*!< engts (Bit 3)                                         */
+#define MAC_clk_ctrl_engts_Msk            (0x8UL)                   /*!< engts (Bitfield-Mask: 0x01)                           */
+#define MAC_clk_ctrl_enrxm_Pos            (4UL)                     /*!< enrxm (Bit 4)                                         */
+#define MAC_clk_ctrl_enrxm_Msk            (0x10UL)                  /*!< enrxm (Bitfield-Mask: 0x01)                           */
+#define MAC_clk_ctrl_txn_off_Pos          (5UL)                     /*!< txn_off (Bit 5)                                       */
+#define MAC_clk_ctrl_txn_off_Msk          (0x20UL)                  /*!< txn_off (Bitfield-Mask: 0x01)                         */
+#define MAC_clk_ctrl_txb_on_Pos           (6UL)                     /*!< txb_on (Bit 6)                                        */
+#define MAC_clk_ctrl_txb_on_Msk           (0x40UL)                  /*!< txb_on (Bitfield-Mask: 0x01)                          */
+#define MAC_clk_ctrl_ffidle_Pos           (7UL)                     /*!< ffidle (Bit 7)                                        */
+#define MAC_clk_ctrl_ffidle_Msk           (0x80UL)                  /*!< ffidle (Bitfield-Mask: 0x01)                          */
+#define MAC_clk_ctrl_ed_scan_clkon_Pos    (8UL)                     /*!< ed_scan_clkon (Bit 8)                                 */
+#define MAC_clk_ctrl_ed_scan_clkon_Msk    (0x100UL)                 /*!< ed_scan_clkon (Bitfield-Mask: 0x01)                   */
+#define MAC_clk_ctrl_phy_arb_clkon_Pos    (9UL)                     /*!< phy_arb_clkon (Bit 9)                                 */
+#define MAC_clk_ctrl_phy_arb_clkon_Msk    (0x200UL)                 /*!< phy_arb_clkon (Bitfield-Mask: 0x01)                   */
+#define MAC_clk_ctrl_fifo_clkon_Pos       (10UL)                    /*!< fifo_clkon (Bit 10)                                   */
+#define MAC_clk_ctrl_fifo_clkon_Msk       (0x400UL)                 /*!< fifo_clkon (Bitfield-Mask: 0x01)                      */
+#define MAC_clk_ctrl_dbg_clkon_Pos        (11UL)                    /*!< dbg_clkon (Bit 11)                                    */
+#define MAC_clk_ctrl_dbg_clkon_Msk        (0x800UL)                 /*!< dbg_clkon (Bitfield-Mask: 0x01)                       */
+/* =======================================================  mac_timer  ======================================================= */
+#define MAC_mac_timer_mactmr_l_Pos        (0UL)                     /*!< mactmr_l (Bit 0)                                      */
+#define MAC_mac_timer_mactmr_l_Msk        (0xffUL)                  /*!< mactmr_l (Bitfield-Mask: 0xff)                        */
+#define MAC_mac_timer_mactmr_h_Pos        (8UL)                     /*!< mactmr_h (Bit 8)                                      */
+#define MAC_mac_timer_mactmr_h_Msk        (0xff00UL)                /*!< mactmr_h (Bitfield-Mask: 0xff)                        */
+#define MAC_mac_timer_mactmrfr_Pos        (16UL)                    /*!< mactmrfr (Bit 16)                                     */
+#define MAC_mac_timer_mactmrfr_Msk        (0x10000UL)               /*!< mactmrfr (Bitfield-Mask: 0x01)                        */
+#define MAC_mac_timer_btcmp0_dis_Pos      (24UL)                    /*!< btcmp0_dis (Bit 24)                                   */
+#define MAC_mac_timer_btcmp0_dis_Msk      (0x1000000UL)             /*!< btcmp0_dis (Bitfield-Mask: 0x01)                      */
+#define MAC_mac_timer_btcmp1_dis_Pos      (25UL)                    /*!< btcmp1_dis (Bit 25)                                   */
+#define MAC_mac_timer_btcmp1_dis_Msk      (0x2000000UL)             /*!< btcmp1_dis (Bitfield-Mask: 0x01)                      */
+#define MAC_mac_timer_btcmp2_dis_Pos      (26UL)                    /*!< btcmp2_dis (Bit 26)                                   */
+#define MAC_mac_timer_btcmp2_dis_Msk      (0x4000000UL)             /*!< btcmp2_dis (Bitfield-Mask: 0x01)                      */
+#define MAC_mac_timer_btcmp3_dis_Pos      (27UL)                    /*!< btcmp3_dis (Bit 27)                                   */
+#define MAC_mac_timer_btcmp3_dis_Msk      (0x8000000UL)             /*!< btcmp3_dis (Bitfield-Mask: 0x01)                      */
+/* =======================================================  rst_ctrl  ======================================================== */
+#define MAC_rst_ctrl_rstmac_Pos           (16UL)                    /*!< rstmac (Bit 16)                                       */
+#define MAC_rst_ctrl_rstmac_Msk           (0x10000UL)               /*!< rstmac (Bitfield-Mask: 0x01)                          */
+/* =====================================================  rx_frm_length  ===================================================== */
+#define MAC_rx_frm_length_hlen_Pos        (0UL)                     /*!< hlen (Bit 0)                                          */
+#define MAC_rx_frm_length_hlen_Msk        (0x7fUL)                  /*!< hlen (Bitfield-Mask: 0x7f)                            */
+#define MAC_rx_frm_length_flen_Pos        (8UL)                     /*!< flen (Bit 8)                                          */
+#define MAC_rx_frm_length_flen_Msk        (0x7f00UL)                /*!< flen (Bitfield-Mask: 0x7f)                            */
+/* ========================================================  intmsk  ========================================================= */
+#define MAC_intmsk_txnmsk_Pos             (0UL)                     /*!< txnmsk (Bit 0)                                        */
+#define MAC_intmsk_txnmsk_Msk             (0x1UL)                   /*!< txnmsk (Bitfield-Mask: 0x01)                          */
+#define MAC_intmsk_txg1msk_Pos            (1UL)                     /*!< txg1msk (Bit 1)                                       */
+#define MAC_intmsk_txg1msk_Msk            (0x2UL)                   /*!< txg1msk (Bitfield-Mask: 0x01)                         */
+#define MAC_intmsk_txg2msk_Pos            (2UL)                     /*!< txg2msk (Bit 2)                                       */
+#define MAC_intmsk_txg2msk_Msk            (0x4UL)                   /*!< txg2msk (Bitfield-Mask: 0x01)                         */
+#define MAC_intmsk_txnterrmsk_Pos         (3UL)                     /*!< txnterrmsk (Bit 3)                                    */
+#define MAC_intmsk_txnterrmsk_Msk         (0x8UL)                   /*!< txnterrmsk (Bitfield-Mask: 0x01)                      */
+#define MAC_intmsk_rxelymsk_Pos           (4UL)                     /*!< rxelymsk (Bit 4)                                      */
+#define MAC_intmsk_rxelymsk_Msk           (0x10UL)                  /*!< rxelymsk (Bitfield-Mask: 0x01)                        */
+#define MAC_intmsk_secmsk_Pos             (5UL)                     /*!< secmsk (Bit 5)                                        */
+#define MAC_intmsk_secmsk_Msk             (0x20UL)                  /*!< secmsk (Bitfield-Mask: 0x01)                          */
+#define MAC_intmsk_rxmsk_Pos              (6UL)                     /*!< rxmsk (Bit 6)                                         */
+#define MAC_intmsk_rxmsk_Msk              (0x40UL)                  /*!< rxmsk (Bitfield-Mask: 0x01)                           */
+#define MAC_intmsk_mactmrmsk_Pos          (7UL)                     /*!< mactmrmsk (Bit 7)                                     */
+#define MAC_intmsk_mactmrmsk_Msk          (0x80UL)                  /*!< mactmrmsk (Bitfield-Mask: 0x01)                       */
+#define MAC_intmsk_btcmp0msk_Pos          (8UL)                     /*!< btcmp0msk (Bit 8)                                     */
+#define MAC_intmsk_btcmp0msk_Msk          (0x100UL)                 /*!< btcmp0msk (Bitfield-Mask: 0x01)                       */
+#define MAC_intmsk_btcmp1msk_Pos          (9UL)                     /*!< btcmp1msk (Bit 9)                                     */
+#define MAC_intmsk_btcmp1msk_Msk          (0x200UL)                 /*!< btcmp1msk (Bitfield-Mask: 0x01)                       */
+#define MAC_intmsk_gntmsk_Pos             (10UL)                    /*!< gntmsk (Bit 10)                                       */
+#define MAC_intmsk_gntmsk_Msk             (0x400UL)                 /*!< gntmsk (Bitfield-Mask: 0x01)                          */
+#define MAC_intmsk_edscanmsk_Pos          (11UL)                    /*!< edscanmsk (Bit 11)                                    */
+#define MAC_intmsk_edscanmsk_Msk          (0x800UL)                 /*!< edscanmsk (Bitfield-Mask: 0x01)                       */
+#define MAC_intmsk_sfstartmsk_Pos         (12UL)                    /*!< sfstartmsk (Bit 12)                                   */
+#define MAC_intmsk_sfstartmsk_Msk         (0x1000UL)                /*!< sfstartmsk (Bitfield-Mask: 0x01)                      */
+#define MAC_intmsk_sfendmsk_Pos           (13UL)                    /*!< sfendmsk (Bit 13)                                     */
+#define MAC_intmsk_sfendmsk_Msk           (0x2000UL)                /*!< sfendmsk (Bitfield-Mask: 0x01)                        */
+#define MAC_intmsk_btcmp2msk_Pos          (14UL)                    /*!< btcmp2msk (Bit 14)                                    */
+#define MAC_intmsk_btcmp2msk_Msk          (0x4000UL)                /*!< btcmp2msk (Bitfield-Mask: 0x01)                       */
+#define MAC_intmsk_btcmp3msk_Pos          (15UL)                    /*!< btcmp3msk (Bit 15)                                    */
+#define MAC_intmsk_btcmp3msk_Msk          (0x8000UL)                /*!< btcmp3msk (Bitfield-Mask: 0x01)                       */
+/* ========================================================  isrsts  ========================================================= */
+#define MAC_isrsts_txnif_Pos              (0UL)                     /*!< txnif (Bit 0)                                         */
+#define MAC_isrsts_txnif_Msk              (0x1UL)                   /*!< txnif (Bitfield-Mask: 0x01)                           */
+#define MAC_isrsts_txg1if_Pos             (1UL)                     /*!< txg1if (Bit 1)                                        */
+#define MAC_isrsts_txg1if_Msk             (0x2UL)                   /*!< txg1if (Bitfield-Mask: 0x01)                          */
+#define MAC_isrsts_txg2if_Pos             (2UL)                     /*!< txg2if (Bit 2)                                        */
+#define MAC_isrsts_txg2if_Msk             (0x4UL)                   /*!< txg2if (Bitfield-Mask: 0x01)                          */
+#define MAC_isrsts_txnterrif_Pos          (3UL)                     /*!< txnterrif (Bit 3)                                     */
+#define MAC_isrsts_txnterrif_Msk          (0x8UL)                   /*!< txnterrif (Bitfield-Mask: 0x01)                       */
+#define MAC_isrsts_rxelyif_Pos            (4UL)                     /*!< rxelyif (Bit 4)                                       */
+#define MAC_isrsts_rxelyif_Msk            (0x10UL)                  /*!< rxelyif (Bitfield-Mask: 0x01)                         */
+#define MAC_isrsts_secif_Pos              (5UL)                     /*!< secif (Bit 5)                                         */
+#define MAC_isrsts_secif_Msk              (0x20UL)                  /*!< secif (Bitfield-Mask: 0x01)                           */
+#define MAC_isrsts_rxif_Pos               (6UL)                     /*!< rxif (Bit 6)                                          */
+#define MAC_isrsts_rxif_Msk               (0x40UL)                  /*!< rxif (Bitfield-Mask: 0x01)                            */
+#define MAC_isrsts_mactmrif_Pos           (7UL)                     /*!< mactmrif (Bit 7)                                      */
+#define MAC_isrsts_mactmrif_Msk           (0x80UL)                  /*!< mactmrif (Bitfield-Mask: 0x01)                        */
+#define MAC_isrsts_btcmp0if_Pos           (8UL)                     /*!< btcmp0if (Bit 8)                                      */
+#define MAC_isrsts_btcmp0if_Msk           (0x100UL)                 /*!< btcmp0if (Bitfield-Mask: 0x01)                        */
+#define MAC_isrsts_btcmp1if_Pos           (9UL)                     /*!< btcmp1if (Bit 9)                                      */
+#define MAC_isrsts_btcmp1if_Msk           (0x200UL)                 /*!< btcmp1if (Bitfield-Mask: 0x01)                        */
+#define MAC_isrsts_gntif_Pos              (10UL)                    /*!< gntif (Bit 10)                                        */
+#define MAC_isrsts_gntif_Msk              (0x400UL)                 /*!< gntif (Bitfield-Mask: 0x01)                           */
+#define MAC_isrsts_edscanif_Pos           (11UL)                    /*!< edscanif (Bit 11)                                     */
+#define MAC_isrsts_edscanif_Msk           (0x800UL)                 /*!< edscanif (Bitfield-Mask: 0x01)                        */
+#define MAC_isrsts_sfstartif_Pos          (12UL)                    /*!< sfstartif (Bit 12)                                    */
+#define MAC_isrsts_sfstartif_Msk          (0x1000UL)                /*!< sfstartif (Bitfield-Mask: 0x01)                       */
+#define MAC_isrsts_sfendif_Pos            (13UL)                    /*!< sfendif (Bit 13)                                      */
+#define MAC_isrsts_sfendif_Msk            (0x2000UL)                /*!< sfendif (Bitfield-Mask: 0x01)                         */
+#define MAC_isrsts_btcmp2if_Pos           (14UL)                    /*!< btcmp2if (Bit 14)                                     */
+#define MAC_isrsts_btcmp2if_Msk           (0x4000UL)                /*!< btcmp2if (Bitfield-Mask: 0x01)                        */
+#define MAC_isrsts_btcmp3if_Pos           (15UL)                    /*!< btcmp3if (Bit 15)                                     */
+#define MAC_isrsts_btcmp3if_Msk           (0x8000UL)                /*!< btcmp3if (Bitfield-Mask: 0x01)                        */
+/* ======================================================  bt_clk_cmp0  ====================================================== */
+#define MAC_bt_clk_cmp0_bt_ckc_Pos        (0UL)                     /*!< bt_ckc (Bit 0)                                        */
+#define MAC_bt_clk_cmp0_bt_ckc_Msk        (0x3ffUL)                 /*!< bt_ckc (Bitfield-Mask: 0x3ff)                         */
+#define MAC_bt_clk_cmp0_bt_nclk_Pos       (10UL)                    /*!< bt_nclk (Bit 10)                                      */
+#define MAC_bt_clk_cmp0_bt_nclk_Msk       (0xfffffc00UL)            /*!< bt_nclk (Bitfield-Mask: 0x3fffff)                     */
+/* ======================================================  bt_clk_cmp1  ====================================================== */
+#define MAC_bt_clk_cmp1_bt_ckc_Pos        (0UL)                     /*!< bt_ckc (Bit 0)                                        */
+#define MAC_bt_clk_cmp1_bt_ckc_Msk        (0x3ffUL)                 /*!< bt_ckc (Bitfield-Mask: 0x3ff)                         */
+#define MAC_bt_clk_cmp1_bt_nclk_Pos       (10UL)                    /*!< bt_nclk (Bit 10)                                      */
+#define MAC_bt_clk_cmp1_bt_nclk_Msk       (0xfffffc00UL)            /*!< bt_nclk (Bitfield-Mask: 0x3fffff)                     */
+/* ======================================================  bt_clk_cmp2  ====================================================== */
+#define MAC_bt_clk_cmp2_bt_ckc_Pos        (0UL)                     /*!< bt_ckc (Bit 0)                                        */
+#define MAC_bt_clk_cmp2_bt_ckc_Msk        (0x3ffUL)                 /*!< bt_ckc (Bitfield-Mask: 0x3ff)                         */
+#define MAC_bt_clk_cmp2_bt_nclk_Pos       (10UL)                    /*!< bt_nclk (Bit 10)                                      */
+#define MAC_bt_clk_cmp2_bt_nclk_Msk       (0xfffffc00UL)            /*!< bt_nclk (Bitfield-Mask: 0x3fffff)                     */
+/* ======================================================  bt_clk_cmp3  ====================================================== */
+#define MAC_bt_clk_cmp3_bt_ckc_Pos        (0UL)                     /*!< bt_ckc (Bit 0)                                        */
+#define MAC_bt_clk_cmp3_bt_ckc_Msk        (0x3ffUL)                 /*!< bt_ckc (Bitfield-Mask: 0x3ff)                         */
+#define MAC_bt_clk_cmp3_bt_nclk_Pos       (10UL)                    /*!< bt_nclk (Bit 10)                                      */
+#define MAC_bt_clk_cmp3_bt_nclk_Msk       (0xfffffc00UL)            /*!< bt_nclk (Bitfield-Mask: 0x3fffff)                     */
+/* =====================================================  ed_scan_ctrl0  ===================================================== */
+#define MAC_ed_scan_ctrl0_scan_enable_Pos (0UL)                     /*!< scan_enable (Bit 0)                                   */
+#define MAC_ed_scan_ctrl0_scan_enable_Msk (0x1UL)                   /*!< scan_enable (Bitfield-Mask: 0x01)                     */
+#define MAC_ed_scan_ctrl0_scan_round_Pos  (1UL)                     /*!< scan_round (Bit 1)                                    */
+#define MAC_ed_scan_ctrl0_scan_round_Msk  (0x3ffeUL)                /*!< scan_round (Bitfield-Mask: 0x1fff)                    */
+#define MAC_ed_scan_ctrl0_peak_value_Pos  (14UL)                    /*!< peak_value (Bit 14)                                   */
+#define MAC_ed_scan_ctrl0_peak_value_Msk  (0x3fc000UL)              /*!< peak_value (Bitfield-Mask: 0xff)                      */
+#define MAC_ed_scan_ctrl0_scan_symbol_Pos (22UL)                    /*!< scan_symbol (Bit 22)                                  */
+#define MAC_ed_scan_ctrl0_scan_symbol_Msk (0x3c00000UL)             /*!< scan_symbol (Bitfield-Mask: 0x0f)                     */
+#define MAC_ed_scan_ctrl0_ed_scan_encounter_tx_trig_sts_Pos (26UL)  /*!< ed_scan_encounter_tx_trig_sts (Bit 26)                */
+#define MAC_ed_scan_ctrl0_ed_scan_encounter_tx_trig_sts_Msk (0x4000000UL) /*!< ed_scan_encounter_tx_trig_sts (Bitfield-Mask: 0x01) */
+#define MAC_ed_scan_ctrl0_scan_fw_cancel_sts_Pos (27UL)             /*!< scan_fw_cancel_sts (Bit 27)                           */
+#define MAC_ed_scan_ctrl0_scan_fw_cancel_sts_Msk (0x8000000UL)      /*!< scan_fw_cancel_sts (Bitfield-Mask: 0x01)              */
+#define MAC_ed_scan_ctrl0_scan_gnt_deassert_sts_Pos (28UL)          /*!< scan_gnt_deassert_sts (Bit 28)                        */
+#define MAC_ed_scan_ctrl0_scan_gnt_deassert_sts_Msk (0x10000000UL)  /*!< scan_gnt_deassert_sts (Bitfield-Mask: 0x01)           */
+#define MAC_ed_scan_ctrl0_scan_ed_vld_tmo_sts_Pos (29UL)            /*!< scan_ed_vld_tmo_sts (Bit 29)                          */
+#define MAC_ed_scan_ctrl0_scan_ed_vld_tmo_sts_Msk (0x20000000UL)    /*!< scan_ed_vld_tmo_sts (Bitfield-Mask: 0x01)             */
+#define MAC_ed_scan_ctrl0_scan_finish_sts_Pos (30UL)                /*!< scan_finish_sts (Bit 30)                              */
+#define MAC_ed_scan_ctrl0_scan_finish_sts_Msk (0x40000000UL)        /*!< scan_finish_sts (Bitfield-Mask: 0x01)                 */
+#define MAC_ed_scan_ctrl0_scan_done_Pos   (31UL)                    /*!< scan_done (Bit 31)                                    */
+#define MAC_ed_scan_ctrl0_scan_done_Msk   (0x80000000UL)            /*!< scan_done (Bitfield-Mask: 0x01)                       */
+/* =====================================================  ed_scan_ctrl1  ===================================================== */
+#define MAC_ed_scan_ctrl1_scan_cnt_Pos    (0UL)                     /*!< scan_cnt (Bit 0)                                      */
+#define MAC_ed_scan_ctrl1_scan_cnt_Msk    (0x3fffUL)                /*!< scan_cnt (Bitfield-Mask: 0x3fff)                      */
+#define MAC_ed_scan_ctrl1_scan_vld_tmo_cnt_limit_Pos (14UL)         /*!< scan_vld_tmo_cnt_limit (Bit 14)                       */
+#define MAC_ed_scan_ctrl1_scan_vld_tmo_cnt_limit_Msk (0xfc000UL)    /*!< scan_vld_tmo_cnt_limit (Bitfield-Mask: 0x3f)          */
+#define MAC_ed_scan_ctrl1_scan_first_ed_scan_symbol_Pos (20UL)      /*!< scan_first_ed_scan_symbol (Bit 20)                    */
+#define MAC_ed_scan_ctrl1_scan_first_ed_scan_symbol_Msk (0xf00000UL) /*!< scan_first_ed_scan_symbol (Bitfield-Mask: 0x0f)      */
+#define MAC_ed_scan_ctrl1_scan_first_ed_scan_cnt_Pos (24UL)         /*!< scan_first_ed_scan_cnt (Bit 24)                       */
+#define MAC_ed_scan_ctrl1_scan_first_ed_scan_cnt_Msk (0xff000000UL) /*!< scan_first_ed_scan_cnt (Bitfield-Mask: 0xff)          */
+/* ======================================================  ed_scan_dbg  ====================================================== */
+#define MAC_ed_scan_dbg_ed_scan_cst_Pos   (0UL)                     /*!< ed_scan_cst (Bit 0)                                   */
+#define MAC_ed_scan_dbg_ed_scan_cst_Msk   (0xfUL)                   /*!< ed_scan_cst (Bitfield-Mask: 0x0f)                     */
+/* =====================================================  phy_arb_ctrl  ====================================================== */
+#define MAC_phy_arb_ctrl_fw_active_entry_Pos (0UL)                  /*!< fw_active_entry (Bit 0)                               */
+#define MAC_phy_arb_ctrl_fw_active_entry_Msk (0x1UL)                /*!< fw_active_entry (Bitfield-Mask: 0x01)                 */
+#define MAC_phy_arb_ctrl_zb_only_Pos      (1UL)                     /*!< zb_only (Bit 1)                                       */
+#define MAC_phy_arb_ctrl_zb_only_Msk      (0x2UL)                   /*!< zb_only (Bitfield-Mask: 0x01)                         */
+#define MAC_phy_arb_ctrl_anchor_point_Pos (2UL)                     /*!< anchor_point (Bit 2)                                  */
+#define MAC_phy_arb_ctrl_anchor_point_Msk (0xffffcUL)               /*!< anchor_point (Bitfield-Mask: 0x3ffff)                 */
+#define MAC_phy_arb_ctrl_anch_pt_jump_value_Pos (20UL)              /*!< anch_pt_jump_value (Bit 20)                           */
+#define MAC_phy_arb_ctrl_anch_pt_jump_value_Msk (0xf00000UL)        /*!< anch_pt_jump_value (Bitfield-Mask: 0x0f)              */
+#define MAC_phy_arb_ctrl_zbrf_gnt_deassert_sts_Pos (24UL)           /*!< zbrf_gnt_deassert_sts (Bit 24)                        */
+#define MAC_phy_arb_ctrl_zbrf_gnt_deassert_sts_Msk (0x1000000UL)    /*!< zbrf_gnt_deassert_sts (Bitfield-Mask: 0x01)           */
+#define MAC_phy_arb_ctrl_zbrf_gnt_fail_sts_Pos (25UL)               /*!< zbrf_gnt_fail_sts (Bit 25)                            */
+#define MAC_phy_arb_ctrl_zbrf_gnt_fail_sts_Msk (0x2000000UL)        /*!< zbrf_gnt_fail_sts (Bitfield-Mask: 0x01)               */
+#define MAC_phy_arb_ctrl_zbrf_gnt_sts_Pos (26UL)                    /*!< zbrf_gnt_sts (Bit 26)                                 */
+#define MAC_phy_arb_ctrl_zbrf_gnt_sts_Msk (0x4000000UL)             /*!< zbrf_gnt_sts (Bitfield-Mask: 0x01)                    */
+/* ====================================================  phy_arb_status  ===================================================== */
+#define MAC_phy_arb_status_zbrf_meu_cs_Pos (0UL)                    /*!< zbrf_meu_cs (Bit 0)                                   */
+#define MAC_phy_arb_status_zbrf_meu_cs_Msk (0x3UL)                  /*!< zbrf_meu_cs (Bitfield-Mask: 0x03)                     */
+#define MAC_phy_arb_status_zbrf_meu_anchor_point_Pos (2UL)          /*!< zbrf_meu_anchor_point (Bit 2)                         */
+#define MAC_phy_arb_status_zbrf_meu_anchor_point_Msk (0xffffcUL)    /*!< zbrf_meu_anchor_point (Bitfield-Mask: 0x3ffff)        */
+/* ===================================================  bt_clk_latch_ctrl  =================================================== */
+#define MAC_bt_clk_latch_ctrl_bt_timer_native_h_Pos (0UL)           /*!< bt_timer_native_h (Bit 0)                             */
+#define MAC_bt_clk_latch_ctrl_bt_timer_native_h_Msk (0x1fUL)        /*!< bt_timer_native_h (Bitfield-Mask: 0x1f)               */
+#define MAC_bt_clk_latch_ctrl_bt_timer_latch_Pos (31UL)             /*!< bt_timer_latch (Bit 31)                               */
+#define MAC_bt_clk_latch_ctrl_bt_timer_latch_Msk (0x80000000UL)     /*!< bt_timer_latch (Bitfield-Mask: 0x01)                  */
+/* =====================================================  bt_clk_latch  ====================================================== */
+#define MAC_bt_clk_latch_bt_timer_cgn_Pos (0UL)                     /*!< bt_timer_cgn (Bit 0)                                  */
+#define MAC_bt_clk_latch_bt_timer_cgn_Msk (0x3ffUL)                 /*!< bt_timer_cgn (Bitfield-Mask: 0x3ff)                   */
+#define MAC_bt_clk_latch_bt_timer_native_Pos (10UL)                 /*!< bt_timer_native (Bit 10)                              */
+#define MAC_bt_clk_latch_bt_timer_native_Msk (0xfffffc00UL)         /*!< bt_timer_native (Bitfield-Mask: 0x3fffff)             */
+/* ======================================================  mac_version  ====================================================== */
+#define MAC_mac_version_version_Pos       (0UL)                     /*!< version (Bit 0)                                       */
+#define MAC_mac_version_version_Msk       (0xffffffffUL)            /*!< version (Bitfield-Mask: 0xffffffff)                   */
+/* =========================================================  rssi  ========================================================== */
+#define MAC_rssi_rssi_Pos                 (0UL)                     /*!< rssi (Bit 0)                                          */
+#define MAC_rssi_rssi_Msk                 (0xffffUL)                /*!< rssi (Bitfield-Mask: 0xffff)                          */
+/* ======================================================  tx_term_sts  ====================================================== */
+#define MAC_tx_term_sts_zbrf_gts2_tx_termed_Pos (0UL)               /*!< zbrf_gts2_tx_termed (Bit 0)                           */
+#define MAC_tx_term_sts_zbrf_gts2_tx_termed_Msk (0x1UL)             /*!< zbrf_gts2_tx_termed (Bitfield-Mask: 0x01)             */
+#define MAC_tx_term_sts_zbrf_gts1_tx_termed_Pos (1UL)               /*!< zbrf_gts1_tx_termed (Bit 1)                           */
+#define MAC_tx_term_sts_zbrf_gts1_tx_termed_Msk (0x2UL)             /*!< zbrf_gts1_tx_termed (Bitfield-Mask: 0x01)             */
+#define MAC_tx_term_sts_zbrf_normal_tx_termed_Pos (2UL)             /*!< zbrf_normal_tx_termed (Bit 2)                         */
+#define MAC_tx_term_sts_zbrf_normal_tx_termed_Msk (0x4UL)           /*!< zbrf_normal_tx_termed (Bitfield-Mask: 0x01)           */
+#define MAC_tx_term_sts_zbrf_beacon_tx_termed_Pos (3UL)             /*!< zbrf_beacon_tx_termed (Bit 3)                         */
+#define MAC_tx_term_sts_zbrf_beacon_tx_termed_Msk (0x8UL)           /*!< zbrf_beacon_tx_termed (Bitfield-Mask: 0x01)           */
+/* =========================================================  rfctl  ========================================================= */
+#define MAC_rfctl_rfrxmode_Pos            (0UL)                     /*!< rfrxmode (Bit 0)                                      */
+#define MAC_rfctl_rfrxmode_Msk            (0x1UL)                   /*!< rfrxmode (Bitfield-Mask: 0x01)                        */
+#define MAC_rfctl_rftxmode_Pos            (1UL)                     /*!< rftxmode (Bit 1)                                      */
+#define MAC_rfctl_rftxmode_Msk            (0x2UL)                   /*!< rftxmode (Bitfield-Mask: 0x01)                        */
+#define MAC_rfctl_rfrst_Pos               (2UL)                     /*!< rfrst (Bit 2)                                         */
+#define MAC_rfctl_rfrst_Msk               (0x4UL)                   /*!< rfrst (Bitfield-Mask: 0x01)                           */
+/* ===================================================  wakeup_remaincnt  ==================================================== */
+#define MAC_wakeup_remaincnt_remcnt_Pos   (0UL)                     /*!< remcnt (Bit 0)                                        */
+#define MAC_wakeup_remaincnt_remcnt_Msk   (0xffffUL)                /*!< remcnt (Bitfield-Mask: 0xffff)                        */
+#define MAC_wakeup_remaincnt_wakecnt_Pos  (16UL)                    /*!< wakecnt (Bit 16)                                      */
+#define MAC_wakeup_remaincnt_wakecnt_Msk  (0x1ff0000UL)             /*!< wakecnt (Bitfield-Mask: 0x1ff)                        */
+/* ====================================================  wakeup_maincnt  ===================================================== */
+#define MAC_wakeup_maincnt_maincnt_Pos    (0UL)                     /*!< maincnt (Bit 0)                                       */
+#define MAC_wakeup_maincnt_maincnt_Msk    (0x3ffffffUL)             /*!< maincnt (Bitfield-Mask: 0x3ffffff)                    */
+#define MAC_wakeup_maincnt_startcnt_Pos   (26UL)                    /*!< startcnt (Bit 26)                                     */
+#define MAC_wakeup_maincnt_startcnt_Msk   (0x4000000UL)             /*!< startcnt (Bitfield-Mask: 0x01)                        */
+#define MAC_wakeup_maincnt_regwake_Pos    (27UL)                    /*!< regwake (Bit 27)                                      */
+#define MAC_wakeup_maincnt_regwake_Msk    (0x8000000UL)             /*!< regwake (Bitfield-Mask: 0x01)                         */
+#define MAC_wakeup_maincnt_immwake_Pos    (28UL)                    /*!< immwake (Bit 28)                                      */
+#define MAC_wakeup_maincnt_immwake_Msk    (0x10000000UL)            /*!< immwake (Bitfield-Mask: 0x01)                         */
+#define MAC_wakeup_maincnt_slpack_Pos     (31UL)                    /*!< slpack (Bit 31)                                       */
+#define MAC_wakeup_maincnt_slpack_Msk     (0x80000000UL)            /*!< slpack (Bitfield-Mask: 0x01)                          */
+/* ====================================================  wakeup_waketime  ==================================================== */
+#define MAC_wakeup_waketime_waketime_Pos  (0UL)                     /*!< waketime (Bit 0)                                      */
+#define MAC_wakeup_waketime_waketime_Msk  (0x7ffUL)                 /*!< waketime (Bitfield-Mask: 0x7ff)                       */
+/* ======================================================  dbgport_sel  ====================================================== */
+#define MAC_dbgport_sel_gr_dbg_sel_o_Pos  (0UL)                     /*!< gr_dbg_sel_o (Bit 0)                                  */
+#define MAC_dbgport_sel_gr_dbg_sel_o_Msk  (0xfUL)                   /*!< gr_dbg_sel_o (Bitfield-Mask: 0x0f)                    */
+#define MAC_dbgport_sel_gr_dbg_rxm_sel_o_Pos (4UL)                  /*!< gr_dbg_rxm_sel_o (Bit 4)                              */
+#define MAC_dbgport_sel_gr_dbg_rxm_sel_o_Msk (0x10UL)               /*!< gr_dbg_rxm_sel_o (Bitfield-Mask: 0x01)                */
+#define MAC_dbgport_sel_gr_dbg_cnt_reset_o_Pos (5UL)                /*!< gr_dbg_cnt_reset_o (Bit 5)                            */
+#define MAC_dbgport_sel_gr_dbg_cnt_reset_o_Msk (0x20UL)             /*!< gr_dbg_cnt_reset_o (Bitfield-Mask: 0x01)              */
+#define MAC_dbgport_sel_gr_dbg_src_sel_o_Pos (6UL)                  /*!< gr_dbg_src_sel_o (Bit 6)                              */
+#define MAC_dbgport_sel_gr_dbg_src_sel_o_Msk (0x40UL)               /*!< gr_dbg_src_sel_o (Bitfield-Mask: 0x01)                */
+/* =======================================================  dbg_reg0  ======================================================== */
+#define MAC_dbg_reg0_sh_back_Pos          (8UL)                     /*!< sh_back (Bit 8)                                       */
+#define MAC_dbg_reg0_sh_back_Msk          (0xff00UL)                /*!< sh_back (Bitfield-Mask: 0xff)                         */
+#define MAC_dbg_reg0_dbg_rxm_frm_end_cnt_Pos (16UL)                 /*!< dbg_rxm_frm_end_cnt (Bit 16)                          */
+#define MAC_dbg_reg0_dbg_rxm_frm_end_cnt_Msk (0xffff0000UL)         /*!< dbg_rxm_frm_end_cnt (Bitfield-Mask: 0xffff)           */
+/* ========================================================  rxm_dbg  ======================================================== */
+#define MAC_rxm_dbg_dbg_crc_ok_cnt_Pos    (0UL)                     /*!< dbg_crc_ok_cnt (Bit 0)                                */
+#define MAC_rxm_dbg_dbg_crc_ok_cnt_Msk    (0xffffUL)                /*!< dbg_crc_ok_cnt (Bitfield-Mask: 0xffff)                */
+#define MAC_rxm_dbg_dbg_discard_cnt_Pos   (16UL)                    /*!< dbg_discard_cnt (Bit 16)                              */
+#define MAC_rxm_dbg_dbg_discard_cnt_Msk   (0xffff0000UL)            /*!< dbg_discard_cnt (Bitfield-Mask: 0xffff)               */
+/* =====================================================  sf_order_ctrl  ===================================================== */
+#define MAC_sf_order_ctrl_so_Pos          (0UL)                     /*!< so (Bit 0)                                            */
+#define MAC_sf_order_ctrl_so_Msk          (0xfUL)                   /*!< so (Bitfield-Mask: 0x0f)                              */
+#define MAC_sf_order_ctrl_bo_Pos          (4UL)                     /*!< bo (Bit 4)                                            */
+#define MAC_sf_order_ctrl_bo_Msk          (0xf0UL)                  /*!< bo (Bitfield-Mask: 0x0f)                              */
+/* =======================================================  min_lifs  ======================================================== */
+#define MAC_min_lifs_milp_Pos             (0UL)                     /*!< milp (Bit 0)                                          */
+#define MAC_min_lifs_milp_Msk             (0x3fUL)                  /*!< milp (Bitfield-Mask: 0x3f)                            */
+/* =======================================================  ifs_ctrl  ======================================================== */
+#define MAC_ifs_ctrl_misp_Pos             (0UL)                     /*!< misp (Bit 0)                                          */
+#define MAC_ifs_ctrl_misp_Msk             (0xfUL)                   /*!< misp (Bitfield-Mask: 0x0f)                            */
+#define MAC_ifs_ctrl_txpet_Pos            (4UL)                     /*!< txpet (Bit 4)                                         */
+#define MAC_ifs_ctrl_txpet_Msk            (0xf0UL)                  /*!< txpet (Bitfield-Mask: 0x0f)                           */
+#define MAC_ifs_ctrl_ccachkp_Pos          (8UL)                     /*!< ccachkp (Bit 8)                                       */
+#define MAC_ifs_ctrl_ccachkp_Msk          (0xf00UL)                 /*!< ccachkp (Bitfield-Mask: 0x0f)                         */
+#define MAC_ifs_ctrl_aturn_Pos            (12UL)                    /*!< aturn (Bit 12)                                        */
+#define MAC_ifs_ctrl_aturn_Msk            (0xf000UL)                /*!< aturn (Bitfield-Mask: 0x0f)                           */
+/* ========================================================  tx_ctrl  ======================================================== */
+#define MAC_tx_ctrl_pend_Pos              (16UL)                    /*!< pend (Bit 16)                                         */
+#define MAC_tx_ctrl_pend_Msk              (0x10000UL)               /*!< pend (Bitfield-Mask: 0x01)                            */
+#define MAC_tx_ctrl_indirect_Pos          (17UL)                    /*!< indirect (Bit 17)                                     */
+#define MAC_tx_ctrl_indirect_Msk          (0x20000UL)               /*!< indirect (Bitfield-Mask: 0x01)                        */
+#define MAC_tx_ctrl_mawd_Pos              (24UL)                    /*!< mawd (Bit 24)                                         */
+#define MAC_tx_ctrl_mawd_Msk              (0x7f000000UL)            /*!< mawd (Bitfield-Mask: 0x7f)                            */
+/* ======================================================  beacon_ctrl  ====================================================== */
+#define MAC_beacon_ctrl_intl_Pos          (0UL)                     /*!< intl (Bit 0)                                          */
+#define MAC_beacon_ctrl_intl_Msk          (0x3fUL)                  /*!< intl (Bitfield-Mask: 0x3f)                            */
+#define MAC_beacon_ctrl_aoffset_Pos       (16UL)                    /*!< aoffset (Bit 16)                                      */
+#define MAC_beacon_ctrl_aoffset_Msk       (0xff0000UL)              /*!< aoffset (Bitfield-Mask: 0xff)                         */
+/* =======================================================  txm_state  ======================================================= */
+#define MAC_txm_state_txm_mac_state_Pos   (0UL)                     /*!< txm_mac_state (Bit 0)                                 */
+#define MAC_txm_state_txm_mac_state_Msk   (0x1fUL)                  /*!< txm_mac_state (Bitfield-Mask: 0x1f)                   */
+#define MAC_txm_state_txm_busn_state_Pos  (5UL)                     /*!< txm_busn_state (Bit 5)                                */
+#define MAC_txm_state_txm_busn_state_Msk  (0x60UL)                  /*!< txm_busn_state (Bitfield-Mask: 0x03)                  */
+#define MAC_txm_state_txm_busb_state_Pos  (7UL)                     /*!< txm_busb_state (Bit 7)                                */
+#define MAC_txm_state_txm_busb_state_Msk  (0x180UL)                 /*!< txm_busb_state (Bitfield-Mask: 0x03)                  */
+#define MAC_txm_state_txm_busg1_state_Pos (9UL)                     /*!< txm_busg1_state (Bit 9)                               */
+#define MAC_txm_state_txm_busg1_state_Msk (0x600UL)                 /*!< txm_busg1_state (Bitfield-Mask: 0x03)                 */
+#define MAC_txm_state_txm_busg2_state_Pos (11UL)                    /*!< txm_busg2_state (Bit 11)                              */
+#define MAC_txm_state_txm_busg2_state_Msk (0x1800UL)                /*!< txm_busg2_state (Bitfield-Mask: 0x03)                 */
+#define MAC_txm_state_cfp_state_Pos       (13UL)                    /*!< cfp_state (Bit 13)                                    */
+#define MAC_txm_state_cfp_state_Msk       (0xe000UL)                /*!< cfp_state (Bitfield-Mask: 0x07)                       */
+#define MAC_txm_state_csma_state_Pos      (16UL)                    /*!< csma_state (Bit 16)                                   */
+#define MAC_txm_state_csma_state_Msk      (0x1f0000UL)              /*!< csma_state (Bitfield-Mask: 0x1f)                      */
+#define MAC_txm_state_sf_state_Pos        (21UL)                    /*!< sf_state (Bit 21)                                     */
+#define MAC_txm_state_sf_state_Msk        (0xe00000UL)              /*!< sf_state (Bitfield-Mask: 0x07)                        */
+#define MAC_txm_state_rf_mode_state_Pos   (24UL)                    /*!< rf_mode_state (Bit 24)                                */
+#define MAC_txm_state_rf_mode_state_Msk   (0xf000000UL)             /*!< rf_mode_state (Bitfield-Mask: 0x0f)                   */
+#define MAC_txm_state_gts_state_Pos       (28UL)                    /*!< gts_state (Bit 28)                                    */
+#define MAC_txm_state_gts_state_Msk       (0xf0000000UL)            /*!< gts_state (Bitfield-Mask: 0x0f)                       */
+/* =======================================================  txb_trig  ======================================================== */
+#define MAC_txb_trig_txbcntrig_Pos        (0UL)                     /*!< txbcntrig (Bit 0)                                     */
+#define MAC_txb_trig_txbcntrig_Msk        (0x1UL)                   /*!< txbcntrig (Bitfield-Mask: 0x01)                       */
+#define MAC_txb_trig_txbsecen_Pos         (1UL)                     /*!< txbsecen (Bit 1)                                      */
+#define MAC_txb_trig_txbsecen_Msk         (0x2UL)                   /*!< txbsecen (Bitfield-Mask: 0x01)                        */
+/* =======================================================  txn_trig  ======================================================== */
+#define MAC_txn_trig_txntrig_Pos          (0UL)                     /*!< txntrig (Bit 0)                                       */
+#define MAC_txn_trig_txntrig_Msk          (0x1UL)                   /*!< txntrig (Bitfield-Mask: 0x01)                         */
+#define MAC_txn_trig_txnsecen_Pos         (1UL)                     /*!< txnsecen (Bit 1)                                      */
+#define MAC_txn_trig_txnsecen_Msk         (0x2UL)                   /*!< txnsecen (Bitfield-Mask: 0x01)                        */
+#define MAC_txn_trig_txnackreq_Pos        (2UL)                     /*!< txnackreq (Bit 2)                                     */
+#define MAC_txn_trig_txnackreq_Msk        (0x4UL)                   /*!< txnackreq (Bitfield-Mask: 0x01)                       */
+#define MAC_txn_trig_ack_type_Pos         (3UL)                     /*!< ack_type (Bit 3)                                      */
+#define MAC_txn_trig_ack_type_Msk         (0x8UL)                   /*!< ack_type (Bitfield-Mask: 0x01)                        */
+#define MAC_txn_trig_txnfrmtry_Pos        (5UL)                     /*!< txnfrmtry (Bit 5)                                     */
+#define MAC_txn_trig_txnfrmtry_Msk        (0xe0UL)                  /*!< txnfrmtry (Bitfield-Mask: 0x07)                       */
+/* =======================================================  txg1_trig  ======================================================= */
+#define MAC_txg1_trig_txg1trig_Pos        (0UL)                     /*!< txg1trig (Bit 0)                                      */
+#define MAC_txg1_trig_txg1trig_Msk        (0x1UL)                   /*!< txg1trig (Bitfield-Mask: 0x01)                        */
+#define MAC_txg1_trig_txg1secen_Pos       (1UL)                     /*!< txg1secen (Bit 1)                                     */
+#define MAC_txg1_trig_txg1secen_Msk       (0x2UL)                   /*!< txg1secen (Bitfield-Mask: 0x01)                       */
+#define MAC_txg1_trig_txg1ackreq_Pos      (2UL)                     /*!< txg1ackreq (Bit 2)                                    */
+#define MAC_txg1_trig_txg1ackreq_Msk      (0x4UL)                   /*!< txg1ackreq (Bitfield-Mask: 0x01)                      */
+#define MAC_txg1_trig_txg1slot_Pos        (3UL)                     /*!< txg1slot (Bit 3)                                      */
+#define MAC_txg1_trig_txg1slot_Msk        (0x38UL)                  /*!< txg1slot (Bitfield-Mask: 0x07)                        */
+#define MAC_txg1_trig_txg1ifetry_Pos      (6UL)                     /*!< txg1ifetry (Bit 6)                                    */
+#define MAC_txg1_trig_txg1ifetry_Msk      (0xc0UL)                  /*!< txg1ifetry (Bitfield-Mask: 0x03)                      */
+/* =======================================================  txg2_trig  ======================================================= */
+#define MAC_txg2_trig_txg2trig_Pos        (0UL)                     /*!< txg2trig (Bit 0)                                      */
+#define MAC_txg2_trig_txg2trig_Msk        (0x1UL)                   /*!< txg2trig (Bitfield-Mask: 0x01)                        */
+#define MAC_txg2_trig_txg2secen_Pos       (1UL)                     /*!< txg2secen (Bit 1)                                     */
+#define MAC_txg2_trig_txg2secen_Msk       (0x2UL)                   /*!< txg2secen (Bitfield-Mask: 0x01)                       */
+#define MAC_txg2_trig_txg2ackreq_Pos      (2UL)                     /*!< txg2ackreq (Bit 2)                                    */
+#define MAC_txg2_trig_txg2ackreq_Msk      (0x4UL)                   /*!< txg2ackreq (Bitfield-Mask: 0x01)                      */
+#define MAC_txg2_trig_txg2slot_Pos        (3UL)                     /*!< txg2slot (Bit 3)                                      */
+#define MAC_txg2_trig_txg2slot_Msk        (0x38UL)                  /*!< txg2slot (Bitfield-Mask: 0x07)                        */
+#define MAC_txg2_trig_txg2ifetry_Pos      (6UL)                     /*!< txg2ifetry (Bit 6)                                    */
+#define MAC_txg2_trig_txg2ifetry_Msk      (0xc0UL)                  /*!< txg2ifetry (Bitfield-Mask: 0x03)                      */
+/* ======================================================  txm_status  ======================================================= */
+#define MAC_txm_status_sfcntr_Pos         (0UL)                     /*!< sfcntr (Bit 0)                                        */
+#define MAC_txm_status_sfcntr_Msk         (0xffffffUL)              /*!< sfcntr (Bitfield-Mask: 0xffffff)                      */
+#define MAC_txm_status_txg1retryn_Pos     (24UL)                    /*!< txg1retryn (Bit 24)                                   */
+#define MAC_txm_status_txg1retryn_Msk     (0x3000000UL)             /*!< txg1retryn (Bitfield-Mask: 0x03)                      */
+#define MAC_txm_status_txg2retryn_Pos     (26UL)                    /*!< txg2retryn (Bit 26)                                   */
+#define MAC_txm_status_txg2retryn_Msk     (0xc000000UL)             /*!< txg2retryn (Bitfield-Mask: 0x03)                      */
+#define MAC_txm_status_pendack_Pos        (28UL)                    /*!< pendack (Bit 28)                                      */
+#define MAC_txm_status_pendack_Msk        (0x10000000UL)            /*!< pendack (Bitfield-Mask: 0x01)                         */
+/* =======================================================  gts_ctrl  ======================================================== */
+#define MAC_gts_ctrl_enh_ack_trig_Pos     (0UL)                     /*!< enh_ack_trig (Bit 0)                                  */
+#define MAC_gts_ctrl_enh_ack_trig_Msk     (0x1UL)                   /*!< enh_ack_trig (Bitfield-Mask: 0x01)                    */
+#define MAC_gts_ctrl_sec_enh_ack_Pos      (1UL)                     /*!< sec_enh_ack (Bit 1)                                   */
+#define MAC_gts_ctrl_sec_enh_ack_Msk      (0x2UL)                   /*!< sec_enh_ack (Bitfield-Mask: 0x01)                     */
+#define MAC_gts_ctrl_gtsswitch_Pos        (2UL)                     /*!< gtsswitch (Bit 2)                                     */
+#define MAC_gts_ctrl_gtsswitch_Msk        (0x4UL)                   /*!< gtsswitch (Bitfield-Mask: 0x01)                       */
+#define MAC_gts_ctrl_nocsmag_Pos          (3UL)                     /*!< nocsmag (Bit 3)                                       */
+#define MAC_gts_ctrl_nocsmag_Msk          (0x8UL)                   /*!< nocsmag (Bitfield-Mask: 0x01)                         */
+#define MAC_gts_ctrl_cap_Pos              (4UL)                     /*!< cap (Bit 4)                                           */
+#define MAC_gts_ctrl_cap_Msk              (0xf0UL)                  /*!< cap (Bitfield-Mask: 0x0f)                             */
+#define MAC_gts_ctrl_gts1_Pos             (8UL)                     /*!< gts1 (Bit 8)                                          */
+#define MAC_gts_ctrl_gts1_Msk             (0xf00UL)                 /*!< gts1 (Bitfield-Mask: 0x0f)                            */
+#define MAC_gts_ctrl_gts2_Pos             (12UL)                    /*!< gts2 (Bit 12)                                         */
+#define MAC_gts_ctrl_gts2_Msk             (0xf000UL)                /*!< gts2 (Bitfield-Mask: 0x0f)                            */
+#define MAC_gts_ctrl_gts3_Pos             (16UL)                    /*!< gts3 (Bit 16)                                         */
+#define MAC_gts_ctrl_gts3_Msk             (0xf0000UL)               /*!< gts3 (Bitfield-Mask: 0x0f)                            */
+#define MAC_gts_ctrl_gts4_Pos             (20UL)                    /*!< gts4 (Bit 20)                                         */
+#define MAC_gts_ctrl_gts4_Msk             (0xf00000UL)              /*!< gts4 (Bitfield-Mask: 0x0f)                            */
+#define MAC_gts_ctrl_gts5_Pos             (24UL)                    /*!< gts5 (Bit 24)                                         */
+#define MAC_gts_ctrl_gts5_Msk             (0xf000000UL)             /*!< gts5 (Bitfield-Mask: 0x0f)                            */
+#define MAC_gts_ctrl_gts6_Pos             (28UL)                    /*!< gts6 (Bit 28)                                         */
+#define MAC_gts_ctrl_gts6_Msk             (0xf0000000UL)            /*!< gts6 (Bitfield-Mask: 0x0f)                            */
+/* =======================================================  csma_ctrl  ======================================================= */
+#define MAC_csma_ctrl_csma_cw_Pos         (0UL)                     /*!< csma_cw (Bit 0)                                       */
+#define MAC_csma_ctrl_csma_cw_Msk         (0x3UL)                   /*!< csma_cw (Bitfield-Mask: 0x03)                         */
+#define MAC_csma_ctrl_csma_be_Pos         (2UL)                     /*!< csma_be (Bit 2)                                       */
+#define MAC_csma_ctrl_csma_be_Msk         (0x3cUL)                  /*!< csma_be (Bitfield-Mask: 0x0f)                         */
+#define MAC_csma_ctrl_csma_nb_Pos         (6UL)                     /*!< csma_nb (Bit 6)                                       */
+#define MAC_csma_ctrl_csma_nb_Msk         (0x3c0UL)                 /*!< csma_nb (Bitfield-Mask: 0x0f)                         */
+#define MAC_csma_ctrl_txretry_Pos         (10UL)                    /*!< txretry (Bit 10)                                      */
+#define MAC_csma_ctrl_txretry_Msk         (0x1c00UL)                /*!< txretry (Bitfield-Mask: 0x07)                         */
+#define MAC_csma_ctrl_nocsman_Pos         (15UL)                    /*!< nocsman (Bit 15)                                      */
+#define MAC_csma_ctrl_nocsman_Msk         (0x8000UL)                /*!< nocsman (Bitfield-Mask: 0x01)                         */
+#define MAC_csma_ctrl_macminbe_Pos        (16UL)                    /*!< macminbe (Bit 16)                                     */
+#define MAC_csma_ctrl_macminbe_Msk        (0xf0000UL)               /*!< macminbe (Bitfield-Mask: 0x0f)                        */
+#define MAC_csma_ctrl_macmaxbe_Pos        (20UL)                    /*!< macmaxbe (Bit 20)                                     */
+#define MAC_csma_ctrl_macmaxbe_Msk        (0xf00000UL)              /*!< macmaxbe (Bitfield-Mask: 0x0f)                        */
+#define MAC_csma_ctrl_csmabf_Pos          (24UL)                    /*!< csmabf (Bit 24)                                       */
+#define MAC_csma_ctrl_csmabf_Msk          (0xf000000UL)             /*!< csmabf (Bitfield-Mask: 0x0f)                          */
+#define MAC_csma_ctrl_slotted_Pos         (28UL)                    /*!< slotted (Bit 28)                                      */
+#define MAC_csma_ctrl_slotted_Msk         (0x10000000UL)            /*!< slotted (Bitfield-Mask: 0x01)                         */
+#define MAC_csma_ctrl_batlifeext_Pos      (29UL)                    /*!< batlifeext (Bit 29)                                   */
+#define MAC_csma_ctrl_batlifeext_Msk      (0x20000000UL)            /*!< batlifeext (Bitfield-Mask: 0x01)                      */
+#define MAC_csma_ctrl_backoff_nb_gain_Pos (30UL)                    /*!< backoff_nb_gain (Bit 30)                              */
+#define MAC_csma_ctrl_backoff_nb_gain_Msk (0xc0000000UL)            /*!< backoff_nb_gain (Bitfield-Mask: 0x03)                 */
+/* ====================================================  tx_settle_ctrl  ===================================================== */
+#define MAC_tx_settle_ctrl_txont_Pos      (0UL)                     /*!< txont (Bit 0)                                         */
+#define MAC_tx_settle_ctrl_txont_Msk      (0x1ffUL)                 /*!< txont (Bitfield-Mask: 0x1ff)                          */
+#define MAC_tx_settle_ctrl_txonts_Pos     (9UL)                     /*!< txonts (Bit 9)                                        */
+#define MAC_tx_settle_ctrl_txonts_Msk     (0x1e00UL)                /*!< txonts (Bitfield-Mask: 0x0f)                          */
+#define MAC_tx_settle_ctrl_pacont_Pos     (16UL)                    /*!< pacont (Bit 16)                                       */
+#define MAC_tx_settle_ctrl_pacont_Msk     (0x1ff0000UL)             /*!< pacont (Bitfield-Mask: 0x1ff)                         */
+#define MAC_tx_settle_ctrl_paonts_Pos     (25UL)                    /*!< paonts (Bit 25)                                       */
+#define MAC_tx_settle_ctrl_paonts_Msk     (0x1e000000UL)            /*!< paonts (Bitfield-Mask: 0x0f)                          */
+/* ====================================================  tx_frm_len_err  ===================================================== */
+#define MAC_tx_frm_len_err_txg2lerr_Pos   (0UL)                     /*!< txg2lerr (Bit 0)                                      */
+#define MAC_tx_frm_len_err_txg2lerr_Msk   (0x1UL)                   /*!< txg2lerr (Bitfield-Mask: 0x01)                        */
+#define MAC_tx_frm_len_err_txg1lerr_Pos   (1UL)                     /*!< txg1lerr (Bit 1)                                      */
+#define MAC_tx_frm_len_err_txg1lerr_Msk   (0x2UL)                   /*!< txg1lerr (Bitfield-Mask: 0x01)                        */
+#define MAC_tx_frm_len_err_txnlerr_Pos    (2UL)                     /*!< txnlerr (Bit 2)                                       */
+#define MAC_tx_frm_len_err_txnlerr_Msk    (0x4UL)                   /*!< txnlerr (Bitfield-Mask: 0x01)                         */
+#define MAC_tx_frm_len_err_txblerr_Pos    (3UL)                     /*!< txblerr (Bit 3)                                       */
+#define MAC_tx_frm_len_err_txblerr_Msk    (0x8UL)                   /*!< txblerr (Bitfield-Mask: 0x01)                         */
+/* =========================================================  txsr  ========================================================== */
+#define MAC_txsr_txns_Pos                 (0UL)                     /*!< txns (Bit 0)                                          */
+#define MAC_txsr_txns_Msk                 (0x1UL)                   /*!< txns (Bitfield-Mask: 0x01)                            */
+#define MAC_txsr_txg1s_Pos                (1UL)                     /*!< txg1s (Bit 1)                                         */
+#define MAC_txsr_txg1s_Msk                (0x2UL)                   /*!< txg1s (Bitfield-Mask: 0x01)                           */
+#define MAC_txsr_txg2s_Pos                (2UL)                     /*!< txg2s (Bit 2)                                         */
+#define MAC_txsr_txg2s_Msk                (0x4UL)                   /*!< txg2s (Bitfield-Mask: 0x01)                           */
+#define MAC_txsr_txg1fnt_Pos              (3UL)                     /*!< txg1fnt (Bit 3)                                       */
+#define MAC_txsr_txg1fnt_Msk              (0x8UL)                   /*!< txg1fnt (Bitfield-Mask: 0x01)                         */
+#define MAC_txsr_txg2fnt_Pos              (4UL)                     /*!< txg2fnt (Bit 4)                                       */
+#define MAC_txsr_txg2fnt_Msk              (0x10UL)                  /*!< txg2fnt (Bitfield-Mask: 0x01)                         */
+#define MAC_txsr_ccafail_Pos              (5UL)                     /*!< ccafail (Bit 5)                                       */
+#define MAC_txsr_ccafail_Msk              (0x20UL)                  /*!< ccafail (Bitfield-Mask: 0x01)                         */
+/* =====================================================  tx_time_stamp  ===================================================== */
+#define MAC_tx_time_stamp_txm_tx_timestmp_clk_Pos (0UL)             /*!< txm_tx_timestmp_clk (Bit 0)                           */
+#define MAC_tx_time_stamp_txm_tx_timestmp_clk_Msk (0x3fffffUL)      /*!< txm_tx_timestmp_clk (Bitfield-Mask: 0x3fffff)         */
+#define MAC_tx_time_stamp_txm_tx_timestmp_cntr_Pos (22UL)           /*!< txm_tx_timestmp_cntr (Bit 22)                         */
+#define MAC_tx_time_stamp_txm_tx_timestmp_cntr_Msk (0xffc00000UL)   /*!< txm_tx_timestmp_cntr (Bitfield-Mask: 0x3ff)           */
+/* ===================================================  tx_given_time_set  =================================================== */
+#define MAC_tx_given_time_set_txn_nclk_Pos (0UL)                    /*!< txn_nclk (Bit 0)                                      */
+#define MAC_tx_given_time_set_txn_nclk_Msk (0x3ffffUL)              /*!< txn_nclk (Bitfield-Mask: 0x3ffff)                     */
+#define MAC_tx_given_time_set_txn_ckc_Pos (18UL)                    /*!< txn_ckc (Bit 18)                                      */
+#define MAC_tx_given_time_set_txn_ckc_Msk (0xffc0000UL)             /*!< txn_ckc (Bitfield-Mask: 0x3ff)                        */
+#define MAC_tx_given_time_set_schtxnocca_Pos (28UL)                 /*!< schtxnocca (Bit 28)                                   */
+#define MAC_tx_given_time_set_schtxnocca_Msk (0x10000000UL)         /*!< schtxnocca (Bitfield-Mask: 0x01)                      */
+#define MAC_tx_given_time_set_txntmren_Pos (31UL)                   /*!< txntmren (Bit 31)                                     */
+#define MAC_tx_given_time_set_txntmren_Msk (0x80000000UL)           /*!< txntmren (Bitfield-Mask: 0x01)                        */
+/* =================================================  tx_given_time_status  ================================================== */
+#define MAC_tx_given_time_status_zbrf_tx_given_time_encoun_tx_Pos (0UL) /*!< zbrf_tx_given_time_encoun_tx (Bit 0)              */
+#define MAC_tx_given_time_status_zbrf_tx_given_time_encoun_tx_Msk (0x1UL) /*!< zbrf_tx_given_time_encoun_tx (Bitfield-Mask: 0x01) */
+#define MAC_tx_given_time_status_zbrf_tx_given_time_encoun_rx_Pos (1UL) /*!< zbrf_tx_given_time_encoun_rx (Bit 1)              */
+#define MAC_tx_given_time_status_zbrf_tx_given_time_encoun_rx_Msk (0x2UL) /*!< zbrf_tx_given_time_encoun_rx (Bitfield-Mask: 0x01) */
+#define MAC_tx_given_time_status_zbrf_tx_given_time_obsolete_Pos (2UL) /*!< zbrf_tx_given_time_obsolete (Bit 2)                */
+#define MAC_tx_given_time_status_zbrf_tx_given_time_obsolete_Msk (0x4UL) /*!< zbrf_tx_given_time_obsolete (Bitfield-Mask: 0x01) */
+#define MAC_tx_given_time_status_zbrf_tx_given_time_not_gnt_Pos (3UL) /*!< zbrf_tx_given_time_not_gnt (Bit 3)                  */
+#define MAC_tx_given_time_status_zbrf_tx_given_time_not_gnt_Msk (0x8UL) /*!< zbrf_tx_given_time_not_gnt (Bitfield-Mask: 0x01)  */
+#define MAC_tx_given_time_status_zbrf_tx_given_time_not_in_recv_Pos (4UL) /*!< zbrf_tx_given_time_not_in_recv (Bit 4)          */
+#define MAC_tx_given_time_status_zbrf_tx_given_time_not_in_recv_Msk (0x10UL) /*!< zbrf_tx_given_time_not_in_recv (Bitfield-Mask: 0x01) */
+/* =====================================================  gts_slot_cfg  ====================================================== */
+#define MAC_gts_slot_cfg_gts_slot_en_Pos  (0UL)                     /*!< gts_slot_en (Bit 0)                                   */
+#define MAC_gts_slot_cfg_gts_slot_en_Msk  (0x7fUL)                  /*!< gts_slot_en (Bitfield-Mask: 0x7f)                     */
+#define MAC_gts_slot_cfg_gts_slot_trx_Pos (8UL)                     /*!< gts_slot_trx (Bit 8)                                  */
+#define MAC_gts_slot_cfg_gts_slot_trx_Msk (0x7f00UL)                /*!< gts_slot_trx (Bitfield-Mask: 0x7f)                    */
+/* =====================================================  rx_fltr_ctrl  ====================================================== */
+#define MAC_rx_fltr_ctrl_promi_Pos        (0UL)                     /*!< promi (Bit 0)                                         */
+#define MAC_rx_fltr_ctrl_promi_Msk        (0x1UL)                   /*!< promi (Bitfield-Mask: 0x01)                           */
+#define MAC_rx_fltr_ctrl_errpkt_Pos       (1UL)                     /*!< errpkt (Bit 1)                                        */
+#define MAC_rx_fltr_ctrl_errpkt_Msk       (0x2UL)                   /*!< errpkt (Bitfield-Mask: 0x01)                          */
+#define MAC_rx_fltr_ctrl_scanmode_Pos     (2UL)                     /*!< scanmode (Bit 2)                                      */
+#define MAC_rx_fltr_ctrl_scanmode_Msk     (0x4UL)                   /*!< scanmode (Bitfield-Mask: 0x01)                        */
+#define MAC_rx_fltr_ctrl_group_rxmode_Pos (3UL)                     /*!< group_rxmode (Bit 3)                                  */
+#define MAC_rx_fltr_ctrl_group_rxmode_Msk (0x8UL)                   /*!< group_rxmode (Bitfield-Mask: 0x01)                    */
+#define MAC_rx_fltr_ctrl_implicit_broadcast_Pos (4UL)               /*!< implicit_broadcast (Bit 4)                            */
+#define MAC_rx_fltr_ctrl_implicit_broadcast_Msk (0x10UL)            /*!< implicit_broadcast (Bitfield-Mask: 0x01)              */
+#define MAC_rx_fltr_ctrl_rf_early_term_Pos (5UL)                    /*!< rf_early_term (Bit 5)                                 */
+#define MAC_rx_fltr_ctrl_rf_early_term_Msk (0x20UL)                 /*!< rf_early_term (Bitfield-Mask: 0x01)                   */
+#define MAC_rx_fltr_ctrl_frm06_rx_early_Pos (6UL)                   /*!< frm06_rx_early (Bit 6)                                */
+#define MAC_rx_fltr_ctrl_frm06_rx_early_Msk (0x40UL)                /*!< frm06_rx_early (Bitfield-Mask: 0x01)                  */
+#define MAC_rx_fltr_ctrl_rxm_force_crc_Pos (8UL)                    /*!< rxm_force_crc (Bit 8)                                 */
+#define MAC_rx_fltr_ctrl_rxm_force_crc_Msk (0x100UL)                /*!< rxm_force_crc (Bitfield-Mask: 0x01)                   */
+/* =======================================================  rxfrmtype  ======================================================= */
+#define MAC_rxfrmtype_rxftype_Pos         (0UL)                     /*!< rxftype (Bit 0)                                       */
+#define MAC_rxfrmtype_rxftype_Msk         (0xffUL)                  /*!< rxftype (Bitfield-Mask: 0xff)                         */
+#define MAC_rxfrmtype_rxftype15_Pos       (8UL)                     /*!< rxftype15 (Bit 8)                                     */
+#define MAC_rxfrmtype_rxftype15_Msk       (0xff00UL)                /*!< rxftype15 (Bitfield-Mask: 0xff)                       */
+/* =====================================================  group_eadr_l  ====================================================== */
+#define MAC_group_eadr_l_group_ext_addr_l_Pos (0UL)                 /*!< group_ext_addr_l (Bit 0)                              */
+#define MAC_group_eadr_l_group_ext_addr_l_Msk (0xffffffffUL)        /*!< group_ext_addr_l (Bitfield-Mask: 0xffffffff)          */
+/* =====================================================  group_eadr_h  ====================================================== */
+#define MAC_group_eadr_h_group_ext_addr_h_Pos (0UL)                 /*!< group_ext_addr_h (Bit 0)                              */
+#define MAC_group_eadr_h_group_ext_addr_h_Msk (0xffffffffUL)        /*!< group_ext_addr_h (Bitfield-Mask: 0xffffffff)          */
+/* =====================================================  assoc_eadr_l  ====================================================== */
+#define MAC_assoc_eadr_l_assoeadr_l_Pos   (0UL)                     /*!< assoeadr_l (Bit 0)                                    */
+#define MAC_assoc_eadr_l_assoeadr_l_Msk   (0xffffffffUL)            /*!< assoeadr_l (Bitfield-Mask: 0xffffffff)                */
+/* =====================================================  assoc_eadr_h  ====================================================== */
+#define MAC_assoc_eadr_h_assoeadr_h_Pos   (0UL)                     /*!< assoeadr_h (Bit 0)                                    */
+#define MAC_assoc_eadr_h_assoeadr_h_Msk   (0xffffffffUL)            /*!< assoeadr_h (Bitfield-Mask: 0xffffffff)                */
+/* ======================================================  assoc_sadr  ======================================================= */
+#define MAC_assoc_sadr_assosadr_Pos       (0UL)                     /*!< assosadr (Bit 0)                                      */
+#define MAC_assoc_sadr_assosadr_Msk       (0xffffUL)                /*!< assosadr (Bitfield-Mask: 0xffff)                      */
+/* ====================================================  assoc_bcn_ctrl  ===================================================== */
+#define MAC_assoc_bcn_ctrl_abctrl_Pos     (0UL)                     /*!< abctrl (Bit 0)                                        */
+#define MAC_assoc_bcn_ctrl_abctrl_Msk     (0x1UL)                   /*!< abctrl (Bitfield-Mask: 0x01)                          */
+/* ========================================================  rxm_fch  ======================================================== */
+#define MAC_rxm_fch_frame_type_Pos        (0UL)                     /*!< frame_type (Bit 0)                                    */
+#define MAC_rxm_fch_frame_type_Msk        (0x7UL)                   /*!< frame_type (Bitfield-Mask: 0x07)                      */
+#define MAC_rxm_fch_sec_en_Pos            (3UL)                     /*!< sec_en (Bit 3)                                        */
+#define MAC_rxm_fch_sec_en_Msk            (0x8UL)                   /*!< sec_en (Bitfield-Mask: 0x01)                          */
+#define MAC_rxm_fch_pend_Pos              (4UL)                     /*!< pend (Bit 4)                                          */
+#define MAC_rxm_fch_pend_Msk              (0x10UL)                  /*!< pend (Bitfield-Mask: 0x01)                            */
+#define MAC_rxm_fch_ack_req_Pos           (5UL)                     /*!< ack_req (Bit 5)                                       */
+#define MAC_rxm_fch_ack_req_Msk           (0x20UL)                  /*!< ack_req (Bitfield-Mask: 0x01)                         */
+#define MAC_rxm_fch_panid_comp_Pos        (6UL)                     /*!< panid_comp (Bit 6)                                    */
+#define MAC_rxm_fch_panid_comp_Msk        (0x40UL)                  /*!< panid_comp (Bitfield-Mask: 0x01)                      */
+#define MAC_rxm_fch_seq_comp_Pos          (8UL)                     /*!< seq_comp (Bit 8)                                      */
+#define MAC_rxm_fch_seq_comp_Msk          (0x100UL)                 /*!< seq_comp (Bitfield-Mask: 0x01)                        */
+#define MAC_rxm_fch_ie_exist_Pos          (9UL)                     /*!< ie_exist (Bit 9)                                      */
+#define MAC_rxm_fch_ie_exist_Msk          (0x200UL)                 /*!< ie_exist (Bitfield-Mask: 0x01)                        */
+#define MAC_rxm_fch_dst_adr_mode_Pos      (10UL)                    /*!< dst_adr_mode (Bit 10)                                 */
+#define MAC_rxm_fch_dst_adr_mode_Msk      (0xc00UL)                 /*!< dst_adr_mode (Bitfield-Mask: 0x03)                    */
+#define MAC_rxm_fch_frm_ver_Pos           (12UL)                    /*!< frm_ver (Bit 12)                                      */
+#define MAC_rxm_fch_frm_ver_Msk           (0x3000UL)                /*!< frm_ver (Bitfield-Mask: 0x03)                         */
+#define MAC_rxm_fch_src_adr_mode_Pos      (14UL)                    /*!< src_adr_mode (Bit 14)                                 */
+#define MAC_rxm_fch_src_adr_mode_Msk      (0xc000UL)                /*!< src_adr_mode (Bitfield-Mask: 0x03)                    */
+#define MAC_rxm_fch_mp_frame_type_Pos     (16UL)                    /*!< mp_frame_type (Bit 16)                                */
+#define MAC_rxm_fch_mp_frame_type_Msk     (0x70000UL)               /*!< mp_frame_type (Bitfield-Mask: 0x07)                   */
+#define MAC_rxm_fch_mp_long_frm_Pos       (19UL)                    /*!< mp_long_frm (Bit 19)                                  */
+#define MAC_rxm_fch_mp_long_frm_Msk       (0x80000UL)               /*!< mp_long_frm (Bitfield-Mask: 0x01)                     */
+#define MAC_rxm_fch_mp_dst_adr_mode_Pos   (20UL)                    /*!< mp_dst_adr_mode (Bit 20)                              */
+#define MAC_rxm_fch_mp_dst_adr_mode_Msk   (0x300000UL)              /*!< mp_dst_adr_mode (Bitfield-Mask: 0x03)                 */
+#define MAC_rxm_fch_mp_src_adr_mode_Pos   (22UL)                    /*!< mp_src_adr_mode (Bit 22)                              */
+#define MAC_rxm_fch_mp_src_adr_mode_Msk   (0xc00000UL)              /*!< mp_src_adr_mode (Bitfield-Mask: 0x03)                 */
+#define MAC_rxm_fch_mp_panid_exist_Pos    (24UL)                    /*!< mp_panid_exist (Bit 24)                               */
+#define MAC_rxm_fch_mp_panid_exist_Msk    (0x1000000UL)             /*!< mp_panid_exist (Bitfield-Mask: 0x01)                  */
+#define MAC_rxm_fch_mp_sec_en_Pos         (25UL)                    /*!< mp_sec_en (Bit 25)                                    */
+#define MAC_rxm_fch_mp_sec_en_Msk         (0x2000000UL)             /*!< mp_sec_en (Bitfield-Mask: 0x01)                       */
+#define MAC_rxm_fch_mp_seq_comp_Pos       (26UL)                    /*!< mp_seq_comp (Bit 26)                                  */
+#define MAC_rxm_fch_mp_seq_comp_Msk       (0x4000000UL)             /*!< mp_seq_comp (Bitfield-Mask: 0x01)                     */
+#define MAC_rxm_fch_mp_frm_pend_Pos       (27UL)                    /*!< mp_frm_pend (Bit 27)                                  */
+#define MAC_rxm_fch_mp_frm_pend_Msk       (0x8000000UL)             /*!< mp_frm_pend (Bitfield-Mask: 0x01)                     */
+#define MAC_rxm_fch_mp_frm_ver_Pos        (28UL)                    /*!< mp_frm_ver (Bit 28)                                   */
+#define MAC_rxm_fch_mp_frm_ver_Msk        (0x30000000UL)            /*!< mp_frm_ver (Bitfield-Mask: 0x03)                      */
+#define MAC_rxm_fch_mp_ack_req_Pos        (30UL)                    /*!< mp_ack_req (Bit 30)                                   */
+#define MAC_rxm_fch_mp_ack_req_Msk        (0x40000000UL)            /*!< mp_ack_req (Bitfield-Mask: 0x01)                      */
+#define MAC_rxm_fch_rxm_fchmp_ie_exist_Pos (31UL)                   /*!< rxm_fchmp_ie_exist (Bit 31)                           */
+#define MAC_rxm_fch_rxm_fchmp_ie_exist_Msk (0x80000000UL)           /*!< rxm_fchmp_ie_exist (Bitfield-Mask: 0x01)              */
+/* ====================================================  rx_sn_ie_update  ==================================================== */
+#define MAC_rx_sn_ie_update_seq_num_Pos   (0UL)                     /*!< seq_num (Bit 0)                                       */
+#define MAC_rx_sn_ie_update_seq_num_Msk   (0xffUL)                  /*!< seq_num (Bitfield-Mask: 0xff)                         */
+#define MAC_rx_sn_ie_update_hdr_ie_term_Pos (8UL)                   /*!< hdr_ie_term (Bit 8)                                   */
+#define MAC_rx_sn_ie_update_hdr_ie_term_Msk (0x100UL)               /*!< hdr_ie_term (Bitfield-Mask: 0x01)                     */
+#define MAC_rx_sn_ie_update_csl_update_Pos (9UL)                    /*!< csl_update (Bit 9)                                    */
+#define MAC_rx_sn_ie_update_csl_update_Msk (0x200UL)                /*!< csl_update (Bitfield-Mask: 0x01)                      */
+#define MAC_rx_sn_ie_update_tc_update_Pos (10UL)                    /*!< tc_update (Bit 10)                                    */
+#define MAC_rx_sn_ie_update_tc_update_Msk (0x400UL)                 /*!< tc_update (Bitfield-Mask: 0x01)                       */
+/* =======================================================  rx_csl_ie  ======================================================= */
+#define MAC_rx_csl_ie_csl_period_Pos      (0UL)                     /*!< csl_period (Bit 0)                                    */
+#define MAC_rx_csl_ie_csl_period_Msk      (0xffffUL)                /*!< csl_period (Bitfield-Mask: 0xffff)                    */
+#define MAC_rx_csl_ie_csl_phase_Pos       (16UL)                    /*!< csl_phase (Bit 16)                                    */
+#define MAC_rx_csl_ie_csl_phase_Msk       (0xffff0000UL)            /*!< csl_phase (Bitfield-Mask: 0xffff)                     */
+/* ======================================================  rx_tmcor_ie  ====================================================== */
+#define MAC_rx_tmcor_ie_tm_sync_info_Pos  (0UL)                     /*!< tm_sync_info (Bit 0)                                  */
+#define MAC_rx_tmcor_ie_tm_sync_info_Msk  (0xffffUL)                /*!< tm_sync_info (Bitfield-Mask: 0xffff)                  */
+/* ====================================================  rx_aux_sec_hdr  ===================================================== */
+#define MAC_rx_aux_sec_hdr_rxm_sec_level_Pos (0UL)                  /*!< rxm_sec_level (Bit 0)                                 */
+#define MAC_rx_aux_sec_hdr_rxm_sec_level_Msk (0x7UL)                /*!< rxm_sec_level (Bitfield-Mask: 0x07)                   */
+#define MAC_rx_aux_sec_hdr_rxm_keyid_mode_Pos (3UL)                 /*!< rxm_keyid_mode (Bit 3)                                */
+#define MAC_rx_aux_sec_hdr_rxm_keyid_mode_Msk (0x18UL)              /*!< rxm_keyid_mode (Bitfield-Mask: 0x03)                  */
+#define MAC_rx_aux_sec_hdr_rxm_sec_frm_cnt_comp_Pos (5UL)           /*!< rxm_sec_frm_cnt_comp (Bit 5)                          */
+#define MAC_rx_aux_sec_hdr_rxm_sec_frm_cnt_comp_Msk (0x20UL)        /*!< rxm_sec_frm_cnt_comp (Bitfield-Mask: 0x01)            */
+#define MAC_rx_aux_sec_hdr_rxm_sec_asn_nonce_Pos (6UL)              /*!< rxm_sec_asn_nonce (Bit 6)                             */
+#define MAC_rx_aux_sec_hdr_rxm_sec_asn_nonce_Msk (0x40UL)           /*!< rxm_sec_asn_nonce (Bitfield-Mask: 0x01)               */
+#define MAC_rx_aux_sec_hdr_rxm_key_index_Pos (8UL)                  /*!< rxm_key_index (Bit 8)                                 */
+#define MAC_rx_aux_sec_hdr_rxm_key_index_Msk (0xff00UL)             /*!< rxm_key_index (Bitfield-Mask: 0xff)                   */
+/* =====================================================  rx_aux_frmcnt  ===================================================== */
+#define MAC_rx_aux_frmcnt_rxm_sec_frm_cnt_Pos (0UL)                 /*!< rxm_sec_frm_cnt (Bit 0)                               */
+#define MAC_rx_aux_frmcnt_rxm_sec_frm_cnt_Msk (0xffffffffUL)        /*!< rxm_sec_frm_cnt (Bitfield-Mask: 0xffffffff)           */
+/* ===================================================  rx_aux_key_src_l  ==================================================== */
+#define MAC_rx_aux_key_src_l_rxm_key_src_l_Pos (0UL)                /*!< rxm_key_src_l (Bit 0)                                 */
+#define MAC_rx_aux_key_src_l_rxm_key_src_l_Msk (0xffffffffUL)       /*!< rxm_key_src_l (Bitfield-Mask: 0xffffffff)             */
+/* ===================================================  rx_aux_key_src_h  ==================================================== */
+#define MAC_rx_aux_key_src_h_rxm_key_src_h_Pos (0UL)                /*!< rxm_key_src_h (Bit 0)                                 */
+#define MAC_rx_aux_key_src_h_rxm_key_src_h_Msk (0xffffffffUL)       /*!< rxm_key_src_h (Bitfield-Mask: 0xffffffff)             */
+/* =====================================================  rx_fifo_ctrl  ====================================================== */
+#define MAC_rx_fifo_ctrl_rxfifo2_Pos      (0UL)                     /*!< rxfifo2 (Bit 0)                                       */
+#define MAC_rx_fifo_ctrl_rxfifo2_Msk      (0x1UL)                   /*!< rxfifo2 (Bitfield-Mask: 0x01)                         */
+#define MAC_rx_fifo_ctrl_rxffwr_Pos       (2UL)                     /*!< rxffwr (Bit 2)                                        */
+#define MAC_rx_fifo_ctrl_rxffwr_Msk       (0x4UL)                   /*!< rxffwr (Bitfield-Mask: 0x01)                          */
+#define MAC_rx_fifo_ctrl_rxflush_Pos      (8UL)                     /*!< rxflush (Bit 8)                                       */
+#define MAC_rx_fifo_ctrl_rxflush_Msk      (0x100UL)                 /*!< rxflush (Bitfield-Mask: 0x01)                         */
+/* ====================================================  rx_early_fw_sts  ==================================================== */
+#define MAC_rx_early_fw_sts_rx_early_sts_Pos (0UL)                  /*!< rx_early_sts (Bit 0)                                  */
+#define MAC_rx_early_fw_sts_rx_early_sts_Msk (0xffUL)               /*!< rx_early_sts (Bitfield-Mask: 0xff)                    */
+/* ======================================================  bt_clk_sel  ======================================================= */
+#define MAC_bt_clk_sel_rx_tim_sel_Pos     (0UL)                     /*!< rx_tim_sel (Bit 0)                                    */
+#define MAC_bt_clk_sel_rx_tim_sel_Msk     (0x1UL)                   /*!< rx_tim_sel (Bitfield-Mask: 0x01)                      */
+/* ========================================================  rxm_sts  ======================================================== */
+#define MAC_rxm_sts_pidconflict_Pos       (0UL)                     /*!< pidconflict (Bit 0)                                   */
+#define MAC_rxm_sts_pidconflict_Msk       (0x1UL)                   /*!< pidconflict (Bitfield-Mask: 0x01)                     */
+#define MAC_rxm_sts_rxm_hdr_rdy_Pos       (1UL)                     /*!< rxm_hdr_rdy (Bit 1)                                   */
+#define MAC_rxm_sts_rxm_hdr_rdy_Msk       (0x2UL)                   /*!< rxm_hdr_rdy (Bitfield-Mask: 0x01)                     */
+#define MAC_rxm_sts_sec_dec_err_Pos       (2UL)                     /*!< sec_dec_err (Bit 2)                                   */
+#define MAC_rxm_sts_sec_dec_err_Msk       (0x4UL)                   /*!< sec_dec_err (Bitfield-Mask: 0x01)                     */
+#define MAC_rxm_sts_rxm_crc_err_Pos       (3UL)                     /*!< rxm_crc_err (Bit 3)                                   */
+#define MAC_rxm_sts_rxm_crc_err_Msk       (0x8UL)                   /*!< rxm_crc_err (Bitfield-Mask: 0x01)                     */
+#define MAC_rxm_sts_rxfifo_overflow_Pos   (4UL)                     /*!< rxfifo_overflow (Bit 4)                               */
+#define MAC_rxm_sts_rxfifo_overflow_Msk   (0x10UL)                  /*!< rxfifo_overflow (Bitfield-Mask: 0x01)                 */
+#define MAC_rxm_sts_sec_dec_ignored_Pos   (5UL)                     /*!< sec_dec_ignored (Bit 5)                               */
+#define MAC_rxm_sts_sec_dec_ignored_Msk   (0x20UL)                  /*!< sec_dec_ignored (Bitfield-Mask: 0x01)                 */
+#define MAC_rxm_sts_rxfifo_full_Pos       (7UL)                     /*!< rxfifo_full (Bit 7)                                   */
+#define MAC_rxm_sts_rxfifo_full_Msk       (0x80UL)                  /*!< rxfifo_full (Bitfield-Mask: 0x01)                     */
+#define MAC_rxm_sts_rdff1_Pos             (8UL)                     /*!< rdff1 (Bit 8)                                         */
+#define MAC_rxm_sts_rdff1_Msk             (0x100UL)                 /*!< rdff1 (Bitfield-Mask: 0x01)                           */
+#define MAC_rxm_sts_wrff1_Pos             (9UL)                     /*!< wrff1 (Bit 9)                                         */
+#define MAC_rxm_sts_wrff1_Msk             (0x200UL)                 /*!< wrff1 (Bitfield-Mask: 0x01)                           */
+#define MAC_rxm_sts_last_rxm_hdr_rdy_Pos  (25UL)                    /*!< last_rxm_hdr_rdy (Bit 25)                             */
+#define MAC_rxm_sts_last_rxm_hdr_rdy_Msk  (0x2000000UL)             /*!< last_rxm_hdr_rdy (Bitfield-Mask: 0x01)                */
+#define MAC_rxm_sts_last_rxm_crc_err_Pos  (27UL)                    /*!< last_rxm_crc_err (Bit 27)                             */
+#define MAC_rxm_sts_last_rxm_crc_err_Msk  (0x8000000UL)             /*!< last_rxm_crc_err (Bitfield-Mask: 0x01)                */
+#define MAC_rxm_sts_last_rxfifo_overflow_Pos (28UL)                 /*!< last_rxfifo_overflow (Bit 28)                         */
+#define MAC_rxm_sts_last_rxfifo_overflow_Msk (0x10000000UL)         /*!< last_rxfifo_overflow (Bitfield-Mask: 0x01)            */
+#define MAC_rxm_sts_lwrff1_Pos            (30UL)                    /*!< lwrff1 (Bit 30)                                       */
+#define MAC_rxm_sts_lwrff1_Msk            (0x40000000UL)            /*!< lwrff1 (Bitfield-Mask: 0x01)                          */
+#define MAC_rxm_sts_last_rxfifo_full_Pos  (31UL)                    /*!< last_rxfifo_full (Bit 31)                             */
+#define MAC_rxm_sts_last_rxfifo_full_Msk  (0x80000000UL)            /*!< last_rxfifo_full (Bitfield-Mask: 0x01)                */
+/* =====================================================  rx_src_addr_l  ===================================================== */
+#define MAC_rx_src_addr_l_srcadr_l_Pos    (0UL)                     /*!< srcadr_l (Bit 0)                                      */
+#define MAC_rx_src_addr_l_srcadr_l_Msk    (0xffffffffUL)            /*!< srcadr_l (Bitfield-Mask: 0xffffffff)                  */
+/* =====================================================  rx_src_addr_h  ===================================================== */
+#define MAC_rx_src_addr_h_srcadr_h_Pos    (0UL)                     /*!< srcadr_h (Bit 0)                                      */
+#define MAC_rx_src_addr_h_srcadr_h_Msk    (0xffffffffUL)            /*!< srcadr_h (Bitfield-Mask: 0xffffffff)                  */
+/* ======================================================  rxmbcnt_fsm  ====================================================== */
+#define MAC_rxmbcnt_fsm_rxmbytecnt_Pos    (0UL)                     /*!< rxmbytecnt (Bit 0)                                    */
+#define MAC_rxmbcnt_fsm_rxmbytecnt_Msk    (0xffUL)                  /*!< rxmbytecnt (Bitfield-Mask: 0xff)                      */
+#define MAC_rxmbcnt_fsm_frm_cs_Pos        (8UL)                     /*!< frm_cs (Bit 8)                                        */
+#define MAC_rxmbcnt_fsm_frm_cs_Msk        (0x3f00UL)                /*!< frm_cs (Bitfield-Mask: 0x3f)                          */
+#define MAC_rxmbcnt_fsm_frm_ack_cs_Pos    (16UL)                    /*!< frm_ack_cs (Bit 16)                                   */
+#define MAC_rxmbcnt_fsm_frm_ack_cs_Msk    (0x70000UL)               /*!< frm_ack_cs (Bitfield-Mask: 0x07)                      */
+/* =================================================  src_addr_filter_ctrl  ================================================== */
+#define MAC_src_addr_filter_ctrl_enh_frmpend_en_Pos (0UL)           /*!< enh_frmpend_en (Bit 0)                                */
+#define MAC_src_addr_filter_ctrl_enh_frmpend_en_Msk (0x1UL)         /*!< enh_frmpend_en (Bitfield-Mask: 0x01)                  */
+#define MAC_src_addr_filter_ctrl_pending_ack_Pos (1UL)              /*!< pending_ack (Bit 1)                                   */
+#define MAC_src_addr_filter_ctrl_pending_ack_Msk (0x2UL)            /*!< pending_ack (Bitfield-Mask: 0x01)                     */
+#define MAC_src_addr_filter_ctrl_datreq_cmd_pending_ack_Pos (2UL)   /*!< datreq_cmd_pending_ack (Bit 2)                        */
+#define MAC_src_addr_filter_ctrl_datreq_cmd_pending_ack_Msk (0x4UL) /*!< datreq_cmd_pending_ack (Bitfield-Mask: 0x01)          */
+/* ================================================  src_ext_match_entry_en  ================================================= */
+#define MAC_src_ext_match_entry_en_ext_entry_en_Pos (0UL)           /*!< ext_entry_en (Bit 0)                                  */
+#define MAC_src_ext_match_entry_en_ext_entry_en_Msk (0xffffUL)      /*!< ext_entry_en (Bitfield-Mask: 0xffff)                  */
+/* ===============================================  src_short_match_entry_en  ================================================ */
+#define MAC_src_short_match_entry_en_ext_entry_en_Pos (0UL)         /*!< ext_entry_en (Bit 0)                                  */
+#define MAC_src_short_match_entry_en_ext_entry_en_Msk (0xffffffffUL) /*!< ext_entry_en (Bitfield-Mask: 0xffffffff)             */
+/* ==================================================  src_addr_match_sts  =================================================== */
+#define MAC_src_addr_match_sts_src_match_entry_id_Pos (0UL)         /*!< src_match_entry_id (Bit 0)                            */
+#define MAC_src_addr_match_sts_src_match_entry_id_Msk (0x1fUL)      /*!< src_match_entry_id (Bitfield-Mask: 0x1f)              */
+#define MAC_src_addr_match_sts_src_match_entry_type_Pos (5UL)       /*!< src_match_entry_type (Bit 5)                          */
+#define MAC_src_addr_match_sts_src_match_entry_type_Msk (0x20UL)    /*!< src_match_entry_type (Bitfield-Mask: 0x01)            */
+#define MAC_src_addr_match_sts_src_match_status_update_Pos (6UL)    /*!< src_match_status_update (Bit 6)                       */
+#define MAC_src_addr_match_sts_src_match_status_update_Msk (0x40UL) /*!< src_match_status_update (Bitfield-Mask: 0x01)         */
+/* ===================================================  src_short_match0  ==================================================== */
+#define MAC_src_short_match0_addr_Pos     (0UL)                     /*!< addr (Bit 0)                                          */
+#define MAC_src_short_match0_addr_Msk     (0xffffUL)                /*!< addr (Bitfield-Mask: 0xffff)                          */
+#define MAC_src_short_match0_panid_Pos    (16UL)                    /*!< panid (Bit 16)                                        */
+#define MAC_src_short_match0_panid_Msk    (0xffff0000UL)            /*!< panid (Bitfield-Mask: 0xffff)                         */
+/* ===================================================  src_ext_match0_l  ==================================================== */
+#define MAC_src_ext_match0_l_ext_addr_l_Pos (0UL)                   /*!< ext_addr_l (Bit 0)                                    */
+#define MAC_src_ext_match0_l_ext_addr_l_Msk (0xffffffffUL)          /*!< ext_addr_l (Bitfield-Mask: 0xffffffff)                */
+/* ===================================================  src_short_match1  ==================================================== */
+#define MAC_src_short_match1_addr_Pos     (0UL)                     /*!< addr (Bit 0)                                          */
+#define MAC_src_short_match1_addr_Msk     (0xffffUL)                /*!< addr (Bitfield-Mask: 0xffff)                          */
+#define MAC_src_short_match1_panid_Pos    (16UL)                    /*!< panid (Bit 16)                                        */
+#define MAC_src_short_match1_panid_Msk    (0xffff0000UL)            /*!< panid (Bitfield-Mask: 0xffff)                         */
+/* ===================================================  src_ext_match0_h  ==================================================== */
+#define MAC_src_ext_match0_h_ext_addr_h_Pos (0UL)                   /*!< ext_addr_h (Bit 0)                                    */
+#define MAC_src_ext_match0_h_ext_addr_h_Msk (0xffffffffUL)          /*!< ext_addr_h (Bitfield-Mask: 0xffffffff)                */
+/* ===================================================  src_short_match2  ==================================================== */
+#define MAC_src_short_match2_addr_Pos     (0UL)                     /*!< addr (Bit 0)                                          */
+#define MAC_src_short_match2_addr_Msk     (0xffffUL)                /*!< addr (Bitfield-Mask: 0xffff)                          */
+#define MAC_src_short_match2_panid_Pos    (16UL)                    /*!< panid (Bit 16)                                        */
+#define MAC_src_short_match2_panid_Msk    (0xffff0000UL)            /*!< panid (Bitfield-Mask: 0xffff)                         */
+/* ===================================================  src_ext_match1_l  ==================================================== */
+#define MAC_src_ext_match1_l_ext_addr_l_Pos (0UL)                   /*!< ext_addr_l (Bit 0)                                    */
+#define MAC_src_ext_match1_l_ext_addr_l_Msk (0xffffffffUL)          /*!< ext_addr_l (Bitfield-Mask: 0xffffffff)                */
+/* ===================================================  src_short_match3  ==================================================== */
+#define MAC_src_short_match3_addr_Pos     (0UL)                     /*!< addr (Bit 0)                                          */
+#define MAC_src_short_match3_addr_Msk     (0xffffUL)                /*!< addr (Bitfield-Mask: 0xffff)                          */
+#define MAC_src_short_match3_panid_Pos    (16UL)                    /*!< panid (Bit 16)                                        */
+#define MAC_src_short_match3_panid_Msk    (0xffff0000UL)            /*!< panid (Bitfield-Mask: 0xffff)                         */
+/* ===================================================  src_ext_match1_h  ==================================================== */
+#define MAC_src_ext_match1_h_ext_addr_h_Pos (0UL)                   /*!< ext_addr_h (Bit 0)                                    */
+#define MAC_src_ext_match1_h_ext_addr_h_Msk (0xffffffffUL)          /*!< ext_addr_h (Bitfield-Mask: 0xffffffff)                */
+/* ===================================================  src_short_match4  ==================================================== */
+#define MAC_src_short_match4_addr_Pos     (0UL)                     /*!< addr (Bit 0)                                          */
+#define MAC_src_short_match4_addr_Msk     (0xffffUL)                /*!< addr (Bitfield-Mask: 0xffff)                          */
+#define MAC_src_short_match4_panid_Pos    (16UL)                    /*!< panid (Bit 16)                                        */
+#define MAC_src_short_match4_panid_Msk    (0xffff0000UL)            /*!< panid (Bitfield-Mask: 0xffff)                         */
+/* ===================================================  src_ext_match2_l  ==================================================== */
+#define MAC_src_ext_match2_l_ext_addr_l_Pos (0UL)                   /*!< ext_addr_l (Bit 0)                                    */
+#define MAC_src_ext_match2_l_ext_addr_l_Msk (0xffffffffUL)          /*!< ext_addr_l (Bitfield-Mask: 0xffffffff)                */
+/* ===================================================  src_short_match5  ==================================================== */
+#define MAC_src_short_match5_addr_Pos     (0UL)                     /*!< addr (Bit 0)                                          */
+#define MAC_src_short_match5_addr_Msk     (0xffffUL)                /*!< addr (Bitfield-Mask: 0xffff)                          */
+#define MAC_src_short_match5_panid_Pos    (16UL)                    /*!< panid (Bit 16)                                        */
+#define MAC_src_short_match5_panid_Msk    (0xffff0000UL)            /*!< panid (Bitfield-Mask: 0xffff)                         */
+/* ===================================================  src_ext_match2_h  ==================================================== */
+#define MAC_src_ext_match2_h_ext_addr_h_Pos (0UL)                   /*!< ext_addr_h (Bit 0)                                    */
+#define MAC_src_ext_match2_h_ext_addr_h_Msk (0xffffffffUL)          /*!< ext_addr_h (Bitfield-Mask: 0xffffffff)                */
+/* ===================================================  src_short_match6  ==================================================== */
+#define MAC_src_short_match6_addr_Pos     (0UL)                     /*!< addr (Bit 0)                                          */
+#define MAC_src_short_match6_addr_Msk     (0xffffUL)                /*!< addr (Bitfield-Mask: 0xffff)                          */
+#define MAC_src_short_match6_panid_Pos    (16UL)                    /*!< panid (Bit 16)                                        */
+#define MAC_src_short_match6_panid_Msk    (0xffff0000UL)            /*!< panid (Bitfield-Mask: 0xffff)                         */
+/* ===================================================  src_ext_match3_l  ==================================================== */
+#define MAC_src_ext_match3_l_ext_addr_l_Pos (0UL)                   /*!< ext_addr_l (Bit 0)                                    */
+#define MAC_src_ext_match3_l_ext_addr_l_Msk (0xffffffffUL)          /*!< ext_addr_l (Bitfield-Mask: 0xffffffff)                */
+/* ===================================================  src_short_match7  ==================================================== */
+#define MAC_src_short_match7_addr_Pos     (0UL)                     /*!< addr (Bit 0)                                          */
+#define MAC_src_short_match7_addr_Msk     (0xffffUL)                /*!< addr (Bitfield-Mask: 0xffff)                          */
+#define MAC_src_short_match7_panid_Pos    (16UL)                    /*!< panid (Bit 16)                                        */
+#define MAC_src_short_match7_panid_Msk    (0xffff0000UL)            /*!< panid (Bitfield-Mask: 0xffff)                         */
+/* ===================================================  src_ext_match3_h  ==================================================== */
+#define MAC_src_ext_match3_h_ext_addr_h_Pos (0UL)                   /*!< ext_addr_h (Bit 0)                                    */
+#define MAC_src_ext_match3_h_ext_addr_h_Msk (0xffffffffUL)          /*!< ext_addr_h (Bitfield-Mask: 0xffffffff)                */
+/* ===================================================  src_short_match8  ==================================================== */
+#define MAC_src_short_match8_addr_Pos     (0UL)                     /*!< addr (Bit 0)                                          */
+#define MAC_src_short_match8_addr_Msk     (0xffffUL)                /*!< addr (Bitfield-Mask: 0xffff)                          */
+#define MAC_src_short_match8_panid_Pos    (16UL)                    /*!< panid (Bit 16)                                        */
+#define MAC_src_short_match8_panid_Msk    (0xffff0000UL)            /*!< panid (Bitfield-Mask: 0xffff)                         */
+/* ===================================================  src_ext_match4_l  ==================================================== */
+#define MAC_src_ext_match4_l_ext_addr_l_Pos (0UL)                   /*!< ext_addr_l (Bit 0)                                    */
+#define MAC_src_ext_match4_l_ext_addr_l_Msk (0xffffffffUL)          /*!< ext_addr_l (Bitfield-Mask: 0xffffffff)                */
+/* ===================================================  src_short_match9  ==================================================== */
+#define MAC_src_short_match9_addr_Pos     (0UL)                     /*!< addr (Bit 0)                                          */
+#define MAC_src_short_match9_addr_Msk     (0xffffUL)                /*!< addr (Bitfield-Mask: 0xffff)                          */
+#define MAC_src_short_match9_panid_Pos    (16UL)                    /*!< panid (Bit 16)                                        */
+#define MAC_src_short_match9_panid_Msk    (0xffff0000UL)            /*!< panid (Bitfield-Mask: 0xffff)                         */
+/* ===================================================  src_ext_match4_h  ==================================================== */
+#define MAC_src_ext_match4_h_ext_addr_h_Pos (0UL)                   /*!< ext_addr_h (Bit 0)                                    */
+#define MAC_src_ext_match4_h_ext_addr_h_Msk (0xffffffffUL)          /*!< ext_addr_h (Bitfield-Mask: 0xffffffff)                */
+/* ===================================================  src_short_match10  =================================================== */
+#define MAC_src_short_match10_addr_Pos    (0UL)                     /*!< addr (Bit 0)                                          */
+#define MAC_src_short_match10_addr_Msk    (0xffffUL)                /*!< addr (Bitfield-Mask: 0xffff)                          */
+#define MAC_src_short_match10_panid_Pos   (16UL)                    /*!< panid (Bit 16)                                        */
+#define MAC_src_short_match10_panid_Msk   (0xffff0000UL)            /*!< panid (Bitfield-Mask: 0xffff)                         */
+/* ===================================================  src_ext_match5_l  ==================================================== */
+#define MAC_src_ext_match5_l_ext_addr_l_Pos (0UL)                   /*!< ext_addr_l (Bit 0)                                    */
+#define MAC_src_ext_match5_l_ext_addr_l_Msk (0xffffffffUL)          /*!< ext_addr_l (Bitfield-Mask: 0xffffffff)                */
+/* ===================================================  src_short_match11  =================================================== */
+#define MAC_src_short_match11_addr_Pos    (0UL)                     /*!< addr (Bit 0)                                          */
+#define MAC_src_short_match11_addr_Msk    (0xffffUL)                /*!< addr (Bitfield-Mask: 0xffff)                          */
+#define MAC_src_short_match11_panid_Pos   (16UL)                    /*!< panid (Bit 16)                                        */
+#define MAC_src_short_match11_panid_Msk   (0xffff0000UL)            /*!< panid (Bitfield-Mask: 0xffff)                         */
+/* ===================================================  src_ext_match5_h  ==================================================== */
+#define MAC_src_ext_match5_h_ext_addr_h_Pos (0UL)                   /*!< ext_addr_h (Bit 0)                                    */
+#define MAC_src_ext_match5_h_ext_addr_h_Msk (0xffffffffUL)          /*!< ext_addr_h (Bitfield-Mask: 0xffffffff)                */
+/* ===================================================  src_short_match12  =================================================== */
+#define MAC_src_short_match12_addr_Pos    (0UL)                     /*!< addr (Bit 0)                                          */
+#define MAC_src_short_match12_addr_Msk    (0xffffUL)                /*!< addr (Bitfield-Mask: 0xffff)                          */
+#define MAC_src_short_match12_panid_Pos   (16UL)                    /*!< panid (Bit 16)                                        */
+#define MAC_src_short_match12_panid_Msk   (0xffff0000UL)            /*!< panid (Bitfield-Mask: 0xffff)                         */
+/* ===================================================  src_ext_match6_l  ==================================================== */
+#define MAC_src_ext_match6_l_ext_addr_l_Pos (0UL)                   /*!< ext_addr_l (Bit 0)                                    */
+#define MAC_src_ext_match6_l_ext_addr_l_Msk (0xffffffffUL)          /*!< ext_addr_l (Bitfield-Mask: 0xffffffff)                */
+/* ===================================================  src_short_match13  =================================================== */
+#define MAC_src_short_match13_addr_Pos    (0UL)                     /*!< addr (Bit 0)                                          */
+#define MAC_src_short_match13_addr_Msk    (0xffffUL)                /*!< addr (Bitfield-Mask: 0xffff)                          */
+#define MAC_src_short_match13_panid_Pos   (16UL)                    /*!< panid (Bit 16)                                        */
+#define MAC_src_short_match13_panid_Msk   (0xffff0000UL)            /*!< panid (Bitfield-Mask: 0xffff)                         */
+/* ===================================================  src_ext_match6_h  ==================================================== */
+#define MAC_src_ext_match6_h_ext_addr_h_Pos (0UL)                   /*!< ext_addr_h (Bit 0)                                    */
+#define MAC_src_ext_match6_h_ext_addr_h_Msk (0xffffffffUL)          /*!< ext_addr_h (Bitfield-Mask: 0xffffffff)                */
+/* ===================================================  src_short_match14  =================================================== */
+#define MAC_src_short_match14_addr_Pos    (0UL)                     /*!< addr (Bit 0)                                          */
+#define MAC_src_short_match14_addr_Msk    (0xffffUL)                /*!< addr (Bitfield-Mask: 0xffff)                          */
+#define MAC_src_short_match14_panid_Pos   (16UL)                    /*!< panid (Bit 16)                                        */
+#define MAC_src_short_match14_panid_Msk   (0xffff0000UL)            /*!< panid (Bitfield-Mask: 0xffff)                         */
+/* ===================================================  src_ext_match7_l  ==================================================== */
+#define MAC_src_ext_match7_l_ext_addr_l_Pos (0UL)                   /*!< ext_addr_l (Bit 0)                                    */
+#define MAC_src_ext_match7_l_ext_addr_l_Msk (0xffffffffUL)          /*!< ext_addr_l (Bitfield-Mask: 0xffffffff)                */
+/* ===================================================  src_short_match15  =================================================== */
+#define MAC_src_short_match15_addr_Pos    (0UL)                     /*!< addr (Bit 0)                                          */
+#define MAC_src_short_match15_addr_Msk    (0xffffUL)                /*!< addr (Bitfield-Mask: 0xffff)                          */
+#define MAC_src_short_match15_panid_Pos   (16UL)                    /*!< panid (Bit 16)                                        */
+#define MAC_src_short_match15_panid_Msk   (0xffff0000UL)            /*!< panid (Bitfield-Mask: 0xffff)                         */
+/* ===================================================  src_ext_match7_h  ==================================================== */
+#define MAC_src_ext_match7_h_ext_addr_h_Pos (0UL)                   /*!< ext_addr_h (Bit 0)                                    */
+#define MAC_src_ext_match7_h_ext_addr_h_Msk (0xffffffffUL)          /*!< ext_addr_h (Bitfield-Mask: 0xffffffff)                */
+/* ===================================================  src_short_match16  =================================================== */
+#define MAC_src_short_match16_addr_Pos    (0UL)                     /*!< addr (Bit 0)                                          */
+#define MAC_src_short_match16_addr_Msk    (0xffffUL)                /*!< addr (Bitfield-Mask: 0xffff)                          */
+#define MAC_src_short_match16_panid_Pos   (16UL)                    /*!< panid (Bit 16)                                        */
+#define MAC_src_short_match16_panid_Msk   (0xffff0000UL)            /*!< panid (Bitfield-Mask: 0xffff)                         */
+/* ===================================================  src_ext_match8_l  ==================================================== */
+#define MAC_src_ext_match8_l_ext_addr_l_Pos (0UL)                   /*!< ext_addr_l (Bit 0)                                    */
+#define MAC_src_ext_match8_l_ext_addr_l_Msk (0xffffffffUL)          /*!< ext_addr_l (Bitfield-Mask: 0xffffffff)                */
+/* ===================================================  src_short_match17  =================================================== */
+#define MAC_src_short_match17_addr_Pos    (0UL)                     /*!< addr (Bit 0)                                          */
+#define MAC_src_short_match17_addr_Msk    (0xffffUL)                /*!< addr (Bitfield-Mask: 0xffff)                          */
+#define MAC_src_short_match17_panid_Pos   (16UL)                    /*!< panid (Bit 16)                                        */
+#define MAC_src_short_match17_panid_Msk   (0xffff0000UL)            /*!< panid (Bitfield-Mask: 0xffff)                         */
+/* ===================================================  src_ext_match8_h  ==================================================== */
+#define MAC_src_ext_match8_h_ext_addr_h_Pos (0UL)                   /*!< ext_addr_h (Bit 0)                                    */
+#define MAC_src_ext_match8_h_ext_addr_h_Msk (0xffffffffUL)          /*!< ext_addr_h (Bitfield-Mask: 0xffffffff)                */
+/* ===================================================  src_short_match18  =================================================== */
+#define MAC_src_short_match18_addr_Pos    (0UL)                     /*!< addr (Bit 0)                                          */
+#define MAC_src_short_match18_addr_Msk    (0xffffUL)                /*!< addr (Bitfield-Mask: 0xffff)                          */
+#define MAC_src_short_match18_panid_Pos   (16UL)                    /*!< panid (Bit 16)                                        */
+#define MAC_src_short_match18_panid_Msk   (0xffff0000UL)            /*!< panid (Bitfield-Mask: 0xffff)                         */
+/* ===================================================  src_ext_match9_l  ==================================================== */
+#define MAC_src_ext_match9_l_ext_addr_l_Pos (0UL)                   /*!< ext_addr_l (Bit 0)                                    */
+#define MAC_src_ext_match9_l_ext_addr_l_Msk (0xffffffffUL)          /*!< ext_addr_l (Bitfield-Mask: 0xffffffff)                */
+/* ===================================================  src_short_match19  =================================================== */
+#define MAC_src_short_match19_addr_Pos    (0UL)                     /*!< addr (Bit 0)                                          */
+#define MAC_src_short_match19_addr_Msk    (0xffffUL)                /*!< addr (Bitfield-Mask: 0xffff)                          */
+#define MAC_src_short_match19_panid_Pos   (16UL)                    /*!< panid (Bit 16)                                        */
+#define MAC_src_short_match19_panid_Msk   (0xffff0000UL)            /*!< panid (Bitfield-Mask: 0xffff)                         */
+/* ===================================================  src_ext_match9_h  ==================================================== */
+#define MAC_src_ext_match9_h_ext_addr_h_Pos (0UL)                   /*!< ext_addr_h (Bit 0)                                    */
+#define MAC_src_ext_match9_h_ext_addr_h_Msk (0xffffffffUL)          /*!< ext_addr_h (Bitfield-Mask: 0xffffffff)                */
+/* ===================================================  src_short_match20  =================================================== */
+#define MAC_src_short_match20_addr_Pos    (0UL)                     /*!< addr (Bit 0)                                          */
+#define MAC_src_short_match20_addr_Msk    (0xffffUL)                /*!< addr (Bitfield-Mask: 0xffff)                          */
+#define MAC_src_short_match20_panid_Pos   (16UL)                    /*!< panid (Bit 16)                                        */
+#define MAC_src_short_match20_panid_Msk   (0xffff0000UL)            /*!< panid (Bitfield-Mask: 0xffff)                         */
+/* ===================================================  src_ext_match10_l  =================================================== */
+#define MAC_src_ext_match10_l_ext_addr_l_Pos (0UL)                  /*!< ext_addr_l (Bit 0)                                    */
+#define MAC_src_ext_match10_l_ext_addr_l_Msk (0xffffffffUL)         /*!< ext_addr_l (Bitfield-Mask: 0xffffffff)                */
+/* ===================================================  src_short_match21  =================================================== */
+#define MAC_src_short_match21_addr_Pos    (0UL)                     /*!< addr (Bit 0)                                          */
+#define MAC_src_short_match21_addr_Msk    (0xffffUL)                /*!< addr (Bitfield-Mask: 0xffff)                          */
+#define MAC_src_short_match21_panid_Pos   (16UL)                    /*!< panid (Bit 16)                                        */
+#define MAC_src_short_match21_panid_Msk   (0xffff0000UL)            /*!< panid (Bitfield-Mask: 0xffff)                         */
+/* ===================================================  src_ext_match10_h  =================================================== */
+#define MAC_src_ext_match10_h_ext_addr_h_Pos (0UL)                  /*!< ext_addr_h (Bit 0)                                    */
+#define MAC_src_ext_match10_h_ext_addr_h_Msk (0xffffffffUL)         /*!< ext_addr_h (Bitfield-Mask: 0xffffffff)                */
+/* ===================================================  src_short_match22  =================================================== */
+#define MAC_src_short_match22_addr_Pos    (0UL)                     /*!< addr (Bit 0)                                          */
+#define MAC_src_short_match22_addr_Msk    (0xffffUL)                /*!< addr (Bitfield-Mask: 0xffff)                          */
+#define MAC_src_short_match22_panid_Pos   (16UL)                    /*!< panid (Bit 16)                                        */
+#define MAC_src_short_match22_panid_Msk   (0xffff0000UL)            /*!< panid (Bitfield-Mask: 0xffff)                         */
+/* ===================================================  src_ext_match11_l  =================================================== */
+#define MAC_src_ext_match11_l_ext_addr_l_Pos (0UL)                  /*!< ext_addr_l (Bit 0)                                    */
+#define MAC_src_ext_match11_l_ext_addr_l_Msk (0xffffffffUL)         /*!< ext_addr_l (Bitfield-Mask: 0xffffffff)                */
+/* ===================================================  src_short_match23  =================================================== */
+#define MAC_src_short_match23_addr_Pos    (0UL)                     /*!< addr (Bit 0)                                          */
+#define MAC_src_short_match23_addr_Msk    (0xffffUL)                /*!< addr (Bitfield-Mask: 0xffff)                          */
+#define MAC_src_short_match23_panid_Pos   (16UL)                    /*!< panid (Bit 16)                                        */
+#define MAC_src_short_match23_panid_Msk   (0xffff0000UL)            /*!< panid (Bitfield-Mask: 0xffff)                         */
+/* ===================================================  src_ext_match11_h  =================================================== */
+#define MAC_src_ext_match11_h_ext_addr_h_Pos (0UL)                  /*!< ext_addr_h (Bit 0)                                    */
+#define MAC_src_ext_match11_h_ext_addr_h_Msk (0xffffffffUL)         /*!< ext_addr_h (Bitfield-Mask: 0xffffffff)                */
+/* ===================================================  src_short_match24  =================================================== */
+#define MAC_src_short_match24_addr_Pos    (0UL)                     /*!< addr (Bit 0)                                          */
+#define MAC_src_short_match24_addr_Msk    (0xffffUL)                /*!< addr (Bitfield-Mask: 0xffff)                          */
+#define MAC_src_short_match24_panid_Pos   (16UL)                    /*!< panid (Bit 16)                                        */
+#define MAC_src_short_match24_panid_Msk   (0xffff0000UL)            /*!< panid (Bitfield-Mask: 0xffff)                         */
+/* ===================================================  src_ext_match12_l  =================================================== */
+#define MAC_src_ext_match12_l_ext_addr_l_Pos (0UL)                  /*!< ext_addr_l (Bit 0)                                    */
+#define MAC_src_ext_match12_l_ext_addr_l_Msk (0xffffffffUL)         /*!< ext_addr_l (Bitfield-Mask: 0xffffffff)                */
+/* ===================================================  src_short_match25  =================================================== */
+#define MAC_src_short_match25_addr_Pos    (0UL)                     /*!< addr (Bit 0)                                          */
+#define MAC_src_short_match25_addr_Msk    (0xffffUL)                /*!< addr (Bitfield-Mask: 0xffff)                          */
+#define MAC_src_short_match25_panid_Pos   (16UL)                    /*!< panid (Bit 16)                                        */
+#define MAC_src_short_match25_panid_Msk   (0xffff0000UL)            /*!< panid (Bitfield-Mask: 0xffff)                         */
+/* ===================================================  src_ext_match12_h  =================================================== */
+#define MAC_src_ext_match12_h_ext_addr_h_Pos (0UL)                  /*!< ext_addr_h (Bit 0)                                    */
+#define MAC_src_ext_match12_h_ext_addr_h_Msk (0xffffffffUL)         /*!< ext_addr_h (Bitfield-Mask: 0xffffffff)                */
+/* ===================================================  src_short_match26  =================================================== */
+#define MAC_src_short_match26_addr_Pos    (0UL)                     /*!< addr (Bit 0)                                          */
+#define MAC_src_short_match26_addr_Msk    (0xffffUL)                /*!< addr (Bitfield-Mask: 0xffff)                          */
+#define MAC_src_short_match26_panid_Pos   (16UL)                    /*!< panid (Bit 16)                                        */
+#define MAC_src_short_match26_panid_Msk   (0xffff0000UL)            /*!< panid (Bitfield-Mask: 0xffff)                         */
+/* ===================================================  src_ext_match13_l  =================================================== */
+#define MAC_src_ext_match13_l_ext_addr_l_Pos (0UL)                  /*!< ext_addr_l (Bit 0)                                    */
+#define MAC_src_ext_match13_l_ext_addr_l_Msk (0xffffffffUL)         /*!< ext_addr_l (Bitfield-Mask: 0xffffffff)                */
+/* ===================================================  src_short_match27  =================================================== */
+#define MAC_src_short_match27_addr_Pos    (0UL)                     /*!< addr (Bit 0)                                          */
+#define MAC_src_short_match27_addr_Msk    (0xffffUL)                /*!< addr (Bitfield-Mask: 0xffff)                          */
+#define MAC_src_short_match27_panid_Pos   (16UL)                    /*!< panid (Bit 16)                                        */
+#define MAC_src_short_match27_panid_Msk   (0xffff0000UL)            /*!< panid (Bitfield-Mask: 0xffff)                         */
+/* ===================================================  src_ext_match13_h  =================================================== */
+#define MAC_src_ext_match13_h_ext_addr_h_Pos (0UL)                  /*!< ext_addr_h (Bit 0)                                    */
+#define MAC_src_ext_match13_h_ext_addr_h_Msk (0xffffffffUL)         /*!< ext_addr_h (Bitfield-Mask: 0xffffffff)                */
+/* ===================================================  src_short_match28  =================================================== */
+#define MAC_src_short_match28_addr_Pos    (0UL)                     /*!< addr (Bit 0)                                          */
+#define MAC_src_short_match28_addr_Msk    (0xffffUL)                /*!< addr (Bitfield-Mask: 0xffff)                          */
+#define MAC_src_short_match28_panid_Pos   (16UL)                    /*!< panid (Bit 16)                                        */
+#define MAC_src_short_match28_panid_Msk   (0xffff0000UL)            /*!< panid (Bitfield-Mask: 0xffff)                         */
+/* ===================================================  src_ext_match14_l  =================================================== */
+#define MAC_src_ext_match14_l_ext_addr_l_Pos (0UL)                  /*!< ext_addr_l (Bit 0)                                    */
+#define MAC_src_ext_match14_l_ext_addr_l_Msk (0xffffffffUL)         /*!< ext_addr_l (Bitfield-Mask: 0xffffffff)                */
+/* ===================================================  src_short_match29  =================================================== */
+#define MAC_src_short_match29_addr_Pos    (0UL)                     /*!< addr (Bit 0)                                          */
+#define MAC_src_short_match29_addr_Msk    (0xffffUL)                /*!< addr (Bitfield-Mask: 0xffff)                          */
+#define MAC_src_short_match29_panid_Pos   (16UL)                    /*!< panid (Bit 16)                                        */
+#define MAC_src_short_match29_panid_Msk   (0xffff0000UL)            /*!< panid (Bitfield-Mask: 0xffff)                         */
+/* ===================================================  src_ext_match14_h  =================================================== */
+#define MAC_src_ext_match14_h_ext_addr_h_Pos (0UL)                  /*!< ext_addr_h (Bit 0)                                    */
+#define MAC_src_ext_match14_h_ext_addr_h_Msk (0xffffffffUL)         /*!< ext_addr_h (Bitfield-Mask: 0xffffffff)                */
+/* ===================================================  src_short_match30  =================================================== */
+#define MAC_src_short_match30_addr_Pos    (0UL)                     /*!< addr (Bit 0)                                          */
+#define MAC_src_short_match30_addr_Msk    (0xffffUL)                /*!< addr (Bitfield-Mask: 0xffff)                          */
+#define MAC_src_short_match30_panid_Pos   (16UL)                    /*!< panid (Bit 16)                                        */
+#define MAC_src_short_match30_panid_Msk   (0xffff0000UL)            /*!< panid (Bitfield-Mask: 0xffff)                         */
+/* ===================================================  src_ext_match15_l  =================================================== */
+#define MAC_src_ext_match15_l_ext_addr_l_Pos (0UL)                  /*!< ext_addr_l (Bit 0)                                    */
+#define MAC_src_ext_match15_l_ext_addr_l_Msk (0xffffffffUL)         /*!< ext_addr_l (Bitfield-Mask: 0xffffffff)                */
+/* ===================================================  src_short_match31  =================================================== */
+#define MAC_src_short_match31_addr_Pos    (0UL)                     /*!< addr (Bit 0)                                          */
+#define MAC_src_short_match31_addr_Msk    (0xffffUL)                /*!< addr (Bitfield-Mask: 0xffff)                          */
+#define MAC_src_short_match31_panid_Pos   (16UL)                    /*!< panid (Bit 16)                                        */
+#define MAC_src_short_match31_panid_Msk   (0xffff0000UL)            /*!< panid (Bitfield-Mask: 0xffff)                         */
+/* ===================================================  src_ext_match15_h  =================================================== */
+#define MAC_src_ext_match15_h_ext_addr_h_Pos (0UL)                  /*!< ext_addr_h (Bit 0)                                    */
+#define MAC_src_ext_match15_h_ext_addr_h_Msk (0xffffffffUL)         /*!< ext_addr_h (Bitfield-Mask: 0xffffffff)                */
+/* ========================================================  seccr0  ========================================================= */
+#define MAC_seccr0_txncipher_Pos          (0UL)                     /*!< txncipher (Bit 0)                                     */
+#define MAC_seccr0_txncipher_Msk          (0x7UL)                   /*!< txncipher (Bitfield-Mask: 0x07)                       */
+#define MAC_seccr0_rxcipher_Pos           (3UL)                     /*!< rxcipher (Bit 3)                                      */
+#define MAC_seccr0_rxcipher_Msk           (0x38UL)                  /*!< rxcipher (Bitfield-Mask: 0x07)                        */
+#define MAC_seccr0_secstart_Pos           (6UL)                     /*!< secstart (Bit 6)                                      */
+#define MAC_seccr0_secstart_Msk           (0x40UL)                  /*!< secstart (Bitfield-Mask: 0x01)                        */
+#define MAC_seccr0_secignore_Pos          (7UL)                     /*!< secignore (Bit 7)                                     */
+#define MAC_seccr0_secignore_Msk          (0x80UL)                  /*!< secignore (Bitfield-Mask: 0x01)                       */
+#define MAC_seccr0_disenc_Pos             (8UL)                     /*!< disenc (Bit 8)                                        */
+#define MAC_seccr0_disenc_Msk             (0x100UL)                 /*!< disenc (Bitfield-Mask: 0x01)                          */
+#define MAC_seccr0_disdec_Pos             (9UL)                     /*!< disdec (Bit 9)                                        */
+#define MAC_seccr0_disdec_Msk             (0x200UL)                 /*!< disdec (Bitfield-Mask: 0x01)                          */
+#define MAC_seccr0_txbcipher_Pos          (16UL)                    /*!< txbcipher (Bit 16)                                    */
+#define MAC_seccr0_txbcipher_Msk          (0x70000UL)               /*!< txbcipher (Bitfield-Mask: 0x07)                       */
+#define MAC_seccr0_txg1cipher_Pos         (24UL)                    /*!< txg1cipher (Bit 24)                                   */
+#define MAC_seccr0_txg1cipher_Msk         (0x7000000UL)             /*!< txg1cipher (Bitfield-Mask: 0x07)                      */
+#define MAC_seccr0_txg2cipher_Pos         (27UL)                    /*!< txg2cipher (Bit 27)                                   */
+#define MAC_seccr0_txg2cipher_Msk         (0x38000000UL)            /*!< txg2cipher (Bitfield-Mask: 0x07)                      */
+/* ========================================================  seccr1  ========================================================= */
+#define MAC_seccr1_usrflag_Pos            (0UL)                     /*!< usrflag (Bit 0)                                       */
+#define MAC_seccr1_usrflag_Msk            (0x1UL)                   /*!< usrflag (Bitfield-Mask: 0x01)                         */
+#define MAC_seccr1_sec_2006_Pos           (1UL)                     /*!< sec_2006 (Bit 1)                                      */
+#define MAC_seccr1_sec_2006_Msk           (0x2UL)                   /*!< sec_2006 (Bitfield-Mask: 0x01)                        */
+#define MAC_seccr1_aes_only_Pos           (2UL)                     /*!< aes_only (Bit 2)                                      */
+#define MAC_seccr1_aes_only_Msk           (0x4UL)                   /*!< aes_only (Bitfield-Mask: 0x01)                        */
+#define MAC_seccr1_encflg_Pos             (8UL)                     /*!< encflg (Bit 8)                                        */
+#define MAC_seccr1_encflg_Msk             (0xff00UL)                /*!< encflg (Bitfield-Mask: 0xff)                          */
+#define MAC_seccr1_autflg_Pos             (16UL)                    /*!< autflg (Bit 16)                                       */
+#define MAC_seccr1_autflg_Msk             (0xff0000UL)              /*!< autflg (Bitfield-Mask: 0xff)                          */
+/* ====================================================  sec_upper_ctrl  ===================================================== */
+#define MAC_sec_upper_ctrl_upenc_Pos      (0UL)                     /*!< upenc (Bit 0)                                         */
+#define MAC_sec_upper_ctrl_upenc_Msk      (0x1UL)                   /*!< upenc (Bitfield-Mask: 0x01)                           */
+#define MAC_sec_upper_ctrl_updec_Pos      (1UL)                     /*!< updec (Bit 1)                                         */
+#define MAC_sec_upper_ctrl_updec_Msk      (0x2UL)                   /*!< updec (Bitfield-Mask: 0x01)                           */
+/* =====================================================  sec_proc_sts  ====================================================== */
+#define MAC_sec_proc_sts_sec_enc_done_Pos (0UL)                     /*!< sec_enc_done (Bit 0)                                  */
+#define MAC_sec_proc_sts_sec_enc_done_Msk (0x1UL)                   /*!< sec_enc_done (Bitfield-Mask: 0x01)                    */
+#define MAC_sec_proc_sts_upsecerr_Pos     (1UL)                     /*!< upsecerr (Bit 1)                                      */
+#define MAC_sec_proc_sts_upsecerr_Msk     (0x2UL)                   /*!< upsecerr (Bitfield-Mask: 0x01)                        */
+#define MAC_sec_proc_sts_txsecdone_Pos    (8UL)                     /*!< txsecdone (Bit 8)                                     */
+#define MAC_sec_proc_sts_txsecdone_Msk    (0x100UL)                 /*!< txsecdone (Bitfield-Mask: 0x01)                       */
+#define MAC_sec_proc_sts_secdecerr_Pos    (9UL)                     /*!< secdecerr (Bit 9)                                     */
+#define MAC_sec_proc_sts_secdecerr_Msk    (0x200UL)                 /*!< secdecerr (Bitfield-Mask: 0x01)                       */
+#define MAC_sec_proc_sts_sec_upper_enclerr_Pos (10UL)               /*!< sec_upper_enclerr (Bit 10)                            */
+#define MAC_sec_proc_sts_sec_upper_enclerr_Msk (0x400UL)            /*!< sec_upper_enclerr (Bitfield-Mask: 0x01)               */
+#define MAC_sec_proc_sts_aes_only_rdy_Pos (16UL)                    /*!< aes_only_rdy (Bit 16)                                 */
+#define MAC_sec_proc_sts_aes_only_rdy_Msk (0x10000UL)               /*!< aes_only_rdy (Bitfield-Mask: 0x01)                    */
+/* ====================================================  sec_sts_stccmp  ===================================================== */
+#define MAC_sec_sts_stccmp_scu_cs_Pos     (0UL)                     /*!< scu_cs (Bit 0)                                        */
+#define MAC_sec_sts_stccmp_scu_cs_Msk     (0x7UL)                   /*!< scu_cs (Bitfield-Mask: 0x07)                          */
+#define MAC_sec_sts_stccmp_parse_cs_Pos   (3UL)                     /*!< parse_cs (Bit 3)                                      */
+#define MAC_sec_sts_stccmp_parse_cs_Msk   (0x38UL)                  /*!< parse_cs (Bitfield-Mask: 0x07)                        */
+#define MAC_sec_sts_stccmp_key_sr_cs_Pos  (6UL)                     /*!< key_sr_cs (Bit 6)                                     */
+#define MAC_sec_sts_stccmp_key_sr_cs_Msk  (0xc0UL)                  /*!< key_sr_cs (Bitfield-Mask: 0x03)                       */
+#define MAC_sec_sts_stccmp_st_ccmp_Pos    (8UL)                     /*!< st_ccmp (Bit 8)                                       */
+#define MAC_sec_sts_stccmp_st_ccmp_Msk    (0xf00UL)                 /*!< st_ccmp (Bitfield-Mask: 0x0f)                         */
+/* =====================================================  sec_par_order  ===================================================== */
+#define MAC_sec_par_order_extadr_odr_Pos  (0UL)                     /*!< extadr_odr (Bit 0)                                    */
+#define MAC_sec_par_order_extadr_odr_Msk  (0x1UL)                   /*!< extadr_odr (Bitfield-Mask: 0x01)                      */
+#define MAC_sec_par_order_rxmadr_odr_Pos  (1UL)                     /*!< rxmadr_odr (Bit 1)                                    */
+#define MAC_sec_par_order_rxmadr_odr_Msk  (0x2UL)                   /*!< rxmadr_odr (Bitfield-Mask: 0x01)                      */
+#define MAC_sec_par_order_frmctr_odr_Pos  (2UL)                     /*!< frmctr_odr (Bit 2)                                    */
+#define MAC_sec_par_order_frmctr_odr_Msk  (0x4UL)                   /*!< frmctr_odr (Bitfield-Mask: 0x01)                      */
+/* ======================================================  upnonce_0_3  ====================================================== */
+#define MAC_upnonce_0_3_upnonce_Pos       (0UL)                     /*!< upnonce (Bit 0)                                       */
+#define MAC_upnonce_0_3_upnonce_Msk       (0xffffffffUL)            /*!< upnonce (Bitfield-Mask: 0xffffffff)                   */
+/* ======================================================  upnonce_4_7  ====================================================== */
+#define MAC_upnonce_4_7_upnonce_Pos       (0UL)                     /*!< upnonce (Bit 0)                                       */
+#define MAC_upnonce_4_7_upnonce_Msk       (0xffffffffUL)            /*!< upnonce (Bitfield-Mask: 0xffffffff)                   */
+/* =====================================================  upnonce_8_11  ====================================================== */
+#define MAC_upnonce_8_11_upnonce_Pos      (0UL)                     /*!< upnonce (Bit 0)                                       */
+#define MAC_upnonce_8_11_upnonce_Msk      (0xffffffffUL)            /*!< upnonce (Bitfield-Mask: 0xffffffff)                   */
+/* ======================================================  upnonce_12  ======================================================= */
+#define MAC_upnonce_12_upnonce_Pos        (0UL)                     /*!< upnonce (Bit 0)                                       */
+#define MAC_upnonce_12_upnonce_Msk        (0xffUL)                  /*!< upnonce (Bitfield-Mask: 0xff)                         */
+/* =====================================================  sec_initcntl  ====================================================== */
+#define MAC_sec_initcntl_initcnt_Pos      (0UL)                     /*!< initcnt (Bit 0)                                       */
+#define MAC_sec_initcntl_initcnt_Msk      (0xffffUL)                /*!< initcnt (Bitfield-Mask: 0xffff)                       */
+/* ========================================================  tx_set  ========================================================= */
+#define MAC_tx_set_txagc_Pos              (0UL)                     /*!< txagc (Bit 0)                                         */
+#define MAC_tx_set_txagc_Msk              (0xffUL)                  /*!< txagc (Bitfield-Mask: 0xff)                           */
+#define MAC_tx_set_sel_tpm_Pos            (8UL)                     /*!< sel_tpm (Bit 8)                                       */
+#define MAC_tx_set_sel_tpm_Msk            (0x100UL)                 /*!< sel_tpm (Bitfield-Mask: 0x01)                         */
+#define MAC_tx_set_lna_en_Pos             (9UL)                     /*!< lna_en (Bit 9)                                        */
+#define MAC_tx_set_lna_en_Msk             (0x200UL)                 /*!< lna_en (Bitfield-Mask: 0x01)                          */
+#define MAC_tx_set_en_early_txon_tgl_Pos  (12UL)                    /*!< en_early_txon_tgl (Bit 12)                            */
+#define MAC_tx_set_en_early_txon_tgl_Msk  (0x1000UL)                /*!< en_early_txon_tgl (Bitfield-Mask: 0x01)               */
+#define MAC_tx_set_radio_off_Pos          (13UL)                    /*!< radio_off (Bit 13)                                    */
+#define MAC_tx_set_radio_off_Msk          (0x2000UL)                /*!< radio_off (Bitfield-Mask: 0x01)                       */
+#define MAC_tx_set_prestby_dly_zb_Pos     (14UL)                    /*!< prestby_dly_zb (Bit 14)                               */
+#define MAC_tx_set_prestby_dly_zb_Msk     (0x1c000UL)               /*!< prestby_dly_zb (Bitfield-Mask: 0x07)                  */
+#define MAC_tx_set_preturnon_delay_zb_Pos (17UL)                    /*!< preturnon_delay_zb (Bit 17)                           */
+#define MAC_tx_set_preturnon_delay_zb_Msk (0x3e0000UL)              /*!< preturnon_delay_zb (Bitfield-Mask: 0x1f)              */
+#define MAC_tx_set_rampstby_delay_zb_Pos  (22UL)                    /*!< rampstby_delay_zb (Bit 22)                            */
+#define MAC_tx_set_rampstby_delay_zb_Msk  (0x7c00000UL)             /*!< rampstby_delay_zb (Bitfield-Mask: 0x1f)               */
+#define MAC_tx_set_sd_pos_delay_zb_Pos    (27UL)                    /*!< sd_pos_delay_zb (Bit 27)                              */
+#define MAC_tx_set_sd_pos_delay_zb_Msk    (0x78000000UL)            /*!< sd_pos_delay_zb (Bitfield-Mask: 0x0f)                 */
+#define MAC_tx_set_tx_bkprg0_en_Pos       (31UL)                    /*!< tx_bkprg0_en (Bit 31)                                 */
+#define MAC_tx_set_tx_bkprg0_en_Msk       (0x80000000UL)            /*!< tx_bkprg0_en (Bitfield-Mask: 0x01)                    */
+/* ========================================================  rx_set  ========================================================= */
+#define MAC_rx_set_dis_rf_ps_Pos          (0UL)                     /*!< dis_rf_ps (Bit 0)                                     */
+#define MAC_rx_set_dis_rf_ps_Msk          (0x1UL)                   /*!< dis_rf_ps (Bitfield-Mask: 0x01)                       */
+#define MAC_rx_set_prestby_dly_en_Pos     (1UL)                     /*!< prestby_dly_en (Bit 1)                                */
+#define MAC_rx_set_prestby_dly_en_Msk     (0x2UL)                   /*!< prestby_dly_en (Bitfield-Mask: 0x01)                  */
+#define MAC_rx_set_cca_threshold_Pos      (2UL)                     /*!< cca_threshold (Bit 2)                                 */
+#define MAC_rx_set_cca_threshold_Msk      (0x3cUL)                  /*!< cca_threshold (Bitfield-Mask: 0x0f)                   */
+#define MAC_rx_set_cca_ed_threshold_Pos   (6UL)                     /*!< cca_ed_threshold (Bit 6)                              */
+#define MAC_rx_set_cca_ed_threshold_Msk   (0x3fc0UL)                /*!< cca_ed_threshold (Bitfield-Mask: 0xff)                */
+#define MAC_rx_set_txon_early_Pos         (16UL)                    /*!< txon_early (Bit 16)                                   */
+#define MAC_rx_set_txon_early_Msk         (0x3f0000UL)              /*!< txon_early (Bitfield-Mask: 0x3f)                      */
+#define MAC_rx_set_cca_mode_Pos           (22UL)                    /*!< cca_mode (Bit 22)                                     */
+#define MAC_rx_set_cca_mode_Msk           (0xc00000UL)              /*!< cca_mode (Bitfield-Mask: 0x03)                        */
+#define MAC_rx_set_standby_pg_adress_Pos  (24UL)                    /*!< standby_pg_adress (Bit 24)                            */
+#define MAC_rx_set_standby_pg_adress_Msk  (0xff000000UL)            /*!< standby_pg_adress (Bitfield-Mask: 0xff)               */
+/* ======================================================  phy_trx_dly  ====================================================== */
+#define MAC_phy_trx_dly_txon_delay_Pos    (0UL)                     /*!< txon_delay (Bit 0)                                    */
+#define MAC_phy_trx_dly_txon_delay_Msk    (0xffUL)                  /*!< txon_delay (Bitfield-Mask: 0xff)                      */
+#define MAC_phy_trx_dly_rxon_delay_Pos    (8UL)                     /*!< rxon_delay (Bit 8)                                    */
+#define MAC_phy_trx_dly_rxon_delay_Msk    (0xff00UL)                /*!< rxon_delay (Bitfield-Mask: 0xff)                      */
+#define MAC_phy_trx_dly_cca_rxon_delay_Pos (16UL)                   /*!< cca_rxon_delay (Bit 16)                               */
+#define MAC_phy_trx_dly_cca_rxon_delay_Msk (0xff0000UL)             /*!< cca_rxon_delay (Bitfield-Mask: 0xff)                  */
+#define MAC_phy_trx_dly_rx2rx_delay_Pos   (24UL)                    /*!< rx2rx_delay (Bit 24)                                  */
+#define MAC_phy_trx_dly_rx2rx_delay_Msk   (0xff000000UL)            /*!< rx2rx_delay (Bitfield-Mask: 0xff)                     */
+/* ======================================================  phy_to_dly  ======================================================= */
+#define MAC_phy_to_dly_rx_timeout_delay_Pos (0UL)                   /*!< rx_timeout_delay (Bit 0)                              */
+#define MAC_phy_to_dly_rx_timeout_delay_Msk (0xffUL)                /*!< rx_timeout_delay (Bitfield-Mask: 0xff)                */
+#define MAC_phy_to_dly_cca_rx_timeout_delay_Pos (8UL)               /*!< cca_rx_timeout_delay (Bit 8)                          */
+#define MAC_phy_to_dly_cca_rx_timeout_delay_Msk (0xff00UL)          /*!< cca_rx_timeout_delay (Bitfield-Mask: 0xff)            */
+#define MAC_phy_to_dly_rx2tx_delay_Pos    (16UL)                    /*!< rx2tx_delay (Bit 16)                                  */
+#define MAC_phy_to_dly_rx2tx_delay_Msk    (0xff0000UL)              /*!< rx2tx_delay (Bitfield-Mask: 0xff)                     */
+#define MAC_phy_to_dly_tx2rx_delay_Pos    (24UL)                    /*!< tx2rx_delay (Bit 24)                                  */
+#define MAC_phy_to_dly_tx2rx_delay_Msk    (0xff000000UL)            /*!< tx2rx_delay (Bitfield-Mask: 0xff)                     */
+/* =====================================================  tx_prg_reg_0  ====================================================== */
+#define MAC_tx_prg_reg_0_standby_pg_data_Pos (0UL)                  /*!< standby_pg_data (Bit 0)                               */
+#define MAC_tx_prg_reg_0_standby_pg_data_Msk (0xffffUL)             /*!< standby_pg_data (Bitfield-Mask: 0xffff)               */
+#define MAC_tx_prg_reg_0_tx_bkprg0_pg_data_Pos (16UL)               /*!< tx_bkprg0_pg_data (Bit 16)                            */
+#define MAC_tx_prg_reg_0_tx_bkprg0_pg_data_Msk (0xffff0000UL)       /*!< tx_bkprg0_pg_data (Bitfield-Mask: 0xffff)             */
+/* =====================================================  tx_prg_reg_1  ====================================================== */
+#define MAC_tx_prg_reg_1_tx_bkprg2_pg_data_Pos (0UL)                /*!< tx_bkprg2_pg_data (Bit 0)                             */
+#define MAC_tx_prg_reg_1_tx_bkprg2_pg_data_Msk (0xffffUL)           /*!< tx_bkprg2_pg_data (Bitfield-Mask: 0xffff)             */
+#define MAC_tx_prg_reg_1_tx_bkprg1_pg_data_Pos (16UL)               /*!< tx_bkprg1_pg_data (Bit 16)                            */
+#define MAC_tx_prg_reg_1_tx_bkprg1_pg_data_Msk (0xffff0000UL)       /*!< tx_bkprg1_pg_data (Bitfield-Mask: 0xffff)             */
+/* =====================================================  tx_prg_reg_2  ====================================================== */
+#define MAC_tx_prg_reg_2_tx_bkprg0_pg_addr_Pos (0UL)                /*!< tx_bkprg0_pg_addr (Bit 0)                             */
+#define MAC_tx_prg_reg_2_tx_bkprg0_pg_addr_Msk (0xffUL)             /*!< tx_bkprg0_pg_addr (Bitfield-Mask: 0xff)               */
+#define MAC_tx_prg_reg_2_tx_bkprg1_pg_addr_Pos (8UL)                /*!< tx_bkprg1_pg_addr (Bit 8)                             */
+#define MAC_tx_prg_reg_2_tx_bkprg1_pg_addr_Msk (0xff00UL)           /*!< tx_bkprg1_pg_addr (Bitfield-Mask: 0xff)               */
+#define MAC_tx_prg_reg_2_tx_bkprg2_pg_addr_Pos (16UL)               /*!< tx_bkprg2_pg_addr (Bit 16)                            */
+#define MAC_tx_prg_reg_2_tx_bkprg2_pg_addr_Msk (0xff0000UL)         /*!< tx_bkprg2_pg_addr (Bitfield-Mask: 0xff)               */
+#define MAC_tx_prg_reg_2_tx_bkprg1_en_Pos (24UL)                    /*!< tx_bkprg1_en (Bit 24)                                 */
+#define MAC_tx_prg_reg_2_tx_bkprg1_en_Msk (0x1000000UL)             /*!< tx_bkprg1_en (Bitfield-Mask: 0x01)                    */
+#define MAC_tx_prg_reg_2_tx_bkprg2_en_Pos (25UL)                    /*!< tx_bkprg2_en (Bit 25)                                 */
+#define MAC_tx_prg_reg_2_tx_bkprg2_en_Msk (0x2000000UL)             /*!< tx_bkprg2_en (Bitfield-Mask: 0x01)                    */
+#define MAC_tx_prg_reg_2_rx_bkprg0_en_Pos (26UL)                    /*!< rx_bkprg0_en (Bit 26)                                 */
+#define MAC_tx_prg_reg_2_rx_bkprg0_en_Msk (0x4000000UL)             /*!< rx_bkprg0_en (Bitfield-Mask: 0x01)                    */
+#define MAC_tx_prg_reg_2_rx_bkprg1_en_Pos (27UL)                    /*!< rx_bkprg1_en (Bit 27)                                 */
+#define MAC_tx_prg_reg_2_rx_bkprg1_en_Msk (0x8000000UL)             /*!< rx_bkprg1_en (Bitfield-Mask: 0x01)                    */
+#define MAC_tx_prg_reg_2_rx_bkprg2_en_Pos (28UL)                    /*!< rx_bkprg2_en (Bit 28)                                 */
+#define MAC_tx_prg_reg_2_rx_bkprg2_en_Msk (0x10000000UL)            /*!< rx_bkprg2_en (Bitfield-Mask: 0x01)                    */
+#define MAC_tx_prg_reg_2_rx_bkprg0_mode_en_Pos (29UL)               /*!< rx_bkprg0_mode_en (Bit 29)                            */
+#define MAC_tx_prg_reg_2_rx_bkprg0_mode_en_Msk (0x20000000UL)       /*!< rx_bkprg0_mode_en (Bitfield-Mask: 0x01)               */
+#define MAC_tx_prg_reg_2_rx_bkprg1_mode_en_Pos (30UL)               /*!< rx_bkprg1_mode_en (Bit 30)                            */
+#define MAC_tx_prg_reg_2_rx_bkprg1_mode_en_Msk (0x40000000UL)       /*!< rx_bkprg1_mode_en (Bitfield-Mask: 0x01)               */
+#define MAC_tx_prg_reg_2_rx_bkprg2_mode_en_Pos (31UL)               /*!< rx_bkprg2_mode_en (Bit 31)                            */
+#define MAC_tx_prg_reg_2_rx_bkprg2_mode_en_Msk (0x80000000UL)       /*!< rx_bkprg2_mode_en (Bitfield-Mask: 0x01)               */
+/* =====================================================  rx_prg_reg_0  ====================================================== */
+#define MAC_rx_prg_reg_0_rx_bkprg0_pg_data_Pos (0UL)                /*!< rx_bkprg0_pg_data (Bit 0)                             */
+#define MAC_rx_prg_reg_0_rx_bkprg0_pg_data_Msk (0xffffUL)           /*!< rx_bkprg0_pg_data (Bitfield-Mask: 0xffff)             */
+#define MAC_rx_prg_reg_0_rx_bkprg1_pg_data_Pos (16UL)               /*!< rx_bkprg1_pg_data (Bit 16)                            */
+#define MAC_rx_prg_reg_0_rx_bkprg1_pg_data_Msk (0xffff0000UL)       /*!< rx_bkprg1_pg_data (Bitfield-Mask: 0xffff)             */
+/* =====================================================  rx_prg_reg_1  ====================================================== */
+#define MAC_rx_prg_reg_1_rx_bkprg2_pg_data_Pos (0UL)                /*!< rx_bkprg2_pg_data (Bit 0)                             */
+#define MAC_rx_prg_reg_1_rx_bkprg2_pg_data_Msk (0xffffUL)           /*!< rx_bkprg2_pg_data (Bitfield-Mask: 0xffff)             */
+#define MAC_rx_prg_reg_1_rx_bkprg0_pg_addr_Pos (16UL)               /*!< rx_bkprg0_pg_addr (Bit 16)                            */
+#define MAC_rx_prg_reg_1_rx_bkprg0_pg_addr_Msk (0xff0000UL)         /*!< rx_bkprg0_pg_addr (Bitfield-Mask: 0xff)               */
+#define MAC_rx_prg_reg_1_rx_bkprg1_pg_addr_Pos (24UL)               /*!< rx_bkprg1_pg_addr (Bit 24)                            */
+#define MAC_rx_prg_reg_1_rx_bkprg1_pg_addr_Msk (0xff000000UL)       /*!< rx_bkprg1_pg_addr (Bitfield-Mask: 0xff)               */
+/* =====================================================  rx_prg_reg_2r  ===================================================== */
+#define MAC_rx_prg_reg_2r_rx_bkprg2_pg_addr_Pos (0UL)               /*!< rx_bkprg2_pg_addr (Bit 0)                             */
+#define MAC_rx_prg_reg_2r_rx_bkprg2_pg_addr_Msk (0xffUL)            /*!< rx_bkprg2_pg_addr (Bitfield-Mask: 0xff)               */
+#define MAC_rx_prg_reg_2r_channel_Pos     (8UL)                     /*!< channel (Bit 8)                                       */
+#define MAC_rx_prg_reg_2r_channel_Msk     (0x7f00UL)                /*!< channel (Bitfield-Mask: 0x7f)                         */
+#define MAC_rx_prg_reg_2r_opt_cca_ed_or_Pos (15UL)                  /*!< opt_cca_ed_or (Bit 15)                                */
+#define MAC_rx_prg_reg_2r_opt_cca_ed_or_Msk (0x8000UL)              /*!< opt_cca_ed_or (Bitfield-Mask: 0x01)                   */
+#define MAC_rx_prg_reg_2r_bkrpt0_read_data_Pos (16UL)               /*!< bkrpt0_read_data (Bit 16)                             */
+#define MAC_rx_prg_reg_2r_bkrpt0_read_data_Msk (0xffff0000UL)       /*!< bkrpt0_read_data (Bitfield-Mask: 0xffff)              */
+/* =====================================================  rx_prg_reg_2w  ===================================================== */
+#define MAC_rx_prg_reg_2w_rx_bkprg2_pg_addr_Pos (0UL)               /*!< rx_bkprg2_pg_addr (Bit 0)                             */
+#define MAC_rx_prg_reg_2w_rx_bkprg2_pg_addr_Msk (0xffUL)            /*!< rx_bkprg2_pg_addr (Bitfield-Mask: 0xff)               */
+#define MAC_rx_prg_reg_2w_channel_Pos     (8UL)                     /*!< channel (Bit 8)                                       */
+#define MAC_rx_prg_reg_2w_channel_Msk     (0x7f00UL)                /*!< channel (Bitfield-Mask: 0x7f)                         */
+#define MAC_rx_prg_reg_2w_opt_cca_ed_or_Pos (15UL)                  /*!< opt_cca_ed_or (Bit 15)                                */
+#define MAC_rx_prg_reg_2w_opt_cca_ed_or_Msk (0x8000UL)              /*!< opt_cca_ed_or (Bitfield-Mask: 0x01)                   */
+#define MAC_rx_prg_reg_2w_bkrpt0_reg_addr_Pos (16UL)                /*!< bkrpt0_reg_addr (Bit 16)                              */
+#define MAC_rx_prg_reg_2w_bkrpt0_reg_addr_Msk (0xff0000UL)          /*!< bkrpt0_reg_addr (Bitfield-Mask: 0xff)                 */
+#define MAC_rx_prg_reg_2w_bkrpt0_en_Pos   (24UL)                    /*!< bkrpt0_en (Bit 24)                                    */
+#define MAC_rx_prg_reg_2w_bkrpt0_en_Msk   (0x1000000UL)             /*!< bkrpt0_en (Bitfield-Mask: 0x01)                       */
+/* ======================================================  rx_bkrpt0r  ======================================================= */
+#define MAC_rx_bkrpt0r_bkrpt2_read_data_Pos (0UL)                   /*!< bkrpt2_read_data (Bit 0)                              */
+#define MAC_rx_bkrpt0r_bkrpt2_read_data_Msk (0xffffUL)              /*!< bkrpt2_read_data (Bitfield-Mask: 0xffff)              */
+#define MAC_rx_bkrpt0r_bkrpt1_read_data_Pos (16UL)                  /*!< bkrpt1_read_data (Bit 16)                             */
+#define MAC_rx_bkrpt0r_bkrpt1_read_data_Msk (0xffff0000UL)          /*!< bkrpt1_read_data (Bitfield-Mask: 0xffff)              */
+/* ======================================================  rx_bkrpt0w  ======================================================= */
+#define MAC_rx_bkrpt0w_bkrpt2_reg_addr_Pos (0UL)                    /*!< bkrpt2_reg_addr (Bit 0)                               */
+#define MAC_rx_bkrpt0w_bkrpt2_reg_addr_Msk (0xffUL)                 /*!< bkrpt2_reg_addr (Bitfield-Mask: 0xff)                 */
+#define MAC_rx_bkrpt0w_bkrpt2_en_Pos      (8UL)                     /*!< bkrpt2_en (Bit 8)                                     */
+#define MAC_rx_bkrpt0w_bkrpt2_en_Msk      (0x100UL)                 /*!< bkrpt2_en (Bitfield-Mask: 0x01)                       */
+#define MAC_rx_bkrpt0w_bkrpt1_reg_addr_Pos (16UL)                   /*!< bkrpt1_reg_addr (Bit 16)                              */
+#define MAC_rx_bkrpt0w_bkrpt1_reg_addr_Msk (0xff0000UL)             /*!< bkrpt1_reg_addr (Bitfield-Mask: 0xff)                 */
+#define MAC_rx_bkrpt0w_bkrpt1_en_Pos      (24UL)                    /*!< bkrpt1_en (Bit 24)                                    */
+#define MAC_rx_bkrpt0w_bkrpt1_en_Msk      (0x1000000UL)             /*!< bkrpt1_en (Bitfield-Mask: 0x01)                       */
+/* ======================================================  rx_bkrpt1r  ======================================================= */
+#define MAC_rx_bkrpt1r_bkrpt4_read_data_Pos (0UL)                   /*!< bkrpt4_read_data (Bit 0)                              */
+#define MAC_rx_bkrpt1r_bkrpt4_read_data_Msk (0xffffUL)              /*!< bkrpt4_read_data (Bitfield-Mask: 0xffff)              */
+#define MAC_rx_bkrpt1r_bkrpt3_read_data_Pos (16UL)                  /*!< bkrpt3_read_data (Bit 16)                             */
+#define MAC_rx_bkrpt1r_bkrpt3_read_data_Msk (0xffff0000UL)          /*!< bkrpt3_read_data (Bitfield-Mask: 0xffff)              */
+/* ======================================================  rx_bkrpt1w  ======================================================= */
+#define MAC_rx_bkrpt1w_bkrpt4_reg_addr_Pos (0UL)                    /*!< bkrpt4_reg_addr (Bit 0)                               */
+#define MAC_rx_bkrpt1w_bkrpt4_reg_addr_Msk (0xffUL)                 /*!< bkrpt4_reg_addr (Bitfield-Mask: 0xff)                 */
+#define MAC_rx_bkrpt1w_bkrpt4_en_Pos      (8UL)                     /*!< bkrpt4_en (Bit 8)                                     */
+#define MAC_rx_bkrpt1w_bkrpt4_en_Msk      (0x100UL)                 /*!< bkrpt4_en (Bitfield-Mask: 0x01)                       */
+#define MAC_rx_bkrpt1w_bkrpt3_reg_addr_Pos (16UL)                   /*!< bkrpt3_reg_addr (Bit 16)                              */
+#define MAC_rx_bkrpt1w_bkrpt3_reg_addr_Msk (0xff0000UL)             /*!< bkrpt3_reg_addr (Bitfield-Mask: 0xff)                 */
+#define MAC_rx_bkrpt1w_bkrpt3_en_Pos      (24UL)                    /*!< bkrpt3_en (Bit 24)                                    */
+#define MAC_rx_bkrpt1w_bkrpt3_en_Msk      (0x1000000UL)             /*!< bkrpt3_en (Bitfield-Mask: 0x01)                       */
+/* =====================================================  phy_early_afe  ===================================================== */
+#define MAC_phy_early_afe_rxon_early_afe_Pos (0UL)                  /*!< rxon_early_afe (Bit 0)                                */
+#define MAC_phy_early_afe_rxon_early_afe_Msk (0xffUL)               /*!< rxon_early_afe (Bitfield-Mask: 0xff)                  */
+#define MAC_phy_early_afe_txon_early_afe_Pos (8UL)                  /*!< txon_early_afe (Bit 8)                                */
+#define MAC_phy_early_afe_txon_early_afe_Msk (0xff00UL)             /*!< txon_early_afe (Bitfield-Mask: 0xff)                  */
+#define MAC_phy_early_afe_rampdown_delay_zb_Pos (16UL)              /*!< rampdown_delay_zb (Bit 16)                            */
+#define MAC_phy_early_afe_rampdown_delay_zb_Msk (0x3f0000UL)        /*!< rampdown_delay_zb (Bitfield-Mask: 0x3f)               */
+/* =====================================================  mac_rf_state  ====================================================== */
+#define MAC_mac_rf_state_txrx_cst_Pos     (0UL)                     /*!< txrx_cst (Bit 0)                                      */
+#define MAC_mac_rf_state_txrx_cst_Msk     (0x1fUL)                  /*!< txrx_cst (Bitfield-Mask: 0x1f)                        */
+#define MAC_mac_rf_state_radio_cst_Pos    (5UL)                     /*!< radio_cst (Bit 5)                                     */
+#define MAC_mac_rf_state_radio_cst_Msk    (0x3e0UL)                 /*!< radio_cst (Bitfield-Mask: 0x1f)                       */
+#define MAC_mac_rf_state_dbg_sel_Pos      (10UL)                    /*!< dbg_sel (Bit 10)                                      */
+#define MAC_mac_rf_state_dbg_sel_Msk      (0x3c00UL)                /*!< dbg_sel (Bitfield-Mask: 0x0f)                         */
+#define MAC_mac_rf_state_zb_rx_hit_flg_Pos (14UL)                   /*!< zb_rx_hit_flg (Bit 14)                                */
+#define MAC_mac_rf_state_zb_rx_hit_flg_Msk (0x4000UL)               /*!< zb_rx_hit_flg (Bitfield-Mask: 0x01)                   */
+#define MAC_mac_rf_state_rxframe_Pos      (15UL)                    /*!< rxframe (Bit 15)                                      */
+#define MAC_mac_rf_state_rxframe_Msk      (0x8000UL)                /*!< rxframe (Bitfield-Mask: 0x01)                         */
+#define MAC_mac_rf_state_rxlength_Pos     (16UL)                    /*!< rxlength (Bit 16)                                     */
+#define MAC_mac_rf_state_rxlength_Msk     (0x7f0000UL)              /*!< rxlength (Bitfield-Mask: 0x7f)                        */
+#define MAC_mac_rf_state_zb_rx_full_and_hit_flg_Pos (23UL)          /*!< zb_rx_full_and_hit_flg (Bit 23)                       */
+#define MAC_mac_rf_state_zb_rx_full_and_hit_flg_Msk (0x800000UL)    /*!< zb_rx_full_and_hit_flg (Bitfield-Mask: 0x01)          */
+#define MAC_mac_rf_state_dbg_sel_b4_Pos   (24UL)                    /*!< dbg_sel_b4 (Bit 24)                                   */
+#define MAC_mac_rf_state_dbg_sel_b4_Msk   (0x1000000UL)             /*!< dbg_sel_b4 (Bitfield-Mask: 0x01)                      */
+#define MAC_mac_rf_state_zb_lut_state_Pos (25UL)                    /*!< zb_lut_state (Bit 25)                                 */
+#define MAC_mac_rf_state_zb_lut_state_Msk (0x6000000UL)             /*!< zb_lut_state (Bitfield-Mask: 0x03)                    */
+/* ========================================================  dbg_sig  ======================================================== */
+#define MAC_dbg_sig_zb_rx_hit_cnt_Pos     (0UL)                     /*!< zb_rx_hit_cnt (Bit 0)                                 */
+#define MAC_dbg_sig_zb_rx_hit_cnt_Msk     (0xffffUL)                /*!< zb_rx_hit_cnt (Bitfield-Mask: 0xffff)                 */
+/* ========================================================  cca_dbg  ======================================================== */
+#define MAC_cca_dbg_zb_cca_rpt_Pos        (0UL)                     /*!< zb_cca_rpt (Bit 0)                                    */
+#define MAC_cca_dbg_zb_cca_rpt_Msk        (0xfUL)                   /*!< zb_cca_rpt (Bitfield-Mask: 0x0f)                      */
+#define MAC_cca_dbg_zb_ed_rpt_Pos         (4UL)                     /*!< zb_ed_rpt (Bit 4)                                     */
+#define MAC_cca_dbg_zb_ed_rpt_Msk         (0xff0UL)                 /*!< zb_ed_rpt (Bitfield-Mask: 0xff)                       */
+#define MAC_cca_dbg_rx_cca_duration_Pos   (12UL)                    /*!< rx_cca_duration (Bit 12)                              */
+#define MAC_cca_dbg_rx_cca_duration_Msk   (0x1000UL)                /*!< rx_cca_duration (Bitfield-Mask: 0x01)                 */
+#define MAC_cca_dbg_not_cca_turn_tx_Pos   (13UL)                    /*!< not_cca_turn_tx (Bit 13)                              */
+#define MAC_cca_dbg_not_cca_turn_tx_Msk   (0x2000UL)                /*!< not_cca_turn_tx (Bitfield-Mask: 0x01)                 */
+#define MAC_cca_dbg_not_cca_turn_rx_Pos   (14UL)                    /*!< not_cca_turn_rx (Bit 14)                              */
+#define MAC_cca_dbg_not_cca_turn_rx_Msk   (0x4000UL)                /*!< not_cca_turn_rx (Bitfield-Mask: 0x01)                 */
+#define MAC_cca_dbg_phy_cca_i_Pos         (15UL)                    /*!< phy_cca_i (Bit 15)                                    */
+#define MAC_cca_dbg_phy_cca_i_Msk         (0x8000UL)                /*!< phy_cca_i (Bitfield-Mask: 0x01)                       */
+#define MAC_cca_dbg_txm_txpe_Pos          (16UL)                    /*!< txm_txpe (Bit 16)                                     */
+#define MAC_cca_dbg_txm_txpe_Msk          (0x10000UL)               /*!< txm_txpe (Bitfield-Mask: 0x01)                        */
+#define MAC_cca_dbg_no_cca_vld_flg_Pos    (17UL)                    /*!< no_cca_vld_flg (Bit 17)                               */
+#define MAC_cca_dbg_no_cca_vld_flg_Msk    (0x20000UL)               /*!< no_cca_vld_flg (Bitfield-Mask: 0x01)                  */
+/* =======================================================  cca_dbg1  ======================================================== */
+#define MAC_cca_dbg1_zb_rx_cca_cnt_Pos    (0UL)                     /*!< zb_rx_cca_cnt (Bit 0)                                 */
+#define MAC_cca_dbg1_zb_rx_cca_cnt_Msk    (0xffffUL)                /*!< zb_rx_cca_cnt (Bitfield-Mask: 0xffff)                 */
+#define MAC_cca_dbg1_zb_cca_vld_cnt_Pos   (16UL)                    /*!< zb_cca_vld_cnt (Bit 16)                               */
+#define MAC_cca_dbg1_zb_cca_vld_cnt_Msk   (0xffff0000UL)            /*!< zb_cca_vld_cnt (Bitfield-Mask: 0xffff)                */
+/* ========================================================  rx_set1  ======================================================== */
+#define MAC_rx_set1_rx_min_len_Pos        (0UL)                     /*!< rx_min_len (Bit 0)                                    */
+#define MAC_rx_set1_rx_min_len_Msk        (0x7UL)                   /*!< rx_min_len (Bitfield-Mask: 0x07)                      */
+#define MAC_rx_set1_rxon_off_dly_Pos      (3UL)                     /*!< rxon_off_dly (Bit 3)                                  */
+#define MAC_rx_set1_rxon_off_dly_Msk      (0x3f8UL)                 /*!< rxon_off_dly (Bitfield-Mask: 0x7f)                    */
+#define MAC_rx_set1_rxon2ccadt_dly_Pos    (10UL)                    /*!< rxon2ccadt_dly (Bit 10)                               */
+#define MAC_rx_set1_rxon2ccadt_dly_Msk    (0x3c00UL)                /*!< rxon2ccadt_dly (Bitfield-Mask: 0x0f)                  */
+#define MAC_rx_set1_ed_scan_rxon_delay_Pos (16UL)                   /*!< ed_scan_rxon_delay (Bit 16)                           */
+#define MAC_rx_set1_ed_scan_rxon_delay_Msk (0xff0000UL)             /*!< ed_scan_rxon_delay (Bitfield-Mask: 0xff)              */
+#define MAC_rx_set1_rx2tx_imm_ack_delay_Pos (24UL)                  /*!< rx2tx_imm_ack_delay (Bit 24)                          */
+#define MAC_rx_set1_rx2tx_imm_ack_delay_Msk (0xff000000UL)          /*!< rx2tx_imm_ack_delay (Bitfield-Mask: 0xff)             */
+/* ====================================================  tx_enh_ack_ctrl  ==================================================== */
+#define MAC_tx_enh_ack_ctrl_gts_enh_ack_timer_Pos (0UL)             /*!< gts_enh_ack_timer (Bit 0)                             */
+#define MAC_tx_enh_ack_ctrl_gts_enh_ack_timer_Msk (0xffUL)          /*!< gts_enh_ack_timer (Bitfield-Mask: 0xff)               */
+#define MAC_tx_enh_ack_ctrl_rx2tx_enh_ack_delay_Pos (8UL)           /*!< rx2tx_enh_ack_delay (Bit 8)                           */
+#define MAC_tx_enh_ack_ctrl_rx2tx_enh_ack_delay_Msk (0xff00UL)      /*!< rx2tx_enh_ack_delay (Bitfield-Mask: 0xff)             */
+#define MAC_tx_enh_ack_ctrl_gts_enh_ack_trig_en_Pos (16UL)          /*!< gts_enh_ack_trig_en (Bit 16)                          */
+#define MAC_tx_enh_ack_ctrl_gts_enh_ack_trig_en_Msk (0x10000UL)     /*!< gts_enh_ack_trig_en (Bitfield-Mask: 0x01)             */
+#define MAC_tx_enh_ack_ctrl_alt_gts_enh_ack_mask_Pos (17UL)         /*!< alt_gts_enh_ack_mask (Bit 17)                         */
+#define MAC_tx_enh_ack_ctrl_alt_gts_enh_ack_mask_Msk (0x20000UL)    /*!< alt_gts_enh_ack_mask (Bitfield-Mask: 0x01)            */
+#define MAC_tx_enh_ack_ctrl_alt_gts_enh_ack_timer_Pos (24UL)        /*!< alt_gts_enh_ack_timer (Bit 24)                        */
+#define MAC_tx_enh_ack_ctrl_alt_gts_enh_ack_timer_Msk (0xff000000UL) /*!< alt_gts_enh_ack_timer (Bitfield-Mask: 0xff)          */
+/* =======================================================  pta_ctrl1  ======================================================= */
+#define MAC_pta_ctrl1_pta_en_Pos          (0UL)                     /*!< pta_en (Bit 0)                                        */
+#define MAC_pta_ctrl1_pta_en_Msk          (0x1UL)                   /*!< pta_en (Bitfield-Mask: 0x01)                          */
+#define MAC_pta_ctrl1_pta_share_lna_Pos   (1UL)                     /*!< pta_share_lna (Bit 1)                                 */
+#define MAC_pta_ctrl1_pta_share_lna_Msk   (0x2UL)                   /*!< pta_share_lna (Bitfield-Mask: 0x01)                   */
+#define MAC_pta_ctrl1_cca_req_Pos         (2UL)                     /*!< cca_req (Bit 2)                                       */
+#define MAC_pta_ctrl1_cca_req_Msk         (0x4UL)                   /*!< cca_req (Bitfield-Mask: 0x01)                         */
+#define MAC_pta_ctrl1_tx_priority_Pos     (3UL)                     /*!< tx_priority (Bit 3)                                   */
+#define MAC_pta_ctrl1_tx_priority_Msk     (0x8UL)                   /*!< tx_priority (Bitfield-Mask: 0x01)                     */
+/* =======================================================  pta_ctrl0  ======================================================= */
+#define MAC_pta_ctrl0_pta_duty_en_Pos     (0UL)                     /*!< pta_duty_en (Bit 0)                                   */
+#define MAC_pta_ctrl0_pta_duty_en_Msk     (0x1UL)                   /*!< pta_duty_en (Bitfield-Mask: 0x01)                     */
+#define MAC_pta_ctrl0_dis_lo_rx_req_Pos   (1UL)                     /*!< dis_lo_rx_req (Bit 1)                                 */
+#define MAC_pta_ctrl0_dis_lo_rx_req_Msk   (0x2UL)                   /*!< dis_lo_rx_req (Bitfield-Mask: 0x01)                   */
+#define MAC_pta_ctrl0_pta_tick_ctrl_Pos   (4UL)                     /*!< pta_tick_ctrl (Bit 4)                                 */
+#define MAC_pta_ctrl0_pta_tick_ctrl_Msk   (0xfff0UL)                /*!< pta_tick_ctrl (Bitfield-Mask: 0xfff)                  */
+#define MAC_pta_ctrl0_pta_low_duty_tick_Pos (16UL)                  /*!< pta_low_duty_tick (Bit 16)                            */
+#define MAC_pta_ctrl0_pta_low_duty_tick_Msk (0xff0000UL)            /*!< pta_low_duty_tick (Bitfield-Mask: 0xff)               */
+#define MAC_pta_ctrl0_pta_high_duty_tick_Pos (24UL)                 /*!< pta_high_duty_tick (Bit 24)                           */
+#define MAC_pta_ctrl0_pta_high_duty_tick_Msk (0xff000000UL)         /*!< pta_high_duty_tick (Bitfield-Mask: 0xff)              */
+
+/** @} */ /* End of group PosMask_peripherals */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* MAC_REG_MASK_H */
+
+
+/** @} */ /* End of group rtl87x2g */
+
+/** @} */ /* End of group Realtek Semiconductor Corp. */
diff --git a/bee/drivers/mac_802154/rom/mac_reg_type.h b/bee/drivers/mac_802154/rom/mac_reg_type.h
new file mode 100644
index 00000000..554ceaf4
--- /dev/null
+++ b/bee/drivers/mac_802154/rom/mac_reg_type.h
@@ -0,0 +1,3275 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**************************************************************************//**
+ * @file      mac_reg_type.h
+ * @brief
+ * @version   V1.00
+ * @date      2023-7-12 18:32:16
+ *
+ * @note
+ *
+ ******************************************************************************/
+
+#ifndef _MAC_REG_TYPE_H_
+#define _MAC_REG_TYPE_H_
+
+#ifdef  __cplusplus
+extern "C"
+{
+#endif
+
+/// @cond DOXYGEN_GENERAL_REG_TYPE || DOXYGEN_MAC_REG_TYPE
+
+/**
+ * @addtogroup ls_hal_mac_reg MAC Registers.
+ * @ingroup ls_hal_mac
+ * @{
+ */
+
+/**
+  \brief Union type to access mac_device_ctrl (@ 0x00000000).
+*/
+typedef union {
+  __IOM uint32_t w;                           /*!< (@ 0x00000000) MAC Device Control Register                                */
+
+  struct {
+    __IOM uint32_t coord      : 1;            /*!< [0..0] Coordinator: 0: (default) Device is not set as coordinator;
+                                                   1: Set device as coordinator                                              */
+    __IOM uint32_t pancoord   : 1;            /*!< [1..1] PAN Coordinator: 0: (default) Device is not set as PAN
+                                                   coordinator; 1: Set device as PAN coordinator                             */
+    __IOM uint32_t mac_lpbk   : 1;            /*!< [2..2] MAC loopback function enable                                       */
+    __IOM uint32_t noackrsp   : 1;            /*!< [3..3] Automatic Acknowledgement Response: 0: (default) Enables
+                                                   automatic acknowledgement response; 1: Disables automatic
+                                                   acknowledgement response                                                  */
+          uint32_t            : 1;
+    __IOM uint32_t nocrc      : 1;            /*!< [5..5] No CRC data appended with normal fifo                              */
+    __IOM uint32_t fifoen     : 1;            /*!< [6..6] The TXFIFO and RXFIFO output enable control: 0: The TXFIFO
+                                                   and RXFIFO are always output enabled; 1: The enabled signal
+                                                   for the TXFIFO and RXFIFO output is controlled by the internal
+                                                   state machine                                                             */
+          uint32_t            : 1;
+    __IOM uint32_t split_irq  : 1;            /*!< [8..8] Split security IRQ with normal IRQ                                 */
+    __IOM uint32_t irqpol     : 1;            /*!< [9..9] Interrupt Edge Polarity: 0: (default) Falling edge; 1:
+                                                   Rising edge                                                               */
+          uint32_t            : 6;
+    __IOM uint32_t tickp      : 9;            /*!< [24..16] Ticks period representing a symbol.Unit in system clock
+                                                   (20MHz). Default a symbol time is 16us. Tickp = 16/(1/20)
+                                                   = 320d = 140H                                                             */
+          uint32_t            : 7;
+  } b;                                        /*!< bit fields for mac_device_ctrl */
+} mac_device_ctrl_t, *pmac_device_ctrl_t;
+
+/**
+  \brief Union type to access mac_panid (@ 0x00000004).
+*/
+typedef union {
+  __IOM uint16_t w;                           /*!< (@ 0x00000004) PAN ID Configuration Register                              */
+
+  struct {
+    __IOM uint16_t panid      : 16;           /*!< [15..0] 16-bits PAN identifier of this device                             */
+  } b;                                        /*!< bit fields for mac_panid */
+} mac_panid_t, *pmac_panid_t;
+
+/**
+  \brief Union type to access mac_sadr (@ 0x00000006).
+*/
+typedef union {
+  __IOM uint16_t w;                           /*!< (@ 0x00000006) Short Address Configuration Register                       */
+
+  struct {
+    __IOM uint16_t sadr       : 16;           /*!< [15..0] 16-bits Short Address of this device                              */
+  } b;                                        /*!< bit fields for mac_sadr */
+} mac_sadr_t, *pmac_sadr_t;
+
+/**
+  \brief Union type to access mac_eadr_l (@ 0x00000008).
+*/
+typedef union {
+  __IOM uint32_t w;                           /*!< (@ 0x00000008) Extended Address Lower Bytes Register                      */
+
+  struct {
+    __IOM uint32_t eadr_l     : 32;           /*!< [31..0] Bits[31:0] of Extended Address of this device                     */
+  } b;                                        /*!< bit fields for mac_eadr_l */
+} mac_eadr_l_t, *pmac_eadr_l_t;
+
+/**
+  \brief Union type to access mac_eadr_h (@ 0x0000000C).
+*/
+typedef union {
+  __IOM uint32_t w;                           /*!< (@ 0x0000000C) Extended Address Higher Bytes Register                     */
+
+  struct {
+    __IOM uint32_t eadr_h     : 32;           /*!< [31..0] Bits[63:32] of Extended Address of this device                    */
+  } b;                                        /*!< bit fields for mac_eadr_h */
+} mac_eadr_h_t, *pmac_eadr_h_t;
+
+/**
+  \brief Union type to access mac_clk_ctrl (@ 0x00000010).
+*/
+typedef union {
+  __IOM uint32_t w;                           /*!< (@ 0x00000010) Clock Gated Control Register                               */
+
+  struct {
+    __IOM uint32_t ctrl_sec   : 1;            /*!< [0..0] Security clock controller                                          */
+    __IOM uint32_t en_sec     : 1;            /*!< [1..1] Security clock enable/disable when CTRL_SEC is '1'                 */
+    __IOM uint32_t entxm      : 1;            /*!< [2..2] TX MAC Clock Enable: 0: (default) Disable; 1: Enable               */
+    __IOM uint32_t engts      : 1;            /*!< [3..3] GTS FIFO Clock: 0: (default) Disable; 1: Enable                    */
+    __IOM uint32_t enrxm      : 1;            /*!< [4..4] RX MAC Clock Enable: 0: (default) Disable; 1: Enable               */
+    __IOM uint32_t txn_off    : 1;            /*!< [5..5] TXNFIFO clock always off                                           */
+    __IOM uint32_t txb_on     : 1;            /*!< [6..6] Beacon FIFO clock always on                                        */
+    __IOM uint32_t ffidle     : 1;            /*!< [7..7] Force Clock Enable (Rx / Source Match Filter / GTS FIFO
+                                                   / TX Normal)0: (default) Disable1: Enable                                 */
+    __IOM uint32_t ed_scan_clkon : 1;         /*!< [8..8] Force enable clock of ED scan block0: (default) Disable,
+                                                   clock is auto-gated1: Enable                                              */
+    __IOM uint32_t phy_arb_clkon : 1;         /*!< [9..9] Force enable clock of PHY arbitration block0: (default)
+                                                   Disable, clock is auto-gated1: Enable                                     */
+    __IOM uint32_t fifo_clkon : 1;            /*!< [10..10] Force enable Beacon / Normal / GTS / RX / SEC KEY FIFO
+                                                   Clock:0: (default) Disable1: Enable                                       */
+    __IOM uint32_t dbg_clkon  : 1;            /*!< [11..11] Force enable Debug counter circuit clock:0: (default)
+                                                   Disable1: Enable                                                          */
+          uint32_t            : 20;
+  } b;                                        /*!< bit fields for mac_clk_ctrl */
+} mac_clk_ctrl_t, *pmac_clk_ctrl_t;
+
+/**
+  \brief Union type to access mac_mac_timer (@ 0x00000014).
+*/
+typedef union {
+  __IOM uint32_t w;                           /*!< (@ 0x00000014) MAC Timer Control Register                                 */
+
+  struct {
+    __OM  uint32_t mactmr_l   : 8;            /*!< [7..0] 16-Bit MAC Timer, Low Byte                                         */
+    __OM  uint32_t mactmr_h   : 8;            /*!< [15..8] 16-Bit MAC Timer, High Byte. Unit: 8us. FW writing this
+                                                   field will trigger MAC timer start to count down                          */
+    __IOM uint32_t mactmrfr   : 1;            /*!< [16..16] MAC Timer Free Run: 0: (default) Disable; 1: Enable.
+                                                   If the free-run value of MAC timer is selected to be attached
+                                                   to every received packet behind RSSI, this MAC timer free
+                                                   run should be enabled.                                                    */
+          uint32_t            : 7;
+    __OM  uint32_t btcmp0_dis : 1;            /*!< [24..24] BT-MAC Timer (BT Clock comparator) 0 disable.0: (default)
+                                                   malfunction1: Disable BT-MAC timer comparator function.
+                                                   FW can write this bit as 1 to stop the BT-MAC timer 0 if
+                                                   it is running.This bit is cleared to '0' by hardware automatically.       */
+    __OM  uint32_t btcmp1_dis : 1;            /*!< [25..25] BT-MAC Timer (BT Clock comparator) 1 disable.0: (default)
+                                                   malfunction1: Disable BT-MAC timer comparator function.
+                                                   FW can write this bit as 1 to stop the BT-MAC timer 1 if
+                                                   it is running.This bit is cleared to '0' by hardware automatically
+                                                   .                                                                         */
+    __OM  uint32_t btcmp2_dis : 1;            /*!< [26..26] BT-MAC Timer (BT Clock comparator) 2 disable.0: (default)
+                                                   malfunction1: Disable BT-MAC timer comparator function.
+                                                   FW can write this bit as 1 to stop the BT-MAC timer 2 if
+                                                   it is running.This bit is cleared to '0' by hardware automatically
+                                                   .                                                                         */
+    __OM  uint32_t btcmp3_dis : 1;            /*!< [27..27] BT-MAC Timer (BT Clock comparator) 3 disable.0: (default)
+                                                   malfunction1: Disable BT-MAC timer comparator function.
+                                                   FW can write this bit as 1 to stop the BT-MAC timer 3 if
+                                                   it is running.This bit is cleared to '0' by hardware automatically
+                                                   .                                                                         */
+          uint32_t            : 4;
+  } b;                                        /*!< bit fields for mac_mac_timer */
+} mac_mac_timer_t, *pmac_mac_timer_t;
+
+/**
+  \brief Union type to access mac_rst_ctrl (@ 0x00000018).
+*/
+typedef union {
+  __IOM uint32_t w;                           /*!< (@ 0x00000018) MAC Reset Control Register                                 */
+
+  struct {
+          uint32_t            : 16;
+    __OM  uint32_t rstmac     : 1;            /*!< [16..16] MAC and Registers Reset: 1: Reset MAC circuitry and
+                                                   all registers. Initialization is needed after RSTMAC reset.
+                                                   Bit is automatically cleared to '0' by hardware                           */
+          uint32_t            : 15;
+  } b;                                        /*!< bit fields for mac_rst_ctrl */
+} mac_rst_ctrl_t, *pmac_rst_ctrl_t;
+
+/**
+  \brief Union type to access mac_rx_frm_length (@ 0x0000001C).
+*/
+typedef union {
+  __IOM uint32_t w;                           /*!< (@ 0x0000001C) RX Decryption Header Length Control Register               */
+
+  struct {
+    __IOM uint32_t hlen       : 7;            /*!< [6..0] Header Length for Decryption Process in RX FIFO. Header
+                                                   length of the received packet including frame control field,
+                                                   sequence number and address information. If a user-defined
+                                                   header length (including auxiliary header length) is used,
+                                                   user shall update the length value by writing HLEN[5:0]
+                                                   back after security interrupt received. 000000: (default)                 */
+          uint32_t            : 1;
+    __IM  uint32_t flen       : 7;            /*!< [14..8] Internal frame length                                             */
+          uint32_t            : 17;
+  } b;                                        /*!< bit fields for mac_rx_frm_length */
+} mac_rx_frm_length_t, *pmac_rx_frm_length_t;
+
+/**
+  \brief Union type to access mac_intmsk (@ 0x00000020).
+*/
+typedef union {
+  __IOM uint32_t w;                           /*!< (@ 0x00000020) Interrupt Mask Control Register                            */
+
+  struct {
+    __IOM uint32_t txnmsk     : 1;            /*!< [0..0] TX Normal FIFO Transmission Interrupt Mask: 0: Enable
+                                                   the TX Normal FIFO transmission interrupt; 1: (default)
+                                                   Disable the TX Normal FIFO transmission interrupt                         */
+    __IOM uint32_t txg1msk    : 1;            /*!< [1..1] TX GTS1 FIFO Transmission Interrupt Mask: 0: Enable the
+                                                   TX GTS1 FIFO transmission interrupt; 1: (default) Disable
+                                                   the TX GTS1 FIFO transmission interrupt                                   */
+    __IOM uint32_t txg2msk    : 1;            /*!< [2..2] TX GTS2 FIFO Transmission Interrupt Mask: 0: Enable the
+                                                   TX GTS2 FIFO transmission interrupt; 1: (default) Disable
+                                                   the TX GTS2 FIFO transmission interrupt                                   */
+    __IOM uint32_t txnterrmsk : 1;            /*!< [3..3] TX at given time error Interrupt Mask: 0: Enable the
+                                                   TX at given time error interrupt; 1: (default) Disable
+                                                   the TX at given time error interrupt TX at given time error
+                                                   interrupt is triggered when a Normal FIFO TX at a scheduled
+                                                   TX time error is occurred. This error could be caused by
+                                                   an invalid TX time or CCA failure                                         */
+    __IOM uint32_t rxelymsk   : 1;            /*!< [4..4] RX eraly Interrupt Mask: 0: Enable the RX eraly interrupt;
+                                                   1: (default) Disable the RX eraly interrupt RX early interrupt
+                                                   is triggered when on the receiving of an incoming frame
+                                                   and its MAC header and Secure AUX Header (if present) are
+                                                   received complete and pass the RX filter check                            */
+    __IOM uint32_t secmsk     : 1;            /*!< [5..5] Security Key Request Interrupt Mask: 0: Enable security
+                                                   key request interrupt; 1: (default) Disable the security
+                                                   key request interrupt                                                     */
+    __IOM uint32_t rxmsk      : 1;            /*!< [6..6] RX FIFO Reception Interrupt Mask: 0: Enable the RX FIFO
+                                                   reception interrupt; 1: (default) Disable the RX FIFO reception
+                                                   interrupt                                                                 */
+    __IOM uint32_t mactmrmsk  : 1;            /*!< [7..7] MAC Timer Interrupt Mask: 0: Enable the MAC timer interrupt;
+                                                   1: (default) Disable the MAC timer interrupt                              */
+    __IOM uint32_t btcmp0msk  : 1;            /*!< [8..8] BT-MAC timer 0 Interrupt Mask: 0: Enable the BT-MAC timer
+                                                   interrupt; 1: (default) Disable the BT-MAC timer interrupt
+                                                   BT-MAC timer interrupt is triggered when the counter value
+                                                   of the free run BT-MAC timer is matched with the BT-MAC
+                                                   timer comparator value.                                                   */
+    __IOM uint32_t btcmp1msk  : 1;            /*!< [9..9] BT-MAC timer 1 Interrupt Mask: 0: Enable the BT-MAC timer
+                                                   interrupt; 1: (default) Disable the BT-MAC timer interrupt
+                                                   BT-MAC timer interrupt is triggered when the counter value
+                                                   of the free run BT-MAC timer is matched with the BT-MAC
+                                                   timer comparator value.                                                   */
+    __IOM uint32_t gntmsk     : 1;            /*!< [10..10] PHY grant update Interrupt Mask: 0: Enable PHY grant
+                                                   update interrupt; 1: (default) Disable the PHY grant update
+                                                   interrupt PHY grant update interrupt is triggered when
+                                                   the PHY grant request success or failed, or PHY grant is
+                                                   de-asserted by Arbitration Coordinator.                                   */
+    __IOM uint32_t edscanmsk  : 1;            /*!< [11..11] ED scan done Interrupt Mask: 0: Enable ED scan done
+                                                   interrupt; 1: (default) Disable the ED scan done interrupt
+                                                   ED scan done interrupt is triggered when an ED scan procedure
+                                                   is done                                                                   */
+    __IOM uint32_t sfstartmsk : 1;            /*!< [12..12] Slotted enable Superframe start Interrupt Mask: 0:
+                                                   Enable the superframe start interrupt; 1: (default) Disable
+                                                   the superframe start interrupt                                            */
+    __IOM uint32_t sfendmsk   : 1;            /*!< [13..13] Slotted enable Superframe end Interrupt Mask: 0: Enable
+                                                   the superframe end interrupt; 1: (default) Disable the
+                                                   superframe end interrupt                                                  */
+    __IOM uint32_t btcmp2msk  : 1;            /*!< [14..14] BT-MAC timer 2 Interrupt Mask: 0: Enable the BT-MAC
+                                                   timer interrupt; 1: (default) Disable the BT-MAC timer
+                                                   interrupt BT-MAC timer interrupt is triggered when the
+                                                   counter value of the free run BT-MAC timer is matched with
+                                                   the BT-MAC timer comparator value.                                        */
+    __IOM uint32_t btcmp3msk  : 1;            /*!< [15..15] BT-MAC timer 3 Interrupt Mask: 0: Enable the BT-MAC
+                                                   timer interrupt; 1: (default) Disable the BT-MAC timer
+                                                   interrupt BT-MAC timer interrupt is triggered when the
+                                                   counter value of the free run BT-MAC timer is matched with
+                                                   the BT-MAC timer comparator value.                                        */
+          uint32_t            : 16;
+  } b;                                        /*!< bit fields for mac_intmsk */
+} mac_intmsk_t, *pmac_intmsk_t;
+
+/**
+  \brief Union type to access mac_isrsts (@ 0x00000024).
+*/
+typedef union {
+  __IOM uint32_t w;                           /*!< (@ 0x00000024) Interrupt Status Register                                  */
+
+  struct {
+    __IOM uint32_t txnif      : 1;            /*!< [0..0] TX Normal FIFO Transmission Interrupt: 0: (default) No
+                                                   TX Normal FIFO transmission interrupt occurred; 1: TX Normal
+                                                   FIFO transmission interrupt occurred, Write 1 clear                       */
+    __IOM uint32_t txg1if     : 1;            /*!< [1..1] TX GTS1 FIFO Transmission Interrupt: 0: (default) No
+                                                   TX GTS1 FIFO transmission interrupt occurred; 1: A TX GTS1
+                                                   FIFO transmission interrupt occurred, Write 1 clear                       */
+    __IOM uint32_t txg2if     : 1;            /*!< [2..2] TX GTS2 FIFO Transmission Interrupt: 0: (default) No
+                                                   TX GTS2 FIFO transmission interrupt occurred; 1: A TX GTS2
+                                                   FIFO transmission interrupt occurred, Write 1 clear                       */
+    __IOM uint32_t txnterrif  : 1;            /*!< [3..3] TX at given time error Interrupt status: 0: (default)
+                                                   no TX at given time error interrupt occurred; 1: the TX
+                                                   at given time error interrupt is occurred. TX at given
+                                                   time error interrupt is triggered when a Normal FIFO TX
+                                                   at a scheduled TX time error is occurred. This error could
+                                                   be caused by an invalid TX time or CCA failure. Write 1
+                                                   clear.                                                                    */
+    __IOM uint32_t rxelyif    : 1;            /*!< [4..4] RX eraly Interrupt status: 0: (default)no RX eraly interrupt
+                                                   occurred; 1: the RX eraly interrupt is occurred. RX early
+                                                   interrupt is triggered when on the receiving of an incoming
+                                                   frame and its MAC header and Secure AUX Header (if present)
+                                                   are received complete and pass the RX filter check. Write
+                                                   1 clear.                                                                  */
+    __IOM uint32_t secif      : 1;            /*!< [5..5] Security Key Request Interrupt: 0: (default) No security
+                                                   key request interrupt occurred; 1: A security key request
+                                                   interrupt occurred, Write 1 clear                                         */
+    __IOM uint32_t rxif       : 1;            /*!< [6..6] RX FIFO Reception Interrupt: 0: (default) No RX FIFO
+                                                   reception interrupt occurred; 1: An RX FIFO reception interrupt
+                                                   occurred, Write 1 clear                                                   */
+    __IOM uint32_t mactmrif   : 1;            /*!< [7..7] MAC timer Interrupt: 0: (default) No MAC timer interrupt
+                                                   occurred; 1: A MAC timer interrupt occurred, Write 1 clear                */
+    __IOM uint32_t btcmp0if   : 1;            /*!< [8..8] BT-MAC timer 0 Interrupt status: 0: (default) no BT-MAC
+                                                   timer interrupt occurred; 1: the BT-MAC timer interrupt
+                                                   is occurred. BT-MAC timer interrupt is triggered when the
+                                                   counter value of the free run BT-MAC timer is matched with
+                                                   the BT-MAC timer comparator value. Write 1 clear.                         */
+    __IOM uint32_t btcmp1if   : 1;            /*!< [9..9] BT-MAC timer 1 Interrupt status: 0: (default) no BT-MAC
+                                                   timer interrupt occurred; 1: the BT-MAC timer interrupt
+                                                   is occurred. BT-MAC timer interrupt is triggered when the
+                                                   counter value of the free run BT-MAC timer is matched with
+                                                   the BT-MAC timer comparator value. Write 1 clear.                         */
+    __IOM uint32_t gntif      : 1;            /*!< [10..10] PHY grant update Interrupt status: 0: no PHY grant
+                                                   update interrupt is occurred; 1: PHY grant update interrupt
+                                                   is occurred. PHY grant update interrupt is triggered when
+                                                   the PHY grant request success or failed, or PHY grant is
+                                                   de-asserted by Arbitration Coordinator.                                   */
+    __IOM uint32_t edscanif   : 1;            /*!< [11..11] ED scan done Interrupt status: 0: no ED scan done interrupt
+                                                   occurred; 1: the ED scan done interrupt is occurred ED
+                                                   scan done interrupt is triggered when an ED scan procedure
+                                                   is done                                                                   */
+    __IOM uint32_t sfstartif  : 1;            /*!< [12..12] Slotted enable Superframe start Interrupt status: 0:
+                                                   no superframe start interrupt is pending; 1: the superframe
+                                                   start interrupt is occurred and pending                                   */
+    __IOM uint32_t sfendif    : 1;            /*!< [13..13] Slotted enable Superframe end Interrupt status: 0:
+                                                   no superframe end interrupt is pending; 1: the superframe
+                                                   end interrupt is occurred and pending                                     */
+    __IOM uint32_t btcmp2if   : 1;            /*!< [14..14] BT-MAC timer 2 Interrupt status: 0: (default) no BT-MAC
+                                                   timer interrupt occurred; 1: the BT-MAC timer interrupt
+                                                   is occurred. BT-MAC timer interrupt is triggered when the
+                                                   counter value of the free run BT-MAC timer is matched with
+                                                   the BT-MAC timer comparator value. Write 1 clear.                         */
+    __IOM uint32_t btcmp3if   : 1;            /*!< [15..15] BT-MAC timer 3 Interrupt status: 0: (default) no BT-MAC
+                                                   timer interrupt occurred; 1: the BT-MAC timer interrupt
+                                                   is occurred. BT-MAC timer interrupt is triggered when the
+                                                   counter value of the free run BT-MAC timer is matched with
+                                                   the BT-MAC timer comparator value. Write 1 clear.                         */
+          uint32_t            : 16;
+  } b;                                        /*!< bit fields for mac_isrsts */
+} mac_isrsts_t, *pmac_isrsts_t;
+
+/**
+  \brief Union type to access mac_bt_clk_cmp0 (@ 0x00000028).
+*/
+typedef union {
+  __IOM uint32_t w;                           /*!< (@ 0x00000028) BT Clock Comparator 0 Register                             */
+
+  struct {
+    __IOM uint32_t bt_ckc     : 10;           /*!< [9..0] The clock counter value of the BT-MAC timer comparator.When
+                                                   the (BT NativeClock[22:1] || ClockCounter[9:0]) timer value
+                                                   is matched with (bt_nclk || bt_ckc) then trigger the BT-MAC
+                                                   timer comparator0 interrupt.                                              */
+    __IOM uint32_t bt_nclk    : 22;           /*!< [31..10] The native clock value of the BT-MAC timer comparator.
+                                                   When the (BT NativeClock[22:1] || ClockCounter[9:0]) value
+                                                   is matched with (bt_nclk || bt_ckc) then trigger the BT-MAC
+                                                   timer comparator interrupt.                                               */
+  } b;                                        /*!< bit fields for mac_bt_clk_cmp0 */
+} mac_bt_clk_cmp0_t, *pmac_bt_clk_cmp0_t;
+
+/**
+  \brief Union type to access mac_bt_clk_cmp1 (@ 0x0000002C).
+*/
+typedef union {
+  __IOM uint32_t w;                           /*!< (@ 0x0000002C) BT Clock Comparator 1 Register                             */
+
+  struct {
+    __IOM uint32_t bt_ckc     : 10;           /*!< [9..0] The clock counter value of the BT-MAC timer comparator.When
+                                                   the (BT NativeClock[22:1] || ClockCounter[9:0]) timer value
+                                                   is matched with (bt_nclk || bt_ckc) then trigger the BT-MAC
+                                                   timer comparator1 interrupt.                                              */
+    __IOM uint32_t bt_nclk    : 22;           /*!< [31..10] The native clock value of the BT-MAC timer comparator.
+                                                   When the (BT NativeClock[22:1] || ClockCounter[9:0]) value
+                                                   is matched with (bt_nclk || bt_ckc) then trigger the BT-MAC
+                                                   timer comparator interrupt.                                               */
+  } b;                                        /*!< bit fields for mac_bt_clk_cmp1 */
+} mac_bt_clk_cmp1_t, *pmac_bt_clk_cmp1_t;
+
+/**
+  \brief Union type to access mac_bt_clk_cmp2 (@ 0x00000030).
+*/
+typedef union {
+  __IOM uint32_t w;                           /*!< (@ 0x00000030) BT Clock Comparator 2 Register                             */
+
+  struct {
+    __IOM uint32_t bt_ckc     : 10;           /*!< [9..0] The clock counter value of the BT-MAC timer comparator.When
+                                                   the (BT NativeClock[22:1] || ClockCounter[9:0]) timer value
+                                                   is matched with (bt_nclk || bt_ckc) then trigger the BT-MAC
+                                                   timer comparator2 interrupt.                                              */
+    __IOM uint32_t bt_nclk    : 22;           /*!< [31..10] The native clock value of the BT-MAC timer comparator.
+                                                   When the (BT NativeClock[22:1] || ClockCounter[9:0]) value
+                                                   is matched with (bt_nclk || bt_ckc) then trigger the BT-MAC
+                                                   timer comparator interrupt.                                               */
+  } b;                                        /*!< bit fields for mac_bt_clk_cmp2 */
+} mac_bt_clk_cmp2_t, *pmac_bt_clk_cmp2_t;
+
+/**
+  \brief Union type to access mac_bt_clk_cmp3 (@ 0x00000034).
+*/
+typedef union {
+  __IOM uint32_t w;                           /*!< (@ 0x00000034) BT Clock Comparator 3 Register                             */
+
+  struct {
+    __IOM uint32_t bt_ckc     : 10;           /*!< [9..0] The clock counter value of the BT-MAC timer comparator.When
+                                                   the (BT NativeClock[22:1] || ClockCounter[9:0]) timer value
+                                                   is matched with (bt_nclk || bt_ckc) then trigger the BT-MAC
+                                                   timer comparator3 interrupt.                                              */
+    __IOM uint32_t bt_nclk    : 22;           /*!< [31..10] The native clock value of the BT-MAC timer comparator.
+                                                   When the (BT NativeClock[22:1] || ClockCounter[9:0]) value
+                                                   is matched with (bt_nclk || bt_ckc) then trigger the BT-MAC
+                                                   timer comparator interrupt.                                               */
+  } b;                                        /*!< bit fields for mac_bt_clk_cmp3 */
+} mac_bt_clk_cmp3_t, *pmac_bt_clk_cmp3_t;
+
+/**
+  \brief Union type to access mac_ed_scan_ctrl0 (@ 0x00000038).
+*/
+typedef union {
+  __IOM uint32_t w;                           /*!< (@ 0x00000038) ED Scan Control Register 0                                 */
+
+  struct {
+    __IOM uint32_t scan_enable : 1;           /*!< [0..0] write this bit to start or stop ED scan procedure: 1:
+                                                   trigger the ED scan start; 0: cancel a running ED scan;
+                                                   HW will clear this bit when ED scan procedure is done.
+                                                   The ED scan status is updated in bits[29:26] and ED level
+                                                   is updated in peak_value (bits[21:14])                                    */
+    __IOM uint32_t scan_round : 13;           /*!< [13..1] set the round of symbols (default 8 symbols) ED scan
+                                                   to run for a whole ED scan procedure. Scan round = ed_scan_round
+                                                   + 1, ed_scan_round valid value is 0 ~ 8191.                               */
+    __IM  uint32_t peak_value : 8;            /*!< [21..14] keep the peak value of ED scan result                            */
+    __IOM uint32_t scan_symbol : 4;           /*!< [25..22] number of symbol for a round of ED scan, default a
+                                                   round scan 8 symbols                                                      */
+    __IM  uint32_t ed_scan_encounter_tx_trig_sts : 1;/*!< [26..26] indicates ED scan is canceled due to conflict with
+                                                   TX trigger.                                                               */
+    __IM  uint32_t scan_fw_cancel_sts : 1;    /*!< [27..27] indicates the ED scan procedure is finished due to
+                                                   FW cancel                                                                 */
+    __IM  uint32_t scan_gnt_deassert_sts : 1; /*!< [28..28] indicates the ED scan procedure is finished due to
+                                                   PHY grant is de-asserted                                                  */
+    __IM  uint32_t scan_ed_vld_tmo_sts : 1;   /*!< [29..29] indicates the ED scan procedure is finished due to
+                                                   wait PHY report valid timeout                                             */
+    __IM  uint32_t scan_finish_sts : 1;       /*!< [30..30] ed scan finish status:1: ED scan is finished normally            */
+    __IOM uint32_t scan_done  : 1;            /*!< [31..31] MAC HW set this bit to indicates current ED scan is
+                                                   done. Once this bit is set, bits [30:27] indicates the
+                                                   ED scan status. This bit is cleaned by write 1.                           */
+  } b;                                        /*!< bit fields for mac_ed_scan_ctrl0 */
+} mac_ed_scan_ctrl0_t, *pmac_ed_scan_ctrl0_t;
+
+/**
+  \brief Union type to access mac_ed_scan_ctrl1 (@ 0x0000003C).
+*/
+typedef union {
+  __IOM uint32_t w;                           /*!< (@ 0x0000003C) ED Scan Control Register 1                                 */
+
+  struct {
+    __IM  uint32_t scan_cnt   : 14;           /*!< [13..0] indicates how many round of ED symbols scan has ran               */
+    __IOM uint32_t scan_vld_tmo_cnt_limit : 6;/*!< [19..14] set the timeout for PHY scan report valid waitting.
+                                                   Unit is 1T (0.05us for 20MHz)                                             */
+    __IOM uint32_t scan_first_ed_scan_symbol : 4;/*!< [23..20] Timing adjustment before of the 1st round of ED symbols
+                                                   scan. Unit is symbol. Timing adjustment = symbol + cnt.                   */
+    __IOM uint32_t scan_first_ed_scan_cnt : 8;/*!< [31..24] Timing adjustment before of the 1st round of ED symbols
+                                                   scan. Unit is 1 clock (0.05us for 20MHz).                                 */
+  } b;                                        /*!< bit fields for mac_ed_scan_ctrl1 */
+} mac_ed_scan_ctrl1_t, *pmac_ed_scan_ctrl1_t;
+
+/**
+  \brief Union type to access mac_ed_scan_dbg (@ 0x00000040).
+*/
+typedef union {
+  __IOM uint32_t w;                           /*!< (@ 0x00000040) ED Scan Status Register for Debugging                      */
+
+  struct {
+    __IM  uint32_t ed_scan_cst : 4;           /*!< [3..0] ED scan current state for debugging.                               */
+          uint32_t            : 28;
+  } b;                                        /*!< bit fields for mac_ed_scan_dbg */
+} mac_ed_scan_dbg_t, *pmac_ed_scan_dbg_t;
+
+/**
+  \brief Union type to access mac_phy_arb_ctrl (@ 0x00000044).
+*/
+typedef union {
+  __IOM uint32_t w;                           /*!< (@ 0x00000044) PHY Arbitration Control Register                           */
+
+  struct {
+    __IOM uint32_t fw_active_entry : 1;       /*!< [0..0] this bit is controlled by FW to indicates whether the
+                                                   MAC FW intend to use PHY and active the meu_zb_fsm HW to
+                                                   issue PHY request: 1: FW intend to use PHY for RX/TX, active
+                                                   the men_zb_fsm to request PHY; 0: FW write 0 to this bit
+                                                   when it no need to use PHY (ex. entering sleep mode), the
+                                                   men_zb_fsm will issue 'term' signal to Arbitration Coordinator.           */
+    __IOM uint32_t zb_only    : 1;            /*!< [1..1] to control whether to disable ZB MAC PHY grant mechanism
+                                                   and MAC assume that it always own the PHY: 0: PHY is shared
+                                                   by multiple protocol (BLE/ZB concurrent); 1: PHY is used
+                                                   by ZB MAC only, no concurrent multiple protocol                           */
+    __IOM uint32_t anchor_point : 18;         /*!< [19..2] the anchor point (in unit of slot, 625us) for PHY grant
+                                                   request.                                                                  */
+    __IOM uint32_t anch_pt_jump_value : 4;    /*!< [23..20] the anchor point jump value (in unit of slot, 625us)
+                                                   for auto PHY request. HW will auto retry the PHY grant
+                                                   request with current BT slot + anch_pt_jump_value                         */
+    __IM  uint32_t zbrf_gnt_deassert_sts : 1; /*!< [24..24] Indicates the status of PHY grant for ZB MAC: 1: MAC
+                                                   lost the PHY grant. This is caused by PHY is granted to
+                                                   BLE or FW set the fw_active_entry to low and HW has sent
+                                                   term signal to Arbitration Coordinator; 0: MAC still own
+                                                   the PHY grant.                                                            */
+    __IM  uint32_t zbrf_gnt_fail_sts : 1;     /*!< [25..25] Indicates the PHY grant request execution result: 1:
+                                                   PHY is not granted at the assigned anchor point(BT Clock);
+                                                   0: PHY grant successfully                                                 */
+    __IM  uint32_t zbrf_gnt_sts : 1;          /*!< [26..26] Indicates the PHY grant status when the grant interrupt
+                                                   is asserted: 1: PHY is granted; 0: PHY is not granted (grant
+                                                   failed or lost PHY grant)                                                 */
+          uint32_t            : 5;
+  } b;                                        /*!< bit fields for mac_phy_arb_ctrl */
+} mac_phy_arb_ctrl_t, *pmac_phy_arb_ctrl_t;
+
+/**
+  \brief Union type to access mac_phy_arb_status (@ 0x00000048).
+*/
+typedef union {
+  __IOM uint32_t w;                           /*!< (@ 0x00000048) PHY Arbitration Status Register                            */
+
+  struct {
+    __IM  uint32_t zbrf_meu_cs : 2;           /*!< [1..0] current state of men_zb_fsm, for debugging                         */
+    __IM  uint32_t zbrf_meu_anchor_point : 18;/*!< [19..2] the current anchor point of meu_zb_fsm requesting PHY
+                                                   grant                                                                     */
+          uint32_t            : 12;
+  } b;                                        /*!< bit fields for mac_phy_arb_status */
+} mac_phy_arb_status_t, *pmac_phy_arb_status_t;
+
+/**
+  \brief Union type to access mac_bt_clk_latch_ctrl (@ 0x0000004C).
+*/
+typedef union {
+  __IOM uint32_t w;                           /*!< (@ 0x0000004C) BT Clock Latch Control Register                            */
+
+  struct {
+    __IM  uint32_t bt_timer_native_h : 5;     /*!< [4..0] latched BT native clock value bits[27:23]                          */
+          uint32_t            : 26;
+    __IOM uint32_t bt_timer_latch : 1;        /*!< [31..31] Write 1 to this bit will trigger the MAC HW to latch
+                                                   BT free run timer(BT native clock and clock counter) value
+                                                   and store them in BT_CLK_LATCH register. HW will auto-clear
+                                                   this bit when BT timer value latch is done.                               */
+  } b;                                        /*!< bit fields for mac_bt_clk_latch_ctrl */
+} mac_bt_clk_latch_ctrl_t, *pmac_bt_clk_latch_ctrl_t;
+
+/**
+  \brief Union type to access mac_bt_clk_latch (@ 0x00000050).
+*/
+typedef union {
+  __IOM uint32_t w;                           /*!< (@ 0x00000050) BT Clock Latch Value                                       */
+
+  struct {
+    __IM  uint32_t bt_timer_cgn : 10;         /*!< [9..0] latched BT clock counter value                                     */
+    __IM  uint32_t bt_timer_native : 22;      /*!< [31..10] latched BT native clock value bits[22:1]                         */
+  } b;                                        /*!< bit fields for mac_bt_clk_latch */
+} mac_bt_clk_latch_t, *pmac_bt_clk_latch_t;
+
+/**
+  \brief Union type to access mac_mac_version (@ 0x00000054).
+*/
+typedef union {
+  __IOM uint32_t w;                           /*!< (@ 0x00000054) MAC HW Version Number                                      */
+
+  struct {
+    __IM  uint32_t version    : 32;           /*!< [31..0] MAC HW version number                                             */
+  } b;                                        /*!< bit fields for mac_mac_version */
+} mac_mac_version_t, *pmac_mac_version_t;
+
+/**
+  \brief Union type to access mac_rssi (@ 0x00000058).
+*/
+typedef union {
+  __IOM uint32_t w;                           /*!< (@ 0x00000058) Base Band RSSI Value Register                              */
+
+  struct {
+    __IM  uint32_t rssi       : 16;           /*!< [15..0] The BB RSSI value                                                 */
+          uint32_t            : 16;
+  } b;                                        /*!< bit fields for mac_rssi */
+} mac_rssi_t, *pmac_rssi_t;
+
+/**
+  \brief Union type to access mac_tx_term_sts (@ 0x0000005C).
+*/
+typedef union {
+  __IOM uint32_t w;                           /*!< (@ 0x0000005C) TX Termed (Lost PHY Grant) Status Register                 */
+
+  struct {
+    __IM  uint32_t zbrf_gts2_tx_termed : 1;   /*!< [0..0] to indicates the GTS2 FIFO TX is finished due to PHY
+                                                   grant is terminated (PHY is granted to BLE)                               */
+    __IM  uint32_t zbrf_gts1_tx_termed : 1;   /*!< [1..1] to indicates the GTS1 FIFO TX is finished due to PHY
+                                                   grant is terminated (PHY is granted to BLE) or due to the
+                                                   header length is 0 for a secure TX                                        */
+    __IM  uint32_t zbrf_normal_tx_termed : 1; /*!< [2..2] to indicates the Normal FIFO TX is finished due to PHY
+                                                   grant is terminated (PHY is granted to BLE) or due to the
+                                                   header length is 0 for a secure TX                                        */
+    __IM  uint32_t zbrf_beacon_tx_termed : 1; /*!< [3..3] to indicates the Beacon FIFO TX is finished due to PHY
+                                                   grant is terminated (PHY is granted to BLE)                               */
+          uint32_t            : 28;
+  } b;                                        /*!< bit fields for mac_tx_term_sts */
+} mac_tx_term_sts_t, *pmac_tx_term_sts_t;
+
+/**
+  \brief Union type to access mac_rfctl (@ 0x00000060).
+*/
+typedef union {
+  __IOM uint32_t w;                           /*!< (@ 0x00000060) RF Mode Control Register                                   */
+
+  struct {
+    __IOM uint32_t rfrxmode   : 1;            /*!< [0..0] Force RX Mode: 0: (default) Normal operation of RX mode;
+                                                   1: RF state machine is forced to RX mode;                                 */
+    __IOM uint32_t rftxmode   : 1;            /*!< [1..1] Force TX Mode: 0: (default) Normal operation of TX mode;
+                                                   1: RF state machine is forced to TX mode;                                 */
+    __IOM uint32_t rfrst      : 1;            /*!< [2..2] RF State Machine Reset: 0: Normal operation of RF state
+                                                   machine; 1: (default) Hold RF state machine in Reset;                     */
+          uint32_t            : 29;
+  } b;                                        /*!< bit fields for mac_rfctl */
+} mac_rfctl_t, *pmac_rfctl_t;
+
+/**
+  \brief Union type to access mac_wakeup_remaincnt (@ 0x00000064).
+*/
+typedef union {
+  __IOM uint32_t w;                           /*!< (@ 0x00000064) Wakeup Remain Counter Register                             */
+
+  struct {
+    __IOM uint32_t remcnt     : 16;           /*!< [15..0] In the system wakeup procedure, the Remain Counter to
+                                                   wait to switch to high speed clock                                        */
+    __IOM uint32_t wakecnt    : 9;            /*!< [24..16] System Clock Recovery Time. The time to wait system
+                                                   resume from sleep.                                                        */
+          uint32_t            : 7;
+  } b;                                        /*!< bit fields for mac_wakeup_remaincnt */
+} mac_wakeup_remaincnt_t, *pmac_wakeup_remaincnt_t;
+
+/**
+  \brief Union type to access mac_wakeup_maincnt (@ 0x00000068).
+*/
+typedef union {
+  __IOM uint32_t w;                           /*!< (@ 0x00000068) Wakeup Main Counter Control Register                       */
+
+  struct {
+    __IOM uint32_t maincnt    : 26;           /*!< [25..0] Main Counter. Main counter is a 26-bit counter for sleep
+                                                   time counting. Units: Sleep Clock Period                                  */
+    __OM  uint32_t startcnt   : 1;            /*!< [26..26] Start Sleep Counters. 1 = Trigger sleep for Non-beacon
+                                                   mode (BO = 0b1111 and Slotted = 0b0). Bit is automatically
+                                                   cleared to '0' by hardware                                                */
+    __IOM uint32_t regwake    : 1;            /*!< [27..27] Register Triggered Wake-up Signal: 1: To wake up MAC.
+                                                   Bit is automatically cleared to '0' by hardware.                          */
+    __IOM uint32_t immwake    : 1;            /*!< [28..28] Immediate Wake-up Mode Enable: 0: (default) Disable
+                                                   Immediate Wake-up mode; 1: Enable Immediate Wake-up mode                  */
+          uint32_t            : 2;
+    __OM  uint32_t slpack     : 1;            /*!< [31..31] Sleep Acknowledgement. Place the MAC to Power Saving
+                                                   Mode. Bit is automatically cleared to '0' by hardware                     */
+  } b;                                        /*!< bit fields for mac_wakeup_maincnt */
+} mac_wakeup_maincnt_t, *pmac_wakeup_maincnt_t;
+
+/**
+  \brief Union type to access mac_wakeup_waketime (@ 0x0000006C).
+*/
+typedef union {
+  __IOM uint32_t w;                           /*!< (@ 0x0000006C) Wakeup Time Match Register                                 */
+
+  struct {
+    __IOM uint32_t waketime   : 11;           /*!< [10..0] Wake Time Match Value: WAKETIME is an 11-bit value.
+                                                   In sleep mode, when the Main Counter is down counting to
+                                                   the value of WAKETIME, the 32 MHz main oscillator will
+                                                   start to be recovered. Note that the value of WAKETIME
+                                                   has to be greater than that of WAKECNT.                                   */
+          uint32_t            : 21;
+  } b;                                        /*!< bit fields for mac_wakeup_waketime */
+} mac_wakeup_waketime_t, *pmac_wakeup_waketime_t;
+
+/**
+  \brief Union type to access mac_dbgport_sel (@ 0x00000090).
+*/
+typedef union {
+  __IOM uint32_t w;                           /*!< (@ 0x00000090) TX/RX Machine Debug Port Selection Control Register        */
+
+  struct {
+    __IOM uint32_t gr_dbg_sel_o : 4;          /*!< [3..0] Debug Port mux sel: 0: zb_rf_debug_out; 1: txm_fc_debug_out;
+                                                   2: rxm_debug_out; 3: src_debug_out; 4: secure; 5: TXM CSMA;
+                                                   6: reserved; 7: short register; 8: txm_gts; 9 ~ 15 : Reserved             */
+    __IOM uint32_t gr_dbg_rxm_sel_o : 1;      /*!< [4..4] Debug Rxm mux sel, 0: dbg_rxm_fifo; 1: dbg_rxm_fsm                 */
+    __IOM uint32_t gr_dbg_cnt_reset_o : 1;    /*!< [5..5] FW can write 1 this bit to reset all debug counter as
+                                                   0. HW will automatically clear this bit.                                  */
+    __IOM uint32_t gr_dbg_src_sel_o : 1;      /*!< [6..6] Debug Src Match filter mux sel: 0: dbg_src_ctrl; 1: dbg_src_entry  */
+          uint32_t            : 25;
+  } b;                                        /*!< bit fields for mac_dbgport_sel */
+} mac_dbgport_sel_t, *pmac_dbgport_sel_t;
+
+/**
+  \brief Union type to access mac_dbg_reg0 (@ 0x00000094).
+*/
+typedef union {
+  __IOM uint32_t w;                           /*!< (@ 0x00000094) Debug Register 0                                           */
+
+  struct {
+          uint32_t            : 8;
+    __IM  uint32_t sh_back    : 8;            /*!< [15..8] the backoff random number of TXM. FW can get pseudo
+                                                   random number from this register for a SW level TX backoff
+                                                   or key generation.                                                        */
+    __IM  uint32_t dbg_rxm_frm_end_cnt : 16;  /*!< [31..16] number of times a Frame end occurs for debugging                 */
+  } b;                                        /*!< bit fields for mac_dbg_reg0 */
+} mac_dbg_reg0_t, *pmac_dbg_reg0_t;
+
+/**
+  \brief Union type to access mac_rxm_dbg (@ 0x00000098).
+*/
+typedef union {
+  __IOM uint32_t w;                           /*!< (@ 0x00000098) RXM Debug Register                                         */
+
+  struct {
+    __IM  uint32_t dbg_crc_ok_cnt : 16;       /*!< [15..0] number of times of received frame with CRC OK occurs
+                                                   for debugging                                                             */
+    __IM  uint32_t dbg_discard_cnt : 16;      /*!< [31..16] number of times of receiving pkt discarded occurs for
+                                                   debugging                                                                 */
+  } b;                                        /*!< bit fields for mac_rxm_dbg */
+} mac_rxm_dbg_t, *pmac_rxm_dbg_t;
+
+/**
+  \brief Union type to access mac_sf_order_ctrl (@ 0x00000300).
+*/
+typedef union {
+  __IOM uint8_t w;                            /*!< (@ 0x00000300) Superframe Order Control Register                          */
+
+  struct {
+    __IOM uint8_t so          : 4;            /*!< [3..0] Superframe Order (macSuperframeOrder), Specifies the
+                                                   length of the active portion of the superframe, including
+                                                   the beacon frame: 0000: 0;  ... 1110: 14; 1111: (default);
+                                                   The superframe will not be active following the beacon.
+                                                   (i.e., no active portion in the superframe)                               */
+    __IOM uint8_t bo          : 4;            /*!< [7..4] Beacon Order (macBeaconOrder), Specifies how often the
+                                                   coordinator will transmit a beacon: 0000: 0;  ... 1110:
+                                                   14; 1111: (default) The coordinator will not transmit a
+                                                   beacon and the Superframe Order (SO)                                      */
+  } b;                                        /*!< bit fields for mac_sf_order_ctrl */
+} mac_sf_order_ctrl_t, *pmac_sf_order_ctrl_t;
+
+/**
+  \brief Union type to access mac_min_lifs (@ 0x00000301).
+*/
+typedef union {
+  __IOM uint8_t w;                            /*!< (@ 0x00000301) Minimum LIFS Configuration Register                        */
+
+  struct {
+    __IOM uint8_t milp        : 6;            /*!< [5..0] aMinLIFSPeriod, 40 symbols, need to take care txpe turn
+                                                   on period (max. 7 symbols). For unslotted CSMA-CA and GTS
+                                                   to guarantee IFS period.                                                  */
+          uint8_t             : 2;
+  } b;                                        /*!< bit fields for mac_min_lifs */
+} mac_min_lifs_t, *pmac_min_lifs_t;
+
+/**
+  \brief Union type to access mac_ifs_ctrl (@ 0x00000302).
+*/
+typedef union {
+  __IOM uint16_t w;                           /*!< (@ 0x00000302) Inter Frame Space Control Register                         */
+
+  struct {
+    __IOM uint16_t misp       : 4;            /*!< [3..0] Minimum Short Interframe Spacing: 0101: (default - Do
+                                                   Not Change)                                                               */
+    __IOM uint16_t txpet      : 4;            /*!< [7..4] VCO Settling Time: 0101: (default - Do Not Change);                */
+    __IOM uint16_t ccachkp    : 4;            /*!< [11..8] The time for CCA check point Ccachkp 0x8 is recommended           */
+    __IOM uint16_t aturn      : 4;            /*!< [15..12] ACK turnaround time after receiving a packet. Minimum
+                                                   value is 0x2. In unit of 16us (a symbol time)                             */
+  } b;                                        /*!< bit fields for mac_ifs_ctrl */
+} mac_ifs_ctrl_t, *pmac_ifs_ctrl_t;
+
+/**
+  \brief Union type to access mac_tx_ctrl (@ 0x00000304).
+*/
+typedef union {
+  __IOM uint32_t w;                           /*!< (@ 0x00000304) TX Control Register                                        */
+
+  struct {
+          uint32_t            : 16;
+    __IOM uint32_t pend       : 1;            /*!< [16..16] Pending bit in ACK header                                        */
+    __IOM uint32_t indirect   : 1;            /*!< [17..17] Activate Indirect Transmission bit (coordinator only):
+                                                   0: (default) Indirect transmission disabled; 1: Indirect
+                                                   transmission enabled                                                      */
+          uint32_t            : 6;
+    __IOM uint32_t mawd       : 7;            /*!< [30..24] The maximum number of symbols to wait for an acknowledgment
+                                                   frame to arrive following a transmitted data frame. This
+                                                   value is dependent on the currently selected logical channel
+                                                   For 0 <= phyCurrentChannel <= 10, this value is equal to
+                                                   120. For 11 <= phyCurrentChannel <= 26, this value is equal
+                                                   to 54.Consider the timing align issue, suggest use 0x39                   */
+          uint32_t            : 1;
+  } b;                                        /*!< bit fields for mac_tx_ctrl */
+} mac_tx_ctrl_t, *pmac_tx_ctrl_t;
+
+/**
+  \brief Union type to access mac_beacon_ctrl (@ 0x00000308).
+*/
+typedef union {
+  __IOM uint32_t w;                           /*!< (@ 0x00000308) Beacon Control Register                                    */
+
+  struct {
+    __IOM uint32_t intl       : 6;            /*!< [5..0] Interval to Start Beacon: The timing interval between
+                                                   slotted mode triggered (set by REG0x300[7:4]) and the first
+                                                   time to send beacon frame: 000000: 0 (default); 000011:
+                                                   3 (optimized - Do Not Change); in unit of symbol time                     */
+          uint32_t            : 10;
+    __IOM uint32_t aoffset    : 8;            /*!< [23..16] Offset to Align Beacon Boundary. Superframe counter
+                                                   offset to align with beacon boundary. Alignment will happen
+                                                   whenever a beacon is received. Only for device mode: 00000000:
+                                                   (default); 00010101: (optimized - Do Not Change) in unit
+                                                   of symbol time                                                            */
+          uint32_t            : 8;
+  } b;                                        /*!< bit fields for mac_beacon_ctrl */
+} mac_beacon_ctrl_t, *pmac_beacon_ctrl_t;
+
+/**
+  \brief Union type to access mac_txm_state (@ 0x0000030C).
+*/
+typedef union {
+  __IOM uint32_t w;                           /*!< (@ 0x0000030C) TX State Machine Status Register                           */
+
+  struct {
+    __IM  uint32_t txm_mac_state : 5;         /*!< [4..0] txm_mac_state: MAC state machine for debug use                     */
+    __IM  uint32_t txm_busn_state : 2;        /*!< [6..5] Normal packet fifo bus state for debug use                         */
+    __IM  uint32_t txm_busb_state : 2;        /*!< [8..7] Beacon fifo bus state for debug use                                */
+    __IM  uint32_t txm_busg1_state : 2;       /*!< [10..9] GTS fifo1 bus state for debug use                                 */
+    __IM  uint32_t txm_busg2_state : 2;       /*!< [12..11] GTS fifo2 bus state for debug use                                */
+    __IM  uint32_t cfp_state  : 3;            /*!< [15..13] GTS state in CFP for debug use                                   */
+    __IM  uint32_t csma_state : 5;            /*!< [20..16] TXM CSMA state for debug use                                     */
+    __IM  uint32_t sf_state   : 3;            /*!< [23..21] superframe structure state for debug use                         */
+    __IM  uint32_t rf_mode_state : 4;         /*!< [27..24] RF mode state for debug use                                      */
+    __IM  uint32_t gts_state  : 4;            /*!< [31..28] GTS state machine for debug use                                  */
+  } b;                                        /*!< bit fields for mac_txm_state */
+} mac_txm_state_t, *pmac_txm_state_t;
+
+/**
+  \brief Union type to access mac_txb_trig (@ 0x00000310).
+*/
+typedef union {
+  __IOM uint8_t w;                            /*!< (@ 0x00000310) Beacon TX FIFO Trigger Control Register                    */
+
+  struct {
+    __IOM uint8_t txbcntrig   : 1;            /*!< [0..0] Transmit Frame in TX Beacon FIFO bit: 1: Transmit the
+                                                   frame in the TX Beacon FIFO; bit is automatically cleared
+                                                   by hardware.                                                              */
+    __IOM uint8_t txbsecen    : 1;            /*!< [1..1] TX Beacon FIFO Security Enabled bit: 0: (default) Security
+                                                   disabled; 1: Security enabled                                             */
+          uint8_t             : 6;
+  } b;                                        /*!< bit fields for mac_txb_trig */
+} mac_txb_trig_t, *pmac_txb_trig_t;
+
+/**
+  \brief Union type to access mac_txn_trig (@ 0x00000311).
+*/
+typedef union {
+  __IOM uint8_t w;                            /*!< (@ 0x00000311) Normal TX FIFO Trigger Control Register                    */
+
+  struct {
+    __IOM uint8_t txntrig     : 1;            /*!< [0..0] Transmit Frame in TX Normal FIFO bit: 1: Transmit the
+                                                   frame in the TX Normal FIFO. Bit is automatically cleared
+                                                   to '0' by hardware.                                                       */
+    __IOM uint8_t txnsecen    : 1;            /*!< [1..1] TX Normal FIFO Security Enabled bit: 0: (default) Security
+                                                   disabled; 1: Security enabled;                                            */
+    __IOM uint8_t txnackreq   : 1;            /*!< [2..2] TX Normal FIFO Acknowledgement Request bit. Transmit
+                                                   a packet with Acknowledgement request. If Acknowledgement
+                                                   is not received, theMAC HW retransmits up to TXNFRMTRY
+                                                   times: 0: (default) No Acknowledgement packet requested;
+                                                   1: Acknowledgement packet requested                                       */
+    __IOM uint8_t ack_type    : 1;            /*!< [3..3] the ACK frame version for the TXM should wait: 0: (default)
+                                                   Imm-Ack; 1: Enh-Ack; The firmware should according to the
+                                                   frame version of the frame is going to be transmitted to
+                                                   fill this bit's value                                                     */
+          uint8_t             : 1;
+    __IOM uint8_t txnfrmtry   : 3;            /*!< [7..5] normal fifo max retry times                                        */
+  } b;                                        /*!< bit fields for mac_txn_trig */
+} mac_txn_trig_t, *pmac_txn_trig_t;
+
+/**
+  \brief Union type to access mac_txg1_trig (@ 0x00000312).
+*/
+typedef union {
+  __IOM uint8_t w;                            /*!< (@ 0x00000312) GTS1 TX FIFO Trigger Control Register                      */
+
+  struct {
+    __IOM uint8_t txg1trig    : 1;            /*!< [0..0] Transmit Frame in TX GTS1 FIFO: 1: Transmit the frame
+                                                   in the TX GTS1 FIFO. Bit is automatically cleared to '0'
+                                                   by hardware                                                               */
+    __IOM uint8_t txg1secen   : 1;            /*!< [1..1] TX GTS1 FIFO Security Enabled: 0: (default) Security
+                                                   disabled; 1: Security enabled                                             */
+    __IOM uint8_t txg1ackreq  : 1;            /*!< [2..2] TX GTS1 FIFO Acknowledgement Request. Transmit a packet
+                                                   with Acknowledgement request. If Acknowledgement is not
+                                                   received, theMAC HW retransmits up to the times set by
+                                                   txg1ifetry(Reg 0x312[7:6]): 0: (default) Acknowledgement
+                                                   Request disabled; 1: Acknowledgement Request enabled                      */
+    __IOM uint8_t txg1slot    : 3;            /*!< [5..3] GTS Slot that GTS1 FIFO Occupies: 000: 0 (default);
+                                                   ... 111: 7                                                                */
+    __IOM uint8_t txg1ifetry  : 2;            /*!< [7..6] GTS1 FIFO Retry Times. Set the limit of retry times of
+                                                   the packet: 00: 0;  ... 11: 3 (default)                                   */
+  } b;                                        /*!< bit fields for mac_txg1_trig */
+} mac_txg1_trig_t, *pmac_txg1_trig_t;
+
+/**
+  \brief Union type to access mac_txg2_trig (@ 0x00000313).
+*/
+typedef union {
+  __IOM uint8_t w;                            /*!< (@ 0x00000313) GTS2 TX FIFO Trigger Control Register                      */
+
+  struct {
+    __IOM uint8_t txg2trig    : 1;            /*!< [0..0] Transmit Frame in TX GTS2 FIFO: 1: Transmit the frame
+                                                   in the TX GTS2 FIFO. Bit is automatically cleared to '0'
+                                                   by hardware                                                               */
+    __IOM uint8_t txg2secen   : 1;            /*!< [1..1] TX GTS2 FIFO Security Enabled: 0: (default) Security
+                                                   disabled; 1: Security enabled;                                            */
+    __IOM uint8_t txg2ackreq  : 1;            /*!< [2..2] TX GTS2 FIFO Acknowledgement Request. Transmit a packet
+                                                   with Acknowledgement request. If Acknowledgement is not
+                                                   received, the MAC HW retransmits up to the times set by
+                                                   txg2ifetry (Reg 0x313[7:6]) 0: (default) Acknowledgement
+                                                   Request disabled; 1: Acknowledgement Request enabled;                     */
+    __IOM uint8_t txg2slot    : 3;            /*!< [5..3] GTS Slot that GTS2 FIFO Occupies: 000: 0 (default);
+                                                   ... 111: 7                                                                */
+    __IOM uint8_t txg2ifetry  : 2;            /*!< [7..6] GTS2 FIFO Retry Times. Set the limit of retry times of
+                                                   the packet: 00: 0;  ... 11: 3 (default)                                   */
+  } b;                                        /*!< bit fields for mac_txg2_trig */
+} mac_txg2_trig_t, *pmac_txg2_trig_t;
+
+/**
+  \brief Union type to access mac_txm_status (@ 0x00000314).
+*/
+typedef union {
+  __IOM uint32_t w;                           /*!< (@ 0x00000314) TX Machine Status Register                                 */
+
+  struct {
+    __IM  uint32_t sfcntr     : 24;           /*!< [23..0] Superframe counter value                                          */
+    __IM  uint32_t txg1retryn : 2;            /*!< [25..24] The number of retry times of the latest successfully
+                                                   transmitted packet on GTS1 FIFO.                                          */
+    __IM  uint32_t txg2retryn : 2;            /*!< [27..26] The number of retry times of the latest successfully
+                                                   transmitted packet on GTS2 FIFO.                                          */
+    __IM  uint32_t pendack    : 1;            /*!< [28..28] Frame Pending Status bit. Status of the frame pending
+                                                   bit in the received Acknowledgement frame: 0: (default)
+                                                   Frame pending bit = 0; 1: Frame pending bit = 1                           */
+          uint32_t            : 3;
+  } b;                                        /*!< bit fields for mac_txm_status */
+} mac_txm_status_t, *pmac_txm_status_t;
+
+/**
+  \brief Union type to access mac_gts_ctrl (@ 0x00000318).
+*/
+typedef union {
+  __IOM uint32_t w;                           /*!< (@ 0x00000318) GTS FIFO TX Control Register                               */
+
+  struct {
+    __IOM uint32_t enh_ack_trig : 1;          /*!< [0..0] Enh-Ack TX trigger. FW set this bit to trigger the Enh-Ack
+                                                   frame which is prepared in the GTS1 TX FIFO. MAC HW will
+                                                   start the Enh-Ack frame transmission at the time of rxif
+                                                   + gts_enh_ack_timer + rx2tx_enh_ack_delay. To prevent the
+                                                   FW set this bit too late or at inproper time, this bit
+                                                   is available to write only in the time window from rxif
+                                                   to (rxif + gts_enh_ack_timer)                                             */
+    __IOM uint32_t sec_enh_ack : 1;           /*!< [1..1] enable the encryption of Enh-Ack frame. The value of
+                                                   this bit will be copied to txg1secen when the Enh-Ack frame
+                                                   (GTS1) TX is triggered.                                                   */
+    __IOM uint32_t gtsswitch  : 1;            /*!< [2..2] Continue TX GTS FIFO Switch: 0: (default) GTS1 and GTS2
+                                                   FIFO will stop toggling with each other if the transmission
+                                                   fails; 1: GTS1 and GTS2 FIFO will toggle with each other                  */
+    __IOM uint32_t nocsmag    : 1;            /*!< [3..3] Carrier Sense Multiple Access with Collision Avoidance
+                                                   (CSMA-CA) for TX GTS FIFO: 0: (default) Enable CSMA-CA
+                                                   for TX GTS FIFO; 1: Disable CSMA-CA for TX GTS FIFO;                      */
+    __IOM uint32_t cap        : 4;            /*!< [7..4] End Slot of Contention Access Period (CAP): 0000: 0 (default);
+                                                   ... 1111: 15                                                              */
+    __IOM uint32_t gts1       : 4;            /*!< [11..8] End Slot of 1st GTS: 0000: 0 (default);  ... 1111: 15             */
+    __IOM uint32_t gts2       : 4;            /*!< [15..12] End Slot of 2nd GTS: 0000: 0 (default);  ... 1111:
+                                                   15;                                                                       */
+    __IOM uint32_t gts3       : 4;            /*!< [19..16] End Slot of 3rd GTS: 0000: 0 (default) ;  ... 1111:
+                                                   15;                                                                       */
+    __IOM uint32_t gts4       : 4;            /*!< [23..20] End Slot of 4th GTS: 0000: 0 (default);  ... 1111:
+                                                   15;                                                                       */
+    __IOM uint32_t gts5       : 4;            /*!< [27..24] End Slot of 5th GTS: 0000: 0 (default);  ... 1111:
+                                                   15;                                                                       */
+    __IOM uint32_t gts6       : 4;            /*!< [31..28] End Slot of 6th GTS: 0000: 0 (default);  ... 1111:
+                                                   15; If 7th GTS exists, the end slot must be 15.                           */
+  } b;                                        /*!< bit fields for mac_gts_ctrl */
+} mac_gts_ctrl_t, *pmac_gts_ctrl_t;
+
+/**
+  \brief Union type to access mac_csma_ctrl (@ 0x0000031C).
+*/
+typedef union {
+  __IOM uint32_t w;                           /*!< (@ 0x0000031C) CSMA Control and Status Register                           */
+
+  struct {
+    __IM  uint32_t csma_cw    : 2;            /*!< [1..0] the contention window length in the CSMA-CA algorithm              */
+    __IM  uint32_t csma_be    : 4;            /*!< [5..2] the backoff exponent in the CSMA-CA algorithm                      */
+    __IM  uint32_t csma_nb    : 4;            /*!< [9..6] the number of times required to backoff in the CSMA-CA
+                                                   algorithm                                                                 */
+    __IM  uint32_t txretry    : 3;            /*!< [12..10] TX Normal FIFO Retry Times. Number of retrys of the
+                                                   most recent TX Normal FIFO transmission: 00: 0 (default);
+                                                   ... 111: 7;                                                               */
+          uint32_t            : 2;
+    __IOM uint32_t nocsman    : 1;            /*!< [15..15] Carrier Sense Multiple Access with Collision Avoidance
+                                                   (CSMA-CA) for TX Normal FIFO: 0: (default) Enable CSMA-CA
+                                                   for TX normal FIFO; 1: Disable CSMA-CA for TX normal FIFO                 */
+    __IOM uint32_t macminbe   : 4;            /*!< [19..16] MAC Minimum Backoff Exponent (macMinBE). The minimum
+                                                   value of the backoff exponent in the CSMA-CA algorithm:
+                                                   0000: Collision avoidance is disabled; 0011: 3 (default)                  */
+    __IOM uint32_t macmaxbe   : 4;            /*!< [23..20] MAC Maximal Backoff Exponent (macMaxBE). The maximal
+                                                   value of the backoff exponent in the CSMA-CA algorithm:
+                                                   0000: Collision avoidance is disabled; 0101: 5 (default)                  */
+    __IOM uint32_t csmabf     : 4;            /*!< [27..24] Maximum CSMA Backoff (macMaxCSMABackoff). The maximum
+                                                   number of backoffs the CSMA-CA algorithm will attempt before
+                                                   declaring a hannel access failure, default value is 4.                    */
+    __IOM uint32_t slotted    : 1;            /*!< [28..28] Slotted CSMA-CA Mode: 0: (default) Disable Slotted
+                                                   CSMA-CA mode; 1: Enable Slotted CSMA-CA mode;                             */
+    __IOM uint32_t batlifeext : 1;            /*!< [29..29] Battery Life Extention Mode: 0: (default) Disable Battery
+                                                   Life Extention Mode; 1: Enable Battery Life Extention Mode                */
+    __IOM uint32_t backoff_nb_gain : 2;       /*!< [31..30] Gain of csma_nb for next backoff periods increas, the
+                                                   new(next) backoff periods is backoff_p + backoff_nb_gain
+                                                   * csma_nb, backoff_p = (random(2^be -1); 00: periods is
+                                                   backoff_p; 01: periods is backoff_p + csma_nb; 10: periods
+                                                   is backoff_p + 2*csma_nb; 11: periods is backoff_p + 3*csma_nb;           */
+  } b;                                        /*!< bit fields for mac_csma_ctrl */
+} mac_csma_ctrl_t, *pmac_csma_ctrl_t;
+
+/**
+  \brief Union type to access mac_tx_settle_ctrl (@ 0x00000320).
+*/
+typedef union {
+  __IOM uint32_t w;                           /*!< (@ 0x00000320) TX Settling Time Control Register                          */
+
+  struct {
+    __IOM uint32_t txont      : 9;            /*!< [8..0] TX Settling Time 0. Transmitter settling time to begin
+                                                   packet transmission. TXONT is a 9-bit value. 0101000: (default
+                                                   - Do Not Change)                                                          */
+    __IOM uint32_t txonts     : 4;            /*!< [12..9] TX Settling Time 1. Transmitter settling time to begin
+                                                   packet transmission:0010: (default); 0101: (optimized -
+                                                   Do Not Change)                                                            */
+          uint32_t            : 3;
+    __IOM uint32_t pacont     : 9;            /*!< [24..16] Power Amplifier Settling Time 0. Power amplifier settling
+                                                   time to begin packet transmission. PACONT is a 9-bit value.
+                                                   00101001: (default - Do Not Change)                                       */
+    __IOM uint32_t paonts     : 4;            /*!< [28..25] Power Amplifier Settling Time 1. Power amplifier settling
+                                                   time to begin packet transmission: 0001: (default); 0100:
+                                                   (optimized - Do Not Change)                                               */
+          uint32_t            : 3;
+  } b;                                        /*!< bit fields for mac_tx_settle_ctrl */
+} mac_tx_settle_ctrl_t, *pmac_tx_settle_ctrl_t;
+
+/**
+  \brief Union type to access mac_tx_frm_len_err (@ 0x00000324).
+*/
+typedef union {
+  __IOM uint32_t w;                           /*!< (@ 0x00000324) TX Frame Length Error Status Register                      */
+
+  struct {
+    __IM  uint32_t txg2lerr   : 1;            /*!< [0..0] Indicates the error of packet in GTSFIFO2 with the frame
+                                                   length is zero for TX or the header length is 0 for encryption            */
+    __IM  uint32_t txg1lerr   : 1;            /*!< [1..1] Indicates the error of packet in GTSFIFO1 with the frame
+                                                   length is zero for TX or the header length is 0 for encryption            */
+    __IM  uint32_t txnlerr    : 1;            /*!< [2..2] Indicates the error of packet in TX Normal FIFO with
+                                                   the frame length is zero for TX or the header length is
+                                                   0 for encryption                                                          */
+    __IM  uint32_t txblerr    : 1;            /*!< [3..3] Indicates the error of packet in Beacon FIFO with the
+                                                   frame length is zero for TX or the header length is 0 for
+                                                   encryption                                                                */
+          uint32_t            : 28;
+  } b;                                        /*!< bit fields for mac_tx_frm_len_err */
+} mac_tx_frm_len_err_t, *pmac_tx_frm_len_err_t;
+
+/**
+  \brief Union type to access mac_txsr (@ 0x00000328).
+*/
+typedef union {
+  __IOM uint32_t w;                           /*!< (@ 0x00000328) TX Status Register                                         */
+
+  struct {
+    __IM  uint32_t txns       : 1;            /*!< [0..0] Normal FIFO Release Status: 0: (default) Succeeded; 1:
+                                                   Fail, retry count exceed or TX is termed (lost PHY grant)                 */
+    __IM  uint32_t txg1s      : 1;            /*!< [1..1] GTS1 FIFO Release Status: 0: (default) Succeeded; 1:
+                                                   Fail, retry count exceed or TX is termed (lost PHY grant)                 */
+    __IM  uint32_t txg2s      : 1;            /*!< [2..2] GTS2 FIFO Release Status: 0: (default) Succeeded; 1:
+                                                   Fail, retry count exceed or TX is termed(lost PHY grant)                  */
+    __IM  uint32_t txg1fnt    : 1;            /*!< [3..3] GTS1 FIFO Transmission Status: 0: (default) Succeeded;
+                                                   1: Fail, no enough time to transmit before the end of a
+                                                   GTS or TX is termed (lost PHY grant)                                      */
+    __IM  uint32_t txg2fnt    : 1;            /*!< [4..4] GTS2 FIFO Transmission Status: 0: (default) Succeeded;
+                                                   1: Fail, no enough time to transmit before the end of a
+                                                   GTS or TX is termed (loat PHY grant)                                      */
+    __IM  uint32_t ccafail    : 1;            /*!< [5..5] Clear Channel Assessment (CCA) Status of Last Transmission:
+                                                   0: (default) Channel Idle; 1: Channel busy                                */
+          uint32_t            : 26;
+  } b;                                        /*!< bit fields for mac_txsr */
+} mac_txsr_t, *pmac_txsr_t;
+
+/**
+  \brief Union type to access mac_tx_time_stamp (@ 0x00000330).
+*/
+typedef union {
+  __IOM uint32_t w;                           /*!< (@ 0x00000330) Frame TX Timestamp Register                                */
+
+  struct {
+    __IM  uint32_t txm_tx_timestmp_clk : 22;  /*!< [21..0] the BT native clock(BT NativeClock[22:1]) of TX timestamp,
+                                                   which is latched at the 1st symbol of the MAC Header (Frame
+                                                   Control) transmitting is started                                          */
+    __IM  uint32_t txm_tx_timestmp_cntr : 10; /*!< [31..22] the BT clock counter of TX timestamp, which is latched
+                                                   at the 1st symbol of the MAC Header (Frame Control) transmitting
+                                                   is started                                                                */
+  } b;                                        /*!< bit fields for mac_tx_time_stamp */
+} mac_tx_time_stamp_t, *pmac_tx_time_stamp_t;
+
+/**
+  \brief Union type to access mac_tx_given_time_set (@ 0x00000334).
+*/
+typedef union {
+  __IOM uint32_t w;                           /*!< (@ 0x00000334) BT Time Comparator for TX Trigger Time Control
+                                                                  Register                                                   */
+
+  struct {
+    __IOM uint32_t txn_nclk   : 18;           /*!< [17..0] The native clock value of the BT-MAC timer comparator
+                                                   for FW to setup the MAC time to trigger the normal TX FIFO
+                                                   transmission. When the (BT NativeClock[18:1] || ClockCounter[9:0])
+                                                   value is matched with (txn_nclk || txn_ckc) then trigger
+                                                   the normal TX FIFO transmission.                                          */
+    __IOM uint32_t txn_ckc    : 10;           /*!< [27..18] The clock counter value of the BT-MAC timer comparator
+                                                   for FW to setup the MAC time to trigger the normal TX FIFO
+                                                   transmission. When the BT-MAC timer value is matched with
+                                                   (txn_nclk || txn_ckc) then trigger the normal TX FIFO transmission.       */
+    __IOM uint32_t schtxnocca : 1;            /*!< [28..28] To indicate whether the MAC TX machine should do CCA
+                                                   to acquire the channel for Schedule TX mode transmissions:
+                                                   0: The MAC TX machine should do CCA for the Scheduled TX
+                                                   mode transmission; 1: The MAC TX machine do NOT do CCA
+                                                   for the Scheduled TX mode transmission. The HW should re-latch
+                                                   this bit on txntmren is set.                                              */
+          uint32_t            : 2;
+    __IOM uint32_t txntmren   : 1;            /*!< [31..31] BT-MAC Timer comparator for normal FIFO TX time enable
+                                                   control: 0: Disable the BT-MAC Timer comparator which will
+                                                   trigger the normal FIFO transmission; 1: Enable the BT-MAC
+                                                   Timer comparator which will trigger the normal FIFO transmission.The
+                                                   FW should fill the normal TX FIFO with the frame to be
+                                                   transmitted, setup the TX Time comparator value and the
+                                                   TX option (with CCA or not) before enable this Timer comparator.The
+                                                   TX machine should clear this bit once the BT-MAC timer
+                                                   value is matched with (txn_                                               */
+  } b;                                        /*!< bit fields for mac_tx_given_time_set */
+} mac_tx_given_time_set_t, *pmac_tx_given_time_set_t;
+
+/**
+  \brief Union type to access mac_tx_given_time_status (@ 0x00000338).
+*/
+typedef union {
+  __IOM uint32_t w;                           /*!< (@ 0x00000338) Given Time TX Status Register                              */
+
+  struct {
+    __IM  uint32_t zbrf_tx_given_time_encoun_tx : 1;/*!< [0..0] to report the TX at given time procedure is conflict
+                                                   with another TX process. 1 means this conflict is happened.               */
+    __IM  uint32_t zbrf_tx_given_time_encoun_rx : 1;/*!< [1..1] to report the TX at given time procedure is conflict
+                                                   with a RX process. 1 means this conflict is happened.                     */
+    __IM  uint32_t zbrf_tx_given_time_obsolete : 1;/*!< [2..2] to report the TX at given time procedure is failed due
+                                                   to the specified TX trigger time is past or it has no enough
+                                                   time to settle PHY.                                                       */
+    __IM  uint32_t zbrf_tx_given_time_not_gnt : 1;/*!< [3..3] to report the TX at given time procedure is failed due
+                                                   to the PHY is not granted at the specified TX trigger time.               */
+    __IM  uint32_t zbrf_tx_given_time_not_in_recv : 1;/*!< [4..4] to report the TX at given time procedure is failed due
+                                                   to the PHY is not ready (in RX state) at the specified
+                                                   TX trigger time. This case normaly is caused by the scheduled
+                                                   TX is triggered when the PHY is re-granted and still in
+                                                   PHY re-initialization.                                                    */
+          uint32_t            : 27;
+  } b;                                        /*!< bit fields for mac_tx_given_time_status */
+} mac_tx_given_time_status_t, *pmac_tx_given_time_status_t;
+
+/**
+  \brief Union type to access mac_gts_slot_cfg (@ 0x0000033C).
+*/
+typedef union {
+  __IOM uint32_t w;                           /*!< (@ 0x0000033C) GTS Slots Configuration Register                           */
+
+  struct {
+    __IOM uint32_t gts_slot_en : 7;           /*!< [6..0] GTS slot enable control, bit 0 ~ 6 correspond to GTS
+                                                   slot 1 ~7: 0: disable the corresponding GTS slot (default)1:
+                                                   enable the corresponding GTS slot                                         */
+          uint32_t            : 1;
+    __IOM uint32_t gts_slot_trx : 7;          /*!< [14..8] GTS slot TX/RX configuration, bit 0 ~ 6 correspond to
+                                                   GTS slot 1 ~7: 0: configure the corresponding GTS slot
+                                                   for RX1: configure the corresponding GTS slot for TX                      */
+          uint32_t            : 17;
+  } b;                                        /*!< bit fields for mac_gts_slot_cfg */
+} mac_gts_slot_cfg_t, *pmac_gts_slot_cfg_t;
+
+/**
+  \brief Union type to access mac_rx_fltr_ctrl (@ 0x00000380).
+*/
+typedef union {
+  __IOM uint32_t w;                           /*!< (@ 0x00000380) RX Filter Control Register                                 */
+
+  struct {
+    __IOM uint32_t promi      : 1;            /*!< [0..0] Accept all packets with CRC OK                                     */
+    __IOM uint32_t errpkt     : 1;            /*!< [1..1] Accept all kinds of pkt(including CRC error)                       */
+    __IOM uint32_t scanmode   : 1;            /*!< [2..2] enable RX Filter scan mode. When scan mode is enabled,
+                                                   only Beacon frame with FCS correct will be accepted by
+                                                   RX filter.                                                                */
+    __IOM uint32_t group_rxmode : 1;          /*!< [3..3] macGroupRxMode Enable. When group RX mode is enabled,
+                                                   frames with EUI-64 group address as its destination address
+                                                   are accepted by RX filter.                                                */
+    __IOM uint32_t implicit_broadcast : 1;    /*!< [4..4] RX Filter macImplicitBroadcast Enable. When implicit
+                                                   broadcast mode is enabled, frames without destination address
+                                                   are accepted by RX filter                                                 */
+    __IOM uint32_t rf_early_term : 1;         /*!< [5..5] Enable the PHY RX early term for RX packet discard:1:
+                                                   enable the PHY RX early term for power saving. The RX will
+                                                   be truned off for the period of RX discarded frame transmission;
+                                                   0: disable the PHY RX early term                                          */
+    __IOM uint32_t frm06_rx_early : 1;        /*!< [6..6] Enable the RX early interrupt for non-secure 2006 frame:
+                                                   0 : RX early interrupt will be asserted for receiving 2006
+                                                   Security Frame or all 2015 Frame excluding ack frame type;
+                                                   1 : RX early interrupt will be asserted for all receiving
+                                                   frame, including 2006 non-secure frame, excluding ack frame
+                                                   type                                                                      */
+          uint32_t            : 1;
+    __IOM uint32_t rxm_force_crc : 1;         /*!< [8..8] Force RXM Received CRC result is error: 0: (default)
+                                                   Force CRC error disabled; 1: Force CRC error enabled For
+                                                   MAC function test purpose                                                 */
+          uint32_t            : 23;
+  } b;                                        /*!< bit fields for mac_rx_fltr_ctrl */
+} mac_rx_fltr_ctrl_t, *pmac_rx_fltr_ctrl_t;
+
+/**
+  \brief Union type to access mac_rxfrmtype (@ 0x00000384).
+*/
+typedef union {
+  __IOM uint32_t w;                           /*!< (@ 0x00000384) RX Frame Type Filter Control Register                      */
+
+  struct {
+    __IOM uint32_t rxftype    : 8;            /*!< [7..0] RX Frame Type Filter. 00001011: (default - Do Not Change)Packet
+                                                   type field in Frame control byte of IEEE802.15.4 is 3 bits,
+                                                   meaning 8 types of packets. Each bit of RXFRM_TYPE correlated
+                                                   to the 8 types. When correlated bit is '1', RXMAC receives
+                                                   the type of packet without filtering out. bit 0 : 000 (beacon);
+                                                   bit 1 : 001 (data); bit 2 : 010 (ack); bit 3 : 011 (command);
+                                                   bit 4 : (reserved)bit 5: 101 (multipurpose): bit 6~7 :
+                                                   (reserved)                                                                */
+    __IOM uint32_t rxftype15  : 8;            /*!< [15..8] RX Frame Type Filter for IEEE802.15.4 version2015. 00001111:
+                                                   (default)Packet type field in Frame control byte of IEEE802.15.4
+                                                   is 3 bits, meaning 8 types of packets. Each bit of RXFRM_TYPE
+                                                   correlated to the 8 types. When correlated bit is '1',
+                                                   RXMAC receives the type of packet without filtering out.
+                                                   bit 0 : 000 (beacon); bit 1 : 001 (data); bit 2 : 010 (ack);
+                                                   bit 3 : 011 (command); bit 4~5 : (reserved); bit 6: 110
+                                                   (Fragement or Frak): bit 7: 111 (Extended):                               */
+          uint32_t            : 16;
+  } b;                                        /*!< bit fields for mac_rxfrmtype */
+} mac_rxfrmtype_t, *pmac_rxfrmtype_t;
+
+/**
+  \brief Union type to access mac_group_eadr_l (@ 0x00000388).
+*/
+typedef union {
+  __IOM uint32_t w;                           /*!< (@ 0x00000388) Group Extended Address Lower Bytes                         */
+
+  struct {
+    __IOM uint32_t group_ext_addr_l : 32;     /*!< [31..0] EUI-64 group address lower bits (bits[31:0])                      */
+  } b;                                        /*!< bit fields for mac_group_eadr_l */
+} mac_group_eadr_l_t, *pmac_group_eadr_l_t;
+
+/**
+  \brief Union type to access mac_group_eadr_h (@ 0x0000038C).
+*/
+typedef union {
+  __IOM uint32_t w;                           /*!< (@ 0x0000038C) Group Extended Address Higher Bytes                        */
+
+  struct {
+    __IOM uint32_t group_ext_addr_h : 32;     /*!< [31..0] EUI-64 group address higher bits (bits[63:32])                    */
+  } b;                                        /*!< bit fields for mac_group_eadr_h */
+} mac_group_eadr_h_t, *pmac_group_eadr_h_t;
+
+/**
+  \brief Union type to access mac_assoc_eadr_l (@ 0x00000390).
+*/
+typedef union {
+  __IOM uint32_t w;                           /*!< (@ 0x00000390) Associated Coordinator Extended Address Lower
+                                                                  Bytes                                                      */
+
+  struct {
+    __IOM uint32_t assoeadr_l : 32;           /*!< [31..0] Lower bits(bits[31:0]) of Associated Coordinator's 64-Bit
+                                                   Extended Address                                                          */
+  } b;                                        /*!< bit fields for mac_assoc_eadr_l */
+} mac_assoc_eadr_l_t, *pmac_assoc_eadr_l_t;
+
+/**
+  \brief Union type to access mac_assoc_eadr_h (@ 0x00000394).
+*/
+typedef union {
+  __IOM uint32_t w;                           /*!< (@ 0x00000394) Associated Coordinator Extended Address Higher
+                                                                  Bytes                                                      */
+
+  struct {
+    __IOM uint32_t assoeadr_h : 32;           /*!< [31..0] Higher bits(bits[63:32]) of Associated Coordinator's
+                                                   64-Bit Extended Address                                                   */
+  } b;                                        /*!< bit fields for mac_assoc_eadr_h */
+} mac_assoc_eadr_h_t, *pmac_assoc_eadr_h_t;
+
+/**
+  \brief Union type to access mac_assoc_sadr (@ 0x00000398).
+*/
+typedef union {
+  __IOM uint32_t w;                           /*!< (@ 0x00000398) Associated Coordinator Short Address Low Byte              */
+
+  struct {
+    __IOM uint32_t assosadr   : 16;           /*!< [15..0] 16-Bits Short Address of Associated Coordinator                   */
+          uint32_t            : 16;
+  } b;                                        /*!< bit fields for mac_assoc_sadr */
+} mac_assoc_sadr_t, *pmac_assoc_sadr_t;
+
+/**
+  \brief Union type to access mac_assoc_bcn_ctrl (@ 0x0000039C).
+*/
+typedef union {
+  __IOM uint32_t w;                           /*!< (@ 0x0000039C) Association Beacon Source Address Control Register         */
+
+  struct {
+    __IOM uint32_t abctrl     : 1;            /*!< [0..0] Associate beacon source address enable. 1: disable; 0:
+                                                   enable                                                                    */
+          uint32_t            : 31;
+  } b;                                        /*!< bit fields for mac_assoc_bcn_ctrl */
+} mac_assoc_bcn_ctrl_t, *pmac_assoc_bcn_ctrl_t;
+
+/**
+  \brief Union type to access mac_rxm_fch (@ 0x000003A0).
+*/
+typedef union {
+  __IOM uint32_t w;                           /*!< (@ 0x000003A0) Received Frame Control Fields Store Register               */
+
+  struct {
+    __IM  uint32_t frame_type : 3;            /*!< [2..0] the frame type of the latest received frame, for debug             */
+    __IM  uint32_t sec_en     : 1;            /*!< [3..3] the security enable bit of the latest received frame,
+                                                   for debug                                                                 */
+    __IM  uint32_t pend       : 1;            /*!< [4..4] the frame pending bit of the latest received frame, for
+                                                   debug                                                                     */
+    __IM  uint32_t ack_req    : 1;            /*!< [5..5] the ACK request bit of the latest received frame, for
+                                                   debug                                                                     */
+    __IM  uint32_t panid_comp : 1;            /*!< [6..6] the PAN ID compressed bit of the latest received frame,
+                                                   for debug                                                                 */
+          uint32_t            : 1;
+    __IM  uint32_t seq_comp   : 1;            /*!< [8..8] the sequence number compressed bit of the latest received
+                                                   frame, for debug                                                          */
+    __IM  uint32_t ie_exist   : 1;            /*!< [9..9] the IE present bit of the latest received frame, for
+                                                   debug                                                                     */
+    __IM  uint32_t dst_adr_mode : 2;          /*!< [11..10] the destination address mode of the latest received
+                                                   frame, for debug00: None; 01: Reserved; 10: 16-bit short
+                                                   address; 11: 64-bit extended address                                      */
+    __IM  uint32_t frm_ver    : 2;            /*!< [13..12] the frame version of the latest received frame, for
+                                                   debug                                                                     */
+    __IM  uint32_t src_adr_mode : 2;          /*!< [15..14] the source address mode of the latest received frame:00:
+                                                   None; 01: Reserved; 10: 16-bit short address; 11: 64-bit
+                                                   extended address                                                          */
+    __IM  uint32_t mp_frame_type : 3;         /*!< [18..16] the frame type of the latest received frame, for debug           */
+    __IM  uint32_t mp_long_frm : 1;           /*!< [19..19] the Long Frame bit of the latest received MP frame,
+                                                   for debug                                                                 */
+    __IM  uint32_t mp_dst_adr_mode : 2;       /*!< [21..20] the destination address mode of the latest received
+                                                   MP frame, for debug00: None; 01: Reserved; 10: 16-bit short
+                                                   address; 11: 64-bit extended address                                      */
+    __IM  uint32_t mp_src_adr_mode : 2;       /*!< [23..22] the source address mode of the latest received MP frame,
+                                                   for debug00: None; 01: Reserved; 10: 16-bit short address;
+                                                   11: 64-bit extended address                                               */
+    __IM  uint32_t mp_panid_exist : 1;        /*!< [24..24] indicates whether the PAN ID is present in received
+                                                   MP frame, for debug                                                       */
+    __IM  uint32_t mp_sec_en  : 1;            /*!< [25..25] the security enable bit of the latest received MP frame,
+                                                   for debug                                                                 */
+    __IM  uint32_t mp_seq_comp : 1;           /*!< [26..26] the Sequence Number Suppression bit of the latest received
+                                                   MP frame, for debug                                                       */
+    __IM  uint32_t mp_frm_pend : 1;           /*!< [27..27] the Frame Pending bit of the latest received MP frame,
+                                                   for debug                                                                 */
+    __IM  uint32_t mp_frm_ver : 2;            /*!< [29..28] the frame version of the latest received MP frame,
+                                                   for debug                                                                 */
+    __IM  uint32_t mp_ack_req : 1;            /*!< [30..30] the ACK request bit of the latest received MP frame,
+                                                   for debug                                                                 */
+    __IM  uint32_t rxm_fchmp_ie_exist : 1;    /*!< [31..31] the IE present bit of the latest received mp frame,
+                                                   for debug                                                                 */
+  } b;                                        /*!< bit fields for mac_rxm_fch */
+} mac_rxm_fch_t, *pmac_rxm_fch_t;
+
+/**
+  \brief Union type to access mac_rx_sn_ie_update (@ 0x000003A4).
+*/
+typedef union {
+  __IOM uint32_t w;                           /*!< (@ 0x000003A4) Received Frame's Sequence Number and IE Updated
+                                                                  Status                                                     */
+
+  struct {
+    __IM  uint32_t seq_num    : 8;            /*!< [7..0] the sequence number of the latest received frame, for
+                                                   debug                                                                     */
+    __IM  uint32_t hdr_ie_term : 1;           /*!< [8..8] MAC HW set this bit to indicated the Header IEs parsing
+                                                   is finished (Header Termination IE is detected).                          */
+    __IM  uint32_t csl_update : 1;            /*!< [9..9] CSL IE Parser have been update in the transaction which
+                                                   will be set to 1. Auto Clear when next Rx reception starts                */
+    __IM  uint32_t tc_update  : 1;            /*!< [10..10] Time Correction IE have been update in the transaction
+                                                   which will be set to 1. Auto Clear when next Rx reception
+                                                   starts.                                                                   */
+          uint32_t            : 21;
+  } b;                                        /*!< bit fields for mac_rx_sn_ie_update */
+} mac_rx_sn_ie_update_t, *pmac_rx_sn_ie_update_t;
+
+/**
+  \brief Union type to access mac_rx_csl_ie (@ 0x000003A8).
+*/
+typedef union {
+  __IOM uint32_t w;                           /*!< (@ 0x000003A8) CSL IE In Received Frame                                   */
+
+  struct {
+    __IM  uint32_t csl_period : 16;           /*!< [15..0] the CSL period of the CSL IE in received frame                    */
+    __IM  uint32_t csl_phase  : 16;           /*!< [31..16] the CSL phase of the CSL IE in received frame                    */
+  } b;                                        /*!< bit fields for mac_rx_csl_ie */
+} mac_rx_csl_ie_t, *pmac_rx_csl_ie_t;
+
+/**
+  \brief Union type to access mac_rx_tmcor_ie (@ 0x000003AC).
+*/
+typedef union {
+  __IOM uint32_t w;                           /*!< (@ 0x000003AC) Time Correction IE In Received Frame                       */
+
+  struct {
+    __IM  uint32_t tm_sync_info : 16;         /*!< [15..0] the Time Sync Info of the Time Correction IE in received
+                                                   frame                                                                     */
+          uint32_t            : 16;
+  } b;                                        /*!< bit fields for mac_rx_tmcor_ie */
+} mac_rx_tmcor_ie_t, *pmac_rx_tmcor_ie_t;
+
+/**
+  \brief Union type to access mac_rx_aux_sec_hdr (@ 0x000003B0).
+*/
+typedef union {
+  __IOM uint32_t w;                           /*!< (@ 0x000003B0) RX Security Aux Header Information Register                */
+
+  struct {
+    __IM  uint32_t rxm_sec_level : 3;         /*!< [2..0] 'the Security Level field of the received Aux security
+                                                   header. Value of this field indicates the security level
+                                                   (method) of the received secured frame: 0: none; 1: MIC-32;
+                                                   2: MIC-64; 3: MIC-128; 4: AES; 5: AES-MIC-32; 6: AES-MIC-64;
+                                                   7: AES-MIC-128;                                                           */
+    __IM  uint32_t rxm_keyid_mode : 2;        /*!< [4..3] 'the Key Indetifier Mode field of the received Aux security
+                                                   header. Value of this field indicates how many of bis of
+                                                   rxm_keyid is valid.                                                       */
+    __IM  uint32_t rxm_sec_frm_cnt_comp : 1;  /*!< [5..5] the Frame Counter Suppression bit of the Security Control
+                                                   field in the Aux Security header of the latest received
+                                                   frame                                                                     */
+    __IM  uint32_t rxm_sec_asn_nonce : 1;     /*!< [6..6] the 'ASN in Nonce' bit of the Security Control field
+                                                   in the Aux Security header of the latest received frame                   */
+          uint32_t            : 1;
+    __IM  uint32_t rxm_key_index : 8;         /*!< [15..8] the key index of the key identifier in the Aux security
+                                                   header of received incoming frame. This field is valid
+                                                   only when the rxm_keyid_mode != 0                                         */
+          uint32_t            : 16;
+  } b;                                        /*!< bit fields for mac_rx_aux_sec_hdr */
+} mac_rx_aux_sec_hdr_t, *pmac_rx_aux_sec_hdr_t;
+
+/**
+  \brief Union type to access mac_rx_aux_frmcnt (@ 0x000003B4).
+*/
+typedef union {
+  __IOM uint32_t w;                           /*!< (@ 0x000003B4) RX Security Aux Header Frame Counter Information
+                                                                  Register                                                   */
+
+  struct {
+    __IM  uint32_t rxm_sec_frm_cnt : 32;      /*!< [31..0] the frame counter field in the Aux security header of
+                                                   the latest received security frame                                        */
+  } b;                                        /*!< bit fields for mac_rx_aux_frmcnt */
+} mac_rx_aux_frmcnt_t, *pmac_rx_aux_frmcnt_t;
+
+/**
+  \brief Union type to access mac_rx_aux_key_src_l (@ 0x000003B8).
+*/
+typedef union {
+  __IOM uint32_t w;                           /*!< (@ 0x000003B8) RX Security Aux Key Source Lower Bytes Register            */
+
+  struct {
+    __IM  uint32_t rxm_key_src_l : 32;        /*!< [31..0] the bits [31:0] of the Key source field of the received
+                                                   Aux security header. The number of valid bits of the Key
+                                                   source is depends on the Key Identifier Mode: 0: key identifier
+                                                   size is 0, ignore the value of rxm_key_index and rxm_key_src;
+                                                   1: key identifier size is 1 byte, only rxm_key_index is
+                                                   valid; 2: key identifier size is 5 bytes, only rxm_key_indx
+                                                   and rxm_key_src[31:0] are valid; 3: key identifier size
+                                                   is 9 bytes, the rxm_key_indx and whole rxm_key_src are
+                                                   valid;                                                                    */
+  } b;                                        /*!< bit fields for mac_rx_aux_key_src_l */
+} mac_rx_aux_key_src_l_t, *pmac_rx_aux_key_src_l_t;
+
+/**
+  \brief Union type to access mac_rx_aux_key_src_h (@ 0x000003BC).
+*/
+typedef union {
+  __IOM uint32_t w;                           /*!< (@ 0x000003BC) RX Security Aux Key Source Higher Bytes Register           */
+
+  struct {
+    __IM  uint32_t rxm_key_src_h : 32;        /*!< [31..0] the bits [63:32] of the Key source field of the received
+                                                   Aux security header. The number of valid bits of the Key
+                                                   source is depends on the Key Identifier Mode: 0: key identifier
+                                                   size is 0, ignore the value of rxm_key_index and rxm_key_src;
+                                                   1: key identifier size is 1 byte, only rxm_key_index is
+                                                   valid; 2: key identifier size is 5 bytes, only rxm_key_indx
+                                                   and rxm_key_src[31:0] are valid; 3: key identifier size
+                                                   is 9 bytes, the rxm_key_indx and whole rxm_key_src are
+                                                   valid;                                                                    */
+  } b;                                        /*!< bit fields for mac_rx_aux_key_src_h */
+} mac_rx_aux_key_src_h_t, *pmac_rx_aux_key_src_h_t;
+
+/**
+  \brief Union type to access mac_rx_fifo_ctrl (@ 0x000003C0).
+*/
+typedef union {
+  __IOM uint32_t w;                           /*!< (@ 0x000003C0) RX FIFO Control Register                                   */
+
+  struct {
+    __IOM uint32_t rxfifo2    : 1;            /*!< [0..0] RX Ping-pong FIFO Enable: 0: (default) Disable; 1: Enable          */
+          uint32_t            : 1;
+    __IOM uint32_t rxffwr     : 1;            /*!< [2..2] enable FW to access RX FIFO: 1: RX FIFO is owned by FW
+                                                   and FW can read/wrire RX FIFO; 0: RX FIFO is owned by MAC
+                                                   HW, FW cannot access RX FIFO                                              */
+          uint32_t            : 5;
+    __IOM uint32_t rxflush    : 1;            /*!< [8..8] Flush the RX FIFO: 1: Flush RX FIFO. RX FIFO data is
+                                                   not modified. If Ping-pong FIFO is enabled (rxfifo2 = 1),
+                                                   both FIFOs are flushed at the same time. Bit is automatically
+                                                   cleared to '0' by hardware                                                */
+          uint32_t            : 23;
+  } b;                                        /*!< bit fields for mac_rx_fifo_ctrl */
+} mac_rx_fifo_ctrl_t, *pmac_rx_fifo_ctrl_t;
+
+/**
+  \brief Union type to access mac_rx_early_fw_sts (@ 0x000003C4).
+*/
+typedef union {
+  __IOM uint32_t w;                           /*!< (@ 0x000003C4) RX early interrupt FW process status                       */
+
+  struct {
+    __IOM uint32_t rx_early_sts : 8;          /*!< [7..0] for FW to store the RX early interrupt process status
+                                                   to assist the incoming frame receiving pre-processing.
+                                                   MAC HW will clear this field on every start of a new incoming
+                                                   frame receiving.                                                          */
+          uint32_t            : 24;
+  } b;                                        /*!< bit fields for mac_rx_early_fw_sts */
+} mac_rx_early_fw_sts_t, *pmac_rx_early_fw_sts_t;
+
+/**
+  \brief Union type to access mac_bt_clk_sel (@ 0x000003C8).
+*/
+typedef union {
+  __IOM uint32_t w;                           /*!< (@ 0x000003C8) RX Timestamp Timer Selection Control Register              */
+
+  struct {
+    __IOM uint32_t rx_tim_sel : 1;            /*!< [0..0] Controls the RX machine to select the time for RX timestamp
+                                                   latching: 0 : Used 16 bits MAC down count timer; 1 : Used
+                                                   10 bits BT clock counter and BT Native clock[22:1] value                  */
+          uint32_t            : 31;
+  } b;                                        /*!< bit fields for mac_bt_clk_sel */
+} mac_bt_clk_sel_t, *pmac_bt_clk_sel_t;
+
+/**
+  \brief Union type to access mac_rxm_sts (@ 0x000003CC).
+*/
+typedef union {
+  __IOM uint32_t w;                           /*!< (@ 0x000003CC) RX Machine Status Register                                 */
+
+  struct {
+    __IOM uint32_t pidconflict : 1;           /*!< [0..0] PAN ID conflict. Write '1' to clear                                */
+    __IM  uint32_t rxm_hdr_rdy : 1;           /*!< [1..1] RX Header ready, this bit is set to indicates the MAC
+                                                   header (includes Security Aux. header if present) of the
+                                                   incoming frame is received. It is cleared automatically
+                                                   when a new frame receiving is started.                                    */
+    __IM  uint32_t sec_dec_err : 1;           /*!< [2..2] Security MIC check Error (incorrect): 0: (default) Security
+                                                   decryption and MIC is correct; 1: Security decryption done
+                                                   and MIC is inclrrect this bit is set when use the Security
+                                                   engine to do the RX FIFO secure frame decryption and the
+                                                   result of MIC check is error                                              */
+    __IM  uint32_t rxm_crc_err : 1;           /*!< [3..3] RX CRC Error: 0: (default) RX CRC correct; 1: RX CRC
+                                                   error this bit is set when an incoming frame receiving
+                                                   is finished and the FCS check result is error                             */
+    __IM  uint32_t rxfifo_overflow : 1;       /*!< [4..4] RX FIFO Overflow: 0: (default) Not overflow; 1: Overflow
+                                                   RX FIFO overflow is occurred when RX FIFO is full and a
+                                                   new incoming frame is attempts to be stored into RX FIFO.                 */
+    __IM  uint32_t sec_dec_ignored : 1;       /*!< [5..5] rx decryption is ignored for the latest received secure
+                                                   frame, this bit is valid only when the ping-pong FIFO mode
+                                                   is enabled0 : RX decryption is not ignored (start decryption
+                                                   is triggered)1 : RX decryption is ignored                                 */
+          uint32_t            : 1;
+    __IM  uint32_t rxfifo_full : 1;           /*!< [7..7] RX FIFO Full: 0: (default) RX FIFO available for data
+                                                   receiving; 1: RX FIFO not available for data receiving
+                                                   for single RX FIFO operation mode, RX FIFO full is occurred
+                                                   when a received frame is stored into RX FIFO. RX FIFO full
+                                                   status is cleared once the FW read frame data from the
+                                                   RX FIFO. for ping-pong RX FIFO operation mode. RX FIFO
+                                                   full is occurred when 2 received frames are stored into
+                                                   RX FIFO seprately and FW cannot read RX FIFO in time. the
+                                                   RX FIFO full status is cleared once FW read one fr                        */
+    __IM  uint32_t rdff1      : 1;            /*!< [8..8] RX FIFO read selection flag for RX FIFO Reading: 0: (default)
+                                                   Read data from RX FIFO 0; 1: Read data from RX FIFO 1 if
+                                                   the RX FIFO operation mode is single RX FIFO, this flag
+                                                   always is 0; if the RX FIFO operation mode is ping-pong
+                                                   RX FIFO, this flag will toggle for every RX FIFO read.                    */
+    __IM  uint32_t wrff1      : 1;            /*!< [9..9] RX FIFO write selection flag for PHY to select the RX
+                                                   FIFO to store received frame: 0: write data to RX FIFO
+                                                   0; 1: write data to RX FIFO 1 if the RX FIFO operation
+                                                   mode is single RX FIFO, this flag always is 0; if the RX
+                                                   FIFO operation mode is ping-pong RX FIFO, this flag will
+                                                   toggle for every RX FIFO write.                                           */
+          uint32_t            : 15;
+    __IM  uint32_t last_rxm_hdr_rdy : 1;      /*!< [25..25] the latched value of rxm_hdr_rdy bit. It keep update
+                                                   the latched value during RXM state is busy and hold the
+                                                   latest latched value when RXM state is idle                               */
+          uint32_t            : 1;
+    __IM  uint32_t last_rxm_crc_err : 1;      /*!< [27..27] the latched value of rxm_crc_err bit. It keep update
+                                                   the latched value during RXM state is busy and hold the
+                                                   latest latched value when RXM state is idle                               */
+    __IM  uint32_t last_rxfifo_overflow : 1;  /*!< [28..28] the latched value of rxfifo_overflow bit. It keep update
+                                                   the latched value during RXM state is busy and hold the
+                                                   latest latched value when RXM state is idle                               */
+          uint32_t            : 1;
+    __IM  uint32_t lwrff1     : 1;            /*!< [30..30] the latched value of wrff1 bit. It keep update the
+                                                   latched value during RXM state is busy and hold the latest
+                                                   latched value when RXM state is idle                                      */
+    __IM  uint32_t last_rxfifo_full : 1;      /*!< [31..31] the latched value of rxfifo_full bit. It keep update
+                                                   the latched value during RXM state is busy and hold the
+                                                   latest latched value when RXM state is idle                               */
+  } b;                                        /*!< bit fields for mac_rxm_sts */
+} mac_rxm_sts_t, *pmac_rxm_sts_t;
+
+/**
+  \brief Union type to access mac_rx_src_addr_l (@ 0x000003D0).
+*/
+typedef union {
+  __IOM uint32_t w;                           /*!< (@ 0x000003D0) RX Source Address Lower Bytes Register                     */
+
+  struct {
+    __IM  uint32_t srcadr_l   : 32;           /*!< [31..0] Received Packet Source Address lower bits [31:0]                  */
+  } b;                                        /*!< bit fields for mac_rx_src_addr_l */
+} mac_rx_src_addr_l_t, *pmac_rx_src_addr_l_t;
+
+/**
+  \brief Union type to access mac_rx_src_addr_h (@ 0x000003D4).
+*/
+typedef union {
+  __IOM uint32_t w;                           /*!< (@ 0x000003D4) RX Source Address Higher Bytes Register                    */
+
+  struct {
+    __IM  uint32_t srcadr_h   : 32;           /*!< [31..0] Received Packet Source Address higher bits [63:32]                */
+  } b;                                        /*!< bit fields for mac_rx_src_addr_h */
+} mac_rx_src_addr_h_t, *pmac_rx_src_addr_h_t;
+
+/**
+  \brief Union type to access mac_rxmbcnt_fsm (@ 0x000003D8).
+*/
+typedef union {
+  __IOM uint32_t w;                           /*!< (@ 0x000003D8) RX Machine Received Byte Count and RXM State
+                                                                  Register                                                   */
+
+  struct {
+    __IM  uint32_t rxmbytecnt : 8;            /*!< [7..0] RXM receiving byte counter, used to make sure 'superframe
+                                                   specification' of beacon frame is in RXFIFO. It is for
+                                                   decryption of beacon frame                                                */
+    __IOM uint32_t frm_cs     : 6;            /*!< [13..8] RXM frame current state                                           */
+          uint32_t            : 2;
+    __IM  uint32_t frm_ack_cs : 3;            /*!< [18..16] RXM ACK frame current state, for debug                           */
+          uint32_t            : 13;
+  } b;                                        /*!< bit fields for mac_rxmbcnt_fsm */
+} mac_rxmbcnt_fsm_t, *pmac_rxmbcnt_fsm_t;
+
+/**
+  \brief Union type to access mac_src_addr_filter_ctrl (@ 0x00000400).
+*/
+typedef union {
+  __IOM uint32_t w;                           /*!< (@ 0x00000400) Source Address Match Filter Control Register               */
+
+  struct {
+    __IOM uint32_t enh_frmpend_en : 1;        /*!< [0..0] enable the enhanced frame pending mechanism (defined
+                                                   by Thread 1.2 Spec.) of auto frame pending bit fill in
+                                                   the Frame Control of Imm-Ack. 0: enhanced frame pending
+                                                   is disabled. The source address match filter HW will set
+                                                   the Frame Pending bit of a Imm-Ack frame which response
+                                                   to a Data Request command frame. 1: enhanced frame pending
+                                                   is enabled. The source address match filter HW will set
+                                                   the Frame Pending bit of Imm-Ack frames those response
+                                                   to Data frames or Command frames.                                         */
+    __IOM uint32_t pending_ack : 1;           /*!< [1..1] the pending bit value of Imm-Ack to response to an incoming
+                                                   MAC frame other than Data Request command and its source
+                                                   address does not match to any Source Address Match Filter
+                                                   entry.                                                                    */
+    __IOM uint32_t datreq_cmd_pending_ack : 1;/*!< [2..2] the pending bit value of Imm-Ack to response to a Data
+                                                   Request command frame and its source address do not match
+                                                   to any Source Address Match Filter entry.                                 */
+          uint32_t            : 29;
+  } b;                                        /*!< bit fields for mac_src_addr_filter_ctrl */
+} mac_src_addr_filter_ctrl_t, *pmac_src_addr_filter_ctrl_t;
+
+/**
+  \brief Union type to access mac_src_ext_match_entry_en (@ 0x00000404).
+*/
+typedef union {
+  __IOM uint32_t w;                           /*!< (@ 0x00000404) Extended Address Entries of Source Address Match
+                                                                  Filter Enable Control Register                             */
+
+  struct {
+    __IOM uint32_t ext_entry_en : 16;         /*!< [15..0] enable control of each extended address entry of source
+                                                   address match filter. Bit 0 ~ bit 15 control entry 0 ~
+                                                   entry15 corresponding.                                                    */
+          uint32_t            : 16;
+  } b;                                        /*!< bit fields for mac_src_ext_match_entry_en */
+} mac_src_ext_match_entry_en_t, *pmac_src_ext_match_entry_en_t;
+
+/**
+  \brief Union type to access mac_src_short_match_entry_en (@ 0x00000408).
+*/
+typedef union {
+  __IOM uint32_t w;                           /*!< (@ 0x00000408) Short Address Entries of Source Address Match
+                                                                  Filter Enable Control Register                             */
+
+  struct {
+    __IOM uint32_t ext_entry_en : 32;         /*!< [31..0] enable control of each short address entry of source
+                                                   address match filter. Bit 0 ~ bit 31 control entry 0 ~
+                                                   entry31 corresponding.                                                    */
+  } b;                                        /*!< bit fields for mac_src_short_match_entry_en */
+} mac_src_short_match_entry_en_t, *pmac_src_short_match_entry_en_t;
+
+/**
+  \brief Union type to access mac_src_addr_match_sts (@ 0x0000040C).
+*/
+typedef union {
+  __IOM uint32_t w;                           /*!< (@ 0x0000040C) Source Address Match Filter Status Register                */
+
+  struct {
+    __IOM uint32_t src_match_entry_id : 5;    /*!< [4..0] Indicates the entry index of Source Address Match Filter
+                                                   of the latest matched result.                                             */
+    __IOM uint32_t src_match_entry_type : 1;  /*!< [5..5] Indicates the entry type of Source Address Match Filter
+                                                   of the latest matched result. 0: match to a short address
+                                                   entry; 1: match to a extended address entry;                              */
+    __IOM uint32_t src_match_status_update : 1;/*!< [6..6] indicates the source address of an incoming RX frame
+                                                   is matched with one of entry of source address filter.
+                                                   FW write 1 to clear.                                                      */
+          uint32_t            : 25;
+  } b;                                        /*!< bit fields for mac_src_addr_match_sts */
+} mac_src_addr_match_sts_t, *pmac_src_addr_match_sts_t;
+
+/**
+  \brief Union type to access mac_src_short_match0 (@ 0x00000410).
+*/
+typedef union {
+  __IOM uint32_t w;                         /*!< (@ 0x00000410) Short Source Address Match Filter Entry 0                  */
+
+  struct {
+    __IOM uint32_t addr     : 16;           /*!< [15..0] the short address of short address match entry 0                  */
+    __IOM uint32_t panid    : 16;           /*!< [31..16] the PAN ID of short address match entry 0                        */
+  } b;                                        /*!< bit fields for mac_src_short_match0 */
+} mac_src_short_match0_t, *pmac_src_short_match0_t;
+
+/**
+  \brief Union type to access mac_src_ext_match0_l (@ 0x00000410).
+*/
+typedef union {
+  __IOM uint32_t w;                         /*!< (@ 0x00000410) Lower 4-bytes of Extended Source Address Match
+                                                                Filter Entry 0                                             */
+
+  struct {
+    __IOM uint32_t ext_addr_l : 32;         /*!< [31..0] the lower 4-bytes of extended address of extended address
+                                                 match entry 0                                                             */
+  } b;                                        /*!< bit fields for mac_src_ext_match0_l */
+} mac_src_ext_match0_l_t, *pmac_src_ext_match0_l_t;
+
+/**
+  \brief Union type to access mac_src_short_match1 (@ 0x00000414).
+*/
+typedef union {
+  __IOM uint32_t w;                         /*!< (@ 0x00000414) Short Source Address Match Filter Entry 1                  */
+
+  struct {
+    __IOM uint32_t addr     : 16;           /*!< [15..0] the short address of short address match entry 1                  */
+    __IOM uint32_t panid    : 16;           /*!< [31..16] the PAN ID of short address match entry 1                        */
+  } b;                                        /*!< bit fields for mac_src_short_match1 */
+} mac_src_short_match1_t, *pmac_src_short_match1_t;
+
+/**
+  \brief Union type to access mac_src_ext_match0_h (@ 0x00000414).
+*/
+typedef union {
+  __IOM uint32_t w;                         /*!< (@ 0x00000414) Higher 4-bytes of Extended Source Address Match
+                                                                Filter Entry 0                                             */
+
+  struct {
+    __IOM uint32_t ext_addr_h : 32;         /*!< [31..0] the higher 4-bytes of extended address of extended address
+                                                 match entry 0                                                             */
+  } b;                                        /*!< bit fields for mac_src_ext_match0_h */
+} mac_src_ext_match0_h_t, *pmac_src_ext_match0_h_t;
+
+/**
+  \brief Union type to access mac_src_short_match2 (@ 0x00000418).
+*/
+typedef union {
+  __IOM uint32_t w;                         /*!< (@ 0x00000418) Short Source Address Match Filter Entry 2                  */
+
+  struct {
+    __IOM uint32_t addr     : 16;           /*!< [15..0] the short address of short address match entry 2                  */
+    __IOM uint32_t panid    : 16;           /*!< [31..16] the PAN ID of short address match entry 2                        */
+  } b;                                        /*!< bit fields for mac_src_short_match2 */
+} mac_src_short_match2_t, *pmac_src_short_match2_t;
+
+/**
+  \brief Union type to access mac_src_ext_match1_l (@ 0x00000418).
+*/
+typedef union {
+  __IOM uint32_t w;                         /*!< (@ 0x00000418) Lower 4-bytes of Extended Source Address Match
+                                                                Filter Entry 1                                             */
+
+  struct {
+    __IOM uint32_t ext_addr_l : 32;         /*!< [31..0] the lower 4-bytes of extended address of extended address
+                                                 match entry 1                                                             */
+  } b;                                        /*!< bit fields for mac_src_ext_match1_l */
+} mac_src_ext_match1_l_t, *pmac_src_ext_match1_l_t;
+
+/**
+  \brief Union type to access mac_src_short_match3 (@ 0x0000041C).
+*/
+typedef union {
+  __IOM uint32_t w;                         /*!< (@ 0x0000041C) Short Source Address Match Filter Entry 3                  */
+
+  struct {
+    __IOM uint32_t addr     : 16;           /*!< [15..0] the short address of short address match entry 3                  */
+    __IOM uint32_t panid    : 16;           /*!< [31..16] the PAN ID of short address match entry 3                        */
+  } b;                                        /*!< bit fields for mac_src_short_match3 */
+} mac_src_short_match3_t, *pmac_src_short_match3_t;
+
+/**
+  \brief Union type to access mac_src_ext_match1_h (@ 0x0000041C).
+*/
+typedef union {
+  __IOM uint32_t w;                         /*!< (@ 0x0000041C) Higher 4-bytes of Extended Source Address Match
+                                                                Filter Entry 1                                             */
+
+  struct {
+    __IOM uint32_t ext_addr_h : 32;         /*!< [31..0] the higher 4-bytes of extended address of extended address
+                                                 match entry 1                                                             */
+  } b;                                        /*!< bit fields for mac_src_ext_match1_h */
+} mac_src_ext_match1_h_t, *pmac_src_ext_match1_h_t;
+
+/**
+  \brief Union type to access mac_src_short_match4 (@ 0x00000420).
+*/
+typedef union {
+  __IOM uint32_t w;                         /*!< (@ 0x00000420) Short Source Address Match Filter Entry 4                  */
+
+  struct {
+    __IOM uint32_t addr     : 16;           /*!< [15..0] the short address of short address match entry 4                  */
+    __IOM uint32_t panid    : 16;           /*!< [31..16] the PAN ID of short address match entry 4                        */
+  } b;                                        /*!< bit fields for mac_src_short_match4 */
+} mac_src_short_match4_t, *pmac_src_short_match4_t;
+
+/**
+  \brief Union type to access mac_src_ext_match2_l (@ 0x00000420).
+*/
+typedef union {
+  __IOM uint32_t w;                         /*!< (@ 0x00000420) Lower 4-bytes of Extended Source Address Match
+                                                                Filter Entry 2                                             */
+
+  struct {
+    __IOM uint32_t ext_addr_l : 32;         /*!< [31..0] the lower 4-bytes of extended address of extended address
+                                                 match entry 2                                                             */
+  } b;                                        /*!< bit fields for mac_src_ext_match2_l */
+} mac_src_ext_match2_l_t, *pmac_src_ext_match2_l_t;
+
+/**
+  \brief Union type to access mac_src_short_match5 (@ 0x00000424).
+*/
+typedef union {
+  __IOM uint32_t w;                         /*!< (@ 0x00000424) Short Source Address Match Filter Entry 5                  */
+
+  struct {
+    __IOM uint32_t addr     : 16;           /*!< [15..0] the short address of short address match entry 5                  */
+    __IOM uint32_t panid    : 16;           /*!< [31..16] the PAN ID of short address match entry 5                        */
+  } b;                                        /*!< bit fields for mac_src_short_match5 */
+} mac_src_short_match5_t, *pmac_src_short_match5_t;
+
+/**
+  \brief Union type to access mac_src_ext_match2_h (@ 0x00000424).
+*/
+typedef union {
+  __IOM uint32_t w;                         /*!< (@ 0x00000424) Higher 4-bytes of Extended Source Address Match
+                                                                Filter Entry 2                                             */
+
+  struct {
+    __IOM uint32_t ext_addr_h : 32;         /*!< [31..0] the higher 4-bytes of extended address of extended address
+                                                 match entry 2                                                             */
+  } b;                                        /*!< bit fields for mac_src_ext_match2_h */
+} mac_src_ext_match2_h_t, *pmac_src_ext_match2_h_t;
+
+/**
+  \brief Union type to access mac_src_short_match6 (@ 0x00000428).
+*/
+typedef union {
+  __IOM uint32_t w;                         /*!< (@ 0x00000428) Short Source Address Match Filter Entry 6                  */
+
+  struct {
+    __IOM uint32_t addr     : 16;           /*!< [15..0] the short address of short address match entry 6                  */
+    __IOM uint32_t panid    : 16;           /*!< [31..16] the PAN ID of short address match entry 6                        */
+  } b;                                        /*!< bit fields for mac_src_short_match6 */
+} mac_src_short_match6_t, *pmac_src_short_match6_t;
+
+/**
+  \brief Union type to access mac_src_ext_match3_l (@ 0x00000428).
+*/
+typedef union {
+  __IOM uint32_t w;                         /*!< (@ 0x00000428) Lower 4-bytes of Extended Source Address Match
+                                                                Filter Entry 3                                             */
+
+  struct {
+    __IOM uint32_t ext_addr_l : 32;         /*!< [31..0] the lower 4-bytes of extended address of extended address
+                                                 match entry 3                                                             */
+  } b;                                        /*!< bit fields for mac_src_ext_match3_l */
+} mac_src_ext_match3_l_t, *pmac_src_ext_match3_l_t;
+
+/**
+  \brief Union type to access mac_src_short_match7 (@ 0x0000042C).
+*/
+typedef union {
+  __IOM uint32_t w;                         /*!< (@ 0x0000042C) Short Source Address Match Filter Entry 7                  */
+
+  struct {
+    __IOM uint32_t addr     : 16;           /*!< [15..0] the short address of short address match entry 7                  */
+    __IOM uint32_t panid    : 16;           /*!< [31..16] the PAN ID of short address match entry 7                        */
+  } b;                                        /*!< bit fields for mac_src_short_match7 */
+} mac_src_short_match7_t, *pmac_src_short_match7_t;
+
+/**
+  \brief Union type to access mac_src_ext_match3_h (@ 0x0000042C).
+*/
+typedef union {
+  __IOM uint32_t w;                         /*!< (@ 0x0000042C) Higher 4-bytes of Extended Source Address Match
+                                                                Filter Entry 3                                             */
+
+  struct {
+    __IOM uint32_t ext_addr_h : 32;         /*!< [31..0] the higher 4-bytes of extended address of extended address
+                                                 match entry 3                                                             */
+  } b;                                        /*!< bit fields for mac_src_ext_match3_h */
+} mac_src_ext_match3_h_t, *pmac_src_ext_match3_h_t;
+
+/**
+  \brief Union type to access mac_src_short_match8 (@ 0x00000430).
+*/
+typedef union {
+  __IOM uint32_t w;                         /*!< (@ 0x00000430) Short Source Address Match Filter Entry 8                  */
+
+  struct {
+    __IOM uint32_t addr     : 16;           /*!< [15..0] the short address of short address match entry 8                  */
+    __IOM uint32_t panid    : 16;           /*!< [31..16] the PAN ID of short address match entry 8                        */
+  } b;                                        /*!< bit fields for mac_src_short_match8 */
+} mac_src_short_match8_t, *pmac_src_short_match8_t;
+
+/**
+  \brief Union type to access mac_src_ext_match4_l (@ 0x00000430).
+*/
+typedef union {
+  __IOM uint32_t w;                         /*!< (@ 0x00000430) Lower 4-bytes of Extended Source Address Match
+                                                                Filter Entry 4                                             */
+
+  struct {
+    __IOM uint32_t ext_addr_l : 32;         /*!< [31..0] the lower 4-bytes of extended address of extended address
+                                                 match entry 4                                                             */
+  } b;                                        /*!< bit fields for mac_src_ext_match4_l */
+} mac_src_ext_match4_l_t, *pmac_src_ext_match4_l_t;
+
+/**
+  \brief Union type to access mac_src_short_match9 (@ 0x00000434).
+*/
+typedef union {
+  __IOM uint32_t w;                         /*!< (@ 0x00000434) Short Source Address Match Filter Entry 9                  */
+
+  struct {
+    __IOM uint32_t addr     : 16;           /*!< [15..0] the short address of short address match entry 9                  */
+    __IOM uint32_t panid    : 16;           /*!< [31..16] the PAN ID of short address match entry 9                        */
+  } b;                                        /*!< bit fields for mac_src_short_match9 */
+} mac_src_short_match9_t, *pmac_src_short_match9_t;
+
+/**
+  \brief Union type to access mac_src_ext_match4_h (@ 0x00000434).
+*/
+typedef union {
+  __IOM uint32_t w;                         /*!< (@ 0x00000434) Higher 4-bytes of Extended Source Address Match
+                                                                Filter Entry 4                                             */
+
+  struct {
+    __IOM uint32_t ext_addr_h : 32;         /*!< [31..0] the higher 4-bytes of extended address of extended address
+                                                 match entry 4                                                             */
+  } b;                                        /*!< bit fields for mac_src_ext_match4_h */
+} mac_src_ext_match4_h_t, *pmac_src_ext_match4_h_t;
+
+/**
+  \brief Union type to access mac_src_short_match10 (@ 0x00000438).
+*/
+typedef union {
+  __IOM uint32_t w;                         /*!< (@ 0x00000438) Short Source Address Match Filter Entry 10                 */
+
+  struct {
+    __IOM uint32_t addr     : 16;           /*!< [15..0] the short address of short address match entry 10                 */
+    __IOM uint32_t panid    : 16;           /*!< [31..16] the PAN ID of short address match entry 10                       */
+  } b;                                        /*!< bit fields for mac_src_short_match10 */
+} mac_src_short_match10_t, *pmac_src_short_match10_t;
+
+/**
+  \brief Union type to access mac_src_ext_match5_l (@ 0x00000438).
+*/
+typedef union {
+  __IOM uint32_t w;                         /*!< (@ 0x00000438) Lower 4-bytes of Extended Source Address Match
+                                                                Filter Entry 5                                             */
+
+  struct {
+    __IOM uint32_t ext_addr_l : 32;         /*!< [31..0] the lower 4-bytes of extended address of extended address
+                                                 match entry 5                                                             */
+  } b;                                        /*!< bit fields for mac_src_ext_match5_l */
+} mac_src_ext_match5_l_t, *pmac_src_ext_match5_l_t;
+
+/**
+  \brief Union type to access mac_src_short_match11 (@ 0x0000043C).
+*/
+typedef union {
+  __IOM uint32_t w;                         /*!< (@ 0x0000043C) Short Source Address Match Filter Entry 11                 */
+
+  struct {
+    __IOM uint32_t addr     : 16;           /*!< [15..0] the short address of short address match entry 11                 */
+    __IOM uint32_t panid    : 16;           /*!< [31..16] the PAN ID of short address match entry 11                       */
+  } b;                                        /*!< bit fields for mac_src_short_match11 */
+} mac_src_short_match11_t, *pmac_src_short_match11_t;
+
+/**
+  \brief Union type to access mac_src_ext_match5_h (@ 0x0000043C).
+*/
+typedef union {
+  __IOM uint32_t w;                         /*!< (@ 0x0000043C) Higher 4-bytes of Extended Source Address Match
+                                                                Filter Entry 5                                             */
+
+  struct {
+    __IOM uint32_t ext_addr_h : 32;         /*!< [31..0] the higher 4-bytes of extended address of extended address
+                                                 match entry 5                                                             */
+  } b;                                        /*!< bit fields for mac_src_ext_match5_h */
+} mac_src_ext_match5_h_t, *pmac_src_ext_match5_h_t;
+
+/**
+  \brief Union type to access mac_src_short_match12 (@ 0x00000440).
+*/
+typedef union {
+  __IOM uint32_t w;                         /*!< (@ 0x00000440) Short Source Address Match Filter Entry 12                 */
+
+  struct {
+    __IOM uint32_t addr     : 16;           /*!< [15..0] the short address of short address match entry 12                 */
+    __IOM uint32_t panid    : 16;           /*!< [31..16] the PAN ID of short address match entry 12                       */
+  } b;                                        /*!< bit fields for mac_src_short_match12 */
+} mac_src_short_match12_t, *pmac_src_short_match12_t;
+
+/**
+  \brief Union type to access mac_src_ext_match6_l (@ 0x00000440).
+*/
+typedef union {
+  __IOM uint32_t w;                         /*!< (@ 0x00000440) Lower 4-bytes of Extended Source Address Match
+                                                                Filter Entry 6                                             */
+
+  struct {
+    __IOM uint32_t ext_addr_l : 32;         /*!< [31..0] the lower 4-bytes of extended address of extended address
+                                                 match entry 6                                                             */
+  } b;                                        /*!< bit fields for mac_src_ext_match6_l */
+} mac_src_ext_match6_l_t, *pmac_src_ext_match6_l_t;
+
+/**
+  \brief Union type to access mac_src_short_match13 (@ 0x00000444).
+*/
+typedef union {
+  __IOM uint32_t w;                         /*!< (@ 0x00000444) Short Source Address Match Filter Entry 13                 */
+
+  struct {
+    __IOM uint32_t addr     : 16;           /*!< [15..0] the short address of short address match entry 13                 */
+    __IOM uint32_t panid    : 16;           /*!< [31..16] the PAN ID of short address match entry 13                       */
+  } b;                                        /*!< bit fields for mac_src_short_match13 */
+} mac_src_short_match13_t, *pmac_src_short_match13_t;
+
+/**
+  \brief Union type to access mac_src_ext_match6_h (@ 0x00000444).
+*/
+typedef union {
+  __IOM uint32_t w;                         /*!< (@ 0x00000444) Higher 4-bytes of Extended Source Address Match
+                                                                Filter Entry 6                                             */
+
+  struct {
+    __IOM uint32_t ext_addr_h : 32;         /*!< [31..0] the higher 4-bytes of extended address of extended address
+                                                 match entry 6                                                             */
+  } b;                                        /*!< bit fields for mac_src_ext_match6_h */
+} mac_src_ext_match6_h_t, *pmac_src_ext_match6_h_t;
+
+/**
+  \brief Union type to access mac_src_short_match14 (@ 0x00000448).
+*/
+typedef union {
+  __IOM uint32_t w;                         /*!< (@ 0x00000448) Short Source Address Match Filter Entry 14                 */
+
+  struct {
+    __IOM uint32_t addr     : 16;           /*!< [15..0] the short address of short address match entry 14                 */
+    __IOM uint32_t panid    : 16;           /*!< [31..16] the PAN ID of short address match entry 14                       */
+  } b;                                        /*!< bit fields for mac_src_short_match14 */
+} mac_src_short_match14_t, *pmac_src_short_match14_t;
+
+/**
+  \brief Union type to access mac_src_ext_match7_l (@ 0x00000448).
+*/
+typedef union {
+  __IOM uint32_t w;                         /*!< (@ 0x00000448) Lower 4-bytes of Extended Source Address Match
+                                                                Filter Entry 7                                             */
+
+  struct {
+    __IOM uint32_t ext_addr_l : 32;         /*!< [31..0] the lower 4-bytes of extended address of extended address
+                                                 match entry 7                                                             */
+  } b;                                        /*!< bit fields for mac_src_ext_match7_l */
+} mac_src_ext_match7_l_t, *pmac_src_ext_match7_l_t;
+
+/**
+  \brief Union type to access mac_src_short_match15 (@ 0x0000044C).
+*/
+typedef union {
+  __IOM uint32_t w;                         /*!< (@ 0x0000044C) Short Source Address Match Filter Entry 15                 */
+
+  struct {
+    __IOM uint32_t addr     : 16;           /*!< [15..0] the short address of short address match entry 15                 */
+    __IOM uint32_t panid    : 16;           /*!< [31..16] the PAN ID of short address match entry 15                       */
+  } b;                                        /*!< bit fields for mac_src_short_match15 */
+} mac_src_short_match15_t, *pmac_src_short_match15_t;
+
+/**
+  \brief Union type to access mac_src_ext_match7_h (@ 0x0000044C).
+*/
+typedef union {
+  __IOM uint32_t w;                         /*!< (@ 0x0000044C) Higher 4-bytes of Extended Source Address Match
+                                                                Filter Entry 7                                             */
+
+  struct {
+    __IOM uint32_t ext_addr_h : 32;         /*!< [31..0] the higher 4-bytes of extended address of extended address
+                                                 match entry 7                                                             */
+  } b;                                        /*!< bit fields for mac_src_ext_match7_h */
+} mac_src_ext_match7_h_t, *pmac_src_ext_match7_h_t;
+
+/**
+  \brief Union type to access mac_src_short_match16 (@ 0x00000450).
+*/
+typedef union {
+  __IOM uint32_t w;                         /*!< (@ 0x00000450) Short Source Address Match Filter Entry 16                 */
+
+  struct {
+    __IOM uint32_t addr     : 16;           /*!< [15..0] the short address of short address match entry 16                 */
+    __IOM uint32_t panid    : 16;           /*!< [31..16] the PAN ID of short address match entry 16                       */
+  } b;                                        /*!< bit fields for mac_src_short_match16 */
+} mac_src_short_match16_t, *pmac_src_short_match16_t;
+
+/**
+  \brief Union type to access mac_src_ext_match8_l (@ 0x00000450).
+*/
+typedef union {
+  __IOM uint32_t w;                         /*!< (@ 0x00000450) Lower 4-bytes of Extended Source Address Match
+                                                                Filter Entry 8                                             */
+
+  struct {
+    __IOM uint32_t ext_addr_l : 32;         /*!< [31..0] the lower 4-bytes of extended address of extended address
+                                                 match entry 8                                                             */
+  } b;                                        /*!< bit fields for mac_src_ext_match8_l */
+} mac_src_ext_match8_l_t, *pmac_src_ext_match8_l_t;
+
+/**
+  \brief Union type to access mac_src_short_match17 (@ 0x00000454).
+*/
+typedef union {
+  __IOM uint32_t w;                         /*!< (@ 0x00000454) Short Source Address Match Filter Entry 17                 */
+
+  struct {
+    __IOM uint32_t addr     : 16;           /*!< [15..0] the short address of short address match entry 17                 */
+    __IOM uint32_t panid    : 16;           /*!< [31..16] the PAN ID of short address match entry 17                       */
+  } b;                                        /*!< bit fields for mac_src_short_match17 */
+} mac_src_short_match17_t, *pmac_src_short_match17_t;
+
+/**
+  \brief Union type to access mac_src_ext_match8_h (@ 0x00000454).
+*/
+typedef union {
+  __IOM uint32_t w;                         /*!< (@ 0x00000454) Higher 4-bytes of Extended Source Address Match
+                                                                Filter Entry 8                                             */
+
+  struct {
+    __IOM uint32_t ext_addr_h : 32;         /*!< [31..0] the higher 4-bytes of extended address of extended address
+                                                 match entry 7                                                             */
+  } b;                                        /*!< bit fields for mac_src_ext_match8_h */
+} mac_src_ext_match8_h_t, *pmac_src_ext_match8_h_t;
+
+/**
+  \brief Union type to access mac_src_short_match18 (@ 0x00000458).
+*/
+typedef union {
+  __IOM uint32_t w;                         /*!< (@ 0x00000458) Short Source Address Match Filter Entry 18                 */
+
+  struct {
+    __IOM uint32_t addr     : 16;           /*!< [15..0] the short address of short address match entry 18                 */
+    __IOM uint32_t panid    : 16;           /*!< [31..16] the PAN ID of short address match entry 18                       */
+  } b;                                        /*!< bit fields for mac_src_short_match18 */
+} mac_src_short_match18_t, *pmac_src_short_match18_t;
+
+/**
+  \brief Union type to access mac_src_ext_match9_l (@ 0x00000458).
+*/
+typedef union {
+  __IOM uint32_t w;                         /*!< (@ 0x00000458) Lower 4-bytes of Extended Source Address Match
+                                                                Filter Entry 9                                             */
+
+  struct {
+    __IOM uint32_t ext_addr_l : 32;         /*!< [31..0] the lower 4-bytes of extended address of extended address
+                                                 match entry 9                                                             */
+  } b;                                        /*!< bit fields for mac_src_ext_match9_l */
+} mac_src_ext_match9_l_t, *pmac_src_ext_match9_l_t;
+
+/**
+  \brief Union type to access mac_src_short_match19 (@ 0x0000045C).
+*/
+typedef union {
+  __IOM uint32_t w;                         /*!< (@ 0x0000045C) Short Source Address Match Filter Entry 19                 */
+
+  struct {
+    __IOM uint32_t addr     : 16;           /*!< [15..0] the short address of short address match entry 19                 */
+    __IOM uint32_t panid    : 16;           /*!< [31..16] the PAN ID of short address match entry 19                       */
+  } b;                                        /*!< bit fields for mac_src_short_match19 */
+} mac_src_short_match19_t, *pmac_src_short_match19_t;
+
+/**
+  \brief Union type to access mac_src_ext_match9_h (@ 0x0000045C).
+*/
+typedef union {
+  __IOM uint32_t w;                         /*!< (@ 0x0000045C) Higher 4-bytes of Extended Source Address Match
+                                                                Filter Entry 9                                             */
+
+  struct {
+    __IOM uint32_t ext_addr_h : 32;         /*!< [31..0] the higher 4-bytes of extended address of extended address
+                                                 match entry 9                                                             */
+  } b;                                        /*!< bit fields for mac_src_ext_match9_h */
+} mac_src_ext_match9_h_t, *pmac_src_ext_match9_h_t;
+
+/**
+  \brief Union type to access mac_src_short_match20 (@ 0x00000460).
+*/
+typedef union {
+  __IOM uint32_t w;                         /*!< (@ 0x00000460) Short Source Address Match Filter Entry 20                 */
+
+  struct {
+    __IOM uint32_t addr     : 16;           /*!< [15..0] the short address of short address match entry 20                 */
+    __IOM uint32_t panid    : 16;           /*!< [31..16] the PAN ID of short address match entry 20                       */
+  } b;                                        /*!< bit fields for mac_src_short_match20 */
+} mac_src_short_match20_t, *pmac_src_short_match20_t;
+
+/**
+  \brief Union type to access mac_src_ext_match10_l (@ 0x00000460).
+*/
+typedef union {
+  __IOM uint32_t w;                         /*!< (@ 0x00000460) Lower 4-bytes of Extended Source Address Match
+                                                                Filter Entry 10                                            */
+
+  struct {
+    __IOM uint32_t ext_addr_l : 32;         /*!< [31..0] the lower 4-bytes of extended address of extended address
+                                                 match entry 10                                                            */
+  } b;                                        /*!< bit fields for mac_src_ext_match10_l */
+} mac_src_ext_match10_l_t, *pmac_src_ext_match10_l_t;
+
+/**
+  \brief Union type to access mac_src_short_match21 (@ 0x00000464).
+*/
+typedef union {
+  __IOM uint32_t w;                         /*!< (@ 0x00000464) Short Source Address Match Filter Entry 21                 */
+
+  struct {
+    __IOM uint32_t addr     : 16;           /*!< [15..0] the short address of short address match entry 21                 */
+    __IOM uint32_t panid    : 16;           /*!< [31..16] the PAN ID of short address match entry 21                       */
+  } b;                                        /*!< bit fields for mac_src_short_match21 */
+} mac_src_short_match21_t, *pmac_src_short_match21_t;
+
+/**
+  \brief Union type to access mac_src_ext_match10_h (@ 0x00000464).
+*/
+typedef union {
+  __IOM uint32_t w;                         /*!< (@ 0x00000464) Higher 4-bytes of Extended Source Address Match
+                                                                Filter Entry 10                                            */
+
+  struct {
+    __IOM uint32_t ext_addr_h : 32;         /*!< [31..0] the higher 4-bytes of extended address of extended address
+                                                 match entry 10                                                            */
+  } b;                                        /*!< bit fields for mac_src_ext_match10_h */
+} mac_src_ext_match10_h_t, *pmac_src_ext_match10_h_t;
+
+/**
+  \brief Union type to access mac_src_short_match22 (@ 0x00000468).
+*/
+typedef union {
+  __IOM uint32_t w;                         /*!< (@ 0x00000468) Short Source Address Match Filter Entry 22                 */
+
+  struct {
+    __IOM uint32_t addr     : 16;           /*!< [15..0] the short address of short address match entry 22                 */
+    __IOM uint32_t panid    : 16;           /*!< [31..16] the PAN ID of short address match entry 22                       */
+  } b;                                        /*!< bit fields for mac_src_short_match22 */
+} mac_src_short_match22_t, *pmac_src_short_match22_t;
+
+/**
+  \brief Union type to access mac_src_ext_match11_l (@ 0x00000468).
+*/
+typedef union {
+  __IOM uint32_t w;                         /*!< (@ 0x00000468) Lower 4-bytes of Extended Source Address Match
+                                                                Filter Entry 11                                            */
+
+  struct {
+    __IOM uint32_t ext_addr_l : 32;         /*!< [31..0] the lower 4-bytes of extended address of extended address
+                                                 match entry 11                                                            */
+  } b;                                        /*!< bit fields for mac_src_ext_match11_l */
+} mac_src_ext_match11_l_t, *pmac_src_ext_match11_l_t;
+
+/**
+  \brief Union type to access mac_src_short_match23 (@ 0x0000046C).
+*/
+typedef union {
+  __IOM uint32_t w;                         /*!< (@ 0x0000046C) Short Source Address Match Filter Entry 23                 */
+
+  struct {
+    __IOM uint32_t addr     : 16;           /*!< [15..0] the short address of short address match entry 23                 */
+    __IOM uint32_t panid    : 16;           /*!< [31..16] the PAN ID of short address match entry 23                       */
+  } b;                                        /*!< bit fields for mac_src_short_match23 */
+} mac_src_short_match23_t, *pmac_src_short_match23_t;
+
+/**
+  \brief Union type to access mac_src_ext_match11_h (@ 0x0000046C).
+*/
+typedef union {
+  __IOM uint32_t w;                         /*!< (@ 0x0000046C) Higher 4-bytes of Extended Source Address Match
+                                                                Filter Entry 11                                            */
+
+  struct {
+    __IOM uint32_t ext_addr_h : 32;         /*!< [31..0] the higher 4-bytes of extended address of extended address
+                                                 match entry 11                                                            */
+  } b;                                        /*!< bit fields for mac_src_ext_match11_h */
+} mac_src_ext_match11_h_t, *pmac_src_ext_match11_h_t;
+
+/**
+  \brief Union type to access mac_src_short_match24 (@ 0x00000470).
+*/
+typedef union {
+  __IOM uint32_t w;                         /*!< (@ 0x00000470) Short Source Address Match Filter Entry 24                 */
+
+  struct {
+    __IOM uint32_t addr     : 16;           /*!< [15..0] the short address of short address match entry 24                 */
+    __IOM uint32_t panid    : 16;           /*!< [31..16] the PAN ID of short address match entry 24                       */
+  } b;                                        /*!< bit fields for mac_src_short_match24 */
+} mac_src_short_match24_t, *pmac_src_short_match24_t;
+
+/**
+  \brief Union type to access mac_src_ext_match12_l (@ 0x00000470).
+*/
+typedef union {
+  __IOM uint32_t w;                         /*!< (@ 0x00000470) Lower 4-bytes of Extended Source Address Match
+                                                                Filter Entry 12                                            */
+
+  struct {
+    __IOM uint32_t ext_addr_l : 32;         /*!< [31..0] the lower 4-bytes of extended address of extended address
+                                                 match entry 12                                                            */
+  } b;                                        /*!< bit fields for mac_src_ext_match12_l */
+} mac_src_ext_match12_l_t, *pmac_src_ext_match12_l_t;
+
+/**
+  \brief Union type to access mac_src_short_match25 (@ 0x00000474).
+*/
+typedef union {
+  __IOM uint32_t w;                         /*!< (@ 0x00000474) Short Source Address Match Filter Entry 25                 */
+
+  struct {
+    __IOM uint32_t addr     : 16;           /*!< [15..0] the short address of short address match entry 25                 */
+    __IOM uint32_t panid    : 16;           /*!< [31..16] the PAN ID of short address match entry 25                       */
+  } b;                                        /*!< bit fields for mac_src_short_match25 */
+} mac_src_short_match25_t, *pmac_src_short_match25_t;
+
+/**
+  \brief Union type to access mac_src_ext_match12_h (@ 0x00000474).
+*/
+typedef union {
+  __IOM uint32_t w;                         /*!< (@ 0x00000474) Higher 4-bytes of Extended Source Address Match
+                                                                Filter Entry 12                                            */
+
+  struct {
+    __IOM uint32_t ext_addr_h : 32;         /*!< [31..0] the higher 4-bytes of extended address of extended address
+                                                 match entry 12                                                            */
+  } b;                                        /*!< bit fields for mac_src_ext_match12_h */
+} mac_src_ext_match12_h_t, *pmac_src_ext_match12_h_t;
+
+/**
+  \brief Union type to access mac_src_short_match26 (@ 0x00000478).
+*/
+typedef union {
+  __IOM uint32_t w;                         /*!< (@ 0x00000478) Short Source Address Match Filter Entry 26                 */
+
+  struct {
+    __IOM uint32_t addr     : 16;           /*!< [15..0] the short address of short address match entry 26                 */
+    __IOM uint32_t panid    : 16;           /*!< [31..16] the PAN ID of short address match entry 26                       */
+  } b;                                        /*!< bit fields for mac_src_short_match26 */
+} mac_src_short_match26_t, *pmac_src_short_match26_t;
+
+/**
+  \brief Union type to access mac_src_ext_match13_l (@ 0x00000478).
+*/
+typedef union {
+  __IOM uint32_t w;                         /*!< (@ 0x00000478) Lower 4-bytes of Extended Source Address Match
+                                                                Filter Entry 13                                            */
+
+  struct {
+    __IOM uint32_t ext_addr_l : 32;         /*!< [31..0] the lower 4-bytes of extended address of extended address
+                                                 match entry 13                                                            */
+  } b;                                        /*!< bit fields for mac_src_ext_match13_l */
+} mac_src_ext_match13_l_t, *pmac_src_ext_match13_l_t;
+
+/**
+  \brief Union type to access mac_src_short_match27 (@ 0x0000047C).
+*/
+typedef union {
+  __IOM uint32_t w;                         /*!< (@ 0x0000047C) Short Source Address Match Filter Entry 27                 */
+
+  struct {
+    __IOM uint32_t addr     : 16;           /*!< [15..0] the short address of short address match entry 27                 */
+    __IOM uint32_t panid    : 16;           /*!< [31..16] the PAN ID of short address match entry 27                       */
+  } b;                                        /*!< bit fields for mac_src_short_match27 */
+} mac_src_short_match27_t, *pmac_src_short_match27_t;
+
+/**
+  \brief Union type to access mac_src_ext_match13_h (@ 0x0000047C).
+*/
+typedef union {
+  __IOM uint32_t w;                         /*!< (@ 0x0000047C) Higher 4-bytes of Extended Source Address Match
+                                                                Filter Entry 13                                            */
+
+  struct {
+    __IOM uint32_t ext_addr_h : 32;         /*!< [31..0] the higher 4-bytes of extended address of extended address
+                                                 match entry 13                                                            */
+  } b;                                        /*!< bit fields for mac_src_ext_match13_h */
+} mac_src_ext_match13_h_t, *pmac_src_ext_match13_h_t;
+
+/**
+  \brief Union type to access mac_src_short_match28 (@ 0x00000480).
+*/
+typedef union {
+  __IOM uint32_t w;                         /*!< (@ 0x00000480) Short Source Address Match Filter Entry 28                 */
+
+  struct {
+    __IOM uint32_t addr     : 16;           /*!< [15..0] the short address of short address match entry 28                 */
+    __IOM uint32_t panid    : 16;           /*!< [31..16] the PAN ID of short address match entry 28                       */
+  } b;                                        /*!< bit fields for mac_src_short_match28 */
+} mac_src_short_match28_t, *pmac_src_short_match28_t;
+
+/**
+  \brief Union type to access mac_src_ext_match14_l (@ 0x00000480).
+*/
+typedef union {
+  __IOM uint32_t w;                         /*!< (@ 0x00000480) Lower 4-bytes of Extended Source Address Match
+                                                                Filter Entry 14                                            */
+
+  struct {
+    __IOM uint32_t ext_addr_l : 32;         /*!< [31..0] the lower 4-bytes of extended address of extended address
+                                                 match entry 14                                                            */
+  } b;                                        /*!< bit fields for mac_src_ext_match14_l */
+} mac_src_ext_match14_l_t, *pmac_src_ext_match14_l_t;
+
+/**
+  \brief Union type to access mac_src_short_match29 (@ 0x00000484).
+*/
+typedef union {
+  __IOM uint32_t w;                         /*!< (@ 0x00000484) Short Source Address Match Filter Entry 29                 */
+
+  struct {
+    __IOM uint32_t addr     : 16;           /*!< [15..0] the short address of short address match entry 29                 */
+    __IOM uint32_t panid    : 16;           /*!< [31..16] the PAN ID of short address match entry 29                       */
+  } b;                                        /*!< bit fields for mac_src_short_match29 */
+} mac_src_short_match29_t, *pmac_src_short_match29_t;
+
+/**
+  \brief Union type to access mac_src_ext_match14_h (@ 0x00000484).
+*/
+typedef union {
+  __IOM uint32_t w;                         /*!< (@ 0x00000484) Higher 4-bytes of Extended Source Address Match
+                                                                Filter Entry 14                                            */
+
+  struct {
+    __IOM uint32_t ext_addr_h : 32;         /*!< [31..0] the higher 4-bytes of extended address of extended address
+                                                 match entry 14                                                            */
+  } b;                                        /*!< bit fields for mac_src_ext_match14_h */
+} mac_src_ext_match14_h_t, *pmac_src_ext_match14_h_t;
+
+/**
+  \brief Union type to access mac_src_short_match30 (@ 0x00000488).
+*/
+typedef union {
+  __IOM uint32_t w;                         /*!< (@ 0x00000488) Short Source Address Match Filter Entry 30                 */
+
+  struct {
+    __IOM uint32_t addr     : 16;           /*!< [15..0] the short address of short address match entry 30                 */
+    __IOM uint32_t panid    : 16;           /*!< [31..16] the PAN ID of short address match entry 30                       */
+  } b;                                        /*!< bit fields for mac_src_short_match30 */
+} mac_src_short_match30_t, *pmac_src_short_match30_t;
+
+/**
+  \brief Union type to access mac_src_ext_match15_l (@ 0x00000488).
+*/
+typedef union {
+  __IOM uint32_t w;                         /*!< (@ 0x00000488) Lower 4-bytes of Extended Source Address Match
+                                                                Filter Entry 15                                            */
+
+  struct {
+    __IOM uint32_t ext_addr_l : 32;         /*!< [31..0] the lower 4-bytes of extended address of extended address
+                                                 match entry 15                                                            */
+  } b;                                        /*!< bit fields for mac_src_ext_match15_l */
+} mac_src_ext_match15_l_t, *pmac_src_ext_match15_l_t;
+
+/**
+  \brief Union type to access mac_src_short_match31 (@ 0x0000048C).
+*/
+typedef union {
+  __IOM uint32_t w;                         /*!< (@ 0x0000048C) Short Source Address Match Filter Entry 31                 */
+
+  struct {
+    __IOM uint32_t addr     : 16;           /*!< [15..0] the short address of short address match entry 31                 */
+    __IOM uint32_t panid    : 16;           /*!< [31..16] the PAN ID of short address match entry 31                       */
+  } b;                                        /*!< bit fields for mac_src_short_match31 */
+} mac_src_short_match31_t, *pmac_src_short_match31_t;
+
+/**
+  \brief Union type to access mac_src_ext_match15_h (@ 0x0000048C).
+*/
+typedef union {
+  __IOM uint32_t w;                         /*!< (@ 0x0000048C) Higher 4-bytes of Extended Source Address Match
+                                                                Filter Entry 15                                            */
+
+  struct {
+    __IOM uint32_t ext_addr_h : 32;         /*!< [31..0] the higher 4-bytes of extended address of extended address
+                                                 match entry 15                                                            */
+  } b;                                        /*!< bit fields for mac_src_ext_match15_h */
+} mac_src_ext_match15_h_t, *pmac_src_ext_match15_h_t;
+
+/**
+  \brief Union type to access mac_seccr0 (@ 0x00000500).
+*/
+typedef union {
+  __IOM uint32_t w;                           /*!< (@ 0x00000500) Security Engine Control Register 0                         */
+
+  struct {
+    __IOM uint32_t txncipher  : 3;            /*!< [2..0] TX Normal FIFO Security Suite Select: 000: (default)
+                                                   Undefined; 001: AES-ENC; 010: AES-ENC-MIC-128; 011: AES-ENC-MIC-64;
+                                                   100: AES-ENC-MIC-32; 101: AES-MIC-128; 110: AES-MIC-64;
+                                                   111: AES-MIC-32;                                                          */
+    __IOM uint32_t rxcipher   : 3;            /*!< [5..3] RX FIFO Security Suite Select: 000: (default) Undefined;
+                                                   001: AES-ENC; 010: AES-ENC-MIC-128; 011: AES-ENC-MIC-64;
+                                                   100: AES-ENC-MIC-32; 101: AES-MIC-128; 110: AES-MIC-64;
+                                                   111: AES-MIC-32;                                                          */
+    __OM  uint32_t secstart   : 1;            /*!< [6..6] RX Security Decryption Start: 1: Start decryption process.
+                                                   Bit is automatically cleared to '0' by hardware                           */
+    __OM  uint32_t secignore  : 1;            /*!< [7..7] RX Security Decryption Ignore: 1: Ignore decryption process.
+                                                   Bit is automatically cleared to '0' by hardware                           */
+    __IOM uint32_t disenc     : 1;            /*!< [8..8] Disable Encryption Function: 0: (default) Enable encryption
+                                                   function; 1: Disable the encryption process. The MAC TXM
+                                                   does not encrypt the data, even if the TX security is enabled             */
+    __IOM uint32_t disdec     : 1;            /*!< [9..9] Disable Decryption Function: 0: (default) Enable decryption
+                                                   process; 1: Disable the decryption process. The MAC RXM
+                                                   does not generate a security interrupt, even if 'security'
+                                                   bit in the MAC header is detected                                         */
+          uint32_t            : 6;
+    __IOM uint32_t txbcipher  : 3;            /*!< [18..16] TXBCIPHER: TX Beacon FIFO Security Suite Select: 000:
+                                                   (default) Undefined; 001: AES-ENC; 010: AES-ENC-MIC-128;
+                                                   011: AES-ENC-MIC-64; 100: AES-ENC-MIC-32; 101: AES-MIC-128;
+                                                   110: AES-MIC-64; 111: AES-MIC-32;                                         */
+          uint32_t            : 5;
+    __IOM uint32_t txg1cipher : 3;            /*!< [26..24] TX GTS1 FIFO Security Suite Select: 000: (default)
+                                                   Undefined; 001: AES-ENC; 010: AES-ENC-MIC-128; 011: AES-ENC-MIC-64;
+                                                   100: AES-ENC-MIC-32; 101: AES-MIC-128; 110: AES-MIC-64;
+                                                   111: AES-MIC-32;                                                          */
+    __IOM uint32_t txg2cipher : 3;            /*!< [29..27] TX GTS2 FIFO Security Suite Select: 000: (default)
+                                                   Undefined; 001: AES-ENC; 010: AES-ENC-MIC-128; 011: AES-ENC-MIC-64;
+                                                   100: AES-ENC-MIC-32; 101: AES-MIC-128; 110: AES-MIC-64;
+                                                   111: AES-MIC-32;                                                          */
+          uint32_t            : 2;
+  } b;                                        /*!< bit fields for mac_seccr0 */
+} mac_seccr0_t, *pmac_seccr0_t;
+
+/**
+  \brief Union type to access mac_seccr1 (@ 0x00000504).
+*/
+typedef union {
+  __IOM uint32_t w;                           /*!< (@ 0x00000504) Security Engine Control Register 1                         */
+
+  struct {
+    __IOM uint32_t usrflag    : 1;            /*!< [0..0] User Defined Flag and initial Counter: 0: (default) Disable;
+                                                   1: Enable; User-defined flag is defined in ENCFLG(0x004[15:8])
+                                                   and AUTFLG(0x004[23:16]). User-defined counter is defined
+                                                   in LREG0x27A and LREG0x27B.                                               */
+    __IOM uint32_t sec_2006   : 1;            /*!< [1..1] Enable IEEE802.15.4-2006-compliant Block Cipher Mode:
+                                                   0: (default) Disable; 1: Enable                                           */
+    __IOM uint32_t aes_only   : 1;            /*!< [2..2] Trigger AES only mode. SW should set it '0' to come back.
+                                                   Trigger when '0' to '1'                                                   */
+          uint32_t            : 5;
+    __IOM uint32_t encflg     : 8;            /*!< [15..8] Encryption Flag. User-defined flag for encryption in
+                                                   CCM/CCM* mode of Upper Cipher operation. Only works when
+                                                   USRFLAG (0x504[0]) = '1'. 00000000: (default)                             */
+    __IOM uint32_t autflg     : 8;            /*!< [23..16] Authentication Flag. User-defined flag for authentication
+                                                   in CBC-MAC mode of Upper Cipher operation. Only works when
+                                                   USRFLAG (0x504[0]) = '1'. 00000000: (default)                             */
+          uint32_t            : 8;
+  } b;                                        /*!< bit fields for mac_seccr1 */
+} mac_seccr1_t, *pmac_seccr1_t;
+
+/**
+  \brief Union type to access mac_sec_upper_ctrl (@ 0x00000508).
+*/
+typedef union {
+  __IOM uint32_t w;                           /*!< (@ 0x00000508) Upper Layer Security Control Register                      */
+
+  struct {
+    __IOM uint32_t upenc      : 1;            /*!< [0..0] Upper Layer Security Encryption Mode: 1: Perform upper
+                                                   layer encryption using TX Normal FIFO. Bit is automatically
+                                                   cleared to '0' by hardware.                                               */
+    __IOM uint32_t updec      : 1;            /*!< [1..1] Upper Layer Security Decryption Mode: 1: Perform upper
+                                                   layer decryption using TX Normal FIFO. Bit is automatically
+                                                   cleared to '0' by hardware.                                               */
+          uint32_t            : 30;
+  } b;                                        /*!< bit fields for mac_sec_upper_ctrl */
+} mac_sec_upper_ctrl_t, *pmac_sec_upper_ctrl_t;
+
+/**
+  \brief Union type to access mac_sec_proc_sts (@ 0x0000050C).
+*/
+typedef union {
+  __IOM uint32_t w;                           /*!< (@ 0x0000050C) Security Process Status Register                           */
+
+  struct {
+    __IOM uint32_t sec_enc_done : 1;          /*!< [0..0] security engine process done indicator, write 1 clear:
+                                                   0: (default) Security engine process is not started or
+                                                   not done yet; 1: security engine process is done; FW write
+                                                   1 to clear this bit before start a new security engine
+                                                   process                                                                   */
+    __IOM uint32_t upsecerr   : 1;            /*!< [1..1] MIC Error in Upper Layer Security Mode: 0: (default)
+                                                   MIC error did not occur; 1: MIC error occurred. Write '1'
+                                                   to clear                                                                  */
+          uint32_t            : 6;
+    __IM  uint32_t txsecdone  : 1;            /*!< [8..8] Tx frame encryption process done status: 0: data encryption
+                                                   process is running; 1: data encryption is done (or data
+                                                   encryption is not triggered). FW can know whether the security
+                                                   HW engine is doing data encryption or not by read this
+                                                   bit. Ex. A secure frame transmission is failed due to the
+                                                   PHY grant is lost, FW can re-trigger the transmission when
+                                                   PHY is re-granted if the frame data encryption is done.                   */
+    __IM  uint32_t secdecerr  : 1;            /*!< [9..9] Security decryption error. Security engine set this bit
+                                                   as 1 to indicate the RX decryption is finished with MIC
+                                                   check error.                                                              */
+    __IM  uint32_t sec_upper_enclerr : 1;     /*!< [10..10] Security engine will set this bit as 1 to indicate
+                                                   the error of Frame length or Header length is 0 when doing
+                                                   upper layer encryption                                                    */
+          uint32_t            : 5;
+    __IM  uint32_t aes_only_rdy : 1;          /*!< [16..16] AES only mode complete. Setting AES_ONLY bit clears
+                                                   the status. Report '1' when complete AES process                          */
+          uint32_t            : 15;
+  } b;                                        /*!< bit fields for mac_sec_proc_sts */
+} mac_sec_proc_sts_t, *pmac_sec_proc_sts_t;
+
+/**
+  \brief Union type to access mac_sec_sts_stccmp (@ 0x00000510).
+*/
+typedef union {
+  __IOM uint32_t w;                           /*!< (@ 0x00000510) Security State and Status Register                         */
+
+  struct {
+    __IM  uint32_t scu_cs     : 3;            /*!< [2..0] Security current state                                             */
+    __IM  uint32_t parse_cs   : 3;            /*!< [5..3] Parser current state                                               */
+    __IM  uint32_t key_sr_cs  : 2;            /*!< [7..6] Key search current state                                           */
+    __IM  uint32_t st_ccmp    : 4;            /*!< [11..8] CTR/CCM/CBC-MAC current state                                     */
+          uint32_t            : 20;
+  } b;                                        /*!< bit fields for mac_sec_sts_stccmp */
+} mac_sec_sts_stccmp_t, *pmac_sec_sts_stccmp_t;
+
+/**
+  \brief Union type to access mac_sec_par_order (@ 0x00000514).
+*/
+typedef union {
+  __IOM uint32_t w;                           /*!< (@ 0x00000514) Security Parameters Bytes Order Control Register           */
+
+  struct {
+    __IOM uint32_t extadr_odr : 1;            /*!< [0..0] For security, device's extension address order setting.
+                                                   Setting this bit reverses extension address byte order                    */
+    __IOM uint32_t rxmadr_odr : 1;            /*!< [1..1] For security, receiver extension address order. Setting
+                                                   this bit reverses extension address byte order                            */
+    __IOM uint32_t frmctr_odr : 1;            /*!< [2..2] For security, frame counter field order. Setting this
+                                                   bit reverses frame counter byte order                                     */
+          uint32_t            : 29;
+  } b;                                        /*!< bit fields for mac_sec_par_order */
+} mac_sec_par_order_t, *pmac_sec_par_order_t;
+
+/**
+  \brief Union type to access mac_upnonce_0_3 (@ 0x00000518).
+*/
+typedef union {
+  __IOM uint32_t w;                           /*!< (@ 0x00000518) Upper Security Nonce Bytes 0 ~ 3                           */
+
+  struct {
+    __IOM uint32_t upnonce    : 32;           /*!< [31..0] bits[31:0] of 104-Bit Upper NONCE Value                           */
+  } b;                                        /*!< bit fields for mac_upnonce_0_3 */
+} mac_upnonce_0_3_t, *pmac_upnonce_0_3_t;
+
+/**
+  \brief Union type to access mac_upnonce_4_7 (@ 0x0000051C).
+*/
+typedef union {
+  __IOM uint32_t w;                           /*!< (@ 0x0000051C) Upper Security Nonce Bytes 4 ~ 7                           */
+
+  struct {
+    __IOM uint32_t upnonce    : 32;           /*!< [31..0] bits[63:32] of 104-Bit Upper NONCE Value                          */
+  } b;                                        /*!< bit fields for mac_upnonce_4_7 */
+} mac_upnonce_4_7_t, *pmac_upnonce_4_7_t;
+
+/**
+  \brief Union type to access mac_upnonce_8_11 (@ 0x00000520).
+*/
+typedef union {
+  __IOM uint32_t w;                           /*!< (@ 0x00000520) Upper Security Nonce Bytes 8 ~ 11                          */
+
+  struct {
+    __IOM uint32_t upnonce    : 32;           /*!< [31..0] bits[95:64] of 104-Bit Upper NONCE Value                          */
+  } b;                                        /*!< bit fields for mac_upnonce_8_11 */
+} mac_upnonce_8_11_t, *pmac_upnonce_8_11_t;
+
+/**
+  \brief Union type to access mac_upnonce_12 (@ 0x00000524).
+*/
+typedef union {
+  __IOM uint32_t w;                           /*!< (@ 0x00000524) Upper Security Nonce Byte 12                               */
+
+  struct {
+    __IOM uint32_t upnonce    : 8;            /*!< [7..0] bits[103:96] of 104-Bit Upper NONCE Value                          */
+          uint32_t            : 24;
+  } b;                                        /*!< bit fields for mac_upnonce_12 */
+} mac_upnonce_12_t, *pmac_upnonce_12_t;
+
+/**
+  \brief Union type to access mac_sec_initcntl (@ 0x00000528).
+*/
+typedef union {
+  __IOM uint32_t w;                           /*!< (@ 0x00000528) Security Engine AES-CBC Initial Counter Value              */
+
+  struct {
+    __IOM uint32_t initcnt    : 16;           /*!< [15..0] User defined Frame Counter Initial value. User-defined
+                                                   initial counter for Upper Cipher operation. Only works
+                                                   when USRFLAG (0x004[0]) = '1'.                                            */
+          uint32_t            : 16;
+  } b;                                        /*!< bit fields for mac_sec_initcntl */
+} mac_sec_initcntl_t, *pmac_sec_initcntl_t;
+
+/**
+  \brief Union type to access mac_tx_set (@ 0x00000580).
+*/
+typedef union {
+  __IOM uint32_t w;                           /*!< (@ 0x00000580) PHY TX Set Control Register                                */
+
+  struct {
+    __IOM uint32_t txagc      : 8;            /*!< [7..0] TX Gain ControlTBD: output power mapping table                     */
+    __IOM uint32_t sel_tpm    : 1;            /*!< [8..8] TX pattern format before TX On:1: TPM modulation0: IQM
+                                                   modulation                                                                */
+    __IOM uint32_t lna_en     : 1;            /*!< [9..9] enable external LNA for Zigbee                                     */
+          uint32_t            : 2;
+    __IOM uint32_t en_early_txon_tgl : 1;     /*!< [12..12] TX pattern format before TX On:1: 10b0: tail of previous
+                                                   TX packet                                                                 */
+    __IOM uint32_t radio_off  : 1;            /*!< [13..13] radio off indication: 0: radio on; 1(default): radio
+                                                   off, FW use this bit to indicate MAC HW that the RF is
+                                                   un-accessable due to the RF is under certen condition,
+                                                   like RF calibration                                                       */
+    __IOM uint32_t prestby_dly_zb : 3;        /*!< [16..14] the time delay for PHY entering standby state from
+                                                   idle state, in 1us, this field is valid when prestdby_dly_en
+                                                   = 1                                                                       */
+    __IOM uint32_t preturnon_delay_zb : 5;    /*!< [21..17] the time delay for PHY entering turn-on state from
+                                                   standby state, in 1us                                                     */
+    __IOM uint32_t rampstby_delay_zb : 5;     /*!< [26..22] the time delay for PHY entering standby state, in 1us            */
+    __IOM uint32_t sd_pos_delay_zb : 4;       /*!< [30..27] the time delay for PHY TX Turning off entering PHY
+                                                   Off state, in unit of 1us                                                 */
+    __IOM uint32_t tx_bkprg0_en : 1;          /*!< [31..31] TX backup0 programming enable                                    */
+  } b;                                        /*!< bit fields for mac_tx_set */
+} mac_tx_set_t, *pmac_tx_set_t;
+
+/**
+  \brief Union type to access mac_rx_set (@ 0x00000584).
+*/
+typedef union {
+  __IOM uint32_t w;                           /*!< (@ 0x00000584) PHY RX Set Control Register                                */
+
+  struct {
+    __IOM uint32_t dis_rf_ps  : 1;            /*!< [0..0] disable RF shut-down power saving: RF do not enter shout-down
+                                                   mode and keep in standby mode when idle                                   */
+    __IOM uint32_t prestby_dly_en : 1;        /*!< [1..1] enable time delay for PHY entering standby state                   */
+    __IOM uint32_t cca_threshold : 4;         /*!< [5..2] CCA CS mode threashold for channel busy detection, not
+                                                   use currently (FW will write the threshold value to the
+                                                   BB register directly)                                                     */
+    __IOM uint32_t cca_ed_threshold : 8;      /*!< [13..6] CCA energy detection mode threashold for channel busy
+                                                   detection, not use currently (FW will write the threshold
+                                                   value to the BB register directly)                                        */
+          uint32_t            : 2;
+    __IOM uint32_t txon_early : 6;            /*!< [21..16] the time between RIF_TX_ON and TX_PKT                            */
+    __IOM uint32_t cca_mode   : 2;            /*!< [23..22] Clear Channel Assessment (CCA) Mode Select: 00: Disable
+                                                   CCA mode(normal data RX); 01: Energy detection (ED) mode,
+                                                   which detects in-band signals; 10: Carrier sense (CS) mode,
+                                                   which detects IEEE 802.15.4 signals; 11: Combination of
+                                                   carrier sense mode and energy detection mode;                             */
+    __IOM uint32_t standby_pg_adress : 8;     /*!< [31..24] register address for resume register programing                  */
+  } b;                                        /*!< bit fields for mac_rx_set */
+} mac_rx_set_t, *pmac_rx_set_t;
+
+/**
+  \brief Union type to access mac_phy_trx_dly (@ 0x00000588).
+*/
+typedef union {
+  __IOM uint32_t w;                           /*!< (@ 0x00000588) PHY TX/RX Delay Control Register                           */
+
+  struct {
+    __IOM uint32_t txon_delay : 8;            /*!< [7..0] when txrx_timing is from initial to initial tx(such as
+                                                   tx beacon), the wait time for tx rfup                                     */
+    __IOM uint32_t rxon_delay : 8;            /*!< [15..8] when txrx_timing is from initial to initial rx or from
+                                                   tx to received-ack rx, the wait time for rx rfup. In unit
+                                                   of 1us.                                                                   */
+    __IOM uint32_t cca_rxon_delay : 8;        /*!< [23..16] when txrx_timing is from rx to cca rx, the wait time
+                                                   for cca rx rfup. In unit of 1us                                           */
+    __IOM uint32_t rx2rx_delay : 8;           /*!< [31..24] when txrx_timing is from rx to rx, the wait time for
+                                                   rx rfup. In unit of 1us.                                                  */
+  } b;                                        /*!< bit fields for mac_phy_trx_dly */
+} mac_phy_trx_dly_t, *pmac_phy_trx_dly_t;
+
+/**
+  \brief Union type to access mac_phy_to_dly (@ 0x0000058C).
+*/
+typedef union {
+  __IOM uint32_t w;                           /*!< (@ 0x0000058C) PHY Timeout and Delay Control Register                     */
+
+  struct {
+    __IOM uint32_t rx_timeout_delay : 8;      /*!< [7..0] when txrx_timing is in normal rx(rx on for receiving
+                                                   packet), the timeout for rx on, reserved for future                       */
+    __IOM uint32_t cca_rx_timeout_delay : 8;  /*!< [15..8] when txrx_timing is in cca rx, the timeout for cca processing,
+                                                   reserved for future                                                       */
+    __IOM uint32_t rx2tx_delay : 8;           /*!< [23..16] when txrx_timing is from rx to tx, the wait time for
+                                                   tx rfup                                                                   */
+    __IOM uint32_t tx2rx_delay : 8;           /*!< [31..24] when txrx_timing is from tx to rx, the wait time for
+                                                   rx rfup                                                                   */
+  } b;                                        /*!< bit fields for mac_phy_to_dly */
+} mac_phy_to_dly_t, *pmac_phy_to_dly_t;
+
+/**
+  \brief Union type to access mac_tx_prg_reg_0 (@ 0x00000590).
+*/
+typedef union {
+  __IOM uint32_t w;                           /*!< (@ 0x00000590) MAC TX backup register 0                                   */
+
+  struct {
+    __IOM uint32_t standby_pg_data : 16;      /*!< [15..0] the PHY register programming data when PHY enternign
+                                                   standby state                                                             */
+    __IOM uint32_t tx_bkprg0_pg_data : 16;    /*!< [31..16] PHY 'TX register backup 0 programming data                       */
+  } b;                                        /*!< bit fields for mac_tx_prg_reg_0 */
+} mac_tx_prg_reg_0_t, *pmac_tx_prg_reg_0_t;
+
+/**
+  \brief Union type to access mac_tx_prg_reg_1 (@ 0x00000594).
+*/
+typedef union {
+  __IOM uint32_t w;                           /*!< (@ 0x00000594) MAC TX backup register 1                                   */
+
+  struct {
+    __IOM uint32_t tx_bkprg2_pg_data : 16;    /*!< [15..0] PHY 'TX register backup 2 programming data                        */
+    __IOM uint32_t tx_bkprg1_pg_data : 16;    /*!< [31..16] PHY 'TX register backup 1 programming data                       */
+  } b;                                        /*!< bit fields for mac_tx_prg_reg_1 */
+} mac_tx_prg_reg_1_t, *pmac_tx_prg_reg_1_t;
+
+/**
+  \brief Union type to access mac_tx_prg_reg_2 (@ 0x00000598).
+*/
+typedef union {
+  __IOM uint32_t w;                           /*!< (@ 0x00000598) MAC TX backup register 2                                   */
+
+  struct {
+    __IOM uint32_t tx_bkprg0_pg_addr : 8;     /*!< [7..0] PHY TX register backup 0 programming address                       */
+    __IOM uint32_t tx_bkprg1_pg_addr : 8;     /*!< [15..8] PHY TX register backup 1 programming address                      */
+    __IOM uint32_t tx_bkprg2_pg_addr : 8;     /*!< [23..16] PHY TX register backup 2 programming address                     */
+    __IOM uint32_t tx_bkprg1_en : 1;          /*!< [24..24] tx backup programming1 enable; it programmed start
+                                                   from radio GAIN state in order(bkprg0 first, and bkprg1/2
+                                                   as following) by HW:0: disable; 1:enable                                  */
+    __IOM uint32_t tx_bkprg2_en : 1;          /*!< [25..25] tx backup programming2 enable; it programmed start
+                                                   from radio GAIN state in order(bkprg0->bkprg1->bkprg2)
+                                                   by HW: 0: disable; 1:enable                                               */
+    __IOM uint32_t rx_bkprg0_en : 1;          /*!< [26..26] rx backup programming0 enable; it programmed in order(bkprg0->bkprg1-
+                                                   bkprg2) by HW:0: disable; 1:enable                                        */
+    __IOM uint32_t rx_bkprg1_en : 1;          /*!< [27..27] rx backup programming1 enable; it programmed in order(bkprg0
+                                                   first, and bkprg1/2 as following) by HW: 0: disable; 1:enable             */
+    __IOM uint32_t rx_bkprg2_en : 1;          /*!< [28..28] rx backup programming2 enable; it programmed in order(bkprg0
+                                                   first, and bkprg1/2 as following) by HW: 0: disable; 1:enable             */
+    __IOM uint32_t rx_bkprg0_mode_en : 1;     /*!< [29..29] rx backup programming0 mode enable;mode enable indicator
+                                                   the programming setting is before RECV or after RECV state;
+                                                   0: before RECV; 1: after RECV                                             */
+    __IOM uint32_t rx_bkprg1_mode_en : 1;     /*!< [30..30] rx backup programming1 mode enable;mode enable indicator
+                                                   the programming setting is before RECV or after RECV state;0:
+                                                   before RECV; 1: after RECV                                                */
+    __IOM uint32_t rx_bkprg2_mode_en : 1;     /*!< [31..31] rx backup programming2 mode enable;mode enable indicator
+                                                   the programming setting is before RECV or after RECV state;
+                                                   0: before RECV; 1: after RECV                                             */
+  } b;                                        /*!< bit fields for mac_tx_prg_reg_2 */
+} mac_tx_prg_reg_2_t, *pmac_tx_prg_reg_2_t;
+
+/**
+  \brief Union type to access mac_rx_prg_reg_0 (@ 0x0000059C).
+*/
+typedef union {
+  __IOM uint32_t w;                           /*!< (@ 0x0000059C) MAC RX backup register 0                                   */
+
+  struct {
+    __IOM uint32_t rx_bkprg0_pg_data : 16;    /*!< [15..0] PHY RX register backup 0 programming data                         */
+    __IOM uint32_t rx_bkprg1_pg_data : 16;    /*!< [31..16] PHY RX register backup 1 programming data                        */
+  } b;                                        /*!< bit fields for mac_rx_prg_reg_0 */
+} mac_rx_prg_reg_0_t, *pmac_rx_prg_reg_0_t;
+
+/**
+  \brief Union type to access mac_rx_prg_reg_1 (@ 0x000005A0).
+*/
+typedef union {
+  __IOM uint32_t w;                           /*!< (@ 0x000005A0) MAC RX backup register 1                                   */
+
+  struct {
+    __IOM uint32_t rx_bkprg2_pg_data : 16;    /*!< [15..0] PHY RX register backup 2 programming data                         */
+    __IOM uint32_t rx_bkprg0_pg_addr : 8;     /*!< [23..16] PHY RX register backup 0 programming address                     */
+    __IOM uint32_t rx_bkprg1_pg_addr : 8;     /*!< [31..24] PHY RX register backup 1 programming address                     */
+  } b;                                        /*!< bit fields for mac_rx_prg_reg_1 */
+} mac_rx_prg_reg_1_t, *pmac_rx_prg_reg_1_t;
+
+/**
+  \brief Union type to access mac_rx_prg_reg_2r (@ 0x000005A4).
+*/
+typedef union {
+  __IOM uint32_t w;                         /*!< (@ 0x000005A4) MAC/PHY RX backup register 2                               */
+
+  struct {
+    __IM  uint32_t rx_bkprg2_pg_addr : 8;   /*!< [7..0] PHY RX register backup 2 programming address                       */
+    __IM  uint32_t channel  : 7;            /*!< [14..8] Channel Number: IEEE 802.15.4 2.4GHz band channels:
+                                                 Channel Frq. = 2402 MHz + channel (MHz)                                   */
+    __IM  uint32_t opt_cca_ed_or : 1;       /*!< [15..15] 1: use phy_cca_busy equals ed_busy or cca busy when
+                                                 cca_mode equals 3 ; 0 : use phy_cca_busy equals ed_busy
+                                                 and cca busy when cca_mode equals 3                                       */
+    __IM  uint32_t bkrpt0_read_data : 16;   /*!< [31..16] PHY register report 0 read data                                  */
+  } b;                                        /*!< bit fields for mac_rx_prg_reg_2r */
+} mac_rx_prg_reg_2r_t, *pmac_rx_prg_reg_2r_t;
+
+/**
+  \brief Union type to access mac_rx_prg_reg_2w (@ 0x000005A4).
+*/
+typedef union {
+  __OM  uint32_t w;                         /*!< (@ 0x000005A4) MAC/PHY RX backup register 2                               */
+
+  struct {
+    __OM  uint32_t rx_bkprg2_pg_addr : 8;   /*!< [7..0] PHY RX register backup 2 programming address                       */
+    __OM  uint32_t channel  : 7;            /*!< [14..8] Channel Number: IEEE 802.15.4 2.4GHz band channels:
+                                                 Channel Frq. = 2402 MHz + channel (MHz)                                   */
+    __OM  uint32_t opt_cca_ed_or : 1;       /*!< [15..15] 1: use phy_cca_busy equals ed_busy or cca busy when
+                                                 cca_mode equals 3 ; 0 : use phy_cca_busy equals ed_busy
+                                                 and cca busy when cca_mode equals 3                                       */
+    __OM  uint32_t bkrpt0_reg_addr : 8;     /*!< [23..16] PHY register report 0 address. Set bit 7 = 0 for register
+                                                 read                                                                      */
+    __OM  uint32_t bkrpt0_en : 1;           /*!< [24..24] rx backup report0 enable; it programmed only after
+                                                 RECV and report it in order(bkrpt0 first, and bkrpt1/2/3/4
+                                                 as following) by HW: 0: disable; 1:enable                                 */
+          uint32_t          : 7;
+  } b;                                        /*!< bit fields for mac_rx_prg_reg_2w */
+} mac_rx_prg_reg_2w_t, *pmac_rx_prg_reg_2w_t;
+
+/**
+  \brief Union type to access mac_rx_bkrpt0r (@ 0x000005A8).
+*/
+typedef union {
+  __IOM uint32_t w;                         /*!< (@ 0x000005A8) PHY RX backup register 0                                   */
+
+  struct {
+    __IM  uint32_t bkrpt2_read_data : 16;   /*!< [15..0] PHY register report 2 read data                                   */
+    __IM  uint32_t bkrpt1_read_data : 16;   /*!< [31..16] PHY register report 1 read data                                  */
+  } b;                                        /*!< bit fields for mac_rx_bkrpt0r */
+} mac_rx_bkrpt0r_t, *pmac_rx_bkrpt0r_t;
+
+/**
+  \brief Union type to access mac_rx_bkrpt0w (@ 0x000005A8).
+*/
+typedef union {
+  __OM  uint32_t w;                         /*!< (@ 0x000005A8) PHY RX backup register 0                                   */
+
+  struct {
+    __OM  uint32_t bkrpt2_reg_addr : 8;     /*!< [7..0] PHY register report 2 address. Set bit 7 = 0 for register
+                                                 read.                                                                     */
+    __OM  uint32_t bkrpt2_en : 1;           /*!< [8..8] rx backup report2 enable; it programmed only after RECV
+                                                 and report it in order(bkrpt0 first, and bkrpt1/2/3/4 as
+                                                 following) by HW:0: disable; 1:enable                                     */
+          uint32_t          : 7;
+    __OM  uint32_t bkrpt1_reg_addr : 8;     /*!< [23..16] PHY register report 1 address. Set bit 7 = 0 for register
+                                                 read.                                                                     */
+    __OM  uint32_t bkrpt1_en : 1;           /*!< [24..24] rx backup report1 enable; it programmed only after
+                                                 RECV and report it in order(bkrpt0 first, and bkrpt1/2/3/4
+                                                 as following) by HW:0: disable; 1:enable                                  */
+          uint32_t          : 7;
+  } b;                                        /*!< bit fields for mac_rx_bkrpt0w */
+} mac_rx_bkrpt0w_t, *pmac_rx_bkrpt0w_t;
+
+/**
+  \brief Union type to access mac_rx_bkrpt1r (@ 0x000005AC).
+*/
+typedef union {
+  __IOM uint32_t w;                         /*!< (@ 0x000005AC) PHY RX backup register 1                                   */
+
+  struct {
+    __IM  uint32_t bkrpt4_read_data : 16;   /*!< [15..0] PHY register report 4 read data                                   */
+    __IM  uint32_t bkrpt3_read_data : 16;   /*!< [31..16] PHY register report 3 read data                                  */
+  } b;                                        /*!< bit fields for mac_rx_bkrpt1r */
+} mac_rx_bkrpt1r_t, *pmac_rx_bkrpt1r_t;
+
+/**
+  \brief Union type to access mac_rx_bkrpt1w (@ 0x000005AC).
+*/
+typedef union {
+  __OM  uint32_t w;                         /*!< (@ 0x000005AC) PHY RX backup register 1                                   */
+
+  struct {
+    __OM  uint32_t bkrpt4_reg_addr : 8;     /*!< [7..0] PHY register report 4 address. Set bit 7 = 0 for register
+                                                 read.                                                                     */
+    __OM  uint32_t bkrpt4_en : 1;           /*!< [8..8] rx backup report4 enable; it programmed only after RECV
+                                                 and report it in order(bkrpt0 first, and bkrpt1/2/3/4 as
+                                                 following) by HW:0: disable; 1:enable                                     */
+          uint32_t          : 7;
+    __OM  uint32_t bkrpt3_reg_addr : 8;     /*!< [23..16] PHY register report 3 address. Set bit 7 = 0 for register
+                                                 read.                                                                     */
+    __OM  uint32_t bkrpt3_en : 1;           /*!< [24..24] rx backup report3 enable; it programmed only after
+                                                 RECV and report it in order(bkrpt0 first, and bkrpt1/2/3/4
+                                                 as following) by HW:0: disable; 1:enable                                  */
+          uint32_t          : 7;
+  } b;                                        /*!< bit fields for mac_rx_bkrpt1w */
+} mac_rx_bkrpt1w_t, *pmac_rx_bkrpt1w_t;
+
+/**
+  \brief Union type to access mac_phy_early_afe (@ 0x000005B0).
+*/
+typedef union {
+  __IOM uint32_t w;                           /*!< (@ 0x000005B0) PHY Early Analog Fron End On Time Control Register         */
+
+  struct {
+    __IOM uint32_t rxon_early_afe : 8;        /*!< [7..0] time to eraly trun on RF before entering RX ON state               */
+    __IOM uint32_t txon_early_afe : 8;        /*!< [15..8] time to eraly trun on RF before entering TX ON state              */
+    __IOM uint32_t rampdown_delay_zb : 6;     /*!< [21..16] the time delay for PHY entering ramp-standby state
+                                                   from TRAN state, in 1us                                                   */
+          uint32_t            : 10;
+  } b;                                        /*!< bit fields for mac_phy_early_afe */
+} mac_phy_early_afe_t, *pmac_phy_early_afe_t;
+
+/**
+  \brief Union type to access mac_mac_rf_state (@ 0x000005B4).
+*/
+typedef union {
+  __IOM uint32_t w;                           /*!< (@ 0x000005B4) RF State Indication Register for MAC-PHY interface         */
+
+  struct {
+    __IM  uint32_t txrx_cst   : 5;            /*!< [4..0] TX/RX current state                                                */
+    __IM  uint32_t radio_cst  : 5;            /*!< [9..5] Radio current state0: IDLE; 6: PRETURNON; 7: RECV;                 */
+    __IOM uint32_t dbg_sel    : 4;            /*!< [13..10] debug port selection bit[3:0], bit[4] at REG0x5B4[24]zb_rf_debug
+                                                   port select: 0: tx/rx state machine debug port 0 1: tx/rx
+                                                   state machine debug port 1 2: radio state machine debug
+                                                   port 0 3: radio state machine debug port 1 4: radio state
+                                                   machine debug port 2 5: radio state machine debug port
+                                                   3                                                                         */
+    __IM  uint32_t zb_rx_hit_flg : 1;         /*!< [14..14] latch zb_rx_hit , and be cleared when leave RX state(for
+                                                   debug)                                                                    */
+    __IM  uint32_t rxframe    : 1;            /*!< [15..15] latch rxm enable(for debug)                                      */
+    __IM  uint32_t rxlength   : 7;            /*!< [22..16] the frame length of receiving frame, it will be cleared
+                                                   on next RXON (for debug)                                                  */
+    __IM  uint32_t zb_rx_full_and_hit_flg : 1;/*!< [23..23] latch zb_rx_hit and rxfifo_full2(for debug)                      */
+    __IOM uint32_t dbg_sel_b4 : 1;            /*!< [24..24] bit4 of dbg_sel                                                  */
+    __IM  uint32_t zb_lut_state : 2;          /*!< [26..25] PHY arbitration state with BT BR/EDR concurrent (for
+                                                   debug)when PHY is granted, TXM/RXM/Radio state will wait
+                                                   le_block = 0                                                              */
+          uint32_t            : 5;
+  } b;                                        /*!< bit fields for mac_mac_rf_state */
+} mac_mac_rf_state_t, *pmac_mac_rf_state_t;
+
+/**
+  \brief Union type to access mac_dbg_sig (@ 0x000005B8).
+*/
+typedef union {
+  __IOM uint32_t w;                           /*!< (@ 0x000005B8) Signal Latch for Debug                                     */
+
+  struct {
+    __IM  uint32_t zb_rx_hit_cnt : 16;        /*!< [15..0] zb_rx_hit count, increase 1 on every zb_rx_hit. Write
+                                                   1 to gr_dbg_cnt_reset_o (reg 0x90[5]) to clear this count.                */
+          uint32_t            : 16;
+  } b;                                        /*!< bit fields for mac_dbg_sig */
+} mac_dbg_sig_t, *pmac_dbg_sig_t;
+
+/**
+  \brief Union type to access mac_cca_dbg (@ 0x000005BC).
+*/
+typedef union {
+  __IOM uint32_t w;                           /*!< (@ 0x000005BC) CCA Machine signal latch for debug register                */
+
+  struct {
+    __IM  uint32_t zb_cca_rpt : 4;            /*!< [3..0] latch zb_cca_rpt for debugging                                     */
+    __IM  uint32_t zb_ed_rpt  : 8;            /*!< [11..4] latch zb_ed_rpt for debugging                                     */
+    __IM  uint32_t rx_cca_duration : 1;       /*!< [12..12] latch rx_cca_duration for debugging                              */
+    __IM  uint32_t not_cca_turn_tx : 1;       /*!< [13..13] latch not_cca_trun_tx for debugging                              */
+    __IM  uint32_t not_cca_turn_rx : 1;       /*!< [14..14] latch not_cca_trun_rx for debugging                              */
+    __IM  uint32_t phy_cca_i  : 1;            /*!< [15..15] latch phy_cca_i for debugging                                    */
+    __IM  uint32_t txm_txpe   : 1;            /*!< [16..16] latch txm_txpe for debugging                                     */
+    __IM  uint32_t no_cca_vld_flg : 1;        /*!< [17..17] latch no_cca_vld_flg for debugging                               */
+          uint32_t            : 14;
+  } b;                                        /*!< bit fields for mac_cca_dbg */
+} mac_cca_dbg_t, *pmac_cca_dbg_t;
+
+/**
+  \brief Union type to access mac_cca_dbg1 (@ 0x000005C0).
+*/
+typedef union {
+  __IOM uint32_t w;                           /*!< (@ 0x000005C0) CCA Machine signal latch for debug register                */
+
+  struct {
+    __IM  uint32_t zb_rx_cca_cnt : 16;        /*!< [15..0] CCA process count, increase 1 on every CCA process start.
+                                                   Write 1 to reg 0x63[6] to clear this count.                               */
+    __IM  uint32_t zb_cca_vld_cnt : 16;       /*!< [31..16] zb_cca_vld count, increase 1 on every zb_cca_vld. Write
+                                                   1 to reg 0x63[6] to clear this count.                                     */
+  } b;                                        /*!< bit fields for mac_cca_dbg1 */
+} mac_cca_dbg1_t, *pmac_cca_dbg1_t;
+
+/**
+  \brief Union type to access mac_rx_set1 (@ 0x000005C4).
+*/
+typedef union {
+  __IOM uint32_t w;                           /*!< (@ 0x000005C4) PHY RX Setup Control Register1                             */
+
+  struct {
+    __IOM uint32_t rx_min_len : 3;            /*!< [2..0] set the minimum frame length of RX Filter. Frame_length
+                                                   < rx_min_len will not be received.                                        */
+    __IOM uint32_t rxon_off_dly : 7;          /*!< [9..3] in us, last phy_rxrdy to rxm_frm end time duration and
+                                                   add a little delay                                                        */
+    __IOM uint32_t rxon2ccadt_dly : 4;        /*!< [13..10] in us, means rxon to csma_state==CCADT delay, used
+                                                   in scheduled TX mode.                                                     */
+          uint32_t            : 2;
+    __IOM uint32_t ed_scan_rxon_delay : 8;    /*!< [23..16] in us, means rxon to ED Scan start delay                         */
+    __IOM uint32_t rx2tx_imm_ack_delay : 8;   /*!< [31..24] in us, RX to TX delay for Imm-Ack TX.                            */
+  } b;                                        /*!< bit fields for mac_rx_set1 */
+} mac_rx_set1_t, *pmac_rx_set1_t;
+
+/**
+  \brief Union type to access mac_tx_enh_ack_ctrl (@ 0x000005C8).
+*/
+typedef union {
+  __IOM uint32_t w;                           /*!< (@ 0x000005C8) Enhance Ack(GTS1) TX Control Register                      */
+
+  struct {
+    __IOM uint32_t gts_enh_ack_timer : 8;     /*!< [7..0] the time window, in unit of us, for FW to set the Enh-Ack
+                                                   TX trigger. The time window is opened when the rxif is
+                                                   asserted and the received frame is a 2015 version frame
+                                                   with ACK request, if the Enh-Ack frame for this response
+                                                   is ready the the FW need to set the GTS FIFO TX trigger
+                                                   during this time window.                                                  */
+    __IOM uint32_t rx2tx_enh_ack_delay : 8;   /*!< [15..8] in us, the time delay for the trunning of PHY from RX
+                                                   to TX to transmite Enh-Ack frame (in GTS1 FIFO)                           */
+    __IM  uint32_t gts_enh_ack_trig_en : 1;   /*!< [16..16] indicates whether the time window is opened and the
+                                                   Enh-Ack TX trigger is available. 0: the time windows is
+                                                   closed (it's too late to trigger the Enh-Ack TX); 1: the
+                                                   time windows is opened, set the Enh-Ack TX trigger is available.          */
+    __IOM uint32_t alt_gts_enh_ack_mask : 1;  /*!< [17..17] FW set this bit to select the timer value for the RXM
+                                                   to apply to the GTS Enh-Ack timer.0: use gts_enh_ack_timer
+                                                   value; 1: use alt_gts_enh_ack_timer value;Normally, FW
+                                                   set this bit to select a different time window for the
+                                                   Enh-Ack trigger bit writting. Ex. the FW select a wider
+                                                   time window when it will write the Enh-Ack TX trigger bit
+                                                   in RX done interrupt handler rather than in RX early interrupt
+                                                   handler. The RXM will latch this bit value when it starting
+                                                   the Enh-Ack timer.                                                        */
+          uint32_t            : 6;
+    __IOM uint32_t alt_gts_enh_ack_timer : 8; /*!< [31..24] an alternate timer window, in unit of us, for FW to
+                                                   set the timer for Enh-Ack TX trigger. The time window is
+                                                   opened when the rxif is asserted and the received frame
+                                                   is a 2015 version frame with ACK request, if the Enh-Ack
+                                                   frame for this response is ready the the FW need to set
+                                                   the GTS FIFO TX trigger during this time window. The GTS
+                                                   TX FIFO encryption will takes time depends on the frame
+                                                   length to encrypt, so the FW may need to adjust the timer
+                                                   value to make the Enh-Ack frame TX at a proper time to
+                                                   have a                                                                    */
+  } b;                                        /*!< bit fields for mac_tx_enh_ack_ctrl */
+} mac_tx_enh_ack_ctrl_t, *pmac_tx_enh_ack_ctrl_t;
+
+/**
+  \brief Union type to access mac_pta_ctrl1 (@ 0x000005F8).
+*/
+typedef union {
+  __IOM uint32_t w;                           /*!< (@ 0x000005F8) PTA Control Register 1                                     */
+
+  struct {
+    __IOM uint32_t pta_en     : 1;            /*!< [0..0] PTA (packet transmission arbitration) for WIFI + 802.15.4
+                                                   function enable control:0: disable PTA function (default),
+                                                   ignore PTA WL_ACT signal and no abort TX/RX1: enable PTA
+                                                   function, abort TX/RX when PTA WL_ACT is high                             */
+    __IOM uint32_t pta_share_lna : 1;         /*!< [1..1] FW use this bit to indicate the PTA HW whether BT PHY
+                                                   share LAN with WIFI: 1: wifi/BT share LNA. 0: wifi/BT dedicated
+                                                   LNA and zigbee acc hit will trigger high priority request
+                                                   if original RX PTA priority is low                                        */
+    __IOM uint32_t cca_req    : 1;            /*!< [2..2] Dedicated PTA request for the CCA of a packet TX: 0:
+                                                   no dedicated PTA request for CCA. Only issue 1 PTA request
+                                                   for CCA + TX. 1: issue a RX PTA request for CCA and then
+                                                   another PTA request for TX. The priority of the PTA request
+                                                   for CCA follows the priority setting of TX PTA request
+                                                   (tx_priority).                                                            */
+    __IOM uint32_t tx_priority : 1;           /*!< [3..3] The priority of PTA request for a packet TX: 0: issue
+                                                   low priority PTA request for packet TX (include its CCA).
+                                                   1: issue high priority PTA request for packet TX (include
+                                                   its CCA).                                                                 */
+          uint32_t            : 28;
+  } b;                                        /*!< bit fields for mac_pta_ctrl1 */
+} mac_pta_ctrl1_t, *pmac_pta_ctrl1_t;
+
+/**
+  \brief Union type to access mac_pta_ctrl0 (@ 0x000005FC).
+*/
+typedef union {
+  __IOM uint32_t w;                           /*!< (@ 0x000005FC) PTA Control Register 0                                     */
+
+  struct {
+    __IOM uint32_t pta_duty_en : 1;           /*!< [0..0] enable PTA priority duty control function. When this
+                                                   function is enabled, MAC will send high priority PTA request
+                                                   for idle RX periodically. 0: disable PTA priority duty
+                                                   control function (default); 1: enable PTA priority duty
+                                                   control function the PTA duty interval will start with
+                                                   high priority period when PTA priority duty control is
+                                                   enabled.                                                                  */
+    __IOM uint32_t dis_lo_rx_req : 1;         /*!< [1..1] disable low priority PTA request: 0: when RX is low priority,
+                                                   issue a low priority PTA request. 1: when RX is low priority,
+                                                   do not issue PTA request and ignore PTA WL_ACT signal.                    */
+          uint32_t            : 2;
+    __IOM uint32_t pta_tick_ctrl : 12;        /*!< [15..4] this field set the unit, in us, of a tick for the PTA
+                                                   priority duty control function. The duty ratio of the PTA
+                                                   with high priority control is based on this tick counting.
+                                                   Time of a tick = 1 + the value of this field, in unit of
+                                                   us. Example, set this field as 1 means time of a tick is
+                                                   2us. default value is 1000us (1ms).                                       */
+    __IOM uint32_t pta_low_duty_tick : 8;     /*!< [23..16] this field is used to set the time period of the low
+                                                   priority part in a PTA priority duty control interval,
+                                                   in unit of a tick. Low priority period = (1 + value of
+                                                   this filed)* (tick time). Example, set this filed value
+                                                   as 1 means the time period of low priority is 2 ticks time.
+                                                   default value is 100 ticks (100ms).                                       */
+    __IOM uint32_t pta_high_duty_tick : 8;    /*!< [31..24] this field is used to set the time period of the high
+                                                   priority part in a PTA priority duty control interval,
+                                                   in unit of a tick. High priority period = (1 + value of
+                                                   this filed)* (tick time). Example, set this filed value
+                                                   as 3 means the time period of high priority is 4 ticks
+                                                   time. default value is 100 ticks (100ms).                                 */
+  } b;                                        /*!< bit fields for mac_pta_ctrl0 */
+} mac_pta_ctrl0_t, *pmac_pta_ctrl0_t;
+
+/** @} */ /* End of group ls_hal_mac_reg */
+/// @endcond /* End of condition DOXYGEN_GENERAL_REG_TYPE || DOXYGEN_MAC_REG_TYPE */
+
+
+#ifdef  __cplusplus
+}
+#endif
+
+#endif    // end of #ifndef _MAC_REG_TYPE_H_
diff --git a/bee/drivers/mac_802154/rom/portable/rtl87x2g/mac_port_macro.h b/bee/drivers/mac_802154/rom/portable/rtl87x2g/mac_port_macro.h
new file mode 100644
index 00000000..76ea9eb4
--- /dev/null
+++ b/bee/drivers/mac_802154/rom/portable/rtl87x2g/mac_port_macro.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**************************************************************************//**
+ * @file     mac_port_macro.h
+ * @brief    Header file for MAC/PHY driver platform porting macros.
+ *
+ * @version  V1.00
+ * @date     2022-09-14
+ *
+ * @note
+ *
+ ******************************************************************************/
+
+#ifndef _MAC_DRIVER_PORT_H_
+#define _MAC_DRIVER_PORT_H_
+
+/* define macros for MAC driver porting on the specified platform here */
+#include "rtl876x.h"                           /*!< ARM Cortex-M4 processor and core peripherals                              */
+
+#define PORT_CATEGORY_BT_SOC
+#define PORT_PLATFORM_RTL87X2G
+
+#define DEFAULT_RF_MODE     RF_TPM
+#ifndef _IS_ASIC_   // FPGA, use external RF board
+#undef DEFAULT_RF_MODE
+#define DEFAULT_RF_MODE     RF_IQM
+#endif
+
+#endif  /* end of _MAC_DRIVER_PORT_H_ */
diff --git a/bee/drivers/mac_802154/rom/power_manager_unit_zbmac.h b/bee/drivers/mac_802154/rom/power_manager_unit_zbmac.h
new file mode 100644
index 00000000..ba8268cc
--- /dev/null
+++ b/bee/drivers/mac_802154/rom/power_manager_unit_zbmac.h
@@ -0,0 +1,106 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**************************************************************************//**
+ * @file     power_manager_unit_zbmac.h
+ * @brief    Zigbee MAC Power Manager Unit Functions header file.
+ *
+ * @version  V1.00
+ * @date     2022-11-29
+ *
+ * @note
+ *
+ ******************************************************************************/
+
+#ifndef PWR_MANAG_UNIT_ZBMAC_H
+#define PWR_MANAG_UNIT_ZBMAC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "power_manager_interface.h"
+
+typedef enum zbmac_power_mode_e
+{
+    ZBMAC_DEEP_SLEEP        = 0,   /**< Deep sleep */
+    ZBMAC_ACTIVE            = 1,   /**< Active     */
+} zbmac_power_mode_t, *pzbmac_power_mode_t;
+
+/* power manager state(stage) transition cycle:
+  Check -> Store -> Enter -> Exit -> Restore */
+typedef enum zbmac_pm_state_e
+{
+    ZBMAC_PM_CHECK          = 0,
+    ZBMAC_PM_STORE          = 1,
+    ZBMAC_PM_ENTER          = 2,
+    ZBMAC_PM_EXIT           = 3,
+    ZBMAC_PM_RESTORE        = 4,
+    ZBMAC_PM_STAGE_MAX      = 5
+} zbmac_pm_state_t;
+
+typedef enum
+{
+    ZBMAC_PM_WAKEUP_UNKNOWN                 = 0x0,
+    ZBMAC_PM_WAKEUP_RESUME                  = 0x1,
+    ZBMAC_PM_WAKEUP_PRE_SYSTEM_LEVEL        = 0x2,
+} zbmac_wakeup_reason_t;
+
+typedef enum
+{
+    ZBMAC_PM_ERROR_UNKNOWN                  = 0x00,
+    ZBMAC_PM_ERROR_POWER_MODE               = 0x01,
+    ZBMAC_PM_ERROR_RADIO_BUSY               = 0x02,
+    ZBMAC_PM_ERROR_RX_BUSY                  = 0x03,
+    ZBMAC_PM_ERROR_SCANNING                 = 0x04,
+    ZBMAC_PM_ERROR_INTERRUPT_PENDING        = 0x05,
+    ZBMAC_PM_ERROR_WAKEUP_TIME              = 0x06,
+    ZBMAC_PM_ERROR_32K_CHECK_LOCK           = 0x07,
+    ZBMAC_PM_ERROR_HW_TIMER_RUNNING         = 0x08,
+    ZBMAC_PM_ERROR_OCCUPIED_TIME            = 0x09,
+} zbmac_power_mode_err_code_t;
+
+typedef void (*zbpm_callback_t)(void);
+
+typedef struct zbpm_adapter_s
+{
+    zbmac_power_mode_t power_mode;  /* Current power_mode,
+                                       App set power_mode = ZBMAC_DEEP_SLEEP to enter DLPS */
+    zbmac_wakeup_reason_t wakeup_reason;    // what cause ZB MAC waken
+    zbmac_power_mode_err_code_t error_code; // the reason cannot enter sleep mode
+    uint16_t stage_time[ZBMAC_PM_STAGE_MAX];  /* the time, in unit of 32K ticks, will take for
+                                                 each stage */
+    uint16_t minimum_sleep_time;    /* minimum time sleep time, in unit of 32K ticks. the duration
+                                       from current time to wakeup time cannot smaller than this value */
+    uint16_t learning_guard_time;   /* guard time, in 32K ticks, for learned stage time */
+    struct
+    {
+        uint16_t wake_interval_en : 1;     // is wakeup periodical interval enabled
+        uint16_t stage_time_learned : 1;   // is to learn (measure) PM stages consumed time
+        uint16_t reserved : 14;
+    } cfg;
+
+    uint32_t wakeup_time_us;  // the time stamp of next wakeup time, in unit of us by BT clock
+    uint32_t wakeup_interval_us;  // the sleep interval, in unit of us
+    uint32_t scheduled_wakeup_time;
+    zbpm_callback_t enter_callback; // call back function when in enter stage
+    zbpm_callback_t exit_callback;  // call back function when in exit stage
+    uint32_t enter_time_us;  // the time stamp of entering ZBMAC_PM_ENTER stage, in unit of us by BT clock
+    void *pretain_buf;  // the MAC registers retainion buffer
+} zbpm_adapter_t, *pzbpm_adapter_t;
+
+extern PMCheckResult(*zbmac_pm_check)(const uint32_t, const uint32_t, uint32_t *);
+extern void (*zbmac_pm_store)(void);
+extern void (*zbmac_pm_restore)(void);
+extern void (*zbmac_pm_enter)(void);
+extern void (*zbmac_pm_exit)(void);
+extern void (*zbmac_pm_init)(zbpm_adapter_t *padapter);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PWR_MANAG_UNIT_ZBMAC_H */
diff --git a/bee/drivers/mac_802154/rom/zb_section.h b/bee/drivers/mac_802154/rom/zb_section.h
new file mode 100644
index 00000000..aa423eab
--- /dev/null
+++ b/bee/drivers/mac_802154/rom/zb_section.h
@@ -0,0 +1,58 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**************************************************************************//**
+ * @file     zb_section.h
+ * @brief    define memory section name for zigbee.
+ *
+ * @version  V1.00
+ * @date     2023-05-06
+ *
+ * @note
+ *
+ ******************************************************************************/
+
+#ifndef _ZB_SECTION_H_
+#define _ZB_SECTION_H_
+
+#if !defined(SECTION)
+#define SECTION(_name) __attribute__ ((__section__(_name)))
+#endif
+
+#define SECTION_ZB_ROM_TEXT         SECTION(".rom.zb.text")
+#define SECTION_ZB_ROM_RODATA       SECTION(".rom.zb.rodata")
+#define SECTION_ZB_ROM_DATA         SECTION(".rom.zb.data")
+#define SECTION_ZB_ROM_BSS          SECTION(".rom.zb.bss")
+
+#define SECTION_ZB_PATCH_TEXT       SECTION(".patch.zb.text")
+#define SECTION_ZB_PATCH_RODATA     SECTION(".patch.zb.rodata")
+#define SECTION_ZB_PATCH_DATA       SECTION(".patch.zb.data")
+#define SECTION_ZB_PATCH_BSS        SECTION(".patch.zb.bss")
+
+#define SECTION_ZB_MP_ROM_TEXT      SECTION(".rom.zb_mp.text")
+#define SECTION_ZB_MP_ROM_RODATA    SECTION(".rom.zb_mp.rodata")
+#define SECTION_ZB_MP_ROM_DATA      SECTION(".rom.zb_mp.data")
+#define SECTION_ZB_MP_ROM_BSS       SECTION(".rom.zb_mp.bss")
+
+#define SECTION_ZB_MP_PATCH_TEXT    SECTION(".patch.zb_mp.text")
+#define SECTION_ZB_MP_PATCH_RODATA  SECTION(".patch.zb_mp.rodata")
+#define SECTION_ZB_MP_PATCH_DATA    SECTION(".patch.zb_mp.data")
+#define SECTION_ZB_MP_PATCH_BSS     SECTION(".patch.zb_mp.bss")
+
+#define SECTION_ZB_IPC_TEXT         SECTION(".zb_ipc.text")
+#define SECTION_ZB_IPC_ITCM         SECTION(".zb_ipc.itcm.text")
+#define SECTION_ZB_IPC_RODATA       SECTION(".zb_ipc.rodata")
+#define SECTION_ZB_IPC_DATA         SECTION(".zb_ipc.data")
+#define SECTION_ZB_IPC_BSS          SECTION(".zb_ipc.bss")
+#define SECTION_ZB_IPC_SHARE_MEM    SECTION(".zb_ipc_share.bss")
+#define SECTION_ZB_IPC_BUF_DESC     SECTION(".zb_ipc_buf_desc.rodata")
+
+#define SECTION_ZB_PM_ROM_TEXT      SECTION(".rom.zb_pm.text")
+#define SECTION_ZB_PM_ROM_RODATA    SECTION(".rom.zb_pm.rodata")
+#define SECTION_ZB_PM_ROM_DATA      SECTION(".rom.zb_pm.data")
+#define SECTION_ZB_PM_ROM_BSS       SECTION(".rom.zb_pm.bss")
+
+#endif // _ZB_SECTION_H_
diff --git a/bee/drivers/mac_802154/src/mac_802154_frame_parser.c b/bee/drivers/mac_802154/src/mac_802154_frame_parser.c
new file mode 100644
index 00000000..2d7d2bf1
--- /dev/null
+++ b/bee/drivers/mac_802154/src/mac_802154_frame_parser.c
@@ -0,0 +1,646 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "mac_802154_frame_parser.h"
+
+#include <stdlib.h>
+
+/***************************************************************************************************
+ * @section Helper functions
+ **************************************************************************************************/
+
+// Version
+static uint8_t frame_version_get(const uint8_t * p_frame)
+{
+    return p_frame[FRAME_VERSION_OFFSET] & FRAME_VERSION_MASK;
+}
+
+// Addressing
+
+static uint8_t addressing_offset_get(const uint8_t * p_frame)
+{
+    if ((frame_version_get(p_frame) >= FRAME_VERSION_2) &&
+        mac_802154_frame_parser_dsn_suppress_bit_is_set(p_frame))
+    {
+        return PHR_SIZE + FCF_SIZE;
+    }
+    else
+    {
+        return PHR_SIZE + FCF_SIZE + DSN_SIZE;
+    }
+}
+
+static bool src_addr_is_present(const uint8_t * p_frame)
+{
+    return (p_frame[SRC_ADDR_TYPE_OFFSET] & SRC_ADDR_TYPE_MASK) != SRC_ADDR_TYPE_NONE;
+}
+
+static bool dst_addr_is_present(const uint8_t * p_frame)
+{
+    return (p_frame[DEST_ADDR_TYPE_OFFSET] & DEST_ADDR_TYPE_MASK) != DEST_ADDR_TYPE_NONE;
+}
+
+static uint8_t src_addr_size_get(const uint8_t * p_frame)
+{
+    switch (p_frame[SRC_ADDR_TYPE_OFFSET] & SRC_ADDR_TYPE_MASK)
+    {
+        case SRC_ADDR_TYPE_NONE:
+            return 0;
+
+        case SRC_ADDR_TYPE_SHORT:
+            return SHORT_ADDRESS_SIZE;
+
+        case SRC_ADDR_TYPE_EXTENDED:
+            return EXTENDED_ADDRESS_SIZE;
+
+        default:
+            return MAC_802154_FRAME_PARSER_INVALID_OFFSET;
+    }
+}
+
+static uint8_t dst_addr_size_get(const uint8_t * p_frame)
+{
+    switch (p_frame[DEST_ADDR_TYPE_OFFSET] & DEST_ADDR_TYPE_MASK)
+    {
+        case DEST_ADDR_TYPE_NONE:
+            return 0;
+
+        case DEST_ADDR_TYPE_SHORT:
+            return SHORT_ADDRESS_SIZE;
+
+        case DEST_ADDR_TYPE_EXTENDED:
+            return EXTENDED_ADDRESS_SIZE;
+
+        default:
+            return MAC_802154_FRAME_PARSER_INVALID_OFFSET;
+    }
+}
+
+// PAN ID
+static bool dst_panid_is_present(const uint8_t * p_frame)
+{
+    bool panid_compression = (p_frame[PAN_ID_COMPR_OFFSET] & PAN_ID_COMPR_MASK) ? true : false;
+
+    switch (frame_version_get(p_frame))
+    {
+        case FRAME_VERSION_0:
+        case FRAME_VERSION_1:
+            if (!dst_addr_is_present(p_frame))
+            {
+                return false;
+            }
+
+            return true;
+
+        case FRAME_VERSION_2:
+        default:
+            if (mac_802154_frame_parser_dst_addr_is_extended(p_frame) &&
+                mac_802154_frame_parser_src_addr_is_extended(p_frame))
+            {
+                return panid_compression ? false : true;
+            }
+
+            if (src_addr_is_present(p_frame) && dst_addr_is_present(p_frame))
+            {
+                return true;
+            }
+
+            if (src_addr_is_present(p_frame))
+            {
+                return false;
+            }
+
+            if (dst_addr_is_present(p_frame))
+            {
+                return panid_compression ? false : true;
+            }
+
+            return panid_compression ? true : false;
+    }
+}
+
+static bool src_panid_is_present(const uint8_t * p_frame)
+{
+    bool panid_compression = (p_frame[PAN_ID_COMPR_OFFSET] & PAN_ID_COMPR_MASK) ? true : false;
+
+    switch (frame_version_get(p_frame))
+    {
+        case FRAME_VERSION_0:
+        case FRAME_VERSION_1:
+            if (!src_addr_is_present(p_frame))
+            {
+                return false;
+            }
+
+            return panid_compression ? false : true;
+
+        case FRAME_VERSION_2:
+        default:
+            if (mac_802154_frame_parser_dst_addr_is_extended(p_frame) &&
+                mac_802154_frame_parser_src_addr_is_extended(p_frame))
+            {
+                return false;
+            }
+
+            if (src_addr_is_present(p_frame) && dst_addr_is_present(p_frame))
+            {
+                return panid_compression ? false : true;
+            }
+
+            if (src_addr_is_present(p_frame))
+            {
+                return panid_compression ? false : true;
+            }
+
+            if (dst_addr_is_present(p_frame))
+            {
+                return false;
+            }
+
+            return false;
+    }
+}
+
+static bool src_panid_is_compressed(const uint8_t * p_frame)
+{
+    return dst_panid_is_present(p_frame) && !src_panid_is_present(p_frame);
+}
+
+// Security
+static bool security_is_enabled(const uint8_t * p_frame)
+{
+    return p_frame[SECURITY_ENABLED_OFFSET] & SECURITY_ENABLED_BIT ? true : false;
+}
+
+static uint8_t security_offset_get(const uint8_t * p_frame)
+{
+    uint8_t dst_addr_offset  = mac_802154_frame_parser_dst_addr_offset_get(p_frame);
+    uint8_t dst_panid_offset = mac_802154_frame_parser_dst_panid_offset_get(p_frame);
+    uint8_t dst_addr_size    = dst_addr_size_get(p_frame);
+    uint8_t src_addr_offset  = mac_802154_frame_parser_src_addr_offset_get(p_frame);
+    uint8_t src_panid_offset = mac_802154_frame_parser_src_panid_offset_get(p_frame);
+    uint8_t src_addr_size    = src_addr_size_get(p_frame);
+
+    if (src_addr_is_present(p_frame))
+    {
+        if ((src_addr_size == MAC_802154_FRAME_PARSER_INVALID_OFFSET) ||
+            (src_addr_offset == MAC_802154_FRAME_PARSER_INVALID_OFFSET))
+        {
+            return MAC_802154_FRAME_PARSER_INVALID_OFFSET;
+        }
+
+        return src_addr_offset + src_addr_size;
+    }
+    else if (src_panid_is_present(p_frame))
+    {
+        if (src_panid_offset == MAC_802154_FRAME_PARSER_INVALID_OFFSET)
+        {
+            return MAC_802154_FRAME_PARSER_INVALID_OFFSET;
+        }
+
+        return src_panid_offset + PAN_ID_SIZE;
+    }
+    else if (dst_addr_offset)
+    {
+        if (dst_addr_size == MAC_802154_FRAME_PARSER_INVALID_OFFSET)
+        {
+            return MAC_802154_FRAME_PARSER_INVALID_OFFSET;
+        }
+
+        return dst_addr_offset + dst_addr_size;
+    }
+    else if (dst_panid_offset)
+    {
+        return dst_panid_offset + PAN_ID_SIZE;
+    }
+    else
+    {
+        return addressing_offset_get(p_frame);
+    }
+}
+
+static uint8_t key_id_size_get(const uint8_t * p_frame)
+{
+    switch (*mac_802154_frame_parser_sec_ctrl_get(p_frame) & KEY_ID_MODE_MASK)
+    {
+        case KEY_ID_MODE_1:
+            return KEY_ID_MODE_1_SIZE;
+
+        case KEY_ID_MODE_2:
+            return KEY_ID_MODE_2_SIZE;
+
+        case KEY_ID_MODE_3:
+            return KEY_ID_MODE_3_SIZE;
+
+        default:
+            return 0;
+    }
+}
+
+// IEs
+
+static uint8_t ie_offset_get(const uint8_t * p_frame)
+{
+    uint8_t security_offset = security_offset_get(p_frame);
+    uint8_t key_id_offset   = mac_802154_frame_parser_key_id_offset_get(p_frame);
+
+    if (!security_is_enabled(p_frame))
+    {
+        if (security_offset == MAC_802154_FRAME_PARSER_INVALID_OFFSET)
+        {
+            return MAC_802154_FRAME_PARSER_INVALID_OFFSET;
+        }
+
+        return security_offset;
+    }
+    else
+    {
+        if (key_id_offset == MAC_802154_FRAME_PARSER_INVALID_OFFSET)
+        {
+            return MAC_802154_FRAME_PARSER_INVALID_OFFSET;
+        }
+
+        return key_id_offset + key_id_size_get(p_frame);
+    }
+}
+
+/***************************************************************************************************
+ * @section Frame format functions
+ **************************************************************************************************/
+
+bool mac_802154_frame_parser_dst_addr_is_extended(const uint8_t * p_frame)
+{
+    return (p_frame[DEST_ADDR_TYPE_OFFSET] & DEST_ADDR_TYPE_MASK) == DEST_ADDR_TYPE_EXTENDED;
+}
+
+bool mac_802154_frame_parser_src_addr_is_extended(const uint8_t * p_frame)
+{
+    return (p_frame[SRC_ADDR_TYPE_OFFSET] & SRC_ADDR_TYPE_MASK) == SRC_ADDR_TYPE_EXTENDED;
+}
+
+bool mac_802154_frame_parser_src_addr_is_short(const uint8_t * p_frame)
+{
+    return (p_frame[SRC_ADDR_TYPE_OFFSET] & SRC_ADDR_TYPE_MASK) == SRC_ADDR_TYPE_SHORT;
+}
+
+bool mac_802154_frame_parser_dsn_suppress_bit_is_set(const uint8_t * p_frame)
+{
+    return (p_frame[DSN_SUPPRESS_OFFSET] & DSN_SUPPRESS_BIT) ? true : false;
+}
+
+bool mac_802154_frame_parser_ie_present_bit_is_set(const uint8_t * p_frame)
+{
+    return (p_frame[IE_PRESENT_OFFSET] & IE_PRESENT_BIT) ? true : false;
+}
+
+bool mac_802154_frame_parser_ar_bit_is_set(const uint8_t * p_frame)
+{
+    return (p_frame[ACK_REQUEST_OFFSET] & ACK_REQUEST_BIT) ? true : false;
+}
+
+/***************************************************************************************************
+ * @section Offset functions
+ **************************************************************************************************/
+
+uint8_t mac_802154_frame_parser_dst_panid_offset_get(const uint8_t * p_frame)
+{
+    if (dst_panid_is_present(p_frame))
+    {
+        return addressing_offset_get(p_frame);
+    }
+    else
+    {
+        return 0;
+    }
+}
+
+uint8_t mac_802154_frame_parser_dst_addr_offset_get(const uint8_t * p_frame)
+{
+    uint8_t dst_panid_offset = mac_802154_frame_parser_dst_panid_offset_get(p_frame);
+
+    if (dst_addr_is_present(p_frame))
+    {
+        return 0 ==
+               dst_panid_offset ? addressing_offset_get(p_frame) : dst_panid_offset + PAN_ID_SIZE;
+    }
+    else
+    {
+        return 0;
+    }
+}
+
+uint8_t mac_802154_frame_parser_dst_addr_end_offset_get(const uint8_t * p_frame)
+{
+    uint8_t offset        = addressing_offset_get(p_frame);
+    uint8_t dst_addr_size = dst_addr_size_get(p_frame);
+
+    if (dst_addr_size == MAC_802154_FRAME_PARSER_INVALID_OFFSET)
+    {
+        return MAC_802154_FRAME_PARSER_INVALID_OFFSET;
+    }
+
+    if (dst_panid_is_present(p_frame))
+    {
+        offset += PAN_ID_SIZE;
+    }
+
+    offset += dst_addr_size;
+
+    return offset;
+}
+
+uint8_t mac_802154_frame_parser_src_panid_offset_get(const uint8_t * p_frame)
+{
+    uint8_t dst_addr_offset  = mac_802154_frame_parser_dst_addr_offset_get(p_frame);
+    uint8_t dst_panid_offset = mac_802154_frame_parser_dst_panid_offset_get(p_frame);
+    uint8_t dst_addr_size    = dst_addr_size_get(p_frame);
+
+    if (src_panid_is_present(p_frame))
+    {
+        if (dst_addr_offset)
+        {
+            if (dst_addr_size == MAC_802154_FRAME_PARSER_INVALID_OFFSET)
+            {
+                return MAC_802154_FRAME_PARSER_INVALID_OFFSET;
+            }
+
+            return dst_addr_offset + dst_addr_size;
+        }
+        else if (dst_panid_offset)
+        {
+            return dst_panid_offset + PAN_ID_SIZE;
+        }
+        else
+        {
+            return addressing_offset_get(p_frame);
+        }
+    }
+    else if (src_panid_is_compressed(p_frame))
+    {
+        return mac_802154_frame_parser_dst_panid_offset_get(p_frame);
+    }
+    else
+    {
+        return 0;
+    }
+}
+
+uint8_t mac_802154_frame_parser_src_addr_offset_get(const uint8_t * p_frame)
+{
+    uint8_t dst_addr_offset  = mac_802154_frame_parser_dst_addr_offset_get(p_frame);
+    uint8_t dst_panid_offset = mac_802154_frame_parser_dst_panid_offset_get(p_frame);
+    uint8_t dst_addr_size    = dst_addr_size_get(p_frame);
+    uint8_t src_panid_offset = mac_802154_frame_parser_src_panid_offset_get(p_frame);
+
+    if (src_addr_is_present(p_frame))
+    {
+        if (src_panid_is_present(p_frame))
+        {
+            if (src_panid_offset == MAC_802154_FRAME_PARSER_INVALID_OFFSET)
+            {
+                return MAC_802154_FRAME_PARSER_INVALID_OFFSET;
+            }
+
+            return src_panid_offset + PAN_ID_SIZE;
+        }
+        else if (dst_addr_offset)
+        {
+            if (dst_addr_size == MAC_802154_FRAME_PARSER_INVALID_OFFSET)
+            {
+                return MAC_802154_FRAME_PARSER_INVALID_OFFSET;
+            }
+
+            return dst_addr_offset + dst_addr_size;
+        }
+        else if (dst_panid_offset)
+        {
+            return dst_panid_offset + PAN_ID_SIZE;
+        }
+        else
+        {
+            return addressing_offset_get(p_frame);
+        }
+    }
+    else
+    {
+        return 0;
+    }
+}
+
+uint8_t mac_802154_frame_parser_addressing_end_offset_get(const uint8_t * p_frame)
+{
+    return security_offset_get(p_frame);
+}
+
+uint8_t mac_802154_frame_parser_sec_ctrl_offset_get(const uint8_t * p_frame)
+{
+    if (!security_is_enabled(p_frame))
+    {
+        return 0;
+    }
+    else
+    {
+        return security_offset_get(p_frame);
+    }
+}
+
+uint8_t mac_802154_frame_parser_key_id_offset_get(const uint8_t * p_frame)
+{
+    uint8_t sec_ctrl_offset = mac_802154_frame_parser_sec_ctrl_offset_get(p_frame);
+
+    if (0 == sec_ctrl_offset)
+    {
+        return 0;
+    }
+
+    if (MAC_802154_FRAME_PARSER_INVALID_OFFSET == sec_ctrl_offset)
+    {
+        return MAC_802154_FRAME_PARSER_INVALID_OFFSET;
+    }
+
+    if (p_frame[sec_ctrl_offset] & FRAME_COUNTER_SUPPRESS_BIT)
+    {
+        return sec_ctrl_offset + SECURITY_CONTROL_SIZE;
+    }
+    else
+    {
+        return sec_ctrl_offset + SECURITY_CONTROL_SIZE + FRAME_COUNTER_SIZE;
+    }
+}
+
+uint8_t mac_802154_frame_parser_ie_header_offset_get(const uint8_t * p_frame)
+{
+    if (!mac_802154_frame_parser_ie_present_bit_is_set(p_frame))
+    {
+        return 0;
+    }
+    else
+    {
+        return ie_offset_get(p_frame);
+    }
+}
+
+/***************************************************************************************************
+ * @section Get functions
+ **************************************************************************************************/
+
+const uint8_t * mac_802154_frame_parser_dst_addr_get(const uint8_t * p_frame,
+                                                     bool          * p_dst_addr_extended)
+{
+    uint8_t dst_addr_offset = mac_802154_frame_parser_dst_addr_offset_get(p_frame);
+
+    if ((0 == dst_addr_offset) || (MAC_802154_FRAME_PARSER_INVALID_OFFSET == dst_addr_offset))
+    {
+        *p_dst_addr_extended = false;
+        return NULL;
+    }
+    else
+    {
+        *p_dst_addr_extended = mac_802154_frame_parser_dst_addr_is_extended(p_frame);
+        return &p_frame[dst_addr_offset];
+    }
+}
+
+const uint8_t * mac_802154_frame_parser_dst_panid_get(const uint8_t * p_frame)
+{
+    uint8_t dst_panid_offset = mac_802154_frame_parser_dst_panid_offset_get(p_frame);
+
+    return ((0 == dst_panid_offset) || (MAC_802154_FRAME_PARSER_INVALID_OFFSET == dst_panid_offset))
+           ? NULL : &p_frame[dst_panid_offset];
+}
+
+const uint8_t * mac_802154_frame_parser_src_panid_get(const uint8_t * p_frame)
+{
+    uint8_t src_panid_offset = mac_802154_frame_parser_src_panid_offset_get(p_frame);
+
+    return ((0 == src_panid_offset) || (MAC_802154_FRAME_PARSER_INVALID_OFFSET == src_panid_offset))
+           ? NULL : &p_frame[src_panid_offset];
+}
+
+const uint8_t * mac_802154_frame_parser_src_addr_get(const uint8_t * p_frame,
+                                                     bool          * p_src_addr_extended)
+{
+    uint8_t src_addr_offset = mac_802154_frame_parser_src_addr_offset_get(p_frame);
+
+    if ((0 == src_addr_offset) || (MAC_802154_FRAME_PARSER_INVALID_OFFSET == src_addr_offset))
+    {
+        *p_src_addr_extended = false;
+        return NULL;
+    }
+    else
+    {
+        *p_src_addr_extended = mac_802154_frame_parser_src_addr_is_extended(p_frame);
+        return &p_frame[src_addr_offset];
+    }
+}
+
+bool mac_802154_frame_parser_mhr_parse(const uint8_t                      * p_frame,
+                                       mac_802154_frame_parser_mhr_data_t * p_fields)
+{
+    uint8_t offset               = addressing_offset_get(p_frame);
+    bool    is_dst_panid_present = dst_panid_is_present(p_frame);
+    bool    is_src_panid_present = src_panid_is_present(p_frame);
+
+    if (is_dst_panid_present)
+    {
+        p_fields->p_dst_panid = &p_frame[offset];
+        offset               += PAN_ID_SIZE;
+    }
+    else
+    {
+        p_fields->p_dst_panid = NULL;
+    }
+
+    if (dst_addr_is_present(p_frame))
+    {
+        p_fields->p_dst_addr    = &p_frame[offset];
+        p_fields->dst_addr_size = dst_addr_size_get(p_frame);
+        offset                 += (p_fields->dst_addr_size);
+
+        if (p_fields->dst_addr_size == MAC_802154_FRAME_PARSER_INVALID_OFFSET)
+        {
+            return false;
+        }
+    }
+    else
+    {
+        p_fields->p_dst_addr    = NULL;
+        p_fields->dst_addr_size = 0;
+    }
+
+    if (is_src_panid_present)
+    {
+        p_fields->p_src_panid = &p_frame[offset];
+        offset               += PAN_ID_SIZE;
+    }
+    else if (is_dst_panid_present)
+    {
+        p_fields->p_src_panid = p_fields->p_dst_panid;
+    }
+    else
+    {
+        p_fields->p_src_panid = NULL;
+    }
+
+    if (src_addr_is_present(p_frame))
+    {
+        p_fields->p_src_addr    = &p_frame[offset];
+        p_fields->src_addr_size = src_addr_size_get(p_frame);
+        offset                 += (p_fields->src_addr_size);
+
+        if (p_fields->src_addr_size == MAC_802154_FRAME_PARSER_INVALID_OFFSET)
+        {
+            return false;
+        }
+    }
+    else
+    {
+        p_fields->p_src_addr    = NULL;
+        p_fields->src_addr_size = 0;
+    }
+
+    p_fields->addressing_end_offset = offset;
+
+    if (security_is_enabled(p_frame))
+    {
+        p_fields->p_sec_ctrl = &p_frame[offset];
+        // TODO increment offset...
+    }
+    else
+    {
+        p_fields->p_sec_ctrl = NULL;
+    }
+
+    return true;
+}
+
+const uint8_t * mac_802154_frame_parser_sec_ctrl_get(const uint8_t * p_frame)
+{
+    uint8_t sec_ctrl_offset = mac_802154_frame_parser_sec_ctrl_offset_get(p_frame);
+
+    return ((0 == sec_ctrl_offset) || (MAC_802154_FRAME_PARSER_INVALID_OFFSET == sec_ctrl_offset)) ?
+           NULL : &p_frame[sec_ctrl_offset];
+}
+
+const uint8_t * mac_802154_frame_parser_key_id_get(const uint8_t * p_frame)
+{
+    uint8_t key_id_offset = mac_802154_frame_parser_key_id_offset_get(p_frame);
+
+    return ((0 == key_id_offset) || (MAC_802154_FRAME_PARSER_INVALID_OFFSET == key_id_offset)) ?
+           NULL : &p_frame[key_id_offset];
+}
+
+const uint8_t * mac_802154_frame_parser_ie_header_get(const uint8_t * p_frame)
+{
+    uint8_t ie_header_offset = mac_802154_frame_parser_ie_header_offset_get(p_frame);
+
+    if ((0 == ie_header_offset) || (MAC_802154_FRAME_PARSER_INVALID_OFFSET == ie_header_offset))
+    {
+        return NULL;
+    }
+
+    return &p_frame[ie_header_offset];
+}
diff --git a/bee/drivers/mac_802154/src/mac_802154_xip.c b/bee/drivers/mac_802154/src/mac_802154_xip.c
new file mode 100644
index 00000000..8cb9b2d5
--- /dev/null
+++ b/bee/drivers/mac_802154/src/mac_802154_xip.c
@@ -0,0 +1,457 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <string.h>
+#include <stdlib.h>
+#include "rtl876x.h"
+#include "mac_driver.h"
+#include "mac_reg.h"
+#include "mac_reg_type.h"
+#include "trace.h"
+
+/*============================================================================*
+ *                              mac driver patch begin
+ *============================================================================*/
+
+extern pmac_driver_t pmac_driver;
+extern volatile uint64_t bt_clk_offset;
+extern void mac_EDScanProcess_rom(void);
+
+typedef void (*bt_hci_reset_handler_t)(void);
+static bt_hci_reset_handler_t bt_rci_reset_handler = NULL;
+
+static uint16_t saved_shortaddr = 0;
+static uint8_t saved_extaddr[8];
+
+void mac_RegisterBtHciResetHandler(bt_hci_reset_handler_t handler)
+{
+    bt_rci_reset_handler = handler;
+}
+
+bool_t mac_GrantPHYStatus(void)
+{
+    if (pmac_driver->mac_attribute.phy_arbitration_en)
+    {
+        return MAC->phy_arb_ctrl_b.zbrf_gnt_sts;
+    }
+    else
+    {
+        return true;
+    }
+}
+
+bool mac_GetTxNTermedStatus(void)
+{
+    return MAC->tx_term_sts_b.zbrf_normal_tx_termed ? true : false;
+}
+
+bool mac_GetTxEnhAckTermedStatus(void)
+{
+    return MAC->tx_term_sts_b.zbrf_gts1_tx_termed ? true : false;
+}
+
+static void mac_PHYGrantIntHandler_Patch(mac_isrsts_t isrsts)
+{
+    uint32_t gnt;
+    if (MAC->phy_arb_ctrl_b.zbrf_gnt_sts == 0)
+    {
+        //pmac_driver->mac_radio_state = MAC_RADIO_STATE_W4PHYGNT;
+    }
+    else
+    {
+        //pmac_driver->mac_radio_state = MAC_RADIO_STATE_RX;
+#if 1
+        MAC->rfctl_b.rfrst = 1;
+        while (MAC->mac_rf_state_b.radio_cst);
+        MAC->rfctl_b.rfrst = 0;
+        if (pmac_driver->txntrig_saved.w > 0)
+        {
+            MAC->txn_trig = pmac_driver->txntrig_saved.w;
+        }
+#endif
+    }
+}
+
+void Zigbee_Handler_Patch(void)
+{
+    mac_isrsts_t isrsts;
+
+    isrsts.w = MAC->isrsts;
+    pmac_driver->IntIn.w ^= isrsts.w;
+    MAC->isrsts = isrsts.w; // write 1 to clear interrupt
+
+    if (isrsts.w & MAC_intmsk_btcmp3msk_Msk)
+    {
+        mac_bt_clk_t bt_clk;
+
+        *((uint32_t *)&bt_clk) = 0;
+        mac_SetBTClkInt(BT_CLK_OVFLW_WATCH_TIMER, &bt_clk);
+        bt_clk_offset += MAX_BT_CLOCK_COUNTER;
+    }
+
+    if (isrsts.b.gntif)
+    {
+        // PHY grant interrupt
+        mac_PHYGrantIntHandler_Patch(isrsts);
+    }
+
+    {
+        if (isrsts.b.txnterrif)
+        {
+            if (pmac_driver->txntrig_saved.w > 0)
+            {
+                // txn
+                pmac_driver->txntrig_saved.w = 0;
+            }
+        }
+
+        if (isrsts.b.txnif)
+        {
+            if (pmac_driver->txntrig_saved.w > 0)
+            {
+                pmac_driver->txntrig_saved.w = 0;
+            }
+            else
+            {
+                // upper layer encryption
+                isrsts.b.txnif = 0;
+            }
+        }
+
+        if (isrsts.b.txg1if)
+        {
+            // toggle nocsmag bit to reset GTS1/GTS2 TX switching
+            MAC->gts_ctrl_b.nocsmag = 0;
+            MAC->gts_ctrl_b.nocsmag = 1;
+        }
+
+        if (isrsts.b.txg2if)
+        {
+        }
+    }
+
+    if (isrsts.b.edscanif)
+    {
+        // ED scan done interrupt
+        //mac_EDScanProcess_rom();
+    }
+
+    if (pmac_driver->mac_intr_cb)
+    {
+        pmac_driver->mac_intr_cb(isrsts.w);
+    }
+}
+
+uint8_t mac_LoadTxNPayload_patch(uint8_t HdrL, uint8_t FrmL, uint8_t *TxFIFO)
+{
+    pmac_txfifo_t pTxNFIFO = (pmac_txfifo_t)((uint32_t)(MAC->txn_fifo));
+
+    // max data length is 125
+    if ((FrmL > MAC_MAX_TX_FRM_LEN) || (FrmL < MAC_MIN_TX_FRM_LEN))
+    {
+        return MAC_STS_DATA_LEN_ERROR;
+    }
+
+    pTxNFIFO->hdr_len = HdrL; //write header length into tx normal fifo
+    pTxNFIFO->frm_len = FrmL; //write frame length into tx normal fifo
+    mac_memcpy((void *)pTxNFIFO->payload, TxFIFO, FrmL); //write data into tx normal fifo
+
+    return MAC_STS_SUCCESS;
+}
+
+void mac_TrigUpperEnc_patch(void)
+{
+    mac_txn_trig_t txntrig;
+    txntrig.w = 0;
+    txntrig.b.txnsecen = 1;
+    txntrig.b.txntrig = 1;
+    MAC->sec_upper_ctrl_b.upenc = 1; //enable upper cipher mode
+    MAC->sec_proc_sts_b.sec_enc_done = 1; // clear encryption done status
+    MAC->txn_trig = txntrig.w; // trigger secure process, txnsecen & txntrig must write simultaneously
+    while (0 == MAC->sec_proc_sts_b.sec_enc_done); //wait encryption is done
+    MAC->sec_upper_ctrl_b.upenc = 0;
+    txntrig.b.txnsecen = 0;
+    txntrig.b.txntrig = 0;
+}
+
+uint8_t  mac_TrigTxN_patch(bool_t AckReq, bool_t SecReq, bool_t Is2015)
+{
+    mac_txn_trig_t txntrig;
+
+    txntrig.w = 0;
+
+    if (SecReq)
+    {
+        txntrig.b.txnsecen = 1;
+    }
+
+    if (AckReq)
+    {
+        txntrig.b.txnackreq = 1;
+        txntrig.b.ack_type = Is2015;
+    }
+
+    txntrig.b.txntrig = 1;
+    //mac_EnterCritical_rom();
+    pmac_driver->IntProc.b.txnif = pmac_driver->IntIn.b.txnif;  // update TX processing toggle bit
+    pmac_driver->txntrig_saved.w = txntrig.w;
+    if (mac_GrantPHYStatus())
+    {
+        MAC->txn_trig = pmac_driver->txntrig_saved.w;
+    }
+    //mac_ExitCritical_rom();
+    return (uint8_t)MAC_STS_SUCCESS;
+}
+
+uint8_t mac_TrigTxNAtTime_patch(bool_t AckReq, bool_t SecReq, bool_t Is2015, uint32_t time_us)
+{
+    mac_bt_clk_t TxTime;
+    mac_USToBTClk(time_us, &TxTime);
+
+    mac_txn_trig_t txntrig;
+    mac_tx_given_time_set_t tx_given_time_set;
+    int32_t bt_clk_cntr;
+
+    txntrig.w = 0;
+
+    if (SecReq)
+    {
+        txntrig.b.txnsecen = 1;
+    }
+
+    if (AckReq)
+    {
+        txntrig.b.txnackreq = 1;
+        txntrig.b.ack_type = Is2015;
+    }
+
+    // to compansate PHY TX Settling time, TX trigger earlier
+    bt_clk_cntr = BT_SLOT_TIME_US - TxTime.bt_clk_counter;
+    bt_clk_cntr -= (int32_t)(pmac_driver->tagt_no_cca_trig_tim);
+
+    while (bt_clk_cntr < 0)
+    {
+        TxTime.bt_native_clk--;
+        bt_clk_cntr += BT_SLOT_TIME_US;
+    }
+    TxTime.bt_clk_counter = BT_SLOT_TIME_US - bt_clk_cntr;
+
+    tx_given_time_set.w = 0;
+    tx_given_time_set.b.txn_nclk = TxTime.bt_native_clk;
+    tx_given_time_set.b.txn_ckc = TxTime.bt_clk_counter;
+    tx_given_time_set.b.schtxnocca = 1;
+    tx_given_time_set.b.txntmren = 1;
+    //mac_EnterCritical_rom();
+    pmac_driver->IntProc.b.txnif = pmac_driver->IntIn.b.txnif;  // update TX processing toggle bit
+    pmac_driver->txntrig_saved.w = txntrig.w;
+    pmac_driver->tx_given_time_set_saved.w = tx_given_time_set.w;
+    MAC->txn_trig = pmac_driver->txntrig_saved.w;
+    MAC->tx_given_time_set = pmac_driver->tx_given_time_set_saved.w;
+    //mac_ExitCritical_rom();
+
+    return (uint8_t)MAC_STS_SUCCESS;
+}
+
+uint8_t  mac_TrigTxEnhAck_patch(bool_t early, bool_t SecReq)
+{
+    while (MAC->txm_state_b.gts_state > 0)
+    {
+        __NOP();
+    }
+
+    mac_gts_ctrl_t enh_ack_trig;
+
+    enh_ack_trig.w = MAC->gts_ctrl & ~(MAC_gts_ctrl_enh_ack_trig_Msk | MAC_gts_ctrl_sec_enh_ack_Msk);
+
+    if (SecReq)
+    {
+        enh_ack_trig.b.sec_enh_ack = 1;
+    }
+    enh_ack_trig.b.enh_ack_trig = 1;
+
+    if (early)
+    {
+        MAC->gts_ctrl = enh_ack_trig.w;
+        return MAC_STS_SUCCESS;
+    }
+    else
+    {
+        if (MAC->tx_enh_ack_ctrl_b.gts_enh_ack_trig_en)
+        {
+            if (mac_GrantPHYStatus())
+            {
+                MAC->gts_ctrl = enh_ack_trig.w;
+                return MAC_STS_SUCCESS;
+            }
+            else
+            {
+                return MAC_STS_PENDING;
+            }
+        }
+        else
+        {
+            return MAC_STS_TIMEOUT;
+        }
+    }
+}
+
+void mac_TrigMacTmr(void)
+{
+    MAC->mac_timer_b.mactmr_h = 0x00;
+    MAC->mac_timer_b.mactmr_l = 0x01;
+}
+
+void mac_RxInfo(uint8_t *p_len, mac_rxfifo_tail_t *p_rxfifo_tail)
+{
+    uint8_t len;
+    MAC->rx_fifo_ctrl_b.rxffwr = 1;  // enable FW RX FIFO access
+    len = MAC->rx_fifo[0];
+    *p_len = len;
+    mac_memcpy(p_rxfifo_tail, &MAC->rx_fifo[len], 7);
+    MAC->rx_fifo_ctrl_b.rxffwr = 0;  // disable FW RX FIFO access
+}
+
+void mac_RxPayload(uint8_t len, uint8_t *payload)
+{
+    MAC->rx_fifo_ctrl_b.rxffwr = 1;  // enable FW RX FIFO access
+    mac_memcpy(payload, &MAC->rx_fifo[1], len);
+    MAC->rx_fifo_ctrl_b.rxffwr = 0;  // disable FW RX FIFO access
+}
+
+bool mac_GetPendingBit(void)
+{
+    return MAC->tx_ctrl_b.pend;
+}
+
+void mac_SetPendingBit(bool pending)
+{
+    MAC->tx_ctrl_b.pend = pending;
+}
+
+void mac_SetAddrMatchMode_patch(uint8_t mode)
+{
+    mac_src_addr_filter_ctrl_t mac_src_addr_filter_ctrl;
+
+    mac_src_addr_filter_ctrl.w = MAC->src_addr_filter_ctrl;
+    if (mode == AUTO_ACK_PENDING_MODE_THREAD)
+    {
+        mac_src_addr_filter_ctrl.b.enh_frmpend_en = 1;
+        mac_src_addr_filter_ctrl.b.pending_ack = 0;
+        mac_src_addr_filter_ctrl.b.datreq_cmd_pending_ack = 0;
+    }
+    else
+    {
+        mac_src_addr_filter_ctrl.b.enh_frmpend_en = 0;
+        mac_src_addr_filter_ctrl.b.pending_ack = 0;
+        mac_src_addr_filter_ctrl.b.datreq_cmd_pending_ack = 0;
+    }
+    MAC->src_addr_filter_ctrl = mac_src_addr_filter_ctrl.w;
+}
+
+void __wrap_mac_EnterCritical_rom(void)
+{
+    __NOP();
+}
+
+void __wrap_mac_ExitCritical_rom(void)
+{
+    __NOP();
+}
+
+void __wrap_mac_RstRF_rom(void)
+{
+    if (mac_GrantPHYStatus())
+    {
+        MAC->rfctl_b.rfrst = 1;
+        while (MAC->mac_rf_state_b.radio_cst);
+        MAC->rfctl_b.rfrst = 0;
+    }
+    else
+    {
+        while (!mac_GrantPHYStatus());
+    }
+}
+
+/*============================================================================*
+ *                              mac driver patch end
+ *============================================================================*/
+
+uint32_t get_zigbee_window_slot_imp(int16_t *prio, int16_t *prio_min)
+{
+    return (pmac_driver->mac_attribute.mac_cfg.anch_jump_val - 1);
+}
+
+#define SYSCALL_STACK_NONE 0
+#define SYSCALL_STACK_HCI_RESET_ENTER 1
+#define SYSCALL_STACK_HCI_RESET_EXIT 2
+
+extern bool (*patch_SystemCall_Zigbee_Stack)(uint32_t opcode);
+
+bool patch_SystemCall_Zigbee_Stack_imp(uint32_t opcode)
+{
+    switch (opcode)
+    {
+        case SYSCALL_STACK_HCI_RESET_ENTER:
+        mac_memcpy(saved_extaddr, &MAC->eadr_l, 8);
+        saved_shortaddr = MAC->sadr;
+        break;
+
+        case SYSCALL_STACK_HCI_RESET_EXIT:
+        bt_rci_reset_handler();
+        mac_SetLongAddress(saved_extaddr);
+        mac_SetShortAddress(saved_shortaddr);
+        break;
+
+        default:
+        break;
+    }
+}
+
+void mac_Initialize_Patch(void)
+{
+    patch_SystemCall_Zigbee_Stack = patch_SystemCall_Zigbee_Stack_imp;
+}
+
+//++++++++++++++++++++++++++++++++++++++++++++++++
+// mac driver
+//++++++++++++++++++++++++++++++++++++++++++++++++
+
+void mac_Initialize_Additional(void)
+{
+    MAC->clk_ctrl_b.engts = 1;          // patch: enable GTS TXM clock
+    MAC->seccr0_b.disdec = 1;
+    MAC->rxfrmtype_b.rxftype = 0x0f;
+    MAC->tx_enh_ack_ctrl_b.gts_enh_ack_timer = 0xc0;
+    mac_SetTXPower(8);                  // set TX power = 4 dBm (max)
+    mac_Initialize_Patch();
+}
+
+void mac_SetTxNCsma(bool enable)
+{
+    MAC->csma_ctrl_b.nocsman = enable ? 0 : 1;
+}
+
+uint32_t mac_BackoffDelay(void)
+{
+    uint32_t backoff = MAC->dbg_reg0_b.sh_back & 0xf;
+    if (backoff < 8)
+    {
+        backoff = 8;
+    }
+    return (320 * backoff);
+}
+
+uint32_t mac_GetTxMStatus(void)
+{
+    return MAC->txm_status;
+}
+
+uint32_t mac_GetTxAtStatus(void)
+{
+    return MAC->tx_given_time_status;
+}
+
+//------------------------------------------------
diff --git a/bee/drivers/pinmux/CMakeLists.txt b/bee/drivers/pinmux/CMakeLists.txt
new file mode 100644
index 00000000..be8712ba
--- /dev/null
+++ b/bee/drivers/pinmux/CMakeLists.txt
@@ -0,0 +1,6 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+add_subdirectory(inc)
+
+add_subdirectory_ifdef(CONFIG_REALTEK_BEE_PINMUX src)
diff --git a/bee/drivers/pinmux/Kconfig b/bee/drivers/pinmux/Kconfig
new file mode 100644
index 00000000..168a4331
--- /dev/null
+++ b/bee/drivers/pinmux/Kconfig
@@ -0,0 +1,8 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config REALTEK_BEE_PINMUX
+	bool "Realtek Bee PINMUX driver"
+	default n
+	help
+	  This option enables the PINMUX driver for Realtek Bee.
diff --git a/bee/drivers/pinmux/inc/CMakeLists.txt b/bee/drivers/pinmux/inc/CMakeLists.txt
new file mode 100644
index 00000000..0519bcd1
--- /dev/null
+++ b/bee/drivers/pinmux/inc/CMakeLists.txt
@@ -0,0 +1,9 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+if(CONFIG_REALTEK_BEE_COMMON_DRIVER)
+    zephyr_include_directories(${CMAKE_CURRENT_SOURCE_DIR})
+endif()
+
+add_soc_series_subdir(rtl87x2g)
+add_soc_series_subdir(rtl87x2j)
diff --git a/bee/drivers/pinmux/inc/rtl87x2g/pin_def.h b/bee/drivers/pinmux/inc/rtl87x2g/pin_def.h
new file mode 100644
index 00000000..453a9348
--- /dev/null
+++ b/bee/drivers/pinmux/inc/rtl87x2g/pin_def.h
@@ -0,0 +1,152 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *               Define to prevent recursive inclusion
+ *============================================================================*/
+#ifndef PIN_DEF_H
+#define PIN_DEF_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** \defgroup PIN_DEFINE       PIN DEFINE
+  * \brief
+  * \{
+  */
+
+/*============================================================================*
+ *                         RTL87x2G Pin Number
+ *============================================================================*/
+/** \defgroup Pin_Number       Pin Number
+  * \brief
+  * \{
+  */
+
+#define P0_0        0       /*!< GPIOA_0  */
+#define P0_1        1       /*!< GPIOA_1  */
+#define P0_2        2       /*!< GPIOA_2  */
+#define P0_3        3       /*!< GPIOA_3  */
+#define P0_4        4       /*!< GPIOA_4  */
+#define P0_5        5       /*!< GPIOA_5  */
+#define P0_6        6       /*!< GPIOA_6  */
+#define P0_7        7       /*!< GPIOA_7  */
+
+#define P1_0        8       /*!< GPIOA_8  */
+#define P1_1        9       /*!< GPIOA_9  */
+#define P1_2        10      /*!< GPIOA_10 */
+#define P1_3        11      /*!< GPIOA_11 */
+#define P1_4        12      /*!< GPIOA_12 */
+#define P1_5        13      /*!< GPIOA_13 */
+#define P1_6        14      /*!< GPIOA_14 */
+#define P1_7        15      /*!< GPIOA_15 */
+
+#define P2_0        16      /*!< GPIOA_21 */
+#define P2_1        17      /*!< GPIOA_22 */
+#define P2_2        18      /*!< GPIOA_23 */
+#define P2_3        19      /*!< GPIOA_24 */
+#define P2_4        20      /*!< GPIOA_25 */
+#define P2_5        21      /*!< GPIOA_26 */
+#define P2_6        22      /*!< GPIOA_27 */
+#define P2_7        23      /*!< GPIOA_28 */
+
+#define P3_0        24      /*!< GPIOA_29 */
+#define P3_1        25      /*!< GPIOA_30 */
+#define P3_2        26      /*!< GPIOA_31 */
+#define P3_3        27      /*!< GPIOB_0 */
+#define P3_4        28      /*!< GPIOB_1 */
+#define P3_5        29      /*!< GPIOB_2 */
+#define P3_6        30      /*!< GPIOB_3 */
+#define P3_7        31      /*!< GPIOB_4 */
+
+#define P4_0        32      /*!< GPIOB_5  */
+#define P4_1        33      /*!< GPIOB_6  */
+#define P4_2        34      /*!< GPIOB_7  */
+#define P4_3        35      /*!< GPIOB_8  */
+#define P4_4        36      /*!< GPIOB_9  */
+#define P4_5        37      /*!< GPIOB_10  */
+#define P4_6        38      /*!< GPIOB_11  */
+#define P4_7        39      /*!< GPIOB_12  */
+
+#define P5_0        40      /*!< GPIOB_13  */
+#define P5_1        41      /*!< GPIOB_14  */
+#define P5_2        42      /*!< GPIOB_15 */
+#define P5_3        43      /*!< GPIOB_16 */
+#define P5_4        44      /*!< GPIOB_17 */
+#define P5_5        45      /*!< GPIOB_18 */
+#define P5_6        46      /*!< GPIOB_19 */
+#define P5_7        47      /*!< GPIOB_20 */
+
+#define P6_0        48      /*!< GPIOB_19 */
+#define P6_1        49      /*!< GPIOB_20 */
+#define P6_2        50      /*!< GPIOB_21 */
+#define P6_3        51      /*!< GPIOB_22 */
+#define P6_4        52      /*!< GPIOB_23 */
+#define P6_5        53      /*!< GPIOB_24 */
+#define P6_6        54      /*!< GPIOB_25 */
+#define P6_7        55      /*!< GPIOB_26 */
+
+#define P7_0        56      /*!< GPIOB_27 */
+#define P7_1        57      /*!< GPIOB_28 */
+#define P7_2        58      /*!< GPIOB_29 */
+#define P7_3        59      /*!< GPIOB_30 */
+#define P7_4        60      /*!< GPIOB_31 */
+
+//#define P7_5        61      /*!< RSVD */
+//#define P7_6        62      /*!< RSVD */
+//#define P7_7        63      /*!< RSVD */
+
+#define MICBIAS     64      /*!< P8_0 GPIOA_16*/
+#define XI32K       65      /*!< P8_1 GPIOA_17*/
+#define XO32K       66      /*!< P8_2 GPIOA_18*/
+#define DACP        67      /*!< P8_3 GPIOA_19*/
+#define DACN        68      /*!< P8_4 GPIOA_20*/
+
+//#define P8_5        69      /*!< RSVD */
+//#define P8_6        70      /*!< RSVD */
+//#define P8_7        71      /*!< RSVD */
+
+#define P9_0        72      /*!< GPIOB_21 */
+#define P9_1        73      /*!< GPIOB_22 */
+#define P9_2        74      /*!< GPIOB_23 */
+#define P9_3        75      /*!< GPIOB_24 */
+#define P9_4        76      /*!< GPIOB_25 */
+#define P9_5        77      /*!< GPIOB_26 */
+#define P9_6        78      /*!< GPIOB_27 */
+#define P9_7        79      /*!< GPIOB_28 */
+
+#define P10_0       80      /*!< GPIOB_29 */
+#define P10_1       81      /*!< GPIOB_30 */
+#define P10_2       82      /*!< GPIOB_31 */
+
+#define ADC_0       P2_0    /*!< GPIO16   */
+#define ADC_1       P2_1    /*!< GPIO17   */
+#define ADC_2       P2_2    /*!< GPIO18   */
+#define ADC_3       P2_3    /*!< GPIO19   */
+#define ADC_4       P2_4    /*!< GPIO20   */
+#define ADC_5       P2_5    /*!< GPIO21   */
+#define ADC_6       P2_6    /*!< GPIO22   */
+#define ADC_7       P2_7    /*!< GPIO23   */
+
+#define TOTAL_PIN_NUM         (83)                       //!< Specify the maximum pin number.
+#define IS_PIN_NUMBER(NUMBER) ((NUMBER) < TOTAL_PIN_NUM) //!< Check if the input parameter is valid.
+
+/** End of Pin_Number
+  * \}
+  */
+
+/** End of PIN DEFINE
+  * \}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PIN_DEF_H */
+
+
diff --git a/bee/drivers/pinmux/inc/rtl87x2j/pin_def.h b/bee/drivers/pinmux/inc/rtl87x2j/pin_def.h
new file mode 100644
index 00000000..392b9c77
--- /dev/null
+++ b/bee/drivers/pinmux/inc/rtl87x2j/pin_def.h
@@ -0,0 +1,108 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *               Define to prevent recursive inclusion
+ *============================================================================*/
+#ifndef PIN_DEF_H
+#define PIN_DEF_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** \defgroup PIN_DEFINE       PIN DEFINE
+  * \brief
+  * \{
+  */
+
+/*============================================================================*
+ *                         Pin Number
+ *============================================================================*/
+/** \defgroup Pin_Number       Pin Number
+  * \brief
+  * \{
+  */
+
+/******************* Reference: Bee5_pin_mux_20250117A-bitfile0305.xlsx *******************/
+#define P0_0                         0         /*!< GPIO_0 */
+#define P0_1                         1         /*!< GPIO_1 */
+#define P0_2                         2         /*!< GPIO_2 */
+#define P0_3                         3         /*!< GPIO_3 */
+#define P0_4                         4         /*!< GPIO_4 */
+#define P0_5                         5         /*!< GPIO_5 */
+#define P0_6                         6         /*!< GPIO_6 */
+#define P0_7                         7         /*!< GPIO_7 */
+#define P1_0                         8         /*!< GPIO_8 */
+#define P1_1                         9         /*!< GPIO_9 */
+#define P1_6                         10        /*!< GPIO_10 */
+#define P1_7                         11        /*!< GPIO_11 */
+#define P2_0                         12        /*!< GPIO_12 */
+#define P2_1                         13        /*!< GPIO_13 */
+#define P2_2                         14        /*!< GPIO_14 */
+#define P2_3                         15        /*!< GPIO_15 */
+#define P2_4                         16        /*!< GPIO_16 */
+#define P2_5                         17        /*!< GPIO_17 */
+#define P2_6                         18        /*!< GPIO_18 */
+#define P2_7                         19        /*!< GPIO_19 */
+#define P3_0                         20        /*!< GPIO_20 */
+#define P3_1                         21        /*!< GPIO_21 */
+#define P3_2                         22        /*!< GPIO_22 */
+#define P3_3                         23        /*!< GPIO_23 */
+#define P3_4                         24        /*!< GPIO_24 */
+#define P3_5                         25        /*!< GPIO_25 */
+#define P3_6                         26        /*!< GPIO_26 */
+#define P4_0                         27        /*!< GPIO_27 */
+#define P4_1                         28        /*!< GPIO_28 */
+#define P4_2                         29        /*!< GPIO_29 */
+#define P4_3                         30        /*!< GPIO_30 */
+#define MICBIAS                      31        /*!< GPIO_31 */
+#define P5_1                         32        /*!< GPIO_32 */
+#define P5_2                         33        /*!< GPIO_33 */
+#define P6_0                         34        /*!< GPIO_34 */
+#define P6_1                         35        /*!< GPIO_35 */
+#define P6_2                         36        /*!< GPIO_36 */
+#define P6_3                         37        /*!< GPIO_37 */
+#define P6_4                         38        /*!< GPIO_38 */
+#define P6_5                         39        /*!< GPIO_39 */
+#define P6_6                         40        /*!< GPIO_40 */
+#define P6_7                         41        /*!< GPIO_41 */
+#define P7_0                         42        /*!< GPIO_42 */
+#define P7_1                         43        /*!< GPIO_43 */
+#define SPIC_CSN                     44        /*!< GPIO_44 */
+#define SPIC_SCK                     45        /*!< GPIO_45 */
+#define SPIC_SI                      46        /*!< GPIO_46 */
+#define SPIC_SO                      47        /*!< GPIO_47 */
+#define SPIC_WEN                     48        /*!< GPIO_48 P1_4 */
+#define SPIC_HOLDEN                  49        /*!< GPIO_49 P1_3 */
+
+#define ADC_0                        P2_0
+#define ADC_1                        P2_1
+#define ADC_2                        P2_2
+#define ADC_3                        P2_3
+#define ADC_4                        P2_4
+#define ADC_5                        P2_5
+#define ADC_6                        P2_6
+#define ADC_7                        P2_7
+
+#define TOTAL_PIN_NUM                (50)
+#define IS_PIN_NUMBER(NUMBER)        (NUMBER < TOTAL_PIN_NUM)
+
+/** End of Pin_Number
+  * \}
+  */
+
+/** End of PIN DEFINE
+  * \}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PIN_DEF_H */
+
+
diff --git a/bee/drivers/pinmux/inc/rtl_pinmux.h b/bee/drivers/pinmux/inc/rtl_pinmux.h
new file mode 100644
index 00000000..e3da53e5
--- /dev/null
+++ b/bee/drivers/pinmux/inc/rtl_pinmux.h
@@ -0,0 +1,733 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *               Define to prevent recursive inclusion
+ *============================================================================*/
+#ifndef RTL_PINMUX_H
+#define RTL_PINMUX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*============================================================================*
+ *                        Header Files
+ *============================================================================*/
+#include "utils/rtl_utils.h"
+#include "pinmux/inc/rtl_wakeup.h"
+#if defined (CONFIG_SOC_SERIES_RTL87X2G)
+#include "pinmux/src/device/rtl87x2g/rtl_pinmux_def.h"
+#include "pinmux/inc/rtl87x2g/pin_def.h"
+#elif defined (CONFIG_SOC_SERIES_RTL87X3E)
+#include "pinmux/src/device/rtl87x3e/rtl_pinmux_def.h"
+#include "pinmux/inc/rtl87x3e/pin_def.h"
+#elif defined (CONFIG_SOC_SERIES_RTL87X3D)
+#include "pinmux/src/device/rtl87x3d/rtl_pinmux_def.h"
+#include "pinmux/inc/rtl87x3d/pin_def.h"
+#elif defined (CONFIG_SOC_SERIES_RTL87X2J)
+#include "pinmux/src/device/rtl87x2j/rtl_pinmux_def.h"
+#include "pinmux/inc/rtl87x2j/pin_def.h"
+#elif defined (CONFIG_SOC_SERIES_RTL87X3EU)
+#include "pinmux/src/device/rtl87x3eu/rtl_pinmux_def.h"
+#include "pinmux/inc/rtl87x3eu/pin_def.h"
+#elif defined (CONFIG_SOC_SERIES_RTL87X3J)
+#include "pinmux/src/device/rtl87x3j/rtl_pinmux_def.h"
+#include "pinmux/inc/rtl87x3j/pin_def.h"
+#endif
+
+/** \defgroup PINMUX      PINMUX
+  * \brief
+  * \{
+  */
+
+/*============================================================================*
+ *                         Macros
+ *============================================================================*/
+
+/*============================================================================*
+ *                         Constants
+ *============================================================================*/
+/** \defgroup PINMUX_Exported_Constants PINMUX Exported Constants
+  * \brief
+  * \{
+  */
+
+/**
+ * \brief       PAD Power Mode
+ *
+ * \ingroup     PINMUX_Exported_Constants
+ */
+
+typedef enum
+{
+    PAD_NOT_PWRON,
+    PAD_IS_PWRON = 1
+} PADPowerMode_TypeDef;
+
+/**
+ * \brief       PAD Output Config
+ *
+ * \ingroup     PINMUX_Exported_Constants
+ */
+
+typedef enum
+{
+    PAD_OUT_DISABLE,
+    PAD_OUT_ENABLE
+} PADOutputMode_TypeDef;
+
+/**
+ * \brief       PAD Output Value
+ *
+ * \ingroup     PINMUX_Exported_Constants
+ */
+
+typedef enum
+{
+    PAD_OUT_LOW,
+    PAD_OUT_HIGH
+} PADOutputValue_TypeDef;
+
+
+/**
+ * \brief       PAD Pull Mode
+ *
+ * \ingroup     PINMUX_Exported_Constants
+ */
+
+typedef enum
+{
+    PAD_PULL_DOWN,
+    PAD_PULL_UP,
+    PAD_PULL_NONE,
+} PADPullMode_TypeDef;
+
+/**
+ * \brief       PAD Pull Strength Mode
+ *
+ * \ingroup     PINMUX_Exported_Constants
+ */
+
+typedef enum
+{
+    PAD_PULL_WEAK,
+    PAD_PULL_STRONG,
+} PADPullStrengthMode_TypeDef;
+
+/**
+ * \brief       PAD Mode
+ *
+ * \ingroup     PINMUX_Exported_Constants
+ */
+
+typedef enum
+{
+    PAD_SW_MODE,
+#if (PAD_SUPPORT_CONFIG_PON_DOMAIN == 1)
+    PAD_PON_MODE,
+#endif
+    PAD_PINMUX_MODE,
+} PADMode_TypeDef;
+
+#if (PAD_SUPPORT_ANALOG_MODE == 1)
+/**
+ * \brief       PADAnalog_TypeDef Pad analog/digital mode for CODEC hybrid IO
+ *
+ * \ingroup     PINMUX_Exported_Constants
+ */
+typedef enum
+{
+    PAD_ANALOG_MODE,
+    PAD_DIGITAL_MODE,
+} PADAnalog_TypeDef;
+#endif
+
+#if (PAD_SUPPORT_GET_OUTPUT_CTRL == 1)
+typedef enum _PAD_AON_Status
+{
+    PAD_AON_OUTPUT_LOW,
+    PAD_AON_OUTPUT_HIGH,
+    PAD_AON_OUTPUT_DISABLE,
+    PAD_AON_PINMUX_ON,
+    PAD_AON_PIN_ERR
+} PAD_AON_Status;
+#endif
+
+/** End of PINMUX_Exported_Constants
+  * \}
+  */
+
+/*============================================================================*
+ *                         Functions
+ *============================================================================*/
+
+/**
+ * \defgroup    PINMUX_Exported_Functions PINMUX Exported Functions
+ * \{
+ * \ingroup     PINMUX
+ */
+
+/**
+ * \brief   Configure or reset all pins to idle mode.
+ *
+ * \param[in] None.
+ *
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void board_xxx_init(void)//XXX represents the name of the peripheral to be configured.
+ * {
+ *     Pinmux_Reset();
+ * }
+ * \endcode
+ */
+void Pinmux_Reset(void);
+
+/**
+ * \brief     Configure the specified pin to idle mode.
+ *
+ * \param[in] Pin_Num: Pin number to be configured. \ref Pin_Number.
+ *
+ * \return    None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void board_xxx_init(void)
+ * {
+ *     Pinmux_Deinit(P2_2);
+ * }
+ * \endcode
+ */
+void Pinmux_Deinit(uint8_t Pin_Num);
+
+/**
+ * \brief     Configure the specified pin to its corresponding peripheral function.
+ *
+ * \param[in] Pin_Num: Pin number to be configured. \ref Pin_Number.
+ *
+ * \param[in] Pin_Func: Peripheral function
+ *            This parameter This parameter refers to \ref Pin_Function_Number
+ *
+ * \return    None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_uart_init(void)
+ * {
+ *     Pad_Config(P2_0, PAD_PINMUX_MODE, PAD_IS_PWRON, PAD_PULL_UP, PAD_OUT_DISABLE,
+               PAD_OUT_HIGH);
+ *     Pad_Config(P2_1, PAD_PINMUX_MODE, PAD_IS_PWRON, PAD_PULL_UP, PAD_OUT_DISABLE,
+               PAD_OUT_HIGH);
+
+ *     Pinmux_Config(P2_0, UART0_TX);
+ *     Pinmux_Config(P2_1, UART0_RX);
+ * }
+ * \endcode
+ */
+void Pinmux_Config(uint8_t Pin_Num, uint32_t Pin_Func);
+
+/**
+ * \brief     Configure the relevant operation mode,
+ *            peripheral circuit and output level value in software mode of the specified pin
+ *
+ * \param[in] Pin_Num: Pin number to be configured. \ref Pin_Number.
+ *
+ * \param[in] AON_PAD_Mode: Use software mode or pinmux mode.
+ *            This parameter can be one of the following values:
+ *            \arg PAD_SW_MODE: Use software mode.
+ *            \arg PAD_PINMUX_MODE: Use pinmux mode.
+ *
+ * \param[in] AON_PAD_PwrOn: Config power of pad.
+ *            This parameter can be one of the following values:
+ *            \arg PAD_NOT_PWRON: Shutdown power of pad.
+ *            \arg PAD_IS_PWRON: Enable power of pad.
+ *
+ * \param[in] AON_PAD_Pull: config pad pull mode.
+ *            This parameter can be one of the following values:
+ *            \arg PAD_PULL_NONE: No pull.
+ *            \arg PAD_PULL_UP: Pull this pin up.
+ *            \arg PAD_PULL_DOWN: Pull this pin down.
+ *
+ * \param[in] AON_PAD_E: Config pad out put function.
+ *            This parameter can be one of the following values:
+ *            \arg PAD_OUT_DISABLE: Disable pin output.
+ *            \arg PAD_OUT_ENABLE: Enable pad output.
+ *
+ * \param[in] AON_PAD_O: Config pin output level.
+ *            This parameter can be one of the following values:
+ *            \arg PAD_OUT_LOW: Pad output low.
+ *            \arg PAD_OUT_HIGH: Pad output high.
+ *
+ * \return    None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_adc_init(void)
+ * {
+ *     Pad_Config(P2_0, PAD_SW_MODE, PAD_IS_PWRON, PAD_PULL_NONE, PAD_OUT_DISABLE, PAD_OUT_LOW);
+ *     Pad_Config(P2_1, PAD_SW_MODE, PAD_IS_PWRON, PAD_PULL_NONE, PAD_OUT_DISABLE, PAD_OUT_LOW);
+ * }
+ * \endcode
+ */
+void Pad_Config(uint8_t                 Pin_Num,
+                PADMode_TypeDef         AON_PAD_Mode,
+                PADPowerMode_TypeDef    AON_PAD_PwrOn,
+                PADPullMode_TypeDef     AON_PAD_Pull,
+                PADOutputMode_TypeDef   AON_PAD_E,
+                PADOutputValue_TypeDef  AON_PAD_O);
+
+#if (PAD_SUPPORT_CONFIG_EXT == 1)
+/**
+ * \brief     Configure the relevant operation mode, peripheral circuit, pull resistor value and
+ *            output level value in software mode of the specified pin.
+ *
+ * \param[in] Pin_Num: Pin number to be configured. \ref Pin_Number.
+ *
+ * \param[in] AON_PAD_Mode: Use software mode or pinmux mode.
+ *            This parameter can be one of the following values:
+ *            \arg PAD_SW_MODE: Use software mode.
+ *            \arg PAD_PINMUX_MODE: Use pinmux mode.
+ *
+ * \param[in] AON_PAD_PwrOn: Config power of pad.
+ *            This parameter can be one of the following values:
+ *            \arg PAD_SHUTDOWN: Shutdown power of pad.
+ *            \arg PAD_IS_PWRON: Enable power of pad.
+ *
+ * \param[in] AON_PAD_Pull: config pad pull mode.
+ *            This parameter can be one of the following values:
+ *            \arg PAD_PULL_NONE: No pull.
+ *            \arg PAD_PULL_UP: Pull this pin up.
+ *            \arg PAD_PULL_DOWN: Pull this pin down.
+ *
+ * \param[in] AON_PAD_E: Config pad output function, which only valid when PAD_SW_MODE.
+ *            This parameter can be one of the following values:
+ *            \arg PAD_OUT_DISABLE: Disable pin output.
+ *            \arg PAD_OUT_ENABLE: Enable pad output.
+ *
+ * \param[in] AON_PAD_O: Config pin output level, which only valid when PAD_SW_MODE and output mode.
+ *            This parameter can be one of the following values:
+ *            \arg PAD_OUT_LOW: Pad output low.
+ *            \arg PAD_OUT_HIGH: Pad output high.
+ *
+ * \param[in] AON_PAD_P: Config resistor value.
+ *            This parameter can be one of the following values:
+ *            \arg PAD_150K_PULL: pad pull 150k resistance.
+ *            \arg PAD_15K_PULL: pad pull 15k resistance.
+ *
+ * \return    None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * void driver_adc_init(void)
+ * {
+ *     Pad_ConfigExt(P2_0, PAD_PINMUX_MODE, PAD_IS_PWRON, PAD_PULL_UP, PAD_OUT_DISABLE, PAD_OUT_LOW, PAD_150K_PULL);
+ *     Pad_ConfigExt(P2_1, PAD_PINMUX_MODE, PAD_IS_PWRON, PAD_PULL_UP, PAD_OUT_DISABLE, PAD_OUT_LOW, PAD_150K_PULL);
+ * }
+ * \endcode
+ */
+extern void Pad_ConfigExt(uint8_t Pin_Num,
+                          PADMode_TypeDef AON_PAD_Mode,
+                          PADPowerMode_TypeDef AON_PAD_PwrOn,
+                          PADPullMode_TypeDef AON_PAD_Pull,
+                          PADOutputMode_TypeDef AON_PAD_E,
+                          PADOutputValue_TypeDef AON_PAD_O,
+                          PADPullStrengthMode_TypeDef AON_PAD_P);
+#endif
+
+#if (PAD_SUPPORT_LOWER_POWER_CONFIG == 1)
+void Pad_LPConfig(uint8_t Pin_Num, PADPullMode_TypeDef AON_PAD_Pull, FunctionalState NewState);
+
+void Pad_ModeAutoSwitchCmd(uint8_t Pin_Num, FunctionalState NewState);
+
+#endif
+
+/**
+ * \brief   Set all pins to the default state.
+ *
+ * \param[in] None.
+ *
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * void board_xxx_init(void)
+ * {
+ *     Pad_AllConfigDefault();
+ * }
+ * \endcode
+ */
+void Pad_AllConfigDefault(void);
+
+#if (PAD_SUPPORT_FUNCTION_CONFIG == 1)
+/**
+  * \brief  Config Pad Function.
+  *
+  * \param[in] Pin_Num: Pin number to be configured. \ref Pin_Number.
+  *
+  * \param[in] Pad_Func: Pad function \ref PAD_Function_Config.
+  *
+  * \return Config the pad function fail or success.
+  *         \arg true   Config success.
+  *         \arg false  Config fail due to wrong config value.
+  */
+bool Pad_FunctionConfig(uint8_t Pin_Num, PADFuncConfig_TypeDef Pad_Func);
+#endif
+
+#if (PAD_SUPPORT_HIGH_SPEED_CONFIG == 1)
+/**
+  * \brief  PAD high speed mode function select.
+  *
+  * \param[in]  Pin_Num: pin number.
+  *    This parameter is from ADC_0 to Max pin number, please refer to rtl876x.h "Pin_Number" part.
+  * \param[in]  PAD_HS_FUNC_SEL_TYPE: Pad_HS_Func_Sel.
+  *             \arg true: Set high speed function select success
+  *             \arg false: Set high speed function select failed due to invalid pinmux
+  *
+  * \return None.
+  */
+bool Pad_HighSpeedConfig(uint8_t *Pin_Group, uint8_t Pin_GroupLen,
+                         PADHSConfig_Typedef Pad_HighSpeed, FunctionalState NewState);
+#endif
+
+/**
+ * \brief     Configure the driving current.
+ *
+ * \param[in] Pin_Num: Pin number to be configured. \ref Pin_Number.
+ *
+ * \param[in] PAD_Driving_Current: This parameter sets the driving current.
+ *            This parameter can be the following:
+ *            \arg PAD_DRIVING_CURRENT_4mA.
+ *            \arg PAD_DRIVING_CURRENT_8mA.
+ *
+ * \return    None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void board_xxx_init(void)
+ * {
+ *     Pad_SetDrivingCurrent(P2_0, PAD_DRIVING_CURRENT_4mA);
+ * }
+ * \endcode
+ */
+void Pad_SetDrivingCurrent(uint8_t Pin_Num, PADDrivingCurrent_TypeDef PAD_DrivingCurrent);
+
+/**
+ * \brief     Set pin control mode.
+ *
+ * \param[in] Pin_Num: Pin number to be configured. \ref Pin_Number.
+ *
+ * \param[in] value: This parameter sets the pin mode.
+ *            This parameter can be the following:
+ *            \arg PAD_SW_MODE: Software mode.
+ *            \arg PAD_PINMUX_MODE: Default pinmux mode.
+ *
+ * \return    None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void board_xxx_init(void)
+ * {
+ *     Pad_SetControlMode(P2_0, PAD_SW_MODE);
+ * }
+ * \endcode
+ */
+void Pad_SetControlMode(uint8_t Pin_Num, PADMode_TypeDef PAD_Mode);
+
+/**
+ * \brief     Enable or disable pad output mode.
+ *
+ * \param[in] Pin_Num: Pin number to be configured. \ref Pin_Number.
+ *
+ * \param[in] value: This parameter sets whether the pin outputs the level in software mode.
+ *            This parameter can be enumerated PAD_OUTPUT_ENABLE_Mod of the values:
+ *            \arg PAD_OUT_DISABLE: Disable output.
+ *            \arg PAD_OUT_ENABLE: Enable output.
+ *
+ * \return    None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void pad_demo(void)
+ * {
+ *     Pad_OutputCmd(P2_0, PAD_OUT_ENABLE);
+ * }
+ * \endcode
+ */
+void Pad_OutputCmd(uint8_t Pin_Num, PADOutputMode_TypeDef PAD_OutEn);
+
+/**
+ * \brief     Configure pad output level.
+ *
+ * \param[in] Pin_Num: Pin number to be configured. \ref Pin_Number.
+ *
+ * \param[in] value: Config pin output level.
+ *            This parameter can be one of the following values:
+ *            \arg PAD_OUT_LOW: Pad output low.
+ *            \arg PAD_OUT_HIGH: Pad output high.
+ *
+ * \return    None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void board_xxx_init(void)
+ * {
+ *     Pad_SetOutputLevel(P2_0, PAD_OUT_HIGH);
+ * }
+ * \endcode
+ */
+void Pad_SetOutputLevel(uint8_t Pin_Num, PADOutputValue_TypeDef PAD_OutValue);
+
+/**
+ * \brief     Enable or disable pad pull-up / pull-down resistance function.
+ *
+ * \param[in] Pin_Num: Pin number to be configured. \ref Pin_Number.
+ *
+ * \param[in] NewState: This parameter enable or disable the the pad pin pull-up/pull-down function.
+ *            This parameter can be the following:
+ *            \arg DISABLE: Disable pad pull-up / pull-down function.
+ *            \arg ENABLE: Enable  pad pull-up / pull-down function.
+ *
+ * \return    None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void board_xxx_init(void)
+ * {
+ *     Pad_PullCmd(P2_0, ENABLE);
+ * }
+ * \endcode
+ */
+void Pad_PullCmd(uint8_t Pin_Num, FunctionalState NewState);
+
+/**
+ * \brief     Pad pull-up/pull-down resistance function selection.
+ *
+ * \param[in] Pin_Num: Pin number to be configured. \ref Pin_Number.
+ *
+ * \param[in] PAD_PullMode: This parameter sets whether the pin pull-up or pull-down.
+ *            This parameter can be the following:
+ *            \arg 0: Config pad pull-up function.
+ *            \arg 1: Config  pad pull-down function.
+ *
+ * \return    None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void board_xxx_init(void)
+ * {
+ *     Pad_SetPullMode(P2_0, 1);
+ * }
+ * \endcode
+ */
+void Pad_SetPullMode(uint8_t Pin_Num, PADPullMode_TypeDef PAD_PullMode);
+
+/**
+ * \brief     Configure the strength of pull-up/pull-down resistance.
+ *
+ * \param[in] Pin_Num: Pin number to be configured. \ref Pin_Number.
+ *
+ * \param[in] PAD_PullStrengthMode: This parameter sets the strength of pull-up/pull-down resistance.
+ *            This parameter can be the following:
+ *            \arg PAD_WEAK_PULL: Resistance weak pull.
+ *            \arg PAD_STRONG_PULL: Resistance strong pull.
+ *
+ * \return    None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void board_xxx_init(void)
+ * {
+ *     Pad_SetPullStrength(P2_0, PAD_STRONG_PULL);
+ * }
+ * \endcode
+ */
+void Pad_SetPullStrength(uint8_t Pin_Num, PADPullStrengthMode_TypeDef PAD_PullStrengthMode);
+
+/**
+ * \brief     Set pin power mode.
+ *
+ * \param[in] Pin_Num: Pin number to be configured. \ref Pin_Number.
+ *
+ * \param[in] value: This parameter sets the power supply mode of the pin,
+ *            and the value is enumeration PADPowerMode_TypeDef One of the values.
+ *            \arg PAD_NOT_PWRON: Power off.
+ *            \arg PAD_IS_PWRON: Power on.
+ *
+ * \return    None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void board_xxx_init(void)
+ * {
+ *     Pad_PowerCmd(P2_0, PAD_NOT_PWRON);
+ * }
+ * \endcode
+ */
+void Pad_PowerCmd(uint8_t Pin_Num, PADPowerMode_TypeDef PAD_PowerMode);
+
+#if (PAD_SUPPORT_ANALOG_MODE == 1)
+/**
+ * \brief   Config Hybrid pad analog/digital functions.
+ *
+ * \param[in] pin: Pin number to be configured. \ref Pin_Number.
+ *
+ * \param[in] mode: Please refer to PADAnalog_TypeDef.
+ *            \arg This parameter can be: PAD_ANALOG_MODE/PAD_DIGITAL_MODE.
+ *
+ * \return   None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * void pad_demo(void)
+ * {
+ *     Pad_AnalogMode(P2_1, PAD_ANALOG_MODE);
+ * }
+ * \endcode
+ */
+void Pad_AnalogMode(uint8_t pin, PADAnalog_TypeDef PAD_AnalogMode);
+#endif
+
+#if (PAD_SUPPORT_GET_OUTPUT_CTRL == 1)
+/**
+ * \brief   Get pad current output/input setting.
+ *
+ * \param[in] Pin_Num: Pin number to be configured. \ref Pin_Number.
+ *
+ * \return   reference PAD_AON_Status.
+ *           \arg PAD_AON_OUTPUT_LOW: Pad AON output low level.
+ *           \arg PAD_AON_OUTPUT_HIGH: Pad AON output high level.
+ *           \arg PAD_AON_OUTPUT_DISABLE: Pad AON output disable.
+ *           \arg PAD_AON_PINMUX_ON: Pad AON pinmux on.
+ *           \arg PAD_AON_PIN_ERR: Pad AON pin error.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * void pad_demo(void)
+ * {
+ *     if (Pad_GetOutputCtrl(P2_1) == PAD_AON_OUTPUT_LOW)
+ *     {
+ *         //Add user code here.
+ *     }
+ * }
+ * \endcode
+ */
+uint8_t Pad_GetOutputCtrl(uint8_t Pin_Num);
+#endif
+
+#if (PAD_SUPPORT_GET_POWER_GROUP == 1)
+/**
+ * \brief   Get the pad power group.
+ *
+ * \param[in] Pin_Num: Pin number to be configured. \ref Pin_Number.
+ *
+ * \return   Get the power group of the pin. Please refer to PADPowerGroup_TypeDef.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * void pad_demo(void)
+ * {
+ *     PADPowerGroup_TypeDef power_group = Pad_GetPowerGroup(P2_1);
+ * }
+ * \endcode
+ */
+PADPowerGroup_TypeDef  Pad_GetPowerGroup(uint8_t Pin_Num);
+#endif
+
+#if (PAD_SUPPORT_GET_PIN_NAME == 1)
+/**
+ * \brief   Get the pin name in string.
+ *
+ * \param[in] Pin_Num: Pin number to be configured. \ref Pin_Number.
+ *
+ * \return   pin name or null.
+ *           \arg pin name
+ *           \arg null due to invalid pin index.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * void pad_demo(void)
+ * {
+ *     Pad_GetPinName(P2_1);
+ * }
+ * \endcode
+ */
+const char *Pad_GetPinName(uint8_t Pin_Num);
+#endif
+
+#if (PAD_SUPPORT_SELECT_CONTROL_CORE == 1)
+/**
+ * \brief   Select the PAD pinmux VCORE domain.
+ *
+ * \param[in] pin: Pin number to be configured. \ref Pin_Number.
+ *
+ * \param[in] mode: Please refer to PADCoreSelect_TypeDef.
+ *            \arg This parameter can be \ref PAD_VCORE_Select.
+ *
+ * \return   None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * void pad_demo(void)
+ * {
+ *     Pad_SelectCore(P2_1, PAD_CORE_SEL_APP);
+ * }
+ * \endcode
+ */
+void Pad_SelectCore(uint8_t pin, PADCoreSelect_TypeDef pad_core_domain);
+#endif
+
+#if (PAD_SUPPORT_GET_SELECT_CONTROL_CORE == 1)
+/**
+ * \brief   Get the Selected VCORE domain.
+ *
+ * \param[in] pin: Pin number to be configured. \ref Pin_Number.
+ *
+ * \param[out] mode: Please refer to PADCoreSelect_TypeDef.
+ *            \arg This parameter can be \ref PAD_VCORE_Select.
+ *
+ * \return   None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * void pad_demo(void)
+ * {
+ *    PADCoreSelect_TypeDef pad_core =  Pad_GetSelectCore(P2_1);
+ * }
+ * \endcode
+ */
+PADCoreSelect_TypeDef Pad_GetSelectCore(uint8_t pin);
+#endif
+
+/** End of PINMUX_Exported_Functions
+  * \}
+  */
+
+/** End of PINMUX
+  * \}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RTL_PINMUX_H */
+
+
+
diff --git a/bee/drivers/pinmux/inc/rtl_wakeup.h b/bee/drivers/pinmux/inc/rtl_wakeup.h
new file mode 100644
index 00000000..72d9bf94
--- /dev/null
+++ b/bee/drivers/pinmux/inc/rtl_wakeup.h
@@ -0,0 +1,596 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *               Define to prevent recursive inclusion
+ *============================================================================*/
+#ifndef RTL_WAKEUP_H
+#define RTL_WAKEUP_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*============================================================================*
+ *                        Header Files
+ *============================================================================*/
+#include "utils/rtl_utils.h"
+#if defined (CONFIG_SOC_SERIES_RTL87X2J)
+#include "pinmux/src/device/rtl87x2j/rtl_pinmux_def.h"
+#include "pinmux/inc/rtl87x2j/pin_def.h"
+#elif defined (CONFIG_SOC_SERIES_RTL87X3D)
+#include "pinmux/src/device/rtl87x3d/rtl_pinmux_def.h"
+#include "pinmux/inc/rtl87x3d/pin_def.h"
+#elif defined (CONFIG_SOC_SERIES_RTL87X2G)
+#include "pinmux/src/device/rtl87x2g/rtl_pinmux_def.h"
+#include "pinmux/inc/rtl87x2g/pin_def.h"
+#elif defined (CONFIG_SOC_SERIES_RTL87X3J)
+#include "pinmux/src/device/rtl87x3j/rtl_pinmux_def.h"
+#include "pinmux/inc/rtl87x3j/pin_def.h"
+#endif
+
+/** \defgroup WAKEUP      WAKEUP
+  * \brief
+  * \{
+  */
+
+/*============================================================================*
+ *                         Macros
+ *============================================================================*/
+
+/*============================================================================*
+ *                         Constants
+ *============================================================================*/
+/** \defgroup WAKEUP_Exported_Constants WAKEUP Exported Constants
+  * \brief
+  * \{
+  */
+/**
+ * \brief       PAD WakeUp Polarity
+ *
+ * \ingroup     WAKEUP_Exported_Constants
+ */
+
+typedef enum
+{
+    SYSTEM_WAKEUP_POLARITY_HIGH,
+    SYSTEM_WAKEUP_POLARITY_LOW,
+} SystemWakeUpPolarity_TypeDef;
+
+#if (PAD_SUPPORT_ADPATER_WAKEUP == 1 | PAD_SUPPORT_MFB_WAKEUP == 1)
+/**
+ * \brief       WAKEUP_ENABLE_MODE PAD WAKE UP ENABLE SET
+ *
+ * \ingroup     WAKEUP_Exported_Constants
+ */
+typedef enum
+{
+    ADP_MODE,
+    BAT_MODE,
+    MFB_MODE,
+#if (PAD_SUPPORT_USB_WAKEUP == 1)
+    USB_MODE,
+#endif
+} SystemWakeUpMode_TypeDef;
+#endif
+
+typedef void (*P_PAD_CBACK)(uint32_t context);
+
+/** End of WAKEUP_Exported_Constants
+  * \}
+  */
+
+/*============================================================================*
+ *                         Functions
+ *============================================================================*/
+/**
+ * \brief     Enable the function of the wake-up system of the specified pin.
+ *
+ * \param[in] Pin_Num: Pin number to be configured. \ref Pin_Number.
+ *
+ * \param[in] Polarity: Polarity of wake-up system.
+ *            This parameter can be the following:
+ *            \arg SYSTEM_WAKEUP_POLARITY_HIGH: Use high level wakeup.
+ *            \arg SYSTEM_WAKEUP_POLARITY_LOW: Use low level wakeup.
+ *
+ * \param[in] DebounceNewState: Enable delay function.
+ *            \arg DISABLE: Disable delay function.
+ *            \arg ENABLE: Enable delay function.
+ *            This parameter is only meaningful if PAD_SUPPORT_CFG_WAKEUP_ENABLE_WITH_DEBOUNCE is defined.
+ *
+ * \return    None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * //PM enter IO call back function.
+ * void io_uart_pm_enter(void)
+ * {
+ *     // Switch pad to software mode
+ *     Pad_SetControlMode(P2_0, PAD_SW_MODE);//tx pin
+ *     Pad_SetControlMode(P2_1, PAD_SW_MODE);//rx pin
+ *
+ * #ifdef PAD_SUPPORT_WAKEUP_ENABLE_WITH_DEBOUNCE
+ *     System_WakeUpPinEnable(P2_1, PAD_WAKEUP_POLARITY_LOW, DISABLE);
+ * #else
+ *     System_WakeUpPinEnable(P2_1, PAD_WAKEUP_POLARITY_LOW);
+ * #endif
+ * }
+ * \endcode
+ */
+#if (PAD_SUPPORT_WAKEUP_ENABLE_WITH_DEBOUNCE == 1)
+void System_WakeUpPinEnable(uint8_t Pin_Num, SystemWakeUpPolarity_TypeDef Polarity,
+                            FunctionalState DebounceNewState);
+#else
+void System_WakeUpPinEnable(uint8_t Pin_Num, SystemWakeUpPolarity_TypeDef Polarity);
+#endif
+
+/**
+ * \brief     Disable the function of the wake-up system of the specified pin.
+ *
+ * \param[in] Pin_Num: Pin number to be configured. \ref Pin_Number.
+ *
+ * \return    None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * #define UART_RX_PIN                P4_1
+ *
+ * //System interrupt handler function, for wakeup pin.
+ * void System_Handler(void)
+ * {
+ *     if (System_WakeUpInterruptValue(UART_RX_PIN) == SET)
+ *     {
+ *         Pad_ClearWakeUpINTPendingBit(UART_RX_PIN);
+ *         System_WakeUpPinDisable(UART_RX_PIN);
+ *         //Add user code here.
+ *     }
+ * }
+ * \endcode
+ */
+void System_WakeUpPinDisable(uint8_t Pin_Num);
+
+/**
+ * \brief   Get pin interrupt status.
+ *
+ * \param[in] Pin_Num: Pin number to be configured. \ref Pin_Number.
+ *
+ * \return Interrupt status.
+ *         \arg 1: Pin wake up system.
+ *         \arg 0: The pin does not wake up the system.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * #define UART_RX_PIN                P4_1
+ *
+ * //System interrupt handler function, for wakeup pin.
+ * void System_Handler(void)
+ * {
+ *     if (System_WakeUpInterruptValue(UART_RX_PIN) == SET)
+ *     {
+ *         System_WakeUpClearINTPendingBit(UART_RX_PIN);
+ *         //Add user code here.
+ *     }
+ * }
+ * \endcode
+ */
+uint8_t System_WakeUpInterruptValue(uint8_t Pin_Num);
+
+#if (PAD_SUPPORT_WAKEUP_DEBOUNCE == 1)
+/**
+ * \brief  Enable or disable wake-up debounce function.
+ *
+ * \param[in]  Pin_Num: Pin number to be configured. \ref Pin_Number.
+ * \note  Pin_Num is invalid parameter for rtl87x2g series
+ *                so that any pin can be filled in.
+ *
+ * \param  PADWakeUpCmd_TypeDef: wake-up system enable or disable
+ *         \arg PAD_WAKEUP_DISABLE: Disable wakeup.
+ *         \arg PAD_WAKEUP_DISABLE: Enable wakeup.
+ *
+ * \return The result of the setting.
+ * \retval true: Config wake up debounce success
+ * \retval false:Set Config wake up debounce failed due to due to invalid pin num or this pin does not have debounce function.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ *void System_WakeUpPinEnable(uint8_t Pin_Num, uint8_t Polarity, FunctionalState NewState)
+ *{
+ *    if(Pin_Num >= MAX_PIN_NUM)
+ *    {
+ *        return;
+ *    }
+ *
+ *    Pad_SetWakeUpPolarity(Pin_Num, Polarity);
+ *    Pad_WakeUpDebounce_Cmd(Pin_Num, NewState);
+ *    if (ENABLE == NewState)
+ *    {
+ *        System_WakeUpDebounceCmd(Pin_Num, ENABLE);
+ *    }
+ *    Pad_WakeUp_Cmd(Pin_Num, ENABLE);
+ *}
+ * \endcode
+ */
+bool System_WakeUpDebounceCmd(uint8_t Pin_Num, FunctionalState NewState);
+
+/**
+ * \brief   Config wak-up system debounce time.
+ *
+ * \param[in]  Pin_Num: Pin number to be configured. \ref Pin_Number.
+ * \note  Pin_Num is invalid parameter for rtl87x2g series
+ *        so that any pin can be filled in.
+ *
+ * \param[in] TimeMs: Debounce time.
+ *
+ * \return The result of the setting.
+ * \retval true: Set debounce time success
+ * \retval false:Set debounce time failed due to due to invalid pin num or this pin does not have debounce function.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void board_xxx_init(void)
+ * {
+ *     System_WakeUpDebounceTime(10);
+ * }
+ * \endcode
+ */
+bool System_WakeUpDebounceTime(uint8_t Pin_Num, uint8_t TimeMs);
+
+/**
+ * \brief   Config wak-up system debounce time.
+ *
+ * \param[in]  Pin_Num: Pin number to be configured. \ref Pin_Number.
+ * \note  Pin_Num is invalid parameter for rtl87x2g series
+ *        so that any pin can be filled in.
+ *
+ * \param[in] TimeUs: Debounce time.
+ *
+ * \return The result of the setting.
+ * \retval true: Set debounce time success
+ * \retval false:Set debounce time failed due to due to invalid pin num or this pin does not have debounce function.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void board_xxx_init(void)
+ * {
+ *     System_WakeUpDebounceTimeUs(1000);
+ * }
+ * \endcode
+ */
+bool System_WakeUpDebounceTimeUs(uint8_t Pin_Num, uint32_t TimeUs);
+
+/**
+ * \brief  Get debounce wake up status.
+ *
+ * \param[in]  Pin_Num: Pin number to be configured. \ref Pin_Number.
+ * \note  Pin_Num is invalid parameter for rtl87x2g series
+ *                    so that any pin can be filled in.
+ *
+ * \return Debounce wakeup status
+ *
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void board_xxx_init(void)
+ * {
+ *     uint8_t WakeUpDebounceStatus = System_WakeUpDebounceStatus;
+ * }
+ * \endcode
+ */
+
+uint8_t System_WakeUpDebounceStatus(uint8_t Pin_Num);
+
+/**
+ * \brief  Clear debounce wake up status. Call this API will clear the debunce wakeup status bit.
+ *
+ * \param[in]  Pin number to be configured. \ref Pin_Number.
+ * \note  Pin_Num is invalid parameter for rtl87x2g series
+ *        so that any pin can be filled in.
+ *
+ * \return None
+ *
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void pm_store(void)
+ * {
+ *     System_WakeUpDebounceClear(P0_0);
+ * }
+ * \endcode
+ */
+void System_WakeUpDebounceClear(uint8_t Pin_Num);
+
+#if (PAD_SUPPORT_WAKEUP_DEBOUNCE_INTERRUPT == 1)
+/**
+ * \brief   Enable or disable wake-up system debounce interrupt.
+ *
+ * \param[in]  Pin_Num: Pin number to be configured. \ref Pin_Number.
+ * \note  Pin_Num is invalid parameter for rtl87x2g series
+ *        so that any pin can be filled in.
+ *
+ * \param[in] NewState: Enable or disable interrupt.
+ *
+ * \return The result of the setting.
+ * \retval true: Config interrupt success
+ * \retval false: Config interrupt failed due to invalid pin num or this pin does not have debounce function.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void board_xxx_init(void)
+ * {
+ *     System_WakeUpDebounceINTConfig(P0_0, ENABLE);
+ * }
+ * \endcode
+ */
+bool System_WakeUpDebounceINTConfig(uint8_t Pin_Num, FunctionalState NewState);
+#endif
+
+#if (PAD_SUPPORT_WAKEUP_DEBOUNCE_MULTI_GROUP == 1)
+bool System_WakeUpDebounceMultiGroupEnable(uint8_t Pin_Num);
+bool System_WakeUpDebounceMultiGroupDisable(uint8_t Pin_Num);
+#endif
+#endif
+
+/**
+ * \brief     Clear the interrupt pendign bit of the specified pin
+ *
+ * \param[in] Pin_Num: Pin number to be configured. \ref Pin_Number.
+ *
+ * \return    None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void board_xxx_init(void)
+ * {
+ *     Pad_ClearWakeUpINTPendingBit(P2_0);
+ * }
+ * \endcode
+ */
+void System_WakeUpClearINTPendingBit(uint8_t Pin_Num);
+
+/**
+ * \brief     Clear all wake up pin interrupt pending bit.
+ *
+ * \param[in] Pin_Num: Pin number to be configured. \ref Pin_Number.
+ *
+ * \return    None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void board_xxx_init(void)
+ * {
+ *     Pad_ClearAllWakeUpINT();
+ * }
+ * \endcode
+ */
+void System_WakeUpClearAllINT(void);
+
+#if (PAD_SUPPORT_WAKEUP_SHORT_PULSE == 1)
+/**
+ * \brief  Short pulse wakeup function.
+ *
+ * \param[in] NewState: Enable or disable short pulse wake up.
+ *            This parameter can be one of the following values:
+ *            \arg ENABLE: Enable short pulse wake up.
+ *            \arg DISABLE: Disable short pulse wake up.
+ *
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void board_xxx_init(void)
+ * {
+ *     Pad_ShortPulseWakeUpCmd(ENABLE);
+ * }
+ * \endcode
+ */
+void System_WakeUpShortPulseCmd(FunctionalState NewState);
+#endif
+
+/**
+  * \brief  Configure wakeup PPU function for the specified pin.
+  *
+  * \param[in]  Pin_Num: The number of the pin to configure. See \ref Pin_Number.
+  * \param[in]  Polarity: Select pin wakeup polarity (high level or low level).
+  *             This parameter can be PAD_WAKEUP_POL_HIGH or PAD_WAKEUP_POL_LOW.
+  * \param[in]  NewState: Enable or disable the wakeup PPU function.
+  *             This parameter can be ENABLE or DISABLE.
+  *
+  * \return None
+  */
+void System_WakeUpPPUCmd(uint8_t Pin_Num, uint8_t Polarity, FunctionalState NewState);
+
+/**
+  * \brief  Configure wakeup RAP function for the specified pin.
+  *
+  * \param[in]  Pin_Num: The number of the pin to configure. See \ref Pin_Number.
+  * \param[in]  Polarity: Select pin wakeup polarity (high level or low level).
+  *             This parameter can be PAD_WAKEUP_POL_HIGH or PAD_WAKEUP_POL_LOW.
+  * \param[in]  NewState: Enable or disable wakeup RAP function.
+  *             This parameter can be ENABLE or DISABLE.
+  *
+  * \return None
+  */
+void System_WakeUpRAPCmd(uint8_t Pin_Num, uint8_t Polarity, FunctionalState NewState);
+
+/**
+  * \brief  Enable or disable the function of the wake-up system of the specified pin.
+  *
+  * \param[in] Pin_Num: Pin number to be configured. \ref Pin_Number.
+  *
+  * \param[in] NewState: Enable or disable PAD wake up.
+  *            This parameter can be one of the following values:
+  *            \arg ENABLE: Enable PAD wake up system.
+  *            \arg DISABLE: Disable PAD wake up system.
+  *
+  * \return None.
+  */
+void System_WakeUpCmd(uint8_t Pin_Num, FunctionalState NewState);
+
+/**
+  * \brief Set the polarity for the function of the wake-up system of the specified pin.
+  *
+  * \param[in] Pin_Num: Pin number to be configured. \ref Pin_Number.
+  *
+  * \param[in] Polarity: Polarity of wake-up system.
+  *            This parameter can be the following:
+  *            \arg SYSTEM_WAKEUP_POLARITY_HIGH: Use high level wakeup.
+  *            \arg SYSTEM_WAKEUP_POLARITY_LOW: Use low level wakeup.
+  *
+  * \return None.
+  */
+void System_SetWakeUpPinPolarity(uint8_t Pin_Num, SystemWakeUpPolarity_TypeDef WakeUpPolarity);
+
+#if (PAD_SUPPORT_ADPATER_WAKEUP == 1 | PAD_SUPPORT_MFB_WAKEUP == 1)
+/**
+ * \brief   Config the system wakeup mode.
+ *
+ * \param[in] mode: mode of set, this parameter can reference WAKEUP_EN_MODE.
+ *            This parameter can be one of the following values:
+ *            \arg ADP_MODE: Wake up by adapter.
+ *            \arg BAT_MODE: Wake up by battery.
+ *            \arg MFB_MODE: Wake up by MFB.
+ *            \arg USB_MODE: Wake up by USB.
+ * \param[in] pol: polarity to wake up.
+ *            This parameter can be the following:
+ *            \arg POL_HIGH: Use high level wakeup.
+ *            \arg POL_LOW: Use low level wakeup.
+ * \param[in] NewState: Enable or disable wake up.
+ *            This parameter can be one of the following values:
+ *            \arg ENABLE: Enable the system wake up at specified polarity.
+ *            \arg DISABLE: Disable the system wake up at specified polarity.
+ *
+ * \return    Config the system wakeup mode fail or success.
+ *            \arg 0   Config success.
+ *            \arg 1   Config fail due to wrong mode.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * void adapter_wake_up_enable(void)
+ * {
+ *     //adapter mode is WAKE_UP_GENERAL
+ *     Pad_WakeUpCmd(ADP_MODE, POL_HIGH, ENABLE);
+ * }
+ * \endcode
+ */
+uint8_t System_WakeUpModeCmd(SystemWakeUpMode_TypeDef WakeUp_Mode,
+                             SystemWakeUpPolarity_TypeDef WakeUpPolarity, FunctionalState NewState);
+#endif
+
+#if (PAD_SUPPORT_ADPATER_WAKEUP == 1)
+/**
+ * \brief   Configure the adpater wake-up system functions in power off(shipping) mode.
+ *
+ * \param[in] NewState: Enable or disable adpater wake up.
+ *            This parameter can be one of the following values:
+ *            \arg ENABLE: Enable adpater wake up system at specified polarity.
+ *            \arg DISABLE: Disable adpater wake up system.
+ * \param[in] pol: Polarity to wake up.
+ *            This parameter can be the following:
+ *            \arg POL_HIGH: Use high level wakeup.
+ *            \arg POL_LOW: Use low level wakeup.
+ *
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * void adapter_wake_up_enable(void)
+ * {
+ *     //adapter mode is wake_up_power_off
+ *     System_SetAdpWakeUpFunction(ENABLE, PAD_WAKEUP_POLARITY_HIGH);
+ * }
+ * \endcode
+ */
+void System_WakeUpAdapterCmd(SystemWakeUpPolarity_TypeDef WakeUpPolarity, FunctionalState NewState);
+#endif
+
+#if (PAD_SUPPORT_MFB_WAKEUP == 1)
+/**
+ * \brief   Configure the MFB wake-up system functions in power off(shipping) mode.
+ *
+ * \param[in] NewState: Enable or disable MFB wake up.
+ *            This parameter can be one of the following values:
+ *            \arg ENABLE: Enable MFB wake up system.
+ *            \arg DISABLE: Disable MFB wake up system.
+ *
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * //io_test_set_mfb_mode is POWER_OFF_WAKEUP_TEST
+ * void mfb_wake_up_enable(void)
+ * {
+ *     System_SetMFBWakeUpFunction(ENABLE);
+ * }
+ * \endcode
+ */
+void System_WakeUpMFBCmd(FunctionalState NewState);
+#endif
+
+#if (PAD_SUPPORT_DETECT_MODE == 1)
+/**
+  * \brief  Selected the DETECT mode of PAD interrupt.
+  *
+  * \param[in]  is_ldetect: Enable or disable the LDETECT.
+  *             This parameter can be true or off.
+  *
+  * \return None
+  */
+void System_SelectLDETECT(bool is_ldetect);
+#endif
+
+#if (PAD_SUPPORT_WKIE_DIFF_BIT == 1)
+/**
+  * \brief  Configure wakeup off mode(power down) function for the specified pin.
+  * \param  Pin_Num: The number of the pin to configure. See \ref Pin_Number.
+  * \param  Polarity: Select pin wakeup polarity (high level or low level).
+  *         This parameter can be PAD_WAKEUP_POL_HIGH or PAD_WAKEUP_POL_LOW.
+  * \param  NewState: Enable or disable wakeup RAP function.
+  *         This parameter can be ENABLE or DISABLE.
+  * \return None
+  */
+void System_WakeUpPDCmd(uint8_t Pin_Num, uint8_t Polarity, FunctionalState NewState);
+#endif
+
+#if (PAD_SUPPORT_WAKE_SUB_IRQ == 1)
+/**
+  * \brief  Register the callback function of the wake-up system of the specified pin.
+  *
+  * \param[in] Pin_Num: Pin number to be configured. \ref Pin_Number.
+  *
+  * \param[in] Callback: Callback function.
+  *
+  * \param[in] Context: Context of the callback
+  *
+  * \return None.
+  */
+void System_RegisterPadWakeupCallback(uint8_t Pin_Num, P_PAD_CBACK Callback, uint32_t Context);
+#endif
+
+/** End of WAKEUP_Exported_Functions
+  * \}
+  */
+
+/** End of WAKEUP
+  * \}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RTL_WAKEUP_H */
+
+
+
diff --git a/bee/drivers/pinmux/src/CMakeLists.txt b/bee/drivers/pinmux/src/CMakeLists.txt
new file mode 100644
index 00000000..dd5e359a
--- /dev/null
+++ b/bee/drivers/pinmux/src/CMakeLists.txt
@@ -0,0 +1,4 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+add_subdirectory(device)
diff --git a/bee/drivers/pinmux/src/device/CMakeLists.txt b/bee/drivers/pinmux/src/device/CMakeLists.txt
new file mode 100644
index 00000000..034df6a1
--- /dev/null
+++ b/bee/drivers/pinmux/src/device/CMakeLists.txt
@@ -0,0 +1,6 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+add_soc_series_subdir(rtl8752h)
+add_soc_series_subdir(rtl87x2g)
+add_soc_series_subdir(rtl87x2j)
diff --git a/bee/drivers/pinmux/src/device/rtl8752h/rtl876x_pinmux.c b/bee/drivers/pinmux/src/device/rtl8752h/rtl876x_pinmux.c
new file mode 100644
index 00000000..2e2211aa
--- /dev/null
+++ b/bee/drivers/pinmux/src/device/rtl8752h/rtl876x_pinmux.c
@@ -0,0 +1,665 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "rtl876x_rcc.h"
+#include "rtl876x_pinmux.h"
+#include "app_section.h"
+
+const uint16_t PINADDR_TABLE[MAX_PIN_NUM] =  //static
+{
+    0xe0, 0xe2, 0xe4, 0xe6, 0xe8, 0xa0, 0xa2, 0xa4,
+    0xea, 0xec, 0xee, 0xf0, 0xf2, 0x80, 0x82, 0x84,
+    0xc0, 0xc2, 0xc4, 0xc6, 0xc8, 0xca, 0xcc, 0xce,
+    0x86, 0x88, 0x8a, 0x8c, 0x8e, 0x90, 0x92, 0x00,
+    0xa6, 0xa8, 0xaa, 0xac, 0xd0, 0x96, 0x98
+};
+
+const uint16_t WKSTATUS_TABLE[MAX_PIN_NUM] =
+{
+    //       Px-0                Px-1               Px-2                Px-3                Px-4                Px-5                Px-6                Px-7
+    ((0 << 12) | 0xf4), ((1 << 12) | 0xf4), ((2 << 12) | 0xf4), ((3 << 12) | 0xf4), ((4 << 12) | 0xf4), ((0 << 12) | 0xae), ((1 << 12) | 0xae), ((2 << 12) | 0xae),
+    ((5 << 12) | 0xf4), ((6 << 12) | 0xf4), ((7 << 12) | 0xf4), ((8 << 12) | 0xf4), ((9 << 12) | 0xf4), ((0 << 12) | 0x9a), ((1 << 12) | 0x9a), ((2 << 12) | 0x9a),
+    ((0 << 12) | 0xd2), ((1 << 12) | 0xd2), ((2 << 12) | 0xd2), ((3 << 12) | 0xd2), ((4 << 12) | 0xd2), ((5 << 12) | 0xd2), ((6 << 12) | 0xd2), ((7 << 12) | 0xd2),
+    ((3 << 12) | 0x9a), ((4 << 12) | 0x9a), ((5 << 12) | 0x9a), ((6 << 12) | 0x9a), ((7 << 12) | 0x9a), ((8 << 12) | 0x9a), ((9 << 12) | 0x9a), ((0 << 00) | 0x00),
+    ((3 << 12) | 0xae), ((4 << 12) | 0xae), ((5 << 12) | 0xae), ((6 << 12) | 0xae), ((8 << 12) | 0xd2), ((11 << 12) | 0x9a), ((12 << 12) | 0x9a)
+};
+
+/**
+  * @brief  Reset all pin to default value.
+  * @param  None.
+  * @note: two SWD pins will also be reset. Please use this function carefully.
+  * @retval None
+  */
+void Pinmux_Reset(void)
+{
+    uint8_t i;
+
+    for (i = 0; i < 10; i++)
+    {
+        PINMUX->CFG[i] = 0x00;
+    }
+
+    return;
+}
+
+/**
+  * @brief  Deinit the IO function of one pin.
+  * @param  Pin_Num: pin number.
+  *     This parameter is from ADC_0 to P4_1, please refer to rtl876x.h "Pin_Number" part.
+  * @retval None
+  */
+void Pinmux_Deinit(uint8_t Pin_Num)
+{
+    uint8_t pinmux_reg_num;
+
+    pinmux_reg_num = Pin_Num >> 2;
+    PINMUX->CFG[pinmux_reg_num] &= ~(0xff << ((Pin_Num % 4) << 3));
+    return;
+}
+
+/**
+  * @brief  Config pin to its corresponding IO function.
+  * @param  Pin_Num: pin number.
+  *     This parameter is from ADC_0 to P4_1, please refer to rtl876x.h "Pin_Number" part.
+  * @param  Pin_Func: mean one IO function, please refer to rtl876x_pinmux.h "Pin_Function_Number" part.
+  * @retval None
+  */
+void Pinmux_Config(uint8_t Pin_Num, uint8_t Pin_Func)
+{
+    uint8_t pinmux_reg_num;
+    uint8_t reg_offset;
+
+    pinmux_reg_num = Pin_Num >> 2;
+    reg_offset = (Pin_Num & 0x03) << 3;
+
+    PINMUX->CFG[pinmux_reg_num] = (PINMUX->CFG[pinmux_reg_num] & ~(0xFF << reg_offset))
+                                  | Pin_Func << reg_offset;
+
+    return;
+}
+
+/**
+  * @brief  config the corresponding pad.
+  * @param  Pin_Num: pin number.
+  *     This parameter is from ADC_0 to P4_1, please refer to rtl876x.h "Pin_Number" part.
+  * @param  AON_PAD_MODE: use software mode or pinmux mode.
+  *     This parameter can be one of the following values:
+  *     @arg PAD_SW_MODE: use software mode.
+  *     @arg PAD_PINMUX_MODE: use pinmux mode.
+  * @param  AON_PAD_PwrOn: config power of pad.
+  *     This parameter can be one of the following values:
+  *     @arg PAD_NOT_PWRON: shutdown power of pad.
+  *     @arg PAD_IS_PWRON: enable power of pad.
+  * @param  AON_PAD_Pull: config pad pull mode.
+  *     This parameter can be one of the following values:
+  *     @arg PAD_PULL_NONE: no pull.
+  *     @arg PAD_PULL_UP: pull this pin up.
+  *     @arg PAD_PULL_DOWN: pull thi pin down.
+  * @param  AON_PAD_E: config pad out put function.
+  *     This parameter can be one of the following values:
+  *     @arg PAD_OUT_DISABLE: disable pin output.
+  *     @arg PAD_OUT_ENABLE: enable pad output.
+  * @param  AON_PAD_O: config pin output level.
+  *     This parameter can be one of the following values:
+  *     @arg PAD_OUT_LOW: pad output low.
+  *     @arg PAD_OUT_HIGH: pad output high.
+  * @retval None
+  */
+
+void Pad_Config(uint8_t Pin_Num,
+                PAD_Mode AON_PAD_Mode,
+                PAD_PWR_Mode AON_PAD_PwrOn,
+                PAD_Pull_Mode AON_PAD_Pull,
+                PAD_OUTPUT_ENABLE_Mode AON_PAD_E,
+                PAD_OUTPUT_VAL AON_PAD_O)
+{
+    uint16_t tmpVal;
+    uint8_t addr = PINADDR_TABLE[Pin_Num];
+
+    tmpVal = btaon_fast_read_safe(addr);
+
+    /* Clear reg value first*/
+    tmpVal &= ~0xF;
+
+    /* Pull Config */
+    if (AON_PAD_Pull == PAD_PULL_UP)
+    {
+        tmpVal |= Pull_En;
+    }
+    else if (AON_PAD_Pull == PAD_PULL_DOWN)
+    {
+        tmpVal |= (Pull_En | Pull_Direction);
+    }
+
+    /* Output Config */
+    tmpVal |= (AON_PAD_O | (AON_PAD_E << 1));
+
+    if (AON_PAD_Mode)
+    {
+        tmpVal |= Pin_Mode;
+    }
+    else
+    {
+        tmpVal &= ~Pin_Mode;
+    }
+
+    btaon_fast_write_safe(addr, tmpVal | SHDN);
+
+    /* Pad control mode */
+    if (AON_PAD_PwrOn == PAD_NOT_PWRON)
+    {
+        tmpVal &= ~SHDN;
+        btaon_fast_write_safe(addr, tmpVal);
+    }
+
+}
+
+//1ms~64ms
+void System_WakeUpDebounceTime(uint8_t time)
+{
+    uint16_t  tmpVal;
+    tmpVal = btaon_fast_read_safe(0x2a);
+    /* clear reg value first */
+    tmpVal &= ~(0x3f00);
+    /* set value */
+    tmpVal |= (time & 0x3f) << 8;
+    /* clear debounce status */
+    tmpVal |= (BIT15 | BIT14);
+    btaon_fast_write_safe(0x2a, tmpVal);
+}
+
+/**
+  * @brief  Enable pin wakeup function.
+  * @param  Pin_Num: pin number.
+  *     This parameter is from ADC_0 to P4_1, please refer to rtl876x.h "Pin_Number" part.
+  * @param  Polarity: PAD_WAKEUP_POL_HIGH--use high level wakeup, PAD_WAKEUP_POL_LOW-- use low level wakeup.
+  * @param[in] DebounceEn: Enable delay function.
+  *      \arg PAD_WK_DEBOUNCE_DISABLE: Disable delay function.
+  *      \arg PAD_WK_DEBOUNCE_ENABLE: Enable delay function.
+  * @param[in] DebounceTime: Set debounce time, range from 0~63ms.
+  * @retval None
+  */
+void System_WakeUpPinEnable(uint8_t Pin_Num, uint8_t Polarity, uint8_t DebounceEn,
+                            uint8_t DebounceTime)
+{
+    if (DebounceEn == ENABLE)
+    {
+        System_WakeUpPinDisable(Pin_Num);
+        if (DebounceTime >= 64)
+        {
+            DebounceTime = 63;
+        }
+        System_WakeUpDebounceTime(DebounceTime);
+    }
+    else
+    {
+        System_DebounceWakeupStatus();
+    }
+    Pad_WakeupPolarityValue(Pin_Num, Polarity);
+    Pad_WKDebounceConfig(Pin_Num, DebounceEn);
+    Pad_WakeupEnableValue(Pin_Num, 1);
+}
+
+/**
+  * @brief  Disable pin wakeup function.
+  * @param  Pin_Num: pin number.
+  *     This parameter is from ADC_0 to P4_1, please refer to rtl876x.h "Pin_Number" part.
+  * @retval None
+  */
+
+void System_WakeUpPinDisable(uint8_t Pin_Num)
+{
+    Pad_WakeupEnableValue(Pin_Num, 0);
+}
+
+/**
+  * @brief  Check debounce wake up status.
+  * @note:  Call this API will clear the debunce wakeup status bit.
+  * @param  None
+  * @retval Debounce wakeup status
+  */
+uint8_t System_DebounceWakeupStatus(void)
+{
+    return Pad_DebounceWakeupStatus();
+}
+
+/**
+  * @brief  Check wake up pin interrupt status.
+  * @param  Pin_Num: pin number.
+  *     This parameter is from ADC_0 to P4_1, please refer to rtl876x.h "Pin_Number" part.
+  * @retval Pin interrupt status
+  */
+uint8_t System_WakeUpInterruptValue(uint8_t Pin_Num)
+{
+    return Pad_WakeupInterruptValue(Pin_Num);
+}
+
+void Pad_OutputControlValue(uint8_t Pin_Num, uint8_t value)
+{
+    uint16_t tmpVal;
+    uint8_t addr = PINADDR_TABLE[Pin_Num];
+
+    tmpVal = btaon_fast_read_safe(addr);
+    if (value)
+    {
+        tmpVal |= Output_Val;
+    }
+    else
+    {
+        tmpVal &= ~Output_Val;
+    }
+    btaon_fast_write_safe((addr), tmpVal);
+}
+
+void Pad_OutputEnableValue(uint8_t Pin_Num, uint8_t value)//0xf6
+{
+    uint16_t tmpVal;
+    uint8_t addr = PINADDR_TABLE[Pin_Num];
+
+    tmpVal = btaon_fast_read_safe(addr);
+    if (value)
+    {
+        tmpVal |= Output_En;
+    }
+    else
+    {
+        tmpVal &= ~Output_En;
+    }
+    btaon_fast_write_safe((addr), tmpVal);
+}
+
+void Pad_PullEnableValue(uint8_t Pin_Num, uint8_t value)
+{
+    uint16_t tmpVal;
+    uint8_t addr = PINADDR_TABLE[Pin_Num];
+
+    tmpVal = btaon_fast_read_safe(addr);
+    if (value)
+    {
+        tmpVal |= Pull_En;
+    }
+    else
+    {
+        tmpVal &= ~Pull_En;
+    }
+    btaon_fast_write_safe((addr), tmpVal);
+}
+
+void Pad_PullUpOrDownValue(uint8_t Pin_Num, uint8_t value)
+{
+    uint16_t tmpVal;
+    uint8_t addr = PINADDR_TABLE[Pin_Num];
+
+    tmpVal = btaon_fast_read_safe(addr);
+    if (value)
+    {
+        tmpVal |= Pull_Direction;
+    }
+    else
+    {
+        tmpVal &= ~Pull_Direction;
+    }
+    btaon_fast_write_safe((addr), tmpVal);
+}
+
+void Pad_PullConfigValue(uint8_t Pin_Num, uint8_t value)
+{
+    uint16_t tmpVal;
+    uint8_t addr = PINADDR_TABLE[Pin_Num];
+
+    tmpVal = btaon_fast_read_safe(addr);
+    if (value)
+    {
+        tmpVal |= Pull_Resistance;
+    }
+    else
+    {
+        tmpVal &= ~(Pull_Resistance);
+    }
+    btaon_fast_write_safe(addr, tmpVal);
+}
+
+void Pad_PowerOrShutDownValue(uint8_t Pin_Num, uint8_t value)
+{
+    uint16_t tmpVal;
+    uint8_t addr = PINADDR_TABLE[Pin_Num];
+
+    tmpVal = btaon_fast_read_safe(addr);
+    if (value)
+    {
+        tmpVal |= SHDN;
+    }
+    else
+    {
+        tmpVal &= ~SHDN;
+    }
+    btaon_fast_write_safe((addr), tmpVal);
+}
+
+void Pad_ControlSelectValue(uint8_t Pin_Num, uint8_t value)
+{
+    uint16_t tmpVal;
+    uint8_t addr = PINADDR_TABLE[Pin_Num];
+
+    tmpVal = btaon_fast_read_safe(addr);
+    if (value)
+    {
+        tmpVal |= Pin_Mode;
+    }
+    else
+    {
+        tmpVal &= ~Pin_Mode;
+    }
+    btaon_fast_write_safe((addr), tmpVal);
+}
+
+void Pad_WakeupEnableValue(uint8_t Pin_Num, uint8_t value)
+{
+    uint16_t tmpVal;
+    uint8_t addr = PINADDR_TABLE[Pin_Num];
+
+    tmpVal = btaon_fast_read_safe(addr);
+    if (value)
+    {
+        tmpVal |= WakeUp_En;
+    }
+    else
+    {
+        tmpVal &= ~WakeUp_En;
+    }
+    btaon_fast_write_safe((addr), tmpVal);
+}
+
+void Pad_WakeupPolarityValue(uint8_t Pin_Num, uint8_t value)
+{
+    uint16_t tmpVal;
+    uint8_t addr = PINADDR_TABLE[Pin_Num];
+
+    tmpVal = btaon_fast_read_safe(addr);
+    if (value)
+    {
+        tmpVal |= WKPOL;
+    }
+    else
+    {
+        tmpVal &= ~WKPOL;
+    }
+    btaon_fast_write_safe((addr), tmpVal);
+}
+
+void Pad_WKDebounceConfig(uint8_t Pin_Num, uint8_t value)
+{
+    uint16_t tmpVal;
+    uint8_t addr = PINADDR_TABLE[Pin_Num];
+
+    tmpVal = btaon_fast_read_safe(addr);
+    if (value)
+    {
+        tmpVal |= Pin_Debounce;
+    }
+    else
+    {
+        tmpVal &= ~Pin_Debounce;
+    }
+    btaon_fast_write_safe((addr), tmpVal);
+}
+
+uint8_t Pad_WakeupInterruptValue(uint8_t Pin_Num)
+{
+    uint16_t reg_temp;
+    uint16_t bit_temp;
+    uint16_t temp_value = 0;
+    uint8_t int_value = RESET;
+
+    reg_temp = (WKSTATUS_TABLE[Pin_Num] & ~(0xf000));
+    bit_temp = BIT((WKSTATUS_TABLE[Pin_Num]  & (0xf000)) >> 12);
+    temp_value = btaon_fast_read_safe(reg_temp);
+    if (temp_value & bit_temp)
+    {
+        int_value = SET;
+    }
+    return int_value;
+}
+
+uint8_t Pad_DebounceWakeupStatus(void)
+{
+    uint16_t value16 = 0;
+    uint8_t status_value = RESET;
+
+    value16 = btaon_fast_read_safe(0x2a);
+    if (value16 & BIT15)
+    {
+        status_value = SET;
+    }
+    //Write 1 to clear debounceWakeupStatus
+    btaon_fast_write_safe(0x2a, (value16 | BIT15));
+    return status_value;
+}
+
+void Pad_ClearWakeupINTPendingBit(uint8_t Pin_Num)
+{
+    uint16_t reg_temp;
+    uint16_t bit_temp;
+    uint16_t reg_value = 0;
+
+    reg_temp = (WKSTATUS_TABLE[Pin_Num] & ~(0xf000));
+    bit_temp = BIT((WKSTATUS_TABLE[Pin_Num]  & (0xf000)) >> 12);
+    reg_value = btaon_fast_read_safe(reg_temp) | bit_temp;
+    btaon_fast_write_safe(reg_temp, reg_value);
+}
+
+/**
+  * @brief Clear all wake up pin interrupt pending bit.
+  * @retun None
+  */
+void Pad_ClearAllWakeupINT(void)
+{
+    uint16_t tmpVal;
+
+    tmpVal = btaon_fast_read_safe(0x9a);
+    tmpVal |= 0x1BFF;
+    btaon_fast_write_safe(0x9a, tmpVal);
+
+    tmpVal = btaon_fast_read_safe(0xae);
+    tmpVal |= 0x7F;
+    btaon_fast_write_safe(0xae, tmpVal);
+
+    tmpVal = btaon_fast_read_safe(0xd2);
+    tmpVal |= 0x1FF;
+    btaon_fast_write_safe(0xd2, tmpVal);
+
+    tmpVal = btaon_fast_read_safe(0xf4);
+    tmpVal |= 0x3FF;
+    btaon_fast_write_safe(0xf4, tmpVal);
+}
+
+/**
+ * @brief  Set pin drivering current.
+ * @param  Pin_Num: Pin number to be configured.
+ * @param  value: This parameter sets the pin drivering current.
+ *         This parameter can be the following:
+ *         @arg PAD_DRIVING_CURRENT_8mA.
+ *         @arg PAD_DRIVING_CURRENT_18mA.
+ *         @arg PAD_DRIVING_CURRENT_28mA.
+ * @return None.
+ */
+void Pad_SetDrivingCurrent(uint8_t Pin_Num, PAD_DRIVING_CURRENT PAD_Driving_Current)
+{
+    if ((Pin_Num != P0_0) && (Pin_Num != P0_5) && (Pin_Num != P0_6) && (Pin_Num != P5_1))
+    {
+        return;
+    }
+
+    uint16_t tmpVal;
+    uint8_t addr = PINADDR_TABLE[Pin_Num];
+
+    tmpVal = btaon_fast_read_safe(addr);
+
+    tmpVal &= ~(0x03 << 11);
+    tmpVal |= PAD_Driving_Current << 11;
+
+    btaon_fast_write_safe((addr), tmpVal);
+}
+
+/**
+  * @brief  LCD8080 pinmux select interface.
+  * @param  value: LCD8080 select interface:
+                0x0 : disable LCD interface
+                0x1 : enable I8080 interface
+                0x2 : enable QSPI interface
+                0x3 : disable LCD interface
+  * @retval None
+  */
+void Pinmux_L8080_Sel_Intfc(uint32_t Sel_Intfc)
+{
+    if (Sel_Intfc > 3)
+    {
+        return;
+    }
+
+    HAL_WRITE32(SYSTEM_REG_BASE, REG_TEST_MODE, \
+                (HAL_READ32(SYSTEM_REG_BASE, REG_TEST_MODE) & (~(BIT(28) | BIT(29)))) | Sel_Intfc << 28);
+}
+
+/**
+  * @brief  LCD8080 pinmux cmd.
+  * @param  Pin_Num: LCD8080 Pinmux pos:
+                     P0_1 LCD PINMUX POS: 0
+                     P0_2 LCD PINMUX POS: 1
+                     P0_4 LCD PINMUX POS: 2
+                     P0_5 LCD PINMUX POS: 3
+                     P2_0 LCD PINMUX POS: 4
+                     P3_2 LCD PINMUX POS: 5
+                     P3_3 LCD PINMUX POS: 6
+                     P3_4 LCD PINMUX POS: 7
+                     P3_5 LCD PINMUX POS: 8
+                     P3_6 LCD PINMUX POS: 9
+                     P4_0 LCD PINMUX POS: 10
+                     P4_1 LCD PINMUX POS: 11
+                     P4_2 LCD PINMUX POS: 12
+                     P4_3 LCD PINMUX POS: 13
+  * @param  NewState: Enable or Disable.
+  * @retval None
+  */
+void Pinmux_L8080_Enable(uint8_t Pin_Num, FunctionalState NewState)
+{
+    uint8_t pin_pos;
+    switch (Pin_Num)
+    {
+    case P0_1:
+    case P0_2:
+        pin_pos = Pin_Num - 1;
+        break;
+    case P0_4:
+    case P0_5:
+        pin_pos = Pin_Num - 2;
+        break;
+    case P2_0:
+        pin_pos = Pin_Num - 12;
+        break;
+    case P3_2:
+    case P3_3:
+    case P3_4:
+    case P3_5:
+    case P3_6:
+        pin_pos = Pin_Num - 21;
+        break;
+    case P4_0:
+    case P4_1:
+    case P4_2:
+    case P4_3:
+        pin_pos = Pin_Num - 22;
+        break;
+    default:
+        return;
+    }
+
+    if (NewState)
+    {
+        HAL_WRITE32(SYSTEM_REG_BASE, REG_MUX_LCD, \
+                    HAL_READ32(SYSTEM_REG_BASE, REG_MUX_LCD) | BIT(pin_pos));
+    }
+    else
+    {
+        HAL_WRITE32(SYSTEM_REG_BASE, REG_MUX_LCD, \
+                    HAL_READ32(SYSTEM_REG_BASE, REG_MUX_LCD) & (~BIT(pin_pos)));
+    }
+}
+
+/**
+  * @brief  Spic0 master enable.
+  * @param  value: 0:Disable 1:Enable .
+  * @retval None
+  */
+void Spic0_control(uint8_t value)
+{
+    if (value)
+    {
+        HAL_WRITE32(SYSTEM_REG_BASE, REG_TEST_MODE, HAL_READ32(SYSTEM_REG_BASE, REG_TEST_MODE) | BIT(24));
+    }
+    else
+    {
+        HAL_WRITE32(SYSTEM_REG_BASE, REG_TEST_MODE, HAL_READ32(SYSTEM_REG_BASE,
+                                                               REG_TEST_MODE) & (~BIT(24)));
+    }
+}
+/**
+  * @brief  Spic1 master enable.
+  * @param  value: 0:Disable 1:Enable .
+  * @retval None
+  */
+void Spic1_control(uint8_t value)
+{
+    if (value)
+    {
+        HAL_WRITE32(SYSTEM_REG_BASE, REG_TEST_MODE, HAL_READ32(SYSTEM_REG_BASE, REG_TEST_MODE) | BIT(8));
+    }
+    else
+    {
+        HAL_WRITE32(SYSTEM_REG_BASE, REG_TEST_MODE, HAL_READ32(SYSTEM_REG_BASE, REG_TEST_MODE) & (~BIT(8)));
+    }
+}
+
+/**
+  * \brief  Store PINMUX register values when system enter DLPS.
+  * \param  PeriReg: Specifies to select the PINMUX peripheral.
+  * \param  StoreBuf: Store buffer to store PINMUX register data.
+  * \return None.
+  */
+DATA_RAM_FUNCTION
+void Pinmux_DLPSEnter(void *PeriReg, void *StoreBuf)
+{
+    PINMUXStoreReg_TypeDef *store_buf = (PINMUXStoreReg_TypeDef *)StoreBuf;
+    uint8_t i = 0;
+
+    for (i = 0; i < 10; i++)
+    {
+        store_buf->pinmux_reg[i] = PINMUX->CFG[i];
+    }
+
+    return;
+}
+
+/**
+  * \brief  Restore PINMUX register values when system exit DLPS.
+  * \param  PeriReg: Specifies to select the PINMUX peripheral.
+  * \param  StoreBuf: Restore buffer to restore PINMUX register data.
+  * \return None.
+  */
+DATA_RAM_FUNCTION
+void Pinmux_DLPSExit(void *PeriReg, void *StoreBuf)
+{
+    PINMUXStoreReg_TypeDef *store_buf = (PINMUXStoreReg_TypeDef *)StoreBuf;
+    uint8_t i;
+
+    for (i = 0; i < 10; i++)
+    {
+        PINMUX->CFG[i] = store_buf->pinmux_reg[i];
+    }
+
+    return;
+}
+
diff --git a/bee/drivers/pinmux/src/device/rtl8752h/rtl876x_pinmux.h b/bee/drivers/pinmux/src/device/rtl8752h/rtl876x_pinmux.h
new file mode 100644
index 00000000..5cc7ea1e
--- /dev/null
+++ b/bee/drivers/pinmux/src/device/rtl8752h/rtl876x_pinmux.h
@@ -0,0 +1,884 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _RTL876X_PINMUX_H_
+#define _RTL876X_PINMUX_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup  IO          Peripheral Drivers
+ * \defgroup    PINMUX      PINMUX
+ *
+ * \brief       Manage the PINMUX peripheral functions.
+ *
+ * \ingroup     IO
+ */
+
+/*============================================================================*
+ *                         Includes
+ *============================================================================*/
+#include "rtl876x.h"
+
+/*============================================================================*
+ *                         Constants
+ *============================================================================*/
+/**
+ * \defgroup    PINMUX_Exported_Constants   PINMUX Exported Constants
+ * \{
+ * \ingroup     PINMUX
+ */
+
+/**
+ * \cond
+ * \brief RTL8752H LCD8080 PINMUX OFFSET
+ * \{
+ */
+#define REG_MUX_LCD                 0x2A8
+/**
+ * \}
+ * \endcond
+ */
+
+/**
+ * \cond
+ * \brief Internal Macros
+ * \{
+ */
+/* Pad Functions */
+#define Output_Val                  (BIT0)
+#define Output_En                   (BIT1)
+#define Pull_En                     (BIT2)
+#define Pull_Direction              (BIT3)
+#define Pull_Resistance             (BIT4)
+#define WakeUp_En                   (BIT5)
+#define WKPOL                       (BIT6)
+#define SHDN                        (BIT8)
+#define Pin_Mode                    (BIT9)
+#define Pin_Debounce                (BIT10)
+/**
+ * \}
+ * \endcond
+ */
+
+/**
+ * \cond
+ * \brief Max Pin Number
+ * \{
+ */
+#define  MAX_PIN_NUM                39
+#define  TOTAL_PIN_NUM              39
+/**
+ * \}
+ * \endcond
+ */
+
+/**
+ * \defgroup    Pin_Function_Number Pin Function Number
+ * \{
+ * \ingroup     PINMUX_Exported_Constants
+ */
+#define IDLE_MODE                   0
+#define UART2_TX                    1
+#define UART2_RX                    2
+#define UART2_CTS                   3
+#define UART2_RTS                   4
+#define I2C0_CLK                    5
+#define I2C0_DAT                    6
+#define I2C1_CLK                    7
+#define I2C1_DAT                    8
+#define PWM2_P                      9
+#define PWM2_N                      10
+#define ENPWM0_P                    11
+#define ENPWM0_N                    12
+#define TIM_PWM0                    13
+#define TIM_PWM1                    14
+#define TIM_PWM2                    15
+#define TIM_PWM3                    16
+#define TIM_PWM4                    17
+#define TIM_PWM5                    18
+#define ENPWM0                      19
+#define ENPWM1                      20
+#define qdec_phase_a_x              21
+#define qdec_phase_b_x              22
+#define qdec_phase_a_y              23
+#define qdec_phase_b_y              24
+#define qdec_phase_a_z              25
+#define qdec_phase_b_z              26
+#define UART0_TX                    29
+#define UART0_RX                    30
+#define UART0_CTS                   31
+#define UART0_RTS                   32
+#define IRDA_TX                     33
+#define IRDA_RX                     34
+#define UART1_TX                    35
+#define UART1_RX                    36
+#define UART1_CTS                   37
+#define UART1_RTS                   38
+#define SPI1_SS_N_0_MASTER          39
+#define SPI1_SS_N_1_MASTER          40
+#define SPI1_SS_N_2_MASTER          41
+#define SPI1_CLK_MASTER             42
+#define SPI1_MO_MASTER              43
+#define SPI1_MI_MASTER              44
+#define SPI0_SS_N_0_SLAVE           45
+#define SPI0_CLK_SLAVE              46
+#define SPI0_SO_SLAVE               47
+#define SPI0_SI_SLAVE               48
+#define SPI0_SS_N_0_MASTER          49
+#define SPI0_CLK_MASTER             50
+#define SPI0_MO_MASTER              51
+#define SPI0_MI_MASTER              52
+#define SPI2W_DATA                  53
+#define SPI2W_CLK                   54
+#define SPI2W_CS                    55
+#define SWD_CLK                     56
+#define SWD_DIO                     57
+#define KEY_COL_0                   58
+#define KEY_COL_1                   59
+#define KEY_COL_2                   60
+#define KEY_COL_3                   61
+#define KEY_COL_4                   62
+#define KEY_COL_5                   63
+#define KEY_COL_6                   64
+#define KEY_COL_7                   65
+#define KEY_COL_8                   66
+#define KEY_COL_9                   67
+#define KEY_COL_10                  68
+#define KEY_COL_11                  69
+#define KEY_COL_12                  70
+#define KEY_COL_13                  71
+#define KEY_COL_14                  72
+#define KEY_COL_15                  73
+#define KEY_COL_16                  74
+#define KEY_COL_17                  75
+#define KEY_COL_18                  76
+#define KEY_COL_19                  77
+#define KEY_ROW_0                   78
+#define KEY_ROW_1                   79
+#define KEY_ROW_2                   80
+#define KEY_ROW_3                   81
+#define KEY_ROW_4                   82
+#define KEY_ROW_5                   83
+#define KEY_ROW_6                   84
+#define KEY_ROW_7                   85
+#define KEY_ROW_8                   86
+#define KEY_ROW_9                   87
+#define KEY_ROW_10                  88
+#define KEY_ROW_11                  89
+#define DWGPIO                      90
+#define DMIC1_CLK                   96
+#define DMIC1_DAT                   97
+#define LRC_I_CODEC_SLAVE           98
+#define BCLK_I_CODEC_SLAVE          99
+#define SDI_CODEC_SLAVE             100
+#define SDO_CODEC_SLAVE             101
+#define BT_COEX_I_0                 106
+#define BT_COEX_I_1                 107
+#define BT_COEX_I_2                 108
+#define BT_COEX_I_3                 109
+#define BT_COEX_O_0                 110
+#define BT_COEX_O_1                 111
+#define BT_COEX_O_2                 112
+#define BT_COEX_O_3                 113
+#define PTA_I2C_CLK_SLAVE           114
+#define PTA_I2C_DAT_SLAVE           115
+#define PTA_I2C_INT_OUT             116
+#define EN_EXPA                     117
+#define EN_EXLNA                    118
+#define LRC_SPORT0                  123
+#define BCLK_SPORT0                 124
+#define ADCDAT_SPORT0               125
+#define DACDAT_SPORT0               126
+#define MCLK                        127
+/** \} */
+
+/**
+ * \defgroup    PAD_Output_Value    PAD Output Value
+ * \{
+ * \ingroup     PINMUX_Exported_Constants
+ */
+
+typedef enum PAD_OUTPUT_VAL
+{
+    PAD_OUT_LOW,
+    PAD_OUT_HIGH
+} PAD_OUTPUT_VAL;
+
+/** \} */
+
+/**
+ * \defgroup    PAD_Output_Config PAD Output Config
+ * \{
+ * \ingroup     PINMUX_Exported_Constants
+ */
+
+typedef enum PAD_OUTPUT_ENABLE_Mode
+{
+    PAD_OUT_DISABLE,
+    PAD_OUT_ENABLE
+} PAD_OUTPUT_ENABLE_Mode;
+
+/** \} */
+
+/**
+ * \defgroup    PAD_Pull_Mode PAD Pull Mode
+ * \{
+ * \ingroup     PINMUX_Exported_Constants
+ */
+typedef enum PAD_Pull_Mode
+{
+    PAD_PULL_UP,
+    PAD_PULL_DOWN,
+    PAD_PULL_NONE
+} PAD_Pull_Mode;
+
+/** \} */
+
+/**
+ * \defgroup    PAD_PULL_CONFIG_VAL PAD Pull Config
+ * \{
+ * \ingroup     PINMUX_Exported_Constants
+ */
+
+typedef enum PAD_PULL_CONFIG_VAL
+{
+    PAD_WEAK_PULL,
+    PAD_STRONG_PULL
+} PAD_PULL_VAL;
+
+/** \} */
+
+/**
+ * \defgroup    PAD_WakeUp_Polarity_Value   PAD WakeUp Polarity
+ * \{
+ * \ingroup     PINMUX_Exported_Constants
+ */
+
+typedef enum PAD_WAKEUP_POL_VAL
+{
+    PAD_WAKEUP_POL_HIGH,
+    PAD_WAKEUP_POL_LOW
+} PAD_WAKEUP_POL_VAL;
+
+/** \} */
+
+/**
+ * \defgroup    PAD_Power_Mode PAD Power Mode
+ * \{
+ * \ingroup     PINMUX_Exported_Constants
+ */
+
+typedef enum PAD_PWR_Mode
+{
+    PAD_NOT_PWRON,
+    PAD_IS_PWRON = 1
+} PAD_PWR_Mode;
+
+/** \} */
+
+/**
+ * \defgroup    PAD_Mode PAD Mode
+ * \{
+ * \ingroup     PINMUX_Exported_Constants
+ */
+
+typedef enum PAD_Mode
+{
+    PAD_SW_MODE,
+    PAD_PINMUX_MODE
+} PAD_Mode;
+
+/** \} */
+
+/**
+ * \defgroup    PAD_WakeUp_Debounce_En  PAD WakeUp Debounce enable
+ * \{
+ * \ingroup     PINMUX_Exported_Constants
+ */
+
+typedef enum PAD_WAKEUP_DEBOUNCE_EN
+{
+    PAD_WK_DEBOUNCE_DISABLE,
+    PAD_WK_DEBOUNCE_ENABLE
+} PAD_WAKEUP_DEBOUNCE_EN;
+
+/** \} */
+
+/**
+ * \defgroup    PAD_Driving_Current PAD Driving Current
+ * \{
+ * \ingroup     PINMUX_Exported_Constants
+ */
+typedef enum PAD_DRIVING_CURRENT
+{
+    PAD_DRIVING_CURRENT_8_8mA = 0x0,
+    PAD_DRIVING_CURRENT_12_18mA = 0x1,
+    PAD_DRIVING_CURRENT_16_28mA = 0x3,
+} PAD_DRIVING_CURRENT;
+
+/** \} */
+
+/** End of PINMUX_Exported_Constants
+  * \}
+  */
+
+/*============================================================================*
+ *                         Functions
+ *============================================================================*/
+/**
+ * \defgroup    PINMUX_Exported_Functions PINMUX Exported Functions
+ * \{
+ * \ingroup     PINMUX
+ */
+
+/**
+ * \brief   Configure or reset all pins to idle mode.
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void board_xxx_init(void)//XXX represents the name of the peripheral to be configured.
+ * {
+ *     Pinmux_Reset();
+ * }
+ * \endcode
+ */
+void Pinmux_Reset(void);
+
+/**
+ * \brief   Configure the specified pin to idle mode.
+ * \param[in] Pin_Num: Pin number to be configured. \ref Pin_Define.
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void board_xxx_init(void)
+ * {
+ *     Pinmux_Deinit(P2_2);
+ * }
+ * \endcode
+ */
+void Pinmux_Deinit(uint8_t Pin_Num);
+
+/**
+ * \brief   Configure the usage function of the selected pin.
+ * \param[in] Pin_Num: Pin number to be configured. \ref Pin_Define.
+ * \param[in] Pin_Func: Use function of pin.
+ *      This parameter refers to \ref Pin_Function_Number
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_uart_init(void)
+ * {
+ *     Pad_Config(P2_0, PAD_PINMUX_MODE, PAD_IS_PWRON, PAD_PULL_UP, PAD_OUT_DISABLE,
+               PAD_OUT_HIGH);
+ *     Pad_Config(P2_1, PAD_PINMUX_MODE, PAD_IS_PWRON, PAD_PULL_UP, PAD_OUT_DISABLE,
+               PAD_OUT_HIGH);
+
+ *     Pinmux_Config(P2_0, UART0_TX);
+ *     Pinmux_Config(P2_1, UART0_RX);
+ * }
+ * \endcode
+ */
+void Pinmux_Config(uint8_t Pin_Num, uint8_t Pin_Func);
+
+/**
+ * \brief   Configure the relevant operation mode,
+ *          peripheral circuit and output level value in software mode of the specified pin
+ * \param[in] Pin_Num: Pin number to be configured. \ref Pin_Define.
+ * \param[in] AON_PAD_Mode: Use software mode or pinmux mode.
+ *      This parameter can be one of the following values:
+ *      \arg PAD_SW_MODE: Use software mode.
+ *      \arg PAD_PINMUX_MODE: Use pinmux mode.
+ * \param[in] AON_PAD_PwrOn: Configure power of pad.
+ *      This parameter can be one of the following values:
+ *      \arg PAD_NOT_PWRON: Shutdown power of pad.
+ *      \arg PAD_IS_PWRON: Enable power of pad.
+ * \param[in] AON_PAD_Pull: Configure pad pull mode.
+ *      This parameter can be one of the following values:
+ *      \arg PAD_PULL_NONE: No pull.
+ *      \arg PAD_PULL_UP: Pull this pin up.
+ *      \arg PAD_PULL_DOWN: Pull this pin down.
+ * \param[in] AON_PAD_E: Configure pad output function.
+ *      This parameter can be one of the following values:
+ *      \arg PAD_OUT_DISABLE: Disable pin output.
+ *      \arg PAD_OUT_ENABLE: Enable pad output.
+ * \param[in] AON_PAD_O: Configure pin output level.
+ *      This parameter can be one of the following values:
+ *      \arg PAD_OUT_LOW: Pad output low.
+ *      \arg PAD_OUT_HIGH: Pad output high.
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_adc_init(void)
+ * {
+ *     Pad_Config(P2_0, PAD_SW_MODE, PAD_IS_PWRON, PAD_PULL_NONE, PAD_OUT_DISABLE, PAD_OUT_LOW);
+ *     Pad_Config(P2_1, PAD_SW_MODE, PAD_IS_PWRON, PAD_PULL_NONE, PAD_OUT_DISABLE, PAD_OUT_LOW);
+ * }
+ * \endcode
+ */
+void Pad_Config(uint8_t Pin_Num,
+                PAD_Mode AON_PAD_Mode,
+                PAD_PWR_Mode AON_PAD_PwrOn,
+                PAD_Pull_Mode AON_PAD_Pull,
+                PAD_OUTPUT_ENABLE_Mode AON_PAD_E,
+                PAD_OUTPUT_VAL AON_PAD_O);
+
+/**
+ * \brief   Enable the function of the wake-up system of the specified pin.
+ * \param[in] Pin_Num: Pin number to be configured. \ref Pin_Define.
+ * \param[in] Polarity: Polarity of wake-up system.
+ *      This parameter can be the following:
+ *      \arg PAD_WAKEUP_POL_HIGH: Use high level wakeup.
+ *      \arg PAD_WAKEUP_POL_LOW: Use low level wakeup.
+ * \param[in] DebounceEn: Enable delay function.
+ *      \arg PAD_WK_DEBOUNCE_DISABLE: Disable delay function.
+ *      \arg PAD_WK_DEBOUNCE_ENABLE: Enable delay function.
+ * \param[in] DebounceTime: Set debounce time, range from 0~63ms.
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * //IO enter DLPS callback function.
+ * void io_uart_dlps_enter(void)
+ * {
+ *     // Switch pad to software mode
+ *     Pad_ControlSelectValue(P2_0, PAD_SW_MODE); //TX pin
+ *     Pad_ControlSelectValue(P2_1, PAD_SW_MODE); //RX pin
+ *
+ *     System_WakeUpPinEnable(P2_1, PAD_WAKEUP_POL_LOW, PAD_WK_DEBOUNCE_DISABLE);
+ * }
+ * \endcode
+ */
+void System_WakeUpPinEnable(uint8_t Pin_Num, uint8_t Polarity, uint8_t DebounceEn,
+                            uint8_t DebounceTime);
+
+/**
+ * \brief   Disable the function of the wake-up system of the specified pin.
+ * \param[in] Pin_Num: Pin number to be configured. \ref Pin_Define.
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * #define UART_RX_PIN                P4_1
+ *
+ * //System interrupt handler function, for wakeup pin.
+ * void System_Handler(void)
+ * {
+ *     if (System_WakeUpInterruptValue(UART_RX_PIN) == SET)
+ *     {
+ *         Pad_ClearWakeupINTPendingBit(UART_RX_PIN);
+ *         System_WakeUpPinDisable(UART_RX_PIN);
+ *         //Add user code here.
+ *     }
+ * }
+ * \endcode
+ */
+void System_WakeUpPinDisable(uint8_t Pin_Num);
+
+/**
+ * \brief   Get pin interrupt status.
+ * \param[in] Pin_Num: Pin number to be configured. \ref Pin_Define.
+ * \return Interrupt status.
+ * \retval 1: Pin wake up system.
+ * \retval 0: The pin does not wake up the system.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * #define UART_RX_PIN                P4_1
+ *
+ * //System interrupt handler function, for wakeup pin.
+ * void System_Handler(void)
+ * {
+ *     if (System_WakeUpInterruptValue(UART_RX_PIN) == SET)
+ *     {
+ *         Pad_ClearWakeupINTPendingBit(UART_RX_PIN);
+ *         System_WakeUpPinDisable(UART_RX_PIN);
+ *         //Add user code here.
+ *     }
+ * }
+ * \endcode
+ */
+uint8_t System_WakeUpInterruptValue(uint8_t Pin_Num);
+
+/**
+  * @brief  Get debounce wake up status.
+  * @note  Call this API will clear the debounce wakeup status bit.
+  * @retval Debounce wakeup status
+  *
+  *
+  * <b>Example usage</b>
+  * \code{.c}
+  *
+  * void board_xxx_init(void)
+  * {
+  *     uint8_t DebounceWakeupStatus = System_DebounceWakeupStatus();
+  * }
+  * \endcode
+  */
+uint8_t System_DebounceWakeupStatus(void);
+
+/**
+ * \brief     Configure pad output level.
+ * \param[in] Pin_Num: Pin number to be configured. \ref Pin_Define.
+ * \param[in] value: Configure pin output level.
+ *            This parameter can be one of the following values:
+ *            \arg PAD_OUT_LOW: Pad output low.
+ *            \arg PAD_OUT_HIGH: Pad output high.
+ * \return    None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void board_xxx_init(void)
+ * {
+ *     Pad_OutputControlValue(P2_0, PAD_OUT_HIGH);
+ * }
+ * \endcode
+ */
+void Pad_OutputControlValue(uint8_t Pin_Num, uint8_t value);
+
+/**
+ * \brief     Enable or disable pad output mode.
+ * \param[in] Pin_Num: Pin number to be configured. \ref Pin_Define.
+ * \param[in] value: This parameter sets whether the pin outputs the level in software mode.
+ *            This parameter can be enumerated PAD_OUTPUT_ENABLE_Mode of the values:
+ *            \arg PAD_OUT_DISABLE: Disable output.
+ *            \arg PAD_OUT_ENABLE: Enable output.
+ * \return    None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void pad_demo(void)
+ * {
+ *     Pad_OutputEnableValue(P2_0, PAD_OUT_ENABLE);
+ * }
+ * \endcode
+ */
+void Pad_OutputEnableValue(uint8_t Pin_Num, uint8_t value);
+
+/**
+ * \brief     Enable or disable pad pull-up / pull-down resistance function.
+ * \param[in] Pin_Num: Pin number to be configured. \ref Pin_Define.
+ * \param[in] value: This parameter Enable or disable the pad pin pull-up/pull-down function.
+ *            This parameter can be the following:
+ *            \arg DISABLE: Disable pad pull-up / pull-down function.
+ *            \arg ENABLE: Enable pad pull-up / pull-down function.
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void board_xxx_init(void)
+ * {
+ *     Pad_PullEnableValue(P2_0, ENABLE);
+ * }
+ * \endcode
+ */
+void Pad_PullEnableValue(uint8_t Pin_Num, uint8_t value);
+
+/**
+ * \brief     Pad pull-up/pull-down resistance function selection.
+ * \param[in] Pin_Num: Pin number to be configured.
+ *            This parameter is from P0_0 to H_2, please refer to rtl876x.h \ref Pin_Define part.
+ * \param[in] value: This parameter sets whether the pin pull-up or pull-down.
+ *            This parameter can be the following:
+ *            \arg 0: Config pad pull-up function.
+ *            \arg 1: Config pad pull-down function.
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void board_xxx_init(void)
+ * {
+ *     Pad_PullUpOrDownValue(P2_0, 1);
+ * }
+ * \endcode
+ */
+void Pad_PullUpOrDownValue(uint8_t Pin_Num, uint8_t value);
+
+/**
+ * \brief     Configure the strength of pull-up/pull-down resistance.
+ * \param[in] Pin_Num: Pin number to be configured. \ref Pin_Define.
+ * \param[in] value: This parameter sets the strength of pull-up/pull-down resistance.
+ *            This parameter can be the following:
+ *            \arg PAD_WEAK_PULL: Resistance weak pull.
+ *            \arg PAD_STRONG_PULL: Resistance strong pull.
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void board_xxx_init(void)
+ * {
+ *     Pad_PullConfigValue(P2_0, PAD_STRONG_PULL);
+ * }
+ * \endcode
+ */
+void Pad_PullConfigValue(uint8_t Pin_Num, uint8_t value);
+
+/**
+ * \brief     Set pin power mode.
+ * \param[in] Pin_Num: Pin number to be configured. \ref Pin_Define.
+ * \param[in] value: This parameter sets the power supply mode of the pin,
+ *                   and the value is enumeration PAD_PWR_Mode One of the values.
+ *            \arg PAD_NOT_PWRON: Power off.
+ *            \arg PAD_IS_PWRON: Power on.
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void board_xxx_init(void)
+ * {
+ *     Pad_PowerOrShutDownValue(P2_0, PAD_NOT_PWRON);
+ * }
+ * \endcode
+ */
+void Pad_PowerOrShutDownValue(uint8_t Pin_Num, uint8_t value);
+
+/**
+ * \brief     Set pin mode.
+ * \param[in] Pin_Num: Pin number to be configured. \ref Pin_Define.
+ * \param[in] value: This parameter sets the pin mode.
+ *            This parameter can be the following:
+ *            \arg PAD_SW_MODE: Software mode.
+ *            \arg PAD_PINMUX_MODE: Pinmux mode.
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void board_xxx_init(void)
+ * {
+ *     Pad_ControlSelectValue(P2_0, PAD_SW_MODE);
+ * }
+ * \endcode
+ */
+void Pad_ControlSelectValue(uint8_t Pin_Num, uint8_t value);
+
+/**
+ * \brief     Set pin driving current.
+ * \param[in] Pin_Num: Pin number to be configured.
+ *            This parameter can be P0_0 P0_5 P0_6 P5_1.
+ * \param[in] PAD_Driving_Current: This parameter sets the pin driving current.
+ *            This parameter can be the following:
+ *            \arg PAD_DRIVING_CURRENT_8_8mA.
+ *            \arg PAD_DRIVING_CURRENT_12_18mA.
+ *            \arg PAD_DRIVING_CURRENT_16_28mA.
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void board_xxx_init(void)
+ * {
+ *     Pad_SetDrivingCurrent(P0_0, PAD_DRIVING_CURRENT_16_28mA);
+ * }
+ * \endcode
+ */
+void Pad_SetDrivingCurrent(uint8_t Pin_Num, PAD_DRIVING_CURRENT PAD_Driving_Current);
+
+/**
+ * \brief     Enable the function of the wake-up system of the specified pin.
+ * \param[in] Pin_Num: Pin number to be configured. \ref Pin_Define.
+ * \param[in] value: Enable wake-up system function.
+ *            \arg 0: Disable wake-up system function.
+ *            \arg 1: Enable wake-up system function.
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void board_xxx_init(void)
+ * {
+ *     Pad_WakeupEnableValue(P2_0, 1);
+ * }
+ * \endcode
+ */
+void Pad_WakeupEnableValue(uint8_t Pin_Num, uint8_t value);
+
+/**
+ * \brief     Set polarity of wake-up system.
+ * \param[in] Pin_Num: Pin number to be configured. \ref Pin_Define.
+ * \param[in] Polarity: Polarity of wake-up system.
+ *            This parameter can be the following:
+ *            \arg PAD_WAKEUP_POL_LOW: Use low-level wakeup.
+ *            \arg PAD_WAKEUP_POL_HIGH: Use high-level wakeup.
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void board_xxx_init(void)
+ * {
+ *     Pad_WakeupPolarityValue(P2_0, PAD_WAKEUP_POL_HIGH);
+ * }
+ * \endcode
+ */
+void Pad_WakeupPolarityValue(uint8_t Pin_Num, uint8_t value);
+
+/**
+ * \brief     Config pin delay function.
+ * \param[in] Pin_Num: Pin number to be configured. \ref Pin_Define.
+ * \param[in] value: Enable delay function.
+ *            \arg 0: Disable delay function.
+ *            \arg 1: Enable delay function.
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void board_xxx_init(void)
+ * {
+ *     Pad_WKDebounceConfig(P2_0, 1);
+ * }
+ * \endcode
+ */
+void Pad_WKDebounceConfig(uint8_t Pin_Num, uint8_t value);
+
+/**
+ * \brief     Get pin interrupt status, function is the same as \see system_WakeUpInterruptValue.
+ * \param[in] Pin_Num: Pin number to be configured. \ref Pin_Define.
+ * \return    Interrupt status.
+ *            \retval 0: The pin does not wake up the system.
+ *            \retval 1: Pin wake up system.
+ */
+uint8_t Pad_WakeupInterruptValue(uint8_t Pin_Num);
+
+/**
+  * \brief  Check debounce wake up status.
+  * \note   Call this API will clear the debounce wakeup status bit.
+  * \return Debounce wakeup status
+  */
+uint8_t Pad_DebounceWakeupStatus(void);
+
+/**
+ * \brief     Clear the interrupt pending bit of the specified pin
+ * \param[in] Pin_Num: Pin number to be configured. \ref Pin_Define.
+ * \return    None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void board_xxx_init(void)
+ * {
+ *     Pad_ClearWakeupINTPendingBit(P2_0);
+ * }
+ * \endcode
+ */
+void Pad_ClearWakeupINTPendingBit(uint8_t Pin_Num);
+
+/**
+ * \brief     Clear all wake up pin interrupt pending bit.
+ * \return    None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void board_xxx_init(void)
+ * {
+ *     Pad_ClearAllWakeupINT();
+ * }
+ * \endcode
+ */
+void Pad_ClearAllWakeupINT(void);
+
+/**
+  * \brief  LCD8080 pinmux select interface.
+  * \param[in]  value: LCD8080 select interface:
+  *         \arg 0x0 : disable LCD interface
+  *         \arg 0x1 : enable I8080 interface
+  *         \arg 0x2 : enable QSPI interface
+  *         \arg 0x3 : disable LCD interface
+  * \return None
+  */
+void Pinmux_L8080_Sel_Intfc(uint32_t Sel_Intfc);
+
+/**
+  * \brief  LCD8080 pinmux cmd.
+  * \param[in]  Pin_Num: LCD8080 Pinmux pos:
+  *         \arg P0_1 LCD PINMUX POS: 0
+  *         \arg P0_2 LCD PINMUX POS: 1
+  *         \arg P0_4 LCD PINMUX POS: 2
+  *         \arg P0_5 LCD PINMUX POS: 3
+  *         \arg P2_0 LCD PINMUX POS: 4
+  *         \arg P3_2 LCD PINMUX POS: 5
+  *         \arg P3_3 LCD PINMUX POS: 6
+  *         \arg P3_4 LCD PINMUX POS: 7
+  *         \arg P3_5 LCD PINMUX POS: 8
+  *         \arg P3_6 LCD PINMUX POS: 9
+  *         \arg P4_0 LCD PINMUX POS: 10
+  *         \arg P4_1 LCD PINMUX POS: 11
+  *         \arg P4_2 LCD PINMUX POS: 12
+  *         \arg P4_3 LCD PINMUX POS: 13
+  * \param  NewState: Enable or Disable.
+  * \return None
+  */
+void Pinmux_L8080_Enable(uint8_t Pin_Num, FunctionalState NewState);
+
+/**
+ * \brief     Spic0 master enable.
+ * \param[in] value: 0:Disable 1:Enable.
+ * \return    None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void io_demo(void)
+ * {
+ *     Spic0_control(1);
+ * }
+ * \endcode
+ */
+void Spic0_control(uint8_t value);
+
+/**
+ * \brief     Spic1 master enable.
+ * \param[in] value: 0:Disable 1:Enable.
+ * \return    None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void io_demo(void)
+ * {
+ *     Spic1_control(1);
+ * }
+ * \endcode
+ */
+void Spic1_control(uint8_t value);
+
+/** End of PINMUX_Exported_Functions
+  * \}
+  */
+
+/** End of PINMUX
+  * \}
+  */
+
+typedef struct
+{
+    uint32_t pinmux_reg[10];
+} PINMUXStoreReg_TypeDef;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTL876X_PINMUX_H_ */
+
diff --git a/bee/drivers/pinmux/src/device/rtl87x2g/CMakeLists.txt b/bee/drivers/pinmux/src/device/rtl87x2g/CMakeLists.txt
new file mode 100644
index 00000000..76468827
--- /dev/null
+++ b/bee/drivers/pinmux/src/device/rtl87x2g/CMakeLists.txt
@@ -0,0 +1,7 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_include_directories(${CMAKE_CURRENT_SOURCE_DIR})
+
+zephyr_library_sources(rtl_pinmux.c)
+zephyr_code_relocate(FILES rtl_pinmux.c LOCATION ITCM)
diff --git a/bee/drivers/pinmux/src/device/rtl87x2g/rtl_pinmux.c b/bee/drivers/pinmux/src/device/rtl87x2g/rtl_pinmux.c
new file mode 100644
index 00000000..2dfb43cc
--- /dev/null
+++ b/bee/drivers/pinmux/src/device/rtl87x2g/rtl_pinmux.c
@@ -0,0 +1,1393 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *                        Header Files
+ *============================================================================*/
+#include "rtl_pinmux.h"
+
+/*============================================================================*
+ *                           Private Functions
+ *============================================================================*/
+static void Pad_WakeupConfig(uint8_t Pin_Num, PADWakeupCmd_TypeDef Status);
+static void Pad_SetWakeupPolarity(uint8_t Pin_Num, PADWakeupPolarity_TypeDef Wakeup_Polarity);
+static void Pad_WakeupDebounceCmd(uint8_t Pin_Num, PADWakeupDebCmd_TypeDef Status);
+static uint8_t Pad_GetWakeupINTStatus(uint8_t Pin_Num);
+
+static uint32_t pad_aon_read(uint32_t reg_addr)
+{
+    uint32_t reg_value = *((volatile uint32_t *)(reg_addr));
+    return reg_value;
+}
+
+static void pad_aon_write(uint32_t reg_addr, uint32_t reg_value)
+{
+    *((volatile uint32_t *)(reg_addr)) = reg_value;
+}
+/*============================================================================*
+ *                            Private Macros
+ *============================================================================*/
+#define Output_Val                  (BIT0)
+#define Output_En                   (BIT1)
+#define Pull_En                     (BIT2)
+#define Pull_Direction              (BIT3)
+#define Pull_Resistance             (BIT4)
+#define WKEN                        (BIT5)
+#define WKPOL                       (BIT6)
+#define Driving_Current             (BIT7)
+#define SHDN                        (BIT8)
+#define AON_SEL                     (BIT9)
+#define DEB                         (BIT10)
+
+/* BIT11~BIT15 has diffs in different PAD */
+#define DEDICATE                    (BIT11)
+#define Out_Gate_En                 (BIT15)
+
+/* IO_SYS_NS Configs */
+#define DEBIO_WAKEUP                (BIT14)
+#define DEBIO_WAKEUP_STS            (BIT15)
+
+#define MAX_PIN_ADDR_NUM            ((TOTAL_PIN_NUM / 2) + ((TOTAL_PIN_NUM % 2) != 0)) /* pad Register number: 42 */
+#define MAX_PIN_REG_NUM             ((TOTAL_PIN_NUM / 4) + ((TOTAL_PIN_NUM % 4) != 0)) /* pinmux Register number: 21 */
+
+#define PAD_DEBOUNCE_WKUP_STS       0x40001AACUL
+#define PAD_HS_MUX_SEL              (*((volatile uint32_t *)0x40002560UL))
+
+#define GPIO_32KXTAL_SEL_GPIO_FUNC  (SYSTEM_REG_BASE + 0xC84)
+
+const uint16_t PINADDR_TABLE[MAX_PIN_ADDR_NUM] =
+{
+    0x00, 0x04, 0x08, 0x0C, //P0
+    0x10, 0x14, 0x18, 0x1C, //P1
+    0x20, 0x24, 0x28, 0x2C, //P2
+    0x30, 0x34, 0x38, 0x3C, //P3
+    0x40, 0x44, 0x5C, 0x60, //P4
+    0x64, 0x68, 0x6C, 0x70, //P5
+    0x74, 0x78, 0x7C, 0x80, //P6
+    0x84, 0x88, 0x8C, 0xff, //P7
+    0x4C,                   //MICBIAS
+    0x48,                   //32K_XI_XO
+    0x58, 0xff,             //DAC
+    0xB0, 0xB4, 0xB8, 0xBC, //P9
+    0xC0, 0xC4,             //P10
+};
+
+const uint16_t WKSTATUS_TABLE[4] =
+{
+    0x00, 0x04, 0x08, 0x10
+};
+
+/*============================================================================*
+ *                           Public Functions
+ *============================================================================*/
+/**
+  * \brief  Reset all pin to default value.
+  * \param  None.
+  * \note   two SWD pins will also be reset. Please use this function carefully.
+  * \return None
+  */
+void Pinmux_Reset(void)
+{
+    for (uint8_t i = 0; i < MAX_PIN_REG_NUM; i++)
+    {
+        PINMUX->CFG[i] = 0x00;
+    }
+
+    return;
+}
+
+/**
+  * \brief  Configure the specified pin to idle mode.
+  * \param  Pin_Num: Pin number to be configured. \ref Pin_Number.
+  * \return None
+  */
+void Pinmux_Deinit(uint8_t Pin_Num)
+{
+    uint8_t pinmux_reg_num;
+
+    if (!IS_PIN_NUMBER(Pin_Num))
+    {
+        return;
+    }
+
+    pinmux_reg_num = Pin_Num >> 2;
+    PINMUX->CFG[pinmux_reg_num] &= ~(0xff << ((Pin_Num % 4) << 3));
+
+    return;
+}
+
+/**
+  * \brief  Configure the specified pin to its corresponding pin function.
+  * \param  Pin_Num: Pin number to be configured. \ref Pin_Number.
+  * \param  Pin_Func: Pin function. \ref PIN_Function.
+  * \return None
+  */
+void Pinmux_Config(uint8_t Pin_Num, uint8_t Pin_Func)
+{
+    uint8_t pinmux_reg_num;
+    uint8_t reg_offset;
+
+    if (!IS_PIN_NUMBER(Pin_Num))
+    {
+        return;
+    }
+
+    pinmux_reg_num = Pin_Num >> 2;
+    reg_offset = (Pin_Num & 0x03) << 3;
+
+    PINMUX->CFG[pinmux_reg_num] = (PINMUX->CFG[pinmux_reg_num] & ~(0xFF << reg_offset))
+                                  | Pin_Func << reg_offset;
+
+    /* Select GPIO Func when XI32K and XO32K should config as GPIO */
+    if (((Pin_Num >= XI32K) && (Pin_Num <= XO32K)) && Pin_Func == DWGPIO)
+    {
+        *((uint32_t *) GPIO_32KXTAL_SEL_GPIO_FUNC) |= BIT6;
+    }
+
+    return;
+}
+
+/**
+  * \brief  Configure the specified pin to its corresponding pin AON function.
+  * \param  Pin_Func: Pin AON function. \ref PINMUX_AON_Function.
+  * \return None
+  */
+void Pinmux_AON_Config(uint16_t Pin_Func)
+{
+    uint32_t reg_value = AON_REG_READ(AON_REG3X_SYS);
+    uint8_t offset = (Pin_Func & 0xFF00) >> 8;
+    uint8_t value = Pin_Func & 0xFF;
+
+    reg_value |= value << offset;
+
+    AON_REG_WRITE(AON_REG3X_SYS, reg_value);
+    return;
+}
+
+/**
+  * \brief  Configure the specified pin to its corresponding pin high speed function.
+  * \param  Pin_Func: High Speed function. \ref PINMUX_HS_Function.
+  * \return None
+  */
+void Pinmux_HS_Config(uint32_t Pin_Func)
+{
+    if (Pin_Func < (uint32_t)SDHC_HS_MUX)
+    {
+        PAD_HS_MUX_SEL &= ~0xF;
+        PAD_HS_MUX_SEL |= Pin_Func;
+    }
+    else
+    {
+        PAD_HS_MUX_SEL &= ~0xFFF0;
+        PAD_HS_MUX_SEL |= (Pin_Func & 0xFFF0);
+    }
+
+    return;
+}
+
+/**
+  * \brief  config the corresponding pad.
+  * \param  Pin_Num: Pin number to be configured. \ref Pin_Number.
+  * \param  AON_PAD_MODE: use software mode or pinmux mode.
+  *         This parameter can be one of the following values:
+  *         \arg PAD_SW_MODE: use software mode.
+  *         \arg PAD_PINMUX_MODE: use pinmux mode.
+  * \param  AON_PAD_PwrOn: config power of pad.
+  *         This parameter can be one of the following values:
+  *         \arg PAD_NOT_PWRON: shutdown power of pad.
+  *         \arg PAD_IS_PWRON: enable power of pad.
+  * \param  AON_PAD_Pull: config pad pull mode.
+  *         This parameter can be one of the following values:
+  *         \arg PAD_PULL_NONE: no pull.
+  *         \arg PAD_PULL_UP: pull this pin up.
+  *         \arg PAD_PULL_DOWN: pull thi pin down.
+  * \param  AON_PAD_E: config pad out put function.
+  *         This parameter can be one of the following values:
+  *         \arg PAD_OUT_DISABLE: disable pin output.
+  *         \arg PAD_OUT_ENABLE: enable pad output.
+  * \param  AON_PAD_O: config pin output level.
+  *         This parameter can be one of the following values:
+  *         \arg PAD_OUT_LOW: pad output low.
+  *         \arg PAD_OUT_HIGH: pad output high.
+  * \return None
+  */
+void Pad_Config(uint8_t                 Pin_Num,
+                PADMode_TypeDef         AON_PAD_Mode,
+                PADPowerMode_TypeDef    AON_PAD_PwrOn,
+                PADPullMode_TypeDef     AON_PAD_Pull,
+                PADOutputMode_TypeDef   AON_PAD_E,
+                PADOutputValue_TypeDef  AON_PAD_O)
+{
+    uint32_t reg_value_high_low = Pin_Num % 2;
+    uint32_t reg_addr = PAD_REG_BASE + PINADDR_TABLE[Pin_Num / 2];
+    uint32_t reg_value;
+    bool P40_gate_offset = 0;
+
+    if (!IS_PIN_NUMBER(Pin_Num))
+    {
+        return;
+    }
+
+    if ((Pin_Num >= XI32K) && (Pin_Num <= XO32K))
+    {
+        reg_addr = PAD_REG_BASE + PINADDR_TABLE[(Pin_Num + 1) / 2];
+        reg_value_high_low = (Pin_Num + 1) % 2;
+    }
+    if ((Pin_Num >= DACP) && (Pin_Num <= DACN))
+    {
+        reg_addr = PAD_REG_BASE + PINADDR_TABLE[(Pin_Num + 1) / 2];
+    }
+    if (Pin_Num == P4_0)
+    {
+        P40_gate_offset = 1;
+    }
+
+    reg_value = pad_aon_read(reg_addr);
+
+    if (reg_value_high_low)
+    {
+        /* GATE  RSVD  CLKP  CLKP  1111
+           AMUX  DEB   ASEL  SHDN  1100
+           DCUR  WKP   WKE   PULR  1111
+           PULD  PULE  OUTE  OUTV  0000
+         Clear reg value first. */
+        reg_value &= 0xFCF0FFFF;
+
+        /* Power on first */
+        reg_value |= SHDN << 16;
+        pad_aon_write(reg_addr, reg_value);
+
+        if (AON_PAD_Mode)
+        {
+            reg_value |= AON_SEL << 16;
+        }
+        else
+        {
+            reg_value &= ~(AON_SEL << 16);
+        }
+
+        /* Pull config */
+        if (AON_PAD_Pull == PAD_PULL_UP)
+        {
+            reg_value |= Pull_En << 16;
+            reg_value &= ~(Pull_Direction << 16);
+        }
+        else if (AON_PAD_Pull == PAD_PULL_DOWN)
+        {
+            reg_value |= Pull_En << 16;
+            reg_value |= Pull_Direction << 16;
+        }
+        else if (AON_PAD_Pull == PAD_PULL_NONE)
+        {
+            reg_value &= ~(Pull_En << 16);
+        }
+
+        /* Output Config */
+        if (AON_PAD_E == PAD_OUT_ENABLE)
+        {
+            reg_value |= (Output_En | AON_PAD_O) << 16;
+        }
+
+        /* Enable pad output gate. */
+        reg_value |= (Out_Gate_En >> P40_gate_offset) << 16;
+
+        pad_aon_write(reg_addr, reg_value);
+    }
+    else
+    {
+        /* RSVD  GATE  CLKP  CLKP  1111
+           AMUX  DEB   ASEL  SHDN  1100
+           DCUR  WKP   WKE   PULR  1111
+           PULD  PULE  OUTE  OUTV  0000
+         Clear reg value first. */
+        reg_value &= 0xFFFFFCF0;
+
+        /* Power on first */
+        reg_value |= SHDN;
+        pad_aon_write(reg_addr, reg_value);
+
+        if (AON_PAD_Mode)
+        {
+            reg_value |= AON_SEL;
+        }
+        else
+        {
+            reg_value &= ~AON_SEL;
+        }
+
+        /* Pull config */
+        if (AON_PAD_Pull == PAD_PULL_UP)
+        {
+            reg_value |= Pull_En;
+            reg_value &= ~Pull_Direction;
+        }
+        else if (AON_PAD_Pull == PAD_PULL_DOWN)
+        {
+            reg_value |= Pull_En;
+            reg_value |= Pull_Direction;
+        }
+        else if (AON_PAD_Pull == PAD_PULL_NONE)
+        {
+            reg_value &= ~(Pull_En);
+        }
+
+        /* Output Config */
+        if (AON_PAD_E == PAD_OUT_ENABLE)
+        {
+            reg_value |= (Output_En | AON_PAD_O);
+        }
+
+        /* Enable pad output gate. */
+        reg_value |= Out_Gate_En >> P40_gate_offset;
+
+        pad_aon_write(reg_addr, reg_value);
+    }
+
+    /* Pad control mode */
+    if (AON_PAD_PwrOn == PAD_NOT_PWRON)
+    {
+        if (reg_value_high_low)
+        {
+            reg_value &= ~(SHDN << 16);
+            pad_aon_write(reg_addr, reg_value);
+        }
+        else
+        {
+            reg_value &= ~SHDN ;
+            pad_aon_write(reg_addr, reg_value);
+        }
+    }
+}
+
+/**
+ * \brief  Config the corresponding pad dedicated function.
+ * \param  Pin_Num: Pin number to be configured.
+ *         This parameter is specific to certain PINs that support dedicated IO.
+ * \param  Status: Select from AON_MUX_SEL or dedicated IO.
+ * \return None
+ */
+void Pad_Dedicated_Config(uint8_t Pin_Num, FunctionalState Status)
+{
+    uint32_t reg_value_high_low = Pin_Num % 2;
+    uint32_t reg_addr = PAD_REG_BASE + PINADDR_TABLE[Pin_Num / 2];
+    uint32_t reg_value = 0;
+
+    if (!IS_PIN_NUMBER(Pin_Num))
+    {
+        return;
+    }
+
+    if ((Pin_Num >= XI32K) && (Pin_Num <= XO32K))
+    {
+        reg_addr = PAD_REG_BASE + PINADDR_TABLE[(Pin_Num + 1) / 2];
+        reg_value_high_low = (Pin_Num + 1) % 2;
+    }
+    if ((Pin_Num >= DACP) && (Pin_Num <= DACN))
+    {
+        reg_addr = PAD_REG_BASE + PINADDR_TABLE[(Pin_Num + 1) / 2];
+    }
+
+    reg_value = pad_aon_read(reg_addr);
+
+    if (Status == ENABLE)
+    {
+        if (reg_value_high_low)
+        {
+            reg_value |= DEDICATE << 16;
+        }
+        else
+        {
+            reg_value |= DEDICATE;
+        }
+    }
+    else
+    {
+        if (reg_value_high_low)
+        {
+            reg_value &= ~(DEDICATE << 16);
+        }
+        else
+        {
+            reg_value &= ~DEDICATE;
+        }
+    }
+
+    pad_aon_write(reg_addr, reg_value);
+}
+
+/**
+  * \brief  Enable the function of the wake-up system of the specified pin.
+  * \param  Pin_Num: Pin number to be configured. \ref Pin_Number.
+  * \param  Polarity: use high or low level wakeu to wakeup system.
+            This parameter is can be PAD_WAKEUP_POL_HIGH and PAD_WAKEUP_POL_LOW.
+  * \param  DebounceEn: Enable or disable debounce function.
+            This parameter is can be PAD_WK_DEBOUNCE_ENABLE and PAD_WK_DEBOUNCE_DISABLE.
+  * \return None
+  */
+void System_WakeUpPinEnable(uint8_t Pin_Num, uint8_t Polarity, uint8_t DebounceEn)
+{
+    uint32_t reg_value = 0;
+    uint32_t reg_addr = PAD_DEBOUNCE_WKUP_STS;
+
+    reg_value = pad_aon_read(reg_addr);
+
+    if (reg_value & DEBIO_WAKEUP_STS)
+    {
+        //Write 1 to clear debounceWakeupStatus
+        pad_aon_write(reg_addr, reg_value | DEBIO_WAKEUP_STS);
+    }
+
+    Pad_SetWakeupPolarity(Pin_Num, Polarity);
+    Pad_WakeupDebounceCmd(Pin_Num, DebounceEn);
+    if (PAD_WAKEUP_DEB_ENABLE == DebounceEn)
+    {
+        System_WakeUpDebounceCmd(Pin_Num, PAD_WAKEUP_ENABLE);
+    }
+    Pad_WakeupConfig(Pin_Num, PAD_WAKEUP_ENABLE);
+}
+
+/**
+  * \brief  Disable the function of the wake-up system of the specified pin.
+  * \param  Pin_Num: Pin number to be configured. \ref Pin_Number.
+  * \return None
+  */
+void System_WakeUpPinDisable(uint8_t Pin_Num)
+{
+    Pad_WakeupConfig(Pin_Num, PAD_WAKEUP_DISABLE);
+}
+
+/**
+  * \brief  Check wake up pin interrupt status.
+  * \param  Pin_Num: Pin number to be configured. \ref Pin_Number.
+  * \return Pin interrupt status
+  */
+uint8_t System_WakeUpInterruptValue(uint8_t Pin_Num)
+{
+    return Pad_GetWakeupINTStatus(Pin_Num);
+}
+
+/**
+ * \brief  Enable or disable wake-up debounce function.
+ * \param  Pin_Num: Pin number to be configured. \ref Pin_Number.
+ *         \note: Pin_Num is invalid parameter for rtl87x2g series
+ *                so that any pin can be filled in.
+ * \param  PADWakeupCmd_TypeDef: wake-up system enable or disable.
+ *         \arg PAD_WAKEUP_DISABLE: Disable wakeup.
+ *         \arg PAD_WAKEUP_DISABLE: Enable wakeup.
+ * \return None.
+ */
+void System_WakeUpDebounceCmd(uint8_t Pin_Num, PADWakeupCmd_TypeDef Status)
+{
+    uint32_t reg_value = 0;
+    uint32_t reg_addr = PAD_DEBOUNCE_WKUP_STS;
+    reg_value = pad_aon_read(reg_addr);
+
+    if (Status == PAD_WAKEUP_ENABLE)
+    {
+        reg_value |= DEBIO_WAKEUP;
+    }
+    else if (Status == PAD_WAKEUP_DISABLE)
+    {
+        reg_value &= ~DEBIO_WAKEUP;
+    }
+
+    pad_aon_write(reg_addr, reg_value);
+}
+
+/**
+ * \brief  Config wak-up system debounce time.
+ * \param  Pin_Num: Pin number to be configured. \ref Pin_Number.
+ *         \note: Pin_Num is invalid parameter for rtl87x2g series
+ *                so that any pin can be filled in.
+ * \param  time: Debounce time, 1 ~ 64ms.
+ * \return None.
+ */
+void System_WakeUpDebounceTime(uint8_t Pin_Num, uint8_t time_ms)
+{
+    uint8_t cnt = time_ms;
+    uint32_t reg_value = 0;
+    uint32_t reg_addr = PAD_DEBOUNCE_WKUP_STS;
+    reg_value = pad_aon_read(reg_addr);
+
+    if (cnt > 0x3F)
+    {
+        cnt = 0x3F;
+    }
+
+    reg_value &= 0x00003F00;
+    reg_value |= (cnt << 8) | DEBIO_WAKEUP;
+
+    pad_aon_write(reg_addr, reg_value);
+}
+
+/**
+  * \brief  Check debounce wake up status.
+  * \param  Pin_Num: Pin number to be configured. \ref Pin_Number.
+  *         \note: Pin_Num is invalid parameter for rtl87x2g series
+  *                so that any pin can be filled in.
+  * \return Debounce wakeup status.
+  */
+uint8_t System_WakeupDebounceStatus(uint8_t Pin_Num)
+{
+    uint8_t int_status = RESET;
+
+    uint32_t reg_value = 0;
+    uint32_t reg_addr = PAD_DEBOUNCE_WKUP_STS;
+
+    reg_value = pad_aon_read(reg_addr);
+
+    if (reg_value & DEBIO_WAKEUP_STS)
+    {
+        int_status = SET;
+    }
+
+    return int_status;
+}
+
+/**
+  * \brief  Clear debounce wake up status.
+  * \note:  Call this API will clear the debunce wakeup status bit.
+  * \param  Pin_Num: Pin number to be configured. \ref Pin_Number.
+  *         \note: Pin_Num is invalid parameter for rtl87x2g series
+  *                so that any pin can be filled in.
+  * \return None.
+  */
+void System_WakeupDebounceClear(uint8_t Pin_Num)
+{
+    uint32_t reg_value = 0;
+    uint32_t reg_addr = PAD_DEBOUNCE_WKUP_STS;
+
+    /* Write 1 to clear debounceWakeupStatus */
+    reg_value = pad_aon_read(reg_addr);
+    pad_aon_write(reg_addr, reg_value | DEBIO_WAKEUP_STS);
+}
+
+/**
+ * \brief  Set pin drivering current.
+ * \param  Pin_Num: Pin number to be configured. \ref Pin_Number.
+ * \param  value: This parameter sets the pin drivering current.
+ *         This parameter can be the following:
+ *         \arg PAD_DRIVING_CURRENT_4mA.
+ *         \arg PAD_DRIVING_CURRENT_8mA.
+ * \return None.
+ */
+void Pad_SetDrivingCurrent(uint8_t Pin_Num, PADDrivingCurrent_TypeDef PAD_Driving_Current)
+{
+    uint32_t reg_value = 0;
+    uint32_t reg_value_high_low = Pin_Num % 2;
+    uint32_t reg_addr = PAD_REG_BASE + PINADDR_TABLE[Pin_Num / 2];
+
+    if (!IS_PIN_NUMBER(Pin_Num))
+    {
+        return;
+    }
+
+    if ((Pin_Num >= XI32K) && (Pin_Num <= XO32K))
+    {
+        reg_addr = PAD_REG_BASE + PINADDR_TABLE[(Pin_Num + 1) / 2];
+        reg_value_high_low = (Pin_Num + 1) % 2;
+    }
+    if ((Pin_Num >= DACP) && (Pin_Num <= DACN))
+    {
+        reg_addr = PAD_REG_BASE + PINADDR_TABLE[(Pin_Num + 1) / 2];
+    }
+
+    uint8_t driver_current_e2 = 0;
+    uint8_t driver_current_e3 = 0;
+    if (PAD_Driving_Current == PAD_DRIVING_CURRENT_4mA)
+    {
+        driver_current_e2 = 0;
+        driver_current_e3 = 0;
+    }
+    else if (PAD_Driving_Current == PAD_DRIVING_CURRENT_8mA)
+    {
+        driver_current_e2 = 1;
+        driver_current_e3 = 0;
+    }
+    else if (PAD_Driving_Current == PAD_DRIVING_CURRENT_12mA)
+    {
+        driver_current_e2 = 0;
+        driver_current_e3 = 1;
+    }
+    else if (PAD_Driving_Current == PAD_DRIVING_CURRENT_16mA)
+    {
+        driver_current_e2 = 1;
+        driver_current_e3 = 1;
+    }
+
+    /* Set driving current E2 */
+    reg_value = pad_aon_read(reg_addr);
+    reg_value = driver_current_e2 ?
+                (reg_value | (Driving_Current << (16 * reg_value_high_low))) :
+                (reg_value & ~(Driving_Current << (16 * reg_value_high_low)));
+    pad_aon_write(reg_addr, reg_value);
+
+    /* Set driving current E3 */
+    pad_aon_write(PAD_REG_BASE + 0xC8, driver_current_e3);
+}
+
+/**
+ * \brief  Set pin control mode.
+ * \param  Pin_Num: Pin number to be configured. \ref Pin_Number.
+ * \param  value: This parameter sets the pin mode.
+ *         This parameter can be the following:
+ *         \arg PAD_SW_MODE: Software mode.
+ *         \arg PAD_PINMUX_MODE: Default pinmux mode.
+ * \return None.
+ */
+void Pad_SetControlMode(uint8_t Pin_Num, PADMode_TypeDef PAD_Mode)
+{
+    uint32_t reg_value = 0;
+    uint32_t reg_value_high_low = Pin_Num % 2;
+    uint32_t reg_addr = PAD_REG_BASE + PINADDR_TABLE[Pin_Num / 2];
+
+    if (!IS_PIN_NUMBER(Pin_Num))
+    {
+        return;
+    }
+
+    if ((Pin_Num >= XI32K) && (Pin_Num <= XO32K))
+    {
+        reg_addr = PAD_REG_BASE + PINADDR_TABLE[(Pin_Num + 1) / 2];
+        reg_value_high_low = (Pin_Num + 1) % 2;
+    }
+    if ((Pin_Num >= DACP) && (Pin_Num <= DACN))
+    {
+        reg_addr = PAD_REG_BASE + PINADDR_TABLE[(Pin_Num + 1) / 2];
+    }
+
+    reg_value = pad_aon_read(reg_addr);
+
+    if (reg_value_high_low) //1
+    {
+        reg_value &= ~(AON_SEL << 16);
+        reg_value |= PAD_Mode << 25;
+    }
+    else
+    {
+        reg_value &= ~AON_SEL;
+        reg_value |= PAD_Mode << 9;
+    }
+
+    pad_aon_write(reg_addr, reg_value);
+}
+
+/**
+ * \brief  Enable or disable pad output mode.
+ * \param  Pin_Num: Pin number to be configured. \ref Pin_Number.
+ * \param  value: This parameter sets whether the pin outputs the level in software mode.
+ *         This parameter can be enumerated PAD_OUTPUT_ENABLE_Mod of the values:
+ *         \arg PAD_OUT_DISABLE: Disable output.
+ *         \arg PAD_OUT_ENABLE: Enable output.
+ * \return None.
+ */
+void Pad_OutputCmd(uint8_t Pin_Num, PADOutputMode_TypeDef Status)
+{
+    uint32_t reg_value = 0;
+    uint32_t reg_value_high_low = Pin_Num % 2;
+    uint32_t reg_addr = PAD_REG_BASE + PINADDR_TABLE[Pin_Num / 2];
+
+    if (!IS_PIN_NUMBER(Pin_Num))
+    {
+        return;
+    }
+
+    if ((Pin_Num >= XI32K) && (Pin_Num <= XO32K))
+    {
+        reg_addr = PAD_REG_BASE + PINADDR_TABLE[(Pin_Num + 1) / 2];
+        reg_value_high_low = (Pin_Num + 1) % 2;
+    }
+    if ((Pin_Num >= DACP) && (Pin_Num <= DACN))
+    {
+        reg_addr = PAD_REG_BASE + PINADDR_TABLE[(Pin_Num + 1) / 2];
+    }
+
+    reg_value = pad_aon_read(reg_addr);
+
+    if (Status == PAD_OUT_ENABLE)
+    {
+        if (reg_value_high_low) //1
+        {
+            reg_value &= ~(Output_En << 16);
+            reg_value |= Output_En << 16;
+        }
+        else
+        {
+            reg_value &= ~Output_En;
+            reg_value |= Output_En;
+        }
+    }
+    else
+    {
+        if (reg_value_high_low) //1
+        {
+            reg_value &= ~(Output_En << 16);
+        }
+        else
+        {
+            reg_value &= ~Output_En;
+        }
+    }
+
+    pad_aon_write(reg_addr, reg_value);
+}
+
+/**
+ * \brief  Configure pad output level.
+ * \param  Pin_Num: Pin number to be configured. \ref Pin_Number.
+ * \param  value: Config pin output level.
+ *         This parameter can be one of the following values:
+ *         \arg PAD_OUT_LOW: Pad output low.
+ *         \arg PAD_OUT_HIGH: Pad output high.
+ * \return None.
+ */
+void Pad_SetOutputLevel(uint8_t Pin_Num, uint8_t value)
+{
+    uint32_t reg_value = 0;
+    uint32_t reg_value_high_low = Pin_Num % 2;
+    uint32_t reg_addr = PAD_REG_BASE + PINADDR_TABLE[Pin_Num / 2];
+
+    if (!IS_PIN_NUMBER(Pin_Num))
+    {
+        return;
+    }
+
+    if ((Pin_Num >= XI32K) && (Pin_Num <= XO32K))
+    {
+        reg_addr = PAD_REG_BASE + PINADDR_TABLE[(Pin_Num + 1) / 2];
+        reg_value_high_low = (Pin_Num + 1) % 2;
+    }
+    if ((Pin_Num >= DACP) && (Pin_Num <= DACN))
+    {
+        reg_addr = PAD_REG_BASE + PINADDR_TABLE[(Pin_Num + 1) / 2];
+    }
+
+    reg_value = pad_aon_read(reg_addr);
+
+    if (value)
+    {
+        if (reg_value_high_low) //1
+        {
+            reg_value &= ~(Output_Val << 16);
+            reg_value |= Output_Val << 16;
+        }
+        else
+        {
+            reg_value &= ~Output_Val;
+            reg_value |= Output_Val;
+        }
+    }
+    else
+    {
+        if (reg_value_high_low) //1
+        {
+            reg_value &= ~(Output_Val << 16);
+        }
+        else
+        {
+            reg_value &= ~Output_Val;
+        }
+    }
+
+    pad_aon_write(reg_addr, reg_value);
+}
+
+/**
+ * \brief  Enable or disable pad pull-up / pull-down resistance function.
+ * \param  Pin_Num: Pin number to be configured. \ref Pin_Number.
+ * \param  value: This parameter enable or disable the the pad pin pull-up/pull-down function.
+ *         This parameter can be the following:
+ *         \arg DISABLE: Disable pad pull-up / pull-down function.
+ *         \arg ENABLE: Enable  pad pull-up / pull-down function.
+ * \return None.
+ */
+void Pad_PullCmd(uint8_t Pin_Num, FunctionalState Status)
+{
+    uint32_t reg_value = 0;
+    uint32_t reg_value_high_low = Pin_Num % 2;
+    uint32_t reg_addr = PAD_REG_BASE + PINADDR_TABLE[Pin_Num / 2];
+
+    if (!IS_PIN_NUMBER(Pin_Num))
+    {
+        return;
+    }
+
+    if ((Pin_Num >= XI32K) && (Pin_Num <= XO32K))
+    {
+        reg_addr = PAD_REG_BASE + PINADDR_TABLE[(Pin_Num + 1) / 2];
+        reg_value_high_low = (Pin_Num + 1) % 2;
+    }
+    if ((Pin_Num >= DACP) && (Pin_Num <= DACN))
+    {
+        reg_addr = PAD_REG_BASE + PINADDR_TABLE[(Pin_Num + 1) / 2];
+    }
+
+    reg_value = pad_aon_read(reg_addr);
+
+    if (Status == ENABLE)
+    {
+        if (reg_value_high_low) //1
+        {
+            reg_value &= ~(Pull_En << 16);
+            reg_value |= Pull_En << 16;
+        }
+        else
+        {
+            reg_value &= ~Pull_En;
+            reg_value |= Pull_En;
+        }
+    }
+    else
+    {
+        if (reg_value_high_low) //1
+        {
+            reg_value &= ~(Pull_En << 16);
+        }
+        else
+        {
+            reg_value &= ~Pull_En;
+        }
+    }
+
+    pad_aon_write(reg_addr, reg_value);
+}
+
+/**
+ * \brief  Pad pull-up/pull-down resistance function selection.
+ * \param  Pin_Num: Pin number to be configured. \ref Pin_Number.
+ * \param  value: This parameter sets whether the pin pull-up or pull-down.
+ *         This parameter can be the following:
+ *         \arg 0: Config pad pull-up function.
+ *         \arg 1: Config  pad pull-down function.
+ * \return None.
+ */
+void Pad_SetPullMode(uint8_t Pin_Num, PADPullMode_TypeDef PAD_Pull_Mode)
+{
+    uint32_t tmp_value = 0;
+    uint32_t reg_value_high_low = Pin_Num % 2;
+    uint32_t reg_addr = PAD_REG_BASE + PINADDR_TABLE[Pin_Num / 2];
+    uint32_t reg_value = 0;
+
+    if (!IS_PIN_NUMBER(Pin_Num))
+    {
+        return;
+    }
+
+    if ((Pin_Num >= XI32K) && (Pin_Num <= XO32K))
+    {
+        reg_addr = PAD_REG_BASE + PINADDR_TABLE[(Pin_Num + 1) / 2];
+        reg_value_high_low = (Pin_Num + 1) % 2;
+    }
+    if ((Pin_Num >= DACP) && (Pin_Num <= DACN))
+    {
+        reg_addr = PAD_REG_BASE + PINADDR_TABLE[(Pin_Num + 1) / 2];
+    }
+
+    if (PAD_Pull_Mode == PAD_PULL_UP)
+    {
+        tmp_value |= Pull_En;
+        tmp_value &= ~Pull_Direction;
+    }
+    else if (PAD_Pull_Mode == PAD_PULL_DOWN)
+    {
+        tmp_value |= Pull_En;
+        tmp_value |= Pull_Direction;
+    }
+    else if (PAD_Pull_Mode == PAD_PULL_NONE)
+    {
+        tmp_value &= ~Pull_En;
+    }
+
+    reg_value = pad_aon_read(reg_addr);
+
+    if (reg_value_high_low) //1
+    {
+        reg_value &= ~((Pull_Direction | Pull_En) << 16);
+        reg_value |= tmp_value << 16;
+    }
+    else
+    {
+        reg_value &= ~(Pull_Direction | Pull_En);
+        reg_value |= tmp_value;
+    }
+
+    pad_aon_write(reg_addr, reg_value);
+}
+
+/**
+ * \brief  Configure the strength of pull-up/pull-down resistance.
+ * \param  Pin_Num: Pin number to be configured. \ref Pin_Number.
+ * \param  value: This parameter sets the strength of pull-up/pull-down resistance.
+ *         This parameter can be the following:
+ *         \arg PAD_WEAK_PULL: Resistance weak pull.
+ *         \arg PAD_STRONG_PULL: Resistance strong pull.
+ * \return None.
+ */
+void Pad_SetPullStrength(uint8_t Pin_Num, PADPullStrengthMode_TypeDef PAD_Pull_Strength_Mode)
+{
+    uint32_t reg_value = 0;
+    uint32_t reg_value_high_low = Pin_Num % 2;
+    uint32_t reg_addr = PAD_REG_BASE + PINADDR_TABLE[Pin_Num / 2];
+
+    if (!IS_PIN_NUMBER(Pin_Num))
+    {
+        return;
+    }
+
+    if ((Pin_Num >= XI32K) && (Pin_Num <= XO32K))
+    {
+        reg_addr = PAD_REG_BASE + PINADDR_TABLE[(Pin_Num + 1) / 2];
+        reg_value_high_low = (Pin_Num + 1) % 2;
+    }
+    if ((Pin_Num >= DACP) && (Pin_Num <= DACN))
+    {
+        reg_addr = PAD_REG_BASE + PINADDR_TABLE[(Pin_Num + 1) / 2];
+    }
+
+    reg_value = pad_aon_read(reg_addr);
+
+    if (PAD_Pull_Strength_Mode == PAD_PULL_STRONG)
+    {
+        if (reg_value_high_low) //1
+        {
+            reg_value &= ~(Pull_Resistance << 16);
+            reg_value |= Pull_Resistance << 16;
+        }
+        else
+        {
+            reg_value &= ~Pull_Resistance;
+            reg_value |= Pull_Resistance;
+        }
+    }
+    else
+    {
+        if (reg_value_high_low) //1
+        {
+            reg_value &= ~(Pull_Resistance << 16);
+        }
+        else
+        {
+            reg_value &= ~Pull_Resistance;
+        }
+    }
+
+    pad_aon_write(reg_addr, reg_value);
+}
+
+/**
+ * \brief  Set pin power mode.
+ * \param  Pin_Num: Pin number to be configured. \ref Pin_Number.
+ * \param  value: This parameter sets the power supply mode of the pin,
+ *                and the value is enumeration PADPowerMode_TypeDef One of the values.
+ *         \arg PAD_NOT_PWRON: Power off.
+ *         \arg PAD_IS_PWRON: Power on.
+ * \return None.
+ */
+void Pad_PowerCmd(uint8_t Pin_Num, PADPowerMode_TypeDef PWR_Mode)
+{
+    uint32_t reg_value = 0;
+    uint32_t reg_value_high_low = Pin_Num % 2;
+    uint32_t reg_addr = PAD_REG_BASE + PINADDR_TABLE[Pin_Num / 2];
+
+    if (!IS_PIN_NUMBER(Pin_Num))
+    {
+        return;
+    }
+
+    if ((Pin_Num >= XI32K) && (Pin_Num <= XO32K))
+    {
+        reg_addr = PAD_REG_BASE + PINADDR_TABLE[(Pin_Num + 1) / 2];
+        reg_value_high_low = (Pin_Num + 1) % 2;
+    }
+    if ((Pin_Num >= DACP) && (Pin_Num <= DACN))
+    {
+        reg_addr = PAD_REG_BASE + PINADDR_TABLE[(Pin_Num + 1) / 2];
+    }
+
+    reg_value = pad_aon_read(reg_addr);
+
+    if (PWR_Mode == PAD_IS_PWRON)
+    {
+        if (reg_value_high_low) //1
+        {
+            reg_value &= ~(SHDN << 16);
+            reg_value |= SHDN << 16;
+        }
+        else
+        {
+            reg_value &= ~SHDN;
+            reg_value |= SHDN;
+        }
+    }
+    else
+    {
+        if (reg_value_high_low) //1
+        {
+            reg_value &= ~(SHDN << 16);
+        }
+        else
+        {
+            reg_value &= ~SHDN;
+        }
+    }
+
+    pad_aon_write(reg_addr, reg_value);
+}
+
+/**
+ * \brief  Enable the function of the wake-up system of the specified pin.
+ * \param  Pin_Num: Pin number to be configured. \ref Pin_Number.
+ * \param  value: Enable wake-up system function.
+ *         \arg 0:Disable wake-up system function.
+ *         \arg 1:Enable wake-up system function.
+ * \return None.
+ */
+static void Pad_WakeupConfig(uint8_t Pin_Num, PADWakeupCmd_TypeDef Status)
+{
+    uint32_t reg_value = 0;
+    uint32_t reg_value_high_low = Pin_Num % 2;
+    uint32_t reg_addr = PAD_REG_BASE + PINADDR_TABLE[Pin_Num / 2];
+
+    if (!IS_PIN_NUMBER(Pin_Num))
+    {
+        return;
+    }
+
+    if ((Pin_Num >= XI32K) && (Pin_Num <= XO32K))
+    {
+        reg_addr = PAD_REG_BASE + PINADDR_TABLE[(Pin_Num + 1) / 2];
+        reg_value_high_low = (Pin_Num + 1) % 2;
+    }
+    if ((Pin_Num >= DACP) && (Pin_Num <= DACN))
+    {
+        reg_addr = PAD_REG_BASE + PINADDR_TABLE[(Pin_Num + 1) / 2];
+    }
+
+    reg_value = pad_aon_read(reg_addr);
+
+    if (Status == PAD_WAKEUP_ENABLE)
+    {
+        if (reg_value_high_low) //1
+        {
+            reg_value |= WKEN << 16;
+        }
+        else
+        {
+            reg_value |= WKEN;
+        }
+    }
+    else
+    {
+        if (reg_value_high_low) //1
+        {
+            reg_value &= ~(WKEN << 16);
+        }
+        else
+        {
+            reg_value &= ~WKEN;
+        }
+    }
+
+    pad_aon_write(reg_addr, reg_value);
+}
+
+/**
+ * \brief  Set polarity of wake-up system.
+ * \param  Pin_Num: Pin number to be configured. \ref Pin_Number.
+ * \param  Polarity: Polarity of wake-up system.
+ *         This parameter can be the following:
+ *         \arg PAD_WAKEUP_POL_LOW:Use low level wakeup.
+ *         \arg PAD_WAKEUP_POL_HIGH: Use high level wakeup.
+ * \return None.
+ */
+static void Pad_SetWakeupPolarity(uint8_t Pin_Num, PADWakeupPolarity_TypeDef Wakeup_Polarity)
+{
+    uint32_t reg_value = 0;
+    uint32_t reg_value_high_low = Pin_Num % 2;
+    uint32_t reg_addr = PAD_REG_BASE + PINADDR_TABLE[Pin_Num / 2];
+
+    if (!IS_PIN_NUMBER(Pin_Num))
+    {
+        return;
+    }
+
+    if ((Pin_Num >= XI32K) && (Pin_Num <= XO32K))
+    {
+        reg_addr = PAD_REG_BASE + PINADDR_TABLE[(Pin_Num + 1) / 2];
+        reg_value_high_low = (Pin_Num + 1) % 2;
+    }
+    if ((Pin_Num >= DACP) && (Pin_Num <= DACN))
+    {
+        reg_addr = PAD_REG_BASE + PINADDR_TABLE[(Pin_Num + 1) / 2];
+    }
+
+    reg_value = pad_aon_read(reg_addr);
+
+    if (Wakeup_Polarity == PAD_WAKEUP_POL_LOW)
+    {
+        if (reg_value_high_low) //1
+        {
+            reg_value |= WKPOL << 16;
+        }
+        else
+        {
+            reg_value |= WKPOL;
+        }
+    }
+    else
+    {
+        if (reg_value_high_low) //1
+        {
+            reg_value &= ~(WKPOL << 16);
+        }
+        else
+        {
+            reg_value &= ~WKPOL;
+        }
+    }
+
+    pad_aon_write(reg_addr, reg_value);
+}
+
+/**
+ * \brief  Config pin delay function.
+ * \param  Pin_Num: Pin number to be configured. \ref Pin_Number.
+ * \param  value: Enable delay function.
+ *         \arg 0:Disable delay function.
+ *         \arg 1:Enable delay function.
+ * \return None.
+ */
+static void Pad_WakeupDebounceCmd(uint8_t Pin_Num, PADWakeupDebCmd_TypeDef Status)
+{
+    uint32_t reg_value = 0;
+    uint32_t reg_value_high_low = Pin_Num % 2;
+    uint32_t reg_addr = PAD_REG_BASE + PINADDR_TABLE[Pin_Num / 2];
+
+    if (!IS_PIN_NUMBER(Pin_Num))
+    {
+        return;
+    }
+
+    if ((Pin_Num >= XI32K) && (Pin_Num <= XO32K))
+    {
+        reg_addr = PAD_REG_BASE + PINADDR_TABLE[(Pin_Num + 1) / 2];
+        reg_value_high_low = (Pin_Num + 1) % 2;
+    }
+    if ((Pin_Num >= DACP) && (Pin_Num <= DACN))
+    {
+        reg_addr = PAD_REG_BASE + PINADDR_TABLE[(Pin_Num + 1) / 2];
+    }
+
+    reg_value = pad_aon_read(reg_addr);
+
+    if (Status == PAD_WAKEUP_DEB_ENABLE)
+    {
+        if (reg_value_high_low) //1
+        {
+            reg_value |= DEB << 16;
+        }
+        else
+        {
+            reg_value |= DEB;
+        }
+    }
+    else
+    {
+        if (reg_value_high_low) //1
+        {
+            reg_value &= ~(DEB << 16);
+        }
+        else
+        {
+            reg_value &= ~DEB;
+        }
+    }
+
+    pad_aon_write(reg_addr, reg_value);
+}
+
+/**
+ * \brief  Get pin interrupt status, function is the same as \ref system_WakeUpInterruptValue.
+ * \param  Pin_Num: Pin number to be configured. \ref Pin_Number.
+ * \return Interrupt status.
+ *         \retval 0: The pin does not wake up the system.
+ *         \retval 1: Pin wake up system.
+ */
+static uint8_t Pad_GetWakeupINTStatus(uint8_t Pin_Num)
+{
+    uint8_t  int_status = RESET;
+    uint32_t bit_temp = 0;
+    uint32_t num_temp = 0;
+    uint32_t order_temp = 0;
+
+    if (!IS_PIN_NUMBER(Pin_Num))
+    {
+        return 0xFF;
+    }
+
+    //P0_0-P7_4
+    if ((Pin_Num >= P0_0) && (Pin_Num <= P7_4))
+    {
+        num_temp = Pin_Num;
+    }
+    //MICBIAS
+    else if (Pin_Num == MICBIAS)
+    {
+        num_temp = Pin_Num + 2;
+    }
+    //XI32K-XO32K
+    else if ((Pin_Num >= XI32K) && (Pin_Num <= XO32K))
+    {
+        num_temp = Pin_Num - 1;
+    }
+    //DACP-DACN
+    else if ((Pin_Num >= DACP) && (Pin_Num <= DACN))
+    {
+        order_temp = Pin_Num  % 2;
+        if (order_temp)
+        {
+            num_temp = Pin_Num + 1;
+        }
+        else
+        {
+            num_temp = Pin_Num - 1;
+        }
+
+    }
+    //P9_0-P10_2
+    else if ((Pin_Num >= P9_0) && (Pin_Num <= P10_2))
+    {
+        num_temp = Pin_Num + 24;
+    }
+
+    bit_temp = num_temp % 32;
+
+    uint32_t reg_addr = PAD_STS_REG_BASE + WKSTATUS_TABLE[num_temp / 32];
+    uint32_t reg_value = pad_aon_read(reg_addr);
+
+    if (reg_value & BIT(bit_temp))
+    {
+        int_status = SET;
+    }
+
+    return int_status;
+}
+
+/**
+ * \brief  Clear the interrupt pending bit of the specified pin
+ * \param  Pin_Num: Pin number to be configured. \ref Pin_Number.
+ * \return None.
+ */
+void Pad_ClearWakeupINTPendingBit(uint8_t Pin_Num)
+{
+    uint32_t bit_temp = 0;
+    uint32_t num_temp = 0;
+    uint32_t order_temp = 0;
+
+    if (!IS_PIN_NUMBER(Pin_Num))
+    {
+        return;
+    }
+
+    //P0_0-P7_4
+    if ((Pin_Num >= P0_0) && (Pin_Num <= P7_4))
+    {
+        num_temp = Pin_Num;
+    }
+    //MICBIAS
+    else if (Pin_Num == MICBIAS)
+    {
+        num_temp = Pin_Num + 2;
+    }
+    //XI32K-XO32K
+    else if ((Pin_Num >= XI32K) && (Pin_Num <= XO32K))
+    {
+        num_temp = Pin_Num - 1;
+    }
+    //DACP-DACN
+    else if ((Pin_Num >= DACP) && (Pin_Num <= DACN))
+    {
+        order_temp = Pin_Num  % 2;
+        if (order_temp)
+        {
+            num_temp = Pin_Num + 1;
+        }
+        else
+        {
+            num_temp = Pin_Num - 1;
+        }
+    }
+    //P9_0-P10_2
+    else if ((Pin_Num >= P9_0) && (Pin_Num <= P10_2))
+    {
+        num_temp = Pin_Num + 24;
+    }
+
+    bit_temp = num_temp % 32;
+
+    uint32_t reg_addr = PAD_STS_REG_BASE + WKSTATUS_TABLE[num_temp / 32];
+    uint32_t reg_value = 0;
+
+    reg_value = 1 << bit_temp;
+
+    pad_aon_write(reg_addr, reg_value);
+}
+
+/**
+ * \brief Clear all wake up pin interrupt pending bit.
+ * \param  None.
+ * \return None.
+ */
+void Pad_ClearAllWakeupINT(void)
+{
+    uint32_t reg_value = 0xFFFFFFFF;
+
+    for (uint8_t i = 0; i < 4; i++)
+    {
+        pad_aon_write(PAD_STS_REG_BASE + WKSTATUS_TABLE[i], reg_value);
+    }
+}
+
+/**
+  * \brief  Store PINMUX register values when system enter DLPS.
+  * \param  PeriReg: Specifies to select the PINMUX peripheral.
+  * \param  StoreBuf: Store buffer to store PINMUX register data.
+  * \return None.
+  */
+void Pinmux_DLPSEnter(void *PeriReg, void *StoreBuf)
+{
+    PINMUXStoreReg_Typedef *store_buf = (PINMUXStoreReg_Typedef *)StoreBuf;
+
+    uint8_t i = 0;
+
+    for (i = 0; i < MAX_PIN_REG_NUM; i++)
+    {
+        store_buf->pinmux_reg[i] = PINMUX->CFG[i];
+    }
+
+    return;
+}
+
+/**
+  * \brief  Restore PINMUX register values when system enter DLPS.
+  * \param  PeriReg: Specifies to select the PINMUX peripheral.
+  * \param  StoreBuf: Restore buffer to restore PINMUX register data.
+  * \return None.
+  */
+void Pinmux_DLPSExit(void *PeriReg, void *StoreBuf)
+{
+    PINMUXStoreReg_Typedef *store_buf = (PINMUXStoreReg_Typedef *)StoreBuf;
+
+    uint8_t i;
+
+    for (i = 0; i < MAX_PIN_REG_NUM; i++)
+    {
+        PINMUX->CFG[i] = store_buf->pinmux_reg[i];
+    }
+
+    return;
+}
+
diff --git a/bee/drivers/pinmux/src/device/rtl87x2g/rtl_pinmux.h b/bee/drivers/pinmux/src/device/rtl87x2g/rtl_pinmux.h
new file mode 100644
index 00000000..8a3da7b7
--- /dev/null
+++ b/bee/drivers/pinmux/src/device/rtl87x2g/rtl_pinmux.h
@@ -0,0 +1,1332 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *               Define to prevent recursive inclusion
+ *============================================================================*/
+#ifndef RTL_PINMUX_H
+#define RTL_PINMUX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*============================================================================*
+ *                        Header Files
+ *============================================================================*/
+#include "utils/rtl_utils.h"
+#include "rtl_pinmux_def.h"
+#include "pin_def.h"
+
+/** \defgroup PINMUX      PINMUX
+  * \brief
+  * \{
+  */
+
+/*============================================================================*
+ *                         Macros
+ *============================================================================*/
+
+/*============================================================================*
+ *                         Constants
+ *============================================================================*/
+/** \defgroup PINMUX_Exported_Constants PINMUX Exported Constants
+  * \brief
+  * \{
+  */
+
+/**
+ * \defgroup    PAD_Power_Mode PAD Power Mode
+ * \{
+ * \ingroup     PINMUX_Exported_Constants
+ */
+typedef enum
+{
+    PAD_NOT_PWRON,     //!< Disable pad power mode.
+    PAD_IS_PWRON = 1   //!< Enable pad power mode.
+} PADPowerMode_TypeDef;
+
+/** End of PAD_Power_Mode
+  * \}
+  */
+
+/**
+ * \defgroup    PAD_Output_Config PAD Output Config
+ * \{
+ * \ingroup     PINMUX_Exported_Constants
+ */
+typedef enum
+{
+    PAD_OUT_DISABLE,   //!< Disable pad output.
+    PAD_OUT_ENABLE     //!< Enable pad output.
+} PADOutputMode_TypeDef;
+
+/** End of PAD_Output_Config
+  * \}
+  */
+
+/**
+ * \defgroup    PAD_Output_Value PAD Output Value
+ * \{
+ * \ingroup     PINMUX_Exported_Constants
+ */
+typedef enum
+{
+    PAD_OUT_LOW,     //!< The pad outputs a low level.
+    PAD_OUT_HIGH     //!< The pad outputs a high level.
+} PADOutputValue_TypeDef;
+
+/** End of PAD_Output_Value
+  * \}
+  */
+
+/**
+ * \defgroup    PAD_Pull_Mode PAD Pull Mode
+ * \{
+ * \ingroup     PINMUX_Exported_Constants
+ */
+typedef enum
+{
+    PAD_PULL_DOWN,     //!< Enable the pull-down resistor function for the pad.
+    PAD_PULL_UP,       //!< Enable the pull-up resistor function for the pad.
+    PAD_PULL_NONE,     //!< Pad is in a floating state.
+} PADPullMode_TypeDef;
+
+/** End of PAD_Pull_Mode
+  * \}
+  */
+
+/**
+ * \defgroup    PAD_Pull_Strength_Mode PAD Pull Strength Mode
+ * \{
+ * \ingroup     PINMUX_Exported_Constants
+ */
+typedef enum
+{
+    PAD_PULL_WEAK,       //!< PAD pull mode is weak pull mode.
+    PAD_PULL_STRONG,     //!< PAD pull mode is srtong pull mode.
+} PADPullStrengthMode_TypeDef;
+
+/** End of PAD_Pull_Strength_Mode
+  * \}
+  */
+
+/**
+ * \defgroup    PAD_Driving_Current_Value PAD Driving Current Value
+ * \{
+ * \ingroup     PINMUX_Exported_Constants
+ * \brief       Detailed  level and current relationship refers to \ref PAD_Constant_Wrapper.
+ */
+typedef enum
+{
+    LEVEL0,   //!< The PAD driving current is set to level 0.
+    LEVEL2,   //!< The PAD driving current is set to level 2.
+#if (PAD_DRIVING_CURRENT_LEVEL == 4)
+    LEVEL1,   //!< The PAD driving current is set to level 1.
+    LEVEL3,   //!< The PAD driving current is set to level 3.
+#endif
+} PADDrivingCurrent_TypeDef;
+
+/** End of PAD_Driving_Current_Value
+  * \}
+  */
+
+/**
+ * \defgroup    PAD_WakeUp_Debounce PAD WakeUp Debounce
+ * \{
+ * \ingroup     PINMUX_Exported_Constants
+ */
+typedef enum
+{
+    PAD_WAKEUP_DEB_DISABLE,   //!< Disable pad wakeup debounce function.
+    PAD_WAKEUP_DEB_ENABLE     //!< Enable pad wakeup debounce function.
+} PADWakeupDebCmd_TypeDef;
+
+/** End of PAD_WakeUp_Debounce
+  * \}
+  */
+
+/**
+ * \defgroup    PAD_WakeUp PAD WakeUp
+ * \{
+ * \ingroup     PINMUX_Exported_Constants
+ */
+typedef enum
+{
+    PAD_WAKEUP_DISABLE,    //!< Disable PAD wakeup function.
+    PAD_WAKEUP_ENABLE      //!< Enable PAD wakeup function.
+} PADWakeupCmd_TypeDef;
+
+/** End of PAD_WakeUp
+  * \}
+  */
+
+/**
+ * \defgroup    PAD_Short_Pulse_WakeUp PAD Short Pulse WakeUp
+ * \{
+ * \ingroup     PINMUX_Exported_Constants
+ */
+typedef enum
+{
+    PAD_SHORT_PULSE_WAKEUP_DISABLE,    //!< Disable PAD short pulse wakeup function.
+    PAD_SHORT_PULSE_WAKEUP_ENABLE      //!< Enable PAD short pulse wakeup function.
+} PADSPWakeupCmd_TypeDef;
+
+/** End of PAD_Short_Pulse_WakeUp
+  * \}
+  */
+
+/**
+ * \defgroup    PAD_WakeUp_Polarity PAD WakeUp Polarity
+ * \{
+ * \ingroup     PINMUX_Exported_Constants
+ */
+typedef enum
+{
+    PAD_WAKEUP_POL_HIGH,    //!< PAD wakeup polarity is high.
+    PAD_WAKEUP_POL_LOW,     //!< PAD wakeup polarity is low.
+    PAD_WAKEUP_NONE         //!< PAD wakeup polarity is none.
+} PADWakeupPolarity_TypeDef;
+
+/** End of PAD_WakeUp_Polarity
+  * \}
+  */
+
+/**
+ * \defgroup    PAD_Debounce_Frequency PAD Debounce Frequency
+ * \{
+ * \ingroup     PINMUX_Exported_Constants
+ */
+typedef enum
+{
+    PAD_DEB_FREQ_32KHz,         //!< The frequency of PAD debounce is 32kHz.
+    PAD_DEB_FREQ_16KHz,         //!< The frequency of PAD debounce is 16kHz.
+    PAD_DEB_FREQ_8KHz = 3,      //!< The frequency of PAD debounce is 8kHz.
+    PAD_DEB_FREQ_4KHz = 7,      //!< The frequency of PAD debounce is 4kHz.
+    PAD_DEB_FREQ_2KHz = 15,     //!< The frequency of PAD debounce is 2kHz.
+    PAD_DEB_FREQ_1KHz = 31,     //!< The frequency of PAD debounce is 1kHz.
+    PAD_DEB_FREQ_500Hz = 63,    //!< The frequency of PAD debounce is 500Hz.
+} PADWakeupDebFreq_TypeDef;
+
+/** End of PAD_Debounce_Frequency
+  * \}
+  */
+
+/**
+ * \defgroup    PAD_Mode PAD_Mode
+ * \{
+ * \ingroup     PINMUX_Exported_Constants
+ */
+typedef enum
+{
+    PAD_SW_MODE,            //!< PAD pin is configured in software mode.
+#if PAD_SUPPORT_MULTI_CORE
+    PAD_V1_PINMUX_MODE,     //!< PAD pin is configured in vcore1 pinmux mode.
+    PAD_V2_V4_PINMUX_MODE,  //!< PAD pin is configured in Vcore2&4 pinmux mode.
+    PAD_V3_PINMUX_MODE,     //!< PAD pin is configured in Vcore3 pinmux mode.
+    PAD_PINMUX_MODE = PAD_V2_V4_PINMUX_MODE, //!< PAD pins are configured in pinmux mode.
+#elif PAD_SUPPORT_PON_DOMAIN
+    PAD_PON_MODE,          //!< PAD pin is configured in pon domain mode.
+    PAD_PINMUX_MODE,       //!< PAD pin is configured in pinmux mode.
+#else
+    PAD_PINMUX_MODE,       //!< PAD pin is configured in pinmux mode.
+#endif
+} PADMode_TypeDef;
+
+/** End of PAD_Mode
+  * \}
+  */
+
+#if PAD_SUPPORT_SLEEP_LED
+/**
+ * \defgroup    Sleep_LED_Pin Sleep LED Pin
+ * \{
+ * \ingroup     PINMUX_Exported_Constants
+ */
+typedef enum _SLEEP_LED_PIN
+{
+    SLEEP_LED_ADC_0,
+    SLEEP_LED_ADC_1,
+    SLEEP_LED_ADC_6,
+    SLEEP_LED_ADC_7,
+    SLEEP_LED_P1_0,
+    SLEEP_LED_P1_1,
+    SLEEP_LED_P1_4,
+    SLEEP_LED_P2_0,
+    SLEEP_LED_P2_1,
+    SLEEP_LED_P2_2,
+} SLEEP_LED_PIN;
+
+/** End of Sleep_LED_Pin
+  * \}
+  */
+#endif
+
+#if PAD_SUPPORT_FUNCTION_CONFIG
+/**
+ * \defgroup    PAD_Function_Config PAD Function Config
+ * \{
+ * \ingroup     PINMUX_Exported_Constants
+ */
+typedef enum _PAD_FUNCTION_CONFIG_VALUE
+{
+    AON_GPIO,
+    LED0,
+    LED1,
+    LED2,
+    CLK_REQ,
+    EXTRN_SWR_POW_SWR,
+    EXTRN_LDO1_POW_LDO,
+    EXTRN_LDO2_POW_LDO,
+    PAD_FUNC_MAX,
+} PAD_FUNCTION_CONFIG_VAL;
+
+/** End of PAD_Function_Config
+  * \}
+  */
+#endif
+
+#if PAD_SUPPORT_GET_POWER_GROUP
+/**
+ * \defgroup    PAD_Power_Group PAD Power Group
+ * \{
+ * \ingroup     PINMUX_Exported_Constants
+ */
+typedef enum _PIN_POWER_GROUP
+{
+    INVALID_PIN_GROUP  = 0,      //!< Invalid pad power group.
+    VDDIO1             = 1,      //!< Pad power group of VDDIO1 pin.
+    VDDIO2             = 2,      //!< Pad power group of VDDIO2 pin.
+    VDDIO3             = 3,      //!< Pad power group of VDDIO3 pin.
+    VDDIO4             = 4,      //!< Pad power group of VDDIO4 pin.
+    VDDIO5             = 5,      //!< Pad power group of VDDIO5 pin.
+    VCODEC             = 6,      //!< Pad power group of VCODEC pin.
+    GROUP_ADC          = 7,      //!< Pad power group of ADC pin.
+} T_PIN_POWER_GROUP;
+
+/** End of PAD_Power_Group
+  * \}
+  */
+#endif
+
+#if PAD_SUPPORT_ANALOG_MODE
+/**
+ * \defgroup    Pad_ANA_Mode Pad ANA Mode
+ * \{
+ * \ingroup     PINMUX_Exported_Constants
+ */
+typedef enum _ANA_MODE
+{
+    PAD_ANALOG_MODE,      //!< Config Hybrid pad analog function.
+    PAD_DIGITAL_MODE,     //!< Config Hybrid pad digital function.
+} ANA_MODE;
+
+/** End of Pad_ANA_Mode
+  * \}
+  */
+#endif
+
+#if (PAD_SUPPORT_ADPATER_WAKEUP | PAD_SUPPORT_MFB_WAKEUP)
+
+/**
+ * \defgroup    WakeUp_EN_Mode WakeUp EN Mode
+ * \{
+ * \ingroup     PINMUX_Exported_Constants
+ */
+typedef enum _WAKEUP_EN_MODE
+{
+    ADP_MODE,    //!< Wake up by adapter.
+    BAT_MODE,    //!< Wake up by battery.
+    MFB_MODE     //!< Wake up by MFB.
+} WAKEUP_EN_MODE;
+
+/** End of WakeUp_EN_Mode
+  * \}
+  */
+
+/**
+ * \defgroup    WakeUp_Polarity WakeUp Polarity
+ * \{
+ * \ingroup     PINMUX_Exported_Constants
+ */
+typedef enum _WAKEUP_POL
+{
+    POL_HIGH,    //!< PAD high-level trigger wakeup.
+    POL_LOW,     //!< PAD low-level trigger wakeup.
+} WAKEUP_POL;
+
+/** End of WakeUp_Polarity
+  * \}
+  */
+#endif
+
+#if PAD_SUPPORT_GET_OUTPUT_CTRL
+/**
+ * \defgroup    PAD_AON_Status PAD AON Status
+ * \{
+ * \ingroup     PINMUX_Exported_Constants
+ */
+typedef enum _PAD_AON_Status
+{
+    PAD_AON_OUTPUT_LOW,        //!< Pad AON output low level.
+    PAD_AON_OUTPUT_HIGH,       //!< Pad AON output high level.
+    PAD_AON_OUTPUT_DISABLE,    //!< Pad AON output disable.
+    PAD_AON_PINMUX_ON,         //!< Pad AON pinmux on.
+    PAD_AON_PIN_ERR            //!< Pad AON pin error.
+} PAD_AON_Status;
+
+/** End of PAD_AON_Status
+  * \}
+  */
+#endif
+
+/** End of PINMUX_Exported_Constants
+  * \}
+  */
+
+
+/*============================================================================*
+ *                         Functions
+ *============================================================================*/
+
+/**
+ * \defgroup    PINMUX_Exported_Functions PINMUX Exported Functions
+ * \{
+ * \ingroup     PINMUX
+ */
+
+/**
+ * \brief   Configure or reset all pins to idle mode.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void board_xxx_init(void)//XXX represents the name of the peripheral to be configured.
+ * {
+ *     Pinmux_Reset();
+ * }
+ * \endcode
+ */
+void Pinmux_Reset(void);
+
+/**
+ * \brief     Configure the specified pin to idle mode.
+ *
+ * \param[in] Pin_Num  Pin number to be configured. Refer to \ref Pin_Number.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void board_xxx_init(void)
+ * {
+ *     Pinmux_Deinit(P2_2);
+ * }
+ * \endcode
+ */
+void Pinmux_Deinit(uint8_t Pin_Num);
+
+#if PAD_SUPPORT_MULTI_CORE
+/**
+ * \brief  Deinit the VCORE1 IO function of one pin.
+ *
+ * \param[in] Pin_Num  Pin number to be configured. Refer to \ref Pin_Number.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void board_xxx_init(void)
+ * {
+ *     Pinmux_V1_Deinit(P2_2);
+ * }
+  * \endcode
+  */
+void Pinmux_V1_Deinit(uint8_t Pin_Num);
+
+/**
+ * \brief  Deinit the VCORE3 IO function of one pin.
+ *
+ * \param[in] Pin_Num  Pin number to be configured. Refer to \ref Pin_Number.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void board_xxx_init(void)
+ * {
+ *     Pinmux_CODEC_Deinit(P2_2);
+ * }
+  * \endcode
+  */
+void Pinmux_CODEC_Deinit(uint8_t Pin_Num);
+#endif
+
+/**
+ * \brief     Configure the specified pin to its corresponding IO function.
+ *
+ * \param[in] Pin_Num   Pin number to be configured. Refer to \ref Pin_Number.
+ * \param[in] Pin_Func  IO function of pin. Refer to \ref PIN_Function.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_uart_init(void)
+ * {
+ *     Pad_Config(P2_0, PAD_PINMUX_MODE, PAD_IS_PWRON, PAD_PULL_UP, PAD_OUT_DISABLE,
+               PAD_OUT_HIGH);
+ *     Pad_Config(P2_1, PAD_PINMUX_MODE, PAD_IS_PWRON, PAD_PULL_UP, PAD_OUT_DISABLE,
+               PAD_OUT_HIGH);
+
+ *     Pinmux_Config(P2_0, UART0_TX);
+ *     Pinmux_Config(P2_1, UART0_RX);
+ * }
+ * \endcode
+ */
+void Pinmux_Config(uint8_t Pin_Num, uint8_t Pin_Func);
+
+#if PAD_SUPPORT_MULTI_CORE
+/**
+ * \brief     Config the usage function of the selected pin.
+ *
+ * \param[in] Pin_Num   Pin number to be configured. Refer to \ref Pin_Number.
+ * \param[in] Pin_Func  IO function of pin. Refer to \ref PIN_Function.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_uart_init(void)
+ * {
+ *     Pad_Config(P2_0, PAD_PINMUX_MODE, PAD_IS_PWRON, PAD_PULL_UP, PAD_OUT_DISABLE,
+               PAD_OUT_HIGH);
+ *     Pad_Config(P2_1, PAD_PINMUX_MODE, PAD_IS_PWRON, PAD_PULL_UP, PAD_OUT_DISABLE,
+               PAD_OUT_HIGH);
+
+ *     Pinmux_CODEC_Config(P2_0, UART0_TX);
+ *     Pinmux_CODEC_Config(P2_1, UART0_RX);
+ * }
+ * \endcode
+ */
+void Pinmux_CODEC_Config(uint8_t Pin_Num, uint8_t Pin_Func);
+
+/**
+ * \brief  Config pin to VCORE1 domain dedicated mux.
+ *
+ * \param[in] Pin_Num   Pin number to be configured. Refer to \ref Pin_Number.
+ * \param[in] Pin_Func  IO function of pin. Refer to \ref PIN_Function.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_uart_init(void)
+ * {
+ *     Pad_Config(P2_0, PAD_PINMUX_MODE, PAD_IS_PWRON, PAD_PULL_UP, PAD_OUT_DISABLE,
+               PAD_OUT_HIGH);
+ *     Pad_Config(P2_1, PAD_PINMUX_MODE, PAD_IS_PWRON, PAD_PULL_UP, PAD_OUT_DISABLE,
+               PAD_OUT_HIGH);
+
+ *     Pinmux_CODEC_Config(P2_0, DMIC1_CLK);
+ *     Pinmux_CODEC_Config(P2_1, DMIC1_DAT);
+ * }
+ * \endcode
+ */
+
+void Pinmux_V1_Config(uint8_t Pin_Num, uint8_t Pin_Func);
+#endif
+
+#if PINMUX_SUPPORT_AON_CONFIG
+/**
+ * \brief  Configure the specified pin to its corresponding pin AON function
+ *
+ * \param[in] Pin_Func  AON function of pin. Refer to \ref PINMUX_AON_Function.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_uart_init(void)
+ * {
+ *     Pad_Config(XI32K, PAD_SW_MODE, PAD_IS_PWRON, PAD_PULL_UP, PAD_OUT_DISABLE, PAD_OUT_HIGH);
+ *     Pinmux_AON_Config(RTC_IN_PAD_32K_XI);
+ * }
+ * \endcode
+ */
+void Pinmux_AON_Config(uint16_t Pin_Func);
+#endif
+
+#if PINMUX_SUPPORT_HS_CONFIG
+/**
+ * \brief  Configure the specified pin to its corresponding pin high speed function.
+ *
+ * \param[in] Pin_Func  High Speed function. Refer to \ref PINMUX_HS_Function.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_spi_init(void)
+ * {
+ *      Pinmux_HS_Config(SPI0_HS);
+ * }
+ * \endcode
+ */
+void Pinmux_HS_Config(uint32_t Pin_Func);
+#endif
+
+/**
+ * \brief     Configure the relevant operation mode,
+ *            peripheral circuit and output level value in software mode of the specified pin
+ *
+ * \param[in] Pin_Num        Pin number to be configured. Refer to \ref Pin_Number.
+ * \param[in] AON_PAD_Mode   Use software mode or pinmux mode.
+ *                           This parameter can be one of the following values:
+ *                           \arg PAD_SW_MODE: pad pin is configured software mode.
+ *                           \arg PAD_PINMUX_MODE: pad pin is configured pinmux mode.
+ * \param[in] AON_PAD_PwrOn  Config power of pad.
+ *                           This parameter can be one of the following values:
+ *                           \arg PAD_NOT_PWRON: pad is not power.
+ *                           \arg PAD_IS_PWRON: pad is power on.
+ * \param[in] AON_PAD_Pull   Config pad pull mode.
+ *                           This parameter can be one of the following values:
+ *                           \arg PAD_PULL_NONE: Pull None.
+ *                           \arg PAD_PULL_UP: Pull up.
+ *                           \arg PAD_PULL_DOWN: Pull down.
+ * \param[in] AON_PAD_E      Config pad out put function.
+ *                           This parameter can be one of the following values:
+ *                           \arg PAD_OUT_DISABLE: Disable pin output.
+ *                           \arg PAD_OUT_ENABLE: Enable pad output.
+ * \param[in] AON_PAD_O      Config pin output level.
+ *                           This parameter can be one of the following values:
+ *                           - PAD_OUT_LOW: Pad output low level.
+ *                           - PAD_OUT_HIGH: Pad output high level.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_adc_init(void)
+ * {
+ *     Pad_Config(P2_0, PAD_SW_MODE, PAD_IS_PWRON, PAD_PULL_NONE, PAD_OUT_DISABLE, PAD_OUT_LOW);
+ *     Pad_Config(P2_1, PAD_SW_MODE, PAD_IS_PWRON, PAD_PULL_NONE, PAD_OUT_DISABLE, PAD_OUT_LOW);
+ * }
+ * \endcode
+ */
+void Pad_Config(uint8_t                 Pin_Num,
+                PADMode_TypeDef         AON_PAD_Mode,
+                PADPowerMode_TypeDef    AON_PAD_PwrOn,
+                PADPullMode_TypeDef     AON_PAD_Pull,
+                PADOutputMode_TypeDef   AON_PAD_E,
+                PADOutputValue_TypeDef  AON_PAD_O);
+
+#if PAD_SUPPORT_CONFIG_EXT
+/**
+ * \brief     Configure the relevant operation mode, peripheral circuit, pull resistor value and
+ *            output level value in software mode of the specified pin.
+ *
+ * \param[in] Pin_Num        Pin number to be configured. Refer to \ref Pin_Number.
+ * \param[in] AON_PAD_Mode   Use software mode or pinmux mode.
+ *                           This parameter can be one of the following values:
+ *                           \arg PAD_SW_MODE: Use software mode.
+ *                           \arg PAD_PINMUX_MODE: Use pinmux mode.
+ * \param[in] AON_PAD_PwrOn  Config power of pad.
+ *                           This parameter can be one of the following values:
+ *                           \arg PAD_SHUTDOWN: Shutdown power of pad.
+ *                           \arg PAD_IS_PWRON: Enable power of pad.
+ * \param[in] AON_PAD_Pull   Config pad pull mode.
+ *                           This parameter can be one of the following values:
+ *                           \arg PAD_PULL_NONE: No pull.
+ *                           \arg PAD_PULL_UP: Pull this pin up.
+ *                           \arg PAD_PULL_DOWN: Pull this pin down.
+ * \param[in] AON_PAD_E      Config pad output function, which only valid when PAD_SW_MODE.
+ *                           This parameter can be one of the following values:
+ *                           \arg PAD_OUT_DISABLE: Disable pin output.
+ *                           \arg PAD_OUT_ENABLE: Enable pad output.
+ * \param[in] AON_PAD_O      Config pin output level, which only valid when PAD_SW_MODE and output mode.
+ *                           This parameter can be one of the following values:
+ *                           \arg PAD_OUT_LOW: Pad output low.
+ *                           \arg PAD_OUT_HIGH: Pad output high.
+ * \param[in] AON_PAD_P      Config resistor value.
+ *                           This parameter can be one of the following values:
+ *                           - PAD_150K_PULL: pad pull 150k resistance.
+ *                           - PAD_15K_PULL: pad pull 15k resistance.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * void driver_adc_init(void)
+ * {
+ *     Pad_ConfigExt(P2_0, PAD_PINMUX_MODE, PAD_IS_PWRON, PAD_PULL_UP, PAD_OUT_DISABLE, PAD_OUT_LOW, PAD_150K_PULL);
+ *     Pad_ConfigExt(P2_1, PAD_PINMUX_MODE, PAD_IS_PWRON, PAD_PULL_UP, PAD_OUT_DISABLE, PAD_OUT_LOW, PAD_150K_PULL);
+ * }
+ * \endcode
+ */
+extern void Pad_ConfigExt(uint8_t Pin_Num,
+                          PADMode_TypeDef AON_PAD_Mode,
+                          PADPowerMode_TypeDef AON_PAD_PwrOn,
+                          PADPullMode_TypeDef AON_PAD_Pull,
+                          PADOutputMode_TypeDef AON_PAD_E,
+                          PADOutputValue_TypeDef AON_PAD_O,
+                          PADPullStrengthMode_TypeDef AON_PAD_P);
+#endif
+
+#if PAD_SUPPORT_DEDICATE_CONFIG
+/**
+ * \brief     Config the corresponding pad dedicated function.
+ *
+ * \param[in] Pin_Num  Pin number to be configured.
+ *                     This parameter is specific to certain Pins that support dedicated IO.
+ * \param[in] Status   Enable or disable the pad dedicate dedicated function.
+ *                     - ENABLE: Enable the pad dedicated function.
+ *                     - DISABLE: Disable the pad dedicated function.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_adc_init(void)
+ * {
+ *     Pad_Dedicated_Config(P2_2, Enable);
+ * }
+ * \endcode
+ */
+void Pad_Dedicated_Config(uint8_t Pin_Num, FunctionalState Status);
+#endif
+
+#if PAD_SUPPORT_CONFIG_DEFAULT
+/**
+ * \brief   Set all pins to the default state.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void board_xxx_init(void)
+ * {
+ *     Pad_AllConfigDefault();
+ * }
+ * \endcode
+ */
+extern void Pad_AllConfigDefault(void);
+#endif
+
+#if PAD_SUPPORT_WAKEUP_MULTI_GROUP
+bool System_WakeUpDebounceMultiGroupEnable(uint8_t Pin_Num);
+bool System_WakeUpDebounceMultiGroupDisable(uint8_t Pin_Num);
+#endif
+
+/**
+ * \brief     Enable the function of the wake-up system of the specified pin.
+ *
+ * \param[in] Pin_Num     Pin number to be configured. Refer to \ref Pin_Number.
+ * \param[in] Polarity    Polarity of wake-up system.
+ *                        This parameter can be the following:
+ *                        \arg PAD_WAKEUP_POL_HIGH: Use high level wake-up polarity.
+ *                        \arg PAD_WAKEUP_POL_LOW: Use low level wake-up polarity.
+ * \param[in] DebounceEn  Enable delay function.
+ *                        - PAD_WK_DEBOUNCE_DISABLE: Disable wake-up debounce function.
+ *                        - PAD_WK_DEBOUNCE_ENABLE: Enable wake-up debounce function.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * //IO enter dlps call back function.
+ * void io_uart_dlps_enter(void)
+ * {
+ *     // Switch pad to software mode
+ *     Pad_ControlSelectValue(P2_0, PAD_SW_MODE);//tx pin
+ *     Pad_ControlSelectValue(P2_1, PAD_SW_MODE);//rx pin
+ *
+ *     System_WakeUpPinEnable(P2_1, PAD_WAKEUP_POL_LOW, PAD_WK_DEBOUNCE_DISABLE);
+ * }
+ * \endcode
+ */
+void System_WakeUpPinEnable(uint8_t Pin_Num, uint8_t Polarity, uint8_t DebounceEn);
+
+/**
+ * \brief     Disable the function of the wake-up system of the specified pin.
+ *
+ * \param[in] Pin_Num  Pin number to be configured. Refer to \ref Pin_Number.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * #define UART_RX_PIN                P4_1
+ *
+ * //System interrupt handler function, for wake-up pin.
+ * void System_Handler(void)
+ * {
+ *     if (System_WakeUpInterruptValue(UART_RX_PIN) == SET)
+ *     {
+ *         Pad_ClearWakeupINTPendingBit(UART_RX_PIN);
+ *         System_WakeUpPinDisable(UART_RX_PIN);
+ *         //Add user code here.
+ *     }
+ * }
+ * \endcode
+ */
+void System_WakeUpPinDisable(uint8_t Pin_Num);
+
+/**
+ * \brief   Get pin interrupt status.
+ *
+ * \param[in] Pin_Num  Pin number to be configured. Refer to \ref Pin_Number.
+ *
+ * \return Interrupt status.
+ *         - 1: Pin wake up interrupt status is true.
+ *         - 0: Pin wake up interrupt status is false.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * #define UART_RX_PIN                P4_1
+ *
+ * //System interrupt handler function, for wakeup pin.
+ * void System_Handler(void)
+ * {
+ *     if (System_WakeUpInterruptValue(UART_RX_PIN) == SET)
+ *     {
+ *         Pad_ClearWakeupINTPendingBit(UART_RX_PIN);
+ *         System_WakeUpPinDisable(UART_RX_PIN);
+ *         //Add user code here.
+ *     }
+ * }
+ * \endcode
+ */
+uint8_t System_WakeUpInterruptValue(uint8_t Pin_Num);
+
+/**
+ * \brief  Enable or disable wake-up debounce function.
+ *
+ * \param[in] Pin_Num               Pin number to be configured. Refer to \ref Pin_Number.
+ * \note                            Pin_Num is invalid parameter for rtl87x2g series so that any pin can be filled in.
+ * \param[in] PADWakeupCmd_TypeDef  Wake-up system enable or disable
+ *                                  - PAD_WAKEUP_DISABLE: Disable wake-up function.
+ *                                  - PAD_WAKEUP_DISABLE: Enable wake-up function.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ *void System_WakeUpPinEnable(uint8_t Pin_Num, uint8_t Polarity, uint8_t DebounceEn)
+ *{
+ *    if(Pin_Num >= MAX_PIN_NUM)
+ *    {
+ *        return;
+ *    }
+ *
+ *    Pad_SetWakeupPolarity(Pin_Num, Polarity);
+ *    Pad_WakeupDebounce_Cmd(Pin_Num, DebounceEn);
+ *    if (PAD_WAKEUP_DEB_ENABLE == DebounceEn)
+ *    {
+ *        System_WakeUpDebounceCmd(Pin_Num, PAD_WAKEUP_ENABLE);
+ *    }
+ *    Pad_Wakeup_Cmd(Pin_Num, ENABLE);
+ *}
+ * \endcode
+ */
+void System_WakeUpDebounceCmd(uint8_t Pin_Num, PADWakeupCmd_TypeDef Status);
+
+/**
+ * \brief   Config wake up system debounce time.
+ *
+ * \param[in] Pin_Num  Pin number to be configured. Refer to \ref Pin_Number.
+ * \note               Pin_Num is invalid parameter for rtl87x2g series so that any pin can be filled in.
+ * \param[in] time_ms  Debounce time. Unit: ms.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void board_xxx_init(void)
+ * {
+ *     System_WakeUpDebounceTime(10);
+ * }
+ * \endcode
+ */
+void System_WakeUpDebounceTime(uint8_t Pin_Num, uint8_t time_ms);
+
+/**
+ * \brief   Config wake up system debounce time.
+ *
+ * \param[in] Pin_Num  Pin number to be configured. Refer to \ref Pin_Number.
+ * \note               Pin_Num is invalid parameter for rtl87x2g series so that any pin can be filled in.
+ * \param[in] time_us  Debounce time. Unit: us.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void board_xxx_init(void)
+ * {
+ *     System_WakeUpDebounceTimeUs(1000);
+ * }
+ * \endcode
+ */
+void System_WakeUpDebounceTimeUs(uint8_t Pin_Num, uint8_t time_us);
+
+/**
+ * \brief  Get debounce wake up status.
+ *
+ * \param[in] Pin_Num  Pin number to be configured. Refer to \ref Pin_Number.
+ * \note               Pin_Num is invalid parameter for rtl87x2g series so that any pin can be filled in.
+ *
+ * \return Debounce wakeup status.
+ *         - 1: Pin debounce wakeup status is true.
+ *         - 0: Pin debounce wakeup status is false.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void board_xxx_init(void)
+ * {
+ *     uint8_t WakeupDebounceStatus = System_WakeupDebounceStatus;
+ * }
+ * \endcode
+ */
+
+uint8_t System_WakeupDebounceStatus(uint8_t Pin_Num);
+
+/**
+ * \brief  Clear debounce wake up status. Call this API will clear the debunce wakeup status bit.
+ *
+ * \param[in] Pin_Num  Pin number to be configured. Refer to \ref Pin_Number.
+ * \note               Pin_Num is invalid parameter for rtl87x2g series so that any pin can be filled in.
+ *
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void dlps_store(void)
+ * {
+ *     System_WakeupDebounceClear(P0_0);
+ * }
+ * \endcode
+ */
+void System_WakeupDebounceClear(uint8_t Pin_Num);
+
+/**
+ * \brief     Configure the driving current.
+ *
+ * \param[in] Pin_Num              Pin number to be configured. Refer to \ref Pin_Number.
+ * \param[in] PAD_Driving_Current  This parameter sets the driving current.
+ *                                 Refer to \ref PADDrivingCurrent_TypeDef.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void board_xxx_init(void)
+ * {
+ *     Pad_SetDrivingCurrent(P2_0, PAD_DRIVING_CURRENT_4mA);
+ * }
+ * \endcode
+ */
+void Pad_SetDrivingCurrent(uint8_t Pin_Num, PADDrivingCurrent_TypeDef PAD_Driving_Current);
+
+/**
+ * \brief     Set pin control mode.
+ *
+ * \param[in] Pin_Num  Pin number to be configured. Refer to \ref Pin_Number.
+ * \param[in] value    This parameter sets the pin mode.
+ *                     This parameter can be the following:
+ *                     - PAD_SW_MODE: Software mode.
+ *                     - PAD_PINMUX_MODE: Pinmux mode.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void board_xxx_init(void)
+ * {
+ *     Pad_SetControlMode(P2_0, PAD_SW_MODE);
+ * }
+ * \endcode
+ */
+void Pad_SetControlMode(uint8_t Pin_Num, PADMode_TypeDef PAD_Mode);
+
+/**
+ * \brief     Enable or disable pad output mode.
+ *
+ * \param[in] Pin_Num  Pin number to be configured. Refer to \ref Pin_Number.
+ * \param[in] value    This parameter sets whether the pin outputs the level in software mode.
+ *                     This parameter can be enumerated \ref PAD_Output_Config of the values:
+ *                     - PAD_OUT_DISABLE: Disable output.
+ *                     - PAD_OUT_ENABLE: Enable output.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void pad_demo(void)
+ * {
+ *     Pad_OutputEnableValue(P2_0, PAD_OUT_ENABLE);
+ * }
+ * \endcode
+ */
+void Pad_OutputCmd(uint8_t Pin_Num, PADOutputMode_TypeDef Status);
+
+/**
+ * \brief     Configure pad output level.
+ *
+ * \param[in] Pin_Num  Pin number to be configured. Refer to \ref Pin_Number.
+ * \param[in] value    Config pin output level.
+ *                     This parameter can be one of the following values:
+ *                     - PAD_OUT_LOW: Pad output low.
+ *                     - PAD_OUT_HIGH: Pad output high.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void board_xxx_init(void)
+ * {
+ *     Pad_OutputControlValue(P2_0, PAD_OUT_HIGH);
+ * }
+ * \endcode
+ */
+void Pad_SetOutputLevel(uint8_t Pin_Num, uint8_t value);
+
+/**
+ * \brief     Enable or disable pad pull resistance.
+ *
+ * \param[in] Pin_Num  Pin number to be configured. Refer to \ref Pin_Number.
+ * \param[in] value    This parameter enable or disable the the pad pin pull resistance.
+ *                     This parameter can be the following value:
+ *                     - DISABLE: Disable pad pull function.
+ *                     - ENABLE: Enable  pad pull function.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void board_xxx_init(void)
+ * {
+ *     Pad_PullEnableValue(P2_0, ENABLE);
+ * }
+ * \endcode
+ */
+void Pad_PullCmd(uint8_t Pin_Num, FunctionalState Status);
+
+/**
+ * \brief     Pad pull-up/pull-down resistance function selection.
+ *
+ * \param[in] Pin_Num        Pin number to be configured. Refer to \ref Pin_Number.
+ * \param[in] PAD_Pull_Mode  Config pad pull mode.
+ *                           This parameter can be the following values, refer to \ref PAD_Pull_Mode.
+ *                           - PAD_PULL_NONE: No pull.
+ *                           - PAD_PULL_UP: Pull this pin up
+ *                           - PAD_PULL_DOWN: Pull this pin down.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void board_xxx_init(void)
+ * {
+ *     Pad_PullUpOrDownValue(P2_0, 1);
+ * }
+ * \endcode
+ */
+void Pad_SetPullMode(uint8_t Pin_Num, PADPullMode_TypeDef PAD_Pull_Mode);
+
+/**
+ * \brief     Configure the strength of pull-up/pull-down resistance.
+ *
+ * \param[in] Pin_Num                 Pin number to be configured. Refer to \ref Pin_Number.
+ * \param[in] PAD_Pull_Strength_Mode  This parameter sets the strength of pull-up/pull-down resistance.
+ *                                    This parameter can be the following values, refer to \ref PAD_Pull_Strength_Mode.
+ *                                    - PAD_PULL_WEAK: Resistance weak pull.
+ *                                    - PAD_PULL_STRONG: Resistance strong pull.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void board_xxx_init(void)
+ * {
+ *     Pad_PullConfigValue(P2_0, PAD_PULL_STRONG);
+ * }
+ * \endcode
+ */
+void Pad_SetPullStrength(uint8_t Pin_Num, PADPullStrengthMode_TypeDef PAD_Pull_Strength_Mode);
+
+/**
+ * \brief     Set pin power mode.
+ *
+ * \param[in] Pin_Num   Pin number to be configured. Refer to \ref Pin_Number.
+ * \param[in] PWR_Mode  Config power of pad.
+ *                      This parameter can be the following values, refer to \ref PAD_Power_Mode.
+ *                      - PAD_NOT_PWRON: Power off.
+ *                      - PAD_IS_PWRON: Power on.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void board_xxx_init(void)
+ * {
+ *     Pad_PowerOrShutDownValue(P2_0, PAD_NOT_PWRON);
+ * }
+ * \endcode
+ */
+void Pad_PowerCmd(uint8_t Pin_Num, PADPowerMode_TypeDef PWR_Mode);
+
+/**
+ * \brief     Clear the interrupt pending bit of the specified pin.
+ *
+ * \param[in] Pin_Num  Pin number to be configured. Refer to \ref Pin_Number.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void board_xxx_init(void)
+ * {
+ *     Pad_ClearWakeupINTPendingBit(P2_0);
+ * }
+ * \endcode
+ */
+void Pad_ClearWakeupINTPendingBit(uint8_t Pin_Num);
+
+/**
+ * \brief     Clear all wake up pin interrupt pending bit.
+ *
+ * \param[in] Pin_Num  Pin number to be configured. Refer to \ref Pin_Number.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void board_xxx_init(void)
+ * {
+ *     Pad_ClearAllWakeupINT();
+ * }
+ * \endcode
+ */
+void Pad_ClearAllWakeupINT(void);
+
+/**
+ * \brief  Short pulse wakeup function.
+ *
+ * \param[in] Status  PAD_SHORT_PULSE_WAKEUP_DISABLE or PAD_SHORT_PULSE_WAKEUP_ENABLE.
+ *                    This parameter refer to \ref PAD_SHORT_PULSE_WAKEUP_EN.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void board_xxx_init(void)
+ * {
+ *     Pad_ShortPulseWakeUpCmd(PAD_SHORT_PULSE_WAKEUP_ENABLE);
+ * }
+ * \endcode
+ */
+
+void Pad_ShortPulseWakeUpCmd(PADSPWakeupCmd_TypeDef Status);
+
+#if PAD_SUPPORT_AON_WAKEUP
+/**
+ * \brief  Get aon wake up int.
+ *
+ * \return  Wakeup intterupt.
+ *          - bit0: aon pad wake up int
+ *          - bit1: aon lpc0 wake up int
+ *          - bit2: aon lpc1 wake up int
+ *          - bit3: aon qdec wake up int
+ *          - bit4: aon vadbuf wake up int
+ *          - bit5: aon vad wake up int
+ *          - bit6: aon usb wake up int
+ *          - bit7: aon rtc wake up int
+ *          - bit8: aon pf rtc wake up int
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void board_xxx_init(void)
+ * {
+ *     get_aon_wakeup_int();
+ * }
+ * \endcode
+ */
+
+uint32_t get_aon_wakeup_int(void);
+
+/**
+ * \brief  Clear aon wake up int.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void board_xxx_init(void)
+ * {
+ *     clear_aon_wakeup_int();
+ * }
+ * \endcode
+ */
+void clear_aon_wakeup_int(void);
+#endif
+
+#if PAD_SUPPORT_GET_OUTPUT_CTRL
+/**
+ * \brief   Get pad current output/input setting.
+ *
+ * \param[in] Pin_Num  Pin number to be configured. Refer to \ref Pin_Number.
+ *
+ * \return   Refer to \ref PAD_AON_Status.
+ *           - PAD_AON_OUTPUT_LOW: Pad AON output low level.
+ *           - PAD_AON_OUTPUT_HIGH: Pad AON output high level.
+ *           - PAD_AON_OUTPUT_DISABLE: Pad AON output disable.
+ *           - PAD_AON_PINMUX_ON: Pad AON pinmux on.
+ *           - PAD_AON_PIN_ERR: Pad AON pin error.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void pad_demo(void)
+ * {
+ *     if (Pad_GetOutputCtrl(P2_1) == PAD_AON_OUTPUT_LOW)
+ *     {
+ *         //Add user code here.
+ *     }
+ * }
+ * \endcode
+ */
+uint8_t Pad_GetOutputCtrl(uint8_t Pin_Num);
+#endif
+
+#if PAD_SUPPORT_GET_POWER_GROUP
+/**
+ * \brief   Get the pin power group.
+ *
+ * \param[in] pin  pin of set only VDDIO pin.
+ *
+ * \return   get the power group of the pin. Please refer to \ref PAD_Power_Group.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void pad_demo(void)
+ * {
+ *     Pad_GetPowerGroup(P2_1);
+ * }
+ * \endcode
+ */
+T_PIN_POWER_GROUP  Pad_GetPowerGroup(uint8_t pin);
+#endif
+
+#if PAD_SUPPORT_GET_PIN_NAME
+/**
+ * \brief   Get the pin name in string.
+ *
+ * \param[in] pin_num  Pin number to be configured. Refer to \ref Pin_Number.
+ *
+ * \return   pin name or null.
+ *           - pin name
+ *           - null due to invalid pin index.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * void pad_demo(void)
+ * {
+ *     Pad_GetPinName(P2_1);
+ * }
+ * \endcode
+ */
+const char *Pad_GetPinName(uint8_t pin_num);
+#endif
+
+#if PAD_SUPPORT_ANALOG_MODE
+/**
+ * \brief   Config Hybrid pad analog/digital functions.
+ *
+ * \param[in] pin   Pin number to be configured. Refer to \ref Pin_Number.
+ * \param[in] mode  Please refer to \ref Pad_ANA_Mode.
+ *                  This parameter can be: PAD_ANALOG_MODE/PAD_DIGITAL_MODE.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * void pad_demo(void)
+ * {
+ *     Pad_AnalogMode(P2_1, PAD_ANALOG_MODE);
+ * }
+ * \endcode
+ */
+void Pad_AnalogMode(uint8_t pin, ANA_MODE mode);
+#endif
+
+#if (PAD_SUPPORT_ADPATER_WAKEUP | PAD_SUPPORT_MFB_WAKEUP)
+/**
+ * \brief   Config the system wakeup mode.
+ *
+ * \param[in] mode      Mode of set, this parameter can refer to \ref WakeUp_EN_Mode.
+ *                      This parameter can be one of the following values:
+ *                      \arg ADP_MODE: Wake up by adapter.
+ *                      \arg BAT_MODE: Wake up by battery.
+ *                      \arg MFB_MODE: Wake up by MFB.
+ *                      \arg USB_MODE: Wake up by USB.
+ * \param[in] pol       Polarity to wake up.
+ *                      This parameter can be one of the following values:
+ *                      \arg POL_HIGH: Use high level wakeup.
+ *                      \arg POL_LOW: Use low level wakeup.
+ * \param[in] NewState  Enable or disable wake up.
+ *                      This parameter can be one of the following values:
+ *                      \arg ENABLE: Enable the system wake up at specified polarity.
+ *                      \arg DISABLE: Disable the system wake up at specified polarity.
+ *
+ * \return     Config the system wakeup mode fail or success.
+ *             - 0: Config success.
+ *             - 1: Config fail due to wrong mode.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * void adapter_wake_up_enable(void)
+ * {
+ *     //adapter mode is WAKE_UP_GENERAL
+ *     Pad_WakeUpConfig(ADP_MODE, POL_HIGH, ENABLE);
+ * }
+ * \endcode
+ */
+uint8_t  Pad_WakeUpCmd(WAKEUP_EN_MODE mode, WAKEUP_POL pol, FunctionalState NewState);
+#endif
+
+#if PAD_SUPPORT_ADPATER_WAKEUP
+/**
+ * \brief   Configure the adpater wake-up system functions in power off(shipping) mode.
+ *
+ * \param[in] NewState  Enable or disable adpater wake up.
+ *                      This parameter can be one of the following values:
+ *                      \arg ENABLE: Enable adpater wake up system at specified polarity.
+ *                      \arg DISABLE: Disable adpater wake up system.
+ * \param[in] pol       Polarity to wake up.
+ *                      This parameter can be one of the following values:
+ *                      - POL_HIGH: Use high level wakeup.
+ *                      - POL_LOW: Use low level wakeup.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * void adapter_wake_up_enable(void)
+ * {
+ *     //adapter mode is wake_up_power_off
+ *     System_SetAdpWakeUpFunction(ENABLE, POL_HIGH);
+ * }
+ * \endcode
+ */
+void System_SetAdpWakeUpFunction(FunctionalState NewState, WAKEUP_POL pol);
+#endif
+
+#if PAD_SUPPORT_MFB_WAKEUP
+/**
+ * \brief   Configure the MFB wake-up system functions in power off(shipping) mode.
+ *
+ * \param[in] NewState  Enable or disable MFB wake up.
+ *                      This parameter can be one of the following values:
+ *                      - ENABLE: Enable MFB wake up system.
+ *                      - DISABLE: Disable MFB wake up system.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * //io_test_set_mfb_mode is POWER_OFF_WAKEUP_TEST
+ * void mfb_wake_up_enable(void)
+ * {
+ *     System_SetMFBWakeUpFunction(ENABLE);
+ * }
+ * \endcode
+ */
+void System_SetMFBWakeUpFunction(FunctionalState NewState);
+#endif
+
+/** End of PINMUX_Exported_Functions
+  * \}
+  */
+
+/** End of PINMUX
+  * \}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RTL_PINMUX_H */
+
+
diff --git a/bee/drivers/pinmux/src/device/rtl87x2g/rtl_pinmux_def.h b/bee/drivers/pinmux/src/device/rtl87x2g/rtl_pinmux_def.h
new file mode 100644
index 00000000..05b6cd7d
--- /dev/null
+++ b/bee/drivers/pinmux/src/device/rtl87x2g/rtl_pinmux_def.h
@@ -0,0 +1,431 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef RTL_PINMUX_DEF_H
+#define RTL_PINMUX_DEF_H
+
+#include "utils/rtl_utils.h"
+#include "address_map.h"
+#include "aon_reg.h"
+
+#ifdef  __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/*============================================================================*
+ *                          PINMUX Defines
+ *============================================================================*/
+/** \defgroup PINMUX      PINMUX
+  * \brief
+  * \{
+  */
+
+/** \defgroup PINMUX_Exported_Constants PINMUX Exported Constants
+  * \brief
+  * \{
+  */
+
+/**
+ * \defgroup PINMUX_Defines PINMUX Defines
+ * \{
+ * \ingroup  PINMUX_Exported_Constants
+ */
+#define PINMUX_SUPPORT_AON_CONFIG                      (1)   //!< The definition supports AON configuration.
+#define PINMUX_SUPPORT_HS_CONFIG                       (1)   //!< The definition supports HS configuration.
+#define PAD_DRIVING_CURRENT_LEVEL                      (4)   //!< The definition supports pad driving current level.
+#define PAD_SUPPORT_DEDICATE_CONFIG                    (1)   //!< The definition supports dedicate config.
+#define PAD_SUPPORT_MULTI_CORE                         (0)   //!< The function is not supported.
+#define PAD_SUPPORT_AON_WAKEUP                         (0)   //!< The function is not supported.
+#define PAD_SUPPORT_CONFIG_EXT                         (0)   //!< The function is not supported.
+#define PAD_SUPPORT_CONFIG_DEFAULT                     (0)   //!< The function is not supported.
+#define PAD_SUPPORT_SLEEP_LED                          (0)   //!< The function is not supported.
+#define PAD_SUPPORT_FUNCTION_CONFIG                    (0)   //!< The function is not supported.
+#define PAD_SUPPORT_GET_POWER_GROUP                    (0)   //!< The function is not supported.
+#define PAD_SUPPORT_GET_PIN_NAME                       (0)   //!< The function is not supported.
+#define PAD_SUPPORT_GET_OUTPUT_CTRL                    (0)   //!< The function is not supported.
+#define PAD_SUPPORT_ANALOG_MODE                        (0)   //!< The function is not supported.
+#define PAD_SUPPORT_ADPATER_WAKEUP                     (0)   //!< The function is not supported.
+#define PAD_SUPPORT_MFB_WAKEUP                         (0)   //!< The function is not supported.
+
+/** End of PINMUX_Defines
+  * \}
+  */
+
+/** End of PINMUX_Exported_Constants
+  * \}
+  */
+
+/** End of PINMUX
+  * \}
+  */
+
+/*============================================================================*
+ *                         PINMUX Registers Memory Map
+ *============================================================================*/
+/**
+ * \brief Pinmux Register
+ */
+
+typedef struct                      /*!< Pinmux Structure */
+{
+    __IO uint32_t CFG[21];          /*!<  */
+} PINMUX_TypeDef;
+
+/*============================================================================*
+ *                         PINMUX Declaration
+ *============================================================================*/
+/** \defgroup PINMUX      PINMUX
+  * \brief
+  * \{
+  */
+
+/** \defgroup PINMUX_Exported_Constants PINMUX Exported Constants
+  * \brief
+  * \{
+  */
+
+/**
+ * \defgroup PINMUX_Declaration PINMUX Declaration
+ * \{
+ * \ingroup  PINMUX_Exported_Constants
+ */
+#define PINMUX          ((PINMUX_TypeDef *) PINMUX_REG_BASE)   //!< PINMUX base address.
+
+/** End of PINMUX_Declaration
+  * \}
+  */
+
+/** End of PINMUX_Exported_Constants
+  * \}
+  */
+
+/** End of PINMUX
+  * \}
+  */
+
+/*============================================================================*
+ *                         PINMUX Private Types
+ *============================================================================*/
+typedef struct
+{
+    uint32_t pinmux_reg[21];
+} PINMUXStoreReg_Typedef;
+
+/*============================================================================*
+ *                         PINMUX Constants
+ *============================================================================*/
+/** \defgroup PINMUX      PINMUX
+  * \brief
+  * \{
+  */
+
+/** \defgroup PINMUX_Exported_Constants PINMUX Exported Constants
+  * \brief
+  * \{
+  */
+
+/**
+ * \defgroup    PIN_Function PIN Function
+ * \{
+ * \ingroup     PINMUX_Exported_Constants
+ */
+
+#define IDLE_MODE                   0
+
+#define UART0_TX                    1
+#define UART0_RX                    2
+#define UART0_CTS                   3
+#define UART0_RTS                   4
+#define UART1_TX                    5
+#define UART1_RX                    6
+#define UART1_CTS                   7
+#define UART1_RTS                   8
+#define UART2_TX                    9
+#define UART2_RX                    10
+#define UART2_CTS                   11
+#define UART2_RTS                   12
+#define UART3_TX                    13
+#define UART3_RX                    14
+#define UART3_CTS                   15
+#define UART3_RTS                   16
+#define UART4_TX                    17
+#define UART4_RX                    18
+#define UART4_CTS                   19
+#define UART4_RTS                   20
+#define UART5_TX                    21
+#define UART5_RX                    22
+#define UART5_CTS                   23
+#define UART5_RTS                   24
+
+#define I2C0_CLK                    29
+#define I2C0_DAT                    30
+#define I2C1_CLK                    31
+#define I2C1_DAT                    32
+#define I2C2_CLK                    33
+#define I2C2_DAT                    34
+#define I2C3_CLK                    35
+#define I2C3_DAT                    36
+#define SPI0_CLK_MASTER             37
+#define SPI0_MO_MASTER              38
+#define SPI0_MI_MASTER              39
+#define SPI0_CSN_0_MASTER           40
+#define SPI0_CSN_1_MASTER           41
+#define SPI0_CSN_2_MASTER           42
+#define SPI0_CSN_0_SLAVE            43
+#define SPI0_CLK_SLAVE              44
+#define SPI0_SO_SLAVE               45
+#define SPI0_SI_SLAVE               46
+#define SPI1_CLK_MASTER             47
+#define SPI1_MO_MASTER              48
+#define SPI1_MI_MASTER              49
+#define SPI1_CSN_0_MASTER           50
+#define SPI1_CSN_1_MASTER           51
+#define SPI1_CSN_2_MASTER           52
+#define SPI2W_DATA                  53
+#define SPI2W_CLK                   54
+#define SPI2W_CS                    55
+
+#define ENPWM0_P                    65
+#define ENPWM0_N                    66
+#define ENPWM1_P                    67
+#define ENPWM1_N                    68
+#define ENPWM2_P                    69
+#define ENPWM2_N                    70
+#define ENPWM3_P                    71
+#define ENPWM3_N                    72
+
+#define TIMER_PWM2                  83
+#define TIMER_PWM3                  84
+
+#define ISO7816_RST                 85
+#define ISO7816_CLK                 86
+#define ISO7816_IO                  87
+#define ISO7816_VCC_EN              88
+#define DWGPIO                      89
+#define IRDA_TX                     90
+#define IRDA_RX                     91
+#define TIMER_PWM4                  92
+#define TIMER_PWM5                  93
+#define TIMER_PWM6                  94
+#define TIMER_PWM7                  95
+#define TIMER_PWM2_P                96
+#define TIMER_PWM2_N                97
+#define TIMER_PWM3_P                98
+#define TIMER_PWM3_N                99
+#define KEY_COL_0                   100
+#define KEY_COL_1                   101
+#define KEY_COL_2                   102
+#define KEY_COL_3                   103
+#define KEY_COL_4                   104
+#define KEY_COL_5                   105
+#define KEY_COL_6                   106
+#define KEY_COL_7                   107
+#define KEY_COL_8                   108
+#define KEY_COL_9                   109
+#define KEY_COL_10                  110
+#define KEY_COL_11                  111
+#define KEY_COL_12                  112
+#define KEY_COL_13                  113
+#define KEY_COL_14                  114
+#define KEY_COL_15                  115
+#define KEY_COL_16                  116
+#define KEY_COL_17                  117
+#define KEY_COL_18                  118
+#define KEY_COL_19                  119
+#define KEY_ROW_0                   120
+#define KEY_ROW_1                   121
+#define KEY_ROW_2                   122
+#define KEY_ROW_3                   123
+#define KEY_ROW_4                   124
+#define KEY_ROW_5                   125
+#define KEY_ROW_6                   126
+#define KEY_ROW_7                   127
+#define KEY_ROW_8                   128
+#define KEY_ROW_9                   129
+#define KEY_ROW_10                  130
+#define KEY_ROW_11                  131
+
+#define km4_clk_div_4               138
+//#define DSP_GPIO_OUT                139
+//#define DSP_JTCK                    140
+//#define DSP_JTDI                    141
+//#define DSP_JTDO                    142
+//#define DSP_JTMS                    143
+//#define DSP_JTRST                   144
+//#define dsp_clk_div_4               145
+
+#define card_detect_n_0             147
+#define biu_volt_reg_0              148
+#define back_end_power_0            149
+#define card_int_n_sdhc_0           150
+
+#define CAN_TX                      155
+#define CAN_RX                      156
+
+#define LRC_SPORT1                  157
+#define BCLK_SPORT1                 158
+#define ADCDAT_SPORT1               159
+#define DACDAT_SPORT1               160
+
+#define DMIC1_CLK                   162
+#define DMIC1_DAT                   163
+#define LRC_I_CODEC_SLAVE           164
+#define BCLK_I_CODEC_SLAVE          165
+#define SDI_CODEC_SLAVE             166
+#define SDO_CODEC_SLAVE             167
+
+#define LRC_SPORT0                  172
+#define BCLK_SPORT0                 173
+#define ADCDAT_SPORT0               174
+#define DACDAT_SPORT0               175
+#define MCLK_OUT                    176
+
+#define MCLK_IN                     189
+#define LRC_RX_CODEC_SLAVE          190
+#define LRC_RX_SPORT0               191
+#define LRC_RX_SPORT1               192
+
+#define PDM_DATA                    196
+#define PDM_CLK                     197
+
+#define I2S1_LRC_TX_SLAVE           198
+#define I2S1_BCLK_SLAVE             199
+#define I2S1_SDI_SLAVE              200
+#define I2S1_SDO_SLAVE              201
+#define I2S1_LRC_RX_SLAVE           202
+
+#define BT_COEX_I_0                 216
+#define BT_COEX_I_1                 217
+#define BT_COEX_I_2                 218
+#define BT_COEX_I_3                 219
+#define BT_COEX_O_0                 220
+#define BT_COEX_O_1                 221
+#define BT_COEX_O_2                 222
+#define BT_COEX_O_3                 223
+#define PTA_I2C_CLK_SLAVE           224
+#define PTA_I2C_DAT_SLAVE           225
+#define PTA_I2C_INT_OUT             226
+#define EN_EXPA                     227
+#define EN_EXLNA                    228
+#define SEL_TPM_SW                  229
+#define SEL_TPM_N_SW                230
+#define ANT_SW0                     231
+#define ANT_SW1                     232
+#define ANT_SW2                     233
+#define ANT_SW3                     234
+#define ANT_SW4                     235
+#define ANT_SW5                     236
+#define phy_gpio_1                  237
+#define phy_gpio_2                  238
+#define slow_debug_mux_1            239
+#define slow_debug_mux_2            240
+
+#define test_mode                   246
+
+#define SWD_CLK                     253
+#define SWD_DIO                     254
+#define dig_debug                   255
+
+/** End of PIN_Function
+  * \}
+  */
+
+/**
+ * \defgroup    PAD_Aon_Mux PAD Aon Mux
+ * \{
+ * \ingroup     PINMUX_Exported_Constants
+ */
+#define RTC_IN_NONE         0x0800
+#define RTC_IN_PAD_32K_XI   0x0801
+#define RTC_IN_PAD_P2_4     0x0802
+
+#define QDPH0_IN_NONE       0x0F00
+#define QDPH0_IN_P1_3_P1_4  0x0F01
+#define QDPH0_IN_P5_6_P5_7  0x0F02
+#define QDPH0_IN_P9_0_P9_1  0x0F03
+
+/** End of PAD_Aon_Mux
+  * \}
+  */
+
+/**
+ * \defgroup    PAD_HS_Mux PAD HSMux
+ * \{
+ * \ingroup     PINMUX_Exported_Constants
+ */
+#define DISPLAY_CONTROLLER_HS_MUX     0x00000
+#define SPI0_HS_MUX                   0x0000F
+#define SDHC_HS_MUX                   0x10000
+#define SPIC2_HS_MUX                  0x15550
+#define ETHERNET_HS_MUX               0x1AAA0
+
+/** End of PAD_HS_Mux
+  * \}
+  */
+
+/*============================================================================*
+ *                          PINMUX TYPE/API WRAPPERS
+ *============================================================================*/
+/**
+ * \defgroup PAD_Constant_Wrapper PAD_Constant_Wrapper
+ * \{
+ * \ingroup  PINMUX_Exported_Constants
+ */
+#define PAD_DRIVING_CURRENT_4mA         LEVEL0  //!< The macro is a wrapper for LEVEL0
+#define PAD_DRIVING_CURRENT_8mA         LEVEL1  //!< The macro is a wrapper for LEVEL1
+#define PAD_DRIVING_CURRENT_12mA        LEVEL2  //!< The macro is a wrapper for LEVEL2
+#define PAD_DRIVING_CURRENT_16mA        LEVEL3  //!< The macro is a wrapper for LEVEL3
+
+/** End of PAD_Constant_Wrapper
+  * \}
+  */
+
+/**
+ * \defgroup PAD_API_Wrapper PAD API Wrapper
+ * \{
+ * \ingroup  PINMUX_Exported_Constants
+ */
+#define Pad_ControlSelectValue          Pad_SetControlMode            //!< The macro is a wrapper for Pad_SetControlMode
+#define Pad_OutputEnableValue           Pad_Output_Cmd                //!< The macro is a wrapper for Pad_Output_Cmd         
+#define Pad_OutputControlValue          Pad_SetOutputValue            //!< The macro is a wrapper for Pad_SetOutputValue     
+#define Pad_PullEnableValue             Pad_Pull_Cmd                  //!< The macro is a wrapper for Pad_Pull_Cmd           
+#define Pad_PullUpOrDownValue           Pad_SetPullMode               //!< The macro is a wrapper for Pad_SetPullMode        
+#define Pad_PullConfigValue             Pad_SetPullStrengthMode       //!< The macro is a wrapper for Pad_SetPullStrengthMode
+#define Pad_PowerOrShutDownValue        Pad_Power_Cmd                 //!< The macro is a wrapper for Pad_Power_Cmd          
+#define Pad_DrivingCurrentControl       Pad_SetDrivingCurrent         //!< The macro is a wrapper for Pad_SetDrivingCurrent  
+#define Pad_WakeupEnableValue           Pad_Wakeup_Cmd                //!< The macro is a wrapper for Pad_Wakeup_Cmd         
+#define Pad_WakeupPolarityValue         Pad_SetWakeupPolarity         //!< The macro is a wrapper for Pad_SetWakeupPolarity  
+#define Pad_WKDebounceConfig            Pad_WakeupDebounce_Cmd        //!< The macro is a wrapper for Pad_WakeupDebounce_Cmd 
+#define Pad_WakeupInterruptValue        Pad_GetWakeupINTStatus        //!< The macro is a wrapper for Pad_GetWakeupINTStatus 
+
+#define System_DebounceWakeupStatus     System_WakeupDebounceStatus   //!< The macro is a wrapper for System_WakeupDebounceStatus
+#define System_Pad_WakeUp_Cmd           System_WakeUpDebounceCmd      //!< The macro is a wrapper for System_WakeUpDebounceCmd
+
+#define Pad_Output_Cmd                  Pad_OutputCmd                 //!< The macro is a wrapper for Pad_OutputCmd        
+#define Pad_SetOutputValue              Pad_SetOutputLevel            //!< The macro is a wrapper for Pad_SetOutputLevel   
+#define Pad_Pull_Cmd                    Pad_PullCmd                   //!< The macro is a wrapper for Pad_PullCmd          
+#define Pad_SetPullStrengthMode         Pad_SetPullStrength           //!< The macro is a wrapper for Pad_SetPullStrength  
+#define Pad_Power_Cmd                   Pad_PowerCmd                  //!< The macro is a wrapper for Pad_PowerCmd         
+#define Pad_Wakeup_Cmd                  Pad_WakeupConfig              //!< The macro is a wrapper for Pad_WakeupConfig     
+#define Pad_WakeupDebounce_Cmd          Pad_WakeupDebounceCmd         //!< The macro is a wrapper for Pad_WakeupDebounceCmd
+
+/** End of PAD_API_Wrapper
+  * \}
+  */
+
+/** End of PINMUX_Exported_Constants
+  * \}
+  */
+
+/** End of PINMUX
+  * \}
+  */
+
+#ifdef  __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* RTL_PINMUX_DEF_H */
diff --git a/bee/drivers/pinmux/src/device/rtl87x2j/rtl_pinmux.c b/bee/drivers/pinmux/src/device/rtl87x2j/rtl_pinmux.c
new file mode 100644
index 00000000..fd2a307c
--- /dev/null
+++ b/bee/drivers/pinmux/src/device/rtl87x2j/rtl_pinmux.c
@@ -0,0 +1,686 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *                           Header Files
+ *============================================================================*/
+#include "rtl_pinmux.h"
+
+/*============================================================================*
+ *                           Private Defines
+ *============================================================================*/
+#define MAX_PINMUX_NUM      ((PCC_REG_PMUX_GPIO_SPIC_2 - PCC_r_PMUX_GPIO_P0_0to3 + 4) >> 2) /* pinmux Register number: 13 */
+
+#if (PAD_SUPPORT_GET_PIN_NAME == 1)
+static const char *const pad_name_table[] =
+{
+    "P0_0",     "P0_1",      "P0_2",      "P0_3",      "P0_4",    "P0_5",      "P0_6",      "P0_7",
+    "P1_0",     "P1_1",      "P1_6",      "P1_7",
+    "P2_0",     "P2_1",      "P2_2",      "P2_3",      "P2_4",    "P2_5",      "P2_6",      "P2_7",
+    "P3_0",     "P3_1",      "P3_2",      "P3_3",      "P3_4",    "P3_5",      "P3_6",
+    "P4_0",     "P4_1",      "P4_2",      "P4_3",
+    "MICBIAS",  "P5_1",      "P5_2",
+    "P6_0",     "P6_1",      "P6_2",      "P6_3",      "P6_4",    "P6_5",      "P6_6",      "P6_7",
+    "P7_0",     "P7_1",      "SPIC_CSN",  "SPIC_SCK",  "SPIC_SI", "SPIC_SO",   "SPIC_WEN",  "SPIC_HOLDEN",
+};
+#endif
+
+const PADAddrTable_TypeDef pad_addr_table =
+{
+    .reg[P0_0] =     0x120,
+    .reg[P0_1] =     0x122,
+    .reg[P0_2] =     0x124,
+    .reg[P0_3] =     0x126,
+    .reg[P0_4] =     0x128,
+    .reg[P0_5] =     0x12a,
+    .reg[P0_6] =     0x12C,
+    .reg[P0_7] =     0x12e,
+    .reg[P1_0] =     0x130,
+    .reg[P1_1] =     0x132,
+    .reg[P1_6] =     0x134,
+    .reg[P1_7] =     0x136,
+    .reg[P2_0] =     0x138,
+    .reg[P2_1] =     0x13a,
+    .reg[P2_2] =     0x13C,
+    .reg[P2_3] =     0x13e,
+    .reg[P2_4] =     0x140,
+    .reg[P2_5] =     0x142,
+    .reg[P2_6] =     0x144,
+    .reg[P2_7] =     0x146,
+    .reg[P3_0] =     0x148,
+    .reg[P3_1] =     0x14a,
+    .reg[P3_2] =     0x14C,
+    .reg[P3_3] =     0x14e,
+    .reg[P3_4] =     0x150,
+    .reg[P3_5] =     0x152,
+    .reg[P3_6] =     0x154,
+    .reg[P4_0] =     0x158,
+    .reg[P4_1] =     0x15a,
+    .reg[P4_2] =     0x15C,
+    .reg[P4_3] =     0x15e,
+    .reg[MICBIAS] =  0x178,
+    .reg[P5_1] =     0x160,
+    .reg[P5_2] =     0x162,
+    .reg[P6_0] =     0x164,
+    .reg[P6_1] =     0x166,
+    .reg[P6_2] =     0x168,
+    .reg[P6_3] =     0x16a,
+    .reg[P6_4] =     0x16C,
+    .reg[P6_5] =     0x16e,
+    .reg[P6_6] =     0x170,
+    .reg[P6_7] =     0x172,
+    .reg[P7_0] =     0x174,
+    .reg[P7_1] =     0x176,
+    .reg[SPIC_CSN] = 0x18E,
+    .reg[SPIC_SCK] = 0x18C,
+    .reg[SPIC_SI] =  0x192,
+    .reg[SPIC_SO] =  0x190,
+    .reg[SPIC_WEN] = 0x196,    /*!< P1_4 */
+    .reg[SPIC_HOLDEN] = 0x194, /*!< P1_3 */
+};
+
+const PINMUXIndexTable_TypeDef pinmux_index_table =
+{
+    .reg[P0_0] =    0,
+    .reg[P0_1] =    1,
+    .reg[P0_2] =    2,
+    .reg[P0_3] =    3,
+    .reg[P0_4] =    4,
+    .reg[P0_5] =    5,
+    .reg[P0_6] =    6,
+    .reg[P0_7] =    7,
+    .reg[P1_0] =    8,
+    .reg[P1_1] =    9,
+    .reg[P1_6] =    10,
+    .reg[P1_7] =    11,
+    .reg[P2_0] =    12,
+    .reg[P2_1] =    13,
+    .reg[P2_2] =    14,
+    .reg[P2_3] =    15,
+    .reg[P2_4] =    16,
+    .reg[P2_5] =    17,
+    .reg[P2_6] =    18,
+    .reg[P2_7] =    19,
+    .reg[P3_0] =    20,
+    .reg[P3_1] =    21,
+    .reg[P3_2] =    22,
+    .reg[P3_3] =    23,
+    .reg[P3_4] =    24,
+    .reg[P3_5] =    25,
+    .reg[P3_6] =    26,
+    .reg[P4_0] =    28,
+    .reg[P4_1] =    29,
+    .reg[P4_2] =    30,
+    .reg[P4_3] =    31,
+    .reg[MICBIAS] = 32,
+    .reg[P5_1] =    33,
+    .reg[P5_2] =    34,
+    .reg[P6_0] =    36,
+    .reg[P6_1] =    37,
+    .reg[P6_2] =    38,
+    .reg[P6_3] =    39,
+    .reg[P6_4] =    40,
+    .reg[P6_5] =    41,
+    .reg[P6_6] =    42,
+    .reg[P6_7] =    43,
+    .reg[P7_0] =    44,
+    .reg[P7_1] =    45,
+    .reg[SPIC_CSN] = 46,
+    .reg[SPIC_SCK] = 47,
+    .reg[SPIC_SI]  = 48,
+    .reg[SPIC_SO]  = 49,
+    .reg[SPIC_WEN] = 50,
+    .reg[SPIC_HOLDEN] = 51,
+};
+
+
+/*============================================================================*
+ *                        Private Functions
+ *============================================================================*/
+
+/*============================================================================*
+ *                        Public Functions
+ *============================================================================*/
+/**
+  * \brief  Reset all pin to default value.
+  * \param  None.
+  * \note   two SWD pins will also be reset. Please use this function carefully.
+  * \return None
+  */
+void Pinmux_Reset(void)
+{
+    for (uint8_t i = 0; i < MAX_PINMUX_NUM; i++)
+    {
+        PINMUX->CFG[i] = 0x00;
+    }
+
+    return;
+}
+
+/**
+  * \brief  Configure the specified pin to idle mode.
+  * \param  Pin_Num: Pin number to be configured. \ref Pin_Number.
+  * \return None
+  */
+void Pinmux_Deinit(uint8_t Pin_Num)
+{
+    if (!IS_PIN_NUMBER(Pin_Num))
+    {
+        return;
+    }
+
+    uint8_t pinmux_index = pinmux_index_table.reg[Pin_Num];
+    uint8_t pinmux_reg_num = pinmux_index >> 2;
+    PINMUX->CFG[pinmux_reg_num] &= ~(0xff << ((pinmux_index % 4) << 3));
+
+    return;
+}
+
+/**
+  * \brief  Configure the specified pin to its corresponding pin function.
+  * \param  Pin_Num: Pin number to be configured. \ref Pin_Number.
+  * \param  Pin_Func: Pin function. \ref PIN_Function.
+  * \return None
+  */
+void Pinmux_Config(uint8_t Pin_Num, uint32_t Pin_Func)
+{
+    if (!IS_PIN_NUMBER(Pin_Num))
+    {
+        return;
+    }
+
+    uint8_t pinmux_index = pinmux_index_table.reg[Pin_Num];
+    uint8_t pinmux_reg_num = pinmux_index >> 2;
+    uint8_t reg_offset = (pinmux_index & 0x03) << 3;
+
+    PINMUX->CFG[pinmux_reg_num] = (PINMUX->CFG[pinmux_reg_num] & ~(0xFF << reg_offset))
+                                  | Pin_Func << reg_offset;
+
+    return;
+}
+
+/**
+  * \brief  config the corresponding pad.
+  * \param  Pin_Num: Pin number to be configured. \ref Pin_Number.
+  * \param  AON_PAD_MODE: use software mode or pinmux mode.
+  *         This parameter can be one of the following values:
+  *         \arg PAD_SW_MODE: use software mode.
+  *         \arg PAD_PINMUX_MODE: use pinmux mode.
+  * \param  AON_PAD_PwrOn: config power of pad.
+  *         This parameter can be one of the following values:
+  *         \arg PAD_NOT_PWRON: shutdown power of pad.
+  *         \arg PAD_IS_PWRON: enable power of pad.
+  * \param  AON_PAD_Pull: config pad pull mode.
+  *         This parameter can be one of the following values:
+  *         \arg PAD_PULL_NONE: no pull.
+  *         \arg PAD_PULL_UP: pull this pin up.
+  *         \arg PAD_PULL_DOWN: pull thi pin down.
+  * \param  AON_PAD_E: config pad out put function.
+  *         This parameter can be one of the following values:
+  *         \arg PAD_OUT_DISABLE: disable pin output.
+  *         \arg PAD_OUT_ENABLE: enable pad output.
+  * \param  AON_PAD_O: config pin output level.
+  *         This parameter can be one of the following values:
+  *         \arg PAD_OUT_LOW: pad output low.
+  *         \arg PAD_OUT_HIGH: pad output high.
+  * \return None
+  */
+void Pad_Config(uint8_t                Pin_Num,
+                PADMode_TypeDef        AON_PAD_Mode,
+                PADPowerMode_TypeDef   AON_PAD_PwrOn,
+                PADPullMode_TypeDef    AON_PAD_Pull,
+                PADOutputMode_TypeDef  AON_PAD_E,
+                PADOutputValue_TypeDef AON_PAD_O)
+{
+    if (!IS_PIN_NUMBER(Pin_Num))
+    {
+        return;
+    }
+
+    uint32_t temp_value = 0;
+    uint32_t reg_addr_offset = PAD_REG_BASE + pad_addr_table.reg[Pin_Num];
+    uint32_t reg_high_offset = (reg_addr_offset & BIT1) ? 16 : 0;
+    reg_addr_offset &= ~BIT1;
+
+    /* AON MUX */
+    if (AON_PAD_Mode)
+    {
+        temp_value |= AON_PAD_Mode << BITOFFSET(AON_MUX);
+    }
+
+    /* Pull config */
+    if (AON_PAD_Pull == PAD_PULL_UP)
+    {
+        temp_value |= PULL_EN;
+        temp_value &= ~PULL_DIR;
+    }
+    else if (AON_PAD_Pull == PAD_PULL_DOWN)
+    {
+        temp_value |= PULL_EN;
+        temp_value |= PULL_DIR;
+    }
+    else if (AON_PAD_Pull == PAD_PULL_NONE)
+    {
+        temp_value &= ~PULL_EN;
+    }
+
+    /* Output Config */
+    if (AON_PAD_E == PAD_OUT_ENABLE)
+    {
+        temp_value |= (OUTPUT_EN) | (AON_PAD_O << BITOFFSET(OUTPUT_VAL));
+    }
+
+    /* Get reg value from register */
+    uint32_t reg_value = PAD_REG_READ(reg_addr_offset);
+
+    /* Clear reg value first. */
+    reg_value &= ~(PAD_CONFIG_MASK << reg_high_offset);
+
+    /* Set reg value to register and need power on first*/
+    reg_value |= (temp_value | POWER_SHDN) << reg_high_offset;
+    PAD_REG_WRITE(reg_addr_offset, reg_value);
+
+    /* Pad control mode */
+    if (AON_PAD_PwrOn == PAD_NOT_PWRON)
+    {
+        reg_value &= ~(POWER_SHDN << reg_high_offset);
+        PAD_REG_WRITE(reg_addr_offset, reg_value);
+    }
+
+    Pad_ModeAutoSwitchCmd(Pin_Num, AON_PAD_Mode == PAD_PINMUX_MODE);
+}
+
+/**
+  * \brief  config the corresponding pad.
+  * \param  Pin_Num: Pin number to be configured. \ref Pin_Number.
+  * \param  NewState: This parameter enable or disable the the pad for auto switch.
+  *         This parameter can be the following:
+  *         \arg DISABLE: Disable the pad for auto switch function.
+  *         \arg ENABLE: Enable the pad for auto switch function.
+  * \return None
+  */
+void Pad_ModeAutoSwitchCmd(uint8_t Pin_Num, FunctionalState NewState)
+{
+    volatile uint32_t *aonmux_as_register = (volatile uint32_t *)(PAD_AONMUX_AS_BASE + 4 *
+                                                                  (Pin_Num > MICBIAS));
+
+    if (NewState == ENABLE)
+    {
+        /* Enable Auto Switch which is switched to aon when enter dlps and to pinmux when exit dlps */
+        *aonmux_as_register |= BIT(Pin_Num & 0x1F);
+    }
+    else
+    {
+        /* Disable Auto Switch which is hold on pinmux mode when enter dlps */
+        *aonmux_as_register &= ~BIT(Pin_Num & 0x1F);
+    }
+}
+
+/**
+  * \brief  Config the corresponding pad for low power mode.
+  * \param  Pin_Num: Pin number to be configured. \ref Pin_Number.
+  * \param  AON_PAD_PwrOn: config power of pad.
+  *         This parameter can be one of the following values:
+  *         \arg PAD_NOT_PWRON: shutdown power of pad.
+  *         \arg PAD_IS_PWRON: enable power of pad.
+  * \param  AON_PAD_Pull: config pad pull mode.
+  *         This parameter can be one of the following values:
+  *         \arg PAD_PULL_NONE: no pull.
+  *         \arg PAD_PULL_UP: pull this pin up.
+  *         \arg PAD_PULL_DOWN: pull thi pin down.
+ * \param  AON_PAD_Strength: This parameter sets the strength of pull-up/pull-down resistance.
+ *         This parameter can be the following:
+ *         \arg PAD_WEAK_PULL: Resistance weak pull.
+ *         \arg PAD_STRONG_PULL: Resistance strong pull.
+ * \param  NewState: This parameter enable or disable the the pad for low power.
+ *         This parameter can be the following:
+ *         \arg DISABLE: Disable the pad for low power function.
+ *         \arg ENABLE: Enable the pad for low power function.
+ * \return None
+ */
+void Pad_LPConfig(uint8_t Pin_Num, PADPullMode_TypeDef AON_PAD_Pull, FunctionalState NewState)
+{
+    uint8_t supported_pin_table[] = {P0_2, P0_4, P0_0, P0_1, \
+                                     P1_0, P1_1, P0_5, P0_6, \
+                                     P2_2, P2_3, P2_0, P2_1, \
+                                     P2_6, P2_7, P2_4, P2_5, \
+                                     P3_2, P3_3, P3_0, P3_1, \
+                                     P4_2, P4_3, P4_0, P4_1, \
+                                     SPIC_SO, SPIC_SI, SPIC_SCK, SPIC_CSN, \
+                                     0xFF, 0xFF, SPIC_HOLDEN, SPIC_WEN
+                                    };
+    /* If PIN_Num is not in supported_pin_table, return early */
+    if (memchr(supported_pin_table, Pin_Num, sizeof(supported_pin_table)) == NULL)
+    {
+        return;
+    }
+
+    uint32_t reg_addr_offset = PAD_REG_BASE + pad_addr_table.reg[Pin_Num];
+    uint32_t reg_high_offset = (reg_addr_offset & BIT1) ? 16 : 0;
+    reg_addr_offset &= ~BIT1;
+    uint32_t reg_value = PAD_REG_READ(reg_addr_offset);
+
+    for (uint8_t i = 0; i < sizeof(supported_pin_table); i++)
+    {
+        if (supported_pin_table[i] == Pin_Num)
+        {
+            PADMUXAS_TypeDef pull_as_aon_address = {.d32 = (*((volatile uint32_t *) PAD_PULL_AON_AS_BASE + i / 4))};
+            PADMUXAS_TypeDef pull_as_core_address = {.d32 = (*((volatile uint32_t *) PAD_PULL_CORE_AS_BASE + i / 4))};
+            if (NewState)
+            {
+                pull_as_aon_address.b[i % 4].as_en = ENABLE;
+                if (AON_PAD_Pull == PAD_PULL_UP)
+                {
+                    pull_as_aon_address.b[i % 4].pu_en = 1;
+                    pull_as_aon_address.b[i % 4].pd = 0;
+                }
+                else if (AON_PAD_Pull == PAD_PULL_DOWN)
+                {
+                    pull_as_aon_address.b[i % 4].pu_en = 1;
+                    pull_as_aon_address.b[i % 4].pd = 1;
+                }
+                else if (AON_PAD_Pull == PAD_PULL_NONE)
+                {
+                    pull_as_aon_address.b[i % 4].pu_en = 0;
+                    pull_as_aon_address.b[i % 4].pd = 0;
+                }
+
+                pull_as_core_address.b[i % 4].pu_en = (((reg_value >> reg_high_offset) & PULL_EN) == PULL_EN);
+                pull_as_core_address.b[i % 4].pd = (((reg_value >> reg_high_offset) & PULL_DIR) == PULL_DIR);
+            }
+            else
+            {
+                pull_as_aon_address.d32 &= ~(0xFF << ((i % 4) << 3));
+                pull_as_core_address.d32 &= ~(0xFF << ((i % 4) << 3));
+            }
+            (*((volatile uint32_t *) PAD_PULL_AON_AS_BASE + i / 4)) = pull_as_aon_address.d32;
+            (*((volatile uint32_t *) PAD_PULL_CORE_AS_BASE + i / 4)) = pull_as_core_address.d32;
+        }
+    }
+
+    /* Check all Pin Auto Switch En is Disabled */
+    bool all_auto_switch_disabled = true;
+    for (uint8_t i = 0; i < sizeof(supported_pin_table); i++)
+    {
+        PADMUXAS_TypeDef pull_as_aon_address = {.d32 = (*((volatile uint32_t *) PAD_PULL_AON_AS_BASE + i / 4))};
+        if (pull_as_aon_address.b[i % 4].as_en == ENABLE)
+        {
+            all_auto_switch_disabled = false;
+            break;
+        }
+    }
+    if (all_auto_switch_disabled == true)
+    {
+        (*((volatile uint32_t *) PAD_PULL_AON_AS_BASE + 7)) &= ~BIT0;
+    }
+    else
+    {
+        (*((volatile uint32_t *) PAD_PULL_AON_AS_BASE + 7)) |= BIT0;
+    }
+}
+
+/**
+  * \brief  Configure the pin to corresponding function.
+  * \param  Pin_Num: Pin number to be configured. \ref Pin_Number.
+  * \param  Pad_Func: Pad function. \ref Pad_Function_Config.
+  * \return None
+  */
+bool Pad_FunctionConfig(uint8_t Pin_Num, PADFuncConfig_TypeDef Pad_Func)
+{
+    if (!IS_PIN_NUMBER(Pin_Num))
+    {
+        /* Disable the PAD function when the pin number is invalid by setting the XXX_SEL_EN to 0. */
+        PAD_FUNCTION &= ~(0xFF << (Pad_Func << 3));
+        return false;
+    }
+
+    for (uint8_t i = 0; i < 4; i++)
+    {
+        /* If the pin is already set to a different function, setting the XXX_SEL_EN to 0. */
+        if ((PAD_FUNCTION & (BIT7 << (i << 3))) && (Pad_Func != i) &&
+            (Pin_Num == ((PAD_FUNCTION >> (i << 3)) & 0x3F)))
+        {
+            PAD_FUNCTION &= ~(0xFF << (i << 3));
+        }
+    }
+
+    /* Set the PAD function for the specified pin number. */
+    PAD_FUNCTION &= ~(0xFF << (Pad_Func << 3));
+    PAD_FUNCTION |= (Pin_Num << (Pad_Func << 3));
+    PAD_FUNCTION |= (BIT7 << (Pad_Func << 3));
+
+    return true;
+}
+
+/**
+  * \brief  Configure the pin to high speed function.
+  * \param  Pin_Num: Pin number to be configured. \ref Pin_Number.
+  * \param  Pad_Func: Pad function. \ref Pad_Function_Config.
+  * \return None
+  */
+bool Pad_HighSpeedConfig(uint8_t *Pin_Group, uint8_t Pin_GroupLen,
+                         PADHSConfig_Typedef Pad_HighSpeed, FunctionalState NewState)
+{
+    if (Pad_HighSpeed == PAD_HIGH_SPEED_SPI0)
+    {
+        AON_REG_WRITE_BITFIELD(AON_REG_SPI_PAD_REG30X, SPI0M_AON_PATH_EN, NewState);
+        AON_REG_WRITE_BITFIELD(AON_REG_PAD_REG24X, PAD_P4_0_O_EN, !NewState);
+    }
+    else if (Pad_HighSpeed == PAD_HIGH_SPEED_SPI1)
+    {
+        AON_REG_WRITE_BITFIELD(AON_REG_SPI_PAD_REG30X, SPI1M_AON_PATH_EN, NewState);
+        AON_REG_WRITE_BITFIELD(AON_REG_PAD_REG23X, PAD_P0_4_O_EN, !NewState);
+    }
+    else if (Pad_HighSpeed == PAD_HIGH_SPEED_SPI2)
+    {
+        AON_REG_WRITE_BITFIELD(AON_REG_SPI_PAD_REG30X, SPI2M_AON_PATH_EN, NewState);
+        AON_REG_WRITE_BITFIELD(AON_REG_PAD_REG23X, PAD_P0_1_O_EN, !NewState);
+    }
+
+    return true;
+}
+
+/**
+ * \brief   Get the pin name in string.
+ * \param   Pin_Num: Pin number to be configured. \ref Pin_Number.
+ * \return  pin name.
+ */
+const char *Pad_GetPinName(uint8_t Pin_Num)
+{
+    return pad_name_table[Pin_Num];
+}
+
+/**
+ * \brief  Get pin power group.
+ * \param  Pin_Num: Pin number to be configured. \ref Pin_Number
+ * \return power group.
+ */
+static PADPowerGroup_TypeDef Pad_GetPowerGroup(uint8_t Pin_Num)
+{
+    if ((Pin_Num >= P0_0 && Pin_Num <= P0_1) ||
+        (Pin_Num >= P0_7 && Pin_Num <= P1_7) ||
+        (Pin_Num >= P3_0 && Pin_Num <= P3_3) ||
+        (Pin_Num >= P7_0 && Pin_Num <= P7_1))
+    {
+        return PAD_POWER_GROUP_RIGHT;
+    }
+    else if ((Pin_Num == P0_2) || (Pin_Num >= P0_4 && Pin_Num <= P0_6) ||
+             (Pin_Num >= P2_0 && Pin_Num <= P2_7) ||
+             (Pin_Num >= P3_4 && Pin_Num <= P3_6) ||
+             (Pin_Num >= MICBIAS && Pin_Num <= P5_2) ||
+             (Pin_Num >= SPIC_CSN && Pin_Num <= SPIC_WEN))
+    {
+        return PAD_POWER_GROUP_LEFT;
+    }
+    else if ((Pin_Num == P0_3) ||
+             (Pin_Num >= P4_0 && Pin_Num <= P4_3) ||
+             (Pin_Num >= P6_0 && Pin_Num <= P6_7))
+    {
+        return PAD_POWER_GROUP_BOTTOM;
+    }
+
+    return PAD_POWER_GROUP_INVALID;
+}
+
+/**
+ * \brief  Set pin drivering current.
+ * \param  Pin_Num: Pin number to be configured. \ref Pin_Number
+ * \param  value: This parameter sets the pin drivering current.
+ *         This parameter can be the following:
+ *         \arg PAD_DRIVING_CURRENT_4mA.
+ *         \arg PAD_DRIVING_CURRENT_8mA.
+ * \return None.
+ */
+void Pad_SetDrivingCurrent(uint8_t Pin_Num, PADDrivingCurrent_TypeDef PAD_DrivingCurrent)
+{
+    if (Pin_Num == P0_5) /* P0_5 only support 8/18/28mA */
+    {
+        Pad_TableConfig(CUR_DRIVING, Pin_Num, (PAD_DrivingCurrent >> 1) & BIT0);
+        AON_REG_WRITE_BITFIELD(AON_REG_PAD_REG26X, LEFT_PAD_E2, (PAD_DrivingCurrent == 3));
+        return;
+    }
+    else if (Pin_Num == P6_0) /* P6_0 only support 8/18/28mA */
+    {
+        Pad_TableConfig(CUR_DRIVING, Pin_Num, (PAD_DrivingCurrent >> 1) & BIT0);
+        AON_REG_WRITE_BITFIELD(AON_REG_PAD_REG26X, BOTTOM_PAD_E2, (PAD_DrivingCurrent == 3));
+        return;
+    }
+
+    /* Others only support 4/8mA only */
+    PADPowerGroup_TypeDef power_group = Pad_GetPowerGroup(Pin_Num);
+    if (power_group == PAD_POWER_GROUP_LEFT)
+    {
+        if ((Pin_Num >= SPIC_CSN && Pin_Num <= SPIC_WEN))
+        {
+            AON_REG_WRITE_BITFIELD(AON_REG_SPI_PAD_REG30X, SPIC_PAD_E2, (PAD_DrivingCurrent > 0));
+        }
+        else
+        {
+            AON_REG_WRITE_BITFIELD(AON_REG_PAD_REG26X, LEFT_PAD_E2, (PAD_DrivingCurrent > 0));
+        }
+    }
+    else if (power_group == PAD_POWER_GROUP_RIGHT)
+    {
+        AON_REG_WRITE_BITFIELD(AON_REG_PAD_REG26X, RIGHT_PAD_E2, (PAD_DrivingCurrent > 0));
+    }
+    else if (power_group == PAD_POWER_GROUP_BOTTOM)
+    {
+        AON_REG_WRITE_BITFIELD(AON_REG_PAD_REG26X, BOTTOM_PAD_E2, (PAD_DrivingCurrent > 0));
+    }
+}
+
+/**
+ * \brief  Set pin control mode.
+ * \param  Pin_Num: Pin number to be configured. \ref Pin_Number
+ * \param  value: This parameter sets the pin mode.
+ *         This parameter can be the following:
+ *         \arg PAD_SW_MODE: Software mode.
+ *         \arg PAD_PINMUX_MODE: Default pinmux mode.
+ * \return None.
+ */
+void Pad_SetControlMode(uint8_t Pin_Num, PADMode_TypeDef PAD_Mode)
+{
+    Pad_TableConfig(AON_MUX, Pin_Num, PAD_Mode);
+}
+
+/**
+ * \brief  Enable or disable pad output mode.
+ * \param  Pin_Num: Pin number to be configured. \ref Pin_Number
+ * \param  value: This parameter sets whether the pin outputs the level in software mode.
+ *         This parameter can be enumerated PAD_OUTPUT_ENABLE_Mod of the values:
+ *         \arg PAD_OUT_DISABLE: Disable output.
+ *         \arg PAD_OUT_ENABLE: Enable output.
+ * \return None.
+ */
+void Pad_OutputCmd(uint8_t Pin_Num, PADOutputMode_TypeDef PAD_OutEn)
+{
+    Pad_TableConfig(OUTPUT_EN, Pin_Num, PAD_OutEn);
+}
+
+/**
+ * \brief  Configure pad output level.
+ * \param  Pin_Num: Pin number to be configured. \ref Pin_Number
+ * \param  value: Config pin output level.
+ *         This parameter can be one of the following values:
+ *         \arg PAD_OUT_LOW: Pad output low.
+ *         \arg PAD_OUT_HIGH: Pad output high.
+ * \return None.
+ */
+void Pad_SetOutputLevel(uint8_t Pin_Num, PADOutputValue_TypeDef PAD_OutValue)
+{
+    Pad_TableConfig(OUTPUT_VAL, Pin_Num, PAD_OutValue);
+}
+
+/**
+ * \brief  Enable or disable pad pull-up / pull-down resistance function.
+ * \param  Pin_Num: Pin number to be configured. \ref Pin_Number
+ * \param  value: This parameter enable or disable the the pad pin pull-up/pull-down function.
+ *         This parameter can be the following:
+ *         \arg DISABLE: Disable pad pull-up / pull-down function.
+ *         \arg ENABLE: Enable  pad pull-up / pull-down function.
+ * \return None.
+ */
+void Pad_PullCmd(uint8_t Pin_Num, FunctionalState NewState)
+{
+    Pad_TableConfig(PULL_EN, Pin_Num, NewState);
+}
+
+/**
+ * \brief  Pad pull-up/pull-down resistance function selection.
+ * \param  Pin_Num: Pin number to be configured. \ref Pin_Number
+ * \param  value: This parameter sets whether the pin pull-up or pull-down.
+ *         This parameter can be the following:
+ *         \arg 0: Config pad pull-up function.
+ *         \arg 1: Config  pad pull-down function.
+ * \return None.
+ */
+void Pad_SetPullMode(uint8_t Pin_Num, PADPullMode_TypeDef PAD_PullMode)
+{
+    if (PAD_PullMode == PAD_PULL_NONE)
+    {
+        Pad_TableConfig(PULL_EN, Pin_Num, DISABLE);
+    }
+    else if (PAD_PullMode == PAD_PULL_UP)
+    {
+        Pad_TableConfig(PULL_EN, Pin_Num, ENABLE);
+        Pad_TableConfig(PULL_DIR, Pin_Num, DISABLE);
+    }
+    else if (PAD_PullMode == PAD_PULL_DOWN)
+    {
+        Pad_TableConfig(PULL_EN, Pin_Num, ENABLE);
+        Pad_TableConfig(PULL_DIR, Pin_Num, ENABLE);
+    }
+}
+
+/**
+ * \brief  Configure the strength of pull-up/pull-down resistance.
+ * \param  Pin_Num: Pin number to be configured. \ref Pin_Number
+ * \param  value: This parameter sets the strength of pull-up/pull-down resistance.
+ *         This parameter can be the following:
+ *         \arg PAD_WEAK_PULL: Resistance weak pull.
+ *         \arg PAD_STRONG_PULL: Resistance strong pull.
+ * \return None.
+ */
+void Pad_SetPullStrength(uint8_t Pin_Num, PADPullStrengthMode_TypeDef PAD_PullStrengthMode)
+{
+    Pad_TableConfig(PULL_RES, Pin_Num, PAD_PullStrengthMode);
+}
+
+/**
+ * \brief  Set pin power mode.
+ * \param  Pin_Num: Pin number to be configured. \ref Pin_Number
+ * \param  value: This parameter sets the power supply mode of the pin,
+ *                and the value is enumeration PAD_PWR_Mode One of the values.
+ *         \arg PAD_NOT_PWRON: Power off.
+ *         \arg PAD_IS_PWRON: Power on.
+ * \return None.
+ */
+void Pad_PowerCmd(uint8_t Pin_Num, PADPowerMode_TypeDef PAD_PowerMode)
+{
+    Pad_TableConfig(POWER_SHDN, Pin_Num, PAD_PowerMode);
+}
+
+
diff --git a/bee/drivers/pinmux/src/device/rtl87x2j/rtl_pinmux_def.h b/bee/drivers/pinmux/src/device/rtl87x2j/rtl_pinmux_def.h
new file mode 100644
index 00000000..55bcedbb
--- /dev/null
+++ b/bee/drivers/pinmux/src/device/rtl87x2j/rtl_pinmux_def.h
@@ -0,0 +1,505 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef RTL_PINMUX_DEF_H
+#define RTL_PINMUX_DEF_H
+
+#include <string.h>
+#include "utils/rtl_utils.h"
+#include "address_map.h"
+#include "aon_reg.h"
+#include "pcc_reg.h"
+#include "pinmux/inc/rtl87x2j/pin_def.h"
+
+#ifdef  __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/*============================================================================*
+ *                          PINMUX Defines
+ *============================================================================*/
+/** \defgroup PINMUX      PINMUX
+  * \brief
+  * \{
+  */
+
+/** \defgroup PINMUX_Exported_Constants PINMUX Exported Constants
+  * \brief
+  * \{
+  */
+
+/**
+ * \defgroup PINMUX_Defines PINMUX Defines
+ * \{
+ * \ingroup  PINMUX_Exported_Constants
+ */
+#define PAD_SUPPORT_CONFIG_PON_DOMAIN                  (1)
+#define PAD_SUPPORT_FUNCTION_CONFIG                    (1)
+#define PAD_SUPPORT_HIGH_SPEED_CONFIG                  (1)
+#define PAD_SUPPORT_CONFIG_EXT                         (0)
+#define PAD_SUPPORT_ANALOG_MODE                        (0)
+#define PAD_SUPPORT_GET_PIN_NAME                       (1)
+#define PAD_SUPPORT_GET_POWER_GROUP                    (0)
+#define PAD_SUPPORT_GET_OUTPUT_CTRL                    (0)
+
+#define PAD_SUPPORT_WAKEUP_ENABLE_WITH_DEBOUNCE        (1)
+#define PAD_SUPPORT_WAKEUP_DEBOUNCE                    (1)
+#define PAD_SUPPORT_WAKEUP_DEBOUNCE_MULTI_GROUP        (1)
+#define PAD_SUPPORT_WAKEUP_SHORT_PULSE                 (0)
+#define PAD_SUPPORT_ADPATER_WAKEUP                     (0)
+#define PAD_SUPPORT_MFB_WAKEUP                         (0)
+#define PAD_SUPPORT_USB_WAKEUP                         (0)
+#define PAD_SUPPORT_LOWER_POWER_CONFIG                 (1)
+#define PAD_SUPPORT_WAKE_SUB_IRQ                       (1)
+#define PAD_SUPPORT_WKIE_DIFF_BIT                      (1)
+
+/** End of PINMUX_Defines
+  * \}
+  */
+
+/** End of PINMUX_Exported_Constants
+  * \}
+  */
+
+/** End of PINMUX
+  * \}
+  */
+
+/*============================================================================*
+ *                         PINMUX Registers Memory Map
+ *============================================================================*/
+/**
+ * \brief Pinmux Register
+ */
+
+typedef struct                      /*!< Pinmux Structure */
+{
+    __IO uint32_t CFG[(PCC_REG_PMUX_GPIO_SPIC_2 - PCC_r_PMUX_GPIO_P0_0to3 + 4) >> 2];
+} PINMUX_TypeDef;
+
+/**
+ * \brief Pad Debounce Register
+ */
+
+typedef struct
+{
+    __IO uint32_t MUX_SEL;         /*!< 0x00 */
+    __IO uint32_t CNT[3];          /*!< 0x04 ~ 0x0C */
+    __IO uint32_t STS;             /*!< 0x10 */
+} PADDEB_TypeDef;
+
+/*============================================================================*
+ *                         PINMUX Declaration
+ *============================================================================*/
+/** \defgroup PINMUX      PINMUX
+  * \brief
+  * \{
+  */
+
+/** \defgroup PINMUX_Exported_Constants PINMUX Exported Constants
+  * \brief
+  * \{
+  */
+
+/**
+ * \defgroup PINMUX_Declaration PINMUX Declaration
+ * \{
+ * \ingroup  PINMUX_Exported_Constants
+ */
+
+#define PAD_REG_BASE            (SYSON_BASE)
+#define PAD_DEBOUNCE_BASE       (SYSON_BASE + AON_REG_DEB_MUX_SEL)
+#define PAD_FUNCTION_BASE       (SYSON_BASE + AON_REG_PAD_VPON_REG0X)
+#define PAD_AONMUX_AS_BASE      (SYSON_BASE + AON_REG_PAD_AUTO_SW_AON_REG8X)
+#define PAD_PULL_AON_AS_BASE    (SYSON_BASE + AON_REG_PAD_AUTO_SW_AON_REG0X)
+#define PAD_PULL_CORE_AS_BASE   (SYSON_BASE + AON_REG_PAD_AUTO_SW_PON_REG0X)
+#define PINMUX_REG_BASE         (SYSON_BASE + PCC_r_PMUX_GPIO_P0_0to3)
+
+#define PAD_DEBOUNCE           ((PADDEB_TypeDef *) PAD_DEBOUNCE_BASE)
+#define PAD_FUNCTION           (*((volatile uint32_t *) PAD_FUNCTION_BASE))
+#define PINMUX                 ((PINMUX_TypeDef *) PINMUX_REG_BASE)
+
+/** End of PINMUX_Exported_Constants
+  * \}
+  */
+
+/** End of PINMUX_Declaration
+  * \}
+  */
+
+/** End of PINMUX
+  * \}
+  */
+
+/*============================================================================*
+ *                         PINMUX Private Types
+ *============================================================================*/
+
+/* 0x00
+   5:0     R/W    deb_mux_sel0        6'h3f
+   7:6     R      reserved10          2'b0
+   13:8    R/W    deb_mux_sel1        6'h3f
+   15:14   R      reserved8           2'b0
+   21:16   R/W    deb_mux_sel2        6'h3f
+   23:22   R      reserved6           2'b0
+   29:24   R/W    deb_mux_sel3        6'h3f
+   31:30   R      reserved4           2'b0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t deb_mux_sel0: 6;
+        const uint32_t reserved_3: 2;
+        uint32_t deb_mux_sel1: 6;
+        const uint32_t reserved_2: 2;
+        uint32_t deb_mux_sel2: 6;
+        const uint32_t reserved_1: 2;
+        uint32_t deb_mux_sel3: 6;
+        const uint32_t reserved_0: 2;
+    } b;
+} PAD_DEB_MUX_SEL_TypeDef;
+
+/* 0x04 ~ 0x0C
+   3:0     R      reserved20          4'h0
+   11:4    R/W    deb_cnt_l_cnt_limit 8'h0
+   14:12   R/W    deb_cnt_l_clk_div   3'h0
+   15      R/W    deb_cnt_l_en        1'b0
+   19:16   R      reserved16          4'h0
+   27:20   R/W    deb_cnt_h_cnt_limit 8'h0
+   30:28   R/W    deb_cnt_h_clk_div   3'h0
+   31      R/W    deb_cnt_h_en        1'b0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t reserved_1: 4;
+        uint32_t deb_cnt_l_cnt_limit: 8;
+        uint32_t deb_cnt_l_clk_div: 3;
+        uint32_t deb_cnt_l_en: 1;
+        const uint32_t reserved_0: 4;
+        uint32_t deb_cnt_h_cnt_limit: 8;
+        uint32_t deb_cnt_h_clk_div: 3;
+        uint32_t deb_cnt_h_en: 1;
+    } b;
+} PAD_DEB_CNT_TypeDef;
+
+/* 0x10
+   0       R/W1C  deb_cnt_0_sts       1'b1
+   1       R/W1C  deb_cnt_1_sts       1'b1
+   2       R/W1C  deb_cnt_2_sts       1'b1
+   3       R/W1C  deb_cnt_3_sts       1'b1
+   4       R/W1C  deb_cnt_4_sts       1'b1
+   31:5    R      reserved37          27'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t deb_cnt_0_sts: 1;
+        uint32_t deb_cnt_1_sts: 1;
+        uint32_t deb_cnt_2_sts: 1;
+        uint32_t deb_cnt_3_sts: 1;
+        uint32_t deb_cnt_4_sts: 1;
+        const uint32_t reserved_0: 27;
+    } b;
+} DEB_STS_TypeDef;
+
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint8_t reserved: 1;
+        uint8_t pd: 1;
+        uint8_t pu_en: 1;
+        uint8_t reserved1: 4;
+        uint8_t as_en: 1;
+    } b[4];
+} PADMUXAS_TypeDef;
+
+/*============================================================================*
+ *                         PINMUX Constants
+ *============================================================================*/
+/** \defgroup PINMUX      PINMUX
+  * \brief
+  * \{
+  */
+
+/** \defgroup PINMUX_Exported_Constants PINMUX Exported Constants
+  * \brief
+  * \{
+  */
+
+/**
+ * \defgroup    PIN_Function PIN Function
+ * \{
+ * \ingroup     PINMUX_Exported_Constants
+ */
+/******************* Reference: Bee5_pin_mux_20241231A-bitfile0103.xlsx *******************/
+#define IDLE_MODE                  0
+#define UART0_TX                   1
+#define UART0_RX                   2
+#define UART0_CTS                  3
+#define UART0_RTS                  4
+#define UART1_TX                   5
+#define UART1_RX                   6
+#define UART1_CTS                  7
+#define UART1_RTS                  8
+#define UART2_TX                   9
+#define UART2_RX                   10
+#define UART2_CTS                  11
+#define UART2_RTS                  12
+#define UART3_TX                   13
+#define UART3_RX                   14
+#define UART3_CTS                  15
+#define UART3_RTS                  16
+#define I2C0_CLK                   17
+#define I2C0_DAT                   18
+#define I2C1_CLK                   19
+#define I2C1_DAT                   20
+#define SPI0_SS_N_0_SLAVE          21
+#define SPI0_CLK_SLAVE             22
+#define SPI0_SO_SLAVE              23
+#define SPI0_SI_SLAVE              24
+#define SPI0_SS_N_0_MASTER         25
+#define SPI0_SS_N_1_MASTER         26
+#define SPI0_SS_N_2_MASTER         27
+#define SPI0_CLK_MASTER            28
+#define SPI0_MO_MASTER             29
+#define SPI0_MI_MASTER             30
+#define SPI1_SS_N_0_MASTER         31
+#define SPI1_SS_N_1_MASTER         32
+#define SPI1_SS_N_2_MASTER         33
+#define SPI1_CLK_MASTER            34
+#define SPI1_MO_MASTER             35
+#define SPI1_MI_MASTER             36
+#define SPI3W_DATA_MASTER          37
+#define SPI3W_CLK_MASTER           38
+#define SPI3W_CS_MASTER            39
+#define SPI3W_QB_MASTER            40
+#define PWM0                       41
+#define PWM1                       42
+#define PWM2                       43
+#define PWM3                       44
+#define PWM4                       45
+#define PWM5                       46
+#define PWM6_P                     47
+#define PWM6_N                     48
+#define PWM7_P                     49
+#define PWM7_N                     50
+#define PWM8_P                     51
+#define PWM8_N                     52
+#define PWM9_P                     53
+#define PWM9_N                     54
+#define IRDA_TX                    55
+#define IRDA_RX                    56
+#define CAN_TX                     57
+#define CAN_RX                     58
+#define SWD_CLK                    59
+#define SWD_DIO                    60
+#define DWGPIO                     90
+#define SPI2_SS_N_0_MASTER         91
+#define SPI2_CLK_MASTER            92
+#define SPI2_MO_MASTER             93
+#define SPI2_MI_MASTER             94
+#define DIG_DEBUG                  95
+#define DMIC1_CLK                  96
+#define DMIC1_DAT                  97
+#define LRC_I_CODEC_SLAVE          98
+#define BCLK_I_CODEC_SLAVE         99
+#define SDI_CODEC_SLAVE            100
+#define SDO_CODEC_SLAVE            101
+#define BT_COEX_I_0                106
+#define BT_COEX_I_1                107
+#define BT_COEX_I_2                108
+#define BT_COEX_I_3                109
+#define BT_COEX_O_0                110
+#define BT_COEX_O_1                111
+#define BT_COEX_O_2                112
+#define BT_COEX_O_3                113
+#define PTA_I2C_CLK_SLAVE          114
+#define PTA_I2C_DAT_SLAVE          115
+#define PTA_I2C_INT_OUT            116
+#define EN_EXPA                    117
+#define EN_EXLNA                   118
+#define TRACECLKIN                 119
+#define TRACESWO                   120
+#define LRC_SPORT0                 123
+#define BCLK_SPORT0                124
+#define ADCDAT_SPORT0              125
+#define DACDAT_SPORT0              126
+#define MCLK                       127
+#define KEY_COL_0                  128
+#define KEY_COL_1                  129
+#define KEY_COL_2                  130
+#define KEY_COL_3                  131
+#define KEY_COL_4                  132
+#define KEY_COL_5                  133
+#define KEY_COL_6                  134
+#define KEY_COL_7                  135
+#define KEY_COL_8                  136
+#define KEY_COL_9                  137
+#define KEY_COL_10                 138
+#define KEY_COL_11                 139
+#define KEY_COL_12                 140
+#define KEY_COL_13                 141
+#define KEY_COL_14                 142
+#define KEY_COL_15                 143
+#define KEY_COL_16                 144
+#define KEY_COL_17                 145
+#define KEY_COL_18                 146
+#define KEY_COL_19                 147
+#define KEY_ROW_0                  148
+#define KEY_ROW_1                  149
+#define KEY_ROW_2                  150
+#define KEY_ROW_3                  151
+#define KEY_ROW_4                  152
+#define KEY_ROW_5                  153
+#define KEY_ROW_6                  154
+#define KEY_ROW_7                  155
+#define KEY_ROW_8                  156
+#define KEY_ROW_9                  157
+#define KEY_ROW_10                 158
+#define KEY_ROW_11                 159
+#define KEY_ROW_12                 160
+#define KEY_ROW_13                 161
+#define KEY_ROW_14                 162
+#define KEY_ROW_15                 163
+#define KEY_ROW_16                 164
+#define KEY_ROW_17                 165
+
+/** End of PIN_Function
+  * \}
+  */
+
+/**
+ * \defgroup    PAD_Function_Config PAD Function Config
+ * \{
+ * \ingroup     PINMUX_Exported_Constants
+ */
+typedef enum
+{
+    LPPWM_CH0_SEL  = 0,
+    LPQDEC_LED_SEL = 1,
+    LPQDEC_PHB_SEL = 2,
+    LPQDEC_PHA_SEL = 3,
+} PADFuncConfig_TypeDef;
+
+/** End of PAD_Function_Config
+  * \}
+  */
+
+/**
+ * \defgroup    PAD_High_Speed_Config PAD High Speed Config
+ * \{
+ * \ingroup     PINMUX_Exported_Constants
+ */
+typedef enum
+{
+    PAD_HIGH_SPEED_SPI0 = 0,
+    PAD_HIGH_SPEED_SPI1 = 1,
+    PAD_HIGH_SPEED_SPI2 = 2,
+} PADHSConfig_Typedef;
+
+/** End of PAD_High_Speed_Config
+  * \}
+  */
+
+/**
+ * \defgroup    PAD_Driving_Current PAD Driving Current
+ * \{
+ * \ingroup     PINMUX_Exported_Constants
+ *
+ * \note        Others support 4/8mA Only
+ *              P2_0 ~ P2_7 support 4/8/12/16mA
+ *              P0_5 P5_1 P6_1 support 8/16/28mA
+ */
+typedef enum
+{
+    PAD_DRIVING_CURRENT_4mA,
+    PAD_DRIVING_CURRENT_8mA,
+    PAD_DRIVING_CURRENT_18mA,
+    PAD_DRIVING_CURRENT_28mA,
+} PADDrivingCurrent_TypeDef;
+
+
+typedef enum _PIN_POWER_GROUP
+{
+    PAD_POWER_GROUP_INVALID            = 0,
+    PAD_POWER_GROUP_RIGHT              = 1,
+    PAD_POWER_GROUP_LEFT               = 2,
+    PAD_POWER_GROUP_BOTTOM             = 3,
+} PADPowerGroup_TypeDef;
+
+/** End of PAD_Driving_Current
+  * \}
+  */
+
+/** End of PINMUX_Exported_Constants
+  * \}
+  */
+
+/** End of PINMUX
+  * \}
+  */
+
+/*============================================================================*
+ *                         PINMUX Private
+ *============================================================================*/
+#define BITOFFSET(n)                     (__builtin_ffs(n) - 1)
+#define PAD_REG_READ(addr)               (*((volatile uint32_t *)(addr)))
+#define PAD_REG_WRITE(addr, value)       (*((volatile uint32_t *)(addr)) = (value))
+#define Pad_TableConfig(Mode, Pin_Num, Value) do                                  \
+    {                                                                             \
+        uint32_t reg_addr_offset = PAD_REG_BASE + pad_addr_table.reg[Pin_Num];    \
+        uint32_t reg_high_offset = (reg_addr_offset & BIT1) ? 16 : 0;             \
+        reg_addr_offset &= ~BIT1;                                                 \
+        uint32_t reg_value = PAD_REG_READ(reg_addr_offset);                       \
+        reg_value &= ~(Mode << reg_high_offset);                                  \
+        if (Value) {                                                              \
+            reg_value |= (Value << BITOFFSET(Mode) << reg_high_offset);           \
+        }                                                                         \
+        PAD_REG_WRITE(reg_addr_offset, reg_value);                                \
+    } while(0)
+
+/* PAD Registers Field -------------------------------------- */
+#define OUTPUT_VAL                  (BIT0)
+#define OUTPUT_EN                   (BIT1)
+#define PULL_EN                     (BIT2)
+#define PULL_DIR                    (BIT3)
+#define PULL_RES                    (BIT4)
+#define WAKEUP_EN                   (BIT5)
+#define WAKEUP_POL                  (BIT6)
+#define POWER_SHDN                  (BIT7)
+#define PAD_DEB                     (BIT8)
+#define WAKEUP_RAP                  (BIT9)
+#define WAKEUP_PPU                  (BIT10)
+#define PAD_RSVD0                   (BIT11)
+#define CUR_DRIVING                 (BIT12)
+#define PAD_RSVD1                   (BIT13)
+#define AON_MUX                     (BIT14 | BIT15)
+#define PAD_CONFIG_MASK             (OUTPUT_VAL | OUTPUT_EN | PULL_EN | PULL_DIR | POWER_SHDN | AON_MUX)
+
+typedef struct
+{
+    uint16_t reg[TOTAL_PIN_NUM];
+} PADAddrTable_TypeDef;
+
+typedef struct
+{
+    uint8_t reg[TOTAL_PIN_NUM];
+} PINMUXIndexTable_TypeDef;
+
+#ifdef  __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* RTL_PINMUX_DEF_H */
diff --git a/bee/drivers/pinmux/src/device/rtl87x2j/rtl_wakeup.c b/bee/drivers/pinmux/src/device/rtl87x2j/rtl_wakeup.c
new file mode 100644
index 00000000..cd300a66
--- /dev/null
+++ b/bee/drivers/pinmux/src/device/rtl87x2j/rtl_wakeup.c
@@ -0,0 +1,657 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *                           Header Files
+ *============================================================================*/
+#include "rtl_wakeup.h"
+#include "rtl_pinmux.h"
+#include "rtl_nvic.h"
+
+/*============================================================================*
+ *                           Private Defines
+ *============================================================================*/
+#define DEBOUNCE_GROUP_USED_MASK    (0xFFFFFFF0)
+static uint32_t debounce_group_allocated_mask = DEBOUNCE_GROUP_USED_MASK;
+
+#define PAD_BIT_TABLE_OFFSET        (11)
+#define PAD_ITEM(reg_addr, bit_num) (reg_addr | (bit_num << PAD_BIT_TABLE_OFFSET))
+#define PAD_ITEM_ADDR(item)         (item & 0x7FF)
+#define PAD_ITEM_BIT_OFFSET(item)   ((item & 0xF800) >> PAD_BIT_TABLE_OFFSET)
+
+#define PAD_INT_STS_W1C_MASK_GROUP0   0x00FFF0FF
+#define PAD_INT_STS_W1C_MASK_GROUP1   0x1FEC07FF
+#define PAD_INT_STS_W1C_MASK_GROUP2   0x58000000
+#define PAD_INT_STS_W1C_MASK_GROUP3   0x7E000000
+
+static void Pad_Handler(void);
+
+static volatile uint64_t pad_int_used_mask = 0x0;
+
+extern const PADAddrTable_TypeDef pad_addr_table;
+const PADAddrTable_TypeDef wakeup_status_table =
+{
+    .reg[P0_0] =        PAD_ITEM(0x17C, 0),
+    .reg[P0_1] =        PAD_ITEM(0x17C, 1),
+    .reg[P0_2] =        PAD_ITEM(0x17C, 2),
+    .reg[P0_3] =        PAD_ITEM(0x17C, 3),
+    .reg[P0_4] =        PAD_ITEM(0x17C, 4),
+    .reg[P0_5] =        PAD_ITEM(0x17C, 5),
+    .reg[P0_6] =        PAD_ITEM(0x17C, 6),
+    .reg[P0_7] =        PAD_ITEM(0x17C, 7),
+    .reg[P1_0] =        PAD_ITEM(0x17C, 12),
+    .reg[P1_1] =        PAD_ITEM(0x17C, 13),
+    .reg[P1_6] =        PAD_ITEM(0x17C, 14),
+    .reg[P1_7] =        PAD_ITEM(0x17C, 15),
+    .reg[P2_0] =        PAD_ITEM(0x17C, 16),
+    .reg[P2_1] =        PAD_ITEM(0x17C, 17),
+    .reg[P2_2] =        PAD_ITEM(0x17C, 18),
+    .reg[P2_3] =        PAD_ITEM(0x17C, 19),
+    .reg[P2_4] =        PAD_ITEM(0x17C, 20),
+    .reg[P2_5] =        PAD_ITEM(0x17C, 21),
+    .reg[P2_6] =        PAD_ITEM(0x17C, 22),
+    .reg[P2_7] =        PAD_ITEM(0x17C, 23),
+    .reg[P3_0] =        PAD_ITEM(0x180, 0),
+    .reg[P3_1] =        PAD_ITEM(0x180, 1),
+    .reg[P3_2] =        PAD_ITEM(0x180, 2),
+    .reg[P3_3] =        PAD_ITEM(0x180, 3),
+    .reg[P3_4] =        PAD_ITEM(0x180, 4),
+    .reg[P3_5] =        PAD_ITEM(0x180, 5),
+    .reg[P3_6] =        PAD_ITEM(0x180, 6),
+    .reg[P4_0] =        PAD_ITEM(0x180, 7),
+    .reg[P4_1] =        PAD_ITEM(0x180, 8),
+    .reg[P4_2] =        PAD_ITEM(0x180, 9),
+    .reg[P4_3] =        PAD_ITEM(0x180, 10),
+    .reg[MICBIAS] =     PAD_ITEM(0x184, 30),
+    .reg[P5_1] =        PAD_ITEM(0x180, 18),
+    .reg[P5_2] =        PAD_ITEM(0x180, 19),
+    .reg[P6_0] =        PAD_ITEM(0x180, 21),
+    .reg[P6_1] =        PAD_ITEM(0x180, 22),
+    .reg[P6_2] =        PAD_ITEM(0x180, 23),
+    .reg[P6_3] =        PAD_ITEM(0x180, 24),
+    .reg[P6_4] =        PAD_ITEM(0x180, 25),
+    .reg[P6_5] =        PAD_ITEM(0x180, 26),
+    .reg[P6_6] =        PAD_ITEM(0x180, 27),
+    .reg[P6_7] =        PAD_ITEM(0x180, 28),
+    .reg[P7_0] =        PAD_ITEM(0x184, 27),
+    .reg[P7_1] =        PAD_ITEM(0x184, 28),
+    .reg[SPIC_CSN] =    PAD_ITEM(0x198, 30),
+    .reg[SPIC_SCK] =    PAD_ITEM(0x198, 29),
+    .reg[SPIC_SI] =     PAD_ITEM(0x198, 28),
+    .reg[SPIC_SO] =     PAD_ITEM(0x198, 27),
+    .reg[SPIC_WEN] =    PAD_ITEM(0x198, 26), /*!< P1_4 */
+    .reg[SPIC_HOLDEN] = PAD_ITEM(0x198, 25), /*!< P1_3 */
+};
+
+/*============================================================================*
+ *                        Public Functions
+ *============================================================================*/
+#if (PAD_SUPPORT_WAKEUP_DEBOUNCE_MULTI_GROUP == 1)
+static uint8_t System_WakeUpDebounceGetGroup(uint8_t Pin_Num)
+{
+    for (uint8_t i = 0; i <= 3; i++)
+    {
+        if (((PAD_DEBOUNCE->MUX_SEL >> (i << 3)) & 0x3F) == 0x3F)
+        {
+            continue;
+        }
+        if (((PAD_DEBOUNCE->MUX_SEL >> (i << 3)) & 0x3F) == Pin_Num)
+        {
+            return i;
+        }
+    }
+    return 4;
+}
+
+bool System_WakeUpDebounceMultiGroupEnable(uint8_t Pin_Num)
+{
+    bool is_alloc_success = false;
+    uint8_t deb_group = System_WakeUpDebounceGetGroup(Pin_Num);
+
+    if (deb_group <= 3)
+    {
+        /* Already allocate group */
+        return true;
+    }
+
+    for (deb_group = 0; deb_group < 4; deb_group++)
+    {
+        if (!(debounce_group_allocated_mask & BIT(deb_group)))
+        {
+            debounce_group_allocated_mask |= BIT(deb_group);
+            is_alloc_success = true;
+
+            PAD_DEBOUNCE->MUX_SEL &= ~(0x3F << (deb_group << 3));
+            PAD_DEBOUNCE->MUX_SEL |= (Pin_Num << (deb_group << 3));
+
+            break;
+        }
+    }
+
+    return is_alloc_success;
+}
+
+bool System_WakeUpDebounceMultiGroupDisable(uint8_t Pin_Num)
+{
+    uint8_t deb_group = System_WakeUpDebounceGetGroup(Pin_Num);
+
+    if (deb_group <= 3)
+    {
+        debounce_group_allocated_mask &= ~BIT(deb_group);
+        PAD_DEBOUNCE->MUX_SEL |= (0x3F << (deb_group << 3));
+
+        return true;
+    }
+
+    return false;
+}
+#endif
+
+/**
+  * \brief  Enable the function of the wakeup system of the specified pin.
+  * \param  Pin_Num: Pin number to be configured. \ref Pin_Number.
+  * \param  Polarity: use high or low level wakeu to wakeup system.
+            This parameter is can be PAD_WAKEUP_POL_HIGH and PAD_WAKEUP_POL_LOW.
+  * \param  DebounceEn: Enable or disable debounce function.
+            This parameter is can be PAD_WK_DEBOUNCE_ENABLE and PAD_WK_DEBOUNCE_DISABLE.
+  * \return None
+  */
+void System_WakeUpPinEnable(uint8_t Pin_Num, SystemWakeUpPolarity_TypeDef Polarity,
+                            FunctionalState DebounceNewState)
+{
+    /* Disable PAD interrupt NVIC */
+    NVIC_DisableIRQ(PAD_IRQn);
+
+    /* Config PAD wakeup polarity */
+    Pad_TableConfig(WAKEUP_POL, Pin_Num, Polarity);
+
+    /* Config PAD wakeup debounce */
+    Pad_TableConfig(PAD_DEB, Pin_Num, DebounceNewState);
+
+    if (DebounceNewState == ENABLE)
+    {
+        System_WakeUpDebounceCmd(Pin_Num, ENABLE);
+    }
+
+    /* Enable PAD interrupt wakeup function */
+    Pad_TableConfig(WAKEUP_EN, Pin_Num, ENABLE);
+
+    /* Initialize NVIC only on first PIN enable */
+    if (pad_int_used_mask == 0)
+    {
+        /* Record pad int use status */
+        pad_int_used_mask |= BIT64(Pin_Num);
+
+        /* Enable PAD interrupt at AON REG */
+        AON_REG_WRITE_BITFIELD(AON_REG_SYSTEM_REG29X, GPIO_PORT_INT_EN, ENABLE);
+
+        /* Config NVIC vector and enable */
+        ram_vector_table_update(PAD_IRQn, (IRQ_Fun)Pad_Handler);
+
+        NVIC_InitTypeDef pad_nvic;
+        pad_nvic.NVIC_IRQChannel = PAD_IRQn;
+        pad_nvic.NVIC_IRQChannelPriority = 5;
+        pad_nvic.NVIC_IRQChannelCmd = (FunctionalState)ENABLE;
+        NVIC_Init(&pad_nvic);
+
+        /* Record pad int use status */
+        pad_int_used_mask |= BIT64(Pin_Num);
+    }
+    else
+    {
+        /* Record pad int use status */
+        pad_int_used_mask |= BIT64(Pin_Num);
+
+        /* Re-enable NVIC for subsequent PINs */
+        NVIC_EnableIRQ(PAD_IRQn);
+    }
+}
+
+/**
+  * \brief  Disable the function of the wakeup system of the specified pin.
+  * \param  Pin_Num: Pin number to be configured. \ref Pin_Number.
+  * \return None
+  */
+void System_WakeUpPinDisable(uint8_t Pin_Num)
+{
+    Pad_TableConfig(WAKEUP_EN, Pin_Num, DISABLE);
+
+    /* Record pad int use status */
+    pad_int_used_mask &= ~BIT64(Pin_Num);
+
+    /* If no PAD use interrupt */
+    if (pad_int_used_mask == 0)
+    {
+        /* Pad NVIC Disable */
+        AON_REG_WRITE_BITFIELD(AON_REG_SYSTEM_REG29X, GPIO_PORT_INT_EN, DISABLE);
+
+        NVIC_DisableIRQ(PAD_IRQn);
+    }
+
+}
+
+/**
+  * \brief  Check wake up pin interrupt status.
+  * \param  Pin_Num: Pin number to be configured. \ref Pin_Number.
+  * \return Pin interrupt status
+  */
+uint8_t System_WakeUpInterruptValue(uint8_t Pin_Num)
+{
+    uint32_t reg_address = PAD_REG_BASE + PAD_ITEM_ADDR(wakeup_status_table.reg[Pin_Num]);
+    uint32_t reg_value = PAD_REG_READ(reg_address);
+
+    if (reg_value & BIT(PAD_ITEM_BIT_OFFSET(wakeup_status_table.reg[Pin_Num])))
+    {
+        return SET;
+    }
+    return RESET;
+}
+
+#if (PAD_SUPPORT_WAKEUP_DEBOUNCE == 1)
+
+/**
+ * \brief  Enable or disable wakeup debounce function.
+ * \param  Pin_Num: Pin number to be configured. \ref Pin_Number.
+ *         \note: Pin_Num is invalid parameter for rtl87x2g series
+ *                so that any pin can be filled in.
+ * \param  FunctionalState: wakeup system enable or disable.
+ *         \arg DISABLE: Disable wakeup.
+ *         \arg ENABLE: Enable wakeup.
+ * \return None.
+ */
+bool System_WakeUpDebounceCmd(uint8_t Pin_Num, FunctionalState NewState)
+{
+    Pad_TableConfig(PAD_DEB, Pin_Num, NewState);
+    uint32_t deb_group = System_WakeUpDebounceGetGroup(Pin_Num);
+    PAD_DEB_CNT_TypeDef pad_deb = {.d32 = PAD_DEBOUNCE->CNT[deb_group / 2]};
+    if (deb_group % 2)
+    {
+        pad_deb.b.deb_cnt_h_en = NewState;
+    }
+    else
+    {
+        pad_deb.b.deb_cnt_l_en = NewState;
+    }
+    PAD_DEBOUNCE->CNT[deb_group / 2] = pad_deb.d32;
+
+    return true;
+}
+
+/**
+ * \brief  Config wak-up system debounce time.
+ * \param  Pin_Num: Pin number to be configured. \ref Pin_Number.
+ *         \note: Pin_Num is invalid parameter for rtl87x2g series
+ *                so that any pin can be filled in.
+ * \param  time: Debounce time, 1 ~ 255ms.
+ * \return None.
+ */
+bool System_WakeUpDebounceTime(uint8_t Pin_Num, uint8_t TimeMs)
+{
+    uint32_t deb_group = System_WakeUpDebounceGetGroup(Pin_Num);
+    PAD_DEB_CNT_TypeDef pad_deb = {.d32 = PAD_DEBOUNCE->CNT[deb_group / 2]};
+    if (deb_group % 2)
+    {
+        pad_deb.b.deb_cnt_h_clk_div = 5;
+        pad_deb.b.deb_cnt_h_cnt_limit = TimeMs - 1;
+    }
+    else
+    {
+        pad_deb.b.deb_cnt_l_clk_div = 5;
+        pad_deb.b.deb_cnt_l_cnt_limit = TimeMs - 1;
+    }
+    PAD_DEBOUNCE->CNT[deb_group / 2] = pad_deb.d32;
+
+    return true;
+}
+
+bool System_WakeUpDebounceTimeUs(uint8_t Pin_Num, uint32_t TimeUs)
+{
+    uint8_t deb_div = 0;
+    for (deb_div = 0; deb_div <= 6 /* 0x7 is bypass divide */; deb_div++)
+    {
+        if (TimeUs <= ((1 << deb_div) * 8000))  /* (1 << 8) / (32000 / 1000 / 1000) = 8000 */
+        {
+            break;
+        }
+    }
+
+    uint32_t deb_group = System_WakeUpDebounceGetGroup(Pin_Num);
+    PAD_DEB_CNT_TypeDef pad_deb = {.d32 = PAD_DEBOUNCE->CNT[deb_group / 2]};
+    if (deb_group % 2)
+    {
+        pad_deb.b.deb_cnt_h_clk_div = deb_div;
+        pad_deb.b.deb_cnt_h_cnt_limit = TimeUs * 32 / 1000 / (1 << deb_div) - 1;
+    }
+    else
+    {
+        pad_deb.b.deb_cnt_l_clk_div = deb_div;
+        pad_deb.b.deb_cnt_l_cnt_limit = TimeUs * 32 / 1000 / (1 << deb_div) - 1;
+    }
+    PAD_DEBOUNCE->CNT[deb_group / 2] = pad_deb.d32;
+
+    return true;
+}
+
+/**
+  * \brief  Check debounce wake up status.
+  * \param  Pin_Num: Pin number to be configured. \ref Pin_Number.
+  *         \note: Pin_Num is invalid parameter for rtl87x2g series
+  *                so that any pin can be filled in.
+  * \return Debounce wakeup status.
+  */
+uint8_t System_WakeUpDebounceStatus(uint8_t Pin_Num)
+{
+    uint32_t deb_group = System_WakeUpDebounceGetGroup(Pin_Num);
+
+    return ((PAD_DEBOUNCE->STS & BIT(deb_group)) == BIT(deb_group));
+}
+
+/**
+  * \brief  Clear debounce wake up status.
+  * \note:  Call this API will clear the debunce wakeup status bit.
+  * \param  Pin_Num: Pin number to be configured. \ref Pin_Number.
+  *         \note: Pin_Num is invalid parameter for rtl87x2g series
+  *                so that any pin can be filled in.
+  * \return None.
+  */
+void System_WakeUpDebounceClear(uint8_t Pin_Num)
+{
+    uint32_t deb_group = System_WakeUpDebounceGetGroup(Pin_Num);
+
+    PAD_DEBOUNCE->STS = BIT(deb_group);
+}
+#endif
+
+/**
+  * \brief  Enable or disable the function of the wakeup system of the specified pin.
+  * \param  Pin_Num: Pin number to be configured. \ref Pin_Number.
+  * \param  NewState: Enable or disable PAD wake up.
+  *            This parameter can be one of the following values:
+  *            \arg ENABLE: Enable PAD wake up system.
+  *            \arg DISABLE: Disable PAD wake up system.
+  * \return None.
+  */
+void System_WakeUpCmd(uint8_t Pin_Num, FunctionalState NewState)
+{
+    Pad_TableConfig(WAKEUP_EN, Pin_Num, NewState);
+}
+
+/**
+  * \brief Set the polarity for the function of the wakeup system of the specified pin.
+  * \param Pin_Num: Pin number to be configured. \ref Pin_Number.
+  * \param Polarity: Polarity of wakeup system.
+  *            This parameter can be the following:
+  *            \arg SYSTEM_WAKEUP_POLARITY_HIGH: Use high level wakeup.
+  *            \arg SYSTEM_WAKEUP_POLARITY_LOW: Use low level wakeup.
+  * \return None.
+  */
+void System_SetWakeUpPinPolarity(uint8_t Pin_Num, SystemWakeUpPolarity_TypeDef WakeUpPolarity)
+{
+    Pad_TableConfig(WAKEUP_POL, Pin_Num, WakeUpPolarity);
+}
+
+/**
+ * \brief  Clear the interrupt pendign bit of the specified pin
+ * \param  Pin_Num: Pin number to be configured. \ref Pin_Number
+ * \return None.
+ */
+void System_WakeUpClearINTPendingBit(uint8_t Pin_Num)
+{
+    /* Calculate the absolute register address based on the pin number lookup table */
+    uint32_t reg_address = PAD_REG_BASE + PAD_ITEM_ADDR(wakeup_status_table.reg[Pin_Num]);
+    /* Get the specific bit mask (Set '1' to the target bit) that needs to be cleared */
+    uint32_t reg_value = BIT(PAD_ITEM_BIT_OFFSET(wakeup_status_table.reg[Pin_Num]));
+    /* Variable to store the mask of ALL W1C (Write 1 to Clear) bits in the target register */
+    uint32_t page_write_mask = 0;
+    /* Identify the target register and assign the corresponding W1C bit mask */
+    switch (reg_address)
+    {
+    case PAD_REG_BASE + AON_REG_PAD_REG23X:
+        page_write_mask = PAD_INT_STS_W1C_MASK_GROUP0;
+        break;
+
+    case PAD_REG_BASE + AON_REG_PAD_REG24X:
+        page_write_mask = PAD_INT_STS_W1C_MASK_GROUP1;
+        break;
+
+    case PAD_REG_BASE + AON_REG_PAD_REG25X:
+        page_write_mask = PAD_INT_STS_W1C_MASK_GROUP2;
+        break;
+
+    case PAD_REG_BASE + AON_REG_SPI_PAD_REG30X:
+        page_write_mask = PAD_INT_STS_W1C_MASK_GROUP3;
+        break;
+
+    default:
+        break;
+    }
+    /*
+     * Safe Read-Modify-Write for W1C registers:
+     * 1. PAD_REG_READ(reg_address) : Read the current register value.
+     * 2. & (~page_write_mask)      : Mask out (set to 0) ALL W1C bits to prevent accidentally
+     *                                writing '1' back to other pending bits (which would clear them).
+     *                                Normal R/W config bits are preserved.
+     * 3. | reg_value               : Set '1' ONLY to the target status bit we want to clear.
+     */
+    PAD_REG_WRITE(reg_address, (PAD_REG_READ(reg_address) & (~page_write_mask)) | reg_value);
+}
+
+/**
+ * \brief Clear all wake up pin interrupt pending bit.
+ * \param  None.
+ * \return None.
+ */
+void System_WakeUpClearAllINT(void)
+{
+    uint32_t reg_address0 = PAD_REG_BASE + AON_REG_PAD_REG23X;
+    uint32_t reg_address1 = PAD_REG_BASE + AON_REG_PAD_REG24X;
+    uint32_t reg_address2 = PAD_REG_BASE + AON_REG_PAD_REG25X;
+    uint32_t reg_address3 = PAD_REG_BASE + AON_REG_SPI_PAD_REG30X;
+    PAD_REG_WRITE(reg_address0, PAD_REG_READ(reg_address0) | PAD_INT_STS_W1C_MASK_GROUP0);
+    PAD_REG_WRITE(reg_address1, PAD_REG_READ(reg_address1) | PAD_INT_STS_W1C_MASK_GROUP1);
+    PAD_REG_WRITE(reg_address2, PAD_REG_READ(reg_address2) | PAD_INT_STS_W1C_MASK_GROUP2);
+    PAD_REG_WRITE(reg_address3, PAD_REG_READ(reg_address3) | PAD_INT_STS_W1C_MASK_GROUP3);
+
+    PAD_DEBOUNCE->STS = (BIT0 | BIT1 | BIT2 | BIT3 | BIT4);
+}
+
+/**
+  * \brief  Configure wakeup PPU function for the specified pin.
+  * \param  Pin_Num: The number of the pin to configure. See \ref Pin_Number.
+  * \param  Polarity: Select pin wakeup polarity (high level or low level).
+  *         This parameter can be PAD_WAKEUP_POL_HIGH or PAD_WAKEUP_POL_LOW.
+  * \param  NewState: Enable or disable the wakeup PPU function.
+  *         This parameter can be ENABLE or DISABLE.
+  * \return None
+  */
+void System_WakeUpPPUCmd(uint8_t Pin_Num, uint8_t Polarity, FunctionalState NewState)
+{
+    Pad_TableConfig(WAKEUP_POL, Pin_Num, Polarity);
+    Pad_TableConfig(WAKEUP_PPU, Pin_Num, NewState);
+    AON_REG_WRITE_BITFIELD(AON_REG_SYSTEM_REG29X, EN_PAD_SYSTEM_ON_WAKEUP, NewState);
+}
+
+/**
+  * \brief  Configure wakeup RAP function for the specified pin.
+  * \param  Pin_Num: The number of the pin to configure. See \ref Pin_Number.
+  * \param  Polarity: Select pin wakeup polarity (high level or low level).
+  *         This parameter can be PAD_WAKEUP_POL_HIGH or PAD_WAKEUP_POL_LOW.
+  * \param  NewState: Enable or disable wakeup RAP function.
+  *         This parameter can be ENABLE or DISABLE.
+  * \return None
+  */
+void System_WakeUpRAPCmd(uint8_t Pin_Num, uint8_t Polarity, FunctionalState NewState)
+{
+    Pad_TableConfig(WAKEUP_POL, Pin_Num, Polarity);
+    Pad_TableConfig(WAKEUP_RAP, Pin_Num, NewState);
+}
+
+/**
+  * \brief  Configure wakeup off mode(power down) function for the specified pin.
+  * \param  Pin_Num: The number of the pin to configure. See \ref Pin_Number.
+  * \param  Polarity: Select pin wakeup polarity (high level or low level).
+  *         This parameter can be PAD_WAKEUP_POL_HIGH or PAD_WAKEUP_POL_LOW.
+  * \param  NewState: Enable or disable wakeup RAP function.
+  *         This parameter can be ENABLE or DISABLE.
+  * \return None
+  */
+void System_WakeUpPDCmd(uint8_t Pin_Num, uint8_t Polarity, FunctionalState NewState)
+{
+    Pad_TableConfig(WAKEUP_POL, Pin_Num, Polarity);
+    Pad_TableConfig(WAKEUP_EN, Pin_Num, NewState);
+}
+
+/*============================================================================*
+ *                           PAD INTERRUPT
+ *============================================================================*/
+/* Define invalid index */
+#define PAD_ISR_IDX_INVALID  0xFF
+
+/* Define linked list node structure for PAD ISR */
+typedef struct PadIsrNode
+{
+    P_PAD_CBACK  pad_callback;   /* Pointer to the callback function
+                                    to be executed when the pad wakes up. */
+    uint32_t     context;        /* User-defined context passed to
+                                    the callback function. */
+    uint8_t      pin_num;        /* The specific GPIO pin number associated
+                                    with this wake-up interrupt. */
+    uint8_t      next_idx;       /* Index of the next node in the static
+                                    memory pool linked list. */
+    bool         is_used;        /* Status flag indicating whether this node
+                                    is currently allocated (true) or free (false). */
+} T_PAD_ISR_NODE;
+
+/* Define static memory pool: support up to TOTAL_PIN_NUM concurrent wake-up pins */
+static T_PAD_ISR_NODE g_pad_node_pool[TOTAL_PIN_NUM];
+
+/* Linked list head index, initialized to invalid value */
+static uint8_t g_pad_isr_head_idx = PAD_ISR_IDX_INVALID;
+
+/**
+  * \brief  Pad handler function.
+  * \return None.
+  */
+static void Pad_Handler(void)
+{
+    /* Clear PAD interrupt status */
+    AON_REG_WRITE_BITFIELD(AON_REG_SYSTEM_REG29X, GPIO_INTR_PORT, true);
+
+    /* Iterate through the registered callback linked list using index */
+    uint8_t curr_idx = g_pad_isr_head_idx;
+
+    while (curr_idx != PAD_ISR_IDX_INVALID)
+    {
+        /* Get current node pointer via index for easy access */
+        T_PAD_ISR_NODE *curr_node = &g_pad_node_pool[curr_idx];
+
+        /* Check if there is a pending interrupt for the current node's PIN */
+        if (System_WakeUpInterruptValue(curr_node->pin_num))
+        {
+            /* Invoke the callback function */
+            if (curr_node->pad_callback)
+            {
+                curr_node->pad_callback(curr_node->context);
+            }
+        }
+
+        /* Move to the next node */
+        curr_idx = curr_node->next_idx;
+    }
+}
+
+/**
+  * \brief  Register the callback function of the wake-up system of the specified pin.
+  *
+  * \param[in] Pin_Num: Pin number to be configured. \ref Pin_Number.
+  *
+  * \param[in] Callback: Callback function.
+  *
+  * \param[in] Context: Context of the callback
+  *
+  * \return None.
+  */
+void System_RegisterPadWakeupCallback(uint8_t Pin_Num, P_PAD_CBACK Callback, uint32_t Context)
+{
+    if (!IS_PIN_NUMBER(Pin_Num))
+    {
+        return;
+    }
+
+    uint16_t pad_item = wakeup_status_table.reg[Pin_Num];
+    if (!pad_item)
+    {
+        return;
+    }
+
+    uint8_t curr_idx = g_pad_isr_head_idx;
+    uint8_t prev_idx = PAD_ISR_IDX_INVALID;
+
+    /* Check if the Pin_Num is already registered */
+    while (curr_idx != PAD_ISR_IDX_INVALID)
+    {
+        T_PAD_ISR_NODE *curr_node = &g_pad_node_pool[curr_idx];
+
+        if (curr_node->pin_num == Pin_Num)
+        {
+            /* 1. If the PIN already exists in the list */
+            if (Callback != NULL)
+            {
+                /* Update the existing Callback and Context */
+                curr_node->pad_callback = Callback;
+                curr_node->context      = Context;
+            }
+            else
+            {
+                /* If the given Callback is NULL, it means unregistration.
+                   Remove the node and free memory. */
+                if (prev_idx == PAD_ISR_IDX_INVALID)
+                {
+                    /* Remove head node */
+                    g_pad_isr_head_idx = curr_node->next_idx;
+                }
+                else
+                {
+                    /* Remove middle or tail node */
+                    g_pad_node_pool[prev_idx].next_idx = curr_node->next_idx;
+                }
+                curr_node->is_used = false;
+            }
+            return;
+        }
+        prev_idx = curr_idx;
+        curr_idx = curr_node->next_idx;
+    }
+
+    /* 2. If it doesn't exist and Callback is valid, allocate a new node from the pool */
+    if (Callback != NULL)
+    {
+        uint8_t new_idx = PAD_ISR_IDX_INVALID;
+
+        /* Find a free node from the static pool */
+        for (uint8_t i = 0; i < TOTAL_PIN_NUM; i++)
+        {
+            if (!g_pad_node_pool[i].is_used)
+            {
+                new_idx = i;
+                g_pad_node_pool[i].is_used = true;
+                break;
+            }
+        }
+
+        if (new_idx != PAD_ISR_IDX_INVALID)
+        {
+            T_PAD_ISR_NODE *new_node = &g_pad_node_pool[new_idx];
+            new_node->pin_num      = Pin_Num;
+            new_node->pad_callback = Callback;
+            new_node->context      = Context;
+
+            /* Insert the new node at the head of the list */
+            new_node->next_idx = g_pad_isr_head_idx;
+            g_pad_isr_head_idx = new_idx;
+        }
+    }
+}
diff --git a/bee/drivers/pm/CMakeLists.txt b/bee/drivers/pm/CMakeLists.txt
new file mode 100644
index 00000000..3008f51f
--- /dev/null
+++ b/bee/drivers/pm/CMakeLists.txt
@@ -0,0 +1,6 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+if(CONFIG_SOC_SERIES_RTL87X2J)
+    zephyr_include_directories(inc/rtl87x2j)
+endif()
diff --git a/bee/drivers/pm/inc/rtl87x2j/pck600.h b/bee/drivers/pm/inc/rtl87x2j/pck600.h
new file mode 100644
index 00000000..2cdccbc0
--- /dev/null
+++ b/bee/drivers/pm/inc/rtl87x2j/pck600.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+
+/*============================================================================*
+ *               Define to prevent recursive inclusion
+ *============================================================================*/
+#ifndef __PCK600_H
+#define __PCK600_H
+
+/*============================================================================*
+ *                               Header Files
+ *============================================================================*/
+
+
+/*============================================================================*
+ *                              Compile Checkers
+ *============================================================================*/
+
+/*============================================================================*
+ *                              Types
+ *============================================================================*/
+typedef enum
+{
+    POWER_POLICY_SYSTEM_OFF                 = 0x0,
+    POWER_POLICY_SYSTEM_ON_LOW_POWER        = 0x1,
+    POWER_POLICY_SYSTEM_ON_CONST_LATENCY    = 0x2,
+    POWER_POLICY_SYSTEM_ON_ACTIVE           = 0x3,
+    POWER_POLICY_SYSTEM_MAX,
+
+    POWER_POLICY_SYSTEM_INVALID             = 0xFF,
+} POWER_POLICY_SYSTEM;
+
+extern void (*pck600_system_set_dynamic_power_policy)(POWER_POLICY_SYSTEM);
+
+
+#endif /* __PCK600_H */
diff --git a/bee/drivers/pwm/CMakeLists.txt b/bee/drivers/pwm/CMakeLists.txt
new file mode 100644
index 00000000..71d1bde0
--- /dev/null
+++ b/bee/drivers/pwm/CMakeLists.txt
@@ -0,0 +1,8 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+if(CONFIG_REALTEK_BEE_COMMON_DRIVER)
+    zephyr_include_directories(inc)
+endif()
+
+add_subdirectory_ifdef(CONFIG_REALTEK_BEE_PWM src)
diff --git a/bee/drivers/pwm/Kconfig b/bee/drivers/pwm/Kconfig
new file mode 100644
index 00000000..ea5f1abf
--- /dev/null
+++ b/bee/drivers/pwm/Kconfig
@@ -0,0 +1,8 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config REALTEK_BEE_PWM
+	bool "Realtek Bee PWM driver"
+	default n
+	help
+	  This option enables the PWM driver for Realtek Bee.
diff --git a/bee/drivers/pwm/inc/rtl_lppwm.h b/bee/drivers/pwm/inc/rtl_lppwm.h
new file mode 100644
index 00000000..f567d9ce
--- /dev/null
+++ b/bee/drivers/pwm/inc/rtl_lppwm.h
@@ -0,0 +1,133 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *               Define to prevent recursive inclusion
+ *============================================================================*/
+#ifndef RTL_WDT_H
+#define RTL_WDT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*============================================================================*
+ *                               Header Files
+*============================================================================*/
+#include "utils/rtl_utils.h"
+#if defined (CONFIG_SOC_SERIES_RTL87X2G)
+#include "wdt/src/rtl87x2g/rtl_wdt_def.h"
+#elif defined (CONFIG_SOC_SERIES_RTL87X3E)
+#include "wdt/src/rtl87x3e/rtl_wdt_def.h"
+#elif defined (CONFIG_SOC_SERIES_RTL87X3D)
+#include "wdt/src/rtl87x3d/rtl_wdt_def.h"
+#elif defined (CONFIG_SOC_SERIES_RTL8762J)
+#include "wdt/src/rtl87x2j/rtl_wdt_def.h"
+#endif
+
+/** \defgroup WDT         WDT
+  * \brief
+  * \{
+  */
+
+/*============================================================================*
+ *                         Types
+ *============================================================================*/
+/** \defgroup WDT_Exported_Types WDT Exported Types
+  * \brief
+  * \{
+  */
+
+/**
+  * \brief       WDT Mode structure definition.
+  *
+  * \ingroup     WDT_Exported_Types
+  */
+typedef enum
+{
+    RESET_ALL = 0,                //!< Reset all.
+    RESET_ALL_EXCEPT_AON = 1,     //!< Reset all except RTC and some AON register.
+    INTERRUPT_CPU = 2,            //!< Interrupt CPU.
+    WDT_MODE_NUM = 3,             //!< The maximum selectable value for WDT mode.
+} WDTMode_TypeDef;
+
+#define IS_WDT_Mode(MODE) (((MODE) == RESET_ALL) || \
+                           ((MODE) == RESET_ALL_EXCEPT_AON) || \
+                           ((MODE) == INTERRUPT_CPU)) //!< Check if the input parameter is valid.
+
+/** End of group WDT_Exported_Types
+  * \}
+  */
+
+/*============================================================================*
+ *                         Functions
+ *============================================================================*/
+/** \defgroup WDT_Exported_Functions WDT Exported Functions
+  * \{
+  */
+
+/**
+ * \brief  Start WDT. This function will enable WDT clock, set and start WDT.
+ *
+ * \param[in]  TimeMs  WDT Timeout Time. Unit: ms.
+ * \param[in]  Mode    Refer to \ref WDTMode_TypeDef. If the Reset WDT operation is not performed within the Timeout period,
+ *                     the configured mode operation will be executed.
+ *
+ * \return  true or false.
+ *          - true: WDT mode set successfully, enabling the function..
+ *          - false: WDT setting failed.
+ */
+bool WDT_Start(uint32_t TimeMs, WDTMode_TypeDef Mode);
+
+/**
+ * \brief  Enable WDT.
+ */
+void WDT_Enable(void);
+
+/**
+ * \brief  Disable WDT.
+ */
+void WDT_Disable(void);
+
+/**
+ * \brief  Kick WDT to restart WDT.
+ */
+void WDT_Kick(void);
+
+/**
+ * \brief  Is WDT enable.
+ *
+ * \return Is WDT enable or not
+ */
+bool WDT_IsEnable(void);
+
+/**
+ * \brief  Get WDT timeout.
+ *
+ * \return WDT timeout
+ */
+uint32_t WDT_GetTimeoutMs(void);
+
+/**
+ * \brief  Get WDT mode.
+ *
+ * \return WDT mode
+ */
+WDTMode_TypeDef WDT_GetMode(void);
+
+/** End of WDT_Exported_Functions
+  * \}
+  */
+
+/** End of WDT
+  * \}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RTL_WDT_H */
diff --git a/bee/drivers/pwm/src/CMakeLists.txt b/bee/drivers/pwm/src/CMakeLists.txt
new file mode 100644
index 00000000..dd5e359a
--- /dev/null
+++ b/bee/drivers/pwm/src/CMakeLists.txt
@@ -0,0 +1,4 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+add_subdirectory(device)
diff --git a/bee/drivers/pwm/src/device/CMakeLists.txt b/bee/drivers/pwm/src/device/CMakeLists.txt
new file mode 100644
index 00000000..35d1b389
--- /dev/null
+++ b/bee/drivers/pwm/src/device/CMakeLists.txt
@@ -0,0 +1,9 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+if(CONFIG_REALTEK_BEE_COMMON_DRIVER)
+    file(GLOB BEE_DRIVER_COMMON_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/rtl_common/*.c")
+    zephyr_library_sources(${BEE_DRIVER_COMMON_SOURCES})
+endif()
+
+add_soc_series_subdir(rtl87x2j)
diff --git a/bee/drivers/pwm/src/device/rtl87x2j/rtl87x2j_lppwm.c b/bee/drivers/pwm/src/device/rtl87x2j/rtl87x2j_lppwm.c
new file mode 100644
index 00000000..7ac17232
--- /dev/null
+++ b/bee/drivers/pwm/src/device/rtl87x2j/rtl87x2j_lppwm.c
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *                           Header Files
+ *============================================================================*/
+
+/*============================================================================*
+ *                           Private Defines
+ *============================================================================*/
+
+/*============================================================================*
+ *                           Public Functions
+ *============================================================================*/
+
+
+
diff --git a/bee/drivers/pwm/src/device/rtl87x2j/rtl_lppwm_def.h b/bee/drivers/pwm/src/device/rtl87x2j/rtl_lppwm_def.h
new file mode 100644
index 00000000..963b3657
--- /dev/null
+++ b/bee/drivers/pwm/src/device/rtl87x2j/rtl_lppwm_def.h
@@ -0,0 +1,149 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef RTL_LPPWM_DEF_H
+#define RTL_LPPWM_DEF_H
+
+#include "utils/rtl_utils.h"
+#include "address_map.h"
+#include "aon_reg.h"
+
+#ifdef  __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/*============================================================================*
+ *                          LPPWM Defines
+ *============================================================================*/
+
+/*============================================================================*
+ *                          LPPWM Registers Memory Map
+ *============================================================================*/
+typedef struct
+{
+    __IO uint32_t LPPWM_CH0_CTL;                    /*!< 0x00 */
+    __IO uint32_t LPPWM_CH0_P0_H;                   /*!< 0x04 */
+    __IO uint32_t LPPWM_CH0_P0_L;                   /*!< 0x08 */
+    __I  uint32_t LPPWM_CH0_CURRENT;                /*!< 0x0C */
+    __I  uint32_t LPPWM_VERSION;                    /*!< 0x10 */
+    __IO uint32_t LPPWM_QACTIVE_MANUAL_CTRL;        /*!< 0x14 */
+} LPPWM_TypeDef;
+
+/*============================================================================*
+ *                          LPPWM Declaration
+ *============================================================================*/
+#define LPPWM_REG_BASE           (SYSON_BASE + AON_REG_LPPWM_CH0_CTL)
+#define LPPWM                    ((LPPWM_TypeDef *) LPPWM_REG_BASE)
+
+#define IS_LPPWM_PERIPH(PERIPH)  ((PERIPH) == LPPWM)
+
+/*============================================================================*
+ *                          LPPWM Private Types
+ *============================================================================*/
+
+/*============================================================================*
+ *                          LPPWM Registers and Field Descriptions
+ *============================================================================*/
+/* 0x00
+   0       R/W    lppwm_ch0_reg_rst_n         1'h0
+   1       R/W    lppwm_ch0_en                1'h0
+   2       R/W    lppwm_ch0_polarity          1'h0
+   31:3    R      rsvd                        29'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t lppwm_ch0_reg_rst_n: 1;
+        uint32_t lppwm_ch0_en: 1;
+        uint32_t lppwm_ch0_polarity: 1;
+        const uint32_t reserved_0: 29;
+    } b;
+} LPPWM_CH0_CTL_TypeDef;
+
+
+/* 0x04
+   15:0    R/W    lppwm_ch0_p0_h              16'h0
+   31:16   R      rsvd                        16'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t lppwm_ch0_p0_h: 16;
+        const uint32_t reserved_0: 16;
+    } b;
+} LPPWM_CH0_P0_H_TypeDef;
+
+
+/* 0x08
+   15:0    R/W    lppwm_ch0_p0_l              16'h0
+   31:16   R      rsvd                        16'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t lppwm_ch0_p0_l: 16;
+        const uint32_t reserved_0: 16;
+    } b;
+} LPPWM_CH0_P0_L_TypeDef;
+
+
+/* 0x0C
+   15:0    R      lppwm_ch0_current           16'h0
+   31:16   R      rsvd                        16'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t lppwm_ch0_current: 16;
+        const uint32_t reserved_0: 16;
+    } b;
+} LPPWM_CH0_CURRENT_TypeDef;
+
+
+/* 0x10
+   31:0    R      lppwm_version               32'h2305230A
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t lppwm_version: 32;
+    } b;
+} LPPWM_VERSION_TypeDef;
+
+
+/* 0x14
+   0       R/W    lppwm_clk_qactive_man_data  1'h0
+   1       R/W    lppwm_clk_qactive_man_enable 1'h0
+   31:2    R      rsvd                        30'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t lppwm_clk_qactive_man_data: 1;
+        uint32_t lppwm_clk_qactive_man_enable: 1;
+        const uint32_t reserved_0: 30;
+    } b;
+} LPPWM_QACTIVE_MANUAL_CTRL_TypeDef;
+
+
+
+#ifdef  __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* RTL_LPPWM_DEF_H */
diff --git a/bee/drivers/pwm/src/device/rtl_common/rtl_lppwm.c b/bee/drivers/pwm/src/device/rtl_common/rtl_lppwm.c
new file mode 100644
index 00000000..a66f1fa6
--- /dev/null
+++ b/bee/drivers/pwm/src/device/rtl_common/rtl_lppwm.c
@@ -0,0 +1,86 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *                           Header Files
+ *============================================================================*/
+#include "rtl_lppwm.h"
+
+/*============================================================================*
+ *                           Public Functions
+ *============================================================================*/
+
+void LPPWM_Init(LPPWM_TypeDef *LPPWMx, LPPWM_InitTypeDef *LPPWM_InitStruct)
+{
+    assert_param(IS_LPPWM_PERIPH(LPPWMx));
+
+    LPPWM_CH0_CTL_TypeDef lppwm_ctrl = {.d32 = LPPWMx->LPPWM_CH0_CTL};
+    lppwm_ctrl.b.lppwm_ch0_polarity = LPPWM_InitStruct->LPPWM_Polarity;
+    LPPWMx->LPPWM_CH0_CTL = lppwm_ctrl.d32;
+
+    LPPWMx->LPPWM_CH0_P0_H = LPPWM_InitStruct->LPPWM_PeriodHigh & 0xFFFF;
+    LPPWMx->LPPWM_CH0_P0_L = LPPWM_InitStruct->LPPWM_PeriodLow & 0xFFFF;
+
+    return;
+}
+
+void LPPWM_StructInit(LPPWM_InitTypeDef *LPPWM_InitStruct)
+{
+    assert_param(IS_LPPWM_PERIPH(LPPWMx));
+
+    /* High Polarity is selected as default polarity */
+    LPPWM_InitStruct->LPPWM_Polarity = LPPWM_POLARITY_NORMAL;
+
+    /* Set default high & low count  */
+    LPPWM_InitStruct->LPPWM_PeriodHigh = 0;
+    LPPWM_InitStruct->LPPWM_PeriodLow = 0;
+
+    return;
+}
+
+void LPPWM_Cmd(LPPWM_TypeDef *LPPWMx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_LPPWM_PERIPH(LPPWMx));
+
+    LPPWM_CH0_CTL_TypeDef lppwm_ctrl = {.d32 = LPPWMx->LPPWM_CH0_CTL};
+    lppwm_ctrl.b.lppwm_ch0_en = NewState;
+    LPPWMx->LPPWM_CH0_CTL = lppwm_ctrl.d32;
+
+    return;
+}
+
+void LPPWM_Reset(LPPWM_TypeDef *LPPWMx)
+{
+    /* Check the parameters */
+    assert_param(IS_LPPWM_PERIPH(LPPWMx));
+
+    LPPWM_CH0_CTL_TypeDef lppwm_ctrl = {.d32 = LPPWMx->LPPWM_CH0_CTL};
+    lppwm_ctrl.b.lppwm_ch0_reg_rst_n = 1;
+    LPPWMx->LPPWM_CH0_CTL = lppwm_ctrl.d32;
+
+    return;
+}
+
+void LPPWM_ChangePWMCount(LPPWM_TypeDef *LPPWMx, uint32_t period_high, uint32_t period_low)
+{
+    /* Check the parameters */
+    assert_param(IS_LPPWM_PERIPH(LPPWMx));
+
+    LPPWMx->LPPWM_CH0_P0_H = period_high & 0xFFFF;
+    LPPWMx->LPPWM_CH0_P0_L = period_low & 0xFFFF;
+}
+
+uint32_t LPPWM_GetCurrentValue(LPPWM_TypeDef *LPPWMx)
+{
+    /* Check the parameters */
+    assert_param(IS_LPPWM_PERIPH(LPPWMx));
+
+    return LPPWMx->LPPWM_CH0_CURRENT & 0xFFFF;
+}
+
+
+
diff --git a/bee/drivers/qdec/CMakeLists.txt b/bee/drivers/qdec/CMakeLists.txt
new file mode 100644
index 00000000..3e52feb4
--- /dev/null
+++ b/bee/drivers/qdec/CMakeLists.txt
@@ -0,0 +1,10 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+if(CONFIG_REALTEK_BEE_COMMON_DRIVER)
+    zephyr_include_directories(inc)
+endif()
+
+if(CONFIG_REALTEK_BEE_QDEC OR CONFIG_REALTEK_BEE_AON_QDEC OR CONFIG_REALTEK_BEE_LPQDEC)
+    add_subdirectory(src)
+endif()
diff --git a/bee/drivers/qdec/Kconfig b/bee/drivers/qdec/Kconfig
new file mode 100644
index 00000000..468a7d41
--- /dev/null
+++ b/bee/drivers/qdec/Kconfig
@@ -0,0 +1,20 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config REALTEK_BEE_QDEC
+	bool "Realtek Bee QDEC driver"
+	default n
+	help
+	  This option enables the QDEC driver for Realtek Bee.
+
+config REALTEK_BEE_AON_QDEC
+	bool "Realtek Bee AON QDEC driver"
+	default n
+	help
+	  This option enables the AON QDEC driver for Realtek Bee.
+
+config REALTEK_BEE_LPQDEC
+	bool "Realtek Bee LP QDEC driver"
+	default n
+	help
+	  This option enables the LP QDEC driver for Realtek Bee.
diff --git a/bee/drivers/qdec/inc/rtl_lpqdec.h b/bee/drivers/qdec/inc/rtl_lpqdec.h
new file mode 100644
index 00000000..5dc1b07e
--- /dev/null
+++ b/bee/drivers/qdec/inc/rtl_lpqdec.h
@@ -0,0 +1,652 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *               Define to prevent recursive inclusion
+ *============================================================================*/
+#ifndef RTL_LPQDEC_H
+#define RTL_LPQDEC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*============================================================================*
+ *                        Header Files
+ *============================================================================*/
+#include "utils/rtl_utils.h"
+#if defined (CONFIG_SOC_SERIES_RTL87X2J)
+#include "qdec/src/device/rtl87x2j/rtl_lpqdec_def.h"
+#elif defined (CONFIG_SOC_SERIES_RTL87X3J)
+#include "qdec/src/device/rtl87x3j/rtl_lpqdec_def.h"
+#endif
+
+/** \defgroup LPQDEC    LPQDEC
+  * \brief
+  * \{
+  */
+
+/*============================================================================*
+ *                         Constants
+ *============================================================================*/
+/** \defgroup LPQDEC_Exported_Constants LPQDEC Exported Constants
+  * \brief
+  * \{
+  */
+
+/**
+ * \defgroup    LPQDEC_Counter_Scale LPQDEC Counter Scale
+ * \{
+ * \ingroup     LPQDEC_Exported_Constants
+ */
+typedef enum
+{
+    LPQDEC_COUNTER_SCALE_1_PHASE = 0x00,
+    LPQDEC_COUNTER_SCALE_2_PHASE = 0x01,
+} LPQDECCounterScale_TypeDef;
+
+#define IS_LPQDEC_COUNTER_SCALE_PHASE(PHASE) ((PHASE) <= 0x01)
+
+/** End of LPQDEC_Counter_Scale
+  * \}
+  */
+
+/**
+ * \defgroup    LPQDEC_Phase LPQDEC Phase
+ * \{
+ * \ingroup     LPQDEC_Exported_Constants
+ */
+typedef enum
+{
+    LPQDEC_PHASE_MODE0 = 0x00, //phase 00
+    LPQDEC_PHASE_MODE1 = 0x01, //phase 01
+    LPQDEC_PHASE_MODE2 = 0x02, //phase 10
+    LPQDEC_PHASE_MODE3 = 0x03, //phase 11
+} LPQDECPhase_TypeDef;
+
+#define IS_LPQDEC_PHSAE(PHSAE) ((PHSAE) <= 0x03)
+
+/** End of LPQDEC_Phase
+  * \}
+  */
+
+/**
+ * \defgroup    LPQDEC_Axis_Direction LPQDEC Axis Direction
+ * \{
+ * \ingroup     LPQDEC_Exported_Constants
+ */
+typedef enum
+{
+    LPQDEC_AXIS_DIR_DOWN = 0x00,
+    LPQDEC_AXIS_DIR_UP = 0x01,
+} LPQDECAxisDir_TypeDef;
+
+#define IS_LPQDEC_AXIS_DIRECTION(DIRECTION) ((DIRECTION) <= 0x01)
+
+/** End of LPQDEC_Axis_Direction
+  * \}
+  */
+
+#if (LPQDEC_SUPPORT_LED_FUNCTION == 1)
+/**
+ * \defgroup    LPQDEC_LED_Polarity LPQDEC LED Polarity
+ * \{
+ * \ingroup     LPQDEC_Exported_Constants
+ */
+typedef enum
+{
+    LPQDEC_LED_POLARITY_LOW = 0x0,
+    LPQDEC_LED_POLARITY_HIGH = 0x1,
+} LPQDECLedPolarity_TypeDef;
+
+#define IS_LPQDEC_LED_POLARITY(POLARITY) ((POLARITY) <= 0x01)
+
+/** End of LPQDEC_LED_Polarity
+  * \}
+  */
+
+/**
+ * \defgroup    LPQDEC_LED_Period LPQDEC LED Period
+ * \{
+ * \ingroup     LPQDEC_Exported_Constants
+ */
+typedef enum
+{
+    LPQDEC_LED_PERIOD_0US      = 0x0,
+    LPQDEC_LED_PERIOD_31P25US  = 0x1,
+    LPQDEC_LED_PERIOD_62P5US   = 0x2,
+    LPQDEC_LED_PERIOD_93P75US  = 0x3,
+    LPQDEC_LED_PERIOD_125US    = 0x4,
+    LPQDEC_LED_PERIOD_156P25US = 0x5,
+    LPQDEC_LED_PERIOD_187P5US  = 0x6,
+    LPQDEC_LED_PERIOD_218P75US = 0x7,
+} LPQDECLedPeriod_TypeDef;
+
+#define IS_LPQDEC_LED_PERIOD(PERIOD) ((PERIOD) <= 0x7)
+
+/** End of LPQDEC_LED_Period
+  * \}
+  */
+#endif
+
+/**
+ * \defgroup    LPQDEC_Interrupts LPQDEC Interrupts
+ * \{
+ * \ingroup     LPQDEC_Exported_Constants
+ */
+#define LPQDEC_X_INT_NEW_DATA               BIT6
+#define LPQDEC_X_INT_ILLEGAL                BIT5
+
+#define IS_LPQDEC_INT_CONFIG(CONFIG)        (((CONFIG) == LPQDEC_X_INT_NEW_DATA) || \
+                                             ((CONFIG) == LPQDEC_X_INT_ILLEGAL))
+
+/** End of LPQDEC_Interrupts
+  * \}
+  */
+
+/**
+ * \defgroup    LPQDEC_Interrupts_Mask LPQDEC Interrupts Mask
+ * \{
+ * \ingroup     LPQDEC_Exported_Constants
+ */
+
+#define LPQDEC_X_INT_MASK_NEW_DATA          BIT8
+#define LPQDEC_X_INT_MASK_ILLEGAL           BIT7
+
+#define IS_LPQDEC_INT_MASK_CONFIG(CONFIG)   (((CONFIG) == LPQDEC_X_INT_MASK_NEW_DATA) || \
+                                             ((CONFIG) == LPQDEC_X_INT_MASK_ILLEGAL))
+
+/** End of LPQDEC_Interrupts_Mask
+  * \}
+  */
+
+/**
+ * \defgroup    LPQDEC_Interrupts_Clear LPQDEC Interrupts Clear
+ * \{
+ * \ingroup     LPQDEC_Exported_Constants
+ */
+#define LPQDEC_X_INT_CLEAR_ILLEGAL          BIT4
+#define LPQDEC_X_INT_CLEAR_UNDERFLOW        BIT3
+#define LPQDEC_X_INT_CLEAR_OVERFLOW         BIT2
+#define LPQDEC_X_INT_CLEAR_NEW_DATA         BIT1
+
+#define IS_LPQDEC_INT_CLEAR_CONFIG(CONFIG)  (((CONFIG) == LPQDEC_X_INT_CLEAR_ILLEGAL) || \
+                                             ((CONFIG) == LPQDEC_X_INT_CLEAR_UNDERFLOW) || \
+                                             ((CONFIG) == LPQDEC_X_INT_CLEAR_OVERFLOW) || \
+                                             ((CONFIG) == LPQDEC_X_INT_CLEAR_NEW_DATA))
+
+/** End of LPQDEC_Interrupts_Clear
+  * \}
+  */
+
+/**
+ * \defgroup    LPQDEC_Counter_Clear LPQDEC Counter Clear
+ * \{
+ * \ingroup     LPQDEC_Exported_Constants
+ */
+#define LPQDEC_X_CLEAR_ILLEGAL_COUNTER      BIT5
+#define LPQDEC_X_CLEAR_ACC_COUNTER          BIT0
+
+#define IS_LPQDEC_CNT_CLEAR_CONFIG(CONFIG)  (((CONFIG) == LPQDEC_X_CLEAR_ILLEGAL_COUNTER) || \
+                                             ((CONFIG) == LPQDEC_X_CLEAR_ACC_COUNTER))
+
+/** End of LPQDEC_Counter_Clear
+  * \}
+  */
+
+/**
+ * \defgroup    LPQDEC_Interrupts_Flag LPQDEC Interrupts Flag
+ * \{
+ * \ingroup     LPQDEC_Exported_Constants
+ */
+#define LPQDEC_X_INT_FLAG_NEW_DATA          BIT18
+#define LPQDEC_X_INT_FLAG_OVERFLOW          BIT16
+#define LPQDEC_X_INT_FLAG_UNDERFLOW         BIT17
+#define LPQDEC_X_INT_FLAG_ILLEGAL           BIT19
+
+#define IS_LPQDEC_INT_FLAG_CONFIG(CONFIG)   (((CONFIG) == LPQDEC_X_INT_FLAG_NEW_COUNT) || \
+                                             ((CONFIG) == LPQDEC_X_INT_FLAG_OVERFLOW) || \
+                                             ((CONFIG) == LPQDEC_X_INT_FLAG_UNDERFLOW) || \
+                                             ((CONFIG) == LPQDEC_X_INT_FLAG_ILLEGAL))
+
+/** End of LPQDEC_Interrupts_Flag
+  * \}
+  */
+
+/**
+ * \defgroup    LPQDEC_Axis LPQDEC Axis
+ * \{
+ * \ingroup     LPQDEC_Exported_Constants
+ */
+#define LPQDEC_AXIS_X                      (0)
+
+/** End of LPQDEC_Axis
+  * \}
+  */
+
+/** End of LPQDEC_Exported_Constants
+  * \}
+  */
+
+/*============================================================================*
+ *                         Types
+ *============================================================================*/
+/** \defgroup LPQDEC_Exported_Types LPQDEC Exported Types
+  * \brief
+  * \{
+  */
+
+/**
+ * \brief       LPQDEC init structure definition.
+ *
+ * \ingroup     LPQDEC_Exported_Types
+ */
+typedef struct
+{
+#if (LPQDEC_SUPPORT_CLK_SRC_DIV == 1)
+    uint16_t LPQDEC_ScanClockDiv;              /*!< Specifies DIV for Scan clock. */
+#endif
+
+    FunctionalState LPQDEC_AxisConfigX;        /*!< Specifies the axis X function.
+                                                    This parameter can be a value of ENABLE or DISABLE. */
+
+    FunctionalState LPQDEC_ManualLoadInitPhase;/*!< Specifies manual-load Initphase function.
+                                                    This parameter can be a value of ENABLE or DISABLE. */
+
+    LPQDECPhase_TypeDef LPQDEC_InitPhaseX;     /*!< Specifies the axis X function. */
+
+
+    FunctionalState LPQDEC_DebounceEnableX;    /*!< Specifies the axis X debounce.
+                                                    This parameter can be a value of ENABLE or DISABLE. */
+
+    uint16_t LPQDEC_DebounceCountX;            /*!< Specifies the axis X debounce time. */
+
+    LPQDECCounterScale_TypeDef LPQDEC_CounterScaleX; /*!< Specifies the axis X conter scale. */
+
+#if (LPQDEC_SUPPORT_LED_FUNCTION == 1)
+    FunctionalState LPQDEC_LedEn;              /*!< Specifies LED output status. */
+
+    LPQDECLedPolarity_TypeDef LPQDEC_LedPolarity; /*!< Specifies LED output pin polarity. */
+
+    LPQDECLedPeriod_TypeDef LPQDEC_LedPeriod;  /*!< Time period the LED is switched ON
+                                                    prior to sampling. When setting LEDPRE,
+                                                    make sure sample period > LEDPRE */
+#endif
+} LPQDEC_InitTypeDef;
+
+/** End of LPQDEC_Exported_Types
+  * \}
+  */
+
+/*============================================================================*
+ *                         Functions
+ *============================================================================*/
+/** \defgroup LPQDEC_Exported_Functions LPQDEC Exported Functions
+  * \brief
+  * \{
+  */
+
+/**
+ * \brief  Deinitializes the LPQDEC peripheral registers to their default reset values.
+ *
+ * \param  LPQDECx: Select the LPQDEC peripheral. \ref LPQDEC_Declaration.
+ *
+ * \return None
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_lpqdec_init(void)
+ * {
+ *     LPQDEC_DeInit(LPQDEC);
+ * }
+ * \endcode
+ */
+void LPQDEC_DeInit(LPQDEC_TypeDef *LPQDECx);
+
+/**
+ * \brief   Initializes the LPQDEC peripheral according to the specified
+  *         parameters in the LPQDEC_InitStruct.
+ *
+ * \param[in]  LPQDECx: Select the LPQDEC peripheral. \ref LPQDEC_Declaration.
+ * \param[in]  LPQDEC_InitStruct: pointer to an LPQDEC_InitStruct structure that
+  *            contains the configuration information for the specified LPQDEC peripheral.
+ *
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_lpqdec_init(void)
+ * {
+ *     LPQDEC_InitTypeDef LPQDEC_InitStruct;
+ *     LPQDEC_StructInit(&LPQDEC_InitStruct);
+ *     LPQDEC_InitStruct.LPQDEC_AxisConfigX       = ENABLE;
+ *     LPQDEC_InitStruct.LPQDEC_DebounceEnableX   = DISABLE;
+ *     LPQDEC_Init(LPQDEC, &LPQDEC_InitStruct);
+ *
+ *     LPQDEC_Cmd(LPQDEC, LPQDEC_AXIS_X, ENABLE);
+ * }
+ * \endcode
+ */
+void LPQDEC_Init(LPQDEC_TypeDef *LPQDECx, LPQDEC_InitTypeDef *LPQDEC_InitStruct);
+
+/**
+ * \brief  Fills each LPQDEC_InitStruct member with its default value.
+ *
+ * \param[in]  LPQDEC_InitStruct: pointer to an LPQDEC_InitStruct structure which will be initialized.
+ *
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_lpqdec_init(void)
+ * {
+ *
+ *     LPQDEC_InitTypeDef LPQDEC_InitStruct;
+ *     LPQDEC_StructInit(&LPQDEC_InitStruct);
+ *     LPQDEC_InitStruct.LPQDEC_AxisConfigX       = ENABLE;
+ *     LPQDEC_InitStruct.LPQDEC_DebounceEnableX   = DISABLE;
+ *     LPQDEC_Init(LPQDEC, &LPQDEC_InitStruct);
+ *
+ *     LPQDEC_Cmd(LPQDEC, LPQDEC_AXIS_X, ENABLE);
+ * }
+ * \endcode
+ */
+void LPQDEC_StructInit(LPQDEC_InitTypeDef *LPQDEC_InitStruct);
+
+/**
+ * \brief  Enable or disable LPQDEC Function.
+ *
+ * \param[in] LPQDECx: Select the LPQDEC peripheral. \ref LPQDEC_Declaration.
+ * \param[in] LPQDEC_AXIS: Specifies the LPQDEC axis.
+ *            This parameter can be one of the following values:
+ *            \arg LPQDEC_AXIS_X: The LPQDEC X axis.
+ * \param[in] NewState: New state of the selected LPQDEC axis.
+ *            This parameter can be one of the following values:
+  *           \arg ENABLE: Pause.
+  *           \arg DISABLE: Resume.
+ *
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void lpqdec_demo(void)
+ * {
+ *     LPQDEC_Cmd(LPQDEC, LPQDEC_AXIS_X, ENABLE);
+ * }
+ * \endcode
+ */
+void LPQDEC_Cmd(LPQDEC_TypeDef *LPQDECx, uint32_t LPQDEC_AXIS, FunctionalState NewState);
+
+/**
+ * \brief  Enables or disables the specified LPQDEC interrupts.
+ *
+ * \param[in] LPQDECx: Select the LPQDEC peripheral. \ref LPQDEC_Declaration.
+ * \param[in] LPQDEC_INT: Specifies the LPQDEC interrupts sources to be enabled or disabled.
+ *            This parameter parameter can be one of the following values:
+ *            \arg LPQDEC_X_INT_NEW_DATA: The counter interrupt for X axis.
+ *            \arg LPQDEC_X_INT_ILLEGAL: The illegal interrupt for X axis.
+ * \param[in] NewState: New state of the specified LPQDEC interrupt.
+ *            This parameter parameter can be: ENABLE or DISABLE.
+ *
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_lpqdec_init(void)
+ * {
+ *     LPQDEC_INTConfig(LPQDEC, LPQDEC_X_INT_NEW_DATA, ENABLE);
+ * }
+ * \endcode
+ */
+void LPQDEC_INTConfig(LPQDEC_TypeDef *LPQDECx, uint32_t LPQDEC_INT, FunctionalState NewState);
+
+/**
+ * \brief  Enables or disables mask the specified LPQDEC axis interrupts.
+ *
+ * \param[in] LPQDECx: Select the LPQDEC peripheral. \ref LPQDEC_Declaration.
+ * \param[in] LPQDEC_AXIS: Specifies the LPQDEC axis.
+ *            This parameter can be one or logical OR of the following values:
+ *            \arg LPQDEC_X_INT_MASK_NEW_DATA: The LPQDEC CNT interrupt mask.
+ *            \arg LPQDEC_X_INT_MASK_ILLEGAL: The LPQDEC illegal interrupt mask.
+ * \param[in] NewState: New state of the specified LPQDEC interrupts mask.
+ *            This parameter can be: ENABLE or DISABLE.
+ *
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void lpqdec_demo(void)
+ * {
+ *     LPQDEC_MaskINTConfig(LPQDEC, LPQDEC_X_INT_MASK_NEW_DATA, ENABLE);
+ * }
+ * \endcode
+ */
+void LPQDEC_MaskINTConfig(LPQDEC_TypeDef *LPQDECx, uint32_t LPQDEC_MASK, FunctionalState NewState);
+
+/**
+ * \brief  Enables or disables interrupt signal to CPU NVIC.
+ *
+ * \param[in]  LPQDECx: Select the LPQDEC peripheral. \ref LPQDEC_Declaration.
+ * \param[in]  NewState: New state of the specified LPQDEC interrupts mask.
+ *             This parameter can be: ENABLE or DISABLE.
+ *
+ * \return None
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void lpqdec_demo(void)
+ * {
+ *     LPQDEC_NVICCmd(LPQDEC, ENABLE);
+ * }
+ * \endcode
+ */
+void LPQDEC_NVICCmd(LPQDEC_TypeDef *LPQDECx, FunctionalState NewState);
+
+/**
+ * \brief  Enables or disables wakeup system.
+ *
+ * \param[in]  LPQDECx: Select the LPQDEC peripheral. \ref LPQDEC_Declaration.
+ * \param[in]  NewState: New state of the specified LPQDEC interrupts mask.
+ *             This parameter can be: ENABLE or DISABLE.
+ *
+ * \return None
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void lpqdec_demo(void)
+ * {
+ *     LPQDEC_WakeUpCmd(LPQDEC, ENABLE);
+ * }
+ * \endcode
+ */
+void LPQDEC_WakeUpCmd(LPQDEC_TypeDef *LPQDECx, FunctionalState NewState);
+
+/**
+ * \brief  Checks whether the specified LPQDEC flag is set or not..
+ *
+ * \param[in] LPQDECx: Select the LPQDEC peripheral. \ref LPQDEC_Declaration.
+ * \param[in] LPQDEC_FLAG: Specifies the flag to check.
+ *            This parameter can be one of the following values:
+ *            \arg LPQDEC_X_INT_FLAG_NEW_COUNT: Status of the counter interrupt for X axis.
+ *            \arg LPQDEC_X_INT_FLAG_ILLEGAL: Status of the illegal interrupt for X axis.
+ *            \arg LPQDEC_X_INT_FLAG_OVERFLOW: The overflow flag for x-axis accumulation counter.
+ *            \arg LPQDEC_X_INT_FLAG_UNDERFLOW: The underflow flag for x-axis accumulation counter.
+ *
+ * \return The New state of LPQDEC_FLAG(SET or RESET).
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void lpqdec_demo(void)
+ * {
+ *     FlagStatus flag_status = LPQDEC_GetFlagState(LPQDEC, LPQDEC_X_INT_FLAG_NEW_COUNT);
+ * }
+ * \endcode
+ */
+FlagStatus LPQDEC_GetFlagState(LPQDEC_TypeDef *LPQDECx, uint32_t LPQDEC_FLAG);
+
+/**
+ * \brief   Clear LPQDEC interrupt pending bit.
+ *
+ * \param[in] LPQDECx: Select the LPQDEC peripheral. \ref LPQDEC_Declaration.
+ * \param[in] LPQDEC_FLAG: Specifies the flag to clear.
+ *            This parameter parameter can be one of the following values:
+ *            \arg LPQDEC_X_INT_CLEAR_ILLEGAL: The illegal interrupt for X axis.
+ *            \arg LPQDEC_X_INT_CLEAR_UNDERFLOW: The underflow flag for x-axis accumulation counter.
+ *            \arg LPQDEC_X_INT_CLEAR_OVERFLOW: The overflow flag for x-axis accumulation counter.
+ *            \arg LPQDEC_X_INT_CLEAR_NEW_DATA: The counter interrupt for X axis.
+ *
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void lpqdec_demo(void)
+ * {
+ *     LPQDEC_ClearINTPendingBit(LPQDEC, LPQDEC_X_INT_CLEAR_NEW_DATA);
+ * }
+ * \endcode
+ */
+void LPQDEC_ClearINTPendingBit(LPQDEC_TypeDef *LPQDECx, uint32_t LPQDEC_CLR_INT);
+
+/**
+ * \brief   Clear LPQDEC counter.
+ *
+ * \param[in]  LPQDECx: Select the LPQDEC peripheral. \ref LPQDEC_Declaration.
+ * \param[in]  LPQDEC_CLEAR: Specifies the counter to clear.
+ *             This parameter parameter can be one of the following values:
+ *             \arg LPQDEC_X_CLEAR_ILLEGAL_COUNTER: The illegal counter for X axis.
+ *             \arg LPQDEC_X_CLEAR_ACC_COUNTER: The acc counter for X axis.
+ *
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void lpqdec_demo(void)
+ * {
+ *     LPQDEC_ClearCounter(LPQDEC, LPQDEC_X_INT_CLEAR_ILLEGAL_CNT);
+ * }
+ * \endcode
+ */
+void LPQDEC_ClearCounter(LPQDEC_TypeDef *LPQDECx, uint32_t LPQDEC_CLEAR);
+
+/**
+ * \brief  Get LPQDEC X-Axis direction.
+ *
+ * \param[in] LPQDECx: Select the LPQDEC peripheral. \ref LPQDEC_Declaration.
+ * \param[in] LPQDEC_AXIS: Specifies the LPQDEC axis.
+ *            This parameter parameter can be one of the following values:
+ *            \arg  LPQDEC_AXIS_X: The LPQDEC X axis.
+ *
+ * \return The direction of the axis. This parameter parameter can be one of the following values:
+ *         \retval LPQDEC_AXIS_DIR_UP: The axis is rolling up.
+ *         \retval LPQDEC_AXIS_DIR_DOWN: The axis is rolling down.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void lpqdec_demo(void)
+ * {
+ *     bool dir = LPQDEC_GetAxisDirection(LPQDEC, LPQDEC_AXIS_X);
+ * }
+ * \endcode
+ */
+bool LPQDEC_GetAxisDirection(LPQDEC_TypeDef *LPQDECx, uint32_t LPQDEC_AXIS);
+
+/**
+ * \brief  Get LPQDEC X-Axis count.
+ *
+ * \param[in] LPQDECx: Select the LPQDEC peripheral. \ref LPQDEC_Declaration.
+ * \param[in] LPQDEC_AXIS: Specifies the LPQDEC axis.
+ *            This parameter parameter can be one of the following values:
+ *            \arg LPQDEC_AXIS_X: The LPQDEC X axis.
+ *
+ * \return The count of the axis.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void lpqdec_demo(void)
+ * {
+ *     uint16_t counter = LPQDEC_GetAxisCount(LPQDEC, LPQDEC_AXIS_X);
+ * }
+ * \endcode
+ */
+uint16_t LPQDEC_GetAxisCount(LPQDEC_TypeDef *LPQDECx, uint32_t LPQDEC_AXIS);
+
+/**
+ * \brief  Pause or resume LPQDEC Axis x.
+ *
+ * \param[in] LPQDECx: Select the LPQDEC peripheral. \ref LPQDEC_Declaration.
+ * \param[in] LPQDEC_AXIS: Specifies the LPQDEC axis.
+ *            This parameter parameter can be one of the following values:
+ *            \arg LPQDEC_AXIS_X: The LPQDEC X axis.
+ * \param[in] NewState: New state of the specified LPQDEC Axis.
+ *            This parameter parameter can be one of the following values:
+ *            \arg ENABLE: Pause.
+ *            \arg DISABLE: Resume.
+ *
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void lpqdec_demo(void)
+ * {
+ *     LPQDEC_CounterPauseCmd(LPQDEC, LPQDEC_AXIS_X, ENABLE);
+ * }
+ * \endcode
+ */
+void LPQDEC_CounterPauseCmd(LPQDEC_TypeDef *LPQDECx, uint32_t LPQDEC_AXIS,
+                            FunctionalState NewState);
+
+/**
+ * \brief  Get current state of phase.
+ * \param[in] LPQDECx: Select the LPQDEC peripheral. \ref LPQDEC_Declaration.
+ *
+ * \return The current state of phase. \ref LPQDECPhase_TypeDef
+ *         \retval LPQDEC_PHASE_MODE0: Phase 00.
+ *         \retval LPQDEC_PHASE_MODE1: Phase 01.
+ *         \retval LPQDEC_PHASE_MODE2: Phase 10.
+ *         \retval LPQDEC_PHASE_MODE3: Phase 11.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void lpqdec_demo(void)
+ * {
+ *     LPQDECPhase_TypeDef phase = LPQDEC_GetPhaseState(LPQDEC);
+ * }
+ * \endcode
+  */
+LPQDECPhase_TypeDef LPQDEC_GetPhaseState(LPQDEC_TypeDef *LPQDECx);
+
+/** End of LPQDEC_Exported_Functions
+  * \}
+  */
+
+/** End of LPQDEC
+  * \}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RTL_LPQDEC_H */
+
+
+
+
diff --git a/bee/drivers/qdec/src/CMakeLists.txt b/bee/drivers/qdec/src/CMakeLists.txt
new file mode 100644
index 00000000..dd5e359a
--- /dev/null
+++ b/bee/drivers/qdec/src/CMakeLists.txt
@@ -0,0 +1,4 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+add_subdirectory(device)
diff --git a/bee/drivers/qdec/src/device/CMakeLists.txt b/bee/drivers/qdec/src/device/CMakeLists.txt
new file mode 100644
index 00000000..1f5eaa43
--- /dev/null
+++ b/bee/drivers/qdec/src/device/CMakeLists.txt
@@ -0,0 +1,8 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+add_subdirectory_ifdef(CONFIG_REALTEK_BEE_COMMON_DRIVER rtl_common)
+
+add_soc_series_subdir(rtl8752h)
+add_soc_series_subdir(rtl87x2g)
+add_soc_series_subdir(rtl87x2j)
diff --git a/bee/drivers/qdec/src/device/rtl8752h/rtl876x_qdec.c b/bee/drivers/qdec/src/device/rtl8752h/rtl876x_qdec.c
new file mode 100644
index 00000000..1e097738
--- /dev/null
+++ b/bee/drivers/qdec/src/device/rtl8752h/rtl876x_qdec.c
@@ -0,0 +1,410 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "rtl876x_rcc.h"
+#include "rtl876x_qdec.h"
+#include "app_section.h"
+
+/**
+  * @brief Initializes the Qdecoder peripheral according to the specified
+  *   parameters in the QDEC_InitStruct
+  * @param  QDECx: selected Qdecoder peripheral.
+  * @param  QDEC_InitStruct: pointer to a QDEC_InitStruct structure that
+  *     contains the configuration information for the specified Qdecoder peripheral
+  * @retval None
+  */
+void QDEC_Init(QDEC_TypeDef *QDECx, QDEC_InitTypeDef *QDEC_InitStruct)
+{
+    assert_param(IS_QDEC_PERIPH(QDECx));
+
+    QDECx->REG_DIV = (QDEC_InitStruct->scanClockDiv << 4) | (QDEC_InitStruct->debounceClockDiv);
+
+    /* QDEC configure */
+    if (QDEC_InitStruct->axisConfigX == ENABLE)
+    {
+        /* Clear REG_CR_X Register*/
+        QDECx->REG_CR_X &= ~((0xFF << 4) | BIT13 | BIT12 | (0x3));
+
+        /* Set Manual Initial Phase*/
+        if (QDEC_InitStruct->manualLoadInitPhase == ENABLE)
+        {
+            QDECx->REG_CR_X &= ~BIT31;
+            QDECx->REG_CR_X |= BIT2 | (QDEC_InitStruct->initPhaseX);
+            QDECx->REG_CR_X &= ~BIT2;
+
+        }
+        else
+        {
+            QDECx->REG_CR_X &= ~BIT2;
+        }
+        QDECx->REG_CR_X |= ((QDEC_InitStruct->debounceTimeX << 4) | (QDEC_InitStruct->counterScaleX << 13) |
+                            \
+                            (QDEC_InitStruct->debounceEnableX << 12));
+    }
+    if (QDEC_InitStruct->axisConfigY == ENABLE)
+    {
+        /* Clear REG_CR_Y Register*/
+        QDECx->REG_CR_Y &= ~((0xFF << 4) | BIT13 | BIT12 | (0x3));
+
+        /* Set Manual Initial Phase*/
+        if (QDEC_InitStruct->manualLoadInitPhase == ENABLE)
+        {
+            QDECx->REG_CR_Y &= ~BIT31;
+            QDECx->REG_CR_Y |= BIT2 | (QDEC_InitStruct->initPhaseY);
+            QDECx->REG_CR_Y &= ~BIT2;
+
+        }
+        else
+        {
+            QDECx->REG_CR_Y &= ~BIT2;
+        }
+        QDECx->REG_CR_Y |= ((QDEC_InitStruct->debounceTimeY << 4) | (QDEC_InitStruct->counterScaleY << 13) |
+                            \
+                            (QDEC_InitStruct->debounceEnableY << 12));
+    }
+    if (QDEC_InitStruct->axisConfigZ == ENABLE)
+    {
+        /* Clear REG_CR_Z Register*/
+        QDECx->REG_CR_Z &= ~((0xFF << 4) | BIT13 | BIT12 | (0x3));
+
+        /* Set Manual Initial Phase*/
+        if (QDEC_InitStruct->manualLoadInitPhase == ENABLE)
+        {
+            QDECx->REG_CR_Z &= ~BIT31;
+            QDECx->REG_CR_Z |= BIT2 | (QDEC_InitStruct->initPhaseZ);
+            QDECx->REG_CR_Z &= ~BIT2;
+
+        }
+        else
+        {
+            QDECx->REG_CR_Z &= ~BIT2;
+        }
+        QDECx->REG_CR_Z |= ((QDEC_InitStruct->debounceTimeZ << 4) | (QDEC_InitStruct->counterScaleZ << 13) |
+                            \
+                            (QDEC_InitStruct->debounceEnableZ << 12));
+    }
+    return;
+}
+
+/**
+  * @brief  Deinitializes the Qdecoder peripheral registers to their default reset values(turn off Qdecoder clock).
+  * @param  QDECx: selected Qdecoder peripheral.
+  * @retval None
+  */
+void QDEC_DeInit(QDEC_TypeDef *QDECx)
+{
+    RCC_PeriphClockCmd(APBPeriph_QDEC, APBPeriph_QDEC_CLOCK, DISABLE);
+}
+
+
+/**
+  * @brief  Fills each QDEC_InitStruct member with its default value.
+  * @param  QDEC_InitStruct: pointer to an QDEC_InitStruct structure which will be initialized.
+  * @retval None
+  */
+void QDEC_StructInit(QDEC_InitTypeDef *QDEC_InitStruct)
+{
+    QDEC_InitStruct->scanClockDiv      = 0x7CF;/*!< 20M/(scanClockDiv+1) = 10KHz */
+    QDEC_InitStruct->debounceClockDiv  = 0x4; /*!< 10KHz/(debounceClockDiv +1) = 2K */
+
+    QDEC_InitStruct->axisConfigX       = DISABLE;
+    QDEC_InitStruct->debounceTimeX     = 2 * 5; /*!< 5ms */
+    QDEC_InitStruct->counterScaleX     = CounterScale_1_Phase;
+    QDEC_InitStruct->debounceEnableX   = Debounce_Disable;
+    QDEC_InitStruct->initPhaseX        = phaseMode0;
+
+    QDEC_InitStruct->axisConfigY       = DISABLE;
+    QDEC_InitStruct->debounceTimeY     = 2 * 5; /*!< 5ms */
+    QDEC_InitStruct->counterScaleY     = CounterScale_1_Phase;
+    QDEC_InitStruct->debounceEnableY   = Debounce_Disable;
+    QDEC_InitStruct->initPhaseY        = phaseMode0;
+
+    QDEC_InitStruct->axisConfigZ       = DISABLE;
+    QDEC_InitStruct->debounceTimeZ     = 2 * 5; /*!< 5ms */
+    QDEC_InitStruct->counterScaleZ     = CounterScale_1_Phase;
+    QDEC_InitStruct->debounceEnableZ   = Debounce_Disable;
+    QDEC_InitStruct->initPhaseZ        = phaseMode0;
+
+    return;
+}
+
+
+/**
+  * @brief  Enables or disables the specified Qdecoder interrupts.
+  * @param  QDECx: selected Qdecoder peripheral.
+  * @param  QDEC_IT: specifies the QDECODER interrupts sources to be enabled or disabled.
+  *   This parameter can be one of the following values:
+  *     @arg QDEC_X_INT_NEW_DATA:
+  *     @arg QDEC_X_INT_ILLEAGE:
+  *     @arg QDEC_Y_INT_NEW_DATA:
+  *     @arg QDEC_Y_INT_ILLEAGE:
+  *     @arg QDEC_Z_INT_NEW_DATA:
+  *     @arg QDEC_Z_INT_ILLEAGE:
+  * @param  NewState: new state of the specified QDECODER interrupts.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void QDEC_INTConfig(QDEC_TypeDef *QDECx, uint32_t QDEC_IT, FunctionalState newState)
+{
+    /* Check the parameters */
+    assert_param(IS_QDEC_PERIPH(QDECx));
+    assert_param(IS_FUNCTIONAL_STATE(newState));
+    assert_param(IS_QDEC_INT_CONFIG(QDEC_IT));
+
+    if (newState == ENABLE)
+    {
+        /* Enable the selected QDECODER interrupts */
+        if (QDEC_IT & QDEC_X_INT_NEW_DATA)
+        {
+            QDECx->REG_CR_X |= BIT15;
+        }
+        if (QDEC_IT & QDEC_Y_INT_NEW_DATA)
+        {
+            QDECx->REG_CR_Y |= BIT15;
+        }
+        if (QDEC_IT & QDEC_Z_INT_NEW_DATA)
+        {
+            QDECx->REG_CR_Z |= BIT15;
+        }
+        if (QDEC_IT & QDEC_X_INT_ILLEGAL)
+        {
+            QDECx->REG_CR_X |= BIT14;
+        }
+        if (QDEC_IT & QDEC_Y_INT_ILLEGAL)
+        {
+            QDECx->REG_CR_Y |= BIT14;
+        }
+        if (QDEC_IT & QDEC_Z_INT_ILLEGAL)
+        {
+            QDECx->REG_CR_Z |= BIT14;
+        }
+    }
+    else
+    {
+        /* Disable the selected QDECODER interrupts */
+        if (QDEC_IT & QDEC_X_INT_NEW_DATA)
+        {
+            QDECx->REG_CR_X &= ~BIT15;
+        }
+        if (QDEC_IT & QDEC_Y_INT_NEW_DATA)
+        {
+            QDECx->REG_CR_Y &= ~BIT15;
+        }
+        if (QDEC_IT & QDEC_Z_INT_NEW_DATA)
+        {
+            QDECx->REG_CR_Z &= ~BIT15;
+        }
+        if (QDEC_IT & QDEC_X_INT_ILLEGAL)
+        {
+            QDECx->REG_CR_X &= ~BIT14;
+        }
+        if (QDEC_IT & QDEC_Y_INT_ILLEGAL)
+        {
+            QDECx->REG_CR_X &= ~BIT14;
+        }
+        if (QDEC_IT & QDEC_Z_INT_ILLEGAL)
+        {
+            QDECx->REG_CR_X &= ~BIT14;
+        }
+    }
+
+    return;
+}
+
+/**
+  * @brief  Checks whether the specified Qdecoder flag is set or not.
+  * @param  QDECx: selected Qdecoder peripheral.
+  * @param  QDEC_FLAG: specifies the flag to check.
+  *   This parameter can be one of the following values:
+  *     @arg QDEC_FLAG_ILLEGAL_STATUS_X:
+  *     @arg QDEC_FLAG_ILLEGAL_STATUS_Y:
+  *     @arg QDEC_FLAG_ILLEGAL_STATUS_Z:
+  *     @arg QDEC_FLAG_NEW_STATUS_X:
+  *     @arg QDEC_FLAG_NEW_STATUS_Y:
+  *     @arg QDEC_FLAG_NEW_STATUS_Z:
+  * @retval The new state of QDEC_FLAG (SET or RESET).
+  */
+FlagStatus QDEC_GetFlagState(QDEC_TypeDef *QDECx, uint32_t QDEC_FLAG)
+{
+    FlagStatus bitstatus = RESET;
+
+    /* Check the parameters */
+    assert_param(IS_QDEC_PERIPH(QDECx));
+    assert_param(IS_QDEC_CLR_INT_STATUS(QDEC_FLAG));
+
+    if (((QDEC_FLAG & 0x7) | (QDEC_FLAG & (0x7 << 12))))
+    {
+        if (QDECx->INT_SR & QDEC_FLAG)
+        {
+            bitstatus = SET;
+        }
+    }
+    else if (QDEC_FLAG == QDEC_FLAG_OVERFLOW_X)
+    {
+        if (QDECx->REG_SR_X & (BIT18))
+        {
+            bitstatus = SET;
+        }
+    }
+    else if (QDEC_FLAG == QDEC_FLAG_OVERFLOW_Y)
+    {
+        if (QDECx->REG_SR_Y & (BIT18))
+        {
+            bitstatus = SET;
+        }
+    }
+    else if (QDEC_FLAG == QDEC_FLAG_OVERFLOW_Z)
+    {
+        if (QDECx->REG_SR_Z & (BIT18))
+        {
+            bitstatus = SET;
+        }
+    }
+    else if (QDEC_FLAG == QDEC_FLAG_UNDERFLOW_X)
+    {
+        if (QDECx->REG_SR_X & (BIT19))
+        {
+            bitstatus = SET;
+        }
+    }
+    else if (QDEC_FLAG == QDEC_FLAG_UNDERFLOW_Y)
+    {
+        if (QDECx->REG_SR_Y & (BIT19))
+        {
+            bitstatus = SET;
+        }
+    }
+    else if (QDEC_FLAG == QDEC_FLAG_UNDERFLOW_Z)
+    {
+        if (QDECx->REG_SR_Z & (BIT19))
+        {
+            bitstatus = SET;
+        }
+    }
+
+    return bitstatus;
+}
+
+/**
+  * @brief  Enables or disables mask the specified Qdecoder axis interrupts.
+  * @param  QDECx: selected Qdecoder peripheral.
+  * @param  QDEC_AXIS: specifies the Qdecoder axis.
+  *   This parameter can be one or logical OR of the following values:
+  *     @arg QDEC_X_CT_INT_MASK: The qdecoder X axis.
+  *     @arg QDEC_X_ILLEAGE_INT_MASK: The qdecoder Y axis.
+  *     @arg QDEC_Y_CT_INT_MASK: The qdecoder Z axis.
+  *     @arg QDEC_Y_ILLEAGE_INT_MASK: The qdecoder X axis.
+  *     @arg QDEC_Z_CNT_INT_MASK: The qdecoder Y axis.
+  *     @arg QDEC_Z_ILLEAGE_INT_MASK: The qdecoder Z axis.
+  * @param  NewState: new state of the specified Qdecoder interrupts mask.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void QDEC_INTMask(QDEC_TypeDef *QDECx, uint32_t QDEC_AXIS, FunctionalState newState)
+{
+    /* Check the parameters */
+    assert_param(IS_QDEC_PERIPH(QDECx));
+    assert_param(IS_QDEC_INT_MASK_CONFIG(QDEC_AXIS));
+    assert_param(IS_FUNCTIONAL_STATE(newState));
+
+    if (newState == ENABLE)
+    {
+        /* mask the selected QDEC interrupts */
+        QDECx->INT_MASK |= (QDEC_AXIS);
+    }
+    else
+    {
+        /* unmask the selected QDEC interrupts */
+        QDEC->INT_MASK &= (~(QDEC_AXIS));
+    }
+
+    return;
+}
+
+/**
+  * @brief  Get Qdecoder Axis(x/y/z) direction.
+  * @param  QDECx: selected Qdecoder peripheral.
+  * @param  QDEC_AXIS: specifies the Qdecoder axis.
+  *   This parameter can be one of the following values:
+  *     @arg QDEC_AXIS_X: The qdecoder X axis.
+  *     @arg QDEC_AXIS_Y: The qdecoder Y axis.
+  *     @arg QDEC_AXIS_Z: The qdecoder Z axis.
+  * @param  newState
+  *   This parameter can be one of the following values:
+  *     @arg ENABLE: Pause.
+  *     @arg DISABLE: Resume.
+  * @retval The count of the axis.
+  */
+void QDEC_Cmd(QDEC_TypeDef *QDECx, uint32_t QDEC_AXIS,
+              FunctionalState newState)
+{
+    /* Check the parameters */
+    assert_param(IS_QDEC_PERIPH(QDECx));
+    assert_param(IS_QDEC_AXIS_DIR(QDEC_AXIS));
+
+    if (newState == ENABLE)
+    {
+        *((volatile uint32_t *)(&QDECx->REG_CR_X) + QDEC_AXIS / 2) |= BIT31;
+    }
+    else
+    {
+        *((volatile uint32_t *)(&QDECx->REG_CR_X) + QDEC_AXIS / 2) &= ~(BIT31);
+    }
+}
+
+/**
+  * \brief  Store QDEC register values when system enter DLPS.
+  * \param  PeriReg: Specifies to select the QDEC peripheral.
+  * \param  StoreBuf: Store buffer to store QDEC register data.
+  * \return None.
+  */
+DATA_RAM_FUNCTION
+void QDEC_DLPSEnter(void *PeriReg, void *StoreBuf)
+{
+    QDECStoreReg_TypeDef *store_buf = (QDECStoreReg_TypeDef *)StoreBuf;
+
+    /*Open 20M clock source*/
+    SYSBLKCTRL->u_20C.PERION_REG_SYS_CLK_SEL_2 |= BIT26;
+    SYSBLKCTRL->u_20C.PERION_REG_SYS_CLK_SEL_2 |= BIT27;
+
+    RCC_PeriphClockCmd(APBPeriph_QDEC, APBPeriph_QDEC_CLOCK, ENABLE);
+
+    store_buf->qdec_reg[0] = QDEC->REG_DIV;
+    store_buf->qdec_reg[1] = QDEC->REG_CR_X;
+    store_buf->qdec_reg[2] = QDEC->REG_CR_Y;
+    store_buf->qdec_reg[3] = QDEC->REG_CR_Z;
+    store_buf->qdec_reg[4] = QDEC->INT_MASK;
+
+    return;
+}
+
+/**
+  * \brief  Restore QDEC register values when system exit DLPS.
+  * \param  PeriReg: Specifies to select the QDEC peripheral.
+  * \param  StoreBuf: Restore buffer to restore QDEC register data.
+  * \return None.
+  */
+DATA_RAM_FUNCTION
+void QDEC_DLPSExit(void *PeriReg, void *StoreBuf)
+{
+    QDECStoreReg_TypeDef *store_buf = (QDECStoreReg_TypeDef *)StoreBuf;
+
+    /*Open 20M clock source*/
+    SYSBLKCTRL->u_20C.PERION_REG_SYS_CLK_SEL_2 |= BIT26;
+    SYSBLKCTRL->u_20C.PERION_REG_SYS_CLK_SEL_2 |= BIT27;
+
+    RCC_PeriphClockCmd(APBPeriph_QDEC, APBPeriph_QDEC_CLOCK, ENABLE);
+
+    //clear flags
+    QDEC->REG_DIV  = store_buf->qdec_reg[0];
+    QDEC->REG_CR_X = store_buf->qdec_reg[1];
+    QDEC->REG_CR_Y = store_buf->qdec_reg[2];
+    QDEC->REG_CR_Z = store_buf->qdec_reg[3];
+    QDEC->INT_MASK = store_buf->qdec_reg[4];
+
+    return;
+}
+
diff --git a/bee/drivers/qdec/src/device/rtl8752h/rtl876x_qdec.h b/bee/drivers/qdec/src/device/rtl8752h/rtl876x_qdec.h
new file mode 100644
index 00000000..35068932
--- /dev/null
+++ b/bee/drivers/qdec/src/device/rtl8752h/rtl876x_qdec.h
@@ -0,0 +1,606 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _RTL876X_QDEC_H_
+#define _RTL876X_QDEC_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/**
+ * \addtogroup  IO          Peripheral Drivers
+ * \defgroup    QDEC        QDEC
+ *
+ * \brief       Manage the QDEC peripheral functions.
+ *
+ * \ingroup     IO
+ */
+
+/*============================================================================*
+ *                         Includes
+ *============================================================================*/
+#include "rtl876x.h"
+
+/*============================================================================*
+ *                         Types
+ *============================================================================*/
+/**
+ * \defgroup    QDEC_Exported_Types QDEC Exported Types
+ * \{
+ * \ingroup     QDEC
+ */
+
+/**
+ * \brief       Qdecoder initialize parameters.
+ *
+ * \ingroup     QDEC_Exported_Types
+ */
+typedef struct
+{
+    uint16_t scanClockDiv;              /*!< This parameter is used to set debounce time. */
+    uint16_t debounceClockDiv;          /*!< This parameter is used to set debounce time. */
+    uint8_t axisConfigX;                /*!< Specify the axis X function.
+                                             This parameter can be a value of ENABLE or DISABLE. */
+    uint8_t axisConfigY;                /*!< Specify the axis Y function.
+                                             This parameter can be a value of ENABLE or DISABLE. */
+    uint8_t axisConfigZ;                /*!< Specify the axis Z function.
+                                             This parameter can be a value of ENABLE or DISABLE. */
+    uint8_t manualLoadInitPhase;        /*!< Specify manual-load Initphase function.
+                                             This parameter can be a value of ENABLE or DISABLE. */
+    uint16_t counterScaleX;             /*!< Specify the axis X counter scale.
+                                             This parameter can be a value of \ref QDEC_Axis_Counter_Scale. */
+    uint16_t debounceEnableX;           /*!< Specify the axis X debounce.
+                                             This parameter can be a value of \ref QDEC_Debounce. */
+    uint16_t debounceTimeX;             /*!< Specify the axis X debounce time. */
+    uint16_t initPhaseX;                /*!< Specify the axis X function.
+                                             This parameter can be a value of \ref QDEC_Init_Phase. */
+    uint16_t counterScaleY;             /*!< Specify the axis Y counter scale.
+                                             This parameter can be a value of \ref QDEC_Axis_Counter_Scale. */
+    uint16_t debounceEnableY;           /*!< Specify the axis Y debounce.
+                                             This parameter can be a value of \ref QDEC_Debounce. */
+    uint16_t debounceTimeY;             /*!< Specify the axis Y debounce time. */
+    uint16_t initPhaseY;                /*!< Specify the axis Y function.
+                                             This parameter can be a value of \ref QDEC_Init_Phase. */
+    uint16_t counterScaleZ;             /*!< Specify the axis Z counter scale.
+                                             This parameter can be a value of \ref QDEC_Axis_Counter_Scale. */
+    uint16_t debounceEnableZ;           /*!< Specify the axis Z debounce.
+                                             This parameter can be a value of \ref QDEC_Debounce. */
+    uint16_t debounceTimeZ;             /*!< Specify the axis Z debounce time. */
+    uint16_t initPhaseZ;                /*!< Specify the axis Z function.
+                                             This parameter can be a value of \ref QDEC_Init_Phase. */
+} QDEC_InitTypeDef;
+
+/** End of QDEC_Exported_Types
+  * \}
+  */
+
+/*============================================================================*
+ *                         Constants
+ *============================================================================*/
+/**
+ * \defgroup    QDEC_Exported_Constants     QDEC Exported Constants
+ *
+ * \ingroup     QDEC
+ */
+
+#define IS_QDEC_PERIPH(PERIPH) ((PERIPH) == QDEC)
+
+/**
+ * \defgroup    QDEC_Interrupts_Definition  QDEC Interrupts Definition
+ * \{
+ * \ingroup     QDEC_Exported_Constants
+ */
+#define QDEC_X_INT_NEW_DATA                                   BIT(0) //get new data and state change
+#define QDEC_X_INT_ILLEGAL                                    BIT(1) //illegal
+#define QDEC_Y_INT_NEW_DATA                                   BIT(2) //get new data and state change
+#define QDEC_Y_INT_ILLEGAL                                    BIT(3) //illegal
+#define QDEC_Z_INT_NEW_DATA                                   BIT(4) //get new data and state change
+#define QDEC_Z_INT_ILLEGAL                                    BIT(5) //illegal
+
+#define IS_QDEC_INT_CONFIG(CONFIG) (((CONFIG) == QDEC_X_INT_NEW_DATA) || ((CONFIG) == QDEC_X_INT_ILLEGAL)\
+                                    || ((CONFIG) == QDEC_Y_INT_NEW_DATA) || ((CONFIG) == QDEC_Y_INT_ILLEGAL)\
+                                    || ((CONFIG) == QDEC_Z_INT_NEW_DATA) || ((CONFIG) == QDEC_Z_INT_ILLEGAL))
+/** \} */
+
+/**
+ * \defgroup    QDEC_Interrupts_Mask    QDEC Interrupts Mask
+ * \{
+ * \ingroup     QDEC_Exported_Constants
+ */
+#define QDEC_X_CT_INT_MASK                                   BIT(0) //get new data and state change
+#define QDEC_X_ILLEGAL_INT_MASK                              BIT(4) //illegal
+#define QDEC_Y_CT_INT_MASK                                   BIT(1) //get new data and state change
+#define QDEC_Y_ILLEGAL_INT_MASK                              BIT(5) //illegal
+#define QDEC_Z_CT_INT_MASK                                   BIT(2) //get new data and state change
+#define QDEC_Z_ILLEGAL_INT_MASK                              BIT(6) //illegal
+
+#define IS_QDEC_INT_MASK_CONFIG(CONFIG) (((CONFIG) == QDEC_X_CT_INT_MASK) || ((CONFIG) == QDEC_X_ILLEGAL_INT_MASK)\
+                                         || ((CONFIG) == QDEC_Y_CT_INT_MASK) || ((CONFIG) == QDEC_Y_ILLEGAL_INT_MASK)\
+                                         || ((CONFIG) == QDEC_Z_CT_INT_MASK) || ((CONFIG) == QDEC_Z_ILLEGAL_INT_MASK))
+/** \} */
+
+/**
+ * \defgroup    QDEC_Axis_Counter_Scale     QDEC Axis Counter Scale
+ * \{
+ * \ingroup     QDEC_Exported_Constants
+ */
+#define CounterScale_2_Phase                      true
+#define CounterScale_1_Phase                      false
+/** \} */
+
+/**
+ * \defgroup    QDEC_Debounce QDEC Debounce
+ * \{
+ * \ingroup     QDEC_Exported_Constants
+ */
+#define Debounce_Enable                        true
+#define Debounce_Disable                       false
+/** \} */
+
+/**
+ * \defgroup    QDEC_Manual_Phase   QDEC Manual Phase
+ * \{
+ * \ingroup     QDEC_Exported_Constants
+ */
+
+#define manualPhaseEnable                        true
+#define manualPhaseDisable                       false
+/** \} */
+
+/**
+ * \defgroup    QDEC_Init_Phase     QDEC Init Phase
+ * \{
+ * \ingroup     QDEC_Exported_Constants
+ */
+
+#define phaseMode0                        0       //phase 00
+#define phaseMode1                        1       //phase 01
+#define phaseMode2                        2       //phase 10
+#define phaseMode3                        3       //phase 11
+/** \} */
+
+/**
+ * \defgroup    QDEC_Clr_Flag   QDEC Clr Flag
+ * \{
+ * \ingroup     QDEC_Exported_Constants
+ */
+#define QDEC_CLR_ILLEGAL_CT_X                            ((uint32_t)(1 << 20))
+#define QDEC_CLR_ILLEGAL_CT_Y                            ((uint32_t)(1 << 21))
+#define QDEC_CLR_ILLEGAL_CT_Z                            ((uint32_t)(1 << 22))
+
+#define QDEC_CLR_ACC_CT_X                                ((uint32_t)(1 << 16))
+#define QDEC_CLR_ACC_CT_Y                                ((uint32_t)(1 << 17))
+#define QDEC_CLR_ACC_CT_Z                                ((uint32_t)(1 << 18))
+
+#define QDEC_CLR_ILLEGAL_INT_X                           ((uint32_t)(1 << 12))
+#define QDEC_CLR_ILLEGAL_INT_Y                           ((uint32_t)(1 << 13))
+#define QDEC_CLR_ILLEGAL_INT_Z                           ((uint32_t)(1 << 14))
+
+#define QDEC_CLR_UNDERFLOW_X                             ((uint32_t)(1 << 8))
+#define QDEC_CLR_UNDERFLOW_Y                             ((uint32_t)(1 << 9))
+#define QDEC_CLR_UNDERFLOW_Z                             ((uint32_t)(1 << 10))
+
+#define QDEC_CLR_OVERFLOW_X                              ((uint32_t)(1 << 4))
+#define QDEC_CLR_OVERFLOW_Y                              ((uint32_t)(1 << 5))
+#define QDEC_CLR_OVERFLOW_Z                              ((uint32_t)(1 << 6))
+
+#define QDEC_CLR_NEW_CT_X                                ((uint32_t)(1 << 0))
+#define QDEC_CLR_NEW_CT_Y                                ((uint32_t)(1 << 1))
+#define QDEC_CLR_NEW_CT_Z                                ((uint32_t)(1 << 2))
+
+#define IS_QDEC_INT_CLR_CONFIG(CONFIG) (((CONFIG) == QDEC_CLR_ACC_CT_X) || ((CONFIG) == QDEC_CLR_ACC_CT_Y)\
+                                        || ((CONFIG) == QDEC_CLR_ACC_CT_Z) || ((CONFIG) == QDEC_CLR_ILLEGAL_INT_Y)\
+                                        || ((CONFIG) == QDEC_CLR_ILLEGAL_INT_Z) || ((CONFIG) == QDEC_CLR_UNDERFLOW_X)\
+                                        || ((CONFIG) == QDEC_CLR_UNDERFLOW_Y) || ((CONFIG) == QDEC_CLR_UNDERFLOW_Z)\
+                                        || ((CONFIG) == QDEC_CLR_OVERFLOW_X) || ((CONFIG) == QDEC_CLR_OVERFLOW_Y)\
+                                        || ((CONFIG) == QDEC_CLR_OVERFLOW_Z) || ((CONFIG) == QDEC_CLR_NEW_CT_X)\
+                                        || ((CONFIG) == QDEC_CLR_NEW_CT_Y) || ((CONFIG) == QDEC_CLR_NEW_CT_Z))
+/** \} */
+
+/**
+ * \defgroup    QDEC_Flag QDEC Flag
+ * \{
+ * \ingroup     QDEC_Exported_Constants
+ */
+
+#define QDEC_FLAG_NEW_CT_STATUS_X                             ((uint32_t)(1 << 0))
+#define QDEC_FLAG_NEW_CT_STATUS_Y                             ((uint32_t)(1 << 1))
+#define QDEC_FLAG_NEW_CT_STATUS_Z                             ((uint32_t)(1 << 2))
+#define QDEC_FLAG_OVERFLOW_X                                  ((uint32_t)(1 << 3))
+#define QDEC_FLAG_OVERFLOW_Y                                  ((uint32_t)(1 << 4))
+#define QDEC_FLAG_OVERFLOW_Z                                  ((uint32_t)(1 << 5))
+#define QDEC_FLAG_UNDERFLOW_X                                 ((uint32_t)(1 << 6))
+#define QDEC_FLAG_UNDERFLOW_Y                                 ((uint32_t)(1 << 7))
+#define QDEC_FLAG_UNDERFLOW_Z                                 ((uint32_t)(1 << 8))
+#define QDEC_FLAG_AUTO_STATUS_X                               ((uint32_t)(1 << 9))
+#define QDEC_FLAG_AUTO_STATUS_Y                               ((uint32_t)(1 << 10))
+#define QDEC_FLAG_AUTO_STATUS_Z                               ((uint32_t)(1 << 11))
+#define QDEC_FLAG_ILLEGAL_STATUS_X                            ((uint32_t)(1 << 12))
+#define QDEC_FLAG_ILLEGAL_STATUS_Y                            ((uint32_t)(1 << 13))
+#define QDEC_FLAG_ILLEGAL_STATUS_Z                            ((uint32_t)(1 << 14))
+
+#define IS_QDEC_CLR_INT_STATUS(INT) (((INT) == QDEC_FLAG_ILLEGAL_STATUS_X) || ((INT) == QDEC_FLAG_ILLEGAL_STATUS_Y)\
+                                     || ((INT) == QDEC_FLAG_ILLEGAL_STATUS_Z) || ((INT) == QDEC_FLAG_NEW_CT_STATUS_X)\
+                                     || ((INT) == QDEC_FLAG_NEW_CT_STATUS_Y) || ((INT) == QDEC_FLAG_NEW_CT_STATUS_Z)\
+                                     || ((INT) == QDEC_FLAG_OVERFLOW_X) || ((INT) == QDEC_FLAG_OVERFLOW_Y)\
+                                     || ((INT) == QDEC_FLAG_OVERFLOW_Z) || ((INT) == QDEC_FLAG_UNDERFLOW_X)\
+                                     || ((INT) == QDEC_FLAG_UNDERFLOW_Y) || ((INT) == QDEC_FLAG_UNDERFLOW_Z)\
+                                     || ((INT) == QDEC_FLAG_AUTO_STATUS_X) || ((INT) == QDEC_FLAG_AUTO_STATUS_Y)\
+                                     || ((INT) == QDEC_FLAG_AUTO_STATUS_Z))
+/** \} */
+
+/**
+ * \defgroup    QDEC_Axis   QDEC Axis
+ * \{
+ * \ingroup     QDEC_Exported_Constants
+ */
+
+#define QDEC_AXIS_X                                     ((uint32_t)(1 << 0))
+#define QDEC_AXIS_Y                                     ((uint32_t)(1 << 2))
+#define QDEC_AXIS_Z                                     ((uint32_t)(1 << 3))
+/** \} */
+
+/**
+ * \defgroup   QDEC_Axis_Direction     QDEC Axis Direction
+ * \{
+ * \ingroup    QDEC_Exported_Constants
+ */
+
+#define QDEC_AXIS_DIR_UP                                 ((uint16_t)0x01)
+#define QDEC_AXIS_DIR_DOWN                               ((uint16_t)0x00)
+
+#define IS_QDEC_AXIS_DIR(QDEC_AXIS)     ((QDEC_AXIS == QDEC_AXIS_DIR_UP) || (QDEC_AXIS == QDEC_AXIS_DIR_DOWN))
+/** \} */
+
+/** End of QDEC_Exported_Constants
+  * \}
+  */
+
+/*============================================================================*
+ *                         Functions
+ *============================================================================*/
+/**
+ * \defgroup    QDEC_Exported_Functions QDEC Exported Functions
+ * \{
+ * \ingroup     QDEC
+ */
+
+/**
+ * \brief   Deinitialize the QDEC peripheral registers to their default reset values (turn off QDEC clock).
+ * \param[in] QDECx: Selected QDEC peripheral.
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_qdec_init(void)
+ * {
+ *     QDEC_DeInit();
+ * }
+ * \endcode
+ */
+void QDEC_DeInit(QDEC_TypeDef *QDECx);
+
+/**
+ * \brief   Initialize the QDEC peripheral according to the specified
+ *          parameters in the QDEC_InitStruct.
+ * \param[in]  QDECx: Selected QDEC peripheral.
+ * \param[in]  QDEC_InitStruct: Pointer to a QDEC_InitStruct structure that
+ *                              contains the configuration information for the specified QDEC peripheral.
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_qdec_init(void)
+ * {
+ *     QDEC_DeInit(QDEC);
+ *     RCC_PeriphClockCmd(APBPeriph_QDEC, APBPeriph_QDEC_CLOCK, ENABLE);
+ *
+ *     QDEC_InitTypeDef QDEC_InitStruct;
+ *     QDEC_StructInit(&QDEC_InitStruct);
+ *     QDEC_InitStruct.axisConfigY       = ENABLE;
+ *     QDEC_InitStruct.debounceEnableY   = Debounce_Enable;
+ *     QDEC_Init(QDEC, &QDEC_InitStruct);
+ *
+ *     QDEC_Cmd(QDEC, QDEC_AXIS_Y, ENABLE);
+ * }
+ * \endcode
+ */
+void QDEC_Init(QDEC_TypeDef *QDECx, QDEC_InitTypeDef *QDEC_InitStruct);
+
+/**
+ * \brief  Fill each QDEC_InitStruct member with its default value.
+ * \param[in]  QDEC_InitStruct: Pointer to a QDEC_InitStruct structure which will be initialized.
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_qdec_init(void)
+ * {
+ *     QDEC_DeInit(QDEC);
+ *     RCC_PeriphClockCmd(APBPeriph_QDEC, APBPeriph_QDEC_CLOCK, ENABLE);
+ *
+ *     QDEC_InitTypeDef QDEC_InitStruct;
+ *     QDEC_StructInit(&QDEC_InitStruct);
+ *     QDEC_InitStruct.axisConfigY       = ENABLE;
+ *     QDEC_InitStruct.debounceEnableY   = Debounce_Enable;
+ *     QDEC_Init(QDEC, &QDEC_InitStruct);
+ *
+ *     QDEC_Cmd(QDEC, QDEC_AXIS_Y, ENABLE);
+ * }
+ * \endcode
+ */
+void QDEC_StructInit(QDEC_InitTypeDef *QDEC_InitStruct);
+
+/**
+ * \brief  Enable or disable the specified QDEC interrupt source.
+ * \param[in]  QDECx: Selected QDEC peripheral.
+ * \param[in]  QDEC_IT: Specify the QDEC interrupt sources to be enabled or disabled.
+ *      This parameter can be one of the following values, which refer to \ref QDEC_Interrupts_Definition.
+ *      \arg  QDEC_X_INT_NEW_DATA: The counter interrupt for X axis.
+ *      \arg  QDEC_X_INT_ILLEGAL: The illegal interrupt for X axis.
+ *      \arg  QDEC_Y_INT_NEW_DATA: The counter interrupt for Y axis.
+ *      \arg  QDEC_Y_INT_ILLEGAL: The illegal interrupt for Y axis.
+ *      \arg  QDEC_Z_INT_NEW_DATA: The counter interrupt for Z axis.
+ *      \arg  QDEC_Z_INT_ILLEGAL: The illegal interrupt for Z axis.
+ * \param[in]  newState: New state of the specified QDEC interrupt.
+ *      This parameter can be: ENABLE or DISABLE.
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_qdec_init(void)
+ * {
+ *     QDEC_INTConfig(QDEC, QDEC_Y_INT_NEW_DATA, ENABLE);
+ * }
+ * \endcode
+ */
+void QDEC_INTConfig(QDEC_TypeDef *QDECx, uint32_t QDEC_IT, FunctionalState newState);
+
+/**
+ * \brief  Check whether the specified QDEC flag is set.
+ * \param[in]  QDECx: Selected QDEC peripheral.
+ * \param[in]  QDEC_FLAG: Specify the flag to check.
+ *      This parameter can be one of the following values, which refer to \ref QDEC_Flag.
+ *      \arg QDEC_FLAG_NEW_CT_STATUS_X: Status of the counter interrupt for X axis.
+ *      \arg QDEC_FLAG_NEW_CT_STATUS_Y: Status of the counter interrupt for Y axis.
+ *      \arg QDEC_FLAG_NEW_CT_STATUS_Z: Status of the counter interrupt for Z axis.
+ *      \arg QDEC_FLAG_ILLEGAL_STATUS_X: Status of the illegal interrupt for X axis.
+ *      \arg QDEC_FLAG_ILLEGAL_STATUS_Y: Status of the illegal interrupt for Y axis.
+ *      \arg QDEC_FLAG_ILLEGAL_STATUS_Z: Status of the illegal interrupt for Z axis.
+ *      \arg QDEC_FLAG_OVERFLOW_X: The overflow flag for x-axis accumulation counter.
+ *      \arg QDEC_FLAG_OVERFLOW_Y: The overflow flag for y-axis accumulation counter.
+ *      \arg QDEC_FLAG_OVERFLOW_Z: The overflow flag for z-axis accumulation counter.
+ *      \arg QDEC_FLAG_UNDERFLOW_X: The underflow flag for x-axis accumulation counter.
+ *      \arg QDEC_FLAG_UNDERFLOW_Y: The underflow flag for y-axis accumulation counter.
+ *      \arg QDEC_FLAG_UNDERFLOW_Z: The underflow flag for z-axis accumulation counter.
+ * \return The new state of QDEC_FLAG (SET or RESET).
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void qdec_demo(void)
+ * {
+ *     FlagStatus flag_status = QDEC_GetFlagState(QDEC, QDEC_Y_INT_NEW_DATA, ENABLE);
+ * }
+ * \endcode
+ */
+FlagStatus QDEC_GetFlagState(QDEC_TypeDef *QDECx, uint32_t QDEC_FLAG);
+
+/**
+ * \brief  Enable or disable mask the specified QDEC axis interrupts.
+ * \param[in]  QDECx: Selected QDEC peripheral.
+ * \param[in]  QDEC_AXIS: Specify the QDEC axis.
+ *      This parameter can be one or logical OR of the following values, which refer to \ref QDEC_Interrupts_Mask.
+ *      \arg  QDEC_X_CT_INT_MASK: The x-axis counter interrupt mask.
+ *      \arg  QDEC_X_ILLEGAL_INT_MASK: The x-axis illegal interrupt mask.
+ *      \arg  QDEC_Y_CT_INT_MASK: The y-axis counter interrupt mask.
+ *      \arg  QDEC_Y_ILLEGAL_INT_MASK: The y-axis illegal interrupt mask.
+ *      \arg  QDEC_Z_CNT_INT_MASK: The z-axis counter interrupt mask.
+ *      \arg  QDEC_Z_ILLEGAL_INT_MASK: The z-axis illegal interrupt mask.
+ * \param[in]  newState: New state of the specified QDEC interrupts mask.
+ *      This parameter can be: ENABLE or DISABLE.
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void qdec_demo(void)
+ * {
+ *
+ *     QDEC_INTMask(QDEC, QDEC_X_CT_INT_MASK, ENABLE);
+ *
+ * }
+ * \endcode
+ */
+void QDEC_INTMask(QDEC_TypeDef *QDECx, uint32_t QDEC_AXIS, FunctionalState newState);
+
+/**
+ * \brief  Enable or disable the selected QDEC axis(x/y/z).
+ * \param[in]  QDECx: Selected QDEC peripheral.
+ * \param[in]  QDEC_AXIS: Specify the QDEC axis.
+ *      This parameter can be one of the following values, which refer to \ref QDEC_Axis.
+ *      \arg  QDEC_AXIS_X: The qdecoder X axis.
+ *      \arg  QDEC_AXIS_Y: The qdecoder Y axis.
+ *      \arg  QDEC_AXIS_Z: The qdecoder Z axis.
+ * \param[in]  newState: New state of the selected QDEC axis.
+ *      This parameter can be : ENABLE or DISABLE.
+ * \return The count of the axis.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void qdec_demo(void)
+ * {
+ *     QDEC_Cmd(QDEC, QDEC_AXIS_X, ENABLE);
+ * }
+ * \endcode
+ */
+void QDEC_Cmd(QDEC_TypeDef *QDECx, uint32_t QDEC_AXIS,
+              FunctionalState newState);
+
+/**
+ * \brief   Clear QDEC interrupt pending bit.
+ * \param[in]  QDECx: Selected QDEC peripheral.
+ * \param[in]  QDEC_CLR_INT: Specify the flag to clear.
+ *      This parameter can be one of the following values, which refer to \ref QDEC_Clr_Flag.
+ *      \arg  QDEC_CLR_OVERFLOW_X: The overflow flag for x-axis accumulation counter.
+ *      \arg  QDEC_CLR_OVERFLOW_Y: The overflow flag for y-axis accumulation counter.
+ *      \arg  QDEC_CLR_OVERFLOW_Z: The overflow flag for z-axis accumulation counter.
+ *      \arg  QDEC_CLR_ILLEGAL_INT_X: The illegal interrupt for X axis.
+ *      \arg  QDEC_CLR_ILLEGAL_INT_Y: The illegal interrupt for Y axis.
+ *      \arg  QDEC_CLR_ILLEGAL_INT_Z: The illegal interrupt for Z axis.
+ *      \arg  QDEC_CLR_UNDERFLOW_X: The underflow flag for x-axis accumulation counter.
+ *      \arg  QDEC_CLR_UNDERFLOW_Y: The underflow flag for y-axis accumulation counter.
+ *      \arg  QDEC_CLR_UNDERFLOW_Z: The underflow flag for z-axis accumulation counter.
+ *      \arg  QDEC_CLR_NEW_CT_X: The counter interrupt for X axis.
+ *      \arg  QDEC_CLR_NEW_CT_Y: The counter interrupt for Y axis.
+ *      \arg  QDEC_CLR_NEW_CT_Z: The counter interrupt for Z axis.
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void qdec_demo(void)
+ * {
+ *     QDEC_ClearINTPendingBit(QDEC, QDEC_CLR_OVERFLOW_X);
+ * }
+ * \endcode
+ */
+__STATIC_INLINE void QDEC_ClearINTPendingBit(QDEC_TypeDef *QDECx, uint32_t QDEC_CLR_INT)
+{
+    /* Check the parameters */
+    assert_param(IS_QDEC_PERIPH(QDECx));
+    assert_param(IS_QDEC_CLR_INT_STATUS(QDEC_CLR_INT));
+
+    QDECx->INT_CLR |= QDEC_CLR_INT;
+
+    return;
+}
+
+/**
+ * \brief  Get QDEC Axis(x/y/z) direction.
+ * \param[in]  QDECx: Selected QDEC peripheral.
+ * \param[in]  QDEC_AXIS: Specify the QDEC axis.
+ *      This parameter can be one of the following values, which refer to \ref QDEC_Axis.
+ *      \arg  QDEC_AXIS_X: The qdecoder X axis.
+ *      \arg  QDEC_AXIS_Y: The qdecoder Y axis.
+ *      \arg  QDEC_AXIS_Z: The qdecoder Z axis.
+ * \return The direction of the axis.
+ *      This parameter can be one of the following values, which refer to \ref QDEC_Axis_Direction.
+ *     \retval QDEC_AXIS_DIR_UP: The axis is rolling up.
+ *     \retval QDEC_AXIS_DIR_DOWN: The axis is rolling down.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void qdec_demo(void)
+ * {
+ *     uint16_t dir = QDEC_GetAxisDirection(QDEC, QDEC_AXIS_X);
+ * }
+ * \endcode
+ */
+__STATIC_INLINE uint16_t QDEC_GetAxisDirection(QDEC_TypeDef *QDECx, uint32_t QDEC_AXIS)
+{
+    /* Check the parameters */
+    assert_param(IS_QDEC_PERIPH(QDECx));
+    assert_param(IS_QDEC_AXIS_DIR(QDEC_AXIS));
+
+    return ((*((volatile uint32_t *)(&QDECx->REG_SR_X) + QDEC_AXIS / 2) & (1 << 16)) == BIT(16));
+}
+
+/**
+ * \brief  Get QDEC Axis(x/y/z) count.
+ * \param[in]  QDECx: Selected QDEC peripheral.
+ * \param[in]  QDEC_AXIS: Specify the QDEC axis.
+ *      This parameter can be one of the following values, which refer to \ref QDEC_Axis.
+ *      \arg  QDEC_AXIS_X: The qdecoder X axis.
+ *      \arg  QDEC_AXIS_Y: The qdecoder Y axis.
+ *      \arg  QDEC_AXIS_Z: The qdecoder Z axis.
+ * \return The count of the axis.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void qdec_demo(void)
+ * {
+ *     uint16_t counter = QDEC_GetAxisCount(QDEC, QDEC_AXIS_X);
+ * }
+ * \endcode
+ */
+__STATIC_INLINE uint16_t QDEC_GetAxisCount(QDEC_TypeDef *QDECx, uint32_t QDEC_AXIS)
+{
+    /* Check the parameters */
+    assert_param(IS_QDEC_PERIPH(QDECx));
+    assert_param(IS_QDEC_AXIS_DIR(QDEC_AXIS));
+
+    return ((uint16_t)(*((volatile uint32_t *)(&QDECx->REG_SR_X) + QDEC_AXIS / 2)));
+}
+
+/**
+ * \brief  Pause or resume QDEC Axis(x/y/z).
+ * \param[in]  QDECx: Selected QDEC peripheral.
+ * \param[in]  QDEC_AXIS: Specify the QDEC axis.
+ *      This parameter can be one of the following values, which refer to \ref QDEC_Axis.
+ *      \arg  QDEC_AXIS_X: The qdecoder X axis.
+ *      \arg  QDEC_AXIS_Y: The qdecoder Y axis.
+ *      \arg  QDEC_AXIS_Z: The qdecoder Z axis.
+ * \param[in]  newState: New state of the specified QDEC Axis.
+ *      This parameter can be one of the following values:
+ *      \arg  ENABLE: Pause.
+ *      \arg  DISABLE: Resume.
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void qdec_demo(void)
+ * {
+ *     QDEC_CounterPauseCmd(QDEC, QDEC_AXIS_X, ENABLE);
+ * }
+ * \endcode
+ */
+__STATIC_INLINE void QDEC_CounterPauseCmd(QDEC_TypeDef *QDECx, uint32_t QDEC_AXIS,
+                                          FunctionalState newState)
+{
+    /* Check the parameters */
+    assert_param(IS_QDEC_PERIPH(QDECx));
+    assert_param(IS_QDEC_AXIS_DIR(QDEC_AXIS));
+
+    if (newState == ENABLE)
+    {
+        *((volatile uint32_t *)(&QDECx->REG_CR_X) + QDEC_AXIS / 2) |= BIT3;
+    }
+    else
+    {
+        *((volatile uint32_t *)(&QDECx->REG_CR_X) + QDEC_AXIS / 2) &= ~BIT3;
+    }
+}
+
+/** End of QDEC_Exported_Functions
+  * \}
+  */
+
+/** End of QDEC
+  * \}
+  */
+
+typedef struct
+{
+    uint32_t qdec_reg[5];
+} QDECStoreReg_TypeDef;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTL876X_QDEC_H_ */
+
diff --git a/bee/drivers/qdec/src/device/rtl87x2g/rtl_aon_qdec.c b/bee/drivers/qdec/src/device/rtl87x2g/rtl_aon_qdec.c
new file mode 100644
index 00000000..876632a0
--- /dev/null
+++ b/bee/drivers/qdec/src/device/rtl87x2g/rtl_aon_qdec.c
@@ -0,0 +1,366 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *                        Header Files
+ *============================================================================*/
+#include "rtl_aon_qdec.h"
+
+/*============================================================================*
+ *                           Public Functions
+ *============================================================================*/
+/**
+  * \brief  Reset AON QDEC.
+  * \param  None
+  * \return None
+  */
+void AON_QDEC_DeInit(void)
+{
+    AON_QDEC_CONFIG_TypeDef aon_qdec_0x00 = {.d32 = AON_QDEC->AON_QDEC_CONFIG};
+    /* Disable the AON QDEC. */
+    aon_qdec_0x00.b.x_axis_en = 0;
+
+    /* Disable the interrupt of AON QDEC. */
+    aon_qdec_0x00.b.x_cnt_int_en = 0;
+    aon_qdec_0x00.b.x_illegal_int_en = 0;
+
+    /* Mask the interrupt of AON QDEC. */
+    aon_qdec_0x00.b.cnt_int_mask = 1;
+    aon_qdec_0x00.b.illegal_int_mask = 1;
+    aon_qdec_0x00.b.x_int_mask = 1;
+    aon_qdec_0x00.b.x_wake_aon_mask = 1;
+
+    /* Disable the debounce function and clear the debounce time. */
+    aon_qdec_0x00.b.x_debounce_en = 0;
+    aon_qdec_0x00.b.x_debounce_cnt = 0;
+
+    /* Reset counter scale. */
+    aon_qdec_0x00.b.x_cnt_scale = 0;
+    AON_QDEC->AON_QDEC_CONFIG = aon_qdec_0x00.d32;
+    for (volatile uint32_t i = 0; i < 150; i++);
+
+    /* Set initial phase to 00. */
+    aon_qdec_0x00.b.x_set_initial_phase = 1;
+    aon_qdec_0x00.b.x_initial_phase = phaseMode0;
+    AON_QDEC->AON_QDEC_CONFIG = aon_qdec_0x00.d32;
+    for (volatile uint32_t i = 0; i < 150; i++);
+
+    aon_qdec_0x00.b.x_set_initial_phase = 0;
+    AON_QDEC->AON_QDEC_CONFIG = aon_qdec_0x00.d32;
+    for (volatile uint32_t i = 0; i < 150; i++);
+
+    /* Clear ACC counter and illegal counter. */
+    AON_QDEC_INT_CLR_TypeDef aon_qdec_0x08 = {.d32 = AON_QDEC->AON_QDEC_INT_CLR};
+    aon_qdec_0x08.b.acc_cnt_clr = 1;
+    aon_qdec_0x08.b.illegal_cnt_clr = 1;
+    AON_QDEC->AON_QDEC_INT_CLR = aon_qdec_0x08.d32;
+    for (volatile uint32_t i = 0; i < 150; i++);
+}
+
+
+/**
+  * \brief  Initializes the AON Qdecoder peripheral according to the specified
+  *         parameters in the AON_QDEC_InitStruct
+  * \param  AON_QDECx: selected AON Qdecoder peripheral.
+  * \param  AON_QDEC_InitStruct: pointer to an AON_QDEC_InitStruct structure that
+  *         contains the configuration information for the specified AON Qdecoder peripheral
+  * \return None
+  */
+void AON_QDEC_Init(AON_QDEC_TypeDef *AON_QDECx, AON_QDEC_InitTypeDef *AON_QDEC_InitStruct)
+{
+    assert_param(IS_QDEC_PERIPH(AON_QDECx));
+
+    AON_QDEC_CONFIG_TypeDef aon_qdec_0x00 = {.d32 = AON_QDECx->AON_QDEC_CONFIG};
+
+    /* Set Manual Initial Phase*/
+    if (AON_QDEC_InitStruct->manualLoadInitPhase == ENABLE)
+    {
+        aon_qdec_0x00.b.x_axis_en = 0x0;
+        aon_qdec_0x00.b.x_set_initial_phase = 0x1;
+        aon_qdec_0x00.b.x_initial_phase = AON_QDEC_InitStruct->initPhaseX;
+        AON_QDECx->AON_QDEC_CONFIG = aon_qdec_0x00.d32;
+        for (volatile uint32_t i = 0; i < 150; i++);
+    }
+
+    aon_qdec_0x00.b.x_set_initial_phase = 0x0;
+    AON_QDECx->AON_QDEC_CONFIG = aon_qdec_0x00.d32;
+    for (volatile uint32_t i = 0; i < 150; i++);
+
+    /* The max debounce cnt is 0x1FFF*/
+    if (AON_QDEC_InitStruct->debounceTimeX >=  0x1FFF)
+    {
+        AON_QDEC_InitStruct->debounceTimeX = 0x1FFF;
+
+    }
+    /* QDEC configure */
+    aon_qdec_0x00.b.x_debounce_cnt = AON_QDEC_InitStruct->debounceTimeX;
+    aon_qdec_0x00.b.x_cnt_scale = AON_QDEC_InitStruct->counterScaleX;
+    aon_qdec_0x00.b.x_debounce_en = AON_QDEC_InitStruct->debounceEnableX;
+    AON_QDECx->AON_QDEC_CONFIG = aon_qdec_0x00.d32;
+
+    AON_QDEC_INT_CLR_TypeDef aon_qdec_0x08 = {.d32 = AON_QDECx->AON_QDEC_INT_CLR};
+    aon_qdec_0x08.b.acc_cnt_clr = 0x1; // write 1 to clear acc cnt
+    AON_QDECx->AON_QDEC_INT_CLR = aon_qdec_0x08.d32;
+    return;
+}
+
+
+/**
+  * \brief  Fills each AON_QDEC_InitStruct member with its default value.
+  * \param  AON_QDEC_InitStruct: pointer to an AON_QDEC_InitStruct structure which will be initialized.
+  * \return None
+  */
+void AON_QDEC_StructInit(AON_QDEC_InitTypeDef *AON_QDEC_InitStruct)
+{
+    AON_QDEC_InitStruct->debounceTimeX       = 32 * 5; /*!< 5ms */
+    AON_QDEC_InitStruct->counterScaleX       = CounterScale_1_Phase;
+    AON_QDEC_InitStruct->debounceEnableX     = DISABLE;
+    AON_QDEC_InitStruct->manualLoadInitPhase = DISABLE;
+    AON_QDEC_InitStruct->initPhaseX          = phaseMode0;
+
+    return;
+}
+
+
+/**
+  * \brief  Enable or disable the specified AON Qdecoder interrupts.
+  * \param  AON_QDECx: selected AON Qdecoder peripheral.
+  * \param  AON_QDEC_IT: specifies the AON QDECODER interrupts sources to be enabled or disabled.
+  *         This parameter can be one of the following values:
+  *         \arg AON_QDEC_X_INT_NEW_DATA:
+  *         \arg AON_QDEC_X_INT_ILLEAGE:
+  * \param  NewState: new state of the specified AON QDECODER interrupts.
+  *         This parameter can be: ENABLE or DISABLE.
+  * \return None
+  */
+void AON_QDEC_INTConfig(AON_QDEC_TypeDef *AON_QDECx, uint32_t AON_QDEC_IT,
+                        FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_AON_QDEC_PERIPH(AON_QDECx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+    assert_param(IS_AON_QDEC_INT_CONFIG(AON_QDEC_IT));
+
+    AON_QDEC_CONFIG_TypeDef aon_qdec_0x00 = {.d32 = AON_QDECx->AON_QDEC_CONFIG};
+
+    /* Enable or disable the selected AON QDECODER interrupts */
+    if (AON_QDEC_IT & AON_QDEC_X_INT_NEW_DATA)
+    {
+        aon_qdec_0x00.b.x_cnt_int_en = NewState;
+    }
+    if (AON_QDEC_IT & AON_QDEC_X_INT_ILLEAGE)
+    {
+        aon_qdec_0x00.b.x_illegal_int_en = NewState;
+    }
+    AON_QDECx->AON_QDEC_CONFIG = aon_qdec_0x00.d32;
+    return;
+}
+
+/**
+  * \brief  Checks whether the specified AON Qdecoder flag is set or not.
+  * \param  AON_QDECx: selected AON Qdecoder peripheral.
+  * \param  AON_QDEC_FLAG: specifies the flag to check.
+  *         This parameter can be one of the following values:
+  *         \arg AON_QDEC_FLAG_NEW_CT_STATUS_X:
+  *         \arg AON_QDEC_FLAG_ILLEGAL_STATUS_X:
+  *         \arg AON_QDEC_FLAG_OVERFLOW_X:
+  *         \arg AON_QDEC_FLAG_UNDERFLOW_X:
+  * \return The new state of AON_QDEC_FLAG (SET or RESET).
+  */
+FlagStatus AON_QDEC_GetFlagState(AON_QDEC_TypeDef *AON_QDECx, uint32_t AON_QDEC_FLAG)
+{
+    /* Check the parameters */
+    assert_param(IS_AON_QDEC_PERIPH(QDECx));
+    assert_param(IS_AON_QDEC_CLR_INT_STATUS(QDEC_FLAG));
+
+    FlagStatus bitstatus = RESET;
+
+    if (AON_QDEC_FLAG == AON_QDEC_FLAG_NEW_CT_STATUS_X)
+    {
+        if (AON_QDECx->AON_QDEC_SR_X & (BIT18))
+        {
+            bitstatus = SET;
+        }
+    }
+    else if (AON_QDEC_FLAG == AON_QDEC_FLAG_ILLEGAL_STATUS_X)
+    {
+        if (AON_QDECx->AON_QDEC_SR_X & (BIT19))
+        {
+            bitstatus = SET;
+        }
+    }
+    else if (AON_QDEC_FLAG == AON_QDEC_FLAG_OVERFLOW_X)
+    {
+        if (AON_QDECx->AON_QDEC_SR_X & (BIT16))
+        {
+            bitstatus = SET;
+        }
+    }
+    else if (AON_QDEC_FLAG == AON_QDEC_FLAG_UNDERFLOW_X)
+    {
+        if (AON_QDECx->AON_QDEC_SR_X & (BIT17))
+        {
+            bitstatus = SET;
+        }
+    }
+
+    return bitstatus;
+}
+
+/**
+  * \brief  Enable or disable mask the specified AON Qdecoder axis interrupts.
+  * \param  AON_QDECx: selected AON Qdecoder peripheral.
+  * \param  AON_QDEC_AXIS: specifies the AON Qdecoder axis.
+  *         This parameter can be one or logical OR of the following values:
+  *         \arg AON_QDEC_X_CT_INT_MASK: The AON qdecoder CNT interrupt mask.
+  *         \arg AON_QDEC_X_ILLEAGE_INT_MASK: The AON qdecoder illeage interrupt mask.
+  *         \arg AON_QDEC_X_WAKE_AON_MASK: The AON qdecoder wake up AON mask.
+  *         \arg AON_QDEC_X_INT_MASK: The AON qdecoder interrupt mask.
+  * \param  NewState: new state of the specified AON Qdecoder interrupts mask.
+  *         This parameter can be: ENABLE or DISABLE.
+  * \return None
+  */
+void AON_QDEC_INTMask(AON_QDEC_TypeDef *AON_QDECx, uint32_t AON_QDEC_AXIS,
+                      FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_AON_QDEC_PERIPH(AON_QDECx));
+    assert_param(IS_AON_QDEC_INT_MASK_CONFIG(AON_QDEC_AXIS));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (NewState == ENABLE)
+    {
+        /* mask the selected AON_QDEC interrupts */
+        AON_QDECx->AON_QDEC_CONFIG |= (AON_QDEC_AXIS);
+    }
+    else
+    {
+        /* unmask the selected AON_QDEC interrupts */
+        AON_QDECx->AON_QDEC_CONFIG &= (~(AON_QDEC_AXIS));
+    }
+
+    return;
+}
+
+/**
+  * \brief  Enable or disable AON Qdecoder Axis x direction.
+  * \param  AON_QDECx: selected AON Qdecoder peripheral.
+  * \param  AON_QDEC_AXIS: specifies the AON Qdecoder axis.
+  *         This parameter can be one of the following values:
+  *         \arg QDEC_AXIS_X: The qdecoder X axis.
+  * \param  NewState: This parameter can be one of the following values:
+  *         \arg ENABLE: Pause.
+  *         \arg DISABLE: Resume.
+  */
+void AON_QDEC_Cmd(AON_QDEC_TypeDef *AON_QDECx, uint32_t AON_QDEC_AXIS,
+                  FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_AON_QDEC_PERIPH(AON_QDECx));
+    assert_param(IS_AON_QDEC_AXIS_DIR(AON_QDEC_AXIS));
+
+    if (NewState == ENABLE)
+    {
+        *((volatile uint32_t *)(&AON_QDECx->AON_QDEC_CONFIG) + AON_QDEC_AXIS / 2) |= AON_QDEC_0X00_AXIS_EN;
+
+    }
+    else
+    {
+        *((volatile uint32_t *)(&AON_QDECx->AON_QDEC_CONFIG) + AON_QDEC_AXIS / 2) &= ~
+                                                                                     (AON_QDEC_0X00_AXIS_EN);
+    }
+}
+
+/**
+  * \brief  Clear AON Qdecoder interrupt pending bit.
+  * \param  AON_QDECx: Selected AON Qdecoder peripheral.
+  * \param  AON_QDEC_FLAG: Specifies the flag to clear.
+  *         This parameter parameter can be one of the following values:
+  *         \arg AON_QDEC_CLR_OVERFLOW_X: The overflow flag for x-axis accumulation counter.
+  *         \arg AON_QDEC_CLR_ILLEGAL_INT_X: The illegal interrupt for X axis.
+  *         \arg AON_QDEC_CLR_UNDERFLOW_X: The underflow flag for x-axis accumulation counter.
+  *         \arg AON_QDEC_CLR_NEW_CT_X: The counter interrupt for X axis.
+  * \return None.
+  */
+void AON_QDEC_ClearINTPendingBit(AON_QDEC_TypeDef *AON_QDECx, uint32_t AON_QDEC_CLR_INT)
+{
+    /* Check the parameters */
+    assert_param(IS_AON_QDEC_PERIPH(AON_QDECx));
+    assert_param(IS_AON_QDEC_CLR_INT_STATUS(AON_QDEC_CLR_INT));
+
+    AON_QDECx->AON_QDEC_INT_CLR |= AON_QDEC_CLR_INT;
+
+    return;
+}
+
+/**
+  * \brief  Get AON Qdecoder Axis(x/y/z) direction.
+  *
+  * \param  AON_QDECx: Selected AON Qdecoder peripheral.
+  * \param  AON_QDEC_AXIS: Specifies the AON Qdecoder axis.
+  *         This parameter parameter can be one of the following values:
+  *         \arg  AON_QDEC_AXIS_X: The AON qdecoder X axis.
+  * \return The direction of the axis. This parameter parameter can be one of the following values:
+  *         \retval AON_QDEC_AXIS_DIR_UP: The axis is rolling up.
+  *         \retval AON_QDEC_AXIS_DIR_DOWN: The axis is rolling down.
+  */
+uint16_t AON_QDEC_GetAxisDirection(AON_QDEC_TypeDef *AON_QDECx,
+                                   uint32_t AON_QDEC_AXIS)
+{
+    /* Check the parameters */
+    assert_param(IS_AON_QDEC_PERIPH(AON_QDECx));
+    assert_param(IS_AON_QDEC_AXIS_DIR(AON_QDEC_AXIS));
+
+    return ((*((volatile uint32_t *)(&AON_QDECx->AON_QDEC_SR_X)) & (1 << 20)) == AON_QDEC_0X04_CNT_DIR);
+}
+
+/**
+  * \brief  Get AON Qdecoder Axis(x/y/z) count.
+  *
+  * \param  AON_QDECx: Selected AON Qdecoder peripheral.
+  * \param  AON_QDEC_AXIS: Specifies the AON Qdecoder axis.
+  *         This parameter parameter can be one of the following values:
+  *         \arg AON_QDEC_AXIS_X: The AON qdecoder X axis.
+  * \return The count of the axis.
+  */
+uint16_t AON_QDEC_GetAxisCount(AON_QDEC_TypeDef *AON_QDECx,
+                               uint32_t AON_QDEC_AXIS)
+{
+    /* Check the parameters */
+    assert_param(IS_AON_QDEC_PERIPH(AON_QDECx));
+    assert_param(IS_AON_QDEC_AXIS_DIR(AON_QDEC_AXIS));
+
+    return ((uint16_t)(*((volatile uint32_t *)(&AON_QDECx->AON_QDEC_SR_X))));
+}
+
+/**
+  * \brief  Pause or resume AON Qdecoder Axis x.
+  *
+  * \param  AON_QDECx: Selected AON Qdecoder peripheral.
+  * \param  AON_QDEC_AXIS: Specifies the AON Qdecoder axis.
+  *         This parameter parameter can be one of the following values:
+  *         \arg AON_QDEC_AXIS_X: The AON qdecoder X axis.
+  * \param  NewState: New state of the specified AON Qdecoder Axis.
+  *         This parameter parameter can be one of the following values:
+  *         \arg ENABLE: Pause.
+  *         \arg DISABLE: Resume.
+  * \return None.
+  */
+void AON_QDEC_CounterPauseCmd(AON_QDEC_TypeDef *AON_QDECx,
+                              uint32_t AON_QDEC_AXIS,
+                              FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_AON_QDEC_PERIPH(AON_QDECx));
+    assert_param(IS_AON_QDEC_AXIS_DIR(AON_QDEC_AXIS));
+
+    AON_QDEC_CONFIG_TypeDef aon_qdec_0x00 = {.d32 = AON_QDECx->AON_QDEC_CONFIG};
+    aon_qdec_0x00.b.x_cnt_pause = NewState;
+    AON_QDECx->AON_QDEC_CONFIG = aon_qdec_0x00.d32;
+}
+
+
+
diff --git a/bee/drivers/qdec/src/device/rtl87x2g/rtl_aon_qdec.h b/bee/drivers/qdec/src/device/rtl87x2g/rtl_aon_qdec.h
new file mode 100644
index 00000000..6d256998
--- /dev/null
+++ b/bee/drivers/qdec/src/device/rtl87x2g/rtl_aon_qdec.h
@@ -0,0 +1,502 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *               Define to prevent recursive inclusion
+ *============================================================================*/
+#ifndef RTL_AON_QDEC_H
+#define RTL_AON_QDEC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*============================================================================*
+ *                        Header Files
+ *============================================================================*/
+#include "utils/rtl_utils.h"
+#include "rtl_aon_qdec_def.h"
+
+/** \defgroup AON_QDEC    AON_QDEC
+  * \brief
+  * \{
+  */
+
+/*============================================================================*
+ *                         Constants
+ *============================================================================*/
+/** \defgroup AON_QDEC_Exported_Constants AON_QDEC Exported Constants
+  * \brief
+  * \{
+  */
+
+/**
+ * \defgroup    AON_QDEC_Counter_Scale AON_QDEC Counter Scale
+ * \{
+ * \ingroup     AON_QDEC_Exported_Constants
+ */
+typedef enum
+{
+    CounterScale_1_Phase = 0x00,     //!< AON_QDEC update counter when 1 phase change.
+    CounterScale_2_Phase = 0x01,     //!< AON_QDEC update counter when 2 phases change.
+} AONQDECAxisCntScale_TypeDef;
+
+#define IS_CNT_SCALE_PHASE_TYPE(TYPE) ((TYPE) <= 0x01) //!< Check if the input parameter is valid.
+
+/** End of AON_QDEC_Counter_Scale
+  * \}
+  */
+
+/**
+ * \defgroup    AON_QDEC_Init_Phase AON_QDEC Init Phase
+ * \{
+ * \ingroup     AON_QDEC_Exported_Constants
+ */
+typedef enum
+{
+    phaseMode0 = 0x00,     //!< AON_QDEC initial phase 00.
+    phaseMode1 = 0x01,     //!< AON_QDEC initial phase 01.
+    phaseMode2 = 0x02,     //!< AON_QDEC initial phase 10.
+    phaseMode3 = 0x03,     //!< AON_QDEC initial phase 11.
+} AONQDECInitPhase_TypeDef;
+
+#define IS_PHSAE_MODE_TYPE(TYPE) ((TYPE) <= 0x03) //!< Check if the input parameter is valid.
+
+/** End of AON_QDEC_Init_Phase
+  * \}
+  */
+
+/**
+ * \defgroup    AON_QDEC_Axis_Direction AON_QDEC Axis Direction
+ * \{
+ * \ingroup     AON_QDEC_Exported_Constants
+ */
+typedef enum
+{
+    AON_QDEC_AXIS_DIR_DOWN = 0x00,     //!< The direction for x-axis is decreasing.
+    AON_QDEC_AXIS_DIR_UP = 0x01,       //!< The direction for x-axis is increasing.
+} AONQDECAxisDir_TypeDef;
+
+#define IS_AON_QDEC_AXIS_DIR_TYPE(TYPE) ((TYPE) <= 0x01) //!< Check if the input parameter is valid.
+
+/** End of AON_QDEC_Axis_Direction
+  * \}
+  */
+
+/**
+ * \defgroup    AON_QDEC_Interrupts AON_QDEC Interrupts
+ * \{
+ * \ingroup     AON_QDEC_Exported_Constants
+ */
+#define AON_QDEC_X_INT_NEW_DATA                     BIT0     //!< The counter interrupt triggered by new data on x-axis.
+#define AON_QDEC_X_INT_ILLEAGE                      BIT1     //!< The illegal interrupt on x-axis.
+
+#define IS_AON_QDEC_INT_CONFIG(CONFIG) (((CONFIG) == AON_QDEC_X_INT_NEW_DATA) || ((CONFIG) == AON_QDEC_X_INT_ILLEAGE)) //!< Check if the input parameter is valid.
+
+/** End of AON_QDEC_Interrupts
+  * \}
+  */
+
+/**
+ * \defgroup    AON_QDEC_Interrupts_Mask AON_QDEC Interrupts Mask
+ * \{
+ * \ingroup     AON_QDEC_Exported_Constants
+ */
+#define AON_QDEC_X_INT_MASK                         BIT24     //!< AON_QDEC interrupt mask.
+#define AON_QDEC_X_WAKE_AON_MASK                    BIT23     //!< AON_QDEC wakeup interrupt mask.
+#define AON_QDEC_X_CT_INT_MASK                      BIT8      //!< AON_QDEC counter interrupt mask triggered by new data.
+#define AON_QDEC_X_ILLEAGE_INT_MASK                 BIT7      //!< AON_QDEC illegal interrupt mask.
+
+#define IS_AON_QDEC_INT_MASK_CONFIG(CONFIG) (((CONFIG) == AON_QDEC_X_CT_INT_MASK) || ((CONFIG) == AON_QDEC_X_ILLEAGE_INT_MASK)) //!< Check if the input parameter is valid.
+
+/** End of AON_QDEC_Interrupts_Mask
+  * \}
+  */
+
+/**
+ * \defgroup    AON_QDEC_Clr_Flag AON_QDEC Clr Flag
+ * \{
+ * \ingroup     AON_QDEC_Exported_Constants
+ */
+#define AON_QDEC_CLR_ILLEGAL_CT_X                   BIT5    //!< Clear the counter of illegal interrupts.
+#define AON_QDEC_CLR_ILLEGAL_INT_X                  BIT4    //!< Clear the illegal interrupt flag.
+#define AON_QDEC_CLR_UNDERFLOW_X                    BIT3    //!< Clear the underflow flag.
+#define AON_QDEC_CLR_OVERFLOW_X                     BIT2    //!< Clear the overflow flag.
+#define AON_QDEC_CLR_NEW_CT_X                       BIT1    //!< Clear the new data flag.
+#define AON_QDEC_CLR_ACC_CT_X                       BIT0    //!< Clear the ACC counter flag.
+
+#define IS_AON_QDEC_INT_CLR_CONFIG(CONFIG) (((CONFIG) == AON_QDEC_CLR_ACC_CT_X) ||  ((CONFIG) == AON_QDEC_CLR_ILLEGAL_INT_X)\
+                                            || ((CONFIG) == AON_QDEC_CLR_UNDERFLOW_X) ||((CONFIG) == AON_QDEC_CLR_OVERFLOW_X)\
+                                            || ((CONFIG) == AON_QDEC_CLR_NEW_CT_X)) //!< Check if the input parameter is valid.
+
+/** End of AON_QDEC_Clr_Flag
+  * \}
+  */
+
+/**
+ * \defgroup    AON_QDEC_Flag AON_QDEC Flag
+ * \{
+ * \ingroup     AON_QDEC_Exported_Constants
+ */
+#define AON_QDEC_FLAG_NEW_CT_STATUS_X               BIT0    //!< The new data flag.
+#define AON_QDEC_FLAG_OVERFLOW_X                    BIT1    //!< The overflow flag.
+#define AON_QDEC_FLAG_UNDERFLOW_X                   BIT2    //!< The underflow flag.
+#define AON_QDEC_FLAG_ILLEGAL_STATUS_X              BIT4    //!< The illegal counting flag.
+
+#define IS_AON_QDEC_CLR_INT_STATUS(INT) (((INT) == AON_QDEC_FLAG_ILLEGAL_STATUS_X) || ((INT) == AON_QDEC_FLAG_NEW_CT_STATUS_X)\
+                                         || ((INT) == AON_QDEC_FLAG_OVERFLOW_X) || ((INT) == AON_QDEC_FLAG_UNDERFLOW_X)\
+                                         || ((INT) == AON_QDEC_FLAG_AUTO_STATUS_X)) //!< Check if the input parameter is valid.
+
+/** End of AON_QDEC_Flag
+  * \}
+  */
+
+/**
+ * \defgroup    AON_QDEC_Axis AON_QDEC Axis
+ * \{
+ * \ingroup     AON_QDEC_Exported_Constants
+ */
+#define AON_QDEC_AXIS_X                             BIT0    //!< The AON_QDEC X axis.
+
+/** End of AON_QDEC_Axis
+  * \}
+  */
+
+/**
+ * \defgroup    AON_QDEC_Immediate_Number AON_QDEC Immediate Number
+ * \{
+ * \ingroup     AON_QDEC_Exported_Constants
+ */
+#define AON_QDEC_0X04_CNT_DIR           BIT20    //!< The AON_QDEC x-axis direction.
+#define AON_QDEC_0X00_AXIS_EN           BIT31    //!< The AON_QDEC x-axis enable bit.
+
+/** End of AON_QDEC_Immediate_Number
+  * \}
+  */
+
+/** End of AON_QDEC_Exported_Constants
+  * \}
+  */
+
+/*============================================================================*
+ *                         Types
+ *============================================================================*/
+/** \defgroup AON_QDEC_Exported_Types AON_QDEC Exported Types
+  * \brief
+  * \{
+  */
+
+/**
+ * \brief       AON_QDEC init structure definition.
+ *
+ * \ingroup     AON_QDEC_Exported_Types
+ */
+typedef struct
+{
+    FunctionalState axisConfigX;               /*!< Specify the x-axis function.
+                                                    This parameter can be a value of ENABLE or DISABLE. */
+
+    FunctionalState manualLoadInitPhase;       /*!< Specify manual-load initial phase function.
+                                                    This parameter can be a value of ENABLE or DISABLE. */
+
+    AONQDECAxisCntScale_TypeDef counterScaleX; /*!< Specify the x-axis counter scale.
+                                                    This parameter can be a value of \ref AON_QDEC_Counter_Scale */
+
+    FunctionalState debounceEnableX;           /*!< Specify the x-axis debounce function.
+                                                    This parameter can be a value of ENABLE or DISABLE. */
+
+    uint16_t debounceTimeX;                    /*!< Specify the x-axis debounce time.
+                                                    This parameter can be a value of 0 - 8191 */
+
+    AONQDECInitPhase_TypeDef initPhaseX;       /*!< Specify the x-axis initial phase.
+                                                    This parameter can be a value of \ref AON_QDEC_Init_Phase */
+} AON_QDEC_InitTypeDef;
+
+/** End of AON_QDEC_Exported_Types
+  * \}
+  */
+
+/*============================================================================*
+ *                         Functions
+ *============================================================================*/
+/** \defgroup AON_QDEC_Exported_Functions AON_QDEC Exported Functions
+  * \brief
+  * \{
+  */
+
+/**
+  * \brief  Reset AON QDEC.
+  *
+  * \param[in]  None
+  */
+void AON_QDEC_DeInit(void);
+
+/**
+ * \brief   Initialize the AON_QDEC peripheral according to the specified
+ *          parameters in the AON_QDEC_InitStruct
+ *
+ * \param[in]  AON_QDECx            Selected AON_QDEC peripheral. Refer to \ref AON_QDEC_Declaration.
+ * \param[in]  AON_QDEC_InitStruct  Pointer to a AON_QDEC_InitStruct structure which will be initialized.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_aon_qdec_init(void)
+ * {
+ *
+ *     AON_QDEC_InitTypeDef AON_QDEC_InitStruct;
+ *     AON_QDEC_StructInit(&AON_QDEC_InitStruct);
+ *     AON_QDEC_InitStruct.axisConfigX       = ENABLE;
+ *     AON_QDEC_InitStruct.debounceEnableX   = Debounce_Enable;
+ *     AON_QDEC_Init(AON_QDEC, &AON_QDEC_InitStruct);
+ *
+ *     AON_QDEC_Cmd(AON_QDEC, AON_QDEC_AXIS_X, ENABLE);
+ * }
+ * \endcode
+ */
+void AON_QDEC_Init(AON_QDEC_TypeDef *AON_QDECx, AON_QDEC_InitTypeDef *AON_QDEC_InitStruct);
+
+/**
+ * \brief  Fill each AON_QDEC_InitStruct member with its default value.
+ *
+ * \note The default settings for the AON_QDEC_InitStruct member are shown in the following table:
+ *       | AON_QDEC_InitStruct member   | Default value                        |
+ *       |:----------------------------:|:------------------------------------:|
+ *       | debounceTimeX                | 32 * 5                               |
+ *       | counterScaleX                | \ref CounterScale_1_Phase            |
+ *       | debounceEnableX              | DISABLE                              |
+ *       | manualLoadInitPhase          | DISABLE                              |
+ *       | initPhaseX                   | \ref phaseMode0                      |
+ *
+ * \param[in]  AON_QDEC_InitStruct  Pointer to an AON_QDEC_InitStruct structure which will be initialized.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_aon_qdec_init(void)
+ * {
+ *
+ *     AON_QDEC_InitTypeDef AON_QDEC_InitStruct;
+ *     AON_QDEC_StructInit(&AON_QDEC_InitStruct);
+ *     AON_QDEC_InitStruct.axisConfigX       = ENABLE;
+ *     AON_QDEC_InitStruct.debounceEnableX   = Debounce_Enable;
+ *     AON_QDEC_Init(AON_QDEC, &AON_QDEC_InitStruct);
+ *
+ *     AON_QDEC_Cmd(AON_QDEC, AON_QDEC_AXIS_X, ENABLE);
+ * }
+ * \endcode
+ */
+void AON_QDEC_StructInit(AON_QDEC_InitTypeDef *AON_QDEC_InitStruct);
+
+/**
+ * \brief  Enable or disable the specified AON_QDEC interrupt source.
+ *
+ * \param[in] AON_QDECx    Selected AON_QDEC peripheral. Refer to \ref AON_QDEC_Declaration.
+ * \param[in] AON_QDEC_IT  Specify the AON_QDEC interrupts sources to be enabled or disabled.
+ *                         This parameter can be one of the following values:
+ *                         \arg AON_QDEC_X_INT_NEW_DATA: The counter interrupt for X axis.
+ *                         \arg AON_QDEC_X_INT_ILLEAGE: The illegal interrupt for X axis.
+ * \param[in] NewState     New state of the specified AON_QDEC interrupt.
+ *                         This parameter can be one of the following values:
+ *                         - ENABLE: Enable the interrupt of AON_QDEC.
+ *                         - DISABLE: Disable the interrupt of AON_QDEC.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_aon_qdec_init(void)
+ * {
+ *     AON_QDEC_INTConfig(AON_QDEC, AON_QDEC_X_INT_NEW_DATA, ENABLE);
+ * }
+ * \endcode
+ */
+void AON_QDEC_INTConfig(AON_QDEC_TypeDef *AON_QDECx, uint32_t AON_QDEC_IT,
+                        FunctionalState NewState);
+
+/**
+ * \brief  Get the specified AON_QDEC flag status.
+ *
+ * \param[in] AON_QDECx      Selected AON_QDEC peripheral. Refer to \ref AON_QDEC_Declaration.
+ * \param[in] AON_QDEC_FLAG  Specify the flag to check.
+ *                           This parameter can be one of the following values:
+ *                           \arg AON_QDEC_FLAG_NEW_CT_STATUS_X: Status of the counter interrupt for X axis.
+ *                           \arg AON_QDEC_FLAG_ILLEGAL_STATUS_X: Status of the illegal interrupt for X axis.
+ *                           \arg AON_QDEC_FLAG_OVERFLOW_X: The overflow flag for x-axis accumulation counter.
+ *                           \arg AON_QDEC_FLAG_UNDERFLOW_X: The underflow flag for x-axis accumulation counter.
+ *
+ * \return  The new state of AON_QDEC_FLAG.
+ *          - SET: The AON_QDEC flag has been set.
+ *          - RESET: The AON_QDEC flag has been reset.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void aon_qdec_demo(void)
+ * {
+ *     FlagStatus flag_status = AON_QDEC_GetFlagState(AON_QDEC, AON_QDEC_FLAG_NEW_CT_STATUS_X);
+ * }
+ * \endcode
+ */
+FlagStatus AON_QDEC_GetFlagState(AON_QDEC_TypeDef *AON_QDECx, uint32_t AON_QDEC_FLAG);
+
+/**
+ * \brief  Mask or unmask the specified AON_QDEC axis interrupts.
+ *
+ * \param[in] AON_QDECx      Selected AON_QDEC peripheral. Refer to \ref AON_QDEC_Declaration.
+ * \param[in] AON_QDEC_AXIS  Specify the AON_QDEC interrupt mask.
+ *                           This parameter can be one or logical OR of the following values:
+ *                           \arg AON_QDEC_X_CT_INT_MASK: The x-axis counter interrupt mask.
+ *                           \arg AON_QDEC_X_ILLEAGE_INT_MASK: The x-axis illegal interrupt mask.
+ * \param[in] NewState       New state of the specified AON_QDEC interrupts mask.
+ *                           This parameter can be one of the following values:
+ *                           - ENABLE: Enable the interrupt mask of AON_QDEC.
+ *                           - DISABLE: Disable the interrupt mask of AON_QDEC.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void aon_qdec_demo(void)
+ * {
+ *
+ *     AON_QDEC_INTMask(AON_QDEC, AON_QDEC_X_CT_INT_MASK, ENABLE);
+ *
+ * }
+ * \endcode
+ */
+void AON_QDEC_INTMask(AON_QDEC_TypeDef *AON_QDECx, uint32_t AON_QDEC_AXIS,
+                      FunctionalState NewState);
+
+/**
+ * \brief  Enable or disable the selected AON_QDEC axis x.
+ *
+ * \param[in] AON_QDECx      Selected AON_QDEC peripheral. Refer to \ref AON_QDEC_Declaration.
+ * \param[in] AON_QDEC_AXIS  Specify the AON_QDEC axis.
+ *                           This parameter can be one of the following values:
+ *                           \arg AON_QDEC_AXIS_X: The AON_QDEC X axis.
+ * \param[in] NewState       New state of the selected AON_QDEC axis.
+ *                           This parameter can be one of the following values:
+ *                           - ENABLE: Count value changes upon detecting a phase change.
+ *                           - DISABLE: AON_QDEC stops working.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void aon_qdec_demo(void)
+ * {
+ *     AON_QDEC_Cmd(AON_QDEC, AON_QDEC_AXIS_X, ENABLE);
+ * }
+ * \endcode
+ */
+void AON_QDEC_Cmd(AON_QDEC_TypeDef *AON_QDECx, uint32_t AON_QDEC_AXIS,
+                  FunctionalState NewState);
+
+/**
+ * \brief   Clear AON_QDEC interrupt pending bit.
+ *
+ * \param[in] AON_QDECx      Selected AON_QDEC peripheral. Refer to \ref AON_QDEC_Declaration.
+ * \param[in] AON_QDEC_FLAG  Specify the flag to clear.
+ *                           This parameter can be one of the following values.
+ *                           Refer to \ref AON_QDEC_Clr_Flag.
+ *                           - AON_QDEC_CLR_OVERFLOW_X: The overflow flag for x-axis accumulation counter.
+ *                           - AON_QDEC_CLR_ILLEGAL_INT_X: The illegal interrupt for X axis.
+ *                           - AON_QDEC_CLR_UNDERFLOW_X: The underflow flag for x-axis accumulation counter.
+ *                           - AON_QDEC_CLR_NEW_CT_X: The counter interrupt for X axis.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void aon_qdec_demo(void)
+ * {
+ *     AON_QDEC_ClearINTPendingBit(AON_QDEC, AON_QDEC_CLR_OVERFLOW_X);
+ * }
+ * \endcode
+ */
+
+void AON_QDEC_ClearINTPendingBit(AON_QDEC_TypeDef *AON_QDECx, uint32_t AON_QDEC_CLR_INT);
+/**
+ * \brief  Get AON_QDEC Axis direction.
+ *
+ * \param[in] AON_QDECx      Selected AON_QDEC peripheral. Refer to \ref AON_QDEC_Declaration.
+ * \param[in] AON_QDEC_AXIS  Specify the AON_QDEC axis.
+ *                            This parameter can be one of the following values:
+ *                            \arg  AON_QDEC_AXIS_X: The AON_QDEC X axis.
+ *
+ * \return The direction of the axis.
+ *         - AON_QDEC_AXIS_DIR_UP: The axis is rolling up.
+ *         - AON_QDEC_AXIS_DIR_DOWN: The axis is rolling down.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void aon_qdec_demo(void)
+ * {
+ *     uint16_t dir = AON_QDEC_GetAxisDirection(AON_QDEC, AON_QDEC_AXIS_X);
+ * }
+ * \endcode
+ */
+uint16_t AON_QDEC_GetAxisDirection(AON_QDEC_TypeDef *AON_QDECx, uint32_t AON_QDEC_AXIS);
+
+/**
+ * \brief  Get AON_QDEC Axis(x) count.
+ *
+ * \param[in] AON_QDECx      Selected AON_QDEC peripheral. Refer to \ref AON_QDEC_Declaration.
+ * \param[in] AON_QDEC_AXIS  Specify the AON_QDEC axis.
+ *                           This parameter can be one of the following values:
+ *                           - AON_QDEC_AXIS_X: The AON_QDEC X axis.
+ *
+ * \return The count of the axis.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void aon_qdec_demo(void)
+ * {
+ *     uint16_t counter = AON_QDEC_GetAxisCount(AON_QDEC, AON_QDEC_AXIS_X);
+ * }
+ * \endcode
+ */
+uint16_t AON_QDEC_GetAxisCount(AON_QDEC_TypeDef *AON_QDECx, uint32_t AON_QDEC_AXIS);
+
+/**
+ * \brief  Pause or resume AON_QDEC Axis x counter.
+ *
+ * \param[in] AON_QDECx      Selected AON_QDEC peripheral. Refer to \ref AON_QDEC_Declaration.
+ * \param[in] AON_QDEC_AXIS  Specify the AON_QDEC axis.
+ *                           This parameter can be one of the following values:
+ *                           \arg AON_QDEC_AXIS_X: The AON_QDEC X axis.
+ * \param[in] NewState       New state of the specified AON_QDEC Axis.
+ *                           This parameter can be one of the following values:
+ *                           - ENABLE: Pause the X-axis of the AON_QDEC counter.
+ *                           - DISABLE: Resume the X-axis of the AON_QDEC counter.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void aon_qdec_demo(void)
+ * {
+ *     AON_QDEC_CounterPauseCmd(AON_QDEC, AON_QDEC_AXIS_X, ENABLE);
+ * }
+ * \endcode
+ */
+void AON_QDEC_CounterPauseCmd(AON_QDEC_TypeDef *AON_QDECx, uint32_t AON_QDEC_AXIS,
+                              FunctionalState NewState);
+
+/** End of AON_QDEC_Exported_Functions
+  * \}
+  */
+
+/** End of AON_QDEC
+  * \}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RTL_AON_QDEC_H */
+
+
+
diff --git a/bee/drivers/qdec/src/device/rtl87x2g/rtl_aon_qdec_def.h b/bee/drivers/qdec/src/device/rtl87x2g/rtl_aon_qdec_def.h
new file mode 100644
index 00000000..8bf4adf7
--- /dev/null
+++ b/bee/drivers/qdec/src/device/rtl87x2g/rtl_aon_qdec_def.h
@@ -0,0 +1,168 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef RTL_AON_QDEC_DEF_H
+#define RTL_AON_QDEC_DEF_H
+
+#include "utils/rtl_utils.h"
+#include "address_map.h"
+
+#ifdef  __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/*============================================================================*
+ *                         AON QDEC Registers Memory Map
+ *============================================================================*/
+typedef struct
+{
+    __IO uint32_t AON_QDEC_CONFIG;           /*!< 0x00 */
+    __I  uint32_t AON_QDEC_SR_X;             /*!< 0x04 */
+    __IO uint32_t AON_QDEC_INT_CLR;          /*!< 0x08 */
+} AON_QDEC_TypeDef;
+
+/*============================================================================*
+ *                         AON QDEC Declaration
+ *============================================================================*/
+/** \defgroup AON_QDEC    AON_QDEC
+  * \brief
+  * \{
+  */
+
+/** \defgroup AON_QDEC_Exported_Constants AON_QDEC Exported Constants
+  * \brief
+  * \{
+  */
+
+/** \defgroup AON_QDEC_Declaration AON_QDEC Declaration
+  * \{
+  * \ingroup  AON_QDEC_Exported_Constants
+  */
+#define AON_QDEC      ((AON_QDEC_TypeDef *)  QUAD_DECODER_REG_BASE)   //!< AON_QDEC base address.
+
+#define IS_AON_QDEC_PERIPH(PERIPH)  ((PERIPH) == AON_QDEC) //!< Check if the input parameter is valid.
+
+/** End of AON_QDEC_Declaration
+  * \}
+  */
+
+/** End of AON_QDEC_Exported_Constants
+  * \}
+  */
+
+/** End of AON_QDEC
+  * \}
+  */
+/*============================================================================*
+ *                         AON QDEC Registers and Field Descriptions
+ *============================================================================*/
+/* 0x00
+   1:0     R/W    x_initial_phase         2'h0
+   2       R/W    x_set_initial_phase     1'h0
+   3       R/W    x_cnt_pause             1'h0
+   4       R/W    x_cnt_scale             1'h0
+   5       R/W    x_illegal_int_en        1'h0
+   6       R/W    x_cnt_int_en            1'h0
+   7       R/W    illegal_int_mask        1'h1
+   8       R/W    cnt_int_mask            1'h1
+   21:9    R/W    x_debounce_cnt          13'h0
+   22      R/W    x_debounce_en           1'h0
+   23      R/W    x_wake_aon_mask         1'b1
+   24      R/W    x_int_mask              1'b1
+   28:25   R/W    reg_config_dummy1       4'b0
+   29      R/W    x_rst                   1'b0
+   30      R/WAC  x_fsm_en                1'h0
+   31      R/W    x_axis_en               1'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t x_initial_phase: 2;
+        uint32_t x_set_initial_phase: 1;
+        uint32_t x_cnt_pause: 1;
+        uint32_t x_cnt_scale: 1;
+        uint32_t x_illegal_int_en: 1;
+        uint32_t x_cnt_int_en: 1;
+        uint32_t illegal_int_mask: 1;
+        uint32_t cnt_int_mask: 1;
+        uint32_t x_debounce_cnt: 13;
+        uint32_t x_debounce_en: 1;
+        uint32_t x_wake_aon_mask: 1;
+        uint32_t x_int_mask: 1;
+        uint32_t reg_config_dummy1: 4;
+        uint32_t x_rst: 1;
+        uint32_t x_fsm_en: 1;
+        uint32_t x_axis_en: 1;
+    } b;
+} AON_QDEC_CONFIG_TypeDef;
+
+
+
+/* 0x04
+   15:0    R      acc_cnt                 16'h0
+   16      R/W1C  cnt_of_flg              1'h0
+   17      R/W1C  cnt_uf_flg              1'h0
+   18      R/W1C  cnt_int_sta             1'h0
+   19      R/W1C  illegal_int_sta         1'h0
+   20      R      cnt_dir                 1'h0
+   21      R/W    reg_sr_x_dummy          1'h0
+   23:22   R      debug_state_x           2'h0
+   31:24   R      debug_illegal_counter_x 8'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        const  uint32_t acc_cnt: 16;
+        uint32_t cnt_of_flg: 1;
+        uint32_t cnt_uf_flg: 1;
+        uint32_t cnt_int_sta: 1;
+        uint32_t illegal_int_sta: 1;
+        const  uint32_t cnt_dir: 1;
+        uint32_t reserved_0: 1;
+        const  uint32_t debug_state_x: 2;
+        const  uint32_t debug_illegal_counter_x: 8;
+    } b;
+} AON_QDEC_SR_X_TypeDef;
+
+
+
+/* 0x08
+   0       W1C    acc_cnt_clr                 1'h0
+   1       W1C    cnt_int_clr                 1'h0
+   2       W1C    of_flg_clr                  1'h0
+   3       W1C    uf_flg_clr                  1'h0
+   4       W1C    illegal_int_clr             1'h0
+   5       W1C    illegal_cnt_clr             1'h0
+   31:6    R/W    reserved31_6                26'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t acc_cnt_clr: 1;
+        uint32_t cnt_int_clr: 1;
+        uint32_t of_flg_clr: 1;
+        uint32_t uf_flg_clr: 1;
+        uint32_t illegal_int_clr: 1;
+        uint32_t illegal_cnt_clr: 1;
+        uint32_t reserved_0: 26;
+    } b;
+} AON_QDEC_INT_CLR_TypeDef;
+
+
+#ifdef  __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* RTL_AON_QDEC_DEF_H */
diff --git a/bee/drivers/qdec/src/device/rtl87x2j/rtl87x2j_lpqdec.c b/bee/drivers/qdec/src/device/rtl87x2j/rtl87x2j_lpqdec.c
new file mode 100644
index 00000000..302b54e6
--- /dev/null
+++ b/bee/drivers/qdec/src/device/rtl87x2j/rtl87x2j_lpqdec.c
@@ -0,0 +1,58 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *                           Header Files
+ *============================================================================*/
+#include "rtl_lpqdec.h"
+#include "rtl_rcc.h"
+
+/*============================================================================*
+ *                           Private Defines
+ *============================================================================*/
+
+/*============================================================================*
+ *                           Public Functions
+ *============================================================================*/
+/**
+  * \brief  Get LPQDEC X-Axis direction.
+  * \param  LPQDECx: Select the LPQDEC peripheral. \ref LPQDEC_Declaration.
+  * \param  LPQDEC_AXIS: Specifies the LPQDEC axis.
+  *         This parameter parameter can be one of the following values:
+  *         \arg  LPQDEC_AXIS_X: The LPQDEC X axis.
+  * \return The direction of the axis. This parameter parameter can be one of the following values:
+  *         \retval LPQDEC_AXIS_DIR_UP: The axis is rolling up.
+  *         \retval LPQDEC_AXIS_DIR_DOWN: The axis is rolling down.
+  */
+bool LPQDEC_GetAxisDirection(LPQDEC_TypeDef *LPQDECx, uint32_t LPQDEC_AXIS)
+{
+    /* Check the parameters */
+    assert_param(IS_LPQDEC_PERIPH(LPQDECx));
+    assert_param(IS_LPQDEC_AXIS_DIR(LPQDEC_AXIS));
+
+    LPQDEC_SR_1_X_TypeDef lpqdec_sr1x = {.d32 = LPQDECx->LPQDEC_SR_1_X};
+    return lpqdec_sr1x.b.cnt_dir;
+}
+
+/**
+  * \brief  Get current state of phase.
+  * \param  LPQDECx: Select the LPQDEC peripheral. \ref LPQDEC_Declaration.
+  * \return The current state of phase. \ref LPQDECPhase_TypeDef
+  */
+LPQDECPhase_TypeDef LPQDEC_GetPhaseState(LPQDEC_TypeDef *LPQDECx)
+{
+    /* Check the parameters */
+    assert_param(IS_LPQDEC_PERIPH(LPQDECx));
+
+    LPQDEC_SR_1_X_TypeDef lpqdec_sr_1 = {.d32 = LPQDECx->LPQDEC_SR_1_X};
+    LPQDECPhase_TypeDef phase = LPQDEC_PHASE_MODE0;
+
+    phase = lpqdec_sr_1.b.pha_sta | (lpqdec_sr_1.b.phb_sta << 1);
+
+    return phase;
+}
+
+
diff --git a/bee/drivers/qdec/src/device/rtl87x2j/rtl_lpqdec_def.h b/bee/drivers/qdec/src/device/rtl87x2j/rtl_lpqdec_def.h
new file mode 100644
index 00000000..1c2c5b72
--- /dev/null
+++ b/bee/drivers/qdec/src/device/rtl87x2j/rtl_lpqdec_def.h
@@ -0,0 +1,243 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef RTL_LPQDEC_DEF_H
+#define RTL_LPQDEC_DEF_H
+
+#include "utils/rtl_utils.h"
+#include "address_map.h"
+#include "aon_reg.h"
+
+#ifdef  __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/*============================================================================*
+ *                          LPQDEC Defines
+ *============================================================================*/
+#define LPQDEC_SUPPORT_LED_FUNCTION                         (1)
+#define LPQDEC_SUPPORT_CLK_SRC_DIV                          (1)
+
+/*============================================================================*
+ *                          LPQDEC Registers Memory Map
+ *============================================================================*/
+typedef struct
+{
+    __IO uint32_t LPQDEC_DIV;                   /*!< 0x00 */
+    __IO uint32_t LPQDEC_CONFIG;                /*!< 0x04 */
+    __I  uint32_t LPQDEC_SR_1_X;                /*!< 0x08 */
+    __I  uint32_t LPQDEC_SR_2_X;                /*!< 0x0C */
+    __IO uint32_t LPQDEC_INT_CLR;               /*!< 0x10 */
+    __I  uint32_t LPQDEC_VERSION;               /*!< 0x14 */
+    __IO uint32_t LPQDEC_LED_CTRL;              /*!< 0x18 */
+    __IO uint32_t LPQDEC_QACTIVE_CTRL;          /*!< 0x1C */
+} LPQDEC_TypeDef;
+
+/*============================================================================*
+ *                          LPQDEC Declaration
+ *============================================================================*/
+#define LPQDEC_REG_BASE           (SYSON_BASE + AON_REG_LPQDEC_X_DIV)
+#define LPQDEC                    ((LPQDEC_TypeDef *) LPQDEC_REG_BASE)
+
+#define IS_LPQDEC_PERIPH(PERIPH)  ((PERIPH) == LPQDEC)
+
+/*============================================================================*
+ *                          LPQDEC Private Types
+ *============================================================================*/
+
+/*============================================================================*
+ *                          LPQDEC Registers and Field Descriptions
+ *============================================================================*/
+/* 0x00
+   3:0     R/W    scan_div                        4'h0
+   31:4    R      reg_div_reserved31_4            28'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t scan_div: 4;
+        const uint32_t reg_div_reserved31_4: 28;
+    } b;
+} LPQDEC_DIV_TypeDef;
+
+
+/* 0x04
+   1:0     R/W    x_initial_phase                 2'h0
+   2       R/W    x_set_inital_phase              1'h0
+   3       R/W    x_cnt_pause                     1'h0
+   4       R/W    x_cnt_scale                     1'h0
+   5       R/W    x_illegal_int_en                1'h0
+   6       R/W    x_cnt_int_en                    1'h0
+   7       R/W    illegal_int_mask                1'h1
+   8       R/W    cnt_int_mask                    1'h1
+   21:9    R/W    x_debounce_cnt                  13'h0
+   22      R/W    x_debounce_en                   1'h0
+   23      R/W    x_wake_aon_mask                 1'b1
+   24      R/W    x_int_mask                      1'b1
+   28:25   R      reg_config_reserved28_25        4'b0
+   29      R/W    x_rst                           1'b0
+   30      R/WAC  x_fsm_en                        1'h0
+   31      R/W    x_axis_en                       1'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t x_initial_phase: 2;
+        uint32_t x_set_inital_phase: 1;
+        uint32_t x_cnt_pause: 1;
+        uint32_t x_cnt_scale: 1;
+        uint32_t x_illegal_int_en: 1;
+        uint32_t x_cnt_int_en: 1;
+        uint32_t illegal_int_mask: 1;
+        uint32_t cnt_int_mask: 1;
+        uint32_t x_debounce_cnt: 13;
+        uint32_t x_debounce_en: 1;
+        uint32_t x_wake_aon_mask: 1;
+        uint32_t x_int_mask: 1;
+        const uint32_t reg_config_reserved28_25: 4;
+        uint32_t x_rst: 1;
+        uint32_t x_fsm_en: 1;
+        uint32_t x_axis_en: 1;
+    } b;
+} LPQDEC_CONFIG_TypeDef;
+
+
+/* 0x08
+   15:0    R      reg_sr_1_x_reserved15_0         16'h0
+   16      R      cnt_of_flg                      1'h0
+   17      R      cnt_uf_flg                      1'h0
+   18      R      cnt_int_sta                     1'h0
+   19      R      illegal_int_sta                 1'h0
+   20      R      cnt_dir                         1'h0
+   21      R      pha_sta                         1'h0
+   22      R      phb_sta                         1'h0
+   31:23   R      reg_sr_1_x_reserved31_23        9'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t reg_sr_1_x_reserved15_0: 16;
+        const uint32_t cnt_of_flg: 1;
+        const uint32_t cnt_uf_flg: 1;
+        const uint32_t cnt_int_sta: 1;
+        const uint32_t illegal_int_sta: 1;
+        const uint32_t cnt_dir: 1;
+        const uint32_t pha_sta: 1;
+        const uint32_t phb_sta: 1;
+        const uint32_t reg_sr_1_x_reserved31_23: 9;
+    } b;
+} LPQDEC_SR_1_X_TypeDef;
+
+
+/* 0x0C
+   15:0    R      acc_cnt                         16'h0
+   21:16   R      reg_sr_2_x_reserved21           6'h0
+   23:22   R      debug_state_x                   2'h0
+   31:24   R      debug_illegal_counter_x         8'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t acc_cnt: 16;
+        const uint32_t reg_sr_2_x_reserved21: 6;
+        const uint32_t debug_state_x: 2;
+        const uint32_t debug_illegal_counter_x: 8;
+    } b;
+} LPQDEC_SR_2_X_TypeDef;
+
+
+/* 0x10
+   0       R/WAC  acc_cnt_clr                     1'h0
+   1       R/WAC  cnt_int_clr                     1'h0
+   2       R/WAC  of_flg_clr                      1'h0
+   3       R/WAC  uf_flg_clr                      1'h0
+   4       R/WAC  illegal_int_clr                 1'h0
+   5       R/WAC  illegal_cnt_clr                 1'h0
+   31:6    R      reg_int_clr_reserved31_6        26'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t acc_cnt_clr: 1;
+        uint32_t cnt_int_clr: 1;
+        uint32_t of_flg_clr: 1;
+        uint32_t uf_flg_clr: 1;
+        uint32_t illegal_int_clr: 1;
+        uint32_t illegal_cnt_clr: 1;
+        const uint32_t reg_int_clr_reserved31_6: 26;
+    } b;
+} LPQDEC_INT_CLR_TypeDef;
+
+
+/* 0x14
+   31:0    R      qdec_version                    32'h20240329
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t qdec_version: 32;
+    } b;
+} LPQDEC_VERSION_TypeDef;
+
+
+/* 0x18
+   0       R/W    led_en                          1'h0
+   1       R/W    ledpol                          1'h0
+   4:2     R/W    ledpre                          3'h0
+   31:5    R      reg_led_ctrl_reserved31_5       27'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t led_en: 1;
+        uint32_t ledpol: 1;
+        uint32_t ledpre: 3;
+        const uint32_t reg_led_ctrl_reserved31_5: 27;
+    } b;
+} LPQDEC_LED_CTRL_TypeDef;
+
+
+/* 0x1C
+   0       R/W    lpqdec_qact_sclk_man_data       1'h0
+   1       R/W    lpqdec_qact_sclk_man_en         1'h0
+   2       R/W    lpqdec_qact_pclk_man_data       1'h0
+   3       R/W    lpqdec_qact_pclk_man_en         1'h0
+   31:4    R      reg_qactive_ctrl_reserved31_4   28'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t lpqdec_qact_sclk_man_data: 1;
+        uint32_t lpqdec_qact_sclk_man_en: 1;
+        uint32_t lpqdec_qact_pclk_man_data: 1;
+        uint32_t lpqdec_qact_pclk_man_en: 1;
+        const uint32_t reg_qactive_ctrl_reserved31_4: 28;
+    } b;
+} LPQDEC_QACTIVE_CTRL_TypeDef;
+
+
+
+#ifdef  __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* RTL_LPQDEC_DEF_H */
diff --git a/bee/drivers/qdec/src/device/rtl_common/CMakeLists.txt b/bee/drivers/qdec/src/device/rtl_common/CMakeLists.txt
new file mode 100644
index 00000000..3d8dd794
--- /dev/null
+++ b/bee/drivers/qdec/src/device/rtl_common/CMakeLists.txt
@@ -0,0 +1,4 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_library_sources_ifdef(CONFIG_REALTEK_BEE_LPQDEC rtl_lpqdec.c)
diff --git a/bee/drivers/qdec/src/device/rtl_common/rtl_lpqdec.c b/bee/drivers/qdec/src/device/rtl_common/rtl_lpqdec.c
new file mode 100644
index 00000000..91fe95be
--- /dev/null
+++ b/bee/drivers/qdec/src/device/rtl_common/rtl_lpqdec.c
@@ -0,0 +1,358 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *                           Header Files
+ *============================================================================*/
+#include "rtl_lpqdec.h"
+#include "utils.h"
+
+/*============================================================================*
+ *                           Private Functions
+ *============================================================================*/
+
+/*============================================================================*
+ *                           Public Functions
+ *============================================================================*/
+/**
+  * \brief  Deinitializes the LPQDEC peripheral registers to their default reset values.
+  * \param  LPQDECx: Select the LPQDEC peripheral. \ref LPQDEC_Declaration.
+  * \return None
+  */
+void LPQDEC_DeInit(LPQDEC_TypeDef *LPQDECx)
+{
+    LPQDEC_CONFIG_TypeDef lpqdec_config = {.d32 = LPQDECx->LPQDEC_CONFIG};
+    lpqdec_config.b.x_rst = 0x1;
+    LPQDECx->LPQDEC_CONFIG = lpqdec_config.d32;
+    __NOP();
+    __NOP();
+    lpqdec_config.b.x_rst = 0x0;
+    LPQDECx->LPQDEC_CONFIG = lpqdec_config.d32;
+}
+
+/**
+  * \brief  Initializes the LPQDEC peripheral according to the specified
+  *         parameters in the LPQDEC_InitStruct.
+  * \param  LPQDECx: Select the LPQDEC peripheral. \ref LPQDEC_Declaration.
+  * \param  LPQDEC_InitStruct: pointer to an LPQDEC_InitStruct structure that
+  *         contains the configuration information for the specified LPQDEC peripheral.
+  * \return None
+  */
+void LPQDEC_Init(LPQDEC_TypeDef *LPQDECx, LPQDEC_InitTypeDef *LPQDEC_InitStruct)
+{
+    /* Check the parameters */
+    assert_param(IS_QDEC_PERIPH(LPQDECx));
+
+#if (LPQDEC_SUPPORT_CLK_SRC_DIV == 1)
+    LPQDEC_DIV_TypeDef lpqdec_div = {.d32 = LPQDECx->LPQDEC_DIV};
+    lpqdec_div.b.scan_div = LPQDEC_InitStruct->LPQDEC_ScanClockDiv;
+    LPQDECx->LPQDEC_DIV = lpqdec_div.d32;
+#endif
+
+    LPQDEC_CONFIG_TypeDef lpqdec_config = {.d32 = LPQDECx->LPQDEC_CONFIG};
+    lpqdec_config.b.x_fsm_en = 0x1;
+    lpqdec_config.b.x_axis_en = 0x0;
+    LPQDECx->LPQDEC_CONFIG = lpqdec_config.d32;
+    platform_delay_us(63);
+
+    /* Set Manual Initial Phase*/
+    if (LPQDEC_InitStruct->LPQDEC_ManualLoadInitPhase == ENABLE)
+    {
+        lpqdec_config.b.x_set_inital_phase = 0x1;
+        LPQDECx->LPQDEC_CONFIG = lpqdec_config.d32;
+        platform_delay_us(63);
+        lpqdec_config.b.x_initial_phase = LPQDEC_InitStruct->LPQDEC_InitPhaseX;
+        LPQDECx->LPQDEC_CONFIG = lpqdec_config.d32;
+
+        lpqdec_config.b.x_set_inital_phase = 0x0;
+        LPQDECx->LPQDEC_CONFIG = lpqdec_config.d32;
+    }
+
+    /* The max debounce cnt is 0x1FFF*/
+    if (LPQDEC_InitStruct->LPQDEC_DebounceCountX >= 0x1FFF)
+    {
+        LPQDEC_InitStruct->LPQDEC_DebounceCountX = 0x1FFF;
+    }
+    lpqdec_config.b.x_debounce_en = LPQDEC_InitStruct->LPQDEC_DebounceEnableX;
+    lpqdec_config.b.x_debounce_cnt = LPQDEC_InitStruct->LPQDEC_DebounceCountX;
+    lpqdec_config.b.x_cnt_scale = LPQDEC_InitStruct->LPQDEC_CounterScaleX;
+    LPQDECx->LPQDEC_CONFIG = lpqdec_config.d32;
+
+    /* write 1 to clear acc counter and illegal counter */
+    LPQDEC_INT_CLR_TypeDef lpqdec_clear = {.d32 = LPQDECx->LPQDEC_INT_CLR};
+    lpqdec_clear.b.acc_cnt_clr = 0x1;
+    lpqdec_clear.b.illegal_cnt_clr = 0x1;
+    LPQDECx->LPQDEC_INT_CLR = lpqdec_clear.d32;
+
+#if (LPQDEC_SUPPORT_LED_FUNCTION == 1)
+    /* Configure the optical roller function */
+    LPQDEC_LED_CTRL_TypeDef lpqdec_led = {.d32 = LPQDECx->LPQDEC_LED_CTRL};
+    lpqdec_led.b.led_en = LPQDEC_InitStruct->LPQDEC_LedEn;
+    lpqdec_led.b.ledpol = LPQDEC_InitStruct->LPQDEC_LedPolarity;
+    lpqdec_led.b.ledpre = LPQDEC_InitStruct->LPQDEC_LedPeriod;
+    LPQDECx->LPQDEC_LED_CTRL = lpqdec_led.d32;
+#endif
+
+    /* Accessing some registers requires 2T 32K delay between each access.
+       Use one delay for overlapping delays at the last access. */
+    platform_delay_us(63);
+}
+
+/**
+  * \brief  Fills each LPQDEC_InitStruct member with its default value.
+  * \param  LPQDEC_InitStruct: pointer to an LPQDEC_InitStruct structure which will be initialized.
+  * \return None
+  */
+void LPQDEC_StructInit(LPQDEC_InitTypeDef *LPQDEC_InitStruct)
+{
+#if (LPQDEC_SUPPORT_CLK_SRC_DIV == 1)
+    LPQDEC_InitStruct->LPQDEC_ScanClockDiv        = 0x0;
+#endif
+    LPQDEC_InitStruct->LPQDEC_AxisConfigX         = DISABLE;
+    LPQDEC_InitStruct->LPQDEC_ManualLoadInitPhase = DISABLE;
+    LPQDEC_InitStruct->LPQDEC_InitPhaseX          = LPQDEC_PHASE_MODE0;
+    LPQDEC_InitStruct->LPQDEC_DebounceEnableX     = DISABLE;
+    LPQDEC_InitStruct->LPQDEC_DebounceCountX      = 32 * 5; /*!< 5ms */
+    LPQDEC_InitStruct->LPQDEC_CounterScaleX       = LPQDEC_COUNTER_SCALE_1_PHASE;
+#if (LPQDEC_SUPPORT_LED_FUNCTION == 1)
+    LPQDEC_InitStruct->LPQDEC_LedEn               = DISABLE;
+    LPQDEC_InitStruct->LPQDEC_LedPolarity         = LPQDEC_LED_POLARITY_LOW;
+    LPQDEC_InitStruct->LPQDEC_LedPeriod           = LPQDEC_LED_PERIOD_0US;
+#endif
+
+    return;
+}
+
+/**
+  * \brief  Enable or disable LPQDEC Function.
+  * \param  LPQDECx: Select the LPQDEC peripheral. \ref LPQDEC_Declaration.
+  * \param  LPQDEC_AXIS: Specifies the LPQDEC axis.
+  *         This parameter can be one of the following values:
+  *         \arg QDEC_AXIS_X: The LPQDEC X axis.
+  * \param  NewState: New state of the selected LPQDEC axis.
+  *         This parameter can be one of the following values:
+  *         \arg ENABLE: Pause.
+  *         \arg DISABLE: Resume.
+  * \return None.
+  */
+void LPQDEC_Cmd(LPQDEC_TypeDef *LPQDECx, uint32_t LPQDEC_AXIS, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_LPQDEC_PERIPH(LPQDECx));
+    assert_param(IS_LPQDEC_AXIS_DIR(LPQDEC_AXIS));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    LPQDEC_CONFIG_TypeDef lpqdec_config = {.d32 = LPQDECx->LPQDEC_CONFIG};
+    lpqdec_config.b.x_axis_en = NewState;
+    LPQDECx->LPQDEC_CONFIG = lpqdec_config.d32;
+}
+
+/**
+  * \brief  Enables or disables the specified LPQDEC interrupts.
+  * \param  LPQDECx: Select the LPQDEC peripheral. \ref LPQDEC_Declaration.
+  * \param  LPQDEC_INT: Specifies the LPQDEC interrupts sources to be enabled or disabled.
+  *         This parameter can be one of the following values:
+  *         \arg LPQDEC_X_INT_NEW_DATA: The counter interrupt for X axis.
+  *         \arg LPQDEC_X_INT_ILLEGAL: The illegal interrupt for X axis.
+  * \param  NewState: New state of the specified LPQDEC interrupts.
+  *         This parameter can be: ENABLE or DISABLE.
+  * \return None
+  */
+void LPQDEC_INTConfig(LPQDEC_TypeDef *LPQDECx, uint32_t LPQDEC_INT, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_LPQDEC_PERIPH(LPQDECx));
+    assert_param(IS_LPQDEC_INT_CONFIG(LPQDEC_INT));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (NewState == ENABLE)
+    {
+        LPQDECx->LPQDEC_CONFIG |= LPQDEC_INT;
+    }
+    else
+    {
+        LPQDECx->LPQDEC_CONFIG &= ~LPQDEC_INT;
+    }
+
+    return;
+}
+
+/**
+  * \brief  Enables or disables mask the specified LPQDEC axis interrupts.
+  * \param  LPQDECx: Select the LPQDEC peripheral. \ref LPQDEC_Declaration.
+  * \param  LPQDEC_AXIS: Specifies the LPQDEC axis.
+  *         This parameter can be one or logical OR of the following values:
+  *         \arg LPQDEC_X_INT_MASK_NEW_DATA: The LPQDEC CNT interrupt mask.
+  *         \arg LPQDEC_X_INT_MASK_ILLEGAL: The LPQDEC illegal interrupt mask.
+  * \param  NewState: New state of the specified LPQDEC interrupts mask.
+  *         This parameter can be: ENABLE or DISABLE.
+  * \return None
+  */
+void LPQDEC_MaskINTConfig(LPQDEC_TypeDef *LPQDECx, uint32_t LPQDEC_MASK, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_LPQDEC_PERIPH(LPQDECx));
+    assert_param(IS_LPQDEC_INT_MASK_CONFIG(LPQDEC_AXIS));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (NewState == ENABLE)
+    {
+        LPQDECx->LPQDEC_CONFIG |= LPQDEC_MASK;
+    }
+    else
+    {
+        LPQDECx->LPQDEC_CONFIG &= ~LPQDEC_MASK;
+    }
+
+    return;
+}
+
+/**
+  * \brief  Enables or disables interrupt signal to CPU NVIC.
+  * \param  LPQDECx: Select the LPQDEC peripheral. \ref LPQDEC_Declaration.
+  * \param  NewState: New state of the specified LPQDEC interrupts mask.
+  *         This parameter can be: ENABLE or DISABLE.
+  * \return None
+  */
+void LPQDEC_NVICCmd(LPQDEC_TypeDef *LPQDECx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_LPQDEC_PERIPH(LPQDECx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    LPQDEC_CONFIG_TypeDef lpqdec_config = {.d32 = LPQDECx->LPQDEC_CONFIG};
+    lpqdec_config.b.x_int_mask = !NewState;
+    LPQDECx->LPQDEC_CONFIG = lpqdec_config.d32;
+}
+
+/**
+  * \brief  Enables or disables wakeup system.
+  * \param  LPQDECx: Select the LPQDEC peripheral. \ref LPQDEC_Declaration.
+  * \param  NewState: New state of the specified LPQDEC interrupts mask.
+  *         This parameter can be: ENABLE or DISABLE.
+  * \return None
+  */
+void LPQDEC_WakeUpCmd(LPQDEC_TypeDef *LPQDECx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_LPQDEC_PERIPH(LPQDECx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    LPQDEC_CONFIG_TypeDef lpqdec_config = {.d32 = LPQDECx->LPQDEC_CONFIG};
+    lpqdec_config.b.x_wake_aon_mask = !NewState;
+    LPQDECx->LPQDEC_CONFIG = lpqdec_config.d32;
+}
+
+/**
+  * \brief  Checks whether the specified LPQDEC flag is set or not.
+  * \param  LPQDECx: Select the LPQDEC peripheral. \ref LPQDEC_Declaration.
+  * \param  LPQDEC_FLAG: specifies the flag to check.
+  *         This parameter can be one of the following values:
+  *         \arg LPQDEC_X_INT_FLAG_NEW_COUNT: Status of the counter interrupt for X axis.
+  *         \arg LPQDEC_X_INT_FLAG_ILLEGAL: Status of the illegal interrupt for X axis.
+  *         \arg LPQDEC_X_INT_FLAG_OVERFLOW: The overflow flag for x-axis accumulation counter.
+  *         \arg LPQDEC_X_INT_FLAG_UNDERFLOW: The underflow flag for x-axis accumulation counter.
+  * \return The New state of LPQDEC_FLAG (SET or RESET).
+  */
+FlagStatus LPQDEC_GetFlagState(LPQDEC_TypeDef *LPQDECx, uint32_t LPQDEC_FLAG)
+{
+    /* Check the parameters */
+    assert_param(IS_LPQDEC_PERIPH(LPQDECx));
+    assert_param(IS_LPQDEC_CLR_INT_STATUS(LPQDEC_FLAG));
+
+    if ((LPQDECx->LPQDEC_SR_1_X & LPQDEC_FLAG) != (uint32_t)RESET)
+    {
+        return SET;
+    }
+    return RESET;
+}
+
+/**
+  * \brief  Clear LPQDEC interrupt pending bit.
+  * \param  LPQDECx: Select the LPQDEC peripheral. \ref LPQDEC_Declaration.
+  * \param  LPQDEC_FLAG: Specifies the flag to clear.
+  *         This parameter parameter can be one of the following values:
+  *         \arg LPQDEC_X_INT_CLEAR_ILLEGAL: The illegal interrupt for X axis.
+  *         \arg LPQDEC_X_INT_CLEAR_UNDERFLOW: The underflow flag for x-axis accumulation counter.
+  *         \arg LPQDEC_X_INT_CLEAR_OVERFLOW: The overflow flag for x-axis accumulation counter.
+  *         \arg LPQDEC_X_INT_CLEAR_NEW_DATA: The counter interrupt for X axis.
+  * \return None.
+  */
+void LPQDEC_ClearINTPendingBit(LPQDEC_TypeDef *LPQDECx, uint32_t LPQDEC_CLEAR)
+{
+    /* Check the parameters */
+    assert_param(IS_LPQDEC_PERIPH(LPQDECx));
+    assert_param(IS_LPQDEC_INT_CLEAR_CONFIG(LPQDEC_CLEAR));
+
+    LPQDECx->LPQDEC_INT_CLR |= LPQDEC_CLEAR;
+
+    return;
+}
+
+/**
+  * \brief  Clear LPQDEC counter.
+  * \param  LPQDECx: Select the LPQDEC peripheral. \ref LPQDEC_Declaration.
+  * \param  LPQDEC_CLEAR: Specifies the counter to clear.
+  *         This parameter parameter can be one of the following values:
+  *         \arg LPQDEC_X_CLEAR_ILLEGAL_COUNTER: The illegal counter for X axis.
+  *         \arg LPQDEC_X_CLEAR_ACC_COUNTER: The acc counter for X axis.
+  * \return None.
+  */
+void LPQDEC_ClearCounter(LPQDEC_TypeDef *LPQDECx, uint32_t LPQDEC_CLEAR)
+{
+    /* Check the parameters */
+    assert_param(IS_LPQDEC_PERIPH(LPQDECx));
+    assert_param(IS_LPQDEC_CNT_CLEAR_CONFIG(LPQDEC_CLEAR));
+
+    LPQDECx->LPQDEC_INT_CLR |= LPQDEC_CLEAR;
+
+    return;
+}
+
+/**
+  * \brief  Get LPQDEC X-Axis count.
+  * \param  LPQDECx: Select the LPQDEC peripheral. \ref LPQDEC_Declaration.
+  * \param  LPQDEC_AXIS: Specifies the LPQDEC axis.
+  *         This parameter parameter can be one of the following values:
+  *         \arg LPQDEC_AXIS_X: The LPQDEC X axis.
+  * \return The count of the axis.
+  */
+uint16_t LPQDEC_GetAxisCount(LPQDEC_TypeDef *LPQDECx, uint32_t LPQDEC_AXIS)
+{
+    /* Check the parameters */
+    assert_param(IS_LPQDEC_PERIPH(LPQDECx));
+    assert_param(IS_LPQDEC_AXIS_DIR(LPQDEC_AXIS));
+
+    LPQDEC_SR_2_X_TypeDef lpqdec_sr2x = {.d32 = LPQDECx->LPQDEC_SR_2_X};
+    return lpqdec_sr2x.b.acc_cnt;
+}
+
+/**
+  * \brief  Pause or resume LPQDEC Axis x.
+  * \param  LPQDECx: Select the LPQDEC peripheral. \ref LPQDEC_Declaration.
+  * \param  LPQDEC_AXIS: Specifies the LPQDEC axis.
+  *         This parameter parameter can be one of the following values:
+  *         \arg LPQDEC_AXIS_X: The LPQDEC X axis.
+  * \param  NewState: New state of the specified LPQDEC Axis.
+  *         This parameter parameter can be one of the following values:
+  *         \arg ENABLE: Pause.
+  *         \arg DISABLE: Resume.
+  * \return None.
+  */
+void LPQDEC_CounterPauseCmd(LPQDEC_TypeDef *LPQDECx, uint32_t LPQDEC_AXIS, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_LPQDEC_PERIPH(LPQDECx));
+    assert_param(IS_LPQDEC_AXIS_DIR(LPQDEC_AXIS));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    LPQDEC_CONFIG_TypeDef lpqdec_config = {.d32 = LPQDECx->LPQDEC_CONFIG};
+    lpqdec_config.b.x_cnt_pause = NewState;
+    LPQDECx->LPQDEC_CONFIG = lpqdec_config.d32;
+}
+
+
+
diff --git a/bee/drivers/rcc/CMakeLists.txt b/bee/drivers/rcc/CMakeLists.txt
new file mode 100644
index 00000000..1475b731
--- /dev/null
+++ b/bee/drivers/rcc/CMakeLists.txt
@@ -0,0 +1,8 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+if(CONFIG_REALTEK_BEE_COMMON_DRIVER)
+    zephyr_include_directories(inc)
+endif()
+
+add_subdirectory_ifdef(CONFIG_REALTEK_BEE_RCC src)
diff --git a/bee/drivers/rcc/Kconfig b/bee/drivers/rcc/Kconfig
new file mode 100644
index 00000000..1a834e97
--- /dev/null
+++ b/bee/drivers/rcc/Kconfig
@@ -0,0 +1,8 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config REALTEK_BEE_RCC
+	bool "Realtek Bee RCC driver"
+	default n
+	help
+	  This option enables the RCC driver for Realtek Bee.
diff --git a/bee/drivers/rcc/inc/rtl_rcc.h b/bee/drivers/rcc/inc/rtl_rcc.h
new file mode 100644
index 00000000..03172752
--- /dev/null
+++ b/bee/drivers/rcc/inc/rtl_rcc.h
@@ -0,0 +1,200 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *               Define to prevent recursive inclusion
+ *============================================================================*/
+#ifndef RTL_RCC_H
+#define RTL_RCC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*============================================================================*
+ *                        Header Files
+ *============================================================================*/
+#include "utils/rtl_utils.h"
+#if defined (CONFIG_SOC_SERIES_RTL87X2G)
+#include "rcc/src/device/rtl87x2g/rtl_rcc_def.h"
+#elif defined (CONFIG_SOC_SERIES_RTL87X2J)
+#include "rcc/src/device/rtl87x2j/rtl_rcc_def.h"
+#elif defined (CONFIG_SOC_SERIES_RTL87X3D)
+#include "rcc/src/device/rtl87x3d/rtl_rcc_def.h"
+#elif defined (CONFIG_SOC_SERIES_RTL87X3E)
+#include "rcc/src/device/rtl87x3e/rtl_rcc_def.h"
+#elif defined (CONFIG_SOC_SERIES_RTL87X3EU)
+#include "rcc/src/device/rtl87x3eu/rtl_rcc_def.h"
+#elif defined (CONFIG_SOC_SERIES_RTL87X3J)
+#include "rcc/src/device/rtl87x3j/rtl_rcc_def.h"
+#endif
+
+/** \defgroup RCC         RCC
+  * \brief
+  * \{
+  */
+
+/*============================================================================*
+ *                         Constants
+ *============================================================================*/
+/** \defgroup RCC_Exported_Constants RCC Exported Constants
+  * \brief
+  * \{
+  */
+
+/**
+ * \defgroup    Clock_Divider Clock Divider
+ * \{
+ * \ingroup     RCC_Exported_Constants
+ */
+typedef enum
+{
+    CLOCK_DIV_1,
+    CLOCK_DIV_2,
+    CLOCK_DIV_4,
+    CLOCK_DIV_8,
+    CLOCK_DIV_16,
+    CLOCK_DIV_32,
+    CLOCK_DIV_40,
+    CLOCK_DIV_64,
+} RCCClockDiv_Typedef;
+
+#define IS_DIV(DIV)   (((DIV) == CLOCK_DIV_1) || \
+                       ((DIV) == CLOCK_DIV_2) || \
+                       ((DIV) == CLOCK_DIV_4) || \
+                       ((DIV) == CLOCK_DIV_8) || \
+                       ((DIV) == CLOCK_DIV_16) || \
+                       ((DIV) == CLOCK_DIV_32) || \
+                       ((DIV) == CLOCK_DIV_40) || \
+                       ((DIV) == CLOCK_DIV_64))
+
+/** End of Clock_Divider
+  * \}
+  */
+
+/** End of RCC_Exported_Constants
+  * \}
+  */
+
+/*============================================================================*
+ *                         Functions
+ *============================================================================*/
+/** \defgroup RCC_Exported_Functions RCC Exported Functions
+  * \brief
+  * \{
+  */
+
+#if (RCC_SUPPORT_AUTO_CLOCK == 0)
+/**
+ * \brief  Enable or disable the APB peripheral clock.
+ *
+ * \param[in] APBPeriph: Specifies the APB peripheral to gates its clock.
+ *            This parameter can refer to \ref APB_Peripheral_Func.
+ * \param[in] APBPeriph_Clock: Specifies the APB peripheral clock config.
+ *            This parameter can refer to \ref APB_Peripheral_Clock (must be the same with APBPeriph).
+ * \param[in] NewState: New state of the specified peripheral clock.
+ *            This parameter can be one of the following values:
+ *            \arg ENABLE: Enable the specified peripheral clock.
+ *            \arg DISABLE: Disable the specified peripheral clock.
+ *
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_spi_init(void)
+ * {
+ *     RCC_PeriphClockCmd(APBPeriph_SPI0, APBPeriph_SPI0_CLOCK, ENABLE);
+ * }
+ * \endcode
+ */
+void RCC_PeriphClockCmd(uint32_t APBPeriph, uint32_t APBPeriph_Clock, FunctionalState NewState);
+#endif
+
+/**
+ * \brief  Enable or disable the APB peripheral.
+ *
+ * \param[in] APBPeriph: Specifies the APB peripheral.
+ *            This parameter can refer APB Peripheral.
+ * #if RCC_SUPPORT_PERIPHCLOCKCONFIG_API_MORE_PARAMS
+ * \param[in] APBPeriph_Clock: specifies the APB peripheral clock config.
+ *            This parameter can refer to APB Peripheral Clock (must be the same with APBPeriph).
+ * #endif
+ * \param[in] NewState: New state of the specified peripheral.
+ *            This parameter can be one of the following values:
+ *            \arg ENABLE: Enable the specified peripheral.
+ *            \arg DISABLE: Disable the specified peripheral.
+ *
+ * \return  None.
+ */
+void RCC_ClockCmd(uint32_t APBPeriph, FunctionalState NewState);
+
+#if (RCC_SUPPORT_AUTO_CLOCK == 0)
+/**
+ * \brief  Enable or disable the specified APB peripheral clock.
+ *
+ * \param[in] APBPeriph: specifies the APB peripheral to gates its clock.
+ *            This parameter can refer APB Peripheral.
+ * #if RCC_SUPPORT_PERIPHCLOCKCONFIG_API_MORE_PARAMS
+ * \param[in] APBPeriph_Clock: Specifies the APB peripheral clock config.
+ *            This parameter can refer to APB Peripheral Clock (must be the same with APBPeriph).
+ * #endif
+ * \param[in] NewState: New state of the specified APB peripheral clock.
+ *            This parameter can be one of the following values:
+ *            \arg ENABLE: Enable the specified APB peripheral clock.
+ *            \arg DISABLE: Disable the specified APB peripheral clock.
+ *
+ * \return None
+ */
+void RCC_PeriClockConfig(uint32_t APBPeriph_Clock, FunctionalState NewState);
+#endif
+
+#if (RCC_SUPPORT_CLOCKGATECMD_API == 1)
+/**
+ * rtl876x_rcc.h
+ *
+ * \brief  Enable or disable the specified RCC Clock Source Gating.
+ *
+ * \param[in] ClockGate: Specifies the clock source to gate.
+ *            This parameter can be one of the following values:
+ *            \arg CLOCK_GATE_5M: 5M clock source for adc and keyscan.
+ *            \arg CLOCK_GATE_10M: 10M clock source for bluewiz.
+ *            \arg CLOCK_GATE_20M: 20M clock source for 2wssi and qdec.
+ * \param[in] NewState: New state of the specified RCC Clock Source.
+ *            This parameter can be one of the following values:
+ *            \arg ENABLE: Enable the specified RCC Clock Source.
+ *            \arg DISABLE: Disable the specified RCC Clock Source.
+ *
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_xx_init(void)
+ * {
+ *     RCC_ClockGateCmd(CLOCK_GATE_5M, ENABLE);
+ * }
+ * \endcode
+ */
+extern void RCC_ClockGateCmd(uint32_t ClockGate, FunctionalState NewState);
+#endif
+
+/** End of RCC_Exported_Functions
+  * \}
+  */
+
+/** End of RCC
+  * \}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RTL_RCC_H */
+
+
+
diff --git a/bee/drivers/rcc/src/CMakeLists.txt b/bee/drivers/rcc/src/CMakeLists.txt
new file mode 100644
index 00000000..dd5e359a
--- /dev/null
+++ b/bee/drivers/rcc/src/CMakeLists.txt
@@ -0,0 +1,4 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+add_subdirectory(device)
diff --git a/bee/drivers/rcc/src/device/CMakeLists.txt b/bee/drivers/rcc/src/device/CMakeLists.txt
new file mode 100644
index 00000000..034df6a1
--- /dev/null
+++ b/bee/drivers/rcc/src/device/CMakeLists.txt
@@ -0,0 +1,6 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+add_soc_series_subdir(rtl8752h)
+add_soc_series_subdir(rtl87x2g)
+add_soc_series_subdir(rtl87x2j)
diff --git a/bee/drivers/rcc/src/device/rtl8752h/rtl876x_rcc.c b/bee/drivers/rcc/src/device/rtl8752h/rtl876x_rcc.c
new file mode 100644
index 00000000..ed9729fc
--- /dev/null
+++ b/bee/drivers/rcc/src/device/rtl8752h/rtl876x_rcc.c
@@ -0,0 +1,558 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "rtl876x.h"
+#include "rtl876x_bitfields.h"
+#include "rtl876x_rcc.h"
+
+/**
+  * @brief  Enables or disables the APB peripheral clock.
+  * @param  APBPeriph: specifies the APB peripheral to gates its clock.
+  *   This parameter can be one of the following values:
+  *     @arg APBPeriph_TIMER
+  *     @arg APBPeriph_ENHTIMER
+  *     @arg APBPeriph_FLASH
+  *     @arg APBPeriph_GDMA
+  *     @arg APBPeriph_PKE
+  *     @arg APBPeriph_SHA256
+  *     @arg APBPeriph_FLASH1
+  *     @arg APBPeriph_FLH_SEC
+  *     @arg APBPeriph_MODEM
+  *     @arg APBPeriph_BLUEWIZ
+  *     @arg APBPeriph_ZIGBEE
+  *     @arg APBPeriph_IF8080
+  *     @arg APBPeriph_SPI2W
+  *     @arg APBPeriph_KEYSCAN
+  *     @arg APBPeriph_QDEC
+  *     @arg APBPeriph_I2C1
+  *     @arg APBPeriph_I2C0
+  *     @arg APBPeriph_IR
+  *     @arg APBPeriph_SPI1
+  *     @arg APBPeriph_SPI0
+  *     @arg APBPeriph_UART0
+  *     @arg APBPeriph_UART1
+  *     @arg APBPeriph_UART2
+  *     @arg APBPeriph_GPIO
+  *     @arg APBPeriph_ADC
+  *     @arg APBPeriph_I2S0
+  *     @arg APBPeriph_I2S1
+  *     @arg APBPeriph_CODEC
+  * @param  APBPeriph_Clock: specifies the APB peripheral clock config.
+  *   This parameter can be one of the following values(must be the same with APBPeriph):
+  *     @arg APBPeriph_TIMER_CLOCK
+  *     @arg APBPeriph_ENHTIMER_CLOCK
+  *     @arg APBPeriph_FLASH_CLOCK
+  *     @arg APBPeriph_GDMA_CLOCK
+  *     @arg APBPeriph_PKE_CLOCK
+  *     @arg APBPeriph_SHA256_CLOCK
+  *     @arg APBPeriph_FLASH1_CLOCK
+  *     @arg APBPeriph_FLH_SEC_CLOCK
+  *     @arg APBPeriph_MODEM_CLOCK
+  *     @arg APBPeriph_BLUEWIZ_CLOCK
+  *     @arg APBPeriph_ZIGBEE_CLOCK
+  *     @arg APBPeriph_IF8080_CLOCK
+  *     @arg APBPeriph_SPI2W_CLOCK
+  *     @arg APBPeriph_KEYSCAN_CLOCK
+  *     @arg APBPeriph_QDEC_CLOCK
+  *     @arg APBPeriph_I2C1_CLOCK
+  *     @arg APBPeriph_I2C0_CLOCK
+  *     @arg APBPeriph_IR_CLOCK
+  *     @arg APBPeriph_SPI1_CLOCK
+  *     @arg APBPeriph_SPI0_CLOCK
+  *     @arg APBPeriph_UART0_CLOCK
+  *     @arg APBPeriph_UART1_CLOCK
+  *     @arg APBPeriph_UART2_CLOCK
+  *     @arg APBPeriph_GPIO_CLOCK
+  *     @arg APBPeriph_ADC_CLOCK
+  *     @arg APBPeriph_I2S0_CLOCK
+  *     @arg APBPeriph_I2S1_CLOCK
+  *     @arg APBPeriph_CODEC_CLOCK
+  * @param  NewState: new state of the specified peripheral clock.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RCC_PeriphClockCmd(uint32_t APBPeriph, uint32_t APBPeriph_Clock, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_APB_PERIPH(APBPeriph));
+    assert_param(IS_APB_PERIPH_CLOCK(APBPeriph_Clock));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    uint32_t apbRegOff = ((APBPeriph & (0x03 << 26)) >> 26);
+    uint32_t clkRegOff = ((APBPeriph_Clock & (0x03 << 29)) >> 29);
+    /*Open clock gating first*/
+    if (NewState == ENABLE)
+    {
+        if (APBPeriph_Clock == APBPeriph_KEYSCAN_CLOCK)
+        {
+            /*Open 5M clock source*/
+            SYSBLKCTRL->u_20C.PERION_REG_SYS_CLK_SEL_2 |= BIT26;
+            SYSBLKCTRL->u_20C.PERION_REG_SYS_CLK_SEL_2 |= BIT29;
+        }
+        else if (APBPeriph_Clock == APBPeriph_ADC_CLOCK)
+        {
+            /*Open 10M clock source*/
+            SYSBLKCTRL->u_20C.PERION_REG_SYS_CLK_SEL_2 |= BIT26;
+            SYSBLKCTRL->u_20C.PERION_REG_SYS_CLK_SEL_2 |= BIT22;
+            SYSBLKCTRL->u_20C.PERION_REG_SYS_CLK_SEL_2 |= BIT28;
+        }
+        else if ((APBPeriph_Clock == APBPeriph_QDEC_CLOCK) || (APBPeriph_Clock == APBPeriph_SPI2W_CLOCK))
+        {
+            /*Open 20M clock source*/
+            SYSBLKCTRL->u_20C.PERION_REG_SYS_CLK_SEL_2 |= BIT26;
+            SYSBLKCTRL->u_20C.PERION_REG_SYS_CLK_SEL_2 |= BIT27;
+        }
+        else if ((APBPeriph_Clock == APBPeriph_TIMER_CLOCK) ||
+                 (APBPeriph_Clock == APBPeriph_ENHTIMER_CLOCK))
+        {
+            /* Enable Timer fixed 40M */
+            CLK_SOURCE_REG_2 |= BIT9;
+        }
+    }
+
+    /* Special register handle */
+    if (NewState == ENABLE)
+    {
+        if ((APBPeriph_Clock == APBPeriph_I2S0_CLOCK) || ((APBPeriph_Clock == APBPeriph_I2S1_CLOCK)) ||
+            (APBPeriph_Clock == APBPeriph_CODEC_CLOCK))
+        {
+            SYSBLKCTRL->u_220.PERION_REG_SOC_AUDIO_IF_EN |= APBPeriph | APBPeriph_Clock;
+//            SYSBLKCTRL->u_220.PERION_REG_SOC_AUDIO_IF_EN |= 0x133;
+            return;
+        }
+    }
+    else
+    {
+        if ((APBPeriph_Clock == APBPeriph_I2S0_CLOCK) || ((APBPeriph_Clock == APBPeriph_I2S1_CLOCK)) ||
+            (APBPeriph_Clock == APBPeriph_CODEC_CLOCK))
+        {
+            SYSBLKCTRL->u_220.PERION_REG_SOC_AUDIO_IF_EN &= ~(APBPeriph | APBPeriph_Clock);
+//            SYSBLKCTRL->u_220.PERION_REG_SOC_AUDIO_IF_EN &= ~(0x13F);
+            return;
+        }
+    }
+
+    /* clear flag */
+    APBPeriph &= (~(0x03 << 26));
+    APBPeriph_Clock &= (~(0x03 << 29));
+    if (NewState == ENABLE)
+    {
+        //enable peripheral
+        *((uint32_t *)(&(SYSBLKCTRL->u_210.PERION_REG_SOC_FUNC_EN)) + apbRegOff) |= APBPeriph;
+
+        if ((APBPeriph_Clock & BIT31) != 0)// for PKE only
+        {
+            //enable peripheral clock
+            *((uint32_t *)(&(SYSBLKCTRL->u_230.PERION_REG_PESOC_CLK_CTRL)) + clkRegOff - 1) |= APBPeriph_Clock
+                    << 1;
+            //enable peripheral clock in sleep mode
+            *((uint32_t *)(&(SYSBLKCTRL->u_230.PERION_REG_PESOC_CLK_CTRL)) + clkRegOff - 1) |=
+                (APBPeriph_Clock << 2);
+
+        }
+        else
+        {
+            //enable peripheral clock
+            *((uint32_t *)(&(SYSBLKCTRL->u_230.PERION_REG_PESOC_CLK_CTRL)) + clkRegOff - 1) |= APBPeriph_Clock;
+            //enable peripheral clock in sleep mode
+            *((uint32_t *)(&(SYSBLKCTRL->u_230.PERION_REG_PESOC_CLK_CTRL)) + clkRegOff - 1) |=
+                (APBPeriph_Clock << 1);
+        }
+
+    }
+    else
+    {
+        //disable peripheral
+        *((uint32_t *)(&(SYSBLKCTRL->u_210.PERION_REG_SOC_FUNC_EN)) + apbRegOff) &= (~APBPeriph);
+        if ((APBPeriph_Clock & BIT31) != 0)// for PKE only
+        {
+            //disable peripheral clock
+            *((uint32_t *)(&(SYSBLKCTRL->u_230.PERION_REG_PESOC_CLK_CTRL)) + clkRegOff - 1) &=
+                (~(APBPeriph_Clock << 1));
+            //disable peripheral clock in sleep mode
+            *((uint32_t *)(&(SYSBLKCTRL->u_230.PERION_REG_PESOC_CLK_CTRL)) + clkRegOff - 1) &= (~
+                    (APBPeriph_Clock << 2));
+        }
+        else
+        {
+            //disable peripheral clock
+            *((uint32_t *)(&(SYSBLKCTRL->u_230.PERION_REG_PESOC_CLK_CTRL)) + clkRegOff - 1) &=
+                (~APBPeriph_Clock);
+            //disable peripheral clock in sleep mode
+            *((uint32_t *)(&(SYSBLKCTRL->u_230.PERION_REG_PESOC_CLK_CTRL)) + clkRegOff - 1) &= (~
+                    (APBPeriph_Clock << 1));
+        }
+
+    }
+
+    return;
+}
+
+/**
+  * @brief  Enables or disables the APB peripheral clock.
+  * @param  APBPeriph: specifies the APB peripheral to gates its clock.
+  *   This parameter can be one of the following values:
+  *     @arg APBPeriph_TIMER
+  *     @arg APBPeriph_ENHTIMER
+  *     @arg APBPeriph_FLASH
+  *     @arg APBPeriph_GDMA
+  *     @arg APBPeriph_PKE
+  *     @arg APBPeriph_SHA256
+  *     @arg APBPeriph_FLASH1
+  *     @arg APBPeriph_FLH_SEC
+  *     @arg APBPeriph_MODEM
+  *     @arg APBPeriph_BLUEWIZ
+  *     @arg APBPeriph_ZIGBEE
+  *     @arg APBPeriph_IF8080
+  *     @arg APBPeriph_SPI2W
+  *     @arg APBPeriph_KEYSCAN
+  *     @arg APBPeriph_QDEC
+  *     @arg APBPeriph_I2C1
+  *     @arg APBPeriph_I2C0
+  *     @arg APBPeriph_IR
+  *     @arg APBPeriph_SPI1
+  *     @arg APBPeriph_SPI0
+  *     @arg APBPeriph_UART0
+  *     @arg APBPeriph_UART1
+  *     @arg APBPeriph_UART2
+  *     @arg APBPeriph_GPIO
+  *     @arg APBPeriph_ADC
+  *     @arg APBPeriph_I2S0
+  *     @arg APBPeriph_I2S1
+  *     @arg APBPeriph_CODEC
+  * @param  NewState: new state of the specified peripheral clock.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RCC_PeriFunctionConfig(uint32_t APBPeriph, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_APB_PERIPH(APBPeriph));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    uint32_t apbRegOff = ((APBPeriph & (0x03 << 26)) >> 26);
+
+    /* Special register handle */
+    if (NewState == ENABLE)
+    {
+        if ((APBPeriph == APBPeriph_I2S0) || ((APBPeriph == APBPeriph_I2S1)) ||
+            (APBPeriph == APBPeriph_CODEC))
+        {
+            SYSBLKCTRL->u_220.PERION_REG_SOC_AUDIO_IF_EN |= APBPeriph;
+            return;
+        }
+    }
+    else
+    {
+        if ((APBPeriph == APBPeriph_I2S0) || ((APBPeriph == APBPeriph_I2S1)) ||
+            (APBPeriph == APBPeriph_CODEC))
+        {
+            SYSBLKCTRL->u_220.PERION_REG_SOC_AUDIO_IF_EN &= ~(APBPeriph);
+            return;
+        }
+    }
+
+    /* clear flag */
+    APBPeriph &= (~(0x03 << 26));
+
+    if (NewState == ENABLE)
+    {
+        //enable peripheral
+        *((uint32_t *)(&(SYSBLKCTRL->u_210.PERION_REG_SOC_FUNC_EN)) + apbRegOff) |= APBPeriph;
+    }
+    else
+    {
+        //disable peripheral
+        *((uint32_t *)(&(SYSBLKCTRL->u_210.PERION_REG_SOC_FUNC_EN)) + apbRegOff) &= (~APBPeriph);
+    }
+
+    return;
+}
+
+/**
+  * @brief  Enables or disables the APB peripheral clock.
+  * @param  APBPeriph_Clock: specifies the APB peripheral clock config.
+  *     @arg APBPeriph_TIMER_CLOCK
+  *     @arg APBPeriph_ENHTIMER_CLOCK
+  *     @arg APBPeriph_FLASH_CLOCK
+  *     @arg APBPeriph_GDMA_CLOCK
+  *     @arg APBPeriph_PKE_CLOCK
+  *     @arg APBPeriph_SHA256_CLOCK
+  *     @arg APBPeriph_FLASH1_CLOCK
+  *     @arg APBPeriph_FLH_SEC_CLOCK
+  *     @arg APBPeriph_MODEM_CLOCK
+  *     @arg APBPeriph_BLUEWIZ_CLOCK
+  *     @arg APBPeriph_ZIGBEE_CLOCK
+  *     @arg APBPeriph_IF8080_CLOCK
+  *     @arg APBPeriph_SPI2W_CLOCK
+  *     @arg APBPeriph_KEYSCAN_CLOCK
+  *     @arg APBPeriph_QDEC_CLOCK
+  *     @arg APBPeriph_I2C1_CLOCK
+  *     @arg APBPeriph_I2C0_CLOCK
+  *     @arg APBPeriph_IR_CLOCK
+  *     @arg APBPeriph_SPI1_CLOCK
+  *     @arg APBPeriph_SPI0_CLOCK
+  *     @arg APBPeriph_UART0_CLOCK
+  *     @arg APBPeriph_UART1_CLOCK
+  *     @arg APBPeriph_UART2_CLOCK
+  *     @arg APBPeriph_GPIO_CLOCK
+  *     @arg APBPeriph_ADC_CLOCK
+  *     @arg APBPeriph_I2S0_CLOCK
+  *     @arg APBPeriph_I2S1_CLOCK
+  *     @arg APBPeriph_CODEC_CLOCK
+  * @param  NewState: new state of the specified peripheral clock.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RCC_PeriClockConfig(uint32_t APBPeriph_Clock, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_APB_PERIPH_CLOCK(APBPeriph_Clock));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    uint32_t clkRegOff = ((APBPeriph_Clock & (0x03 << 29)) >> 29);
+
+    /* Special register handle */
+    if (NewState == ENABLE)
+    {
+        if ((APBPeriph_Clock == APBPeriph_I2S0_CLOCK) || ((APBPeriph_Clock == APBPeriph_I2S1_CLOCK)) ||
+            (APBPeriph_Clock == APBPeriph_CODEC_CLOCK))
+        {
+            SYSBLKCTRL->u_220.PERION_REG_SOC_AUDIO_IF_EN |= APBPeriph_Clock;
+            return;
+        }
+    }
+    else
+    {
+        if ((APBPeriph_Clock == APBPeriph_I2S0_CLOCK) || ((APBPeriph_Clock == APBPeriph_I2S1_CLOCK)) ||
+            (APBPeriph_Clock == APBPeriph_CODEC_CLOCK))
+        {
+            SYSBLKCTRL->u_220.PERION_REG_SOC_AUDIO_IF_EN &= ~(APBPeriph_Clock);
+            return;
+        }
+    }
+    /* clear flag */
+    APBPeriph_Clock &= (~(0x03 << 29));
+
+    if (NewState == ENABLE)
+    {
+
+        if ((APBPeriph_Clock & BIT31) != 0)// for PKE only
+        {
+            //enable peripheral clock
+            *((uint32_t *)(&(SYSBLKCTRL->u_230.PERION_REG_PESOC_CLK_CTRL)) + clkRegOff - 1) |= APBPeriph_Clock
+                    << 1;
+            //enable peripheral clock in sleep mode
+            *((uint32_t *)(&(SYSBLKCTRL->u_230.PERION_REG_PESOC_CLK_CTRL)) + clkRegOff - 1) |=
+                (APBPeriph_Clock << 2);
+
+        }
+        else
+        {
+            //enable peripheral clock
+            *((uint32_t *)(&(SYSBLKCTRL->u_230.PERION_REG_PESOC_CLK_CTRL)) + clkRegOff - 1) |= APBPeriph_Clock;
+            //enable peripheral clock in sleep mode
+            *((uint32_t *)(&(SYSBLKCTRL->u_230.PERION_REG_PESOC_CLK_CTRL)) + clkRegOff - 1) |=
+                (APBPeriph_Clock << 1);
+        }
+
+    }
+    else
+    {
+        //disable peripheral
+        if ((APBPeriph_Clock & BIT31) != 0)// for PKE only
+        {
+            //disable peripheral clock
+            *((uint32_t *)(&(SYSBLKCTRL->u_230.PERION_REG_PESOC_CLK_CTRL)) + clkRegOff - 1) &=
+                (~(APBPeriph_Clock << 1));
+            //disable peripheral clock in sleep mode
+            *((uint32_t *)(&(SYSBLKCTRL->u_230.PERION_REG_PESOC_CLK_CTRL)) + clkRegOff - 1) &= (~
+                    (APBPeriph_Clock << 2));
+        }
+        else
+        {
+            //disable peripheral clock
+            *((uint32_t *)(&(SYSBLKCTRL->u_230.PERION_REG_PESOC_CLK_CTRL)) + clkRegOff - 1) &=
+                (~APBPeriph_Clock);
+            //disable peripheral clock in sleep mode
+            *((uint32_t *)(&(SYSBLKCTRL->u_230.PERION_REG_PESOC_CLK_CTRL)) + clkRegOff - 1) &= (~
+                    (APBPeriph_Clock << 1));
+        }
+
+    }
+    return;
+}
+
+/**
+  * @brief  I2C clock divider config.
+  * @param  I2Cx: where x can be 0 or 1 to select the I2C peripheral.
+  * @param  ClockDiv: specifies the APB peripheral to gates its clock.
+  *   This parameter can be one of the following values:
+  *     @arg I2C_CLOCK_DIV_1
+  *     @arg I2C_CLOCK_DIV_2
+  *     @arg I2C_CLOCK_DIV_4
+  *     @arg I2C_CLOCK_DIV_8
+  * @retval None
+  */
+void RCC_I2CClkDivConfig(I2C_TypeDef *I2Cx, uint16_t ClockDiv)
+{
+    assert_param(IS_I2C_DIV(ClockDiv));
+
+    /* Config I2C clock divider */
+    if (I2Cx == I2C0)
+    {
+        /* disable clock first */
+        SYSBLKCTRL->u_238.PERION_r_PON_PERI_CLK_CTRL1 &= ~SYSBLK_ACTCK_I2C0_EN_Msk;
+        //platform_delay_us(1);
+
+        CLK_SOURCE_REG_1 &= ~(0x03 << 15);
+        CLK_SOURCE_REG_1 |= (ClockDiv << 15);
+
+        //platform_delay_us(1);
+        SYSBLKCTRL->u_238.PERION_r_PON_PERI_CLK_CTRL1 |= SYSBLK_ACTCK_I2C0_EN_Msk;
+    }
+    else if (I2Cx == I2C1)
+    {
+        SYSBLKCTRL->u_238.PERION_r_PON_PERI_CLK_CTRL1 &= ~SYSBLK_ACTCK_I2C1_EN_Msk;
+        //platform_delay_us(1);
+
+        CLK_SOURCE_REG_1 &= ~(0x03 << 17);
+        CLK_SOURCE_REG_1 |= (ClockDiv << 17);
+
+        //platform_delay_us(1);
+        SYSBLKCTRL->u_238.PERION_r_PON_PERI_CLK_CTRL1 |= SYSBLK_ACTCK_I2C1_EN_Msk;
+    }
+
+    return;
+}
+
+/**
+  * @brief  SPI clock divider config.
+  * @param  SPIx: where x can be 0 or 1 to select the SPI peripheral.
+  * @param  ClockDiv: specifies the APB peripheral to gates its clock.
+  *   This parameter can be one of the following values:
+  *     @arg SPI_CLOCK_DIV_1
+  *     @arg SPI_CLOCK_DIV_2
+  *     @arg SPI_CLOCK_DIV_4
+  *     @arg SPI_CLOCK_DIV_8
+  * @retval None
+  */
+void RCC_SPIClkDivConfig(SPI_TypeDef *SPIx, uint16_t ClockDiv)
+{
+    assert_param(IS_SPI_DIV(ClockDiv));
+
+    /* Config I2C clock divider */
+    if (SPIx == SPI0)
+    {
+        /* disable clock first */
+        SYSBLKCTRL->u_234.PERION_REG_PESOC_PERI_CLK_CTRL0 &= ~SYSBLK_ACTCK_SPI0_EN_Msk;
+        //platform_delay_us(1);
+
+        CLK_SOURCE_REG_1 &= ~(0x03 << 19);
+        CLK_SOURCE_REG_1 |= (ClockDiv << 19);
+
+        //platform_delay_us(1);
+        SYSBLKCTRL->u_234.PERION_REG_PESOC_PERI_CLK_CTRL0 |= SYSBLK_ACTCK_SPI0_EN_Msk;
+    }
+    else if (SPIx == SPI1)
+    {
+        SYSBLKCTRL->u_234.PERION_REG_PESOC_PERI_CLK_CTRL0 &= ~SYSBLK_ACTCK_SPI1_EN_Msk;
+        //platform_delay_us(1);
+
+        CLK_SOURCE_REG_1 &= ~(0x03 << 21);
+        CLK_SOURCE_REG_1 |= (ClockDiv << 21);
+
+        //platform_delay_us(1);
+        SYSBLKCTRL->u_234.PERION_REG_PESOC_PERI_CLK_CTRL0 |= SYSBLK_ACTCK_SPI1_EN_Msk;
+    }
+    return;
+}
+
+/**
+  * @brief  TIMER & ENH-TIMER clock divider config.
+  * @param  TIMx: selected TIM number.
+  * @param  ClockDiv: specifies the APB peripheral to gates its clock.
+  *         This parameter can be one of the following values:
+  *         @arg TIM_CLOCK_DIV_1
+  *         @arg TIM_CLOCK_DIV_125
+  *         @arg TIM_CLOCK_DIV_2
+  *         @arg TIM_CLOCK_DIV_4
+  *         @arg TIM_CLOCK_DIV_8
+  *         @arg TIM_CLOCK_DIV_40
+  * @retval None
+  */
+void RCC_TIMClkDivConfig(E_TIM_NUM TIMx, uint16_t ClockDiv)
+{
+    assert_param(IS_UART_DIV(ClockDiv));
+
+    /* Config TIM clock divider */
+    /* disable clock first */
+    SYSBLKCTRL->u_230.PERION_REG_PESOC_CLK_CTRL &= ~SYSBLK_ACTCK_TIMER_EN_Msk;
+    //platform_delay_us(1);
+
+    CLK_SOURCE_REG_2 &= ~(0x07 << (13 + (TIMx - 2) * 3));
+    CLK_SOURCE_REG_2 |= (ClockDiv << (13 + (TIMx - 2) * 3));
+
+    //platform_delay_us(1);
+    SYSBLKCTRL->u_230.PERION_REG_PESOC_CLK_CTRL |= SYSBLK_ACTCK_TIMER_EN_Msk;
+
+    return;
+}
+
+/**
+  * @brief  UART clock divider config.
+  * @param  UARTx: selected UART peripheral.
+  * @param  ClockDiv: specifies the APB peripheral to gates its clock.
+  *   This parameter can be one of the following values:
+  *     @arg UART_CLOCK_DIV_1
+  *     @arg UART_CLOCK_DIV_2
+  *     @arg UART_CLOCK_DIV_4
+  *     @arg UART_CLOCK_DIV_16
+  * @retval None
+  */
+void RCC_UARTClkDivConfig(UART_TypeDef *UARTx, uint16_t ClockDiv)
+{
+    assert_param(IS_UART_DIV(ClockDiv));
+
+    /* Config UART clock divider */
+    if (UARTx == UART0)
+    {
+        /* disable clock first */
+        SYSBLKCTRL->u_230.PERION_REG_PESOC_CLK_CTRL &= ~SYSBLK_ACTCK_UART0_EN_Msk;
+        //platform_delay_us(1);
+
+        CLK_SOURCE_REG_1 &= ~(0x03 << 13);
+        CLK_SOURCE_REG_1 |= (ClockDiv << 13);
+
+        //platform_delay_us(1);
+        SYSBLKCTRL->u_230.PERION_REG_PESOC_CLK_CTRL |= SYSBLK_ACTCK_UART0_EN_Msk;
+    }
+    if (UARTx == UART1)
+    {
+        /* disable clock first */
+        SYSBLKCTRL->u_234.PERION_REG_PESOC_PERI_CLK_CTRL0 &= ~SYSBLK_ACTCK_UART1_EN_Msk;
+        //platform_delay_us(1);
+
+        CLK_SOURCE_REG_1 &= ~(0x03 << 9);
+        CLK_SOURCE_REG_1 |= (ClockDiv << 9);
+
+        //platform_delay_us(1);
+        SYSBLKCTRL->u_234.PERION_REG_PESOC_PERI_CLK_CTRL0 |= SYSBLK_ACTCK_UART1_EN_Msk;
+    }
+    else if (UARTx == UART2)
+    {
+        SYSBLKCTRL->u_230.PERION_REG_PESOC_CLK_CTRL &= ~SYSBLK_ACTCK_UART2_EN_Msk;
+        //platform_delay_us(1);
+
+        CLK_SOURCE_REG_1 &= ~(0x03 << 11);
+        CLK_SOURCE_REG_1 |= (ClockDiv << 11);
+
+        //platform_delay_us(1);
+        SYSBLKCTRL->u_230.PERION_REG_PESOC_CLK_CTRL |= SYSBLK_ACTCK_UART2_EN_Msk;
+    }
+
+    return;
+}
diff --git a/bee/drivers/rcc/src/device/rtl8752h/rtl876x_rcc.h b/bee/drivers/rcc/src/device/rtl8752h/rtl876x_rcc.h
new file mode 100644
index 00000000..00f183ba
--- /dev/null
+++ b/bee/drivers/rcc/src/device/rtl8752h/rtl876x_rcc.h
@@ -0,0 +1,484 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _RTL876X_RCC_H_
+#define _RTL876X_RCC_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup  IO          Peripheral Drivers
+ * \defgroup    RCC         RCC
+ *
+ * \brief       Manage the RCC peripheral functions.
+ *
+ * \ingroup     IO
+ */
+
+
+/*============================================================================*
+ *                         Includes
+ *============================================================================*/
+#include "rtl876x.h"
+
+/*============================================================================*
+ *                         Constants
+ *============================================================================*/
+
+/**
+ * \defgroup    RCC_Exported_Constants RCC Exported Constants
+ *
+ * \ingroup     RCC
+ */
+
+/**
+ * \defgroup    RCC_Peripheral_Clock RCC Peripheral Clock
+ * \{
+ * \ingroup     RCC_Exported_Constants
+ */
+
+#define APBPeriph_I2S0_CLOCK                ((uint32_t)((1 << 5) | (1 << 8) | (0x00 << 29)))
+#define APBPeriph_I2S1_CLOCK                ((uint32_t)((1 << 6) | (1 << 8) | (0x00 << 29)))
+#define APBPeriph_CODEC_CLOCK               ((uint32_t)((1 << 4) | (0x00 << 29)))
+
+#define APBPeriph_GPIO_CLOCK                ((uint32_t)((0x01 << 24) | (0x01 << 29)))
+#define APBPeriph_GDMA_CLOCK                ((uint32_t)((0x01 << 16) | (0x01 << 29)))
+#define APBPeriph_TIMER_CLOCK               ((uint32_t)((0x01 << 14) | (0x01 << 29)))
+#define APBPeriph_ENHTIMER_CLOCK            ((uint32_t)((0x01 << 14) | (0x01 << 29)))
+#define APBPeriph_UART2_CLOCK               ((uint32_t)((0x01 << 10) | (0x01 << 29)))
+#define APBPeriph_UART0_CLOCK               ((uint32_t)((0x01 << 12) | (0x01 << 29)))
+#define APBPeriph_FLASH_CLOCK               ((uint32_t)((0x01 << 8)  | (0x01 << 29)))
+
+#define APBPeriph_PKE_CLOCK                 ((uint32_t)((0x01 << 31) | (0x02 << 29)))
+#define APBPeriph_SHA256_CLOCK              ((uint32_t)((0x01 << 28) | (0x02 << 29)))
+#define APBPeriph_FLASH1_CLOCK              ((uint32_t)((0x01 << 24) | (0x02 << 29)))
+#define APBPeriph_FLH_SEC_CLOCK             ((uint32_t)((0x01 << 22) | (0x02 << 29)))
+#define APBPeriph_IR_CLOCK                  ((uint32_t)((0x01 << 20) | (0x02 << 29)))
+#define APBPeriph_SPI1_CLOCK                ((uint32_t)((0x01 << 18) | (0x02 << 29)))
+#define APBPeriph_SPI0_CLOCK                ((uint32_t)((0x01 << 16) | (0x02 << 29)))
+#define APBPeriph_UART1_CLOCK               ((uint32_t)((0x01 << 0)  | (0x02 << 29)))
+
+#define APBPeriph_IF8080_CLOCK              ((uint32_t)((0x01 << 28) | (0x03 << 29)))
+#define APBPeriph_ADC_CLOCK                 ((uint32_t)((0x01 << 24) | (0x03 << 29)))
+#define APBPeriph_SPI2W_CLOCK               ((uint32_t)((0x01 << 16) | (0x03 << 29)))
+#define APBPeriph_MODEM_CLOCK               ((uint32_t)((0x01 << 14) | (0x03 << 29)))
+#define APBPeriph_BLUEWIZ_CLOCK             ((uint32_t)((0x01 << 12) | (0x03 << 29)))
+#define APBPeriph_ZIGBEE_CLOCK              ((uint32_t)((0x01 << 10) | (0x03 << 29)))
+#define APBPeriph_KEYSCAN_CLOCK             ((uint32_t)((0x01 << 6) | (0x03 << 29)))
+#define APBPeriph_QDEC_CLOCK                ((uint32_t)((0x01 << 4) | (0x03 << 29)))
+#define APBPeriph_I2C1_CLOCK                ((uint32_t)((0x01 << 2) | (0x03 << 29)))
+#define APBPeriph_I2C0_CLOCK                ((uint32_t)((0x01 << 0) | (0x03 << 29)))
+
+#define IS_APB_PERIPH_CLOCK(CLOCK) (((CLOCK) == APBPeriph_GPIO_CLOCK) || ((CLOCK) == APBPeriph_GDMA_CLOCK)\
+                                    || ((CLOCK) == APBPeriph_TIMER_CLOCK) || ((CLOCK) == APBPeriph_IR_CLOCK)\
+                                    || ((CLOCK) == APBPeriph_ENHTIMER_CLOCK) || ((CLOCK) == APBPeriph_FLASH_CLOCK)\
+                                    || ((CLOCK) == APBPeriph_PKE_CLOCK) || ((CLOCK) == APBPeriph_SHA256_CLOCK)\
+                                    || ((CLOCK) == APBPeriph_FLASH1_CLOCK) || ((CLOCK) == APBPeriph_FLH_SEC_CLOCK)\
+                                    || ((CLOCK) == APBPeriph_MODEM_CLOCK) || ((CLOCK) == APBPeriph_BLUEWIZ_CLOCK)\
+                                    || ((CLOCK) == APBPeriph_ZIGBEE_CLOCK) \
+                                    || ((CLOCK) == APBPeriph_SPI1_CLOCK) || ((CLOCK) == APBPeriph_SPI0_CLOCK)\
+                                    || ((CLOCK) == APBPeriph_UART0_CLOCK) || ((CLOCK) == APBPeriph_ADC_CLOCK)\
+                                    || ((CLOCK) == APBPeriph_SPI2W_CLOCK) || ((CLOCK) == APBPeriph_KEYSCAN_CLOCK)\
+                                    || ((CLOCK) == APBPeriph_QDEC_CLOCK) || ((CLOCK) == APBPeriph_I2C1_CLOCK)\
+                                    || ((CLOCK) == APBPeriph_I2C0_CLOCK) || ((CLOCK) == APBPeriph_CODEC_CLOCK)\
+                                    || ((CLOCK) == APBPeriph_UART1_CLOCK) || ((CLOCK) == APBPeriph_UART2_CLOCK)\
+                                    || ((CLOCK) == APBPeriph_I2S0_CLOCK) || ((CLOCK) == APBPeriph_I2S1_CLOCK)\
+                                    || ((CLOCK) == APBPeriph_IF8080_CLOCK) || ((CLOCK) == APBPeriph_ENHTIMER_CLOCK))
+/** \} */
+
+/**
+ * \defgroup    APB_Peripheral_Define APB Peripheral Define
+ * \{
+ * \ingroup     RCC_Exported_Constants
+ */
+
+#define APBPeriph_TIMER                     ((uint32_t)((1 << 16) | (0x00 << 26)))
+#define APBPeriph_ENHTIMER                  ((uint32_t)((1 << 16) | (0x00 << 26)))
+#define APBPeriph_GDMA                      ((uint32_t)((1 << 13) | (0x00 << 26)))
+#define APBPeriph_UART0                     ((uint32_t)((1 << 12) | (0x00 << 26)))
+#define APBPeriph_ZIGBEE                    ((uint32_t)((1 << 11) | (0x00 << 26)))
+#define APBPeriph_BLUEWIZ                   ((uint32_t)((1 << 10) | (0x00 << 26)))
+#define APBPeriph_MODEMRFCPI                ((uint32_t)((1 << 9) | (0x00 << 26)))
+#define APBPeriph_FLH_SEC                   ((uint32_t)((1 << 8) | (0x00 << 26)))
+#define APBPeriph_SHA256                    ((uint32_t)((1 << 7) | (0x00 << 26)))
+#define APBPeriph_PKE                       ((uint32_t)((1 << 6) | (0x00 << 26)))
+#define APBPeriph_FLASH                     ((uint32_t)((1 << 4) | (0x00 << 26)))
+#define APBPeriph_FLASH1                    ((uint32_t)((1 << 3) | (0x00 << 26)))
+
+#define APBPeriph_IF8080                    ((uint32_t)((1 << 25) | (0x02 << 26)))
+#define APBPeriph_SPI2W                     ((uint32_t)((1 << 24) | (0x02 << 26)))
+#define APBPeriph_KEYSCAN                   ((uint32_t)((1 << 19) | (0x02 << 26)))
+#define APBPeriph_QDEC                      ((uint32_t)((1 << 18) | (0x02 << 26)))
+#define APBPeriph_I2C1                      ((uint32_t)((1 << 17) | (0x02 << 26)))
+#define APBPeriph_I2C0                      ((uint32_t)((1 << 16) | (0x02 << 26)))
+#define APBPeriph_IR                        ((uint32_t)((1 << 10) | (0x02 << 26)))
+#define APBPeriph_SPI1                      ((uint32_t)((1 << 9) | (0x02 << 26)))
+#define APBPeriph_SPI0                      ((uint32_t)((1 << 8) | (0x02 << 26)))
+#define APBPeriph_UART1                     ((uint32_t)((1 << 0) | (0x02 << 26)))
+#define APBPeriph_UART2                     ((uint32_t)((1 << 1) | (0x02 << 26)))
+
+#define APBPeriph_GPIO                      ((uint32_t)((1 << 8) | (0x03 << 26)))
+#define APBPeriph_ADC                       ((uint32_t)((1 << 0) | (0x03 << 26)))
+
+#define APBPeriph_I2S1                      ((uint32_t)((1 << 2) | (0x00 << 26)))
+#define APBPeriph_I2S0                      ((uint32_t)((1 << 1) | (0x00 << 26)))
+#define APBPeriph_CODEC                     ((uint32_t)((1 << 0) | (0x00 << 26)))
+
+#define IS_APB_PERIPH(PERIPH) (((PERIPH) == APBPeriph_TIMER) || ((PERIPH) == APBPeriph_GDMA)\
+                               || ((PERIPH) == APBPeriph_SPI2W) || ((PERIPH) == APBPeriph_KEYSCAN)\
+                               || ((PERIPH) == APBPeriph_QDEC) || ((PERIPH) == APBPeriph_I2C1)\
+                               || ((PERIPH) == APBPeriph_I2C0) || ((PERIPH) == APBPeriph_IR)\
+                               || ((PERIPH) == APBPeriph_ENHTIMER) || ((PERIPH) == APBPeriph_FLASH)\
+                               || ((PERIPH) == APBPeriph_PKE) || ((PERIPH) == APBPeriph_SHA256)\
+                               || ((PERIPH) == APBPeriph_FLASH1) || ((PERIPH) == APBPeriph_FLH_SEC)\
+                               || ((PERIPH) == APBPeriph_MODEM) || ((PERIPH) == APBPeriph_BLUEWIZ)\
+                               || ((PERIPH) == APBPeriph_ZIGBEE) \
+                               || ((PERIPH) == APBPeriph_SPI1) || ((PERIPH) == APBPeriph_SPI0)\
+                               || ((PERIPH) == APBPeriph_UART0) || ((PERIPH) == APBPeriph_GPIO)\
+                               || ((PERIPH) == APBPeriph_ADC) || ((PERIPH) == APBPeriph_CODEC)\
+                               || (PERIPH == APBPeriph_UART1) || (PERIPH == APBPeriph_UART2)\
+                               || ((PERIPH) == APBPeriph_I2S0) || ((PERIPH) == APBPeriph_I2S1)\
+                               || ((PERIPH) == APBPeriph_IF8080) || ((PERIPH) == APBPeriph_ENHTIMER))
+/** \} */
+
+/**
+ * \defgroup    I2C_Clock_Divider I2C Clock Divider
+ * \{
+ * \ingroup     RCC_Exported_Constants
+ */
+
+#define I2C_CLOCK_DIV_1                     ((uint16_t)0x0)
+#define I2C_CLOCK_DIV_2                     ((uint16_t)0x1)
+#define I2C_CLOCK_DIV_4                     ((uint16_t)0x2)
+#define I2C_CLOCK_DIV_8                     ((uint16_t)0x3)
+
+#define IS_I2C_DIV(DIV)              (((DIV) == I2C_CLOCK_DIV_1) || \
+                                      ((DIV) == I2C_CLOCK_DIV_2) || \
+                                      ((DIV) == I2C_CLOCK_DIV_4) || \
+                                      ((DIV) == I2C_CLOCK_DIV_8))
+/** \} */
+
+/**
+ * \defgroup    SPI_Clock_Divider SPI Clock Divider
+ * \{
+ * \ingroup     RCC_Exported_Constants
+ */
+
+#define SPI_CLOCK_DIV_1                     ((uint16_t)0x0)
+#define SPI_CLOCK_DIV_2                     ((uint16_t)0x1)
+#define SPI_CLOCK_DIV_4                     ((uint16_t)0x2)
+#define SPI_CLOCK_DIV_8                     ((uint16_t)0x3)
+
+#define IS_SPI_DIV(DIV)              (((DIV) == SPI_CLOCK_DIV_1) || \
+                                      ((DIV) == SPI_CLOCK_DIV_2) || \
+                                      ((DIV) == SPI_CLOCK_DIV_4) || \
+                                      ((DIV) == SPI_CLOCK_DIV_8))
+/** \} */
+
+/**
+ * \defgroup    UART_Clock_Divider UART Clock Divider
+ * \{
+ * \ingroup     RCC_Exported_Constants
+ */
+
+#define UART_CLOCK_DIV_1                    ((uint16_t)0x0)
+#define UART_CLOCK_DIV_2                    ((uint16_t)0x1)
+#define UART_CLOCK_DIV_4                    ((uint16_t)0x2)
+#define UART_CLOCK_DIV_16                   ((uint16_t)0x3)
+
+#define IS_UART_DIV(DIV)              (((DIV) == UART_CLOCK_DIV_1) || \
+                                       ((DIV) == UART_CLOCK_DIV_2) || \
+                                       ((DIV) == UART_CLOCK_DIV_4) || \
+                                       ((DIV) == UART_CLOCK_DIV_16))
+/** \} */
+
+/**
+ * \defgroup    TIM_Clock_Divider TIM Clock Divider
+ * \{
+ * \ingroup     RCC_Exported_Constants
+ */
+
+#define TIM_CLOCK_DIV_1                     0x00
+#define TIM_CLOCK_DIV_125                   0x03
+#define TIM_CLOCK_DIV_2                     0x04
+#define TIM_CLOCK_DIV_4                     0x05
+#define TIM_CLOCK_DIV_8                     0x06
+#define TIM_CLOCK_DIV_40                    0x07
+
+#define IS_TIM_DIV(DIV) (((DIV) == TIM_CLOCK_DIV_1) || \
+                         ((DIV) == TIM_CLOCK_DIV_125) || \
+                         ((DIV) == TIM_CLOCK_DIV_2) || \
+                         ((DIV) == TIM_CLOCK_DIV_4) || \
+                         ((DIV) == TIM_CLOCK_DIV_8) || \
+                         ((DIV) == TIM_CLOCK_DIV_40))
+/** \} */
+
+/**
+ * \defgroup    TIM_Clock TIM Clock
+ * \{
+ * \ingroup     RCC_Exported_Constants
+ */
+typedef enum
+{
+    TIM_CLK_2   = 2,
+    TIM_CLK_3,
+    TIM_CLK_4,
+    TIM_CLK_5,
+    TIMENH_CLK_0,
+    TIMENH_CLK_1,
+} E_TIM_NUM;
+/** \} */
+
+/** End of RCC_Exported_Constants
+  * \}
+  */
+
+/*============================================================================*
+ *                         Functions
+ *============================================================================*/
+/**
+ * \defgroup    RCC_Exported_Functions RCC Exported Functions
+ * \{
+ * \ingroup     RCC
+ */
+
+/**
+ * \brief  Enable or disable the APB peripheral clock.
+ * \param  APBPeriph: Specify the APB peripheral to gate its clock.
+ *     This parameter can be one of the following values, refer to \ref APB_Peripheral_Define.
+ *     \arg APBPeriph_TIMER: The APB peripheral of TIMER.
+ *     \arg APBPeriph_ENHTIMER: The APB peripheral of ENHTIMER.
+ *     \arg APBPeriph_FLASH: The APB peripheral of FLASH.
+ *     \arg APBPeriph_GDMA: The APB peripheral of GDMA.
+ *     \arg APBPeriph_PKE: The APB peripheral of PKE.
+ *     \arg APBPeriph_SHA256: The APB peripheral of SHA256.
+ *     \arg APBPeriph_FLASH1: The APB peripheral of FLASH1.
+ *     \arg APBPeriph_FLH_SEC: The APB peripheral of FLH_SEC.
+ *     \arg APBPeriph_MODEM: The APB peripheral of MODEM.
+ *     \arg APBPeriph_BLUEWIZ: The APB peripheral of BLUEWIZ.
+ *     \arg APBPeriph_ZIGBEE: The APB peripheral of ZIGBEE.
+ *     \arg APBPeriph_IF8080: The APB peripheral of IF8080.
+ *     \arg APBPeriph_SPI2W: The APB peripheral of SPI2W.
+ *     \arg APBPeriph_KEYSCAN: The APB peripheral of KEYSCAN.
+ *     \arg APBPeriph_QDEC: The APB peripheral of QDEC.
+ *     \arg APBPeriph_I2Cx: The APB peripheral of I2C, where x can be 0 to 1.
+ *     \arg APBPeriph_IR: The APB peripheral of IR.
+ *     \arg APBPeriph_SPIx:  The APB peripheral of SPI, where x can be 0 to 1.
+ *     \arg APBPeriph_UARTx: The APB peripheral of UART, where x can be 0 to 2.
+ *     \arg APBPeriph_GPIO: The APB peripheral of GPIO.
+ *     \arg APBPeriph_ADC: The APB peripheral of ADC.
+ *     \arg APBPeriph_I2Sx:  The APB peripheral of I2S, where x can be 0 to 1.
+ *     \arg APBPeriph_CODEC: The APB peripheral of CODEC.
+ * \param  APBPeriph_Clock: Specify the APB peripheral clock config.
+ *   This parameter can be one of the following values (must be the same with APBPeriph), refer to \ref RCC_Peripheral_Clock.
+ *     \arg APBPeriph_TIMER_CLOCK: The APB peripheral clock of TIMER.
+ *     \arg APBPeriph_ENHTIMER_CLOCK: The APB peripheral clock of ENHTIMER.
+ *     \arg APBPeriph_FLASH_CLOCK: The APB peripheral clock of FLASH.
+ *     \arg APBPeriph_GDMA_CLOCK: The APB peripheral clock of GDMA.
+ *     \arg APBPeriph_PKE_CLOCK: The APB peripheral clock of PKE.
+ *     \arg APBPeriph_SHA256_CLOCK: The APB peripheral clock of SHA256.
+ *     \arg APBPeriph_FLASH1_CLOCK: The APB peripheral clock of FLASH1.
+ *     \arg APBPeriph_FLH_SEC_CLOCK: The APB peripheral clock of FLH_SEC.
+ *     \arg APBPeriph_MODEM_CLOCK: The APB peripheral clock of MODEM.
+ *     \arg APBPeriph_BLUEWIZ_CLOCK: The APB peripheral clock of BLUEWIZ.
+ *     \arg APBPeriph_ZIGBEE_CLOCK: The APB peripheral clock of ZIGBEE.
+ *     \arg APBPeriph_IF8080_CLOCK: The APB peripheral clock of IF8080.
+ *     \arg APBPeriph_SPI2W_CLOCK: The APB peripheral clock of SPI2W.
+ *     \arg APBPeriph_KEYSCAN_CLOCK: The APB peripheral clock of KEYSCAN.
+ *     \arg APBPeriph_QDEC_CLOCK: The APB peripheral clock of QDEC.
+ *     \arg APBPeriph_I2Cx_CLOCK: The APB peripheral clock of I2C, where x can be 0 to 1.
+ *     \arg APBPeriph_IR_CLOCK: The APB peripheral clock of IR.
+ *     \arg APBPeriph_SPIx_CLOCK: The APB peripheral clock of SPI, where x can be 0 to 1.
+ *     \arg APBPeriph_UARTx_CLOCK: The APB peripheral clock of UART, where x can be 0 to 2.
+ *     \arg APBPeriph_GPIO_CLOCK: The APB peripheral clock of GPIO.
+ *     \arg APBPeriph_ADC_CLOCK: The APB peripheral clock of ADC.
+ *     \arg APBPeriph_I2Sx_CLOCK: The APB peripheral clock of I2S, where x can be 0 to 1.
+ *     \arg APBPeriph_CODEC_CLOCK: The APB peripheral clock of CODEC.
+ * \param  NewState: New state of the specified peripheral clock.
+ *     This parameter can be: ENABLE or DISABLE.
+ * \return None.
+ */
+void RCC_PeriphClockCmd(uint32_t APBPeriph, uint32_t APBPeriph_Clock,
+                        FunctionalState NewState);
+
+/**
+ * \brief  Configure the I2C clock divider.
+ * \param  I2Cx: Where x can be 0 or 1 to select the I2C peripheral.
+ * \param  ClockDiv: Specify the APB peripheral to gate its clock.
+ *     This parameter can be one of the following values, refer to \ref I2C_Clock_Divider.
+ *     \arg I2C_CLOCK_DIV_1
+ *     \arg I2C_CLOCK_DIV_2
+ *     \arg I2C_CLOCK_DIV_4
+ *     \arg I2C_CLOCK_DIV_8
+ * \return None.
+ */
+void RCC_I2CClkDivConfig(I2C_TypeDef *I2Cx, uint16_t ClockDiv);
+
+/**
+ * \brief  Configure the SPI clock divider.
+ * \param  SPIx: Where x can be 0 or 1 to select the SPI peripheral.
+ * \param  ClockDiv: Specify the APB peripheral to gate its clock.
+ *     This parameter can be one of the following values, refer to \ref SPI_Clock_Divider.
+ *     \arg SPI_CLOCK_DIV_1
+ *     \arg SPI_CLOCK_DIV_2
+ *     \arg SPI_CLOCK_DIV_4
+ *     \arg SPI_CLOCK_DIV_8
+ * \return None.
+ */
+void RCC_SPIClkDivConfig(SPI_TypeDef *SPIx, uint16_t ClockDiv);
+
+/**
+  * \brief  Configure the TIMER and ENH-TIMER clock divider.
+  * \param  TIMx: selected TIM number.
+  * \param  ClockDiv: Specify the APB peripheral to gate its clock.
+  *         This parameter can be one of the following values, refer to \ref TIM_Clock_Divider.
+  *         \arg TIM_CLOCK_DIV_1
+  *         \arg TIM_CLOCK_DIV_125
+  *         \arg TIM_CLOCK_DIV_2
+  *         \arg TIM_CLOCK_DIV_4
+  *         \arg TIM_CLOCK_DIV_8
+  *         \arg TIM_CLOCK_DIV_40
+  * \return None
+  */
+void RCC_TIMClkDivConfig(E_TIM_NUM TIMx, uint16_t ClockDiv);
+
+/**
+ * \brief  Configure the UART clock divider.
+ * \param  UARTx: Selected UART peripheral.
+ * \param  ClockDiv: Specify the APB peripheral to gate its clock.
+ *     This parameter can be one of the following values, refer to \ref UART_Clock_Divider.
+ *     \arg UART_CLOCK_DIV_1
+ *     \arg UART_CLOCK_DIV_2
+ *     \arg UART_CLOCK_DIV_4
+ *     \arg UART_CLOCK_DIV_16
+ * \return None.
+ */
+void RCC_UARTClkDivConfig(UART_TypeDef *UARTx, uint16_t ClockDiv);
+
+/**
+ * \brief   Enable or disable the APB peripheral function.
+ * \param   APBPeriph: Specify the APB peripheral.
+ *          This parameter can be one of the following values, refer to \ref APB_Peripheral_Define.
+ *     \arg APBPeriph_TIMER
+ *     \arg APBPeriph_ENHTIMER
+ *     \arg APBPeriph_FLASH
+ *     \arg APBPeriph_GDMA
+ *     \arg APBPeriph_PKE
+ *     \arg APBPeriph_SHA256
+ *     \arg APBPeriph_FLASH1
+ *     \arg APBPeriph_FLH_SEC
+ *     \arg APBPeriph_MODEM
+ *     \arg APBPeriph_BLUEWIZ
+ *     \arg APBPeriph_ZIGBEE
+ *     \arg APBPeriph_IF8080
+ *     \arg APBPeriph_SPI2W
+ *     \arg APBPeriph_KEYSCAN
+ *     \arg APBPeriph_QDEC
+ *     \arg APBPeriph_I2C1
+ *     \arg APBPeriph_I2C0
+ *     \arg APBPeriph_IR
+ *     \arg APBPeriph_SPI1
+ *     \arg APBPeriph_SPI0
+ *     \arg APBPeriph_UART0
+ *     \arg APBPeriph_UART1
+ *     \arg APBPeriph_UART2
+ *     \arg APBPeriph_GPIO
+ *     \arg APBPeriph_ADC
+ *     \arg APBPeriph_I2S0
+ *     \arg APBPeriph_I2S1
+ *     \arg APBPeriph_CODEC
+ * \param  NewState: New state of the specified peripheral clock.
+ *     This parameter can be: ENABLE or DISABLE.
+ * \return None.
+ */
+void RCC_PeriFunctionConfig(uint32_t APBPeriph, FunctionalState NewState);
+
+/**
+ * \brief  Enable or disable the APB peripheral clock.
+ * \param  APBPeriph_Clock: Specify the APB peripheral clock config.
+ *     This parameter can be one of the following values (must be the same with APBPeriph), refer to \ref RCC_Peripheral_Clock.
+ *     \arg APBPeriph_TIMER_CLOCK
+ *     \arg APBPeriph_ENHTIMER_CLOCK
+ *     \arg APBPeriph_FLASH_CLOCK
+ *     \arg APBPeriph_GDMA_CLOCK
+ *     \arg APBPeriph_PKE_CLOCK
+ *     \arg APBPeriph_SHA256_CLOCK
+ *     \arg APBPeriph_FLASH1_CLOCK
+ *     \arg APBPeriph_FLH_SEC_CLOCK
+ *     \arg APBPeriph_MODEM_CLOCK
+ *     \arg APBPeriph_BLUEWIZ_CLOCK
+ *     \arg APBPeriph_ZIGBEE_CLOCK
+ *     \arg APBPeriph_IF8080_CLOCK
+ *     \arg APBPeriph_SPI2W_CLOCK
+ *     \arg APBPeriph_KEYSCAN_CLOCK
+ *     \arg APBPeriph_QDEC_CLOCK
+ *     \arg APBPeriph_I2C1_CLOCK
+ *     \arg APBPeriph_I2C0_CLOCK
+ *     \arg APBPeriph_IR_CLOCK
+ *     \arg APBPeriph_SPI1_CLOCK
+ *     \arg APBPeriph_SPI0_CLOCK
+ *     \arg APBPeriph_UART0_CLOCK
+ *     \arg APBPeriph_UART1_CLOCK
+ *     \arg APBPeriph_UART2_CLOCK
+ *     \arg APBPeriph_GPIO_CLOCK
+ *     \arg APBPeriph_ADC_CLOCK
+ *     \arg APBPeriph_I2S0_CLOCK
+ *     \arg APBPeriph_I2S1_CLOCK
+ *     \arg APBPeriph_CODEC_CLOCK
+ * \param  NewState: New state of the specified peripheral clock.
+ *                   This parameter can be: ENABLE or DISABLE.
+ * \return None.
+ */
+void RCC_PeriClockConfig(uint32_t APBPeriph_Clock, FunctionalState NewState);
+
+/**
+ * \brief   Enables the 5M clock source.
+ * \return  None.
+ */
+__STATIC_INLINE void RCC_ClockSrc5MCmd(void)
+{
+    /* Open 5M clock source */
+    SYSBLKCTRL->u_20C.PERION_REG_SYS_CLK_SEL_2 |= BIT26;
+    SYSBLKCTRL->u_20C.PERION_REG_SYS_CLK_SEL_2 |= BIT29;
+}
+
+/**
+ * \brief   Enables the 10M clock source.
+ * \return  None.
+ */
+__STATIC_INLINE void RCC_ClockSrc10MCmd(void)
+{
+    /* Open 10M clock source */
+    SYSBLKCTRL->u_20C.PERION_REG_SYS_CLK_SEL_2 |= BIT26;
+    SYSBLKCTRL->u_20C.PERION_REG_SYS_CLK_SEL_2 |= BIT28;
+}
+
+/**
+ * \brief   Enables the 20M clock source.
+ * \return  None.
+ */
+__STATIC_INLINE void RCC_ClockSrc20MCmd(void)
+{
+    /* Open 20M clock source */
+    SYSBLKCTRL->u_20C.PERION_REG_SYS_CLK_SEL_2 |= BIT26;
+    SYSBLKCTRL->u_20C.PERION_REG_SYS_CLK_SEL_2 |= BIT27;
+}
+
+/** End of RCC_Exported_Functions
+  * \}
+  */
+
+/** End of RCC
+  * \}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTL876X_RCC_H_ */
diff --git a/bee/drivers/rcc/src/device/rtl87x2g/rtl_rcc.c b/bee/drivers/rcc/src/device/rtl87x2g/rtl_rcc.c
new file mode 100644
index 00000000..6cebbe4d
--- /dev/null
+++ b/bee/drivers/rcc/src/device/rtl87x2g/rtl_rcc.c
@@ -0,0 +1,223 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *                        Header Files
+ *============================================================================*/
+#include "rtl_rcc.h"
+
+/*============================================================================*
+ *                          Private Macros
+ *============================================================================*/
+#define PERI_ON_CLOCK_CTRL            *((volatile uint32_t *)PERI_ON_RCC_REG_BASE)
+#define PERI_ON_AUDIO_CLOCK_CTRL      *((volatile uint32_t *)PERIBLKCTRL_AUDIO_REG_BASE)
+
+/*============================================================================*
+ *                           Public Functions
+ *============================================================================*/
+/**
+  * \brief  Enable or disable the APB peripheral clock.
+  * \param  APBPeriph: specifies the APB peripheral to gates its clock.
+  *         This parameter can refer APB Peripheral.
+  * \param  APBPeriph_Clock: specifies the APB peripheral clock config.
+  *         This parameter can refer to APB Peripheral Clock (must be the same with APBPeriph).
+  * \param  NewState: new state of the specified peripheral clock.
+  *         This parameter can be: ENABLE or DISABLE.
+  * \return None
+  */
+void RCC_PeriphClockCmd(uint32_t APBPeriph, uint32_t APBPeriph_Clock, FunctionalState NewState)
+{
+    /* Check the parameters. */
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    uint32_t tmp_1 = APBPeriph & 0x800;
+    uint32_t apbRegOff = (APBPeriph & (0XFF));
+    uint32_t clk = APBPeriph_Clock;
+    uint32_t clk_func = APBPeriph_Clock;
+
+    if (tmp_1 == 0x800)
+    {
+        clk_func += clk << 1;
+    }
+    else
+    {
+        clk_func += clk >> 1;
+    }
+
+
+    if (NewState == ENABLE)
+    {
+        if (APBPeriph == APBPeriph_CODEC)
+        {
+            *((uint32_t *)(&(PERI_ON_AUDIO_CLOCK_CTRL)) + apbRegOff) |= clk_func;
+        }
+
+        else
+        {
+            if (APBPeriph == APBPeriph_SPI0)
+            {
+                if (APBPeriph_Clock == APBPeriph_SPI0_CLOCK)
+                {
+                    PERIBLKCTRL_PERI_CLK->u_310.BITS_310.spi0_mux_clk_cg_en = 1;
+                }
+                else if (APBPeriph_Clock == APBPeriph_SPI0_SLAVE_CLOCK)
+                {
+                    PERIBLKCTRL_PERI_CLK->u_310.BITS_310.spi0_s_mux_clk_cg_en = 1;
+                }
+            }
+            if (APBPeriph == APBPeriph_IR)
+            {
+                if (APBPeriph_Clock == APBPeriph_IR_CLOCK)
+                {
+                    PERIBLKCTRL_PERI_CLK->u_320.BITS_320.r_ir_mux_clk_cg_en = 1;
+                }
+            }
+            /* Enable peripheral and peripheral clock */
+            *((uint32_t *)(&(PERI_ON_CLOCK_CTRL)) + apbRegOff) |= clk_func;
+        }
+    }
+    else
+    {
+        if (APBPeriph == APBPeriph_CODEC)
+        {
+            *((uint32_t *)(&(PERI_ON_AUDIO_CLOCK_CTRL)) + apbRegOff) &= ~clk_func;
+        }
+        else
+        {
+            if (APBPeriph == APBPeriph_SPI0)
+            {
+                if (APBPeriph_Clock == APBPeriph_SPI0_CLOCK)
+                {
+                    PERIBLKCTRL_PERI_CLK->u_310.BITS_310.spi0_mux_clk_cg_en = 0;
+                }
+                else if (APBPeriph_Clock == APBPeriph_SPI0_SLAVE_CLOCK)
+                {
+                    PERIBLKCTRL_PERI_CLK->u_310.BITS_310.spi0_s_mux_clk_cg_en = 0;
+                }
+            }
+            if (APBPeriph == APBPeriph_IR)
+            {
+                if (APBPeriph_Clock == APBPeriph_IR_CLOCK)
+                {
+                    PERIBLKCTRL_PERI_CLK->u_320.BITS_320.r_ir_mux_clk_cg_en = 0;
+                }
+            }
+            /* Disable peripheral and peripheral clock */
+            *((uint32_t *)(&(PERI_ON_CLOCK_CTRL)) + apbRegOff) &= (~clk_func);
+        }
+
+    }
+
+    return;
+}
+
+/**
+  * \brief  Enable or disable the APB peripheral clock.
+  * \param  APBPeriph: specifies the APB peripheral to gates its clock.
+  *         This parameter can refer APB Peripheral.
+  * \param  APBPeriph_Clock: specifies the APB peripheral clock config.
+  *         This parameter can refer to APB Peripheral Clock (must be the same with APBPeriph).
+  * \param  NewState: new state of the specified peripheral clock.
+  *         This parameter can be: ENABLE or DISABLE.
+  * \return None
+  */
+void RCC_PeriFunctionConfig(uint32_t APBPeriph, uint32_t APBPeriph_Clock, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_APB_PERIPH(APBPeriph));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    uint32_t tmp_1 = APBPeriph & 0x800;
+    uint32_t apbRegOff = (APBPeriph & (0XFF));
+    uint32_t clk = APBPeriph_Clock;
+    uint32_t clk_func = APBPeriph_Clock;
+
+    if (tmp_1 == 0x800)
+    {
+        clk_func = clk << 1;
+    }
+    else
+    {
+        clk_func = clk >> 1;
+    }
+
+
+    if (NewState == ENABLE)
+    {
+        if (APBPeriph == APBPeriph_CODEC)
+        {
+            *((uint32_t *)(&(PERI_ON_AUDIO_CLOCK_CTRL)) + apbRegOff) |= clk_func;
+        }
+        else
+        {
+            /* Enable peripheral and peripheral clock */
+            *((uint32_t *)(&(PERI_ON_CLOCK_CTRL)) + apbRegOff) |= clk_func;
+        }
+    }
+    else
+    {
+        if (APBPeriph == APBPeriph_CODEC)
+        {
+            *((uint32_t *)(&(PERI_ON_AUDIO_CLOCK_CTRL)) + apbRegOff) &= ~clk_func;
+        }
+        else
+        {
+            /* Disable peripheral and peripheral clock */
+            *((uint32_t *)(&(PERI_ON_CLOCK_CTRL)) + apbRegOff) &= (~clk_func);
+        }
+
+    }
+    return;
+}
+
+/**
+  * \brief  Enable or disable the APB peripheral clock.
+  * \param  APBPeriph: specifies the APB peripheral to gates its clock.
+  *         This parameter can refer APB Peripheral.
+  * \param  APBPeriph_Clock: specifies the APB peripheral clock config.
+  *         This parameter can refer to APB Peripheral Clock (must be the same with APBPeriph).
+  * \param  NewState: new state of the specified peripheral clock.
+  *         This parameter can be: ENABLE or DISABLE.
+  * \return None
+  */
+void RCC_PeriClockConfig(uint32_t APBPeriph, uint32_t APBPeriph_Clock, FunctionalState NewState)
+{
+    /* Check the parameters. */
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    uint32_t apbRegOff = (APBPeriph & (0XFF));
+    uint32_t clk_func = APBPeriph_Clock;
+
+    if (NewState == ENABLE)
+    {
+
+        if (APBPeriph == APBPeriph_CODEC)
+        {
+            *((uint32_t *)(&(PERI_ON_AUDIO_CLOCK_CTRL)) + apbRegOff) |= clk_func;
+        }
+        else
+        {
+            /* Enable peripheral and peripheral clock */
+            *((uint32_t *)(&(PERI_ON_CLOCK_CTRL)) + apbRegOff) |= clk_func;
+        }
+    }
+    else
+    {
+        if (APBPeriph == APBPeriph_CODEC)
+        {
+            *((uint32_t *)(&(PERI_ON_AUDIO_CLOCK_CTRL)) + apbRegOff) &= ~clk_func;
+        }
+        else
+        {
+            /* Disable peripheral and peripheral clock */
+            *((uint32_t *)(&(PERI_ON_CLOCK_CTRL)) + apbRegOff) &= (~clk_func);
+        }
+
+    }
+
+    return;
+}
+
diff --git a/bee/drivers/rcc/src/device/rtl87x2g/rtl_rcc.h b/bee/drivers/rcc/src/device/rtl87x2g/rtl_rcc.h
new file mode 100644
index 00000000..8b190bd7
--- /dev/null
+++ b/bee/drivers/rcc/src/device/rtl87x2g/rtl_rcc.h
@@ -0,0 +1,181 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *               Define to prevent recursive inclusion
+ *============================================================================*/
+#ifndef RTL_RCC_H
+#define RTL_RCC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*============================================================================*
+ *                        Header Files
+ *============================================================================*/
+#include "utils/rtl_utils.h"
+#include "rtl_rcc_def.h"
+
+/** \defgroup RCC         RCC
+  * \brief
+  * \{
+  */
+
+/*============================================================================*
+ *                         Constants
+ *============================================================================*/
+/** \defgroup RCC_Exported_Constants RCC Exported Constants
+  * \brief
+  * \{
+  */
+
+/**
+ * \defgroup    Clock_Divider Clock Divider
+ * \{
+ * \ingroup     RCC_Exported_Constants
+ */
+typedef enum
+{
+    CLOCK_DIV_1,    //!< The RCC clock divider is set to 1.
+    CLOCK_DIV_2,    //!< The RCC clock divider is set to 2.
+    CLOCK_DIV_4,    //!< The RCC clock divider is set to 4.
+    CLOCK_DIV_8,    //!< The RCC clock divider is set to 8.
+    CLOCK_DIV_16,   //!< The RCC clock divider is set to 16.
+    CLOCK_DIV_32,   //!< The RCC clock divider is set to 32.
+    CLOCK_DIV_40,   //!< The RCC clock divider is set to 40.
+    CLOCK_DIV_64,   //!< The RCC clock divider is set to 64.
+} RCCClockDiv_Typedef;
+
+#define IS_DIV(DIV)   (((DIV) == CLOCK_DIV_1) || \
+                       ((DIV) == CLOCK_DIV_2) || \
+                       ((DIV) == CLOCK_DIV_4) || \
+                       ((DIV) == CLOCK_DIV_8) || \
+                       ((DIV) == CLOCK_DIV_16) || \
+                       ((DIV) == CLOCK_DIV_32) || \
+                       ((DIV) == CLOCK_DIV_40) || \
+                       ((DIV) == CLOCK_DIV_64)) //!< Check if the input parameter is valid.
+
+/** End of Clock_Divider
+  * \}
+  */
+
+/** End of RCC_Exported_Constants
+  * \}
+  */
+
+/*============================================================================*
+ *                         Functions
+ *============================================================================*/
+/** \defgroup RCC_Exported_Functions RCC Exported Functions
+  * \brief
+  * \{
+  */
+
+/**
+ * \brief  Enable or disable the APB peripheral clock.
+ *
+ * \param[in] APBPeriph        Specify the APB peripheral to gates its clock.
+ *                             This parameter can refer to \ref APB_Peripheral_Func.
+ * \param[in] APBPeriph_Clock  Specify the APB peripheral clock config.
+ *                             This parameter can refer to \ref APB_Peripheral_Clock (must be the same with APBPeriph).
+ * \param[in] NewState         New state of the specified peripheral clock.
+ *                             This parameter can be one of the following values:
+ *                             - ENABLE: Enable the specified peripheral clock.
+ *                             - DISABLE: Disable the specified peripheral clock.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_spi_init(void)
+ * {
+ *     RCC_PeriphClockCmd(APBPeriph_SPI0, APBPeriph_SPI0_CLOCK, ENABLE);
+ * }
+ * \endcode
+ */
+void RCC_PeriphClockCmd(uint32_t APBPeriph, uint32_t APBPeriph_Clock, FunctionalState NewState);
+
+/**
+ * \brief  Enable or disable the APB peripheral function.
+ *
+ * \param[in] APBPeriph        Specify the APB peripheral.
+ *                             This parameter can refer APB Peripheral.
+ * #if RCC_SUPPORT_PERIPHCLOCKCONFIG_API_MORE_PARAMS
+ * \param[in] APBPeriph_Clock  Specify the APB peripheral clock config.
+ *                             This parameter can refer to APB Peripheral Clock (must be the same with APBPeriph).
+ * #endif
+ * \param[in] NewState         New state of the specified peripheral function.
+ *                             This parameter can be one of the following values:
+ *                             \arg ENABLE: Enable the specified peripheral function.
+ *                             \arg DISABLE: Disable the specified peripheral function.
+ */
+#if RCC_SUPPORT_PERIPHCLOCKCONFIG_API_MORE_PARAMS
+void RCC_PeriFunctionConfig(uint32_t APBPeriph, uint32_t APBPeriph_Clock, FunctionalState NewState);
+#else
+void RCC_PeriFunctionConfig(uint32_t APBPeriph, FunctionalState NewState);
+#endif
+
+/**
+ * \brief  Enable or disable the specified APB peripheral clock.
+ *
+ * \param[in] APBPeriph        Specify the APB peripheral to gates its clock.
+ *                             This parameter can refer APB Peripheral.
+ * #if RCC_SUPPORT_PERIPHCLOCKCONFIG_API_MORE_PARAMS
+ * \param[in] APBPeriph_Clock  Specify the APB peripheral clock config.
+ *                             This parameter can refer to APB Peripheral Clock (must be the same with APBPeriph).
+ * #endif
+ * \param[in] NewState         New state of the specified APB peripheral clock.
+ *                             This parameter can be one of the following values:
+ *                             \arg ENABLE: Enable the specified APB peripheral clock.
+ *                             \arg DISABLE: Disable the specified APB peripheral clock.
+ */
+#if RCC_SUPPORT_PERIPHCLOCKCONFIG_API_MORE_PARAMS
+void RCC_PeriClockConfig(uint32_t APBPeriph, uint32_t APBPeriph_Clock, FunctionalState NewState);
+#else
+void RCC_PeriClockConfig(uint32_t APBPeriph_Clock, FunctionalState NewState);
+#endif
+
+#if RCC_SUPPORT_CLOCKGATECMD_API
+/**
+ * \brief  Enable or disable the specified RCC Clock Source Gating.
+ *
+ * \param[in] ClockGate  Specify the clock source to gate.
+ *                       This parameter can be one of the following values:
+ *                       \arg CLOCK_GATE_5M: 5M clock source for adc and keyscan.
+ *                       \arg CLOCK_GATE_10M: 10M clock source for bluewiz.
+ *                       \arg CLOCK_GATE_20M: 20M clock source for 2wssi and qdec.
+ * \param[in] NewState   New state of the specified RCC Clock Source.
+ *                       This parameter can be one of the following values:
+ *                       - ENABLE: Enable the specified RCC Clock Source.
+ *                       - DISABLE: Disable the specified RCC Clock Source.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_xx_init(void)
+ * {
+ *     RCC_ClockGateCmd(CLOCK_GATE_5M, ENABLE);
+ * }
+ * \endcode
+ */
+extern void RCC_ClockGateCmd(uint32_t ClockGate, FunctionalState NewState);
+#endif
+
+/** End of RCC_Exported_Functions
+  * \}
+  */
+
+/** End of RCC
+  * \}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RTL_RCC_H */
+
+
diff --git a/bee/drivers/rcc/src/device/rtl87x2g/rtl_rcc_def.h b/bee/drivers/rcc/src/device/rtl87x2g/rtl_rcc_def.h
new file mode 100644
index 00000000..aa637475
--- /dev/null
+++ b/bee/drivers/rcc/src/device/rtl87x2g/rtl_rcc_def.h
@@ -0,0 +1,323 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef RTL_RCC_DEF_H
+#define RTL_RCC_DEF_H
+
+#include "utils/rtl_utils.h"
+#include "address_map.h"
+#include "pcc_reg.h"
+
+#ifdef  __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/*============================================================================*
+ *                          RCC Defines
+ *============================================================================*/
+/** \defgroup RCC         RCC
+  * \brief
+  * \{
+  */
+
+/** \defgroup RCC_Exported_Constants RCC Exported Constants
+  * \brief
+  * \{
+  */
+
+/**
+ * \defgroup RCC_Defines RCC Defines
+ * \{
+ * \ingroup  RCC_Exported_Constants
+ */
+#define RCC_SUPPORT_PERIPHCLOCKCONFIG_API_MORE_PARAMS  (1) //!< The chip supports peripheral clock config.
+#define RCC_SUPPORT_CLOCKGATECMD_API                   (0) //!< The function is not supported.
+
+/** End of RCC_Defines
+  * \}
+  */
+
+/** End of RCC_Exported_Constants
+  * \}
+  */
+
+/** End of RCC
+  * \}
+  */
+
+/*============================================================================*
+ *                         RCC Constants
+ *============================================================================*/
+/** \defgroup RCC         RCC
+  * \brief
+  * \{
+  */
+
+/** \defgroup RCC_Exported_Constants RCC Exported Constants
+  * \brief
+  * \{
+  */
+
+/**
+ * \defgroup    APB_Peripheral_Clock APB Peripheral Clock
+ * \{
+ * \ingroup     RCC_Exported_Constants
+ */
+#define APBPeriph_SPIC0_CLOCK               ((uint32_t)(1 << 30))  //!< SPIC0 clock
+
+#define APBPeriph_SPIC1_CLOCK               ((uint32_t)(1 << 30))  //!< SPIC1 clock
+
+#define APBPeriph_SPIC2_CLOCK               ((uint32_t)(1 << 30))  //!< SPIC2 clock
+
+#define APBPeriph_GDMA_CLOCK                ((uint32_t)(1 << 1))   //!< GDMA clock
+
+#define APBPeriph_SPI0_SLAVE_CLOCK          ((uint32_t)(1 << 17))  //!< SPI0 slave clock
+#define APBPeriph_SPI1_CLOCK                ((uint32_t)(1 << 9))   //!< SPI1 clock
+#define APBPeriph_SPI0_CLOCK                ((uint32_t)(1 << 1))   //!< SPI0 clock
+
+#define APBPeriph_I2C3_CLOCK                ((uint32_t)(1 << 25))  //!< I2C3 clock
+#define APBPeriph_I2C2_CLOCK                ((uint32_t)(1 << 17))  //!< I2C2 clock
+#define APBPeriph_I2C1_CLOCK                ((uint32_t)(1 << 9))   //!< I2C1 clock
+#define APBPeriph_I2C0_CLOCK                ((uint32_t)(1 << 1))   //!< I2C0 clock
+
+#define APBPeriph_UART3_CLOCK               ((uint32_t)(1 << 26))  //!< UART3 clock
+#define APBPeriph_UART2_CLOCK               ((uint32_t)(1 << 18))  //!< UART2 clock
+#define APBPeriph_UART1_CLOCK               ((uint32_t)(1 << 10))  //!< UART1 clock
+#define APBPeriph_UART0_CLOCK               ((uint32_t)(1 << 2))   //!< UART0 clock
+
+#define APBPeriph_ACCXTAL_CLOCK             ((uint32_t)(1 << 31))  //!< ACCXTAL clock
+#define APBPeriph_PDCK_CLOCK                ((uint32_t)(1 << 29))  //!< PDCK clock
+#define APBPeriph_ZBMAC_CLOCK               ((uint32_t)(1 << 25))  //!< ZBMAC clock
+#define APBPeriph_BTPHY_CLOCK               ((uint32_t)(1 << 23))  //!< BTPHY clock
+#define APBPeriph_BTMAC_CLOCK               ((uint32_t)(1 << 21))  //!< BTMAC clock
+#define APBPeriph_SEGCOM_CLOCK              ((uint32_t)(1 << 19))  //!< SEGCOM clock
+#define APBPeriph_SPI3W_CLOCK               ((uint32_t)(1 << 15))  //!< SPI3W clock
+#define APBPeriph_ETH_CLOCK                 ((uint32_t)(1 << 13))  //!< ETH clock
+#define APBPeriph_PPE_CLOCK                 ((uint32_t)(1 << 11))  //!< PPE clock
+#define APBPeriph_KEYSCAN_CLOCK             ((uint32_t)(1 << 7))   //!< KEYSCAN clock
+#define APBPeriph_HRADC_CLOCK               ((uint32_t)(1 << 3))   //!< HRADC clock
+#define APBPeriph_ADC_CLOCK                 ((uint32_t)(1 << 1))   //!< ADC clock
+
+#define APBPeriph_CAN_CLOCK                 ((uint32_t)(1 << 24))  //!< CAN clock
+#define APBPeriph_IR_CLOCK                  ((uint32_t)(1 << 19))  //!< IR clock
+#define APBPeriph_ISO7816_CLOCK             ((uint32_t)(1 << 9))   //!< ISO7816 clock
+#define APBPeriph_GPIOB_CLOCK               ((uint32_t)(1 << 5))   //!< GPIOB clock
+#define APBPeriph_GPIOA_CLOCK               ((uint32_t)(1 << 1))   //!< GPIOA clock
+
+#define APBPeriph_DISP_CLOCK                ((uint32_t)(1 << 23))  //!< DISP clock
+#define APBPeriph_IDU_CLOCK                 ((uint32_t)(1 << 7))   //!< IDU clock
+
+#define APBPeriph_TIMER_CLOCK               ((uint32_t)(1 << 31))  //!< TIMER clock
+
+#define APBPeriph_ENHTIMER_CLOCK            ((uint32_t)(1 << 31))  //!< ENHTIMER clock
+#define APBPeriph_ENHTIMER_PWM1_CLOCK       ((uint32_t)(1 << 29))  //!< ENHTIMER_PWM1 clock
+#define APBPeriph_ENHTIMER_PWM0_CLOCK       ((uint32_t)(1 << 13))  //!< ENHTIMER_PWM0 clock
+
+#define APBPeriph_ENHTIMER_PWM3_CLOCK       ((uint32_t)(1 << 29))  //!< ENHTIMER_PWM3 clock
+#define APBPeriph_ENHTIMER_PWM2_CLOCK       ((uint32_t)(1 << 13))  //!< ENHTIMER_PWM2 clock
+
+#define APBPeriph_SDHC_CLOCK                ((uint32_t)(1 << 0))   //!< SDHC clock
+
+#define APBPeriph_UART5_CLOCK               ((uint32_t)(1 << 10))  //!< UART5 clock
+#define APBPeriph_UART4_CLOCK               ((uint32_t)(1 << 2))   //!< UART4 clock
+
+#define APBPeriph_CODEC_CLOCK               ((uint32_t)(1 << 9))   //!< CODEC clock
+#define APBPeriph_I2S1_CLOCK                ((uint32_t)(1 << 3))   //!< I2S1 clock
+#define APBPeriph_I2S0_CLOCK                ((uint32_t)(1 << 1))   //!< I2S0 clock
+
+#define IS_APB_PERIPH_CLOCK(CLOCK) (((CLOCK) == APBPeriph_GDMA_CLOCK) \
+                                    || ((CLOCK) == APBPeriph_SPI1_CLOCK) \
+                                    || ((CLOCK) == APBPeriph_SPI0_SLAVE_CLOCK) \
+                                    || ((CLOCK) == APBPeriph_I2C2_CLOCK) \
+                                    || ((CLOCK) == APBPeriph_I2C1_CLOCK) \
+                                    || ((CLOCK) == APBPeriph_I2C0_CLOCK) \
+                                    || ((CLOCK) == APBPeriph_SPI0_CLOCK) \
+                                    || ((CLOCK) == APBPeriph_ADC_CLOCK) \
+                                    || ((CLOCK) == APBPeriph_UART5_CLOCK) \
+                                    || ((CLOCK) == APBPeriph_UART4_CLOCK) \
+                                    || ((CLOCK) == APBPeriph_UART3_CLOCK) \
+                                    || ((CLOCK) == APBPeriph_UART2_CLOCK) \
+                                    || ((CLOCK) == APBPeriph_UART1_CLOCK) \
+                                    || ((CLOCK) == APBPeriph_UART0_CLOCK) \
+                                    || ((CLOCK) == APBPeriph_TIMERB_CLOCK) \
+                                    || ((CLOCK) == APBPeriph_ENHTIMER_CLOCK) \
+                                    || ((CLOCK) == APBPeriph_ENHTIMER_PWM1_CLOCK) \
+                                    || ((CLOCK) == APBPeriph_ENHTIMER_PWM0_CLOCK) \
+                                    || ((CLOCK) == APBPeriph_ENHTIMER_PWM3_CLOCK) \
+                                    || ((CLOCK) == APBPeriph_ENHTIMER_PWM2_CLOCK) \
+                                    || ((CLOCK) == APBPeriph_GPIOB_CLOCK) \
+                                    || ((CLOCK) == APBPeriph_GPIOA_CLOCK) \
+                                    || ((CLOCK) == APBPeriph_KEYSCAN_CLOCK) \
+                                    || ((CLOCK) == APBPeriph_QDEC_CLOCK) \
+                                    || ((CLOCK) == APBPeriph_IR_CLOCK) \
+                                    || ((CLOCK) == APBPeriph_I2C3_CLOCK) \
+                                    || ((CLOCK) == APBPeriph_ISO7816_CLOCK) \
+                                    || ((CLOCK) == APBPeriph_SPI2_CLOCK) \
+                                    || ((CLOCK) == APBPeriph_SPI3_CLOCK) \
+                                    || ((CLOCK) == APBPeriph_TIMER_CLOCK) \
+                                    || ((CLOCK) == APBPeriph_CODEC_CLOCK) \
+                                    || ((CLOCK) == APBPeriph_I2S0_CLOCK) \
+                                    || ((CLOCK) == APBPeriph_I2S1_CLOCK) \
+                                    || ((CLOCK) == APBPeriph_I2S2_CLOCK) \
+                                    || ((CLOCK) == APBPeriph_I2S3_CLOCK) \
+                                    || ((CLOCK) == APBPeriph_ACCXTAL_CLOCK)\
+                                    || ((CLOCK) == APBPeriph_ZBMAC_CLOCK) \
+                                    || ((CLOCK) == APBPeriph_BTPHY_CLOCK) \
+                                    || ((CLOCK) == APBPeriph_BTMAC_CLOCK)) //!< Check if the input parameter is valid.
+
+/** End of APB_Peripheral_Clock
+  * \}
+  */
+
+/**
+ * \defgroup    APB_Peripheral_Func APB Peripheral Func
+ * \{
+ * \ingroup     RCC_Exported_Constants
+ */
+#define APBPeriph_SPIC0                 ((uint32_t)(0x800))   //!< SPIC0 function
+#define APBPeriph_SPIC1                 ((uint32_t)(0x801))   //!< SPIC1 function
+#define APBPeriph_SPIC2                 ((uint32_t)(0x802))   //!< SPIC2 function
+
+
+#define APBPeriph_GDMA                  ((uint32_t)(0x3))     //!< GDMA function
+
+#define APBPeriph_SPI0_SLAVE            ((uint32_t)(0x4))     //!< SPI0 slave function
+#define APBPeriph_SPI1                  ((uint32_t)(0x4))     //!< SPI1 function
+#define APBPeriph_SPI0                  ((uint32_t)(0x4))     //!< SPI0 function
+
+#define APBPeriph_I2C3                  ((uint32_t)(0x5))     //!< I2C3 function
+#define APBPeriph_I2C2                  ((uint32_t)(0x5))     //!< I2C2 function
+#define APBPeriph_I2C1                  ((uint32_t)(0x5))     //!< I2C1 function
+#define APBPeriph_I2C0                  ((uint32_t)(0x5))     //!< I2C0 function
+
+
+#define APBPeriph_UART3                 ((uint32_t)(0x6))     //!< UART3 function
+#define APBPeriph_UART2                 ((uint32_t)(0x6))     //!< UART2 function
+#define APBPeriph_UART1                 ((uint32_t)(0x6))     //!< UART1 function
+#define APBPeriph_UART0                 ((uint32_t)(0x6))     //!< UART0 function
+
+
+#define APBPeriph_ACCXTAL               ((uint32_t)(0x7))     //!< ACCXTAL function
+#define APBPeriph_PDCK                  ((uint32_t)(0x7))     //!< PDCK function
+#define APBPeriph_ZBMAC                 ((uint32_t)(0x7))     //!< ZBMAC function
+#define APBPeriph_BTPHY                 ((uint32_t)(0x7))     //!< BTPHY function
+#define APBPeriph_BTMAC                 ((uint32_t)(0x7))     //!< BTMAC function
+#define APBPeriph_SEGCOM                ((uint32_t)(0x7))     //!< SEGCOM function
+#define APBPeriph_SPI3W                 ((uint32_t)(0x7))     //!< SPI3W function
+#define APBPeriph_ETH                   ((uint32_t)(0x7))     //!< ETH function
+#define APBPeriph_PPE                   ((uint32_t)(0x7))     //!< PPE function
+#define APBPeriph_KEYSCAN               ((uint32_t)(0x7))     //!< KEYSCAN function
+#define APBPeriph_HRADC                 ((uint32_t)(0x7))     //!< HRADC function
+#define APBPeriph_ADC                   ((uint32_t)(0x7))     //!< ADC function
+
+#define APBPeriph_CAN                   ((uint32_t)(0x808))   //!< CAN function
+#define APBPeriph_IR                    ((uint32_t)(0x808))   //!< IR function
+#define APBPeriph_ISO7816               ((uint32_t)(0x808))   //!< ISO7816 function
+#define APBPeriph_GPIOB                 ((uint32_t)(0x8))     //!< GPIOB function
+#define APBPeriph_GPIOA                 ((uint32_t)(0x8))     //!< GPIOA function
+
+#define APBPeriph_DISP                  ((uint32_t)(0x809))   //!< DISP function
+#define APBPeriph_IDU                  ((uint32_t)(0x809))    //!< IDU function
+
+#define APBPeriph_TIMER                 ((uint32_t)(0xA))     //!< TIMER function
+
+#define APBPeriph_ENHTIMER              ((uint32_t)(0x11))    //!< ENHTIMER function
+#define APBPeriph_ENHTIMER_PWM1         ((uint32_t)(0x11))    //!< ENHTIMER_PWM1 function
+#define APBPeriph_ENHTIMER_PWM0         ((uint32_t)(0x11))    //!< ENHTIMER_PWM0 function
+#define APBPeriph_ENHTIMER_PWM3         ((uint32_t)(0x12))    //!< ENHTIMER_PWM3 function
+#define APBPeriph_ENHTIMER_PWM2         ((uint32_t)(0x12))    //!< ENHTIMER_PWM2 function
+
+#define APBPeriph_SDHC                  ((uint32_t)(0x81D))   //!< SDHC function
+
+#define APBPeriph_UART5                 ((uint32_t)(0x23))    //!< UART5 function
+#define APBPeriph_UART4                 ((uint32_t)(0x23))    //!< UART4 function
+
+#define APBPeriph_CODEC                 ((uint32_t)(0x100))   //!< CODEC function
+#define APBPeriph_I2S1                  ((uint32_t)(0x100))   //!< I2S1 function
+#define APBPeriph_I2S0                  ((uint32_t)(0x100))   //!< I2S0 function
+
+#define IS_APB_PERIPH(PERIPH) (((PERIPH) == APBPeriph_GDMA) \
+                               || ((PERIPH) == APBPeriph_SPI1) \
+                               || ((PERIPH) == APBPeriph_SPI0_SLAVE) \
+                               || ((PERIPH) == APBPeriph_I2C2) \
+                               || ((PERIPH) == APBPeriph_I2C1) \
+                               || ((PERIPH) == APBPeriph_I2C0) \
+                               || ((PERIPH) == APBPeriph_SPI0) \
+                               || ((PERIPH) == APBPeriph_ADC) \
+                               || ((PERIPH) == APBPeriph_UART5) \
+                               || ((PERIPH) == APBPeriph_UART4) \
+                               || ((PERIPH) == APBPeriph_UART3) \
+                               || ((PERIPH) == APBPeriph_UART2) \
+                               || ((PERIPH) == APBPeriph_UART1) \
+                               || ((PERIPH) == APBPeriph_UART0) \
+                               || ((PERIPH) == APBPeriph_TIMER) \
+                               || ((PERIPH) == APBPeriph_ENHTIMER) \
+                               || ((PERIPH) == APBPeriph_ENHTIMER_PWM1) \
+                               || ((PERIPH) == APBPeriph_ENHTIMER_PWM0) \
+                               || ((PERIPH) == APBPeriph_ENHTIMER_PWM3) \
+                               || ((PERIPH) == APBPeriph_ENHTIMER_PWM2) \
+                               || ((PERIPH) == APBPeriph_GPIOB) \
+                               || ((PERIPH) == APBPeriph_GPIOA) \
+                               || ((PERIPH) == APBPeriph_SDHC) \
+                               || ((PERIPH) == APBPeriph_KEYSCAN) \
+                               || ((PERIPH) == APBPeriph_QDEC) \
+                               || ((PERIPH) == APBPeriph_IR) \
+                               || ((PERIPH) == APBPeriph_I2C3) \
+                               || ((PERIPH) == APBPeriph_ISO7816) \
+                               || ((PERIPH) == APBPeriph_SPI2) \
+                               || ((PERIPH) == APBPeriph_SPI3) \
+                               || ((PERIPH) == APBPeriph_CODEC) \
+                               || ((PERIPH) == APBPeriph_I2S0) \
+                               || ((PERIPH) == APBPeriph_I2S1) \
+                               || ((PERIPH) == APBPeriph_ACCXTAL)\
+                               || ((PERIPH) == APBPeriph_PDCK)\
+                               || ((PERIPH) == APBPeriph_ZBMAC)\
+                               || ((PERIPH) == APBPeriph_BTPHY)\
+                               || ((PERIPH) == APBPeriph_BTMAC)) //!< Check if the input parameter is valid.
+
+/** End of APB_Peripheral_Func
+  * \}
+  */
+
+/*============================================================================*
+ *                          RCC TYPE/API Wrappers
+ *============================================================================*/
+/** \defgroup RCC        RCC
+  * \brief
+  * \{
+  */
+
+/** \defgroup RCC_Exported_Constants RCC Exported Constants
+  * \brief
+  * \{
+  */
+
+/**
+ * \brief       To be compatible with the previous driver.
+ * \defgroup    RCC_Constant_Wrapper RCC Constant Wrapper
+ * \{
+ * \ingroup     RCC_Exported_Constants
+ */
+#define APBPeriph_CAN0                APBPeriph_CAN         //!< The macro is a wrapper for APBPeriph_CAN.
+#define APBPeriph_CAN0_CLOCK          APBPeriph_CAN_CLOCK   //!< The macro is a wrapper for APBPeriph_CAN_CLOCK.
+
+/** End of RCC_Constant_Wrapper
+  * \}
+  */
+
+/** End of RCC_Exported_Constants
+  * \}
+  */
+
+/** End of RCC
+  * \}
+  */
+
+#ifdef  __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* RTL_RCC_DEF_H */
diff --git a/bee/drivers/rcc/src/device/rtl87x2j/rtl_rcc.c b/bee/drivers/rcc/src/device/rtl87x2j/rtl_rcc.c
new file mode 100644
index 00000000..7dc7a1d6
--- /dev/null
+++ b/bee/drivers/rcc/src/device/rtl87x2j/rtl_rcc.c
@@ -0,0 +1,71 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *                           Header Files
+ *============================================================================*/
+#include "rtl_rcc.h"
+
+/*============================================================================*
+ *                           Private Defines
+ *============================================================================*/
+#define RCC_CLOCK_ADDR(n)           (*((volatile uint32_t *)(SYSON_BASE + PCC_REG_PERION_CLK_VPON_REG0X) + n))
+
+/*============================================================================*
+ *                           Public Functions
+ *============================================================================*/
+void RCC_ClockCmd(uint32_t PeriphClock, FunctionalState NewState)
+{
+    /* Check the parameters. */
+    assert_param(IS_PERIPH_CLOCK(PeriphClock));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    uint32_t RegOffset = (PeriphClock >> 24);
+    uint32_t RegClock  = (PeriphClock << 8 >> 8);
+
+    if (NewState == ENABLE)
+    {
+        RCC_CLOCK_ADDR(RegOffset) |= BIT(RegClock);
+
+        if (PeriphClock == TIMER1_CLOCK)
+        {
+            /* TIMER1_Clock_PWM6 TIMER1_Clock_PWM7 TIMER1_Clock_PWM8 */
+            RCC_CLOCK_ADDR(RegOffset + 1) |= (BIT(22) | BIT(23) | BIT(24));
+        }
+        else if (PeriphClock == TIMER2_CLOCK)
+        {
+            /* TIMER2_Clock_PWM */
+            RCC_CLOCK_ADDR(RegOffset) |= BIT(17);
+            /* TIMER2_Clock_GPIO_DBNC_2P4G for GPIO LATCH DEBOUNCE */
+            RCC_CLOCK_ADDR(RegOffset) |= BIT(8);
+        }
+        else if (PeriphClock == BLUEWIZ_CLOCK)
+        {
+            while (PCC_REG_READ_BITFIELD(PCC_REG_PERION_CLK_VPON_REG2X, CLKEN_O_BTMAC) == false);
+        }
+    }
+    else
+    {
+        RCC_CLOCK_ADDR(RegOffset) &= ~BIT(RegClock);
+
+        if (PeriphClock == TIMER1_CLOCK)
+        {
+            /* Clock_TIMER1_PWM6 Clock_TIMER1_PWM7 Clock_TIMER1_PWM8 */
+            RCC_CLOCK_ADDR(RegOffset + 1) &= ~(BIT(22) | BIT(23) | BIT(24));
+        }
+        else if (PeriphClock == TIMER2_CLOCK)
+        {
+            /* Clock_TIMER2_PWM */
+            RCC_CLOCK_ADDR(RegOffset) &= ~BIT(17);
+            /* TIMER2_Clock_GPIO_DBNC_2P4G for GPIO LATCH DEBOUNCE */
+            RCC_CLOCK_ADDR(RegOffset) &= ~ BIT(8);
+        }
+    }
+
+    return;
+}
+
+
diff --git a/bee/drivers/rcc/src/device/rtl87x2j/rtl_rcc_def.h b/bee/drivers/rcc/src/device/rtl87x2j/rtl_rcc_def.h
new file mode 100644
index 00000000..9874787c
--- /dev/null
+++ b/bee/drivers/rcc/src/device/rtl87x2j/rtl_rcc_def.h
@@ -0,0 +1,167 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef RTL_RCC_DEF_H
+#define RTL_RCC_DEF_H
+
+#include "utils/rtl_utils.h"
+#include "address_map.h"
+#include "pcc_reg.h"
+
+#ifdef  __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/*============================================================================*
+ *                          RCC Defines
+ *============================================================================*/
+/** \defgroup RCC         RCC
+  * \brief
+  * \{
+  */
+
+/** \defgroup RCC_Exported_Constants RCC Exported Constants
+  * \brief
+  * \{
+  */
+
+/**
+ * \defgroup RCC_Defines RCC Defines
+ * \{
+ * \ingroup  RCC_Exported_Constants
+ */
+#define RCC_SUPPORT_CLOCKGATECMD_API                   (0)
+#define RCC_SUPPORT_AUTO_CLOCK                         (1)
+
+/** End of RCC_Defines
+  * \}
+  */
+
+/** End of RCC_Exported_Constants
+  * \}
+  */
+
+/** End of RCC
+  * \}
+  */
+/*============================================================================*
+ *                         RCC Private Defines
+ *============================================================================*/
+
+
+/*============================================================================*
+ *                         RCC Constants
+ *============================================================================*/
+/** \defgroup RCC         RCC
+  * \brief
+  * \{
+  */
+
+/** \defgroup RCC_Exported_Constants RCC Exported Constants
+  * \brief
+  * \{
+  */
+
+
+/**
+ * \defgroup    RCC_PERIPH_CLOCK RCC PERIPH CLOCK
+ * \{
+ * \ingroup     RCC_Exported_Constants
+ */
+
+/* 32bit Encoding:    VUTSRQPO NMLKJIHG FEDCBA98 76543210
+ * Positions of FEN:  FFFFFFFF ffffffff ffffffff ffffffff
+ * Note:
+ *   F ~ FEN ADDRESS  8 BIT   24 ~ 31
+ *   f ~ FEN BIT     24 BIT    0 ~ 23
+ */
+#define WDT_CLOCK                   ((uint32_t)((0x00 << 24) | (30)))
+#define MODEMRFCPI_CLOCK            ((uint32_t)((0x00 << 24) | (27)))
+#define DMA_CLOCK                   ((uint32_t)((0x00 << 24) | (26)))
+#define SPI0_CLOCK                  ((uint32_t)((0x00 << 24) | (24)))
+#define SPI1_CLOCK                  ((uint32_t)((0x00 << 24) | (23)))
+#define SPI2_CLOCK                  ((uint32_t)((0x00 << 24) | (22)))
+#define I2S_CLOCK                   ((uint32_t)((0x00 << 24) | (21)))
+#define TIMER0_CLOCK                ((uint32_t)((0x00 << 24) | (20)))
+#define TIMER1_CLOCK                ((uint32_t)((0x00 << 24) | (19)))
+#define TIMER2_CLOCK                ((uint32_t)((0x00 << 24) | (18)))
+#define USB_CLOCK                   ((uint32_t)((0x00 << 24) | (16)))
+#define ADC_CLOCK                   ((uint32_t)((0x00 << 24) | (15)))
+#define I2C0_CLOCK                  ((uint32_t)((0x00 << 24) | (14)))
+#define I2C1_CLOCK                  ((uint32_t)((0x00 << 24) | (13)))
+#define KEYSCAN_CLOCK               ((uint32_t)((0x00 << 24) | (12)))
+#define SPI3W_CLOCK                 ((uint32_t)((0x00 << 24) | (11)))
+#define CAN_CLOCK                   ((uint32_t)((0x00 << 24) | ( 9)))
+#define UART0_CLOCK                 ((uint32_t)((0x00 << 24) | ( 7)))
+#define UART1_CLOCK                 ((uint32_t)((0x00 << 24) | ( 6)))
+#define UART2_CLOCK                 ((uint32_t)((0x00 << 24) | ( 5)))
+#define CODEC_CLOCK                 ((uint32_t)((0x00 << 24) | ( 4)))
+#define TMETER_CLOCK                ((uint32_t)((0x00 << 24) | ( 2)))
+
+#define UART3_CLOCK                 ((uint32_t)((0x01 << 24) | (31)))
+#define GPIOA_CLOCK                 ((uint32_t)((0x01 << 24) | (30)))
+#define GPIOB_CLOCK                 ((uint32_t)((0x01 << 24) | (30)))
+#define IR_CLOCK                    ((uint32_t)((0x01 << 24) | (28)))
+
+#define LPPWM_CLOCK                 ((uint32_t)((0x03 << 24) | (31)))
+#define LPQDEC_CLOCK                ((uint32_t)((0x04 << 24) | (31)))
+#define GRTC_CLOCK                  ((uint32_t)((0x05 << 24) | (31)))
+#define BLUEWIZ_CLOCK               ((uint32_t)((0x06 << 24) | (31)))
+#define RTC_CLOCK                   ((uint32_t)((0x07 << 24) | (31)))
+//#define RAP_CLOCK                   ((uint32_t)((0x08 << 24) | (31)))
+#define LPWDT_CLOCK                 ((uint32_t)((0x0B << 24) | (31)))
+#define LPC_CLOCK                   ((uint32_t)((0x0E << 24) | (31)))
+
+#define IS_PERIPH_CLOCK(CLOCK)      (((CLOCK) == WDT_CLOCK) || \
+                                     ((CLOCK) == MODEMRFCPI_CLOCK) || \
+                                     ((CLOCK) == DMA_CLOCK) || \
+                                     ((CLOCK) == SPI0_CLOCK) || \
+                                     ((CLOCK) == SPI1_CLOCK) || \
+                                     ((CLOCK) == SPI2_CLOCK) || \
+                                     ((CLOCK) == I2S_CLOCK) || \
+                                     ((CLOCK) == TIMER0_CLOCK) || \
+                                     ((CLOCK) == TIMER1_CLOCK) || \
+                                     ((CLOCK) == TIMER2_CLOCK) || \
+                                     ((CLOCK) == USB_CLOCK) || \
+                                     ((CLOCK) == ADC_CLOCK) || \
+                                     ((CLOCK) == I2C0_CLOCK) || \
+                                     ((CLOCK) == I2C1_CLOCK) || \
+                                     ((CLOCK) == KEYSCAN_CLOCK) || \
+                                     ((CLOCK) == SPI3W_CLOCK) || \
+                                     ((CLOCK) == CAN_CLOCK) || \
+                                     ((CLOCK) == UART0_CLOCK) || \
+                                     ((CLOCK) == UART1_CLOCK) || \
+                                     ((CLOCK) == UART2_CLOCK) || \
+                                     ((CLOCK) == CODEC_CLOCK) || \
+                                     ((CLOCK) == TMETER_CLOCK) || \
+                                     ((CLOCK) == UART3_CLOCK) || \
+                                     ((CLOCK) == GPIOA_CLOCK) || \
+                                     ((CLOCK) == GPIOB_CLOCK) || \
+                                     ((CLOCK) == IR_CLOCK) || \
+                                     ((CLOCK) == LPPWM_CLOCK) || \
+                                     ((CLOCK) == LPQDEC_CLOCK) || \
+                                     ((CLOCK) == GRTC_CLOCK) || \
+                                     ((CLOCK) == RTC_CLOCK) || \
+                                     ((CLOCK) == LPWDT_CLOCK) || \
+                                     ((CLOCK) == LPC_CLOCK))
+
+/** End of RCC_PERIPH_CLOCK
+  * \}
+  */
+
+/** End of RCC_Exported_Constants
+  * \}
+  */
+
+/** End of RCC
+  * \}
+  */
+
+#ifdef  __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* RTL_RCC_DEF_H */
diff --git a/bee/drivers/rtc/CMakeLists.txt b/bee/drivers/rtc/CMakeLists.txt
new file mode 100644
index 00000000..74910db5
--- /dev/null
+++ b/bee/drivers/rtc/CMakeLists.txt
@@ -0,0 +1,10 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+if(CONFIG_REALTEK_BEE_COMMON_DRIVER)
+    zephyr_include_directories(inc)
+endif()
+
+if(CONFIG_REALTEK_BEE_RTC OR CONFIG_REALTEK_BEE_GRTC)
+    add_subdirectory(src)
+endif()
diff --git a/bee/drivers/rtc/Kconfig b/bee/drivers/rtc/Kconfig
new file mode 100644
index 00000000..d197ad72
--- /dev/null
+++ b/bee/drivers/rtc/Kconfig
@@ -0,0 +1,14 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config REALTEK_BEE_RTC
+	bool "Realtek Bee RTC driver"
+	default n
+	help
+	  This option enables the RTC driver for Realtek Bee.
+
+config REALTEK_BEE_GRTC
+	bool "Realtek Bee GRTC driver"
+	default n
+	help
+	  This option enables the GRTC driver for Realtek Bee.
diff --git a/bee/drivers/rtc/inc/rtl_grtc.h b/bee/drivers/rtc/inc/rtl_grtc.h
new file mode 100644
index 00000000..0074d144
--- /dev/null
+++ b/bee/drivers/rtc/inc/rtl_grtc.h
@@ -0,0 +1,454 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *               Define to prevent recursive inclusion
+ *============================================================================*/
+#ifndef RTL_GRTC_H
+#define RTL_GRTC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*============================================================================*
+ *                        Header Files
+ *============================================================================*/
+#include "utils/rtl_utils.h"
+#if defined (CONFIG_SOC_SERIES_RTL87X2J)
+#include "rtc/src/device/rtl87x2j/rtl_grtc_def.h"
+#endif
+#if defined (CONFIG_SOC_SERIES_RTL87X3J)
+#include "rtc/src/device/rtl87x3j/rtl_grtc_def.h"
+#endif
+
+/** \defgroup GRTC         GRTC
+  * \{
+  */
+
+/*============================================================================*
+ *                         Constants
+ *============================================================================*/
+/** \defgroup GRTC_Exported_Constants GRTC Exported Constants
+  * \brief
+  * \{
+  */
+
+/**
+ * \defgroup    GRTC_Comparator GRTC Comparator
+ * \{
+ * \ingroup     GRTC_Exported_Constants
+ */
+typedef enum
+{
+    GRTC_COMP0 = 0x00,
+#if (GRTC_COMP_NUM > 1)
+    GRTC_COMP1 = 0x01,
+#endif
+#if (GRTC_COMP_NUM > 2)
+    GRTC_COMP2 = 0x02,
+#endif
+#if (GRTC_COMP_NUM > 3)
+    GRTC_COMP3 = 0x03,
+#endif
+#if (GRTC_COMP_NUM > 4)
+    GRTC_COMP4 = 0x04,
+#endif
+#if (GRTC_COMP_NUM > 5)
+    GRTC_COMP5 = 0x05,
+#endif
+#if (GRTC_COMP_NUM > 6)
+    GRTC_COMP6 = 0x06,
+#endif
+#if (GRTC_COMP_NUM > 7)
+    GRTC_COMP7 = 0x07,
+#endif
+#if (GRTC_COMP_NUM > 8)
+    GRTC_COMP8 = 0x08,
+#endif
+#if (GRTC_COMP_NUM > 9)
+    GRTC_COMP9 = 0x09,
+#endif
+} GRTCCompIndex_TypeDef;
+
+#define IS_GRTC_COMP(COMP)  ((COMP) < GRTC_COMP_NUM)
+
+/** End of GRTC_Comparator
+  * \}
+  */
+
+
+/**
+ * \defgroup    GRTC_Interrupts GRTC Interrupts
+ * \{
+ * \ingroup     GRTC_Exported_Constants
+ */
+#define GRTC_INT_COMP0          BIT0
+#if (GRTC_COMP_NUM > 1)
+#define GRTC_INT_COMP1          BIT1
+#endif
+#if (GRTC_COMP_NUM > 2)
+#define GRTC_INT_COMP2          BIT2
+#endif
+#if (GRTC_COMP_NUM > 3)
+#define GRTC_INT_COMP3          BIT3
+#endif
+#if (GRTC_COMP_NUM > 4)
+#define GRTC_INT_COMP4          BIT4
+#endif
+#if (GRTC_COMP_NUM > 5)
+#define GRTC_INT_COMP5          BIT5
+#endif
+#if (GRTC_COMP_NUM > 6)
+#define GRTC_INT_COMP6          BIT6
+#endif
+#if (GRTC_COMP_NUM > 7)
+#define GRTC_INT_COMP7          BIT7
+#endif
+#if (GRTC_COMP_NUM > 8)
+#define GRTC_INT_COMP8          BIT8
+#endif
+#if (GRTC_COMP_NUM > 9)
+#define GRTC_INT_COMP9          BIT9
+#endif
+
+#define IS_GRTC_INT(INT)  ((INT) & (BIT(GRTC_COMP_NUM)  -1))
+
+/** End of GRTC_Interrupts
+  * \}
+  */
+
+#if (GRTC_SUPPORT_RAP_FUNCTION == 1)
+/**
+ * \defgroup    GRTC_Action GRTC Action
+ * \{
+ * \ingroup     GRTC_Exported_Constants
+ */
+typedef enum
+{
+    GRTC_ACTION_RELOAD_COMP = 0,
+} GRTCAction_TypeDef;
+
+/** End of GRTC_Action
+  * \}
+  */
+#endif
+
+/** End of GRTC_Exported_Constants
+  * \}
+  */
+
+/*============================================================================*
+ *                         Functions
+ *============================================================================*/
+/** \defgroup GRTC_Exported_Functions GRTC Exported Functions
+  * \brief
+  * \{
+  */
+
+/**
+ * \brief     Reset all registers of GRTC.
+ *
+ * \param[in] None.
+ *
+ * \return    None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void grtc_demo(void)
+ * {
+ *     GRTC_DeInit();
+ * }
+ * \endcode
+ */
+void GRTC_DeInit(void);
+
+/**
+ * \brief     Enable or disable the specified GRTC interrupt.
+ *
+ * \param[in] GRTC_INT: Specifies the GRTC interrupt source which to be enabled or disabled.
+ *            This parameter can be any combination of the following values:
+ *            \arg GRTC_INT_COMP0: compare 0 interrupt source
+ *            \arg GRTC_INT_COMP1: compare 1 interrupt source
+ *            \arg GRTC_INT_COMP2: compare 2 interrupt source
+ *            \arg GRTC_INT_COMP3: compare 3 interrupt source
+ *            \arg GRTC_INT_COMP4: compare 4 interrupt source
+ *            \arg GRTC_INT_COMP5: compare 5 interrupt source
+ *            \arg GRTC_INT_COMP6: compare 6 interrupt source
+ *            \arg GRTC_INT_COMP7: compare 7 interrupt source
+ * \param[in] NewState: New state of the specified GRTC interrupt.
+ *            This parameter can be: ENABLE or DISABLE.
+ *
+ * \return    None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_grtc_init(void)
+ * {
+ *     GRTC_INTConfig(GRTC_COMP_INDEX_INT, ENABLE);
+ * }
+ * \endcode
+ */
+void GRTC_INTConfig(uint32_t GRTC_INT, FunctionalState NewState);
+
+/**
+ * \brief  Check whether the specified GRTC interrupt is set.
+ *
+ * \param[in] GRTC_INT: Specifies the GRTC interrupt source to be enabled or disabled.
+ *            This parameter can be any combination of the following values:
+ *            \arg GRTC_INT_COMP0: compare 0 interrupt source
+ *            \arg GRTC_INT_COMP1: compare 1 interrupt source
+ *            \arg GRTC_INT_COMP2: compare 2 interrupt source
+ *            \arg GRTC_INT_COMP3: compare 3 interrupt source
+ *            \arg GRTC_INT_COMP4: compare 4 interrupt source
+ *            \arg GRTC_INT_COMP5: compare 5 interrupt source
+ *            \arg GRTC_INT_COMP6: compare 6 interrupt source
+ *            \arg GRTC_INT_COMP7: compare 7 interrupt source
+ *
+ * \return     The new state of GRTC_INT (SET or RESET).
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void grtc_demo(void)
+ * {
+ *     ITStatus int_status = GRTC_GetINTStatus(GRTC_INT_COMP0);
+ * }
+ * \endcode
+ */
+ITStatus GRTC_GetINTStatus(uint32_t GRTC_INT);
+
+/**
+ * \brief     Clear the interrupt pending bits of GRTC.
+ *
+ * \param[in] GRTC_INT: specifies the GRTC interrupt flag to clear.
+ *            This parameter can be any combination of the following values:
+ *            \arg GRTC_INT_COMP0: compare 0 interrupt source
+ *            \arg GRTC_INT_COMP1: compare 1 interrupt source
+ *            \arg GRTC_INT_COMP2: compare 2 interrupt source
+ *            \arg GRTC_INT_COMP3: compare 3 interrupt source
+ *            \arg GRTC_INT_COMP4: compare 4 interrupt source
+ *            \arg GRTC_INT_COMP5: compare 5 interrupt source
+ *            \arg GRTC_INT_COMP6: compare 6 interrupt source
+ *            \arg GRTC_INT_COMP7: compare 7 interrupt source
+ *
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void grtc_demo(void)
+ * {
+ *     GRTC_ClearINTPendingBit(GRTC_INT_COMP0);
+ * }
+ * \endcode
+ */
+void GRTC_ClearINTPendingBit(uint32_t GRTC_INT);
+
+#if (GRTC_SUPPORT_ERROR_INTERRUPT == 1)
+/**
+ * \brief     Checks whether the specified GRTC error interrupt is set or not.
+ *
+ * \param[in] Index: The comparator number which can be 0 ~ 7.
+ *
+ * \return    The new state of GRTC error interrupt (SET or RESET).
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void grtc_demo(void)
+ * {
+ *     ITStatus int_status = GRTC_GetErrorINTStatus(GRTC_COMP0);
+ * }
+ * \endcode
+ */
+ITStatus GRTC_GetErrorINTStatus(GRTCCompIndex_TypeDef Index);
+
+/**
+ * \brief     Clear the error interrupt pending bits of GRTC.
+ *
+ * \param[in] Index: The comparator number which can be 0 ~ 7.
+ *
+ * \return    None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void grtc_demo(void)
+ * {
+ *     GRTC_ClearErrorINTPendingBit(GRTC_COMP0);
+ * }
+ * \endcode
+ */
+void GRTC_ClearErrorINTPendingBit(GRTCCompIndex_TypeDef Index);
+#endif
+
+#if (GRTC_SUPPORT_FORCE_QACTIVE == 1)
+/**
+ * \brief     Enable or Disable the GRTC force qactive function.
+ *
+ * \param[in] Index: The comparator number which can be 0 ~ 7.
+ * \param[in] NewState: new state of GRTC peripheral.
+ *            This parameter can be the following values:
+ *            \arg ENABLE: Enable GRTC force qactive function.
+ *            \arg DISABLE: Disable GRTC force qactive function.
+ *
+ * \return    None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void grtc_demo(void)
+ * {
+ *     GRTC_ForceQactiveCmd(GRTC_COMP0, ENABLE);
+ * }
+ * \endcode
+ */
+void GRTC_ForceQactiveCmd(GRTCCompIndex_TypeDef Index, FunctionalState NewState);
+#endif
+
+/**
+ * \brief     Set GRTC comparator value.
+ *
+ * \param[in] Index: The comparator number which can be 0 ~ 7.
+ * \param[in] Value: The comparator value.
+ *
+ * \return    None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * #define GRTC_COMP_INDEX          GRTC_COMP3
+ * #define GRTC_COMP_VALUE          (1000)
+ *
+ * void driver_grtc_init(void)
+ * {
+ *     GRTC_SetCompValue(GRTC_COMP_INDEX, GRTC_COMP_VALUE);
+ * }
+ * \endcode
+ */
+void GRTC_SetCompValue(GRTCCompIndex_TypeDef Index, uint32_t Value);
+
+/**
+ * \brief     Get GRTC comparator value.
+ *
+ * \param[in] Index: The comparator number.
+ *
+ * \return    The comparator value.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void grtc_demo(void)
+ * {
+ *     uint32_t data = GRTC_GetCompValue(GRTC_COMP0);
+ * }
+ * \endcode
+ */
+uint32_t GRTC_GetCompValue(GRTCCompIndex_TypeDef Index);
+
+/**
+ * \brief     Enable or Disable the GRTC comparator reload function.
+ *
+ * \param[in] Index: The comparator number which can be 0 ~ 7.
+ * \param[in] NewState: new state of GRTC peripheral.
+ *            This parameter can be the following values:
+ *            \arg ENABLE: start GRTC.
+ *            \arg DISABLE: stop GRTC.
+ *
+ * \return    None.
+ */
+void GRTC_CompReloadCmd(GRTCCompIndex_TypeDef Index, FunctionalState NewState);
+
+/**
+ * \brief     Set GRTC comparator reload value.
+ *
+ * \param[in] Index: The comparator number which can be 0 ~ 7.
+ * \param[in] Value: The comparator reload value.
+ *
+ * \return    None.
+ */
+void GRTC_SetCompReloadValue(GRTCCompIndex_TypeDef Index, uint32_t Value);
+
+/**
+ * \brief     Get GRTC comparator reload value.
+ *
+ * \param[in] Index: The comparator number.
+ *
+ * \return    The comparator reload value.
+ */
+uint32_t GRTC_GetCompReloadValue(GRTCCompIndex_TypeDef Index);
+
+/**
+ * \brief     Enable or Disable the GRTC function of sleep control.
+ *
+ * \param[in] Index: The comparator number which can be 0 ~ 7.
+ * \param[in] NewState: new state of GRTC peripheral.
+ *            This parameter can be the following values:
+ *            \arg ENABLE: start GRTC.
+ *            \arg DISABLE: stop GRTC.
+ *
+ * \return    None.
+ */
+void GRTC_SleepCmd(GRTCCompIndex_TypeDef Index, FunctionalState NewState);
+
+/**
+ * \brief     Get GRTC sleep counter.
+ *
+ * \param[in] Index: The comparator number which can be 0 ~ 7.
+ *
+ * \return    The sleep counter.
+ */
+uint32_t GRTC_GetSleepCounter(GRTCCompIndex_TypeDef Index);
+
+#if (GRTC_SUPPORT_RAP_FUNCTION == 1)
+
+/**
+ * \brief     Enable or Disable the GRTC RAP mode function.
+ *
+ * \param[in] Index: The comparator number which can be 0 ~ 7.
+ * \param[in] NewState: new state of GRTC peripheral.
+ *            This parameter can be the following values:
+ *            \arg ENABLE: start GRTC.
+ *            \arg DISABLE: stop GRTC.
+ *
+ * \return The result of config GRTC RAP mode function.
+ *         \arg true: Config GRTC RAP mode function success.
+ *         \arg false: The GRTC comp is not support RAP mode.
+ */
+bool GRTC_RAPModeCmd(GRTCCompIndex_TypeDef Index, FunctionalState NewState);
+
+/**
+ * \brief     Trigger a GRTC task.
+ *
+ * \param[in] Action: The task to be triggered.
+ *
+ * \return The result of trigger a GRTC task.
+ *         \arg true: Config trigger a GRTC task success.
+ *         \arg false: The GRTC comp is not support to trigger a GRTC task.
+ */
+bool GRTC_ActionTrigger(GRTCCompIndex_TypeDef Index, uint32_t Action);
+
+#endif
+
+/** End of GRTC_Exported_Functions
+  * \}
+  */
+
+/** End of GRTC
+  * \}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RTL_GRTC_H */
+
+
+
diff --git a/bee/drivers/rtc/inc/rtl_rtc.h b/bee/drivers/rtc/inc/rtl_rtc.h
new file mode 100644
index 00000000..2c67b3dc
--- /dev/null
+++ b/bee/drivers/rtc/inc/rtl_rtc.h
@@ -0,0 +1,994 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *               Define to prevent recursive inclusion
+ *============================================================================*/
+#ifndef RTL_RTC_H
+#define RTL_RTC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*============================================================================*
+ *                        Header Files
+ *============================================================================*/
+#include "utils/rtl_utils.h"
+#if defined (CONFIG_SOC_SERIES_RTL87X2G)
+#include "rtc/src/device/rtl87x2g/rtl_rtc_def.h"
+#elif defined (CONFIG_SOC_SERIES_RTL87X3E)
+#include "rtc/src/device/rtl87x3e/rtl_rtc_def.h"
+#elif defined (CONFIG_SOC_SERIES_RTL87X3D)
+#include "rtc/src/device/rtl87x3d/rtl_rtc_def.h"
+#elif defined (CONFIG_SOC_SERIES_RTL87X2J)
+#include "rtc/src/device/rtl87x2j/rtl_rtc_def.h"
+#elif defined (CONFIG_SOC_SERIES_RTL87X3EU)
+#include "rtc/src/device/rtl87x3eu/rtl_rtc_def.h"
+#elif defined (CONFIG_SOC_SERIES_RTL87X3J)
+#include "rtc/src/device/rtl87x3j/rtl_rtc_def.h"
+#endif
+
+/** \defgroup RTC         RTC
+  * \brief
+  * \{
+  */
+
+/*============================================================================*
+ *                         Constants
+ *============================================================================*/
+/** \defgroup RTC_Exported_Constants RTC Exported Constants
+  * \brief
+  * \{
+  */
+
+/**
+ * \defgroup    RTC_Compare_Index RTC Compare Index
+ * \{
+ * \ingroup     RTC_Exported_Constants
+ */
+
+typedef enum
+{
+    RTC_COMP0 = 0x00,
+    RTC_COMP1 = 0x01,
+    RTC_COMP2 = 0x02,
+    RTC_COMP3 = 0x03,
+} RTCCompIndex_TypeDef;
+
+#define IS_RTC_COMPARE(COMP) (((COMP) == RTC_COMP0) || \
+                              ((COMP) == RTC_COMP1) || \
+                              ((COMP) == RTC_COMP2) || \
+                              ((COMP) == RTC_COMP3))
+
+/** End of RTC_Compare_Index
+  * \}
+  */
+
+/**
+ * \defgroup    RTC_Interrupts RTC Interrupts
+ * \{
+ * \ingroup     RTC_Exported_Constants
+ */
+#define RTC_INT_TICK                (BIT8)
+#define RTC_INT_OVERFLOW            (BIT9)
+#define RTC_INT_PRECOMP             (BIT10)
+#define RTC_INT_PRECOMP_COMP3       (BIT11)
+#define RTC_INT_COMP0               (BIT16)
+#define RTC_INT_COMP1               (BIT17)
+#define RTC_INT_COMP2               (BIT18)
+#define RTC_INT_COMP3               (BIT19)
+
+#define IS_RTC_INTERRUPT(INT)       (((INT) == RTC_INT_TICK) || \
+                                     ((INT) == RTC_INT_OVERFLOW) || \
+                                     ((INT) == RTC_INT_PRECOMP) || \
+                                     ((INT) == RTC_INT_PRECOMP_COMP3) || \
+                                     ((INT) == RTC_INT_COMP0) || \
+                                     ((INT) == RTC_INT_COMP1) || \
+                                     ((INT) == RTC_INT_COMP2) || \
+                                     ((INT) == RTC_INT_COMP3))
+
+/** End of RTC_Interrupts
+  * \}
+  */
+
+/**
+ * \defgroup    RTC_WakeUp RTC WakeUp
+ * \{
+ * \ingroup     RTC_Exported_Constants
+ */
+#if (RTC_SUPPORT_WAKEUP_MORE_SOURCE == 1)
+#define RTC_WAKEUP_TICK             (BIT8)
+#define RTC_WAKEUP_OVERFLOW         (BIT9)
+#define RTC_WAKEUP_PRECOMP          (BIT10)
+#define RTC_WAKEUP_PRECOMP_COMP3    (BIT11)
+#endif
+
+#if (RTC_SUPPORT_WAKEUP_COMPARE_GUARDTIME == 1)
+#define RTC_WAKEUP_COMP0GT          (BIT12)
+#define RTC_WAKEUP_COMP1GT          (BIT13)
+#define RTC_WAKEUP_COMP2GT          (BIT14)
+#define RTC_WAKEUP_COMP3GT          (BIT15)
+#endif
+
+#define RTC_WAKEUP_COMP0            (BIT20)
+#define RTC_WAKEUP_COMP1            (BIT21)
+#define RTC_WAKEUP_COMP2            (BIT22)
+#define RTC_WAKEUP_COMP3            (BIT23)
+
+#if (RTC_SUPPORT_WAKEUP_MORE_SOURCE == 1)
+#define IS_RTC_WAKEUP_MORE_SOURCE(WAKEUP) (((WAKEUP) == RTC_WAKEUP_TICK) || \
+                                           ((WAKEUP) == RTC_WAKEUP_OVERFLOW) || \
+                                           ((WAKEUP) == RTC_WAKEUP_PRECOMP) || \
+                                           ((WAKEUP) == RTC_WAKEUP_PRECOMP_COMP3))
+#else
+#define IS_RTC_WAKEUP_MORE_SOURCE(WAKEUP) (0)
+#endif
+
+#if (RTC_SUPPORT_WAKEUP_COMPARE_GUARDTIME == 1)
+#define IS_RTC_WAKEUP_COMPGT(WAKEUP)      (((WAKEUP) == RTC_WAKEUP_COMP0GT) || \
+                                           ((WAKEUP) == RTC_WAKEUP_COMP1GT) || \
+                                           ((WAKEUP) == RTC_WAKEUP_COMP2GT) || \
+                                           ((WAKEUP) == RTC_WAKEUP_COMP3GT))
+#else
+#define IS_RTC_WAKEUP_COMPGT(WAKEUP)      (0)
+#endif
+
+#define IS_RTC_WAKUP(WAKEUP)              (((WAKEUP) == RTC_WAKEUP_COMP0) || \
+                                           ((WAKEUP) == RTC_WAKEUP_COMP1) || \
+                                           ((WAKEUP) == RTC_WAKEUP_COMP2) || \
+                                           ((WAKEUP) == RTC_WAKEUP_COMP3) || \
+                                           (IS_RTC_WAKEUP_MORE_SOURCE(WAKEUP)) || \
+                                           (IS_RTC_WAKEUP_COMPGT(WAKEUP)))
+/** End of RTC_WakeUp
+  * \}
+  */
+
+
+#if (RTC_SUPPORT_RAP_FUNCTION == 1)
+/**
+ * \defgroup    RTC_Action RTC Action
+ * \{
+ * \ingroup     RTC_Exported_Constants
+ */
+typedef enum
+{
+    RTC_ACTION_START = 0,
+    RTC_ACTION_STOP  = 1,
+    RTC_ACTION_CLEAR = 2,
+    RTC_ACTION_RELOAD_COMP0 = 3,
+    RTC_ACTION_RELOAD_COMP1 = 4,
+    RTC_ACTION_RELOAD_COMP2 = 5,
+    RTC_ACTION_RELOAD_COMP3 = 6,
+} RTCAction_TypeDef;
+
+/** End of RTC_Action
+  * \}
+  */
+
+/**
+ * \defgroup    RTC_Event RTC Event
+ * \{
+ * \ingroup     RTC_Exported_Constants
+ */
+typedef enum
+{
+    RTC_EVENT_COMP0 = 0,
+    RTC_EVENT_COMP1 = 1,
+    RTC_EVENT_COMP2 = 2,
+    RTC_EVENT_COMP3 = 3,
+} RTCEvent_TypeDef;
+
+/** End of RTC_Event
+  * \}
+  */
+#endif
+
+/** End of RTC_Exported_Constants
+  * \}
+  */
+
+/*============================================================================*
+ *                         Functions
+ *============================================================================*/
+/** \defgroup RTC_Exported_Functions RTC Exported Functions
+  * \brief
+  * \{
+  */
+/**
+ * \brief     Deinitializes the RTC peripheral registers to their default reset values(turn off clock).
+ *
+ * \param[in] None.
+ *
+ * \return    None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_rtc_init(void)
+ * {
+ *     RTC_DeInit();
+ * }
+ * \endcode
+ */
+void RTC_DeInit(void);
+
+/**
+ * \brief     Set RTC prescaler value.
+ *
+ * \param[in] Vaule: The prescaler value to be set.Should be no more than 12 bits!
+ *
+ * \return    None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * #define RTC_PRESCALER_VALUE     49
+ * #define RTC_COMP_INDEX          RTC_COMP3
+ * #define RTC_COMP_INDEX_INT      RTC_INT_COMP3
+ * #define RTC_COMP_VALUE          (1000)
+ *
+ * void driver_rtc_init(void)
+ * {
+ *     RTC_DeInit();
+ *
+ *     RTC_SetPrescaler(RTC_PRESCALER_VALUE);
+ *     RTC_SetCompValue(RTC_COMP_INDEX, RTC_COMP_VALUE);
+ *
+ *     RTC_MaskINTConfig(RTC_COMP_INDEX_INT, DISABLE);
+ *     RTC_INTConfig(RTC_COMP_INDEX_INT, ENABLE);
+ *
+ *     RTC_NvCmd(ENABLE);
+ *     RTC_Cmd(ENABLE);
+ * }
+ * \endcode
+ */
+void RTC_SetPrescaler(uint16_t Vaule);
+
+/**
+ * \brief     Start or stop RTC peripheral.
+ *
+ * \param[in] NewState: New state of RTC peripheral.
+ *            This parameter can be one of the following values:
+ *            \arg ENABLE: Start RTC.
+ *            \arg DISABLE: Stop RTC.
+ *
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * #define RTC_PRESCALER_VALUE     49
+ * #define RTC_COMP_INDEX          RTC_COMP3
+ * #define RTC_COMP_INDEX_INT      RTC_INT_COMP3
+ * #define RTC_COMP_VALUE          (1000)
+ *
+ * void driver_rtc_init(void)
+ * {
+ *     RTC_DeInit();
+ *
+ *     RTC_SetPrescaler(RTC_PRESCALER_VALUE);
+ *     RTC_SetCompValue(RTC_COMP_INDEX, RTC_COMP_VALUE);
+ *
+ *     RTC_MaskINTConfig(RTC_COMP_INDEX_INT, DISABLE);
+ *     RTC_INTConfig(RTC_COMP_INDEX_INT, ENABLE);
+ *
+ *     RTC_NvCmd(ENABLE);
+ *     RTC_Cmd(ENABLE);
+ * }
+ * \endcode
+ */
+void RTC_Cmd(FunctionalState NewState);
+
+/**
+ * \brief     Enable or disable the specified RTC interrupt source.
+ *
+ * \param[in] RTC_INT: Specifies the RTC interrupt source which to be enabled or disabled.
+ *            This parameter can be any combination of the following values:
+ *            \arg RTC_INT_TICK: Tick interrupt source.
+ *            \arg RTC_INT_OVERFLOW: counter overflow interrupt
+ *            \arg RTC_INT_COMP0: Compare 0 interrupt source.
+ *            \arg RTC_INT_COMP1: Compare 1 interrupt source.
+ *            \arg RTC_INT_COMP2: Compare 2 interrupt source.
+ *            \arg RTC_INT_COMP3: Compare 3 interrupt source.
+ *            \arg RTC_INT_PRECOMP: Prescale compare interrupt source.
+ *            \arg RTC_INT_PRECOMP_COMP3: Prescale & compare 3 interrupt source.
+ * \param[in] NewState: New state of the specified RTC interrupt.
+ *            This parameter can be: ENABLE or DISABLE.
+ *
+ * \return    None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * #define RTC_PRESCALER_VALUE     49
+ * #define RTC_COMP_INDEX          RTC_COMP3
+ * #define RTC_COMP_INDEX_INT      RTC_INT_COMP3
+ * #define RTC_COMP_VALUE          (1000)
+ *
+ * void driver_rtc_init(void)
+ * {
+ *     RTC_DeInit();
+ *
+ *     RTC_SetPrescaler(RTC_PRESCALER_VALUE);
+ *     RTC_SetCompValue(RTC_COMP_INDEX, RTC_COMP_VALUE);
+ *
+ *     RTC_MaskINTConfig(RTC_COMP_INDEX_INT, DISABLE);
+ *     RTC_INTConfig(RTC_COMP_INDEX_INT, ENABLE);
+ *
+ *     RTC_NvCmd(ENABLE);
+ *     RTC_Cmd(ENABLE);
+ * }
+ * \endcode
+ */
+void RTC_INTConfig(uint32_t RTC_INT, FunctionalState NewState);
+
+/**
+ * \brief  Enable or disable the specified RTC wakeup function.
+ *
+ * \param[in] RTC_WAKEUP: specifies the RTC wakeup function to be enabled or disabled.
+ *            This parameter can be any combination of the following values:
+ *            \arg RTC_WAKEUP_TICK: tick wakeup function
+ *            \arg RTC_WAKEUP_OVERFLOW: tick wakeup function
+ *            \arg RTC_WAKEUP_PRECOMP: prescale compare wakeup function
+ *            \arg RTC_WAKEUP_PRECOMP_COMP3: prescale & compare 3 wakeup function
+ *            \arg RTC_WAKEUP_COMP0GT: compare 0 gt wakeup function
+ *            \arg RTC_WAKEUP_COMP1GT: compare 1 gt wakeup function
+ *            \arg RTC_WAKEUP_COMP2GT: compare 2 gt wakeup function
+ *            \arg RTC_WAKEUP_COMP3GT: compare 3 gt wakeup function
+ *            \arg RTC_WAKEUP_COMP0: compare 0 wakeup function
+ *            \arg RTC_WAKEUP_COMP1: compare 1 wakeup function
+ *            \arg RTC_WAKEUP_COMP2: compare 2 wakeup function
+ *            \arg RTC_WAKEUP_COMP3: compare 3 wakeup function
+ * \param[in] NewState: new state of the specified RTC wakeup function.
+ *            This parameter can be: ENABLE or DISABLE.
+ *
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * #define RTC_PRESCALER_VALUE     49
+ * #define RTC_COMP_INDEX          RTC_COMP3
+ * #define RTC_COMP_INDEX_INT      RTC_INT_COMP3
+ * #define RTC_COMP_VALUE          (1000)
+ *
+ * void driver_rtc_init(void)
+ * {
+ *     RTC_DeInit();
+ *
+ *     RTC_SetPrescaler(RTC_PRESCALER_VALUE);
+ *     RTC_SetCompValue(RTC_COMP_INDEX, RTC_COMP_VALUE);
+ *
+ *     RTC_MaskINTConfig(RTC_COMP_INDEX_INT, DISABLE);
+ *     RTC_INTConfig(RTC_COMP_INDEX_INT, ENABLE);
+ *
+ *     RTC_NvCmd(ENABLE);
+ *     RTC_Cmd(ENABLE);
+ * }
+ * \endcode
+ */
+void RTC_WakeUpConfig(uint32_t RTC_WAKEUP, FunctionalState NewState);
+
+/**
+ * \brief     Enable RTC interrupt signal to CPU NVIC.
+ *
+ * \param[in] NewState: Enable or disable RTC interrupt signal to MCU.
+ *            This parameter can be: ENABLE or DISABLE.
+ *
+ * \return    None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * #define RTC_PRESCALER_VALUE     49
+ * #define RTC_COMP_INDEX          RTC_COMP3
+ * #define RTC_COMP_INDEX_INT      RTC_INT_COMP3
+ * #define RTC_COMP_VALUE          (1000)
+ *
+ * void driver_rtc_init(void)
+ * {
+ *     RTC_DeInit();
+ *
+ *     RTC_SetPrescaler(RTC_PRESCALER_VALUE);
+ *     RTC_SetCompValue(RTC_COMP_INDEX, RTC_COMP_VALUE);
+ *
+ *     RTC_MaskINTConfig(RTC_COMP_INDEX_INT, DISABLE);
+ *     RTC_INTConfig(RTC_COMP_INDEX_INT, ENABLE);
+ *
+ *     RTC_NvCmd(ENABLE);
+ *     RTC_Cmd(ENABLE);
+ * }
+ * \endcode
+ */
+void RTC_NVICCmd(FunctionalState NewState);
+
+/**
+ * \brief     Enable or disable system wake up function of RTC.
+ *
+ * \param[in] NewState: new state of the wake up function.
+ *            This parameter can be: ENABLE or DISABLE.
+ *
+ * \return    None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void rtc_demo(void)
+ * {
+ *     RTC_WakeUpConfig(ENABLE);
+ * }
+ * \endcode
+ */
+void RTC_WakeUpCmd(FunctionalState NewState);
+
+/**
+ * \brief  Check whether the specified RTC interrupt is set.
+ *
+ * \param[in] RTC_INT: Specifies the RTC interrupt source to be enabled or disabled.
+ *            This parameter can be any combination of the following values:
+ *            \arg RTC_INT_TICK: RTC tick interrupt source.
+ *            \arg RTC_INT_COMP0: Compare 0 interrupt source.
+ *            \arg RTC_INT_COMP1: Compare 1 interrupt source.
+ *            \arg RTC_INT_COMP2: Compare 2 interrupt source.
+ *            \arg RTC_INT_COMP3: Compare 3 interrupt source.
+ *            \arg RTC_INT_PRECOMP: Prescale compare interrupt source.
+ *            \arg RTC_INT_PRECOMP_COMP3: Prescale & compare 3 interrupt source.
+ *
+ * \return The new state of RTC_INT (SET or RESET).
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void rtc_demo(void)
+ * {
+ *     ITStatus int_status = RTC_GetINTStatus(RTC_INT_COMP0);
+ * }
+ * \endcode
+ */
+ITStatus RTC_GetINTStatus(uint32_t RTC_INT);
+
+/**
+ * \brief  Checks whether the specified RTC wakeup state is set or not.
+ *
+ * \param[in] RTC_WAKEUP: specifies the RTC interrupt source to be enabled or disabled.
+ *            This parameter can be any combination of the following values:
+ *            \arg RTC_WAKEUP_TICK: tick wakeup function
+ *            \arg RTC_WAKEUP_OVERFLOW: tick wakeup function
+ *            \arg RTC_WAKEUP_PRECOMP: prescale compare wakeup function
+ *            \arg RTC_WAKEUP_PRECOMP_COMP3: prescale & compare 3 wakeup function
+ *            \arg RTC_WAKEUP_COMP0GT: compare 0 gt wakeup function
+ *            \arg RTC_WAKEUP_COMP1GT: compare 1 gt wakeup function
+ *            \arg RTC_WAKEUP_COMP2GT: compare 2 gt wakeup function
+ *            \arg RTC_WAKEUP_COMP3GT: compare 3 gt wakeup function
+ *            \arg RTC_WAKEUP_COMP0: compare 0 wakeup function
+ *            \arg RTC_WAKEUP_COMP1: compare 1 wakeup function
+ *            \arg RTC_WAKEUP_COMP2: compare 2 wakeup function
+ *            \arg RTC_WAKEUP_COMP3: compare 3 wakeup function
+ *
+ * \return The new state of RTC_INT (SET or RESET).
+ */
+ITStatus RTC_GetWakeUpStatus(uint32_t RTC_WAKEUP);
+
+/**
+ * \brief     Clear the interrupt pending bits of RTC.
+ *
+ * \param[in] RTC_INT: specifies the RTC interrupt flag to clear.
+ *            This parameter can be any combination of the following values:
+ *            \arg RTC_INT_TICK: RTC tick interrupt source.
+ *            \arg RTC_INT_OVERFLOW: RTC counter overflow interrupt source.
+ *            \arg RTC_INT_COMP0: Compare 0 interrupt source.
+ *            \arg RTC_INT_COMP1: Compare 1 interrupt source.
+ *            \arg RTC_INT_COMP2: Compare 2 interrupt source.
+ *            \arg RTC_INT_COMP3: Compare 3 interrupt source.
+ *            \arg RTC_INT_PRECOMP: Prescale compare interrupt source.
+ *            \arg RTC_INT_PRECOMP_COMP3: Prescale & compare 3 interrupt source.
+ *
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void rtc_demo(void)
+ * {
+ *     RTC_ClearINTPendingBit(RTC_INT_COMP0);
+ * }
+ * \endcode
+ */
+void RTC_ClearINTPendingBit(uint32_t RTC_INT);
+
+/**
+ * \brief  Clear the wakeup status bits of RTC.
+ *
+ * \param[in] RTC_WAKEUP: specifies the RTC wakeup flag to clear.
+ *            This parameter can be any combination of the following values:
+ *            \arg RTC_WAKEUP_TICK: tick wakeup function
+ *            \arg RTC_WAKEUP_OVERFLOW: tick wakeup function
+ *            \arg RTC_WAKEUP_PRECOMP: prescale compare wakeup function
+ *            \arg RTC_WAKEUP_PRECOMP_COMP3: prescale & compare 3 wakeup function
+ *            \arg RTC_WAKEUP_COMP0GT: compare 0 gt wakeup function
+ *            \arg RTC_WAKEUP_COMP1GT: compare 1 gt wakeup function
+ *            \arg RTC_WAKEUP_COMP2GT: compare 2 gt wakeup function
+ *            \arg RTC_WAKEUP_COMP3GT: compare 3 gt wakeup function
+ *            \arg RTC_WAKEUP_COMP0: compare 0 wakeup function
+ *            \arg RTC_WAKEUP_COMP1: compare 1 wakeup function
+ *            \arg RTC_WAKEUP_COMP2: compare 2 wakeup function
+ *            \arg RTC_WAKEUP_COMP3: compare 3 wakeup function
+ *
+ * \return None.
+ */
+void RTC_ClearWakeUpStatusBit(uint32_t RTC_WAKEUP);
+
+/**
+ * \brief     Clear the interrupt pending bit of the select comparator of RTC.
+ *
+ * \param[in] Index: the comparator number.
+ *
+ * \return    None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void rtc_demo(void)
+ * {
+ *     RTC_ClearCompINT(0);
+ * }
+ * \endcode
+ */
+void RTC_ClearCompINT(RTCCompIndex_TypeDef Index);
+
+/**
+ * \brief     Clear the overflow interrupt pending bit of RTC.
+ *
+ * \param[in] None.
+ *
+ * \return    None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void rtc_demo(void)
+ * {
+ *     RTC_ClearOverFlowINT();
+ * }
+ * \endcode
+ */
+void RTC_ClearOverFlowINT(void);
+
+/**
+ * \brief     Clear the tick interrupt pending bit of RTC.
+ *
+ * \param[in] None.
+ *
+ * \return    None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void rtc_demo(void)
+ * {
+ *     RTC_ClearTickINT();
+ * }
+ * \endcode
+ */
+void RTC_ClearTickINT(void);
+
+/**
+ * \brief     Set RTC comparator value.
+ *
+ * \param[in] Index: The comparator number,can be 0 ~ 3.
+ * \param[in] Vaule: The comparator value to be set.Should be no more than 24 bits!
+ *
+ * \return    None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * #define RTC_PRESCALER_VALUE     49
+ * #define RTC_COMP_INDEX          RTC_COMP3
+ * #define RTC_COMP_INDEX_INT      RTC_INT_COMP3
+ * #define RTC_COMP_VALUE          (1000)
+ *
+ * void driver_rtc_init(void)
+ * {
+ *     RTC_DeInit();
+ *
+ *     RTC_SetPrescaler(RTC_PRESCALER_VALUE);
+ *     RTC_SetCompValue(RTC_COMP_INDEX, RTC_COMP_VALUE);
+ *
+ *     RTC_MaskINTConfig(RTC_COMP_INDEX_INT, DISABLE);
+ *     RTC_INTConfig(RTC_COMP_INDEX_INT, ENABLE);
+ *
+ *     RTC_NvCmd(ENABLE);
+ *     RTC_Cmd(ENABLE);
+ * }
+ * \endcode
+ */
+void RTC_SetCompValue(RTCCompIndex_TypeDef Index, uint32_t Vaule);
+
+/**
+ * \brief     Get RTC comparator value.
+ *
+ * \param[in] Index: The comparator number.
+ *
+ * \return    The comparator value.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void rtc_demo(void)
+ * {
+ *     uint32_t data = RTC_GetCompValue(RTC_COMP0);
+ * }
+ * \endcode
+ */
+uint32_t RTC_GetCompValue(RTCCompIndex_TypeDef Index);
+
+/**
+ * \brief     Set RTC prescaler comparator value.
+ *
+ * \param[in] Vaule: The comparator value to be set.Should be no more than 12 bits!
+ *
+ * \return    None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * #define RTC_PRESCALER_VALUE     (3200 - 1)//max 4095
+ * #define RTC_PRECOMP_VALUE       (320)//max 4095
+ * #define RTC_COMP3_VALUE         (10)
+ *
+ * void driver_rtc_init(void)
+ * {
+ *     RTC_DeInit();
+ *
+ *     RTC_SetPrescaler(RTC_PRESCALER_VALUE);
+ *     RTC_SetPreCompValue(RTC_PRECOMP_VALUE);
+ *     RTC_SetCompValue(RTC_COMP3, RTC_COMP3_VALUE);
+ *
+ *     RTC_MaskINTConfig(RTC_INT_PRECOMP_COMP3, DISABLE);
+ *     RTC_INTConfig(RTC_INT_PRECOMP_COMP3, ENABLE);
+ *
+ *     RTC_NvCmd(ENABLE);
+ *     RTC_Cmd(ENABLE);
+ * }
+ * \endcode
+ */
+void RTC_SetPreCompValue(uint32_t Vaule);
+
+/**
+ * \brief     Get RTC prescaler comparator value.
+ *
+ * \param[in] None.
+ *
+ * \return    The prescaler comparator value.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void rtc_demo(void)
+ * {
+ *     uitn32_t data = RTC_GetPreCompValue();
+ * }
+ * \endcode
+ */
+uint32_t RTC_GetPreCompValue(void);
+
+/**
+ * \brief     Reset counter value of RTC.
+ *
+ * \param[in] None.
+ *
+ * \return    None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void rtc_demo(void)
+ * {
+ *     RTC_ResetCounter();
+ *     RTC_Cmd(ENABLE);
+ * }
+ * \endcode
+ */
+void RTC_ResetCounter(void);
+
+/**
+ * \brief     Get counter value of RTC.
+ *
+ * \param[in] None.
+ *
+ * \return    The counter value.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void rtc_demo(void)
+ * {
+ *     uitn32_t counter = RTC_GetCounter();
+ * }
+ * \endcode
+ */
+uint32_t RTC_GetCounter(void);
+
+/**
+ * \brief     Reset prescaler counter value of RTC.
+ *
+ * \param[in] None.
+ *
+ * \return    None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void rtc_demo(void)
+ * {
+ *     RTC_ResetPrescalerCounter();
+ *     RTC_Cmd(ENABLE);
+ * }
+ * \endcode
+ */
+void RTC_ResetPrescalerCounter(void);
+
+/**
+ * \brief     Get prescaler counter value of RTC.
+ *
+ * \param[in] None.
+ *
+ * \return    The prescaler counter value.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void rtc_demo(void)
+ * {
+ *     uitn32_t pre_counter = RTC_GetPreCounter();
+ * }
+ * \endcode
+ */
+uint32_t RTC_GetPreCounter(void);
+
+/**
+ * \brief     Write backup register for store time information.
+ *
+ * \param[in] Vaule: valuer=write to back up reister
+ *
+ * \return    None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void rtc_demo(void)
+ * {
+ *     RTC_SetBackupReg(0x01020304);
+ * }
+ * \endcode
+ */
+void RTC_SetBackupReg(uint32_t Vaule);
+
+/**
+ * \brief     Read backup register.
+ *
+ * \param[in] None.
+ *
+ * \return    Register value.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void rtc_demo(void)
+ * {
+ *     uint32_t reg_data = RTC_GetBackupReg();
+ * }
+ * \endcode
+ */
+uint32_t RTC_GetBackupReg(void);
+
+#if (RTC_SUPPORT_COMPARE_AUTO_RELOAD == 1)
+/**
+ * \brief     Set RTC comparator auto reload value.
+ *
+ * \param[in] Index: The comparator number,can be 0 ~ 3.
+ * \param[in] Vaule: The comparator value to be set.
+ *
+ * \return    None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * #define RTC_COMP_INDEX          RTC_COMP3
+ *
+ * void driver_rtc_init(void)
+ * {
+ *     RTC_SetCompReloadValue(RTC_COMP_INDEX, RTC_COMP_VALUE);
+ * }
+ * \endcode
+ */
+void RTC_SetCompReloadValue(RTCCompIndex_TypeDef Index, uint32_t Vaule);
+
+/**
+ * \brief     Get RTC comparator auto reload value.
+ *
+ * \param[in] Index: The comparator number.
+ *
+ * \return    The comparator value.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void rtc_demo(void)
+ * {
+ *     uint32_t data = RTC_GetCompReloadValue(RTC_COMP0);
+ * }
+ * \endcode
+ */
+uint32_t RTC_GetCompReloadValue(RTCCompIndex_TypeDef Index);
+
+/**
+ * \brief     Enable RTC comparator auto reload.
+ * When the counter value reaches the value of comparator, it automatically adds the compare value,
+ * which equals Current Compare + Reload Value.
+ * \param[in] comp_value: The initialize value of comparator.
+ * \param[in] reload_value: The comparator auto reload value.
+ *
+ *
+ * \return    None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ *
+ * void driver_rtc_init(void)
+ * {
+ *     RTC_EnableCompAutoReload(RTC_COMP0, 1000, 1000);
+ * }
+ * \endcode
+ */
+void RTC_EnableCompAutoReload(RTCCompIndex_TypeDef Index, uint32_t Comp_Value,
+                              uint32_t Reload_Value);
+
+/**
+ * \brief     Disable RTC comparator auto reload.
+ *
+ * \return    None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ *
+ * void driver_rtc_init(void)
+ * {
+ *     RTC_DisableCompAutoReload(RTC_COMP0);
+ * }
+ * \endcode
+ */
+void RTC_DisableCompAutoReload(RTCCompIndex_TypeDef Index);
+#endif
+
+#if (RTC_SUPPORT_WAKEUP_COMPARE_GUARDTIME == 1)
+/**
+ * \brief     Set RTC comparator GT value.
+ *
+ * \param[in] Index: The comparator gt number, can be 0 ~ 3.
+ * \param[in] Vaule: The comparator value to be set.
+ *
+ * \return    None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * #define RTC_PRESCALER_VALUE     49
+ * #define RTC_COMP_INDEX          RTC_COMP3
+ * #define RTC_COMP_INDEX_INT      RTC_INT_COMP3
+ * #define RTC_COMP_VALUE          (1000)
+ *
+ * void driver_rtc_init(void)
+ * {
+ *     RTC_DeInit();
+ *
+ *     RTC_SetPrescaler(RTC_PRESCALER_VALUE);
+ *     RTC_SetCompValue(RTC_COMP_INDEX, RTC_COMP_VALUE);
+ *
+ *     RTC_MaskINTConfig(RTC_COMP_INDEX_INT, DISABLE);
+ *     RTC_INTConfig(RTC_COMP_INDEX_INT, ENABLE);
+ *
+ *     RTC_NvCmd(ENABLE);
+ *     RTC_Cmd(ENABLE);
+ * }
+ * \endcode
+ */
+void RTC_SetCompGTValue(RTCCompIndex_TypeDef Index, uint32_t Vaule);
+
+/**
+ * \brief     Get RTC comparator gt value.
+ *
+ * \param[in] Index: The comparator number 0~3.
+ *
+ * \return    The comparator value.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void rtc_demo(void)
+ * {
+ *     uitn32_t data = RTC_GetCompGTValue(0);
+ * }
+ * \endcode
+ */
+uint32_t RTC_GetCompGTValue(RTCCompIndex_TypeDef Index);
+#endif
+
+#if (RTC_SUPPORT_RAP_FUNCTION == 1)
+
+void RTC_RAPModeCmd(FunctionalState NewState);
+
+void RTC_ActionTrigger(uint32_t Action);
+
+void RTC_ShortcutCmd(uint32_t Action, uint32_t Event, FunctionalState NewState);
+
+#endif
+
+#if (RTC_SUPPORT_CLOCK_IN_FROM_OUTSIDE_PAD == 1)
+/**
+ * \brief  Enable or disable using external clock for RTC.
+ *
+ * \param[in]  ClockIn: Select which externel pad as RTC clock in.
+ *
+ * \param[in] NewState: Newstate of RTC peripheral.
+ *
+ * \return None
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void rtc_demo(void)
+ * {
+ *     RTC_ClockInCmd(PAD_RTC_IN_P0_1, ENABLE);
+ * }
+ * \endcode
+ */
+void RTC_ClockInCmd(RTCClockIn_TypeDef ClockIn, FunctionalState NewState);
+#endif
+
+#if (RTC_SUPPORT_CLOCK_OUT_TO_OUTSIDE_PAD == 1)
+/**
+ * \brief  Enable or disable the clock output to the pad for RTC.
+ *
+ * \param[in]  ClockOut: Select RTC clock output pad and type.
+ *
+ * \param[in] NewState: Newstate of RTC peripheral.
+ *
+ * \return None
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void rtc_demo(void)
+ * {
+ *     RTC_ClockOutCmd(RTC_CLOCK_OUT_P0_1_OSC, ENABLE);
+ * }
+ * \endcode
+ */
+void RTC_ClockOutCmd(RTCClockOut_TypeDef ClockOut, FunctionalState NewState);
+#endif
+
+/** End of RTC_Exported_Functions
+  * \}
+  */
+
+/** End of RTC
+  * \}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RTL_RTC_H */
+
+
+
+
diff --git a/bee/drivers/rtc/src/CMakeLists.txt b/bee/drivers/rtc/src/CMakeLists.txt
new file mode 100644
index 00000000..dd5e359a
--- /dev/null
+++ b/bee/drivers/rtc/src/CMakeLists.txt
@@ -0,0 +1,4 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+add_subdirectory(device)
diff --git a/bee/drivers/rtc/src/device/CMakeLists.txt b/bee/drivers/rtc/src/device/CMakeLists.txt
new file mode 100644
index 00000000..1f5eaa43
--- /dev/null
+++ b/bee/drivers/rtc/src/device/CMakeLists.txt
@@ -0,0 +1,8 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+add_subdirectory_ifdef(CONFIG_REALTEK_BEE_COMMON_DRIVER rtl_common)
+
+add_soc_series_subdir(rtl8752h)
+add_soc_series_subdir(rtl87x2g)
+add_soc_series_subdir(rtl87x2j)
diff --git a/bee/drivers/rtc/src/device/rtl8752h/rtl876x_rtc.c b/bee/drivers/rtc/src/device/rtl8752h/rtl876x_rtc.c
new file mode 100644
index 00000000..7776f418
--- /dev/null
+++ b/bee/drivers/rtc/src/device/rtl8752h/rtl876x_rtc.c
@@ -0,0 +1,412 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "rtl876x_rtc.h"
+
+/* Internal defines ------------------------------------------------------------*/
+#define REG_FAST_WRITE_BASE_ADDR        (0x40000100UL)
+#define REG_RTC_FAST_WDATA              (0x400001F0UL)
+#define REG_RTC_FAST_ADDR               (0x400001F4UL)
+#define REG_RTC_WR_STROBE               (0x400001F8UL)
+
+/**
+  * @brief  Fast write RTC register.
+  * @param  reg_address: the register address.
+  * @param  data: data which write to register.
+  * @return None
+  */
+void RTC_WriteReg(uint32_t reg_address, uint32_t data)
+{
+    static bool is_called = false;
+
+    if (is_called == false)
+    {
+        *((volatile uint32_t *)0x40000014) |= BIT(9);//no need run this every time
+        is_called = true;
+    }
+
+    /* Write data */
+    *((volatile uint32_t *)REG_RTC_FAST_WDATA) = data;
+    /* Write RTC register address. Only offset */
+    *((volatile uint32_t *)REG_RTC_FAST_ADDR) = reg_address - REG_FAST_WRITE_BASE_ADDR;
+    *((volatile uint32_t *)REG_RTC_WR_STROBE) = 1;
+}
+
+/**
+  * @brief  Reset RTC.
+  * @param  None
+  * @return None
+  */
+void RTC_DeInit(void)
+{
+    /* Stop RTC counter */
+    RTC_WriteReg((uint32_t)(&(RTC->CR0)), (RTC->CR0 & RTC_START_CLR));
+
+    /* Disable wakeup signal */
+    RTC_WriteReg((uint32_t)(&(RTC->CR0)), (RTC->CR0 & RTC_NV_EN_CLR));
+    RTC_WriteReg((uint32_t)(&(RTC->CR0)), (RTC->CR0 & RTC_WAKEUP_EN_CLR));
+
+    /* Clear all RTC interrupt & wakeup */
+    RTC_WriteReg((uint32_t)(&(RTC->INT_CLR)), RTC_ALL_INT_CLR_SET | RTC_ALL_WAKEUP_CLR_SET);
+    __NOP();
+    __NOP();
+    RTC_WriteReg((uint32_t)(&(RTC->INT_CLR)), 0);
+
+    /* Clear prescale register */
+    RTC_WriteReg((uint32_t)(&(RTC->PRESCALER)), 0);
+    /* Clear all comparator register */
+    RTC_WriteReg((uint32_t)(&(RTC->COMP0)), 0);
+    RTC_WriteReg((uint32_t)(&(RTC->COMP1)), 0);
+    RTC_WriteReg((uint32_t)(&(RTC->COMP2)), 0);
+    RTC_WriteReg((uint32_t)(&(RTC->COMP3)), 0);
+    RTC_WriteReg((uint32_t)(&(RTC->COMP0GT)), 0);
+    RTC_WriteReg((uint32_t)(&(RTC->COMP1GT)), 0);
+    RTC_WriteReg((uint32_t)(&(RTC->COMP2GT)), 0);
+    RTC_WriteReg((uint32_t)(&(RTC->COMP3GT)), 0);
+    RTC_WriteReg((uint32_t)(&(RTC->PRE_COMP)), 0);
+
+    /* Reset prescale counter and counter */
+    RTC_WriteReg((uint32_t)(&(RTC->CR0)), RTC_PRE_COUNTER_RST_Msk | RTC_COUNTER_RST_Msk);
+    __NOP();
+    __NOP();
+    RTC_WriteReg((uint32_t)(&(RTC->CR0)), 0x0);
+}
+
+/**
+  * @brief  Set RTC prescaler value.
+  * @param  value: the prescaler value to be set.Should be no more than 12 bits!
+  * @return None
+  */
+void RTC_SetPrescaler(uint16_t value)
+{
+    RTC_WriteReg((uint32_t)(&(RTC->PRESCALER)), value & 0xFFF);
+}
+
+/**
+  * @brief  Start or stop RTC peripheral.
+  * @param  NewState: new state of RTC peripheral.
+  *         This parameter can be the following values:
+  *         @arg ENABLE: start RTC.
+  *         @arg DISABLE: stop RTC.
+  * @return None
+  */
+void RTC_Cmd(FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (NewState == ENABLE)
+    {
+        /* Start RTC */
+        RTC_WriteReg((uint32_t)(&(RTC->CR0)), RTC->CR0 | RTC_START_Msk);
+    }
+    else
+    {
+        /* Stop RTC */
+        RTC_WriteReg((uint32_t)(&(RTC->CR0)), RTC->CR0 & RTC_START_CLR);
+    }
+}
+
+/**
+  * @brief  Enable or disable the specified RTC interrupts.
+  * @param  RTC_INT: specifies the RTC interrupt source to be enabled or disabled.
+  *         This parameter can be any combination of the following values:
+  *         @arg RTC_INT_TICK: tick interrupt
+  *         @arg RTC_INT_OVF: counter overflow interrupt
+  *         @arg RTC_INT_PRE_CMP: prescale compare interrupt
+  *         @arg RTC_INT_PRE_CMP3: prescale & compare 3 interrupt
+  *         @arg RTC_INT_CMP0: compare 0 interrupt
+  *         @arg RTC_INT_CMP1: compare 1 interrupt
+  *         @arg RTC_INT_CMP2: compare 2 interrupt
+  *         @arg RTC_INT_CMP3: compare 3 interrupt
+  * @param  NewState: new state of the specified RTC interrupt.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @return None.
+  */
+void RTC_INTConfig(E_RTC_INT RTC_INT, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_RTC_INT(RTC_INT));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (NewState == ENABLE)
+    {
+        /* Enable the selected RTC comparator interrupt */
+        RTC_WriteReg((uint32_t)(&(RTC->CR0)), (RTC->CR0 | RTC_INT));
+    }
+    else
+    {
+        /* Disable the selected RTC comparator interrupt */
+        RTC_WriteReg((uint32_t)(&(RTC->CR0)), (RTC->CR0 & (~RTC_INT)));
+    }
+}
+
+/**
+  * @brief  Enable or disable the specified RTC wakeup function.
+  * @param  RTC_WK: specifies the RTC wakeup function to be enabled or disabled.
+  *         This parameter can be any combination of the following values:
+  *         @arg RTC_WK_TICK: tick wakeup function
+  *         @arg RTC_WK_OVF: tick wakeup function
+  *         @arg RTC_WK_PRE_CMP: prescale compare wakeup function
+  *         @arg RTC_WK_PRE_CMP3: prescale & compare 3 wakeup function
+  *         @arg RTC_WK_COMP0GT: compare 0 gt wakeup function
+  *         @arg RTC_WK_COMP1GT: compare 1 gt wakeup function
+  *         @arg RTC_WK_COMP2GT: compare 2 gt wakeup function
+  *         @arg RTC_WK_COMP3GT: compare 3 gt wakeup function
+  *         @arg RTC_WK_CMP0: compare 0 wakeup function
+  *         @arg RTC_WK_CMP1: compare 1 wakeup function
+  *         @arg RTC_WK_CMP2: compare 2 wakeup function
+  *         @arg RTC_WK_CMP3: compare 3 wakeup function
+  * @param  NewState: new state of the specified RTC wakeup function.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @return None.
+  */
+void RTC_WKConfig(E_RTC_WK RTC_WK, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_RTC_WK(RTC_WK));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (NewState == ENABLE)
+    {
+        /* Enable the selected RTC comparator interrupt */
+        RTC_WriteReg((uint32_t)(&(RTC->CR0)), (RTC->CR0 | RTC_WK));
+    }
+    else
+    {
+        /* Disable the selected RTC comparator interrupt */
+        RTC_WriteReg((uint32_t)(&(RTC->CR0)), (RTC->CR0 & (~RTC_WK)));
+    }
+}
+
+/**
+  * @brief  Enable interrupt signal to CPU NVIC.
+  * @param  This parameter can be: ENABLE or DISABLE.
+  * @return None.
+  */
+void RTC_NvCmd(FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (NewState != DISABLE)
+    {
+        RTC_WriteReg((uint32_t)(&(RTC->CR0)), (RTC->CR0 | RTC_NV_EN_Msk));
+    }
+    else
+    {
+        RTC_WriteReg((uint32_t)(&(RTC->CR0)), (RTC->CR0 & RTC_NV_EN_CLR));
+    }
+}
+
+/**
+ * @brief  Enable or disable system wake up of RTC.
+ * @param  NewState: new state of the wake up function.
+ *         This parameter can be: ENABLE or DISABLE.
+ * @return None
+ */
+void RTC_SystemWakeupConfig(FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (NewState == ENABLE)
+    {
+        /* Enable system wake up */
+        RTC_WriteReg((uint32_t)(&(RTC->CR0)), (RTC->CR0  | RTC_WAKEUP_EN_Msk));
+    }
+    else
+    {
+        /* Disable system wake up */
+        RTC_WriteReg((uint32_t)(&(RTC->CR0)), (RTC->CR0  & RTC_WAKEUP_EN_CLR));
+    }
+}
+
+/**
+  * @brief  Reset counter value of RTC.
+  * @param  None
+  * @return None
+  */
+void RTC_ResetCounter(void)
+{
+    RTC_WriteReg((uint32_t)(&(RTC->CR0)), (RTC->CR0) | RTC_COUNTER_RST_Msk);
+    __NOP();
+    __NOP();
+    RTC_WriteReg((uint32_t)(&(RTC->CR0)), (RTC->CR0) & RTC_COUNTER_RST_CLR);
+}
+
+/**
+  * @brief  Reset prescaler counter value of RTC.
+  * @param  None
+  * @return None
+  */
+void RTC_ResetPrescalerCounter(void)
+{
+    RTC_WriteReg((uint32_t)(&(RTC->CR0)), (RTC->CR0) | RTC_PRE_COUNTER_RST_Msk);
+    __NOP();
+    __NOP();
+    RTC_WriteReg((uint32_t)(&(RTC->CR0)), (RTC->CR0) & RTC_PRE_COUNTER_RST_CLR);
+}
+
+/**
+  * @brief  Checks whether the specified RTC interrupt is set or not.
+  * @param  RTC_INT: specifies the RTC interrupt source to be enabled or disabled.
+  *         This parameter can be any combination of the following values:
+  *         @arg RTC_INT_TICK: RTC tick interrupt source
+  *         @arg RTC_INT_PRE_COMP: prescale compare interrupt source
+  *         @arg RTC_INT_PRE_COMP3: prescale & compare 3 interrupt source
+  *         @arg RTC_INT_COMP0: compare 0 interrupt source
+  *         @arg RTC_INT_COMP1: compare 1 interrupt source
+  *         @arg RTC_INT_COMP2: compare 2 interrupt source
+  *         @arg RTC_INT_COMP3: compare 3 interrupt source
+  * @return The new state of RTC_INT (SET or RESET).
+  */
+ITStatus RTC_GetINTStatus(E_RTC_INT RTC_INT)
+{
+    /* Check the parameters */
+    assert_param(IS_RTC_CONFIG_INT(RTC_INT));
+
+    ITStatus int_status = RESET;
+
+    if ((RTC->INT_SR & ((uint32_t)RTC_INT >> 8)) != (uint32_t)RESET)
+    {
+        int_status = SET;
+    }
+
+    /* Return the RTC_INT status */
+    return  int_status;
+}
+
+/**
+  * @brief  Clear the interrupt pending bits of RTC.
+  * @param  RTC_INT: specifies the RTC interrupt flag to clear.
+  *   This parameter can be any combination of the following values:
+  *     @arg RTC_INT_TICK: RTC tick interrupt source
+  *     @arg RTC_INT_OVF: RTC counter overflow interrupt source
+  *     @arg RTC_INT_PRE_COMP: prescale compare interrupt source
+  *     @arg RTC_INT_PRE_COMP3: prescale & compare 3 interrupt source
+  *     @arg RTC_INT_COMP0: compare 0 interrupt source
+  *     @arg RTC_INT_COMP1: compare 1 interrupt source
+  *     @arg RTC_INT_COMP2: compare 2 interrupt source
+  *     @arg RTC_INT_COMP3: compare 3 interrupt source
+  * @return None
+  */
+void RTC_ClearINTPendingBit(E_RTC_INT RTC_INT)
+{
+    /* Check the parameters */
+    assert_param(IS_RTC_INT(RTC_INT));
+
+    RTC_WriteReg((uint32_t)(&(RTC->INT_CLR)), (uint32_t)RTC_INT >> 8);
+    __NOP();
+    __NOP();
+    RTC_WriteReg((uint32_t)(&(RTC->INT_CLR)), 0);
+}
+
+/**
+  * @brief  Checks whether the specified RTC wakeup state is set or not.
+  * @param  RTC_WK: specifies the RTC interrupt source to be enabled or disabled.
+  *         This parameter can be any combination of the following values:
+  *         @arg RTC_WK_TICK: tick wakeup function
+  *         @arg RTC_WK_OVF: tick wakeup function
+  *         @arg RTC_WK_PRE_CMP: prescale compare wakeup function
+  *         @arg RTC_WK_PRE_CMP3: prescale & compare 3 wakeup function
+  *         @arg RTC_WK_COMP0GT: compare 0 gt wakeup function
+  *         @arg RTC_WK_COMP1GT: compare 1 gt wakeup function
+  *         @arg RTC_WK_COMP2GT: compare 2 gt wakeup function
+  *         @arg RTC_WK_COMP3GT: compare 3 gt wakeup function
+  *         @arg RTC_WK_CMP0: compare 0 wakeup function
+  *         @arg RTC_WK_CMP1: compare 1 wakeup function
+  *         @arg RTC_WK_CMP2: compare 2 wakeup function
+  *         @arg RTC_WK_CMP3: compare 3 wakeup function
+  * @return The new state of RTC_INT (SET or RESET).
+  */
+ITStatus RTC_GetWakeupStatus(E_RTC_WK RTC_WK)
+{
+    /* Check the parameters */
+    assert_param(IS_RTC_CONFIG_INT(RTC_WK));
+
+    ITStatus wakeup_status = RESET;
+
+    if ((RTC->INT_SR & ((uint32_t)RTC_WK >> 8)) != (uint32_t)RESET)
+    {
+        wakeup_status = SET;
+    }
+
+    /* Return the RTC_INT status */
+    return  wakeup_status;
+}
+
+/**
+  * @brief  Clear the wakeup status bits of RTC.
+  * @param  RTC_WK: specifies the RTC wakeup flag to clear.
+  *         This parameter can be any combination of the following values:
+  *         @arg RTC_WK_TICK: tick wakeup function
+  *         @arg RTC_WK_OVF: tick wakeup function
+  *         @arg RTC_WK_PRE_CMP: prescale compare wakeup function
+  *         @arg RTC_WK_PRE_CMP3: prescale & compare 3 wakeup function
+  *         @arg RTC_WK_COMP0GT: compare 0 gt wakeup function
+  *         @arg RTC_WK_COMP1GT: compare 1 gt wakeup function
+  *         @arg RTC_WK_COMP2GT: compare 2 gt wakeup function
+  *         @arg RTC_WK_COMP3GT: compare 3 gt wakeup function
+  *         @arg RTC_WK_CMP0: compare 0 wakeup function
+  *         @arg RTC_WK_CMP1: compare 1 wakeup function
+  *         @arg RTC_WK_CMP2: compare 2 wakeup function
+  *         @arg RTC_WK_CMP3: compare 3 wakeup function
+  * @return None
+  */
+void RTC_ClearWakeupStatusBit(E_RTC_WK RTC_WK)
+{
+    /* Check the parameters */
+    assert_param(IS_RTC_WK(RTC_WK));
+
+    RTC_WriteReg((uint32_t)(&(RTC->INT_CLR)), (uint32_t)RTC_WK >> 8);
+    __NOP();
+    __NOP();
+    RTC_WriteReg((uint32_t)(&(RTC->INT_CLR)), 0);
+}
+
+/**
+  * @brief  Clear the interrupt pending bit of the select comparator of RTC.
+  * @param  index: the comparator number 0~3.
+  * @return None
+  */
+void RTC_ClearCompINT(E_RTC_COMP_INDEX index)
+{
+    RTC_WriteReg((uint32_t)(&(RTC->INT_CLR)), BIT(RTC_COMP0_CLR_Pos + index));
+    __NOP();
+    __NOP();
+    RTC_WriteReg((uint32_t)(&(RTC->INT_CLR)), 0);
+}
+
+/**
+  * @brief  Clear the overflow interrupt pending bit of RTC.
+  * @param  None
+  * @return None
+  */
+void RTC_ClearOverFlowINT(void)
+{
+    RTC_WriteReg((uint32_t)(&(RTC->INT_CLR)), RTC_OVERFLOW_CLR_SET);
+    __NOP();
+    __NOP();
+    RTC_WriteReg((uint32_t)(&(RTC->INT_CLR)), 0);
+}
+
+/**
+  * @brief  Clear the tick interrupt pending bit of RTC.
+  * @param  None
+  * @return None
+  */
+void RTC_ClearTickINT(void)
+{
+    RTC_WriteReg((uint32_t)(&(RTC->INT_CLR)), RTC_TICK_CLR_SET);
+    __NOP();
+    __NOP();
+    RTC_WriteReg((uint32_t)(&(RTC->INT_CLR)), 0);
+}
+
+
+
diff --git a/bee/drivers/rtc/src/device/rtl8752h/rtl876x_rtc.h b/bee/drivers/rtc/src/device/rtl8752h/rtl876x_rtc.h
new file mode 100644
index 00000000..27a92e29
--- /dev/null
+++ b/bee/drivers/rtc/src/device/rtl8752h/rtl876x_rtc.h
@@ -0,0 +1,1021 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _RTL876X_RTC_H_
+#define _RTL876X_RTC_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup  IO          Peripheral Drivers
+ * \defgroup    RTC         RTC
+ *
+ * \brief       Manage the RTC peripheral functions.
+ *
+ * \ingroup     IO
+ */
+
+
+/*============================================================================*
+ *                         Includes
+ *============================================================================*/
+#include "rtl876x.h"
+#include "rtl876x_alias.h"
+
+
+/*============================================================================*
+ *                         Registers Definitions
+ *============================================================================*/
+
+/* Peripheral: RTC */
+/* Description: Real time counter register defines */
+
+/* Register: CR0 */
+/* Description: RTC Control Register 0. Offset: 0x00. Address: 0x40000100. */
+
+/* CR0[31] :RTC_RST. Enable interrupt signal to MCU.  0x1: Enable. 0x0: Disable. */
+#define RTC_RST_Pos                     (31UL)
+#define RTC_RST_Msk                     (0x1UL << RTC_RST_Pos)
+#define RTC_RST_CLR                     (~(RTC_RST_Msk))
+
+/* CR0[30] :RTC_NV_EN. Enable interrupt signal to MCU.  0x1: Enable. 0x0: Disable. */
+#define RTC_NV_EN_Pos                   (30UL)
+#define RTC_NV_EN_Msk                   (0x1UL << RTC_NV_EN_Pos)
+#define RTC_NV_EN_CLR                   (~(RTC_NV_EN_Msk))
+
+/* CR0[29] :RTC_WAKEUP_EN. Enable wakeup signal to AON register.  0x1: Enable. 0x0: Disable. */
+#define RTC_WAKEUP_EN_Pos               (29UL)
+#define RTC_WAKEUP_EN_Msk               (0x1UL << RTC_WAKEUP_EN_Pos)
+#define RTC_WAKEUP_EN_CLR               (~(RTC_WAKEUP_EN_Msk))
+
+/* CR0[23] :RTC_COMP3_WAKEUP_EN. Enable or disable compare3 wakeup function.  0x1: Enable. 0x0: Disable. */
+#define RTC_COMP3_WAKEUP_EN_Pos         (23UL)
+#define RTC_COMP3_WAKEUP_EN_Msk         (0x1UL << RTC_COMP3_WAKEUP_EN_Pos)
+#define RTC_COMP3_WAKEUP_EN_Clr         (~(RTC_COMP3_WAKEUP_EN_Msk))
+
+/* CR0[22] :RTC_INT_EN. Enable or disable compare2 wakeup function.  0x1: Enable. 0x0: Disable. */
+#define RTC_COMP2_WAKEUP_EN_Pos         (22UL)
+#define RTC_COMP2_WAKEUP_EN_Msk         (0x1UL << RTC_COMP2_WAKEUP_EN_Pos)
+#define RTC_COMP2_WAKEUP_EN_Clr         (~(RTC_COMP2_WAKEUP_EN_Msk))
+
+/* CR0[21] :RTC_INT_EN. Enable or disable compare1 wakeup function.  0x1: Enable. 0x0: Disable. */
+#define RTC_COMP1_WAKEUP_EN_Pos         (21UL)
+#define RTC_COMP1_WAKEUP_EN_Msk         (0x1UL << RTC_COMP1_WAKEUP_EN_Pos)
+#define RTC_COMP1_WAKEUP_EN_Clr         (~(RTC_COMP1_WAKEUP_EN_Msk))
+
+/* CR0[20] :RTC_INT_EN. Enable or disable compare0 wakeup function.  0x1: Enable. 0x0: Disable. */
+#define RTC_COMP0_WAKEUP_EN_Pos         (20UL)
+#define RTC_COMP0_WAKEUP_EN_Msk         (0x1UL << RTC_COMP0_WAKEUP_EN_Pos)
+#define RTC_COMP0_WAKEUP_EN_Clr         (~(RTC_COMP0_WAKEUP_EN_Msk))
+
+/* CR0[19] :RTC_INT_EN. Enable or disable compare3 interrupt.  0x1: Enable. 0x0: Disable. */
+#define RTC_INT_COMP3_EN_Pos            (19UL)
+#define RTC_INT_COMP3_EN_Msk            (0x1UL << RTC_INT_COMP3_EN_Pos)
+#define RTC_INT_COMP3_EN_Clr            (~(RTC_INT_COMP3_EN_Msk))
+
+/* CR0[18] :RTC_INT_EN. Enable or disable compare2 interrupt.  0x1: Enable. 0x0: Disable. */
+#define RTC_INT_COMP2_EN_Pos            (18UL)
+#define RTC_INT_COMP2_EN_Msk            (0x1UL << RTC_INT_COMP2_EN_Pos)
+#define RTC_INT_COMP2_EN_Clr            (~(RTC_INT_COMP2_EN_Msk))
+
+/* CR0[17] :RTC_INT_EN. Enable or disable compare1 interrupt.  0x1: Enable. 0x0: Disable. */
+#define RTC_INT_COMP1_EN_Pos            (17UL)
+#define RTC_INT_COMP1_EN_Msk            (0x1UL << RTC_INT_COMP1_EN_Pos)
+#define RTC_INT_COMP1_EN_Clr            (~(RTC_INT_COMP1_EN_Msk))
+
+/* CR0[16] :RTC_INT_EN. Enable or disable compare0 interrupt.  0x1: Enable. 0x0: Disable. */
+#define RTC_INT_COMP0_EN_Pos            (16UL)
+#define RTC_INT_COMP0_EN_Msk            (0x1UL << RTC_INT_COMP0_EN_Pos)
+#define RTC_INT_COMP0_EN_Clr            (~(RTC_INT_COMP0_EN_Msk))
+
+/* CR0[15] :RTC_INT_EN. Enable or disable compare3gt interrupt.  0x1: Enable. 0x0: Disable. */
+#define RTC_COMP3GT_WAKEUP_EN_Pos       (15UL)
+#define RTC_COMP3GT_WAKEUP_EN_Msk       (0x1UL << RTC_COMP3GT_WAKEUP_EN_Pos)
+#define RTC_COMP3GT_WAKEUP_EN_Clr       (~(RTC_COMP3GT_WAKEUP_EN_Msk))
+
+/* CR0[14] :RTC_INT_EN. Enable or disable compare2gt interrupt.  0x1: Enable. 0x0: Disable. */
+#define RTC_COMP2GT_WAKEUP_EN_Pos       (14UL)
+#define RTC_COMP2GT_WAKEUP_EN_Msk       (0x1UL << RTC_COMP2GT_WAKEUP_EN_Pos)
+#define RTC_COMP2GT_WAKEUP_EN_Clr       (~(RTC_COMP2GT_WAKEUP_EN_Msk))
+
+/* CR0[13] :RTC_INT_EN. Enable or disable compare1gt interrupt.  0x1: Enable. 0x0: Disable. */
+#define RTC_COMP1GT_WAKEUP_EN_Pos       (13UL)
+#define RTC_COMP1GT_WAKEUP_EN_Msk       (0x1UL << RTC_COMP1GT_WAKEUP_EN_Pos)
+#define RTC_COMP1GT_WAKEUP_EN_Clr       (~(RTC_COMP1GT_WAKEUP_EN_Msk))
+
+/* CR0[12] :RTC_INT_EN. Enable or disable compare0gt interrupt.  0x1: Enable. 0x0: Disable. */
+#define RTC_COMP0GT_WAKEUP_EN_Pos       (12UL)
+#define RTC_COMP0GT_WAKEUP_EN_Msk       (0x1UL << RTC_COMP0GT_WAKEUP_EN_Pos)
+#define RTC_COMP0GT_WAKEUP_EN_Clr       (~(RTC_COMP0GT_WAKEUP_EN_Msk))
+
+/* CR0[11] :RTC_INT_EN. Enable or disable prescale & comp3 interrupt.  0x1: Enable. 0x0: Disable. */
+#define RTC_INT_PRE_COMP3_EN_Pos         (11UL)
+#define RTC_INT_PRE_COMP3_EN_Msk         (0x1UL << RTC_INT_PRE_COMP3_EN_Pos)
+#define RTC_INT_PRE_COMP3_EN_Clr         (~(RTC_INT_PRE_COMP3_EN_Msk))
+
+/* CR0[10] :RTC_INT_EN. Enable or disable prescale comp interrupt.  0x1: Enable. 0x0: Disable. */
+#define RTC_INT_PRE_COMP_EN_Pos          (10UL)
+#define RTC_INT_PRE_COMP_EN_Msk          (0x1UL << RTC_INT_PRE_COMP_EN_Pos)
+#define RTC_INT_PRE_COMP_EN_Clr          (~(RTC_INT_PRE_COMP_EN_Msk))
+
+/* CR0[9] :RTC_MASK_TICK_INT. Mask RTC tick interrupt.  0x1: Unmask. 0x0: Mask. */
+#define RTC_INT_OVERFLOW_EN_Pos         (9UL)
+#define RTC_INT_OVERFLOW_EN_Msk         (0x1UL << RTC_INT_OVERFLOW_EN_Pos)
+#define RTC_INT_OVERFLOW_EN_Clr         (~(RTC_INT_OVERFLOW_EN_Msk))
+
+/* CR0[8] :RTC_INT_EN. Enable or disable tick interrupt.  0x1: Enable. 0x0: Disable. */
+#define RTC_INT_TICK_EN_Pos             (8UL)
+#define RTC_INT_TICK_EN_Msk             (0x1UL << RTC_INT_TICK_EN_Pos)
+#define RTC_INT_TICK_EN_Clr             (~(RTC_INT_TICK_EN_Msk))
+
+/* CR0[2] :RTC_PRE_COUNTER_RST. Reset Prescale Counter. 0x1: Reset Counter to 0. */
+#define RTC_PRE_COUNTER_RST_Pos         (2UL)
+#define RTC_PRE_COUNTER_RST_Msk         (0x1UL << RTC_PRE_COUNTER_RST_Pos)
+#define RTC_PRE_COUNTER_RST_CLR         (~(RTC_PRE_COUNTER_RST_Msk))
+
+/* CR0[1] :RTC_COUNTER_RST. Reset 24bit-RTC Counter. 0x1: Reset Counter to 0. */
+#define RTC_COUNTER_RST_Pos             (1UL)
+#define RTC_COUNTER_RST_Msk             (0x1UL << RTC_COUNTER_RST_Pos)
+#define RTC_COUNTER_RST_CLR             (~(RTC_COUNTER_RST_Msk))
+
+/* CR0[0] :RTC_START. Start or stop RTC 24bit-RTC Counter. 0x1: Start 24bit-RTC Counter.0x0: Stop 24bit-RTC Counter. */
+#define RTC_START_Pos                   (0UL)
+#define RTC_START_Msk                   (0x1UL << RTC_START_Pos)
+#define RTC_START_CLR                   (~(RTC_START_Msk))
+
+/* Register: INT_CLR */
+/* Description: Interrupt clear register. Offset: 0x04. Address: 0x40000104. */
+
+/* INT_CLR[15] :RTC_COMP3_WK_CLR. Clear Interrupt Status of Comparator1. */
+/* This status is cleared by software. Write 1 then write 0 after 2T to clear. */
+#define RTC_COMP3_WK_CLR_Pos            (15UL)
+#define RTC_COMP3_WK_CLR_SET            (0x1UL << RTC_COMP3_WK_CLR_Pos)
+#define RTC_COMP3_WK_CLR_RESET          (~(RTC_COMP3_WK_CLR_SET))
+
+/* INT_CLR[14] :RTC_COMP2_WK_CLR. Clear Interrupt Status of Comparator1. */
+/* This status is cleared by software. Write 1 then write 0 after 2T to clear. */
+#define RTC_COMP2_WK_CLR_Pos            (14UL)
+#define RTC_COMP2_WK_CLR_SET            (0x1UL << RTC_COMP2_WK_CLR_Pos)
+#define RTC_COMP2_WK_CLR_RESET          (~(RTC_COMP2_WK_CLR_SET))
+
+/* INT_CLR[13] :RTC_COMP1_WK_CLR. Clear Interrupt Status of Comparator1. */
+/* This status is cleared by software. Write 1 then write 0 after 2T to clear. */
+#define RTC_COMP1_WK_CLR_Pos            (13UL)
+#define RTC_COMP1_WK_CLR_SET            (0x1UL << RTC_COMP1_WK_CLR_Pos)
+#define RTC_COMP1_WK_CLR_RESET          (~(RTC_COMP1_WK_CLR_SET))
+
+/* INT_CLR[12] :RTC_COMP0_WK_CLR. Clear Interrupt Status of Comparator0. */
+/* This status is cleared by software. Write 1 then write 0 after 2T to clear. */
+#define RTC_COMP0_WK_CLR_Pos            (12UL)
+#define RTC_COMP0_WK_CLR_SET            (0x1UL << RTC_COMP0_WK_CLR_Pos)
+#define RTC_COMP0_WK_CLR_RESET          (~(RTC_COMP0_WK_CLR_SET))
+
+/* INT_CLR[11] :RTC_COMP3_CLR. Clear Interrupt Status of Comparator1. */
+/* This interrupt is cleared by software. Write 1 then write 0 after 2T to clear. */
+#define RTC_COMP3_CLR_Pos               (11UL)
+#define RTC_COMP3_CLR_SET               (0x1UL << RTC_COMP3_CLR_Pos)
+#define RTC_COMP3_CLR_RESET             (~(RTC_COMP3_CLR_SET))
+
+/* INT_CLR[10] :RTC_COMP2_CLR. Clear Interrupt Status of Comparator1. */
+/* This interrupt is cleared by software. Write 1 then write 0 after 2T to clear. */
+#define RTC_COMP2_CLR_Pos               (10UL)
+#define RTC_COMP2_CLR_SET               (0x1UL << RTC_COMP2_CLR_Pos)
+#define RTC_COMP2_CLR_RESET             (~(RTC_COMP2_CLR_SET))
+
+/* INT_CLR[9] :RTC_COMP1_CLR. Clear Interrupt Status of Comparator1. */
+/* This interrupt is cleared by software. Write 1 then write 0 after 2T to clear. */
+#define RTC_COMP1_CLR_Pos               (9UL)
+#define RTC_COMP1_CLR_SET               (0x1UL << RTC_COMP1_CLR_Pos)
+#define RTC_COMP1_CLR_RESET             (~(RTC_COMP1_CLR_SET))
+
+/* INT_CLR[8] :RTC_COMP0_CLR. Clear Interrupt Status of Comparator0. */
+/* This interrupt is cleared by software. Write 1 then write 0 after 2T to clear. */
+#define RTC_COMP0_CLR_Pos               (8UL)
+#define RTC_COMP0_CLR_SET               (0x1UL << RTC_COMP0_CLR_Pos)
+#define RTC_COMP0_CLR_RESET             (~(RTC_COMP0_CLR_SET))
+
+/* INT_CLR[7] :RTC_COMP3_CLR. Clear Interrupt Status of Comparator1. */
+/* This interrupt is cleared by software. Write 1 then write 0 after 2T to clear. */
+#define RTC_COMP3GT_CLR_Pos             (7UL)
+#define RTC_COMP3GT_CLR_SET             (0x1UL << RTC_COMP3GT_CLR_Pos)
+#define RTC_COMP3GT_CLR_RESET           (~(RTC_COMP3GT_CLR_SET))
+
+/* INT_CLR[6] :RTC_COMP2GT_CLR. Clear Interrupt Status of Comparator2. */
+/* This interrupt is cleared by software. Write 1 then write 0 after 2T to clear. */
+#define RTC_COMP2GT_CLR_Pos             (6UL)
+#define RTC_COMP2GT_CLR_SET             (0x1UL << RTC_COMP2GT_CLR_Pos)
+#define RTC_COMP2GT_CLR_RESET           (~(RTC_COMP2GT_CLR_SET))
+
+/* INT_CLR[5] :RTC_COMP1GT_CLR. Clear Interrupt Status of Comparator1. */
+/* This interrupt is cleared by software. Write 1 then write 0 after 2T to clear. */
+#define RTC_COMP1GT_CLR_Pos             (5UL)
+#define RTC_COMP1GT_CLR_SET             (0x1UL << RTC_COMP1GT_CLR_Pos)
+#define RTC_COMP1GT_CLR_RESET           (~(RTC_COMP1GT_CLR_SET))
+
+/* INT_CLR[4] :RTC_COMP0GT_CLR. Clear Interrupt Status of Comparator0. */
+/* This interrupt is cleared by software. Write 1 then write 0 after 2T to clear. */
+#define RTC_COMP0GT_CLR_Pos             (4UL)
+#define RTC_COMP0GT_CLR_SET             (0x1UL << RTC_COMP0GT_CLR_Pos)
+#define RTC_COMP0GT_CLR_RESET           (~(RTC_COMP0GT_CLR_SET))
+
+/* INT_CLR[3] :RTC_PRE_COMP3_CLR. Clear Interrupt Status of prescale and prescale_comp3. */
+/* This interrupt is cleared by software. Write 1 then write 0 after 2T to clear. */
+#define RTC_PRE_COMP3_CLR_Pos           (3UL)
+#define RTC_PRE_COMP3_CLR_SET           (0x1UL << RTC_PRE_COMP3_CLR_Pos)
+#define RTC_PRE_COMP3_CLR_RESET         (~(RTC_PRE_COMP3_CLR_SET))
+
+/* INT_CLR[6] :RTC_PRE_COMP_CLR. Clear Interrupt Status of Comparator1. */
+/* This interrupt is cleared by software. Write 1 then write 0 after 2T to clear. */
+#define RTC_PRE_COMP_CLR_Pos            (2UL)
+#define RTC_PRE_COMP_CLR_SET            (0x1UL << RTC_PRE_COMP_CLR_Pos)
+#define RTC_PRE_COMP_CLR_RESET          (~(RTC_PRE_COMP_CLR_SET))
+
+/* INT_CLR[1] :RTC_OVERFLOW_CLR. Clear Interrupt Status of Overflow. */
+/* This interrupt is cleared by software. Write 1 then write 0 after 2T to clear. */
+#define RTC_OVERFLOW_CLR_Pos            (1UL)
+#define RTC_OVERFLOW_CLR_SET            (0x1UL << RTC_OVERFLOW_CLR_Pos)
+#define RTC_OVERFLOW_CLR_RESET          (~(RTC_OVERFLOW_CLR_SET))
+
+/* INT_CLR[0] :RTC_TICK_CLR. Clear Interrupt Status of Tick. */
+/* This interrupt is cleared by software. Write 1 then write 0 after 2T to clear. */
+#define RTC_TICK_CLR_Pos                (0UL)
+#define RTC_TICK_CLR_SET                (0x1UL << RTC_TICK_CLR_Pos)
+#define RTC_TICK_CLR_RESET              (~(RTC_TICK_CLR_SET))
+
+#define RTC_COMP_INT_EN_OFFSET          (RTC_INT_COMP0_EN_Pos - RTC_COMP0_CLR_Pos)
+#define RTC_PRE_COMP_INT_EN_OFFSET      (RTC_INT_PRE_COMP_EN_Pos - RTC_PRE_COMP_CLR_Pos)
+
+
+/* Clear all interrupts */
+#define RTC_ALL_INT_CLR_SET             (RTC_PRE_COMP3_CLR_SET | RTC_PRE_COMP_CLR_SET | \
+                                         RTC_COMP3_CLR_SET | RTC_COMP2_CLR_SET | \
+                                         RTC_COMP1_CLR_SET | RTC_COMP0_CLR_SET | \
+                                         RTC_OVERFLOW_CLR_SET | RTC_TICK_CLR_SET)
+
+/* Clear all wakeups */
+#define RTC_ALL_WAKEUP_CLR_SET          (RTC_COMP3_WK_CLR_SET | RTC_COMP2_WK_CLR_SET | \
+                                         RTC_COMP1_WK_CLR_SET | RTC_COMP0_WK_CLR_SET | \
+                                         RTC_COMP3GT_CLR_SET | RTC_COMP2GT_CLR_SET | \
+                                         RTC_COMP1GT_CLR_SET | RTC_COMP0GT_CLR_SET)
+
+/*============================================================================*
+ *                         Constants
+ *============================================================================*/
+/**
+ * \defgroup    RTC_Exported_Constants RTC Exported Constants
+ *
+ * \ingroup     RTC
+ */
+
+/**
+ * \defgroup    RTC_Interrupt_Definition RTC Interrupt Definition
+ * \{
+ * \ingroup     RTC_Exported_Constants
+ */
+typedef enum
+{
+    RTC_INT_TICK        = RTC_INT_TICK_EN_Msk,
+    RTC_INT_OVF         = RTC_INT_OVERFLOW_EN_Msk,
+    RTC_INT_PRE_COMP    = RTC_INT_PRE_COMP_EN_Msk,
+    RTC_INT_PRE_COMP3   = RTC_INT_PRE_COMP3_EN_Msk,
+    RTC_INT_COMP0       = RTC_INT_COMP0_EN_Msk,
+    RTC_INT_COMP1       = RTC_INT_COMP1_EN_Msk,
+    RTC_INT_COMP2       = RTC_INT_COMP2_EN_Msk,
+    RTC_INT_COMP3       = RTC_INT_COMP3_EN_Msk,
+} E_RTC_INT;
+
+#define IS_RTC_INT(INT) (((INT) == RTC_INT_TICK) || \
+                         ((INT) == RTC_INT_OVF) || \
+                         ((INT) == RTC_INT_COMP0) || \
+                         ((INT) == RTC_INT_COMP1) || \
+                         ((INT) == RTC_INT_COMP2) || \
+                         ((INT) == RTC_INT_COMP3) || \
+                         ((INT) == RTC_INT_PRE_COMP) || \
+                         ((INT) == RTC_INT_PRE_COMP3))
+/** \} */
+
+/**
+ * \defgroup    RTC_Wakeup_Definition RTC Wakeup Definition
+ * \{
+ * \ingroup     RTC_Exported_Constants
+ */
+typedef enum
+{
+    RTC_WK_TICK         = RTC_INT_TICK_EN_Msk,
+    RTC_WK_OVF          = RTC_INT_OVERFLOW_EN_Msk,
+    RTC_WK_PRE_COMP     = RTC_INT_PRE_COMP_EN_Msk,
+    RTC_WK_PRE_COMP3    = RTC_INT_PRE_COMP3_EN_Msk,
+    RTC_WK_COMP0GT      = RTC_COMP0GT_WAKEUP_EN_Msk,
+    RTC_WK_COMP1GT      = RTC_COMP1GT_WAKEUP_EN_Msk,
+    RTC_WK_COMP2GT      = RTC_COMP2GT_WAKEUP_EN_Msk,
+    RTC_WK_COMP3GT      = RTC_COMP3GT_WAKEUP_EN_Msk,
+    RTC_WK_COMP0        = RTC_COMP0_WAKEUP_EN_Msk,
+    RTC_WK_COMP1        = RTC_COMP1_WAKEUP_EN_Msk,
+    RTC_WK_COMP2        = RTC_COMP2_WAKEUP_EN_Msk,
+    RTC_WK_COMP3        = RTC_COMP3_WAKEUP_EN_Msk,
+} E_RTC_WK;
+
+#define IS_RTC_WK(WK) (((WK) == RTC_WK_TICK) || \
+                       ((WK) == RTC_WK_OVF) || \
+                       ((WK) == RTC_WK_PRE_COMP) || \
+                       ((WK) == RTC_WK_PRE_COMP3) || \
+                       ((WK) == RTC_WK_COMP0GT) || \
+                       ((WK) == RTC_WK_COMP1GT) || \
+                       ((WK) == RTC_WK_COMP2GT) || \
+                       ((WK) == RTC_WK_COMP3GT) || \
+                       ((WK) == RTC_WK_COMP0) || \
+                       ((WK) == RTC_WK_COMP1) || \
+                       ((WK) == RTC_WK_COMP2) || \
+                       ((WK) == RTC_WK_COMP3))
+/** \} */
+
+/**
+ * \defgroup    RTC_Comp_Index RTC Comparator Index
+ * \{
+ * \ingroup     RTC_Exported_Constants
+ */
+typedef enum
+{
+    RTC_COMP0 = 0,
+    RTC_COMP1,
+    RTC_COMP2,
+    RTC_COMP3,
+} E_RTC_COMP_INDEX;
+
+#define IS_RTC_COMP(COMP) (((COMP) == RTC_COMP0) || \
+                           ((COMP) == RTC_COMP1) || \
+                           ((COMP) == RTC_COMP2) || \
+                           ((COMP) == RTC_COMP3))
+/** \} */
+
+/**
+ * \defgroup    RTC_CompGT_Index RTC ComparatorGT Index
+ * \{
+ * \ingroup     RTC_Exported_Constants
+ */
+typedef enum
+{
+    RTC_COMP0GT = 0,
+    RTC_COMP1GT,
+    RTC_COMP2GT,
+    RTC_COMP3GT,
+} E_RTC_COMPGT_INDEX;
+
+/** \} */
+
+/** End of RTC_Exported_Constants
+  * \}
+  */
+
+/*============================================================================*
+ *                         Functions
+ *============================================================================*/
+/**
+ * \defgroup    RTC_Exported_Functions RTC Exported Functions
+ * \{
+ * \ingroup     RTC
+ */
+
+/**
+ * \brief     Fast write RTC register, internal function.
+ * \param[in] regAddress: The register address.
+ * \param[in] data: Data to be written to the register.
+ * \return    None.
+ */
+void RTC_WriteReg(uint32_t regAddress, uint32_t data);
+
+/**
+ * \brief     Deinitialize the RTC peripheral registers to their default reset values (turn off clock).
+ * \return    None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_rtc_init(void)
+ * {
+ *     RTC_DeInit();
+ * }
+ * \endcode
+ */
+void RTC_DeInit(void);
+
+/**
+ * \brief     Set RTC prescaler value.
+ * \param[in] value: The prescaler value to be set. Should be no more than 12 bits!
+ * \return    None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * #define RTC_PRESCALER_VALUE     49
+ * #define RTC_COMP_INDEX          RTC_COMP3
+ * #define RTC_COMP_INDEX_INT      RTC_INT_COMP3
+ * #define RTC_COMP_VALUE          (1000)
+ *
+ * void driver_rtc_init(void)
+ * {
+ *     RTC_DeInit();
+ *
+ *     RTC_SetPrescaler(RTC_PRESCALER_VALUE);
+ *     RTC_SetCompValue(RTC_COMP_INDEX, RTC_COMP_VALUE);
+ *
+ *     RTC_MaskINTConfig(RTC_COMP_INDEX_INT, DISABLE);
+ *     RTC_INTConfig(RTC_COMP_INDEX_INT, ENABLE);
+ *
+ *     RTC_NvCmd(ENABLE);
+ *     RTC_Cmd(ENABLE);
+ * }
+ * \endcode
+ */
+void RTC_SetPrescaler(uint16_t value);
+
+/**
+ * \brief     Start or stop the RTC peripheral.
+ * \param[in] NewState: New state of the RTC peripheral.
+ *            This parameter can be one of the following values:
+ *            \arg ENABLE: Start RTC.
+ *            \arg DISABLE: Stop RTC.
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * #define RTC_PRESCALER_VALUE     49
+ * #define RTC_COMP_INDEX          RTC_COMP3
+ * #define RTC_COMP_INDEX_INT      RTC_INT_COMP3
+ * #define RTC_COMP_VALUE          (1000)
+ *
+ * void driver_rtc_init(void)
+ * {
+ *     RTC_DeInit();
+ *
+ *     RTC_SetPrescaler(RTC_PRESCALER_VALUE);
+ *     RTC_SetCompValue(RTC_COMP_INDEX, RTC_COMP_VALUE);
+ *
+ *     RTC_MaskINTConfig(RTC_COMP_INDEX_INT, DISABLE);
+ *     RTC_INTConfig(RTC_COMP_INDEX_INT, ENABLE);
+ *
+ *     RTC_NvCmd(ENABLE);
+ *     RTC_Cmd(ENABLE);
+ * }
+ * \endcode
+ */
+void RTC_Cmd(FunctionalState NewState);
+
+/**
+ * \brief     Enable or disable the specified RTC interrupt source.
+ * \param[in] RTC_INT: Specify the RTC interrupt source to be enabled or disabled.
+ *            This parameter can be any combination of the following values, refer to \ref RTC_Interrupt_Definition.
+ *            \arg RTC_INT_TICK: Tick interrupt source.
+ *            \arg RTC_INT_OVF: Counter overflow interrupt.
+ *            \arg RTC_INT_COMP0: Compare 0 interrupt source.
+ *            \arg RTC_INT_COMP1: Compare 1 interrupt source.
+ *            \arg RTC_INT_COMP2: Compare 2 interrupt source.
+ *            \arg RTC_INT_COMP3: Compare 3 interrupt source.
+ *            \arg RTC_INT_PRE_COMP: Prescale compare interrupt source.
+ *            \arg RTC_INT_PRE_COMP3: Prescale & compare 3 interrupt source.
+ * \param[in] NewState: New state of the specified RTC interrupt.
+ *            This parameter can be: ENABLE or DISABLE.
+ * \return    None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * #define RTC_PRESCALER_VALUE     49
+ * #define RTC_COMP_INDEX          RTC_COMP3
+ * #define RTC_COMP_INDEX_INT      RTC_INT_COMP3
+ * #define RTC_COMP_VALUE          (1000)
+ *
+ * void driver_rtc_init(void)
+ * {
+ *     RTC_DeInit();
+ *
+ *     RTC_SetPrescaler(RTC_PRESCALER_VALUE);
+ *     RTC_SetCompValue(RTC_COMP_INDEX, RTC_COMP_VALUE);
+ *
+ *     RTC_MaskINTConfig(RTC_COMP_INDEX_INT, DISABLE);
+ *     RTC_INTConfig(RTC_COMP_INDEX_INT, ENABLE);
+ *
+ *     RTC_NvCmd(ENABLE);
+ *     RTC_Cmd(ENABLE);
+ * }
+ * \endcode
+ */
+void RTC_INTConfig(E_RTC_INT RTC_INT, FunctionalState NewState);
+
+/**
+ * \brief  Enable or disable the specified RTC wakeup function.
+ * \param  RTC_WK: Specify the RTC wakeup function to be enabled or disabled.
+ *         This parameter can be any combination of the following values, refer to \ref RTC_Wakeup_Definition.
+ *         \arg RTC_WK_TICK: tick wakeup function
+ *         \arg RTC_WK_OVF: tick wakeup function
+ *         \arg RTC_WK_PRE_CMP: prescale compare wakeup function
+ *         \arg RTC_WK_PRE_CMP3: prescale & compare 3 wakeup function
+ *         \arg RTC_WK_COMP0GT: compare 0 gt wakeup function
+ *         \arg RTC_WK_COMP1GT: compare 1 gt wakeup function
+ *         \arg RTC_WK_COMP2GT: compare 2 gt wakeup function
+ *         \arg RTC_WK_COMP3GT: compare 3 gt wakeup function
+ *         \arg RTC_WK_CMP0: compare 0 wakeup function
+ *         \arg RTC_WK_CMP1: compare 1 wakeup function
+ *         \arg RTC_WK_CMP2: compare 2 wakeup function
+ *         \arg RTC_WK_CMP3: compare 3 wakeup function
+ * \param  NewState: new state of the specified RTC wakeup function.
+ *         This parameter can be: ENABLE or DISABLE.
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * #define RTC_PRESCALER_VALUE     49
+ * #define RTC_COMP_INDEX          RTC_COMP3
+ * #define RTC_COMP_INDEX_INT      RTC_INT_COMP3
+ * #define RTC_COMP_VALUE          (1000)
+ *
+ * void driver_rtc_init(void)
+ * {
+ *     RTC_DeInit();
+ *
+ *     RTC_SetPrescaler(RTC_PRESCALER_VALUE);
+ *     RTC_SetCompValue(RTC_COMP_INDEX, RTC_COMP_VALUE);
+ *
+ *     RTC_MaskINTConfig(RTC_COMP_INDEX_INT, DISABLE);
+ *     RTC_INTConfig(RTC_COMP_INDEX_INT, ENABLE);
+ *
+ *     RTC_NvCmd(ENABLE);
+ *     RTC_Cmd(ENABLE);
+ * }
+ * \endcode
+ */
+void RTC_WKConfig(E_RTC_WK RTC_WK, FunctionalState NewState);
+
+/**
+ * \brief     Enable RTC interrupt signal to CPU NVIC.
+ * \param[in] NewState: Enable or disable the RTC interrupt signal to MCU.
+ *            This parameter can be: ENABLE or DISABLE.
+ * \return    None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * #define RTC_PRESCALER_VALUE     49
+ * #define RTC_COMP_INDEX          RTC_COMP3
+ * #define RTC_COMP_INDEX_INT      RTC_INT_COMP3
+ * #define RTC_COMP_VALUE          (1000)
+ *
+ * void driver_rtc_init(void)
+ * {
+ *     RTC_DeInit();
+ *
+ *     RTC_SetPrescaler(RTC_PRESCALER_VALUE);
+ *     RTC_SetCompValue(RTC_COMP_INDEX, RTC_COMP_VALUE);
+ *
+ *     RTC_MaskINTConfig(RTC_COMP_INDEX_INT, DISABLE);
+ *     RTC_INTConfig(RTC_COMP_INDEX_INT, ENABLE);
+ *
+ *     RTC_NvCmd(ENABLE);
+ *     RTC_Cmd(ENABLE);
+ * }
+ * \endcode
+ */
+void RTC_NvCmd(FunctionalState NewState);
+
+/**
+ * \brief     Enable or disable the system wakeup function of RTC.
+ * \param[in] NewState: New state of the wakeup function.
+ *            This parameter can be: ENABLE or DISABLE.
+ * \return    None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void rtc_demo(void)
+ * {
+ *     RTC_SystemWakeupConfig(ENABLE);
+ * }
+ * \endcode
+ */
+void RTC_SystemWakeupConfig(FunctionalState NewState);
+
+/**
+ * \brief     Reset the counter value of RTC.
+ * \return    None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void rtc_demo(void)
+ * {
+ *     RTC_ResetCounter();
+ *     RTC_Cmd(ENABLE);
+ * }
+ * \endcode
+ */
+void RTC_ResetCounter(void);
+
+/**
+ * \brief     Reset prescaler counter value of RTC.
+ * \return    None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void rtc_demo(void)
+ * {
+ *     RTC_ResetPrescalerCounter();
+ *     RTC_Cmd(ENABLE);
+ * }
+ * \endcode
+ */
+void RTC_ResetPrescalerCounter(void);
+
+/**
+ * \brief  Check whether the specified RTC interrupt is set.
+  * \param[in]  RTC_INT: Specify the RTC interrupt source to be enabled or disabled.
+ *   This parameter can be any combination of the following values, refer to \ref RTC_Interrupt_Definition.
+ *            \arg RTC_INT_TICK: RTC tick interrupt source.
+ *            \arg RTC_INT_COMP0: Compare 0 interrupt source.
+ *            \arg RTC_INT_COMP1: Compare 1 interrupt source.
+ *            \arg RTC_INT_COMP2: Compare 2 interrupt source.
+ *            \arg RTC_INT_COMP3: Compare 3 interrupt source.
+ *            \arg RTC_INT_PRE_COMP: Prescale compare interrupt source.
+ *            \arg RTC_INT_PRE_COMP3: Prescale & compare 3 interrupt source.
+ * \return The new state of RTC_INT (SET or RESET).
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void rtc_demo(void)
+ * {
+ *     ITStatus int_status = RTC_GetINTStatus(RTC_INT_COMP0);
+ * }
+ * \endcode
+ */
+ITStatus RTC_GetINTStatus(E_RTC_INT RTC_INT);
+
+/**
+ * \brief     Clear the interrupt pending bits of RTC.
+ * \param[in] RTC_INT: Specify the RTC interrupt flag to clear.
+ *            This parameter can be any combination of the following values, refer to \ref RTC_Interrupt_Definition.
+ *            \arg RTC_INT_TICK: RTC tick interrupt source.
+ *            \arg RTC_INT_OVF: RTC counter overflow interrupt source.
+ *            \arg RTC_INT_COMP0: Compare 0 interrupt source.
+ *            \arg RTC_INT_COMP1: Compare 1 interrupt source.
+ *            \arg RTC_INT_COMP2: Compare 2 interrupt source.
+ *            \arg RTC_INT_COMP3: Compare 3 interrupt source.
+ *            \arg RTC_INT_PRE_COMP: Prescale compare interrupt source.
+ *            \arg RTC_INT_PRE_COMP3: Prescale & compare 3 interrupt source.
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void rtc_demo(void)
+ * {
+ *     RTC_ClearINTPendingBit(RTC_INT_COMP0);
+ * }
+ * \endcode
+ */
+void RTC_ClearINTPendingBit(E_RTC_INT RTC_INT);
+
+/**
+  * \brief  Check whether the specified RTC wakeup state is set or not.
+  * \param  RTC_WK: Specify the RTC interrupt source to be enabled or disabled.
+  *         This parameter can be any combination of the following values, refer to \ref RTC_Wakeup_Definition.
+  *         \arg RTC_WK_TICK: Tick wakeup function.
+  *         \arg RTC_WK_OVF: Tick wakeup function.
+  *         \arg RTC_WK_PRE_CMP: Prescale compare wakeup function.
+  *         \arg RTC_WK_PRE_CMP3: Prescale & compare 3 wakeup function.
+  *         \arg RTC_WK_COMP0GT: Compare 0 gt wakeup function.
+  *         \arg RTC_WK_COMP1GT: Compare 1 gt wakeup function.
+  *         \arg RTC_WK_COMP2GT: Compare 2 gt wakeup function.
+  *         \arg RTC_WK_COMP3GT: Compare 3 gt wakeup function.
+  *         \arg RTC_WK_CMP0: Compare 0 wakeup function.
+  *         \arg RTC_WK_CMP1: Compare 1 wakeup function.
+  *         \arg RTC_WK_CMP2: Compare 2 wakeup function.
+  *         \arg RTC_WK_CMP3: Compare 3 wakeup function.
+  * \return The new state of RTC_INT (SET or RESET).
+  */
+ITStatus RTC_GetWakeupStatus(E_RTC_WK RTC_WK);
+
+/**
+  * \brief  Clear the wakeup status bits of RTC.
+  * \param  RTC_WK: Specify the RTC wakeup flag to clear.
+  *         This parameter can be any combination of the following values, refer to \ref RTC_Wakeup_Definition.
+  *         \arg RTC_WK_TICK: Tick wakeup function.
+  *         \arg RTC_WK_OVF: Tick wakeup function.
+  *         \arg RTC_WK_PRE_CMP: Prescale compare wakeup function.
+  *         \arg RTC_WK_PRE_CMP3: Prescale & compare 3 wakeup function.
+  *         \arg RTC_WK_COMP0GT: Compare 0 gt wakeup function.
+  *         \arg RTC_WK_COMP1GT: Compare 1 gt wakeup function.
+  *         \arg RTC_WK_COMP2GT: Compare 2 gt wakeup function.
+  *         \arg RTC_WK_COMP3GT: Compare 3 gt wakeup function.
+  *         \arg RTC_WK_CMP0: Compare 0 wakeup function.
+  *         \arg RTC_WK_CMP1: Compare 1 wakeup function.
+  *         \arg RTC_WK_CMP2: Compare 2 wakeup function.
+  *         \arg RTC_WK_CMP3: Compare 3 wakeup function.
+  * \return None.
+  */
+void RTC_ClearWakeupStatusBit(E_RTC_WK RTC_WK);
+
+/**
+ * \brief     Clear the interrupt pending bit of the select comparator of RTC.
+ * \param[in] index: the comparator number, refer to \ref RTC_Comp_Index.
+ * \return    None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void rtc_demo(void)
+ * {
+ *     RTC_ClearCompINT(0);
+ * }
+ * \endcode
+ */
+void RTC_ClearCompINT(E_RTC_COMP_INDEX index);
+
+/**
+ * \brief     Clear the overflow interrupt pending bit of RTC.
+ * \return    None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void rtc_demo(void)
+ * {
+ *     RTC_ClearOverFlowINT();
+ * }
+ * \endcode
+ */
+void RTC_ClearOverFlowINT(void);
+
+/**
+ * \brief     Clear the tick interrupt pending bit of RTC.
+ * \return    None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void rtc_demo(void)
+ * {
+ *     RTC_ClearTickINT();
+ * }
+ * \endcode
+ */
+void RTC_ClearTickINT(void);
+
+/**
+ * \brief     Set RTC comparator value.
+ * \param[in] index: The comparator number can be 0 ~ 3.
+ * \param[in] value: The comparator value to be set. Should be no more than 24 bits!
+ * \return    None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * #define RTC_PRESCALER_VALUE     49
+ * #define RTC_COMP_INDEX          RTC_COMP3
+ * #define RTC_COMP_INDEX_INT      RTC_INT_COMP3
+ * #define RTC_COMP_VALUE          (1000)
+ *
+ * void driver_rtc_init(void)
+ * {
+ *     RTC_DeInit();
+ *
+ *     RTC_SetPrescaler(RTC_PRESCALER_VALUE);
+ *     RTC_SetCompValue(RTC_COMP_INDEX, RTC_COMP_VALUE);
+ *
+ *     RTC_MaskINTConfig(RTC_COMP_INDEX_INT, DISABLE);
+ *     RTC_INTConfig(RTC_COMP_INDEX_INT, ENABLE);
+ *
+ *     RTC_NvCmd(ENABLE);
+ *     RTC_Cmd(ENABLE);
+ * }
+ * \endcode
+ */
+__STATIC_INLINE void RTC_SetCompValue(E_RTC_COMP_INDEX index, uint32_t value)
+{
+    /* Check the parameters */
+    assert_param(IS_RTC_COMP(index));
+
+    RTC_WriteReg((uint32_t)(&(RTC->COMP0) + index), (value & 0xFFFFFFFF));
+}
+
+/**
+ * \brief     Set RTC comparator GT value.
+ * \param[in] index: The comparator GT number, can be 0 ~ 3.
+ * \param[in] value: The comparator value to be set.
+ * \return    None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * #define RTC_PRESCALER_VALUE     49
+ * #define RTC_COMP_INDEX          RTC_COMP3
+ * #define RTC_COMP_INDEX_INT      RTC_INT_COMP3
+ * #define RTC_COMP_VALUE          (1000)
+ *
+ * void driver_rtc_init(void)
+ * {
+ *     RTC_DeInit();
+ *
+ *     RTC_SetPrescaler(RTC_PRESCALER_VALUE);
+ *     RTC_SetCompValue(RTC_COMP_INDEX, RTC_COMP_VALUE);
+ *
+ *     RTC_MaskINTConfig(RTC_COMP_INDEX_INT, DISABLE);
+ *     RTC_INTConfig(RTC_COMP_INDEX_INT, ENABLE);
+ *
+ *     RTC_NvCmd(ENABLE);
+ *     RTC_Cmd(ENABLE);
+ * }
+ * \endcode
+ */
+__STATIC_INLINE void RTC_SetCompGTValue(E_RTC_COMPGT_INDEX index, uint32_t value)
+{
+    /* Check the parameters */
+    assert_param(IS_RTC_COMPGT(index));
+
+    RTC_WriteReg((uint32_t)(&(RTC->COMP0GT) + index), (value & 0xFFFFFFFF));
+}
+
+/**
+ * \brief     Set RTC prescaler comparator value.
+ * \param[in] value: The comparator value to be set. Should be no more than 12 bits!
+ * \return    None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * #define RTC_PRESCALER_VALUE     (3200 - 1)//max 4095
+ * #define RTC_PRECOMP_VALUE       (320)//max 4095
+ * #define RTC_COMP3_VALUE         (10)
+ *
+ * void driver_rtc_init(void)
+ * {
+ *     RTC_DeInit();
+ *
+ *     RTC_SetPrescaler(RTC_PRESCALER_VALUE);
+ *     RTC_SetPreCompValue(RTC_PRECOMP_VALUE);
+ *     RTC_SetCompValue(RTC_COMP3, RTC_COMP3_VALUE);
+ *
+ *     RTC_MaskINTConfig(RTC_INT_PRE_COMP3, DISABLE);
+ *     RTC_INTConfig(RTC_INT_PRE_COMP3, ENABLE);
+ *
+ *     RTC_NvCmd(ENABLE);
+ *     RTC_Cmd(ENABLE);
+ * }
+ * \endcode
+ */
+__STATIC_INLINE void RTC_SetPreCompValue(uint32_t value)
+{
+    RTC_WriteReg((uint32_t)(&(RTC->PRE_COMP)), (value & 0xFFF));
+}
+
+/**
+ * \brief     Get counter value of RTC.
+ * \return    The counter value.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void rtc_demo(void)
+ * {
+ *     uint32_t counter = RTC_GetCounter();
+ * }
+ * \endcode
+ */
+__STATIC_INLINE uint32_t RTC_GetCounter(void)
+{
+    return RTC->CNT;
+}
+
+/**
+ * \brief     Get prescaler counter value of RTC.
+ * \return    The prescaler counter value.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void rtc_demo(void)
+ * {
+ *     uint32_t pre_counter = RTC_GetPreCounter();
+ * }
+ * \endcode
+ */
+__STATIC_INLINE uint32_t RTC_GetPreCounter(void)
+{
+    return RTC->PRE_CNT;
+}
+
+/**
+ * \brief     Get RTC comparator value.
+ * \param[in] index: The comparator number.
+ * \return    The comparator value.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void rtc_demo(void)
+ * {
+ *     uint32_t data = RTC_GetCompValue(0);
+ * }
+ * \endcode
+ */
+__STATIC_INLINE uint32_t RTC_GetCompValue(E_RTC_COMP_INDEX index)
+{
+    return *((volatile uint32_t *)(&(RTC->COMP0) + index));
+}
+
+/**
+ * \brief     Get RTC comparator GT value.
+ * \param[in] index: The comparator number 0~3.
+ * \return    The comparator value.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void rtc_demo(void)
+ * {
+ *     uint32_t data = RTC_GetCompGTValue(0);
+ * }
+ * \endcode
+ */
+__STATIC_INLINE uint32_t RTC_GetCompGTValue(E_RTC_COMPGT_INDEX index)
+{
+    return *((volatile uint32_t *)(&(RTC->COMP0GT) + index));
+}
+
+/**
+ * \brief     Get RTC prescaler comparator value.
+ * \return    The prescaler comparator value.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void rtc_demo(void)
+ * {
+ *     uint32_t data = RTC_GetPreCompValue();
+ * }
+ * \endcode
+ */
+__STATIC_INLINE uint32_t RTC_GetPreCompValue(void)
+{
+    return RTC->PRE_COMP;
+}
+
+/**
+ * \brief     Write backup register for store time information.
+ * \param[in] value: value write to backup register.
+ * \return    None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void rtc_demo(void)
+ * {
+ *     RTC_WriteBackupReg(0x01020304);
+ * }
+ * \endcode
+ */
+//void RTC_WriteBackupReg(uint32_t value);
+__STATIC_INLINE void RTC_WriteBackupReg(uint32_t value)
+{
+    RTC_WriteReg((uint32_t)(&(RTC->BACKUP)), value);
+}
+
+/**
+ * \brief     Read backup register.
+ * \return    Register value.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void rtc_demo(void)
+ * {
+ *     uint32_t reg_data = RTC_ReadBackupReg();
+ * }
+ * \endcode
+ */
+//uint32_t RTC_ReadBackupReg(void);
+__STATIC_INLINE uint32_t RTC_ReadBackupReg(void)
+{
+    return (RTC->BACKUP);
+}
+
+/** End of RTC_Exported_Functions
+  * \}
+  */
+
+/** End of RTC
+  * \}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTL876X_RTC_H_ */
diff --git a/bee/drivers/rtc/src/device/rtl87x2g/rtl87x2g_rtc.c b/bee/drivers/rtc/src/device/rtl87x2g/rtl87x2g_rtc.c
new file mode 100644
index 00000000..7b2b9ea8
--- /dev/null
+++ b/bee/drivers/rtc/src/device/rtl87x2g/rtl87x2g_rtc.c
@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *                        Header Files
+ *============================================================================*/
+#include "rtl_rtc.h"
+
+/*============================================================================*
+ *                        Private Defines
+ *============================================================================*/
+#define RTC_IN_SEL             *((volatile uint32_t *)0x4000080C)
+#define RTC_IN_32K             *((volatile uint32_t *)0x40000814)
+#define RTC_GPIO_32K           *((volatile uint32_t *)0x40000C84)
+/*============================================================================*
+ *                           Public Functions
+ *============================================================================*/
+/**
+  * \brief  Select source clock to gpio input of RTC.
+  * \param  gpio: the selected gpio.
+  * \return None
+  */
+void RTC_SelectSrcToGpioInput(RTCInSel_TypeDef rtc_in)
+{
+    /* Set en_gpio_32k if any muxes need USE_32K_GPIO_IN */
+    RTC_IN_SEL |= BIT10;
+
+    /* Set XTAL32K_GPIO_SEL if rtc_in choose PAD_32KXI_RTC_IN */
+    if (rtc_in == PAD_32KXI_RTC_IN)
+    {
+        RTC_GPIO_32K |= BIT6;
+    }
+    else
+    {
+        RTC_GPIO_32K &= ~BIT6;
+    }
+    /* Choose rtc_in PAD */
+    RTC_IN_SEL &= ~((rtc_in & 0x3) << 8);
+    RTC_IN_SEL |= (rtc_in & 0x3) << 8;
+
+    /* Open SEL_32K_GPIO_rtc */
+    RTC_IN_32K |= BIT10;
+}
+
+
diff --git a/bee/drivers/rtc/src/device/rtl87x2g/rtl_rtc.c b/bee/drivers/rtc/src/device/rtl87x2g/rtl_rtc.c
new file mode 100644
index 00000000..12c81f86
--- /dev/null
+++ b/bee/drivers/rtc/src/device/rtl87x2g/rtl_rtc.c
@@ -0,0 +1,554 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *                        Header Files
+ *============================================================================*/
+#include "rtl_rtc.h"
+
+/*============================================================================*
+ *                           Public Functions
+ *============================================================================*/
+/**
+  * \brief  Reset RTC.
+  * \param  None
+  * \return None
+  */
+void RTC_DeInit(void)
+{
+    /* Stop RTC counter */
+    RTC_CR0_TypeDef rtc_0x00 = {.d32 = RTC->RTC_CR0};
+    rtc_0x00.b.rtc_cnt_start = 0;
+    RTC->RTC_CR0 = rtc_0x00.d32;
+
+    /* Disable wakeup signal */
+    rtc_0x00.b.rtc_nv_ie = 0;
+    rtc_0x00.b.rtc_wk_ie = 0;
+    RTC->RTC_CR0 = rtc_0x00.d32;
+
+    /* Clear all RTC interrupt & wakeup */
+    RTC->RTC_INT_CLEAR = RTC_ALL_INT_CLR | RTC_ALL_WAKEUP_CLR;
+
+    /* Clear prescale register */
+    RTC->RTC_PRESCALER0 = 0;
+    /* Clear all comparator register */
+    RTC->RTC_COMP_0 = 0;
+    RTC->RTC_COMP_1 = 0;
+    RTC->RTC_COMP_2 = 0;
+    RTC->RTC_COMP_3 = 0;
+
+#if (RTC_SUPPORT_COMPARE_GUARDTIME == 1)
+    RTC->RTC_COMP0_GT = 0;
+    RTC->RTC_COMP1_GT = 0;
+    RTC->RTC_COMP2_GT = 0;
+    RTC->RTC_COMP3_GT = 0;
+#endif
+
+    RTC->RTC_PRESCALE_CMP0 = 0;
+
+    /* Reset prescale counter and counter */
+    rtc_0x00.d32 = 0;
+    rtc_0x00.b.rtc_cnt_rst = 1;
+    rtc_0x00.b.rtc_pre_cnt_rst = 1;
+    RTC->RTC_CR0 = rtc_0x00.d32;
+    __NOP();
+    __NOP();
+    RTC->RTC_CR0 = 0;
+}
+
+/**
+  * \brief  Set RTC prescaler value.
+  * \param  value: the prescaler value to be set.Should be no more than 12 bits!
+  * \return None
+  */
+void RTC_SetPrescaler(uint16_t value)
+{
+    RTC->RTC_PRESCALER0 = value & 0xFFF;
+}
+
+/**
+  * \brief  Start or stop RTC peripheral.
+  * \param  NewState: new state of RTC peripheral.
+  *         This parameter can be the following values:
+  *         \arg ENABLE: start RTC.
+  *         \arg DISABLE: stop RTC.
+  * \return None
+  */
+void RTC_Cmd(FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    /* Start or stop RTC */
+    RTC_CR0_TypeDef rtc_0x00 = {.d32 = RTC->RTC_CR0};
+    rtc_0x00.b.rtc_cnt_start = NewState;
+    RTC->RTC_CR0 = rtc_0x00.d32;
+}
+
+/**
+  * \brief  Enable or disable the specified RTC interrupts.
+  * \param  RTC_INT: specifies the RTC interrupt source to be enabled or disabled.
+  *         This parameter can be any combination of the following values:
+  *         \arg RTC_INT_TICK: tick interrupt
+  *         \arg RTC_INT_OVF: counter overflow interrupt
+  *         \arg RTC_INT_PRE_CMP: prescale compare interrupt
+  *         \arg RTC_INT_PRE_CMP3: prescale & compare 3 interrupt
+  *         \arg RTC_INT_CMP0: compare 0 interrupt
+  *         \arg RTC_INT_CMP1: compare 1 interrupt
+  *         \arg RTC_INT_CMP2: compare 2 interrupt
+  *         \arg RTC_INT_CMP3: compare 3 interrupt
+  * \param  NewState: new state of the specified RTC interrupt.
+  *         This parameter can be: ENABLE or DISABLE.
+  * \return None.
+  */
+void RTC_INTConfig(uint32_t RTC_INT, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_RTC_INT(RTC_INT));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (NewState == ENABLE)
+    {
+        /* Enable the selected RTC comparator interrupt */
+        RTC->RTC_CR0 |= RTC_INT;
+    }
+    else
+    {
+        /* Disable the selected RTC comparator interrupt */
+        RTC->RTC_CR0 &= (~RTC_INT);
+    }
+}
+
+/**
+  * \brief  Enable or disable the specified RTC wakeup function.
+  * \param  RTC_WK: specifies the RTC wakeup function to be enabled or disabled.
+  *         This parameter can be any combination of the following values:
+  *         \arg RTC_WK_TICK: tick wakeup function
+  *         \arg RTC_WK_OVF: tick wakeup function
+  *         \arg RTC_WK_PRE_CMP: prescale compare wakeup function
+  *         \arg RTC_WK_PRE_CMP3: prescale & compare 3 wakeup function
+  *         \arg RTC_WK_COMP0GT: compare 0 gt wakeup function
+  *         \arg RTC_WK_COMP1GT: compare 1 gt wakeup function
+  *         \arg RTC_WK_COMP2GT: compare 2 gt wakeup function
+  *         \arg RTC_WK_COMP3GT: compare 3 gt wakeup function
+  *         \arg RTC_WK_CMP0: compare 0 wakeup function
+  *         \arg RTC_WK_CMP1: compare 1 wakeup function
+  *         \arg RTC_WK_CMP2: compare 2 wakeup function
+  *         \arg RTC_WK_CMP3: compare 3 wakeup function
+  * \param  NewState: new state of the specified RTC wakeup function.
+  *         This parameter can be: ENABLE or DISABLE.
+  * \return None.
+  */
+void RTC_WKConfig(uint32_t RTC_WK, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_RTC_WK(RTC_WK));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (NewState == ENABLE)
+    {
+        /* Enable the selected RTC comparator interrupt */
+        RTC->RTC_CR0 |= RTC_WK;
+    }
+    else
+    {
+        /* Disable the selected RTC comparator interrupt */
+        RTC->RTC_CR0 &= (~RTC_WK);
+    }
+}
+
+/**
+  * \brief  Enable interrupt signal to CPU NVIC.
+  * \param  This parameter can be: ENABLE or DISABLE.
+  * \return None.
+  */
+void RTC_NvCmd(FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    RTC_CR0_TypeDef rtc_0x00 = {.d32 = RTC->RTC_CR0};
+    rtc_0x00.b.rtc_nv_ie = NewState;
+    RTC->RTC_CR0 = rtc_0x00.d32;
+}
+
+/**
+ * \brief  Enable or disable system wake up of RTC.
+ * \param  NewState: new state of the wake up function.
+ *         This parameter can be: ENABLE or DISABLE.
+ * \return None
+ */
+void RTC_SystemWakeupConfig(FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    /* Enable or disable system wake up */
+    RTC_CR0_TypeDef rtc_0x00 = {.d32 = RTC->RTC_CR0};
+    rtc_0x00.b.rtc_wk_ie = NewState;
+    RTC->RTC_CR0 = rtc_0x00.d32;
+}
+
+/**
+  * \brief  Reset counter value of RTC.
+  * \param  None
+  * \return None
+  */
+void RTC_ResetCounter(void)
+{
+    RTC_CR0_TypeDef rtl_0x00 = {.d32 = RTC->RTC_CR0};
+    rtl_0x00.b.rtc_cnt_rst = 1;
+    RTC->RTC_CR0 = rtl_0x00.d32;
+    __NOP();
+    __NOP();
+    rtl_0x00.b.rtc_cnt_rst = 0;
+    RTC->RTC_CR0 = rtl_0x00.d32;
+}
+
+/**
+  * \brief  Reset prescaler counter value of RTC.
+  * \param  None
+  * \return None
+  */
+void RTC_ResetPrescalerCounter(void)
+{
+    RTC_CR0_TypeDef rtl_0x00 = {.d32 = RTC->RTC_CR0};
+    rtl_0x00.b.rtc_pre_cnt_rst = 1;
+    RTC->RTC_CR0 = rtl_0x00.d32;
+    __NOP();
+    __NOP();
+    rtl_0x00.b.rtc_pre_cnt_rst = 0;
+    RTC->RTC_CR0 = rtl_0x00.d32;
+}
+
+/**
+  * \brief  Checks whether the specified RTC interrupt is set or not.
+  * \param  RTC_INT: specifies the RTC interrupt source to be enabled or disabled.
+  *         This parameter can be any combination of the following values:
+  *         \arg RTC_INT_TICK: RTC tick interrupt source
+  *         \arg RTC_INT_PRE_COMP: prescale compare interrupt source
+  *         \arg RTC_INT_PRE_COMP3: prescale & compare 3 interrupt source
+  *         \arg RTC_INT_COMP0: compare 0 interrupt source
+  *         \arg RTC_INT_COMP1: compare 1 interrupt source
+  *         \arg RTC_INT_COMP2: compare 2 interrupt source
+  *         \arg RTC_INT_COMP3: compare 3 interrupt source
+  * \return The new state of RTC_INT (SET or RESET).
+  */
+ITStatus RTC_GetINTStatus(uint32_t RTC_INT)
+{
+    /* Check the parameters */
+    assert_param(IS_RTC_CONFIG_INT(RTC_INT));
+
+    ITStatus int_status = RESET;
+
+    if ((RTC->RTC_INT_SR & (RTC_INT >> 8)) != (uint32_t)RESET)
+    {
+        int_status = SET;
+    }
+
+    /* Return the RTC_INT status */
+    return  int_status;
+}
+
+/**
+  * \brief  Clear the interrupt pending bits of RTC.
+  * \param  RTC_INT: specifies the RTC interrupt flag to clear.
+  *         This parameter can be any combination of the following values:
+  *         \arg RTC_INT_TICK: RTC tick interrupt source
+  *         \arg RTC_INT_OVF: RTC counter overflow interrupt source
+  *         \arg RTC_INT_PRE_COMP: prescale compare interrupt source
+  *         \arg RTC_INT_PRE_COMP3: prescale & compare 3 interrupt source
+  *         \arg RTC_INT_COMP0: compare 0 interrupt source
+  *         \arg RTC_INT_COMP1: compare 1 interrupt source
+  *         \arg RTC_INT_COMP2: compare 2 interrupt source
+  *         \arg RTC_INT_COMP3: compare 3 interrupt source
+  * \return None
+  */
+void RTC_ClearINTPendingBit(uint32_t RTC_INT)
+{
+    /* Check the parameters */
+    assert_param(IS_RTC_INT(RTC_INT));
+
+    RTC->RTC_INT_CLEAR |= RTC_INT >> 8;
+}
+
+/**
+  * \brief  Checks whether the specified RTC wakeup state is set or not.
+  * \param  RTC_WK: specifies the RTC interrupt source to be enabled or disabled.
+  *         This parameter can be any combination of the following values:
+  *         \arg RTC_WK_TICK: tick wakeup function
+  *         \arg RTC_WK_OVF: tick wakeup function
+  *         \arg RTC_WK_PRE_CMP: prescale compare wakeup function
+  *         \arg RTC_WK_PRE_CMP3: prescale & compare 3 wakeup function
+  *         \arg RTC_WK_COMP0GT: compare 0 gt wakeup function
+  *         \arg RTC_WK_COMP1GT: compare 1 gt wakeup function
+  *         \arg RTC_WK_COMP2GT: compare 2 gt wakeup function
+  *         \arg RTC_WK_COMP3GT: compare 3 gt wakeup function
+  *         \arg RTC_WK_CMP0: compare 0 wakeup function
+  *         \arg RTC_WK_CMP1: compare 1 wakeup function
+  *         \arg RTC_WK_CMP2: compare 2 wakeup function
+  *         \arg RTC_WK_CMP3: compare 3 wakeup function
+  * \return The new state of RTC_INT (SET or RESET).
+  */
+ITStatus RTC_GetWakeupStatus(uint32_t RTC_WK)
+{
+    /* Check the parameters */
+    assert_param(IS_RTC_CONFIG_INT(RTC_WK));
+
+    ITStatus wakeup_status = RESET;
+
+    if ((RTC->RTC_INT_SR & (RTC_WK >> 8)) != (uint32_t)RESET)
+    {
+        wakeup_status = SET;
+    }
+
+    /* Return the RTC_INT status */
+    return  wakeup_status;
+}
+
+/**
+  * \brief  Clear the wakeup status bits of RTC.
+  * \param  RTC_WK: specifies the RTC wakeup flag to clear.
+  *         This parameter can be any combination of the following values:
+  *         \arg RTC_WK_TICK: tick wakeup function
+  *         \arg RTC_WK_OVF: tick wakeup function
+  *         \arg RTC_WK_PRE_CMP: prescale compare wakeup function
+  *         \arg RTC_WK_PRE_CMP3: prescale & compare 3 wakeup function
+  *         \arg RTC_WK_COMP0GT: compare 0 gt wakeup function
+  *         \arg RTC_WK_COMP1GT: compare 1 gt wakeup function
+  *         \arg RTC_WK_COMP2GT: compare 2 gt wakeup function
+  *         \arg RTC_WK_COMP3GT: compare 3 gt wakeup function
+  *         \arg RTC_WK_CMP0: compare 0 wakeup function
+  *         \arg RTC_WK_CMP1: compare 1 wakeup function
+  *         \arg RTC_WK_CMP2: compare 2 wakeup function
+  *         \arg RTC_WK_CMP3: compare 3 wakeup function
+  * \return None
+  */
+void RTC_ClearWakeupStatusBit(uint32_t RTC_WK)
+{
+    /* Check the parameters */
+    assert_param(IS_RTC_WK(RTC_WK));
+
+    RTC->RTC_INT_CLEAR |= RTC_WK >> 8;
+}
+
+/**
+  * \brief  Clear the interrupt pending bit of the select comparator of RTC.
+  * \param  index: the comparator number 0~3.
+  * \return None
+  */
+void RTC_ClearCompINT(RTCComIndex_TypeDef index)
+{
+    RTC->RTC_INT_CLEAR |= RTC_COMP0_CLR << (uint32_t)index;
+}
+
+/**
+  * \brief  Clear the overflow interrupt pending bit of RTC.
+  * \param  None
+  * \return None
+  */
+void RTC_ClearOverFlowINT(void)
+{
+    RTC_INT_CLEAR_TypeDef rtc_0x04 = {.d32 = RTC->RTC_INT_CLEAR};
+    rtc_0x04.b.rtc_cnt_ov_clr = 0x1;
+    RTC->RTC_INT_CLEAR = rtc_0x04.d32;
+}
+
+/**
+  * \brief  Clear the tick interrupt pending bit of RTC.
+  * \param  None
+  * \return None
+  */
+void RTC_ClearTickINT(void)
+{
+    RTC_INT_CLEAR_TypeDef rtc_0x04 = {.d32 = RTC->RTC_INT_CLEAR};
+    rtc_0x04.b.rtc_tick_clr = 0x1;
+    RTC->RTC_INT_CLEAR = rtc_0x04.d32;
+}
+
+/**
+  * \brief  Set RTC comparator value.
+  * \param  index: The comparator number,can be 0 ~ 3.
+  * \param  value: The comparator value to be set.Should be no more than 24 bits!
+  * \return None
+  */
+void RTC_SetCompValue(RTCComIndex_TypeDef index, uint32_t value)
+{
+    /* Check the parameters */
+    assert_param(IS_RTC_COMP(index));
+
+    *(&(RTC->RTC_COMP_0) + index) = value;
+}
+
+#if (RTC_SUPPORT_COMPARE_GUARDTIME == 1)
+/**
+  * \brief  Set RTC comparator GT value.
+  * \param  index: The comparator gt number, can be 0 ~ 3.
+  * \param  value: The comparator value to be set.
+  * \return None
+  */
+void RTC_SetCompGTValue(RTCCmopGTIndex_TypeDef index, uint32_t value)
+{
+    /* Check the parameters */
+    assert_param(IS_RTC_COMPGT(index));
+
+    *(&(RTC->RTC_COMP0_GT) + index) = value;
+}
+#endif
+
+/**
+  * \brief  Set RTC prescaler comparator value.
+  * \param  value: The comparator value to be set.Should be no more than 12 bits!
+  * \return None
+  */
+void RTC_SetPreCompValue(uint32_t value)
+{
+    RTC->RTC_PRESCALE_CMP0 = (value & 0xFFF);
+}
+
+/**
+  * \brief  Get counter value of RTC.
+  * \param  None.
+  * \return The counter value.
+  */
+uint32_t RTC_GetCounter(void)
+{
+    return RTC->RTC_CNT0;
+}
+
+/**
+  * \brief  Get prescaler counter value of RTC.
+  * \param  None.
+  * \return The prescaler counter value.
+  */
+uint32_t RTC_GetPreCounter(void)
+{
+    return RTC->RTC_PRESCALE_CNT0;
+}
+
+/**
+  * \brief  Get RTC comparator value.
+  * \param  index: The comparator number.
+  * \return The comparator value.
+  */
+uint32_t RTC_GetCompValue(RTCComIndex_TypeDef index)
+{
+    return *(&(RTC->RTC_COMP_0) + index);
+}
+
+#if (RTC_SUPPORT_COMPARE_GUARDTIME == 1)
+/**
+  * \brief  Get RTC comparator gt value.
+  * \param  index: The comparator number 0~3.
+  * \return The comparator value.
+  */
+uint32_t RTC_GetCompGTValue(RTCCmopGTIndex_TypeDef index)
+{
+    return *(&(RTC->RTC_COMP0_GT) + index);
+}
+#endif
+
+/**
+  * \brief  Get RTC prescaler comparator value.
+  * \param  None.
+  * \return The prescaler comparator value.
+  */
+uint32_t RTC_GetPreCompValue(void)
+{
+    return RTC->RTC_PRESCALE_CMP0;
+}
+
+/**
+  * \brief  Write backup register for store time information.
+  * \param  value: valuer=write to back up register
+  * \return None.
+  */
+void RTC_WriteBackupReg(uint32_t value)
+{
+    (RTC->RTC_BACKUP) = value;
+}
+
+/**
+  * \brief  Read backup register.
+  * \param  None.
+  * \return Register value.
+  */
+uint32_t RTC_ReadBackupReg(void)
+{
+    return (RTC->RTC_BACKUP);
+}
+
+/*============================================================================*
+ *                        RAP Functions
+ *============================================================================*/
+#if (RTC_SUPPORT_RAP_FUNCTION == 1)
+void RTC_RAPQactiveCtrl(uint32_t Qactive, FunctionalState NewState)
+{
+    return;
+}
+
+void RTC_RAPModeCmd(FunctionalState NewState)
+{
+    RTC_TASK_CTRL_TypeDef rtc_ctrl = {.d32 = RTC->RTC_TASK_CTRL};
+    rtc_ctrl.b.rtc_rap_mode = NewState;
+    RTC->RTC_TASK_CTRL = rtc_ctrl.d32;
+
+    return;
+}
+
+void RTC_TaskTrigger(uint32_t Task)
+{
+    RTC_TASK_CTRL_TypeDef rtc_ctrl = {.d32 = RTC->RTC_TASK_CTRL};
+    if (Task == RTC_TASK_START)
+    {
+        rtc_ctrl.b.rtc_fw_task_start = 1;
+    }
+    else if (Task == RTC_TASK_STOP)
+    {
+        rtc_ctrl.b.rtc_fw_task_stop = 1;
+    }
+    else if (Task == RTC_TASK_CLR)
+    {
+        rtc_ctrl.b.rtc_fw_task_clear = 1;
+    }
+    RTC->RTC_TASK_CTRL = rtc_ctrl.d32;
+
+    return;
+}
+
+void RTC_ShortcutCmd(uint32_t Task, uint32_t Event, FunctionalState NewState)
+{
+    RTC_SHOT_CTRL_TypeDef rtc_short = {.d32 = RTC->RTC_SHOT_CTRL};
+    if (Task == RTC_SHORTCUT_TASK_STOP)
+    {
+        rtc_short.b.rtc_task_stop_sub_en = NewState;
+    }
+    else if (Task == RTC_SHORTCUT_TASK_CLEAR)
+    {
+        rtc_short.b.rtc_task_clear_sub_en = NewState;
+    }
+    if (Event == RTC_SHORTCUT_EVENT_COM0)
+    {
+        rtc_short.b.rtc_event_cmp0_pub_en = NewState;
+    }
+    else if (Event == RTC_SHORTCUT_EVENT_COM1)
+    {
+        rtc_short.b.rtc_event_cmp1_pub_en = NewState;
+    }
+    else if (Event == RTC_SHORTCUT_EVENT_COM2)
+    {
+        rtc_short.b.rtc_event_cmp2_pub_en = NewState;
+    }
+    else if (Event == RTC_SHORTCUT_EVENT_COM3)
+    {
+        rtc_short.b.rtc_event_cmp3_pub_en = NewState;
+    }
+    RTC->RTC_SHOT_CTRL = rtc_short.d32;
+    return;
+}
+
+#endif
+
diff --git a/bee/drivers/rtc/src/device/rtl87x2g/rtl_rtc.h b/bee/drivers/rtc/src/device/rtl87x2g/rtl_rtc.h
new file mode 100644
index 00000000..ba555484
--- /dev/null
+++ b/bee/drivers/rtc/src/device/rtl87x2g/rtl_rtc.h
@@ -0,0 +1,935 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *               Define to prevent recursive inclusion
+ *============================================================================*/
+#ifndef RTL_RTC_H
+#define RTL_RTC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*============================================================================*
+ *                        Header Files
+ *============================================================================*/
+#include "utils/rtl_utils.h"
+#include "rtl_rtc_def.h"
+
+/** \defgroup RTC         RTC
+  * \brief
+  * \{
+  */
+
+/*============================================================================*
+ *                         Constants
+ *============================================================================*/
+/** \defgroup RTC_Exported_Constants RTC Exported Constants
+  * \brief
+  * \{
+  */
+
+/**
+ * \defgroup    RTC_Comparator_Index RTC Comparator Index
+ * \{
+ * \ingroup     RTC_Exported_Constants
+ */
+
+typedef enum
+{
+    RTC_COMP0 = 0x00,     //!< RTC comparator index0.
+    RTC_COMP1 = 0x01,     //!< RTC comparator index1.
+    RTC_COMP2 = 0x02,     //!< RTC comparator index2.
+    RTC_COMP3 = 0x03,     //!< RTC comparator index3.
+} RTCComIndex_TypeDef;
+
+#define IS_RTC_COMP(COMP) (((COMP) == RTC_COMP0) || \
+                           ((COMP) == RTC_COMP1) || \
+                           ((COMP) == RTC_COMP2) || \
+                           ((COMP) == RTC_COMP3)) //!< Check if the input parameter is valid.
+
+/** End of RTC_Comparator_Index
+  * \}
+  */
+
+#if (RTC_SUPPORT_COMPARE_GUARDTIME == 1)
+/**
+ * \defgroup    RTC_ComparatorGT_Index RTC ComparatorGT Index
+ * \{
+ * \ingroup     RTC_Exported_Constants
+ */
+
+typedef enum
+{
+    RTC_COMP0GT = 0x0,     //!< RTC comparator GT index0.
+    RTC_COMP1GT = 0x1,     //!< RTC comparator GT index1.
+    RTC_COMP2GT = 0x2,     //!< RTC comparator GT index2.
+    RTC_COMP3GT = 0x3,     //!< RTC comparator GT index3.
+} RTCCmopGTIndex_TypeDef;
+
+#define IS_RTC_COMPGT(COMP) (((COMP) == RTC_COMP0GT) || \
+                             ((COMP) == RTC_COMP1GT) || \
+                             ((COMP) == RTC_COMP2GT) || \
+                             ((COMP) == RTC_COMP3GT)) //!< Check if the input parameter is valid.
+
+/** End of RTC_ComparatorGT_Index
+  * \}
+  */
+#endif
+
+/**
+ * \defgroup    RTC_Interrupts RTC Interrupts
+ * \{
+ * \ingroup     RTC_Exported_Constants
+ */
+#define RTC_INT_TICK           BIT8     //!< RTC tick interrupt.
+#define RTC_INT_OVF            BIT9     //!< RTC overflow interrupt.
+#define RTC_INT_PRE_COMP       BIT10    //!< RTC PRECOMP interrupt.
+#define RTC_INT_PRE_COMP3      BIT11    //!< RTC PRECOMP&CMP3 interrupt.
+#define RTC_INT_COMP0          BIT16    //!< RTC CMP0 interrupt.
+#define RTC_INT_COMP1          BIT17    //!< RTC CMP1 interrupt.
+#define RTC_INT_COMP2          BIT18    //!< RTC CMP2 interrupt.
+#define RTC_INT_COMP3          BIT19    //!< RTC CMP3 interrupt.
+
+#define IS_RTC_INT(INT) (((INT) == RTC_INT_TICK) || \
+                         ((INT) == RTC_INT_OVF) || \
+                         ((INT) == RTC_INT_COMP0) || \
+                         ((INT) == RTC_INT_COMP1) || \
+                         ((INT) == RTC_INT_COMP2) || \
+                         ((INT) == RTC_INT_COMP3) || \
+                         ((INT) == RTC_INT_PRE_COMP) || \
+                         ((INT) == RTC_INT_PRE_COMP3)) //!< Check if the input parameter is valid.
+
+/** End of RTC_Interrupts
+  * \}
+  */
+
+/**
+ * \defgroup    RTC_Wakeup_Interrupts RTC Wakeup Interrupts
+ * \{
+ * \ingroup     RTC_Exported_Constants
+ */
+#if (RTC_SUPPORT_PRE_COMP_OVF_TICK_WAKE_UP == 1)
+#define RTC_WK_TICK            BIT8     //!< RTC tick wakeup interrupt.
+#define RTC_WK_OVF             BIT9     //!< RTC overflow wakeup interrupt. 
+#define RTC_WK_PRE_COMP        BIT10    //!< RTC PRECOMP wakeup interrupt.
+#define RTC_WK_PRE_COMP3       BIT11    //!< RTC PRECOMP&CMP3 wakeup interrupt.
+
+#define IS_RTC_WK_PRECOMP_OVF_TICK(WK) (((WK) == RTC_WK_TICK) || \
+                                        ((WK) == RTC_WK_OVF) || \
+                                        ((WK) == RTC_WK_PRE_COMP) || \
+                                        ((WK) == RTC_WK_PRE_COMP3)) //!< Check if the input parameter is valid.
+#else
+#define IS_RTC_WK_PRECOMP_OVF_TICK(WK) (0) //!< Check if the input parameter is valid.
+#endif
+
+#if (RTC_SUPPORT_COMPARE_GUARDTIME == 1)
+#define RTC_WK_COMP0GT         BIT12     //!< RTC CMP0 GT wakeup interrupt.
+#define RTC_WK_COMP1GT         BIT13     //!< RTC CMP1 GT wakeup interrupt.
+#define RTC_WK_COMP2GT         BIT14     //!< RTC CMP2 GT wakeup interrupt.
+#define RTC_WK_COMP3GT         BIT15     //!< RTC CMP3 GT wakeup interrupt.
+
+#define IS_RTC_WK_CMPGT(WK) (((WK) == RTC_WK_COMP0GT) || \
+                             ((WK) == RTC_WK_COMP1GT) || \
+                             ((WK) == RTC_WK_COMP2GT) || \
+                             ((WK) == RTC_WK_COMP3GT)) //!< Check if the input parameter is valid.
+#else
+#define IS_RTC_WK_CMPGT(WK) (0) //!< Check if the input parameter is valid.
+#endif
+
+#define RTC_WK_COMP0           BIT20     //!< RTC CMP0 wakeup interrupt.
+#define RTC_WK_COMP1           BIT21     //!< RTC CMP1 wakeup interrupt.
+#define RTC_WK_COMP2           BIT22     //!< RTC CMP2 wakeup interrupt.
+#define RTC_WK_COMP3           BIT23     //!< RTC CMP3 wakeup interrupt.
+
+#define IS_RTC_WK(WK)         (((WK) == RTC_WK_COMP0) || \
+                               ((WK) == RTC_WK_COMP1) || \
+                               ((WK) == RTC_WK_COMP2) || \
+                               ((WK) == RTC_WK_COMP3) || \
+                               (IS_RTC_WK_CMPGT(WK)) || \
+                               (IS_RTC_WK_PRECOMP_OVF_TICK(WK))) //!< Check if the input parameter is valid.
+
+/** End of RTC_Wakeup_Interrupts
+  * \}
+  */
+
+/**
+ * \defgroup    RTC_Interrupt_Clear RTC Interrupt Clear
+ * \{
+ * \ingroup     RTC_Exported_Constants
+ */
+#define RTC_COMP3_CLR               (RTC_INT_COMP3     >> 8)    //!< Clear interrupt status of CMP3.
+#define RTC_COMP2_CLR               (RTC_INT_COMP2     >> 8)    //!< Clear interrupt status of CMP2.
+#define RTC_COMP1_CLR               (RTC_INT_COMP1     >> 8)    //!< Clear interrupt status of CMP1.
+#define RTC_COMP0_CLR               (RTC_INT_COMP0     >> 8)    //!< Clear interrupt status of CMP0.
+#define RTC_PRE_COMP3_CLR           (RTC_INT_PRE_COMP3 >> 8)    //!< Clear interrupt status of PRECOMP&CMP3.
+#define RTC_PRE_COMP_CLR            (RTC_INT_PRE_COMP  >> 8)    //!< Clear interrupt status of PRECOMP.
+#define RTC_OVERFLOW_CLR            (RTC_INT_OVF       >> 8)    //!< Clear interrupt status of overflow.
+#define RTC_TICK_CLR                (RTC_INT_TICK      >> 8)    //!< Clear interrupt status of tick.
+
+#define RTC_ALL_INT_CLR             (RTC_PRE_COMP3_CLR | \
+                                     RTC_PRE_COMP_CLR | \
+                                     RTC_COMP3_CLR | \
+                                     RTC_COMP2_CLR | \
+                                     RTC_COMP1_CLR | \
+                                     RTC_COMP0_CLR | \
+                                     RTC_OVERFLOW_CLR | \
+                                     RTC_TICK_CLR) //!< Check if the input parameter is valid.
+
+/** End of RTC_Interrupt_Clear
+  * \}
+  */
+
+/**
+ * \defgroup    RTC_Wakeup_Clear RTC Wakeup Clear
+ * \{
+ * \ingroup     RTC_Exported_Constants
+ */
+#if (RTC_SUPPORT_COMPARE_GUARDTIME == 1)
+#define RTC_COMP3GT_CLR             (RTC_WK_COMP3GT >> 8)    //!< Clear interrupt status of CMP3GT.
+#define RTC_COMP2GT_CLR             (RTC_WK_COMP2GT >> 8)    //!< Clear interrupt status of CMP2GT.
+#define RTC_COMP1GT_CLR             (RTC_WK_COMP1GT >> 8)    //!< Clear interrupt status of CMP1GT.
+#define RTC_COMP0GT_CLR             (RTC_WK_COMP0GT >> 8)    //!< Clear interrupt status of CMP0GT.
+
+#define RTC_COMPGT_WAKEUP_CLR       (RTC_COMP3GT_CLR | \
+                                     RTC_COMP2GT_CLR | \
+                                     RTC_COMP1GT_CLR | \
+                                     RTC_COMP0GT_CLR) //!< Check if the input parameter is valid.
+#else
+#define RTC_COMPGT_WAKEUP_CLR       (0) //!< Check if the input parameter is valid.
+#endif
+
+#define RTC_COMP3_WK_CLR            (RTC_WK_COMP3   >> 8)    //!< Clear interrupt status of CMP3 wakeup.
+#define RTC_COMP2_WK_CLR            (RTC_WK_COMP2   >> 8)    //!< Clear interrupt status of CMP2 wakeup.
+#define RTC_COMP1_WK_CLR            (RTC_WK_COMP1   >> 8)    //!< Clear interrupt status of CMP1 wakeup.
+#define RTC_COMP0_WK_CLR            (RTC_WK_COMP0   >> 8)    //!< Clear interrupt status of CMP0 wakeup.
+
+#define RTC_ALL_WAKEUP_CLR          (RTC_COMP3_WK_CLR | \
+                                     RTC_COMP2_WK_CLR | \
+                                     RTC_COMP1_WK_CLR | \
+                                     RTC_COMP0_WK_CLR | \
+                                     RTC_COMPGT_WAKEUP_CLR) //!< Check if the input parameter is valid.
+
+/** End of RTC_Wakeup_Clear
+  * \}
+  */
+
+#if (RTC_SUPPORT_RAP_FUNCTION == 1)
+/**
+ * \defgroup    RTC_Task RTC Task
+ * \{
+ * \ingroup     RTC_Exported_Constants
+ */
+typedef enum
+{
+    RTC_TASK_START = 0,
+    RTC_TASK_STOP  = 1,
+    RTC_TASK_CLR = 2,
+} RTCTask_TypeDef;
+
+/** End of RTC_Task
+  * \}
+  */
+
+/**
+ * \defgroup    RTC_Shortcut_Task RTC Shortcut Task
+ * \{
+ * \ingroup     RTC_Exported_Constants
+ */
+typedef enum
+{
+    RTC_SHORTCUT_TASK_STOP = 1,
+    RTC_SHORTCUT_TASK_CLEAR = 2,
+} RTCShortcutTask_TypeDef;
+
+/** End of RTC_Shortcut_Task
+  * \}
+  */
+
+/**
+ * \defgroup    RTC_Shortcut_Event RTC Shortcut Event
+ * \{
+ * \ingroup     RTC_Exported_Constants
+ */
+typedef enum
+{
+    RTC_SHORTCUT_EVENT_COM0 = 0,
+    RTC_SHORTCUT_EVENT_COM1 = 1,
+    RTC_SHORTCUT_EVENT_COM2 = 2,
+    RTC_SHORTCUT_EVENT_COM3 = 3,
+} RTCShortcutEvent_TypeDef;
+
+/** End of RTC_Shortcut_Event
+  * \}
+  */
+#endif
+
+/** End of RTC_Exported_Constants
+  * \}
+  */
+
+/*============================================================================*
+ *                         Functions
+ *============================================================================*/
+/** \defgroup RTC_Exported_Functions RTC Exported Functions
+  * \brief
+  * \{
+  */
+
+/**
+ * \brief     Deinitialize the RTC peripheral registers to their default reset values(turn off clock).
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_rtc_init(void)
+ * {
+ *     RTC_DeInit();
+ * }
+ * \endcode
+ */
+void RTC_DeInit(void);
+
+/**
+ * \brief     Set RTC prescaler value.
+ *
+ * \param[in] value  The prescaler value to be set. Should be no more than 12 bits!
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * #define RTC_PRESCALER_VALUE     49
+ * #define RTC_COMP_INDEX          RTC_COMP3
+ * #define RTC_COMP_INDEX_INT      RTC_INT_COMP3
+ * #define RTC_COMP_VALUE          (1000)
+ *
+ * void driver_rtc_init(void)
+ * {
+ *     RTC_DeInit();
+ *
+ *     RTC_SetPrescaler(RTC_PRESCALER_VALUE);
+ *     RTC_SetCompValue(RTC_COMP_INDEX, RTC_COMP_VALUE);
+ *
+ *     RTC_MaskINTConfig(RTC_COMP_INDEX_INT, DISABLE);
+ *     RTC_INTConfig(RTC_COMP_INDEX_INT, ENABLE);
+ *
+ *     RTC_NvCmd(ENABLE);
+ *     RTC_Cmd(ENABLE);
+ * }
+ * \endcode
+ */
+void RTC_SetPrescaler(uint16_t value);
+
+/**
+ * \brief     Start or stop RTC peripheral.
+ *
+ * \param[in] NewState  New state of RTC peripheral.
+ *                      This parameter can be one of the following values:
+ *                      - ENABLE: RTC count start.
+ *                      - DISABLE: RTC count stop and clear count value.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * #define RTC_PRESCALER_VALUE     49
+ * #define RTC_COMP_INDEX          RTC_COMP3
+ * #define RTC_COMP_INDEX_INT      RTC_INT_COMP3
+ * #define RTC_COMP_VALUE          (1000)
+ *
+ * void driver_rtc_init(void)
+ * {
+ *     RTC_DeInit();
+ *
+ *     RTC_SetPrescaler(RTC_PRESCALER_VALUE);
+ *     RTC_SetCompValue(RTC_COMP_INDEX, RTC_COMP_VALUE);
+ *
+ *     RTC_MaskINTConfig(RTC_COMP_INDEX_INT, DISABLE);
+ *     RTC_INTConfig(RTC_COMP_INDEX_INT, ENABLE);
+ *
+ *     RTC_NvCmd(ENABLE);
+ *     RTC_Cmd(ENABLE);
+ * }
+ * \endcode
+ */
+void RTC_Cmd(FunctionalState NewState);
+
+/**
+ * \brief     Enable or disable the specified RTC interrupt source.
+ *
+ * \param[in] RTC_INT   Specify the RTC interrupt sources.
+ *                      This parameter can be any combination of the following values, refer to \ref RTC_Interrupts.
+ *                      \arg RTC_INT_TICK: tick interrupt.
+ *                      \arg RTC_INT_OVF: counter overflow interrupt
+ *                      \arg RTC_INT_COMP0: Compare 0 interrupt.
+ *                      \arg RTC_INT_COMP1: Compare 1 interrupt.
+ *                      \arg RTC_INT_COMP2: Compare 2 interrupt.
+ *                      \arg RTC_INT_COMP3: Compare 3 interrupt.
+ *                      \arg RTC_INT_PRE_COMP: Prescale compare interrupt.
+ *                      \arg RTC_INT_PRE_COMP3: Prescale & compare 3 interrupt.
+ * \param[in] NewState  New state of the specified RTC interrupt.
+ *                      This parameter can be one of the following values:
+ *                      - ENABLE: Enable the specified interrupt of RTC.
+ *                      - DISABLE: Disable the specified interrupt of RTC.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * #define RTC_PRESCALER_VALUE     49
+ * #define RTC_COMP_INDEX          RTC_COMP3
+ * #define RTC_COMP_INDEX_INT      RTC_INT_COMP3
+ * #define RTC_COMP_VALUE          (1000)
+ *
+ * void driver_rtc_init(void)
+ * {
+ *     RTC_DeInit();
+ *
+ *     RTC_SetPrescaler(RTC_PRESCALER_VALUE);
+ *     RTC_SetCompValue(RTC_COMP_INDEX, RTC_COMP_VALUE);
+ *
+ *     RTC_MaskINTConfig(RTC_COMP_INDEX_INT, DISABLE);
+ *     RTC_INTConfig(RTC_COMP_INDEX_INT, ENABLE);
+ *
+ *     RTC_NvCmd(ENABLE);
+ *     RTC_Cmd(ENABLE);
+ * }
+ * \endcode
+ */
+void RTC_INTConfig(uint32_t RTC_INT, FunctionalState NewState);
+
+/**
+ * \brief  Enable or disable the specified RTC wakeup function.
+ *
+ * \param[in] RTC_WK    Specify the RTC wakeup sources.
+ *                      This parameter can be any combination of the following values.
+ *                      Refer to \ref RTC_Wakeup_Interrupts.
+ *                      \arg RTC_WK_TICK: tick wakeup function
+ *                      \arg RTC_WK_OVF: tick wakeup function
+ *                      \arg RTC_WK_PRE_COMP: prescale compare wakeup function
+ *                      \arg RTC_WK_PRE_COMP3: prescale & compare 3 wakeup function
+ *                      \arg RTC_WK_COMP0GT: compare 0 gt wakeup function
+ *                      \arg RTC_WK_COMP1GT: compare 1 gt wakeup function
+ *                      \arg RTC_WK_COMP2GT: compare 2 gt wakeup function
+ *                      \arg RTC_WK_COMP3GT: compare 3 gt wakeup function
+ *                      \arg RTC_WK_COMP0: compare 0 wakeup function
+ *                      \arg RTC_WK_COMP1: compare 1 wakeup function
+ *                      \arg RTC_WK_COMP2: compare 2 wakeup function
+ *                      \arg RTC_WK_COMP3: compare 3 wakeup function
+ * \param[in] NewState  New state of the specified RTC wakeup function.
+ *                      This parameter can be one of the following values:
+ *                      - ENABLE: Enable the specified interrupt of RTC wakeup.
+ *                      - DISABLE: Disable the specified interrupt of RTC wakeup.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * #define RTC_PRESCALER_VALUE     49
+ * #define RTC_COMP_INDEX          RTC_COMP3
+ * #define RTC_COMP_INDEX_INT      RTC_INT_COMP3
+ * #define RTC_COMP_VALUE          (1000)
+ *
+ * void driver_rtc_init(void)
+ * {
+ *     RTC_DeInit();
+ *
+ *     RTC_SetPrescaler(RTC_PRESCALER_VALUE);
+ *     RTC_SetCompValue(RTC_COMP_INDEX, RTC_COMP_VALUE);
+ *
+ *     RTC_MaskINTConfig(RTC_COMP_INDEX_INT, DISABLE);
+ *     RTC_INTConfig(RTC_COMP_INDEX_INT, ENABLE);
+ *     RTC_WKConfig(RTC_WK_TICK, ENABLE);
+ *     RTC_NvCmd(ENABLE);
+ *     RTC_Cmd(ENABLE);
+ * }
+ * \endcode
+ */
+void RTC_WKConfig(uint32_t RTC_WK, FunctionalState NewState);
+
+/**
+ * \brief     Enable or disable RTC interrupt signal to CPU NVIC.
+ *
+ * \param[in] NewState  Enable or disable RTC interrupt signal to CPU.
+ *                      This parameter can be one of the following values:
+ *                      - ENABLE: Enable the interrupt of CPU NVIC.
+ *                      - DISABLE: Disable the interrupt of CPU NVIC.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * #define RTC_PRESCALER_VALUE     49
+ * #define RTC_COMP_INDEX          RTC_COMP3
+ * #define RTC_COMP_INDEX_INT      RTC_INT_COMP3
+ * #define RTC_COMP_VALUE          (1000)
+ *
+ * void driver_rtc_init(void)
+ * {
+ *     RTC_DeInit();
+ *
+ *     RTC_SetPrescaler(RTC_PRESCALER_VALUE);
+ *     RTC_SetCompValue(RTC_COMP_INDEX, RTC_COMP_VALUE);
+ *
+ *     RTC_MaskINTConfig(RTC_COMP_INDEX_INT, DISABLE);
+ *     RTC_INTConfig(RTC_COMP_INDEX_INT, ENABLE);
+ *
+ *     RTC_NvCmd(ENABLE);
+ *     RTC_Cmd(ENABLE);
+ * }
+ * \endcode
+ */
+void RTC_NvCmd(FunctionalState NewState);
+
+/**
+ * \brief     Enable or disable system wake up function of RTC.
+ *
+ * \param[in] NewState  New state of the wake up function.
+ *                      This parameter can be one of the following values:
+ *                      - ENABLE: Enable the system wake up function.
+ *                      - DISABLE: Disable the system wake up function.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void rtc_demo(void)
+ * {
+ *     RTC_SystemWakeupConfig(ENABLE);
+ * }
+ * \endcode
+ */
+void RTC_SystemWakeupConfig(FunctionalState NewState);
+
+/**
+ * \brief     Reset counter value of RTC.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void rtc_demo(void)
+ * {
+ *     RTC_ResetCounter();
+ *     RTC_Cmd(ENABLE);
+ * }
+ * \endcode
+ */
+void RTC_ResetCounter(void);
+
+/**
+ * \brief     Reset prescaler counter value of RTC.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void rtc_demo(void)
+ * {
+ *     RTC_ResetPrescalerCounter();
+ *     RTC_Cmd(ENABLE);
+ * }
+ * \endcode
+ */
+void RTC_ResetPrescalerCounter(void);
+
+/**
+ * \brief  Get the specified RTC interrupt status.
+ *
+ * \param[in] RTC_INT  Specify the RTC interrupt sources.
+ *                     This parameter can be any combination of the following values.
+ *                     Refer to \ref RTC_Interrupts.
+ *                     - RTC_INT_TICK: RTC tick interrupt source.
+ *                     - RTC_INT_COMP0: Compare 0 interrupt source.
+ *                     - RTC_INT_COMP1: Compare 1 interrupt source.
+ *                     - RTC_INT_COMP2: Compare 2 interrupt source.
+ *                     - RTC_INT_COMP3: Compare 3 interrupt source.
+ *                     - RTC_INT_PRE_COMP: Prescale compare interrupt source.
+ *                     - RTC_INT_PRE_COMP3: Prescale & compare 3 interrupt source.
+ *
+ * \return  The status of \ref RTC_Interrupts.
+ *          - SET: The RTC interrupt has occurred.
+ *          - RESET: The RTC interrupt has not occurred.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void rtc_demo(void)
+ * {
+ *     ITStatus int_status = RTC_GetINTStatus(RTC_INT_COMP0);
+ * }
+ * \endcode
+ */
+ITStatus RTC_GetINTStatus(uint32_t RTC_INT);
+
+/**
+ * \brief     Clear the interrupt pending bits of RTC.
+ *
+ * \param[in] RTC_INT  Specify the RTC interrupt flag to clear.
+ *                     This parameter can be any combination of the following values.
+ *                     Refer to \ref RTC_Interrupts.
+ *                     - RTC_INT_TICK: RTC tick interrupt source.
+ *                     - RTC_INT_OVF: RTC counter overflow interrupt source.
+ *                     - RTC_INT_COMP0: Compare 0 interrupt source.
+ *                     - RTC_INT_COMP1: Compare 1 interrupt source.
+ *                     - RTC_INT_COMP2: Compare 2 interrupt source.
+ *                     - RTC_INT_COMP3: Compare 3 interrupt source.
+ *                     - RTC_INT_PRE_COMP: Prescale compare interrupt source.
+ *                     - RTC_INT_PRE_COMP3: Prescale & compare 3 interrupt source.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void rtc_demo(void)
+ * {
+ *     RTC_ClearINTPendingBit(RTC_INT_COMP0);
+ * }
+ * \endcode
+ */
+void RTC_ClearINTPendingBit(uint32_t RTC_INT);
+
+/**
+ * \brief  Get the specified RTC wakeup interrupt status.
+ *
+ * \param[in] RTC_WK  Specify the RTC wakeup interrupt sources.
+ *                    This parameter can be any combination of the following values.
+ *                    Refer to \ref RTC_Wakeup_Interrupts.
+ *                    \arg RTC_WK_TICK: tick wakeup function
+ *                    \arg RTC_WK_OVF: tick wakeup function
+ *                    \arg RTC_WK_PRE_COMP: prescale compare wakeup function
+ *                    \arg RTC_WK_PRE_COMP3: prescale & compare 3 wakeup function
+ *                    \arg RTC_WK_COMP0GT: compare 0 gt wakeup function
+ *                    \arg RTC_WK_COMP1GT: compare 1 gt wakeup function
+ *                    \arg RTC_WK_COMP2GT: compare 2 gt wakeup function
+ *                    \arg RTC_WK_COMP3GT: compare 3 gt wakeup function
+ *                    \arg RTC_WK_COMP0: compare 0 wakeup function
+ *                    \arg RTC_WK_COMP1: compare 1 wakeup function
+ *                    \arg RTC_WK_COMP2: compare 2 wakeup function
+ *                    \arg RTC_WK_COMP3: compare 3 wakeup function
+ *
+ * \return  The status of \ref RTC_Wakeup.
+ *          - SET: The RTC wakeup interrupt has occurred.
+ *          - RESET: The RTC wakeup interrupt has not occurred.
+ */
+ITStatus RTC_GetWakeupStatus(uint32_t RTC_WK);
+
+/**
+ * \brief  Clear the wakeup status bits of RTC.
+ *
+ * \param[in] RTC_WK  Specify the RTC wakeup flag to clear.
+ *                    This parameter can be any combination of the following values.
+ *                    Refer to \ref RTC_Wakeup_Interrupts.
+ *                    \arg RTC_WK_TICK: tick wakeup function
+ *                    \arg RTC_WK_OVF: tick wakeup function
+ *                    \arg RTC_WK_PRE_COMP: prescale compare wakeup function
+ *                    \arg RTC_WK_PRE_COMP3: prescale & compare 3 wakeup function
+ *                    \arg RTC_WK_COMP0GT: compare 0 gt wakeup function
+ *                    \arg RTC_WK_COMP1GT: compare 1 gt wakeup function
+ *                    \arg RTC_WK_COMP2GT: compare 2 gt wakeup function
+ *                    \arg RTC_WK_COMP3GT: compare 3 gt wakeup function
+ *                    \arg RTC_WK_COMP0: compare 0 wakeup function
+ *                    \arg RTC_WK_COMP1: compare 1 wakeup function
+ *                    \arg RTC_WK_COMP2: compare 2 wakeup function
+ *                    \arg RTC_WK_COMP3: compare 3 wakeup function
+ */
+void RTC_ClearWakeupStatusBit(uint32_t RTC_WK);
+
+/**
+ * \brief     Clear the interrupt pending bit of the select comparator of RTC.
+ *
+ * \param[in] index  The comparator number, Refer to \ref RTC_Comparator_Index.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void rtc_demo(void)
+ * {
+ *     RTC_ClearCompINT(RTC_COMP0);
+ * }
+ * \endcode
+ */
+void RTC_ClearCompINT(RTCComIndex_TypeDef index);
+
+/**
+ * \brief     Clear the overflow interrupt pending bit of RTC.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void rtc_demo(void)
+ * {
+ *     RTC_ClearOverFlowINT();
+ * }
+ * \endcode
+ */
+void RTC_ClearOverFlowINT(void);
+
+/**
+ * \brief     Clear the tick interrupt pending bit of RTC.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void rtc_demo(void)
+ * {
+ *     RTC_ClearTickINT();
+ * }
+ * \endcode
+ */
+void RTC_ClearTickINT(void);
+
+#if (RTC_SUPPORT_CLK_INPUT_FROM_PAD_SEL == 1)
+/**
+ * \brief  Use the GPIO input signal as the clock source for the RTC.
+ *
+ * \param[in] rtc_in  The selected gpio pin.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void rtc_demo(void)
+ * {
+ *     RTC_SelectSrcToGpioInput(PAD_P2_4_RTC_IN);
+ * }
+ * \endcode
+ */
+void RTC_SelectSrcToGpioInput(RTCInSel_TypeDef rtc_in);
+#endif
+
+/**
+ * \brief     Set RTC comparator value.
+ *
+ * \param[in] index  The comparator number can range from 0 to 3, Refer to \ref RTC_Comparator_Index.
+ * \param[in] value  The comparator value to be set. Should be no more than 24 bits!
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * #define RTC_PRESCALER_VALUE     49
+ * #define RTC_COMP_INDEX          RTC_COMP3
+ * #define RTC_COMP_INDEX_INT      RTC_INT_COMP3
+ * #define RTC_COMP_VALUE          (1000)
+ *
+ * void driver_rtc_init(void)
+ * {
+ *     RTC_DeInit();
+ *
+ *     RTC_SetPrescaler(RTC_PRESCALER_VALUE);
+ *     RTC_SetCompValue(RTC_COMP_INDEX, RTC_COMP_VALUE);
+ *
+ *     RTC_MaskINTConfig(RTC_COMP_INDEX_INT, DISABLE);
+ *     RTC_INTConfig(RTC_COMP_INDEX_INT, ENABLE);
+ *
+ *     RTC_NvCmd(ENABLE);
+ *     RTC_Cmd(ENABLE);
+ * }
+ * \endcode
+ */
+void RTC_SetCompValue(RTCComIndex_TypeDef index, uint32_t value);
+
+#if (RTC_SUPPORT_COMPARE_GUARDTIME == 1)
+/**
+ * \brief     Set RTC comparator GT value.
+ *
+ * \param[in] index  The comparator gt number can range from 0 ~ 3, Refer to \ref RTC_ComparatorGT_Index.
+ * \param[in] value  The comparator value to be set.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * #define RTC_PRESCALER_VALUE     49
+ * #define RTC_COMP_INDEX          RTC_COMP3
+ * #define RTC_COMP_INDEX_INT      RTC_INT_COMP3
+ * #define RTC_COMP_VALUE          (1000)
+ *
+ * void driver_rtc_init(void)
+ * {
+ *     RTC_DeInit();
+ *
+ *     RTC_SetPrescaler(RTC_PRESCALER_VALUE);
+ *     RTC_SetCompValue(RTC_COMP_INDEX, RTC_COMP_VALUE);
+ *
+ *     RTC_MaskINTConfig(RTC_COMP_INDEX_INT, DISABLE);
+ *     RTC_INTConfig(RTC_COMP_INDEX_INT, ENABLE);
+ *
+ *     RTC_NvCmd(ENABLE);
+ *     RTC_Cmd(ENABLE);
+ * }
+ * \endcode
+ */
+void RTC_SetCompGTValue(RTCCmopGTIndex_TypeDef index, uint32_t value);
+#endif
+
+/**
+ * \brief     Set RTC prescaler comparator value.
+ *
+ * \param[in] value  The prescaler comparator value to be set. Should be no more than 12 bits!
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * #define RTC_PRESCALER_VALUE     (3200 - 1)//max 4095
+ * #define RTC_PRECOMP_VALUE       (320)//max 4095
+ * #define RTC_COMP3_VALUE         (10)
+ *
+ * void driver_rtc_init(void)
+ * {
+ *     RTC_DeInit();
+ *
+ *     RTC_SetPrescaler(RTC_PRESCALER_VALUE);
+ *     RTC_SetPreCompValue(RTC_PRECOMP_VALUE);
+ *     RTC_SetCompValue(RTC_COMP3, RTC_COMP3_VALUE);
+ *
+ *     RTC_MaskINTConfig(RTC_INT_PRE_COMP3, DISABLE);
+ *     RTC_INTConfig(RTC_INT_PRE_COMP3, ENABLE);
+ *
+ *     RTC_NvCmd(ENABLE);
+ *     RTC_Cmd(ENABLE);
+ * }
+ * \endcode
+ */
+void RTC_SetPreCompValue(uint32_t value);
+
+/**
+ * \brief     Get counter value of RTC.
+ *
+ * \return    The counter value.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void rtc_demo(void)
+ * {
+ *     uitn32_t counter = RTC_GetCounter();
+ * }
+ * \endcode
+ */
+uint32_t RTC_GetCounter(void);
+
+/**
+ * \brief     Get prescaler counter value of RTC.
+ *
+ * \return    The prescaler counter value.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void rtc_demo(void)
+ * {
+ *     uitn32_t pre_counter = RTC_GetPreCounter();
+ * }
+ * \endcode
+ */
+uint32_t RTC_GetPreCounter(void);
+
+/**
+ * \brief     Get RTC comparator value.
+ *
+ * \param[in] index  The comparator number,  Refer to \ref RTC_Comparator_Index
+ *
+ * \return    The comparator value.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void rtc_demo(void)
+ * {
+ *     uint32_t data = RTC_GetCompValue(RTC_COMP0);
+ * }
+ * \endcode
+ */
+uint32_t RTC_GetCompValue(RTCComIndex_TypeDef index);
+
+#if (RTC_SUPPORT_COMPARE_GUARDTIME == 1)
+/**
+ * \brief     Get RTC comparator gt value.
+ *
+ * \param[in] index  The comparator number 0~3, Refer to \ref RTC_ComparatorGT_Index.
+ *
+ * \return    The comparator value.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void rtc_demo(void)
+ * {
+ *     uitn32_t data = RTC_GetCompGTValue(RTC_COMP0);
+ * }
+ * \endcode
+ */
+uint32_t RTC_GetCompGTValue(RTCCmopGTIndex_TypeDef index);
+#endif
+
+/**
+ * \brief     Get RTC prescaler comparator value.
+ *
+ * \return    The prescaler comparator value.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void rtc_demo(void)
+ * {
+ *     uitn32_t data = RTC_GetPreCompValue();
+ * }
+ * \endcode
+ */
+uint32_t RTC_GetPreCompValue(void);
+
+/**
+ * \brief     Write backup register for store time information.
+ *
+ * \param[in] value  The data to be written to the backup register.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void rtc_demo(void)
+ * {
+ *     RTC_WriteBackupReg(0x01020304);
+ * }
+ * \endcode
+ */
+void RTC_WriteBackupReg(uint32_t value);
+
+/**
+ * \brief     Read backup register.
+ *
+ * \return    Register value.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void rtc_demo(void)
+ * {
+ *     uint32_t reg_data = RTC_ReadBackupReg();
+ * }
+ * \endcode
+ */
+uint32_t RTC_ReadBackupReg(void);
+
+#if (RTC_SUPPORT_RAP_FUNCTION == 1)
+
+void RTC_RAPQactiveCtrl(uint32_t Qactive, FunctionalState NewState);
+
+void RTC_RAPModeCmd(FunctionalState NewState);
+
+void RTC_TaskTrigger(uint32_t Task);
+
+void RTC_ShortcutCmd(uint32_t Task, uint32_t Event, FunctionalState NewState);
+
+#endif
+
+/** End of RTC_Exported_Functions
+  * \}
+  */
+
+/** End of RTC
+  * \}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RTL_RTC_H */
+
+
+
diff --git a/bee/drivers/rtc/src/device/rtl87x2g/rtl_rtc_def.h b/bee/drivers/rtc/src/device/rtl87x2g/rtl_rtc_def.h
new file mode 100644
index 00000000..cb89a060
--- /dev/null
+++ b/bee/drivers/rtc/src/device/rtl87x2g/rtl_rtc_def.h
@@ -0,0 +1,501 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef RTL_RTC_DEF_H
+#define RTL_RTC_DEF_H
+
+#include "utils/rtl_utils.h"
+#include "address_map.h"
+#include "aon_reg.h"
+
+#ifdef  __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+
+/*============================================================================*
+ *                          RTC Defines
+ *============================================================================*/
+/** \defgroup RTC         RTC
+  * \brief
+  * \{
+  */
+
+/** \defgroup RTC_Exported_Constants RTC Exported Constants
+  * \brief
+  * \{
+  */
+
+/**
+ * \defgroup RTC_Defines RTC Defines
+ * \{
+ * \ingroup  RTC_Exported_Constants
+ */
+#define RTC_SUPPORT_CLK_INPUT_FROM_PAD_SEL      (1) //!< The definition supports gpio input of RTC.
+#define RTC_SUPPORT_PRE_COMP_OVF_TICK_WAKE_UP   (1) //!< The definition supports interrupt wakeup.
+#define RTC_SUPPORT_COMPARE_GUARDTIME           (1) //!< The definition supports comparator guardtime.
+
+/** End of RTC_Defines
+  * \}
+  */
+
+/** End of RTC_Exported_Constants
+  * \}
+  */
+
+/** End of RTC
+  * \}
+  */
+
+/*============================================================================*
+ *                         RTC Registers Memory Map
+ *============================================================================*/
+typedef struct
+{
+    __IO uint32_t RTC_CR0;                  /*!< 0X00 */
+    __IO uint32_t RTC_INT_CLEAR;            /*!< 0X04 */
+    __IO uint32_t RTC_INT_SR;               /*!< 0X08 */
+    __IO uint32_t RTC_PRESCALER0;           /*!< 0X0C */
+    __IO uint32_t RTC_COMP_0;               /*!< 0X10 */
+    __IO uint32_t RTC_COMP_1;               /*!< 0X14 */
+    __IO uint32_t RTC_COMP_2;               /*!< 0X18 */
+    __IO uint32_t RTC_COMP_3;               /*!< 0X1C */
+    __IO uint32_t RTC_COMP0_GT;             /*!< 0X20 */
+    __IO uint32_t RTC_COMP1_GT;             /*!< 0X24 */
+    __IO uint32_t RTC_COMP2_GT;             /*!< 0X28 */
+    __IO uint32_t RTC_COMP3_GT;             /*!< 0X2C */
+    __I  uint32_t RTC_CNT0;                 /*!< 0X30 */
+    __IO uint32_t RTC_PRESCALE_CNT0;        /*!< 0X34 */
+    __IO uint32_t RTC_PRESCALE_CMP0;        /*!< 0X38 */
+    __IO uint32_t RTC_BACKUP;               /*!< 0X3C */
+    __I  uint32_t RTC_RTL_VERSION0;         /*!< 0X40 */
+} RTC_TypeDef;
+
+/*============================================================================*
+ *                         RTC Declaration
+ *============================================================================*/
+#define RTC                ((RTC_TypeDef *) RTC_REG_BASE)
+
+/*============================================================================*
+ *                         RTC Registers and Field Descriptions
+ *============================================================================*/
+/* 0x00
+   0       R/W    rtc_cnt_start           1'b0
+   1       R/W    rtc_cnt_rst             1'b0
+   2       R/W    rtc_pre_cnt_rst         1'b0
+   7:3     R/W    rtc_cr0_dummy0          5'b0
+   8       R/W    rtc_tick_ie             1'b0
+   9       R/W    rtc_cnt_ov_ie           1'b0
+   10      R/W    rtc_precmp_ie           1'b0
+   11      R/W    rtc_precmp_cmp3_ie      1'b0
+   12      R/W    rtc_cmp0gt_ie           1'b0
+   13      R/W    rtc_cmp1gt_ie           1'b0
+   14      R/W    rtc_cmp2gt_ie           1'b0
+   15      R/W    rtc_cmp3gt_ie           1'b0
+   16      R/W    rtc_cmp0_nv_ie          1'b0
+   17      R/W    rtc_cmp1_nv_ie          1'b0
+   18      R/W    rtc_cmp2_nv_ie          1'b0
+   19      R/W    rtc_cmp3_nv_ie          1'b0
+   20      R/W    rtc_cmp0_wk_ie          1'b0
+   21      R/W    rtc_cmp1_wk_ie          1'b0
+   22      R/W    rtc_cmp2_wk_ie          1'b0
+   23      R/W    rtc_cmp3_wk_ie          1'b0
+   28:24   R/W    rtc_cr0_dummy1          5'b0
+   29      R/W    rtc_wk_ie               1'b0
+   30      R/W    rtc_nv_ie               1'b0
+   31      R/W    rtc_rst                 1'b0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t rtc_cnt_start: 1;
+        uint32_t rtc_cnt_rst: 1;
+        uint32_t rtc_pre_cnt_rst: 1;
+        uint32_t rtc_cr0_dummy0: 5;
+        uint32_t rtc_tick_ie: 1;
+        uint32_t rtc_cnt_ov_ie: 1;
+        uint32_t rtc_precmp_ie: 1;
+        uint32_t rtc_precmp_cmp3_ie: 1;
+        uint32_t rtc_cmp0gt_ie: 1;
+        uint32_t rtc_cmp1gt_ie: 1;
+        uint32_t rtc_cmp2gt_ie: 1;
+        uint32_t rtc_cmp3gt_ie: 1;
+        uint32_t rtc_cmp0_nv_ie: 1;
+        uint32_t rtc_cmp1_nv_ie: 1;
+        uint32_t rtc_cmp2_nv_ie: 1;
+        uint32_t rtc_cmp3_nv_ie: 1;
+        uint32_t rtc_cmp0_wk_ie: 1;
+        uint32_t rtc_cmp1_wk_ie: 1;
+        uint32_t rtc_cmp2_wk_ie: 1;
+        uint32_t rtc_cmp3_wk_ie: 1;
+        uint32_t rtc_cr0_dummy1: 5;
+        uint32_t rtc_wk_ie: 1;
+        uint32_t rtc_nv_ie: 1;
+        uint32_t rtc_rst: 1;
+    } b;
+} RTC_CR0_TypeDef;
+
+
+
+/* 0x04
+   0       R/WAC  rtc_tick_clr            1'b0
+   1       R/WAC  rtc_cnt_ov_clr          1'b0
+   2       R/WAC  rtc_precmp_clr          1'b0
+   3       R/WAC  rtc_precmp_cmp3_clr     1'b0
+   4       R/WAC  rtc_cmp0gt_clr          1'b0
+   5       R/WAC  rtc_cmp1gt_clr          1'b0
+   6       R/WAC  rtc_cmp2gt_clr          1'b0
+   7       R/WAC  rtc_cmp3gt_clr          1'b0
+   8       R/WAC  rtc_cmp0_nv_clr         1'b0
+   9       R/WAC  rtc_cmp1_nv_clr         1'b0
+   10      R/WAC  rtc_cmp2_nv_clr         1'b0
+   11      R/WAC  rtc_cmp3_nv_clr         1'b0
+   12      R/WAC  rtc_cmp0_wk_clr         1'b0
+   13      R/WAC  rtc_cmp1_wk_clr         1'b0
+   14      R/WAC  rtc_cmp2_wk_clr         1'b0
+   15      R/WAC  rtc_cmp3_wk_clr         1'b0
+   31:16   R/W    rtc_int_clear_dummy     16'b0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t rtc_tick_clr: 1;
+        uint32_t rtc_cnt_ov_clr: 1;
+        uint32_t rtc_precmp_clr: 1;
+        uint32_t rtc_precmp_cmp3_clr: 1;
+        uint32_t rtc_cmp0gt_clr: 1;
+        uint32_t rtc_cmp1gt_clr: 1;
+        uint32_t rtc_cmp2gt_clr: 1;
+        uint32_t rtc_cmp3gt_clr: 1;
+        uint32_t rtc_cmp0_nv_clr: 1;
+        uint32_t rtc_cmp1_nv_clr: 1;
+        uint32_t rtc_cmp2_nv_clr: 1;
+        uint32_t rtc_cmp3_nv_clr: 1;
+        uint32_t rtc_cmp0_wk_clr: 1;
+        uint32_t rtc_cmp1_wk_clr: 1;
+        uint32_t rtc_cmp2_wk_clr: 1;
+        uint32_t rtc_cmp3_wk_clr: 1;
+        uint32_t rtc_int_clear_dummy: 16;
+    } b;
+} RTC_INT_CLEAR_TypeDef;
+
+
+
+/* 0x08
+   0       R/W1C  rtc_tick_sr             1'b0
+   1       R/W1C  rtc_cnt_ov_sr           1'b0
+   2       R/W1C  rtc_precmp_sr           1'b0
+   3       R/W1C  rtc_precmp_cmp3_sr      1'b0
+   4       R/W1C  rtc_cmp0gt_sr           1'b0
+   5       R/W1C  rtc_cmp1gt_sr           1'b0
+   6       R/W1C  rtc_cmp2gt_sr           1'b0
+   7       R/W1C  rtc_cmp3gt_sr           1'b0
+   8       R/W1C  rtc_cmp0_nv_sr          1'b0
+   9       R/W1C  rtc_cmp1_nv_sr          1'b0
+   10      R/W1C  rtc_cmp2_nv_sr          1'b0
+   11      R/W1C  rtc_cmp3_nv_sr          1'b0
+   12      R/W1C  rtc_cmp0_wk_sr          1'b0
+   13      R/W1C  rtc_cmp1_wk_sr          1'b0
+   14      R/W1C  rtc_cmp2_wk_sr          1'b0
+   15      R/W1C  rtc_cmp3_wk_sr          1'b0
+   31:16   R/W    rtc_int_sr_dummy        16'b0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t rtc_tick_sr: 1;
+        uint32_t rtc_cnt_ov_sr: 1;
+        uint32_t rtc_precmp_sr: 1;
+        uint32_t rtc_precmp_cmp3_sr: 1;
+        uint32_t rtc_cmp0gt_sr: 1;
+        uint32_t rtc_cmp1gt_sr: 1;
+        uint32_t rtc_cmp2gt_sr: 1;
+        uint32_t rtc_cmp3gt_sr: 1;
+        uint32_t rtc_cmp0_nv_sr: 1;
+        uint32_t rtc_cmp1_nv_sr: 1;
+        uint32_t rtc_cmp2_nv_sr: 1;
+        uint32_t rtc_cmp3_nv_sr: 1;
+        uint32_t rtc_cmp0_wk_sr: 1;
+        uint32_t rtc_cmp1_wk_sr: 1;
+        uint32_t rtc_cmp2_wk_sr: 1;
+        uint32_t rtc_cmp3_wk_sr: 1;
+        uint32_t rtc_int_sr_dummy: 16;
+    } b;
+} RTC_INT_SR_TypeDef;
+
+
+
+/* 0x0C
+   11:0    R/W    rtc_prescaler           12'b0
+   31:12   R/W    rtc_prescaler_dummy     20'b0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t rtc_prescaler: 12;
+        uint32_t rtc_prescaler_dummy: 20;
+    } b;
+} RTC_PRESCALER0_TypeDef;
+
+
+
+/* 0x10
+   31:0    R/W    rtc_cmp0                32'b0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t rtc_cmp0: 32;
+    } b;
+} RTC_COMP_0_TypeDef;
+
+
+
+/* 0x14
+   31:0    R/W    rtc_cmp1                32'b0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t rtc_cmp1: 32;
+    } b;
+} RTC_COMP_1_TypeDef;
+
+
+
+/* 0x18
+   31:0    R/W    rtc_cmp2                32'b0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t rtc_cmp2: 32;
+    } b;
+} RTC_COMP_2_TypeDef;
+
+
+
+/* 0x1C
+   31:0    R/W    rtc_cmp3                32'b0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t rtc_cmp3: 32;
+    } b;
+} RTC_COMP_3_TypeDef;
+
+
+
+/* 0x20
+   31:0    R/W    rtc_cmp0gt              32'b0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t rtc_cmp0gt: 32;
+    } b;
+} RTC_COMP0_GT_TypeDef;
+
+
+
+/* 0x24
+   31:0    R/W    rtc_cmp1gt              32'b0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t rtc_cmp1gt: 32;
+    } b;
+} RTC_COMP1_GT_TypeDef;
+
+
+
+/* 0x28
+   31:0    R/W    rtc_cmp2gt              32'b0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t rtc_cmp2gt: 32;
+    } b;
+} RTC_COMP2_GT_TypeDef;
+
+
+
+/* 0x2C
+   31:0    R/W    rtc_cmp3gt              32'b0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t rtc_cmp3gt: 32;
+    } b;
+} RTC_COMP3_GT_TypeDef;
+
+
+
+/* 0x30
+   31:0    R      rtc_cnt                 32'b0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        const uint32_t rtc_cnt: 32;
+    } b;
+} RTC_CNT0_TypeDef;
+
+
+
+/* 0x34
+   11:0    R      rtc_prescale_cnt        12'b0
+   31:12   R/W    rtc_prescale_cnt_dummy  20'b0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        const uint32_t rtc_prescale_cnt: 12;
+        uint32_t rtc_prescale_cnt_dummy: 20;
+    } b;
+} RTC_PRESCALE_CNT0_TypeDef;
+
+
+
+/* 0x38
+   11:0    R/W    rtc_prescale_cmp        12'b0
+   31:12   R/W    rtc_prescale_cmp_dummy  20'b0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t rtc_prescale_cmp: 12;
+        uint32_t rtc_prescale_cmp_dummy: 20;
+    } b;
+} RTC_PRESCALE_CMP0_TypeDef;
+
+
+
+/* 0x3C
+   31:0    R/W    rtc_backup              32'b0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t rtc_backup: 32;
+    } b;
+} RTC_BACKUP_TypeDef;
+
+
+
+/* 0x40
+   31:0    R      rtc_rtl_version         32'h2112180A
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        const uint32_t rtc_rtl_version: 32;
+    } b;
+} RTC_RTL_VERSION0_TypeDef;
+
+
+/*============================================================================*
+ *                          RTC Constants
+ *============================================================================*/
+/** \defgroup RTC        RTC
+  * \brief
+  * \{
+  */
+
+/** \defgroup RTC_Exported_Constants RTC Exported Constants
+  * \brief
+  * \{
+  */
+
+/**
+ * \defgroup    RTC_IN_PAD_Select RTC IN PAD Select
+ * \{
+ * \ingroup     RTC_Exported_Constants
+ */
+typedef enum
+{
+    PAD_RTC_IN_DISABLE,  //!< Disable GPIO input of RTC.
+    PAD_32KXI_RTC_IN,    //!< Select PAD 32KXI.
+    PAD_P2_4_RTC_IN,     //!< Select PAD P2_4.
+    RTC_IN_SEL_DEFAULT = PAD_RTC_IN_DISABLE,    //!< Disable GPIO input of RTC.
+} RTCInSel_TypeDef;
+
+#define RTC_ALL_IN_SEL         (PAD_RTC_IN_DISABLE | PAD_32KXI_RTC_IN | \
+                                PAD_P2_4_RTC_IN | RTC_IN_SEL_DEFAULT) //!< Check if the input parameter is valid.
+
+/** End of RTC_IN_PAD_Select
+  * \}
+  */
+
+/** End of RTC_Exported_Constants
+  * \}
+  */
+
+/** End of RTC
+  * \}
+  */
+
+
+#ifdef  __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* RTL_RTC_DEF_H */
diff --git a/bee/drivers/rtc/src/device/rtl87x2j/CMakeLists.txt b/bee/drivers/rtc/src/device/rtl87x2j/CMakeLists.txt
new file mode 100644
index 00000000..c58501c6
--- /dev/null
+++ b/bee/drivers/rtc/src/device/rtl87x2j/CMakeLists.txt
@@ -0,0 +1,7 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_include_directories(${CMAKE_CURRENT_SOURCE_DIR})
+
+zephyr_library_sources_ifdef(CONFIG_REALTEK_BEE_RTC rtl87x2j_rtc.c)
+zephyr_library_sources_ifdef(CONFIG_REALTEK_BEE_GRTC rtl87x2j_grtc.c)
diff --git a/bee/drivers/rtc/src/device/rtl87x2j/rtl87x2j_grtc.c b/bee/drivers/rtc/src/device/rtl87x2j/rtl87x2j_grtc.c
new file mode 100644
index 00000000..75a9bbfb
--- /dev/null
+++ b/bee/drivers/rtc/src/device/rtl87x2j/rtl87x2j_grtc.c
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *                           Header Files
+ *============================================================================*/
+#include "rtl_grtc.h"
+
+/*============================================================================*
+ *                           Private Defines
+ *============================================================================*/
+#define GRTC_CLOCK_AUTO_MODE_CONFIG_ALWAYSRUN       (0x0F) // Force off 0x0A
+
+/*============================================================================*
+ *                           Public Functions
+ *============================================================================*/
+void GRTC_ClockAutoModeCmd(FunctionalState Newstate)
+{
+    if (Newstate == ENABLE)
+    {
+        GRTC->GRTC_QACTIVE_CTRL &= ~GRTC_CLOCK_AUTO_MODE_CONFIG_ALWAYSRUN;
+    }
+    else
+    {
+        GRTC->GRTC_QACTIVE_CTRL |= GRTC_CLOCK_AUTO_MODE_CONFIG_ALWAYSRUN;
+    }
+
+    return;
+}
+
+#if (GRTC_SUPPORT_RAP_FUNCTION == 1)
+bool GRTC_IsSupportRAPComp(GRTCCompIndex_TypeDef Index)
+{
+    return true;
+}
+#endif
+
+
diff --git a/bee/drivers/rtc/src/device/rtl87x2j/rtl87x2j_rtc.c b/bee/drivers/rtc/src/device/rtl87x2j/rtl87x2j_rtc.c
new file mode 100644
index 00000000..29c993c2
--- /dev/null
+++ b/bee/drivers/rtc/src/device/rtl87x2j/rtl87x2j_rtc.c
@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *                           Header Files
+ *============================================================================*/
+#include "rtl_rtc.h"
+#include "rtl_rcc.h"
+
+/*============================================================================*
+ *                           Private Defines
+ *============================================================================*/
+
+/*============================================================================*
+ *                           Public Functions
+ *============================================================================*/
+
+void RTC_ClockInCmd(RTCClockIn_TypeDef ClockIn, FunctionalState NewState)
+{
+    if (NewState)
+    {
+        /* Select which externel pad as rtc clock in */
+        AON_REG_WRITE_BITFIELD(AON_REG_PAD_VPON_REG1X, RTC_IN_SEL, ClockIn);
+    }
+
+    /* Select rtc clock in from external pad */
+    PCC_REG_WRITE_BITFIELD(PCC_REG_USER_RTC, R_RTC_GPIO_CLK_SRC_SEL, NewState);
+}
+
+void RTC_ClockOutCmd(RTCClockOut_TypeDef ClockOut, FunctionalState NewState)
+{
+    if (NewState)
+    {
+        if (ClockOut / 2)
+        {
+            AON_REG_WRITE_BITFIELD(AON_REG_PAD_VPON_REG1X, PIN_CLK_OUT_SEL_1, ClockOut % 2);
+            AON_REG_WRITE_BITFIELD(AON_REG_PAD_REG23X, PAD_P0_3_RTC_CLK_OUT_EN, ENABLE);
+        }
+        else
+        {
+            AON_REG_WRITE_BITFIELD(AON_REG_PAD_VPON_REG1X, PIN_CLK_OUT_SEL_0, ClockOut % 2);
+            AON_REG_WRITE_BITFIELD(AON_REG_PAD_REG23X, PAD_P0_1_RTC_CLK_OUT_EN, ENABLE);
+        }
+    }
+    else
+    {
+        if (ClockOut / 2)
+        {
+            AON_REG_WRITE_BITFIELD(AON_REG_PAD_REG23X, PAD_P0_3_RTC_CLK_OUT_EN, DISABLE);
+        }
+        else
+        {
+            AON_REG_WRITE_BITFIELD(AON_REG_PAD_REG23X, PAD_P0_1_RTC_CLK_OUT_EN, DISABLE);
+        }
+    }
+}
+
+/**
+  * \brief  Enable/Disable the RTC function of auto reload.
+  * \param  index: The comparator number,can be 0 ~ 3.
+  * \param  NewState: new state of RTC peripheral.
+  *         This parameter can be the following values:
+  *         \arg ENABLE: start RTC.
+  *         \arg DISABLE: stop RTC.
+  * \return None
+  */
+void RTC_CompAutoReloadCmd(RTCCompIndex_TypeDef index, FunctionalState NewState)
+{
+    RTC_RELOAD_CTRL_TypeDef rtc_0x34 = {.d32 = RTC->RTC_RELOAD_CTRL};
+
+    if (NewState == ENABLE)
+    {
+        rtc_0x34.d32 |= BIT(index);
+    }
+    else
+    {
+        rtc_0x34.d32 &= (~BIT(index));
+    }
+
+    RTC_WRITE(RTC_RELOAD_CTRL, rtc_0x34.d32);
+}
+
+
+
diff --git a/bee/drivers/rtc/src/device/rtl87x2j/rtl_grtc_def.h b/bee/drivers/rtc/src/device/rtl87x2j/rtl_grtc_def.h
new file mode 100644
index 00000000..9b8fdf50
--- /dev/null
+++ b/bee/drivers/rtc/src/device/rtl87x2j/rtl_grtc_def.h
@@ -0,0 +1,720 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef RTL_GRTC_DEF_H
+#define RTL_GRTC_DEF_H
+
+#include "utils/rtl_utils.h"
+#include "address_map.h"
+#include "aon_reg.h"
+#include "utils.h"
+
+#ifdef  __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/*============================================================================*
+ *                          GRTC Defines
+ *============================================================================*/
+#define GRTC_COMP_NUM                         (8)
+
+#define GRTC_SUPPORT_RAP_FUNCTION             (1)
+#define GRTC_SUPPORT_FORCE_QACTIVE            (1)
+#define GRTC_SUPPORT_ERROR_INTERRUPT          (1)
+
+/*============================================================================*
+ *                          GRTC Registers Memory Map
+ *============================================================================*/
+typedef struct
+{
+    __IO uint32_t GRTC_CTRL;                                /*!< 0x00 */
+    __IO uint32_t GRTC_INTR_CTRL;                           /*!< 0x04 */
+    __I  uint32_t GRTC_COMP_INTR_SR;                        /*!< 0x08 */
+    __IO uint32_t GRTC_COMP_INT_CLR;                        /*!< 0x0C */
+    __IO uint32_t GRTC_COMP_0;                              /*!< 0x10 */
+    __IO uint32_t GRTC_COMP_1;                              /*!< 0x14 */
+    __IO uint32_t GRTC_COMP_2;                              /*!< 0x18 */
+    __IO uint32_t GRTC_COMP_3;                              /*!< 0x1C */
+    __IO uint32_t GRTC_COMP_4;                              /*!< 0x20 */
+    __IO uint32_t GRTC_COMP_5;                              /*!< 0x24 */
+    __IO uint32_t GRTC_COMP_6;                              /*!< 0x28 */
+    __IO uint32_t GRTC_COMP_7;                              /*!< 0x2C */
+    __IO uint32_t GRTC_RELOAD_CTRL;                         /*!< 0x30 */
+    __IO uint32_t GRTC_COMP_0_RELOAD;                       /*!< 0x34 */
+    __IO uint32_t GRTC_COMP_1_RELOAD;                       /*!< 0x38 */
+    __IO uint32_t GRTC_COMP_2_RELOAD;                       /*!< 0x3C */
+    __IO uint32_t GRTC_COMP_3_RELOAD;                       /*!< 0x40 */
+    __IO uint32_t GRTC_COMP_4_RELOAD;                       /*!< 0x44 */
+    __IO uint32_t GRTC_COMP_5_RELOAD;                       /*!< 0x48 */
+    __IO uint32_t GRTC_COMP_6_RELOAD;                       /*!< 0x4C */
+    __IO uint32_t GRTC_COMP_7_RELOAD;                       /*!< 0x50 */
+    __IO uint32_t GRTC_SLEEP_CTRL;                          /*!< 0x54 */
+    __I  uint32_t GRTC_COMP_0_SLEEP_PENDING_CNT;            /*!< 0x58 */
+    __I  uint32_t GRTC_COMP_1_SLEEP_PENDING_CNT;            /*!< 0x5C */
+    __I  uint32_t GRTC_COMP_2_SLEEP_PENDING_CNT;            /*!< 0x60 */
+    __I  uint32_t GRTC_COMP_3_SLEEP_PENDING_CNT;            /*!< 0x64 */
+    __I  uint32_t GRTC_COMP_4_SLEEP_PENDING_CNT;            /*!< 0x68 */
+    __I  uint32_t GRTC_COMP_5_SLEEP_PENDING_CNT;            /*!< 0x6C */
+    __I  uint32_t GRTC_COMP_6_SLEEP_PENDING_CNT;            /*!< 0x70 */
+    __I  uint32_t GRTC_COMP_7_SLEEP_PENDING_CNT;            /*!< 0x74 */
+    __IO uint32_t GRTC_TASK_CTRL;                           /*!< 0x78 */
+    __IO uint32_t GRTC_QACTIVE_CTRL;                        /*!< 0x7C */
+    __I  uint32_t GRTC_RTL_VERSION;                         /*!< 0x80 */
+    __IO uint32_t GRTC_COMP_TIMEOUT_OV_ERR_SR;              /*!< 0x84 */
+    __IO uint32_t GRTC_COMP_TIMEOUT_OV_ERR_CLR;             /*!< 0x88 */
+} GRTC_TypeDef;
+
+/*============================================================================*
+ *                          GRTC Declaration
+ *============================================================================*/
+#define GRTC_REG_BASE       (SYSON_BASE + AON_REG_GRTC_CTRL)
+#define GRTC                ((GRTC_TypeDef *) GRTC_REG_BASE)
+
+/*============================================================================*
+ *                          GRTC Private Types
+ *============================================================================*/
+
+/*============================================================================*
+ *                          GRTC Registers and Field Descriptions
+ *============================================================================*/
+/* 0x00
+   30:0    R      grtc_ctrl_reserved30_0                      31'b0
+   31      R/W    grtc_rst                                    1'b0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t grtc_ctrl_reserved30_0: 31;
+        uint32_t grtc_rst: 1;
+    } b;
+} GRTC_CTRL_TypeDef;
+
+
+/* 0x04
+   0       R/W    grtc_cmp0_nv_ie                             1'b0
+   1       R/W    grtc_cmp1_nv_ie                             1'b0
+   2       R/W    grtc_cmp2_nv_ie                             1'b0
+   3       R/W    grtc_cmp3_nv_ie                             1'b0
+   4       R/W    grtc_cmp4_nv_ie                             1'b0
+   5       R/W    grtc_cmp5_nv_ie                             1'b0
+   6       R/W    grtc_cmp6_nv_ie                             1'b0
+   7       R/W    grtc_cmp7_nv_ie                             1'b0
+   31:8    R      grtc_intr_ctrl_reserved31_8                 24'b0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t grtc_cmp0_nv_ie: 1;
+        uint32_t grtc_cmp1_nv_ie: 1;
+        uint32_t grtc_cmp2_nv_ie: 1;
+        uint32_t grtc_cmp3_nv_ie: 1;
+        uint32_t grtc_cmp4_nv_ie: 1;
+        uint32_t grtc_cmp5_nv_ie: 1;
+        uint32_t grtc_cmp6_nv_ie: 1;
+        uint32_t grtc_cmp7_nv_ie: 1;
+        const uint32_t grtc_intr_ctrl_reserved31_8: 24;
+    } b;
+} GRTC_INTR_CTRL_TypeDef;
+
+
+/* 0x08
+   0       R      grtc_cmp0_nv_sr                             1'b0
+   1       R      grtc_cmp1_nv_sr                             1'b0
+   2       R      grtc_cmp2_nv_sr                             1'b0
+   3       R      grtc_cmp3_nv_sr                             1'b0
+   4       R      grtc_cmp4_nv_sr                             1'b0
+   5       R      grtc_cmp5_nv_sr                             1'b0
+   6       R      grtc_cmp6_nv_sr                             1'b0
+   7       R      grtc_cmp7_nv_sr                             1'b0
+   31:8    R      grtc_comp_intr_sr_reserved31_8              24'b0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t grtc_cmp0_nv_sr: 1;
+        const uint32_t grtc_cmp1_nv_sr: 1;
+        const uint32_t grtc_cmp2_nv_sr: 1;
+        const uint32_t grtc_cmp3_nv_sr: 1;
+        const uint32_t grtc_cmp4_nv_sr: 1;
+        const uint32_t grtc_cmp5_nv_sr: 1;
+        const uint32_t grtc_cmp6_nv_sr: 1;
+        const uint32_t grtc_cmp7_nv_sr: 1;
+        const uint32_t grtc_comp_intr_sr_reserved31_8: 24;
+    } b;
+} GRTC_COMP_INTR_SR_TypeDef;
+
+
+/* 0x0C
+   0       R/WAC  grtc_cmp0_nv_clr                            1'b0
+   1       R/WAC  grtc_cmp1_nv_clr                            1'b0
+   2       R/WAC  grtc_cmp2_nv_clr                            1'b0
+   3       R/WAC  grtc_cmp3_nv_clr                            1'b0
+   4       R/WAC  grtc_cmp4_nv_clr                            1'b0
+   5       R/WAC  grtc_cmp5_nv_clr                            1'b0
+   6       R/WAC  grtc_cmp6_nv_clr                            1'b0
+   7       R/WAC  grtc_cmp7_nv_clr                            1'b0
+   31:8    R      grtc_comp_intr_clr_reserved31_8             24'b0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t grtc_cmp0_nv_clr: 1;
+        uint32_t grtc_cmp1_nv_clr: 1;
+        uint32_t grtc_cmp2_nv_clr: 1;
+        uint32_t grtc_cmp3_nv_clr: 1;
+        uint32_t grtc_cmp4_nv_clr: 1;
+        uint32_t grtc_cmp5_nv_clr: 1;
+        uint32_t grtc_cmp6_nv_clr: 1;
+        uint32_t grtc_cmp7_nv_clr: 1;
+        const uint32_t grtc_comp_intr_clr_reserved31_8: 24;
+    } b;
+} GRTC_COMP_INT_CLR_TypeDef;
+
+
+/* 0x10
+   31:0    R/W    grtc_cmp0                                   32'b0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t grtc_cmp0: 32;
+    } b;
+} GRTC_COMP_0_TypeDef;
+
+
+/* 0x14
+   31:0    R/W    grtc_cmp1                                   32'b0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t grtc_cmp1: 32;
+    } b;
+} GRTC_COMP_1_TypeDef;
+
+
+/* 0x18
+   31:0    R/W    grtc_cmp2                                   32'b0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t grtc_cmp2: 32;
+    } b;
+} GRTC_COMP_2_TypeDef;
+
+
+/* 0x1C
+   31:0    R/W    grtc_cmp3                                   32'b0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t grtc_cmp3: 32;
+    } b;
+} GRTC_COMP_3_TypeDef;
+
+
+/* 0x20
+   31:0    R/W    grtc_cmp4                                   32'b0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t grtc_cmp4: 32;
+    } b;
+} GRTC_COMP_4_TypeDef;
+
+
+/* 0x24
+   31:0    R/W    grtc_cmp5                                   32'b0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t grtc_cmp5: 32;
+    } b;
+} GRTC_COMP_5_TypeDef;
+
+
+/* 0x28
+   31:0    R/W    grtc_cmp6                                   32'b0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t grtc_cmp6: 32;
+    } b;
+} GRTC_COMP_6_TypeDef;
+
+
+/* 0x2C
+   31:0    R/W    grtc_cmp7                                   32'b0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t grtc_cmp7: 32;
+    } b;
+} GRTC_COMP_7_TypeDef;
+
+
+/* 0x30
+   0       R/W    grtc_cmp0_reload_en                         1'h0
+   1       R/W    grtc_cmp1_reload_en                         1'b0
+   2       R/W    grtc_cmp2_reload_en                         1'b0
+   3       R/W    grtc_cmp3_reload_en                         1'b0
+   4       R/W    grtc_cmp4_reload_en                         1'b0
+   5       R/W    grtc_cmp5_reload_en                         1'b0
+   6       R/W    grtc_cmp6_reload_en                         1'b0
+   7       R/W    grtc_cmp7_reload_en                         1'b0
+   31:8    R      grtc_comp_reload_ctrl_reserved31_8          24'b0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t grtc_cmp0_reload_en: 1;
+        uint32_t grtc_cmp1_reload_en: 1;
+        uint32_t grtc_cmp2_reload_en: 1;
+        uint32_t grtc_cmp3_reload_en: 1;
+        uint32_t grtc_cmp4_reload_en: 1;
+        uint32_t grtc_cmp5_reload_en: 1;
+        uint32_t grtc_cmp6_reload_en: 1;
+        uint32_t grtc_cmp7_reload_en: 1;
+        const uint32_t grtc_comp_reload_ctrl_reserved31_8: 24;
+    } b;
+} GRTC_RELOAD_CTRL_TypeDef;
+
+
+/* 0x34
+   31:0    R/W    grtc_cmp0_reload                            32'b0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t grtc_cmp0_reload: 32;
+    } b;
+} GRTC_COMP_0_RELOAD_TypeDef;
+
+
+/* 0x38
+   31:0    R/W    grtc_cmp1_reload                            32'b0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t grtc_cmp1_reload: 32;
+    } b;
+} GRTC_COMP_1_RELOAD_TypeDef;
+
+
+/* 0x3C
+   31:0    R/W    grtc_cmp2_reload                            32'b0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t grtc_cmp2_reload: 32;
+    } b;
+} GRTC_COMP_2_RELOAD_TypeDef;
+
+
+/* 0x40
+   31:0    R/W    grtc_cmp3_reload                            32'b0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t grtc_cmp3_reload: 32;
+    } b;
+} GRTC_COMP_3_RELOAD_TypeDef;
+
+
+/* 0x44
+   31:0    R/W    grtc_cmp4_reload                            32'b0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t grtc_cmp4_reload: 32;
+    } b;
+} GRTC_COMP_4_RELOAD_TypeDef;
+
+
+/* 0x48
+   31:0    R/W    grtc_cmp5_reload                            32'b0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t grtc_cmp5_reload: 32;
+    } b;
+} GRTC_COMP_5_RELOAD_TypeDef;
+
+
+/* 0x4C
+   31:0    R/W    grtc_cmp6_reload                            32'b0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t grtc_cmp6_reload: 32;
+    } b;
+} GRTC_COMP_6_RELOAD_TypeDef;
+
+
+/* 0x50
+   31:0    R/W    grtc_cmp7_reload                            32'b0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t grtc_cmp7_reload: 32;
+    } b;
+} GRTC_COMP_7_RELOAD_TypeDef;
+
+
+/* 0x54
+   0       R/W    grtc_cmp0_sleep_ctrl                        1'h0
+   1       R/W    grtc_cmp1_sleep_ctrl                        1'b0
+   2       R/W    grtc_cmp2_sleep_ctrl                        1'b0
+   3       R/W    grtc_cmp3_sleep_ctrl                        1'b0
+   4       R/W    grtc_cmp4_sleep_ctrl                        1'b0
+   5       R/W    grtc_cmp5_sleep_ctrl                        1'b0
+   6       R/W    grtc_cmp6_sleep_ctrl                        1'b0
+   7       R/W    grtc_cmp7_sleep_ctrl                        1'b0
+   31:8    R      grtc_sleep_ctrl_reserved31_8                24'b0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t grtc_cmp0_sleep_ctrl: 1;
+        uint32_t grtc_cmp1_sleep_ctrl: 1;
+        uint32_t grtc_cmp2_sleep_ctrl: 1;
+        uint32_t grtc_cmp3_sleep_ctrl: 1;
+        uint32_t grtc_cmp4_sleep_ctrl: 1;
+        uint32_t grtc_cmp5_sleep_ctrl: 1;
+        uint32_t grtc_cmp6_sleep_ctrl: 1;
+        uint32_t grtc_cmp7_sleep_ctrl: 1;
+        const uint32_t grtc_sleep_ctrl_reserved31_8: 24;
+    } b;
+} GRTC_SLEEP_CTRL_TypeDef;
+
+
+/* 0x58
+   31:0    R      grtc_cmp0_sleep_pending_cnt                 32'b0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t grtc_cmp0_sleep_pending_cnt: 32;
+    } b;
+} GRTC_COMP_0_SLEEP_PENDING_CNT_TypeDef;
+
+
+/* 0x5C
+   31:0    R      grtc_cmp1_sleep_pending_cnt                 32'b0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t grtc_cmp1_sleep_pending_cnt: 32;
+    } b;
+} GRTC_COMP_1_SLEEP_PENDING_CNT_TypeDef;
+
+
+/* 0x60
+   31:0    R      grtc_cmp2_sleep_pending_cnt                 32'b0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t grtc_cmp2_sleep_pending_cnt: 32;
+    } b;
+} GRTC_COMP_2_SLEEP_PENDING_CNT_TypeDef;
+
+
+/* 0x64
+   31:0    R      grtc_cmp3_sleep_pending_cnt                 32'b0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t grtc_cmp3_sleep_pending_cnt: 32;
+    } b;
+} GRTC_COMP_3_SLEEP_PENDING_CNT_TypeDef;
+
+
+/* 0x68
+   31:0    R      grtc_cmp4_sleep_pending_cnt                 32'b0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t grtc_cmp4_sleep_pending_cnt: 32;
+    } b;
+} GRTC_COMP_4_SLEEP_PENDING_CNT_TypeDef;
+
+
+/* 0x6C
+   31:0    R      grtc_cmp5_sleep_pending_cnt                 32'b0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t grtc_cmp5_sleep_pending_cnt: 32;
+    } b;
+} GRTC_COMP_5_SLEEP_PENDING_CNT_TypeDef;
+
+
+/* 0x70
+   31:0    R      grtc_cmp6_sleep_pending_cnt                 32'b0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t grtc_cmp6_sleep_pending_cnt: 32;
+    } b;
+} GRTC_COMP_6_SLEEP_PENDING_CNT_TypeDef;
+
+
+/* 0x74
+   31:0    R      grtc_cmp7_sleep_pending_cnt                 32'b0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t grtc_cmp7_sleep_pending_cnt: 32;
+    } b;
+} GRTC_COMP_7_SLEEP_PENDING_CNT_TypeDef;
+
+
+/* 0x78
+   0       R/W    grtc_cmp0_rap_mode                          1'h0
+   1       R/W    grtc_cmp1_rap_mode                          1'h0
+   2       R/W    grtc_cmp2_rap_mode                          1'h0
+   3       R/W    grtc_cmp3_rap_mode                          1'h0
+   4       R/W    grtc_cmp4_rap_mode                          1'h0
+   5       R/W    grtc_cmp5_rap_mode                          1'h0
+   6       R/W    grtc_cmp6_rap_mode                          1'h0
+   7       R/W    grtc_cmp7_rap_mode                          1'h0
+   8       R/WAC  grtc_fw_task_reload_cmp0                    1'h0
+   9       R/WAC  grtc_fw_task_reload_cmp1                    1'b0
+   10      R/WAC  grtc_fw_task_reload_cmp2                    1'b0
+   11      R/WAC  grtc_fw_task_reload_cmp3                    1'b0
+   12      R/WAC  grtc_fw_task_reload_cmp4                    1'b0
+   13      R/WAC  grtc_fw_task_reload_cmp5                    1'b0
+   14      R/WAC  grtc_fw_task_reload_cmp6                    1'b0
+   15      R/WAC  grtc_fw_task_reload_cmp7                    1'b0
+   31:16   R      grtc_task_ctrl_reserved31_16                16'b0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t grtc_cmp0_rap_mode: 1;
+        uint32_t grtc_cmp1_rap_mode: 1;
+        uint32_t grtc_cmp2_rap_mode: 1;
+        uint32_t grtc_cmp3_rap_mode: 1;
+        uint32_t grtc_cmp4_rap_mode: 1;
+        uint32_t grtc_cmp5_rap_mode: 1;
+        uint32_t grtc_cmp6_rap_mode: 1;
+        uint32_t grtc_cmp7_rap_mode: 1;
+        uint32_t grtc_fw_task_reload_cmp0: 1;
+        uint32_t grtc_fw_task_reload_cmp1: 1;
+        uint32_t grtc_fw_task_reload_cmp2: 1;
+        uint32_t grtc_fw_task_reload_cmp3: 1;
+        uint32_t grtc_fw_task_reload_cmp4: 1;
+        uint32_t grtc_fw_task_reload_cmp5: 1;
+        uint32_t grtc_fw_task_reload_cmp6: 1;
+        uint32_t grtc_fw_task_reload_cmp7: 1;
+        const uint32_t grtc_task_ctrl_reserved31_16: 16;
+    } b;
+} GRTC_TASK_CTRL_TypeDef;
+
+
+/* 0x7C
+   0       R/W    grtc_qact_sclk_man_data                     1'h0
+   1       R/W    grtc_qact_sclk_man_en                       1'h0
+   2       R/W    grtc_qact_pclk_man_data                     1'h0
+   3       R/W    grtc_qact_pclk_man_en                       1'h0
+   7:4     R      grtc_intr_clr_reserved7_4                   4'b0
+   8       R/W    grtc_cmp0_force_qact_en                     1'h0
+   9       R/W    grtc_cmp1_force_qact_en                     1'h0
+   10      R/W    grtc_cmp2_force_qact_en                     1'h0
+   11      R/W    grtc_cmp3_force_qact_en                     1'h0
+   12      R/W    grtc_cmp4_force_qact_en                     1'h0
+   13      R/W    grtc_cmp5_force_qact_en                     1'h0
+   14      R/W    grtc_cmp6_force_qact_en                     1'h0
+   15      R/W    grtc_cmp7_force_qact_en                     1'h0
+   31:16   R      grtc_intr_clr_reserved31_16                 16'b0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t grtc_qact_sclk_man_data: 1;
+        uint32_t grtc_qact_sclk_man_en: 1;
+        uint32_t grtc_qact_pclk_man_data: 1;
+        uint32_t grtc_qact_pclk_man_en: 1;
+        const uint32_t grtc_intr_clr_reserved7_4: 4;
+        uint32_t grtc_cmp0_force_qact_en: 1;
+        uint32_t grtc_cmp1_force_qact_en: 1;
+        uint32_t grtc_cmp2_force_qact_en: 1;
+        uint32_t grtc_cmp3_force_qact_en: 1;
+        uint32_t grtc_cmp4_force_qact_en: 1;
+        uint32_t grtc_cmp5_force_qact_en: 1;
+        uint32_t grtc_cmp6_force_qact_en: 1;
+        uint32_t grtc_cmp7_force_qact_en: 1;
+        const uint32_t grtc_intr_clr_reserved31_16: 16;
+    } b;
+} GRTC_QACTIVE_CTRL_TypeDef;
+
+
+/* 0x80
+   31:0    R      grtc_rtl_version                            32'h20240930
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t grtc_rtl_version: 32;
+    } b;
+} GRTC_RTL_VERSION_TypeDef;
+
+
+/* 0x84
+   0       R      grtc_cmp0_timeout_ov_err_sr                 1'b0
+   1       R      grtc_cmp1_timeout_ov_err_sr                 1'b0
+   2       R      grtc_cmp2_timeout_ov_err_sr                 1'b0
+   3       R      grtc_cmp3_timeout_ov_err_sr                 1'b0
+   4       R      grtc_cmp4_timeout_ov_err_sr                 1'b0
+   5       R      grtc_cmp5_timeout_ov_err_sr                 1'b0
+   6       R      grtc_cmp6_timeout_ov_err_sr                 1'b0
+   7       R      grtc_cmp7_timeout_ov_err_sr                 1'b0
+   31:8    R      grtc_comp_timeout_ov_err_sr_reserved31_8    24'b0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t grtc_cmp0_timeout_ov_err_sr: 1;
+        const uint32_t grtc_cmp1_timeout_ov_err_sr: 1;
+        const uint32_t grtc_cmp2_timeout_ov_err_sr: 1;
+        const uint32_t grtc_cmp3_timeout_ov_err_sr: 1;
+        const uint32_t grtc_cmp4_timeout_ov_err_sr: 1;
+        const uint32_t grtc_cmp5_timeout_ov_err_sr: 1;
+        const uint32_t grtc_cmp6_timeout_ov_err_sr: 1;
+        const uint32_t grtc_cmp7_timeout_ov_err_sr: 1;
+        const uint32_t grtc_comp_timeout_ov_err_sr_reserved31_8: 24;
+    } b;
+} GRTC_COMP_TIMEOUT_OV_ERR_SR_TypeDef;
+
+
+/* 0x88
+   0       R/WAC  grtc_cmp0_timeout_ov_err_clr                1'b0
+   1       R/WAC  grtc_cmp1_timeout_ov_err_clr                1'b0
+   2       R/WAC  grtc_cmp2_timeout_ov_err_clr                1'b0
+   3       R/WAC  grtc_cmp3_timeout_ov_err_clr                1'b0
+   4       R/WAC  grtc_cmp4_timeout_ov_err_clr                1'b0
+   5       R/WAC  grtc_cmp5_timeout_ov_err_clr                1'b0
+   6       R/WAC  grtc_cmp6_timeout_ov_err_clr                1'b0
+   7       R/WAC  grtc_cmp7_timeout_ov_err_clr                1'b0
+   31:8    R      grtc_comp_timeout_ov_err_clr_reserved31_8   24'b0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t grtc_cmp0_timeout_ov_err_clr: 1;
+        uint32_t grtc_cmp1_timeout_ov_err_clr: 1;
+        uint32_t grtc_cmp2_timeout_ov_err_clr: 1;
+        uint32_t grtc_cmp3_timeout_ov_err_clr: 1;
+        uint32_t grtc_cmp4_timeout_ov_err_clr: 1;
+        uint32_t grtc_cmp5_timeout_ov_err_clr: 1;
+        uint32_t grtc_cmp6_timeout_ov_err_clr: 1;
+        uint32_t grtc_cmp7_timeout_ov_err_clr: 1;
+        const uint32_t grtc_comp_timeout_ov_err_clr_reserved31_8: 24;
+    } b;
+} GRTC_COMP_TIMEOUT_OV_ERR_CLR_TypeDef;
+
+
+
+/*============================================================================*
+ *                         GRTC Wrappers
+ *============================================================================*/
+
+
+#ifdef  __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* RTL_GRTC_DEF_H */
diff --git a/bee/drivers/rtc/src/device/rtl87x2j/rtl_rtc_def.h b/bee/drivers/rtc/src/device/rtl87x2j/rtl_rtc_def.h
new file mode 100644
index 00000000..c9d69846
--- /dev/null
+++ b/bee/drivers/rtc/src/device/rtl87x2j/rtl_rtc_def.h
@@ -0,0 +1,611 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef RTL_RTC_DEF_H
+#define RTL_RTC_DEF_H
+
+#include "utils/rtl_utils.h"
+#include "address_map.h"
+#include "aon_reg.h"
+#include "utils.h"
+
+#ifdef  __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+
+/*============================================================================*
+ *                          RTC Defines
+ *============================================================================*/
+/** \defgroup RTC         RTC
+  * \brief
+  * \{
+  */
+
+/** \defgroup RTC_Exported_Constants RTC Exported Constants
+  * \brief
+  * \{
+  */
+
+/**
+ * \defgroup RTC_Defines RTC Defines
+ * \{
+ * \ingroup  RTC_Exported_Constants
+ */
+#define RTC_SUPPORT_CLOCK_IN_FROM_OUTSIDE_PAD          (1)
+#define RTC_SUPPORT_CLOCK_OUT_TO_OUTSIDE_PAD           (0)
+#define RTC_SUPPORT_WAKEUP_MORE_SOURCE                 (1) /*Support TICK OVERFLOW PRECOMP PRECOMP_COMP3*/
+#define RTC_SUPPORT_WAKEUP_COMPARE_GUARDTIME           (0)
+#define RTC_SUPPORT_COMPARE_AUTO_RELOAD                (1)
+#define RTC_SUPPORT_RAP_FUNCTION                       (1)
+#define RTC_SUPPORT_RESET_REGISTER_TO_DEFAULT          (1)
+
+/** End of RTC_Defines
+  * \}
+  */
+
+/** End of RTC_Exported_Constants
+  * \}
+  */
+
+/** End of RTC
+  * \}
+  */
+
+/*============================================================================*
+ *                          RTC Registers Memory Map
+ *============================================================================*/
+typedef struct
+{
+    __IO uint32_t RTC_CR0;                  /*!< 0x00 */
+    __IO uint32_t RTC_INT_CLEAR;            /*!< 0x04 */
+    __IO uint32_t RTC_INT_SR;               /*!< 0x08 */
+    __IO uint32_t RTC_PRESCALER0;           /*!< 0x0C */
+    __IO uint32_t RTC_COMP_0;               /*!< 0x10 */
+    __IO uint32_t RTC_COMP_1;               /*!< 0x14 */
+    __IO uint32_t RTC_COMP_2;               /*!< 0x18 */
+    __IO uint32_t RTC_COMP_3;               /*!< 0x1C */
+    __I  uint32_t RTC_CNT0;                 /*!< 0x20 */
+    __IO uint32_t RTC_PRESCALE_CNT0;        /*!< 0x24 */
+    __IO uint32_t RTC_PRESCALE_CMP0;        /*!< 0x28 */
+    __IO uint32_t RTC_BACKUP;               /*!< 0x2C */
+    __I  uint32_t RTC_RTL_VERSION0;         /*!< 0x30 */
+    __IO uint32_t RTC_RELOAD_CTRL;          /*!< 0x34 */
+    __IO uint32_t RTC_COMP_0_RELOAD;        /*!< 0x38 */
+    __IO uint32_t RTC_COMP_1_RELOAD;        /*!< 0x3C */
+    __IO uint32_t RTC_COMP_2_RELOAD;        /*!< 0x40 */
+    __IO uint32_t RTC_COMP_3_RELOAD;        /*!< 0x44 */
+    __IO uint32_t RTC_TASK_CTRL;            /*!< 0x48 */
+    __IO uint32_t RTC_SHOT_CTRL;            /*!< 0x4C */
+    __IO uint32_t RTC_QACTIVE_CTRL;         /*!< 0x50 */
+} RTC_TypeDef;
+
+/*============================================================================*
+ *                          RTC Declaration
+ *============================================================================*/
+#define RTC_REG_BASE       (SYSON_BASE + AON_REG_RTC_CR0)
+#define RTC                ((RTC_TypeDef *) RTC_REG_BASE)
+
+/*============================================================================*
+ *                          RTC Registers and Field Descriptions
+ *============================================================================*/
+/* 0x00
+   0       R/W    rtc_cnt_start                   1'b0
+   1       R/W    rtc_cnt_rst                     1'b0
+   2       R/W    rtc_pre_cnt_rst                 1'b0
+   7:3     R      rtc_cr0_reserved7_3             5'b0
+   8       R/W    rtc_tick_ie                     1'b0
+   9       R/W    rtc_cnt_ov_ie                   1'b0
+   10      R/W    rtc_precmp_ie                   1'b0
+   11      R/W    rtc_precmp_cmp3_ie              1'b0
+   15:12   R      rtc_cr0_reserved15_12           4'h0
+   16      R/W    rtc_cmp0_nv_ie                  1'b0
+   17      R/W    rtc_cmp1_nv_ie                  1'b0
+   18      R/W    rtc_cmp2_nv_ie                  1'b0
+   19      R/W    rtc_cmp3_nv_ie                  1'b0
+   20      R/W    rtc_cmp0_wk_ie                  1'b0
+   21      R/W    rtc_cmp1_wk_ie                  1'b0
+   22      R/W    rtc_cmp2_wk_ie                  1'b0
+   23      R/W    rtc_cmp3_wk_ie                  1'b0
+   28:24   R      rtc_cr0_reserved28_24           5'b0
+   29      R/W    rtc_wk_ie                       1'b0
+   30      R/W    rtc_nv_ie                       1'b0
+   31      R/W    rtc_rst                         1'b0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t rtc_cnt_start: 1;
+        uint32_t rtc_cnt_rst: 1;
+        uint32_t rtc_pre_cnt_rst: 1;
+        const uint32_t rtc_cr0_reserved7_3: 5;
+        uint32_t rtc_tick_ie: 1;
+        uint32_t rtc_cnt_ov_ie: 1;
+        uint32_t rtc_precmp_ie: 1;
+        uint32_t rtc_precmp_cmp3_ie: 1;
+        const uint32_t rtc_cr0_reserved15_12: 4;
+        uint32_t rtc_cmp0_nv_ie: 1;
+        uint32_t rtc_cmp1_nv_ie: 1;
+        uint32_t rtc_cmp2_nv_ie: 1;
+        uint32_t rtc_cmp3_nv_ie: 1;
+        uint32_t rtc_cmp0_wk_ie: 1;
+        uint32_t rtc_cmp1_wk_ie: 1;
+        uint32_t rtc_cmp2_wk_ie: 1;
+        uint32_t rtc_cmp3_wk_ie: 1;
+        const uint32_t rtc_cr0_reserved28_24: 5;
+        uint32_t rtc_wk_ie: 1;
+        uint32_t rtc_nv_ie: 1;
+        uint32_t rtc_rst: 1;
+    } b;
+} RTC_CR0_TypeDef;
+
+
+/* 0x04
+   0       R/WAC  rtc_tick_clr                    1'b0
+   1       R/WAC  rtc_cnt_ov_clr                  1'b0
+   2       R/WAC  rtc_precmp_clr                  1'b0
+   3       R/WAC  rtc_precmp_cmp3_clr             1'b0
+   7:4     R      rtc_int_clear_reserved7_4       4'h0
+   8       R/WAC  rtc_cmp0_nv_clr                 1'b0
+   9       R/WAC  rtc_cmp1_nv_clr                 1'b0
+   10      R/WAC  rtc_cmp2_nv_clr                 1'b0
+   11      R/WAC  rtc_cmp3_nv_clr                 1'b0
+   12      R/WAC  rtc_cmp0_wk_clr                 1'b0
+   13      R/WAC  rtc_cmp1_wk_clr                 1'b0
+   14      R/WAC  rtc_cmp2_wk_clr                 1'b0
+   15      R/WAC  rtc_cmp3_wk_clr                 1'b0
+   31:16   R      rtc_int_clear_reserved31_16     16'b0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t rtc_tick_clr: 1;
+        uint32_t rtc_cnt_ov_clr: 1;
+        uint32_t rtc_precmp_clr: 1;
+        uint32_t rtc_precmp_cmp3_clr: 1;
+        const uint32_t rtc_int_clear_reserved7_4: 4;
+        uint32_t rtc_cmp0_nv_clr: 1;
+        uint32_t rtc_cmp1_nv_clr: 1;
+        uint32_t rtc_cmp2_nv_clr: 1;
+        uint32_t rtc_cmp3_nv_clr: 1;
+        uint32_t rtc_cmp0_wk_clr: 1;
+        uint32_t rtc_cmp1_wk_clr: 1;
+        uint32_t rtc_cmp2_wk_clr: 1;
+        uint32_t rtc_cmp3_wk_clr: 1;
+        const uint32_t rtc_int_clear_reserved31_16: 16;
+    } b;
+} RTC_INT_CLEAR_TypeDef;
+
+
+/* 0x08
+   0       R      rtc_tick_sr                     1'b0
+   1       R      rtc_cnt_ov_sr                   1'b0
+   2       R      rtc_precmp_sr                   1'b0
+   3       R      rtc_precmp_cmp3_sr              1'b0
+   7:4     R      rtc_int_sr_reserved7_4          4'h0
+   8       R      rtc_cmp0_nv_sr                  1'b0
+   9       R      rtc_cmp1_nv_sr                  1'b0
+   10      R      rtc_cmp2_nv_sr                  1'b0
+   11      R      rtc_cmp3_nv_sr                  1'b0
+   12      R      rtc_cmp0_wk_sr                  1'b0
+   13      R      rtc_cmp1_wk_sr                  1'b0
+   14      R      rtc_cmp2_wk_sr                  1'b0
+   15      R      rtc_cmp3_wk_sr                  1'b0
+   31:16   R      rtc_int_sr_reserved31_16        16'b0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t rtc_tick_sr: 1;
+        const uint32_t rtc_cnt_ov_sr: 1;
+        const uint32_t rtc_precmp_sr: 1;
+        const uint32_t rtc_precmp_cmp3_sr: 1;
+        const uint32_t rtc_int_sr_reserved7_4: 4;
+        const uint32_t rtc_cmp0_nv_sr: 1;
+        const uint32_t rtc_cmp1_nv_sr: 1;
+        const uint32_t rtc_cmp2_nv_sr: 1;
+        const uint32_t rtc_cmp3_nv_sr: 1;
+        const uint32_t rtc_cmp0_wk_sr: 1;
+        const uint32_t rtc_cmp1_wk_sr: 1;
+        const uint32_t rtc_cmp2_wk_sr: 1;
+        const uint32_t rtc_cmp3_wk_sr: 1;
+        const uint32_t rtc_int_sr_reserved31_16: 16;
+    } b;
+} RTC_INT_SR_TypeDef;
+
+
+/* 0x0C
+   11:0    R/W    rtc_prescaler                   12'b0
+   31:12   R      rtc_prescaler_reserved31_12     20'b0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t rtc_prescaler: 12;
+        const uint32_t rtc_prescaler_reserved31_12: 20;
+    } b;
+} RTC_PRESCALER0_TypeDef;
+
+
+/* 0x10
+   31:0    R/W    rtc_cmp0                        32'b0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t rtc_cmp0: 32;
+    } b;
+} RTC_COMP_0_TypeDef;
+
+
+/* 0x14
+   31:0    R/W    rtc_cmp1                        32'b0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t rtc_cmp1: 32;
+    } b;
+} RTC_COMP_1_TypeDef;
+
+
+/* 0x18
+   31:0    R/W    rtc_cmp2                        32'b0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t rtc_cmp2: 32;
+    } b;
+} RTC_COMP_2_TypeDef;
+
+
+/* 0x1C
+   31:0    R/W    rtc_cmp3                        32'b0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t rtc_cmp3: 32;
+    } b;
+} RTC_COMP_3_TypeDef;
+
+
+/* 0x20
+   31:0    R      rtc_cnt                         32'b0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t rtc_cnt: 32;
+    } b;
+} RTC_CNT0_TypeDef;
+
+
+/* 0x24
+   11:0    R      rtc_prescale_cnt                12'b0
+   31:12   R      rtc_prescaler_cnt0_reserved31_12 20'b0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t rtc_prescale_cnt: 12;
+        const uint32_t rtc_prescaler_cnt0_reserved31_12: 20;
+    } b;
+} RTC_PRESCALE_CNT0_TypeDef;
+
+
+/* 0x28
+   11:0    R/W    rtc_prescale_cmp                12'b0
+   31:12   R      rtc_prescaler_cmp0_reserved31_12 20'b0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t rtc_prescale_cmp: 12;
+        const uint32_t rtc_prescaler_cmp0_reserved31_12: 20;
+    } b;
+} RTC_PRESCALE_CMP0_TypeDef;
+
+
+/* 0x2C
+   31:0    R/W    rtc_backup                      32'b0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t rtc_backup: 32;
+    } b;
+} RTC_BACKUP_TypeDef;
+
+
+/* 0x30
+   31:0    R      rtc_rtl_version                 32'h20240402
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t rtc_rtl_version: 32;
+    } b;
+} RTC_RTL_VERSION0_TypeDef;
+
+
+/* 0x34
+   0       R/W    rtc_cmp0_reload_en              1'h0
+   1       R/W    rtc_cmp1_reload_en              1'h0
+   2       R/W    rtc_cmp2_reload_en              1'h0
+   3       R/W    rtc_cmp3_reload_en              1'h0
+   31:4    R      rtc_qactive_ctrl_reserved31_4   28'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t rtc_cmp0_reload_en: 1;
+        uint32_t rtc_cmp1_reload_en: 1;
+        uint32_t rtc_cmp2_reload_en: 1;
+        uint32_t rtc_cmp3_reload_en: 1;
+        const uint32_t rtc_qactive_ctrl_reserved31_4: 28;
+    } b;
+} RTC_RELOAD_CTRL_TypeDef;
+
+
+/* 0x38
+   31:0    R/W    rtc_cmp0_reload                 32'b0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t rtc_cmp0_reload: 32;
+    } b;
+} RTC_COMP_0_RELOAD_TypeDef;
+
+
+/* 0x3C
+   31:0    R/W    rtc_cmp1_reload                 32'b0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t rtc_cmp1_reload: 32;
+    } b;
+} RTC_COMP_1_RELOAD_TypeDef;
+
+
+/* 0x40
+   31:0    R/W    rtc_cmp2_reload                 32'b0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t rtc_cmp2_reload: 32;
+    } b;
+} RTC_COMP_2_RELOAD_TypeDef;
+
+
+/* 0x44
+   31:0    R/W    rtc_cmp3_reload                 32'b0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t rtc_cmp3_reload: 32;
+    } b;
+} RTC_COMP_3_RELOAD_TypeDef;
+
+
+/* 0x48
+   0       R/W    rtc_rap_mode                    1'h0
+   1       R/WAC  rtc_fw_task_start               1'h0
+   2       R/WAC  rtc_fw_task_stop                1'h0
+   3       R/WAC  rtc_fw_task_clear               1'h0
+   4       R/WAC  rtc_fw_task_reload_cmp0         1'h0
+   5       R/WAC  rtc_fw_task_reload_cmp1         1'h0
+   6       R/WAC  rtc_fw_task_reload_cmp2         1'h0
+   7       R/WAC  rtc_fw_task_reload_cmp3         1'h0
+   31:8    R      rtc_task_ctrl_reserved31_8      24'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t rtc_rap_mode: 1;
+        uint32_t rtc_fw_task_start: 1;
+        uint32_t rtc_fw_task_stop: 1;
+        uint32_t rtc_fw_task_clear: 1;
+        uint32_t rtc_fw_task_reload_cmp0: 1;
+        uint32_t rtc_fw_task_reload_cmp1: 1;
+        uint32_t rtc_fw_task_reload_cmp2: 1;
+        uint32_t rtc_fw_task_reload_cmp3: 1;
+        const uint32_t rtc_task_ctrl_reserved31_8: 24;
+    } b;
+} RTC_TASK_CTRL_TypeDef;
+
+
+/* 0x4C
+   0       R/W    rtc_task_stop_sub_en            1'h0
+   1       R/W    rtc_task_clear_sub_en           1'h0
+   2       R/W    rtc_task_reload_cmp0_sub_en     1'h0
+   3       R/W    rtc_task_reload_cmp1_sub_en     1'h0
+   4       R/W    rtc_task_reload_cmp2_sub_en     1'h0
+   5       R/W    rtc_task_reload_cmp3_sub_en     1'h0
+   15:6    R      rtc_shot_ctrl_reserved15_6      10'h0
+   16      R/W    rtc_event_cmp0_pub_en           1'h0
+   17      R/W    rtc_event_cmp1_pub_en           1'h0
+   18      R/W    rtc_event_cmp2_pub_en           1'h0
+   19      R/W    rtc_event_cmp3_pub_en           1'h0
+   31:20   R      rtc_shot_ctrl_reserved31_20     12'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t rtc_task_stop_sub_en: 1;
+        uint32_t rtc_task_clear_sub_en: 1;
+        uint32_t rtc_task_reload_cmp0_sub_en: 1;
+        uint32_t rtc_task_reload_cmp1_sub_en: 1;
+        uint32_t rtc_task_reload_cmp2_sub_en: 1;
+        uint32_t rtc_task_reload_cmp3_sub_en: 1;
+        const uint32_t rtc_shot_ctrl_reserved15_6: 10;
+        uint32_t rtc_event_cmp0_pub_en: 1;
+        uint32_t rtc_event_cmp1_pub_en: 1;
+        uint32_t rtc_event_cmp2_pub_en: 1;
+        uint32_t rtc_event_cmp3_pub_en: 1;
+        const uint32_t rtc_shot_ctrl_reserved31_20: 12;
+    } b;
+} RTC_SHOT_CTRL_TypeDef;
+
+
+/* 0x50
+   0       R/W    rtc_qact_sclk_man_data          1'h0
+   1       R/W    rtc_qact_sclk_man_en            1'h0
+   2       R/W    rtc_qact_pclk_man_data          1'h0
+   3       R/W    rtc_qact_pclk_man_en            1'h0
+   31:4    R      rtc_qactive_ctrl_reserved31_4   28'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t rtc_qact_sclk_man_data: 1;
+        uint32_t rtc_qact_sclk_man_en: 1;
+        uint32_t rtc_qact_pclk_man_data: 1;
+        uint32_t rtc_qact_pclk_man_en: 1;
+        const uint32_t rtc_qactive_ctrl_reserved31_4: 28;
+    } b;
+} RTC_QACTIVE_CTRL_TypeDef;
+
+
+/*============================================================================*
+ *                          RTC Constants
+ *============================================================================*/
+/** \defgroup RTC        RTC
+  * \brief
+  * \{
+  */
+
+/** \defgroup RTC_Exported_Constants RTC Exported Constants
+  * \brief
+  * \{
+  */
+
+/**
+ * \defgroup    RTC_CLOCK_IN RTC CLOCK IN
+ * \{
+ * \ingroup     RTC_Exported_Constants
+ */
+
+typedef enum
+{
+    RTC_CLOCK_IN_DISABLE,
+    RTC_CLOCK_IN_P5_1,
+    RTC_CLOCK_IN_P2_1,
+    RTC_CLOCK_IN_MAX = RTC_CLOCK_IN_DISABLE,
+} RTCClockIn_TypeDef;
+
+#define RTC_CLOCK_IN         (RTC_CLOCK_OUT_DISABLE | \
+                              RTC_CLOCK_OUT_P5_1 | \
+                              RTC_CLOCK_OUT_P2_1)
+
+/** End of RTC_CLOCK_IN
+  * \}
+  */
+
+/**
+ * \defgroup    RTC_CLOCK_OUT RTC CLOCK OUT
+ * \{
+ * \ingroup     RTC_Exported_Constants
+ */
+
+typedef enum
+{
+    RTC_CLOCK_OUT_P0_1_OSC,
+    RTC_CLOCK_OUT_P0_1_XTAL,
+    RTC_CLOCK_OUT_P0_3_OSC,
+    RTC_CLOCK_OUT_P0_3_XTAL,
+} RTCClockOut_TypeDef;
+
+#define RTC_CLOCK_OUT         (RTC_CLOCK_OUT_P0_1_OSC | \
+                               RTC_CLOCK_OUT_P0_1_XTAL | \
+                               RTC_CLOCK_OUT_P0_3_OSC \
+                               RTC_CLOCK_OUT_P0_3_XTAL)
+
+/** End of RTC_CLOCK_OUT
+  * \}
+  */
+
+/** End of RTC_Exported_Constants
+  * \}
+  */
+
+/*============================================================================*
+ *                         RTC Wrappers
+ *============================================================================*/
+
+/**
+ * \brief    RTC Macro Wrapper
+ *
+ * \ingroup  RTC_Exported_Constants
+ */
+#define RTC_WRITE(reg, value)         \
+    do {                              \
+        RTC->reg = (value);           \
+    } while (0)
+
+#define RTC_WRITE_DELAY(reg, value)   \
+    do {                              \
+        RTC->reg = (value);           \
+        platform_delay_us(63);        \
+    } while (0)
+
+/** End of RTC
+  * \}
+  */
+
+
+#ifdef  __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* RTL_RTC_DEF_H */
diff --git a/bee/drivers/rtc/src/device/rtl_common/CMakeLists.txt b/bee/drivers/rtc/src/device/rtl_common/CMakeLists.txt
new file mode 100644
index 00000000..9c39e9be
--- /dev/null
+++ b/bee/drivers/rtc/src/device/rtl_common/CMakeLists.txt
@@ -0,0 +1,5 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_library_sources_ifdef(CONFIG_REALTEK_BEE_RTC rtl_rtc.c)
+zephyr_library_sources_ifdef(CONFIG_REALTEK_BEE_GRTC rtl_grtc.c)
diff --git a/bee/drivers/rtc/src/device/rtl_common/rtl_grtc.c b/bee/drivers/rtc/src/device/rtl_common/rtl_grtc.c
new file mode 100644
index 00000000..dc5e7489
--- /dev/null
+++ b/bee/drivers/rtc/src/device/rtl_common/rtl_grtc.c
@@ -0,0 +1,322 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *                        Header Files
+ *============================================================================*/
+#include "rtl_grtc.h"
+
+/*============================================================================*
+ *                           Private Functions
+ *============================================================================*/
+#if (GRTC_SUPPORT_RAP_FUNCTION == 1)
+extern bool GRTC_IsSupportRAPComp(GRTCCompIndex_TypeDef Index);
+#endif
+
+/*============================================================================*
+ *                           Public Functions
+ *============================================================================*/
+/**
+  * \brief  Reset all registers of GRTC.
+  * \param  None
+  * \return None
+  */
+void GRTC_DeInit(void)
+{
+    /* Reset GRTC all registers */
+    GRTC_CTRL_TypeDef grtc_0x00 = {.d32 = GRTC->GRTC_CTRL};
+    grtc_0x00.b.grtc_rst = 1;
+    GRTC->GRTC_CTRL = grtc_0x00.d32;
+    __NOP();
+    __NOP();
+    grtc_0x00.b.grtc_rst = 0;
+    GRTC->GRTC_CTRL = grtc_0x00.d32;
+}
+
+/**
+  * \brief  Enable or disable the specified GRTC interrupt.
+  * \param  GRTC_INT: specifies the GRTC interrupt source to be enabled or disabled.
+  *         This parameter can be any combination of the following values:
+  *         \arg GRTC_INT_COMP0: compare 0 interrupt source
+  *         \arg GRTC_INT_COMP1: compare 1 interrupt source
+  *         \arg GRTC_INT_COMP2: compare 2 interrupt source
+  *         \arg GRTC_INT_COMP3: compare 3 interrupt source
+  *         \arg GRTC_INT_COMP4: compare 4 interrupt source
+  *         \arg GRTC_INT_COMP5: compare 5 interrupt source
+  *         \arg GRTC_INT_COMP6: compare 6 interrupt source
+  *         \arg GRTC_INT_COMP7: compare 7 interrupt source
+  * \param  NewState: New state of the specified GRTC interrupt.
+  * \return None.
+  */
+void GRTC_INTConfig(uint32_t GRTC_INT, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_GRTC_INT(GRTC_INT));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (NewState == ENABLE)
+    {
+        GRTC->GRTC_INTR_CTRL |= GRTC_INT;
+    }
+    else
+    {
+        GRTC->GRTC_INTR_CTRL &= (~GRTC_INT);
+    }
+}
+
+/**
+  * \brief  Checks whether the specified GRTC interrupt is set or not.
+  * \param  GRTC_INT: specifies the GRTC interrupt source to be enabled or disabled.
+  *         This parameter can be any combination of the following values:
+  *         \arg GRTC_INT_COMP0: compare 0 interrupt source
+  *         \arg GRTC_INT_COMP1: compare 1 interrupt source
+  *         \arg GRTC_INT_COMP2: compare 2 interrupt source
+  *         \arg GRTC_INT_COMP3: compare 3 interrupt source
+  *         \arg GRTC_INT_COMP4: compare 4 interrupt source
+  *         \arg GRTC_INT_COMP5: compare 5 interrupt source
+  *         \arg GRTC_INT_COMP6: compare 6 interrupt source
+  *         \arg GRTC_INT_COMP7: compare 7 interrupt source
+  * \return The new state of GRTC_INT (SET or RESET).
+  */
+ITStatus GRTC_GetINTStatus(uint32_t GRTC_INT)
+{
+    /* Check the parameters */
+    assert_param(IS_GRTC_CONFIG_INT(GRTC_INT));
+
+    if ((GRTC->GRTC_COMP_INTR_SR & GRTC_INT) != (uint32_t)RESET)
+    {
+        return SET;
+    }
+    return RESET;
+}
+
+/**
+  * \brief  Clear the interrupt pending bits of GRTC.
+  * \param  GRTC_INT: specifies the GRTC interrupt flag to clear.
+  *         This parameter can be any combination of the following values:
+  *         \arg GRTC_INT_COMP0: compare 0 interrupt source
+  *         \arg GRTC_INT_COMP1: compare 1 interrupt source
+  *         \arg GRTC_INT_COMP2: compare 2 interrupt source
+  *         \arg GRTC_INT_COMP3: compare 3 interrupt source
+  *         \arg GRTC_INT_COMP4: compare 4 interrupt source
+  *         \arg GRTC_INT_COMP5: compare 5 interrupt source
+  *         \arg GRTC_INT_COMP6: compare 6 interrupt source
+  *         \arg GRTC_INT_COMP7: compare 7 interrupt source
+  * \return None
+  */
+void GRTC_ClearINTPendingBit(uint32_t GRTC_INT)
+{
+    /* Check the parameters */
+    assert_param(IS_GRTC_INT(GRTC_INT));
+
+    GRTC_COMP_INT_CLR_TypeDef grtc_clr = {.d32 = GRTC->GRTC_COMP_INT_CLR};
+    grtc_clr.d32 |= GRTC_INT;
+    GRTC->GRTC_COMP_INT_CLR = grtc_clr.d32;
+}
+
+#if (GRTC_SUPPORT_ERROR_INTERRUPT == 1)
+/**
+  * \brief  Checks whether the specified GRTC error interrupt is set or not.
+  * \param  Index: The comparator number which can be 0 ~ 7.
+  * \return The new state of GRTC error interrupt (SET or RESET).
+  */
+ITStatus GRTC_GetErrorINTStatus(GRTCCompIndex_TypeDef Index)
+{
+    /* Check the parameters */
+    assert_param(IS_GRTC_COMP(Index));
+
+    if ((GRTC->GRTC_COMP_TIMEOUT_OV_ERR_SR & BIT(Index)) != (uint32_t)RESET)
+    {
+        return SET;
+    }
+    return RESET;
+}
+
+/**
+  * \brief  Clear the error interrupt pending bits of GRTC.
+  * \param  Index: The comparator number which can be 0 ~ 7.
+  * \return None
+  */
+void GRTC_ClearErrorINTPendingBit(GRTCCompIndex_TypeDef Index)
+{
+    /* Check the parameters */
+    assert_param(IS_GRTC_COMP(Index));
+
+    GRTC->GRTC_COMP_TIMEOUT_OV_ERR_CLR = BIT(Index);
+}
+#endif
+
+/**
+  * \brief  Set GRTC comparator value.
+  * \param  Index: The comparator number which can be 0 ~ 7.
+  * \param  Value: The comparator value.
+  * \return None
+  */
+void GRTC_SetCompValue(GRTCCompIndex_TypeDef Index, uint32_t Value)
+{
+    /* Check the parameters */
+    assert_param(IS_GRTC_COMP(Index));
+
+    (*((volatile uint32_t *)(&GRTC->GRTC_COMP_0) + Index)) = Value;
+}
+
+/**
+  * \brief  Get GRTC comparator value.
+  * \param  Index: The comparator number.
+  * \return The comparator value.
+  */
+uint32_t GRTC_GetCompValue(GRTCCompIndex_TypeDef Index)
+{
+    /* Check the parameters */
+    assert_param(IS_GRTC_COMP(Index));
+
+    return (*((volatile uint32_t *)(&GRTC->GRTC_COMP_0) + Index));
+}
+
+/**
+  * \brief  Enable or Disable the GRTC comparator reload function.
+  * \param  Index: The comparator number which can be 0 ~ 7.
+  * \param  NewState: new state of GRTC peripheral.
+  *         This parameter can be the following values:
+  *         \arg ENABLE: start GRTC.
+  *         \arg DISABLE: stop GRTC.
+  * \return None
+  */
+void GRTC_CompReloadCmd(GRTCCompIndex_TypeDef Index, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_GRTC_COMP(Index));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (NewState == ENABLE)
+    {
+        GRTC->GRTC_RELOAD_CTRL |= BIT(Index);
+    }
+    else
+    {
+        GRTC->GRTC_RELOAD_CTRL &= ~BIT(Index);
+    }
+}
+
+/**
+  * \brief  Set GRTC comparator reload value.
+  * \param  Index: The comparator number which can be 0 ~ 7.
+  * \param  Value: The comparator reload value.
+  * \return None
+  */
+void GRTC_SetCompReloadValue(GRTCCompIndex_TypeDef Index, uint32_t Value)
+{
+    /* Check the parameters */
+    assert_param(IS_GRTC_COMP(Index));
+
+    (*((volatile uint32_t *)(&GRTC->GRTC_COMP_0_RELOAD) + Index)) = Value;
+}
+
+/**
+  * \brief  Get GRTC comparator reload value.
+  * \param  Index: The comparator number.
+  * \return The comparator reload value.
+  */
+uint32_t GRTC_GetCompReloadValue(GRTCCompIndex_TypeDef Index)
+{
+    /* Check the parameters */
+    assert_param(IS_GRTC_COMP(Index));
+
+    return (*((volatile uint32_t *)(&GRTC->GRTC_COMP_0_RELOAD) + Index));
+}
+
+/**
+  * \brief  Enable or Disable the GRTC function of sleep control.
+  * \param  Index: The comparator number which can be 0 ~ 7.
+  * \param  NewState: new state of GRTC peripheral.
+  *         This parameter can be the following values:
+  *         \arg ENABLE: start GRTC.
+  *         \arg DISABLE: stop GRTC.
+  * \return None
+  */
+void GRTC_SleepCmd(GRTCCompIndex_TypeDef Index, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_GRTC_COMP(Index));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (NewState == ENABLE)
+    {
+        GRTC->GRTC_SLEEP_CTRL |= BIT(Index);
+    }
+    else
+    {
+        GRTC->GRTC_SLEEP_CTRL &= ~BIT(Index);
+    }
+}
+
+/**
+  * \brief  Get GRTC sleep counter.
+  * \param  Index: The comparator number which can be 0 ~ 7.
+  * \return The sleep counter.
+  */
+uint32_t GRTC_GetSleepCounter(GRTCCompIndex_TypeDef Index)
+{
+    /* Check the parameters */
+    assert_param(IS_GRTC_COMP(Index));
+
+    return (*((volatile uint32_t *)(&GRTC->GRTC_COMP_0_SLEEP_PENDING_CNT) + Index));
+}
+
+/*============================================================================*
+ *                        RAP Functions
+ *============================================================================*/
+#if (GRTC_SUPPORT_RAP_FUNCTION == 1)
+bool GRTC_RAPModeCmd(GRTCCompIndex_TypeDef Index, FunctionalState NewState)
+{
+    if (GRTC_IsSupportRAPComp(Index) == 0)
+    {
+        return false;
+    }
+
+    if (NewState == ENABLE)
+    {
+        GRTC->GRTC_TASK_CTRL |= BIT(Index);
+    }
+    else
+    {
+        GRTC->GRTC_TASK_CTRL &= ~BIT(Index);
+    }
+
+    return true;
+}
+
+bool GRTC_ActionTrigger(GRTCCompIndex_TypeDef Index, uint32_t Action)
+{
+    if (GRTC_IsSupportRAPComp(Index) == 0)
+    {
+        return false;
+    }
+
+    GRTC->GRTC_TASK_CTRL |= BIT(Index + 8 + (GRTC_COMP_NUM > 8) * 8);
+
+    return true;
+}
+#endif
+
+#if (GRTC_SUPPORT_FORCE_QACTIVE == 1)
+void GRTC_ForceQactiveCmd(GRTCCompIndex_TypeDef Index, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_GRTC_COMP(Index));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (NewState == ENABLE)
+    {
+        GRTC->GRTC_QACTIVE_CTRL |= BIT(8 + Index);
+    }
+    else
+    {
+        GRTC->GRTC_QACTIVE_CTRL &= ~BIT(8 + Index);
+    }
+}
+#endif
+
diff --git a/bee/drivers/rtc/src/device/rtl_common/rtl_rtc.c b/bee/drivers/rtc/src/device/rtl_common/rtl_rtc.c
new file mode 100644
index 00000000..213eadeb
--- /dev/null
+++ b/bee/drivers/rtc/src/device/rtl_common/rtl_rtc.c
@@ -0,0 +1,622 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *                           Header Files
+ *============================================================================*/
+#include "rtl_rtc.h"
+
+/*============================================================================*
+ *                           Private Functions
+ *============================================================================*/
+#if (RTC_SUPPORT_COMPARE_AUTO_RELOAD == 1)
+extern void RTC_CompAutoReloadCmd(RTCCompIndex_TypeDef Index, FunctionalState NewState);
+#endif
+
+#define DELAY_BETWEEN_SET_COMP()          platform_delay_us(47)   //1.5T 32K
+/*============================================================================*
+ *                           Public Functions
+ *============================================================================*/
+/**
+  * \brief  Reset RTC.
+  * \param  None
+  * \return None
+  */
+void RTC_DeInit(void)
+{
+#if (RTC_SUPPORT_RESET_REGISTER_TO_DEFAULT == 1)
+    RTC_CR0_TypeDef rtc_0x00 = {.d32 = 0};
+    rtc_0x00.b.rtc_rst = 1;
+    RTC_WRITE(RTC_CR0, rtc_0x00.d32);
+    __NOP();
+    __NOP();
+    RTC_WRITE(RTC_CR0, 0);
+#else
+    /* Stop RTC counter */
+    RTC_CR0_TypeDef rtc_0x00 = {.d32 = RTC->RTC_CR0};
+    rtc_0x00.b.rtc_cnt_start = 0;
+    RTC_WRITE(RTC_CR0, rtc_0x00.d32);
+
+    /* Disable wakeup signal */
+    rtc_0x00.b.rtc_nv_ie = 0;
+    rtc_0x00.b.rtc_wk_ie = 0;
+    RTC_WRITE(RTC_CR0, rtc_0x00.d32);
+
+    /* Clear all RTC interrupt & wakeup */
+    RTC_WRITE_DELAY(RTC_INT_CLEAR, 0xFFFF);
+
+    /* Clear prescale and prescale comparator register */
+    RTC_WRITE(RTC_PRESCALER0, 0);
+    RTC_WRITE(RTC_PRESCALE_CMP0, 0);
+
+    /* Clear all comparator register */
+    RTC_WRITE(RTC_COMP_0, 0);
+    RTC_WRITE(RTC_COMP_1, 0);
+    RTC_WRITE(RTC_COMP_2, 0);
+    RTC_WRITE(RTC_COMP_3, 0);
+
+#if (RTC_SUPPORT_WAKEUP_COMPARE_GUARDTIME == 1)
+    RTC_WRITE(RTC_COMP0_GT, 0);
+    RTC_WRITE(RTC_COMP1_GT, 0);
+    RTC_WRITE(RTC_COMP2_GT, 0);
+    RTC_WRITE(RTC_COMP3_GT, 0);
+#endif
+
+    /* Reset prescale counter and counter */
+    rtc_0x00.d32 = 0;
+    rtc_0x00.b.rtc_cnt_rst = 1;
+    rtc_0x00.b.rtc_pre_cnt_rst = 1;
+    RTC_WRITE(RTC_CR0, rtc_0x00.d32);
+    __NOP();
+    __NOP();
+    RTC_WRITE(RTC_CR0, 0);
+#endif
+
+    /* Accessing comp registers requires 1.5T 32K delay between each access.
+       Use one delay for overlapping delays at the last access. */
+    DELAY_BETWEEN_SET_COMP();
+}
+
+/**
+  * \brief  Set RTC prescaler value.
+  * \param  value: the prescaler value to be set.Should be no more than 12 bits!
+  * \return None
+  */
+void RTC_SetPrescaler(uint16_t Value)
+{
+    RTC_WRITE(RTC_PRESCALER0, Value & 0xFFF);
+}
+
+/**
+  * \brief  Start or stop RTC peripheral.
+  * \param  NewState: new state of RTC peripheral.
+  *         This parameter can be the following values:
+  *         \arg ENABLE: start RTC.
+  *         \arg DISABLE: stop RTC.
+  * \return None
+  */
+void RTC_Cmd(FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    /* Start or stop RTC */
+    RTC_CR0_TypeDef rtc_0x00 = {.d32 = RTC->RTC_CR0};
+    rtc_0x00.b.rtc_cnt_start = NewState;
+    RTC_WRITE(RTC_CR0, rtc_0x00.d32);
+}
+
+/**
+  * \brief  Enable or disable the specified RTC interrupts.
+  * \param  RTC_INT: specifies the RTC interrupt source to be enabled or disabled.
+  *         This parameter can be any combination of the following values:
+  *         \arg RTC_INT_TICK: tick interrupt
+  *         \arg RTC_INT_OVERFLOW: counter overflow interrupt
+  *         \arg RTC_INT_PRECOMP: prescale compare interrupt
+  *         \arg RTC_INT_PRECOMP_COMP3: prescale & compare 3 interrupt
+  *         \arg RTC_INT_COMP0: compare 0 interrupt
+  *         \arg RTC_INT_COMP1: compare 1 interrupt
+  *         \arg RTC_INT_COMP2: compare 2 interrupt
+  *         \arg RTC_INT_COMP3: compare 3 interrupt
+  * \param  NewState: new state of the specified RTC interrupt.
+  *         This parameter can be: ENABLE or DISABLE.
+  * \return None.
+  */
+void RTC_INTConfig(uint32_t RTC_INT, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_RTC_INT(RTC_INT));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    RTC_CR0_TypeDef rtc_0x00 = {.d32 = RTC->RTC_CR0};
+    if (NewState == ENABLE)
+    {
+        rtc_0x00.d32 |= RTC_INT;
+    }
+    else
+    {
+        rtc_0x00.d32 &= ~RTC_INT;
+    }
+    RTC_WRITE(RTC_CR0, rtc_0x00.d32);
+}
+
+/**
+  * \brief  Enable or disable the specified RTC wakeup function.
+  * \param  RTC_WAKEUP: specifies the RTC wakeup function to be enabled or disabled.
+  *         This parameter can be any combination of the following values:
+  *         \arg RTC_WAKEUP_TICK: tick wakeup function
+  *         \arg RTC_WAKEUP_OVERFLOW: tick wakeup function
+  *         \arg RTC_WAKEUP_PRECOMP: prescale compare wakeup function
+  *         \arg RTC_WAKEUP_PRECOMP_COMP3: prescale & compare 3 wakeup function
+  *         \arg RTC_WAKEUP_COMP0: compare 0 wakeup function
+  *         \arg RTC_WAKEUP_COMP1: compare 1 wakeup function
+  *         \arg RTC_WAKEUP_COMP2: compare 2 wakeup function
+  *         \arg RTC_WAKEUP_COMP3: compare 3 wakeup function
+  * \param  NewState: new state of the specified RTC wakeup function.
+  *         This parameter can be: ENABLE or DISABLE.
+  * \return None.
+  */
+void RTC_WakeUpConfig(uint32_t RTC_WAKEUP, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_RTC_WAKUP(RTC_WAKEUP));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+
+    RTC_CR0_TypeDef rtc_0x00 = {.d32 = RTC->RTC_CR0};
+    if (NewState == ENABLE)
+    {
+        rtc_0x00.d32 |= RTC_WAKEUP;
+    }
+    else
+    {
+        rtc_0x00.d32 &= ~RTC_WAKEUP;
+    }
+    RTC_WRITE(RTC_CR0, rtc_0x00.d32);
+}
+
+/**
+  * \brief  Enable interrupt signal to CPU NVIC.
+  * \param  This parameter can be: ENABLE or DISABLE.
+  * \return None.
+  */
+void RTC_NVICCmd(FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    RTC_CR0_TypeDef rtc_0x00 = {.d32 = RTC->RTC_CR0};
+    rtc_0x00.b.rtc_nv_ie = NewState;
+    RTC_WRITE(RTC_CR0, rtc_0x00.d32);
+}
+
+/**
+ * \brief  Enable or disable system wake up of RTC.
+ * \param  NewState: new state of the wake up function.
+ *         This parameter can be: ENABLE or DISABLE.
+ * \return None
+ */
+void RTC_WakeUpCmd(FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    RTC_CR0_TypeDef rtc_0x00 = {.d32 = RTC->RTC_CR0};
+    rtc_0x00.b.rtc_wk_ie = NewState;
+    RTC_WRITE(RTC_CR0, rtc_0x00.d32);
+}
+
+/**
+  * \brief  Checks whether the specified RTC interrupt is set or not.
+  * \param  RTC_INT: specifies the RTC interrupt source to be enabled or disabled.
+  *         This parameter can be any combination of the following values:
+  *         \arg RTC_INT_TICK: RTC tick interrupt source
+  *         \arg RTC_INT_PRECOMP: prescale compare interrupt source
+  *         \arg RTC_INT_PRECOMP_COMP3: prescale & compare 3 interrupt source
+  *         \arg RTC_INT_COMP0: compare 0 interrupt source
+  *         \arg RTC_INT_COMP1: compare 1 interrupt source
+  *         \arg RTC_INT_COMP2: compare 2 interrupt source
+  *         \arg RTC_INT_COMP3: compare 3 interrupt source
+  * \return The new state of RTC_INT (SET or RESET).
+  */
+ITStatus RTC_GetINTStatus(uint32_t RTC_INT)
+{
+    /* Check the parameters */
+    assert_param(IS_RTC_CONFIG_INT(RTC_INT));
+
+    if ((RTC->RTC_INT_SR & (RTC_INT >> 8)) != (uint32_t)RESET)
+    {
+        return SET;
+    }
+    return  RESET;
+}
+
+/**
+  * \brief  Checks whether the specified RTC wakeup state is set or not.
+  * \param  RTC_WAKEUP: specifies the RTC interrupt source to be enabled or disabled.
+  *         This parameter can be any combination of the following values:
+  *         \arg RTC_WAKEUP_TICK: tick wakeup function
+  *         \arg RTC_WAKEUP_OVERFLOW: tick wakeup function
+  *         \arg RTC_WAKEUP_PRECOMP: prescale compare wakeup function
+  *         \arg RTC_WAKEUP_PREOCOMP_COMP3: prescale & compare 3 wakeup function
+  *         \arg RTC_WAKEUP_COMP0GT: compare 0 gt wakeup function
+  *         \arg RTC_WAKEUP_COMP1GT: compare 1 gt wakeup function
+  *         \arg RTC_WAKEUP_COMP2GT: compare 2 gt wakeup function
+  *         \arg RTC_WAKEUP_COMP3GT: compare 3 gt wakeup function
+  *         \arg RTC_WAKEUP_COMP0: compare 0 wakeup function
+  *         \arg RTC_WAKEUP_COMP1: compare 1 wakeup function
+  *         \arg RTC_WAKEUP_COMP2: compare 2 wakeup function
+  *         \arg RTC_WAKEUP_COMP3: compare 3 wakeup function
+  * \return The new state of RTC_INT (SET or RESET).
+  */
+ITStatus RTC_GetWakeUpStatus(uint32_t RTC_WAKEUP)
+{
+    /* Check the parameters */
+    assert_param(IS_RTC_CONFIG_INT(RTC_WAKEUP));
+
+    if ((RTC->RTC_INT_SR & (RTC_WAKEUP >> 8)) != (uint32_t)RESET)
+    {
+        return SET;
+    }
+    return  RESET;
+}
+
+/**
+  * \brief  Clear the interrupt pending bits of RTC.
+  * \param  RTC_INT: specifies the RTC interrupt flag to clear.
+  *         This parameter can be any combination of the following values:
+  *         \arg RTC_INT_TICK: RTC tick interrupt source
+  *         \arg RTC_INT_OVERFLOW: RTC counter overflow interrupt source
+  *         \arg RTC_INT_PRECOMP: prescale compare interrupt source
+  *         \arg RTC_INT_PRECOMP_COMP3: prescale & compare 3 interrupt source
+  *         \arg RTC_INT_COMP0: compare 0 interrupt source
+  *         \arg RTC_INT_COMP1: compare 1 interrupt source
+  *         \arg RTC_INT_COMP2: compare 2 interrupt source
+  *         \arg RTC_INT_COMP3: compare 3 interrupt source
+  * \return None
+  */
+void RTC_ClearINTPendingBit(uint32_t RTC_INT)
+{
+    /* Check the parameters */
+    assert_param(IS_RTC_INT(RTC_INT));
+
+    RTC_INT_CLEAR_TypeDef rtc_0x04 = {.d32 = RTC->RTC_INT_CLEAR};
+    rtc_0x04.d32 |= RTC_INT >> 8;
+    RTC_WRITE_DELAY(RTC_INT_CLEAR, rtc_0x04.d32);
+}
+
+/**
+  * \brief  Clear the wakeup status bits of RTC.
+  * \param  RTC_WAKEUP: specifies the RTC wakeup flag to clear.
+  *         This parameter can be any combination of the following values:
+  *         \arg RTC_WAKEUP_TICK: tick wakeup function
+  *         \arg RTC_WAKEUP_OVERFLOW: tick wakeup function
+  *         \arg RTC_WAKEUP_PRECOMP: prescale compare wakeup function
+  *         \arg RTC_WAKEUP_PRECOMP_COMP3: prescale & compare 3 wakeup function
+  *         \arg RTC_WAKEUP_COMP0GT: compare 0 gt wakeup function
+  *         \arg RTC_WAKEUP_COMP1GT: compare 1 gt wakeup function
+  *         \arg RTC_WAKEUP_COMP2GT: compare 2 gt wakeup function
+  *         \arg RTC_WAKEUP_COMP3GT: compare 3 gt wakeup function
+  *         \arg RTC_WAKEUP_COMP0: compare 0 wakeup function
+  *         \arg RTC_WAKEUP_COMP1: compare 1 wakeup function
+  *         \arg RTC_WAKEUP_COMP2: compare 2 wakeup function
+  *         \arg RTC_WAKEUP_COMP3: compare 3 wakeup function
+  * \return None
+  */
+void RTC_ClearWakeUpStatusBit(uint32_t RTC_WAKEUP)
+{
+    /* Check the parameters */
+    assert_param(IS_RTC_WAKEUP(RTC_WAKEUP));
+
+    RTC_INT_CLEAR_TypeDef rtc_0x04 = {.d32 = RTC->RTC_INT_CLEAR};
+    rtc_0x04.d32 |= RTC_WAKEUP >> 8;
+    RTC_WRITE_DELAY(RTC_INT_CLEAR, rtc_0x04.d32);
+}
+
+/**
+  * \brief  Clear the interrupt pending bit of the select comparator of RTC.
+  * \param  Index: the comparator number 0~3.
+  * \return None
+  */
+void RTC_ClearCompINT(RTCCompIndex_TypeDef Index)
+{
+    RTC_INT_CLEAR_TypeDef rtc_0x04 = {.d32 = RTC->RTC_INT_CLEAR};
+    rtc_0x04.d32 |= (RTC_INT_COMP0 >> 8) << (uint32_t)Index;
+    RTC_WRITE_DELAY(RTC_INT_CLEAR, rtc_0x04.d32);
+}
+
+/**
+  * \brief  Clear the overflow interrupt pending bit of RTC.
+  * \param  None
+  * \return None
+  */
+void RTC_ClearOverFlowINT(void)
+{
+    RTC_INT_CLEAR_TypeDef rtc_0x04 = {.d32 = RTC->RTC_INT_CLEAR};
+    rtc_0x04.b.rtc_cnt_ov_clr = 0x1;
+    RTC_WRITE_DELAY(RTC_INT_CLEAR, rtc_0x04.d32);
+}
+
+/**
+  * \brief  Clear the tick interrupt pending bit of RTC.
+  * \param  None
+  * \return None
+  */
+void RTC_ClearTickINT(void)
+{
+    RTC_INT_CLEAR_TypeDef rtc_0x04 = {.d32 = RTC->RTC_INT_CLEAR};
+    rtc_0x04.b.rtc_tick_clr = 0x1;
+    RTC_WRITE_DELAY(RTC_INT_CLEAR, rtc_0x04.d32);
+}
+
+/**
+  * \brief  Set RTC comparator value.
+  * \param  Index: The comparator number,can be 0 ~ 3.
+  * \param  value: The comparator value to be set.Should be no more than 24 bits!
+  * \return None
+  */
+void RTC_SetCompValue(RTCCompIndex_TypeDef Index, uint32_t Value)
+{
+    /* Check the parameters */
+    assert_param(IS_RTC_COMP(Index));
+
+    switch (Index)
+    {
+    case RTC_COMP0:
+        RTC_WRITE(RTC_COMP_0, Value);
+        break;
+    case RTC_COMP1:
+        RTC_WRITE(RTC_COMP_1, Value);
+        break;
+    case RTC_COMP2:
+        RTC_WRITE(RTC_COMP_2, Value);
+        break;
+    case RTC_COMP3:
+        RTC_WRITE(RTC_COMP_3, Value);
+        break;
+    default:
+        break;
+    }
+
+    /* Accessing comp registers requires 1.5T 32K delay between each access.
+       Use one delay for overlapping delays at the last access. */
+    DELAY_BETWEEN_SET_COMP();
+}
+
+/**
+  * \brief  Get RTC comparator value.
+  * \param  Index: The comparator number.
+  * \return The comparator value.
+  */
+uint32_t RTC_GetCompValue(RTCCompIndex_TypeDef Index)
+{
+    return (*((volatile uint32_t *)(&RTC->RTC_COMP_0) + Index));
+}
+
+/**
+  * \brief  Set RTC prescaler comparator value.
+  * \param  value: The comparator value to be set.Should be no more than 12 bits!
+  * \return None
+  */
+void RTC_SetPreCompValue(uint32_t Value)
+{
+    RTC_WRITE(RTC_PRESCALE_CMP0, Value & 0xFFF);
+}
+
+/**
+  * \brief  Get RTC prescaler comparator value.
+  * \param  None.
+  * \return The prescaler comparator value.
+  */
+uint32_t RTC_GetPreCompValue(void)
+{
+    return RTC->RTC_PRESCALE_CMP0;
+}
+
+/**
+  * \brief  Reset counter value of RTC.
+  * \param  None
+  * \return None
+  */
+void RTC_ResetCounter(void)
+{
+    RTC_CR0_TypeDef rtc_0x00 = {.d32 = RTC->RTC_CR0};
+    rtc_0x00.b.rtc_cnt_rst = 1;
+    RTC_WRITE(RTC_CR0, rtc_0x00.d32);
+    __NOP();
+    __NOP();
+    rtc_0x00.b.rtc_cnt_rst = 0;
+    RTC_WRITE(RTC_CR0, rtc_0x00.d32);
+}
+
+/**
+  * \brief  Get counter value of RTC.
+  * \param  None.
+  * \return The counter value.
+  */
+uint32_t RTC_GetCounter(void)
+{
+    return RTC->RTC_CNT0;
+}
+
+/**
+  * \brief  Reset prescaler counter value of RTC.
+  * \param  None
+  * \return None
+  */
+void RTC_ResetPrescalerCounter(void)
+{
+    RTC_CR0_TypeDef rtc_0x00 = {.d32 = RTC->RTC_CR0};
+    rtc_0x00.b.rtc_pre_cnt_rst = 1;
+    RTC_WRITE(RTC_CR0, rtc_0x00.d32);
+    __NOP();
+    __NOP();
+    rtc_0x00.b.rtc_pre_cnt_rst = 0;
+    RTC_WRITE(RTC_CR0, rtc_0x00.d32);
+}
+
+/**
+  * \brief  Get prescaler counter value of RTC.
+  * \param  None.
+  * \return The prescaler counter value.
+  */
+uint32_t RTC_GetPreCounter(void)
+{
+    return RTC->RTC_PRESCALE_CNT0;
+}
+
+/**
+  * \brief  Set backup register for store time information.
+  * \param  value: the value which is set to backup reister
+  * \return None.
+  */
+void RTC_SetBackupReg(uint32_t Value)
+{
+    RTC_WRITE(RTC_BACKUP, Value);
+}
+
+/**
+  * \brief  Get backup register for store time information.
+  * \param  None.
+  * \return Register value.
+  */
+uint32_t RTC_GetBackupReg(void)
+{
+    return RTC->RTC_BACKUP;
+}
+
+#if (RTC_SUPPORT_COMPARE_AUTO_RELOAD == 1)
+void RTC_SetCompReloadValue(RTCCompIndex_TypeDef Index, uint32_t Value)
+{
+    /* Check the parameters */
+    assert_param(IS_RTC_COMP(Index));
+
+    switch (Index)
+    {
+    case RTC_COMP0:
+        RTC_WRITE(RTC_COMP_0_RELOAD, Value);
+        break;
+    case RTC_COMP1:
+        RTC_WRITE(RTC_COMP_1_RELOAD, Value);
+        break;
+    case RTC_COMP2:
+        RTC_WRITE(RTC_COMP_2_RELOAD, Value);
+        break;
+    case RTC_COMP3:
+        RTC_WRITE(RTC_COMP_3_RELOAD, Value);
+        break;
+    default:
+        break;
+    }
+}
+
+uint32_t RTC_GetCompReloadValue(RTCCompIndex_TypeDef Index)
+{
+    return (*((volatile uint32_t *)(&RTC->RTC_COMP_0_RELOAD) + Index));
+}
+
+void RTC_EnableCompAutoReload(RTCCompIndex_TypeDef Index, uint32_t Comp_Value,
+                              uint32_t Reload_Value)
+{
+    /* Set comp value before enable auto reload */
+    RTC_SetCompValue(Index, Comp_Value);
+    RTC_SetCompReloadValue(Index, Reload_Value);
+
+    RTC_CompAutoReloadCmd(Index, ENABLE);
+}
+
+void RTC_DisableCompAutoReload(RTCCompIndex_TypeDef Index)
+{
+    RTC_CompAutoReloadCmd(Index, DISABLE);
+}
+#endif
+
+#if (RTC_SUPPORT_WAKEUP_COMPARE_GUARDTIME == 1)
+/**
+  * \brief  Set RTC comparator GT value.
+  * \param  Index: The comparator gt number, can be 0 ~ 3.
+  * \param  value: The comparator value to be set.
+  * \return None
+  */
+void RTC_SetCompGTValue(RTCCompIndex_TypeDef Index, uint32_t Value)
+{
+    /* Check the parameters */
+    assert_param(IS_RTC_COMPGT(Index));
+
+    switch (Index)
+    {
+    case RTC_COMP0:
+        RTC_WRITE(RTC_COMP0_GT, Value);
+        break;
+    case RTC_COMP1:
+        RTC_WRITE(RTC_COMP1_GT, Value);
+        break;
+    case RTC_COMP2:
+        RTC_WRITE(RTC_COMP2_GT, Value);
+        break;
+    case RTC_COMP3:
+        RTC_WRITE(RTC_COMP3_GT, Value);
+        break;
+    default:
+        break;
+    }
+
+    /* Accessing comp registers requires 1.5T 32K delay between each access.
+       Use one delay for overlapping delays at the last access. */
+    DELAY_BETWEEN_SET_COMP();
+}
+
+/**
+  * \brief  Get RTC comparator gt value.
+  * \param  Index: The comparator number 0~3.
+  * \return The comparator value.
+  */
+uint32_t RTC_GetCompGTValue(RTCCompIndex_TypeDef Index)
+{
+    return (*((volatile uint32_t *)(&RTC->RTC_COMP0_GT) + Index));
+}
+#endif
+
+#if (RTC_SUPPORT_RAP_FUNCTION == 1)
+
+void RTC_RAPModeCmd(FunctionalState NewState)
+{
+    RTC_TASK_CTRL_TypeDef rtc_ctrl = {.d32 = RTC->RTC_TASK_CTRL};
+    rtc_ctrl.b.rtc_rap_mode = NewState;
+    RTC_WRITE_DELAY(RTC_TASK_CTRL, rtc_ctrl.d32);
+
+    return;
+}
+
+void RTC_ActionTrigger(uint32_t Action)
+{
+    RTC->RTC_TASK_CTRL |= BIT(Action + 1);
+
+    return;
+}
+
+void RTC_ShortcutCmd(uint32_t Action, uint32_t Event, FunctionalState NewState)
+{
+    if (Action == RTC_ACTION_START)
+    {
+        return;
+    }
+
+    if (NewState == ENABLE)
+    {
+        RTC->RTC_SHOT_CTRL |= (BIT(Action - 1) | BIT(Event + 16));
+    }
+    else
+    {
+        RTC->RTC_SHOT_CTRL &= ~(BIT(Action - 1) | BIT(Event + 16));
+    }
+
+    return;
+}
+#endif
+
+
+
diff --git a/bee/drivers/sdhc/CMakeLists.txt b/bee/drivers/sdhc/CMakeLists.txt
new file mode 100644
index 00000000..3e8fb371
--- /dev/null
+++ b/bee/drivers/sdhc/CMakeLists.txt
@@ -0,0 +1,4 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+add_subdirectory_ifdef(CONFIG_REALTEK_BEE_SDHC src)
diff --git a/bee/drivers/sdhc/Kconfig b/bee/drivers/sdhc/Kconfig
new file mode 100644
index 00000000..70ef4ea4
--- /dev/null
+++ b/bee/drivers/sdhc/Kconfig
@@ -0,0 +1,8 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config REALTEK_BEE_SDHC
+	bool "Realtek Bee SDHC driver"
+	default n
+	help
+	  This option enables the sdhc driver for Realtek Bee MCU.
diff --git a/bee/drivers/sdhc/src/CMakeLists.txt b/bee/drivers/sdhc/src/CMakeLists.txt
new file mode 100644
index 00000000..dd5e359a
--- /dev/null
+++ b/bee/drivers/sdhc/src/CMakeLists.txt
@@ -0,0 +1,4 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+add_subdirectory(device)
diff --git a/bee/drivers/sdhc/src/device/CMakeLists.txt b/bee/drivers/sdhc/src/device/CMakeLists.txt
new file mode 100644
index 00000000..d18af886
--- /dev/null
+++ b/bee/drivers/sdhc/src/device/CMakeLists.txt
@@ -0,0 +1,4 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+add_soc_series_subdir(rtl87x2g)
diff --git a/bee/drivers/sdhc/src/device/rtl87x2g/CMakeLists.txt b/bee/drivers/sdhc/src/device/rtl87x2g/CMakeLists.txt
new file mode 100644
index 00000000..4f4babec
--- /dev/null
+++ b/bee/drivers/sdhc/src/device/rtl87x2g/CMakeLists.txt
@@ -0,0 +1,4 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_include_directories(${CMAKE_CURRENT_SOURCE_DIR})
diff --git a/bee/drivers/sdhc/src/device/rtl87x2g/rtl_sdhc.h b/bee/drivers/sdhc/src/device/rtl87x2g/rtl_sdhc.h
new file mode 100644
index 00000000..3b925142
--- /dev/null
+++ b/bee/drivers/sdhc/src/device/rtl87x2g/rtl_sdhc.h
@@ -0,0 +1,420 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+*********************************************************************************************************
+* \file     rtl_sdhc.h
+* \brief    The header file of the peripheral SDHC driver.
+* \details  This file provides all SDHC(SD Host Controller) firmware functions.
+* \author   Bert
+* \date     2023-10-17
+* \version  v1.0
+* *********************************************************************************************************
+*/
+
+/*============================================================================*
+ *               Define to prevent recursive inclusion
+ *============================================================================*/
+#ifndef RTL_SDHC_H
+#define RTL_SDHC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*============================================================================*
+ *                        Header Files
+ *============================================================================*/
+#include "rtl_sdhc_reg.h"
+
+/*============================================================================*
+ *                          Private Functions
+ *============================================================================*/
+extern void *gSDHC0Sem;
+extern void *gSDHC1Sem;
+
+/** \defgroup 87X2G_SDHC        SDHC
+  * \brief
+  * \{
+  */
+
+/*============================================================================*
+ *                         Constants
+ *============================================================================*/
+/** \defgroup SDHC_Exported_Constants SDHC Exported Constants
+  * \brief
+  * \{
+  */
+
+/**
+ * \defgroup    SDHC_Macros SDHC Macros
+ * \{
+ * \ingroup     SDHC_Exported_Constants
+ */
+#define SDHC0_IRQn          SDHC_IRQn
+#define SDHC1_IRQn          SDHC_IRQn
+#define SDHC0_Handler       SDHC_Handler
+
+/** End of SDHC_Macros
+  * \}
+  */
+
+/**
+ * \defgroup    MAX_BLOCK_PER_DESC MAX BLOCK PER DESC
+ * \{
+ * \ingroup     SDHC_Exported_Constants
+ */
+#define DESC_CNT  4
+#define MAX_BLOCK_PER_DESC  16
+#define BYTES_PER_BLOCK  512
+
+#define MAX_BYTES_PER_DESC  (MAX_BLOCK_PER_DESC * BYTES_PER_BLOCK)
+#define MAX_BLOCK_PER_XFER  (MAX_BLOCK_PER_DESC * DESC_CNT)
+#define MAX_BYTES_PER_XFER  (MAX_BYTES_PER_DESC * DESC_CNT)
+
+/** End of MAX_BLOCK_PER_DESC
+  * \}
+  */
+
+#ifndef NDEBUG
+#include "trace.h"
+#include "utils.h"
+#define ASSERT(e) \
+    do { \
+        if(!(e)) { \
+            platform_delay_ms(1000); \
+            DBG_DIRECT("(" #e ") assert failed! Func: %s. Line: %d.", __func__, __LINE__); \
+            DBG_DIRECT("(" #e ") assert failed! Func: %s. Line: %d.", __func__, __LINE__); \
+            *(volatile int *)0x1 = 0; \
+        } \
+    } while(0)
+#else
+#define ASSERT(e) ((void)0)
+#endif // NDEBUG
+
+/**
+ * \brief       Specifies the data width.
+ *
+ * \ingroup     SDHC_Exported_Constants
+ */
+typedef enum
+{
+    DATAWIDTH_1BIT,
+    DATAWIDTH_4BIT,
+    DATAWIDTH_8BIT,
+    DATAWIDTH_4BIT_DDR,
+    DATAWIDTH_8BIT_DDR,
+} DataWidth_t;
+
+/**
+ * \brief       Specifies the data transfer direction,
+ *              whether the transfer is a read or write.
+ *
+ * \ingroup     SDHC_Exported_Constants
+ */
+typedef enum
+{
+    READ_DATA = 0,
+    WRITE_DATA = 1,
+} SDHC_TransferDir_t;
+
+/**
+ * \brief       Specifies whether data transfer is in stream or block mode.
+ *
+ * \ingroup     SDHC_Exported_Constants
+ */
+typedef enum
+{
+    BLOCK_TRANSFER = 0,
+    STREAM_TRANSFER = 1,
+} SDHC_TransferMode_t;
+
+/**
+ * \brief       Specifies whether data transfer by dma or host.
+ *
+ * \ingroup     SDHC_Exported_Constants
+ */
+typedef enum
+{
+    OWN_BY_HOST = 0,
+    OWN_BY_DMA = 1,
+} SDHC_TransferDma_t;
+
+/**
+ * \brief       SDHC Clock Source Selection
+ *
+ * \ingroup     SDHC_Exported_Constants
+ */
+typedef enum
+{
+    CLKSRC_CLK_40M_VCORE4 = 0,
+    CLKSRC_CKO1_PLL1_VCORE4 = 1,
+    CLKSRC_CKO1_PLL2_VCORE4 = 3,
+} ClockSrcSel_t;
+
+
+/**
+ * \brief       SDHC Result Error
+ *
+ * \ingroup     SDHC_Exported_Constants
+ */
+typedef enum
+{
+    SDHCRES_OK = 0,
+
+    SDHCRES_HARDWARE_LOCKED_ERROR, // 1
+    SDHCRES_RESPONSE_ERROR,
+    SDHCRES_RESPONSE_CRC_ERROR,
+    SDHCRES_RESPONSE_TIMEOUT,
+
+    SDHCRES_DATA_CRC_ERROR, // 5
+    SDHCRES_DATA_READ_TIMEOUT,
+    SDHCRES_DATA_START_BIT_ERROR,
+    SDHCRES_DATA_END_BIT_ERROR,
+    SDHCRES_WRITE_NO_CRC, // 9
+
+    SDHCRES_FATAL_BUS_ERROR,
+    SDHCRES_DESCRIPTOR_UNAVAILABLE,
+    SDHCRES_CARD_ERROR, // 12
+
+    SDHCRES_WAIT_DATA0_IDLE_TIMEOUT,
+} SDHCRes_t;
+
+/** End of SDHC_Exported_Constants
+  * \}
+  */
+
+typedef struct
+{
+    uint32_t sdhc_reg[15];
+} SDHCStoreReg_Typedef;
+
+/*============================================================================*
+ *                         Types
+ *============================================================================*/
+/** \defgroup SDHC_Exported_Types SDHC Exported Types
+  * \brief
+  * \{
+  */
+
+/**
+ * \brief       SDHC init structure definition.
+ *
+ * \ingroup     SDHC_Exported_Types
+ */
+typedef struct
+{
+    uint8_t CmdIdx;        /*!< Specifies the SDHC command index. It must be lower than 0x40 */
+
+    uint32_t CmdArg;       /*!< Specifies the SDHC command argument which is sent
+                                to a card as part of a command message. If a command
+                                contains an argument, it must be loaded into this register
+                                before writing the command to the command register */
+
+    bool IsResetCmd;       /*!< Specifies whether Send initialization sequence before sending
+                                this command After power on.
+                                Such as CMD0 is ResetCmd */
+
+    bool IsStopCmd;        /*!< Specifies whether stop current data transfer in progress.
+                                Such as CMD12 is StopCmd */
+
+    bool IsRspExpected;    /*!< Specifies wethcer response is expected from card.
+                                Such as CMD0, CMD4, CMD15... have no response */
+
+    bool IsR2Rsp;          /*!< Specifies wethcer long response is expected from card.
+                                Such as R2 is long response.*/
+
+    bool CheckRspCrc;      /*!< Specifies wethcer check response CRC.
+                                Some of command responses do not return valid CRC bits,
+                                such as ACMD41 for eMMC and CMD8 for SD.*/
+} CmdInfo_t;
+
+
+typedef struct
+{
+    uint32_t BlockSize;    /*!< Specifies the data block size for block transfer.
+                                This parameter usually is 512 bytes */
+
+    uint32_t BlockCount;   /*!< Specifies the block counts you want to transfer */
+
+    bool SendAutoStop;     /*!< Specifies wethcer send stop command at end of data transfer.
+                                Such as CMD12 will be sent automatically after data transfer. */
+} DataInfo_t;
+
+
+typedef struct
+{
+    struct
+    {
+        uint32_t Reserved0: 1;
+        uint32_t DisableInterruptOnCompletion: 1;
+        uint32_t LastDescriptor: 1;
+        uint32_t FirstDescriptor: 1;
+        uint32_t SecondAddressChained: 1;
+        uint32_t EndOfRing: 1;
+        uint32_t Reserved1: 24;
+        uint32_t CardErrorSummary: 1;
+        uint32_t OWN: 1;
+    } DES0;
+    struct
+    {
+        uint32_t Buffer1Size: 13;
+        uint32_t Buffer2Size: 13;
+        uint32_t Reserved: 6;
+    } DES1;
+    struct
+    {
+        uint32_t BufferAddressPointer1: 32;
+    } DES2;
+    struct
+    {
+        uint32_t BufferAddressPointer2: 32;
+    } DES3;
+} __attribute__((packed)) DmaDesc_t;
+
+/** End of SDHC_Exported_Types
+  * \}
+  */
+
+/*============================================================================*
+ *                         Functions
+ *============================================================================*/
+/** \defgroup SDHC_Exported_Functions SDHC Exported Functions
+  * \brief
+  * \{
+  */
+
+/**
+  * \brief  Initializes the SDHC Pad.
+  * \param  SDHCx: Specifies the SDHC peripheral.
+  * \param  DataWidth: Specifies the data width.
+  * \return None
+  */
+void SDHC_InitPad(SDHC_TypeDef *SDHCx, DataWidth_t DataWidth);
+
+/**
+  * \brief  Deinitializes the SDHC Pad.
+  * \param  SDHCx: Specifies the SDHC peripheral.
+  * \param  DataWidth: Specifies the data width.
+  * \return None
+  */
+void SDHC_DeInitPad(SDHC_TypeDef *SDHCx, DataWidth_t DataWidth);
+
+/**
+  * \brief  Initializes the SDHC peripheral.
+  * \param  SDHCx: Specifies the SDHC peripheral.
+  * \return None
+  */
+void SDHC_Init(SDHC_TypeDef *SDHCx);
+
+/**
+  * \brief  Deinitializes the SDHC peripheral.
+  * \param  SDHCx: Specifies the SDHC peripheral.
+  * \return None
+  */
+void SDHC_DeInit(SDHC_TypeDef *SDHCx);
+
+/**
+  * \brief  Set the SDHC Clock out.
+  * \param  SDHCx: Specifies the SDHC peripheral.
+  * \param  Freq_kHz: Specifies the SDHC Clock out value.
+            This parameter unit is kHz.
+  * \return None
+  */
+uint32_t SDHC_SetClkOutFreq(SDHC_TypeDef *SDHCx, uint32_t Freq_kHz);
+
+/**
+  * \brief  Get the SDHC Clock out.
+  * \param  SDHCx: Specifies the SDHC peripheral.
+  * \return SDHC Clock out: This parameter unit is kHz.
+  */
+uint32_t SDHC_GetClkOutFreq_kHz(SDHC_TypeDef *SDHCx);
+
+/**
+  * \brief  Set the transfer data width.
+  * \param  SDHCx: Specifies the SDHC peripheral.
+  * \param  Width: Specifies the transfer data width.
+  * \return None
+  */
+void SDHC_SetHostDataWidth(SDHC_TypeDef *SDHCx, DataWidth_t Width);
+
+/**
+  * \brief  Send cmd without data.
+  * \param  SDHCx: Specifies the SDHC peripheral.
+  * \param  pCmdInfo: pointer to a cmd info, such as Cmd0.
+  * \param  pRspBuf: pointer to a response buffer.
+  * \return SDHCRes_t: SDHC Result error
+  */
+SDHCRes_t SDHC_SendNoDataCmd(SDHC_TypeDef *SDHCx, const CmdInfo_t *pCmdInfo, void *pRspBuf);
+
+/**
+  * \brief  Send cmd without rx data.
+  * \param  SDHCx: Specifies the SDHC peripheral.
+  * \param  pCmdInfo: pointer to a cmd info, such as Cmd18.
+  * \param  pRspBuf: pointer to a response buffer.
+  * \param  pDataInfo: pointer to a data info.
+  * \param  pRxDataBuf: pointer to a rx data buffer.
+  * \return SDHCRes_t: SDHC Result error
+  */
+SDHCRes_t SDHC_SendCmdWithRxData(SDHC_TypeDef *SDHCx,
+                                 const CmdInfo_t *pCmdInfo, void *pRspBuf,
+                                 const DataInfo_t *pDataInfo, void *pRxDataBuf);
+
+/**
+  * \brief  Send cmd without tx data.
+  * \param  SDHCx: Specifies the SDHC peripheral.
+  * \param  pCmdInfo: pointer to a cmd info, such as Cmd25.
+  * \param  pRspBuf: pointer to a response buffer.
+  * \param  pDataInfo: pointer to a data info.
+  * \param  pRxDataBuf: pointer to a tx data buffer.
+  * \return SDHCRes_t: SDHC Result error
+  */
+SDHCRes_t SDHC_SendCmdWithTxData(SDHC_TypeDef *SDHCx,
+                                 const CmdInfo_t *pCmdInfo, void *pRspBuf,
+                                 const DataInfo_t *pDataInfo, const void *pDataToTx);
+
+/**
+  * \brief  Wait Data idle.
+  * \param  SDHCx: Specifies the SDHC peripheral.
+  * \param  Timeout_ms: wait data idle time, which uite is ms.
+  * \return SDHCRes_t: SDHC Result error
+  */
+SDHCRes_t SDHC_WaitData0Idle(SDHC_TypeDef *SDHCx, uint32_t Timeout_ms);
+
+/**
+  * \brief  Disable Interrupt nvic.
+  * \param  SDHCx: Specifies the SDHC peripheral.
+  * \return SDHCRes_t: SDHC Result error
+  */
+void DisableIntrByNvic(SDHC_TypeDef *SDHCx);
+
+void ResetAll(SDHC_TypeDef *SDHCx);
+void InitClk(SDHC_TypeDef *SDHCx);
+
+void SDHC_DLPSEnter(void *PeriReg, void *StoreBuf);
+
+void SDHC_DLPSExit(void *PeriReg, void *StoreBuf);
+
+/* pParm is shallow copied, and must keep valid during the whole SDHC session. */
+
+/* All the APIs must run in task environment. */
+
+/* The asynchronous API may not be needed because if it is,
+   you can build a separate task to do it using the synchronous API. */
+
+/** End of SDHC_Exported_Functions
+  * \}
+  */
+
+/** End of SDHC
+  * \}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RTL_SDHC_H */
diff --git a/bee/drivers/sdhc/src/device/rtl87x2g/rtl_sdhc_reg.h b/bee/drivers/sdhc/src/device/rtl87x2g/rtl_sdhc_reg.h
new file mode 100644
index 00000000..897b4e3b
--- /dev/null
+++ b/bee/drivers/sdhc/src/device/rtl87x2g/rtl_sdhc_reg.h
@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef RTL_SDHC_REG_H
+#define RTL_SDHC_REG_H
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "rtl876x.h"
+
+#ifdef  __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/*============================================================================*
+ *                         SDHC Registers Memory Map
+ *============================================================================*/
+typedef struct
+{
+    __IO uint32_t CTRL;                   /*!< 0x00 */
+    __IO uint32_t PWREN;                  /*!< 0x04 */
+    __IO uint32_t CLKDIV;                 /*!< 0x08 */
+    __IO uint32_t CLKSRC;                 /*!< 0x0C */
+    __IO uint32_t CLKENA;                 /*!< 0x10 */
+    __IO uint32_t TMOUT;                  /*!< 0x14 */
+    __IO uint32_t CTYPE;                  /*!< 0x18 */
+    __IO uint32_t BLKSIZ;                 /*!< 0x1C */
+    __IO uint32_t BYTCNT;                 /*!< 0x20 */
+    __IO uint32_t INTMASK;                /*!< 0x24 */
+    __IO uint32_t CMDARG;                 /*!< 0x28 */
+    __IO uint32_t CMD;                    /*!< 0x2C */
+    __I  uint32_t RESP0;                  /*!< 0x30 */
+    __I  uint32_t RESP1;                  /*!< 0x34 */
+    __I  uint32_t RESP2;                  /*!< 0x38 */
+    __I  uint32_t RESP3;                  /*!< 0x3C */
+    __I  uint32_t MINTSTS;                /*!< 0x40 */
+    __IO uint32_t RINTSTS;                /*!< 0x44 */
+    __I  uint32_t STATUS;                 /*!< 0x48 */
+    __IO uint32_t FIFOTH;                 /*!< 0x4C */
+    __I  uint32_t CDETECT;                /*!< 0x50 */
+    __I  uint32_t WRTPRT;                 /*!< 0x54 */
+    __IO uint32_t GPIO;                   /*!< 0x58 */
+    __I  uint32_t TCBCNT;                 /*!< 0x5C */
+    __I  uint32_t TBBCNT;                 /*!< 0x60 */
+    __IO uint32_t DEBNCE;                 /*!< 0x64 */
+    __IO uint32_t USRID;                  /*!< 0x68 */
+    __I  uint32_t VERID;                  /*!< 0x6C */
+    __I  uint32_t HCON;                   /*!< 0x70 */
+    __IO uint32_t UHS_REG;                /*!< 0x74 */
+    __IO uint32_t RST_N;                  /*!< 0x78 */
+    __I  uint32_t Reserved0;              /*!< 0x7C */
+    __IO uint32_t BMOD;                   /*!< 0x80 */
+    __O  uint32_t PLDMND;                 /*!< 0x84 */
+    __IO uint32_t DBADDR;                 /*!< 0x88 */
+    __IO uint32_t IDSTS;                  /*!< 0x8C */
+    __IO uint32_t IDINTEN;                /*!< 0x90 */
+    __I  uint32_t DSCADDR;                /*!< 0x94 */
+    __I  uint32_t BUFADDR;                /*!< 0x98 */
+    __I  uint8_t Reserved1[0x100 - 0x9C]; /*!< 0x9C */
+    __IO uint32_t CARDTHRCTL;             /*!< 0x100 */
+    __IO uint32_t BACK_END_POWER;         /*!< 0x104 */
+    __IO uint32_t UHS_REG_EXT;            /*!< 0x108 */
+    __IO uint32_t EMMC_DDR_REG;           /*!< 0x10C */
+    __IO uint32_t ENABLE_SHIFT;           /*!< 0x110 */
+    __IO uint8_t Reserved2[0x100 - 0x14]; /*!< 0x114 */
+    __IO uint32_t DATA;                   /*!< >=0x200 */
+} SDHC_TypeDef;
+
+/*============================================================================*
+ *                         SDHC Declaration
+ *============================================================================*/
+#define SDHC0                           ((SDHC_TypeDef *) SDHC_REG_BASE)
+#define SDHC1                           ((SDHC_TypeDef *) SDHC_REG_BASE)
+
+#ifdef  __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* RTL_SDHC_REG_H */
+
diff --git a/bee/drivers/spi/CMakeLists.txt b/bee/drivers/spi/CMakeLists.txt
new file mode 100644
index 00000000..487ec320
--- /dev/null
+++ b/bee/drivers/spi/CMakeLists.txt
@@ -0,0 +1,8 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+if(CONFIG_REALTEK_BEE_COMMON_DRIVER)
+    zephyr_include_directories(inc)
+endif()
+
+add_subdirectory_ifdef(CONFIG_REALTEK_BEE_SPI src)
diff --git a/bee/drivers/spi/Kconfig b/bee/drivers/spi/Kconfig
new file mode 100644
index 00000000..8867a615
--- /dev/null
+++ b/bee/drivers/spi/Kconfig
@@ -0,0 +1,8 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config REALTEK_BEE_SPI
+	bool "Realtek Bee SPI driver"
+	default n
+	help
+	  This option enables the spi driver for Realtek Bee.
diff --git a/bee/drivers/spi/inc/rtl_spi.h b/bee/drivers/spi/inc/rtl_spi.h
new file mode 100644
index 00000000..e24bf33e
--- /dev/null
+++ b/bee/drivers/spi/inc/rtl_spi.h
@@ -0,0 +1,1324 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *               Define to prevent recursive inclusion
+ *============================================================================*/
+#ifndef RTL_SPI_H
+#define RTL_SPI_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*============================================================================*
+ *                        Header Files
+ *============================================================================*/
+#include "utils/rtl_utils.h"
+#if defined (CONFIG_SOC_SERIES_RTL87X2G)
+#include "spi/src/device/rtl87x2g/rtl_spi_def.h"
+#elif defined (CONFIG_SOC_SERIES_RTL87X3E)
+#include "spi/src/device/rtl87x3e/rtl_spi_def.h"
+#elif defined (CONFIG_SOC_SERIES_RTL87X3D)
+#include "spi/src/device/rtl87x3d/rtl_spi_def.h"
+#elif defined (CONFIG_SOC_SERIES_RTL87X2J)
+#include "spi/src/device/rtl87x2j/rtl_spi_def.h"
+#elif defined (CONFIG_SOC_SERIES_RTL87X3J)
+#include "spi/src/device/rtl87x3j/rtl_spi_def.h"
+#endif
+
+/** \defgroup SPI         SPI
+  * \brief
+  * \{
+  */
+/*============================================================================*
+ *                         Constants
+ *============================================================================*/
+/** \defgroup SPI_Exported_Constants SPI Exported Constants
+  * \brief
+  * \{
+  */
+
+/**
+ * \defgroup    SPI_Clock_Speed SPI Clock Speed
+ * \{
+ * \ingroup     SPI_Exported_Constants
+ */
+#define IS_SPI_CLOCK_SPEED(SPEED) (((SPEED) >= 0x01) && \
+                                   ((SPEED) <= 40000000))
+
+/** End of SPI_Clock_Speed
+  * \}
+  */
+
+/**
+ * \defgroup    SPI_Direction SPI Direction
+ * \{
+ * \ingroup     SPI_Exported_Constants
+ */
+typedef enum
+{
+    SPI_DIRECTION_FULLDUPLEX = 0x00,
+    SPI_DIRECTION_TXONLY     = 0x01,
+    SPI_DIRECTION_RXONLY     = 0x02,
+    SPI_DIRECTION_EEPROM     = 0x03,
+} SPIDirection_TypeDef;
+
+#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_DIRECTION_FULLDUPLEX) || \
+                                     ((MODE) == SPI_DIRECTION_TXONLY) || \
+                                     ((MODE) == SPI_DIRECTION_RXONLY) || \
+                                     ((MODE) == SPI_DIRECTION_EEPROM))
+
+/** End of SPI_Direction
+  * \}
+  */
+
+/**
+ * \defgroup    SPI_Data_Size SPI Data Size
+ * \{
+ * \ingroup     SPI_Exported_Constants
+ */
+
+typedef enum
+{
+    SPI_DATA_SIZE_4b  = 0x03,
+    SPI_DATA_SIZE_5b  = 0x04,
+    SPI_DATA_SIZE_6b  = 0x05,
+    SPI_DATA_SIZE_7b  = 0x06,
+    SPI_DATA_SIZE_8b  = 0x07,
+    SPI_DATA_SIZE_9b  = 0x08,
+    SPI_DATA_SIZE_10b = 0x09,
+    SPI_DATA_SIZE_11b = 0x0a,
+    SPI_DATA_SIZE_12b = 0x0b,
+    SPI_DATA_SIZE_13b = 0x0c,
+    SPI_DATA_SIZE_14b = 0x0d,
+    SPI_DATA_SIZE_15b = 0x0e,
+    SPI_DATA_SIZE_16b = 0x0f,
+#if (SPI_SUPPORT_DFS_4BIT_TO_16BIT == 0)
+    SPI_DATA_SIZE_17b = 0x10,
+    SPI_DATA_SIZE_18b = 0x11,
+    SPI_DATA_SIZE_19b = 0x12,
+    SPI_DATA_SIZE_20b = 0x13,
+    SPI_DATA_SIZE_21b = 0x14,
+    SPI_DATA_SIZE_22b = 0x15,
+    SPI_DATA_SIZE_23b = 0x16,
+    SPI_DATA_SIZE_24b = 0x17,
+    SPI_DATA_SIZE_25b = 0x18,
+    SPI_DATA_SIZE_26b = 0x19,
+    SPI_DATA_SIZE_27b = 0x1A,
+    SPI_DATA_SIZE_28b = 0x1B,
+    SPI_DATA_SIZE_29b = 0x1C,
+    SPI_DATA_SIZE_30b = 0x1D,
+    SPI_DATA_SIZE_31b = 0x1E,
+    SPI_DATA_SIZE_32b = 0x1F,
+#endif
+} SPIDataSize_TypeDef;
+
+#if (SPI_SUPPORT_DFS_4BIT_TO_16BIT == 1)
+#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATA_SIZE_4b)  || \
+                                   ((DATASIZE) == SPI_DATA_SIZE_5b)  || \
+                                   ((DATASIZE) == SPI_DATA_SIZE_6b)  || \
+                                   ((DATASIZE) == SPI_DATA_SIZE_7b)  || \
+                                   ((DATASIZE) == SPI_DATA_SIZE_8b)  || \
+                                   ((DATASIZE) == SPI_DATA_SIZE_9b)  || \
+                                   ((DATASIZE) == SPI_DATA_SIZE_10b) || \
+                                   ((DATASIZE) == SPI_DATA_SIZE_11b) || \
+                                   ((DATASIZE) == SPI_DATA_SIZE_12b) || \
+                                   ((DATASIZE) == SPI_DATA_SIZE_13b) || \
+                                   ((DATASIZE) == SPI_DATA_SIZE_14b) || \
+                                   ((DATASIZE) == SPI_DATA_SIZE_15b) || \
+                                   ((DATASIZE) == SPI_DATA_SIZE_16b))
+
+#else
+#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATA_SIZE_4b)  || \
+                                   ((DATASIZE) == SPI_DATA_SIZE_5b)  || \
+                                   ((DATASIZE) == SPI_DATA_SIZE_6b)  || \
+                                   ((DATASIZE) == SPI_DATA_SIZE_7b)  || \
+                                   ((DATASIZE) == SPI_DATA_SIZE_8b)  || \
+                                   ((DATASIZE) == SPI_DATA_SIZE_9b)  || \
+                                   ((DATASIZE) == SPI_DATA_SIZE_10b) || \
+                                   ((DATASIZE) == SPI_DATA_SIZE_11b) || \
+                                   ((DATASIZE) == SPI_DATA_SIZE_12b) || \
+                                   ((DATASIZE) == SPI_DATA_SIZE_13b) || \
+                                   ((DATASIZE) == SPI_DATA_SIZE_14b) || \
+                                   ((DATASIZE) == SPI_DATA_SIZE_15b) || \
+                                   ((DATASIZE) == SPI_DATA_SIZE_16b) || \
+                                   ((DATASIZE) == SPI_DATA_SIZE_17b) || \
+                                   ((DATASIZE) == SPI_DATA_SIZE_18b) || \
+                                   ((DATASIZE) == SPI_DATA_SIZE_19b) || \
+                                   ((DATASIZE) == SPI_DATA_SIZE_20b) || \
+                                   ((DATASIZE) == SPI_DATA_SIZE_21b) || \
+                                   ((DATASIZE) == SPI_DATA_SIZE_22b) || \
+                                   ((DATASIZE) == SPI_DATA_SIZE_23b) || \
+                                   ((DATASIZE) == SPI_DATA_SIZE_24b) || \
+                                   ((DATASIZE) == SPI_DATA_SIZE_25b) || \
+                                   ((DATASIZE) == SPI_DATA_SIZE_26b) || \
+                                   ((DATASIZE) == SPI_DATA_SIZE_27b) || \
+                                   ((DATASIZE) == SPI_DATA_SIZE_28b) || \
+                                   ((DATASIZE) == SPI_DATA_SIZE_29b) || \
+                                   ((DATASIZE) == SPI_DATA_SIZE_30b) || \
+                                   ((DATASIZE) == SPI_DATA_SIZE_31b) || \
+                                   ((DATASIZE) == SPI_DATA_SIZE_32b))
+#endif
+
+/** End of SPI_Data_Size
+  * \}
+  */
+
+/**
+ * \defgroup    SPI_Clock_Polarity SPI Clock Polarity
+ * \{
+ * \ingroup     SPI_Exported_Constants
+ */
+typedef enum
+{
+    SPI_CPOL_LOW = 0x00,
+    SPI_CPOL_HIGH = 0x01,
+} SPIClockPolarity_TypeDef;
+
+#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_LOW) || \
+                           ((CPOL) == SPI_CPOL_HIGH))
+
+/** End of SPI_Clock_Polarity
+  * \}
+  */
+
+/**
+ * \defgroup    SPI_Clock_Phase SPI Clock Phase
+ * \{
+ * \ingroup     SPI_Exported_Constants
+ */
+typedef enum
+{
+    SPI_CPHA_1EDGE = 0x00,
+    SPI_CPHA_2EDGE = 0x01,
+} SPIClockPhase_TypeDef;
+
+#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1EDGE) || \
+                           ((CPHA) == SPI_CPHA_2EDGE))
+
+/** End of SPI_Clock_Phase
+  * \}
+  */
+
+/**
+ * \defgroup    SPI_BaudRate_Prescaler SPI BaudRate Prescaler
+ * \{
+ * \ingroup     SPI_Exported_Constants
+ */
+typedef enum
+{
+    SPI_BAUDRATE_PRESCALER_2   = 0x02,
+    SPI_BAUDRATE_PRESCALER_4   = 0x04,
+    SPI_BAUDRATE_PRESCALER_6   = 0x06,
+    SPI_BAUDRATE_PRESCALER_8   = 0x08,
+    SPI_BAUDRATE_PRESCALER_10  = 0x0A,
+    SPI_BAUDRATE_PRESCALER_12  = 0x0C,
+    SPI_BAUDRATE_PRESCALER_14  = 0x0E,
+    SPI_BAUDRATE_PRESCALER_16  = 0x10,
+    SPI_BAUDRATE_PRESCALER_32  = 0x20,
+    SPI_BAUDRATE_PRESCALER_64  = 0x40,
+    SPI_BAUDRATE_PRESCALER_128 = 0x80,
+    SPI_BAUDRATE_PRESCALER_256 = 0x100,
+} SPIBaudRatePrescaler_TypeDef;
+
+#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFFF)
+
+/** End of SPI_BaudRate_Prescaler
+  * \}
+  */
+
+#if (SPI_FIXED_FRAME_FORMAT == 0)
+/**
+ * \defgroup    SPI_Frame_Format SPI Frame Format
+ * \{
+ * \ingroup     SPI_Exported_Constants
+ */
+typedef enum
+{
+    SPI_FRAME_MOTOROLA      = 0x00,
+    SPI_FRAME_TI_SSP        = 0x01,
+    SPI_FRAME_NS_MICROWIRE  = 0x02,
+    SPI_FRAME_RESERVE       = 0x03,
+} SPIFrameFormat_TypeDef;
+
+#define IS_SPI_FRAME_FORMAT(FRAME) (((FRAME) == SPI_FRAME_MOTOROLA) || \
+                                    ((FRAME) == SPI_Frame_TI_SSP) || \
+                                    ((FRAME) == SPI_Frame_NS_MICROWIRE) || \
+                                    ((FRAME) == SPI_FRAME_RESERVE))
+
+/** End of SPI_Frame_Format
+  * \}
+  */
+#endif
+
+/**
+ * \defgroup    SPI_DMA_Transfer_Request SPI DMA Transfer Request
+ * \{
+ * \ingroup     SPI_Exported_Constants
+ */
+typedef enum
+{
+    SPI_DMA_REQ_RX = 0x01,
+    SPI_DMA_REQ_TX = 0x02,
+#if (SPI_SUPPORT_WRAP_MODE == 1)
+    SPI_WRAP_DMA_REQ_TX = 0x03,
+#endif
+} SPIDMARequests_TypeDef;
+
+#if (SPI_SUPPORT_WRAP_MODE == 0)
+#define IS_SPI_DMAREQ(REQ) (((REQ) == SPI_DMA_REQ_RX) || \
+                            ((REQ) == SPI_DMA_REQ_TX))
+#else
+#define IS_SPI_DMAREQ(REQ) (((REQ) == SPI_DMA_REQ_RX) || \
+                            ((REQ) == SPI_DMA_REQ_TX) || \
+                            ((REQ) == SPI_WRAP_DMA_REQ_TX))
+#endif
+
+/** End of SPI_DMA_Transfer_Request
+  * \}
+  */
+
+/**
+ * \defgroup    SPI_Flags SPI Flags
+ * \{
+ * \ingroup     SPI_Exported_Constants
+ */
+#define SPI_FLAG_BUSY                   BIT0
+#define SPI_FLAG_TFNF                   BIT1
+#define SPI_FLAG_TFE                    BIT2
+#define SPI_FLAG_RFNE                   BIT3
+#define SPI_FLAG_RFF                    BIT4
+#define SPI_FLAG_TXE                    BIT5
+#define SPI_FLAG_DCOL                   BIT6
+#if (SPI_SUPPORT_WRAP_MODE == 1)
+#define SPI_FLAG_WRAP_CS_EN             BIT8
+#define SPI_FLAG_WRAP_TFNF              BIT9
+#define SPI_FLAG_WRAP_TFE               BIT10
+#endif
+
+#if (SPI_SUPPORT_WRAP_MODE == 1)
+#define IS_SPI_GET_FLAG(FLAG)   (((FLAG) == SPI_FLAG_DCOL) || \
+                                 ((FLAG) == SPI_FLAG_TXE) || \
+                                 ((FLAG) == SPI_FLAG_RFF) || \
+                                 ((FLAG) == SPI_FLAG_RFNE) || \
+                                 ((FLAG) == SPI_FLAG_TFE) || \
+                                 ((FLAG) == SPI_FLAG_TFNF) || \
+                                 ((FLAG) == SPI_FLAG_BUSY) || \
+                                 ((FLAG) == SPI_FLAG_WRAP_CS_EN) || \
+                                 ((FLAG) == SPI_FLAG_WRAP_TFNF) || \
+                                 ((FLAG) == SPI_FLAG_WRAP_TFE))
+#else
+#define IS_SPI_GET_FLAG(FLAG)   (((FLAG) == SPI_FLAG_DCOL) || \
+                                 ((FLAG) == SPI_FLAG_TXE) || \
+                                 ((FLAG) == SPI_FLAG_RFF) || \
+                                 ((FLAG) == SPI_FLAG_RFNE) || \
+                                 ((FLAG) == SPI_FLAG_TFE) || \
+                                 ((FLAG) == SPI_FLAG_TFNF) || \
+                                 ((FLAG) == SPI_FLAG_BUSY))
+#endif
+
+/** End of SPI_Flags
+  * \}
+  */
+
+/**
+ * \defgroup    SPI_Interrupt SPI Interrupt
+ * \{
+ * \ingroup     SPI_Exported_Constants
+ */
+#define SPI_INT_TXE                    BIT0
+#define SPI_INT_TXO                    BIT1
+#define SPI_INT_RXU                    BIT2
+#define SPI_INT_RXO                    BIT3
+#define SPI_INT_RXF                    BIT4
+#define SPI_INT_MST                    BIT5  //only MASTER
+#define SPI_INT_FAE                    BIT5  //only SLAVE
+#define SPI_INT_TUF                    BIT6  //only SLAVE
+#define SPI_INT_RIG                    BIT7  //only SLAVE
+#if (SPI_SUPPORT_WRAP_MODE == 1)
+#define SPI_INT_WRAP_TXE               BIT8
+#define SPI_INT_WRAP_TXO               BIT9
+#define SPI_INT_WRAP_TXD               BIT10
+#endif
+
+#if (SPI_SUPPORT_WRAP_MODE == 1)
+#define IS_SPI_CONFIG_IT(IT) (((IT) == SPI_INT_TXE) || \
+                              ((IT) == SPI_INT_TXO) || \
+                              ((IT) == SPI_INT_RXU) || \
+                              ((IT) == SPI_INT_RXO) || \
+                              ((IT) == SPI_INT_RXF) || \
+                              ((IT) == SPI_INT_MST) || \
+                              ((IT) == SPI_INT_FAE) || \
+                              ((IT) == SPI_INT_TUF) || \
+                              ((IT) == SPI_INT_RIG) || \
+                              ((IT) == SPI_INT_WRAP_TXE) || \
+                              ((IT) == SPI_INT_WRAP_TXO) || \
+                              ((IT) == SPI_INT_WRAP_TXD))
+#else
+#define IS_SPI_CONFIG_IT(IT) (((IT) == SPI_INT_TXE) || \
+                              ((IT) == SPI_INT_TXO) || \
+                              ((IT) == SPI_INT_RXU) || \
+                              ((IT) == SPI_INT_RXO) || \
+                              ((IT) == SPI_INT_RXF) || \
+                              ((IT) == SPI_INT_MST) || \
+                              ((IT) == SPI_INT_FAE) || \
+                              ((IT) == SPI_INT_TUF) || \
+                              ((IT) == SPI_INT_RIG) )
+#endif
+
+/** End of SPI_Interrupt
+  * \}
+  */
+
+#if (SPI0_SUPPORT_MASTER_SLAVE == 1)
+
+/**
+ * \defgroup    SPI_mode SPI Mode
+ * \{
+ * \ingroup     SPI_Exported_Constants
+ */
+typedef enum
+{
+    SPI_MODE_MASTER = ((uint16_t)0x0104),
+    SPI_MODE_SLAVE  = ((uint16_t)0x0000)
+} SPIMode_Typedef;
+
+#define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_MASTER) || \
+                           ((MODE) == SPI_MODE_SLAVE))
+
+/** End of SPI_mode
+  * \}
+  */
+#endif
+
+#if (SPI_SUPPORT_WRAP_MODE == 1)
+/**
+ * \defgroup    SPI_Wrap_CS_Clock_Divider SPI Wrap CS Clock Divider
+ * \{
+ * \ingroup     SPI_Exported_Constants
+ */
+typedef enum
+{
+    SPI_WRAP_CS_CLOCK_DIV_1 = 0x0,
+    SPI_WRAP_CS_CLOCK_DIV_2 = 0x1,
+    SPI_WRAP_CS_CLOCK_DIV_4 = 0x2,
+    SPI_WRAP_CS_CLOCK_DIV_8 = 0x3,
+    SPI_WRAP_CS_CLOCK_DIV_16 = 0x4,
+    SPI_WRAP_CS_CLOCK_DIV_32 = 0x5,
+    SPI_WRAP_CS_CLOCK_DIV_64 = 0x6,
+    SPI_WRAP_CS_CLOCK_DIV_128 = 0x7,
+    SPI_WRAP_CS_CLOCK_DIV_256 = 0x8,
+} SPIWrapCSClockDiv_TypeDef;
+
+/** End of SPI_Wrap_CS_Clock_Divider
+  * \}
+  */
+
+#endif
+
+/**
+ * \defgroup    SPI_ActionEvent SPI Action Event
+ * \{
+ * \ingroup     SPI_Exported_Constants
+ */
+#if (SPI_SUPPORT_RAP_FUNCTION == 1)
+typedef enum
+{
+    SPI_ACTION_START  = 0,
+    SPI_EVENT_START = 1,
+    SPI_EVENT_END   = 2,
+} SPIActionEvent_TypeDef;
+#endif
+
+/** End of SPI_ActionEvent
+  * \}
+  */
+
+#if (SPI_SUPPORT_REPEAT_MODE == 1)
+/**
+ * \defgroup    SPI_Repeat_Reg_Mode SPI Repeat Register Mode
+ * \{
+ * \ingroup     SPI_Exported_Constants
+ */
+typedef enum
+{
+    SPI_REPEAT_WRAPPER_FIFO = 0x00, /*!< Repeat data output from wrapper FIFO. */
+    SPI_REPEAT_NORMAL_FIFO = 0x01,  /*!< Repeat data output from SPI data register. */
+} SPIRepeatMode_TypeDef;
+
+/** End of SPI_Repeat_Reg_Mode
+  * \}
+  */
+
+/**
+ * \defgroup    SPI_Repeat_Transfer_Size SPI Repeat Transfer Size
+ * \{
+ * \ingroup     SPI_Exported_Constants
+ */
+typedef enum
+{
+    SPI_REPEAT_SIZE_8BIT = 0x00, /*!< 8bit mode. */
+    SPI_REPEAT_SIZE_16BIT = 0x01,  /*!< 16bit mode. */
+} SPIRepeatSize_TypeDef;
+
+/** End of SPI_Repeat_Transfer_Size
+  * \}
+  */
+
+#endif
+
+/** End of SPI_Exported_Constants
+  * \}
+  */
+
+/*============================================================================*
+ *                         Types
+ *============================================================================*/
+/** \defgroup SPI_Exported_Types SPI Exported Types
+  * \brief
+  * \{
+  */
+
+/**
+ * \brief       SPI init structure definition.
+ *
+ * \ingroup     SPI_Exported_Types
+ */
+typedef struct
+{
+    SPIDirection_TypeDef SPI_Direction;        /*!< Specifies the SPI unidirectional
+                                                    or bidirectional data mode. */
+#if (SPI_SUPPORT_WRAP_MODE == 1)
+    uint32_t SPI_TXNDF;                        /*!< Specifies the trigger condition in TxOnly or FullDuplex mode.
+                                                    This parameter sets the number of data frames to be continuously transmitted,
+                                                    from 1 to 65536. */
+
+    FunctionalState SPI_CSHighActiveEn;        /*!< Specifies whether to enable CS high active.
+                                                    This parameter can be a value of ENABLE or DISABLE. */
+
+    FunctionalState SPI_WrapModeEn;            /*!< Specifies the TX waper mode (TX NDF) enable.
+                                                    Only SPI1 have txndf mode.
+                                                    ENABLE: Hardware won't automatically pull
+                                                    SPI_CSN high when TX FIFO is empty.
+                                                    DISABLE: SPI_CSN pull high when
+                                                    TX data number = SPI_TXNDF+1.*/
+
+    FunctionalState SPI_WrapModeDMAEn;      /*!< Specifies the TX waper mode(TX NDF) DMA enable. */
+
+    uint8_t  SPI_WrapTxThresholdLevel;      /*!< Specifies the wrapper transmit FIFO Threshold.
+                                                This parameter can be a value equal or less than SPI_WRAPPER_TX_FIFO_SIZE. */
+
+    uint8_t  SPI_WrapTxWaterlevel;           /*!< Specifies the TX NDF DMA tx water.
+                                                  The best value is SPI_WRAPPER_TX_FIFO_SIZE - Tx GDMA MSize. */
+
+    SPIWrapCSClockDiv_TypeDef SPI_WrapCSClockDiv;  /*!< Specifies the CS clock divider.
+                                                  This parameter can be a value of \ref SPI_Wrap_CS_Clock_Divider. */
+
+    uint8_t SPI_WrapCSHoldDlyCount;             /*!< Specifies the CS hold delay count.
+                                                     The hold delay time = cs_divider * (hold_delay_count + 2.5) * 25ns.
+                                                     This parameter can be a value from 0 to 15. */
+    uint8_t SPI_WrapCSSetupDlyCount;            /*!< Specifies the CS setup delay count.
+                                                     The setup delay time = cs_divider * (setup_delay_count + 1) * 25ns.
+                                                     This parameter can be a value from 0 to 15. */
+#endif
+
+    uint32_t SPI_RXNDF;                        /*!< Specifies the trigger condition in RxOnly or EEPROM mode.
+                                                    This parameter should be the value of the length of read data,
+                                                    from 1 to 65536. */
+
+#if (SPI0_SUPPORT_MASTER_SLAVE == 1)
+    SPIMode_Typedef           SPI_Mode;        /*!< Specifies the SPI Mode. */
+#endif
+
+    SPIDataSize_TypeDef SPI_DataSize;          /*!< Specifies the SPI data size. */
+
+    SPIClockPolarity_TypeDef SPI_CPOL;         /*!< Specifies the serial clock steady state. */
+
+    SPIClockPhase_TypeDef SPI_CPHA;            /*!< Specifies clock active edge for bit capture. */
+#if (SPI_FIXED_FRAME_FORMAT == 0)
+    SPIFrameFormat_TypeDef SPI_FrameFormat;    /*!< Specifies frame format which serial
+                                                    protocol transfers the data. */
+#endif
+    uint32_t SPI_BaudRatePrescaler;            /*!< Specifies the speed of SCK clock.
+                                                    SPI Clock Speed = clk source/SPI_ClkDIV.
+                                                    This parameter can be a value of \ref SPI_BaudRate_Prescaler.
+                                                    \note The communication clock is derived from the master clock.
+                                                    The slave clock does not need to be set. */
+
+#if (SPI_SUPPORT_SWAP == 1)
+    FunctionalState SPI_SwapTxBitEn;           /*!< Specifies whether to swap SPI Tx data bit.
+                                                    This parameter can be a value of ENABLE or DISABLE. */
+
+    FunctionalState SPI_SwapRxBitEn;           /*!< Specifies whether to swap SPI Rx data bit.
+                                                    This parameter can be a value of ENABLE or DISABLE. */
+
+    FunctionalState SPI_SwapTxByteEn;          /*!< Specifies whether to swap SPI Tx data byte.
+                                                    This parameter can be a value of ENABLE or DISABLE. */
+
+    FunctionalState SPI_SwapRxByteEn;          /*!< Specifies whether to swap SPI Rx data byte.
+                                                    This parameter can be a value of ENABLE or DISABLE. */
+#endif
+
+    FunctionalState SPI_ToggleEn;              /*!< Specifies whether to toggle when transfer done.
+                                                    This parameter can be a value of ENABLE or DISABLE. */
+
+    uint32_t SPI_TxThresholdLevel;             /*!< Specifies the transmit FIFO Threshold.
+                                                    This parameter can be a value equal or less than SPI_TX_FIFO_SIZE. */
+
+    uint32_t SPI_RxThresholdLevel;             /*!< Specifies the receive FIFO Threshold.
+                                                    This parameter can be a value equal or less than SPI_RX_FIFO_SIZE. */
+
+    FunctionalState SPI_TxDMAEn;               /*!< Specifies the Tx dma mode.
+                                                    This parameter can be a value of ENABLE or DISABLE. */
+
+    FunctionalState SPI_RxDMAEn;               /*!< Specifies the Rx dma mode.
+                                                    This parameter can be a value of ENABLE or DISABLE. */
+
+    uint8_t SPI_TxWaterlevel;                  /*!< Specifies the DMA tx water level.
+                                                    The best value is SPI_TX_FIFO_SIZE - Tx GDMA MSize. */
+
+    uint8_t SPI_RxWaterlevel;                  /*!< Specifies the DMA rx water level.
+                                                    The best value is SPI Rx DMA MSize. */
+} SPI_InitTypeDef;
+
+/** End of SPI_Exported_Types
+  * \}
+  */
+
+/*============================================================================*
+ *                         Functions
+ *============================================================================*/
+/** \defgroup SPI_Exported_Functions SPI Exported Functions
+  * \brief
+  * \{
+  */
+
+/**
+ * \brief   Deinitializes the SPIx peripheral registers to their default reset values.
+ *
+ * \param[in] SPIx: Select the SPI peripheral. \ref SPI_Declaration
+ *
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_spi_init(void)
+ * {
+ *     SPI_DeInit(SPI0);
+ * }
+ * \endcode
+ */
+void SPI_DeInit(SPI_TypeDef *SPIx);
+
+/**
+ * \brief   Initializes the SPIx peripheral according to the specified
+ *          parameters in the SPI_InitStruct.
+ *
+ * \param[in] SPIx: Select the SPI peripheral. \ref SPI_Declaration
+ * \param[in] SPI_InitStruct: Pointer to a SPI_InitTypeDef structure that
+ *            contains the configuration information for the specified SPI peripheral.
+ *
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_spi_init(void)
+ * {
+ *     RCC_ClockCmd(SPI0_CLOCK, ENABLE);
+
+ *     SPI_InitTypeDef  SPI_InitStruct;
+ *     SPI_StructInit(&SPI_InitStruct);
+ *
+ *     SPI_InitStruct.SPI_Direction   = SPI_Direction_EEPROM;
+ *     SPI_InitStruct.SPI_DataSize    = SPI_DataSize_8b;
+ *     SPI_InitStruct.SPI_CPOL        = SPI_CPOL_High;
+ *     SPI_InitStruct.SPI_CPHA        = SPI_CPHA_2Edge;
+ *     SPI_InitStruct.SPI_BaudRatePrescaler  = 100;
+ *     SPI_InitStruct.SPI_RxThresholdLevel  = 1 - 1;
+ *     SPI_InitStruct.SPI_NDF               = 1 - 1;
+ *     SPI_InitStruct.SPI_FrameFormat = SPI_Frame_Motorola;
+ *
+ *     SPI_Init(SPI0, &SPI_InitStruct);
+ * }
+ * \endcode
+ */
+void SPI_Init(SPI_TypeDef *SPIx, SPI_InitTypeDef *SPI_InitStruct);
+
+/**
+ * \brief  Fills each SPI_InitStruct member with its default value.
+ *
+ * \param[in]  SPI_InitStruct: Pointer to a SPI_InitTypeDef structure which will be initialized.
+ *
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_spi_init(void)
+ * {
+ *
+ *     RCC_ClockCmd(SPI0_CLOCK, ENABLE);
+
+ *     SPI_InitTypeDef  SPI_InitStruct;
+ *     SPI_StructInit(&SPI_InitStruct);
+ *
+ *     SPI_InitStruct.SPI_Direction   = SPI_Direction_EEPROM;
+ *     SPI_InitStruct.SPI_DataSize    = SPI_DataSize_8b;
+ *     SPI_InitStruct.SPI_CPOL        = SPI_CPOL_High;
+ *     SPI_InitStruct.SPI_CPHA        = SPI_CPHA_2Edge;
+ *     SPI_InitStruct.SPI_BaudRatePrescaler  = 100;
+ *     SPI_InitStruct.SPI_RxThresholdLevel  = 1 - 1;
+ *     SPI_InitStruct.SPI_NDF               = 1 - 1;
+ *     SPI_InitStruct.SPI_FrameFormat = SPI_Frame_Motorola;
+ *
+ *     SPI_Init(SPI0, &SPI_InitStruct);
+ * }
+ * \endcode
+ */
+void SPI_StructInit(SPI_InitTypeDef *SPI_InitStruct);
+
+/**
+ * \brief  Enables or disables the selected SPI peripheral.
+ *
+ * \param[in] SPIx: Select the SPI peripheral. \ref SPI_Declaration
+ * \param[in] NewState: New state of the SPIx peripheral.
+ *            This parameter can be: ENABLE or DISABLE.
+ *
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_spi_init(void)
+ * {
+ *
+ *     RCC_ClockCmd(SPI0_CLOCK, ENABLE);
+ *
+ *     SPI_InitTypeDef  SPI_InitStruct;
+ *     SPI_StructInit(&SPI_InitStruct);
+ *
+ *     SPI_InitStruct.SPI_Direction   = SPI_Direction_EEPROM;
+ *     SPI_InitStruct.SPI_DataSize    = SPI_DataSize_8b;
+ *     SPI_InitStruct.SPI_CPOL        = SPI_CPOL_High;
+ *     SPI_InitStruct.SPI_CPHA        = SPI_CPHA_2Edge;
+ *     SPI_InitStruct.SPI_BaudRatePrescaler  = 100;
+ *     SPI_InitStruct.SPI_RxThresholdLevel  = 1 - 1;
+ *     SPI_InitStruct.SPI_NDF               = 1 - 1;
+ *     SPI_InitStruct.SPI_FrameFormat = SPI_Frame_Motorola;
+ *
+ *     SPI_Init(SPI0, &SPI_InitStruct);
+ *     SPI_Cmd(SPI0, ENABLE);
+ * }
+ * \endcode
+ */
+void SPI_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState);
+
+/**
+ * \brief  Transmits a number of bytes through the SPIx peripheral.
+ *
+ * \param[in] SPIx: Select the SPI peripheral. \ref SPI_Declaration
+ * \param[in] pBuf: Bytes to be transmitted.
+ * \param[in] len: Byte length to be transmitted.
+ *
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void spi_demo(void)
+ * {
+ *     uint8_t data_buf[] = {0x01,0x02,0x03};
+ *     SPI_SendBuffer(SPI0, data_buf, sizeof(data_buf));
+ * }
+ * \endcode
+ */
+void SPI_SendBuffer(SPI_TypeDef *SPIx, uint8_t *pBuf, uint16_t len);
+
+/**
+ * \brief  Transmits a number of bytes through the SPIx peripheral without polling.
+ *
+ * \param[in] SPIx: Select the SPI peripheral \ref SPI_Declaration.
+ * \param[in] pBuf: Bytes to be transmitted.
+ * \param[in] len: Byte length to be transmitted.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void spi_demo(void)
+ * {
+ *     uint8_t data_buf[] = {0x01,0x02,0x03};
+ *     SPI_SendBufferDirect(SPI0, data_buf, sizeof(data_buf));
+ * }
+ * \endcode
+ */
+void SPI_SendBufferDirect(SPI_TypeDef *SPIx, uint8_t *pBuf, uint16_t len);
+
+/**
+ * \brief  Transmits a number of halfWords through the SPIx peripheral.
+ *
+ * \param[in] SPIx: Select the SPI peripheral. \ref SPI_Declaration
+ * \param[in] pBuf: Halfwords to be transmitted.
+ * \param[in] len: Halfwords length to be transmitted.
+ *
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void spi_demo(void)
+ * {
+ *     uint16_t data_buf[] = {0x0102,0x0203,0x0304};
+ *     SPI_SendHalfWord(SPI0, data_buf, sizeof(data_buf)/sizeof(uint16_t));
+ * }
+ * \endcode
+  */
+void SPI_SendHalfWord(SPI_TypeDef *SPIx, uint16_t *pBuf, uint16_t len);
+
+/**
+ * \brief  Transmits a number of halfWords through the SPIx peripheral without polling.
+ *
+ * \param[in] SPIx: Select the SPI peripheral \ref SPI_Declaration.
+ * \param[in] pBuf: Halfwords to be transmitted.
+ * \param[in] len: Halfwords length to be transmitted.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void spi_demo(void)
+ * {
+ *     uint16_t data_buf[] = {0x0102,0x0203,0x0304};
+ *     SPI_SendHalfWordDirect(SPI0, data_buf, sizeof(data_buf)/sizeof(uint16_t));
+ * }
+ * \endcode
+  */
+void SPI_SendHalfWordDirect(SPI_TypeDef *SPIx, uint16_t *pBuf, uint16_t len);
+
+/**
+ * \brief  Transmits a number of words through the SPIx peripheral.
+ *
+ * \param[in] SPIx: Select the SPI peripheral. \ref SPI_Declaration
+ * \param[in] pBuf: Words to be transmitted.
+ * \param[in] len: Word length to be transmitted.
+ *
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void spi_demo(void)
+ * {
+ *     uint32_t data_buf[] = {0x01020304,0x02030405,0x03040506};
+ *     SPI_SendWord(SPI0, data_buf, sizeof(data_buf)/sizeof(uint32_t));
+ * }
+ * \endcode
+ */
+void SPI_SendWord(SPI_TypeDef *SPIx, uint32_t *pBuf, uint16_t len);
+
+/**
+ * \brief  Transmits a number of words through the SPIx peripheral without polling.
+ *
+ * \param[in] SPIx: Select the SPI peripheral \ref SPI_Declaration.
+ * \param[in] pBuf: Words to be transmitted.
+ * \param[in] len: Word length to be transmitted.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void spi_demo(void)
+ * {
+ *     uint32_t data_buf[] = {0x01020304,0x02030405,0x03040506};
+ *     SPI_SendWordDirect(SPI0, data_buf, sizeof(data_buf)/sizeof(uint32_t));
+ * }
+ * \endcode
+ */
+void SPI_SendWordDirect(SPI_TypeDef *SPIx, uint32_t *pBuf, uint16_t len);
+
+/**
+ * \brief  Enable or disable the specified SPI interrupt source.
+ *
+ * \param[in] SPIx: Select the SPI peripheral. \ref SPI_Declaration
+ * \param[in] SPI_IT: Specifies the SPI interrupt source to be enabled or disabled.
+ *            This parameter can be one of the following values:
+ *            \arg SPI_INT_TXE: Transmit FIFO empty interrupt.
+ *            \arg SPI_INT_TXO: Transmit FIFO overflow interrupt.
+ *            \arg SPI_INT_RXU: Receive FIFO underflow interrupt.
+ *            \arg SPI_INT_RXO: Receive FIFO overflow interrupt.
+ *            \arg SPI_INT_RXF: Receive FIFO full interrupt.
+ *            \arg SPI_INT_MST: Multi-Master Contention Interrupt.
+ *            \arg SPI_INT_FAE: TX Frame Alignment interrupt.
+ *            \arg SPI_INT_TUF: Transmit FIFO underflow interrupt.
+ *            \arg SPI_INT_RIG: Rising edge detect interrupt.
+ * \param[in] NewState: New state of the specified SPI interrupt source.
+ *            This parameter can be: ENABLE or DISABLE.
+ *
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void spi_demo(void)
+ * {
+ *     SPI_INTConfig(SPI0, SPI_INT_RXF, ENABLE);
+ * }
+ * \endcode
+ */
+void SPI_INTConfig(SPI_TypeDef *SPIx, uint16_t SPI_IT, FunctionalState NewState);
+
+/**
+ * \brief  Clear the specified SPI interrupt pending bit.
+ *
+ * \param[in] SPIx: Select the SPI peripheral. \ref SPI_Declaration
+ * \param[in] SPI_IT: Specifies the SPI interrupt to clear.
+ *            This parameter can be one of the following values:
+ *            \arg SPI_INT_TXO: Transmit FIFO Overflow Interrupt.
+ *            \arg SPI_INT_RXO: Receive FIFO Overflow Interrupt.
+ *            \arg SPI_INT_RXU: Receive FIFO Underflow Interrupt.
+ *            \arg SPI_INT_MST: Multi-Master Contention Interrupt.
+ *            \arg SPI_INT_FAE: TX Frame Alignment Interrupt.
+ *            \arg SPI_INT_TUF: Transmit FIFO Underflow Interrupt.
+ *            \arg SPI_INT_RIG: Rising edge detect Interrupt.
+ *
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void spi_demo(void)
+ * {
+ *     SPI_ClearINTPendingBit(SPI0, SPI_INT_RXF);
+ * }
+ * \endcode
+ */
+void SPI_ClearINTPendingBit(SPI_TypeDef *SPIx, uint16_t SPI_IT);
+
+/**
+ * \brief  Transmits a data through the SPIx peripheral.
+ *
+ * \param[in] SPIx: Select the SPI peripheral. \ref SPI_Declaration
+ * \param[in] Data: Data to be transmitted.
+ *
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void spi_demo(void)
+ * {
+ *     uint32_t data = 0x01020304;
+ *     SPI_SendData(SPI0, data);
+ * }
+ * \endcode
+ */
+void SPI_SendData(SPI_TypeDef *SPIx, uint32_t Data);
+
+/**
+ * \brief   Received data by the SPI peripheral.
+ *
+ * \param[in] SPIx: Select the SPI peripheral. \ref SPI_Declaration
+ *
+ * \return  The most recent received data.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void spi_demo(void)
+ * {
+ *     uint32_t data = SPI_ReceiveData(SPI0);
+ * }
+ * \endcode
+ */
+uint32_t SPI_ReceiveData(SPI_TypeDef *SPIx);
+
+/**
+ * \brief   Get data length in Tx FIFO through the SPIx peripheral.
+ *
+ * \param[in] SPIx: Select the SPI peripheral. \ref SPI_Declaration
+ *
+ * \return  Data length in Tx FIFO.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void spi_demo(void)
+ * {
+ *     uint8_t data_len = SPI_GetTxFIFOLen(SPI0);
+ * }
+ * \endcode
+ */
+uint8_t SPI_GetTxFIFOLen(SPI_TypeDef *SPIx);
+
+/**
+ * \brief   Get data length in Rx FIFO through the SPIx peripheral.
+ *
+ * \param[in] SPIx: Select the SPI peripheral. \ref SPI_Declaration
+ *
+ * \return  Data length in Rx FIFO.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void spi_demo(void)
+ * {
+ *     uint8_t data_len = SPI_GetRxFIFOLen(SPI0);
+ * }
+ * \endcode
+ */
+uint8_t SPI_GetRxFIFOLen(SPI_TypeDef *SPIx);
+
+/**
+ * \brief   Change SPI direction mode.
+ *
+ * \param[in] SPIx: Select the SPI peripheral. \ref SPI_Declaration
+ * \param[in] dir: Value of direction mode.
+ *
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void spi_demo(void)
+ * {
+ *     SPI_SetDirection(SPI0, SPI_Direction_EEPROM);
+ * }
+ * \endcode
+ */
+void SPI_SetDirection(SPI_TypeDef *SPIx, uint16_t dir);
+
+/**
+ * \brief   Set read Data length only in EEPROM mode through the SPIx peripheral,which
+            enables you to receive up to 64 KB of data in a continuous transfer.
+ *
+ * \param[in] SPIx: Select the SPI peripheral. \ref SPI_Declaration
+ * \param[in] len: Length of read data which can be 1 to 65536.
+ *
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void spi_demo(void)
+ * {
+ *     SPI_SetReadLen(SPI0, 100);
+ * }
+ * \endcode
+ */
+void SPI_SetReadLen(SPI_TypeDef *SPIx, uint16_t len);
+
+/**
+ * \brief   Set cs number through the SPIx peripheral.
+ *
+ * \param[in] SPIx: Select the SPI peripheral. \ref SPI_Declaration
+ * \param[in] number: Number can be 0 to 2.
+ *
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void spi_demo(void)
+ * {
+ *     SPI_SetCSNumber(SPI1, 1);
+ * }
+ * \endcode
+ */
+void SPI_SetCSNumber(SPI_TypeDef *SPIx, uint8_t number);
+
+/**
+ * \brief  Check whether the specified SPI interrupt is set.
+ *
+ * \param[in] SPIx: Select the SPI peripheral. \ref SPI_Declaration
+ * \param[in] SPI_IT: Specifies the SPI interrupt to check.
+ *            This parameter can be one of the following values:
+ *            \arg SPI_INT_MST: Multi-Master Contention Interrupt.
+ *            \arg SPI_INT_FAE: TX Frame Alignment Interrupt.
+ *            \arg SPI_INT_RXF: Receive FIFO Full Interrupt.
+ *            \arg SPI_INT_RXO: Receive FIFO Overflow Interrupt.
+ *            \arg SPI_INT_RXU: Receive FIFO Underflow Interrupt.
+ *            \arg SPI_INT_TXO: Transmit FIFO Overflow Interrupt .
+ *            \arg SPI_INT_TXE: Transmit FIFO Empty Interrupt.
+ *            \arg SPI_INT_WRAP_TXE: TX NDF mode FIFO Transmit FIFO Empty Interrupt.
+ *            \arg SPI_INT_WRAP_TXO: TX NDF mode FIFO Overflow Interrupt.
+ *            \arg SPI_INT_WRAP_TXD: TX NDF mode transmit done Interrupt.
+ *
+ * \return The new state of SPI_IT (SET or RESET).
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void spi_demo(void)
+ * {
+ *     ITStatus int_status = SPI_GetINTStatus(SPI0, SPI_INT_RXF);
+ * }
+ * \endcode
+ */
+ITStatus SPI_GetINTStatus(SPI_TypeDef *SPIx, uint32_t SPI_IT);
+
+/**
+ * \brief  Check whether the specified SPI flag is set.
+ *
+ * \param[in] SPIx: Select the SPI peripheral. \ref SPI_Declaration
+ * \param[in] SPI_FLAG: Specifies the SPI flag to check.
+ *            This parameter can be one of the following values:
+ *            \arg SPI_FLAG_DCOL: Data Collision Error flag.Set if it is actively transmitting in master mode when another master selects this device as a slave.
+ *            \arg SPI_FLAG_TXE: Transmission error flag.Set if the transmit FIFO is empty when a transfer is started in slave mode.
+ *            \arg SPI_FLAG_RFF: Receive FIFO full flag. Set if the receive FIFO is completely full.
+ *            \arg SPI_FLAG_RFNE: Receive FIFO Not Empty flag.Set if receive FIFO is not empty.
+ *            \arg SPI_FLAG_TFE: Transmit FIFO Empty flag.Set if transmit FIFO is empty.
+ *            \arg SPI_FLAG_TFNF: Transmit FIFO Not Full flag.Set if transmit FIFO is not full.
+ *            \arg SPI_FLAG_BUSY: SPI Busy flag.Set if it is actively transferring data.reset if it is idle or disabled.
+ *            \arg SPI_FLAG_TXNDF_BUSY: TX NDF mode Busy flag.
+ *            \arg SPI_FLAG_TXNDF_TFNF: TX NDF mode FIFO Not Full flag.
+ *            \arg SPI_FLAG_TXNDF_TFE: TX NDF mode FIFO Empty flag.
+ *
+ * \return The new state of SPI_FLAG (SET or RESET).
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void spi_demo(void)
+ * {
+ *     FlagStatus flag_status = SPI_GetFlagState(SPI0, SPI_FLAG_TXE);
+ *
+ * }
+ * \endcode
+ */
+FlagStatus SPI_GetFlagState(SPI_TypeDef *SPIx, uint16_t SPI_FLAG);
+
+/**
+ * \brief   Enables or disables the SPIx DMA interface.
+ *
+ * \param[in] SPIx: Select the SPI peripheral. \ref SPI_Declaration
+ * \param[in] SPI_DMAReq: Specifies the SPI DMA transfer request to be enabled or disabled.
+ *            This parameter can be one of the following values:
+ *            \arg SPI_DMAReq_Tx: Tx buffer DMA transfer request.
+ *            \arg SPI_DMAReq_Rx: Rx buffer DMA transfer request.
+ * \param[in] NewState: New state of the selected SPI DMA transfer request.
+ *            This parameter can be: ENABLE or DISABLE.
+ *
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void spi_demo(void)
+ * {
+ *     SPI_DMACmd(SPI0, SPI_DMAReq_Tx, ENABLE);
+ * }
+ * \endcode
+ */
+void SPI_DMACmd(SPI_TypeDef *SPIx, SPIDMARequests_TypeDef SPI_DMAReq,
+                FunctionalState NewState);
+
+/**
+ * \brief  Change SPI speed daynamically.
+ *
+ * \param[in] SPIx: Select the SPI peripheral. \ref SPI_Declaration
+ * \param[in] precalser: Value of prescaler.
+ *            This parameter can be one of the following values:
+ *            \arg  SPI_BaudRatePrescaler_2
+ *            \arg  SPI_BaudRatePrescaler_4
+ *            \arg  SPI_BaudRatePrescaler_6
+ *            \arg  SPI_BaudRatePrescaler_8
+ *            \arg  SPI_BaudRatePrescaler_10
+ *            \arg  SPI_BaudRatePrescaler_12
+ *            \arg  SPI_BaudRatePrescaler_14
+ *            \arg  SPI_BaudRatePrescaler_16
+ *            \arg  SPI_BaudRatePrescaler_32
+ *            \arg  SPI_BaudRatePrescaler_64
+ *            \arg  SPI_BaudRatePrescaler_128
+ *            \arg  SPI_BaudRatePrescaler_256
+ *
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void spi_demo(void)
+ * {
+ *     SPI_SetPrescaler(SPI0, SPI_BaudRatePrescaler_2);
+ * }
+ * \endcode
+ */
+void SPI_SetPrescaler(SPI_TypeDef *SPIx, uint32_t prescaler);
+
+/**
+ * \brief   Set SPI Rx sample delay.
+ *
+ * \param[in] SPIx: Select the SPI peripheral. \ref SPI_Declaration
+ * \param[in] delay: This parameter can be 0 to 255.
+ *
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void spi_demo(void)
+ * {
+ *     SPI_SetRxSampleDly(SPI0, 1);
+ * }
+ * \endcode
+ */
+void SPI_SetRxSampleDly(SPI_TypeDef *SPIx, uint32_t delay);
+
+#if (SPI_SUPPORT_WRAP_MODE == 1)
+
+/**
+ * \brief   Enables or disables the specified SPI wrap mode start transfer.
+ *
+ * \param[in] SPIx: Select the SPI peripheral. \ref SPI_Declaration
+ * \param[in] NewState: new state of the SPIx peripheral.
+ *            This parameter can be: ENABLE or DISABLE.
+ *
+ * \return  None
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void spi_demo(void)
+ * {
+ *     SPI_WrapModeStartTx(SPI0, ENABLE);
+ * }
+ * \endcode
+ */
+void SPI_WrapModeStartTx(SPI_TypeDef *SPIx, FunctionalState NewState);
+
+/**
+ * \brief   Whether inverse CS active polarity.
+ *
+ * \param[in] SPIx: Select the SPI peripheral. \ref SPI_Declaration
+ * \param[in] NewState: new state of the SPIx peripheral.
+ *            This parameter can be one of the following values:
+ *            \arg  ENABLE: Inverse CS active polarity, which means CS is low active.
+ *            \arg  DISABLE: Not inverse CS active polarity, which means CS is high active.
+ *
+ * \return  None
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void spi_demo(void)
+ * {
+ *     SPI_InverseCSActivePolarity(SPI0, ENABLE);
+ * }
+ * \endcode
+ */
+void SPI_InverseCSActivePolarity(SPI_TypeDef *SPIx, FunctionalState NewState);
+
+/**
+ * \brief   Whether drive MOSI low in idle state.
+ *
+ * \param[in] SPIx: Select the SPI peripheral. \ref SPI_Declaration
+ * \param[in] NewState: new state of the SPIx peripheral.
+ *            This parameter can be one of the following values:
+ *            \arg  ENABLE: Drive MOSI low in idle state.
+ *            \arg  DISABLE: Not drive MOSI low in idle state, which means MOSI is Hi-Z in idle state.
+ *
+ * \return  None
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void spi_demo(void)
+ * {
+ *     SPI_DriveMOSILow(SPI0, ENABLE);
+ * }
+ * \endcode
+ */
+void SPI_DriveMOSILow(SPI_TypeDef *SPIx, FunctionalState NewState);
+
+/**
+ * \brief   Whether enable MOSI pull in idle state.
+ *
+ * \param[in] SPIx: Select the SPI peripheral. \ref SPI_Declaration
+ * \param[in] NewState: new state of the SPIx peripheral.
+ *            This parameter can be one of the following values:
+ *            \arg  ENABLE: MOSI is pull down in idle state.
+ *            \arg  DISABLE: MOSI is pull none in idle state.
+ *
+ * \return  None
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void spi_demo(void)
+ * {
+ *     SPI_PullMOSIEn(SPI0, ENABLE);
+ * }
+ * \endcode
+ */
+void SPI_PullMOSIEn(SPI_TypeDef *SPIx, FunctionalState NewState);
+
+void SPI_WrapModeSetTxNdf(SPI_TypeDef *SPIx, uint16_t tx_ndf);
+
+void SPI_WrapModeResetTxFIFO(SPI_TypeDef *SPIx);
+#endif
+
+#if SPI_SUPPORT_CLOCK_SOURCE_CONFIG
+/**
+  * \brief  SPI clock config.
+  * \param  SPIx: Select the SPI peripheral. \ref SPI_Declaration
+  * \param  ClockSrc: specifies the clock source to gates its clock.
+  * \param  ClockDiv: specifies the clock divide to gates its clock.
+  * \return None
+  */
+void SPI_SetClock(SPI_TypeDef *SPIx, SPIClockSrc_TypeDef ClockSrc, SPIClockDiv_TypeDef ClockDiv);
+#endif
+
+#if (SPI_SUPPORT_RAP_FUNCTION == 1)
+
+void SPI_RAPModeCmd(SPI_TypeDef *SPIx, FunctionalState NewState);
+
+void SPI_SetActionCmdNum(SPI_TypeDef *SPIx, uint8_t num);
+
+void SPI_SetActionWaitNum(SPI_TypeDef *SPIx, uint16_t num);
+
+void SPI_SetActionTransferNum(SPI_TypeDef *SPIx, uint16_t num);
+
+void SPI_ActionTrigger(SPI_TypeDef *SPIx, uint32_t task);
+
+bool SPI_ActionEventStsCheck(SPI_TypeDef *SPIx, uint32_t te);
+
+void SPI_ActionEventStsClear(SPI_TypeDef *SPIx, uint32_t te);
+
+void SPI_SetActionTransfer(SPI_TypeDef *SPIx, uint8_t cmd_len, uint16_t wati_cnt,
+                           uint16_t dummy_len);
+
+#endif
+
+#if (SPI_SUPPORT_AUTO_CLOCK == 1)
+
+void SPI_ClockAutoModeCmd(SPI_TypeDef *SPIx, FunctionalState Newstate);
+
+#endif
+
+#if (SPI_SUPPORT_REPEAT_MODE == 1)
+
+void SPI_SetRepeatMode(SPI_TypeDef *SPIx, SPIRepeatMode_TypeDef mode);
+void SPI_SetRepeatSize(SPI_TypeDef *SPIx, SPIRepeatSize_TypeDef size);
+void SPI_SendRepeatData(SPI_TypeDef *SPIx, uint32_t data_l, uint32_t data_h);
+
+#endif
+
+/** End of SPI_Exported_Functions
+  * \}
+  */
+
+/** End of SPI
+  * \}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RTL_SPI_H */
+
+
+
+
diff --git a/bee/drivers/spi/src/CMakeLists.txt b/bee/drivers/spi/src/CMakeLists.txt
new file mode 100644
index 00000000..dd5e359a
--- /dev/null
+++ b/bee/drivers/spi/src/CMakeLists.txt
@@ -0,0 +1,4 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+add_subdirectory(device)
diff --git a/bee/drivers/spi/src/device/CMakeLists.txt b/bee/drivers/spi/src/device/CMakeLists.txt
new file mode 100644
index 00000000..390b5305
--- /dev/null
+++ b/bee/drivers/spi/src/device/CMakeLists.txt
@@ -0,0 +1,11 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+if(CONFIG_REALTEK_BEE_COMMON_DRIVER)
+    file(GLOB BEE_DRIVER_COMMON_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/rtl_common/*.c")
+    zephyr_library_sources(${BEE_DRIVER_COMMON_SOURCES})
+endif()
+
+add_soc_series_subdir(rtl8752h)
+add_soc_series_subdir(rtl87x2g)
+add_soc_series_subdir(rtl87x2j)
diff --git a/bee/drivers/spi/src/device/rtl8752h/rtl876x_spi.c b/bee/drivers/spi/src/device/rtl8752h/rtl876x_spi.c
new file mode 100644
index 00000000..927240be
--- /dev/null
+++ b/bee/drivers/spi/src/device/rtl8752h/rtl876x_spi.c
@@ -0,0 +1,428 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "rtl876x_spi.h"
+#include "rtl876x_rcc.h"
+#include "app_section.h"
+
+/**
+  * @brief  Deinitializes the SPIx peripheral registers to their default reset values.
+  * @param  SPIx: where x can be 0 or 1 to select the SPI peripheral.
+  * @retval None
+  */
+void SPI_DeInit(SPI_TypeDef *SPIx)
+{
+    /* Check the parameters */
+    assert_param(IS_SPI_ALL_PERIPH(SPIx));
+
+    /*Disable SPI clock */
+    if (SPIx == SPI0)
+    {
+        RCC_PeriphClockCmd(APBPeriph_SPI0, APBPeriph_SPI0_CLOCK, DISABLE);
+    }
+    else
+    {
+        RCC_PeriphClockCmd(APBPeriph_SPI1, APBPeriph_SPI1_CLOCK, DISABLE);
+    }
+}
+
+/**
+  * @brief  Initializes the SPIx peripheral according to the specified
+  *   parameters in the SPI_InitStruct.
+  * @param  SPIx: where x can be 0 or 1 to select the SPI peripheral.
+  * @param  SPI_InitStruct: pointer to a SPI_InitTypeDef structure that
+  *   contains the configuration information for the specified SPI peripheral.
+  * @retval None
+  */
+void SPI_Init(SPI_TypeDef *SPIx, SPI_InitTypeDef *SPI_InitStruct)
+{
+    /* Check the parameters */
+    assert_param(IS_SPI_ALL_PERIPH(SPIx));
+
+    /* Check the SPI parameters */
+    assert_param(IS_SPI_DIRECTION_MODE(SPI_InitStruct->SPI_Direction));
+    assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode));
+    assert_param(IS_SPI_DATASIZE(SPI_InitStruct->SPI_DataSize));
+    assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL));
+    assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA));
+    assert_param(IS_SPI_FRAME_FORMAT(SPI_InitStruct->SPI_FrameFormat));
+
+    /* Disable SPI device before change configuration */
+    SPIx->SSIENR &= ~0x01;
+
+    /* Configure SPI0 mode if select SPI0 */
+    if (SPIx == SPI0)
+    {
+        if (SPI_InitStruct->SPI_Mode == SPI_Mode_Master)
+        {
+            /*Enable SPI0 master mode*/
+            *((volatile uint32_t *)0x40000308) = *((volatile uint32_t *)0x40000308) | BIT(0);
+            /* configure SPI parameters */
+            SPIx->CTRLR0 = (SPI_InitStruct->SPI_DataSize << 16)
+                           | (SPI_InitStruct->SPI_FrameFormat << 4)
+                           | (SPI_InitStruct->SPI_CPHA << 6)
+                           | (SPI_InitStruct->SPI_CPOL << 7)
+                           | (SPI_InitStruct->SPI_Direction << 8)
+//                           | (SPI_InitStruct->SPI_SwapTxBitEn << 22)
+//                           | (SPI_InitStruct->SPI_SwapRxBitEn << 24)
+//                           | (SPI_InitStruct->SPI_SwapTxByteEn << 21)
+//                           | (SPI_InitStruct->SPI_SwapRxByteEn << 23)
+                           | (SPI_InitStruct->SPI_ToggleEn << 31);
+        }
+        else
+        {
+            /*Enable SPI0 slave mode*/
+            *((volatile uint32_t *)0x40000308) = *((volatile uint32_t *)0x40000308) & (~(BIT(0)));
+            /* configure SPI parameters */
+            SPIx->CTRLR0 = (SPI_InitStruct->SPI_DataSize)
+                           | (SPI_InitStruct->SPI_FrameFormat << 4)
+                           | (SPI_InitStruct->SPI_CPHA << 6)
+                           | (SPI_InitStruct->SPI_CPOL << 7)
+                           | (SPI_InitStruct->SPI_Direction << 8)
+//                           | (SPI_InitStruct->SPI_SwapTxBitEn << 22)
+//                           | (SPI_InitStruct->SPI_SwapRxBitEn << 24)
+//                           | (SPI_InitStruct->SPI_SwapTxByteEn << 21)
+//                           | (SPI_InitStruct->SPI_SwapRxByteEn << 23)
+                           | (SPI_InitStruct->SPI_ToggleEn << 31);
+        }
+    }
+    else if (SPIx == SPI1)
+    {
+        /* configure SPI parameters */
+        SPIx->CTRLR0 = (SPI_InitStruct->SPI_DataSize << 16)
+                       | (SPI_InitStruct->SPI_FrameFormat << 4)
+                       | (SPI_InitStruct->SPI_CPHA << 6)
+                       | (SPI_InitStruct->SPI_CPOL << 7)
+                       | (SPI_InitStruct->SPI_Direction << 8)
+                       | (SPI_InitStruct->SPI_ToggleEn << 24);
+    }
+
+    /* configure SPI clock speed  in master mode or  enable slave output in slave mode */
+    if (SPI_InitStruct->SPI_Mode == SPI_Mode_Master)
+    {
+        SPIx->BAUDR = (SPI_InitStruct->SPI_BaudRatePrescaler) % 0xFFFF;
+        /* Enable slave Select function in master mode */
+        SPIx->SER |= BIT(0);
+    }
+    else
+    {
+        /* Enable slave output */
+        SPIx->CTRLR0 &= ~(BIT(10));
+    }
+
+    /*set SPI Tx and Rx threshold level ,below this level or equal this level would trigger Tx and Rx FIFO empty interrupt */
+    SPIx->TXFTLR = SPI_InitStruct->SPI_TxThresholdLevel;
+    SPIx->RXFTLR = SPI_InitStruct->SPI_RxThresholdLevel;
+
+    /* mask SPI interrupt in REG_DW_SSI_IMR */
+    SPIx->IMR = 0;
+
+    /* set read length in SPI EEPROM & rx only mode */
+    if ((SPI_InitStruct->SPI_Direction == 0x02) || (SPI_InitStruct->SPI_Direction == 0x03))
+    {
+        SPIx->CTRLR1 = SPI_InitStruct->SPI_NDF;
+    }
+#if 1
+
+    /* Config SPI dma mode */
+    SPIx->DMACR = ((SPI_InitStruct->SPI_RxDmaEn)\
+                   | ((SPI_InitStruct->SPI_TxDmaEn) << 1));
+
+    /* Config SPI waterlevel */
+    SPIx->DMARDLR = SPI_InitStruct->SPI_RxWaterlevel;
+    SPIx->DMATDLR = SPI_InitStruct->SPI_TxWaterlevel;
+#endif
+}
+
+/**
+  * @brief  Fills each SPI_InitStruct member with its default value.
+  * @param  SPI_InitStruct : pointer to a SPI_InitTypeDef structure which will be initialized.
+  * @retval None
+  */
+void SPI_StructInit(SPI_InitTypeDef *SPI_InitStruct)
+{
+    SPI_InitStruct->SPI_Mode              = SPI_Mode_Master;
+    SPI_InitStruct->SPI_DataSize          = SPI_DataSize_8b;    /* 8-bit serial data transfer */
+    SPI_InitStruct->SPI_FrameFormat       = 0;                  /* 0:FRF_MOTOROLA_SPI; 1,2,3:Reserved */
+    SPI_InitStruct->SPI_Direction         =
+        0;                  /* 0:TX and RX Mode; 1:TX Only Mode; 2:RX Only Mode;
+                                                                   3:EEPROM Read Mode */
+    SPI_InitStruct->SPI_CPOL              =
+        1;                  /* 0:inactive state of clock is low; 1:inactive
+                                                                   state of clock is high */
+    SPI_InitStruct->SPI_CPHA              =
+        1;                  /* 1:Serial clock toggles in first of first data bit;
+                                                                   0:Serial clock toggles in middle of first data bit*/
+    SPI_InitStruct->SPI_BaudRatePrescaler =
+        SPI_BaudRatePrescaler_128;             /* Speed = SPI Clock source/ SPI_ClkDIV*/
+    SPI_InitStruct->SPI_TxThresholdLevel  = 1;                  /* Transmit FIFO Threshold */
+    SPI_InitStruct->SPI_RxThresholdLevel  = 0;                  /* Receive FIFO Threshold */
+    SPI_InitStruct->SPI_NDF               = 1;
+//    SPI_InitStruct->SPI_SwapRxBitEn       = SPI_SWAP_DISABLE;       /* reverse the rx bit or not */
+//    SPI_InitStruct->SPI_SwapTxBitEn       = SPI_SWAP_DISABLE;
+//    SPI_InitStruct->SPI_SwapRxByteEn      = SPI_SWAP_DISABLE;
+//    SPI_InitStruct->SPI_SwapTxByteEn      = SPI_SWAP_DISABLE;
+    SPI_InitStruct->SPI_ToggleEn          = DISABLE;
+
+    SPI_InitStruct->SPI_RxDmaEn           = DISABLE;
+    SPI_InitStruct->SPI_TxDmaEn           = DISABLE;
+    SPI_InitStruct->SPI_RxWaterlevel      =
+        1;                   /* SPI Rx waterlevel, should be less than fifo threshold, the best value is
+                                                                    GDMA Msize */
+    SPI_InitStruct->SPI_TxWaterlevel      =
+        35;                  /* SPI Tx waterlevel, should be less than fifo threshold, the best value is
+                                                                    SPI FIFO Depth minus GDMA Msize */
+}
+
+/**
+  * @brief  Enables or disables the specified SPI peripheral.
+  * @param  SPIx: where x can be 0 or 1 to select the SPI peripheral.
+  * @param  NewState: new state of the SPIx peripheral.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void SPI_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_SPI_ALL_PERIPH(SPIx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (NewState != DISABLE)
+    {
+        /* Enable the selected SPI peripheral */
+        SPIx->SSIENR |= 0x01;
+    }
+    else
+    {
+        /* Disable the selected SPI peripheral */
+        SPIx->SSIENR &= ~0x01;
+    }
+}
+
+/**
+  * @brief  Transmits a number of bytes through the SPIx peripheral.
+  * @param  SPIx: where x can be 0 or 1 to select the SPI peripheral.
+  * @param  pBuf: Bytes to be transmitted.
+  * @param  len: Byte length to be transmitted.
+  * @retval None
+  */
+void SPI_SendBuffer(SPI_TypeDef *SPIx, uint8_t *pBuf, uint16_t len)
+{
+    uint16_t i = 0;
+
+    /* Check the parameters */
+    assert_param(IS_SPI_ALL_PERIPH(SPIx));
+
+    for (i = 0; i < len; i++)
+    {
+        SPIx->DR[0] = (*pBuf++);
+        /*read TFNF bit status in SR register: SET is Tx FIFO is not full*/
+        while (!(SPIx->SR & BIT(1)));
+    }
+}
+
+/**
+  * @brief  Transmits a number of words through the SPIx peripheral.
+  * @param  SPIx: where x can be 0 or 1 to select the SPI peripheral.
+  * @param  pBuf: Words to be transmitted.
+  * @param  len: Word length to be transmitted.
+  * @retval None
+  */
+void SPI_SendWord(SPI_TypeDef *SPIx, uint32_t *pBuf, uint16_t len)
+{
+    uint16_t i = 0;
+
+    /* Check the parameters */
+    assert_param(IS_SPI_ALL_PERIPH(SPIx));
+
+    for (i = 0; i < len; i++)
+    {
+        SPIx->DR[0] = (*pBuf++);
+        /*read TFNF bit status in SR register: SET is Tx FIFO is not full*/
+        while (!(SPIx->SR & BIT(1)));
+    }
+}
+
+/**
+  * @brief  Transmits a number of halfWords through the SPIx peripheral.
+  * @param  SPIx: where x can be 0 or 1 to select the SPI peripheral.
+  * @param  pBuf: Halfwords to be transmitted.
+  * @param  len: Halfwords length to be transmitted.
+  * @retval None
+  */
+void SPI_SendHalfWord(SPI_TypeDef *SPIx, uint16_t *pBuf, uint16_t len)
+{
+    uint16_t i = 0;
+
+    /* Check the parameters */
+    assert_param(IS_SPI_ALL_PERIPH(SPIx));
+
+    for (i = 0; i < len; i++)
+    {
+        SPIx->DR[0] = (*pBuf++);
+        /*read TFNF bit status in SR register: SET is Tx FIFO is not full*/
+        while (!(SPIx->SR & BIT(1)));
+    }
+}
+
+/**
+  * @brief  Enables or disables the specified SPI interrupts.
+  * @param  SPIx: where x can be 0 or 1 to select the SPI peripheral.
+  * @param  SPI_IT: specifies the SPI interrupt source to be enabled or disabled.
+  *   This parameter can be one of the following values:
+  *     @arg SPI_INT_TXE: The TX FIFO is equal to or below its threshold value and requires service to prevent an under-run.
+  *     @arg SPI_INT_TXO: An APB access attempts to write into the TX FIFO after it has been completely filled. When set, data written from the APB is discarded.
+  *     @arg SPI_INT_RXU: An APB access attempts to read from the RX FIFO when it is empty. When set, zeros are read back from the RX FIFO.
+  *     @arg SPI_INT_RXO: The receive logic attempts to place data into the RX FIFO after it has been completely filled. When set, newly received data are discarded.
+  *     @arg SPI_INT_RXF: RX FIFO is equal to or above its threshold value plus 1 and requires service to prevent an overflow.
+  *     @arg SPI_INT_MST: The interrupt is set when another serial master on the serial bus selects the SPI master as a serial-slave device and is actively transferring data
+  * @param  NewState: new state of the specified SPI interrupt.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void SPI_INTConfig(SPI_TypeDef *SPIx, uint8_t SPI_IT, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_SPI_ALL_PERIPH(SPIx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+    assert_param(IS_SPI_CONFIG_IT(SPI_IT));
+
+    if (NewState != DISABLE)
+    {
+        /* Enable the selected SPI interrupt */
+        SPIx->IMR |= SPI_IT;
+    }
+    else
+    {
+        /* Disable the selected SPI interrupt */
+        SPIx->IMR &= (uint16_t)~(SPI_IT);
+    }
+}
+
+/**
+  * @brief  Clear the specified SPI interrupt.
+  * @param  SPIx: where x can be 0 or 1
+  * @param  SPI_IT: specifies the SPI interrupt to clear.
+  *   This parameter can be one of the following values:
+  *     @arg SPI_INT_TXE: The TX FIFO is equal to or below its threshold value and requires service to prevent an under-run.
+  *     @arg SPI_INT_TXO: An APB access attempts to write into the TX FIFO after it has been completely filled. When set, data written from the APB is discarded.
+  *     @arg SPI_INT_RXU: An APB access attempts to read from the RX FIFO when it is empty. When set, zeros are read back from the RX FIFO.
+  *     @arg SPI_INT_RXO: The receive logic attempts to place data into the RX FIFO after it has been completely filled. When set, newly received data are discarded.
+  *     @arg SPI_INT_RXF: RX FIFO is equal to or above its threshold value plus 1 and requires service to prevent an overflow.
+  *     @arg SPI_INT_MST: The interrupt is set when another serial master on the serial bus selects the SPI master as a serial-slave device and is actively transferring data
+  * @retval None.
+  */
+void SPI_ClearINTPendingBit(SPI_TypeDef *SPIx, uint16_t SPI_IT)
+{
+    /* Check the parameters */
+    assert_param(IS_SPI_ALL_PERIPH(SPIx));
+    assert_param(IS_SPI_CONFIG_IT(SPI_IT));
+
+    switch (SPI_IT)
+    {
+    case SPI_INT_RXO:
+        (void)SPIx->RXOICR;
+        break;
+    case SPI_INT_RXU:
+        (void)SPIx->RXUICR;
+        break;
+    case SPI_INT_TXO:
+        (void)SPIx->TXOICR;
+        break;
+    case SPI_INT_MST:
+        (void)SPIx->FAEICR;
+        break;
+    case SPI_INT_TUF:
+        (void)SPIx->TXUICR;
+        break;
+    case SPI_INT_RIG:
+        (void)SPIx->SSRICR;
+        break;
+    default:
+        break;
+    }
+
+}
+
+/**
+  * \brief  Restore SPI register values when system enter DLPS.
+  * \param  PeriReg: Specifies to select the SPI peripheral.
+  * \param  StoreBuf: Restore buffer to restore SPI register data.
+  * \return None
+  */
+DATA_RAM_FUNCTION
+void SPI_DLPSEnter(void *PeriReg, void *StoreBuf)
+{
+    SPI_TypeDef *SPIx = (SPI_TypeDef *)PeriReg;
+    SPIStoreReg_TypeDef *store_buf = (SPIStoreReg_TypeDef *)StoreBuf;
+
+    if (SPIx == SPI0)
+    {
+        RCC_PeriphClockCmd(APBPeriph_SPI0, APBPeriph_SPI0_CLOCK, ENABLE);
+    }
+    else if (SPIx == SPI1)
+    {
+        RCC_PeriphClockCmd(APBPeriph_SPI1, APBPeriph_SPI1_CLOCK, ENABLE);
+    }
+
+    store_buf->spi_reg[0]  = SPIx->CTRLR0;
+    store_buf->spi_reg[1]  = SPIx->CTRLR1;
+    store_buf->spi_reg[2]  = SPIx->SSIENR;
+    store_buf->spi_reg[3]  = SPIx->SER;
+    store_buf->spi_reg[4]  = SPIx->BAUDR;
+    store_buf->spi_reg[5]  = SPIx->TXFTLR;
+    store_buf->spi_reg[6]  = SPIx->RXFTLR;
+    store_buf->spi_reg[7]  = SPIx->IMR;
+    store_buf->spi_reg[8]  = SPIx->DMACR;
+    store_buf->spi_reg[9]  = SPIx->DMATDLR;
+    store_buf->spi_reg[10] = SPIx->DMARDLR;
+    store_buf->spi_reg[11] = SPIx->RX_SAMPLE_DLY;
+    store_buf->spi_reg[12] = *(volatile uint32_t *)0x40000308UL;
+    store_buf->spi_reg[13] = *(volatile uint32_t *)0x4000035CUL;
+}
+
+/**
+  * \brief  Restore SPI register values when system exit DLPS.
+  * \param  PeriReg: Specifies to select the SPI peripheral.
+  * \param  StoreBuf: Restore buffer to restore SPI register data.
+  * \return None.
+  */
+DATA_RAM_FUNCTION
+void SPI_DLPSExit(void *PeriReg, void *StoreBuf)
+{
+    SPI_TypeDef *SPIx = (SPI_TypeDef *)PeriReg;
+    SPIStoreReg_TypeDef *store_buf = (SPIStoreReg_TypeDef *)StoreBuf;
+
+    *(volatile uint32_t *)0x4000035CUL = store_buf->spi_reg[13];
+    *(volatile uint32_t *)0x40000308UL = store_buf->spi_reg[12];
+
+    if (SPIx == SPI0)
+    {
+        RCC_PeriphClockCmd(APBPeriph_SPI0, APBPeriph_SPI0_CLOCK, ENABLE);
+    }
+    else if (SPIx == SPI1)
+    {
+        RCC_PeriphClockCmd(APBPeriph_SPI1, APBPeriph_SPI1_CLOCK, ENABLE);
+    }
+
+    SPIx->CTRLR0        = store_buf->spi_reg[0];
+    SPIx->CTRLR1        = store_buf->spi_reg[1];
+    SPIx->SER           = store_buf->spi_reg[3];
+    SPIx->BAUDR         = store_buf->spi_reg[4];
+    SPIx->TXFTLR        = store_buf->spi_reg[5];
+    SPIx->RXFTLR        = store_buf->spi_reg[6];
+    SPIx->IMR           = store_buf->spi_reg[7];
+    SPIx->DMACR         = store_buf->spi_reg[8];
+    SPIx->DMATDLR       = store_buf->spi_reg[9];
+    SPIx->DMARDLR       = store_buf->spi_reg[10];
+    SPIx->RX_SAMPLE_DLY = store_buf->spi_reg[11];
+
+    /* Enable the selected SPI peripheral */
+    SPIx->SSIENR        = store_buf->spi_reg[2];
+}
+
+
diff --git a/bee/drivers/spi/src/device/rtl8752h/rtl876x_spi.h b/bee/drivers/spi/src/device/rtl8752h/rtl876x_spi.h
new file mode 100644
index 00000000..f2b8de0f
--- /dev/null
+++ b/bee/drivers/spi/src/device/rtl8752h/rtl876x_spi.h
@@ -0,0 +1,942 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _RTL876X_SPI_H_
+#define _RTL876X_SPI_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/**
+ * \addtogroup  IO          Peripheral Drivers
+ * \defgroup    SPI         SPI
+ *
+ * \brief       Manage the SPI peripheral functions.
+ *
+ * \ingroup     IO
+ */
+
+/*============================================================================*
+ *                         Includes
+ *============================================================================*/
+#include "rtl876x.h"
+
+
+/*============================================================================*
+ *                         Types
+ *============================================================================*/
+/**
+ * \defgroup    SPI_Exported_Types SPI Exported Types
+ * \{
+ * \ingroup     SPI
+ */
+
+/**
+ * \brief       SPI init structure definition.
+ *
+ * \ingroup     SPI_Exported_Types
+ */
+
+typedef struct
+{
+    uint16_t SPI_Direction;         /*!< Specify the SPI unidirectional or bidirectional data mode.
+                                            This parameter can be a value of \ref SPI_Data_Direction. */
+    uint16_t SPI_Mode;              /*!< Specify the SPI operating mode.
+                                            This parameter can be a value of \ref SPI_Mode. */
+    uint16_t SPI_DataSize;          /*!< Specify the SPI data size.
+                                            This parameter can be a value of \ref SPI_Data_Size. */
+    uint16_t SPI_CPOL;              /*!< Specify the polarity of the clock signal during the idle state.
+                                            This parameter can be a value of \ref SPI_Clock_Polarity. */
+    uint16_t SPI_CPHA;              /*!< Specify the clock active edge for the bit capture.
+                                            This parameter can be a value of \ref SPI_Clock_Phase. */
+//    uint32_t SPI_SwapTxBitEn;       /*!< Specify whether to swap spi tx data bit.
+//                                            This parameter can be a value of \ref SPI_Swap_Enable.
+//                                            \note This parameter can only be configured if the SPI0 peripheral is set to Slave Mode.*/
+//    uint32_t SPI_SwapRxBitEn;       /*!< Specify whether to swap spi rx data bit
+//                                            This parameter can be a value of \ref SPI_Swap_Enable.
+//                                            \note This parameter can only be configured if the SPI0 peripheral is set to Slave Mode.*/
+//    uint32_t SPI_SwapTxByteEn;      /*!< Specify whether to swap spi tx data bit
+//                                            This parameter can be a value of \ref SPI_Swap_Enable.
+//                                            \note This parameter can only be configured if the SPI0 peripheral is set to Slave Mode.*/
+//    uint32_t SPI_SwapRxByteEn;      /*!< Specify whether to swap spi rx data bit
+//                                            This parameter can be a value of \ref SPI_Swap_Enable.
+//                                            \note This parameter can only be configured if the SPI0 peripheral is set to Slave Mode.*/
+    uint32_t SPI_ToggleEn;          /*!< Specify whether to toggle CS between successive frames. */
+    uint32_t SPI_BaudRatePrescaler; /*!< Specify the speed of SCK clock. SPI Clock Speed = clk source/SPI_BaudRatePrescaler.
+                                            \note The communication clock is derived from the master clock. The slave clock does not need to be set. */
+    uint16_t SPI_FrameFormat;       /*!< Specify which serial protocol transfers the data.
+                                            This parameter can be a value of \ref SPI_Frame_Format. */
+    uint32_t SPI_TxThresholdLevel;  /*!< Specify the transmit FIFO Threshold. */
+    uint32_t SPI_RxThresholdLevel;  /*!< Specify the receive FIFO Threshold. */
+    uint32_t SPI_NDF;               /*!< Specify the number of data frames to be continuously received by the SPI in EEPROM mode or RX only mode.
+                                            This parameter should be the value of the length of read data. */
+    uint16_t SPI_TxDmaEn;           /*!< Specify the Tx DMA mode. */
+    uint16_t SPI_RxDmaEn;           /*!< Specify the Rx DMA mode. */
+    uint8_t SPI_TxWaterlevel;       /*!< Specify the DMA Tx water level. */
+    uint8_t SPI_RxWaterlevel;       /*!< Specify the DMA Rx water level. */
+
+} SPI_InitTypeDef;
+
+/** End of SPI_Exported_Types
+  * \}
+  */
+
+/*============================================================================*
+ *                         Constants
+ *============================================================================*/
+/**
+ * \defgroup    SPI_Exported_Constants SPI Exported Constants
+ *
+ * \ingroup     SPI
+ */
+
+#define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI0) || \
+                                   ((PERIPH) == SPI1))
+
+#define IS_SPI_CLOCK_SPEED(SPEED) (((SPEED) >= 0x01) && ((SPEED) <= 40000000))
+
+/**
+ * \defgroup    SPI_Data_Direction SPI Data Direction
+ * \{
+ * \ingroup     SPI_Exported_Constants
+ */
+#define SPI_Direction_FullDuplex        ((uint16_t)0x0000)
+#define SPI_Direction_TxOnly            ((uint16_t)0x0001)
+#define SPI_Direction_RxOnly            ((uint16_t)0x0002)
+#define SPI_Direction_EEPROM            ((uint16_t)0x0003)
+
+#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_FullDuplex) || \
+                                     ((MODE) == SPI_Direction_RxOnly) || \
+                                     ((MODE) == SPI_Direction_TxOnly) || \
+                                     ((MODE) == SPI_Direction_EEPROM))
+/** \} */
+
+/**
+ * \defgroup    SPI_Mode SPI Mode
+ * \{
+ * \ingroup     SPI_Exported_Constants
+ */
+
+#define SPI_Mode_Master                         ((uint16_t)0x0104)
+#define SPI_Mode_Slave                          ((uint16_t)0x0000)
+
+#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \
+                           ((MODE) == SPI_Mode_Slave))
+/** \} */
+
+/**
+ * \defgroup    SPI_Data_Size SPI Data Size
+ * \{
+ * \ingroup     SPI_Exported_Constants
+ */
+
+#define SPI_DataSize_4b                 ((uint16_t)0x0003)
+#define SPI_DataSize_5b                 ((uint16_t)0x0004)
+#define SPI_DataSize_6b                 ((uint16_t)0x0005)
+#define SPI_DataSize_7b                 ((uint16_t)0x0006)
+#define SPI_DataSize_8b                 ((uint16_t)0x0007)
+#define SPI_DataSize_9b                 ((uint16_t)0x0008)
+#define SPI_DataSize_10b                 ((uint16_t)0x0009)
+#define SPI_DataSize_11b                 ((uint16_t)0x000a)
+#define SPI_DataSize_12b                 ((uint16_t)0x000b)
+#define SPI_DataSize_13b                 ((uint16_t)0x000c)
+#define SPI_DataSize_14b                 ((uint16_t)0x000d)
+#define SPI_DataSize_15b                 ((uint16_t)0x000e)
+#define SPI_DataSize_16b                 ((uint16_t)0x000f)
+#define SPI_DataSize_17b                 ((uint16_t)0x0010)
+#define SPI_DataSize_18b                 ((uint16_t)0x0011)
+#define SPI_DataSize_19b                 ((uint16_t)0x0012)
+#define SPI_DataSize_20b                 ((uint16_t)0x0013)
+#define SPI_DataSize_21b                 ((uint16_t)0x0014)
+#define SPI_DataSize_22b                 ((uint16_t)0x0015)
+#define SPI_DataSize_23b                 ((uint16_t)0x0016)
+#define SPI_DataSize_24b                 ((uint16_t)0x0017)
+#define SPI_DataSize_25b                 ((uint16_t)0x0018)
+#define SPI_DataSize_26b                 ((uint16_t)0x0019)
+#define SPI_DataSize_27b                 ((uint16_t)0x001A)
+#define SPI_DataSize_28b                 ((uint16_t)0x001B)
+#define SPI_DataSize_29b                 ((uint16_t)0x001C)
+#define SPI_DataSize_30b                 ((uint16_t)0x001D)
+#define SPI_DataSize_31b                 ((uint16_t)0x001E)
+#define SPI_DataSize_32b                 ((uint16_t)0x001F)
+
+#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DataSize_4b)  || \
+                                   ((DATASIZE) == SPI_DataSize_5b)  || \
+                                   ((DATASIZE) == SPI_DataSize_6b)  || \
+                                   ((DATASIZE) == SPI_DataSize_7b)  || \
+                                   ((DATASIZE) == SPI_DataSize_8b)  || \
+                                   ((DATASIZE) == SPI_DataSize_9b)  || \
+                                   ((DATASIZE) == SPI_DataSize_10b) || \
+                                   ((DATASIZE) == SPI_DataSize_11b) || \
+                                   ((DATASIZE) == SPI_DataSize_12b) || \
+                                   ((DATASIZE) == SPI_DataSize_13b) || \
+                                   ((DATASIZE) == SPI_DataSize_14b) || \
+                                   ((DATASIZE) == SPI_DataSize_15b) || \
+                                   ((DATASIZE) == SPI_DataSize_16b) || \
+                                   ((DATASIZE) == SPI_DataSize_17b) || \
+                                   ((DATASIZE) == SPI_DataSize_18b) || \
+                                   ((DATASIZE) == SPI_DataSize_19b) || \
+                                   ((DATASIZE) == SPI_DataSize_20b) || \
+                                   ((DATASIZE) == SPI_DataSize_21b) || \
+                                   ((DATASIZE) == SPI_DataSize_22b) || \
+                                   ((DATASIZE) == SPI_DataSize_23b) || \
+                                   ((DATASIZE) == SPI_DataSize_24b) || \
+                                   ((DATASIZE) == SPI_DataSize_25b) || \
+                                   ((DATASIZE) == SPI_DataSize_26b) || \
+                                   ((DATASIZE) == SPI_DataSize_27b) || \
+                                   ((DATASIZE) == SPI_DataSize_28b) || \
+                                   ((DATASIZE) == SPI_DataSize_29b) || \
+                                   ((DATASIZE) == SPI_DataSize_30b) || \
+                                   ((DATASIZE) == SPI_DataSize_31b) || \
+                                   ((DATASIZE) == SPI_DataSize_32b))
+/** \} */
+
+/**
+ * \defgroup    SPI_BaudRate_Prescaler SPI BaudRate Prescaler Value
+ * \{
+ * \ingroup     SPI_Exported_Constants
+ */
+
+#define SPI_BaudRatePrescaler_2         ((uint32_t)0x0002)
+#define SPI_BaudRatePrescaler_4         ((uint32_t)0x0004)
+#define SPI_BaudRatePrescaler_6         ((uint32_t)0x0006)
+#define SPI_BaudRatePrescaler_8         ((uint32_t)0x0008)
+#define SPI_BaudRatePrescaler_10        ((uint32_t)0x000A)
+#define SPI_BaudRatePrescaler_12        ((uint32_t)0x000C)
+#define SPI_BaudRatePrescaler_14        ((uint32_t)0x000E)
+#define SPI_BaudRatePrescaler_16        ((uint32_t)0x0010)
+#define SPI_BaudRatePrescaler_32        ((uint32_t)0x0020)
+#define SPI_BaudRatePrescaler_64        ((uint32_t)0x0040)
+#define SPI_BaudRatePrescaler_128       ((uint32_t)0x0080)
+#define SPI_BaudRatePrescaler_256       ((uint32_t)0x0100)
+
+#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \
+                                              ((PRESCALER) == SPI_BaudRatePrescaler_4) || \
+                                              ((PRESCALER) == SPI_BaudRatePrescaler_8) || \
+                                              ((PRESCALER) == SPI_BaudRatePrescaler_10) || \
+                                              ((PRESCALER) == SPI_BaudRatePrescaler_12) || \
+                                              ((PRESCALER) == SPI_BaudRatePrescaler_14) || \
+                                              ((PRESCALER) == SPI_BaudRatePrescaler_16) || \
+                                              ((PRESCALER) == SPI_BaudRatePrescaler_32) || \
+                                              ((PRESCALER) == SPI_BaudRatePrescaler_64) || \
+                                              ((PRESCALER) == SPI_BaudRatePrescaler_128) || \
+                                              ((PRESCALER) == SPI_BaudRatePrescaler_256))
+/** \} */
+
+/**
+ * \defgroup    SPI_Clock_Polarity SPI Clock Polarity
+ * \{
+ * \ingroup     SPI_Exported_Constants
+ */
+
+#define SPI_CPOL_Low                    ((uint16_t)0x0000)
+#define SPI_CPOL_High                   ((uint16_t)0x0001)
+
+#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \
+                           ((CPOL) == SPI_CPOL_High))
+/** \} */
+
+/**
+ * \defgroup    SPI_Clock_Phase SPI Clock Phase
+ * \{
+ * \ingroup     SPI_Exported_Constants
+ */
+
+#define SPI_CPHA_1Edge                  ((uint16_t)0x0000)
+#define SPI_CPHA_2Edge                  ((uint16_t)0x0001)
+
+#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \
+                           ((CPHA) == SPI_CPHA_2Edge))
+/** \} */
+
+/**
+ * \defgroup    SPI_Frame_Format SPI Frame Format
+ * \{
+ * \ingroup     SPI_Exported_Constants
+ */
+
+#define SPI_Frame_Motorola              ((uint16_t)0x0000)
+#define SPI_Frame_TI_SSP                ((uint16_t)0x0001)
+#define SPI_Frame_NS_MICROWIRE          ((uint16_t)0x0002)
+#define SPI_Frame_Reserve               ((uint16_t)0x0003)
+
+#define IS_SPI_FRAME_FORMAT(FRAME) (((FRAME) == SPI_Frame_Motorola) || \
+                                    ((FRAME) == SPI_Frame_TI_SSP) || \
+                                    ((FRAME) == SPI_Frame_NS_MICROWIRE) || \
+                                    ((FRAME) == SPI_Frame_Reserve))
+/** \} */
+
+/**
+ * \defgroup    SPI_Flags_Definition SPI Flags Definition
+ * \{
+ * \ingroup     SPI_Exported_Constants
+ */
+
+#define SPI_FLAG_BUSY                   ((uint16_t)0x0001)
+#define SPI_FLAG_TFNF                   ((uint16_t)0x0002)
+#define SPI_FLAG_TFE                    ((uint16_t)0x0004)
+#define SPI_FLAG_RFNE                   ((uint16_t)0x0008)
+#define SPI_FLAG_RFF                    ((uint16_t)0x0010)
+#define SPI_FLAG_TXE                    ((uint16_t)0x0020)
+#define SPI_FLAG_DCOL                   ((uint16_t)0x0040)
+
+#define IS_SPI_GET_FLAG(FLAG)   (((FLAG) == SPI_FLAG_DCOL) || ((FLAG) == SPI_FLAG_TXE) || \
+                                 ((FLAG) == SPI_FLAG_RFF) || ((FLAG) == SPI_FLAG_RFNE) || \
+                                 ((FLAG) == SPI_FLAG_TFE) || ((FLAG) == SPI_FLAG_TFNF) || \
+                                 ((FLAG) == SPI_FLAG_BUSY))
+/** \} */
+
+/**
+ * \defgroup    SPI_Interrupt_Definition SPI Interrupt Definition
+ * \{
+ * \ingroup     SPI_Exported_Constants
+ */
+
+#define SPI_INT_TXE                  ((uint8_t)BIT(0))
+#define SPI_INT_TXO                  ((uint8_t)BIT(1))
+#define SPI_INT_RXU                  ((uint8_t)BIT(2))
+#define SPI_INT_RXO                  ((uint8_t)BIT(3))
+#define SPI_INT_RXF                  ((uint8_t)BIT(4))
+#define SPI_INT_MST                  ((uint8_t)BIT(5))
+#define SPI_INT_TUF                  ((uint8_t)BIT(6))
+#define SPI_INT_RIG                  ((uint8_t)BIT(7))
+
+#define IS_SPI_CONFIG_IT(IT) (((IT) == SPI_INT_TXE) || \
+                              ((IT) == SPI_INT_TXO) || \
+                              ((IT) == SPI_INT_RXU) || \
+                              ((IT) == SPI_INT_RXO) || \
+                              ((IT) == SPI_INT_RXF) || \
+                              ((IT) == SPI_INT_MST) || \
+                              ((IT) == SPI_INT_TUF) || \
+                              ((IT) == SPI_INT_RIG) )
+/** \} */
+
+/**
+ * \defgroup    SPI_GDMA_Transfer_Request SPI GDMA Transfer Request
+ * \{
+ * \ingroup     SPI_Exported_Constants
+ */
+
+#define SPI_GDMAReq_Tx               ((uint16_t)0x0002)
+#define SPI_GDMAReq_Rx               ((uint16_t)0x0001)
+
+#define IS_SPI_GDMAREQ(GDMAREQ) ((((GDMAREQ) & (uint16_t)0xFFFC) == 0x00) && ((GDMAREQ) != 0x00))
+/** \} */
+
+/**
+ * \defgroup    SPI_Swap_Enable SPI Swap Enable
+ * \{
+ * \ingroup     SPI_Exported_Constants
+ */
+
+#define SPI_SWAP_ENABLE                ((uint32_t)0x0001)
+#define SPI_SWAP_DISABLE               ((uint32_t)0x0000)
+
+#define IS_SPI_SWAPMODE(mode) (((mode) == SPI_SWAP_ENABLE) || \
+                               ((mode) == SPI_SWAP_DISABLE))
+/** \} */
+
+/** End of SPI_Exported_Constants
+  * \}
+  */
+
+#define SPI_TX_FIFO_ADDR(SPIx)    (uint32_t)(&(((SPI_TypeDef *)(SPIx))->DR[0]))
+#define SPI_RX_FIFO_ADDR(SPIx)    (uint32_t)(&(((SPI_TypeDef *)(SPIx))->DR[0]))
+
+/*============================================================================*
+ *                         Functions
+ *============================================================================*/
+/**
+ * \defgroup    SPI_Exported_Functions  SPI Exported Functions
+ * \{
+ * \ingroup     SPI
+ */
+
+/**
+ * \brief   Deinitialize the SPIx peripheral registers to their default reset values.
+ * \param[in] SPIx: Where x can be 0 or 1 to select the SPI peripheral.
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_spi_init(void)
+ * {
+ *     SPI_DeInit(SPI0);
+ * }
+ * \endcode
+ */
+void SPI_DeInit(SPI_TypeDef *SPIx);
+
+/**
+ * \brief   Initialize the SPIx peripheral according to the specified
+ *          parameters in the SPI_InitStruct.
+ * \param[in] SPIx: Where x can be 0 or 1 to select the SPI peripheral.
+ * \param[in] SPI_InitStruct: Pointer to a SPI_InitTypeDef structure that
+ *            contains the configuration information for the specified SPI peripheral.
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_spi_init(void)
+ * {
+ *     RCC_PeriphClockCmd(APBPeriph_SPI0, APBPeriph_SPI0_CLOCK, ENABLE);
+
+ *     SPI_InitTypeDef  SPI_InitStruct;
+ *     SPI_StructInit(&SPI_InitStruct);
+ *
+ *     SPI_InitStruct.SPI_Direction   = SPI_Direction_EEPROM;
+ *     SPI_InitStruct.SPI_Mode        = SPI_Mode_Master;
+ *     SPI_InitStruct.SPI_DataSize    = SPI_DataSize_8b;
+ *     SPI_InitStruct.SPI_CPOL        = SPI_CPOL_High;
+ *     SPI_InitStruct.SPI_CPHA        = SPI_CPHA_2Edge;
+ *     SPI_InitStruct.SPI_BaudRatePrescaler  = 100;
+ *     SPI_InitStruct.SPI_RxThresholdLevel  = 1 - 1;
+ *     SPI_InitStruct.SPI_NDF               = 1 - 1;
+ *     SPI_InitStruct.SPI_FrameFormat = SPI_Frame_Motorola;
+ *
+ *     SPI_Init(SPI0, &SPI_InitStruct);
+ * }
+ * \endcode
+ */
+void SPI_Init(SPI_TypeDef *SPIx, SPI_InitTypeDef *SPI_InitStruct);
+
+/**
+ * \brief  Fill each SPI_InitStruct member with its default value.
+ * \param[in]  SPI_InitStruct: Pointer to a SPI_InitTypeDef structure which will be initialized.
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_spi_init(void)
+ * {
+ *
+ *     RCC_PeriphClockCmd(APBPeriph_SPI0, APBPeriph_SPI0_CLOCK, ENABLE);
+
+ *     SPI_InitTypeDef  SPI_InitStruct;
+ *     SPI_StructInit(&SPI_InitStruct);
+ *
+ *     SPI_InitStruct.SPI_Direction   = SPI_Direction_EEPROM;
+ *     SPI_InitStruct.SPI_Mode        = SPI_Mode_Master;
+ *     SPI_InitStruct.SPI_DataSize    = SPI_DataSize_8b;
+ *     SPI_InitStruct.SPI_CPOL        = SPI_CPOL_High;
+ *     SPI_InitStruct.SPI_CPHA        = SPI_CPHA_2Edge;
+ *     SPI_InitStruct.SPI_BaudRatePrescaler  = 100;
+ *     SPI_InitStruct.SPI_RxThresholdLevel  = 1 - 1;
+ *     SPI_InitStruct.SPI_NDF               = 1 - 1;
+ *     SPI_InitStruct.SPI_FrameFormat = SPI_Frame_Motorola;
+ *
+ *     SPI_Init(SPI0, &SPI_InitStruct);
+ * }
+ * \endcode
+ */
+void SPI_StructInit(SPI_InitTypeDef *SPI_InitStruct);
+
+/**
+ * \brief  Enable or disable the selected SPI peripheral.
+ * \param[in]  SPIx: Where x can be 0 or 1 to select the SPI peripheral.
+ * \param[in]  NewState: New state of the SPIx peripheral.
+ *      This parameter can be: ENABLE or DISABLE.
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_spi_init(void)
+ * {
+ *
+ *     RCC_PeriphClockCmd(APBPeriph_SPI0, APBPeriph_SPI0_CLOCK, ENABLE);
+ *
+ *     SPI_InitTypeDef  SPI_InitStruct;
+ *     SPI_StructInit(&SPI_InitStruct);
+ *
+ *     SPI_InitStruct.SPI_Direction   = SPI_Direction_EEPROM;
+ *     SPI_InitStruct.SPI_Mode        = SPI_Mode_Master;
+ *     SPI_InitStruct.SPI_DataSize    = SPI_DataSize_8b;
+ *     SPI_InitStruct.SPI_CPOL        = SPI_CPOL_High;
+ *     SPI_InitStruct.SPI_CPHA        = SPI_CPHA_2Edge;
+ *     SPI_InitStruct.SPI_BaudRatePrescaler  = 100;
+ *     SPI_InitStruct.SPI_RxThresholdLevel  = 1 - 1;
+ *     SPI_InitStruct.SPI_NDF               = 1 - 1;
+ *     SPI_InitStruct.SPI_FrameFormat = SPI_Frame_Motorola;
+ *
+ *     SPI_Init(SPI0, &SPI_InitStruct);
+ *     SPI_Cmd(SPI0, ENABLE);
+ * }
+ * \endcode
+ */
+void SPI_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState);
+
+/**
+ * \brief  Transmit a number of bytes through the SPIx peripheral.
+ * \param[in] SPIx: Where x can be 0 or 1 to select the SPI peripheral.
+ * \param[in] pBuf: Bytes to be transmitted.
+ * \param[in] len: Byte length to be transmitted.
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void spi_demo(void)
+ * {
+ *     uint8_t data_buf[] = {0x01,0x02,0x03};
+ *     SPI_SendBuffer(SPI0, data_buf, sizeof(data_buf));
+ * }
+ * \endcode
+ */
+void SPI_SendBuffer(SPI_TypeDef *SPIx, uint8_t *pBuf, uint16_t len);
+
+/**
+  * \brief  Transmit a number of halfWords through the SPIx peripheral.
+  * \param[in] SPIx: Where x can be 0 or 1 to select the SPI peripheral.
+  * \param[in] pBuf: Halfwords to be transmitted.
+  * \param[in] len: Halfwords length to be transmitted.
+  * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void spi_demo(void)
+ * {
+ *     uint16_t data_buf[] = {0x0102,0x0203,0x0304};
+ *     SPI_SendHalfWord(SPI0, data_buf, sizeof(data_buf));
+ * }
+ * \endcode
+  */
+void SPI_SendHalfWord(SPI_TypeDef *SPIx, uint16_t *pBuf, uint16_t len);
+
+/**
+ * \brief  Transmit a number of words through the SPIx peripheral.
+ * \param[in] SPIx: Where x can be 0 or 1 to select the SPI peripheral.
+ * \param[in] pBuf: Words to be transmitted.
+ * \param[in] len: Word length to be transmitted.
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void spi_demo(void)
+ * {
+ *     uint32_t data_buf[] = {0x01020304,0x02030405,0x03040506};
+ *     SPI_SendWord(SPI0, data_buf, sizeof(data_buf));
+ * }
+ * \endcode
+ */
+void SPI_SendWord(SPI_TypeDef *SPIx, uint32_t *pBuf, uint16_t len);
+
+/**
+ * \brief  Enable or disable the specified SPI interrupt source.
+ * \param[in] SPIx: Where x can be 0 or 1 to select the SPI peripheral.
+ * \param[in] SPI_IT: Specify the SPI interrupt source to be enabled or disabled.
+ *      This parameter can be one of the following values, refer to \ref SPI_Interrupt_Definition.
+ *      \arg SPI_INT_TXE: The TX FIFO is equal to or below its threshold value and requires service to prevent an under-run.
+ *      \arg SPI_INT_TXO: An APB access attempts to write into the TX FIFO after it has been completely filled. When set, data written from the APB is discarded.
+ *      \arg SPI_INT_RXU: An APB access attempts to read from the RX FIFO when it is empty. When set, zeros are read back from the RX FIFO.
+ *      \arg SPI_INT_RXO: The receive logic attempts to place data into the RX FIFO after it has been completely filled. When set, newly received data are discarded.
+ *      \arg SPI_INT_RXF: RX FIFO is equal to or above its threshold value plus 1 and requires service to prevent an overflow.
+ *      \arg SPI_INT_MST: The interrupt is set when another serial master on the serial bus selects the SPI master as a serial-slave device and is actively transferring data.
+ * \param[in] NewState: New state of the specified SPI interrupt source.
+ *      This parameter can be: ENABLE or DISABLE.
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void spi_demo(void)
+ * {
+ *     SPI_INTConfig(SPI0, SPI_INT_RXF, ENABLE);
+ * }
+ * \endcode
+ */
+void SPI_INTConfig(SPI_TypeDef *SPIx, uint8_t SPI_IT, FunctionalState NewState);
+
+/**
+ * \brief  Clear the specified SPI interrupt pending bit.
+ * \param[in] SPIx: Where x can be 0 or 1 to select the SPI peripheral.
+ * \param[in] SPI_IT: Specify the SPI interrupt to clear.
+ *      This parameter can be one of the following values, refer to \ref SPI_Interrupt_Definition.
+ *      \arg SPI_INT_TXE: The TX FIFO is equal to or below its threshold value and requires service to prevent an under-run.
+ *      \arg SPI_INT_TXO: An APB access attempts to write into the TX FIFO after it has been completely filled. When set, data written from the APB is discarded.
+ *      \arg SPI_INT_RXU: An APB access attempts to read from the RX FIFO when it is empty. When set, zeros are read back from the RX FIFO.
+ *      \arg SPI_INT_RXO: The receive logic attempts to place data into the RX FIFO after it has been completely filled. When set, newly received data are discarded.
+ *      \arg SPI_INT_RXF: RX FIFO is equal to or above its threshold value plus 1 and requires service to prevent an overflow.
+ *      \arg SPI_INT_MST: The interrupt is set when another serial master on the serial bus selects the SPI master as a serial-slave device and is actively transferring data.
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void spi_demo(void)
+ * {
+ *     SPI_ClearINTPendingBit(SPI0, SPI_INT_RXF);
+ * }
+ * \endcode
+ */
+void SPI_ClearINTPendingBit(SPI_TypeDef *SPIx, uint16_t SPI_IT);
+
+/**
+ * \brief  Transmit a data through the SPIx peripheral.
+ * \param[in] SPIx: Where x can be 0 or 1 to select the SPI peripheral.
+ * \param[in] Data: Data to be transmitted.
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void spi_demo(void)
+ * {
+ *     uint32_t data = 0x01020304;
+ *     SPI_SendData(SPI0, data);
+ * }
+ * \endcode
+ */
+__STATIC_INLINE void SPI_SendData(SPI_TypeDef *SPIx, uint32_t Data)
+{
+    /* Check the parameters */
+    assert_param(IS_SPI_ALL_PERIPH(SPIx));
+
+    SPIx->DR[0] = Data;
+    while (!(SPIx->SR & BIT(1)));
+}
+
+/**
+ * \brief   Receive data by the SPIx peripheral.
+ * \param[in] SPIx: Where x can be 0 or 1 to select the SPI peripheral.
+ * \return  The most recent received data.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void spi_demo(void)
+ * {
+ *     uint32_t data = SPI_ReceiveData(SPI0);
+ * }
+ * \endcode
+ */
+__STATIC_INLINE uint32_t SPI_ReceiveData(SPI_TypeDef *SPIx)
+{
+    /* Check the parameters */
+    assert_param(IS_SPI_ALL_PERIPH(SPIx));
+
+    return (uint32_t)SPIx->DR[0];
+}
+
+/**
+ * \brief   Get data length in Tx FIFO through the SPIx peripheral.
+ * \param[in] SPIx: Where x can be 0 or 1 to select the SPI peripheral.
+ * \return  Data length in Tx FIFO.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void spi_demo(void)
+ * {
+ *     uint8_t data_len = SPI_GetTxFIFOLen(SPI0);
+ * }
+ * \endcode
+ */
+__STATIC_INLINE uint8_t SPI_GetTxFIFOLen(SPI_TypeDef *SPIx)
+{
+    /* Check the parameters */
+    assert_param(IS_SPI_ALL_PERIPH(SPIx));
+
+    return (uint8_t)SPIx->TXFLR;
+}
+
+/**
+ * \brief   Get data length in Rx FIFO through the SPIx peripheral.
+ * \param[in] SPIx: Where x can be 0 or 1 to select the SPI peripheral.
+ * \return  Data length in Rx FIFO.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void spi_demo(void)
+ * {
+ *     uint8_t data_len = SPI_GetRxFIFOLen(SPI0);
+ * }
+ * \endcode
+ */
+__STATIC_INLINE uint8_t SPI_GetRxFIFOLen(SPI_TypeDef *SPIx)
+{
+    /* Check the parameters */
+    assert_param(IS_SPI_ALL_PERIPH(SPIx));
+    return (uint8_t)SPIx->RXFLR;
+}
+
+/**
+ * \brief   Change SPI direction mode.
+ * \param[in] SPIx: Where x can be 0 or 1 to select the SPI peripheral.
+ * \param[in] dir: Value of direction mode, refer to \ref SPI_Data_Direction.
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void spi_demo(void)
+ * {
+ *     SPI_ChangeDirection(SPI0, SPI_Direction_EEPROM);
+ * }
+ * \endcode
+ */
+__STATIC_INLINE void SPI_ChangeDirection(SPI_TypeDef *SPIx, uint16_t dir)
+{
+    /* Check the parameters */
+    assert_param(IS_SPI_ALL_PERIPH(SPIx));
+    assert_param(IS_SPI_DIRECTION_MODE(dir));
+
+    /* Disable the selected SPI peripheral */
+    SPIx->SSIENR &= ~0x01;
+
+    /* Change SPI direction mode */
+    SPIx->CTRLR0 &= ~(0x03 << 8);
+    SPIx->CTRLR0 |= dir << 8;
+
+    /* Enable the selected SPI peripheral */
+    SPIx->SSIENR |= 0x01;
+}
+
+/**
+ * \brief   Set read Data length only in EEPROM mode or RX only mode through the SPIx peripheral, which
+            enables receiving up to 64 KB of data in a continuous transfer.
+ * \param[in] SPIx: Where x can be 0 or 1 to select the SPI peripheral.
+ * \param[in] len: Length of read data which can be 1 to 65536.
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void spi_demo(void)
+ * {
+ *     SPI_SetReadLen(SPI0, 100);
+ * }
+ * \endcode
+ */
+__STATIC_INLINE void SPI_SetReadLen(SPI_TypeDef *SPIx, uint16_t len)
+{
+    /* Check the parameters */
+    assert_param(IS_SPI_ALL_PERIPH(SPIx));
+
+    /* Disable the selected SPI peripheral */
+    SPIx->SSIENR &= ~0x01;
+    /* Set read length in SPI EEPROM mode or RX only mode */
+    SPIx->CTRLR1 = len - 1;
+    /* Enable the selected SPI peripheral */
+    SPIx->SSIENR |= 0x01;
+}
+
+/**
+ * \brief   Set cs number through the SPIx peripheral.
+ * \param[in] SPIx: Where x can be 0 or 1 to select the SPI peripheral.
+ * \param[in] number: If SPIx is SPI0, number must be 0. If SPIx is SPI1, number can be 0 to 2.
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void spi_demo(void)
+ * {
+ *     SPI_SetCSNumber(SPI1, 1);
+ * }
+ * \endcode
+ */
+__STATIC_INLINE void SPI_SetCSNumber(SPI_TypeDef *SPIx, uint8_t number)
+{
+    /* Check the parameters */
+    assert_param(IS_SPI_ALL_PERIPH(SPIx));
+
+    /* Set cs number */
+    SPIx->SER = BIT(number);
+}
+
+/**
+ * \brief  Check whether the specified SPI interrupt is set.
+ * \param[in] SPIx: Where x can be 0 or 1 to select the SPI peripheral.
+ * \param[in]  SPI_IT: Specify the SPI interrupt to check.
+ *      This parameter can be one of the following values, refer to \ref SPI_Interrupt_Definition.
+ *      \arg SPI_INT_TXE: The TX FIFO is equal to or below its threshold value and requires service to prevent an under-run.
+ *      \arg SPI_INT_TXO: An APB access attempts to write into the TX FIFO after it has been completely filled. When set, data written from the APB is discarded.
+ *      \arg SPI_INT_RXU: An APB access attempts to read from the RX FIFO when it is empty. When set, zeros are read back from the RX FIFO.
+ *      \arg SPI_INT_RXO: The receive logic attempts to place data into the RX FIFO after it has been completely filled. When set, newly received data are discarded.
+ *      \arg SPI_INT_RXF: RX FIFO is equal to or above its threshold value plus 1 and requires service to prevent an overflow.
+ *      \arg SPI_INT_MST: The interrupt is set when another serial master on the serial bus selects the SPI master as a serial-slave device and is actively transferring data.
+ * \return The new state of SPI_IT (SET or RESET).
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void spi_demo(void)
+ * {
+ *     ITStatus int_status = SPI_GetINTStatus(SPI0, SPI_INT_RXF);
+ * }
+ * \endcode
+ */
+__STATIC_INLINE ITStatus SPI_GetINTStatus(SPI_TypeDef *SPIx, uint32_t SPI_IT)
+{
+    ITStatus bit_status = RESET;
+
+    /* Check the parameters */
+    assert_param(IS_SPI_ALL_PERIPH(SPIx));
+    assert_param(IS_SPI_CONFIG_IT(SPI_IT));
+
+    if ((SPIx->ISR & SPI_IT) != (uint32_t)RESET)
+    {
+        bit_status = SET;
+    }
+
+    /* Return the SPI_IT status */
+    return  bit_status;
+}
+
+/**
+ * \brief  Check whether the specified SPI flag is set.
+ * \param[in] SPIx: Where x can be 0 or 1 to select the SPI peripheral.
+ * \param[in]  SPI_FLAG: Specify the SPI flag to check.
+ *      This parameter can be one of the following values, refer to \ref SPI_Flags_Definition.
+ *      \arg SPI_FLAG_DCOL: Data Collision Error flag. Set if it is actively transmitting in master mode when another master selects this device as a slave.
+ *      \arg SPI_FLAG_TXE: Set if the transmit FIFO is empty when a transfer is started.
+ *      \arg SPI_FLAG_RFF: When the receive FIFO is completely full, this bit is set.
+ *      \arg SPI_FLAG_RFNE: Set when the receive FIFO contains one or more entries and is cleared when the receive FIFO is empty.
+ *      \arg SPI_FLAG_TFE: When the transmit FIFO is completely empty, this bit is set.
+ *      \arg SPI_FLAG_TFNF: Set when the transmit FIFO contains one or more empty locations, and is cleared when the FIFO is full.
+ *      \arg SPI_FLAG_BUSY: When set, indicates that a serial transfer is in progress; when cleared indicates that the SPI is idle or disabled.
+ * \return The new state of SPI_FLAG (SET or RESET).
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void spi_demo(void)
+ * {
+ *     FlagStatus flag_status = SPI_GetFlagState(SPI0, SPI_FLAG_TXE);
+ *
+ * }
+ * \endcode
+ */
+__STATIC_INLINE FlagStatus SPI_GetFlagState(SPI_TypeDef *SPIx, uint8_t SPI_FLAG)
+{
+    FlagStatus bitstatus = RESET;
+
+    /* Check the parameters */
+    assert_param(IS_SPI_ALL_PERIPH(SPIx));
+    assert_param(IS_SPI_GET_FLAG(SPI_FLAG));
+
+    /* Check the status of the specified SPI flag */
+    if ((SPIx->SR & SPI_FLAG) != (uint8_t)RESET)
+    {
+        /* SPI_FLAG is set */
+        bitstatus = SET;
+    }
+
+    /* Return the SPI_FLAG status */
+    return  bitstatus;
+}
+
+/**
+ * \brief   Enable or disable the SPIx GDMA interface.
+ * \param[in] SPIx: Where x can be 0 or 1 to select the SPI peripheral.
+ * \param[in] SPI_GDMAReq: Specify the SPI GDMA transfer request to be enabled or disabled.
+ *      This parameter can be one of the following values, refer to \ref SPI_GDMA_Transfer_Request.
+ *      \arg SPI_GDMAReq_Tx: Tx buffer DMA transfer request.
+ *      \arg SPI_GDMAReq_Rx: Rx buffer DMA transfer request.
+ * \param[in]  NewState: New state of the selected SPI GDMA transfer request.
+ *      This parameter can be: ENABLE or DISABLE.
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void spi_demo(void)
+ * {
+ *     SPI_GDMACmd(SPI0, SPI_GDMAReq_Tx, ENABLE);
+ * }
+ * \endcode
+ */
+__STATIC_INLINE void SPI_GDMACmd(SPI_TypeDef *SPIx, uint16_t SPI_GDMAReq, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_SPI_ALL_PERIPH(SPIx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+    assert_param(IS_SPI_GDMAREQ(SPI_GDMAReq));
+
+    if (NewState != DISABLE)
+    {
+        /* Enable the selected SPI GDMA request */
+        SPIx->DMACR |= SPI_GDMAReq;
+    }
+    else
+    {
+        /* Disable the selected SPI GDMA request */
+        SPIx->DMACR &= (uint16_t)~(SPI_GDMAReq);
+    }
+}
+/**
+ * \brief  Change SPI speed dynamically.
+ * \param[in] SPIx: Where x can be 0 or 1 to select the SPI peripheral.
+ * \param[in] prescaler: Value of prescaler.
+ *            This parameter can be one of the following values, refer to \ref SPI_BaudRate_Prescaler.
+ * \note  In addition to the reference values, you can also set custom frequency divisions that are multiples of an even number.
+ *        Note that only even multiples are allowed.
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void spi_demo(void)
+ * {
+ *     SPI_Change_CLK(SPI0, SPI_BaudRatePrescaler_2);
+ * }
+ * \endcode
+ */
+__STATIC_INLINE void SPI_Change_CLK(SPI_TypeDef *SPIx, uint32_t prescaler)
+{
+    SPIx->BAUDR = prescaler % 0xFFFF;
+}
+
+/**
+ * \brief   Set SPI Rx sample delay.
+ * \param[in] SPIx: Where x can be 0 or 1 to select the SPI peripheral.
+ * \param[in] delay: This parameter can be 0 to 255.
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void spi_demo(void)
+ * {
+ *     SPI_SetRxSampleDly(SPI0, 1);
+ * }
+ * \endcode
+ */
+__STATIC_INLINE void SPI_SetRxSampleDly(SPI_TypeDef *SPIx, uint32_t delay)
+{
+    SPIx->RX_SAMPLE_DLY = delay & 0xFF;
+}
+
+/** End of SPI_Exported_Functions
+  * \}
+  */
+
+/** End of SPI
+  * \}
+  */
+
+typedef struct
+{
+    uint32_t spi_reg[14];
+} SPIStoreReg_TypeDef;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTL876X_SPI_H_ */
+
+
+
diff --git a/bee/drivers/spi/src/device/rtl87x2g/rtl87x2g_spi.c b/bee/drivers/spi/src/device/rtl87x2g/rtl87x2g_spi.c
new file mode 100644
index 00000000..3374622f
--- /dev/null
+++ b/bee/drivers/spi/src/device/rtl87x2g/rtl87x2g_spi.c
@@ -0,0 +1,239 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *                        Header Files
+ *============================================================================*/
+#include "rtl_spi.h"
+#include "rtl_rcc.h"
+#include "app_section.h"
+
+/*============================================================================*
+ *                        Public Functions
+ *============================================================================*/
+void SPI_ClkDivConfig(SPI_TypeDef *SPIx, SPIClockDiv_TypeDef ClockDiv)
+{
+    assert_param(IS_SPI_DIV(ClockDiv));
+
+    /* Config SPI clock divider */
+    if (SPIx == SPI0 || SPIx == SPI0_HS)
+    {
+        /* disable clock first */
+        PERIBLKCTRL_PERI_CLK->u_310.BITS_310.spi0_div_en = 0;
+        PERIBLKCTRL_PERI_CLK->u_310.BITS_310.spi0_div_sel =  ClockDiv;
+        PERIBLKCTRL_PERI_CLK->u_310.BITS_310.spi0_div_en = 1;
+    }
+    else if (SPIx == SPI1)
+    {
+        PERIBLKCTRL_PERI_CLK->u_310.BITS_310.spi1_div_en = 0;
+        PERIBLKCTRL_PERI_CLK->u_310.BITS_310.spi1_div_sel =  ClockDiv;
+        PERIBLKCTRL_PERI_CLK->u_310.BITS_310.spi1_div_en = 1;
+
+    }
+    else if (SPIx == SPI0_SLAVE)
+    {
+        PERIBLKCTRL_PERI_CLK->u_310.BITS_310.spi0_s_div_en = 0;
+        PERIBLKCTRL_PERI_CLK->u_310.BITS_310.spi0_s_div_sel =  ClockDiv;
+        PERIBLKCTRL_PERI_CLK->u_310.BITS_310.spi0_s_div_en = 1;
+    }
+    return;
+}
+
+bool SPI_ClkGet(SPI_TypeDef *SPIx, SPIClockSrc_TypeDef *ClockSrc, SPIClockDiv_TypeDef *ClockDiv)
+{
+    if (SPIx == SPI0)
+    {
+        // read clk div
+        *ClockDiv = (PERIBLKCTRL_PERI_CLK->u_310.BITS_310.spi0_div_en == 0) ? SPI_CLOCK_DIVIDER_1 :
+                    (SPIClockDiv_TypeDef)PERIBLKCTRL_PERI_CLK->u_310.BITS_310.spi0_div_sel;
+        // read clk src
+        *ClockSrc = (PERIBLKCTRL_PERI_CLK->u_310.BITS_310.spi0_src_clk_sel1 == 0) ? SPI_CLOCK_SRC_40M :
+                    (SPIClockSrc_TypeDef)PERIBLKCTRL_PERI_CLK->u_310.BITS_310.spi0_src_clk_sel0;
+    }
+    else if (SPIx == SPI0_SLAVE)
+    {
+        // read clk div
+        *ClockDiv = (PERIBLKCTRL_PERI_CLK->u_310.BITS_310.spi0_s_div_en == 0) ? SPI_CLOCK_DIVIDER_1 :
+                    (SPIClockDiv_TypeDef)PERIBLKCTRL_PERI_CLK->u_310.BITS_310.spi0_s_div_sel;
+        // read clk src
+        *ClockSrc = (PERIBLKCTRL_PERI_CLK->u_310.BITS_310.spi0_s_src_clk_sel1 == 0) ? SPI_CLOCK_SRC_40M :
+                    (SPIClockSrc_TypeDef)PERIBLKCTRL_PERI_CLK->u_310.BITS_310.spi0_s_src_clk_sel0;
+    }
+    else if (SPIx == SPI1)
+    {
+        *ClockSrc = SPI_CLOCK_SRC_40M;
+        *ClockDiv = (PERIBLKCTRL_PERI_CLK->u_310.BITS_310.spi1_div_en == 0) ? SPI_CLOCK_DIVIDER_1 :
+                    (SPIClockDiv_TypeDef)PERIBLKCTRL_PERI_CLK->u_310.BITS_310.spi1_div_sel;
+    }
+    else
+    {
+        return false;
+    }
+
+    return true;
+}
+
+void SPI_ClkConfig(SPI_TypeDef *SPIx, SPIClockSrc_TypeDef ClockSrc, SPIClockDiv_TypeDef ClockDiv)
+{
+    assert_param(IS_SPI_DIV(ClockDiv));
+    assert_param(IS_SPI_CLK_SOURCE(ClockSrc));
+    if (SPIx == SPI0)
+    {
+        /* disable clock first */
+        PERIBLKCTRL_PERI_CLK->u_310.BITS_310.spi0_div_en = 0;
+        if (ClockSrc == SPI_CLOCK_SRC_40M)
+        {
+            PERIBLKCTRL_PERI_CLK->u_310.BITS_310.spi0_src_clk_sel1 = 0;
+        }
+        else if (ClockSrc == SPI_CLOCK_SRC_PLL1)
+        {
+            PERIBLKCTRL_PERI_CLK->u_310.BITS_310.spi0_src_clk_sel1 = 1;
+            PERIBLKCTRL_PERI_CLK->u_310.BITS_310.spi0_src_clk_sel0 = 0;
+        }
+        else if (ClockSrc == SPI_CLOCK_SRC_PLL2)
+        {
+            PERIBLKCTRL_PERI_CLK->u_310.BITS_310.spi0_src_clk_sel1 = 1;
+            PERIBLKCTRL_PERI_CLK->u_310.BITS_310.spi0_src_clk_sel0 = 1;
+        }
+        PERIBLKCTRL_PERI_CLK->u_310.BITS_310.spi0_div_sel =  ClockDiv;
+        PERIBLKCTRL_PERI_CLK->u_310.BITS_310.spi0_div_en = 1;
+    }
+    else if (SPIx == SPI0_SLAVE)
+    {
+        PERIBLKCTRL_PERI_CLK->u_310.BITS_310.spi0_s_div_en = 0;
+        if (ClockSrc == SPI_CLOCK_SRC_40M)
+        {
+            PERIBLKCTRL_PERI_CLK->u_310.BITS_310.spi0_s_src_clk_sel1 = 0;
+        }
+        else if (ClockSrc == SPI_CLOCK_SRC_PLL1)
+        {
+            PERIBLKCTRL_PERI_CLK->u_310.BITS_310.spi0_s_src_clk_sel1 = 1;
+            PERIBLKCTRL_PERI_CLK->u_310.BITS_310.spi0_s_src_clk_sel0 = 0;
+        }
+        else if (ClockSrc == SPI_CLOCK_SRC_PLL2)
+        {
+            PERIBLKCTRL_PERI_CLK->u_310.BITS_310.spi0_s_src_clk_sel1 = 1;
+            PERIBLKCTRL_PERI_CLK->u_310.BITS_310.spi0_s_src_clk_sel0 = 1;
+        }
+        PERIBLKCTRL_PERI_CLK->u_310.BITS_310.spi0_s_div_sel =  ClockDiv;
+        PERIBLKCTRL_PERI_CLK->u_310.BITS_310.spi0_s_div_en = 1;
+    }
+    else if (SPIx == SPI1)
+    {
+        PERIBLKCTRL_PERI_CLK->u_310.BITS_310.spi1_div_en = 0;
+        PERIBLKCTRL_PERI_CLK->u_310.BITS_310.spi1_div_sel =  ClockDiv;
+        PERIBLKCTRL_PERI_CLK->u_310.BITS_310.spi1_div_en = 1;
+    }
+    return;
+}
+
+void SPI_SPI0AHBBridgeConfig(FunctionalState NewState)
+{
+    if (NewState == ENABLE)
+    {
+        /* Open SPI0 AHB bridge*/
+        PERIBLKCTRL_PERI_CLK->u_310.BITS_310.spi0_hs_ck_en = 1;
+    }
+    else
+    {
+        /* Close SPI0 AHB bridge*/
+        PERIBLKCTRL_PERI_CLK->u_310.BITS_310.spi0_hs_ck_en = 0;
+    }
+}
+
+void SPI_ConfigAPHBridge(SPI_TypeDef *SPIx)
+{
+    if (SPIx == SPI0)
+    {
+        /*Open SPI0 APB Bridge for high speed*/
+        PERIBLKCTRL_PERI_CLK->u_310.BITS_310.spi0_brg_en = 1;
+    }
+    else if (SPIx == SPI1)
+    {
+        PERIBLKCTRL_PERI_CLK->u_310.BITS_310.spi1_brg_en = 1;
+    }
+    else if (SPIx == SPI0_HS)
+    {
+        /*Close SPI0 APB Bridge for high speed*/
+        PERIBLKCTRL_PERI_CLK->u_310.BITS_310.spi0_brg_en = 0;
+    }
+}
+
+
+RAM_FUNCTION
+void SPI_DLPSEnter(void *PeriReg, void *StoreBuf)
+{
+    SPI_TypeDef *SPIx = (SPI_TypeDef *)PeriReg;
+    SPIStoreReg_Typedef *store_buf = (SPIStoreReg_Typedef *)StoreBuf;
+
+    if (SPIx == SPI0)
+    {
+        RCC_PeriphClockCmd(APBPeriph_SPI0, APBPeriph_SPI0_CLOCK, ENABLE);
+    }
+    else if (SPIx == SPI0_SLAVE)
+    {
+        RCC_PeriphClockCmd(APBPeriph_SPI0_SLAVE, APBPeriph_SPI0_SLAVE_CLOCK, ENABLE);
+    }
+    else if (SPIx == SPI1)
+    {
+        RCC_PeriphClockCmd(APBPeriph_SPI1, APBPeriph_SPI1_CLOCK, ENABLE);
+    }
+
+    store_buf->spi_reg[0] = SPIx->SPI_M_S_CTRL0;        /*!< 0x00 */
+    store_buf->spi_reg[1] = SPIx->SPI_M_CTRL1;          /*!< 0x04 */
+    store_buf->spi_reg[2] = SPIx->SPI_SPIENR;           /*!< 0x08 */
+    store_buf->spi_reg[3] = SPIx->SPI_M_SER;            /*!< 0x10 */
+    store_buf->spi_reg[4] = SPIx->SPI_M_BAUDR;          /*!< 0x14 */
+    store_buf->spi_reg[5] = SPIx->SPI_TXFTLR;           /*!< 0x18 */
+    store_buf->spi_reg[6] = SPIx->SPI_RXFTLR;           /*!< 0x1C */
+    store_buf->spi_reg[7] = SPIx->SPI_M_S_IMR;          /*!< 0x2C */
+    store_buf->spi_reg[8] = SPIx->SPI_DMACR;            /*!< 0x4C */
+    store_buf->spi_reg[9] = SPIx->SPI_DMATDLR;          /*!< 0x50 */
+    store_buf->spi_reg[10] = SPIx->SPI_DMARDLR;         /*!< 0x54 */
+    store_buf->spi_reg[11] = SPIx->SPI_M_RSDR;          /*!< 0xF0 */
+}
+
+
+RAM_FUNCTION
+void SPI_DLPSExit(void *PeriReg, void *StoreBuf)
+{
+    SPI_TypeDef *SPIx = (SPI_TypeDef *)PeriReg;
+    SPIStoreReg_Typedef *store_buf = (SPIStoreReg_Typedef *)StoreBuf;
+
+    if (SPIx == SPI0)
+    {
+        RCC_PeriphClockCmd(APBPeriph_SPI0, APBPeriph_SPI0_CLOCK, ENABLE);
+    }
+    else if (SPIx == SPI0_SLAVE)
+    {
+        RCC_PeriphClockCmd(APBPeriph_SPI0_SLAVE, APBPeriph_SPI0_SLAVE_CLOCK, ENABLE);
+    }
+    else if (SPIx == SPI1)
+    {
+        RCC_PeriphClockCmd(APBPeriph_SPI1, APBPeriph_SPI1_CLOCK, ENABLE);
+    }
+    if (SPIx == SPI0_HS)
+    {
+        SPI_ConfigAPHBridge(SPIx);
+        SPI_SPI0AHBBridgeConfig(ENABLE);
+    }
+
+    SPIx->SPI_M_S_CTRL0 = store_buf->spi_reg[0];
+    SPIx->SPI_M_CTRL1   = store_buf->spi_reg[1];
+    SPIx->SPI_M_SER     = store_buf->spi_reg[3];
+    SPIx->SPI_M_BAUDR   = store_buf->spi_reg[4];
+    SPIx->SPI_TXFTLR    = store_buf->spi_reg[5];
+    SPIx->SPI_RXFTLR    = store_buf->spi_reg[6];
+    SPIx->SPI_M_S_IMR   = store_buf->spi_reg[7];
+    SPIx->SPI_DMACR     = store_buf->spi_reg[8];
+    SPIx->SPI_DMATDLR   = store_buf->spi_reg[9];
+    SPIx->SPI_DMARDLR   = store_buf->spi_reg[10];
+    SPIx->SPI_M_RSDR    = store_buf->spi_reg[11];
+
+    /* Enable the selected SPI peripheral */
+    SPIx->SPI_SPIENR    = store_buf->spi_reg[2];
+}
+
diff --git a/bee/drivers/spi/src/device/rtl87x2g/rtl_spi.c b/bee/drivers/spi/src/device/rtl87x2g/rtl_spi.c
new file mode 100644
index 00000000..98973863
--- /dev/null
+++ b/bee/drivers/spi/src/device/rtl87x2g/rtl_spi.c
@@ -0,0 +1,1027 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *                        Header Files
+ *============================================================================*/
+#include "rtl_spi.h"
+#include "rtl_rcc.h"
+
+#if SPI0_SUPPORT_MASTER_SLAVE
+#define SPI_NOT_SLAVE(SPIx)          (!SPI_IN_SLAVE_MODE(SPIx))
+#define SPI_CONFIGURED_MASTER(mode)  (mode == SPI_Mode_Master)
+#else
+#define SPI_NOT_SLAVE(SPIx)          (SPIx != SPI0_SLAVE)
+#define SPI_CONFIGURED_MASTER(mode)  (1)
+#endif
+
+#if SPI0_SUPPORT_MASTER_SLAVE
+extern void SPI_ConfigMasterSlave(SPIMode_Typedef SPI_Mode);
+#endif
+
+#if (SPI_SUPPORT_APH_BRIDGE_FOR_HIGH_SPEED == 1)
+extern void SPI_ConfigAPHBridge(SPI_TypeDef *SPIx);
+#endif
+
+#if (SPI0_SUPPORT_HS == 1)
+extern void SPI_SPI0AHBBridgeConfig(FunctionalState NewState);
+#endif
+
+/*============================================================================*
+ *                           Public Functions
+ *============================================================================*/
+/**
+  * \brief  Deinitializes the SPIx peripheral registers to their default reset values.
+  * \param  SPIx: Select the SPI peripheral. \ref SPI_Declaration
+  * \return None
+  */
+void SPI_DeInit(SPI_TypeDef *SPIx)
+{
+    /* Check the parameters */
+    assert_param(IS_SPI_ALL_PERIPH(SPIx));
+
+    switch ((uint32_t)SPIx)
+    {
+#ifdef SPI0
+    case (uint32_t)SPI0:
+        RCC_PeriphClockCmd(APBPeriph_SPI0, APBPeriph_SPI0_CLOCK, DISABLE);
+        break;
+#endif
+#ifdef SPI0_SLAVE
+    case (uint32_t)SPI0_SLAVE:
+        RCC_PeriphClockCmd(APBPeriph_SPI0_SLAVE, APBPeriph_SPI0_SLAVE_CLOCK, DISABLE);
+        break;
+#endif
+#ifdef SPI1
+    case (uint32_t)SPI1:
+        RCC_PeriphClockCmd(APBPeriph_SPI1, APBPeriph_SPI1_CLOCK, DISABLE);
+        break;
+#endif
+#ifdef SPI2
+    case (uint32_t)SPI2:
+        RCC_PeriphClockCmd(APBPeriph_SPI2, APBPeriph_SPI2_CLOCK, DISABLE);
+        break;
+#endif
+#ifdef SPI3
+    case (uint32_t)SPI3:
+        RCC_PeriphClockCmd(APBPeriph_SPI3, APBPeriph_SPI3_CLOCK, DISABLE);
+        break;
+#endif
+
+    default:
+        break;
+    }
+}
+
+/**
+  * \brief  Initializes the SPIx peripheral according to the specified
+  *         parameters in the SPI_InitStruct.
+  * \param  SPIx: Select the SPI peripheral. \ref SPI_Declaration
+  * \param  SPI_InitStruct: Pointer to a SPI_InitTypeDef structure that
+  *         contains the configuration information for the specified SPI peripheral.
+  * \return None
+  */
+void SPI_Init(SPI_TypeDef *SPIx, SPI_InitTypeDef *SPI_InitStruct)
+{
+    /* Check the parameters */
+    assert_param(IS_SPI_ALL_PERIPH(SPIx));
+    assert_param(IS_SPI_DIRECTION_MODE(SPI_InitStruct->SPI_Direction));
+    assert_param(IS_SPI_DATASIZE(SPI_InitStruct->SPI_DataSize));
+    assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL));
+    assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA));
+    assert_param(IS_SPI_FRAME_FORMAT(SPI_InitStruct->SPI_FrameFormat));
+    assert_param(IS_SPI_BAUDRATE_PRESCALER(SPI_InitStruct->SPI_BaudRatePrescaler));
+
+    /* Disable SPI device before change configuration */
+    SPI_SPIENR_TypeDef spi_0x08 = {.d32 = SPIx->SPI_SPIENR};
+    spi_0x08.b.spi_en = 0;
+    SPIx->SPI_SPIENR = spi_0x08.d32;
+
+    /* Configure SPI Master mode if select SPI0, SPI1, SPI2 or SPI3 */
+    if (IS_SPIM_PERIPH(SPIx))
+    {
+#if (SPI0_SUPPORT_MASTER_SLAVE == 1)
+        if (SPIx == SPI0)
+        {
+            SPI_ConfigMasterSlave(SPI_InitStruct->SPI_Mode);
+        }
+#endif
+
+#if (SPI_SUPPORT_APH_BRIDGE_FOR_HIGH_SPEED == 1)
+        SPI_ConfigAPHBridge(SPIx);
+#endif
+
+#if (SPI0_SUPPORT_HS == 1)
+        if (SPIx == SPI0)
+        {
+            SPI_SPI0AHBBridgeConfig(DISABLE);
+        }
+        else if (SPIx == SPI0_HS)
+        {
+            SPI_SPI0AHBBridgeConfig(ENABLE);
+        }
+#endif
+        /* Configure SPI master mode parameters */
+        SPI_M_CTRL0_TypeDef spi_0x00 = {.d32 = SPIx->SPI_M_S_CTRL0};
+        spi_0x00.b.frf = SPI_InitStruct->SPI_FrameFormat;
+        spi_0x00.b.scph = SPI_InitStruct->SPI_CPHA;
+        spi_0x00.b.scpol = SPI_InitStruct->SPI_CPOL;
+        spi_0x00.b.tmod = SPI_InitStruct->SPI_Direction;
+        spi_0x00.b.SPI_DFS_BIT_FIELD = SPI_InitStruct->SPI_DataSize;
+        spi_0x00.b.sste = SPI_InitStruct->SPI_ToggleEn;
+        SPIx->SPI_M_S_CTRL0 = spi_0x00.d32;
+#if (SPI0_SUPPORT_MASTER_SLAVE == 1)
+        if (SPI_InitStruct->SPI_Mode == SPI_Mode_Slave)
+        {
+            SPI_S_CTRL0_TypeDef spi_0x00 = {.d32 = SPIx->SPI_M_S_CTRL0};
+            spi_0x00.b.slv_oe = 0;
+            spi_0x00.b.dfs = SPI_InitStruct->SPI_DataSize;
+            SPIx->SPI_M_S_CTRL0 = spi_0x00.d32;
+        }
+#endif
+
+        /* Set master clock divider */
+        SPI_M_BAUDR_TypeDef spi_0x14 = {.d32 = SPIx->SPI_M_BAUDR};
+        spi_0x14.b.sckdv = SPI_InitStruct->SPI_BaudRatePrescaler % 0xFFFF;
+        SPIx->SPI_M_BAUDR = spi_0x14.d32;
+
+        /* Enable slave Select function in master mode */
+        if (SPI_CONFIGURED_MASTER(SPI_InitStruct->SPI_Mode))
+        {
+            SPI_M_SER_TypeDef spi_0x10 = {.d32 = SPIx->SPI_M_SER};
+            spi_0x10.b.ser = 1;
+            SPIx->SPI_M_SER = spi_0x10.d32;
+        }
+
+        /* Set read length in SPI EEPROM & rx only mode */
+        if ((SPI_InitStruct->SPI_Direction == SPI_Direction_RxOnly) || \
+            (SPI_InitStruct->SPI_Direction == SPI_Direction_EEPROM))
+        {
+            SPI_M_CTRL1_TypeDef spi_0x04 = {.d32 = SPIx->SPI_M_CTRL1};
+            if (SPI_InitStruct->SPI_RXNDF > 0)
+            {
+                spi_0x04.b.ndf = SPI_InitStruct->SPI_RXNDF - 1;
+            }
+            SPIx->SPI_M_CTRL1 = spi_0x04.d32;
+        }
+#if (SPI_SUPPORT_WRAP_MODE == 1)
+        else if ((SPI_InitStruct->SPI_Direction == SPI_Direction_TxOnly) || \
+                 (SPI_InitStruct->SPI_Direction == SPI_Direction_FullDuplex))
+        {
+            if (SPI_InitStruct->SPI_WrapModeEn)
+            {
+                SPIx->SPI_WRAP_CTRL = 0;
+
+                /* Wrapper mode enable */
+                SPI_WRAP_CTRL_TypeDef spi_0x200 = {.d32 = SPIx->SPI_WRAP_CTRL};
+                SPI_WRAP_TXFTLR_TypeDef spi_0x204 = {.d32 = SPIx->SPI_WRAP_TXFTLR};
+                spi_0x200.b.wrap_ctrl_mode = 1;
+                if (SPI_InitStruct->SPI_TXNDF > 0)
+                {
+                    spi_0x200.b.mst_tx_ndf = SPI_InitStruct->SPI_TXNDF - 1;
+                }
+                spi_0x204.b.tx_fifo_tl = SPI_InitStruct->SPI_TxThresholdLevel;
+
+                SPIx->SPI_WRAP_CTRL = spi_0x200.d32;
+                SPIx->SPI_WRAP_TXFTLR = spi_0x204.d32;
+
+                if (SPI_InitStruct->SPI_WrapModeDmaEn)
+                {
+                    /* enable tx ndf dma */
+                    SPI_WRAP_DMACR_TypeDef spi_0x220 = {.d32 = SPIx->SPI_WRAP_DMACR};
+                    SPI_WRAP_DMATDLR_TypeDef spi_0x224 = {.d32 = SPIx->SPI_WRAP_DMATDLR};
+                    spi_0x220.b.tx_dma_en = 1;
+                    spi_0x224.b.dma_tx_dl = SPI_InitStruct->SPI_TxNdfWaterlevel;
+                    SPIx->SPI_WRAP_DMACR = spi_0x220.d32;
+                    SPIx->SPI_WRAP_DMATDLR = spi_0x224.d32;
+                }
+            }
+        }
+
+        SPI_WRAP_CTRL_TypeDef spi_0x200 = {.d32 = SPIx->SPI_WRAP_CTRL};
+        spi_0x200.b.cs_inv_en = SPI_InitStruct->SPI_CSHighActiveEn;
+        SPIx->SPI_WRAP_CTRL = spi_0x200.d32;
+#endif
+    }
+#if !SPI0_SUPPORT_MASTER_SLAVE
+    /* Configure SPI Slave mode if select SPI0_SLAVE */
+    else if (SPIx == SPI0_SLAVE)
+    {
+        /* Configure SPI slave mode parameters */
+        SPI_S_CTRL0_TypeDef spi_0x00 = {.d32 = SPIx->SPI_M_S_CTRL0};
+        spi_0x00.b.scph = SPI_InitStruct->SPI_CPHA;
+        spi_0x00.b.scpol = SPI_InitStruct->SPI_CPOL;
+        spi_0x00.b.dfs = SPI_InitStruct->SPI_DataSize;
+#if (SPI_SUPPORT_SWAP == 1)
+        spi_0x00.b.tx_byte_swap = SPI_InitStruct->SPI_SwapTxByteEn;
+        spi_0x00.b.tx_bit_swap = SPI_InitStruct->SPI_SwapTxBitEn;
+        spi_0x00.b.rx_byte_swap = SPI_InitStruct->SPI_SwapRxByteEn;
+        spi_0x00.b.rx_bit_swap = SPI_InitStruct->SPI_SwapRxBitEn;
+#endif
+
+        /* Enable slave output */
+        spi_0x00.b.slv_oe = 0;
+        SPIx->SPI_M_S_CTRL0 = spi_0x00.d32;
+    }
+#endif
+    /* Set Tx empty level */
+    SPI_TXFTLR_TypeDef spi_0x18 = {.d32 = SPIx->SPI_TXFTLR};
+    spi_0x18.b.tft = SPI_InitStruct->SPI_TxThresholdLevel;
+    SPIx->SPI_TXFTLR = spi_0x18.d32;
+
+    /*set Rx full level*/
+    SPI_RXFTLR_TypeDef spi_0x1c = {.d32 = SPIx->SPI_RXFTLR};
+    spi_0x1c.b.rft = SPI_InitStruct->SPI_RxThresholdLevel;
+
+    /* Config SPI dma mode */
+    SPI_DMACR_TypeDef spi_0x4c = {.d32 = SPIx->SPI_DMACR};
+    spi_0x4c.b.rdmae = SPI_InitStruct->SPI_RxDmaEn;
+    spi_0x4c.b.tdmae = SPI_InitStruct->SPI_TxDmaEn;
+    SPIx->SPI_DMACR = spi_0x4c.d32;
+
+    /* Config SPI waterlevel */
+    SPI_DMATDLR_TypeDef spi_0x50 = {.d32 = SPIx->SPI_DMATDLR};
+    SPI_DMARDLR_TypeDef spi_0x54 = {.d32 = SPIx->SPI_DMARDLR};
+    spi_0x50.b.dmatdl = SPI_InitStruct->SPI_TxWaterlevel;
+    spi_0x54.b.dmardl = SPI_InitStruct->SPI_RxWaterlevel;
+    SPIx->SPI_DMATDLR = spi_0x50.d32;
+
+    if (SPI_InitStruct->SPI_RxDmaEn)
+    {
+        /* DMA mode should config DMARDLR later if open AHB */
+        SPIx->SPI_RXFTLR = spi_0x1c.d32;
+        SPIx->SPI_DMARDLR = spi_0x54.d32;
+    }
+    else
+    {
+        /* CPU mode should config RXFTLR later if open AHB */
+        SPIx->SPI_DMARDLR = spi_0x54.d32;
+        SPIx->SPI_RXFTLR = spi_0x1c.d32;
+    }
+
+    /* Mask SPI interrupt in REG_DW_SSI_IMR */
+    SPIx->SPI_M_S_IMR = 0;
+}
+
+/**
+  * \brief  Fills each SPI_InitStruct member with its default value.
+  * \param  SPI_InitStruct : Pointer to a SPI_InitTypeDef structure which will be initialized.
+  * \return None
+  */
+void SPI_StructInit(SPI_InitTypeDef *SPI_InitStruct)
+{
+    /* TX and RX Mode */
+    SPI_InitStruct->SPI_Direction         = SPI_Direction_FullDuplex;
+    /* Number of data to read in RX/EEPROM Mode */
+    SPI_InitStruct->SPI_RXNDF              = 1;
+    /* 8-bit serial data transfer */
+    SPI_InitStruct->SPI_DataSize          = SPI_DataSize_8b;
+    /* Inactive state of clock is high */
+    SPI_InitStruct->SPI_CPOL              = SPI_CPOL_High;
+    /* Serial clock toggles in first of first data bit */
+    SPI_InitStruct->SPI_CPHA              = SPI_CPHA_2Edge;
+    /* Motorola format */
+    SPI_InitStruct->SPI_FrameFormat       = SPI_Frame_Motorola;
+    /* Speed = SPI Clock source/ SPI_ClkDIV*/
+    SPI_InitStruct->SPI_BaudRatePrescaler = 128;
+#if (SPI0_SUPPORT_MASTER_SLAVE == 1)
+    SPI_InitStruct->SPI_Mode = SPI_Mode_Master;
+#endif
+#if (SPI_SUPPORT_SWAP == 1)
+    /* Reverse the rx bit or not */
+    SPI_InitStruct->SPI_SwapTxBitEn       = DISABLE;
+    SPI_InitStruct->SPI_SwapRxBitEn       = DISABLE;
+    SPI_InitStruct->SPI_SwapTxByteEn      = DISABLE;
+    SPI_InitStruct->SPI_SwapRxByteEn      = DISABLE;
+#endif
+    /* Toggle CS line or not */
+    SPI_InitStruct->SPI_ToggleEn          = DISABLE;
+#if (SPI_SUPPORT_WRAP_MODE == 1)
+    /* Number of data to read in TX/FullDuplex Mode */
+    SPI_InitStruct->SPI_TXNDF             = 1;
+    /* Enable CS high active or not */
+    SPI_InitStruct->SPI_CSHighActiveEn    = DISABLE;
+    /* Disable tx ndf */
+    SPI_InitStruct->SPI_WrapModeEn     = DISABLE;
+    /* Disable dma */
+    SPI_InitStruct->SPI_WrapModeDmaEn  = DISABLE;
+    /* SPI Tx waterlevel, should be less than fifo threshold.
+       The best value is SPI FIFO Depth - GDMA Msize */
+    SPI_InitStruct->SPI_TxNdfWaterlevel   =  SPI_TX_FIFO_SIZE - 1;
+#endif
+    /* Tx fifo depth: 32/64 bytes */
+    SPI_InitStruct->SPI_TxThresholdLevel  = 1;
+    /* Rx fifo depth: 32/64 bytes */
+    SPI_InitStruct->SPI_RxThresholdLevel  = 0;
+    /* Disable dma */
+    SPI_InitStruct->SPI_TxDmaEn           = DISABLE;
+    SPI_InitStruct->SPI_RxDmaEn           = DISABLE;
+    /* SPI Tx waterlevel, should be less than fifo threshold.
+       The best value is SPI FIFO Depth - GDMA Msize */
+    SPI_InitStruct->SPI_TxWaterlevel      = SPI_TX_FIFO_SIZE - 1;
+    /* SPI Rx waterlevel, should be less than fifo threshold.
+       The best value is GDMA Msize */
+    SPI_InitStruct->SPI_RxWaterlevel      = 1;
+}
+
+/**
+  * \brief  Enable or disable the specified SPI peripheral.
+  * \param  SPIx: Select the SPI peripheral. \ref SPI_Declaration
+  * \param  NewState: New state of the SPIx peripheral.
+  *         This parameter can be: ENABLE or DISABLE.
+  * \return None
+  */
+void SPI_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_SPI_ALL_PERIPH(SPIx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    SPI_SPIENR_TypeDef spi_0x08 = {.d32 = SPIx->SPI_SPIENR};
+    spi_0x08.b.spi_en = NewState;
+    SPIx->SPI_SPIENR = spi_0x08.d32;
+}
+
+/**
+  * \brief  Transmits a number of bytes through the SPIx peripheral.
+  * \param  SPIx: Select the SPI peripheral. \ref SPI_Declaration
+  * \param  pBuf : Bytes to be transmitted.
+  * \param  len : Byte length to be transmitted.
+  * \return None
+  */
+void SPI_SendBuffer(SPI_TypeDef *SPIx, uint8_t *pBuf, uint16_t len)
+{
+    uint16_t i = 0;
+
+    /* Check the parameters */
+    assert_param(IS_SPI_ALL_PERIPH(SPIx));
+
+#if (SPI_SUPPORT_WRAP_MODE == 1)
+    SPI_WRAP_CTRL_TypeDef spi_0x200 = {.d32 = SPIx->SPI_WRAP_CTRL};
+    if (spi_0x200.b.wrap_ctrl_mode && SPI_NOT_SLAVE(SPIx))
+    {
+        for (i = 0; i < len; i++)
+        {
+            /* Read TFNF bit status in SPI_SR register: SET is Tx FIFO is not full */
+            while (!(SPIx->SPI_WRAP_SR & SPI_FLAG_TFNF));
+            SPIx->SPI_DR[0] = (*pBuf++);
+        }
+        return;
+    }
+#endif
+    for (i = 0; i < len; i++)
+    {
+        /* Read TFNF bit status in SPI_SR register: SET is Tx FIFO is not full */
+        while (SPI_NOT_SLAVE(SPIx) && !(SPIx->SPI_M_S_SR & SPI_FLAG_TFNF));
+        SPIx->SPI_DR[0] = (*pBuf++);
+    }
+}
+
+/**
+  * \brief  Transmits a number of halfwords through the SPIx peripheral.
+  * \param  SPIx: Select the SPI peripheral. \ref SPI_Declaration
+  * \param  pBuf : Halfwords to be transmitted.
+  * \param  len: Halfword length to be transmitted.
+  * \return None
+  */
+void SPI_SendHalfWord(SPI_TypeDef *SPIx, uint16_t *pBuf, uint16_t len)
+{
+    uint16_t i = 0;
+
+    /* Check the parameters */
+    assert_param(IS_SPI_ALL_PERIPH(SPIx));
+
+#if (SPI_SUPPORT_WRAP_MODE == 1)
+    SPI_WRAP_CTRL_TypeDef spi_0x200 = {.d32 = SPIx->SPI_WRAP_CTRL};
+    if (spi_0x200.b.wrap_ctrl_mode && SPI_NOT_SLAVE(SPIx))
+    {
+        for (i = 0; i < len; i++)
+        {
+            /* Read TFNF bit status in SPI_SR register: SET is Tx FIFO is not full */
+            while (!(SPIx->SPI_WRAP_SR & SPI_FLAG_TFNF));
+            SPIx->SPI_DR[0] = (*pBuf++);
+        }
+        return;
+    }
+#endif
+    for (i = 0; i < len; i++)
+    {
+        /* Read TFNF bit status in SPI_SR register: SET is Tx FIFO is not full */
+        while (SPI_NOT_SLAVE(SPIx) && !(SPIx->SPI_M_S_SR & SPI_FLAG_TFNF));
+        SPIx->SPI_DR[0] = (*pBuf++);
+    }
+}
+
+/**
+  * \brief  Transmits a number of words through the SPIx peripheral.
+  * \param  SPIx: Select the SPI peripheral. \ref SPI_Declaration
+  * \param  pBuf : Words to be transmitted.
+  * \param  len: Word length to be transmitted.
+  * \return None
+  */
+void SPI_SendWord(SPI_TypeDef *SPIx, uint32_t *pBuf, uint16_t len)
+{
+    uint16_t i = 0;
+
+    /* Check the parameters */
+    assert_param(IS_SPI_ALL_PERIPH(SPIx));
+
+#if (SPI_SUPPORT_WRAP_MODE == 1)
+    SPI_WRAP_CTRL_TypeDef spi_0x200 = {.d32 = SPIx->SPI_WRAP_CTRL};
+    if (spi_0x200.b.wrap_ctrl_mode && SPI_NOT_SLAVE(SPIx))
+    {
+        for (i = 0; i < len; i++)
+        {
+            /* Read TFNF bit status in SPI_SR register: SET is Tx FIFO is not full */
+            while (!(SPIx->SPI_WRAP_SR & SPI_FLAG_TFNF));
+            SPIx->SPI_DR[0] = (*pBuf++);
+        }
+        return;
+    }
+#endif
+    for (i = 0; i < len; i++)
+    {
+        /* Read TFNF bit status in SPI_SR register: SET is Tx FIFO is not full */
+        while (SPI_NOT_SLAVE(SPIx) && !(SPIx->SPI_M_S_SR & SPI_FLAG_TFNF));
+        SPIx->SPI_DR[0] = (*pBuf++);
+    }
+}
+
+/**
+  * \brief  Clear the specified SPI interrupt.
+  * \param  SPIx: Select the SPI peripheral. \ref SPI_Declaration
+  * \param  SPI_IT: Specifies the SPI interrupt to clear.
+  *         This parameter can be one of the following values:
+  *         \arg SPI_INT_TXO: Transmit FIFO Overflow Interrupt .
+  *         \arg SPI_INT_RXO: Receive FIFO Overflow Interrupt.
+  *         \arg SPI_INT_RXU: Receive FIFO Underflow Interrupt.
+  *         \arg SPI_INT_MST: Multi-Master Contention Interrupt.
+  *         \arg SPI_INT_FAE: TX Frame Alignment Interrupt.
+  *         \arg SPI_INT_TUF: Transmit FIFO Underflow Interrupt.
+  *         \arg SPI_INT_RIG: Rising edge detect Interrupt.
+  *         \arg SPI_INT_WRAP_TXE: TX NDF mode FIFO Transmit FIFO Empty Interrupt.
+  *         \arg SPI_INT_WRAP_TXO: TX NDF mode FIFO Overflow Interrupt.
+  *         \arg SPI_INT_WRAP_TXD: TX NDF mode transmit done Interrupt.
+  * \return None.
+  */
+void SPI_ClearINTPendingBit(SPI_TypeDef *SPIx, uint16_t SPI_IT)
+{
+    /* Check the parameters */
+    assert_param(IS_SPI_ALL_PERIPH(SPIx));
+    assert_param(IS_SPI_CONFIG_IT(SPI_IT));
+
+    if (SPI_IT & SPI_INT_TXO)
+    {
+        (void)SPIx->SPI_TXOICR;
+    }
+
+    if (SPI_IT & SPI_INT_RXO)
+    {
+        (void)SPIx->SPI_RXOICR;
+    }
+
+    if (SPI_IT & SPI_INT_RXU)
+    {
+        (void)SPIx->SPI_RXUICR;
+    }
+
+    if (SPI_IT & SPI_INT_FAE)
+    {
+        (void)SPIx->SPI_M_S_MSTICR_FAEICR;
+    }
+
+    if (SPI_IT & SPI_INT_TUF)
+    {
+        (void)SPIx->SPI_M_S_IDR_TXUICR;
+    }
+
+    if (SPI_IT & SPI_INT_RIG)
+    {
+        (void)SPIx->SPI_M_S_VERSION_ID_SSRICR;
+    }
+
+#if (SPI_SUPPORT_WRAP_MODE == 1)
+    if (SPI_IT & (SPI_INT_WRAP_TXD | SPI_INT_WRAP_TXO))
+    {
+        (void)SPIx->SPI_WRAP_ICR;
+    }
+#endif
+}
+
+/**
+  * \brief  Transmits a data through the SPIx peripheral.
+  * \param  SPIx: Select the SPI peripheral. \ref SPI_Declaration
+  * \param  Data: Data to be transmitted.
+  * \return None.
+  */
+void SPI_SendData(SPI_TypeDef *SPIx, uint32_t Data)
+{
+    /* Check the parameters */
+    assert_param(IS_SPI_ALL_PERIPH(SPIx));
+
+#if (SPI_SUPPORT_WRAP_MODE == 1)
+    SPI_WRAP_CTRL_TypeDef spi_0x200 = {.d32 = SPIx->SPI_WRAP_CTRL};
+    if (spi_0x200.b.wrap_ctrl_mode && SPI_NOT_SLAVE(SPIx))
+    {
+        while (!(SPIx->SPI_WRAP_SR & SPI_FLAG_TFNF));
+        SPIx->SPI_DR[0] = Data;
+        return;
+    }
+#endif
+    while (SPI_NOT_SLAVE(SPIx) && !(SPIx->SPI_M_S_SR & SPI_FLAG_TFNF));
+    SPIx->SPI_DR[0] = Data;
+}
+
+/**
+  * \brief  Received data by the SPI peripheral.
+  * \param  SPIx: Select the SPI peripheral. \ref SPI_Declaration
+  * \return The most recent received data.
+  */
+uint32_t SPI_ReceiveData(SPI_TypeDef *SPIx)
+{
+    /* Check the parameters */
+    assert_param(IS_SPI_ALL_PERIPH(SPIx));
+
+    return (uint32_t)SPIx->SPI_DR[0];
+}
+
+/**
+  * \brief  Get data length in Tx FIFO through the SPIx peripheral.
+  * \param  SPIx: Select the SPI peripheral. \ref SPI_Declaration
+  * \return Data length in Tx FIFO.
+  */
+uint8_t SPI_GetTxFIFOLen(SPI_TypeDef *SPIx)
+{
+    /* Check the parameters */
+    assert_param(IS_SPI_ALL_PERIPH(SPIx));
+
+    SPI_TXFLR_TypeDef spi_0x20 = {.d32 = SPIx->SPI_TXFLR};
+    return spi_0x20.b.txtfl;
+}
+
+/**
+  * \brief  Get data length in Rx FIFO through the SPIx peripheral.
+  * \param  SPIx: Select the SPI peripheral. \ref SPI_Declaration
+  * \return Data length in Rx FIFO.
+  */
+uint8_t SPI_GetRxFIFOLen(SPI_TypeDef *SPIx)
+{
+    /* Check the parameters */
+    assert_param(IS_SPI_ALL_PERIPH(SPIx));
+
+    SPI_RXFLR_TypeDef spi_0x24 = {.d32 = SPIx->SPI_RXFLR};
+    return spi_0x24.b.rxtfl;
+}
+
+/**
+  * \brief  Change SPI direction mode.
+  * \param  SPIx: Select the SPI peripheral. \ref SPI_Declaration
+  * \param  dir: Value of direction mode.
+  * \return None.
+  */
+void SPI_ChangeDirection(SPI_TypeDef *SPIx, uint16_t dir)
+{
+    /* Check the parameters */
+    assert_param(IS_SPI_ALL_PERIPH(SPIx));
+    assert_param(IS_SPI_DIRECTION_MODE(dir));
+
+    /* Disable the selected SPI peripheral */
+    SPI_SPIENR_TypeDef spi_0x08 = {.d32 = SPIx->SPI_SPIENR};
+    spi_0x08.b.spi_en = 0;
+    SPIx->SPI_SPIENR = spi_0x08.d32;
+
+    /* Change SPI direction mode */
+    SPI_M_CTRL0_TypeDef spi_0x00 = {.d32 = SPIx->SPI_M_S_CTRL0};
+    spi_0x00.b.tmod = dir;
+    SPIx->SPI_M_S_CTRL0 = spi_0x00.d32;
+
+    /* Enable the selected SPI peripheral */
+    spi_0x08.b.spi_en = 1;
+    SPIx->SPI_SPIENR = spi_0x08.d32;
+}
+
+/**
+  * \brief  Set read Data length only in EEPROM mode through the SPIx peripheral,which
+            enables you to receive up to 64 KB of data in a continuous transfer.
+  * \param  SPIx: Select the SPI peripheral. \ref SPI_Declaration
+  * \param  len: Length of read data which can be 1 to 65536.
+  * \return None.
+  */
+void SPI_SetReadLen(SPI_TypeDef *SPIx, uint16_t len)
+{
+    /* Check the parameters */
+    assert_param(IS_SPI_ALL_PERIPH(SPIx));
+
+    /* Disable the selected SPI peripheral */
+    SPI_SPIENR_TypeDef spi_0x08 = {.d32 = SPIx->SPI_SPIENR};
+    spi_0x08.b.spi_en = 0;
+    SPIx->SPI_SPIENR = spi_0x08.d32;
+
+    /* Set read length in SPI EEPROM or RX only mode */
+    SPI_M_CTRL1_TypeDef spi_0x04 = {.d32 = SPIx->SPI_M_CTRL1};
+    spi_0x04.b.ndf = len - 1;
+    SPIx->SPI_M_CTRL1 = spi_0x04.d32;
+
+    /* Enable the selected SPI peripheral */
+    spi_0x08.b.spi_en = 1;
+    SPIx->SPI_SPIENR = spi_0x08.d32;
+}
+
+/**
+  * \brief  Set cs number through the SPIx peripheral.
+  * \param  SPIx: Select the SPI peripheral. \ref SPI_Declaration
+  * \param  number: Number can be 0 to 2.
+  * \return None.
+ */
+void SPI_SetCSNumber(SPI_TypeDef *SPIx, uint8_t number)
+{
+    /* Check the parameters */
+    assert_param(IS_SPI_ALL_PERIPH(SPIx));
+
+    /* set cs number */
+    SPIx->SPI_M_SER = BIT(number);
+}
+
+/**
+  * \brief  Check whether the specified SPI interrupt is set.
+  * \param  SPIx: Select the SPI peripheral. \ref SPI_Declaration
+  * \param  SPI_IT: Specifies the SPI interrupt to check.
+  *         This parameter can be one of the following values:
+  *         \arg SPI_INT_MST: Multi-Master Contention Interrupt.
+  *         \arg SPI_INT_FAE: TX Frame Alignment Interrupt.
+  *         \arg SPI_INT_RXF: Receive FIFO Full Interrupt.
+  *         \arg SPI_INT_RXO: Receive FIFO Overflow Interrupt.
+  *         \arg SPI_INT_RXU: Receive FIFO Underflow Interrupt.
+  *         \arg SPI_INT_TXO: Transmit FIFO Overflow Interrupt .
+  *         \arg SPI_INT_TXE: Transmit FIFO Empty Interrupt.
+  *         \arg SPI_INT_WRAP_TXD: TX NDF mode transmit done Interrupt.
+  * \return The new state of SPI_IT (SET or RESET).
+  */
+ITStatus SPI_GetINTStatus(SPI_TypeDef *SPIx, uint32_t SPI_IT)
+{
+    /* Check the parameters */
+    assert_param(IS_SPI_ALL_PERIPH(SPIx));
+    assert_param(IS_SPI_CONFIG_IT(SPI_IT));
+
+    ITStatus bit_status = RESET;
+
+#if (SPI_SUPPORT_WRAP_MODE == 1)
+    SPI_WRAP_CTRL_TypeDef spi_0x200 = {.d32 = SPIx->SPI_WRAP_CTRL};
+    if (SPI_IT & (SPI_INT_WRAP_TXE | SPI_INT_WRAP_TXO | SPI_INT_WRAP_TXD))
+    {
+        if (spi_0x200.b.wrap_ctrl_mode)
+        {
+            if (SPIx->SPI_WRAP_ISR & (SPI_IT >> 8))
+            {
+                bit_status = SET;
+            }
+        }
+        return  bit_status;
+    }
+#endif
+    /* Check the status of the specified SPI flag */
+    if ((SPIx->SPI_M_S_ISR & SPI_IT) != (uint32_t)RESET)
+    {
+        bit_status = SET;
+    }
+
+    /* Return the SPI_IT status */
+    return  bit_status;
+}
+
+/**
+  * \brief  Enable or disable the specified SPI interrupt source.
+  * \param  SPIx: Select the SPI peripheral. \ref SPI_Declaration
+  * \param  SPI_IT: Specifies the SPI interrupt source to be enabled or disabled.
+  *         This parameter can be one of the following values:
+  *         \arg SPI_INT_TXE: Transmit FIFO empty interrupt.
+  *         \arg SPI_INT_TXO: Transmit FIFO overflow interrupt.
+  *         \arg SPI_INT_RXU: Receive FIFO underflow interrupt.
+  *         \arg SPI_INT_RXO: Receive FIFO overflow interrupt.
+  *         \arg SPI_INT_RXF: Receive FIFO full interrupt.
+  *         \arg SPI_INT_MST: Multi-Master Contention Interrupt.
+  *         \arg SPI_INT_FAE: TX Frame Alignment interrupt.
+  *         \arg SPI_INT_TUF: Transmit FIFO underflow interrupt.
+  *         \arg SPI_INT_RIG: Rising edge detect interrupt.
+  *         \arg SPI_INT_WRAP_TXD: TX NDF mode transmit done Interrupt.
+  * \param  NewState: New state of the specified SPI interrupt source.
+  *         This parameter can be: ENABLE or DISABLE.
+  * \return None
+  */
+void SPI_INTConfig(SPI_TypeDef *SPIx, uint16_t SPI_IT, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_SPI_ALL_PERIPH(SPIx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+    assert_param(IS_SPI_CONFIG_IT(SPI_IT));
+
+#if (SPI_SUPPORT_WRAP_MODE == 1)
+    SPI_WRAP_CTRL_TypeDef spi_0x200 = {.d32 = SPIx->SPI_WRAP_CTRL};
+    if (SPI_IT & (SPI_INT_WRAP_TXE | SPI_INT_WRAP_TXO | SPI_INT_WRAP_TXD))
+    {
+        if (spi_0x200.b.wrap_ctrl_mode)
+        {
+            if (NewState != DISABLE)
+            {
+                SPIx->SPI_WRAP_IMR |= (SPI_IT >> 8);
+            }
+            else
+            {
+                SPIx->SPI_WRAP_IMR &= ~(SPI_IT >> 8);
+            }
+        }
+    }
+#endif
+    if (NewState != DISABLE)
+    {
+        SPIx->SPI_M_S_IMR |= (SPI_IT & 0xff);
+    }
+    else
+    {
+        SPIx->SPI_M_S_IMR &= ~(SPI_IT & 0xff);
+    }
+}
+
+
+/**
+ * \brief  Check whether the specified SPI flag is set.
+ *
+ * \param  SPIx: Select the SPI peripheral. \ref SPI_Declaration
+ * \param  SPI_FLAG: Specifies the SPI flag to check.
+ *         This parameter can be one of the following values:
+ *         \arg SPI_FLAG_DCOL: Data Collision Error flag.Set if it is actively transmitting in master mode when another master selects this device as a slave.
+ *         \arg SPI_FLAG_TXE: Transmission error flag.Set if the transmit FIFO is empty when a transfer is started in slave mode.
+ *         \arg SPI_FLAG_RFF: Receive FIFO full flag. Set if the receive FIFO is completely full.
+ *         \arg SPI_FLAG_RFNE: Receive FIFO Not Empty flag.Set if receive FIFO is not empty.
+ *         \arg SPI_FLAG_TFE: Transmit FIFO Empty flag.Set if transmit FIFO is empty.
+ *         \arg SPI_FLAG_TFNF: Transmit FIFO Not Full flag.Set if transmit FIFO is not full.
+ *         \arg SPI_FLAG_BUSY: SPI Busy flag.Set if it is actively transferring data.reset if it is idle or disabled.
+ *
+ * \return The new state of SPI_FLAG (SET or RESET).
+ */
+FlagStatus SPI_GetFlagState(SPI_TypeDef *SPIx, uint16_t SPI_FLAG)
+{
+    /* Check the parameters */
+    assert_param(IS_SPI_ALL_PERIPH(SPIx));
+    assert_param(IS_SPI_GET_FLAG(SPI_FLAG));
+
+    FlagStatus bitstatus = RESET;
+
+#if (SPI_SUPPORT_WRAP_MODE == 1)
+    SPI_WRAP_CTRL_TypeDef spi_0x200 = {.d32 = SPIx->SPI_WRAP_CTRL};
+    if ((SPI_FLAG & (SPI_FLAG_WRAP_CS_EN | SPI_FLAG_WRAP_TFNF |
+                     SPI_FLAG_WRAP_TFE)))
+    {
+        if ((spi_0x200.b.wrap_ctrl_mode))
+        {
+            if (SPIx->SPI_WRAP_SR & (SPI_FLAG >> 8))
+            {
+                bitstatus = SET;
+            }
+        }
+        return  bitstatus;
+    }
+#endif
+    /* Check the status of the specified SPI flag */
+    if ((SPIx->SPI_M_S_SR & SPI_FLAG) != (uint8_t)RESET)
+    {
+        /* SPI_FLAG is set */
+        bitstatus = SET;
+    }
+
+    /* Return the SPI_FLAG status */
+    return  bitstatus;
+}
+
+/**
+  * \brief  Enable or disable the SPIx GDMA interface.
+  * \param  SPIx: Select the SPI peripheral. \ref SPI_Declaration
+  * \param  SPI_GDMAReq: Specifies the SPI GDMA transfer request to be enabled or disabled.
+  *         This parameter can be one of the following values:
+  *         \arg SPI_GDMAReq_Tx: Tx buffer DMA transfer request.
+  *         \arg SPI_GDMAReq_Rx: Rx buffer DMA transfer request.
+  * \param  NewState: New state of the selected SPI GDMA transfer request.
+  *         This parameter can be: ENABLE or DISABLE.
+  * \return None.
+  */
+void SPI_GDMACmd(SPI_TypeDef *SPIx, SPIGdmaTransferRequests_TypeDef SPI_GDMAReq,
+                 FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_SPI_ALL_PERIPH(SPIx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+    assert_param(IS_SPI_GDMAREQ(SPI_GDMAReq));
+
+    if (NewState != DISABLE)
+    {
+        /* Enable the selected SPI GDMA request */
+        SPIx->SPI_DMACR |= SPI_GDMAReq;
+    }
+    else
+    {
+        /* Disable the selected SPI GDMA request */
+        SPIx->SPI_DMACR &= (uint16_t)~(SPI_GDMAReq);
+    }
+}
+
+/**
+  * \brief  Change SPI speed daynamically.
+  * \param  SPIx: Select the SPI peripheral. \ref SPI_Declaration
+  * \param  precalser: Value of prescaler.
+  * \return None.
+  */
+void SPI_ChangeClock(SPI_TypeDef *SPIx, uint32_t prescaler)
+{
+    /* Disable the selected SPI peripheral */
+    SPI_SPIENR_TypeDef spi_0x08 = {.d32 = SPIx->SPI_SPIENR};
+    spi_0x08.b.spi_en = 0;
+    SPIx->SPI_SPIENR = spi_0x08.d32;
+
+    /* Change SPI speed */
+    SPI_M_BAUDR_TypeDef spi_0x14 = {.d32 = SPIx->SPI_M_BAUDR};
+    spi_0x14.b.sckdv = prescaler & 0xFFFF;
+    SPIx->SPI_M_BAUDR = spi_0x14.d32;
+
+    /* Enable the selected SPI peripheral */
+    spi_0x08.b.spi_en = 1;
+    SPIx->SPI_SPIENR = spi_0x08.d32;
+}
+
+/**
+  * \brief  Set SPI Rx sample delay.
+  * \param  SPIx: Select the SPI peripheral. \ref SPI_Declaration
+  * \param  delay: This parameter can be 0 to 255.
+  * \return None.
+  */
+void SPI_SetRxSampleDly(SPI_TypeDef *SPIx, uint32_t delay)
+{
+    /* Disable the selected SPI peripheral */
+    SPI_SPIENR_TypeDef spi_0x08 = {.d32 = SPIx->SPI_SPIENR};
+    spi_0x08.b.spi_en = 0;
+    SPIx->SPI_SPIENR = spi_0x08.d32;
+
+    /* Set SPI Rx sample delay */
+    SPI_M_RSDR_TypeDef spi_0xf0 = {.d32 = SPIx->SPI_M_RSDR};
+    spi_0xf0.b.rsd = delay & 0xFF;
+    SPIx->SPI_M_RSDR = spi_0xf0.d32;
+
+    /* Enable the selected SPI peripheral */
+    spi_0x08.b.spi_en = 1;
+    SPIx->SPI_SPIENR = spi_0x08.d32;
+}
+
+#if (SPI_SUPPORT_WRAP_MODE == 1)
+
+/**
+  * \brief  Enable or disable the specified SPI wrap mode start transfer.
+  * \param  SPIx: Select the SPI peripheral. \ref SPI_Declaration
+  * \param  NewState: new state of the SPIx peripheral.
+  *         This parameter can be: ENABLE or DISABLE.
+  * \return None
+  */
+void SPI_WrapModeStartTx(SPI_TypeDef *SPIx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_SPI_ALL_PERIPH(SPIx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    SPI_WRAP_CTRL_TypeDef spi_0x200 = {.d32 = SPIx->SPI_WRAP_CTRL};
+    spi_0x200.b.mst_tx_fifo_en = NewState;
+    SPIx->SPI_WRAP_CTRL = spi_0x200.d32;
+}
+
+/**
+  * \brief  Whether inverse CS active polarity.
+  * \param  SPIx: Select the SPI peripheral. \ref SPI_Declaration
+  * \param  NewState: new state of the SPIx peripheral.
+  *         This parameter can be one of the following values:
+  *         \arg  ENABLE: Inverse CS active polarity, which means CS is low active.
+  *         \arg  DISABLE: Not inverse CS active polarity, which means CS is high active.
+  * \return None
+  */
+void SPI_InverseCSActivePolarity(SPI_TypeDef *SPIx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_SPI_ALL_PERIPH(SPIx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    SPI_WRAP_CTRL_TypeDef spi_0x200 = {.d32 = SPIx->SPI_WRAP_CTRL};
+    spi_0x200.b.cs_inv_en = NewState;
+    SPIx->SPI_WRAP_CTRL = spi_0x200.d32;
+}
+
+/**
+  * \brief  Whether drive MOSI low in idle state.
+  * \param  SPIx: Select the SPI peripheral. \ref SPI_Declaration
+  * \param  NewState: new state of the SPIx peripheral.
+  *         This parameter can be one of the following values:
+  *         \arg  ENABLE: Drive MOSI low in idle state.
+  *         \arg  DISABLE: Not drive MOSI low in idle state, which means MOSI is Hi-Z in idle state.
+  * \return None
+  */
+void SPI_DriveMOSILow(SPI_TypeDef *SPIx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_SPI_ALL_PERIPH(SPIx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    SPI_WRAP_CTRL_TypeDef spi_0x200 = {.d32 = SPIx->SPI_WRAP_CTRL};
+    spi_0x200.b.mosi_drv_low_en = NewState;
+    SPIx->SPI_WRAP_CTRL = spi_0x200.d32;
+}
+
+/**
+  * \brief  Whether enable MOSI pull in idle state.
+  * \param  SPIx: Select the SPI peripheral. \ref SPI_Declaration
+  * \param  NewState: new state of the SPIx peripheral.
+  *         This parameter can be one of the following values:
+  *         \arg  ENABLE: MOSI is pull down in idle state.
+  *         \arg  DISABLE: MOSI is pull none in idle state.
+  * \return  None
+  */
+void SPI_PullMOSIEn(SPI_TypeDef *SPIx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_SPI_ALL_PERIPH(SPIx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    SPI_WRAP_CTRL_TypeDef spi_0x200 = {.d32 = SPIx->SPI_WRAP_CTRL};
+    spi_0x200.b.mosi_pull_en = NewState;
+    SPIx->SPI_WRAP_CTRL = spi_0x200.d32;
+}
+
+#endif
+
+#if (SPI_SUPPORT_RAP_FUNCTION == 1)
+void SPI_RAPModeCmd(SPI_TypeDef *SPIx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_SPI_ALL_PERIPH(SPIx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    SPI_WRAP_CTRL_TypeDef spi_0x200 = {.d32 = SPIx->SPI_WRAP_CTRL};
+    spi_0x200.b.rap_ctrl_mode = NewState;
+    SPIx->SPI_WRAP_CTRL = spi_0x200.d32;
+}
+
+void SPI_SetTaskCmdNum(SPI_TypeDef *SPIx, uint8_t num)
+{
+    /* Check the parameters */
+    assert_param(IS_SPI_ALL_PERIPH(SPIx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    SPI_WRAP_TCMD_NUM_TypeDef spi_0x230 = {.d32 = SPIx->SPI_WRAP_TCMD_NUM};
+    spi_0x230.b.task_cmd_num = num;
+    SPIx->SPI_WRAP_TCMD_NUM = spi_0x230.d32;
+}
+
+void SPI_SetTaskWaitNum(SPI_TypeDef *SPIx, uint8_t num)
+{
+    /* Check the parameters */
+    assert_param(IS_SPI_ALL_PERIPH(SPIx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    SPI_WRAP_TWAIT_NUM_TypeDef spi_0x234 = {.d32 = SPIx->SPI_WRAP_TWAIT_NUM};
+    spi_0x234.b.task_wait_num = num;
+    SPIx->SPI_WRAP_TWAIT_NUM = spi_0x234.d32;
+}
+
+void SPI_SetTaskTransferNum(SPI_TypeDef *SPIx, uint8_t num)
+{
+    /* Check the parameters */
+    assert_param(IS_SPI_ALL_PERIPH(SPIx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    SPI_WRAP_TTRAN_NUM_TypeDef spi_0x238 = {.d32 = SPIx->SPI_WRAP_TTRAN_NUM};
+    spi_0x238.b.task_tran_num = num;
+    SPIx->SPI_WRAP_TTRAN_NUM = spi_0x238.d32;
+}
+
+void SPI_TaskTrigger(SPI_TypeDef *SPIx, uint32_t task)
+{
+    /* Check the parameters */
+    assert_param(IS_SPI_ALL_PERIPH(SPIx));
+
+    SPIx->SPI_WRAP_FW_ST |= BIT(task);
+}
+
+bool SPI_TaskEventStsCheck(SPI_TypeDef *SPIx, uint32_t te)
+{
+    /* Check the parameters */
+    assert_param(IS_SPI_ALL_PERIPH(SPIx));
+
+    return SPIx->SPI_WRAP_TASK_STS & BIT(te);
+}
+
+void SPI_TaskEventStsClear(SPI_TypeDef *SPIx, uint32_t te)
+{
+    /* Check the parameters */
+    assert_param(IS_SPI_ALL_PERIPH(SPIx));
+
+    SPIx->SPI_WRAP_TASK_STS |= BIT(te);
+}
+#endif
+
diff --git a/bee/drivers/spi/src/device/rtl87x2g/rtl_spi.h b/bee/drivers/spi/src/device/rtl87x2g/rtl_spi.h
new file mode 100644
index 00000000..4f50e08a
--- /dev/null
+++ b/bee/drivers/spi/src/device/rtl87x2g/rtl_spi.h
@@ -0,0 +1,1149 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *               Define to prevent recursive inclusion
+ *============================================================================*/
+#ifndef RTL_SPI_H
+#define RTL_SPI_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*============================================================================*
+ *                        Header Files
+ *============================================================================*/
+#include "utils/rtl_utils.h"
+#include "rtl_spi_def.h"
+
+/** \defgroup SPI         SPI
+  * \brief
+  * \{
+  */
+/*============================================================================*
+ *                         Constants
+ *============================================================================*/
+/** \defgroup SPI_Exported_Constants SPI Exported Constants
+  * \brief
+  * \{
+  */
+
+/**
+ * \defgroup    SPI_Clock_Speed SPI Clock Speed
+ * \{
+ * \ingroup     SPI_Exported_Constants
+ */
+#define IS_SPI_CLOCK_SPEED(SPEED) (((SPEED) >= 0x01) && \
+                                   ((SPEED) <= 40000000)) //!< SPI clock speed is between 1 and 40000000.
+
+/** End of SPI_Clock_Speed
+  * \}
+  */
+
+/**
+ * \defgroup    SPI_Data_Direction SPI Data Direction
+ * \{
+ * \ingroup     SPI_Exported_Constants
+ */
+typedef enum
+{
+    SPI_Direction_FullDuplex = 0x00, //!< Data can be transmitted and received at the same time.
+    SPI_Direction_TxOnly     = 0x01, //!< Data can only be transmitted at a time.
+    SPI_Direction_RxOnly     = 0x02, //!< Data can only be received at a time.
+    SPI_Direction_EEPROM     = 0x03, //!< Send data first to read target numbers of data.
+} SPIDataDirection_TypeDef;
+
+#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_FullDuplex) || \
+                                     ((MODE) == SPI_Direction_RxOnly) || \
+                                     ((MODE) == SPI_Direction_TxOnly) || \
+                                     ((MODE) == SPI_Direction_EEPROM)) //!< Check if the input parameter is valid.
+
+/** End of SPI_Data_Direction
+  * \}
+  */
+
+/**
+ * \defgroup    SPI_Data_Size SPI Data Size
+ * \{
+ * \ingroup     SPI_Exported_Constants
+ */
+typedef enum
+{
+    SPI_DataSize_4b  = 0x03,     //!< The data frame size is programmed to 4bits.
+    SPI_DataSize_5b  = 0x04,     //!< The data frame size is programmed to 5bits.
+    SPI_DataSize_6b  = 0x05,     //!< The data frame size is programmed to 6bits.
+    SPI_DataSize_7b  = 0x06,     //!< The data frame size is programmed to 7bits.
+    SPI_DataSize_8b  = 0x07,     //!< The data frame size is programmed to 8bits.
+    SPI_DataSize_9b  = 0x08,     //!< The data frame size is programmed to 9bits.
+    SPI_DataSize_10b = 0x09,     //!< The data frame size is programmed to 10bits.
+    SPI_DataSize_11b = 0x0a,     //!< The data frame size is programmed to 11bits.
+    SPI_DataSize_12b = 0x0b,     //!< The data frame size is programmed to 12bits.
+    SPI_DataSize_13b = 0x0c,     //!< The data frame size is programmed to 13bits.
+    SPI_DataSize_14b = 0x0d,     //!< The data frame size is programmed to 14bits.
+    SPI_DataSize_15b = 0x0e,     //!< The data frame size is programmed to 15bits.
+    SPI_DataSize_16b = 0x0f,     //!< The data frame size is programmed to 16bits.
+    SPI_DataSize_17b = 0x10,     //!< The data frame size is programmed to 17bits.
+    SPI_DataSize_18b = 0x11,     //!< The data frame size is programmed to 18bits.
+    SPI_DataSize_19b = 0x12,     //!< The data frame size is programmed to 19bits.
+    SPI_DataSize_20b = 0x13,     //!< The data frame size is programmed to 20bits.
+    SPI_DataSize_21b = 0x14,     //!< The data frame size is programmed to 21bits.
+    SPI_DataSize_22b = 0x15,     //!< The data frame size is programmed to 22bits.
+    SPI_DataSize_23b = 0x16,     //!< The data frame size is programmed to 23bits.
+    SPI_DataSize_24b = 0x17,     //!< The data frame size is programmed to 24bits.
+    SPI_DataSize_25b = 0x18,     //!< The data frame size is programmed to 25bits.
+    SPI_DataSize_26b = 0x19,     //!< The data frame size is programmed to 26bits.
+    SPI_DataSize_27b = 0x1A,     //!< The data frame size is programmed to 27bits.
+    SPI_DataSize_28b = 0x1B,     //!< The data frame size is programmed to 28bits.
+    SPI_DataSize_29b = 0x1C,     //!< The data frame size is programmed to 29bits.
+    SPI_DataSize_30b = 0x1D,     //!< The data frame size is programmed to 30bits.
+    SPI_DataSize_31b = 0x1E,     //!< The data frame size is programmed to 31bits.
+    SPI_DataSize_32b = 0x1F,     //!< The data frame size is programmed to 32bits.
+} SPIDataSize_TypeDef;
+
+#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DataSize_4b)  || \
+                                   ((DATASIZE) == SPI_DataSize_5b)  || \
+                                   ((DATASIZE) == SPI_DataSize_6b)  || \
+                                   ((DATASIZE) == SPI_DataSize_7b)  || \
+                                   ((DATASIZE) == SPI_DataSize_8b)  || \
+                                   ((DATASIZE) == SPI_DataSize_9b)  || \
+                                   ((DATASIZE) == SPI_DataSize_10b) || \
+                                   ((DATASIZE) == SPI_DataSize_11b) || \
+                                   ((DATASIZE) == SPI_DataSize_12b) || \
+                                   ((DATASIZE) == SPI_DataSize_13b) || \
+                                   ((DATASIZE) == SPI_DataSize_14b) || \
+                                   ((DATASIZE) == SPI_DataSize_15b) || \
+                                   ((DATASIZE) == SPI_DataSize_16b) || \
+                                   ((DATASIZE) == SPI_DataSize_17b) || \
+                                   ((DATASIZE) == SPI_DataSize_18b) || \
+                                   ((DATASIZE) == SPI_DataSize_19b) || \
+                                   ((DATASIZE) == SPI_DataSize_20b) || \
+                                   ((DATASIZE) == SPI_DataSize_21b) || \
+                                   ((DATASIZE) == SPI_DataSize_22b) || \
+                                   ((DATASIZE) == SPI_DataSize_23b) || \
+                                   ((DATASIZE) == SPI_DataSize_24b) || \
+                                   ((DATASIZE) == SPI_DataSize_25b) || \
+                                   ((DATASIZE) == SPI_DataSize_26b) || \
+                                   ((DATASIZE) == SPI_DataSize_27b) || \
+                                   ((DATASIZE) == SPI_DataSize_28b) || \
+                                   ((DATASIZE) == SPI_DataSize_29b) || \
+                                   ((DATASIZE) == SPI_DataSize_30b) || \
+                                   ((DATASIZE) == SPI_DataSize_31b) || \
+                                   ((DATASIZE) == SPI_DataSize_32b)) //!< Check if the input parameter is valid.
+
+/** End of SPI_Data_Size
+  * \}
+  */
+
+/**
+ * \defgroup    SPI_Clock_Polarity SPI Clock Polarity
+ * \{
+ * \ingroup     SPI_Exported_Constants
+ */
+typedef enum
+{
+    SPI_CPOL_Low = 0x00,  //!< Inactive state of serial clock is low.
+    SPI_CPOL_High = 0x01, //!< Inactive state of serial clock is high.
+} SPIClockPolarity_TypeDef;
+
+#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \
+                           ((CPOL) == SPI_CPOL_High)) //!< Check if the input parameter is valid.
+
+/** End of SPI_Clock_Polarity
+  * \}
+  */
+
+/**
+ * \defgroup    SPI_Clock_Phase SPI Clock Phase
+ * \{
+ * \ingroup     SPI_Exported_Constants
+ */
+typedef enum
+{
+    SPI_CPHA_1Edge = 0x00, //!< Serial clock toggles in middle of first data bit.
+    SPI_CPHA_2Edge = 0x01, //!< Serial clock toggles at start of first data bit.
+} SPIClockPhase_TypeDef;
+
+#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \
+                           ((CPHA) == SPI_CPHA_2Edge)) //!< Check if the input parameter is valid.
+
+/** End of SPI_Clock_Phase
+  * \}
+  */
+
+/**
+ * \defgroup    SPI_BaudRate_Prescaler_Value SPI BaudRate Prescaler Value
+ * \{
+ * \ingroup     SPI_Exported_Constants
+ */
+
+#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFFF) //!< Check if the input parameter is valid.
+
+/** End of SPI_BaudRate_Prescaler_Value
+  * \}
+  */
+
+/**
+ * \defgroup    SPI_Frame_Format SPI Frame Format
+ * \{
+ * \ingroup     SPI_Exported_Constants
+ */
+typedef enum
+{
+    SPI_Frame_Motorola      = 0x00, //!< Standard SPI frame format.
+    SPI_Frame_TI_SSP        = 0x01, //!< Texas instruments SSP frame format.
+    SPI_Frame_NS_MICROWIRE  = 0x02, //!< National microwire frame format.
+    SPI_Frame_Reserve       = 0x03, //!< Reserved value.
+} SPIFrameFormat_TypeDef;
+
+#define IS_SPI_FRAME_FORMAT(FRAME) (((FRAME) == SPI_Frame_Motorola) || \
+                                    ((FRAME) == SPI_Frame_TI_SSP) || \
+                                    ((FRAME) == SPI_Frame_NS_MICROWIRE) || \
+                                    ((FRAME) == SPI_Frame_Reserve)) //!< Check if the input parameter is valid.
+
+/** End of SPI_Frame_Format
+  * \}
+  */
+
+/**
+ * \defgroup    SPI_GDMA_Transfer_Request SPI GDMA Transfer Request
+ * \{
+ * \ingroup     SPI_Exported_Constants
+ */
+typedef enum
+{
+    SPI_GDMAReq_Rx = 0x01, //!< RX buffer GDMA transfer request.
+    SPI_GDMAReq_Tx = 0x02, //!< TX buffer GDMA transfer request.
+} SPIGdmaTransferRequests_TypeDef;
+
+#define IS_SPI_GDMAREQ(GDMAREQ) (((GDMAREQ)  == SPI_GDMAReq_Rx) || \
+                                 ((GDMAREQ) == SPI_GDMAReq_Tx)) //!< Check if the input parameter is valid.
+
+/** End of SPI_GDMA_Transfer_Request
+  * \}
+  */
+
+/**
+ * \defgroup    SPI_Flags SPI Flags
+ * \{
+ * \ingroup     SPI_Exported_Constants
+ */
+#define SPI_FLAG_BUSY                   BIT0  /**< SPI Busy flag. Set if it is actively transferring data. Reset if it is idle or disabled. */
+#define SPI_FLAG_TFNF                   BIT1  /**< Transmit FIFO not full flag. Set if transmit FIFO is not full. */
+#define SPI_FLAG_TFE                    BIT2  /**< Transmit FIFO empty flag. Set if transmit FIFO is empty. */
+#define SPI_FLAG_RFNE                   BIT3  /**< Receive FIFO not empty flag. Set if receive FIFO is not empty. */
+#define SPI_FLAG_RFF                    BIT4  /**< Receive FIFO full flag. Set if the receive FIFO is completely full. */
+#define SPI_FLAG_TXE                    BIT5  /**< Transmission error flag. Set if the transmit FIFO is empty when a transfer is started in slave mode. */
+#define SPI_FLAG_DCOL                   BIT6  /**< Data collision error flag. Set if it is actively transmitting in master mode when another master selects this device as a slave. */
+#if (SPI_SUPPORT_WRAP_MODE == 1)
+#define SPI_FLAG_WRAP_CS_EN             BIT8
+#define SPI_FLAG_WRAP_TFNF              BIT9
+#define SPI_FLAG_WRAP_TFE               BIT10
+#endif
+
+#if (SPI_SUPPORT_WRAP_MODE == 1)
+#define IS_SPI_GET_FLAG(FLAG)   (((FLAG) == SPI_FLAG_DCOL) || \
+                                 ((FLAG) == SPI_FLAG_TXE) || \
+                                 ((FLAG) == SPI_FLAG_RFF) || \
+                                 ((FLAG) == SPI_FLAG_RFNE) || \
+                                 ((FLAG) == SPI_FLAG_TFE) || \
+                                 ((FLAG) == SPI_FLAG_TFNF) || \
+                                 ((FLAG) == SPI_FLAG_BUSY) || \
+                                 ((FLAG) == SPI_FLAG_WRAP_CS_EN) || \
+                                 ((FLAG) == SPI_FLAG_WRAP_TFNF) || \
+                                 ((FLAG) == SPI_FLAG_WRAP_TFE)) //!< Check if the input parameter is valid.
+#else
+#define IS_SPI_GET_FLAG(FLAG)   (((FLAG) == SPI_FLAG_DCOL) || \
+                                 ((FLAG) == SPI_FLAG_TXE) || \
+                                 ((FLAG) == SPI_FLAG_RFF) || \
+                                 ((FLAG) == SPI_FLAG_RFNE) || \
+                                 ((FLAG) == SPI_FLAG_TFE) || \
+                                 ((FLAG) == SPI_FLAG_TFNF) || \
+                                 ((FLAG) == SPI_FLAG_BUSY)) //!< Check if the input parameter is valid.
+#endif
+
+/** End of SPI_Flags
+  * \}
+  */
+
+/**
+ * \defgroup    SPI_Interrupt SPI Interrupt
+ * \{
+ * \ingroup     SPI_Exported_Constants
+ */
+#define SPI_INT_TXE                    BIT0 //!< Transmit FIFO empty interrupt.
+#define SPI_INT_TXO                    BIT1 //!< Transmit FIFO overflow interrupt.
+#define SPI_INT_RXU                    BIT2 //!< Receive FIFO underflow interrupt.
+#define SPI_INT_RXO                    BIT3 //!< Receive FIFO overflow interrupt.
+#define SPI_INT_RXF                    BIT4 //!< Receive FIFO full interrupt.
+#define SPI_INT_MST                    BIT5 //!< Multi-Master contention interrupt. (master only)
+#define SPI_INT_FAE                    BIT5 //!< The data of slave rx does not match DFS. (slave only)
+#define SPI_INT_TUF                    BIT6 //!< Transmit FIFO underflow interrupt. (slave only)
+#define SPI_INT_RIG                    BIT7 //!< CS rising edge detect interrupt. (slave only)
+#if (SPI_SUPPORT_WRAP_MODE == 1)
+#define SPI_INT_WRAP_TXE               BIT8
+#define SPI_INT_WRAP_TXO               BIT9
+#define SPI_INT_WRAP_TXD               BIT10
+#endif
+
+#if (SPI_SUPPORT_WRAP_MODE == 1)
+#define IS_SPI_CONFIG_IT(IT) (((IT) == SPI_INT_TXE) || \
+                              ((IT) == SPI_INT_TXO) || \
+                              ((IT) == SPI_INT_RXU) || \
+                              ((IT) == SPI_INT_RXO) || \
+                              ((IT) == SPI_INT_RXF) || \
+                              ((IT) == SPI_INT_MST) || \
+                              ((IT) == SPI_INT_FAE) || \
+                              ((IT) == SPI_INT_TUF) || \
+                              ((IT) == SPI_INT_RIG) || \
+                              ((IT) == SPI_INT_WRAP_TXE) || \
+                              ((IT) == SPI_INT_WRAP_TXO) || \
+                              ((IT) == SPI_INT_WRAP_TXD)) //!< Check if the input parameter is valid.
+#else
+#define IS_SPI_CONFIG_IT(IT) (((IT) == SPI_INT_TXE) || \
+                              ((IT) == SPI_INT_TXO) || \
+                              ((IT) == SPI_INT_RXU) || \
+                              ((IT) == SPI_INT_RXO) || \
+                              ((IT) == SPI_INT_RXF) || \
+                              ((IT) == SPI_INT_MST) || \
+                              ((IT) == SPI_INT_FAE) || \
+                              ((IT) == SPI_INT_TUF) || \
+                              ((IT) == SPI_INT_RIG) ) //!< Check if the input parameter is valid.
+#endif
+
+/** End of SPI_Interrupt
+  * \}
+  */
+
+#if (SPI0_SUPPORT_MASTER_SLAVE == 1)
+
+/**
+ * \defgroup    SPI_mode SPI Mode
+ * \{
+ * \ingroup     SPI_Exported_Constants
+ */
+typedef enum
+{
+    SPI_Mode_Master = ((uint16_t)0x0104), //!< SPI device operating mode as master.
+    SPI_Mode_Slave  = ((uint16_t)0x0000)  //!< SPI device operating mode as slave.
+} SPIMode_Typedef;
+
+#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \
+                           ((MODE) == SPI_Mode_Slave)) //!< Check if the input parameter is valid.
+
+/** End of SPI_mode
+  * \}
+  */
+#endif
+
+#if (SPI_SUPPORT_RAP_FUNCTION == 1)
+/**
+ * \defgroup    SPI_TaskEvent SPI Task Event
+ * \{
+ * \ingroup     SPI_Exported_Constants
+ */
+typedef enum
+{
+    SPI_TASK_START  = 0,
+    SPI_EVENT_START = 1,
+    SPI_EVENT_END   = 2,
+} SPITaskEvent_TypeDef;
+
+/** End of SPI_TaskEvent
+  * \}
+  */
+#endif
+
+/** End of SPI_Exported_Constants
+  * \}
+  */
+
+/*============================================================================*
+ *                         Types
+ *============================================================================*/
+/** \defgroup SPI_Exported_Types SPI Exported Types
+  * \brief
+  * \{
+  */
+
+/**
+ * \brief       SPI init structure definition.
+ *
+ * \ingroup     SPI_Exported_Types
+ */
+typedef struct
+{
+    SPIDataDirection_TypeDef
+    SPI_Direction;    /*!< Specify the SPI unidirectional or bidirectional data mode.
+                                                    This parameter can be a value of \ref SPI_Data_Direction. */
+#if (SPI_SUPPORT_WRAP_MODE == 1)
+    uint32_t SPI_TXNDF;                        /*!< Specify the trigger condition in TxOnly or FullDuplex mode.
+                                                    This parameter should be the value of the length of read data,
+                                                    from 1 to 65536. */
+
+    FunctionalState SPI_CSHighActiveEn;        /*!< Specify whether to enable CS high active.
+                                                    This parameter can be a value of ENABLE or DISABLE. */
+
+    FunctionalState
+    SPI_WrapModeEn;            /*!< Specify the TX waper mode (TX NDF) enable. Only SPI1 have txndf mode.
+                                                    ENABLE: Hardware won't automatically pull SPI_CSN high when TX FIFO is empty.
+                                                    DISABLE: SPI_CSN pull high when TX data number = SPI_TXNDF+1. */
+
+    FunctionalState SPI_WrapModeDmaEn;         /*!< Specify the TX waper mode(TX NDF) DMA enable.
+                                                    This parameter can be a value of ENABLE or DISABLE. */
+
+    uint8_t  SPI_TxNdfWaterlevel;              /*!< Specify the TX NDF DMA tx water level max number is 63. */
+#endif
+
+    uint32_t SPI_RXNDF;                        /*!< Specify the trigger condition in RxOnly or EEPROM mode.
+                                                    This parameter should be a value of the length of read data,
+                                                    ranging from 1 to 65536. */
+
+#if (SPI0_SUPPORT_MASTER_SLAVE == 1)
+    SPIMode_Typedef SPI_Mode;                  /*!< Specify the SPI Mode.
+                                                    This parameter can be a value of \ref SPI_mode. */
+#endif
+
+    SPIDataSize_TypeDef SPI_DataSize;          /*!< Specify the SPI data size.
+                                                    This parameter can be a value of \ref SPI_Data_Size. */
+
+    SPIClockPolarity_TypeDef SPI_CPOL;         /*!< Specify the serial clock steady state.
+                                                    This parameter can be a value of \ref SPI_Clock_Polarity. */
+
+    SPIClockPhase_TypeDef SPI_CPHA;            /*!< Specify clock active edge for bit capture.
+                                                    This parameter can be a value of \ref SPI_Clock_Phase. */
+
+    SPIFrameFormat_TypeDef
+    SPI_FrameFormat;                           /*!< Specify which serial protocol transfers the data.
+                                                    This parameter can be a value of \ref SPI_Frame_Format. */
+
+    uint32_t SPI_BaudRatePrescaler;            /*!< Specify the divider of SPI clock. SPI Clock Speed = clk source/SPI_BaudRatePrescaler.
+                                                    This parameter can be any even value between 2 and 65534.
+                                                    This parameter can also refer to the listed values of \ref SPI_BaudRate_Prescaler_Value. */
+
+#if (SPI_SUPPORT_SWAP == 1)
+    FunctionalState SPI_SwapTxBitEn;           /*!< Specify whether to swap SPI Tx data bit.
+                                                    This parameter can be a value of ENABLE or DISABLE. */
+
+    FunctionalState SPI_SwapRxBitEn;           /*!< Specify whether to swap SPI Rx data bit.
+                                                    This parameter can be a value of ENABLE or DISABLE. */
+
+    FunctionalState SPI_SwapTxByteEn;          /*!< Specify whether to swap SPI Tx data byte.
+                                                    This parameter can be a value of ENABLE or DISABLE. */
+
+    FunctionalState SPI_SwapRxByteEn;          /*!< Specify whether to swap SPI Rx data byte.
+                                                    This parameter can be a value of ENABLE or DISABLE. */
+#endif
+
+    FunctionalState SPI_ToggleEn;              /*!< Specify whether to toggle when transfer done.
+                                                    This parameter can be a value of ENABLE or DISABLE. */
+
+    uint32_t SPI_TxThresholdLevel;             /*!< Specify the transmit FIFO Threshold.
+                                                    This parameter can be a value less than 64.*/
+
+    uint32_t SPI_RxThresholdLevel;             /*!< Specify the receive FIFO Threshold.
+                                                    This parameter can be a value less than 64.*/
+
+    FunctionalState SPI_TxDmaEn;               /*!< Specify the Tx dma mode.
+                                                    This parameter can be a value of ENABLE or DISABLE. */
+
+    FunctionalState SPI_RxDmaEn;               /*!< Specify the Rx dma mode.
+                                                    This parameter can be a value of ENABLE or DISABLE. */
+
+    uint8_t SPI_TxWaterlevel;                  /*!< Specify the DMA Tx water level.
+                                                    The best value is SPI fifo depth - Tx GDMA MSize. */
+
+    uint8_t SPI_RxWaterlevel;                  /*!< Specify the DMA Rx water level.
+                                                    The best value is SPI Rx GDMA MSize. */
+} SPI_InitTypeDef;
+
+/** End of SPI_Exported_Types
+  * \}
+  */
+
+/*============================================================================*
+ *                         Functions
+ *============================================================================*/
+/** \defgroup SPI_Exported_Functions SPI Exported Functions
+  * \brief
+  * \{
+  */
+
+/**
+ * \brief   Deinitialize the SPIx peripheral registers to their default reset values.
+ *
+ * \param[in] SPIx  Select the SPI peripheral. Refer to \ref SPI_Declaration.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_spi_init(void)
+ * {
+ *     SPI_DeInit(SPI0);
+ * }
+ * \endcode
+ */
+void SPI_DeInit(SPI_TypeDef *SPIx);
+
+/**
+ * \brief   Initialize the SPIx peripheral according to the specified
+ *          parameters in the SPI_InitStruct.
+ *
+ * \param[in] SPIx            Select the SPI peripheral. Refer to \ref SPI_Declaration.
+ * \param[in] SPI_InitStruct  Pointer to a SPI_InitTypeDef structure which will be initialized.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_spi_init(void)
+ * {
+ *     RCC_PeriphClockCmd(APBPeriph_SPI0, APBPeriph_SPI0_CLOCK, ENABLE);
+
+ *     SPI_InitTypeDef  SPI_InitStruct;
+ *     SPI_StructInit(&SPI_InitStruct);
+ *
+ *     SPI_InitStruct.SPI_Direction   = SPI_Direction_EEPROM;
+ *     SPI_InitStruct.SPI_DataSize    = SPI_DataSize_8b;
+ *     SPI_InitStruct.SPI_CPOL        = SPI_CPOL_High;
+ *     SPI_InitStruct.SPI_CPHA        = SPI_CPHA_2Edge;
+ *     SPI_InitStruct.SPI_BaudRatePrescaler  = 100;
+ *     SPI_InitStruct.SPI_RxThresholdLevel  = 1 - 1;
+ *     SPI_InitStruct.SPI_NDF               = 1 - 1;
+ *     SPI_InitStruct.SPI_FrameFormat = SPI_Frame_Motorola;
+ *
+ *     SPI_Init(SPI0, &SPI_InitStruct);
+ * }
+ * \endcode
+ */
+void SPI_Init(SPI_TypeDef *SPIx, SPI_InitTypeDef *SPI_InitStruct);
+
+/**
+ * \brief  Fill each SPI_InitStruct member with its default value.
+ *
+ * \note   The default settings for the SPI_InitStruct member are shown in the following table:
+ *         | SPI_InitStruct member  | Default value                  |
+ *         |:----------------------:|:------------------------------:|
+ *         | SPI_Direction          | \ref SPI_Direction_FullDuplex  |
+ *         | SPI_RXNDF              | 1                              |
+ *         | SPI_DataSize           | \ref SPI_DataSize_8b           |
+ *         | SPI_CPOL               | \ref SPI_CPOL_High             |
+ *         | SPI_CPHA               | \ref SPI_CPHA_2Edge            |
+ *         | SPI_FrameFormat        | \ref SPI_Frame_Motorola        |
+ *         | SPI_BaudRatePrescaler  | 128                            |
+ *         | SPI_ToggleEn           | DISABLE                        |
+ *         | SPI_TxThresholdLevel   | 1                              |
+ *         | SPI_RxThresholdLevel   | 0                              |
+ *         | SPI_TxDmaEn            | DISABLE                        |
+ *         | SPI_RxDmaEn            | DISABLE                        |
+ *         | SPI_TxWaterlevel       | SPI_TX_FIFO_SIZE - 1           |
+ *         | SPI_RxWaterlevel       | 1                              |
+ *
+ * \param[in] SPI_InitStruct  Pointer to a SPI_InitTypeDef structure which will be initialized.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_spi_init(void)
+ * {
+ *
+ *     RCC_PeriphClockCmd(APBPeriph_SPI0, APBPeriph_SPI0_CLOCK, ENABLE);
+
+ *     SPI_InitTypeDef  SPI_InitStruct;
+ *     SPI_StructInit(&SPI_InitStruct);
+ *
+ *     SPI_InitStruct.SPI_Direction   = SPI_Direction_EEPROM;
+ *     SPI_InitStruct.SPI_DataSize    = SPI_DataSize_8b;
+ *     SPI_InitStruct.SPI_CPOL        = SPI_CPOL_High;
+ *     SPI_InitStruct.SPI_CPHA        = SPI_CPHA_2Edge;
+ *     SPI_InitStruct.SPI_BaudRatePrescaler  = 100;
+ *     SPI_InitStruct.SPI_RxThresholdLevel  = 1 - 1;
+ *     SPI_InitStruct.SPI_NDF               = 1 - 1;
+ *     SPI_InitStruct.SPI_FrameFormat = SPI_Frame_Motorola;
+ *
+ *     SPI_Init(SPI0, &SPI_InitStruct);
+ * }
+ * \endcode
+ */
+void SPI_StructInit(SPI_InitTypeDef *SPI_InitStruct);
+
+/**
+ * \brief  Enable or disable the selected SPI peripheral.
+ *
+ * \param[in] SPIx      Select the SPI peripheral. Refer to \ref SPI_Declaration.
+ * \param[in] NewState  New state of the SPIx peripheral.
+ *                      This parameter can be one of the following values:
+ *                      - ENABLE: Enable the selected SPI peripheral.
+ *                      - DISABLE: Disable the selected SPI peripheral.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_spi_init(void)
+ * {
+ *
+ *     RCC_PeriphClockCmd(APBPeriph_SPI0, APBPeriph_SPI0_CLOCK, ENABLE);
+ *
+ *     SPI_InitTypeDef  SPI_InitStruct;
+ *     SPI_StructInit(&SPI_InitStruct);
+ *
+ *     SPI_InitStruct.SPI_Direction   = SPI_Direction_EEPROM;
+ *     SPI_InitStruct.SPI_DataSize    = SPI_DataSize_8b;
+ *     SPI_InitStruct.SPI_CPOL        = SPI_CPOL_High;
+ *     SPI_InitStruct.SPI_CPHA        = SPI_CPHA_2Edge;
+ *     SPI_InitStruct.SPI_BaudRatePrescaler  = 100;
+ *     SPI_InitStruct.SPI_RxThresholdLevel  = 1 - 1;
+ *     SPI_InitStruct.SPI_NDF               = 1 - 1;
+ *     SPI_InitStruct.SPI_FrameFormat = SPI_Frame_Motorola;
+ *
+ *     SPI_Init(SPI0, &SPI_InitStruct);
+ *     SPI_Cmd(SPI0, ENABLE);
+ * }
+ * \endcode
+ */
+void SPI_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState);
+
+/**
+ * \brief  Transmit a number of bytes through the SPIx peripheral.
+ *
+ * \param[in] SPIx  Select the SPI peripheral. Refer to \ref SPI_Declaration.
+ * \param[in] pBuf  Bytes to be transmitted.
+ * \param[in] len   Byte length to be transmitted.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void spi_demo(void)
+ * {
+ *     uint8_t data_buf[] = {0x01,0x02,0x03};
+ *     SPI_SendBuffer(SPI0, data_buf, sizeof(data_buf));
+ * }
+ * \endcode
+ */
+void SPI_SendBuffer(SPI_TypeDef *SPIx, uint8_t *pBuf, uint16_t len);
+
+/**
+ * \brief  Transmit a number of halfword through the SPIx peripheral.
+ *
+ * \param[in] SPIx  Select the SPI peripheral. Refer to \ref SPI_Declaration.
+ * \param[in] pBuf  Halfwords to be transmitted.
+ * \param[in] len   Halfwords length to be transmitted.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void spi_demo(void)
+ * {
+ *     uint16_t data_buf[] = {0x0102,0x0203,0x0304};
+ *     SPI_SendHalfWord(SPI0, data_buf, sizeof(data_buf)/sizeof(uint16_t));
+ * }
+ * \endcode
+  */
+void SPI_SendHalfWord(SPI_TypeDef *SPIx, uint16_t *pBuf, uint16_t len);
+
+/**
+ * \brief  Transmit a number of words through the SPIx peripheral.
+ *
+ * \param[in] SPIx  Select the SPI peripheral. Refer to \ref SPI_Declaration.
+ * \param[in] pBuf  Words to be transmitted.
+ * \param[in] len   Word length to be transmitted.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void spi_demo(void)
+ * {
+ *     uint32_t data_buf[] = {0x01020304,0x02030405,0x03040506};
+ *     SPI_SendWord(SPI0, data_buf, sizeof(data_buf)/sizeof(uint32_t));
+ * }
+ * \endcode
+ */
+void SPI_SendWord(SPI_TypeDef *SPIx, uint32_t *pBuf, uint16_t len);
+
+/**
+ * \brief  Enable or disable the specified SPI interrupt source.
+ *
+ * \param[in] SPIx      Select the SPI peripheral. Refer to \ref SPI_Declaration.
+ * \param[in] SPI_IT    Specify the SPI interrupt source to be enabled or disabled.
+ *                      This parameter can be one of the following values, refer to \ref SPI_Interrupt.
+ *                      \arg SPI_INT_TXE: Transmit FIFO empty interrupt.
+ *                      \arg SPI_INT_TXO: Transmit FIFO overflow interrupt.
+ *                      \arg SPI_INT_RXU: Receive FIFO underflow interrupt.
+ *                      \arg SPI_INT_RXO: Receive FIFO overflow interrupt.
+ *                      \arg SPI_INT_RXF: Receive FIFO full interrupt.
+ *                      \arg SPI_INT_MST: Multi-Master Contention Interrupt.
+ *                      \arg SPI_INT_FAE: TX Frame Alignment interrupt.
+ *                      \arg SPI_INT_TUF: Transmit FIFO underflow interrupt.
+ *                      \arg SPI_INT_RIG: Rising edge detect interrupt.
+ * \param[in] NewState  New state of the specified SPI interrupt source.
+ *                      This parameter can be one of the following values:
+ *                      - ENABLE: Enable the specified SPI interrupt source.
+ *                      - DISABLE: Disable the specified SPI interrupt source.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void spi_demo(void)
+ * {
+ *     SPI_INTConfig(SPI0, SPI_INT_RXF, ENABLE);
+ * }
+ * \endcode
+ */
+void SPI_INTConfig(SPI_TypeDef *SPIx, uint16_t SPI_IT, FunctionalState NewState);
+
+/**
+ * \brief  Clear the specified SPI interrupt pending bit.
+ *
+ * \param[in] SPIx    Select the SPI peripheral. Refer to \ref SPI_Declaration.
+ * \param[in] SPI_IT  Specify the SPI interrupt to clear.
+ *                    This parameter can be one of the following values, refer to \ref SPI_Interrupt.
+ *                    - SPI_INT_TXO: Transmit FIFO Overflow Interrupt.
+ *                    - SPI_INT_RXO: Receive FIFO Overflow Interrupt.
+ *                    - SPI_INT_RXU: Receive FIFO Underflow Interrupt.
+ *                    - SPI_INT_MST: Multi-Master Contention Interrupt.
+ *                    - SPI_INT_FAE: TX Frame Alignment Interrupt.
+ *                    - SPI_INT_TUF: Transmit FIFO Underflow Interrupt.
+ *                    - SPI_INT_RIG: Rising edge detect Interrupt.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void spi_demo(void)
+ * {
+ *     SPI_ClearINTPendingBit(SPI0, SPI_INT_RXF);
+ * }
+ * \endcode
+ */
+void SPI_ClearINTPendingBit(SPI_TypeDef *SPIx, uint16_t SPI_IT);
+
+/**
+ * \brief  Transmit a data through the SPIx peripheral.
+ *
+ * \param[in] SPIx  Select the SPI peripheral. Refer to \ref SPI_Declaration.
+ * \param[in] Data  Data to be transmitted.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void spi_demo(void)
+ * {
+ *     uint32_t data = 0x01020304;
+ *     SPI_SendData(SPI0, data);
+ * }
+ * \endcode
+ */
+void SPI_SendData(SPI_TypeDef *SPIx, uint32_t Data);
+
+/**
+ * \brief   Receive data by the SPI peripheral.
+ *
+ * \param[in] SPIx  Select the SPI peripheral. Refer to \ref SPI_Declaration.
+ *
+ * \return  The most recent received data.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void spi_demo(void)
+ * {
+ *     uint32_t data = SPI_ReceiveData(SPI0);
+ * }
+ * \endcode
+ */
+uint32_t SPI_ReceiveData(SPI_TypeDef *SPIx);
+
+/**
+ * \brief   Get data length in Tx FIFO through the SPIx peripheral.
+ *
+ * \param[in] SPIx  Select the SPI peripheral. Refer to \ref SPI_Declaration.
+ *
+ * \return  Data length in Tx FIFO.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void spi_demo(void)
+ * {
+ *     uint8_t data_len = SPI_GetTxFIFOLen(SPI0);
+ * }
+ * \endcode
+ */
+uint8_t SPI_GetTxFIFOLen(SPI_TypeDef *SPIx);
+
+/**
+ * \brief   Get data length in Rx FIFO through the SPIx peripheral.
+ *
+ * \param[in] SPIx  Select the SPI peripheral. Refer to \ref SPI_Declaration.
+ *
+ * \return  Data length in Rx FIFO.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void spi_demo(void)
+ * {
+ *     uint8_t data_len = SPI_GetRxFIFOLen(SPI0);
+ * }
+ * \endcode
+ */
+uint8_t SPI_GetRxFIFOLen(SPI_TypeDef *SPIx);
+
+/**
+ * \brief   Change SPI direction mode.
+ *
+ * \param[in] SPIx  Select the SPI peripheral. Refer to \ref SPI_Declaration.
+ * \param[in] dir   Value of direction mode.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void spi_demo(void)
+ * {
+ *     SPI_ChangeDirection(SPI0, SPI_Direction_EEPROM);
+ * }
+ * \endcode
+ */
+void SPI_ChangeDirection(SPI_TypeDef *SPIx, uint16_t dir);
+
+/**
+ * \brief   Set read Data length only in EEPROM mode through the SPIx peripheral,which
+            enables you to receive up to 64 KB of data in a continuous transfer.
+ *
+ * \param[in] SPIx  Select the SPI peripheral. Refer to \ref SPI_Declaration.
+ * \param[in] len   Length of read data which can be 1 to 65536.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void spi_demo(void)
+ * {
+ *     SPI_SetReadLen(SPI0, 100);
+ * }
+ * \endcode
+ */
+void SPI_SetReadLen(SPI_TypeDef *SPIx, uint16_t len);
+
+/**
+ * \brief   Set cs number through the SPIx peripheral.
+ *
+ * \param[in] SPIx    Select the SPI peripheral. Refer to \ref SPI_Declaration.
+ * \param[in] number  Number can be 0 to 2.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void spi_demo(void)
+ * {
+ *     SPI_SetCSNumber(SPI1, 1);
+ * }
+ * \endcode
+ */
+void SPI_SetCSNumber(SPI_TypeDef *SPIx, uint8_t number);
+
+/**
+ * \brief  Get the specified SPI interrupt status.
+ *
+ * \param[in] SPIx    Select the SPI peripheral. Refer to \ref SPI_Declaration.
+ * \param[in] SPI_IT  Specify the SPI interrupt to check.
+ *                    This parameter can be one of the following values, refer to \ref SPI_Interrupt.
+ *                    \arg SPI_INT_MST: Multi-Master Contention Interrupt.
+ *                    \arg SPI_INT_FAE: TX Frame Alignment Interrupt.
+ *                    \arg SPI_INT_RXF: Receive FIFO Full Interrupt.
+ *                    \arg SPI_INT_RXO: Receive FIFO Overflow Interrupt.
+ *                    \arg SPI_INT_RXU: Receive FIFO Underflow Interrupt.
+ *                    \arg SPI_INT_TXO: Transmit FIFO Overflow Interrupt .
+ *                    \arg SPI_INT_TXE: Transmit FIFO Empty Interrupt.
+ *                    \arg SPI_INT_WRAP_TXE: TX NDF mode FIFO Transmit FIFO Empty Interrupt.
+ *                    \arg SPI_INT_WRAP_TXO: TX NDF mode FIFO Overflow Interrupt.
+ *                    \arg SPI_INT_WRAP_TXD: TX NDF mode transmit done Interrupt.
+ *
+ * \return  The status of the SPI interrupt.
+ *          - SET: The SPI interrupt status has been set.
+ *          - RESET: The SPI interrupt status has been reset.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void spi_demo(void)
+ * {
+ *     ITStatus int_status = SPI_GetINTStatus(SPI0, SPI_INT_RXF);
+ * }
+ * \endcode
+ */
+ITStatus SPI_GetINTStatus(SPI_TypeDef *SPIx, uint32_t SPI_IT);
+
+/**
+ * \brief  Get the specified SPI flag status.
+ *
+ * \param[in] SPIx      Select the SPI peripheral. Refer to \ref SPI_Declaration.
+ * \param[in] SPI_FLAG  Specify the SPI flag to check.
+ *                      This parameter can be one of the following values, refer to \ref SPI_Flags.
+ *                      \arg SPI_FLAG_DCOL: Data Collision Error flag.Set if it is actively transmitting in master mode when another master selects this device as a slave.
+ *                      \arg SPI_FLAG_TXE: Transmission error flag.Set if the transmit FIFO is empty when a transfer is started in slave mode.
+ *                      \arg SPI_FLAG_RFF: Receive FIFO full flag. Set if the receive FIFO is completely full.
+ *                      \arg SPI_FLAG_RFNE: Receive FIFO Not Empty flag.Set if receive FIFO is not empty.
+ *                      \arg SPI_FLAG_TFE: Transmit FIFO Empty flag.Set if transmit FIFO is empty.
+ *                      \arg SPI_FLAG_TFNF: Transmit FIFO Not Full flag.Set if transmit FIFO is not full.
+ *                      \arg SPI_FLAG_BUSY: SPI Busy flag.Set if it is actively transferring data.reset if it is idle or disabled.
+ *                      \arg SPI_FLAG_TXNDF_BUSY: TX NDF mode Busy flag.
+ *                      \arg SPI_FLAG_TXNDF_TFNF: TX NDF mode FIFO Not Full flag.
+ *                      \arg SPI_FLAG_TXNDF_TFE: TX NDF mode FIFO Empty flag.
+ *
+ * \return  The status of SPI flag.
+ *          - SET: The SPI flag has been set.
+ *          - RESET: The SPI flag has been reset.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void spi_demo(void)
+ * {
+ *     FlagStatus flag_status = SPI_GetFlagState(SPI0, SPI_FLAG_TXE);
+ *
+ * }
+ * \endcode
+ */
+FlagStatus SPI_GetFlagState(SPI_TypeDef *SPIx, uint16_t SPI_FLAG);
+
+/**
+ * \brief   Enable or disable the SPIx GDMA interface.
+ *
+ * \param[in] SPIx         Select the SPI peripheral. Refer to \ref SPI_Declaration.
+ * \param[in] SPI_GDMAReq  Specify the SPI GDMA transfer request to be enabled or disabled.
+ *                         This parameter can be one of the following values:
+ *                         \arg SPI_GDMAReq_Tx: Tx buffer DMA transfer request.
+ *                         \arg SPI_GDMAReq_Rx: Rx buffer DMA transfer request.
+ * \param[in] NewState     New state of the selected SPI GDMA transfer request.
+ *                         This parameter can be one of the following values:
+ *                         - ENABLE: Enable the SPIx GDMA interface.
+ *                         - DISABLE: Disable the SPIx GDMA interface.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void spi_demo(void)
+ * {
+ *     SPI_GDMACmd(SPI0, SPI_GDMAReq_Tx, ENABLE);
+ * }
+ * \endcode
+ */
+void SPI_GDMACmd(SPI_TypeDef *SPIx, SPIGdmaTransferRequests_TypeDef SPI_GDMAReq,
+                 FunctionalState NewState);
+
+/**
+ * \brief  Change SPI speed daynamically.
+ *
+ * \param[in] SPIx       Select the SPI peripheral. Refer to \ref SPI_Declaration.
+ * \param[in] precalser  Value of prescaler.
+ *                       This parameter can be any even value between 2 and 65534.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void spi_demo(void)
+ * {
+ *     SPI_ChangeClock(SPI0, 2);
+ * }
+ * \endcode
+ */
+void SPI_ChangeClock(SPI_TypeDef *SPIx, uint32_t prescaler);
+
+/**
+ * \brief   Set SPI Rx sample delay.
+ *
+ * \param[in] SPIx   Select the SPI peripheral. Refer to \ref SPI_Declaration.
+ * \param[in] delay  This parameter can be 0 to 255.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void spi_demo(void)
+ * {
+ *     SPI_SetRxSampleDly(SPI0, 1);
+ * }
+ * \endcode
+ */
+void SPI_SetRxSampleDly(SPI_TypeDef *SPIx, uint32_t delay);
+
+#if (SPI_SUPPORT_WRAP_MODE == 1)
+
+/**
+ * \brief   Enable or disable the specified SPI wrap mode start transfer.
+ *
+ * \param[in] SPIx      Select the SPI peripheral. Refer to \ref SPI_Declaration.
+ * \param[in] NewState  New state of the SPIx peripheral.
+ *                      This parameter can be one of the following values:
+ *                      - ENABLE: Enable the specified SPI wrap mode start transfer.
+ *                      - DISABLE: Disable the specified SPI wrap mode start transfer.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void spi_demo(void)
+ * {
+ *     SPI_WrapModeStartTx(SPI0, ENABLE);
+ * }
+ * \endcode
+ */
+void SPI_WrapModeStartTx(SPI_TypeDef *SPIx, FunctionalState NewState);
+
+/**
+ * \brief   Enable or disable inverse CS active polarity.
+ *
+ * \param[in] SPIx      Select the SPI peripheral. Refer to \ref SPI_Declaration.
+ * \param[in] NewState  New state of the SPIx peripheral.
+ *                      This parameter can be one of the following values:
+ *                      - ENABLE: Inverse CS active polarity, which means CS is low active.
+ *                      - DISABLE: Not inverse CS active polarity, which means CS is high active.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void spi_demo(void)
+ * {
+ *     SPI_InverseCSActivePolarity(SPI0, ENABLE);
+ * }
+ * \endcode
+ */
+void SPI_InverseCSActivePolarity(SPI_TypeDef *SPIx, FunctionalState NewState);
+
+/**
+ * \brief   Enable or disable driving MOSI low during the idle state.
+ *
+ * \param[in] SPIx      Select the SPI peripheral. Refer to \ref SPI_Declaration.
+ * \param[in] NewState  New state of the SPIx peripheral.
+ *                      This parameter can be one of the following values:
+ *                      - ENABLE: Drive MOSI low in idle state.
+ *                      - DISABLE: Set MOSI to high-impedance (Hi-Z) in idle state.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void spi_demo(void)
+ * {
+ *     SPI_DriveMOSILow(SPI0, ENABLE);
+ * }
+ * \endcode
+ */
+void SPI_DriveMOSILow(SPI_TypeDef *SPIx, FunctionalState NewState);
+
+/**
+ * \brief   Enable or disable the MOSI pull function in the idle state.
+ *
+ * \param[in] SPIx      Select the SPI peripheral. Refer to \ref SPI_Declaration.
+ * \param[in] NewState  New state of the SPIx peripheral.
+ *                      This parameter can be one of the following values:
+ *                      - ENABLE: MOSI is pull down in idle state.
+ *                      - DISABLE: MOSI is pull none in idle state.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void spi_demo(void)
+ * {
+ *     SPI_PullMOSIEn(SPI0, ENABLE);
+ * }
+ * \endcode
+ */
+void SPI_PullMOSIEn(SPI_TypeDef *SPIx, FunctionalState NewState);
+
+#endif
+
+/**
+ * \brief     Configure the SPI clock divider.
+ *
+ * \param[in] SPIx      Select the SPI peripheral. Refer to \ref SPI_Declaration.
+ * \param[in] ClockDiv  Specify the SPI clock divider.
+ *                      This parameter can refer to \ref SPI_Clock_Divider.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_spi_init(void)
+ * {
+ *     RCC_SPIClkDivConfig(SPI0, CLOCK_DIV_1);
+ * }
+ * \endcode
+ */
+void SPI_ClkDivConfig(SPI_TypeDef *SPIx, SPIClockDiv_TypeDef ClockDiv);
+
+#if SPI_SUPPORT_CLOCK_SOURCE_CONFIG
+/**
+ * \brief  Configure the SPI clock.
+ *
+ * \param[in]  SPIx      Select the SPI peripheral. Refer to \ref SPI_Declaration.
+ * \param[in]  ClockSrc  Specify the clock source to gates its clock.
+ * \param[in]  ClockDiv  Specify the clock divider to gates its clock.
+ */
+void SPI_ClkConfig(SPI_TypeDef *SPIx, SPIClockSrc_TypeDef ClockSrc,
+                   SPIClockDiv_TypeDef ClockDiv);
+
+/**
+ * \brief  Get the SPI clock configuration.
+ *
+ * \param[in] SPIx      Select the SPI peripheral. Refer to \ref SPI_Declaration.
+ * \param[in] ClockSrc  Specify the clock source to gates its clock.
+ * \param[in] ClockDiv  Specify the clock divide to gates its clock.
+ *
+ * \return The status of get clock.
+ */
+bool SPI_ClkGet(SPI_TypeDef *SPIx, SPIClockSrc_TypeDef *ClockSrc, SPIClockDiv_TypeDef *ClockDiv);
+#endif
+
+#if SPI_SUPPORT_CLOCK_SOURCE_SWTICH
+/**
+ * \brief  SPI clock source switch.
+ *
+ * \param[in] SPIx         Select the SPI peripheral. Refer to \ref SPI_Declaration.
+ * \param[in] ClockSource  SPI clock source to switch.
+ *                         This parameter can be one of the following values:
+ *                         - SPI_CLOCK_SOURCE_40M: Select SPI clock source of 40MHz.
+ *                         - SPI_CLOCK_SOURCE_PLL: Select SPI clock source of PLL.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_spi_init(void)
+ * {
+ *     SPI_ClkSourceSwitch(SPI0, SPI_CLOCK_SOURCE_40M);
+ * }
+ * \endcode
+ */
+extern void SPI_ClkSourceSwitch(SPI_TypeDef *SPIx, uint16_t ClockSource);
+#endif
+
+
+#if (SPI_SUPPORT_RAP_FUNCTION == 1)
+
+void SPI_RAPModeCmd(SPI_TypeDef *SPIx, FunctionalState NewState);
+
+void SPI_SetTaskCmdNum(SPI_TypeDef *SPIx, uint8_t num);
+
+void SPI_SetTaskWaitNum(SPI_TypeDef *SPIx, uint8_t num);
+
+void SPI_SetTaskTransferNum(SPI_TypeDef *SPIx, uint8_t num);
+
+void SPI_TaskTrigger(SPI_TypeDef *SPIx, uint32_t task);
+
+bool SPI_TaskEventStsCheck(SPI_TypeDef *SPIx, uint32_t te);
+
+void SPI_TaskEventStsClear(SPI_TypeDef *SPIx, uint32_t te);
+
+#endif
+/** End of SPI_Exported_Functions
+  * \}
+  */
+
+/** End of SPI
+  * \}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RTL_SPI_H */
+
+
diff --git a/bee/drivers/spi/src/device/rtl87x2g/rtl_spi_def.h b/bee/drivers/spi/src/device/rtl87x2g/rtl_spi_def.h
new file mode 100644
index 00000000..22fa9257
--- /dev/null
+++ b/bee/drivers/spi/src/device/rtl87x2g/rtl_spi_def.h
@@ -0,0 +1,935 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef RTL_SPI_DEF_H
+#define RTL_SPI_DEF_H
+
+#include "utils/rtl_utils.h"
+#include "address_map.h"
+
+#ifdef  __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+
+/*============================================================================*
+ *                          SPI Defines
+ *============================================================================*/
+/** \defgroup SPI         SPI
+  * \brief
+  * \{
+  */
+
+/** \defgroup SPI_Exported_Constants SPI Exported Constants
+  * \brief
+  * \{
+  */
+
+/**
+ * \defgroup SPI_Defines SPI Defines
+ * \{
+ * \ingroup  SPI_Exported_Constants
+ */
+#define SPI_TX_FIFO_SIZE                               (32)     //!< The chip supports 32 TX FIFO SIZE.
+#define SPI_RX_FIFO_SIZE                               (32)     //!< The chip supports 32 RX FIFO SIZE.
+#define SPI0_SLAVE_TX_FIFO_SIZE                        (64)     //!< The chip supports 64 TX FIFO SIZE.
+#define SPI0_SLAVE_RX_FIFO_SIZE                        (64)     //!< The chip supports 64 RX FIFO SIZE.
+#define SPI_SUPPORT_WRAP_MODE                          (0)      //!< The function is not supported.
+#define SPI0_SUPPORT_MASTER_SLAVE                      (0)      //!< The function is not supported.
+#define SPI0_SUPPORT_HS                                (1)      //!< The chip supports HS function.
+#define SPI_SUPPORT_APH_BRIDGE_FOR_HIGH_SPEED          (1)      //!< The chip supports APH bridge for high speed.
+#define SPI_SUPPORT_CLOCK_SOURCE_SWITCH                (0)      //!< The function is not supported.
+#define SPI_SUPPORT_CLOCK_SOURCE_CONFIG                (1)      //!< The chip supports clock source configuration.
+#define SPI_DFS_BIT_FIELD                              dfs_32   //!< The SPI DFS bit field is dfs_32.
+/** End of SPI_Defines
+  * \}
+  */
+
+/** End of SPI_Exported_Constants
+  * \}
+  */
+
+/** End of SPI
+  * \}
+  */
+
+/*============================================================================*
+ *                         SPI Registers Memory Map
+ *============================================================================*/
+typedef struct
+{
+    __IO  uint32_t SPI_M_S_CTRL0;               /*!< 0x00 */
+    __IO  uint32_t SPI_M_CTRL1;                 /*!< 0x04 */
+    __IO  uint32_t SPI_SPIENR;                  /*!< 0x08 */
+    __IO  uint32_t RSVD_0C;                     /*!< 0x0C */
+    __IO  uint32_t SPI_M_SER;                   /*!< 0x10 */
+    __IO  uint32_t SPI_M_BAUDR;                 /*!< 0x14 */
+    __IO  uint32_t SPI_TXFTLR;                  /*!< 0x18 */
+    __IO  uint32_t SPI_RXFTLR;                  /*!< 0x1C */
+    __I   uint32_t SPI_TXFLR;                   /*!< 0x20 */
+    __I   uint32_t SPI_RXFLR;                   /*!< 0x24 */
+    __I   uint32_t SPI_M_S_SR;                  /*!< 0x28 */
+    __IO  uint32_t SPI_M_S_IMR;                 /*!< 0x2C */
+    __I   uint32_t SPI_M_S_ISR;                 /*!< 0x30 */
+    __I   uint32_t SPI_M_S_RISR;                /*!< 0x34 */
+    __I   uint32_t SPI_TXOICR;                  /*!< 0x38 */
+    __I   uint32_t SPI_RXOICR;                  /*!< 0x3C */
+    __I   uint32_t SPI_RXUICR;                  /*!< 0x40 */
+    __I   uint32_t SPI_M_S_MSTICR_FAEICR;       /*!< 0x44 */
+    __I   uint32_t SPI_ICR;                     /*!< 0x48 */
+    __IO  uint32_t SPI_DMACR;                   /*!< 0x4C */
+    __IO  uint32_t SPI_DMATDLR;                 /*!< 0x50 */
+    __IO  uint32_t SPI_DMARDLR;                 /*!< 0x54 */
+    __I   uint32_t SPI_M_S_IDR_TXUICR;          /*!< 0x58 */
+    __I   uint32_t SPI_M_S_VERSION_ID_SSRICR;   /*!< 0x5C */
+    __IO  uint32_t SPI_DR[36];                  /*!< 0x60 - 0xEC */
+    __IO  uint32_t SPI_M_RSDR;                  /*!< 0xF0 */
+} SPI_TypeDef;
+
+/*============================================================================*
+ *                         SPI Declaration
+ *============================================================================*/
+/** \defgroup SPI         SPI
+  * \brief
+  * \{
+  */
+
+/** \defgroup SPI_Exported_Constants SPI Exported Constants
+  * \brief
+  * \{
+  */
+
+/** \defgroup SPI_Declaration SPI Declaration
+  * \brief
+  * \{
+  */
+
+#define SPI0                      ((SPI_TypeDef *) SPI0_REG_BASE)      //!< SPI0 base address.
+#define SPI1                      ((SPI_TypeDef *) SPI1_REG_BASE)      //!< SPI1 base address.
+#define SPI0_SLAVE                ((SPI_TypeDef *) SPI_SLAVE_REG_BASE) //!< SPI0_SLAVE base address.
+#define SPI0_HS                   ((SPI_TypeDef *) SPI0_HS_REG_BASE)   //!< SPI0_HS base address.
+
+#define IS_SPIM_PERIPH(PERIPH)    (((PERIPH) == SPI0) || \
+                                   ((PERIPH) == SPI1) || \
+                                   ((PERIPH) == SPI0_HS))       //!< Check if the input parameter is valid.
+#define IS_SPIS_PERIPH(PERIPH)    (((PERIPH) == SPI0_SLAVE))    //!< Check if the input parameter is valid.
+#define IS_SPI_ALL_PERIPH(PERIPH) (IS_SPIM_PERIPH(PERIPH) || \
+                                   IS_SPIS_PERIPH(PERIPH))      //!< Check if the input parameter is valid.
+
+#define SPI_TX_FIFO_ADDR(SPIx)    (uint32_t)(&(((SPI_TypeDef *)(SPIx))->SPI_DR[0]))
+#define SPI_RX_FIFO_ADDR(SPIx)    (uint32_t)(&(((SPI_TypeDef *)(SPIx))->SPI_DR[0]))
+
+/** End of SPI_Declaration
+  * \}
+  */
+
+/** End of SPI_Exported_Constants
+  * \}
+  */
+
+/** End of SPI
+  * \}
+  */
+
+/*============================================================================*
+ *                         SPI Private Types
+ *============================================================================*/
+typedef struct
+{
+    uint32_t spi_reg[12];
+} SPIStoreReg_Typedef;
+
+/*============================================================================*
+ *                         SPI Registers and Field Descriptions
+ *============================================================================*/
+/* 0x00
+    3:0     R      dfs             4'h0
+    5:4     R/W    frf             2'b0
+    6       R/W    scph            1'b0
+    7       R/W    scpol           1'b0
+    9:8     R/W    tmod            2'b0
+    10      R/W    slv_oe          1'b0
+    11      R/W    srl             1'b0
+    15:12   R/W    cfs             4'b0
+    20:16   R/W    dfs_32          5'h7
+    22:21   R      spi_frf         2'b0
+    23      R      reserved23      1'b0
+    24      R/W    sste            1'b1
+    31:25   R      reserved31_25   7'b0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        const uint32_t dfs: 4;
+        uint32_t frf: 2;
+        uint32_t scph: 1;
+        uint32_t scpol: 1;
+        uint32_t tmod: 2;
+        uint32_t slv_oe: 1;
+        uint32_t srl: 1;
+        uint32_t cfs: 4;
+        uint32_t dfs_32: 5;
+        const uint32_t spi_frf: 2;
+        const uint32_t reserved_1: 1;
+        uint32_t sste: 1;
+        const uint32_t reserved_0: 7;
+    } b;
+} SPI_M_CTRL0_TypeDef;
+
+
+
+/* 0x00
+    3:0     R/W    dfs             4'h7
+    5:4     R      reserved5_4     2'b0
+    6       R/W    scph            1'b0
+    7       R/W    scpol           1'b0
+    9:8     R      reserved9_8     2'b0
+    10      R/W    slv_oe          1'b0
+    20:11   R      reserved20_11   10'b0
+    21      R/W    tx_byte_swap    1'b0
+    22      R/W    tx_bit_swap     1'b0
+    23      R/W    rx_byte_swap    1'b0
+    24      R/W    rx_bit_swap     1'b0
+    31:25   R      reserved31_25   7'b0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t dfs: 4;
+        const uint32_t reserved_3: 2;
+        uint32_t scph: 1;
+        uint32_t scpol: 1;
+        const uint32_t reserved_2: 2;
+        uint32_t slv_oe: 1;
+        const uint32_t reserved_1: 10;
+        uint32_t tx_byte_swap: 1;
+        uint32_t tx_bit_swap: 1;
+        uint32_t rx_byte_swap: 1;
+        uint32_t rx_bit_swap: 1;
+        const uint32_t reserved_0: 7;
+    } b;
+} SPI_S_CTRL0_TypeDef;
+
+
+
+/* 0x04
+    15:0    R/W    ndf             16'h0
+    31:16   R      reserved0       16'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t ndf: 16;
+        const uint32_t reserved_0: 16;
+    } b;
+} SPI_M_CTRL1_TypeDef;
+
+
+
+/* 0x08
+    0       R/W    spi_en          1'b0
+    31:1    R      reserved0       31'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t spi_en: 1;
+        const uint32_t reserved_0: 31;
+    } b;
+} SPI_SPIENR_TypeDef;
+
+
+
+/* 0x10
+    0       R/W    ser             1'b0
+    31:1    R      reserved0       31'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t ser: 1;
+        const uint32_t reserved_0: 31;
+    } b;
+} SPI_M_SER_TypeDef;
+
+
+
+/* 0x14
+    15:0    R/W    sckdv           16'b0
+    31:16   R      reserved0       16'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t sckdv: 16;
+        const uint32_t reserved_0: 16;
+    } b;
+} SPI_M_BAUDR_TypeDef;
+
+
+
+/* 0x18
+    5:0     R/W    tft             6'b0
+    31:6    R      reserved0       26'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t tft: 6;
+        const uint32_t reserved_0: 26;
+    } b;
+} SPI_TXFTLR_TypeDef;
+
+
+
+/* 0x1C
+    5:0     R/W    rft             6'b0
+    31:6    R      reserved0       26'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t rft: 6;
+        const uint32_t reserved_0: 26;
+    } b;
+} SPI_RXFTLR_TypeDef;
+
+
+
+/* 0x20
+    6:0     R      txtfl           7'b0
+    31:7    R      reserved0       25'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        const uint32_t txtfl: 7;
+        const uint32_t reserved_0: 25;
+    } b;
+} SPI_TXFLR_TypeDef;
+
+
+
+/* 0x24
+    6:0     R      rxtfl           7'b0
+    31:7    R      reserved0       25'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        const uint32_t rxtfl: 7;
+        const uint32_t reserved_0: 25;
+    } b;
+} SPI_RXFLR_TypeDef;
+
+
+
+/* 0x28
+    0       R      busy            1'b0
+    1       R      tfnf            1'b1
+    2       R      tfe             1'b1
+    3       R      rfne            1'b0
+    4       R      rff             1'b0
+    5       R      txe             1'b0
+    6       R      dcol            1'b0
+    31:7    R      reserved31_7    25'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        const uint32_t busy: 1;
+        const uint32_t tfnf: 1;
+        const uint32_t tfe: 1;
+        const uint32_t rfne: 1;
+        const uint32_t rff: 1;
+        const uint32_t txe: 1;
+        const uint32_t dcol: 1;
+        const uint32_t reserved_0: 25;
+    } b;
+} SPI_M_SR_TypeDef;
+
+
+
+/* 0x28
+    0       R      busy            1'b0
+    1       R      tfnf            1'b1
+    2       R      tfe             1'b1
+    3       R      rfne            1'b0
+    4       R      rff             1'b0
+    5       R      txe             1'b0
+    6       R      reserved6       1'b0
+    31:7    R      reserved31_7    25'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        const uint32_t busy: 1;
+        const uint32_t tfnf: 1;
+        const uint32_t tfe: 1;
+        const uint32_t rfne: 1;
+        const uint32_t rff: 1;
+        const uint32_t txe: 1;
+        const uint32_t reserved_1: 1;
+        const uint32_t reserved_0: 25;
+    } b;
+} SPI_S_SR_TypeDef;
+
+
+
+/* 0x2C
+    0       R/W    txeim           1'b1
+    1       R/W    txoim           1'b1
+    2       R/W    rxuim           1'b1
+    3       R/W    rxoim           1'b1
+    4       R/W    rxfim           1'b1
+    5       R/W    mstim           1'b1
+    31:6    R      reserved31_6    26'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t txeim: 1;
+        uint32_t txoim: 1;
+        uint32_t rxuim: 1;
+        uint32_t rxoim: 1;
+        uint32_t rxfim: 1;
+        uint32_t mstim: 1;
+        const uint32_t reserved_0: 26;
+    } b;
+} SPI_M_IMR_TypeDef;
+
+
+
+/* 0x2C
+    0       R/W    txeim           1'b1
+    1       R/W    txoim           1'b1
+    2       R/W    rxuim           1'b1
+    3       R/W    rxoim           1'b1
+    4       R/W    rxfim           1'b1
+    5       R/W    faeim           1'b1
+    6       R/W    txuim           1'b1
+    7       R/W    ssrim           1'b1
+    31:8    R      reserved0       24'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t txeim: 1;
+        uint32_t txoim: 1;
+        uint32_t rxuim: 1;
+        uint32_t rxoim: 1;
+        uint32_t rxfim: 1;
+        uint32_t faeim: 1;
+        uint32_t txuim: 1;
+        uint32_t ssrim: 1;
+        const uint32_t reserved_0: 24;
+    } b;
+} SPI_S_IMR_TypeDef;
+
+
+
+/* 0x30
+    0       R      txeis           1'b0
+    1       R      txois           1'b0
+    2       R      rxuis           1'b0
+    3       R      rxois           1'b0
+    4       R      rxfis           1'b0
+    5       R      mstis           1'b0
+    31:6    R      reserved31_6    26'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        const uint32_t txeis: 1;
+        const uint32_t txois: 1;
+        const uint32_t rxuis: 1;
+        const uint32_t rxois: 1;
+        const uint32_t rxfis: 1;
+        const uint32_t mstis: 1;
+        const uint32_t reserved_0: 26;
+    } b;
+} SPI_M_ISR_TypeDef;
+
+
+
+/* 0x30
+    0       R      txeis           1'b0
+    1       R      txois           1'b0
+    2       R      rxuis           1'b0
+    3       R      rxois           1'b0
+    4       R      rxfis           1'b0
+    5       R      faeis           1'b0
+    6       R      txuis           1'b0
+    7       R      ssris           1'b0
+    31:8    R      reserved0       24'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        const uint32_t txeis: 1;
+        const uint32_t txois: 1;
+        const uint32_t rxuis: 1;
+        const uint32_t rxois: 1;
+        const uint32_t rxfis: 1;
+        const uint32_t faeis: 1;
+        const uint32_t txuis: 1;
+        const uint32_t ssris: 1;
+        const uint32_t reserved_0: 24;
+    } b;
+} SPI_S_ISR_TypeDef;
+
+
+
+/* 0x34
+    0       R      txeir           1'b0
+    1       R      txoir           1'b0
+    2       R      rxuir           1'b0
+    3       R      rxoir           1'b0
+    4       R      rxfir           1'b0
+    5       R      mstir           1'b0
+    31:6    R      reserved31_6    26'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        const uint32_t txeir: 1;
+        const uint32_t txoir: 1;
+        const uint32_t rxuir: 1;
+        const uint32_t rxoir: 1;
+        const uint32_t rxfir: 1;
+        const uint32_t mstir: 1;
+        const uint32_t reserved_0: 26;
+    } b;
+} SPI_M_RISR_TypeDef;
+
+
+
+/* 0x34
+    0       R      txeir           1'b0
+    1       R      txoir           1'b0
+    2       R      rxuir           1'b0
+    3       R      rxoir           1'b0
+    4       R      rxfir           1'b0
+    5       R      faeir           1'b0
+    6       R      txuir           1'b0
+    7       R      ssrir           1'b0
+    31:8    R      reserved0       24'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        const uint32_t txeir: 1;
+        const uint32_t txoir: 1;
+        const uint32_t rxuir: 1;
+        const uint32_t rxoir: 1;
+        const uint32_t rxfir: 1;
+        const uint32_t faeir: 1;
+        const uint32_t txuir: 1;
+        const uint32_t ssrir: 1;
+        const uint32_t reserved_0: 24;
+    } b;
+} SPI_S_RISR_TypeDef;
+
+
+
+/* 0x38
+    0       R      txoicr          1'b0
+    31:1    R      reserved0       31'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        const uint32_t txoicr: 1;
+        const uint32_t reserved_0: 31;
+    } b;
+} SPI_TXOICR_TypeDef;
+
+
+
+/* 0x3C
+    0       R      rxoicr          1'b0
+    31:1    R      reserved0       31'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        const uint32_t rxoicr: 1;
+        const uint32_t reserved_0: 31;
+    } b;
+} SPI_RXOICR_TypeDef;
+
+
+
+/* 0x40
+    0       R      rxuicr          1'b0
+    31:1    R      reserved0       31'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        const uint32_t rxuicr: 1;
+        const uint32_t reserved_0: 31;
+    } b;
+} SPI_RXUICR_TypeDef;
+
+
+
+/* 0x44
+    0       R      msticr          1'b0
+    31:1    R      reserved0       31'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        const uint32_t msticr: 1;
+        const uint32_t reserved_0: 31;
+    } b;
+} SPI_M_MSTICR_TypeDef;
+
+
+
+/* 0x44
+    0       R      faeicr          1'b0
+    31:1    R      reserved0       31'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        const uint32_t faeicr: 1;
+        const uint32_t reserved_0: 31;
+    } b;
+} SPI_S_FAEICR_TypeDef;
+
+
+
+/* 0x48
+    0       R      icr             1'b0
+    31:1    R      reserved0       31'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        const uint32_t icr: 1;
+        const uint32_t reserved_0: 31;
+    } b;
+} SPI_ICR_TypeDef;
+
+
+
+/* 0x4C
+    0       R/W    rdmae           1'b0
+    1       R/W    tdmae           1'b0
+    31:2    R      reserved0       30'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t rdmae: 1;
+        uint32_t tdmae: 1;
+        const uint32_t reserved_0: 30;
+    } b;
+} SPI_DMACR_TypeDef;
+
+
+
+/* 0x50
+    5:0     R/W    dmatdl          6'b0
+    31:6    R      reserved0       26'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t dmatdl: 6;
+        const uint32_t reserved_0: 26;
+    } b;
+} SPI_DMATDLR_TypeDef;
+
+
+
+/* 0x54
+    5:0     R/W    dmardl          6'b0
+    31:6    R      reserved0       26'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t dmardl: 6;
+        const uint32_t reserved_0: 26;
+    } b;
+} SPI_DMARDLR_TypeDef;
+
+
+
+/* 0x58
+    31:0    R      idcode       32'hffffffff
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        const uint32_t idcode: 32;
+    } b;
+} SPI_M_IDR_TypeDef;
+
+
+
+/* 0x58
+    0       R      txuicr          1'b0
+    31:1    R      reserved0       31'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        const uint32_t txuicr: 1;
+        const uint32_t reserved_0: 31;
+    } b;
+} SPI_S_TXUICR_TypeDef;
+
+
+
+/* 0x5C
+    31:0    R      ssi_comp_version       32'h3430322a
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        const uint32_t ssi_comp_version: 32;
+    } b;
+} SPI_M_VERSION_ID_TypeDef;
+
+
+
+/* 0x5C
+    0       R      ssricr          1'b0
+    31:1    R      reserved0       31'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        const uint32_t ssricr: 1;
+        const uint32_t reserved_0: 31;
+    } b;
+} SPI_S_SSRICR_TypeDef;
+
+
+
+/* 0x60
+    31:0    R/W    dr              32'b0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t dr: 32;
+    } b;
+} SPI_DR_TypeDef;
+
+
+
+/* 0xF0
+    7:0     R/W    rsd             8'b0
+    31:8    R      reserved0       24'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t rsd: 8;
+        const uint32_t reserved_0: 24;
+    } b;
+} SPI_M_RSDR_TypeDef;
+
+/* ================================================================================ */
+/* ================                   SPI  Constants               ================ */
+/* ================================================================================ */
+/** \defgroup SPI         SPI
+  * \brief
+  * \{
+  */
+
+/** \defgroup SPI_Exported_Constants SPI Exported Constants
+  * \brief
+  * \{
+  */
+
+/**
+ * \defgroup    SPI_Clock_Source SPI Clock Source
+ * \{
+ * \ingroup     SPI_Exported_Constants
+ */
+typedef enum
+{
+    SPI_CLOCK_SRC_PLL1 = 0x0,    //!< The SPI clock source is PLL1.
+    SPI_CLOCK_SRC_PLL2 = 0x1,    //!< The SPI clock source is PLL2.
+    SPI_CLOCK_SRC_40M = 0x2,     //!< The SPI clock source is 40MHz.
+} SPIClockSrc_TypeDef;
+
+#define IS_SPI_CLK_SOURCE(PERIPH)     (((PERIPH) == SPI_CLOCK_SRC_40M) || \
+                                       ((PERIPH) == SPI_CLOCK_SRC_PLL1) || \
+                                       ((PERIPH) == SPI_CLOCK_SRC_PLL2)) //!< Check if the input parameter is valid.
+
+/** End of SPI_Clock_Source
+  * \}
+  */
+
+/**
+ * \defgroup    SPI_Clock_Divider SPI Clock Divider
+ * \{
+ * \ingroup     SPI_Exported_Constants
+ */
+typedef enum
+{
+    SPI_CLOCK_DIVIDER_1 = 0x0,      //!< The clock divider is 1.
+    SPI_CLOCK_DIVIDER_2 = 0x1,      //!< The clock divider is 2.
+    SPI_CLOCK_DIVIDER_4 = 0x2,      //!< The clock divider is 4.
+    SPI_CLOCK_DIVIDER_8 = 0x3,      //!< The clock divider is 8.
+    SPI_CLOCK_DIVIDER_16 = 0x4,     //!< The clock divider is 16.
+    SPI_CLOCK_DIVIDER_32 = 0x5,     //!< The clock divider is 32.
+    SPI_CLOCK_DIVIDER_40 = 0x6,     //!< The clock divider is 40.
+    SPI_CLOCK_DIVIDER_64 = 0x7,     //!< The clock divider is 64.
+} SPIClockDiv_TypeDef;
+
+#define IS_SPI_CLK_DIV(DIV) (((DIV) == SPI_CLOCK_DIVIDER_1) || \
+                             ((DIV) == SPI_CLOCK_DIVIDER_2) || \
+                             ((DIV) == SPI_CLOCK_DIVIDER_4) || \
+                             ((DIV) == SPI_CLOCK_DIVIDER_8) || \
+                             ((DIV) == SPI_CLOCK_DIVIDER_16) || \
+                             ((DIV) == SPI_CLOCK_DIVIDER_32) || \
+                             ((DIV) == SPI_CLOCK_DIVIDER_40) || \
+                             ((DIV) == SPI_CLOCK_DIVIDER_64)) //!< Check if the input parameter is valid.
+
+/** End of SPI_Clock_Divider
+  * \}
+  */
+
+/*============================================================================*
+ *                          SPI TYPE/API Wrappers
+ *============================================================================*/
+/**
+ * \defgroup SPI_API_Wrapper SPI API Wrapper
+ * \{
+ * \ingroup  SPI_Exported_Constants
+ */
+#define SPI_Change_CLK                  SPI_ChangeClock      //!< The macro is a wrapper for SPI_ChangeClock
+#define SPI_NDF                         SPI_RXNDF            //!< The macro is a wrapper for SPI_RXNDF
+
+#define CK_40M_SPI                      SPI_CLOCK_SRC_40M    //!< The macro is a wrapper for SPI_CLOCK_SRC_40M
+#define CK_PLL1_SPI                     SPI_CLOCK_SRC_PLL1   //!< The macro is a wrapper for SPI_CLOCK_SRC_PLL1
+#define CK_PLL2_SPI                     SPI_CLOCK_SRC_PLL2   //!< The macro is a wrapper for SPI_CLOCK_SRC_PLL2
+
+/** End of SPI_API_Wrapper
+  * \}
+  */
+
+/** End of SPI_Exported_Constants
+  * \}
+  */
+
+/** End of SPI
+  * \}
+  */
+
+#ifdef  __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* RTL_SPI_DEF_H */
diff --git a/bee/drivers/spi/src/device/rtl87x2j/rtl87x2j_spi.c b/bee/drivers/spi/src/device/rtl87x2j/rtl87x2j_spi.c
new file mode 100644
index 00000000..91732da4
--- /dev/null
+++ b/bee/drivers/spi/src/device/rtl87x2j/rtl87x2j_spi.c
@@ -0,0 +1,128 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *                           Header Files
+ *============================================================================*/
+#include "rtl_spi.h"
+
+/*============================================================================*
+ *                           Private Defines
+ *============================================================================*/
+#define SPI_CLOCK_AUTO_MODE_CONFIG_AUTOMATIC       (0x00000)
+#define SPI_CLOCK_AUTO_MODE_CONFIG_ALWAYSRUN       (0x3003F)
+/*============================================================================*
+ *                           Public Functions
+ *============================================================================*/
+/**
+  * \brief  SPI clock config.
+  * \param  SPIx: Select the SPI peripheral. \ref SPI_Declaration
+  * \param  ClockSrc: specifies the clock source to gates its clock.
+  * \param  ClockDiv: specifies the clock divide to gates its clock.
+  * \return None
+  */
+void SPI_SetClock(SPI_TypeDef *SPIx, SPIClockSrc_TypeDef ClockSrc, SPIClockDiv_TypeDef ClockDiv)
+{
+    assert_param(IS_SPI_CLOCK_DIV(ClockDiv));
+    assert_param(IS_SPI_CLOCK_SRC(ClockSrc));
+
+    if ((SPIx == SPI0) || (SPIx == SPI0_HS))
+    {
+        PCC_REG_WRITE_BITFIELD(PCC_REG_SPI0, R_SPI0_CLK_SRC_SEL, ClockSrc);
+        PCC_REG_WRITE_BITFIELD(PCC_REG_SPI0, R_SPI0_CLK_DIV_SEL, ClockDiv);
+    }
+    else if ((SPIx == SPI1) || (SPIx == SPI1_HS))
+    {
+        PCC_REG_WRITE_BITFIELD(PCC_REG_SPI1, R_SPI1_CLK_SRC_SEL, ClockSrc);
+        PCC_REG_WRITE_BITFIELD(PCC_REG_SPI1, R_SPI1_CLK_DIV_SEL, ClockDiv);
+    }
+    else if (SPIx == SPI2)
+    {
+        PCC_REG_WRITE_BITFIELD(PCC_REG_SPI2, R_SPI2_CLK_SRC_SEL, ClockSrc);
+        PCC_REG_WRITE_BITFIELD(PCC_REG_SPI2, R_SPI2_CLK_DIV_SEL, ClockDiv);
+    }
+
+    return;
+}
+
+void SPI_ClockAutoModeCmd(SPI_TypeDef *SPIx, FunctionalState Newstate)
+{
+    /* Check the parameters */
+    assert_param(IS_SPI_ALL_PERIPH(SPIx));
+
+    if (Newstate == ENABLE)
+    {
+        SPIx->SPI_WRAP_QACTIVE_MAN = SPI_CLOCK_AUTO_MODE_CONFIG_AUTOMATIC;
+    }
+    else
+    {
+        SPIx->SPI_WRAP_QACTIVE_MAN = SPI_CLOCK_AUTO_MODE_CONFIG_ALWAYSRUN;
+    }
+
+    return;
+}
+
+void SPI_SPI0AHBBridgeConfig(FunctionalState NewState)
+{
+    if (NewState == ENABLE)
+    {
+        /* Open SPI0 AHB bridge*/
+        PCC_REG_WRITE_BITFIELD(PCC_REG_SPI0, PON_SPI0_H2S_BRG_EN, 1);
+    }
+    else
+    {
+        /* Close SPI0 AHB bridge*/
+        PCC_REG_WRITE_BITFIELD(PCC_REG_SPI0, PON_SPI0_H2S_BRG_EN, 0);
+    }
+}
+
+void SPI_SPI1AHBBridgeConfig(FunctionalState NewState)
+{
+    if (NewState == ENABLE)
+    {
+        /* Open SPI1 AHB bridge*/
+        PCC_REG_WRITE_BITFIELD(PCC_REG_SPI1, PON_SPI1_H2S_BRG_EN, 1);
+    }
+    else
+    {
+        /* Close SPI1 AHB bridge*/
+        PCC_REG_WRITE_BITFIELD(PCC_REG_SPI1, PON_SPI1_H2S_BRG_EN, 0);
+    }
+}
+
+
+void SPI_ConfigAPHBridge(SPI_TypeDef *SPIx)
+{
+    if (SPIx == SPI0)
+    {
+        PCC_REG_WRITE_BITFIELD(PCC_REG_SPI0, PON_SPI0_BRG_EN, 1);
+    }
+    else if (SPIx == SPI1)
+    {
+        PCC_REG_WRITE_BITFIELD(PCC_REG_SPI1, PON_SPI1_BRG_EN, 1);
+    }
+    else if (SPIx == SPI2)
+    {
+        PCC_REG_WRITE_BITFIELD(PCC_REG_SPI2, PON_SPI2_BRG_EN, 1);
+    }
+}
+
+void SPI_ConfigMasterSlave(SPIMode_Typedef SPI_Mode)
+{
+    if (SPI_Mode == SPI_MODE_MASTER)
+    {
+        /* Enable SPI0 master mode */
+        PCC_REG_WRITE_BITFIELD(PCC_REG_SPI0, PON_SPI0_MST, 1);
+    }
+    else if (SPI_Mode == SPI_MODE_SLAVE)
+    {
+        /* Enable SPI0 slave mode */
+        PCC_REG_WRITE_BITFIELD(PCC_REG_SPI0, PON_SPI0_MST, 0);
+    }
+}
+
+
+
diff --git a/bee/drivers/spi/src/device/rtl87x2j/rtl_spi_def.h b/bee/drivers/spi/src/device/rtl87x2j/rtl_spi_def.h
new file mode 100644
index 00000000..41788767
--- /dev/null
+++ b/bee/drivers/spi/src/device/rtl87x2j/rtl_spi_def.h
@@ -0,0 +1,1246 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef RTL_SPI_DEF_H
+#define RTL_SPI_DEF_H
+
+#include "utils/rtl_utils.h"
+#include "address_map.h"
+#include "pcc_reg.h"
+
+#ifdef  __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+
+/*============================================================================*
+ *                          SPI Defines
+ *============================================================================*/
+/** \defgroup SPI         SPI
+  * \brief
+  * \{
+  */
+
+/** \defgroup SPI_Exported_Constants SPI Exported Constants
+  * \brief
+  * \{
+  */
+
+/**
+ * \defgroup SPI_Defines SPI Defines
+ * \{
+ * \ingroup  SPI_Exported_Constants
+ */
+#define SPI_TX_FIFO_SIZE                               (16)
+#define SPI_RX_FIFO_SIZE                               (16)
+#define SPI0_SLAVE_TX_FIFO_SIZE                        (32)
+#define SPI0_SLAVE_RX_FIFO_SIZE                        (32)
+#define SPI_WRAPPER_TX_FIFO_SIZE                       (32)
+#define SPI_SUPPORT_WRAP_MODE                          (1)
+#define SPI0_SUPPORT_MASTER_SLAVE                      (1)
+#define SPI0_SUPPORT_HS                                (1)
+#define SPI1_SUPPORT_HS                                (1)
+#define SPI2_SUPPORT_HS                                (0)
+#define SPI_SUPPORT_APH_BRIDGE_FOR_HIGH_SPEED          (1)
+#define SPI_SUPPORT_DFS_4BIT_TO_16BIT                  (1)
+#define SPI_SUPPORT_SWAP                               (0)
+#define SPI_SUPPORT_RAP_FUNCTION                       (1)
+#define SPI_SUPPORT_CLOCK_SOURCE_CONFIG                (1)
+#define SPI_SUPPORT_AUTO_CLOCK                         (1)
+
+#define SPI_DFS_BIT_FIELD                              dfs
+#define SPI_IN_SLAVE_MODE(SPIx)                       ((SPIx == SPI0) && (PCC_REG_READ_BITFIELD(PCC_REG_SPI0, PON_SPI0_MST) == 0))
+/** End of SPI_Defines
+  * \}
+  */
+
+/** End of SPI_Exported_Constants
+  * \}
+  */
+
+/** End of SPI
+  * \}
+  */
+
+/*============================================================================*
+ *                         SPI Registers Memory Map
+ *============================================================================*/
+typedef struct
+{
+    __IO uint32_t SPI_M_S_CTRL0;                /*!< 0x00 */
+    __IO uint32_t SPI_M_CTRL1;                  /*!< 0x04 */
+    __IO uint32_t SPI_SPIENR;                   /*!< 0x08 */
+    __IO uint32_t RSVD_0C;                      /*!< 0x0C */
+    __IO uint32_t SPI_M_SER;                    /*!< 0x10 */
+    __IO uint32_t SPI_M_BAUDR;                  /*!< 0x14 */
+    __IO uint32_t SPI_TXFTLR;                   /*!< 0x18 */
+    __IO uint32_t SPI_RXFTLR;                   /*!< 0x1C */
+    __I  uint32_t SPI_TXFLR;                    /*!< 0x20 */
+    __I  uint32_t SPI_RXFLR;                    /*!< 0x24 */
+    __I  uint32_t SPI_M_S_SR;                   /*!< 0x28 */
+    __IO uint32_t SPI_M_S_IMR;                  /*!< 0x2C */
+    __I  uint32_t SPI_M_S_ISR;                  /*!< 0x30 */
+    __I  uint32_t SPI_M_S_RISR;                 /*!< 0x34 */
+    __I  uint32_t SPI_TXOICR;                   /*!< 0x38 */
+    __I  uint32_t SPI_RXOICR;                   /*!< 0x3C */
+    __I  uint32_t SPI_RXUICR;                   /*!< 0x40 */
+    __I  uint32_t SPI_M_S_MSTICR_FAEICR;        /*!< 0x44 */
+    __I  uint32_t SPI_ICR;                      /*!< 0x48 */
+    __IO uint32_t SPI_DMACR;                    /*!< 0x4C */
+    __IO uint32_t SPI_DMATDLR;                  /*!< 0x50 */
+    __IO uint32_t SPI_DMARDLR;                  /*!< 0x54 */
+    __I  uint32_t SPI_M_S_IDR_TXUICR;           /*!< 0x58 */
+    __I  uint32_t SPI_M_S_VERSION_ID_SSRICR;    /*!< 0x5C */
+    __IO uint32_t SPI_DR[36];                   /*!< 0x60 - 0xEC */
+    __IO uint32_t SPI_M_RSDR;                   /*!< 0xF0 */
+    __IO uint32_t RSVD_F4[67];                  /*!< 0xF4 - 0x1FC */
+    __IO uint32_t SPI_WRAP_CTRL;                /*!< 0x200 */
+    __IO uint32_t SPI_WRAP_TXFTLR;              /*!< 0x204 */
+    __I  uint32_t SPI_MST_TXFLR;                /*!< 0x208 */
+    __I  uint32_t SPI_WRAP_SR;                  /*!< 0x20C */
+    __IO uint32_t SPI_WRAP_IMR;                 /*!< 0x210 */
+    __I  uint32_t SPI_WRAP_ISR;                 /*!< 0x214 */
+    __I  uint32_t SPI_WRAP_RISR;                /*!< 0x218 */
+    __I  uint32_t SPI_WRAP_ICR;                 /*!< 0x21C */
+    __IO uint32_t SPI_WRAP_DMACR;               /*!< 0x220 */
+    __IO uint32_t SPI_WRAP_DMATDLR;             /*!< 0x224 */
+    __I  uint32_t SPI_WRAP_TXNDF_CNT;           /*!< 0x228 */
+    __IO uint32_t SPI_WRAP_CS_DLY;              /*!< 0x22C */
+    __IO uint32_t SPI_WRAP_TCMD_NUM;            /*!< 0x230 */
+    __IO uint32_t SPI_WRAP_TWAIT_NUM;           /*!< 0x234 */
+    __IO uint32_t SPI_WRAP_TTRAN_NUM;           /*!< 0x238 */
+    __IO uint32_t SPI_WRAP_FW_ST;               /*!< 0x23C */
+    __IO uint32_t SPI_WRAP_TASK_STS;            /*!< 0x240 */
+    __IO uint32_t SPI_WRAP_QACTIVE_MAN;         /*!< 0x244 */
+} SPI_TypeDef;
+
+/*============================================================================*
+ *                         SPI Declaration
+ *============================================================================*/
+/** \defgroup SPI         SPI
+  * \brief
+  * \{
+  */
+
+/** \defgroup SPI_Exported_Constants SPI Exported Constants
+  * \brief
+  * \{
+  */
+
+/** \defgroup SPI_Declaration SPI Declaration
+  * \brief
+  * \{
+  */
+
+#define SPI0                      ((SPI_TypeDef *) SPI0_BASE)
+#define SPI1                      ((SPI_TypeDef *) SPI1_BASE)
+#define SPI2                      ((SPI_TypeDef *) SPI2_BASE)
+#define SPI0_HS                   ((SPI_TypeDef *) SPI0_HS_BASE)
+#define SPI1_HS                   ((SPI_TypeDef *) SPI1_HS_BASE)
+
+#define IS_SPIM_PERIPH(PERIPH)    (((PERIPH) == SPI0) || \
+                                   ((PERIPH) == SPI1) || \
+                                   ((PERIPH) == SPI2) || \
+                                   ((PERIPH) == SPI0_HS) || \
+                                   ((PERIPH) == SPI1_HS))
+
+#define IS_SPI_ALL_PERIPH(PERIPH) (IS_SPIM_PERIPH(PERIPH) || \
+                                   IS_SPIS_PERIPH(PERIPH))
+
+/** End of SPI_Declaration
+  * \}
+  */
+
+/** End of SPI_Exported_Constants
+  * \}
+  */
+
+/** End of SPI
+  * \}
+  */
+
+/*============================================================================*
+ *                         SPI Private Types
+ *============================================================================*/
+typedef struct
+{
+    uint32_t spi_reg[12];
+} SPIStoreReg_Typedef;
+
+/*============================================================================*
+ *                         SPI Registers and Field Descriptions
+ *============================================================================*/
+/* 0x00
+   3:0     R/W    dfs                 4'h0
+   5:4     R/W    frf                 2'b0
+   6       R/W    scph                1'b0
+   7       R/W    scpol               1'b0
+   9:8     R/W    tmod                2'b0
+   11:10   R      reserved0_11_10     2'b0
+   15:12   R      reserved0_15_12     4'b0
+   20:16   R      dfs_31              5'h0
+   22:21   R      spi_frf             2'b0
+   23      R      reserved0_23        1'b0
+   24      R/W    sste                1'b1
+   31:25   R      reserved0_31_25     7'b0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t dfs: 4;
+        uint32_t frf: 2;
+        uint32_t scph: 1;
+        uint32_t scpol: 1;
+        uint32_t tmod: 2;
+        const uint32_t reserved_3: 2;
+        const uint32_t reserved_2: 4;
+        const uint32_t dfs_31: 5;
+        const uint32_t spi_frf: 2;
+        const uint32_t reserved_1: 1;
+        uint32_t sste: 1;
+        const uint32_t reserved_0: 7;
+    } b;
+} SPI_M_CTRL0_TypeDef;
+
+
+/* 0x00
+    3:0     R/W    dfs             4'h7
+    5:4     R      reserved5_4     2'b0
+    6       R/W    scph            1'b0
+    7       R/W    scpol           1'b0
+    9:8     R      reserved9_8     2'b0
+    10      R/W    slv_oe          1'b0
+    20:11   R      reserved20_11   10'b0
+    21      R/W    tx_byte_swap    1'b0
+    22      R/W    tx_bit_swap     1'b0
+    23      R/W    rx_byte_swap    1'b0
+    24      R/W    rx_bit_swap     1'b0
+    31:25   R      reserved31_25   7'b0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t dfs: 4;
+        const uint32_t reserved_3: 2;
+        uint32_t scph: 1;
+        uint32_t scpol: 1;
+        const uint32_t reserved_2: 2;
+        uint32_t slv_oe: 1;
+        const uint32_t reserved_1: 10;
+        uint32_t tx_byte_swap: 1;
+        uint32_t tx_bit_swap: 1;
+        uint32_t rx_byte_swap: 1;
+        uint32_t rx_bit_swap: 1;
+        const uint32_t reserved_0: 7;
+    } b;
+} SPI_S_CTRL0_TypeDef;
+
+
+
+/* 0x04
+    15:0    R/W    ndf             16'h0
+    31:16   R      reserved0       16'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t ndf: 16;
+        const uint32_t reserved_0: 16;
+    } b;
+} SPI_M_CTRL1_TypeDef;
+
+
+
+/* 0x08
+    0       R/W    spi_en          1'b0
+    31:1    R      reserved0       31'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t spi_en: 1;
+        const uint32_t reserved_0: 31;
+    } b;
+} SPI_SPIENR_TypeDef;
+
+
+
+/* 0x10
+    0       R/W    ser             1'b0
+    31:1    R      reserved0       31'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t ser: 1;
+        const uint32_t reserved_0: 31;
+    } b;
+} SPI_M_SER_TypeDef;
+
+
+
+/* 0x14
+    15:0    R/W    sckdv           16'b0
+    31:16   R      reserved0       16'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t sckdv: 16;
+        const uint32_t reserved_0: 16;
+    } b;
+} SPI_M_BAUDR_TypeDef;
+
+
+
+/* 0x18
+   4:0     R/W    tft                 5'b0
+   31:5    R      reserved18_31_5     27'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t tft: 5;
+        const uint32_t reserved_0: 27;
+    } b;
+} SPI_TXFTLR_TypeDef;
+
+
+
+/* 0x1C
+   4:0     R/W    rft                 5'b0
+   31:5    R      reserved1c_31_5     27'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t rft: 5;
+        const uint32_t reserved_0: 27;
+    } b;
+} SPI_RXFTLR_TypeDef;
+
+
+
+/* 0x20
+   4:0     R      txtfl               5'b0
+   31:5    R      reserved20_31_5     27'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t txtfl: 5;
+        const uint32_t reserved_0: 27;
+    } b;
+} SPI_TXFLR_TypeDef;
+
+
+
+
+/* 0x24
+   4:0     R      rxtfl               5'b0
+   31:5    R      reserved24_31_5     27'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t rxtfl: 5;
+        const uint32_t reserved_0: 27;
+    } b;
+} SPI_RXFLR_TypeDef;
+
+
+
+/* 0x28
+    0       R      busy            1'b0
+    1       R      tfnf            1'b1
+    2       R      tfe             1'b1
+    3       R      rfne            1'b0
+    4       R      rff             1'b0
+    5       R      reserved5       1'b0
+    6       R      dcol            1'b0
+    31:7    R      reserved31_7    25'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t busy: 1;
+        const uint32_t tfnf: 1;
+        const uint32_t tfe: 1;
+        const uint32_t rfne: 1;
+        const uint32_t rff: 1;
+        const uint32_t reserved_1: 1;
+        const uint32_t dcol: 1;
+        const uint32_t reserved_0: 25;
+    } b;
+} SPI_M_SR_TypeDef;
+
+
+
+/* 0x28
+    0       R      busy            1'b0
+    1       R      tfnf            1'b1
+    2       R      tfe             1'b1
+    3       R      rfne            1'b0
+    4       R      rff             1'b0
+    5       R      txe             1'b0
+    6       R      reserved6       1'b0
+    31:7    R      reserved31_7    25'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t busy: 1;
+        const uint32_t tfnf: 1;
+        const uint32_t tfe: 1;
+        const uint32_t rfne: 1;
+        const uint32_t rff: 1;
+        const uint32_t txe: 1;
+        const uint32_t reserved_1: 1;
+        const uint32_t reserved_0: 25;
+    } b;
+} SPI_S_SR_TypeDef;
+
+
+
+/* 0x2C
+    0       R/W    txeim           1'b1
+    1       R/W    txoim           1'b1
+    2       R/W    rxuim           1'b1
+    3       R/W    rxoim           1'b1
+    4       R/W    rxfim           1'b1
+    31:5    R      reserved31_5    27'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t txeim: 1;
+        uint32_t txoim: 1;
+        uint32_t rxuim: 1;
+        uint32_t rxoim: 1;
+        uint32_t rxfim: 1;
+        const uint32_t reserved_0: 27;
+    } b;
+} SPI_M_IMR_TypeDef;
+
+
+
+/* 0x2C
+    0       R/W    txeim           1'b1
+    1       R/W    txoim           1'b1
+    2       R/W    rxuim           1'b1
+    3       R/W    rxoim           1'b1
+    4       R/W    rxfim           1'b1
+    5       R/W    faeim           1'b1
+    6       R/W    txuim           1'b1
+    7       R/W    ssrim           1'b1
+    31:8    R      reserved0       24'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t txeim: 1;
+        uint32_t txoim: 1;
+        uint32_t rxuim: 1;
+        uint32_t rxoim: 1;
+        uint32_t rxfim: 1;
+        uint32_t faeim: 1;
+        uint32_t txuim: 1;
+        uint32_t ssrim: 1;
+        const uint32_t reserved_0: 24;
+    } b;
+} SPI_S_IMR_TypeDef;
+
+
+
+/* 0x30
+    0       R      txeis           1'b0
+    1       R      txois           1'b0
+    2       R      rxuis           1'b0
+    3       R      rxois           1'b0
+    4       R      rxfis           1'b0
+    31:5    R      reserved31_5    27'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t txeis: 1;
+        const uint32_t txois: 1;
+        const uint32_t rxuis: 1;
+        const uint32_t rxois: 1;
+        const uint32_t rxfis: 1;
+        const uint32_t reserved_0: 27;
+    } b;
+} SPI_M_ISR_TypeDef;
+
+
+
+/* 0x30
+    0       R      txeis           1'b0
+    1       R      txois           1'b0
+    2       R      rxuis           1'b0
+    3       R      rxois           1'b0
+    4       R      rxfis           1'b0
+    5       R      faeis           1'b0
+    6       R      txuis           1'b0
+    7       R      ssris           1'b0
+    31:8    R      reserved0       24'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t txeis: 1;
+        const uint32_t txois: 1;
+        const uint32_t rxuis: 1;
+        const uint32_t rxois: 1;
+        const uint32_t rxfis: 1;
+        const uint32_t faeis: 1;
+        const uint32_t txuis: 1;
+        const uint32_t ssris: 1;
+        const uint32_t reserved_0: 24;
+    } b;
+} SPI_S_ISR_TypeDef;
+
+
+
+/* 0x34
+    0       R      txeir           1'b0
+    1       R      txoir           1'b0
+    2       R      rxuir           1'b0
+    3       R      rxoir           1'b0
+    4       R      rxfir           1'b0
+    31:5    R      reserved31_5    27'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t txeir: 1;
+        const uint32_t txoir: 1;
+        const uint32_t rxuir: 1;
+        const uint32_t rxoir: 1;
+        const uint32_t rxfir: 1;
+        const uint32_t reserved_0: 27;
+    } b;
+} SPI_M_RISR_TypeDef;
+
+
+
+/* 0x34
+    0       R      txeir           1'b0
+    1       R      txoir           1'b0
+    2       R      rxuir           1'b0
+    3       R      rxoir           1'b0
+    4       R      rxfir           1'b0
+    5       R      faeir           1'b0
+    6       R      txuir           1'b0
+    7       R      ssrir           1'b0
+    31:8    R      reserved0       24'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t txeir: 1;
+        const uint32_t txoir: 1;
+        const uint32_t rxuir: 1;
+        const uint32_t rxoir: 1;
+        const uint32_t rxfir: 1;
+        const uint32_t faeir: 1;
+        const uint32_t txuir: 1;
+        const uint32_t ssrir: 1;
+        const uint32_t reserved_0: 24;
+    } b;
+} SPI_S_RISR_TypeDef;
+
+
+
+/* 0x38
+    0       R      txoicr          1'b0
+    31:1    R      reserved0       31'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t txoicr: 1;
+        const uint32_t reserved_0: 31;
+    } b;
+} SPI_TXOICR_TypeDef;
+
+
+
+/* 0x3C
+    0       R      rxoicr          1'b0
+    31:1    R      reserved0       31'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t rxoicr: 1;
+        const uint32_t reserved_0: 31;
+    } b;
+} SPI_RXOICR_TypeDef;
+
+
+
+/* 0x40
+    0       R      rxuicr          1'b0
+    31:1    R      reserved0       31'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t rxuicr: 1;
+        const uint32_t reserved_0: 31;
+    } b;
+} SPI_RXUICR_TypeDef;
+
+
+
+/* 0x44
+    0       R      msticr          1'b0
+    31:1    R      reserved0       31'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t msticr: 1;
+        const uint32_t reserved_0: 31;
+    } b;
+} SPI_M_MSTICR_TypeDef;
+
+
+
+/* 0x44
+    0       R      faeicr          1'b0
+    31:1    R      reserved0       31'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t faeicr: 1;
+        const uint32_t reserved_0: 31;
+    } b;
+} SPI_S_FAEICR_TypeDef;
+
+
+
+/* 0x48
+    0       R      icr             1'b0
+    31:1    R      reserved0       31'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t icr: 1;
+        const uint32_t reserved_0: 31;
+    } b;
+} SPI_ICR_TypeDef;
+
+
+
+/* 0x4C
+    0       R/W    rdmae           1'b0
+    1       R/W    tdmae           1'b0
+    31:2    R      reserved0       30'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t rdmae: 1;
+        uint32_t tdmae: 1;
+        const uint32_t reserved_0: 30;
+    } b;
+} SPI_DMACR_TypeDef;
+
+
+
+/* 0x50
+   3:0     R/W    dmatdl              4'b0
+   31:4    R      reserved50_31_4     28'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t dmatdl: 4;
+        const uint32_t reserved_0: 28;
+    } b;
+} SPI_DMATDLR_TypeDef;
+
+
+
+/* 0x54
+   3:0     R/W    dmardl              4'b0
+   31:4    R      reserved54_31_4     28'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t dmardl: 4;
+        const uint32_t reserved_0: 28;
+    } b;
+} SPI_DMARDLR_TypeDef;
+
+
+
+/* 0x58
+    31:0    R      idcode       32'hffffffff
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t idcode: 32;
+    } b;
+} SPI_M_IDR_TypeDef;
+
+
+
+/* 0x58
+    0       R      txuicr          1'b0
+    31:1    R      reserved0       31'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t txuicr: 1;
+        const uint32_t reserved_0: 31;
+    } b;
+} SPI_S_TXUICR_TypeDef;
+
+
+
+/* 0x5C
+    31:0    R      ssi_comp_version       32'h3430322a
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t ssi_comp_version: 32;
+    } b;
+} SPI_M_VERSION_ID_TypeDef;
+
+
+
+/* 0x5C
+    0       R      ssricr          1'b0
+    31:1    R      reserved0       31'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t ssricr: 1;
+        const uint32_t reserved_0: 31;
+    } b;
+} SPI_S_SSRICR_TypeDef;
+
+
+
+/* 0x60
+    31:0    R/W    dr              32'b0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t dr: 32;
+    } b;
+} SPI_DR_TypeDef;
+
+
+
+/* 0xF0
+    7:0     R/W    rsd             8'b0
+    31:8    R      reserved0       24'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t rsd: 8;
+        const uint32_t reserved_0: 24;
+    } b;
+} SPI_M_RSDR_TypeDef;
+
+
+/* 0x200
+   0       R/W    wrap_ctrl_mode      1'b0
+   1       R/WAC  mst_tx_fifo_en      1'b0
+   2       R/W    tx_fifo_rst         1'b0
+   3       R/W    mosi_pull_en        1'b0
+   4       R/W    mosi_drv_low_en     1'b0
+   5       R/W    cs_inv_en           1'b0
+   6       R/W    rap_ctrl_mode       1'b0
+   15:7    R      reserved200_15_7    9'b0
+   31:16   R/W    mst_tx_ndf          16'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t wrap_ctrl_mode: 1;
+        uint32_t mst_tx_fifo_en: 1;
+        uint32_t tx_fifo_rst: 1;
+        uint32_t mosi_pull_en: 1;
+        uint32_t mosi_drv_low_en: 1;
+        uint32_t cs_inv_en: 1;
+        uint32_t rap_ctrl_mode: 1;
+        const uint32_t reserved_0: 9;
+        uint32_t mst_tx_ndf: 16;
+    } b;
+} SPI_WRAP_CTRL_TypeDef;
+
+
+/* 0x204
+   4:0     R/W    tx_fifo_tl          5'b0
+   31:5    R      reserved204_31_5    27'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t tx_fifo_tl: 5;
+        const uint32_t reserved_0: 27;
+    } b;
+} SPI_WRAP_TXFTLR_TypeDef;
+
+
+/* 0x208
+   4:0     R      tx_fifo_lv          5'b0
+   31:5    R      reserved208_31_5    27'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t tx_fifo_lv: 5;
+        const uint32_t reserved_0: 27;
+    } b;
+} SPI_MST_TXFLR_TypeDef;
+
+
+/* 0x20C
+   0       R      cs_en               1'b0
+   1       R      tx_fifo_not_full    1'b1
+   2       R      tx_fifo_empty       1'b1
+   31:3    R      reserved20c_31_3    29'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t cs_en: 1;
+        const uint32_t tx_fifo_not_full: 1;
+        const uint32_t tx_fifo_empty: 1;
+        const uint32_t reserved_0: 29;
+    } b;
+} SPI_WRAP_SR_TypeDef;
+
+
+/* 0x210
+   0       R/W    tx_fifo_empty_int_m 1'b0
+   1       R/W    tx_fifo_ov_int_m    1'b0
+   2       R/W    tx_ndf_done_int_m   1'b0
+   31:3    R      reserved210_31_3    29'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t tx_fifo_empty_int_m: 1;
+        uint32_t tx_fifo_ov_int_m: 1;
+        uint32_t tx_ndf_done_int_m: 1;
+        const uint32_t reserved_0: 29;
+    } b;
+} SPI_WRAP_IMR_TypeDef;
+
+
+/* 0x214
+   0       R      tx_fifo_empty_int_st1'b0
+   1       R      tx_fifo_ov_int_st   1'b0
+   2       R      tx_ndf_done_int_st  1'b0
+   31:3    R      reserved214_31_3    29'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t tx_fifo_empty_int_st: 1;
+        const uint32_t tx_fifo_ov_int_st: 1;
+        const uint32_t tx_ndf_done_int_st: 1;
+        const uint32_t reserved_0: 29;
+    } b;
+} SPI_WRAP_ISR_TypeDef;
+
+
+/* 0x218
+   0       R      tx_fifo_empty_r_st  1'b0
+   1       R      tx_fifo_ov_r_st     1'b0
+   2       R      tx_ndf_done_r_st    1'b0
+   31:3    R      reserved218_31_3    29'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t tx_fifo_empty_r_st: 1;
+        const uint32_t tx_fifo_ov_r_st: 1;
+        const uint32_t tx_ndf_done_r_st: 1;
+        const uint32_t reserved_0: 29;
+    } b;
+} SPI_WRAP_RISR_TypeDef;
+
+
+/* 0x21C
+   0       R      int_clr             1'b0
+   31:1    R      reserved21c_31_1    31'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t int_clr: 1;
+        const uint32_t reserved_0: 31;
+    } b;
+} SPI_WRAP_ICR_TypeDef;
+
+
+/* 0x220
+   0       R/W    tx_dma_en           1'b0
+   31:1    R      reserved220_31_1    31'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t tx_dma_en: 1;
+        const uint32_t reserved_0: 31;
+    } b;
+} SPI_WRAP_DMACR_TypeDef;
+
+
+/* 0x224
+   4:0     R/W    dma_tx_dl           5'b0
+   31:5    R      reserved224_31_5    27'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t dma_tx_dl: 5;
+        const uint32_t reserved_0: 27;
+    } b;
+} SPI_WRAP_DMATDLR_TypeDef;
+
+
+/* 0x228
+   16:0    R      tx_ndf_cnt          17'b0
+   31:17   R      reserved228_31_17   15'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t tx_ndf_cnt: 17;
+        const uint32_t reserved_0: 15;
+    } b;
+} SPI_WRAP_TXNDF_CNT_TypeDef;
+
+
+/* 0x22C
+   3:0     R/W    cs_setup_dly        4'b0
+   7:4     R      reserved22c_7_4     4'b0
+   11:8    R/W    cs_hold_dly         4'b0
+   15:12   R      reserved22c_15_12   4'b0
+   23:16   R/W    cs_clk_div_sel      8'b0
+   31:24   R      reserved22c_31_24   8'b0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t cs_setup_dly: 4;
+        const uint32_t reserved_2: 4;
+        uint32_t cs_hold_dly: 4;
+        const uint32_t reserved_1: 4;
+        uint32_t cs_clk_div_sel: 8;
+        const uint32_t reserved_0: 8;
+    } b;
+} SPI_WRAP_CS_DLY_TypeDef;
+
+
+/* 0x230
+   3:0     R/W    task_cmd_num        4'b0
+   31:4    R      reserved230_31_4    28'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t task_cmd_num: 4;
+        const uint32_t reserved_0: 28;
+    } b;
+} SPI_WRAP_TCMD_NUM_TypeDef;
+
+
+/* 0x234
+   15:0    R/W    task_wait_num       16'b0
+   31:16   R      reserved234_31_16   16'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t task_wait_num: 16;
+        const uint32_t reserved_0: 16;
+    } b;
+} SPI_WRAP_TWAIT_NUM_TypeDef;
+
+
+/* 0x238
+   15:0    R/W    task_tran_num       16'b0
+   31:16   R      reserved238_31_16   16'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t task_tran_num: 16;
+        const uint32_t reserved_0: 16;
+    } b;
+} SPI_WRAP_TTRAN_NUM_TypeDef;
+
+
+/* 0x23C
+   0       R/WAC  fw_start_task       1'b0
+   31:1    R      reserved23c_31_1    31'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t fw_start_task: 1;
+        const uint32_t reserved_0: 31;
+    } b;
+} SPI_WRAP_FW_ST_TypeDef;
+
+
+/* 0x240
+   0       R/W1C  start_task_sts      1'b0
+   1       R/W1C  start_event_sts     1'b0
+   2       R/W1C  end_event_sts       1'b0
+   31:3    R      reserved240_31_3    29'b0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t start_task_sts: 1;
+        uint32_t start_event_sts: 1;
+        uint32_t end_event_sts: 1;
+        const uint32_t reserved_0: 29;
+    } b;
+} SPI_WRAP_TASK_STS_TypeDef;
+
+
+/* 0x244
+   0       R/W    clk1_qactive_man_data   1'b0
+   1       R/W    clk1_qactive_man_en     1'b0
+   2       R/W    clk2_qactive_man_data   1'b0
+   3       R/W    clk2_qactive_man_en     1'b0
+   4       R/W    clk3_qactive_man_data   1'b0
+   5       R/W    clk3_qactive_man_en     1'b0
+   15:6    R      reserved244_15_6        10'b0
+   16      R/W    pwr_qactive_man_data    1'b0
+   17      R/W    pwr_qactive_man_en      1'b0
+   31:18   R      reserved240_31_18       14'b0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t clk1_qactive_man_data: 1;
+        uint32_t clk1_qactive_man_en: 1;
+        uint32_t clk2_qactive_man_data: 1;
+        uint32_t clk2_qactive_man_en: 1;
+        uint32_t clk3_qactive_man_data: 1;
+        uint32_t clk3_qactive_man_en: 1;
+        const uint32_t reserved_1: 10;
+        uint32_t pwr_qactive_man_data: 1;
+        uint32_t pwr_qactive_man_en: 1;
+        const uint32_t reserved_0: 14;
+    } b;
+} SPI_WRAP_QACTIVE_MAN_TypeDef;
+
+/*============================================================================*
+ *                         SPI Constant
+ *============================================================================*/
+/** \defgroup SPI         SPI
+  * \brief
+  * \{
+  */
+
+/** \defgroup SPI_Exported_Constants SPI Exported Constants
+  * \brief
+  * \{
+  */
+
+/**
+ * \defgroup    SPI_Clock_Source SPI Clock Source
+ * \{
+ * \ingroup     SPI_Exported_Constants
+ */
+typedef enum
+{
+    SPI_CLOCK_SRC_40M = 0x0,
+    SPI_CLOCK_SRC_80M = 0x1,
+} SPIClockSrc_TypeDef;
+
+#define IS_SPI_CLOCK_SRC(CLOCK)     (((CLOCK) == SPI_CLOCK_SRC_40M) || \
+                                     ((CLOCK) == SPI_CLOCK_SRC_80M))
+
+/** End of SPI_Clock_Source
+  * \}
+  */
+
+/**
+ * \defgroup    SPI_Clock_Divider SPI Clock Divider
+ * \{
+ * \ingroup     SPI_Exported_Constants
+ *
+ * \note        SPI2 Clock divider only support:
+ *              SPI_CLOCK_DIV_1
+ *              SPI_CLOCK_DIV_2
+ *              SPI_CLOCK_DIV_4
+ *              SPI_CLOCK_DIV_8
+ */
+typedef enum
+{
+    SPI_CLOCK_DIV_1 = 0x0,
+    SPI_CLOCK_DIV_2 = 0x1,
+    SPI_CLOCK_DIV_4 = 0x2,
+    SPI_CLOCK_DIV_8 = 0x3,
+    SPI_CLOCK_DIV_16 = 0x4,
+    SPI_CLOCK_DIV_32 = 0x5,
+    SPI_CLOCK_DIV_40 = 0x6,
+    SPI_CLOCK_DIV_64 = 0x7,
+} SPIClockDiv_TypeDef;
+
+#define IS_SPI_CLOCK_DIV(DIV) (((DIV) == SPI_CLOCK_DIV_1) || \
+                               ((DIV) == SPI_CLOCK_DIV_2) || \
+                               ((DIV) == SPI_CLOCK_DIV_4) || \
+                               ((DIV) == SPI_CLOCK_DIV_8) || \
+                               ((DIV) == SPI_CLOCK_DIV_16) || \
+                               ((DIV) == SPI_CLOCK_DIV_32) || \
+                               ((DIV) == SPI_CLOCK_DIV_40) || \
+                               ((DIV) == SPI_CLOCK_DIV_64))
+
+/** End of SPI_Clock_Divider
+  * \}
+  */
+
+/**
+ * \defgroup SPI_Constant_Private SPI Constant Private
+ * \{
+ * \ingroup  SPI_Exported_Constants
+ */
+#define SPI_NDF                         SPI_RXNDF
+
+/** End of SPI_Constant_Private
+  * \}
+  */
+
+/** End of SPI_Exported_Constants
+  * \}
+  */
+
+/** End of SPI
+  * \}
+  */
+
+#ifdef  __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* RTL_SPI_DEF_H */
diff --git a/bee/drivers/spi/src/device/rtl_common/rtl_spi.c b/bee/drivers/spi/src/device/rtl_common/rtl_spi.c
new file mode 100644
index 00000000..b8513a5f
--- /dev/null
+++ b/bee/drivers/spi/src/device/rtl_common/rtl_spi.c
@@ -0,0 +1,1280 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *                           Header Files
+ *============================================================================*/
+#include "rtl_spi.h"
+#include "rtl_rcc.h"
+
+#if SPI0_SUPPORT_MASTER_SLAVE
+#define SPI_NOT_SLAVE(SPIx)          (!SPI_IN_SLAVE_MODE(SPIx))
+#define SPI_CONFIGURED_MASTER(mode)  (mode == SPI_MODE_MASTER)
+#else
+
+#ifdef SPI0_SLAVE
+#define SPI_NOT_SLAVE(SPIx)          (SPIx != SPI0_SLAVE)
+#else
+#define SPI_NOT_SLAVE(SPIx)          (1)
+#endif
+
+#define SPI_CONFIGURED_MASTER(mode)  (1)
+#endif
+
+#if SPI0_SUPPORT_MASTER_SLAVE
+extern void SPI_ConfigMasterSlave(SPIMode_Typedef SPI_Mode);
+#endif
+#if (SPI_SUPPORT_APH_BRIDGE_FOR_HIGH_SPEED == 1)
+extern void SPI_ConfigAPHBridge(SPI_TypeDef *SPIx);
+#endif
+#if (SPI0_SUPPORT_HS == 1)
+extern void SPI_SPI0AHBBridgeConfig(FunctionalState NewState);
+#endif
+#if (SPI1_SUPPORT_HS == 1)
+extern void SPI_SPI1AHBBridgeConfig(FunctionalState NewState);
+#endif
+#if (SPI2_SUPPORT_HS == 1)
+extern void SPI_SPI2AHBBridgeConfig(FunctionalState NewState);
+#endif
+/*============================================================================*
+ *                           Public Functions
+ *============================================================================*/
+/**
+  * \brief  Deinitializes the SPIx peripheral registers to their default reset values.
+  * \param  SPIx: Select the SPI peripheral. \ref SPI_Declaration
+  * \return None
+  */
+void SPI_DeInit(SPI_TypeDef *SPIx)
+{
+    /* Check the parameters */
+    assert_param(IS_SPI_ALL_PERIPH(SPIx));
+
+#ifdef SPI0
+    if (SPIx == SPI0)
+    {
+        RCC_ClockCmd(SPI0_CLOCK, DISABLE);
+        return;
+    }
+#endif
+#ifdef SPI0_SLAVE
+    if (SPIx == SPI0_SLAVE)
+    {
+        RCC_ClockCmd(SPI0_SLAVE_CLOCK, DISABLE);
+        return;
+    }
+#endif
+#ifdef SPI1
+    if (SPIx == SPI1)
+    {
+        RCC_ClockCmd(SPI1_CLOCK, DISABLE);
+        return;
+    }
+#endif
+#ifdef SPI2
+    if (SPIx == SPI2)
+    {
+        RCC_ClockCmd(SPI2_CLOCK, DISABLE);
+        return;
+    }
+#endif
+#ifdef SPI3
+    if (SPIx == SPI3)
+    {
+        RCC_ClockCmd(SPI3_CLOCK, DISABLE);
+        return;
+    }
+#endif
+}
+
+/**
+  * \brief  Initializes the SPIx peripheral according to the specified
+  *         parameters in the SPI_InitStruct.
+  * \param  SPIx: Select the SPI peripheral. \ref SPI_Declaration
+  * \param  SPI_InitStruct: Pointer to a SPI_InitTypeDef structure that
+  *         contains the configuration information for the specified SPI peripheral.
+  * \return None
+  */
+void SPI_Init(SPI_TypeDef *SPIx, SPI_InitTypeDef *SPI_InitStruct)
+{
+    /* Check the parameters */
+    assert_param(IS_SPI_ALL_PERIPH(SPIx));
+    assert_param(IS_SPI_DIRECTION_MODE(SPI_InitStruct->SPI_Direction));
+    assert_param(IS_SPI_DATASIZE(SPI_InitStruct->SPI_DataSize));
+    assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL));
+    assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA));
+    assert_param(IS_SPI_FRAME_FORMAT(SPI_InitStruct->SPI_FrameFormat));
+    assert_param(IS_SPI_BAUDRATE_PRESCALER(SPI_InitStruct->SPI_BaudRatePrescaler));
+
+    /* Disable SPI device before change configuration */
+    SPI_SPIENR_TypeDef spi_0x08 = {.d32 = SPIx->SPI_SPIENR};
+    spi_0x08.b.spi_en = 0;
+    SPIx->SPI_SPIENR = spi_0x08.d32;
+
+    /* Configure SPI Master mode if select SPI0, SPI1, SPI2 or SPI3 */
+    if (IS_SPIM_PERIPH(SPIx))
+    {
+#if (SPI0_SUPPORT_MASTER_SLAVE == 1)
+#if (SPI0_SUPPORT_HS == 1)
+        if ((SPIx == SPI0) || (SPIx == SPI0_HS))
+#else
+        if (SPIx == SPI0)
+#endif
+        {
+            SPI_ConfigMasterSlave(SPI_InitStruct->SPI_Mode);
+        }
+#endif
+
+#if (SPI_SUPPORT_APH_BRIDGE_FOR_HIGH_SPEED == 1)
+        SPI_ConfigAPHBridge(SPIx);
+#endif
+
+#if (SPI0_SUPPORT_HS == 1)
+        if (SPIx == SPI0)
+        {
+            SPI_SPI0AHBBridgeConfig(DISABLE);
+        }
+        else if (SPIx == SPI0_HS)
+        {
+            SPI_SPI0AHBBridgeConfig(ENABLE);
+        }
+#endif
+#if (SPI1_SUPPORT_HS == 1)
+        if (SPIx == SPI1)
+        {
+            SPI_SPI1AHBBridgeConfig(DISABLE);
+        }
+        else if (SPIx == SPI1_HS)
+        {
+            SPI_SPI1AHBBridgeConfig(ENABLE);
+        }
+#endif
+#if (SPI2_SUPPORT_HS == 1)
+        if (SPIx == SPI2)
+        {
+            SPI_SPI2AHBBridgeConfig(DISABLE);
+        }
+        else if (SPIx == SPI2_HS)
+        {
+            SPI_SPI2AHBBridgeConfig(ENABLE);
+        }
+#endif
+        /* Configure SPI master mode parameters */
+        SPI_M_CTRL0_TypeDef spi_0x00 = {.d32 = SPIx->SPI_M_S_CTRL0};
+#if (SPI_FIXED_FRAME_FORMAT == 0)
+        spi_0x00.b.frf = SPI_InitStruct->SPI_FrameFormat;
+#endif
+        spi_0x00.b.scph = SPI_InitStruct->SPI_CPHA;
+        spi_0x00.b.scpol = SPI_InitStruct->SPI_CPOL;
+        spi_0x00.b.tmod = SPI_InitStruct->SPI_Direction;
+        spi_0x00.b.SPI_DFS_BIT_FIELD = SPI_InitStruct->SPI_DataSize;
+        spi_0x00.b.sste = SPI_InitStruct->SPI_ToggleEn;
+        SPIx->SPI_M_S_CTRL0 = spi_0x00.d32;
+#if (SPI0_SUPPORT_MASTER_SLAVE == 1)
+        if (SPI_InitStruct->SPI_Mode == SPI_MODE_SLAVE)
+        {
+            SPI_S_CTRL0_TypeDef spi_0x00 = {.d32 = SPIx->SPI_M_S_CTRL0};
+            spi_0x00.b.slv_oe = 0;
+            spi_0x00.b.dfs = SPI_InitStruct->SPI_DataSize;
+            SPIx->SPI_M_S_CTRL0 = spi_0x00.d32;
+        }
+#endif
+
+        /* Set master clock divider */
+        SPI_M_BAUDR_TypeDef spi_0x14 = {.d32 = SPIx->SPI_M_BAUDR};
+        spi_0x14.b.sckdv = SPI_InitStruct->SPI_BaudRatePrescaler % 0xFFFF;
+        SPIx->SPI_M_BAUDR = spi_0x14.d32;
+
+        /* Enable slave Select function in master mode */
+        if (SPI_CONFIGURED_MASTER(SPI_InitStruct->SPI_Mode))
+        {
+            SPI_M_SER_TypeDef spi_0x10 = {.d32 = SPIx->SPI_M_SER};
+            spi_0x10.b.ser = 1;
+            SPIx->SPI_M_SER = spi_0x10.d32;
+        }
+
+        /* Set read length in SPI EEPROM & rx only mode */
+        if ((SPI_InitStruct->SPI_Direction == SPI_DIRECTION_RXONLY) || \
+            (SPI_InitStruct->SPI_Direction == SPI_DIRECTION_EEPROM))
+        {
+            SPI_M_CTRL1_TypeDef spi_0x04 = {.d32 = SPIx->SPI_M_CTRL1};
+            if (SPI_InitStruct->SPI_RXNDF > 0)
+            {
+                spi_0x04.b.ndf = SPI_InitStruct->SPI_RXNDF - 1;
+            }
+            SPIx->SPI_M_CTRL1 = spi_0x04.d32;
+        }
+#if (SPI_SUPPORT_WRAP_MODE == 1)
+        else if ((SPI_InitStruct->SPI_Direction == SPI_DIRECTION_TXONLY) || \
+                 (SPI_InitStruct->SPI_Direction == SPI_DIRECTION_FULLDUPLEX))
+        {
+            if (SPI_InitStruct->SPI_WrapModeEn)
+            {
+                SPIx->SPI_WRAP_CTRL = 0;
+
+                /* Wrapper mode enable */
+                SPI_WRAP_CTRL_TypeDef spi_0x200 = {.d32 = SPIx->SPI_WRAP_CTRL};
+                SPI_WRAP_TXFTLR_TypeDef spi_0x204 = {.d32 = SPIx->SPI_WRAP_TXFTLR};
+                spi_0x200.b.wrap_ctrl_mode = 1;
+                if (SPI_InitStruct->SPI_TXNDF > 0)
+                {
+                    spi_0x200.b.mst_tx_ndf = SPI_InitStruct->SPI_TXNDF - 1;
+                }
+                spi_0x204.b.tx_fifo_tl = SPI_InitStruct->SPI_WrapTxThresholdLevel;
+
+                SPIx->SPI_WRAP_CTRL = spi_0x200.d32;
+                SPIx->SPI_WRAP_TXFTLR = spi_0x204.d32;
+
+                if (SPI_InitStruct->SPI_WrapModeDMAEn)
+                {
+                    /* enable tx ndf dma */
+                    SPI_WRAP_DMACR_TypeDef spi_0x220 = {.d32 = SPIx->SPI_WRAP_DMACR};
+                    spi_0x220.b.tx_dma_en = 1;
+                    SPIx->SPI_WRAP_DMACR = spi_0x220.d32;
+                }
+
+                SPI_WRAP_DMATDLR_TypeDef spi_0x224 = {.d32 = SPIx->SPI_WRAP_DMATDLR};
+                spi_0x224.b.dma_tx_dl = SPI_InitStruct->SPI_WrapTxWaterlevel;
+                SPIx->SPI_WRAP_DMATDLR = spi_0x224.d32;
+            }
+        }
+
+        SPI_WRAP_CTRL_TypeDef spi_0x200 = {.d32 = SPIx->SPI_WRAP_CTRL};
+        spi_0x200.b.cs_inv_en = SPI_InitStruct->SPI_CSHighActiveEn;
+        SPIx->SPI_WRAP_CTRL = spi_0x200.d32;
+
+        SPI_WRAP_CS_DLY_TypeDef spi_0x22c = {.d32 = SPIx->SPI_WRAP_CS_DLY};
+        spi_0x22c.b.cs_clk_div_sel = SPI_InitStruct->SPI_WrapCSClockDiv;
+        spi_0x22c.b.cs_hold_dly = SPI_InitStruct->SPI_WrapCSHoldDlyCount;
+        spi_0x22c.b.cs_setup_dly = SPI_InitStruct->SPI_WrapCSSetupDlyCount;
+        SPIx->SPI_WRAP_CS_DLY = spi_0x22c.d32;
+#endif
+    }
+
+#if (SPI0_SUPPORT_MASTER_SLAVE == 0) && defined(SPI0_SLAVE)
+    /* Configure SPI Slave mode if select SPI0_SLAVE */
+    else if (SPIx == SPI0_SLAVE)
+    {
+#if (SPI_SLAVE_SUPPORT_APH_BRIDGE_FOR_HIGH_SPEED == 1)
+        SPI_ConfigAPHBridge(SPIx);
+#endif
+        /* Configure SPI slave mode parameters */
+        SPI_S_CTRL0_TypeDef spi_0x00 = {.d32 = SPIx->SPI_M_S_CTRL0};
+        spi_0x00.b.scph = SPI_InitStruct->SPI_CPHA;
+        spi_0x00.b.scpol = SPI_InitStruct->SPI_CPOL;
+        spi_0x00.b.dfs = SPI_InitStruct->SPI_DataSize;
+#if (SPI_SUPPORT_SWAP == 1)
+        spi_0x00.b.tx_byte_swap = SPI_InitStruct->SPI_SwapTxByteEn;
+        spi_0x00.b.tx_bit_swap = SPI_InitStruct->SPI_SwapTxBitEn;
+        spi_0x00.b.rx_byte_swap = SPI_InitStruct->SPI_SwapRxByteEn;
+        spi_0x00.b.rx_bit_swap = SPI_InitStruct->SPI_SwapRxBitEn;
+#endif
+
+        /* Enable slave output */
+        spi_0x00.b.slv_oe = 0;
+        SPIx->SPI_M_S_CTRL0 = spi_0x00.d32;
+    }
+#endif
+    /* Set Tx empty level */
+    SPI_TXFTLR_TypeDef spi_0x18 = {.d32 = SPIx->SPI_TXFTLR};
+    spi_0x18.b.tft = SPI_InitStruct->SPI_TxThresholdLevel;
+    SPIx->SPI_TXFTLR = spi_0x18.d32;
+
+    /*set Rx full level*/
+    SPI_RXFTLR_TypeDef spi_0x1c = {.d32 = SPIx->SPI_RXFTLR};
+    spi_0x1c.b.rft = SPI_InitStruct->SPI_RxThresholdLevel;
+
+    /* Config SPI dma mode */
+    SPI_DMACR_TypeDef spi_0x4c = {.d32 = SPIx->SPI_DMACR};
+    spi_0x4c.b.rdmae = SPI_InitStruct->SPI_RxDMAEn;
+    spi_0x4c.b.tdmae = SPI_InitStruct->SPI_TxDMAEn;
+    SPIx->SPI_DMACR = spi_0x4c.d32;
+
+    /* Config SPI waterlevel */
+    SPI_DMATDLR_TypeDef spi_0x50 = {.d32 = SPIx->SPI_DMATDLR};
+    SPI_DMARDLR_TypeDef spi_0x54 = {.d32 = SPIx->SPI_DMARDLR};
+    spi_0x50.b.dmatdl = SPI_InitStruct->SPI_TxWaterlevel;
+    spi_0x54.b.dmardl = SPI_InitStruct->SPI_RxWaterlevel;
+    SPIx->SPI_DMATDLR = spi_0x50.d32;
+
+    if (SPI_InitStruct->SPI_RxDMAEn)
+    {
+        /* DMA mode should config DMARDLR later if open AHB */
+        SPIx->SPI_RXFTLR = spi_0x1c.d32;
+        SPIx->SPI_DMARDLR = spi_0x54.d32;
+    }
+    else
+    {
+        /* CPU mode should config RXFTLR later if open AHB */
+        SPIx->SPI_DMARDLR = spi_0x54.d32;
+        SPIx->SPI_RXFTLR = spi_0x1c.d32;
+    }
+
+    /* Mask SPI interrupt in REG_DW_SSI_IMR */
+    SPIx->SPI_M_S_IMR = 0;
+}
+
+/**
+  * \brief  Fills each SPI_InitStruct member with its default value.
+  * \param  SPI_InitStruct : Pointer to a SPI_InitTypeDef structure which will be initialized.
+  * \return None
+  */
+void SPI_StructInit(SPI_InitTypeDef *SPI_InitStruct)
+{
+    /* TX and RX Mode */
+    SPI_InitStruct->SPI_Direction         = SPI_DIRECTION_FULLDUPLEX;
+    /* Number of data to read in RX/EEPROM Mode */
+    SPI_InitStruct->SPI_RXNDF              = 1;
+    /* 8-bit serial data transfer */
+    SPI_InitStruct->SPI_DataSize          = SPI_DATA_SIZE_8b;
+    /* Inactive state of clock is high */
+    SPI_InitStruct->SPI_CPOL              = SPI_CPOL_HIGH;
+    /* Serial clock toggles in first of first data bit */
+    SPI_InitStruct->SPI_CPHA              = SPI_CPHA_2EDGE;
+#if (SPI_FIXED_FRAME_FORMAT == 0)
+    /* Motorola format */
+    SPI_InitStruct->SPI_FrameFormat       = SPI_FRAME_MOTOROLA;
+#endif
+    /* Speed = SPI Clock source/ SPI_ClkDIV*/
+    SPI_InitStruct->SPI_BaudRatePrescaler = 128;
+#if (SPI0_SUPPORT_MASTER_SLAVE == 1)
+    SPI_InitStruct->SPI_Mode = SPI_MODE_MASTER;
+#endif
+#if (SPI_SUPPORT_SWAP == 1)
+    /* Reverse the rx bit or not */
+    SPI_InitStruct->SPI_SwapTxBitEn       = DISABLE;
+    SPI_InitStruct->SPI_SwapRxBitEn       = DISABLE;
+    SPI_InitStruct->SPI_SwapTxByteEn      = DISABLE;
+    SPI_InitStruct->SPI_SwapRxByteEn      = DISABLE;
+#endif
+    /* Toggle CS line or not */
+    SPI_InitStruct->SPI_ToggleEn          = DISABLE;
+#if (SPI_SUPPORT_WRAP_MODE == 1)
+    /* Number of data to read in TX/FullDuplex Mode */
+    SPI_InitStruct->SPI_TXNDF             = 1;
+    /* Enable CS high active or not */
+    SPI_InitStruct->SPI_CSHighActiveEn    = DISABLE;
+    /* Disable tx ndf */
+    SPI_InitStruct->SPI_WrapModeEn     = DISABLE;
+    /* Disable dma */
+    SPI_InitStruct->SPI_WrapModeDMAEn  = DISABLE;
+    /* Wrapper Tx fifo depth: SPI_WRAPPER_TX_FIFO_SIZE bytes */
+    SPI_InitStruct->SPI_WrapTxThresholdLevel  = 1;
+    /* SPI Tx waterlevel, should be less than fifo threshold.
+       The best value is SPI FIFO Depth - GDMA Msize */
+    SPI_InitStruct->SPI_WrapTxWaterlevel   =  SPI_TX_FIFO_SIZE - 1;
+    /* Set CS clock divider */
+    SPI_InitStruct->SPI_WrapCSClockDiv = SPI_WRAP_CS_CLOCK_DIV_1;
+    /* Set CS hold delay count */
+    SPI_InitStruct->SPI_WrapCSHoldDlyCount = 0;
+    /* Set CS setup delay count */
+    SPI_InitStruct->SPI_WrapCSSetupDlyCount = 0;
+
+#endif
+    /* Tx fifo depth: SPI_TX_FIFO_SIZE bytes */
+    SPI_InitStruct->SPI_TxThresholdLevel  = 1;
+    /* Rx fifo depth: SPI_RX_FIFO_SIZE bytes */
+    SPI_InitStruct->SPI_RxThresholdLevel  = 0;
+    /* Disable dma */
+    SPI_InitStruct->SPI_TxDMAEn           = DISABLE;
+    SPI_InitStruct->SPI_RxDMAEn           = DISABLE;
+    /* SPI Tx waterlevel, should be less than fifo threshold.
+       The best value is SPI FIFO Depth - DMA Msize */
+    SPI_InitStruct->SPI_TxWaterlevel      = SPI_TX_FIFO_SIZE - 1;
+    /* SPI Rx waterlevel, should be less than fifo threshold.
+       The best value is DMA Msize */
+    SPI_InitStruct->SPI_RxWaterlevel      = 1;
+}
+
+/**
+  * \brief  Enables or disables the specified SPI peripheral.
+  * \param  SPIx: Select the SPI peripheral. \ref SPI_Declaration
+  * \param  NewState: New state of the SPIx peripheral.
+  *         This parameter can be: ENABLE or DISABLE.
+  * \return None
+  */
+void SPI_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_SPI_ALL_PERIPH(SPIx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    SPI_SPIENR_TypeDef spi_0x08 = {.d32 = SPIx->SPI_SPIENR};
+    spi_0x08.b.spi_en = NewState;
+    SPIx->SPI_SPIENR = spi_0x08.d32;
+}
+
+/**
+  * \brief  Transmits a number of bytes through the SPIx peripheral.
+  * \param  SPIx: Select the SPI peripheral. \ref SPI_Declaration
+  * \param  pBuf : Bytes to be transmitted.
+  * \param  len : Byte length to be transmitted.
+  * \return None
+  */
+void SPI_SendBuffer(SPI_TypeDef *SPIx, uint8_t *pBuf, uint16_t len)
+{
+    uint16_t i = 0;
+
+    /* Check the parameters */
+    assert_param(IS_SPI_ALL_PERIPH(SPIx));
+
+#if (SPI_SUPPORT_WRAP_MODE == 1)
+    SPI_WRAP_CTRL_TypeDef spi_0x200 = {.d32 = SPIx->SPI_WRAP_CTRL};
+    if (spi_0x200.b.wrap_ctrl_mode && SPI_NOT_SLAVE(SPIx))
+    {
+        for (i = 0; i < len; i++)
+        {
+            /* Read TFNF bit status in SPI_SR register: SET is Tx FIFO is not full */
+            while (!(SPIx->SPI_WRAP_SR & SPI_FLAG_TFNF));
+            SPIx->SPI_DR[0] = (*pBuf++);
+        }
+        return;
+    }
+#endif
+    for (i = 0; i < len; i++)
+    {
+        /* Read TFNF bit status in SPI_SR register: SET is Tx FIFO is not full */
+        while (SPI_NOT_SLAVE(SPIx) && !(SPIx->SPI_M_S_SR & SPI_FLAG_TFNF));
+        SPIx->SPI_DR[0] = (*pBuf++);
+    }
+}
+
+/**
+  * \brief  Transmits a number of bytes through the SPIx peripheral without polling.
+  * \param  SPIx: Select the SPI peripheral \ref SPI_Declaration.
+  * \param  pBuf : Bytes to be transmitted.
+  * \param  len : Byte length to be transmitted.
+  */
+void SPI_SendBufferDirect(SPI_TypeDef *SPIx, uint8_t *pBuf, uint16_t len)
+{
+    uint16_t i = 0;
+
+    /* Check the parameters */
+    assert_param(IS_SPI_ALL_PERIPH(SPIx));
+
+#if (SPI_SUPPORT_WRAP_MODE == 1)
+    SPI_WRAP_CTRL_TypeDef spi_0x200 = {.d32 = SPIx->SPI_WRAP_CTRL};
+    if (spi_0x200.b.wrap_ctrl_mode && SPI_NOT_SLAVE(SPIx))
+    {
+        for (i = 0; i < len; i++)
+        {
+            SPIx->SPI_DR[0] = (*pBuf++);
+        }
+        return;
+    }
+#endif
+    for (i = 0; i < len; i++)
+    {
+        SPIx->SPI_DR[0] = (*pBuf++);
+    }
+}
+
+/**
+  * \brief  Transmits a number of halfWords through the SPIx peripheral.
+  * \param  SPIx: Select the SPI peripheral. \ref SPI_Declaration
+  * \param  pBuf : Halfwords to be transmitted.
+  * \param  len: Halfword length to be transmitted.
+  * \return None
+  */
+void SPI_SendHalfWord(SPI_TypeDef *SPIx, uint16_t *pBuf, uint16_t len)
+{
+    uint16_t i = 0;
+
+    /* Check the parameters */
+    assert_param(IS_SPI_ALL_PERIPH(SPIx));
+
+#if (SPI_SUPPORT_WRAP_MODE == 1)
+    SPI_WRAP_CTRL_TypeDef spi_0x200 = {.d32 = SPIx->SPI_WRAP_CTRL};
+    if (spi_0x200.b.wrap_ctrl_mode && SPI_NOT_SLAVE(SPIx))
+    {
+        for (i = 0; i < len; i++)
+        {
+            /* Read TFNF bit status in SPI_SR register: SET is Tx FIFO is not full */
+            while (!(SPIx->SPI_WRAP_SR & SPI_FLAG_TFNF));
+            SPIx->SPI_DR[0] = (*pBuf++);
+        }
+        return;
+    }
+#endif
+    for (i = 0; i < len; i++)
+    {
+        /* Read TFNF bit status in SPI_SR register: SET is Tx FIFO is not full */
+        while (SPI_NOT_SLAVE(SPIx) && !(SPIx->SPI_M_S_SR & SPI_FLAG_TFNF));
+        SPIx->SPI_DR[0] = (*pBuf++);
+    }
+}
+
+/**
+  * \brief  Transmits a number of halfWords through the SPIx peripheral without polling.
+  * \param  SPIx: Select the SPI peripheral \ref SPI_Declaration.
+  * \param  pBuf : Halfwords to be transmitted.
+  * \param  len: Halfword length to be transmitted.
+  */
+void SPI_SendHalfWordDirect(SPI_TypeDef *SPIx, uint16_t *pBuf, uint16_t len)
+{
+    uint16_t i = 0;
+
+    /* Check the parameters */
+    assert_param(IS_SPI_ALL_PERIPH(SPIx));
+
+#if (SPI_SUPPORT_WRAP_MODE == 1)
+    SPI_WRAP_CTRL_TypeDef spi_0x200 = {.d32 = SPIx->SPI_WRAP_CTRL};
+    if (spi_0x200.b.wrap_ctrl_mode && SPI_NOT_SLAVE(SPIx))
+    {
+        for (i = 0; i < len; i++)
+        {
+            SPIx->SPI_DR[0] = (*pBuf++);
+        }
+        return;
+    }
+#endif
+    for (i = 0; i < len; i++)
+    {
+        SPIx->SPI_DR[0] = (*pBuf++);
+    }
+}
+
+/**
+  * \brief  Transmits a number of words through the SPIx peripheral.
+  * \param  SPIx: Select the SPI peripheral. \ref SPI_Declaration
+  * \param  pBuf : Words to be transmitted.
+  * \param  len: Word length to be transmitted.
+  * \return None
+  */
+void SPI_SendWord(SPI_TypeDef *SPIx, uint32_t *pBuf, uint16_t len)
+{
+    uint16_t i = 0;
+
+    /* Check the parameters */
+    assert_param(IS_SPI_ALL_PERIPH(SPIx));
+
+#if (SPI_SUPPORT_WRAP_MODE == 1)
+    SPI_WRAP_CTRL_TypeDef spi_0x200 = {.d32 = SPIx->SPI_WRAP_CTRL};
+    if (spi_0x200.b.wrap_ctrl_mode && SPI_NOT_SLAVE(SPIx))
+    {
+        for (i = 0; i < len; i++)
+        {
+            /* Read TFNF bit status in SPI_SR register: SET is Tx FIFO is not full */
+            while (!(SPIx->SPI_WRAP_SR & SPI_FLAG_TFNF));
+            SPIx->SPI_DR[0] = (*pBuf++);
+        }
+        return;
+    }
+#endif
+    for (i = 0; i < len; i++)
+    {
+        /* Read TFNF bit status in SPI_SR register: SET is Tx FIFO is not full */
+        while (SPI_NOT_SLAVE(SPIx) && !(SPIx->SPI_M_S_SR & SPI_FLAG_TFNF));
+        SPIx->SPI_DR[0] = (*pBuf++);
+    }
+}
+
+/**
+  * \brief  Transmits a number of words through the SPIx peripheral without polling.
+  * \param  SPIx: Select the SPI peripheral \ref SPI_Declaration.
+  * \param  pBuf : Words to be transmitted.
+  * \param  len: Word length to be transmitted.
+  */
+void SPI_SendWordDirect(SPI_TypeDef *SPIx, uint32_t *pBuf, uint16_t len)
+{
+    uint16_t i = 0;
+
+    /* Check the parameters */
+    assert_param(IS_SPI_ALL_PERIPH(SPIx));
+
+#if (SPI_SUPPORT_WRAP_MODE == 1)
+    SPI_WRAP_CTRL_TypeDef spi_0x200 = {.d32 = SPIx->SPI_WRAP_CTRL};
+    if (spi_0x200.b.wrap_ctrl_mode && SPI_NOT_SLAVE(SPIx))
+    {
+        for (i = 0; i < len; i++)
+        {
+            SPIx->SPI_DR[0] = (*pBuf++);
+        }
+        return;
+    }
+#endif
+    for (i = 0; i < len; i++)
+    {
+        SPIx->SPI_DR[0] = (*pBuf++);
+    }
+}
+
+/**
+  * \brief  Clear the specified SPI interrupt.
+  * \param  SPIx: Select the SPI peripheral. \ref SPI_Declaration
+  * \param  SPI_IT: Specifies the SPI interrupt to clear.
+  *         This parameter can be one of the following values:
+  *         \arg SPI_INT_TXO: Transmit FIFO Overflow Interrupt .
+  *         \arg SPI_INT_RXO: Receive FIFO Overflow Interrupt.
+  *         \arg SPI_INT_RXU: Receive FIFO Underflow Interrupt.
+  *         \arg SPI_INT_MST: Multi-Master Contention Interrupt.
+  *         \arg SPI_INT_FAE: TX Frame Alignment Interrupt.
+  *         \arg SPI_INT_TUF: Transmit FIFO Underflow Interrupt.
+  *         \arg SPI_INT_RIG: Rising edge detect Interrupt.
+  *         \arg SPI_INT_WRAP_TXE: TX NDF mode FIFO Transmit FIFO Empty Interrupt.
+  *         \arg SPI_INT_WRAP_TXO: TX NDF mode FIFO Overflow Interrupt.
+  *         \arg SPI_INT_WRAP_TXD: TX NDF mode transmit done Interrupt.
+  * \return None.
+  */
+void SPI_ClearINTPendingBit(SPI_TypeDef *SPIx, uint16_t SPI_IT)
+{
+    /* Check the parameters */
+    assert_param(IS_SPI_ALL_PERIPH(SPIx));
+    assert_param(IS_SPI_CONFIG_IT(SPI_IT));
+
+    if (SPI_IT & SPI_INT_TXO)
+    {
+        (void)SPIx->SPI_TXOICR;
+    }
+
+    if (SPI_IT & SPI_INT_RXO)
+    {
+        (void)SPIx->SPI_RXOICR;
+    }
+
+    if (SPI_IT & SPI_INT_RXU)
+    {
+        (void)SPIx->SPI_RXUICR;
+    }
+
+    if (SPI_IT & SPI_INT_FAE)
+    {
+        (void)SPIx->SPI_M_S_MSTICR_FAEICR;
+    }
+
+    if (SPI_IT & SPI_INT_TUF)
+    {
+        (void)SPIx->SPI_M_S_IDR_TXUICR;
+    }
+
+    if (SPI_IT & SPI_INT_RIG)
+    {
+        (void)SPIx->SPI_M_S_VERSION_ID_SSRICR;
+    }
+
+#if (SPI_SUPPORT_WRAP_MODE == 1)
+    if (SPI_IT & (SPI_INT_WRAP_TXD | SPI_INT_WRAP_TXO))
+    {
+        (void)SPIx->SPI_WRAP_ICR;
+    }
+#endif
+}
+
+/**
+  * \brief  Transmits a data through the SPIx peripheral.
+  * \param  SPIx: Select the SPI peripheral. \ref SPI_Declaration
+  * \param  Data: Data to be transmitted.
+  * \return None.
+  */
+void SPI_SendData(SPI_TypeDef *SPIx, uint32_t Data)
+{
+    /* Check the parameters */
+    assert_param(IS_SPI_ALL_PERIPH(SPIx));
+
+#if (SPI_SUPPORT_WRAP_MODE == 1)
+    SPI_WRAP_CTRL_TypeDef spi_0x200 = {.d32 = SPIx->SPI_WRAP_CTRL};
+    if (spi_0x200.b.wrap_ctrl_mode && SPI_NOT_SLAVE(SPIx))
+    {
+        while (!(SPIx->SPI_WRAP_SR & SPI_FLAG_TFNF));
+        SPIx->SPI_DR[0] = Data;
+        return;
+    }
+#endif
+    while (SPI_NOT_SLAVE(SPIx) && !(SPIx->SPI_M_S_SR & SPI_FLAG_TFNF));
+    SPIx->SPI_DR[0] = Data;
+}
+
+/**
+  * \brief  Received data by the SPI peripheral.
+  * \param  SPIx: Select the SPI peripheral. \ref SPI_Declaration
+  * \return The most recent received data.
+  */
+uint32_t SPI_ReceiveData(SPI_TypeDef *SPIx)
+{
+    /* Check the parameters */
+    assert_param(IS_SPI_ALL_PERIPH(SPIx));
+
+    return (uint32_t)SPIx->SPI_DR[0];
+}
+
+/**
+  * \brief  Get data length in Tx FIFO through the SPIx peripheral.
+  * \param  SPIx: Select the SPI peripheral. \ref SPI_Declaration
+  * \return Data length in Tx FIFO.
+  */
+uint8_t SPI_GetTxFIFOLen(SPI_TypeDef *SPIx)
+{
+    /* Check the parameters */
+    assert_param(IS_SPI_ALL_PERIPH(SPIx));
+
+    SPI_TXFLR_TypeDef spi_0x20 = {.d32 = SPIx->SPI_TXFLR};
+    return spi_0x20.b.txtfl;
+}
+
+/**
+  * \brief  Get data length in Rx FIFO through the SPIx peripheral.
+  * \param  SPIx: Select the SPI peripheral. \ref SPI_Declaration
+  * \return Data length in Rx FIFO.
+  */
+uint8_t SPI_GetRxFIFOLen(SPI_TypeDef *SPIx)
+{
+    /* Check the parameters */
+    assert_param(IS_SPI_ALL_PERIPH(SPIx));
+
+    SPI_RXFLR_TypeDef spi_0x24 = {.d32 = SPIx->SPI_RXFLR};
+    return spi_0x24.b.rxtfl;
+}
+
+/**
+  * \brief  Change SPI direction mode.
+  * \param  SPIx: Select the SPI peripheral. \ref SPI_Declaration
+  * \param  dir: Value of direction mode.
+  * \return None.
+  */
+void SPI_SetDirection(SPI_TypeDef *SPIx, uint16_t dir)
+{
+    /* Check the parameters */
+    assert_param(IS_SPI_ALL_PERIPH(SPIx));
+    assert_param(IS_SPI_DIRECTION_MODE(dir));
+
+    /* Disable the selected SPI peripheral */
+    SPI_SPIENR_TypeDef spi_0x08 = {.d32 = SPIx->SPI_SPIENR};
+    spi_0x08.b.spi_en = 0;
+    SPIx->SPI_SPIENR = spi_0x08.d32;
+
+    /* Change SPI direction mode */
+    SPI_M_CTRL0_TypeDef spi_0x00 = {.d32 = SPIx->SPI_M_S_CTRL0};
+    spi_0x00.b.tmod = dir;
+    SPIx->SPI_M_S_CTRL0 = spi_0x00.d32;
+
+    /* Enable the selected SPI peripheral */
+    spi_0x08.b.spi_en = 1;
+    SPIx->SPI_SPIENR = spi_0x08.d32;
+}
+
+/**
+  * \brief  Set read Data length only in EEPROM mode through the SPIx peripheral,which
+            enables you to receive up to 64 KB of data in a continuous transfer.
+  * \param  SPIx: Select the SPI peripheral. \ref SPI_Declaration
+  * \param  len: Length of read data which can be 1 to 65536.
+  * \return None.
+  */
+void SPI_SetReadLen(SPI_TypeDef *SPIx, uint16_t len)
+{
+    /* Check the parameters */
+    assert_param(IS_SPI_ALL_PERIPH(SPIx));
+
+    /* Disable the selected SPI peripheral */
+    SPI_SPIENR_TypeDef spi_0x08 = {.d32 = SPIx->SPI_SPIENR};
+    spi_0x08.b.spi_en = 0;
+    SPIx->SPI_SPIENR = spi_0x08.d32;
+
+    /* Set read length in SPI EEPROM or RX only mode */
+    SPI_M_CTRL1_TypeDef spi_0x04 = {.d32 = SPIx->SPI_M_CTRL1};
+    spi_0x04.b.ndf = len - 1;
+    SPIx->SPI_M_CTRL1 = spi_0x04.d32;
+
+    /* Enable the selected SPI peripheral */
+    spi_0x08.b.spi_en = 1;
+    SPIx->SPI_SPIENR = spi_0x08.d32;
+}
+
+/**
+  * \brief  Set cs number through the SPIx peripheral.
+  * \param  SPIx: Select the SPI peripheral. \ref SPI_Declaration
+  * \param  number: Number can be 0 to 2.
+  * \return None.
+ */
+void SPI_SetCSNumber(SPI_TypeDef *SPIx, uint8_t number)
+{
+    /* Check the parameters */
+    assert_param(IS_SPI_ALL_PERIPH(SPIx));
+
+    /* set cs number */
+    SPIx->SPI_M_SER = BIT(number);
+}
+
+/**
+  * \brief  Check whether the specified SPI interrupt is set.
+  * \param  SPIx: Select the SPI peripheral. \ref SPI_Declaration
+  * \param  SPI_IT: Specifies the SPI interrupt to check.
+  *         This parameter can be one of the following values:
+  *         \arg SPI_INT_MST: Multi-Master Contention Interrupt.
+  *         \arg SPI_INT_FAE: TX Frame Alignment Interrupt.
+  *         \arg SPI_INT_RXF: Receive FIFO Full Interrupt.
+  *         \arg SPI_INT_RXO: Receive FIFO Overflow Interrupt.
+  *         \arg SPI_INT_RXU: Receive FIFO Underflow Interrupt.
+  *         \arg SPI_INT_TXO: Transmit FIFO Overflow Interrupt .
+  *         \arg SPI_INT_TXE: Transmit FIFO Empty Interrupt.
+  *         \arg SPI_INT_WRAP_TXD: TX NDF mode transmit done Interrupt.
+  * \return The new state of SPI_IT (SET or RESET).
+  */
+ITStatus SPI_GetINTStatus(SPI_TypeDef *SPIx, uint32_t SPI_IT)
+{
+    /* Check the parameters */
+    assert_param(IS_SPI_ALL_PERIPH(SPIx));
+    assert_param(IS_SPI_CONFIG_IT(SPI_IT));
+
+    ITStatus bit_status = RESET;
+
+#if (SPI_SUPPORT_WRAP_MODE == 1)
+    SPI_WRAP_CTRL_TypeDef spi_0x200 = {.d32 = SPIx->SPI_WRAP_CTRL};
+    if (SPI_IT & (SPI_INT_WRAP_TXE | SPI_INT_WRAP_TXO | SPI_INT_WRAP_TXD))
+    {
+        if (spi_0x200.b.wrap_ctrl_mode)
+        {
+            if (SPIx->SPI_WRAP_ISR & (SPI_IT >> 8))
+            {
+                bit_status = SET;
+            }
+        }
+        return  bit_status;
+    }
+#endif
+    /* Check the status of the specified SPI flag */
+    if ((SPIx->SPI_M_S_ISR & SPI_IT) != (uint32_t)RESET)
+    {
+        bit_status = SET;
+    }
+
+    /* Return the SPI_IT status */
+    return  bit_status;
+}
+
+/**
+  * \brief  Enables or disables the specified SPI interrupt source.
+  * \param  SPIx: Select the SPI peripheral. \ref SPI_Declaration
+  * \param  SPI_IT: Specifies the SPI interrupt source to be enabled or disabled.
+  *         This parameter can be one of the following values:
+  *         \arg SPI_INT_TXE: Transmit FIFO empty interrupt.
+  *         \arg SPI_INT_TXO: Transmit FIFO overflow interrupt.
+  *         \arg SPI_INT_RXU: Receive FIFO underflow interrupt.
+  *         \arg SPI_INT_RXO: Receive FIFO overflow interrupt.
+  *         \arg SPI_INT_RXF: Receive FIFO full interrupt.
+  *         \arg SPI_INT_MST: Multi-Master Contention Interrupt.
+  *         \arg SPI_INT_FAE: TX Frame Alignment interrupt.
+  *         \arg SPI_INT_TUF: Transmit FIFO underflow interrupt.
+  *         \arg SPI_INT_RIG: Rising edge detect interrupt.
+  *         \arg SPI_INT_WRAP_TXD: TX NDF mode transmit done Interrupt.
+  * \param  NewState: New state of the specified SPI interrupt source.
+  *         This parameter can be: ENABLE or DISABLE.
+  * \return None
+  */
+void SPI_INTConfig(SPI_TypeDef *SPIx, uint16_t SPI_IT, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_SPI_ALL_PERIPH(SPIx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+    assert_param(IS_SPI_CONFIG_IT(SPI_IT));
+
+#if (SPI_SUPPORT_WRAP_MODE == 1)
+    SPI_WRAP_CTRL_TypeDef spi_0x200 = {.d32 = SPIx->SPI_WRAP_CTRL};
+    if (SPI_IT & (SPI_INT_WRAP_TXE | SPI_INT_WRAP_TXO | SPI_INT_WRAP_TXD))
+    {
+        if (spi_0x200.b.wrap_ctrl_mode)
+        {
+            if (NewState != DISABLE)
+            {
+                SPIx->SPI_WRAP_IMR |= (SPI_IT >> 8);
+            }
+            else
+            {
+                SPIx->SPI_WRAP_IMR &= ~(SPI_IT >> 8);
+            }
+        }
+    }
+#endif
+    if (NewState != DISABLE)
+    {
+        SPIx->SPI_M_S_IMR |= (SPI_IT & 0xff);
+    }
+    else
+    {
+        SPIx->SPI_M_S_IMR &= ~(SPI_IT & 0xff);
+    }
+}
+
+
+/**
+ * \brief  Check whether the specified SPI flag is set.
+ *
+ * \param  SPIx: Select the SPI peripheral. \ref SPI_Declaration
+ * \param  SPI_FLAG: Specifies the SPI flag to check.
+ *         This parameter can be one of the following values:
+ *         \arg SPI_FLAG_DCOL: Data Collision Error flag.Set if it is actively transmitting in master mode when another master selects this device as a slave.
+ *         \arg SPI_FLAG_TXE: Transmission error flag.Set if the transmit FIFO is empty when a transfer is started in slave mode.
+ *         \arg SPI_FLAG_RFF: Receive FIFO full flag. Set if the receive FIFO is completely full.
+ *         \arg SPI_FLAG_RFNE: Receive FIFO Not Empty flag.Set if receive FIFO is not empty.
+ *         \arg SPI_FLAG_TFE: Transmit FIFO Empty flag.Set if transmit FIFO is empty.
+ *         \arg SPI_FLAG_TFNF: Transmit FIFO Not Full flag.Set if transmit FIFO is not full.
+ *         \arg SPI_FLAG_BUSY: SPI Busy flag.Set if it is actively transferring data.reset if it is idle or disabled.
+ *
+ * \return The new state of SPI_FLAG (SET or RESET).
+ */
+FlagStatus SPI_GetFlagState(SPI_TypeDef *SPIx, uint16_t SPI_FLAG)
+{
+    /* Check the parameters */
+    assert_param(IS_SPI_ALL_PERIPH(SPIx));
+    assert_param(IS_SPI_GET_FLAG(SPI_FLAG));
+
+    FlagStatus bitstatus = RESET;
+
+#if (SPI_SUPPORT_WRAP_MODE == 1)
+    SPI_WRAP_CTRL_TypeDef spi_0x200 = {.d32 = SPIx->SPI_WRAP_CTRL};
+    if ((SPI_FLAG & (SPI_FLAG_WRAP_CS_EN | SPI_FLAG_WRAP_TFNF |
+                     SPI_FLAG_WRAP_TFE)))
+    {
+        if ((spi_0x200.b.wrap_ctrl_mode))
+        {
+            if (SPIx->SPI_WRAP_SR & (SPI_FLAG >> 8))
+            {
+                bitstatus = SET;
+            }
+        }
+        return  bitstatus;
+    }
+#endif
+    /* Check the status of the specified SPI flag */
+    if ((SPIx->SPI_M_S_SR & SPI_FLAG) != (uint8_t)RESET)
+    {
+        /* SPI_FLAG is set */
+        bitstatus = SET;
+    }
+
+    /* Return the SPI_FLAG status */
+    return  bitstatus;
+}
+
+/**
+  * \brief  Enables or disables the SPIx DMA interface.
+  * \param  SPIx: Select the SPI peripheral. \ref SPI_Declaration
+  * \param  SPI_DMAReq: Specifies the SPI DMA transfer request to be enabled or disabled.
+  *         This parameter can be one of the following values:
+  *         \arg SPI_DMAReq_Tx: Tx buffer DMA transfer request.
+  *         \arg SPI_DMAReq_Rx: Rx buffer DMA transfer request.
+  * \param  NewState: New state of the selected SPI DMA transfer request.
+  *         This parameter can be: ENABLE or DISABLE.
+  * \return None.
+  */
+void SPI_DMACmd(SPI_TypeDef *SPIx, SPIDMARequests_TypeDef SPI_DMAReq,
+                FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_SPI_ALL_PERIPH(SPIx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+    assert_param(IS_SPI_DMAREQ(SPI_DMAReq));
+
+    if ((SPI_DMAReq == SPI_DMA_REQ_TX) || (SPI_DMAReq == SPI_DMA_REQ_RX))
+    {
+        if (NewState != DISABLE)
+        {
+            /* Enable the selected SPI DMA request */
+            SPIx->SPI_DMACR |= SPI_DMAReq;
+        }
+        else
+        {
+            /* Disable the selected SPI DMA request */
+            SPIx->SPI_DMACR &= (uint16_t)~(SPI_DMAReq);
+        }
+    }
+#if (SPI_SUPPORT_WRAP_MODE == 1)
+    else
+    {
+        SPI_WRAP_CTRL_TypeDef spi_0x200 = {.d32 = SPIx->SPI_WRAP_CTRL};
+        if (spi_0x200.b.wrap_ctrl_mode && SPI_NOT_SLAVE(SPIx))
+        {
+            /* enable tx ndf dma */
+            SPI_WRAP_DMACR_TypeDef spi_0x220 = {.d32 = SPIx->SPI_WRAP_DMACR};
+            spi_0x220.b.tx_dma_en = NewState;
+            SPIx->SPI_WRAP_DMACR = spi_0x220.d32;
+        }
+    }
+#endif
+}
+
+/**
+  * \brief  Change SPI speed daynamically.
+  * \param  SPIx: Select the SPI peripheral. \ref SPI_Declaration
+  * \param  precalser: Value of prescaler.
+  *         This parameter can be one of the following values:
+  *         \arg  SPI_BaudRatePrescaler_2
+  *         \arg  SPI_BaudRatePrescaler_4
+  *         \arg  SPI_BaudRatePrescaler_6
+  *         \arg  SPI_BaudRatePrescaler_8
+  *         \arg  SPI_BaudRatePrescaler_10
+  *         \arg  SPI_BaudRatePrescaler_12
+  *         \arg  SPI_BaudRatePrescaler_14
+  *         \arg  SPI_BaudRatePrescaler_16
+  *         \arg  SPI_BaudRatePrescaler_32
+  *         \arg  SPI_BaudRatePrescaler_64
+  *         \arg  SPI_BaudRatePrescaler_128
+  *         \arg  SPI_BaudRatePrescaler_256
+  * \return None.
+  */
+void SPI_SetPrescaler(SPI_TypeDef *SPIx, uint32_t prescaler)
+{
+    /* Disable the selected SPI peripheral */
+    SPI_SPIENR_TypeDef spi_0x08 = {.d32 = SPIx->SPI_SPIENR};
+    spi_0x08.b.spi_en = 0;
+    SPIx->SPI_SPIENR = spi_0x08.d32;
+
+    /* Change SPI speed */
+    SPI_M_BAUDR_TypeDef spi_0x14 = {.d32 = SPIx->SPI_M_BAUDR};
+    spi_0x14.b.sckdv = prescaler & 0xFFFF;
+    SPIx->SPI_M_BAUDR = spi_0x14.d32;
+
+    /* Enable the selected SPI peripheral */
+    spi_0x08.b.spi_en = 1;
+    SPIx->SPI_SPIENR = spi_0x08.d32;
+}
+
+/**
+  * \brief  Set SPI Rx sample delay.
+  * \param  SPIx: Select the SPI peripheral. \ref SPI_Declaration
+  * \param  delay: This parameter can be 0 to 255.
+  * \return None.
+  */
+void SPI_SetRxSampleDly(SPI_TypeDef *SPIx, uint32_t delay)
+{
+    /* Disable the selected SPI peripheral */
+    SPI_SPIENR_TypeDef spi_0x08 = {.d32 = SPIx->SPI_SPIENR};
+    spi_0x08.b.spi_en = 0;
+    SPIx->SPI_SPIENR = spi_0x08.d32;
+
+    /* Set SPI Rx sample delay */
+    SPI_M_RSDR_TypeDef spi_0xf0 = {.d32 = SPIx->SPI_M_RSDR};
+    spi_0xf0.b.rsd = delay & 0xFF;
+    SPIx->SPI_M_RSDR = spi_0xf0.d32;
+
+    /* Enable the selected SPI peripheral */
+    spi_0x08.b.spi_en = 1;
+    SPIx->SPI_SPIENR = spi_0x08.d32;
+}
+
+#if (SPI_SUPPORT_WRAP_MODE == 1)
+
+/**
+  * \brief  Enables or disables the specified SPI wrap mode start transfer.
+  * \param  SPIx: Select the SPI peripheral. \ref SPI_Declaration
+  * \param  NewState: new state of the SPIx peripheral.
+  *         This parameter can be: ENABLE or DISABLE.
+  * \return None
+  */
+void SPI_WrapModeStartTx(SPI_TypeDef *SPIx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_SPI_ALL_PERIPH(SPIx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    SPI_WRAP_CTRL_TypeDef spi_0x200 = {.d32 = SPIx->SPI_WRAP_CTRL};
+    spi_0x200.b.mst_tx_fifo_en = NewState;
+    SPIx->SPI_WRAP_CTRL = spi_0x200.d32;
+}
+
+/**
+  * \brief  Whether inverse CS active polarity.
+  * \param  SPIx: Select the SPI peripheral. \ref SPI_Declaration
+  * \param  NewState: new state of the SPIx peripheral.
+  *         This parameter can be one of the following values:
+  *         \arg  ENABLE: Inverse CS active polarity, which means CS is low active.
+  *         \arg  DISABLE: Not inverse CS active polarity, which means CS is high active.
+  * \return None
+  */
+void SPI_InverseCSActivePolarity(SPI_TypeDef *SPIx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_SPI_ALL_PERIPH(SPIx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    SPI_WRAP_CTRL_TypeDef spi_0x200 = {.d32 = SPIx->SPI_WRAP_CTRL};
+    spi_0x200.b.cs_inv_en = NewState;
+    SPIx->SPI_WRAP_CTRL = spi_0x200.d32;
+}
+
+/**
+  * \brief  Whether drive MOSI low in idle state.
+  * \param  SPIx: Select the SPI peripheral. \ref SPI_Declaration
+  * \param  NewState: new state of the SPIx peripheral.
+  *         This parameter can be one of the following values:
+  *         \arg  ENABLE: Drive MOSI low in idle state.
+  *         \arg  DISABLE: Not drive MOSI low in idle state, which means MOSI is Hi-Z in idle state.
+  * \return None
+  */
+void SPI_DriveMOSILow(SPI_TypeDef *SPIx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_SPI_ALL_PERIPH(SPIx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    SPI_WRAP_CTRL_TypeDef spi_0x200 = {.d32 = SPIx->SPI_WRAP_CTRL};
+    spi_0x200.b.mosi_drv_low_en = NewState;
+    SPIx->SPI_WRAP_CTRL = spi_0x200.d32;
+}
+
+/**
+  * \brief  Whether enable MOSI pull in idle state.
+  * \param  SPIx: Select the SPI peripheral. \ref SPI_Declaration
+  * \param  NewState: new state of the SPIx peripheral.
+  *         This parameter can be one of the following values:
+  *         \arg  ENABLE: MOSI is pull down in idle state.
+  *         \arg  DISABLE: MOSI is pull none in idle state.
+  * \return  None
+  */
+#if (SPI_REMOVE_Pull_MOSI_En == 0)
+void SPI_PullMOSIEn(SPI_TypeDef *SPIx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_SPI_ALL_PERIPH(SPIx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    SPI_WRAP_CTRL_TypeDef spi_0x200 = {.d32 = SPIx->SPI_WRAP_CTRL};
+    spi_0x200.b.mosi_pull_en = NewState;
+    SPIx->SPI_WRAP_CTRL = spi_0x200.d32;
+}
+#endif
+
+void SPI_WrapModeSetTxNdf(SPI_TypeDef *SPIx, uint16_t tx_ndf)
+{
+    /* Check the parameters */
+    assert_param(IS_SPI_ALL_PERIPH(SPIx));
+
+    SPI_WRAP_CTRL_TypeDef spi_0x200 = {.d32 = SPIx->SPI_WRAP_CTRL};
+    spi_0x200.b.mst_tx_ndf = tx_ndf - 1;
+    SPIx->SPI_WRAP_CTRL = spi_0x200.d32;
+}
+
+void SPI_WrapModeResetTxFIFO(SPI_TypeDef *SPIx)
+{
+    /* Check the parameters */
+    assert_param(IS_SPI_ALL_PERIPH(SPIx));
+
+    SPI_WRAP_CTRL_TypeDef spi_0x200 = {.d32 = SPIx->SPI_WRAP_CTRL};
+    spi_0x200.b.tx_fifo_rst = 1;
+    SPIx->SPI_WRAP_CTRL = spi_0x200.d32;
+}
+
+#endif
+
+#if (SPI_SUPPORT_RAP_FUNCTION == 1)
+void SPI_RAPModeCmd(SPI_TypeDef *SPIx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_SPI_ALL_PERIPH(SPIx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    SPI_WRAP_CTRL_TypeDef spi_0x200 = {.d32 = SPIx->SPI_WRAP_CTRL};
+    spi_0x200.b.rap_ctrl_mode = NewState;
+    SPIx->SPI_WRAP_CTRL = spi_0x200.d32;
+}
+
+void SPI_SetActionCmdNum(SPI_TypeDef *SPIx, uint8_t num)
+{
+    /* Check the parameters */
+    assert_param(IS_SPI_ALL_PERIPH(SPIx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    SPI_WRAP_TCMD_NUM_TypeDef spi_0x230 = {.d32 = SPIx->SPI_WRAP_TCMD_NUM};
+    spi_0x230.b.task_cmd_num = num;
+    SPIx->SPI_WRAP_TCMD_NUM = spi_0x230.d32;
+}
+
+void SPI_SetActionWaitNum(SPI_TypeDef *SPIx, uint16_t num)
+{
+    /* Check the parameters */
+    assert_param(IS_SPI_ALL_PERIPH(SPIx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    SPI_WRAP_TWAIT_NUM_TypeDef spi_0x234 = {.d32 = SPIx->SPI_WRAP_TWAIT_NUM};
+    spi_0x234.b.task_wait_num = num;
+    SPIx->SPI_WRAP_TWAIT_NUM = spi_0x234.d32;
+}
+
+void SPI_SetActionTransferNum(SPI_TypeDef *SPIx, uint16_t num)
+{
+    /* Check the parameters */
+    assert_param(IS_SPI_ALL_PERIPH(SPIx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    SPI_WRAP_TTRAN_NUM_TypeDef spi_0x238 = {.d32 = SPIx->SPI_WRAP_TTRAN_NUM};
+    spi_0x238.b.task_tran_num = num;
+    SPIx->SPI_WRAP_TTRAN_NUM = spi_0x238.d32;
+}
+
+void SPI_SetActionTransfer(SPI_TypeDef *SPIx, uint8_t cmd_len, uint16_t wati_cnt,
+                           uint16_t dummy_len)
+{
+    SPI_WRAP_TCMD_NUM_TypeDef spi_0x230 = {.d32 = SPIx->SPI_WRAP_TCMD_NUM};
+    spi_0x230.b.task_cmd_num = cmd_len;
+    SPIx->SPI_WRAP_TCMD_NUM = spi_0x230.d32;
+
+    SPI_WRAP_TWAIT_NUM_TypeDef spi_0x234 = {.d32 = SPIx->SPI_WRAP_TWAIT_NUM};
+    spi_0x234.b.task_wait_num = wati_cnt;
+    SPIx->SPI_WRAP_TWAIT_NUM = spi_0x234.d32;
+
+    SPI_WRAP_TTRAN_NUM_TypeDef spi_0x238 = {.d32 = SPIx->SPI_WRAP_TTRAN_NUM};
+    spi_0x238.b.task_tran_num = dummy_len;
+    SPIx->SPI_WRAP_TTRAN_NUM = spi_0x238.d32;
+}
+
+void SPI_ActionTrigger(SPI_TypeDef *SPIx, uint32_t task)
+{
+    /* Check the parameters */
+    assert_param(IS_SPI_ALL_PERIPH(SPIx));
+
+    SPIx->SPI_WRAP_FW_ST |= BIT(task);
+}
+
+bool SPI_ActionEventStsCheck(SPI_TypeDef *SPIx, uint32_t te)
+{
+    /* Check the parameters */
+    assert_param(IS_SPI_ALL_PERIPH(SPIx));
+
+    return SPIx->SPI_WRAP_TASK_STS & BIT(te);
+}
+
+void SPI_ActionEventStsClear(SPI_TypeDef *SPIx, uint32_t te)
+{
+    /* Check the parameters */
+    assert_param(IS_SPI_ALL_PERIPH(SPIx));
+
+    SPIx->SPI_WRAP_TASK_STS |= BIT(te);
+}
+#endif
+
+#if (SPI_SUPPORT_REPEAT_MODE == 1)
+
+void SPI_SetRepeatMode(SPI_TypeDef *SPIx, SPIRepeatMode_TypeDef mode)
+{
+    /* Check the parameters */
+    assert_param(IS_SPI_ALL_PERIPH(SPIx));
+
+    SPI_WRAP_CTRL_TypeDef spi_0x200 = {.d32 = SPIx->SPI_WRAP_CTRL};
+    spi_0x200.b.repeat_reg_mode = mode;
+    SPIx->SPI_WRAP_CTRL = spi_0x200.d32;
+}
+
+void SPI_SetRepeatSize(SPI_TypeDef *SPIx, SPIRepeatSize_TypeDef size)
+{
+    /* Check the parameters */
+    assert_param(IS_SPI_ALL_PERIPH(SPIx));
+
+    SPI_WRAP_CTRL_TypeDef spi_0x200 = {.d32 = SPIx->SPI_WRAP_CTRL};
+    spi_0x200.b.repeat_size = size;
+    SPIx->SPI_WRAP_CTRL = spi_0x200.d32;
+}
+
+void SPI_SendRepeatData(SPI_TypeDef *SPIx, uint32_t data_l, uint32_t data_h)
+{
+    /* Check the parameters */
+    assert_param(IS_SPI_ALL_PERIPH(SPIx));
+
+    SPIx->SPI_WRAP_DATA_0 = data_l;
+    SPIx->SPI_WRAP_DATA_1 = data_h;
+}
+
+#endif
+
+
+
diff --git a/bee/drivers/timer/CMakeLists.txt b/bee/drivers/timer/CMakeLists.txt
new file mode 100644
index 00000000..49f51063
--- /dev/null
+++ b/bee/drivers/timer/CMakeLists.txt
@@ -0,0 +1,10 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+if(CONFIG_REALTEK_BEE_COMMON_DRIVER)
+    zephyr_include_directories(inc)
+endif()
+
+if (CONFIG_REALTEK_BEE_TIMER OR CONFIG_REALTEK_BEE_ENHTIMER)
+    add_subdirectory(src)
+endif()
diff --git a/bee/drivers/timer/Kconfig b/bee/drivers/timer/Kconfig
new file mode 100644
index 00000000..e15f2cc1
--- /dev/null
+++ b/bee/drivers/timer/Kconfig
@@ -0,0 +1,14 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config REALTEK_BEE_TIMER
+	bool "Realtek Bee TIMER driver"
+	default n
+	help
+	  This option enables the timer driver for Realtek Bee.
+
+config REALTEK_BEE_ENHTIMER
+	bool "Realtek Bee ENHTIMER driver"
+	default n
+	help
+	  This option enables the enhtimer driver for Realtek Bee.
diff --git a/bee/drivers/timer/inc/rtl_timer.h b/bee/drivers/timer/inc/rtl_timer.h
new file mode 100644
index 00000000..31b29b38
--- /dev/null
+++ b/bee/drivers/timer/inc/rtl_timer.h
@@ -0,0 +1,1021 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *               Define to prevent recursive inclusion
+ *============================================================================*/
+#ifndef RTL_TIMER_H
+#define RTL_TIMER_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*============================================================================*
+ *                        Header Files
+ *============================================================================*/
+#include "utils/rtl_utils.h"
+#if defined (CONFIG_SOC_SERIES_RTL87X2G)
+#include "timer/src/device/rtl87x2g/rtl_timer_def.h"
+#elif defined (CONFIG_SOC_SERIES_RTL87X3E)
+#include "timer/src/device/rtl87x3e/rtl_timer_def.h"
+#elif defined (CONFIG_SOC_SERIES_RTL87X3D)
+#include "timer/src/device/rtl87x3d/rtl_tim_def.h"
+#elif defined (CONFIG_SOC_SERIES_RTL87X2J)
+#include "timer/src/device/rtl87x2j/rtl_timer_def.h"
+#include "pinmux/inc/rtl87x2j/pin_def.h"
+#elif defined (CONFIG_SOC_SERIES_RTL87X3J)
+#include "timer/src/device/rtl87x3j/rtl_timer_def.h"
+#include "timer/src/device/rtl87x3j/rtl_timer_cc.h"
+#endif
+
+/** \defgroup TIMER         TIMER
+  * \brief
+  * \{
+  */
+/*============================================================================*
+ *                         Constants
+ *============================================================================*/
+/** \defgroup TIMER_Exported_Constants TIMER Exported Constants
+  * \brief
+  * \{
+  */
+
+/**
+ * \defgroup    TIMER_Mode TIMER Mode
+ * \{
+ * \ingroup     TIMER_Exported_Constants
+ */
+typedef enum
+{
+#if (TIMER_SUPPORT_FREERUN_MODE == 1)
+    TIMER_MODE_FREERUN,
+#endif
+    TIMER_MODE_USERDEFINE = 0x2,
+#if (TIMER_SUPPORT_USERDEFINE_AUTO_MODE == 1)
+    TIMER_MODE_USERDEFINE_AUTO = 0x1,
+#endif
+} TIMERMode_TypeDef;
+
+#define IS_TIMER_MODE(MODE) (((MODE) == TIMER_MODE_FREERUN) || \
+                             ((MODE) == TIMER_MODE_USERDEFINE) || \
+                             ((MODE) == TIMER_MODE_USERDEFINE_AUTO))
+
+/** End of TIMER_Mode
+  * \}
+  */
+
+#if (TIMER_SUPPORT_DIRECTION == 1)
+/**
+ * \defgroup    TIMER_Direction TIMER Direction
+ * \{
+ * \ingroup     TIMER_Exported_Constants
+ */
+
+typedef enum
+{
+    TIMER_DIRECTION_UP_COUNTING = 0x0,
+    TIMER_DIRECTION_DOWN_COUNTING = 0x1,
+} TIMERDirection_TypeDef;
+
+#define IS_TIMER_Direction(DIRECTION) (((DIRECTION) == TIMER_DIRECTION_UP_COUNTING) || \
+                                       ((DIRECTION) == TIMER_DIRECTION_DOWN_COUNTING))
+
+/** End of TIMER_Direction
+  * \}
+  */
+#endif
+
+#if (TIMER_SUPPORT_PWM_FUNCTION == 1)
+/**
+ * \defgroup    PWM_Polarity PWM Polarity
+ * \{
+ * \ingroup     TIMER_Exported_Constants
+ */
+typedef enum
+{
+    PWM_POLARITY_LOW = 0x00,
+    PWM_POLARITY_HIGH = 0x01,
+} PWMPolarity_TypeDef;
+
+#define IS_PWM_POLARITY(POL) (((POL) == PWM_POLARITY_LOW) || \
+                              ((POL) == PWM_POLARITY_HIGH))
+
+/** End of PWM_Polarity
+  * \}
+  */
+
+/**
+ * \defgroup    PWM_Output_Mode PWM Output Mode
+ * \{
+ * \ingroup     TIMER_Exported_Constants
+ */
+typedef enum
+{
+    PWM_PUSH_PULL = 0x0,
+    PWM_OPEN_DRAIN = 0x1,
+}
+PWMOutputMode_TypeDef;
+
+#define IS_PWM_OUTPUT_MODE(MODE) (((MODE) == PWM_PUSH_PULL) || \
+                                  ((MODE) == PWM_OPEN_DRAIN))
+
+/** End of PWM_Output_Mode
+  * \}
+  */
+
+#if (TIMER_SUPPORT_PWM_MODE == 1)
+/**
+ * \defgroup    PWM_Mode PWM Mode
+ * \{
+ * \ingroup     TIMER_Exported_Constants
+ */
+typedef enum
+{
+    PWM_MODE_OUTPUT_HIGH_CNT_BELOW_CMP = 0x0,
+    PWM_MODE_OUTPUT_LOW_CNT_BELOW_CMP = 0x1,
+    PWM_MODE_FIX_LOW = 0x2,
+    PWM_MODE_FIX_HIGH = 0x3,
+} PWMMode_TypeDef;
+
+#define IS_PWM_MODE(MODE)    (((MODE) == PWM_MODE_OUTPUT_HIGH_CNT_BELOW_CMP) || \
+                              ((MODE) == PWM_MODE_OUTPUT_LOW_CNT_BELOW_CMP) || \
+                              ((MODE) == PWM_MODE_FIX_LOW) || \
+                              ((MODE) == PWM_MODE_FIX_HIGH))
+
+/** End of PWM_Mode
+  * \}
+  */
+#endif
+
+#if (TIMER_SUPPORT_PWM_STOP_STATE_CONTROL == 1)
+/**
+ * \defgroup    PWM_Stop_State PWM Stop State
+ * \{
+ * \ingroup     TIMER_Exported_Constants
+ */
+typedef enum
+{
+    PWM_STOP_STATE_POLARITY_CONTROLLED = 0x0,
+    PWM_STOP_STATE_KEEP_LAST = 0x1,
+} PWMStopState_TypeDef;
+
+#define IS_PWM_STOP_STATE(STATE) (((STATE) == PWM_STOP_STATE_POLARITY_CONTROLLED) || \
+                                  ((STATE) == PWM_STOP_STATE_KEEP_LAST))
+
+/** End of PWM_Stop_State
+  * \}
+  */
+#endif
+
+#if (TIMER_SUPPORT_PWM_DEADZONE == 1)
+/**
+ * \defgroup    PWM_DeadZone_Stop_State PWM DeadZone Stop State
+ * \{
+ * \ingroup     TIMER_Exported_Constants
+ */
+typedef enum
+{
+    PWM_DZ_STOP_AT_LOW = 0x0,
+    PWM_DZ_STOP_AT_HIGH = 0x1,
+} PWMDZStopState_TypeDef;
+
+#define IS_PWM_DEADZONE_STOP_STATE(STATE) (((STATE) == PWM_DZ_STOP_AT_LOW) || \
+                                           ((STATE) == PWM_DZ_STOP_AT_HIGH))
+
+/** End of PWM_DeadZone_Stop_State
+  * \}
+  */
+
+#if (TIMER_SUPPORT_PWM_DEADZONE_REFERENCE == 1)
+/**
+ * \defgroup    PWM_DeadZone_Reference PWM DeadZone Reference
+ * \{*
+ * \ingroup     TIMER_Exported_Constants
+ */
+typedef enum
+{
+    PWM_DZ_REF_PWMPN = 0x0,
+    PWM_DZ_REF_PWMNN = 0x1,
+    PWM_DZ_REF_PWMPP = 0x2,
+    PWM_DZ_REF_PWMNP = 0x3,
+} PWMDZRef_TypeDef;
+
+#define IS_PWM_DEADZONE_REFERENCE(STATE) (((STATE) == PWM_DZ_REF_PWMPN) || \
+                                          ((STATE) == PWM_DZ_REF_PWMNN) || \
+                                          ((STATE) == PWM_DZ_REF_PWMPP) || \
+                                          ((STATE) == PWM_DZ_REF_PWMNP))
+
+/** End of PWM_DeadZone_Reference
+  * \}
+  */
+#endif
+#endif
+#endif
+
+#if (TIMER_SUPPORT_LATCH_CNT_0 == 1)
+/**
+ * \defgroup    TIMER_Latch_Trigger_Mode TIMER Latch Trigger Mode
+ * \{
+ * \ingroup     TIMER_Exported_Constants
+ */
+typedef enum
+{
+    TIMER_LATCH_TRIGGER_RISING_EDGE = 0x00,
+    TIMER_LATCH_TRIGGER_FALLING_EDGE = 0x01,
+    TIMER_LATCH_TRIGGER_BOTH_EDGE = 0x02,
+} TIMERLatchTriggerMode_TypeDef;
+
+#define IS_TIMER_LATCH_TRIGGER_MODE(MODE) (((MODE) == TIMER_LATCH_TRIGGER_RISING_EDGE) || \
+                                           ((MODE) == TIMER_LATCH_TRIGGER_FALLING_EDGE) || \
+                                           ((MODE) == TIMER_LATCH_TRIGGER_BOTH_EDGE))
+
+/** End of TIMER_Latch_Trigger_Mode
+  * \}
+  */
+#endif
+
+#if (TIMER_SUPPORT_DMA_FUNCTION == 1)
+/**
+ * \defgroup    TIMER_DMA_TARGET TIMER DMA TARGET
+ * \{
+ * \ingroup     TIMER_Exported_Constants
+ */
+typedef enum
+{
+    TIMER_DMA_CCR_FIFO = 0x00,
+    TIMER_DMA_LATCH_FIFO = 0x01,
+} TIMERDMATarget_TypeDef;
+
+#define IS_TIMER_DMA_TARGET(MODE) (((MODE) == TIMER_DMA_CCR_FIFO) || \
+                                   ((MODE) == TIMER_DMA_LATCH_FIFO))
+
+/** End of TIMER_DMA_TARGET
+  * \}
+  */
+#endif
+
+/**
+ * \defgroup    TIMER_Interrupts TIMER Interrupts
+ * \{
+ * \ingroup     TIMER_Exported_Constants
+ */
+#define TIMER_INT_TIMEOUT                        (1 << 0)
+#define TIMER_INT_PAUSE                          (1 << 1)
+#if (TIMER_SUPPORT_LATCH_CNT_0 == 1)
+#define TIMER_INT_LATCH_FIFO_FULL                (1 << 2)
+#define TIMER_INT_LATCH_FIFO_THRESHOLD           (1 << 3)
+#endif
+
+#if (TIMER_SUPPORT_LATCH_CNT_0 == 1)
+#define IS_TIMER_INT(INT) (((INT) == TIMER_INT_TIMEOUT) || \
+                           ((INT) == TIMER_INT_PAUSE)  || \
+                           ((INT) == TIMER_INT_LATCH_FIFO_FULL)   || \
+                           ((INT) == TIMER_INT_LATCH_FIFO_THRESHOLD))
+#else
+#define IS_TIMER_INT(INT) (((INT) == TIMER_INT_TIMEOUT) || \
+                           ((INT) == TIMER_INT_PAUSE))
+#endif
+
+/** End of TIMER_Interrupts
+  * \}
+  */
+
+#if (TIMER_SUPPORT_CCR_FIFO == 1 || TIMER_SUPPORT_LATCH_CNT_0 == 1)
+/**
+ * \defgroup    TIMER_Flag TIMER Flag
+ * \{
+ * \ingroup     TIMER_Exported_Constants
+ */
+#define TIMER_FLAG_CCR_FIFO_EMPTY                (0)
+#define TIMER_FLAG_CCR_FIFO_FULL                 (1)
+#define TIMER_FLAG_LATCH_FIFO_EMPTY              (2)
+#define TIMER_FLAG_LATCH_FIFO_FULL               (3)
+#define TIMER_FLAG_LATCH_FIFO_THRESHOLD          (4)
+
+#define IS_TIMER_FLAG(flag) (((flag) == TIMER_FLAG_CCR_FIFO_FULL) || \
+                             ((flag) == TIMER_FLAG_CCR_FIFO_EMPTY) || \
+                             ((flag) == TIMER_FLAG_LATCH_FIFO_EMPTY) || \
+                             ((flag) == TIMER_FLAG_LATCH_FIFO_FULL) || \
+                             ((flag) == TIMER_FLAG_LATCH_FIFO_THRESHOLD))
+
+/** End of TIMER_Flag
+  * \}
+  */
+
+/**
+ * \defgroup    TIMER_Clear_FIFO TIMER Clear FIFO
+ * \{
+ * \ingroup     TIMER_Exported_Constants
+ */
+#define TIMER_CLEAR_CCR_FIFO                     (0)
+#define TIMER_CLEAR_LATCH_FIFO                   (1)
+
+/** End of TIMER_Clear_FIFO
+  * \}
+  */
+#endif
+
+#if (TIMER_SUPPORT_RAP_FUNCTION == 1)
+
+/**
+ * \defgroup    TIMER_Action TIMER Action
+ * \{
+ * \ingroup     TIMER_Exported_Constants
+ */
+typedef enum
+{
+    TIMER_ACTION_START            = 0,
+    TIMER_ACTION_PAUSE            = 1,
+    TIMER_ACTION_STOP             = 2,
+} TIMERAction_TypeDef;
+
+/** End of TIMER_Action
+ * \}
+ */
+
+/**
+ * \defgroup    TIMER_Shortcut_Action TIMER Shortcut Action
+ * \{
+ * \ingroup     TIMER_Exported_Constants
+ */
+typedef enum
+{
+    TIMER_SHORTCUT_ACTION_PAUSE = 1,
+    TIMER_SHORTCUT_ACTION_STOP  = 2,
+} TIMERShortcutAction_TypeDef;
+
+/** End of TIMER_Shortcut_Action
+ * \}
+ */
+
+/**
+ * \defgroup    TIMER_Shortcut_Event TIMER Shortcut Event
+ * \{
+ * \ingroup     TIMER_Exported_Constants
+ */
+typedef enum
+{
+    TIMER_SHORTCUT_EVENT_TIMEOUT = 0,
+} TIMERShortcutEvent_TypeDef;
+
+/** End of TIMER_Shortcut_Event
+ * \}
+ */
+#endif
+
+/** End of TIMER_Exported_Constants
+  * \}
+  */
+
+/*============================================================================*
+ *                         Types
+ *============================================================================*/
+/** \defgroup TIMER_Exported_Types TIMER Exported Types
+  * \brief
+  * \{
+  */
+
+#if (TIMER_SUPPORT_PWM_DEADZONE == 1)
+/**
+ * \brief       TIMER init structure definition.
+ *
+ * \ingroup     TIMER_Exported_Types
+ */
+typedef struct
+{
+    PWMDZClockSrc_TypeDef PWM_DZClockSrc;     /*!< Specifies the pwm deazone clock source. */
+
+    PWMDZClockDiv_TypeDef PWM_DZClockDiv;     /*!< Specifies the pwm deazone clock divide. */
+
+    uint32_t PWM_DZSize;                      /*!< Specifies the pwm deazone Size.
+                                                   DeadzoneTime = deadzonesize / (32000 or 32768).
+                                                   This parameter must range from 1 to 0xff. */
+
+    FunctionalState PWM_DZEn;                 /*!< Specifies the pwm deazone enable.
+                                                   This parameter can be a value of DISABLE or ENABLE. */
+
+    PWMDZStopState_TypeDef PWM_DZStopStateP;  /*!< Specifies the PWM deazone P stop state. */
+
+    PWMDZStopState_TypeDef PWM_DZStopStateN;  /*!< Specifies the PWM deazone N stop state. */
+
+#if (TIMER_SUPPORT_PWM_DEADZONE_REFERENCE == 1)
+    FunctionalState PWM_DZInvertP;            /*!< Specifies ENHTIMER invertion of pwm_p.
+                                                   This parameter can be a value of PWM Reference */
+
+    FunctionalState PWM_DZInvertN;            /*!< Specifies ENHTIMER invertion of pwm_n.
+                                                   This parameter can be a value of PWM Reference */
+#endif
+} PWMDeadZone_TypeDef;
+#endif
+
+#if (TIMER_SUPPORT_LATCH_CNT_0 == 1)
+typedef struct
+{
+    FunctionalState TIMER_LatchEn[3];         /*!< Enable or disable TIMER latch function.
+                                                   This parameter can be a value of ENABLE or DISABLE. */
+
+    uint16_t        TIMER_LatchThreshold;     /*!< Specifies TIMER latched count fifo threshold.
+                                                   This parameter can be value of 0~8. */
+
+    TIMERLatchTriggerMode_TypeDef TIMER_LatchTriggerMode[3]; /*!< Specifies TIMER latch
+                                                   trigger mode. This parameter can be a
+                                                   value of /ref TIMERLatchTriggerMode_TypeDef. */
+
+
+    uint16_t        TIMER_LatchTriggerPad;    /*!< Specifies the TIMER latch trigger pad.
+                                                   This parameter can be a value of P0_0 to P19_0. */
+
+    FunctionalState TIMER_LatchDebEn;         /*!< Enable or disable TIMER latch debounce function.
+                                                   This parameter can be a value of ENABLE or DISABLE. */
+
+    TIMERClockDiv_TypeDef TIMER_LatchDebClockDiv; /*!< Specifies the TIMER latch debounce
+                                                   clock div.This parameter can be a value
+                                                   of /ref TIMERClockDiv_TypeDef. */
+
+    uint16_t       TIMER_LatchDebCountLimit;  /*!< Specifies the TIMER latch debounce count limit.
+                                                   This parameter must range from 0 to 65535. */
+} TIMERLatch_TypeDef;
+#endif
+
+typedef struct
+{
+    TIMERClockSrc_TypeDef TIMER_ClockSrc;   /*!< Specifies the clock source. */
+
+    TIMERClockDiv_TypeDef TIMER_ClockDiv;   /*!< Specifies the clock source div.
+                                                 This parameter can be a value of TIMER_Clock_Divider. */
+
+    TIMERMode_TypeDef TIMER_Mode;           /*!< Specifies the operating mode. */
+
+#if (TIMER_SUPPORT_DIRECTION == 1)
+    TIMERDirection_TypeDef TIMER_Direction; /*!< Specifies the timer direction. */
+#endif
+
+    uint32_t TIMER_Period;                  /*!< Specifies the period value to be loaded into the active
+                                                 Auto-Reload Register at the next update event.
+                                                 This parameter must range from 0x0 to 0xFFFFFFFF.
+                                                 period = PWM_HighCount + PWM_LowCount */
+
+    FunctionalState TIMER_OneShotEn;        /*!< Specifies the one shot mode. */
+
+#if (TIMER_SUPPORT_PERIOD_IMMEDIATELY_UPDATE == 1)
+    FunctionalState
+    TIMER_PeriodImmediatelyUpdateEn;    /*!< Enable or disable immediately update period.
+                                                             This parameter can be a value of ENABLE or DISABLE. */
+#endif
+
+#if (TIMER_SUPPORT_TOGGLE_OUTPUT == 1)
+    FunctionalState TIMER_ToggleOutputEn;   /*!< Enable or disable timer toggle output.
+                                                 This parameter can be a value of ENABLE or DISABLE. */
+#endif
+
+#if (TIMER_SUPPORT_PWM_FUNCTION == 1)
+    FunctionalState PWM_En;                 /*!< Specifies the PWM mode.
+                                                 This parameter can be a value of DISABLE or ENABLE. */
+
+    uint32_t PWM_HighCount;                 /*!< Specifies the PWM High Count.
+                                                This parameter must range from 0x0 to 0xFFFFFFFF. */
+
+    PWMPolarity_TypeDef PWM_Polarity;       /*!< Specifies enhtimer toggle output polarity
+                                                 for user-define PWM mode.*/
+
+    PWMOutputMode_TypeDef PWM_OutputMode;   /*!< Specifies enable PWM open drain. */
+
+#if (TIMER_SUPPORT_PWM_MODE == 1)
+    PWMMode_TypeDef PWM_Mode;       /*!< Specifies PWM mode.
+                                         This parameter can be a value of /ref PWM_Mode. */
+#endif
+
+#if (TIMER_SUPPORT_PWM_STOP_STATE_CONTROL == 1)
+    PWMStopState_TypeDef PWM_StopState;     /*!< Specifies enable PWM stop state.
+                                                 This parameter can be a value of /ref PWM_Stop_State. */
+#endif
+#endif
+
+#if (TIMER_SUPPORT_PWM_DEADZONE == 1)
+    PWMDeadZone_TypeDef PWM_DZ;             /*!< Specifies PWM Dead Zone. */
+#endif
+
+#if (TIMER_SUPPORT_LATCH_CNT_0 == 1)
+    TIMERLatch_TypeDef TIMER_Latch;        /*!< Specifies TIMER Latch Count. */
+#endif
+
+#if (TIMER_SUPPORT_DMA_FUNCTION == 1)
+    FunctionalState TIMER_DMAEn;            /*!< Specifies enable TIMER DMA.
+                                                 This parameter can be a value of DISABLE or ENABLE. */
+
+    TIMERDMATarget_TypeDef TIMER_DMATarget; /*!< Specifies TIMER DMA target. */
+#endif
+
+#if (TIMER_COMPARE_CHANNEL_NUM > 0)
+    TIMERCompare_TypeDef TIMER_Compare;     /*!< Specifies timer compare. */
+#endif
+
+#if (TIMER_CAPTURE_CHANNEL_NUM > 0)
+    TIMERCapture_TypeDef TIMER_Capture;        /*!< Specifies TIMER Latch Count. */
+#endif
+
+#if (TIMER_SUPPORT_CC_FIFO == 1)
+    TIMERCCFIFO_TypeDef TIMER_CCFIFO;       /*!< Specifies timer CC FIFO. */
+#endif
+
+#if (TIMER_SUPPORT_AUTO_CLOCK == 1)
+    FunctionalState TIMER_DynConfigEn;      /*!< Specifies the functon to dynamic adjustment of
+                                                    CCR & MAX_CNT.  When this feature is enabled,
+                                                    dynamic adjustment is supported. When this feature
+                                                    is disabled, dynamic adjustment is not supported,
+                                                    resulting in lower power consumption.*/
+#endif
+} TIMER_TimeBaseInitTypeDef;
+
+/** End of TIMER_Exported_Types
+  * \}
+  */
+
+/*============================================================================*
+ *                         Functions
+ *============================================================================*/
+/** \defgroup TIMER_Exported_Functions TIMER Exported Functions
+  * \brief
+  * \{
+  */
+
+/**
+ * \brief   Deinitialize the TIMERx peripheral registers to their default reset values.
+ *
+ * \return  None.
+ */
+void TIMER_DeInit(TIMER_TypeDef *TIMERx);
+
+/**
+ * \brief   Initialize the TIMERx time base unit peripheral according to
+ *          the specified parameters in TIMER_InitStruct.
+ *
+ * \param[in] TIMERx: Select the TIMER peripheral. \ref TIMER_Declaration
+ * \param[in] TIMER_InitStruct: Pointer to a TIMER_TimeBaseInitTypeDef
+ *            structure that contains the configuration information for the selected TIMER peripheral.
+ *
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_timer_init(void)
+ * {
+ *     RCC_ClockCmd(TIMER_CLOCK, ENABLE);
+ *
+ *     TIMER_TimeBaseInitTypeDef TIMER_InitStruct;
+ *     TIMER_StructInit(&TIMER_InitStruct);
+ *     TIMER_InitStruct.TIMER_PWM_En = DISABLE;
+ *     TIMER_InitStruct.TIMER_Period = 1000000 - 1 ;
+ *     TIMER_InitStruct.TIMER_Mode = TIMER_Mode_UserDefine;
+ *     TIMER_TimeBaseInit(TIMER6, &TIMER_InitStruct);
+ * }
+ * \endcode
+ */
+void TIMER_TimeBaseInit(TIMER_TypeDef *TIMERx, TIMER_TimeBaseInitTypeDef *TIMER_InitStruct);
+
+/**
+ * \brief   Fills each TIMER_InitStruct member with its default value.
+ *
+ * \param[in] TIMER_InitStruct: Pointer to a TIMER_TimeBaseInitTypeDef structure which will be initialized.
+ *
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_timer_init(void)
+ * {
+ *     RCC_ClockCmd(TIMER_CLOCK, ENABLE);
+ *
+ *     TIMER_TimeBaseInitTypeDef TIMER_InitStruct;
+ *     TIMER_StructInit(&TIMER_InitStruct);
+ *     TIMER_InitStruct.TIMER_PWM_En = DISABLE;
+ *     TIMER_InitStruct.TIMER_Period = 1000000 - 1;
+ *     TIMER_InitStruct.TIMER_Mode = TIMER_Mode_UserDefine;
+ *     TIMER_TimeBaseInit(TIMER6, &TIMER_InitStruct);
+ * }
+ * \endcode
+ */
+void TIMER_StructInit(TIMER_TimeBaseInitTypeDef *TIMER_InitStruct);
+
+/**
+ * \brief   Enables or disables the specified TIMER peripheral.
+ *
+ * \param[in] TIMERx: Select the TIMER peripheral. \ref TIMER_Declaration
+ * \param[in] NewState: New state of the TIMERx peripheral.
+ *            This parameter can be: ENABLE or DISABLE.
+ *
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_timer_init(void)
+ * {
+ *     RCC_ClockCmd(TIMER_CLOCK, ENABLE);
+ *
+ *     TIMER_TimeBaseInitTypeDef TIMER_InitStruct;
+ *     TIMER_StructInit(&TIMER_InitStruct);
+ *     TIMER_InitStruct.TIMER_PWM_En = DISABLE;
+ *     TIMER_InitStruct.TIMER_Period = 1000000 - 1;
+ *     TIMER_InitStruct.TIMER_Mode = TIMER_Mode_UserDefine;
+ *     TIMER_TimeBaseInit(TIMER6, &TIMER_InitStruct);
+ *     TIMER_Cmd(TIMER6, ENABLE);
+ * }
+ * \endcode
+ */
+void TIMER_Cmd(TIMER_TypeDef *TIMERx, FunctionalState NewState);
+
+#if (TIMER_SUPPORT_CLEAR_COUNTER == 1)
+/**
+ * \brief   Clear counter of the specified TIMER peripheral.
+ *
+ * \param[in] TIMERx: Select the TIMER peripheral. \ref TIMER_Declaration
+ *
+ * \return  None.
+ *
+ */
+void TIMER_ClearCounter(TIMER_TypeDef *TIMERx);
+#endif
+
+/**
+ * \brief       Enables or disables the specified TIMERx interrupt.
+ *
+ * \param[in]   TIMERx: Select the TIMER peripheral. \ref TIMER_Declaration
+ * \param[in]   NewState: New state of the TIMERx peripheral.
+ *              This parameter can be: ENABLE or DISABLE.
+ *
+ * \return      None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_timer_init(void)
+ * {
+ *     RCC_ClockCmd(TIMER_CLOCK, ENABLE);
+ *
+ *     TIMER_TimeBaseInitTypeDef TIMER_InitStruct;
+ *     TIMER_StructInit(&TIMER_InitStruct);
+ *     TIMER_InitStruct.TIMER_PWM_En = DISABLE;
+ *     TIMER_InitStruct.TIMER_Period = 1000000 - 1;
+ *     TIMER_InitStruct.TIMER_Mode = TIMER_Mode_UserDefine;
+ *     TIMER_TimeBaseInit(TIMER6, &TIMER_InitStruct);
+ *     TIMER_ClearINT(TIMER6);
+ *     TIMER_INTConfig(TIMER6, ENABLE);
+ */
+void TIMER_INTConfig(TIMER_TypeDef *TIMERx, uint8_t TIMER_INT, FunctionalState NewState);
+
+
+/**
+ * \brief   Check whether the TIMER interrupt has occurred or not.
+ *
+ * \param[in] TIMERx: Select the TIMER peripheral. \ref TIMER_Declaration
+ *
+ * \return  The new state of the TIMER_IT(SET or RESET).
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void timer_demo(void)
+ * {
+ *     ITStatus int_status = TIMER_GetINTStatus(TIMER6);
+ * }
+ * \endcode
+ */
+ITStatus TIMER_GetINTStatus(TIMER_TypeDef *TIMERx, uint8_t TIMER_INT);
+
+/**
+ * \brief   Clear TIMER interrupt.
+ *
+ * \param[in] TIMERx: Select the TIMER peripheral. \ref TIMER_Declaration
+ *
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void timer_demo(void)
+ * {
+ *     TIMER_ClearINT(TIMER6);
+ * }
+ * \endcode
+ */
+void TIMER_ClearINT(TIMER_TypeDef *TIMERx, uint8_t TIMER_INT);
+
+#if (TIMER_SUPPORT_CCR_FIFO == 1 || TIMER_SUPPORT_LATCH_CNT_0 == 1) || (TIMER_SUPPORT_CC_FIFO == 1)
+/**
+  * \brief  Check whether the specified TIMER flag is set.
+  * \param  TIMERx: Select the TIMER peripheral. \ref TIMER_Declaration
+  * \param  TIMER_FLAG: Specifies the flag to check.
+  * \return The new state of TIMER_FLAG (SET or RESET).
+  */
+FlagStatus TIMER_GetFIFOFlagStatus(TIMER_TypeDef *TIMERx, uint32_t TIMER_FLAG);
+#endif
+
+/**
+ * \brief       Change TIMER period value.
+ *
+ * \param[in]   TIMERx: Select the TIMER peripheral. \ref TIMER_Declaration
+ * \param[in]   period: Period value to be changed.
+ *
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void timer_demo(void)
+ * {
+ *     uint32_t new_period = 1000000 - 1;
+ *     TIMER_Cmd(TIMER6, DISABLE);
+ *     TIMER_ChangePeriod(TIMER6, new_period);
+ *
+ * }
+ * \endcode
+ */
+void TIMER_ChangePeriod(TIMER_TypeDef *TIMERx, uint32_t period);
+
+/**
+ * \brief   Get TIMERx period value.
+ *
+ * \param[in] TIMERx: Select the TIMER peripheral. \ref TIMER_Declaration
+ *
+ * \return  TIMER period value.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void timer_demo(void)
+ * {
+ *     uint32_t period = TIMER_GetPeriod(TIMER6);
+ * }
+ * \endcode
+ */
+uint32_t TIMER_GetPeriod(TIMER_TypeDef *TIMERx);
+
+/**
+ * \brief   Get TIMERx current value when timer is running.
+ *
+ * \param[in] TIMERx: Select the TIMER peripheral. \ref TIMER_Declaration
+ *
+ * \return  The counter value.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void timer_demo(void)
+ * {
+ *     uint32_t cur_value = TIMER_GetCurrentValue(TIMER6);
+ * }
+ * \endcode
+ */
+uint32_t TIMER_GetCurrentValue(TIMER_TypeDef *TIMERx);
+
+/**
+ * \brief Get TIMERx elapsed value when timer is running.
+ *
+ * \param[in] TIMERx: Select the TIMER peripheral. \ref TIMER_Declaration
+ *
+ * \return The elapsed counter value.
+ */
+uint32_t TIMER_GetElapsedValue(TIMER_TypeDef *TIMERx);
+
+/**
+ * \brief   Check whether the TIMER is in operation or not.
+ *
+ * \param[in] TIMERx: Select the TIMER peripheral. \ref TIMER_Declaration
+ *
+ * \return  The new state of the timer operation status (SET or RESET).
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void timer_demo(void)
+ * {
+ *     ITStatus intstatus = TIMER_GetOperationStatus(TIMER6);
+ * }
+ * \endcode
+ */
+FlagStatus TIMER_GetOperationStatus(TIMER_TypeDef *TIMERx);
+
+/**
+  * \brief  Enable/disable to pause timer counter.
+  * \param  TIMERx: Select the TIMER peripheral. \ref TIMER_Declaration
+  * \param  NewState: New state of the TIMERx peripheral.
+  * \return None.
+  */
+void TIMER_PauseCmd(TIMER_TypeDef *TIMERx, FunctionalState NewState);
+
+#if (TIMER_SUPPORT_CCR_FIFO == 1) || (TIMER_SUPPORT_CC_FIFO == 1)
+/**
+  * \brief  Write TIMERx compare FIFO.
+  * \param  TIMERx: Select the TIMER peripheral. \ref TIMER_Declaration
+  * \param  value: Value to be written to compare FIFO.
+  * \return None
+  */
+void TIMER_SetCompareFIFO(TIMER_TypeDef *TIMERx, uint32_t value);
+#endif
+
+#if (TIMER_SUPPORT_CCR_FIFO == 1 || TIMER_SUPPORT_LATCH_CNT_0 == 1)
+/**
+  * \brief  Clear capture/compare or latch count0 fifo.
+  * \param  TIMERx: Select the TIMER peripheral. \ref TIMER_Declaration
+  * \param  FIFO_CLR: Specifies the FIFO type which to be clear.
+  * \return FIFO data length.
+  */
+void TIMER_ClearFIFO(TIMER_TypeDef *TIMERx, uint8_t FIFO_CLR);
+#endif
+
+#if (TIMER_SUPPORT_LATCH_CNT_0 == 1)
+/**
+  * \brief  Read TIMERx latch counter0 fifo data.
+  * \param  TIMERx: Select the TIMER peripheral. \ref TIMER_Declaration
+  * \param  length: Latch count0 fifo length, max 8.
+  * \pBuf   pBuf: FIFO data out buffer.
+  * \return None.
+  */
+void TIMER_GetLatchFIFO(TIMER_TypeDef *TIMERx, uint32_t *pBuf, uint8_t length);
+
+/**
+  * \brief  Get TIMER latch counter0 fifo length.
+  * \param  TIMERx: Select the TIMER peripheral. \ref TIMER_Declaration
+  * \return FIFO data length.
+  */
+uint8_t TIMER_GetLatchFIFOLength(TIMER_TypeDef *TIMERx);
+#endif
+
+/**
+  * \brief  Get TIMER toggle state
+  * \param  TIMERx: Select the TIMER peripheral. \ref TIMER_Declaration
+  * \return The new state of toggle state(SET or RESET).
+  */
+bool TIMER_GetToggleState(TIMER_TypeDef *TIMERx);
+
+#if (TIMER_SUPPORT_PWM_FUNCTION == 1)
+/**
+ * \brief   Change PWM freq and duty according high_cnt and low_cnt
+ *
+ * \param[in]   TIMERx: Select the TIMER peripheral. \ref TIMER_Declaration
+ * \param[in]   high_count: This parameter can be 0x00~0xFFFFFFFF.
+ * \param[in]  low_count: This parameter can be 0x00~0xFFFFFFFF.
+ *
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * #define TIMER_DEMO TIMERB_6
+ *
+ * void timer_demo(void)
+ * {
+ *     uint32_t high_count = 1000000 - 1;
+ *     uint32_t low_count = 1000000 - 1;
+ *     TIMER_Cmd(TIMER_DEMO, DISABLE);
+ *     TIMER_ChangePeriod(TIMER_DEMO, high_count, low_count);
+ * }
+ * \endcode
+ */
+void TIMER_PWMChangeFreqAndDuty(TIMER_TypeDef *TIMERx, uint32_t period, uint32_t high_count);
+
+#if (TIMER_SUPPORT_PWM_PHASE_SHIFT == 1)
+/**
+ * \brief  Change TIMER pwm_phase_shift count
+ * \param  TIMERx: Select the TIMER peripheral. \ref TIMER_Declaration
+ * \param  ShiftCount:This parameter can be 0 to ccr;
+ * \return None
+ */
+void TIMER_SetShiftCount(TIMER_TypeDef *TIMERx, uint32_t ShiftCount);
+#endif
+
+#if (TIMER_SUPPORT_PWM_DEADZONE == 1)
+#if (TIMER_SUPPORT_PWM_DEADZONE_REFERENCE == 1)
+/**
+ * \brief  TIMER PWMP/N Source Select.
+ * \param  TIMERx: Select the TIMER peripheral. \ref TIMER_Declaration
+ * \param  PWMDZRefcSel: State of the TIMERx PWMP/N.
+ * \return None.
+ */
+void TIMER_SetPWMDZRef(TIMER_TypeDef *TIMERx, PWMDZRef_TypeDef PWMDZRef);
+#endif
+
+/**
+ * \brief   PWM complementary output emergency stop and resume.
+ *          PWM_P emergency stop level state is configured by PWM_Stop_State_P,
+ *          PWM_N emergency stop level state is configured by PWM_Stop_State_N.
+ *
+ * \param[in] PWMx: Select the PWM peripheral. \ref PWM_Declaration
+ * \param[in] NewState: New state of complementary output.
+ *            \ref DISABLE: Resume PWM complementary output.
+ *            \ref ENABLE: PWM complementary output emergency stop.
+ *
+ * \return  None.
+ * \note    To use this function, need to configure the corresponding timer.
+ *          PWM2 ->> TIMER2, PWM3 ->> TIMER3.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void board_pwm_init(void)
+ * {
+ *     Pad_Config(P0_1, PAD_PINMUX_MODE, PAD_IS_PWRON, PAD_PULL_NONE, PAD_OUT_ENABLE, PAD_OUT_HIGH);
+ *     Pad_Config(P0_2, PAD_PINMUX_MODE, PAD_IS_PWRON, PAD_PULL_NONE, PAD_OUT_ENABLE,
+ *                PAD_OUT_HIGH);
+ *     Pad_Config(P2_2, PAD_PINMUX_MODE, PAD_IS_PWRON, PAD_PULL_NONE, PAD_OUT_ENABLE,
+ *                PAD_OUT_HIGH);
+ *
+ *     Pinmux_Config(P0_1, PWM_OUT_PIN_PINMUX);
+ *     Pinmux_Config(P0_2, PWM_OUT_P_PIN_PINMUX);
+ *     Pinmux_Config(P2_2, PWM_OUT_N_PIN_PINMUX);
+ * }
+ *
+ * void driver_pwm_init(void)
+ * {
+ *     RCC_ClockCmd(TIMER_CLOCK, ENABLE);
+ *
+ *     TIMER_TimeBaseInitTypeDef TIMER_InitStruct;
+ *     TIMER_StructInit(&TIMER_InitStruct);
+ *     TIMER_InitStruct.TIMER_Mode             = TIMER_Mode_UserDefine;
+ *     TIMER_InitStruct.TIMER_PWM_En           = ENABLE;
+ *     TIMER_InitStruct.TIMER_PWM_High_Count   = PWM_HIGH_COUNT;
+ *     TIMER_InitStruct.TIMER_PWM_Low_Count    = PWM_LOW_COUNT;
+ *     TIMER_InitStruct.PWM_Stop_State_P     = PWM_STOP_AT_HIGH;
+ *     TIMER_InitStruct.PWM_Stop_State_N     = PWM_STOP_AT_LOW;
+ *     TIMER_InitStruct.PWMDeadZone_En       = ENABLE;  //enable to use pwn p/n output
+ *     TIMER_InitStruct.PWM_Deazone_Size     = 255;
+ *     TIMER_TimeBaseInit(PWM2, &TIMER_InitStruct);
+ *
+ *     TIMER_Cmd(PWM2, ENABLE);
+ * }
+ *
+ * void pwm_demo(void)
+ * {
+ *    board_pwm_init();
+ *    driver_pwm_init();
+ *    //Add delay.
+ *    TIMER_PWMComplOutputEMCmd(PWM2,ENABLE);
+ * }
+ * \endcode
+ */
+void TIMER_PWMComplOutputEMCmd(TIMER_TypeDef *TIMERx, FunctionalState NewState);
+#endif
+#endif
+
+/**
+ * \brief  TIMER clock config.
+ *
+ * \param[in] TIMERx: Select the TIMER peripheral. \ref TIMER_Declaration
+ * \param[in] ClockSrc: specifies the PLL clock source.
+ * \param[in] ClockDiv: specifies the APB peripheral to gates its clock.
+ *
+ * \return None
+ */
+void TIMER_SetClock(TIMER_TypeDef *TIMERx, uint32_t ClockSrc, uint16_t ClockDiv);
+
+/**
+ * \brief  Get TIMER clock.
+ *
+ * \param[in] TIMERx: Select the TIMER peripheral. \ref TIMER_Declaration
+ * \param[in] ClockSrc: specifies the clock source.
+ * \param[in] ClockDiv: specifies the clock divide.
+ *
+ * \return None
+ */
+bool TIMER_GetClock(TIMER_TypeDef *TIMERx, uint32_t *ClockSrc, uint16_t *ClockDiv);
+
+#if (TIMER_SUPPORT_RAP_FUNCTION == 1)
+
+void TIMER_RAPModeCmd(TIMER_TypeDef *TIMERx, FunctionalState NewState);
+
+void TIMER_ActionTrigger(TIMER_TypeDef *TIMERx, uint32_t Action);
+
+void TIMER_ShortcutCmd(TIMER_TypeDef *TIMERx, uint32_t Action, uint32_t Event,
+                       FunctionalState NewState);
+
+#endif
+
+#if (TIMER_SUPPORT_AUTO_CLOCK == 1)
+
+void TIMER_SetClockAutoMode(TIMER_TypeDef *TIMERx, uint32_t AutoMode);
+
+#endif
+
+/** End of TIMER_Exported_Functions
+  * \}
+  */
+
+/** End of TIMER
+  * \}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*_RTL_TIMER_H_*/
+
+
+
diff --git a/bee/drivers/timer/src/CMakeLists.txt b/bee/drivers/timer/src/CMakeLists.txt
new file mode 100644
index 00000000..dd5e359a
--- /dev/null
+++ b/bee/drivers/timer/src/CMakeLists.txt
@@ -0,0 +1,4 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+add_subdirectory(device)
diff --git a/bee/drivers/timer/src/device/CMakeLists.txt b/bee/drivers/timer/src/device/CMakeLists.txt
new file mode 100644
index 00000000..390b5305
--- /dev/null
+++ b/bee/drivers/timer/src/device/CMakeLists.txt
@@ -0,0 +1,11 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+if(CONFIG_REALTEK_BEE_COMMON_DRIVER)
+    file(GLOB BEE_DRIVER_COMMON_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/rtl_common/*.c")
+    zephyr_library_sources(${BEE_DRIVER_COMMON_SOURCES})
+endif()
+
+add_soc_series_subdir(rtl8752h)
+add_soc_series_subdir(rtl87x2g)
+add_soc_series_subdir(rtl87x2j)
diff --git a/bee/drivers/timer/src/device/rtl8752h/CMakeLists.txt b/bee/drivers/timer/src/device/rtl8752h/CMakeLists.txt
new file mode 100644
index 00000000..834e2962
--- /dev/null
+++ b/bee/drivers/timer/src/device/rtl8752h/CMakeLists.txt
@@ -0,0 +1,7 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_include_directories(${CMAKE_CURRENT_SOURCE_DIR})
+
+zephyr_library_sources_ifdef(CONFIG_REALTEK_BEE_TIMER rtl876x_tim.c)
+zephyr_library_sources_ifdef(CONFIG_REALTEK_BEE_ENHTIMER rtl876x_enh_tim.c)
diff --git a/bee/drivers/timer/src/device/rtl8752h/rtl876x_enh_tim.c b/bee/drivers/timer/src/device/rtl8752h/rtl876x_enh_tim.c
new file mode 100644
index 00000000..e6512737
--- /dev/null
+++ b/bee/drivers/timer/src/device/rtl8752h/rtl876x_enh_tim.c
@@ -0,0 +1,595 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "rtl876x_rcc.h"
+#include "rtl876x_enh_tim.h"
+#include "app_section.h"
+
+/* ENHTIM Private Defines */
+#define TIMER_CLK_SOURCE_REG_35C (*((volatile uint32_t *)0x4000035CUL))
+#define TIMER_CLK_SOURCE_REG_360 (*((volatile uint32_t *)0x40000360UL))
+
+/**
+  * @brief  Initializes the ENHTIMx peripheral according to
+  *         the specified parameters in the ENHTIM_InitStruct.
+  * @param  ENHTIMx: where x can be 0 to 1 to select the ENHTIM peripheral.
+  * @param  ENHTIM_InitStruct: pointer to a ENHTIM_InitTypeDef structure
+  *         that contains the configuration information for the specified ENHTIM peripheral.
+  * @retval None
+  */
+void ENHTIM_Init(ENHTIM_TypeDef *ENHTIMx, ENHTIM_InitTypeDef *ENHTIM_InitStruct)
+{
+    uint32_t enhtim_id = 0;
+    uint32_t temp = 0;
+
+    /* Check the parameters */
+    assert_param(IS_ENHTIM_ALL_PERIPH(ENHTIMx));
+
+    enhtim_id = ((uint32_t)ENHTIMx - (uint32_t)ENH_TIM0) / 0x24;
+
+    ENH_TIM_SHARE->CMD &= ~BIT(enhtim_id);
+    ENH_TIM_SHARE->INT_CMD &= ~BIT(enhtim_id);
+
+    /* Clock source config */
+    if (TIMER_CLK_SOURCE_REG_360 & BIT(10))
+    {
+        TIMER_CLK_SOURCE_REG_360 &= ~(BIT(10));
+    }
+
+    TIMER_CLK_SOURCE_REG_360 |= ((ENHTIM_InitStruct->ENHTIM_ClockDiv & 0x07) << (enhtim_id * 3 + 25));
+
+    if (ENHTIM_InitStruct->ENHTIM_PWMDeadZoneClockSource == ENHTIM_PWM_DZCLKSRCE_32K)
+    {
+        TIMER_CLK_SOURCE_REG_360 |= BIT8;
+    }
+
+    TIMER_CLK_SOURCE_REG_35C |= ((ENHTIM_InitStruct->ENHTIM_ClockSource & 0x01) << (enhtim_id + 1));
+
+    temp = 0;
+    for (uint8_t i = 0; i < 3; i++)
+    {
+        temp |= ((ENHTIM_InitStruct->ENHTIM_LatchCountEn[i] & 0x01) << (i + 10)) \
+                | ((ENHTIM_InitStruct->ENHTIM_LatchCountTrigger[i] & 0x03) << (i * 2 + 4));
+    }
+    ENHTIMx->CR |= temp;
+
+    /*Config latch count2. */
+    temp = 0x3F;
+    if (ENHTIM_InitStruct->ENHTIM_LatchCountEn[2] == ENHTIM_LATCH_COUNT_ENABLE)
+    {
+        /* Clear Latch Count2 thd */
+        ENHTIMx->CR &= ~(0x1F << 23);
+        ENHTIMx->CR |= (ENHTIM_InitStruct->ENHTIM_LatchCount2Thd & 0x1F) << 23;
+
+        /* Config Latch Count2 trigger GPIO pin. */
+        if ((ENHTIM_InitStruct->ENHTIM_LatchTriggerPad >= P1_6) &&
+            (ENHTIM_InitStruct->ENHTIM_LatchTriggerPad <= P3_6))
+        {
+            temp = (ENHTIM_InitStruct->ENHTIM_LatchTriggerPad - 4);
+        }
+        else if ((ENHTIM_InitStruct->ENHTIM_LatchTriggerPad >= P4_0) &&
+                 (ENHTIM_InitStruct->ENHTIM_LatchTriggerPad <= P5_2))
+        {
+            temp = (ENHTIM_InitStruct->ENHTIM_LatchTriggerPad - 5);
+        }
+        else if (ENHTIM_InitStruct->ENHTIM_LatchTriggerPad <= P1_1)
+        {
+            temp = (ENHTIM_InitStruct->ENHTIM_LatchTriggerPad);
+        }
+    }
+
+    ENHTIM_LATCH_COUNT_CR &=  ~(0x1FF);
+    ENHTIM_LATCH_COUNT_CR |= (ENHTIM_InitStruct->ENHTIM_TimerGPIOTriggerEn << 8) | \
+                             (ENHTIM_InitStruct->ENHTIM_BTGPIOTriggerEn << 7) | \
+                             ((enhtim_id & 0x01) << 6) | ((temp) & 0x3F);
+
+    /* Config PWM mode. */
+    temp = 0;
+    if ((ENHTIM_InitStruct->ENHTIM_Mode == ENHTIM_MODE_PWM_AUTO) ||
+        (ENHTIM_InitStruct->ENHTIM_Mode == ENHTIM_MODE_PWM_MANUAL))
+    {
+        temp = (ENHTIM_InitStruct->ENHTIM_PWMStartPolarity & 0x04) |
+               (ENHTIM_InitStruct->ENHTIM_PWMOutputEn & 0x08) |
+               ENHTIM_InitStruct->ENHTIM_Mode;
+        ENHTIMx->CR |= temp;
+        temp = 0;
+        ENHTIMx->MAX_CNT = ENHTIM_InitStruct->ENHTIM_MaxCount;
+    }
+
+    if (ENHTIM_InitStruct->ENHTIM_Mode == ENHTIM_MODE_PWM_MANUAL)
+    {
+        ENHTIMx->CCR = ENHTIM_InitStruct->ENHTIM_CCValue;
+    }
+
+    /* Set pwm1 deadzone mode, pwm1_pn based on enhance timer0 */
+    if (ENHTIM_InitStruct->ENHTIM_PWMDeadZoneEn == ENHTIM_PWM_DEADZONE_ENABLE)
+    {
+        if (enhtim_id  == 0)
+        {
+            /* Set pwm deadzone time. */
+            ENHTIM_PWM_DEADZONE_CR |= ((ENHTIM_InitStruct->ENHTIM_PWMDeadZoneClockSource & 0x90000) \
+                                       | ((ENHTIM_InitStruct->ENHTIM_PWMStopStateP << 10) & (BIT10)) \
+                                       | ((ENHTIM_InitStruct->ENHTIM_PWMStopStateN << 9) & (BIT9)) \
+                                       | (ENHTIM_InitStruct->ENHTIM_DeadZoneSize & 0xFF) \
+                                       | BIT12 | BIT17 | BIT18);
+        }
+    }
+    else
+    {
+        if (enhtim_id == 0)
+        {
+            /* Disable pwm1 deadzone mode. */
+            ENHTIM_PWM_DEADZONE_CR &= ~(BIT12 | BIT17 | BIT18);
+        }
+    }
+
+    /* Clear the IT status */
+    ENH_TIM_SHARE->FIFO_SR0 |= BIT(16 + enhtim_id);
+    ENH_TIM_SHARE->FIFO_SR2 |= BIT(16 + enhtim_id * 2);
+    ENH_TIM_SHARE->INT_SR |= BIT(enhtim_id);
+}
+
+/**
+  * @brief  Fills each ENHTIM_InitStruct member with its default value.
+  * @param  ENHTIM_InitStruct: Pointer to a ENHTIM_InitStruct structure which will be initialized.
+  * @return None.
+  */
+void ENHTIM_StructInit(ENHTIM_InitTypeDef *ENHTIM_InitStruct)
+{
+    ENHTIM_InitStruct->ENHTIM_ClockSource           = ENHTIM_DIVIDER_CLOCK;
+    ENHTIM_InitStruct->ENHTIM_ClockDiv              = ENHTIM_CLOCK_DIVIDER_1;
+    ENHTIM_InitStruct->ENHTIM_Mode                  = ENHTIM_MODE_FreeRun;
+    ENHTIM_InitStruct->ENHTIM_PWMOutputEn           = ENHTIM_PWM_DISABLE;
+    ENHTIM_InitStruct->ENHTIM_PWMStartPolarity      = ENHTIM_PWM_START_WITH_LOW;
+    ENHTIM_InitStruct->ENHTIM_LatchCountEn[0]       = ENHTIM_LATCH_COUNT_DISABLE;
+    ENHTIM_InitStruct->ENHTIM_LatchCountTrigger[0]  = ENHTIM_LATCH_TRIGGER_RISING_EDGE;
+    ENHTIM_InitStruct->ENHTIM_LatchCountEn[1]       = ENHTIM_LATCH_COUNT_DISABLE;
+    ENHTIM_InitStruct->ENHTIM_LatchCountTrigger[1]  = ENHTIM_LATCH_TRIGGER_RISING_EDGE;
+    ENHTIM_InitStruct->ENHTIM_LatchCountEn[2]       = ENHTIM_LATCH_COUNT_DISABLE;
+    ENHTIM_InitStruct->ENHTIM_LatchCountTrigger[2]  = ENHTIM_LATCH_TRIGGER_RISING_EDGE;
+    ENHTIM_InitStruct->ENHTIM_LatchCount2Thd        = 3;
+    ENHTIM_InitStruct->ENHTIM_LatchTriggerPad       = P0_0;
+    ENHTIM_InitStruct->ENHTIM_TimerGPIOTriggerEn    = DISABLE;
+    ENHTIM_InitStruct->ENHTIM_BTGPIOTriggerEn       = DISABLE;
+    ENHTIM_InitStruct->ENHTIM_MaxCount              = 0xFFFFFFFE;//range 0x1~0xFFFFFFFE
+    ENHTIM_InitStruct->ENHTIM_CCValue               = 0x0;
+
+    ENHTIM_InitStruct->ENHTIM_PWMDeadZoneClockSource    = ENHTIM_PWM_DZCLKSRCE_32K;
+    ENHTIM_InitStruct->ENHTIM_PWMDeadZoneEn             = ENHTIM_PWM_DEADZONE_DISABLE;
+    ENHTIM_InitStruct->ENHTIM_PWMStopStateP         = ENHTIM_PWM_STOP_AT_HIGH;
+    ENHTIM_InitStruct->ENHTIM_PWMStopStateN         = ENHTIM_PWM_STOP_AT_LOW;
+    ENHTIM_InitStruct->ENHTIM_DeadZoneSize          = 0xFF;/*!< range 0x1 ~ 0xFF */
+}
+
+/**
+  * @brief  Enables or disables the specified ENHTIM peripheral.
+  * @param  ENHTIMx: Where x can be 0 to 1 to select the ENHTIMx peripheral.
+  * @param  NewState: New state of the ENHTIMx peripheral.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retutn None.
+  */
+void ENHTIM_Cmd(ENHTIM_TypeDef *ENHTIMx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_ENHTIM_ALL_PERIPH(ENHTIMx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    uint32_t enhtim_id = ((uint32_t)ENHTIMx - (uint32_t)ENH_TIM0) / 0x24;
+    uint32_t current_clock_reg = CLK_SOURCE_REG_2;
+    uint32_t clock_mask = (enhtim_id == 0) ? (0x07 << 25) : (0x07 << 28);
+
+    if (NewState != DISABLE)
+    {
+        /* Enable the ENHTIM Counter */
+        ENH_TIM_SHARE->CMD |= BIT(enhtim_id);
+    }
+    else
+    {
+        /* Disable the ENHTIM Counter */
+        ENH_TIM_SHARE->CMD &= ~(BIT(enhtim_id));
+
+        if ((current_clock_reg & clock_mask) != 0)
+        {
+            uint32_t timer_setting = (ENHTIMx->CR) & 0x0F; /* Include timer mode, pwm enable, pwm polarity */
+            uint32_t timeout_int = (ENH_TIM_SHARE->INT_CMD) & BIT(enhtim_id);
+            uint32_t latch_int_full = (ENH_TIM_SHARE->LC_INT_CMD0) & BIT(24 + enhtim_id);
+            uint32_t latch_int_th = (ENH_TIM_SHARE->LC_INT_CMD2) & BIT(24 + enhtim_id);
+
+            /* Pre disable interrupt to avoid trigger interrupt.
+            * - Disable the ENHTIM PWM
+            * - Disable the ENHTIM timeout interrupt
+            * - Disable the ENHTIM latch count interrupt
+            * - Set ENHTIM mode to free-run mode
+            */
+            ENHTIMx->CR &= ~ENHTIM_PWM_ENABLE;
+            ENH_TIM_SHARE->INT_CMD &= ~BIT(enhtim_id);
+            ENH_TIM_SHARE->LC_INT_CMD0 &= ~BIT(enhtim_id + 24);
+            ENH_TIM_SHARE->LC_INT_CMD2 &= ~BIT(enhtim_id + 24);
+            ENHTIMx->CR &= ~0x03;
+
+            /* Set ENHTIM clock divider to TIM_CLOCK_DIV_1 */
+            E_TIM_NUM timx = (enhtim_id == 0) ? TIMENH_CLK_0 : TIMENH_CLK_1;
+            RCC_TIMClkDivConfig(timx, TIM_CLOCK_DIV_1);
+
+            /* Enable the ENHTIM Counter for above settings succsivae */
+            ENH_TIM_SHARE->CMD |= BIT(enhtim_id);
+
+            /* Disable the ENHTIM Counter */
+            ENH_TIM_SHARE->CMD &= ~BIT(enhtim_id);
+
+            /* Restore ENHTIM for above settings
+            * - Restore ENHTIM clock divider
+            * - Restore ENHTIM PWM settings
+            * - Restore ENHTIM timer mode
+            * - Restore ENHTIM timeout interrupt
+            * - Restore ENHTIM latch count interrupt
+            */
+            CLK_SOURCE_REG_2 = current_clock_reg;
+            ENHTIMx->CR |= timer_setting;
+            ENH_TIM_SHARE->INT_CMD |= timeout_int;
+            ENH_TIM_SHARE->LC_INT_CMD0 |= latch_int_full;
+            ENH_TIM_SHARE->LC_INT_CMD2 |= latch_int_th;
+        }
+    }
+}
+
+
+/**
+  * @brief  Mask or unmask the latch count2 fifo interrupt.
+  * @param  ENHTIMx: Where x can be 0 to 1 to select the ENHTIMx peripheral.
+  * @param  NewState: New state of the specified ENHTIMx peripheral latch count2 fifo interrupt.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval None.
+  */
+void ENHTIM_LCFIFOMaskConfig(ENHTIM_TypeDef *ENHTIMx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_ENHTIM_ALL_PERIPH(ENHTIMx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    uint32_t enhtim_id = ((uint32_t)ENHTIMx - (uint32_t)ENH_TIM0) / 0X24;
+
+    if (NewState != DISABLE)
+    {
+        ENH_TIM_SHARE->INT_CMD |= BIT(24) << enhtim_id;
+    }
+    else
+    {
+        ENH_TIM_SHARE->INT_CMD &= ~(BIT(24) << enhtim_id);
+    }
+}
+
+/**
+  * @brief  Enables or disables ENHTIMx interrupt.
+  * @param  ENHTIMx: Where x can be 0 to 1 to select the ENHTIMx peripheral.
+ * \param[in] ENHTIM_INT: Specifies the ENHTIMx interrupt source which to be enabled or disabled.
+ *            This parameter can be one of the following values:
+ *            \arg ENHTIM_INT_TIM: Enhance Timer interrupt source.
+ *            \arg ENHTIM_INT_LATCH_CNT2_FIFO_FULL: Enhance Timer latch count0 interrupt source.
+ *            \arg ENHTIM_INT_LATCH_CNT2_FIFO_THD: Enhance Timer latch count2 interrupt source.
+  * @param  NewState: New state of the ENHTIMx peripheral.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @return None.
+  */
+void ENHTIM_INTConfig(ENHTIM_TypeDef *ENHTIMx, uint8_t ENHTIM_INT, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_ENHTIM_ALL_PERIPH(ENHTIMx));
+    assert_param(IS_ENHTIM_INT(ENHTIM_INT));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    uint32_t enhtim_id = ((uint32_t)ENHTIMx - (uint32_t)ENH_TIM0) / 0X24;
+
+    if (NewState != DISABLE)
+    {
+        /* Enable the ENHTIM Interrupt */
+        if (ENHTIM_INT & 0x40)
+        {
+            *((volatile uint32_t *)(&(ENH_TIM_SHARE->LC_INT_CMD0) + (ENHTIM_INT & 0xF))) |= BIT(
+                    24) << enhtim_id;
+        }
+        else
+        {
+            ENH_TIM_SHARE->INT_CMD |= BIT(enhtim_id);
+        }
+    }
+    else
+    {
+        /* Disable the ENHTIM Interrupt */
+        if (ENHTIM_INT & 0x40)
+        {
+            *((volatile uint32_t *)(&(ENH_TIM_SHARE->LC_INT_CMD0) + (ENHTIM_INT & 0xF))) &= ~(BIT(
+                    24) << enhtim_id);;
+        }
+        else
+        {
+            ENH_TIM_SHARE->INT_CMD &= ~BIT(enhtim_id);
+        }
+    }
+}
+
+/**
+ * \brief     Read ENHTIMx latch counter2 fifo data.
+ * \param[in] ENHTIMx: Where x can be 0 to 1 to select the ENHTIMx peripheral.
+ * \param[in] length: Latch count2 fifo length, max 4.
+ * \pBuf[out] pBuf: FIFO data out buffer.
+ * \return    None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void enhance_timer_demo(void)
+ * {
+ *     uint8_t length = ENHTIM_GetLatchCount2FIFOLength(ENH_TIM0);
+ * }
+ * \endcode
+ */
+void ENHTIM_ReadLatchCount2FIFO(ENHTIM_TypeDef *ENHTIMx, uint32_t *pBuf, uint8_t length)
+{
+    /* Check the parameters */
+    assert_param(IS_ENHTIM_ALL_PERIPH(ENHTIMx));
+
+    if ((pBuf == 0) || (length > 4))
+    {
+        return;
+    }
+
+    for (uint8_t i = 0; i < length; i++)
+    {
+        pBuf[i] = ENHTIMx->LATCH_CNT2;
+    }
+}
+
+/**
+ * \brief     Check whether the ENHTIM latch count2 fifo has data or not.
+ * \param[in] ENHTIMx: Where x can be 0 to 1 to select the ENHTIMx peripheral.
+ * \return    The new state of the specified ENHTIMx peripheral
+ *            latch count2 fifo (SET or RESET).
+ */
+ITStatus ENHTIM_GetLCFIFOStatus(ENHTIM_TypeDef *ENHTIMx)
+{
+    /* Check the parameters */
+    assert_param(IS_ENHTIM_ALL_PERIPH(ENHTIMx));
+
+    uint32_t enhtim_id = ((uint32_t)ENHTIMx - (uint32_t)ENH_TIM0) / 0X24;
+    ITStatus itstatus = RESET;
+
+    if (ENH_TIM_SHARE->INT_SR & ((BIT(24) << enhtim_id)))
+    {
+        itstatus = SET;
+    }
+
+    return itstatus;
+}
+
+/**
+ * \brief     Check whether the ENHTIM latch count2 fifo interrupt has occurred or not.
+ * \param[in] ENHTIMx: Where x can be 0 to 1 to select the ENHTIMx peripheral.
+ * \return    The new state of the specified ENHTIMx peripheral
+ *            latch count2 fifo interrupt(SET or RESET).
+ */
+ITStatus ENHTIM_GetLCFIFOMaskStatus(ENHTIM_TypeDef *ENHTIMx)
+{
+    /* Check the parameters */
+    assert_param(IS_ENHTIM_ALL_PERIPH(ENHTIMx));
+
+    uint32_t enhtim_id = ((uint32_t)ENHTIMx - (uint32_t)ENH_TIM0) / 0X24;
+    ITStatus itstatus = RESET;
+
+    if (ENH_TIM_SHARE->MASK_INT_SR & ((BIT(24) << enhtim_id)))
+    {
+        itstatus = SET;
+    }
+
+    return itstatus;
+}
+
+/**
+ * \brief     Check whether the ENHTIM interrupt has occurred or not.
+ * \param[in] ENHTIMx: Where x can be 0 to 1 to select the ENHTIMx peripheral.
+ * \param[in] ENHTIM_INT: Specifies the ENHTIMx interrupt source which to be enabled or disabled.
+ *            This parameter can be one of the following values:
+ *            \arg ENHTIM_INT_TIM: Enhance Timer interrupt source.
+ *            \arg ENHTIM_INT_LATCH_CNT2_FIFO_FULL: Enhance Timer latch count2 fifo full interrupt source.
+// *            \arg ENHTIM_INT_LATCH_CNT2_FIFO_EMPTY: Enhance Timer latch count2 fifo empty interrupt source.
+ *            \arg ENHTIM_INT_LATCH_CNT2_FIFO_THD: Enhance Timer latch count2 fifo threshold interrupt source.
+ * \return    The new state of the ENHTIM_INT(SET or RESET).
+ */
+ITStatus ENHTIM_GetINTStatus(ENHTIM_TypeDef *ENHTIMx, uint8_t ENHTIM_INT)
+{
+    /* Check the parameters */
+    assert_param(IS_ENHTIM_ALL_PERIPH(ENHTIMx));
+    assert_param(IS_ENHTIM_INT(INT));
+
+    uint32_t enhtim_id = ((uint32_t)ENHTIMx - (uint32_t)ENH_TIM0) / 0X24;
+    ITStatus itstatus = RESET;
+
+    if (ENHTIM_INT == ENHTIM_INT_TIM)
+    {
+        itstatus = (ITStatus)((ENH_TIM_SHARE->INT_SR) >> (enhtim_id));
+    }
+    else if (ENHTIM_INT == ENHTIM_INT_LATCH_CNT2_FIFO_FULL)
+    {
+        itstatus = (ITStatus)(((ENH_TIM_SHARE->FIFO_SR2) >> (16 + enhtim_id * 2)) & 0x01);
+    }
+    else if (ENHTIM_INT == ENHTIM_INT_LATCH_CNT2_FIFO_EMPTY)
+    {
+        itstatus = (ITStatus)(((ENH_TIM_SHARE->FIFO_SR2) >> (17 + enhtim_id * 2)) & 0x01);
+    }
+    else if (ENHTIM_INT == ENHTIM_INT_LATCH_CNT2_FIFO_THD)
+    {
+        itstatus = (ITStatus)(((ENH_TIM_SHARE->FIFO_SR0) >> (16 + enhtim_id)) & 0x01);
+    }
+
+    return itstatus;
+}
+
+/**
+ * \brief     Clear ENHTIM interrupt.
+ * \param[in] ENHTIMx: Where x can be 0 to 1 to select the ENHTIMx peripheral.
+ * \param[in] ENHTIM_INT: Specifies the ENHTIMx interrupt source which to be enabled or disabled.
+ *            This parameter can be one of the following values:
+ *            \arg ENHTIM_INT_TIM: Enhance Timer interrupt source.
+ *            \arg ENHTIM_INT_LATCH_CNT2_FIFO_FULL: Enhance Timer latch count2 fifo full interrupt source.
+ *            \arg ENHTIM_INT_LATCH_CNT2_FIFO_THD: Enhance Timer latch count2 fifo threshold interrupt source.
+ * \return    None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void enhance_timer_demo(void)
+ * {
+ *     ENHTIM_ClearINTPendingBit(ENH_TIM0, ENHTIM_INT_TIM);
+ * }
+ * \endcode
+ */
+void ENHTIM_ClearINTPendingBit(ENHTIM_TypeDef *ENHTIMx, uint8_t ENHTIM_INT)
+{
+    /* Check the parameters */
+    assert_param(IS_ENHTIM_ALL_PERIPH(ENHTIMx));
+
+    uint32_t enhtim_id = ((uint32_t)ENHTIMx - (uint32_t)ENH_TIM0) / 0X24;
+
+    /* Clear the IT */
+    if (ENHTIM_INT == ENHTIM_INT_TIM)
+    {
+        ENH_TIM_SHARE->INT_SR |= BIT(enhtim_id);
+    }
+    else if (ENHTIM_INT == ENHTIM_INT_LATCH_CNT2_FIFO_FULL)
+    {
+        ENH_TIM_SHARE->FIFO_SR2 |= BIT(16 + enhtim_id * 2);
+    }
+    else if (ENHTIM_INT == ENHTIM_INT_LATCH_CNT2_FIFO_EMPTY)
+    {
+        ENH_TIM_SHARE->FIFO_SR2 |= BIT(17 + enhtim_id * 2);
+    }
+    else if (ENHTIM_INT == ENHTIM_INT_LATCH_CNT2_FIFO_THD)
+    {
+        ENH_TIM_SHARE->FIFO_SR0 |= BIT(16 + enhtim_id);
+    }
+}
+
+/**
+ * \brief   Enable or disable bypass dead zone function of PWM complementary output.
+ *          After enabling, PWM_P = ~PWM_N.
+ * \param[in] ENHTIMx: ENHTIM0.
+ * \param[in] NewState: New state of the ENHTIMx peripheral.
+ *      \ref DISABLE: Disable bypass dead zone function.
+ *      \ref ENABLE: Enable bypass dead zone function.
+ * \note    To use this function, need to configure the corresponding enhtimer.
+ *          ENHTIMx can be only ENHTIM0.
+ * \return  None.
+ */
+void ENHTIM_PWMDZBypassCmd(ENHTIM_TypeDef *ENHTIMx, FunctionalState NewState)
+{
+    /* Check the parameters. */
+    assert_param(IS_ENHTIM_ALL_PERIPH(ENHTIMx));
+
+    if (NewState != DISABLE)
+    {
+        /* Enable bypass dead zone function. */
+        ENHTIM_PWM_DEADZONE_CR |= BIT13;
+    }
+    else
+    {
+        /* Disable bypass dead zone function. */
+        ENHTIM_PWM_DEADZONE_CR &= (~BIT13);
+    }
+}
+
+/**
+  * \brief  Store ENHTIM register values when system enter DLPS.
+  * \param  PeriReg: Specifies to select the ENHTIM peripheral.
+  * \param  StoreBuf: Store buffer to store ENHTIM register data.
+  * \return None.
+  */
+DATA_RAM_FUNCTION
+void ENHTIM_DLPSEnter(void *PeriReg, void *StoreBuf)
+{
+    ENHTIM_TypeDef *ENHTIMx = (ENHTIM_TypeDef *)PeriReg;
+    ENHTIMStoreReg_TypeDef *store_buf = (ENHTIMStoreReg_TypeDef *)StoreBuf;
+
+    store_buf->enhtim_reg[0] = ENHTIMx->CR;
+    store_buf->enhtim_reg[1] = ENHTIMx->MAX_CNT;
+    store_buf->enhtim_reg[2] = ENHTIMx->CCR;
+    store_buf->enhtim_reg[3] = ENHTIMx->CCR_FIFO;
+}
+
+/**
+  * \brief  Store ENHTIM share register values when system enter DLPS.
+  * \param  PeriReg: Specifies to select the ENHTIM share peripheral.
+  * \param  StoreBuf: Store buffer to store ENHTIM share register data.
+  * \return None.
+  */
+DATA_RAM_FUNCTION
+void ENHTIMSHARE_DLPSEnter(void *StoreBuf)
+{
+    ENHTIMShareStoreReg_TypeDef *store_buf = (ENHTIMShareStoreReg_TypeDef *)StoreBuf;
+
+    RCC_PeriphClockCmd(APBPeriph_ENHTIMER, APBPeriph_ENHTIMER_CLOCK, ENABLE);
+
+    store_buf->enhtimshare_reg[0]  = ENH_TIM_SHARE->FIFO_CLR;
+    store_buf->enhtimshare_reg[1]  = ENH_TIM_SHARE->CMD;
+    store_buf->enhtimshare_reg[2]  = ENH_TIM_SHARE->INT_CMD;
+    store_buf->enhtimshare_reg[3]  = ENH_TIM_SHARE->INT_SR;
+    store_buf->enhtimshare_reg[4]  = ENH_TIM_SHARE->LC_INT_CMD0;
+    store_buf->enhtimshare_reg[5]  = ENH_TIM_SHARE->LC_INT_CMD2;
+    store_buf->enhtimshare_reg[6]  = ENH_TIM_SHARE->LC_FIFO_LEVEL0;
+    store_buf->enhtimshare_reg[7]  = ENH_TIM_SHARE->LC_FIFO_LEVEL1;
+    store_buf->enhtimshare_reg[8]  = *((volatile uint32_t *)0x4000035CUL);
+    store_buf->enhtimshare_reg[9]  = *((volatile uint32_t *)0x40000360UL);
+    store_buf->enhtimshare_reg[10] = *((volatile uint32_t *)0x40000368UL);
+    store_buf->enhtimshare_reg[11] = ENHTIM_PWM_DEADZONE_CR;
+}
+
+/**
+  * \brief  Restore ENHTIM register values when system exit DLPS.
+  * \param  PeriReg: Specifies to select the ENHTIM peripheral.
+  * \param  StoreBuf: Restore buffer to restore ENHTIM register data.
+  * \return None.
+  */
+DATA_RAM_FUNCTION
+void ENHTIM_DLPSExit(void *PeriReg, void *StoreBuf)
+{
+    ENHTIM_TypeDef *ENHTIMx = (ENHTIM_TypeDef *)PeriReg;
+    ENHTIMStoreReg_TypeDef *store_buf = (ENHTIMStoreReg_TypeDef *)StoreBuf;
+
+    ENHTIMx->CR             = store_buf->enhtim_reg[0];
+    ENHTIMx->MAX_CNT        = store_buf->enhtim_reg[1];
+    ENHTIMx->CCR            = store_buf->enhtim_reg[2];
+    ENHTIMx->CCR_FIFO       = store_buf->enhtim_reg[3];
+}
+
+/**
+  * \brief  Restore ENHTIM share register values when system exit DLPS.
+  * \param  PeriReg: Specifies to select the ENHTIM share peripheral.
+  * \param  StoreBuf: Restore buffer to restore ENHTIM share register data.
+  * \return None.
+  */
+DATA_RAM_FUNCTION
+void ENHTIMSHARE_DLPSExit(void *StoreBuf)
+{
+    ENHTIMShareStoreReg_TypeDef *store_buf = (ENHTIMShareStoreReg_TypeDef *)StoreBuf;
+
+    RCC_PeriphClockCmd(APBPeriph_ENHTIMER, APBPeriph_ENHTIMER_CLOCK, ENABLE);
+
+    *((volatile uint32_t *)0x4000035CUL) = store_buf->enhtimshare_reg[8];
+    *((volatile uint32_t *)0x40000360UL) = store_buf->enhtimshare_reg[9];
+    *((volatile uint32_t *)0x40000368UL) = store_buf->enhtimshare_reg[10];
+    ENH_TIM_SHARE->FIFO_CLR              = store_buf->enhtimshare_reg[0];
+    ENH_TIM_SHARE->CMD                   = store_buf->enhtimshare_reg[1] ;
+    ENH_TIM_SHARE->INT_CMD               = store_buf->enhtimshare_reg[2];
+    ENH_TIM_SHARE->INT_SR                = store_buf->enhtimshare_reg[3];
+    ENH_TIM_SHARE->LC_INT_CMD0           = store_buf->enhtimshare_reg[4];
+    ENH_TIM_SHARE->LC_INT_CMD2           = store_buf->enhtimshare_reg[5];
+    ENH_TIM_SHARE->LC_FIFO_LEVEL0        = store_buf->enhtimshare_reg[6];
+    ENH_TIM_SHARE->LC_FIFO_LEVEL1        = store_buf->enhtimshare_reg[7];
+    ENHTIM_PWM_DEADZONE_CR               = store_buf->enhtimshare_reg[11];
+}
+
+
+
diff --git a/bee/drivers/timer/src/device/rtl8752h/rtl876x_enh_tim.h b/bee/drivers/timer/src/device/rtl8752h/rtl876x_enh_tim.h
new file mode 100644
index 00000000..6596470f
--- /dev/null
+++ b/bee/drivers/timer/src/device/rtl8752h/rtl876x_enh_tim.h
@@ -0,0 +1,872 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _RTL876X_ENH_TIM_H_
+#define _RTL876X_ENH_TIM_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/**
+ * \addtogroup  IO          Peripheral Drivers
+ * \defgroup    ENHTIM      ENHTIM
+ * \brief       Manage the ENHTIM peripheral functions.
+ *
+ * \ingroup     IO
+ */
+
+/*============================================================================*
+ *                         Includes
+ *============================================================================*/
+#include "rtl876x.h"
+
+/*============================================================================*
+ *                         Constants
+ *============================================================================*/
+
+/* ENHTIM private defines */
+#define ENHTIM_PWM_DEADZONE_CR  *((volatile uint32_t *)0x40000368UL)
+#define ENHTIM_LATCH_COUNT_CR   *((volatile uint32_t *)0x40006028UL)
+
+/**
+ * \defgroup    ENHTIM_Exported_Constants  ENHTIM Exported Constants
+ *
+ * \ingroup     ENHTIM
+ */
+#define IS_ENHTIM_ALL_PERIPH(PERIPH) (((PERIPH) == ENH_TIM0) || \
+                                      ((PERIPH) == ENH_TIM1))
+
+/**
+ * \defgroup    ENHTIM_Clock_Source ENHTIM Clock Source
+ * \{
+ * \ingroup     ENHTIM_Exported_Constants
+ */
+#define ENHTIM_TIMER_TOGGLE_OUTPUT          ((uint16_t)0x1)
+#define ENHTIM_DIVIDER_CLOCK                ((uint16_t)0x0)
+
+#define IS_ENHTIM_CLOCK_SOURCE(src) (((src) == ENHTIM_TIMER_TOGGLE_OUTPUT) || \
+                                     ((src) == ENHTIM_DIVIDER_CLOCK))
+/** \} */
+
+/**
+ * \defgroup    ENHTIM_Latch_En ENHTIM Latch Count Enable
+ * \{
+ * \ingroup     ENHTIM_Exported_Constants
+ */
+#define ENHTIM_LATCH_COUNT_ENABLE          ((uint16_t)0x1)
+#define ENHTIM_LATCH_COUNT_DISABLE         ((uint16_t)0x0)
+
+#define IS_ENHTIM_LATCH_COUNT_En(mode) (((mode) == ENHTIM_LATCH_COUNT_ENABLE) || \
+                                        ((mode) == ENHTIM_LATCH_COUNT_DISABLE))
+/** \} */
+
+/**
+ * \defgroup    ENHTIM_Latch_Trigger_Mode ENHTIM Latch Count Trigger Mode
+ * \{
+ * \ingroup     ENHTIM_Exported_Constants
+ */
+#define ENHTIM_LATCH_TRIGGER_BOTH_EDGE      ((uint16_t)0x02)
+#define ENHTIM_LATCH_TRIGGER_FALLING_EDGE   ((uint16_t)0x01)
+#define ENHTIM_LATCH_TRIGGER_RISING_EDGE    ((uint16_t)0x00)
+
+#define IS_ENHTIM_Latch_Trigger_Mode(mode) (((mode) == ENHTIM_LATCH_TRIGGER_BOTH_EDGE) || \
+                                            ((mode) == ENHTIM_LATCH_TRIGGER_FALLING_EDGE) || \
+                                            ((mode) == ENHTIM_LATCH_TRIGGER_RISING_EDGE))
+/** \} */
+
+/**
+ * \defgroup    ENHTIM_PWM_En ENHTIM PWM Output Enable
+ * \{
+ * \ingroup     ENHTIM_Exported_Constants
+ */
+#define ENHTIM_PWM_ENABLE                   ((uint16_t)0x08)
+#define ENHTIM_PWM_DISABLE                  ((uint16_t)0x00)
+
+#define IS_ENHTIM_PWM_En(mode) (((mode) == ENHTIM_PWM_ENABLE) || \
+                                ((mode) == ENHTIM_PWM_DISABLE))
+/** \} */
+
+/**
+ * \defgroup    ENHTIM_PWM_Polarity ENHTIM PWM Polarity
+ * \{
+ * \ingroup     ENHTIM_Exported_Constants
+ */
+#define ENHTIM_PWM_START_WITH_HIGH          ((uint16_t)0x04)
+#define ENHTIM_PWM_START_WITH_LOW           ((uint16_t)0x00)
+
+#define IS_ENHTIM_PWM_POLARITY(pola) (((pola) == ENHTIM_PWM_START_WITH_HIGH) || \
+                                      ((pola) == ENHTIM_PWM_START_WITH_LOW))
+/** \} */
+
+/**
+ * \defgroup    ENHTIM_Mode ENHTIM Mode
+ * \{
+ * \ingroup     ENHTIM_Exported_Constants
+ */
+#define ENHTIM_MODE_PWM_MANUAL              ((uint16_t)0x02) /*!< User define pwm manual mode. */
+#define ENHTIM_MODE_PWM_AUTO                ((uint16_t)0x01) /*!< User define pwm auto mode. */
+#define ENHTIM_MODE_FreeRun                 ((uint16_t)0x00) /*!< Freerun mode. */
+
+#define IS_ENHTIM_MODE(mode) (((mode) == ENHTIM_MODE_PWM_MANUAL) || \
+                              ((mode) == ENHTIM_MODE_PWM_AUTO) || \
+                              ((mode) == ENHTIM_MODE_FreeRun))
+/** \} */
+
+/**
+ * \defgroup    ENHTIM_Interrupts_Definition ENHTIM Interrupts Definition
+ * \{
+ * \ingroup     ENHTIM_Exported_Constants
+ */
+#define ENHTIM_INT_TIM                      (0x00)
+#define ENHTIM_INT_LATCH_CNT2_FIFO_EMPTY    (0x01)
+#define ENHTIM_INT_LATCH_CNT2_FIFO_FULL     (0x40)
+#define ENHTIM_INT_LATCH_CNT2_FIFO_THD      (0x42)
+
+#define IS_ENHTIM_INT(INT) (((INT) == ENHTIM_INT_TIM) || \
+                            ((INT) == ENHTIM_INT_LATCH_CNT2_FIFO_FULL) || \
+                            ((INT) == ENHTIM_INT_LATCH_CNT2_FIFO_THD))
+/** \} */
+
+/**
+ * \defgroup    ENHTIM_FIFO_Flag ENHTIM FIFO Flag
+ * \{
+ * \ingroup     ENHTIM_Exported_Constants
+ */
+#define ENHTIM_FLAG_TIM1_LC_FIFO_EMPTY          BIT(19)
+#define ENHTIM_FLAG_TIM0_LC_FIFO_EMPTY          BIT(17)
+#define ENHTIM_FLAG_TIM1_CCR_FIFO_EMPTY         BIT(3)
+#define ENHTIM_FLAG_TIM1_CCR_FIFO_FULL          BIT(2)
+#define ENHTIM_FLAG_TIM0_CCR_FIFO_EMPTY         BIT(1)
+#define ENHTIM_FLAG_TIM0_CCR_FIFO_FULL          BIT(0)
+
+#define IS_ENHTIM_CCR_FIFO_FLAG(flag) (((flag) == ENHTIM_FLAG_TIM1_LC_FIFO_EMPTY) || \
+                                       ((flag) == ENHTIM_FLAG_TIM0_LC_FIFO_EMPTY) || \
+                                       ((flag) == ENHTIM_FLAG_TIM1_CCR_FIFO_EMPTY) || \
+                                       ((flag) == ENHTIM_FLAG_TIM1_CCR_FIFO_FULL) || \
+                                       ((flag) == ENHTIM_FLAG_TIM0_CCR_FIFO_EMPTY) || \
+                                       ((flag) == ENHTIM_FLAG_TIM0_CCR_FIFO_FULL))
+/** \} */
+
+/**
+ * \defgroup    ENHTIM_PWM_DeadZone_En ENHTIM PWM DeadZone Enable
+ * \{
+ * \ingroup     ENHTIM_Exported_Constants
+ */
+#define ENHTIM_PWM_DEADZONE_ENABLE          ((uint16_t)0x1)
+#define ENHTIM_PWM_DEADZONE_DISABLE         ((uint16_t)0x0)
+
+#define IS_ENHTIM_PWM_DEADZONE_EN(mode) (((mode) == ENHTIM_PWM_DEADZONE_ENABLE) || \
+                                         ((mode) == ENHTIM_PWM_DEADZONE_DISABLE))
+/** \} */
+
+/**
+ * \defgroup    ENHTIM_PWM_DeadZone_Clock ENHTIM PWM DeadZone Clock
+ * \{
+ * \ingroup     ENHTIM_Exported_Constants
+ */
+#define ENHTIM_PWM_DZCLKSRCE_ENHTIM         ((uint32_t)0x80000)
+#define ENHTIM_PWM_DZCLKSRCE_5M             ((uint32_t)0x10000)
+#define ENHTIM_PWM_DZCLKSRCE_32K            ((uint32_t)0x0)
+
+#define IS_ENHTIM_PWM_DEADZONE_Clock(mode) (((mode) == ENHTIM_PWM_DEADZONE_ENABLE) || \
+                                            ((mode) == ENHTIM_PWM_DEADZONE_DISABLE))
+/** \} */
+
+/**
+ * \defgroup    ENHTIM_PWM_DeadZone_Stop_State ENHTIM PWM DeadZone Stop State
+ * \{
+ * \ingroup     ENHTIM_Exported_Constants
+ */
+#define ENHTIM_PWM_STOP_AT_HIGH             ((uint16_t)0x1)
+#define ENHTIM_PWM_STOP_AT_LOW              ((uint16_t)0x0)
+/** \} */
+
+/**
+ * \defgroup    ENHTIM_FIFO_Clear_Flag ENHTIM FIFO Clear Flag
+ * \{
+ * \ingroup     ENHTIM_Exported_Constants
+ */
+#define ENHTIM_FIFO_CLR_CCR                 (0)
+#define ENHTIM_FIFO_CLR_CNT2                (24)
+/** \} */
+
+/**
+ * \defgroup    ENHTIM_Clock_Divider ENHTIM Clock Divider
+ * \{
+ * \ingroup     ENHTIM_Exported_Constants
+ */
+typedef enum
+{
+    ENHTIM_CLOCK_DIVIDER_1   = 0x00,
+    ENHTIM_CLOCK_DIVIDER_125 = 0x03,
+    ENHTIM_CLOCK_DIVIDER_2   = 0x04,
+    ENHTIM_CLOCK_DIVIDER_4   = 0x05,
+    ENHTIM_CLOCK_DIVIDER_8   = 0x06,
+    ENHTIM_CLOCK_DIVIDER_40  = 0x07,
+} E_ENHTIM_CLKDIV;
+/** \} */
+
+/**
+ * \defgroup    ENHTIM_Latch_Counter ENHTIM Latch Counter
+ * \{
+ * \ingroup     ENHTIM_Exported_Constants
+ */
+typedef enum
+{
+    LATCH_CNT_0 = 0,
+    LATCH_CNT_1 = 1,
+    LATCH_CNT_2 = 2,
+} E_ENHTIM_LATCHCNT;
+/** \} */
+
+/** End of ENHTIM_Exported_Constants
+  * \}
+  */
+
+/*============================================================================*
+ *                         Types
+ *============================================================================*/
+/**
+ * \defgroup    ENHTIM_Exported_Types ENHTIM Exported Types
+ * \{
+ * \ingroup     ENHTIM
+ */
+
+/**
+ * \brief       ENHTIM init structure definition
+ *
+ * \ingroup     ENHTIM_Exported_Types
+ */
+typedef struct
+{
+    uint16_t ENHTIM_ClockSource;            /*!< <b>Deprecated</b> use RCC instead.*/
+    E_ENHTIM_CLKDIV ENHTIM_ClockDiv;        /*!< Specify the clock source div.
+                                                 This parameter can be a value of \ref ENHTIM_Clock_Divider.*/
+    uint16_t ENHTIM_Mode;                   /*!< Specify the counter mode.
+                                                 This parameter can be a value of \ref ENHTIM_Mode. */
+    uint16_t ENHTIM_PWMOutputEn;            /*!< Enable or disable the PWM mode.
+                                                 This parameter can be a value of \ref ENHTIM_PWM_En. */
+    uint16_t ENHTIM_PWMStartPolarity;       /*!< Specify the PWM start polarity.
+                                                 This parameter can be a value of \ref ENHTIM_PWM_Polarity. */
+    uint16_t ENHTIM_LatchCountEn[3];        /*!< Enable or disable Enhtimer Latch_cnt.
+                                                 This parameter can be a value of DISABLE or ENABLE. */
+    uint16_t ENHTIM_LatchCountTrigger[3];   /*!< Specify Enhtimer counter latch trigger mode.
+                                                 This parameter can be a value of \ref ENHTIM_Latch_Trigger_Mode. */
+    uint16_t ENHTIM_LatchCount2Thd;         /*!< Specify Enhtimer latched counter fifo threshold.
+                                                 This parameter can be a value of 0~4. */
+    uint16_t ENHTIM_LatchTriggerPad;        /*!< Specify the Enhtimer latch trigger Pad.
+                                                 This parameter can be a value of P0_0 to P5_2. */
+    uint16_t ENHTIM_TimerGPIOTriggerEn;     /*!< Enable or disable acc latch.
+                                                 This parameter can be a value of DISABLE or ENABLE. */
+    uint16_t ENHTIM_BTGPIOTriggerEn;        /*!< Enable or disable BT latch.
+                                                 This parameter can be a value of DISABLE or ENABLE. */
+    uint32_t ENHTIM_MaxCount;               /*!< Specify the Enhtimer max counter value for user-defined PWM mode.
+                                                 This parameter legal value range is from 0 ~ 2^32-2. */
+    uint32_t ENHTIM_CCValue;                /*!< Specify the Enhtimer capture/compare value for user-defined PWM manual mode.
+                                                 This parameter legal value range is from 0 ~ 2^32-2.*/
+    uint16_t ENHTIM_PWMDeadZoneEn;          /*!< Enable or disable PWM Deadzone, pwm0_pn: timer2, pwm1_pn:timer3.
+                                                 This parameter can be a value of ENABLE or DISABLE. */
+    uint32_t ENHTIM_PWMDeadZoneClockSource; /*!< Specify the pwm deadzone clock source.
+                                                 This parameter can be a value of \ref ENHTIM_PWM_DeadZone_Clock. */
+    uint16_t ENHTIM_PWMStopStateP;          /*!< Specify the PWM P stop state.
+                                                 This parameter can be a value of \ref PWMDeadZone_Stop_State. */
+    uint16_t ENHTIM_PWMStopStateN;          /*!< Specify the PWM N stop state.
+                                                 This parameter can be a value of \ref PWMDeadZone_Stop_State. */
+    uint32_t ENHTIM_DeadZoneSize;           /*!< Specify the size of deadzone time, deadzone Time = ENHTIM_DeadZoneSize/32000(internal clock src) or 32768(external clock src).
+                                                 This parameter must range 0x1 ~ 0xFF. */
+} ENHTIM_InitTypeDef;
+
+/** End of ENHTIM_Exported_Types
+  * \}
+  */
+
+/*============================================================================*
+ *                         Functions
+ *============================================================================*/
+/**
+ * \defgroup    ENHTIM_Exported_Functions  ENHTIM Exported Functions
+ * \{
+ * \ingroup     ENHTIM
+ */
+
+/**
+ * \brief     Initialize the ENHTIMx unit peripheral according to
+ *            the specified parameters in ENHTIM_TimeBaseInitStruct.
+ * \param[in] ENHTIMx: Where x can be 0 to 1 to select the ENHTIM peripheral.
+ * \param[in] ENHTIM_TimeBaseInitStruct: pointer to a ENHTIM_InitTypeDef structure
+  *           that contains the configuration information for the specified ENHTIM peripheral.
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_enhance_timer_init(void)
+ * {
+ *     RCC_PeriphClockCmd(APBPeriph_ENHTIMER, APBPeriph_ENHTIMER_CLOCK, ENABLE);
+ *
+ *     ENHTIM_InitTypeDef ENHTIM_InitStruct;
+ *     ENHTIM_StructInit(&ENHTIM_InitStruct);
+ *
+ *     ENHTIM_InitStruct.ENHTIM_PWMOutputEn = ENHTIM_PWM_DISABLE;
+ *     ENHTIM_InitStruct.ENHTIM_MaxCount = 4000;
+ *     ENHTIM_InitStruct.ENHTIM_CCValue  = 2000;
+ *     ENHTIM_InitStruct.ENHTIM_Mode = ENHTIM_MODE_PWM_MANUAL;
+ *     ENHTIM_Init(ENHTIMER_NUM, &ENHTIM_InitStruct);
+ * }
+ * \endcode
+ */
+void ENHTIM_Init(ENHTIM_TypeDef *ENHTIMx, ENHTIM_InitTypeDef *ENHTIM_TimeBaseInitStruct);
+
+/**
+ * \brief   Fill each ENHTIM_InitStruct member with its default value.
+ * \param[in] ENHTIM_InitStruct: Pointer to a ENHTIM_InitTypeDef structure which will be initialized.
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_enhance_timer_init(void)
+ * {
+ *     RCC_PeriphClockCmd(APBPeriph_ENHTIMER, APBPeriph_ENHTIMER_CLOCK, ENABLE);
+ *
+ *     ENHTIM_InitTypeDef ENHTIM_InitStruct;
+ *     ENHTIM_StructInit(&ENHTIM_InitStruct);
+ *
+ *     ENHTIM_InitStruct.ENHTIM_PWMOutputEn = ENHTIM_PWM_ENABLE;
+ *     ENHTIM_InitStruct.ENHTIM_MaxCount = 4000;
+ *     ENHTIM_InitStruct.ENHTIM_CCValue  = 2000;
+ *     ENHTIM_InitStruct.ENHTIM_Mode = ENHTIM_MODE_PWM_MANUAL;
+ *     ENHTIM_Init(ENHTIMER_NUM, &ENHTIM_InitStruct);
+ * }
+ * \endcode
+ */
+void ENHTIM_StructInit(ENHTIM_InitTypeDef *ENHTIM_InitStruct);
+
+/**
+ * \brief     Enable or disable the specified ENHTIM peripheral.
+ * \param[in] ENHTIMx: Where x can be 0 to 1 to select the ENHTIMx peripheral.
+ * \param[in] NewState: New state of the ENHTIMx peripheral.
+ *            This parameter can be: ENABLE or DISABLE.
+ * \return    None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_enhance_timer_init(void)
+ * {
+ *     RCC_PeriphClockCmd(APBPeriph_ENHTIMER, APBPeriph_ENHTIMER_CLOCK, ENABLE);
+ *
+ *     ENHTIM_InitTypeDef ENHTIM_InitStruct;
+ *     ENHTIM_StructInit(&ENHTIM_InitStruct);
+ *
+ *     ENHTIM_InitStruct.ENHTIM_PWMOutputEn = ENHTIM_PWM_ENABLE;
+ *     ENHTIM_InitStruct.ENHTIM_MaxCount = 4000;
+ *     ENHTIM_InitStruct.ENHTIM_CCValue  = 2000;
+ *     ENHTIM_InitStruct.ENHTIM_Mode = ENHTIM_MODE_PWM_MANUAL;
+ *     ENHTIM_Init(ENHTIMER_NUM, &ENHTIM_InitStruct);
+ *     ENHTIM_Cmd(ENHTIMER_NUM, ENABLE);
+ * }
+ * \endcode
+ */
+void ENHTIM_Cmd(ENHTIM_TypeDef *ENHTIMx, FunctionalState NewState);
+
+/**
+  * \brief     Mask or unmask the latch count2 fifo interrupt.
+  * \param[in] ENHTIMx: Where x can be 0 to 1 to select the ENHTIMx peripheral.
+  * \param[in] NewState: New state of the specified ENHTIMx peripheral latch count2 fifo interrupt.
+  *            This parameter can be: ENABLE or DISABLE.
+  * \return None.
+  */
+void ENHTIM_LCFIFOMaskConfig(ENHTIM_TypeDef *ENHTIMx, FunctionalState NewState);
+
+/**
+ * \brief     Enable or disable ENHTIMx interrupt.
+ * \param[in] ENHTIMx: Where x can be 0 to 1 to select the ENHTIMx peripheral.
+ * \param[in] ENHTIM_INT: Specify the ENHTIMx interrupt source which is to be enabled or disabled.
+ *            This parameter can be one of the following values, which refer to \ref ENHTIM_Interrupts_Definition.
+ *            \arg ENHTIM_INT_TIM: Enhance Timer interrupt source.
+ *            \arg ENHTIM_INT_LATCH_CNT2_FIFO_FULL: Enhance Timer latch count2 fifo full interrupt source.
+ *            \arg ENHTIM_INT_LATCH_CNT2_FIFO_EMPTY: Enhance Timer latch count2 fifo empty interrupt source.
+ *            \arg ENHTIM_INT_LATCH_CNT2_FIFO_THD: Enhance Timer latch count2 fifo threshold interrupt source.
+ * \param[in] NewState: New state of the ENHTIMx peripheral.
+ *            This parameter can be: ENABLE or DISABLE.
+ * \return    None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_enhance_timer_init(void)
+ * {
+ *     RCC_PeriphClockCmd(APBPeriph_ENHTIMER, APBPeriph_ENHTIMER_CLOCK, ENABLE);
+ *
+ *     ENHTIM_InitTypeDef ENHTIM_InitStruct;
+ *     ENHTIM_StructInit(&ENHTIM_InitStruct);
+ *
+ *     ENHTIM_InitStruct.ENHTIM_ClockDiv               = ENHTIM_CLOCK_DIVIDER_1;
+ *     ENHTIM_InitStruct.ENHTIM_Mode                   = ENHTIM_MODE_FreeRun;
+ *     ENHTIM_InitStruct.ENHTIM_LatchCountEn[2]        = ENHTIM_LATCH_COUNT_ENABLE;
+ *     ENHTIM_InitStruct.ENHTIM_LatchCountTrigger[2]   = ENHTIM_LATCH_TRIGGER_RISING_EDGE;
+ *     ENHTIM_InitStruct.ENHTIM_LatchCount2Thd         = 3;
+ *     ENHTIM_InitStruct.ENHTIM_LatchTriggerPad        = GPIO_INPUT_PIN_0;
+ *     ENHTIM_Init(ENHTIMER_NUM, &ENHTIM_InitStruct);
+ *     ENHTIM_ClearINTPendingBit(ENHTIMER_NUM, ENHTIM_INT_LATCH_CNT2_FIFO_THD);
+ *     ENHTIM_INTConfig(ENHTIMER_NUM, ENHTIM_INT_LATCH_CNT2_FIFO_THD, ENABLE);
+ * }
+ * \endcode
+ */
+void ENHTIM_INTConfig(ENHTIM_TypeDef *ENHTIMx, uint8_t ENHTIM_INT, FunctionalState NewState);
+
+/**
+ * \brief     Read ENHTIMx latch counter2 fifo data.
+ * \param[in] ENHTIMx: Where x can be 0 to 1 to select the ENHTIMx peripheral.
+ * \param[in] length: Latch count2 fifo length, max 4.
+ * \pBuf[out] pBuf: FIFO data out buffer.
+ * \return    None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void enhance_timer_demo(void)
+ * {
+ *     uint8_t length = ENHTIM_GetLatchCount2FIFOLength(ENH_TIM0);
+ *     uint32_t data[4] = {0};
+ *     ENHTIM_ReadLatchCount2FIFO(ENH_TIM0, data, length);
+ * }
+ * \endcode
+ */
+void ENHTIM_ReadLatchCount2FIFO(ENHTIM_TypeDef *ENHTIMx, uint32_t *pBuf, uint8_t length);
+
+/**
+ * \brief     Check whether the ENHTIM latch count2 fifo interrupt has occurred or not.
+ * \param[in] ENHTIMx: Where x can be 0 to 1 to select the ENHTIMx peripheral.
+ * \return    The new state of the specified ENHTIMx peripheral
+ *            latch count2 fifo interrupt (SET or RESET).
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void enhance_timer_demo(void)
+ * {
+ *     ITStatus int_status = ENHTIM_GetLCMaskINTStatus(ENH_TIM0);
+ * }
+ * \endcode
+ */
+ITStatus ENHTIM_GetLCFIFOMaskStatus(ENHTIM_TypeDef *ENHTIMx);
+
+/**
+ * \brief     Check whether the ENHTIM interrupt has occurred or not.
+ * \param[in] ENHTIMx: Where x can be 0 to 1 to select the ENHTIMx peripheral.
+ * \param[in] ENHTIM_INT: Specify the ENHTIMx interrupt source which is to be enabled or disabled.
+ *            This parameter can be one of the following values, which refer to \ref ENHTIM_Interrupts_Definition.
+ *            \arg ENHTIM_INT_TIM: Enhance Timer interrupt source.
+ *            \arg ENHTIM_INT_LATCH_CNT2_FIFO_FULL: Enhance Timer latch count2 fifo full interrupt source.
+ *            \arg ENHTIM_INT_LATCH_CNT2_FIFO_EMPTY: Enhance Timer latch count2 fifo empty interrupt source.
+ *            \arg ENHTIM_INT_LATCH_CNT2_FIFO_THD: Enhance Timer latch count2 fifo threshold interrupt source.
+ * \return    The new state of the ENHTIM_INT (SET or RESET).
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void enhance_timer_demo(void)
+ * {
+ *     ENHTIM_GetINTStatus(ENH_TIM0, ENHTIM_INT_TIM);
+ * }
+ * \endcode
+ */
+ITStatus ENHTIM_GetINTStatus(ENHTIM_TypeDef *ENHTIMx, uint8_t ENHTIM_INT);
+
+/**
+ * \brief     Clear ENHTIMx interrupt.
+ * \param[in] ENHTIMx: Where x can be 0 to 1 to select the ENHTIMx peripheral.
+ * \param[in] ENHTIM_INT: Specify the ENHTIMx interrupt source which is to be enabled or disabled.
+ *            This parameter can be one of the following values, which refer to \ref ENHTIM_Interrupts_Definition.
+ *            \arg ENHTIM_INT_TIM: Enhance Timer interrupt source.
+ *            \arg ENHTIM_INT_LATCH_CNT2_FIFO_FULL: Enhance Timer latch count2 fifo full interrupt source.
+ *            \arg ENHTIM_INT_LATCH_CNT2_FIFO_EMPTY: Enhance Timer latch count2 fifo empty interrupt source.
+ *            \arg ENHTIM_INT_LATCH_CNT2_FIFO_THD: Enhance Timer latch count2 fifo threshold interrupt source.
+ * \return    None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void enhance_timer_demo(void)
+ * {
+ *     ENHTIM_ClearINTPendingBit(ENH_TIM0, ENHTIM_INT_TIM);
+ * }
+ * \endcode
+ */
+void ENHTIM_ClearINTPendingBit(ENHTIM_TypeDef *ENHTIMx, uint8_t ENHTIM_INT);
+
+/**
+ * \brief     Get ENHTIMx current value when timer is running.
+ * \param[in] ENHTIMx: Where x can be 0 to 1 to select the ENHTIMx peripheral.
+ * \return    The counter value.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void enhance_timer_demo(void)
+ * {
+ *     uint32_t cur_value = ENHTIM_GetCurrentValue(ENH_TIM0);
+ * }
+ * \endcode
+ */
+__STATIC_INLINE uint32_t ENHTIM_GetCurrentCount(ENHTIM_TypeDef *ENHTIMx)
+{
+    /* Check the parameters */
+    assert_param(IS_ENHTIM_ALL_PERIPH(ENHTIMx));
+
+    return ENHTIMx->CUR_CNT;
+}
+
+/**
+ * \brief     Set Max Count value.
+ * \param[in] ENHTIMx: Where x can be 0 to 1 to select the ENHTIMx peripheral.
+ * \param[in] count: This parameter legal value range is from 0 ~ 2^32-2.
+ * \note      If it needs a dynamic change of MAX_CNT value, MAX_CNT has a minimum value limit.
+ *            Ex. cpu_clk = 40MHz, ETIMER_CLK = 40MHz, then MAX_CNT should larger than 10.
+ *            Ex. cpu_clk = 40MHz, ETIMER_CLK = 32kHz, then MAX_CNT should larger than 4.
+ *            If in the state where ENHTIM is disabled, there is no such limitation.
+ * \return    None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void enhance_timer_demo(void)
+ * {
+ *     ENHTIM_SetMaxCount(ENH_TIM0, 0x10000);
+ * }
+ * \endcode
+ */
+__STATIC_INLINE void ENHTIM_SetMaxCount(ENHTIM_TypeDef *ENHTIMx, uint32_t count)
+{
+    /* Check the parameters */
+    assert_param(IS_ENHTIM_ALL_PERIPH(ENHTIMx));
+
+    if (count > 0xFFFFFFFE)
+    {
+        count = 0xFFFFFFFE;
+    }
+    ENHTIMx->MAX_CNT = count;
+}
+
+/**
+ * \brief     Set ENHTIMx capture/compare value for user-defined manual mode.
+ * \param[in] ENHTIMx: Where x can be 0 to 1 to select the ENHTIMx peripheral.
+ * \param[in] value: This parameter legal value range is from 0 ~ 2^32-2.
+ * \note      If it needs a dynamic change of CCR value, CCR value has a minimum value limit.
+ *            Ex. cpu_clk = 40MHz, ETIMER_CLK = 40MHz, then CCR value should larger than 10.
+ *            Ex. cpu_clk = 40MHz, ETIMER_CLK = 32kHz, then CCR value should larger than 4.
+ *            If in the state where ENHTIM is disabled, there is no such limitation.
+ * \return    None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void enhance_timer_demo(void)
+ * {
+ *     ENHTIM_SetCCValue(ENH_TIM0, 0x1000);
+ * }
+ * \endcode
+ */
+__STATIC_INLINE void ENHTIM_SetCCValue(ENHTIM_TypeDef *ENHTIMx, uint32_t value)
+{
+    /* Check the parameters */
+    assert_param(IS_ENHTIM_ALL_PERIPH(ENHTIMx));
+
+    ENHTIMx->CCR = value;
+}
+
+/**
+ * \brief     Write value to ENHTIM CCR FIFO.
+ * \param[in] ENHTIMx: Where x can be 0 to 1 to select the ENHTIMx peripheral.
+ * \param[in] value: This parameter legal value range is from 0 ~ 2^32-2.
+ * \return    None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void enhance_timer_demo(void)
+ * {
+ *     ENHTIM_WriteCCFIFO(ENH_TIM0, 0x10000);
+ * }
+ * \endcode
+ */
+__STATIC_INLINE void ENHTIM_WriteCCFIFO(ENHTIM_TypeDef *ENHTIMx, uint32_t value)
+{
+    /* Check the parameters */
+    assert_param(IS_ENHTIM_ALL_PERIPH(ENHTIMx));
+
+    ENHTIMx->CCR_FIFO = value;
+}
+
+/**
+ * \brief     Check whether the specified ENHTIM CCR FIFO flag is set.
+ * \param[in] ENHTIM_FLAG: Specify the flag to check.
+ *            This parameter can be one of the following values, which refer to \ref ENHTIM_FIFO_Flag.
+ *            \arg ENHTIM_FLAG_TIM1_LC_FIFO_EMPTY: FIFO empty or not. If SET, CCR FIFO is empty.
+ *            \arg ENHTIM_FLAG_TIM0_LC_FIFO_EMPTY: FIFO full or not. If SET, CCR FIFO is full.
+ *            \arg ENHTIM_FLAG_TIM1_CCR_FIFO_EMPTY: FIFO empty or not. If SET, CCR FIFO is empty.
+ *            \arg ENHTIM_FLAG_TIM1_CCR_FIFO_FULL: FIFO full or not. If SET, CCR FIFO is full.
+ *            \arg ENHTIM_FLAG_TIM0_CCR_FIFO_EMPTY: FIFO empty or not. If SET, CCR FIFO is empty.
+ *            \arg ENHTIM_FLAG_TIM0_CCR_FIFO_FULL: FIFO full or not. If SET, CCR FIFO is full.
+ * \return    The new state of ENHTIM_FLAG (SET or RESET).
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void enhance_timer_demo(void)
+ * {
+ *     FlagStatus flag_status = ENHTIM_GetCCRFIFOFlagStatus(ENHTIM_FLAG_FIFO_EMPTY);
+ * }
+ * \endcode
+ */
+__STATIC_INLINE FlagStatus ENHTIM_GetFIFOFlagStatus(uint32_t ENHTIM_FLAG)
+{
+    /* Check the parameters */
+    assert_param(IS_ENHTIM_FIFO_FLAG(ENHTIM_FLAG));
+
+    FlagStatus bitstatus = RESET;
+
+    if (ENH_TIM_SHARE->FIFO_SR2 & ENHTIM_FLAG)
+    {
+        bitstatus = SET;
+    }
+
+    return bitstatus;
+}
+
+/**
+ * \brief     Enable ENHTIMx latch counter.
+ * \param[in] ENHTIMx: Where x can be 0 to 1 to select the ENHTIMx peripheral.
+ * \param[in] LatchCntIdx: E_ENHTIM_LATCHCNT enum value.
+ *            This parameter can be one of the following.
+ *            \arg LATCH_COUNT_0: Enhance timer latch count 0.
+ *            \arg LATCH_COUNT_1: Enhance timer latch count 1.
+ *            \arg LATCH_COUNT_2: Enhance timer latch count 2.
+ * \return    None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void enhance_timer_demo(void)
+ * {
+ *     uint32_t cur_value = ENHTIM_LatchCountEnable(ENH_TIM0, LATCH_COUNT_2);
+ * }
+ * \endcode
+ */
+__STATIC_INLINE void ENHTIM_LatchCountEnable(ENHTIM_TypeDef *ENHTIMx, E_ENHTIM_LATCHCNT LatchCntIdx)
+{
+    /* Check the parameters */
+    assert_param(IS_ENHTIM_ALL_PERIPH(ENHTIMx));
+
+    ENHTIMx->CR |= BIT(LatchCntIdx + 10);
+}
+
+/**
+ * \brief     Disable ENHTIMx latch counter.
+ * \param[in] ENHTIMx: where x can be 0 to 1 to select the ENHTIMx peripheral.
+ * \param[in] LatchCntIdx: E_ENHTIM_LATCHCNT enum value.
+ *            This parameter can be one of the following.
+ *            \arg LATCH_COUNT_0: Enhance timer latch count 0.
+ *            \arg LATCH_COUNT_1: Enhance timer latch count 1.
+ *            \arg LATCH_COUNT_2: Enhance timer latch count 2.
+ * \return    None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void enhance_timer_demo(void)
+ * {
+ *     uint32_t cur_value = ENHTIM_LatchCountDisable(ENH_TIM0, LATCH_COUNT_2);
+ * }
+ * \endcode
+ */
+__STATIC_INLINE void ENHTIM_LatchCountDisable(ENHTIM_TypeDef *ENHTIMx,
+                                              E_ENHTIM_LATCHCNT LatchCntIdx)
+{
+    /* Check the parameters */
+    assert_param(IS_ENHTIM_ALL_PERIPH(ENHTIMx));
+
+    ENHTIMx->CR &= ~BIT(LatchCntIdx + 10);
+}
+
+/**
+ * \brief     Get the value of ENHTIMx latch counter.
+ * \param[in] ENHTIMx: Where x can be 0 to 1 to select the ENHTIMx peripheral.
+ * \param[in] LatchCntIdx: E_ENHTIM_LATCHCNT enum value.
+ *            This parameter can be one of the following.
+ *            \arg LATCH_COUNT_0: Enhance timer latch count 0.
+ *            \arg LATCH_COUNT_1: Enhance timer latch count 1.
+ *            \arg LATCH_COUNT_2: Enhance timer latch count 2.
+ * \return    The latch counter value.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void enhance_timer_demo(void)
+ * {
+ *     uint32_t count_value = ENHTIM_GetLatchCountValue(ENH_TIM0, LATCH_COUNT_0);
+ * }
+ * \endcode
+ */
+__STATIC_INLINE uint32_t ENHTIM_GetLatchCount(ENHTIM_TypeDef *ENHTIMx,
+                                              E_ENHTIM_LATCHCNT LatchCntIdx)
+{
+    /* Check the parameters */
+    assert_param(IS_ENHTIM_ALL_PERIPH(ENHTIMx));
+
+    uint32_t count = 0;
+    count = *(volatile uint32_t *)(&(ENHTIMx->LATCH_CNT0) + LatchCntIdx);
+    return count;
+}
+
+/**
+ * \brief     Get the fifo length of ENHTIMx latch counter.
+ * \param[in] ENHTIMx: where x can be 0 to 1 to select the ENHTIMx peripheral.
+ * \return    FIFO data length.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void enhance_timer_demo(void)
+ * {
+ *     uint8_t length = ENHTIM_GetLatchCount2FIFOLength(ENH_TIM0);
+ * }
+ * \endcode
+ */
+__STATIC_INLINE uint8_t ENHTIM_GetLatchCount2FIFOLength(ENHTIM_TypeDef *ENHTIMx)
+{
+    /* Check the parameters */
+    assert_param(IS_ENHTIM_ALL_PERIPH(ENHTIMx));
+
+    uint32_t enhtim_id = ((uint32_t)ENHTIMx - (uint32_t)ENH_TIM0) / 0X24;
+
+    return (uint8_t)(((*((volatile uint32_t *)(&(ENH_TIM_SHARE->LC_FIFO_LEVEL0) + enhtim_id))) >> 16) &
+                     0x1F);
+}
+
+/**
+ * \brief     Clear capture/compare or latch count2 fifo.
+ * \param[in] ENHTIMx: Where x can be 0 to 1 to select the ENHTIMx peripheral.
+ * \param[in] FIFO_CLR: Specify the FIFO type which to be cleared.
+ *            This parameter can be one of the following values, which refer to \ref ENHTIM_FIFO_Clear_Flag.
+ *            \arg ENHTIM_FIFO_CLR_CCR: Enhance Timer CCR FIFO clear flag.
+ *            \arg ENHTIM_FIFO_CLR_CNT2: Enhance Timer latch count2 FIFO clear flag.
+ * \return    None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void enhance_timer_demo(void)
+ * {
+ *     ENHTIM_ClearFIFO(ENH_TIM0, ENHTIM_FIFO_CLR_CCR);
+ * }
+ * \endcode
+ */
+__STATIC_INLINE void ENHTIM_ClearFIFO(ENHTIM_TypeDef *ENHTIMx, uint8_t FIFO_CLR)
+{
+    /* Check the parameters */
+    assert_param(IS_ENHTIM_ALL_PERIPH(ENHTIMx));
+
+    uint32_t enhtim_id = ((uint32_t)ENHTIMx - (uint32_t)ENH_TIM0) / 0X24;
+
+    ENH_TIM_SHARE->FIFO_CLR |= (BIT(FIFO_CLR + enhtim_id));
+}
+
+/**
+ * \brief   ENHTIM PWM complementary output emergency stop.
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void enhance_timer_demo(void)
+ * {
+ *     ENHTIM_PWMDeadZoneEMStop();
+ * }
+ * \endcode
+ */
+__STATIC_INLINE void ENHTIM_PWMDeadZoneEMStop(void)
+{
+    ENHTIM_PWM_DEADZONE_CR |= BIT(8);
+}
+
+/**
+ * \brief     Get ENHTIM PWM output status.
+ * \param[in] ENHTIMx: Where x can be 0 to 1 to select the ENHTIMx peripheral.
+ * \return    ENHTIM PWM output status (SET or RESET).
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void enhance_timer_demo(void)
+ * {
+ *     FlagStatus status = ENHTIM_GetPWMOutputState(ENH_TIM0);
+ * }
+ * \endcode
+ */
+__STATIC_INLINE FlagStatus ENHTIM_GetPWMOutputState(ENHTIM_TypeDef *ENHTIMx)
+{
+    /* Check the parameters */
+    assert_param(IS_ENHTIM_ALL_PERIPH(ENHTIMx));
+
+    uint32_t enhtim_id = ((uint32_t)ENHTIMx - (uint32_t)ENH_TIM0) / 0X24;
+    uint32_t status = ENHTIM_LATCH_COUNT_CR & (0x1 << (enhtim_id + 6));
+    return (FlagStatus)(status >> (enhtim_id + 6));
+}
+
+/**
+ * \brief   Enable or disable bypass dead zone function of PWM complementary output.
+ *          After enabling, PWM_P = ~PWM_N.
+ * \param[in] ENHTIMx: ENHTIM0.
+ * \param[in] NewState: New state of the ENHTIMx peripheral.
+ *      \ref DISABLE: Disable bypass dead zone function.
+ *      \ref ENABLE: Enable bypass dead zone function.
+ * \note    To use this function, need to configure the corresponding enhtimer.
+ *          ENHTIMx can be only ENHTIM0.
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_pwm_init(void)
+ * {
+ *     ENHTIM_PWMDZBypassCmd(ENHTIM0, ENABLE);
+ * }
+ * \endcode
+ */
+void ENHTIM_PWMDZBypassCmd(ENHTIM_TypeDef *ENHTIMx, FunctionalState NewState);
+
+/** End of ENHTIM_Exported_Functions
+  * \}
+  */
+
+/** End of ENHTIM
+  * \}
+  */
+
+typedef struct
+{
+    uint32_t enhtim_reg[4];
+} ENHTIMStoreReg_TypeDef;
+
+typedef struct
+{
+    uint32_t enhtimshare_reg[12];
+} ENHTIMShareStoreReg_TypeDef;
+
+#define ENHTIM_GetCurrentControl(ENHTIMx)     (((ENHTIM_TypeDef *)(ENHTIMx))->CR)
+#define ENHTIM_GetCurrentMAXCNT(ENHTIMx)      (((ENHTIM_TypeDef *)(ENHTIMx))->MAX_CNT)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*_RTL876X_ENH_TIM_H_*/
+
diff --git a/bee/drivers/timer/src/device/rtl8752h/rtl876x_tim.c b/bee/drivers/timer/src/device/rtl8752h/rtl876x_tim.c
new file mode 100644
index 00000000..b78fc1b1
--- /dev/null
+++ b/bee/drivers/timer/src/device/rtl8752h/rtl876x_tim.c
@@ -0,0 +1,389 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "rtl876x_rcc.h"
+#include "rtl876x_tim.h"
+#include "app_section.h"
+
+/* TIM Private Defines */
+#define TIMER_CLK_SOURCE_REG_35C *((volatile uint32_t *)0x4000035CUL)
+#define TIMER_CLK_SOURCE_REG_360 *((volatile uint32_t *)0x40000360UL)
+
+/**
+  * @brief  Deinitializes the TIMx peripheral registers to their default reset values.
+  * @param  None
+  * @retval None
+  */
+void TIM_DeInit()
+{
+    /*enable timer IP clock and function */
+    RCC_PeriphClockCmd(APBPeriph_TIMER, APBPeriph_TIMER_CLOCK, DISABLE);
+}
+
+/**
+  * @brief  Initializes the TIMx Time Base Unit peripheral according to
+  *         the specified parameters in the TIM_TimeBaseInitStruct.
+  * @param  TIMx: where x can be 2 to 5 to select the TIM peripheral.
+  * @param  TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef
+  *         structure that contains the configuration information for the
+  *         specified TIM peripheral.
+  * @retval None
+  */
+void TIM_TimeBaseInit(TIM_TypeDef *TIMx, TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct)
+{
+    uint32_t timerid = 0;
+    uint32_t tempreg = 0;
+    volatile uint32_t *count2_address;
+
+    /* Check the parameters */
+    assert_param(IS_TIM_ALL_PERIPH(TIMx));
+    assert_param(IS_TIM_MODE(TIM_TimeBaseInitStruct->TIM_Mode));
+    assert_param(IS_TIM_PWM_DeadZone_En(TIM_TimeBaseInitStruct->PWMDeadZone_En));
+
+    /* Select clock source which can be system clock or 40 MHz  or pll*/
+    tempreg = (uint32_t)TIMx;
+    timerid = (tempreg - TIM0_REG_BASE) / 20;
+
+    /*div the clock source,actually it need enable TIM_SOURCE_CLOCK_DIV_EN*/
+    TIMER_CLK_SOURCE_REG_360 |= BIT9;
+
+    if (TIMER_CLK_SOURCE_REG_360 & BIT(10))
+    {
+        TIMER_CLK_SOURCE_REG_360 &= ~(BIT(10));
+    }
+
+    if (timerid < 2)
+    {
+        TIMER_CLK_SOURCE_REG_360 &= ~(0x7 << (timerid * 3));
+        TIMER_CLK_SOURCE_REG_360 |= ((TIM_TimeBaseInitStruct->TIM_SOURCE_DIV) << (timerid * 3));
+    }
+    else if ((timerid >= 2) && (timerid < 6))
+    {
+        TIMER_CLK_SOURCE_REG_360 &= ~(0x7 << (((timerid - 2) * 3) + 13));
+        TIMER_CLK_SOURCE_REG_360 |= ((TIM_TimeBaseInitStruct->TIM_SOURCE_DIV) \
+                                     << (((timerid - 2) * 3) + 13));
+    }
+
+    if (timerid == 3 || timerid == 5)
+    {
+        if (TIM_TimeBaseInitStruct->ClockDepend == true)
+        {
+            TIMER_CLK_SOURCE_REG_35C |= BIT(((timerid - 1) >> 1) - 1);
+        }
+        else
+        {
+            TIMER_CLK_SOURCE_REG_35C &= ~BIT(((timerid - 1) >> 1) - 1);
+        }
+    }
+
+    /* set timer mode and mask interrupt */
+    if (TIM_TimeBaseInitStruct->TIM_PWM_En == PWM_DISABLE)
+    {
+        TIMx->ControlReg = (TIM_TimeBaseInitStruct->TIM_Mode << 1) | BIT(2);
+        /* set timer period */
+        TIMx->LoadCount = TIM_TimeBaseInitStruct->TIM_Period;
+    }
+    else
+    {
+        TIMx->ControlReg = (TIM_TimeBaseInitStruct->TIM_Mode << 1) | BIT(2) | BIT(3);
+        count2_address = &TIMER0_LOAD_COUNT2;
+        count2_address = count2_address + timerid;
+        *count2_address = TIM_TimeBaseInitStruct->TIM_PWM_High_Count ;
+        /* set timer period */
+        TIMx->LoadCount = TIM_TimeBaseInitStruct->TIM_PWM_Low_Count;
+    }
+
+    /* set pwm deadzone mode, pwm0_pn based on timer2 */
+    if (TIM_TimeBaseInitStruct->PWMDeadZone_En == ENABLE)
+    {
+        if (timerid  == 2)
+        {
+            /* set pwm deadzone time */
+            TIMER_PWM2_CR = ((TIM_TimeBaseInitStruct->PWM_Deazone_Size) \
+                             | (TIM_TimeBaseInitStruct->PWM_Stop_State_N << 9) \
+                             | (TIM_TimeBaseInitStruct->PWM_Stop_State_P << 10) \
+                             | BIT12 | BIT17 | BIT18);
+        }
+    }
+    else
+    {
+        if (timerid == 2)
+        {
+            /*disable pwm2 deadzone mode*/
+            TIMER_PWM2_CR &= ~(BIT12 | BIT17 | BIT18);
+        }
+    }
+
+    /* Clear the IT status */
+    (void)TIMx->EOI;
+}
+
+/**
+  * @brief  Fills each TIM_InitStruct member with its default value.
+  * @param  TIM_InitStruct : pointer to a TIM_InitTypeDef structure which will be initialized.
+  * @retval None
+  */
+void TIM_StructInit(TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct)
+{
+    TIM_TimeBaseInitStruct->TIM_Mode = TIM_Mode_UserDefine;
+    TIM_TimeBaseInitStruct->TIM_Period = 0xfff;
+    TIM_TimeBaseInitStruct->TIM_SOURCE_DIV = TIM_CLOCK_DIVIDER_1;
+    TIM_TimeBaseInitStruct->ClockDepend = false;
+    TIM_TimeBaseInitStruct->TIM_PWM_En = PWM_DISABLE;
+    TIM_TimeBaseInitStruct->PWM_Stop_State_P = PWM_STOP_AT_LOW;
+    TIM_TimeBaseInitStruct->PWM_Stop_State_N = PWM_STOP_AT_HIGH;
+    TIM_TimeBaseInitStruct->PWMDeadZone_En = DEADZONE_DISABLE;
+}
+
+/**
+  * @brief  Enables or disables the specified TIM peripheral.
+  * @param  TIMx: where x can be 2 to 5 to select the TIMx peripheral.
+  * @param  NewState: new state of the TIMx peripheral.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void TIM_Cmd(TIM_TypeDef *TIMx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_TIM_ALL_PERIPH(TIMx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (NewState != DISABLE)
+    {
+        /* Enable the TIM Counter */
+        TIMx->ControlReg |= BIT(0);
+    }
+    else
+    {
+        /* Disable the TIM Counter */
+        TIMx->ControlReg &= ~(BIT(0));
+    }
+}
+
+/**
+  * @brief  change TIM period value.
+  * @param  TIMx: where x can be 2 to 5 to select the TIMx peripheral.
+  * @retval The new state of success or not  (SET or RESET).
+  */
+void TIM_ChangePeriod(TIM_TypeDef *TIMx, uint32_t period)
+{
+    /* Check the parameters */
+    assert_param(IS_TIM_ALL_PERIPH(TIMx));
+
+    TIMx->LoadCount = period;
+
+    return;
+}
+
+/**
+  * @brief  Enables or disables the specified TIMx interrupt.
+  * @param  TIMx: where x can be 2 to 5 to select the TIMx peripheral.
+  * @param  NewState: new state of the TIMx peripheral.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void TIM_INTConfig(TIM_TypeDef *TIMx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_TIM_ALL_PERIPH(TIMx));
+
+    if (NewState != DISABLE)
+    {
+        /* Enable the Interrupt sources */
+        TIMx->ControlReg &= ~(BIT(2));
+    }
+    else
+    {
+        /* Disable the Interrupt sources */
+        TIMx->ControlReg |= BIT(2);
+    }
+}
+
+/**
+  * @brief  Change PWM freq and duty according high_cnt and low_cnt
+  * @param  TIMx: where x can be 2 to 5 to select the TIMx peripheral.
+  * @param  high_count:
+    *   This parameter can be:
+    * @param  low_count:
+  *   This parameter can be:
+  * @retval None
+  */
+void TIM_PWMChangeFreqAndDuty(TIM_TypeDef *TIMx, uint32_t high_count, uint32_t low_count)
+{
+    volatile uint32_t *count2_address;
+    uint32_t timerid = 0;
+    uint32_t tempreg = 0;
+    tempreg = (uint32_t)TIMx;
+    timerid = (tempreg - TIM0_REG_BASE) / 20;
+    TIMx->LoadCount = low_count;
+    count2_address = &TIMER0_LOAD_COUNT2;
+    count2_address = count2_address + timerid;
+    *count2_address = high_count;
+
+}
+
+/**
+ * \brief   PWM complementary output emergency stop.
+ *          PWM_P emergency stop level state is configured by PWM_Stop_State_P,
+ *          PWM_N emergency stop level state is configured by PWM_Stop_State_N.
+ * \param[in] PWMx: PWM2.
+ * \param[in] NewState: New state of complementary output.
+ *      \ref DISABLE: Resume PWM complementary output.
+ *      \ref ENABLE: PWM complementary output emergency stop.
+ * \return  None.
+ * \note    To use this function, need to configure the corresponding timer.
+ *          PWM2 ->> TIM2.
+ */
+void TIM_PWMComplOutputEMCmd(PWM_TypeDef *PWMx, FunctionalState NewState)
+{
+    /* Check the parameters. */
+    assert_param(IS_PWM_ALL_PERIPH(PWMx));
+
+    if (NewState != DISABLE)
+    {
+        /* PWM complementary output emergency stop. */
+        PWMx->CR |= BIT8;
+    }
+    else
+    {
+        /* Resume PWM complementary output. */
+        PWMx->CR &= (~BIT8);
+    }
+}
+
+/**
+ * \brief   Enable or disable bypass dead zone function of PWM complementary output.
+ *          After enabling, PWM_P = ~PWM_N.
+ * \param[in] PWMx: PWM2.
+ * \param[in] NewState: New state of the PWMx peripheral.
+ *      \ref DISABLE: Disable bypass dead zone function.
+ *      \ref ENABLE: Enable bypass dead zone function.
+ * \note    To use this function, need to configure the corresponding timer.
+ *          PWM2 ->> TIM2.
+ * \return  None.
+ */
+void TIM_PWMDZBypassCmd(PWM_TypeDef *PWMx, FunctionalState NewState)
+{
+    /* Check the parameters. */
+    assert_param(IS_PWM_ALL_PERIPH(PWMx));
+
+    if (NewState != DISABLE)
+    {
+        /* Enable bypass dead zone function. */
+        PWMx->CR |= BIT13;
+    }
+    else
+    {
+        /* Disable bypass dead zone function. */
+        PWMx->CR &= (~BIT13);
+    }
+}
+
+/**
+ * \brief   Change the PWM dead zone clock source.
+ * \param[in] PWMx: PWM2.
+ * \param[in] NewState: New state of the PWMx peripheral.
+ *      \ref DISABLE: Use 32k clock source.
+ *      \ref ENABLE: Use 5M clock source.
+ * \return  None.
+ * \note    To use this function, need to configure the corresponding timer.
+ *          PWM2 ->> TIM2.
+ */
+void TIM_PWMChangeDZClockSrc(PWM_TypeDef *PWMx, FunctionalState NewState)
+{
+    /* Check the parameters. */
+    assert_param(IS_PWM_ALL_PERIPH(PWMx));
+
+    if (NewState != DISABLE)
+    {
+        /* Use 5M clock source. */
+        PWMx->CR |= BIT16;
+    }
+    else
+    {
+        /* Use 32k clock source. */
+        PWMx->CR &= (~BIT16);
+    }
+}
+
+/**
+  * \brief  Store TIM share register values when system enter DLPS.
+  * \param  PeriReg: Specifies to select the TIM share peripheral.
+  * \param  StoreBuf: Store buffer to store TIM share register data.
+  * \return None.
+  */
+DATA_RAM_FUNCTION
+void TIMSHARE_DLPSEnter(void *StoreBuf)
+{
+    TIMSHAREStoreReg_TypeDef *store_buf = (TIMSHAREStoreReg_TypeDef *)StoreBuf;
+    RCC_PeriphClockCmd(APBPeriph_TIMER, APBPeriph_TIMER_CLOCK, ENABLE);
+
+    store_buf->timshare_reg[0] = *((volatile uint32_t *)0x4000035CUL);
+    store_buf->timshare_reg[1] = *((volatile uint32_t *)0x40000360UL);
+    store_buf->timshare_reg[2] = *((volatile uint32_t *)0x40000364UL);
+    store_buf->timshare_reg[3] = *((volatile uint32_t *)0x40000368UL);
+    store_buf->timshare_reg[4] = TIMER_PWM2_CR;
+}
+
+/**
+  * \brief  Store TIM register values when system enter DLPS.
+  * \param  PeriReg: Specifies to select the TIM peripheral.
+  * \param  StoreBuf: Store buffer to store TIM register data.
+  * \return None.
+  */
+DATA_RAM_FUNCTION
+void TIM_DLPSEnter(void *PeriReg, void *StoreBuf)
+{
+    TIM_TypeDef *TIMx = (TIM_TypeDef *)PeriReg;
+    uint32_t tempreg = (uint32_t)TIMx;
+    uint32_t timerid = (tempreg - TIM0_REG_BASE) / 20;
+    TIMStoreReg_TypeDef *store_buf = (TIMStoreReg_TypeDef *)StoreBuf;
+
+    store_buf->tim_reg[0] = TIMx->LoadCount;
+    store_buf->tim_reg[1] = TIMx->ControlReg;
+    store_buf->tim_reg[2] = *(volatile uint32_t *)((uint32_t)(&TIMER0_LOAD_COUNT2) + timerid * 0x04);
+}
+
+/**
+  * \brief  Restore TIM share register values when system exit DLPS.
+  * \param  PeriReg: Specifies to select the TIM share peripheral.
+  * \param  StoreBuf: Restore buffer to restore TIM share register data.
+  * \return None
+  */
+DATA_RAM_FUNCTION
+void TIMSHARE_DLPSExit(void *StoreBuf)
+{
+    TIMSHAREStoreReg_TypeDef *store_buf = (TIMSHAREStoreReg_TypeDef *)StoreBuf;
+    RCC_PeriphClockCmd(APBPeriph_TIMER, APBPeriph_TIMER_CLOCK, ENABLE);
+
+    *((volatile uint32_t *)0x4000035CUL) = store_buf->timshare_reg[0];
+    *((volatile uint32_t *)0x40000360UL) = store_buf->timshare_reg[1];
+    *((volatile uint32_t *)0x40000364UL) = store_buf->timshare_reg[2];
+    *((volatile uint32_t *)0x40000368UL) = store_buf->timshare_reg[3];
+    TIMER_PWM2_CR                        = store_buf->timshare_reg[4];
+}
+
+/**
+  * \brief  Restore TIM register values when system exit DLPS.
+  * \param  PeriReg: Specifies to select the TIM peripheral.
+  * \param  StoreBuf: Restore buffer to restore TIM register data.
+  * \return None
+  */
+DATA_RAM_FUNCTION
+void TIM_DLPSExit(void *PeriReg, void *StoreBuf)
+{
+    TIM_TypeDef *TIMx = (TIM_TypeDef *)PeriReg;
+    uint32_t tempreg = (uint32_t)TIMx;
+    uint32_t timerid = (tempreg - TIM0_REG_BASE) / 20;
+    TIMStoreReg_TypeDef *store_buf = (TIMStoreReg_TypeDef *)StoreBuf;
+
+    TIMx->LoadCount  = store_buf->tim_reg[0];
+    TIMx->ControlReg = store_buf->tim_reg[1] ;
+    *(volatile uint32_t *)((uint32_t)(&TIMER0_LOAD_COUNT2) + timerid * 0x04) = store_buf->tim_reg[2];
+}
+
+
diff --git a/bee/drivers/timer/src/device/rtl8752h/rtl876x_tim.h b/bee/drivers/timer/src/device/rtl8752h/rtl876x_tim.h
new file mode 100644
index 00000000..10083ab1
--- /dev/null
+++ b/bee/drivers/timer/src/device/rtl8752h/rtl876x_tim.h
@@ -0,0 +1,670 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _RTL876X_TIM_H_
+#define _RTL876X_TIM_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/**
+ * \addtogroup  IO          Peripheral Drivers
+ * \defgroup    TIM         TIM
+ * \brief       Manage the TIM peripheral functions.
+ *
+ * \ingroup     IO
+ */
+
+/*============================================================================*
+ *                         Includes
+ *============================================================================*/
+#include "rtl876x.h"
+
+/*============================================================================*
+ *                         Types
+ *============================================================================*/
+/**
+ * \defgroup    TIM_Exported_Types TIM Exported Types
+ * \{
+ * \ingroup     TIM
+ */
+
+/**
+ * \brief       TIM init structure definition
+ *
+ * \ingroup     TIM_Exported_Types
+ */
+typedef struct
+{
+    uint16_t TIM_ClockSrc;          /*!< <b>Deprecated</b> use RCC instead.*/
+    uint16_t TIM_SOURCE_DIV;        /*!< Specify the clock source div.
+                                         This parameter can be a value of \ref TIM_Clock_Divider. */
+    uint16_t TIM_SOURCE_DIV_En;     /*!< Enable or disable timer source clock div. */
+    uint16_t TIM_Mode;              /*!< Specify the counter mode.
+                                         This parameter can be a value of \ref TIM_Mode. */
+    uint16_t TIM_PWM_En;            /*!< Specify the PWM mode.
+                                         This parameter can be a value of DISABLE or ENABLE */
+    uint32_t TIM_Period;            /*!< Specify the period value to be loaded into the active
+                                         Auto-Reload Register at the next update event.
+                                         This parameter must range from 0x0 to 0xFFFFFFFF. */
+    uint32_t TIM_PWM_High_Count;    /*!< Specify the PWM High Count.
+                                         This parameter must range from 0x0 to 0xFFFFFFFF. */
+    uint32_t TIM_PWM_Low_Count;     /*!< Specify the PWM Low Count.
+                                         This parameter must range from 0x0 to 0xFFFFFFFF. */
+    uint8_t  ClockDepend;           /*!< Specify TIM Source depend. timer3 depend timer2, timer5 depend timer4.
+                                         This parameter can be a value of ENABLE or DISABLE. */
+    uint32_t PWM_Deazone_Size;      /*!< Size of deadzone time, DeadzoneTime = deadzonesize / (32000 or 32768).
+                                         This parameter must range from 1 to 0xff. */
+    uint16_t PWMDeadZone_En;        /*!< PWM Deadzone enable.
+                                         This parameter can be a value of ENABLE or DISABLE. */
+    uint16_t PWM_Stop_State_P;      /*!< Specify the PWM P stop state.
+                                         This parameter can be a value of \ref PWMDeadZone_Stop_State. */
+    uint16_t PWM_Stop_State_N;      /*!< Specify the PWM N stop state.
+                                         This parameter can be a value of \ref PWMDeadZone_Stop_State. */
+} TIM_TimeBaseInitTypeDef;
+
+/** End of TIM_Exported_Types
+  * \}
+  */
+
+/*============================================================================*
+ *                         Constants
+ *============================================================================*/
+
+/* TIM private defines */
+#define TIMER0_LOAD_COUNT2      *((volatile uint32_t *)0x400020B0UL)
+#define TIMER1_LOAD_COUNT2      *((volatile uint32_t *)0x400020B4UL)
+#define TIMER2_LOAD_COUNT2      *((volatile uint32_t *)0x400020B8UL)
+#define TIMER3_LOAD_COUNT2      *((volatile uint32_t *)0x400020BCUL)
+#define TIMER4_LOAD_COUNT2      *((volatile uint32_t *)0x400020C0UL)
+#define TIMER5_LOAD_COUNT2      *((volatile uint32_t *)0x400020C4UL)
+
+#define TIMER_PWM2_CR           *((volatile uint32_t *)0x40000364UL)
+
+/**
+ * \defgroup    TIM_Exported_Constants  TIM Exported Constants
+ *
+ * \ingroup     TIM
+ */
+
+/**
+ * \defgroup    TIM_Config TIM Config
+ * \{
+ * \ingroup     TIM_Exported_Constants
+ */
+#define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM0) || \
+                                   ((PERIPH) == TIM1) || \
+                                   ((PERIPH) == TIM2) || \
+                                   ((PERIPH) == TIM3) || \
+                                   ((PERIPH) == TIM4) || \
+                                   ((PERIPH) == TIM5))
+
+#define IS_PWM_ALL_PERIPH(PERIPH) ((PERIPH) == PWM2)
+/** \} */
+
+/**
+ * \defgroup    TIM_CLK_Divider TIM CLK Divider
+ * \{
+ * \ingroup     TIM_Exported_Constants
+ */
+#define TIM_CLOCK_DIVIDER_1                           ((uint16_t)0x0)
+#define TIM_CLOCK_DIVIDER_125                         ((uint16_t)0x3)
+#define TIM_CLOCK_DIVIDER_2                           ((uint16_t)0x4)
+#define TIM_CLOCK_DIVIDER_4                           ((uint16_t)0x5)
+#define TIM_CLOCK_DIVIDER_8                           ((uint16_t)0x6)
+#define TIM_CLOCK_DIVIDER_40                          ((uint16_t)0x7)
+
+#define IS_TIM_SOURCE_DIVIDER(DIV)              (((DIV) == TIM_CLOCK_DIVIDER_1)  || \
+                                                 ((DIV) == TIM_CLOCK_DIVIDER_125)|| \
+                                                 ((DIV) == TIM_CLOCK_DIVIDER_2)  || \
+                                                 ((DIV) == TIM_CLOCK_DIVIDER_4)  || \
+                                                 ((DIV) == TIM_CLOCK_DIVIDER_8)  || \
+                                                 ((DIV) == TIM_CLOCK_DIVIDER_40))
+/** \} */
+
+/**
+ * \defgroup    TIM_Mode TIM Mode
+ * \{
+ * \ingroup     TIM_Exported_Constants
+ */
+#define TIM_Mode_FreeRun                    ((uint16_t)0x0000)
+#define TIM_Mode_UserDefine                 ((uint16_t)0x0001)
+
+#define IS_TIM_MODE(mode) (((mode) == TIM_Mode_FreeRun) || \
+                           ((mode) == TIM_Mode_UserDefine))
+/** \} */
+
+/**
+ * \defgroup    TIM_PWM_En TIM PWM Mode Enable
+ * \{
+ * \ingroup     TIM_Exported_Constants
+ */
+#define PWM_ENABLE                        ((uint16_t)0x1)
+#define PWM_DISABLE                       ((uint16_t)0x0)
+
+#define IS_TIM_PWM_En(mode) (((mode) == PWM_ENABLE) || \
+                             ((mode) == PWM_DISABLE))
+/** \} */
+
+/**
+ * \defgroup    TIM_Event_Duration TIM Event Duration
+ * \{
+ * \ingroup     TIM_Exported_Constants
+ */
+#define TIM_EventDuration_32us                    ((uint16_t)0x0000)
+#define TIM_EventDuration_64us                    ((uint16_t)0x0001)
+#define TIM_EventDuration_128us                   ((uint16_t)0x0002)
+#define TIM_EventDuration_256us                   ((uint16_t)0x0003)
+
+#define IS_TIM_Event_DURATION(duration) (((duration) == TIM_EventDuration_32us) || \
+                                         ((duration) == TIM_EventDuration_64us) || \
+                                         ((duration) == TIM_EventDuration_128us) || \
+                                         ((duration) == TIM_EventDuration_256us))
+/** \} */
+
+/**
+ * \defgroup    PWMDeadZone_En PWM DeadZone Enable
+ * \{
+ * \ingroup     TIM_Exported_Constants
+ */
+#define DEADZONE_ENABLE                        ((uint16_t)0x1)
+#define DEADZONE_DISABLE                       ((uint16_t)0x0)
+
+#define IS_TIM_PWM_DeadZone_En(mode) (((mode) == DEADZONE_ENABLE) || \
+                                      ((mode) == DEADZONE_DISABLE))
+/** \} */
+
+/**
+ * \defgroup    PWMDeadZone_Stop_State PWM DeadZone Stop State
+ * \{
+ * \ingroup     TIM_Exported_Constants
+ */
+#define PWM_STOP_AT_HIGH                        ((uint16_t)0x1)
+#define PWM_STOP_AT_LOW                         ((uint16_t)0x0)
+/** \} */
+
+/** End of TIM_Exported_Constants
+  * \}
+  */
+
+/*============================================================================*
+ *                         Functions
+ *============================================================================*/
+/**
+ * \defgroup    TIM_Exported_Functions  TIM Exported Functions
+ * \{
+ * \ingroup     TIM
+ */
+
+/**
+ * \brief   Deinitialize the TIMx peripheral registers to their default reset values.
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_timer_init(void)
+ * {
+ *     TIM_DeInit();
+ * }
+ * \endcode
+ */
+void TIM_DeInit(void);
+
+/**
+ * \brief   Initialize the TIMx time base unit peripheral according to
+ *          the specified parameters in TIM_TimeBaseInitStruct.
+ * \param[in] TIMx: where x can be 2 to 5 to select the TIM peripheral.
+ * \param[in] TIM_TimeBaseInitStruct: Pointer to a TIM_TimeBaseInitTypeDef
+ *            structure that contains the configuration information for the selected TIM peripheral.
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_timer_init(void)
+ * {
+ *     RCC_PeriphClockCmd(APBPeriph_TIMER, APBPeriph_TIMER_CLOCK, ENABLE);
+ *
+ *     TIM_TimeBaseInitTypeDef TIM_InitStruct;
+ *     TIM_StructInit(&TIM_InitStruct);
+ *
+ *     TIM_InitStruct.TIM_PWM_En = PWM_DISABLE;
+ *     TIM_InitStruct.TIM_Period = 1000000 - 1 ;
+ *     TIM_InitStruct.TIM_Mode = TIM_Mode_UserDefine;
+ *     TIM_TimeBaseInit(TIMER_NUM, &TIM_InitStruct);
+ * }
+ * \endcode
+ */
+void TIM_TimeBaseInit(TIM_TypeDef *TIMx, TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct);
+
+/**
+ * \brief   Fill each TIM_InitStruct member with its default value.
+ * \param[in] TIM_TimeBaseInitStruct: Pointer to a TIM_TimeBaseInitTypeDef structure which will be initialized.
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_timer_init(void)
+ * {
+ *     RCC_PeriphClockCmd(APBPeriph_TIMER, APBPeriph_TIMER_CLOCK, ENABLE);
+ *
+ *     TIM_TimeBaseInitTypeDef TIM_InitStruct;
+ *     TIM_StructInit(&TIM_InitStruct);
+ *
+ *     TIM_InitStruct.TIM_PWM_En = PWM_DISABLE;
+ *     TIM_InitStruct.TIM_Period = 1000000 - 1;
+ *     TIM_InitStruct.TIM_Mode = TIM_Mode_UserDefine;
+ *     TIM_TimeBaseInit(TIM4, &TIM_InitStruct);
+ * }
+ * \endcode
+ */
+void TIM_StructInit(TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct);
+
+/**
+ * \brief   Enable or disable the specified TIM peripheral.
+ * \param[in] TIMx: Where x can be 2 to 5 to select the TIMx peripheral.
+ * \param[in] NewState: New state of the TIMx peripheral.
+ *      This parameter can be: ENABLE or DISABLE.
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_timer_init(void)
+ * {
+ *     RCC_PeriphClockCmd(APBPeriph_TIMER, APBPeriph_TIMER_CLOCK, ENABLE);
+ *
+ *     TIM_TimeBaseInitTypeDef TIM_InitStruct;
+ *     TIM_StructInit(&TIM_InitStruct);
+ *
+ *     TIM_InitStruct.TIM_PWM_En = PWM_DISABLE;
+ *     TIM_InitStruct.TIM_Period = 1000000 - 1;
+ *     TIM_InitStruct.TIM_Mode = TIM_Mode_UserDefine;
+ *     TIM_TimeBaseInit(TIM4, &TIM_InitStruct);
+ *     TIM_Cmd(TIM4, ENABLE);
+ * }
+ * \endcode
+ */
+void TIM_Cmd(TIM_TypeDef *TIMx, FunctionalState NewState);
+
+/**
+ * \brief   Enable or disable the specified TIMx interrupt.
+ * \param[in]   TIMx: Where x can be 2 to 5 to select the TIMx peripheral.
+ * \param[in]   NewState: New state of the TIMx peripheral.
+ *      This parameter can be: ENABLE or DISABLE.
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_timer_init(void)
+ * {
+ *     RCC_PeriphClockCmd(APBPeriph_TIMER, APBPeriph_TIMER_CLOCK, ENABLE);
+ *
+ *     TIM_TimeBaseInitTypeDef TIM_InitStruct;
+ *     TIM_StructInit(&TIM_InitStruct);
+ *
+ *     TIM_InitStruct.TIM_PWM_En = PWM_DISABLE;
+ *     TIM_InitStruct.TIM_Period = 1000000 - 1;
+ *     TIM_InitStruct.TIM_Mode = TIM_Mode_UserDefine;
+ *     TIM_TimeBaseInit(TIM4, &TIM_InitStruct);
+ *     TIM_ClearINT(TIM4);
+ *     TIM_INTConfig(TIM4, ENABLE);
+ * }
+ * \endcode
+ */
+void TIM_INTConfig(TIM_TypeDef *TIMx, FunctionalState NewState);
+
+/**
+ * \brief   Change TIM period value.
+ * \param[in]   TIMx: Where x can be 2 to 5 to select the TIMx peripheral.
+ * \param[in]   period: Period value to be changed.
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void timer_demo(void)
+ * {
+ *     uint32_t new_period = 1000000 - 1;
+ *     TIM_Cmd(TIM4, DISABLE);
+ *     TIM_ChangePeriod(TIM4, new_period);
+ *
+ * }
+ * \endcode
+ */
+void TIM_ChangePeriod(TIM_TypeDef *TIMx, uint32_t period);
+
+/**
+ * \brief   Change PWM freq and duty according high_cnt and low_cnt
+ * \param[in]   TIMx: Where x can be 2 to 5 to select the TIMx peripheral.
+ * \param[in]   high_count: This parameter can be 0x00~0xFFFFFFFF.
+ * \param[in]  low_count: This parameter can be 0x00~0xFFFFFFFF.
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void timer_demo(void)
+ * {
+ *     uint32_t high_count = 1000000 - 1;
+ *     uint32_t low_count = 1000000 - 1;
+ *     TIM_Cmd(TIM4, DISABLE);
+ *     TIM_ChangePeriod(TIM4, high_count, low_count);
+ * }
+ * \endcode
+ */
+void TIM_PWMChangeFreqAndDuty(TIM_TypeDef *TIMx, uint32_t high_count, uint32_t low_count);
+
+/**
+ * \brief   Get TIMx current value when timer is running.
+ * \param[in]   TIMx: Where x can be 2 to 5 to select the TIMx peripheral.
+ * \return  The counter value.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void timer_demo(void)
+ * {
+ *     uint32_t cur_value = TIM_GetCurrentValue(TIM4);
+ * }
+ * \endcode
+ */
+__STATIC_INLINE uint32_t TIM_GetCurrentValue(TIM_TypeDef *TIMx)
+{
+    /* Check the parameters */
+    assert_param(IS_TIM_ALL_PERIPH(TIMx));
+
+    return TIMx->CurrentValue;
+}
+
+/**
+ * \brief   Check whether the TIM interrupt has occurred or not.
+ * \param[in]   TIMx: Where x can be 2 to 5 to select the TIMx peripheral.
+ * \return  The new state of the TIM_IT(SET or RESET).
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void timer_demo(void)
+ * {
+ *     ITStatus int_status = TIM_GetINTStatus(TIM4);
+ * }
+ * \endcode
+ */
+__STATIC_INLINE ITStatus TIM_GetINTStatus(TIM_TypeDef *TIMx)
+{
+    ITStatus bitstatus = RESET;
+    uint16_t itstatus = (uint16_t)TIMx->IntStatus;
+
+    /* Check the parameters */
+    assert_param(IS_TIM_ALL_PERIPH(TIMx));
+
+    if (itstatus != (uint16_t)RESET)
+    {
+        bitstatus = SET;
+    }
+
+    return bitstatus;
+}
+
+/**
+ * \brief   Clear TIM interrupt.
+ * \param[in]   TIMx: Where x can be 2 to 5 to select the TIMx peripheral.
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void timer_demo(void)
+ * {
+ *     TIM_ClearINT(TIM4);
+ * }
+ * \endcode
+ */
+__STATIC_INLINE void TIM_ClearINT(TIM_TypeDef *TIMx)
+{
+    /* Check the parameters */
+    assert_param(IS_TIM_ALL_PERIPH(TIMx));
+    /* Clear the IT */
+    (void)(TIMx->EOI);
+}
+
+/**
+ * \brief   Check whether the TIM is in operation or not.
+ * \param[in]   TIMx: Where x can be 2 to 5 to select the TIMx peripheral.
+ * \return  The new state of the timer operation status (SET or RESET).
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void timer_demo(void)
+ * {
+ *     ITStatus intstatus = TIM_GetOperationStatus(TIM4);
+ * }
+ * \endcode
+ */
+__STATIC_INLINE ITStatus TIM_GetOperationStatus(TIM_TypeDef *TIMx)
+{
+    ITStatus bitstatus = RESET;
+
+    /* Check the parameters */
+    assert_param(IS_TIM_ALL_PERIPH(TIMx));
+
+    if (TIMx->ControlReg & BIT(0))
+    {
+        bitstatus = SET;
+    }
+
+    return bitstatus;
+}
+
+/**
+ * \brief   PWM complementary output emergency stop and resume.
+ *          PWM_P emergency stop level state is configured by PWM_Stop_State_P,
+ *          PWM_N emergency stop level state is configured by PWM_Stop_State_N.
+ * \param[in] PWMx: PWM2.
+ * \param[in] NewState: New state of complementary output.
+ *      \ref DISABLE: Resume PWM complementary output.
+ *      \ref ENABLE: PWM complementary output emergency stop.
+ * \note    To use this function, need to configure the corresponding timer.
+ *          PWM2 ->> TIM2.
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void board_pwm_init(void)
+ * {
+ *     Pad_Config(P0_1, PAD_PINMUX_MODE, PAD_IS_PWRON, PAD_PULL_NONE, PAD_OUT_ENABLE, PAD_OUT_HIGH);
+ *     Pad_Config(P0_2, PAD_PINMUX_MODE, PAD_IS_PWRON, PAD_PULL_NONE, PAD_OUT_ENABLE,
+ *                PAD_OUT_HIGH);
+ *     Pad_Config(P2_2, PAD_PINMUX_MODE, PAD_IS_PWRON, PAD_PULL_NONE, PAD_OUT_ENABLE,
+ *                PAD_OUT_HIGH);
+ *
+ *     Pinmux_Config(P0_1, PWM_OUT_PIN_PINMUX);
+ *     Pinmux_Config(P0_2, PWM_OUT_P_PIN_PINMUX);
+ *     Pinmux_Config(P2_2, PWM_OUT_N_PIN_PINMUX);
+ * }
+ *
+ * void driver_pwm_init(void)
+ * {
+ *     RCC_PeriphClockCmd(APBPeriph_TIMER, APBPeriph_TIMER_CLOCK, ENABLE);
+ *
+ *     TIM_TimeBaseInitTypeDef TIM_InitStruct;
+ *     TIM_StructInit(&TIM_InitStruct);
+ *     TIM_InitStruct.TIM_Mode             = TIM_Mode_UserDefine;
+ *     TIM_InitStruct.TIM_PWM_En           = PWM_ENABLE;
+ *     TIM_InitStruct.TIM_PWM_High_Count   = PWM_HIGH_COUNT;
+ *     TIM_InitStruct.TIM_PWM_Low_Count    = PWM_LOW_COUNT;
+ *     TIM_InitStruct.PWM_Stop_State_P     = PWM_STOP_AT_HIGH;
+ *     TIM_InitStruct.PWM_Stop_State_N     = PWM_STOP_AT_LOW;
+ *     TIM_InitStruct.PWMDeadZone_En       = DEADZONE_ENABLE;  //enable to use pwn p/n output
+ *     TIM_InitStruct.PWM_Deazone_Size     = 255;
+ *     TIM_TimeBaseInit(TIM2, &TIM_InitStruct);
+ *
+ *     TIM_Cmd(TIM2, ENABLE);
+ * }
+ *
+ * void pwm_demo(void)
+ * {
+ *    board_pwm_init();
+ *    driver_pwm_init();
+ *    //Add delay.
+ *    TIM_PWMComplOutputEMCmd(PWM2,ENABLE);
+ * }
+ * \endcode
+ */
+void TIM_PWMComplOutputEMCmd(PWM_TypeDef *PWMx, FunctionalState NewState);
+
+/**
+ * \brief   Enable or disable bypass dead zone function of PWM complementary output.
+ *          After enabling, PWM_P = ~PWM_N.
+ * \param[in] PWMx: PWM2.
+ * \param[in] NewState: New state of the PWMx peripheral.
+ *      \ref DISABLE: Disable bypass dead zone function.
+ *      \ref ENABLE: Enable bypass dead zone function.
+ * \return  None.
+ * \note    To use this function, need to configure the corresponding timer.
+ *          PWM2 ->> TIM2.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_pwm_init(void)
+ * {
+ *     RCC_PeriphClockCmd(APBPeriph_TIMER, APBPeriph_TIMER_CLOCK, ENABLE);
+ *
+ *     TIM_TimeBaseInitTypeDef TIM_InitStruct;
+ *     TIM_StructInit(&TIM_InitStruct);
+ *     TIM_InitStruct.TIM_Mode             = TIM_Mode_UserDefine;
+ *     TIM_InitStruct.TIM_PWM_En           = PWM_ENABLE;
+ *     TIM_InitStruct.TIM_PWM_High_Count   = PWM_HIGH_COUNT;
+ *     TIM_InitStruct.TIM_PWM_Low_Count    = PWM_LOW_COUNT;
+ *     TIM_InitStruct.PWM_Stop_State_P     = PWM_STOP_AT_HIGH;
+ *     TIM_InitStruct.PWM_Stop_State_N     = PWM_STOP_AT_LOW;
+ *     TIM_InitStruct.PWMDeadZone_En       = DEADZONE_ENABLE;  //enable to use pwn p/n output
+ *     TIM_InitStruct.PWM_Deazone_Size     = 255;
+ *     TIM_TimeBaseInit(TIM2, &TIM_InitStruct);
+ *
+ *     TIM_Cmd(TIM2, ENABLE);
+ *     TIM_PWMDZBypassCmd(PWM2, ENABLE);
+ * }
+ * \endcode
+ */
+void TIM_PWMDZBypassCmd(PWM_TypeDef *PWMx, FunctionalState NewState);
+
+/**
+ * \brief   Change the PWM dead time clock source.
+ * \param[in] PWMx: PWM2.
+ * \param[in] NewState: New state of the PWMx peripheral.
+ *      \ref DISABLE: Use 32k clock source.
+ *      \ref ENABLE: Use 5M clock source.
+ * \return  None.
+ * \note    To use this function, need to configure the corresponding timer.
+ *          PWM2 ->> TIM2.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_pwm_init(void)
+ * {
+ *     RCC_PeriphClockCmd(APBPeriph_TIMER, APBPeriph_TIMER_CLOCK, ENABLE);
+ *     //Open 5M clock source.
+ *     RCC_ClockSrc5MCmd();
+ *
+ *     TIM_TimeBaseInitTypeDef TIM_InitStruct;
+ *
+ *     TIM_StructInit(&TIM_InitStruct);
+ *     TIM_InitStruct.TIM_Mode             = TIM_Mode_UserDefine;
+ *     TIM_InitStruct.TIM_PWM_En           = PWM_ENABLE;
+ *     TIM_InitStruct.TIM_PWM_High_Count   = PWM_HIGH_COUNT;
+ *     TIM_InitStruct.TIM_PWM_Low_Count    = PWM_LOW_COUNT;
+ *     TIM_InitStruct.PWM_Stop_State_P     = PWM_STOP_AT_HIGH;
+ *     TIM_InitStruct.PWM_Stop_State_N     = PWM_STOP_AT_LOW;
+ *     TIM_InitStruct.PWMDeadZone_En       = DEADZONE_ENABLE;  //enable to use pwn p/n output
+ *     TIM_InitStruct.PWM_Deazone_Size     = PWM_DEAD_ZONE_SIZE;
+ *     TIM_TimeBaseInit(TIM2, &TIM_InitStruct);
+ *
+ *     //Use 5M clock source.
+ *     TIM_PWMChangeDZClockSrc(PWM2,ENABLE);
+ *
+ *     TIM_Cmd(TIM2, ENABLE);
+ * }
+ * \endcode
+ */
+void TIM_PWMChangeDZClockSrc(PWM_TypeDef *PWMx, FunctionalState NewState);
+
+/**
+ * \brief   PWM complementary output emergency stop.
+ * \param[in] PWMx: PWM2.
+ * \return  None.
+ */
+__STATIC_INLINE void PWM_Deadzone_EMStop(PWM_TypeDef *PWMx)
+{
+    /* Check the parameters. */
+    assert_param(IS_PWM_ALL_PERIPH(PWMx));
+
+    PWMx->CR |= BIT(8);
+}
+
+/**
+  * @brief  Get PWM current output status.
+  * @param  TIMx: where x can be 2 to 5 to select the TIMx peripheral.
+  * @return The output state of the timer(SET: High or RESET: Low).
+  */
+__STATIC_INLINE FlagStatus TIM_GetPWMOutputStatus(TIM_TypeDef *TIMx)
+{
+    uint32_t timer_index = 0;
+    uint32_t reg_value = 0;
+    ITStatus bitstatus = RESET;
+
+    /* Check the parameters */
+    assert_param(IS_TIM_ALL_PERIPH(TIMx));
+
+    timer_index = ((uint32_t)TIMx - TIM0_REG_BASE) / (TIM1_REG_BASE - TIM0_REG_BASE);
+    reg_value = *((volatile uint32_t *)0x40006024UL);
+
+    if ((reg_value >> timer_index) & BIT(0))
+    {
+        bitstatus = SET;
+    }
+
+    return bitstatus;
+}
+
+#define TIM_GetCurrentControl(TIMx)      (((TIM_TypeDef *)(TIMx))->ControlReg)
+#define TIM_GetCurrentLoadCnt(TIMx)      (((TIM_TypeDef *)(TIMx))->LoadCount)
+
+/** End of TIM_Exported_Functions
+  * \}
+  */
+
+/** End of TIM
+  * \}
+  */
+
+typedef struct
+{
+    uint32_t tim_reg[3];
+} TIMStoreReg_TypeDef;
+
+typedef struct
+{
+    uint32_t timshare_reg[5];
+} TIMSHAREStoreReg_TypeDef;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*_RTL876X_TIM_H_*/
+
+
diff --git a/bee/drivers/timer/src/device/rtl87x2g/CMakeLists.txt b/bee/drivers/timer/src/device/rtl87x2g/CMakeLists.txt
new file mode 100644
index 00000000..4c82d05f
--- /dev/null
+++ b/bee/drivers/timer/src/device/rtl87x2g/CMakeLists.txt
@@ -0,0 +1,7 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_include_directories(${CMAKE_CURRENT_SOURCE_DIR})
+
+zephyr_library_sources_ifdef(CONFIG_REALTEK_BEE_TIMER rtl_tim.c rtl87x2g_tim.c)
+zephyr_library_sources_ifdef(CONFIG_REALTEK_BEE_ENHTIMER rtl_enh_tim.c rtl87x2g_enh_tim.c)
diff --git a/bee/drivers/timer/src/device/rtl87x2g/rtl87x2g_enh_tim.c b/bee/drivers/timer/src/device/rtl87x2g/rtl87x2g_enh_tim.c
new file mode 100644
index 00000000..e17032c2
--- /dev/null
+++ b/bee/drivers/timer/src/device/rtl87x2g/rtl87x2g_enh_tim.c
@@ -0,0 +1,306 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *                        Header Files
+ *============================================================================*/
+#include "rtl_enh_tim.h"
+#include "rtl_rcc.h"
+#include "app_section.h"
+
+/*============================================================================*
+ *                          Private Macros
+ *============================================================================*/
+#define PWM_EMG_STOP        BIT8
+
+/*============================================================================*
+ *                           Public Functions
+ *============================================================================*/
+uint32_t ENHTIM_GetTimerID(ENHTIM_TypeDef *ENHTIMx)
+{
+    uint32_t enhtim_id = ((uint32_t)ENHTIMx - (uint32_t)ENH_TIM0) / 0x24;
+
+    return enhtim_id;
+}
+
+ENHPWM_TypeDef *ENHTIM_GetPwmID(uint32_t enhtim_id)
+{
+    switch (enhtim_id)
+    {
+    case 0:
+        return ENH_TIM0_PWM;
+    case 1:
+        return ENH_TIM1_PWM;
+    case 2:
+        return ENH_TIM2_PWM;
+    case 3:
+        return ENH_TIM3_PWM;
+    default:
+        return 0;
+    }
+}
+
+bool ENHTIM_ClkGet(ENHTIM_TypeDef *ENHTIMx, ENHTIMClkSrc_TypdDef *ClockSrc,
+                   ENHTIMClkDiv_TypeDef *ClockDiv)
+{
+    uint32_t enhtim_id = ((uint32_t)ENHTIMx - (uint32_t)ENH_TIM0) / 0x24;
+    uint32_t enhtim_id_odd = enhtim_id % 2;
+    uint32_t enhtim_id_temp = enhtim_id / 2;
+
+    uint32_t temp_addr_value = *((uint32_t *)(&(REG_ENHTIMER_CLOCK_CTRL)) + enhtim_id_temp);
+    *ClockSrc = (temp_addr_value >> 4) & 0x7;
+
+    *ClockDiv = (((temp_addr_value >> (3 + 16 * enhtim_id_odd)) & BIT0) == 0) ? ENHTIM_CLOCK_DIVIDER_1 :
+                ((temp_addr_value >> (16 * enhtim_id_odd)) & 0x7);
+
+    return true;
+}
+
+void ENHTIM_ClkConfig(ENHTIM_TypeDef *ENHTIMx, ENHTIMClkSrc_TypdDef ClockSrc,
+                      ENHTIMClkDiv_TypeDef ClockDiv)
+{
+    uint32_t enhtim_id = ((uint32_t)ENHTIMx - (uint32_t)ENH_TIM0) / 0x24;
+    uint32_t enhtim_id_odd = enhtim_id % 2;
+    uint32_t enhtim_id_temp = enhtim_id / 2;
+    uint8_t ENHTIM_ClockDiv_En = ClockDiv == 0 ? DISABLE : ENABLE;
+
+    *((uint32_t *)(&(REG_ENHTIMER_CLOCK_CTRL)) + enhtim_id_temp) &= ~(0x7 << 4);
+    *((uint32_t *)(&(REG_ENHTIMER_CLOCK_CTRL)) + enhtim_id_temp) |= (ClockSrc << 4);
+
+    /*Clear ENHTIM Clock DIV */
+    *((uint32_t *)(&(REG_ENHTIMER_CLOCK_CTRL)) + enhtim_id_temp) &= ~(0xF << 16 * enhtim_id_odd);
+    if ((ENHTIM_ClockDiv_En != DISABLE))
+    {
+        *((uint32_t *)(&(REG_ENHTIMER_CLOCK_CTRL)) + enhtim_id_temp) |= BIT3 << 16 * enhtim_id_odd;
+        *((uint32_t *)(&(REG_ENHTIMER_CLOCK_CTRL)) + enhtim_id_temp) |= (ClockDiv << 16 * enhtim_id_odd);
+    }
+}
+
+void ENHTIM_PWMDeadZoneEMStop(ENHTIM_TypeDef *ENHTIMx)
+{
+    uint32_t enhtim_id = ENHTIM_GetTimerID(ENHTIMx);
+    ENHPWM_TypeDef *ENH_TIMx_PWM = ENHTIM_GetPwmID(enhtim_id);
+
+    ENH_TIMx_PWM->ENHTIMER_PWM_CFG |= PWM_EMG_STOP;
+}
+
+void ENHTIM_ConfigLatchTrigger(uint32_t enhtim_id, const ENHTIM_InitTypeDef *ENHTIM_InitStruct)
+{
+    uint8_t ENHTIM_LatchTriggerPad =  ENHTIM_InitStruct->ENHTIM_LatchTriggerPad;
+    uint32_t temp = 0xFF;
+
+    /* Config Latch Count0 trigger GPIO pin. */
+
+    if ((ENHTIM_LatchTriggerPad >= P0_0) && (ENHTIM_LatchTriggerPad <= P7_4))
+    {
+        temp = ENHTIM_LatchTriggerPad + 1;
+    }
+    else if ((ENHTIM_LatchTriggerPad >= MICBIAS) && (ENHTIM_LatchTriggerPad <= DACN))
+    {
+        temp = ENHTIM_LatchTriggerPad - 2;
+    }
+    else if ((ENHTIM_LatchTriggerPad >= P9_0) && (ENHTIM_LatchTriggerPad <= P10_2))
+    {
+        temp = ENHTIM_LatchTriggerPad - 5;
+    }
+
+    *((uint32_t *)(&(REG_ENHTIMER_0_LATCH_TRIG_CFG)) + enhtim_id) |= temp;
+
+    /* Config gpio trigger target enhtimer channel selection. */
+    *((uint32_t *)(&(REG_BT_GPIO_TRIG_ENHTIMER_CTRL))) &= ~0x7;
+    *((uint32_t *)(&(REG_BT_GPIO_TRIG_ENHTIMER_CTRL))) |= enhtim_id + 1;
+}
+
+void ENHTIM_ConfigLatchTriggerBtTxOn(uint32_t enhtim_id,
+                                     const ENHTIM_InitTypeDef *ENHTIM_InitStruct)
+{
+    /* Config bt tx on trigger target enhtimer channel selection. */
+    *((uint32_t *)(&(REG_BT_TX_ON_TRIG_ENHTIMER_CTRL))) &= ~0x7;
+    *((uint32_t *)(&(REG_BT_TX_ON_TRIG_ENHTIMER_CTRL))) |= enhtim_id + 1;
+}
+
+void ENHTIM_ConfigLatchTriggerBtAccHit(uint32_t enhtim_id,
+                                       const ENHTIM_InitTypeDef *ENHTIM_InitStruct)
+{
+    /* Config bt acc hit trigger target enhtimer channel selection. */
+    *((uint32_t *)(&(REG_BT_ACC_HIT_TRIG_ENHTIMER_CTRL))) &= ~0x7;
+    *((uint32_t *)(&(REG_BT_ACC_HIT_TRIG_ENHTIMER_CTRL))) |= enhtim_id + 1;
+}
+
+void ENHTIM_PWMDeadzoneConfig(uint32_t enhtim_id, \
+                              const ENHTIM_InitTypeDef *ENHTIM_InitStruct)
+{
+    ENHPWM_TypeDef *ENH_TIMx_PWM = ENHTIM_GetPwmID(enhtim_id);
+
+    uint32_t enhtim_id_odd = enhtim_id % 2;
+    uint32_t enhtim_id_temp = enhtim_id / 2;
+    uint8_t ENHTIM_PWMDeadZoneClockSource = ENHTIM_InitStruct->ENHTIM_PWMDeadZoneClockSource;
+    uint8_t  ENHTIM_PWMDeadZone_ClockDiv = ENHTIM_InitStruct->ENHTIM_PWMDeadZone_ClockDiv;
+    uint8_t ENHTIM_PWMDeadZoneEn = ENHTIM_InitStruct->ENHTIM_PWMDeadZoneEn;
+    uint32_t ENHTIM_DeadZoneSize = ENHTIM_InitStruct->ENHTIM_DeadZoneSize;
+    uint8_t ENHTIM_PWMStopStateP = ENHTIM_InitStruct->ENHTIM_PWMStopStateP;
+    uint8_t ENHTIM_PWMStopStateN = ENHTIM_InitStruct->ENHTIM_PWMStopStateN;
+    uint8_t ENHTIM_PWMDeadZone_ClockDivEn = ENHTIM_PWMDeadZone_ClockDiv == 0 ? DISABLE : ENABLE;
+
+    /* Set pwm1 deadzone mode, pwm1_pn based on enhance timer0 */
+
+    ENHTIMER_PWM_CFG_TypeDef enhpwm_cfg = {.d32 = ENH_TIMx_PWM->ENHTIMER_PWM_CFG};
+    if (ENHTIM_PWMDeadZoneEn == ENABLE)
+    {
+        *((uint32_t *)(&(REG_ENHTIMER_CLOCK_CTRL)) + enhtim_id_temp) |= BIT12 << 16 * enhtim_id_odd;
+        *((uint32_t *)(&(REG_ENHTIMER_CLOCK_CTRL)) + enhtim_id_temp) |= BIT13 << 16 * enhtim_id_odd;
+        *((uint32_t *)(&(REG_ENHTIMER_CLOCK_CTRL)) + enhtim_id_temp) |= ((ENHTIM_PWMDeadZoneClockSource)
+                                                                         << (11 + 16 * enhtim_id_odd));
+
+        if ((ENHTIM_PWMDeadZone_ClockDivEn != DISABLE))
+        {
+            *((uint32_t *)(&(REG_ENHTIMER_CLOCK_CTRL)) + enhtim_id_temp) |= BIT10 << 16 * enhtim_id_odd;
+            *((uint32_t *)(&(REG_ENHTIMER_CLOCK_CTRL)) + enhtim_id_temp) &= ~(0x7 << (7 + 16 * enhtim_id_odd));
+            *((uint32_t *)(&(REG_ENHTIMER_CLOCK_CTRL)) + enhtim_id_temp) |= ((ENHTIM_PWMDeadZone_ClockDiv) <<
+                                                                             (7 + 16 * enhtim_id_odd));
+        }
+        else
+        {
+            *((uint32_t *)(&(REG_ENHTIMER_CLOCK_CTRL)) + enhtim_id_temp) &= ~(BIT10 << 16 * enhtim_id_odd);
+        }
+
+        /* Enable pwm1 deadzone mode. */
+
+        ENH_TIMx_PWM->ENHTIMER_PWM_CFG &= ~0xFFFF;
+        enhpwm_cfg.b.enhtimer_pwm_dz_en = ENABLE;
+        enhpwm_cfg.b.enhtimer_pwm_dz_stop_state_p = ENHTIM_PWMStopStateP;
+        enhpwm_cfg.b.enhtimer_pwm_dz_stop_state_n = ENHTIM_PWMStopStateN;
+        enhpwm_cfg.b.enhtimer_pwm_dz_size = ENHTIM_DeadZoneSize;
+        ENH_TIMx_PWM->ENHTIMER_PWM_CFG = enhpwm_cfg.d32;
+    }
+    else
+    {
+        *((uint32_t *)(&REG_ENHTIMER_CLOCK_CTRL) + enhtim_id_temp) &= ~(BIT12 << 16 * enhtim_id_odd);
+        *((uint32_t *)(&REG_ENHTIMER_CLOCK_CTRL) + enhtim_id_temp) &= ~(BIT13 << 16 * enhtim_id_odd);
+
+        /* Disable pwm1 deadzone mode. */
+
+        enhpwm_cfg.b.enhtimer_pwm_dz_en = DISABLE;
+        ENH_TIMx_PWM->ENHTIMER_PWM_CFG = enhpwm_cfg.d32;
+    }
+}
+
+#if ENHTIM_SUPPORT_PWM_SRC_SELECT
+void ENHTIM_PWMSrcSelect(ENHTIM_TypeDef *ENHTIMx, ENHTIMPWMDZRef_TypeDef PWMSrcSel)
+{
+    uint32_t enhtim_id = ENHTIM_GetTimerID(ENHTIMx);
+    ENHPWM_TypeDef *ENH_TIMx_PWM = ENHTIM_GetPwmID(enhtim_id);
+
+    ENHTIMER_PWM_CFG_TypeDef enhtim_0x300 = {.d32 = ENH_TIMx_PWM->ENHTIMER_PWM_CFG};
+    enhtim_0x300.b.enhtimer_pwm_dz_ref_sel = PWMSrcSel;
+    ENH_TIMx_PWM->ENHTIMER_PWM_CFG = enhtim_0x300.d32;
+}
+#endif
+
+
+RAM_FUNCTION
+void ENHTIM_DLPSEnter(void *PeriReg, void *StoreBuf)
+{
+    ENHTIMStoreReg_Typedef *store_buf = (ENHTIMStoreReg_Typedef *)StoreBuf;
+
+    RCC_PeriphClockCmd(APBPeriph_ENHTIMER, APBPeriph_ENHTIMER_CLOCK, ENABLE);
+
+    store_buf->enhtim_reg[29] = PERIBLKCTRL_PERI_CLK->u_344.REG_ENHTIMER_1_0_CLOCK_CTRL;
+    store_buf->enhtim_reg[30] = PERIBLKCTRL_PERI_CLK->u_348.REG_ENHTIMER_3_2_CLOCK_CTRL;
+
+    store_buf->enhtim_reg[0] = ENH_TIM0->ENHTIM_CONFIGURE;
+    store_buf->enhtim_reg[1] = ENH_TIM0->ENHTIM_MAX_CNT;
+    store_buf->enhtim_reg[2] = ENH_TIM0->ENHTIM_CCR;
+    store_buf->enhtim_reg[3] = ENH_TIM0->ENHTIM_CCR_FIFO_ENTRY;
+
+    store_buf->enhtim_reg[4] = ENH_TIM1->ENHTIM_CONFIGURE;
+    store_buf->enhtim_reg[5] = ENH_TIM1->ENHTIM_MAX_CNT;
+    store_buf->enhtim_reg[6] = ENH_TIM1->ENHTIM_CCR;
+    store_buf->enhtim_reg[7] = ENH_TIM1->ENHTIM_CCR_FIFO_ENTRY;
+
+    store_buf->enhtim_reg[8]  = ENH_TIM2->ENHTIM_CONFIGURE;
+    store_buf->enhtim_reg[9]  = ENH_TIM2->ENHTIM_MAX_CNT;
+    store_buf->enhtim_reg[10] = ENH_TIM2->ENHTIM_CCR;
+    store_buf->enhtim_reg[11] = ENH_TIM2->ENHTIM_CCR_FIFO_ENTRY;
+
+    store_buf->enhtim_reg[12] = ENH_TIM3->ENHTIM_CONFIGURE;
+    store_buf->enhtim_reg[13] = ENH_TIM3->ENHTIM_MAX_CNT;
+    store_buf->enhtim_reg[14] = ENH_TIM3->ENHTIM_CCR;
+    store_buf->enhtim_reg[15] = ENH_TIM3->ENHTIM_CCR_FIFO_ENTRY;
+
+    store_buf->enhtim_reg[16] = ENH_TIM_SHARE->ENHTIM_FIFO_CLR;
+    store_buf->enhtim_reg[17] = ENH_TIM_SHARE->ENHTIM_CONTROL;
+    store_buf->enhtim_reg[18] = ENH_TIM_SHARE->ENHTIM_INT_CONTROL;
+    store_buf->enhtim_reg[19] = ENH_TIM_SHARE->ENHTIM_LATCH_INT_CONTROL_0;
+    store_buf->enhtim_reg[20] = ENH_TIM_SHARE->ENHTIM_LATCH_INT_CONTROL_2;
+
+    store_buf->enhtim_reg[21] = REG_ENHTIMER_0_LATCH_TRIG_CFG;
+    store_buf->enhtim_reg[22] = REG_ENHTIMER_1_LATCH_TRIG_CFG;
+    store_buf->enhtim_reg[23] = REG_ENHTIMER_2_LATCH_TRIG_CFG;
+    store_buf->enhtim_reg[24] = REG_ENHTIMER_3_LATCH_TRIG_CFG;
+    store_buf->enhtim_reg[25] = REG_BT_GPIO_TRIG_ENHTIMER_CTRL;
+    store_buf->enhtim_reg[26] = REG_BT_TX_ON_TRIG_ENHTIMER_CTRL;
+    store_buf->enhtim_reg[27] = REG_BT_ACC_HIT_TRIG_ENHTIMER_CTRL;
+    store_buf->enhtim_reg[28] = REG_ENHTIMER_ONESHOT;
+
+    store_buf->enhpwm_reg[0] = ENH_TIM0_PWM->ENHTIMER_PWM_CFG;
+    store_buf->enhpwm_reg[1] = ENH_TIM1_PWM->ENHTIMER_PWM_CFG;
+    store_buf->enhpwm_reg[2] = ENH_TIM2_PWM->ENHTIMER_PWM_CFG;
+    store_buf->enhpwm_reg[3] = ENH_TIM3_PWM->ENHTIMER_PWM_CFG;
+}
+
+RAM_FUNCTION
+void ENHTIM_DLPSExit(void *PeriReg, void *StoreBuf)
+{
+    ENHTIMStoreReg_Typedef *store_buf = (ENHTIMStoreReg_Typedef *)StoreBuf;
+
+    /* Enable timer IP clock and function */
+    RCC_PeriphClockCmd(APBPeriph_ENHTIMER, APBPeriph_ENHTIMER_CLOCK, ENABLE);
+    PERIBLKCTRL_PERI_CLK->u_344.REG_ENHTIMER_1_0_CLOCK_CTRL = store_buf->enhtim_reg[29];
+    PERIBLKCTRL_PERI_CLK->u_348.REG_ENHTIMER_3_2_CLOCK_CTRL = store_buf->enhtim_reg[30];
+
+    ENH_TIM0->ENHTIM_CONFIGURE      = store_buf->enhtim_reg[0];
+    ENH_TIM0->ENHTIM_MAX_CNT        = store_buf->enhtim_reg[1];
+    ENH_TIM0->ENHTIM_CCR            = store_buf->enhtim_reg[2];
+    ENH_TIM0->ENHTIM_CCR_FIFO_ENTRY = store_buf->enhtim_reg[3];
+
+    ENH_TIM1->ENHTIM_CONFIGURE      = store_buf->enhtim_reg[4];
+    ENH_TIM1->ENHTIM_MAX_CNT        = store_buf->enhtim_reg[5];
+    ENH_TIM1->ENHTIM_CCR            = store_buf->enhtim_reg[6];
+    ENH_TIM1->ENHTIM_CCR_FIFO_ENTRY = store_buf->enhtim_reg[7];
+
+    ENH_TIM2->ENHTIM_CONFIGURE      = store_buf->enhtim_reg[8];
+    ENH_TIM2->ENHTIM_MAX_CNT        = store_buf->enhtim_reg[9];
+    ENH_TIM2->ENHTIM_CCR            = store_buf->enhtim_reg[10];
+    ENH_TIM2->ENHTIM_CCR_FIFO_ENTRY = store_buf->enhtim_reg[11];
+
+    ENH_TIM3->ENHTIM_CONFIGURE      = store_buf->enhtim_reg[12];
+    ENH_TIM3->ENHTIM_MAX_CNT        = store_buf->enhtim_reg[13];
+    ENH_TIM3->ENHTIM_CCR            = store_buf->enhtim_reg[14];
+    ENH_TIM3->ENHTIM_CCR_FIFO_ENTRY = store_buf->enhtim_reg[15];
+
+    ENH_TIM_SHARE->ENHTIM_FIFO_CLR            = store_buf->enhtim_reg[16];
+    ENH_TIM_SHARE->ENHTIM_CONTROL             = store_buf->enhtim_reg[17] ;
+    ENH_TIM_SHARE->ENHTIM_INT_CONTROL         = store_buf->enhtim_reg[18];
+    ENH_TIM_SHARE->ENHTIM_LATCH_INT_CONTROL_0 = store_buf->enhtim_reg[19];
+    ENH_TIM_SHARE->ENHTIM_LATCH_INT_CONTROL_2 = store_buf->enhtim_reg[20];
+
+    REG_ENHTIMER_0_LATCH_TRIG_CFG     =  store_buf->enhtim_reg[21];
+    REG_ENHTIMER_1_LATCH_TRIG_CFG     =  store_buf->enhtim_reg[22];
+    REG_ENHTIMER_2_LATCH_TRIG_CFG     =  store_buf->enhtim_reg[23];
+    REG_ENHTIMER_3_LATCH_TRIG_CFG     =  store_buf->enhtim_reg[24];
+    REG_BT_GPIO_TRIG_ENHTIMER_CTRL    =  store_buf->enhtim_reg[25];
+    REG_BT_TX_ON_TRIG_ENHTIMER_CTRL   =  store_buf->enhtim_reg[26];
+    REG_BT_ACC_HIT_TRIG_ENHTIMER_CTRL =  store_buf->enhtim_reg[27];
+    REG_ENHTIMER_ONESHOT              =  store_buf->enhtim_reg[28];
+
+    ENH_TIM0_PWM->ENHTIMER_PWM_CFG = store_buf->enhpwm_reg[0];
+    ENH_TIM1_PWM->ENHTIMER_PWM_CFG = store_buf->enhpwm_reg[1];
+    ENH_TIM2_PWM->ENHTIMER_PWM_CFG = store_buf->enhpwm_reg[2];
+    ENH_TIM3_PWM->ENHTIMER_PWM_CFG = store_buf->enhpwm_reg[3];
+}
+
+
diff --git a/bee/drivers/timer/src/device/rtl87x2g/rtl87x2g_tim.c b/bee/drivers/timer/src/device/rtl87x2g/rtl87x2g_tim.c
new file mode 100644
index 00000000..a5206d62
--- /dev/null
+++ b/bee/drivers/timer/src/device/rtl87x2g/rtl87x2g_tim.c
@@ -0,0 +1,375 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *                        Header Files
+ *============================================================================*/
+#include "rtl_tim.h"
+#include "rtl_rcc.h"
+#include "app_section.h"
+
+/*============================================================================*
+ *                           Public Functions
+ *============================================================================*/
+uint32_t TIM_GetTimerID(TIM_TypeDef *TIMx)
+{
+    uint32_t tempreg = (uint32_t)TIMx;
+    uint32_t timerid = (tempreg - TIMER_REG_BASE) / 20;
+
+    return timerid;
+}
+
+bool TIM_ClkGet(TIM_TypeDef *TIMx, TIMClockSrc_TypeDef *ClockSrc, TIMClockDiv_TypeDef *ClockDiv)
+{
+    uint32_t tempreg = (uint32_t)TIMx;
+    uint32_t timerid = (tempreg - TIMER_REG_BASE) / 20;
+    uint32_t tim_id_odd = timerid % 2;
+    uint32_t tim_id_temp = timerid / 2;
+
+    if (timerid < 2)
+    {
+        *ClockSrc = TIM_CLOCK_SRC_40M;
+        *ClockDiv = ((TIMER_CLK_SOURCE_REG_328 >> ((timerid * 16) + 3)) & BIT0) == 0 ? 0 :
+                    ((TIMER_CLK_SOURCE_REG_328 >> (timerid * 16)) & 0x7);
+    }
+    else if ((timerid >= 2) && (timerid < 8))
+    {
+        uint32_t temp_addr_value = *((uint32_t *)(&(TIMER_CLK_SOURCE_REG_328)) + tim_id_temp);
+
+        if (((temp_addr_value >> (4 + 16 * tim_id_odd)) & BIT0) == 1)
+        {
+            *ClockSrc = TIM_CLOCK_SRC_PLL1;
+        }
+        else if (((temp_addr_value >> (12 + 16 * tim_id_odd)) & BIT0) == 1)
+        {
+            *ClockSrc = TIM_CLOCK_SRC_PLL2;
+        }
+        else
+        {
+            *ClockSrc = (temp_addr_value >> (13 + 16 * tim_id_odd) & BIT0);
+        }
+        *ClockDiv = (((temp_addr_value >> ((16 * tim_id_odd) + 3)) & BIT0) == 0) ? 0 :
+                    ((temp_addr_value >> (16 * tim_id_odd)) & 0x7);
+    }
+    else
+    {
+        return false;
+    }
+
+    return true;
+}
+
+void TIM_ClkConfig(TIM_TypeDef *TIMx, TIMClockSrc_TypeDef ClockSrc, TIMClockDiv_TypeDef ClockDiv)
+{
+    /* Select clock source which can be system clock or 40 MHz  or pll*/
+    uint32_t tempreg = (uint32_t)TIMx;
+    uint32_t timerid = (tempreg - TIMER_REG_BASE) / 20;
+    uint32_t tim_id_odd = timerid % 2;
+    uint32_t tim_id_temp = timerid / 2;
+    uint8_t ClockDivEn = ClockDiv == 0 ? DISABLE : ENABLE;
+
+    /*div the clock source,actually it need enable TIM_SOURCE_CLOCK_DIV_EN*/
+    if (timerid < 2)
+    {
+        /*set TIM clock src*/
+        if (ClockDivEn != DISABLE)
+        {
+            TIMER_CLK_SOURCE_REG_328 |= (0x1 << (3 + (timerid * 16)));
+            TIMER_CLK_SOURCE_REG_328 &= ~(0x7 << (timerid * 16));
+            TIMER_CLK_SOURCE_REG_328 |= ((ClockDiv) << (timerid * 16));
+        }
+        else
+        {
+            TIMER_CLK_SOURCE_REG_328 &= ~(0x1 << (3 + (timerid * 16)));
+        }
+    }
+    else if ((timerid >= 2) && (timerid < 8))
+    {
+        /*set TIM clock src*/
+        if (ClockSrc == TIM_CLOCK_SRC_PLL1)
+        {
+            *((uint32_t *)(&(TIMER_CLK_SOURCE_REG_328)) + tim_id_temp) |= ((BIT0) << (4 + 16 * tim_id_odd));
+        }
+        else if (ClockSrc == TIM_CLOCK_SRC_PLL2)
+        {
+            *((uint32_t *)(&(TIMER_CLK_SOURCE_REG_328)) + tim_id_temp) &= ~(BIT0 << (4 + (tim_id_odd * 16)));
+            *((uint32_t *)(&(TIMER_CLK_SOURCE_REG_328)) + tim_id_temp) |= ((BIT0) << (12 + 16 * tim_id_odd));
+        }
+        else
+        {
+            *((uint32_t *)(&(TIMER_CLK_SOURCE_REG_328)) + tim_id_temp) &= ~(BIT0 << (4 + (tim_id_odd * 16)));
+            *((uint32_t *)(&(TIMER_CLK_SOURCE_REG_328)) + tim_id_temp) &= ~(BIT0 << (12 + (tim_id_odd * 16)));
+            *((uint32_t *)(&(TIMER_CLK_SOURCE_REG_328)) + tim_id_temp) &= ~(BIT0 << (13 + (tim_id_odd * 16)));
+            *((uint32_t *)(&(TIMER_CLK_SOURCE_REG_328)) + tim_id_temp) |= (ClockSrc << (13 + 16 * tim_id_odd));
+        }
+
+        /*Clear TIM Clock DIV */
+        *((uint32_t *)(&(TIMER_CLK_SOURCE_REG_328)) + tim_id_temp) &= ~(0xF << 16 * tim_id_odd);
+        if ((ClockDivEn != DISABLE))
+        {
+            *((uint32_t *)(&(TIMER_CLK_SOURCE_REG_328)) + tim_id_temp) |= BIT3 << 16 * tim_id_odd;
+            *((uint32_t *)(&(TIMER_CLK_SOURCE_REG_328)) + tim_id_temp) |= (ClockDiv << 16 * tim_id_odd);
+        }
+        else
+        {
+            *((uint32_t *)(&(TIMER_CLK_SOURCE_REG_328)) + tim_id_temp) &= ~(BIT3 << 16 * tim_id_odd);
+        }
+
+    }
+}
+
+void TIM_SetHighLoadCount(TIM_TypeDef *TIMx, uint32_t TIM_PWM_High_Count)
+{
+    uint32_t timerid = TIM_GetTimerID(TIMx);
+
+    *(&TIMER0_LOAD_COUNT2 + timerid) = TIM_PWM_High_Count;
+}
+
+void TIM_PWMDeadzoneConfig(TIM_TypeDef *TIMx,
+                           uint8_t PWM_Deazone_ClockSrc, uint8_t PWM_Deadzone_DIV,
+                           uint8_t PWMDeadZone_En, uint32_t PWM_Deazone_Size,
+                           uint8_t PWM_Stop_State_P, uint8_t PWM_Stop_State_N)
+{
+    uint32_t timerid = TIM_GetTimerID(TIMx);
+
+    /* Set Pwm Deadzone Mode */
+    if (PWMDeadZone_En == ENABLE)
+    {
+        if (timerid  == 2)
+        {
+            PWM_Deazone_ClockSrc &= 0x1;
+            TIMER_PWM_CLK_CR &= ~(0X7 << 9);
+            TIMER_PWM_CLK_CR |= BIT10 | BIT11 | (PWM_Deazone_ClockSrc << 9);
+            /* set pwm deadzone time */
+            TIMER_PWM_CR &= ~0xFF;
+            TIMER_PWM_CR |= ((PWM_Deazone_Size) \
+                             | (PWM_Stop_State_N << 9) \
+                             | (PWM_Stop_State_P << 10) \
+                             | BIT12);
+        }
+        else if (timerid == 3)
+        {
+            TIMER_PWM_CLK_CR &= ~(0X7 << 25);
+            TIMER_PWM_CLK_CR |= ((BIT10 | BIT11 | (PWM_Deazone_ClockSrc << 9)) << 16);
+            /* set pwm deadzone time */
+            TIMER_PWM_CR &= ~(0xFF << 16);
+            TIMER_PWM_CR |= (((PWM_Deazone_Size) \
+                              | (PWM_Stop_State_N << 9) \
+                              | (PWM_Stop_State_P << 10) \
+                              | BIT12) << 16);
+        }
+    }
+    else
+    {
+        if (timerid == 2)
+        {
+            /*disable pwm0 deadzone mode*/
+            TIMER_PWM_CR &= ~(BIT12);
+            TIMER_PWM_CLK_CR &= ~(0X3 << 10);
+        }
+        else if (timerid == 3)
+        {
+            /*disable pwm1 deadzone mode*/
+            TIMER_PWM_CR &= ~(BIT28);
+            TIMER_PWM_CLK_CR &= ~(0X3 << 26);
+        }
+    }
+}
+
+void TIM_PWMComplOutputEMCmd(PWM_TypeDef *PWMx, FunctionalState NewState)
+{
+    /* Check the parameters. */
+    assert_param(IS_PWM_ALL_PERIPH(PWMx));
+
+    if (NewState != DISABLE)
+    {
+        if (PWMx  == PWM2)
+        {
+            /* PWM2 complementary output emergency stop. */
+            *((uint32_t *)TIMER_PWM_REG_BASE) |= BIT8;
+        }
+        else if (PWMx  == PWM3)
+        {
+            /* PWM3 complementary output emergency stop. */
+            *((uint32_t *)TIMER_PWM_REG_BASE) |= BIT24;
+        }
+    }
+    else
+    {
+        if (PWMx  == PWM2)
+        {
+            /* Resume PWM2 complementary output. */
+            *((uint32_t *)TIMER_PWM_REG_BASE) &= (~BIT8);
+        }
+        else if (PWMx  == PWM3)
+        {
+            /* Resume PWM3 complementary output. */
+            *((uint32_t *)TIMER_PWM_REG_BASE) &= (~BIT24);
+        }
+    }
+}
+
+void TIM_PWMDZBypassCmd(PWM_TypeDef *PWMx, FunctionalState NewState)
+{
+    /* Check the parameters. */
+    assert_param(IS_PWM_ALL_PERIPH(PWMx));
+
+    if (NewState != DISABLE)
+    {
+        if (PWMx  == PWM2)
+        {
+            /* Enable bypass dead zone function. */
+            *((uint32_t *)TIMER_PWM_REG_BASE) |= BIT13;
+        }
+        else if (PWMx  == PWM3)
+        {
+            /* Enable bypass dead zone function. */
+            *((uint32_t *)TIMER_PWM_REG_BASE) |= BIT29;
+        }
+    }
+    else
+    {
+        if (PWMx  == PWM2)
+        {
+            /* Disable bypass dead zone function. */
+            *((uint32_t *)TIMER_PWM_REG_BASE) &= (~BIT13);
+        }
+        else if (PWMx  == PWM3)
+        {
+            /* Disable bypass dead zone function. */
+            *((uint32_t *)TIMER_PWM_REG_BASE) &= (~BIT29);
+        }
+    }
+}
+
+void TIM_PWMChangeDZClockSrc(PWM_TypeDef *PWMx, PWMDZClockSrc_TypeDef PWM_Deazone_ClockSrc)
+{
+    /* Check the parameters. */
+    assert_param(IS_PWM_ALL_PERIPH(PWMx));
+
+    if (PWM_Deazone_ClockSrc == PWM_CK_32K_TIMER)
+    {
+        if (PWMx  == PWM2)
+        {
+            /* Use 5M clock source. */
+            TIMER_PWM_CLK_CR |= BIT9;
+        }
+        else if (PWMx  == PWM3)
+        {
+            /* Use 5M clock source. */
+            TIMER_PWM_CLK_CR |= BIT25;
+        }
+    }
+    else
+    {
+        if (PWMx  == PWM2)
+        {
+            /* Use 5M clock source. */
+            TIMER_PWM_CLK_CR &= (~BIT9);
+        }
+        else if (PWMx  == PWM3)
+        {
+            /* Use 5M clock source. */
+            TIMER_PWM_CLK_CR &= (~BIT25);
+        }
+    }
+}
+
+RAM_FUNCTION
+void TIM_DLPSEnter(void *PeriReg, void *StoreBuf)
+{
+    TIMStoreReg_Typedef *store_buf = (TIMStoreReg_Typedef *)StoreBuf;
+
+    /* Enable timer IP clock and function */
+    RCC_PeriphClockCmd(APBPeriph_TIMER, APBPeriph_TIMER_CLOCK, ENABLE);
+    store_buf->tim_reg[24] = PERIBLKCTRL_PERI_CLK->u_328.REG_TIMER_0_CLOCK_CTRL;
+    store_buf->tim_reg[25] = PERIBLKCTRL_PERI_CLK->u_32C.REG_TIMER_1_CLOCK_CTRL;
+    store_buf->tim_reg[26] = PERIBLKCTRL_PERI_CLK->u_330.REG_TIMER_2_CLOCK_CTRL;
+    store_buf->tim_reg[27] = PERIBLKCTRL_PERI_CLK->u_334.REG_TIMER_3_CLOCK_CTRL;
+
+    store_buf->tim_reg[0] = TIM0->TIMER_LOADCOUNT;
+    store_buf->tim_reg[1] = TIM0->TIMER_CONTROLREG;
+    store_buf->tim_reg[2] = TIMER0_LOAD_COUNT2;
+
+    store_buf->tim_reg[3] = TIM1->TIMER_LOADCOUNT;
+    store_buf->tim_reg[4] = TIM1->TIMER_CONTROLREG;
+    store_buf->tim_reg[5] = TIMER1_LOAD_COUNT2;
+
+    store_buf->tim_reg[6] = TIM2->TIMER_LOADCOUNT;
+    store_buf->tim_reg[7] = TIM2->TIMER_CONTROLREG;
+    store_buf->tim_reg[8] = TIMER2_LOAD_COUNT2;
+
+    store_buf->tim_reg[9]  = TIM3->TIMER_LOADCOUNT;
+    store_buf->tim_reg[10] = TIM3->TIMER_CONTROLREG;
+    store_buf->tim_reg[11] = TIMER3_LOAD_COUNT2;
+
+    store_buf->tim_reg[12] = TIM4->TIMER_LOADCOUNT;
+    store_buf->tim_reg[13] = TIM4->TIMER_CONTROLREG;
+    store_buf->tim_reg[14] = TIMER4_LOAD_COUNT2;
+
+    store_buf->tim_reg[15] = TIM5->TIMER_LOADCOUNT;
+    store_buf->tim_reg[16] = TIM5->TIMER_CONTROLREG;
+    store_buf->tim_reg[17] = TIMER5_LOAD_COUNT2;
+
+    store_buf->tim_reg[18] = TIM6->TIMER_LOADCOUNT;
+    store_buf->tim_reg[19] = TIM6->TIMER_CONTROLREG;
+    store_buf->tim_reg[20] = TIMER6_LOAD_COUNT2;
+
+    store_buf->tim_reg[21] = TIM7->TIMER_LOADCOUNT;
+    store_buf->tim_reg[22] = TIM7->TIMER_CONTROLREG;
+    store_buf->tim_reg[23] = TIMER7_LOAD_COUNT2;
+
+    store_buf->tim_reg[28] = PERIBLKCTRL_PERI_CLK->u_33C.REG_TIMER_PWM_WRAP_1_CFG;
+}
+
+RAM_FUNCTION
+void TIM_DLPSExit(void *PeriReg, void *StoreBuf)
+{
+    TIMStoreReg_Typedef *store_buf = (TIMStoreReg_Typedef *)StoreBuf;
+
+    /* Enable timer IP clock and function */
+    RCC_PeriphClockCmd(APBPeriph_TIMER, APBPeriph_TIMER_CLOCK, ENABLE);
+    PERIBLKCTRL_PERI_CLK->u_328.REG_TIMER_0_CLOCK_CTRL = store_buf->tim_reg[24];
+    PERIBLKCTRL_PERI_CLK->u_32C.REG_TIMER_1_CLOCK_CTRL = store_buf->tim_reg[25];
+    PERIBLKCTRL_PERI_CLK->u_330.REG_TIMER_2_CLOCK_CTRL = store_buf->tim_reg[26];
+    PERIBLKCTRL_PERI_CLK->u_334.REG_TIMER_3_CLOCK_CTRL = store_buf->tim_reg[27];
+
+    TIM0->TIMER_LOADCOUNT  = store_buf->tim_reg[0];
+    TIM0->TIMER_CONTROLREG = store_buf->tim_reg[1];
+    TIMER0_LOAD_COUNT2     = store_buf->tim_reg[2];
+
+    TIM1->TIMER_LOADCOUNT  = store_buf->tim_reg[3];
+    TIM1->TIMER_CONTROLREG = store_buf->tim_reg[4];
+    TIMER1_LOAD_COUNT2     = store_buf->tim_reg[5];
+
+    TIM2->TIMER_LOADCOUNT  = store_buf->tim_reg[6];
+    TIM2->TIMER_CONTROLREG = store_buf->tim_reg[7];
+    TIMER2_LOAD_COUNT2     = store_buf->tim_reg[8];
+
+    TIM3->TIMER_LOADCOUNT  = store_buf->tim_reg[9];
+    TIM3->TIMER_CONTROLREG = store_buf->tim_reg[10];
+    TIMER3_LOAD_COUNT2     = store_buf->tim_reg[11];
+
+    TIM4->TIMER_LOADCOUNT  = store_buf->tim_reg[12];
+    TIM4->TIMER_CONTROLREG = store_buf->tim_reg[13];
+    TIMER4_LOAD_COUNT2     = store_buf->tim_reg[14];
+
+    TIM5->TIMER_LOADCOUNT  = store_buf->tim_reg[15];
+    TIM5->TIMER_CONTROLREG = store_buf->tim_reg[16];
+    TIMER5_LOAD_COUNT2     = store_buf->tim_reg[17];
+
+    TIM6->TIMER_LOADCOUNT  = store_buf->tim_reg[18];
+    TIM6->TIMER_CONTROLREG = store_buf->tim_reg[19];
+    TIMER6_LOAD_COUNT2     = store_buf->tim_reg[20];
+
+    TIM7->TIMER_LOADCOUNT  = store_buf->tim_reg[21];
+    TIM7->TIMER_CONTROLREG = store_buf->tim_reg[22];
+    TIMER7_LOAD_COUNT2     = store_buf->tim_reg[23];
+
+    PERIBLKCTRL_PERI_CLK->u_33C.REG_TIMER_PWM_WRAP_1_CFG = store_buf->tim_reg[28];
+}
+
+
diff --git a/bee/drivers/timer/src/device/rtl87x2g/rtl_enh_tim.c b/bee/drivers/timer/src/device/rtl87x2g/rtl_enh_tim.c
new file mode 100644
index 00000000..4a601a77
--- /dev/null
+++ b/bee/drivers/timer/src/device/rtl87x2g/rtl_enh_tim.c
@@ -0,0 +1,741 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *                        Header Files
+ *============================================================================*/
+#include "rtl_enh_tim.h"
+
+/*============================================================================*
+ *                          Private Defines
+ *============================================================================*/
+#define  ENHTIM_DMAC_FLOW_CONTROL  0x00
+
+/*============================================================================*
+ *                          Private Functions
+ *============================================================================*/
+extern uint32_t ENHTIM_GetTimerID(ENHTIM_TypeDef *ENHTIMx);
+
+extern void ENHTIM_ConfigLatchTrigger(uint32_t enhtim_id, \
+                                      const ENHTIM_InitTypeDef *ENHTIM_InitStruct);
+extern void ENHTIM_ConfigLatchTriggerBtTxOn(uint32_t enhtim_id,
+                                            const ENHTIM_InitTypeDef *ENHTIM_InitStruct);
+extern void ENHTIM_ConfigLatchTriggerBtAccHit(uint32_t enhtim_id,
+                                              const ENHTIM_InitTypeDef *ENHTIM_InitStruct);
+extern void ENHTIM_PWMDeadzoneConfig(uint32_t enhtim_id, \
+                                     const ENHTIM_InitTypeDef *ENHTIM_InitStruct);
+
+/*============================================================================*
+ *                           Public Functions
+ *============================================================================*/
+/**
+  * \brief  Initializes the ENHTIMx peripheral according to
+  *         the specified parameters in the ENHTIM_InitStruct.
+  * \param  ENHTIMx: Select the ENHTIM peripheral. \ref ENHTIM_Declaration
+  * \param  ENHTIM_InitStruct: pointer to a ENHTIM_InitTypeDef structure
+  *         that contains the configuration information for the specified ENHTIM peripheral.
+  * \return None
+  */
+void ENHTIM_Init(ENHTIM_TypeDef *ENHTIMx, ENHTIM_InitTypeDef *ENHTIM_InitStruct)
+{
+    /* Check the parameters */
+    assert_param(IS_ENHTIM_ALL_PERIPH(ENHTIMx));
+
+    uint32_t enhtim_id = ENHTIM_GetTimerID(ENHTIMx);
+
+    /* Clock source config */
+    ENH_TIM_SHARE->ENHTIM_CONTROL &= ~BIT(enhtim_id);
+    ENH_TIM_SHARE->ENHTIM_INT_CONTROL &= ~BIT(enhtim_id);
+
+    /* Clock source config */
+    ENHTIM_ClkConfig(ENHTIMx,
+                     ENHTIM_InitStruct->ENHTIM_ClockSource,
+                     ENHTIM_InitStruct->ENHTIM_ClockDiv);
+
+#if ENHTIM_SUPPORT_ONESHOT_CMD
+    if (ENHTIM_InitStruct->ENHTIM_OneShotEn == ENABLE)
+    {
+        REG_ENHTIMER_ONESHOT |= BIT(enhtim_id);
+    }
+    else
+    {
+        REG_ENHTIMER_ONESHOT &= ~BIT(enhtim_id);
+    }
+#endif
+    /* Config latch function. */
+    ENHTIM_CONFIGURE_TypeDef enhtim_0x10 = {.d32 = ENHTIMx->ENHTIM_CONFIGURE};
+    enhtim_0x10.b.Enhtimer_mode = 0x0;
+    ENHTIMx->ENHTIM_CONFIGURE = enhtim_0x10.d32;
+
+    enhtim_0x10.d32 = ENHTIMx->ENHTIM_CONFIGURE;
+#if ENHTIM_SUPPORT_LATCH_CNT_0
+    enhtim_0x10.b.Enhtimer_Latch_cnt_0_en = ENHTIM_InitStruct->ENHTIM_LatchCountEn[0] & 0x01;
+    enhtim_0x10.b.Enhtimer_latch_cnt_0_trig_mode = ENHTIM_InitStruct->ENHTIM_LatchCountTrigger[0] &
+                                                   0x03;
+    enhtim_0x10.b.Enhtimer_latch_cnt_0_fifo_th = ENHTIM_InitStruct->ENHTIM_LatchCountThd & 0x1F;
+#endif
+#if ENHTIM_SUPPORT_LATCH_CNT_1
+    enhtim_0x10.b.Enhtimer_Latch_cnt_1_en = ENHTIM_InitStruct->ENHTIM_LatchCountEn[1] & 0x01;
+    enhtim_0x10.b.Enhtimer_latch_cnt_1_trig_mode = ENHTIM_InitStruct->ENHTIM_LatchCountTrigger[1] &
+                                                   0x03;
+#endif
+#if ENHTIM_SUPPORT_LATCH_CNT_2
+    enhtim_0x10.b.Enhtimer_Latch_cnt_2_en = ENHTIM_InitStruct->ENHTIM_LatchCountEn[2] & 0x01;
+    enhtim_0x10.b.Enhtimer_latch_cnt_2_trig_mode = ENHTIM_InitStruct->ENHTIM_LatchCountTrigger[2] &
+                                                   0x03;
+#endif
+    ENHTIMx->ENHTIM_CONFIGURE = enhtim_0x10.d32;
+
+    /* Config latch trigger. */
+#if ENHTIM_SUPPORT_LATCH_CNT_0
+    if (ENHTIM_InitStruct->ENHTIM_LatchCountEn[0] == ENABLE)
+    {
+        ENHTIM_ConfigLatchTrigger(enhtim_id, ENHTIM_InitStruct);
+    }
+#endif
+#if ENHTIM_SUPPORT_LATCH_CNT_1
+    if (ENHTIM_InitStruct->ENHTIM_LatchCountEn[1] == ENABLE)
+    {
+        ENHTIM_ConfigLatchTriggerBtTxOn(enhtim_id, ENHTIM_InitStruct);
+    }
+#endif
+#if ENHTIM_SUPPORT_LATCH_CNT_2
+    if (ENHTIM_InitStruct->ENHTIM_LatchCountEn[2] == ENABLE)
+    {
+        ENHTIM_ConfigLatchTriggerBtAccHit(enhtim_id, ENHTIM_InitStruct);
+    }
+#endif
+
+    /* Config PWM mode. */
+    if ((ENHTIM_InitStruct->ENHTIM_Mode == ENHTIM_MODE_PWM_AUTO) ||
+        (ENHTIM_InitStruct->ENHTIM_Mode == ENHTIM_MODE_PWM_MANUAL))
+    {
+        enhtim_0x10.d32 = ENHTIMx->ENHTIM_CONFIGURE;
+        enhtim_0x10.b.Enhtimer_PWM_polarity = ENHTIM_InitStruct->ENHTIM_PWMStartPolarity;
+        enhtim_0x10.b.Enhtimer_PWM_output_en = ENHTIM_InitStruct->ENHTIM_PWMOutputEn;
+        enhtim_0x10.b.Enhtimer_mode = ENHTIM_InitStruct->ENHTIM_Mode;
+        ENHTIMx->ENHTIM_CONFIGURE = enhtim_0x10.d32;
+
+        ENHTIM_MAX_CNT_TypeDef enhtim_0x14 = {.d32 = ENHTIMx->ENHTIM_MAX_CNT};
+        enhtim_0x14.b.Enhtimer_max_cnt = ENHTIM_InitStruct->ENHTIM_MaxCount;
+        ENHTIMx->ENHTIM_MAX_CNT = enhtim_0x14.d32;
+    }
+
+    if (ENHTIM_InitStruct->ENHTIM_Mode == ENHTIM_MODE_PWM_MANUAL)
+    {
+        ENHTIM_CCR_TypeDef enhtim_0x18 = {.d32 = ENHTIMx->ENHTIM_CCR};
+        enhtim_0x18.b.Enhtimer_ccr = ENHTIM_InitStruct->ENHTIM_CCValue;
+        ENHTIMx->ENHTIM_CCR = enhtim_0x18.d32;
+    }
+
+    /* Config PWM Deadzone */
+    ENHTIM_PWMDeadzoneConfig(enhtim_id, ENHTIM_InitStruct);
+
+    /* DMA function. */
+    if (ENHTIM_InitStruct->ENHTIM_DmaEn != DISABLE)
+    {
+        enhtim_0x10.b.Enhtimer_dma_en = ENABLE;
+        enhtim_0x10.b.Enhtimer_dma_mode = ENHTIM_DMAC_FLOW_CONTROL;
+        enhtim_0x10.b.Enhtimer_dma_target = ENHTIM_InitStruct->ENHTIM_DmaTragget;
+        ENHTIMx->ENHTIM_CONFIGURE = enhtim_0x10.d32;
+    }
+
+    /* Clear the IT status */
+    ENH_TIM_SHARE->ENHTIM_LACTH_FIFO_TH_STATUS |= BIT(enhtim_id);
+    ENH_TIM_SHARE->ENHTIM_LATCH_CNT_FIFO_STATUS |= BIT(enhtim_id * 2);
+    ENH_TIM_SHARE->ENHTIM_STATUS |= BIT(enhtim_id);
+    ENH_TIM_SHARE->ENHTIM_STATUS |= BIT(enhtim_id + 8);
+}
+
+/**
+  * \brief  Fills each ENHTIM_InitStruct member with its default value.
+  * \param  ENHTIM_InitStruct: Pointer to a ENHTIM_InitStruct structure which will be initialized.
+  * \return None.
+  */
+void ENHTIM_StructInit(ENHTIM_InitTypeDef *ENHTIM_InitStruct)
+{
+    ENHTIM_InitStruct->ENHTIM_ClockSource           = ENHTIM_CLOCK_SOURCE_40M;
+    ENHTIM_InitStruct->ENHTIM_ClockDiv_En           = DISABLE;
+    ENHTIM_InitStruct->ENHTIM_ClockDiv              = ENHTIM_CLOCK_DIVIDER_1;
+    ENHTIM_InitStruct->ENHTIM_Mode                  = ENHTIM_MODE_FreeRun;
+    ENHTIM_InitStruct->ENHTIM_PWMOutputEn           = DISABLE;
+    ENHTIM_InitStruct->ENHTIM_PWMStartPolarity      = ENHTIM_PWM_START_WITH_LOW;
+#if ENHTIM_SUPPORT_ONESHOT_CMD
+    ENHTIM_InitStruct->ENHTIM_OneShotEn             = DISABLE;
+#endif
+#if ENHTIM_SUPPORT_LATCH_CNT_0
+    ENHTIM_InitStruct->ENHTIM_LatchCountEn[0]       = DISABLE;
+    ENHTIM_InitStruct->ENHTIM_LatchCountTrigger[0]  = ENHTIM_LATCH_TRIGGER_RISING_EDGE;
+#endif
+#if ENHTIM_SUPPORT_LATCH_CNT_1
+    ENHTIM_InitStruct->ENHTIM_LatchCountEn[1]       = DISABLE;
+    ENHTIM_InitStruct->ENHTIM_LatchCountTrigger[1]  = ENHTIM_LATCH_TRIGGER_RISING_EDGE;
+#endif
+#if ENHTIM_SUPPORT_LATCH_CNT_2
+    ENHTIM_InitStruct->ENHTIM_LatchCountEn[2]       = DISABLE;
+    ENHTIM_InitStruct->ENHTIM_LatchCountTrigger[2]  = ENHTIM_LATCH_TRIGGER_RISING_EDGE;
+#endif
+    ENHTIM_InitStruct->ENHTIM_LatchCountThd         = 3;
+    ENHTIM_InitStruct->ENHTIM_LatchTriggerPad       = P0_0;
+    ENHTIM_InitStruct->ENHTIM_MaxCount              = 0xFFFFFFFE;//range 0x1~0xFFFFFFFE
+    ENHTIM_InitStruct->ENHTIM_CCValue               = 0x0;
+
+    ENHTIM_InitStruct->ENHTIM_PWMDeadZoneClockSource    = ENHTIM_PWM_DZCLKSRCE_32K;
+    ENHTIM_InitStruct->ENHTIM_PWMDeadZone_ClockDivEn    = DISABLE;
+    ENHTIM_InitStruct->ENHTIM_PWMDeadZone_ClockDiv      = ENHTIM_CLOCK_DIVIDER_1;
+    ENHTIM_InitStruct->ENHTIM_PWMDeadZoneEn             = DISABLE;
+    ENHTIM_InitStruct->ENHTIM_PWMStopStateP             = ENHTIM_PWM_STOP_AT_HIGH;
+    ENHTIM_InitStruct->ENHTIM_PWMStopStateN             = ENHTIM_PWM_STOP_AT_LOW;
+    ENHTIM_InitStruct->ENHTIM_DeadZoneSize              = 0xFF;/*!< range 0x1 ~ 0xFF */
+    ENHTIM_InitStruct->ENHTIM_DmaEn                   = DISABLE;
+
+    ENHTIM_InitStruct->ENHTIM_DmaTragget              = ENHTIM_DMA_CCR_FIFO;
+}
+
+/**
+  * \brief  Enable or disable the specified ENHTIM peripheral.
+  * \param  ENHTIMx: Select the ENHTIM peripheral. \ref ENHTIM_Declaration
+  * \param  NewState: New state of the ENHTIMx peripheral.
+  *         This parameter can be: ENABLE or DISABLE.
+  * \return None.
+  */
+void ENHTIM_Cmd(ENHTIM_TypeDef *ENHTIMx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_ENHTIM_ALL_PERIPH(ENHTIMx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    uint32_t enhtim_id = ENHTIM_GetTimerID(ENHTIMx);
+
+    if (NewState != DISABLE)
+    {
+        /* Enable the TIM Counter */
+        ENH_TIM_SHARE->ENHTIM_CONTROL |= BIT(enhtim_id);
+    }
+    else
+    {
+        /* Disable the TIM Counter */
+        ENH_TIM_SHARE->ENHTIM_CONTROL &= ~(BIT(enhtim_id));
+    }
+}
+
+/**
+  * \brief  Enable or disable the specified ENHTIM peripheral.
+  * \param  ENHTIMx: Select the ENHTIM peripheral. \ref ENHTIM_Declaration
+  * \param  NewState: New state of the ENHTIMx peripheral.
+  *         This parameter can be: ENABLE or DISABLE.
+  * \return None.
+  */
+#if ENHTIM_SUPPORT_ONESHOT_CMD
+void ENHTIM_OneShotCmd(ENHTIM_TypeDef *ENHTIMx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_ENHTIM_ALL_PERIPH(ENHTIMx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    uint32_t enhtim_id = ENHTIM_GetTimerID(ENHTIMx);
+
+    if (NewState != DISABLE)
+    {
+        /*oneshot_mode_en*/
+        REG_ENHTIMER_ONESHOT |= BIT(enhtim_id);
+
+        /* Enable the TIM Counter */
+        ENH_TIM_SHARE->ENHTIM_CONTROL |= BIT(enhtim_id);
+
+        /*oneshot_mode_go*/
+        REG_ENHTIMER_ONESHOT |= BIT(enhtim_id + 8);
+    }
+    else
+    {
+        /*oneshot_mode_en*/
+        REG_ENHTIMER_ONESHOT &= ~BIT(enhtim_id);
+
+        /* Disable the TIM Counter */
+        ENH_TIM_SHARE->ENHTIM_CONTROL &= ~(BIT(enhtim_id));
+
+        /*oneshot_mode_en*/
+        REG_ENHTIMER_ONESHOT &= ~BIT(enhtim_id + 8);
+    }
+}
+#endif
+
+/**
+  * \brief  Enable or disable ENHTIMx interrupt.
+  * \param  ENHTIMx: Select the ENHTIM peripheral. \ref ENHTIM_Declaration
+  * \param  ENHTIM_INT: Specifies the ENHTIMx interrupt source which to be enabled or disabled.
+  *         This parameter can be one of the following values:
+  *         \arg ENHTIM_INT_TIM: Enhance Timer interrupt source.
+  *         \arg ENHTIM_INT_LATCH_CNT_FIFO_FULL: Enhance Timer latch count0 interrupt source.
+  *         \arg ENHTIM_INT_LATCH_CNT_FIFO_THD: Enhance Timer latch count0 interrupt source.
+  * \param  NewState: New state of the ENHTIMx peripheral.
+  *         This parameter can be: ENABLE or DISABLE.
+  * \return None.
+  */
+void ENHTIM_INTConfig(ENHTIM_TypeDef *ENHTIMx, uint8_t ENHTIM_INT, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_ENHTIM_ALL_PERIPH(ENHTIMx));
+    assert_param(IS_ENHTIM_INT(ENHTIM_INT));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    uint32_t enhtim_id = ENHTIM_GetTimerID(ENHTIMx);
+
+    if (NewState != DISABLE)
+    {
+        /* Enable the ENHTIM Interrupt */
+        if (ENHTIM_INT == ENHTIM_INT_LATCH_CNT_FIFO_FULL)
+        {
+            ENH_TIM_SHARE->ENHTIM_LATCH_INT_CONTROL_0 |= BIT(8) << enhtim_id;
+        }
+        else if (ENHTIM_INT == ENHTIM_INT_LATCH_CNT_FIFO_THD)
+        {
+            ENH_TIM_SHARE->ENHTIM_LATCH_INT_CONTROL_2 |= BIT(8) << enhtim_id;
+        }
+        else
+        {
+            ENH_TIM_SHARE->ENHTIM_INT_CONTROL |= BIT(enhtim_id);
+        }
+    }
+    else
+    {
+        /* Disable the ENHTIM Interrupt */
+        if (ENHTIM_INT == ENHTIM_INT_LATCH_CNT_FIFO_FULL)
+        {
+            ENH_TIM_SHARE->ENHTIM_LATCH_INT_CONTROL_0 &= ~(BIT(8) << enhtim_id);
+        }
+        else if (ENHTIM_INT == ENHTIM_INT_LATCH_CNT_FIFO_THD)
+        {
+            ENH_TIM_SHARE->ENHTIM_LATCH_INT_CONTROL_2 &= ~ BIT(8) << enhtim_id;
+        }
+        else
+        {
+            ENH_TIM_SHARE->ENHTIM_INT_CONTROL &= ~BIT(enhtim_id);
+        }
+    }
+}
+
+/**
+  * \brief  Check whether the ENHTIM latch count0 fifo has data or not.
+  * \param  ENHTIMx: Select the ENHTIM peripheral. \ref ENHTIM_Declaration
+  * \return The new state of the specified ENHTIMx peripheral
+  *         latch count0 fifo (SET or RESET).
+  */
+ITStatus ENHTIM_GetLCFIFOStatus(ENHTIM_TypeDef *ENHTIMx)
+{
+    /* Check the parameters */
+    assert_param(IS_ENHTIM_ALL_PERIPH(ENHTIMx));
+
+    uint32_t enhtim_id = ENHTIM_GetTimerID(ENHTIMx);
+
+    if (ENH_TIM_SHARE->ENHTIM_STATUS & ((BIT(8) << enhtim_id)))
+    {
+        return SET;
+    }
+
+    return RESET;
+}
+
+/**
+  * \brief  Read ENHTIMx latch counter fifo data.
+  * \param  ENHTIMx: Select the ENHTIM peripheral. \ref ENHTIM_Declaration
+  * \param  length: Latch count0 fifo length, max 32.
+  * \pBuf   pBuf: FIFO data out buffer.
+  * \return None.
+  */
+void ENHTIM_ReadLatchCountFIFO(ENHTIM_TypeDef *ENHTIMx, uint32_t *pBuf, uint8_t length)
+{
+    /* Check the parameters */
+    assert_param(IS_ENHTIM_ALL_PERIPH(ENHTIMx));
+
+    if ((pBuf == 0) || (length > 31))
+    {
+        return;
+    }
+
+    for (uint8_t i = 0; i < length; i++)
+    {
+        pBuf[i] = ENHTIMx->ENHTIM_LATCH_CNT_0;
+    }
+}
+
+/**
+  * \brief  Check whether the ENHTIM interrupt has occurred or not.
+  * \param  ENHTIMx: Select the ENHTIM peripheral. \ref ENHTIM_Declaration
+  * \param  ENHTIM_INT: Specifies the ENHTIMx interrupt source which to be enabled or disabled.
+  *         This parameter can be one of the following values:
+  *         \arg ENHTIM_INT_TIM: Enhance Timer interrupt source.
+  *         \arg ENHTIM_INT_LATCH_CNT_FIFO_FULL: Enhance Timer latch count0 fifo full interrupt source.
+  *         \arg ENHTIM_INT_LATCH_CNT_FIFO_EMPTY: Enhance Timer latch count0 fifo empty interrupt source.
+  *         \arg ENHTIM_INT_LATCH_CNT_FIFO_THD: Enhance Timer latch count0 fifo threshold interrupt source.
+  * \return The new state of the ENHTIM_INT(SET or RESET).
+  */
+ITStatus ENHTIM_GetINTStatus(ENHTIM_TypeDef *ENHTIMx, uint8_t ENHTIM_INT)
+{
+    /* Check the parameters */
+    assert_param(IS_ENHTIM_ALL_PERIPH(ENHTIMx));
+    assert_param(IS_ENHTIM_INT(INT));
+
+    uint32_t enhtim_id = ENHTIM_GetTimerID(ENHTIMx);
+    ITStatus itstatus = RESET;
+
+    if (ENHTIM_INT == ENHTIM_INT_TIM)
+    {
+        itstatus = (ITStatus)((ENH_TIM_SHARE->ENHTIM_STATUS) >> (enhtim_id));
+    }
+    else if (ENHTIM_INT == ENHTIM_INT_LATCH_CNT_FIFO_FULL)
+    {
+        itstatus = (ITStatus)(((ENH_TIM_SHARE->ENHTIM_LATCH_CNT_FIFO_STATUS) >> (enhtim_id * 2)) & 0x01);
+    }
+    else if (ENHTIM_INT == ENHTIM_INT_LATCH_CNT_FIFO_THD)
+    {
+        itstatus = (ITStatus)(((ENH_TIM_SHARE->ENHTIM_LACTH_FIFO_TH_STATUS) >> (enhtim_id)) & 0x01);
+    }
+    else if (ENHTIM_INT == ENHTIM_INT_LATCH_CNT_FIFO_EMPTY)
+    {
+        itstatus = (ITStatus)(((ENH_TIM_SHARE->ENHTIM_LATCH_CNT_FIFO_STATUS) >>
+                               (1 + enhtim_id * 2)) & 0x01);
+    }
+
+    return itstatus;
+}
+
+/**
+  * \brief  Clear ENHTIM interrupt.
+  * \param  ENHTIMx: Select the ENHTIM peripheral. \ref ENHTIM_Declaration
+  * \param  ENHTIM_INT: Specifies the ENHTIMx interrupt source which to be enabled or disabled.
+  *         This parameter can be one of the following values:
+  *         \arg ENHTIM_INT_TIM: Enhance Timer interrupt source.
+  *         \arg ENHTIM_INT_LATCH_CNT_FIFO_FULL: Enhance Timer latch count0 fifo full interrupt source.
+  *         \arg ENHTIM_INT_LATCH_CNT_FIFO_THD: Enhance Timer latch count0 fifo threshold interrupt source.
+  * \return None.
+ */
+void ENHTIM_ClearINTPendingBit(ENHTIM_TypeDef *ENHTIMx, uint8_t ENHTIM_INT)
+{
+    /* Check the parameters */
+    assert_param(IS_ENHTIM_ALL_PERIPH(ENHTIMx));
+
+    uint32_t enhtim_id = ENHTIM_GetTimerID(ENHTIMx);
+
+    /* Clear the IT */
+    if (ENHTIM_INT == ENHTIM_INT_TIM)
+    {
+        ENH_TIM_SHARE->ENHTIM_STATUS |= BIT(enhtim_id);
+    }
+    else if (ENHTIM_INT == ENHTIM_INT_LATCH_CNT_FIFO_FULL)
+    {
+        ENH_TIM_SHARE->ENHTIM_LATCH_CNT_FIFO_STATUS |= BIT(enhtim_id * 2);
+    }
+    else if (ENHTIM_INT == ENHTIM_INT_LATCH_CNT_FIFO_THD)
+    {
+        ENH_TIM_SHARE->ENHTIM_LACTH_FIFO_TH_STATUS |= BIT(enhtim_id);
+    }
+}
+
+/**
+  * \brief  Change ENHTIME PWM freq and duty according high_cnt
+  * \param  ENHTIMx: Select the ENHTIM peripheral. \ref ENHTIM_Declaration
+  * \param  enhtim_mode: This parameter can be ENHTIM_MODE_PWM_MANUAL or ENHTIM_MODE_PWM_AUTO.
+  * \param  max_count: Timer max counter value for user-define mode
+  *         This parameter can be 1 ~ 2^32-2
+  * \param  high_count: Timer capture/compare value for user-define manual mode or timer capture/compare fifo entry for user-define auto mode.
+  *         This parameter can be 0 ~ 2^32-2
+  * \return None
+  */
+void ENHTIM_PWMChangeFreqAndDuty(ENHTIM_TypeDef *ENHTIMx, uint16_t enhtim_mode, uint32_t max_count,
+                                 uint32_t high_count)
+{
+    /* Check the parameters */
+    assert_param(IS_ENHTIM_ALL_PERIPH(ENHTIMx));
+
+    ENHTIMx->ENHTIM_MAX_CNT = max_count;
+
+    if (enhtim_mode == ENHTIM_MODE_PWM_MANUAL)
+    {
+        ENHTIMx->ENHTIM_CCR = high_count;
+    }
+    else if (enhtim_mode == ENHTIM_MODE_PWM_AUTO)
+    {
+        ENHTIMx->ENHTIM_CCR_FIFO_ENTRY = high_count;
+    }
+}
+
+/**
+  * \brief  Get ENHTIME toggle state
+  * \param  ENHTIMx: Select the ENHTIM peripheral. \ref ENHTIM_Declaration
+  * \return The new state of toggle state(SET or RESET).
+  */
+bool ENHTIM_GetToggleState(ENHTIM_TypeDef *ENHTIMx)
+{
+    /* Check the parameters */
+    assert_param(IS_ENHTIM_ALL_PERIPH(ENHTIMx));
+
+    uint32_t enhtim_id = ENHTIM_GetTimerID(ENHTIMx);
+
+    if (((ENH_TIM_SHARE->ENHTIM_TOGGLE_STATE)&BIT(enhtim_id)) != 0)
+    {
+        return true;
+    }
+    else
+    {
+        return false;
+    }
+}
+
+/**
+  * \brief  Change Enhtimer pwm_phase_shift count
+  * \param  ENHTIMx: Select the ENHTIM peripheral. \ref ENHTIM_Declaration
+  * \param  PhaseShiftCnt:This parameter can be 0 to ccr ;
+  * \return None
+  */
+#if ENHTIM_SUPPORT_PWM_PHASE_SHIFT
+void ENHTIM_PhaseShiftCnt(ENHTIM_TypeDef *ENHTIMx, uint32_t PhaseShiftCnt)
+{
+    assert_param(IS_ENHTIM_ALL_PERIPH(ENHTIMx));
+    if (PhaseShiftCnt > 0xFFFFFFFF)
+    {
+        PhaseShiftCnt = 0xFFFFFFFF;
+    }
+    ENHTIMx->PHASE_SHIFT_CNT  =  PhaseShiftCnt ;
+}
+#endif
+
+/**
+  * \brief  Get Enhtimer current count
+  * \param  ENHTIMx: Select the ENHTIM peripheral. \ref ENHTIM_Declaration
+  * \return None
+  */
+uint32_t ENHTIM_GetCurrentCount(ENHTIM_TypeDef *ENHTIMx)
+{
+    /* Check the parameters */
+    assert_param(IS_ENHTIM_ALL_PERIPH(ENHTIMx));
+
+    return ENHTIMx->ENHTIM_CUR_CNT;
+}
+
+/**
+  * \brief  Set Max Count value.
+  * \param  ENHTIMx: Select the ENHTIM peripheral. \ref ENHTIM_Declaration
+  * \param  count: Max counter value for user-define PWM mode (leagel value: 0 ~ 2^32-2).
+  * \note   If it needs a dynamic change of MAX_CNT value, MAX_CNT has a minimum value limit.
+  *         Ex. cpu_clk = 40MHz, ETIMER_CLK = 40MHz, then MAX_CNT should larger than 10.
+  *         Ex. cpu_clk = 40MHz, ETIMER_CLK = 32kHz, then MAX_CNT should larger than 4.
+  *         If in the state where ENHTIM is disabled, there is no such limitation.
+  * \return None
+  */
+void ENHTIM_SetMaxCount(ENHTIM_TypeDef *ENHTIMx, uint32_t count)
+{
+    /* Check the parameters */
+    assert_param(IS_ENHTIM_ALL_PERIPH(ENHTIMx));
+
+    if (count > 0xFFFFFFFE)
+    {
+        count = 0xFFFFFFFE;
+    }
+    ENHTIMx->ENHTIM_MAX_CNT = count;
+}
+
+/**
+  * \brief  Set ENHTIMx capture/compare value for user-define PWM manual mode.
+  * \param  ENHTIMx: Select the ENHTIM peripheral. \ref ENHTIM_Declaration
+  * \param  value: User-defined EnhtimerN capture/compare value for PWM manual mode,
+  *         ranging from 0 to 2^31.
+  * \note   If it needs a dynamic change of CCR value, CCR value has a minimum value limit.
+  *         Ex. cpu_clk = 40MHz, ETIMER_CLK = 40MHz, then CCR value should larger than 10.
+  *         Ex. cpu_clk = 40MHz, ETIMER_CLK = 32kHz, then CCR value should larger than 4.
+  *         If in the state where ENHTIM is disabled, there is no such limitation.
+  * \return None
+  */
+void ENHTIM_SetCCValue(ENHTIM_TypeDef *ENHTIMx, uint32_t value)
+{
+    /* Check the parameters */
+    assert_param(IS_ENHTIM_ALL_PERIPH(ENHTIMx));
+
+    ENHTIMx->ENHTIM_CCR = value;
+}
+
+/**
+  * \brief  Set ENHTIMx capture/compare value for user-define PWM auto mode.
+  * \param  ENHTIMx: Select the ENHTIM peripheral. \ref ENHTIM_Declaration
+  * \param  value:  User-defined EnhtimerN capture/compare value for PWM manual mode,
+  *            ranging from 0 to 2^31.
+  * \return None
+  */
+void ENHTIM_WriteCCFIFO(ENHTIM_TypeDef *ENHTIMx, uint32_t value)
+{
+    /* Check the parameters */
+    assert_param(IS_ENHTIM_ALL_PERIPH(ENHTIMx));
+
+    ENHTIMx->ENHTIM_CCR_FIFO_ENTRY = value;
+}
+
+/**
+  * \brief  Check whether the specified ENHTIM flag is set.
+  * \param  ENHTIMx: Select the ENHTIM peripheral. \ref ENHTIM_Declaration
+  * \param  ENHTIM_FLAG: Specifies the flag to check.
+  * \return The new state of ENHTIM_FLAG (SET or RESET).
+  */
+FlagStatus ENHTIM_GetFIFOFlagStatus(ENHTIM_TypeDef *ENHTIMx, uint32_t ENHTIM_FLAG)
+{
+    /* Check the parameters */
+    assert_param(IS_ENHTIM_FIFO_FLAG(ENHTIM_FLAG));
+
+    FlagStatus bitstatus = RESET;
+    uint32_t enhtim_id = ENHTIM_GetTimerID(ENHTIMx);
+    uint32_t pos = ENHTIM_FLAG & BIT0;
+    uint32_t bit_id = BIT(enhtim_id * 2);
+
+    if (ENHTIM_FLAG == ENHTIM_FLAG_LC_FIFO_FULL || ENHTIM_FLAG == ENHTIM_FLAG_LC_FIFO_EMPTY)
+    {
+        if (ENH_TIM_SHARE -> ENHTIM_LATCH_CNT_FIFO_STATUS & (bit_id << pos))
+        {
+            bitstatus = SET;
+        }
+    }
+    else if (ENHTIM_FLAG == ENHTIM_FLAG_CCR_FIFO_FULL || ENHTIM_FLAG == ENHTIM_FLAG_CCR_FIFO_EMPTY)
+    {
+
+        if (ENH_TIM_SHARE -> ENHTIM_CCR_FIFO_STATUS & (bit_id << pos))
+        {
+            bitstatus = SET;
+        }
+    }
+
+    return bitstatus;
+}
+
+/**
+  * \brief  Enable ENHTIMx latch counter.
+  * \param  ENHTIMx: Select the ENHTIM peripheral. \ref ENHTIM_Declaration
+  * \param  LatchCntIdx: E_ENHTIM_LATCHCNT enum value.
+  * \return None.
+  */
+void ENHTIM_LatchCountEnable(ENHTIM_TypeDef *ENHTIMx,
+                             ENHTIMLatchCnt_TypeDef LatchCntIdx)
+{
+    /* Check the parameters */
+    assert_param(IS_ENHTIM_ALL_PERIPH(ENHTIMx));
+
+    ENHTIM_CONFIGURE_TypeDef ENHTIM_0x10 = {.d32 = ENHTIMx->ENHTIM_CONFIGURE};
+
+    switch (LatchCntIdx)
+    {
+#if ENHTIM_SUPPORT_LATCH_CNT_0
+    case LATCH_CNT_0:
+        ENHTIM_0x10.b.Enhtimer_Latch_cnt_0_en = 0x1;
+        break;
+#endif
+#if ENHTIM_SUPPORT_LATCH_CNT_1
+    case LATCH_CNT_1:
+        ENHTIM_0x10.b.Enhtimer_Latch_cnt_1_en = 0x1;
+        break;
+#endif
+#if ENHTIM_SUPPORT_LATCH_CNT_2
+    case LATCH_CNT_2:
+        ENHTIM_0x10.b.Enhtimer_Latch_cnt_2_en = 0x1;
+        break;
+#endif
+    default:
+        break;
+    }
+
+    ENHTIMx->ENHTIM_CONFIGURE = ENHTIM_0x10.d32;
+}
+
+/**
+  * \brief  Disable ENHTIMx latch counter.
+  * \param  ENHTIMx: Select the ENHTIM peripheral. \ref ENHTIM_Declaration
+  * \param  LatchCntIdx: E_ENHTIM_LATCHCNT enum value.
+  * \return None.
+  */
+void ENHTIM_LatchCountDisable(ENHTIM_TypeDef *ENHTIMx,
+                              ENHTIMLatchCnt_TypeDef LatchCntIdx)
+{
+    /* Check the parameters */
+    assert_param(IS_ENHTIM_ALL_PERIPH(ENHTIMx));
+
+    ENHTIM_CONFIGURE_TypeDef ENHTIM_0x10 = {.d32 = ENHTIMx->ENHTIM_CONFIGURE};
+    switch (LatchCntIdx)
+    {
+#if ENHTIM_SUPPORT_LATCH_CNT_0
+    case LATCH_CNT_0:
+        ENHTIM_0x10.b.Enhtimer_Latch_cnt_0_en = 0x0;
+        break;
+#endif
+#if ENHTIM_SUPPORT_LATCH_CNT_1
+    case LATCH_CNT_1:
+        ENHTIM_0x10.b.Enhtimer_Latch_cnt_1_en = 0x0;
+        break;
+#endif
+#if ENHTIM_SUPPORT_LATCH_CNT_2
+    case LATCH_CNT_2:
+        ENHTIM_0x10.b.Enhtimer_Latch_cnt_2_en = 0x0;
+        break;
+#endif
+    default:
+        break;
+    }
+
+    ENHTIMx->ENHTIM_CONFIGURE = ENHTIM_0x10.d32;
+}
+
+/**
+  * \brief  Get ENHTIMx latch count value.
+  * \param  ENHTIMx: Select the ENHTIM peripheral. \ref ENHTIM_Declaration
+  * \param  LatchCntIdx: E_ENHTIM_LATCHCNT enum value.
+  * \return None.
+  */
+uint32_t ENHTIM_GetLatchCount(ENHTIM_TypeDef *ENHTIMx,
+                              ENHTIMLatchCnt_TypeDef LatchCntIdx)
+{
+    /* Check the parameters */
+    assert_param(IS_ENHTIM_ALL_PERIPH(ENHTIMx));
+
+    return *(volatile uint32_t *)(&(ENHTIMx->ENHTIM_LATCH_CNT_0) + LatchCntIdx);
+}
+
+/**
+  * \brief  Get ENHTIMx latch counter2 fifo length.
+  * \param  ENHTIMx: Select the ENHTIM peripheral. \ref ENHTIM_Declaration
+  * \return FIFO data length.
+  */
+uint8_t ENHTIM_GetLatchCountFIFOLength(ENHTIM_TypeDef *ENHTIMx)
+{
+    /* Check the parameters */
+    assert_param(IS_ENHTIM_ALL_PERIPH(ENHTIMx));
+
+    uint32_t enhtim_id = ENHTIM_GetTimerID(ENHTIMx);
+
+    return (uint8_t)(*(&(ENH_TIM_SHARE->ENHTIM0_LATCH_FIFO_DEPTH) + enhtim_id)) & 0xF;
+}
+
+/**
+  * \brief  Clear capture/compare or latch count2 fifo.
+  * \param  ENHTIMx: Select the ENHTIM peripheral. \ref ENHTIM_Declaration
+  * \param  FIFO_CLR: Specifies the FIFO type which to be clear.
+  * \return FIFO data length.
+  */
+void ENHTIM_ClearFIFO(ENHTIM_TypeDef *ENHTIMx, uint8_t FIFO_CLR)
+{
+    /* Check the parameters */
+    assert_param(IS_ENHTIM_ALL_PERIPH(ENHTIMx));
+
+    uint32_t enhtim_id = ENHTIM_GetTimerID(ENHTIMx);
+
+    ENH_TIM_SHARE->ENHTIM_FIFO_CLR |= (BIT(FIFO_CLR + enhtim_id));
+}
+
+
+/**
+  * \brief  Get all the ENHTIM interrupt status.
+  * \param  None.
+  * \return All the state of the ENHTIM_INT.
+  */
+uint32_t ENHTIM_GetAllINTStatus(void)
+{
+    return ENH_TIM_SHARE->ENHTIM_INT_STATUS;
+}
+
diff --git a/bee/drivers/timer/src/device/rtl87x2g/rtl_enh_tim.h b/bee/drivers/timer/src/device/rtl87x2g/rtl_enh_tim.h
new file mode 100644
index 00000000..9b87da71
--- /dev/null
+++ b/bee/drivers/timer/src/device/rtl87x2g/rtl_enh_tim.h
@@ -0,0 +1,992 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *               Define to prevent recursive inclusion
+ *============================================================================*/
+#ifndef RTL_ENH_TIM_H
+#define RTL_ENH_TIM_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*============================================================================*
+ *                        Header Files
+ *============================================================================*/
+#include "utils/rtl_utils.h"
+#include "rtl_enhtim_def.h"
+#include "pin_def.h"
+
+/** \defgroup ENHTIM      ENHTIM
+  * \brief
+  * \{
+  */
+
+/*============================================================================*
+ *                         Constants
+ *============================================================================*/
+/** \defgroup ENHTIM_Exported_Constants ENHTIM Exported Constants
+  * \brief
+  * \{
+  */
+
+/**
+ * \defgroup    ENHTIM_Clock_Divider ENHTIM Clock Divider
+ * \{
+ * \ingroup     ENHTIM_Exported_Constants
+ */
+typedef enum
+{
+    ENHTIM_CLOCK_DIVIDER_1   = 0x0,     //!< Clock divider is 1.
+    ENHTIM_CLOCK_DIVIDER_2   = 0x1,     //!< Clock divider is 2.
+    ENHTIM_CLOCK_DIVIDER_4   = 0x2,     //!< Clock divider is 4.
+    ENHTIM_CLOCK_DIVIDER_8   = 0x3,     //!< Clock divider is 8.
+    ENHTIM_CLOCK_DIVIDER_16  = 0x4,     //!< Clock divider is 16.
+    ENHTIM_CLOCK_DIVIDER_32  = 0x5,     //!< Clock divider is 32.
+    ENHTIM_CLOCK_DIVIDER_40  = 0x6,     //!< Clock divider is 40.
+    ENHTIM_CLOCK_DIVIDER_64  = 0x7,     //!< Clock divider is 64.
+} ENHTIMClkDiv_TypeDef;
+
+#define IS_ENHTIM_CLK_DIVIDER(div) (((div) == ENHTIM_CLOCK_DIVIDER_1) || \
+                                    ((div) == ENHTIM_CLOCK_DIVIDER_2) || \
+                                    ((div) == ENHTIM_CLOCK_DIVIDER_4) || \
+                                    ((div) == ENHTIM_CLOCK_DIVIDER_8) || \
+                                    ((div) == ENHTIM_CLOCK_DIVIDER_16)|| \
+                                    ((div) == ENHTIM_CLOCK_DIVIDER_32)|| \
+                                    ((div) == ENHTIM_CLOCK_DIVIDER_40)|| \
+                                    ((div) == ENHTIM_CLOCK_DIVIDER_64)) //!< Check if the input parameter is valid.
+
+/** End of ENHTIM_Clock_Divider
+  * \}
+  */
+
+/**
+ * \defgroup    ENHTIM_Latch_Channel_Count ENHTIM Latch Channel Count
+ * \{
+ * \ingroup     ENHTIM_Exported_Constants
+ */
+typedef enum
+{
+#if ENHTIM_SUPPORT_LATCH_CNT_0
+    LATCH_CNT_0 = 0x0,     //!< GPIO trigger function.
+#endif
+#if ENHTIM_SUPPORT_LATCH_CNT_1
+    LATCH_CNT_1 = 0x1,     //!< Tx on trigger function.
+#endif
+#if ENHTIM_SUPPORT_LATCH_CNT_2
+    LATCH_CNT_2 = 0x2,     //!< Acc hit trigger function.
+#endif
+} ENHTIMLatchCnt_TypeDef;
+
+#if (ENHTIM_SUPPORT_LATCH_CNT_0 && !ENHTIM_SUPPORT_LATCH_CNT_1 && !ENHTIM_SUPPORT_LATCH_CNT_2)
+#define IS_ENHTIM_LATCH_CNT(cnt) ((cnt) == LATCH_CNT_0) //!< Check if the input parameter is valid.
+#endif
+#if (ENHTIM_SUPPORT_LATCH_CNT_0 && ENHTIM_SUPPORT_LATCH_CNT_1 && ENHTIM_SUPPORT_LATCH_CNT_2)
+#define IS_ENHTIM_LATCH_CNT(cnt) ((cnt) == LATCH_CNT_0 || (cnt) == LATCH_CNT_1 || (cnt) == LATCH_CNT_2) //!< Check if the input parameter is valid.
+#endif
+
+/** End of ENHTIM_Latch_Channel_Count
+  * \}
+  */
+
+
+/**
+ * \defgroup    ENHTIM_DMA_Target ENHTIM DMA Target
+ * \{
+ * \ingroup     ENHTIM_Exported_Constants
+ */
+typedef enum
+{
+    ENHTIM_DMA_CCR_FIFO = 0x00,     //!< DMA target is CCR FIFO.
+    ENHTIM_DMA_LC_FIFO = 0x01,      //!< DMA target is latch count FIFO.
+} ENHTIMDmaTarget_TypeDef;
+
+#define IS_ENHTIM_DMA_TARGET(mode) (((mode) == ENHTIM_DMA_CCR_FIFO) || \
+                                    ((mode) == ENHTIM_DMA_LC_FIFO)) //!< Check if the input parameter is valid.
+
+/** End of ENHTIM_DMA_Target
+  * \}
+  */
+
+/**
+ * \defgroup    ENHTIM_Latch_Trigger_Mode ENHTIM Latch Trigger Mode
+ * \{
+ * \ingroup     ENHTIM_Exported_Constants
+ */
+typedef enum
+{
+    ENHTIM_LATCH_TRIGGER_RISING_EDGE = 0x00,     //!< Latch trigger mode is rising edge.
+    ENHTIM_LATCH_TRIGGER_FALLING_EDGE = 0x01,    //!< Latch trigger mode is falling edge.
+    ENHTIM_LATCH_TRIGGER_BOTH_EDGE = 0x02,       //!< Latch trigger mode is both rising and falling edge.
+} ENHTIMLatchTriggleMode_TypeDef;
+
+#define IS_ENHTIM_LATCH_TRIG_Mode(mode) (((mode) == ENHTIM_LATCH_TRIGGER_BOTH_EDGE) || \
+                                         ((mode) == ENHTIM_LATCH_TRIGGER_FALLING_EDGE) || \
+                                         ((mode) == ENHTIM_LATCH_TRIGGER_RISING_EDGE)) //!< Check if the input parameter is valid.
+
+/** End of ENHTIM_Latch_Trigger_Mode
+  * \}
+  */
+
+/**
+ * \defgroup    ENHTIM_Mode ENHTIM Mode
+ * \{
+ * \ingroup     ENHTIM_Exported_Constants
+ */
+typedef enum
+{
+    ENHTIM_MODE_FreeRun = 0x00,        //!< Freerun mode.
+    ENHTIM_MODE_PWM_AUTO = 0x01,       //!< User define pwm auto mode.
+    ENHTIM_MODE_PWM_MANUAL = 0x02,     //!< User define pwm manual mode.
+} ENHTIMMode_TypeDef;
+
+#define IS_ENHTIM_MODE(mode) (((mode) == ENHTIM_MODE_PWM_MANUAL) || \
+                              ((mode) == ENHTIM_MODE_PWM_AUTO) || \
+                              ((mode) == ENHTIM_MODE_UserDefine)) //!< Check if the input parameter is valid.
+
+/** End of ENHTIM_Mode
+  * \}
+  */
+
+/**
+ * \defgroup    ENHTIM_PWM_Polarity ENHTIM PWM Polarity
+ * \{
+ * \ingroup     ENHTIM_Exported_Constants
+ */
+typedef enum
+{
+    ENHTIM_PWM_START_WITH_LOW = 0x00,      //!< PWM start with output low.
+    ENHTIM_PWM_START_WITH_HIGH = 0x01,     //!< PWM start with output high.
+} ENHTIMPWMPolarity_TypeDef;
+
+#define IS_ENHTIM_PWM_POLARITY(Pol) (((Pol) == ENHTIM_PWM_START_WITH_HIGH) || \
+                                     ((Pol) == ENHTIM_PWM_START_WITH_LOW)) //!< Check if the input parameter is valid.
+
+/** End of ENHTIM_PWM_Polarity
+  * \}
+  */
+
+/**
+ * \defgroup    ENHTIM_PWM_DeadZone_Clock_Source ENHTIM PWM DeadZone Clock Source
+ * \{
+ * \ingroup     ENHTIM_Exported_Constants
+ */
+typedef enum
+{
+    ENHTIM_PWM_DZCLKSRCE_ENHTIM = 0x0,     //!< PWM deadzone clock source is the same as ENHTIM clock source.
+    ENHTIM_PWM_DZCLKSRCE_32K = 0x1,        //!< PWM deadzone clock source is 32KHz.
+} ENHTIMPWMDZClkSrc_TypeDef;
+
+#define IS_ENHTIM_PWM_DeadZone_Clock_Source(src) (((src) == ENHTIM_PWM_DZCLKSRCE_ENHTIM) || \
+                                                  ((src) == ENHTIM_PWM_DZCLKSRCE_32K)) //!< Check if the input parameter is valid.
+
+/** End of ENHTIM_PWM_DeadZone_Clock_Source
+  * \}
+  */
+
+/**
+ * \defgroup    ENHPWM_DeadZone_Stop_State ENHPWM DeadZone Stop State
+ * \{
+ * \ingroup     ENHTIM_Exported_Constants
+ */
+typedef enum
+{
+    ENHTIM_PWM_STOP_AT_LOW = 0x0,     //!< PWM deadzone mergence stop state at low.
+    ENHTIM_PWM_STOP_AT_HIGH = 0x1,    //!< PWM deadzone mergence stop state at high.
+} ENHTIMPWMDZStopState_TypeDef;
+
+/** End of ENHPWM_DeadZone_Stop_State
+  * \}
+  */
+
+#if ENHTIM_SUPPORT_PWM_SRC_SELECT
+/**
+ * \defgroup    ENHPWM_DeadZone_Reference_Selection ENHPWM DeadZone Reference Selection
+ * \brief   The actual output waveforms of the P and N in complementary PWM mode.
+ * \{
+ * \ingroup     ENHTIM_Exported_Constants
+ */
+typedef enum
+{
+    ENHTIM_DZ_REF_PWMPN = 0x0,     //!< PWM P waveform is PWM_P, PWM N waveform is PWM_N,
+    ENHTIM_DZ_REF_PWMNN = 0x1,     //!< PWM P waveform is PWM_N, PWM N waveform is PWM_N,
+    ENHTIM_DZ_REF_PWMPP = 0x2,     //!< PWM P waveform is PWM_P, PWM N waveform is PWM_P,
+    ENHTIM_DZ_REF_PWMNP = 0x3,     //!< PWM P waveform is PWM_N, PWM N waveform is PWM_P,
+} ENHTIMPWMDZRef_TypeDef;
+
+/** End of ENHPWM_Reference_Selection
+  * \}
+  */
+#endif
+
+/**
+ * \defgroup    ENHTIM_Interrupts ENHTIM Interrupts
+ * \{
+ * \ingroup     ENHTIM_Exported_Constants
+ */
+#define ENHTIM_INT_TIM                            (0x00)     //!< ENHTIM timeout interrupt.
+#define ENHTIM_INT_LATCH_CNT_FIFO_FULL            (0x40)     //!< ENHTIM latch count FIFO full interrupt.
+#define ENHTIM_INT_LATCH_CNT_FIFO_THD             (0x42)     //!< ENHTIM latch count FIFO threshold interrupt.
+#define ENHTIM_INT_LATCH_CNT_FIFO_EMPTY           (0x01)     //!< ENHTIM latch count FIFO empty interrupt.
+
+#define IS_ENHTIM_INT(INT) (((INT) == ENHTIM_INT_TIM) || \
+                            ((INT) == ENHTIM_INT_LATCH_CNT_FIFO_FULL) || \
+                            ((INT) == ENHTIM_INT_LATCH_CNT_FIFO_THD)) //!< Check if the input parameter is valid.
+
+/** End of ENHTIM_Interrupts
+  * \}
+  */
+
+/**
+ * \defgroup    ENHTIM_Flag ENHTIM Flag
+ * \{
+ * \ingroup     ENHTIM_Exported_Constants
+ */
+#define ENHTIM_FLAG_CCR_FIFO_EMPTY        3     //!< ENHTIM CCR FIFO empty flag.
+#define ENHTIM_FLAG_CCR_FIFO_FULL         2     //!< ENHTIM CCR FIFO full flag.
+#define ENHTIM_FLAG_LC_FIFO_EMPTY         1     //!< ENHTIM latch count FIFO empty flag.
+#define ENHTIM_FLAG_LC_FIFO_FULL          0     //!< ENHTIM latch count FIFO full flag.
+
+#define IS_ENHTIM_FLAG(flag) (((flag) == ENHTIM_FLAG_CCR_FIFO_FULL) || \
+                              ((flag) == ENHTIM_FLAG_CCR_FIFO_EMPTY)|| \
+                              ((flag) == ENHTIM_FLAG_LC_FIFO_FULL)  || \
+                              ((flag) == ENHTIM_FLAG_LC_FIFO_EMPTY) )) //!< Check if the input parameter is valid.
+
+/** End of ENHTIM_Flag
+  * \}
+  */
+
+/**
+ * \defgroup    ENHTIM_FIFO_Clear ENHTIM FIFO Clear
+ * \{
+ * \ingroup     ENHTIM_Exported_Constants
+ */
+#define ENHTIM_FIFO_CLR_CCR                 (0)     //!< ENHTIM CCR FIFO clear.
+#define ENHTIM_FIFO_CLR_CNT0                (8)     //!< ENHTIM latch count FIFO clear.
+
+/** End of ENHTIM_FIFO_Clear
+  * \}
+  */
+
+/** End of ENHTIM_Exported_Constants
+  * \}
+  */
+
+/*============================================================================*
+ *                         Types
+ *============================================================================*/
+/** \defgroup ENHTIM_Exported_Types ENHTIM Exported Types
+  * \brief
+  * \{
+  */
+
+/**
+ * \brief       ENHTIM init structure definition.
+ *
+ * \ingroup     ENHTIM_Exported_Types
+ */
+typedef struct
+{
+    ENHTIMClkSrc_TypdDef ENHTIM_ClockSource;   /*!< Specify the ENHTIM clock source.
+                                                    This parameter can be a value of \ref ENHTIM_Clock_Source . */
+
+    FunctionalState ENHTIM_ClockDiv_En;        /*!< Enable or disable the ENHTIM clock source divider.
+                                                    This parameter can be a value of DISABLE or ENABLE. */
+
+    ENHTIMClkDiv_TypeDef ENHTIM_ClockDiv;      /*!< Specify the divider for the ENHTIM clock source.
+                                                    This parameter can be a value of \ref ENHTIM_Clock_Divider */
+
+    ENHTIMMode_TypeDef ENHTIM_Mode;            /*!< Specify the counter mode.
+                                                    This parameter can be a value of \ref ENHTIM_Mode */
+
+    FunctionalState ENHTIM_PWMOutputEn;        /*!< Enable or disable the ENHTIM PWM output.
+                                                    This parameter can be a value of DISABLE or ENABLE. */
+
+    ENHTIMPWMPolarity_TypeDef
+    ENHTIM_PWMStartPolarity; /*!< Specify ENHTIM toggle output polarity for user-define mode.
+                                                            This parameter can be a value of \ref ENHTIM_PWM_Polarity */
+
+    FunctionalState ENHTIM_LatchCountEn[3];    /*!< Enable or disable the ENHTIM Latch count.
+                                                    This parameter can be a value of DISABLE or ENABLE. */
+
+    ENHTIMLatchTriggleMode_TypeDef ENHTIM_LatchCountTrigger[3]; /*!< Specify ENHTIM latch trigger mode.
+                                                                     This parameter can be a value of \ref ENHTIM_Latch_Trigger_Mode */
+
+    uint16_t ENHTIM_LatchCountThd;             /*!< Specify the latch counter FIFO threshold.
+                                                    This parameter can be value of 0 ~ 0x1F. */
+
+    uint16_t ENHTIM_LatchTriggerPad;           /*!< Specify the latch trigger pin.
+                                                    This parameter can be a value of P0_0 to P19_0. */
+
+    uint32_t ENHTIM_MaxCount;                  /*!< Specify the ENHTIM maximum counter value for user-define mode.
+                                                    This parameter leagel value range is from 1 ~ 2^32-2. */
+
+    uint32_t ENHTIM_CCValue;                   /*!< Specify the ENHTIM capture/compare value for user-define mode.
+                                                    This parameter leagel value range is from 0 ~ 2^32-2.*/
+
+    FunctionalState ENHTIM_PWMDeadZoneEn;      /*!< Enable or disable the ENHTIM PWM deadzone function.
+                                                    This parameter can be a value of ENABLE or DISABLE. */
+
+    uint16_t ENHTIM_PWMDeadZoneClockSource;    /*!< Specify the PWM deadzone Clock Source.
+                                                    This parameter can be a value of \ref ENHTIM_PWM_DeadZone_Clock_Source. */
+
+    FunctionalState
+    ENHTIM_PWMDeadZone_ClockDivEn; /*!< Enable or disable the PWM deadzone clock source divider.
+                                                        This parameter can be a value of ENABLE or DISABLE. */
+
+    ENHTIMClkDiv_TypeDef
+    ENHTIM_PWMDeadZone_ClockDiv; /*!< Specify the divider for the PWM deadzone clock source.
+                                                           This parameter can be a value of \ref ENHTIM_Clock_Divider */
+
+    ENHTIMPWMDZStopState_TypeDef ENHTIM_PWMStopStateP; /*!< Specify the PWM_P stop state.
+                                                            This parameter can be a value of \ref ENHPWM_DeadZone_Stop_State */
+
+    ENHTIMPWMDZStopState_TypeDef ENHTIM_PWMStopStateN; /*!< Specify the PWM_N stop state.
+                                                            This parameter can be a value of \ref ENHPWM_DeadZone_Stop_State */
+
+    uint32_t ENHTIM_DeadZoneSize;              /*!< Specify size of deadzone time. Deadzone Time = (deadzone size)*(deadzone clock period).
+                                                    This parameter must range from 1 to 0xff. */
+
+    FunctionalState ENHTIM_DmaEn;              /*!< Enable or disable the ENHTIM DMA function.
+                                                    This parameter can be a value of DISABLE or ENABLE. */
+
+    ENHTIMDmaTarget_TypeDef ENHTIM_DmaTragget; /*!< Specify ENHTIM DMA target.
+                                                    This parameter can be a value of \ref ENHTIM_DMA_Target */
+
+#if ENHTIM_SUPPORT_ONESHOT_CMD
+    FunctionalState ENHTIM_OneShotEn;          /*!< Enable or disable the one shot mode. */
+#endif
+} ENHTIM_InitTypeDef;
+
+/** End of ENHTIM_Exported_Types
+  * \}
+  */
+
+/*============================================================================*
+ *                         Functions
+ *============================================================================*/
+/** \defgroup ENHTIM_Exported_Functions ENHTIM Exported Functions
+  * \brief
+  * \{
+  */
+
+/**
+ * \brief     Initialize the ENHTIMx unit peripheral according to
+ *            the specified parameters in ENHTIM_InitStruct.
+ *
+ * \param[in] ENHTIMx                    Select the ENHTIM peripheral. Refer to \ref ENHTIM_Declaration.
+ * \param[in] ENHTIM_TimeBaseInitStruct  Pointer to a ENHTIM_InitTypeDef structure which will be initialized.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_enhance_timer_init(void)
+ * {
+ *     RCC_PeriphClockCmd(APBPeriph_TIMER, APBPeriph_TIMER_CLOCK, ENABLE);
+ *
+ *     ENHTIM_InitTypeDef ENHTIM_InitStruct;
+ *     ENHTIM_StructInit(&ENHTIM_InitStruct);
+ *
+ *     ENHTIM_InitStruct.ENHTIM_PWM_En = PWM_DISABLE;
+ *     ENHTIM_InitStruct.ENHTIM_Period = 1000000 - 1 ;
+ *     ENHTIM_InitStruct.ENHTIM_Mode = ENHTIM_Mode_UserDefine;
+ *     ENHTIM_Init(ENHTIMER_NUM, &ENHTIM_InitStruct);
+ * }
+ * \endcode
+ */
+void ENHTIM_Init(ENHTIM_TypeDef *ENHTIMx, ENHTIM_InitTypeDef *ENHTIM_TimeBaseInitStruct);
+/**
+ * \brief Fill each ENHTIM_InitStruct member with its default value.
+ *
+ * \note The default settings for the ENHTIM_InitStruct member are shown in the following table:
+ *       | ENHTIM_InitStruct member        | Default value                         |
+ *       |:-------------------------------:|:-------------------------------------:|
+ *       | ENHTIM_ClockSource              | \ref ENHTIM_CLOCK_SOURCE_40M          |
+ *       | ENHTIM_ClockDiv_En              | DISABLE                               |
+ *       | ENHTIM_ClockDiv                 | \ref ENHTIM_CLOCK_DIVIDER_1           |
+ *       | ENHTIM_Mode                     | \ref ENHTIM_MODE_FreeRun              |
+ *       | ENHTIM_PWMOutputEn              | DISABLE                               |
+ *       | ENHTIM_PWMStartPolarity         | \ref ENHTIM_PWM_START_WITH_LOW        |
+ *       | ENHTIM_OneShotEn                | DISABLE                               |
+ *       | ENHTIM_LatchCountEn[0]          | DISABLE                               |
+ *       | ENHTIM_LatchCountTrigger[0]     | \ref ENHTIM_LATCH_TRIGGER_RISING_EDGE |
+ *       | ENHTIM_LatchCountEn[1]          | DISABLE                               |
+ *       | ENHTIM_LatchCountTrigger[1]     | \ref ENHTIM_LATCH_TRIGGER_RISING_EDGE |
+ *       | ENHTIM_LatchCountEn[2]          | DISABLE                               |
+ *       | ENHTIM_LatchCountTrigger[2]     | \ref ENHTIM_LATCH_TRIGGER_RISING_EDGE |
+ *       | ENHTIM_LatchCountThd            | 3                                     |
+ *       | ENHTIM_LatchTriggerPad          | P0_0                                  |
+ *       | ENHTIM_MaxCount                 | 0xFFFFFFFE                            |
+ *       | ENHTIM_CCValue                  | 0x0                                   |
+ *       | ENHTIM_PWMDeadZoneClockSource   | \ref ENHTIM_PWM_DZCLKSRCE_32K         |
+ *       | ENHTIM_PWMDeadZone_ClockDivEn   | DISABLE                               |
+ *       | ENHTIM_PWMDeadZone_ClockDiv     | \ref ENHTIM_CLOCK_DIVIDER_1           |
+ *       | ENHTIM_PWMDeadZoneEn            | DISABLE                               |
+ *       | ENHTIM_PWMStopStateP            | \ref ENHTIM_PWM_STOP_AT_HIGH          |
+ *       | ENHTIM_PWMStopStateN            | \ref ENHTIM_PWM_STOP_AT_LOW           |
+ *       | ENHTIM_DeadZoneSize             | 0xFF                                  |
+ *       | ENHTIM_DmaEn                    | DISABLE                               |
+ *       | ENHTIM_DmaTragget               | \ref ENHTIM_DMA_CCR_FIFO              |
+ *
+ * \param[in]   ENHTIM_InitStruct  Pointer to a ENHTIM_InitTypeDef structure which will be initialized.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_enhance_timer_init(void)
+ * {
+ *     RCC_PeriphClockCmd(APBPeriph_ENHTIMER, APBPeriph_ENHTIMER_CLOCK, ENABLE);
+ *
+ *     ENHTIM_InitTypeDef ENHTIM_InitStruct;
+ *     ENHTIM_StructInit(&ENHTIM_InitStruct);
+ *
+ *     ENHTIM_InitStruct.ENHTIM_PWM_En = PWM_DISABLE;
+ *     ENHTIM_InitStruct.ENHTIM_Period = 1000000 - 1;
+ *     ENHTIM_InitStruct.ENHTIM_Mode = ENHTIM_Mode_UserDefine;
+ *     ENHTIM_Init(ENH_TIM0, &ENHTIM_InitStruct);
+ * }
+ * \endcode
+ */
+void ENHTIM_StructInit(ENHTIM_InitTypeDef *ENHTIM_InitStruct);
+/**
+ * \brief     Enable or disable the specified ENHTIMx peripheral.
+ *
+ * \param[in] ENHTIMx   Select the ENHTIM peripheral. Refer to \ref ENHTIM_Declaration.
+ * \param[in] NewState  New state of the ENHTIMx peripheral.
+ *                      This parameter can be one of the following values:
+ *                      - ENABLE: Count start.
+ *                      - DISABLE: Count stop and clear count value.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_enhance_timer_init(void)
+ * {
+ *     RCC_PeriphClockCmd(APBPeriph_ENHTIMER, APBPeriph_ENHTIMER_CLOCK, ENABLE);
+ *
+ *     ENHTIM_InitTypeDef ENHTIM_InitStruct;
+ *     ENHTIM_StructInit(&ENHTIM_InitStruct);
+ *
+ *     ENHTIM_InitStruct.ENHTIM_PWM_En = PWM_DISABLE;
+ *     ENHTIM_InitStruct.ENHTIM_Period = 1000000 - 1;
+ *     ENHTIM_InitStruct.ENHTIM_Mode = ENHTIM_Mode_UserDefine;
+ *     ENHTIM_Init(ENH_TIM0, &ENHTIM_InitStruct);
+ *     ENHTIM_Cmd(ENH_TIM0, ENABLE);
+ * }
+ * \endcode
+ */
+void ENHTIM_Cmd(ENHTIM_TypeDef *ENHTIMx, FunctionalState NewState);
+
+/**
+ * \brief     Enable or disable the specified ENHTIMx interrupt.
+ *
+ * \param[in] ENHTIMx     Select the specified ENHTIMx peripheral. Refer to \ref ENHTIM_Declaration.
+ * \param[in] ENHTIM_INT  Specify the ENHTIMx interrupt source which to be enabled or disabled. Refer to \ref ENHTIM_Interrupts.
+ * \param[in] NewState    New state of the ENHTIMx peripheral.
+ *                        This parameter can be one of the following values:
+ *                        - ENABLE: Enable the specified interrupt.
+ *                        - DISABLE: Disable the specified interrupt.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_enhance_timer_init(void)
+ * {
+ *     RCC_PeriphClockCmd(APBPeriph_TIMER, APBPeriph_TIMER_CLOCK, ENABLE);
+ *
+ *     ENHTIM_InitTypeDef ENHTIM_InitStruct;
+ *     ENHTIM_StructInit(&ENHTIM_InitStruct);
+ *
+ *     ENHTIM_InitStruct.ENHTIM_PWM_En = PWM_DISABLE;
+ *     ENHTIM_InitStruct.ENHTIM_Period = 1000000 - 1;
+ *     ENHTIM_InitStruct.ENHTIM_Mode = ENHTIM_Mode_UserDefine;
+ *     ENHTIM_Init(ENH_TIM0, &ENHTIM_InitStruct);
+ *     ENHTIM_ClearINT(ENH_TIM0);
+ *     ENHTIM_INTConfig(ENH_TIM0, ENABLE);
+ * }
+ * \endcode
+ */
+void ENHTIM_INTConfig(ENHTIM_TypeDef *ENHTIMx, uint8_t ENHTIM_INT, FunctionalState NewState);
+
+/**
+ * \brief     Read ENHTIM latch count fifo data.
+ *
+ * \param[in] ENHTIMx  Select the ENHTIM peripheral. Refer to \ref ENHTIM_Declaration.
+ * \param[in] length   Latch count0 fifo length, max 32.
+ * \pBuf[out] pBuf     FIFO data out buffer.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void enhance_timer_demo(void)
+ * {
+ *     uint8_t length = ENHTIM_GetLatchCountFIFOLength(ENH_TIM0);
+ * }
+ * \endcode
+ */
+void ENHTIM_ReadLatchCountFIFO(ENHTIM_TypeDef *ENHTIMx, uint32_t *pBuf, uint8_t length);
+
+/**
+ * \brief     Get the specified ENHTIMx interrupt status.
+ *
+ * \param[in] ENHTIMx     Select the ENHTIM peripheral. Refer to \ref ENHTIM_Declaration.
+ * \param[in] ENHTIM_INT  Specify the ENHTIMx interrupt source which to be enabled or disabled.
+ *                        This parameter can be one of the following values, Refer to \ref ENHTIM_Interrupts.
+ *                        \arg ENHTIM_INT_TIM: ENHTIM timeout interrupt.
+ *                        \arg ENHTIM_INT_LATCH_CNT_FIFO_FULL: Enhance Timer latch count0 fifo full interrupt source.
+ *                        \arg ENHTIM_INT_LATCH_CNT_FIFO_EMPTY: Enhance Timer latch count0 fifo empty interrupt source.
+ *                        \arg ENHTIM_INT_LATCH_CNT_FIFO_THD: Enhance Timer latch count0 fifo threshold interrupt source.
+ *
+ * \return    The status of the \ref ENHTIM_Interrupts.
+ *            - SET: The specified ENHTIMx interrupt status is set.
+ *            - RESET: The specified ENHTIMx interrupt status is reset.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void enhance_timer_demo(void)
+ * {
+ *     ENHTIM_GetINTStatus(ENH_TIM0, ENHTIM_INT_TIM);
+ * }
+ * \endcode
+ */
+ITStatus ENHTIM_GetINTStatus(ENHTIM_TypeDef *ENHTIMx, uint8_t ENHTIM_INT);
+
+/**
+ * \brief     Clear the specified ENHTIMx interrupt.
+ *
+ * \param[in] ENHTIMx     Select the ENHTIM peripheral. Refer to \ref ENHTIM_Declaration.
+ * \param[in] ENHTIM_INT  Specify the ENHTIMx interrupt source which to be configured.
+ *                        This parameter can be one of the following values, Refer to \ref ENHTIM_Interrupts.
+ *                        - ENHTIM_INT_TIM: ENHTIM timeout interrupt.
+ *                        - ENHTIM_INT_LATCH_CNT_FIFO_FULL: Enhance Timer latch count0 fifo full interrupt source.
+ *                        - ENHTIM_INT_LATCH_CNT_FIFO_THD: Enhance Timer latch count0 fifo threshold interrupt source.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void enhance_timer_demo(void)
+ * {
+ *     ENHTIM_ClearINTPendingBit(ENH_TIM0, ENHTIM_INT_TIM);
+ * }
+ * \endcode
+ */
+void ENHTIM_ClearINTPendingBit(ENHTIM_TypeDef *ENHTIMx, uint8_t ENHTIM_INT);
+
+/**
+ * \brief     Get the specified ENHTIMx toggle state.
+ *
+ * \param[in] ENHTIMx  Select the ENHTIM peripheral. Refer to \ref ENHTIM_Declaration.
+ *
+ * \return    The status of the ENHTIM Toggle.
+ *            - SET: The specified ENHTIMx Toggle status is set.
+ *            - RESET: The specified ENHTIMx Toggle status is reset.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void enhance_timer_demo(void)
+ * {
+ *     bool State=ENHTIM_GetToggleState(ENHTIM0);
+ * }
+ * \endcode
+ */
+bool ENHTIM_GetToggleState(ENHTIM_TypeDef *ENHTIMx);
+
+#if ENHTIM_SUPPORT_PWM_PHASE_SHIFT
+/**
+ * \brief  Change ENHTIM pwm_phase_shift count
+ *
+ * \param[in] ENHTIMx        Select the ENHTIM peripheral. Refer to \ref ENHTIM_Declaration.
+ * \param[in] PhaseShiftCnt  This parameter specify the phase shift count.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void enhance_timer_demo(void)
+ * {
+ *     ENHTIM_PhaseShiftCnt(ENH_TIM0, 0);
+ * }
+ * \endcode
+ */
+void ENHTIM_PhaseShiftCnt(ENHTIM_TypeDef *ENHTIMx, uint32_t PhaseShiftCnt);
+#endif
+
+/**
+ * \brief  Get the specified ENHTIMx current count.
+ *
+ * \param[in] ENHTIMx  Select the ENHTIM peripheral. Refer to \ref ENHTIM_Declaration.
+ *
+ * \return   The current count value.
+
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void enhance_timer_demo(void)
+ * {
+ *     ENHTIM_GetCurrentCount(ENH_TIM0);
+ * }
+ * \endcode
+ */
+uint32_t ENHTIM_GetCurrentCount(ENHTIM_TypeDef *ENHTIMx);
+
+/**
+ * \brief     Set the maximum count value.
+ *
+ * \param[in] ENHTIMx  Select the ENHTIM peripheral. Refer to \ref ENHTIM_Declaration.
+ * \param[in] count    Maximum counter value for user-defined PWM mode (legal value: 0 to (2^{32} - 2)).
+ *
+ * \note      If it needs a dynamic change of MAX_CNT value, MAX_CNT has a minimum value limit.
+ *            Ex. cpu_clk = 40MHz, ETIMER_CLK = 40MHz, then MAX_CNT should larger than 10.
+ *            Ex. cpu_clk = 40MHz, ETIMER_CLK = 32kHz, then MAX_CNT should larger than 4.
+ *            If in the state where ENHTIM is disabled, there is no such limitation.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void enhance_timer_demo(void)
+ * {
+ *     ENHTIM_SetMaxCount(ENH_TIM0, 0x10000);
+ * }
+ * \endcode
+ */
+void ENHTIM_SetMaxCount(ENHTIM_TypeDef *ENHTIMx, uint32_t count);
+
+/**
+ * \brief     Set the capture/compare value for the user-define manual mode.
+ *
+ * \param[in] ENHTIMx  Select the ENHTIM peripheral. Refer to \ref ENHTIM_Declaration.
+ * \param[in] value    User-defined ENHTIM capture/compare value for PWM manual mode,
+ *                     ranging from 0 to 2^31.
+ *
+ * \note      If it needs a dynamic change of CCR value, CCR value has a minimum value limit.
+ *            Ex. cpu_clk = 40MHz, ETIMER_CLK = 40MHz, then CCR value should larger than 10.
+ *            Ex. cpu_clk = 40MHz, ETIMER_CLK = 32kHz, then CCR value should larger than 4.
+ *            If in the state where ENHTIM is disabled, there is no such limitation.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void enhance_timer_demo(void)
+ * {
+ *     ENHTIM_SetCCValue(ENH_TIM0, 0x1000);
+ * }
+ * \endcode
+ */
+void ENHTIM_SetCCValue(ENHTIM_TypeDef *ENHTIMx, uint32_t value);
+
+/**
+ * \brief     Set the capture/compare value for the user-define auto mode.
+ *
+ * \param[in] ENHTIMx  Select the ENHTIM peripheral. Refer to \ref ENHTIM_Declaration.
+ * \param[in] value    User-defined ENHTIM capture/compare value for PWM manual mode,
+ *                     ranging from 0 to 2^31.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void enhance_timer_demo(void)
+ * {
+ *     ENHTIM_WriteCCFIFO(ENH_TIM0,0x10000);
+ * }
+ * \endcode
+ */
+void ENHTIM_WriteCCFIFO(ENHTIM_TypeDef *ENHTIMx, uint32_t value);
+
+/**
+ * \brief     Get the specified ENHTIM FIFO flag status.
+ *
+ * \param[in] ENHTIMx      Where x can be 0 to 7 to select the ENHTIMx peripheral.
+ * \param[in] ENHTIM_FLAG  Specify the flag to check.
+ *                         This parameter can be one of the following values, Refer to \ref ENHTIM_Flag.
+ *                         \arg ENHTIM_FLAG_LC_FIFO_EMPTY: FIFO empty or not. If SET, LC FIFO is empty.
+ *                         \arg ENHTIM_FLAG_LC_FIFO_FULL: FIFO full or not. If SET, LC FIFO is full.
+ *                         \arg ENHTIM_FLAG_CCR_FIFO_EMPTY: FIFO empty or not. If SET, CCR FIFO is empty.
+ *                         \arg ENHTIM_FLAG_CCR_FIFO_FULL: FIFO full or not. If SET, CCR FIFO is full.
+ *
+ * \return  The status of \ref ENHTIM_Flag.
+ *          - SET: The specified ENHTIM flag is set.
+ *          - RESET: The specified ENHTIM flag is reset.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void enhance_timer_demo(void)
+ * {
+ *     FlagStatus flag_status = ENHTIM_GetFIFOFlagStatus(ENH_TIM0, ENHTIM_FLAG_LC_FIFO_EMPTY);
+ * }
+ * \endcode
+ */
+FlagStatus ENHTIM_GetFIFOFlagStatus(ENHTIM_TypeDef *ENHTIMx, uint32_t ENHTIM_FLAG);
+
+/**
+ * \brief     Enable the specified ENHTIMx latch counter.
+ *
+ * \param[in] ENHTIMx      Select the ENHTIM peripheral. Refer to \ref ENHTIM_Declaration.
+ * \param[in] LatchCntIdx  E_ENHTIM_LATCHCNT enum value.
+ *                         This parameter can be one of the following values, Refer to \ref ENHTIM_Latch_Channel_Count.
+ *                         - LATCH_CNT_0: Enhance timer latch count 0.
+ *                         - LATCH_CNT_1: Enhance timer latch count 1.
+ *                         - LATCH_CNT_2: Enhance timer latch count 2.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void enhance_timer_demo(void)
+ * {
+ *     ENHTIM_LatchCountEnable(ENH_TIM0, LATCH_CNT_0);
+ * }
+ * \endcode
+ */
+void ENHTIM_LatchCountEnable(ENHTIM_TypeDef *ENHTIMx,
+                             ENHTIMLatchCnt_TypeDef LatchCntIdx);
+
+/**
+ * \brief     Disable the specified ENHTIMx latch counter.
+ *
+ * \param[in] ENHTIMx      Select the ENHTIM peripheral. Refer to \ref ENHTIM_Declaration.
+ * \param[in] LatchCntIdx  E_ENHTIM_LATCHCNT enum value.
+ *                         This parameter can be one of the following values, Refer to \ref ENHTIM_Latch_Channel_Count.
+ *                         - LATCH_CNT_0: Enhance timer latch count 0.
+ *                         - LATCH_CNT_1: Enhance timer latch count 1.
+ *                         - LATCH_CNT_2: Enhance timer latch count 2.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void enhance_timer_demo(void)
+ * {
+ *     ENHTIM_LatchCountDisable(ENH_TIM0, LATCH_CNT_0);
+ * }
+ * \endcode
+ */
+void ENHTIM_LatchCountDisable(ENHTIM_TypeDef *ENHTIMx,
+                              ENHTIMLatchCnt_TypeDef LatchCntIdx);
+
+/**
+ * \brief     Get the specified ENHTIMx latch count value.
+ *
+ * \param[in] ENHTIMx      Select the ENHTIM peripheral. Refer to \ref ENHTIM_Declaration.
+ * \param[in] LatchCntIdx  E_ENHTIM_LATCHCNT enum value.
+ *                         This parameter can be one of the following values, Refer to \ref ENHTIM_Latch_Channel_Count.
+ *                         - LATCH_CNT_0: Enhance timer latch count 0.
+ *                         - LATCH_CNT_1: Enhance timer latch count 1.
+ *                         - LATCH_CNT_2: Enhance timer latch count 2.
+ *
+ * \return    The latch counter value.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void enhance_timer_demo(void)
+ * {
+ *     uint32_t count_value = ENHTIM_GetLatchCountValue(ENH_TIM0, LATCH_CNT_0);
+ * }
+ * \endcode
+ */
+uint32_t ENHTIM_GetLatchCount(ENHTIM_TypeDef *ENHTIMx,
+                              ENHTIMLatchCnt_TypeDef LatchCntIdx);
+
+/**
+ * \brief     Get the specified ENHTIMx latch count fifo length.
+ *
+ * \param[in] ENHTIMx  Select the ENHTIM peripheral. Refer to \ref ENHTIM_Declaration.
+ *
+ * \return    FIFO data length.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void enhance_timer_demo(void)
+ * {
+ *     uint8_t length = ENHTIM_GetLatchCountFIFOLength(ENH_TIM0);
+ * }
+ * \endcode
+ */
+uint8_t ENHTIM_GetLatchCountFIFOLength(ENHTIM_TypeDef *ENHTIMx);
+
+/**
+ * \brief     Clear the capture/compare or latch count FIFO.
+ *
+ * \param[in] ENHTIMx   Select the ENHTIM peripheral. Refer to \ref ENHTIM_Declaration.
+ * \param[in] FIFO_CLR  Specify the FIFO type which to be clear.
+ *                      This parameter can be one of the following values, Refer to \ref ENHTIM_FIFO_Clear.
+ *                      - ENHTIM_FIFO_CLR_CCR: Enhance Timer CCR FIFO clear flag.
+ *                      - ENHTIM_FIFO_CLR_CNT0: Enhance Timer latch count2 FIFO clear flag.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void enhance_timer_demo(void)
+ * {
+ *     ENHTIM_ClearFIFO(ENH_TIM0, ENHTIM_FIFO_CLR_CCR);
+ * }
+ * \endcode
+ */
+void ENHTIM_ClearFIFO(ENHTIM_TypeDef *ENHTIMx, uint8_t FIFO_CLR);
+
+/**
+ * \brief   ENHTIM PWM complementary output emergency stop.
+ *
+ * \param[in] ENHTIMx  Select the ENHTIM peripheral. Refer to \ref ENHTIM_Declaration.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void enhance_timer_demo(void)
+ * {
+ *     ENHTIM_PWMDeadZoneEMStop(ENH_TIM0);
+ * }
+ * \endcode
+ */
+void ENHTIM_PWMDeadZoneEMStop(ENHTIM_TypeDef *ENHTIMx);
+
+#if ENHTIM_SUPPORT_PWM_SRC_SELECT
+/**
+ * \brief   ENHTIM PWMP/N Source Select.
+ *
+ * \param[in] ENHTIMx    Select the ENHTIM peripheral. Refer to \ref ENHTIM_Declaration.
+ * \param[in] PWMSrcSel  PWMP/N reference selection. The actual output waveforms of the P and N in complementary PWM mode.
+ *                       This parameter can be one of the following values, Refer to \ref ENHPWM_Reference_Selection.
+ *                       - ENHTIM_DZ_REF_PWMPN: PWM P waveform is PWM_P, PWM N waveform is PWM_N,
+ *                       - ENHTIM_DZ_REF_PWMNN: PWM P waveform is PWM_N, PWM N waveform is PWM_N,
+ *                       - ENHTIM_DZ_REF_PWMPP: PWM P waveform is PWM_P, PWM N waveform is PWM_P,
+ *                       - ENHTIM_DZ_REF_PWMNP: PWM P waveform is PWM_N, PWM N waveform is PWM_P,
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void enhance_timer_demo(void)
+ * {
+ *     ENHTIM_PWMSrcSelect(ENH_TIM0, ENHTIM_DZ_REF_PWMPN)
+ * }
+ * \endcode
+ */
+void ENHTIM_PWMSrcSelect(ENHTIM_TypeDef *ENHTIMx, ENHTIMPWMDZRef_TypeDef PWMSrcSel);
+#endif
+
+/**
+ * \brief     Get all the ENHTIM interrupt status.
+ *
+ * \return    All Status of the ENHTIM interrupts.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void enhance_timer_demo(void)
+ * {
+ *     ITStatus int_status = ENHTIM_GetAllINTStatus();
+ * }
+ * \endcode
+ */
+uint32_t ENHTIM_GetAllINTStatus(void);
+
+#if ENHTIM_SUPPORT_ONESHOT_CMD
+/**
+ * \brief  Enable or disable the specified ENHTIMx oneshot mode.
+ *
+ * \param[in] ENHTIMx   Select the ENHTIM peripheral. Refer to \ref ENHTIM_Declaration.
+ * \param[in] NewState  New state of the ENHTIMx peripheral.
+ *                      This parameter can be one of the following values:
+ *                      - ENABLE: The timer only triggers the timing function once.
+ *                      - DISABLE: Disable the oneshot mode function.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void enhance_timer_demo(void)
+ * {
+ *     ENHTIM_OneShotCmd(ENH_TIM0, ENABLE);
+ * }
+ * \endcode
+ */
+void ENHTIM_OneShotCmd(ENHTIM_TypeDef *ENHTIMx, FunctionalState NewState);
+#endif
+
+/**
+ * \brief  Get the ENHTIM latch count0 FIFO status.
+ *
+ * \param[in] ENHTIMx  Select the ENHTIM peripheral. Refer to \ref ENHTIM_Declaration.
+ *
+ * \return   The status of the specified ENHTIMx latch count0 FIFO.
+ *           - SET: ENHTIM latch count0 FIFO has data.
+ *           - RESET: ENHTIM latch count0 FIFO has no data.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void enhance_timer_demo(void)
+ * {
+ *     ENHTIM_GetLCFIFOStatus(ENH_TIM0);
+ * }
+ * \endcode
+ */
+ITStatus ENHTIM_GetLCFIFOStatus(ENHTIM_TypeDef *ENHTIMx);
+
+/**
+ * \brief  Change the specified ENHTIMx PWM frequency and duty cycle.
+ *
+ * \param[in]  ENHTIMx      Select the ENHTIM peripheral. Refer to \ref ENHTIM_Declaration.
+ * \param[in]  ENHTIM_mode  This parameter can be ENHTIM_MODE_PWM_MANUAL or ENHTIM_MODE_PWM_AUTO.
+ * \param[in]  max_count    Timer max counter value for user-define mode.
+ *                          This parameter can be 1 ~ 2^32-2
+ * \param[in]  high_count   Timer capture/compare value for user-define manual mode.
+ *                          Timer capture/compare fifo entry for user-define auto mode.
+ *                          This parameter can be 0 ~ 2^32-2
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void enhance_timer_demo(void)
+ * {
+ *     ENHTIM_PWMChangeFreqAndDuty(ENH_TIM0, ENHTIM_MODE_PWM_MANUAL, 1000, 100);
+ * }
+ * \endcode
+ */
+void ENHTIM_PWMChangeFreqAndDuty(ENHTIM_TypeDef *ENHTIMx, uint16_t ENHTIM_mode, uint32_t max_count,
+                                 uint32_t high_count);
+
+#if ENHTIM_SUPPORT_CLOCK_SOURCE_CONFIG
+/**
+ * \brief  ENHTIM clock config.
+ *
+ * \param[in]  ENHTIMx   Select the ENHTIM peripheral. Refer to \ref ENHTIM_Declaration.
+ * \param[in]  ClockSrc  Specify the ENHTIM clock source.  Refer to \ref ENHTIM_Clock_Source.
+ * \param[in]  ClockDiv  Specify the ENHTIM clock source divider. Refer to \ref ENHTIM_Clock_Divider.
+ *
+ */
+void ENHTIM_ClkConfig(ENHTIM_TypeDef *ENHTIMx, ENHTIMClkSrc_TypdDef ClockSrc,
+                      ENHTIMClkDiv_TypeDef ClockDiv);
+
+/**
+ * \brief  Get ENHTIM clock config.
+ *
+ * \param[in]  ENHTIMx    Select the ENHTIM peripheral. Refer to \ref ENHTIM_Declaration.
+ * \param[out]  ClockSrc  Specify the ENHTIM clock source. Refer to \ref ENHTIM_Clock_Source.
+ * \param[out]  ClockDiv  Specify the ENHTIM clock source divider. Refer to \ref ENHTIM_Clock_Divider.
+ *
+ * \return   The status of the ENHTIM clock configuration .
+ *           - TRUE: get clock configuration successful.
+ *           - FALSE: get clock configuration false.
+ */
+bool ENHTIM_ClkGet(ENHTIM_TypeDef *ENHTIMx, ENHTIMClkSrc_TypdDef *ClockSrc,
+                   ENHTIMClkDiv_TypeDef *ClockDiv);
+#endif
+
+/** End of ENHTIM_Exported_Functions
+  * \}
+  */
+
+/** End of ENHTIM
+  * \}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RTL_ENH_TIM_H */
diff --git a/bee/drivers/timer/src/device/rtl87x2g/rtl_enhtim_def.h b/bee/drivers/timer/src/device/rtl87x2g/rtl_enhtim_def.h
new file mode 100644
index 00000000..839bf5f0
--- /dev/null
+++ b/bee/drivers/timer/src/device/rtl87x2g/rtl_enhtim_def.h
@@ -0,0 +1,852 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef RTL_ENHTIM_DEF_H
+#define RTL_ENHTIM_DEF_H
+
+#include "utils/rtl_utils.h"
+#include "address_map.h"
+#include "platform_reg.h"
+
+#ifdef  __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/*============================================================================*
+ *                          ENHTIM Defines
+ *============================================================================*/
+/** \defgroup ENHTIM      ENHTIM
+  * \brief
+  * \{
+  */
+
+/** \defgroup ENHTIM_Exported_Constants ENHTIM Exported Constants
+  * \brief
+  * \{
+  */
+
+/**
+ * \defgroup ENHTIM_Defines ENHTIM Defines
+ * \{
+ * \ingroup  ENHTIM_Exported_Constants
+ */
+#define CHIP_ENHTIM_CHANNEL_NUM                        (4)     //!< The chip supports 4 ENHTIM.
+#define ENHTIM_SUPPORT_LATCH_CNT_0                     (1)     //!< The chip supports latch count0 function.
+#define ENHTIM_SUPPORT_LATCH_CNT_1                     (1)     //!< The chip supports latch count1 function.
+#define ENHTIM_SUPPORT_LATCH_CNT_2                     (1)     //!< The chip supports latch count2 function.
+#define ENHTIM_SUPPORT_PWM_SRC_SELECT                  (1)     //!< The chip supports PWM clock source select.
+#define ENHTIM_SUPPORT_PWM_PHASE_SHIFT                 (1)     //!< The chip supports PWM phase shift.
+#define ENHTIM_SUPPORT_ONESHOT_CMD                     (1)     //!< The chip supports oneshot mode.
+#define ENHTIM_SUPPORT_CLOCK_SOURCE_CONFIG             (1)     //!< The chip supports clock source config.
+
+/** End of ENHTIM_Defines
+  * \}
+  */
+
+/** End of ENHTIM_Exported_Constants
+  * \}
+  */
+
+/** End of ENHTIM
+  * \}
+  */
+/*============================================================================*
+ *                         ENHTIM Registers Memory Map
+ *============================================================================*/
+typedef struct
+{
+    __I  uint32_t ENHTIM_CUR_CNT;                /*!< 0x00 */
+    __I  uint32_t ENHTIM_LATCH_CNT_0;            /*!< 0x04 */
+    __I  uint32_t ENHTIM_LATCH_CNT_1;            /*!< 0x08 */
+    __I  uint32_t ENHTIM_LATCH_CNT_2;            /*!< 0x0C */
+    __IO uint32_t ENHTIM_CONFIGURE;              /*!< 0x10 */
+    __IO uint32_t ENHTIM_MAX_CNT;                /*!< 0x14 */
+    __IO uint32_t ENHTIM_CCR;                    /*!< 0x18 */
+    __IO uint32_t ENHTIM_CCR_FIFO_ENTRY;         /*!< 0x1C */
+    __IO uint32_t PHASE_SHIFT_CNT;               /*!< 0x20*/
+} ENHTIM_TypeDef;
+
+typedef struct
+{
+    __IO uint32_t ENHTIM_LACTH_FIFO_TH_STATUS;   /*!< 0x120 */
+    __IO uint32_t ENHTIM_LATCH_CNT_FIFO_STATUS;  /*!< 0x124 */
+    __I  uint32_t ENHTIM_CCR_FIFO_STATUS;        /*!< 0x128 */
+    __IO uint32_t ENHTIM_FIFO_CLR;               /*!< 0x12C */
+    __IO uint32_t ENHTIM_CONTROL;                /*!< 0x130 */
+    __IO uint32_t ENHTIM_INT_CONTROL;            /*!< 0x134 */
+    __IO uint32_t ENHTIM_STATUS;                 /*!< 0x138 */
+    __I  uint32_t ENHTIM_INT_STATUS;             /*!< 0x13C */
+    __IO uint32_t ENHTIM_LATCH_INT_CONTROL_0;    /*!< 0x140 */
+    __IO uint32_t RESERVED0;                     /*!< 0x144 */
+    __IO uint32_t ENHTIM_LATCH_INT_CONTROL_2;    /*!< 0x148 */
+    __IO uint32_t RESERVED1;                     /*!< 0x14C */
+    __I  uint32_t ENHTIM0_LATCH_FIFO_DEPTH;      /*!< 0x150 */
+    __I  uint32_t ENHTIM1_LATCH_FIFO_DEPTH;      /*!< 0x154 */
+    __I  uint32_t ENHTIM2_LATCH_FIFO_DEPTH;      /*!< 0x158 */
+    __I  uint32_t ENHTIM3_LATCH_FIFO_DEPTH;      /*!< 0x15C */
+    __I  uint32_t RSVD[4];                       /*!< 0x160 - 0x16C */
+    __I  uint32_t ENHTIM_TOGGLE_STATE;           /*!< 0x170 */
+} ENHTIM_ShareTypeDef;
+
+typedef struct
+{
+    __IO uint32_t ENHTIMER_PWM_CFG;              /*!< 0x300 */
+} ENHPWM_TypeDef;
+
+/*============================================================================*
+ *                         ENHTIM Declaration
+ *============================================================================*/
+#define ENHANCED_TIMER0_REG_BASE        (ENHANCED_TIMER_REG_BASE + 0x0000)
+#define ENHANCED_TIMER1_REG_BASE        (ENHANCED_TIMER_REG_BASE + 0x0024)
+#define ENHANCED_TIMER2_REG_BASE        (ENHANCED_TIMER_REG_BASE + 0x0048)
+#define ENHANCED_TIMER3_REG_BASE        (ENHANCED_TIMER_REG_BASE + 0x006c)
+#define ENHTIM_SHARE_REG_BASE           (ENHANCED_TIMER_REG_BASE + 0x0120)
+#define ENHANCED_PWM0_REG_BASE          (ENHANCED_TIMER_REG_BASE + 0x0300)
+#define ENHANCED_PWM1_REG_BASE          (ENHANCED_TIMER_REG_BASE + 0x0304)
+#define ENHANCED_PWM2_REG_BASE          (ENHANCED_TIMER_REG_BASE + 0x0308)
+#define ENHANCED_PWM3_REG_BASE          (ENHANCED_TIMER_REG_BASE + 0x030C)
+#define REG_ENHTIMER_ONESHOT_CFG        (ENHANCED_TIMER_REG_BASE + 0x0320)
+
+
+/** \defgroup ENHTIM      ENHTIM
+  * \brief
+  * \{
+  */
+
+/** \defgroup ENHTIM_Exported_Constants ENHTIM Exported Constants
+  * \brief
+  * \{
+  */
+
+/** \defgroup ENHTIM_Declaration ENHTIM Declaration
+  * \{
+  * \ingroup  ENHTIM_Exported_Constants
+  */
+
+#define ENH_TIM0           ((ENHTIM_TypeDef      *) ENHANCED_TIMER0_REG_BASE)   //!< ENH_TIM0 base address.
+#define ENH_TIM1           ((ENHTIM_TypeDef      *) ENHANCED_TIMER1_REG_BASE)   //!< ENH_TIM1 base address.
+#define ENH_TIM2           ((ENHTIM_TypeDef      *) ENHANCED_TIMER2_REG_BASE)   //!< ENH_TIM2 base address.
+#define ENH_TIM3           ((ENHTIM_TypeDef      *) ENHANCED_TIMER3_REG_BASE)   //!< ENH_TIM3 base address.
+#define ENH_TIM_SHARE      ((ENHTIM_ShareTypeDef *) ENHTIM_SHARE_REG_BASE)      //!< The register address shared by all enhtim.
+#define ENH_TIM0_PWM       ((ENHPWM_TypeDef      *) ENHANCED_PWM0_REG_BASE)     //!< ENH_TIM0_PWM base address.
+#define ENH_TIM1_PWM       ((ENHPWM_TypeDef      *) ENHANCED_PWM1_REG_BASE)     //!< ENH_TIM1_PWM base address.
+#define ENH_TIM2_PWM       ((ENHPWM_TypeDef      *) ENHANCED_PWM2_REG_BASE)     //!< ENH_TIM2_PWM base address.
+#define ENH_TIM3_PWM       ((ENHPWM_TypeDef      *) ENHANCED_PWM3_REG_BASE)     //!< ENH_TIM3_PWM base address.
+
+#define IS_ENHTIM_ALL_PERIPH(PERIPH)    (((PERIPH) == ENH_ENHTIM0) || \
+                                         ((PERIPH) == ENH_ENHTIM1) || \
+                                         ((PERIPH) == ENH_ENHTIM2) || \
+                                         ((PERIPH) == ENH_ENHTIM3)) //!< Check if the input parameter is valid.
+/** End of ENHTIM_Declaration
+  * \}
+  */
+
+/** End of ENHTIM_Exported_Constants
+  * \}
+  */
+
+/** End of ENHTIM
+  * \}
+  */
+
+/*============================================================================*
+ *                         ENHTIM Private Defines
+ *============================================================================*/
+#define REG_ENHTIMER_CLOCK_CTRL            *((volatile uint32_t *)0x40002344UL)
+#define REG_ENHTIMER_0_LATCH_TRIG_CFG      *((volatile uint32_t *)0x400030C0UL)
+#define REG_ENHTIMER_1_LATCH_TRIG_CFG      *((volatile uint32_t *)0x400030C4UL)
+#define REG_ENHTIMER_2_LATCH_TRIG_CFG      *((volatile uint32_t *)0x400030C8UL)
+#define REG_ENHTIMER_3_LATCH_TRIG_CFG      *((volatile uint32_t *)0x400030CCUL)
+#define REG_BT_GPIO_TRIG_ENHTIMER_CTRL     *((volatile uint32_t *)0x400030D0UL)
+#define REG_BT_TX_ON_TRIG_ENHTIMER_CTRL    *((volatile uint32_t *)0x400030D4UL)
+#define REG_BT_ACC_HIT_TRIG_ENHTIMER_CTRL  *((volatile uint32_t *)0x400030D8UL)
+#define REG_ENHTIMER_ONESHOT               *((volatile uint32_t *)REG_ENHTIMER_ONESHOT_CFG)
+#define ENHTIM_GetCurrentControl(ENHTIMx)   (((ENHTIM_TypeDef *)(ENHTIMx))->ENHTIM_CONFIGURE)
+#define ENHTIM_GetCurrentMAXCNT(ENHTIMx)    (((ENHTIM_TypeDef *)(ENHTIMx))->ENHTIM_MAX_CNT)
+/*============================================================================*
+ *                         ENHTIM Private Types
+ *============================================================================*/
+typedef struct
+{
+    uint32_t enhtim_reg[31];
+    uint32_t enhpwm_reg[4];
+} ENHTIMStoreReg_Typedef;
+
+/*============================================================================*
+ *                         ENHTIM Registers and Field Descriptions
+ *============================================================================*/
+/* 0x00
+   31:0    R      Enhtimer_cur_cnt                            32'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        const uint32_t Enhtimer_cur_cnt: 32;
+    } b;
+} ENHTIM_CUR_CNT_TypeDef;
+
+
+
+/* 0x04
+   31:0    R      Enhtimer_latch_cnt_0                        32'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        const uint32_t Enhtimer_latch_cnt_0: 32;
+    } b;
+} ENHTIM_LATCH_CNT_0_TypeDef;
+
+
+
+/* 0x08
+   31:0    R      Enhtimer_latch_cnt_1                        32'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        const uint32_t reg_timer_0_latch_cnt_1: 32;
+    } b;
+} ENHTIM_LATCH_CNT_1_TypeDef;
+
+
+
+/* 0x0C
+   31:0    R      Enhtimer_latch_cnt_2                        32'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        const uint32_t reg_timer_0_latch_cnt_2: 32;
+    } b;
+} ENHTIM_LATCH_CNT_2_TypeDef;
+
+
+
+/* 0x10
+   1:0     R/W    Enhtimer_mode                               2'h0
+   2       R/W    Enhtimer_PWM_polarity                       1'h0
+   3       R/W    Enhtimer_PWM_output_en                      1'h0
+   5:4     R/W    Enhtimer_latch_cnt_0_trig_mode              2'h0
+   7:6     R/W    Enhtimer_latch_cnt_1_trig_mode              2'h0
+   9:8     R/W    Enhtimer_latch_cnt_2_trig_mode              2'h0
+   10      R/W    Enhtimer_Latch_cnt_0_en                     1'h0
+   11      R/W    Enhtimer_Latch_cnt_1_en                     1'h0
+   12      R/W    Enhtimer_Latch_cnt_2_en                     1'h0
+   17:13   R/W    Enhtimer_latch_cnt_0_fifo_th                5'h1
+   22:18   R/W    RSVD                                        5'h1
+   27:23   R/W    RSVD                                        5'h1
+   28      R/W    Enhtimer_dma_en                             1'h0
+   29      R/W    Enhtimer_dma_mode                           1'h0
+   31:30   R/W    Enhtimer_dma_target                         2'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t Enhtimer_mode: 2;
+        uint32_t Enhtimer_PWM_polarity: 1;
+        uint32_t Enhtimer_PWM_output_en: 1;
+        uint32_t Enhtimer_latch_cnt_0_trig_mode: 2;
+        uint32_t Enhtimer_latch_cnt_1_trig_mode: 2;
+        uint32_t Enhtimer_latch_cnt_2_trig_mode: 2;
+        uint32_t Enhtimer_Latch_cnt_0_en: 1;
+        uint32_t Enhtimer_Latch_cnt_1_en: 1;
+        uint32_t Enhtimer_Latch_cnt_2_en: 1;
+        uint32_t Enhtimer_latch_cnt_0_fifo_th: 5;
+        uint32_t reserved_1: 5;
+        uint32_t reserved_0: 5;
+        uint32_t Enhtimer_dma_en: 1;
+        uint32_t Enhtimer_dma_mode: 1;
+        uint32_t Enhtimer_dma_target: 2;
+    } b;
+} ENHTIM_CONFIGURE_TypeDef;
+
+
+
+/* 0x14
+   31:0    R/W    Enhtimer_max_cnt                            32'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t Enhtimer_max_cnt: 32;
+    } b;
+} ENHTIM_MAX_CNT_TypeDef;
+
+
+
+/* 0x18
+   31:0    R/W    Enhtimer_ccr                                32'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t Enhtimer_ccr: 32;
+    } b;
+} ENHTIM_CCR_TypeDef;
+
+
+
+/* 0x1C
+   31:0    R/W    Enhtimer_ccr_fifo_entry                     32'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t Enhtimer_ccr_fifo_entry: 32;
+    } b;
+} ENHTIM_CCR_FIFO_ENTRY_TypeDef;
+
+
+
+
+/* 0x20
+    31:0    R/W    Enhtimer_pwm_phase_shift_cnt             32'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t Enhtimer_pwm_phase_shift_cnt: 32;
+    } b;
+} ENHTIMER_0_PWM_SHIFT_CNT_TypeDef;
+
+
+
+/* 0x120
+   0       R/W1C  Enhtimer0_latch_cnt_0_fifo_met_th           1'h0
+   1       R/W1C  Enhtimer1_latch_cnt_0_fifo_met_th           1'h0
+   2       R/W1C  Enhtimer2_latch_cnt_0_fifo_met_th           1'h0
+   3       R/W1C  Enhtimer3_latch_cnt_0_fifo_met_th           1'h0
+   31:4    R      RSVD                                        28'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t Enhtimer0_latch_cnt_0_fifo_met_th: 1;
+        uint32_t Enhtimer1_latch_cnt_0_fifo_met_th: 1;
+        uint32_t Enhtimer2_latch_cnt_0_fifo_met_th: 1;
+        uint32_t Enhtimer3_latch_cnt_0_fifo_met_th: 1;
+        const uint32_t reserved_0: 28;
+    } b;
+} ENHTIM_LACTH_FIFO_TH_STATUS_TypeDef;
+
+
+
+/* 0x124
+   0       R/W1C  Enhtimerr0_latch_cnt_0_fifo_full            1'h0
+   1       R      Enhtimer0_latch_cnt_0_fifo_empty            1'h1
+   2       R/W1C  Enhtimer1_latch_cnt_0_fifo_full             1'h0
+   3       R      Enhtimer1_latch_cnt_0_fifo_empty            1'h1
+   4       R/W1C  Enhtimer2_latch_cnt_0_fifo_full             1'h0
+   5       R      Enhtimer2_latch_cnt_0_fifo_empty            1'h1
+   6       R/W1C  Enhtimer3_latch_cnt_0_fifo_full             1'h0
+   7       R      Enhtimer3_latch_cnt_0_fifo_empty            1'h1
+   31:8    R      RSVD                                        24'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t Enhtimerr0_latch_cnt_0_fifo_full: 1;
+        const uint32_t Enhtimer0_latch_cnt_0_fifo_empty: 1;
+        uint32_t Enhtimer1_latch_cnt_0_fifo_full: 1;
+        const uint32_t Enhtimer1_latch_cnt_0_fifo_empty: 1;
+        uint32_t Enhtimer2_latch_cnt_0_fifo_full: 1;
+        const uint32_t Enhtimer2_latch_cnt_0_fifo_empty: 1;
+        uint32_t Enhtimer3_latch_cnt_0_fifo_full: 1;
+        const uint32_t Enhtimer3_latch_cnt_0_fifo_empty: 1;
+        const uint32_t reserved_0: 24;
+    } b;
+} ENHTIM_LATCH_CNT_FIFO_STATUS_TypeDef;
+
+
+
+/* 0x128
+   0       R      Enhtimerr0_ccr_fifo_full                    1'h0
+   1       R      Enhtimer0_ccr_fifo_empty                    1'h1
+   2       R      Enhtimer1_ccr_fifo_full                     1'h0
+   3       R      Enhtimer1_ccr_fifo_empty                    1'h1
+   4       R      Enhtimer2_ccr_fifo_full                     1'h0
+   5       R      Enhtimer2_ccr_fifo_empty                    1'h1
+   6       R      Enhtimer3_ccr_fifo_full                     1'h0
+   7       R      Enhtimer3_ccr_fifo_empty                    1'h1
+   31:8    R      RSVD                                        24'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        const uint32_t Enhtimerr0_ccr_fifo_full: 1;
+        const uint32_t Enhtimer0_ccr_fifo_empty: 1;
+        const uint32_t Enhtimer1_ccr_fifo_full: 1;
+        const uint32_t Enhtimer1_ccr_fifo_empty: 1;
+        const uint32_t Enhtimer2_ccr_fifo_full: 1;
+        const uint32_t Enhtimer2_ccr_fifo_empty: 1;
+        const uint32_t Enhtimer3_ccr_fifo_full: 1;
+        const uint32_t Enhtimer3_ccr_fifo_empty: 1;
+        const uint32_t reserved_0: 24;
+    } b;
+} ENHTIM_CCR_FIFO_STATUS_TypeDef;
+
+
+
+/* 0x12C
+   0       R/W1C  Enhtimer0_ccr_fifo_clr                      1'h0
+   1       R/W1C  Enhtimer1_ccr_fifo_clr                      1'h0
+   2       R/W1C  Enhtimer2_ccr_fifo_clr                      1'h0
+   3       R/W1C  Enhtimer3_ccr_fifo_clr                      1'h0
+   7:4     R      RSVD0                                       4'h0
+   8       R/W1C  Enhtimer0_latch_cnt_0_fifo_clr              1'h0
+   9       R/W1C  Enhtimer1_latch_cnt_0_fifo_clr              1'h0
+   10      R/W1C  Enhtimer2_latch_cnt_0_fifo_clr              1'h0
+   11      R/W1C  Enhtimer3_latch_cnt_0_fifo_clr              1'h0
+   31:12   R      RSVD1                                       20'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t Enhtimer0_ccr_fifo_clr: 1;
+        uint32_t Enhtimer1_ccr_fifo_clr: 1;
+        uint32_t Enhtimer2_ccr_fifo_clr: 1;
+        uint32_t Enhtimer3_ccr_fifo_clr: 1;
+        const  uint32_t reserved_0: 4;
+        uint32_t Enhtimer0_latch_cnt_0_fifo_clr: 1;
+        uint32_t Enhtimer1_latch_cnt_0_fifo_clr: 1;
+        uint32_t Enhtimer2_latch_cnt_0_fifo_clr: 1;
+        uint32_t Enhtimer3_latch_cnt_0_fifo_clr: 1;
+        const  uint32_t reserved_1: 20;
+    } b;
+} ENHTIM_FIFO_CLR_TypeDef;
+
+
+
+/* 0x130
+   0       R/W    Enhtimer0_enable                            1'h0
+   1       R/W    Enhtimer1_enable                            1'h0
+   2       R/W    Enhtimer2_enable                            1'h0
+   3       R/W    Enhtimer3_enable                            1'h0
+   31:4    R      RSVD                                        28'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t Enhtimer0_enable: 1;
+        uint32_t Enhtimer1_enable: 1;
+        uint32_t Enhtimer2_enable: 1;
+        uint32_t Enhtimer3_enable: 1;
+        const uint32_t reserved_0: 28;
+    } b;
+} ENHTIM_CONTROL_TypeDef;
+
+
+
+/* 0x134
+   0       R/W    Enhtimer0_Interrupt_enable                  1'h0
+   1       R/W    Enhtimer1_Interrupt_enable                  1'h0
+   2       R/W    Enhtimer2_Interrupt_enable                  1'h0
+   3       R/W    Enhtimer3_Interrupt_enable                  1'h0
+   31:4    R      RSVD                                        28'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t Enhtimer0_Interrupt_enable: 1;
+        uint32_t Enhtimer1_Interrupt_enable: 1;
+        uint32_t Enhtimer2_Interrupt_enable: 1;
+        uint32_t Enhtimer3_Interrupt_enable: 1;
+        uint32_t reserved_0: 28;
+    } b;
+} ENHTIM_INT_CONTROL_TypeDef;
+
+
+
+/* 0x138
+   0       R/W1C  Enhtimer0_Status                            1'h0
+   1       R/W1C  Enhtimer1_Status                            1'h0
+   2       R/W1C  Enhtimer2_Status                            1'h0
+   3       R/W1C  Enhtimer3_Status                            1'h0
+   7:4     R      RSVD0                                       4'h0
+   8       R/W1C  Enhtimer0_latch_cnt_0_fifo_intr_status      1'h0
+   9       R/W1C  Enhtimer1_latch_cnt_0_fifo_intr_status      1'h0
+   10      R/W1C  Enhtimer2_latch_cnt_0_fifo_intr_status      1'h0
+   11      R/W1C  Enhtimer3_latch_cnt_0_fifo_intr_status      1'h0
+   31:12   R      RSVD1                                       20'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t Enhtimer0_Status: 1;
+        uint32_t Enhtimer1_Status: 1;
+        uint32_t Enhtimer2_Status: 1;
+        uint32_t Enhtimer3_Status: 1;
+        uint32_t reserved_0: 4;
+        uint32_t Enhtimer0_latch_cnt_0_fifo_intr_status: 1;
+        uint32_t Enhtimer1_latch_cnt_0_fifo_intr_status: 1;
+        uint32_t Enhtimer2_latch_cnt_0_fifo_intr_status: 1;
+        uint32_t Enhtimer3_latch_cnt_0_fifo_intr_status: 1;
+        uint32_t reserved_1: 20;
+    } b;
+} ENHTIM_STATUS_TypeDef;
+
+
+
+/* 0x13C
+   0       R      reg_timer_0_interrupt_masked                1'h0
+   1       R      reg_timer_1_interrupt_masked                1'h0
+   2       R      reg_timer_2_interrupt_masked                1'h0
+   3       R      reg_timer_3_interrupt_masked                1'h0
+   31:8    R      RSVD                                        28'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        const uint32_t reg_timer_0_interrupt_masked: 1;
+        const uint32_t reg_timer_1_interrupt_masked: 1;
+        const uint32_t reg_timer_2_interrupt_masked: 1;
+        const uint32_t reg_timer_3_interrupt_masked: 1;
+        const uint32_t reserved_0: 28;
+    } b;
+} ENHTIM_INT_STATUS_TypeDef;
+
+
+
+/* 0x140
+   7:0     R      RSVD                                        8'h0
+   8       R/W    Enhtimer0_latch_cnt_0_fifo_full_intr_en     1'h0
+   9       R/W    Enhtimer1_latch_cnt_0_fifo_full_intr_en     1'h0
+   10      R/W    Enhtimer2_latch_cnt_0_fifo_full_intr_en     1'h0
+   11      R/W    Enhtimer3_latch_cnt_0_fifo_full_intr_en     1'h0
+   31:12   R      RSVD                                        16'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        const uint32_t reserved_16: 8;
+        uint32_t Enhtimer0_latch_cnt_0_fifo_full_intr_en: 1;
+        uint32_t Enhtimer1_latch_cnt_0_fifo_full_intr_en: 1;
+        uint32_t Enhtimer2_latch_cnt_0_fifo_full_intr_en: 1;
+        uint32_t Enhtimer3_latch_cnt_0_fifo_full_intr_en: 1;
+        const  uint32_t reserved_0: 20;
+    } b;
+} ENHTIM_LATCH_INT_CONTROL_0_TypeDef;
+
+
+
+/* 0x148
+   7:0     R      RSVD                                        8'h0
+   8       R/W    Enhtimer0_latch_cnt_0_fifo_met_th_intr_en   1'h0
+   9       R/W    Enhtimer1_latch_cnt_0_fifo_met_th_intr_en   1'h0
+   10      R/W    Enhtimer2_latch_cnt_0_fifo_met_th_intr_en   1'h0
+   11      R/W    Enhtimer3_latch_cnt_0_fifo_met_th_intr_en   1'h0
+   31:12   R      RSVD                                        20'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        const  uint32_t reserved_1: 8;
+        uint32_t Enhtimer0_latch_cnt_0_fifo_met_th_intr_en: 1;
+        uint32_t Enhtimer1_latch_cnt_0_fifo_met_th_intr_en: 1;
+        uint32_t Enhtimer2_latch_cnt_0_fifo_met_th_intr_en: 1;
+        uint32_t Enhtimer3_latch_cnt_0_fifo_met_th_intr_en: 1;
+        const  uint32_t reserved_0: 20;
+    } b;
+} ENHTIM_LATCH_INT_CONTROL_2_TypeDef;
+
+
+
+
+/* 0x150
+   7:0     R      Enhtimer0_latch_cnt_0_fifo_depth            8'h0
+   31:8    R      RSVD                                        24'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        const uint32_t Enhtimer0_latch_cnt_0_fifo_depth: 8;
+        const uint32_t reserved_0: 24;
+    } b;
+} ENHTIM0_LATCH_FIFO_DEPTH_TypeDef;
+
+
+
+/* 0x154
+   7:0     R      Enhtimer1_latch_cnt_0_fifo_depth            8'h0
+   31:8    R      RSVD                                        24'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        const uint32_t Enhtimer1_latch_cnt_0_fifo_depth: 8;
+        const uint32_t reserved_0: 24;
+    } b;
+} ENHTIM1_LATCH_FIFO_DEPTH_TypeDef;
+
+
+
+/* 0x158
+   7:0     R      Enhtimer2_latch_cnt_0_fifo_depth            8'h0
+   31:8    R      RSVD                                        24'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        const uint32_t Enhtimer2_latch_cnt_0_fifo_depth: 8;
+        const uint32_t reserved_0: 24;
+    } b;
+} ENHTIM2_LATCH_FIFO_DEPTH_TypeDef;
+
+
+
+/* 0x15C
+   7:0     R      Enhtimer3_latch_cnt_0_fifo_depth            8'h0
+   31:8    R      RSVD                                        24'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        const uint32_t Enhtimer3_latch_cnt_0_fifo_depth: 8;
+        const uint32_t reserved_0: 24;
+    } b;
+} ENHTIM3_LATCH_FIFO_DEPTH_TypeDef;
+
+
+
+/* 0x170
+   0       R      Enhtimer0_toggle_state                      1'h0
+   1       R      Enhtimer1_toggle_state                      1'h0
+   2       R      Enhtimer2_toggle_state                      1'h0
+   3       R      Enhtimer3_toggle_state                      1'h0
+   31:4    R      RSVD                                        28'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        const uint32_t Enhtimer0_toggle_state: 1;
+        const uint32_t Enhtimer1_toggle_state: 1;
+        const uint32_t Enhtimer2_toggle_state: 1;
+        const uint32_t Enhtimer3_toggle_state: 1;
+        const uint32_t reserved_0: 28;
+    } b;
+} ENHTIM_TOGGLE_STATE_TypeDef;
+
+
+
+/* 0x300
+    7:0     R/W    enhtimer_pwm_dz_size                     8'h0
+    8       R/W    enhtimer_pwm_dz_emg_stop                 1'h0
+    9       R/W    enhtimer_pwm_dz_stop_state_n             1'h0
+    10      R/W    enhtimer_pwm_dz_stop_state_p             1'h0
+    11      R/W    enhtimer_pwm_dz_en                       1'h0
+    13:12   R/W    enhtimer_pwm_dz_ref_sel                  2'h0
+    14      R/W    enhtimer_pwm_dz_ref_n_inv_en             1'h0
+    15      R/W    enhtimer_pwm_dz_ref_p_inv_en             1'h0
+    16      R/W    enhtimer_pwm_open_drain_en               1'h0
+    31:17   R      RSVD529                                     15'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t enhtimer_pwm_dz_size: 8;
+        uint32_t enhtimer_pwm_dz_emg_stop: 1;
+        uint32_t enhtimer_pwm_dz_stop_state_n: 1;
+        uint32_t enhtimer_pwm_dz_stop_state_p: 1;
+        uint32_t enhtimer_pwm_dz_en: 1;
+        uint32_t enhtimer_pwm_dz_ref_sel: 2;
+        uint32_t enhtimer_pwm_dz_ref_n_inv_en: 1;
+        uint32_t enhtimer_pwm_dz_ref_p_inv_en: 1;
+        uint32_t enhtimer_pwm_open_drain_en: 1;
+        const uint32_t RSVD529: 15;
+    } b;
+} ENHTIMER_PWM_CFG_TypeDef;
+
+
+
+/* 0x320
+    0       R/W    Enhtimer_0_oneshot_mode_en                 1'h0
+    1       R/W    Enhtimer_1_oneshot_mode_en                 1'h0
+    2       R/W    Enhtimer_2_oneshot_mode_en                 1'h0
+    3       R/W    Enhtimer_3_oneshot_mode_en                 1'h0
+    7:4     R/W    RSVD0                                       4'h0
+    8       R/WAC  Enhtimer_0_oneshot_go                      1'h0
+    9       R/WAC  Enhtimer_1_oneshot_go                      1'h0
+    10      R/WAC  Enhtimer_2_oneshot_go                      1'h0
+    11      R/WAC  Enhtimer_3_oneshot_go                      1'h0
+    31:12   R/W    RSVD1                                       20'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t Enhtimer_0_oneshot_mode_en: 1;
+        uint32_t Enhtimer_1_oneshot_mode_en: 1;
+        uint32_t Enhtimer_2_oneshot_mode_en: 1;
+        uint32_t Enhtimer_3_oneshot_mode_en: 1;
+        const  uint32_t RSVD0: 4;
+        uint32_t Enhtimer_0_oneshot_go: 1;
+        uint32_t Enhtimer_1_oneshot_go: 1;
+        uint32_t Enhtimer_2_oneshot_go: 1;
+        uint32_t Enhtimer_3_oneshot_go: 1;
+        const  uint32_t RSVD1: 20;
+    } b;
+} ENHTIMER_ONESHOT_CFG_TypeDef;
+
+/*============================================================================*
+ *                          ENHTIM Constants
+ *============================================================================*/
+/** \defgroup ENHTIM      ENHTIM
+  * \brief
+  * \{
+  */
+
+/** \defgroup ENHTIM_Exported_Constants ENHTIM Exported Constants
+  * \brief
+  * \{
+  */
+
+/**
+ * \defgroup  ENHTIM_Clock_Source ENHTIM Clock Source
+ * \{
+ * \ingroup   ENHTIM_Exported_Constants
+ */
+typedef enum
+{
+    ENHTIM_CLOCK_SOURCE_40M = 0x00,     //!< Clock source is 40MHz.
+    ENHTIM_CLOCK_SOURCE_PLL1 = 0x01,    //!< Clock source is PLL1.
+    ENHTIM_CLOCK_SOURCE_PLL2 = 0x02,    //!< Clock source is PLL2.
+    ENHTIM_CLOCK_SOURCE_32K = 0x04,     //!< Clock source is 32KHz.
+} ENHTIMClkSrc_TypdDef;
+
+#define IS_ENHTIM_CLK_SOURCE(src) (((src) == ENHTIM_CLOCK_SOURCE_40M) || \
+                                   ((src) == ENHTIM_CLOCK_SOURCE_32K)|| \\
+                                   ((src) == ENHTIM_CLOCK_SOURCE_PLL2)|| \\
+                                   ((src) == ENHTIM_CLOCK_SOURCE_PLL1)) //!< Check if the input parameter is valid.
+
+/** End of ENHTIM_Clock_Source
+  * \}
+  */
+
+/** End of ENHTIM_Exported_Constants
+  * \}
+  */
+
+/** End of ENHTIM
+  * \}
+  */
+
+/*============================================================================*
+ *                          ENHTIM TYPE/API Wrappers
+ *============================================================================*/
+/** \defgroup ENHTIM         ENHTIM
+  * \brief
+  * \{
+  */
+
+/** \defgroup ENHTIM_Exported_Constants ENHTIM Exported Constants
+  * \brief
+  * \{
+  */
+
+/**
+ * \defgroup    ENHTIM_API_Wrapper ENHTIM API Wrapper
+ * \{
+ * \ingroup     ENHTIM_Exported_Constants
+ */
+#define ENHTIM_SOURCE_CLOCK_40M     ENHTIM_CLOCK_SOURCE_40M     //!< The macro is a wrapper for ENHTIM_CLOCK_SOURCE_40M.
+#define ENHTIM_SOURCE_CLOCK_PLL1    ENHTIM_CLOCK_SOURCE_PLL1    //!< The macro is a wrapper for ENHTIM_CLOCK_SOURCE_PLL1.
+#define ENHTIM_SOURCE_CLOCK_PLL2    ENHTIM_CLOCK_SOURCE_PLL2    //!< The macro is a wrapper for ENHTIM_CLOCK_SOURCE_PLL2.
+
+/** End of ENHTIM_API_Wrapper
+  * \}
+  */
+
+/** End of ENHTIM_Exported_Constants
+  * \}
+  */
+
+/** End of ENHTIM
+  * \}
+  */
+
+#ifdef  __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* RTL_ENHTIM_DEF_H */
diff --git a/bee/drivers/timer/src/device/rtl87x2g/rtl_tim.c b/bee/drivers/timer/src/device/rtl87x2g/rtl_tim.c
new file mode 100644
index 00000000..c51ac4da
--- /dev/null
+++ b/bee/drivers/timer/src/device/rtl87x2g/rtl_tim.c
@@ -0,0 +1,298 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *                        Header Files
+ *============================================================================*/
+#include "rtl_tim.h"
+#include "rtl_rcc.h"
+
+/*============================================================================*
+ *                          Private Functions
+ *============================================================================*/
+#define TIM_0X08_TIMERENABLE      BIT0
+
+extern uint32_t TIM_GetTimerID(TIM_TypeDef *TIMx);
+
+#if TIM_SUPPORT_CLOCK_DEPEND
+extern void TIM_ConfigClkDepend(TIM_TypeDef *TIMx, uint8_t ClockDepend);
+#endif
+
+extern void TIM_SetHighLoadCount(TIM_TypeDef *TIMx, uint32_t TIM_PWM_High_Count);
+
+extern void TIM_PWMDeadzoneConfig(TIM_TypeDef *TIMx,
+                                  uint8_t PWM_Deazone_ClockSrc, uint8_t PWM_Deadzone_DIV,
+                                  uint8_t PWMDeadZone_En, uint32_t PWM_Deazone_Size,
+                                  uint8_t PWM_Stop_State_P, uint8_t PWM_Stop_State_N);
+
+/*============================================================================*
+ *                           Public Functions
+ *============================================================================*/
+/**
+  * \brief  Deinitialize the specified TIMx registers to their default reset values.
+  * \param  TIMx: Select the TIM peripheral. \ref TIMER_Declaration
+  * \return None
+  */
+void TIM_DeInit(TIM_TypeDef *TIMx)
+{
+    /* Check the parameters */
+    assert_param(IS_TIM_ALL_PERIPH(TIMx));
+
+    /* Disable timer IP clock and function */
+#ifdef IS_TIM_PERIPH
+    if (IS_TIM_PERIPH(TIMx))
+    {
+        RCC_PeriphClockCmd(APBPeriph_TIMER, APBPeriph_TIMER_CLOCK, DISABLE);
+    }
+#endif
+#ifdef IS_TIMB_PERIPH
+    if (IS_TIMB_PERIPH(TIMx))
+    {
+        RCC_PeriphClockCmd(APBPeriph_TIMERB, APBPeriph_TIMERB_CLOCK, DISABLE);
+    }
+#endif
+#ifdef IS_TIMC_PERIPH
+    if (IS_TIMC_PERIPH(TIMx))
+    {
+        RCC_PeriphClockCmd(APBPeriph_TIMERC, APBPeriph_TIMERC_CLOCK, DISABLE);
+    }
+#endif
+}
+
+/**
+  * \brief  Initialize the TIMx according to the specified parameters
+  *         in TIM_TimeBaseInitStruct.
+  * \param  TIMx: Select the TIM peripheral. \ref TIMER_Declaration
+  * \param  TIM_TimeBaseInitStruct: Pointer to a TIM_TimeBaseInitTypeDef structure which will be initialized.
+  * \return None
+  */
+void TIM_TimeBaseInit(TIM_TypeDef *TIMx, TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct)
+{
+    /* Check the parameters */
+    assert_param(IS_TIM_ALL_PERIPH(TIMx));
+    assert_param(IS_TIM_MODE(TIM_TimeBaseInitStruct->TIM_Mode));
+    assert_param(IS_TIM_PWM_DeadZone_En(TIM_TimeBaseInitStruct->PWMDeadZone_En));
+
+    TIM_ClkConfig(TIMx,
+                  TIM_TimeBaseInitStruct->TIM_ClockSrc,
+                  TIM_TimeBaseInitStruct->TIM_SOURCE_DIV);
+
+#if TIM_SUPPORT_CLOCK_DEPEND
+    TIM_ConfigClkDepend(TIMx, TIM_TimeBaseInitStruct->ClockDepend);
+#endif
+
+    /* set timer mode and mask interrupt */
+    TIMER_CONTROLREG_TypeDef timer_0x08 = {.d32 = TIMx->TIMER_CONTROLREG};
+    if (TIM_TimeBaseInitStruct->TIM_PWM_En == DISABLE)
+    {
+        timer_0x08.b.TimerMode = TIM_TimeBaseInitStruct->TIM_Mode;
+        timer_0x08.b.TimerInterruptMask = 0x1;
+        TIMx->TIMER_CONTROLREG = timer_0x08.d32;
+        /* set timer period */
+        TIMx->TIMER_LOADCOUNT = TIM_TimeBaseInitStruct->TIM_Period;
+    }
+    else
+    {
+        timer_0x08.b.TimerMode = TIM_TimeBaseInitStruct->TIM_Mode;
+        timer_0x08.b.TimerInterruptMask = 0x1;
+        timer_0x08.b.TIMER_PWM = 0x1;
+        TIMx->TIMER_CONTROLREG = timer_0x08.d32;
+
+        /* set pwm high count */
+        TIM_SetHighLoadCount(TIMx, TIM_TimeBaseInitStruct->TIM_PWM_High_Count);
+        /* set pwm low count */
+        TIMx->TIMER_LOADCOUNT = TIM_TimeBaseInitStruct->TIM_PWM_Low_Count;
+    }
+
+    /* Config PWM Deadzone */
+    TIM_PWMDeadzoneConfig(TIMx,
+                          TIM_TimeBaseInitStruct->PWM_Deazone_ClockSrc,
+                          TIM_TimeBaseInitStruct->PWM_Deadzone_DIV,
+                          TIM_TimeBaseInitStruct->PWMDeadZone_En,
+                          TIM_TimeBaseInitStruct->PWM_Deazone_Size,
+                          TIM_TimeBaseInitStruct->PWM_Stop_State_P,
+                          TIM_TimeBaseInitStruct->PWM_Stop_State_N);
+
+    /* Clear the IT status */
+    (void)TIMx->TIMER_EOI;
+}
+
+/**
+  * \brief  Fill each TIM_InitStruct member with its default value.
+  * \param  TIM_InitStruct : pointer to a TIM_InitTypeDef structure which will be initialized.
+  * \return None
+  */
+void TIM_StructInit(TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct)
+{
+    TIM_TimeBaseInitStruct->TIM_ClockSrc = TIM_CLOCK_SRC_40M;
+    TIM_TimeBaseInitStruct->TIM_Mode = TIM_Mode_UserDefine;
+    TIM_TimeBaseInitStruct->TIM_Period = 0xfff;
+#if TIM_SUPPORT_EVENT_DURATION
+    TIM_TimeBaseInitStruct->TIM_EventMode = false;
+    TIM_TimeBaseInitStruct->TIM_EventIndex = 1;
+    TIM_TimeBaseInitStruct->TIM_EventDuration = TIM_EventDuration_64us;
+#endif
+    TIM_TimeBaseInitStruct->TIM_SOURCE_DIV = TIM_CLOCK_DIVIDER_1;
+    TIM_TimeBaseInitStruct->TIM_SOURCE_DIV_En = DISABLE;
+    TIM_TimeBaseInitStruct->TIM_PWM_En = DISABLE;
+    TIM_TimeBaseInitStruct->PWM_Stop_State_P = PWM_STOP_AT_LOW;
+    TIM_TimeBaseInitStruct->PWM_Stop_State_N = PWM_STOP_AT_HIGH;
+    TIM_TimeBaseInitStruct->PWMDeadZone_En = DISABLE;
+    TIM_TimeBaseInitStruct->PWM_Deadzone_DIV = TIM_CLOCK_DIVIDER_1;
+    TIM_TimeBaseInitStruct->PWM_Deazone_ClockSrc = PWM_CK_32K_TIMER;
+    TIM_TimeBaseInitStruct->PWM_Deazone_Size = 10;
+}
+
+/**
+  * \brief  Enable or disable the specified TIMx peripheral.
+  * \param  TIMx: Select the TIM peripheral. \ref TIMER_Declaration
+  * \param  NewState: new state of the TIMx peripheral.
+  *   This parameter can be: ENABLE or DISABLE.
+  * \return None
+  */
+void TIM_Cmd(TIM_TypeDef *TIMx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_TIM_ALL_PERIPH(TIMx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    TIMER_CONTROLREG_TypeDef timer_0x08 = {.d32 = TIMx->TIMER_CONTROLREG};
+    timer_0x08.b.TimerEnable = NewState;
+    TIMx->TIMER_CONTROLREG = timer_0x08.d32;
+}
+
+/**
+  * \brief  Change the specified TIMx period value.
+  * \param  TIMx: Select the TIM peripheral. \ref TIMER_Declaration
+  * \return The new state of success or not  (SET or RESET).
+  */
+void TIM_ChangePeriod(TIM_TypeDef *TIMx, uint32_t period)
+{
+    /* Check the parameters */
+    assert_param(IS_TIM_ALL_PERIPH(TIMx));
+
+    TIMx->TIMER_LOADCOUNT = period;
+
+    return;
+}
+
+/**
+  * \brief  Enable or disable the specified TIMx interrupt.
+  * \param  TIMx: Select the TIM peripheral. \ref TIMER_Declaration
+  * \param  NewState: new state of the TIMx peripheral.
+  *   This parameter can be: ENABLE or DISABLE.
+  * \return None
+  */
+void TIM_INTConfig(TIM_TypeDef *TIMx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_TIM_ALL_PERIPH(TIMx));
+
+    /* Enable the Interrupt sources */
+    TIMER_CONTROLREG_TypeDef timer_0x08 = {.d32 = TIMx->TIMER_CONTROLREG};
+    timer_0x08.b.TimerInterruptMask = !NewState;
+    TIMx->TIMER_CONTROLREG = timer_0x08.d32;
+}
+
+/**
+  * \brief  Change the PWM frequency and duty cycle of the specified TIMx according to high_count and low_count.
+  * \param  TIMx: Select the TIM peripheral. \ref TIMER_Declaration
+  * \param  high_count: This parameter must range from 0x0000 to 0xFFFFFFFF
+  * \param  low_count: This parameter must range from 0x0000 to 0xFFFFFFFF
+  * \return None
+  */
+void TIM_PWMChangeFreqAndDuty(TIM_TypeDef *TIMx, uint32_t high_count, uint32_t low_count)
+{
+    /* Check the parameters */
+    assert_param(IS_TIM_ALL_PERIPH(TIMx));
+
+    /* Change PWM freq and duty */
+    TIMx->TIMER_LOADCOUNT = low_count;
+    TIM_SetHighLoadCount(TIMx, high_count);
+}
+
+/**
+ * \brief   Get the specified TIMx current value when timer is running.
+ * \param   TIMx: Select the TIM peripheral. \ref TIMER_Declaration
+ * \return  The counter value.
+ */
+uint32_t TIM_GetCurrentValue(TIM_TypeDef *TIMx)
+{
+    /* Check the parameters */
+    assert_param(IS_TIM_ALL_PERIPH(TIMx));
+
+    return TIMx->TIMER_CURRENTVALUE;
+}
+
+/**
+ * \brief   Get the specified TIMx interrupt status.
+ * \param   TIMx: Select the TIM peripheral. \ref TIMER_Declaration
+ * \return  The NewState of the timer interrupt status.
+ *          \arg SET: The TIM interrupt has occurred.
+ *          \arg RESET: The TIM interrupt has not occurred.
+ */
+ITStatus TIM_GetINTStatus(TIM_TypeDef *TIMx)
+{
+    /* Check the parameters */
+    assert_param(IS_TIM_ALL_PERIPH(TIMx));
+
+    if ((uint16_t)TIMx->TIMER_INTSTATUS != (uint16_t)RESET)
+    {
+        return SET;
+    }
+
+    return RESET;
+}
+
+/**
+ * \brief   Get the specified TIMx operation status.
+ * \param   TIMx: Select the TIM peripheral. \ref TIMER_Declaration
+ * \return  The NewState of the timer operation status.
+ *          \arg SET: The timer is running.
+ *          \arg RESET: The timer is not running.
+ */
+ITStatus TIM_GetOperationStatus(TIM_TypeDef *TIMx)
+{
+    /* Check the parameters */
+    assert_param(IS_TIM_ALL_PERIPH(TIMx));
+
+    if (TIMx->TIMER_CONTROLREG & TIM_0X08_TIMERENABLE)
+    {
+        return SET;
+    }
+    else
+    {
+        return RESET;
+    }
+}
+
+/**
+ * \brief  Get the specified TIMx elapsed value when timer is running.
+ * \param  TIMx: Select the TIM peripheral. \ref TIMER_Declaration
+ * \return The elapsed counter value.
+ */
+uint32_t TIM_GetElapsedValue(TIM_TypeDef *TIMx)
+{
+    /* Check the parameters */
+    assert_param(IS_TIM_ALL_PERIPH(TIMx));
+
+    return (TIMx->TIMER_LOADCOUNT - TIMx->TIMER_CURRENTVALUE);
+}
+
+/**
+ * \brief   Clear the specified TIMx interrupts.
+ * \param   TIMx: Select the TIM peripheral. \ref TIMER_Declaration
+ * \return  None.
+ */
+void TIM_ClearINT(TIM_TypeDef *TIMx)
+{
+    /* Check the parameters */
+    assert_param(IS_TIM_ALL_PERIPH(TIMx));
+
+    /* Clear the IT */
+    (void)TIMx->TIMER_EOI;
+}
+
diff --git a/bee/drivers/timer/src/device/rtl87x2g/rtl_tim.h b/bee/drivers/timer/src/device/rtl87x2g/rtl_tim.h
new file mode 100644
index 00000000..88848663
--- /dev/null
+++ b/bee/drivers/timer/src/device/rtl87x2g/rtl_tim.h
@@ -0,0 +1,667 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *               Define to prevent recursive inclusion
+ *============================================================================*/
+#ifndef RTL_TIM_H
+#define RTL_TIM_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*============================================================================*
+ *                        Header Files
+ *============================================================================*/
+#include "utils/rtl_utils.h"
+#include "rtl_tim_def.h"
+
+/** \defgroup TIM         TIM
+  * \brief
+  * \{
+  */
+/*============================================================================*
+ *                         Constants
+ *============================================================================*/
+/** \defgroup TIM_Exported_Constants TIM Exported Constants
+  * \brief
+  * \{
+  */
+
+/**
+ * \defgroup    PWM_DeadZone_Clock_Source PWM DeadZone Clock Source
+ * \{
+ * \ingroup     TIM_Exported_Constants
+ */
+typedef enum
+{
+    PWM_CK_5M_TIMER = 0x0,     //!< PWM DeadZone Clock Source is 5MHz.
+    PWM_CK_32K_TIMER = 0x1,    //!< PWM DeadZone Clock Source is 32KHz.
+} PWMDZClockSrc_TypeDef;
+
+#define IS_TIM_PWM_DZ_SOURCE(PERIPH)     (((PERIPH) == PWM_CK_5M_TIMER) || \
+                                          ((PERIPH) == PWM_CK_32K_TIMER)) //!< Check if the input parameter is valid.
+
+/** End of PWM_DeadZone_Clock_Source
+  * \}
+  */
+
+/**
+ * \defgroup    TIM_Mode TIM Mode
+ * \{
+ * \ingroup     TIM_Exported_Constants
+ */
+typedef enum
+{
+    TIM_Mode_FreeRun = 0x0,      //!< Select the TIM mode as Free-running mode. In free-running mode, the TIM counts down from 0xFFFFFFFF.
+    TIM_Mode_UserDefine = 0x1,   //!< Select the TIM mode as User-defined mode. In user-defined mode, the TIM counts down from the value set by TIM_Period in \ref TIM_TimeBaseInitTypeDef.
+} TIMMode_TypeDef;
+
+#define IS_TIM_MODE(mode) (((mode) == TIM_Mode_FreeRun) || \
+                           ((mode) == TIM_Mode_UserDefine)) //!< Check if the input parameter is valid.
+
+/** End of TIM_Mode
+  * \}
+  */
+
+/**
+ * \defgroup    PWM_DeadZone_Stop_State PWM DeadZone Stop State
+ * \{
+ * \ingroup     TIM_Exported_Constants
+ */
+typedef enum
+{
+    PWM_STOP_AT_LOW = 0x0,   //!< PWM DeadZone stop at low level.
+    PWM_STOP_AT_HIGH = 0x1,  //!< PWM DeadZone stop at high level.
+} PWMDZStopState_TypeDef;
+
+#define IS_PWM_STOP_STATE(STATE) (((STATE) == PWM_STOP_AT_LOW) || \
+                                  ((STATE) == PWM_STOP_AT_HIGH)) //!< Check if the input parameter is valid.
+
+/** End of PWM_DeadZone_Stop_State
+  * \}
+  */
+
+#if TIM_SUPPORT_EVENT_DURATION
+/**
+ * \brief       TIM_Event_Duration TIM Event Duration
+ *
+ * \ingroup     TIM_Exported_Constants
+ */
+typedef enum
+{
+    TIM_EventDuration_32us  = 0x00,   //!< The TIM event duration is 32us.
+    TIM_EventDuration_64us  = 0x01,   //!< The TIM event duration is 64us.
+    TIM_EventDuration_128us = 0x02,   //!< The TIM event duration is 128us.
+    TIM_EventDuration_256us = 0x03,   //!< The TIM event duration is 256us.
+} TIMEventDuration_TypeDef;
+
+#define IS_TIM_Event_DURATION(duration) (((duration) == TIM_EventDuration_32us) || \
+                                         ((duration) == TIM_EventDuration_64us) || \
+                                         ((duration) == TIM_EventDuration_128us) || \
+                                         ((duration) == TIM_EventDuration_256us)) //!< Check if the input parameter is valid.
+#endif
+
+/** End of TIM_Exported_Constants
+  * \}
+  */
+
+/*============================================================================*
+ *                         Types
+ *============================================================================*/
+/** \defgroup TIM_Exported_Types TIM Exported Types
+  * \brief
+  * \{
+  */
+
+/**
+ * \brief       TIM init structure definition.
+ *
+ * \ingroup     TIM_Exported_Types
+ */
+typedef struct
+{
+    TIMClockSrc_TypeDef TIM_ClockSrc;          /*!< Specify the clock source.
+                                                    This parameter can be a value of \ref TIM_Clock_Source.
+                                                    The calculation formula for timer clock is as follows:
+                                                    TIM clock = TIM_ClockSrc / TIM_SOURCE_DIV. */
+
+    TIMClockDiv_TypeDef TIM_SOURCE_DIV;        /*!< Specify the clock source div.
+                                                    This parameter can be a value of \ref TIM_Clock_Divider. */
+
+    FunctionalState TIM_SOURCE_DIV_En;         /*!< Enable or disable timer source clock divider.
+                                                    This parameter can be a value of DISABLE or ENABLE. */
+
+    TIMMode_TypeDef TIM_Mode;                  /*!< Specify the counter mode.
+                                                    This parameter can be a value of \ref TIM_Mode. */
+
+    FunctionalState TIM_PWM_En;                /*!< Enable or disable the PWM mode.
+                                                    This parameter can be a value of DISABLE or ENABLE. */
+
+    uint32_t TIM_Period;                       /*!< Specify the period value to be loaded into the active
+                                                    Auto-Reload Register at the next update event.
+                                                    This parameter must range from 0x0 to 0xFFFFFFFF. */
+
+    uint32_t TIM_PWM_High_Count;               /*!< Specify the PWM High Count.
+                                                    This parameter must range from 0x0 to 0xFFFFFFFF.
+                                                    PWM high period = (TIM_PWM_High_Count + 1) * TIM clock period.*/
+
+    uint32_t TIM_PWM_Low_Count;                /*!< Specify the PWM Low Count.
+                                                    This parameter must range from 0x0 to 0xFFFFFFFF.
+                                                    PWM low period = (TIM_PWM_Low_Count + 1) * TIM clock period. */
+
+#if TIM_SUPPORT_EVENT_DURATION
+    uint32_t TIM_EventMode;                    /*!< Specify the TIM event mode. */
+
+    uint32_t TIM_EventIndex;                   /*!< Specify the TIM event index. */
+
+    uint32_t TIM_EventDuration;                /*!< Specify the TIM event duration. */
+#endif
+
+#if TIM_SUPPORT_CLOCK_DEPEND
+    uint8_t  ClockDepend;                      /*!< Specify TIM Source depend.
+                                                    timer3 depend timer2, timer5 depend timer4, timer7 depend timer6.
+                                                    This parameter can be a value of ENABLE or DISABLE. */
+#endif
+
+    PWMDZClockSrc_TypeDef PWM_Deazone_ClockSrc;/*!< Specify the PWM deadzone clock source.
+                                                    The calculation formula for PWM deadzone clock is as follows:
+                                                    PWM deadzone clock = PWM_Deazone_ClockSrc / PWM_Deadzone_DIV.
+                                                    This parameter can be a value of \ref PWM_DeadZone_Clock_Source. */
+
+    TIMClockDiv_TypeDef PWM_Deadzone_DIV;      /*!< Specify the PWM deadzone clock divider.
+                                                    This parameter can be a value of \ref TIM_Clock_Divider. */
+
+    uint32_t PWM_Deazone_Size;                 /*!< Specify the PWM deadzone size.
+                                                    This parameter must range from 0x1 to 0xff.
+                                                    The calculation formula for deadzone time is as follows:
+                                                    deadzone time = (PWM_Deazone_Size) / deadzone clock. */
+
+    FunctionalState
+    PWMDeadZone_En;                            /*!< Enable or disable the PWM complementary output and deadzone.
+                                                    This parameter can be a value of ENABLE or DISABLE. */
+
+    PWMDZStopState_TypeDef PWM_Stop_State_P;   /*!< Specify the PWM P stop state.
+                                                    This parameter can be a value of \ref PWM_DeadZone_Stop_State. */
+
+    PWMDZStopState_TypeDef PWM_Stop_State_N;   /*!< Specify the PWM N stop state.
+                                                    This parameter can be a value of \ref PWM_DeadZone_Stop_State. */
+
+} TIM_TimeBaseInitTypeDef;
+
+/** End of TIM_Exported_Types
+  * \}
+  */
+
+/*============================================================================*
+ *                         Functions
+ *============================================================================*/
+/** \defgroup TIM_Exported_Functions TIM Exported Functions
+  * \brief
+  * \{
+  */
+
+/**
+ * \brief   Deinitialize the specified TIMx registers to their default reset values.
+ *
+ * \param[in] TIMx  Select the TIM peripheral. Refer to \ref TIM_Declaration.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void timer_demo(void)
+ * {
+ *     TIM_DeInit(TIM6);
+ * }
+ * \endcode
+ */
+void TIM_DeInit(TIM_TypeDef *TIMx);
+
+/**
+ * \brief   Initialize the specified TIMx according to the specified parameters
+ *          in TIM_TimeBaseInitStruct.
+ *
+ * \param[in] TIMx                    Select the TIM peripheral. Refer to \ref TIM_Declaration.
+ * \param[in] TIM_TimeBaseInitStruct  Pointer to a TIM_TimeBaseInitTypeDef structure which will be initialized.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_timer_init(void)
+ * {
+ *     RCC_PeriphClockCmd(APBPeriph_TIMER, APBPeriph_TIMER_CLOCK, ENABLE);
+ *
+ *     TIM_TimeBaseInitTypeDef TIM_InitStruct;
+ *     TIM_StructInit(&TIM_InitStruct);
+ *     TIM_InitStruct.TIM_PWM_En = DISABLE;
+ *     TIM_InitStruct.TIM_Period = 1000000 - 1 ;
+ *     TIM_InitStruct.TIM_Mode = TIM_Mode_UserDefine;
+ *     TIM_TimeBaseInit(TIM6, &TIM_InitStruct);
+ * }
+ * \endcode
+ */
+void TIM_TimeBaseInit(TIM_TypeDef *TIMx, TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct);
+
+/**
+ * \brief   Fill each TIM_InitStruct member with its default value.
+ *
+ * \note The default settings for the TIM_InitStruct member are shown in the following table:
+ *       | TIM_InitStruct member        | Default value                        |
+ *       |:----------------------------:|:------------------------------------:|
+ *       | TIM_ClockSrc                 | \ref TIM_CLOCK_SRC_40M               |
+ *       | TIM_Mode                     | \ref TIM_Mode_UserDefine             |
+ *       | TIM_Period                   | 0xfff                                |
+ *       | TIM_SOURCE_DIV               | \ref TIM_CLOCK_DIVIDER_1             |
+ *       | TIM_SOURCE_DIV_En            | DISABLE                              |
+ *       | TIM_PWM_En                   | DISABLE                              |
+ *       | PWM_Stop_State_P             | \ref PWM_STOP_AT_LOW                 |
+ *       | PWM_Stop_State_N             | \ref PWM_STOP_AT_HIGH                |
+ *       | PWMDeadZone_En               | DISABLE                              |
+ *       | PWM_Deadzone_DIV             | \ref TIM_CLOCK_DIVIDER_1             |
+ *       | PWM_Deazone_ClockSrc         | \ref PWM_CK_32K_TIMER                |
+ *       | PWM_Deazone_Size             | 10                                   |
+ *
+ * \param[in] TIM_TimeBaseInitStruct  Pointer to a TIM_TimeBaseInitTypeDef structure which will be initialized.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_timer_init(void)
+ * {
+ *     RCC_PeriphClockCmd(APBPeriph_TIMER, APBPeriph_TIMER_CLOCK, ENABLE);
+ *
+ *     TIM_TimeBaseInitTypeDef TIM_InitStruct;
+ *     TIM_StructInit(&TIM_InitStruct);
+ *     TIM_InitStruct.TIM_PWM_En = DISABLE;
+ *     TIM_InitStruct.TIM_Period = 1000000 - 1;
+ *     TIM_InitStruct.TIM_Mode = TIM_Mode_UserDefine;
+ *     TIM_TimeBaseInit(TIM6, &TIM_InitStruct);
+ * }
+ * \endcode
+ */
+void TIM_StructInit(TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct);
+
+/**
+ * \brief   Enable or disable the specified TIMx peripheral.
+ *
+ * \param[in] TIMx      Select the TIM peripheral. Refer to \ref TIM_Declaration.
+ * \param[in] NewState  New state of the TIMx peripheral.
+ *                      This parameter can be one of the following values:
+ *                      - ENABLE: Count start.
+ *                      - DISABLE: Count stop and clear count value.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_timer_init(void)
+ * {
+ *     RCC_PeriphClockCmd(APBPeriph_TIMER, APBPeriph_TIMER_CLOCK, ENABLE);
+ *
+ *     TIM_TimeBaseInitTypeDef TIM_InitStruct;
+ *     TIM_StructInit(&TIM_InitStruct);
+ *     TIM_InitStruct.TIM_PWM_En = DISABLE;
+ *     TIM_InitStruct.TIM_Period = 1000000 - 1;
+ *     TIM_InitStruct.TIM_Mode = TIM_Mode_UserDefine;
+ *     TIM_TimeBaseInit(TIM6, &TIM_InitStruct);
+ *     TIM_Cmd(TIM6, ENABLE);
+ * }
+ * \endcode
+ */
+void TIM_Cmd(TIM_TypeDef *TIMx, FunctionalState NewState);
+
+/**
+ * \brief     Enable or disable the specified TIMx interrupt.
+ *
+ * \param[in] TIMx      Select the TIM peripheral. Refer to \ref TIM_Declaration.
+ * \param[in] NewState  New state of the TIMx interrupt.
+ *                      This parameter can be one of the following values:
+ *                      - ENABLE: Enable the timeout interrupt.
+ *                      - DISABLE: Disable the timeout interrupt.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_timer_init(void)
+ * {
+ *     RCC_PeriphClockCmd(APBPeriph_TIMER, APBPeriph_TIMER_CLOCK, ENABLE);
+ *
+ *     TIM_TimeBaseInitTypeDef TIM_InitStruct;
+ *     TIM_StructInit(&TIM_InitStruct);
+ *     TIM_InitStruct.TIM_PWM_En = DISABLE;
+ *     TIM_InitStruct.TIM_Period = 1000000 - 1;
+ *     TIM_InitStruct.TIM_Mode = TIM_Mode_UserDefine;
+ *     TIM_TimeBaseInit(TIM6, &TIM_InitStruct);
+ *     TIM_ClearINT(TIM6);
+ *     TIM_INTConfig(TIM6, ENABLE);
+ * }
+ * \endcode
+ */
+void TIM_INTConfig(TIM_TypeDef *TIMx, FunctionalState NewState);
+
+/**
+ * \brief     Change the specified TIMx period value.
+ *
+ * \param[in] TIMx    Select the TIM peripheral. Refer to \ref TIM_Declaration.
+ * \param[in] period  Period value to be changed. This parameter must range from 0x0 to 0xFFFFFFFF.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void timer_demo(void)
+ * {
+ *     uint32_t new_period = 1000000 - 1;
+ *     TIM_Cmd(TIM6, DISABLE);
+ *     TIM_ChangePeriod(TIM6, new_period);
+ * }
+ * \endcode
+ */
+void TIM_ChangePeriod(TIM_TypeDef *TIMx, uint32_t period);
+
+/**
+ * \brief   Change the PWM frequency and duty cycle of the specified TIMx according to high_count and low_count.
+ *
+ * \param[in] TIMx        Select the TIM peripheral. Refer to \ref TIM_Declaration.
+ * \param[in] high_count  This parameter must range from 0~0xFFFFFFFF.
+ * \param[in] low_count   This parameter must range from be 0~0xFFFFFFFF.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * #define TIM_DEMO TIMB_6
+ *
+ * void timer_demo(void)
+ * {
+ *     uint32_t high_count = 1000000 - 1;
+ *     uint32_t low_count = 1000000 - 1;
+ *     TIM_Cmd(TIM_DEMO, DISABLE);
+ *     TIM_ChangePeriod(TIM_DEMO, high_count, low_count);
+ * }
+ * \endcode
+ */
+void TIM_PWMChangeFreqAndDuty(TIM_TypeDef *TIMx, uint32_t high_count, uint32_t low_count);
+
+/**
+ * \brief   Get the specified TIMx current value when timer is running.
+ *
+ * \param[in] TIMx  Select the TIM peripheral. Refer to \ref TIM_Declaration.
+ *
+ * \return  The current counter value.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void timer_demo(void)
+ * {
+ *     uint32_t cur_value = TIM_GetCurrentValue(TIM6);
+ * }
+ * \endcode
+ */
+uint32_t TIM_GetCurrentValue(TIM_TypeDef *TIMx);
+
+/**
+ * \brief   Get the specified TIMx interrupt status.
+ *
+ * \param[in] TIMx  Select the TIM peripheral. Refer to \ref TIM_Declaration.
+ *
+ * \return  The NewState of the timer interrupt status.
+ *          - SET: The TIM interrupt has occurred.
+ *          - RESET: The TIM interrupt has not occurred.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void timer_demo(void)
+ * {
+ *     ITStatus int_status = TIM_GetINTStatus(TIM6);
+ * }
+ * \endcode
+ */
+ITStatus TIM_GetINTStatus(TIM_TypeDef *TIMx);
+
+/**
+ * \brief   Get the specified TIMx operation status.
+ *
+ * \param[in] TIMx  Select the TIM peripheral. Refer to \ref TIM_Declaration.
+ *
+ * \return  The NewState of the timer operation status.
+ *          - SET: The timer is running.
+ *          - RESET: The timer is not running.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void timer_demo(void)
+ * {
+ *     ITStatus intstatus = TIM_GetOperationStatus(TIM6);
+ * }
+ * \endcode
+ */
+ITStatus TIM_GetOperationStatus(TIM_TypeDef *TIMx);
+
+/**
+ * \brief Get the specified TIMx elapsed value when timer is running.
+ *
+ * \param[in] TIMx  Select the TIM peripheral. Refer to \ref TIM_Declaration.
+ *
+ * \return The elapsed counter value.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void timer_demo(void)
+ * {
+ *     uint32_t value = TIM_GetElapsedValue(TIM6);
+ * }
+ * \endcode
+ */
+uint32_t TIM_GetElapsedValue(TIM_TypeDef *TIMx);
+
+/**
+ * \brief   Clear the specified TIMx interrupt.
+ *
+ * \param[in] TIMx  Select the TIM peripheral. Refer to \ref TIM_Declaration.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void timer_demo(void)
+ * {
+ *     TIM_ClearINT(TIM6);
+ * }
+ * \endcode
+ */
+void TIM_ClearINT(TIM_TypeDef *TIMx);
+
+/**
+ * \brief   Enable or disable the emergency stop for PWM complementary output function.
+ *
+ * \param[in] PWMx      Select the PWM peripheral. Refer to \ref PWM_Declaration.
+ * \param[in] NewState  NewState of complementary output.
+ *                      \arg ENABLE: Enable the emergency stop output function.
+ *                      \arg DISABLE: Disable the emergency stop output function.
+ *
+ * \note    When using PWM functions, it is crucial to pay attention to the corresponding relationships:
+ *          PWM2 corresponds to TIM2, and PWM3 corresponds to TIM3.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void pwm_demo(void)
+ * {
+ *    board_pwm_init();
+ *    driver_pwm_init();
+ *    TIM_PWMComplOutputEMCmd(PWM2,ENABLE);
+ * }
+ * \endcode
+ */
+void TIM_PWMComplOutputEMCmd(PWM_TypeDef *PWMx, FunctionalState NewState);
+
+/**
+ * \brief   Enable or disable deadzone bypass for the PWM complementary output function.
+ *          If enabled, PWM_P will become the inverse of PWM_N.
+ *
+ * \param[in] PWMx      Select the PWM peripheral. Refer to \ref PWM_Declaration.
+ * \param[in] NewState  NewState of the PWMx peripheral.
+ *                      \arg ENABLE: Enable bypass deadzone function.
+ *                      \arg DISABLE: Disable bypass deadzone function.
+ *
+ * \note    When using PWM functions, it is crucial to pay attention to the corresponding relationships:
+ *          PWM2 corresponds to TIM2, and PWM3 corresponds to TIM3.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_pwm_init(void)
+ * {
+ *     RCC_PeriphClockCmd(APBPeriph_TIMER, APBPeriph_TIMER_CLOCK, ENABLE);
+ *
+ *     TIM_TimeBaseInitTypeDef TIM_InitStruct;
+ *     TIM_StructInit(&TIM_InitStruct);
+ *     TIM_InitStruct.TIM_Mode             = TIM_Mode_UserDefine;
+ *     TIM_InitStruct.TIM_PWM_En           = ENABLE;
+ *     TIM_InitStruct.TIM_PWM_High_Count   = PWM_HIGH_COUNT;
+ *     TIM_InitStruct.TIM_PWM_Low_Count    = PWM_LOW_COUNT;
+ *     TIM_InitStruct.PWM_Stop_State_P     = PWM_STOP_AT_HIGH;
+ *     TIM_InitStruct.PWM_Stop_State_N     = PWM_STOP_AT_LOW;
+ *     TIM_InitStruct.PWMDeadZone_En       = ENABLE;  //enable to use pwn p/n output
+ *     TIM_InitStruct.PWM_Deazone_Size     = 255;
+ *     TIM_TimeBaseInit(PWM2, &TIM_InitStruct);
+ *
+ *     TIM_Cmd(PWM2, ENABLE);
+ *     TIM_PWMDZBypassCmd(PWM2, ENABLE);
+ * }
+ * \endcode
+ */
+void TIM_PWMDZBypassCmd(PWM_TypeDef *PWMx, FunctionalState NewState);
+
+/**
+ * \brief   Change the clock source for the PWM deadzone time.
+ *
+ * \param[in] PWMx                  Select the PWM peripheral. Refer to \ref PWM_Declaration.
+ * \param[in] PWM_Deazone_ClockSrc  Specify the PWM deadzone clock source. Refer to \ref PWM_DeadZone_Clock_Source.
+ *
+ * \note    When using PWM functions, it is crucial to pay attention to the corresponding relationships:
+ *          PWM2 corresponds to TIM2, and PWM3 corresponds to TIM3.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_pwm_init(void)
+ * {
+ *     RCC_PeriphClockCmd(APBPeriph_TIMER, APBPeriph_TIMER_CLOCK, ENABLE);
+ *     //Open 32k clock source.
+ *     RCC_ClockSrc5MCmd();
+ *
+ *     TIM_TimeBaseInitTypeDef TIM_InitStruct;
+ *
+ *     TIM_StructInit(&TIM_InitStruct);
+ *     TIM_InitStruct.TIM_Mode             = TIM_Mode_UserDefine;
+ *     TIM_InitStruct.TIM_PWM_En           = ENABLE;
+ *     TIM_InitStruct.TIM_PWM_High_Count   = PWM_HIGH_COUNT;
+ *     TIM_InitStruct.TIM_PWM_Low_Count    = PWM_LOW_COUNT;
+ *     TIM_InitStruct.PWM_Stop_State_P     = PWM_STOP_AT_HIGH;
+ *     TIM_InitStruct.PWM_Stop_State_N     = PWM_STOP_AT_LOW;
+ *     TIM_InitStruct.PWMDeadZone_En       = ENABLE;  //enable to use pwn p/n output
+ *     TIM_InitStruct.PWM_Deazone_Size     = PWM_DEAD_ZONE_SIZE;
+ *     TIM_TimeBaseInit(TIM2, &TIM_InitStruct);
+ *
+ *     //Use 32k clock source.
+ *     TIM_PWMChangeDZClockSrc(TIM2, PWM_CK_32K_TIMER);
+ *
+ *     TIM_Cmd(TIM2, ENABLE);
+ * }
+ * \endcode
+ */
+void TIM_PWMChangeDZClockSrc(PWM_TypeDef *PWMx, PWMDZClockSrc_TypeDef PWM_Deazone_ClockSrc);
+
+/**
+ * \brief  Configure the specified TIMx clock.
+ *
+ * \param[in] TIMx      Select the TIM peripheral. Refer to \ref TIM_Declaration.
+ * \param[in] ClockSrc  Specify the TIM clock source. Refer to \ref TIM_Clock_Source.
+ * \param[in] ClockDiv  Specify the TIM clock divider. Refer to \ref TIM_Clock_Divider.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void timer_demo(void)
+ * {
+ *     TIM_ClkConfig(TIM6, TIM_CLOCK_SRC_40M, TIM_CLOCK_DIVIDER_1)
+ * }
+ * \endcode
+ */
+void TIM_ClkConfig(TIM_TypeDef *TIMx, TIMClockSrc_TypeDef ClockSrc,
+                   TIMClockDiv_TypeDef ClockDiv);
+
+/**
+ * \brief  Get the specified TIMx clock configuration.
+ *
+ * \param[in]  TIMx      Select the TIM peripheral. Refer to \ref TIM_Declaration.
+ * \param[out] ClockSrc  The TIM clock source. Refer to \ref TIM_Clock_Source.
+ * \param[out] ClockDiv  The TIM clock divider. Refer to \ref TIM_Clock_Divider.
+ *
+ * \return The status of get clock.
+ *         - true: TIM clock is set correctly.
+ *         - false: The TIM clock is set incorrectly.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void timer_demo(void)
+ * {
+ *     TIMClockSrc_TypeDef clock_src;
+ *     TIMClockDiv_TypeDef clock_div;
+ *     TIM_ClkGet(TIM6, &clock_src, &clock_div);
+ * }
+ * \endcode
+ */
+bool TIM_ClkGet(TIM_TypeDef *TIMx, TIMClockSrc_TypeDef *ClockSrc, TIMClockDiv_TypeDef *ClockDiv);
+
+#if RCC_SUPPORT_TIMSOURCECONFIG_API
+/**
+ * rtl876x_rcc.h
+ *
+ * \brief     Select the specified divider and source for the timer clock.
+ *
+ * \param[in] clocklevel   Timer clock divider.
+ *                         This parameter can be one of the following values:
+ *                         \arg TIM2TO7_CLOCK_DIV_x: TIM2TO7 clock divider, where x can be 1 ~ 4, 6, 8, 16.
+ * \param[in] clocksource  Timer clock Source.
+ *                         This parameter can be one of the following values:
+ *                         \arg TIM_CLOCK_SOURCE_SYSTEM_CLOCK: Select timer clock source of system clock.
+ *                         \arg TIM_CLOCK_SOURCE_40MHZ: Select timer clock source of 40MHz.
+ *                         \arg TIM_CLOCK_SOURCE_PLL: Select timer clock source of PLL.
+ * \param[in] NewState     New state of the specified RCC Clock Source.
+ *                         This parameter can be one of the following values:
+ *                         - ENABLE: Enable the specified RCC Clock Source.
+ *                         - DISABLE: Disable the specified RCC Clock Source.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_xx_init(void)
+ * {
+ *     TIM_SourceConfig(TIM2TO7_CLOCK_DIV_1, TIM_CLOCK_SOURCE_40MHZ, ENABLE);
+ * }
+ * \endcode
+ */
+void TIM_SourceConfig(uint16_t clocklevel, uint16_t clocksource, FunctionalState NewState);
+#endif
+
+/** End of TIM_Exported_Functions
+  * \}
+  */
+
+/** End of TIM
+  * \}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*_RTL_TIM_H_*/
diff --git a/bee/drivers/timer/src/device/rtl87x2g/rtl_tim_def.h b/bee/drivers/timer/src/device/rtl87x2g/rtl_tim_def.h
new file mode 100644
index 00000000..b16caf94
--- /dev/null
+++ b/bee/drivers/timer/src/device/rtl87x2g/rtl_tim_def.h
@@ -0,0 +1,444 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef RTL_TIM_DEF_H
+#define RTL_TIM_DEF_H
+
+#include "utils/rtl_utils.h"
+#include "address_map.h"
+
+#ifdef  __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/*============================================================================*
+ *                          TIM Defines
+ *============================================================================*/
+/** \defgroup TIM         TIM
+  * \brief
+  * \{
+  */
+
+/** \defgroup TIM_Exported_Constants TIM Exported Constants
+  * \brief
+  * \{
+  */
+
+/**
+ * \defgroup TIM_Defines TIM Defines
+ * \brief The following macro represents whether TIM supports this feature.
+ * \{
+ * \ingroup  TIM_Exported_Constants
+ */
+
+#define CHIP_PWM_DEAD_ZONE_NUM         (2) //!< The chip supports 2 PWM deadzone.
+#define TIM_SUPPORT_CLOCK_DEPEND       (0) //!< The function is not supported.
+#define TIM_SUPPORT_EVENT_DURATION     (0) //!< The function is not supported.
+#define TIM_SUPPORT_SOURCECONFIG_API   (0) //!< The function is not supported.
+
+/** End of TIM_Defines
+  * \}
+  */
+
+/** End of TIM_Exported_Constants
+  * \}
+  */
+
+/** End of TIM
+  * \}
+  */
+
+/*============================================================================*
+ *                         TIMER Registers Memory Map
+ *============================================================================*/
+typedef struct
+{
+    __IO uint32_t TIMER_LOADCOUNT;        /*!< 0x00 */
+    __I  uint32_t TIMER_CURRENTVALUE;     /*!< 0x04 */
+    __IO uint32_t TIMER_CONTROLREG;       /*!< 0x08 */
+    __I  uint32_t TIMER_EOI;              /*!< 0x0C */
+    __I  uint32_t TIMER_INTSTATUS;        /*!< 0x10 */
+} TIM_TypeDef;
+
+typedef struct
+{
+    __IO uint32_t TIMER_PWM_WRAP_CFG;    /*!< 0x33C */
+} PWM_TypeDef;
+
+/*============================================================================*
+ *                         TIMER Declaration
+ *============================================================================*/
+
+#define TIMER_0_REG_BASE          (TIMER_REG_BASE + 0x0000)
+#define TIMER_1_REG_BASE          (TIMER_REG_BASE + 0x0014)
+#define TIMER_2_REG_BASE          (TIMER_REG_BASE + 0x0028)
+#define TIMER_3_REG_BASE          (TIMER_REG_BASE + 0x003c)
+#define TIMER_4_REG_BASE          (TIMER_REG_BASE + 0x0050)
+#define TIMER_5_REG_BASE          (TIMER_REG_BASE + 0x0064)
+#define TIMER_6_REG_BASE          (TIMER_REG_BASE + 0x0078)
+#define TIMER_7_REG_BASE          (TIMER_REG_BASE + 0x008c)
+
+/** \defgroup TIM         TIM
+  * \brief
+  * \{
+  */
+
+/** \defgroup TIM_Exported_Constants TIM Exported Constants
+  * \brief
+  * \{
+  */
+
+/** \defgroup TIM_Declaration TIM Declaration
+  * \{
+  * \ingroup  TIM_Exported_Constants
+  */
+#define TIM0        ((TIM_TypeDef *) TIMER_0_REG_BASE)   //!< TIM0 base address.
+#define TIM1        ((TIM_TypeDef *) TIMER_1_REG_BASE)   //!< TIM1 base address.
+#define TIM2        ((TIM_TypeDef *) TIMER_2_REG_BASE)   //!< TIM2 base address.
+#define TIM3        ((TIM_TypeDef *) TIMER_3_REG_BASE)   //!< TIM3 base address.
+#define TIM4        ((TIM_TypeDef *) TIMER_4_REG_BASE)   //!< TIM4 base address.
+#define TIM5        ((TIM_TypeDef *) TIMER_5_REG_BASE)   //!< TIM5 base address.
+#define TIM6        ((TIM_TypeDef *) TIMER_6_REG_BASE)   //!< TIM6 base address.
+#define TIM7        ((TIM_TypeDef *) TIMER_7_REG_BASE)   //!< TIM7 base address.
+
+#define IS_TIM_PERIPH(PERIPH)     (((PERIPH) == TIM0) || \
+                                   ((PERIPH) == TIM1) || \
+                                   ((PERIPH) == TIM2) || \
+                                   ((PERIPH) == TIM3) || \
+                                   ((PERIPH) == TIM4) || \
+                                   ((PERIPH) == TIM5) || \
+                                   ((PERIPH) == TIM6) || \
+                                   ((PERIPH) == TIM7))    //!< Check if the input parameter is valid.
+#define IS_TIM_ALL_PERIPH(PERIPH) (IS_TIM_PERIPH(PERIPH)) //!< Check if the input parameter is valid.
+
+/** End of TIM_Declaration
+  * \}
+  */
+
+/* Reasons for the definition of PWMx
+   PWM2 and PWM3 share the same register(TIMER_PWM_WRAP_CFG: 0x4000233CUL). When the
+   register is 32 bits, PWM2 and PWM3 cannot be distinguished in the function. When
+   the register is 16 bits, the function of PWM2 and PWM3 can be opened separately,
+   but cannot be opened simultaneously. So the definition of PWM2 and PWM3 is just to
+   make a distinction.
+*/
+
+/** \defgroup PWM_Declaration PWM Declaration
+  * \{
+  * \ingroup  TIM_Exported_Constants
+  */
+
+#define PWM2                      ((PWM_TypeDef *) 1)   //!< PWM2 base address.
+#define PWM3                      ((PWM_TypeDef *) 0)   //!< PWM3 base address.
+
+#define IS_PWM_ALL_PERIPH(PERIPH) (((PERIPH) == PWM2)  || \
+                                   ((PERIPH) == PWM3)) //!< Check if the input parameter is valid.
+
+/** End of PWM_Declaration
+  * \}
+  */
+
+/** End of TIM_Exported_Constants
+  * \}
+  */
+
+/** End of TIM
+  * \}
+  */
+
+/*============================================================================*
+ *                         TIMER Private Defines
+ *============================================================================*/
+#define TIMER0_LOAD_COUNT2       *((volatile uint32_t *)(TIMER_REG_BASE+0xB0))
+#define TIMER1_LOAD_COUNT2       *((volatile uint32_t *)(TIMER_REG_BASE+0xB4))
+#define TIMER2_LOAD_COUNT2       *((volatile uint32_t *)(TIMER_REG_BASE+0xB8))
+#define TIMER3_LOAD_COUNT2       *((volatile uint32_t *)(TIMER_REG_BASE+0xBC))
+#define TIMER4_LOAD_COUNT2       *((volatile uint32_t *)(TIMER_REG_BASE+0xC0))
+#define TIMER5_LOAD_COUNT2       *((volatile uint32_t *)(TIMER_REG_BASE+0xC4))
+#define TIMER6_LOAD_COUNT2       *((volatile uint32_t *)(TIMER_REG_BASE+0xC8))
+#define TIMER7_LOAD_COUNT2       *((volatile uint32_t *)(TIMER_REG_BASE+0xCC))
+
+#define TIMER_CLK_SOURCE_REG_328 *((volatile uint32_t *)0x40002328UL)
+
+#define TIMER_PWM_CLK_CR         *((volatile uint32_t *)0x4000232CUL)
+#define TIMER_PWM_CR             *((volatile uint32_t *)0x4000233CUL)
+#define TIM_GetCurrentControl(TIMx)      (((TIM_TypeDef *)(TIMx))->TIMER_CONTROLREG)
+#define TIM_GetCurrentLoadCnt(TIMx)      (((TIM_TypeDef *)(TIMx))->TIMER_LOADCOUNT)
+
+
+/*============================================================================*
+ *                         TIM Private Types
+ *============================================================================*/
+typedef struct
+{
+    uint32_t tim_reg[29];
+} TIMStoreReg_Typedef;
+
+/*============================================================================*
+ *                         TIMER Registers and Field Descriptions
+ *============================================================================*/
+/* 0x00
+   31:0    R/W    TimerNLoadCount                     0x0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t TimerNLoadCount: 32;
+    } b;
+} TIMER_LOADCOUNT_TypeDef;
+
+
+
+/* 0x04
+   31:0    R      TimerNCurrentValue                  0x0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        const uint32_t TimerNCurrentValue: 32;
+    } b;
+} TIMER_CURRENTVALUE_TypeDef;
+
+
+
+/* 0x08
+   0       R/W    TimerEnable                         0x0
+   1       R/W    TimerMode                           0x0
+   2       R/W    TimerInterruptMask                  0x0
+   3       R/W    TIMER_PWM                           0x0
+   31:4    R      Reserved                            0x0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t TimerEnable: 1;
+        uint32_t TimerMode: 1;
+        uint32_t TimerInterruptMask: 1;
+        uint32_t TIMER_PWM: 1;
+        const uint32_t reserved_0: 28;
+    } b;
+} TIMER_CONTROLREG_TypeDef;
+
+
+
+/* 0x0C
+   0       R      TimerNEndofInterrupt                0x0
+   31:1    R      Reserved                            0x0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        const uint32_t TimerNEndofInterrupt: 1;
+        const uint32_t reserved_0: 31;
+    } b;
+} TIMER_EOI_TypeDef;
+
+
+
+/* 0x10
+   0       R      TimerNInterruptStatus               0x0
+   31:1    R      Reserved                            0x0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        const uint32_t TimerNInterruptStatus: 1;
+        const uint32_t reserved_0: 31;
+    } b;
+} TIMER_INTSTATUS_TypeDef;
+
+
+
+/* 0x33C
+   7:0     R/W    timer_pwm_2_dead_zone_size        8'h0
+   8       R/W    timer_pwm_2_emg_stop              1'h0
+   9       R/W    timer_pwm_2_stop_state[0]         1'h0
+   10      R/W    timer_pwm_2_stop_state[1]         1'h0
+   11      R/W    timer_pwm_2_dummy_b11             1'h0
+   12      R/W    timer_pwm_2_dead_zone_en          1'h0
+   13      R/W    timer_pwm_2_pwm_pn_invserse_sel   1'h0
+   14      R/W    timer_pwm_2_dummy_b14             1'h0
+   15      R/W    timer_pwm_2_dummy_b15             1'h0
+   23:16   R/W    timer_pwm_3_dead_zone_size        8'h0
+   24      R/W    timer_pwm_3_emg_stop              1'h0
+   25      R/W    timer_pwm_3_stop_state[0]         1'h0
+   26      R/W    timer_pwm_3_stop_state[1]         1'h0
+   27      R/W    timer_pwm_3_dummy_b11             1'h0
+   28      R/W    timer_pwm_3_dead_zone_en          1'h0
+   29      R/W    timer_pwm_3_pwm_pn_invserse_sel   1'h0
+   30      R/W    timer_pwm_3_dummy_b14             1'h0
+   31      R/W    timer_pwm_3_dummy_b15             1'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t timer_pwm_2_dead_zone_size: 8;
+        uint32_t timer_pwm_2_emg_stop: 1;
+        uint32_t timer_pwm_2_stop_state_0: 1;
+        uint32_t timer_pwm_2_stop_state_1: 1;
+        uint32_t timer_pwm_2_dummy_b11: 1;
+        uint32_t timer_pwm_2_dead_zone_en: 1;
+        uint32_t timer_pwm_2_pwm_pn_invserse_sel: 1;
+        uint32_t timer_pwm_2_dummy_b14: 1;
+        uint32_t timer_pwm_2_dummy_b15: 1;
+        uint32_t timer_pwm_3_dead_zone_size: 8;
+        uint32_t timer_pwm_3_emg_stop: 1;
+        uint32_t timer_pwm_3_stop_state_0: 1;
+        uint32_t timer_pwm_3_stop_state_1: 1;
+        uint32_t timer_pwm_3_dummy_b11: 1;
+        uint32_t timer_pwm_3_dead_zone_en: 1;
+        uint32_t timer_pwm_3_pwm_pn_invserse_sel: 1;
+        uint32_t timer_pwm_3_dummy_b14: 1;
+        uint32_t timer_pwm_3_dummy_b15: 1;
+    } b;
+} TIMER_PWM_WRAP_CFG_TypeDef;
+
+/* ================================================================================ */
+/* ================                   TIMER  Constants             ================ */
+/* ================================================================================ */
+/** \defgroup TIM         TIM
+  * \brief
+  * \{
+  */
+
+/** \defgroup TIM_Exported_Constants TIM Exported Constants
+  * \brief
+  * \{
+  */
+
+/**
+ * \defgroup    TIM_Clock_Source TIM Clock Source
+ * \{
+ * \ingroup     TIM_Exported_Constants
+ */
+typedef enum
+{
+    TIM_CLOCK_SRC_40M = 0x0,    //!< The TIM clock source is 40MHz.
+    TIM_CLOCK_SRC_32K = 0x1,    //!< The TIM clock source is 32KHz.
+    TIM_CLOCK_SRC_PLL1 = 0x2,   //!< The TIM clock source is PLL1.
+    TIM_CLOCK_SRC_PLL2 = 0x3,   //!< The TIM clock source is PLL2.
+} TIMClockSrc_TypeDef;
+
+#define IS_TIM_CLK_SOURCE(PERIPH)     (((PERIPH) == TIM_CLOCK_SRC_40M ) || \
+                                       ((PERIPH) == TIM_CLOCK_SRC_32K ) || \
+                                       ((PERIPH) == TIM_CLOCK_SRC_PLL1) || \
+                                       ((PERIPH) == TIM_CLOCK_SRC_PLL2)) //!< Check if the input parameter is valid.
+
+/** End of TIM_Clock_Source
+  * \}
+  */
+
+/**
+ * \defgroup    TIM_Clock_Divider TIM Clock Divider
+ * \{
+ * \ingroup     TIM_Exported_Constants
+ */
+typedef enum
+{
+    TIM_CLOCK_DIVIDER_1 = 0x0,     //!< The clock divider is 1.
+    TIM_CLOCK_DIVIDER_2 = 0x1,     //!< The clock divider is 2.
+    TIM_CLOCK_DIVIDER_4 = 0x2,     //!< The clock divider is 4.
+    TIM_CLOCK_DIVIDER_8 = 0x3,     //!< The clock divider is 8.
+    TIM_CLOCK_DIVIDER_16 = 0x4,    //!< The clock divider is 16.
+    TIM_CLOCK_DIVIDER_32 = 0x5,    //!< The clock divider is 32.
+    TIM_CLOCK_DIVIDER_40 = 0x6,    //!< The clock divider is 40.
+    TIM_CLOCK_DIVIDER_64 = 0x7,    //!< The clock divider is 64.
+} TIMClockDiv_TypeDef;
+
+#define IS_TIM_CLK_DIV(DIV) (((DIV) == TIM_CLOCK_DIVIDER_1) || \
+                             ((DIV) == TIM_CLOCK_DIVIDER_2) || \
+                             ((DIV) == TIM_CLOCK_DIVIDER_4) || \
+                             ((DIV) == TIM_CLOCK_DIVIDER_8) || \
+                             ((DIV) == TIM_CLOCK_DIVIDER_16) || \
+                             ((DIV) == TIM_CLOCK_DIVIDER_32) || \
+                             ((DIV) == TIM_CLOCK_DIVIDER_40) || \
+                             ((DIV) == TIM_CLOCK_DIVIDER_64)) //!< Check if the input parameter is valid.
+
+/** End of TIM_Clock_Divider
+  * \}
+  */
+
+/** End of TIM_Exported_Constants
+  * \}
+  */
+
+/** End of TIM
+  * \}
+  */
+
+/*============================================================================*
+ *                          TIM TYPE/API Wrappers
+ *============================================================================*/
+/** \defgroup TIM         TIM
+  * \brief
+  * \{
+  */
+
+/** \defgroup TIM_Exported_Constants TIM Exported Constants
+  * \brief
+  * \{
+  */
+
+/**
+* \defgroup    TIM_Struct_Wrapper TIM Struct Wrapper
+* \{
+* \ingroup     TIM_Exported_Constants
+*/
+
+#define TIM_ClockSrcDiv      TIM_SOURCE_DIV     //!< The macro is a wrapper for TIM_SOURCE_DIV.
+#define TIM_ClockSrcDiv_En   TIM_SOURCE_DIV_En  //!< The macro is a wrapper for TIM_SOURCE_DIV_En.
+
+#define CK_40M_TIMER         TIM_CLOCK_SRC_40M  //!< The macro is a wrapper for TIM_CLOCK_SRC_40M.
+#define CK_32K_TIMER         TIM_CLOCK_SRC_32K  //!< The macro is a wrapper for TIM_CLOCK_SRC_32K.
+#define CK_PLL2_TIMER        TIM_CLOCK_SRC_PLL1 //!< The macro is a wrapper for TIM_CLOCK_SRC_PLL1.
+#define CK_PLL1_TIMER        TIM_CLOCK_SRC_PLL2 //!< The macro is a wrapper for TIM_CLOCK_SRC_PLL2.
+
+/** End of TIM_Struct_Wrapper
+  * \}
+  */
+
+/**
+ * \defgroup    TIM_API_Wrapper TIM API Wrapper
+ * \{
+ * \ingroup     TIM_Exported_Constants
+ */
+#define TIM_GetStatus      TIM_GetOperationStatus //!< The macro is a wrapper for TIM_GetOperationStatus.
+
+/** End of TIM_API_Wrapper
+  * \}
+  */
+
+/** End of TIM_Exported_Constants
+  * \}
+  */
+
+/** End of TIM
+  * \}
+  */
+
+#ifdef  __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* RTL_TIM_DEF_H */
diff --git a/bee/drivers/timer/src/device/rtl87x2j/rtl87x2j_timer.c b/bee/drivers/timer/src/device/rtl87x2j/rtl87x2j_timer.c
new file mode 100644
index 00000000..682f9c10
--- /dev/null
+++ b/bee/drivers/timer/src/device/rtl87x2j/rtl87x2j_timer.c
@@ -0,0 +1,296 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *                           Header Files
+ *============================================================================*/
+#include "rtl_timer.h"
+#include "rtl_rcc.h"
+
+/*============================================================================*
+ *                           Private Defines
+ *============================================================================*/
+#define TIMER_TRIG_CTRL *((volatile uint32_t *)(SOC_VENDOR_REG_BASE + 0x0028))
+
+/*============================================================================*
+ *                           Public Functions
+ *============================================================================*/
+uint32_t TIMER_GetTimerID(TIMER_TypeDef *TIMERx)
+{
+    uint32_t timerid = 0xFF;
+    uint32_t timerbase = (uint32_t)TIMERx;
+
+    if ((TIMERx == TIMER0_CH0) || (TIMERx == TIMER0_CH1))
+    {
+        timerid = (timerbase - TIMER0_BASE) / 0x50;
+    }
+    else if (TIMERx == TIMER2_CH0)
+    {
+        timerid = (timerbase - ENHANCED_TIMER_BASE) / 0x50;
+    }
+    else
+    {
+        timerid = (timerbase - TIMER1_BASE) / 0x50;
+    }
+    return timerid;
+}
+
+TIMERCASE_TypeDef TIMER_GetTimerCase(TIMER_TypeDef *TIMERx)
+{
+    if ((TIMERx == TIMER0_CH0) || (TIMERx == TIMER0_CH1))
+    {
+        return TIMER_CASE1;
+    }
+    else if ((TIMERx >= TIMER1_CH0) && (TIMERx <= TIMER1_CH5))
+    {
+        return TIMER_CASE7;
+    }
+    else if ((TIMERx >= TIMER1_CH6) && (TIMERx <= TIMER1_CH8))
+    {
+        return TIMER_CASE3;
+    }
+    else
+    {
+        return TIMER_CASE5;
+    }
+}
+
+TIMER_ShareTypeDef *TIMER_GetTimerShareBase(TIMER_TypeDef *TIMERx)
+{
+    if ((TIMERx == TIMER0_CH0) || (TIMERx == TIMER0_CH1))
+    {
+        return TIMER0_SHARE;
+    }
+    else if (TIMERx == TIMER2_CH0)
+    {
+        return TIMER2_SHARE;
+    }
+    else
+    {
+        return TIMER1_SHARE;
+    }
+}
+
+/**
+  * \brief  TIMER clock config.
+  * \param  TIMERx: Select the TIMER peripheral. \ref TIMER_Declaration
+  * \param  ClockSrc: specifies the clock source to gates its clock.
+  * \param  ClockDiv: specifies the clock divide to gates its clock.
+  * \return None
+  */
+void TIMER_SetClock(TIMER_TypeDef *TIMERx, uint32_t ClockSrc, uint16_t ClockDiv)
+{
+    uint32_t timerid = TIMER_GetTimerID(TIMERx);
+
+    if (TIMERx == TIMER0_CH0)
+    {
+        PCC_REG_WRITE_BITFIELD(PCC_REG_TIMER0, R_TIMER_1_CLK_DIV, ClockDiv);
+    }
+    else if (TIMERx == TIMER0_CH1)
+    {
+        PCC_REG_WRITE_BITFIELD(PCC_REG_TIMER0, R_TIMER_2_CLK_DIV, ClockDiv);
+    }
+    else if (TIMERx == TIMER2_CH0)
+    {
+        PCC_REG_WRITE_BITFIELD(PCC_REG_TIMER2, R_ETIMER_CLK_DIV_SEL, ClockDiv);
+    }
+    else
+    {
+        uint32_t clkdivpos = 0;
+        if (timerid <= 2) /* TIMER1_CH0 TIMER1_CH1 TIMER1_CH2 */
+        {
+            clkdivpos = 20 + timerid * 3; /* BIT20~22 BIT23~25 BIT26~28 */
+
+            PCC_REG_UPDATE(PCC_REG_TIMER1_A, 7 << clkdivpos, ClockDiv << clkdivpos);
+        }
+        else if (timerid <= 5) /* TIMER1_CH3 TIMER1_CH4 TIMER1_CH5 */
+        {
+            clkdivpos = 20 + (timerid - 3) * 3; /* BIT20~22 BIT23~25 BIT26~28 */
+
+            PCC_REG_UPDATE(PCC_REG_TIMER1_B, 7 << clkdivpos, ClockDiv << clkdivpos);
+        }
+        else /* TIMER1_CH6 TIMER1_CH7 TIMER1_CH8 */
+        {
+            clkdivpos = 20 + (timerid - 6) * 3; /* BIT20~22 BIT23~25 BIT26~28 */
+
+            PCC_REG_UPDATE(PCC_REG_TIMER1_C, 7 << clkdivpos, ClockDiv << clkdivpos);
+        }
+    }
+}
+
+/**
+ * \brief  Change the PWM dead zone clock source.
+ * \param  PWMx: Select the PWM peripheral. \ref PWM_Declaration
+ * \param  PWM_Deazone_ClockSrc: New state of the PWMx peripheral.
+ *         \arg PWM_CK_5M_TIMER: Use 5M clock source.
+ *         \arg PWM_TIM_CLOCK_SRC_32K: Use 32k clock source.
+ * \return None.
+ * \note   To use this function, need to configure the corresponding timer.
+ *         PWM2 ->> TIMER2, PWM3 ->> TIMER3.
+ */
+void TIMER_SetPWMDZClock(TIMER_TypeDef *TIMERx, uint16_t ClockSrc, uint16_t ClockDiv)
+{
+    uint32_t timerid = TIMER_GetTimerID(TIMERx);
+
+    if (TIMERx == TIMER2_CH0)
+    {
+        PCC_REG_WRITE_BITFIELD(PCC_REG_TIMER2_PWM, R_ETIMER_PWM_CLK_SRC_SEL, ClockSrc);
+        PCC_REG_WRITE_BITFIELD(PCC_REG_TIMER2_PWM, R_ETIMER_PWM_CLK_DIV_SEL, ClockDiv);
+    }
+    else if (TIMERx == TIMER1_CH6 || TIMERx == TIMER1_CH7 || TIMERx == TIMER1_CH8)
+    {
+        /* TIMER1_CH6 TIMER1_CH7 TIMER1_CH8 */
+        uint32_t clksrcpos = 16 + (timerid - 6); /* BIT16 BIT17 BIT18 */
+        uint32_t clkdivpos = 19 + (timerid - 6) * 3; /* BIT19~21 BIT22~24 BIT25~28 */
+
+        PCC_REG_UPDATE(PCC_REG_TIMER1_D, 1 << clksrcpos, ClockSrc << clksrcpos);
+        PCC_REG_UPDATE(PCC_REG_TIMER1_D, 7 << clkdivpos, ClockDiv << clkdivpos);
+    }
+}
+
+void TIMER_ClockAutoModeCmd(TIMER_TypeDef *TIMERx, FunctionalState Newstate)
+{
+    /* Check the parameters */
+    assert_param(IS_TIMER_ALL_PERIPH(TIMERx));
+    uint32_t timerid = TIMER_GetTimerID(TIMERx);
+
+    if (Newstate == ENABLE)
+    {
+        if (TIMERx == TIMER2_CH0)
+        {
+            PCC_REG_WRITE_BITFIELD(PCC_REG_PERION_CLK_REG4X, FORCE_QACTIVE_ETIMER, 0);
+        }
+        else if ((TIMERx == TIMER0_CH0) || (TIMERx == TIMER0_CH1))
+        {
+            uint8_t timerxpos = 18 + timerid;
+            PCC_REG_UPDATE(PCC_REG_PERION_CLK_REG4X, 1 << timerxpos, 0 << timerxpos);
+        }
+        else
+        {
+            uint8_t timerxpos = 20 + timerid;
+            PCC_REG_UPDATE(PCC_REG_PERION_CLK_REG4X, 1 << timerxpos, 0 << timerxpos);
+        }
+    }
+    else
+    {
+        if (TIMERx == TIMER2_CH0)
+        {
+            PCC_REG_WRITE_BITFIELD(PCC_REG_PERION_CLK_REG4X, FORCE_QACTIVE_ETIMER, 1);
+            while (!PCC_REG_READ_BITFIELD(PCC_REG_PERION_CLK_REG0X, CLKEN_O_ETIMER));
+        }
+        else if ((TIMERx == TIMER0_CH0) || (TIMERx == TIMER0_CH1))
+        {
+            uint8_t timerxpos = 18 + timerid;
+            PCC_REG_UPDATE(PCC_REG_PERION_CLK_REG4X, 1 << timerxpos, 1 << timerxpos);
+            while (!((PCC_REG_READ(PCC_REG_PERION_CLK_REG0X) & BIT(timerxpos)) >> timerxpos));
+        }
+        else
+        {
+            uint8_t timerxpos = 20 + timerid;
+            PCC_REG_UPDATE(PCC_REG_PERION_CLK_REG4X, 1 << timerxpos, 1 << timerxpos);
+            while (!((PCC_REG_READ(PCC_REG_PERION_CLK_REG0X) & BIT(timerxpos)) >> timerxpos));
+        }
+    }
+
+
+    return;
+}
+
+void TIMER_DynamicConfigCmd(TIMER_TypeDef *TIMERx, FunctionalState Newstate)
+{
+    /* Check the parameters */
+    assert_param(IS_TIMER_ALL_PERIPH(TIMERx));
+
+    uint32_t timerid = TIMER_GetTimerID(TIMERx);
+    TIMER_ShareTypeDef *sharebase = TIMER_GetTimerShareBase(TIMERx);
+
+    if (Newstate == ENABLE)
+    {
+        sharebase->TIMER_Q_CH_FW_CTRL0 &= ~BIT(timerid);
+    }
+    else
+    {
+        sharebase->TIMER_Q_CH_FW_CTRL0 |= BIT(timerid);
+    }
+
+    return;
+}
+
+/*============================================================================*
+ *                        LATCH Functions
+ *============================================================================*/
+const uint8_t latch_mapping_table[TOTAL_PIN_NUM] =
+{
+    0,  1,  2,  3,      /*!< P0_0 P0_1 P0_2 P0_3 */
+    4,  5,  6,  7,      /*!< P0_4 P0_5 P0_6 P0_7 */
+    8,  9,  12, 13,     /*!< P1_0 P1_1 P1_6 P1_7 */
+    14, 15, 16, 17,     /*!< P2_0 P2_1 P2_2 P2_3 */
+    18, 19, 20, 21,     /*!< P2_4 P2_5 P2_6 P2_7 */
+    22, 23, 24, 25,     /*!< P3_0 P3_1 P3_2 P3_3 */
+    26, 27, 28, 29,     /*!< P3_4 P3_5 P3_6 P4_0 */
+    30, 31, 32, 49,     /*!< P4_1 P4_2 P4_3 MICBIAS */
+    33, 34, 35, 36,     /*!< P5_1 P5_2 P6_0 P6_1 */
+    37, 38, 39, 40,     /*!< P6_2 P6_3 P6_4 P6_5 */
+    41, 42, 43, 44,     /*!< P6_6 P6_7 P7_0 P7_1 */
+    45, 46, 47, 48,     /*!< SPIC_CSN SPIC_SCK SPIC_SI SPIC_SO */
+    11, 10,             /*!< SPIC_WEN SPIC_HOLDEN */
+};
+
+void TIMER_SetLatchTriggerPad(TIMER_TypeDef *TIMERx, uint8_t Pin_num)
+{
+    uint8_t latch_number = latch_mapping_table[Pin_num];
+
+    PLATFORM_REG_WRITE_BITFIELD(PLATFORM_REG_ENHTIMER_TRIG_CTRL, enhtimer_gpio_trig_sel, latch_number);
+}
+
+void TIMER_LatchDebCmd(TIMER_TypeDef *TIMERx, FunctionalState Newstate)
+{
+    PLATFORM_REG_WRITE_BITFIELD(PLATFORM_REG_ENHTIMER_TRIG_CTRL, enhtimer_gpio_trig_deb_en, Newstate);;
+}
+
+void TIMER_SetLatchDebClock(TIMER_TypeDef *TIMERx, uint16_t ClockSrc, uint16_t ClockDiv,
+                            uint16_t CountLimit)
+{
+    /* Clock Source Fix 32K */
+    PCC_REG_WRITE_BITFIELD(PCC_REG_GPIO_DEBOUNCE_2P4G, DBNC_DIV_SEL, ClockDiv);
+    PLATFORM_REG_WRITE_BITFIELD(PLATFORM_REG_ENHTIMER_TRIG_CTRL, enhtimer_gpio_trig_deb_cnt_limit,
+                                CountLimit);
+}
+
+/*============================================================================*
+ *                        EXTI Functions
+ *============================================================================*/
+static struct
+{
+    IRQ_Fun timer_callback[2];
+} timer_isr;
+
+static void TIMER_ISRUpdate(uint32_t irqn, IRQ_Fun isr_handler)
+{
+    timer_isr.timer_callback[irqn & 0xFF] = isr_handler;
+}
+
+void TIMER0_CH0_CH1_ISR(void)
+{
+    uint32_t real_interrupt_status = TIMER0_SHARE->TIMER_INTR;
+    while (real_interrupt_status)
+    {
+        uint8_t idx = 31 - __builtin_clz(real_interrupt_status);
+        if (timer_isr.timer_callback[idx])
+        {
+            timer_isr.timer_callback[idx]();
+        }
+        real_interrupt_status &= ~BIT(idx);
+    }
+}
+
+void TIMER_IRQInit(void)
+{
+    ram_vector_table_register(TIMER0_CH0_CH1_IRQn, TIMER_ISRUpdate);
+    ram_vector_table_update(TIMER0_CH0_CH1_IRQn, TIMER0_CH0_CH1_ISR);
+}
+
+
diff --git a/bee/drivers/timer/src/device/rtl87x2j/rtl_timer_def.h b/bee/drivers/timer/src/device/rtl87x2j/rtl_timer_def.h
new file mode 100644
index 00000000..3eb628db
--- /dev/null
+++ b/bee/drivers/timer/src/device/rtl87x2j/rtl_timer_def.h
@@ -0,0 +1,4020 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef RTL_TIMER_DEF_H
+#define RTL_TIMER_DEF_H
+
+#include "utils/rtl_utils.h"
+#include "address_map.h"
+#include "platform_reg.h"
+
+#ifdef  __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/*============================================================================*
+ *                          TIMER Defines
+ *============================================================================*/
+/** \defgroup TIMER      TIMER
+  * \brief
+  * \{
+  */
+
+/** \defgroup TIMER_Exported_Constants TIMER Exported Constants
+  * \brief
+  * \{
+  */
+
+/**
+ * \defgroup TIMER_Defines TIMER Defines
+ * \{
+ * \ingroup  TIMER_Exported_Constants
+ */
+/**********************************************************************************************************************
+ **********************************************************************************************************************
+ |             Function              | case1  case7  case6  case2  case3  case4  case5 |         TIMER Defines          |
+ |-----------------------------------|-------------------------------------------------|------------------------------|
+ |  Timer Only                       |   Y      Y      Y      Y      Y      Y      Y   |  NO                          |
+ |-----------------------------------|-------------------------------------------------|------------------------------|
+ |  PWM Only                         |          Y      Y      Y      Y      Y      Y   |  TIMER_SUPPORT_PWM_FUNCTION    |
+ |-----------------------------------|-------------------------------------------------|------------------------------|
+ |  PWM with shift_mode + dead_zone  |                 Y      Y      Y      Y      Y   |  TIMER_SUPPORT_PWM_PHASE_SHIFT |
+ |                                   |                                                 |  TIMER_SUPPORT_PWM_DEADZONE    |
+ |-----------------------------------|-------------------------------------------------|------------------------------|
+ |  PWM with CCR FIFO                |                        Y      Y      Y      Y   |  TIMER_SUPPORT_CCR_FIFO        |
+ |-----------------------------------|-------------------------------------------------|------------------------------|
+ |  PWM with CCR FIFO + DMA          |                               Y      Y      Y   |  TIMER_SUPPORT_CCR_FIFO        |
+ |                                   |                                                 |  TIMER_SUPPORT_DMA             |
+ |-----------------------------------|-------------------------------------------------|------------------------------|
+ |  LATCH_COUNT_0                    |                                      Y      Y   |  TIMER_SUPPORT_LATCH_CNT_0     |
+ |-----------------------------------|-------------------------------------------------|------------------------------|
+ |  LATCH_COUNT_1 + LATCH_COUNT_2    |                                             Y   |  TIMER_SUPPORT_LATCH_CNT_1     |
+ |                                   |                                                 |  TIMER_SUPPORT_LATCH_CNT_2     |
+ |-----------------------------------|-------------------------------------------------|------------------------------|
+ ***********************************************************************************************************************/
+#define TIMER_SUPPORT_PWM_FUNCTION                    (1) /* Case7 */
+#define TIMER_SUPPORT_PWM_PHASE_SHIFT                 (1) /* Case6 */
+#define TIMER_SUPPORT_PWM_DEADZONE                    (1) /* Case6 */
+#define TIMER_SUPPORT_CCR_FIFO                        (1) /* Case2 Case3*/
+#define TIMER_SUPPORT_DMA_FUNCTION                    (1) /* Case3 */
+#define TIMER_SUPPORT_LATCH_CNT_0                     (1) /* Case4 */
+#define TIMER_SUPPORT_LATCH_CNT_1                     (1) /* Case5 */
+#define TIMER_SUPPORT_LATCH_CNT_2                     (1) /* Case5 */
+#define TIMER_SUPPORT_FREERUN_MODE                    (1)
+#define TIMER_SUPPORT_USERDEFINE_AUTO_MODE            (1)
+#define TIMER_SUPPORT_DIRECTION                       (0)
+#define TIMER_SUPPORT_PWM_MODE                        (0)
+#define TIMER_SUPPORT_PWM_STOP_STATE_CONTROL          (0)
+#define TIMER_SUPPORT_PWM_DEADZONE_REFERENCE          (1)
+#define TIMER_SUPPORT_PERIOD_IMMEDIATELY_UPDATE       (0)
+#define TIMER_SUPPORT_TOGGLE_OUTPUT                   (0)
+#define TIMER_COMPARE_CHANNEL_NUM                     (0)
+#define TIMER_CAPTURE_CHANNEL_NUM                     (0)
+#define TIMER_SUPPORT_CC_FIFO                         (0)
+#define TIMER_SUPPORT_CLEAR_COUNTER                   (0)
+
+#define TIMER_SUPPORT_RAP_FUNCTION                    (1)
+#define TIMER_SUPPORT_AUTO_CLOCK                      (1)
+
+/** End of TIMER_Defines
+  * \}
+  */
+
+/** End of TIMER_Exported_Constants
+  * \}
+  */
+
+/** End of TIMER
+  * \}
+  */
+/*============================================================================*
+ *                         TIMER Registers Memory Map
+ *============================================================================*/
+typedef struct
+{
+    __I  uint32_t TIMER_CUR_CNT;                /*!< 0x00 */
+    __IO uint32_t TIMER_MODE_CFG;               /*!< 0x04 */
+    __IO uint32_t TIMER_MAX_CNT;                /*!< 0x08 */
+    __IO uint32_t TIMER_CCR;                    /*!< 0x0C */
+    __IO uint32_t TIMER_CCR_FIFO;               /*!< 0x10 */
+    __IO uint32_t TIMER_PWM_CFG;                /*!< 0x14 */
+    __IO uint32_t TIMER_PWM_SHIFT_CNT;          /*!< 0x18 */
+    __IO uint32_t TIMER_LAT_CNT_0_CFG;          /*!< 0x1C */
+    __I  uint32_t TIMER_LAT_CNT_0;              /*!< 0x20 */
+    __I  uint32_t TIMER_LAT_CNT_0_FIFO_DEPTH;   /*!< 0x24 */
+    __IO uint32_t TIMER_LAT_CNT_1_CFG;          /*!< 0x28 */
+    __I  uint32_t TIMER_LAT_CNT_1;              /*!< 0x2C */
+    __I  uint32_t TIMER_LAT_CNT_1_FIFO_DEPTH;   /*!< 0x30 */
+    __IO uint32_t TIMER_LAT_CNT_2_CFG;          /*!< 0x34 */
+    __I  uint32_t TIMER_LAT_CNT_2;              /*!< 0x38 */
+    __I  uint32_t TIMER_LAT_CNT_2_FIFO_DEPTH;   /*!< 0x3C */
+    __IO uint32_t TIMER_DMA_CFG;                /*!< 0x40 */
+    __I  uint32_t TIMER_DMY_0;                  /*!< 0x44 */
+    __I  uint32_t TIMER_DMY_1;                  /*!< 0x48 */
+    __I  uint32_t TIMER_DMY_2;                  /*!< 0x4C */
+} TIMER_TypeDef;
+
+typedef struct
+{
+    __IO uint32_t TIMER_EN_CTRL;                                   /*!< 0x00 */
+    __IO uint32_t TIMER_ONESHOT_GO_CTRL;                           /*!< 0x04 */
+    __I  uint32_t TIMER_PWM_STATE;                                 /*!< 0x08 */
+    __IO uint32_t TIMER_INTR_EN_CTRL;                              /*!< 0x0C */
+    __IO uint32_t TIMER_INTR_STS;                                  /*!< 0x10 */
+    __I  uint32_t TIMER_INTR;                                      /*!< 0x14 */
+    __I  uint32_t TIMER_CCR_FIFO_EMPTY_STS;                        /*!< 0x18 */
+    __I  uint32_t TIMER_CCR_FIFO_FULL_STS;                         /*!< 0x1C */
+    __IO uint32_t TIMER_LAT_CNT_0_FIFO_FULL_INTR_EN_CTRL;          /*!< 0x20 */
+    __IO uint32_t TIMER_LAT_CNT_0_FIFO_MET_THRESHOLD_INTR_EN_CTRL; /*!< 0x24 */
+    __I  uint32_t TIMER_LAT_CNT_0_FIFO_EMPTY_STS;                  /*!< 0x28 */
+    __IO uint32_t TIMER_LAT_CNT_0_FIFO_FULL_INTR;                  /*!< 0x2C */
+    __IO uint32_t TIMER_LAT_CNT_0_FIFO_MET_THRESHOLD_INTR;         /*!< 0x30 */
+    __I  uint32_t TIMER_LAT_CNT_1_FIFO_FULL_INTR_EN_CTRL;          /*!< 0x34 */
+    __I  uint32_t TIMER_LAT_CNT_1_FIFO_MET_THRESHOLD_INTR_EN_CTRL; /*!< 0x38 */
+    __I  uint32_t TIMER_LAT_CNT_1_FIFO_EMPTY_STS;                  /*!< 0x3C */
+    __I  uint32_t TIMER_LAT_CNT_1_FIFO_FULL_INTR;                  /*!< 0x40 */
+    __I  uint32_t TIMER_LAT_CNT_1_FIFO_MET_THRESHOLD_INTR;         /*!< 0x44 */
+    __I  uint32_t TIMER_LAT_CNT_2_FIFO_FULL_INTR_EN_CTRL;          /*!< 0x48 */
+    __I  uint32_t TIMER_LAT_CNT_2_FIFO_MET_THRESHOLD_INTR_EN_CTRL; /*!< 0x4C */
+    __I  uint32_t TIMER_LAT_CNT_2_FIFO_EMPTY_STS;                  /*!< 0x50 */
+    __I  uint32_t TIMER_LAT_CNT_2_FIFO_FULL_INTR;                  /*!< 0x54 */
+    __I  uint32_t TIMER_LAT_CNT_2_FIFO_MET_THRESHOLD_INTR;         /*!< 0x58 */
+    __IO uint32_t TIMER_PAUSE_CTRL;                                /*!< 0x5C */
+    __IO uint32_t TIMER_PAUSE_INTR_EN_CTRL;                        /*!< 0x60 */
+    __IO uint32_t TIMER_PAUSE_INTR_STS;                            /*!< 0x64 */
+    __I  uint32_t TIMER_PAUSE_INTR;                                /*!< 0x68 */
+    __I  uint32_t TIMER_SHARE_DMY_0;                               /*!< 0x6C */
+    __I  uint32_t TIMER_SHARE_DMY_1;                               /*!< 0x70 */
+    __I  uint32_t TIMER_SHARE_DMY_2;                               /*!< 0x74 */
+    __I  uint32_t TIMER_SHARE_DMY_3;                               /*!< 0x78 */
+    __I  uint32_t TIMER_SHARE_DMY_4;                               /*!< 0x7C */
+    __IO uint32_t TIMER_RAP_CTRL0;                                 /*!< 0x80 */
+    __IO uint32_t TIMER_RAP_CTRL1;                                 /*!< 0x84 */
+    __IO uint32_t TIMER_RAP_FW_TSAK_START;                         /*!< 0x88 */
+    __IO uint32_t TIMER_RAP_FW_TASK_PAUSE;                         /*!< 0x8C */
+    __IO uint32_t TIMER_RAP_FW_TASK_DISABLE;                       /*!< 0x90 */
+    __I  uint32_t TIMER_RAP_STS_ACTIVE;                            /*!< 0x94 */
+    __IO uint32_t TIMER_RAP_SHORTCUT_SUB_TASK_PAUSE;               /*!< 0x98 */
+    __IO uint32_t TIMER_RAP_SHORTCUT_SUB_TASK_DISABLE;             /*!< 0x9C */
+    __IO uint32_t TIMER_RAP_SHORTCUT_PUB_EVENT_TIMEOUT;            /*!< 0xA0 */
+    __I  uint32_t TIMER_RAP_DMY_0;                                 /*!< 0xA4 */
+    __I  uint32_t TIMER_RAP_DMY_1;                                 /*!< 0xA8 */
+    __I  uint32_t TIMER_RAP_DMY_2;                                 /*!< 0xAC */
+    __I  uint32_t TIMER_IP_VER;                                    /*!< 0xB0 */
+    __I  uint32_t TIMER_SHARE_DMY_5;                               /*!< 0xB4 */
+    __I  uint32_t TIMER_SHARE_DMY_6;                               /*!< 0xB8 */
+    __I  uint32_t TIMER_SHARE_DMY_7;                               /*!< 0xBC */
+    __IO uint32_t TIMER_Q_CH_FW_CTRL0;                             /*!< 0xC0 */
+    __IO uint32_t TIMER_Q_CH_FW_CTRL1;                             /*!< 0xC4 */
+    __I  uint32_t TIMER_Q_CH_QACTIVE_FW_CTRL2;                     /*!< 0xC8 */
+    __IO uint32_t TIMER_Q_CH_QACTIVE_FW_CTRL3;                     /*!< 0xCC */
+    __I  uint32_t TIMER_Q_CH_QACTIVE_FW_CTRL4;                     /*!< 0xD0 */
+    __IO uint32_t TIMER_Q_CH_QACTIVE_FW_CTRL5;                     /*!< 0xD4 */
+} TIMER_ShareTypeDef;
+
+typedef struct
+{
+    __IO uint32_t TIMER_PWM_CFG;                                  /*!< 0x14 */
+} PWM_TypeDef;
+
+/*============================================================================*
+ *                         TIMER Declaration
+ *============================================================================*/
+/** \defgroup TIMER      TIMER
+  * \brief
+  * \{
+  */
+
+/** \defgroup TIMER_Exported_Constants TIMER Exported Constants
+  * \brief
+  * \{
+  */
+
+/** \defgroup TIMER_Declaration TIMER Declaration
+  * \{
+  * \ingroup  TIMER_Exported_Constants
+  */
+
+#define TIMER0_SHARE                 ((TIMER_ShareTypeDef *) (TIMER0_BASE + 0xA00))
+#define TIMER1_SHARE                 ((TIMER_ShareTypeDef *) (TIMER1_BASE + 0xA00))
+#define TIMER2_SHARE                 ((TIMER_ShareTypeDef *) (ENHANCED_TIMER_BASE + 0xA00))
+
+/*============================================================================*
+ *                         TIMER0 Declaration
+ *============================================================================*/
+#define TIMER0_CH0_REG_BASE          (TIMER0_BASE + 0x0000)
+#define TIMER0_CH1_REG_BASE          (TIMER0_BASE + 0x0050)
+
+#define TIMER0_CH0                     ((TIMER_TypeDef *) TIMER0_CH0_REG_BASE)
+#define TIMER0_CH1                     ((TIMER_TypeDef *) TIMER0_CH1_REG_BASE)
+
+#define IS_TIMER0_PERIPH(PERIPH)       (((PERIPH) == TIMER0_CH0) || \
+                                        ((PERIPH) == TIMER0_CH1))
+
+/*============================================================================*
+ *                         TIMER1 Declaration
+ *============================================================================*/
+#define TIMER1_CH0_REG_BASE          (TIMER1_BASE + 0x0000)
+#define TIMER1_CH1_REG_BASE          (TIMER1_BASE + 0x0050)
+#define TIMER1_CH2_REG_BASE          (TIMER1_BASE + 0x00A0)
+#define TIMER1_CH3_REG_BASE          (TIMER1_BASE + 0x00F0)
+#define TIMER1_CH4_REG_BASE          (TIMER1_BASE + 0x0140)
+#define TIMER1_CH5_REG_BASE          (TIMER1_BASE + 0x0190)
+#define TIMER1_CH6_REG_BASE          (TIMER1_BASE + 0x01E0)
+#define TIMER1_CH7_REG_BASE          (TIMER1_BASE + 0x0230)
+#define TIMER1_CH8_REG_BASE          (TIMER1_BASE + 0x0280)
+
+#define TIMER1_CH0                     ((TIMER_TypeDef *) TIMER1_CH0_REG_BASE)
+#define TIMER1_CH1                     ((TIMER_TypeDef *) TIMER1_CH1_REG_BASE)
+#define TIMER1_CH2                     ((TIMER_TypeDef *) TIMER1_CH2_REG_BASE)
+#define TIMER1_CH3                     ((TIMER_TypeDef *) TIMER1_CH3_REG_BASE)
+#define TIMER1_CH4                     ((TIMER_TypeDef *) TIMER1_CH4_REG_BASE)
+#define TIMER1_CH5                     ((TIMER_TypeDef *) TIMER1_CH5_REG_BASE)
+#define TIMER1_CH6                     ((TIMER_TypeDef *) TIMER1_CH6_REG_BASE)
+#define TIMER1_CH7                     ((TIMER_TypeDef *) TIMER1_CH7_REG_BASE)
+#define TIMER1_CH8                     ((TIMER_TypeDef *) TIMER1_CH8_REG_BASE)
+
+#define IS_TIMER1_PERIPH(PERIPH)       (((PERIPH) == TIMER1_CH0) || \
+                                        ((PERIPH) == TIMER1_CH1) || \
+                                        ((PERIPH) == TIMER1_CH2) || \
+                                        ((PERIPH) == TIMER1_CH3) || \
+                                        ((PERIPH) == TIMER1_CH4) || \
+                                        ((PERIPH) == TIMER1_CH5) || \
+                                        ((PERIPH) == TIMER1_CH6) || \
+                                        ((PERIPH) == TIMER1_CH7) || \
+                                        ((PERIPH) == TIMER1_CH8))
+
+/*============================================================================*
+ *                         ENHTIMER Declaration
+ *============================================================================*/
+#define TIMER2_REG_BASE                (ENHANCED_TIMER_BASE + 0x0000)
+
+#define TIMER2_CH0                     ((TIMER_TypeDef *) TIMER2_REG_BASE)
+
+#define IS_TIMER2_PERIPH(PERIPH)       (((PERIPH) == TIMER2_CH0))
+
+
+#define IS_TIMER_ALL_PERIPH(PERIPH)    (IS_TIMER0_PERIPH(PERIPH) || \
+                                        IS_TIMER1_PERIPH(PERIPH) || \
+                                        IS_TIMER2_PERIPH(PERIPH))
+
+/** End of TIMER_Declaration
+  * \}
+  */
+
+/** \defgroup TIMER_IRQn TIMER IRQn
+  * \{
+  * \ingroup  TIMER_Exported_Constants
+  */
+#ifdef IS_TIMER0_PERIPH
+#define TIMER0_CH0_IRQn                SUB_IRQ_DEF(TIMER0_CH0_CH1_IRQn, 0)
+#define TIMER0_CH1_IRQn                SUB_IRQ_DEF(TIMER0_CH0_CH1_IRQn, 1)
+#endif
+
+/** End of GPIO_IRQn
+  * \}
+  */
+
+/** End of TIMER_Exported_Constants
+  * \}
+  */
+
+/** End of TIMER
+  * \}
+  */
+
+/*============================================================================*
+ *                         TIMER Private Defines
+ *============================================================================*/
+
+/*============================================================================*
+ *                         TIMER Private Types
+ *============================================================================*/
+
+/*============================================================================*
+ *                         TIMER Registers and Field Descriptions
+ *============================================================================*/
+/* 0x00
+   31:0    R      reg_timer_cur_cnt                                   32'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t reg_timer_cur_cnt: 32;
+    } b;
+} TIMER_CUR_CNT_TypeDef;
+
+
+/* 0x04
+   1:0     R/W    reg_timer_mode                                      2'h0
+   2       R/WAC  reg_timer_ccr_fifo_clr                              1'h0
+   7:3     R      reserved8                                           5'h0
+   8       R/W    reg_timer_oneshot_mode_en                           1'h0
+   31:9    R      reserved6                                           23'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t reg_timer_mode: 2;
+        uint32_t reg_timer_ccr_fifo_clr: 1;
+        const uint32_t reserved_1: 5;
+        uint32_t reg_timer_oneshot_mode_en: 1;
+        const uint32_t reserved_0: 23;
+    } b;
+} TIMER_MODE_CFG_TypeDef;
+
+
+/* 0x08
+   31:0    R/W    reg_timer_max_cnt                                   32'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t reg_timer_max_cnt: 32;
+    } b;
+} TIMER_MAX_CNT_TypeDef;
+
+
+/* 0x0C
+   31:0    R/W    reg_timer_ccr                                       32'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t reg_timer_ccr: 32;
+    } b;
+} TIMER_CCR_TypeDef;
+
+
+/* 0x10
+   31:0    R/W    reg_timer_ccr_fifo                                  32'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t reg_timer_ccr_fifo: 32;
+    } b;
+} TIMER_CCR_FIFO_TypeDef;
+
+
+/* 0x14
+   0       R/W    reg_timer_pwm_en                                    1'h0
+   1       R/W    reg_timer_pwm_polarity                              1'h0
+   2       R/W    reg_timer_pwm_open_drain_en                         1'h0
+   3       R/W    reg_timer_pwm_dz_en                                 1'h0
+   11:4    R/W    reg_timer_pwm_dz_size                               8'h0
+   12      R/W    reg_timer_pwm_dz_emg_stop                           1'h0
+   13      R/W    reg_timer_pwm_dz_stop_state_n                       1'h0
+   14      R/W    reg_timer_pwm_dz_stop_state_p                       1'h0
+   16:15   R/W    reg_timer_pwm_dz_ref_sel                            2'h0
+   17      R/W    reg_timer_pwm_dz_ref_n_inv_en                       1'h0
+   18      R/W    reg_timer_pwm_dz_ref_p_inv_en                       1'h0
+   19      R      reserved19                                          1'h0
+   31:20   R      reserved18                                          12'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t reg_timer_pwm_en: 1;
+        uint32_t reg_timer_pwm_polarity: 1;
+        uint32_t reg_timer_pwm_open_drain_en: 1;
+        uint32_t reg_timer_pwm_dz_en: 1;
+        uint32_t reg_timer_pwm_dz_size: 8;
+        uint32_t reg_timer_pwm_dz_emg_stop: 1;
+        uint32_t reg_timer_pwm_dz_stop_state_n: 1;
+        uint32_t reg_timer_pwm_dz_stop_state_p: 1;
+        uint32_t reg_timer_pwm_dz_ref_sel: 2;
+        uint32_t reg_timer_pwm_dz_ref_n_inv_en: 1;
+        uint32_t reg_timer_pwm_dz_ref_p_inv_en: 1;
+        const uint32_t reserved_1: 1;
+        const uint32_t reserved_0: 12;
+    } b;
+} TIMER_PWM_CFG_TypeDef;
+
+
+/* 0x18
+   31:0    R/W    reg_timer_pwm_phase_shift_cnt                       32'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t reg_timer_pwm_phase_shift_cnt: 32;
+    } b;
+} TIMER_PWM_SHIFT_CNT_TypeDef;
+
+
+/* 0x1C
+   0       R/W    reg_timer_latch_cnt_0_en                            1'h0
+   2:1     R/W    reg_timer_latch_cnt_0_trig_mode                     2'h0
+   3       R/WAC  reg_timer_latch_cnt_0_fifo_clr                      1'h0
+   7:4     R      reserved36                                          4'h0
+   15:8    R/W    reg_timer_latch_cnt_0_fifo_th                       8'h1
+   31:16   R      reserved34                                          16'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t reg_timer_latch_cnt_0_en: 1;
+        uint32_t reg_timer_latch_cnt_0_trig_mode: 2;
+        uint32_t reg_timer_latch_cnt_0_fifo_clr: 1;
+        const uint32_t reserved_1: 4;
+        uint32_t reg_timer_latch_cnt_0_fifo_th: 8;
+        const uint32_t reserved_0: 16;
+    } b;
+} TIMER_LAT_CNT_0_CFG_TypeDef;
+
+
+/* 0x20
+   31:0    R      reg_timer_latch_cnt_0                               32'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t reg_timer_latch_cnt_0: 32;
+    } b;
+} TIMER_LAT_CNT_0_TypeDef;
+
+
+/* 0x24
+   7:0     R      reg_timer_latch_cnt_0_fifo_depth                    8'h0
+   31:8    R      reserved43                                          24'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t reg_timer_latch_cnt_0_fifo_depth: 8;
+        const uint32_t reserved_0: 24;
+    } b;
+} TIMER_LAT_CNT_0_FIFO_DEPTH_TypeDef;
+
+
+/* 0x28
+   0       R/W    reg_timer_latch_cnt_1_en                            1'h0
+   2:1     R/W    reg_timer_latch_cnt_1_trig_mode                     2'h0
+   3       R      reserved49                                          1'h0
+   7:4     R      reserved48                                          4'h0
+   15:8    R      reserved47                                          8'h0
+   31:16   R      reserved46                                          16'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t reg_timer_latch_cnt_1_en: 1;
+        uint32_t reg_timer_latch_cnt_1_trig_mode: 2;
+        const uint32_t reserved_3: 1;
+        const uint32_t reserved_2: 4;
+        const uint32_t reserved_1: 8;
+        const uint32_t reserved_0: 16;
+    } b;
+} TIMER_LAT_CNT_1_CFG_TypeDef;
+
+
+/* 0x2C
+   31:0    R      reg_timer_latch_cnt_1                               32'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t reg_timer_latch_cnt_1: 32;
+    } b;
+} TIMER_LAT_CNT_1_TypeDef;
+
+
+/* 0x30
+   7:0     R      reserved56                                          8'h0
+   31:8    R      reserved55                                          24'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t reserved_1: 8;
+        const uint32_t reserved_0: 24;
+    } b;
+} TIMER_LAT_CNT_1_FIFO_DEPTH_TypeDef;
+
+
+/* 0x34
+   0       R/W    reg_timer_latch_cnt_2_en                            1'h0
+   2:1     R/W    reg_timer_latch_cnt_2_trig_mode                     2'h0
+   3       R      reserved61                                          1'h0
+   7:4     R      reserved60                                          4'h0
+   15:8    R      reserved59                                          8'h0
+   31:16   R      reserved58                                          16'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t reg_timer_latch_cnt_2_en: 1;
+        uint32_t reg_timer_latch_cnt_2_trig_mode: 2;
+        const uint32_t reserved_3: 1;
+        const uint32_t reserved_2: 4;
+        const uint32_t reserved_1: 8;
+        const uint32_t reserved_0: 16;
+    } b;
+} TIMER_LAT_CNT_2_CFG_TypeDef;
+
+
+/* 0x38
+   31:0    R      reg_timer_latch_cnt_2                               32'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t reg_timer_latch_cnt_2: 32;
+    } b;
+} TIMER_LAT_CNT_2_TypeDef;
+
+
+/* 0x3C
+   7:0     R      reserved68                                          8'h0
+   31:8    R      reserved67                                          24'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t reserved_1: 8;
+        const uint32_t reserved_0: 24;
+    } b;
+} TIMER_LAT_CNT_2_FIFO_DEPTH_TypeDef;
+
+
+/* 0x40
+   0       R/W    reg_timer_dma_en                                    1'h0
+   1       R/W    reg_timer_dma_mode                                  1'h0
+   3:2     R/W    reg_timer_dma_target                                2'h0
+   31:4    R      reserved70                                          28'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t reg_timer_dma_en: 1;
+        uint32_t reg_timer_dma_mode: 1;
+        uint32_t reg_timer_dma_target: 2;
+        const uint32_t reserved_0: 28;
+    } b;
+} TIMER_DMA_CFG_TypeDef;
+
+
+/* 0x44
+   31:0    R      reserved75                                          32'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t reserved_0: 32;
+    } b;
+} TIMER_DMY_0_TypeDef;
+
+
+/* 0x48
+   31:0    R      reserved77                                          32'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t reserved_0: 32;
+    } b;
+} TIMER_DMY_1_TypeDef;
+
+
+/* 0x4C
+   31:0    R      reserved79                                          32'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t reserved_0: 32;
+    } b;
+} TIMER_DMY_2_TypeDef;
+
+
+/*============================================================================*
+ *              TIMER Share Registers and Field Descriptions
+ *============================================================================*/
+/* 0x00
+   0       R/W    reg_timer_0_en                              1'h0
+   1       R/W    reg_timer_1_en                              1'h0
+   2       R/W    reg_timer_2_en                              1'h0
+   3       R/W    reg_timer_3_en                              1'h0
+   4       R/W    reg_timer_4_en                              1'h0
+   5       R/W    reg_timer_5_en                              1'h0
+   6       R/W    reg_timer_6_en                              1'h0
+   7       R/W    reg_timer_7_en                              1'h0
+   8       R/W    reg_timer_8_en                              1'h0
+   9       R      RESERVED2490                                1'h0
+   10      R      RESERVED2489                                1'h0
+   11      R      RESERVED2488                                1'h0
+   12      R      RESERVED2487                                1'h0
+   13      R      RESERVED2486                                1'h0
+   14      R      RESERVED2485                                1'h0
+   15      R      RESERVED2484                                1'h0
+   16      R      RESERVED2483                                1'h0
+   17      R      RESERVED2482                                1'h0
+   18      R      RESERVED2481                                1'h0
+   19      R      RESERVED2480                                1'h0
+   20      R      RESERVED2479                                1'h0
+   21      R      RESERVED2478                                1'h0
+   22      R      RESERVED2477                                1'h0
+   23      R      RESERVED2476                                1'h0
+   24      R      RESERVED2475                                1'h0
+   25      R      RESERVED2474                                1'h0
+   26      R      RESERVED2473                                1'h0
+   27      R      RESERVED2472                                1'h0
+   28      R      RESERVED2471                                1'h0
+   29      R      RESERVED2470                                1'h0
+   30      R      RESERVED2469                                1'h0
+   31      R      RESERVED2468                                1'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t reg_timer_0_en: 1;
+        uint32_t reg_timer_1_en: 1;
+        uint32_t reg_timer_2_en: 1;
+        uint32_t reg_timer_3_en: 1;
+        uint32_t reg_timer_4_en: 1;
+        uint32_t reg_timer_5_en: 1;
+        uint32_t reg_timer_6_en: 1;
+        uint32_t reg_timer_7_en: 1;
+        uint32_t reg_timer_8_en: 1;
+        const uint32_t reserved_22: 1;
+        const uint32_t reserved_21: 1;
+        const uint32_t reserved_20: 1;
+        const uint32_t reserved_19: 1;
+        const uint32_t reserved_18: 1;
+        const uint32_t reserved_17: 1;
+        const uint32_t reserved_16: 1;
+        const uint32_t reserved_15: 1;
+        const uint32_t reserved_14: 1;
+        const uint32_t reserved_13: 1;
+        const uint32_t reserved_12: 1;
+        const uint32_t reserved_11: 1;
+        const uint32_t reserved_10: 1;
+        const uint32_t reserved_9: 1;
+        const uint32_t reserved_8: 1;
+        const uint32_t reserved_7: 1;
+        const uint32_t reserved_6: 1;
+        const uint32_t reserved_5: 1;
+        const uint32_t reserved_4: 1;
+        const uint32_t reserved_3: 1;
+        const uint32_t reserved_2: 1;
+        const uint32_t reserved_1: 1;
+        const uint32_t reserved_0: 1;
+    } b;
+} TIMER_EN_CTRL_TypeDef;
+
+
+/* 0x04
+   0       R/WAC  reg_timer_0_oneshot_go                      1'h0
+   1       R/WAC  reg_timer_1_oneshot_go                      1'h0
+   2       R/WAC  reg_timer_2_oneshot_go                      1'h0
+   3       R/WAC  reg_timer_3_oneshot_go                      1'h0
+   4       R/WAC  reg_timer_4_oneshot_go                      1'h0
+   5       R/WAC  reg_timer_5_oneshot_go                      1'h0
+   6       R/WAC  reg_timer_6_oneshot_go                      1'h0
+   7       R/WAC  reg_timer_7_oneshot_go                      1'h0
+   8       R/WAC  reg_timer_8_oneshot_go                      1'h0
+   9       R      RESERVED2523                                1'h0
+   10      R      RESERVED2522                                1'h0
+   11      R      RESERVED2521                                1'h0
+   12      R      RESERVED2520                                1'h0
+   13      R      RESERVED2519                                1'h0
+   14      R      RESERVED2518                                1'h0
+   15      R      RESERVED2517                                1'h0
+   16      R      RESERVED2516                                1'h0
+   17      R      RESERVED2515                                1'h0
+   18      R      RESERVED2514                                1'h0
+   19      R      RESERVED2513                                1'h0
+   20      R      RESERVED2512                                1'h0
+   21      R      RESERVED2511                                1'h0
+   22      R      RESERVED2510                                1'h0
+   23      R      RESERVED2509                                1'h0
+   24      R      RESERVED2508                                1'h0
+   25      R      RESERVED2507                                1'h0
+   26      R      RESERVED2506                                1'h0
+   27      R      RESERVED2505                                1'h0
+   28      R      RESERVED2504                                1'h0
+   29      R      RESERVED2503                                1'h0
+   30      R      RESERVED2502                                1'h0
+   31      R      RESERVED2501                                1'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t reg_timer_0_oneshot_go: 1;
+        uint32_t reg_timer_1_oneshot_go: 1;
+        uint32_t reg_timer_2_oneshot_go: 1;
+        uint32_t reg_timer_3_oneshot_go: 1;
+        uint32_t reg_timer_4_oneshot_go: 1;
+        uint32_t reg_timer_5_oneshot_go: 1;
+        uint32_t reg_timer_6_oneshot_go: 1;
+        uint32_t reg_timer_7_oneshot_go: 1;
+        uint32_t reg_timer_8_oneshot_go: 1;
+        const uint32_t reserved_22: 1;
+        const uint32_t reserved_21: 1;
+        const uint32_t reserved_20: 1;
+        const uint32_t reserved_19: 1;
+        const uint32_t reserved_18: 1;
+        const uint32_t reserved_17: 1;
+        const uint32_t reserved_16: 1;
+        const uint32_t reserved_15: 1;
+        const uint32_t reserved_14: 1;
+        const uint32_t reserved_13: 1;
+        const uint32_t reserved_12: 1;
+        const uint32_t reserved_11: 1;
+        const uint32_t reserved_10: 1;
+        const uint32_t reserved_9: 1;
+        const uint32_t reserved_8: 1;
+        const uint32_t reserved_7: 1;
+        const uint32_t reserved_6: 1;
+        const uint32_t reserved_5: 1;
+        const uint32_t reserved_4: 1;
+        const uint32_t reserved_3: 1;
+        const uint32_t reserved_2: 1;
+        const uint32_t reserved_1: 1;
+        const uint32_t reserved_0: 1;
+    } b;
+} TIMER_ONESHOT_GO_CTRL_TypeDef;
+
+
+/* 0x08
+   0       R      reg_timer_0_toggle_state                    1'h0
+   1       R      reg_timer_1_toggle_state                    1'h0
+   2       R      reg_timer_2_toggle_state                    1'h0
+   3       R      reg_timer_3_toggle_state                    1'h0
+   4       R      reg_timer_4_toggle_state                    1'h0
+   5       R      reg_timer_5_toggle_state                    1'h0
+   6       R      reg_timer_6_toggle_state                    1'h0
+   7       R      reg_timer_7_toggle_state                    1'h0
+   8       R      reg_timer_8_toggle_state                    1'h0
+   9       R      RESERVED2556                                1'h0
+   10      R      RESERVED2555                                1'h0
+   11      R      RESERVED2554                                1'h0
+   12      R      RESERVED2553                                1'h0
+   13      R      RESERVED2552                                1'h0
+   14      R      RESERVED2551                                1'h0
+   15      R      RESERVED2550                                1'h0
+   16      R      RESERVED2549                                1'h0
+   17      R      RESERVED2548                                1'h0
+   18      R      RESERVED2547                                1'h0
+   19      R      RESERVED2546                                1'h0
+   20      R      RESERVED2545                                1'h0
+   21      R      RESERVED2544                                1'h0
+   22      R      RESERVED2543                                1'h0
+   23      R      RESERVED2542                                1'h0
+   24      R      RESERVED2541                                1'h0
+   25      R      RESERVED2540                                1'h0
+   26      R      RESERVED2539                                1'h0
+   27      R      RESERVED2538                                1'h0
+   28      R      RESERVED2537                                1'h0
+   29      R      RESERVED2536                                1'h0
+   30      R      RESERVED2535                                1'h0
+   31      R      RESERVED2534                                1'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t reg_timer_0_toggle_state: 1;
+        const uint32_t reg_timer_1_toggle_state: 1;
+        const uint32_t reg_timer_2_toggle_state: 1;
+        const uint32_t reg_timer_3_toggle_state: 1;
+        const uint32_t reg_timer_4_toggle_state: 1;
+        const uint32_t reg_timer_5_toggle_state: 1;
+        const uint32_t reg_timer_6_toggle_state: 1;
+        const uint32_t reg_timer_7_toggle_state: 1;
+        const uint32_t reg_timer_8_toggle_state: 1;
+        const uint32_t reserved_22: 1;
+        const uint32_t reserved_21: 1;
+        const uint32_t reserved_20: 1;
+        const uint32_t reserved_19: 1;
+        const uint32_t reserved_18: 1;
+        const uint32_t reserved_17: 1;
+        const uint32_t reserved_16: 1;
+        const uint32_t reserved_15: 1;
+        const uint32_t reserved_14: 1;
+        const uint32_t reserved_13: 1;
+        const uint32_t reserved_12: 1;
+        const uint32_t reserved_11: 1;
+        const uint32_t reserved_10: 1;
+        const uint32_t reserved_9: 1;
+        const uint32_t reserved_8: 1;
+        const uint32_t reserved_7: 1;
+        const uint32_t reserved_6: 1;
+        const uint32_t reserved_5: 1;
+        const uint32_t reserved_4: 1;
+        const uint32_t reserved_3: 1;
+        const uint32_t reserved_2: 1;
+        const uint32_t reserved_1: 1;
+        const uint32_t reserved_0: 1;
+    } b;
+} TIMER_PWM_STATE_TypeDef;
+
+
+/* 0x0C
+   0       R/W    reg_timer_0_intr_en                         1'h0
+   1       R/W    reg_timer_1_intr_en                         1'h0
+   2       R/W    reg_timer_2_intr_en                         1'h0
+   3       R/W    reg_timer_3_intr_en                         1'h0
+   4       R/W    reg_timer_4_intr_en                         1'h0
+   5       R/W    reg_timer_5_intr_en                         1'h0
+   6       R/W    reg_timer_6_intr_en                         1'h0
+   7       R/W    reg_timer_7_intr_en                         1'h0
+   8       R/W    reg_timer_8_intr_en                         1'h0
+   9       R      RESERVED2589                                1'h0
+   10      R      RESERVED2588                                1'h0
+   11      R      RESERVED2587                                1'h0
+   12      R      RESERVED2586                                1'h0
+   13      R      RESERVED2585                                1'h0
+   14      R      RESERVED2584                                1'h0
+   15      R      RESERVED2583                                1'h0
+   16      R      RESERVED2582                                1'h0
+   17      R      RESERVED2581                                1'h0
+   18      R      RESERVED2580                                1'h0
+   19      R      RESERVED2579                                1'h0
+   20      R      RESERVED2578                                1'h0
+   21      R      RESERVED2577                                1'h0
+   22      R      RESERVED2576                                1'h0
+   23      R      RESERVED2575                                1'h0
+   24      R      RESERVED2574                                1'h0
+   25      R      RESERVED2573                                1'h0
+   26      R      RESERVED2572                                1'h0
+   27      R      RESERVED2571                                1'h0
+   28      R      RESERVED2570                                1'h0
+   29      R      RESERVED2569                                1'h0
+   30      R      RESERVED2568                                1'h0
+   31      R      RESERVED2567                                1'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t reg_timer_0_intr_en: 1;
+        uint32_t reg_timer_1_intr_en: 1;
+        uint32_t reg_timer_2_intr_en: 1;
+        uint32_t reg_timer_3_intr_en: 1;
+        uint32_t reg_timer_4_intr_en: 1;
+        uint32_t reg_timer_5_intr_en: 1;
+        uint32_t reg_timer_6_intr_en: 1;
+        uint32_t reg_timer_7_intr_en: 1;
+        uint32_t reg_timer_8_intr_en: 1;
+        const uint32_t reserved_22: 1;
+        const uint32_t reserved_21: 1;
+        const uint32_t reserved_20: 1;
+        const uint32_t reserved_19: 1;
+        const uint32_t reserved_18: 1;
+        const uint32_t reserved_17: 1;
+        const uint32_t reserved_16: 1;
+        const uint32_t reserved_15: 1;
+        const uint32_t reserved_14: 1;
+        const uint32_t reserved_13: 1;
+        const uint32_t reserved_12: 1;
+        const uint32_t reserved_11: 1;
+        const uint32_t reserved_10: 1;
+        const uint32_t reserved_9: 1;
+        const uint32_t reserved_8: 1;
+        const uint32_t reserved_7: 1;
+        const uint32_t reserved_6: 1;
+        const uint32_t reserved_5: 1;
+        const uint32_t reserved_4: 1;
+        const uint32_t reserved_3: 1;
+        const uint32_t reserved_2: 1;
+        const uint32_t reserved_1: 1;
+        const uint32_t reserved_0: 1;
+    } b;
+} TIMER_INTR_EN_CTRL_TypeDef;
+
+
+/* 0x10
+   0       R/W1C  reg_timer_0_intr_sts                        1'h0
+   1       R/W1C  reg_timer_1_intr_sts                        1'h0
+   2       R/W1C  reg_timer_2_intr_sts                        1'h0
+   3       R/W1C  reg_timer_3_intr_sts                        1'h0
+   4       R/W1C  reg_timer_4_intr_sts                        1'h0
+   5       R/W1C  reg_timer_5_intr_sts                        1'h0
+   6       R/W1C  reg_timer_6_intr_sts                        1'h0
+   7       R/W1C  reg_timer_7_intr_sts                        1'h0
+   8       R/W1C  reg_timer_8_intr_sts                        1'h0
+   9       R      RESERVED2622                                1'h0
+   10      R      RESERVED2621                                1'h0
+   11      R      RESERVED2620                                1'h0
+   12      R      RESERVED2619                                1'h0
+   13      R      RESERVED2618                                1'h0
+   14      R      RESERVED2617                                1'h0
+   15      R      RESERVED2616                                1'h0
+   16      R      RESERVED2615                                1'h0
+   17      R      RESERVED2614                                1'h0
+   18      R      RESERVED2613                                1'h0
+   19      R      RESERVED2612                                1'h0
+   20      R      RESERVED2611                                1'h0
+   21      R      RESERVED2610                                1'h0
+   22      R      RESERVED2609                                1'h0
+   23      R      RESERVED2608                                1'h0
+   24      R      RESERVED2607                                1'h0
+   25      R      RESERVED2606                                1'h0
+   26      R      RESERVED2605                                1'h0
+   27      R      RESERVED2604                                1'h0
+   28      R      RESERVED2603                                1'h0
+   29      R      RESERVED2602                                1'h0
+   30      R      RESERVED2601                                1'h0
+   31      R      RESERVED2600                                1'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t reg_timer_0_intr_sts: 1;
+        uint32_t reg_timer_1_intr_sts: 1;
+        uint32_t reg_timer_2_intr_sts: 1;
+        uint32_t reg_timer_3_intr_sts: 1;
+        uint32_t reg_timer_4_intr_sts: 1;
+        uint32_t reg_timer_5_intr_sts: 1;
+        uint32_t reg_timer_6_intr_sts: 1;
+        uint32_t reg_timer_7_intr_sts: 1;
+        uint32_t reg_timer_8_intr_sts: 1;
+        const uint32_t reserved_22: 1;
+        const uint32_t reserved_21: 1;
+        const uint32_t reserved_20: 1;
+        const uint32_t reserved_19: 1;
+        const uint32_t reserved_18: 1;
+        const uint32_t reserved_17: 1;
+        const uint32_t reserved_16: 1;
+        const uint32_t reserved_15: 1;
+        const uint32_t reserved_14: 1;
+        const uint32_t reserved_13: 1;
+        const uint32_t reserved_12: 1;
+        const uint32_t reserved_11: 1;
+        const uint32_t reserved_10: 1;
+        const uint32_t reserved_9: 1;
+        const uint32_t reserved_8: 1;
+        const uint32_t reserved_7: 1;
+        const uint32_t reserved_6: 1;
+        const uint32_t reserved_5: 1;
+        const uint32_t reserved_4: 1;
+        const uint32_t reserved_3: 1;
+        const uint32_t reserved_2: 1;
+        const uint32_t reserved_1: 1;
+        const uint32_t reserved_0: 1;
+    } b;
+} TIMER_INTR_STS_TypeDef;
+
+
+/* 0x14
+   0       R      reg_timer_0_intr_sts_masked                 1'h0
+   1       R      reg_timer_1_intr_sts_masked                 1'h0
+   2       R      reg_timer_2_intr_sts_masked                 1'h0
+   3       R      reg_timer_3_intr_sts_masked                 1'h0
+   4       R      reg_timer_4_intr_sts_masked                 1'h0
+   5       R      reg_timer_5_intr_sts_masked                 1'h0
+   6       R      reg_timer_6_intr_sts_masked                 1'h0
+   7       R      reg_timer_7_intr_sts_masked                 1'h0
+   8       R      reg_timer_8_intr_sts_masked                 1'h0
+   9       R      RESERVED2655                                1'h0
+   10      R      RESERVED2654                                1'h0
+   11      R      RESERVED2653                                1'h0
+   12      R      RESERVED2652                                1'h0
+   13      R      RESERVED2651                                1'h0
+   14      R      RESERVED2650                                1'h0
+   15      R      RESERVED2649                                1'h0
+   16      R      RESERVED2648                                1'h0
+   17      R      RESERVED2647                                1'h0
+   18      R      RESERVED2646                                1'h0
+   19      R      RESERVED2645                                1'h0
+   20      R      RESERVED2644                                1'h0
+   21      R      RESERVED2643                                1'h0
+   22      R      RESERVED2642                                1'h0
+   23      R      RESERVED2641                                1'h0
+   24      R      RESERVED2640                                1'h0
+   25      R      RESERVED2639                                1'h0
+   26      R      RESERVED2638                                1'h0
+   27      R      RESERVED2637                                1'h0
+   28      R      RESERVED2636                                1'h0
+   29      R      RESERVED2635                                1'h0
+   30      R      RESERVED2634                                1'h0
+   31      R      RESERVED2633                                1'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t reg_timer_0_intr_sts_masked: 1;
+        const uint32_t reg_timer_1_intr_sts_masked: 1;
+        const uint32_t reg_timer_2_intr_sts_masked: 1;
+        const uint32_t reg_timer_3_intr_sts_masked: 1;
+        const uint32_t reg_timer_4_intr_sts_masked: 1;
+        const uint32_t reg_timer_5_intr_sts_masked: 1;
+        const uint32_t reg_timer_6_intr_sts_masked: 1;
+        const uint32_t reg_timer_7_intr_sts_masked: 1;
+        const uint32_t reg_timer_8_intr_sts_masked: 1;
+        const uint32_t reserved_22: 1;
+        const uint32_t reserved_21: 1;
+        const uint32_t reserved_20: 1;
+        const uint32_t reserved_19: 1;
+        const uint32_t reserved_18: 1;
+        const uint32_t reserved_17: 1;
+        const uint32_t reserved_16: 1;
+        const uint32_t reserved_15: 1;
+        const uint32_t reserved_14: 1;
+        const uint32_t reserved_13: 1;
+        const uint32_t reserved_12: 1;
+        const uint32_t reserved_11: 1;
+        const uint32_t reserved_10: 1;
+        const uint32_t reserved_9: 1;
+        const uint32_t reserved_8: 1;
+        const uint32_t reserved_7: 1;
+        const uint32_t reserved_6: 1;
+        const uint32_t reserved_5: 1;
+        const uint32_t reserved_4: 1;
+        const uint32_t reserved_3: 1;
+        const uint32_t reserved_2: 1;
+        const uint32_t reserved_1: 1;
+        const uint32_t reserved_0: 1;
+    } b;
+} TIMER_INTR_TypeDef;
+
+
+/* 0x18
+   0       R      reg_timer_ccr_fifo_empty                  1'h1
+   1       R      RESERVED2696                              1'h1
+   2       R      RESERVED2695                              1'h1
+   3       R      RESERVED2694                              1'h1
+   4       R      RESERVED2693                              1'h1
+   5       R      RESERVED2692                              1'h1
+   6       R      RESERVED2691                              1'h1
+   7       R      RESERVED2690                              1'h1
+   8       R      RESERVED2689                              1'h1
+   9       R      RESERVED2688                              1'h1
+   10      R      RESERVED2687                              1'h1
+   11      R      RESERVED2686                              1'h1
+   12      R      RESERVED2685                              1'h1
+   13      R      RESERVED2684                              1'h1
+   14      R      RESERVED2683                              1'h1
+   15      R      RESERVED2682                              1'h1
+   16      R      RESERVED2681                              1'h1
+   17      R      RESERVED2680                              1'h1
+   18      R      RESERVED2679                              1'h1
+   19      R      RESERVED2678                              1'h1
+   20      R      RESERVED2677                              1'h1
+   21      R      RESERVED2676                              1'h1
+   22      R      RESERVED2675                              1'h1
+   23      R      RESERVED2674                              1'h1
+   24      R      RESERVED2673                              1'h1
+   25      R      RESERVED2672                              1'h1
+   26      R      RESERVED2671                              1'h1
+   27      R      RESERVED2670                              1'h1
+   28      R      RESERVED2669                              1'h1
+   29      R      RESERVED2668                              1'h1
+   30      R      RESERVED2667                              1'h1
+   31      R      RESERVED2666                              1'h1
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t reg_timer_ccr_fifo_empty: 1;
+        const uint32_t reserved_30: 1;
+        const uint32_t reserved_29: 1;
+        const uint32_t reserved_28: 1;
+        const uint32_t reserved_27: 1;
+        const uint32_t reserved_26: 1;
+        const uint32_t reserved_25: 1;
+        const uint32_t reserved_24: 1;
+        const uint32_t reserved_23: 1;
+        const uint32_t reserved_22: 1;
+        const uint32_t reserved_21: 1;
+        const uint32_t reserved_20: 1;
+        const uint32_t reserved_19: 1;
+        const uint32_t reserved_18: 1;
+        const uint32_t reserved_17: 1;
+        const uint32_t reserved_16: 1;
+        const uint32_t reserved_15: 1;
+        const uint32_t reserved_14: 1;
+        const uint32_t reserved_13: 1;
+        const uint32_t reserved_12: 1;
+        const uint32_t reserved_11: 1;
+        const uint32_t reserved_10: 1;
+        const uint32_t reserved_9: 1;
+        const uint32_t reserved_8: 1;
+        const uint32_t reserved_7: 1;
+        const uint32_t reserved_6: 1;
+        const uint32_t reserved_5: 1;
+        const uint32_t reserved_4: 1;
+        const uint32_t reserved_3: 1;
+        const uint32_t reserved_2: 1;
+        const uint32_t reserved_1: 1;
+        const uint32_t reserved_0: 1;
+    } b;
+} TIMER_CCR_FIFO_EMPTY_STS_TypeDef;
+
+
+/* 0x1C
+   0       R      reg_timer_ccr_fifo_full                   1'h0
+   1       R      RESERVED2729                              1'h0
+   2       R      RESERVED2728                              1'h0
+   3       R      RESERVED2727                              1'h0
+   4       R      RESERVED2726                              1'h0
+   5       R      RESERVED2725                              1'h0
+   6       R      RESERVED2724                              1'h0
+   7       R      RESERVED2723                              1'h0
+   8       R      RESERVED2722                              1'h0
+   9       R      RESERVED2721                              1'h0
+   10      R      RESERVED2720                              1'h0
+   11      R      RESERVED2719                              1'h0
+   12      R      RESERVED2718                              1'h0
+   13      R      RESERVED2717                              1'h0
+   14      R      RESERVED2716                              1'h0
+   15      R      RESERVED2715                              1'h0
+   16      R      RESERVED2714                              1'h0
+   17      R      RESERVED2713                              1'h0
+   18      R      RESERVED2712                              1'h0
+   19      R      RESERVED2711                              1'h0
+   20      R      RESERVED2710                              1'h0
+   21      R      RESERVED2709                              1'h0
+   22      R      RESERVED2708                              1'h0
+   23      R      RESERVED2707                              1'h0
+   24      R      RESERVED2706                              1'h0
+   25      R      RESERVED2705                              1'h0
+   26      R      RESERVED2704                              1'h0
+   27      R      RESERVED2703                              1'h0
+   28      R      RESERVED2702                              1'h0
+   29      R      RESERVED2701                              1'h0
+   30      R      RESERVED2700                              1'h0
+   31      R      RESERVED2699                              1'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t reg_timer_ccr_fifo_full: 1;
+        const uint32_t reserved_30: 1;
+        const uint32_t reserved_29: 1;
+        const uint32_t reserved_28: 1;
+        const uint32_t reserved_27: 1;
+        const uint32_t reserved_26: 1;
+        const uint32_t reserved_25: 1;
+        const uint32_t reserved_24: 1;
+        const uint32_t reserved_23: 1;
+        const uint32_t reserved_22: 1;
+        const uint32_t reserved_21: 1;
+        const uint32_t reserved_20: 1;
+        const uint32_t reserved_19: 1;
+        const uint32_t reserved_18: 1;
+        const uint32_t reserved_17: 1;
+        const uint32_t reserved_16: 1;
+        const uint32_t reserved_15: 1;
+        const uint32_t reserved_14: 1;
+        const uint32_t reserved_13: 1;
+        const uint32_t reserved_12: 1;
+        const uint32_t reserved_11: 1;
+        const uint32_t reserved_10: 1;
+        const uint32_t reserved_9: 1;
+        const uint32_t reserved_8: 1;
+        const uint32_t reserved_7: 1;
+        const uint32_t reserved_6: 1;
+        const uint32_t reserved_5: 1;
+        const uint32_t reserved_4: 1;
+        const uint32_t reserved_3: 1;
+        const uint32_t reserved_2: 1;
+        const uint32_t reserved_1: 1;
+        const uint32_t reserved_0: 1;
+    } b;
+} TIMER_CCR_FIFO_FULL_STS_TypeDef;
+
+
+/* 0x20
+   0       R/W    reg_timer_latch_cnt_0_fifo_full_intr_en   1'h0
+   1       R      RESERVED2762                              1'h0
+   2       R      RESERVED2761                              1'h0
+   3       R      RESERVED2760                              1'h0
+   4       R      RESERVED2759                              1'h0
+   5       R      RESERVED2758                              1'h0
+   6       R      RESERVED2757                              1'h0
+   7       R      RESERVED2756                              1'h0
+   8       R      RESERVED2755                              1'h0
+   9       R      RESERVED2754                              1'h0
+   10      R      RESERVED2753                              1'h0
+   11      R      RESERVED2752                              1'h0
+   12      R      RESERVED2751                              1'h0
+   13      R      RESERVED2750                              1'h0
+   14      R      RESERVED2749                              1'h0
+   15      R      RESERVED2748                              1'h0
+   16      R      RESERVED2747                              1'h0
+   17      R      RESERVED2746                              1'h0
+   18      R      RESERVED2745                              1'h0
+   19      R      RESERVED2744                              1'h0
+   20      R      RESERVED2743                              1'h0
+   21      R      RESERVED2742                              1'h0
+   22      R      RESERVED2741                              1'h0
+   23      R      RESERVED2740                              1'h0
+   24      R      RESERVED2739                              1'h0
+   25      R      RESERVED2738                              1'h0
+   26      R      RESERVED2737                              1'h0
+   27      R      RESERVED2736                              1'h0
+   28      R      RESERVED2735                              1'h0
+   29      R      RESERVED2734                              1'h0
+   30      R      RESERVED2733                              1'h0
+   31      R      RESERVED2732                              1'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t reg_timer_latch_cnt_0_fifo_full_intr_en: 1;
+        const uint32_t reserved_30: 1;
+        const uint32_t reserved_29: 1;
+        const uint32_t reserved_28: 1;
+        const uint32_t reserved_27: 1;
+        const uint32_t reserved_26: 1;
+        const uint32_t reserved_25: 1;
+        const uint32_t reserved_24: 1;
+        const uint32_t reserved_23: 1;
+        const uint32_t reserved_22: 1;
+        const uint32_t reserved_21: 1;
+        const uint32_t reserved_20: 1;
+        const uint32_t reserved_19: 1;
+        const uint32_t reserved_18: 1;
+        const uint32_t reserved_17: 1;
+        const uint32_t reserved_16: 1;
+        const uint32_t reserved_15: 1;
+        const uint32_t reserved_14: 1;
+        const uint32_t reserved_13: 1;
+        const uint32_t reserved_12: 1;
+        const uint32_t reserved_11: 1;
+        const uint32_t reserved_10: 1;
+        const uint32_t reserved_9: 1;
+        const uint32_t reserved_8: 1;
+        const uint32_t reserved_7: 1;
+        const uint32_t reserved_6: 1;
+        const uint32_t reserved_5: 1;
+        const uint32_t reserved_4: 1;
+        const uint32_t reserved_3: 1;
+        const uint32_t reserved_2: 1;
+        const uint32_t reserved_1: 1;
+        const uint32_t reserved_0: 1;
+    } b;
+} TIMER_LAT_CNT_0_FIFO_FULL_INTR_EN_CTRL_TypeDef;
+
+
+/* 0x24
+   0       R/W    reg_timer_latch_cnt_0_fifo_met_th_intr_en 1'h0
+   1       R      RESERVED2795                              1'h0
+   2       R      RESERVED2794                              1'h0
+   3       R      RESERVED2793                              1'h0
+   4       R      RESERVED2792                              1'h0
+   5       R      RESERVED2791                              1'h0
+   6       R      RESERVED2790                              1'h0
+   7       R      RESERVED2789                              1'h0
+   8       R      RESERVED2788                              1'h0
+   9       R      RESERVED2787                              1'h0
+   10      R      RESERVED2786                              1'h0
+   11      R      RESERVED2785                              1'h0
+   12      R      RESERVED2784                              1'h0
+   13      R      RESERVED2783                              1'h0
+   14      R      RESERVED2782                              1'h0
+   15      R      RESERVED2781                              1'h0
+   16      R      RESERVED2780                              1'h0
+   17      R      RESERVED2779                              1'h0
+   18      R      RESERVED2778                              1'h0
+   19      R      RESERVED2777                              1'h0
+   20      R      RESERVED2776                              1'h0
+   21      R      RESERVED2775                              1'h0
+   22      R      RESERVED2774                              1'h0
+   23      R      RESERVED2773                              1'h0
+   24      R      RESERVED2772                              1'h0
+   25      R      RESERVED2771                              1'h0
+   26      R      RESERVED2770                              1'h0
+   27      R      RESERVED2769                              1'h0
+   28      R      RESERVED2768                              1'h0
+   29      R      RESERVED2767                              1'h0
+   30      R      RESERVED2766                              1'h0
+   31      R      RESERVED2765                              1'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t reg_timer_latch_cnt_0_fifo_met_th_intr_en: 1;
+        const uint32_t reserved_30: 1;
+        const uint32_t reserved_29: 1;
+        const uint32_t reserved_28: 1;
+        const uint32_t reserved_27: 1;
+        const uint32_t reserved_26: 1;
+        const uint32_t reserved_25: 1;
+        const uint32_t reserved_24: 1;
+        const uint32_t reserved_23: 1;
+        const uint32_t reserved_22: 1;
+        const uint32_t reserved_21: 1;
+        const uint32_t reserved_20: 1;
+        const uint32_t reserved_19: 1;
+        const uint32_t reserved_18: 1;
+        const uint32_t reserved_17: 1;
+        const uint32_t reserved_16: 1;
+        const uint32_t reserved_15: 1;
+        const uint32_t reserved_14: 1;
+        const uint32_t reserved_13: 1;
+        const uint32_t reserved_12: 1;
+        const uint32_t reserved_11: 1;
+        const uint32_t reserved_10: 1;
+        const uint32_t reserved_9: 1;
+        const uint32_t reserved_8: 1;
+        const uint32_t reserved_7: 1;
+        const uint32_t reserved_6: 1;
+        const uint32_t reserved_5: 1;
+        const uint32_t reserved_4: 1;
+        const uint32_t reserved_3: 1;
+        const uint32_t reserved_2: 1;
+        const uint32_t reserved_1: 1;
+        const uint32_t reserved_0: 1;
+    } b;
+} TIMER_LAT_CNT_0_FIFO_MET_THRESHOLD_INTR_EN_CTRL_TypeDef;
+
+
+/* 0x28
+   0       R      reg_timer_latch_cnt_0_fifo_empty          1'h1
+   1       R      RESERVED2828                              1'h1
+   2       R      RESERVED2827                              1'h1
+   3       R      RESERVED2826                              1'h1
+   4       R      RESERVED2825                              1'h1
+   5       R      RESERVED2824                              1'h1
+   6       R      RESERVED2823                              1'h1
+   7       R      RESERVED2822                              1'h1
+   8       R      RESERVED2821                              1'h1
+   9       R      RESERVED2820                              1'h1
+   10      R      RESERVED2819                              1'h1
+   11      R      RESERVED2818                              1'h1
+   12      R      RESERVED2817                              1'h1
+   13      R      RESERVED2816                              1'h1
+   14      R      RESERVED2815                              1'h1
+   15      R      RESERVED2814                              1'h1
+   16      R      RESERVED2813                              1'h1
+   17      R      RESERVED2812                              1'h1
+   18      R      RESERVED2811                              1'h1
+   19      R      RESERVED2810                              1'h1
+   20      R      RESERVED2809                              1'h1
+   21      R      RESERVED2808                              1'h1
+   22      R      RESERVED2807                              1'h1
+   23      R      RESERVED2806                              1'h1
+   24      R      RESERVED2805                              1'h1
+   25      R      RESERVED2804                              1'h1
+   26      R      RESERVED2803                              1'h1
+   27      R      RESERVED2802                              1'h1
+   28      R      RESERVED2801                              1'h1
+   29      R      RESERVED2800                              1'h1
+   30      R      RESERVED2799                              1'h1
+   31      R      RESERVED2798                              1'h1
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t reg_timer_latch_cnt_0_fifo_empty: 1;
+        const uint32_t reserved_30: 1;
+        const uint32_t reserved_29: 1;
+        const uint32_t reserved_28: 1;
+        const uint32_t reserved_27: 1;
+        const uint32_t reserved_26: 1;
+        const uint32_t reserved_25: 1;
+        const uint32_t reserved_24: 1;
+        const uint32_t reserved_23: 1;
+        const uint32_t reserved_22: 1;
+        const uint32_t reserved_21: 1;
+        const uint32_t reserved_20: 1;
+        const uint32_t reserved_19: 1;
+        const uint32_t reserved_18: 1;
+        const uint32_t reserved_17: 1;
+        const uint32_t reserved_16: 1;
+        const uint32_t reserved_15: 1;
+        const uint32_t reserved_14: 1;
+        const uint32_t reserved_13: 1;
+        const uint32_t reserved_12: 1;
+        const uint32_t reserved_11: 1;
+        const uint32_t reserved_10: 1;
+        const uint32_t reserved_9: 1;
+        const uint32_t reserved_8: 1;
+        const uint32_t reserved_7: 1;
+        const uint32_t reserved_6: 1;
+        const uint32_t reserved_5: 1;
+        const uint32_t reserved_4: 1;
+        const uint32_t reserved_3: 1;
+        const uint32_t reserved_2: 1;
+        const uint32_t reserved_1: 1;
+        const uint32_t reserved_0: 1;
+    } b;
+} TIMER_LAT_CNT_0_FIFO_EMPTY_STS_TypeDef;
+
+
+/* 0x2C
+   0       R/W1C  reg_timer_latch_cnt_0_fifo_full           1'h0
+   1       R      RESERVED2861                              1'h0
+   2       R      RESERVED2860                              1'h0
+   3       R      RESERVED2859                              1'h0
+   4       R      RESERVED2858                              1'h0
+   5       R      RESERVED2857                              1'h0
+   6       R      RESERVED2856                              1'h0
+   7       R      RESERVED2855                              1'h0
+   8       R      RESERVED2854                              1'h0
+   9       R      RESERVED2853                              1'h0
+   10      R      RESERVED2852                              1'h0
+   11      R      RESERVED2851                              1'h0
+   12      R      RESERVED2850                              1'h0
+   13      R      RESERVED2849                              1'h0
+   14      R      RESERVED2848                              1'h0
+   15      R      RESERVED2847                              1'h0
+   16      R      RESERVED2846                              1'h0
+   17      R      RESERVED2845                              1'h0
+   18      R      RESERVED2844                              1'h0
+   19      R      RESERVED2843                              1'h0
+   20      R      RESERVED2842                              1'h0
+   21      R      RESERVED2841                              1'h0
+   22      R      RESERVED2840                              1'h0
+   23      R      RESERVED2839                              1'h0
+   24      R      RESERVED2838                              1'h0
+   25      R      RESERVED2837                              1'h0
+   26      R      RESERVED2836                              1'h0
+   27      R      RESERVED2835                              1'h0
+   28      R      RESERVED2834                              1'h0
+   29      R      RESERVED2833                              1'h0
+   30      R      RESERVED2832                              1'h0
+   31      R      RESERVED2831                              1'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t reg_timer_latch_cnt_0_fifo_full: 1;
+        const uint32_t reserved_30: 1;
+        const uint32_t reserved_29: 1;
+        const uint32_t reserved_28: 1;
+        const uint32_t reserved_27: 1;
+        const uint32_t reserved_26: 1;
+        const uint32_t reserved_25: 1;
+        const uint32_t reserved_24: 1;
+        const uint32_t reserved_23: 1;
+        const uint32_t reserved_22: 1;
+        const uint32_t reserved_21: 1;
+        const uint32_t reserved_20: 1;
+        const uint32_t reserved_19: 1;
+        const uint32_t reserved_18: 1;
+        const uint32_t reserved_17: 1;
+        const uint32_t reserved_16: 1;
+        const uint32_t reserved_15: 1;
+        const uint32_t reserved_14: 1;
+        const uint32_t reserved_13: 1;
+        const uint32_t reserved_12: 1;
+        const uint32_t reserved_11: 1;
+        const uint32_t reserved_10: 1;
+        const uint32_t reserved_9: 1;
+        const uint32_t reserved_8: 1;
+        const uint32_t reserved_7: 1;
+        const uint32_t reserved_6: 1;
+        const uint32_t reserved_5: 1;
+        const uint32_t reserved_4: 1;
+        const uint32_t reserved_3: 1;
+        const uint32_t reserved_2: 1;
+        const uint32_t reserved_1: 1;
+        const uint32_t reserved_0: 1;
+    } b;
+} TIMER_LAT_CNT_0_FIFO_FULL_INTR_TypeDef;
+
+
+/* 0x30
+   0       R/W1C  reg_timer_latch_cnt_0_fifo_met_th         1'h0
+   1       R      RESERVED2894                              1'h0
+   2       R      RESERVED2893                              1'h0
+   3       R      RESERVED2892                              1'h0
+   4       R      RESERVED2891                              1'h0
+   5       R      RESERVED2890                              1'h0
+   6       R      RESERVED2889                              1'h0
+   7       R      RESERVED2888                              1'h0
+   8       R      RESERVED2887                              1'h0
+   9       R      RESERVED2886                              1'h0
+   10      R      RESERVED2885                              1'h0
+   11      R      RESERVED2884                              1'h0
+   12      R      RESERVED2883                              1'h0
+   13      R      RESERVED2882                              1'h0
+   14      R      RESERVED2881                              1'h0
+   15      R      RESERVED2880                              1'h0
+   16      R      RESERVED2879                              1'h0
+   17      R      RESERVED2878                              1'h0
+   18      R      RESERVED2877                              1'h0
+   19      R      RESERVED2876                              1'h0
+   20      R      RESERVED2875                              1'h0
+   21      R      RESERVED2874                              1'h0
+   22      R      RESERVED2873                              1'h0
+   23      R      RESERVED2872                              1'h0
+   24      R      RESERVED2871                              1'h0
+   25      R      RESERVED2870                              1'h0
+   26      R      RESERVED2869                              1'h0
+   27      R      RESERVED2868                              1'h0
+   28      R      RESERVED2867                              1'h0
+   29      R      RESERVED2866                              1'h0
+   30      R      RESERVED2865                              1'h0
+   31      R      RESERVED2864                              1'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t reg_timer_latch_cnt_0_fifo_met_th: 1;
+        const uint32_t reserved_30: 1;
+        const uint32_t reserved_29: 1;
+        const uint32_t reserved_28: 1;
+        const uint32_t reserved_27: 1;
+        const uint32_t reserved_26: 1;
+        const uint32_t reserved_25: 1;
+        const uint32_t reserved_24: 1;
+        const uint32_t reserved_23: 1;
+        const uint32_t reserved_22: 1;
+        const uint32_t reserved_21: 1;
+        const uint32_t reserved_20: 1;
+        const uint32_t reserved_19: 1;
+        const uint32_t reserved_18: 1;
+        const uint32_t reserved_17: 1;
+        const uint32_t reserved_16: 1;
+        const uint32_t reserved_15: 1;
+        const uint32_t reserved_14: 1;
+        const uint32_t reserved_13: 1;
+        const uint32_t reserved_12: 1;
+        const uint32_t reserved_11: 1;
+        const uint32_t reserved_10: 1;
+        const uint32_t reserved_9: 1;
+        const uint32_t reserved_8: 1;
+        const uint32_t reserved_7: 1;
+        const uint32_t reserved_6: 1;
+        const uint32_t reserved_5: 1;
+        const uint32_t reserved_4: 1;
+        const uint32_t reserved_3: 1;
+        const uint32_t reserved_2: 1;
+        const uint32_t reserved_1: 1;
+        const uint32_t reserved_0: 1;
+    } b;
+} TIMER_LAT_CNT_0_FIFO_MET_THRESHOLD_INTR_TypeDef;
+
+
+/* 0x34
+   0       R      RESERVED2928                                1'h0
+   1       R      RESERVED2927                                1'h0
+   2       R      RESERVED2926                                1'h0
+   3       R      RESERVED2925                                1'h0
+   4       R      RESERVED2924                                1'h0
+   5       R      RESERVED2923                                1'h0
+   6       R      RESERVED2922                                1'h0
+   7       R      RESERVED2921                                1'h0
+   8       R      RESERVED2920                                1'h0
+   9       R      RESERVED2919                                1'h0
+   10      R      RESERVED2918                                1'h0
+   11      R      RESERVED2917                                1'h0
+   12      R      RESERVED2916                                1'h0
+   13      R      RESERVED2915                                1'h0
+   14      R      RESERVED2914                                1'h0
+   15      R      RESERVED2913                                1'h0
+   16      R      RESERVED2912                                1'h0
+   17      R      RESERVED2911                                1'h0
+   18      R      RESERVED2910                                1'h0
+   19      R      RESERVED2909                                1'h0
+   20      R      RESERVED2908                                1'h0
+   21      R      RESERVED2907                                1'h0
+   22      R      RESERVED2906                                1'h0
+   23      R      RESERVED2905                                1'h0
+   24      R      RESERVED2904                                1'h0
+   25      R      RESERVED2903                                1'h0
+   26      R      RESERVED2902                                1'h0
+   27      R      RESERVED2901                                1'h0
+   28      R      RESERVED2900                                1'h0
+   29      R      RESERVED2899                                1'h0
+   30      R      RESERVED2898                                1'h0
+   31      R      RESERVED2897                                1'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t reserved_31: 1;
+        const uint32_t reserved_30: 1;
+        const uint32_t reserved_29: 1;
+        const uint32_t reserved_28: 1;
+        const uint32_t reserved_27: 1;
+        const uint32_t reserved_26: 1;
+        const uint32_t reserved_25: 1;
+        const uint32_t reserved_24: 1;
+        const uint32_t reserved_23: 1;
+        const uint32_t reserved_22: 1;
+        const uint32_t reserved_21: 1;
+        const uint32_t reserved_20: 1;
+        const uint32_t reserved_19: 1;
+        const uint32_t reserved_18: 1;
+        const uint32_t reserved_17: 1;
+        const uint32_t reserved_16: 1;
+        const uint32_t reserved_15: 1;
+        const uint32_t reserved_14: 1;
+        const uint32_t reserved_13: 1;
+        const uint32_t reserved_12: 1;
+        const uint32_t reserved_11: 1;
+        const uint32_t reserved_10: 1;
+        const uint32_t reserved_9: 1;
+        const uint32_t reserved_8: 1;
+        const uint32_t reserved_7: 1;
+        const uint32_t reserved_6: 1;
+        const uint32_t reserved_5: 1;
+        const uint32_t reserved_4: 1;
+        const uint32_t reserved_3: 1;
+        const uint32_t reserved_2: 1;
+        const uint32_t reserved_1: 1;
+        const uint32_t reserved_0: 1;
+    } b;
+} TIMER_LAT_CNT_1_FIFO_FULL_INTR_EN_CTRL_TypeDef;
+
+
+/* 0x38
+   0       R      RESERVED2961                                1'h0
+   1       R      RESERVED2960                                1'h0
+   2       R      RESERVED2959                                1'h0
+   3       R      RESERVED2958                                1'h0
+   4       R      RESERVED2957                                1'h0
+   5       R      RESERVED2956                                1'h0
+   6       R      RESERVED2955                                1'h0
+   7       R      RESERVED2954                                1'h0
+   8       R      RESERVED2953                                1'h0
+   9       R      RESERVED2952                                1'h0
+   10      R      RESERVED2951                                1'h0
+   11      R      RESERVED2950                                1'h0
+   12      R      RESERVED2949                                1'h0
+   13      R      RESERVED2948                                1'h0
+   14      R      RESERVED2947                                1'h0
+   15      R      RESERVED2946                                1'h0
+   16      R      RESERVED2945                                1'h0
+   17      R      RESERVED2944                                1'h0
+   18      R      RESERVED2943                                1'h0
+   19      R      RESERVED2942                                1'h0
+   20      R      RESERVED2941                                1'h0
+   21      R      RESERVED2940                                1'h0
+   22      R      RESERVED2939                                1'h0
+   23      R      RESERVED2938                                1'h0
+   24      R      RESERVED2937                                1'h0
+   25      R      RESERVED2936                                1'h0
+   26      R      RESERVED2935                                1'h0
+   27      R      RESERVED2934                                1'h0
+   28      R      RESERVED2933                                1'h0
+   29      R      RESERVED2932                                1'h0
+   30      R      RESERVED2931                                1'h0
+   31      R      RESERVED2930                                1'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t reserved_31: 1;
+        const uint32_t reserved_30: 1;
+        const uint32_t reserved_29: 1;
+        const uint32_t reserved_28: 1;
+        const uint32_t reserved_27: 1;
+        const uint32_t reserved_26: 1;
+        const uint32_t reserved_25: 1;
+        const uint32_t reserved_24: 1;
+        const uint32_t reserved_23: 1;
+        const uint32_t reserved_22: 1;
+        const uint32_t reserved_21: 1;
+        const uint32_t reserved_20: 1;
+        const uint32_t reserved_19: 1;
+        const uint32_t reserved_18: 1;
+        const uint32_t reserved_17: 1;
+        const uint32_t reserved_16: 1;
+        const uint32_t reserved_15: 1;
+        const uint32_t reserved_14: 1;
+        const uint32_t reserved_13: 1;
+        const uint32_t reserved_12: 1;
+        const uint32_t reserved_11: 1;
+        const uint32_t reserved_10: 1;
+        const uint32_t reserved_9: 1;
+        const uint32_t reserved_8: 1;
+        const uint32_t reserved_7: 1;
+        const uint32_t reserved_6: 1;
+        const uint32_t reserved_5: 1;
+        const uint32_t reserved_4: 1;
+        const uint32_t reserved_3: 1;
+        const uint32_t reserved_2: 1;
+        const uint32_t reserved_1: 1;
+        const uint32_t reserved_0: 1;
+    } b;
+} TIMER_LAT_CNT_1_FIFO_MET_THRESHOLD_INTR_EN_CTRL_TypeDef;
+
+
+/* 0x3C
+   0       R      RESERVED2994                                1'h1
+   1       R      RESERVED2993                                1'h1
+   2       R      RESERVED2992                                1'h1
+   3       R      RESERVED2991                                1'h1
+   4       R      RESERVED2990                                1'h1
+   5       R      RESERVED2989                                1'h1
+   6       R      RESERVED2988                                1'h1
+   7       R      RESERVED2987                                1'h1
+   8       R      RESERVED2986                                1'h1
+   9       R      RESERVED2985                                1'h1
+   10      R      RESERVED2984                                1'h1
+   11      R      RESERVED2983                                1'h1
+   12      R      RESERVED2982                                1'h1
+   13      R      RESERVED2981                                1'h1
+   14      R      RESERVED2980                                1'h1
+   15      R      RESERVED2979                                1'h1
+   16      R      RESERVED2978                                1'h1
+   17      R      RESERVED2977                                1'h1
+   18      R      RESERVED2976                                1'h1
+   19      R      RESERVED2975                                1'h1
+   20      R      RESERVED2974                                1'h1
+   21      R      RESERVED2973                                1'h1
+   22      R      RESERVED2972                                1'h1
+   23      R      RESERVED2971                                1'h1
+   24      R      RESERVED2970                                1'h1
+   25      R      RESERVED2969                                1'h1
+   26      R      RESERVED2968                                1'h1
+   27      R      RESERVED2967                                1'h1
+   28      R      RESERVED2966                                1'h1
+   29      R      RESERVED2965                                1'h1
+   30      R      RESERVED2964                                1'h1
+   31      R      RESERVED2963                                1'h1
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t reserved_31: 1;
+        const uint32_t reserved_30: 1;
+        const uint32_t reserved_29: 1;
+        const uint32_t reserved_28: 1;
+        const uint32_t reserved_27: 1;
+        const uint32_t reserved_26: 1;
+        const uint32_t reserved_25: 1;
+        const uint32_t reserved_24: 1;
+        const uint32_t reserved_23: 1;
+        const uint32_t reserved_22: 1;
+        const uint32_t reserved_21: 1;
+        const uint32_t reserved_20: 1;
+        const uint32_t reserved_19: 1;
+        const uint32_t reserved_18: 1;
+        const uint32_t reserved_17: 1;
+        const uint32_t reserved_16: 1;
+        const uint32_t reserved_15: 1;
+        const uint32_t reserved_14: 1;
+        const uint32_t reserved_13: 1;
+        const uint32_t reserved_12: 1;
+        const uint32_t reserved_11: 1;
+        const uint32_t reserved_10: 1;
+        const uint32_t reserved_9: 1;
+        const uint32_t reserved_8: 1;
+        const uint32_t reserved_7: 1;
+        const uint32_t reserved_6: 1;
+        const uint32_t reserved_5: 1;
+        const uint32_t reserved_4: 1;
+        const uint32_t reserved_3: 1;
+        const uint32_t reserved_2: 1;
+        const uint32_t reserved_1: 1;
+        const uint32_t reserved_0: 1;
+    } b;
+} TIMER_LAT_CNT_1_FIFO_EMPTY_STS_TypeDef;
+
+
+/* 0x40
+   0       R      RESERVED3027                                1'h0
+   1       R      RESERVED3026                                1'h0
+   2       R      RESERVED3025                                1'h0
+   3       R      RESERVED3024                                1'h0
+   4       R      RESERVED3023                                1'h0
+   5       R      RESERVED3022                                1'h0
+   6       R      RESERVED3021                                1'h0
+   7       R      RESERVED3020                                1'h0
+   8       R      RESERVED3019                                1'h0
+   9       R      RESERVED3018                                1'h0
+   10      R      RESERVED3017                                1'h0
+   11      R      RESERVED3016                                1'h0
+   12      R      RESERVED3015                                1'h0
+   13      R      RESERVED3014                                1'h0
+   14      R      RESERVED3013                                1'h0
+   15      R      RESERVED3012                                1'h0
+   16      R      RESERVED3011                                1'h0
+   17      R      RESERVED3010                                1'h0
+   18      R      RESERVED3009                                1'h0
+   19      R      RESERVED3008                                1'h0
+   20      R      RESERVED3007                                1'h0
+   21      R      RESERVED3006                                1'h0
+   22      R      RESERVED3005                                1'h0
+   23      R      RESERVED3004                                1'h0
+   24      R      RESERVED3003                                1'h0
+   25      R      RESERVED3002                                1'h0
+   26      R      RESERVED3001                                1'h0
+   27      R      RESERVED3000                                1'h0
+   28      R      RESERVED2999                                1'h0
+   29      R      RESERVED2998                                1'h0
+   30      R      RESERVED2997                                1'h0
+   31      R      RESERVED2996                                1'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t reserved_31: 1;
+        const uint32_t reserved_30: 1;
+        const uint32_t reserved_29: 1;
+        const uint32_t reserved_28: 1;
+        const uint32_t reserved_27: 1;
+        const uint32_t reserved_26: 1;
+        const uint32_t reserved_25: 1;
+        const uint32_t reserved_24: 1;
+        const uint32_t reserved_23: 1;
+        const uint32_t reserved_22: 1;
+        const uint32_t reserved_21: 1;
+        const uint32_t reserved_20: 1;
+        const uint32_t reserved_19: 1;
+        const uint32_t reserved_18: 1;
+        const uint32_t reserved_17: 1;
+        const uint32_t reserved_16: 1;
+        const uint32_t reserved_15: 1;
+        const uint32_t reserved_14: 1;
+        const uint32_t reserved_13: 1;
+        const uint32_t reserved_12: 1;
+        const uint32_t reserved_11: 1;
+        const uint32_t reserved_10: 1;
+        const uint32_t reserved_9: 1;
+        const uint32_t reserved_8: 1;
+        const uint32_t reserved_7: 1;
+        const uint32_t reserved_6: 1;
+        const uint32_t reserved_5: 1;
+        const uint32_t reserved_4: 1;
+        const uint32_t reserved_3: 1;
+        const uint32_t reserved_2: 1;
+        const uint32_t reserved_1: 1;
+        const uint32_t reserved_0: 1;
+    } b;
+} TIMER_LAT_CNT_1_FIFO_FULL_INTR_TypeDef;
+
+
+/* 0x44
+   0       R      RESERVED3060                                1'h0
+   1       R      RESERVED3059                                1'h0
+   2       R      RESERVED3058                                1'h0
+   3       R      RESERVED3057                                1'h0
+   4       R      RESERVED3056                                1'h0
+   5       R      RESERVED3055                                1'h0
+   6       R      RESERVED3054                                1'h0
+   7       R      RESERVED3053                                1'h0
+   8       R      RESERVED3052                                1'h0
+   9       R      RESERVED3051                                1'h0
+   10      R      RESERVED3050                                1'h0
+   11      R      RESERVED3049                                1'h0
+   12      R      RESERVED3048                                1'h0
+   13      R      RESERVED3047                                1'h0
+   14      R      RESERVED3046                                1'h0
+   15      R      RESERVED3045                                1'h0
+   16      R      RESERVED3044                                1'h0
+   17      R      RESERVED3043                                1'h0
+   18      R      RESERVED3042                                1'h0
+   19      R      RESERVED3041                                1'h0
+   20      R      RESERVED3040                                1'h0
+   21      R      RESERVED3039                                1'h0
+   22      R      RESERVED3038                                1'h0
+   23      R      RESERVED3037                                1'h0
+   24      R      RESERVED3036                                1'h0
+   25      R      RESERVED3035                                1'h0
+   26      R      RESERVED3034                                1'h0
+   27      R      RESERVED3033                                1'h0
+   28      R      RESERVED3032                                1'h0
+   29      R      RESERVED3031                                1'h0
+   30      R      RESERVED3030                                1'h0
+   31      R      RESERVED3029                                1'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t reserved_31: 1;
+        const uint32_t reserved_30: 1;
+        const uint32_t reserved_29: 1;
+        const uint32_t reserved_28: 1;
+        const uint32_t reserved_27: 1;
+        const uint32_t reserved_26: 1;
+        const uint32_t reserved_25: 1;
+        const uint32_t reserved_24: 1;
+        const uint32_t reserved_23: 1;
+        const uint32_t reserved_22: 1;
+        const uint32_t reserved_21: 1;
+        const uint32_t reserved_20: 1;
+        const uint32_t reserved_19: 1;
+        const uint32_t reserved_18: 1;
+        const uint32_t reserved_17: 1;
+        const uint32_t reserved_16: 1;
+        const uint32_t reserved_15: 1;
+        const uint32_t reserved_14: 1;
+        const uint32_t reserved_13: 1;
+        const uint32_t reserved_12: 1;
+        const uint32_t reserved_11: 1;
+        const uint32_t reserved_10: 1;
+        const uint32_t reserved_9: 1;
+        const uint32_t reserved_8: 1;
+        const uint32_t reserved_7: 1;
+        const uint32_t reserved_6: 1;
+        const uint32_t reserved_5: 1;
+        const uint32_t reserved_4: 1;
+        const uint32_t reserved_3: 1;
+        const uint32_t reserved_2: 1;
+        const uint32_t reserved_1: 1;
+        const uint32_t reserved_0: 1;
+    } b;
+} TIMER_LAT_CNT_1_FIFO_MET_THRESHOLD_INTR_TypeDef;
+
+
+/* 0x48
+   0       R      RESERVED3093                                1'h0
+   1       R      RESERVED3092                                1'h0
+   2       R      RESERVED3091                                1'h0
+   3       R      RESERVED3090                                1'h0
+   4       R      RESERVED3089                                1'h0
+   5       R      RESERVED3088                                1'h0
+   6       R      RESERVED3087                                1'h0
+   7       R      RESERVED3086                                1'h0
+   8       R      RESERVED3085                                1'h0
+   9       R      RESERVED3084                                1'h0
+   10      R      RESERVED3083                                1'h0
+   11      R      RESERVED3082                                1'h0
+   12      R      RESERVED3081                                1'h0
+   13      R      RESERVED3080                                1'h0
+   14      R      RESERVED3079                                1'h0
+   15      R      RESERVED3078                                1'h0
+   16      R      RESERVED3077                                1'h0
+   17      R      RESERVED3076                                1'h0
+   18      R      RESERVED3075                                1'h0
+   19      R      RESERVED3074                                1'h0
+   20      R      RESERVED3073                                1'h0
+   21      R      RESERVED3072                                1'h0
+   22      R      RESERVED3071                                1'h0
+   23      R      RESERVED3070                                1'h0
+   24      R      RESERVED3069                                1'h0
+   25      R      RESERVED3068                                1'h0
+   26      R      RESERVED3067                                1'h0
+   27      R      RESERVED3066                                1'h0
+   28      R      RESERVED3065                                1'h0
+   29      R      RESERVED3064                                1'h0
+   30      R      RESERVED3063                                1'h0
+   31      R      RESERVED3062                                1'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t reserved_31: 1;
+        const uint32_t reserved_30: 1;
+        const uint32_t reserved_29: 1;
+        const uint32_t reserved_28: 1;
+        const uint32_t reserved_27: 1;
+        const uint32_t reserved_26: 1;
+        const uint32_t reserved_25: 1;
+        const uint32_t reserved_24: 1;
+        const uint32_t reserved_23: 1;
+        const uint32_t reserved_22: 1;
+        const uint32_t reserved_21: 1;
+        const uint32_t reserved_20: 1;
+        const uint32_t reserved_19: 1;
+        const uint32_t reserved_18: 1;
+        const uint32_t reserved_17: 1;
+        const uint32_t reserved_16: 1;
+        const uint32_t reserved_15: 1;
+        const uint32_t reserved_14: 1;
+        const uint32_t reserved_13: 1;
+        const uint32_t reserved_12: 1;
+        const uint32_t reserved_11: 1;
+        const uint32_t reserved_10: 1;
+        const uint32_t reserved_9: 1;
+        const uint32_t reserved_8: 1;
+        const uint32_t reserved_7: 1;
+        const uint32_t reserved_6: 1;
+        const uint32_t reserved_5: 1;
+        const uint32_t reserved_4: 1;
+        const uint32_t reserved_3: 1;
+        const uint32_t reserved_2: 1;
+        const uint32_t reserved_1: 1;
+        const uint32_t reserved_0: 1;
+    } b;
+} TIMER_LAT_CNT_2_FIFO_FULL_INTR_EN_CTRL_TypeDef;
+
+
+/* 0x4C
+   0       R      RESERVED3126                                1'h0
+   1       R      RESERVED3125                                1'h0
+   2       R      RESERVED3124                                1'h0
+   3       R      RESERVED3123                                1'h0
+   4       R      RESERVED3122                                1'h0
+   5       R      RESERVED3121                                1'h0
+   6       R      RESERVED3120                                1'h0
+   7       R      RESERVED3119                                1'h0
+   8       R      RESERVED3118                                1'h0
+   9       R      RESERVED3117                                1'h0
+   10      R      RESERVED3116                                1'h0
+   11      R      RESERVED3115                                1'h0
+   12      R      RESERVED3114                                1'h0
+   13      R      RESERVED3113                                1'h0
+   14      R      RESERVED3112                                1'h0
+   15      R      RESERVED3111                                1'h0
+   16      R      RESERVED3110                                1'h0
+   17      R      RESERVED3109                                1'h0
+   18      R      RESERVED3108                                1'h0
+   19      R      RESERVED3107                                1'h0
+   20      R      RESERVED3106                                1'h0
+   21      R      RESERVED3105                                1'h0
+   22      R      RESERVED3104                                1'h0
+   23      R      RESERVED3103                                1'h0
+   24      R      RESERVED3102                                1'h0
+   25      R      RESERVED3101                                1'h0
+   26      R      RESERVED3100                                1'h0
+   27      R      RESERVED3099                                1'h0
+   28      R      RESERVED3098                                1'h0
+   29      R      RESERVED3097                                1'h0
+   30      R      RESERVED3096                                1'h0
+   31      R      RESERVED3095                                1'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t reserved_31: 1;
+        const uint32_t reserved_30: 1;
+        const uint32_t reserved_29: 1;
+        const uint32_t reserved_28: 1;
+        const uint32_t reserved_27: 1;
+        const uint32_t reserved_26: 1;
+        const uint32_t reserved_25: 1;
+        const uint32_t reserved_24: 1;
+        const uint32_t reserved_23: 1;
+        const uint32_t reserved_22: 1;
+        const uint32_t reserved_21: 1;
+        const uint32_t reserved_20: 1;
+        const uint32_t reserved_19: 1;
+        const uint32_t reserved_18: 1;
+        const uint32_t reserved_17: 1;
+        const uint32_t reserved_16: 1;
+        const uint32_t reserved_15: 1;
+        const uint32_t reserved_14: 1;
+        const uint32_t reserved_13: 1;
+        const uint32_t reserved_12: 1;
+        const uint32_t reserved_11: 1;
+        const uint32_t reserved_10: 1;
+        const uint32_t reserved_9: 1;
+        const uint32_t reserved_8: 1;
+        const uint32_t reserved_7: 1;
+        const uint32_t reserved_6: 1;
+        const uint32_t reserved_5: 1;
+        const uint32_t reserved_4: 1;
+        const uint32_t reserved_3: 1;
+        const uint32_t reserved_2: 1;
+        const uint32_t reserved_1: 1;
+        const uint32_t reserved_0: 1;
+    } b;
+} TIMER_LAT_CNT_2_FIFO_MET_THRESHOLD_INTR_EN_CTRL_TypeDef;
+
+
+/* 0x50
+   0       R      RESERVED3159                                1'h1
+   1       R      RESERVED3158                                1'h1
+   2       R      RESERVED3157                                1'h1
+   3       R      RESERVED3156                                1'h1
+   4       R      RESERVED3155                                1'h1
+   5       R      RESERVED3154                                1'h1
+   6       R      RESERVED3153                                1'h1
+   7       R      RESERVED3152                                1'h1
+   8       R      RESERVED3151                                1'h1
+   9       R      RESERVED3150                                1'h1
+   10      R      RESERVED3149                                1'h1
+   11      R      RESERVED3148                                1'h1
+   12      R      RESERVED3147                                1'h1
+   13      R      RESERVED3146                                1'h1
+   14      R      RESERVED3145                                1'h1
+   15      R      RESERVED3144                                1'h1
+   16      R      RESERVED3143                                1'h1
+   17      R      RESERVED3142                                1'h1
+   18      R      RESERVED3141                                1'h1
+   19      R      RESERVED3140                                1'h1
+   20      R      RESERVED3139                                1'h1
+   21      R      RESERVED3138                                1'h1
+   22      R      RESERVED3137                                1'h1
+   23      R      RESERVED3136                                1'h1
+   24      R      RESERVED3135                                1'h1
+   25      R      RESERVED3134                                1'h1
+   26      R      RESERVED3133                                1'h1
+   27      R      RESERVED3132                                1'h1
+   28      R      RESERVED3131                                1'h1
+   29      R      RESERVED3130                                1'h1
+   30      R      RESERVED3129                                1'h1
+   31      R      RESERVED3128                                1'h1
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t reserved_31: 1;
+        const uint32_t reserved_30: 1;
+        const uint32_t reserved_29: 1;
+        const uint32_t reserved_28: 1;
+        const uint32_t reserved_27: 1;
+        const uint32_t reserved_26: 1;
+        const uint32_t reserved_25: 1;
+        const uint32_t reserved_24: 1;
+        const uint32_t reserved_23: 1;
+        const uint32_t reserved_22: 1;
+        const uint32_t reserved_21: 1;
+        const uint32_t reserved_20: 1;
+        const uint32_t reserved_19: 1;
+        const uint32_t reserved_18: 1;
+        const uint32_t reserved_17: 1;
+        const uint32_t reserved_16: 1;
+        const uint32_t reserved_15: 1;
+        const uint32_t reserved_14: 1;
+        const uint32_t reserved_13: 1;
+        const uint32_t reserved_12: 1;
+        const uint32_t reserved_11: 1;
+        const uint32_t reserved_10: 1;
+        const uint32_t reserved_9: 1;
+        const uint32_t reserved_8: 1;
+        const uint32_t reserved_7: 1;
+        const uint32_t reserved_6: 1;
+        const uint32_t reserved_5: 1;
+        const uint32_t reserved_4: 1;
+        const uint32_t reserved_3: 1;
+        const uint32_t reserved_2: 1;
+        const uint32_t reserved_1: 1;
+        const uint32_t reserved_0: 1;
+    } b;
+} TIMER_LAT_CNT_2_FIFO_EMPTY_STS_TypeDef;
+
+
+/* 0x54
+   0       R      RESERVED3192                                1'h0
+   1       R      RESERVED3191                                1'h0
+   2       R      RESERVED3190                                1'h0
+   3       R      RESERVED3189                                1'h0
+   4       R      RESERVED3188                                1'h0
+   5       R      RESERVED3187                                1'h0
+   6       R      RESERVED3186                                1'h0
+   7       R      RESERVED3185                                1'h0
+   8       R      RESERVED3184                                1'h0
+   9       R      RESERVED3183                                1'h0
+   10      R      RESERVED3182                                1'h0
+   11      R      RESERVED3181                                1'h0
+   12      R      RESERVED3180                                1'h0
+   13      R      RESERVED3179                                1'h0
+   14      R      RESERVED3178                                1'h0
+   15      R      RESERVED3177                                1'h0
+   16      R      RESERVED3176                                1'h0
+   17      R      RESERVED3175                                1'h0
+   18      R      RESERVED3174                                1'h0
+   19      R      RESERVED3173                                1'h0
+   20      R      RESERVED3172                                1'h0
+   21      R      RESERVED3171                                1'h0
+   22      R      RESERVED3170                                1'h0
+   23      R      RESERVED3169                                1'h0
+   24      R      RESERVED3168                                1'h0
+   25      R      RESERVED3167                                1'h0
+   26      R      RESERVED3166                                1'h0
+   27      R      RESERVED3165                                1'h0
+   28      R      RESERVED3164                                1'h0
+   29      R      RESERVED3163                                1'h0
+   30      R      RESERVED3162                                1'h0
+   31      R      RESERVED3161                                1'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t reserved_31: 1;
+        const uint32_t reserved_30: 1;
+        const uint32_t reserved_29: 1;
+        const uint32_t reserved_28: 1;
+        const uint32_t reserved_27: 1;
+        const uint32_t reserved_26: 1;
+        const uint32_t reserved_25: 1;
+        const uint32_t reserved_24: 1;
+        const uint32_t reserved_23: 1;
+        const uint32_t reserved_22: 1;
+        const uint32_t reserved_21: 1;
+        const uint32_t reserved_20: 1;
+        const uint32_t reserved_19: 1;
+        const uint32_t reserved_18: 1;
+        const uint32_t reserved_17: 1;
+        const uint32_t reserved_16: 1;
+        const uint32_t reserved_15: 1;
+        const uint32_t reserved_14: 1;
+        const uint32_t reserved_13: 1;
+        const uint32_t reserved_12: 1;
+        const uint32_t reserved_11: 1;
+        const uint32_t reserved_10: 1;
+        const uint32_t reserved_9: 1;
+        const uint32_t reserved_8: 1;
+        const uint32_t reserved_7: 1;
+        const uint32_t reserved_6: 1;
+        const uint32_t reserved_5: 1;
+        const uint32_t reserved_4: 1;
+        const uint32_t reserved_3: 1;
+        const uint32_t reserved_2: 1;
+        const uint32_t reserved_1: 1;
+        const uint32_t reserved_0: 1;
+    } b;
+} TIMER_LAT_CNT_2_FIFO_FULL_INTR_TypeDef;
+
+
+/* 0x58
+   0       R      RESERVED3225                                1'h0
+   1       R      RESERVED3224                                1'h0
+   2       R      RESERVED3223                                1'h0
+   3       R      RESERVED3222                                1'h0
+   4       R      RESERVED3221                                1'h0
+   5       R      RESERVED3220                                1'h0
+   6       R      RESERVED3219                                1'h0
+   7       R      RESERVED3218                                1'h0
+   8       R      RESERVED3217                                1'h0
+   9       R      RESERVED3216                                1'h0
+   10      R      RESERVED3215                                1'h0
+   11      R      RESERVED3214                                1'h0
+   12      R      RESERVED3213                                1'h0
+   13      R      RESERVED3212                                1'h0
+   14      R      RESERVED3211                                1'h0
+   15      R      RESERVED3210                                1'h0
+   16      R      RESERVED3209                                1'h0
+   17      R      RESERVED3208                                1'h0
+   18      R      RESERVED3207                                1'h0
+   19      R      RESERVED3206                                1'h0
+   20      R      RESERVED3205                                1'h0
+   21      R      RESERVED3204                                1'h0
+   22      R      RESERVED3203                                1'h0
+   23      R      RESERVED3202                                1'h0
+   24      R      RESERVED3201                                1'h0
+   25      R      RESERVED3200                                1'h0
+   26      R      RESERVED3199                                1'h0
+   27      R      RESERVED3198                                1'h0
+   28      R      RESERVED3197                                1'h0
+   29      R      RESERVED3196                                1'h0
+   30      R      RESERVED3195                                1'h0
+   31      R      RESERVED3194                                1'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t reserved_31: 1;
+        const uint32_t reserved_30: 1;
+        const uint32_t reserved_29: 1;
+        const uint32_t reserved_28: 1;
+        const uint32_t reserved_27: 1;
+        const uint32_t reserved_26: 1;
+        const uint32_t reserved_25: 1;
+        const uint32_t reserved_24: 1;
+        const uint32_t reserved_23: 1;
+        const uint32_t reserved_22: 1;
+        const uint32_t reserved_21: 1;
+        const uint32_t reserved_20: 1;
+        const uint32_t reserved_19: 1;
+        const uint32_t reserved_18: 1;
+        const uint32_t reserved_17: 1;
+        const uint32_t reserved_16: 1;
+        const uint32_t reserved_15: 1;
+        const uint32_t reserved_14: 1;
+        const uint32_t reserved_13: 1;
+        const uint32_t reserved_12: 1;
+        const uint32_t reserved_11: 1;
+        const uint32_t reserved_10: 1;
+        const uint32_t reserved_9: 1;
+        const uint32_t reserved_8: 1;
+        const uint32_t reserved_7: 1;
+        const uint32_t reserved_6: 1;
+        const uint32_t reserved_5: 1;
+        const uint32_t reserved_4: 1;
+        const uint32_t reserved_3: 1;
+        const uint32_t reserved_2: 1;
+        const uint32_t reserved_1: 1;
+        const uint32_t reserved_0: 1;
+    } b;
+} TIMER_LAT_CNT_2_FIFO_MET_THRESHOLD_INTR_TypeDef;
+
+
+/* 0x5C
+   0       R/WAC  reg_timer_0_pause                           1'h0
+   1       R/WAC  reg_timer_1_pause                           1'h0
+   2       R/WAC  reg_timer_2_pause                           1'h0
+   3       R/WAC  reg_timer_3_pause                           1'h0
+   4       R/WAC  reg_timer_4_pause                           1'h0
+   5       R/WAC  reg_timer_5_pause                           1'h0
+   6       R/WAC  reg_timer_6_pause                           1'h0
+   7       R/WAC  reg_timer_7_pause                           1'h0
+   8       R/WAC  reg_timer_8_pause                           1'h0
+   9       R      RESERVED3249                                1'h0
+   10      R      RESERVED3248                                1'h0
+   11      R      RESERVED3247                                1'h0
+   12      R      RESERVED3246                                1'h0
+   13      R      RESERVED3245                                1'h0
+   14      R      RESERVED3244                                1'h0
+   15      R      RESERVED3243                                1'h0
+   16      R      RESERVED3242                                1'h0
+   17      R      RESERVED3241                                1'h0
+   18      R      RESERVED3240                                1'h0
+   19      R      RESERVED3239                                1'h0
+   20      R      RESERVED3238                                1'h0
+   21      R      RESERVED3237                                1'h0
+   22      R      RESERVED3236                                1'h0
+   23      R      RESERVED3235                                1'h0
+   24      R      RESERVED3234                                1'h0
+   25      R      RESERVED3233                                1'h0
+   26      R      RESERVED3232                                1'h0
+   27      R      RESERVED3231                                1'h0
+   28      R      RESERVED3230                                1'h0
+   29      R      RESERVED3229                                1'h0
+   30      R      RESERVED3228                                1'h0
+   31      R      RESERVED3227                                1'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t reg_timer_0_pause: 1;
+        uint32_t reg_timer_1_pause: 1;
+        uint32_t reg_timer_2_pause: 1;
+        uint32_t reg_timer_3_pause: 1;
+        uint32_t reg_timer_4_pause: 1;
+        uint32_t reg_timer_5_pause: 1;
+        uint32_t reg_timer_6_pause: 1;
+        uint32_t reg_timer_7_pause: 1;
+        uint32_t reg_timer_8_pause: 1;
+        const uint32_t reserved_22: 1;
+        const uint32_t reserved_21: 1;
+        const uint32_t reserved_20: 1;
+        const uint32_t reserved_19: 1;
+        const uint32_t reserved_18: 1;
+        const uint32_t reserved_17: 1;
+        const uint32_t reserved_16: 1;
+        const uint32_t reserved_15: 1;
+        const uint32_t reserved_14: 1;
+        const uint32_t reserved_13: 1;
+        const uint32_t reserved_12: 1;
+        const uint32_t reserved_11: 1;
+        const uint32_t reserved_10: 1;
+        const uint32_t reserved_9: 1;
+        const uint32_t reserved_8: 1;
+        const uint32_t reserved_7: 1;
+        const uint32_t reserved_6: 1;
+        const uint32_t reserved_5: 1;
+        const uint32_t reserved_4: 1;
+        const uint32_t reserved_3: 1;
+        const uint32_t reserved_2: 1;
+        const uint32_t reserved_1: 1;
+        const uint32_t reserved_0: 1;
+    } b;
+} TIMER_PAUSE_CTRL_TypeDef;
+
+
+/* 0x60
+   0       R/W    reg_timer_0_pause_intr_en                   1'h0
+   1       R/W    reg_timer_1_pause_intr_en                   1'h0
+   2       R/W    reg_timer_2_pause_intr_en                   1'h0
+   3       R/W    reg_timer_3_pause_intr_en                   1'h0
+   4       R/W    reg_timer_4_pause_intr_en                   1'h0
+   5       R/W    reg_timer_5_pause_intr_en                   1'h0
+   6       R/W    reg_timer_6_pause_intr_en                   1'h0
+   7       R/W    reg_timer_7_pause_intr_en                   1'h0
+   8       R/W    reg_timer_8_pause_intr_en                   1'h0
+   9       R      RESERVED3282                                1'h0
+   10      R      RESERVED3281                                1'h0
+   11      R      RESERVED3280                                1'h0
+   12      R      RESERVED3279                                1'h0
+   13      R      RESERVED3278                                1'h0
+   14      R      RESERVED3277                                1'h0
+   15      R      RESERVED3276                                1'h0
+   16      R      RESERVED3275                                1'h0
+   17      R      RESERVED3274                                1'h0
+   18      R      RESERVED3273                                1'h0
+   19      R      RESERVED3272                                1'h0
+   20      R      RESERVED3271                                1'h0
+   21      R      RESERVED3270                                1'h0
+   22      R      RESERVED3269                                1'h0
+   23      R      RESERVED3268                                1'h0
+   24      R      RESERVED3267                                1'h0
+   25      R      RESERVED3266                                1'h0
+   26      R      RESERVED3265                                1'h0
+   27      R      RESERVED3264                                1'h0
+   28      R      RESERVED3263                                1'h0
+   29      R      RESERVED3262                                1'h0
+   30      R      RESERVED3261                                1'h0
+   31      R      RESERVED3260                                1'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t reg_timer_0_pause_intr_en: 1;
+        uint32_t reg_timer_1_pause_intr_en: 1;
+        uint32_t reg_timer_2_pause_intr_en: 1;
+        uint32_t reg_timer_3_pause_intr_en: 1;
+        uint32_t reg_timer_4_pause_intr_en: 1;
+        uint32_t reg_timer_5_pause_intr_en: 1;
+        uint32_t reg_timer_6_pause_intr_en: 1;
+        uint32_t reg_timer_7_pause_intr_en: 1;
+        uint32_t reg_timer_8_pause_intr_en: 1;
+        const uint32_t reserved_22: 1;
+        const uint32_t reserved_21: 1;
+        const uint32_t reserved_20: 1;
+        const uint32_t reserved_19: 1;
+        const uint32_t reserved_18: 1;
+        const uint32_t reserved_17: 1;
+        const uint32_t reserved_16: 1;
+        const uint32_t reserved_15: 1;
+        const uint32_t reserved_14: 1;
+        const uint32_t reserved_13: 1;
+        const uint32_t reserved_12: 1;
+        const uint32_t reserved_11: 1;
+        const uint32_t reserved_10: 1;
+        const uint32_t reserved_9: 1;
+        const uint32_t reserved_8: 1;
+        const uint32_t reserved_7: 1;
+        const uint32_t reserved_6: 1;
+        const uint32_t reserved_5: 1;
+        const uint32_t reserved_4: 1;
+        const uint32_t reserved_3: 1;
+        const uint32_t reserved_2: 1;
+        const uint32_t reserved_1: 1;
+        const uint32_t reserved_0: 1;
+    } b;
+} TIMER_PAUSE_INTR_EN_CTRL_TypeDef;
+
+
+/* 0x64
+   0       R/W1C  reg_timer_0_pause_intr_sts                  1'h0
+   1       R/W1C  reg_timer_1_pause_intr_sts                  1'h0
+   2       R/W1C  reg_timer_2_pause_intr_sts                  1'h0
+   3       R/W1C  reg_timer_3_pause_intr_sts                  1'h0
+   4       R/W1C  reg_timer_4_pause_intr_sts                  1'h0
+   5       R/W1C  reg_timer_5_pause_intr_sts                  1'h0
+   6       R/W1C  reg_timer_6_pause_intr_sts                  1'h0
+   7       R/W1C  reg_timer_7_pause_intr_sts                  1'h0
+   8       R/W1C  reg_timer_8_pause_intr_sts                  1'h0
+   9       R      RESERVED3315                                1'h0
+   10      R      RESERVED3314                                1'h0
+   11      R      RESERVED3313                                1'h0
+   12      R      RESERVED3312                                1'h0
+   13      R      RESERVED3311                                1'h0
+   14      R      RESERVED3310                                1'h0
+   15      R      RESERVED3309                                1'h0
+   16      R      RESERVED3308                                1'h0
+   17      R      RESERVED3307                                1'h0
+   18      R      RESERVED3306                                1'h0
+   19      R      RESERVED3305                                1'h0
+   20      R      RESERVED3304                                1'h0
+   21      R      RESERVED3303                                1'h0
+   22      R      RESERVED3302                                1'h0
+   23      R      RESERVED3301                                1'h0
+   24      R      RESERVED3300                                1'h0
+   25      R      RESERVED3299                                1'h0
+   26      R      RESERVED3298                                1'h0
+   27      R      RESERVED3297                                1'h0
+   28      R      RESERVED3296                                1'h0
+   29      R      RESERVED3295                                1'h0
+   30      R      RESERVED3294                                1'h0
+   31      R      RESERVED3293                                1'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t reg_timer_0_pause_intr_sts: 1;
+        uint32_t reg_timer_1_pause_intr_sts: 1;
+        uint32_t reg_timer_2_pause_intr_sts: 1;
+        uint32_t reg_timer_3_pause_intr_sts: 1;
+        uint32_t reg_timer_4_pause_intr_sts: 1;
+        uint32_t reg_timer_5_pause_intr_sts: 1;
+        uint32_t reg_timer_6_pause_intr_sts: 1;
+        uint32_t reg_timer_7_pause_intr_sts: 1;
+        uint32_t reg_timer_8_pause_intr_sts: 1;
+        const uint32_t reserved_22: 1;
+        const uint32_t reserved_21: 1;
+        const uint32_t reserved_20: 1;
+        const uint32_t reserved_19: 1;
+        const uint32_t reserved_18: 1;
+        const uint32_t reserved_17: 1;
+        const uint32_t reserved_16: 1;
+        const uint32_t reserved_15: 1;
+        const uint32_t reserved_14: 1;
+        const uint32_t reserved_13: 1;
+        const uint32_t reserved_12: 1;
+        const uint32_t reserved_11: 1;
+        const uint32_t reserved_10: 1;
+        const uint32_t reserved_9: 1;
+        const uint32_t reserved_8: 1;
+        const uint32_t reserved_7: 1;
+        const uint32_t reserved_6: 1;
+        const uint32_t reserved_5: 1;
+        const uint32_t reserved_4: 1;
+        const uint32_t reserved_3: 1;
+        const uint32_t reserved_2: 1;
+        const uint32_t reserved_1: 1;
+        const uint32_t reserved_0: 1;
+    } b;
+} TIMER_PAUSE_INTR_STS_TypeDef;
+
+
+/* 0x68
+   0       R      reg_timer_0_pause_intr_sts_masked           1'h0
+   1       R      reg_timer_1_pause_intr_sts_masked           1'h0
+   2       R      reg_timer_2_pause_intr_sts_masked           1'h0
+   3       R      reg_timer_3_pause_intr_sts_masked           1'h0
+   4       R      reg_timer_4_pause_intr_sts_masked           1'h0
+   5       R      reg_timer_5_pause_intr_sts_masked           1'h0
+   6       R      reg_timer_6_pause_intr_sts_masked           1'h0
+   7       R      reg_timer_7_pause_intr_sts_masked           1'h0
+   8       R      reg_timer_8_pause_intr_sts_masked           1'h0
+   9       R      RESERVED3348                                1'h0
+   10      R      RESERVED3347                                1'h0
+   11      R      RESERVED3346                                1'h0
+   12      R      RESERVED3345                                1'h0
+   13      R      RESERVED3344                                1'h0
+   14      R      RESERVED3343                                1'h0
+   15      R      RESERVED3342                                1'h0
+   16      R      RESERVED3341                                1'h0
+   17      R      RESERVED3340                                1'h0
+   18      R      RESERVED3339                                1'h0
+   19      R      RESERVED3338                                1'h0
+   20      R      RESERVED3337                                1'h0
+   21      R      RESERVED3336                                1'h0
+   22      R      RESERVED3335                                1'h0
+   23      R      RESERVED3334                                1'h0
+   24      R      RESERVED3333                                1'h0
+   25      R      RESERVED3332                                1'h0
+   26      R      RESERVED3331                                1'h0
+   27      R      RESERVED3330                                1'h0
+   28      R      RESERVED3329                                1'h0
+   29      R      RESERVED3328                                1'h0
+   30      R      RESERVED3327                                1'h0
+   31      R      RESERVED3326                                1'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t reg_timer_0_pause_intr_sts_masked: 1;
+        const uint32_t reg_timer_1_pause_intr_sts_masked: 1;
+        const uint32_t reg_timer_2_pause_intr_sts_masked: 1;
+        const uint32_t reg_timer_3_pause_intr_sts_masked: 1;
+        const uint32_t reg_timer_4_pause_intr_sts_masked: 1;
+        const uint32_t reg_timer_5_pause_intr_sts_masked: 1;
+        const uint32_t reg_timer_6_pause_intr_sts_masked: 1;
+        const uint32_t reg_timer_7_pause_intr_sts_masked: 1;
+        const uint32_t reg_timer_8_pause_intr_sts_masked: 1;
+        const uint32_t reserved_22: 1;
+        const uint32_t reserved_21: 1;
+        const uint32_t reserved_20: 1;
+        const uint32_t reserved_19: 1;
+        const uint32_t reserved_18: 1;
+        const uint32_t reserved_17: 1;
+        const uint32_t reserved_16: 1;
+        const uint32_t reserved_15: 1;
+        const uint32_t reserved_14: 1;
+        const uint32_t reserved_13: 1;
+        const uint32_t reserved_12: 1;
+        const uint32_t reserved_11: 1;
+        const uint32_t reserved_10: 1;
+        const uint32_t reserved_9: 1;
+        const uint32_t reserved_8: 1;
+        const uint32_t reserved_7: 1;
+        const uint32_t reserved_6: 1;
+        const uint32_t reserved_5: 1;
+        const uint32_t reserved_4: 1;
+        const uint32_t reserved_3: 1;
+        const uint32_t reserved_2: 1;
+        const uint32_t reserved_1: 1;
+        const uint32_t reserved_0: 1;
+    } b;
+} TIMER_PAUSE_INTR_TypeDef;
+
+
+/* 0x6C
+   31:0    R      RESERVED3359                                32'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t reserved_0: 32;
+    } b;
+} TIMER_SHARE_DMY_0_TypeDef;
+
+
+/* 0x70
+   31:0    R      RESERVED3361                                        32'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t reserved_0: 32;
+    } b;
+} TIMER_SHARE_DMY_1_TypeDef;
+
+
+/* 0x74
+   31:0    R      RESERVED3363                                        32'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t reserved_0: 32;
+    } b;
+} TIMER_SHARE_DMY_2_TypeDef;
+
+
+/* 0x78
+   31:0    R      RESERVED3365                                        32'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t reserved_0: 32;
+    } b;
+} TIMER_SHARE_DMY_3_TypeDef;
+
+
+/* 0x7C
+   31:0    R      RESERVED3367                                        32'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t reserved_0: 32;
+    } b;
+} TIMER_SHARE_DMY_4_TypeDef;
+
+
+/* 0x80
+   0       R/W    reg_timer_0_rap_mode                        1'h0
+   1       R/W    reg_timer_1_rap_mode                        1'h0
+   2       R/W    reg_timer_2_rap_mode                        1'h0
+   3       R/W    reg_timer_3_rap_mode                        1'h0
+   4       R/W    reg_timer_4_rap_mode                        1'h0
+   5       R/W    reg_timer_5_rap_mode                        1'h0
+   6       R/W    reg_timer_6_rap_mode                        1'h0
+   7       R/W    reg_timer_7_rap_mode                        1'h0
+   8       R/W    reg_timer_8_rap_mode                        1'h0
+   9       R      RESERVED3453                                1'h0
+   10      R      RESERVED3452                                1'h0
+   11      R      RESERVED3451                                1'h0
+   12      R      RESERVED3450                                1'h0
+   13      R      RESERVED3449                                1'h0
+   14      R      RESERVED3448                                1'h0
+   15      R      RESERVED3447                                1'h0
+   16      R      RESERVED3446                                1'h0
+   17      R      RESERVED3445                                1'h0
+   18      R      RESERVED3444                                1'h0
+   19      R      RESERVED3443                                1'h0
+   20      R      RESERVED3442                                1'h0
+   21      R      RESERVED3441                                1'h0
+   22      R      RESERVED3440                                1'h0
+   23      R      RESERVED3439                                1'h0
+   24      R      RESERVED3438                                1'h0
+   25      R      RESERVED3437                                1'h0
+   26      R      RESERVED3436                                1'h0
+   27      R      RESERVED3435                                1'h0
+   28      R      RESERVED3434                                1'h0
+   29      R      RESERVED3433                                1'h0
+   30      R      RESERVED3432                                1'h0
+   31      R      RESERVED3431                                1'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t reg_timer_0_rap_mode: 1;
+        uint32_t reg_timer_1_rap_mode: 1;
+        uint32_t reg_timer_2_rap_mode: 1;
+        uint32_t reg_timer_3_rap_mode: 1;
+        uint32_t reg_timer_4_rap_mode: 1;
+        uint32_t reg_timer_5_rap_mode: 1;
+        uint32_t reg_timer_6_rap_mode: 1;
+        uint32_t reg_timer_7_rap_mode: 1;
+        uint32_t reg_timer_8_rap_mode: 1;
+        const uint32_t reserved_22: 1;
+        const uint32_t reserved_21: 1;
+        const uint32_t reserved_20: 1;
+        const uint32_t reserved_19: 1;
+        const uint32_t reserved_18: 1;
+        const uint32_t reserved_17: 1;
+        const uint32_t reserved_16: 1;
+        const uint32_t reserved_15: 1;
+        const uint32_t reserved_14: 1;
+        const uint32_t reserved_13: 1;
+        const uint32_t reserved_12: 1;
+        const uint32_t reserved_11: 1;
+        const uint32_t reserved_10: 1;
+        const uint32_t reserved_9: 1;
+        const uint32_t reserved_8: 1;
+        const uint32_t reserved_7: 1;
+        const uint32_t reserved_6: 1;
+        const uint32_t reserved_5: 1;
+        const uint32_t reserved_4: 1;
+        const uint32_t reserved_3: 1;
+        const uint32_t reserved_2: 1;
+        const uint32_t reserved_1: 1;
+        const uint32_t reserved_0: 1;
+    } b;
+} TIMER_RAP_CTRL0_TypeDef;
+
+
+/* 0x84
+   0       R/W    reg_timer_0_rap_task_mode                   1'h0
+   1       R/W    reg_timer_1_rap_task_mode                   1'h0
+   2       R/W    reg_timer_2_rap_task_mode                   1'h0
+   3       R/W    reg_timer_3_rap_task_mode                   1'h0
+   4       R/W    reg_timer_4_rap_task_mode                   1'h0
+   5       R/W    reg_timer_5_rap_task_mode                   1'h0
+   6       R/W    reg_timer_6_rap_task_mode                   1'h0
+   7       R/W    reg_timer_7_rap_task_mode                   1'h0
+   8       R/W    reg_timer_8_rap_task_mode                   1'h0
+   9       R      RESERVED3486                                1'h0
+   10      R      RESERVED3485                                1'h0
+   11      R      RESERVED3484                                1'h0
+   12      R      RESERVED3483                                1'h0
+   13      R      RESERVED3482                                1'h0
+   14      R      RESERVED3481                                1'h0
+   15      R      RESERVED3480                                1'h0
+   16      R      RESERVED3479                                1'h0
+   17      R      RESERVED3478                                1'h0
+   18      R      RESERVED3477                                1'h0
+   19      R      RESERVED3476                                1'h0
+   20      R      RESERVED3475                                1'h0
+   21      R      RESERVED3474                                1'h0
+   22      R      RESERVED3473                                1'h0
+   23      R      RESERVED3472                                1'h0
+   24      R      RESERVED3471                                1'h0
+   25      R      RESERVED3470                                1'h0
+   26      R      RESERVED3469                                1'h0
+   27      R      RESERVED3468                                1'h0
+   28      R      RESERVED3467                                1'h0
+   29      R      RESERVED3466                                1'h0
+   30      R      RESERVED3465                                1'h0
+   31      R      RESERVED3464                                1'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t reg_timer_0_rap_task_mode: 1;
+        uint32_t reg_timer_1_rap_task_mode: 1;
+        uint32_t reg_timer_2_rap_task_mode: 1;
+        uint32_t reg_timer_3_rap_task_mode: 1;
+        uint32_t reg_timer_4_rap_task_mode: 1;
+        uint32_t reg_timer_5_rap_task_mode: 1;
+        uint32_t reg_timer_6_rap_task_mode: 1;
+        uint32_t reg_timer_7_rap_task_mode: 1;
+        uint32_t reg_timer_8_rap_task_mode: 1;
+        const uint32_t reserved_22: 1;
+        const uint32_t reserved_21: 1;
+        const uint32_t reserved_20: 1;
+        const uint32_t reserved_19: 1;
+        const uint32_t reserved_18: 1;
+        const uint32_t reserved_17: 1;
+        const uint32_t reserved_16: 1;
+        const uint32_t reserved_15: 1;
+        const uint32_t reserved_14: 1;
+        const uint32_t reserved_13: 1;
+        const uint32_t reserved_12: 1;
+        const uint32_t reserved_11: 1;
+        const uint32_t reserved_10: 1;
+        const uint32_t reserved_9: 1;
+        const uint32_t reserved_8: 1;
+        const uint32_t reserved_7: 1;
+        const uint32_t reserved_6: 1;
+        const uint32_t reserved_5: 1;
+        const uint32_t reserved_4: 1;
+        const uint32_t reserved_3: 1;
+        const uint32_t reserved_2: 1;
+        const uint32_t reserved_1: 1;
+        const uint32_t reserved_0: 1;
+    } b;
+} TIMER_RAP_CTRL1_TypeDef;
+
+
+/* 0x88
+   0       R/WAC  reg_timer_0_rap_fw_task_start               1'h0
+   1       R/WAC  reg_timer_1_rap_fw_task_start               1'h0
+   2       R/WAC  reg_timer_2_rap_fw_task_start               1'h0
+   3       R/WAC  reg_timer_3_rap_fw_task_start               1'h0
+   4       R/WAC  reg_timer_4_rap_fw_task_start               1'h0
+   5       R/WAC  reg_timer_5_rap_fw_task_start               1'h0
+   6       R/WAC  reg_timer_6_rap_fw_task_start               1'h0
+   7       R/WAC  reg_timer_7_rap_fw_task_start               1'h0
+   8       R/WAC  reg_timer_8_rap_fw_task_start               1'h0
+   9       R      RESERVED3519                                1'h0
+   10      R      RESERVED3518                                1'h0
+   11      R      RESERVED3517                                1'h0
+   12      R      RESERVED3516                                1'h0
+   13      R      RESERVED3515                                1'h0
+   14      R      RESERVED3514                                1'h0
+   15      R      RESERVED3513                                1'h0
+   16      R      RESERVED3512                                1'h0
+   17      R      RESERVED3511                                1'h0
+   18      R      RESERVED3510                                1'h0
+   19      R      RESERVED3509                                1'h0
+   20      R      RESERVED3508                                1'h0
+   21      R      RESERVED3507                                1'h0
+   22      R      RESERVED3506                                1'h0
+   23      R      RESERVED3505                                1'h0
+   24      R      RESERVED3504                                1'h0
+   25      R      RESERVED3503                                1'h0
+   26      R      RESERVED3502                                1'h0
+   27      R      RESERVED3501                                1'h0
+   28      R      RESERVED3500                                1'h0
+   29      R      RESERVED3499                                1'h0
+   30      R      RESERVED3498                                1'h0
+   31      R      RESERVED3497                                1'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t reg_timer_0_rap_fw_task_start: 1;
+        uint32_t reg_timer_1_rap_fw_task_start: 1;
+        uint32_t reg_timer_2_rap_fw_task_start: 1;
+        uint32_t reg_timer_3_rap_fw_task_start: 1;
+        uint32_t reg_timer_4_rap_fw_task_start: 1;
+        uint32_t reg_timer_5_rap_fw_task_start: 1;
+        uint32_t reg_timer_6_rap_fw_task_start: 1;
+        uint32_t reg_timer_7_rap_fw_task_start: 1;
+        uint32_t reg_timer_8_rap_fw_task_start: 1;
+        const uint32_t reserved_22: 1;
+        const uint32_t reserved_21: 1;
+        const uint32_t reserved_20: 1;
+        const uint32_t reserved_19: 1;
+        const uint32_t reserved_18: 1;
+        const uint32_t reserved_17: 1;
+        const uint32_t reserved_16: 1;
+        const uint32_t reserved_15: 1;
+        const uint32_t reserved_14: 1;
+        const uint32_t reserved_13: 1;
+        const uint32_t reserved_12: 1;
+        const uint32_t reserved_11: 1;
+        const uint32_t reserved_10: 1;
+        const uint32_t reserved_9: 1;
+        const uint32_t reserved_8: 1;
+        const uint32_t reserved_7: 1;
+        const uint32_t reserved_6: 1;
+        const uint32_t reserved_5: 1;
+        const uint32_t reserved_4: 1;
+        const uint32_t reserved_3: 1;
+        const uint32_t reserved_2: 1;
+        const uint32_t reserved_1: 1;
+        const uint32_t reserved_0: 1;
+    } b;
+} TIMER_RAP_FW_TSAK_START_TypeDef;
+
+
+/* 0x8C
+   0       R/WAC  reg_timer_0_rap_fw_task_pause               1'h0
+   1       R/WAC  reg_timer_1_rap_fw_task_pause               1'h0
+   2       R/WAC  reg_timer_2_rap_fw_task_pause               1'h0
+   3       R/WAC  reg_timer_3_rap_fw_task_pause               1'h0
+   4       R/WAC  reg_timer_4_rap_fw_task_pause               1'h0
+   5       R/WAC  reg_timer_5_rap_fw_task_pause               1'h0
+   6       R/WAC  reg_timer_6_rap_fw_task_pause               1'h0
+   7       R/WAC  reg_timer_7_rap_fw_task_pause               1'h0
+   8       R/WAC  reg_timer_8_rap_fw_task_pause               1'h0
+   9       R      RESERVED3552                                1'h0
+   10      R      RESERVED3551                                1'h0
+   11      R      RESERVED3550                                1'h0
+   12      R      RESERVED3549                                1'h0
+   13      R      RESERVED3548                                1'h0
+   14      R      RESERVED3547                                1'h0
+   15      R      RESERVED3546                                1'h0
+   16      R      RESERVED3545                                1'h0
+   17      R      RESERVED3544                                1'h0
+   18      R      RESERVED3543                                1'h0
+   19      R      RESERVED3542                                1'h0
+   20      R      RESERVED3541                                1'h0
+   21      R      RESERVED3540                                1'h0
+   22      R      RESERVED3539                                1'h0
+   23      R      RESERVED3538                                1'h0
+   24      R      RESERVED3537                                1'h0
+   25      R      RESERVED3536                                1'h0
+   26      R      RESERVED3535                                1'h0
+   27      R      RESERVED3534                                1'h0
+   28      R      RESERVED3533                                1'h0
+   29      R      RESERVED3532                                1'h0
+   30      R      RESERVED3531                                1'h0
+   31      R      RESERVED3530                                1'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t reg_timer_0_rap_fw_task_pause: 1;
+        uint32_t reg_timer_1_rap_fw_task_pause: 1;
+        uint32_t reg_timer_2_rap_fw_task_pause: 1;
+        uint32_t reg_timer_3_rap_fw_task_pause: 1;
+        uint32_t reg_timer_4_rap_fw_task_pause: 1;
+        uint32_t reg_timer_5_rap_fw_task_pause: 1;
+        uint32_t reg_timer_6_rap_fw_task_pause: 1;
+        uint32_t reg_timer_7_rap_fw_task_pause: 1;
+        uint32_t reg_timer_8_rap_fw_task_pause: 1;
+        const uint32_t reserved_22: 1;
+        const uint32_t reserved_21: 1;
+        const uint32_t reserved_20: 1;
+        const uint32_t reserved_19: 1;
+        const uint32_t reserved_18: 1;
+        const uint32_t reserved_17: 1;
+        const uint32_t reserved_16: 1;
+        const uint32_t reserved_15: 1;
+        const uint32_t reserved_14: 1;
+        const uint32_t reserved_13: 1;
+        const uint32_t reserved_12: 1;
+        const uint32_t reserved_11: 1;
+        const uint32_t reserved_10: 1;
+        const uint32_t reserved_9: 1;
+        const uint32_t reserved_8: 1;
+        const uint32_t reserved_7: 1;
+        const uint32_t reserved_6: 1;
+        const uint32_t reserved_5: 1;
+        const uint32_t reserved_4: 1;
+        const uint32_t reserved_3: 1;
+        const uint32_t reserved_2: 1;
+        const uint32_t reserved_1: 1;
+        const uint32_t reserved_0: 1;
+    } b;
+} TIMER_RAP_FW_TASK_PAUSE_TypeDef;
+
+
+/* 0x90
+   0       R/WAC  reg_timer_0_rap_fw_task_disable             1'h0
+   1       R/WAC  reg_timer_1_rap_fw_task_disable             1'h0
+   2       R/WAC  reg_timer_2_rap_fw_task_disable             1'h0
+   3       R/WAC  reg_timer_3_rap_fw_task_disable             1'h0
+   4       R/WAC  reg_timer_4_rap_fw_task_disable             1'h0
+   5       R/WAC  reg_timer_5_rap_fw_task_disable             1'h0
+   6       R/WAC  reg_timer_6_rap_fw_task_disable             1'h0
+   7       R/WAC  reg_timer_7_rap_fw_task_disable             1'h0
+   8       R/WAC  reg_timer_8_rap_fw_task_disable             1'h0
+   9       R      RESERVED3585                                1'h0
+   10      R      RESERVED3584                                1'h0
+   11      R      RESERVED3583                                1'h0
+   12      R      RESERVED3582                                1'h0
+   13      R      RESERVED3581                                1'h0
+   14      R      RESERVED3580                                1'h0
+   15      R      RESERVED3579                                1'h0
+   16      R      RESERVED3578                                1'h0
+   17      R      RESERVED3577                                1'h0
+   18      R      RESERVED3576                                1'h0
+   19      R      RESERVED3575                                1'h0
+   20      R      RESERVED3574                                1'h0
+   21      R      RESERVED3573                                1'h0
+   22      R      RESERVED3572                                1'h0
+   23      R      RESERVED3571                                1'h0
+   24      R      RESERVED3570                                1'h0
+   25      R      RESERVED3569                                1'h0
+   26      R      RESERVED3568                                1'h0
+   27      R      RESERVED3567                                1'h0
+   28      R      RESERVED3566                                1'h0
+   29      R      RESERVED3565                                1'h0
+   30      R      RESERVED3564                                1'h0
+   31      R      RESERVED3563                                1'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t reg_timer_0_rap_fw_task_disable: 1;
+        uint32_t reg_timer_1_rap_fw_task_disable: 1;
+        uint32_t reg_timer_2_rap_fw_task_disable: 1;
+        uint32_t reg_timer_3_rap_fw_task_disable: 1;
+        uint32_t reg_timer_4_rap_fw_task_disable: 1;
+        uint32_t reg_timer_5_rap_fw_task_disable: 1;
+        uint32_t reg_timer_6_rap_fw_task_disable: 1;
+        uint32_t reg_timer_7_rap_fw_task_disable: 1;
+        uint32_t reg_timer_8_rap_fw_task_disable: 1;
+        const uint32_t reserved_22: 1;
+        const uint32_t reserved_21: 1;
+        const uint32_t reserved_20: 1;
+        const uint32_t reserved_19: 1;
+        const uint32_t reserved_18: 1;
+        const uint32_t reserved_17: 1;
+        const uint32_t reserved_16: 1;
+        const uint32_t reserved_15: 1;
+        const uint32_t reserved_14: 1;
+        const uint32_t reserved_13: 1;
+        const uint32_t reserved_12: 1;
+        const uint32_t reserved_11: 1;
+        const uint32_t reserved_10: 1;
+        const uint32_t reserved_9: 1;
+        const uint32_t reserved_8: 1;
+        const uint32_t reserved_7: 1;
+        const uint32_t reserved_6: 1;
+        const uint32_t reserved_5: 1;
+        const uint32_t reserved_4: 1;
+        const uint32_t reserved_3: 1;
+        const uint32_t reserved_2: 1;
+        const uint32_t reserved_1: 1;
+        const uint32_t reserved_0: 1;
+    } b;
+} TIMER_RAP_FW_TASK_DISABLE_TypeDef;
+
+
+/* 0x94
+   0       R      reg_timer_0_rap_sts_active                  1'h0
+   1       R      reg_timer_1_rap_sts_active                  1'h0
+   2       R      reg_timer_2_rap_sts_active                  1'h0
+   3       R      reg_timer_3_rap_sts_active                  1'h0
+   4       R      reg_timer_4_rap_sts_active                  1'h0
+   5       R      reg_timer_5_rap_sts_active                  1'h0
+   6       R      reg_timer_6_rap_sts_active                  1'h0
+   7       R      reg_timer_7_rap_sts_active                  1'h0
+   8       R      reg_timer_8_rap_sts_active                  1'h0
+   9       R      RESERVED3618                                1'h0
+   10      R      RESERVED3617                                1'h0
+   11      R      RESERVED3616                                1'h0
+   12      R      RESERVED3615                                1'h0
+   13      R      RESERVED3614                                1'h0
+   14      R      RESERVED3613                                1'h0
+   15      R      RESERVED3612                                1'h0
+   16      R      RESERVED3611                                1'h0
+   17      R      RESERVED3610                                1'h0
+   18      R      RESERVED3609                                1'h0
+   19      R      RESERVED3608                                1'h0
+   20      R      RESERVED3607                                1'h0
+   21      R      RESERVED3606                                1'h0
+   22      R      RESERVED3605                                1'h0
+   23      R      RESERVED3604                                1'h0
+   24      R      RESERVED3603                                1'h0
+   25      R      RESERVED3602                                1'h0
+   26      R      RESERVED3601                                1'h0
+   27      R      RESERVED3600                                1'h0
+   28      R      RESERVED3599                                1'h0
+   29      R      RESERVED3598                                1'h0
+   30      R      RESERVED3597                                1'h0
+   31      R      RESERVED3596                                1'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t reg_timer_0_rap_sts_active: 1;
+        const uint32_t reg_timer_1_rap_sts_active: 1;
+        const uint32_t reg_timer_2_rap_sts_active: 1;
+        const uint32_t reg_timer_3_rap_sts_active: 1;
+        const uint32_t reg_timer_4_rap_sts_active: 1;
+        const uint32_t reg_timer_5_rap_sts_active: 1;
+        const uint32_t reg_timer_6_rap_sts_active: 1;
+        const uint32_t reg_timer_7_rap_sts_active: 1;
+        const uint32_t reg_timer_8_rap_sts_active: 1;
+        const uint32_t reserved_22: 1;
+        const uint32_t reserved_21: 1;
+        const uint32_t reserved_20: 1;
+        const uint32_t reserved_19: 1;
+        const uint32_t reserved_18: 1;
+        const uint32_t reserved_17: 1;
+        const uint32_t reserved_16: 1;
+        const uint32_t reserved_15: 1;
+        const uint32_t reserved_14: 1;
+        const uint32_t reserved_13: 1;
+        const uint32_t reserved_12: 1;
+        const uint32_t reserved_11: 1;
+        const uint32_t reserved_10: 1;
+        const uint32_t reserved_9: 1;
+        const uint32_t reserved_8: 1;
+        const uint32_t reserved_7: 1;
+        const uint32_t reserved_6: 1;
+        const uint32_t reserved_5: 1;
+        const uint32_t reserved_4: 1;
+        const uint32_t reserved_3: 1;
+        const uint32_t reserved_2: 1;
+        const uint32_t reserved_1: 1;
+        const uint32_t reserved_0: 1;
+    } b;
+} TIMER_RAP_STS_ACTIVE_TypeDef;
+
+
+/* 0x98
+   0       R/W    reg_timer_0_rap_shortcut_sub_task_pause     1'h0
+   1       R/W    reg_timer_1_rap_shortcut_sub_task_pause     1'h0
+   2       R/W    reg_timer_2_rap_shortcut_sub_task_pause     1'h0
+   3       R/W    reg_timer_3_rap_shortcut_sub_task_pause     1'h0
+   4       R/W    reg_timer_4_rap_shortcut_sub_task_pause     1'h0
+   5       R/W    reg_timer_5_rap_shortcut_sub_task_pause     1'h0
+   6       R/W    reg_timer_6_rap_shortcut_sub_task_pause     1'h0
+   7       R/W    reg_timer_7_rap_shortcut_sub_task_pause     1'h0
+   8       R/W    reg_timer_8_rap_shortcut_sub_task_pause     1'h0
+   9       R      RESERVED3651                                1'h0
+   10      R      RESERVED3650                                1'h0
+   11      R      RESERVED3649                                1'h0
+   12      R      RESERVED3648                                1'h0
+   13      R      RESERVED3647                                1'h0
+   14      R      RESERVED3646                                1'h0
+   15      R      RESERVED3645                                1'h0
+   16      R      RESERVED3644                                1'h0
+   17      R      RESERVED3643                                1'h0
+   18      R      RESERVED3642                                1'h0
+   19      R      RESERVED3641                                1'h0
+   20      R      RESERVED3640                                1'h0
+   21      R      RESERVED3639                                1'h0
+   22      R      RESERVED3638                                1'h0
+   23      R      RESERVED3637                                1'h0
+   24      R      RESERVED3636                                1'h0
+   25      R      RESERVED3635                                1'h0
+   26      R      RESERVED3634                                1'h0
+   27      R      RESERVED3633                                1'h0
+   28      R      RESERVED3632                                1'h0
+   29      R      RESERVED3631                                1'h0
+   30      R      RESERVED3630                                1'h0
+   31      R      RESERVED3629                                1'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t reg_timer_0_rap_shortcut_sub_task_pause: 1;
+        uint32_t reg_timer_1_rap_shortcut_sub_task_pause: 1;
+        uint32_t reg_timer_2_rap_shortcut_sub_task_pause: 1;
+        uint32_t reg_timer_3_rap_shortcut_sub_task_pause: 1;
+        uint32_t reg_timer_4_rap_shortcut_sub_task_pause: 1;
+        uint32_t reg_timer_5_rap_shortcut_sub_task_pause: 1;
+        uint32_t reg_timer_6_rap_shortcut_sub_task_pause: 1;
+        uint32_t reg_timer_7_rap_shortcut_sub_task_pause: 1;
+        uint32_t reg_timer_8_rap_shortcut_sub_task_pause: 1;
+        const uint32_t reserved_22: 1;
+        const uint32_t reserved_21: 1;
+        const uint32_t reserved_20: 1;
+        const uint32_t reserved_19: 1;
+        const uint32_t reserved_18: 1;
+        const uint32_t reserved_17: 1;
+        const uint32_t reserved_16: 1;
+        const uint32_t reserved_15: 1;
+        const uint32_t reserved_14: 1;
+        const uint32_t reserved_13: 1;
+        const uint32_t reserved_12: 1;
+        const uint32_t reserved_11: 1;
+        const uint32_t reserved_10: 1;
+        const uint32_t reserved_9: 1;
+        const uint32_t reserved_8: 1;
+        const uint32_t reserved_7: 1;
+        const uint32_t reserved_6: 1;
+        const uint32_t reserved_5: 1;
+        const uint32_t reserved_4: 1;
+        const uint32_t reserved_3: 1;
+        const uint32_t reserved_2: 1;
+        const uint32_t reserved_1: 1;
+        const uint32_t reserved_0: 1;
+    } b;
+} TIMER_RAP_SHORTCUT_SUB_TASK_PAUSE_TypeDef;
+
+
+/* 0x9C
+   0       R/W    reg_timer_0_rap_shortcut_sub_task_disable   1'h0
+   1       R/W    reg_timer_1_rap_shortcut_sub_task_disable   1'h0
+   2       R/W    reg_timer_2_rap_shortcut_sub_task_disable   1'h0
+   3       R/W    reg_timer_3_rap_shortcut_sub_task_disable   1'h0
+   4       R/W    reg_timer_4_rap_shortcut_sub_task_disable   1'h0
+   5       R/W    reg_timer_5_rap_shortcut_sub_task_disable   1'h0
+   6       R/W    reg_timer_6_rap_shortcut_sub_task_disable   1'h0
+   7       R/W    reg_timer_7_rap_shortcut_sub_task_disable   1'h0
+   8       R/W    reg_timer_8_rap_shortcut_sub_task_disable   1'h0
+   9       R      RESERVED3684                                1'h0
+   10      R      RESERVED3683                                1'h0
+   11      R      RESERVED3682                                1'h0
+   12      R      RESERVED3681                                1'h0
+   13      R      RESERVED3680                                1'h0
+   14      R      RESERVED3679                                1'h0
+   15      R      RESERVED3678                                1'h0
+   16      R      RESERVED3677                                1'h0
+   17      R      RESERVED3676                                1'h0
+   18      R      RESERVED3675                                1'h0
+   19      R      RESERVED3674                                1'h0
+   20      R      RESERVED3673                                1'h0
+   21      R      RESERVED3672                                1'h0
+   22      R      RESERVED3671                                1'h0
+   23      R      RESERVED3670                                1'h0
+   24      R      RESERVED3669                                1'h0
+   25      R      RESERVED3668                                1'h0
+   26      R      RESERVED3667                                1'h0
+   27      R      RESERVED3666                                1'h0
+   28      R      RESERVED3665                                1'h0
+   29      R      RESERVED3664                                1'h0
+   30      R      RESERVED3663                                1'h0
+   31      R      RESERVED3662                                1'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t reg_timer_0_rap_shortcut_sub_task_disable: 1;
+        uint32_t reg_timer_1_rap_shortcut_sub_task_disable: 1;
+        uint32_t reg_timer_2_rap_shortcut_sub_task_disable: 1;
+        uint32_t reg_timer_3_rap_shortcut_sub_task_disable: 1;
+        uint32_t reg_timer_4_rap_shortcut_sub_task_disable: 1;
+        uint32_t reg_timer_5_rap_shortcut_sub_task_disable: 1;
+        uint32_t reg_timer_6_rap_shortcut_sub_task_disable: 1;
+        uint32_t reg_timer_7_rap_shortcut_sub_task_disable: 1;
+        uint32_t reg_timer_8_rap_shortcut_sub_task_disable: 1;
+        const uint32_t reserved_22: 1;
+        const uint32_t reserved_21: 1;
+        const uint32_t reserved_20: 1;
+        const uint32_t reserved_19: 1;
+        const uint32_t reserved_18: 1;
+        const uint32_t reserved_17: 1;
+        const uint32_t reserved_16: 1;
+        const uint32_t reserved_15: 1;
+        const uint32_t reserved_14: 1;
+        const uint32_t reserved_13: 1;
+        const uint32_t reserved_12: 1;
+        const uint32_t reserved_11: 1;
+        const uint32_t reserved_10: 1;
+        const uint32_t reserved_9: 1;
+        const uint32_t reserved_8: 1;
+        const uint32_t reserved_7: 1;
+        const uint32_t reserved_6: 1;
+        const uint32_t reserved_5: 1;
+        const uint32_t reserved_4: 1;
+        const uint32_t reserved_3: 1;
+        const uint32_t reserved_2: 1;
+        const uint32_t reserved_1: 1;
+        const uint32_t reserved_0: 1;
+    } b;
+} TIMER_RAP_SHORTCUT_SUB_TASK_DISABLE_TypeDef;
+
+
+/* 0xA0
+   0       R/W    reg_timer_0_rap_shortcut_pub_event_timereout  1'h0
+   1       R/W    reg_timer_1_rap_shortcut_pub_event_timereout  1'h0
+   2       R/W    reg_timer_2_rap_shortcut_pub_event_timereout  1'h0
+   3       R/W    reg_timer_3_rap_shortcut_pub_event_timereout  1'h0
+   4       R/W    reg_timer_4_rap_shortcut_pub_event_timereout  1'h0
+   5       R/W    reg_timer_5_rap_shortcut_pub_event_timereout  1'h0
+   6       R/W    reg_timer_6_rap_shortcut_pub_event_timereout  1'h0
+   7       R/W    reg_timer_7_rap_shortcut_pub_event_timereout  1'h0
+   8       R/W    reg_timer_8_rap_shortcut_pub_event_timereout  1'h0
+   9       R      RESERVED3717                                1'h0
+   10      R      RESERVED3716                                1'h0
+   11      R      RESERVED3715                                1'h0
+   12      R      RESERVED3714                                1'h0
+   13      R      RESERVED3713                                1'h0
+   14      R      RESERVED3712                                1'h0
+   15      R      RESERVED3711                                1'h0
+   16      R      RESERVED3710                                1'h0
+   17      R      RESERVED3709                                1'h0
+   18      R      RESERVED3708                                1'h0
+   19      R      RESERVED3707                                1'h0
+   20      R      RESERVED3706                                1'h0
+   21      R      RESERVED3705                                1'h0
+   22      R      RESERVED3704                                1'h0
+   23      R      RESERVED3703                                1'h0
+   24      R      RESERVED3702                                1'h0
+   25      R      RESERVED3701                                1'h0
+   26      R      RESERVED3700                                1'h0
+   27      R      RESERVED3699                                1'h0
+   28      R      RESERVED3698                                1'h0
+   29      R      RESERVED3697                                1'h0
+   30      R      RESERVED3696                                1'h0
+   31      R      RESERVED3695                                1'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t reg_timer_0_rap_shortcut_pub_event_timereout: 1;
+        uint32_t reg_timer_1_rap_shortcut_pub_event_timereout: 1;
+        uint32_t reg_timer_2_rap_shortcut_pub_event_timereout: 1;
+        uint32_t reg_timer_3_rap_shortcut_pub_event_timereout: 1;
+        uint32_t reg_timer_4_rap_shortcut_pub_event_timereout: 1;
+        uint32_t reg_timer_5_rap_shortcut_pub_event_timereout: 1;
+        uint32_t reg_timer_6_rap_shortcut_pub_event_timereout: 1;
+        uint32_t reg_timer_7_rap_shortcut_pub_event_timereout: 1;
+        uint32_t reg_timer_8_rap_shortcut_pub_event_timereout: 1;
+        const uint32_t reserved_22: 1;
+        const uint32_t reserved_21: 1;
+        const uint32_t reserved_20: 1;
+        const uint32_t reserved_19: 1;
+        const uint32_t reserved_18: 1;
+        const uint32_t reserved_17: 1;
+        const uint32_t reserved_16: 1;
+        const uint32_t reserved_15: 1;
+        const uint32_t reserved_14: 1;
+        const uint32_t reserved_13: 1;
+        const uint32_t reserved_12: 1;
+        const uint32_t reserved_11: 1;
+        const uint32_t reserved_10: 1;
+        const uint32_t reserved_9: 1;
+        const uint32_t reserved_8: 1;
+        const uint32_t reserved_7: 1;
+        const uint32_t reserved_6: 1;
+        const uint32_t reserved_5: 1;
+        const uint32_t reserved_4: 1;
+        const uint32_t reserved_3: 1;
+        const uint32_t reserved_2: 1;
+        const uint32_t reserved_1: 1;
+        const uint32_t reserved_0: 1;
+    } b;
+} TIMER_RAP_SHORTCUT_PUB_EVENT_TIMEOUT_TypeDef;
+
+
+/* 0xA4
+   31:0    R      RESERVED3728                                32'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t reserved_0: 32;
+    } b;
+} TIMER_RAP_DMY_0_TypeDef;
+
+
+/* 0xA8
+   31:0    R      RESERVED3730                                32'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t reserved_0: 32;
+    } b;
+} TIMER_RAP_DMY_1_TypeDef;
+
+
+/* 0xAC
+   31:0    R      RESERVED3732                                32'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t reserved_0: 32;
+    } b;
+} TIMER_RAP_DMY_2_TypeDef;
+
+
+/* 0xB0
+   31:0    R      reg_timer_ip_ver                            32'h2402206A
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t reg_timer_ip_ver: 32;
+    } b;
+} TIMER_IP_VER_TypeDef;
+
+/* 0xB4
+   31:0    R      RESERVED3674                                32'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t reserved_0: 32;
+    } b;
+} TIMER_SHARE_DMY_5_TypeDef;
+
+
+/* 0xB8
+   31:0    R      RESERVED3676                                32'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t reserved_0: 32;
+    } b;
+} TIMER_SHARE_DMY_6_TypeDef;
+
+
+/* 0xBC
+   31:0    R      RESERVED3678                                32'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t reserved_0: 32;
+    } b;
+} TIMER_SHARE_DMY_7_TypeDef;
+
+/* 0xC0
+   0       R/W    reg_timer_0_q_ch_fw_force_pclk_qactive      1'h0
+   1       R/W    reg_timer_1_q_ch_fw_force_pclk_qactive      1'h0
+   2       R/W    reg_timer_2_q_ch_fw_force_pclk_qactive      1'h0
+   3       R/W    reg_timer_3_q_ch_fw_force_pclk_qactive      1'h0
+   4       R/W    reg_timer_4_q_ch_fw_force_pclk_qactive      1'h0
+   5       R/W    reg_timer_5_q_ch_fw_force_pclk_qactive      1'h0
+   6       R/W    reg_timer_6_q_ch_fw_force_pclk_qactive      1'h0
+   7       R/W    reg_timer_7_q_ch_fw_force_pclk_qactive      1'h0
+   8       R/W    reg_timer_8_q_ch_fw_force_pclk_qactive      1'h0
+   9       R      RESERVED3702                                1'h0
+   10      R      RESERVED3701                                1'h0
+   11      R      RESERVED3700                                1'h0
+   12      R      RESERVED3699                                1'h0
+   13      R      RESERVED3698                                1'h0
+   14      R      RESERVED3697                                1'h0
+   15      R      RESERVED3696                                1'h0
+   16      R      RESERVED3695                                1'h0
+   17      R      RESERVED3694                                1'h0
+   18      R      RESERVED3693                                1'h0
+   19      R      RESERVED3692                                1'h0
+   20      R      RESERVED3691                                1'h0
+   21      R      RESERVED3690                                1'h0
+   22      R      RESERVED3689                                1'h0
+   23      R      RESERVED3688                                1'h0
+   24      R      RESERVED3687                                1'h0
+   25      R      RESERVED3686                                1'h0
+   26      R      RESERVED3685                                1'h0
+   27      R      RESERVED3684                                1'h0
+   28      R      RESERVED3683                                1'h0
+   29      R      RESERVED3682                                1'h0
+   30      R      RESERVED3681                                1'h0
+   31      R      RESERVED3680                                1'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t reg_timer_0_q_ch_fw_force_pclk_qactive: 1;
+        uint32_t reg_timer_1_q_ch_fw_force_pclk_qactive: 1;
+        uint32_t reg_timer_2_q_ch_fw_force_pclk_qactive: 1;
+        uint32_t reg_timer_3_q_ch_fw_force_pclk_qactive: 1;
+        uint32_t reg_timer_4_q_ch_fw_force_pclk_qactive: 1;
+        uint32_t reg_timer_5_q_ch_fw_force_pclk_qactive: 1;
+        uint32_t reg_timer_6_q_ch_fw_force_pclk_qactive: 1;
+        uint32_t reg_timer_7_q_ch_fw_force_pclk_qactive: 1;
+        uint32_t reg_timer_8_q_ch_fw_force_pclk_qactive: 1;
+        const uint32_t reserved_22: 1;
+        const uint32_t reserved_21: 1;
+        const uint32_t reserved_20: 1;
+        const uint32_t reserved_19: 1;
+        const uint32_t reserved_18: 1;
+        const uint32_t reserved_17: 1;
+        const uint32_t reserved_16: 1;
+        const uint32_t reserved_15: 1;
+        const uint32_t reserved_14: 1;
+        const uint32_t reserved_13: 1;
+        const uint32_t reserved_12: 1;
+        const uint32_t reserved_11: 1;
+        const uint32_t reserved_10: 1;
+        const uint32_t reserved_9: 1;
+        const uint32_t reserved_8: 1;
+        const uint32_t reserved_7: 1;
+        const uint32_t reserved_6: 1;
+        const uint32_t reserved_5: 1;
+        const uint32_t reserved_4: 1;
+        const uint32_t reserved_3: 1;
+        const uint32_t reserved_2: 1;
+        const uint32_t reserved_1: 1;
+        const uint32_t reserved_0: 1;
+    } b;
+} TIMER_Q_CH_FW_CTRL0_TypeDef;
+
+/* 0xC4
+   0       R/W    reg_timer_0_clk_q_ch_qactive_fw_manual_data 1'h0
+   1       R/W    reg_timer_0_clk_q_ch_qactive_fw_manual_en   1'h0
+   2       R/W    reg_timer_1_clk_q_ch_qactive_fw_manual_data 1'h0
+   3       R/W    reg_timer_1_clk_q_ch_qactive_fw_manual_en   1'h0
+   4       R/W    reg_timer_2_clk_q_ch_qactive_fw_manual_data 1'h0
+   5       R/W    reg_timer_2_clk_q_ch_qactive_fw_manual_en   1'h0
+   6       R/W    reg_timer_3_clk_q_ch_qactive_fw_manual_data 1'h0
+   7       R/W    reg_timer_3_clk_q_ch_qactive_fw_manual_en   1'h0
+   8       R/W    reg_timer_4_clk_q_ch_qactive_fw_manual_data 1'h0
+   9       R/W    reg_timer_4_clk_q_ch_qactive_fw_manual_en   1'h0
+   10      R/W    reg_timer_5_clk_q_ch_qactive_fw_manual_data 1'h0
+   11      R/W    reg_timer_5_clk_q_ch_qactive_fw_manual_en   1'h0
+   12      R/W    reg_timer_6_clk_q_ch_qactive_fw_manual_data 1'h0
+   13      R/W    reg_timer_6_clk_q_ch_qactive_fw_manual_en   1'h0
+   14      R/W    reg_timer_7_clk_q_ch_qactive_fw_manual_data 1'h0
+   15      R/W    reg_timer_7_clk_q_ch_qactive_fw_manual_en   1'h0
+   16      R/W    reg_timer_8_clk_q_ch_qactive_fw_manual_data 1'h0
+   17      R/W    reg_timer_8_clk_q_ch_qactive_fw_manual_en   1'h0
+   18      R      RESERVED3726                                1'h0
+   19      R      RESERVED3725                                1'h0
+   20      R      RESERVED3724                                1'h0
+   21      R      RESERVED3723                                1'h0
+   22      R      RESERVED3722                                1'h0
+   23      R      RESERVED3721                                1'h0
+   24      R      RESERVED3720                                1'h0
+   25      R      RESERVED3719                                1'h0
+   26      R      RESERVED3718                                1'h0
+   27      R      RESERVED3717                                1'h0
+   28      R      RESERVED3716                                1'h0
+   29      R      RESERVED3715                                1'h0
+   30      R      RESERVED3714                                1'h0
+   31      R      RESERVED3713                                1'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t reg_timer_0_clk_q_ch_qactive_fw_manual_data: 1;
+        uint32_t reg_timer_0_clk_q_ch_qactive_fw_manual_en: 1;
+        uint32_t reg_timer_1_clk_q_ch_qactive_fw_manual_data: 1;
+        uint32_t reg_timer_1_clk_q_ch_qactive_fw_manual_en: 1;
+        uint32_t reg_timer_2_clk_q_ch_qactive_fw_manual_data: 1;
+        uint32_t reg_timer_2_clk_q_ch_qactive_fw_manual_en: 1;
+        uint32_t reg_timer_3_clk_q_ch_qactive_fw_manual_data: 1;
+        uint32_t reg_timer_3_clk_q_ch_qactive_fw_manual_en: 1;
+        uint32_t reg_timer_4_clk_q_ch_qactive_fw_manual_data: 1;
+        uint32_t reg_timer_4_clk_q_ch_qactive_fw_manual_en: 1;
+        uint32_t reg_timer_5_clk_q_ch_qactive_fw_manual_data: 1;
+        uint32_t reg_timer_5_clk_q_ch_qactive_fw_manual_en: 1;
+        uint32_t reg_timer_6_clk_q_ch_qactive_fw_manual_data: 1;
+        uint32_t reg_timer_6_clk_q_ch_qactive_fw_manual_en: 1;
+        uint32_t reg_timer_7_clk_q_ch_qactive_fw_manual_data: 1;
+        uint32_t reg_timer_7_clk_q_ch_qactive_fw_manual_en: 1;
+        uint32_t reg_timer_8_clk_q_ch_qactive_fw_manual_data: 1;
+        uint32_t reg_timer_8_clk_q_ch_qactive_fw_manual_en: 1;
+        const uint32_t reserved_13: 1;
+        const uint32_t reserved_12: 1;
+        const uint32_t reserved_11: 1;
+        const uint32_t reserved_10: 1;
+        const uint32_t reserved_9: 1;
+        const uint32_t reserved_8: 1;
+        const uint32_t reserved_7: 1;
+        const uint32_t reserved_6: 1;
+        const uint32_t reserved_5: 1;
+        const uint32_t reserved_4: 1;
+        const uint32_t reserved_3: 1;
+        const uint32_t reserved_2: 1;
+        const uint32_t reserved_1: 1;
+        const uint32_t reserved_0: 1;
+    } b;
+} TIMER_Q_CH_FW_CTRL1_TypeDef;
+
+/* 0xC8
+   0       R      RESERVED3777                                1'h0
+   1       R      RESERVED3776                                1'h0
+   2       R      RESERVED3775                                1'h0
+   3       R      RESERVED3774                                1'h0
+   4       R      RESERVED3773                                1'h0
+   5       R      RESERVED3772                                1'h0
+   6       R      RESERVED3771                                1'h0
+   7       R      RESERVED3770                                1'h0
+   8       R      RESERVED3769                                1'h0
+   9       R      RESERVED3768                                1'h0
+   10      R      RESERVED3767                                1'h0
+   11      R      RESERVED3766                                1'h0
+   12      R      RESERVED3765                                1'h0
+   13      R      RESERVED3764                                1'h0
+   14      R      RESERVED3763                                1'h0
+   15      R      RESERVED3762                                1'h0
+   16      R      RESERVED3761                                1'h0
+   17      R      RESERVED3760                                1'h0
+   18      R      RESERVED3759                                1'h0
+   19      R      RESERVED3758                                1'h0
+   20      R      RESERVED3757                                1'h0
+   21      R      RESERVED3756                                1'h0
+   22      R      RESERVED3755                                1'h0
+   23      R      RESERVED3754                                1'h0
+   24      R      RESERVED3753                                1'h0
+   25      R      RESERVED3752                                1'h0
+   26      R      RESERVED3751                                1'h0
+   27      R      RESERVED3750                                1'h0
+   28      R      RESERVED3749                                1'h0
+   29      R      RESERVED3748                                1'h0
+   30      R      RESERVED3747                                1'h0
+   31      R      RESERVED3746                                1'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t reserved_31: 1;
+        const uint32_t reserved_30: 1;
+        const uint32_t reserved_29: 1;
+        const uint32_t reserved_28: 1;
+        const uint32_t reserved_27: 1;
+        const uint32_t reserved_26: 1;
+        const uint32_t reserved_25: 1;
+        const uint32_t reserved_24: 1;
+        const uint32_t reserved_23: 1;
+        const uint32_t reserved_22: 1;
+        const uint32_t reserved_21: 1;
+        const uint32_t reserved_20: 1;
+        const uint32_t reserved_19: 1;
+        const uint32_t reserved_18: 1;
+        const uint32_t reserved_17: 1;
+        const uint32_t reserved_16: 1;
+        const uint32_t reserved_15: 1;
+        const uint32_t reserved_14: 1;
+        const uint32_t reserved_13: 1;
+        const uint32_t reserved_12: 1;
+        const uint32_t reserved_11: 1;
+        const uint32_t reserved_10: 1;
+        const uint32_t reserved_9: 1;
+        const uint32_t reserved_8: 1;
+        const uint32_t reserved_7: 1;
+        const uint32_t reserved_6: 1;
+        const uint32_t reserved_5: 1;
+        const uint32_t reserved_4: 1;
+        const uint32_t reserved_3: 1;
+        const uint32_t reserved_2: 1;
+        const uint32_t reserved_1: 1;
+        const uint32_t reserved_0: 1;
+    } b;
+} TIMER_Q_CH_QACTIVE_FW_CTRL2_TypeDef;
+
+/* 0xCC
+   0       R/W    reg_timer_0_clk_pwm_dz_q_ch_qactive_fw_manual_data  1'h0
+   1       R/W    reg_timer_0_clk_pwm_dz_q_ch_qactive_fw_manual_en    1'h0
+   2       R      RESERVED3808                                        1'h0
+   3       R      RESERVED3807                                        1'h0
+   4       R      RESERVED3806                                        1'h0
+   5       R      RESERVED3805                                        1'h0
+   6       R      RESERVED3804                                        1'h0
+   7       R      RESERVED3803                                        1'h0
+   8       R      RESERVED3802                                        1'h0
+   9       R      RESERVED3801                                        1'h0
+   10      R      RESERVED3800                                        1'h0
+   11      R      RESERVED3799                                        1'h0
+   12      R      RESERVED3798                                        1'h0
+   13      R      RESERVED3797                                        1'h0
+   14      R      RESERVED3796                                        1'h0
+   15      R      RESERVED3795                                        1'h0
+   16      R      RESERVED3794                                        1'h0
+   17      R      RESERVED3793                                        1'h0
+   18      R      RESERVED3792                                        1'h0
+   19      R      RESERVED3791                                        1'h0
+   20      R      RESERVED3790                                        1'h0
+   21      R      RESERVED3789                                        1'h0
+   22      R      RESERVED3788                                        1'h0
+   23      R      RESERVED3787                                        1'h0
+   24      R      RESERVED3786                                        1'h0
+   25      R      RESERVED3785                                        1'h0
+   26      R      RESERVED3784                                        1'h0
+   27      R      RESERVED3783                                        1'h0
+   28      R      RESERVED3782                                        1'h0
+   29      R      RESERVED3781                                        1'h0
+   30      R      RESERVED3780                                        1'h0
+   31      R      RESERVED3779                                        1'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t reg_timer_0_clk_pwm_dz_q_ch_qactive_fw_manual_data: 1;
+        uint32_t reg_timer_0_clk_pwm_dz_q_ch_qactive_fw_manual_en: 1;
+        const uint32_t reserved_29: 1;
+        const uint32_t reserved_28: 1;
+        const uint32_t reserved_27: 1;
+        const uint32_t reserved_26: 1;
+        const uint32_t reserved_25: 1;
+        const uint32_t reserved_24: 1;
+        const uint32_t reserved_23: 1;
+        const uint32_t reserved_22: 1;
+        const uint32_t reserved_21: 1;
+        const uint32_t reserved_20: 1;
+        const uint32_t reserved_19: 1;
+        const uint32_t reserved_18: 1;
+        const uint32_t reserved_17: 1;
+        const uint32_t reserved_16: 1;
+        const uint32_t reserved_15: 1;
+        const uint32_t reserved_14: 1;
+        const uint32_t reserved_13: 1;
+        const uint32_t reserved_12: 1;
+        const uint32_t reserved_11: 1;
+        const uint32_t reserved_10: 1;
+        const uint32_t reserved_9: 1;
+        const uint32_t reserved_8: 1;
+        const uint32_t reserved_7: 1;
+        const uint32_t reserved_6: 1;
+        const uint32_t reserved_5: 1;
+        const uint32_t reserved_4: 1;
+        const uint32_t reserved_3: 1;
+        const uint32_t reserved_2: 1;
+        const uint32_t reserved_1: 1;
+        const uint32_t reserved_0: 1;
+    } b;
+} TIMER_Q_CH_QACTIVE_FW_CTRL3_TypeDef;
+
+/* 0xD0
+   0       R      RESERVED3843                                1'h0
+   1       R      RESERVED3842                                1'h0
+   2       R      RESERVED3841                                1'h0
+   3       R      RESERVED3840                                1'h0
+   4       R      RESERVED3839                                1'h0
+   5       R      RESERVED3838                                1'h0
+   6       R      RESERVED3837                                1'h0
+   7       R      RESERVED3836                                1'h0
+   8       R      RESERVED3835                                1'h0
+   9       R      RESERVED3834                                1'h0
+   10      R      RESERVED3833                                1'h0
+   11      R      RESERVED3832                                1'h0
+   12      R      RESERVED3831                                1'h0
+   13      R      RESERVED3830                                1'h0
+   14      R      RESERVED3829                                1'h0
+   15      R      RESERVED3828                                1'h0
+   16      R      RESERVED3827                                1'h0
+   17      R      RESERVED3826                                1'h0
+   18      R      RESERVED3825                                1'h0
+   19      R      RESERVED3824                                1'h0
+   20      R      RESERVED3823                                1'h0
+   21      R      RESERVED3822                                1'h0
+   22      R      RESERVED3821                                1'h0
+   23      R      RESERVED3820                                1'h0
+   24      R      RESERVED3819                                1'h0
+   25      R      RESERVED3818                                1'h0
+   26      R      RESERVED3817                                1'h0
+   27      R      RESERVED3816                                1'h0
+   28      R      RESERVED3815                                1'h0
+   29      R      RESERVED3814                                1'h0
+   30      R      RESERVED3813                                1'h0
+   31      R      RESERVED3812                                1'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t reserved_31: 1;
+        const uint32_t reserved_30: 1;
+        const uint32_t reserved_29: 1;
+        const uint32_t reserved_28: 1;
+        const uint32_t reserved_27: 1;
+        const uint32_t reserved_26: 1;
+        const uint32_t reserved_25: 1;
+        const uint32_t reserved_24: 1;
+        const uint32_t reserved_23: 1;
+        const uint32_t reserved_22: 1;
+        const uint32_t reserved_21: 1;
+        const uint32_t reserved_20: 1;
+        const uint32_t reserved_19: 1;
+        const uint32_t reserved_18: 1;
+        const uint32_t reserved_17: 1;
+        const uint32_t reserved_16: 1;
+        const uint32_t reserved_15: 1;
+        const uint32_t reserved_14: 1;
+        const uint32_t reserved_13: 1;
+        const uint32_t reserved_12: 1;
+        const uint32_t reserved_11: 1;
+        const uint32_t reserved_10: 1;
+        const uint32_t reserved_9: 1;
+        const uint32_t reserved_8: 1;
+        const uint32_t reserved_7: 1;
+        const uint32_t reserved_6: 1;
+        const uint32_t reserved_5: 1;
+        const uint32_t reserved_4: 1;
+        const uint32_t reserved_3: 1;
+        const uint32_t reserved_2: 1;
+        const uint32_t reserved_1: 1;
+        const uint32_t reserved_0: 1;
+    } b;
+} TIMER_Q_CH_QACTIVE_FW_CTRL4_TypeDef;
+
+/* 0xD4
+   0       R/W    reg_timer_pclk_q_ch_qactive_fw_manual_data          1'h0
+   1       R/W    reg_timer_pclk_q_ch_qactive_fw_manual_en            1'h0
+   2       R/W    reg_timer_apb_brg_pclk_q_ch_qactive_fw_manual_data  1'h0
+   3       R/W    reg_timer_apb_brg_pclk_q_ch_qactive_fw_manual_en    1'h0
+   31:4    R      reserved3845                                        28'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t reg_timer_pclk_q_ch_qactive_fw_manual_data: 1;
+        uint32_t reg_timer_pclk_q_ch_qactive_fw_manual_en: 1;
+        uint32_t reg_timer_apb_brg_pclk_q_ch_qactive_fw_manual_data: 1;
+        uint32_t reg_timer_apb_brg_pclk_q_ch_qactive_fw_manual_en: 1;
+        const uint32_t reserved_0: 30;
+    } b;
+} TIMER_Q_CH_QACTIVE_FW_CTRL5_TypeDef;
+
+/*============================================================================*
+ *                          TIMER Constants
+ *============================================================================*/
+/** \defgroup TIMER         TIMER
+  * \brief
+  * \{
+  */
+
+/** \defgroup TIMER_Exported_Constants TIMER Exported Constants
+  * \brief
+  * \{
+  */
+
+/**
+ * \defgroup    TIMER_CASE TIMER CASE
+ * \{
+ * \ingroup     TIMER_Exported_Constants
+ */
+typedef enum
+{
+    TIMER_CASE1 = 1,
+    TIMER_CASE7 = 2,
+    TIMER_CASE6 = 3,
+    TIMER_CASE2 = 4,
+    TIMER_CASE3 = 5,
+    TIMER_CASE4 = 6,
+    TIMER_CASE5 = 7,
+} TIMERCASE_TypeDef;
+/** End of TIMER_CASE
+  * \}
+  */
+
+/**
+ * \defgroup    TIMER_Clock_Source TIMER Clock Source
+ * \{
+ * \ingroup     TIMER_Exported_Constants
+ */
+typedef enum
+{
+    TIMER_CLOCK_SRC_40M = 0,
+} TIMERClockSrc_TypeDef;
+
+#define IS_TIMER_CLOCK_SRC(CLOCK)     (((CLOCK) == TIMER_CLOCK_SRC_40M))
+
+/** End of TIMER_Clock_Source
+  * \}
+  */
+
+/**
+ * \defgroup    TIMER_Clock_Divider TIMER Clock Divider
+ * \{
+ * \ingroup     TIMER_Exported_Constants
+ */
+typedef enum
+{
+    TIMER_CLOCK_DIV_1 = 0x0,
+    TIMER_CLOCK_DIV_2 = 0x1,
+    TIMER_CLOCK_DIV_4 = 0x2,
+    TIMER_CLOCK_DIV_8 = 0x3,
+    TIMER_CLOCK_DIV_16 = 0x4,
+    TIMER_CLOCK_DIV_32 = 0x5,
+    TIMER_CLOCK_DIV_40 = 0x6,
+    TIMER_CLOCK_DIV_64 = 0x7,
+} TIMERClockDiv_TypeDef;
+
+#define IS_TIMER_CLOCK_DIV(DIV) (((DIV) == TIMER_CLOCK_DIV_1) || \
+                                 ((DIV) == TIMER_CLOCK_DIV_2) || \
+                                 ((DIV) == TIMER_CLOCK_DIV_4) || \
+                                 ((DIV) == TIMER_CLOCK_DIV_8) || \
+                                 ((DIV) == TIMER_CLOCK_DIV_16) || \
+                                 ((DIV) == TIMER_CLOCK_DIV_32) || \
+                                 ((DIV) == TIMER_CLOCK_DIV_40) || \
+                                 ((DIV) == TIMER_CLOCK_DIV_64))
+
+/** End of TIMER_Clock_Divider
+  * \}
+  */
+
+/**
+ * \defgroup    PWM_DZ_Clock_Divider PWM DZ Clock Divider
+ * \{
+ * \ingroup     TIMER_Exported_Constants
+ */
+typedef enum
+{
+    PWM_DZ_CLOCK_DIV_1 = 0x0,
+    PWM_DZ_CLOCK_DIV_2 = 0x1,
+    PWM_DZ_CLOCK_DIV_4 = 0x2,
+    PWM_DZ_CLOCK_DIV_8 = 0x3,
+    PWM_DZ_CLOCK_DIV_16 = 0x4,
+    PWM_DZ_CLOCK_DIV_32 = 0x5,
+    PWM_DZ_CLOCK_DIV_40 = 0x6,
+    PWM_DZ_CLOCK_DIV_64 = 0x7,
+} PWMDZClockDiv_TypeDef;
+
+#define IS_PWM_DZ_CLOCK_DIV(DIV) (((DIV) == PWM_DZ_CLOCK_DIV_1) || \
+                                  ((DIV) == PWM_DZ_CLOCK_DIV_2) || \
+                                  ((DIV) == PWM_DZ_CLOCK_DIV_4) || \
+                                  ((DIV) == PWM_DZ_CLOCK_DIV_8) || \
+                                  ((DIV) == PWM_DZ_CLOCK_DIV_16) || \
+                                  ((DIV) == PWM_DZ_CLOCK_DIV_32) || \
+                                  ((DIV) == PWM_DZ_CLOCK_DIV_40) || \
+                                  ((DIV) == PWM_DZ_CLOCK_DIV_64))
+
+/** End of PWM_DZ_Clock_Divider
+  * \}
+  */
+
+/**
+ * \defgroup    PWM_DeadZone_Clock_Source PWM DeadZone Clock Source
+ * \{
+ * \ingroup     TIMER_Exported_Constants
+ */
+typedef enum
+{
+    PWM_DZ_CLOCK_SRC_TIMER = 0x0,
+    PWM_DZ_CLOCK_SRC_32K   = 0x1,
+} PWMDZClockSrc_TypeDef;
+
+#define IS_PWM_DEADZONE_CLOCK_SRC(CLOCK) (((CLOCK) == PWM_DZ_CLOCK_SRC_TIMER) || \
+                                          ((CLOCK) == PWM_DZ_CLOCK_SRC_32K))
+
+/** End of PWM_DeadZone_Clock_Source
+  * \}
+  */
+
+/** End of TIMER_Exported_Constants
+  * \}
+  */
+
+/** End of TIMER
+  * \}
+  */
+
+#ifdef  __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* RTL_TIMER_DEF_H */
+
+
diff --git a/bee/drivers/timer/src/device/rtl_common/rtl_timer.c b/bee/drivers/timer/src/device/rtl_common/rtl_timer.c
new file mode 100644
index 00000000..7744ba9d
--- /dev/null
+++ b/bee/drivers/timer/src/device/rtl_common/rtl_timer.c
@@ -0,0 +1,949 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *                           Header Files
+ *============================================================================*/
+#include "rtl_timer.h"
+#include "rtl_rcc.h"
+
+/*============================================================================*
+ *                           Private Functions
+ *============================================================================*/
+extern uint32_t TIMER_GetTimerID(TIMER_TypeDef *TIMERx);
+extern TIMERCASE_TypeDef TIMER_GetTimerCase(TIMER_TypeDef *TIMERx);
+extern TIMER_ShareTypeDef *TIMER_GetTimerShareBase(TIMER_TypeDef *TIMERx);
+extern void TIMER_SetPWMDZClock(TIMER_TypeDef *TIMERx, uint16_t ClockSrc, uint16_t ClockDiv);
+extern void TIMER_DynamicConfigCmd(TIMER_TypeDef *TIMERx, FunctionalState Newstate);
+
+#if (TIMER_SUPPORT_LATCH_CNT_0 == 1)
+extern void TIMER_SetLatchTriggerPad(TIMER_TypeDef *TIMERx, uint8_t Pin_num);
+extern void TIMER_LatchDebCmd(TIMER_TypeDef *TIMERx, FunctionalState Newstate);
+extern void TIMER_SetLatchDebClock(TIMER_TypeDef *TIMERx, uint16_t ClockSrc, uint16_t ClockDiv,
+                                   uint16_t CountLimit);
+#endif
+
+
+/*============================================================================*
+ *                           Public Functions
+ *============================================================================*/
+/**
+  * \brief  Deinitializes the TIMERx peripheral registers to their default reset values.
+  * \param  TIMERx: Select the TIMER peripheral. \ref TIMER_Declaration
+  * \return None
+  */
+void TIMER_DeInit(TIMER_TypeDef *TIMERx)
+{
+    /* Check the parameters */
+    assert_param(IS_TIMER_ALL_PERIPH(TIMERx));
+
+    /* Disable timer IP clock and function */
+#ifdef IS_TIMER0_PERIPH
+    if (IS_TIMER0_PERIPH(TIMERx))
+    {
+        RCC_ClockCmd(TIMER0_CLOCK, DISABLE);
+    }
+#endif
+#ifdef IS_TIMER1_PERIPH
+    if (IS_TIMER1_PERIPH(TIMERx))
+    {
+        RCC_ClockCmd(TIMER1_CLOCK, DISABLE);
+    }
+#endif
+#ifdef IS_TIMER2_PERIPH
+    if (IS_TIMER2_PERIPH(TIMERx))
+    {
+        RCC_ClockCmd(TIMER2_CLOCK, DISABLE);
+    }
+#endif
+}
+
+/**
+  * \brief  Initializes the TIMERx Time Base Unit peripheral according to
+  *         the specified parameters in the TIMER_InitStruct.
+  * \param  TIMERx: Select the TIMER peripheral. \ref TIMER_Declaration
+  * \param  TIMER_InitStruct: pointer to a TIMER_TimeBaseInitTypeDef
+  *         structure that contains the configuration information for the
+  *         specified TIMER peripheral.
+  * \return None
+  */
+void TIMER_TimeBaseInit(TIMER_TypeDef *TIMERx, TIMER_TimeBaseInitTypeDef *TIMER_InitStruct)
+{
+    /* Check the parameters */
+    assert_param(IS_TIMER_ALL_PERIPH(TIMERx));
+    assert_param(IS_TIMER_MODE(TIMER_InitStruct->TIMER_Mode));
+    assert_param(IS_PWM_DeadZone_En(TIMER_InitStruct->PWMDeadZone_En));
+
+    TIMERCASE_TypeDef timercase = TIMER_GetTimerCase(TIMERx);
+
+    /* Clock source config */
+    TIMER_SetClock(TIMERx,
+                   TIMER_InitStruct->TIMER_ClockSrc,
+                   TIMER_InitStruct->TIMER_ClockDiv);
+
+#if (TIMER_SUPPORT_AUTO_CLOCK == 1)
+    /* Dynamic Config CCR & MAX_CNT */
+    TIMER_DynamicConfigCmd(TIMERx, TIMER_InitStruct->TIMER_DynConfigEn);
+#endif
+
+    /* Set timer mode */
+    TIMER_MODE_CFG_TypeDef timer_0x04 = {.d32 = TIMERx->TIMER_MODE_CFG};
+    timer_0x04.b.reg_timer_mode = TIMER_InitStruct->TIMER_Mode;
+    timer_0x04.b.reg_timer_oneshot_mode_en = TIMER_InitStruct->TIMER_OneShotEn;
+    TIMERx->TIMER_MODE_CFG = timer_0x04.d32;
+
+    if (TIMER_InitStruct->TIMER_Mode == TIMER_MODE_FREERUN)
+    {
+        if (timercase >= TIMER_CASE4)
+        {
+#if (TIMER_SUPPORT_LATCH_CNT_0 == 1)
+            /* Config latch0 function. */
+            TIMER_LAT_CNT_0_CFG_TypeDef timer_0x1C = {.d32 = TIMERx->TIMER_LAT_CNT_0_CFG};
+            timer_0x1C.b.reg_timer_latch_cnt_0_en = TIMER_InitStruct->TIMER_Latch.TIMER_LatchEn[0];
+            timer_0x1C.b.reg_timer_latch_cnt_0_trig_mode =
+                TIMER_InitStruct->TIMER_Latch.TIMER_LatchTriggerMode[0];
+            timer_0x1C.b.reg_timer_latch_cnt_0_fifo_th = TIMER_InitStruct->TIMER_Latch.TIMER_LatchThreshold;
+            TIMERx->TIMER_LAT_CNT_0_CFG = timer_0x1C.d32;
+
+            /* Config latch0 trigger. */
+            if (TIMER_InitStruct->TIMER_Latch.TIMER_LatchEn[0] == ENABLE)
+            {
+                TIMER_SetLatchTriggerPad(TIMERx, TIMER_InitStruct->TIMER_Latch.TIMER_LatchTriggerPad);
+            }
+            /* Config latch0 trigger debounce. */
+            if (TIMER_InitStruct->TIMER_Latch.TIMER_LatchDebEn == ENABLE)
+            {
+                TIMER_LatchDebCmd(TIMERx, ENABLE);
+                TIMER_SetLatchDebClock(TIMERx, TIMER_CLOCK_SRC_40M,
+                                       TIMER_InitStruct->TIMER_Latch.TIMER_LatchDebClockDiv,
+                                       TIMER_InitStruct->TIMER_Latch.TIMER_LatchDebCountLimit);
+            }
+            else
+            {
+                TIMER_LatchDebCmd(TIMERx, DISABLE);
+            }
+#endif
+            if (timercase >= TIMER_CASE5)
+            {
+#if (TIMER_SUPPORT_LATCH_CNT_1 == 1)
+                /* Config latch1 function. */
+                TIMER_LAT_CNT_1_CFG_TypeDef timer_0x28 = {.d32 = TIMERx->TIMER_LAT_CNT_1_CFG};
+                timer_0x28.b.reg_timer_latch_cnt_1_en = TIMER_InitStruct->TIMER_Latch.TIMER_LatchEn[1];
+                timer_0x28.b.reg_timer_latch_cnt_1_trig_mode =
+                    TIMER_InitStruct->TIMER_Latch.TIMER_LatchTriggerMode[1];
+                TIMERx->TIMER_LAT_CNT_1_CFG = timer_0x28.d32;
+
+#endif
+#if (TIMER_SUPPORT_LATCH_CNT_2 == 1)
+                /* Config latch2 function. */
+                TIMER_LAT_CNT_2_CFG_TypeDef timer_0x34 = {.d32 = TIMERx->TIMER_LAT_CNT_2_CFG};
+                timer_0x34.b.reg_timer_latch_cnt_2_en = TIMER_InitStruct->TIMER_Latch.TIMER_LatchEn[2];
+                timer_0x34.b.reg_timer_latch_cnt_2_trig_mode =
+                    TIMER_InitStruct->TIMER_Latch.TIMER_LatchTriggerMode[2];
+                TIMERx->TIMER_LAT_CNT_2_CFG = timer_0x34.d32;
+#endif
+            }
+        }
+    }
+    else if ((TIMER_InitStruct->TIMER_Mode == TIMER_MODE_USERDEFINE) ||
+             (TIMER_InitStruct->TIMER_Mode == TIMER_MODE_USERDEFINE_AUTO))
+    {
+        /* set timer period */
+        TIMERx->TIMER_MAX_CNT = TIMER_InitStruct->TIMER_Period;
+
+#if (TIMER_SUPPORT_PWM_FUNCTION == 1)
+        if (timercase >= TIMER_CASE7)
+        {
+            TIMER_PWM_CFG_TypeDef timer_0x14 = {.d32 = TIMERx->TIMER_PWM_CFG};
+            if (TIMER_InitStruct->PWM_En == DISABLE)
+            {
+                timer_0x14.b.reg_timer_pwm_en = DISABLE;
+                TIMERx->TIMER_PWM_CFG = timer_0x14.d32;
+            }
+            else
+            {
+                timer_0x14.b.reg_timer_pwm_en = ENABLE;
+                timer_0x14.b.reg_timer_pwm_polarity = TIMER_InitStruct->PWM_Polarity;
+                timer_0x14.b.reg_timer_pwm_open_drain_en = TIMER_InitStruct->PWM_OutputMode;
+                TIMERx->TIMER_PWM_CFG = timer_0x14.d32;
+
+                /* set pwm high count */
+                if (TIMER_InitStruct->TIMER_Mode == TIMER_MODE_USERDEFINE)
+                {
+                    if (TIMER_InitStruct->PWM_HighCount > TIMER_InitStruct->TIMER_Period)
+                    {
+                        TIMER_InitStruct->PWM_HighCount = TIMER_InitStruct->TIMER_Period;
+                    }
+                    if (TIMER_InitStruct->PWM_Polarity == PWM_POLARITY_HIGH)
+                    {
+                        TIMERx->TIMER_CCR = ((TIMER_InitStruct->TIMER_Period) - \
+                                             (TIMER_InitStruct->PWM_HighCount));
+                    }
+                    else
+                    {
+                        TIMERx->TIMER_CCR = TIMER_InitStruct->PWM_HighCount;
+                    }
+                }
+            }
+        }
+#endif
+    }
+
+#if (TIMER_SUPPORT_PWM_DEADZONE == 1)
+    if (timercase >= TIMER_CASE6)
+    {
+        /* Config PWM Deadzone */
+        if (TIMER_InitStruct->PWM_DZ.PWM_DZEn == ENABLE)
+        {
+            /* Set deadzone clock source and div */
+            TIMER_SetPWMDZClock(TIMERx, \
+                                TIMER_InitStruct->PWM_DZ.PWM_DZClockSrc, \
+                                TIMER_InitStruct->PWM_DZ.PWM_DZClockDiv);
+
+            /* Enable pwm deadzone mode. */
+            TIMER_PWM_CFG_TypeDef timer_0x14 = {.d32 = TIMERx->TIMER_PWM_CFG};
+            timer_0x14.b.reg_timer_pwm_dz_en = ENABLE;
+            timer_0x14.b.reg_timer_pwm_dz_stop_state_p = TIMER_InitStruct->PWM_DZ.PWM_DZStopStateP;
+            timer_0x14.b.reg_timer_pwm_dz_stop_state_n = TIMER_InitStruct->PWM_DZ.PWM_DZStopStateN;
+            timer_0x14.b.reg_timer_pwm_dz_ref_p_inv_en = TIMER_InitStruct->PWM_DZ.PWM_DZInvertP;
+            timer_0x14.b.reg_timer_pwm_dz_ref_n_inv_en = TIMER_InitStruct->PWM_DZ.PWM_DZInvertN;
+            timer_0x14.b.reg_timer_pwm_dz_size = TIMER_InitStruct->PWM_DZ.PWM_DZSize;
+            TIMERx->TIMER_PWM_CFG = timer_0x14.d32;
+        }
+        else
+        {
+            /* Disable pwm deadzone mode. */
+            TIMER_PWM_CFG_TypeDef timer_0x14 = {.d32 = TIMERx->TIMER_PWM_CFG};
+            timer_0x14.b.reg_timer_pwm_dz_en = DISABLE;
+            TIMERx->TIMER_PWM_CFG = timer_0x14.d32;
+        }
+    }
+#endif
+
+#if (TIMER_SUPPORT_DMA_FUNCTION == 1)
+    if (timercase >= TIMER_CASE3)
+    {
+        /* DMA function. */
+        if (TIMER_InitStruct->TIMER_DMAEn != DISABLE)
+        {
+            TIMER_DMA_CFG_TypeDef timer_0x40 = {.d32 = TIMERx->TIMER_DMA_CFG};
+            timer_0x40.b.reg_timer_dma_en = 1;
+            timer_0x40.b.reg_timer_dma_mode = 0;
+            timer_0x40.b.reg_timer_dma_target = TIMER_InitStruct->TIMER_DMATarget;
+            TIMERx->TIMER_DMA_CFG = timer_0x40.d32;
+        }
+    }
+#endif
+
+    /* Clear the IT */
+    TIMER_ClearINT(TIMERx, TIMER_INT_TIMEOUT
+#if (TIMER_SUPPORT_LATCH_CNT_0 == 1)
+                   | TIMER_INT_LATCH_FIFO_FULL
+                   | TIMER_INT_LATCH_FIFO_THRESHOLD
+#endif
+                   | TIMER_INT_PAUSE);
+}
+
+/**
+  * \brief  Fills each TIMER_InitStruct member with its default value.
+  * \param  TIMER_InitStruct : pointer to a TIMER_InitTypeDef structure which will be initialized.
+  * \return None
+  */
+void TIMER_StructInit(TIMER_TimeBaseInitTypeDef *TIMER_InitStruct)
+{
+    TIMER_InitStruct->TIMER_ClockSrc  = TIMER_CLOCK_SRC_40M;
+    TIMER_InitStruct->TIMER_ClockDiv  = TIMER_CLOCK_DIV_1;
+    TIMER_InitStruct->TIMER_Mode      = TIMER_MODE_USERDEFINE;
+    TIMER_InitStruct->TIMER_Period    = 0xfffffff;
+    TIMER_InitStruct->TIMER_OneShotEn = DISABLE;
+
+#if (TIMER_SUPPORT_PWM_FUNCTION == 1)
+    TIMER_InitStruct->PWM_En = DISABLE;
+    TIMER_InitStruct->PWM_Polarity   = PWM_POLARITY_HIGH;
+    TIMER_InitStruct->PWM_OutputMode = PWM_PUSH_PULL;
+    TIMER_InitStruct->PWM_HighCount  = 0;
+#endif
+
+#if (TIMER_SUPPORT_PWM_DEADZONE == 1)
+    TIMER_InitStruct->PWM_DZ.PWM_DZClockSrc   = PWM_DZ_CLOCK_SRC_TIMER;
+    TIMER_InitStruct->PWM_DZ.PWM_DZClockDiv   = PWM_DZ_CLOCK_DIV_1;
+    TIMER_InitStruct->PWM_DZ.PWM_DZStopStateP = PWM_DZ_STOP_AT_LOW;
+    TIMER_InitStruct->PWM_DZ.PWM_DZStopStateN = PWM_DZ_STOP_AT_HIGH;
+    TIMER_InitStruct->PWM_DZ.PWM_DZInvertP    = DISABLE;
+    TIMER_InitStruct->PWM_DZ.PWM_DZInvertN    = DISABLE;
+    TIMER_InitStruct->PWM_DZ.PWM_DZEn         = DISABLE;
+    TIMER_InitStruct->PWM_DZ.PWM_DZSize       = 10;
+#endif
+
+#if (TIMER_SUPPORT_LATCH_CNT_0 == 1)
+    TIMER_InitStruct->TIMER_Latch.TIMER_LatchEn[0]          = DISABLE;
+    TIMER_InitStruct->TIMER_Latch.TIMER_LatchTriggerMode[0] = TIMER_LATCH_TRIGGER_RISING_EDGE;
+    TIMER_InitStruct->TIMER_Latch.TIMER_LatchThreshold      = 0;
+    TIMER_InitStruct->TIMER_Latch.TIMER_LatchTriggerPad     = 0;
+    TIMER_InitStruct->TIMER_Latch.TIMER_LatchDebEn          = DISABLE;
+    TIMER_InitStruct->TIMER_Latch.TIMER_LatchDebCountLimit  = 10;
+    TIMER_InitStruct->TIMER_Latch.TIMER_LatchDebClockDiv    = TIMER_CLOCK_DIV_1;
+#endif
+#if (TIMER_SUPPORT_LATCH_CNT_1 == 1)
+    TIMER_InitStruct->TIMER_Latch.TIMER_LatchEn[1]          = DISABLE;
+    TIMER_InitStruct->TIMER_Latch.TIMER_LatchTriggerMode[1] = TIMER_LATCH_TRIGGER_RISING_EDGE;
+#endif
+#if (TIMER_SUPPORT_LATCH_CNT_2 == 1)
+    TIMER_InitStruct->TIMER_Latch.TIMER_LatchEn[2]          = DISABLE;
+    TIMER_InitStruct->TIMER_Latch.TIMER_LatchTriggerMode[2] = TIMER_LATCH_TRIGGER_RISING_EDGE;
+#endif
+
+#if (TIMER_SUPPORT_DMA_FUNCTION == 1)
+    TIMER_InitStruct->TIMER_DMAEn     = DISABLE;
+    TIMER_InitStruct->TIMER_DMATarget = TIMER_DMA_CCR_FIFO;
+#endif
+
+#if (TIMER_SUPPORT_AUTO_CLOCK == 1)
+    /* Support dynamic adjustment of CCR & MAX_CNT.  When this
+       feature is enabled, dynamic adjustment is supported.
+       When this feature is disabled, dynamic adjustment is
+       not supported, resulting in lower power consumption.*/
+    TIMER_InitStruct->TIMER_DynConfigEn = ENABLE;
+#endif
+}
+
+/**
+  * \brief  Enables or disables the specified TIMER peripheral.
+  * \param  TIMERx: Select the TIMER peripheral. \ref TIMER_Declaration
+  * \param  NewState: new state of the TIMERx peripheral.
+  *   This parameter can be: ENABLE or DISABLE.
+  * \return None
+  */
+void TIMER_Cmd(TIMER_TypeDef *TIMERx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_TIMER_ALL_PERIPH(TIMERx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    uint32_t timerid = TIMER_GetTimerID(TIMERx);
+    TIMER_ShareTypeDef *sharebase = TIMER_GetTimerShareBase(TIMERx);
+
+    if (NewState != DISABLE)
+    {
+        sharebase->TIMER_EN_CTRL |= BIT(timerid);
+        TIMER_MODE_CFG_TypeDef timer_0x04 = {.d32 = TIMERx->TIMER_MODE_CFG};
+        if (timer_0x04.b.reg_timer_oneshot_mode_en)
+        {
+            sharebase->TIMER_ONESHOT_GO_CTRL |= BIT(timerid);
+        }
+    }
+    else
+    {
+        sharebase->TIMER_EN_CTRL &= ~(BIT(timerid));
+    }
+}
+
+/**
+  * \brief  Enables or disables the specified TIMERx interrupt.
+  * \param  TIMERx: Select the TIMER peripheral. \ref TIMER_Declaration
+  * \param  NewState: new state of the TIMERx peripheral.
+  *   This parameter can be: ENABLE or DISABLE.
+  * \return None
+  */
+void TIMER_INTConfig(TIMER_TypeDef *TIMERx, uint8_t TIMER_INT, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_TIMER_ALL_PERIPH(TIMERx));
+
+    uint32_t timerid = TIMER_GetTimerID(TIMERx);
+    TIMERCASE_TypeDef timercase = TIMER_GetTimerCase(TIMERx);
+    TIMER_ShareTypeDef *sharebase = TIMER_GetTimerShareBase(TIMERx);
+
+    if (NewState != DISABLE)
+    {
+        if (TIMER_INT & TIMER_INT_TIMEOUT)
+        {
+            sharebase->TIMER_INTR_EN_CTRL |= BIT(timerid);
+        }
+#if (TIMER_SUPPORT_LATCH_CNT_0 == 1)
+        if ((TIMER_INT & TIMER_INT_LATCH_FIFO_FULL) && (timercase >= TIMER_CASE4))
+        {
+            sharebase->TIMER_LAT_CNT_0_FIFO_FULL_INTR_EN_CTRL |= BIT(timerid);
+        }
+        if ((TIMER_INT & TIMER_INT_LATCH_FIFO_THRESHOLD) && (timercase >= TIMER_CASE4))
+        {
+            sharebase->TIMER_LAT_CNT_0_FIFO_MET_THRESHOLD_INTR_EN_CTRL |= BIT(timerid);
+        }
+#endif
+        if (TIMER_INT & TIMER_INT_PAUSE)
+        {
+            sharebase->TIMER_PAUSE_INTR_EN_CTRL |= BIT(timerid);
+        }
+    }
+    else
+    {
+
+        if (TIMER_INT & TIMER_INT_TIMEOUT)
+        {
+            sharebase->TIMER_INTR_EN_CTRL &= ~(BIT(timerid));
+        }
+#if (TIMER_SUPPORT_LATCH_CNT_0 == 1)
+        if ((TIMER_INT & TIMER_INT_LATCH_FIFO_FULL) && (timercase >= TIMER_CASE4))
+        {
+            sharebase->TIMER_LAT_CNT_0_FIFO_FULL_INTR_EN_CTRL &= ~(BIT(timerid));
+        }
+        if ((TIMER_INT & TIMER_INT_LATCH_FIFO_THRESHOLD) && (timercase >= TIMER_CASE4))
+        {
+            sharebase->TIMER_LAT_CNT_0_FIFO_MET_THRESHOLD_INTR_EN_CTRL &= ~(BIT(timerid));
+        }
+#endif
+        if (TIMER_INT & TIMER_INT_PAUSE)
+        {
+            sharebase->TIMER_PAUSE_INTR_EN_CTRL &= ~(BIT(timerid));
+        }
+    }
+}
+
+
+/**
+ * \brief   Check whether the TIMER interrupt has occurred or not.
+ * \param   TIMERx: Select the TIMER peripheral. \ref TIMER_Declaration
+ * \return  The new state of the TIMER_INTR(SET or RESET).
+ */
+ITStatus TIMER_GetINTStatus(TIMER_TypeDef *TIMERx, uint8_t TIMER_INT)
+{
+    /* Check the parameters */
+    assert_param(IS_TIMER_ALL_PERIPH(TIMERx));
+
+    uint32_t timerid = TIMER_GetTimerID(TIMERx);
+    TIMERCASE_TypeDef timercase = TIMER_GetTimerCase(TIMERx);
+    TIMER_ShareTypeDef *sharebase = TIMER_GetTimerShareBase(TIMERx);
+
+    ITStatus itstatus = RESET;
+    if (TIMER_INT == TIMER_INT_TIMEOUT)
+    {
+        if (sharebase->TIMER_INTR & BIT(timerid))
+        {
+            itstatus = SET;
+        }
+    }
+#if (TIMER_SUPPORT_LATCH_CNT_0 == 1)
+    else if ((TIMER_INT == TIMER_INT_LATCH_FIFO_FULL) && (timercase >= TIMER_CASE4))
+    {
+        if (sharebase->TIMER_LAT_CNT_0_FIFO_FULL_INTR & BIT(timerid))
+        {
+            itstatus = SET;
+        }
+    }
+    else if ((TIMER_INT == TIMER_INT_LATCH_FIFO_THRESHOLD) && (timercase >= TIMER_CASE4))
+    {
+        if (sharebase->TIMER_LAT_CNT_0_FIFO_MET_THRESHOLD_INTR & BIT(timerid))
+        {
+            itstatus = SET;
+        }
+    }
+#endif
+    else if (TIMER_INT == TIMER_INT_PAUSE)
+    {
+        if (sharebase->TIMER_PAUSE_INTR & BIT(timerid))
+        {
+            itstatus = SET;
+        }
+    }
+
+    return itstatus;
+}
+
+
+/**
+ * \brief   Clear TIMER interrupt.
+ * \param   TIMERx: Select the TIMER peripheral. \ref TIMER_Declaration
+ * \return  None.
+ */
+void TIMER_ClearINT(TIMER_TypeDef *TIMERx, uint8_t TIMER_INT)
+{
+    /* Check the parameters */
+    assert_param(IS_TIMER_ALL_PERIPH(TIMERx));
+
+    uint32_t timerid = TIMER_GetTimerID(TIMERx);
+    TIMERCASE_TypeDef timercase = TIMER_GetTimerCase(TIMERx);
+    TIMER_ShareTypeDef *sharebase = TIMER_GetTimerShareBase(TIMERx);
+
+    /* Clear the IT */
+    if (TIMER_INT & TIMER_INT_TIMEOUT)
+    {
+        sharebase->TIMER_INTR_STS = BIT(timerid);
+    }
+#if (TIMER_SUPPORT_LATCH_CNT_0 == 1)
+    if ((TIMER_INT & TIMER_INT_LATCH_FIFO_FULL) && (timercase >= TIMER_CASE4))
+    {
+        sharebase->TIMER_LAT_CNT_0_FIFO_FULL_INTR = BIT(timerid);
+    }
+    if ((TIMER_INT & TIMER_INT_LATCH_FIFO_THRESHOLD) && (timercase >= TIMER_CASE4))
+    {
+        sharebase->TIMER_LAT_CNT_0_FIFO_MET_THRESHOLD_INTR = BIT(timerid);
+    }
+#endif
+    if (TIMER_INT & TIMER_INT_PAUSE)
+    {
+        sharebase->TIMER_PAUSE_INTR_STS = BIT(timerid);
+    }
+}
+
+#if (TIMER_SUPPORT_CCR_FIFO == 1 || TIMER_SUPPORT_LATCH_CNT_0 == 1)
+/**
+  * \brief  Check whether the specified TIMER flag is set.
+  * \param  TIMERx: Select the TIMER peripheral. \ref TIMER_Declaration
+  * \param  TIMER_FLAG: Specifies the flag to check.
+  * \return The new state of TIMER_FLAG (SET or RESET).
+  */
+FlagStatus TIMER_GetFIFOFlagStatus(TIMER_TypeDef *TIMERx, uint32_t TIMER_FLAG)
+{
+    /* Check the parameters */
+    assert_param(IS_TIMER_ALL_PERIPH(TIMERx));
+
+    uint32_t timerid = TIMER_GetTimerID(TIMERx);
+    TIMERCASE_TypeDef timercase = TIMER_GetTimerCase(TIMERx);
+    TIMER_ShareTypeDef *sharebase = TIMER_GetTimerShareBase(TIMERx);
+    FlagStatus flagstatus = RESET;
+
+    if ((TIMER_FLAG == TIMER_FLAG_CCR_FIFO_FULL) && (timercase >= TIMER_CASE2))
+    {
+        if (sharebase->TIMER_CCR_FIFO_FULL_STS & BIT(timerid))
+        {
+            flagstatus = SET;
+        }
+    }
+    else if ((TIMER_FLAG == TIMER_FLAG_CCR_FIFO_EMPTY) && (timercase >= TIMER_CASE2))
+    {
+        if (sharebase->TIMER_CCR_FIFO_EMPTY_STS & BIT(timerid))
+        {
+            flagstatus = SET;
+        }
+    }
+    else if ((TIMER_FLAG == TIMER_FLAG_LATCH_FIFO_EMPTY) && (timercase >= TIMER_CASE4))
+    {
+        if (sharebase->TIMER_LAT_CNT_0_FIFO_EMPTY_STS & BIT(timerid))
+        {
+            flagstatus = SET;
+        }
+    }
+
+    return flagstatus;
+}
+#endif
+
+/**
+  * \brief  change TIMER period value.
+  * \param  TIMERx: Select the TIMER peripheral. \ref TIMER_Declaration
+  * \return The new state of success or not  (SET or RESET).
+  */
+void TIMER_ChangePeriod(TIMER_TypeDef *TIMERx, uint32_t period)
+{
+    /* Check the parameters */
+    assert_param(IS_TIMER_ALL_PERIPH(TIMERx));
+
+    TIMERx->TIMER_MAX_CNT = period;
+
+    return;
+}
+
+/**
+  * \brief  Get TIMER period value.
+  * \param  TIMERx: Select the TIMER peripheral. \ref TIMER_Declaration
+  * \return TIMER period value.
+  */
+uint32_t TIMER_GetPeriod(TIMER_TypeDef *TIMERx)
+{
+    /* Check the parameters */
+    assert_param(IS_TIMER_ALL_PERIPH(TIMERx));
+
+    return TIMERx->TIMER_MAX_CNT;
+}
+
+/**
+ * \brief   Get TIMERx current value when timer is running.
+ * \param   TIMERx: Select the TIMER peripheral. \ref TIMER_Declaration
+ * \return  The counter value.
+ */
+uint32_t TIMER_GetCurrentValue(TIMER_TypeDef *TIMERx)
+{
+    /* Check the parameters */
+    assert_param(IS_TIMER_ALL_PERIPH(TIMERx));
+
+    return TIMERx->TIMER_CUR_CNT;
+}
+
+/**
+ * \brief  Get TIMERx elapsed value when timer is running.
+ * \param  TIMERx: Select the TIMER peripheral. \ref TIMER_Declaration
+ * \return The elapsed counter value.
+ */
+uint32_t TIMER_GetElapsedValue(TIMER_TypeDef *TIMERx)
+{
+    /* Check the parameters */
+    assert_param(IS_TIMER_ALL_PERIPH(TIMERx));
+
+    return (TIMERx->TIMER_MAX_CNT - TIMERx->TIMER_CUR_CNT);
+}
+
+/**
+ * \brief   Check whether the TIMER is in operation or not.
+ * \param   TIMERx: Select the TIMER peripheral. \ref TIMER_Declaration
+ * \return  The new state of the timer operation status (SET or RESET).
+ */
+FlagStatus TIMER_GetOperationStatus(TIMER_TypeDef *TIMERx)
+{
+    /* Check the parameters */
+    assert_param(IS_TIMER_ALL_PERIPH(TIMERx));
+
+    uint32_t timerid = TIMER_GetTimerID(TIMERx);
+    TIMER_ShareTypeDef *sharebase = TIMER_GetTimerShareBase(TIMERx);
+    FlagStatus flagstatus = RESET;
+
+    TIMER_MODE_CFG_TypeDef timer_0x04 = {.d32 = TIMERx->TIMER_MODE_CFG};
+
+    if (timer_0x04.b.reg_timer_oneshot_mode_en)
+    {
+        if (sharebase->TIMER_ONESHOT_GO_CTRL & BIT(timerid))
+        {
+            flagstatus = SET;
+        }
+    }
+    else
+    {
+        if (sharebase->TIMER_EN_CTRL & BIT(timerid))
+        {
+            flagstatus = SET;
+        }
+    }
+
+    return flagstatus;
+}
+
+/**
+  * \brief  Enable/disable to pause timer counter.
+  * \param  TIMERx: Select the TIMER peripheral. \ref TIMER_Declaration
+  * \param  NewState: New state of the TIMERx peripheral.
+  * \return None.
+  */
+void TIMER_PauseCmd(TIMER_TypeDef *TIMERx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_TIMER_ALL_PERIPH(TIMERx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    uint32_t timerid = TIMER_GetTimerID(TIMERx);
+    TIMER_ShareTypeDef *sharebase = TIMER_GetTimerShareBase(TIMERx);
+
+    if (NewState != DISABLE)
+    {
+        sharebase->TIMER_PAUSE_CTRL |= BIT(timerid);
+    }
+    else
+    {
+        sharebase->TIMER_PAUSE_CTRL &= ~(BIT(timerid));
+    }
+}
+
+#if (TIMER_SUPPORT_CCR_FIFO == 1)
+/**
+  * \brief  Set TIMERx capture/compare value for user-define PWM auto mode.
+  * \param  TIMERx: Select the TIMER peripheral. \ref TIMER_Declaration
+  * \param  value:  User-defined TIMER capture/compare value for PWM auto mode,
+  *         ranging from 0 to 2^31.
+  * \return None
+  */
+void TIMER_SetCompareFIFO(TIMER_TypeDef *TIMERx, uint32_t value)
+{
+    /* Check the parameters */
+    assert_param(IS_TIMER_ALL_PERIPH(TIMERx));
+
+    TIMERx->TIMER_CCR_FIFO = value;
+}
+#endif
+
+#if (TIMER_SUPPORT_CCR_FIFO == 1 || TIMER_SUPPORT_LATCH_CNT_0 == 1)
+/**
+  * \brief  Clear capture/compare or latch count0 fifo.
+  * \param  TIMERx: Select the ENHTIMER peripheral. \ref TIMER_Declaration
+  * \param  FIFO_CLR: Specifies the FIFO type which to be clear.
+  * \return FIFO data length.
+  */
+void TIMER_ClearFIFO(TIMER_TypeDef *TIMERx, uint8_t FIFO_CLR)
+{
+    /* Check the parameters */
+    assert_param(IS_TIMER_ALL_PERIPH(TIMERx));
+
+    uint32_t timerid = TIMER_GetTimerID(TIMERx);
+
+    if (FIFO_CLR == TIMER_CLEAR_CCR_FIFO)
+    {
+        TIMER_MODE_CFG_TypeDef timer_0x04 = {.d32 = TIMERx->TIMER_MODE_CFG};
+        timer_0x04.b.reg_timer_ccr_fifo_clr = 1;
+        TIMERx->TIMER_MODE_CFG = timer_0x04.d32;
+    }
+    else if (FIFO_CLR == TIMER_CLEAR_LATCH_FIFO)
+    {
+        TIMER_LAT_CNT_0_CFG_TypeDef timer_0x1c = {.d32 = TIMERx->TIMER_LAT_CNT_0_CFG};
+        timer_0x1c.b.reg_timer_latch_cnt_0_fifo_clr = 1;
+        TIMERx->TIMER_LAT_CNT_0_CFG = timer_0x1c.d32;
+    }
+}
+#endif
+
+#if (TIMER_SUPPORT_LATCH_CNT_0 == 1)
+/**
+  * \brief  Read TIMERx latch counter0 fifo data.
+  * \param  TIMERx: Select the TIMER peripheral. \ref TIMER_Declaration
+  * \param  length: Latch count0 fifo length, max 8.
+  * \pBuf   pBuf: FIFO data out buffer.
+  * \return None.
+  */
+void TIMER_GetLatchFIFO(TIMER_TypeDef *TIMERx, uint32_t *pBuf, uint8_t length)
+{
+    /* Check the parameters */
+    assert_param(IS_TIMER_ALL_PERIPH(TIMERx));
+
+    if ((pBuf == NULL) || (length > 8))
+    {
+        return;
+    }
+
+    for (uint8_t i = 0; i < length; i++)
+    {
+        pBuf[i] = TIMERx->TIMER_LAT_CNT_0;
+    }
+}
+
+/**
+  * \brief  Get TIMER latch counter0 fifo length.
+  * \param  TIMERx: Select the TIMER peripheral. \ref TIMER_Declaration
+  * \return FIFO data length.
+  */
+uint8_t TIMER_GetLatchFIFOLength(TIMER_TypeDef *TIMERx)
+{
+    /* Check the parameters */
+    assert_param(IS_TIMER_ALL_PERIPH(TIMERx));
+
+    return (uint8_t)(TIMERx->TIMER_LAT_CNT_0_FIFO_DEPTH) & 0xFF;
+}
+#endif
+
+#if (TIMER_SUPPORT_PWM_FUNCTION == 1)
+/**
+  * \brief  Change PWM freq and duty according high_cnt and low_cnt
+  * \param  TIMERx: Select the TIMER peripheral. \ref TIMER_Declaration
+  * \param  period: This parameter controls the frequency, ranging from 0x0000 to 0xFFFFFFFF.
+  * \param  high_count: This parameter controls the duty cycle, ranging from 0x0000 to 0xFFFFFFFF.
+  * \return None
+  */
+void TIMER_PWMChangeFreqAndDuty(TIMER_TypeDef *TIMERx, uint32_t period, uint32_t high_count)
+{
+    /* Check the parameters */
+    assert_param(IS_TIMER_ALL_PERIPH(TIMERx));
+
+    TIMER_MODE_CFG_TypeDef timer_0x04 = {.d32 = TIMERx->TIMER_MODE_CFG};
+    uint16_t timer_mode = timer_0x04.b.reg_timer_mode;
+
+    TIMER_PWM_CFG_TypeDef timer_0x14 = {.d32 = TIMERx->TIMER_PWM_CFG};
+    uint16_t timer_polarity = timer_0x14.b.reg_timer_pwm_polarity;
+
+    TIMERx->TIMER_MAX_CNT = period;
+
+    if (timer_polarity == PWM_POLARITY_HIGH)
+    {
+        if (high_count > period)
+        {
+            high_count = period;
+        }
+        if (timer_mode == TIMER_MODE_USERDEFINE)
+        {
+            TIMERx->TIMER_CCR = (period - high_count);
+        }
+        else if (timer_mode == TIMER_MODE_USERDEFINE_AUTO)
+        {
+            TIMERx->TIMER_CCR_FIFO = (period - high_count);
+        }
+    }
+    else
+    {
+        if (timer_mode == TIMER_MODE_USERDEFINE)
+        {
+            TIMERx->TIMER_CCR = high_count;
+        }
+        else if (timer_mode == TIMER_MODE_USERDEFINE_AUTO)
+        {
+            TIMERx->TIMER_CCR_FIFO = high_count;
+        }
+    }
+}
+
+/**
+  * \brief  Get TIMER toggle state
+  * \param  TIMERx: Select the TIMER peripheral. \ref TIMER_Declaration
+  * \return The new state of toggle state(SET or RESET).
+  */
+bool TIMER_GetToggleState(TIMER_TypeDef *TIMERx)
+{
+    /* Check the parameters */
+    assert_param(IS_TIMER_ALL_PERIPH(TIMERx));
+
+    uint32_t timerid = TIMER_GetTimerID(TIMERx);
+    TIMERCASE_TypeDef timercase = TIMER_GetTimerCase(TIMERx);
+    TIMER_ShareTypeDef *sharebase = TIMER_GetTimerShareBase(TIMERx);
+
+    if (((sharebase->TIMER_PWM_STATE & BIT(timerid)) != 0) && (timercase > TIMER_CASE1))
+    {
+        return true;
+    }
+
+    return false;
+}
+
+/**
+  * \brief  Change TIMER pwm_phase_shift count
+  * \param  TIMERx: Select the TIMER peripheral. \ref TIMER_Declaration
+  * \param  PhaseShiftCnt:This parameter can be 0 to ccr;
+  * \return None
+  */
+#if (TIMER_SUPPORT_PWM_PHASE_SHIFT == 1)
+void TIMER_SetShiftCount(TIMER_TypeDef *TIMERx, uint32_t ShiftCount)
+{
+    assert_param(IS_TIMER_ALL_PERIPH(TIMERx));
+
+    TIMERx->TIMER_PWM_SHIFT_CNT = ShiftCount;
+}
+#endif
+
+
+#if (TIMER_SUPPORT_PWM_DEADZONE == 1)
+/**
+ * \brief  TIMER PWMP/N Source Select.
+ * \param  TIMERx: Select the TIMER peripheral. \ref TIMER_Declaration
+ * \param  PWMSrcSel: State of the TIMERx PWMP/N.
+ * \return None.
+ */
+void TIMER_SetPWMDZRef(TIMER_TypeDef *TIMERx, PWMDZRef_TypeDef PWMDZRef)
+{
+    /* Check the parameters. */
+    assert_param(IS_TIMER_ALL_PERIPH(TIMERx));
+
+    TIMER_PWM_CFG_TypeDef timer_0x14 = {.d32 = TIMERx->TIMER_PWM_CFG};
+    timer_0x14.b.reg_timer_pwm_dz_ref_sel = PWMDZRef;
+    TIMERx->TIMER_PWM_CFG = timer_0x14.d32;
+}
+#endif
+
+/**
+ * \brief  PWM complementary output emergency stop.
+ *         PWM_P emergency stop level state is configured by PWM_Stop_State_P,
+ *         PWM_N emergency stop level state is configured by PWM_Stop_State_N.
+ * \param  PWMx: Select the PWM peripheral. \ref PWM_Declaration
+ * \param  NewState: New state of complementary output.
+ *         \arg DISABLE: Resume PWM complementary output.
+ *         \arg ENABLE: PWM complementary output emergency stop.
+ * \return None.
+ * \note   To use this function, need to configure the corresponding timer.
+ *         PWM2 ->> TIMER2, PWM3 ->> TIMER3.
+ */
+void TIMER_PWMComplOutputEMCmd(TIMER_TypeDef *TIMERx, FunctionalState NewState)
+{
+    /* Check the parameters. */
+    assert_param(IS_TIMER_ALL_PERIPH(TIMERx));
+
+    TIMER_PWM_CFG_TypeDef timer_0x14 = {.d32 = TIMERx->TIMER_PWM_CFG};
+    timer_0x14.b.reg_timer_pwm_dz_emg_stop = NewState;
+    TIMERx->TIMER_PWM_CFG = timer_0x14.d32;
+}
+#endif
+
+#if (TIMER_SUPPORT_RAP_FUNCTION == 1)
+
+void TIMER_RAPModeCmd(TIMER_TypeDef *TIMERx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_TIMER_ALL_PERIPH(TIMERx));
+
+    uint32_t timerid = TIMER_GetTimerID(TIMERx);
+    TIMER_ShareTypeDef *sharebase = TIMER_GetTimerShareBase(TIMERx);
+
+    if (NewState != DISABLE)
+    {
+        sharebase->TIMER_RAP_CTRL0 |= BIT(timerid);
+        sharebase->TIMER_RAP_CTRL1 |= BIT(timerid);
+    }
+    else
+    {
+        sharebase->TIMER_RAP_CTRL0 &= ~BIT(timerid);
+        sharebase->TIMER_RAP_CTRL1 &= ~BIT(timerid);
+    }
+    return;
+}
+
+void TIMER_ActionTrigger(TIMER_TypeDef *TIMERx, uint32_t Action)
+{
+    /* Check the parameters */
+    assert_param(IS_TIMER_ALL_PERIPH(TIMERx));
+
+    uint32_t timerid = TIMER_GetTimerID(TIMERx);
+    TIMER_ShareTypeDef *sharebase = TIMER_GetTimerShareBase(TIMERx);
+
+    if (Action == TIMER_ACTION_START)
+    {
+        sharebase->TIMER_RAP_FW_TSAK_START |= BIT(timerid);
+    }
+    else if (Action == TIMER_ACTION_PAUSE)
+    {
+        sharebase->TIMER_RAP_FW_TASK_PAUSE |= BIT(timerid);
+    }
+    else if (Action == TIMER_ACTION_STOP)
+    {
+        sharebase->TIMER_RAP_FW_TASK_DISABLE |= BIT(timerid);
+    }
+
+    return;
+}
+
+void TIMER_ShortcutCmd(TIMER_TypeDef *TIMERx, uint32_t Action, uint32_t Event,
+                       FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_TIMER_ALL_PERIPH(TIMERx));
+
+    uint32_t timerid = TIMER_GetTimerID(TIMERx);
+    TIMER_ShareTypeDef *sharebase = TIMER_GetTimerShareBase(TIMERx);
+
+    if (NewState != DISABLE)
+    {
+        if (Action == TIMER_SHORTCUT_ACTION_PAUSE)
+        {
+            sharebase->TIMER_RAP_SHORTCUT_SUB_TASK_PAUSE |= BIT(timerid);
+        }
+        else if (Action == TIMER_SHORTCUT_ACTION_STOP)
+        {
+            sharebase->TIMER_RAP_SHORTCUT_SUB_TASK_DISABLE |= BIT(timerid);
+        }
+        if (Event == TIMER_SHORTCUT_EVENT_TIMEOUT)
+        {
+            sharebase->TIMER_RAP_SHORTCUT_PUB_EVENT_TIMEOUT |= BIT(timerid);
+        }
+    }
+    else
+    {
+        if (Action == TIMER_SHORTCUT_ACTION_PAUSE)
+        {
+            sharebase->TIMER_RAP_SHORTCUT_SUB_TASK_PAUSE &= ~BIT(timerid);
+        }
+        else if (Action == TIMER_SHORTCUT_ACTION_STOP)
+        {
+            sharebase->TIMER_RAP_SHORTCUT_SUB_TASK_DISABLE &= ~BIT(timerid);
+        }
+        if (Event == TIMER_SHORTCUT_EVENT_TIMEOUT)
+        {
+            sharebase->TIMER_RAP_SHORTCUT_PUB_EVENT_TIMEOUT &= ~BIT(timerid);
+        }
+    }
+    return;
+}
+#endif
+
+
diff --git a/bee/drivers/uart/CMakeLists.txt b/bee/drivers/uart/CMakeLists.txt
new file mode 100644
index 00000000..cdbbcfca
--- /dev/null
+++ b/bee/drivers/uart/CMakeLists.txt
@@ -0,0 +1,8 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+if(CONFIG_REALTEK_BEE_COMMON_DRIVER)
+    zephyr_include_directories(inc)
+endif()
+
+add_subdirectory_ifdef(CONFIG_REALTEK_BEE_UART src)
diff --git a/bee/drivers/uart/Kconfig b/bee/drivers/uart/Kconfig
new file mode 100644
index 00000000..fade7e0f
--- /dev/null
+++ b/bee/drivers/uart/Kconfig
@@ -0,0 +1,8 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config REALTEK_BEE_UART
+	bool "Realtek Bee UART driver"
+	default n
+	help
+	  This option enables the UART driver for Realtek Bee.
diff --git a/bee/drivers/uart/inc/rtl_uart.h b/bee/drivers/uart/inc/rtl_uart.h
new file mode 100644
index 00000000..b109e92a
--- /dev/null
+++ b/bee/drivers/uart/inc/rtl_uart.h
@@ -0,0 +1,1251 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *               Define to prevent recursive inclusion
+ *============================================================================*/
+#ifndef RTL_UART_H
+#define RTL_UART_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*============================================================================*
+ *                        Header Files
+ *============================================================================*/
+#include "utils/rtl_utils.h"
+#if defined (CONFIG_SOC_SERIES_RTL87X2G)
+#include "uart/src/device/rtl87x2g/rtl_uart_def.h"
+#elif defined (CONFIG_SOC_SERIES_RTL87X3E)
+#include "uart/src/device/rtl87x3e/rtl_uart_def.h"
+#elif defined (CONFIG_SOC_SERIES_RTL87X3D)
+#include "uart/src/device/rtl87x3d/rtl_uart_def.h"
+#elif defined (CONFIG_SOC_SERIES_RTL87X2J)
+#include "uart/src/device/rtl87x2j/rtl_uart_def.h"
+#elif defined (CONFIG_SOC_SERIES_RTL87X3EU)
+#include "uart/src/device/rtl87x3eu/rtl_uart_def.h"
+#elif defined (CONFIG_SOC_SERIES_RTL87X3J)
+#include "uart/src/device/rtl87x3j/rtl_uart_def.h"
+#endif
+
+/** \defgroup UART        UART
+  * \brief
+  * \{
+  */
+/*============================================================================*
+ *                         Constants
+ *============================================================================*/
+/** \defgroup UART_Exported_Constants UART Exported Constants
+  * \brief
+  * \{
+  */
+
+/**
+ * \defgroup    UART_FIFO_Size UART FIFO Size
+ * \{
+ * \ingroup     UART_Exported_Constants
+ */
+#define UART_TX_FIFO_SIZE           16
+#define UART_RX_FIFO_SIZE           32
+
+/** End of UART_FIFO_Size
+  * \}
+  */
+
+/**
+ * \defgroup    UART_Baudrate UART Baudrate
+ * \{
+ * \ingroup     UART_Exported_Constants
+ */
+typedef enum
+{
+    UART_BAUD_RATE_1200,
+    UART_BAUD_RATE_4800,
+    UART_BAUD_RATE_7200,
+    UART_BAUD_RATE_9600,
+    UART_BAUD_RATE_14400,
+    UART_BAUD_RATE_19200,
+    UART_BAUD_RATE_28800,
+    UART_BAUD_RATE_38400,
+    UART_BAUD_RATE_57600,
+    UART_BAUD_RATE_76800,
+    UART_BAUD_RATE_115200,
+    UART_BAUD_RATE_128000,
+    UART_BAUD_RATE_153600,
+    UART_BAUD_RATE_230400,
+    UART_BAUD_RATE_460800,
+    UART_BAUD_RATE_500000,
+    UART_BAUD_RATE_921600,
+    UART_BAUD_RATE_1000000,
+    UART_BAUD_RATE_1382400,
+    UART_BAUD_RATE_1444400,
+    UART_BAUD_RATE_1500000,
+    UART_BAUD_RATE_1843200,
+    UART_BAUD_RATE_2000000,
+    UART_BAUD_RATE_3000000,
+    UART_BAUD_RATE_4000000,
+    UART_BAUD_RATE_MAXIMUM,
+} UARTBaudrate_TypeDef;
+
+/** End of UART_Baudrate
+  * \}
+  */
+
+/**
+ * \defgroup    UART_Parity UART Parity
+ * \{
+ * \ingroup     UART_Exported_Constants
+ */
+typedef enum
+{
+    UART_PARITY_NO_PARTY = 0x0,
+    UART_PARITY_ODD = 0x1,
+    UART_PARITY_EVEN = 0x3,
+    UART_PARITY_STICK_HIGH = 0x5,
+    UART_PARITY_STICK_LOW = 0x7,
+} UARTParity_TypeDef;
+
+#define IS_UART_PARITY(PARITY) (((PARITY) == UART_PARITY_NO_PARTY) || \
+                                ((PARITY) == UART_PARITY_ODD) || \
+                                ((PARITY) == UART_PARITY_EVEN) || \
+                                ((PARITY) == UART_PARITY_STICK_HIGH) || \
+                                ((PARITY) == UART_PARITY_STICK_LOW))
+
+/** End of UART_Parity
+  * \}
+  */
+
+/**
+ * \defgroup    UART_Stop_Bits UART Stop Bits
+ * \{
+ * \ingroup     UART_Exported_Constants
+ */
+typedef enum
+{
+    UART_STOP_BITS_1 = 0x0,
+    UART_STOP_BITS_2 = 0x1,
+} UARTStopBits_TypeDef;
+
+#define IS_UART_STOPBITS(STOP) (((STOP) == UART_STOP_BITS_1) || \
+                                ((STOP) == UART_STOP_BITS_2))
+
+/** End of UART_Stop_Bits
+  * \}
+  */
+
+/**
+ * \defgroup    UART_Word_Length UART Word Length
+ * \{
+ * \ingroup     UART_Exported_Constants
+ */
+typedef enum
+{
+    UART_WORD_LENGTH_7BIT = 0x0,
+    UART_WORD_LENGTH_8BIT = 0x1,
+} UARTWordLen_TypeDef;
+
+#define IS_UART_WORD_LENGTH(LEN) ((((LEN)) == UART_WORD_LENGTH_7BIT) || \
+                                  (((LEN)) == UART_WORD_LENGTH_8BIT))
+
+/** End of UART_Word_Length
+  * \}
+  */
+
+/**
+ * \defgroup    UART_RX_Idle_Time UART RX Idle Time
+ * \{
+ * \ingroup     UART_Exported_Constants
+ */
+typedef enum
+{
+    UART_RX_IDLE_1BYTE = 0x0,
+    UART_RX_IDLE_2BYTE = 0x1,
+    UART_RX_IDLE_4BYTE = 0x2,
+    UART_RX_IDLE_8BYTE = 0x3,
+    UART_RX_IDLE_16BYTE = 0x4,
+    UART_RX_IDLE_32BYTE = 0x5,
+    UART_RX_IDLE_64BYTE = 0x6,
+    UART_RX_IDLE_128BYTE = 0x7,
+    UART_RX_IDLE_256BYTE = 0x8,
+    UART_RX_IDLE_512BYTE = 0x9,
+    UART_RX_IDLE_1024BYTE = 0xA,
+    UART_RX_IDLE_2048BYTE = 0xB,
+    UART_RX_IDLE_4096BYTE = 0xC,
+    UART_RX_IDLE_8192BYTE = 0xD,
+    UART_RX_IDLE_16384BYTE = 0xE,
+    UART_RX_IDLE_32768BYTE = 0xF,
+} UARTRXIdleTime_TypeDef;
+
+#define IS_UART_RX_IDLE_TIME(TIME) ((TIME) <= 0x0F)
+
+/** End of UART_RX_Idle_Time
+  * \}
+  */
+
+/**
+ * \defgroup    UART_Interrupts UART Interrupts
+ * \{
+ * \ingroup     UART_Exported_Constants
+ */
+#define UART_INT_RD_AVA                 (BIT0)
+#define UART_INT_TX_FIFO_EMPTY          (BIT1)
+#define UART_INT_RX_LINE_STS            (BIT2)
+#if (UART_SUPPORT_TX_DONE == 1)
+#define UART_INT_TX_DONE                (BIT4)
+#endif
+#if (UART_SUPPORT_TX_THRESHOLD == 1)
+#define UART_INT_TX_THD                 (BIT5)
+#endif
+#define UART_INT_RX_IDLE                (BIT7)
+#if (UART_SUPPORT_CTS_TOGGLE == 1)
+#define UART_INT_CTS_TOGGLE             (BIT8)
+#endif
+
+#define IS_UART_INTERRUPT(INT)          (((INT) == UART_INT_RD_AVA) || \
+                                         ((INT) == UART_INT_TX_FIFO_EMPTY) || \
+                                         ((INT) == UART_INT_RX_LINE_STS) || \
+                                         ((INT) == UART_INT_TX_DONE) || \
+                                         ((INT) == UART_INT_TX_THD) || \
+                                         ((INT) == UART_INT_RX_IDLE) || \
+                                         ((INT) == UART_INT_CTS_TOGGLE))
+
+/** End of UART_Interrupts
+  * \}
+  */
+
+/**
+ * \defgroup    UART_Interrupts_Identifier UART Interrupts Identifier
+ * \{
+ * \ingroup     UART_Exported_Constants
+ */
+#define UART_INT_PENDING                ((uint16_t)(0x01 << 0))
+#define UART_INT_ID_LINE_STATUS         ((uint16_t)(0x03 << 1))
+#define UART_INT_ID_RX_LEVEL_REACH      ((uint16_t)(0x02 << 1))
+#define UART_INT_ID_RX_DATA_TIMEOUT     ((uint16_t)(0x06 << 1))
+#define UART_INT_ID_TX_FIFO_EMPTY       ((uint16_t)(0x01 << 1))
+
+#define IS_UART_INT_ID(ID) (((ID) == UART_INT_ID_LINE_STATUS) || \
+                            ((ID) == UART_INT_ID_RX_LEVEL_REACH) || \
+                            ((ID) == UART_INT_ID_RX_DATA_TIMEOUT) || \
+                            ((ID) == UART_INT_ID_TX_FIFO_EMPTY))
+
+/** End of UART_Interrupts_Identifier
+  * \}
+  */
+
+/**
+ * \defgroup    UART_Flag UART Flag
+ * \{
+ * \ingroup     UART_Exported_Constants
+ */
+#define UART_FLAG_RX_DATA_AVA           (BIT0)
+#define UART_FLAG_RX_OVERRUN            (BIT1)
+#define UART_FLAG_RX_PARITY_ERR         (BIT2)
+#define UART_FLAG_RX_FRAME_ERR          (BIT3)
+#define UART_FLAG_RX_BREAK_ERR          (BIT4)
+#define UART_FLAG_TX_FIFO_EMPTY         (BIT5)
+#define UART_FLAG_TX_EMPTY              (BIT6)
+#define UART_FLAG_RX_FIFO_ERR           (BIT7)
+#define UART_FLAG_RX_IDLE               (BIT9)
+#if (UART_SUPPORT_TX_DONE == 1)
+#define UART_FLAG_TX_DONE               (BIT10)
+#endif
+#if (UART_SUPPORT_TX_THRESHOLD == 1)
+#define UART_FLAG_TX_THD                (BIT11)
+#endif
+#if (UART_SUPPORT_CTS_TOGGLE == 1)
+#define UART_FLAG_CTS_TOGGLE            (BIT12)
+#endif
+
+#define IS_UART_GET_FLAG(FLAG) (((FLAG) == UART_FLAG_RX_DATA_AVA) || \
+                                ((FLAG) == UART_FLAG_RX_OVERRUN) || \
+                                ((FLAG) == UART_FLAG_RX_PARITY_ERR) || \
+                                ((FLAG) == UART_FLAG_RX_FRAME_ERR) || \
+                                ((FLAG) == UART_FLAG_RX_BREAK_ERR) || \
+                                ((FLAG) == UART_FLAG_TX_FIFO_EMPTY) || \
+                                ((FLAG) == UART_FLAG_TX_EMPTY) || \
+                                ((FLAG) == UART_FLAG_RX_FIFO_ERR) || \
+                                ((FLAG) == UART_FLAG_RX_IDLE) || \
+                                ((FLAG) == UART_FLAG_TX_DONE) || \
+                                ((FLAG) == UART_FLAG_TX_THD) || \
+                                ((FLAG) == UART_FLAG_CTS_TOGGLE))
+
+/** End of UART_Flag
+  * \}
+  */
+
+/**
+ * \defgroup    UART_Interrupts_Mask UART Interrupts Mask
+ * \{
+ * \ingroup     UART_Exported_Constants
+ */
+#define UART_INT_MASK_RD_AVA            (BIT0)
+#define UART_INT_MASK_TX_FIFO_EMPTY     (BIT1)
+#define UART_INT_MASK_RX_LINE_STS       (BIT2)
+#define UART_INT_MASK_RX_IDLE           (BIT5)
+#if (UART_SUPPORT_TX_DONE == 1)
+#define UART_INT_MASK_TX_DONE           (BIT6)
+#endif
+#if (UART_SUPPORT_TX_THRESHOLD == 1)
+#define UART_INT_MASK_TX_THD            (BIT7)
+#endif
+#if (UART_SUPPORT_CTS_TOGGLE == 1)
+#define UART_INT_MASK_CTS_TOGGLE        (BIT8)
+#endif
+
+#define IS_UART_INT_MASK(INT) ((INT) & (UART_INT_MASK_RD_AVA | \
+                                        UART_INT_MASK_TX_FIFO_EMPTY | \
+                                        UART_INT_MASK_RX_LINE_STS | \
+                                        UART_INT_MASK_RX_IDLE | \
+                                        UART_INT_MASK_TX_DONE | \
+                                        UART_INT_MASK_TX_THD  | \
+                                        UART_INT_MASK_CTS_TOGGLE))
+
+/** End of UART_Interrupts_Mask
+  * \}
+  */
+
+/** End of UART_Exported_Constants
+  * \}
+  */
+
+/*============================================================================*
+ *                         Types
+ *============================================================================*/
+/** \defgroup UART_Exported_Types UART Exported Types
+  * \brief
+  * \{
+  */
+
+/**
+ * \brief       UART initialize parameters
+ *
+ * \ingroup     UART_Exported_Types
+ */
+typedef struct
+{
+    uint16_t UART_OvsrAdj;              /*!< Specifies the baud rate setting, ovsr_adj, please refer to baudrate setting table.*/
+
+    uint16_t UART_Div;                  /*!< Specifies the baud rate setting, div, please refer to baudrate setting table.*/
+
+    uint16_t UART_Ovsr;                 /*!< Specifies the baud rate setting, ovsr, please refer to baudrate setting table.*/
+
+    UARTWordLen_TypeDef UART_WordLen;   /*!< Specifies the UART Wordlength. */
+
+    UARTStopBits_TypeDef UART_StopBits; /*!< Specifies the stop bit. */
+
+    UARTParity_TypeDef UART_Parity;     /*!< Specifies the parity. */
+
+    uint8_t UART_TxThdLevel;            /*!< Specifies the Tx threshold level. This parameter must range from 1 to 29.*/
+
+    uint8_t UART_RxThdLevel;            /*!< Specifies the Rx threshold level. This parameter must range from 1 to 29.*/
+
+    UARTRXIdleTime_TypeDef UART_IdleTime; /*!< Specifies the idle time. */
+
+    FunctionalState UART_HardwareFlowControl; /*!< Enable or Disable hardware flow control. */
+
+    FunctionalState UART_DMAEn;         /*!< Enable or Disable dma mode. */
+
+    FunctionalState UART_TxDMAEn;       /*!< Enable or Disable Tx dma mode. */
+
+    FunctionalState UART_RxDMAEn;       /*!< Enable or Disable Rx dma mode. */
+
+    uint8_t UART_TxWaterLevel;          /*!< Specifies the DMA tx water level. This parameter must range from 1 to 16.*/
+
+    uint8_t UART_RxWaterLevel;          /*!< Specifies the DMA rx water level. This parameter must range from 1 to 31.*/
+
+    FunctionalState UART_TxOnlyEn;      /*!< Enable or Disable tx only mode. */
+
+#if (UART_SUPPORT_AUTO_CLOCK == 1)
+    FunctionalState UART_AutoModeEn;    /*!< Enable or disable the UART auto mode.
+                                             When the UART automatic mode is enabled, the UART clock automatically
+                                             activates when preparing to receive data and goes idle when no more data
+                                             is received for the duration specified by UART_AutoModeTime. */
+
+    uint16_t UART_AutoModeTime;         /*!< Specifies the UART auto mode time.
+                                             UART_AutoModeTime is the period after which the UART clock will enter
+                                             idle mode if no further data is received. */
+#endif
+} UART_InitTypeDef;
+
+/** End of UART_Exported_Types
+  * \}
+  */
+
+/*============================================================================*
+ *                         Functions
+ *============================================================================*/
+/** \defgroup UART_Exported_Functions UART Exported Functions
+  * \brief
+  * \{
+  */
+
+/**
+ * \brief   Deinitialize the selected UART peripheral registers to their default reset values(turn off UART clock).
+ *
+ * \param[in] UARTx: Select the UART peripheral. \ref UART_Declaration
+ *
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_uart_init(void)
+ * {
+ *    UART_DeInit(UART0);
+ * }
+ * \endcode
+ */
+void UART_DeInit(UART_TypeDef *UARTx);
+
+/**
+ * \brief   Initialize the selected UART peripheral according to the specified
+ *          parameters in  UART_InitStruct.
+ *
+ * \param[in] UARTx: Select the UART peripheral. \ref UART_Declaration
+ * \param[in] UART_InitStruct: Pointer to a UART_InitTypeDef structure that
+ *            contains the configuration information for the selected UART peripheral.
+ *
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_uart_init(void)
+ * {
+ *     UART_DeInit(UART0);
+ *
+ *     RCC_ClockCmd(UART0_CLOCK, ENABLE);
+ *
+ *     UART_InitTypeDef UART_InitStruct;
+ *     UART_StructInit(&UART_InitStruct);
+ *     UART_InitStruct.UART_Div         = 20;
+ *     UART_InitStruct.UART_Ovsr        = 12;
+ *     UART_InitStruct.UART_OvsrAdj     = 0x252;
+ *     UART_InitStruct.UART_RxThdLevel  = 16;
+ *    //Add other initialization parameters that need to be configured here.
+ *     UART_Init(UART0, &UART_InitStruct);
+ * }
+ * \endcode
+ */
+void UART_Init(UART_TypeDef *UARTx, UART_InitTypeDef *UART_InitStruct);
+
+/**
+ * \brief   Fills each UART_InitStruct member with its default value.
+ *
+ * \param[in] UART_InitStruct: pointer to an UART_InitTypeDef structure which will be initialized.
+ *
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_uart_init(void)
+ * {
+ *     UART_DeInit(UART0);
+ *
+ *     RCC_ClockCmd(UART0_CLOCK, ENABLE);
+ *
+ *     UART_InitTypeDef UART_InitStruct;
+ *     UART_StructInit(&UART_InitStruct);
+ *     UART_InitStruct.UART_Div         = 20;
+ *     UART_InitStruct.UART_Ovsr        = 12;
+ *     UART_InitStruct.UART_OvsrAdj     = 0x252;
+ *     UART_InitStruct.UART_RxThdLevel  = 16;
+ *     //Add other initialization parameters that need to be configured here.
+ *     UART_Init(UART0, &UART_InitStruct);
+ * }
+ * \endcode
+ */
+void UART_StructInit(UART_InitTypeDef *UART_InitStruct);
+
+/**
+ * \brief   Mask or unmask the specified UART interrupt source.
+ *
+ * \param[in] UARTx: Select the UART peripheral. \ref UART_Declaration
+ * \param[in] UART_INT: Specified the UART interrupt source that to be mask or unmask.
+ *            This parameter can be one of the following values:
+ *            \arg UART_INT_MASK_RD_AVA: Mask INTCR(erbi).
+ *            \arg UART_INT_MASK_FIFO_EMPTY: Mask INTCR(etbei).
+ *            \arg UART_INT_MASK_LINE_STS: Mask INTCR(elsi).
+ *            \arg UART_INT_MASK_MODEM_STS: Mask INTCR(edssi).
+ *            \arg UART_INT_MASK_RX_BREAK: Mask rx break interrupt.
+ *            \arg UART_INT_MASK_RX_IDLE: Mask rx break interrupt.
+ *            \arg UART_INT_MASK_TX_DONE: Mask the interrupt tx done interrupt.
+ *            \arg UART_INT_MASK_TX_THD: Mask tx fifo threshold interrupt.
+ *            \arg UART_INT_MASK_CTS_TOGGLE: mask CTS toggle interrupt.
+ * \param[in] NewState: New state of the specified UART interrupt source.
+ *            This parameter can be: ENABLE or DISABLE.
+ *
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_uart_init(void)
+ * {
+ *     UART_DeInit(UART0);
+ *
+ *     RCC_ClockCmd(UART0_CLOCK, ENABLE);
+ *
+ *     UART_InitTypeDef UART_InitStruct;
+ *     UART_StructInit(&UART_InitStruct);
+ *     UART_InitStruct.UART_Div         = 20;
+ *     UART_InitStruct.UART_Ovsr        = 12;
+ *     UART_InitStruct.UART_OvsrAdj     = 0x252;
+ *     UART_InitStruct.UART_RxThdLevel  = 16;
+ *     //Add other initialization parameters that need to be configured here.
+ *     UART_Init(UART0, &UART_InitStruct);
+ *
+ *     UART_MaskINTConfig(UART0, UART_INT_MASK_RD_AVA, ENABLE);
+ *     UART_INTConfig(UART0, UART_INT_RD_AVA, ENABLE);
+ *     UART_MaskINTConfig(UART0, UART_INT_MASK_RD_AVA, DISABLE);
+ * }
+ * \endcode
+ */
+void UART_MaskINTConfig(UART_TypeDef *UARTx, uint32_t UART_INT_MASK,
+                        FunctionalState NewState);
+/**
+ * \brief   Enables or disables the specified UART interrupts.
+ *
+ * \param[in] UARTx: Select the UART peripheral. \ref UART_Declaration
+ * \param[in] UART_IT: Specified the UART interrupt source that to be enabled or disabled.
+ *            This parameter can be any combination of the following values:
+ *            \arg UART_INT_RD_AVA: Rx data avaliable interrupt source.
+ *            \arg UART_INT_TX_FIFO_EMPTY: Tx FIFO empty interrupt source.
+ *            \arg UART_INT_RX_LINE_STS: Rx line status interrupt source.
+ *            \arg UART_INT_MODEM_STS: Modem status interrupt source.
+ *            \arg UART_INT_TX_DONE: Tx done interrupt source.
+ *            \arg UART_INT_TX_THD: Tx threshold(FIFO data length <= thredhold) interrupt source.
+ *            \arg UART_INT_RX_BREAK: Rx break signal interrupt source.
+ *            \arg UART_INT_RX_IDLE: Rx bus ilde interrupt source.
+ *            \arg UART_INT_CTS_TOGGLE: CTS toggle interrupt source.
+ * \param[in] NewState: New state of the specified UART interrupt source.
+ *            This parameter can be: ENABLE or DISABLE.
+ *
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_uart_init(void)
+ * {
+ *     UART_DeInit(UART0);
+ *
+ *     RCC_ClockCmd(UART0_CLOCK, ENABLE);
+ *
+ *     UART_InitTypeDef UART_InitStruct;
+ *     UART_StructInit(&UART_InitStruct);
+ *     UART_InitStruct.UART_Div         = 20;
+ *     UART_InitStruct.UART_Ovsr        = 12;
+ *     UART_InitStruct.UART_OvsrAdj     = 0x252;
+ *     UART_InitStruct.UART_RxThdLevel  = 16;
+ *     //Add other initialization parameters that need to be configured here.
+ *     UART_Init(UART0, &UART_InitStruct);
+ *
+ *     UART_INTConfig(UART0, UART_INT_RD_AVA, ENABLE);
+ * }
+ * \endcode
+ */
+void UART_INTConfig(UART_TypeDef *UARTx, uint32_t UART_IT, FunctionalState NewState);
+
+/**
+ * \brief   Send data.
+ *
+ * \param[in] UARTx: Select the UART peripheral. \ref UART_Declaration
+ * \param[in] inBuf: Buffer of data to be sent.
+ * \param[in] count: Length of data to be sent.
+ *
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void uart_demo(void)
+ * {
+ *     uint8_t data[] = "UART demo";
+ *     UART_SendData(UART0, data, sizeof(data));
+ * }
+ * \endcode
+ */
+void UART_SendData(UART_TypeDef *UARTx, const uint8_t *inBuf, uint16_t Count);
+
+#if (UART_SUPPORT_HALF_WORD == 1)
+/**
+ * \brief   Send half word data.
+ *
+ * \param[in] UARTx: Select the UART peripheral. \ref UART_Declaration
+ * \param[in] inBuf: Buffer of data to be sent.
+ * \param[in] count: Length of data to be sent.
+ *
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void uart_demo(void)
+ * {
+ *     uint8_t data[] = "UART demo";
+ *     UART_SendHalfWordData(UART0, data, sizeof(data));
+ * }
+ * \endcode
+ */
+void UART_SendHalfWordData(UART_TypeDef *UARTx, const uint16_t *inBuf, uint16_t Count);
+#endif
+
+#if (UART_SUPPORT_TXDATA_API == 1)
+/**
+ * \brief   Tx data.
+ *
+ * \param[in] UARTx: Select the UART peripheral. \ref UART_Declaration
+ * \param[in] inBuf: Buffer of data to be sent.
+ * \param[in] count: Length of data to be sent.
+ *
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void uart_demo(void)
+ * {
+ *     uint8_t data[] = "UART demo";
+ *     UART_TxData(UART0, data, sizeof(data));
+ * }
+ * \endcode
+ */
+void UART_TxData(UART_TypeDef *UARTx, const uint8_t *inBuf, uint16_t count);
+#endif
+
+/**
+ * \brief   Receive data from RX FIFO.
+ *
+ * \param[in]  UARTx: Select the UART peripheral. \ref UART_Declaration
+ * \param[out] outBuf: Buffer to store data which read from RX FIFO.
+ * \param[in]  count: Length of data to read.
+ *
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void uart_demo(void)
+ * {
+ *     uint8_t data[32] = {10};
+ *     UART_ReceiveData(UART0, data, 10);
+ * }
+ * \endcode
+ */
+void UART_ReceiveData(UART_TypeDef *UARTx, uint8_t *outBuf, uint16_t count);
+
+#if (UART_SUPPORT_HALF_WORD == 1)
+/**
+ * \brief   Receive half word data from RX FIFO.
+ *
+ * \param[in]  UARTx: Select the UART peripheral. \ref UART_Declaration
+ * \param[out] outBuf: Buffer to store data which read from RX FIFO.
+ * \param[in]  count: Length of data to read.
+ *
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void uart_demo(void)
+ * {
+ *     uint8_t data[32] = {10};
+ *     UART_ReceiveData(UART0, data, 10);
+ * }
+ * \endcode
+ */
+void UART_ReceiveHalfWordData(UART_TypeDef *UARTx, uint16_t *outBuf, uint16_t count);
+#endif
+
+/**
+ * \brief   Set UART communication baudrate.
+ *
+ * \param[in]  UARTx: Select the UART peripheral. \ref UART_Declaration
+ * \param[in]  div: Parameter of the selected UART baudrate.
+ * \param[in]  ovsr: Parameter of the selected UART baudrate.
+ * \param[in]  ovsr_adj: Parameter of the selected UART baudrate.
+ *
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * UART BaudRate Table: Baud rate set value for different data length (clock source 40MHz only)
+ *  9 bits data length: start bit + 7 data bit + stop bit
+ * 10 bits data length: start bit + 8 data bit + stop bit
+ * 11 bits data length: start bit + 8 data bit + parity bit + stop bit
+ * 12 bits data length: start bit + 8 data bit + parity bit + stop bit+ 2nd Stop bit
+    baudrate |       9 bits data length      |       10 bits data length     |      11 bits data length      |      12 bits data length      |
+             |  ovsr  |  ovsr_adj  |  div    |  ovsr  |  ovsr_adj  |  div    |  ovsr  |  ovsr_adj  |  div    |  ovsr  |  ovsr_adj  |  div    |
+   --------------------------------------------------------------------------------------------------------------------------------------------
+   1200      |   0x5      0x16D      0xC35   |   0x9      0x112      0x91B   |   0x9      0x70       0x91B   |   0x9      0x71       0x91B   |
+   4800      |   0x0      0x0        0x682   |   0x0      0x0        0x682   |   0xB      0x6DD      0x1F3   |   0xB      0x6D5      0x1F3   |
+   7200      |   0x0      0x0        0x457   |   0x0      0x0        0x457   |   0xC      0x84       0x143   |   0xC      0x84       0x143   |
+   9600      |   0x0      0x0        0x341   |   0x0      0x0        0x341   |   0x7      0x7EF      0x143   |   0x7      0x7EF      0x143   |
+   14400     |   0x6      0x10       0xFA    |   0x9      0x10       0xC5    |   0x9      0x10       0xC5    |   0x9      0x10       0xC5    |
+   19200     |   0x2      0x3        0x120   |   0x1      0x3        0x150   |   0x8      0x77B      0x97    |   0x8      0x77B      0x97    |
+   28800     |   0x2      0x3        0xC0    |   0x1      0x3        0xE0    |   0x6      0x84       0x7C    |   0x6      0x84       0x7C    |
+   38400     |   0x2      0x3        0x90    |   0x1      0x3        0xA8    |   0xE      0x122      0x36    |   0xE      0x122      0x36    |
+   57600     |   0x2      0x3        0x60    |   0x1      0x3        0x70    |   0x6      0x84       0x3E    |   0x6      0x84       0x3E    |
+   76800     |   0x2      0x3        0x48    |   0x1      0x3        0x54    |   0xE      0x122      0x1B    |   0xE      0x122      0x1B    |
+   115200    |   0x2      0x3        0x30    |   0x1      0x3        0x38    |   0x6      0x84       0x1F    |   0x6      0x84       0x1F    |
+   230400    |   0x2      0x3        0x18    |   0x1      0x3        0x1C    |   0xE      0x122      0x9     |   0xE      0x122      0x9     |
+   460800    |   0x2      0x3        0xC     |   0x1      0x3        0xE     |   0x7      0x14A      0x7     |   0x7      0x15A      0x7     |
+   500000    |   0x5      0x0        0x8     |   0x5      0x0        0x8     |   0x5      0x0        0x8     |   0x5      0x0        0x8     |
+   921600    |   0x2      0x3        0x6     |   0x1      0x3        0x7     |   0x9      0x2AA      0x3     |   0x9      0x2AB      0x3     |
+   1000000   |   0x0      0x0        0x8     |   0x0      0x0        0x8     |   0x5      0x0        0x4     |   0x5      0x0        0x4     |
+   1382400   |   0x9      0xAA       0x2     |   0x9      0x2AA      0x2     |   0x9      0x2AA      0x2     |   0x9      0x2AB      0x2     |
+   1444400   |   0x8      0x1F7      0x2     |   0x8      0x3F7      0x2     |   0x8      0x3F7      0x2     |   0x8      0x3FF      0x2     |
+   1500000   |   0x8      0x92       0x2     |   0x8      0x92       0x2     |   0x8      0x492      0x2     |   0x8      0x490      0x2     |
+   1843200   |   0x5      0x1F7      0x2     |   0x5      0x3F7      0x2     |   0x5      0x3F7      0x2     |   0x5      0x3FF      0x2     |
+   2000000   |   0x0      0x0        0x4     |   0x0      0x0        0x4     |   0x5      0x0        0x2     |   0x5      0x0        0x2     |
+   3000000   |   0x8      0x92       0x1     |   0x8      0x92       0x1     |   0x8      0x492      0x1     |   0x8      0x490      0x1     |
+   4000000   |   0x5      0x0        0x1     |   0x5      0x0        0x1     |   0x5      0x0        0x1     |   0x5      0x0        0x1     |
+   ---------------------------------------------------------------------------------------------------------------------------------------------
+ *
+ * void uart_demo(void)
+ * {
+ *     uint16_t div = 0x38;
+ *     uint16_t ovsr = 0x1;
+ *     uint16_t ovsr_adj = 0x3;
+ *     UART_SetBaudRate(UART0, div, ovsr, ovsr_adj);
+ * }
+ *
+ * \endcode
+ */
+void UART_SetBaudRate(UART_TypeDef *UARTx, uint16_t div, uint16_t ovsr, uint16_t ovsr_adj);
+
+/**
+ * \brief   Set UART communication parameters.
+ *
+ * \param[in] UARTx: Select the UART peripheral. \ref UART_Declaration
+ * \param[in] wordLen: Data width of the selected UART peripheral.
+ *            This parameter can be one of the following values:
+ *            \arg UART_WORD_LENGTH_7BIT: 7-bit data length.
+ *            \arg UART_WORD_LENGTH_8BIT: 8-bit data length.
+ * \param[in] parity: parity of the selected UART peripheral.
+ *            This parameter can be one of the following values:
+ *            \arg UART_STOP_BITS_1: 1-bit stop bit.
+ *            \arg UART_STOP_BITS_2: 2-bit stop bit.
+ * \param[in] stopBits: Stop bit of the selected UART peripheral.
+ *            This parameter can be one of the following values:
+ *            \arg UART_PARITY_NO_PARTY: No parity.
+ *            \arg UART_PARITY_ODD: Odd parity.
+ *            \arg UART_PARITY_EVEN: Even parity.
+ *
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void uart_demo(void)
+ * {
+ *     uint16_t word_len = UART_WORD_LENGTH_8BIT;
+ *     uint16_t parity = UART_PARITY_NO_PARTY;
+ *     uint16_t stop_bits = UART_STOP_BITS_1;
+ *     UART_SetParams(UART0, wordLen, parity, stopBits);
+ * }
+ * \endcode
+ */
+void UART_SetParams(UART_TypeDef *UARTx, uint16_t wordLen, uint16_t parity, uint16_t stopBits);
+
+/**
+ * \brief   Config UART loopback function.
+ *
+ * \param[in] UARTx: Select the UART peripheral. \ref UART_Declaration
+ * \param[in] NewState: Enable or disable UART loopback function.
+ *            This parameter can be: ENABLE or DISABLE.
+ *
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void uart_demo(void)
+ * {
+ *     UART_LoopBackCmd(UART0, ENABLE);
+ * }
+ * \endcode
+ */
+void UART_LoopBackCmd(UART_TypeDef *UARTx, FunctionalState NewState);
+
+/**
+ * \brief  Check whether the specified UART flag is set.
+ *
+ * \param[in] UARTx: Select the UART peripheral. \ref UART_Declaration
+ * \param[in] UART_FLAG: Specified UART flag to check.
+ *            This parameter can be one of the following values:
+ *            \arg UART_FLAG_RX_DATA_AVA: Rx data is avaliable.
+ *            \arg UART_FLAG_RX_OVERRUN: Rx FIFO overrun.
+ *            \arg UART_FLAG_RX_PARITY_ERR: Rx parity error.
+ *            \arg UART_FLAG_RX_FRAME_ERR: Rx frame error.
+ *            \arg UART_FLAG_RX_BREAK_ERR: Rx break error.
+ *            \arg UART_FLAG_TX_FIFO_EMPTY: Tx Holding Register or Tx FIFO empty
+ *            \arg UART_FLAG_TX_EMPTY: Tx FIFO and Tx shift register are both empty.
+ *            \arg UART_FLAG_RX_FIFO_ERR: Rx FIFO error.
+ *            \arg UART_FLAG_RX_IDLE: Rx idle.
+ *            \arg UART_FLAG_TX_DONE: Tx waveform done & TX_FIFO_EMPTY = 1.
+ *            \arg UART_FLAG_TX_THD: TX_FIFO_LEVEL<=txfifo_trigger_level.
+ *            \arg UART_FLAG_CTS_TOGGLE: CTS toggle.
+ *
+ * \return New status of UART flag.
+ *         \retval SET: The specified UART flag bit is set.
+ *         \retval RESET: The specified flag is not set.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void uart_senddata_continuous(UART_TypeDef *UARTx, const uint8_t *pSend_Buf, uint16_t vCount)
+ * {
+ *     uint8_t count;
+ *
+ *     while (vCount / UART_TX_FIFO_SIZE > 0)
+ *     {
+ *         while (UART_GetFlagStatus(UARTx, UART_FLAG_TX_FIFO_EMPTY) == 0);
+ *         for (count = UART_TX_FIFO_SIZE; count > 0; count--)
+ *         {
+ *             UARTx->UART_RBR_THR = *pSend_Buf++;
+ *         }
+ *         vCount -= UART_TX_FIFO_SIZE;
+ *     }
+ *
+ *     while (UART_GetFlagStatus(UARTx, UART_FLAG_TX_FIFO_EMPTY) == 0);
+ *     while (vCount--)
+ *     {
+ *         UARTx->UART_RBR_THR = *pSend_Buf++;
+ *     }
+ * }
+ * \endcode
+ */
+FlagStatus UART_GetFlagStatus(UART_TypeDef *UARTx, uint32_t UART_FLAG);
+
+/**
+ * \brief  Check whether the specified UART flag is set.
+ *
+ * \param[in] UARTx: Select the UART peripheral. \ref UART_Declaration
+ *
+ * \return New status of UART flag.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * uint32_t line_status = UART_GetLineStatus(UART_DEMO);
+ *
+ * if (line_status & UART_FLAG)
+ * {
+ *     //Add user code here.
+ * }
+ *
+ * \endcode
+ */
+uint8_t UART_GetLineStatus(UART_TypeDef *UARTx);
+
+/**
+ * \brief   Send one byte of data.
+ *
+ * \param[in] UARTx: Select the UART peripheral. \ref UART_Declaration
+ * \param[in] data: Byte data to send.
+ *
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void uart_demo(void)
+ * {
+ *     uint8_t data = 0x55;
+ *     UART_SendByte(UART0, data);
+ * }
+ * \endcode
+ */
+void UART_SendByte(UART_TypeDef *UARTx, uint8_t data);
+
+#if (UART_SUPPORT_HALF_WORD == 1)
+/**
+ * \brief   Send half word of data.
+ *
+ * \param[in] UARTx: Select the UART peripheral. \ref UART_Declaration
+ * \param[in] data: Byte data to send.
+ *
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void uart_demo(void)
+ * {
+ *     uint8_t data = 0x55;
+ *     UART_SendByte(UART0, data);
+ * }
+ * \endcode
+ */
+void UART_SendHalfWord(UART_TypeDef *UARTx, uint16_t data);
+#endif
+
+/**
+ * \brief   Read a byte of data from UART RX FIFO.
+ *
+ * \param[in] UARTx: Select the UART peripheral. \ref UART_Declaration
+ *
+ * \return  Which byte data has been read.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void uart_demo(void)
+ * {
+ *     uint8_t data = UART_ReceiveByte(UART0);
+ *
+ * }
+ * \endcode
+ */
+uint8_t UART_ReceiveByte(UART_TypeDef *UARTx);
+
+#if (UART_SUPPORT_HALF_WORD == 1)
+/**
+ * \brief   Read a byte of data from UART RX FIFO.
+ *
+ * \param[in] UARTx: Select the UART peripheral. \ref UART_Declaration
+ *
+ * \return  Which byte data has been read.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void uart_demo(void)
+ * {
+ *     uint8_t data = UART_ReceiveByte(UART0);
+ *
+ * }
+ * \endcode
+ */
+uint8_t UART_ReceiveHalfWord(UART_TypeDef *UARTx);
+#endif
+
+/**
+ * \brief   Get interrupt identifier of the selected UART peripheral.
+ *
+ * \param[in] UARTx: Select the UART peripheral. \ref UART_Declaration
+ *
+ * \return The interrupt identifier value.
+ *         This return value can be one or a combination of the following:
+ *         \retval UART_INT_ID_LINE_STATUS: Rx line status interrupt ID.
+ *         \retval UART_INT_ID_RX_LEVEL_REACH: Rx data available or trigger level reached interrupt ID.
+ *         \retval UART_INT_ID_RX_DATA_TIMEOUT: Rx FIFO data timeout interrupt ID.
+ *         \retval UART_INT_ID_TX_FIFO_EMPTY: Tx FIFO empty interrupt ID.
+ *         \retval UART_INT_ID_MODEM_STATUS: Modem status interrupt ID.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void UART0_Handler()
+ * {
+ *     uint16_t rx_len = 0;
+ *     uint8_t uart_rev_data[32];
+ *
+ *     //Get interrupt ID.
+ *     uint32_t int_status = UART_GetIID(UART0);
+ *
+ *     //Disable interrupt.
+ *     UART_INTConfig(UART0, UART_INT_RD_AVA, DISABLE);
+ *
+ *     if (UART_GetFlagStatus(UART0, UART_FLAG_RX_IDLE) == SET)
+ *     {
+ *         UART_INTConfig(UART0, UART_INT_RX_IDLE, DISABLE);
+ *         //Add user code here.
+ *         UART_ClearRxFIFO(UART0);
+ *         UART_INTConfig(UART0, UART_INT_RX_IDLE, ENABLE);
+ *     }
+ *
+ * }
+ * \endcode
+ */
+uint16_t UART_GetIID(UART_TypeDef *UARTx);
+
+#if (UART_SUPPORT_CLEAR_TX_FIFO == 1)
+/**
+ * \brief   Clear Tx FIFO of the selected UART peripheral.
+ *
+ * \param[in] UARTx: Select the UART peripheral. \ref UART_Declaration
+ *
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void uart_demo(void)
+ * {
+ *     UART_ClearTxFIFO(UART0);
+ * }
+ * \endcode
+ */
+void UART_ClearTxFIFO(UART_TypeDef *UARTx);
+#endif
+
+/**
+ * \brief   Clear Rx FIFO of the selected UART peripheral.
+ *
+ * \param[in] UARTx: Select the UART peripheral. \ref UART_Declaration
+ *
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void uart_demo(void)
+ * {
+ *     UART_ClearRxFIFO(UART0);
+ * }
+ * \endcode
+ */
+void UART_ClearRxFIFO(UART_TypeDef *UARTx);
+
+/**
+ * \brief   Get the data length in Tx FIFO of the selected UART peripheral.
+ *
+ * \param[in] UARTx: Select the UART peripheral. \ref UART_Declaration
+ *
+ * \return  Data length in UART TX FIFO.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void uart_demo(void)
+ * {
+ *     uint8_t data_len = UART_GetTxFIFODataLen(UART0);
+ * }
+ * \endcode
+ */
+uint8_t UART_GetTxFIFODataLen(UART_TypeDef *UARTx);
+
+/**
+ * \brief   Get the data length in Rx FIFO of the selected UART peripheral.
+ *
+ * \param[in] UARTx: Select the UART peripheral. \ref UART_Declaration
+ *
+ * \return  Data length in UART RX FIFO.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void uart_demo(void)
+ * {
+ *     uint8_t data_len = UART_GetRxFIFODataLen(UART0);
+ * }
+ * \endcode
+ */
+uint8_t UART_GetRxFIFODataLen(UART_TypeDef *UARTx);
+
+/**
+ * \brief    Enable/Disable DMA mode on UART side.
+ *
+ * \param[in] UARTx: Select the UART peripheral. \ref UART_Declaration
+ * \param[in] NewState: Enable or disable UART DMA mode.
+ *            This parameter can be one of the following values:
+ *            \arg true: Enable UART DMA mode.
+ *            \arg false: Disable UART DMA mode.
+ *
+ * \return   None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * void driver_uart_init(void)
+ * {
+ *     UART_TxDMACmd(UART_DEMO, false);
+ * }
+ * \endcode
+ */
+void UART_TxDMACmd(UART_TypeDef *UARTx, FunctionalState NewState);
+
+/**
+ * \brief    Enable/Disable DMA mode on UART side.
+ *
+ * \param[in] UARTx: Select the UART peripheral. \ref UART_Declaration
+ * \param[in] NewState: Enable or disable UART DMA mode.
+ *            This parameter can be one of the following values:
+ *            \arg true: Enable UART DMA mode.
+ *            \arg false: Disable UART DMA mode.
+ *
+ * \return   None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * void driver_uart_init(void)
+ * {
+ *     UART_RxDMACmd(UART_DEMO, false);
+ * }
+ * \endcode
+ */
+void UART_RxDMACmd(UART_TypeDef *UARTx, FunctionalState NewState);
+
+/**
+ * \brief   UART one wire config.
+ *
+ * \param[in] UARTx: Select the UART peripheral. \ref UART_Declaration
+ * \param[in] NewState: UART one wire config is set or not.
+ *            This parameter can be one of the following values:
+ *            \arg true: UART one wire config is set.
+ *            \arg false: UART one wire config is unset.
+ *
+ * \return   None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * void uart_demo(void)
+ * {
+ *     UART_OneWireConfig(UART0, true);
+ * }
+ * \endcode
+ */
+void UART_OneWireConfig(UART_TypeDef *UARTx, FunctionalState NewState);
+
+/**
+ * \brief  UART clock divider config.
+ *
+ * \param[in] UARTx: Select the UART peripheral. \ref UART_Declaration
+ * \param[in] ClockDiv: Specifies the UART clock divider.
+ *            This parameter can be one of the following values:
+ *            \arg CLOCK_DIV_x: where x can refer to CLock Divider to select the specified clock divider
+ *
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_i2c_init(void)
+ * {
+ *     RCC_UARTClkDivConfig(UART0, CLOCK_DIV_1);
+ * }
+ * \endcode
+ */
+void UART_SetClock(UART_TypeDef *UARTx, uint16_t ClockSrc, uint16_t ClockDiv);
+
+#if (UART_SUPPORT_AUTO_CLOCK == 1)
+
+void UART_ClockAutoModeCmd(UART_TypeDef *UARTx, FunctionalState Newstate);
+
+#endif
+
+/**
+ *
+ * \brief   Clear the specified UART flag, Only UART_FLAG_RX_IDLE need to be cleared manually, other interrupt flag cannot be cleared.
+ *
+ * \param[in]   UARTx: UART peripheral selected, x can be 0 ~ 3.
+ * \param[in]   UART_FLAG: Specified UART flag to check.
+ *      This parameter can be one of the following values:
+ *      \arg  UART_FLAG_RX_IDLE: interrupt status of RX IDLE timeout.
+ *      \arg  UART_FLAG_CTS_TOGGLE: Clear the CTS toggle interrupt.
+ *
+ * \return   New state of UART flag.
+ * \retval SET: The specified UART flag bit is set.
+ * \retval RESET: The specified flag is not set.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * void uart_handler(void)
+ * {
+ *     if(UART_GetFlagStatus(UART2, UART_FLAG_RX_IDLE) == SET)
+ *     {
+ *          UART_ClearINT(UART2, UART_FLAG_RX_IDLE);
+ *     }
+ * }
+ * \endcode
+ */
+void UART_ClearINT(UART_TypeDef *UARTx, uint32_t UART_FLAG);
+
+#if (UART_SUPPORT_RAP_FUNCTION == 1)
+/**
+ *
+ * \brief   Enable or disable UART RAP mode.
+ *
+ * \param[in]   UARTx: UART peripheral selected, x can be 0 ~ 3.
+ * \param[in] NewState: UART RAP mode is enable or disable.
+ *            This parameter can be one of the following values:
+ *            \arg ENABLE: Enable RAP mode.
+ *            \arg DISABLE: DIsable RAP mode.
+ *
+ * \return   New state of UART flag.
+ * \retval true: Config RAP mode success.
+ * \retval false: The UART is not support RAP mode.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * void uart_demo(void)
+ * {
+ *     UART_RAPModeCmd(UART0, ENABLE);
+ * }
+ * \endcode
+ */
+bool UART_RAPModeCmd(UART_TypeDef *UARTx, FunctionalState NewState);
+#endif
+
+#if (UART_SUPPORT_CTS_TOGGLE == 1)
+/**
+ *
+ * \brief   Get the CTS level of UART.
+ *
+ * \param[in]   UARTx: UART peripheral selected, x can be 0 ~ 3.
+ *
+ * \return   Level of CTS.
+ * \retval SET: CTS is high.
+ * \retval RESET: CTS is low.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * void uart_demo(void)
+ * {
+ *     UART_GetCTSStatus(UART0);
+ * }
+ * \endcode
+ */
+uint8_t UART_GetCTSLevel(UART_TypeDef *UARTx);
+#endif
+
+uint32_t UART_GetBaudSettings(uint32_t baudrate,
+                              uint8_t data_width, uint8_t parity, uint8_t stop_bits,
+                              uint16_t *div, uint16_t *ovsr, uint16_t *adj);
+
+/**
+ *
+ * \brief   Enable/Disable TX-only mode for UART.
+ *
+ * \param[in]   UARTx: UART peripheral selected, x can be 0 ~ 3.
+ * \param[in]   NewState: New state of the TX-only mode.
+ *      This parameter can be one of the following values:
+ *      - ENABLE: Enable TX-only mode, disables RX functionality.
+ *      - DISABLE: Disable TX-only mode, enable normal UART RX/TX mode.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * void uart_tx_only_demo(void)
+ * {
+ *     UART_TxOnlyModeCmd(UART0, ENABLE);  // Enable TX-only mode
+ *     // ... send data ...
+ *     UART_TxOnlyModeCmd(UART0, DISABLE); // Disable TX-only mode
+ * }
+ * \endcode
+ */
+void UART_TxOnlyModeCmd(UART_TypeDef *UARTx, FunctionalState NewState);
+/** End of UART_Exported_Functions
+  * \}
+  */
+
+/** End of UART
+  * \}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RTL_UART_H */
+
+
+
diff --git a/bee/drivers/uart/src/CMakeLists.txt b/bee/drivers/uart/src/CMakeLists.txt
new file mode 100644
index 00000000..dd5e359a
--- /dev/null
+++ b/bee/drivers/uart/src/CMakeLists.txt
@@ -0,0 +1,4 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+add_subdirectory(device)
diff --git a/bee/drivers/uart/src/device/CMakeLists.txt b/bee/drivers/uart/src/device/CMakeLists.txt
new file mode 100644
index 00000000..390b5305
--- /dev/null
+++ b/bee/drivers/uart/src/device/CMakeLists.txt
@@ -0,0 +1,11 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+if(CONFIG_REALTEK_BEE_COMMON_DRIVER)
+    file(GLOB BEE_DRIVER_COMMON_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/rtl_common/*.c")
+    zephyr_library_sources(${BEE_DRIVER_COMMON_SOURCES})
+endif()
+
+add_soc_series_subdir(rtl8752h)
+add_soc_series_subdir(rtl87x2g)
+add_soc_series_subdir(rtl87x2j)
diff --git a/bee/drivers/uart/src/device/rtl8752h/rtl876x_uart.c b/bee/drivers/uart/src/device/rtl8752h/rtl876x_uart.c
new file mode 100644
index 00000000..49f91989
--- /dev/null
+++ b/bee/drivers/uart/src/device/rtl8752h/rtl876x_uart.c
@@ -0,0 +1,501 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "rtl876x_rcc.h"
+#include "rtl876x_uart.h"
+#include "app_section.h"
+
+#define LCR_DLAB_Set                    ((uint32_t)(1 << 7))
+#define LCR_DLAB_Reset                  ((uint32_t)~(1 << 7))
+
+/**
+  * @brief  Deinitializes the UART peripheral registers to their default reset values(turn off UART clock).
+  * @param  UARTx: selected UART peripheral.
+  * @retval None
+  */
+void UART_DeInit(UART_TypeDef *UARTx)
+{
+    assert_param(IS_UART_PERIPH(UARTx));
+
+    if (UARTx == UART0)
+    {
+        RCC_PeriphClockCmd(APBPeriph_UART0, APBPeriph_UART0_CLOCK, DISABLE);
+    }
+    else if (UARTx == UART1)
+    {
+        RCC_PeriphClockCmd(APBPeriph_UART1, APBPeriph_UART1_CLOCK, DISABLE);
+    }
+    else if (UARTx == UART2)
+    {
+        RCC_PeriphClockCmd(APBPeriph_UART2, APBPeriph_UART2_CLOCK, DISABLE);
+    }
+
+    return;
+}
+
+/**
+  * @brief Initializes the UART peripheral according to the specified
+  *   parameters in the UART_InitStruct
+  * @param  UARTx: selected UART peripheral.
+  * @param  UART_InitStruct: pointer to a UART_InitTypeDef structure that
+  *   contains the configuration information for the specified UART peripheral
+  * @retval None
+  */
+void UART_Init(UART_TypeDef *UARTx, UART_InitTypeDef *UART_InitStruct)
+{
+    assert_param(IS_UART_PERIPH(UARTx));
+    assert_param(IS_UART_WORD_LENGTH(UART_InitStruct->UART_WordLen));
+    assert_param(IS_UART_STOPBITS(UART_InitStruct->UART_StopBits));
+    assert_param(IS_UART_PARITY(UART_InitStruct->UART_Parity));
+    assert_param(IS_UART_RX_FIFO_TRIGGER_LEVEL(UART_InitStruct->UART_RxThdLevel));
+    assert_param(IS_UART_IDLE_TIME(UART_InitStruct->UART_IdleTime));
+    assert_param(IS_UART_DMA_CFG(UART_InitStruct->UART_DmaEn));
+    assert_param(IS_UART_AUTO_FLOW_CTRL(UART_InitStruct->UART_HardwareFlowControl));
+
+    //clear DLAB bit
+    UARTx->LCR &= LCR_DLAB_Reset;
+    //disable all interrupt
+    UARTx->DLH_INTCR = 0x00;
+
+    //read to clear Line Status Reg
+    (void)UARTx->LSR;
+    //clear FIFO
+    UARTx->INTID_FCR |= (FCR_CLEAR_RX_FIFO_Set | FCR_CLEAR_TX_FIFO_Set);
+
+    //set baudrate, firstly set DLAB bit
+    UARTx->LCR |= LCR_DLAB_Set;
+    //set calibration parameters(OVSR)
+    UARTx->STSR &= ~0xF0;
+    UARTx->STSR |= (UART_InitStruct->UART_Ovsr << 4);
+    //set calibration parameters(OVSR_adj)
+    UARTx->SPR &= (~(0x7ff << 16));
+    UARTx->SPR |= (UART_InitStruct->UART_OvsrAdj << 16);
+    //set DLL and DLH
+    UARTx->DLL = (UART_InitStruct->UART_Div & 0x00FF);
+    UARTx->DLH_INTCR = ((UART_InitStruct->UART_Div & 0xFF00) >> 8);
+    //after set baudrate, clear DLAB bit
+    UARTx->LCR &= LCR_DLAB_Reset;
+
+    //set LCR reg
+    UARTx->LCR = (UART_InitStruct->UART_Parity | UART_InitStruct->UART_StopBits |
+                  UART_InitStruct->UART_WordLen);
+    //set FCR reg, FIFO must enable
+    UARTx->INTID_FCR = ((1 << 0) | UART_InitStruct->UART_TxThdLevel << 16 \
+                        | UART_InitStruct->UART_RxThdLevel << 8 | UART_InitStruct->UART_DmaEn);
+
+    /* harware flow control */
+    UARTx->MCR &= (~((1 << 5) | (1 << 1)));
+    UARTx->MCR |= UART_InitStruct->UART_HardwareFlowControl;
+
+    /* set rx idle time */
+    UARTx->RX_IDLE_TOCR = (UART_InitStruct->UART_IdleTime);
+
+    /* Config UART Tx/Rx dma parameter */
+    UARTx->MISCR &= ~(0x1f << 3 | 0x3f << 8 | BIT(1) | BIT(2));
+
+    if (UART_InitStruct->UART_TxDmaEn != DISABLE)
+    {
+        UARTx->MISCR |= BIT(1);
+    }
+
+    if (UART_InitStruct->UART_RxDmaEn != DISABLE)
+    {
+        UARTx->MISCR |= BIT(2);
+    }
+
+    UARTx->MISCR |= ((UART_InitStruct->UART_TxWaterLevel) << 3) | (UART_InitStruct->UART_RxWaterLevel <<
+                                                                   8);
+
+    return;
+}
+
+/**
+  * @brief  Fills each UART_InitStruct member with its default value.
+  * @param  UART_InitStruct: pointer to an UART_InitTypeDef structure which will be initialized.
+  * @retval None
+  */
+void UART_StructInit(UART_InitTypeDef *UART_InitStruct)
+{
+    //115200 default
+    UART_InitStruct->UART_Div               = 20;
+    UART_InitStruct->UART_Ovsr              = 12;
+    UART_InitStruct->UART_OvsrAdj           = 0x252;
+
+    UART_InitStruct->UART_WordLen           = UART_WORD_LENGTH_8BIT;
+    UART_InitStruct->UART_StopBits          = UART_STOP_BITS_1;
+    UART_InitStruct->UART_Parity            = UART_PARITY_NO_PARTY;
+    UART_InitStruct->UART_TxThdLevel        = 16; //1~29
+    UART_InitStruct->UART_RxThdLevel        = 16; //1~29
+    UART_InitStruct->UART_IdleTime          = UART_RX_IDLE_2BYTE; //idle interrupt wait time
+    UART_InitStruct->UART_HardwareFlowControl   = UART_HW_FLOW_CTRL_DISABLE;
+    UART_InitStruct->UART_DmaEn                 = UART_DMA_DISABLE;
+    UART_InitStruct->UART_TxDmaEn               = DISABLE;
+    UART_InitStruct->UART_RxDmaEn               = DISABLE;
+    UART_InitStruct->UART_TxWaterLevel          = 15; //Better to equal TX_FIFO_SIZE(16)- GDMA_MSize
+    UART_InitStruct->UART_RxWaterLevel          = 1; //Better to equal GDMA_MSize
+    return;
+}
+
+/**
+  * @brief  Mask or unmask the specified UART interrupts.
+  * @param  UART_INT: specifies the IR interrupts sources to be mask or unmask.
+  *     This parameter can be the following values:
+  *     @arg UART_INT_MASK_RD_AVA: mask INTCR(erbi).
+  *     @arg UART_INT_MASK_TX_FIFO_EMPTY: mask INTCR(etbei).
+  *     @arg UART_INT_MASK_RX_LINE_STS: mask INTCR(elsi).
+  *     @arg UART_INT_MASK_MODEM_STS: mask INTCR(edssi).
+  *     @arg UART_INT_MASK_RX_BREAK: mask rx break interrupt.
+  *     @arg UART_INT_MASK_RX_IDLE: mask rx idle interrupt.
+  *     @arg UART_INT_MASK_TX_DONE: mask the interrupt tx done interrupt.
+  *     @arg UART_INT_MASK_TX_THD: mask tx fifo threshold interrupt.
+  * @param  NewState: new state of the specified UART interrupts.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void UART_MaskINTConfig(UART_TypeDef *UARTx, uint32_t UART_INT_MASK, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+    assert_param(IS_UART_INT_MASK(UART_INT_MASK));
+    assert_param(IS_FUNCTIONAL_STATE(newState));
+
+    if (NewState != DISABLE)
+    {
+        UARTx->INTMASK |= UART_INT_MASK;
+    }
+    else
+    {
+        UARTx->INTMASK &= ~(UART_INT_MASK);
+    }
+}
+
+/**
+  * @brief  Enables or disables the specified UART interrupts.
+  * @param  UARTx: selected UARTx peripheral.
+  * @param  UART_INT: specifies the UART interrupts sources to be enabled or disabled.
+  *     This parameter can be any combination of the following values:
+  *     @arg UART_INT_RD_AVA: Rx data avaliable interrupt source.
+  *     @arg UART_INT_TX_FIFO_EMPTY: Tx FIFO empty interrupt source.
+  *     @arg UART_INT_RX_LINE_STS: Rx line status interrupt source.
+  *     @arg UART_INT_MODEM_STS: modem status interrupt source.
+  *     @arg UART_INT_TX_DONE: Tx data done interrupt source.
+  *     @arg UART_INT_TX_THD: Tx FIFO data <= thredhold interrupt source.
+  *     @arg UART_INT_RX_BREAK: Rx break signal interrupt source.
+  *     @arg UART_INT_RX_IDLE: Rx idle interrupt source.
+  * @param  NewState: new state of the specified UART interrupts.
+  *     This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void UART_INTConfig(UART_TypeDef *UARTx, uint32_t UART_INT, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+    assert_param(IS_UART_INT(UART_INT));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (UART_INT & UART_INT_RX_IDLE)
+    {
+        if (NewState == ENABLE)
+        {
+            UARTx->RX_IDLE_INTSR |= BIT0;
+            UARTx->RX_IDLE_INTCR |= BIT0;
+            UARTx->RX_IDLE_TOCR |= BIT31;
+        }
+        else
+        {
+            UARTx->RX_IDLE_TOCR &= (~BIT31);
+            UARTx->RX_IDLE_INTCR &= (~BIT0);
+        }
+    }
+
+    if (UART_INT & UART_INT_RX_BREAK)
+    {
+        if (NewState == ENABLE)
+        {
+            UARTx->SPR |= BIT6;
+        }
+        else
+        {
+            UARTx->SPR &= (~BIT6);
+        }
+    }
+
+    if (UART_INT & 0x3F)
+    {
+        if (NewState == ENABLE)
+        {
+            /* Enable the selected UARTx interrupts */
+            UARTx->DLH_INTCR |= UART_INT;
+        }
+        else
+        {
+            /* Disable the selected UARTx interrupts */
+            UARTx->DLH_INTCR &= (uint32_t)~UART_INT;
+        }
+    }
+    return;
+}
+
+/**
+  * @brief  Send data to tx FIFO.
+  * @param  UARTx: selected UART peripheral.
+  * @param  inBuf: buffer to be written to Tx FIFO.
+  * @param  num: number of data to be written.
+  * @retval None
+  */
+void UART_SendData(UART_TypeDef *UARTx, const uint8_t *inBuf, uint16_t num)
+{
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+
+    while (num--)
+    {
+        UARTx->RB_THR = *inBuf++;
+    }
+
+    return;
+}
+
+/**
+  * @brief  Receive data from rx FIFO.
+  * @param  UARTx: selected UART peripheral.
+  * @param[out]  outBuf: buffer to save data read from UART FIFO.
+  * @param  count: number of data to be read.
+  * @retval None
+  */
+void UART_ReceiveData(UART_TypeDef *UARTx, uint8_t *outBuf, uint16_t count)
+{
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+
+    while (count--)
+    {
+        *outBuf++ = (uint8_t)UARTx->RB_THR;
+    }
+
+    return;
+}
+
+/**
+  *@brief  Change UART baudrate.
+  *@param  UARTx: selected UART peripheral.
+  *@param  div: parameter of the selected UART baudrate.
+  *@param  ovsr: parameter of the selected UART baudrate.
+  *@param  ovsr_adj: parameter of the selected UART baudrate.
+  *@retval None.
+  */
+void UART_SetBaudRate(UART_TypeDef *UARTx, uint16_t div, uint16_t ovsr, uint16_t ovsr_adj)
+{
+    //set baudrate, firstly set DLAB bit
+    UARTx->LCR |= LCR_DLAB_Set;
+
+    //set calibration parameters(OVSR)
+    UARTx->STSR &= ~0xF0;
+    UARTx->STSR |= (ovsr << 4);
+    //set calibration parameters(OVSR_adj)
+    UARTx->SPR &= (~(0x7ff << 16));
+    UARTx->SPR |= (ovsr_adj << 16);
+    //set DLL and DLH
+    UARTx->DLL = (div & 0x00FF);
+    UARTx->DLH_INTCR = ((div & 0xFF00) >> 8);
+
+    //after set baudrate, clear DLAB bit
+    UARTx->LCR &= LCR_DLAB_Reset;
+}
+
+/**
+  *@brief  Set UART parameters.
+  *@param  UARTx: selected UART peripheral.
+  *@param  wordLen: data width of selected UART peripheral.
+  *@param  parity: parity of selected UART peripheral.
+  *@param  stopBits: stop bit of selected UART peripheral.
+  *@retval None
+  */
+void UART_SetParams(UART_TypeDef *UARTx, uint16_t wordLen, uint16_t parity, uint16_t stopBits)
+{
+    //set LCR reg
+    UARTx->LCR = (wordLen | stopBits | parity);
+}
+
+/**
+  *@brief  UART loop back mode config.
+  *@param  UARTx: selected UART peripheral.
+  *@param  NewState: new state of the DMA Channelx.
+  *        This parameter can be: ENABLE or DISABLE.
+  *@retval None.
+  */
+void UART_LoopBackCmd(UART_TypeDef *UARTx, FunctionalState NewState)
+{
+    assert_param(IS_UART_PERIPH(UARTx));
+
+    if (NewState == ENABLE)
+    {
+        UARTx->MCR |= BIT4;
+    }
+    else
+    {
+        UARTx->MCR &= ~BIT4;
+    }
+}
+
+/**
+  * @brief  Checks whether the specified UART flag is set or not.
+  * @param  UARTx: selected UART peripheral.
+  * @param  UART_FLAG: specifies the flag to check.
+  *     This parameter can be one of the following values:
+  *     @arg UART_FLAG_RX_DATA_RDY: rx data is avaliable.
+  *     @arg UART_FLAG_RX_OVERRUN: rx overrun.
+  *     @arg UART_FLAG_PARTY_ERR: parity error.
+  *     @arg UART_FLAG_FRAME_ERR: UARTx frame error.
+  *     @arg UART_FLAG_BREAK_ERR: UARTx break error.
+  *     @arg UART_FLAG_THR_EMPTY: tx FIFO is empty.
+  *     @arg UART_FLAG_THR_TSR_EMPTY: tx FIFO and tx shift reg are both empty.
+  *     @arg UART_FLAG_RX_FIFO_ERR: rx FIFO error.
+  *     @arg UART_FLAG_RX_IDLE.
+  * @retval The new state of UART_FLAG (SET or RESET).
+  */
+FlagStatus UART_GetFlagStatus(UART_TypeDef *UARTx, uint32_t UART_FLAG)
+{
+    FlagStatus bitstatus = RESET;
+
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+    assert_param(IS_UART_GET_FLAG(UART_FLAG));
+
+    if (UART_FLAG == UART_FLAG_TX_THD)
+    {
+        if (UARTx->TX_THR_INTSR & BIT(0))
+        {
+            bitstatus = SET;
+        }
+    }
+    else if (UART_FLAG == UART_FLAG_TX_DONE)
+    {
+        if (UARTx->TX_DONE_INTSR & BIT(0))
+        {
+            bitstatus = SET;
+        }
+    }
+    else if (UART_FLAG == UART_FLAG_RX_IDLE)
+    {
+        if (UARTx->RX_IDLE_INTSR & BIT(0))
+        {
+            bitstatus = SET;
+        }
+    }
+    else if (UART_FLAG == UART_FLAG_RX_BREAK)
+    {
+        if (UARTx->SPR & BIT(7))
+        {
+            bitstatus = SET;
+        }
+    }
+
+    else
+    {
+        if (UARTx->LSR & UART_FLAG)
+        {
+            bitstatus = SET;
+        }
+    }
+
+    return bitstatus;
+}
+
+/**
+  * \brief  Store UART register values when system enter DLPS.
+  * \param  PeriReg: Specifies to select the UART peripheral.
+  * \param  StoreBuf: Store buffer to store UART register data.
+  * \return None.
+  */
+DATA_RAM_FUNCTION
+void UART_DLPSEnter(void *PeriReg, void *StoreBuf)
+{
+    UART_TypeDef *UARTx = (UART_TypeDef *)PeriReg;
+    UARTStoreReg_TypeDef *store_buf = (UARTStoreReg_TypeDef *)StoreBuf;
+
+    if (UARTx == UART0)
+    {
+        RCC_PeriphClockCmd(APBPeriph_UART0, APBPeriph_UART0_CLOCK, ENABLE);
+    }
+    else if (UARTx == UART1)
+    {
+        RCC_PeriphClockCmd(APBPeriph_UART1, APBPeriph_UART1_CLOCK, ENABLE);
+    }
+    else if (UARTx == UART2)
+    {
+        RCC_PeriphClockCmd(APBPeriph_UART2, APBPeriph_UART2_CLOCK, ENABLE);
+    }
+
+    //access DLH and DLL
+    UARTx->LCR |= (1 << 7);
+    store_buf->uart_reg[0] = UARTx->DLL;
+    store_buf->uart_reg[1] = UARTx->DLH_INTCR;
+    UARTx->LCR &= (~(1 << 7));
+
+    //save other registers
+    store_buf->uart_reg[2]  = UARTx->DLH_INTCR;
+    store_buf->uart_reg[4]  = UARTx->LCR;
+    store_buf->uart_reg[5]  = UARTx->MCR;
+    store_buf->uart_reg[6]  = UARTx->SPR;
+    store_buf->uart_reg[7]  = UARTx->STSR;
+    store_buf->uart_reg[8]  = UARTx->RX_IDLE_TOCR;
+    store_buf->uart_reg[9]  = UARTx->RX_IDLE_INTCR;
+    store_buf->uart_reg[10] = UARTx->MISCR;
+    store_buf->uart_reg[11] = UARTx->INTMASK;
+
+    return;
+}
+
+/**
+  * \brief  Restore UART register values when system exit DLPS.
+  * \param  PeriReg: Specifies to select the UART peripheral.
+  * \param  StoreBuf: Restore buffer to restore UART register data.
+  * \return None
+  */
+DATA_RAM_FUNCTION
+void UART_DLPSExit(void *PeriReg, void *StoreBuf)
+{
+    UART_TypeDef *UARTx = (UART_TypeDef *)PeriReg;
+    UARTStoreReg_TypeDef *store_buf = (UARTStoreReg_TypeDef *)StoreBuf;
+
+    if (UARTx == UART0)
+    {
+        RCC_PeriphClockCmd(APBPeriph_UART0, APBPeriph_UART0_CLOCK, ENABLE);
+    }
+    else if (UARTx == UART1)
+    {
+        RCC_PeriphClockCmd(APBPeriph_UART1, APBPeriph_UART1_CLOCK, ENABLE);
+    }
+    else if (UARTx == UART2)
+    {
+        RCC_PeriphClockCmd(APBPeriph_UART2, APBPeriph_UART2_CLOCK, ENABLE);
+    }
+
+    //access DLH and DLL
+    UARTx->LCR          |= (1 << 7);
+    UARTx->STSR          = store_buf->uart_reg[7];
+    UARTx->SPR           = store_buf->uart_reg[6];
+    UARTx->DLL           = store_buf->uart_reg[0];
+    UARTx->DLH_INTCR     = store_buf->uart_reg[1];
+    UARTx->LCR &= (~(1 << 7));
+
+    //access other registers
+    UARTx->INTID_FCR = (((store_buf->uart_reg[7] & BIT24) >> 21) | ((store_buf->uart_reg[7] &
+                                                                     0x7C000000) >> 18) |
+                        (1));
+    UARTx->LCR           = store_buf->uart_reg[4];
+    UARTx->MCR           = store_buf->uart_reg[5];
+    UARTx->DLH_INTCR     = store_buf->uart_reg[2];
+    UARTx->RX_IDLE_TOCR  = store_buf->uart_reg[8];
+    UARTx->RX_IDLE_INTCR = store_buf->uart_reg[9];
+    UARTx->MISCR         = store_buf->uart_reg[10];
+    UARTx->INTMASK       = store_buf->uart_reg[11];
+
+    return;
+}
+
+
diff --git a/bee/drivers/uart/src/device/rtl8752h/rtl876x_uart.h b/bee/drivers/uart/src/device/rtl8752h/rtl876x_uart.h
new file mode 100644
index 00000000..2744111e
--- /dev/null
+++ b/bee/drivers/uart/src/device/rtl8752h/rtl876x_uart.h
@@ -0,0 +1,892 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _RTL876X_UART_H_
+#define _RTL876X_UART_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup  IO          Peripheral Drivers
+ * \defgroup    UART        UART
+ *
+ * \brief       Manage the UART peripheral functions.
+ *
+ * \ingroup     IO
+ */
+
+/*============================================================================*
+ *                         Includes
+ *============================================================================*/
+#include "rtl876x.h"
+#include "rtl876x_alias.h"
+
+/*============================================================================*
+ *                         Types
+ *============================================================================*/
+/**
+ * \defgroup    UART_Exported_Types     UART Exported Types
+ *
+ * \ingroup     UART
+ */
+
+/**
+ * \brief       UART initialization parameters
+ * \ingroup     UART_Exported_Types
+ */
+typedef struct
+{
+    //baudrate calibration
+    uint16_t UART_OvsrAdj;              /*!< Specify the baud rate setting, ovsr_adj. Refer to the baud rate setting table. */
+    uint16_t UART_Div;                  /*!< Specify the baud rate setting, div. Refer to the baud rate setting table. */
+    uint16_t UART_Ovsr;                 /*!< Specify the baud rate setting, ovsr. Refer to the baud rate setting table. */
+    uint16_t UART_WordLen;              /*!< Specify the UART Word length.
+                                             This parameter can be a value of \ref UART_Word_Length. */
+    uint16_t UART_StopBits;             /*!< Specify the stop bit.
+                                             This parameter can be a value of \ref UART_Stop_Bits. */
+    uint16_t UART_Parity;               /*!< Specify the parity.
+                                             This parameter can be a value of \ref UART_Parity. */
+    uint16_t UART_TxThdLevel;           /*!< Specify the Tx threshold level.
+                                             This parameter must range from 1 to 16. */
+    uint16_t UART_RxThdLevel;           /*!< Specify the Rx threshold level.
+                                             This parameter must range from 1 to 31. */
+    uint16_t UART_IdleTime;             /*!< Specify the idle time.
+                                             This parameter can be a value of \ref UART_Rx_Idle_Time. */
+    uint16_t UART_HardwareFlowControl;  /*!< Specify the hardware flow control.
+                                             This parameter can be a value of \ref UART_Hardware_Flow_Control. */
+    uint16_t UART_DmaEn;                /*!< Specify the DMA mode.
+                                             This parameter can be DISABLE or ENABLE. */
+    uint16_t UART_TxDmaEn;              /*!< Specify the Tx DMA mode.
+                                             This parameter can be DISABLE or ENABLE.
+                                             This bit field controls the level at which a DMA request is made by the transmit logic.
+                                             (TX FIFO depth - TX_FIFO_LEVEL) >= UART_TxWaterLevel, that is, the dma_tx_req signal is
+                                             generated when the number of free entries in the transmit FIFO is equal to or above this field value. */
+    uint16_t UART_RxDmaEn;              /*!< Specify the Rx DMA mode.
+                                             This parameter can be DISABLE or ENABLE.
+                                             This Function controls the level at which a DMA request is made by the receive logic.
+                                             RX_FIFO_LEVEL >= UART_RxWaterLevel ; that is, dma_rx_req is generated when the number of
+                                             valid data entries in the receive FIFO is equal to or above this field value. */
+    uint8_t UART_TxWaterLevel;          /*!< Specify the DMA Tx water level.
+                                             This parameter must range from 1 to 16. */
+    uint8_t UART_RxWaterLevel;          /*!< Specify the DMA Rx water level.
+                                             This parameter must range from 1 to 31. */
+} UART_InitTypeDef;
+
+/** End of UART_Exported_Types
+  * \}
+  */
+
+/*============================================================================*
+ *                         Constants
+ *============================================================================*/
+/**
+ * \defgroup    UART_Exported_Constants     UART Exported Constants
+ *
+ * \ingroup     UART
+ */
+
+/**
+ * \defgroup    UART_Config UART Config
+ * \{
+ * \ingroup     UART_Exported_Constants
+ */
+#define IS_UART_PERIPH(PERIPH) (((PERIPH) == UART0) || ((PERIPH) == UART1) || ((PERIPH) == UART2))
+
+#define UART_TX_FIFO_SIZE           16
+#define UART_RX_FIFO_SIZE           32
+#define UART_TX_FIFO_ADDR(UARTx)    (uint32_t)(&(((UART_TypeDef *)(UARTx))->RB_THR))
+#define UART_RX_FIFO_ADDR(UARTx)    (uint32_t)(&(((UART_TypeDef *)(UARTx))->RB_THR))
+/** \} */
+
+/**
+ * \defgroup    UART_BAUD_RATE_Define UART BAUD RATE Define
+ * \{
+ * \ingroup     UART_Exported_Constants
+ */
+typedef enum
+{
+    UART_BAUD_RATE_1200,
+    UART_BAUD_RATE_9600,
+    UART_BAUD_RATE_14400,
+    UART_BAUD_RATE_19200,
+    UART_BAUD_RATE_28800,
+    UART_BAUD_RATE_38400,
+    UART_BAUD_RATE_57600,
+    UART_BAUD_RATE_76800,
+    UART_BAUD_RATE_115200,
+    UART_BAUD_RATE_128000,
+    UART_BAUD_RATE_153600,
+    UART_BAUD_RATE_230400,
+    UART_BAUD_RATE_460800,
+    UART_BAUD_RATE_500000,
+    UART_BAUD_RATE_921600,
+    UART_BAUD_RATE_1000000,
+    UART_BAUD_RATE_1382400,
+    UART_BAUD_RATE_1444400,
+    UART_BAUD_RATE_1500000,
+    UART_BAUD_RATE_1843200,
+    UART_BAUD_RATE_2000000,
+    UART_BAUD_RATE_3000000,
+    UART_BAUD_RATE_4000000,
+    UART_BAUD_RATE_6000000
+} UartBaudRate_TypeDef;
+/** \} */
+
+/**
+ * \defgroup   UART_Interrupts_Definition  UART Interrupts Definition
+ * \{
+ * \ingroup     UART_Exported_Constants
+ */
+
+#define UART_INT_RD_AVA                         ((uint16_t)(1 << 0)) // Receive data available
+#define UART_INT_TX_FIFO_EMPTY                  ((uint16_t)(1 << 1))
+#define UART_INT_RX_LINE_STS                    ((uint16_t)(1 << 2))
+#define UART_INT_TX_DONE                        ((uint16_t)(1 << 4))
+#define UART_INT_TX_THD                         ((uint16_t)(1 << 5))
+#define UART_INT_RX_BREAK                       ((uint16_t)(1 << 6))
+#define UART_INT_RX_IDLE                        ((uint16_t)(1 << 7))
+
+#define IS_UART_INT(INT) ((((INT) & 0xFFFFFF80) == 0x00) && ((INT) != 0x00))
+
+#define IS_UART_GET_INT(INT) ((INT) & (UART_INT_RD_AVA | UART_INT_TX_FIFO_EMPTY | UART_INT_RX_LINE_STS |\
+                                       UART_INT_MODEM_STS | UART_INT_TX_DONE | UART_INT_TX_THD |\
+                                       UART_INT_RX_IDLE))
+/** \} */
+
+/**
+ * \defgroup   UART_Interrupt_Identifier  UART Interrupt Identifier
+ * \{
+ * \ingroup     UART_Exported_Constants
+ */
+
+#define UART_INT_PENDING                        ((uint16_t)(1 << 0))
+#define UART_INT_ID_LINE_STATUS                 ((uint16_t)(0x03 << 1))
+#define UART_INT_ID_RX_LEVEL_REACH              ((uint16_t)(0x02 << 1))
+#define UART_INT_ID_RX_DATA_TIMEOUT             ((uint16_t)(0x06 << 1))
+#define UART_INT_ID_TX_EMPTY                    ((uint16_t)(0x01 << 1))
+#define UART_INT_ID_MODEM_STATUS                ((uint16_t)(0x00 << 1))
+
+#define IS_UART_INT_ID(ID) (((ID) == UART_INT_ID_LINE_STATUS) || ((ID) == UART_INT_ID_RX_LEVEL_REACH) || \
+                            ((ID) == UART_INT_ID_RX_DATA_TIMEOUT) || ((ID) == UART_INT_ID_TX_EMPTY) || \
+                            ((ID) == UART_INT_ID_MODEM_STATUS))
+/** \} */
+
+/**
+ * \defgroup   UART_Parity UART Parity
+ * \{
+ * \ingroup     UART_Exported_Constants
+ */
+
+#define UART_PARITY_NO_PARTY                    ((uint16_t)(0x00 << 3))
+#define UART_PARITY_ODD                         ((uint16_t)(0x01 << 3))
+#define UART_PARITY_EVEN                        ((uint16_t)(0x03 << 3))
+
+#define IS_UART_PARITY(PARITY) (((PARITY) == UART_PARITY_NO_PARTY) || ((PARITY) == UART_PARITY_ODD)\
+                                ((PARITY) == UART_PARITY_EVEN))
+/** \} */
+
+/**
+ * \defgroup   UART_Stop_Bits  UART Stop Bits
+ * \{
+ * \ingroup     UART_Exported_Constants
+ */
+
+#define UART_STOP_BITS_1                        ((uint16_t)(0 << 2))
+#define UART_STOP_BITS_2                        ((uint16_t)(1 << 2))
+
+#define IS_UART_STOPBITS(STOP) (((STOP) == UART_STOP_BITS_1) || ((STOP) == UART_STOP_BITS_2))
+/** \} */
+
+/**
+ * \defgroup    UART_Word_Length UART Word Length
+ * \{
+ * \ingroup     UART_Exported_Constants
+ */
+#define UART_WORD_LENGTH_7BIT                   ((uint16_t)(0 << 0))
+#define UART_WORD_LENGTH_8BIT                   ((uint16_t)(1 << 0))
+
+#define IS_UART_WORD_LENGTH(LEN) ((((LEN)) == UART_WORD_LENGTH_7BIT) || (((LEN)) == UART_WORD_LENGTH_8BIT))
+/** \} */
+
+/**
+ * \defgroup   UART_Hardware_Flow_Control  UART Hardware Flow Control
+ * \{
+ * \ingroup     UART_Exported_Constants
+ */
+
+#define UART_HW_FLOW_CTRL_DISABLE               ((uint16_t)0x00)
+#define UART_HW_FLOW_CTRL_ENABLE                ((uint16_t)((1 << 5) | (1 << 1)))
+
+#define IS_UART_AUTO_FLOW_CTRL(CTRL) (((CTRL) == UART_AUTO_FLOW_CTRL_EN) || ((CTRL) == UART_AUTO_FLOW_CTRL_DIS))
+/** \} */
+
+/**
+ * \defgroup   UART_Flag UART Flag
+ * \{
+ * \ingroup     UART_Exported_Constants
+ */
+
+#define UART_FLAG_RX_DATA_AVA                   ((uint16_t)(1 << 0))
+#define UART_FLAG_RX_OVERRUN                    ((uint16_t)(1 << 1))
+#define UART_FLAG_RX_PARITY_ERR                 ((uint16_t)(1 << 2))
+#define UART_FLAG_RX_FRAME_ERR                  ((uint16_t)(1 << 3))
+#define UART_FLAG_RX_BREAK_ERR                  ((uint16_t)(1 << 4))
+#define UART_FLAG_TX_FIFO_EMPTY                 ((uint16_t)(1 << 5))  // Transmitter Holding Register or Transmitter FIFO empty
+#define UART_FLAG_TX_EMPTY                      ((uint16_t)(1 << 6))  // Transmitter Holding Register (or tx FIFO) and Transmitter shift Register empty
+#define UART_FLAG_RX_FIFO_ERR                   ((uint16_t)(1 << 7))
+#define UART_FLAG_RX_BREAK                      ((uint16_t)(1 << 8))
+#define UART_FLAG_RX_IDLE                       ((uint16_t)(1 << 9))  // Only to show difference because the address of UART RX Idle flag is isolate
+#define UART_FLAG_TX_DONE                       ((uint16_t)(1 << 10)) // Interrupt status of tx waveform done & TX_FIFO_EMPTY = 1
+#define UART_FLAG_TX_THD                        ((uint16_t)(1 << 11)) // Interrupt status of TX_FIFO_LEVEL <= txfifo_trigger_level
+
+#define IS_UART_GET_FLAG(FLAG) (((FLAG) == UART_FLAG_RX_DATA_AVA) || ((FLAG) == UART_FLAG_RX_OVERRUN) || \
+                                ((FLAG) == UART_FLAG_RX_PARITY_ERR) || ((FLAG) == UART_FLAG_RX_FRAME_ERR) || \
+                                ((FLAG) == UART_FLAG_RX_BREAK_ERR) || ((FLAG) == UART_FLAG_TX_FIFO_EMPTY) || \
+                                ((FLAG) == UART_FLAG_TX_EMPTY) || ((FLAG) == UART_FLAG_RX_FIFO_ERR) || \
+                                ((FLAG) == UART_FLAG_RX_BREAK) || ((FLAG) == UART_FLAG_RX_IDLE) || \
+                                ((FLAG) == UART_FLAG_TX_DONE) || ((FLAG) == UART_FLAG_TX_THD))
+/** \} */
+
+/**
+ * \defgroup   UART_DMA UART DMA
+ * \{
+ * \ingroup     UART_Exported_Constants
+ */
+
+#define UART_DMA_DISABLE                        ((uint16_t)(0 << 3))
+#define UART_DMA_ENABLE                         ((uint16_t)(1 << 3))
+
+#define IS_UART_DMA_CFG(CFG) (((CFG) == UART_DMA_ENABLE) || ((CFG) == UART_DMA_DISABLE))
+/** \} */
+
+/**
+ * \defgroup   UART_Rx_Idle_Time   UART Rx Idle Time
+ * \{
+ * \ingroup     UART_Exported_Constants
+ */
+
+#define UART_RX_IDLE_1BYTE                      ((uint16_t)(0x00))
+#define UART_RX_IDLE_2BYTE                      ((uint16_t)(0x01))
+#define UART_RX_IDLE_4BYTE                      ((uint16_t)(0x02))
+#define UART_RX_IDLE_8BYTE                      ((uint16_t)(0x03))
+#define UART_RX_IDLE_16BYTE                     ((uint16_t)(0x04))
+#define UART_RX_IDLE_32BYTE                     ((uint16_t)(0x05))
+#define UART_RX_IDLE_64BYTE                     ((uint16_t)(0x06))
+#define UART_RX_IDLE_128BYTE                    ((uint16_t)(0x07))
+#define UART_RX_IDLE_256BYTE                    ((uint16_t)(0x08))
+#define UART_RX_IDLE_512BYTE                    ((uint16_t)(0x09))
+#define UART_RX_IDLE_1024BYTE                   ((uint16_t)(0x0A))
+#define UART_RX_IDLE_2048BYTE                   ((uint16_t)(0x0B))
+#define UART_RX_IDLE_4096BYTE                   ((uint16_t)(0x0C))
+#define UART_RX_IDLE_8192BYTE                   ((uint16_t)(0x0D))
+#define UART_RX_IDLE_16384BYTE                  ((uint16_t)(0x0E))
+#define UART_RX_IDLE_32768BYTE                  ((uint16_t)(0x0F))
+
+#define IS_UART_IDLE_TIME(TIME) ((TIME) <= 0x0F)
+/** \} */
+
+/**
+ * \defgroup   UART_Interrupts_Mask_Definition  UART Interrupts Mask Definition
+ * \{
+ * \ingroup     UART_Exported_Constants
+ */
+#define UART_INT_MASK_RD_AVA                    ((uint16_t)(1 << 0))
+#define UART_INT_MASK_TX_FIFO_EMPTY             ((uint16_t)(1 << 1))
+#define UART_INT_MASK_RX_LINE_STS               ((uint16_t)(1 << 2))
+#define UART_INT_MASK_RX_BREAK                  ((uint16_t)(1 << 4))
+#define UART_INT_MASK_RX_IDLE                   ((uint16_t)(1 << 5))
+#define UART_INT_MASK_TX_DONE                   ((uint16_t)(1 << 6)) // Transmitter Holding Register (or tx FIFO) and Transmitter shift Register both empty
+#define UART_INT_MASK_TX_THD                    ((uint16_t)(1 << 7))
+
+#define IS_UART_INT_MASK(INT) ((INT) & (UART_INT_MASK_RD_AVA | UART_INT_MASK_TX_FIFO_EMPTY | UART_INT_MASK_RX_LINE_STS | \
+                                        UART_INT_MASK_RX_BREAK | UART_INT_MASK_RX_IDLE | UART_INT_MASK_TX_DONE | \
+                                        UART_INT_MASK_TX_THD))
+/** \} */
+
+/**
+ * \cond
+ * \defgroup   UART_Tx_Rx_FIFO_CLEAR_BIT   UART TRx Fifo Clear Bits
+ * \{
+ */
+#define FCR_CLEAR_RX_FIFO_Set           ((uint32_t)(1 << 1))
+#define FCR_CLEAR_RX_FIFO_Reset         ((uint32_t)~(1 << 1))
+#define FCR_CLEAR_TX_FIFO_Set           ((uint32_t)(1 << 2))
+#define FCR_CLEAR_TX_FIFO_Reset         ((uint32_t)~(1 << 2))
+/**
+ * \}
+ * \endcond
+ */
+
+/** End of UART_Exported_Constants
+  * \}
+  */
+
+/*============================================================================*
+ *                         Functions
+ *============================================================================*/
+/**
+ * \defgroup    UART_Exported_Functions UART Exported Functions
+ * \{
+ * \ingroup     UART
+ */
+
+/**
+ * \brief   Deinitialize the selected UART peripheral registers to their default reset values (turns off UART clock).
+ * \param[in] UARTx: UART peripheral selected, x can be 0 ~ 2.
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_uart_init(void)
+ * {
+ *    UART_DeInit(UART0);
+ * }
+ * \endcode
+ */
+void UART_DeInit(UART_TypeDef *UARTx);
+
+/**
+ * \brief   Initialize the selected UART peripheral according to the specified parameters in UART_InitStruct.
+ * \param[in] UARTx: UART peripheral selected, x can be 0 ~ 2.
+ * \param[in] UART_InitStruct: Pointer to a UART_InitTypeDef structure that
+*             contains the configuration information for the selected UART peripheral.
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_uart_init(void)
+ * {
+ *     UART_DeInit(UART0);
+ *
+ *     RCC_PeriphClockCmd(APBPeriph_UART0, APBPeriph_UART0_CLOCK, ENABLE);
+ *
+ *     UART_InitTypeDef UART_InitStruct;
+ *     UART_StructInit(&UART_InitStruct);
+ *     UART_InitStruct.UART_Div         = 20;
+ *     UART_InitStruct.UART_Ovsr        = 12;
+ *     UART_InitStruct.UART_OvsrAdj     = 0x252;
+ *     UART_InitStruct.UART_RxThdLevel  = 16;
+ *    // Add other initialization parameters that need to be configured here.
+ *     UART_Init(UART0, &UART_InitStruct);
+ * }
+ * \endcode
+ */
+void UART_Init(UART_TypeDef *UARTx, UART_InitTypeDef *UART_InitStruct);
+
+/**
+ * \brief   Fill each UART_InitStruct member with its default value.
+ * \param[in] UART_InitStruct: pointer to a UART_InitTypeDef structure which will be initialized.
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_uart_init(void)
+ * {
+ *     UART_DeInit(UART0);
+ *
+ *     RCC_PeriphClockCmd(APBPeriph_UART0, APBPeriph_UART0_CLOCK, ENABLE);
+ *
+ *     UART_InitTypeDef UART_InitStruct;
+ *     UART_StructInit(&UART_InitStruct);
+ *     UART_InitStruct.UART_Div         = 20;
+ *     UART_InitStruct.UART_Ovsr        = 12;
+ *     UART_InitStruct.UART_OvsrAdj     = 0x252;
+ *     UART_InitStruct.UART_RxThdLevel  = 16;
+ *     // Add other initialization parameters that need to be configured here.
+ *     UART_Init(UART0, &UART_InitStruct);
+ * }
+ * \endcode
+ */
+void UART_StructInit(UART_InitTypeDef *UART_InitStruct);
+
+/**
+ * \brief   Mask or unmask the specified UART interrupt source.
+ * \param[in] UARTx: UART peripheral selected, x can be 0 ~ 2.
+ * \param[in] UART_INT_MASK: Specify the UART interrupt source to be masked or unmasked.
+ *                           This parameter can be any combination of the following values, refer to \ref UART_Interrupts_Mask_Definition.
+ *      \arg UART_INT_MASK_RD_AVA: Mask INTCR (erbi).
+ *      \arg UART_INT_MASK_TX_FIFO_EMPTY: Mask INTCR (etbei).
+ *      \arg UART_INT_MASK_RX_LINE_STS: Mask INTCR (elsi).
+ *      \arg UART_INT_MASK_RX_BREAK: Mask rx break interrupt.
+ *      \arg UART_INT_MASK_RX_IDLE: Mask rx idle interrupt.
+ *      \arg UART_INT_MASK_TX_DONE: Mask tx done interrupt.
+ *      \arg UART_INT_MASK_TX_THD: Mask tx fifo threshold interrupt.
+ * \param[in] NewState: New state of the specified UART interrupt source.
+ *                      This parameter can be: ENABLE or DISABLE.
+ * \return None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_uart_init(void)
+ * {
+ *     UART_DeInit(UART0);
+ *
+ *     RCC_PeriphClockCmd(APBPeriph_UART0, APBPeriph_UART0_CLOCK, ENABLE);
+ *
+ *     UART_InitTypeDef UART_InitStruct;
+ *     UART_StructInit(&UART_InitStruct);
+ *     UART_InitStruct.UART_Div         = 20;
+ *     UART_InitStruct.UART_Ovsr        = 12;
+ *     UART_InitStruct.UART_OvsrAdj     = 0x252;
+ *     UART_InitStruct.UART_RxThdLevel  = 16;
+ *     // Add other initialization parameters that need to be configured here.
+ *     UART_Init(UART0, &UART_InitStruct);
+ *
+ *     UART_MaskINTConfig(UART0, UART_INT_MASK_RD_AVA, ENABLE);
+ *     UART_INTConfig(UART0, UART_INT_RD_AVA, ENABLE);
+ *     UART_MaskINTConfig(UART0, UART_INT_MASK_RD_AVA, DISABLE);
+ * }
+ * \endcode
+ */
+void UART_MaskINTConfig(UART_TypeDef *UARTx, uint32_t UART_INT_MASK, FunctionalState NewState);
+
+/**
+ * \brief   Enable or disable the specified UART interrupts.
+ * \param[in] UARTx: UART peripheral selected, x can be 0 ~ 2.
+ * \param[in] UART_IT: Specify the UART interrupt source to be enabled or disabled.
+ *                     This parameter can be any combination of the following values, refer to \ref UART_Interrupts_Definition.
+ *      \arg UART_INT_RD_AVA: Rx data available interrupt source.
+ *      \arg UART_INT_TX_FIFO_EMPTY: Tx FIFO empty interrupt source.
+ *      \arg UART_INT_RX_LINE_STS: Rx line status interrupt source.
+ *      \arg UART_INT_MODEM_STS: Modem status interrupt source.
+ *      \arg UART_INT_TX_DONE: Tx done interrupt source.
+ *      \arg UART_INT_TX_THD: Tx threshold (FIFO data length <= threshold) interrupt source.
+ *      \arg UART_INT_RX_BREAK: Rx break signal interrupt source.
+ *      \arg UART_INT_RX_IDLE: Rx bus idle interrupt source.
+ * \param[in] NewState: New state of the specified UART interrupt source.
+ *            This parameter can be: ENABLE or DISABLE.
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_uart_init(void)
+ * {
+ *     UART_DeInit(UART0);
+ *
+ *     RCC_PeriphClockCmd(APBPeriph_UART0, APBPeriph_UART0_CLOCK, ENABLE);
+ *
+ *     UART_InitTypeDef UART_InitStruct;
+ *     UART_StructInit(&UART_InitStruct);
+ *     UART_InitStruct.UART_Div = 20;
+ *     UART_InitStruct.UART_Ovsr = 12;
+ *     UART_InitStruct.UART_OvsrAdj = 0x252;
+ *     UART_InitStruct.UART_RxThdLevel = 16;
+ *     // Add other initialization parameters that need to be configured here.
+ *     UART_Init(UART0, &UART_InitStruct);
+ *
+ *     UART_INTConfig(UART0, UART_INT_RD_AVA, ENABLE);
+ * }
+ * \endcode
+ */
+void UART_INTConfig(UART_TypeDef *UARTx, uint32_t UART_IT, FunctionalState NewState);
+
+/**
+ * \brief   Send data.
+ * \param[in] UARTx: UART peripheral selected, x can be 0 ~ 2.
+ * \param[in] inBuf: Buffer of data to be sent.
+ * \param[in] count: Length of data to be sent.
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void uart_demo(void)
+ * {
+ *     uint8_t data[] = "UART demo";
+ *     UART_SendData(UART0, data, sizeof(data));
+ * }
+ * \endcode
+ */
+void UART_SendData(UART_TypeDef *UARTx, const uint8_t *inBuf, uint16_t count);
+
+/**
+ * \brief   Receive data from RX FIFO.
+ * \param[in]  UARTx: UART peripheral selected, x can be 0 ~ 2.
+ * \param[out] outBuf: Buffer to store data read from RX FIFO.
+ * \param[in]  count: Length of data to read.
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void uart_demo(void)
+ * {
+ *     uint8_t data[32] = {10};
+ *     UART_ReceiveData(UART0, data, 10);
+ * }
+ * \endcode
+ */
+void UART_ReceiveData(UART_TypeDef *UARTx, uint8_t *outBuf, uint16_t count);
+
+/**
+ * \brief   Set UART communication baudrate.
+ * \param[in]   UARTx: UART peripheral selected, x can be 0 ~ 2.
+ * \param[in]   div: Parameter of the selected UART baudrate.
+ * \param[in]   ovsr: Parameter of the selected UART baudrate.
+ * \param[in]   ovsr_adj: Parameter of the selected UART baudrate.
+ * \return  None.
+ *
+ * \note UART_BaudRate_Table div/ovsr/ovsr_adj: These three parameters set the baud rate calibration parameters of UART.
+ *
+ *  |baudrate   |div     |ovsr    |ovsr_adj   |
+ *  |:---------:|:------:|:------:|:---------:|
+ *  |1200Hz     |2589    |7       |0x7F7      |
+ *  |2400Hz     |1200    |8       |0x3EF      |
+ *  |4800Hz     |600     |8       |0x3EF      |
+ *  |9600Hz     |271     |10      |0x24A      |
+ *  |14400Hz    |271     |5       |0x222      |
+ *  |19200Hz    |165     |7       |0x5AD      |
+ *  |28800Hz    |110     |7       |0x5AD      |
+ *  |38400Hz    |85      |7       |0x222      |
+ *  |57600Hz    |55      |7       |0x5AD      |
+ *  |76800Hz    |35      |9       |0x7EF      |
+ *  |115200Hz   |20      |12      |0x252      |
+ *  |128000Hz   |25      |7       |0x555      |
+ *  |153600Hz   |15      |12      |0x252      |
+ *  |230400Hz   |10      |12      |0x252      |
+ *  |460800Hz   |5       |12      |0x252      |
+ *  |500000Hz   |8       |5       |0          |
+ *  |921600Hz   |4       |5       |0x3F7      |
+ *  |1000000Hz  |4       |5       |0          |
+ *  |1382400Hz  |2       |9       |0x2AA      |
+ *  |1444400Hz  |2       |8       |0x5F7      |
+ *  |1500000Hz  |2       |8       |0x492      |
+ *  |1843200Hz  |2       |5       |0x3F7      |
+ *  |2000000Hz  |2       |5       |0          |
+ *  |2100000Hz  |1       |14      |0x400      |
+ *  |2764800Hz  |1       |9       |0x2AA      |
+ *  |3000000Hz  |1       |8       |0x492      |
+ *  |3250000Hz  |1       |7       |0x112      |
+ *  |3692300Hz  |1       |5       |0x5F7      |
+ *  |3750000Hz  |1       |5       |0x36D      |
+ *  |4000000Hz  |1       |5       |0          |
+ *  |6000000Hz  |1       |1       |0x36D      |
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void uart_demo(void)
+ * {
+ *     uint16_t div = 20;
+ *     uint16_t ovsr = 12;
+ *     uint16_t ovsr_adj = 0x252;
+ *     UART_SetBaudRate(UART0, div, ovsr, ovsr_adj);
+ * }
+ * \endcode
+ */
+void UART_SetBaudRate(UART_TypeDef *UARTx, uint16_t div, uint16_t ovsr, uint16_t ovsr_adj);
+
+/**
+ * \brief   Set UART communication parameters.
+ * \param[in]   UARTx: UART peripheral selected, x can be 0 ~ 2.
+ * \param[in]   wordLen: Data width of the selected UART peripheral.
+ *              This parameter can be one of the following values:
+ *      \arg UART_WORD_LENGTH_7BIT: 7-bit data length.
+ *      \arg UART_WORD_LENGTH_8BIT: 8-bit data length.
+ * \param[in]   parity: Parity of the selected UART peripheral.
+ *              This parameter can be one of the following values:
+ *      \arg UART_PARITY_NO_PARITY: No parity.
+ *      \arg UART_PARITY_ODD: Odd parity.
+ *      \arg UART_PARITY_EVEN: Even parity.
+ * \param[in]   stopBits: Stop bit of the selected UART peripheral.
+ *              This parameter can be one of the following values:
+ *      \arg UART_STOP_BITS_1: 1-bit stop bit.
+ *      \arg UART_STOP_BITS_2: 2-bit stop bit.
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void uart_demo(void)
+ * {
+ *     uint16_t word_len = UART_WORD_LENGTH_8BIT;
+ *     uint16_t parity = UART_PARITY_NO_PARTY;
+ *     uint16_t stop_bits = UART_STOP_BITS_1;
+ *     UART_SetParams(UART0, wordLen, parity, stopBits);
+ * }
+ * \endcode
+ */
+void UART_SetParams(UART_TypeDef *UARTx, uint16_t wordLen, uint16_t parity, uint16_t stopBits);
+
+/**
+ * \brief   Configure UART loopback function.
+ * \param[in] UARTx: UART peripheral selected, x can be 0 ~ 2.
+ * \param[in] NewState: New state of the UART loopback function.
+ *                      This parameter can be: ENABLE or DISABLE.
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void uart_demo(void)
+ * {
+ *     UART_LoopBackCmd(UART0, ENABLE);
+ * }
+ * \endcode
+ */
+void UART_LoopBackCmd(UART_TypeDef *UARTx, FunctionalState NewState);
+
+/**
+ * \brief  Check whether the specified UART flag is set.
+ * \param[in]  UARTx: UART peripheral selected, x can be 0 ~ 2.
+ * \param[in]  UART_FLAG: Specify the UART flag to check.
+ *      This parameter can be one of the following values, refer to \ref UART_Flag.
+ *      \arg UART_FLAG_RX_DATA_AVA: Rx data is available.
+ *      \arg UART_FLAG_RX_OVERRUN: Rx FIFO overrun.
+ *      \arg UART_FLAG_RX_PARITY_ERR: Rx parity error.
+ *      \arg UART_FLAG_RX_FRAME_ERR: Rx frame error.
+ *      \arg UART_FLAG_RX_BREAK_ERR: Rx break error.
+ *      \arg UART_FLAG_TX_FIFO_EMPTY: Tx Holding Register or Tx FIFO empty.
+ *      \arg UART_FLAG_TX_EMPTY: Tx FIFO and Tx shift register are both empty.
+ *      \arg UART_FLAG_RX_FIFO_ERR: Rx FIFO error.
+ *      \arg UART_FLAG_RX_BREAK: Rx break.
+ *      \arg UART_FLAG_RX_IDLE: Rx idle.
+ *      \arg UART_FLAG_TX_DONE: Tx waveform done & TX_FIFO_EMPTY = 1.
+ *      \arg UART_FLAG_TX_THD: TX_FIFO_LEVEL <= txfifo_trigger_level.
+ * \return New status of the UART flag.
+ * \retval SET: The specified UART flag bit is set.
+ * \retval RESET: The specified flag is not set.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void uart_senddata_continuous(UART_TypeDef *UARTx, const uint8_t *pSend_Buf, uint16_t vCount)
+ * {
+ *     uint8_t count;
+ *
+ *     while (vCount / UART_TX_FIFO_SIZE > 0)
+ *     {
+ *         while (UART_GetFlagStatus(UARTx, UART_FLAG_TX_FIFO_EMPTY) == RESET);
+ *         for (count = UART_TX_FIFO_SIZE; count > 0; count--)
+ *         {
+ *             UARTx->RB_THR = *pSend_Buf++;
+ *         }
+ *         vCount -= UART_TX_FIFO_SIZE;
+ *     }
+ *     while (UART_GetFlagStatus(UARTx, UART_FLAG_TX_FIFO_EMPTY) == RESET);
+ *     while (vCount--)
+ *     {
+ *         UARTx->RB_THR = *pSend_Buf++;
+ *     }
+ * }
+ * \endcode
+ */
+FlagStatus UART_GetFlagStatus(UART_TypeDef *UARTx, uint32_t UART_FLAG);
+
+/**
+ * \brief   Send one byte of data.
+ * \param[in] UARTx: UART peripheral selected, x can be 0 ~ 2.
+ * \param[in] data: Byte data to send.
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void uart_demo(void)
+ * {
+ *     uint8_t data = 0x55;
+ *     UART_SendByte(UART0, data);
+ * }
+ * \endcode
+ */
+__STATIC_INLINE void UART_SendByte(UART_TypeDef *UARTx, uint8_t data)
+{
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+
+    UARTx->RB_THR = data;
+
+    return;
+}
+
+/**
+ * \brief   Read a byte of data from UART RX FIFO.
+ * \param[in] UARTx: UART peripheral selected, x can be 0 ~ 2.
+ * \return  The byte data that has been read.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void uart_demo(void)
+ * {
+ *     uint8_t data = UART_ReceiveByte(UART0);
+ *
+ * }
+ * \endcode
+ */
+__STATIC_INLINE uint8_t UART_ReceiveByte(UART_TypeDef *UARTx)
+{
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+
+    return (uint8_t)(UARTx->RB_THR);
+}
+
+/**
+ * \brief   Get the interrupt identifier of the selected UART peripheral.
+ * \param[in] UARTx: UART peripheral selected, x can be 0 ~ 2.
+ * \return  The interrupt identifier value.
+ *          This return value can be one of the following \ref UART_Interrupt_Identifier.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void UART0_Handler(void)
+ * {
+ *     //Get interrupt ID.
+ *     uint32_t int_status = UART_GetIID(UART0);
+ * }
+ * \endcode
+ */
+__STATIC_INLINE uint16_t UART_GetIID(UART_TypeDef *UARTx)
+{
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+
+    return (uint16_t)(UARTx->INTID_FCR & 0x0000000E);
+}
+
+/**
+ * \brief   Clear Tx FIFO of the selected UART peripheral.
+ * \param[in] UARTx: UART peripheral selected, x can be 0 ~ 2.
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void uart_demo(void)
+ * {
+ *     UART_ClearTxFIFO(UART0);
+ * }
+ * \endcode
+ */
+__STATIC_INLINE void UART_ClearTxFIFO(UART_TypeDef *UARTx)
+{
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+
+    UARTx->INTID_FCR = (((UARTx->STSR & BIT24) >> 21) | ((UARTx->STSR & 0x7C000000) >> 18) |
+                        ((UARTx->STSR & BIT25) >> 25) | FCR_CLEAR_TX_FIFO_Set);
+}
+
+/**
+ * \brief   Clear Rx FIFO of the selected UART peripheral.
+ * \param[in] UARTx: UART peripheral selected, x can be 0 ~ 2.
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void uart_demo(void)
+ * {
+ *     UART_ClearRxFIFO(UART0);
+ * }
+ * \endcode
+ */
+__STATIC_INLINE void UART_ClearRxFIFO(UART_TypeDef *UARTx)
+{
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+
+    UARTx->INTID_FCR = (((UARTx->STSR & BIT24) >> 21) | ((UARTx->STSR & 0x7C000000) >> 18) |
+                        ((UARTx->STSR & BIT25) >> 25) | FCR_CLEAR_RX_FIFO_Set);
+}
+
+/**
+ * \brief   Get the data length in Tx FIFO of the selected UART peripheral.
+ * \param[in] UARTx: UART peripheral selected, x can be 0 ~ 2.
+ * \return  Data length in UART TX FIFO.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void uart_demo(void)
+ * {
+ *     uint8_t data_len = UART_GetTxFIFODataLen(UART0);
+ * }
+ * \endcode
+ */
+__STATIC_INLINE uint8_t UART_GetTxFIFODataLen(UART_TypeDef *UARTx)
+{
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+
+    return (uint8_t)(UARTx->FIFO_LEVEL & 0x1F);
+}
+
+/**
+ * \brief   Get the data length in Rx FIFO of the selected UART peripheral.
+ * \param[in] UARTx: UART peripheral selected, x can be 0 ~ 2.
+ * \return  Data length in UART RX FIFO.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void uart_demo(void)
+ * {
+ *     uint8_t data_len = UART_GetRxFIFODataLen(UART0);
+ * }
+ * \endcode
+ */
+__STATIC_INLINE uint8_t UART_GetRxFIFODataLen(UART_TypeDef *UARTx)
+{
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+
+    return (uint8_t)((UARTx->FIFO_LEVEL >> 8) & 0x3F);
+}
+
+/**
+ * \brief   Clear Rx break of the selected UART peripheral.
+ * \param[in] UARTx: UART peripheral selected, x can be 0 ~ 2.
+ * \return  None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void uart_demo(void)
+ * {
+ *     UART_ClearRxBreak(UART0);
+ * }
+ * \endcode
+ */
+__STATIC_INLINE void UART_ClearRxBreak(UART_TypeDef *UARTx)
+{
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+
+    UARTx->LSR |= BIT7;
+    return;
+}
+
+/** End of UART_Exported_Functions
+  * \}
+  */
+
+/** End of UART
+  * \}
+  */
+
+typedef struct
+{
+    uint32_t uart_reg[12];
+} UARTStoreReg_TypeDef;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTL876X_UART_H_ */
+
+
+
diff --git a/bee/drivers/uart/src/device/rtl87x2g/rtl87x2g_uart.c b/bee/drivers/uart/src/device/rtl87x2g/rtl87x2g_uart.c
new file mode 100644
index 00000000..ac2fbe5f
--- /dev/null
+++ b/bee/drivers/uart/src/device/rtl87x2g/rtl87x2g_uart.c
@@ -0,0 +1,252 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *                        Header Files
+ *============================================================================*/
+#include "rtl_uart.h"
+#include "rtl_rcc.h"
+#include "app_section.h"
+
+/*============================================================================*
+ *                           Public Functions
+ *============================================================================*/
+void UART_OneWireConfig(UART_TypeDef *UARTx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+
+    if (UARTx == UART0)
+    {
+        PERIBLKCTRL_PERI_CLK->u_318.BITS_318.r_PMUX_1_WIRE_UART0_EN = NewState;
+    }
+    else if (UARTx == UART1)
+    {
+        PERIBLKCTRL_PERI_CLK->u_318.BITS_318.r_PMUX_1_WIRE_UART1_EN = NewState;
+    }
+    else if (UARTx == UART2)
+    {
+        PERIBLKCTRL_PERI_CLK->u_318.BITS_318.r_PMUX_1_WIRE_UART2_EN = NewState;
+    }
+    else if (UARTx == UART3)
+    {
+        PERIBLKCTRL_PERI_CLK->u_318.BITS_318.r_PMUX_1_WIRE_UART3_EN = NewState;
+    }
+    else if (UARTx == UART4)
+    {
+        PERIBLKCTRL_PERI_CLK->u_38C.BITS_38C.r_PMUX_1_WIRE_UART4_EN = NewState;
+    }
+    else if (UARTx == UART5)
+    {
+        PERIBLKCTRL_PERI_CLK->u_38C.BITS_38C.r_PMUX_1_WIRE_UART5_EN = NewState;
+    }
+}
+
+bool UART_ClkGet(UART_TypeDef *UARTx, UARTClockSrc_TypeDef *ClockSrc,
+                 UARTClockDiv_TypeDef *ClockDiv)
+{
+    *ClockSrc = UART_CLOCK_SRC_40M;
+    if (UARTx == UART0)
+    {
+        *ClockDiv = (PERIBLKCTRL_PERI_CLK->u_318.BITS_318.rtk_uart0_div_en == 0) ? 0 :
+                    PERIBLKCTRL_PERI_CLK->u_318.BITS_318.rtk_uart0_div_sel;
+    }
+    else if (UARTx == UART1)
+    {
+        *ClockDiv = (PERIBLKCTRL_PERI_CLK->u_318.BITS_318.rtk_uart1_div_en == 0) ? 0 :
+                    PERIBLKCTRL_PERI_CLK->u_318.BITS_318.rtk_uart1_div_sel;
+    }
+    else if (UARTx == UART2)
+    {
+        *ClockDiv = (PERIBLKCTRL_PERI_CLK->u_318.BITS_318.rtk_uart2_div_en == 0) ? 0 :
+                    PERIBLKCTRL_PERI_CLK->u_318.BITS_318.rtk_uart2_div_sel;
+    }
+    else if (UARTx == UART3)
+    {
+        *ClockDiv = (PERIBLKCTRL_PERI_CLK->u_318.BITS_318.rtk_uart3_div_en == 0) ? 0 :
+                    PERIBLKCTRL_PERI_CLK->u_318.BITS_318.rtk_uart3_div_sel;
+    }
+    else if (UARTx == UART4)
+    {
+        *ClockDiv = (PERIBLKCTRL_PERI_CLK->u_38C.BITS_38C.rtk_uart4_div_en == 0) ? 0 :
+                    PERIBLKCTRL_PERI_CLK->u_38C.BITS_38C.rtk_uart4_div_sel;
+    }
+    else if (UARTx == UART5)
+    {
+        *ClockDiv = (PERIBLKCTRL_PERI_CLK->u_38C.BITS_38C.rtk_uart5_div_en == 0) ? 0 :
+                    PERIBLKCTRL_PERI_CLK->u_38C.BITS_38C.rtk_uart5_div_sel;
+    }
+    else
+    {
+        return false;
+    }
+    return true;
+}
+
+void UART_ClkDivConfig(UART_TypeDef *UARTx, UARTClockDiv_TypeDef ClockDiv)
+{
+    assert_param(IS_UART_DIV(ClockDiv));
+
+    /* Config UART clock divider */
+    if (UARTx == UART0)
+    {
+        /* disable clock first */
+        PERIBLKCTRL_PERI_CLK->u_318.BITS_318.rtk_uart0_div_en = 0;
+        PERIBLKCTRL_PERI_CLK->u_318.BITS_318.rtk_uart0_div_sel = ClockDiv;
+        PERIBLKCTRL_PERI_CLK->u_318.BITS_318.rtk_uart0_div_en = 1;
+    }
+    else if (UARTx == UART1)
+    {
+        PERIBLKCTRL_PERI_CLK->u_318.BITS_318.rtk_uart1_div_en = 0;
+        PERIBLKCTRL_PERI_CLK->u_318.BITS_318.rtk_uart1_div_sel = ClockDiv;
+        PERIBLKCTRL_PERI_CLK->u_318.BITS_318.rtk_uart1_div_en = 1;
+    }
+    else if (UARTx == UART2)
+    {
+        PERIBLKCTRL_PERI_CLK->u_318.BITS_318.rtk_uart2_div_en = 0;
+        PERIBLKCTRL_PERI_CLK->u_318.BITS_318.rtk_uart2_div_sel = ClockDiv;
+        PERIBLKCTRL_PERI_CLK->u_318.BITS_318.rtk_uart2_div_en = 1;
+    }
+    else if (UARTx == UART3)
+    {
+        PERIBLKCTRL_PERI_CLK->u_318.BITS_318.rtk_uart3_div_en = 0;
+        PERIBLKCTRL_PERI_CLK->u_318.BITS_318.rtk_uart3_div_sel = ClockDiv;
+        PERIBLKCTRL_PERI_CLK->u_318.BITS_318.rtk_uart3_div_en = 1;
+    }
+    else if (UARTx == UART4)
+    {
+        PERIBLKCTRL_PERI_CLK->u_38C.BITS_38C.rtk_uart4_div_en = 0;
+        PERIBLKCTRL_PERI_CLK->u_38C.BITS_38C.rtk_uart4_div_sel = ClockDiv;
+        PERIBLKCTRL_PERI_CLK->u_38C.BITS_38C.rtk_uart4_div_en = 1;
+    }
+    else if (UARTx == UART5)
+    {
+        PERIBLKCTRL_PERI_CLK->u_38C.BITS_38C.rtk_uart5_div_en = 0;
+        PERIBLKCTRL_PERI_CLK->u_38C.BITS_38C.rtk_uart5_div_sel = ClockDiv;
+        PERIBLKCTRL_PERI_CLK->u_38C.BITS_38C.rtk_uart5_div_en = 1;
+    }
+    return;
+}
+
+
+RAM_FUNCTION
+void UART_DLPSEnter(void *PeriReg, void *StoreBuf)
+{
+    UART_TypeDef *UARTx = (UART_TypeDef *)PeriReg;
+    UARTStoreReg_Typedef *store_buf = (UARTStoreReg_Typedef *)StoreBuf;
+
+    if (UARTx == UART0)
+    {
+        RCC_PeriphClockCmd(APBPeriph_UART0, APBPeriph_UART0_CLOCK, ENABLE);
+        store_buf->uart_reg[12] = PERIBLKCTRL_PERI_CLK->u_318.REG_UART_PERI_CTL0;
+    }
+    else if (UARTx == UART1)
+    {
+        RCC_PeriphClockCmd(APBPeriph_UART1, APBPeriph_UART1_CLOCK, ENABLE);
+        store_buf->uart_reg[12] = PERIBLKCTRL_PERI_CLK->u_318.REG_UART_PERI_CTL0;
+    }
+    else if (UARTx == UART2)
+    {
+        RCC_PeriphClockCmd(APBPeriph_UART2, APBPeriph_UART2_CLOCK, ENABLE);
+        store_buf->uart_reg[12] = PERIBLKCTRL_PERI_CLK->u_318.REG_UART_PERI_CTL0;
+    }
+    else if (UARTx == UART3)
+    {
+        RCC_PeriphClockCmd(APBPeriph_UART3, APBPeriph_UART3_CLOCK, ENABLE);
+        store_buf->uart_reg[12] = PERIBLKCTRL_PERI_CLK->u_318.REG_UART_PERI_CTL0;
+    }
+    else if (UARTx == UART4)
+    {
+        RCC_PeriphClockCmd(APBPeriph_UART4, APBPeriph_UART4_CLOCK, ENABLE);
+        store_buf->uart_reg[12] = PERIBLKCTRL_PERI_CLK->u_38C.REG_UART_PERI_CTL1;
+    }
+    else if (UARTx == UART5)
+    {
+        RCC_PeriphClockCmd(APBPeriph_UART5, APBPeriph_UART5_CLOCK, ENABLE);
+        store_buf->uart_reg[12] = PERIBLKCTRL_PERI_CLK->u_38C.REG_UART_PERI_CTL1;
+    }
+
+    //access DLH and DLL
+    UARTx->UART_LCR |= (1 << 7);
+    store_buf->uart_reg[0] = UARTx->UART_DLL;
+    store_buf->uart_reg[1] = UARTx->UART_DLM_IER;
+    UARTx->UART_LCR &= (~(1 << 7));
+
+    //save other registers
+    store_buf->uart_reg[2] = UARTx->UART_DLM_IER;
+    store_buf->uart_reg[4] = UARTx->UART_LCR;
+    store_buf->uart_reg[5] = UARTx->UART_CTRL0;
+    store_buf->uart_reg[6] = UARTx->UART_SCR;
+    store_buf->uart_reg[7] = UARTx->UART_STSR;
+    store_buf->uart_reg[8] = UARTx->UART_RX_TIMEOUT;
+    store_buf->uart_reg[9] = UARTx->UART_RX_TIMEOUT_EN;
+    store_buf->uart_reg[10] = UARTx->UART_MISCR;
+    store_buf->uart_reg[11] = UARTx->UART_INT_MASK;
+
+    return;
+}
+
+
+RAM_FUNCTION
+void UART_DLPSExit(void *PeriReg, void *StoreBuf)
+{
+    UART_TypeDef *UARTx = (UART_TypeDef *)PeriReg;
+    UARTStoreReg_Typedef *store_buf = (UARTStoreReg_Typedef *)StoreBuf;
+
+    if (UARTx == UART0)
+    {
+        RCC_PeriphClockCmd(APBPeriph_UART0, APBPeriph_UART0_CLOCK, ENABLE);
+        store_buf->uart_reg[12] = PERIBLKCTRL_PERI_CLK->u_318.REG_UART_PERI_CTL0;
+    }
+    else if (UARTx == UART1)
+    {
+        RCC_PeriphClockCmd(APBPeriph_UART1, APBPeriph_UART1_CLOCK, ENABLE);
+        store_buf->uart_reg[12] = PERIBLKCTRL_PERI_CLK->u_318.REG_UART_PERI_CTL0;
+    }
+    else if (UARTx == UART2)
+    {
+        RCC_PeriphClockCmd(APBPeriph_UART2, APBPeriph_UART2_CLOCK, ENABLE);
+        store_buf->uart_reg[12] = PERIBLKCTRL_PERI_CLK->u_318.REG_UART_PERI_CTL0;
+    }
+    else if (UARTx == UART3)
+    {
+        RCC_PeriphClockCmd(APBPeriph_UART3, APBPeriph_UART3_CLOCK, ENABLE);
+        store_buf->uart_reg[12] = PERIBLKCTRL_PERI_CLK->u_318.REG_UART_PERI_CTL0;
+    }
+    else if (UARTx == UART4)
+    {
+        RCC_PeriphClockCmd(APBPeriph_UART4, APBPeriph_UART4_CLOCK, ENABLE);
+        store_buf->uart_reg[12] = PERIBLKCTRL_PERI_CLK->u_38C.REG_UART_PERI_CTL1;
+    }
+    else if (UARTx == UART5)
+    {
+        RCC_PeriphClockCmd(APBPeriph_UART5, APBPeriph_UART5_CLOCK, ENABLE);
+        store_buf->uart_reg[12] = PERIBLKCTRL_PERI_CLK->u_38C.REG_UART_PERI_CTL1;
+    }
+
+    //access DLH and DLL
+    UARTx->UART_LCR         |= (1 << 7);
+    UARTx->UART_STSR        = store_buf->uart_reg[7];
+    UARTx->UART_SCR         = store_buf->uart_reg[6];
+    UARTx->UART_DLL         = store_buf->uart_reg[0];
+    UARTx->UART_DLM_IER     = store_buf->uart_reg[1];
+    UARTx->UART_LCR         &= (~(1 << 7));
+
+    //access other registers
+    UARTx->UART_IIR_FCR = (((store_buf->uart_reg[7] & BIT24) >> 21) | \
+                           ((store_buf->uart_reg[7] & 0x7C000000) >> 18) | \
+                           (1));
+    UARTx->UART_LCR         = store_buf->uart_reg[4];
+    UARTx->UART_CTRL0       = store_buf->uart_reg[5];
+    UARTx->UART_DLM_IER     = store_buf->uart_reg[2];
+    UARTx->UART_RX_TIMEOUT  = store_buf->uart_reg[8];
+    UARTx->UART_RX_TIMEOUT_EN = store_buf->uart_reg[9];
+    UARTx->UART_MISCR       = store_buf->uart_reg[10];
+    UARTx->UART_INT_MASK    = store_buf->uart_reg[11];
+
+    return;
+}
+
diff --git a/bee/drivers/uart/src/device/rtl87x2g/rtl_uart.c b/bee/drivers/uart/src/device/rtl87x2g/rtl_uart.c
new file mode 100644
index 00000000..b7eab47d
--- /dev/null
+++ b/bee/drivers/uart/src/device/rtl87x2g/rtl_uart.c
@@ -0,0 +1,694 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *                        Header Files
+ *============================================================================*/
+#include "rtl_uart.h"
+#include "rtl_rcc.h"
+
+/*============================================================================*
+ *                          UART Private Defines
+ *============================================================================*/
+#define FCR_CLEAR_RX_FIFO_Set           ((uint32_t)(1 << 1))
+#define FCR_CLEAR_RX_FIFO_Reset         ((uint32_t)~(1 << 1))
+#define FCR_CLEAR_TX_FIFO_Set           ((uint32_t)(1 << 2))
+#define FCR_CLEAR_TX_FIFO_Reset         ((uint32_t)~(1 << 2))
+
+/*============================================================================*
+ *                           Public Functions
+ *============================================================================*/
+/**
+  * \brief  Deinitializes the UART peripheral registers to their default reset values(turn off UART clock).
+  * \param  UARTx: Select the UART peripheral. \ref UART_Declaration
+  * \return None
+  */
+void UART_DeInit(UART_TypeDef *UARTx)
+{
+    assert_param(IS_UART_PERIPH(UARTx));
+
+    switch ((uint32_t)UARTx)
+    {
+#ifdef UART0
+    case (uint32_t)UART0:
+        RCC_PeriphClockCmd(APBPeriph_UART0, APBPeriph_UART0_CLOCK, DISABLE);
+        break;
+#endif
+#ifdef UART1
+    case (uint32_t)UART1:
+        RCC_PeriphClockCmd(APBPeriph_UART1, APBPeriph_UART1_CLOCK, DISABLE);
+        break;
+#endif
+#ifdef UART2
+    case (uint32_t)UART2:
+        RCC_PeriphClockCmd(APBPeriph_UART2, APBPeriph_UART2_CLOCK, DISABLE);
+        break;
+#endif
+#ifdef UART3
+    case (uint32_t)UART3:
+        RCC_PeriphClockCmd(APBPeriph_UART3, APBPeriph_UART3_CLOCK, DISABLE);
+        break;
+#endif
+#ifdef UART4
+    case (uint32_t)UART4:
+        RCC_PeriphClockCmd(APBPeriph_UART4, APBPeriph_UART4_CLOCK, DISABLE);
+        break;
+#endif
+#ifdef UART5
+    case (uint32_t)UART5:
+        RCC_PeriphClockCmd(APBPeriph_UART5, APBPeriph_UART5_CLOCK, DISABLE);
+        break;
+#endif
+#ifdef UART6
+    case (uint32_t)UART6:
+        RCC_PeriphClockCmd(APBPeriph_UART6, APBPeriph_UART6_CLOCK, DISABLE);
+        break;
+#endif
+
+    default:
+        break;
+    }
+}
+
+/**
+  * \brief  Initializes the UART peripheral according to the specified
+  *         parameters in the UART_InitStruct
+  * \param  UARTx: Select the UART peripheral. \ref UART_Declaration
+  * \param  UART_InitStruct: pointer to a UART_InitTypeDef structure that
+  *         contains the configuration information for the specified UART peripheral
+  * \return None
+  */
+void UART_Init(UART_TypeDef *UARTx, UART_InitTypeDef *UART_InitStruct)
+{
+    assert_param(IS_UART_PERIPH(UARTx));
+    assert_param(IS_UART_WORD_LENGTH(UART_InitStruct->UART_WordLen));
+    assert_param(IS_UART_STOPBITS(UART_InitStruct->UART_StopBits));
+    assert_param(IS_UART_PARITY(UART_InitStruct->UART_Parity));
+    assert_param(IS_UART_RX_FIFO_TRIGGER_LEVEL(UART_InitStruct->UART_RxThdLevel));
+    assert_param(IS_UART_IDLE_TIME(UART_InitStruct->UART_IdleTime));
+    assert_param(IS_UART_DMA_CFG(UART_InitStruct->UART_DmaEn));
+    assert_param(IS_UART_AUTO_FLOW_CTRL(UART_InitStruct->UART_HardwareFlowControl));
+
+    /* Clear DLAB bit*/
+    UART_LCR_TypeDef uart_0x0c = {.d32 = UARTx->UART_LCR};
+    uart_0x0c.b.dlab = 0x0;
+    UARTx->UART_LCR = uart_0x0c.d32;
+
+    /* Disable all interrupt */
+    UARTx->UART_DLM_IER = 0x0;
+
+    /* Read to clear Line Status Reg */
+    (void) UARTx->UART_LSR;
+
+    /* Clear FIFO */
+    UART_FCR_TypeDef uart_0x08 = {.d32 = 0x0};
+    uart_0x08.b.clear_rxfifo = 0x1;
+#if UART_SUPPORT_CLEAR_TX_FIFO
+    uart_0x08.b.clear_txfifo = 0x1;
+#endif
+    UARTx->UART_IIR_FCR = uart_0x08.d32;
+
+    /* Set baudrate, firstly set DLAB bit */
+    uart_0x0c.b.dlab = 0x1;
+    UARTx->UART_LCR = uart_0x0c.d32;
+    /* Set calibration parameters(OVSR) */
+    UART_STSR_TypeDef uart_0x20 = {.d32 = UARTx->UART_STSR};
+    uart_0x20.b.xfactor = UART_InitStruct->UART_Ovsr;
+    UARTx->UART_STSR = uart_0x20.d32;
+    /* Set calibration parameters(OVSR_adj) */
+    UART_SCR_TypeDef uart_0x1c = {.d32 = UARTx->UART_SCR};
+    uart_0x1c.b.xfactor_adj = UART_InitStruct->UART_OvsrAdj;
+    UARTx->UART_SCR = uart_0x1c.d32;
+    /* Set DLL and DLH */
+    UARTx->UART_DLL = (UART_InitStruct->UART_Div & 0x00FF);
+    UARTx->UART_DLM_IER = ((UART_InitStruct->UART_Div & 0xFF00) >> 8);
+    /* After set baudrate, clear DLAB bit */
+    uart_0x0c.b.dlab = 0x0;
+    UARTx->UART_LCR = uart_0x0c.d32;
+
+    /* Set LCR reg */
+    uart_0x0c.b.wls0 = UART_InitStruct->UART_WordLen;
+    uart_0x0c.b.stb = UART_InitStruct->UART_StopBits;
+    uart_0x0c.b.parity_sel = UART_InitStruct->UART_Parity;
+    UARTx->UART_LCR = uart_0x0c.d32;
+
+    /* Set FCR reg, FIFO must enable */
+    uart_0x08.d32 = 0x0;
+    uart_0x08.b.rxfifo_error_en = ENABLE;
+    uart_0x08.b.dma_mode = UART_InitStruct->UART_DmaEn;
+    uart_0x08.b.rxfifo_trigger_level = UART_InitStruct->UART_RxThdLevel;
+    uart_0x08.b.tx_fifo_th = UART_InitStruct->UART_TxThdLevel;
+    UARTx->UART_IIR_FCR = uart_0x08.d32;
+
+    /* Harware flow control */ //Bert check register
+    UART_CTRL0_TypeDef uart_0x10 = {.d32 = UARTx->UART_CTRL0};
+    uart_0x10.b.rts = UART_InitStruct->UART_HardwareFlowControl;
+    uart_0x10.b.autoflow_en = UART_InitStruct->UART_HardwareFlowControl;
+    UARTx->UART_CTRL0 = uart_0x10.d32;
+
+    /* Set rx idle time */
+    UARTx->UART_RX_TIMEOUT = (UART_InitStruct->UART_IdleTime);
+
+    UART_MISCR_TypeDef uart_0x28 = {.d32 = UARTx->UART_MISCR};
+    uart_0x28.b.txdma_en = UART_InitStruct->UART_TxDmaEn;
+    uart_0x28.b.rxdma_en = UART_InitStruct->UART_RxDmaEn;
+    uart_0x28.b.txdma_burstsize = UART_InitStruct->UART_TxWaterLevel;
+    uart_0x28.b.rxdma_burstsize = UART_InitStruct->UART_RxWaterLevel;
+    UARTx->UART_MISCR = uart_0x28.d32;
+
+    return;
+}
+
+/**
+  * \brief  Fills each UART_InitStruct member with its default value.
+  * \param  UART_InitStruct: pointer to an UART_InitTypeDef structure which will be initialized.
+  * \return None
+  */
+void UART_StructInit(UART_InitTypeDef *UART_InitStruct)
+{
+    //115200 default
+    UART_InitStruct->UART_Div                 = 20;
+    UART_InitStruct->UART_Ovsr                = 12;
+    UART_InitStruct->UART_OvsrAdj             = 0x252;
+
+    UART_InitStruct->UART_WordLen             = UART_WORD_LENGTH_8BIT;
+    UART_InitStruct->UART_StopBits            = UART_STOP_BITS_1;
+    UART_InitStruct->UART_Parity              = UART_PARITY_NO_PARTY;
+    UART_InitStruct->UART_TxThdLevel          = 16; //1~29
+    UART_InitStruct->UART_RxThdLevel          = 16; //1~29
+    UART_InitStruct->UART_IdleTime            = UART_RX_IDLE_2BYTE; //idle interrupt wait time
+    UART_InitStruct->UART_HardwareFlowControl = UART_HW_FLOW_CTRL_DISABLE;
+    UART_InitStruct->UART_DmaEn               = UART_DMA_DISABLE;
+    UART_InitStruct->UART_TxDmaEn             = DISABLE;
+    UART_InitStruct->UART_RxDmaEn             = DISABLE;
+    UART_InitStruct->UART_TxWaterLevel        = 15; //Better to equal TX_FIFO_SIZE(16)- GDMA_MSize
+    UART_InitStruct->UART_RxWaterLevel        = 1; //Better to equal GDMA_MSize
+    return;
+}
+
+/**
+  * \brief  Mask or unmask the specified UART interrupts.
+  * \param  UART_INT: specifies the IR interrupts sources to be mask or unmask.
+  *         This parameter can be the following values:
+  *         \arg UART_INT_MASK_RD_AVA: mask INTCR(erbi).
+  *         \arg UART_INT_MASK_TX_FIFO_EMPTY: mask INTCR(etbei).
+  *         \arg UART_INT_MASK_RX_LINE_STS: mask INTCR(elsi).
+  *         \arg UART_INT_MASK_MODEM_STS: mask INTCR(edssi).
+  *         \arg UART_INT_MASK_RX_BREAK: mask rx break interrupt.
+  *         \arg UART_INT_MASK_RX_IDLE: mask rx idle interrupt.
+  *         \arg UART_INT_MASK_TX_DONE: mask the interrupt tx done interrupt.
+  *         \arg UART_INT_MASK_TX_THD: mask tx fifo threshold interrupt.
+  * \param  NewState: new state of the specified UART interrupts.
+  *         This parameter can be: ENABLE or DISABLE.
+  * \return None
+  */
+void UART_MaskINTConfig(UART_TypeDef *UARTx, uint32_t UART_INT_MASK, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+    assert_param(IS_UART_INT_MASK(UART_INT_MASK));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (NewState != DISABLE)
+    {
+        UARTx->UART_INT_MASK |= UART_INT_MASK;
+    }
+    else
+    {
+        UARTx->UART_INT_MASK &= ~(UART_INT_MASK);
+    }
+}
+
+/**
+  * \brief  Enable or disable the specified UART interrupts.
+  * \param  UARTx: Select the UART peripheral. \ref UART_Declaration
+  * \param  UART_INT: specifies the UART interrupts sources to be enabled or disabled.
+  *         This parameter can be any combination of the following values:
+  *         \arg UART_INT_RD_AVA: Rx data avaliable interrupt source.
+  *         \arg UART_INT_TX_FIFO_EMPTY: Tx FIFO empty interrupt source.
+  *         \arg UART_INT_RX_LINE_STS: Rx line status interrupt source.
+  *         \arg UART_INT_MODEM_STS: modem status interrupt source.
+  *         \arg UART_INT_TX_DONE: Tx data done interrupt source.
+  *         \arg UART_INT_TX_THD: Tx FIFO data <= thredhold interrupt source.
+  *         \arg UART_INT_RX_BREAK: Rx break signal interrupt source.
+  *         \arg UART_INT_RX_IDLE: Rx idle interrupt source.
+  * \param  NewState: new state of the specified UART interrupts.
+  *         This parameter can be: ENABLE or DISABLE.
+  * \return None
+  */
+void UART_INTConfig(UART_TypeDef *UARTx, uint32_t UART_INT, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+    assert_param(IS_UART_INT(UART_INT));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (UART_INT & UART_INT_RX_IDLE)
+    {
+        if (NewState == ENABLE)
+        {
+            UARTx->UART_RX_TIMEOUT_EN |= BIT0;
+            UARTx->UART_RX_TIMEOUT |= BIT31;
+        }
+        else
+        {
+            UARTx->UART_RX_TIMEOUT &= (~BIT31);
+            UARTx->UART_RX_TIMEOUT_STS |= BIT0;
+            UARTx->UART_RX_TIMEOUT_EN &= (~BIT0);
+        }
+    }
+
+    if (UART_INT & 0x3F)
+    {
+
+        if (NewState == ENABLE)
+        {
+            /* Enable the selected UARTx interrupts */
+            UARTx->UART_DLM_IER |= UART_INT;
+        }
+        else
+        {
+            /* Disable the selected UARTx interrupts */
+            UARTx->UART_DLM_IER &= (uint32_t)~UART_INT;
+        }
+    }
+    return;
+}
+
+/**
+  * \brief  Send data to tx FIFO.
+  * \param  UARTx: Select the UART peripheral. \ref UART_Declaration
+  * \param  inBuf: buffer to be written to Tx FIFO.
+  * \param  num: number of data to be written.
+  * \return None
+  */
+void UART_SendData(UART_TypeDef *UARTx, const uint8_t *inBuf, uint16_t Count)
+{
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+
+    while (Count--)
+    {
+        UARTx->UART_RBR_THR = *inBuf++;
+    }
+
+    return;
+}
+
+#if UART_SUPPORT_HALF_WORD
+/**
+  * \brief  Send half word data to tx FIFO.
+  * \param  UARTx: Select the UART peripheral. \ref UART_Declaration
+  * \param  inBuf: buffer to be written to Tx FIFO.
+  * \param  num: number of data to be written.
+  * \return None
+  */
+void UART_SendHalfWordData(UART_TypeDef *UARTx, const uint16_t *inBuf, uint16_t Count)
+{
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+
+    while (Count--)
+    {
+        UARTx->UART_RBR_THR = *inBuf++;
+    }
+
+    return;
+}
+#endif
+
+/**
+  * \brief  Receive data from rx FIFO.
+  * \param  UARTx: Select the UART peripheral. \ref UART_Declaration
+  * \param[out] outBuf: buffer to save data read from UART FIFO.
+  * \param  count: number of data to be read.
+  * \return None
+  */
+void UART_ReceiveData(UART_TypeDef *UARTx, uint8_t *OutBuf, uint16_t Count)
+{
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+
+    while (Count--)
+    {
+        *OutBuf++ = (uint8_t)UARTx->UART_RBR_THR;
+    }
+
+    return;
+}
+
+#if UART_SUPPORT_HALF_WORD
+/**
+  * \brief  Receive data from rx FIFO.
+  * \param  UARTx: Select the UART peripheral. \ref UART_Declaration
+  * \param[out] outBuf: buffer to save data read from UART FIFO.
+  * \param  count: number of data to be read.
+  * \return None
+  */
+void UART_ReceiveHalfWordData(UART_TypeDef *UARTx, uint16_t *OutBuf, uint16_t Count)
+{
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+
+    while (Count--)
+    {
+        *OutBuf++ = (uint16_t)UARTx->UART_RBR_THR;
+    }
+
+    return;
+}
+#endif
+
+/**
+  * \brief  Change UART baudrate.
+  * \param  UARTx: Select the UART peripheral. \ref UART_Declaration
+  * \param  div: parameter of the selected UART baudrate.
+  * \param  ovsr: parameter of the selected UART baudrate.
+  * \param  ovsr_adj: parameter of the selected UART baudrate.
+  * \return None.
+  */
+void UART_SetBaudRate(UART_TypeDef *UARTx, uint16_t div, uint16_t ovsr, uint16_t ovsr_adj)
+{
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+
+    /* Set baudrate, firstly set DLAB bit */
+    UART_LCR_TypeDef uart_0x0c = {.d32 = UARTx->UART_LCR};
+    uart_0x0c.b.dlab = 0x1;
+    UARTx->UART_LCR = uart_0x0c.d32;
+
+    /* Set calibration parameters(OVSR) */
+    UART_STSR_TypeDef uart_0x20 = {.d32 = UARTx->UART_STSR};
+    uart_0x20.b.xfactor = ovsr;
+    UARTx->UART_STSR = uart_0x20.d32;
+
+    /* Set calibration parameters(OVSR_adj) */
+    UART_SCR_TypeDef uart_0x1c = {.d32 = UARTx->UART_SCR};
+    uart_0x1c.b.xfactor_adj = ovsr_adj;
+    UARTx->UART_SCR = uart_0x1c.d32;
+
+    /* Set DLL and DLH */
+    UARTx->UART_DLL = (div & 0x00FF);
+    UARTx->UART_DLM_IER = ((div & 0xFF00) >> 8);
+
+    /* After set baudrate, clear DLAB bit */
+    uart_0x0c.b.dlab = 0x0;
+    UARTx->UART_LCR = uart_0x0c.d32;
+}
+
+/**
+  * \brief  Set UART parameters.
+  * \param  UARTx: Select the UART peripheral. \ref UART_Declaration
+  * \param  wordLen: data width of selected UART peripheral.
+  * \param  parity: parity of selected UART peripheral.
+  * \param  stopBits: stop bit of selected UART peripheral.
+  * \return None
+  */
+void UART_SetParams(UART_TypeDef *UARTx, uint16_t wordLen, uint16_t parity, uint16_t stopBits)
+{
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+
+    /* set LCR reg */
+    UART_LCR_TypeDef uart_0x0c = {.d32 = UARTx->UART_LCR};
+    uart_0x0c.b.wls0 = wordLen;
+    uart_0x0c.b.stb = stopBits;
+    uart_0x0c.b.parity_sel = parity;
+    UARTx->UART_LCR = uart_0x0c.d32;
+}
+
+/**
+  * \brief  UART loop back mode config.
+  * \param  UARTx: Select the UART peripheral. \ref UART_Declaration
+  * \param  NewState: new state, this parameter can be: ENABLE or DISABLE.
+  * \return None.
+  */
+void UART_LoopBackCmd(UART_TypeDef *UARTx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+
+    UART_CTRL0_TypeDef uart_0x10 = {.d32 = UARTx->UART_CTRL0};
+    uart_0x10.b.loopback_en = NewState;
+    UARTx->UART_CTRL0 = uart_0x10.d32;
+}
+
+/**
+  * \brief  Checks whether the specified UART flag is set or not.
+  * \param  UARTx: Select the UART peripheral. \ref UART_Declaration
+  * \param  UART_FLAG: specifies the flag to check.
+  *         This parameter can be one of the following values:
+  *         \arg UART_FLAG_RX_DATA_RDY: rx data is avaliable.
+  *         \arg UART_FLAG_RX_OVERRUN: rx overrun.
+  *         \arg UART_FLAG_PARTY_ERR: parity error.
+  *         \arg UART_FLAG_FRAME_ERR: UARTx frame error.
+  *         \arg UART_FLAG_BREAK_ERR: UARTx break error.
+  *         \arg UART_FLAG_THR_EMPTY: tx FIFO is empty.
+  *         \arg UART_FLAG_THR_TSR_EMPTY: tx FIFO and tx shift reg are both empty.
+  *         \arg UART_FLAG_RX_FIFO_ERR: rx FIFO error.
+  *         \arg UART_FLAG_RX_IDLE.
+  * \return The new state of UART_FLAG (SET or RESET).
+  */
+FlagStatus UART_GetFlagStatus(UART_TypeDef *UARTx, uint32_t UART_FLAG)
+{
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+    assert_param(IS_UART_GET_FLAG(UART_FLAG));
+
+    FlagStatus bitstatus = RESET;
+
+    if (UART_FLAG == UART_FLAG_RX_IDLE)
+    {
+        if (UARTx->UART_RX_TIMEOUT_STS & BIT(0))
+        {
+            bitstatus = SET;
+        }
+    }
+#if UART_SUPPORT_TX_DONE
+    else if (UART_FLAG == UART_FLAG_TX_THD)
+    {
+        if (UARTx->UART_TX_THD_INT & BIT(0))
+        {
+            bitstatus = SET;
+        }
+    }
+#endif
+#if UART_SUPPORT_TX_THD
+    else if (UART_FLAG == UART_FLAG_TX_DONE)
+    {
+        if (UARTx->UART_TXDONE_INT & BIT(0))
+        {
+            bitstatus = SET;
+        }
+    }
+#endif
+    else
+    {
+        if (UART_GetLineStatus(UARTx) & UART_FLAG)
+        {
+            bitstatus = SET;
+        }
+    }
+
+    return bitstatus;
+}
+
+/**
+  * \brief  Get line status.
+  * \param  UARTx: Select the UART peripheral. \ref UART_Declaration
+  * \return Line status.
+  */
+uint8_t UART_GetLineStatus(UART_TypeDef *UARTx)
+{
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+
+    return (uint8_t)(UARTx->UART_LSR & (0x000000FF));
+}
+
+/**
+ * \brief   Send one byte of data.
+ * \param   UARTx: Select the UART peripheral. \ref UART_Declaration
+ * \param   data: Byte data to send.
+ * \return  None.
+ */
+void UART_SendByte(UART_TypeDef *UARTx, uint8_t data)
+{
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+
+    UARTx->UART_RBR_THR = data;
+
+    return;
+}
+
+#if UART_SUPPORT_HALF_WORD
+/**
+ * \brief   Send half word of data.
+ * \param   UARTx: Select the UART peripheral. \ref UART_Declaration
+ * \param   data: Byte data to send.
+ * \return  None.
+ */
+void UART_SendHalfWord(UART_TypeDef *UARTx, uint16_t data)
+{
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+
+    UARTx->UART_RBR_THR = data;
+
+    return;
+}
+#endif
+
+/**
+ * \brief   Read a byte of data from UART RX FIFO.
+ * \param   UARTx: Select the UART peripheral. \ref UART_Declaration
+ * \return  Which byte data has been read.
+ */
+uint8_t UART_ReceiveByte(UART_TypeDef *UARTx)
+{
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+
+    return (uint8_t)(UARTx->UART_RBR_THR);
+}
+
+#if UART_SUPPORT_HALF_WORD
+/**
+ * \brief   Read a byte of data from UART RX FIFO.
+ * \param   UARTx: Select the UART peripheral. \ref UART_Declaration
+ * \return  Which byte data has been read.
+ */
+uint8_t UART_ReceiveHalfWord(UART_TypeDef *UARTx)
+{
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+
+    return (uint16_t)(UARTx->UART_RBR_THR);
+}
+#endif
+
+/**
+ * \brief   Get interrupt identifier of the selected UART peripheral.
+ * \param   UARTx: Select the UART peripheral. \ref UART_Declaration
+ * \return  The interrupt identifier value.
+ *          This return value can be one or a combination of the following:
+ *          \retval UART_INT_ID_LINE_STATUS: Rx line status interrupt ID.
+ *          \retval UART_INT_ID_RX_LEVEL_REACH: Rx data available or trigger level reached interrupt ID.
+ *          \retval UART_INT_ID_RX_TMEOUT: Rx FIFO data timeout interrupt ID.
+ *          \retval UART_INT_ID_TX_FIFO_EMPTY: Tx FIFO empty interrupt ID.
+ *          \retval UART_INT_ID_MODEM_STATUS: Modem status interrupt ID.
+ */
+uint16_t UART_GetIID(UART_TypeDef *UARTx)
+{
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+
+    return (uint16_t)(UARTx->UART_IIR_FCR & (0x0000000E));
+}
+
+#if UART_SUPPORT_CLEAR_TX_FIFO
+/**
+ * \brief   Clear Tx FIFO of the selected UART peripheral.
+ * \param   UARTx: Select the UART peripheral. \ref UART_Declaration
+ * \return  None.
+ */
+void UART_ClearTxFIFO(UART_TypeDef *UARTx)
+{
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+
+    UARTx->UART_IIR_FCR = (((UARTx->UART_STSR & BIT24) >> 21) | \
+                           ((UARTx->UART_STSR & 0x7C000000) >> 18) | \
+                           ((UARTx->UART_STSR & BIT25) >> 25) | \
+                           FCR_CLEAR_TX_FIFO_Set);
+
+    return;
+}
+#endif
+
+/**
+ * \brief   Clear Rx FIFO of the selected UART peripheral.
+ * \param   UARTx: Select the UART peripheral. \ref UART_Declaration
+ * \return  None.
+ */
+void UART_ClearRxFIFO(UART_TypeDef *UARTx)
+{
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+
+    UARTx->UART_IIR_FCR = (((UARTx->UART_STSR & BIT24) >> 21) | \
+                           ((UARTx->UART_STSR & 0x7C000000) >> 18) | \
+                           ((UARTx->UART_STSR & BIT25) >> 25) | \
+                           FCR_CLEAR_RX_FIFO_Set);
+
+    return;
+}
+
+/**
+ * \brief   Get the data length in Tx FIFO of the selected UART peripheral.
+ * \param   UARTx: Select the UART peripheral. \ref UART_Declaration
+ * \return  Data length in UART TX FIFO.
+ */
+uint8_t UART_GetTxFIFODataLen(UART_TypeDef *UARTx)
+{
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+
+    return (uint8_t)(UARTx->UART_RXTX_FIFO_WL & 0x1F);
+}
+
+/**
+ * \brief   Get the data length in Rx FIFO of the selected UART peripheral.
+ * \param   UARTx: Select the UART peripheral. \ref UART_Declaration
+ * \return  Data length in UART RX FIFO.
+ */
+uint8_t UART_GetRxFIFODataLen(UART_TypeDef *UARTx)
+{
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+
+    return (uint8_t)((UARTx->UART_RXTX_FIFO_WL >> 8) & 0x3F);
+}
+
+/**
+ * \brief    Enable/Disable DMA mode on UART side.
+ * \param    UARTx: Select the UART peripheral. \ref UART_Declaration
+ * \param    NewState: Enable or disable UART DMA mode.
+ *           This parameter can be one of the following values:
+ *           \arg true: Enable UART DMA mode.
+ *           \arg false: Disable UART DMA mode.
+ * \return   None.
+ */
+void UART_TxDmaCmd(UART_TypeDef *UARTx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+
+    UART_MISCR_TypeDef uart_0x28 = {.d32 = UARTx->UART_MISCR};
+    uart_0x28.b.txdma_en = NewState;
+    UARTx->UART_MISCR = uart_0x28.d32;
+}
+
+/**
+ * \brief    Enable/Disable DMA mode on UART side.
+ * \param    UARTx: Select the UART peripheral. \ref UART_Declaration
+ * \param    NewState: Enable or disable UART DMA mode.
+ *           This parameter can be one of the following values:
+ *           \arg true: Enable UART DMA mode.
+ *           \arg false: Disable UART DMA mode.
+ * \return   None.
+ */
+void UART_RxDmaCmd(UART_TypeDef *UARTx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+
+    UART_MISCR_TypeDef uart_0x28 = {.d32 = UARTx->UART_MISCR};
+    uart_0x28.b.rxdma_en = NewState;
+    UARTx->UART_MISCR = uart_0x28.d32;
+}
+
diff --git a/bee/drivers/uart/src/device/rtl87x2g/rtl_uart.h b/bee/drivers/uart/src/device/rtl87x2g/rtl_uart.h
new file mode 100644
index 00000000..ef276c4f
--- /dev/null
+++ b/bee/drivers/uart/src/device/rtl87x2g/rtl_uart.h
@@ -0,0 +1,1200 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *               Define to prevent recursive inclusion
+ *============================================================================*/
+#ifndef RTL_UART_H
+#define RTL_UART_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*============================================================================*
+ *                        Header Files
+ *============================================================================*/
+#include "utils/rtl_utils.h"
+#include "rtl_uart_def.h"
+
+/** \defgroup UART        UART
+  * \brief
+  * \{
+  */
+/*============================================================================*
+ *                         Constants
+ *============================================================================*/
+/** \defgroup UART_Exported_Constants UART Exported Constants
+  * \brief
+  * \{
+  */
+
+/**
+ * \defgroup    UART_FIFO_Size UART FIFO Size
+ * \{
+ * \ingroup     UART_Exported_Constants
+ */
+#define UART_TX_FIFO_SIZE           16 //!< UART TX FIFO size is 16.
+#define UART_RX_FIFO_SIZE           32 //!< UART RX FIFO size is 32.
+
+/** End of UART_FIFO_Size
+  * \}
+  */
+
+/**
+ * \defgroup    UART_Baudrate UART Baudrate
+ * \{
+ * \ingroup     UART_Exported_Constants
+ */
+typedef enum
+{
+    UART_BAUD_RATE_1200,      //!< UART bandrate is 1200Hz.
+    UART_BAUD_RATE_4800,      //!< UART bandrate is 4800Hz.
+    UART_BAUD_RATE_7200,      //!< UART bandrate is 7200Hz.
+    UART_BAUD_RATE_9600,      //!< UART bandrate is 9600Hz.
+    UART_BAUD_RATE_14400,     //!< UART bandrate is 14400Hz.
+    UART_BAUD_RATE_19200,     //!< UART bandrate is 19200Hz.
+    UART_BAUD_RATE_28800,     //!< UART bandrate is 28800Hz.
+    UART_BAUD_RATE_38400,     //!< UART bandrate is 38400Hz.
+    UART_BAUD_RATE_57600,     //!< UART bandrate is 57600Hz.
+    UART_BAUD_RATE_76800,     //!< UART bandrate is 76800Hz.
+    UART_BAUD_RATE_115200,    //!< UART bandrate is 115200Hz.
+    UART_BAUD_RATE_128000,    //!< UART bandrate is 128000Hz.
+    UART_BAUD_RATE_153600,    //!< UART bandrate is 153600Hz.
+    UART_BAUD_RATE_230400,    //!< UART bandrate is 230400Hz.
+    UART_BAUD_RATE_460800,    //!< UART bandrate is 460800Hz.
+    UART_BAUD_RATE_500000,    //!< UART bandrate is 500000Hz.
+    UART_BAUD_RATE_921600,    //!< UART bandrate is 921600Hz.
+    UART_BAUD_RATE_1000000,   //!< UART bandrate is 1000000Hz.
+    UART_BAUD_RATE_1382400,   //!< UART bandrate is 1382400Hz.
+    UART_BAUD_RATE_1444400,   //!< UART bandrate is 1444400Hz.
+    UART_BAUD_RATE_1500000,   //!< UART bandrate is 1500000Hz.
+    UART_BAUD_RATE_1843200,   //!< UART bandrate is 1843200Hz.
+    UART_BAUD_RATE_2000000,   //!< UART bandrate is 2000000Hz.
+    UART_BAUD_RATE_3000000,   //!< UART bandrate is 3000000Hz.
+    UART_BAUD_RATE_4000000,   //!< UART bandrate is 4000000Hz.
+} UARTBaudrate_TypeDef;
+
+/** End of UART_Baudrate
+  * \}
+  */
+
+/**
+ * \defgroup    UART_Parity UART Parity
+ * \{
+ * \ingroup     UART_Exported_Constants
+ */
+typedef enum
+{
+    UART_PARITY_NO_PARTY = 0x0,      //!< UART has no parity.
+    UART_PARITY_ODD = 0x1,           //!< UART parity bit is set to odd.
+    UART_PARITY_EVEN = 0x3,          //!< UART parity bit is set to even.
+} UARTParity_TypeDef;
+
+#define IS_UART_PARITY(PARITY) (((PARITY) == UART_PARITY_NO_PARTY) || \
+                                ((PARITY) == UART_PARITY_ODD) || \
+                                ((PARITY) == UART_PARITY_EVEN)) //!< Check if the input parameter is valid.
+
+/** End of UART_Parity
+  * \}
+  */
+
+/**
+ * \defgroup    UART_Stop_Bits UART Stop Bits
+ * \{
+ * \ingroup     UART_Exported_Constants
+ */
+typedef enum
+{
+    UART_STOP_BITS_1 = 0x0,      //!< UART is configured with 1 stop bit.
+    UART_STOP_BITS_2 = 0x1,      //!< UART is configured with 2 stop bit.
+} UARTStopBits_TypeDef;
+
+#define IS_UART_STOPBITS(STOP) (((STOP) == UART_STOP_BITS_1) || \
+                                ((STOP) == UART_STOP_BITS_2)) //!< Check if the input parameter is valid.
+
+/** End of UART_Stop_Bits
+  * \}
+  */
+
+/**
+ * \defgroup    UART_Word_Length UART Word Length
+ * \{
+ * \ingroup     UART_Exported_Constants
+ */
+typedef enum
+{
+    UART_WORD_LENGTH_7BIT = 0x0,     //!< UART word length is set to 7 Data Bits.
+    UART_WORD_LENGTH_8BIT = 0x1,     //!< UART word length is set to 8 Data Bits.
+} UARTWordLen_TypeDef;
+
+#define IS_UART_WORD_LENGTH(LEN) ((((LEN)) == UART_WORD_LENGTH_7BIT) || \
+                                  (((LEN)) == UART_WORD_LENGTH_8BIT)) //!< Check if the input parameter is valid.
+
+/** End of UART_Word_Length
+  * \}
+  */
+
+/**
+ * \defgroup    UART_Hardware_Flow_Control UART Hardware Flow Control
+ * \{
+ * \ingroup     UART_Exported_Constants
+ */
+typedef enum
+{
+    UART_HW_FLOW_CTRL_DISABLE = 0x0,     //!< Disable UART hardware flow control.
+    UART_HW_FLOW_CTRL_ENABLE = 0x1,      //!< Enable UART hardware flow control.
+} UARTHwFlowCtrl_TypeDef;
+
+#define IS_UART_AUTO_FLOW_CTRL(CTRL) (((CTRL) == UART_HW_FLOW_CTRL_ENABLE) || \
+                                      ((CTRL) == UART_HW_FLOW_CTRL_DISABLE)) //!< Check if the input parameter is valid.
+
+/** End of UART_Hardware_Flow_Control
+  * \}
+  */
+
+/**
+ * \defgroup    UART_DMA UART DMA
+ * \{
+ * \ingroup     UART_Exported_Constants
+ */
+typedef enum
+{
+    UART_DMA_DISABLE = 0x0,     //!< Disable UART DMA function.
+    UART_DMA_ENABLE  = 0x1,     //!< Enable UART DMA function.
+} UARTDma_TypeDef;
+
+#define IS_UART_DMA_CFG(CFG) (((CFG) == UART_DMA_ENABLE) || \
+                              ((CFG) == UART_DMA_DISABLE)) //!< Check if the input parameter is valid.
+
+/** End of UART_DMA
+  * \}
+  */
+
+/**
+ * \defgroup    UART_Rx_Idle_Time UART Rx Idle Time
+ * \{
+ * \ingroup     UART_Exported_Constants
+ */
+typedef enum
+{
+    UART_RX_IDLE_1BYTE = 0x0,        //!< UART Rx idle time is set to 1 byte.
+    UART_RX_IDLE_2BYTE = 0x1,        //!< UART Rx idle time is set to 2 bytes.
+    UART_RX_IDLE_4BYTE = 0x2,        //!< UART Rx idle time is set to 4 bytes.
+    UART_RX_IDLE_8BYTE = 0x3,        //!< UART Rx idle time is set to 8 bytes.
+    UART_RX_IDLE_16BYTE = 0x4,       //!< UART Rx idle time is set to 16 bytes.
+    UART_RX_IDLE_32BYTE = 0x5,       //!< UART Rx idle time is set to 32 bytes.
+    UART_RX_IDLE_64BYTE = 0x6,       //!< UART Rx idle time is set to 64 bytes.
+    UART_RX_IDLE_128BYTE = 0x7,      //!< UART Rx idle time is set to 128 bytes.
+    UART_RX_IDLE_256BYTE = 0x8,      //!< UART Rx idle time is set to 256 bytes.
+    UART_RX_IDLE_512BYTE = 0x9,      //!< UART Rx idle time is set to 512 bytes.
+    UART_RX_IDLE_1024BYTE = 0xA,     //!< UART Rx idle time is set to 1024 bytes.
+    UART_RX_IDLE_2048BYTE = 0xB,     //!< UART Rx idle time is set to 2048 bytes.
+    UART_RX_IDLE_4096BYTE = 0xC,     //!< UART Rx idle time is set to 4096 bytes.
+    UART_RX_IDLE_8192BYTE = 0xD,     //!< UART Rx idle time is set to 8192 bytes.
+    UART_RX_IDLE_16384BYTE = 0xE,    //!< UART Rx idle time is set to 16384 bytes.
+    UART_RX_IDLE_32768BYTE = 0xF,    //!< UART Rx idle time is set to 32768 bytes.
+} UARTTimeout_TypeDef;
+
+#define IS_UART_IDLE_TIME(TIME) ((TIME) <= 0x0F) //!< Check if the input parameter is valid.
+
+/** End of UART_Rx_Idle_Time
+  * \}
+  */
+
+/**
+ * \defgroup    UART_Rx_FIFO_Trigger_Level UART Rx FIFO Trigger Level
+ * \{
+ * \ingroup     UART_Exported_Constants
+ */
+typedef enum
+{
+    UART_RX_FIFO_TRIGGER_LEVEL_1BYTE = 0x1,    //!< UART Rx FIFO trigger level is set to 1 byte.
+    UART_RX_FIFO_TRIGGER_LEVEL_4BYTE = 0x4,    //!< UART Rx FIFO trigger level is set to 4 bytes.
+    UART_RX_FIFO_TRIGGER_LEVEL_8BYTE = 0x8,    //!< UART Rx FIFO trigger level is set to 8 bytes.
+    UART_RX_FIFO_TRIGGER_LEVEL_14BYTE = 0xE,   //!< UART Rx FIFO trigger level is set to 14 bytes.
+} UARTRxFifoTriggerLevel_TypeDef;
+
+#define IS_UART_RX_FIFO_TRIGGER_LEVEL(BYTES) ((BYTES) <= 29) //!< Check if the input parameter is valid.
+
+/** End of UART_Rx_FIFO_Trigger_Level
+  * \}
+  */
+
+#if (UART_SUPPORT_RAP_FUNCTION == 1)
+/**
+ * \defgroup    UART_Qactive_Force UART Qactive Force
+ * \{
+ * \ingroup     UART_Exported_Constants
+ */
+typedef enum
+{
+    UART_QACTIVE_SCLK_FORCE = 0x0,
+    UART_QACTIVE_PCLK_FORCE = 0x1,
+    UART_QACTIVE_PCLK_ICG   = 0x2,
+} UARTQactiveForce_TypeDef;
+
+/** End of UART_Qactive_Force
+  * \}
+  */
+
+#endif
+
+/**
+ * \defgroup    UART_Interrupts UART Interrupts
+ * \{
+ * \ingroup     UART_Exported_Constants
+ */
+#define UART_INT_RD_AVA                 BIT0     //!< UART Rx data available interrupt
+#define UART_INT_TX_FIFO_EMPTY          BIT1     //!< UART Tx FIFO empty interrupt
+#define UART_INT_RX_LINE_STS            BIT2     //!< UART Rx line status error interrupt
+//#define UART_INT_MODEM_STS              BIT3
+#if UART_SUPPORT_TX_DONE
+#define UART_INT_TX_DONE                BIT4     //!< UART Tx done interrupt
+#endif
+#if UART_SUPPORT_TX_THD
+#define UART_INT_TX_THD                 BIT5     //!< UART Tx threshold interrupt
+#endif
+//#define UART_INT_RX_BREAK               BIT6
+#define UART_INT_RX_IDLE                BIT7     //!< UART Rx idle interrupt
+
+#define IS_UART_INT(INT) ((((INT) & 0xFFFFFF80) == 0x00) && ((INT) != 0x00)) //!< Check if the input parameter is valid.
+
+#define IS_UART_GET_INT(INT) ((INT) & (UART_INT_RD_AVA | \
+                                       UART_INT_TX_FIFO_EMPTY | \
+                                       UART_INT_RX_LINE_STS | \
+                                       UART_INT_MODEM_STS | \
+                                       UART_INT_TX_DONE | \
+                                       UART_INT_TX_THD | \
+                                       UART_INT_RX_BREAK | \
+                                       UART_INT_RX_IDLE)) //!< Check if the input parameter is valid.
+
+/** End of UART_Interrupts
+  * \}
+  */
+
+/**
+ * \defgroup    UART_Interrupt_Identifier UART Interrupt Identifier
+ * \{
+ * \ingroup     UART_Exported_Constants
+ */
+#define UART_INT_PENDING                ((uint16_t)(0x01 << 0))     //!< UART interrupt is pending.
+#define UART_INT_ID_LINE_STATUS         ((uint16_t)(0x03 << 1))     //!< UART Rx line status interrupt ID.
+#define UART_INT_ID_RX_LEVEL_REACH      ((uint16_t)(0x02 << 1))     //!< UART Rx data available or trigger level reached interrupt ID.
+#define UART_INT_ID_RX_DATA_TIMEOUT     ((uint16_t)(0x06 << 1))     //!< UART Rx FIFO data timeout interrupt ID.
+#define UART_INT_ID_TX_FIFO_EMPTY       ((uint16_t)(0x01 << 1))     //!< UART Tx FIFO empty interrupt ID.
+//#define UART_INT_ID_MODEM_STATUS        ((uint16_t)(0x00 << 1))
+
+#define IS_UART_INT_ID(ID) (((ID) == UART_INT_ID_LINE_STATUS) || \
+                            ((ID) == UART_INT_ID_RX_LEVEL_REACH) || \
+                            ((ID) == UART_INT_ID_RX_DATA_TIMEOUT) || \
+                            ((ID) == UART_INT_ID_TX_FIFO_EMPTY) || \
+                            ((ID) == UART_INT_ID_MODEM_STATUS)) //!< Check if the input parameter is valid.
+
+/** End of UART_Interrupt_Identifier
+  * \}
+  */
+
+/**
+ * \defgroup    UART_Flag UART Flag
+ * \{
+ * \ingroup     UART_Exported_Constants
+ */
+#define UART_FLAG_RX_DATA_AVA           BIT0     //!< UART Rx data available interrupt flag.
+#define UART_FLAG_RX_OVERRUN            BIT1     //!< UART Rx FIFO overrun interrupt flag.
+#define UART_FLAG_RX_PARITY_ERR         BIT2     //!< UART Rx parity error interrupt flag.
+#define UART_FLAG_RX_FRAME_ERR          BIT3     //!< UART Rx frame error interrupt flag.
+#define UART_FLAG_RX_BREAK_ERR          BIT4     //!< UART Rx break error interrupt flag.
+#define UART_FLAG_TX_FIFO_EMPTY         BIT5     //!< UART Tx holding register or Tx FIFO empty interrupt flag.
+#define UART_FLAG_TX_EMPTY              BIT6     //!< UART Tx FIFO and Tx shift register are both empty interrupt flag.
+#define UART_FLAG_RX_FIFO_ERR           BIT7     //!< UART Rx FIFO error interrupt flag.
+//#define UART_FLAG_RX_BREAK              BIT8
+#define UART_FLAG_RX_IDLE               BIT9     //!< UART Rx idle interrupt flag.
+#if UART_SUPPORT_TX_DONE
+#define UART_FLAG_TX_DONE               BIT10    //!< UART Tx done interrupt flag.
+#endif
+#if UART_SUPPORT_TX_THD
+#define UART_FLAG_TX_THD                BIT11    //!< UART Tx threshold interrupt flag.
+#endif
+
+#define IS_UART_GET_FLAG(FLAG) (((FLAG) == UART_FLAG_RX_DATA_RDY) || \
+                                ((FLAG) == UART_FLAG_RX_OVERRUN) || \
+                                ((FLAG) == UART_FLAG_PARTY_ERR) || \
+                                ((FLAG) == UART_FLAG_FRAME_ERR) || \
+                                ((FLAG) == UART_FLAG_BREAK_ERR) || \
+                                ((FLAG) == UART_FLAG_THR_EMPTY) || \
+                                ((FLAG) == UART_FLAG_THR_TSR_EMPTY) || \
+                                ((FLAG) == UART_FLAG_RX_FIFO_ERR) || \
+                                ((FLAG) == UART_FLAG_RX_IDLE)) //!< Check if the input parameter is valid.
+
+/** End of UART_Flag
+  * \}
+  */
+
+/**
+ * \defgroup    UART_Interrupts_Mask UART Interrupts Mask
+ * \{
+ * \ingroup     UART_Exported_Constants
+ */
+#define UART_INT_MASK_RD_AVA            BIT0 //!< Mask received data avaliable interrupt(RX fifo trigger level or timeout).
+#define UART_INT_MASK_TX_FIFO_EMPTY     BIT1 //!< Mask transmitter FIFO empty interrupt.
+#define UART_INT_MASK_RX_LINE_STS       BIT2 //!< Mask receiver line status interrupt.
+//#define UART_INT_MASK_MODEM_STS         BIT3
+//#define UART_INT_MASK_RX_BREAK          BIT4
+#define UART_INT_MASK_RX_IDLE           BIT5 //!< Mask RX idle timeout interrupt.
+#if UART_SUPPORT_TX_DONE
+#define UART_INT_MASK_TX_DONE           BIT6 //!< Mask TX done(TX shift register empty and TX FIFO empty) interrupt.
+#endif
+#if UART_SUPPORT_TX_THD
+#define UART_INT_MASK_TX_THD            BIT7 //!< Mask TX FIFO threshold interrupt.
+#endif
+
+#define IS_UART_INT_MASK(INT) ((INT) & (UART_INT_MASK_RD_AVA | \
+                                        UART_INT_MASK_TX_FIFO_EMPTY | \
+                                        UART_INT_MASK_RX_LINE_STS | \
+                                        UART_INT_MASK_MODEM_STS | \
+                                        UART_INT_MASK_RX_BREAK | \
+                                        UART_INT_MASK_RX_IDLE | \
+                                        UART_INT_MASK_TX_DONE | \
+                                        UART_INT_MASK_TX_THD)) //!< Check if the input parameter is valid.
+
+/** End of UART_Interrupts_Mask
+  * \}
+  */
+
+
+/** End of UART_Exported_Constants
+  * \}
+  */
+
+/*============================================================================*
+ *                         Types
+ *============================================================================*/
+/** \defgroup UART_Exported_Types UART Exported Types
+  * \brief
+  * \{
+  */
+
+/**
+ * \brief       UART initialize parameters
+ *
+ * \ingroup     UART_Exported_Types
+ */
+typedef struct
+{
+    uint16_t UART_OvsrAdj;              /*!< Specify the baudrate setting of ovsr_adj.
+                                             Please refer to UART_BaudRate_Table in \ref UART_SetBaudRate. */
+
+    uint16_t UART_Div;                  /*!< Specify the baud rate setting of div.
+                                             Please refer to UART_BaudRate_Table in \ref UART_SetBaudRate. */
+
+    uint16_t UART_Ovsr;                 /*!< Specify the baud rate setting of ovsr.
+                                             Please refer to UART_BaudRate_Table in \ref UART_SetBaudRate. */
+
+    UARTWordLen_TypeDef UART_WordLen;   /*!< Specify the UART word length.
+                                             This parameter can be a value of \ref UART_Word_Length. */
+
+    UARTStopBits_TypeDef UART_StopBits; /*!< Specify the UART stop bit.
+                                             This parameter can be a value of \ref UART_Stop_Bits. */
+
+    UARTParity_TypeDef UART_Parity;     /*!< Specify the parity.
+                                             This parameter can be a value of \ref UART_Parity. */
+
+    uint8_t UART_TxThdLevel;            /*!< Specify the Tx threshold level.
+                                             This parameter must range from 1 to 29.*/
+
+    uint8_t UART_RxThdLevel;            /*!< Specify the Rx threshold level.
+                                             This parameter must range from 1 to 29.*/
+
+    UARTTimeout_TypeDef UART_IdleTime;  /*!< Specify the idle time.
+                                             This parameter can be a value of \ref UART_Rx_Idle_Time. */
+
+    uint8_t UART_HardwareFlowControl;   /*!< Enable or Disable hardware flow control.
+                                             This parameter can be a value of DISABLE and ENABLE. */
+
+    uint8_t UART_DmaEn;                 /*!< Enable or Disable dma mode.
+                                             This parameter can be a value of DISABLE and ENABLE. */
+
+    uint8_t UART_TxDmaEn;               /*!< Enable or Disable Tx dma mode.
+                                             This parameter can be a value of DISABLE and ENABLE. */
+
+    uint8_t UART_RxDmaEn;               /*!< Enable or Disable Rx dma mode.
+                                             This parameter can be a value of DISABLE and ENABLE. */
+
+    uint8_t UART_TxWaterLevel;          /*!< Specify the DMA tx water level.
+                                             This parameter must range from 1 to 16. */
+
+    uint8_t UART_RxWaterLevel;          /*!< Specify the DMA rx water level.
+                                             This parameter must range from 1 to 31. */
+} UART_InitTypeDef;
+
+/** End of UART_Exported_Types
+  * \}
+  */
+
+/*============================================================================*
+ *                         Functions
+ *============================================================================*/
+/** \defgroup UART_Exported_Functions UART Exported Functions
+  * \brief
+  * \{
+  */
+
+/**
+ * \brief   Deinitialize the selected UART peripheral registers to their default reset values(turn off UART clock).
+ *
+ * \param[in] UARTx  Select the UART peripheral. Refer to \ref UART_Declaration.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_uart_init(void)
+ * {
+ *    UART_DeInit(UART0);
+ * }
+ * \endcode
+ */
+void UART_DeInit(UART_TypeDef *UARTx);
+
+/**
+ * \brief   Initialize the selected UART peripheral according to the specified
+ *          parameters in  UART_InitStruct.
+ *
+ * \param[in] UARTx            Select the UART peripheral. Refer to \ref UART_Declaration.
+ * \param[in] UART_InitStruct  Pointer to a UART_InitTypeDef structure which will be initialized.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_uart_init(void)
+ * {
+ *     UART_DeInit(UART0);
+ *
+ *     RCC_PeriphClockCmd(APBPeriph_UART0, APBPeriph_UART0_CLOCK, ENABLE);
+ *
+ *     UART_InitTypeDef UART_InitStruct;
+ *     UART_StructInit(&UART_InitStruct);
+ *     UART_InitStruct.UART_Div         = 20;
+ *     UART_InitStruct.UART_Ovsr        = 12;
+ *     UART_InitStruct.UART_OvsrAdj     = 0x252;
+ *     UART_InitStruct.UART_RxThdLevel  = 16;
+ *    //Add other initialization parameters that need to be configured here.
+ *     UART_Init(UART0, &UART_InitStruct);
+ * }
+ * \endcode
+ */
+void UART_Init(UART_TypeDef *UARTx, UART_InitTypeDef *UART_InitStruct);
+
+/**
+ * \brief   Fill each UART_InitStruct member with its default value.
+ *
+ * \note   The default settings for the UART_InitStruct member are shown in the following table:
+ *         | UART_InitStruct member     | Default value                  |
+ *         |:--------------------------:|:------------------------------:|
+ *         | UART_Div                   | 20                             |
+ *         | UART_Ovsr                  | 12                             |
+ *         | UART_OvsrAdj               | 0x252                          |
+ *         | UART_Parity                | \ref UART_PARITY_NO_PARTY      |
+ *         | UART_StopBits              | \ref UART_STOP_BITS_1          |
+ *         | UART_WordLen               | \ref UART_WORD_LENGTH_8BIT     |
+ *         | UART_TxThdLevel            | 16                             |
+ *         | UART_RxThdLevel            | 16                             |
+ *         | UART_IdleTime              | \ref UART_RX_IDLE_2BYTE        |
+ *         | UART_HardwareFlowControl   | \ref UART_HW_FLOW_CTRL_DISABLE |
+ *         | UART_DmaEn                 | \ref UART_DMA_DISABLE          |
+ *         | UART_TxDmaEn               | DISABLE                        |
+ *         | UART_RxDmaEn               | DISABLE                        |
+ *         | UART_TxWaterLevel          | 15                             |
+ *         | UART_RxWaterLevel          | 1                              |
+ *
+ * \param[in] UART_InitStruct  Pointer to an UART_InitTypeDef structure which will be initialized.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_uart_init(void)
+ * {
+ *     UART_DeInit(UART0);
+ *
+ *     RCC_PeriphClockCmd(APBPeriph_UART0, APBPeriph_UART0_CLOCK, ENABLE);
+ *
+ *     UART_InitTypeDef UART_InitStruct;
+ *     UART_StructInit(&UART_InitStruct);
+ *     UART_InitStruct.UART_Div         = 20;
+ *     UART_InitStruct.UART_Ovsr        = 12;
+ *     UART_InitStruct.UART_OvsrAdj     = 0x252;
+ *     UART_InitStruct.UART_RxThdLevel  = 16;
+ *     //Add other initialization parameters that need to be configured here.
+ *     UART_Init(UART0, &UART_InitStruct);
+ * }
+ * \endcode
+ */
+void UART_StructInit(UART_InitTypeDef *UART_InitStruct);
+
+/**
+ * \brief   Mask or unmask the specified UART interrupt source.
+ *
+ * \param[in] UARTx     Select the UART peripheral. Refer to \ref UART_Declaration.
+ * \param[in] UART_INT  Specify the UART interrupt source that to be mask or unmask.
+ *                      This parameter can be one of the following values, refer to \ref UART_Interrupts_Mask.
+ *                      \arg UART_INT_MASK_RD_AVA: Mask INTCR(erbi).
+ *                      \arg UART_INT_MASK_FIFO_EMPTY: Mask INTCR(etbei).
+ *                      \arg UART_INT_MASK_LINE_STS: Mask INTCR(elsi).
+ *                      \arg UART_INT_MASK_MODEM_STS: Mask INTCR(edssi).
+ *                      \arg UART_INT_MASK_RX_BREAK: Mask rx break interrupt.
+ *                      \arg UART_INT_MASK_RX_IDLE: Mask rx break interrupt.
+ *                      \arg UART_INT_MASK_TX_DONE: Mask the interrupt tx done interrupt.
+ *                      \arg UART_INT_MASK_TX_THD: Mask tx fifo threshold interrupt.
+ * \param[in] NewState  New state of the specified UART interrupt source.
+ *                      This parameter can be one of the following values:
+ *                      - ENABLE: Mask the specified UART interrupt source.
+ *                      - DISABLE: Unmask the specified UART interrupt source.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_uart_init(void)
+ * {
+ *     UART_DeInit(UART0);
+ *
+ *     RCC_PeriphClockCmd(APBPeriph_UART0, APBPeriph_UART0_CLOCK, ENABLE);
+ *
+ *     UART_InitTypeDef UART_InitStruct;
+ *     UART_StructInit(&UART_InitStruct);
+ *     UART_InitStruct.UART_Div         = 20;
+ *     UART_InitStruct.UART_Ovsr        = 12;
+ *     UART_InitStruct.UART_OvsrAdj     = 0x252;
+ *     UART_InitStruct.UART_RxThdLevel  = 16;
+ *     //Add other initialization parameters that need to be configured here.
+ *     UART_Init(UART0, &UART_InitStruct);
+ *
+ *     UART_MaskINTConfig(UART0, UART_INT_MASK_RD_AVA, ENABLE);
+ *     UART_INTConfig(UART0, UART_INT_RD_AVA, ENABLE);
+ *     UART_MaskINTConfig(UART0, UART_INT_MASK_RD_AVA, DISABLE);
+ * }
+ * \endcode
+ */
+void UART_MaskINTConfig(UART_TypeDef *UARTx, uint32_t UART_INT_MASK,
+                        FunctionalState NewState);
+/**
+ * \brief   Enable or disable the specified UART interrupts.
+ *
+ * \param[in] UARTx     Select the UART peripheral. Refer to \ref UART_Declaration.
+ * \param[in] UART_IT   Specify the UART interrupt source that to be enabled or disabled.
+ *                      This parameter can be any combination of the following values, refer to \ref UART_Interrupts.
+ *                      \arg UART_INT_RD_AVA: Rx data avaliable interrupt source.
+ *                      \arg UART_INT_TX_FIFO_EMPTY: Tx FIFO empty interrupt source.
+ *                      \arg UART_INT_RX_LINE_STS: Rx line status interrupt source.
+ *                      \arg UART_INT_MODEM_STS: Modem status interrupt source.
+ *                      \arg UART_INT_TX_DONE: Tx done interrupt source.
+ *                      \arg UART_INT_TX_THD: Tx threshold(FIFO data length <= thredhold) interrupt source.
+ *                      \arg UART_INT_RX_BREAK: Rx break signal interrupt source.
+ *                      \arg UART_INT_RX_IDLE: Rx bus ilde interrupt source.
+ * \param[in] NewState  New state of the specified UART interrupt source.
+ *                      This parameter can be one of the following values:
+ *                      - ENABLE: Enable the specified UART interrupt.
+ *                      - DISABLE: Disable the specified UART interrupt.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_uart_init(void)
+ * {
+ *     UART_DeInit(UART0);
+ *
+ *     RCC_PeriphClockCmd(APBPeriph_UART0, APBPeriph_UART0_CLOCK, ENABLE);
+ *
+ *     UART_InitTypeDef UART_InitStruct;
+ *     UART_StructInit(&UART_InitStruct);
+ *     UART_InitStruct.UART_Div         = 20;
+ *     UART_InitStruct.UART_Ovsr        = 12;
+ *     UART_InitStruct.UART_OvsrAdj     = 0x252;
+ *     UART_InitStruct.UART_RxThdLevel  = 16;
+ *     //Add other initialization parameters that need to be configured here.
+ *     UART_Init(UART0, &UART_InitStruct);
+ *
+ *     UART_INTConfig(UART0, UART_INT_RD_AVA, ENABLE);
+ * }
+ * \endcode
+ */
+void UART_INTConfig(UART_TypeDef *UARTx, uint32_t UART_IT, FunctionalState NewState);
+
+/**
+ * \brief   Send data.
+ *
+ * \param[in] UARTx  Select the UART peripheral. Refer to \ref UART_Declaration.
+ * \param[in] inBuf  Buffer of data to be sent.
+ * \param[in] count  Length of data to be sent.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void uart_demo(void)
+ * {
+ *     uint8_t data[] = "UART demo";
+ *     UART_SendData(UART0, data, sizeof(data));
+ * }
+ * \endcode
+ */
+void UART_SendData(UART_TypeDef *UARTx, const uint8_t *inBuf, uint16_t Count);
+
+#if UART_SUPPORT_HALF_WORD
+/**
+ * \brief   Send half word data.
+ *
+ * \param[in] UARTx  Select the UART peripheral. Refer to \ref UART_Declaration.
+ * \param[in] inBuf  Buffer of data to be sent.
+ * \param[in] count  Length of data to be sent.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void uart_demo(void)
+ * {
+ *     uint8_t data[] = "UART demo";
+ *     UART_SendHalfWordData(UART0, data, sizeof(data));
+ * }
+ * \endcode
+ */
+void UART_SendHalfWordData(UART_TypeDef *UARTx, const uint16_t *inBuf, uint16_t Count);
+#endif
+
+#if UART_SUPPORT_TXDATA_API
+/**
+ * \brief   Tx data.
+ *
+ * \param[in] UARTx  Select the UART peripheral. Refer to \ref UART_Declaration.
+ * \param[in] inBuf  Buffer of data to be sent.
+ * \param[in] count  Length of data to be sent.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void uart_demo(void)
+ * {
+ *     uint8_t data[] = "UART demo";
+ *     UART_TxData(UART0, data, sizeof(data));
+ * }
+ * \endcode
+ */
+void UART_TxData(UART_TypeDef *UARTx, const uint8_t *inBuf, uint16_t count);
+#endif
+
+/**
+ * \brief   Receive data from RX FIFO.
+ *
+ * \param[in]  UARTx   Select the UART peripheral. Refer to \ref UART_Declaration.
+ * \param[out] outBuf  Buffer to store data which read from RX FIFO.
+ * \param[in]  count   Length of data to read.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void uart_demo(void)
+ * {
+ *     uint8_t data[32] = {10};
+ *     UART_ReceiveData(UART0, data, 10);
+ * }
+ * \endcode
+ */
+void UART_ReceiveData(UART_TypeDef *UARTx, uint8_t *outBuf, uint16_t count);
+
+#if UART_SUPPORT_HALF_WORD
+/**
+ * \brief   Receive half word data from RX FIFO.
+ *
+ * \param[in]  UARTx   Select the UART peripheral. Refer to \ref UART_Declaration.
+ * \param[out] outBuf  Buffer to store data which read from RX FIFO.
+ * \param[in]  count   Length of data to read.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void uart_demo(void)
+ * {
+ *     uint8_t data[32] = {10};
+ *     UART_ReceiveData(UART0, data, 10);
+ * }
+ * \endcode
+ */
+void UART_ReceiveHalfWordData(UART_TypeDef *UARTx, uint16_t *outBuf, uint16_t count);
+#endif
+
+/**
+ * \brief   Set UART communication baudrate.
+ *
+ * \param[in]  UARTx     Select the UART peripheral. Refer to \ref UART_Declaration.
+ * \param[in]  div       Parameter of the selected UART baudrate.
+ * \param[in]  ovsr      Parameter of the selected UART baudrate.
+ * \param[in]  ovsr_adj  Parameter of the selected UART baudrate.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * UART BaudRate Table: Baud rate set value for different data length (clock source 40MHz only)
+ *  9 bits data length: start bit + 7 data bit + stop bit
+ * 10 bits data length: start bit + 8 data bit + stop bit
+ * 11 bits data length: start bit + 8 data bit + parity bit + stop bit
+ * 12 bits data length: start bit + 8 data bit + parity bit + stop bit+ 2nd Stop bit
+    baudrate |       9 bits data length      |       10 bits data length     |      11 bits data length      |      12 bits data length      |
+             |  ovsr  |  ovsr_adj  |  div    |  ovsr  |  ovsr_adj  |  div    |  ovsr  |  ovsr_adj  |  div    |  ovsr  |  ovsr_adj  |  div    |
+   --------------------------------------------------------------------------------------------------------------------------------------------
+   1200      |   0x5      0x16D      0xC35   |   0x9      0x112      0x91B   |   0x9      0x70       0x91B   |   0x9      0x71       0x91B   |
+   4800      |   0x0      0x0        0x682   |   0x0      0x0        0x682   |   0xB      0x6DD      0x1F3   |   0xB      0x6D5      0x1F3   |
+   7200      |   0x0      0x0        0x457   |   0x0      0x0        0x457   |   0xC      0x84       0x143   |   0xC      0x84       0x143   |
+   9600      |   0x0      0x0        0x341   |   0x0      0x0        0x341   |   0x7      0x7EF      0x143   |   0x7      0x7EF      0x143   |
+   14400     |   0x6      0x10       0xFA    |   0x9      0x10       0xC5    |   0x9      0x10       0xC5    |   0x9      0x10       0xC5    |
+   19200     |   0x2      0x3        0x120   |   0x1      0x3        0x150   |   0x8      0x77B      0x97    |   0x8      0x77B      0x97    |
+   28800     |   0x2      0x3        0xC0    |   0x1      0x3        0xE0    |   0x6      0x84       0x7C    |   0x6      0x84       0x7C    |
+   38400     |   0x2      0x3        0x90    |   0x1      0x3        0xA8    |   0xE      0x122      0x36    |   0xE      0x122      0x36    |
+   57600     |   0x2      0x3        0x60    |   0x1      0x3        0x70    |   0x6      0x84       0x3E    |   0x6      0x84       0x3E    |
+   76800     |   0x2      0x3        0x48    |   0x1      0x3        0x54    |   0xE      0x122      0x1B    |   0xE      0x122      0x1B    |
+   115200    |   0x2      0x3        0x30    |   0x1      0x3        0x38    |   0x6      0x84       0x1F    |   0x6      0x84       0x1F    |
+   230400    |   0x2      0x3        0x18    |   0x1      0x3        0x1C    |   0xE      0x122      0x9     |   0xE      0x122      0x9     |
+   460800    |   0x2      0x3        0xC     |   0x1      0x3        0xE     |   0x7      0x14A      0x7     |   0x7      0x15A      0x7     |
+   500000    |   0x5      0x0        0x8     |   0x5      0x0        0x8     |   0x5      0x0        0x8     |   0x5      0x0        0x8     |
+   921600    |   0x2      0x3        0x6     |   0x1      0x3        0x7     |   0x9      0x2AA      0x3     |   0x9      0x2AB      0x3     |
+   1000000   |   0x0      0x0        0x8     |   0x0      0x0        0x8     |   0x5      0x0        0x4     |   0x5      0x0        0x4     |
+   1382400   |   0x9      0xAA       0x2     |   0x9      0x2AA      0x2     |   0x9      0x2AA      0x2     |   0x9      0x2AB      0x2     |
+   1444400   |   0x8      0x1F7      0x2     |   0x8      0x3F7      0x2     |   0x8      0x3F7      0x2     |   0x8      0x3FF      0x2     |
+   1500000   |   0x8      0x92       0x2     |   0x8      0x92       0x2     |   0x8      0x492      0x2     |   0x8      0x490      0x2     |
+   1843200   |   0x5      0x1F7      0x2     |   0x5      0x3F7      0x2     |   0x5      0x3F7      0x2     |   0x5      0x3FF      0x2     |
+   2000000   |   0x0      0x0        0x4     |   0x0      0x0        0x4     |   0x5      0x0        0x2     |   0x5      0x0        0x2     |
+   3000000   |   0x8      0x92       0x1     |   0x8      0x92       0x1     |   0x8      0x492      0x1     |   0x8      0x490      0x1     |
+   4000000   |   0x5      0x0        0x1     |   0x5      0x0        0x1     |   0x5      0x0        0x1     |   0x5      0x0        0x1     |
+   ---------------------------------------------------------------------------------------------------------------------------------------------
+ *
+ * void uart_demo(void)
+ * {
+ *     uint16_t div = 20;
+ *     uint16_t ovsr = 12;
+ *     uint16_t ovsr_adj = 0x252;
+ *     UART_SetBaudRate(UART0, div, ovsr, ovsr_adj);
+ * }
+ *
+ * \endcode
+ */
+void UART_SetBaudRate(UART_TypeDef *UARTx, uint16_t div, uint16_t ovsr, uint16_t ovsr_adj);
+
+/**
+ * \brief   Set UART communication parameters.
+ *
+ * \param[in] UARTx     Select the UART peripheral. Refer to \ref UART_Declaration.
+ * \param[in] wordLen   Data width of the selected UART peripheral.
+ *                      This parameter can be one of the following values:
+ *                      \arg UART_WORD_LENGTH_7BIT: 7-bit data length.
+ *                      \arg UART_WORD_LENGTH_8BIT: 8-bit data length.
+ * \param[in] parity    Parity of the selected UART peripheral.
+ *                      This parameter can be one of the following values:
+ *                      \arg UART_STOP_BITS_1: 1-bit stop bit.
+ *                      \arg UART_STOP_BITS_2: 2-bit stop bit.
+ * \param[in] stopBits  Stop bit of the selected UART peripheral.
+ *                      This parameter can be one of the following values:
+ *                      - UART_PARITY_NO_PARTY: No parity.
+ *                      - UART_PARITY_ODD: Odd parity.
+ *                      - UART_PARITY_EVEN: Even parity.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void uart_demo(void)
+ * {
+ *     uint16_t word_len = UART_WORD_LENGTH_8BIT;
+ *     uint16_t parity = UART_PARITY_NO_PARTY;
+ *     uint16_t stop_bits = UART_STOP_BITS_1;
+ *     UART_SetParams(UART0, wordLen, parity, stopBits);
+ * }
+ * \endcode
+ */
+void UART_SetParams(UART_TypeDef *UARTx, uint16_t wordLen, uint16_t parity, uint16_t stopBits);
+
+/**
+ * \brief   Config UART loopback function.
+ *
+ * \param[in] UARTx     Select the UART peripheral. Refer to \ref UART_Declaration.
+ * \param[in] NewState  Enable or disable UART loopback function.
+ *                      This parameter can be one of the following values:
+ *                      - ENABLE: Enable the specified UART loopback function.
+ *                      - DISABLE: Disable the specified UART loopback function.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void uart_demo(void)
+ * {
+ *     UART_LoopBackCmd(UART0, ENABLE);
+ * }
+ * \endcode
+ */
+void UART_LoopBackCmd(UART_TypeDef *UARTx, FunctionalState NewState);
+
+/**
+ * \brief  Check whether the specified UART flag is set.
+ *
+ * \param[in] UARTx      Select the UART peripheral. Refer to \ref UART_Declaration.
+ * \param[in] UART_FLAG  Specify UART flag to check.
+ *                       This parameter can be one of the following values, refer to \ref UART_Flag.
+ *                       \arg UART_FLAG_RX_DATA_AVA: Rx data is avaliable.
+ *                       \arg UART_FLAG_RX_OVERRUN: Rx FIFO overrun.
+ *                       \arg UART_FLAG_RX_PARITY_ERR: Rx parity error.
+ *                       \arg UART_FLAG_RX_FRAME_ERR: Rx frame error.
+ *                       \arg UART_FLAG_RX_BREAK_ERR: Rx break error.
+ *                       \arg UART_FLAG_TX_FIFO_EMPTY: Tx Holding Register or Tx FIFO empty
+ *                       \arg UART_FLAG_TX_EMPTY: Tx FIFO and Tx shift register are both empty.
+ *                       \arg UART_FLAG_RX_FIFO_ERR: Rx FIFO error.
+ *                       \arg UART_FLAG_RX_IDLE: Rx idle.
+ *                       \arg UART_FLAG_TX_DONE: Tx waveform done & TX_FIFO_EMPTY = 1.
+ *                       \arg UART_FLAG_TX_THD: TX_FIFO_LEVEL<=txfifo_trigger_level.
+ *
+ * \return New status of UART flag.
+ *         - SET: The specified UART flag bit is set.
+ *         - RESET: The specified flag is not set.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void uart_senddata_continuous(UART_TypeDef *UARTx, const uint8_t *pSend_Buf, uint16_t vCount)
+ * {
+ *     uint8_t count;
+ *
+ *     while (vCount / UART_TX_FIFO_SIZE > 0)
+ *     {
+ *         while (UART_GetFlagStatus(UARTx, UART_FLAG_TX_FIFO_EMPTY) == 0);
+ *         for (count = UART_TX_FIFO_SIZE; count > 0; count--)
+ *         {
+ *             UARTx->UART_RBR_THR = *pSend_Buf++;
+ *         }
+ *         vCount -= UART_TX_FIFO_SIZE;
+ *     }
+ *
+ *     while (UART_GetFlagStatus(UARTx, UART_FLAG_TX_FIFO_EMPTY) == 0);
+ *     while (vCount--)
+ *     {
+ *         UARTx->UART_RBR_THR = *pSend_Buf++;
+ *     }
+ * }
+ * \endcode
+ */
+FlagStatus UART_GetFlagStatus(UART_TypeDef *UARTx, uint32_t UART_FLAG);
+
+/**
+ * \brief  Get the specified UART line status.
+ *
+ * \param[in] UARTx  Select the UART peripheral. Refer to \ref UART_Declaration.
+ *
+ * \return Line status.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * uint32_t line_status = UART_GetLineStatus(UART_DEMO);
+ *
+ * if (line_status & UART_FLAG)
+ * {
+ *     //Add user code here.
+ * }
+ *
+ * \endcode
+ */
+uint8_t UART_GetLineStatus(UART_TypeDef *UARTx);
+
+/**
+ * \brief   Send one byte of data.
+ *
+ * \param[in] UARTx  Select the UART peripheral. Refer to \ref UART_Declaration.
+ * \param[in] data   Byte data to send.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void uart_demo(void)
+ * {
+ *     uint8_t data = 0x55;
+ *     UART_SendByte(UART0, data);
+ * }
+ * \endcode
+ */
+void UART_SendByte(UART_TypeDef *UARTx, uint8_t data);
+
+#if UART_SUPPORT_HALF_WORD
+/**
+ * \brief   Send half word of data.
+ *
+ * \param[in] UARTx  Select the UART peripheral. Refer to \ref UART_Declaration.
+ * \param[in] data   Byte data to send.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void uart_demo(void)
+ * {
+ *     uint8_t data = 0x55;
+ *     UART_SendByte(UART0, data);
+ * }
+ * \endcode
+ */
+void UART_SendHalfWord(UART_TypeDef *UARTx, uint16_t data);
+#endif
+
+/**
+ * \brief   Read a byte of data from UART RX FIFO.
+ *
+ * \param[in] UARTx  Select the UART peripheral. Refer to \ref UART_Declaration.
+ *
+ * \return  Which byte data has been read.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void uart_demo(void)
+ * {
+ *     uint8_t data = UART_ReceiveByte(UART0);
+ *
+ * }
+ * \endcode
+ */
+uint8_t UART_ReceiveByte(UART_TypeDef *UARTx);
+
+#if UART_SUPPORT_HALF_WORD
+/**
+ * \brief   Read a byte of data from UART RX FIFO.
+ *
+ * \param[in] UARTx  Select the UART peripheral. Refer to \ref UART_Declaration.
+ *
+ * \return  Which byte data has been read.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void uart_demo(void)
+ * {
+ *     uint8_t data = UART_ReceiveByte(UART0);
+ *
+ * }
+ * \endcode
+ */
+uint8_t UART_ReceiveHalfWord(UART_TypeDef *UARTx);
+#endif
+
+/**
+ * \brief   Get the interrupt identifier of the selected UART peripheral.
+ *
+ * \param[in] UARTx  Select the UART peripheral. Refer to \ref UART_Declaration.
+ *
+ * \return The interrupt identifier value.
+ *         This return value can be one or a combination of the following:
+ *         - UART_INT_ID_LINE_STATUS: Rx line status interrupt ID.
+ *         - UART_INT_ID_RX_LEVEL_REACH: Rx data available or trigger level reached interrupt ID.
+ *         - UART_INT_ID_RX_TIMEOUT: Rx FIFO data timeout interrupt ID.
+ *         - UART_INT_ID_TX_FIFO_EMPTY: Tx FIFO empty interrupt ID.
+ *         - UART_INT_ID_MODEM_STATUS: Modem status interrupt ID.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void UART0_Handler()
+ * {
+ *     uint16_t rx_len = 0;
+ *     uint8_t uart_rev_data[32];
+ *
+ *     //Get interrupt ID.
+ *     uint32_t int_status = UART_GetIID(UART0);
+ *
+ *     //Disable interrupt.
+ *     UART_INTConfig(UART0, UART_INT_RD_AVA, DISABLE);
+ *
+ *     if (UART_GetFlagStatus(UART0, UART_FLAG_RX_IDLE) == SET)
+ *     {
+ *         UART_INTConfig(UART0, UART_INT_RX_IDLE, DISABLE);
+ *         //Add user code here.
+ *         UART_ClearRxFIFO(UART0);
+ *         UART_INTConfig(UART0, UART_INT_RX_IDLE, ENABLE);
+ *     }
+ *
+ * }
+ * \endcode
+ */
+uint16_t UART_GetIID(UART_TypeDef *UARTx);
+
+#if UART_SUPPORT_CLEAR_TX_FIFO
+/**
+ * \brief   Clear Tx FIFO of the selected UART peripheral.
+ *
+ * \param[in] UARTx  Select the UART peripheral. Refer to \ref UART_Declaration.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void uart_demo(void)
+ * {
+ *     UART_ClearTxFIFO(UART0);
+ * }
+ * \endcode
+ */
+void UART_ClearTxFIFO(UART_TypeDef *UARTx);
+#endif
+
+/**
+ * \brief   Clear Rx FIFO of the selected UART peripheral.
+ *
+ * \param[in] UARTx  Select the UART peripheral. Refer to \ref UART_Declaration.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void uart_demo(void)
+ * {
+ *     UART_ClearRxFIFO(UART0);
+ * }
+ * \endcode
+ */
+void UART_ClearRxFIFO(UART_TypeDef *UARTx);
+
+/**
+ * \brief   Get the data length in Tx FIFO of the selected UART peripheral.
+ *
+ * \param[in] UARTx  Select the UART peripheral. Refer to \ref UART_Declaration.
+ *
+ * \return  Data length in UART TX FIFO.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void uart_demo(void)
+ * {
+ *     uint8_t data_len = UART_GetTxFIFODataLen(UART0);
+ * }
+ * \endcode
+ */
+uint8_t UART_GetTxFIFODataLen(UART_TypeDef *UARTx);
+
+/**
+ * \brief   Get the data length in Rx FIFO of the selected UART peripheral.
+ *
+ * \param[in] UARTx  Select the UART peripheral. Refer to \ref UART_Declaration.
+ *
+ * \return  Data length in UART RX FIFO.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void uart_demo(void)
+ * {
+ *     uint8_t data_len = UART_GetRxFIFODataLen(UART0);
+ * }
+ * \endcode
+ */
+uint8_t UART_GetRxFIFODataLen(UART_TypeDef *UARTx);
+
+/**
+ * \brief    Enable/Disable DMA mode on UART side.
+ *
+ * \param[in] UARTx     Select the UART peripheral. Refer to \ref UART_Declaration.
+ * \param[in] NewState  Enable or disable UART DMA mode.
+ *                      This parameter can be one of the following values:
+ *                      - true: Enable UART DMA mode.
+ *                      - false: Disable UART DMA mode.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * void driver_uart_init(void)
+ * {
+ *     UART_TxDmaCmd(UART_DEMO, false);
+ * }
+ * \endcode
+ */
+void UART_TxDmaCmd(UART_TypeDef *UARTx, FunctionalState NewState);
+
+/**
+ * \brief    Enable/Disable DMA mode on UART side.
+ *
+ * \param[in] UARTx     Select the UART peripheral. Refer to \ref UART_Declaration.
+ * \param[in] NewState  Enable or disable UART DMA mode.
+ *                      This parameter can be one of the following values:
+ *                      - true: Enable UART DMA mode.
+ *                      - false: Disable UART DMA mode.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * void driver_uart_init(void)
+ * {
+ *     UART_RxDmaCmd(UART_DEMO, false);
+ * }
+ * \endcode
+ */
+void UART_RxDmaCmd(UART_TypeDef *UARTx, FunctionalState NewState);
+
+/**
+ * \brief   UART one wire config.
+ *
+ * \param[in] UARTx     Select the UART peripheral. Refer to \ref UART_Declaration.
+ * \param[in] NewState  UART one wire config is set or not.
+ *                      This parameter can be one of the following values:
+ *                      - true: UART one wire config is set.
+ *                      - false: UART one wire config is unset.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * void uart_demo(void)
+ * {
+ *     UART_OneWireConfig(UART0, true);
+ * }
+ * \endcode
+ */
+void UART_OneWireConfig(UART_TypeDef *UARTx, FunctionalState NewState);
+
+/**
+ * \brief  UART clock divider config.
+ *
+ * \param[in] UARTx     Select the UART peripheral. Refer to \ref UART_Declaration.
+ * \param[in] ClockDiv  Specify the UART clock divider.
+ *                      This parameter can refer to \ref UART_Clock_Divider.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void driver_i2c_init(void)
+ * {
+ *     RCC_UARTClkDivConfig(UART0, UART_CLOCK_DIVIDER_1);
+ * }
+ * \endcode
+ */
+void UART_ClkDivConfig(UART_TypeDef *UARTx, UARTClockDiv_TypeDef ClockDiv);
+
+/**
+ * \brief  Get UART clock divider config.
+ *
+ * \param[in]  UARTx     Select the UART peripheral. Refer to \ref UART_Declaration.
+ * \param[out] ClockSrc  Specify the UART clock source.
+ * \param[out] ClockDiv  Specify the UART clock divider.
+ *                       This parameter can refer to \ref UART_Clock_Divider.
+ *
+ * \return The status of get clock.
+ */
+bool UART_ClkGet(UART_TypeDef *UARTx, UARTClockSrc_TypeDef *ClockSrc,
+                 UARTClockDiv_TypeDef *ClockDiv);
+
+#if (UART_SUPPORT_RAP_FUNCTION == 1)
+
+void UART_RAPQactiveCtrl(UART_TypeDef *UARTx, uint32_t Qactive, FunctionalState NewState);
+
+#endif
+
+/** End of UART_Exported_Functions
+  * \}
+  */
+
+/** End of UART
+  * \}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RTL_UART_H */
+
+
diff --git a/bee/drivers/uart/src/device/rtl87x2g/rtl_uart_def.h b/bee/drivers/uart/src/device/rtl87x2g/rtl_uart_def.h
new file mode 100644
index 00000000..c19c5271
--- /dev/null
+++ b/bee/drivers/uart/src/device/rtl87x2g/rtl_uart_def.h
@@ -0,0 +1,749 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef RTL_UART_DEF_H
+#define RTL_UART_DEF_H
+
+#include "utils/rtl_utils.h"
+#include "address_map.h"
+
+#ifdef  __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+
+/*============================================================================*
+ *                          UART Defines
+ *============================================================================*/
+/** \defgroup UART        UART
+  * \brief
+  * \{
+  */
+
+/** \defgroup UART_Exported_Constants UART Exported Constants
+  * \brief
+  * \{
+  */
+
+/**
+ * \defgroup UART_Defines UART Defines
+ * \{
+ * \ingroup  UART_Exported_Constants
+ */
+#define UART_SUPPORT_TX_DONE                (1)    //!< The chip supports TX done interrupt.
+#define UART_SUPPORT_TX_THD                 (1)    //!< The chip supports TX threshold interrupt.
+#define UART_SUPPORT_TXDATA_API             (0)    //!< The function is not supported.
+#define UART_SUPPORT_HALF_WORD              (0)    //!< The function is not supported.
+#define UART_SUPPORT_CLEAR_TX_FIFO          (0)    //!< The function is not supported.
+
+/** End of UART_Defines
+  * \}
+  */
+
+/** End of UART_Exported_Constants
+  * \}
+  */
+
+/** End of UART
+  * \}
+  */
+
+/*============================================================================*
+ *                         UART Registers Memory Map
+ *============================================================================*/
+typedef struct
+{
+    __IO uint32_t UART_DLL;                  /*!< 0x00 */
+    __IO uint32_t UART_DLM_IER;              /*!< 0x04 */
+    __IO uint32_t UART_IIR_FCR;              /*!< 0x08 */
+    __IO uint32_t UART_LCR;                  /*!< 0x0C */
+    __IO uint32_t UART_CTRL0;                /*!< 0x10 */
+    __I  uint32_t UART_LSR;                  /*!< 0x14 */
+    __IO uint32_t UART_RSVD0;                /*!< 0x18 */
+    __IO uint32_t UART_SCR;                  /*!< 0x1C */
+    __IO uint32_t UART_STSR;                 /*!< 0x20 */
+    __IO uint32_t UART_RBR_THR;              /*!< 0x24 */
+    __IO uint32_t UART_MISCR;                /*!< 0x28 */
+    __IO uint32_t UART_RSVD1[5];             /*!< 0x2C - 0x3C */
+    __IO uint32_t UART_RX_TIMEOUT;           /*!< 0x40 */
+    __IO uint32_t UART_RX_TIMEOUT_STS;       /*!< 0x44 */
+    __IO uint32_t UART_RX_TIMEOUT_EN;        /*!< 0x48 */
+    __I  uint32_t UART_RXTX_FIFO_WL;         /*!< 0x4C */
+    __IO uint32_t UART_INT_MASK;             /*!< 0x50 */
+    __I  uint32_t UART_TXDONE_INT;           /*!< 0x54 */
+    __I  uint32_t UART_TX_THD_INT;           /*!< 0x58 */
+    __IO uint32_t UART_RSVD2;                /*!< 0x5C */
+} UART_TypeDef;
+
+/*============================================================================*
+ *                         UART Declaration
+ *============================================================================*/
+/** \defgroup UART        UART
+  * \brief
+  * \{
+  */
+
+/** \defgroup UART_Exported_Constants UART Exported Constants
+  * \brief
+  * \{
+  */
+
+/** \defgroup UART_Declaration UART Declaration
+  * \{
+  * \ingroup  UART_Exported_Constants
+  */
+
+#define UART0                   ((UART_TypeDef *) UART0_REG_BASE)   //!< UART0 base address.
+#define UART1                   ((UART_TypeDef *) UART1_REG_BASE)   //!< UART1 base address.
+#define UART2                   ((UART_TypeDef *) UART2_REG_BASE)   //!< UART2 base address.
+#define UART3                   ((UART_TypeDef *) UART3_REG_BASE)   //!< UART3 base address.
+#define UART4                   ((UART_TypeDef *) UART4_REG_BASE)   //!< UART4 base address.
+#define UART5                   ((UART_TypeDef *) UART5_REG_BASE)   //!< UART5 base address.
+#define UART                    UART0                               //!< The macro is a wrapper for UART0.
+
+#define IS_UART_PERIPH(PERIPH)  (((PERIPH) == UART0) || \
+                                 ((PERIPH) == UART1) || \
+                                 ((PERIPH) == UART2) || \
+                                 ((PERIPH) == UART3) || \
+                                 ((PERIPH) == UART4) || \
+                                 ((PERIPH) == UART5)) //!< Check if the input parameter is valid.
+
+#define UART_TX_FIFO_ADDR(UARTx)    (uint32_t)(&(((UART_TypeDef *)(UARTx))->UART_RBR_THR))
+#define UART_RX_FIFO_ADDR(UARTx)    (uint32_t)(&(((UART_TypeDef *)(UARTx))->UART_RBR_THR))
+
+/** End of UART_Declaration
+  * \}
+  */
+
+/** End of UART_Exported_Constants
+  * \}
+  */
+
+/** End of UART
+  * \}
+  */
+
+/*============================================================================*
+ *                         UART Private Types
+ *============================================================================*/
+typedef struct
+{
+    uint32_t uart_reg[13];
+} UARTStoreReg_Typedef;
+
+/*============================================================================*
+ *                         UART Registers and Field Descriptions
+ *============================================================================*/
+/* 0x00
+   7:0     R/W    dll                                 8'h0
+   31:8    R      reserved1                           24'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t dll: 8;
+        const uint32_t reserved_0: 24;
+    } b;
+} UART_DLL_TypeDef;
+
+
+
+/* 0x04
+   7:0     R/W    dlm                                 8'h0
+   31:8    R      reserved2                           24'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t dlm: 8;
+        const uint32_t reserved_0: 24;
+    } b;
+} UART_DLM_TypeDef;
+
+
+
+/* 0x04
+   0       R/W    erbi                                1'h0
+   1       R/W    etbei                               1'h0
+   2       R/W    elsi                                1'h0
+   3       R/W    uart_DUMMY_000                      1'h0
+   4       R/W    tx_empty_stop_int_en                1'h0
+   5       R/W    tx_fifo_th_int_en                   1'h0
+   31:6    R      reserved3                           26'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t erbi: 1;
+        uint32_t etbei: 1;
+        uint32_t elsi: 1;
+        uint32_t uart_DUMMY_000: 1;
+        uint32_t tx_empty_stop_int_en: 1;
+        uint32_t tx_fifo_th_int_en: 1;
+        const uint32_t reserved_0: 26;
+    } b;
+} UART_IER_TypeDef;
+
+
+
+/* 0x08
+   0       R      int_pend                            1'h1
+   3:1     R      int_id                              3'h0
+   31:4    R      reserved4                           28'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        const uint32_t int_pend: 1;
+        const uint32_t int_id: 3;
+        const uint32_t reserved_0: 28;
+    } b;
+} UART_IIR_TypeDef;
+
+
+
+/* 0x08
+   0       W      rxfifo_error_en                     1'h1
+   1       W1C    clear_rxfifo                        1'h0
+   2       W1C    clear_txfifo                        1'h0
+   3       W      dma_mode                            1'h0
+   7:4     R      reserved7                           4'h0
+   12:8    W      rxfifo_trigger_level                5'he
+   15:13   R      reserved6                           3'h0
+   20:16   W      tx_fifo_th                          5'h0
+   31:21   R      reserved5                           11'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t rxfifo_error_en: 1;
+        uint32_t clear_rxfifo: 1;
+        uint32_t clear_txfifo: 1;
+        uint32_t dma_mode: 1;
+        const uint32_t reserved_2: 4;
+        uint32_t rxfifo_trigger_level: 5;
+        const uint32_t reserved_1: 3;
+        uint32_t tx_fifo_th: 5;
+        const uint32_t reserved_0: 11;
+    } b;
+} UART_FCR_TypeDef;
+
+
+
+/* 0x0C
+   0       R/W    wls0                                1'h1
+   1       R      reserved9                           1'h1
+   2       R/W    stb                                 1'h0
+   3       R/W    parity_en                           1'h0
+   4       R/W    even_parity_sel                     1'h0
+   5       R/W    stick_parity                        1'h0
+   6       R/W    break_ctrl                          1'h0
+   7       R/W    dlab                                1'h0
+   31:8    R      reserved8                           24'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t wls0: 1;
+        const uint32_t reserved_1: 1;
+        uint32_t stb: 1;
+        uint32_t parity_sel: 2;
+        uint32_t stick_parity: 1;
+        uint32_t break_ctrl: 1;
+        uint32_t dlab: 1;
+        const uint32_t reserved_0: 24;
+    } b;
+} UART_LCR_TypeDef;
+
+
+
+/* 0x10
+   0       R/W    uart_DUMMY_002                      1'h0
+   1       R/W    rts                                 1'h0
+   3:2     R/W    uart_DUMMY_001                      2'h0
+   4       R/W    loopback_en                         1'h0
+   5       R/W    autoflow_en                         1'h0
+   31:6    R      reserved10                          26'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t uart_DUMMY_002: 1;
+        uint32_t rts: 1;
+        uint32_t uart_DUMMY_001: 2;
+        uint32_t loopback_en: 1;
+        uint32_t autoflow_en: 1;
+        const uint32_t reserved_0: 26;
+    } b;
+} UART_CTRL0_TypeDef;
+
+
+
+/* 0x14
+   0       R      rxfifo_datardy                      1'h0
+   1       R      overrun_err                         1'h0
+   2       R      parity_err                          1'h0
+   3       R      framing_err                         1'h0
+   4       R      break_err_int                       1'h0
+   5       R      tx_fifo_empty_indicator             1'h1
+   6       R      tx_empty                            1'h1
+   7       R      rxfifo_err                          1'h0
+   31:8    R      reserved11                          24'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        const uint32_t rxfifo_datardy: 1;
+        const uint32_t overrun_err: 1;
+        const uint32_t parity_err: 1;
+        const uint32_t framing_err: 1;
+        const uint32_t break_err_int: 1;
+        const uint32_t tx_fifo_empty_indicator: 1;
+        const uint32_t tx_empty: 1;
+        const uint32_t rxfifo_err: 1;
+        const uint32_t reserved_0: 24;
+    } b;
+} UART_LSR_TypeDef;
+
+
+
+/* 0x1C
+   2:0     R      reserved16                          3'h0
+   3       R/W    Pin_lb_test                         1'h0
+   5:4     R/W    uart_DUMMY_003                      2'h0
+   6       R/W    rxbreaksignalinterruptenable        1'h0
+   7       R/W1C  rxbreaksignalinterruptstatus        1'h0
+   11:8    R/W    Dbg_sel[3:0]                        4'h0
+   15:12   R      reserved15                          4'h0
+   26:16   R/W    xfactor_adj[10:0]                   11'h0
+   31:27   R      reserved14                          5'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        const uint32_t reserved_2: 3;
+        uint32_t Pin_lb_test: 1;
+        uint32_t uart_DUMMY_003: 2;
+        uint32_t rx_break_signal_interrupt_enable: 1;
+        uint32_t rx_break_signal_interrupt_status: 1;
+        uint32_t Dbg_sel: 4;
+        const uint32_t reserved_1: 4;
+        uint32_t xfactor_adj: 11;
+        const uint32_t reserved_0: 5;
+    } b;
+} UART_SCR_TypeDef;
+
+
+
+/* 0x20
+   2:0     R      reserved19                          3'h0
+   3       R/W    reset_rcv                           1'h0
+   7:4     R/W    xfactor                             4'hb
+   18:8    R      reserved18                          11'h0
+   23:19   R      tx_fifo_th                          5'h0
+   24      R      dma_mode                            1'h0
+   25      R      rxfifo_error_en                     1'h1
+   30:26   R      rxfifo_trigger_level                5'he
+   31      R      reserved17                          1'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        const uint32_t reserved_2: 3;
+        uint32_t reset_rcv: 1;
+        uint32_t xfactor: 4;
+        const uint32_t reserved_1: 11;
+        const uint32_t tx_fifo_th: 5;
+        const uint32_t dma_mode: 1;
+        const uint32_t rxfifo_error_en: 1;
+        const uint32_t rxfifo_trigger_level: 5;
+        const uint32_t reserved_0: 1;
+    } b;
+} UART_STSR_TypeDef;
+
+
+/* 0x24
+   7:0     W      rx_data                             8'h0
+   31:8    R      reserved21                          24'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        const uint32_t rx_data: 8;
+        const uint32_t reserved_0: 24;
+    } b;
+} UART_RBR_TypeDef;
+
+
+
+/* 0x24
+   7:0     W      tx_data                             8'h0
+   31:8    R      reserved21                          24'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t tx_data: 8;
+        const uint32_t reserved_0: 24;
+    } b;
+} UART_THR_TypeDef;
+
+
+
+/* 0x28
+   0       R/W    uart_DUMMY_005                      1'h0
+   1       R/W    txdma_en                            1'h0
+   2       R/W    rxdma_en                            1'h0
+   7:3     R/W    txdma_burstsize                     5'h0
+   13:8    R/W    rxdma_burstsize                     6'h0
+   15:14   R/W    uart_DUMMY_004                      2'h0
+   31:16   R      reserved22                          16'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t uart_DUMMY_005: 1;
+        uint32_t txdma_en: 1;
+        uint32_t rxdma_en: 1;
+        uint32_t txdma_burstsize: 5;
+        uint32_t rxdma_burstsize: 6;
+        uint32_t uart_DUMMY_004: 2;
+        const uint32_t reserved_0: 16;
+    } b;
+} UART_MISCR_TypeDef;
+
+
+
+/* 0x40
+   3:0     R/W    rxidle_timeout_value                4'h0
+   30:4    R      reserved23                          27'h0
+   31      R/W    rxidle_timeourt_en                  1'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t rxidle_timeout_value: 4;
+        const uint32_t reserved_0: 27;
+        uint32_t rxidle_timeourt_en: 1;
+    } b;
+} UART_RX_TIMEOUT_TypeDef;
+
+
+
+/* 0x44
+   0       R/W1C  rxidle_timeout_int_sts              1'h0
+   31:1    R      reserved24                          31'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t rxidle_timeout_int_sts: 1;
+        const uint32_t reserved_0: 31;
+    } b;
+} UART_RX_TIMEOUT_STS_TypeDef;
+
+
+
+/* 0x48
+   0       R/W    rxidle_timeout_int_en               1'h0
+   31:1    R      reserved25                          31'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t rxidle_timeout_int_en: 1;
+        const uint32_t reserved_0: 31;
+    } b;
+} UART_RX_TIMEOUT_EN_TypeDef;
+
+
+
+/* 0x4C
+   4:0     R      tx_fifo_level                       5'h0
+   7:5     R      reserved27                          3'h0
+   13:8    R      rx_fifo_level                       6'h0
+   31:14   R      reserved26                          18'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        const uint32_t tx_fifo_level: 5;
+        const uint32_t reserved_1: 3;
+        const uint32_t rx_fifo_level: 6;
+        const uint32_t reserved_0: 18;
+    } b;
+} UART_RXTX_FIFO_WL_TypeDef;
+
+
+
+/* 0x50
+   0       R/W    rd_ava_int_mask                     1'h0
+   1       R/W    txfifo_empty_int_mask               1'h0
+   2       R/W    rx_line_sts_int_mask                1'h0
+   3       R/W    modem_sts_int_mask                  1'h0
+   4       R/W    rx_break_int_mask                   1'h0
+   5       R/W    rxidle_timeout_int_mask             1'h0
+   6       R/W    txdone_int_mask                     1'h0
+   7       R/W    tx_thd_int_mask                     1'h0
+   31:8    R      reserved28                          24'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        uint32_t rd_ava_int_mask: 1;
+        uint32_t txfifo_empty_int_mask: 1;
+        uint32_t rx_line_sts_int_mask: 1;
+        uint32_t modem_sts_int_mask: 1;
+        uint32_t rx_break_int_mask: 1;
+        uint32_t rxidle_timeout_int_mask: 1;
+        uint32_t txdone_int_mask: 1;
+        uint32_t tx_thd_int_mask: 1;
+        const uint32_t reserved_0: 24;
+    } b;
+} UART_INT_MASK_TypeDef;
+
+
+
+/* 0x54
+   0       R      tx_empty_stop_rdy                   1'h0
+   31:1    R      reserved29                          31'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        const uint32_t tx_empty_stop_rdy: 1;
+        const uint32_t reserved_0: 31;
+    } b;
+} UART_TXDONE_INT_TypeDef;
+
+
+
+/* 0x58
+   0       R      int_tx_fifo                         1'h0
+   31:1    R      reserved30                          31'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    uint8_t d8[4];
+    struct
+    {
+        const uint32_t int_tx_fifo: 1;
+        const uint32_t reserved_0: 31;
+    } b;
+} UART_TX_THD_INT_TypeDef;
+
+/*============================================================================*
+ *                        UART Constants
+ *============================================================================*/
+/** \defgroup UART          UART
+  * \brief
+  * \{
+  */
+
+/** \defgroup UART_Exported_Constants UART Exported Constants
+  * \brief
+  * \{
+  */
+
+/**
+ * \defgroup    UART_Source_Clock UART Source Clock
+ * \{
+ * \ingroup     UART_Exported_Constants
+ */
+typedef enum
+{
+    UART_CLOCK_SRC_40M,    //!< The UART clock source is 40MHz.
+} UARTClockSrc_TypeDef;
+
+#define IS_UART_SRC_CLOCK(CLK) ((CLK) == UART_CLOCK_SRC_40M) //!< Check if the input parameter is valid.
+
+/** End of UART_Source_Clock
+  * \}
+  */
+
+/**
+ * \defgroup    UART_Clock_Divider UART Clock Divider
+ * \{
+ * \ingroup     UART_Exported_Constants
+ */
+typedef enum
+{
+    UART_CLOCK_DIVIDER_1 = 0x0,       //!< The clock divider is 1.
+    UART_CLOCK_DIVIDER_2 = 0x1,       //!< The clock divider is 2.
+    UART_CLOCK_DIVIDER_4 = 0x2,       //!< The clock divider is 4.
+    UART_CLOCK_DIVIDER_8 = 0x3,       //!< The clock divider is 8.
+    UART_CLOCK_DIVIDER_16 = 0x4,      //!< The clock divider is 16.
+    UART_CLOCK_DIVIDER_32 = 0x5,      //!< The clock divider is 32.
+    UART_CLOCK_DIVIDER_40 = 0x6,      //!< The clock divider is 40.
+    UART_CLOCK_DIVIDER_64 = 0x7,      //!< The clock divider is 64.
+} UARTClockDiv_TypeDef;
+
+#define IS_UART_CLK_DIV(DIV) (((DIV) == UART_CLOCK_DIVIDER_1) || \
+                              ((DIV) == UART_CLOCK_DIVIDER_2) || \
+                              ((DIV) == UART_CLOCK_DIVIDER_4) || \
+                              ((DIV) == UART_CLOCK_DIVIDER_8) || \
+                              ((DIV) == UART_CLOCK_DIVIDER_16) || \
+                              ((DIV) == UART_CLOCK_DIVIDER_32) || \
+                              ((DIV) == UART_CLOCK_DIVIDER_40) || \
+                              ((DIV) == UART_CLOCK_DIVIDER_64)) //!< Check if the input parameter is valid.
+
+/** End of UART_Clock_Divider
+  * \}
+  */
+
+/** End of UART_Exported_Constants
+  * \}
+  */
+
+/** End of UART
+  * \}
+  */
+
+/*============================================================================*
+ *                          UART TYPE/API Wrappers
+ *============================================================================*/
+/** \defgroup UART        UART
+  * \brief
+  * \{
+  */
+
+/** \defgroup UART_Exported_Constants UART Exported Constants
+  * \brief
+  * \{
+  */
+
+/**
+ * \brief       To be compatible with the previous driver.
+ * \defgroup    UART_InitStruct_Wrapper UART InitStruct Wrapper
+ * \{
+ * \ingroup     UART_Exported_Constants
+ */
+#define UART_OvsrAdj                ovsr_adj        //!< The macro is a wrapper for ovsr_adj
+#define UART_Div                    div             //!< The macro is a wrapper for div
+#define UART_Ovsr                   ovsr            //!< The macro is a wrapper for ovsr
+#define UART_WordLen                wordLen         //!< The macro is a wrapper for wordLen
+#define UART_Parity                 parity          //!< The macro is a wrapper for parity
+#define UART_StopBits               stopBits        //!< The macro is a wrapper for stopBits
+#define UART_HardwareFlowControl    autoFlowCtrl    //!< The macro is a wrapper for autoFlowCtrl
+#define UART_TxThdLevel             txTriggerLevel  //!< The macro is a wrapper for txTriggerLevel
+#define UART_RxThdLevel             rxTriggerLevel  //!< The macro is a wrapper for rxTriggerLevel
+#define UART_DmaEn                  dmaEn           //!< The macro is a wrapper for dmaEn
+#define UART_IdleTime               idle_time       //!< The macro is a wrapper for idle_time
+#define UART_TxWaterLevel           TxWaterlevel    //!< The macro is a wrapper for TxWaterlevel
+#define UART_RxWaterLevel           RxWaterlevel    //!< The macro is a wrapper for RxWaterlevel
+#define UART_TxDmaEn                TxDmaEn         //!< The macro is a wrapper for TxDmaEn
+#define UART_RxDmaEn                RxDmaEn         //!< The macro is a wrapper for RxDmaEn
+
+/** End of UART_InitStruct_Wrapper
+  * \}
+  */
+
+/**
+ * \brief       To be compatible with the previous driver.
+ * \defgroup    UART_Constant_Wrapper UART Constant Wrapper
+ * \{
+ * \ingroup     UART_Exported_Constants
+ */
+#define UART_INT_LINE_STS           UART_INT_RX_LINE_STS        //!< The macro is a wrapper for UART_INT_RX_LINE_STS
+#define UART_INT_ID_RX_TMEOUT       UART_INT_ID_RX_DATA_TIMEOUT //!< The macro is a wrapper for UART_INT_ID_RX_DATA_TIMEOUT
+#define UART_FLAG_THR_EMPTY         UART_FLAG_TX_FIFO_EMPTY     //!< The macro is a wrapper for UART_FLAG_TX_FIFO_EMPTY
+#define UART_FLAG_THR_TSR_EMPTY     UART_FLAG_TX_EMPTY          //!< The macro is a wrapper for UART_FLAG_TX_EMPTY
+#define UART_FLAG_RX_DATA_RDY       UART_FLAG_RX_DATA_AVA       //!< The macro is a wrapper for UART_FLAG_RX_DATA_AVA 
+#define UART_INT_ID_TX_EMPTY        UART_INT_ID_TX_FIFO_EMPTY   //!< The macro is a wrapper for UART_INT_ID_TX_FIFO_EMPTY
+
+/** End of UART_Constant_Wrapper
+  * \}
+  */
+
+/**
+ * \brief       To be compatible with the previous driver.
+ * \defgroup    UART_API_Wrapper UART API Wrapper
+ * \{
+ * \ingroup     UART_Exported_Constants
+ */
+#define UART_GetFlagState           UART_GetFlagStatus        //!< The macro is a wrapper for UART_GetFlagStatus
+#define UART_ChangeBaudRate         UART_SetBaudRate          //!< The macro is a wrapper for UART_SetBaudRate
+#define UART_ChangeParams           UART_SetParams            //!< The macro is a wrapper for UART_SetParams
+#define UART_ClearTxFifo            UART_ClearTxFIFO          //!< The macro is a wrapper for UART_ClearTxFIFO
+#define UART_ClearRxFifo            UART_ClearRxFIFO          //!< The macro is a wrapper for UART_ClearRxFIFO
+#define UART_GetTxFIFOLen           UART_GetTxFIFODataLen     //!< The macro is a wrapper for UART_GetTxFIFODataLen
+#define UART_GetRxFIFOLen           UART_GetRxFIFODataLen     //!< The macro is a wrapper for UART_GetRxFIFODataLen
+
+/** End of UART_API_Wrapper
+  * \}
+  */
+
+/** End of UART_Exported_Constants
+  * \}
+  */
+
+/** End of UART
+  * \}
+  */
+
+#ifdef  __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* RTL_UART_DEF_H */
diff --git a/bee/drivers/uart/src/device/rtl87x2j/rtl87x2j_uart.c b/bee/drivers/uart/src/device/rtl87x2j/rtl87x2j_uart.c
new file mode 100644
index 00000000..01250839
--- /dev/null
+++ b/bee/drivers/uart/src/device/rtl87x2j/rtl87x2j_uart.c
@@ -0,0 +1,295 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *                           Header Files
+ *============================================================================*/
+#include "rtl_uart.h"
+#include "rtl_rcc.h"
+
+/*============================================================================*
+ *                           Private Defines
+ *============================================================================*/
+#define UART_CLOCK_AUTO_MODE_CONFIG_ALWAYSRUN       (0x7E)//Force off 0x54
+#define UART_MIN_OVSR                               10
+#define UART_MAX_OVSR                               20
+#define UART_OVSR_OFFSET                            5
+
+uint32_t uart_clock_src_hz = 40000000;
+
+static const uint32_t uart_baudrate_table[] =
+{
+    1200, 4800, 7200, 9600, 14400, 19200, 28800, 38400, 57600, 76800, 115200,  128000,  153600,
+    230400, 460800, 500000, 921600, 1000000, 1382400, 1444400, 1500000, 1843200, 2000000, 3000000, 4000000
+};
+
+/*============================================================================*
+ *                           Public Functions
+ *============================================================================*/
+/**
+  * @brief  TX data to tx FIFO.
+  * @param  UARTx: selected UART peripheral.
+  * @param  data: buffer to be written to Tx FIFO.
+  * @param  len: len of data to be written.
+  * @return None
+  */
+void UART_TxData(UART_TypeDef *UARTx, const uint8_t *InBuf, uint16_t Count)
+{
+    uint32_t blkcount  = Count / UART_TX_FIFO_SIZE;
+    uint32_t remainder = Count % UART_TX_FIFO_SIZE;
+    uint32_t i = 0;
+
+    for (i = 0; i < blkcount; ++i)
+    {
+        UART_SendData(UARTx, InBuf + UART_TX_FIFO_SIZE * i, UART_TX_FIFO_SIZE);
+        /* wait tx fifo empty */
+        while (UART_GetFlagStatus(UARTx, UART_FLAG_TX_EMPTY) != SET);
+    }
+
+    /* send left bytes */
+    if (remainder)
+    {
+        UART_SendData(UARTx, InBuf + UART_TX_FIFO_SIZE * i, remainder);
+        /* wait tx fifo empty */
+        while (UART_GetFlagStatus(UARTx, UART_FLAG_TX_EMPTY) != SET);
+    }
+}
+
+/**
+ * \brief   UART one wire config.
+ * \param   UARTx: Select the UART peripheral. \ref UART_Declaration
+ * \param   NewState: UART one wire config is set or not.
+ *          This parameter can be one of the following values:
+ *          \arg true: UART one wire config is set.
+ *          \arg false: UART one wire config is unset.
+ * \return  None.
+ */
+void UART_OneWireConfig(UART_TypeDef *UARTx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+
+    uint32_t uart_id = (((uint32_t)UARTx - UART0_BASE) / 0x400);
+
+    uint32_t uartx_one_wire_mask = PCC_REG_READ_BITFIELD(PCC_r_PMUX_TEST_MODE, R_PMUX_1_WIRE_UART_EN);
+
+    uartx_one_wire_mask = NewState ?
+                          (uartx_one_wire_mask | BIT(uart_id)) :
+                          (uartx_one_wire_mask & ~BIT(uart_id));
+
+    PCC_REG_WRITE_BITFIELD(PCC_r_PMUX_TEST_MODE, R_PMUX_1_WIRE_UART_EN, uartx_one_wire_mask);
+}
+
+/**
+  * \brief  UART clock divider config.
+  * \param  UARTx: Select the UART peripheral. \ref UART_Declaration
+  * \param  ClockDiv: specifies the APB peripheral to gates its clock. \ref Clock_Divider
+  * \return None
+  */
+void UART_SetClock(UART_TypeDef *UARTx, uint16_t ClockSrc, uint16_t ClockDiv)
+{
+    assert_param(IS_UART_DIV(ClockDiv));
+
+    if (UARTx == UART0)
+    {
+        PCC_REG_WRITE_BITFIELD(PCC_REG_UART0, R_UART0_CLK_DIV_SEL, ClockDiv);
+    }
+    else if (UARTx == UART1)
+    {
+        PCC_REG_WRITE_BITFIELD(PCC_REG_UART1, R_UART1_CLK_DIV_SEL, ClockDiv);
+    }
+    else if (UARTx == UART2)
+    {
+        PCC_REG_WRITE_BITFIELD(PCC_REG_UART2, R_UART2_CLK_DIV_SEL, ClockDiv);
+    }
+    else if (UARTx == UART3)
+    {
+        PCC_REG_WRITE_BITFIELD(PCC_REG_UART3, R_UART3_CLK_DIV_SEL, ClockDiv);
+    }
+
+    uint8_t divider = 1;
+    if (ClockDiv < UART_CLOCK_DIV_40)
+    {
+        divider = BIT(ClockDiv);
+    }
+    else if (ClockDiv == UART_CLOCK_DIV_40)
+    {
+        divider = 40;
+    }
+    else if (ClockDiv == UART_CLOCK_DIV_64)
+    {
+        divider = 64;
+    }
+    if (ClockSrc == UART_CLOCK_SRC_40M)
+    {
+        uart_clock_src_hz = 40000000 / divider;
+    }
+
+    return;
+}
+
+void UART_ClockAutoModeCmd(UART_TypeDef *UARTx, FunctionalState Newstate)
+{
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+
+    uint32_t uart_id = (((uint32_t)UARTx - UART0_BASE) / 0x400);
+    volatile uint32_t *manual_force = (volatile uint32_t *)(PCC_REG_BASE + PCC_REG_PERION_CLK_REG4X);
+    volatile uint32_t *clken_o = (volatile uint32_t *)(PCC_REG_BASE + PCC_REG_PERION_CLK_REG0X);
+
+    if (Newstate == DISABLE)
+    {
+        *manual_force |= BIT(12 + uart_id);
+        while (!(*clken_o & BIT(12 + uart_id)));
+    }
+    else
+    {
+        *manual_force &= ~BIT(12 + uart_id);
+    }
+
+    return;
+}
+
+
+static uint32_t UART_CalcAdjMask(uint32_t adj_num, uint32_t frame_len)
+{
+    /* Initialize accumulator to frame_len / 2 for center-aligned distribution */
+    uint32_t mask = 0, acc = frame_len / 2;
+
+    for (uint32_t i = 0; i < frame_len; i++)
+    {
+        acc += adj_num;
+
+        /* Check if accumulator overflows the threshold (frame_len) */
+        uint32_t bit = (acc >= frame_len);
+        mask |= (bit << i);
+        acc -= (bit * frame_len);
+    }
+    return mask;
+}
+
+static uint32_t UART_CalcBaudSettings(uint32_t baudrate, uint8_t frame_len,
+                                      uint16_t *div, uint16_t *ovsr, uint16_t *adj)
+{
+    /* Default initialization */
+    *div = 1;
+    *ovsr = 10;
+    *adj = 0;
+
+    /*
+     * Calculate target clock cycles per bit.
+     * Note: it will overflow when Clock > 67MHz.
+     */
+    uint32_t target_bit_x64 = ((uart_clock_src_hz << 6) + (baudrate / 2)) / baudrate;
+    uint32_t target_frame_x64 = target_bit_x64 * frame_len;
+    uint32_t min_err = 0xFFFFFFFF;
+    uint32_t last_div_try = 0;
+
+    /* Iterate through valid Oversampling Ratios to find the best Div */
+    for (uint32_t ovsr_try = UART_MAX_OVSR; ovsr_try >= UART_MIN_OVSR; ovsr_try--)
+    {
+        /* Calculate trial Divider based on current OVSR guess */
+        uint32_t div_try = target_bit_x64 / (ovsr_try << 6);
+
+        if (div_try == 0 || div_try == last_div_try) { continue; }
+        last_div_try = div_try;
+
+        /* Reverse calculation: Given this Div, what is the precise OVSR needed? */
+        uint32_t ideal_ovsr_x64 = target_bit_x64 / div_try;
+
+        /* Split precise OVSR into Integer and Fractional parts */
+        uint32_t ovsr_int = ideal_ovsr_x64 >> 6;
+        uint32_t ovsr_frac = ideal_ovsr_x64 & 0x3F;
+
+        /* Filter invalid OVSR integer parts */
+        if (ovsr_int < UART_MIN_OVSR || ovsr_int > UART_MAX_OVSR) { continue; }
+
+        /*
+         * Convert OVSR fraction to Adjustment bits (distributed over frame_len).
+         * Formula: (Fraction/64) * FrameLen. Rounding (+32) included.
+         */
+        uint32_t adj_cnt = (ovsr_frac * frame_len + 32) >> 6;
+
+        /* Handle carry-over case (e.g., fraction rounds up to a full bit) */
+        if (adj_cnt >= frame_len)
+        {
+            adj_cnt = 0;
+            ovsr_int++;
+            if (ovsr_int > UART_MAX_OVSR) { continue; }
+        }
+
+        /* Generate the mask temporarily to verify constraints */
+        uint32_t temp_adj = UART_CalcAdjMask(adj_cnt, frame_len);
+
+#if (UART_SUPPORT_CONSTRAINT_START_AND_STOP_ADJ == 1)
+        /*
+         * Constraint Check:
+         * Prevent that Start Bit (Bit 0) is 0,
+         * meanwhile Last Stop Bit (Bit frame_len-1) is 1.
+         */
+        uint32_t start_bit_val = temp_adj & 0x01;
+        uint32_t stop_bit_val  = (temp_adj >> (frame_len - 1)) & 0x01;
+
+        if (start_bit_val == 0 && stop_bit_val == 1)
+        {
+            /* Constraint failed, skip this OVSR candidate */
+            continue;
+        }
+#endif
+
+        /* Calculate actual cycles generated by these parameters (x64 format) */
+        uint32_t real_cycles_x64 = div_try * ((ovsr_int * frame_len + adj_cnt) << 6);
+
+        /* Calculate absolute error */
+        uint32_t diff = (real_cycles_x64 > target_frame_x64) ?
+                        (real_cycles_x64 - target_frame_x64) :
+                        (target_frame_x64 - real_cycles_x64);
+
+        /* Update best result if error is smaller, or same error with larger Div (lower power?) */
+        if (diff < min_err)
+        {
+            min_err = diff;
+            *div = div_try;
+            *ovsr = ovsr_int - UART_OVSR_OFFSET;
+            *adj = temp_adj;
+
+            if (diff == 0) { break; }
+        }
+    }
+
+    uint32_t err_x10000 = 10000;
+    if (min_err != 0xFFFFFFFF && target_frame_x64 > 0)
+    {
+        err_x10000 = (min_err * 10000 + (target_frame_x64 / 2)) / target_frame_x64;
+    }
+    return err_x10000;
+}
+
+uint32_t UART_GetBaudSettings(uint32_t baudrate,
+                              uint8_t data_width, uint8_t parity, uint8_t stop_bits,
+                              uint16_t *div, uint16_t *ovsr, uint16_t *adj)
+{
+    uint32_t target_baudrate = 115200;
+
+    if ((uint32_t)baudrate < UART_BAUD_RATE_MAXIMUM)
+    {
+        target_baudrate = uart_baudrate_table[baudrate];
+    }
+    else
+    {
+        target_baudrate = baudrate;
+    }
+
+    uint8_t frame_len = 1 +
+                        (uint8_t)(data_width == UART_WORD_LENGTH_7BIT ? 7 : 8) +
+                        (uint8_t)(parity == UART_PARITY_NO_PARTY ? 0 : 1) +
+                        (uint8_t)(stop_bits == UART_STOP_BITS_1 ? 1 : 2);
+
+    return UART_CalcBaudSettings(target_baudrate, frame_len, div, ovsr, adj);
+}
+
+
+
diff --git a/bee/drivers/uart/src/device/rtl87x2j/rtl_uart_def.h b/bee/drivers/uart/src/device/rtl87x2j/rtl_uart_def.h
new file mode 100644
index 00000000..35f9e4a3
--- /dev/null
+++ b/bee/drivers/uart/src/device/rtl87x2j/rtl_uart_def.h
@@ -0,0 +1,727 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef RTL_UART_DEF_H
+#define RTL_UART_DEF_H
+
+#include "utils/rtl_utils.h"
+#include "address_map.h"
+
+#ifdef  __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+
+/*============================================================================*
+ *                          UART Defines
+ *============================================================================*/
+/** \defgroup UART        UART
+  * \brief
+  * \{
+  */
+
+/** \defgroup UART_Exported_Constants UART Exported Constants
+  * \brief
+  * \{
+  */
+
+/**
+ * \defgroup UART_Defines UART Defines
+ * \{
+ * \ingroup  UART_Exported_Constants
+ */
+#define CHIP_UART_NUM                       (4)
+#define UART_SUPPORT_TX_DONE                (1)
+#define UART_SUPPORT_TX_THRESHOLD           (1)
+#define UART_SUPPORT_TXDATA_API             (1)
+#define UART_SUPPORT_HALF_WORD              (0)
+#define UART_SUPPORT_CLEAR_TX_FIFO          (1)
+#define UART_SUPPORT_AUTO_CLOCK             (1)
+
+/** End of UART_Defines
+  * \}
+  */
+
+/** End of UART_Exported_Constants
+  * \}
+  */
+
+/** End of UART
+  * \}
+  */
+
+/*============================================================================*
+ *                          UART Registers Memory Map
+ *============================================================================*/
+typedef struct
+{
+    __IO uint32_t UART_DLL;                  /*!< 0x00 */
+    __IO uint32_t UART_DLM_IER;              /*!< 0x04 */
+    __IO uint32_t UART_IIR_FCR;              /*!< 0x08 */
+    __IO uint32_t UART_LCR;                  /*!< 0x0C */
+    __IO uint32_t UART_CTRL0;                /*!< 0x10 */
+    __I  uint32_t UART_LSR;                  /*!< 0x14 */
+    __IO uint32_t UART_CTRL1;                /*!< 0x18 */
+    __IO uint32_t UART_SCR;                  /*!< 0x1C */
+    __IO uint32_t UART_STSR;                 /*!< 0x20 */
+    __IO uint32_t UART_RBR_THR;              /*!< 0x24 */
+    __IO uint32_t UART_MISCR;                /*!< 0x28 */
+    __IO uint32_t UART_DUMMY;                /*!< 0x2C */
+    __IO uint32_t UART_RSVD1[4];             /*!< 0x30 - 0x3C */
+    __IO uint32_t UART_RX_TIMEOUT;           /*!< 0x40 */
+    __IO uint32_t UART_RX_TIMEOUT_STS;       /*!< 0x44 */
+    __IO uint32_t UART_RX_TIMEOUT_EN;        /*!< 0x48 */
+    __I  uint32_t UART_RXTX_FIFO_WL;         /*!< 0x4C */
+    __IO uint32_t UART_INT_MASK;             /*!< 0x50 */
+    __I  uint32_t UART_TXDONE_INT;           /*!< 0x54 */
+    __I  uint32_t UART_TX_THD_INT;           /*!< 0x58 */
+    __IO uint32_t UART_CTRL2;                /*!< 0x5C */
+    __IO uint32_t UART_VERSION;              /*!< 0x60 */
+    __IO uint32_t UART_QACTIVE_CTRL;         /*!< 0x64 */
+} UART_TypeDef;
+
+/*============================================================================*
+ *                          UART Declaration
+ *============================================================================*/
+/** \defgroup UART        UART
+  * \brief
+  * \{
+  */
+
+/** \defgroup UART_Exported_Constants UART Exported Constants
+  * \brief
+  * \{
+  */
+
+/** \defgroup UART_Declaration UART Declaration
+  * \{
+  * \ingroup  UART_Exported_Constants
+  */
+
+#define UART0                   ((UART_TypeDef *) UART0_BASE)
+#define UART1                   ((UART_TypeDef *) UART1_BASE)
+#define UART2                   ((UART_TypeDef *) UART2_BASE)
+#define UART3                   ((UART_TypeDef *) UART3_BASE)
+
+#define IS_UART_PERIPH(PERIPH)  (((PERIPH) == UART0) || \
+                                 ((PERIPH) == UART1) || \
+                                 ((PERIPH) == UART2) || \
+                                 ((PERIPH) == UART3))
+
+/** End of UART_Declaration
+  * \}
+  */
+
+/** End of UART_Exported_Constants
+  * \}
+  */
+
+/** End of UART
+  * \}
+  */
+
+/*============================================================================*
+ *                          UART Private Types
+ *============================================================================*/
+typedef struct
+{
+    uint32_t uart_reg[13];
+} UARTStoreReg_Typedef;
+
+/*============================================================================*
+ *                          UART Registers and Field Descriptions
+ *============================================================================*/
+/* 0x00
+   7:0     R/W    dll                             8'h0
+   31:8    R      reserved1                       24'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t dll: 8;
+        const uint32_t reserved_0: 24;
+    } b;
+} UART_DLL_TypeDef;
+
+
+/* 0x04
+   7:0     R/W    dlm                                 8'h0
+   31:8    R      reserved2                           24'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t dlm: 8;
+        const uint32_t reserved_0: 24;
+    } b;
+} UART_DLM_TypeDef;
+
+
+/* 0x04
+   0       R/W    erbi                            1'h0
+   1       R/W    etbei                           1'h0
+   2       R/W    elsi                            1'h0
+   3       R/W    uart_dummy_000                  1'h0
+   4       R/W    tx_empty_stop_int_en            1'h0
+   5       R/W    tx_fifo_th_int_en               1'h0
+   31:6    R      reserved3                       26'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t erbi: 1;
+        uint32_t etbei: 1;
+        uint32_t elsi: 1;
+        uint32_t uart_dummy_000: 1;
+        uint32_t tx_empty_stop_int_en: 1;
+        uint32_t tx_fifo_th_int_en: 1;
+        const uint32_t reserved_0: 26;
+    } b;
+} UART_IER_TypeDef;
+
+
+/* 0x08
+   0       R      int_pend                        1'h1
+   3:1     R      int_id                          3'h0
+   31:4    R      reserved4                       28'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t int_pend: 1;
+        const uint32_t int_id: 3;
+        const uint32_t reserved_0: 28;
+    } b;
+} UART_IIR_TypeDef;
+
+
+/* 0x08
+   0       W      rxfifo_error_en                 1'h1
+   1       R/WAC  clear_rxfifo                    1'h0
+   2       R/WAC  clear_txfifo                    1'h0
+   3       W      dma_mode                        1'h0
+   7:4     R      reserved7                       4'h0
+   12:8    W      rxfifo_trigger_level            5'he
+   15:13   R      reserved6                       3'h0
+   20:16   W      tx_fifo_th                      5'h0
+   31:21   R      reserved5                       11'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t rxfifo_error_en: 1;
+        uint32_t clear_rxfifo: 1;
+        uint32_t clear_txfifo: 1;
+        uint32_t dma_mode: 1;
+        const uint32_t reserved_2: 4;
+        uint32_t rxfifo_trigger_level: 5;
+        const uint32_t reserved_1: 3;
+        uint32_t tx_fifo_th: 5;
+        const uint32_t reserved_0: 11;
+    } b;
+} UART_FCR_TypeDef;
+
+
+/* 0x0C
+   0       R/W    wls0                            1'h1
+   1       R      reserved9                       1'h1
+   2       R/W    stb                             1'h0
+   3       R/W    parity_en                       1'h0
+   4       R/W    even_parity_sel                 1'h0
+   5       R/W    stick_parity                    1'h0
+   6       R/W    break_ctrl                      1'h0
+   7       R/W    dlab                            1'h0
+   31:8    R      reserved8                       24'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t wls0: 1;
+        const uint32_t reserved_1: 1;
+        uint32_t stb: 1;
+        uint32_t parity_sel: 3;
+        uint32_t break_ctrl: 1;
+        uint32_t dlab: 1;
+        const uint32_t reserved_0: 24;
+    } b;
+} UART_LCR_TypeDef;
+
+
+/* 0x10
+   0       R/W    uart_dummy_002                  1'h0
+   1       R/W    rts                             1'h0
+   3:2     R/W    uart_dummy_001                  2'h0
+   4       R/W    loopback_en                     1'h0
+   5       R/W    autoflow_en                     1'h0
+   31:6    R      reserved10                      26'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t uart_dummy_002: 1;
+        uint32_t rts: 1;
+        uint32_t uart_dummy_001: 2;
+        uint32_t loopback_en: 1;
+        uint32_t autoflow_en: 1;
+        const uint32_t reserved_0: 26;
+    } b;
+} UART_CTRL0_TypeDef;
+
+
+/* 0x14
+   0       R      rxfifo_datardy                  1'h0
+   1       R      overrun_err                     1'h0
+   2       R      parity_err                      1'h0
+   3       R      framing_err                     1'h0
+   4       R      break_err_int                   1'h0
+   5       R      tx_fifo_empty                   1'h1
+   6       R      tx_empty                        1'h1
+   7       R      rxfifo_err                      1'h0
+   31:8    R      reserved11                      24'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t rxfifo_datardy: 1;
+        const uint32_t overrun_err: 1;
+        const uint32_t parity_err: 1;
+        const uint32_t framing_err: 1;
+        const uint32_t break_err_int: 1;
+        const uint32_t tx_fifo_empty: 1;
+        const uint32_t tx_empty: 1;
+        const uint32_t rxfifo_err: 1;
+        const uint32_t reserved_0: 24;
+    } b;
+} UART_LSR_TypeDef;
+
+
+/* 0x18
+   0       R      cts_tog                         1'h0
+   3:1     R      reserved13                      3'h0
+   4       R      cts_inv                         1'h1
+   31:5    R      reserved12                      27'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t cts_tog: 1;
+        const uint32_t reserved_1: 3;
+        const uint32_t cts_inv: 1;
+        const uint32_t reserved_0: 27;
+    } b;
+} UART_CTRL1_TypeDef;
+
+
+/* 0x1C
+   2:0     R      reserved16                      3'h0
+   3       R/W    pin_lb_test                     1'h0
+   5:4     R/W    uart_dummy_003                  2'h3
+   6       R/W    rxbreaksignalinterruptenable    1'h0
+   7       R/W1C  rxbreaksignalinterruptstatus    1'h0
+   11:8    R/W    dbg_sel                         4'h0
+   15:12   R      reserved15                      4'h0
+   27:16   R/W    xfactor_adj                     12'h0
+   31:28   R      reserved14                      4'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t reserved_2: 3;
+        uint32_t pin_lb_test: 1;
+        uint32_t uart_dummy_003: 2;
+        uint32_t rxbreaksignalinterruptenable: 1;
+        uint32_t rxbreaksignalinterruptstatus: 1;
+        uint32_t dbg_sel: 4;
+        const uint32_t reserved_1: 4;
+        uint32_t xfactor_adj: 12;
+        const uint32_t reserved_0: 4;
+    } b;
+} UART_SCR_TypeDef;
+
+
+/* 0x20
+   2:0     R      reserved19                      3'h0
+   3       R/W    reset_rcv                       1'h0
+   7:4     R/W    xfactor                         4'hb
+   18:8    R      reserved18                      11'h0
+   23:19   R      tx_fifo_th                      5'h0
+   24      R      dma_mode                        1'h0
+   25      R      rxfifo_error_en                 1'h1
+   30:26   R      rxfifo_trigger_level            5'he
+   31      R      reserved17                      1'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t reserved_2: 3;
+        uint32_t reset_rcv: 1;
+        uint32_t xfactor: 4;
+        const uint32_t reserved_1: 11;
+        const uint32_t tx_fifo_th: 5;
+        const uint32_t dma_mode: 1;
+        const uint32_t rxfifo_error_en: 1;
+        const uint32_t rxfifo_trigger_level: 5;
+        const uint32_t reserved_0: 1;
+    } b;
+} UART_STSR_TypeDef;
+
+
+/* 0x24
+   7:0     R      rx_data                         8'h0
+   31:8    R      reserved20                      24'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t rx_data: 8;
+        const uint32_t reserved_0: 24;
+    } b;
+} UART_RBR_TypeDef;
+
+
+
+/* 0x24
+   7:0     W      tx_data                             8'h0
+   31:8    R      reserved21                          24'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t tx_data: 8;
+        const uint32_t reserved_0: 24;
+    } b;
+} UART_THR_TypeDef;
+
+
+
+/* 0x28
+   0       R/W    uart_dummy_005                  1'h0
+   1       R/W    txdma_en                        1'h0
+   2       R/W    rxdma_en                        1'h0
+   7:3     R/W    txdma_burstsize                 5'h0
+   13:8    R/W    rxdma_burstsize                 6'h0
+   15:14   R/W    uart_dummy_004                  2'h0
+   31:16   R      reserved22                      16'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t uart_dummy_005: 1;
+        uint32_t txdma_en: 1;
+        uint32_t rxdma_en: 1;
+        uint32_t txdma_burstsize: 5;
+        uint32_t rxdma_burstsize: 6;
+        uint32_t uart_dummy_004: 2;
+        const uint32_t reserved_0: 16;
+    } b;
+} UART_MISCR_TypeDef;
+
+
+/* 0x2C
+   31:0    R/W    uart_dummy_006                  32'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t uart_dummy_006: 32;
+    } b;
+} UART_DUMMY_TypeDef;
+
+
+
+/* 0x40
+   3:0     R/W    rxidle_timeout_value            4'h0
+   29:4    R      reserved23                      26'h0
+   30      R/W    rxidle_timeout_en_clr_opt       1'h0
+   31      R/W    rxidle_timeout_en               1'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t rxidle_timeout_value: 4;
+        const uint32_t reserved_0: 26;
+        uint32_t rxidle_timeout_en_clr_opt: 1;
+        uint32_t rxidle_timeout_en: 1;
+    } b;
+} UART_RX_TIMEOUT_TypeDef;
+
+
+/* 0x44
+   0       R/W1C  rxidle_timeout_int_sts          1'h0
+   31:1    R      reserved24                      31'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t rxidle_timeout_int_sts: 1;
+        const uint32_t reserved_0: 31;
+    } b;
+} UART_RX_TIMEOUT_STS_TypeDef;
+
+
+/* 0x48
+   0       R/W    rxidle_timeout_int_en           1'h0
+   31:1    R      reserved25                      31'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t rxidle_timeout_int_en: 1;
+        const uint32_t reserved_0: 31;
+    } b;
+} UART_RX_TIMEOUT_EN_TypeDef;
+
+
+/* 0x4C
+   4:0     R      tx_fifo_level                   5'h0
+   7:5     R      reserved27                      3'h0
+   13:8    R      rx_fifo_level                   6'h0
+   31:14   R      reserved26                      18'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t tx_fifo_level: 5;
+        const uint32_t reserved_1: 3;
+        const uint32_t rx_fifo_level: 6;
+        const uint32_t reserved_0: 18;
+    } b;
+} UART_RXTX_FIFO_WL_TypeDef;
+
+
+/* 0x50
+   0       R/W    rd_ava_int_mask                     1'h0
+   1       R/W    txfifo_empty_int_mask               1'h0
+   2       R/W    rx_line_sts_int_mask                1'h0
+   3       R/W    modem_sts_int_mask                  1'h0
+   4       R/W    rx_break_int_mask                   1'h0
+   5       R/W    rxidle_timeout_int_mask             1'h0
+   6       R/W    txdone_int_mask                     1'h0
+   7       R/W    tx_thd_int_mask                     1'h0
+   31:8    R      reserved28                          24'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t rd_ava_int_mask: 1;
+        uint32_t txfifo_empty_int_mask: 1;
+        uint32_t rx_line_sts_int_mask: 1;
+        uint32_t modem_sts_int_mask: 1;
+        uint32_t rx_break_int_mask: 1;
+        uint32_t rxidle_timeout_int_mask: 1;
+        uint32_t txdone_int_mask: 1;
+        uint32_t tx_thd_int_mask: 1;
+        const uint32_t reserved_0: 24;
+    } b;
+} UART_INT_MASK_TypeDef;
+
+
+/* 0x54
+   0       R      tx_empty_stop_rdy               1'h0
+   31:1    R      reserved29                      31'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t tx_empty_stop_rdy: 1;
+        const uint32_t reserved_0: 31;
+    } b;
+} UART_TXDONE_INT_TypeDef;
+
+
+/* 0x58
+   0       R      int_tx_fifo                     1'h0
+   31:1    R      reserved30                      31'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t int_tx_fifo: 1;
+        const uint32_t reserved_0: 31;
+    } b;
+} UART_TX_THD_INT_TypeDef;
+
+
+/* 0x5C
+   0       R/W    rx_data_sw                      1'h0
+   31:1    R      reserved31                      31'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t rx_data_sw: 1;
+        const uint32_t reserved_0: 31;
+    } b;
+} UART_CTRL2_TypeDef;
+
+
+/* 0x60
+   31:0    R      rtlversion                      32'h20240227
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t rtlversion: 32;
+    } b;
+} UART_VERSION_TypeDef;
+
+
+/* 0x64
+   0       R/W    qact_pclk_icg_en                1'h0
+   1       R/W    qact_sclk_man_data              1'h0
+   2       R/W    qact_sclk_man_en                1'h0
+   3       R/W    qact_pclk_man_data              1'h0
+   4       R/W    qact_pclk_man_en                1'h0
+   5       R/W    qact_pwr_man_data               1'h0
+   6       R/W    qact_pwr_man_en                 1'h0
+   15:7    R      reserved33                      9'h0
+   16      R/W    rx_qact_auto_en                 1'h1
+   17      R/W1O  rx_qact_auto_sts                1'h1
+   29:18   R/W    rx_qact_auto_timeout_val_sel    12'h0
+   31:30   R      reserved32                      2'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t qact_pclk_icg_en: 1;
+        uint32_t qact_sclk_man_data: 1;
+        uint32_t qact_sclk_man_en: 1;
+        uint32_t qact_pclk_man_data: 1;
+        uint32_t qact_pclk_man_en: 1;
+        uint32_t qact_pwr_man_data: 1;
+        uint32_t qact_pwr_man_en: 1;
+        const uint32_t reserved_1: 9;
+        uint32_t rx_qact_auto_en: 1;
+        uint32_t rx_qact_auto_sts: 1;
+        uint32_t rx_qact_auto_timeout_val_sel: 12;
+        const uint32_t reserved_0: 2;
+    } b;
+} UART_QACTIVE_CTRL_TypeDef;
+
+
+/*============================================================================*
+ *                          UART TYPE/API Wrappers
+ *============================================================================*/
+/** \defgroup UART        UART
+  * \brief
+  * \{
+  */
+
+
+/** \defgroup UART_Exported_Constants UART Exported Constants
+  * \brief
+  * \{
+  */
+
+/**
+ * \defgroup    UART_Clock_Source UART Clock Source
+ * \{
+ * \ingroup     UART_Exported_Constants
+ */
+typedef enum
+{
+    UART_CLOCK_SRC_40M = 0x0,
+} UARTClockSrc_TypeDef;
+
+#define IS_UART_CLOCK_SRC(CLOCK)     (((CLOCK) == UART_CLOCK_SRC_40M))
+
+/** End of UART_Clock_Source
+  * \}
+  */
+
+/**
+ * \defgroup    UART_Clock_Divider UART Clock Divider
+ * \{
+ * \ingroup     UART_Exported_Constants
+ */
+typedef enum
+{
+    UART_CLOCK_DIV_1 = 0x0,
+    UART_CLOCK_DIV_2 = 0x1,
+    UART_CLOCK_DIV_4 = 0x2,
+    UART_CLOCK_DIV_8 = 0x3,
+    UART_CLOCK_DIV_16 = 0x4,
+    UART_CLOCK_DIV_32 = 0x5,
+    UART_CLOCK_DIV_40 = 0x6,
+    UART_CLOCK_DIV_64 = 0x7,
+} UARTClockDiv_TypeDef;
+
+#define IS_UART_CLOCK_DIV(DIV) (((DIV) == UART_CLOCK_DIV_1) || \
+                                ((DIV) == UART_CLOCK_DIV_2) || \
+                                ((DIV) == UART_CLOCK_DIV_4) || \
+                                ((DIV) == UART_CLOCK_DIV_8) || \
+                                ((DIV) == UART_CLOCK_DIV_16) || \
+                                ((DIV) == UART_CLOCK_DIV_32) || \
+                                ((DIV) == UART_CLOCK_DIV_40) || \
+                                ((DIV) == UART_CLOCK_DIV_64))
+
+/** End of UART_Clock_Divider
+  * \}
+  */
+
+/** End of UART_Exported_Constants
+  * \}
+  */
+
+/** End of UART
+  * \}
+  */
+
+#ifdef  __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* RTL_UART_DEF_H */
diff --git a/bee/drivers/uart/src/device/rtl_common/rtl_uart.c b/bee/drivers/uart/src/device/rtl_common/rtl_uart.c
new file mode 100644
index 00000000..4a0ac1f3
--- /dev/null
+++ b/bee/drivers/uart/src/device/rtl_common/rtl_uart.c
@@ -0,0 +1,844 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *                           Header Files
+ *============================================================================*/
+#include "rtl_uart.h"
+#include "rtl_rcc.h"
+
+/*============================================================================*
+ *                           Private Functions
+ *============================================================================*/
+/* UART Immediate Number */
+#define FCR_CLEAR_RX_FIFO_SET           ((uint32_t)(1 << 1))
+#define FCR_CLEAR_RX_FIFO_RESET         ((uint32_t)~(1 << 1))
+#define FCR_CLEAR_TX_FIFO_SET           ((uint32_t)(1 << 2))
+#define FCR_CLEAR_TX_FIFO_RESET         ((uint32_t)~(1 << 2))
+
+#if (UART_SUPPORT_RAP_FUNCTION == 1)
+bool UART_IsSupportRAP(UART_TypeDef *UARTx);
+#endif
+/*============================================================================*
+ *                           Public Functions
+ *============================================================================*/
+/**
+  * \brief  Deinitializes the UART peripheral registers to their default reset values(turn off UART clock).
+  * \param  UARTx: Select the UART peripheral. \ref UART_Declaration
+  * \return None
+  */
+void UART_DeInit(UART_TypeDef *UARTx)
+{
+    assert_param(IS_UART_PERIPH(UARTx));
+
+#ifdef UART0
+    if (UARTx == UART0)
+    {
+        RCC_ClockCmd(UART0_CLOCK, DISABLE);
+        return;
+    }
+#endif
+#ifdef UART1
+    if (UARTx == UART1)
+    {
+        RCC_ClockCmd(UART1_CLOCK, DISABLE);
+        return;
+    }
+#endif
+#ifdef UART2
+    if (UARTx == UART2)
+    {
+        RCC_ClockCmd(UART2_CLOCK, DISABLE);
+        return;
+    }
+#endif
+#ifdef UART3
+    if (UARTx == UART3)
+    {
+        RCC_ClockCmd(UART3_CLOCK, DISABLE);
+        return;
+    }
+#endif
+#ifdef UART4
+    if (UARTx == UART4)
+    {
+        RCC_ClockCmd(UART4_CLOCK, DISABLE);
+        return;
+    }
+#endif
+#ifdef UART5
+    if (UARTx == UART5)
+    {
+        RCC_ClockCmd(UART5_CLOCK, DISABLE);
+        return;
+    }
+#endif
+#ifdef UART6
+    if (UARTx == UART6)
+    {
+        RCC_ClockCmd(UART6_CLOCK, DISABLE);
+        return;
+    }
+#endif
+}
+
+/**
+  * \brief  Initializes the UART peripheral according to the specified
+  *         parameters in the UART_InitStruct
+  * \param  UARTx: Select the UART peripheral. \ref UART_Declaration
+  * \param  UART_InitStruct: pointer to a UART_InitTypeDef structure that
+  *         contains the configuration information for the specified UART peripheral
+  * \return None
+  */
+void UART_Init(UART_TypeDef *UARTx, UART_InitTypeDef *UART_InitStruct)
+{
+    assert_param(IS_UART_PERIPH(UARTx));
+    assert_param(IS_UART_WORD_LENGTH(UART_InitStruct->UART_WordLen));
+    assert_param(IS_UART_STOPBITS(UART_InitStruct->UART_StopBits));
+    assert_param(IS_UART_PARITY(UART_InitStruct->UART_Parity));
+    assert_param(IS_UART_RX_FIFO_TRIGGER_LEVEL(UART_InitStruct->UART_RxThdLevel));
+    assert_param(IS_UART_IDLE_TIME(UART_InitStruct->UART_IdleTime));
+    assert_param(IS_UART_DMA_CFG(UART_InitStruct->UART_DMAEn));
+    assert_param(IS_UART_AUTO_FLOW_CTRL(UART_InitStruct->UART_HardwareFlowControl));
+
+    /* Set tx only mode */
+    UART_STSR_TypeDef uart_0x20 = {.d32 = UARTx->UART_STSR};
+    uart_0x20.b.reset_rcv = UART_InitStruct->UART_TxOnlyEn;
+    UARTx->UART_STSR = uart_0x20.d32;
+
+    /* Clear DLAB bit */
+    UART_LCR_TypeDef uart_0x0c = {.d32 = UARTx->UART_LCR};
+    uart_0x0c.b.dlab = 0x0;
+    UARTx->UART_LCR = uart_0x0c.d32;
+
+    /* Disable all interrupt */
+    UARTx->UART_DLM_IER = 0x0;
+
+    /* Read to clear Line Status Reg */
+    (void) UARTx->UART_LSR;
+
+    /* Clear FIFO */
+    UART_FCR_TypeDef uart_0x08 = {.d32 = 0x0};
+    uart_0x08.b.clear_rxfifo = 0x1;
+#if (UART_SUPPORT_CLEAR_TX_FIFO == 1)
+    uart_0x08.b.clear_txfifo = 0x1;
+#endif
+    UARTx->UART_IIR_FCR = uart_0x08.d32;
+
+    /* Set baudrate, firstly set DLAB bit */
+    uart_0x0c.b.dlab = 0x1;
+    UARTx->UART_LCR = uart_0x0c.d32;
+    /* Set calibration parameters(OVSR) */
+    uart_0x20.b.xfactor = UART_InitStruct->UART_Ovsr;
+    UARTx->UART_STSR = uart_0x20.d32;
+    /* Set calibration parameters(OVSR_adj) */
+    UART_SCR_TypeDef uart_0x1c = {.d32 = UARTx->UART_SCR};
+    uart_0x1c.b.xfactor_adj = UART_InitStruct->UART_OvsrAdj;
+    UARTx->UART_SCR = uart_0x1c.d32;
+    /* Set DLL and DLH */
+    UARTx->UART_DLL = (UART_InitStruct->UART_Div & 0x00FF);
+    UARTx->UART_DLM_IER = ((UART_InitStruct->UART_Div & 0xFF00) >> 8);
+    /* After set baudrate, clear DLAB bit */
+    uart_0x0c.b.dlab = 0x0;
+    UARTx->UART_LCR = uart_0x0c.d32;
+
+    /* Set LCR reg */
+    uart_0x0c.b.wls0 = UART_InitStruct->UART_WordLen;
+    uart_0x0c.b.stb = UART_InitStruct->UART_StopBits;
+    uart_0x0c.b.parity_sel = UART_InitStruct->UART_Parity;
+    UARTx->UART_LCR = uart_0x0c.d32;
+
+    /* Set FCR reg, FIFO must enable */
+    uart_0x08.d32 = 0x0;
+    uart_0x08.b.rxfifo_error_en = ENABLE;
+    uart_0x08.b.dma_mode = UART_InitStruct->UART_DMAEn;
+    uart_0x08.b.rxfifo_trigger_level = UART_InitStruct->UART_RxThdLevel;
+    uart_0x08.b.tx_fifo_th = UART_InitStruct->UART_TxThdLevel;
+    UARTx->UART_IIR_FCR = uart_0x08.d32;
+
+    /* Harware flow control */
+    UART_CTRL0_TypeDef uart_0x10 = {.d32 = UARTx->UART_CTRL0};
+    uart_0x10.b.rts = UART_InitStruct->UART_HardwareFlowControl;
+    uart_0x10.b.autoflow_en = UART_InitStruct->UART_HardwareFlowControl;
+    UARTx->UART_CTRL0 = uart_0x10.d32;
+
+    /* Set rx idle time */
+    UARTx->UART_RX_TIMEOUT = UART_InitStruct->UART_IdleTime;
+
+    if (UART_InitStruct->UART_DMAEn == ENABLE)
+    {
+        /* Config UART Tx dma parameter */
+        UART_MISCR_TypeDef uart_0x28 = {.d32 = UARTx->UART_MISCR};
+        if (UART_InitStruct->UART_TxDMAEn != DISABLE)
+        {
+            /* Mask uart TX threshold value */
+            uart_0x28.b.txdma_en = ENABLE;
+            uint8_t tx_water_level = UART_InitStruct->UART_TxWaterLevel;
+            tx_water_level = (tx_water_level > UART_TX_FIFO_SIZE - 1) ? (UART_TX_FIFO_SIZE - 1) :
+                             (tx_water_level < 1) ? 1 : tx_water_level;
+            UART_InitStruct->UART_TxWaterLevel = tx_water_level;
+            uart_0x28.b.txdma_burstsize = UART_TX_FIFO_SIZE - UART_InitStruct->UART_TxWaterLevel;
+        }
+        /* Config UART Rx dma parameter */
+        if (UART_InitStruct->UART_RxDMAEn != DISABLE)
+        {
+            /* Mask uart RX threshold value */
+            uart_0x28.b.rxdma_en = ENABLE;
+            uart_0x28.b.rxdma_burstsize = UART_InitStruct->UART_RxWaterLevel;
+        }
+        UARTx->UART_MISCR = uart_0x28.d32;
+    }
+
+#if (UART_SUPPORT_AUTO_CLOCK == 1)
+    UART_QACTIVE_CTRL_TypeDef uart_qactive = {.d32 = UARTx->UART_QACTIVE_CTRL};
+    uart_qactive.b.rx_qact_auto_en = UART_InitStruct->UART_AutoModeEn;
+    uart_qactive.b.rx_qact_auto_timeout_val_sel = UART_InitStruct->UART_AutoModeTime;
+    uart_qactive.b.qact_pclk_icg_en = 1;
+    UARTx->UART_QACTIVE_CTRL = uart_qactive.d32;
+#endif
+
+    return;
+}
+
+/**
+  * \brief  Fills each UART_InitStruct member with its default value.
+  * \param  UART_InitStruct: pointer to an UART_InitTypeDef structure which will be initialized.
+  * \return None
+  */
+void UART_StructInit(UART_InitTypeDef *UART_InitStruct)
+{
+    //115200 default
+    UART_InitStruct->UART_Div                 = 20;
+    UART_InitStruct->UART_Ovsr                = 12;
+    UART_InitStruct->UART_OvsrAdj             = 0x252;
+
+    UART_InitStruct->UART_WordLen             = UART_WORD_LENGTH_8BIT;
+    UART_InitStruct->UART_StopBits            = UART_STOP_BITS_1;
+    UART_InitStruct->UART_Parity              = UART_PARITY_NO_PARTY;
+    UART_InitStruct->UART_TxThdLevel          = 16; //1~29
+    UART_InitStruct->UART_RxThdLevel          = 16; //1~29
+    UART_InitStruct->UART_IdleTime            = UART_RX_IDLE_2BYTE; //idle interrupt wait time
+    UART_InitStruct->UART_HardwareFlowControl = DISABLE;
+    UART_InitStruct->UART_DMAEn               = DISABLE;
+    UART_InitStruct->UART_TxDMAEn             = DISABLE;
+    UART_InitStruct->UART_RxDMAEn             = DISABLE;
+    UART_InitStruct->UART_TxWaterLevel        = 15; //Better to equal TX_FIFO_SIZE(16)- DMA_MSize
+    UART_InitStruct->UART_RxWaterLevel        = 1; //Better to equal DMA_MSize
+    UART_InitStruct->UART_TxOnlyEn            = DISABLE;
+#if (UART_SUPPORT_AUTO_CLOCK == 1)
+    UART_InitStruct->UART_AutoModeEn          = ENABLE;
+    UART_InitStruct->UART_AutoModeTime        = 20;
+#endif
+
+    return;
+}
+
+/**
+  * \brief  Mask or unmask the specified UART interrupts.
+  * \param  UART_INT: specifies the IR interrupts sources to be mask or unmask.
+  *         This parameter can be the following values:
+  *         \arg UART_INT_MASK_RD_AVA: mask INTCR(erbi).
+  *         \arg UART_INT_MASK_TX_FIFO_EMPTY: mask INTCR(etbei).
+  *         \arg UART_INT_MASK_RX_LINE_STS: mask INTCR(elsi).
+  *         \arg UART_INT_MASK_MODEM_STS: mask INTCR(edssi).
+  *         \arg UART_INT_MASK_RX_BREAK: mask rx break interrupt.
+  *         \arg UART_INT_MASK_RX_IDLE: mask rx idle interrupt.
+  *         \arg UART_INT_MASK_TX_DONE: mask the interrupt tx done interrupt.
+  *         \arg UART_INT_MASK_TX_THD: mask tx fifo threshold interrupt.
+  *         \arg UART_INT_MASK_CTS_TOGGLE: mask CTS toggle interrupt.
+  * \param  NewState: new state of the specified UART interrupts.
+  *         This parameter can be: ENABLE or DISABLE.
+  * \return None
+  */
+void UART_MaskINTConfig(UART_TypeDef *UARTx, uint32_t UART_INT_MASK, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+    assert_param(IS_UART_INT_MASK(UART_INT_MASK));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (NewState != DISABLE)
+    {
+        UARTx->UART_INT_MASK |= UART_INT_MASK;
+    }
+    else
+    {
+        UARTx->UART_INT_MASK &= ~(UART_INT_MASK);
+    }
+}
+
+/**
+  * \brief  Enables or disables the specified UART interrupts.
+  * \param  UARTx: Select the UART peripheral. \ref UART_Declaration
+  * \param  UART_INT: specifies the UART interrupts sources to be enabled or disabled.
+  *         This parameter can be any combination of the following values:
+  *         \arg UART_INT_RD_AVA: Rx data avaliable interrupt source.
+  *         \arg UART_INT_TX_FIFO_EMPTY: Tx FIFO empty interrupt source.
+  *         \arg UART_INT_RX_LINE_STS: Rx line status interrupt source.
+  *         \arg UART_INT_MODEM_STS: modem status interrupt source.
+  *         \arg UART_INT_TX_DONE: Tx data done interrupt source.
+  *         \arg UART_INT_TX_THD: Tx FIFO data <= thredhold interrupt source.
+  *         \arg UART_INT_RX_BREAK: Rx break signal interrupt source.
+  *         \arg UART_INT_RX_IDLE: Rx idle interrupt source.
+  *         \arg UART_INT_CTS_TOGGLE: CTS toggle interrupt source.
+  * \param  NewState: new state of the specified UART interrupts.
+  *         This parameter can be: ENABLE or DISABLE.
+  * \return None
+  */
+void UART_INTConfig(UART_TypeDef *UARTx, uint32_t UART_INT, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+    assert_param(IS_UART_INT(UART_INT));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (UART_INT & UART_INT_RX_IDLE)
+    {
+        UART_RX_TIMEOUT_TypeDef uart_0x40 = {.d32 = UARTx->UART_RX_TIMEOUT};
+        UART_RX_TIMEOUT_STS_TypeDef uart_0x44 = {.d32 = UARTx->UART_RX_TIMEOUT_STS};
+        UART_RX_TIMEOUT_EN_TypeDef uart_0x48 = {.d32 = UARTx->UART_RX_TIMEOUT_EN};
+        if (NewState == ENABLE)
+        {
+            uart_0x48.b.rxidle_timeout_int_en = 1;
+            UARTx->UART_RX_TIMEOUT_EN = uart_0x48.d32;
+            uart_0x40.b.rxidle_timeout_en = 1;
+            UARTx->UART_RX_TIMEOUT = uart_0x40.d32;
+        }
+        else
+        {
+            uart_0x40.b.rxidle_timeout_en = 0;
+            UARTx->UART_RX_TIMEOUT = uart_0x40.d32;
+            uart_0x44.b.rxidle_timeout_int_sts = 1;
+            UARTx->UART_RX_TIMEOUT_STS = uart_0x44.d32;
+            uart_0x48.b.rxidle_timeout_int_en = 0;
+            UARTx->UART_RX_TIMEOUT_EN = uart_0x48.d32;
+        }
+    }
+
+#if (UART_SUPPORT_CTS_TOGGLE == 1)
+    if (UART_INT & UART_INT_CTS_TOGGLE)
+    {
+        UART_CTRL0_TypeDef uart_0x10 = {.d32 = UARTx->UART_CTRL0};
+        uart_0x10.b.cts_tog_int_en = NewState;
+        UARTx->UART_CTRL0 = uart_0x10.d32;
+    }
+#endif
+    if (UART_INT & 0x3F)
+    {
+
+        if (NewState == ENABLE)
+        {
+            /* Enable the selected UARTx interrupts */
+            UARTx->UART_DLM_IER |= UART_INT;
+        }
+        else
+        {
+            /* Disable the selected UARTx interrupts */
+            UARTx->UART_DLM_IER &= (uint32_t)~UART_INT;
+        }
+    }
+    return;
+}
+
+/**
+  * \brief  Send data to tx FIFO.
+  * \param  UARTx: Select the UART peripheral. \ref UART_Declaration
+  * \param  InBuf: buffer to be written to Tx FIFO.
+  * \param  num: number of data to be written.
+  * \return None
+  */
+void UART_SendData(UART_TypeDef *UARTx, const uint8_t *InBuf, uint16_t Count)
+{
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+
+    while (Count--)
+    {
+        UARTx->UART_RBR_THR = *InBuf++;
+    }
+
+    return;
+}
+
+#if (UART_SUPPORT_HALF_WORD == 1)
+/**
+  * \brief  Send half word data to tx FIFO.
+  * \param  UARTx: Select the UART peripheral. \ref UART_Declaration
+  * \param  InBuf: buffer to be written to Tx FIFO.
+  * \param  num: number of data to be written.
+  * \return None
+  */
+void UART_SendHalfWordData(UART_TypeDef *UARTx, const uint16_t *InBuf, uint16_t Count)
+{
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+
+    while (Count--)
+    {
+        UARTx->UART_RBR_THR = *InBuf++;
+    }
+
+    return;
+}
+#endif
+
+/**
+  * \brief  Receive data from rx FIFO.
+  * \param  UARTx: Select the UART peripheral. \ref UART_Declaration
+  * \param[out] OutBuf: buffer to save data read from UART FIFO.
+  * \param  Count: number of data to be read.
+  * \return None
+  */
+void UART_ReceiveData(UART_TypeDef *UARTx, uint8_t *OutBuf, uint16_t Count)
+{
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+
+    while (Count--)
+    {
+        *OutBuf++ = (uint8_t)UARTx->UART_RBR_THR;
+    }
+
+    return;
+}
+
+#if (UART_SUPPORT_HALF_WORD == 1)
+/**
+  * \brief  Receive data from rx FIFO.
+  * \param  UARTx: Select the UART peripheral. \ref UART_Declaration
+  * \param[out] OutBuf: buffer to save data read from UART FIFO.
+  * \param  Count: number of data to be read.
+  * \return None
+  */
+void UART_ReceiveHalfWordData(UART_TypeDef *UARTx, uint16_t *OutBuf, uint16_t Count)
+{
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+
+    while (Count--)
+    {
+        *OutBuf++ = (uint16_t)UARTx->UART_RBR_THR;
+    }
+
+    return;
+}
+#endif
+
+/**
+  * \brief  Change UART baudrate.
+  * \param  UARTx: Select the UART peripheral. \ref UART_Declaration
+  * \param  div: parameter of the selected UART baudrate.
+  * \param  ovsr: parameter of the selected UART baudrate.
+  * \param  ovsr_adj: parameter of the selected UART baudrate.
+  * \return None.
+  */
+void UART_SetBaudRate(UART_TypeDef *UARTx, uint16_t div, uint16_t ovsr, uint16_t ovsr_adj)
+{
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+
+    /* Set baudrate, firstly set DLAB bit */
+    UART_LCR_TypeDef uart_0x0c = {.d32 = UARTx->UART_LCR};
+    uart_0x0c.b.dlab = 0x1;
+    UARTx->UART_LCR = uart_0x0c.d32;
+
+    /* Set calibration parameters(OVSR) */
+    UART_STSR_TypeDef uart_0x20 = {.d32 = UARTx->UART_STSR};
+    uart_0x20.b.xfactor = ovsr;
+    UARTx->UART_STSR = uart_0x20.d32;
+
+    /* Set calibration parameters(OVSR_adj) */
+    UART_SCR_TypeDef uart_0x1c = {.d32 = UARTx->UART_SCR};
+    uart_0x1c.b.xfactor_adj = ovsr_adj;
+    UARTx->UART_SCR = uart_0x1c.d32;
+
+    /* Set DLL and DLH */
+    UARTx->UART_DLL = (div & 0x00FF);
+    UARTx->UART_DLM_IER = ((div & 0xFF00) >> 8);
+
+    /* After set baudrate, clear DLAB bit */
+    uart_0x0c.b.dlab = 0x0;
+    UARTx->UART_LCR = uart_0x0c.d32;
+}
+
+/**
+  * \brief  Set UART parameters.
+  * \param  UARTx: Select the UART peripheral. \ref UART_Declaration
+  * \param  wordLen: data width of selected UART peripheral.
+  * \param  parity: parity of selected UART peripheral.
+  * \param  stopBits: stop bit of selected UART peripheral.
+  * \return None
+  */
+void UART_SetParams(UART_TypeDef *UARTx, uint16_t wordLen, uint16_t parity, uint16_t stopBits)
+{
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+
+    /* set LCR reg */
+    UART_LCR_TypeDef uart_0x0c = {.d32 = UARTx->UART_LCR};
+    uart_0x0c.b.wls0 = wordLen;
+    uart_0x0c.b.stb = stopBits;
+    uart_0x0c.b.parity_sel = parity;
+    UARTx->UART_LCR = uart_0x0c.d32;
+}
+
+/**
+  * \brief  UART loop back mode config.
+  * \param  UARTx: Select the UART peripheral. \ref UART_Declaration
+  * \param  NewState: new state, this parameter can be: ENABLE or DISABLE.
+  * \return None.
+  */
+void UART_LoopBackCmd(UART_TypeDef *UARTx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+
+    UART_CTRL0_TypeDef uart_0x10 = {.d32 = UARTx->UART_CTRL0};
+    uart_0x10.b.loopback_en = NewState;
+    UARTx->UART_CTRL0 = uart_0x10.d32;
+}
+
+/**
+  * \brief  Checks whether the specified UART flag is set or not.
+  * \param  UARTx: Select the UART peripheral. \ref UART_Declaration
+  * \param  UART_FLAG: specifies the flag to check.
+  *         This parameter can be one of the following values:
+  *         \arg UART_FLAG_RX_DATA_AVA: rx data is avaliable.
+  *         \arg UART_FLAG_RX_OVERRUN: rx overrun.
+  *         \arg UART_FLAG_PARTY_ERR: parity error.
+  *         \arg UART_FLAG_FRAME_ERR: UARTx frame error.
+  *         \arg UART_FLAG_BREAK_ERR: UARTx break error.
+  *         \arg UART_FLAG_TX_FIFO_EMPTY: tx FIFO is empty.
+  *         \arg UART_FLAG_TX_EMPTY: tx FIFO and tx shift reg are both empty.
+  *         \arg UART_FLAG_RX_FIFO_ERR: rx FIFO error.
+  *         \arg UART_FLAG_RX_IDLE.
+  *         \arg UART_FLAG_CTS_TOGGLE: CTS toggle.
+  * \return The new state of UART_FLAG (SET or RESET).
+  */
+FlagStatus UART_GetFlagStatus(UART_TypeDef *UARTx, uint32_t UART_FLAG)
+{
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+    assert_param(IS_UART_GET_FLAG(UART_FLAG));
+
+    FlagStatus bitstatus = RESET;
+
+    if (UART_FLAG == UART_FLAG_RX_IDLE)
+    {
+        if (UARTx->UART_RX_TIMEOUT_STS & BIT(0))
+        {
+            bitstatus = SET;
+        }
+    }
+#if (UART_SUPPORT_TX_THRESHOLD == 1)
+    else if (UART_FLAG == UART_FLAG_TX_THD)
+    {
+        if (UARTx->UART_TX_THD_INT & BIT(0))
+        {
+            bitstatus = SET;
+        }
+    }
+#endif
+#if (UART_SUPPORT_TX_DONE == 1)
+    else if (UART_FLAG == UART_FLAG_TX_DONE)
+    {
+        if (UARTx->UART_TXDONE_INT & BIT(0))
+        {
+            bitstatus = SET;
+        }
+    }
+#endif
+#if (UART_SUPPORT_CTS_TOGGLE == 1)
+    else if (UART_FLAG == UART_FLAG_CTS_TOGGLE)
+    {
+        if (UARTx->UART_CTRL0 & BIT(8))
+        {
+            bitstatus = SET;
+        }
+    }
+#endif
+    else
+    {
+        if (UART_GetLineStatus(UARTx) & UART_FLAG)
+        {
+            bitstatus = SET;
+        }
+    }
+
+    return bitstatus;
+}
+
+/**
+  * \brief  Get line status.
+  * \param  UARTx: Select the UART peripheral. \ref UART_Declaration
+  * \return Line status.
+  */
+uint8_t UART_GetLineStatus(UART_TypeDef *UARTx)
+{
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+
+    return (uint8_t)(UARTx->UART_LSR & (0x000000FF));
+}
+
+/**
+ * \brief   Send one byte of data.
+ * \param   UARTx: Select the UART peripheral. \ref UART_Declaration
+ * \param   data: Byte data to send.
+ * \return  None.
+ */
+void UART_SendByte(UART_TypeDef *UARTx, uint8_t data)
+{
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+
+    UARTx->UART_RBR_THR = data;
+
+    return;
+}
+
+#if (UART_SUPPORT_HALF_WORD == 1)
+/**
+ * \brief   Send half word of data.
+ * \param   UARTx: Select the UART peripheral. \ref UART_Declaration
+ * \param   data: Byte data to send.
+ * \return  None.
+ */
+void UART_SendHalfWord(UART_TypeDef *UARTx, uint16_t data)
+{
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+
+    UARTx->UART_RBR_THR = data;
+
+    return;
+}
+#endif
+
+/**
+ * \brief   Read a byte of data from UART RX FIFO.
+ * \param   UARTx: Select the UART peripheral. \ref UART_Declaration
+ * \return  Which byte data has been read.
+ */
+uint8_t UART_ReceiveByte(UART_TypeDef *UARTx)
+{
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+
+    return (uint8_t)(UARTx->UART_RBR_THR);
+}
+
+#if (UART_SUPPORT_HALF_WORD == 1)
+/**
+ * \brief   Read a byte of data from UART RX FIFO.
+ * \param   UARTx: Select the UART peripheral. \ref UART_Declaration
+ * \return  Which byte data has been read.
+ */
+uint8_t UART_ReceiveHalfWord(UART_TypeDef *UARTx)
+{
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+
+    return (uint16_t)(UARTx->UART_RBR_THR);
+}
+#endif
+
+/**
+ * \brief   Get interrupt identifier of the selected UART peripheral.
+ * \param   UARTx: Select the UART peripheral. \ref UART_Declaration
+ * \return  The interrupt identifier value.
+ *          This return value can be one or a combination of the following:
+ *          \retval UART_INT_ID_LINE_STATUS: Rx line status interrupt ID.
+ *          \retval UART_INT_ID_RX_LEVEL_REACH: Rx data available or trigger level reached interrupt ID.
+ *          \retval UART_INT_ID_RX_DATA_TIMEOUT: Rx FIFO data timeout interrupt ID.
+ *          \retval UART_INT_ID_TX_FIFO_EMPTY: Tx FIFO empty interrupt ID.
+ *          \retval UART_INT_ID_MODEM_STATUS: Modem status interrupt ID.
+ */
+uint16_t UART_GetIID(UART_TypeDef *UARTx)
+{
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+
+    return (uint16_t)(UARTx->UART_IIR_FCR & (0x0000000E));
+}
+
+#if (UART_SUPPORT_CLEAR_TX_FIFO == 1)
+/**
+ * \brief   Clear Tx FIFO of the selected UART peripheral.
+ * \param   UARTx: Select the UART peripheral. \ref UART_Declaration
+ * \return  None.
+ */
+void UART_ClearTxFIFO(UART_TypeDef *UARTx)
+{
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+
+    UARTx->UART_IIR_FCR = (((UARTx->UART_STSR & BIT24) >> 21) | \
+                           ((UARTx->UART_STSR & 0x7C000000) >> 18) | \
+                           ((UARTx->UART_STSR & BIT25) >> 25) | \
+                           FCR_CLEAR_TX_FIFO_SET);
+
+    return;
+}
+#endif
+
+/**
+ * \brief   Clear Rx FIFO of the selected UART peripheral.
+ * \param   UARTx: Select the UART peripheral. \ref UART_Declaration
+ * \return  None.
+ */
+void UART_ClearRxFIFO(UART_TypeDef *UARTx)
+{
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+
+    UARTx->UART_IIR_FCR = (((UARTx->UART_STSR & BIT24) >> 21) | \
+                           ((UARTx->UART_STSR & 0x7C000000) >> 18) | \
+                           ((UARTx->UART_STSR & BIT25) >> 25) | \
+                           FCR_CLEAR_RX_FIFO_SET);
+
+    return;
+}
+
+/**
+ * \brief   Get the data length in Tx FIFO of the selected UART peripheral.
+ * \param   UARTx: Select the UART peripheral. \ref UART_Declaration
+ * \return  Data length in UART TX FIFO.
+ */
+uint8_t UART_GetTxFIFODataLen(UART_TypeDef *UARTx)
+{
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+
+    return (uint8_t)(UARTx->UART_RXTX_FIFO_WL & 0x1F);
+}
+
+/**
+ * \brief   Get the data length in Rx FIFO of the selected UART peripheral.
+ * \param   UARTx: Select the UART peripheral. \ref UART_Declaration
+ * \return  Data length in UART RX FIFO.
+ */
+uint8_t UART_GetRxFIFODataLen(UART_TypeDef *UARTx)
+{
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+
+    return (uint8_t)((UARTx->UART_RXTX_FIFO_WL >> 8) & 0x3F);
+}
+
+/**
+ * \brief    Enable/Disable DMA mode on UART side.
+ * \param    UARTx: Select the UART peripheral. \ref UART_Declaration
+ * \param    NewState: Enable or disable UART DMA mode.
+ *           This parameter can be one of the following values:
+ *           \arg true: Enable UART DMA mode.
+ *           \arg false: Disable UART DMA mode.
+ * \return   None.
+ */
+void UART_TxDMACmd(UART_TypeDef *UARTx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+
+    UART_MISCR_TypeDef uart_0x28 = {.d32 = UARTx->UART_MISCR};
+    uart_0x28.b.txdma_en = NewState;
+    UARTx->UART_MISCR = uart_0x28.d32;
+}
+
+/**
+ * \brief    Enable/Disable DMA mode on UART side.
+ * \param    UARTx: Select the UART peripheral. \ref UART_Declaration
+ * \param    NewState: Enable or disable UART DMA mode.
+ *           This parameter can be one of the following values:
+ *           \arg true: Enable UART DMA mode.
+ *           \arg false: Disable UART DMA mode.
+ * \return   None.
+ */
+void UART_RxDMACmd(UART_TypeDef *UARTx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+
+    UART_MISCR_TypeDef uart_0x28 = {.d32 = UARTx->UART_MISCR};
+    uart_0x28.b.rxdma_en = NewState;
+    UARTx->UART_MISCR = uart_0x28.d32;
+}
+
+void UART_ClearINT(UART_TypeDef *UARTx, uint32_t UART_FLAG)
+{
+    if (UART_FLAG == UART_FLAG_RX_IDLE)
+    {
+        UART_RX_TIMEOUT_TypeDef uart_0x40 = {.d32 = UARTx->UART_RX_TIMEOUT};
+        UART_RX_TIMEOUT_STS_TypeDef uart_0x44 = {.d32 = UARTx->UART_RX_TIMEOUT_STS};
+
+        uart_0x44.b.rxidle_timeout_int_sts = 1;
+        UARTx->UART_RX_TIMEOUT_STS = uart_0x44.d32;
+
+        uart_0x40.b.rxidle_timeout_en = 1;
+        UARTx->UART_RX_TIMEOUT = uart_0x40.d32;
+    }
+
+#if (UART_SUPPORT_CTS_TOGGLE == 1)
+    if (UART_FLAG == UART_FLAG_CTS_TOGGLE)
+    {
+        UART_CTRL0_TypeDef uart_0x10 = {.d32 = UARTx->UART_CTRL0};
+        uart_0x10.b.cts_tog_int_sts = 1;
+        UARTx->UART_CTRL0 = uart_0x10.d32;
+    }
+#endif
+}
+
+#if (UART_SUPPORT_CTS_TOGGLE == 1)
+/**
+ * \brief   Get the CTS level of UART.
+ * \param   UARTx: Select the UART peripheral. \ref UART_Declaration
+ * \return  The level of CTS.
+ */
+uint8_t UART_GetCTSLevel(UART_TypeDef *UARTx)
+{
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+
+    if (UARTx->UART_CTRL0 & BIT(6))
+    {
+        return SET;
+    }
+    else
+    {
+        return RESET;
+    }
+}
+#endif
+
+#if (UART_SUPPORT_RAP_FUNCTION == 1)
+bool UART_RAPModeCmd(UART_TypeDef *UARTx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+
+    if (UART_IsSupportRAP(UARTx) == 0)
+    {
+        return false;
+    }
+
+    UART_RAP_CTRL_TypeDef uart_0x68 = {.d32 = UARTx->UART_RAP_CTRL};
+    uart_0x68.b.uart_rap_mode = NewState;
+    UARTx->UART_RAP_CTRL = uart_0x68.d32;
+
+    return true;
+}
+
+#endif
+
+void UART_TxOnlyModeCmd(UART_TypeDef *UARTx, FunctionalState NewState)
+{
+    /* Set tx only mode */
+    UART_STSR_TypeDef uart_0x20 = {.d32 = UARTx->UART_STSR};
+    uart_0x20.b.reset_rcv = NewState;
+    UARTx->UART_STSR = uart_0x20.d32;
+
+    return;
+}
diff --git a/bee/drivers/usb/CMakeLists.txt b/bee/drivers/usb/CMakeLists.txt
new file mode 100644
index 00000000..dfee95a8
--- /dev/null
+++ b/bee/drivers/usb/CMakeLists.txt
@@ -0,0 +1,4 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+add_subdirectory_ifdef(CONFIG_REALTEK_BEE_USING_USB_HAL usb_hal)
diff --git a/bee/drivers/usb/Kconfig b/bee/drivers/usb/Kconfig
new file mode 100644
index 00000000..d484aa60
--- /dev/null
+++ b/bee/drivers/usb/Kconfig
@@ -0,0 +1,12 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config REALTEK_BEE_USB
+	bool "Realtek Bee MCU usb driver"
+	default n
+
+config REALTEK_BEE_USING_USB_HAL
+	bool "Realtek Bee usb hal library"
+	default y if REALTEK_BEE_USB
+	help
+		This option enables the usb hal library for Realtek Bee MCU.
diff --git a/bee/drivers/usb/usb_hal/CMakeLists.txt b/bee/drivers/usb/usb_hal/CMakeLists.txt
new file mode 100644
index 00000000..1a3da872
--- /dev/null
+++ b/bee/drivers/usb/usb_hal/CMakeLists.txt
@@ -0,0 +1,4 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+add_subdirectory(lib)
diff --git a/bee/drivers/usb/usb_hal/lib/CMakeLists.txt b/bee/drivers/usb/usb_hal/lib/CMakeLists.txt
new file mode 100644
index 00000000..800cf3c3
--- /dev/null
+++ b/bee/drivers/usb/usb_hal/lib/CMakeLists.txt
@@ -0,0 +1,4 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+add_subdirectory_ifdef(CONFIG_SOC_SERIES_RTL87X2G rtl87x2g)
diff --git a/bee/drivers/usb/usb_hal/lib/rtl87x2g/CMakeLists.txt b/bee/drivers/usb/usb_hal/lib/rtl87x2g/CMakeLists.txt
new file mode 100644
index 00000000..970aee1e
--- /dev/null
+++ b/bee/drivers/usb/usb_hal/lib/rtl87x2g/CMakeLists.txt
@@ -0,0 +1,2 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
diff --git a/bee/drivers/utils/rtl_utils.h b/bee/drivers/utils/rtl_utils.h
new file mode 100644
index 00000000..bd362b9d
--- /dev/null
+++ b/bee/drivers/utils/rtl_utils.h
@@ -0,0 +1,112 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *                         Define to prevent recursive inclusion
+ *============================================================================*/
+#ifndef RTL_UTILS_H
+#define RTL_UTILS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*============================================================================*
+ *                         Header Files
+ *============================================================================*/
+#include <stdint.h>
+#include <stdbool.h>
+#include "bitops.h"
+#include "cpu_setting.h"
+
+/*============================================================================*
+ *                         Types
+*============================================================================*/
+/** \defgroup UTILS       UTILS
+  * \brief
+  * \{
+  */
+
+/** \defgroup UTILS_Exported_Constants UTILS Exported Constants
+  * \brief
+  * \{
+  */
+
+/**
+ * \defgroup    ITStatus ITStatus
+ * \{
+ * \ingroup     UTILS_Exported_Constants
+ */
+typedef enum
+{
+    RESET = 0,      //!< Define the constant RESET and assign it the value 0.
+    SET = !RESET    //!< Define the constant SET and assign it the value 1.
+} FlagStatus, ITStatus;
+
+/** End of ITStatus
+  * \}
+  */
+
+/**
+ * \defgroup    FunctionalState FunctionalState
+ * \{
+ * \ingroup     UTILS_Exported_Constants
+ */
+typedef enum
+{
+    DISABLE = 0,         //!< Define the constant DISABLE and assign it the value 0.
+    ENABLE = !DISABLE    //!< Define the constant ENABLE and assign it the value 1.
+} FunctionalState;
+
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) //!< Check if the input parameter is valid.
+
+/** End of FunctionalState
+  * \}
+  */
+
+/** End of UTILS_Exported_Constants
+  * \}
+  */
+
+/*============================================================================*
+ *                         Functions
+ *============================================================================*/
+/** \defgroup UTILS_Exported_Functions UTILS Exported Functions
+  * \brief
+  * \{
+  */
+
+/* Uncomment the line below to expanse the "assert_param" macro in the
+   Standard Peripheral Library drivers code */
+//#define USE_FULL_ASSERT
+
+/**
+  * \brief  The assert_param macro is used for function's parameters check.
+  * \param  expr: If expr is false, it calls assert_failed function which reports
+  *         the name of the source file and the source line number of the call
+  *         that failed. If expr is true, it returns no value.
+  *
+  */
+#ifdef USE_FULL_ASSERT
+#define assert_param(expr) ((expr) ? (void)0 : io_assert_failed((uint8_t *)__FILE__, __LINE__))
+void io_assert_failed(uint8_t *file, uint32_t line);
+#else
+#define assert_param(expr) ((void)0)
+#endif /* USE_FULL_ASSERT */
+
+/** End of UTILS_Exported_Functions
+  * \}
+  */
+
+/** End of UTILS
+  * \}
+  */
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RTL_UTILS_H */
+
diff --git a/bee/drivers/wdt/CMakeLists.txt b/bee/drivers/wdt/CMakeLists.txt
new file mode 100644
index 00000000..329920e8
--- /dev/null
+++ b/bee/drivers/wdt/CMakeLists.txt
@@ -0,0 +1,6 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_include_directories(inc)
+
+add_subdirectory(src)
diff --git a/bee/drivers/wdt/Kconfig b/bee/drivers/wdt/Kconfig
new file mode 100644
index 00000000..c621a5d1
--- /dev/null
+++ b/bee/drivers/wdt/Kconfig
@@ -0,0 +1,18 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config REALTEK_BEE_AON_WDT
+	bool "Realtek Bee MCU aon watchdog timer"
+	default n
+
+	help
+	  This option enables the aon wdt driver for Realtek Bee family of
+	  processors.
+
+config REALTEK_BEE_CORE_WDT
+	bool "Realtek Bee MCU core watchdog timer"
+	default n
+
+	help
+	  This option enables the core wdt driver for Realtek Bee family of
+	  processors.
diff --git a/bee/drivers/wdt/inc/hal_wdt.h b/bee/drivers/wdt/inc/hal_wdt.h
new file mode 100644
index 00000000..92560efc
--- /dev/null
+++ b/bee/drivers/wdt/inc/hal_wdt.h
@@ -0,0 +1,241 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: LicenseRef-Realtek-5-Clause
+ */
+
+/*============================================================================*
+ *               Define to prevent recursive inclusion
+ *============================================================================*/
+#ifndef _HAL_WDT_H
+#define _HAL_WDT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*============================================================================*
+ *                               Header Files
+*============================================================================*/
+#include <stdint.h>
+#include <stdbool.h>
+
+/** @addtogroup HAL_WDT HAL WDT
+  * @brief HAL WDT function module
+  * @{
+  */
+
+/*============================================================================*
+ *                         Types
+ *============================================================================*/
+/** @defgroup HAL_WDT_Exported_Types HAL WDT Exported Types
+  * @{
+  */
+
+/**
+ * \brief       WDT supported modes.
+ *
+ * \ingroup     HAL_WDT_Exported_Types
+ */
+typedef enum _WDT_MODE
+{
+    WDT_MODE_RESET_ALL = 0,               /**< Reset all. */
+    WDT_MODE_RESET_ALL_EXCEPT_AON = 1,    /**< Reset all except RTC and some AON register. */
+    WDT_MODE_INTERRUPT_CPU = 2,           /**< Interrupt CPU. */
+    WDT_MODE_UNKNOWN = 3                  /**< Mode unknown */
+} T_WDT_MODE;
+
+#define IS_WDT_MODE(MODE) ((MODE) < WDT_MODE_UNKNOWN)
+
+/**
+ * \brief       This enum define the API return type.
+ *
+ * \ingroup     HAL_WDT_Exported_Types
+ */
+typedef enum
+{
+    HAL_WDT_STATUS_INVALID_PARAMETER = -1,       /**<  A wrong parameter is given. */
+    HAL_WDT_STATUS_OK = 0                        /**<  No error occurred during the function call. */
+} T_WDT_STATUS;
+
+/**
+ * \brief       This enum define WDT RESET TYPE for debug
+ *
+ * \ingroup     HAL_WDT_Exported_Types
+ */
+
+/**
+ * \brief       Define the type of wdt reset callback.
+ *
+ * \ingroup     HAL_WDT_Exported_Types
+ */
+
+
+/** End of group HAL_WDT_Exported_Types
+  * @}
+  */
+
+/*============================================================================*
+ *                         Functions
+ *============================================================================*/
+
+/** @defgroup HAL_WDT_API_Exported_Functions WDT Api
+  * @{
+  */
+
+/**
+ * hal_wdt.h
+ *
+ * \brief  Start wdt.
+ *
+ * \param[in] mode: wdt reset mode \ref T_WDT_MODE.
+ * \param[in] timeout_ms: wdt timeout.
+ *
+ * \return T_WDT_STATUS: wdt status.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void wdt_demo(void)
+ * {
+ *     hal_wdt_start(RESET_ALL, 4000);
+ * }
+ * \endcode
+ */
+T_WDT_STATUS hal_wdt_start(T_WDT_MODE mode, uint32_t timeout_ms);
+
+/**
+ * hal_wdt.h
+ *
+ * \brief  Disable wdt.
+ * \return T_WDT_STATUS: wdt status.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void wdt_demo(void)
+ * {
+ *     hal_wdt_stop();
+ * }
+ * \endcode
+ */
+T_WDT_STATUS hal_wdt_stop(void);
+
+/**
+ * hal_wdt.h
+ *
+ * \brief  Check whether wdt is enable.
+ * \return The result of wdt.
+ * \retval true: wdt is enable.
+ * \retval false: wdt is disable.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void wdt_demo(void)
+ * {
+ *     if (hal_wdt_is_enable() == true)
+ *     {
+ *
+ *     }
+ * }
+ * \endcode
+ */
+bool hal_wdt_is_enable(void);
+
+/**
+ * hal_wdt.h
+ *
+ * \brief  Get wdt reset mode.
+ * \return T_WDT_MODE: wdt reset mode \ref T_WDT_MODE.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void wdt_demo(void)
+ * {
+ *     T_WDT_MODE mode = hal_wdt_get_mode();
+ * }
+ * \endcode
+ */
+T_WDT_MODE hal_wdt_get_mode(void);
+
+/**
+ * hal_wdt.h
+ *
+ * \brief  Get wdt current timeout value.
+ * \return current timeout value.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void wdt_demo(void)
+ * {
+ *     uint32_t timeout = hal_wdt_get_timeout_ms();
+ * }
+ * \endcode
+ */
+uint32_t hal_wdt_get_timeout_ms(void);
+
+/**
+ * hal_wdt.h
+ *
+ * \brief  Change wdt timeout value.
+ * \param[in] timeout_ms: wdt new timeout value.
+ * \return T_WDT_STATUS: wdt status.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void wdt_demo(void)
+ * {
+ *     hal_wdt_change_timeout_period(4000);
+ * }
+ * \endcode
+ */
+T_WDT_STATUS hal_wdt_change_timeout_period(uint32_t timeout_ms);
+
+/**
+ * hal_wdt.h
+ *
+ * \brief  Change wdt mode.
+ * \param[in] mode: wdt new reset mode \ref T_WDT_MODE.
+ * \return T_WDT_STATUS: wdt status.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void wdt_demo(void)
+ * {
+ *     hal_wdt_change_mode(RESET_ALL);
+ * }
+ * \endcode
+ */
+T_WDT_STATUS hal_wdt_change_mode(T_WDT_MODE mode);
+
+/**
+ * hal_wdt.h
+ *
+ * \brief  Kick wdt.
+ * \return T_WDT_STATUS: wdt status.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ *
+ * void wdt_demo(void)
+ * {
+ *     hal_wdt_kick();
+ * }
+ * \endcode
+ */
+T_WDT_STATUS hal_wdt_kick(void);
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+/** @} */ /* End of group HAL_WDT_API_Exported_Functions */
+/** @} */ /* End of group HAL_WDT */
+#endif
diff --git a/bee/drivers/wdt/inc/rtl_aon_wdt.h b/bee/drivers/wdt/inc/rtl_aon_wdt.h
new file mode 100644
index 00000000..54c4690c
--- /dev/null
+++ b/bee/drivers/wdt/inc/rtl_aon_wdt.h
@@ -0,0 +1,105 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *               Define to prevent recursive inclusion
+ *============================================================================*/
+#ifndef RTL_AON_WDT_H
+#define RTL_AON_WDT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*============================================================================*
+ *                               Header Files
+*============================================================================*/
+#include "utils/rtl_utils.h"
+#include "wdt/inc/rtl_wdt.h"
+#if defined (CONFIG_SOC_SERIES_RTL87X2G)
+#include "wdt/src/rtl87x2g/rtl_aon_wdt_def.h"
+#endif
+
+/** \defgroup AON_WDT         AON_WDT
+  * \brief
+  * \{
+  */
+
+/*============================================================================*
+ *                         Functions
+ *============================================================================*/
+/** \defgroup AON_WDT_Exported_Functions AON_WDT Exported Functions
+  * \{
+  */
+
+/**
+ * \brief  Start AON WDT.
+ *
+ * \param[in] AON_WDTx  Select the AON_WDT peripheral. Refer to \ref AON_WDT_Declaration.
+ * \param[in] TimeMs    AON WDT Timeout Time. Unit: ms.
+ * \param[in] Mode      Refer to \ref WDTMode_TypeDef. If the Reset AON WDT operation is not performed within the Timeout period,
+ *                       the configured mode operation will be executed.
+ *
+ * \return  true or false.
+ *          - true: AON WDT mode set successfully, enabling the function..
+ *          - false: If set to interrupt mode, it will return false.
+ */
+bool AON_WDT_Start(AON_WDT_TypeDef *AON_WDTx, uint32_t TimeMs, WDTMode_TypeDef Mode);
+
+/**
+ * \brief  Disable AON WDT.
+ *
+ * \param[in] AON_WDTx  Select the AON_WDT peripheral. Refer to \ref AON_WDT_Declaration.
+ */
+void AON_WDT_Disable(AON_WDT_TypeDef *AON_WDTx);
+
+/**
+ * \brief  Kick AON WDT to restart WDT.
+ *
+ * \param[in] AON_WDTx  Select the AON_WDT peripheral. Refer to \ref AON_WDT_Declaration
+ */
+void AON_WDT_Kick(AON_WDT_TypeDef *AON_WDTx);
+
+/**
+ * \brief  Is AON WDT enable.
+ *
+ * \param[in] AON_WDTx  Select the AON_WDT peripheral. Refer to \ref AON_WDT_Declaration.
+ *
+ * \return Is AON WDT enable or not
+ */
+bool AON_WDT_IsEnable(AON_WDT_TypeDef *AON_WDTx);
+
+/**
+ * \brief  Get AON WDT timeout.
+ *
+ * \param[in] AON_WDTx  Select the AON_WDT peripheral. Refer to \ref AON_WDT_Declaration.
+ *
+ * \return AON WDT timeout
+ */
+uint32_t AON_WDT_GetTimeoutMs(AON_WDT_TypeDef *AON_WDTx);
+
+/**
+ * \brief  Get AON WDT mode.
+ *
+ * \param[in] AON_WDTx  Select the AON_WDT peripheral. Refer to \ref AON_WDT_Declaration.
+ *
+ * \return AON WDT mode
+ */
+WDTMode_TypeDef AON_WDT_GetMode(AON_WDT_TypeDef *AON_WDTx);
+
+/** End of AON_WDT_Exported_Functions
+  * \}
+  */
+
+/** End of AON_WDT
+  * \}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RTL_AON_WDT_H */
diff --git a/bee/drivers/wdt/inc/rtl_lpwdt.h b/bee/drivers/wdt/inc/rtl_lpwdt.h
new file mode 100644
index 00000000..1060c206
--- /dev/null
+++ b/bee/drivers/wdt/inc/rtl_lpwdt.h
@@ -0,0 +1,116 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *               Define to prevent recursive inclusion
+ *============================================================================*/
+#ifndef RTL_LPWDT_H
+#define RTL_LPWDT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*============================================================================*
+ *                               Header Files
+*============================================================================*/
+#include "utils/rtl_utils.h"
+#include "wdt/inc/rtl_wdt.h"
+#if defined (CONFIG_SOC_SERIES_RTL87X2J)
+#include "wdt/src/device/rtl87x2j/rtl_lpwdt_def.h"
+#elif defined (CONFIG_SOC_SERIES_RTL87X3D)
+#include "wdt/src/device/rtl87x3d/rtl_lpwdt_def.h"
+#elif defined (CONFIG_SOC_SERIES_RTL87X3E)
+#include "wdt/src/device/rtl87x3e/rtl_lpwdt_def.h"
+#elif defined (CONFIG_SOC_SERIES_RTL87X3J)
+#include "wdt/src/device/rtl87x3j/rtl_lpwdt_def.h"
+#endif
+
+/** \defgroup LPWDT         LPWDT
+  * \brief
+  * \{
+  */
+
+/*============================================================================*
+ *                         Functions
+ *============================================================================*/
+/** \defgroup LPWDT_Exported_Functions LPWDT Exported Functions
+  * \{
+  */
+
+/**
+  * \brief  Start LPWDT.
+  * \param  LPWDTx \ref LPWDT_Declaration
+  * \param  TimeMs
+  * \param  Mode \ref WDTMode_Typedef
+  * \return true or false.
+  */
+bool LPWDT_Start(LPWDT_TypeDef *LPWDTx, uint32_t TimeMs, WDTMode_TypeDef Mode);
+
+/**
+  * \brief  Enable LPWDT.
+  * \param  LPWDTx \ref LPWDT_Declaration
+  * \return None.
+  */
+void LPWDT_Enable(LPWDT_TypeDef *LPWDTx);
+
+/**
+  * \brief  Disable LPWDT.
+  * \param  LPWDTx \ref LPWDT_Declaration
+  * \return None.
+  */
+void LPWDT_Disable(LPWDT_TypeDef *LPWDTx);
+
+/**
+  * \brief  Kick LPWDT to restart WDT.
+  * \param  LPWDTx \ref LPWDT_Declaration
+  * \return None.
+  */
+void LPWDT_Kick(LPWDT_TypeDef *LPWDTx);
+
+/**
+  * \brief  Is LPWDT enable.
+  * \param  LPWDTx \ref LPWDT_Declaration
+  * \return Is LPWDT enable or not
+  */
+bool LPWDT_IsEnable(LPWDT_TypeDef *LPWDTx);
+
+/**
+  * \brief  Get LPWDT timeout.
+  * \param  LPWDTx \ref LPWDT_Declaration
+  * \return LPWDT timeout
+  */
+uint32_t LPWDT_GetTimeoutMs(LPWDT_TypeDef *LPWDTx);
+
+/**
+  * \brief  Get LPWDT mode.
+  * \param  LPWDTx \ref LPWDT_Declaration
+  * \return LPWDT mode
+  */
+WDTMode_TypeDef LPWDT_GetMode(LPWDT_TypeDef *LPWDTx);
+
+#if (LPWDT_SUPPORT_GET_CURRENT_COUNTER == 1)
+/**
+  * \brief  Get LPWDT current Count.
+  * \param  LPWDTx \ref LPWDT_Declaration
+  * \return Current Count
+  */
+uint32_t LPWDT_GetCurrentCount(LPWDT_TypeDef *LPWDTx);
+#endif
+
+/** End of LPWDT_Exported_Functions
+  * \}
+  */
+
+/** End of LPWDT
+  * \}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RTL_LPWDT_H */
diff --git a/bee/drivers/wdt/inc/rtl_wdt.h b/bee/drivers/wdt/inc/rtl_wdt.h
new file mode 100644
index 00000000..5b0d58d2
--- /dev/null
+++ b/bee/drivers/wdt/inc/rtl_wdt.h
@@ -0,0 +1,194 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *               Define to prevent recursive inclusion
+ *============================================================================*/
+#ifndef RTL_WDT_H
+#define RTL_WDT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*============================================================================*
+ *                               Header Files
+*============================================================================*/
+#include "utils/rtl_utils.h"
+#if defined (CONFIG_SOC_SERIES_RTL87X2G)
+#include "wdt/src/device/rtl87x2g/rtl_wdt_def.h"
+#elif defined (CONFIG_SOC_SERIES_RTL87X3E)
+#include "wdt/src/device/rtl87x3e/rtl_wdt_def.h"
+#elif defined (CONFIG_SOC_SERIES_RTL87X3D)
+#include "wdt/src/device/rtl87x3d/rtl_wdt_def.h"
+#elif defined (CONFIG_SOC_SERIES_RTL87X2J)
+#include "wdt/src/device/rtl87x2j/rtl_wdt_def.h"
+#elif defined (CONFIG_SOC_SERIES_RTL87X3J)
+#include "wdt/src/device/rtl87x3j/rtl_wdt_def.h"
+#endif
+
+/** \defgroup WDT         WDT
+  * \brief
+  * \{
+  */
+
+/*============================================================================*
+ *                         Types
+ *============================================================================*/
+/** \defgroup WDT_Exported_Types WDT Exported Types
+  * \brief
+  * \{
+  */
+
+/**
+  * \brief       WDT Mode structure definition.
+  *
+  * \ingroup     WDT_Exported_Types
+  */
+typedef enum
+{
+    RESET_ALL = 0,               /**< Reset all. */
+    RESET_ALL_EXCEPT_AON = 1,    /**< Reset all except RTC and some AON register. */
+    INTERRUPT_CPU = 2,           /**< Interrupt CPU. */
+    WDT_MODE_NUM = 3,            /**< Max number. */
+} WDTMode_TypeDef;
+
+#define IS_WDT_Mode(MODE) (((MODE) == RESET_ALL) || \
+                           ((MODE) == RESET_ALL_EXCEPT_AON) || \
+                           ((MODE) == INTERRUPT_CPU))
+
+/** End of group WDT_Exported_Types
+  * \}
+  */
+
+/*============================================================================*
+ *                         Functions
+ *============================================================================*/
+/** \defgroup WDT_Exported_Functions WDT Exported Functions
+  * \{
+  */
+
+/**
+  * \brief  Start WDT. This function will enable WDT clock, set and start WDT.
+  * \param  TimeMs.
+  * \param  Mode \ref WDTMode_TypeDef.
+  * \return true or false.
+  */
+bool WDT_Start(uint32_t TimeMs, WDTMode_TypeDef Mode);
+
+/**
+  * \brief  Enable WDT.
+  * \return None.
+  */
+void WDT_Enable(void);
+
+/**
+  * \brief  Disable WDT.
+  * \return None.
+  */
+void WDT_Disable(void);
+
+/**
+  * \brief  Kick WDT to restart WDT.
+  * \return None.
+  */
+void WDT_Kick(void);
+
+/**
+  * \brief  Is WDT enable.
+  * \return Is WDT enable or not
+  */
+bool WDT_IsEnable(void);
+
+/**
+  * \brief  Get WDT timeout.
+  * \return WDT timeout
+  */
+uint32_t WDT_GetTimeoutMs(void);
+
+/**
+  * \brief  Get WDT mode.
+  * \return WDT mode
+  */
+WDTMode_TypeDef WDT_GetMode(void);
+
+#if (WDT_SUPPORT_AUTO_CLOCK == 1)
+void WDT_ClockAutoModeCmd(FunctionalState Newstate);
+#endif
+
+#if (WDT_SUPPORT_GET_CURRENT_COUNTER == 1)
+/**
+  * \brief  Get WDT current count.
+  * \return Current count
+  */
+uint32_t WDT_GetCurrentCount(void);
+#endif
+
+/**
+  * \brief  Clear WDT interrupt pending bit.
+  * \return None
+  */
+void WDT_ClearINTPendingBit(void);
+
+#if (WDT_SUPPORT_CNT_LIMIT2 == 1)
+/**
+  * \brief  Set WDT reset time.
+  * \param  TimeMs.
+  * \return True or false.
+  */
+bool WDT_SetResetTime(uint32_t TimeMs);
+
+/**
+  * \brief  Get reset time(ms).
+  * \return Reset time.
+  */
+uint32_t WDT_GetResetTimeMs(void);
+
+/**
+  * \brief  Start WDT with interrupt time and reset time.
+  * \param  TimeMs.
+  * \param  Mode \ref WDTMode_TypeDef.
+  * \return true or false.
+  */
+bool WDT_StartWithResetTime(uint32_t InterruptTimeMs, uint32_t ResetTimeMs, WDTMode_TypeDef Mode);
+#endif
+
+#if (WDT_SUPPORT_RECORD_TIMEOUT == 1)
+/**
+  * \brief  Get last WDT timeout mode.
+  * \return Timeout mode \ref WDTMode_TypeDef.
+  */
+WDTMode_TypeDef WDT_GetLastTimeoutMode(void);
+
+/**
+  * \brief  Clear last WDT timeout mode.
+  */
+void WDT_ClearLastTimeoutMode(void);
+
+/**
+  * \brief  Get WDT timeout flag.
+  * \return true: WDT timeout, false: WDT not timeout.
+  */
+bool WDT_GetTimeoutFlag(void);
+
+/**
+  * \brief  Clear WDT timeout flag.
+  */
+void WDT_ClearTimeoutFlag(void);
+#endif
+/** End of WDT_Exported_Functions
+  * \}
+  */
+
+/** End of WDT
+  * \}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RTL_WDT_H */
diff --git a/bee/drivers/wdt/src/CMakeLists.txt b/bee/drivers/wdt/src/CMakeLists.txt
new file mode 100644
index 00000000..dd5e359a
--- /dev/null
+++ b/bee/drivers/wdt/src/CMakeLists.txt
@@ -0,0 +1,4 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+add_subdirectory(device)
diff --git a/bee/drivers/wdt/src/device/CMakeLists.txt b/bee/drivers/wdt/src/device/CMakeLists.txt
new file mode 100644
index 00000000..034df6a1
--- /dev/null
+++ b/bee/drivers/wdt/src/device/CMakeLists.txt
@@ -0,0 +1,6 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+add_soc_series_subdir(rtl8752h)
+add_soc_series_subdir(rtl87x2g)
+add_soc_series_subdir(rtl87x2j)
diff --git a/bee/drivers/wdt/src/device/rtl8752h/CMakeLists.txt b/bee/drivers/wdt/src/device/rtl8752h/CMakeLists.txt
new file mode 100644
index 00000000..4895c71d
--- /dev/null
+++ b/bee/drivers/wdt/src/device/rtl8752h/CMakeLists.txt
@@ -0,0 +1,9 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_library()
+
+zephyr_library_sources_ifdef(CONFIG_REALTEK_BEE_AON_WDT rtl876x_aon_wdg.c)
+zephyr_library_sources_ifdef(CONFIG_REALTEK_BEE_CORE_WDT rtl876x_wdg.c)
+
+zephyr_include_directories(.)
diff --git a/bee/drivers/wdt/src/device/rtl8752h/rtl876x_aon_wdg.c b/bee/drivers/wdt/src/device/rtl8752h/rtl876x_aon_wdg.c
new file mode 100644
index 00000000..e02c1110
--- /dev/null
+++ b/bee/drivers/wdt/src/device/rtl8752h/rtl876x_aon_wdg.c
@@ -0,0 +1,146 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "rtl876x.h"
+#include "rtl876x_aon_wdg.h"
+#include "rtl876x_rtc.h"
+
+
+#define REG_RTC_FAST_WRITE_BASE_ADDR    (0x40000100UL)
+#define REG_RTC_FAST_WDATA              (0x400001f0UL)
+#define REG_RTC_FAST_ADDR               (0x400001f4UL)
+#define REG_RTC_WR_STROBE               (0x400001f8UL)
+
+/* Enable Write to CRT register */
+#define AON_WDG_EnableWriteCRT() AON_WDG_WriteReg((uint32_t)&AON_WDG->WP - SYSTEM_REG_BASE, AON_WDG->WP | BIT0)
+
+/* Disable Write to CRT register */
+#define AON_WDG_DisableWriteCRT() AON_WDG_WriteReg((uint32_t)&AON_WDG->WP - SYSTEM_REG_BASE, AON_WDG->WP & ~BIT0);
+
+/**
+  * @brief  Fast write RTC register.
+  * @param  offset: the offset of RTC register.
+  * @param  data: data which write to register.
+  * @retval None
+  */
+static void AON_WDG_WriteReg(uint32_t offset, uint32_t data)
+{
+    static bool is_called = false;
+
+    if (is_called == false)
+    {
+        *((volatile uint32_t *)0x40000014) |= BIT(9);//no need run this every time
+        is_called = true;
+    }
+
+    /* Write data */
+    *((volatile uint32_t *)REG_RTC_FAST_WDATA) = data;
+    /* Write RTC register address. Only offset */
+    *((volatile uint32_t *)REG_RTC_FAST_ADDR) = offset - REG_RTC_FAST_WRITE_BASE_ADDR;
+    *((volatile uint32_t *)REG_RTC_WR_STROBE) = 1;
+}
+
+void AON_WDG_Config(uint8_t reset_level, uint32_t comp, uint8_t cnt_ctl, uint8_t cnt_reload)
+{
+    AON_WDG_TypeDef aon_wdg;
+
+    aon_wdg.u.CRT = AON_WDG->u.CRT;
+
+    aon_wdg.u.CRT_BITS.RST_LVL = reset_level;
+    aon_wdg.u.CRT_BITS.COMP = comp;
+    aon_wdg.u.CRT_BITS.CNT_CTL = cnt_ctl;
+    aon_wdg.u.CRT_BITS.CNT_RELOAD = cnt_reload;
+
+    AON_WDG_EnableWriteCRT();
+    AON_WDG_WriteReg((uint32_t)&AON_WDG->u.CRT - SYSTEM_REG_BASE, aon_wdg.u.CRT);
+    AON_WDG_DisableWriteCRT();
+}
+
+void AON_WDG_ConfigResetLevel(uint8_t reset_level)
+{
+    AON_WDG_TypeDef aon_wdg;
+
+    aon_wdg.u.CRT = AON_WDG->u.CRT;
+    aon_wdg.u.CRT_BITS.RST_LVL = reset_level;
+
+    AON_WDG_EnableWriteCRT();
+    AON_WDG_WriteReg((uint32_t)&AON_WDG->u.CRT - SYSTEM_REG_BASE, aon_wdg.u.CRT);
+    AON_WDG_DisableWriteCRT();
+}
+
+void AON_WDG_ConfigComp(uint32_t comp)
+{
+    AON_WDG_TypeDef aon_wdg;
+
+    aon_wdg.u.CRT = AON_WDG->u.CRT;
+    aon_wdg.u.CRT_BITS.COMP = comp;
+
+    AON_WDG_EnableWriteCRT();
+    AON_WDG_WriteReg((uint32_t)&AON_WDG->u.CRT - SYSTEM_REG_BASE, aon_wdg.u.CRT);
+    AON_WDG_DisableWriteCRT();
+}
+
+void AON_WDG_ConfigCntCtl(uint8_t cnt_ctl)
+{
+    AON_WDG_TypeDef aon_wdg;
+
+    aon_wdg.u.CRT = AON_WDG->u.CRT;
+    aon_wdg.u.CRT_BITS.CNT_CTL = cnt_ctl;
+
+    AON_WDG_EnableWriteCRT();
+    AON_WDG_WriteReg((uint32_t)&AON_WDG->u.CRT - SYSTEM_REG_BASE, aon_wdg.u.CRT);
+    AON_WDG_DisableWriteCRT();
+}
+
+void AON_WDG_ConfigCntReload(uint8_t cnt_reload)
+{
+    AON_WDG_TypeDef aon_wdg;
+
+    aon_wdg.u.CRT = AON_WDG->u.CRT;
+    aon_wdg.u.CRT_BITS.CNT_RELOAD = cnt_reload;
+
+    AON_WDG_EnableWriteCRT();
+    AON_WDG_WriteReg((uint32_t)&AON_WDG->u.CRT - SYSTEM_REG_BASE, aon_wdg.u.CRT);
+    AON_WDG_DisableWriteCRT();
+}
+
+void AON_WDG_Enable(void)
+{
+    AON_WDG_TypeDef aon_wdg;
+
+    aon_wdg.u.CRT = AON_WDG->u.CRT;
+    aon_wdg.u.CRT_BITS.EN = 1;
+
+    AON_WDG_EnableWriteCRT();
+    AON_WDG_WriteReg((uint32_t)&AON_WDG->u.CRT - SYSTEM_REG_BASE, aon_wdg.u.CRT);
+    AON_WDG_DisableWriteCRT();
+}
+
+void AON_WDG_Disable(void)
+{
+    AON_WDG_TypeDef aon_wdg;
+
+    aon_wdg.u.CRT = AON_WDG->u.CRT;
+    aon_wdg.u.CRT_BITS.EN = 2;
+
+    AON_WDG_EnableWriteCRT();
+    AON_WDG_WriteReg((uint32_t)&AON_WDG->u.CRT - SYSTEM_REG_BASE, aon_wdg.u.CRT);
+    AON_WDG_DisableWriteCRT();
+}
+
+void AON_WDG_Restart(void)
+{
+    AON_WDG_WriteReg((uint32_t)&AON_WDG->CNT_CLR, 1);
+    AON_WDG_WriteReg((uint32_t)&AON_WDG->CNT_CLR, 0);
+}
+
+void AON_WDG_SystemReset(void)
+{
+    AON_WDG_Config(1, 1, 1, 0);
+    AON_WDG_Enable();
+
+    while (1); /* wait until reset */
+}
diff --git a/bee/drivers/wdt/src/device/rtl8752h/rtl876x_aon_wdg.h b/bee/drivers/wdt/src/device/rtl8752h/rtl876x_aon_wdg.h
new file mode 100644
index 00000000..0c08118c
--- /dev/null
+++ b/bee/drivers/wdt/src/device/rtl8752h/rtl876x_aon_wdg.h
@@ -0,0 +1,162 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _RTL876X_AON_WDG_H_
+#define _RTL876X_AON_WDG_H_
+
+#include <stdint.h>
+#include <rtl876x.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @addtogroup AON_WATCH_DOG AON_WATCH_DOG
+  * @brief AON Watch Dog driver module
+  * @{
+  */
+
+/** @defgroup AON_WATCH_DOG_Exported_Functions AON WATCH DOG Exported Functions
+  * @{
+  */
+
+/**
+ * \brief  Configure initialization parameters.
+ * \param[in]  reset_level: Specify the reset level.
+ *     This parameter can be 0 or 1.
+ *     \arg 0: Reset whole chip except partial AON and RTC.
+ *     \arg 1: Reset whole chip.
+ * \param[in]  comp: Set period in ms.
+ * \param[in]  cnt_ctl: Specify whether to continue counting in low power mode.
+ *     This parameter can be 0 or 1.
+ *     \arg 0: Stop count in low power mode.
+ *     \arg 1: Continue count in low power mode.
+ * \param[in]  cnt_reload: Specify whether to reload counter when exiting low power mode.
+ *     This parameter can be 0 or 1.
+ *     \arg 0: Not reload counter when exiting low power mode.
+ *     \arg 1: Reload counter when exiting low power mode.
+ * \return None.
+ */
+void AON_WDG_Config(uint8_t reset_level, uint32_t comp, uint8_t cnt_ctl, uint8_t cnt_reload);
+
+/**
+ * \brief  Configure Reset Level.
+ * \param[in]  reset_level: Specify the reset level.
+ *     This parameter can be 0 or 1.
+ *     \arg 0: Reset whole chip except partial AON and RTC.
+ *     \arg 1: Reset whole chip.
+ * \return None.
+ */
+void AON_WDG_ConfigResetLevel(uint8_t reset_level);
+
+/**
+ * \brief  Configure comp period of the AON Watch Dog.
+ * \param[in]  comp: Set period in ms.
+ * \return None.
+ */
+void AON_WDG_ConfigComp(uint32_t comp);
+
+/**
+ * \brief  Configure whether to continue counting in low power mode or not.
+ * \param[in]  cnt_ctl: Specify whether to continue counting in low power mode.
+ *     This parameter can be 0 or 1.
+ *     \arg 0: Stop count in low power mode.
+ *     \arg 1: Continue count in low power mode.
+ * \return None.
+ */
+void AON_WDG_ConfigCntCtl(uint8_t cnt_ctl);
+
+/**
+ * \brief  Configure whether to reload the counter when exiting low power mode or not.
+ * \param[in]  cnt_reload: Specify whether to reload counter when exiting low power mode.
+ *     This parameter can be 0 or 1.
+ *     \arg 0: Not reload counter when exiting low power mode.
+ *     \arg 1: Reload counter when exiting low power mode.
+ * \return None.
+ */
+void AON_WDG_ConfigCntReload(uint8_t cnt_reload);
+
+/**
+ * \brief  Enable the AON Watch Dog.
+ * \return None.
+ */
+void AON_WDG_Enable(void);
+
+/**
+ * \brief  Disable the AON Watch Dog.
+ * \return None.
+ */
+void AON_WDG_Disable(void);
+
+/**
+ * \brief  Restart the AON Watch Dog.
+ * \return None.
+ */
+void AON_WDG_Restart(void);
+
+/**
+ * \brief  Reset the system of the AON Watch Dog.
+ * \return None.
+ */
+void AON_WDG_SystemReset(void);
+
+/**
+ * \brief  AON Watch Dog initialization.
+ * \param[in]  reset_level: Specify the reset level.
+ *     This parameter can be 0 or 1.
+ *     \arg 0: Reset whole chip except partial AON and RTC.
+ *     \arg 1: Reset whole chip.
+ * \param[in]  timeout_second: Specify the timeout period in seconds, the maximum value is 65s
+ * \return None.
+ */
+static inline void aon_wdg_init(uint8_t reset_level, uint8_t timeout_second)
+{
+    uint32_t comp = (timeout_second * 1000) & 0x3FFFF;  //only 18 bit
+    AON_WDG_Config(reset_level, comp, 1, 1);
+}
+
+/**
+ * \brief  Enable the AON Watch Dog.
+ * \return None.
+ * \note   For APP use.
+ */
+static inline void aon_wdg_enable(void)
+{
+    AON_WDG_Enable();
+}
+
+/**
+ * \brief  Restart and disable the AON Watch Dog.
+ * \return None.
+ * \note   For APP use.
+ */
+static inline void aon_wdg_disable(void)
+{
+    AON_WDG_Restart();
+    AON_WDG_Disable();
+}
+
+/**
+ * @brief  Is AON Watch Dog enable.
+ */
+static inline bool AON_WDG_IsEnable(void)
+{
+    return (AON_WDG->u.CRT_BITS.EN == 1);
+}
+
+/**
+  * \}
+  */
+
+/**
+  * \}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTL876X_AON_WDG_H_ */
diff --git a/bee/drivers/wdt/src/device/rtl8752h/rtl876x_wdg.c b/bee/drivers/wdt/src/device/rtl8752h/rtl876x_wdg.c
new file mode 100644
index 00000000..a5627242
--- /dev/null
+++ b/bee/drivers/wdt/src/device/rtl8752h/rtl876x_wdg.c
@@ -0,0 +1,180 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "rtl876x_wdg.h"
+#include "platform_cfg.h"
+
+void WDG_ClockEnable(void)
+{
+    HAL_WRITE32(PERIPH_REG_BASE, 0x230, HAL_READ32(PERIPH_REG_BASE, 0x230) | BIT6);
+    HAL_WRITE32(PERIPH_REG_BASE, 0x360, HAL_READ32(PERIPH_REG_BASE, 0x360) | BIT8);
+    HAL_WRITE32(PERIPH_REG_BASE, 0x210, HAL_READ32(PERIPH_REG_BASE, 0x210) | BIT16);
+}
+
+#define CLK_FREQ_HZ 32000
+#define WDT_MAX_TIMEOUT_MS 8192000
+
+/**
+ * @brief  Calculate best div_factor and cnt_limit for target timeout (ms).
+ */
+static void get_wdt_config_params(uint32_t target_ms, uint16_t *out_div_factor, uint8_t *out_cnt_limit)
+{
+    uint8_t best_cnt_limit = 11;
+    uint16_t best_div_factor = 0xFFFF;
+    uint64_t best_diff = 0xFFFFFFFFFFFFFFFFULL;
+
+    /* Iterate through all possible cnt_limit values (0 to 11) */
+    for (uint8_t limit = 0; limit <= 11; limit++) {
+        uint32_t max_cnt = (1UL << (limit + 1)) - 1; /* 0x1, 0x3, 0x7 ... 0xFFF */
+
+        /*
+         * Reverse calculate required div_factor:
+         * Hardware counts from 0 to max_cnt, which is (max_cnt + 1) clock cycles.
+         * Formula: ((max_cnt + 1) * (1 + div_factor) * 1000) / CLK_FREQ_HZ = target_ms
+         * 1 + div_factor = (target_ms * CLK_FREQ_HZ) / ((max_cnt + 1) * 1000)
+         */
+        uint64_t numerator = (uint64_t)target_ms * CLK_FREQ_HZ;
+        uint64_t denominator = (uint64_t)(max_cnt + 1) * 1000ULL;
+
+        /* Round up to ensure timeout >= target_ms */
+        uint64_t required_div_plus_1 = (numerator + denominator - 1) / denominator;
+
+        if (required_div_plus_1 == 0) {
+            required_div_plus_1 = 1;
+        }
+
+        /* Check hardware limits (div_factor max is 0xFFFF) */
+        if (required_div_plus_1 > 65536) {
+            continue;
+        }
+
+        uint16_t div_factor = (uint16_t)(required_div_plus_1 - 1);
+
+        /* WDG_Config has a limitation that div_factor cannot be 0, so clamp to 1 */
+        if (div_factor == 0) {
+            div_factor = 1;
+        }
+
+        /* Calculate actual timeout - counter counts (max_cnt + 1) times */
+        uint64_t actual_ms = ((max_cnt + 1) * (1ULL + div_factor) * 1000ULL) / CLK_FREQ_HZ;
+        uint64_t diff = actual_ms >= target_ms ? (actual_ms - target_ms) : (target_ms - actual_ms);
+
+        /* Find the combination with the smallest difference */
+        if (diff < best_diff) {
+            best_diff = diff;
+            best_cnt_limit = limit;
+            best_div_factor = div_factor;
+        }
+    }
+
+    *out_cnt_limit = best_cnt_limit;
+    *out_div_factor = best_div_factor;
+}
+
+/**
+divfactor: 16Bit: 32000/(1+divfactor)
+cnt_limit: 2^(cnt_limit+1) - 1 ; max 11~15 = 0xFFF
+            0: 0x001
+            1: 0x003
+            2: 0x007
+            3: 0x00F
+            4: 0x01F
+            5: 0x03F
+            6: 0x07F
+            7: 0x0FF
+            8: 0x1FF
+            9: 0x3FF
+            10: 0x7FF
+            11~15: 0xFFF
+Wdg_mode: 0: interrupt cpu
+          1: reset all except AON
+          2: reset core domain
+          3: reset all
+*/
+void WDG_Config(
+    uint16_t div_factor,
+    uint8_t  cnt_limit,
+    T_WDG_MODE  wdg_mode
+)
+{
+    T_WATCH_DOG_TIMER_REG wdg_ctrl_value;
+    if (patch_WDG_Config)
+    {
+        if (patch_WDG_Config(div_factor, cnt_limit, wdg_mode))
+        {
+            return;
+        }
+    }
+    if (div_factor == 0)
+    {
+        div_factor = 1;
+    }
+
+    wdg_ctrl_value.d32 = WDG->WDG_CTL;
+
+    wdg_ctrl_value.b.div_factor = div_factor;
+    wdg_ctrl_value.b.cnt_limit = cnt_limit;
+    wdg_ctrl_value.b.wdg_mode = wdg_mode;
+
+    WDG->WDG_CTL = wdg_ctrl_value.d32;
+}
+
+
+void WDG_Enable(void)
+{
+    T_WATCH_DOG_TIMER_REG wdg_ctrl_value;
+
+    wdg_ctrl_value.d32 = WDG->WDG_CTL;
+
+    wdg_ctrl_value.b.en_byte = 0xA5;
+    wdg_ctrl_value.b.clear = 1;
+    wdg_ctrl_value.b.timeout = 1; // W1C;
+
+    WDG->WDG_CTL = wdg_ctrl_value.d32;
+}
+
+
+void WDG_Disable(void)
+{
+    T_WATCH_DOG_TIMER_REG wdg_ctrl_value;
+
+    wdg_ctrl_value.d32 = WDG->WDG_CTL;
+
+    wdg_ctrl_value.b.en_byte = 0;
+    wdg_ctrl_value.b.clear = 1;
+    wdg_ctrl_value.b.timeout = 1; // W1C;
+
+    WDG->WDG_CTL = wdg_ctrl_value.d32;
+}
+
+void WDG_Restart(void)
+{
+    T_WATCH_DOG_TIMER_REG wdg_ctrl_value;
+
+    wdg_ctrl_value.d32 = WDG->WDG_CTL;
+    wdg_ctrl_value.b.clear = 1;
+    WDG->WDG_CTL = wdg_ctrl_value.d32;
+}
+
+bool WDT_Start(uint32_t time_ms, T_WDG_MODE wdt_mode)
+{
+    /* Check for invalid input (zero or exceeding maximum hardware capability) */
+    if (time_ms == 0 || time_ms > WDT_MAX_TIMEOUT_MS) {
+        return false;
+    }
+
+    uint16_t div_factor;
+    uint8_t cnt_limit;
+
+    /* Get the optimal configuration based on required milliseconds */
+    get_wdt_config_params(time_ms, &div_factor, &cnt_limit);
+
+    /* Configure and Enable Watchdog */
+    WDG_Config(div_factor, cnt_limit, wdt_mode);
+    WDG_Enable();
+
+    return true;
+}
diff --git a/bee/drivers/wdt/src/device/rtl8752h/rtl876x_wdg.h b/bee/drivers/wdt/src/device/rtl8752h/rtl876x_wdg.h
new file mode 100644
index 00000000..c67cf98e
--- /dev/null
+++ b/bee/drivers/wdt/src/device/rtl8752h/rtl876x_wdg.h
@@ -0,0 +1,115 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _RTL876X_WDG_H_
+#define _RTL876X_WDG_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "rtl876x.h"
+#include "rtl876x_bitfields.h"
+
+/** @addtogroup WATCH_DOG WATCH_DOG
+  * @brief Watch Dog driver module
+  * @{
+  */
+
+/** @defgroup WATCH_DOG_Exported_Types Watch Dog Exported Types
+  * @{
+  */
+typedef enum _WDG_MODE
+{
+    INTERRUPT_CPU = 0,
+    RESET_ALL_EXCEPT_AON = 1,
+    RESET_CORE_DOMAIN = 2,
+    RESET_ALL = 3
+} T_WDG_MODE;
+/**
+  * @}
+  */
+
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t div_factor  : 16; //[15:0]  R/W Dividing factor. (at least set 1)
+        uint32_t en_byte     : 8; //[23:16] R/WSet 0xA5 to enable watch dog timer
+        uint32_t clear       : 1; //[24]    W     Write 1 to clear timer
+        uint32_t cnt_limit   : 4; //[28:25] R/W   0: 0x001 1: 0x003 .... 10: 0x7FF 11~15: 0xFFF
+        uint32_t wdg_mode    : 2; //[29:30] R/W
+        uint32_t timeout     : 1; //[31]    R/W1C Watch dog timer timeout. 1 cycle pulse
+    } b;
+} T_WATCH_DOG_TIMER_REG;
+
+typedef bool (*BOOL_PATCH_FUNC)();
+
+extern BOOL_PATCH_FUNC patch_WDG_Config;
+
+/**
+  * @}
+  */
+
+/** @defgroup WATCH_DOG_Exported_Functions Watch Dog Exported Functions
+  * @{
+  */
+
+/**
+   * @brief  Watch Dog Clock Enable.
+   */
+extern void WDG_ClockEnable(void);
+
+/**
+   * @brief  Watch Dog Timer Config.
+   * @param  div_factor: 16Bit: 32.768k/(1+divfactor).
+   * @param  cnt_limit: 2^(cnt_limit+1) - 1 ; max 11~15 = 0xFFF.
+   * @param  wdg_mode: 0: interrupt CPU
+   *                   1: reset all except aon
+   *                   2: reset core domain
+   *                   3: reset all
+   * @retval none.
+   */
+extern void WDG_Config(uint16_t div_factor, uint8_t cnt_limit, T_WDG_MODE wdg_mode);
+
+/**
+   * @brief  Watch Dog Timer Enable.
+   */
+extern void WDG_Enable(void);
+
+/**
+   * @brief  Watch Dog Timer Disable.
+   */
+extern void WDG_Disable(void);
+
+/**
+   * @brief  Watch Dog Timer Restart.
+   */
+extern void WDG_Restart(void);
+
+/**
+ * @brief  Start Watchdog Timer with specified timeout and mode.
+ * @param  time_ms: Timeout value in milliseconds.
+ * @param  wdt_mode: Watchdog Timer mode (0: Interrupt, 1: Reset except AON, 2: Reset Core, 3: Reset All)
+ * @retval true if started successfully, false otherwise.
+ */
+bool WDT_Start(uint32_t time_ms, T_WDG_MODE wdt_mode);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //_RTL876X_WDG_H_
diff --git a/bee/drivers/wdt/src/device/rtl87x2g/CMakeLists.txt b/bee/drivers/wdt/src/device/rtl87x2g/CMakeLists.txt
new file mode 100644
index 00000000..75ea6a82
--- /dev/null
+++ b/bee/drivers/wdt/src/device/rtl87x2g/CMakeLists.txt
@@ -0,0 +1,7 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_library()
+
+zephyr_library_sources_ifdef(CONFIG_REALTEK_BEE_AON_WDT rtl87x2g_aon_wdt.c)
+zephyr_library_sources_ifdef(CONFIG_REALTEK_BEE_CORE_WDT rtl87x2g_wdt.c)
diff --git a/bee/drivers/wdt/src/device/rtl87x2g/rtl87x2g_aon_wdt.c b/bee/drivers/wdt/src/device/rtl87x2g/rtl87x2g_aon_wdt.c
new file mode 100644
index 00000000..379cfc8c
--- /dev/null
+++ b/bee/drivers/wdt/src/device/rtl87x2g/rtl87x2g_aon_wdt.c
@@ -0,0 +1,72 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *                         Header Files
+*============================================================================*/
+#include "rtl_aon_wdt.h"
+#include "nsc_veneer.h"
+
+/*============================================================================*
+ *                         Private Functions
+ *============================================================================*/
+extern bool aon_wdg_start(uint32_t TimeMs, WDTMode_TypeDef Mode);
+extern void aon_wdg_disable();
+extern void aon_wdg_kick();
+
+/*============================================================================*
+ *                         Functions
+ *============================================================================*/
+bool AON_WDT_Start(AON_WDT_TypeDef *AON_WDTx, uint32_t TimeMs, WDTMode_TypeDef Mode)
+{
+    if (Mode == INTERRUPT_CPU)
+    {
+        return false;
+    }
+
+    aon_wdg_start(TimeMs, Mode);
+    aon_wdg_kick();
+
+    return true;
+}
+
+void AON_WDT_Disable(AON_WDT_TypeDef *AON_WDTx)
+{
+    aon_wdg_disable();
+}
+
+void AON_WDT_Kick(AON_WDT_TypeDef *AON_WDTx)
+{
+    aon_wdg_kick();
+}
+
+bool AON_WDT_IsEnable(AON_WDT_TypeDef *AON_WDTx)
+{
+    bool is_enable;
+
+    secure_function_call(AON_WDT_IS_ENABLE, &is_enable);
+
+    return is_enable;
+}
+
+uint32_t AON_WDT_GetTimeoutMs(AON_WDT_TypeDef *AON_WDTx)
+{
+    uint32_t timeout;
+
+    secure_function_call(AON_WDT_GET_TIMEOUT_MS, &timeout);
+
+    return timeout;
+}
+
+WDTMode_TypeDef AON_WDT_GetMode(AON_WDT_TypeDef *AON_WDTx)
+{
+    uint8_t wdt_mode;
+
+    secure_function_call(AON_WDT_GET_MODE, &wdt_mode);
+
+    return (WDTMode_TypeDef)wdt_mode;
+}
+
diff --git a/bee/drivers/wdt/src/device/rtl87x2g/rtl87x2g_wdt.c b/bee/drivers/wdt/src/device/rtl87x2g/rtl87x2g_wdt.c
new file mode 100644
index 00000000..ce5adaf9
--- /dev/null
+++ b/bee/drivers/wdt/src/device/rtl87x2g/rtl87x2g_wdt.c
@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *                         Header Files
+*============================================================================*/
+#include "rtl_wdt.h"
+#include "nsc_veneer.h"
+
+/*============================================================================*
+ *                         Private Functions
+ *============================================================================*/
+extern bool WDG_Start(uint32_t TimeMs, WDTMode_TypeDef Mode);
+extern bool WDG_Disable();
+extern bool WDG_Kick();
+extern bool is_WDG_Enable();
+
+/*============================================================================*
+ *                         Functions
+ *============================================================================*/
+bool WDT_Start(uint32_t TimeMs, WDTMode_TypeDef Mode)
+{
+    return WDG_Start(TimeMs, Mode);
+}
+
+void WDT_Disable(void)
+{
+    WDG_Disable();
+}
+
+void WDT_Kick(void)
+{
+    WDG_Kick();
+}
+
+bool WDT_IsEnable(void)
+{
+    return is_WDG_Enable();
+}
+
+uint32_t WDT_GetTimeoutMs(void)
+{
+    uint32_t timeout;
+
+    secure_function_call(WDT_GET_TIMEOUT_MS, &timeout);
+
+    return timeout;
+}
+
+WDTMode_TypeDef WDT_GetMode(void)
+{
+    uint8_t wdt_mode;
+
+    secure_function_call(WDT_GET_MODE, &wdt_mode);
+
+    return (WDTMode_TypeDef)wdt_mode;
+}
+
diff --git a/bee/drivers/wdt/src/device/rtl87x2g/rtl_aon_wdt_def.h b/bee/drivers/wdt/src/device/rtl87x2g/rtl_aon_wdt_def.h
new file mode 100644
index 00000000..42426b5d
--- /dev/null
+++ b/bee/drivers/wdt/src/device/rtl87x2g/rtl_aon_wdt_def.h
@@ -0,0 +1,103 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef RTL_AON_WDT_DEF_H
+#define RTL_AON_WDT_DEF_H
+
+#include "utils/rtl_utils.h"
+#include "address_map.h"
+
+#ifdef  __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/*============================================================================*
+ *                          AON WDT Defines
+ *============================================================================*/
+
+
+/*============================================================================*
+ *                         AON WDT Registers Memory Map
+ *============================================================================*/
+typedef struct
+{
+    /*!< 0x00 0xA5A5: disable AON_WDT_CONFIG write protect; other: enable AON_WDT_CONFIG write protect */
+    __IO uint32_t aon_wdt_wp : 16;
+    __IO uint32_t aon_wdt_rscd0 : 16;
+    /*!< Dividing factor. Watch dog timer is count with /(divfactor+1). Minimum dividing factor is 1. */
+    __IO uint32_t aon_wdt_clk_div_factor : 16; /*!< 0x04 */
+    /*!< when AON_WDT_CNT>=AON_WDT_CNT_LIMIT then WDT timeout  */
+    __IO uint32_t aon_wdt_cnt_limit : 12;
+    /*!< "01:Level 1:whole reset chip except xxx; 00:Level 0:whole chip reset(include LV1)" */
+    __IO uint32_t aon_wdt_mode : 1;
+    /*!< "1:WDT countine count in DLPS 0:WDT stop count in DLPS" */
+    __IO uint32_t aon_wdt_cnt_ctl : 1;
+    /*!< "when  reg_aon_wdt_cnt_ctl ==0 1:reload counter when exit DLPS 0:not reload counter when exit DLPS" */
+    __IO uint32_t aon_wdt_cnt_reload : 1;
+    /*!< "0:stop & reset AON_WDT_CNT; 1:enable AON_WDT_CNT run" */
+    __IO uint32_t aon_wdt_en : 1;
+    /*!< 0x08 0x5A5A: reset watch dog counter(not stop counter) other: no effect */
+    __IO uint32_t aon_wdt_cnt_reset : 16;
+    __IO uint32_t aon_wdt_rscd1 : 16;
+    /*!< 0x0c "0: AON_WDT_WP register can be accessed by Secure accesses
+               1: AON_WDT_WP register can be accessed by Non-secure accesses" */
+    __IO uint32_t aon_wdt_wp_sec : 1;
+    /*!< "0: AON_WDT_CONFIG register can be accessed by Secure accesses
+          1: AON_WDT_CONFIG register can be accessed by Non-secure accesses" */
+    __IO uint32_t aon_wdt_config_sec : 1;
+    /*!< "0: AON_WDT_RESET_SEC register can be accessed by Secure accesses
+          1: AON_WDT_RESET_SEC register can be accessed by Non-secure accesses" */
+    __IO uint32_t aon_wdt_reset_sec : 1;
+    __IO uint32_t aon_wdt_rscd2 : 29;
+} AON_WDT_TypeDef;
+
+/*============================================================================*
+ *                         AON WDT Declaration
+ *============================================================================*/
+/** \defgroup AON_WDT         AON_WDT
+  * \brief
+  * \{
+  */
+
+/** \defgroup AON_WDT_Exported_Constants AON_WDT Exported Constants
+  * \brief
+  * \{
+  */
+
+/** \defgroup AON_WDT_Declaration AON_WDT Declaration
+  * \brief
+  * \{
+  */
+
+#define AON_WDT            ((AON_WDT_TypeDef *) AON_WDT_REG_BASE) //!< AON_WDT base address.
+
+/** End of AON_WDT_Declaration
+  * \}
+  */
+
+/** End of AON_WDT_Exported_Constants
+  * \}
+  */
+
+/** End of AON_WDT
+  * \}
+  */
+
+/*============================================================================*
+ *                         AON WDT Private Types
+ *============================================================================*/
+
+
+/*============================================================================*
+ *                         AON WDT Registers and Field Descriptions
+ *============================================================================*/
+
+
+#ifdef  __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* RTL_AON_WDT_DEF_H */
diff --git a/bee/drivers/wdt/src/device/rtl87x2g/rtl_wdt_def.h b/bee/drivers/wdt/src/device/rtl87x2g/rtl_wdt_def.h
new file mode 100644
index 00000000..923e6026
--- /dev/null
+++ b/bee/drivers/wdt/src/device/rtl87x2g/rtl_wdt_def.h
@@ -0,0 +1,89 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef RTL_WDT_DEF_H
+#define RTL_WDT_DEF_H
+
+#include "utils/rtl_utils.h"
+#include "address_map.h"
+
+#ifdef  __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/*============================================================================*
+ *                          WDT Defines
+ *============================================================================*/
+
+/*============================================================================*
+ *                         WDT Registers Memory Map
+ *============================================================================*/
+typedef struct                              /*!< WDT Structure */
+{
+    __IO uint32_t WDT_WP : 16;                  /*!< 0x00 */
+    __IO uint32_t RSVD0 : 16;
+    __IO uint32_t WDT_CLK_DIV_FACTOR : 16;      /*!< 0x04 */
+    __IO uint32_t WDT_CNT_LIMIT : 12;
+    __IO uint32_t WDT_MODE : 2;
+    __IO uint32_t WDT_TIMEOUT_FLG : 1;
+    __IO uint32_t WDT_ENABLE : 1;
+    __IO uint32_t WDT_CNT_RESET : 16;           /*!< 0x08 */
+    __IO uint32_t RSVD1 : 16;
+    __IO uint32_t WDT_WP_SEC : 1;               /*!< 0x0C */
+    __IO uint32_t WDT_CONFIG_SEC : 1;
+    __IO uint32_t WDT_RESET_SEC : 1;
+    __IO uint32_t RSVD2 : 29;
+} WDT_TypeDef;
+
+/*============================================================================*
+ *                         WDT Declaration
+ *============================================================================*/
+#define WDT_REG_BASE       (SOC_VENDOR_REG_BASE + 0x100)
+
+/** \defgroup WDT         WDT
+  * \brief
+  * \{
+  */
+
+/** \defgroup WDT_Exported_Constants WDT Exported Constants
+  * \brief
+  * \{
+  */
+
+/** \defgroup WDT_Declaration WDT Declaration
+  * \brief
+  * \{
+  */
+#define WDT                ((WDT_TypeDef *) WDT_REG_BASE)   //!< WDT base address.
+
+
+/** End of WDT_Declaration
+  * \}
+  */
+
+/** End of WDT_Exported_Constants
+  * \}
+  */
+
+/** End of WDT
+  * \}
+  */
+
+/*============================================================================*
+ *                         WDT Private Types
+ *============================================================================*/
+
+
+/*============================================================================*
+ *                         WDT Registers and Field Descriptions
+ *============================================================================*/
+
+
+#ifdef  __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* RTL_WDT_DEF_H */
diff --git a/bee/drivers/wdt/src/device/rtl87x2j/CMakeLists.txt b/bee/drivers/wdt/src/device/rtl87x2j/CMakeLists.txt
new file mode 100644
index 00000000..9760de29
--- /dev/null
+++ b/bee/drivers/wdt/src/device/rtl87x2j/CMakeLists.txt
@@ -0,0 +1,8 @@
+#
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+# zephyr_library_sources_ifdef(CONFIG_REALTEK_BEE_AON_WDT rtl87x2g_aon_wdt.c)
+zephyr_library_sources_ifdef(CONFIG_REALTEK_BEE_CORE_WDT rtl_wdt.c)
diff --git a/bee/drivers/wdt/src/device/rtl87x2j/rtl_lpwdt.c b/bee/drivers/wdt/src/device/rtl87x2j/rtl_lpwdt.c
new file mode 100644
index 00000000..f44999d9
--- /dev/null
+++ b/bee/drivers/wdt/src/device/rtl87x2j/rtl_lpwdt.c
@@ -0,0 +1,149 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *                           Header Files
+*============================================================================*/
+#include "rtl_lpwdt.h"
+#include "rtl_rcc.h"
+
+/*============================================================================*
+ *                           Private Constants
+ *============================================================================*/
+#define LPWDT_CLOCK_FREQUENCY        (32000)
+#define LPWDT_MAX_TIMEOUT_MS         (((1 << 28) - 1) / (LPWDT_CLOCK_FREQUENCY / 1000))
+#define LPWDT_VPON_ADDR              0x400003E0
+
+/*============================================================================*
+*                           Private Functions
+*============================================================================*/
+static bool LPWDT_CalculateConfig(uint32_t timeout_ms, uint32_t *cnt_limit)
+{
+    if (timeout_ms > LPWDT_MAX_TIMEOUT_MS)
+    {
+        return false;
+    }
+
+    *cnt_limit = timeout_ms * (LPWDT_CLOCK_FREQUENCY / 1000);
+
+    return true;
+}
+
+static void LPWDT_Config(uint32_t cnt_limit, WDTMode_TypeDef wdt_mode)
+{
+    /* LPWDT function enable*/
+    RCC_ClockCmd(LPWDT_CLOCK, ENABLE);
+
+    WDT_REG0X_TypeDef lpwdt_reg0 = {.d32 = LPWDT->WDT_REG0X};
+    lpwdt_reg0.b.lpwdt_mode = wdt_mode;
+    lpwdt_reg0.b.lpwdt_cnt_limit = cnt_limit;
+
+    /* counter will go on and counter value is reload from active when enter low power mode*/
+    lpwdt_reg0.b.lpwdt_cnt_ctl = 1;
+    lpwdt_reg0.b.lpwdt_cnt_reload = 1;
+    LPWDT->WDT_REG0X = lpwdt_reg0.d32;
+}
+
+/*============================================================================*
+ *                           Public Functions
+ *============================================================================*/
+/**
+  * \brief  Start Watchdog. This function will enable watchdog clock, set and start watchdog.
+  * \param  Time_ms.
+  * \param  LPWDT_Mode \ref LPWDTMode_TypeDef.
+  * \return true or false.
+  */
+bool LPWDT_Start(LPWDT_TypeDef *LPWDTx, uint32_t TimeMs, WDTMode_TypeDef Mode)
+{
+    uint32_t cnt_limit;
+    if (LPWDT_CalculateConfig(TimeMs, &cnt_limit))
+    {
+        LPWDT_Config(cnt_limit, Mode);
+        LPWDT_Kick(LPWDTx);
+        LPWDT_Enable(LPWDTx);
+        return true;
+    }
+    return false;
+}
+
+/**
+  * \brief  Enable Watchdog.
+  * \return None.
+  */
+void LPWDT_Enable(LPWDT_TypeDef *LPWDTx)
+{
+    WDT_REG0X_TypeDef lpwdt_reg0 = {.d32 = LPWDTx->WDT_REG0X};
+    lpwdt_reg0.b.lpwdt_enable = 1;
+    LPWDTx->WDT_REG0X = lpwdt_reg0.d32;
+}
+
+/**
+  * \brief  Disable Watchdog.
+  * \return None.
+  */
+void LPWDT_Disable(LPWDT_TypeDef *LPWDTx)
+{
+    WDT_REG0X_TypeDef lpwdt_reg0 = {.d32 = LPWDTx->WDT_REG0X};
+    lpwdt_reg0.b.lpwdt_enable = 0;
+    LPWDTx->WDT_REG0X = lpwdt_reg0.d32;
+}
+
+/**
+  * \brief  Kick Watchdog to restart watchdog timer.
+  * \return None.
+  */
+void LPWDT_Kick(LPWDT_TypeDef *LPWDTx)
+{
+    WDT_REG1X_TypeDef lpwdt_reg1 = {.d32 = LPWDTx->WDT_REG1X};
+    lpwdt_reg1.b.lpwdt_cnt_reset = 0x5A5A;
+    LPWDTx->WDT_REG1X = lpwdt_reg1.d32;
+}
+
+/**
+  * \brief  Is watchdog enable.
+  * \return Is watchdog enable or not
+  */
+bool LPWDT_IsEnable(LPWDT_TypeDef *LPWDTx)
+{
+    WDT_REG0X_TypeDef lpwdt_reg0 = {.d32 = LPWDTx->WDT_REG0X};
+
+    return (lpwdt_reg0.b.lpwdt_enable == 1);
+}
+
+/**
+  * \brief  Get LPWDT timeout_ms.
+  * \return LPWDT timeout_ms
+  */
+uint32_t LPWDT_GetTimeoutMs(LPWDT_TypeDef *LPWDTx)
+{
+    WDT_REG0X_TypeDef lpwdt_reg0 = {.d32 = LPWDTx->WDT_REG0X};
+
+    uint32_t timeout_ms = (lpwdt_reg0.b.lpwdt_cnt_limit / (LPWDT_CLOCK_FREQUENCY / 1000));
+
+    return timeout_ms;
+}
+
+/**
+  * \brief  Get LPWDT mode.
+  * \return LPWDT mode
+  */
+WDTMode_TypeDef LPWDT_GetMode(LPWDT_TypeDef *LPWDTx)
+{
+    WDT_REG0X_TypeDef lpwdt_reg0 = {.d32 = LPWDT->WDT_REG0X};
+
+    return (WDTMode_TypeDef)(lpwdt_reg0.b.lpwdt_mode);
+}
+
+/**
+  * \brief  Get LPWDT current Count.
+  * \return Current Count
+  */
+uint32_t LPWDT_GetCurrentCount(LPWDT_TypeDef *LPWDTx)
+{
+    WDT_REG19X_TypeDef lpwdt_reg19 = {.d32 = LPWDT->WDT_REG19X};
+
+    return (uint32_t)lpwdt_reg19.b.lpwdt_current;
+}
diff --git a/bee/drivers/wdt/src/device/rtl87x2j/rtl_lpwdt_def.h b/bee/drivers/wdt/src/device/rtl87x2j/rtl_lpwdt_def.h
new file mode 100644
index 00000000..81dd0afe
--- /dev/null
+++ b/bee/drivers/wdt/src/device/rtl87x2j/rtl_lpwdt_def.h
@@ -0,0 +1,439 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef RTL_LPWDT_DEF_H
+#define RTL_LPWDT_DEF_H
+
+#include "utils/rtl_utils.h"
+#include "address_map.h"
+#include "aon_reg.h"
+
+#ifdef  __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/*============================================================================*
+ *                          LPWDT Defines
+ *============================================================================*/
+#define LPWDT_SUPPORT_GET_CURRENT_COUNTER              (1)
+
+/*============================================================================*
+ *                          LPWDT Registers Memory Map
+ *============================================================================*/
+typedef struct
+{
+    __IO uint32_t WDT_REG0X;            /*!< 0x00 */
+    __IO uint32_t WDT_REG1X;            /*!< 0x04 */
+    __IO uint32_t WDT_REG2X;            /*!< 0x08 */
+    __IO uint32_t WDT_REG3X;            /*!< 0x0C */
+    __IO uint32_t WDT_REG4X;            /*!< 0x10 */
+    __IO uint32_t WDT_REG5X;            /*!< 0x14 */
+    __IO uint32_t WDT_REG6X;            /*!< 0x18 */
+    __IO uint32_t WDT_REG7X;            /*!< 0x1C */
+    __IO uint32_t WDT_REG8X;            /*!< 0x20 */
+    __IO uint32_t WDT_REG9X;            /*!< 0x24 */
+    __IO uint32_t WDT_REG10X;           /*!< 0x28 */
+    __IO uint32_t WDT_REG11X;           /*!< 0x2C */
+    __IO uint32_t WDT_REG12X;           /*!< 0x30 */
+    __IO uint32_t WDT_REG13X;           /*!< 0x34 */
+    __IO uint32_t WDT_REG14X;           /*!< 0x38 */
+    __IO uint32_t WDT_REG15X;           /*!< 0x3C */
+    __IO uint32_t WDT_REG16X;           /*!< 0x40 */
+    __IO uint32_t WDT_REG17X;           /*!< 0x44 */
+    __IO uint32_t WDT_REG18X;           /*!< 0x48 */
+    __IO uint32_t WDT_REG19X;           /*!< 0x4C */
+    __IO uint32_t WDT_REG20X;           /*!< 0x50 */
+    __IO uint32_t IO_WDT_REG0X;         /*!< 0x58 */
+    __IO uint32_t IO_WDT_REG1X;         /*!< 0x5C */
+} LPWDT_TypeDef;
+
+/*============================================================================*
+ *                          LPWDT Declaration
+ *============================================================================*/
+/** \defgroup LPWDT         LPWDT
+  * \brief
+  * \{
+  */
+
+/** \defgroup LPWDT_Exported_Constants LPWDT Exported Constants
+  * \brief
+  * \{
+  */
+
+/** \defgroup LPWDT_Declaration LPWDT Declaration
+  * \brief
+  * \{
+  */
+
+#define LPWDT_REG_BASE       (SYSON_BASE + AON_REG_WDT_REG0X)
+#define LPWDT                ((LPWDT_TypeDef *) LPWDT_REG_BASE)
+
+
+/** End of LPWDT_Declaration
+  * \}
+  */
+
+/** End of LPWDT_Exported_Constants
+  * \}
+  */
+
+/** End of LPWDT
+  * \}
+  */
+/*============================================================================*
+ *                          LPWDT Private Types
+ *============================================================================*/
+
+/*============================================================================*
+ *                          LPWDT Registers and Field Descriptions
+ *============================================================================*/
+/* 0x00
+   27:0    R/W    lpwdt_cnt_limit                 28'h55F00
+   28      R/W    lpwdt_mode                      1'b0
+   29      R/W    lpwdt_cnt_ctl                   1'b0
+   30      R/W    lpwdt_cnt_reload                1'b0
+   31      R/W    lpwdt_enable                    1'b0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t lpwdt_cnt_limit: 28;
+        uint32_t lpwdt_mode: 1;
+        uint32_t lpwdt_cnt_ctl: 1;
+        uint32_t lpwdt_cnt_reload: 1;
+        uint32_t lpwdt_enable: 1;
+    } b;
+} WDT_REG0X_TypeDef;
+
+
+/* 0x04
+   15:0    R/WAC  lpwdt_cnt_reset                 16'h0
+   16      R/W    lpwdt_clk32k_qactive_man_data   1'b0
+   17      R/W    lpwdt_clk32k_qactive_man_en     1'b0
+   31:18   R/W    reserved                        14'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t lpwdt_cnt_reset: 16;
+        uint32_t lpwdt_clk32k_qactive_man_data: 1;
+        uint32_t lpwdt_clk32k_qactive_man_en: 1;
+        uint32_t reserved_0: 14;
+    } b;
+} WDT_REG1X_TypeDef;
+
+
+/* 0x08
+   15:0    R      corewdt_cpu_pc_lsb              16'b0
+   31:16   R      corewdt_cpu_pc_msb              16'b0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t corewdt_cpu_pc_lsb: 16;
+        const uint32_t corewdt_cpu_pc_msb: 16;
+    } b;
+} WDT_REG2X_TypeDef;
+
+
+/* 0x0C
+   15:0    R      corewdt_cpu_xpsr_lsb            16'b0
+   31:16   R      corewdt_cpu_xpsr_msb            16'b0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t corewdt_cpu_xpsr_lsb: 16;
+        const uint32_t corewdt_cpu_xpsr_msb: 16;
+    } b;
+} WDT_REG3X_TypeDef;
+
+
+/* 0x10
+   15:0    R      corewdt_cpu_lr_lsb              16'b0
+   31:16   R      corewdt_cpu_lr_msb              16'b0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t corewdt_cpu_lr_lsb: 16;
+        const uint32_t corewdt_cpu_lr_msb: 16;
+    } b;
+} WDT_REG4X_TypeDef;
+
+
+/* 0x14
+   15:0    R      corewdt_cpu_r00_q_lsb           16'b0
+   31:16   R      corewdt_cpu_r00_q_msb           16'b0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t corewdt_cpu_r00_q_lsb: 16;
+        const uint32_t corewdt_cpu_r00_q_msb: 16;
+    } b;
+} WDT_REG5X_TypeDef;
+
+
+/* 0x18
+   15:0    R      corewdt_cpu_r01_q_lsb           16'b0
+   31:16   R      corewdt_cpu_r01_q_msb           16'b0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t corewdt_cpu_r01_q_lsb: 16;
+        const uint32_t corewdt_cpu_r01_q_msb: 16;
+    } b;
+} WDT_REG6X_TypeDef;
+
+
+/* 0x1C
+   15:0    R      corewdt_cpu_r02_q_lsb           16'b0
+   31:16   R      corewdt_cpu_r02_q_msb           16'b0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t corewdt_cpu_r02_q_lsb: 16;
+        const uint32_t corewdt_cpu_r02_q_msb: 16;
+    } b;
+} WDT_REG7X_TypeDef;
+
+
+/* 0x20
+   15:0    R      corewdt_cpu_r03_q_lsb           16'b0
+   31:16   R      corewdt_cpu_r03_q_msb           16'b0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t corewdt_cpu_r03_q_lsb: 16;
+        const uint32_t corewdt_cpu_r03_q_msb: 16;
+    } b;
+} WDT_REG8X_TypeDef;
+
+
+/* 0x24
+   0       R      corewdt_flag                    1'b0
+   2:1     R      corewdt_mode                    2'b0
+   31:3    R      reserved                        29'b0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t corewdt_flag: 1;
+        const uint32_t corewdt_mode: 2;
+        const uint32_t reserved_0: 29;
+    } b;
+} WDT_REG9X_TypeDef;
+
+
+/* 0x28
+   0       R/WAC  corewdt_flag_clr                1'b0
+   1       R/WAC  corewdt_mode_clr                1'b0
+   15:2    R      reserved                        14'b0
+   16      R/WAC  corewdt_cpu_reg_clr             1'b0
+   31:17   R      reserved                        15'b0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t corewdt_flag_clr: 1;
+        uint32_t corewdt_mode_clr: 1;
+        const uint32_t reserved_1: 14;
+        uint32_t corewdt_cpu_reg_clr: 1;
+        const uint32_t reserved_0: 15;
+    } b;
+} WDT_REG10X_TypeDef;
+
+
+/* 0x2C
+   31:0    R      reserved                        32'b0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t reserved_0: 32;
+    } b;
+} WDT_REG11X_TypeDef;
+
+
+/* 0x30
+   15:0    R      lpwdt_cpu_pc_lsb                16'b0
+   31:16   R      lpwdt_cpu_pc_msb                16'b0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t lpwdt_cpu_pc_lsb: 16;
+        const uint32_t lpwdt_cpu_pc_msb: 16;
+    } b;
+} WDT_REG12X_TypeDef;
+
+
+/* 0x34
+   15:0    R      lpwdt_cpu_xpsr_lsb              16'b0
+   31:16   R      lpwdt_cpu_xpsr_msb              16'b0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t lpwdt_cpu_xpsr_lsb: 16;
+        const uint32_t lpwdt_cpu_xpsr_msb: 16;
+    } b;
+} WDT_REG13X_TypeDef;
+
+
+/* 0x38
+   15:0    R      lpwdt_cpu_lr_lsb                16'b0
+   31:16   R      lpwdt_cpu_lr_msb                16'b0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t lpwdt_cpu_lr_lsb: 16;
+        const uint32_t lpwdt_cpu_lr_msb: 16;
+    } b;
+} WDT_REG14X_TypeDef;
+
+
+/* 0x3C
+   15:0    R      lpwdt_cpu_r00_q_lsb             16'b0
+   31:16   R      lpwdt_cpu_r00_q_msb             16'b0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t lpwdt_cpu_r00_q_lsb: 16;
+        const uint32_t lpwdt_cpu_r00_q_msb: 16;
+    } b;
+} WDT_REG15X_TypeDef;
+
+
+/* 0x40
+   15:0    R      lpwdt_cpu_r01_q_lsb             16'b0
+   31:16   R      lpwdt_cpu_r01_q_msb             16'b0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t lpwdt_cpu_r01_q_lsb: 16;
+        const uint32_t lpwdt_cpu_r01_q_msb: 16;
+    } b;
+} WDT_REG16X_TypeDef;
+
+
+/* 0x44
+   15:0    R      lpwdt_cpu_r02_q_lsb             16'b0
+   31:16   R      lpwdt_cpu_r02_q_msb             16'b0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t lpwdt_cpu_r02_q_lsb: 16;
+        const uint32_t lpwdt_cpu_r02_q_msb: 16;
+    } b;
+} WDT_REG17X_TypeDef;
+
+
+/* 0x48
+   15:0    R      lpwdt_cpu_r03_q_lsb             16'b0
+   31:16   R      lpwdt_cpu_r03_q_msb             16'b0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t lpwdt_cpu_r03_q_lsb: 16;
+        const uint32_t lpwdt_cpu_r03_q_msb: 16;
+    } b;
+} WDT_REG18X_TypeDef;
+
+
+/* 0x4C
+   0       R      lpwdt_flag                      1'b0
+   2:1     R      lpwdt_mode_record               2'b0
+   30:3    R      lpwdt_current                   28'b0
+   31      R      reserved                        1'b0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t lpwdt_flag: 1;
+        const uint32_t lpwdt_mode_record: 2;
+        const uint32_t lpwdt_current: 28;
+        const uint32_t reserved_0: 1;
+    } b;
+} WDT_REG19X_TypeDef;
+
+
+/* 0x50
+   0       R/WAC  lpwdt_flag_clr                  1'b0
+   1       R/WAC  lpwdt_mode_clr                  1'b0
+   15:2    R      reserved                        14'b0
+   16      R/WAC  lpwdt_cpu_reg_clr               1'b0
+   31:17   R      reserved                        15'b0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t lpwdt_flag_clr: 1;
+        uint32_t lpwdt_mode_clr: 1;
+        const uint32_t reserved_1: 14;
+        uint32_t lpwdt_cpu_reg_clr: 1;
+        const uint32_t reserved_0: 15;
+    } b;
+} WDT_REG20X_TypeDef;
+
+
+
+#ifdef  __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* RTL_LPWDT_DEF_H */
diff --git a/bee/drivers/wdt/src/device/rtl87x2j/rtl_wdt.c b/bee/drivers/wdt/src/device/rtl87x2j/rtl_wdt.c
new file mode 100644
index 00000000..cd789992
--- /dev/null
+++ b/bee/drivers/wdt/src/device/rtl87x2j/rtl_wdt.c
@@ -0,0 +1,180 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *                           Header Files
+*============================================================================*/
+#include "rtl_wdt.h"
+#include "rtl_rcc.h"
+#include "stdio.h"
+/*============================================================================*
+ *                           Private Constants
+ *============================================================================*/
+#define WDT_CLOCK_FREQUENCY        (32000)
+#define WDT_MAX_TIMEOUT_MS         (((1 << 28) - 1) / (WDT_CLOCK_FREQUENCY / 1000))
+
+#define WDT_CLOCK_AUTO_MODE_CONFIG_AUTOMATIC       (0x00)
+#define WDT_CLOCK_AUTO_MODE_CONFIG_ALWAYSRUN       (0x03)//Force off 0x02
+
+/*============================================================================*
+*                           Private Functions
+*============================================================================*/
+static void WDT_ClockEnable(void)
+{
+    RCC_ClockCmd(WDT_CLOCK, ENABLE);
+}
+
+static bool WDT_CalculateConfig(uint32_t timeout_ms, uint32_t *cnt_limit)
+{
+    if (timeout_ms > WDT_MAX_TIMEOUT_MS)
+    {
+        return false;
+    }
+
+    *cnt_limit = timeout_ms * (WDT_CLOCK_FREQUENCY / 1000);
+
+    return true;
+}
+
+static void WDT_Config(uint32_t cnt_limit, WDTMode_TypeDef wdt_mode)
+{
+    WDT_CTL_TypeDef wdt_ctl = {.d32 = WDT->WDT_CTL};
+    wdt_ctl.b.wdt_cnt_limit = cnt_limit;
+    wdt_ctl.b.wdt_mode = wdt_mode;
+    WDT->WDT_CTL = wdt_ctl.d32;
+}
+
+/*============================================================================*
+ *                           Public Functions
+ *============================================================================*/
+/**
+  * \brief  Start Watchdog. This function will enable watchdog clock, set and start watchdog.
+  * \param  Time_ms.
+  * \param  WDT_Mode \ref WDTMode_TypeDef.
+  * \return true or false.
+  */
+bool WDT_Start(uint32_t TimeMs, WDTMode_TypeDef Mode)
+{
+    uint32_t cnt_limit;
+    printf("WDT start with timeout %u ms, mode %u\n", TimeMs, Mode);
+    if (WDT_CalculateConfig(TimeMs, &cnt_limit))
+    {
+        WDT_ClockEnable();
+        WDT_Config(cnt_limit, Mode);
+        WDT_Kick();
+        WDT_Enable();
+        return true;
+    }
+    return false;
+}
+
+/**
+  * \brief  Enable Watchdog.
+  * \return None.
+  */
+void WDT_Enable(void)
+{
+    WDT_CTL_TypeDef wdt_ctl = {.d32 = WDT->WDT_CTL};
+    wdt_ctl.b.wdt_en = 1;
+    wdt_ctl.b.wdt_to = 1;
+    WDT->WDT_CTL = wdt_ctl.d32;
+}
+
+/**
+  * \brief  Disable Watchdog.
+  * \return None.
+  */
+void WDT_Disable(void)
+{
+    WDT_CTL_TypeDef wdt_ctl = {.d32 = WDT->WDT_CTL};
+    wdt_ctl.b.wdt_en = 0;
+    wdt_ctl.b.wdt_to = 1;
+    WDT->WDT_CTL = wdt_ctl.d32;
+}
+
+/**
+  * \brief  Kick Watchdog to restart watchdog timer.
+  * \return None.
+  */
+void WDT_Kick(void)
+{
+    WDT->WDT_KICK = 0x5A5A;
+}
+
+/**
+  * \brief  Clear WDT interrupt pending bit.
+  * \return None
+  */
+void WDT_ClearINTPendingBit(void)
+{
+
+    WDT_CTL_TypeDef wdt_ctl = {.d32 = WDT->WDT_CTL};
+    wdt_ctl.b.wdt_to = 1;
+    WDT->WDT_CTL = wdt_ctl.d32;
+}
+
+/**
+  * \brief  Is watchdog enable.
+  * \return Is watchdog enable or not
+  */
+bool WDT_IsEnable(void)
+{
+    WDT_CTL_TypeDef wdt_ctl = {.d32 = WDT->WDT_CTL};
+
+    return (wdt_ctl.b.wdt_en == 1);
+}
+
+/**
+  * \brief  Get WDT timeout_ms.
+  * \return WDT timeout_ms
+  */
+uint32_t WDT_GetTimeoutMs(void)
+{
+    WDT_CTL_TypeDef wdt_ctl = {.d32 = WDT->WDT_CTL};
+
+    uint32_t timeout_ms = (wdt_ctl.b.wdt_cnt_limit / (WDT_CLOCK_FREQUENCY / 1000));
+
+    return timeout_ms;
+}
+
+/**
+  * \brief  Get WDT current count.
+  * \return Current count
+  */
+uint32_t WDT_GetCurrentCount(void)
+{
+    return WDT->WDT_CURRENT;
+}
+
+/**
+  * \brief  Get WDT mode.
+  * \return WDT mode
+  */
+WDTMode_TypeDef WDT_GetMode(void)
+{
+    WDT_CTL_TypeDef wdt_ctl = {.d32 = WDT->WDT_CTL};
+
+    return (WDTMode_TypeDef)(wdt_ctl.b.wdt_mode);
+}
+
+/**
+  * \brief  Set Clock auto mode.
+  * \param  AutoMode: This parameter can ref to \ref Clock_Auto_Mode.
+  * \return Current count
+  */
+void WDT_ClockAutoModeCmd(FunctionalState Newstate)
+{
+    if (Newstate == ENABLE)
+    {
+        WDT->WDT_CLK_QACTIVE_CTL = WDT_CLOCK_AUTO_MODE_CONFIG_AUTOMATIC;
+    }
+    else
+    {
+        WDT->WDT_CLK_QACTIVE_CTL = WDT_CLOCK_AUTO_MODE_CONFIG_ALWAYSRUN;
+    }
+
+    return;
+}
diff --git a/bee/drivers/wdt/src/device/rtl87x2j/rtl_wdt_def.h b/bee/drivers/wdt/src/device/rtl87x2j/rtl_wdt_def.h
new file mode 100644
index 00000000..6d70481e
--- /dev/null
+++ b/bee/drivers/wdt/src/device/rtl87x2j/rtl_wdt_def.h
@@ -0,0 +1,162 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef RTL_WDT_DEF_H
+#define RTL_WDT_DEF_H
+
+#include "utils/rtl_utils.h"
+#include "address_map.h"
+#include "platform_reg.h"
+
+#ifdef  __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/*============================================================================*
+ *                          WDT Defines
+ *============================================================================*/
+
+#define WDT_SUPPORT_AUTO_CLOCK                         (1)
+#define WDT_SUPPORT_GET_CURRENT_COUNTER                (1)
+
+/*============================================================================*
+ *                          WDT Registers Memory Map
+ *============================================================================*/
+typedef struct
+{
+    __IO uint32_t WDT_CTL;                      /*!< 0x00 */
+    __IO uint32_t WDT_KICK;                     /*!< 0x04 */
+    __I  uint32_t WDT_CURRENT;                  /*!< 0x08 */
+    __I  uint32_t WDT_VER;                      /*!< 0x0C */
+    __IO uint32_t WDT_CLK_QACTIVE_CTL;          /*!< 0x10 */
+} WDT_TypeDef;
+
+/*============================================================================*
+ *                          WDT Declaration
+ *============================================================================*/
+/** \defgroup WDT         WDT
+  * \brief
+  * \{
+  */
+
+/** \defgroup WDT_Exported_Constants WDT Exported Constants
+  * \brief
+  * \{
+  */
+
+/** \defgroup WDT_Declaration WDT Declaration
+  * \brief
+  * \{
+  */
+
+#define WDT_REG_BASE       (0x40006000 + PLATFORM_REG_WDT_CTL)
+#define WDT                ((WDT_TypeDef *) WDT_REG_BASE)
+
+
+/** End of WDT_Declaration
+  * \}
+  */
+
+/** End of WDT_Exported_Constants
+  * \}
+  */
+
+/** End of WDT
+  * \}
+  */
+
+/*============================================================================*
+ *                          WDT Private Types
+ *============================================================================*/
+
+/*============================================================================*
+ *                          WDT Registers and Field Descriptions
+ *============================================================================*/
+/* 0x00
+   27:0    R/W    wdt_cnt_limit               28'h4E200
+   29:28   R/W    wdt_mode                    2'h0
+   30      R/W1C  wdt_to                      1'h0
+   31      R/W    wdt_en                      1'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t wdt_cnt_limit: 28;
+        uint32_t wdt_mode: 2;
+        uint32_t wdt_to: 1;
+        uint32_t wdt_en: 1;
+    } b;
+} WDT_CTL_TypeDef;
+
+
+/* 0x04
+   15:0    R/WAC  wdt_kick                    16'h0
+   31:16   R      reserved                    16'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t wdt_kick: 16;
+        const uint32_t reserved_0: 16;
+    } b;
+} WDT_KICK_TypeDef;
+
+
+/* 0x08
+   27:0    R      wdt_current                 28'h0
+   31:28   R      reserved                    4'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t wdt_current: 28;
+        const uint32_t reserved_0: 4;
+    } b;
+} WDT_CURRENT_TypeDef;
+
+
+/* 0x0C
+   31:0    R      wdt_ver                     32'h2409030A
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        const uint32_t wdt_ver: 32;
+    } b;
+} WDT_VER_TypeDef;
+
+
+/* 0x10
+   0       R/W    wdt_clk_qactive_man_data    1'h0
+   1       R/W    wdt_clk_qactive_man_enable  1'h0
+   31:2    R      reserved                    30'h0
+*/
+typedef union
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t wdt_clk_qactive_man_data: 1;
+        uint32_t wdt_clk_qactive_man_enable: 1;
+        const uint32_t reserved_0: 30;
+    } b;
+} WDT_CLK_QACTIVE_CTL_TypeDef;
+
+
+
+#ifdef  __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* RTL_WDT_DEF_H */
diff --git a/bee/ld/CMakeLists.txt b/bee/ld/CMakeLists.txt
new file mode 100644
index 00000000..26a8f001
--- /dev/null
+++ b/bee/ld/CMakeLists.txt
@@ -0,0 +1,7 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+add_subdirectory_ifdef(CONFIG_SOC_SERIES_RTL87X2G rtl87x2g)
+add_subdirectory_ifdef(CONFIG_SOC_SERIES_RTL87X2J rtl87x2j)
+add_subdirectory_ifdef(CONFIG_SOC_SERIES_RTL8752H rtl8752h)
+zephyr_include_directories(inc)
diff --git a/bee/ld/inc/app_section.h b/bee/ld/inc/app_section.h
new file mode 100644
index 00000000..9c986486
--- /dev/null
+++ b/bee/ld/inc/app_section.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file app_sections.h
+ * @brief Section definition mapping for Zephyr compatibility.
+ *
+ * This file adapts the Realtek Bee HAL section macros for the Zephyr environment.
+ * Some driver sources in the Realtek Bee HAL rely on macros defined in `app_sections.h`.
+ * To maintain the integrity of the HAL source code without modifications, we redefine
+ * these macros here to align with Zephyr's linker script conventions.
+ *
+ * Mapping Strategy:
+ * - RAM Functions: Mapped to Zephyr's `__ramfunc` section (e.g., APP_RAM_TEXT_SECTION).
+ * - Unsupported/Unused Sections: Defined as empty (NULL) if they have no direct equivalent
+ *   or necessity in the Zephyr build system.
+ *
+ * Note: For general code or data relocation requirements in Zephyr applications,
+ * please refer to the official "Code and Data Relocation" documentation:
+ * https://docs.zephyrproject.org/latest/kernel/code-relocation.html
+ */
+
+#include <zephyr/linker/sections.h>
+
+#define APP_RAM_TEXT_SECTION __ramfunc
+#define RAM_FUNCTION         __ramfunc
+#define DATA_RAM_FUNCTION     __ramfunc
+#define RAM_TEXT_SECTION __ramfunc
+
+#define APP_FLASH_HEADER
+#define APP_FLASH_HEADER_EXT
+#define APP_FLASH_START_SECTION
+#define APP_FLASH_TEXT_SECTION
+#define APP_FLASH_RODATA_SECTION
+#define APP_FLASH_GAP_TEXT_SECTION
+#define APP_RAM_DATA_SECTION
+#define APP_RAM_START_SECTION
+#define APP_PSRAM_SECTION
+#define APP_ENCRYPTION_SIGNATURE
+#define APP_ENCRYPION_DUMMY_ALIGN
+#define APP_ENCRYPTION_TEXT_SECTION
+#define EXT_RAM_DATA
+#define ISR_TEXT_SECTION
+#define SHARE_CACHE_RAM_SECTION
+#define RAM_DATAON_DATA_SECTION
+#define RAM_DATAON_BSS_SECTION
+#define RAM_DATAON_UNINIT_SECTION
+#define RAM_BUFFERON_DATA_SECTION
+#define RAM_BUFFERON_BSS_SECTION
diff --git a/bee/ld/inc/section.h b/bee/ld/inc/section.h
new file mode 100644
index 00000000..8dd11481
--- /dev/null
+++ b/bee/ld/inc/section.h
@@ -0,0 +1,7 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <app_section.h>
diff --git a/bee/ld/rtl8752h/CMakeLists.txt b/bee/ld/rtl8752h/CMakeLists.txt
new file mode 100644
index 00000000..0d317a50
--- /dev/null
+++ b/bee/ld/rtl8752h/CMakeLists.txt
@@ -0,0 +1,5 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_link_libraries(gcc -T${CMAKE_CURRENT_SOURCE_DIR}/bt_controller.ld)
+zephyr_link_libraries(gcc -T${CMAKE_CURRENT_SOURCE_DIR}/ROM.ld)
diff --git a/bee/ld/rtl8752h/ROM.ld b/bee/ld/rtl8752h/ROM.ld
new file mode 100644
index 00000000..5500789b
--- /dev/null
+++ b/bee/ld/rtl8752h/ROM.ld
@@ -0,0 +1,289 @@
+SECTIONS
+{
+    PROVIDE(HardFault_Handler = 0x00000101);
+    PROVIDE(ROM_Default_Handler = 0x0000015f);
+    PROVIDE(hal_setup_hardware = 0x00000da7);
+    PROVIDE(hal_setup_cpu = 0x00000ec7);
+    PROVIDE(share_cache_ram = 0x00001025);
+    PROVIDE(SystemCall = 0x0000181b);
+    PROVIDE(SystemCall_Stack = 0x00001827);
+    PROVIDE(update_ram_layout = 0x00001841);
+    PROVIDE(get_active_ota_bank_addr = 0x000029a1);
+    PROVIDE(Peripheral_Handler = 0x000032fd);
+    PROVIDE(RamVectorTableInit = 0x000034c3);
+    PROVIDE(RamVectorTableUpdate = 0x000034e9);
+    PROVIDE(PPB_BufSwitch = 0x00003545);
+    PROVIDE(PPB_Init = 0x00003569);
+    PROVIDE(PPB_Uninit = 0x000035bd);
+    PROVIDE(PPB_Init_DLPS_Restore = 0x000035e1);
+    PROVIDE(PPB_Write = 0x000035e9);
+    PROVIDE(PPB_ClearOutputBuffer = 0x000036c7);
+    PROVIDE(log_direct = 0x000038f5);
+    PROVIDE(log_buffer = 0x0000399b);
+    PROVIDE(log_buffer_lowerstack = 0x00003b8b);
+    PROVIDE(log_snoop = 0x00003c6b);
+    PROVIDE(trace_bdaddr = 0x00003d6b);
+    PROVIDE(trace_string = 0x00003df7);
+    PROVIDE(trace_binary = 0x00003e97);
+    PROVIDE(LogBufferLowerStack = 0x00003f35);
+    PROVIDE(LogBufferLowerStackData = 0x0000405f);
+    PROVIDE(log_module_trace_init = 0x0000413b);
+    PROVIDE(log_module_trace_set = 0x0000415f);
+    PROVIDE(log_module_bitmap_trace_set = 0x000041ab);
+    PROVIDE(log_buffer_optimise_enable = 0x00004211);
+    PROVIDE(LogUartDMAStart = 0x000042af);
+    PROVIDE(LogDMA_SM_Dispatch = 0x000042c1);
+    PROVIDE(LogUartDMAInit = 0x00004349);
+    PROVIDE(LogUartDMAIdleHook = 0x00004449);
+    PROVIDE(log_pm_check = 0x000044b7);
+    PROVIDE(hw_aes_create_mutex = 0x00004561);
+    PROVIDE(hw_aes_encrypt128_use_dma = 0x0000470d);
+    PROVIDE(hw_aes_decrypt128_use_dma = 0x00004751);
+    PROVIDE(swap_buf = 0x00004795);
+    PROVIDE(aes128_ecb_encrypt = 0x000047ad);
+    PROVIDE(aes128_ecb_decrypt = 0x00004811);
+    PROVIDE(aes128_ecb_encrypt_msb2lsb = 0x00004873);
+    PROVIDE(aes128_ecb_decrypt_msb2lsb = 0x0000488b);
+    PROVIDE(aes256_ecb_encrypt = 0x000048a3);
+    PROVIDE(aes256_ecb_decrypt = 0x0000490b);
+    PROVIDE(aes256_ecb_encrypt_msb2lsb = 0x00004985);
+    PROVIDE(aes256_ecb_decrypt_msb2lsb = 0x0000499d);
+    PROVIDE(hw_aes_decrypt_16byte = 0x000049e1);
+    PROVIDE(set_hci_mode_flag = 0x00006011);
+    PROVIDE(check_hci_mode_flag = 0x0000603f);
+    PROVIDE(check_image_chksum = 0x0000616b);
+    PROVIDE(check_header_valid = 0x00006195);
+    PROVIDE(get_image_addr_in_bank = 0x0000628b);
+    PROVIDE(get_image_size_in_bank = 0x00006295);
+    PROVIDE(get_header_addr_by_img_id = 0x000062a1);
+    PROVIDE(get_active_bank_image_size_by_img_id = 0x000062ef);
+    PROVIDE(is_ota_support_bank_switch = 0x0000633f);
+    PROVIDE(get_temp_ota_bank_addr_by_img_id = 0x0000636b);
+    PROVIDE(get_temp_ota_bank_size_by_img_id = 0x000063e1);
+    PROVIDE(get_active_bank_image_version = 0x000064c7);
+    PROVIDE(image_entry_check = 0x0000651b);
+    PROVIDE(platform_random = 0x000065e7);
+    PROVIDE(init_osc_sdm_timer = 0x00007883);
+    PROVIDE(btaon_fast_read = 0x0000a1d3);
+    PROVIDE(btaon_fast_read_8b = 0x0000a1e7);
+    PROVIDE(btaon_fast_read_safe = 0x0000a207);
+    PROVIDE(btaon_fast_read_safe_8b = 0x0000a223);
+    PROVIDE(btaon_fast_write = 0x0000a24d);
+    PROVIDE(btaon_fast_write_8b = 0x0000a26d);
+    PROVIDE(btaon_fast_write_safe = 0x0000a2ab);
+    PROVIDE(btaon_fast_write_safe_8b = 0x0000a2d5);
+    PROVIDE(btaon_fast_update = 0x0000a31b);
+    PROVIDE(btaon_fast_update_8b = 0x0000a335);
+    PROVIDE(btaon_fast_update_safe = 0x0000a351);
+    PROVIDE(btaon_fast_update_safe_8b = 0x0000a36d);
+    PROVIDE(flash_nor_get_exist = 0x0000e18b);
+    PROVIDE(flash_nor_set_seq_trans = 0x0000e363);
+    PROVIDE(flash_nor_get_flash_size = 0x0000e3ab);
+    PROVIDE(flash_nor_get_addr_base = 0x0000f8c9);
+    PROVIDE(flash_nor_set_all_info = 0x0000f9bf);
+    PROVIDE(flash_nor_auto_read = 0x0000fcff);
+    PROVIDE(flash_nor_auto_dma_read = 0x0000ff61);
+    PROVIDE(flash_nor_get_bank_addr = 0x00010a59);
+    PROVIDE(flash_nor_get_bank_size = 0x00010ac5);
+    PROVIDE(flash_nor_dump_flash_info = 0x00010b27);
+    PROVIDE(flash_nor_ioctl = 0x00010e0d);
+    PROVIDE(flash_nor_auto_read_locked = 0x00010f1f);
+    PROVIDE(flash_nor_set_seq_trans_enable = 0x00011135);
+    PROVIDE(flash_nor_get_id = 0x0001113d);
+    PROVIDE(os_mem_alloc_intern = 0x00015fb5);
+    PROVIDE(os_mem_zalloc_intern = 0x0001600f);
+    PROVIDE(os_mem_aligned_alloc_intern = 0x00016071);
+    PROVIDE(os_mem_free = 0x000160d1);
+    PROVIDE(os_mem_aligned_free = 0x000160ed);
+    PROVIDE(os_mem_peek = 0x00016109);
+    PROVIDE(os_mem_check_heap_usage = 0x0001612b);
+    PROVIDE(os_msg_queue_create_intern = 0x00016165);
+    PROVIDE(os_msg_queue_delete_intern = 0x000161d9);
+    PROVIDE(os_msg_queue_peek_intern = 0x00016223);
+    PROVIDE(os_msg_send_intern = 0x00016277);
+    PROVIDE(os_msg_recv_intern = 0x000162d3);
+    PROVIDE(os_msg_peek_intern = 0x00016331);
+    PROVIDE(os_queue_init = 0x000163b1);
+    PROVIDE(os_queue_in = 0x000163bb);
+    PROVIDE(os_queue_out = 0x000163eb);
+    PROVIDE(os_queue_peek = 0x00016421);
+    PROVIDE(os_queue_insert = 0x00016425);
+    PROVIDE(os_queue_delete = 0x00016465);
+    PROVIDE(os_systick_handler = 0x000164d1);
+    PROVIDE(os_delay = 0x000164e7);
+    PROVIDE(os_sys_time_get = 0x00016503);
+    PROVIDE(os_sys_tick_get = 0x00016521);
+    PROVIDE(os_sys_tick_increase = 0x0001653f);
+    PROVIDE(os_sched_start = 0x00016563);
+    PROVIDE(os_sched_stop = 0x00016581);
+    PROVIDE(os_sched_suspend = 0x0001659f);
+    PROVIDE(os_sched_resume = 0x000165bd);
+    PROVIDE(os_sched_is_start = 0x000165db);
+    PROVIDE(os_sched_state_get = 0x000165f9);
+    PROVIDE(os_vector_table_update = 0x00016617);
+    PROVIDE(os_init = 0x0001662d);
+    PROVIDE(os_lock = 0x00016679);
+    PROVIDE(os_unlock = 0x00016695);
+    PROVIDE(os_sem_create = 0x000166b1);
+    PROVIDE(os_sem_delete = 0x000166e5);
+    PROVIDE(os_sem_take = 0x00016709);
+    PROVIDE(os_sem_give = 0x00016731);
+    PROVIDE(os_mutex_create = 0x00016755);
+    PROVIDE(os_mutex_delete = 0x00016779);
+    PROVIDE(os_mutex_take = 0x0001679d);
+    PROVIDE(os_mutex_give = 0x000167c5);
+    PROVIDE(os_task_create = 0x00016811);
+    PROVIDE(os_task_delete = 0x0001684d);
+    PROVIDE(os_task_suspend = 0x00016871);
+    PROVIDE(os_task_resume = 0x00016895);
+    PROVIDE(os_task_yield = 0x000168b9);
+    PROVIDE(os_task_handle_get = 0x000168d7);
+    PROVIDE(os_task_priority_get = 0x000168fb);
+    PROVIDE(os_task_priority_set = 0x00016923);
+    PROVIDE(os_task_signal_create = 0x0001694b);
+    PROVIDE(os_task_status_dump = 0x00016973);
+    PROVIDE(os_task_dlps_return_idle_task = 0x00016989);
+    PROVIDE(os_task_notify_take = 0x0001699f);
+    PROVIDE(os_task_notify_give = 0x000169cb);
+    PROVIDE(os_timer_id_get = 0x00016a25);
+    PROVIDE(os_timer_create = 0x00016a61);
+    PROVIDE(os_timer_start = 0x00016a9d);
+    PROVIDE(os_timer_restart = 0x00016ac1);
+    PROVIDE(os_timer_stop = 0x00016ae9);
+    PROVIDE(os_timer_delete = 0x00016b0d);
+    PROVIDE(os_timer_dump = 0x00016b31);
+    PROVIDE(os_timer_state_get = 0x00016b4f);
+    PROVIDE(os_timer_init = 0x00016b8b);
+    PROVIDE(os_timer_number_get = 0x00016ba1);
+    PROVIDE(os_timer_pend_function_call = 0x00016bc9);
+    PROVIDE(os_timer_get_auto_reload = 0x00016bf5);
+    PROVIDE(os_timer_is_timer_active = 0x00016c1d);
+    PROVIDE(hw_sha256_init = 0x0001aecd);
+    PROVIDE(boot_cfg = 0x00200138);
+    PROVIDE(sys_init_cfg = 0x002001b4);
+    PROVIDE(pMCU_PPB = 0x00200298);
+    PROVIDE(pLogDMA_SM = 0x0020029c);
+    PROVIDE(platform_delay_us = 0x002002b4);
+    PROVIDE(platform_delay_ms = 0x002002b8);
+    PROVIDE(set_up_32k_clk_src = 0x00200308);
+    PROVIDE(set_active_mode_clk_src = 0x0020039c);
+    PROVIDE(work_around_32k_power_glitch = 0x002003a0);
+    PROVIDE(work_around_32k_power_glitch_after_restart = 0x002003a4);
+    PROVIDE(platform_rtc_aon_init = 0x0020089c);
+    PROVIDE(ft_paras_apply = 0x002008e8);
+    PROVIDE(si_flow_data_init = 0x002008f0);
+    PROVIDE(si_flow_after_power_on_sequence_restart = 0x002008f8);
+    PROVIDE(pmu_apply_voltage_tune = 0x00200980);
+    PROVIDE(pmu_power_on_sequence_restart = 0x00200990);
+    PROVIDE(power_manager_master_init = 0x00200a48);
+    PROVIDE(power_manager_slave_init = 0x00200aa0);
+    PROVIDE(platform_pm_init = 0x00200b14);
+    PROVIDE(os_sched_restore = 0x00200b18);
+    PROVIDE(os_sys_tick_rate_get = 0x00200b1c);
+    PROVIDE(os_sys_tick_clk_get = 0x00200b20);
+    PROVIDE(os_pm_next_timeout_value_get = 0x00200b24);
+    PROVIDE(os_register_pm_excluded_handle = 0x00200b28);
+    PROVIDE(os_unregister_pm_excluded_handle = 0x00200b2c);
+    PROVIDE(os_pm_store_tickcount = 0x00200b30);
+    PROVIDE(os_pm_restore_tickcount = 0x00200b34);
+    PROVIDE(os_pm_check = 0x00200b38);
+    PROVIDE(os_pm_store = 0x00200b3c);
+    PROVIDE(os_pm_restore = 0x00200b40);
+    PROVIDE(os_pm_init = 0x00200b44);
+    PROVIDE(phy_hw_control_init = 0x00200b54);
+    PROVIDE(phy_init = 0x00200b90);
+    PROVIDE(flash_nor_load_query_info = 0x00200d34);
+    PROVIDE(flash_nor_get_bit_mode = 0x00200d68);
+    PROVIDE(flash_nor_set_bp_lv = 0x00200d74);
+    PROVIDE(flash_nor_try_high_speed_mode = 0x00200db0);
+    PROVIDE(flash_nor_set_tb_bit = 0x00200db8);
+    PROVIDE(flash_nor_erase_locked = 0x00200dc4);
+    PROVIDE(flash_nor_write_locked = 0x00200dc8);
+    PROVIDE(flash_nor_read_locked = 0x00200dcc);
+    PROVIDE(check_flash_bp_before_ota_copy = 0x00200dd0);
+    PROVIDE(flash_nor_get_default_bp_lv = 0x00200dd4);
+    PROVIDE(flash_nor_unlock_bp_all = 0x00200dd8);
+    PROVIDE(flash_nor_unlock_bp_by_addr_locked = 0x00200ddc);
+    PROVIDE(flash_nor_set_bp_lv_locked = 0x00200de0);
+    PROVIDE(flash_nor_set_tb_bit_locked = 0x00200de4);
+    PROVIDE(flash_nor_get_bp_lv_locked = 0x00200de8);
+    PROVIDE(hw_sha256_start = 0x00200e50);
+    PROVIDE(hw_sha256_cpu_update = 0x00200e5c);
+    PROVIDE(hw_sha256_finish = 0x00200e60);
+    PROVIDE(hw_sha256 = 0x00200e70);
+    PROVIDE(app_pre_main = 0x00200e7c);
+    PROVIDE(vector_table_level_two = 0x00200e80);
+    PROVIDE(upperstack_entry = 0x00200e84);
+    PROVIDE(app_main = 0x00200e88);
+    PROVIDE(is_log_init = 0x00200f16);
+    PROVIDE(flash_sem = 0x0020137c);
+    PROVIDE(flash_nor_ioctl_buf = 0x00201434);
+    PROVIDE(flash_nor_ioctl_buf_len = 0x00201438);
+    PROVIDE(patch_WDG_Config = 0x00201674);
+    PROVIDE(patch_osif_os_systick_handler = 0x0020167c);
+    PROVIDE(patch_osif_os_delay = 0x00201680);
+    PROVIDE(patch_osif_os_sys_time_get = 0x00201684);
+    PROVIDE(patch_osif_os_sys_tick_get = 0x00201688);
+    PROVIDE(patch_osif_os_sys_tick_increase = 0x0020168c);
+    PROVIDE(patch_osif_os_sched_start = 0x00201690);
+    PROVIDE(patch_osif_os_sched_stop = 0x00201694);
+    PROVIDE(patch_osif_os_sched_suspend = 0x00201698);
+    PROVIDE(patch_osif_os_sched_resume = 0x0020169c);
+    PROVIDE(patch_osif_os_sched_is_start = 0x002016a0);
+    PROVIDE(patch_osif_os_sched_state_get = 0x002016a4);
+    PROVIDE(patch_osif_os_vector_table_update = 0x002016a8);
+    PROVIDE(patch_osif_os_init = 0x002016ac);
+    PROVIDE(patch_osif_os_task_create = 0x002016b0);
+    PROVIDE(patch_osif_os_task_delete = 0x002016b4);
+    PROVIDE(patch_osif_os_task_suspend = 0x002016b8);
+    PROVIDE(patch_osif_os_task_resume = 0x002016bc);
+    PROVIDE(patch_osif_os_task_yield = 0x002016c0);
+    PROVIDE(patch_osif_os_task_handle_get = 0x002016c4);
+    PROVIDE(patch_osif_os_task_priority_get = 0x002016c8);
+    PROVIDE(patch_osif_os_task_priority_set = 0x002016cc);
+    PROVIDE(patch_osif_os_task_signal_create = 0x002016d0);
+    PROVIDE(patch_osif_os_task_status_dump = 0x002016d4);
+    PROVIDE(patch_osif_os_task_dlps_return_idle_task = 0x002016d8);
+    PROVIDE(patch_osif_os_task_notify_take = 0x002016dc);
+    PROVIDE(patch_osif_os_task_notify_give = 0x002016e0);
+    PROVIDE(patch_osif_os_lock = 0x002016e4);
+    PROVIDE(patch_osif_os_unlock = 0x002016e8);
+    PROVIDE(patch_osif_os_sem_create = 0x002016ec);
+    PROVIDE(patch_osif_os_sem_delete = 0x002016f0);
+    PROVIDE(patch_osif_os_sem_take = 0x002016f4);
+    PROVIDE(patch_osif_os_sem_give = 0x002016f8);
+    PROVIDE(patch_osif_os_mutex_create = 0x002016fc);
+    PROVIDE(patch_osif_os_mutex_delete = 0x00201700);
+    PROVIDE(patch_osif_os_mutex_take = 0x00201704);
+    PROVIDE(patch_osif_os_mutex_give = 0x00201708);
+    PROVIDE(patch_osif_os_msg_queue_create_intern = 0x0020170c);
+    PROVIDE(patch_osif_os_msg_queue_delete_intern = 0x00201710);
+    PROVIDE(patch_osif_os_msg_queue_peek_intern = 0x00201714);
+    PROVIDE(patch_osif_os_msg_send_intern = 0x00201718);
+    PROVIDE(patch_osif_os_msg_recv_intern = 0x0020171c);
+    PROVIDE(patch_osif_os_msg_peek_intern = 0x00201720);
+    PROVIDE(patch_osif_os_mem_alloc_intern = 0x00201724);
+    PROVIDE(patch_osif_os_mem_zalloc_intern = 0x00201728);
+    PROVIDE(patch_osif_os_mem_aligned_alloc_intern = 0x0020172c);
+    PROVIDE(patch_osif_os_mem_free = 0x00201730);
+    PROVIDE(patch_osif_os_mem_aligned_free = 0x00201734);
+    PROVIDE(patch_osif_os_mem_peek = 0x00201738);
+    PROVIDE(patch_osif_os_mem_check_heap_usage = 0x0020173c);
+    PROVIDE(patch_osif_os_queue_in = 0x00201740);
+    PROVIDE(patch_osif_os_queue_out = 0x00201744);
+    PROVIDE(patch_osif_os_queue_insert = 0x00201748);
+    PROVIDE(patch_osif_os_queue_delete = 0x0020174c);
+    PROVIDE(patch_osif_os_timer_id_get = 0x00201750);
+    PROVIDE(patch_osif_os_timer_create = 0x00201754);
+    PROVIDE(patch_osif_os_timer_start = 0x00201758);
+    PROVIDE(patch_osif_os_timer_restart = 0x0020175c);
+    PROVIDE(patch_osif_os_timer_stop = 0x00201760);
+    PROVIDE(patch_osif_os_timer_delete = 0x00201764);
+    PROVIDE(patch_osif_os_timer_dump = 0x00201768);
+    PROVIDE(patch_osif_os_timer_state_get = 0x0020176c);
+    PROVIDE(patch_osif_os_timer_init = 0x00201770);
+    PROVIDE(patch_osif_os_timer_number_get = 0x00201774);
+    PROVIDE(patch_osif_os_timer_pend_function_call = 0x00201778);
+    PROVIDE(patch_osif_os_timer_get_auto_reload = 0x0020177c);
+    PROVIDE(patch_osif_os_timer_is_timer_active = 0x00201780);
+}
diff --git a/bee/ld/rtl8752h/bt_controller.ld b/bee/ld/rtl8752h/bt_controller.ld
new file mode 100644
index 00000000..0f3dbf49
--- /dev/null
+++ b/bee/ld/rtl8752h/bt_controller.ld
@@ -0,0 +1,12 @@
+SECTIONS
+{
+    PROVIDE(vhci_has_sig_pended = 0x0004a383);
+    PROVIDE(GDMA0_Channel2_Handler = 0x0004ab87);
+    PROVIDE(GDMA0_Channel1_Handler = 0x0004ab9b);
+    PROVIDE(BTMAC_Handler = 0x00050359);
+    PROVIDE(vhci_ack = 0x00202b2c);
+    PROVIDE(vhci_ack_nowake = 0x00202b30);
+    PROVIDE(vhci_close = 0x00202b34);
+    PROVIDE(vhci_open = 0x00202b38);
+    PROVIDE(vhci_send = 0x00202b3c);
+}
diff --git a/bee/ld/rtl87x2g/CMakeLists.txt b/bee/ld/rtl87x2g/CMakeLists.txt
new file mode 100644
index 00000000..5da932ad
--- /dev/null
+++ b/bee/ld/rtl87x2g/CMakeLists.txt
@@ -0,0 +1,6 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_link_libraries(gcc -T${CMAKE_CURRENT_SOURCE_DIR}/bt_controller.ld)
+zephyr_link_libraries(gcc -T${CMAKE_CURRENT_SOURCE_DIR}/ROM_S.ld)
+zephyr_link_libraries(gcc -T${CMAKE_CURRENT_SOURCE_DIR}/ROM_NS.ld)
diff --git a/bee/ld/rtl87x2g/ROM_NS.ld b/bee/ld/rtl87x2g/ROM_NS.ld
new file mode 100644
index 00000000..1addb1e8
--- /dev/null
+++ b/bee/ld/rtl87x2g/ROM_NS.ld
@@ -0,0 +1,146 @@
+SECTIONS
+{
+    PROVIDE(os_queue_func_init = 0x0001d1e1);
+    PROVIDE(Default_Handler_rom = 0x0001e20d);
+    PROVIDE(LogUartTxData = 0x0001e6fd);
+    PROVIDE(RamVectorTableInit = 0x0001f509);
+    PROVIDE(RamVectorTableUpdate = 0x0001f5a5);
+    PROVIDE(clk_cnt_cmp = 0x00020d15);
+    PROVIDE(clk_cnt_diff = 0x00020db9);
+    PROVIDE(dwt_cyccnt_init = 0x00021f79);
+    PROVIDE(empty_function = 0x00022029);
+    PROVIDE(fill_log_data = 0x00022145);
+    PROVIDE(flash_nor_ioctl = 0x00022271);
+    PROVIDE(get_sys_tick_clk_type = 0x00022b8d);
+    PROVIDE(hw_aes_mutex_init = 0x0002380d);
+    PROVIDE(init_osc_sdm_timer = 0x00023a11);
+    PROVIDE(is_overlapped = 0x00023ee1);
+    PROVIDE(log_buffer = 0x00023fd1);
+    PROVIDE(log_buffer_lowerstack = 0x000241d9);
+    PROVIDE(log_module_bitmap_trace_set = 0x00024515);
+    PROVIDE(log_module_trace_init = 0x0002454d);
+    PROVIDE(os_register_pm_excluded_handle_imp = 0x00028215);
+    PROVIDE(os_unregister_pm_excluded_handle_imp = 0x000287dd);
+    PROVIDE(read_cpu_counter = 0x0002d351);
+    PROVIDE(register_log_dest_cb = 0x0002d395);
+    PROVIDE(reverse_bits_in_word = 0x0002d3c9);
+    PROVIDE(rtc_clk_to_us = 0x0002d8f5);
+    PROVIDE(secure_os_func_ptr_init_rom = 0x0002dae1);
+    PROVIDE(true_function = 0x0002f495);
+    PROVIDE(update_cpu_tick_to_us = 0x0002f761);
+    PROVIDE(us_to_rtc_clk = 0x0002f849);
+    PROVIDE(vAssertHandler = 0x0002fc61);
+    PROVIDE(void_ptr_function = 0x00030d65);
+    PROVIDE(RamVectorTable = 0x0013cc00);
+    PROVIDE(hal_setup_hardware = 0x0013cef0);
+    PROVIDE(mpu_setup = 0x0013cef4);
+    PROVIDE(hal_setup_cpu = 0x0013cef8);
+    PROVIDE(hal_setup_fpu = 0x0013cefc);
+    PROVIDE(system_restore = 0x0013cf00);
+    PROVIDE(SystemCoreClock = 0x0013d318);
+    PROVIDE(cal_quotient_remainder = 0x0013d398);
+    PROVIDE(dvfs_init = 0x0013d468);
+    PROVIDE(ft_paras_apply = 0x0013d4e8);
+    PROVIDE(get_SystemCpuClock = 0x0013d510);
+    PROVIDE(get_stack_en = 0x0013d54c);
+    PROVIDE(log_buffer_init = 0x0013d5a0);
+    PROVIDE(log_direct = 0x0013d5ac);
+    PROVIDE(log_gdma_init = 0x0013d5b0);
+    PROVIDE(log_snoop = 0x0013d5bc);
+    PROVIDE(log_timestamp_get = 0x0013d5c0);
+    PROVIDE(os_lock = 0x0013d7bc);
+    PROVIDE(os_unlock = 0x0013d7c4);
+    PROVIDE(phy_hw_control_init = 0x0013d7d8);
+    PROVIDE(phy_init = 0x0013d7dc);
+    PROVIDE(platform_delay_ms = 0x0013d80c);
+    PROVIDE(platform_delay_us = 0x0013d810);
+    PROVIDE(platform_pm_init = 0x0013d834);
+    PROVIDE(platform_rtc_aon_init = 0x0013d8ec);
+    PROVIDE(pmu_apply_voltage_tune = 0x0013d938);
+    PROVIDE(pmu_auto_switch_map_force_base_level = 0x0013d944);
+    PROVIDE(pmu_power_on_sequence_restart = 0x0013d96c);
+    PROVIDE(power_manager_master_init = 0x0013da24);
+    PROVIDE(power_manager_slave_init = 0x0013db40);
+    PROVIDE(secure_os_func_ptr_init = 0x0013dca4);
+    PROVIDE(secure_platform_func_ptr_init = 0x0013dca8);
+    PROVIDE(set_active_mode_clk_src = 0x0013dcb0);
+    PROVIDE(set_lp_module_clk_info = 0x0013dcc8);
+    PROVIDE(set_up_32k_clk_src = 0x0013dce0);
+    PROVIDE(si_flow_data_init = 0x0013dcf8);
+    PROVIDE(thermal_tracking_timer_init = 0x0013de74);
+    PROVIDE(trace_string = 0x0013de88);
+    PROVIDE(flash_nor_ioctl_buf = 0x0013e0a4);
+    PROVIDE(flash_nor_ioctl_buf_len = 0x0013e0a8);
+    PROVIDE(os_alloc_secure_ctx = 0x0013e228);
+    PROVIDE(os_delay = 0x0013e234);
+    PROVIDE(os_init = 0x0013e238);
+    PROVIDE(os_mem_aligned_alloc_intern = 0x0013e23c);
+    PROVIDE(os_mem_aligned_free = 0x0013e240);
+    PROVIDE(os_mem_alloc_intern = 0x0013e244);
+    PROVIDE(os_mem_check_heap_usage = 0x0013e248);
+    PROVIDE(os_mem_free = 0x0013e24c);
+    PROVIDE(os_mem_peek = 0x0013e250);
+    PROVIDE(os_mem_peek_max_free_block = 0x0013e254);
+    PROVIDE(os_mem_peek_printf = 0x0013e258);
+    PROVIDE(os_mem_zalloc_intern = 0x0013e25c);
+    PROVIDE(os_msg_peek_intern = 0x0013e260);
+    PROVIDE(os_msg_queue_create_intern = 0x0013e264);
+    PROVIDE(os_msg_queue_delete_intern = 0x0013e268);
+    PROVIDE(os_msg_queue_peek_intern = 0x0013e26c);
+    PROVIDE(os_msg_recv_intern = 0x0013e270);
+    PROVIDE(os_msg_send_intern = 0x0013e274);
+    PROVIDE(os_mutex_create = 0x0013e278);
+    PROVIDE(os_mutex_delete = 0x0013e27c);
+    PROVIDE(os_mutex_give = 0x0013e280);
+    PROVIDE(os_mutex_take = 0x0013e284);
+    PROVIDE(os_queue_delete = 0x0013e2e0);
+    PROVIDE(os_queue_in = 0x0013e2e4);
+    PROVIDE(os_queue_init = 0x0013e2e8);
+    PROVIDE(os_queue_insert = 0x0013e2ec);
+    PROVIDE(os_queue_out = 0x0013e2f0);
+    PROVIDE(os_queue_peek = 0x0013e2f4);
+    PROVIDE(os_queue_search = 0x0013e2f8);
+    PROVIDE(os_register_pm_excluded_handle = 0x0013e2fc);
+    PROVIDE(os_sched_is_start = 0x0013e300);
+    PROVIDE(os_sched_resume = 0x0013e308);
+    PROVIDE(os_sched_start = 0x0013e30c);
+    PROVIDE(os_sched_state_get = 0x0013e310);
+    PROVIDE(os_sched_stop = 0x0013e314);
+    PROVIDE(os_sched_suspend = 0x0013e318);
+    PROVIDE(os_sem_create = 0x0013e31c);
+    PROVIDE(os_sem_delete = 0x0013e320);
+    PROVIDE(os_sem_give = 0x0013e324);
+    PROVIDE(os_sem_take = 0x0013e328);
+    PROVIDE(os_sys_tick_get = 0x0013e330);
+    PROVIDE(os_sys_time_get = 0x0013e33c);
+    PROVIDE(os_task_create = 0x0013e344);
+    PROVIDE(os_task_delete = 0x0013e348);
+    PROVIDE(os_task_handle_get = 0x0013e34c);
+    PROVIDE(os_task_notify_give = 0x0013e350);
+    PROVIDE(os_task_notify_take = 0x0013e354);
+    PROVIDE(os_task_priority_get = 0x0013e358);
+    PROVIDE(os_task_priority_set = 0x0013e35c);
+    PROVIDE(os_task_resume = 0x0013e360);
+    PROVIDE(os_task_signal_clear = 0x0013e364);
+    PROVIDE(os_task_signal_create = 0x0013e368);
+    PROVIDE(os_task_signal_recv = 0x0013e36c);
+    PROVIDE(os_task_signal_send = 0x0013e370);
+    PROVIDE(os_task_status_dump = 0x0013e374);
+    PROVIDE(os_task_suspend = 0x0013e378);
+    PROVIDE(os_task_yield = 0x0013e37c);
+    PROVIDE(os_timer_create = 0x0013e380);
+    PROVIDE(os_timer_delete = 0x0013e384);
+    PROVIDE(os_timer_dump = 0x0013e388);
+    PROVIDE(os_timer_get_auto_reload = 0x0013e38c);
+    PROVIDE(os_timer_get_timer_number = 0x0013e390);
+    PROVIDE(os_timer_id_get = 0x0013e394);
+    PROVIDE(os_timer_init = 0x0013e398);
+    PROVIDE(os_timer_is_timer_active = 0x0013e39c);
+    PROVIDE(os_timer_pend_function_call = 0x0013e3a0);
+    PROVIDE(os_timer_restart = 0x0013e3a4);
+    PROVIDE(os_timer_start = 0x0013e3a8);
+    PROVIDE(os_timer_state_get = 0x0013e3ac);
+    PROVIDE(os_timer_stop = 0x0013e3b0);
+    PROVIDE(os_unregister_pm_excluded_handle = 0x0013e3c0);
+    PROVIDE(os_vector_table_update = 0x0013e3c4);
+}
diff --git a/bee/ld/rtl87x2g/ROM_S.ld b/bee/ld/rtl87x2g/ROM_S.ld
new file mode 100644
index 00000000..7aaf65f7
--- /dev/null
+++ b/bee/ld/rtl87x2g/ROM_S.ld
@@ -0,0 +1,78 @@
+SECTIONS
+{
+    PROVIDE(Peripheral_Handler = 0x00003705);
+    PROVIDE(WDG_Enable = 0x000040b1);
+    PROVIDE(flash_nor_set_all_info = 0x0000aa79);
+    PROVIDE(swap_buf = 0x0001776f);
+    PROVIDE(get_occd_addr = 0x0001bf89);
+    PROVIDE(get_occd_size = 0x0001bf91);
+    PROVIDE(get_extra_occd_addr = 0x0001bf99);
+    PROVIDE(get_extra_occd_size = 0x0001bfa1);
+    PROVIDE(flash_nor_wait_busy = 0x0001bfc1);
+    PROVIDE(flash_nor_dump_main_info = 0x0001bfc9);
+    PROVIDE(flash_nor_get_bank_addr = 0x0001bfd1);
+    PROVIDE(flash_nor_get_bank_size = 0x0001bfd9);
+    PROVIDE(flash_nor_read_locked = 0x0001bff1);
+    PROVIDE(flash_nor_write_locked = 0x0001bff9);
+    PROVIDE(flash_nor_erase_locked = 0x0001c001);
+    PROVIDE(flash_nor_auto_dma_read_locked = 0x0001c009);
+    PROVIDE(flash_nor_auto_seq_trans_dma_read_locked = 0x0001c011);
+    PROVIDE(flash_nor_get_exist_nsc = 0x0001c021);
+    PROVIDE(flash_nor_set_bp_lv_locked = 0x0001c029);
+    PROVIDE(flash_nor_get_bp_lv_locked = 0x0001c031);
+    PROVIDE(flash_nor_set_tb_bit_locked = 0x0001c039);
+    PROVIDE(flash_nor_try_high_speed_mode = 0x0001c059);
+    PROVIDE(flash_nor_set_seq_trans_enable = 0x0001c061);
+    PROVIDE(flash_nor_set_addr_mode = 0x0001c069);
+    PROVIDE(flash_nor_get_id = 0x0001c071);
+    PROVIDE(flash_nor_cmd_list_init_nsc = 0x0001c0a9);
+    PROVIDE(flash_nor_init_bp_lv_nsc = 0x0001c0b1);
+    PROVIDE(update_cpu_tick_to_us_nsc = 0x0001c169);
+    PROVIDE(platform_random = 0x0001c171);
+    PROVIDE(deinit_swd_pinmux = 0x0001c179);
+    PROVIDE(setup_non_secure_nvic = 0x0001c189);
+    PROVIDE(get_disable_hci_set_uart_baudrate = 0x0001c191);
+    PROVIDE(get_disable_hci_rf_dbg_func = 0x0001c199);
+    PROVIDE(get_disable_hci_read_chip_info = 0x0001c1a1);
+    PROVIDE(get_disable_hci_bt_extension = 0x0001c1a9);
+    PROVIDE(get_airplane_mode = 0x0001c1b1);
+    PROVIDE(set_airplane_mode = 0x0001c1b9);
+    PROVIDE(get_disable_hci_flash_access = 0x0001c1d1);
+    PROVIDE(get_disable_hci_system_access = 0x0001c1d9);
+    PROVIDE(get_disable_hci_wifi_coexist_func = 0x0001c1e1);
+    PROVIDE(get_disable_hci_bt_test = 0x0001c1e9);
+    PROVIDE(get_disable_hci_efuse_access = 0x0001c1f9);
+    PROVIDE(get_default_hci_rx_pin = 0x0001c201);
+    PROVIDE(get_default_hci_tx_pin = 0x0001c209);
+    PROVIDE(get_timer_clk_src_from_40m = 0x0001c211);
+    PROVIDE(get_stack_patch_valid = 0x0001c219);
+    PROVIDE(get_stack_patch_rom_header_addr = 0x0001c221);
+    PROVIDE(enable_nonsecure_access_peri_on_register = 0x0001c229);
+    PROVIDE(is_WDG_Enable = 0x0001c2b1);
+    PROVIDE(WDG_Disable = 0x0001c2b9);
+    PROVIDE(WDG_Kick = 0x0001c2c1);
+    PROVIDE(WDG_Start = 0x0001c2c9);
+    PROVIDE(WDG_SystemReset = 0x0001c2d1);
+    PROVIDE(hw_sha256_init = 0x0001c2e9);
+    PROVIDE(hw_sha256_start = 0x0001c2f1);
+    PROVIDE(hw_sha256_cpu_update = 0x0001c2f9);
+    PROVIDE(hw_sha256_finish = 0x0001c301);
+    PROVIDE(hw_sha256 = 0x0001c309);
+    PROVIDE(secure_app_function_call = 0x0001c3b9);
+    PROVIDE(secure_function_call = 0x0001c3c1);
+    PROVIDE(set_secure_func_ptr = 0x0001c3c9);
+    PROVIDE(aes128_ecb_encrypt = 0x0001c3d9);
+    PROVIDE(aes128_ecb_decrypt = 0x0001c3e1);
+    PROVIDE(aes128_ecb_encrypt_msb2lsb = 0x0001c3e9);
+    PROVIDE(aes128_ecb_decrypt_msb2lsb = 0x0001c3f1);
+    PROVIDE(aes128_cbc_encrypt = 0x0001c3f9);
+    PROVIDE(aes128_cbc_decrypt = 0x0001c401);
+    PROVIDE(aes256_ecb_encrypt = 0x0001c409);
+    PROVIDE(aes256_ecb_decrypt = 0x0001c411);
+    PROVIDE(aes256_ecb_encrypt_msb2lsb = 0x0001c419);
+    PROVIDE(aes256_ecb_decrypt_msb2lsb = 0x0001c421);
+    PROVIDE(aes256_cbc_encrypt = 0x0001c429);
+    PROVIDE(aes256_cbc_decrypt = 0x0001c431);
+    PROVIDE(flash_nor_ioctl_buf = 0x0014f40c);
+    PROVIDE(flash_nor_ioctl_buf_len = 0x0014f410);
+}
diff --git a/bee/ld/rtl87x2g/bt_controller.ld b/bee/ld/rtl87x2g/bt_controller.ld
new file mode 100644
index 00000000..e824aa00
--- /dev/null
+++ b/bee/ld/rtl87x2g/bt_controller.ld
@@ -0,0 +1,28 @@
+SECTIONS
+{
+    PROVIDE(BB_read_baseband_register = 0x00070a3d);
+    PROVIDE(BB_write_baseband_register = 0x00070a75);
+    PROVIDE(BB_read_native_clock = 0x00070ae9);
+    PROVIDE(BB_read_native_counter = 0x00070b37);
+    PROVIDE(bzdma_ble_set_segment_valid_bitmap = 0x00071401);
+    PROVIDE(bzdma_send_burst_rxcmd_and_wait_complete = 0x000720fd);
+    PROVIDE(vhci_has_sig_pended = 0x00073eb5);
+    PROVIDE(BTMAC_Handler = 0x0007a93d);
+    PROVIDE(btmac_pm_check_inactive = 0x0007ace7);
+    PROVIDE(btmac_pm_initiate_wakeup = 0x0007ad2d);
+    PROVIDE(btmac_pm_set_power_mode = 0x0007ad49);
+    PROVIDE(btmac_pm_get_power_mode = 0x0007ad55);
+    PROVIDE(__aeabi_memset = 0x0007e775);
+    PROVIDE(bzdma_supported_le_max_seg_num = 0x0013ea89);
+    PROVIDE(bzdma_send_packet_to_ble_data_ring_fifo = 0x0013edb4);
+    PROVIDE(lowerstack_SystemCall = 0x0013f54c);
+    PROVIDE(vhci_ack = 0x0013f7a4);
+    PROVIDE(vhci_ack_nowake = 0x0013f7a8);
+    PROVIDE(vhci_close = 0x0013f7ac);
+    PROVIDE(vhci_open = 0x0013f7b0);
+    PROVIDE(vhci_send = 0x0013f7b4);
+    PROVIDE(Bzdma_Manager = 0x0013fb54);
+    PROVIDE(g_modem_psd_report_array = 0x0013ffd8);
+    PROVIDE(rcp_BB_handle_psd_end_intr_func = 0x00141218);
+    PROVIDE(rcp_BTMAC_Handler = 0x00141230);
+}
\ No newline at end of file
diff --git a/bee/ld/rtl87x2j/CMakeLists.txt b/bee/ld/rtl87x2j/CMakeLists.txt
new file mode 100644
index 00000000..b5510a2f
--- /dev/null
+++ b/bee/ld/rtl87x2j/CMakeLists.txt
@@ -0,0 +1,7 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_link_libraries(gcc -T${CMAKE_CURRENT_SOURCE_DIR}/bootloader.ld)
+zephyr_link_libraries(gcc -T${CMAKE_CURRENT_SOURCE_DIR}/bt_controller.ld)
+zephyr_link_libraries(gcc -T${CMAKE_CURRENT_SOURCE_DIR}/ROM.ld)
+# zephyr_link_libraries(${CMAKE_CURRENT_SOURCE_DIR}/libdriver.a)
diff --git a/bee/ld/rtl87x2j/ROM.ld b/bee/ld/rtl87x2j/ROM.ld
new file mode 100644
index 00000000..d72f1f9a
--- /dev/null
+++ b/bee/ld/rtl87x2j/ROM.ld
@@ -0,0 +1,47 @@
+SECTIONS
+{
+    PROVIDE(RomVectorTable = 0x00000000);
+    PROVIDE(VTORInit = 0x00000ec9);
+    PROVIDE(WDT_Disable = 0x00000f05);
+    PROVIDE(WDT_Enable = 0x00000f25);
+    PROVIDE(WDT_GetMode = 0x00000f4d);
+    PROVIDE(WDT_GetTimeoutMs = 0x00000f59);
+    PROVIDE(WDT_IsEnable = 0x00000f8d);
+    PROVIDE(WDT_Kick = 0x00000f95);
+    PROVIDE(WDT_Start = 0x00000fb1);
+    PROVIDE(cal_quotient_remainder = 0x0000117d);
+    PROVIDE(check_header_valid = 0x00001221);
+    PROVIDE(check_zero_count = 0x00001349);
+    PROVIDE(clk_cnt_diff = 0x0000135b);
+    PROVIDE(count_zeros = 0x000014bd);
+    PROVIDE(data_cmp = 0x00001725);
+    PROVIDE(default_handler = 0x000017a1);
+    PROVIDE(dump_raw_mem = 0x00001905);
+    PROVIDE(dwt_cyccnt_init = 0x00001a1d);
+    PROVIDE(empty_function = 0x00002429);
+    PROVIDE(image_entry = 0x00002db5);
+    PROVIDE(is_overlapped = 0x00002ea9);
+    PROVIDE(log_buffer = 0x00002ec3);
+    PROVIDE(log_direct = 0x00002f39);
+    PROVIDE(platform_delay_ms = 0x00003291);
+    PROVIDE(platform_delay_us = 0x000032b1);
+    PROVIDE(ram_vector_table_init = 0x000033d1);
+    PROVIDE(ram_vector_table_register = 0x000033f9);
+    PROVIDE(ram_vector_table_update = 0x00003439);
+    PROVIDE(read_cpu_counter = 0x000034d9);
+    PROVIDE(reverse_bits_in_word = 0x000034e5);
+    PROVIDE(saturate_by_boundary = 0x0000387d);
+    PROVIDE(swap_buf = 0x00003a71);
+    PROVIDE(tick_32000_to_us = 0x00003bdd);
+    PROVIDE(tick_32768_to_us = 0x00003bff);
+    PROVIDE(true_function = 0x00003c71);
+    PROVIDE(update_cpu_tick_to_us = 0x00003ca9);
+    PROVIDE(us_to_tick_32000 = 0x00003cc5);
+    PROVIDE(us_to_tick_32768 = 0x00003ce7);
+    PROVIDE(vector_table_ram_init = 0x00003d11);
+    PROVIDE(void_ptr_function = 0x00003d45);
+    PROVIDE(image_integrity_check = 0x20019870);
+    PROVIDE(patch_ram_vector_table_update = 0x200199e8);
+    PROVIDE(platform_random = 0x000032d1);
+    PROVIDE(deinit_true_random_generator = 0x000017c5);
+}
diff --git a/bee/ld/rtl87x2j/bootloader.ld b/bee/ld/rtl87x2j/bootloader.ld
new file mode 100644
index 00000000..a66ba46e
--- /dev/null
+++ b/bee/ld/rtl87x2j/bootloader.ld
@@ -0,0 +1,123 @@
+SECTIONS
+{
+    PROVIDE(srand_bl = 0x0200063d);
+    PROVIDE(GTC_CounterToUs = 0x0200113d);
+    PROVIDE(GTC_UsToCounter = 0x0200117d);
+    PROVIDE(eflash_erase = 0x2006171);
+    PROVIDE(eflash_read = 0x20061ad);
+    PROVIDE(eflash_write = 0x20061ef);
+    PROVIDE(get_soc_rtl_num = 0x020065dd);
+    PROVIDE(image_addr_get = 0x020073d1);
+    PROVIDE(image_customer_name_get = 0x02007419);
+    PROVIDE(image_entry_validation = 0x020076f1);
+    PROVIDE(image_extra_info_get = 0x02007819);
+    PROVIDE(image_header_size_get = 0x02007859);
+    PROVIDE(image_load_addr_get = 0x02007861);
+    PROVIDE(image_load_size_get = 0x020078bd);
+    PROVIDE(image_partition_addr_get = 0x02007959);
+    PROVIDE(image_partition_size_get = 0x020079a1);
+    PROVIDE(image_payload_addr_get = 0x020079f1);
+    PROVIDE(image_payload_size_get = 0x02007a01);
+    PROVIDE(image_size_get = 0x02007a15);
+    PROVIDE(image_temp_addr_get = 0x02007a1d);
+    PROVIDE(image_temp_size_get = 0x02007a7d);
+    PROVIDE(image_version_get = 0x02007ae5);
+    PROVIDE(log_buffer_bt_controller = 0x02007ddd);
+    PROVIDE(log_index = 0x02007ef5);
+    PROVIDE(log_snoop2 = 0x02008061);
+    PROVIDE(log_stream = 0x02008179);
+    PROVIDE(log_trace_bdaddr = 0x020081e5);
+    PROVIDE(log_trace_binary = 0x020081ef);
+    PROVIDE(log_uart_switch_clock_auto_mode = 0x02008375);
+    PROVIDE(os_alloc_secure_ctx = 0x02009621);
+    PROVIDE(os_bottom_half = 0x02009629);
+    PROVIDE(os_delay = 0x02009631);
+    PROVIDE(os_init = 0x02009641);
+    PROVIDE(os_lock = 0x02009649);
+    PROVIDE(os_mem_aligned_alloc_intern = 0x02009651);
+    PROVIDE(os_mem_aligned_free = 0x02009659);
+    PROVIDE(os_mem_alloc_intern = 0x02009661);
+    PROVIDE(os_mem_check_heap_usage = 0x02009669);
+    PROVIDE(os_mem_free = 0x02009671);
+    PROVIDE(os_mem_peek = 0x0200968d);
+    PROVIDE(os_mem_peek_max_free_block = 0x02009695);
+    PROVIDE(os_mem_realloc_intern = 0x0200969d);
+    PROVIDE(os_mem_zalloc_intern = 0x020096a5);
+    PROVIDE(os_msg_peek_intern = 0x020096ad);
+    PROVIDE(os_msg_queue_create_intern = 0x020096b5);
+    PROVIDE(os_msg_queue_delete_intern = 0x020096c5);
+    PROVIDE(os_msg_queue_peek_intern = 0x020096cd);
+    PROVIDE(os_msg_recv_intern = 0x020096d5);
+    PROVIDE(os_msg_send_intern = 0x020096dd);
+    PROVIDE(os_mutex_create = 0x020096e5);
+    PROVIDE(os_mutex_delete = 0x020096ed);
+    PROVIDE(os_mutex_give = 0x020096f5);
+    PROVIDE(os_mutex_take = 0x020096fd);
+    PROVIDE(os_pm_excluded_handle_register = 0x02009705);
+    PROVIDE(os_pm_excluded_handle_unregister = 0x0200970d);
+    PROVIDE(os_pm_init = 0x02009715);
+    PROVIDE(os_pm_next_timeout_value_get = 0x0200971d);
+    PROVIDE(os_pm_tickcount_restore = 0x02009725);
+    PROVIDE(os_pm_tickcount_store = 0x0200972d);
+    PROVIDE(os_sched_restore = 0x02009735);
+    PROVIDE(os_sched_resume = 0x0200973d);
+    PROVIDE(os_sched_start = 0x02009745);
+    PROVIDE(os_sched_state_get = 0x0200974d);
+    PROVIDE(os_sched_stop = 0x02009755);
+    PROVIDE(os_sched_suspend = 0x0200975d);
+    PROVIDE(os_sem_create = 0x02009765);
+    PROVIDE(os_sem_delete = 0x02009775);
+    PROVIDE(os_sem_give = 0x0200977d);
+    PROVIDE(os_sem_take = 0x02009785);
+    PROVIDE(os_sys_tick_get = 0x0200978d);
+    PROVIDE(os_sys_time_get = 0x02009795);
+    PROVIDE(os_task_create = 0x0200979d);
+    PROVIDE(os_task_delete = 0x020097b1);
+    PROVIDE(os_task_handle_get = 0x020097b9);
+    PROVIDE(os_task_priority_get = 0x020097c1);
+    PROVIDE(os_task_priority_set = 0x020097c9);
+    PROVIDE(os_task_resume = 0x020097d1);
+    PROVIDE(os_task_signal_clear = 0x020097d9);
+    PROVIDE(os_task_signal_recv = 0x020097e1);
+    PROVIDE(os_task_signal_send = 0x020097e9);
+    PROVIDE(os_task_status_dump = 0x020097f1);
+    PROVIDE(os_task_suspend = 0x020097f9);
+    PROVIDE(os_task_yield = 0x02009801);
+    PROVIDE(os_timer_auto_reload_get = 0x02009809);
+    PROVIDE(os_timer_clock_get = 0x02009811);
+    PROVIDE(os_timer_create = 0x02009819);
+    PROVIDE(os_timer_delete = 0x0200982d);
+    PROVIDE(os_timer_dump = 0x02009835);
+    PROVIDE(os_timer_handle_get = 0x0200983d);
+    PROVIDE(os_timer_id_get = 0x02009845);
+    PROVIDE(os_timer_init = 0x0200984d);
+    PROVIDE(os_timer_pend_function_call = 0x0200986d);
+    PROVIDE(os_timer_restart = 0x02009875);
+    PROVIDE(os_timer_start = 0x0200987d);
+    PROVIDE(os_timer_state_get = 0x02009885);
+    PROVIDE(os_timer_stop = 0x0200988d);
+    PROVIDE(os_timer_tick_handler = 0x02009895);
+    PROVIDE(os_timer_tick_increase = 0x0200989d);
+    PROVIDE(os_timer_tick_rate_get = 0x020098a5);
+    PROVIDE(os_unlock = 0x020098ad);
+    PROVIDE(ota_bank_addr_get = 0x020098c5);
+    PROVIDE(ota_dual_bank_enable = 0x020098d9);
+    PROVIDE(phy_hw_control_init = 0x0200a90d);
+    PROVIDE(trace_double = 0x0200da29);
+    PROVIDE(trace_string = 0x0200da3b);
+    PROVIDE(trace_uint64 = 0x0200da51);
+    PROVIDE(GTC_GetCounter = 0x20000195);
+    PROVIDE(amu_init = 0x20001f64);
+    PROVIDE(amu_script_init = 0x20001f74);
+    PROVIDE(pck600_system_set_dynamic_power_policy = 0x20002164);
+    PROVIDE(phy_init = 0x200021f4);
+    PROVIDE(platform_pm_init = 0x200022b8);
+    PROVIDE(power_manager_init = 0x200023a4);
+    PROVIDE(thermal_meter_init = 0x200024e0);
+    PROVIDE(thermal_tracking_init = 0x200024ec);
+    PROVIDE(wakeup_init = 0x20002500);
+    PROVIDE(lowerstack_SystemCall_in_platform = 0x20002a10);
+    PROVIDE(os_interface = 0x20002a1c);
+    PROVIDE(os_pm_feature_cfg = 0x20002b3c);
+    PROVIDE(patch_os_timer_max_num_get = 0x20002cb0);
+}
diff --git a/bee/ld/rtl87x2j/bt_controller.ld b/bee/ld/rtl87x2j/bt_controller.ld
new file mode 100644
index 00000000..fff7bbe7
--- /dev/null
+++ b/bee/ld/rtl87x2j/bt_controller.ld
@@ -0,0 +1,7 @@
+SECTIONS
+{
+    PROVIDE(vhci_ack = 0x20004000);
+    PROVIDE(vhci_close = 0x20004008);
+    PROVIDE(vhci_open = 0x2000400c);
+    PROVIDE(vhci_send = 0x20004010);
+}
diff --git a/bee/ld/rtl87x2j/libdriver.a b/bee/ld/rtl87x2j/libdriver.a
new file mode 100644
index 00000000..85d9494e
Binary files /dev/null and b/bee/ld/rtl87x2j/libdriver.a differ
diff --git a/bee/logging/CMakeLists.txt b/bee/logging/CMakeLists.txt
new file mode 100644
index 00000000..55b24f13
--- /dev/null
+++ b/bee/logging/CMakeLists.txt
@@ -0,0 +1,6 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_include_directories_ifdef(CONFIG_SOC_SERIES_RTL87X2G inc/rtl87x2g)
+zephyr_include_directories_ifdef(CONFIG_SOC_SERIES_RTL87X2J inc/rtl87x2j)
+zephyr_include_directories_ifdef(CONFIG_SOC_SERIES_RTL8752H inc/rtl8752h)
diff --git a/bee/logging/inc/rtl8752h/log_uart_dma.h b/bee/logging/inc/rtl8752h/log_uart_dma.h
new file mode 100644
index 00000000..7675f2d4
--- /dev/null
+++ b/bee/logging/inc/rtl8752h/log_uart_dma.h
@@ -0,0 +1,79 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef LOG_UART_DMA_H
+#define LOG_UART_DMA_H
+
+#include "pingpong_buffer.h"
+#include "rtl876x.h"
+#include "trace.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum
+{
+    LOG_DMA_STATE_IDLE = 0,
+    LOG_DMA_STATE_PROCESS_MCU,
+    LOG_DMA_STATE_PENDING_MCU,
+    LOG_DMA_STATE_MAX
+} T_LOG_DMA_STATE;
+
+typedef enum
+{
+    LOG_DMA_SIGNAL_MCU_REQUEST = 0,
+    LOG_DMA_SIGNAL_MCU_DONE,
+    LOG_DMA_SIGNAL_MAX
+} T_LOG_DMA_SIGNAL;
+
+typedef struct
+{
+    uint16_t MCU_LogMissed;
+    uint16_t PendedMCU_BufferSize;
+    uint8_t *PendedMCU_Buffer;      /* MCU uses ping pong buffer */
+    volatile T_LOG_DMA_STATE State;
+    T_LOG_DMA_STATE LastState;
+} T_LOG_DMA_SM;
+
+typedef struct
+{
+    uint32_t ReadIndex;     /* DSP uses ring buffer */
+    uint32_t WriteIndex;
+    uint8_t *Buffer;
+    uint16_t BufferSize;    /* MCU uses ping pong buffer */
+    T_LOG_DMA_SIGNAL Signal;
+} T_LOG_DMA_EVT;
+
+#define LogDMA_StateTran(State_) (me->LastState = me->State, me->State = (State_))
+
+/* Config Log DMA Channel */
+#define LogDMAChannelNum      3
+#define LogDMAChannel         GDMA_Channel3
+#define LogDMAIRQn            GDMA0_Channel3_IRQn
+#define LogUartDMAIntrHandler GDMA0_Channel3_Handler
+
+extern PingpongBuffer *pMCU_PPB;
+extern T_LOG_DMA_SM   *pLogDMA_SM;
+
+void LogUartDMAInit(void);
+void LogUartDMAStart(uint8_t *p_outputbuf, uint16_t output_size);
+void LogUartDMAIntrHandler(void);
+void LogUartDMAIdleHook(void);
+bool log_pm_check(void);
+
+void LogDMA_SM_Dispatch(T_LOG_DMA_SM *me, T_LOG_DMA_EVT const *e);
+
+__STATIC_INLINE void NEVER_HAPPEN(uint32_t line_no, T_LOG_DMA_SM *me, T_LOG_DMA_EVT const *e)
+{
+    OS_PRINT_WARN3("Line %d: Log SM Error: state: %d, signal: %d", line_no, me->State, e->Signal);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LOG_UART_DMA_H */
diff --git a/bee/logging/inc/rtl8752h/pingpong_buffer.h b/bee/logging/inc/rtl8752h/pingpong_buffer.h
new file mode 100644
index 00000000..da94fd43
--- /dev/null
+++ b/bee/logging/inc/rtl8752h/pingpong_buffer.h
@@ -0,0 +1,76 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef PINGPONG_BUFFER_H
+#define PINGPONG_BUFFER_H
+
+#include <stdint.h>
+#include <string.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @brief LogMissedCounter records the number of log missed.
+    If the value is greater then 0, please reduce logs or speed up log uart/DMA.
+    */
+typedef struct
+{
+    uint8_t *pInputBuffer;
+    uint8_t *pOutputBuffer;
+    uint16_t InputBufferSize;
+    uint16_t OutputBufferSize;
+    uint32_t LogMissedCounter;
+    uint32_t MaxBufferSize;
+} PingpongBuffer;
+
+static inline uint32_t PPB_GetLogMissedCounter(PingpongBuffer *pPPB)
+{
+    return pPPB->LogMissedCounter;
+}
+
+static inline void PPB_ClearLogMissedCounter(PingpongBuffer *pPPB)
+{
+    pPPB->LogMissedCounter = 0;
+}
+
+static inline bool PPB_IsInit(PingpongBuffer *pPPB)
+{
+    return ((pPPB->pInputBuffer != NULL) && (pPPB->pOutputBuffer != NULL));
+}
+
+static inline bool PPB_IsOutputBufEmpty(PingpongBuffer *pPPB)
+{
+    return (pPPB->OutputBufferSize == 0);
+}
+
+static inline bool PPB_IsInputBufEmpty(PingpongBuffer *pPPB)
+{
+    return (pPPB->InputBufferSize == 0);
+}
+
+static inline uint16_t PPB_GetOutputBufSize(PingpongBuffer *pPPB)
+{
+    return pPPB->OutputBufferSize;
+}
+
+static inline uint16_t PPB_GetInputBufSize(PingpongBuffer *pPPB)
+{
+    return pPPB->InputBufferSize;
+}
+
+void PPB_Init(PingpongBuffer *pPPB);
+void PPB_Uninit(PingpongBuffer *pPPB);
+void PPB_Init_DLPS_Restore(PingpongBuffer *pPPB);
+void PPB_Write(PingpongBuffer *pPPB, const uint8_t *source, uint16_t size);
+void PPB_ClearOutputBuffer(PingpongBuffer *pPPB);
+void PPB_BufSwitch(PingpongBuffer *pPPB);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/bee/logging/inc/rtl8752h/trace.h b/bee/logging/inc/rtl8752h/trace.h
new file mode 100644
index 00000000..542bd4a4
--- /dev/null
+++ b/bee/logging/inc/rtl8752h/trace.h
@@ -0,0 +1,2249 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *               Define to prevent recursive inclusion
+ *============================================================================*/
+
+#ifndef _TRACE_H_
+#define _TRACE_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+/*============================================================================*
+ *                        Header Files
+ *============================================================================*/
+#include <stdint.h>
+#include <stdbool.h>
+
+/**
+ * \defgroup    TRACE       Trace
+ * \brief       Defines debug trace macros for each module.
+ * @{
+*/
+
+/*============================================================================*
+ *                         Types
+ *============================================================================*/
+/** @defgroup TRACE_Exported_Types Trace Exported Types
+  * @brief
+  * @{
+  */
+
+/* Log type definition */
+typedef enum
+{
+    TYPE_UPPERSTACK_RESET       = 0,
+    TYPE_UPPERSTACK_FORMAT      = 1,
+    TYPE_UPPERSTACK_MESSAGE     = 2,
+    TYPE_UPPERSTACK_BINARY      = 3,
+    TYPE_UPPERSTACK_STRING      = 4,
+    TYPE_UPPERSTACK_BDADDR1     = 5,
+    TYPE_UPPERSTACK_BDADDR2     = 6,
+    TYPE_UPPERSTACK_RAMDATA1    = 7,
+    TYPE_UPPERSTACK_RAMDATA2    = 8,
+    TYPE_UPPERSTACK_RAMDATA3    = 9,
+    TYPE_UPPERSTACK_RAMDATA4    = 10,
+    TYPE_UPPERSTACK_RAMDATA5    = 11,
+    TYPE_UPPERSTACK_RAMDATA6    = 12,
+    TYPE_UPPERSTACK_RAMDATA7    = 13,
+    TYPE_UPPERSTACK_RAMDATA8    = 14,
+
+    TYPE_PLATFORM_DBG_DIRECT    = 16,
+
+    TYPE_RTL8752H               = 37,
+    TYPE_RTL87X2G               = 38,
+} T_LOG_TYPE;
+
+
+/* Log subtype definition */
+typedef enum
+{
+    SUBTYPE_DIRECT                  = 0x00,
+
+    SUBTYPE_FORMAT                  = 0x10,
+    SUBTYPE_DOWN_MESSAGE            = 0x11,
+    SUBTYPE_UP_MESSAGE              = 0x12,
+
+    SUBTYPE_DOWN_SNOOP              = 0x20,
+    SUBTYPE_UP_SNOOP                = 0x28,
+
+    SUBTYPE_BDADDR                  = 0x30,
+
+    SUBTYPE_STRING                  = 0x40,
+
+    SUBTYPE_BINARY                  = 0x50,
+
+    SUBTYPE_INDEX                   = 0x60,
+    SUBTYPE_STACK_INDEX             = 0x61,
+
+    SUBTYPE_TEXT                    = 0x70,
+} T_LOG_SUBTYPE;
+
+/**
+ * trace.h
+ *
+ * \name    MODULE_ID
+ * \brief   Module ID definition.
+ * \anchor  MODULE_ID
+ */
+/**@{*/
+typedef enum
+{
+    /* platform modules */
+    MODULE_PATCH                    = 0,
+    MODULE_OS                       = 1,
+    MODULE_OSIF                     = 2,
+    MODULE_BOOT                     = 3,
+    MODULE_PM                       = 4,
+    MODULE_AES                      = 5,
+    MODULE_FS                       = 6,
+    MODULE_DEBUG                    = 7,
+    MODULE_PHY                      = 8,
+
+    /* device modules */
+    MODULE_KEYSCAN                  = 12,
+    MODULE_QDECODE                  = 13,
+    MODULE_IR                       = 14,
+    MODULE_3DG                      = 15,
+    MODULE_ADC                      = 16,
+    MODULE_GDMA                     = 17,
+    MODULE_I2C                      = 18,
+    MODULE_RTC                      = 19,
+    MODULE_SPI                      = 20,
+    MODULE_TIMER                    = 21,
+    MODULE_UART                     = 22,
+    MODULE_FLASH                    = 23,
+    MODULE_GPIO                     = 24,
+    MODULE_PINMUX                   = 25,
+    MODULE_PWM                      = 26,
+    MODULE_USB                      = 27,
+    MODULE_SDIO                     = 28,
+    MODULE_CHARGER                  = 29,
+    MODULE_DSP                      = 30,
+    MODULE_EFUSE                    = 31,
+    MODULE_CTC                      = 32,
+
+    /* stack modules */
+    MODULE_ZIGBEE                   = 47,
+    MODULE_APP                      = 48,
+    MODULE_DFU                      = 49,
+    MODULE_RFCOMM                   = 50,
+    MODULE_PROFILE                  = 51,
+    MODULE_PROTOCOL                 = 52,
+    MODULE_GAP                      = 53,
+    MODULE_BTE                      = 54,
+    MODULE_BTIF                     = 55,
+    MODULE_GATT                     = 56,
+    MODULE_SMP                      = 57,
+    MODULE_SDP                      = 58,
+    MODULE_L2CAP                    = 59,
+    MODULE_HCI                      = 60,
+    MODULE_SNOOP                    = 61,
+    MODULE_UPPERSTACK               = 62,
+    MODULE_LOWERSTACK               = 63,
+
+    MODULE_NUM                      = 64
+} T_MODULE_ID;
+/**@}*/
+
+/** End of TRACE_Exported_Types
+  * @}
+  */
+
+/*============================================================================*
+ *                         Macros
+ *============================================================================*/
+/** @defgroup TRACE_Exported_Macros Trace Exported Macros
+  * @brief
+  * @{
+  */
+
+/* Log Section Definition */
+#define TRACE_DATA __attribute__((section(".TRACE"))) __attribute__((aligned(4))) __attribute__((used))
+
+/**
+ * trace.h
+ *
+ * \name    TRACE_LEVEL
+ * \brief   Log Level Definition.
+ * \anchor  TRACE_LEVEL
+ */
+/**@{*/
+#define LEVEL_ERROR     0
+#define LEVEL_WARN      1
+#define LEVEL_INFO      2
+#define LEVEL_TRACE     3
+#define LEVEL_NUM       4
+/**@}*/
+
+/*
+ * DBG_LEVEL is used to control the log printed by DBG_BUFFER().
+ * -1          : Print None
+ * LEVEL_ERROR : Print ERROR
+ * LEVEL_WARN  : Print ERROR, WARN
+ * LEVEL_INFO  : Print ERROR, WARN, INFO
+ * LEVEL_TRACE : Print ERROR, WARN, INFO, TRACE
+ */
+#define DBG_LEVEL               LEVEL_TRACE
+
+
+
+/* Log type current ic used */
+#define LOG_TYPE                (TYPE_RTL8752H)
+
+/**
+ * trace.h
+ *
+ * \name    MODULE_BITMAP
+ * \brief   Module bitmap definition.
+ * \anchor  MODULE_BITMAP
+ */
+/**@{*/
+#define MODULE_BIT_PATCH            ((uint64_t)1 << MODULE_PATCH     )
+#define MODULE_BIT_OS               ((uint64_t)1 << MODULE_OS        )
+#define MODULE_BIT_OSIF             ((uint64_t)1 << MODULE_OSIF      )
+#define MODULE_BIT_BOOT             ((uint64_t)1 << MODULE_BOOT      )
+#define MODULE_BIT_PM               ((uint64_t)1 << MODULE_PM        )
+#define MODULE_BIT_AES              ((uint64_t)1 << MODULE_AES       )
+#define MODULE_BIT_FS               ((uint64_t)1 << MODULE_FS        )
+
+#define MODULE_BIT_KEYSCAN          ((uint64_t)1 << MODULE_KEYSCAN   )
+#define MODULE_BIT_QDECODE          ((uint64_t)1 << MODULE_QDECODE   )
+#define MODULE_BIT_IR               ((uint64_t)1 << MODULE_IR        )
+#define MODULE_BIT_3DG              ((uint64_t)1 << MODULE_3DG       )
+#define MODULE_BIT_ADC              ((uint64_t)1 << MODULE_ADC       )
+#define MODULE_BIT_GDMA             ((uint64_t)1 << MODULE_GDMA      )
+#define MODULE_BIT_I2C              ((uint64_t)1 << MODULE_I2C       )
+#define MODULE_BIT_RTC              ((uint64_t)1 << MODULE_RTC       )
+#define MODULE_BIT_SPI              ((uint64_t)1 << MODULE_SPI       )
+#define MODULE_BIT_TIMER            ((uint64_t)1 << MODULE_TIMER     )
+#define MODULE_BIT_UART             ((uint64_t)1 << MODULE_UART      )
+#define MODULE_BIT_FLASH            ((uint64_t)1 << MODULE_FLASH     )
+#define MODULE_BIT_GPIO             ((uint64_t)1 << MODULE_GPIO      )
+#define MODULE_BIT_PINMUX           ((uint64_t)1 << MODULE_PINMUX    )
+#define MODULE_BIT_PWM              ((uint64_t)1 << MODULE_PWM       )
+#define MODULE_BIT_USB              ((uint64_t)1 << MODULE_USB       )
+#define MODULE_BIT_SDIO             ((uint64_t)1 << MODULE_SDIO      )
+#define MODULE_BIT_CHARGER          ((uint64_t)1 << MODULE_CHARGER   )
+#define MODULE_BIT_DSP              ((uint64_t)1 << MODULE_DSP       )
+#define MODULE_BIT_EFUSE            ((uint64_t)1 << MODULE_EFUSE     )
+#define MODULE_BIT_CTC              ((uint64_t)1 << MODULE_CTC       )
+
+#define MODULE_BIT_ZIGBEE           ((uint64_t)1 << MODULE_ZIGBEE    )
+#define MODULE_BIT_APP              ((uint64_t)1 << MODULE_APP       )
+#define MODULE_BIT_DFU              ((uint64_t)1 << MODULE_DFU       )
+#define MODULE_BIT_RFCOMM           ((uint64_t)1 << MODULE_RFCOMM    )
+#define MODULE_BIT_PROFILE          ((uint64_t)1 << MODULE_PROFILE   )
+#define MODULE_BIT_PROTOCOL         ((uint64_t)1 << MODULE_PROTOCOL  )
+#define MODULE_BIT_GAP              ((uint64_t)1 << MODULE_GAP       )
+#define MODULE_BIT_BTIF             ((uint64_t)1 << MODULE_BTIF      )
+#define MODULE_BIT_GATT             ((uint64_t)1 << MODULE_GATT      )
+#define MODULE_BIT_SMP              ((uint64_t)1 << MODULE_SMP       )
+#define MODULE_BIT_SDP              ((uint64_t)1 << MODULE_SDP       )
+#define MODULE_BIT_L2CAP            ((uint64_t)1 << MODULE_L2CAP     )
+#define MODULE_BIT_HCI              ((uint64_t)1 << MODULE_HCI       )
+#define MODULE_BIT_SNOOP            ((uint64_t)1 << MODULE_SNOOP     )
+#define MODULE_BIT_LOWERSTACK       ((uint64_t)1 << MODULE_LOWERSTACK)
+#define MODULE_BIT_UPPERSTACK       ((uint64_t)1 << MODULE_UPPERSTACK)
+/**@}*/
+/** End of TRACE_Exported_Macros
+  * @}
+  */
+
+/*============================================================================*
+ *                              Internal functions & macros
+*============================================================================*/
+/**
+ * \cond        Private
+ * \brief       Internal functions and macros.
+ * \defgroup    TRACE_Internal_Functions trace internal functions.
+ * \{
+ */
+
+/* Internal function that is used by internal macro DBG_DIRECT. */
+#if (ENABLE_FULL_FEATURED_DIRECT_LOG == 1)
+extern void log_direct_app(uint32_t info, const char *fmt, ...);
+#define log_direct_retarget     log_direct_app
+#else
+void log_direct(uint32_t info, const char *fmt, ...);
+#define log_direct_retarget     log_direct
+#endif
+
+/* Internal function that is used by internal macro DBG_LOWERSTACK. */
+void LogBufferLowerStack(uint32_t control, uint16_t log_str_index, uint8_t param_num, ...);
+
+/* Internal function that is used by internal macro DBG_LOWERSTACKDATA. */
+void LogBufferLowerStackData(uint32_t control, uint16_t log_str_index, uint16_t length,
+                             uint8_t *p_str);
+
+/* Internal function that is used by internal macro DBG_BUFFER. */
+void log_buffer(uint32_t info, uint32_t log_str_index, uint8_t param_num, ...);
+
+void log_buffer_lowerstack(uint32_t str_index, uint32_t param_num, ...);
+
+/* Internal function that is used by internal macro DBG_INDEX. */
+#define log_index log_buffer
+
+/* Internal function that is used by internal macro DBG_SNOOP. */
+void log_snoop(uint32_t info, uint16_t length, uint8_t *p_snoop);
+
+/* Internal function that is used by public macro TRACE_BDADDR. */
+const char *trace_bdaddr(uint32_t info, char *bd_addr);
+
+/* Internal function that is used by public macro TRACE_STRING. */
+const char *trace_string(uint32_t info, char *p_data);
+
+/* Internal function that is used by public macro TRACE_BINARY. */
+const char *trace_binary(uint32_t info, uint16_t length, uint8_t *p_data);
+
+#define COMBINE_TRACE_INFO(type, subtype, module, level)  (uint32_t)(((type)<<24) | ((subtype)<<16) | ((module)<<8) | (level))
+
+/* Internal macro that is wrapped by internal macro DBG_BUFFER. */
+#define DBG_BUFFER_INTERNAL(type, sub_type, module, level, fmt, param_num, ...) do {\
+        static const char format[] TRACE_DATA = fmt;\
+        log_buffer(COMBINE_TRACE_INFO(type, sub_type, module, level), (uint32_t)format, param_num, ##__VA_ARGS__);\
+    } while (0)
+
+#if (DBG_LEVEL >= LEVEL_ERROR)
+#define DBG_BUFFER_LEVEL_ERROR(type, sub_type, module, fmt, param_num, ...) do {\
+        DBG_BUFFER_INTERNAL(type, sub_type, module, LEVEL_ERROR, fmt, param_num, ##__VA_ARGS__);\
+    } while (0)
+#define DBG_INDEX_LEVEL_ERROR(type, sub_type, module, fmt, param_num, ...) do {\
+        log_index(COMBINE_TRACE_INFO(type, sub_type, module, LEVEL_ERROR), fmt, param_num, ##__VA_ARGS__);\
+    } while (0)
+#else
+#define DBG_BUFFER_LEVEL_ERROR(type, sub_type, module, fmt, param_num, ...)
+#define DBG_INDEX_LEVEL_ERROR(type, sub_type, module, fmt, param_num, ...)
+#endif
+
+#if (DBG_LEVEL >= LEVEL_WARN)
+#define DBG_BUFFER_LEVEL_WARN(type, sub_type, module, fmt, param_num, ...)  do {\
+        DBG_BUFFER_INTERNAL(type, sub_type, module, LEVEL_WARN, fmt, param_num, ##__VA_ARGS__);\
+    } while (0)
+#define DBG_INDEX_LEVEL_WARN(type, sub_type, module, fmt, param_num, ...) do {\
+        log_index(COMBINE_TRACE_INFO(type, sub_type, module, LEVEL_WARN), fmt, param_num, ##__VA_ARGS__);\
+    } while (0)
+#else
+#define DBG_BUFFER_LEVEL_WARN(type, sub_type, module, fmt, param_num, ...)
+#define DBG_INDEX_LEVEL_WARN(type, sub_type, module, fmt, param_num, ...)
+#endif
+
+#if (DBG_LEVEL >= LEVEL_INFO)
+#define DBG_BUFFER_LEVEL_INFO(type, sub_type, module, fmt, param_num, ...)  do {\
+        DBG_BUFFER_INTERNAL(type, sub_type, module, LEVEL_INFO, fmt, param_num, ##__VA_ARGS__);\
+    } while (0)
+#define DBG_INDEX_LEVEL_INFO(type, sub_type, module, fmt, param_num, ...) do {\
+        log_index(COMBINE_TRACE_INFO(type, sub_type, module, LEVEL_INFO), fmt, param_num, ##__VA_ARGS__);\
+    } while (0)
+#else
+#define DBG_BUFFER_LEVEL_INFO(type, sub_type, module, fmt, param_num, ...)
+#define DBG_INDEX_LEVEL_INFO(type, sub_type, module, fmt, param_num, ...)
+#endif
+
+#if (DBG_LEVEL >= LEVEL_TRACE)
+#define DBG_BUFFER_LEVEL_TRACE(type, sub_type, module, fmt, param_num, ...) do {\
+        DBG_BUFFER_INTERNAL(type, sub_type, module, LEVEL_TRACE, fmt, param_num, ##__VA_ARGS__);\
+    } while (0)
+#define DBG_INDEX_LEVEL_TRACE(type, sub_type, module, fmt, param_num, ...) do {\
+        log_index(COMBINE_TRACE_INFO(type, sub_type, module, LEVEL_TRACE), fmt, param_num, ##__VA_ARGS__);\
+    } while (0)
+#else
+#define DBG_BUFFER_LEVEL_TRACE(type, sub_type, module, fmt, param_num, ...)
+#define DBG_INDEX_LEVEL_TRACE(type, sub_type, module, fmt, param_num, ...)
+#endif
+
+#define DBG_BUFFER(type, sub_type, module, level, fmt, param_num,...)   \
+    DBG_BUFFER_##level(type, sub_type, module, fmt, param_num, ##__VA_ARGS__)
+
+#define DBG_INDEX(type, sub_type, module, level, fmt, param_num,...)   \
+    DBG_INDEX_##level(type, sub_type, module, fmt, param_num, ##__VA_ARGS__)
+
+#define DBG_DIRECT(...)     do {\
+        log_direct_retarget(COMBINE_TRACE_INFO(LOG_TYPE, SUBTYPE_DIRECT, 0, 0), __VA_ARGS__);\
+    } while (0)
+
+#if (LOG_TYPE == TYPE_RTL87X2G)
+#define DBG_LOWERSTACK(color, file_num, line_num, str_index, param_num, ...)     do {\
+        log_buffer_lowerstack(str_index, param_num, ##__VA_ARGS__);\
+    } while (0)
+#else
+#define DBG_LOWERSTACK(color, file_num, line_num, str_index, param_num, ...)     do {\
+        log_buffer(((file_num)<<16)|(line_num), (((MODULE_LOWERSTACK)<<16)|(str_index)), param_num, ##__VA_ARGS__);\
+    } while (0)
+#endif
+
+#define DBG_LOWERSTACKDATA(color, file_num, line_num, log_str_index, length, str)     do {\
+        LogBufferLowerStackData(((color)<<24)|((file_num)<<16)|(line_num), (uint16_t)(log_str_index), length, str);\
+    } while (0)
+
+#define DBG_SNOOP(type, sub_type, module, level, length, snoop)    do {\
+        log_snoop(COMBINE_TRACE_INFO(type, sub_type, module, level), length, snoop);\
+    } while (0)
+/**
+ * \}
+ * \endcond
+ */   /* End of group TRACE_Internal_Functions */
+
+/*============================================================================*
+ *                         Variables
+ *============================================================================*/
+/** @defgroup TRACE_Exported_Variables Trace Exported Variables
+  * @brief
+  * @{
+  */
+
+extern bool is_log_init;
+
+/** End of TRACE_Exported_Variables
+  * @}
+  */
+
+/*============================================================================*
+ *                         Functions
+ *============================================================================*/
+/** @defgroup TRACE_Exported_Functions Trace Exported Functions
+  * @brief
+  * @{
+  */
+
+/**
+ * trace.h
+ *
+ * \brief    Initialize module trace mask.
+ *
+ * \param[in]   mask    Module trace mask array. Set NULL to load default mask array.
+ *
+ * \return      None.
+ */
+void log_module_trace_init(uint64_t mask[LEVEL_NUM]);
+
+/**
+ * trace.h
+ *
+ * \brief    Enable/Disable the module ID's trace.
+ *
+ * \param[in]   module_id   The specific module ID defined in \ref MODULE_ID.
+ *
+ * \param[in]   trace_level The trace level of the module ID defined in \ref TRACE_LEVEL.
+ *
+ * \param[in]   set         Enable or disable the module ID's trace.
+ * \arg \c true     Enable the module ID's trace.
+ * \arg \c false    Disable the module ID's trace.
+ *
+ * \return           The status of setting module ID's trace.
+ * \retval true      Module ID's trace was set successfully.
+ * \retval false     Module ID's trace was failed to set.
+ */
+bool log_module_trace_set(T_MODULE_ID module_id, uint8_t trace_level, bool set);
+
+/**
+ * trace.h
+ *
+ * \brief    Enable/Disable module bitmap's trace.
+ *
+ * \param[in]   module_bitmap   The module bitmap defined in \ref MODULE_BITMAP.
+ *
+ * \param[in]   trace_level     The trace level of the module bitmap defined in \ref TRACE_LEVEL.
+ *
+ * \param[in]   set             Enable or disable the module bitmap's trace.
+ * \arg \c true     Enable the module bitmap's trace.
+ * \arg \c false    Disable the module bitmap's trace.
+ *
+ * \return           The status of setting module bitmap's trace.
+ * \retval true      Module bitmap's trace was set successfully.
+ * \retval false     Module bitmap's trace was failed to set.
+ */
+bool log_module_bitmap_trace_set(uint64_t module_bitmap, uint8_t trace_level, bool set);
+
+/** End of TRACE_Exported_Functions
+  * @}
+  */
+
+/*============================================================================*
+ *                         Macros
+ *============================================================================*/
+/** @defgroup TRACE_Exported_Macros Trace Exported Macros
+  * @brief
+  * @{
+  */
+/**
+ * trace.h
+ *
+ * \name    AUXILIARY_PRINT_BDADDR
+ * \brief   Auxiliary Interface that is used to print BD address.
+ * \anchor  AUXILIARY_PRINT_BDADDR
+ */
+#define TRACE_BDADDR(bd_addr)   \
+    trace_bdaddr(COMBINE_TRACE_INFO(LOG_TYPE, SUBTYPE_BDADDR, 0, 0), (char *)(bd_addr))
+
+/**
+ * trace.h
+ *
+ * \name    AUXILIARY_PRINT_STRING
+ * \brief   Auxiliary Interface that is used to print string.
+ * \anchor  AUXILIARY_PRINT_STRING
+ */
+#define TRACE_STRING(data)    \
+    trace_string(COMBINE_TRACE_INFO(LOG_TYPE, SUBTYPE_STRING, 0, 0), (char *)(data))
+
+/**
+ * trace.h
+ *
+ * \name    AUXILIARY_PRINT_BINARY
+ * \brief   Auxiliary Interface that is used to print binary string.
+ * \anchor  AUXILIARY_PRINT_BINARY
+ */
+/**@{*/
+#define TRACE_BINARY(length, data)  \
+    trace_binary(COMBINE_TRACE_INFO(LOG_TYPE, SUBTYPE_BINARY, 0, 0), length, (uint8_t *)(data))
+/**@}*/
+
+
+/* Bluetooth HCI Snoop Trace Interfaces */
+#define BT_SNOOP_DOWN_TRACE(length, snoop)  \
+    DBG_SNOOP(LOG_TYPE, SUBTYPE_DOWN_SNOOP, MODULE_SNOOP, LEVEL_ERROR, length, snoop);
+#define BT_SNOOP_UP_TRACE(length, snoop)  \
+    DBG_SNOOP(LOG_TYPE, SUBTYPE_UP_SNOOP, MODULE_SNOOP, LEVEL_ERROR, length, snoop);
+
+
+/* Bluetooth Message Trace Interfaces */
+#define BT_MESSAGE_DOWN_PRINT_ERROR(length, message)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_DOWN_MESSAGE, MODULE_UPPERSTACK, LEVEL_ERROR, "", 2, length, message)
+#define BT_MESSAGE_DOWN_PRINT_WARN(length, message)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_DOWN_MESSAGE, MODULE_UPPERSTACK, LEVEL_WARN, "", 2, length, message)
+#define BT_MESSAGE_DOWN_PRINT_INFO(length, message)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_DOWN_MESSAGE, MODULE_UPPERSTACK, LEVEL_INFO, "", 2, length, message)
+#define BT_MESSAGE_DOWN_PRINT_TRACE(length, message)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_DOWN_MESSAGE, MODULE_UPPERSTACK, LEVEL_TRACE, "", 2, length, message)
+#define BT_MESSAGE_UP_PRINT_ERROR(length, message)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_UP_MESSAGE, MODULE_UPPERSTACK, LEVEL_ERROR, "", 2, length, message)
+#define BT_MESSAGE_UP_PRINT_WARN(length, message)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_UP_MESSAGE, MODULE_UPPERSTACK, LEVEL_WARN, "", 2, length, message)
+#define BT_MESSAGE_UP_PRINT_INFO(length, message)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_UP_MESSAGE, MODULE_UPPERSTACK, LEVEL_INFO, "", 2, length, message)
+#define BT_MESSAGE_UP_PRINT_TRACE(length, message)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_UP_MESSAGE, MODULE_UPPERSTACK, LEVEL_TRACE, "", 2, length, message)
+
+
+/* Patch Trace Interfaces */
+#define PATCH_PRINT_ERROR0(fmt)   \
+    DBG_INDEX(LOG_TYPE, SUBTYPE_INDEX, MODULE_PATCH, LEVEL_ERROR, fmt, 0)
+#define PATCH_PRINT_ERROR1(fmt, arg0)   \
+    DBG_INDEX(LOG_TYPE, SUBTYPE_INDEX, MODULE_PATCH, LEVEL_ERROR, fmt, 1, arg0)
+#define PATCH_PRINT_ERROR2(fmt, arg0, arg1)   \
+    DBG_INDEX(LOG_TYPE, SUBTYPE_INDEX, MODULE_PATCH, LEVEL_ERROR, fmt, 2, arg0, arg1)
+#define PATCH_PRINT_ERROR3(fmt, arg0, arg1, arg2)   \
+    DBG_INDEX(LOG_TYPE, SUBTYPE_INDEX, MODULE_PATCH, LEVEL_ERROR, fmt, 3, arg0, arg1, arg2)
+#define PATCH_PRINT_ERROR4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_INDEX(LOG_TYPE, SUBTYPE_INDEX, MODULE_PATCH, LEVEL_ERROR, fmt, 4, arg0, arg1, arg2, arg3)
+#define PATCH_PRINT_ERROR5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_INDEX(LOG_TYPE, SUBTYPE_INDEX, MODULE_PATCH, LEVEL_ERROR, fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define PATCH_PRINT_ERROR6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_INDEX(LOG_TYPE, SUBTYPE_INDEX, MODULE_PATCH, LEVEL_ERROR, fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define PATCH_PRINT_ERROR7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_INDEX(LOG_TYPE, SUBTYPE_INDEX, MODULE_PATCH, LEVEL_ERROR, fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define PATCH_PRINT_ERROR8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_INDEX(LOG_TYPE, SUBTYPE_INDEX, MODULE_PATCH, LEVEL_ERROR, fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define PATCH_PRINT_WARN0(fmt)   \
+    DBG_INDEX(LOG_TYPE, SUBTYPE_INDEX, MODULE_PATCH, LEVEL_WARN, fmt, 0)
+#define PATCH_PRINT_WARN1(fmt, arg0)   \
+    DBG_INDEX(LOG_TYPE, SUBTYPE_INDEX, MODULE_PATCH, LEVEL_WARN, fmt, 1, arg0)
+#define PATCH_PRINT_WARN2(fmt, arg0, arg1)   \
+    DBG_INDEX(LOG_TYPE, SUBTYPE_INDEX, MODULE_PATCH, LEVEL_WARN, fmt, 2, arg0, arg1)
+#define PATCH_PRINT_WARN3(fmt, arg0, arg1, arg2)   \
+    DBG_INDEX(LOG_TYPE, SUBTYPE_INDEX, MODULE_PATCH, LEVEL_WARN, fmt, 3, arg0, arg1, arg2)
+#define PATCH_PRINT_WARN4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_INDEX(LOG_TYPE, SUBTYPE_INDEX, MODULE_PATCH, LEVEL_WARN, fmt, 4, arg0, arg1, arg2, arg3)
+#define PATCH_PRINT_WARN5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_INDEX(LOG_TYPE, SUBTYPE_INDEX, MODULE_PATCH, LEVEL_WARN, fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define PATCH_PRINT_WARN6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_INDEX(LOG_TYPE, SUBTYPE_INDEX, MODULE_PATCH, LEVEL_WARN, fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define PATCH_PRINT_WARN7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_INDEX(LOG_TYPE, SUBTYPE_INDEX, MODULE_PATCH, LEVEL_WARN, fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define PATCH_PRINT_WARN8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_INDEX(LOG_TYPE, SUBTYPE_INDEX, MODULE_PATCH, LEVEL_WARN, fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define PATCH_PRINT_INFO0(fmt)   \
+    DBG_INDEX(LOG_TYPE, SUBTYPE_INDEX, MODULE_PATCH, LEVEL_INFO, fmt, 0)
+#define PATCH_PRINT_INFO1(fmt, arg0)   \
+    DBG_INDEX(LOG_TYPE, SUBTYPE_INDEX, MODULE_PATCH, LEVEL_INFO, fmt, 1, arg0)
+#define PATCH_PRINT_INFO2(fmt, arg0, arg1)   \
+    DBG_INDEX(LOG_TYPE, SUBTYPE_INDEX, MODULE_PATCH, LEVEL_INFO, fmt, 2, arg0, arg1)
+#define PATCH_PRINT_INFO3(fmt, arg0, arg1, arg2)   \
+    DBG_INDEX(LOG_TYPE, SUBTYPE_INDEX, MODULE_PATCH, LEVEL_INFO, fmt, 3, arg0, arg1, arg2)
+#define PATCH_PRINT_INFO4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_INDEX(LOG_TYPE, SUBTYPE_INDEX, MODULE_PATCH, LEVEL_INFO, fmt, 4, arg0, arg1, arg2, arg3)
+#define PATCH_PRINT_INFO5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_INDEX(LOG_TYPE, SUBTYPE_INDEX, MODULE_PATCH, LEVEL_INFO, fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define PATCH_PRINT_INFO6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_INDEX(LOG_TYPE, SUBTYPE_INDEX, MODULE_PATCH, LEVEL_INFO, fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define PATCH_PRINT_INFO7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_INDEX(LOG_TYPE, SUBTYPE_INDEX, MODULE_PATCH, LEVEL_INFO, fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define PATCH_PRINT_INFO8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_INDEX(LOG_TYPE, SUBTYPE_INDEX, MODULE_PATCH, LEVEL_INFO, fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define PATCH_PRINT_TRACE0(fmt)   \
+    DBG_INDEX(LOG_TYPE, SUBTYPE_INDEX, MODULE_PATCH, LEVEL_TRACE, fmt, 0)
+#define PATCH_PRINT_TRACE1(fmt, arg0)   \
+    DBG_INDEX(LOG_TYPE, SUBTYPE_INDEX, MODULE_PATCH, LEVEL_TRACE, fmt, 1, arg0)
+#define PATCH_PRINT_TRACE2(fmt, arg0, arg1)   \
+    DBG_INDEX(LOG_TYPE, SUBTYPE_INDEX, MODULE_PATCH, LEVEL_TRACE, fmt, 2, arg0, arg1)
+#define PATCH_PRINT_TRACE3(fmt, arg0, arg1, arg2)   \
+    DBG_INDEX(LOG_TYPE, SUBTYPE_INDEX, MODULE_PATCH, LEVEL_TRACE, fmt, 3, arg0, arg1, arg2)
+#define PATCH_PRINT_TRACE4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_INDEX(LOG_TYPE, SUBTYPE_INDEX, MODULE_PATCH, LEVEL_TRACE, fmt, 4, arg0, arg1, arg2, arg3)
+#define PATCH_PRINT_TRACE5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_INDEX(LOG_TYPE, SUBTYPE_INDEX, MODULE_PATCH, LEVEL_TRACE, fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define PATCH_PRINT_TRACE6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_INDEX(LOG_TYPE, SUBTYPE_INDEX, MODULE_PATCH, LEVEL_TRACE, fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define PATCH_PRINT_TRACE7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_INDEX(LOG_TYPE, SUBTYPE_INDEX, MODULE_PATCH, LEVEL_TRACE, fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define PATCH_PRINT_TRACE8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_INDEX(LOG_TYPE, SUBTYPE_INDEX, MODULE_PATCH, LEVEL_TRACE, fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+
+
+/* Bluetooth Lower Stack Trace Interfaces */
+#define LOWERSTACK_PRINT_ERROR0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_LOWERSTACK, LEVEL_ERROR, "!!!"fmt, 0)
+#define LOWERSTACK_PRINT_ERROR1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_LOWERSTACK, LEVEL_ERROR, "!!!"fmt, 1, arg0)
+#define LOWERSTACK_PRINT_ERROR2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_LOWERSTACK, LEVEL_ERROR, "!!!"fmt, 2, arg0, arg1)
+#define LOWERSTACK_PRINT_ERROR3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_LOWERSTACK, LEVEL_ERROR, "!!!"fmt, 3, arg0, arg1, arg2)
+#define LOWERSTACK_PRINT_ERROR4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_LOWERSTACK, LEVEL_ERROR, "!!!"fmt, 4, arg0, arg1, arg2, arg3)
+#define LOWERSTACK_PRINT_ERROR5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_LOWERSTACK, LEVEL_ERROR, "!!!"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define LOWERSTACK_PRINT_ERROR6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_LOWERSTACK, LEVEL_ERROR, "!!!"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define LOWERSTACK_PRINT_ERROR7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_LOWERSTACK, LEVEL_ERROR, "!!!"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define LOWERSTACK_PRINT_ERROR8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_LOWERSTACK, LEVEL_ERROR, "!!!"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define LOWERSTACK_PRINT_WARN0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_LOWERSTACK, LEVEL_WARN, "!!*"fmt, 0)
+#define LOWERSTACK_PRINT_WARN1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_LOWERSTACK, LEVEL_WARN, "!!*"fmt, 1, arg0)
+#define LOWERSTACK_PRINT_WARN2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_LOWERSTACK, LEVEL_WARN, "!!*"fmt, 2, arg0, arg1)
+#define LOWERSTACK_PRINT_WARN3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_LOWERSTACK, LEVEL_WARN, "!!*"fmt, 3, arg0, arg1, arg2)
+#define LOWERSTACK_PRINT_WARN4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_LOWERSTACK, LEVEL_WARN, "!!*"fmt, 4, arg0, arg1, arg2, arg3)
+#define LOWERSTACK_PRINT_WARN5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_LOWERSTACK, LEVEL_WARN, "!!*"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define LOWERSTACK_PRINT_WARN6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_LOWERSTACK, LEVEL_WARN, "!!*"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define LOWERSTACK_PRINT_WARN7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_LOWERSTACK, LEVEL_WARN, "!!*"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define LOWERSTACK_PRINT_WARN8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_LOWERSTACK, LEVEL_WARN, "!!*"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define LOWERSTACK_PRINT_INFO0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_LOWERSTACK, LEVEL_INFO, "!**"fmt, 0)
+#define LOWERSTACK_PRINT_INFO1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_LOWERSTACK, LEVEL_INFO, "!**"fmt, 1, arg0)
+#define LOWERSTACK_PRINT_INFO2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_LOWERSTACK, LEVEL_INFO, "!**"fmt, 2, arg0, arg1)
+#define LOWERSTACK_PRINT_INFO3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_LOWERSTACK, LEVEL_INFO, "!**"fmt, 3, arg0, arg1, arg2)
+#define LOWERSTACK_PRINT_INFO4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_LOWERSTACK, LEVEL_INFO, "!**"fmt, 4, arg0, arg1, arg2, arg3)
+#define LOWERSTACK_PRINT_INFO5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_LOWERSTACK, LEVEL_INFO, "!**"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define LOWERSTACK_PRINT_INFO6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_LOWERSTACK, LEVEL_INFO, "!**"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define LOWERSTACK_PRINT_INFO7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_LOWERSTACK, LEVEL_INFO, "!**"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define LOWERSTACK_PRINT_INFO8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_LOWERSTACK, LEVEL_INFO, "!**"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define LOWERSTACK_PRINT_TRACE0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_LOWERSTACK, LEVEL_TRACE, fmt, 0)
+#define LOWERSTACK_PRINT_TRACE1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_LOWERSTACK, LEVEL_TRACE, fmt, 1, arg0)
+#define LOWERSTACK_PRINT_TRACE2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_LOWERSTACK, LEVEL_TRACE, fmt, 2, arg0, arg1)
+#define LOWERSTACK_PRINT_TRACE3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_LOWERSTACK, LEVEL_TRACE, fmt, 3, arg0, arg1, arg2)
+#define LOWERSTACK_PRINT_TRACE4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_LOWERSTACK, LEVEL_TRACE, fmt, 4, arg0, arg1, arg2, arg3)
+#define LOWERSTACK_PRINT_TRACE5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_LOWERSTACK, LEVEL_TRACE, fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define LOWERSTACK_PRINT_TRACE6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_LOWERSTACK, LEVEL_TRACE, fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define LOWERSTACK_PRINT_TRACE7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_LOWERSTACK, LEVEL_TRACE, fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define LOWERSTACK_PRINT_TRACE8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_LOWERSTACK, LEVEL_TRACE, fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+
+
+/* OS Trace Interfaces */
+#define OS_PRINT_ERROR0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OS, LEVEL_ERROR, "!!!"fmt, 0)
+#define OS_PRINT_ERROR1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OS, LEVEL_ERROR, "!!!"fmt, 1, arg0)
+#define OS_PRINT_ERROR2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OS, LEVEL_ERROR, "!!!"fmt, 2, arg0, arg1)
+#define OS_PRINT_ERROR3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OS, LEVEL_ERROR, "!!!"fmt, 3, arg0, arg1, arg2)
+#define OS_PRINT_ERROR4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OS, LEVEL_ERROR, "!!!"fmt, 4, arg0, arg1, arg2, arg3)
+#define OS_PRINT_ERROR5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OS, LEVEL_ERROR, "!!!"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define OS_PRINT_ERROR6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OS, LEVEL_ERROR, "!!!"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define OS_PRINT_ERROR7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OS, LEVEL_ERROR, "!!!"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define OS_PRINT_ERROR8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OS, LEVEL_ERROR, "!!!"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define OS_PRINT_WARN0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OS, LEVEL_WARN, "!!*"fmt, 0)
+#define OS_PRINT_WARN1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OS, LEVEL_WARN, "!!*"fmt, 1, arg0)
+#define OS_PRINT_WARN2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OS, LEVEL_WARN, "!!*"fmt, 2, arg0, arg1)
+#define OS_PRINT_WARN3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OS, LEVEL_WARN, "!!*"fmt, 3, arg0, arg1, arg2)
+#define OS_PRINT_WARN4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OS, LEVEL_WARN, "!!*"fmt, 4, arg0, arg1, arg2, arg3)
+#define OS_PRINT_WARN5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OS, LEVEL_WARN, "!!*"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define OS_PRINT_WARN6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OS, LEVEL_WARN, "!!*"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define OS_PRINT_WARN7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OS, LEVEL_WARN, "!!*"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define OS_PRINT_WARN8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OS, LEVEL_WARN, "!!*"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define OS_PRINT_INFO0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OS, LEVEL_INFO, "!**"fmt, 0)
+#define OS_PRINT_INFO1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OS, LEVEL_INFO, "!**"fmt, 1, arg0)
+#define OS_PRINT_INFO2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OS, LEVEL_INFO, "!**"fmt, 2, arg0, arg1)
+#define OS_PRINT_INFO3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OS, LEVEL_INFO, "!**"fmt, 3, arg0, arg1, arg2)
+#define OS_PRINT_INFO4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OS, LEVEL_INFO, "!**"fmt, 4, arg0, arg1, arg2, arg3)
+#define OS_PRINT_INFO5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OS, LEVEL_INFO, "!**"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define OS_PRINT_INFO6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OS, LEVEL_INFO, "!**"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define OS_PRINT_INFO7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OS, LEVEL_INFO, "!**"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define OS_PRINT_INFO8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OS, LEVEL_INFO, "!**"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define OS_PRINT_TRACE0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OS, LEVEL_TRACE, fmt, 0)
+#define OS_PRINT_TRACE1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OS, LEVEL_TRACE, fmt, 1, arg0)
+#define OS_PRINT_TRACE2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OS, LEVEL_TRACE, fmt, 2, arg0, arg1)
+#define OS_PRINT_TRACE3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OS, LEVEL_TRACE, fmt, 3, arg0, arg1, arg2)
+#define OS_PRINT_TRACE4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OS, LEVEL_TRACE, fmt, 4, arg0, arg1, arg2, arg3)
+#define OS_PRINT_TRACE5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OS, LEVEL_TRACE, fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define OS_PRINT_TRACE6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OS, LEVEL_TRACE, fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define OS_PRINT_TRACE7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OS, LEVEL_TRACE, fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define OS_PRINT_TRACE8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OS, LEVEL_TRACE, fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+
+
+/* OSIF Trace Interfaces */
+#define OSIF_PRINT_ERROR0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OSIF, LEVEL_ERROR, "!!!"fmt, 0)
+#define OSIF_PRINT_ERROR1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OSIF, LEVEL_ERROR, "!!!"fmt, 1, arg0)
+#define OSIF_PRINT_ERROR2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OSIF, LEVEL_ERROR, "!!!"fmt, 2, arg0, arg1)
+#define OSIF_PRINT_ERROR3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OSIF, LEVEL_ERROR, "!!!"fmt, 3, arg0, arg1, arg2)
+#define OSIF_PRINT_ERROR4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OSIF, LEVEL_ERROR, "!!!"fmt, 4, arg0, arg1, arg2, arg3)
+#define OSIF_PRINT_ERROR5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OSIF, LEVEL_ERROR, "!!!"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define OSIF_PRINT_ERROR6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OSIF, LEVEL_ERROR, "!!!"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define OSIF_PRINT_ERROR7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OSIF, LEVEL_ERROR, "!!!"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define OSIF_PRINT_ERROR8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OSIF, LEVEL_ERROR, "!!!"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define OSIF_PRINT_WARN0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OSIF, LEVEL_WARN, "!!*"fmt, 0)
+#define OSIF_PRINT_WARN1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OSIF, LEVEL_WARN, "!!*"fmt, 1, arg0)
+#define OSIF_PRINT_WARN2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OSIF, LEVEL_WARN, "!!*"fmt, 2, arg0, arg1)
+#define OSIF_PRINT_WARN3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OSIF, LEVEL_WARN, "!!*"fmt, 3, arg0, arg1, arg2)
+#define OSIF_PRINT_WARN4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OSIF, LEVEL_WARN, "!!*"fmt, 4, arg0, arg1, arg2, arg3)
+#define OSIF_PRINT_WARN5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OSIF, LEVEL_WARN, "!!*"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define OSIF_PRINT_WARN6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OSIF, LEVEL_WARN, "!!*"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define OSIF_PRINT_WARN7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OSIF, LEVEL_WARN, "!!*"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define OSIF_PRINT_WARN8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OSIF, LEVEL_WARN, "!!*"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define OSIF_PRINT_INFO0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OSIF, LEVEL_INFO, "!**"fmt, 0)
+#define OSIF_PRINT_INFO1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OSIF, LEVEL_INFO, "!**"fmt, 1, arg0)
+#define OSIF_PRINT_INFO2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OSIF, LEVEL_INFO, "!**"fmt, 2, arg0, arg1)
+#define OSIF_PRINT_INFO3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OSIF, LEVEL_INFO, "!**"fmt, 3, arg0, arg1, arg2)
+#define OSIF_PRINT_INFO4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OSIF, LEVEL_INFO, "!**"fmt, 4, arg0, arg1, arg2, arg3)
+#define OSIF_PRINT_INFO5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OSIF, LEVEL_INFO, "!**"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define OSIF_PRINT_INFO6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OSIF, LEVEL_INFO, "!**"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define OSIF_PRINT_INFO7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OSIF, LEVEL_INFO, "!**"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define OSIF_PRINT_INFO8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OSIF, LEVEL_INFO, "!**"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define OSIF_PRINT_TRACE0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OSIF, LEVEL_TRACE, fmt, 0)
+#define OSIF_PRINT_TRACE1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OSIF, LEVEL_TRACE, fmt, 1, arg0)
+#define OSIF_PRINT_TRACE2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OSIF, LEVEL_TRACE, fmt, 2, arg0, arg1)
+#define OSIF_PRINT_TRACE3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OSIF, LEVEL_TRACE, fmt, 3, arg0, arg1, arg2)
+#define OSIF_PRINT_TRACE4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OSIF, LEVEL_TRACE, fmt, 4, arg0, arg1, arg2, arg3)
+#define OSIF_PRINT_TRACE5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OSIF, LEVEL_TRACE, fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define OSIF_PRINT_TRACE6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OSIF, LEVEL_TRACE, fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define OSIF_PRINT_TRACE7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OSIF, LEVEL_TRACE, fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define OSIF_PRINT_TRACE8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OSIF, LEVEL_TRACE, fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+
+/* CTC Trace Interfaces */
+#define CTC_PRINT_ERROR0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CTC, LEVEL_ERROR, "!!!"fmt, 0)
+#define CTC_PRINT_ERROR1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CTC, LEVEL_ERROR, "!!!"fmt, 1, arg0)
+#define CTC_PRINT_ERROR2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CTC, LEVEL_ERROR, "!!!"fmt, 2, arg0, arg1)
+#define CTC_PRINT_ERROR3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CTC, LEVEL_ERROR, "!!!"fmt, 3, arg0, arg1, arg2)
+#define CTC_PRINT_ERROR4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CTC, LEVEL_ERROR, "!!!"fmt, 4, arg0, arg1, arg2, arg3)
+#define CTC_PRINT_ERROR5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CTC, LEVEL_ERROR, "!!!"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define CTC_PRINT_ERROR6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CTC, LEVEL_ERROR, "!!!"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define CTC_PRINT_ERROR7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CTC, LEVEL_ERROR, "!!!"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define CTC_PRINT_ERROR8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CTC, LEVEL_ERROR, "!!!"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define CTC_PRINT_WARN0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CTC, LEVEL_WARN, "!!*"fmt, 0)
+#define CTC_PRINT_WARN1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CTC, LEVEL_WARN, "!!*"fmt, 1, arg0)
+#define CTC_PRINT_WARN2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CTC, LEVEL_WARN, "!!*"fmt, 2, arg0, arg1)
+#define CTC_PRINT_WARN3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CTC, LEVEL_WARN, "!!*"fmt, 3, arg0, arg1, arg2)
+#define CTC_PRINT_WARN4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CTC, LEVEL_WARN, "!!*"fmt, 4, arg0, arg1, arg2, arg3)
+#define CTC_PRINT_WARN5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CTC, LEVEL_WARN, "!!*"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define CTC_PRINT_WARN6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CTC, LEVEL_WARN, "!!*"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define CTC_PRINT_WARN7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CTC, LEVEL_WARN, "!!*"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define CTC_PRINT_WARN8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CTC, LEVEL_WARN, "!!*"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define CTC_PRINT_INFO0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CTC, LEVEL_INFO, "!**"fmt, 0)
+#define CTC_PRINT_INFO1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CTC, LEVEL_INFO, "!**"fmt, 1, arg0)
+#define CTC_PRINT_INFO2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CTC, LEVEL_INFO, "!**"fmt, 2, arg0, arg1)
+#define CTC_PRINT_INFO3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CTC, LEVEL_INFO, "!**"fmt, 3, arg0, arg1, arg2)
+#define CTC_PRINT_INFO4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CTC, LEVEL_INFO, "!**"fmt, 4, arg0, arg1, arg2, arg3)
+#define CTC_PRINT_INFO5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CTC, LEVEL_INFO, "!**"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define CTC_PRINT_INFO6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CTC, LEVEL_INFO, "!**"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define CTC_PRINT_INFO7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CTC, LEVEL_INFO, "!**"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define CTC_PRINT_INFO8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CTC, LEVEL_INFO, "!**"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define CTC_PRINT_TRACE0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CTC, LEVEL_TRACE, fmt, 0)
+#define CTC_PRINT_TRACE1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CTC, LEVEL_TRACE, fmt, 1, arg0)
+#define CTC_PRINT_TRACE2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CTC, LEVEL_TRACE, fmt, 2, arg0, arg1)
+#define CTC_PRINT_TRACE3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CTC, LEVEL_TRACE, fmt, 3, arg0, arg1, arg2)
+#define CTC_PRINT_TRACE4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CTC, LEVEL_TRACE, fmt, 4, arg0, arg1, arg2, arg3)
+#define CTC_PRINT_TRACE5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CTC, LEVEL_TRACE, fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define CTC_PRINT_TRACE6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CTC, LEVEL_TRACE, fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define CTC_PRINT_TRACE7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CTC, LEVEL_TRACE, fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define CTC_PRINT_TRACE8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CTC, LEVEL_TRACE, fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+
+/* Bluetooth HCI Trace Interfaces */
+#define HCI_PRINT_ERROR0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_HCI, LEVEL_ERROR, "!!!"fmt, 0)
+#define HCI_PRINT_ERROR1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_HCI, LEVEL_ERROR, "!!!"fmt, 1, arg0)
+#define HCI_PRINT_ERROR2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_HCI, LEVEL_ERROR, "!!!"fmt, 2, arg0, arg1)
+#define HCI_PRINT_ERROR3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_HCI, LEVEL_ERROR, "!!!"fmt, 3, arg0, arg1, arg2)
+#define HCI_PRINT_ERROR4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_HCI, LEVEL_ERROR, "!!!"fmt, 4, arg0, arg1, arg2, arg3)
+#define HCI_PRINT_ERROR5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_HCI, LEVEL_ERROR, "!!!"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define HCI_PRINT_ERROR6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_HCI, LEVEL_ERROR, "!!!"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define HCI_PRINT_ERROR7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_HCI, LEVEL_ERROR, "!!!"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define HCI_PRINT_ERROR8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_HCI, LEVEL_ERROR, "!!!"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define HCI_PRINT_WARN0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_HCI, LEVEL_WARN, "!!*"fmt, 0)
+#define HCI_PRINT_WARN1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_HCI, LEVEL_WARN, "!!*"fmt, 1, arg0)
+#define HCI_PRINT_WARN2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_HCI, LEVEL_WARN, "!!*"fmt, 2, arg0, arg1)
+#define HCI_PRINT_WARN3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_HCI, LEVEL_WARN, "!!*"fmt, 3, arg0, arg1, arg2)
+#define HCI_PRINT_WARN4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_HCI, LEVEL_WARN, "!!*"fmt, 4, arg0, arg1, arg2, arg3)
+#define HCI_PRINT_WARN5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_HCI, LEVEL_WARN, "!!*"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define HCI_PRINT_WARN6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_HCI, LEVEL_WARN, "!!*"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define HCI_PRINT_WARN7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_HCI, LEVEL_WARN, "!!*"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define HCI_PRINT_WARN8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_HCI, LEVEL_WARN, "!!*"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define HCI_PRINT_INFO0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_HCI, LEVEL_INFO, "!**"fmt, 0)
+#define HCI_PRINT_INFO1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_HCI, LEVEL_INFO, "!**"fmt, 1, arg0)
+#define HCI_PRINT_INFO2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_HCI, LEVEL_INFO, "!**"fmt, 2, arg0, arg1)
+#define HCI_PRINT_INFO3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_HCI, LEVEL_INFO, "!**"fmt, 3, arg0, arg1, arg2)
+#define HCI_PRINT_INFO4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_HCI, LEVEL_INFO, "!**"fmt, 4, arg0, arg1, arg2, arg3)
+#define HCI_PRINT_INFO5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_HCI, LEVEL_INFO, "!**"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define HCI_PRINT_INFO6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_HCI, LEVEL_INFO, "!**"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define HCI_PRINT_INFO7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_HCI, LEVEL_INFO, "!**"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define HCI_PRINT_INFO8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_HCI, LEVEL_INFO, "!**"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define HCI_PRINT_TRACE0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_HCI, LEVEL_TRACE, fmt, 0)
+#define HCI_PRINT_TRACE1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_HCI, LEVEL_TRACE, fmt, 1, arg0)
+#define HCI_PRINT_TRACE2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_HCI, LEVEL_TRACE, fmt, 2, arg0, arg1)
+#define HCI_PRINT_TRACE3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_HCI, LEVEL_TRACE, fmt, 3, arg0, arg1, arg2)
+#define HCI_PRINT_TRACE4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_HCI, LEVEL_TRACE, fmt, 4, arg0, arg1, arg2, arg3)
+#define HCI_PRINT_TRACE5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_HCI, LEVEL_TRACE, fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define HCI_PRINT_TRACE6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_HCI, LEVEL_TRACE, fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define HCI_PRINT_TRACE7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_HCI, LEVEL_TRACE, fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define HCI_PRINT_TRACE8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_HCI, LEVEL_TRACE, fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+
+
+/* Bluetooth L2CAP Trace Interfaces */
+#define L2CAP_PRINT_ERROR0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_L2CAP, LEVEL_ERROR, "!!!"fmt, 0)
+#define L2CAP_PRINT_ERROR1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_L2CAP, LEVEL_ERROR, "!!!"fmt, 1, arg0)
+#define L2CAP_PRINT_ERROR2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_L2CAP, LEVEL_ERROR, "!!!"fmt, 2, arg0, arg1)
+#define L2CAP_PRINT_ERROR3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_L2CAP, LEVEL_ERROR, "!!!"fmt, 3, arg0, arg1, arg2)
+#define L2CAP_PRINT_ERROR4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_L2CAP, LEVEL_ERROR, "!!!"fmt, 4, arg0, arg1, arg2, arg3)
+#define L2CAP_PRINT_ERROR5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_L2CAP, LEVEL_ERROR, "!!!"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define L2CAP_PRINT_ERROR6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_L2CAP, LEVEL_ERROR, "!!!"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define L2CAP_PRINT_ERROR7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_L2CAP, LEVEL_ERROR, "!!!"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define L2CAP_PRINT_ERROR8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_L2CAP, LEVEL_ERROR, "!!!"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define L2CAP_PRINT_WARN0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_L2CAP, LEVEL_WARN, "!!*"fmt, 0)
+#define L2CAP_PRINT_WARN1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_L2CAP, LEVEL_WARN, "!!*"fmt, 1, arg0)
+#define L2CAP_PRINT_WARN2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_L2CAP, LEVEL_WARN, "!!*"fmt, 2, arg0, arg1)
+#define L2CAP_PRINT_WARN3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_L2CAP, LEVEL_WARN, "!!*"fmt, 3, arg0, arg1, arg2)
+#define L2CAP_PRINT_WARN4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_L2CAP, LEVEL_WARN, "!!*"fmt, 4, arg0, arg1, arg2, arg3)
+#define L2CAP_PRINT_WARN5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_L2CAP, LEVEL_WARN, "!!*"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define L2CAP_PRINT_WARN6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_L2CAP, LEVEL_WARN, "!!*"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define L2CAP_PRINT_WARN7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_L2CAP, LEVEL_WARN, "!!*"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define L2CAP_PRINT_WARN8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_L2CAP, LEVEL_WARN, "!!*"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define L2CAP_PRINT_INFO0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_L2CAP, LEVEL_INFO, "!**"fmt, 0)
+#define L2CAP_PRINT_INFO1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_L2CAP, LEVEL_INFO, "!**"fmt, 1, arg0)
+#define L2CAP_PRINT_INFO2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_L2CAP, LEVEL_INFO, "!**"fmt, 2, arg0, arg1)
+#define L2CAP_PRINT_INFO3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_L2CAP, LEVEL_INFO, "!**"fmt, 3, arg0, arg1, arg2)
+#define L2CAP_PRINT_INFO4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_L2CAP, LEVEL_INFO, "!**"fmt, 4, arg0, arg1, arg2, arg3)
+#define L2CAP_PRINT_INFO5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_L2CAP, LEVEL_INFO, "!**"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define L2CAP_PRINT_INFO6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_L2CAP, LEVEL_INFO, "!**"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define L2CAP_PRINT_INFO7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_L2CAP, LEVEL_INFO, "!**"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define L2CAP_PRINT_INFO8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_L2CAP, LEVEL_INFO, "!**"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define L2CAP_PRINT_TRACE0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_L2CAP, LEVEL_TRACE, fmt, 0)
+#define L2CAP_PRINT_TRACE1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_L2CAP, LEVEL_TRACE, fmt, 1, arg0)
+#define L2CAP_PRINT_TRACE2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_L2CAP, LEVEL_TRACE, fmt, 2, arg0, arg1)
+#define L2CAP_PRINT_TRACE3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_L2CAP, LEVEL_TRACE, fmt, 3, arg0, arg1, arg2)
+#define L2CAP_PRINT_TRACE4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_L2CAP, LEVEL_TRACE, fmt, 4, arg0, arg1, arg2, arg3)
+#define L2CAP_PRINT_TRACE5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_L2CAP, LEVEL_TRACE, fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define L2CAP_PRINT_TRACE6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_L2CAP, LEVEL_TRACE, fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define L2CAP_PRINT_TRACE7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_L2CAP, LEVEL_TRACE, fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define L2CAP_PRINT_TRACE8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_L2CAP, LEVEL_TRACE, fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+
+
+/* Bluetooth SDP Trace Interfaces */
+#define SDP_PRINT_ERROR0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SDP, LEVEL_ERROR, "!!!"fmt, 0)
+#define SDP_PRINT_ERROR1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SDP, LEVEL_ERROR, "!!!"fmt, 1, arg0)
+#define SDP_PRINT_ERROR2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SDP, LEVEL_ERROR, "!!!"fmt, 2, arg0, arg1)
+#define SDP_PRINT_ERROR3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SDP, LEVEL_ERROR, "!!!"fmt, 3, arg0, arg1, arg2)
+#define SDP_PRINT_ERROR4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SDP, LEVEL_ERROR, "!!!"fmt, 4, arg0, arg1, arg2, arg3)
+#define SDP_PRINT_ERROR5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SDP, LEVEL_ERROR, "!!!"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define SDP_PRINT_ERROR6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SDP, LEVEL_ERROR, "!!!"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define SDP_PRINT_ERROR7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SDP, LEVEL_ERROR, "!!!"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define SDP_PRINT_ERROR8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SDP, LEVEL_ERROR, "!!!"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define SDP_PRINT_WARN0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SDP, LEVEL_WARN, "!!*"fmt, 0)
+#define SDP_PRINT_WARN1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SDP, LEVEL_WARN, "!!*"fmt, 1, arg0)
+#define SDP_PRINT_WARN2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SDP, LEVEL_WARN, "!!*"fmt, 2, arg0, arg1)
+#define SDP_PRINT_WARN3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SDP, LEVEL_WARN, "!!*"fmt, 3, arg0, arg1, arg2)
+#define SDP_PRINT_WARN4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SDP, LEVEL_WARN, "!!*"fmt, 4, arg0, arg1, arg2, arg3)
+#define SDP_PRINT_WARN5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SDP, LEVEL_WARN, "!!*"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define SDP_PRINT_WARN6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SDP, LEVEL_WARN, "!!*"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define SDP_PRINT_WARN7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SDP, LEVEL_WARN, "!!*"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define SDP_PRINT_WARN8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SDP, LEVEL_WARN, "!!*"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define SDP_PRINT_INFO0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SDP, LEVEL_INFO, "!**"fmt, 0)
+#define SDP_PRINT_INFO1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SDP, LEVEL_INFO, "!**"fmt, 1, arg0)
+#define SDP_PRINT_INFO2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SDP, LEVEL_INFO, "!**"fmt, 2, arg0, arg1)
+#define SDP_PRINT_INFO3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SDP, LEVEL_INFO, "!**"fmt, 3, arg0, arg1, arg2)
+#define SDP_PRINT_INFO4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SDP, LEVEL_INFO, "!**"fmt, 4, arg0, arg1, arg2, arg3)
+#define SDP_PRINT_INFO5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SDP, LEVEL_INFO, "!**"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define SDP_PRINT_INFO6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SDP, LEVEL_INFO, "!**"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define SDP_PRINT_INFO7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SDP, LEVEL_INFO, "!**"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define SDP_PRINT_INFO8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SDP, LEVEL_INFO, "!**"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define SDP_PRINT_TRACE0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SDP, LEVEL_TRACE, fmt, 0)
+#define SDP_PRINT_TRACE1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SDP, LEVEL_TRACE, fmt, 1, arg0)
+#define SDP_PRINT_TRACE2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SDP, LEVEL_TRACE, fmt, 2, arg0, arg1)
+#define SDP_PRINT_TRACE3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SDP, LEVEL_TRACE, fmt, 3, arg0, arg1, arg2)
+#define SDP_PRINT_TRACE4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SDP, LEVEL_TRACE, fmt, 4, arg0, arg1, arg2, arg3)
+#define SDP_PRINT_TRACE5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SDP, LEVEL_TRACE, fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define SDP_PRINT_TRACE6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SDP, LEVEL_TRACE, fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define SDP_PRINT_TRACE7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SDP, LEVEL_TRACE, fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define SDP_PRINT_TRACE8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SDP, LEVEL_TRACE, fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+
+
+/* Bluetooth SMP Trace Interfaces */
+#define SMP_PRINT_ERROR0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SMP, LEVEL_ERROR, "!!!"fmt, 0)
+#define SMP_PRINT_ERROR1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SMP, LEVEL_ERROR, "!!!"fmt, 1, arg0)
+#define SMP_PRINT_ERROR2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SMP, LEVEL_ERROR, "!!!"fmt, 2, arg0, arg1)
+#define SMP_PRINT_ERROR3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SMP, LEVEL_ERROR, "!!!"fmt, 3, arg0, arg1, arg2)
+#define SMP_PRINT_ERROR4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SMP, LEVEL_ERROR, "!!!"fmt, 4, arg0, arg1, arg2, arg3)
+#define SMP_PRINT_ERROR5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SMP, LEVEL_ERROR, "!!!"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define SMP_PRINT_ERROR6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SMP, LEVEL_ERROR, "!!!"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define SMP_PRINT_ERROR7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SMP, LEVEL_ERROR, "!!!"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define SMP_PRINT_ERROR8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SMP, LEVEL_ERROR, "!!!"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define SMP_PRINT_WARN0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SMP, LEVEL_WARN, "!!*"fmt, 0)
+#define SMP_PRINT_WARN1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SMP, LEVEL_WARN, "!!*"fmt, 1, arg0)
+#define SMP_PRINT_WARN2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SMP, LEVEL_WARN, "!!*"fmt, 2, arg0, arg1)
+#define SMP_PRINT_WARN3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SMP, LEVEL_WARN, "!!*"fmt, 3, arg0, arg1, arg2)
+#define SMP_PRINT_WARN4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SMP, LEVEL_WARN, "!!*"fmt, 4, arg0, arg1, arg2, arg3)
+#define SMP_PRINT_WARN5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SMP, LEVEL_WARN, "!!*"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define SMP_PRINT_WARN6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SMP, LEVEL_WARN, "!!*"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define SMP_PRINT_WARN7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SMP, LEVEL_WARN, "!!*"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define SMP_PRINT_WARN8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SMP, LEVEL_WARN, "!!*"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define SMP_PRINT_INFO0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SMP, LEVEL_INFO, "!**"fmt, 0)
+#define SMP_PRINT_INFO1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SMP, LEVEL_INFO, "!**"fmt, 1, arg0)
+#define SMP_PRINT_INFO2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SMP, LEVEL_INFO, "!**"fmt, 2, arg0, arg1)
+#define SMP_PRINT_INFO3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SMP, LEVEL_INFO, "!**"fmt, 3, arg0, arg1, arg2)
+#define SMP_PRINT_INFO4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SMP, LEVEL_INFO, "!**"fmt, 4, arg0, arg1, arg2, arg3)
+#define SMP_PRINT_INFO5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SMP, LEVEL_INFO, "!**"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define SMP_PRINT_INFO6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SMP, LEVEL_INFO, "!**"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define SMP_PRINT_INFO7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SMP, LEVEL_INFO, "!**"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define SMP_PRINT_INFO8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SMP, LEVEL_INFO, "!**"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define SMP_PRINT_TRACE0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SMP, LEVEL_TRACE, fmt, 0)
+#define SMP_PRINT_TRACE1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SMP, LEVEL_TRACE, fmt, 1, arg0)
+#define SMP_PRINT_TRACE2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SMP, LEVEL_TRACE, fmt, 2, arg0, arg1)
+#define SMP_PRINT_TRACE3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SMP, LEVEL_TRACE, fmt, 3, arg0, arg1, arg2)
+#define SMP_PRINT_TRACE4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SMP, LEVEL_TRACE, fmt, 4, arg0, arg1, arg2, arg3)
+#define SMP_PRINT_TRACE5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SMP, LEVEL_TRACE, fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define SMP_PRINT_TRACE6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SMP, LEVEL_TRACE, fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define SMP_PRINT_TRACE7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SMP, LEVEL_TRACE, fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define SMP_PRINT_TRACE8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SMP, LEVEL_TRACE, fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+
+
+/* Bluetooth GATT Trace Interfaces */
+#define GATT_PRINT_ERROR0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GATT, LEVEL_ERROR, "!!!"fmt, 0)
+#define GATT_PRINT_ERROR1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GATT, LEVEL_ERROR, "!!!"fmt, 1, arg0)
+#define GATT_PRINT_ERROR2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GATT, LEVEL_ERROR, "!!!"fmt, 2, arg0, arg1)
+#define GATT_PRINT_ERROR3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GATT, LEVEL_ERROR, "!!!"fmt, 3, arg0, arg1, arg2)
+#define GATT_PRINT_ERROR4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GATT, LEVEL_ERROR, "!!!"fmt, 4, arg0, arg1, arg2, arg3)
+#define GATT_PRINT_ERROR5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GATT, LEVEL_ERROR, "!!!"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define GATT_PRINT_ERROR6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GATT, LEVEL_ERROR, "!!!"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define GATT_PRINT_ERROR7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GATT, LEVEL_ERROR, "!!!"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define GATT_PRINT_ERROR8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GATT, LEVEL_ERROR, "!!!"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define GATT_PRINT_WARN0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GATT, LEVEL_WARN, "!!*"fmt, 0)
+#define GATT_PRINT_WARN1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GATT, LEVEL_WARN, "!!*"fmt, 1, arg0)
+#define GATT_PRINT_WARN2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GATT, LEVEL_WARN, "!!*"fmt, 2, arg0, arg1)
+#define GATT_PRINT_WARN3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GATT, LEVEL_WARN, "!!*"fmt, 3, arg0, arg1, arg2)
+#define GATT_PRINT_WARN4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GATT, LEVEL_WARN, "!!*"fmt, 4, arg0, arg1, arg2, arg3)
+#define GATT_PRINT_WARN5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GATT, LEVEL_WARN, "!!*"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define GATT_PRINT_WARN6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GATT, LEVEL_WARN, "!!*"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define GATT_PRINT_WARN7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GATT, LEVEL_WARN, "!!*"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define GATT_PRINT_WARN8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GATT, LEVEL_WARN, "!!*"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define GATT_PRINT_INFO0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GATT, LEVEL_INFO, "!**"fmt, 0)
+#define GATT_PRINT_INFO1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GATT, LEVEL_INFO, "!**"fmt, 1, arg0)
+#define GATT_PRINT_INFO2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GATT, LEVEL_INFO, "!**"fmt, 2, arg0, arg1)
+#define GATT_PRINT_INFO3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GATT, LEVEL_INFO, "!**"fmt, 3, arg0, arg1, arg2)
+#define GATT_PRINT_INFO4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GATT, LEVEL_INFO, "!**"fmt, 4, arg0, arg1, arg2, arg3)
+#define GATT_PRINT_INFO5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GATT, LEVEL_INFO, "!**"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define GATT_PRINT_INFO6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GATT, LEVEL_INFO, "!**"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define GATT_PRINT_INFO7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GATT, LEVEL_INFO, "!**"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define GATT_PRINT_INFO8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GATT, LEVEL_INFO, "!**"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define GATT_PRINT_TRACE0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GATT, LEVEL_TRACE, fmt, 0)
+#define GATT_PRINT_TRACE1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GATT, LEVEL_TRACE, fmt, 1, arg0)
+#define GATT_PRINT_TRACE2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GATT, LEVEL_TRACE, fmt, 2, arg0, arg1)
+#define GATT_PRINT_TRACE3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GATT, LEVEL_TRACE, fmt, 3, arg0, arg1, arg2)
+#define GATT_PRINT_TRACE4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GATT, LEVEL_TRACE, fmt, 4, arg0, arg1, arg2, arg3)
+#define GATT_PRINT_TRACE5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GATT, LEVEL_TRACE, fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define GATT_PRINT_TRACE6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GATT, LEVEL_TRACE, fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define GATT_PRINT_TRACE7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GATT, LEVEL_TRACE, fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define GATT_PRINT_TRACE8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GATT, LEVEL_TRACE, fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+
+
+/* Bluetooth BTIF Trace Interfaces */
+#define BTIF_PRINT_ERROR0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTIF, LEVEL_ERROR, "!!!"fmt, 0)
+#define BTIF_PRINT_ERROR1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTIF, LEVEL_ERROR, "!!!"fmt, 1, arg0)
+#define BTIF_PRINT_ERROR2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTIF, LEVEL_ERROR, "!!!"fmt, 2, arg0, arg1)
+#define BTIF_PRINT_ERROR3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTIF, LEVEL_ERROR, "!!!"fmt, 3, arg0, arg1, arg2)
+#define BTIF_PRINT_ERROR4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTIF, LEVEL_ERROR, "!!!"fmt, 4, arg0, arg1, arg2, arg3)
+#define BTIF_PRINT_ERROR5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTIF, LEVEL_ERROR, "!!!"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define BTIF_PRINT_ERROR6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTIF, LEVEL_ERROR, "!!!"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define BTIF_PRINT_ERROR7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTIF, LEVEL_ERROR, "!!!"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define BTIF_PRINT_ERROR8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTIF, LEVEL_ERROR, "!!!"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define BTIF_PRINT_WARN0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTIF, LEVEL_WARN, "!!*"fmt, 0)
+#define BTIF_PRINT_WARN1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTIF, LEVEL_WARN, "!!*"fmt, 1, arg0)
+#define BTIF_PRINT_WARN2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTIF, LEVEL_WARN, "!!*"fmt, 2, arg0, arg1)
+#define BTIF_PRINT_WARN3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTIF, LEVEL_WARN, "!!*"fmt, 3, arg0, arg1, arg2)
+#define BTIF_PRINT_WARN4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTIF, LEVEL_WARN, "!!*"fmt, 4, arg0, arg1, arg2, arg3)
+#define BTIF_PRINT_WARN5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTIF, LEVEL_WARN, "!!*"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define BTIF_PRINT_WARN6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTIF, LEVEL_WARN, "!!*"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define BTIF_PRINT_WARN7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTIF, LEVEL_WARN, "!!*"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define BTIF_PRINT_WARN8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTIF, LEVEL_WARN, "!!*"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define BTIF_PRINT_INFO0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTIF, LEVEL_INFO, "!**"fmt, 0)
+#define BTIF_PRINT_INFO1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTIF, LEVEL_INFO, "!**"fmt, 1, arg0)
+#define BTIF_PRINT_INFO2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTIF, LEVEL_INFO, "!**"fmt, 2, arg0, arg1)
+#define BTIF_PRINT_INFO3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTIF, LEVEL_INFO, "!**"fmt, 3, arg0, arg1, arg2)
+#define BTIF_PRINT_INFO4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTIF, LEVEL_INFO, "!**"fmt, 4, arg0, arg1, arg2, arg3)
+#define BTIF_PRINT_INFO5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTIF, LEVEL_INFO, "!**"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define BTIF_PRINT_INFO6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTIF, LEVEL_INFO, "!**"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define BTIF_PRINT_INFO7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTIF, LEVEL_INFO, "!**"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define BTIF_PRINT_INFO8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTIF, LEVEL_INFO, "!**"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define BTIF_PRINT_TRACE0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTIF, LEVEL_TRACE, fmt, 0)
+#define BTIF_PRINT_TRACE1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTIF, LEVEL_TRACE, fmt, 1, arg0)
+#define BTIF_PRINT_TRACE2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTIF, LEVEL_TRACE, fmt, 2, arg0, arg1)
+#define BTIF_PRINT_TRACE3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTIF, LEVEL_TRACE, fmt, 3, arg0, arg1, arg2)
+#define BTIF_PRINT_TRACE4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTIF, LEVEL_TRACE, fmt, 4, arg0, arg1, arg2, arg3)
+#define BTIF_PRINT_TRACE5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTIF, LEVEL_TRACE, fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define BTIF_PRINT_TRACE6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTIF, LEVEL_TRACE, fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define BTIF_PRINT_TRACE7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTIF, LEVEL_TRACE, fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define BTIF_PRINT_TRACE8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTIF, LEVEL_TRACE, fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+
+
+/* Bluetooth BTE Trace Interfaces */
+#define BTE_PRINT_ERROR0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTE, LEVEL_ERROR, "!!!"fmt, 0)
+#define BTE_PRINT_ERROR1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTE, LEVEL_ERROR, "!!!"fmt, 1, arg0)
+#define BTE_PRINT_ERROR2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTE, LEVEL_ERROR, "!!!"fmt, 2, arg0, arg1)
+#define BTE_PRINT_ERROR3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTE, LEVEL_ERROR, "!!!"fmt, 3, arg0, arg1, arg2)
+#define BTE_PRINT_ERROR4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTE, LEVEL_ERROR, "!!!"fmt, 4, arg0, arg1, arg2, arg3)
+#define BTE_PRINT_ERROR5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTE, LEVEL_ERROR, "!!!"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define BTE_PRINT_ERROR6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTE, LEVEL_ERROR, "!!!"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define BTE_PRINT_ERROR7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTE, LEVEL_ERROR, "!!!"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define BTE_PRINT_ERROR8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTE, LEVEL_ERROR, "!!!"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define BTE_PRINT_WARN0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTE, LEVEL_WARN, "!!*"fmt, 0)
+#define BTE_PRINT_WARN1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTE, LEVEL_WARN, "!!*"fmt, 1, arg0)
+#define BTE_PRINT_WARN2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTE, LEVEL_WARN, "!!*"fmt, 2, arg0, arg1)
+#define BTE_PRINT_WARN3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTE, LEVEL_WARN, "!!*"fmt, 3, arg0, arg1, arg2)
+#define BTE_PRINT_WARN4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTE, LEVEL_WARN, "!!*"fmt, 4, arg0, arg1, arg2, arg3)
+#define BTE_PRINT_WARN5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTE, LEVEL_WARN, "!!*"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define BTE_PRINT_WARN6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTE, LEVEL_WARN, "!!*"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define BTE_PRINT_WARN7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTE, LEVEL_WARN, "!!*"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define BTE_PRINT_WARN8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTE, LEVEL_WARN, "!!*"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define BTE_PRINT_INFO0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTE, LEVEL_INFO, "!**"fmt, 0)
+#define BTE_PRINT_INFO1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTE, LEVEL_INFO, "!**"fmt, 1, arg0)
+#define BTE_PRINT_INFO2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTE, LEVEL_INFO, "!**"fmt, 2, arg0, arg1)
+#define BTE_PRINT_INFO3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTE, LEVEL_INFO, "!**"fmt, 3, arg0, arg1, arg2)
+#define BTE_PRINT_INFO4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTE, LEVEL_INFO, "!**"fmt, 4, arg0, arg1, arg2, arg3)
+#define BTE_PRINT_INFO5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTE, LEVEL_INFO, "!**"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define BTE_PRINT_INFO6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTE, LEVEL_INFO, "!**"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define BTE_PRINT_INFO7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTE, LEVEL_INFO, "!**"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define BTE_PRINT_INFO8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTE, LEVEL_INFO, "!**"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define BTE_PRINT_TRACE0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTE, LEVEL_TRACE, fmt, 0)
+#define BTE_PRINT_TRACE1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTE, LEVEL_TRACE, fmt, 1, arg0)
+#define BTE_PRINT_TRACE2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTE, LEVEL_TRACE, fmt, 2, arg0, arg1)
+#define BTE_PRINT_TRACE3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTE, LEVEL_TRACE, fmt, 3, arg0, arg1, arg2)
+#define BTE_PRINT_TRACE4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTE, LEVEL_TRACE, fmt, 4, arg0, arg1, arg2, arg3)
+#define BTE_PRINT_TRACE5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTE, LEVEL_TRACE, fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define BTE_PRINT_TRACE6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTE, LEVEL_TRACE, fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define BTE_PRINT_TRACE7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTE, LEVEL_TRACE, fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define BTE_PRINT_TRACE8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTE, LEVEL_TRACE, fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+
+
+/* Bluetooth GAP Trace Interfaces */
+#define GAP_PRINT_ERROR0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GAP, LEVEL_ERROR, "!!!"fmt, 0)
+#define GAP_PRINT_ERROR1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GAP, LEVEL_ERROR, "!!!"fmt, 1, arg0)
+#define GAP_PRINT_ERROR2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GAP, LEVEL_ERROR, "!!!"fmt, 2, arg0, arg1)
+#define GAP_PRINT_ERROR3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GAP, LEVEL_ERROR, "!!!"fmt, 3, arg0, arg1, arg2)
+#define GAP_PRINT_ERROR4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GAP, LEVEL_ERROR, "!!!"fmt, 4, arg0, arg1, arg2, arg3)
+#define GAP_PRINT_ERROR5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GAP, LEVEL_ERROR, "!!!"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define GAP_PRINT_ERROR6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GAP, LEVEL_ERROR, "!!!"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define GAP_PRINT_ERROR7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GAP, LEVEL_ERROR, "!!!"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define GAP_PRINT_ERROR8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GAP, LEVEL_ERROR, "!!!"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define GAP_PRINT_WARN0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GAP, LEVEL_WARN, "!!*"fmt, 0)
+#define GAP_PRINT_WARN1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GAP, LEVEL_WARN, "!!*"fmt, 1, arg0)
+#define GAP_PRINT_WARN2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GAP, LEVEL_WARN, "!!*"fmt, 2, arg0, arg1)
+#define GAP_PRINT_WARN3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GAP, LEVEL_WARN, "!!*"fmt, 3, arg0, arg1, arg2)
+#define GAP_PRINT_WARN4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GAP, LEVEL_WARN, "!!*"fmt, 4, arg0, arg1, arg2, arg3)
+#define GAP_PRINT_WARN5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GAP, LEVEL_WARN, "!!*"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define GAP_PRINT_WARN6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GAP, LEVEL_WARN, "!!*"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define GAP_PRINT_WARN7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GAP, LEVEL_WARN, "!!*"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define GAP_PRINT_WARN8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GAP, LEVEL_WARN, "!!*"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define GAP_PRINT_INFO0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GAP, LEVEL_INFO, "!**"fmt, 0)
+#define GAP_PRINT_INFO1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GAP, LEVEL_INFO, "!**"fmt, 1, arg0)
+#define GAP_PRINT_INFO2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GAP, LEVEL_INFO, "!**"fmt, 2, arg0, arg1)
+#define GAP_PRINT_INFO3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GAP, LEVEL_INFO, "!**"fmt, 3, arg0, arg1, arg2)
+#define GAP_PRINT_INFO4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GAP, LEVEL_INFO, "!**"fmt, 4, arg0, arg1, arg2, arg3)
+#define GAP_PRINT_INFO5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GAP, LEVEL_INFO, "!**"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define GAP_PRINT_INFO6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GAP, LEVEL_INFO, "!**"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define GAP_PRINT_INFO7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GAP, LEVEL_INFO, "!**"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define GAP_PRINT_INFO8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GAP, LEVEL_INFO, "!**"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define GAP_PRINT_TRACE0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GAP, LEVEL_TRACE, fmt, 0)
+#define GAP_PRINT_TRACE1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GAP, LEVEL_TRACE, fmt, 1, arg0)
+#define GAP_PRINT_TRACE2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GAP, LEVEL_TRACE, fmt, 2, arg0, arg1)
+#define GAP_PRINT_TRACE3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GAP, LEVEL_TRACE, fmt, 3, arg0, arg1, arg2)
+#define GAP_PRINT_TRACE4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GAP, LEVEL_TRACE, fmt, 4, arg0, arg1, arg2, arg3)
+#define GAP_PRINT_TRACE5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GAP, LEVEL_TRACE, fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define GAP_PRINT_TRACE6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GAP, LEVEL_TRACE, fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define GAP_PRINT_TRACE7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GAP, LEVEL_TRACE, fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define GAP_PRINT_TRACE8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GAP, LEVEL_TRACE, fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+
+
+/* Bluetooth RFCOMM Trace Interfaces */
+#define RFCOMM_PRINT_ERROR0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_RFCOMM, LEVEL_ERROR, "!!!"fmt, 0)
+#define RFCOMM_PRINT_ERROR1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_RFCOMM, LEVEL_ERROR, "!!!"fmt, 1, arg0)
+#define RFCOMM_PRINT_ERROR2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_RFCOMM, LEVEL_ERROR, "!!!"fmt, 2, arg0, arg1)
+#define RFCOMM_PRINT_ERROR3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_RFCOMM, LEVEL_ERROR, "!!!"fmt, 3, arg0, arg1, arg2)
+#define RFCOMM_PRINT_ERROR4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_RFCOMM, LEVEL_ERROR, "!!!"fmt, 4, arg0, arg1, arg2, arg3)
+#define RFCOMM_PRINT_ERROR5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_RFCOMM, LEVEL_ERROR, "!!!"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define RFCOMM_PRINT_ERROR6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_RFCOMM, LEVEL_ERROR, "!!!"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define RFCOMM_PRINT_ERROR7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_RFCOMM, LEVEL_ERROR, "!!!"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define RFCOMM_PRINT_ERROR8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_RFCOMM, LEVEL_ERROR, "!!!"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define RFCOMM_PRINT_WARN0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_RFCOMM, LEVEL_WARN, "!!*"fmt, 0)
+#define RFCOMM_PRINT_WARN1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_RFCOMM, LEVEL_WARN, "!!*"fmt, 1, arg0)
+#define RFCOMM_PRINT_WARN2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_RFCOMM, LEVEL_WARN, "!!*"fmt, 2, arg0, arg1)
+#define RFCOMM_PRINT_WARN3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_RFCOMM, LEVEL_WARN, "!!*"fmt, 3, arg0, arg1, arg2)
+#define RFCOMM_PRINT_WARN4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_RFCOMM, LEVEL_WARN, "!!*"fmt, 4, arg0, arg1, arg2, arg3)
+#define RFCOMM_PRINT_WARN5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_RFCOMM, LEVEL_WARN, "!!*"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define RFCOMM_PRINT_WARN6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_RFCOMM, LEVEL_WARN, "!!*"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define RFCOMM_PRINT_WARN7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_RFCOMM, LEVEL_WARN, "!!*"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define RFCOMM_PRINT_WARN8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_RFCOMM, LEVEL_WARN, "!!*"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define RFCOMM_PRINT_INFO0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_RFCOMM, LEVEL_INFO, "!**"fmt, 0)
+#define RFCOMM_PRINT_INFO1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_RFCOMM, LEVEL_INFO, "!**"fmt, 1, arg0)
+#define RFCOMM_PRINT_INFO2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_RFCOMM, LEVEL_INFO, "!**"fmt, 2, arg0, arg1)
+#define RFCOMM_PRINT_INFO3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_RFCOMM, LEVEL_INFO, "!**"fmt, 3, arg0, arg1, arg2)
+#define RFCOMM_PRINT_INFO4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_RFCOMM, LEVEL_INFO, "!**"fmt, 4, arg0, arg1, arg2, arg3)
+#define RFCOMM_PRINT_INFO5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_RFCOMM, LEVEL_INFO, "!**"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define RFCOMM_PRINT_INFO6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_RFCOMM, LEVEL_INFO, "!**"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define RFCOMM_PRINT_INFO7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_RFCOMM, LEVEL_INFO, "!**"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define RFCOMM_PRINT_INFO8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_RFCOMM, LEVEL_INFO, "!**"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define RFCOMM_PRINT_TRACE0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_RFCOMM, LEVEL_TRACE, fmt, 0)
+#define RFCOMM_PRINT_TRACE1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_RFCOMM, LEVEL_TRACE, fmt, 1, arg0)
+#define RFCOMM_PRINT_TRACE2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_RFCOMM, LEVEL_TRACE, fmt, 2, arg0, arg1)
+#define RFCOMM_PRINT_TRACE3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_RFCOMM, LEVEL_TRACE, fmt, 3, arg0, arg1, arg2)
+#define RFCOMM_PRINT_TRACE4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_RFCOMM, LEVEL_TRACE, fmt, 4, arg0, arg1, arg2, arg3)
+#define RFCOMM_PRINT_TRACE5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_RFCOMM, LEVEL_TRACE, fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define RFCOMM_PRINT_TRACE6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_RFCOMM, LEVEL_TRACE, fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define RFCOMM_PRINT_TRACE7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_RFCOMM, LEVEL_TRACE, fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define RFCOMM_PRINT_TRACE8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_RFCOMM, LEVEL_TRACE, fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+
+
+/* Bluetooth Protocol Trace Interfaces */
+#define PROTOCOL_PRINT_ERROR0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROTOCOL, LEVEL_ERROR, "!!!"fmt, 0)
+#define PROTOCOL_PRINT_ERROR1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROTOCOL, LEVEL_ERROR, "!!!"fmt, 1, arg0)
+#define PROTOCOL_PRINT_ERROR2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROTOCOL, LEVEL_ERROR, "!!!"fmt, 2, arg0, arg1)
+#define PROTOCOL_PRINT_ERROR3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROTOCOL, LEVEL_ERROR, "!!!"fmt, 3, arg0, arg1, arg2)
+#define PROTOCOL_PRINT_ERROR4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROTOCOL, LEVEL_ERROR, "!!!"fmt, 4, arg0, arg1, arg2, arg3)
+#define PROTOCOL_PRINT_ERROR5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROTOCOL, LEVEL_ERROR, "!!!"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define PROTOCOL_PRINT_ERROR6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROTOCOL, LEVEL_ERROR, "!!!"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define PROTOCOL_PRINT_ERROR7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROTOCOL, LEVEL_ERROR, "!!!"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define PROTOCOL_PRINT_ERROR8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROTOCOL, LEVEL_ERROR, "!!!"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define PROTOCOL_PRINT_WARN0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROTOCOL, LEVEL_WARN, "!!*"fmt, 0)
+#define PROTOCOL_PRINT_WARN1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROTOCOL, LEVEL_WARN, "!!*"fmt, 1, arg0)
+#define PROTOCOL_PRINT_WARN2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROTOCOL, LEVEL_WARN, "!!*"fmt, 2, arg0, arg1)
+#define PROTOCOL_PRINT_WARN3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROTOCOL, LEVEL_WARN, "!!*"fmt, 3, arg0, arg1, arg2)
+#define PROTOCOL_PRINT_WARN4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROTOCOL, LEVEL_WARN, "!!*"fmt, 4, arg0, arg1, arg2, arg3)
+#define PROTOCOL_PRINT_WARN5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROTOCOL, LEVEL_WARN, "!!*"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define PROTOCOL_PRINT_WARN6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROTOCOL, LEVEL_WARN, "!!*"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define PROTOCOL_PRINT_WARN7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROTOCOL, LEVEL_WARN, "!!*"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define PROTOCOL_PRINT_WARN8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROTOCOL, LEVEL_WARN, "!!*"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define PROTOCOL_PRINT_INFO0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROTOCOL, LEVEL_INFO, "!**"fmt, 0)
+#define PROTOCOL_PRINT_INFO1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROTOCOL, LEVEL_INFO, "!**"fmt, 1, arg0)
+#define PROTOCOL_PRINT_INFO2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROTOCOL, LEVEL_INFO, "!**"fmt, 2, arg0, arg1)
+#define PROTOCOL_PRINT_INFO3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROTOCOL, LEVEL_INFO, "!**"fmt, 3, arg0, arg1, arg2)
+#define PROTOCOL_PRINT_INFO4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROTOCOL, LEVEL_INFO, "!**"fmt, 4, arg0, arg1, arg2, arg3)
+#define PROTOCOL_PRINT_INFO5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROTOCOL, LEVEL_INFO, "!**"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define PROTOCOL_PRINT_INFO6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROTOCOL, LEVEL_INFO, "!**"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define PROTOCOL_PRINT_INFO7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROTOCOL, LEVEL_INFO, "!**"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define PROTOCOL_PRINT_INFO8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROTOCOL, LEVEL_INFO, "!**"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define PROTOCOL_PRINT_TRACE0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROTOCOL, LEVEL_TRACE, fmt, 0)
+#define PROTOCOL_PRINT_TRACE1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROTOCOL, LEVEL_TRACE, fmt, 1, arg0)
+#define PROTOCOL_PRINT_TRACE2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROTOCOL, LEVEL_TRACE, fmt, 2, arg0, arg1)
+#define PROTOCOL_PRINT_TRACE3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROTOCOL, LEVEL_TRACE, fmt, 3, arg0, arg1, arg2)
+#define PROTOCOL_PRINT_TRACE4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROTOCOL, LEVEL_TRACE, fmt, 4, arg0, arg1, arg2, arg3)
+#define PROTOCOL_PRINT_TRACE5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROTOCOL, LEVEL_TRACE, fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define PROTOCOL_PRINT_TRACE6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROTOCOL, LEVEL_TRACE, fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define PROTOCOL_PRINT_TRACE7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROTOCOL, LEVEL_TRACE, fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define PROTOCOL_PRINT_TRACE8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROTOCOL, LEVEL_TRACE, fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+
+
+/* Bluetooth Profile Trace Interfaces */
+#define PROFILE_PRINT_ERROR0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROFILE, LEVEL_ERROR, "!!!"fmt, 0)
+#define PROFILE_PRINT_ERROR1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROFILE, LEVEL_ERROR, "!!!"fmt, 1, arg0)
+#define PROFILE_PRINT_ERROR2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROFILE, LEVEL_ERROR, "!!!"fmt, 2, arg0, arg1)
+#define PROFILE_PRINT_ERROR3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROFILE, LEVEL_ERROR, "!!!"fmt, 3, arg0, arg1, arg2)
+#define PROFILE_PRINT_ERROR4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROFILE, LEVEL_ERROR, "!!!"fmt, 4, arg0, arg1, arg2, arg3)
+#define PROFILE_PRINT_ERROR5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROFILE, LEVEL_ERROR, "!!!"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define PROFILE_PRINT_ERROR6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROFILE, LEVEL_ERROR, "!!!"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define PROFILE_PRINT_ERROR7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROFILE, LEVEL_ERROR, "!!!"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define PROFILE_PRINT_ERROR8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROFILE, LEVEL_ERROR, "!!!"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define PROFILE_PRINT_WARN0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROFILE, LEVEL_WARN, "!!*"fmt, 0)
+#define PROFILE_PRINT_WARN1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROFILE, LEVEL_WARN, "!!*"fmt, 1, arg0)
+#define PROFILE_PRINT_WARN2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROFILE, LEVEL_WARN, "!!*"fmt, 2, arg0, arg1)
+#define PROFILE_PRINT_WARN3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROFILE, LEVEL_WARN, "!!*"fmt, 3, arg0, arg1, arg2)
+#define PROFILE_PRINT_WARN4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROFILE, LEVEL_WARN, "!!*"fmt, 4, arg0, arg1, arg2, arg3)
+#define PROFILE_PRINT_WARN5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROFILE, LEVEL_WARN, "!!*"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define PROFILE_PRINT_WARN6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROFILE, LEVEL_WARN, "!!*"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define PROFILE_PRINT_WARN7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROFILE, LEVEL_WARN, "!!*"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define PROFILE_PRINT_WARN8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROFILE, LEVEL_WARN, "!!*"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define PROFILE_PRINT_INFO0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROFILE, LEVEL_INFO, "!**"fmt, 0)
+#define PROFILE_PRINT_INFO1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROFILE, LEVEL_INFO, "!**"fmt, 1, arg0)
+#define PROFILE_PRINT_INFO2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROFILE, LEVEL_INFO, "!**"fmt, 2, arg0, arg1)
+#define PROFILE_PRINT_INFO3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROFILE, LEVEL_INFO, "!**"fmt, 3, arg0, arg1, arg2)
+#define PROFILE_PRINT_INFO4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROFILE, LEVEL_INFO, "!**"fmt, 4, arg0, arg1, arg2, arg3)
+#define PROFILE_PRINT_INFO5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROFILE, LEVEL_INFO, "!**"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define PROFILE_PRINT_INFO6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROFILE, LEVEL_INFO, "!**"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define PROFILE_PRINT_INFO7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROFILE, LEVEL_INFO, "!**"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define PROFILE_PRINT_INFO8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROFILE, LEVEL_INFO, "!**"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define PROFILE_PRINT_TRACE0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROFILE, LEVEL_TRACE, fmt, 0)
+#define PROFILE_PRINT_TRACE1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROFILE, LEVEL_TRACE, fmt, 1, arg0)
+#define PROFILE_PRINT_TRACE2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROFILE, LEVEL_TRACE, fmt, 2, arg0, arg1)
+#define PROFILE_PRINT_TRACE3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROFILE, LEVEL_TRACE, fmt, 3, arg0, arg1, arg2)
+#define PROFILE_PRINT_TRACE4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROFILE, LEVEL_TRACE, fmt, 4, arg0, arg1, arg2, arg3)
+#define PROFILE_PRINT_TRACE5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROFILE, LEVEL_TRACE, fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define PROFILE_PRINT_TRACE6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROFILE, LEVEL_TRACE, fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define PROFILE_PRINT_TRACE7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROFILE, LEVEL_TRACE, fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define PROFILE_PRINT_TRACE8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROFILE, LEVEL_TRACE, fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+
+
+/**
+ * trace.h
+ *
+ * \name    ZIGBEE_PRINT_TRACE
+ * \brief   ZIGBEE Trace Interfaces.
+ * \anchor  ZIGBEE_PRINT_TRACE
+ */
+/**@{*/
+#define ZIGBEE_PRINT_ERROR0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_ZIGBEE, LEVEL_ERROR, "!!!"fmt, 0)
+#define ZIGBEE_PRINT_ERROR1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_ZIGBEE, LEVEL_ERROR, "!!!"fmt, 1, arg0)
+#define ZIGBEE_PRINT_ERROR2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_ZIGBEE, LEVEL_ERROR, "!!!"fmt, 2, arg0, arg1)
+#define ZIGBEE_PRINT_ERROR3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_ZIGBEE, LEVEL_ERROR, "!!!"fmt, 3, arg0, arg1, arg2)
+#define ZIGBEE_PRINT_ERROR4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_ZIGBEE, LEVEL_ERROR, "!!!"fmt, 4, arg0, arg1, arg2, arg3)
+#define ZIGBEE_PRINT_ERROR5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_ZIGBEE, LEVEL_ERROR, "!!!"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define ZIGBEE_PRINT_ERROR6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_ZIGBEE, LEVEL_ERROR, "!!!"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define ZIGBEE_PRINT_ERROR7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_ZIGBEE, LEVEL_ERROR, "!!!"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define ZIGBEE_PRINT_ERROR8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_ZIGBEE, LEVEL_ERROR, "!!!"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define ZIGBEE_PRINT_WARN0(fmt)     \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_ZIGBEE, LEVEL_WARN, "!!*"fmt, 0)
+#define ZIGBEE_PRINT_WARN1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_ZIGBEE, LEVEL_WARN, "!!*"fmt, 1, arg0)
+#define ZIGBEE_PRINT_WARN2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_ZIGBEE, LEVEL_WARN, "!!*"fmt, 2, arg0, arg1)
+#define ZIGBEE_PRINT_WARN3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_ZIGBEE, LEVEL_WARN, "!!*"fmt, 3, arg0, arg1, arg2)
+#define ZIGBEE_PRINT_WARN4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_ZIGBEE, LEVEL_WARN, "!!*"fmt, 4, arg0, arg1, arg2, arg3)
+#define ZIGBEE_PRINT_WARN5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_ZIGBEE, LEVEL_WARN, "!!*"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define ZIGBEE_PRINT_WARN6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_ZIGBEE, LEVEL_WARN, "!!*"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define ZIGBEE_PRINT_WARN7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_ZIGBEE, LEVEL_WARN, "!!*"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define ZIGBEE_PRINT_WARN8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_ZIGBEE, LEVEL_WARN, "!!*"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define ZIGBEE_PRINT_INFO0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_ZIGBEE, LEVEL_INFO, "!**"fmt, 0)
+#define ZIGBEE_PRINT_INFO1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_ZIGBEE, LEVEL_INFO, "!**"fmt, 1, arg0)
+#define ZIGBEE_PRINT_INFO2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_ZIGBEE, LEVEL_INFO, "!**"fmt, 2, arg0, arg1)
+#define ZIGBEE_PRINT_INFO3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_ZIGBEE, LEVEL_INFO, "!**"fmt, 3, arg0, arg1, arg2)
+#define ZIGBEE_PRINT_INFO4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_ZIGBEE, LEVEL_INFO, "!**"fmt, 4, arg0, arg1, arg2, arg3)
+#define ZIGBEE_PRINT_INFO5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_ZIGBEE, LEVEL_INFO, "!**"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define ZIGBEE_PRINT_INFO6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_ZIGBEE, LEVEL_INFO, "!**"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define ZIGBEE_PRINT_INFO7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_ZIGBEE, LEVEL_INFO, "!**"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define ZIGBEE_PRINT_INFO8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_ZIGBEE, LEVEL_INFO, "!**"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define ZIGBEE_PRINT_TRACE0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_ZIGBEE, LEVEL_TRACE, fmt, 0)
+#define ZIGBEE_PRINT_TRACE1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_ZIGBEE, LEVEL_TRACE, fmt, 1, arg0)
+#define ZIGBEE_PRINT_TRACE2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_ZIGBEE, LEVEL_TRACE, fmt, 2, arg0, arg1)
+#define ZIGBEE_PRINT_TRACE3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_ZIGBEE, LEVEL_TRACE, fmt, 3, arg0, arg1, arg2)
+#define ZIGBEE_PRINT_TRACE4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_ZIGBEE, LEVEL_TRACE, fmt, 4, arg0, arg1, arg2, arg3)
+#define ZIGBEE_PRINT_TRACE5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_ZIGBEE, LEVEL_TRACE, fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define ZIGBEE_PRINT_TRACE6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_ZIGBEE, LEVEL_TRACE, fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define ZIGBEE_PRINT_TRACE7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_ZIGBEE, LEVEL_TRACE, fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define ZIGBEE_PRINT_TRACE8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_ZIGBEE, LEVEL_TRACE, fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+/**@}*/
+
+
+/**
+ * trace.h
+ *
+ * \name    APP_PRINT_TRACE
+ * \brief   Bluetooth APP Trace Interfaces.
+ * \anchor  APP_PRINT_TRACE
+ */
+/**@{*/
+#define APP_PRINT_ERROR0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_APP, LEVEL_ERROR, "!!!"fmt, 0)
+#define APP_PRINT_ERROR1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_APP, LEVEL_ERROR, "!!!"fmt, 1, arg0)
+#define APP_PRINT_ERROR2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_APP, LEVEL_ERROR, "!!!"fmt, 2, arg0, arg1)
+#define APP_PRINT_ERROR3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_APP, LEVEL_ERROR, "!!!"fmt, 3, arg0, arg1, arg2)
+#define APP_PRINT_ERROR4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_APP, LEVEL_ERROR, "!!!"fmt, 4, arg0, arg1, arg2, arg3)
+#define APP_PRINT_ERROR5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_APP, LEVEL_ERROR, "!!!"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define APP_PRINT_ERROR6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_APP, LEVEL_ERROR, "!!!"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define APP_PRINT_ERROR7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_APP, LEVEL_ERROR, "!!!"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define APP_PRINT_ERROR8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_APP, LEVEL_ERROR, "!!!"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define APP_PRINT_WARN0(fmt)     \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_APP, LEVEL_WARN, "!!*"fmt, 0)
+#define APP_PRINT_WARN1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_APP, LEVEL_WARN, "!!*"fmt, 1, arg0)
+#define APP_PRINT_WARN2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_APP, LEVEL_WARN, "!!*"fmt, 2, arg0, arg1)
+#define APP_PRINT_WARN3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_APP, LEVEL_WARN, "!!*"fmt, 3, arg0, arg1, arg2)
+#define APP_PRINT_WARN4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_APP, LEVEL_WARN, "!!*"fmt, 4, arg0, arg1, arg2, arg3)
+#define APP_PRINT_WARN5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_APP, LEVEL_WARN, "!!*"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define APP_PRINT_WARN6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_APP, LEVEL_WARN, "!!*"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define APP_PRINT_WARN7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_APP, LEVEL_WARN, "!!*"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define APP_PRINT_WARN8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_APP, LEVEL_WARN, "!!*"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define APP_PRINT_INFO0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_APP, LEVEL_INFO, "!**"fmt, 0)
+#define APP_PRINT_INFO1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_APP, LEVEL_INFO, "!**"fmt, 1, arg0)
+#define APP_PRINT_INFO2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_APP, LEVEL_INFO, "!**"fmt, 2, arg0, arg1)
+#define APP_PRINT_INFO3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_APP, LEVEL_INFO, "!**"fmt, 3, arg0, arg1, arg2)
+#define APP_PRINT_INFO4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_APP, LEVEL_INFO, "!**"fmt, 4, arg0, arg1, arg2, arg3)
+#define APP_PRINT_INFO5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_APP, LEVEL_INFO, "!**"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define APP_PRINT_INFO6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_APP, LEVEL_INFO, "!**"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define APP_PRINT_INFO7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_APP, LEVEL_INFO, "!**"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define APP_PRINT_INFO8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_APP, LEVEL_INFO, "!**"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define APP_PRINT_TRACE0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_APP, LEVEL_TRACE, fmt, 0)
+#define APP_PRINT_TRACE1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_APP, LEVEL_TRACE, fmt, 1, arg0)
+#define APP_PRINT_TRACE2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_APP, LEVEL_TRACE, fmt, 2, arg0, arg1)
+#define APP_PRINT_TRACE3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_APP, LEVEL_TRACE, fmt, 3, arg0, arg1, arg2)
+#define APP_PRINT_TRACE4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_APP, LEVEL_TRACE, fmt, 4, arg0, arg1, arg2, arg3)
+#define APP_PRINT_TRACE5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_APP, LEVEL_TRACE, fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define APP_PRINT_TRACE6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_APP, LEVEL_TRACE, fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define APP_PRINT_TRACE7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_APP, LEVEL_TRACE, fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define APP_PRINT_TRACE8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_APP, LEVEL_TRACE, fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+/**@}*/
+
+
+/* PHY Trace Interfaces */
+#define PHY_PRINT_ERROR0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PHY, LEVEL_ERROR, "!!!"fmt, 0)
+#define PHY_PRINT_ERROR1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PHY, LEVEL_ERROR, "!!!"fmt, 1, arg0)
+#define PHY_PRINT_ERROR2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PHY, LEVEL_ERROR, "!!!"fmt, 2, arg0, arg1)
+#define PHY_PRINT_ERROR3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PHY, LEVEL_ERROR, "!!!"fmt, 3, arg0, arg1, arg2)
+#define PHY_PRINT_ERROR4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PHY, LEVEL_ERROR, "!!!"fmt, 4, arg0, arg1, arg2, arg3)
+#define PHY_PRINT_ERROR5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PHY, LEVEL_ERROR, "!!!"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define PHY_PRINT_ERROR6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PHY, LEVEL_ERROR, "!!!"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define PHY_PRINT_ERROR7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PHY, LEVEL_ERROR, "!!!"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define PHY_PRINT_ERROR8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PHY, LEVEL_ERROR, "!!!"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define PHY_PRINT_WARN0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PHY, LEVEL_WARN, "!!*"fmt, 0)
+#define PHY_PRINT_WARN1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PHY, LEVEL_WARN, "!!*"fmt, 1, arg0)
+#define PHY_PRINT_WARN2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PHY, LEVEL_WARN, "!!*"fmt, 2, arg0, arg1)
+#define PHY_PRINT_WARN3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PHY, LEVEL_WARN, "!!*"fmt, 3, arg0, arg1, arg2)
+#define PHY_PRINT_WARN4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PHY, LEVEL_WARN, "!!*"fmt, 4, arg0, arg1, arg2, arg3)
+#define PHY_PRINT_WARN5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PHY, LEVEL_WARN, "!!*"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define PHY_PRINT_WARN6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PHY, LEVEL_WARN, "!!*"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define PHY_PRINT_WARN7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PHY, LEVEL_WARN, "!!*"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define PHY_PRINT_WARN8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PHY, LEVEL_WARN, "!!*"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define PHY_PRINT_INFO0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PHY, LEVEL_INFO, "!**"fmt, 0)
+#define PHY_PRINT_INFO1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PHY, LEVEL_INFO, "!**"fmt, 1, arg0)
+#define PHY_PRINT_INFO2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PHY, LEVEL_INFO, "!**"fmt, 2, arg0, arg1)
+#define PHY_PRINT_INFO3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PHY, LEVEL_INFO, "!**"fmt, 3, arg0, arg1, arg2)
+#define PHY_PRINT_INFO4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PHY, LEVEL_INFO, "!**"fmt, 4, arg0, arg1, arg2, arg3)
+#define PHY_PRINT_INFO5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PHY, LEVEL_INFO, "!**"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define PHY_PRINT_INFO6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PHY, LEVEL_INFO, "!**"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define PHY_PRINT_INFO7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PHY, LEVEL_INFO, "!**"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define PHY_PRINT_INFO8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PHY, LEVEL_INFO, "!**"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define PHY_PRINT_TRACE0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PHY, LEVEL_TRACE, fmt, 0)
+#define PHY_PRINT_TRACE1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PHY, LEVEL_TRACE, fmt, 1, arg0)
+#define PHY_PRINT_TRACE2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PHY, LEVEL_TRACE, fmt, 2, arg0, arg1)
+#define PHY_PRINT_TRACE3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PHY, LEVEL_TRACE, fmt, 3, arg0, arg1, arg2)
+#define PHY_PRINT_TRACE4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PHY, LEVEL_TRACE, fmt, 4, arg0, arg1, arg2, arg3)
+#define PHY_PRINT_TRACE5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PHY, LEVEL_TRACE, fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define PHY_PRINT_TRACE6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PHY, LEVEL_TRACE, fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define PHY_PRINT_TRACE7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PHY, LEVEL_TRACE, fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define PHY_PRINT_TRACE8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PHY, LEVEL_TRACE, fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define PHY_PRINT_TRACE17(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8, arg9, arg10, arg11, arg12, arg13, arg14, arg15, arg16)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PHY, LEVEL_TRACE, fmt, 17, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8, arg9, arg10, arg11, arg12, arg13, arg14, arg15, arg16)
+#define PHY_PRINT_TRACE18(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8, arg9, arg10, arg11, arg12, arg13, arg14, arg15, arg16, arg17)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PHY, LEVEL_TRACE, fmt, 18, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8, arg9, arg10, arg11, arg12, arg13, arg14, arg15, arg16, arg17)
+
+
+/* AES Trace Interfaces */
+#define AES_PRINT_ERROR0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_AES, LEVEL_ERROR, "!!!"fmt, 0)
+#define AES_PRINT_ERROR1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_AES, LEVEL_ERROR, "!!!"fmt, 1, arg0)
+#define AES_PRINT_ERROR2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_AES, LEVEL_ERROR, "!!!"fmt, 2, arg0, arg1)
+#define AES_PRINT_ERROR3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_AES, LEVEL_ERROR, "!!!"fmt, 3, arg0, arg1, arg2)
+#define AES_PRINT_ERROR4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_AES, LEVEL_ERROR, "!!!"fmt, 4, arg0, arg1, arg2, arg3)
+#define AES_PRINT_WARN0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_AES, LEVEL_WARN, "!!*"fmt, 0)
+#define AES_PRINT_WARN1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_AES, LEVEL_WARN, "!!*"fmt, 1, arg0)
+#define AES_PRINT_WARN2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_AES, LEVEL_WARN, "!!*"fmt, 2, arg0, arg1)
+#define AES_PRINT_WARN3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_AES, LEVEL_WARN, "!!*"fmt, 3, arg0, arg1, arg2)
+#define AES_PRINT_WARN4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_AES, LEVEL_WARN, "!!*"fmt, 4, arg0, arg1, arg2, arg3)
+#define AES_PRINT_INFO0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_AES, LEVEL_INFO, "!**"fmt, 0)
+#define AES_PRINT_INFO1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_AES, LEVEL_INFO, "!**"fmt, 1, arg0)
+#define AES_PRINT_INFO2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_AES, LEVEL_INFO, "!**"fmt, 2, arg0, arg1)
+#define AES_PRINT_INFO3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_AES, LEVEL_INFO, "!**"fmt, 3, arg0, arg1, arg2)
+#define AES_PRINT_INFO4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_AES, LEVEL_INFO, "!**"fmt, 4, arg0, arg1, arg2, arg3)
+
+/* Power Manager Trace Interfaces */
+#define PM_PRINT_ERROR0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PM, LEVEL_ERROR, "!!!"fmt, 0)
+#define PM_PRINT_ERROR1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PM, LEVEL_ERROR, "!!!"fmt, 1, arg0)
+#define PM_PRINT_ERROR2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PM, LEVEL_ERROR, "!!!"fmt, 2, arg0, arg1)
+#define PM_PRINT_ERROR3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PM, LEVEL_ERROR, "!!!"fmt, 3, arg0, arg1, arg2)
+#define PM_PRINT_ERROR4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PM, LEVEL_ERROR, "!!!"fmt, 4, arg0, arg1, arg2, arg3)
+#define PM_PRINT_WARN0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PM, LEVEL_WARN, "!!*"fmt, 0)
+#define PM_PRINT_WARN1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PM, LEVEL_WARN, "!!*"fmt, 1, arg0)
+#define PM_PRINT_WARN2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PM, LEVEL_WARN, "!!*"fmt, 2, arg0, arg1)
+#define PM_PRINT_WARN3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PM, LEVEL_WARN, "!!*"fmt, 3, arg0, arg1, arg2)
+#define PM_PRINT_WARN4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PM, LEVEL_WARN, "!!*"fmt, 4, arg0, arg1, arg2, arg3)
+#define PM_PRINT_INFO0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PM, LEVEL_INFO, "!**"fmt, 0)
+#define PM_PRINT_INFO1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PM, LEVEL_INFO, "!**"fmt, 1, arg0)
+#define PM_PRINT_INFO2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PM, LEVEL_INFO, "!**"fmt, 2, arg0, arg1)
+#define PM_PRINT_INFO3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PM, LEVEL_INFO, "!**"fmt, 3, arg0, arg1, arg2)
+#define PM_PRINT_INFO4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PM, LEVEL_INFO, "!**"fmt, 4, arg0, arg1, arg2, arg3)
+#define PM_PRINT_INFO5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PM, LEVEL_INFO, "!**"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define PM_PRINT_INFO6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PM, LEVEL_INFO, "!**"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define PM_PRINT_INFO7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PM, LEVEL_INFO, "!**"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define PM_PRINT_INFO8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PM, LEVEL_INFO, "!**"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define PM_PRINT_INFO9(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PM, LEVEL_INFO, "!**"fmt, 9, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8)
+#define PM_PRINT_INFO10(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8, arg9)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PM, LEVEL_INFO, "!**"fmt, 10, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8, arg9)
+#define PM_PRINT_INFO13(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8, arg9, arg10, arg11, arg12)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PM, LEVEL_INFO, "!**"fmt, 13, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8, arg9, arg10, arg11, arg12)
+#define PM_PRINT_INFO16(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8, arg9, arg10, arg11, arg12, arg13, arg14, arg15)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PM, LEVEL_INFO, "!**"fmt, 16, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8, arg9, arg10, arg11, arg12, arg13, arg14, arg15)
+
+/* Boot Trace Interfaces */
+#define BOOT_PRINT_ERROR0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BOOT, LEVEL_ERROR, "!!!"fmt, 0)
+#define BOOT_PRINT_ERROR1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BOOT, LEVEL_ERROR, "!!!"fmt, 1, arg0)
+#define BOOT_PRINT_ERROR2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BOOT, LEVEL_ERROR, "!!!"fmt, 2, arg0, arg1)
+#define BOOT_PRINT_ERROR3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BOOT, LEVEL_ERROR, "!!!"fmt, 3, arg0, arg1, arg2)
+#define BOOT_PRINT_ERROR4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BOOT, LEVEL_ERROR, "!!!"fmt, 4, arg0, arg1, arg2, arg3)
+#define BOOT_PRINT_WARN0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BOOT, LEVEL_WARN, "!!*"fmt, 0)
+#define BOOT_PRINT_WARN1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BOOT, LEVEL_WARN, "!!*"fmt, 1, arg0)
+#define BOOT_PRINT_WARN2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BOOT, LEVEL_WARN, "!!*"fmt, 2, arg0, arg1)
+#define BOOT_PRINT_WARN3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BOOT, LEVEL_WARN, "!!*"fmt, 3, arg0, arg1, arg2)
+#define BOOT_PRINT_WARN4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BOOT, LEVEL_WARN, "!!*"fmt, 4, arg0, arg1, arg2, arg3)
+#define BOOT_PRINT_INFO0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BOOT, LEVEL_INFO, "!**"fmt, 0)
+#define BOOT_PRINT_INFO1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BOOT, LEVEL_INFO, "!**"fmt, 1, arg0)
+#define BOOT_PRINT_INFO2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BOOT, LEVEL_INFO, "!**"fmt, 2, arg0, arg1)
+#define BOOT_PRINT_INFO3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BOOT, LEVEL_INFO, "!**"fmt, 3, arg0, arg1, arg2)
+#define BOOT_PRINT_INFO4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BOOT, LEVEL_INFO, "!**"fmt, 4, arg0, arg1, arg2, arg3)
+
+
+/* Bluetooth OTA/DFU Trace Interfaces */
+#define DFU_PRINT_ERROR0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DFU, LEVEL_ERROR, "!!!"fmt, 0)
+#define DFU_PRINT_ERROR1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DFU, LEVEL_ERROR, "!!!"fmt, 1, arg0)
+#define DFU_PRINT_ERROR2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DFU, LEVEL_ERROR, "!!!"fmt, 2, arg0, arg1)
+#define DFU_PRINT_ERROR3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DFU, LEVEL_ERROR, "!!!"fmt, 3, arg0, arg1, arg2)
+#define DFU_PRINT_ERROR4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DFU, LEVEL_ERROR, "!!!"fmt, 4, arg0, arg1, arg2, arg3)
+#define DFU_PRINT_ERROR5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DFU, LEVEL_ERROR, "!!!"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define DFU_PRINT_ERROR6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DFU, LEVEL_ERROR, "!!!"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define DFU_PRINT_ERROR7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DFU, LEVEL_ERROR, "!!!"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define DFU_PRINT_ERROR8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DFU, LEVEL_ERROR, "!!!"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define DFU_PRINT_WARN0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DFU, LEVEL_WARN, "!!*"fmt, 0)
+#define DFU_PRINT_WARN1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DFU, LEVEL_WARN, "!!*"fmt, 1, arg0)
+#define DFU_PRINT_WARN2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DFU, LEVEL_WARN, "!!*"fmt, 2, arg0, arg1)
+#define DFU_PRINT_WARN3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DFU, LEVEL_WARN, "!!*"fmt, 3, arg0, arg1, arg2)
+#define DFU_PRINT_WARN4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DFU, LEVEL_WARN, "!!*"fmt, 4, arg0, arg1, arg2, arg3)
+#define DFU_PRINT_WARN5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DFU, LEVEL_WARN, "!!*"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define DFU_PRINT_WARN6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DFU, LEVEL_WARN, "!!*"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define DFU_PRINT_WARN7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DFU, LEVEL_WARN, "!!*"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define DFU_PRINT_WARN8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DFU, LEVEL_WARN, "!!*"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define DFU_PRINT_INFO0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DFU, LEVEL_INFO, "!**"fmt, 0)
+#define DFU_PRINT_INFO1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DFU, LEVEL_INFO, "!**"fmt, 1, arg0)
+#define DFU_PRINT_INFO2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DFU, LEVEL_INFO, "!**"fmt, 2, arg0, arg1)
+#define DFU_PRINT_INFO3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DFU, LEVEL_INFO, "!**"fmt, 3, arg0, arg1, arg2)
+#define DFU_PRINT_INFO4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DFU, LEVEL_INFO, "!**"fmt, 4, arg0, arg1, arg2, arg3)
+#define DFU_PRINT_INFO5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DFU, LEVEL_INFO, "!**"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define DFU_PRINT_INFO6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DFU, LEVEL_INFO, "!**"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define DFU_PRINT_INFO7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DFU, LEVEL_INFO, "!**"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define DFU_PRINT_INFO8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DFU, LEVEL_INFO, "!**"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define DFU_PRINT_TRACE0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DFU, LEVEL_TRACE, fmt, 0)
+#define DFU_PRINT_TRACE1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DFU, LEVEL_TRACE, fmt, 1, arg0)
+#define DFU_PRINT_TRACE2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DFU, LEVEL_TRACE, fmt, 2, arg0, arg1)
+#define DFU_PRINT_TRACE3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DFU, LEVEL_TRACE, fmt, 3, arg0, arg1, arg2)
+#define DFU_PRINT_TRACE4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DFU, LEVEL_TRACE, fmt, 4, arg0, arg1, arg2, arg3)
+#define DFU_PRINT_TRACE5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DFU, LEVEL_TRACE, fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define DFU_PRINT_TRACE6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DFU, LEVEL_TRACE, fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define DFU_PRINT_TRACE7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DFU, LEVEL_TRACE, fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define DFU_PRINT_TRACE8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DFU, LEVEL_TRACE, fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+
+
+/* Bluetooth FLASH/CACHE Trace Interfaces */
+#define FLASH_PRINT_ERROR0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_FLASH, LEVEL_ERROR, "!!!"fmt, 0)
+#define FLASH_PRINT_ERROR1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_FLASH, LEVEL_ERROR, "!!!"fmt, 1, arg0)
+#define FLASH_PRINT_ERROR2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_FLASH, LEVEL_ERROR, "!!!"fmt, 2, arg0, arg1)
+#define FLASH_PRINT_ERROR3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_FLASH, LEVEL_ERROR, "!!!"fmt, 3, arg0, arg1, arg2)
+#define FLASH_PRINT_ERROR4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_FLASH, LEVEL_ERROR, "!!!"fmt, 4, arg0, arg1, arg2, arg3)
+#define FLASH_PRINT_ERROR5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_FLASH, LEVEL_ERROR, "!!!"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define FLASH_PRINT_ERROR6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_FLASH, LEVEL_ERROR, "!!!"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define FLASH_PRINT_ERROR7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_FLASH, LEVEL_ERROR, "!!!"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define FLASH_PRINT_ERROR8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_FLASH, LEVEL_ERROR, "!!!"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define FLASH_PRINT_WARN0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_FLASH, LEVEL_WARN, "!!*"fmt, 0)
+#define FLASH_PRINT_WARN1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_FLASH, LEVEL_WARN, "!!*"fmt, 1, arg0)
+#define FLASH_PRINT_WARN2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_FLASH, LEVEL_WARN, "!!*"fmt, 2, arg0, arg1)
+#define FLASH_PRINT_WARN3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_FLASH, LEVEL_WARN, "!!*"fmt, 3, arg0, arg1, arg2)
+#define FLASH_PRINT_WARN4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_FLASH, LEVEL_WARN, "!!*"fmt, 4, arg0, arg1, arg2, arg3)
+#define FLASH_PRINT_WARN5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_FLASH, LEVEL_WARN, "!!*"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define FLASH_PRINT_WARN6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_FLASH, LEVEL_WARN, "!!*"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define FLASH_PRINT_WARN7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_FLASH, LEVEL_WARN, "!!*"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define FLASH_PRINT_WARN8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_FLASH, LEVEL_WARN, "!!*"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define FLASH_PRINT_INFO0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_FLASH, LEVEL_INFO, "!**"fmt, 0)
+#define FLASH_PRINT_INFO1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_FLASH, LEVEL_INFO, "!**"fmt, 1, arg0)
+#define FLASH_PRINT_INFO2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_FLASH, LEVEL_INFO, "!**"fmt, 2, arg0, arg1)
+#define FLASH_PRINT_INFO3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_FLASH, LEVEL_INFO, "!**"fmt, 3, arg0, arg1, arg2)
+#define FLASH_PRINT_INFO4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_FLASH, LEVEL_INFO, "!**"fmt, 4, arg0, arg1, arg2, arg3)
+#define FLASH_PRINT_INFO5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_FLASH, LEVEL_INFO, "!**"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define FLASH_PRINT_INFO6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_FLASH, LEVEL_INFO, "!**"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define FLASH_PRINT_INFO7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_FLASH, LEVEL_INFO, "!**"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define FLASH_PRINT_INFO8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_FLASH, LEVEL_INFO, "!**"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define FLASH_PRINT_TRACE0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_FLASH, LEVEL_TRACE, fmt, 0)
+#define FLASH_PRINT_TRACE1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_FLASH, LEVEL_TRACE, fmt, 1, arg0)
+#define FLASH_PRINT_TRACE2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_FLASH, LEVEL_TRACE, fmt, 2, arg0, arg1)
+#define FLASH_PRINT_TRACE3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_FLASH, LEVEL_TRACE, fmt, 3, arg0, arg1, arg2)
+#define FLASH_PRINT_TRACE4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_FLASH, LEVEL_TRACE, fmt, 4, arg0, arg1, arg2, arg3)
+#define FLASH_PRINT_TRACE5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_FLASH, LEVEL_TRACE, fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define FLASH_PRINT_TRACE6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_FLASH, LEVEL_TRACE, fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define FLASH_PRINT_TRACE7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_FLASH, LEVEL_TRACE, fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define FLASH_PRINT_TRACE8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_FLASH, LEVEL_TRACE, fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+
+/** End of TRACE_Exported_Macros
+  * @}
+  */
+
+/** End of TRACE
+  * @}
+  */
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _TRACE_H_ */
diff --git a/bee/logging/inc/rtl87x2g/trace.h b/bee/logging/inc/rtl87x2g/trace.h
new file mode 100644
index 00000000..ee1b95e4
--- /dev/null
+++ b/bee/logging/inc/rtl87x2g/trace.h
@@ -0,0 +1,3906 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _TRACE_H_
+#define _TRACE_H_
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/**
+ * \defgroup    TRACE       Trace
+ *
+ * \brief       Defines debug trace macros for each module.
+ *
+ */
+
+
+/* Log Section Definition */
+#define TRACE_DATA __attribute__((section(".TRACE"))) __attribute__((aligned(4))) __attribute__((used))
+
+/**
+ * trace.h
+ *
+ * \name    TRACE_LEVEL
+ * \brief   Log Level Definition.
+ * \anchor  TRACE_LEVEL
+ */
+/**
+ * \ingroup TRACE
+ */
+/**@{*/
+#define LEVEL_OFF       (-1)
+#define LEVEL_ERROR     (0)
+#define LEVEL_WARN      (1)
+#define LEVEL_INFO      (2)
+#define LEVEL_TRACE     (3)
+#define LEVEL_NUM       (4)
+/**@}*/
+
+/*
+ * DBG_LEVEL is used to control the log printed by DBG_BUFFER(), DBG_INDEX() and DBG_TEXT().
+ * LEVEL_OFF   : Print None
+ * LEVEL_ERROR : Print ERROR
+ * LEVEL_WARN  : Print ERROR, WARN
+ * LEVEL_INFO  : Print ERROR, WARN, INFO
+ * LEVEL_TRACE : Print ERROR, WARN, INFO, TRACE
+ */
+#define DBG_LEVEL               LEVEL_TRACE
+
+/* Log type definition */
+typedef enum
+{
+    TYPE_UPPERSTACK_RESET       = 0,
+    TYPE_UPPERSTACK_FORMAT      = 1,
+    TYPE_UPPERSTACK_MESSAGE     = 2,
+    TYPE_UPPERSTACK_BINARY      = 3,
+    TYPE_UPPERSTACK_STRING      = 4,
+    TYPE_UPPERSTACK_BDADDR1     = 5,
+    TYPE_UPPERSTACK_BDADDR2     = 6,
+    TYPE_UPPERSTACK_RAMDATA1    = 7,
+    TYPE_UPPERSTACK_RAMDATA2    = 8,
+    TYPE_UPPERSTACK_RAMDATA3    = 9,
+    TYPE_UPPERSTACK_RAMDATA4    = 10,
+    TYPE_UPPERSTACK_RAMDATA5    = 11,
+    TYPE_UPPERSTACK_RAMDATA6    = 12,
+    TYPE_UPPERSTACK_RAMDATA7    = 13,
+    TYPE_UPPERSTACK_RAMDATA8    = 14,
+
+    TYPE_PLATFORM_DBG_DIRECT    = 16,
+
+    TYPE_RTL8752H               = 37,
+    TYPE_RTL87X2G               = 38,
+} T_LOG_TYPE;
+
+/* Log type current ic used */
+#define LOG_TYPE                (TYPE_RTL87X2G)
+
+
+/* Log subtype definition */
+typedef enum
+{
+    SUBTYPE_DIRECT                  = 0x00,
+
+    SUBTYPE_FORMAT                  = 0x10,
+    SUBTYPE_DOWN_MESSAGE            = 0x11,
+    SUBTYPE_UP_MESSAGE              = 0x12,
+
+    SUBTYPE_DOWN_SNOOP              = 0x20,
+    SUBTYPE_UP_SNOOP                = 0x28,
+
+    SUBTYPE_BDADDR                  = 0x30,
+
+    SUBTYPE_STRING                  = 0x40,
+
+    SUBTYPE_BINARY                  = 0x50,
+
+    SUBTYPE_INDEX                   = 0x60,
+    SUBTYPE_STACK_INDEX             = 0x61,
+
+    SUBTYPE_TEXT                    = 0x70,
+} T_LOG_SUBTYPE;
+
+/**
+ * trace.h
+ *
+ * \name    MODULE_ID
+ * \brief   Module ID definition.
+ * \anchor  MODULE_ID
+ */
+/**
+ * \ingroup TRACE
+ */
+/**@{*/
+typedef enum
+{
+    /* platform modules */
+    MODULE_PATCH                    = 0,
+    MODULE_OS                       = 1,
+    MODULE_OSIF                     = 2,
+    MODULE_BOOT                     = 3,
+    MODULE_PM                       = 4,
+    MODULE_AES                      = 5,
+    MODULE_FS                       = 6,
+    MODULE_DEBUG                    = 7,
+    MODULE_PHY                      = 8,
+    MODULE_DVFS                     = 9,
+
+    /* device modules */
+    MODULE_DM                       = 12,
+    MODULE_BTM                      = 13,
+    MODULE_AUDIO                    = 14,
+    MODULE_REMOTE                   = 15,
+    MODULE_ENGAGE                   = 17,
+    MODULE_SYS                      = 18,
+    MODULE_UART                     = 22,
+    MODULE_FLASH                    = 23,
+    MODULE_CODEC                    = 24,
+    MODULE_DIPC                     = 25,
+    MODULE_MMI                      = 26,
+    MODULE_USB                      = 27,
+    MODULE_SDIO                     = 28,
+    MODULE_CHARGER                  = 29,
+    MODULE_DSP                      = 30,
+    MODULE_CONSOLE                  = 31,
+    MODULE_CTC                      = 32,
+    MODULE_IO                       = 33,
+    MODULE_SHM                      = 34,
+    MODULE_LOADER                   = 35,
+
+    /* stack modules */
+    MODULE_THREAD                   = 44,
+    MODULE_MATTER                   = 45,
+    MODULE_ZIGBEE                   = 47,
+    MODULE_APP                      = 48,
+    MODULE_DFU                      = 49,
+    MODULE_RFCOMM                   = 50,
+    MODULE_PROFILE                  = 51,
+    MODULE_PROTOCOL                 = 52,
+    MODULE_GAP                      = 53,
+    MODULE_BTE                      = 54,
+    MODULE_BTIF                     = 55,
+    MODULE_GATT                     = 56,
+    MODULE_SMP                      = 57,
+    MODULE_SDP                      = 58,
+    MODULE_L2CAP                    = 59,
+    MODULE_HCI                      = 60,
+    MODULE_SNOOP                    = 61,
+    MODULE_UPPERSTACK               = 62,
+    MODULE_LOWERSTACK               = 63,
+
+    MODULE_NUM                      = 64
+} T_MODULE_ID;
+/**@}*/
+#define LOWERSTACK_LOGBUFFER_SIGNATURE      249
+#define NEW_LOWERSTACK_LOGBUFFER_SIGNATURE  252
+
+#define LOG_FORMAT_VERSION              0
+#define LOG_MESSAGE_SYNC_CODE           0x7E
+#define MAX_LOG_MESSAGE_LEN             252
+#define MAX_ARGUMENT_SIZE               20
+
+#define GET_TYPE(info)                  (uint8_t)((info) >> 24)
+#define GET_SUBTYPE(info)               (uint8_t)((info) >> 16)
+#define GET_MODULE(info)                (uint8_t)((info) >> 8)
+#define GET_LEVEL(info)                 (uint8_t)((info) >> 0)
+#define GET_MODULE_LOWSTACK(str_index)  (uint8_t)((str_index) >> 16)
+
+/**
+ * trace.h
+ *
+ * \name    MODULE_BITMAP
+ * \brief   Module bitmap definition.
+ * \anchor  MODULE_BITMAP
+ */
+/**
+ * \ingroup TRACE
+ */
+/**@{*/
+#define MODULE_BIT_PATCH            ((uint64_t)1 << MODULE_PATCH     )
+#define MODULE_BIT_OS               ((uint64_t)1 << MODULE_OS        )
+#define MODULE_BIT_OSIF             ((uint64_t)1 << MODULE_OSIF      )
+#define MODULE_BIT_BOOT             ((uint64_t)1 << MODULE_BOOT      )
+#define MODULE_BIT_PM               ((uint64_t)1 << MODULE_PM        )
+#define MODULE_BIT_AES              ((uint64_t)1 << MODULE_AES       )
+#define MODULE_BIT_FS               ((uint64_t)1 << MODULE_FS        )
+#define MODULE_BIT_DEBUG            ((uint64_t)1 << MODULE_DEBUG     )
+#define MODULE_BIT_PHY              ((uint64_t)1 << MODULE_PHY       )
+#define MODULE_BIT_DVFS             ((uint64_t)1 << MODULE_DVFS      )
+
+#define MODULE_BIT_DM               ((uint64_t)1 << MODULE_DM        )
+#define MODULE_BIT_BTM              ((uint64_t)1 << MODULE_BTM       )
+#define MODULE_BIT_AUDIO            ((uint64_t)1 << MODULE_AUDIO     )
+#define MODULE_BIT_REMOTE           ((uint64_t)1 << MODULE_REMOTE    )
+#define MODULE_BIT_ENGAGE           ((uint64_t)1 << MODULE_ENGAGE    )
+#define MODULE_BIT_SYS              ((uint64_t)1 << MODULE_SYS       )
+#define MODULE_BIT_UART             ((uint64_t)1 << MODULE_UART      )
+#define MODULE_BIT_FLASH            ((uint64_t)1 << MODULE_FLASH     )
+#define MODULE_BIT_CODEC            ((uint64_t)1 << MODULE_CODEC     )
+#define MODULE_BIT_DIPC             ((uint64_t)1 << MODULE_DIPC      )
+#define MODULE_BIT_MMI              ((uint64_t)1 << MODULE_MMI       )
+#define MODULE_BIT_USB              ((uint64_t)1 << MODULE_USB       )
+#define MODULE_BIT_SDIO             ((uint64_t)1 << MODULE_SDIO      )
+#define MODULE_BIT_CHARGER          ((uint64_t)1 << MODULE_CHARGER   )
+#define MODULE_BIT_DSP              ((uint64_t)1 << MODULE_DSP       )
+#define MODULE_BIT_CONSOLE          ((uint64_t)1 << MODULE_CONSOLE   )
+#define MODULE_BIT_CTC              ((uint64_t)1 << MODULE_CTC       )
+#define MODULE_BIT_IO               ((uint64_t)1 << MODULE_IO        )
+#define MODULE_BIT_SHM              ((uint64_t)1 << MODULE_SHM       )
+#define MODULE_BIT_LOADER           ((uint64_t)1 << MODULE_LOADER    )
+
+#define MODULE_BIT_THREAD           ((uint64_t)1 << MODULE_THREAD    )
+#define MODULE_BIT_MATTER           ((uint64_t)1 << MODULE_MATTER    )
+#define MODULE_BIT_ZIGBEE           ((uint64_t)1 << MODULE_ZIGBEE    )
+#define MODULE_BIT_APP              ((uint64_t)1 << MODULE_APP       )
+#define MODULE_BIT_DFU              ((uint64_t)1 << MODULE_DFU       )
+#define MODULE_BIT_RFCOMM           ((uint64_t)1 << MODULE_RFCOMM    )
+#define MODULE_BIT_PROFILE          ((uint64_t)1 << MODULE_PROFILE   )
+#define MODULE_BIT_PROTOCOL         ((uint64_t)1 << MODULE_PROTOCOL  )
+#define MODULE_BIT_GAP              ((uint64_t)1 << MODULE_GAP       )
+#define MODULE_BIT_BTIF             ((uint64_t)1 << MODULE_BTIF      )
+#define MODULE_BIT_GATT             ((uint64_t)1 << MODULE_GATT      )
+#define MODULE_BIT_SMP              ((uint64_t)1 << MODULE_SMP       )
+#define MODULE_BIT_SDP              ((uint64_t)1 << MODULE_SDP       )
+#define MODULE_BIT_L2CAP            ((uint64_t)1 << MODULE_L2CAP     )
+#define MODULE_BIT_HCI              ((uint64_t)1 << MODULE_HCI       )
+#define MODULE_BIT_SNOOP            ((uint64_t)1 << MODULE_SNOOP     )
+#define MODULE_BIT_LOWERSTACK       ((uint64_t)1 << MODULE_LOWERSTACK)
+#define MODULE_BIT_UPPERSTACK       ((uint64_t)1 << MODULE_UPPERSTACK)
+/**@}*/
+#define LOG_BINARY_MASK             BIT0
+#define LOG_ASCII_MASK              BIT1
+
+#define LOG_OUTPUT_UART_MASK        BIT0
+#define LOG_OUTPUT_FLASH_MASK       BIT1
+#define LOG_OUTPUT_VENDOR_MASK      BIT2
+
+void fill_log_data(uint8_t *l_msg, uint32_t info);
+/* Internal function that is used by internal macro DBG_DIRECT. */
+extern void (*log_direct)(uint32_t info, const char *fmt, ...);
+
+/* Internal function that is used by internal macro DBG_LOWERSTACK. */
+void LogBufferLowerStack(uint32_t control, uint16_t str_index, uint8_t param_num, ...);
+
+/* Internal function that is used by internal macro DBG_LOWERSTACKDATA. */
+void LogBufferLowerStackData(uint32_t control, uint16_t str_index, uint16_t length, uint8_t *p_str);
+
+/* Internal function that is used by internal macro DBG_BUFFER. */
+void log_buffer(uint32_t info, uint32_t str_index, uint32_t param_num, ...);
+
+void log_buffer_lowerstack(uint32_t str_index, uint32_t param_num, ...);
+
+/* Internal function that is used by internal macro DBG_INDEX. */
+#define log_index log_buffer
+
+/* Internal function that is used by internal macro DBG_TEXT. */
+void log_text(uint32_t info, const char *fmt, ...);
+
+/* Internal function that is used by internal macro DBG_SNOOP. */
+extern void (*log_snoop)(uint32_t info, uint16_t length, uint8_t *p_snoop);
+
+/* Internal function that is used by public macro TRACE_BDADDR. */
+const char *trace_bdaddr(uint32_t info, char *bd_addr);
+
+/* Internal function that is used by public macro TRACE_STRING. */
+extern const char *(*trace_string)(uint32_t info, uint16_t length, char *p_data);
+
+/* Internal function that is used by public macro TRACE_BINARY. */
+const char *trace_binary(uint32_t info, uint16_t length, uint8_t *p_data);
+
+#define COMBINE_TRACE_INFO(type, subtype, module, level)  (uint32_t)(((type)<<24) | ((subtype)<<16) | ((module)<<8) | (level))
+
+/* Internal macro that is wrapped by internal macro DBG_BUFFER. */
+#define DBG_BUFFER_INTERNAL(type, sub_type, module, level, fmt, param_num, ...) do {\
+        static const char format[] TRACE_DATA = fmt;\
+        log_buffer(COMBINE_TRACE_INFO(type, sub_type, module, level), (uint32_t)format, param_num, ##__VA_ARGS__);\
+    } while (0)
+
+#if (DBG_LEVEL >= LEVEL_ERROR)
+#define DBG_BUFFER_LEVEL_ERROR(type, sub_type, module, fmt, param_num, ...) do {\
+        DBG_BUFFER_INTERNAL(type, sub_type, module, LEVEL_ERROR, fmt, param_num, ##__VA_ARGS__);\
+    } while (0)
+#define DBG_INDEX_LEVEL_ERROR(type, sub_type, module, fmt, param_num, ...) do {\
+        log_index(COMBINE_TRACE_INFO(type, sub_type, module, LEVEL_ERROR), fmt, param_num, ##__VA_ARGS__);\
+    } while (0)
+#define DBG_TEXT_LEVEL_ERROR(type, sub_type, module, fmt, ...) do {\
+        log_text(COMBINE_TRACE_INFO(type, sub_type, module, LEVEL_ERROR), fmt, ##__VA_ARGS__);\
+    } while (0)
+#else
+#define DBG_BUFFER_LEVEL_ERROR(type, sub_type, module, fmt, param_num, ...)
+#define DBG_INDEX_LEVEL_ERROR(type, sub_type, module, fmt, param_num, ...)
+#define DBG_TEXT_LEVEL_ERROR(type, sub_type, module, fmt, ...)
+#endif
+
+#if (DBG_LEVEL >= LEVEL_WARN)
+#define DBG_BUFFER_LEVEL_WARN(type, sub_type, module, fmt, param_num, ...)  do {\
+        DBG_BUFFER_INTERNAL(type, sub_type, module, LEVEL_WARN, fmt, param_num, ##__VA_ARGS__);\
+    } while (0)
+#define DBG_INDEX_LEVEL_WARN(type, sub_type, module, fmt, param_num, ...) do {\
+        log_index(COMBINE_TRACE_INFO(type, sub_type, module, LEVEL_WARN), fmt, param_num, ##__VA_ARGS__);\
+    } while (0)
+#define DBG_TEXT_LEVEL_WARN(type, sub_type, module, fmt, ...) do {\
+        log_text(COMBINE_TRACE_INFO(type, sub_type, module, LEVEL_WARN), fmt, ##__VA_ARGS__);\
+    } while (0)
+#else
+#define DBG_BUFFER_LEVEL_WARN(type, sub_type, module, fmt, param_num, ...)
+#define DBG_INDEX_LEVEL_WARN(type, sub_type, module, fmt, param_num, ...)
+#define DBG_TEXT_LEVEL_WARN(type, sub_type, module, fmt, ...)
+#endif
+
+#if (DBG_LEVEL >= LEVEL_INFO)
+#define DBG_BUFFER_LEVEL_INFO(type, sub_type, module, fmt, param_num, ...)  do {\
+        DBG_BUFFER_INTERNAL(type, sub_type, module, LEVEL_INFO, fmt, param_num, ##__VA_ARGS__);\
+    } while (0)
+#define DBG_INDEX_LEVEL_INFO(type, sub_type, module, fmt, param_num, ...) do {\
+        log_index(COMBINE_TRACE_INFO(type, sub_type, module, LEVEL_INFO), fmt, param_num, ##__VA_ARGS__);\
+    } while (0)
+#define DBG_TEXT_LEVEL_INFO(type, sub_type, module, fmt, ...) do {\
+        log_text(COMBINE_TRACE_INFO(type, sub_type, module, LEVEL_INFO), fmt, ##__VA_ARGS__);\
+    } while (0)
+#else
+#define DBG_BUFFER_LEVEL_INFO(type, sub_type, module, fmt, param_num, ...)
+#define DBG_INDEX_LEVEL_INFO(type, sub_type, module, fmt, param_num, ...)
+#define DBG_TEXT_LEVEL_INFO(type, sub_type, module, fmt, ...)
+#endif
+
+#if (DBG_LEVEL >= LEVEL_TRACE)
+#define DBG_BUFFER_LEVEL_TRACE(type, sub_type, module, fmt, param_num, ...) do {\
+        DBG_BUFFER_INTERNAL(type, sub_type, module, LEVEL_TRACE, fmt, param_num, ##__VA_ARGS__);\
+    } while (0)
+#define DBG_INDEX_LEVEL_TRACE(type, sub_type, module, fmt, param_num, ...) do {\
+        log_index(COMBINE_TRACE_INFO(type, sub_type, module, LEVEL_TRACE), fmt, param_num, ##__VA_ARGS__);\
+    } while (0)
+#define DBG_TEXT_LEVEL_TRACE(type, sub_type, module, fmt, ...) do {\
+        log_index(COMBINE_TRACE_INFO(type, sub_type, module, LEVEL_TRACE), fmt, ##__VA_ARGS__);\
+    } while (0)
+#else
+#define DBG_BUFFER_LEVEL_TRACE(type, sub_type, module, fmt, param_num, ...)
+#define DBG_INDEX_LEVEL_TRACE(type, sub_type, module, fmt, param_num, ...)
+#define DBG_TEXT_LEVEL_TRACE(type, sub_type, module, fmt, ...)
+#endif
+
+#define DBG_BUFFER(type, sub_type, module, level, fmt, param_num,...)   \
+    DBG_BUFFER_##level(type, sub_type, module, fmt, param_num, ##__VA_ARGS__)
+
+#define DBG_INDEX(type, sub_type, module, level, fmt, param_num,...)   \
+    DBG_INDEX_##level(type, sub_type, module, fmt, param_num, ##__VA_ARGS__)
+
+#define DBG_TEXT(type, sub_type, module, level, fmt, ...)   \
+    DBG_TEXT_##level(type, sub_type, module, fmt, ##__VA_ARGS__)
+
+#define DBG_DIRECT(...)     do {\
+        log_direct(COMBINE_TRACE_INFO(LOG_TYPE, SUBTYPE_DIRECT, 0, 0), __VA_ARGS__);\
+    } while (0)
+
+#define DIRECT_LOG(fmt, param_num,...)     do {\
+        DBG_BUFFER_INTERNAL(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BOOT, LEVEL_ERROR, fmt, param_num, ##__VA_ARGS__);\
+    } while (0)
+
+#if (LOG_TYPE == TYPE_RTL87X2G)
+#define DBG_LOWERSTACK(color, file_num, line_num, str_index, param_num, ...)     do {\
+        log_buffer_lowerstack(str_index, param_num, ##__VA_ARGS__);\
+    } while (0)
+#else
+#define DBG_LOWERSTACK(color, file_num, line_num, str_index, param_num, ...)     do {\
+        log_buffer(((file_num)<<16)|(line_num), (((MODULE_LOWERSTACK)<<16)|(str_index)), param_num, ##__VA_ARGS__);\
+    } while (0)
+#endif
+
+#define DBG_LOWERSTACKDATA(color, file_num, line_num, str_index, length, str)     do {\
+        LogBufferLowerStackData((((file_num)<<16)|(line_num), (uint16_t)(str_index), length, str);\
+    } while (0)
+
+#define DBG_SNOOP(type, sub_type, module, level, length, snoop)    do {\
+        log_snoop(COMBINE_TRACE_INFO(type, sub_type, module, level), length, snoop);\
+    } while (0)
+
+
+void LogUartTxData(uint8_t *data, uint32_t len);
+
+/**
+ * trace.h
+ *
+ * \brief    Initialize module trace mask.
+ *
+ * \param[in]   mask    Module trace mask array. Set NULL to load default mask array.
+ *
+ * \return      None.
+ *
+ * \ingroup  TRACE
+ */
+void log_module_trace_init(uint64_t mask[LEVEL_NUM]);
+
+/**
+ * trace.h
+ *
+ * \brief    Enable/Disable the module ID's trace.
+ *
+ * \param[in]   module_id   The specific module ID defined in \ref MODULE_ID.
+ *
+ * \param[in]   trace_level The trace level of the module ID defined in \ref TRACE_LEVEL.
+ *
+ * \param[in]   set         Enable or disable the module ID's trace.
+ * \arg \c true     Enable the module ID's trace.
+ * \arg \c false    Disable the module ID's trace.
+ *
+ * \return           The status of setting module ID's trace.
+ * \retval true      Module ID's trace was set successfully.
+ * \retval false     Module ID's trace was failed to set.
+ *
+ * \ingroup  TRACE
+ */
+extern bool (*log_module_trace_set)(T_MODULE_ID module_id, uint8_t trace_level, bool set);
+
+/**
+ * trace.h
+ *
+ * \brief    Enable/Disable module bitmap's trace.
+ *
+ * \param[in]   module_bitmap   The module bitmap defined in \ref MODULE_BITMAP.
+ *
+ * \param[in]   trace_level     The trace level of the module bitmap defined in \ref TRACE_LEVEL.
+ *
+ * \param[in]   set             Enable or disable the module bitmap's trace.
+ * \arg \c true     Enable the module bitmap's trace.
+ * \arg \c false    Disable the module bitmap's trace.
+ *
+ * \return           The status of setting module bitmap's trace.
+ * \retval true      Module bitmap's trace was set successfully.
+ * \retval false     Module bitmap's trace was failed to set.
+ *
+ * \ingroup  TRACE
+ */
+bool log_module_bitmap_trace_set(uint64_t module_bitmap, uint8_t trace_level, bool set);
+
+/**
+ * trace.h
+ *
+ * \brief    Get system timestamp.
+ *
+ * \param       None.
+ *
+ * \return      System timestamp value in milliseconds.
+ *
+ * \ingroup  TRACE
+ */
+extern uint32_t (*sys_timestamp_get)(void);
+extern uint32_t (*log_timestamp_get)(void);
+/**
+ * trace.h
+ *
+ * \brief    Register log destination callback function.
+ *
+ * \param[in]   dest    Indicates where the callback is registered in.
+ * \arg \c LOG_OUTPUT_FLASH_MASK    Register callback for log to flash.
+ * \arg \c LOG_OUTPUT_VENDOR_MASK   Register callback for vendor specific use.
+ *
+ * \param[in]   func    The callback function to register.
+ *
+ * \return      None.
+ *
+ * \ingroup  TRACE
+ */
+void register_log_dest_cb(uint8_t dest, void *func);
+
+/**
+ * trace.h
+ *
+ * \name    AUXILIARY_PRINT_BDADDR
+ * \brief   Auxiliary Interface that is used to print BD address.
+ * \anchor  AUXILIARY_PRINT_BDADDR
+ */
+/**
+ * \ingroup TRACE
+ */
+#define TRACE_BDADDR(bd_addr)   \
+    trace_string(COMBINE_TRACE_INFO(LOG_TYPE, SUBTYPE_BDADDR, 0, 0), 0, (char *)(bd_addr))
+
+/**
+ * trace.h
+ *
+ * \name    AUXILIARY_PRINT_STRING
+ * \brief   Auxiliary Interface that is used to print string.
+ * \anchor  AUXILIARY_PRINT_STRING
+ */
+/**
+ * \ingroup TRACE
+ */
+#define TRACE_STRING(data)    \
+    trace_string(COMBINE_TRACE_INFO(LOG_TYPE, SUBTYPE_STRING, 0, 0), 0, (char *)(data))
+
+/**
+ * trace.h
+ *
+ * \name    AUXILIARY_PRINT_BINARY
+ * \brief   Auxiliary Interface that is used to print binary string.
+ * \anchor  AUXILIARY_PRINT_BINARY
+ */
+/**
+ * \ingroup TRACE
+ */
+/**@{*/
+#define TRACE_BINARY(length, data)  \
+    trace_string(COMBINE_TRACE_INFO(LOG_TYPE, SUBTYPE_BINARY, 0, 0), length, (char *)(data))
+/**@}*/
+
+
+/* Bluetooth HCI Snoop Trace Interfaces */
+#define BT_SNOOP_DOWN_TRACE(length, snoop)  \
+    DBG_SNOOP(LOG_TYPE, SUBTYPE_DOWN_SNOOP, MODULE_SNOOP, LEVEL_ERROR, length, snoop);
+#define BT_SNOOP_UP_TRACE(length, snoop)  \
+    DBG_SNOOP(LOG_TYPE, SUBTYPE_UP_SNOOP, MODULE_SNOOP, LEVEL_ERROR, length, snoop);
+
+
+/* Bluetooth Message Trace Interfaces */
+#define BT_MESSAGE_DOWN_PRINT_ERROR(length, message)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_DOWN_MESSAGE, MODULE_UPPERSTACK, LEVEL_ERROR, "", 2, length, message)
+#define BT_MESSAGE_DOWN_PRINT_WARN(length, message)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_DOWN_MESSAGE, MODULE_UPPERSTACK, LEVEL_WARN, "", 2, length, message)
+#define BT_MESSAGE_DOWN_PRINT_INFO(length, message)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_DOWN_MESSAGE, MODULE_UPPERSTACK, LEVEL_INFO, "", 2, length, message)
+#define BT_MESSAGE_DOWN_PRINT_TRACE(length, message)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_DOWN_MESSAGE, MODULE_UPPERSTACK, LEVEL_TRACE, "", 2, length, message)
+#define BT_MESSAGE_UP_PRINT_ERROR(length, message)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_UP_MESSAGE, MODULE_UPPERSTACK, LEVEL_ERROR, "", 2, length, message)
+#define BT_MESSAGE_UP_PRINT_WARN(length, message)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_UP_MESSAGE, MODULE_UPPERSTACK, LEVEL_WARN, "", 2, length, message)
+#define BT_MESSAGE_UP_PRINT_INFO(length, message)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_UP_MESSAGE, MODULE_UPPERSTACK, LEVEL_INFO, "", 2, length, message)
+#define BT_MESSAGE_UP_PRINT_TRACE(length, message)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_UP_MESSAGE, MODULE_UPPERSTACK, LEVEL_TRACE, "", 2, length, message)
+
+
+/* Patch Trace Interfaces */
+#define PATCH_PRINT_ERROR0(fmt)   \
+    DBG_INDEX(LOG_TYPE, SUBTYPE_INDEX, MODULE_PATCH, LEVEL_ERROR, fmt, 0)
+#define PATCH_PRINT_ERROR1(fmt, arg0)   \
+    DBG_INDEX(LOG_TYPE, SUBTYPE_INDEX, MODULE_PATCH, LEVEL_ERROR, fmt, 1, arg0)
+#define PATCH_PRINT_ERROR2(fmt, arg0, arg1)   \
+    DBG_INDEX(LOG_TYPE, SUBTYPE_INDEX, MODULE_PATCH, LEVEL_ERROR, fmt, 2, arg0, arg1)
+#define PATCH_PRINT_ERROR3(fmt, arg0, arg1, arg2)   \
+    DBG_INDEX(LOG_TYPE, SUBTYPE_INDEX, MODULE_PATCH, LEVEL_ERROR, fmt, 3, arg0, arg1, arg2)
+#define PATCH_PRINT_ERROR4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_INDEX(LOG_TYPE, SUBTYPE_INDEX, MODULE_PATCH, LEVEL_ERROR, fmt, 4, arg0, arg1, arg2, arg3)
+#define PATCH_PRINT_ERROR5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_INDEX(LOG_TYPE, SUBTYPE_INDEX, MODULE_PATCH, LEVEL_ERROR, fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define PATCH_PRINT_ERROR6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_INDEX(LOG_TYPE, SUBTYPE_INDEX, MODULE_PATCH, LEVEL_ERROR, fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define PATCH_PRINT_ERROR7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_INDEX(LOG_TYPE, SUBTYPE_INDEX, MODULE_PATCH, LEVEL_ERROR, fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define PATCH_PRINT_ERROR8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_INDEX(LOG_TYPE, SUBTYPE_INDEX, MODULE_PATCH, LEVEL_ERROR, fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define PATCH_PRINT_WARN0(fmt)   \
+    DBG_INDEX(LOG_TYPE, SUBTYPE_INDEX, MODULE_PATCH, LEVEL_WARN, fmt, 0)
+#define PATCH_PRINT_WARN1(fmt, arg0)   \
+    DBG_INDEX(LOG_TYPE, SUBTYPE_INDEX, MODULE_PATCH, LEVEL_WARN, fmt, 1, arg0)
+#define PATCH_PRINT_WARN2(fmt, arg0, arg1)   \
+    DBG_INDEX(LOG_TYPE, SUBTYPE_INDEX, MODULE_PATCH, LEVEL_WARN, fmt, 2, arg0, arg1)
+#define PATCH_PRINT_WARN3(fmt, arg0, arg1, arg2)   \
+    DBG_INDEX(LOG_TYPE, SUBTYPE_INDEX, MODULE_PATCH, LEVEL_WARN, fmt, 3, arg0, arg1, arg2)
+#define PATCH_PRINT_WARN4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_INDEX(LOG_TYPE, SUBTYPE_INDEX, MODULE_PATCH, LEVEL_WARN, fmt, 4, arg0, arg1, arg2, arg3)
+#define PATCH_PRINT_WARN5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_INDEX(LOG_TYPE, SUBTYPE_INDEX, MODULE_PATCH, LEVEL_WARN, fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define PATCH_PRINT_WARN6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_INDEX(LOG_TYPE, SUBTYPE_INDEX, MODULE_PATCH, LEVEL_WARN, fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define PATCH_PRINT_WARN7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_INDEX(LOG_TYPE, SUBTYPE_INDEX, MODULE_PATCH, LEVEL_WARN, fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define PATCH_PRINT_WARN8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_INDEX(LOG_TYPE, SUBTYPE_INDEX, MODULE_PATCH, LEVEL_WARN, fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define PATCH_PRINT_INFO0(fmt)   \
+    DBG_INDEX(LOG_TYPE, SUBTYPE_INDEX, MODULE_PATCH, LEVEL_INFO, fmt, 0)
+#define PATCH_PRINT_INFO1(fmt, arg0)   \
+    DBG_INDEX(LOG_TYPE, SUBTYPE_INDEX, MODULE_PATCH, LEVEL_INFO, fmt, 1, arg0)
+#define PATCH_PRINT_INFO2(fmt, arg0, arg1)   \
+    DBG_INDEX(LOG_TYPE, SUBTYPE_INDEX, MODULE_PATCH, LEVEL_INFO, fmt, 2, arg0, arg1)
+#define PATCH_PRINT_INFO3(fmt, arg0, arg1, arg2)   \
+    DBG_INDEX(LOG_TYPE, SUBTYPE_INDEX, MODULE_PATCH, LEVEL_INFO, fmt, 3, arg0, arg1, arg2)
+#define PATCH_PRINT_INFO4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_INDEX(LOG_TYPE, SUBTYPE_INDEX, MODULE_PATCH, LEVEL_INFO, fmt, 4, arg0, arg1, arg2, arg3)
+#define PATCH_PRINT_INFO5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_INDEX(LOG_TYPE, SUBTYPE_INDEX, MODULE_PATCH, LEVEL_INFO, fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define PATCH_PRINT_INFO6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_INDEX(LOG_TYPE, SUBTYPE_INDEX, MODULE_PATCH, LEVEL_INFO, fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define PATCH_PRINT_INFO7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_INDEX(LOG_TYPE, SUBTYPE_INDEX, MODULE_PATCH, LEVEL_INFO, fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define PATCH_PRINT_INFO8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_INDEX(LOG_TYPE, SUBTYPE_INDEX, MODULE_PATCH, LEVEL_INFO, fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define PATCH_PRINT_TRACE0(fmt)   \
+    DBG_INDEX(LOG_TYPE, SUBTYPE_INDEX, MODULE_PATCH, LEVEL_TRACE, fmt, 0)
+#define PATCH_PRINT_TRACE1(fmt, arg0)   \
+    DBG_INDEX(LOG_TYPE, SUBTYPE_INDEX, MODULE_PATCH, LEVEL_TRACE, fmt, 1, arg0)
+#define PATCH_PRINT_TRACE2(fmt, arg0, arg1)   \
+    DBG_INDEX(LOG_TYPE, SUBTYPE_INDEX, MODULE_PATCH, LEVEL_TRACE, fmt, 2, arg0, arg1)
+#define PATCH_PRINT_TRACE3(fmt, arg0, arg1, arg2)   \
+    DBG_INDEX(LOG_TYPE, SUBTYPE_INDEX, MODULE_PATCH, LEVEL_TRACE, fmt, 3, arg0, arg1, arg2)
+#define PATCH_PRINT_TRACE4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_INDEX(LOG_TYPE, SUBTYPE_INDEX, MODULE_PATCH, LEVEL_TRACE, fmt, 4, arg0, arg1, arg2, arg3)
+#define PATCH_PRINT_TRACE5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_INDEX(LOG_TYPE, SUBTYPE_INDEX, MODULE_PATCH, LEVEL_TRACE, fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define PATCH_PRINT_TRACE6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_INDEX(LOG_TYPE, SUBTYPE_INDEX, MODULE_PATCH, LEVEL_TRACE, fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define PATCH_PRINT_TRACE7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_INDEX(LOG_TYPE, SUBTYPE_INDEX, MODULE_PATCH, LEVEL_TRACE, fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define PATCH_PRINT_TRACE8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_INDEX(LOG_TYPE, SUBTYPE_INDEX, MODULE_PATCH, LEVEL_TRACE, fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+
+/* Bluetooth Lower Stack Trace Interfaces */
+#define LOWERSTACK_PRINT_ERROR0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_LOWERSTACK, LEVEL_ERROR, "!!!"fmt, 0)
+#define LOWERSTACK_PRINT_ERROR1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_LOWERSTACK, LEVEL_ERROR, "!!!"fmt, 1, arg0)
+#define LOWERSTACK_PRINT_ERROR2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_LOWERSTACK, LEVEL_ERROR, "!!!"fmt, 2, arg0, arg1)
+#define LOWERSTACK_PRINT_ERROR3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_LOWERSTACK, LEVEL_ERROR, "!!!"fmt, 3, arg0, arg1, arg2)
+#define LOWERSTACK_PRINT_ERROR4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_LOWERSTACK, LEVEL_ERROR, "!!!"fmt, 4, arg0, arg1, arg2, arg3)
+#define LOWERSTACK_PRINT_ERROR5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_LOWERSTACK, LEVEL_ERROR, "!!!"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define LOWERSTACK_PRINT_ERROR6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_LOWERSTACK, LEVEL_ERROR, "!!!"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define LOWERSTACK_PRINT_ERROR7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_LOWERSTACK, LEVEL_ERROR, "!!!"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define LOWERSTACK_PRINT_ERROR8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_LOWERSTACK, LEVEL_ERROR, "!!!"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define LOWERSTACK_PRINT_WARN0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_LOWERSTACK, LEVEL_WARN, "!!*"fmt, 0)
+#define LOWERSTACK_PRINT_WARN1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_LOWERSTACK, LEVEL_WARN, "!!*"fmt, 1, arg0)
+#define LOWERSTACK_PRINT_WARN2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_LOWERSTACK, LEVEL_WARN, "!!*"fmt, 2, arg0, arg1)
+#define LOWERSTACK_PRINT_WARN3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_LOWERSTACK, LEVEL_WARN, "!!*"fmt, 3, arg0, arg1, arg2)
+#define LOWERSTACK_PRINT_WARN4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_LOWERSTACK, LEVEL_WARN, "!!*"fmt, 4, arg0, arg1, arg2, arg3)
+#define LOWERSTACK_PRINT_WARN5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_LOWERSTACK, LEVEL_WARN, "!!*"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define LOWERSTACK_PRINT_WARN6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_LOWERSTACK, LEVEL_WARN, "!!*"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define LOWERSTACK_PRINT_WARN7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_LOWERSTACK, LEVEL_WARN, "!!*"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define LOWERSTACK_PRINT_WARN8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_LOWERSTACK, LEVEL_WARN, "!!*"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define LOWERSTACK_PRINT_INFO0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_LOWERSTACK, LEVEL_INFO, "!**"fmt, 0)
+#define LOWERSTACK_PRINT_INFO1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_LOWERSTACK, LEVEL_INFO, "!**"fmt, 1, arg0)
+#define LOWERSTACK_PRINT_INFO2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_LOWERSTACK, LEVEL_INFO, "!**"fmt, 2, arg0, arg1)
+#define LOWERSTACK_PRINT_INFO3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_LOWERSTACK, LEVEL_INFO, "!**"fmt, 3, arg0, arg1, arg2)
+#define LOWERSTACK_PRINT_INFO4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_LOWERSTACK, LEVEL_INFO, "!**"fmt, 4, arg0, arg1, arg2, arg3)
+#define LOWERSTACK_PRINT_INFO5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_LOWERSTACK, LEVEL_INFO, "!**"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define LOWERSTACK_PRINT_INFO6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_LOWERSTACK, LEVEL_INFO, "!**"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define LOWERSTACK_PRINT_INFO7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_LOWERSTACK, LEVEL_INFO, "!**"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define LOWERSTACK_PRINT_INFO8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_LOWERSTACK, LEVEL_INFO, "!**"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define LOWERSTACK_PRINT_INFO9(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_LOWERSTACK, LEVEL_INFO, "!**"fmt, 9, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8)
+#define LOWERSTACK_PRINT_TRACE0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_LOWERSTACK, LEVEL_TRACE, fmt, 0)
+#define LOWERSTACK_PRINT_TRACE1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_LOWERSTACK, LEVEL_TRACE, fmt, 1, arg0)
+#define LOWERSTACK_PRINT_TRACE2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_LOWERSTACK, LEVEL_TRACE, fmt, 2, arg0, arg1)
+#define LOWERSTACK_PRINT_TRACE3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_LOWERSTACK, LEVEL_TRACE, fmt, 3, arg0, arg1, arg2)
+#define LOWERSTACK_PRINT_TRACE4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_LOWERSTACK, LEVEL_TRACE, fmt, 4, arg0, arg1, arg2, arg3)
+#define LOWERSTACK_PRINT_TRACE5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_LOWERSTACK, LEVEL_TRACE, fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define LOWERSTACK_PRINT_TRACE6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_LOWERSTACK, LEVEL_TRACE, fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define LOWERSTACK_PRINT_TRACE7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_LOWERSTACK, LEVEL_TRACE, fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define LOWERSTACK_PRINT_TRACE8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_LOWERSTACK, LEVEL_TRACE, fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+
+
+/* OS Trace Interfaces */
+#define OS_PRINT_ERROR0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OS, LEVEL_ERROR, "!!!"fmt, 0)
+#define OS_PRINT_ERROR1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OS, LEVEL_ERROR, "!!!"fmt, 1, arg0)
+#define OS_PRINT_ERROR2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OS, LEVEL_ERROR, "!!!"fmt, 2, arg0, arg1)
+#define OS_PRINT_ERROR3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OS, LEVEL_ERROR, "!!!"fmt, 3, arg0, arg1, arg2)
+#define OS_PRINT_ERROR4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OS, LEVEL_ERROR, "!!!"fmt, 4, arg0, arg1, arg2, arg3)
+#define OS_PRINT_ERROR5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OS, LEVEL_ERROR, "!!!"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define OS_PRINT_ERROR6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OS, LEVEL_ERROR, "!!!"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define OS_PRINT_ERROR7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OS, LEVEL_ERROR, "!!!"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define OS_PRINT_ERROR8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OS, LEVEL_ERROR, "!!!"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define OS_PRINT_WARN0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OS, LEVEL_WARN, "!!*"fmt, 0)
+#define OS_PRINT_WARN1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OS, LEVEL_WARN, "!!*"fmt, 1, arg0)
+#define OS_PRINT_WARN2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OS, LEVEL_WARN, "!!*"fmt, 2, arg0, arg1)
+#define OS_PRINT_WARN3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OS, LEVEL_WARN, "!!*"fmt, 3, arg0, arg1, arg2)
+#define OS_PRINT_WARN4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OS, LEVEL_WARN, "!!*"fmt, 4, arg0, arg1, arg2, arg3)
+#define OS_PRINT_WARN5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OS, LEVEL_WARN, "!!*"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define OS_PRINT_WARN6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OS, LEVEL_WARN, "!!*"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define OS_PRINT_WARN7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OS, LEVEL_WARN, "!!*"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define OS_PRINT_WARN8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OS, LEVEL_WARN, "!!*"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define OS_PRINT_INFO0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OS, LEVEL_INFO, "!**"fmt, 0)
+#define OS_PRINT_INFO1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OS, LEVEL_INFO, "!**"fmt, 1, arg0)
+#define OS_PRINT_INFO2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OS, LEVEL_INFO, "!**"fmt, 2, arg0, arg1)
+#define OS_PRINT_INFO3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OS, LEVEL_INFO, "!**"fmt, 3, arg0, arg1, arg2)
+#define OS_PRINT_INFO4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OS, LEVEL_INFO, "!**"fmt, 4, arg0, arg1, arg2, arg3)
+#define OS_PRINT_INFO5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OS, LEVEL_INFO, "!**"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define OS_PRINT_INFO6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OS, LEVEL_INFO, "!**"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define OS_PRINT_INFO7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OS, LEVEL_INFO, "!**"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define OS_PRINT_INFO8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OS, LEVEL_INFO, "!**"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define OS_PRINT_TRACE0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OS, LEVEL_TRACE, fmt, 0)
+#define OS_PRINT_TRACE1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OS, LEVEL_TRACE, fmt, 1, arg0)
+#define OS_PRINT_TRACE2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OS, LEVEL_TRACE, fmt, 2, arg0, arg1)
+#define OS_PRINT_TRACE3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OS, LEVEL_TRACE, fmt, 3, arg0, arg1, arg2)
+#define OS_PRINT_TRACE4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OS, LEVEL_TRACE, fmt, 4, arg0, arg1, arg2, arg3)
+#define OS_PRINT_TRACE5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OS, LEVEL_TRACE, fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define OS_PRINT_TRACE6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OS, LEVEL_TRACE, fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define OS_PRINT_TRACE7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OS, LEVEL_TRACE, fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define OS_PRINT_TRACE8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OS, LEVEL_TRACE, fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+
+
+/* OSIF Trace Interfaces */
+#define OSIF_PRINT_ERROR0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OSIF, LEVEL_ERROR, "!!!"fmt, 0)
+#define OSIF_PRINT_ERROR1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OSIF, LEVEL_ERROR, "!!!"fmt, 1, arg0)
+#define OSIF_PRINT_ERROR2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OSIF, LEVEL_ERROR, "!!!"fmt, 2, arg0, arg1)
+#define OSIF_PRINT_ERROR3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OSIF, LEVEL_ERROR, "!!!"fmt, 3, arg0, arg1, arg2)
+#define OSIF_PRINT_ERROR4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OSIF, LEVEL_ERROR, "!!!"fmt, 4, arg0, arg1, arg2, arg3)
+#define OSIF_PRINT_ERROR5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OSIF, LEVEL_ERROR, "!!!"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define OSIF_PRINT_ERROR6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OSIF, LEVEL_ERROR, "!!!"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define OSIF_PRINT_ERROR7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OSIF, LEVEL_ERROR, "!!!"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define OSIF_PRINT_ERROR8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OSIF, LEVEL_ERROR, "!!!"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define OSIF_PRINT_WARN0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OSIF, LEVEL_WARN, "!!*"fmt, 0)
+#define OSIF_PRINT_WARN1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OSIF, LEVEL_WARN, "!!*"fmt, 1, arg0)
+#define OSIF_PRINT_WARN2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OSIF, LEVEL_WARN, "!!*"fmt, 2, arg0, arg1)
+#define OSIF_PRINT_WARN3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OSIF, LEVEL_WARN, "!!*"fmt, 3, arg0, arg1, arg2)
+#define OSIF_PRINT_WARN4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OSIF, LEVEL_WARN, "!!*"fmt, 4, arg0, arg1, arg2, arg3)
+#define OSIF_PRINT_WARN5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OSIF, LEVEL_WARN, "!!*"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define OSIF_PRINT_WARN6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OSIF, LEVEL_WARN, "!!*"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define OSIF_PRINT_WARN7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OSIF, LEVEL_WARN, "!!*"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define OSIF_PRINT_WARN8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OSIF, LEVEL_WARN, "!!*"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define OSIF_PRINT_INFO0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OSIF, LEVEL_INFO, "!**"fmt, 0)
+#define OSIF_PRINT_INFO1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OSIF, LEVEL_INFO, "!**"fmt, 1, arg0)
+#define OSIF_PRINT_INFO2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OSIF, LEVEL_INFO, "!**"fmt, 2, arg0, arg1)
+#define OSIF_PRINT_INFO3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OSIF, LEVEL_INFO, "!**"fmt, 3, arg0, arg1, arg2)
+#define OSIF_PRINT_INFO4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OSIF, LEVEL_INFO, "!**"fmt, 4, arg0, arg1, arg2, arg3)
+#define OSIF_PRINT_INFO5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OSIF, LEVEL_INFO, "!**"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define OSIF_PRINT_INFO6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OSIF, LEVEL_INFO, "!**"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define OSIF_PRINT_INFO7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OSIF, LEVEL_INFO, "!**"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define OSIF_PRINT_INFO8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OSIF, LEVEL_INFO, "!**"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define OSIF_PRINT_TRACE0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OSIF, LEVEL_TRACE, fmt, 0)
+#define OSIF_PRINT_TRACE1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OSIF, LEVEL_TRACE, fmt, 1, arg0)
+#define OSIF_PRINT_TRACE2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OSIF, LEVEL_TRACE, fmt, 2, arg0, arg1)
+#define OSIF_PRINT_TRACE3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OSIF, LEVEL_TRACE, fmt, 3, arg0, arg1, arg2)
+#define OSIF_PRINT_TRACE4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OSIF, LEVEL_TRACE, fmt, 4, arg0, arg1, arg2, arg3)
+#define OSIF_PRINT_TRACE5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OSIF, LEVEL_TRACE, fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define OSIF_PRINT_TRACE6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OSIF, LEVEL_TRACE, fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define OSIF_PRINT_TRACE7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OSIF, LEVEL_TRACE, fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define OSIF_PRINT_TRACE8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_OSIF, LEVEL_TRACE, fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+
+
+/* Bluetooth HCI Trace Interfaces */
+#define HCI_PRINT_ERROR0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_HCI, LEVEL_ERROR, "!!!"fmt, 0)
+#define HCI_PRINT_ERROR1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_HCI, LEVEL_ERROR, "!!!"fmt, 1, arg0)
+#define HCI_PRINT_ERROR2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_HCI, LEVEL_ERROR, "!!!"fmt, 2, arg0, arg1)
+#define HCI_PRINT_ERROR3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_HCI, LEVEL_ERROR, "!!!"fmt, 3, arg0, arg1, arg2)
+#define HCI_PRINT_ERROR4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_HCI, LEVEL_ERROR, "!!!"fmt, 4, arg0, arg1, arg2, arg3)
+#define HCI_PRINT_ERROR5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_HCI, LEVEL_ERROR, "!!!"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define HCI_PRINT_ERROR6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_HCI, LEVEL_ERROR, "!!!"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define HCI_PRINT_ERROR7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_HCI, LEVEL_ERROR, "!!!"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define HCI_PRINT_ERROR8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_HCI, LEVEL_ERROR, "!!!"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define HCI_PRINT_WARN0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_HCI, LEVEL_WARN, "!!*"fmt, 0)
+#define HCI_PRINT_WARN1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_HCI, LEVEL_WARN, "!!*"fmt, 1, arg0)
+#define HCI_PRINT_WARN2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_HCI, LEVEL_WARN, "!!*"fmt, 2, arg0, arg1)
+#define HCI_PRINT_WARN3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_HCI, LEVEL_WARN, "!!*"fmt, 3, arg0, arg1, arg2)
+#define HCI_PRINT_WARN4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_HCI, LEVEL_WARN, "!!*"fmt, 4, arg0, arg1, arg2, arg3)
+#define HCI_PRINT_WARN5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_HCI, LEVEL_WARN, "!!*"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define HCI_PRINT_WARN6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_HCI, LEVEL_WARN, "!!*"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define HCI_PRINT_WARN7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_HCI, LEVEL_WARN, "!!*"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define HCI_PRINT_WARN8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_HCI, LEVEL_WARN, "!!*"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define HCI_PRINT_INFO0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_HCI, LEVEL_INFO, "!**"fmt, 0)
+#define HCI_PRINT_INFO1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_HCI, LEVEL_INFO, "!**"fmt, 1, arg0)
+#define HCI_PRINT_INFO2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_HCI, LEVEL_INFO, "!**"fmt, 2, arg0, arg1)
+#define HCI_PRINT_INFO3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_HCI, LEVEL_INFO, "!**"fmt, 3, arg0, arg1, arg2)
+#define HCI_PRINT_INFO4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_HCI, LEVEL_INFO, "!**"fmt, 4, arg0, arg1, arg2, arg3)
+#define HCI_PRINT_INFO5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_HCI, LEVEL_INFO, "!**"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define HCI_PRINT_INFO6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_HCI, LEVEL_INFO, "!**"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define HCI_PRINT_INFO7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_HCI, LEVEL_INFO, "!**"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define HCI_PRINT_INFO8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_HCI, LEVEL_INFO, "!**"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define HCI_PRINT_TRACE0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_HCI, LEVEL_TRACE, fmt, 0)
+#define HCI_PRINT_TRACE1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_HCI, LEVEL_TRACE, fmt, 1, arg0)
+#define HCI_PRINT_TRACE2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_HCI, LEVEL_TRACE, fmt, 2, arg0, arg1)
+#define HCI_PRINT_TRACE3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_HCI, LEVEL_TRACE, fmt, 3, arg0, arg1, arg2)
+#define HCI_PRINT_TRACE4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_HCI, LEVEL_TRACE, fmt, 4, arg0, arg1, arg2, arg3)
+#define HCI_PRINT_TRACE5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_HCI, LEVEL_TRACE, fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define HCI_PRINT_TRACE6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_HCI, LEVEL_TRACE, fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define HCI_PRINT_TRACE7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_HCI, LEVEL_TRACE, fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define HCI_PRINT_TRACE8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_HCI, LEVEL_TRACE, fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+
+
+/* Bluetooth L2CAP Trace Interfaces */
+#define L2CAP_PRINT_ERROR0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_L2CAP, LEVEL_ERROR, "!!!"fmt, 0)
+#define L2CAP_PRINT_ERROR1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_L2CAP, LEVEL_ERROR, "!!!"fmt, 1, arg0)
+#define L2CAP_PRINT_ERROR2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_L2CAP, LEVEL_ERROR, "!!!"fmt, 2, arg0, arg1)
+#define L2CAP_PRINT_ERROR3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_L2CAP, LEVEL_ERROR, "!!!"fmt, 3, arg0, arg1, arg2)
+#define L2CAP_PRINT_ERROR4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_L2CAP, LEVEL_ERROR, "!!!"fmt, 4, arg0, arg1, arg2, arg3)
+#define L2CAP_PRINT_ERROR5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_L2CAP, LEVEL_ERROR, "!!!"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define L2CAP_PRINT_ERROR6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_L2CAP, LEVEL_ERROR, "!!!"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define L2CAP_PRINT_ERROR7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_L2CAP, LEVEL_ERROR, "!!!"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define L2CAP_PRINT_ERROR8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_L2CAP, LEVEL_ERROR, "!!!"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define L2CAP_PRINT_WARN0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_L2CAP, LEVEL_WARN, "!!*"fmt, 0)
+#define L2CAP_PRINT_WARN1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_L2CAP, LEVEL_WARN, "!!*"fmt, 1, arg0)
+#define L2CAP_PRINT_WARN2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_L2CAP, LEVEL_WARN, "!!*"fmt, 2, arg0, arg1)
+#define L2CAP_PRINT_WARN3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_L2CAP, LEVEL_WARN, "!!*"fmt, 3, arg0, arg1, arg2)
+#define L2CAP_PRINT_WARN4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_L2CAP, LEVEL_WARN, "!!*"fmt, 4, arg0, arg1, arg2, arg3)
+#define L2CAP_PRINT_WARN5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_L2CAP, LEVEL_WARN, "!!*"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define L2CAP_PRINT_WARN6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_L2CAP, LEVEL_WARN, "!!*"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define L2CAP_PRINT_WARN7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_L2CAP, LEVEL_WARN, "!!*"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define L2CAP_PRINT_WARN8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_L2CAP, LEVEL_WARN, "!!*"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define L2CAP_PRINT_INFO0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_L2CAP, LEVEL_INFO, "!**"fmt, 0)
+#define L2CAP_PRINT_INFO1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_L2CAP, LEVEL_INFO, "!**"fmt, 1, arg0)
+#define L2CAP_PRINT_INFO2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_L2CAP, LEVEL_INFO, "!**"fmt, 2, arg0, arg1)
+#define L2CAP_PRINT_INFO3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_L2CAP, LEVEL_INFO, "!**"fmt, 3, arg0, arg1, arg2)
+#define L2CAP_PRINT_INFO4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_L2CAP, LEVEL_INFO, "!**"fmt, 4, arg0, arg1, arg2, arg3)
+#define L2CAP_PRINT_INFO5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_L2CAP, LEVEL_INFO, "!**"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define L2CAP_PRINT_INFO6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_L2CAP, LEVEL_INFO, "!**"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define L2CAP_PRINT_INFO7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_L2CAP, LEVEL_INFO, "!**"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define L2CAP_PRINT_INFO8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_L2CAP, LEVEL_INFO, "!**"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define L2CAP_PRINT_TRACE0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_L2CAP, LEVEL_TRACE, fmt, 0)
+#define L2CAP_PRINT_TRACE1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_L2CAP, LEVEL_TRACE, fmt, 1, arg0)
+#define L2CAP_PRINT_TRACE2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_L2CAP, LEVEL_TRACE, fmt, 2, arg0, arg1)
+#define L2CAP_PRINT_TRACE3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_L2CAP, LEVEL_TRACE, fmt, 3, arg0, arg1, arg2)
+#define L2CAP_PRINT_TRACE4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_L2CAP, LEVEL_TRACE, fmt, 4, arg0, arg1, arg2, arg3)
+#define L2CAP_PRINT_TRACE5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_L2CAP, LEVEL_TRACE, fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define L2CAP_PRINT_TRACE6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_L2CAP, LEVEL_TRACE, fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define L2CAP_PRINT_TRACE7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_L2CAP, LEVEL_TRACE, fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define L2CAP_PRINT_TRACE8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_L2CAP, LEVEL_TRACE, fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+
+
+/* Bluetooth SDP Trace Interfaces */
+#define SDP_PRINT_ERROR0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SDP, LEVEL_ERROR, "!!!"fmt, 0)
+#define SDP_PRINT_ERROR1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SDP, LEVEL_ERROR, "!!!"fmt, 1, arg0)
+#define SDP_PRINT_ERROR2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SDP, LEVEL_ERROR, "!!!"fmt, 2, arg0, arg1)
+#define SDP_PRINT_ERROR3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SDP, LEVEL_ERROR, "!!!"fmt, 3, arg0, arg1, arg2)
+#define SDP_PRINT_ERROR4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SDP, LEVEL_ERROR, "!!!"fmt, 4, arg0, arg1, arg2, arg3)
+#define SDP_PRINT_ERROR5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SDP, LEVEL_ERROR, "!!!"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define SDP_PRINT_ERROR6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SDP, LEVEL_ERROR, "!!!"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define SDP_PRINT_ERROR7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SDP, LEVEL_ERROR, "!!!"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define SDP_PRINT_ERROR8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SDP, LEVEL_ERROR, "!!!"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define SDP_PRINT_WARN0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SDP, LEVEL_WARN, "!!*"fmt, 0)
+#define SDP_PRINT_WARN1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SDP, LEVEL_WARN, "!!*"fmt, 1, arg0)
+#define SDP_PRINT_WARN2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SDP, LEVEL_WARN, "!!*"fmt, 2, arg0, arg1)
+#define SDP_PRINT_WARN3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SDP, LEVEL_WARN, "!!*"fmt, 3, arg0, arg1, arg2)
+#define SDP_PRINT_WARN4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SDP, LEVEL_WARN, "!!*"fmt, 4, arg0, arg1, arg2, arg3)
+#define SDP_PRINT_WARN5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SDP, LEVEL_WARN, "!!*"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define SDP_PRINT_WARN6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SDP, LEVEL_WARN, "!!*"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define SDP_PRINT_WARN7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SDP, LEVEL_WARN, "!!*"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define SDP_PRINT_WARN8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SDP, LEVEL_WARN, "!!*"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define SDP_PRINT_INFO0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SDP, LEVEL_INFO, "!**"fmt, 0)
+#define SDP_PRINT_INFO1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SDP, LEVEL_INFO, "!**"fmt, 1, arg0)
+#define SDP_PRINT_INFO2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SDP, LEVEL_INFO, "!**"fmt, 2, arg0, arg1)
+#define SDP_PRINT_INFO3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SDP, LEVEL_INFO, "!**"fmt, 3, arg0, arg1, arg2)
+#define SDP_PRINT_INFO4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SDP, LEVEL_INFO, "!**"fmt, 4, arg0, arg1, arg2, arg3)
+#define SDP_PRINT_INFO5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SDP, LEVEL_INFO, "!**"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define SDP_PRINT_INFO6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SDP, LEVEL_INFO, "!**"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define SDP_PRINT_INFO7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SDP, LEVEL_INFO, "!**"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define SDP_PRINT_INFO8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SDP, LEVEL_INFO, "!**"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define SDP_PRINT_TRACE0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SDP, LEVEL_TRACE, fmt, 0)
+#define SDP_PRINT_TRACE1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SDP, LEVEL_TRACE, fmt, 1, arg0)
+#define SDP_PRINT_TRACE2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SDP, LEVEL_TRACE, fmt, 2, arg0, arg1)
+#define SDP_PRINT_TRACE3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SDP, LEVEL_TRACE, fmt, 3, arg0, arg1, arg2)
+#define SDP_PRINT_TRACE4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SDP, LEVEL_TRACE, fmt, 4, arg0, arg1, arg2, arg3)
+#define SDP_PRINT_TRACE5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SDP, LEVEL_TRACE, fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define SDP_PRINT_TRACE6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SDP, LEVEL_TRACE, fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define SDP_PRINT_TRACE7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SDP, LEVEL_TRACE, fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define SDP_PRINT_TRACE8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SDP, LEVEL_TRACE, fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+
+
+/* Bluetooth SMP Trace Interfaces */
+#define SMP_PRINT_ERROR0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SMP, LEVEL_ERROR, "!!!"fmt, 0)
+#define SMP_PRINT_ERROR1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SMP, LEVEL_ERROR, "!!!"fmt, 1, arg0)
+#define SMP_PRINT_ERROR2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SMP, LEVEL_ERROR, "!!!"fmt, 2, arg0, arg1)
+#define SMP_PRINT_ERROR3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SMP, LEVEL_ERROR, "!!!"fmt, 3, arg0, arg1, arg2)
+#define SMP_PRINT_ERROR4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SMP, LEVEL_ERROR, "!!!"fmt, 4, arg0, arg1, arg2, arg3)
+#define SMP_PRINT_ERROR5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SMP, LEVEL_ERROR, "!!!"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define SMP_PRINT_ERROR6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SMP, LEVEL_ERROR, "!!!"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define SMP_PRINT_ERROR7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SMP, LEVEL_ERROR, "!!!"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define SMP_PRINT_ERROR8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SMP, LEVEL_ERROR, "!!!"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define SMP_PRINT_WARN0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SMP, LEVEL_WARN, "!!*"fmt, 0)
+#define SMP_PRINT_WARN1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SMP, LEVEL_WARN, "!!*"fmt, 1, arg0)
+#define SMP_PRINT_WARN2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SMP, LEVEL_WARN, "!!*"fmt, 2, arg0, arg1)
+#define SMP_PRINT_WARN3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SMP, LEVEL_WARN, "!!*"fmt, 3, arg0, arg1, arg2)
+#define SMP_PRINT_WARN4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SMP, LEVEL_WARN, "!!*"fmt, 4, arg0, arg1, arg2, arg3)
+#define SMP_PRINT_WARN5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SMP, LEVEL_WARN, "!!*"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define SMP_PRINT_WARN6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SMP, LEVEL_WARN, "!!*"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define SMP_PRINT_WARN7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SMP, LEVEL_WARN, "!!*"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define SMP_PRINT_WARN8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SMP, LEVEL_WARN, "!!*"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define SMP_PRINT_INFO0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SMP, LEVEL_INFO, "!**"fmt, 0)
+#define SMP_PRINT_INFO1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SMP, LEVEL_INFO, "!**"fmt, 1, arg0)
+#define SMP_PRINT_INFO2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SMP, LEVEL_INFO, "!**"fmt, 2, arg0, arg1)
+#define SMP_PRINT_INFO3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SMP, LEVEL_INFO, "!**"fmt, 3, arg0, arg1, arg2)
+#define SMP_PRINT_INFO4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SMP, LEVEL_INFO, "!**"fmt, 4, arg0, arg1, arg2, arg3)
+#define SMP_PRINT_INFO5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SMP, LEVEL_INFO, "!**"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define SMP_PRINT_INFO6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SMP, LEVEL_INFO, "!**"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define SMP_PRINT_INFO7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SMP, LEVEL_INFO, "!**"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define SMP_PRINT_INFO8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SMP, LEVEL_INFO, "!**"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define SMP_PRINT_TRACE0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SMP, LEVEL_TRACE, fmt, 0)
+#define SMP_PRINT_TRACE1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SMP, LEVEL_TRACE, fmt, 1, arg0)
+#define SMP_PRINT_TRACE2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SMP, LEVEL_TRACE, fmt, 2, arg0, arg1)
+#define SMP_PRINT_TRACE3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SMP, LEVEL_TRACE, fmt, 3, arg0, arg1, arg2)
+#define SMP_PRINT_TRACE4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SMP, LEVEL_TRACE, fmt, 4, arg0, arg1, arg2, arg3)
+#define SMP_PRINT_TRACE5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SMP, LEVEL_TRACE, fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define SMP_PRINT_TRACE6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SMP, LEVEL_TRACE, fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define SMP_PRINT_TRACE7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SMP, LEVEL_TRACE, fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define SMP_PRINT_TRACE8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SMP, LEVEL_TRACE, fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+
+
+/* Bluetooth GATT Trace Interfaces */
+#define GATT_PRINT_ERROR0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GATT, LEVEL_ERROR, "!!!"fmt, 0)
+#define GATT_PRINT_ERROR1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GATT, LEVEL_ERROR, "!!!"fmt, 1, arg0)
+#define GATT_PRINT_ERROR2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GATT, LEVEL_ERROR, "!!!"fmt, 2, arg0, arg1)
+#define GATT_PRINT_ERROR3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GATT, LEVEL_ERROR, "!!!"fmt, 3, arg0, arg1, arg2)
+#define GATT_PRINT_ERROR4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GATT, LEVEL_ERROR, "!!!"fmt, 4, arg0, arg1, arg2, arg3)
+#define GATT_PRINT_ERROR5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GATT, LEVEL_ERROR, "!!!"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define GATT_PRINT_ERROR6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GATT, LEVEL_ERROR, "!!!"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define GATT_PRINT_ERROR7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GATT, LEVEL_ERROR, "!!!"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define GATT_PRINT_ERROR8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GATT, LEVEL_ERROR, "!!!"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define GATT_PRINT_WARN0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GATT, LEVEL_WARN, "!!*"fmt, 0)
+#define GATT_PRINT_WARN1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GATT, LEVEL_WARN, "!!*"fmt, 1, arg0)
+#define GATT_PRINT_WARN2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GATT, LEVEL_WARN, "!!*"fmt, 2, arg0, arg1)
+#define GATT_PRINT_WARN3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GATT, LEVEL_WARN, "!!*"fmt, 3, arg0, arg1, arg2)
+#define GATT_PRINT_WARN4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GATT, LEVEL_WARN, "!!*"fmt, 4, arg0, arg1, arg2, arg3)
+#define GATT_PRINT_WARN5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GATT, LEVEL_WARN, "!!*"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define GATT_PRINT_WARN6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GATT, LEVEL_WARN, "!!*"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define GATT_PRINT_WARN7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GATT, LEVEL_WARN, "!!*"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define GATT_PRINT_WARN8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GATT, LEVEL_WARN, "!!*"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define GATT_PRINT_INFO0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GATT, LEVEL_INFO, "!**"fmt, 0)
+#define GATT_PRINT_INFO1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GATT, LEVEL_INFO, "!**"fmt, 1, arg0)
+#define GATT_PRINT_INFO2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GATT, LEVEL_INFO, "!**"fmt, 2, arg0, arg1)
+#define GATT_PRINT_INFO3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GATT, LEVEL_INFO, "!**"fmt, 3, arg0, arg1, arg2)
+#define GATT_PRINT_INFO4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GATT, LEVEL_INFO, "!**"fmt, 4, arg0, arg1, arg2, arg3)
+#define GATT_PRINT_INFO5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GATT, LEVEL_INFO, "!**"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define GATT_PRINT_INFO6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GATT, LEVEL_INFO, "!**"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define GATT_PRINT_INFO7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GATT, LEVEL_INFO, "!**"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define GATT_PRINT_INFO8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GATT, LEVEL_INFO, "!**"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define GATT_PRINT_TRACE0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GATT, LEVEL_TRACE, fmt, 0)
+#define GATT_PRINT_TRACE1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GATT, LEVEL_TRACE, fmt, 1, arg0)
+#define GATT_PRINT_TRACE2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GATT, LEVEL_TRACE, fmt, 2, arg0, arg1)
+#define GATT_PRINT_TRACE3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GATT, LEVEL_TRACE, fmt, 3, arg0, arg1, arg2)
+#define GATT_PRINT_TRACE4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GATT, LEVEL_TRACE, fmt, 4, arg0, arg1, arg2, arg3)
+#define GATT_PRINT_TRACE5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GATT, LEVEL_TRACE, fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define GATT_PRINT_TRACE6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GATT, LEVEL_TRACE, fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define GATT_PRINT_TRACE7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GATT, LEVEL_TRACE, fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define GATT_PRINT_TRACE8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GATT, LEVEL_TRACE, fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+
+
+/* Bluetooth BTIF Trace Interfaces */
+#define BTIF_PRINT_ERROR0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTIF, LEVEL_ERROR, "!!!"fmt, 0)
+#define BTIF_PRINT_ERROR1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTIF, LEVEL_ERROR, "!!!"fmt, 1, arg0)
+#define BTIF_PRINT_ERROR2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTIF, LEVEL_ERROR, "!!!"fmt, 2, arg0, arg1)
+#define BTIF_PRINT_ERROR3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTIF, LEVEL_ERROR, "!!!"fmt, 3, arg0, arg1, arg2)
+#define BTIF_PRINT_ERROR4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTIF, LEVEL_ERROR, "!!!"fmt, 4, arg0, arg1, arg2, arg3)
+#define BTIF_PRINT_ERROR5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTIF, LEVEL_ERROR, "!!!"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define BTIF_PRINT_ERROR6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTIF, LEVEL_ERROR, "!!!"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define BTIF_PRINT_ERROR7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTIF, LEVEL_ERROR, "!!!"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define BTIF_PRINT_ERROR8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTIF, LEVEL_ERROR, "!!!"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define BTIF_PRINT_WARN0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTIF, LEVEL_WARN, "!!*"fmt, 0)
+#define BTIF_PRINT_WARN1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTIF, LEVEL_WARN, "!!*"fmt, 1, arg0)
+#define BTIF_PRINT_WARN2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTIF, LEVEL_WARN, "!!*"fmt, 2, arg0, arg1)
+#define BTIF_PRINT_WARN3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTIF, LEVEL_WARN, "!!*"fmt, 3, arg0, arg1, arg2)
+#define BTIF_PRINT_WARN4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTIF, LEVEL_WARN, "!!*"fmt, 4, arg0, arg1, arg2, arg3)
+#define BTIF_PRINT_WARN5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTIF, LEVEL_WARN, "!!*"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define BTIF_PRINT_WARN6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTIF, LEVEL_WARN, "!!*"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define BTIF_PRINT_WARN7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTIF, LEVEL_WARN, "!!*"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define BTIF_PRINT_WARN8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTIF, LEVEL_WARN, "!!*"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define BTIF_PRINT_INFO0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTIF, LEVEL_INFO, "!**"fmt, 0)
+#define BTIF_PRINT_INFO1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTIF, LEVEL_INFO, "!**"fmt, 1, arg0)
+#define BTIF_PRINT_INFO2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTIF, LEVEL_INFO, "!**"fmt, 2, arg0, arg1)
+#define BTIF_PRINT_INFO3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTIF, LEVEL_INFO, "!**"fmt, 3, arg0, arg1, arg2)
+#define BTIF_PRINT_INFO4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTIF, LEVEL_INFO, "!**"fmt, 4, arg0, arg1, arg2, arg3)
+#define BTIF_PRINT_INFO5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTIF, LEVEL_INFO, "!**"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define BTIF_PRINT_INFO6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTIF, LEVEL_INFO, "!**"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define BTIF_PRINT_INFO7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTIF, LEVEL_INFO, "!**"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define BTIF_PRINT_INFO8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTIF, LEVEL_INFO, "!**"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define BTIF_PRINT_TRACE0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTIF, LEVEL_TRACE, fmt, 0)
+#define BTIF_PRINT_TRACE1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTIF, LEVEL_TRACE, fmt, 1, arg0)
+#define BTIF_PRINT_TRACE2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTIF, LEVEL_TRACE, fmt, 2, arg0, arg1)
+#define BTIF_PRINT_TRACE3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTIF, LEVEL_TRACE, fmt, 3, arg0, arg1, arg2)
+#define BTIF_PRINT_TRACE4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTIF, LEVEL_TRACE, fmt, 4, arg0, arg1, arg2, arg3)
+#define BTIF_PRINT_TRACE5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTIF, LEVEL_TRACE, fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define BTIF_PRINT_TRACE6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTIF, LEVEL_TRACE, fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define BTIF_PRINT_TRACE7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTIF, LEVEL_TRACE, fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define BTIF_PRINT_TRACE8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTIF, LEVEL_TRACE, fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+
+
+/* Bluetooth BTE Trace Interfaces */
+#define BTE_PRINT_ERROR0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTE, LEVEL_ERROR, "!!!"fmt, 0)
+#define BTE_PRINT_ERROR1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTE, LEVEL_ERROR, "!!!"fmt, 1, arg0)
+#define BTE_PRINT_ERROR2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTE, LEVEL_ERROR, "!!!"fmt, 2, arg0, arg1)
+#define BTE_PRINT_ERROR3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTE, LEVEL_ERROR, "!!!"fmt, 3, arg0, arg1, arg2)
+#define BTE_PRINT_ERROR4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTE, LEVEL_ERROR, "!!!"fmt, 4, arg0, arg1, arg2, arg3)
+#define BTE_PRINT_ERROR5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTE, LEVEL_ERROR, "!!!"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define BTE_PRINT_ERROR6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTE, LEVEL_ERROR, "!!!"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define BTE_PRINT_ERROR7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTE, LEVEL_ERROR, "!!!"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define BTE_PRINT_ERROR8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTE, LEVEL_ERROR, "!!!"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define BTE_PRINT_WARN0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTE, LEVEL_WARN, "!!*"fmt, 0)
+#define BTE_PRINT_WARN1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTE, LEVEL_WARN, "!!*"fmt, 1, arg0)
+#define BTE_PRINT_WARN2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTE, LEVEL_WARN, "!!*"fmt, 2, arg0, arg1)
+#define BTE_PRINT_WARN3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTE, LEVEL_WARN, "!!*"fmt, 3, arg0, arg1, arg2)
+#define BTE_PRINT_WARN4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTE, LEVEL_WARN, "!!*"fmt, 4, arg0, arg1, arg2, arg3)
+#define BTE_PRINT_WARN5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTE, LEVEL_WARN, "!!*"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define BTE_PRINT_WARN6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTE, LEVEL_WARN, "!!*"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define BTE_PRINT_WARN7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTE, LEVEL_WARN, "!!*"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define BTE_PRINT_WARN8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTE, LEVEL_WARN, "!!*"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define BTE_PRINT_INFO0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTE, LEVEL_INFO, "!**"fmt, 0)
+#define BTE_PRINT_INFO1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTE, LEVEL_INFO, "!**"fmt, 1, arg0)
+#define BTE_PRINT_INFO2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTE, LEVEL_INFO, "!**"fmt, 2, arg0, arg1)
+#define BTE_PRINT_INFO3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTE, LEVEL_INFO, "!**"fmt, 3, arg0, arg1, arg2)
+#define BTE_PRINT_INFO4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTE, LEVEL_INFO, "!**"fmt, 4, arg0, arg1, arg2, arg3)
+#define BTE_PRINT_INFO5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTE, LEVEL_INFO, "!**"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define BTE_PRINT_INFO6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTE, LEVEL_INFO, "!**"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define BTE_PRINT_INFO7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTE, LEVEL_INFO, "!**"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define BTE_PRINT_INFO8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTE, LEVEL_INFO, "!**"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define BTE_PRINT_TRACE0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTE, LEVEL_TRACE, fmt, 0)
+#define BTE_PRINT_TRACE1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTE, LEVEL_TRACE, fmt, 1, arg0)
+#define BTE_PRINT_TRACE2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTE, LEVEL_TRACE, fmt, 2, arg0, arg1)
+#define BTE_PRINT_TRACE3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTE, LEVEL_TRACE, fmt, 3, arg0, arg1, arg2)
+#define BTE_PRINT_TRACE4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTE, LEVEL_TRACE, fmt, 4, arg0, arg1, arg2, arg3)
+#define BTE_PRINT_TRACE5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTE, LEVEL_TRACE, fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define BTE_PRINT_TRACE6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTE, LEVEL_TRACE, fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define BTE_PRINT_TRACE7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTE, LEVEL_TRACE, fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define BTE_PRINT_TRACE8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTE, LEVEL_TRACE, fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+
+
+/* Bluetooth GAP Trace Interfaces */
+#define GAP_PRINT_ERROR0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GAP, LEVEL_ERROR, "!!!"fmt, 0)
+#define GAP_PRINT_ERROR1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GAP, LEVEL_ERROR, "!!!"fmt, 1, arg0)
+#define GAP_PRINT_ERROR2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GAP, LEVEL_ERROR, "!!!"fmt, 2, arg0, arg1)
+#define GAP_PRINT_ERROR3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GAP, LEVEL_ERROR, "!!!"fmt, 3, arg0, arg1, arg2)
+#define GAP_PRINT_ERROR4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GAP, LEVEL_ERROR, "!!!"fmt, 4, arg0, arg1, arg2, arg3)
+#define GAP_PRINT_ERROR5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GAP, LEVEL_ERROR, "!!!"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define GAP_PRINT_ERROR6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GAP, LEVEL_ERROR, "!!!"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define GAP_PRINT_ERROR7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GAP, LEVEL_ERROR, "!!!"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define GAP_PRINT_ERROR8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GAP, LEVEL_ERROR, "!!!"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define GAP_PRINT_WARN0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GAP, LEVEL_WARN, "!!*"fmt, 0)
+#define GAP_PRINT_WARN1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GAP, LEVEL_WARN, "!!*"fmt, 1, arg0)
+#define GAP_PRINT_WARN2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GAP, LEVEL_WARN, "!!*"fmt, 2, arg0, arg1)
+#define GAP_PRINT_WARN3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GAP, LEVEL_WARN, "!!*"fmt, 3, arg0, arg1, arg2)
+#define GAP_PRINT_WARN4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GAP, LEVEL_WARN, "!!*"fmt, 4, arg0, arg1, arg2, arg3)
+#define GAP_PRINT_WARN5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GAP, LEVEL_WARN, "!!*"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define GAP_PRINT_WARN6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GAP, LEVEL_WARN, "!!*"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define GAP_PRINT_WARN7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GAP, LEVEL_WARN, "!!*"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define GAP_PRINT_WARN8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GAP, LEVEL_WARN, "!!*"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define GAP_PRINT_INFO0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GAP, LEVEL_INFO, "!**"fmt, 0)
+#define GAP_PRINT_INFO1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GAP, LEVEL_INFO, "!**"fmt, 1, arg0)
+#define GAP_PRINT_INFO2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GAP, LEVEL_INFO, "!**"fmt, 2, arg0, arg1)
+#define GAP_PRINT_INFO3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GAP, LEVEL_INFO, "!**"fmt, 3, arg0, arg1, arg2)
+#define GAP_PRINT_INFO4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GAP, LEVEL_INFO, "!**"fmt, 4, arg0, arg1, arg2, arg3)
+#define GAP_PRINT_INFO5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GAP, LEVEL_INFO, "!**"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define GAP_PRINT_INFO6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GAP, LEVEL_INFO, "!**"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define GAP_PRINT_INFO7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GAP, LEVEL_INFO, "!**"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define GAP_PRINT_INFO8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GAP, LEVEL_INFO, "!**"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define GAP_PRINT_TRACE0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GAP, LEVEL_TRACE, fmt, 0)
+#define GAP_PRINT_TRACE1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GAP, LEVEL_TRACE, fmt, 1, arg0)
+#define GAP_PRINT_TRACE2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GAP, LEVEL_TRACE, fmt, 2, arg0, arg1)
+#define GAP_PRINT_TRACE3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GAP, LEVEL_TRACE, fmt, 3, arg0, arg1, arg2)
+#define GAP_PRINT_TRACE4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GAP, LEVEL_TRACE, fmt, 4, arg0, arg1, arg2, arg3)
+#define GAP_PRINT_TRACE5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GAP, LEVEL_TRACE, fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define GAP_PRINT_TRACE6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GAP, LEVEL_TRACE, fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define GAP_PRINT_TRACE7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GAP, LEVEL_TRACE, fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define GAP_PRINT_TRACE8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GAP, LEVEL_TRACE, fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+
+
+/* Bluetooth RFCOMM Trace Interfaces */
+#define RFCOMM_PRINT_ERROR0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_RFCOMM, LEVEL_ERROR, "!!!"fmt, 0)
+#define RFCOMM_PRINT_ERROR1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_RFCOMM, LEVEL_ERROR, "!!!"fmt, 1, arg0)
+#define RFCOMM_PRINT_ERROR2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_RFCOMM, LEVEL_ERROR, "!!!"fmt, 2, arg0, arg1)
+#define RFCOMM_PRINT_ERROR3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_RFCOMM, LEVEL_ERROR, "!!!"fmt, 3, arg0, arg1, arg2)
+#define RFCOMM_PRINT_ERROR4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_RFCOMM, LEVEL_ERROR, "!!!"fmt, 4, arg0, arg1, arg2, arg3)
+#define RFCOMM_PRINT_ERROR5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_RFCOMM, LEVEL_ERROR, "!!!"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define RFCOMM_PRINT_ERROR6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_RFCOMM, LEVEL_ERROR, "!!!"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define RFCOMM_PRINT_ERROR7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_RFCOMM, LEVEL_ERROR, "!!!"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define RFCOMM_PRINT_ERROR8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_RFCOMM, LEVEL_ERROR, "!!!"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define RFCOMM_PRINT_WARN0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_RFCOMM, LEVEL_WARN, "!!*"fmt, 0)
+#define RFCOMM_PRINT_WARN1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_RFCOMM, LEVEL_WARN, "!!*"fmt, 1, arg0)
+#define RFCOMM_PRINT_WARN2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_RFCOMM, LEVEL_WARN, "!!*"fmt, 2, arg0, arg1)
+#define RFCOMM_PRINT_WARN3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_RFCOMM, LEVEL_WARN, "!!*"fmt, 3, arg0, arg1, arg2)
+#define RFCOMM_PRINT_WARN4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_RFCOMM, LEVEL_WARN, "!!*"fmt, 4, arg0, arg1, arg2, arg3)
+#define RFCOMM_PRINT_WARN5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_RFCOMM, LEVEL_WARN, "!!*"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define RFCOMM_PRINT_WARN6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_RFCOMM, LEVEL_WARN, "!!*"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define RFCOMM_PRINT_WARN7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_RFCOMM, LEVEL_WARN, "!!*"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define RFCOMM_PRINT_WARN8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_RFCOMM, LEVEL_WARN, "!!*"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define RFCOMM_PRINT_INFO0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_RFCOMM, LEVEL_INFO, "!**"fmt, 0)
+#define RFCOMM_PRINT_INFO1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_RFCOMM, LEVEL_INFO, "!**"fmt, 1, arg0)
+#define RFCOMM_PRINT_INFO2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_RFCOMM, LEVEL_INFO, "!**"fmt, 2, arg0, arg1)
+#define RFCOMM_PRINT_INFO3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_RFCOMM, LEVEL_INFO, "!**"fmt, 3, arg0, arg1, arg2)
+#define RFCOMM_PRINT_INFO4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_RFCOMM, LEVEL_INFO, "!**"fmt, 4, arg0, arg1, arg2, arg3)
+#define RFCOMM_PRINT_INFO5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_RFCOMM, LEVEL_INFO, "!**"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define RFCOMM_PRINT_INFO6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_RFCOMM, LEVEL_INFO, "!**"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define RFCOMM_PRINT_INFO7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_RFCOMM, LEVEL_INFO, "!**"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define RFCOMM_PRINT_INFO8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_RFCOMM, LEVEL_INFO, "!**"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define RFCOMM_PRINT_TRACE0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_RFCOMM, LEVEL_TRACE, fmt, 0)
+#define RFCOMM_PRINT_TRACE1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_RFCOMM, LEVEL_TRACE, fmt, 1, arg0)
+#define RFCOMM_PRINT_TRACE2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_RFCOMM, LEVEL_TRACE, fmt, 2, arg0, arg1)
+#define RFCOMM_PRINT_TRACE3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_RFCOMM, LEVEL_TRACE, fmt, 3, arg0, arg1, arg2)
+#define RFCOMM_PRINT_TRACE4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_RFCOMM, LEVEL_TRACE, fmt, 4, arg0, arg1, arg2, arg3)
+#define RFCOMM_PRINT_TRACE5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_RFCOMM, LEVEL_TRACE, fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define RFCOMM_PRINT_TRACE6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_RFCOMM, LEVEL_TRACE, fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define RFCOMM_PRINT_TRACE7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_RFCOMM, LEVEL_TRACE, fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define RFCOMM_PRINT_TRACE8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_RFCOMM, LEVEL_TRACE, fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+
+
+/* Bluetooth Protocol Trace Interfaces */
+#define PROTOCOL_PRINT_ERROR0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROTOCOL, LEVEL_ERROR, "!!!"fmt, 0)
+#define PROTOCOL_PRINT_ERROR1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROTOCOL, LEVEL_ERROR, "!!!"fmt, 1, arg0)
+#define PROTOCOL_PRINT_ERROR2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROTOCOL, LEVEL_ERROR, "!!!"fmt, 2, arg0, arg1)
+#define PROTOCOL_PRINT_ERROR3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROTOCOL, LEVEL_ERROR, "!!!"fmt, 3, arg0, arg1, arg2)
+#define PROTOCOL_PRINT_ERROR4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROTOCOL, LEVEL_ERROR, "!!!"fmt, 4, arg0, arg1, arg2, arg3)
+#define PROTOCOL_PRINT_ERROR5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROTOCOL, LEVEL_ERROR, "!!!"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define PROTOCOL_PRINT_ERROR6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROTOCOL, LEVEL_ERROR, "!!!"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define PROTOCOL_PRINT_ERROR7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROTOCOL, LEVEL_ERROR, "!!!"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define PROTOCOL_PRINT_ERROR8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROTOCOL, LEVEL_ERROR, "!!!"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define PROTOCOL_PRINT_WARN0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROTOCOL, LEVEL_WARN, "!!*"fmt, 0)
+#define PROTOCOL_PRINT_WARN1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROTOCOL, LEVEL_WARN, "!!*"fmt, 1, arg0)
+#define PROTOCOL_PRINT_WARN2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROTOCOL, LEVEL_WARN, "!!*"fmt, 2, arg0, arg1)
+#define PROTOCOL_PRINT_WARN3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROTOCOL, LEVEL_WARN, "!!*"fmt, 3, arg0, arg1, arg2)
+#define PROTOCOL_PRINT_WARN4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROTOCOL, LEVEL_WARN, "!!*"fmt, 4, arg0, arg1, arg2, arg3)
+#define PROTOCOL_PRINT_WARN5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROTOCOL, LEVEL_WARN, "!!*"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define PROTOCOL_PRINT_WARN6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROTOCOL, LEVEL_WARN, "!!*"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define PROTOCOL_PRINT_WARN7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROTOCOL, LEVEL_WARN, "!!*"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define PROTOCOL_PRINT_WARN8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROTOCOL, LEVEL_WARN, "!!*"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define PROTOCOL_PRINT_INFO0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROTOCOL, LEVEL_INFO, "!**"fmt, 0)
+#define PROTOCOL_PRINT_INFO1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROTOCOL, LEVEL_INFO, "!**"fmt, 1, arg0)
+#define PROTOCOL_PRINT_INFO2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROTOCOL, LEVEL_INFO, "!**"fmt, 2, arg0, arg1)
+#define PROTOCOL_PRINT_INFO3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROTOCOL, LEVEL_INFO, "!**"fmt, 3, arg0, arg1, arg2)
+#define PROTOCOL_PRINT_INFO4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROTOCOL, LEVEL_INFO, "!**"fmt, 4, arg0, arg1, arg2, arg3)
+#define PROTOCOL_PRINT_INFO5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROTOCOL, LEVEL_INFO, "!**"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define PROTOCOL_PRINT_INFO6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROTOCOL, LEVEL_INFO, "!**"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define PROTOCOL_PRINT_INFO7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROTOCOL, LEVEL_INFO, "!**"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define PROTOCOL_PRINT_INFO8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROTOCOL, LEVEL_INFO, "!**"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define PROTOCOL_PRINT_TRACE0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROTOCOL, LEVEL_TRACE, fmt, 0)
+#define PROTOCOL_PRINT_TRACE1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROTOCOL, LEVEL_TRACE, fmt, 1, arg0)
+#define PROTOCOL_PRINT_TRACE2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROTOCOL, LEVEL_TRACE, fmt, 2, arg0, arg1)
+#define PROTOCOL_PRINT_TRACE3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROTOCOL, LEVEL_TRACE, fmt, 3, arg0, arg1, arg2)
+#define PROTOCOL_PRINT_TRACE4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROTOCOL, LEVEL_TRACE, fmt, 4, arg0, arg1, arg2, arg3)
+#define PROTOCOL_PRINT_TRACE5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROTOCOL, LEVEL_TRACE, fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define PROTOCOL_PRINT_TRACE6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROTOCOL, LEVEL_TRACE, fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define PROTOCOL_PRINT_TRACE7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROTOCOL, LEVEL_TRACE, fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define PROTOCOL_PRINT_TRACE8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROTOCOL, LEVEL_TRACE, fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+
+
+/* Bluetooth Profile Trace Interfaces */
+#define PROFILE_PRINT_ERROR0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROFILE, LEVEL_ERROR, "!!!"fmt, 0)
+#define PROFILE_PRINT_ERROR1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROFILE, LEVEL_ERROR, "!!!"fmt, 1, arg0)
+#define PROFILE_PRINT_ERROR2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROFILE, LEVEL_ERROR, "!!!"fmt, 2, arg0, arg1)
+#define PROFILE_PRINT_ERROR3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROFILE, LEVEL_ERROR, "!!!"fmt, 3, arg0, arg1, arg2)
+#define PROFILE_PRINT_ERROR4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROFILE, LEVEL_ERROR, "!!!"fmt, 4, arg0, arg1, arg2, arg3)
+#define PROFILE_PRINT_ERROR5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROFILE, LEVEL_ERROR, "!!!"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define PROFILE_PRINT_ERROR6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROFILE, LEVEL_ERROR, "!!!"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define PROFILE_PRINT_ERROR7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROFILE, LEVEL_ERROR, "!!!"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define PROFILE_PRINT_ERROR8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROFILE, LEVEL_ERROR, "!!!"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define PROFILE_PRINT_WARN0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROFILE, LEVEL_WARN, "!!*"fmt, 0)
+#define PROFILE_PRINT_WARN1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROFILE, LEVEL_WARN, "!!*"fmt, 1, arg0)
+#define PROFILE_PRINT_WARN2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROFILE, LEVEL_WARN, "!!*"fmt, 2, arg0, arg1)
+#define PROFILE_PRINT_WARN3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROFILE, LEVEL_WARN, "!!*"fmt, 3, arg0, arg1, arg2)
+#define PROFILE_PRINT_WARN4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROFILE, LEVEL_WARN, "!!*"fmt, 4, arg0, arg1, arg2, arg3)
+#define PROFILE_PRINT_WARN5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROFILE, LEVEL_WARN, "!!*"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define PROFILE_PRINT_WARN6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROFILE, LEVEL_WARN, "!!*"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define PROFILE_PRINT_WARN7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROFILE, LEVEL_WARN, "!!*"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define PROFILE_PRINT_WARN8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROFILE, LEVEL_WARN, "!!*"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define PROFILE_PRINT_INFO0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROFILE, LEVEL_INFO, "!**"fmt, 0)
+#define PROFILE_PRINT_INFO1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROFILE, LEVEL_INFO, "!**"fmt, 1, arg0)
+#define PROFILE_PRINT_INFO2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROFILE, LEVEL_INFO, "!**"fmt, 2, arg0, arg1)
+#define PROFILE_PRINT_INFO3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROFILE, LEVEL_INFO, "!**"fmt, 3, arg0, arg1, arg2)
+#define PROFILE_PRINT_INFO4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROFILE, LEVEL_INFO, "!**"fmt, 4, arg0, arg1, arg2, arg3)
+#define PROFILE_PRINT_INFO5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROFILE, LEVEL_INFO, "!**"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define PROFILE_PRINT_INFO6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROFILE, LEVEL_INFO, "!**"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define PROFILE_PRINT_INFO7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROFILE, LEVEL_INFO, "!**"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define PROFILE_PRINT_INFO8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROFILE, LEVEL_INFO, "!**"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define PROFILE_PRINT_TRACE0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROFILE, LEVEL_TRACE, fmt, 0)
+#define PROFILE_PRINT_TRACE1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROFILE, LEVEL_TRACE, fmt, 1, arg0)
+#define PROFILE_PRINT_TRACE2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROFILE, LEVEL_TRACE, fmt, 2, arg0, arg1)
+#define PROFILE_PRINT_TRACE3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROFILE, LEVEL_TRACE, fmt, 3, arg0, arg1, arg2)
+#define PROFILE_PRINT_TRACE4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROFILE, LEVEL_TRACE, fmt, 4, arg0, arg1, arg2, arg3)
+#define PROFILE_PRINT_TRACE5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROFILE, LEVEL_TRACE, fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define PROFILE_PRINT_TRACE6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROFILE, LEVEL_TRACE, fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define PROFILE_PRINT_TRACE7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROFILE, LEVEL_TRACE, fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define PROFILE_PRINT_TRACE8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PROFILE, LEVEL_TRACE, fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+
+/**
+ * trace.h
+ *
+ * \name    SHM_PRINT_TRACE
+ * \brief   SHM Trace Interfaces.
+ * \anchor  SHM_PRINT_TRACE
+ */
+/**
+ * \ingroup TRACE
+ */
+/**@{*/
+#define SHM_PRINT_ERROR0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SHM, LEVEL_ERROR, "!!!"fmt, 0)
+#define SHM_PRINT_ERROR1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SHM, LEVEL_ERROR, "!!!"fmt, 1, arg0)
+#define SHM_PRINT_ERROR2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SHM, LEVEL_ERROR, "!!!"fmt, 2, arg0, arg1)
+#define SHM_PRINT_ERROR3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SHM, LEVEL_ERROR, "!!!"fmt, 3, arg0, arg1, arg2)
+#define SHM_PRINT_ERROR4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SHM, LEVEL_ERROR, "!!!"fmt, 4, arg0, arg1, arg2, arg3)
+#define SHM_PRINT_ERROR5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SHM, LEVEL_ERROR, "!!!"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define SHM_PRINT_ERROR6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SHM, LEVEL_ERROR, "!!!"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define SHM_PRINT_ERROR7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SHM, LEVEL_ERROR, "!!!"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define SHM_PRINT_ERROR8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SHM, LEVEL_ERROR, "!!!"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define SHM_PRINT_WARN0(fmt)     \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SHM, LEVEL_WARN, "!!*"fmt, 0)
+#define SHM_PRINT_WARN1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SHM, LEVEL_WARN, "!!*"fmt, 1, arg0)
+#define SHM_PRINT_WARN2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SHM, LEVEL_WARN, "!!*"fmt, 2, arg0, arg1)
+#define SHM_PRINT_WARN3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SHM, LEVEL_WARN, "!!*"fmt, 3, arg0, arg1, arg2)
+#define SHM_PRINT_WARN4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SHM, LEVEL_WARN, "!!*"fmt, 4, arg0, arg1, arg2, arg3)
+#define SHM_PRINT_WARN5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SHM, LEVEL_WARN, "!!*"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define SHM_PRINT_WARN6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SHM, LEVEL_WARN, "!!*"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define SHM_PRINT_WARN7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SHM, LEVEL_WARN, "!!*"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define SHM_PRINT_WARN8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SHM, LEVEL_WARN, "!!*"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define SHM_PRINT_INFO0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SHM, LEVEL_INFO, "!**"fmt, 0)
+#define SHM_PRINT_INFO1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SHM, LEVEL_INFO, "!**"fmt, 1, arg0)
+#define SHM_PRINT_INFO2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SHM, LEVEL_INFO, "!**"fmt, 2, arg0, arg1)
+#define SHM_PRINT_INFO3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SHM, LEVEL_INFO, "!**"fmt, 3, arg0, arg1, arg2)
+#define SHM_PRINT_INFO4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SHM, LEVEL_INFO, "!**"fmt, 4, arg0, arg1, arg2, arg3)
+#define SHM_PRINT_INFO5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SHM, LEVEL_INFO, "!**"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define SHM_PRINT_INFO6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SHM, LEVEL_INFO, "!**"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define SHM_PRINT_INFO7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SHM, LEVEL_INFO, "!**"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define SHM_PRINT_INFO8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SHM, LEVEL_INFO, "!**"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define SHM_PRINT_TRACE0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SHM, LEVEL_TRACE, fmt, 0)
+#define SHM_PRINT_TRACE1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SHM, LEVEL_TRACE, fmt, 1, arg0)
+#define SHM_PRINT_TRACE2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SHM, LEVEL_TRACE, fmt, 2, arg0, arg1)
+#define SHM_PRINT_TRACE3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SHM, LEVEL_TRACE, fmt, 3, arg0, arg1, arg2)
+#define SHM_PRINT_TRACE4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SHM, LEVEL_TRACE, fmt, 4, arg0, arg1, arg2, arg3)
+#define SHM_PRINT_TRACE5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SHM, LEVEL_TRACE, fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define SHM_PRINT_TRACE6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SHM, LEVEL_TRACE, fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define SHM_PRINT_TRACE7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SHM, LEVEL_TRACE, fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define SHM_PRINT_TRACE8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SHM, LEVEL_TRACE, fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+/**@}*/
+
+/**
+ * trace.h
+ *
+ * \name    LOADER_PRINT_TRACE
+ * \brief   BINLOADER Trace Interfaces.
+ * \anchor  BINLOADER_PRINT_TRACE
+ */
+/**
+ * \ingroup TRACE
+ */
+/**@{*/
+#define LOADER_PRINT_ERROR0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_LOADER, LEVEL_ERROR, "!!!"fmt, 0)
+#define LOADER_PRINT_ERROR1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_LOADER, LEVEL_ERROR, "!!!"fmt, 1, arg0)
+#define LOADER_PRINT_ERROR2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_LOADER, LEVEL_ERROR, "!!!"fmt, 2, arg0, arg1)
+#define LOADER_PRINT_ERROR3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_LOADER, LEVEL_ERROR, "!!!"fmt, 3, arg0, arg1, arg2)
+#define LOADER_PRINT_ERROR4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_LOADER, LEVEL_ERROR, "!!!"fmt, 4, arg0, arg1, arg2, arg3)
+#define LOADER_PRINT_ERROR5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_LOADER, LEVEL_ERROR, "!!!"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define LOADER_PRINT_ERROR6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_LOADER, LEVEL_ERROR, "!!!"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define LOADER_PRINT_ERROR7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_LOADER, LEVEL_ERROR, "!!!"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define LOADER_PRINT_ERROR8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_LOADER, LEVEL_ERROR, "!!!"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define LOADER_PRINT_WARN0(fmt)     \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_LOADER, LEVEL_WARN, "!!*"fmt, 0)
+#define LOADER_PRINT_WARN1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_LOADER, LEVEL_WARN, "!!*"fmt, 1, arg0)
+#define LOADER_PRINT_WARN2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_LOADER, LEVEL_WARN, "!!*"fmt, 2, arg0, arg1)
+#define LOADER_PRINT_WARN3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_LOADER, LEVEL_WARN, "!!*"fmt, 3, arg0, arg1, arg2)
+#define LOADER_PRINT_WARN4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_LOADER, LEVEL_WARN, "!!*"fmt, 4, arg0, arg1, arg2, arg3)
+#define LOADER_PRINT_WARN5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_LOADER, LEVEL_WARN, "!!*"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define LOADER_PRINT_WARN6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_LOADER, LEVEL_WARN, "!!*"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define LOADER_PRINT_WARN7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_LOADER, LEVEL_WARN, "!!*"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define LOADER_PRINT_WARN8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_LOADER, LEVEL_WARN, "!!*"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define LOADER_PRINT_INFO0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_LOADER, LEVEL_INFO, "!**"fmt, 0)
+#define LOADER_PRINT_INFO1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_LOADER, LEVEL_INFO, "!**"fmt, 1, arg0)
+#define LOADER_PRINT_INFO2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_LOADER, LEVEL_INFO, "!**"fmt, 2, arg0, arg1)
+#define LOADER_PRINT_INFO3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_LOADER, LEVEL_INFO, "!**"fmt, 3, arg0, arg1, arg2)
+#define LOADER_PRINT_INFO4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_LOADER, LEVEL_INFO, "!**"fmt, 4, arg0, arg1, arg2, arg3)
+#define LOADER_PRINT_INFO5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_LOADER, LEVEL_INFO, "!**"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define LOADER_PRINT_INFO6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_LOADER, LEVEL_INFO, "!**"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define LOADER_PRINT_INFO7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_LOADER, LEVEL_INFO, "!**"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define LOADER_PRINT_INFO8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_LOADER, LEVEL_INFO, "!**"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define LOADER_PRINT_TRACE0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_LOADER, LEVEL_TRACE, fmt, 0)
+#define LOADER_PRINT_TRACE1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_LOADER, LEVEL_TRACE, fmt, 1, arg0)
+#define LOADER_PRINT_TRACE2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_LOADER, LEVEL_TRACE, fmt, 2, arg0, arg1)
+#define LOADER_PRINT_TRACE3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_LOADER, LEVEL_TRACE, fmt, 3, arg0, arg1, arg2)
+#define LOADER_PRINT_TRACE4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_LOADER, LEVEL_TRACE, fmt, 4, arg0, arg1, arg2, arg3)
+#define LOADER_PRINT_TRACE5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_LOADER, LEVEL_TRACE, fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define LOADER_PRINT_TRACE6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_LOADER, LEVEL_TRACE, fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define LOADER_PRINT_TRACE7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_LOADER, LEVEL_TRACE, fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define LOADER_PRINT_TRACE8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_LOADER, LEVEL_TRACE, fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+/**@}*/
+
+
+/**
+ * trace.h
+ *
+ * \name    THREAD_PRINT_TRACE
+ * \brief   THREAD Trace Interfaces.
+ * \anchor  THREAD_PRINT_TRACE
+ */
+/**
+ * \ingroup TRACE
+ */
+/**@{*/
+#define THREAD_PRINT_ERROR0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_THREAD, LEVEL_ERROR, "!!!"fmt, 0)
+#define THREAD_PRINT_ERROR1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_THREAD, LEVEL_ERROR, "!!!"fmt, 1, arg0)
+#define THREAD_PRINT_ERROR2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_THREAD, LEVEL_ERROR, "!!!"fmt, 2, arg0, arg1)
+#define THREAD_PRINT_ERROR3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_THREAD, LEVEL_ERROR, "!!!"fmt, 3, arg0, arg1, arg2)
+#define THREAD_PRINT_ERROR4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_THREAD, LEVEL_ERROR, "!!!"fmt, 4, arg0, arg1, arg2, arg3)
+#define THREAD_PRINT_ERROR5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_THREAD, LEVEL_ERROR, "!!!"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define THREAD_PRINT_ERROR6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_THREAD, LEVEL_ERROR, "!!!"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define THREAD_PRINT_ERROR7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_THREAD, LEVEL_ERROR, "!!!"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define THREAD_PRINT_ERROR8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_THREAD, LEVEL_ERROR, "!!!"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define THREAD_PRINT_WARN0(fmt)     \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_THREAD, LEVEL_WARN, "!!*"fmt, 0)
+#define THREAD_PRINT_WARN1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_THREAD, LEVEL_WARN, "!!*"fmt, 1, arg0)
+#define THREAD_PRINT_WARN2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_THREAD, LEVEL_WARN, "!!*"fmt, 2, arg0, arg1)
+#define THREAD_PRINT_WARN3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_THREAD, LEVEL_WARN, "!!*"fmt, 3, arg0, arg1, arg2)
+#define THREAD_PRINT_WARN4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_THREAD, LEVEL_WARN, "!!*"fmt, 4, arg0, arg1, arg2, arg3)
+#define THREAD_PRINT_WARN5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_THREAD, LEVEL_WARN, "!!*"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define THREAD_PRINT_WARN6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_THREAD, LEVEL_WARN, "!!*"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define THREAD_PRINT_WARN7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_THREAD, LEVEL_WARN, "!!*"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define THREAD_PRINT_WARN8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_THREAD, LEVEL_WARN, "!!*"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define THREAD_PRINT_INFO0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_THREAD, LEVEL_INFO, "!**"fmt, 0)
+#define THREAD_PRINT_INFO1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_THREAD, LEVEL_INFO, "!**"fmt, 1, arg0)
+#define THREAD_PRINT_INFO2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_THREAD, LEVEL_INFO, "!**"fmt, 2, arg0, arg1)
+#define THREAD_PRINT_INFO3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_THREAD, LEVEL_INFO, "!**"fmt, 3, arg0, arg1, arg2)
+#define THREAD_PRINT_INFO4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_THREAD, LEVEL_INFO, "!**"fmt, 4, arg0, arg1, arg2, arg3)
+#define THREAD_PRINT_INFO5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_THREAD, LEVEL_INFO, "!**"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define THREAD_PRINT_INFO6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_THREAD, LEVEL_INFO, "!**"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define THREAD_PRINT_INFO7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_THREAD, LEVEL_INFO, "!**"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define THREAD_PRINT_INFO8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_THREAD, LEVEL_INFO, "!**"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define THREAD_PRINT_TRACE0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_THREAD, LEVEL_TRACE, fmt, 0)
+#define THREAD_PRINT_TRACE1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_THREAD, LEVEL_TRACE, fmt, 1, arg0)
+#define THREAD_PRINT_TRACE2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_THREAD, LEVEL_TRACE, fmt, 2, arg0, arg1)
+#define THREAD_PRINT_TRACE3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_THREAD, LEVEL_TRACE, fmt, 3, arg0, arg1, arg2)
+#define THREAD_PRINT_TRACE4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_THREAD, LEVEL_TRACE, fmt, 4, arg0, arg1, arg2, arg3)
+#define THREAD_PRINT_TRACE5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_THREAD, LEVEL_TRACE, fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define THREAD_PRINT_TRACE6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_THREAD, LEVEL_TRACE, fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define THREAD_PRINT_TRACE7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_THREAD, LEVEL_TRACE, fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define THREAD_PRINT_TRACE8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_THREAD, LEVEL_TRACE, fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+/**@}*/
+
+
+/**
+ * trace.h
+ *
+ * \name    MATTER_PRINT_TRACE
+ * \brief   MATTER Trace Interfaces.
+ * \anchor  MATTER_PRINT_TRACE
+ */
+/**
+ * \ingroup TRACE
+ */
+/**@{*/
+#define MATTER_PRINT_ERROR0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_MATTER, LEVEL_ERROR, "!!!"fmt, 0)
+#define MATTER_PRINT_ERROR1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_MATTER, LEVEL_ERROR, "!!!"fmt, 1, arg0)
+#define MATTER_PRINT_ERROR2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_MATTER, LEVEL_ERROR, "!!!"fmt, 2, arg0, arg1)
+#define MATTER_PRINT_ERROR3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_MATTER, LEVEL_ERROR, "!!!"fmt, 3, arg0, arg1, arg2)
+#define MATTER_PRINT_ERROR4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_MATTER, LEVEL_ERROR, "!!!"fmt, 4, arg0, arg1, arg2, arg3)
+#define MATTER_PRINT_ERROR5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_MATTER, LEVEL_ERROR, "!!!"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define MATTER_PRINT_ERROR6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_MATTER, LEVEL_ERROR, "!!!"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define MATTER_PRINT_ERROR7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_MATTER, LEVEL_ERROR, "!!!"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define MATTER_PRINT_ERROR8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_MATTER, LEVEL_ERROR, "!!!"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define MATTER_PRINT_WARN0(fmt)     \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_MATTER, LEVEL_WARN, "!!*"fmt, 0)
+#define MATTER_PRINT_WARN1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_MATTER, LEVEL_WARN, "!!*"fmt, 1, arg0)
+#define MATTER_PRINT_WARN2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_MATTER, LEVEL_WARN, "!!*"fmt, 2, arg0, arg1)
+#define MATTER_PRINT_WARN3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_MATTER, LEVEL_WARN, "!!*"fmt, 3, arg0, arg1, arg2)
+#define MATTER_PRINT_WARN4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_MATTER, LEVEL_WARN, "!!*"fmt, 4, arg0, arg1, arg2, arg3)
+#define MATTER_PRINT_WARN5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_MATTER, LEVEL_WARN, "!!*"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define MATTER_PRINT_WARN6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_MATTER, LEVEL_WARN, "!!*"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define MATTER_PRINT_WARN7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_MATTER, LEVEL_WARN, "!!*"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define MATTER_PRINT_WARN8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_MATTER, LEVEL_WARN, "!!*"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define MATTER_PRINT_INFO0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_MATTER, LEVEL_INFO, "!**"fmt, 0)
+#define MATTER_PRINT_INFO1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_MATTER, LEVEL_INFO, "!**"fmt, 1, arg0)
+#define MATTER_PRINT_INFO2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_MATTER, LEVEL_INFO, "!**"fmt, 2, arg0, arg1)
+#define MATTER_PRINT_INFO3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_MATTER, LEVEL_INFO, "!**"fmt, 3, arg0, arg1, arg2)
+#define MATTER_PRINT_INFO4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_MATTER, LEVEL_INFO, "!**"fmt, 4, arg0, arg1, arg2, arg3)
+#define MATTER_PRINT_INFO5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_MATTER, LEVEL_INFO, "!**"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define MATTER_PRINT_INFO6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_MATTER, LEVEL_INFO, "!**"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define MATTER_PRINT_INFO7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_MATTER, LEVEL_INFO, "!**"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define MATTER_PRINT_INFO8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_MATTER, LEVEL_INFO, "!**"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define MATTER_PRINT_TRACE0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_MATTER, LEVEL_TRACE, fmt, 0)
+#define MATTER_PRINT_TRACE1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_MATTER, LEVEL_TRACE, fmt, 1, arg0)
+#define MATTER_PRINT_TRACE2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_MATTER, LEVEL_TRACE, fmt, 2, arg0, arg1)
+#define MATTER_PRINT_TRACE3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_MATTER, LEVEL_TRACE, fmt, 3, arg0, arg1, arg2)
+#define MATTER_PRINT_TRACE4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_MATTER, LEVEL_TRACE, fmt, 4, arg0, arg1, arg2, arg3)
+#define MATTER_PRINT_TRACE5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_MATTER, LEVEL_TRACE, fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define MATTER_PRINT_TRACE6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_MATTER, LEVEL_TRACE, fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define MATTER_PRINT_TRACE7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_MATTER, LEVEL_TRACE, fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define MATTER_PRINT_TRACE8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_MATTER, LEVEL_TRACE, fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+/**@}*/
+
+
+/**
+ * trace.h
+ *
+ * \name    ZIGBEE_PRINT_TRACE
+ * \brief   ZIGBEE Trace Interfaces.
+ * \anchor  ZIGBEE_PRINT_TRACE
+ */
+/**
+ * \ingroup TRACE
+ */
+/**@{*/
+#define ZIGBEE_PRINT_ERROR0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_ZIGBEE, LEVEL_ERROR, "!!!"fmt, 0)
+#define ZIGBEE_PRINT_ERROR1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_ZIGBEE, LEVEL_ERROR, "!!!"fmt, 1, arg0)
+#define ZIGBEE_PRINT_ERROR2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_ZIGBEE, LEVEL_ERROR, "!!!"fmt, 2, arg0, arg1)
+#define ZIGBEE_PRINT_ERROR3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_ZIGBEE, LEVEL_ERROR, "!!!"fmt, 3, arg0, arg1, arg2)
+#define ZIGBEE_PRINT_ERROR4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_ZIGBEE, LEVEL_ERROR, "!!!"fmt, 4, arg0, arg1, arg2, arg3)
+#define ZIGBEE_PRINT_ERROR5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_ZIGBEE, LEVEL_ERROR, "!!!"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define ZIGBEE_PRINT_ERROR6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_ZIGBEE, LEVEL_ERROR, "!!!"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define ZIGBEE_PRINT_ERROR7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_ZIGBEE, LEVEL_ERROR, "!!!"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define ZIGBEE_PRINT_ERROR8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_ZIGBEE, LEVEL_ERROR, "!!!"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define ZIGBEE_PRINT_WARN0(fmt)     \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_ZIGBEE, LEVEL_WARN, "!!*"fmt, 0)
+#define ZIGBEE_PRINT_WARN1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_ZIGBEE, LEVEL_WARN, "!!*"fmt, 1, arg0)
+#define ZIGBEE_PRINT_WARN2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_ZIGBEE, LEVEL_WARN, "!!*"fmt, 2, arg0, arg1)
+#define ZIGBEE_PRINT_WARN3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_ZIGBEE, LEVEL_WARN, "!!*"fmt, 3, arg0, arg1, arg2)
+#define ZIGBEE_PRINT_WARN4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_ZIGBEE, LEVEL_WARN, "!!*"fmt, 4, arg0, arg1, arg2, arg3)
+#define ZIGBEE_PRINT_WARN5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_ZIGBEE, LEVEL_WARN, "!!*"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define ZIGBEE_PRINT_WARN6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_ZIGBEE, LEVEL_WARN, "!!*"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define ZIGBEE_PRINT_WARN7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_ZIGBEE, LEVEL_WARN, "!!*"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define ZIGBEE_PRINT_WARN8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_ZIGBEE, LEVEL_WARN, "!!*"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define ZIGBEE_PRINT_INFO0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_ZIGBEE, LEVEL_INFO, "!**"fmt, 0)
+#define ZIGBEE_PRINT_INFO1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_ZIGBEE, LEVEL_INFO, "!**"fmt, 1, arg0)
+#define ZIGBEE_PRINT_INFO2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_ZIGBEE, LEVEL_INFO, "!**"fmt, 2, arg0, arg1)
+#define ZIGBEE_PRINT_INFO3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_ZIGBEE, LEVEL_INFO, "!**"fmt, 3, arg0, arg1, arg2)
+#define ZIGBEE_PRINT_INFO4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_ZIGBEE, LEVEL_INFO, "!**"fmt, 4, arg0, arg1, arg2, arg3)
+#define ZIGBEE_PRINT_INFO5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_ZIGBEE, LEVEL_INFO, "!**"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define ZIGBEE_PRINT_INFO6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_ZIGBEE, LEVEL_INFO, "!**"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define ZIGBEE_PRINT_INFO7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_ZIGBEE, LEVEL_INFO, "!**"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define ZIGBEE_PRINT_INFO8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_ZIGBEE, LEVEL_INFO, "!**"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define ZIGBEE_PRINT_TRACE0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_ZIGBEE, LEVEL_TRACE, fmt, 0)
+#define ZIGBEE_PRINT_TRACE1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_ZIGBEE, LEVEL_TRACE, fmt, 1, arg0)
+#define ZIGBEE_PRINT_TRACE2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_ZIGBEE, LEVEL_TRACE, fmt, 2, arg0, arg1)
+#define ZIGBEE_PRINT_TRACE3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_ZIGBEE, LEVEL_TRACE, fmt, 3, arg0, arg1, arg2)
+#define ZIGBEE_PRINT_TRACE4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_ZIGBEE, LEVEL_TRACE, fmt, 4, arg0, arg1, arg2, arg3)
+#define ZIGBEE_PRINT_TRACE5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_ZIGBEE, LEVEL_TRACE, fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define ZIGBEE_PRINT_TRACE6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_ZIGBEE, LEVEL_TRACE, fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define ZIGBEE_PRINT_TRACE7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_ZIGBEE, LEVEL_TRACE, fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define ZIGBEE_PRINT_TRACE8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_ZIGBEE, LEVEL_TRACE, fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+/**@}*/
+
+
+/**
+ * trace.h
+ *
+ * \name    APP_PRINT_TRACE
+ * \brief   Bluetooth APP Trace Interfaces.
+ * \anchor  APP_PRINT_TRACE
+ */
+/**
+ * \ingroup TRACE
+ */
+/**@{*/
+#define APP_PRINT_ERROR0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_APP, LEVEL_ERROR, "!!!"fmt, 0)
+#define APP_PRINT_ERROR1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_APP, LEVEL_ERROR, "!!!"fmt, 1, arg0)
+#define APP_PRINT_ERROR2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_APP, LEVEL_ERROR, "!!!"fmt, 2, arg0, arg1)
+#define APP_PRINT_ERROR3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_APP, LEVEL_ERROR, "!!!"fmt, 3, arg0, arg1, arg2)
+#define APP_PRINT_ERROR4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_APP, LEVEL_ERROR, "!!!"fmt, 4, arg0, arg1, arg2, arg3)
+#define APP_PRINT_ERROR5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_APP, LEVEL_ERROR, "!!!"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define APP_PRINT_ERROR6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_APP, LEVEL_ERROR, "!!!"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define APP_PRINT_ERROR7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_APP, LEVEL_ERROR, "!!!"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define APP_PRINT_ERROR8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_APP, LEVEL_ERROR, "!!!"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define APP_PRINT_WARN0(fmt)     \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_APP, LEVEL_WARN, "!!*"fmt, 0)
+#define APP_PRINT_WARN1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_APP, LEVEL_WARN, "!!*"fmt, 1, arg0)
+#define APP_PRINT_WARN2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_APP, LEVEL_WARN, "!!*"fmt, 2, arg0, arg1)
+#define APP_PRINT_WARN3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_APP, LEVEL_WARN, "!!*"fmt, 3, arg0, arg1, arg2)
+#define APP_PRINT_WARN4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_APP, LEVEL_WARN, "!!*"fmt, 4, arg0, arg1, arg2, arg3)
+#define APP_PRINT_WARN5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_APP, LEVEL_WARN, "!!*"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define APP_PRINT_WARN6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_APP, LEVEL_WARN, "!!*"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define APP_PRINT_WARN7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_APP, LEVEL_WARN, "!!*"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define APP_PRINT_WARN8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_APP, LEVEL_WARN, "!!*"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define APP_PRINT_INFO0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_APP, LEVEL_INFO, "!**"fmt, 0)
+#define APP_PRINT_INFO1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_APP, LEVEL_INFO, "!**"fmt, 1, arg0)
+#define APP_PRINT_INFO2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_APP, LEVEL_INFO, "!**"fmt, 2, arg0, arg1)
+#define APP_PRINT_INFO3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_APP, LEVEL_INFO, "!**"fmt, 3, arg0, arg1, arg2)
+#define APP_PRINT_INFO4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_APP, LEVEL_INFO, "!**"fmt, 4, arg0, arg1, arg2, arg3)
+#define APP_PRINT_INFO5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_APP, LEVEL_INFO, "!**"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define APP_PRINT_INFO6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_APP, LEVEL_INFO, "!**"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define APP_PRINT_INFO7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_APP, LEVEL_INFO, "!**"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define APP_PRINT_INFO8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_APP, LEVEL_INFO, "!**"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define APP_PRINT_TRACE0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_APP, LEVEL_TRACE, fmt, 0)
+#define APP_PRINT_TRACE1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_APP, LEVEL_TRACE, fmt, 1, arg0)
+#define APP_PRINT_TRACE2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_APP, LEVEL_TRACE, fmt, 2, arg0, arg1)
+#define APP_PRINT_TRACE3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_APP, LEVEL_TRACE, fmt, 3, arg0, arg1, arg2)
+#define APP_PRINT_TRACE4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_APP, LEVEL_TRACE, fmt, 4, arg0, arg1, arg2, arg3)
+#define APP_PRINT_TRACE5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_APP, LEVEL_TRACE, fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define APP_PRINT_TRACE6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_APP, LEVEL_TRACE, fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define APP_PRINT_TRACE7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_APP, LEVEL_TRACE, fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define APP_PRINT_TRACE8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_APP, LEVEL_TRACE, fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+/**@}*/
+
+
+/**
+ * trace.h
+ *
+ * \name    CONSOLE_PRINT_TRACE
+ * \brief   Console Trace Interfaces.
+ * \anchor  CONSOLE_PRINT_TRACE
+ */
+/**
+ * \ingroup TRACE
+ */
+/**@{*/
+#define CONSOLE_PRINT_ERROR0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_TEXT, MODULE_CONSOLE, LEVEL_ERROR, "!!!"fmt)
+#define CONSOLE_PRINT_ERROR1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_TEXT, MODULE_CONSOLE, LEVEL_ERROR, "!!!"fmt, arg0)
+#define CONSOLE_PRINT_ERROR2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_TEXT, MODULE_CONSOLE, LEVEL_ERROR, "!!!"fmt, arg0, arg1)
+#define CONSOLE_PRINT_ERROR3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_TEXT, MODULE_CONSOLE, LEVEL_ERROR, "!!!"fmt, arg0, arg1, arg2)
+#define CONSOLE_PRINT_ERROR4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_TEXT, MODULE_CONSOLE, LEVEL_ERROR, "!!!"fmt, arg0, arg1, arg2, arg3)
+#define CONSOLE_PRINT_ERROR5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_TEXT, MODULE_CONSOLE, LEVEL_ERROR, "!!!"fmt, arg0, arg1, arg2, arg3, arg4)
+#define CONSOLE_PRINT_ERROR6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_TEXT, MODULE_CONSOLE, LEVEL_ERROR, "!!!"fmt, arg0, arg1, arg2, arg3, arg4, arg5)
+#define CONSOLE_PRINT_ERROR7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_TEXT, MODULE_CONSOLE, LEVEL_ERROR, "!!!"fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define CONSOLE_PRINT_ERROR8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_TEXT, MODULE_CONSOLE, LEVEL_ERROR, "!!!"fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define CONSOLE_PRINT_WARN0(fmt)     \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_TEXT, MODULE_CONSOLE, LEVEL_WARN, "!!*"fmt)
+#define CONSOLE_PRINT_WARN1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_TEXT, MODULE_CONSOLE, LEVEL_WARN, "!!*"fmt, arg0)
+#define CONSOLE_PRINT_WARN2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_TEXT, MODULE_CONSOLE, LEVEL_WARN, "!!*"fmt, arg0, arg1)
+#define CONSOLE_PRINT_WARN3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_TEXT, MODULE_CONSOLE, LEVEL_WARN, "!!*"fmt, arg0, arg1, arg2)
+#define CONSOLE_PRINT_WARN4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_TEXT, MODULE_CONSOLE, LEVEL_WARN, "!!*"fmt, arg0, arg1, arg2, arg3)
+#define CONSOLE_PRINT_WARN5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_TEXT, MODULE_CONSOLE, LEVEL_WARN, "!!*"fmt, arg0, arg1, arg2, arg3, arg4)
+#define CONSOLE_PRINT_WARN6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_TEXT, MODULE_CONSOLE, LEVEL_WARN, "!!*"fmt, arg0, arg1, arg2, arg3, arg4, arg5)
+#define CONSOLE_PRINT_WARN7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_TEXT, MODULE_CONSOLE, LEVEL_WARN, "!!*"fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define CONSOLE_PRINT_WARN8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_TEXT, MODULE_CONSOLE, LEVEL_WARN, "!!*"fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define CONSOLE_PRINT_INFO0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_TEXT, MODULE_CONSOLE, LEVEL_INFO, "!**"fmt)
+#define CONSOLE_PRINT_INFO1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_TEXT, MODULE_CONSOLE, LEVEL_INFO, "!**"fmt, arg0)
+#define CONSOLE_PRINT_INFO2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_TEXT, MODULE_CONSOLE, LEVEL_INFO, "!**"fmt, arg0, arg1)
+#define CONSOLE_PRINT_INFO3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_TEXT, MODULE_CONSOLE, LEVEL_INFO, "!**"fmt, arg0, arg1, arg2)
+#define CONSOLE_PRINT_INFO4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_TEXT, MODULE_CONSOLE, LEVEL_INFO, "!**"fmt, arg0, arg1, arg2, arg3)
+#define CONSOLE_PRINT_INFO5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_TEXT, MODULE_CONSOLE, LEVEL_INFO, "!**"fmt, arg0, arg1, arg2, arg3, arg4)
+#define CONSOLE_PRINT_INFO6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_TEXT, MODULE_CONSOLE, LEVEL_INFO, "!**"fmt, arg0, arg1, arg2, arg3, arg4, arg5)
+#define CONSOLE_PRINT_INFO7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_TEXT, MODULE_CONSOLE, LEVEL_INFO, "!**"fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define CONSOLE_PRINT_INFO8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_TEXT, MODULE_CONSOLE, LEVEL_INFO, "!**"fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define CONSOLE_PRINT_TRACE0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_TEXT, MODULE_CONSOLE, LEVEL_TRACE, fmt)
+#define CONSOLE_PRINT_TRACE1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_TEXT, MODULE_CONSOLE, LEVEL_TRACE, fmt, arg0)
+#define CONSOLE_PRINT_TRACE2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_TEXT, MODULE_CONSOLE, LEVEL_TRACE, fmt, arg0, arg1)
+#define CONSOLE_PRINT_TRACE3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_TEXT, MODULE_CONSOLE, LEVEL_TRACE, fmt, arg0, arg1, arg2)
+#define CONSOLE_PRINT_TRACE4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_TEXT, MODULE_CONSOLE, LEVEL_TRACE, fmt, arg0, arg1, arg2, arg3)
+#define CONSOLE_PRINT_TRACE5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_TEXT, MODULE_CONSOLE, LEVEL_TRACE, fmt, arg0, arg1, arg2, arg3, arg4)
+#define CONSOLE_PRINT_TRACE6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_TEXT, MODULE_CONSOLE, LEVEL_TRACE, fmt, arg0, arg1, arg2, arg3, arg4, arg5)
+#define CONSOLE_PRINT_TRACE7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_TEXT, MODULE_CONSOLE, LEVEL_TRACE, fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define CONSOLE_PRINT_TRACE8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_TEXT, MODULE_CONSOLE, LEVEL_TRACE, fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+/**@}*/
+
+/**
+ * trace.h
+ *
+ * \name    ENGAGE_PRINT_TRACE
+ * \brief   Engage Trace Interfaces.
+ * \anchor  ENGAGE_PRINT_TRACE
+ */
+/**
+ * \ingroup TRACE
+ */
+/**@{*/
+#define ENGAGE_PRINT_ERROR0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_ENGAGE, LEVEL_ERROR, "!!!"fmt, 0)
+#define ENGAGE_PRINT_ERROR1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_ENGAGE, LEVEL_ERROR, "!!!"fmt, 1, arg0)
+#define ENGAGE_PRINT_ERROR2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_ENGAGE, LEVEL_ERROR, "!!!"fmt, 2, arg0, arg1)
+#define ENGAGE_PRINT_ERROR3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_ENGAGE, LEVEL_ERROR, "!!!"fmt, 3, arg0, arg1, arg2)
+#define ENGAGE_PRINT_ERROR4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_ENGAGE, LEVEL_ERROR, "!!!"fmt, 4, arg0, arg1, arg2, arg3)
+#define ENGAGE_PRINT_ERROR5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_ENGAGE, LEVEL_ERROR, "!!!"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define ENGAGE_PRINT_ERROR6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_ENGAGE, LEVEL_ERROR, "!!!"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define ENGAGE_PRINT_ERROR7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_ENGAGE, LEVEL_ERROR, "!!!"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define ENGAGE_PRINT_ERROR8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_ENGAGE, LEVEL_ERROR, "!!!"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define ENGAGE_PRINT_WARN0(fmt)     \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_ENGAGE, LEVEL_WARN, "!!*"fmt, 0)
+#define ENGAGE_PRINT_WARN1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_ENGAGE, LEVEL_WARN, "!!*"fmt, 1, arg0)
+#define ENGAGE_PRINT_WARN2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_ENGAGE, LEVEL_WARN, "!!*"fmt, 2, arg0, arg1)
+#define ENGAGE_PRINT_WARN3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_ENGAGE, LEVEL_WARN, "!!*"fmt, 3, arg0, arg1, arg2)
+#define ENGAGE_PRINT_WARN4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_ENGAGE, LEVEL_WARN, "!!*"fmt, 4, arg0, arg1, arg2, arg3)
+#define ENGAGE_PRINT_WARN5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_ENGAGE, LEVEL_WARN, "!!*"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define ENGAGE_PRINT_WARN6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_ENGAGE, LEVEL_WARN, "!!*"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define ENGAGE_PRINT_WARN7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_ENGAGE, LEVEL_WARN, "!!*"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define ENGAGE_PRINT_WARN8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_ENGAGE, LEVEL_WARN, "!!*"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define ENGAGE_PRINT_INFO0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_ENGAGE, LEVEL_INFO, "!**"fmt, 0)
+#define ENGAGE_PRINT_INFO1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_ENGAGE, LEVEL_INFO, "!**"fmt, 1, arg0)
+#define ENGAGE_PRINT_INFO2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_ENGAGE, LEVEL_INFO, "!**"fmt, 2, arg0, arg1)
+#define ENGAGE_PRINT_INFO3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_ENGAGE, LEVEL_INFO, "!**"fmt, 3, arg0, arg1, arg2)
+#define ENGAGE_PRINT_INFO4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_ENGAGE, LEVEL_INFO, "!**"fmt, 4, arg0, arg1, arg2, arg3)
+#define ENGAGE_PRINT_INFO5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_ENGAGE, LEVEL_INFO, "!**"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define ENGAGE_PRINT_INFO6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_ENGAGE, LEVEL_INFO, "!**"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define ENGAGE_PRINT_INFO7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_ENGAGE, LEVEL_INFO, "!**"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define ENGAGE_PRINT_INFO8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_ENGAGE, LEVEL_INFO, "!**"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define ENGAGE_PRINT_TRACE0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_ENGAGE, LEVEL_TRACE, fmt, 0)
+#define ENGAGE_PRINT_TRACE1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_ENGAGE, LEVEL_TRACE, fmt, 1, arg0)
+#define ENGAGE_PRINT_TRACE2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_ENGAGE, LEVEL_TRACE, fmt, 2, arg0, arg1)
+#define ENGAGE_PRINT_TRACE3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_ENGAGE, LEVEL_TRACE, fmt, 3, arg0, arg1, arg2)
+#define ENGAGE_PRINT_TRACE4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_ENGAGE, LEVEL_TRACE, fmt, 4, arg0, arg1, arg2, arg3)
+#define ENGAGE_PRINT_TRACE5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_ENGAGE, LEVEL_TRACE, fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define ENGAGE_PRINT_TRACE6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_ENGAGE, LEVEL_TRACE, fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define ENGAGE_PRINT_TRACE7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_ENGAGE, LEVEL_TRACE, fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define ENGAGE_PRINT_TRACE8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_ENGAGE, LEVEL_TRACE, fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+/**@}*/
+
+/* AES Trace Interfaces */
+#define AES_PRINT_ERROR0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_AES, LEVEL_ERROR, "!!!"fmt, 0)
+#define AES_PRINT_ERROR1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_AES, LEVEL_ERROR, "!!!"fmt, 1, arg0)
+#define AES_PRINT_ERROR2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_AES, LEVEL_ERROR, "!!!"fmt, 2, arg0, arg1)
+#define AES_PRINT_ERROR3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_AES, LEVEL_ERROR, "!!!"fmt, 3, arg0, arg1, arg2)
+#define AES_PRINT_ERROR4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_AES, LEVEL_ERROR, "!!!"fmt, 4, arg0, arg1, arg2, arg3)
+#define AES_PRINT_WARN0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_AES, LEVEL_WARN, "!!*"fmt, 0)
+#define AES_PRINT_WARN1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_AES, LEVEL_WARN, "!!*"fmt, 1, arg0)
+#define AES_PRINT_WARN2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_AES, LEVEL_WARN, "!!*"fmt, 2, arg0, arg1)
+#define AES_PRINT_WARN3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_AES, LEVEL_WARN, "!!*"fmt, 3, arg0, arg1, arg2)
+#define AES_PRINT_WARN4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_AES, LEVEL_WARN, "!!*"fmt, 4, arg0, arg1, arg2, arg3)
+#define AES_PRINT_INFO0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_AES, LEVEL_INFO, "!**"fmt, 0)
+#define AES_PRINT_INFO1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_AES, LEVEL_INFO, "!**"fmt, 1, arg0)
+#define AES_PRINT_INFO2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_AES, LEVEL_INFO, "!**"fmt, 2, arg0, arg1)
+#define AES_PRINT_INFO3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_AES, LEVEL_INFO, "!**"fmt, 3, arg0, arg1, arg2)
+#define AES_PRINT_INFO4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_AES, LEVEL_INFO, "!**"fmt, 4, arg0, arg1, arg2, arg3)
+
+
+/* Power Manager Trace Interfaces */
+#define PM_PRINT_ERROR0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PM, LEVEL_ERROR, "!!!"fmt, 0)
+#define PM_PRINT_ERROR1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PM, LEVEL_ERROR, "!!!"fmt, 1, arg0)
+#define PM_PRINT_ERROR2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PM, LEVEL_ERROR, "!!!"fmt, 2, arg0, arg1)
+#define PM_PRINT_ERROR3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PM, LEVEL_ERROR, "!!!"fmt, 3, arg0, arg1, arg2)
+#define PM_PRINT_ERROR4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PM, LEVEL_ERROR, "!!!"fmt, 4, arg0, arg1, arg2, arg3)
+#define PM_PRINT_WARN0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PM, LEVEL_WARN, "!!*"fmt, 0)
+#define PM_PRINT_WARN1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PM, LEVEL_WARN, "!!*"fmt, 1, arg0)
+#define PM_PRINT_WARN2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PM, LEVEL_WARN, "!!*"fmt, 2, arg0, arg1)
+#define PM_PRINT_WARN3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PM, LEVEL_WARN, "!!*"fmt, 3, arg0, arg1, arg2)
+#define PM_PRINT_WARN4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PM, LEVEL_WARN, "!!*"fmt, 4, arg0, arg1, arg2, arg3)
+#define PM_PRINT_INFO0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PM, LEVEL_INFO, "!**"fmt, 0)
+#define PM_PRINT_INFO1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PM, LEVEL_INFO, "!**"fmt, 1, arg0)
+#define PM_PRINT_INFO2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PM, LEVEL_INFO, "!**"fmt, 2, arg0, arg1)
+#define PM_PRINT_INFO3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PM, LEVEL_INFO, "!**"fmt, 3, arg0, arg1, arg2)
+#define PM_PRINT_INFO4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PM, LEVEL_INFO, "!**"fmt, 4, arg0, arg1, arg2, arg3)
+#define PM_PRINT_INFO5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PM, LEVEL_INFO, "!**"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define PM_PRINT_INFO6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PM, LEVEL_INFO, "!**"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define PM_PRINT_INFO7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PM, LEVEL_INFO, "!**"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define PM_PRINT_INFO8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PM, LEVEL_INFO, "!**"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define PM_PRINT_INFO9(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PM, LEVEL_INFO, "!**"fmt, 9, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8)
+#define PM_PRINT_INFO10(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8, arg9)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PM, LEVEL_INFO, "!**"fmt, 10, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8, arg9)
+#define PM_PRINT_INFO13(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8, arg9, arg10, arg11, arg12)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PM, LEVEL_INFO, "!**"fmt, 16, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8, arg9, arg10, arg11, arg12)
+#define PM_PRINT_INFO16(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8, arg9, arg10, arg11, arg12, arg13, arg14, arg15)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PM, LEVEL_INFO, "!**"fmt, 16, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8, arg9, arg10, arg11, arg12, arg13, arg14, arg15)
+
+/* PHY Trace Interfaces */
+#define PHY_PRINT_ERROR0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PHY, LEVEL_ERROR, "!!!"fmt, 0)
+#define PHY_PRINT_ERROR1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PHY, LEVEL_ERROR, "!!!"fmt, 1, arg0)
+#define PHY_PRINT_ERROR2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PHY, LEVEL_ERROR, "!!!"fmt, 2, arg0, arg1)
+#define PHY_PRINT_ERROR3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PHY, LEVEL_ERROR, "!!!"fmt, 3, arg0, arg1, arg2)
+#define PHY_PRINT_ERROR4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PHY, LEVEL_ERROR, "!!!"fmt, 4, arg0, arg1, arg2, arg3)
+#define PHY_PRINT_ERROR5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PHY, LEVEL_ERROR, "!!!"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define PHY_PRINT_ERROR6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PHY, LEVEL_ERROR, "!!!"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define PHY_PRINT_ERROR7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PHY, LEVEL_ERROR, "!!!"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define PHY_PRINT_ERROR8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PHY, LEVEL_ERROR, "!!!"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define PHY_PRINT_WARN0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PHY, LEVEL_WARN, "!!*"fmt, 0)
+#define PHY_PRINT_WARN1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PHY, LEVEL_WARN, "!!*"fmt, 1, arg0)
+#define PHY_PRINT_WARN2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PHY, LEVEL_WARN, "!!*"fmt, 2, arg0, arg1)
+#define PHY_PRINT_WARN3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PHY, LEVEL_WARN, "!!*"fmt, 3, arg0, arg1, arg2)
+#define PHY_PRINT_WARN4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PHY, LEVEL_WARN, "!!*"fmt, 4, arg0, arg1, arg2, arg3)
+#define PHY_PRINT_WARN5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PHY, LEVEL_WARN, "!!*"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define PHY_PRINT_WARN6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PHY, LEVEL_WARN, "!!*"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define PHY_PRINT_WARN7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PHY, LEVEL_WARN, "!!*"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define PHY_PRINT_WARN8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PHY, LEVEL_WARN, "!!*"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define PHY_PRINT_INFO0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PHY, LEVEL_INFO, "!**"fmt, 0)
+#define PHY_PRINT_INFO1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PHY, LEVEL_INFO, "!**"fmt, 1, arg0)
+#define PHY_PRINT_INFO2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PHY, LEVEL_INFO, "!**"fmt, 2, arg0, arg1)
+#define PHY_PRINT_INFO3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PHY, LEVEL_INFO, "!**"fmt, 3, arg0, arg1, arg2)
+#define PHY_PRINT_INFO4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PHY, LEVEL_INFO, "!**"fmt, 4, arg0, arg1, arg2, arg3)
+#define PHY_PRINT_INFO5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PHY, LEVEL_INFO, "!**"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define PHY_PRINT_INFO6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PHY, LEVEL_INFO, "!**"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define PHY_PRINT_INFO7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PHY, LEVEL_INFO, "!**"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define PHY_PRINT_INFO8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PHY, LEVEL_INFO, "!**"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define PHY_PRINT_TRACE0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PHY, LEVEL_TRACE, fmt, 0)
+#define PHY_PRINT_TRACE1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PHY, LEVEL_TRACE, fmt, 1, arg0)
+#define PHY_PRINT_TRACE2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PHY, LEVEL_TRACE, fmt, 2, arg0, arg1)
+#define PHY_PRINT_TRACE3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PHY, LEVEL_TRACE, fmt, 3, arg0, arg1, arg2)
+#define PHY_PRINT_TRACE4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PHY, LEVEL_TRACE, fmt, 4, arg0, arg1, arg2, arg3)
+#define PHY_PRINT_TRACE5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PHY, LEVEL_TRACE, fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define PHY_PRINT_TRACE6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PHY, LEVEL_TRACE, fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define PHY_PRINT_TRACE7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PHY, LEVEL_TRACE, fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define PHY_PRINT_TRACE8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PHY, LEVEL_TRACE, fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define PHY_PRINT_TRACE17(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8, arg9, arg10, arg11, arg12, arg13, arg14, arg15, arg16)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PHY, LEVEL_TRACE, fmt, 17, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8, arg9, arg10, arg11, arg12, arg13, arg14, arg15, arg16)
+#define PHY_PRINT_TRACE18(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8, arg9, arg10, arg11, arg12, arg13, arg14, arg15, arg16, arg17)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_PHY, LEVEL_TRACE, fmt, 18, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8, arg9, arg10, arg11, arg12, arg13, arg14, arg15, arg16, arg17)
+
+/* DVFS Trace Interfaces */
+#define DVFS_PRINT_ERROR0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DVFS, LEVEL_ERROR, "!!!"fmt, 0)
+#define DVFS_PRINT_ERROR1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DVFS, LEVEL_ERROR, "!!!"fmt, 1, arg0)
+#define DVFS_PRINT_ERROR2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DVFS, LEVEL_ERROR, "!!!"fmt, 2, arg0, arg1)
+#define DVFS_PRINT_ERROR3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DVFS, LEVEL_ERROR, "!!!"fmt, 3, arg0, arg1, arg2)
+#define DVFS_PRINT_ERROR4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DVFS, LEVEL_ERROR, "!!!"fmt, 4, arg0, arg1, arg2, arg3)
+#define DVFS_PRINT_ERROR5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DVFS, LEVEL_ERROR, "!!!"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define DVFS_PRINT_ERROR6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DVFS, LEVEL_ERROR, "!!!"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define DVFS_PRINT_ERROR7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DVFS, LEVEL_ERROR, "!!!"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define DVFS_PRINT_ERROR8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DVFS, LEVEL_ERROR, "!!!"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define DVFS_PRINT_WARN0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DVFS, LEVEL_WARN, "!!*"fmt, 0)
+#define DVFS_PRINT_WARN1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DVFS, LEVEL_WARN, "!!*"fmt, 1, arg0)
+#define DVFS_PRINT_WARN2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DVFS, LEVEL_WARN, "!!*"fmt, 2, arg0, arg1)
+#define DVFS_PRINT_WARN3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DVFS, LEVEL_WARN, "!!*"fmt, 3, arg0, arg1, arg2)
+#define DVFS_PRINT_WARN4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DVFS, LEVEL_WARN, "!!*"fmt, 4, arg0, arg1, arg2, arg3)
+#define DVFS_PRINT_WARN5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DVFS, LEVEL_WARN, "!!*"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define DVFS_PRINT_WARN6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DVFS, LEVEL_WARN, "!!*"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define DVFS_PRINT_WARN7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DVFS, LEVEL_WARN, "!!*"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define DVFS_PRINT_WARN8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DVFS, LEVEL_WARN, "!!*"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define DVFS_PRINT_INFO0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DVFS, LEVEL_INFO, "!**"fmt, 0)
+#define DVFS_PRINT_INFO1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DVFS, LEVEL_INFO, "!**"fmt, 1, arg0)
+#define DVFS_PRINT_INFO2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DVFS, LEVEL_INFO, "!**"fmt, 2, arg0, arg1)
+#define DVFS_PRINT_INFO3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DVFS, LEVEL_INFO, "!**"fmt, 3, arg0, arg1, arg2)
+#define DVFS_PRINT_INFO4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DVFS, LEVEL_INFO, "!**"fmt, 4, arg0, arg1, arg2, arg3)
+#define DVFS_PRINT_INFO5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DVFS, LEVEL_INFO, "!**"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define DVFS_PRINT_INFO6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DVFS, LEVEL_INFO, "!**"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define DVFS_PRINT_INFO7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DVFS, LEVEL_INFO, "!**"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define DVFS_PRINT_INFO8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DVFS, LEVEL_INFO, "!**"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define DVFS_PRINT_TRACE0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DVFS, LEVEL_TRACE, fmt, 0)
+#define DVFS_PRINT_TRACE1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DVFS, LEVEL_TRACE, fmt, 1, arg0)
+#define DVFS_PRINT_TRACE2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DVFS, LEVEL_TRACE, fmt, 2, arg0, arg1)
+#define DVFS_PRINT_TRACE3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DVFS, LEVEL_TRACE, fmt, 3, arg0, arg1, arg2)
+#define DVFS_PRINT_TRACE4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DVFS, LEVEL_TRACE, fmt, 4, arg0, arg1, arg2, arg3)
+#define DVFS_PRINT_TRACE5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DVFS, LEVEL_TRACE, fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define DVFS_PRINT_TRACE6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DVFS, LEVEL_TRACE, fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define DVFS_PRINT_TRACE7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DVFS, LEVEL_TRACE, fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define DVFS_PRINT_TRACE8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DVFS, LEVEL_TRACE, fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+
+/* CTC Trace Interfaces */
+#define CTC_PRINT_ERROR0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CTC, LEVEL_ERROR, "!!!"fmt, 0)
+#define CTC_PRINT_ERROR1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CTC, LEVEL_ERROR, "!!!"fmt, 1, arg0)
+#define CTC_PRINT_ERROR2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CTC, LEVEL_ERROR, "!!!"fmt, 2, arg0, arg1)
+#define CTC_PRINT_ERROR3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CTC, LEVEL_ERROR, "!!!"fmt, 3, arg0, arg1, arg2)
+#define CTC_PRINT_ERROR4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CTC, LEVEL_ERROR, "!!!"fmt, 4, arg0, arg1, arg2, arg3)
+#define CTC_PRINT_ERROR5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CTC, LEVEL_ERROR, "!!!"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define CTC_PRINT_ERROR6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CTC, LEVEL_ERROR, "!!!"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define CTC_PRINT_ERROR7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CTC, LEVEL_ERROR, "!!!"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define CTC_PRINT_ERROR8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CTC, LEVEL_ERROR, "!!!"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define CTC_PRINT_WARN0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CTC, LEVEL_WARN, "!!*"fmt, 0)
+#define CTC_PRINT_WARN1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CTC, LEVEL_WARN, "!!*"fmt, 1, arg0)
+#define CTC_PRINT_WARN2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CTC, LEVEL_WARN, "!!*"fmt, 2, arg0, arg1)
+#define CTC_PRINT_WARN3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CTC, LEVEL_WARN, "!!*"fmt, 3, arg0, arg1, arg2)
+#define CTC_PRINT_WARN4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CTC, LEVEL_WARN, "!!*"fmt, 4, arg0, arg1, arg2, arg3)
+#define CTC_PRINT_WARN5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CTC, LEVEL_WARN, "!!*"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define CTC_PRINT_WARN6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CTC, LEVEL_WARN, "!!*"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define CTC_PRINT_WARN7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CTC, LEVEL_WARN, "!!*"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define CTC_PRINT_WARN8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CTC, LEVEL_WARN, "!!*"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define CTC_PRINT_INFO0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CTC, LEVEL_INFO, "!**"fmt, 0)
+#define CTC_PRINT_INFO1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CTC, LEVEL_INFO, "!**"fmt, 1, arg0)
+#define CTC_PRINT_INFO2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CTC, LEVEL_INFO, "!**"fmt, 2, arg0, arg1)
+#define CTC_PRINT_INFO3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CTC, LEVEL_INFO, "!**"fmt, 3, arg0, arg1, arg2)
+#define CTC_PRINT_INFO4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CTC, LEVEL_INFO, "!**"fmt, 4, arg0, arg1, arg2, arg3)
+#define CTC_PRINT_INFO5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CTC, LEVEL_INFO, "!**"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define CTC_PRINT_INFO6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CTC, LEVEL_INFO, "!**"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define CTC_PRINT_INFO7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CTC, LEVEL_INFO, "!**"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define CTC_PRINT_INFO8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CTC, LEVEL_INFO, "!**"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define CTC_PRINT_TRACE0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CTC, LEVEL_TRACE, fmt, 0)
+#define CTC_PRINT_TRACE1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CTC, LEVEL_TRACE, fmt, 1, arg0)
+#define CTC_PRINT_TRACE2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CTC, LEVEL_TRACE, fmt, 2, arg0, arg1)
+#define CTC_PRINT_TRACE3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CTC, LEVEL_TRACE, fmt, 3, arg0, arg1, arg2)
+#define CTC_PRINT_TRACE4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CTC, LEVEL_TRACE, fmt, 4, arg0, arg1, arg2, arg3)
+#define CTC_PRINT_TRACE5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CTC, LEVEL_TRACE, fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define CTC_PRINT_TRACE6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CTC, LEVEL_TRACE, fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define CTC_PRINT_TRACE7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CTC, LEVEL_TRACE, fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define CTC_PRINT_TRACE8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CTC, LEVEL_TRACE, fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+
+/* Boot Trace Interfaces */
+#define BOOT_PRINT_ERROR0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BOOT, LEVEL_ERROR, "!!!"fmt, 0)
+#define BOOT_PRINT_ERROR1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BOOT, LEVEL_ERROR, "!!!"fmt, 1, arg0)
+#define BOOT_PRINT_ERROR2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BOOT, LEVEL_ERROR, "!!!"fmt, 2, arg0, arg1)
+#define BOOT_PRINT_ERROR3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BOOT, LEVEL_ERROR, "!!!"fmt, 3, arg0, arg1, arg2)
+#define BOOT_PRINT_ERROR4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BOOT, LEVEL_ERROR, "!!!"fmt, 4, arg0, arg1, arg2, arg3)
+#define BOOT_PRINT_WARN0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BOOT, LEVEL_WARN, "!!*"fmt, 0)
+#define BOOT_PRINT_WARN1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BOOT, LEVEL_WARN, "!!*"fmt, 1, arg0)
+#define BOOT_PRINT_WARN2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BOOT, LEVEL_WARN, "!!*"fmt, 2, arg0, arg1)
+#define BOOT_PRINT_WARN3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BOOT, LEVEL_WARN, "!!*"fmt, 3, arg0, arg1, arg2)
+#define BOOT_PRINT_WARN4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BOOT, LEVEL_WARN, "!!*"fmt, 4, arg0, arg1, arg2, arg3)
+#define BOOT_PRINT_INFO0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BOOT, LEVEL_INFO, "!**"fmt, 0)
+#define BOOT_PRINT_INFO1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BOOT, LEVEL_INFO, "!**"fmt, 1, arg0)
+#define BOOT_PRINT_INFO2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BOOT, LEVEL_INFO, "!**"fmt, 2, arg0, arg1)
+#define BOOT_PRINT_INFO3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BOOT, LEVEL_INFO, "!**"fmt, 3, arg0, arg1, arg2)
+#define BOOT_PRINT_INFO4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BOOT, LEVEL_INFO, "!**"fmt, 4, arg0, arg1, arg2, arg3)
+
+
+/* Bluetooth OTA/DFU Trace Interfaces */
+#define DFU_PRINT_ERROR0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DFU, LEVEL_ERROR, "!!!"fmt, 0)
+#define DFU_PRINT_ERROR1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DFU, LEVEL_ERROR, "!!!"fmt, 1, arg0)
+#define DFU_PRINT_ERROR2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DFU, LEVEL_ERROR, "!!!"fmt, 2, arg0, arg1)
+#define DFU_PRINT_ERROR3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DFU, LEVEL_ERROR, "!!!"fmt, 3, arg0, arg1, arg2)
+#define DFU_PRINT_ERROR4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DFU, LEVEL_ERROR, "!!!"fmt, 4, arg0, arg1, arg2, arg3)
+#define DFU_PRINT_ERROR5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DFU, LEVEL_ERROR, "!!!"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define DFU_PRINT_ERROR6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DFU, LEVEL_ERROR, "!!!"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define DFU_PRINT_ERROR7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DFU, LEVEL_ERROR, "!!!"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define DFU_PRINT_ERROR8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DFU, LEVEL_ERROR, "!!!"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define DFU_PRINT_WARN0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DFU, LEVEL_WARN, "!!*"fmt, 0)
+#define DFU_PRINT_WARN1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DFU, LEVEL_WARN, "!!*"fmt, 1, arg0)
+#define DFU_PRINT_WARN2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DFU, LEVEL_WARN, "!!*"fmt, 2, arg0, arg1)
+#define DFU_PRINT_WARN3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DFU, LEVEL_WARN, "!!*"fmt, 3, arg0, arg1, arg2)
+#define DFU_PRINT_WARN4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DFU, LEVEL_WARN, "!!*"fmt, 4, arg0, arg1, arg2, arg3)
+#define DFU_PRINT_WARN5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DFU, LEVEL_WARN, "!!*"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define DFU_PRINT_WARN6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DFU, LEVEL_WARN, "!!*"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define DFU_PRINT_WARN7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DFU, LEVEL_WARN, "!!*"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define DFU_PRINT_WARN8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DFU, LEVEL_WARN, "!!*"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define DFU_PRINT_INFO0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DFU, LEVEL_INFO, "!**"fmt, 0)
+#define DFU_PRINT_INFO1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DFU, LEVEL_INFO, "!**"fmt, 1, arg0)
+#define DFU_PRINT_INFO2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DFU, LEVEL_INFO, "!**"fmt, 2, arg0, arg1)
+#define DFU_PRINT_INFO3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DFU, LEVEL_INFO, "!**"fmt, 3, arg0, arg1, arg2)
+#define DFU_PRINT_INFO4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DFU, LEVEL_INFO, "!**"fmt, 4, arg0, arg1, arg2, arg3)
+#define DFU_PRINT_INFO5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DFU, LEVEL_INFO, "!**"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define DFU_PRINT_INFO6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DFU, LEVEL_INFO, "!**"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define DFU_PRINT_INFO7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DFU, LEVEL_INFO, "!**"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define DFU_PRINT_INFO8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DFU, LEVEL_INFO, "!**"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define DFU_PRINT_TRACE0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DFU, LEVEL_TRACE, fmt, 0)
+#define DFU_PRINT_TRACE1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DFU, LEVEL_TRACE, fmt, 1, arg0)
+#define DFU_PRINT_TRACE2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DFU, LEVEL_TRACE, fmt, 2, arg0, arg1)
+#define DFU_PRINT_TRACE3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DFU, LEVEL_TRACE, fmt, 3, arg0, arg1, arg2)
+#define DFU_PRINT_TRACE4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DFU, LEVEL_TRACE, fmt, 4, arg0, arg1, arg2, arg3)
+#define DFU_PRINT_TRACE5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DFU, LEVEL_TRACE, fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define DFU_PRINT_TRACE6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DFU, LEVEL_TRACE, fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define DFU_PRINT_TRACE7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DFU, LEVEL_TRACE, fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define DFU_PRINT_TRACE8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DFU, LEVEL_TRACE, fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+
+
+/* Bluetooth FLASH/CACHE Trace Interfaces */
+#define FLASH_PRINT_ERROR0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_FLASH, LEVEL_ERROR, "!!!"fmt, 0)
+#define FLASH_PRINT_ERROR1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_FLASH, LEVEL_ERROR, "!!!"fmt, 1, arg0)
+#define FLASH_PRINT_ERROR2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_FLASH, LEVEL_ERROR, "!!!"fmt, 2, arg0, arg1)
+#define FLASH_PRINT_ERROR3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_FLASH, LEVEL_ERROR, "!!!"fmt, 3, arg0, arg1, arg2)
+#define FLASH_PRINT_ERROR4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_FLASH, LEVEL_ERROR, "!!!"fmt, 4, arg0, arg1, arg2, arg3)
+#define FLASH_PRINT_ERROR5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_FLASH, LEVEL_ERROR, "!!!"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define FLASH_PRINT_ERROR6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_FLASH, LEVEL_ERROR, "!!!"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define FLASH_PRINT_ERROR7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_FLASH, LEVEL_ERROR, "!!!"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define FLASH_PRINT_ERROR8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_FLASH, LEVEL_ERROR, "!!!"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define FLASH_PRINT_WARN0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_FLASH, LEVEL_WARN, "!!*"fmt, 0)
+#define FLASH_PRINT_WARN1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_FLASH, LEVEL_WARN, "!!*"fmt, 1, arg0)
+#define FLASH_PRINT_WARN2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_FLASH, LEVEL_WARN, "!!*"fmt, 2, arg0, arg1)
+#define FLASH_PRINT_WARN3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_FLASH, LEVEL_WARN, "!!*"fmt, 3, arg0, arg1, arg2)
+#define FLASH_PRINT_WARN4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_FLASH, LEVEL_WARN, "!!*"fmt, 4, arg0, arg1, arg2, arg3)
+#define FLASH_PRINT_WARN5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_FLASH, LEVEL_WARN, "!!*"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define FLASH_PRINT_WARN6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_FLASH, LEVEL_WARN, "!!*"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define FLASH_PRINT_WARN7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_FLASH, LEVEL_WARN, "!!*"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define FLASH_PRINT_WARN8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_FLASH, LEVEL_WARN, "!!*"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define FLASH_PRINT_INFO0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_FLASH, LEVEL_INFO, "!**"fmt, 0)
+#define FLASH_PRINT_INFO1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_FLASH, LEVEL_INFO, "!**"fmt, 1, arg0)
+#define FLASH_PRINT_INFO2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_FLASH, LEVEL_INFO, "!**"fmt, 2, arg0, arg1)
+#define FLASH_PRINT_INFO3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_FLASH, LEVEL_INFO, "!**"fmt, 3, arg0, arg1, arg2)
+#define FLASH_PRINT_INFO4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_FLASH, LEVEL_INFO, "!**"fmt, 4, arg0, arg1, arg2, arg3)
+#define FLASH_PRINT_INFO5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_FLASH, LEVEL_INFO, "!**"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define FLASH_PRINT_INFO6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_FLASH, LEVEL_INFO, "!**"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define FLASH_PRINT_INFO7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_FLASH, LEVEL_INFO, "!**"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define FLASH_PRINT_INFO8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_FLASH, LEVEL_INFO, "!**"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define FLASH_PRINT_TRACE0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_FLASH, LEVEL_TRACE, fmt, 0)
+#define FLASH_PRINT_TRACE1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_FLASH, LEVEL_TRACE, fmt, 1, arg0)
+#define FLASH_PRINT_TRACE2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_FLASH, LEVEL_TRACE, fmt, 2, arg0, arg1)
+#define FLASH_PRINT_TRACE3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_FLASH, LEVEL_TRACE, fmt, 3, arg0, arg1, arg2)
+#define FLASH_PRINT_TRACE4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_FLASH, LEVEL_TRACE, fmt, 4, arg0, arg1, arg2, arg3)
+#define FLASH_PRINT_TRACE5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_FLASH, LEVEL_TRACE, fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define FLASH_PRINT_TRACE6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_FLASH, LEVEL_TRACE, fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define FLASH_PRINT_TRACE7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_FLASH, LEVEL_TRACE, fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define FLASH_PRINT_TRACE8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_FLASH, LEVEL_TRACE, fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+
+
+/* USB Trace Interfaces */
+#define USB_PRINT_ERROR0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_USB, LEVEL_ERROR, "!!!"fmt, 0)
+#define USB_PRINT_ERROR1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_USB, LEVEL_ERROR, "!!!"fmt, 1, arg0)
+#define USB_PRINT_ERROR2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_USB, LEVEL_ERROR, "!!!"fmt, 2, arg0, arg1)
+#define USB_PRINT_ERROR3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_USB, LEVEL_ERROR, "!!!"fmt, 3, arg0, arg1, arg2)
+#define USB_PRINT_ERROR4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_USB, LEVEL_ERROR, "!!!"fmt, 4, arg0, arg1, arg2, arg3)
+#define USB_PRINT_ERROR5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_USB, LEVEL_ERROR, "!!!"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define USB_PRINT_ERROR6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_USB, LEVEL_ERROR, "!!!"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define USB_PRINT_ERROR7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_USB, LEVEL_ERROR, "!!!"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define USB_PRINT_ERROR8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_USB, LEVEL_ERROR, "!!!"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define USB_PRINT_WARN0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_USB, LEVEL_WARN, "!!*"fmt, 0)
+#define USB_PRINT_WARN1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_USB, LEVEL_WARN, "!!*"fmt, 1, arg0)
+#define USB_PRINT_WARN2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_USB, LEVEL_WARN, "!!*"fmt, 2, arg0, arg1)
+#define USB_PRINT_WARN3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_USB, LEVEL_WARN, "!!*"fmt, 3, arg0, arg1, arg2)
+#define USB_PRINT_WARN4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_USB, LEVEL_WARN, "!!*"fmt, 4, arg0, arg1, arg2, arg3)
+#define USB_PRINT_WARN5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_USB, LEVEL_WARN, "!!*"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define USB_PRINT_WARN6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_USB, LEVEL_WARN, "!!*"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define USB_PRINT_WARN7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_USB, LEVEL_WARN, "!!*"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define USB_PRINT_WARN8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_USB, LEVEL_WARN, "!!*"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define USB_PRINT_INFO0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_USB, LEVEL_INFO, "!**"fmt, 0)
+#define USB_PRINT_INFO1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_USB, LEVEL_INFO, "!**"fmt, 1, arg0)
+#define USB_PRINT_INFO2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_USB, LEVEL_INFO, "!**"fmt, 2, arg0, arg1)
+#define USB_PRINT_INFO3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_USB, LEVEL_INFO, "!**"fmt, 3, arg0, arg1, arg2)
+#define USB_PRINT_INFO4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_USB, LEVEL_INFO, "!**"fmt, 4, arg0, arg1, arg2, arg3)
+#define USB_PRINT_INFO5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_USB, LEVEL_INFO, "!**"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define USB_PRINT_INFO6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_USB, LEVEL_INFO, "!**"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define USB_PRINT_INFO7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_USB, LEVEL_INFO, "!**"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define USB_PRINT_INFO8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_USB, LEVEL_INFO, "!**"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define USB_PRINT_TRACE0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_USB, LEVEL_TRACE, fmt, 0)
+#define USB_PRINT_TRACE1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_USB, LEVEL_TRACE, fmt, 1, arg0)
+#define USB_PRINT_TRACE2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_USB, LEVEL_TRACE, fmt, 2, arg0, arg1)
+#define USB_PRINT_TRACE3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_USB, LEVEL_TRACE, fmt, 3, arg0, arg1, arg2)
+#define USB_PRINT_TRACE4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_USB, LEVEL_TRACE, fmt, 4, arg0, arg1, arg2, arg3)
+#define USB_PRINT_TRACE5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_USB, LEVEL_TRACE, fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define USB_PRINT_TRACE6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_USB, LEVEL_TRACE, fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define USB_PRINT_TRACE7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_USB, LEVEL_TRACE, fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define USB_PRINT_TRACE8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_USB, LEVEL_TRACE, fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+
+
+/* Charger Trace Interfaces */
+#define CHARGER_PRINT_ERROR0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CHARGER, LEVEL_ERROR, "!!!"fmt, 0)
+#define CHARGER_PRINT_ERROR1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CHARGER, LEVEL_ERROR, "!!!"fmt, 1, arg0)
+#define CHARGER_PRINT_ERROR2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CHARGER, LEVEL_ERROR, "!!!"fmt, 2, arg0, arg1)
+#define CHARGER_PRINT_ERROR3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CHARGER, LEVEL_ERROR, "!!!"fmt, 3, arg0, arg1, arg2)
+#define CHARGER_PRINT_ERROR4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CHARGER, LEVEL_ERROR, "!!!"fmt, 4, arg0, arg1, arg2, arg3)
+#define CHARGER_PRINT_ERROR5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CHARGER, LEVEL_ERROR, "!!!"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define CHARGER_PRINT_ERROR6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CHARGER, LEVEL_ERROR, "!!!"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define CHARGER_PRINT_ERROR7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CHARGER, LEVEL_ERROR, "!!!"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define CHARGER_PRINT_ERROR8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CHARGER, LEVEL_ERROR, "!!!"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define CHARGER_PRINT_WARN0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CHARGER, LEVEL_WARN, "!!*"fmt, 0)
+#define CHARGER_PRINT_WARN1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CHARGER, LEVEL_WARN, "!!*"fmt, 1, arg0)
+#define CHARGER_PRINT_WARN2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CHARGER, LEVEL_WARN, "!!*"fmt, 2, arg0, arg1)
+#define CHARGER_PRINT_WARN3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CHARGER, LEVEL_WARN, "!!*"fmt, 3, arg0, arg1, arg2)
+#define CHARGER_PRINT_WARN4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CHARGER, LEVEL_WARN, "!!*"fmt, 4, arg0, arg1, arg2, arg3)
+#define CHARGER_PRINT_WARN5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CHARGER, LEVEL_WARN, "!!*"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define CHARGER_PRINT_WARN6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CHARGER, LEVEL_WARN, "!!*"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define CHARGER_PRINT_WARN7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CHARGER, LEVEL_WARN, "!!*"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define CHARGER_PRINT_WARN8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CHARGER, LEVEL_WARN, "!!*"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define CHARGER_PRINT_INFO0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CHARGER, LEVEL_INFO, "!**"fmt, 0)
+#define CHARGER_PRINT_INFO1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CHARGER, LEVEL_INFO, "!**"fmt, 1, arg0)
+#define CHARGER_PRINT_INFO2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CHARGER, LEVEL_INFO, "!**"fmt, 2, arg0, arg1)
+#define CHARGER_PRINT_INFO3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CHARGER, LEVEL_INFO, "!**"fmt, 3, arg0, arg1, arg2)
+#define CHARGER_PRINT_INFO4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CHARGER, LEVEL_INFO, "!**"fmt, 4, arg0, arg1, arg2, arg3)
+#define CHARGER_PRINT_INFO5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CHARGER, LEVEL_INFO, "!**"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define CHARGER_PRINT_INFO6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CHARGER, LEVEL_INFO, "!**"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define CHARGER_PRINT_INFO7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CHARGER, LEVEL_INFO, "!**"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define CHARGER_PRINT_INFO8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CHARGER, LEVEL_INFO, "!**"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define CHARGER_PRINT_TRACE0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CHARGER, LEVEL_TRACE, fmt, 0)
+#define CHARGER_PRINT_TRACE1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CHARGER, LEVEL_TRACE, fmt, 1, arg0)
+#define CHARGER_PRINT_TRACE2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CHARGER, LEVEL_TRACE, fmt, 2, arg0, arg1)
+#define CHARGER_PRINT_TRACE3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CHARGER, LEVEL_TRACE, fmt, 3, arg0, arg1, arg2)
+#define CHARGER_PRINT_TRACE4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CHARGER, LEVEL_TRACE, fmt, 4, arg0, arg1, arg2, arg3)
+#define CHARGER_PRINT_TRACE5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CHARGER, LEVEL_TRACE, fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define CHARGER_PRINT_TRACE6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CHARGER, LEVEL_TRACE, fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define CHARGER_PRINT_TRACE7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CHARGER, LEVEL_TRACE, fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define CHARGER_PRINT_TRACE8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CHARGER, LEVEL_TRACE, fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+
+/* SYS Trace Interfaces */
+#define SYS_PRINT_ERROR0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SYS, LEVEL_ERROR, "!!!"fmt, 0)
+#define SYS_PRINT_ERROR1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SYS, LEVEL_ERROR, "!!!"fmt, 1, arg0)
+#define SYS_PRINT_ERROR2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SYS, LEVEL_ERROR, "!!!"fmt, 2, arg0, arg1)
+#define SYS_PRINT_ERROR3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SYS, LEVEL_ERROR, "!!!"fmt, 3, arg0, arg1, arg2)
+#define SYS_PRINT_ERROR4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SYS, LEVEL_ERROR, "!!!"fmt, 4, arg0, arg1, arg2, arg3)
+#define SYS_PRINT_ERROR5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SYS, LEVEL_ERROR, "!!!"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define SYS_PRINT_ERROR6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SYS, LEVEL_ERROR, "!!!"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define SYS_PRINT_ERROR7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SYS, LEVEL_ERROR, "!!!"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define SYS_PRINT_ERROR8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SYS, LEVEL_ERROR, "!!!"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define SYS_PRINT_WARN0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SYS, LEVEL_WARN, "!!*"fmt, 0)
+#define SYS_PRINT_WARN1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SYS, LEVEL_WARN, "!!*"fmt, 1, arg0)
+#define SYS_PRINT_WARN2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SYS, LEVEL_WARN, "!!*"fmt, 2, arg0, arg1)
+#define SYS_PRINT_WARN3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SYS, LEVEL_WARN, "!!*"fmt, 3, arg0, arg1, arg2)
+#define SYS_PRINT_WARN4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SYS, LEVEL_WARN, "!!*"fmt, 4, arg0, arg1, arg2, arg3)
+#define SYS_PRINT_WARN5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SYS, LEVEL_WARN, "!!*"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define SYS_PRINT_WARN6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SYS, LEVEL_WARN, "!!*"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define SYS_PRINT_WARN7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SYS, LEVEL_WARN, "!!*"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define SYS_PRINT_WARN8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SYS, LEVEL_WARN, "!!*"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define SYS_PRINT_INFO0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SYS, LEVEL_INFO, "!**"fmt, 0)
+#define SYS_PRINT_INFO1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SYS, LEVEL_INFO, "!**"fmt, 1, arg0)
+#define SYS_PRINT_INFO2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SYS, LEVEL_INFO, "!**"fmt, 2, arg0, arg1)
+#define SYS_PRINT_INFO3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SYS, LEVEL_INFO, "!**"fmt, 3, arg0, arg1, arg2)
+#define SYS_PRINT_INFO4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SYS, LEVEL_INFO, "!**"fmt, 4, arg0, arg1, arg2, arg3)
+#define SYS_PRINT_INFO5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SYS, LEVEL_INFO, "!**"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define SYS_PRINT_INFO6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SYS, LEVEL_INFO, "!**"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define SYS_PRINT_INFO7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SYS, LEVEL_INFO, "!**"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define SYS_PRINT_INFO8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SYS, LEVEL_INFO, "!**"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define SYS_PRINT_TRACE0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SYS, LEVEL_TRACE, fmt, 0)
+#define SYS_PRINT_TRACE1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SYS, LEVEL_TRACE, fmt, 1, arg0)
+#define SYS_PRINT_TRACE2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SYS, LEVEL_TRACE, fmt, 2, arg0, arg1)
+#define SYS_PRINT_TRACE3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SYS, LEVEL_TRACE, fmt, 3, arg0, arg1, arg2)
+#define SYS_PRINT_TRACE4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SYS, LEVEL_TRACE, fmt, 4, arg0, arg1, arg2, arg3)
+#define SYS_PRINT_TRACE5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SYS, LEVEL_TRACE, fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define SYS_PRINT_TRACE6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SYS, LEVEL_TRACE, fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define SYS_PRINT_TRACE7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SYS, LEVEL_TRACE, fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define SYS_PRINT_TRACE8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SYS, LEVEL_TRACE, fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+
+/* DM Trace Interfaces */
+#define DM_PRINT_ERROR0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DM, LEVEL_ERROR, "!!!"fmt, 0)
+#define DM_PRINT_ERROR1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DM, LEVEL_ERROR, "!!!"fmt, 1, arg0)
+#define DM_PRINT_ERROR2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DM, LEVEL_ERROR, "!!!"fmt, 2, arg0, arg1)
+#define DM_PRINT_ERROR3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DM, LEVEL_ERROR, "!!!"fmt, 3, arg0, arg1, arg2)
+#define DM_PRINT_ERROR4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DM, LEVEL_ERROR, "!!!"fmt, 4, arg0, arg1, arg2, arg3)
+#define DM_PRINT_ERROR5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DM, LEVEL_ERROR, "!!!"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define DM_PRINT_ERROR6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DM, LEVEL_ERROR, "!!!"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define DM_PRINT_ERROR7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DM, LEVEL_ERROR, "!!!"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define DM_PRINT_ERROR8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DM, LEVEL_ERROR, "!!!"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define DM_PRINT_WARN0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DM, LEVEL_WARN, "!!*"fmt, 0)
+#define DM_PRINT_WARN1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DM, LEVEL_WARN, "!!*"fmt, 1, arg0)
+#define DM_PRINT_WARN2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DM, LEVEL_WARN, "!!*"fmt, 2, arg0, arg1)
+#define DM_PRINT_WARN3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DM, LEVEL_WARN, "!!*"fmt, 3, arg0, arg1, arg2)
+#define DM_PRINT_WARN4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DM, LEVEL_WARN, "!!*"fmt, 4, arg0, arg1, arg2, arg3)
+#define DM_PRINT_WARN5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DM, LEVEL_WARN, "!!*"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define DM_PRINT_WARN6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DM, LEVEL_WARN, "!!*"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define DM_PRINT_WARN7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DM, LEVEL_WARN, "!!*"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define DM_PRINT_WARN8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DM, LEVEL_WARN, "!!*"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define DM_PRINT_INFO0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DM, LEVEL_INFO, "!**"fmt, 0)
+#define DM_PRINT_INFO1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DM, LEVEL_INFO, "!**"fmt, 1, arg0)
+#define DM_PRINT_INFO2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DM, LEVEL_INFO, "!**"fmt, 2, arg0, arg1)
+#define DM_PRINT_INFO3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DM, LEVEL_INFO, "!**"fmt, 3, arg0, arg1, arg2)
+#define DM_PRINT_INFO4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DM, LEVEL_INFO, "!**"fmt, 4, arg0, arg1, arg2, arg3)
+#define DM_PRINT_INFO5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DM, LEVEL_INFO, "!**"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define DM_PRINT_INFO6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DM, LEVEL_INFO, "!**"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define DM_PRINT_INFO7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DM, LEVEL_INFO, "!**"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define DM_PRINT_INFO8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DM, LEVEL_INFO, "!**"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define DM_PRINT_TRACE0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DM, LEVEL_TRACE, fmt, 0)
+#define DM_PRINT_TRACE1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DM, LEVEL_TRACE, fmt, 1, arg0)
+#define DM_PRINT_TRACE2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DM, LEVEL_TRACE, fmt, 2, arg0, arg1)
+#define DM_PRINT_TRACE3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DM, LEVEL_TRACE, fmt, 3, arg0, arg1, arg2)
+#define DM_PRINT_TRACE4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DM, LEVEL_TRACE, fmt, 4, arg0, arg1, arg2, arg3)
+#define DM_PRINT_TRACE5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DM, LEVEL_TRACE, fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define DM_PRINT_TRACE6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DM, LEVEL_TRACE, fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define DM_PRINT_TRACE7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DM, LEVEL_TRACE, fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define DM_PRINT_TRACE8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DM, LEVEL_TRACE, fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+
+/* BTM Trace Interfaces */
+#define BTM_PRINT_ERROR0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTM, LEVEL_ERROR, "!!!"fmt, 0)
+#define BTM_PRINT_ERROR1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTM, LEVEL_ERROR, "!!!"fmt, 1, arg0)
+#define BTM_PRINT_ERROR2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTM, LEVEL_ERROR, "!!!"fmt, 2, arg0, arg1)
+#define BTM_PRINT_ERROR3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTM, LEVEL_ERROR, "!!!"fmt, 3, arg0, arg1, arg2)
+#define BTM_PRINT_ERROR4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTM, LEVEL_ERROR, "!!!"fmt, 4, arg0, arg1, arg2, arg3)
+#define BTM_PRINT_ERROR5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTM, LEVEL_ERROR, "!!!"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define BTM_PRINT_ERROR6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTM, LEVEL_ERROR, "!!!"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define BTM_PRINT_ERROR7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTM, LEVEL_ERROR, "!!!"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define BTM_PRINT_ERROR8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTM, LEVEL_ERROR, "!!!"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define BTM_PRINT_WARN0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTM, LEVEL_WARN, "!!*"fmt, 0)
+#define BTM_PRINT_WARN1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTM, LEVEL_WARN, "!!*"fmt, 1, arg0)
+#define BTM_PRINT_WARN2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTM, LEVEL_WARN, "!!*"fmt, 2, arg0, arg1)
+#define BTM_PRINT_WARN3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTM, LEVEL_WARN, "!!*"fmt, 3, arg0, arg1, arg2)
+#define BTM_PRINT_WARN4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTM, LEVEL_WARN, "!!*"fmt, 4, arg0, arg1, arg2, arg3)
+#define BTM_PRINT_WARN5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTM, LEVEL_WARN, "!!*"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define BTM_PRINT_WARN6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTM, LEVEL_WARN, "!!*"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define BTM_PRINT_WARN7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTM, LEVEL_WARN, "!!*"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define BTM_PRINT_WARN8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTM, LEVEL_WARN, "!!*"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define BTM_PRINT_INFO0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTM, LEVEL_INFO, "!**"fmt, 0)
+#define BTM_PRINT_INFO1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTM, LEVEL_INFO, "!**"fmt, 1, arg0)
+#define BTM_PRINT_INFO2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTM, LEVEL_INFO, "!**"fmt, 2, arg0, arg1)
+#define BTM_PRINT_INFO3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTM, LEVEL_INFO, "!**"fmt, 3, arg0, arg1, arg2)
+#define BTM_PRINT_INFO4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTM, LEVEL_INFO, "!**"fmt, 4, arg0, arg1, arg2, arg3)
+#define BTM_PRINT_INFO5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTM, LEVEL_INFO, "!**"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define BTM_PRINT_INFO6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTM, LEVEL_INFO, "!**"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define BTM_PRINT_INFO7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTM, LEVEL_INFO, "!**"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define BTM_PRINT_INFO8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTM, LEVEL_INFO, "!**"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define BTM_PRINT_TRACE0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTM, LEVEL_TRACE, fmt, 0)
+#define BTM_PRINT_TRACE1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTM, LEVEL_TRACE, fmt, 1, arg0)
+#define BTM_PRINT_TRACE2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTM, LEVEL_TRACE, fmt, 2, arg0, arg1)
+#define BTM_PRINT_TRACE3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTM, LEVEL_TRACE, fmt, 3, arg0, arg1, arg2)
+#define BTM_PRINT_TRACE4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTM, LEVEL_TRACE, fmt, 4, arg0, arg1, arg2, arg3)
+#define BTM_PRINT_TRACE5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTM, LEVEL_TRACE, fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define BTM_PRINT_TRACE6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTM, LEVEL_TRACE, fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define BTM_PRINT_TRACE7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTM, LEVEL_TRACE, fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define BTM_PRINT_TRACE8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_BTM, LEVEL_TRACE, fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+
+/* AUDIO Trace Interfaces */
+#define AUDIO_PRINT_ERROR0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_AUDIO, LEVEL_ERROR, "!!!"fmt, 0)
+#define AUDIO_PRINT_ERROR1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_AUDIO, LEVEL_ERROR, "!!!"fmt, 1, arg0)
+#define AUDIO_PRINT_ERROR2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_AUDIO, LEVEL_ERROR, "!!!"fmt, 2, arg0, arg1)
+#define AUDIO_PRINT_ERROR3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_AUDIO, LEVEL_ERROR, "!!!"fmt, 3, arg0, arg1, arg2)
+#define AUDIO_PRINT_ERROR4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_AUDIO, LEVEL_ERROR, "!!!"fmt, 4, arg0, arg1, arg2, arg3)
+#define AUDIO_PRINT_ERROR5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_AUDIO, LEVEL_ERROR, "!!!"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define AUDIO_PRINT_ERROR6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_AUDIO, LEVEL_ERROR, "!!!"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define AUDIO_PRINT_ERROR7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_AUDIO, LEVEL_ERROR, "!!!"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define AUDIO_PRINT_ERROR8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_AUDIO, LEVEL_ERROR, "!!!"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define AUDIO_PRINT_WARN0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_AUDIO, LEVEL_WARN, "!!*"fmt, 0)
+#define AUDIO_PRINT_WARN1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_AUDIO, LEVEL_WARN, "!!*"fmt, 1, arg0)
+#define AUDIO_PRINT_WARN2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_AUDIO, LEVEL_WARN, "!!*"fmt, 2, arg0, arg1)
+#define AUDIO_PRINT_WARN3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_AUDIO, LEVEL_WARN, "!!*"fmt, 3, arg0, arg1, arg2)
+#define AUDIO_PRINT_WARN4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_AUDIO, LEVEL_WARN, "!!*"fmt, 4, arg0, arg1, arg2, arg3)
+#define AUDIO_PRINT_WARN5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_AUDIO, LEVEL_WARN, "!!*"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define AUDIO_PRINT_WARN6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_AUDIO, LEVEL_WARN, "!!*"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define AUDIO_PRINT_WARN7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_AUDIO, LEVEL_WARN, "!!*"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define AUDIO_PRINT_WARN8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_AUDIO, LEVEL_WARN, "!!*"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define AUDIO_PRINT_INFO0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_AUDIO, LEVEL_INFO, "!**"fmt, 0)
+#define AUDIO_PRINT_INFO1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_AUDIO, LEVEL_INFO, "!**"fmt, 1, arg0)
+#define AUDIO_PRINT_INFO2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_AUDIO, LEVEL_INFO, "!**"fmt, 2, arg0, arg1)
+#define AUDIO_PRINT_INFO3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_AUDIO, LEVEL_INFO, "!**"fmt, 3, arg0, arg1, arg2)
+#define AUDIO_PRINT_INFO4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_AUDIO, LEVEL_INFO, "!**"fmt, 4, arg0, arg1, arg2, arg3)
+#define AUDIO_PRINT_INFO5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_AUDIO, LEVEL_INFO, "!**"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define AUDIO_PRINT_INFO6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_AUDIO, LEVEL_INFO, "!**"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define AUDIO_PRINT_INFO7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_AUDIO, LEVEL_INFO, "!**"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define AUDIO_PRINT_INFO8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_AUDIO, LEVEL_INFO, "!**"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define AUDIO_PRINT_TRACE0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_AUDIO, LEVEL_TRACE, fmt, 0)
+#define AUDIO_PRINT_TRACE1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_AUDIO, LEVEL_TRACE, fmt, 1, arg0)
+#define AUDIO_PRINT_TRACE2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_AUDIO, LEVEL_TRACE, fmt, 2, arg0, arg1)
+#define AUDIO_PRINT_TRACE3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_AUDIO, LEVEL_TRACE, fmt, 3, arg0, arg1, arg2)
+#define AUDIO_PRINT_TRACE4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_AUDIO, LEVEL_TRACE, fmt, 4, arg0, arg1, arg2, arg3)
+#define AUDIO_PRINT_TRACE5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_AUDIO, LEVEL_TRACE, fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define AUDIO_PRINT_TRACE6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_AUDIO, LEVEL_TRACE, fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define AUDIO_PRINT_TRACE7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_AUDIO, LEVEL_TRACE, fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define AUDIO_PRINT_TRACE8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_AUDIO, LEVEL_TRACE, fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+
+/* REMOTE Trace Interfaces */
+#define REMOTE_PRINT_ERROR0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_REMOTE, LEVEL_ERROR, "!!!"fmt, 0)
+#define REMOTE_PRINT_ERROR1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_REMOTE, LEVEL_ERROR, "!!!"fmt, 1, arg0)
+#define REMOTE_PRINT_ERROR2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_REMOTE, LEVEL_ERROR, "!!!"fmt, 2, arg0, arg1)
+#define REMOTE_PRINT_ERROR3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_REMOTE, LEVEL_ERROR, "!!!"fmt, 3, arg0, arg1, arg2)
+#define REMOTE_PRINT_ERROR4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_REMOTE, LEVEL_ERROR, "!!!"fmt, 4, arg0, arg1, arg2, arg3)
+#define REMOTE_PRINT_ERROR5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_REMOTE, LEVEL_ERROR, "!!!"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define REMOTE_PRINT_ERROR6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_REMOTE, LEVEL_ERROR, "!!!"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define REMOTE_PRINT_ERROR7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_REMOTE, LEVEL_ERROR, "!!!"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define REMOTE_PRINT_ERROR8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_REMOTE, LEVEL_ERROR, "!!!"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define REMOTE_PRINT_WARN0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_REMOTE, LEVEL_WARN, "!!*"fmt, 0)
+#define REMOTE_PRINT_WARN1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_REMOTE, LEVEL_WARN, "!!*"fmt, 1, arg0)
+#define REMOTE_PRINT_WARN2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_REMOTE, LEVEL_WARN, "!!*"fmt, 2, arg0, arg1)
+#define REMOTE_PRINT_WARN3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_REMOTE, LEVEL_WARN, "!!*"fmt, 3, arg0, arg1, arg2)
+#define REMOTE_PRINT_WARN4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_REMOTE, LEVEL_WARN, "!!*"fmt, 4, arg0, arg1, arg2, arg3)
+#define REMOTE_PRINT_WARN5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_REMOTE, LEVEL_WARN, "!!*"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define REMOTE_PRINT_WARN6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_REMOTE, LEVEL_WARN, "!!*"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define REMOTE_PRINT_WARN7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_REMOTE, LEVEL_WARN, "!!*"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define REMOTE_PRINT_WARN8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_REMOTE, LEVEL_WARN, "!!*"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define REMOTE_PRINT_INFO0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_REMOTE, LEVEL_INFO, "!**"fmt, 0)
+#define REMOTE_PRINT_INFO1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_REMOTE, LEVEL_INFO, "!**"fmt, 1, arg0)
+#define REMOTE_PRINT_INFO2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_REMOTE, LEVEL_INFO, "!**"fmt, 2, arg0, arg1)
+#define REMOTE_PRINT_INFO3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_REMOTE, LEVEL_INFO, "!**"fmt, 3, arg0, arg1, arg2)
+#define REMOTE_PRINT_INFO4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_REMOTE, LEVEL_INFO, "!**"fmt, 4, arg0, arg1, arg2, arg3)
+#define REMOTE_PRINT_INFO5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_REMOTE, LEVEL_INFO, "!**"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define REMOTE_PRINT_INFO6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_REMOTE, LEVEL_INFO, "!**"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define REMOTE_PRINT_INFO7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_REMOTE, LEVEL_INFO, "!**"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define REMOTE_PRINT_INFO8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_REMOTE, LEVEL_INFO, "!**"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define REMOTE_PRINT_TRACE0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_REMOTE, LEVEL_TRACE, fmt, 0)
+#define REMOTE_PRINT_TRACE1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_REMOTE, LEVEL_TRACE, fmt, 1, arg0)
+#define REMOTE_PRINT_TRACE2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_REMOTE, LEVEL_TRACE, fmt, 2, arg0, arg1)
+#define REMOTE_PRINT_TRACE3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_REMOTE, LEVEL_TRACE, fmt, 3, arg0, arg1, arg2)
+#define REMOTE_PRINT_TRACE4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_REMOTE, LEVEL_TRACE, fmt, 4, arg0, arg1, arg2, arg3)
+#define REMOTE_PRINT_TRACE5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_REMOTE, LEVEL_TRACE, fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define REMOTE_PRINT_TRACE6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_REMOTE, LEVEL_TRACE, fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define REMOTE_PRINT_TRACE7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_REMOTE, LEVEL_TRACE, fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define REMOTE_PRINT_TRACE8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_REMOTE, LEVEL_TRACE, fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+
+/* GDMA Trace Interfaces */
+#define GDMA_PRINT_ERROR0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GDMA, LEVEL_ERROR, "!!!"fmt, 0)
+#define GDMA_PRINT_ERROR1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GDMA, LEVEL_ERROR, "!!!"fmt, 1, arg0)
+#define GDMA_PRINT_ERROR2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GDMA, LEVEL_ERROR, "!!!"fmt, 2, arg0, arg1)
+#define GDMA_PRINT_ERROR3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GDMA, LEVEL_ERROR, "!!!"fmt, 3, arg0, arg1, arg2)
+#define GDMA_PRINT_ERROR4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GDMA, LEVEL_ERROR, "!!!"fmt, 4, arg0, arg1, arg2, arg3)
+#define GDMA_PRINT_ERROR5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GDMA, LEVEL_ERROR, "!!!"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define GDMA_PRINT_ERROR6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GDMA, LEVEL_ERROR, "!!!"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define GDMA_PRINT_ERROR7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GDMA, LEVEL_ERROR, "!!!"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define GDMA_PRINT_ERROR8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GDMA, LEVEL_ERROR, "!!!"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define GDMA_PRINT_WARN0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GDMA, LEVEL_WARN, "!!*"fmt, 0)
+#define GDMA_PRINT_WARN1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GDMA, LEVEL_WARN, "!!*"fmt, 1, arg0)
+#define GDMA_PRINT_WARN2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GDMA, LEVEL_WARN, "!!*"fmt, 2, arg0, arg1)
+#define GDMA_PRINT_WARN3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GDMA, LEVEL_WARN, "!!*"fmt, 3, arg0, arg1, arg2)
+#define GDMA_PRINT_WARN4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GDMA, LEVEL_WARN, "!!*"fmt, 4, arg0, arg1, arg2, arg3)
+#define GDMA_PRINT_WARN5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GDMA, LEVEL_WARN, "!!*"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define GDMA_PRINT_WARN6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GDMA, LEVEL_WARN, "!!*"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define GDMA_PRINT_WARN7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GDMA, LEVEL_WARN, "!!*"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define GDMA_PRINT_WARN8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GDMA, LEVEL_WARN, "!!*"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define GDMA_PRINT_INFO0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GDMA, LEVEL_INFO, "!**"fmt, 0)
+#define GDMA_PRINT_INFO1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GDMA, LEVEL_INFO, "!**"fmt, 1, arg0)
+#define GDMA_PRINT_INFO2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GDMA, LEVEL_INFO, "!**"fmt, 2, arg0, arg1)
+#define GDMA_PRINT_INFO3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GDMA, LEVEL_INFO, "!**"fmt, 3, arg0, arg1, arg2)
+#define GDMA_PRINT_INFO4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GDMA, LEVEL_INFO, "!**"fmt, 4, arg0, arg1, arg2, arg3)
+#define GDMA_PRINT_INFO5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GDMA, LEVEL_INFO, "!**"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define GDMA_PRINT_INFO6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GDMA, LEVEL_INFO, "!**"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define GDMA_PRINT_INFO7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GDMA, LEVEL_INFO, "!**"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define GDMA_PRINT_INFO8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GDMA, LEVEL_INFO, "!**"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define GDMA_PRINT_TRACE0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GDMA, LEVEL_TRACE, fmt, 0)
+#define GDMA_PRINT_TRACE1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GDMA, LEVEL_TRACE, fmt, 1, arg0)
+#define GDMA_PRINT_TRACE2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GDMA, LEVEL_TRACE, fmt, 2, arg0, arg1)
+#define GDMA_PRINT_TRACE3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GDMA, LEVEL_TRACE, fmt, 3, arg0, arg1, arg2)
+#define GDMA_PRINT_TRACE4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GDMA, LEVEL_TRACE, fmt, 4, arg0, arg1, arg2, arg3)
+#define GDMA_PRINT_TRACE5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GDMA, LEVEL_TRACE, fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define GDMA_PRINT_TRACE6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GDMA, LEVEL_TRACE, fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define GDMA_PRINT_TRACE7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GDMA, LEVEL_TRACE, fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define GDMA_PRINT_TRACE8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_GDMA, LEVEL_TRACE, fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+
+/* IO Trace Interfaces */
+#define IO_PRINT_ERROR0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_IO, LEVEL_ERROR, "!!!"fmt, 0)
+#define IO_PRINT_ERROR1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_IO, LEVEL_ERROR, "!!!"fmt, 1, arg0)
+#define IO_PRINT_ERROR2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_IO, LEVEL_ERROR, "!!!"fmt, 2, arg0, arg1)
+#define IO_PRINT_ERROR3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_IO, LEVEL_ERROR, "!!!"fmt, 3, arg0, arg1, arg2)
+#define IO_PRINT_ERROR4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_IO, LEVEL_ERROR, "!!!"fmt, 4, arg0, arg1, arg2, arg3)
+#define IO_PRINT_ERROR5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_IO, LEVEL_ERROR, "!!!"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define IO_PRINT_ERROR6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_IO, LEVEL_ERROR, "!!!"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define IO_PRINT_ERROR7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_IO, LEVEL_ERROR, "!!!"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define IO_PRINT_ERROR8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_IO, LEVEL_ERROR, "!!!"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define IO_PRINT_WARN0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_IO, LEVEL_WARN, "!!*"fmt, 0)
+#define IO_PRINT_WARN1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_IO, LEVEL_WARN, "!!*"fmt, 1, arg0)
+#define IO_PRINT_WARN2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_IO, LEVEL_WARN, "!!*"fmt, 2, arg0, arg1)
+#define IO_PRINT_WARN3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_IO, LEVEL_WARN, "!!*"fmt, 3, arg0, arg1, arg2)
+#define IO_PRINT_WARN4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_IO, LEVEL_WARN, "!!*"fmt, 4, arg0, arg1, arg2, arg3)
+#define IO_PRINT_WARN5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_IO, LEVEL_WARN, "!!*"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define IO_PRINT_WARN6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_IO, LEVEL_WARN, "!!*"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define IO_PRINT_WARN7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_IO, LEVEL_WARN, "!!*"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define IO_PRINT_WARN8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_IO, LEVEL_WARN, "!!*"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define IO_PRINT_INFO0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_IO, LEVEL_INFO, "!**"fmt, 0)
+#define IO_PRINT_INFO1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_IO, LEVEL_INFO, "!**"fmt, 1, arg0)
+#define IO_PRINT_INFO2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_IO, LEVEL_INFO, "!**"fmt, 2, arg0, arg1)
+#define IO_PRINT_INFO3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_IO, LEVEL_INFO, "!**"fmt, 3, arg0, arg1, arg2)
+#define IO_PRINT_INFO4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_IO, LEVEL_INFO, "!**"fmt, 4, arg0, arg1, arg2, arg3)
+#define IO_PRINT_INFO5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_IO, LEVEL_INFO, "!**"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define IO_PRINT_INFO6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_IO, LEVEL_INFO, "!**"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define IO_PRINT_INFO7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_IO, LEVEL_INFO, "!**"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define IO_PRINT_INFO8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_IO, LEVEL_INFO, "!**"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define IO_PRINT_TRACE0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_IO, LEVEL_TRACE, fmt, 0)
+#define IO_PRINT_TRACE1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_IO, LEVEL_TRACE, fmt, 1, arg0)
+#define IO_PRINT_TRACE2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_IO, LEVEL_TRACE, fmt, 2, arg0, arg1)
+#define IO_PRINT_TRACE3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_IO, LEVEL_TRACE, fmt, 3, arg0, arg1, arg2)
+#define IO_PRINT_TRACE4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_IO, LEVEL_TRACE, fmt, 4, arg0, arg1, arg2, arg3)
+#define IO_PRINT_TRACE5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_IO, LEVEL_TRACE, fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define IO_PRINT_TRACE6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_IO, LEVEL_TRACE, fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define IO_PRINT_TRACE7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_IO, LEVEL_TRACE, fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define IO_PRINT_TRACE8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_IO, LEVEL_TRACE, fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+
+/* UART Trace Interfaces */
+#define UART_PRINT_ERROR0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_UART, LEVEL_ERROR, "!!!"fmt, 0)
+#define UART_PRINT_ERROR1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_UART, LEVEL_ERROR, "!!!"fmt, 1, arg0)
+#define UART_PRINT_ERROR2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_UART, LEVEL_ERROR, "!!!"fmt, 2, arg0, arg1)
+#define UART_PRINT_ERROR3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_UART, LEVEL_ERROR, "!!!"fmt, 3, arg0, arg1, arg2)
+#define UART_PRINT_ERROR4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_UART, LEVEL_ERROR, "!!!"fmt, 4, arg0, arg1, arg2, arg3)
+#define UART_PRINT_ERROR5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_UART, LEVEL_ERROR, "!!!"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define UART_PRINT_ERROR6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_UART, LEVEL_ERROR, "!!!"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define UART_PRINT_ERROR7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_UART, LEVEL_ERROR, "!!!"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define UART_PRINT_ERROR8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_UART, LEVEL_ERROR, "!!!"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define UART_PRINT_WARN0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_UART, LEVEL_WARN, "!!*"fmt, 0)
+#define UART_PRINT_WARN1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_UART, LEVEL_WARN, "!!*"fmt, 1, arg0)
+#define UART_PRINT_WARN2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_UART, LEVEL_WARN, "!!*"fmt, 2, arg0, arg1)
+#define UART_PRINT_WARN3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_UART, LEVEL_WARN, "!!*"fmt, 3, arg0, arg1, arg2)
+#define UART_PRINT_WARN4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_UART, LEVEL_WARN, "!!*"fmt, 4, arg0, arg1, arg2, arg3)
+#define UART_PRINT_WARN5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_UART, LEVEL_WARN, "!!*"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define UART_PRINT_WARN6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_UART, LEVEL_WARN, "!!*"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define UART_PRINT_WARN7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_UART, LEVEL_WARN, "!!*"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define UART_PRINT_WARN8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_UART, LEVEL_WARN, "!!*"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define UART_PRINT_INFO0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_UART, LEVEL_INFO, "!**"fmt, 0)
+#define UART_PRINT_INFO1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_UART, LEVEL_INFO, "!**"fmt, 1, arg0)
+#define UART_PRINT_INFO2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_UART, LEVEL_INFO, "!**"fmt, 2, arg0, arg1)
+#define UART_PRINT_INFO3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_UART, LEVEL_INFO, "!**"fmt, 3, arg0, arg1, arg2)
+#define UART_PRINT_INFO4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_UART, LEVEL_INFO, "!**"fmt, 4, arg0, arg1, arg2, arg3)
+#define UART_PRINT_INFO5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_UART, LEVEL_INFO, "!**"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define UART_PRINT_INFO6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_UART, LEVEL_INFO, "!**"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define UART_PRINT_INFO7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_UART, LEVEL_INFO, "!**"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define UART_PRINT_INFO8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_UART, LEVEL_INFO, "!**"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define UART_PRINT_TRACE0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_UART, LEVEL_TRACE, fmt, 0)
+#define UART_PRINT_TRACE1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_UART, LEVEL_TRACE, fmt, 1, arg0)
+#define UART_PRINT_TRACE2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_UART, LEVEL_TRACE, fmt, 2, arg0, arg1)
+#define UART_PRINT_TRACE3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_UART, LEVEL_TRACE, fmt, 3, arg0, arg1, arg2)
+#define UART_PRINT_TRACE4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_UART, LEVEL_TRACE, fmt, 4, arg0, arg1, arg2, arg3)
+#define UART_PRINT_TRACE5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_UART, LEVEL_TRACE, fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define UART_PRINT_TRACE6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_UART, LEVEL_TRACE, fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define UART_PRINT_TRACE7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_UART, LEVEL_TRACE, fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define UART_PRINT_TRACE8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_UART, LEVEL_TRACE, fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+
+/* CODEC Trace Interfaces */
+#define CODEC_PRINT_ERROR0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CODEC, LEVEL_ERROR, "!!!"fmt, 0)
+#define CODEC_PRINT_ERROR1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CODEC, LEVEL_ERROR, "!!!"fmt, 1, arg0)
+#define CODEC_PRINT_ERROR2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CODEC, LEVEL_ERROR, "!!!"fmt, 2, arg0, arg1)
+#define CODEC_PRINT_ERROR3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CODEC, LEVEL_ERROR, "!!!"fmt, 3, arg0, arg1, arg2)
+#define CODEC_PRINT_ERROR4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CODEC, LEVEL_ERROR, "!!!"fmt, 4, arg0, arg1, arg2, arg3)
+#define CODEC_PRINT_ERROR5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CODEC, LEVEL_ERROR, "!!!"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define CODEC_PRINT_ERROR6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CODEC, LEVEL_ERROR, "!!!"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define CODEC_PRINT_ERROR7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CODEC, LEVEL_ERROR, "!!!"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define CODEC_PRINT_ERROR8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CODEC, LEVEL_ERROR, "!!!"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define CODEC_PRINT_WARN0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CODEC, LEVEL_WARN, "!!*"fmt, 0)
+#define CODEC_PRINT_WARN1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CODEC, LEVEL_WARN, "!!*"fmt, 1, arg0)
+#define CODEC_PRINT_WARN2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CODEC, LEVEL_WARN, "!!*"fmt, 2, arg0, arg1)
+#define CODEC_PRINT_WARN3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CODEC, LEVEL_WARN, "!!*"fmt, 3, arg0, arg1, arg2)
+#define CODEC_PRINT_WARN4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CODEC, LEVEL_WARN, "!!*"fmt, 4, arg0, arg1, arg2, arg3)
+#define CODEC_PRINT_WARN5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CODEC, LEVEL_WARN, "!!*"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define CODEC_PRINT_WARN6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CODEC, LEVEL_WARN, "!!*"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define CODEC_PRINT_WARN7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CODEC, LEVEL_WARN, "!!*"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define CODEC_PRINT_WARN8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CODEC, LEVEL_WARN, "!!*"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define CODEC_PRINT_INFO0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CODEC, LEVEL_INFO, "!**"fmt, 0)
+#define CODEC_PRINT_INFO1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CODEC, LEVEL_INFO, "!**"fmt, 1, arg0)
+#define CODEC_PRINT_INFO2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CODEC, LEVEL_INFO, "!**"fmt, 2, arg0, arg1)
+#define CODEC_PRINT_INFO3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CODEC, LEVEL_INFO, "!**"fmt, 3, arg0, arg1, arg2)
+#define CODEC_PRINT_INFO4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CODEC, LEVEL_INFO, "!**"fmt, 4, arg0, arg1, arg2, arg3)
+#define CODEC_PRINT_INFO5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CODEC, LEVEL_INFO, "!**"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define CODEC_PRINT_INFO6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CODEC, LEVEL_INFO, "!**"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define CODEC_PRINT_INFO7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CODEC, LEVEL_INFO, "!**"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define CODEC_PRINT_INFO8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CODEC, LEVEL_INFO, "!**"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define CODEC_PRINT_TRACE0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CODEC, LEVEL_TRACE, fmt, 0)
+#define CODEC_PRINT_TRACE1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CODEC, LEVEL_TRACE, fmt, 1, arg0)
+#define CODEC_PRINT_TRACE2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CODEC, LEVEL_TRACE, fmt, 2, arg0, arg1)
+#define CODEC_PRINT_TRACE3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CODEC, LEVEL_TRACE, fmt, 3, arg0, arg1, arg2)
+#define CODEC_PRINT_TRACE4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CODEC, LEVEL_TRACE, fmt, 4, arg0, arg1, arg2, arg3)
+#define CODEC_PRINT_TRACE5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CODEC, LEVEL_TRACE, fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define CODEC_PRINT_TRACE6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CODEC, LEVEL_TRACE, fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define CODEC_PRINT_TRACE7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CODEC, LEVEL_TRACE, fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define CODEC_PRINT_TRACE8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_CODEC, LEVEL_TRACE, fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+
+/* DIPC Trace Interfaces */
+#define DIPC_PRINT_ERROR0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DIPC, LEVEL_ERROR, "!!!"fmt, 0)
+#define DIPC_PRINT_ERROR1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DIPC, LEVEL_ERROR, "!!!"fmt, 1, arg0)
+#define DIPC_PRINT_ERROR2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DIPC, LEVEL_ERROR, "!!!"fmt, 2, arg0, arg1)
+#define DIPC_PRINT_ERROR3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DIPC, LEVEL_ERROR, "!!!"fmt, 3, arg0, arg1, arg2)
+#define DIPC_PRINT_ERROR4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DIPC, LEVEL_ERROR, "!!!"fmt, 4, arg0, arg1, arg2, arg3)
+#define DIPC_PRINT_ERROR5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DIPC, LEVEL_ERROR, "!!!"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define DIPC_PRINT_ERROR6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DIPC, LEVEL_ERROR, "!!!"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define DIPC_PRINT_ERROR7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DIPC, LEVEL_ERROR, "!!!"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define DIPC_PRINT_ERROR8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DIPC, LEVEL_ERROR, "!!!"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define DIPC_PRINT_WARN0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DIPC, LEVEL_WARN, "!!*"fmt, 0)
+#define DIPC_PRINT_WARN1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DIPC, LEVEL_WARN, "!!*"fmt, 1, arg0)
+#define DIPC_PRINT_WARN2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DIPC, LEVEL_WARN, "!!*"fmt, 2, arg0, arg1)
+#define DIPC_PRINT_WARN3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DIPC, LEVEL_WARN, "!!*"fmt, 3, arg0, arg1, arg2)
+#define DIPC_PRINT_WARN4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DIPC, LEVEL_WARN, "!!*"fmt, 4, arg0, arg1, arg2, arg3)
+#define DIPC_PRINT_WARN5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DIPC, LEVEL_WARN, "!!*"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define DIPC_PRINT_WARN6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DIPC, LEVEL_WARN, "!!*"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define DIPC_PRINT_WARN7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DIPC, LEVEL_WARN, "!!*"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define DIPC_PRINT_WARN8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DIPC, LEVEL_WARN, "!!*"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define DIPC_PRINT_INFO0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DIPC, LEVEL_INFO, "!**"fmt, 0)
+#define DIPC_PRINT_INFO1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DIPC, LEVEL_INFO, "!**"fmt, 1, arg0)
+#define DIPC_PRINT_INFO2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DIPC, LEVEL_INFO, "!**"fmt, 2, arg0, arg1)
+#define DIPC_PRINT_INFO3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DIPC, LEVEL_INFO, "!**"fmt, 3, arg0, arg1, arg2)
+#define DIPC_PRINT_INFO4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DIPC, LEVEL_INFO, "!**"fmt, 4, arg0, arg1, arg2, arg3)
+#define DIPC_PRINT_INFO5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DIPC, LEVEL_INFO, "!**"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define DIPC_PRINT_INFO6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DIPC, LEVEL_INFO, "!**"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define DIPC_PRINT_INFO7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DIPC, LEVEL_INFO, "!**"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define DIPC_PRINT_INFO8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DIPC, LEVEL_INFO, "!**"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define DIPC_PRINT_TRACE0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DIPC, LEVEL_TRACE, fmt, 0)
+#define DIPC_PRINT_TRACE1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DIPC, LEVEL_TRACE, fmt, 1, arg0)
+#define DIPC_PRINT_TRACE2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DIPC, LEVEL_TRACE, fmt, 2, arg0, arg1)
+#define DIPC_PRINT_TRACE3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DIPC, LEVEL_TRACE, fmt, 3, arg0, arg1, arg2)
+#define DIPC_PRINT_TRACE4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DIPC, LEVEL_TRACE, fmt, 4, arg0, arg1, arg2, arg3)
+#define DIPC_PRINT_TRACE5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DIPC, LEVEL_TRACE, fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define DIPC_PRINT_TRACE6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DIPC, LEVEL_TRACE, fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define DIPC_PRINT_TRACE7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DIPC, LEVEL_TRACE, fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define DIPC_PRINT_TRACE8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_DIPC, LEVEL_TRACE, fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+
+/* MMI Trace Interfaces */
+#define MMI_PRINT_ERROR0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_MMI, LEVEL_ERROR, "!!!"fmt, 0)
+#define MMI_PRINT_ERROR1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_MMI, LEVEL_ERROR, "!!!"fmt, 1, arg0)
+#define MMI_PRINT_ERROR2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_MMI, LEVEL_ERROR, "!!!"fmt, 2, arg0, arg1)
+#define MMI_PRINT_ERROR3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_MMI, LEVEL_ERROR, "!!!"fmt, 3, arg0, arg1, arg2)
+#define MMI_PRINT_ERROR4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_MMI, LEVEL_ERROR, "!!!"fmt, 4, arg0, arg1, arg2, arg3)
+#define MMI_PRINT_ERROR5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_MMI, LEVEL_ERROR, "!!!"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define MMI_PRINT_ERROR6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_MMI, LEVEL_ERROR, "!!!"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define MMI_PRINT_ERROR7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_MMI, LEVEL_ERROR, "!!!"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define MMI_PRINT_ERROR8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_MMI, LEVEL_ERROR, "!!!"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define MMI_PRINT_WARN0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_MMI, LEVEL_WARN, "!!*"fmt, 0)
+#define MMI_PRINT_WARN1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_MMI, LEVEL_WARN, "!!*"fmt, 1, arg0)
+#define MMI_PRINT_WARN2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_MMI, LEVEL_WARN, "!!*"fmt, 2, arg0, arg1)
+#define MMI_PRINT_WARN3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_MMI, LEVEL_WARN, "!!*"fmt, 3, arg0, arg1, arg2)
+#define MMI_PRINT_WARN4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_MMI, LEVEL_WARN, "!!*"fmt, 4, arg0, arg1, arg2, arg3)
+#define MMI_PRINT_WARN5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_MMI, LEVEL_WARN, "!!*"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define MMI_PRINT_WARN6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_MMI, LEVEL_WARN, "!!*"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define MMI_PRINT_WARN7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_MMI, LEVEL_WARN, "!!*"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define MMI_PRINT_WARN8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_MMI, LEVEL_WARN, "!!*"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define MMI_PRINT_INFO0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_MMI, LEVEL_INFO, "!**"fmt, 0)
+#define MMI_PRINT_INFO1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_MMI, LEVEL_INFO, "!**"fmt, 1, arg0)
+#define MMI_PRINT_INFO2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_MMI, LEVEL_INFO, "!**"fmt, 2, arg0, arg1)
+#define MMI_PRINT_INFO3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_MMI, LEVEL_INFO, "!**"fmt, 3, arg0, arg1, arg2)
+#define MMI_PRINT_INFO4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_MMI, LEVEL_INFO, "!**"fmt, 4, arg0, arg1, arg2, arg3)
+#define MMI_PRINT_INFO5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_MMI, LEVEL_INFO, "!**"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define MMI_PRINT_INFO6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_MMI, LEVEL_INFO, "!**"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define MMI_PRINT_INFO7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_MMI, LEVEL_INFO, "!**"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define MMI_PRINT_INFO8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_MMI, LEVEL_INFO, "!**"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define MMI_PRINT_TRACE0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_MMI, LEVEL_TRACE, fmt, 0)
+#define MMI_PRINT_TRACE1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_MMI, LEVEL_TRACE, fmt, 1, arg0)
+#define MMI_PRINT_TRACE2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_MMI, LEVEL_TRACE, fmt, 2, arg0, arg1)
+#define MMI_PRINT_TRACE3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_MMI, LEVEL_TRACE, fmt, 3, arg0, arg1, arg2)
+#define MMI_PRINT_TRACE4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_MMI, LEVEL_TRACE, fmt, 4, arg0, arg1, arg2, arg3)
+#define MMI_PRINT_TRACE5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_MMI, LEVEL_TRACE, fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define MMI_PRINT_TRACE6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_MMI, LEVEL_TRACE, fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define MMI_PRINT_TRACE7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_MMI, LEVEL_TRACE, fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define MMI_PRINT_TRACE8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_MMI, LEVEL_TRACE, fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+
+/* SDIO Trace Interfaces */
+#define SDIO_PRINT_ERROR0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SDIO, LEVEL_ERROR, "!!!"fmt, 0)
+#define SDIO_PRINT_ERROR1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SDIO, LEVEL_ERROR, "!!!"fmt, 1, arg0)
+#define SDIO_PRINT_ERROR2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SDIO, LEVEL_ERROR, "!!!"fmt, 2, arg0, arg1)
+#define SDIO_PRINT_ERROR3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SDIO, LEVEL_ERROR, "!!!"fmt, 3, arg0, arg1, arg2)
+#define SDIO_PRINT_ERROR4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SDIO, LEVEL_ERROR, "!!!"fmt, 4, arg0, arg1, arg2, arg3)
+#define SDIO_PRINT_ERROR5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SDIO, LEVEL_ERROR, "!!!"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define SDIO_PRINT_ERROR6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SDIO, LEVEL_ERROR, "!!!"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define SDIO_PRINT_ERROR7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SDIO, LEVEL_ERROR, "!!!"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define SDIO_PRINT_ERROR8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SDIO, LEVEL_ERROR, "!!!"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define SDIO_PRINT_WARN0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SDIO, LEVEL_WARN, "!!*"fmt, 0)
+#define SDIO_PRINT_WARN1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SDIO, LEVEL_WARN, "!!*"fmt, 1, arg0)
+#define SDIO_PRINT_WARN2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SDIO, LEVEL_WARN, "!!*"fmt, 2, arg0, arg1)
+#define SDIO_PRINT_WARN3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SDIO, LEVEL_WARN, "!!*"fmt, 3, arg0, arg1, arg2)
+#define SDIO_PRINT_WARN4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SDIO, LEVEL_WARN, "!!*"fmt, 4, arg0, arg1, arg2, arg3)
+#define SDIO_PRINT_WARN5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SDIO, LEVEL_WARN, "!!*"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define SDIO_PRINT_WARN6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SDIO, LEVEL_WARN, "!!*"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define SDIO_PRINT_WARN7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SDIO, LEVEL_WARN, "!!*"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define SDIO_PRINT_WARN8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SDIO, LEVEL_WARN, "!!*"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define SDIO_PRINT_INFO0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SDIO, LEVEL_INFO, "!**"fmt, 0)
+#define SDIO_PRINT_INFO1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SDIO, LEVEL_INFO, "!**"fmt, 1, arg0)
+#define SDIO_PRINT_INFO2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SDIO, LEVEL_INFO, "!**"fmt, 2, arg0, arg1)
+#define SDIO_PRINT_INFO3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SDIO, LEVEL_INFO, "!**"fmt, 3, arg0, arg1, arg2)
+#define SDIO_PRINT_INFO4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SDIO, LEVEL_INFO, "!**"fmt, 4, arg0, arg1, arg2, arg3)
+#define SDIO_PRINT_INFO5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SDIO, LEVEL_INFO, "!**"fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define SDIO_PRINT_INFO6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SDIO, LEVEL_INFO, "!**"fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define SDIO_PRINT_INFO7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SDIO, LEVEL_INFO, "!**"fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define SDIO_PRINT_INFO8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SDIO, LEVEL_INFO, "!**"fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+#define SDIO_PRINT_TRACE0(fmt)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SDIO, LEVEL_TRACE, fmt, 0)
+#define SDIO_PRINT_TRACE1(fmt, arg0)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SDIO, LEVEL_TRACE, fmt, 1, arg0)
+#define SDIO_PRINT_TRACE2(fmt, arg0, arg1)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SDIO, LEVEL_TRACE, fmt, 2, arg0, arg1)
+#define SDIO_PRINT_TRACE3(fmt, arg0, arg1, arg2)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SDIO, LEVEL_TRACE, fmt, 3, arg0, arg1, arg2)
+#define SDIO_PRINT_TRACE4(fmt, arg0, arg1, arg2, arg3)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SDIO, LEVEL_TRACE, fmt, 4, arg0, arg1, arg2, arg3)
+#define SDIO_PRINT_TRACE5(fmt, arg0, arg1, arg2, arg3, arg4)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SDIO, LEVEL_TRACE, fmt, 5, arg0, arg1, arg2, arg3, arg4)
+#define SDIO_PRINT_TRACE6(fmt, arg0, arg1, arg2, arg3, arg4, arg5)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SDIO, LEVEL_TRACE, fmt, 6, arg0, arg1, arg2, arg3, arg4, arg5)
+#define SDIO_PRINT_TRACE7(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SDIO, LEVEL_TRACE, fmt, 7, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
+#define SDIO_PRINT_TRACE8(fmt, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)   \
+    DBG_BUFFER(LOG_TYPE, SUBTYPE_FORMAT, MODULE_SDIO, LEVEL_TRACE, fmt, 8, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7)
+
+/*Fixed time stamp after out DLPS*/
+extern void (*timestamp_enter_dlps_cb)(void);
+extern void (*timestamp_exit_dlps_cb)(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _TRACE_H_ */
diff --git a/bee/logging/inc/rtl87x2j/log_core.h b/bee/logging/inc/rtl87x2j/log_core.h
new file mode 100644
index 00000000..a543e828
--- /dev/null
+++ b/bee/logging/inc/rtl87x2j/log_core.h
@@ -0,0 +1,391 @@
+/**
+ * Copyright (c) 2017, Realtek Semiconductor Corporation. All rights reserved.
+ */
+
+#ifndef _LOG_CORE_H_
+#define _LOG_CORE_H_
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "section.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/**
+ * \defgroup    TRACE       Trace
+ *
+ * \brief       Defines debug trace macros for each module.
+ *
+ */
+
+#if defined(CONFIG_SOC_SERIES_RTL87X3J_NETPROCESSOR)
+#define RTL87X3J_NETPROCESSOR_SUBTYPE_MASK  (0x20)
+#define SUBTYPE_MASK  (0x1F)
+#define GET_SUBTYPE(subtype) ((subtype) | RTL87X3J_NETPROCESSOR_SUBTYPE_MASK)
+#define GET_SUBTYPE_MASK_VALUE(subtype)  (subtype & SUBTYPE_MASK)
+#else
+#define GET_SUBTYPE(subtype) (subtype)
+#define GET_SUBTYPE_MASK_VALUE(subtype)  (subtype)
+#endif
+
+
+/* Log Section Definition */
+#define TRACE_DATA __attribute__((section(".TRACE"))) __attribute__((aligned(4))) __attribute__((used))
+
+#define LOG_MESSAGE_SYNC_CODE       0x7E
+#define MAX_LOG_MESSAGE_LEN         252
+#define MAX_ARGUMENT_SIZE           20
+
+
+#define LOG_BINARY_MASK             BIT0
+#define LOG_ASCII_MASK              BIT1
+
+#define LOG_OUTPUT_UART_MASK        BIT0
+#define LOG_OUTPUT_FLASH_MASK       BIT1
+#define LOG_OUTPUT_VENDOR_MASK      BIT2
+
+/**
+ * log_core.h
+ *
+ * \name    TRACE_LEVEL
+ * \brief   Log Level Definition.
+ * \anchor  TRACE_LEVEL
+ */
+/**
+ * \ingroup TRACE
+ */
+/**@{*/
+#define LEVEL_OFF       (-1)
+#define LEVEL_ERROR     (0)
+#define LEVEL_WARN      (1)
+#define LEVEL_INFO      (2)
+#define LEVEL_TRACE     (3)
+#define LEVEL_NUM       (4)
+/**@}*/
+
+/*
+ * DBG_LEVEL is used to control the log printed by DBG_BUFFER(), DBG_INDEX() and DBG_TEXT().
+ * LEVEL_OFF   : Print None
+ * LEVEL_ERROR : Print ERROR
+ * LEVEL_WARN  : Print ERROR, WARN
+ * LEVEL_INFO  : Print ERROR, WARN, INFO
+ * LEVEL_TRACE : Print ERROR, WARN, INFO, TRACE
+ */
+#define DBG_LEVEL               LEVEL_TRACE
+
+/** Log subtype definition:
+ * bit0 ~ bit4: sub type value,
+ * bit5 ~ bit6: log version 0 (reserved),
+ *              log version 1( b'00: AP core, b'01: NP core, b'10 and b'11: reserved).
+ * bit7: 1 dsp log, 0 mcu log.
+ * max subtype value is 0x1F.
+*/
+typedef enum
+{
+    SUBTYPE_BDADDR                  = 0x00,
+    SUBTYPE_STRING                  = 0x01,
+    SUBTYPE_BINARY                  = 0x02,
+    SUBTYPE_DOUBLE                  = 0x03,
+    SUBTYPE_UINT64                  = 0x04,
+
+    SUBTYPE_FORMAT                  = 0x10,
+    SUBTYPE_DIRECT                  = 0x11,
+    SUBTYPE_TEXT                    = 0x12,
+    SUBTYPE_DOWN_MESSAGE            = 0x13,
+    SUBTYPE_UP_MESSAGE              = 0x14,
+    SUBTYPE_DOWN_SNOOP              = 0x15,
+    SUBTYPE_UP_SNOOP                = 0x16,
+    SUBTYPE_LOWERSTACK              = 0x17,
+    SUBTYPE_INDEX                   = 0x18,
+    SUBTYPE_STACK_INDEX             = 0x19,
+    SUBTYPE_SNOOP2                  = 0x1A,
+
+    SUBTYPE_MAX                     = 0x1F,
+
+} T_LOG_SUBTYPE;
+
+/* Internal function that is used by internal macro DBG_DIRECT. */
+extern void log_direct(const char *fmt, ...);
+
+/* Internal function that is used by internal macro DBG_BUFFER. */
+void log_buffer(uint8_t module, uint8_t param_no, uint32_t str_index, ...);
+
+/* Internal function that is used by internal macro DBG_LOWERSTACK. */
+void log_buffer_bt_controller(uint32_t str_index, uint32_t param_num, ...);
+
+/* Internal function that is used by internal macro DBG_INDEX. */
+void log_index(uint8_t subtype, uint8_t module, uint8_t param_no, uint32_t str_index,  ...);
+
+/* Internal function that is used by internal macro DBG_TEXT. */
+void log_text(uint32_t info, const char *fmt, ...);
+
+/* Internal function that is used by internal macro DBG_STREAM. */
+void log_stream(T_LOG_SUBTYPE subtype, uint8_t module, uint16_t length, uint8_t *p_data);
+
+/* Internal function that is used by internal macro TRACE_STRING. */
+uint32_t trace_string(char *p_data);
+
+/* Internal function that is used by internal macro TRACE_BINARY. */
+uint32_t log_trace_binary(uint16_t length, char *p_data);
+
+/* Internal function that is used by internal macro TRACE_BDADDR. */
+uint32_t log_trace_bdaddr(char *bd_addr);
+
+/* Internal function that is used by internal macro DBG_SNOOP2. */
+extern void log_snoop2(uint32_t info, uint16_t length, uint8_t *p_snoop);
+
+/* Internal function that is used by public macro TRACE_FLOAT. */
+static inline uint32_t trace_float(float param)
+{
+    return *((uint32_t *)&param);
+}
+
+/* Internal function that is used by public macro TRACE_UINT64. */
+uint32_t trace_uint64(uint64_t param);
+
+/* Internal function that is used by public macro TRACE_DOUBLE. */
+uint32_t trace_double(double param);
+
+/* Internal macro */
+#define COMBINE_TRACE_INFO(module, level)   (uint8_t)( ((level) << 6) | ((module) & 0x3F))
+#define COMBINE_SNOOP_INFO(entity_id, protocol_type, dir)  (uint32_t)((dir << 16) + (protocol_type << 8) + entity_id)
+
+
+#define COUNT_ARGS_(t0,t1,t2,t3,t4,t5,t6,t7,t8,t9,t10,t11,t12,t13,t14,t15,t16,t17,t18,t19,t20,t21,t22,t23,t24,t25,t26,t27,t28,t29,t30,t31,t32,t33,t34,t35,t36,t37,t38,t39,cnt,...) cnt
+#define COUNT_ARGS(...) COUNT_ARGS_(,##__VA_ARGS__,39,38,37,36,35,34,33,32,31,30,29,28,27,26,25,24,23,22,21,20,19,18,17,16,15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0)
+
+/* Internal macro that is wrapped by internal macro DBG_BUFFER. */
+#define DBG_BUFFER_INTERNAL_WRAPPER( sub_type, module, level, fmt, param_num, ...) do {\
+        static const char format[] TRACE_DATA = fmt;\
+        log_buffer(COMBINE_TRACE_INFO(module, level), param_num,(uint32_t)format, ##__VA_ARGS__);\
+    } while (0)
+#define DBG_INDEX_INTERNAL_WRAPPER( sub_type, module, level, fmt, param_num, ...) do {\
+        log_index(sub_type, COMBINE_TRACE_INFO(module, level), param_num, fmt, ##__VA_ARGS__);\
+    } while (0)
+
+/* Internal macro to remove param num. */
+#define DBG_BUFFER_INTERNAL(sub_type, module, level, fmt, ...)  do {\
+        DBG_BUFFER_INTERNAL_WRAPPER(sub_type, module, level, fmt, COUNT_ARGS(__VA_ARGS__), ##__VA_ARGS__) ;\
+    } while (0)
+#define DBG_INDEX_INTERNAL(sub_type, module, level, fmt, ...) do {\
+        DBG_INDEX_INTERNAL_WRAPPER(sub_type, module, level, fmt, COUNT_ARGS(__VA_ARGS__), ##__VA_ARGS__);\
+    } while (0)
+
+
+#if (DBG_LEVEL >= LEVEL_ERROR)
+#define DBG_BUFFER_LEVEL_ERROR( sub_type, module, fmt, ...) do {\
+        DBG_BUFFER_INTERNAL( sub_type, module, LEVEL_ERROR, fmt, ##__VA_ARGS__);\
+    } while (0)
+#define DBG_INDEX_LEVEL_ERROR( sub_type, module, fmt, ...) do {\
+        DBG_INDEX_INTERNAL(sub_type, module, LEVEL_ERROR, fmt, ##__VA_ARGS__);\
+    } while (0)
+#define DBG_TEXT_LEVEL_ERROR( sub_type, module, fmt, ...) do {\
+        log_text(COMBINE_TRACE_INFO(module, LEVEL_ERROR), fmt, ##__VA_ARGS__);\
+    } while (0)
+#define DBG_STREAM_LEVEL_ERROR(  sub_type, module, level, length, p_data) do {\
+        log_stream(sub_type, COMBINE_TRACE_INFO( module, LEVEL_ERROR), length, (uint8_t *)p_data);\
+    } while (0)
+#else
+#define DBG_BUFFER_LEVEL_ERROR( sub_type, module, fmt, ...)
+#define DBG_INDEX_LEVEL_ERROR( sub_type, module, fmt, ...)
+#define DBG_TEXT_LEVEL_ERROR( sub_type, module, fmt, ...)
+#define DBG_STREAM_LEVEL_ERROR(  sub_type, module, level, length, p_data)
+#endif
+
+#if (DBG_LEVEL >= LEVEL_WARN)
+#define DBG_BUFFER_LEVEL_WARN( sub_type, module, fmt, ...)  do {\
+        DBG_BUFFER_INTERNAL( sub_type, module, LEVEL_WARN, fmt, ##__VA_ARGS__);\
+    } while (0)
+#define DBG_INDEX_LEVEL_WARN( sub_type, module, fmt, ...) do {\
+        DBG_INDEX_INTERNAL(sub_type, module, LEVEL_WARN, fmt, ##__VA_ARGS__);\
+    } while (0)
+#define DBG_TEXT_LEVEL_WARN( sub_type, module, fmt, ...) do {\
+        log_text(COMBINE_TRACE_INFO(module, LEVEL_WARN), fmt, ##__VA_ARGS__);\
+    } while (0)
+#define DBG_STREAM_LEVEL_WARN( sub_type, module, level, length, p_data) do {\
+        log_stream(sub_type, COMBINE_TRACE_INFO( module, LEVEL_WARN), length, (uint8_t *)p_data);\
+    } while (0)
+#else
+#define DBG_BUFFER_LEVEL_WARN( sub_type, module, fmt, ...)
+#define DBG_INDEX_LEVEL_WARN( sub_type, module, fmt, ...)
+#define DBG_TEXT_LEVEL_WARN( sub_type, module, fmt, ...)
+#define DBG_STREAM_LEVEL_ERROR( sub_type, module, level, length, p_data)
+#endif
+
+#if (DBG_LEVEL >= LEVEL_INFO)
+#define DBG_BUFFER_LEVEL_INFO( sub_type, module, fmt, ...)  do {\
+        DBG_BUFFER_INTERNAL( sub_type, module, LEVEL_INFO, fmt, ##__VA_ARGS__);\
+    } while (0)
+#define DBG_INDEX_LEVEL_INFO( sub_type, module, fmt, ...) do {\
+        DBG_INDEX_INTERNAL(sub_type, module, LEVEL_INFO, fmt, ##__VA_ARGS__);\
+    } while (0)
+#define DBG_TEXT_LEVEL_INFO( sub_type, module, fmt, ...) do {\
+        log_text(COMBINE_TRACE_INFO(module, LEVEL_INFO), fmt, ##__VA_ARGS__);\
+    } while (0)
+#define DBG_STREAM_LEVEL_INFO(  sub_type, module, level, length, p_data) do {\
+        log_stream(sub_type, COMBINE_TRACE_INFO(module, LEVEL_INFO), length, (uint8_t *)p_data);\
+    } while (0)
+#else
+#define DBG_BUFFER_LEVEL_INFO( sub_type, module, fmt, ...)
+#define DBG_INDEX_LEVEL_INFO( sub_type, module, fmt, ...)
+#define DBG_TEXT_LEVEL_INFO( sub_type, module, fmt, ...)
+#define DBG_STREAM_LEVEL_ERROR( sub_type, module, level, length, p_data)
+#endif
+
+#if (DBG_LEVEL >= LEVEL_TRACE)
+#define DBG_BUFFER_LEVEL_TRACE( sub_type, module, fmt, ...) do {\
+        DBG_BUFFER_INTERNAL( sub_type, module, LEVEL_TRACE, fmt, ##__VA_ARGS__);\
+    } while (0)
+#define DBG_INDEX_LEVEL_TRACE( sub_type, module, fmt, ...) do {\
+        DBG_INDEX_INTERNAL(sub_type, module, LEVEL_TRACE, fmt, ##__VA_ARGS__);\
+    } while (0)
+#define DBG_TEXT_LEVEL_TRACE( sub_type, module, fmt, ...) do {\
+        log_text(COMBINE_TRACE_INFO(module, LEVEL_TRACE), fmt, ##__VA_ARGS__);\
+    } while (0)
+#define DBG_STREAM_LEVEL_TRACE(  sub_type, module, level, length, p_data) do {\
+        log_stream(sub_type, COMBINE_TRACE_INFO( module, LEVEL_TRACE), length, (uint8_t *)p_data);\
+    } while (0)
+#else
+#define DBG_BUFFER_LEVEL_TRACE( sub_type, module, fmt, ...)
+#define DBG_INDEX_LEVEL_TRACE( sub_type, module, fmt, ...)
+#define DBG_TEXT_LEVEL_TRACE( sub_type, module, fmt, ...)
+#define DBG_STREAM_LEVEL_ERROR( sub_type, module, fmt, ...)
+#endif
+
+#define DBG_BUFFER( sub_type, module, level, fmt,...)   \
+    DBG_BUFFER_##level( sub_type, module, fmt, ##__VA_ARGS__)
+
+#define DBG_INDEX( sub_type, module, level, fmt,...)   \
+    DBG_INDEX_##level( sub_type, module, fmt, ##__VA_ARGS__)
+
+#define DBG_TEXT( sub_type, module, level, fmt, ...)   \
+    DBG_TEXT_##level( sub_type, module, fmt, ##__VA_ARGS__)
+
+#define DBG_STREAM( sub_type, module, level, length, p_data)   \
+    DBG_STREAM_##level( sub_type, module, level, length, p_data)
+
+#define DBG_LOWERSTACK(color, file_num, line_num, str_index, ...)     do {\
+        log_buffer_bt_controller(str_index, COUNT_ARGS(__VA_ARGS__), ##__VA_ARGS__);\
+    } while (0)
+
+#define DIRECT_LOG(fmt, ...)     do {\
+        DBG_BUFFER_INTERNAL(GET_SUBTYPE(SUBTYPE_FORMAT), MODULE_BOOT, LEVEL_ERROR, fmt, ##__VA_ARGS__);\
+    } while (0)
+
+
+#define DBG_DIRECT(...)   do {\
+        log_direct(__VA_ARGS__);\
+    } while (0)
+
+/**
+ * log_core.h
+ *
+ * \name    AUXILIARY_PRINT_BDADDR
+ * \brief   Auxiliary Interface that is used to print BD address.
+ * \anchor  AUXILIARY_PRINT_BDADDR
+ */
+/**
+ * \ingroup TRACE
+ */
+#define TRACE_BDADDR(bd_addr)   \
+    log_trace_bdaddr((char *)bd_addr)
+
+/**
+ * log_core.h
+ *
+ * \name    AUXILIARY_PRINT_STRING
+ * \brief   Auxiliary Interface that is used to print string.
+ * \anchor  AUXILIARY_PRINT_STRING
+ */
+/**
+ * \ingroup TRACE
+ */
+#define TRACE_STRING(data)    \
+    trace_string((char *)(data))
+
+/**
+ * log_core.h
+ *
+ * \name    AUXILIARY_PRINT_BINARY
+ * \brief   Auxiliary Interface that is used to print binary string.
+ * \anchor  AUXILIARY_PRINT_BINARY
+ */
+/**
+ * \ingroup TRACE
+ */
+/**@{*/
+#define TRACE_BINARY(length, data)  \
+    log_trace_binary(length, (char *)(data))
+/**@}*/
+
+/**
+ * log_core.h
+ *
+ * \name    AUXILIARY_PRINT_FLOAT
+ * \brief   Auxiliary Interface that is used to print float.
+ * \anchor  AUXILIARY_PRINT_FLOAT
+ */
+/**
+ * \ingroup TRACE
+ */
+/**@{*/
+#define TRACE_FLOAT(param)   trace_float(param)
+/**@}*/
+
+/**
+ * log_core.h
+ *
+ * \name    AUXILIARY_PRINT_DOUBLE
+ * \brief   Auxiliary Interface that is used to print double.
+ * \anchor  AUXILIARY_PRINT_DOUBLE
+ */
+/**
+ * \ingroup TRACE
+ */
+/**@{*/
+#define TRACE_DOUBLE(param)  \
+    trace_double(param)
+/**
+ * trace.h
+ *
+ * \name    AUXILIARY_PRINT_UINT64
+ * \brief   Auxiliary Interface that is used to print uint64.
+ * \anchor  AUXILIARY_PRINT_UINT64
+ */
+/**
+ * \ingroup TRACE
+ */
+/**@{*/
+#define TRACE_UINT64(param)  \
+    trace_uint64(param)
+/**@}*/
+
+
+#define DBG_SNOOP(subtype, length, snoop)    do {\
+        log_snoop(subtype, length, snoop);\
+    } while (0)
+
+/*DBG_SNOOP2 with sub type SUBTYPE_SNOOP2*/
+#define DBG_SNOOP2(entity_id, protocol_type, dir, length, p_snoop)    do {\
+        log_snoop2(COMBINE_SNOOP_INFO(entity_id, protocol_type, dir), length, p_snoop);\
+    } while (0)
+
+#define LOG_ERROR( module, ...) \
+    DBG_BUFFER(GET_SUBTYPE(SUBTYPE_FORMAT), module, LEVEL_ERROR,  ##__VA_ARGS__)
+
+#define LOG_WARN( module, ...) \
+    DBG_BUFFER(GET_SUBTYPE(SUBTYPE_FORMAT), module, LEVEL_WARN,  ##__VA_ARGS__)
+
+#define LOG_INFO( module, ...) \
+    DBG_BUFFER(GET_SUBTYPE(SUBTYPE_FORMAT), module, LEVEL_INFO,  ##__VA_ARGS__)
+
+#define LOG_TRACE( module, ...) \
+    DBG_BUFFER(GET_SUBTYPE(SUBTYPE_FORMAT), module, LEVEL_TRACE, ##__VA_ARGS__)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _TRACE_H_ */
diff --git a/bee/logging/inc/rtl87x2j/log_uart.h b/bee/logging/inc/rtl87x2j/log_uart.h
new file mode 100644
index 00000000..fa0330f7
--- /dev/null
+++ b/bee/logging/inc/rtl87x2j/log_uart.h
@@ -0,0 +1 @@
+extern void log_uart_switch_clock_auto_mode(bool enable);
diff --git a/bee/logging/inc/rtl87x2j/soc_log.h b/bee/logging/inc/rtl87x2j/soc_log.h
new file mode 100644
index 00000000..b6c6121e
--- /dev/null
+++ b/bee/logging/inc/rtl87x2j/soc_log.h
@@ -0,0 +1,268 @@
+/**
+ * Copyright (c) 2017, Realtek Semiconductor Corporation. All rights reserved.
+ */
+
+#ifndef _SOC_LOG_H_
+#define _SOC_LOG_H_
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "log_core.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/**
+ * \defgroup    TRACE       Trace
+ *
+ * \brief       Defines debug trace macros for each module.
+ *
+ */
+#define LOG_VERSION    (1)
+
+/**
+ * log.h
+ *
+ * \name    MODULE_ID
+ * \brief   Module ID definition.
+ * \anchor  MODULE_ID
+ */
+/**
+ * \ingroup TRACE
+ */
+/**@{*/
+typedef enum
+{
+    /* platform modules */
+    MODULE_BOOT,
+    MODULE_PATCH,
+    MODULE_OS,
+    MODULE_OSIF,
+    MODULE_FS,
+    MODULE_DFU,
+    MODULE_DEBUG,
+    MODULE_CLOCK,
+
+    /* device modules */
+    MODULE_PERIPH,
+    MODULE_FMC,
+    MODULE_CRYPTO,
+
+    MODULE_PM,
+    MODULE_PHY,
+    MODULE_DVFS,
+    MODULE_CHARGER,
+
+    /* stack modules */
+    MODULE_PROFILE,
+    MODULE_PROTOCOL,
+    MODULE_GAP,
+    MODULE_BTE,
+    MODULE_BTIF,
+    MODULE_GATT,
+    MODULE_SMP,
+    MODULE_SDP,
+    MODULE_L2CAP,
+    MODULE_HCI,
+    MODULE_SNOOP,
+    MODULE_BTH,
+    MODULE_BTC,
+
+    MODULE_REG_BEGIN,
+
+    MODULE_NUM = 64,
+} T_MODULE_ID;
+/**@}*/
+
+/* Bluetooth HCI Snoop Trace Interfaces */
+#define BT_SNOOP_DOWN_TRACE(entity_id, length, snoop)  \
+    DBG_SNOOP2(entity_id, 0, SUBTYPE_DOWN_SNOOP,length, snoop)
+#define BT_SNOOP_UP_TRACE(entity_id, length, snoop)  \
+    DBG_SNOOP2(entity_id, 0, SUBTYPE_UP_SNOOP,length, snoop)
+
+
+/* Bluetooth Message Trace Interfaces */
+#define BT_MESSAGE_DOWN_PRINT_ERROR(length, message)   \
+    DBG_STREAM( SUBTYPE_DOWN_MESSAGE, MODULE_BTH, LEVEL_ERROR, length, message)
+#define BT_MESSAGE_DOWN_PRINT_WARN(length, message)   \
+    DBG_STREAM( SUBTYPE_DOWN_MESSAGE, MODULE_BTH, LEVEL_WARN, length, message)
+#define BT_MESSAGE_DOWN_PRINT_INFO(length, message)   \
+    DBG_STREAM( SUBTYPE_DOWN_MESSAGE, MODULE_BTH, LEVEL_INFO, length, message)
+#define BT_MESSAGE_DOWN_PRINT_TRACE(length, message)   \
+    DBG_STREAM( SUBTYPE_DOWN_MESSAGE, MODULE_BTH, LEVEL_TRACE, length, message)
+#define BT_MESSAGE_UP_PRINT_ERROR(length, message)   \
+    DBG_STREAM( SUBTYPE_UP_MESSAGE, MODULE_BTH, LEVEL_ERROR,  length, message)
+#define BT_MESSAGE_UP_PRINT_WARN(length, message)   \
+    DBG_STREAM( SUBTYPE_UP_MESSAGE, MODULE_BTH, LEVEL_WARN, length, message)
+#define BT_MESSAGE_UP_PRINT_INFO(length, message)   \
+    DBG_STREAM( SUBTYPE_UP_MESSAGE, MODULE_BTH, LEVEL_INFO, length, message)
+#define BT_MESSAGE_UP_PRINT_TRACE(length, message)   \
+    DBG_STREAM( SUBTYPE_UP_MESSAGE, MODULE_BTH, LEVEL_TRACE, length, message)
+
+/*  PATCH Trace Interfaces */
+#define PATCH_PRINT_ERROR(...)   \
+    DBG_INDEX( SUBTYPE_INDEX, MODULE_PATCH, LEVEL_ERROR, __VA_ARGS__)
+#define PATCH_PRINT_WARN(...)   \
+    DBG_INDEX( SUBTYPE_INDEX, MODULE_PATCH, LEVEL_WARN, __VA_ARGS__)
+#define PATCH_PRINT_INFO(...)   \
+    DBG_INDEX( SUBTYPE_INDEX, MODULE_PATCH, LEVEL_INFO, __VA_ARGS__)
+#define PATCH_PRINT_TRACE(...)   \
+    DBG_INDEX( SUBTYPE_INDEX, MODULE_PATCH, LEVEL_TRACE, __VA_ARGS__)
+
+/* Bluetooth Lower Stack Trace Interfaces */
+#define LOWERSTACK_PRINT_ERROR(...)   \
+    LOG_ERROR( MODULE_BTC, ##__VA_ARGS__)
+#define LOWERSTACK_PRINT_WARN( ...)   \
+    LOG_WARN( MODULE_BTC,   ##__VA_ARGS__)
+#define LOWERSTACK_PRINT_INFO( ...)   \
+    LOG_INFO( MODULE_BTC,   ##__VA_ARGS__)
+#define LOWERSTACK_PRINT_TRACE( ...)   \
+    LOG_TRACE( MODULE_BTC,   ##__VA_ARGS__)
+
+/* Bluetooth PROTOCOL Trace Interfaces */
+#define PROTOCOL_PRINT_ERROR(...)   \
+    LOG_ERROR( MODULE_PROTOCOL,   ##__VA_ARGS__)
+#define PROTOCOL_PRINT_WARN( ...)   \
+    LOG_WARN( MODULE_PROTOCOL,   ##__VA_ARGS__)
+#define PROTOCOL_PRINT_INFO( ...)   \
+    LOG_INFO( MODULE_PROTOCOL,   ##__VA_ARGS__)
+#define PROTOCOL_PRINT_TRACE( ...)   \
+    LOG_TRACE( MODULE_PROTOCOL,   ##__VA_ARGS__)
+
+/* Bluetooth PROFILE Trace Interfaces */
+#define PROFILE_PRINT_ERROR(...)   \
+    LOG_ERROR( MODULE_PROFILE,   ##__VA_ARGS__)
+#define PROFILE_PRINT_WARN( ...)   \
+    LOG_WARN( MODULE_PROFILE,   ##__VA_ARGS__)
+#define PROFILE_PRINT_INFO( ...)   \
+    LOG_INFO( MODULE_PROFILE,   ##__VA_ARGS__)
+#define PROFILE_PRINT_TRACE( ...)   \
+    LOG_TRACE( MODULE_PROFILE,   ##__VA_ARGS__)
+
+/*  BOOT Trace Interfaces */
+#define BOOT_PRINT_ERROR(...)   \
+    LOG_ERROR( MODULE_BOOT,   ##__VA_ARGS__)
+#define BOOT_PRINT_WARN( ...)   \
+    LOG_WARN( MODULE_BOOT,   ##__VA_ARGS__)
+#define BOOT_PRINT_INFO( ...)   \
+    LOG_INFO( MODULE_BOOT,   ##__VA_ARGS__)
+#define BOOT_PRINT_TRACE( ...)   \
+    LOG_TRACE( MODULE_BOOT,   ##__VA_ARGS__)
+
+/* OS Trace Interfaces */
+#define OS_PRINT_ERROR(...)   \
+    LOG_ERROR( MODULE_OS,   ##__VA_ARGS__)
+#define OS_PRINT_WARN( ...)   \
+    LOG_WARN( MODULE_OS,   ##__VA_ARGS__)
+#define OS_PRINT_INFO( ...)   \
+    LOG_INFO( MODULE_OS,   ##__VA_ARGS__)
+#define OS_PRINT_TRACE( ...)   \
+    LOG_TRACE( MODULE_OS,   ##__VA_ARGS__)
+
+/* OSIF Trace Interfaces */
+#define OSIF_PRINT_ERROR(...)   \
+    LOG_ERROR( MODULE_OSIF,   ##__VA_ARGS__)
+#define OSIF_PRINT_WARN( ...)   \
+    LOG_WARN( MODULE_OSIF,   ##__VA_ARGS__)
+#define OSIF_PRINT_INFO( ...)   \
+    LOG_INFO( MODULE_OSIF,   ##__VA_ARGS__)
+#define OSIF_PRINT_TRACE( ...)   \
+    LOG_TRACE( MODULE_OSIF,   ##__VA_ARGS__)
+
+/*  FLASH Trace Interfaces */
+#define FLASH_PRINT_ERROR(...)   \
+    LOG_ERROR( MODULE_FMC,   ##__VA_ARGS__)
+#define FLASH_PRINT_WARN(...)   \
+    LOG_WARN( MODULE_FMC,   ##__VA_ARGS__)
+#define FLASH_PRINT_INFO(...)   \
+    LOG_INFO( MODULE_FMC,   ##__VA_ARGS__)
+#define FLASH_PRINT_TRACE(...)   \
+    LOG_TRACE( MODULE_FMC,   ##__VA_ARGS__)
+
+/*  CRYPTO Trace Interfaces */
+#define CRYPTO_PRINT_ERROR(...)   \
+    LOG_ERROR( MODULE_CRYPTO,   ##__VA_ARGS__)
+#define CRYPTO_PRINT_WARN( ...)   \
+    LOG_WARN( MODULE_CRYPTO,   ##__VA_ARGS__)
+#define CRYPTO_PRINT_INFO( ...)   \
+    LOG_INFO( MODULE_CRYPTO,   ##__VA_ARGS__)
+#define CRYPTO_PRINT_TRACE( ...)   \
+    LOG_TRACE( MODULE_CRYPTO,   ##__VA_ARGS__)
+
+/*  DFU Trace Interfaces */
+#define DFU_PRINT_ERROR(...)   \
+    LOG_ERROR(MODULE_DFU,   ##__VA_ARGS__)
+#define DFU_PRINT_WARN(...)   \
+    LOG_WARN( MODULE_DFU,   ##__VA_ARGS__)
+#define DFU_PRINT_INFO(...)   \
+    LOG_INFO( MODULE_DFU,   ##__VA_ARGS__)
+#define DFU_PRINT_TRACE(...)   \
+    LOG_TRACE( MODULE_DFU,   ##__VA_ARGS__)
+
+/*  CLOCK Trace Interfaces */
+#define CLOCK_PRINT_ERROR(...)   \
+    LOG_ERROR(MODULE_CLOCK,   ##__VA_ARGS__)
+#define CLOCK_PRINT_WARN(...)   \
+    LOG_WARN( MODULE_CLOCK,   ##__VA_ARGS__)
+#define CLOCK_PRINT_INFO(...)   \
+    LOG_INFO( MODULE_CLOCK,   ##__VA_ARGS__)
+#define CLOCK_PRINT_TRACE(...)   \
+    LOG_TRACE( MODULE_CLOCK,   ##__VA_ARGS__)
+
+/*  IO Trace Interfaces */
+#define IO_PRINT_ERROR(...)   \
+    LOG_ERROR( MODULE_IO,   ##__VA_ARGS__)
+#define IO_PRINT_WARN( ...)   \
+    LOG_WARN( MODULE_IO,   ##__VA_ARGS__)
+#define IO_PRINT_INFO( ...)   \
+    LOG_INFO( MODULE_IO,   ##__VA_ARGS__)
+#define IO_PRINT_TRACE( ...)   \
+    LOG_TRACE( MODULE_IO,   ##__VA_ARGS__)
+
+/*  PM Trace Interfaces */
+#define PM_PRINT_ERROR(...)   \
+    LOG_ERROR( MODULE_PM,   ##__VA_ARGS__)
+#define PM_PRINT_WARN( ...)   \
+    LOG_WARN( MODULE_PM,   ##__VA_ARGS__)
+#define PM_PRINT_INFO( ...)   \
+    LOG_INFO( MODULE_PM,   ##__VA_ARGS__)
+#define PM_PRINT_TRACE( ...)   \
+    LOG_TRACE( MODULE_PM,   ##__VA_ARGS__)
+
+/*  PHY Trace Interfaces */
+#define PHY_PRINT_ERROR(...)   \
+    LOG_ERROR( MODULE_PHY,   ##__VA_ARGS__)
+#define PHY_PRINT_WARN( ...)   \
+    LOG_WARN( MODULE_PHY,   ##__VA_ARGS__)
+#define PHY_PRINT_INFO( ...)   \
+    LOG_INFO( MODULE_PHY,   ##__VA_ARGS__)
+#define PHY_PRINT_TRACE( ...)   \
+    LOG_TRACE( MODULE_PHY,   ##__VA_ARGS__)
+
+/*  DVFS Trace Interfaces */
+#define DVFS_PRINT_ERROR(...)   \
+    LOG_ERROR( MODULE_DVFS,   ##__VA_ARGS__)
+#define DVFS_PRINT_WARN( ...)   \
+    LOG_WARN( MODULE_DVFS,   ##__VA_ARGS__)
+#define DVFS_PRINT_INFO( ...)   \
+    LOG_INFO( MODULE_DVFS,   ##__VA_ARGS__)
+#define DVFS_PRINT_TRACE( ...)   \
+    LOG_TRACE( MODULE_DVFS,   ##__VA_ARGS__)
+
+/*  CHARGER Trace Interfaces */
+#define CHARGER_PRINT_ERROR(...)   \
+    LOG_ERROR( MODULE_CHARGER,   ##__VA_ARGS__)
+#define CHARGER_PRINT_WARN( ...)   \
+    LOG_WARN( MODULE_CHARGER,   ##__VA_ARGS__)
+#define CHARGER_PRINT_INFO( ...)   \
+    LOG_INFO( MODULE_CHARGER,   ##__VA_ARGS__)
+#define CHARGER_PRINT_TRACE( ...)   \
+    LOG_TRACE( MODULE_CHARGER,   ##__VA_ARGS__)
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _SOC_LOG_H_ */
diff --git a/bee/memory/CMakeLists.txt b/bee/memory/CMakeLists.txt
new file mode 100644
index 00000000..55b24f13
--- /dev/null
+++ b/bee/memory/CMakeLists.txt
@@ -0,0 +1,6 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_include_directories_ifdef(CONFIG_SOC_SERIES_RTL87X2G inc/rtl87x2g)
+zephyr_include_directories_ifdef(CONFIG_SOC_SERIES_RTL87X2J inc/rtl87x2j)
+zephyr_include_directories_ifdef(CONFIG_SOC_SERIES_RTL8752H inc/rtl8752h)
diff --git a/bee/memory/inc/rtl8752h/mem_types.h b/bee/memory/inc/rtl8752h/mem_types.h
new file mode 100644
index 00000000..e0df209a
--- /dev/null
+++ b/bee/memory/inc/rtl8752h/mem_types.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *               Define to prevent recursive inclusion
+ *============================================================================*/
+#ifndef _MEM_TYPES_H_
+#define _MEM_TYPES_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/** @defgroup MEM_CONFIG Memory Configure
+  * @{
+  */
+
+/*============================================================================*
+ *                               Types
+*============================================================================*/
+/** @defgroup MEM_CONFIG_Exported_Types Memory Configure Exported Types
+  * @{
+  */
+
+typedef enum
+{
+    RAM_TYPE_DATA_ON = 0,
+    RAM_TYPE_DATA_OFF = RAM_TYPE_DATA_ON,
+    RAM_TYPE_BUFFER_ON = 1,
+    RAM_TYPE_BUFFER_OFF = RAM_TYPE_BUFFER_ON,
+    RAM_TYPE_NUM = 2,
+} RAM_TYPE;
+
+/** @} */ /* End of group MEM_TYPES_Exported_Types */
+
+/** @} */ /* End of group MEM_CONFIG */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _MEM_TYPES_H_ */
diff --git a/bee/memory/inc/rtl87x2g/mem_types.h b/bee/memory/inc/rtl87x2g/mem_types.h
new file mode 100644
index 00000000..f2627137
--- /dev/null
+++ b/bee/memory/inc/rtl87x2g/mem_types.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *               Define to prevent recursive inclusion
+ *============================================================================*/
+#ifndef _MEM_TYPES_H_
+#define _MEM_TYPES_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/** @defgroup MEM_CONFIG Memory Configure
+  * @{
+  */
+
+/*============================================================================*
+ *                               Types
+*============================================================================*/
+/** @defgroup MEM_CONFIG_Exported_Types Memory Configure Exported Types
+  * @{
+  */
+
+typedef enum
+{
+    RAM_TYPE_DATA_ON,        //DTCM Heap
+    RAM_TYPE_DATA_OFF = RAM_TYPE_DATA_ON,
+    RAM_TYPE_BUFFER_ON,
+    RAM_TYPE_BUFFER_OFF = RAM_TYPE_BUFFER_ON,
+    RAM_TYPE_EXT_DATA_SRAM,  //Ext DATA SRAM heap
+    RAM_TYPE_NUM
+} RAM_TYPE;
+
+/** End of MEM_TYPES_Exported_Types
+  * @}
+  */
+
+/** End of MEM_CONFIG
+  * @}
+  */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _MEM_TYPES_H_ */
diff --git a/bee/memory/inc/rtl87x2j/mem_cfg_int.h b/bee/memory/inc/rtl87x2j/mem_cfg_int.h
new file mode 100644
index 00000000..5bcb74ea
--- /dev/null
+++ b/bee/memory/inc/rtl87x2j/mem_cfg_int.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+  *                   Define to prevent recursive inclusion
+  *============================================================================*/
+#ifndef _MEM_CFG_INT_H
+#define _MEM_CFG_INT_H
+#include "mem_config.h"
+//#include "address_map.h"
+
+/*============================================================================*
+  *                               Memory Address Map
+  * refence wiki:
+  *============================================================================*/
+
+
+/*============================================================================*
+  *                                   ROM layout
+  *============================================================================*/
+/* ROM:          Bee5 size: 16K
+example:
+   1) rom code:    16K
+*/
+#define ROM_ADDR                     0x0
+#define ROM_SIZE                     0x00004000 // 16K
+
+
+/*============================================================================*
+  *                                   Other internal defines
+  *============================================================================*/
+#define MAIN_STACK_START_ADDR       DATA_RAM_MAIN_STACK_START_ADDR
+#define MAIN_STACK_SIZE             DATA_RAM_MAIN_STACK_SIZE
+
+#endif  //_MEM_CFG_INT_H
diff --git a/bee/memory/inc/rtl87x2j/mem_config.h b/bee/memory/inc/rtl87x2j/mem_config.h
new file mode 100644
index 00000000..ae138f27
--- /dev/null
+++ b/bee/memory/inc/rtl87x2j/mem_config.h
@@ -0,0 +1,154 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *               Define to prevent recursive inclusion
+ *============================================================================*/
+#ifndef __MEM_CONFIG__
+#define __MEM_CONFIG__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//#include "address_map.h"
+
+
+/** @defgroup MEM_CONFIG Memory Configure
+  * @brief Memory configuration for user application
+  * @{
+  */
+/** @defgroup MEM_CONFIG_Exported_Constant Mem Config Exported Constants
+  * @{
+  */
+
+// Build Bank Configure
+#define BUILD_BANK              0   //Bank0 as default
+
+//Enable RAM Code
+#define FEATURE_RAM_CODE        0
+
+/** @brief encrypt app or not */
+#define FEATURE_ENCRYPTION      0
+
+//Use Cache RAM to run RAM Code
+#define FEATURE_CACHE_RAM_CODE  0
+
+/*============================================================================*
+  *                            Memory layout
+  *============================================================================*/
+#define EFLASH_ADDR            0x02000000
+#define EFLASH_SIZE            (720*1024)
+
+#define EFLASH_NVR_ADDR        0x02200000
+#define EFLASH_NVR_SIZE        (34*1024)
+
+#define EFLASH_NVR_CFG_AREA_ADDR    0x04B00000
+#define EFLASH_NVR_CFG_AREA_SIZE    (2*1024)
+
+#define CODE_RAM_ADDR         0x00200000
+#define CODE_RAM_SIZE         (0*1024)
+
+#define DATA_RAM_ADDR         0x20000000
+#define DATA_RAM_SIZE         (104*1024)
+
+#define BUFFER_RAM_ADDR       0x20100000
+#define BUFFER_RAM_SIZE       (24*1024)
+
+/*============================================================================*
+  *                            Eflash NVR layout
+  *============================================================================*/
+/* Fflash NVR:                  Bee5 size: 34K
+example:
+       1) OTP:                   1K
+       3) OEM Header:            3K
+       4) FTL                    16K
+       5) User Data              14K
+*/
+
+#define OTP_TABLE_SIZE           (1*1024)
+#define OEM_HEADER_SIZE          (3*1024)
+#define FTL_SIZE                 (16*1024)
+
+#define OTP_TABLE_ADDR           (EFLASH_NVR_ADDR)
+#define OEM_HEADER_ADDR          OTP_TABLE_ADDR + OTP_TABLE_SIZE
+#define FTL_ADDR                 OEM_HEADER_ADDR + OEM_HEADER_SIZE
+#define USER_DATA_ADDR           FTL_ADDR + FTL_SIZE
+#define USER_DATA_SIZE           EFLASH_NVR_ADDR + EFLASH_NVR_SIZE - USER_DATA_ADDR
+
+
+/*============================================================================*
+  *                                Data RAM layout
+  *============================================================================*/
+/* Data RAM:                  Bee5 size: 104K
+example:
+       1) boot patch:            5K
+       2) sys patch:             4K
+       3) bt controller:        12K
+       4) bt host:               3K
+       5) APP global:           24K
+       6) heap:                 48K
+       7) non_retention:       5.5K
+       8) rom:                   1K + 64
+       9) main stack:          1.5K - 64
+
+*/
+#define DATA_RAM_ROM_GLOBAL_SIZE          (1*1024 + 64)
+#define DATA_RAM_MAIN_STACK_SIZE          (1*1024+512-64)
+#define DATA_RAM_BOOT_PATCH_SIZE          (5*1024)
+#define DATA_RAM_SYS_PATCH_SIZE           (4*1024)
+#define DATA_RAM_BT_CONTROLLER_SIZE       (12*1024)
+#define DATA_RAM_BT_HOST_SIZE             (3*1024)
+#define DATA_RAM_APP_SIZE                 (24*1024)
+#define DATA_NON_RETENTION_SIZE           (5*1024+512)
+//#define DATA_HEAP_SIZE                    (48*1024)
+
+/** @brief shared cache ram size (adjustable, config SHARE_CACHE_RAM_SIZE: 0/4KB/8KB) */
+#define SHARE_CACHE_RAM_SIZE           (0 * 1024)
+
+
+/* -----------------The following macros should not be modified!------------------------- */
+#define DATA_RAM_BOOT_PATCH_ADDR           (DATA_RAM_ADDR)
+#define DATA_RAM_SYS_PATCH_ADDR            (DATA_RAM_BOOT_PATCH_ADDR + DATA_RAM_BOOT_PATCH_SIZE)
+#define DATA_RAM_BT_CONTROLLER_ADDR        (DATA_RAM_SYS_PATCH_ADDR + DATA_RAM_SYS_PATCH_SIZE)
+#define DATA_RAM_BT_HOST_ADDR              (DATA_RAM_BT_CONTROLLER_ADDR + DATA_RAM_BT_CONTROLLER_SIZE)
+#define DATA_RAM_APP_ADDR                  (DATA_RAM_BT_HOST_ADDR + DATA_RAM_BT_HOST_SIZE)
+#define DATA_HEAP_ADDR                     (DATA_RAM_APP_ADDR + DATA_RAM_APP_SIZE)
+#define DATA_HEAP_SIZE                     (DATA_NON_RETENTION_ADDR - DATA_HEAP_ADDR)
+#define DATA_NON_RETENTION_ADDR            (DATA_RAM_ADDR + DATA_RAM_SIZE - DATA_NON_RETENTION_SIZE - DATA_RAM_MAIN_STACK_SIZE - DATA_RAM_ROM_GLOBAL_SIZE)
+#define DATA_RAM_ROM_GLOBAL_ADDR           (DATA_NON_RETENTION_ADDR + DATA_NON_RETENTION_SIZE)
+#define DATA_RAM_MAIN_STACK_START_ADDR     (DATA_RAM_ROM_GLOBAL_ADDR + DATA_RAM_ROM_GLOBAL_SIZE)
+
+//alias
+#define MAIN_STACK_START_ADDR              DATA_RAM_MAIN_STACK_START_ADDR
+#define MAIN_STACK_SIZE                    DATA_RAM_MAIN_STACK_SIZE
+
+/*============================================================================*
+  *                                 Buffer RAM layout
+  *============================================================================*/
+/* Buffer RAM:                 Bee5 size: 24K
+example:
+   1) global:        2K
+   1) heap:          22K
+*/
+#define BUFFER_RAM_GLOBAL_SIZE             (2*1024)
+/* -----------------The following macros should not be modified!------------------------- */
+#define BUFFER_RAM_GLOBAL_ADDR             (BUFFER_RAM_ADDR)
+#define BUFFER_HEAP_ADDR                   (BUFFER_RAM_GLOBAL_ADDR + BUFFER_RAM_GLOBAL_SIZE)
+#define BUFFER_HEAP_SIZE                   (BUFFER_RAM_SIZE - BUFFER_RAM_GLOBAL_SIZE)
+
+/** @} */ /* End of group MEM_CONFIG_Exported_Constents */
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+/** @} */ /* End of group MEM_CONFIG */
+
+#endif
diff --git a/bee/memory/inc/rtl87x2j/mem_types.h b/bee/memory/inc/rtl87x2j/mem_types.h
new file mode 100644
index 00000000..d477083b
--- /dev/null
+++ b/bee/memory/inc/rtl87x2j/mem_types.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *               Define to prevent recursive inclusion
+ *============================================================================*/
+#ifndef _MEM_TYPES_H_
+#define _MEM_TYPES_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/** @defgroup MEM_CONFIG Memory Configure
+  * @{
+  */
+
+/*============================================================================*
+ *                               Types
+*============================================================================*/
+/** @defgroup MEM_CONFIG_Exported_Types Memory Configure Exported Types
+  * @{
+  */
+
+typedef enum
+{
+    RAM_TYPE_DATA_ON,
+    RAM_TYPE_DATA_OFF = RAM_TYPE_DATA_ON,
+    RAM_TYPE_BUFFER_ON,
+    RAM_TYPE_BUFFER_OFF = RAM_TYPE_BUFFER_ON,
+    RAM_TYPE_NUM,
+} RAM_TYPE;
+
+/** @} */ /* End of group MEM_TYPES_Exported_Types */
+
+/** @} */ /* End of group MEM_CONFIG */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _MEM_TYPES_H_ */
diff --git a/bee/os/osif/inc/rtl8752h/os_mem.h b/bee/os/osif/inc/rtl8752h/os_mem.h
new file mode 100644
index 00000000..be8711d5
--- /dev/null
+++ b/bee/os/osif/inc/rtl8752h/os_mem.h
@@ -0,0 +1,283 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _OS_MEM_H_
+#define _OS_MEM_H_
+
+#include <stdint.h>
+#include <stddef.h>
+#include <mem_types.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup  OS      OSIF APIs
+ * \defgroup    Memory  Memory Management
+ *
+ * \brief   Allocate, free, and peek memory functions.
+ * \details The Memory Management function group allows to allocate, free, and peek heap
+ *          memory in the system.\n
+ *
+ * \ingroup     OS
+ */
+
+
+void *os_mem_alloc_intern(RAM_TYPE ram_type, size_t size,
+                          const char *p_func, uint32_t file_line);
+
+void *os_mem_zalloc_intern(RAM_TYPE ram_type, size_t size,
+                           const char *p_func, uint32_t file_line);
+
+void *os_mem_aligned_alloc_intern(RAM_TYPE ram_type, size_t size, uint8_t alignment,
+                                  const char *p_func, uint32_t file_line);
+
+/**
+ * os_mem.h
+ *
+ * \brief    Allocate a memory block with required size.
+ *
+ * \param[in]   ram_type            RAM type for allocation.
+ * \arg \c      RAM_TYPE_DATA_ON    Data ON RAM type.
+ * \arg \c      RAM_TYPE_BUFFER_ON  BUFFER ON RAM type.
+ *
+ * \param[in]   size     Required memory size.
+ *
+ * \return     The address of the allocated memory block. If the address is NULL, the
+ *             memory allocation failed.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * int test(void)
+ * {
+ *     size_t mem_size = 0x1000;
+ *     void *p_mem = NULL;
+ *
+ *     p_mem = os_mem_alloc(RAM_TYPE_DATA_ON, mem_size);
+ *     if (p_mem != NULL)
+ *     {
+ *         // Memory allocation successed, and free it.
+ *         os_mem_free(p_mem);
+ *     }
+ *     else
+ *     {
+ *         // Memory allocation failed.
+ *         return -1;
+ *     }
+ *
+ *     return 0;
+ * }
+ * \endcode
+ *
+ * \ingroup  Memory
+ */
+#define os_mem_alloc(ram_type, size)    \
+    os_mem_alloc_intern(ram_type, size, __func__, __LINE__)
+
+/**
+ * os_mem.h
+ *
+ * \brief    Allocate and clear a memory block with required size.
+ *
+ * \param[in]   ram_type            RAM type for allocation.
+ * \arg \c      RAM_TYPE_DATA_ON    Data ON RAM type.
+ * \arg \c      RAM_TYPE_BUFFER_ON  BUFFER ON RAM type.
+ *
+ * \param[in]   size     Required memory size.
+ *
+ * \return     The address of the allocated memory block. If the address is NULL, the
+ *             memory allocation failed.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * int test(void)
+ * {
+ *     size_t mem_size = 0x1000;
+ *     void *p_mem = NULL;
+ *
+ *     p_mem = os_mem_zalloc(RAM_TYPE_DATA_ON, mem_size);
+ *     if (p_mem != NULL)
+ *     {
+ *         // Memory allocation successed, and free it.
+ *         os_mem_free(p_mem);
+ *     }
+ *     else
+ *     {
+ *         // Memory allocation failed.
+ *         return -1;
+ *     }
+ *
+ *     return 0;
+ * }
+ * \endcode
+ *
+ * \ingroup  Memory
+ */
+#define os_mem_zalloc(ram_type, size)   \
+    os_mem_zalloc_intern(ram_type, size, __func__, __LINE__)
+
+/**
+ * os_mem.h
+ *
+ * \brief    Allocate an aligned memory block with required size.
+ *
+ * \param[in]   ram_type            RAM type for allocation.
+ * \arg \c      RAM_TYPE_DATA_ON    Data ON RAM type.
+ * \arg \c      RAM_TYPE_BUFFER_ON  BUFFER ON RAM type.
+ *
+ * \param[in]   size        Required memory size.
+ *
+ * \param[in]   alignment   memory alignment in 2^N bytes. If alignment is 0, use
+ *                          system default memory alignment. The aligned memory block
+ *                          must use os_mem_aligned_free() API function to free.
+ *
+ * \return     The address of the allocated memory block. If the address is NULL, the
+ *             memory allocation failed.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * int test(void)
+ * {
+ *     size_t mem_size = 0x1000;
+ *     uint8_t mem_alignment = 16;
+ *     void *p_mem = NULL;
+ *
+ *     p_mem = os_mem_aligned_alloc(RAM_TYPE_DATA_ON, mem_size, mem_alignment);
+ *     if (p_mem != NULL)
+ *     {
+ *         // Aligned memory allocation successed, and free it.
+ *         os_mem_aligned_free(p_mem);
+ *     }
+ *     else
+ *     {
+ *         // Aligned memory allocation failed.
+ *         return -1;
+ *     }
+ *
+ *     return 0;
+ * }
+ * \endcode
+ *
+ * \ingroup  Memory
+ */
+#define os_mem_aligned_alloc(ram_type, size, alignment) \
+    os_mem_aligned_alloc_intern(ram_type, size, alignment, __func__, __LINE__)
+
+/**
+ * os_mem.h
+ *
+ * \brief    Free a memory block that had been allocated.
+ *
+ * \param[in]   p_block     The address of memory block being freed.
+ *
+ * \return     None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * int test(void)
+ * {
+ *     size_t mem_size = 0x1000;
+ *     void *p_mem = NULL;
+ *
+ *     p_mem = os_mem_alloc(RAM_TYPE_DATA_ON, mem_size);
+ *     if (p_mem != NULL)
+ *     {
+ *         // Memory allocation successed, and free it.
+ *         os_mem_free(p_mem);
+ *     }
+ *     else
+ *     {
+ *         // Memory allocation failed.
+ *         return -1;
+ *     }
+ *
+ *     return 0;
+ * }
+ * \endcode
+ *
+ * \ingroup  Memory
+ */
+void os_mem_free(void *p_block);
+
+/**
+ * os_mem.h
+ *
+ * \brief    Free an aligned memory block that had been allocated.
+ *
+ * \param[in]   p_block     The address of memory block being freed.
+ *
+ * \return     None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * int test(void)
+ * {
+ *     size_t mem_size = 0x1000;
+ *     uint8_t mem_alignment = 16;
+ *     void *p_mem = NULL;
+ *
+ *     p_mem = os_mem_aligned_alloc(RAM_TYPE_DATA_ON, mem_size, mem_alignment);
+ *     if (p_mem != NULL)
+ *     {
+ *         // Aligned memory allocation successed, and free it.
+ *         os_mem_aligned_free(p_mem);
+ *     }
+ *     else
+ *     {
+ *         // Aligned memory allocation failed.
+ *         return -1;
+ *     }
+ *
+ *     return 0;
+ * }
+ * \endcode
+ *
+ * \ingroup  Memory
+ */
+void os_mem_aligned_free(void *p_block);
+
+/**
+ * os_mem.h
+ *
+ * \brief    Peek the unused memory size of the specified RAM type.
+ *
+ * \param[in]   ram_type            RAM type for allocation.
+ * \arg \c      RAM_TYPE_DATA_ON    Data ON RAM type.
+ * \arg \c      RAM_TYPE_BUFFER_ON  BUFFER ON RAM type.
+ *
+ * \return     The unused memory size in btyes.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * int test(void)
+ * {
+ *     size_t unused_data_on;
+ *     size_t unused_data_off;
+ *
+ *     // Peek unused DATA ON memory size.
+ *     unused_size = os_mem_peek(RAM_TYPE_DATA_ON);
+ *
+ *     // Peek unused buffer on memory size.
+ *     unused_size = os_mem_peek(RAM_TYPE_BUFFER_ON);
+ *
+ *     return 0;
+ * }
+ * \endcode
+ *
+ * \ingroup  Memory
+ */
+size_t os_mem_peek(RAM_TYPE ram_type);
+
+/* internal functions */
+void os_mem_check_heap_usage(void);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _OS_MEM_H_ */
diff --git a/bee/os/osif/inc/rtl8752h/os_msg.h b/bee/os/osif/inc/rtl8752h/os_msg.h
new file mode 100644
index 00000000..d8752b78
--- /dev/null
+++ b/bee/os/osif/inc/rtl8752h/os_msg.h
@@ -0,0 +1,434 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _OS_MSG_H_
+#define _OS_MSG_H_
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup  OS      OSIF APIs
+ * \defgroup    Message Message Queue
+ *
+ * \brief   Exchange messages between tasks in a FIFO-like operation.
+ * \details The Message Queue function group allows to control, send, receive, or wait for message.
+ *          Message transmission is a basic communication model between tasks that one task sends
+ *          data explicitly, while another task receives it. The operation is more like some
+ *          kind of I/O rather than a direct access to information to be shared. The data to be
+ *          passed can be any type.\n
+ *
+ * \image html OS-message-queue-overview.jpg "Message Queue Overview" width=617px height=321px
+ *
+ * \ingroup     OS
+ */
+
+
+bool os_msg_queue_create_intern(void **pp_handle, uint32_t msg_num, uint32_t msg_size,
+                                const char *p_func, uint32_t file_line);
+
+bool os_msg_queue_delete_intern(void *p_handle, const char *p_func, uint32_t file_line);
+
+bool os_msg_queue_peek_intern(void *p_handle, uint32_t *p_msg_num,
+                              const char *p_func, uint32_t file_line);
+
+bool os_msg_send_intern(void *p_handle, void *p_msg, uint32_t wait_ms,
+                        const char *p_func, uint32_t file_line);
+
+bool os_msg_recv_intern(void *p_handle, void *p_msg, uint32_t wait_ms,
+                        const char *p_func, uint32_t file_line);
+
+bool os_msg_peek_intern(void *p_handle, void *p_msg, uint32_t wait_ms,
+                        const char *p_func, uint32_t file_line);
+
+/**
+ * os_msg.h
+ *
+ * \brief   Creates a message queue instance. This allocates the storage required by the
+ *          new queue and passes back a handle for the queue.
+ *
+ * \param[out]  pp_handle  Used to pass back a handle by which the message queue
+ *                         can be referenced.
+ *
+ * \param[in]   msg_num    The maximum number of items that the queue can contain.
+ *
+ * \param[in]   msg_size   The number of bytes each item in the queue will require. Items
+ *                         are queued by copy, not by reference, so this is the number of
+ *                         bytes that will be copied for each posted item. Each item on the
+ *                         queue must be the same size.
+ *
+ * \return           The status of the message queue creation.
+ * \retval true      Message queue was created successfully.
+ * \retval false     Message queue was failed to create.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * struct test_msg
+ * {
+ *     uint8_t id;
+ *     uint8_t data[16];
+ * }
+ *
+ * #define MSG_NUM  10
+ *
+ * int test(void)
+ * {
+ *     void *p_handle = NULL;
+ *
+ *     // Create a queue capable of containing 10 items of structure test_msg.
+ *     if (os_msg_queue_create(&p_handle, MSG_NUM, sizeof(struct test_msg)) == true)
+ *     {
+ *         // Message queue created successfully.
+ *     }
+ *     else
+ *     {
+ *         // Message queue failed to create.
+ *         return -1;
+ *     }
+ *
+ *     // Delete the message queue.
+ *     os_msg_queue_delete(p_handle);
+ *
+ *     return 0;
+ * }
+ * \endcode
+ *
+ * \ingroup  Message
+ */
+#define os_msg_queue_create(pp_handle, msg_num, msg_size)    \
+    os_msg_queue_create_intern(pp_handle, msg_num, msg_size, __func__, __LINE__)
+
+/**
+ * os_msg.h
+ *
+ * \brief   Delete the specified message queue, and free all the memory allocated for
+ *          storing of items placed on the queue.
+ *
+ * \param[in]   p_handle   The handle to the message queue being deleted.
+ *
+ * \return           The status of the message queue deletion.
+ * \retval true      Message queue was deleted successfully.
+ * \retval false     Message queue was failed to delete.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * struct test_msg
+ * {
+ *     uint8_t id;
+ *     uint8_t data[16];
+ * }
+ *
+ * #define MSG_NUM  10
+ *
+ * int test(void)
+ * {
+ *     void *p_handle = NULL;
+ *
+ *     // Create a queue capable of containing 10 items of structure test_msg.
+ *     if (os_msg_queue_create(&p_handle, MSG_NUM, sizeof(struct test_msg)) == true)
+ *     {
+ *         // Message queue created successfully.
+ *     }
+ *     else
+ *     {
+ *         // Message queue failed to create.
+ *         return -1;
+ *     }
+ *
+ *     // Delete the message queue.
+ *     os_msg_queue_delete(p_handle);
+ *
+ *     return 0;
+ * }
+ * \endcode
+ *
+ * \ingroup  Message
+ */
+#define os_msg_queue_delete(p_handle) \
+    os_msg_queue_delete_intern(p_handle, __func__, __LINE__)
+
+/**
+ * os_msg.h
+ *
+ * \brief    Peek the number of items sent and resided on the message queue.
+ *
+ * \param[in]   p_handle   The handle to the message queue being peeked.
+ *
+ * \param[out]  p_msg_num  Used to pass back the number of items residing on the message queue.
+ *
+ * \return           The status of the message queue peek.
+ * \retval true      Message queue was peeked successfully.
+ * \retval false     Message queue was failed to peek.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * struct test_msg
+ * {
+ *     uint8_t id;
+ *     uint8_t data[16];
+ * }
+ *
+ * #define MSG_NUM  10
+ *
+ * int test(void)
+ * {
+ *     void *p_handle = NULL;
+ *     uint32_t msg_num;
+ *
+ *     // Create a queue capable of containing 10 items of structure test_msg.
+ *     if (os_msg_queue_create(&p_handle, MSG_NUM, sizeof(struct test_msg)) == true)
+ *     {
+ *         // Message queue created successfully.
+ *     }
+ *     else
+ *     {
+ *         // Message queue failed to create.
+ *         return -1;
+ *     }
+ *
+ *     // Peek the number of items sent on this message queue.
+ *     os_msg_queue_peek(p_handle, &msg_num);
+ *
+ *     return 0;
+ * }
+ * \endcode
+ *
+ * \ingroup  Message
+ */
+#define os_msg_queue_peek(p_handle, p_msg_num)  \
+    os_msg_queue_peek_intern(p_handle, p_msg_num, __func__, __LINE__)
+
+/**
+ * os_msg.h
+ *
+ * \brief   Send an item to the back of the specified message queue. The item is
+ *          queued by copy, not by reference.
+ *
+ * \param[in]   p_handle The handle to the message queue on which the item is to be sent.
+ *
+ * \param[in]   p_msg    Pointer to the item that is to be sent on the queue. The referenced
+ *                       item rather than pointer itself will be copied on the queue.
+ *
+ * \param[in]   wait_ms  The maximum amount of time in milliseconds that the task should
+ *                       block waiting for the item to sent on the queue.
+ * \arg \c 0           No blocking and return immediately.
+ * \arg \c 0xFFFFFFFF  Block infinitely until the item sent.
+ * \arg \c others      The timeout value in milliseconds.
+ *
+ * \return           The status of the message item sent.
+ * \retval true      Message item was sent successfully.
+ * \retval false     Message item was failed to send.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * struct test_msg
+ * {
+ *     uint8_t id;
+ *     uint8_t data[16];
+ * }
+ *
+ * #define MSG_NUM  10
+ *
+ * int test(void)
+ * {
+ *     void *p_handle = NULL;
+ *     struct test_msg msg;
+ *
+ *     // Create a queue capable of containing 10 items of structure test_msg.
+ *     if (os_msg_queue_create(&p_handle, MSG_NUM, sizeof(struct test_msg)) == true)
+ *     {
+ *         // Message queue created successfully.
+ *     }
+ *     else
+ *     {
+ *         // Message queue failed to create.
+ *         return -1;
+ *     }
+ *
+ *     // Send the item to this message queue.
+ *     msg.id = 1;
+ *     msg.data[0] = 0;
+ *     os_msg_send(p_handle, &msg, 0);
+ *
+ *     return 0;
+ * }
+ * \endcode
+ *
+ * \ingroup  Message
+ */
+#define os_msg_send(p_handle, p_msg, wait_ms) \
+    os_msg_send_intern(p_handle, p_msg, wait_ms, __func__, __LINE__)
+
+/**
+ * os_msg.h
+ *
+ * \brief   Receive an item from the specified message queue. The item is received by
+ *          copy rather than by reference, so a buffer of adequate size must be provided.
+ *
+ * \param[in]   p_handle The handle to the message queue from which the item is to be received.
+ *
+ * \param[out]  p_msg    Pointer to the buffer into which the received item will be copied.
+ *                       item rather than pointer itself will be copied on the queue.
+ *
+ * \param[in]   wait_ms  The maximum amount of time in milliseconds that the task should
+ *                       block waiting for an item to be received from the queue.
+ * \arg \c 0           No blocking and return immediately.
+ * \arg \c 0xFFFFFFFF  Block infinitely until the item received.
+ * \arg \c others      The timeout value in milliseconds.
+ *
+ * \return           The status of the message item received.
+ * \retval true      Message item was received successfully.
+ * \retval false     Message item was failed to receive.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * struct test_msg
+ * {
+ *     uint8_t id;
+ *     uint8_t data[16];
+ * }
+ *
+ * #define MSG_NUM  10
+ *
+ * void *p_handle = NULL;
+ *
+ * void send_msg(void)
+ * {
+ *     struct test_msg msg;
+ *
+ *     // Create a queue capable of containing 10 items of structure test_msg.
+ *     if (os_msg_queue_create(&p_handle, MSG_NUM, sizeof(struct test_msg)) == true)
+ *     {
+ *         // Message queue created successfully.
+ *     }
+ *     else
+ *     {
+ *         // Message queue failed to create.
+ *         return -1;
+ *     }
+ *
+ *     // Send the item to this message queue.
+ *     msg.id = 1;
+ *     msg.data[0] = 0;
+ *     os_msg_send(p_handle, &msg, 0);
+ *
+ *     return 0;
+ * }
+ *
+ * void receive_msg(void)
+ * {
+ *     struct test_msg msg;
+ *
+ *     // Receive the message queue item.
+ *     if (os_msg_recv(p_handle, &msg, 0) == true)
+ *     {
+ *         // Message item received successfully.
+ *     }
+ *     else
+ *     {
+ *         // Message item failed to receive.
+ *         return -1;
+ *     }
+ *
+ *     return 0;
+ * }
+ * \endcode
+ *
+ * \ingroup  Message
+ */
+#define os_msg_recv(p_handle, p_msg, wait_ms) \
+    os_msg_recv_intern(p_handle, p_msg, wait_ms, __func__, __LINE__)
+
+/**
+ * os_msg.h
+ *
+ * \brief   Receive but not remove an item from the specified message queue. The item is
+ *          received by copy rather than by reference, so a buffer of adequate size must
+ *          be provided.
+ *
+ * \param[in]   p_handle The handle to the message queue on which the item is to be peeked.
+ *
+ * \param[out]  p_msg    Pointer to the buffer into which the received item will be copied.
+ *                       item rather than pointer itself will be copied on the queue.
+ *
+ * \param[in]   wait_ms  The maximum amount of time in milliseconds that the task should
+ *                       block waiting for an item to be received from the queue.
+ * \arg \c 0           No blocking and return immediately.
+ * \arg \c 0xFFFFFFFF  Block infinitely until the item received.
+ * \arg \c others      The timeout value in milliseconds.
+ *
+ * \return           The status of the message item received.
+ * \retval true      Message item was received successfully.
+ * \retval false     Message item was failed to receive.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * struct test_msg
+ * {
+ *     uint8_t id;
+ *     uint8_t data[16];
+ * }
+ *
+ * #define MSG_NUM  10
+ *
+ * void *p_handle = NULL;
+ *
+ * void send_msg(void)
+ * {
+ *     struct test_msg msg;
+ *
+ *     // Create a queue capable of containing 10 items of structure test_msg.
+ *     if (os_msg_queue_create(&p_handle, MSG_NUM, sizeof(struct test_msg)) == true)
+ *     {
+ *         // Message queue created successfully.
+ *     }
+ *     else
+ *     {
+ *         // Message queue failed to create.
+ *         return -1;
+ *     }
+ *
+ *     // Send the item to this message queue.
+ *     msg.id = 1;
+ *     msg.data[0] = 0;
+ *     os_msg_send(p_handle, &msg, 0);
+ *
+ *     return 0;
+ * }
+ *
+ * void peek_msg(void)
+ * {
+ *     struct test_msg msg;
+ *
+ *     // Peek the message queue item.
+ *     if (os_msg_peek(p_handle, &msg, 0) == true)
+ *     {
+ *         // Message item peeked successfully.
+ *     }
+ *     else
+ *     {
+ *         // Message item failed to peek.
+ *         return -1;
+ *     }
+ *
+ *     return 0;
+ * }
+ * \endcode
+ *
+ * \ingroup  Message
+ */
+#define os_msg_peek(p_handle, p_msg, wait_ms) \
+    os_msg_peek_intern(p_handle, p_msg, wait_ms, __func__, __LINE__)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _OS_MSG_H_ */
diff --git a/bee/os/osif/inc/rtl8752h/os_patch.h b/bee/os/osif/inc/rtl8752h/os_patch.h
new file mode 100644
index 00000000..edd2cadc
--- /dev/null
+++ b/bee/os/osif/inc/rtl8752h/os_patch.h
@@ -0,0 +1,96 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _OS_PATCH_H_
+#define _OS_PATCH_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef bool (*BOOL_PATCH_FUNC)();
+
+/* OSIF patch function */
+extern BOOL_PATCH_FUNC patch_osif_os_systick_handler;
+extern BOOL_PATCH_FUNC patch_osif_os_delay;
+extern BOOL_PATCH_FUNC patch_osif_os_sys_time_get;
+extern BOOL_PATCH_FUNC patch_osif_os_sys_tick_get;
+extern BOOL_PATCH_FUNC patch_osif_os_sys_tick_increase;
+extern BOOL_PATCH_FUNC patch_osif_os_sched_start;
+extern BOOL_PATCH_FUNC patch_osif_os_sched_stop;
+extern BOOL_PATCH_FUNC patch_osif_os_sched_suspend;
+extern BOOL_PATCH_FUNC patch_osif_os_sched_resume;
+extern BOOL_PATCH_FUNC patch_osif_os_sched_is_start;
+extern BOOL_PATCH_FUNC patch_osif_os_sched_state_get;
+extern BOOL_PATCH_FUNC patch_osif_os_vector_table_update;
+extern BOOL_PATCH_FUNC patch_osif_os_init;
+
+extern BOOL_PATCH_FUNC patch_osif_os_task_create;
+extern BOOL_PATCH_FUNC patch_osif_os_task_delete;
+extern BOOL_PATCH_FUNC patch_osif_os_task_suspend;
+extern BOOL_PATCH_FUNC patch_osif_os_task_resume;
+extern BOOL_PATCH_FUNC patch_osif_os_task_yield;
+extern BOOL_PATCH_FUNC patch_osif_os_task_handle_get;
+extern BOOL_PATCH_FUNC patch_osif_os_task_priority_get;
+extern BOOL_PATCH_FUNC patch_osif_os_task_priority_set;
+
+extern BOOL_PATCH_FUNC patch_osif_os_task_signal_create;
+
+extern BOOL_PATCH_FUNC patch_osif_os_task_status_dump;
+extern BOOL_PATCH_FUNC patch_osif_os_task_dlps_return_idle_task;
+extern BOOL_PATCH_FUNC patch_osif_os_task_notify_take;
+extern BOOL_PATCH_FUNC patch_osif_os_task_notify_give;
+
+extern BOOL_PATCH_FUNC patch_osif_os_lock;
+extern BOOL_PATCH_FUNC patch_osif_os_unlock;
+extern BOOL_PATCH_FUNC patch_osif_os_sem_create;
+extern BOOL_PATCH_FUNC patch_osif_os_sem_delete;
+extern BOOL_PATCH_FUNC patch_osif_os_sem_take;
+extern BOOL_PATCH_FUNC patch_osif_os_sem_give;
+extern BOOL_PATCH_FUNC patch_osif_os_mutex_create;
+extern BOOL_PATCH_FUNC patch_osif_os_mutex_delete;
+extern BOOL_PATCH_FUNC patch_osif_os_mutex_take;
+extern BOOL_PATCH_FUNC patch_osif_os_mutex_give;
+
+extern BOOL_PATCH_FUNC patch_osif_os_msg_queue_create_intern;
+extern BOOL_PATCH_FUNC patch_osif_os_msg_queue_delete_intern;
+extern BOOL_PATCH_FUNC patch_osif_os_msg_queue_peek_intern;
+extern BOOL_PATCH_FUNC patch_osif_os_msg_send_intern;
+extern BOOL_PATCH_FUNC patch_osif_os_msg_recv_intern;
+extern BOOL_PATCH_FUNC patch_osif_os_msg_peek_intern;
+
+extern BOOL_PATCH_FUNC patch_osif_os_mem_alloc_intern;
+extern BOOL_PATCH_FUNC patch_osif_os_mem_zalloc_intern;
+extern BOOL_PATCH_FUNC patch_osif_os_mem_aligned_alloc_intern;
+extern BOOL_PATCH_FUNC patch_osif_os_mem_free;
+extern BOOL_PATCH_FUNC patch_osif_os_mem_aligned_free;
+extern BOOL_PATCH_FUNC patch_osif_os_mem_peek;
+extern BOOL_PATCH_FUNC patch_osif_os_mem_check_heap_usage;
+
+extern BOOL_PATCH_FUNC patch_osif_os_queue_in;
+extern BOOL_PATCH_FUNC patch_osif_os_queue_out;
+extern BOOL_PATCH_FUNC patch_osif_os_queue_insert;
+extern BOOL_PATCH_FUNC patch_osif_os_queue_delete;
+
+extern BOOL_PATCH_FUNC patch_osif_os_timer_id_get;
+extern BOOL_PATCH_FUNC patch_osif_os_timer_create;
+extern BOOL_PATCH_FUNC patch_osif_os_timer_start;
+extern BOOL_PATCH_FUNC patch_osif_os_timer_restart;
+extern BOOL_PATCH_FUNC patch_osif_os_timer_stop;
+extern BOOL_PATCH_FUNC patch_osif_os_timer_delete;
+extern BOOL_PATCH_FUNC patch_osif_os_timer_dump;
+extern BOOL_PATCH_FUNC patch_osif_os_timer_state_get;
+extern BOOL_PATCH_FUNC patch_osif_os_timer_init;
+extern BOOL_PATCH_FUNC patch_osif_os_timer_number_get;
+extern BOOL_PATCH_FUNC patch_osif_os_timer_pend_function_call;
+extern BOOL_PATCH_FUNC patch_osif_os_timer_get_auto_reload;
+extern BOOL_PATCH_FUNC patch_osif_os_timer_is_timer_active;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _OS_PATCH_H_ */
diff --git a/bee/os/osif/inc/rtl8752h/os_pm.h b/bee/os/osif/inc/rtl8752h/os_pm.h
new file mode 100644
index 00000000..da48ef57
--- /dev/null
+++ b/bee/os/osif/inc/rtl8752h/os_pm.h
@@ -0,0 +1,89 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _OS_POWER_MANAGER_H_
+#define _OS_POWER_MANAGER_H_
+#include <stdbool.h>
+#include <stdint.h>
+#include <stddef.h>
+#include "power_manager_interface.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define UPDATE_TICK_COUNT()\
+    if (portNVIC_INT_CTRL_REG & SCB_ICSR_PENDSTSET_Msk)\
+    {\
+        os_systick_handler();\
+        portNVIC_INT_CTRL_REG = SCB_ICSR_PENDSTCLR_Msk;\
+    }
+
+#define US_TO_TICK_COUNT(us, residual)\
+    cal_quotient_remainder(1000000 * (uint64_t)(os_sys_tick_clk_get() / os_sys_tick_rate_get()), os_sys_tick_clk_get(), us, &residual)
+
+#define US_TO_SYSTICK(us, residual)\
+    cal_quotient_remainder(1000000, os_sys_tick_clk_get(), us, &residual)
+
+#define TICK_COUNT_TO_US(tick_count)\
+    cal_quotient_remainder(os_sys_tick_clk_get(), 1000000 * (uint64_t)(os_sys_tick_clk_get() / os_sys_tick_rate_get()), tick_count, NULL)
+
+#define SYSTICK_TO_US(systick)\
+    cal_quotient_remainder(os_sys_tick_clk_get(), 1000000, systick, NULL)
+
+#define SYSTICK_RELOAD_VALUE    (os_sys_tick_clk_get() / os_sys_tick_rate_get() - 1)
+
+typedef enum
+{
+    PLATFORM_PM_EXCLUDED_TIMER,
+    PLATFORM_PM_EXCLUDED_TASK,
+    PLATFORM_PM_EXCLUDED_TYPE_MAX,
+} PlatformExcludedHandleType;
+
+typedef struct
+{
+    struct PlatformPMExcludedHandleQueueElem *pNext;
+    void **handle;
+} PlatformPMExcludedHandleQueueElem;
+
+typedef union
+{
+    uint8_t value[1];
+    struct
+    {
+        uint8_t os_pm_statistic:        1;
+        uint8_t rsvd:                   7;
+    };
+} OSPMFeatureConfig;
+
+typedef struct
+{
+    uint32_t last_sleep_clk;
+    uint32_t last_sleep_systick;
+    uint32_t tickcount_restore_remain_us;
+} OSPMSystem;
+
+extern bool (*os_sched_restore)(void);
+extern void os_systick_handler(void);
+extern uint32_t (*os_sys_tick_rate_get)(void);
+extern uint32_t (*os_sys_tick_clk_get)(void);
+extern uint64_t os_sys_tick_increase(uint32_t tick_increment);
+
+extern uint32_t (*os_pm_next_timeout_value_get)(void);
+extern bool (*os_register_pm_excluded_handle)(void **pp_handle, PlatformExcludedHandleType type);
+extern bool (*os_unregister_pm_excluded_handle)(void **pp_handle, PlatformExcludedHandleType type);
+extern void (*os_pm_store_tickcount)(void);
+extern void (*os_pm_restore_tickcount)(void);
+extern PMCheckResult(*os_pm_check)(uint32_t *wakeup_time_diff);
+extern void (*os_pm_store)(void);
+extern void (*os_pm_restore)(void);
+extern void (*os_pm_init)(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _OS_POWER_MANAGER_H_ */
diff --git a/bee/os/osif/inc/rtl8752h/os_queue.h b/bee/os/osif/inc/rtl8752h/os_queue.h
new file mode 100644
index 00000000..be1a261d
--- /dev/null
+++ b/bee/os/osif/inc/rtl8752h/os_queue.h
@@ -0,0 +1,313 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _OS_QUEUE_H_
+#define _OS_QUEUE_H_
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup  OS      OSIF APIs
+ * \defgroup    Queue   List Queue
+ *
+ * \brief   Initialize and manage List Queue functions.
+ * \details List Queue is designed as a FIFO-like list, which can enqueue, dequeue and peek
+ *          the list. While, List Queue also keeps these functionalities such as deleting
+ *          and inserting the speicified list item.\n
+ *
+ * \image html OS-queue-overview.jpg "List Queue Overview" width=466px height=256px
+ *
+ * \ingroup     OS
+ */
+
+
+/**
+ * os_queue.h
+ *
+ * \brief   The element structure of List Queue.
+ *
+ * \ingroup  Queue
+ */
+typedef struct t_os_queue_elem
+{
+    struct t_os_queue_elem *p_next; /**< Pointer to next list queue element. */
+} T_OS_QUEUE_ELEM;
+
+/**
+ * os_queue.h
+ *
+ * \brief   The header structure of List Queue.
+ *
+ * \ingroup  Queue
+ */
+typedef struct t_os_queue
+{
+    T_OS_QUEUE_ELEM *p_first;   /**< Pointer to the first queue element. */
+    T_OS_QUEUE_ELEM *p_last;    /**< Pointer to the last queue element. */
+    uint16_t         count;     /**< The queue element count. */
+    uint16_t         flags;     /**< The flags for customer usage. */
+} T_OS_QUEUE;
+
+/**
+ * os_queue.h
+ *
+ * \brief   Initialize the list queue.
+ *
+ * \param[in]   p_queue  Pointer to the list queue header.
+ *
+ * \return      None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * T_OS_QUEUE  test_queue;
+ *
+ * int test(void)
+ * {
+ *     // Initialize the queue before operating it.
+ *     os_queue_init(&test_queue);
+ * }
+ * \endcode
+ *
+ * \ingroup  Queue
+ */
+void  os_queue_init(T_OS_QUEUE *p_queue);
+
+/**
+ * os_queue.h
+ *
+ * \brief   Enqueue an element to the back of the list queue.
+ *
+ * \param[in]   p_queue Pointer to the list queue header.
+ *
+ * \param[in]   p_elem  The list queue element being enqueued.
+ *
+ * \return      None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * struct test_item
+ * {
+ *     struct test_item *p_next; // Pointer to the next item, must be the first field.
+ *     uint32_t          id;
+ *     uint8_t           data[10];
+ * }
+ *
+ * T_OS_QUEUE  test_queue;
+ *
+ * struct test_item a_item;
+ *
+ * int test(void)
+ * {
+ *     // Initialize the queue before operating it.
+ *     os_queue_init(&test_queue);
+ *
+ *     // Enqueue the item.
+ *     os_queue_in(&test_queue, &a_item);
+ * }
+ * \endcode
+ *
+ * \ingroup  Queue
+ */
+void  os_queue_in(T_OS_QUEUE *p_queue, void *p_elem);
+
+/**
+ * os_queue.h
+ *
+ * \brief   Dequeue an element from the front of the list queue.
+ *
+ * \param[in]   p_queue  Pointer to the list queue header.
+ *
+ * \return  The first element from the list queue. If the returned address is
+ *          NULL, the list queue is empty.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * struct test_item
+ * {
+ *     struct test_item *p_next; // Pointer to the next item, must be the first field.
+ *     uint32_t          id;
+ *     uint8_t           data[10];
+ * }
+ *
+ * T_OS_QUEUE  test_queue;
+ *
+ * struct test_item a_item;
+ *
+ * int test(void)
+ * {
+ *     struct test_item *p_item;
+ *
+ *     // Initialize the queue before operating it.
+ *     os_queue_init(&test_queue);
+ *
+ *     // Enqueue the item.
+ *     os_queue_in(&test_queue, &a_item);
+ *
+ *     // Then dequeue the item from the list queue.
+ *     p_item = os_queue_out(&test_queue);
+ * }
+ * \endcode
+ *
+ * \ingroup  Queue
+ */
+void *os_queue_out(T_OS_QUEUE *p_queue);
+
+/**
+ * os_queue.h
+ *
+ * \brief  Peek an element from the list queue.
+ *
+ * \param[in]   p_queue  Pointer to the list queue header.
+ *
+ * \return  The first element from the list queue. If the returned address is
+ *          NULL, the list queue is empty.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * struct test_item
+ * {
+ *     struct test_item *p_next; // Pointer to the next item, must be the first field.
+ *     uint32_t          id;
+ *     uint8_t           data[10];
+ * }
+ *
+ * T_OS_QUEUE  test_queue;
+ *
+ * struct test_item a_item;
+ *
+ * int test(void)
+ * {
+ *     struct test_item *p_item;
+ *
+ *     // Initialize the queue before operating it.
+ *     os_queue_init(&test_queue);
+ *
+ *     // Enqueue the item.
+ *     os_queue_in(&test_queue, &a_item);
+ *
+ *     // Peek but not remove the item from the list queue.
+ *     p_item = os_queue_peek(&test_queue);
+ * }
+ * \endcode
+ *
+ * \ingroup  Queue
+ */
+void *os_queue_peek(T_OS_QUEUE *p_queue);
+
+/**
+ * os_queue.h
+ *
+ * \brief   Insert an element to the list queue.
+ *
+ * \param[in]   p_queue     Pointer to the list queue header.
+ *
+ * \param[in]   p_elem      The element which the new element to be inserted behind.
+ *
+ * \param[in]   p_new_elem  The inserted element.
+ *
+ * \return      None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * struct test_item
+ * {
+ *     struct test_item *p_next; // Pointer to the next item, must be the first field.
+ *     uint32_t          id;
+ *     uint8_t           data[10];
+ * }
+ *
+ * T_OS_QUEUE  test_queue;
+ *
+ * struct test_item item1;
+ * struct test_item item2;
+ * struct test_item item3;
+ *
+ * int test(void)
+ * {
+ *     struct test_item *p_item;
+ *
+ *     // Initialize the queue before operating it.
+ *     os_queue_init(&test_queue);
+ *
+ *     // Enqueue the item 1.
+ *     os_queue_in(&test_queue, &item1);
+ *
+ *     // Enqueue the item 2.
+ *     os_queue_in(&test_queue, &item2);
+ *
+ *     // Insert the item 3 behind item 1 but before item 2.
+ *     os_queue_insert(&test_queue, &item1, &item3);
+ * }
+ * \endcode
+ *
+ * \ingroup  Queue
+ */
+void  os_queue_insert(T_OS_QUEUE *p_queue, void *p_elem, void *p_new_elem);
+
+/**
+ * os_queue.h
+ *
+ * \brief   Delete an element from the list queue.
+ *
+ * \param[in]   p_queue  Pointer to the list queue header.
+ *
+ * \param[in]   p_elem   The element to be deleted from the list queue.
+ *
+ * \return          The status of queue element deletion.
+ * \retval true     Queue element was deleted successfully.
+ * \retval false    Queue element was failed to delete when the queue is empty
+ *                  or the being deleted queue element is not belonged to the queue.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * struct test_item
+ * {
+ *     struct test_item *p_next; // Pointer to the next item, must be the first field.
+ *     uint32_t          id;
+ *     uint8_t           data[10];
+ * }
+ *
+ * T_OS_QUEUE  test_queue;
+ *
+ * struct test_item item1;
+ * struct test_item item2;
+ * struct test_item item3;
+ *
+ * int test(void)
+ * {
+ *     struct test_item *p_item;
+ *
+ *     // Initialize the queue before operating it.
+ *     os_queue_init(&test_queue);
+ *
+ *     // Enqueue the item 1.
+ *     os_queue_in(&test_queue, &item1);
+ *
+ *     // Enqueue the item 2.
+ *     os_queue_in(&test_queue, &item2);
+ *
+ *     // Enqueue the item 3.
+ *     os_queue_in(&test_queue, &item3);
+ *
+ *     // Then delete the item 2.
+ *     os_queue_delete(&test_queue, &item12);
+ * }
+ * \endcode
+ *
+ * \ingroup  Queue
+ */
+bool  os_queue_delete(T_OS_QUEUE *p_queue, void *p_elem);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* _OS_QUEUE_H_ */
diff --git a/bee/os/osif/inc/rtl8752h/os_sched.h b/bee/os/osif/inc/rtl8752h/os_sched.h
new file mode 100644
index 00000000..36d73ec7
--- /dev/null
+++ b/bee/os/osif/inc/rtl8752h/os_sched.h
@@ -0,0 +1,316 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _OS_SCHED_H_
+#define _OS_SCHED_H_
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup  OS          OSIF APIs
+ * \defgroup    Schedule    Kernel Scheduler
+ *
+ * \brief       Manage the kernel scheduler functions.
+ *
+ * \ingroup     OS
+ */
+
+
+/**
+ * os_sched.h
+ *
+ * \brief       Delay current task for a given period in milliseconds.
+ *
+ * \param[in]   ms  The amout of timer in milliseconds that the current task
+ *                  should block.
+ *
+ * \return      None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * // Task routine implementation.
+ * void task_routine(void *p_param)
+ * {
+ *     for (;;)
+ *     {
+ *          // Task code goes here.
+ *          os_delay(100);
+ *
+ *          // Do something here per 100ms.
+ *     }
+ * }
+ * \endcode
+ *
+ * \ingroup  Schedule
+ */
+void os_delay(uint32_t ms);
+
+/**
+ * os_sched.h
+ *
+ * \brief   Get the time in milliseconds since os_sched_start() API function was called.
+ *
+ * \param   None
+ *
+ * \return  The time in milliseconds. Note the time represented by a 32-bit integer
+ *          may be overflowed.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * // Task routine implementation.
+ * void task_routine(void *p_param)
+ * {
+ *     uint32_t last_time;
+ *
+ *     // Get the last timestamp.
+ *     last_time = os_sys_time_get();
+ *
+ *     for (;;)
+ *     {
+ *          // Wait for the next cycle.
+ *          os_delay(100);
+ *
+ *          // Do something here per 100ms.
+ *     }
+ * }
+ * \endcode
+ *
+ * \ingroup  Schedule
+ */
+uint64_t os_sys_time_get(void);
+
+/**
+ * os_sched.h
+ *
+ * \brief   Get the system tick since os_sched_start() API function was called.
+ *
+ * \param   None
+ *
+ * \return  The time in system tick. Note the tick represented by a 32-bit integer
+ *          may be overflowed.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+
+* #define portTICK_PERIOD_MS   10
+
+ * // Task routine implementation.
+ * void task_routine(void *p_param)
+ * {
+ *     uint32_t beg_tick;
+ *     uint32_t end_tick;
+ *     uint32_t time;
+ *
+ *     beg_tick = os_sys_tick_get();
+ *
+ *          // Do something here
+ *
+ *     end_tick = os_sys_tick_get();
+ *
+ *     //get correct passed time in milliseconds
+ *     time = (end_tick - beg_tick) * portTICK_PERIOD_MS;
+ * }
+ * \endcode
+ *
+ * \ingroup  Schedule
+ */
+uint64_t os_sys_tick_get(void);
+
+/**
+ * os_sched.h
+ *
+ * \brief   Start the RTOS kernel scheduler.
+ *
+ * \param   None
+ *
+ * \return  The status of starting kernel scheduler.
+ * \retval  true      Scheduler was started successfully.
+ * \retval  false     Scheduler was failed to start.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * int test(void)
+ * {
+ *     // Create at least one task before starting kernel scheduler.
+ *     if (os_task_create(&p_handle, "task", task_routine,
+ *                        NULL, STACK_SIZE, TASK_PRIORITY) == true)
+ *     {
+ *         // Task created successfully.
+ *     }
+ *     else
+ *     {
+ *         // Task failed to create.
+ *         return -1;
+ *     }
+ *
+ *     // Start the kernel scheduler.
+ *     os_sched_start();
+ *
+ *     // Will not get here unless a task calls os_sched_stop().
+ * }
+ * \endcode
+ *
+ * \ingroup  Schedule
+ */
+bool os_sched_start(void);
+
+/**
+ * os_sched.h
+ *
+ * \brief   Stop the RTOS kernel scheduler. All created tasks will be automatically
+ *          deleted and multitasking (either preemptive or cooperative) stops.
+ *
+ * \param   None
+ *
+ * \return  The status of stopping kernel scheduler.
+ * \retval  true      Scheduler was stopped successfully.
+ * \retval  false     Scheduler was failed to stop.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * // Task routine implementation.
+ * void task_routine(void *p_param)
+ * {
+ *     for (;;)
+ *     {
+ *          // Task code goes here.
+ *
+ *          // At some point we want to end the real time kernel processing.
+ *          os_sched_stop();
+ *     }
+ * }
+ *
+ * int test(void)
+ * {
+ *     // Create at least one task before starting kernel scheduler.
+ *     if (os_task_create(&p_handle, "task", task_routine,
+ *                        NULL, STACK_SIZE, TASK_PRIORITY) == true)
+ *     {
+ *         // Task created successfully.
+ *     }
+ *     else
+ *     {
+ *         // Task failed to create.
+ *         return -1;
+ *     }
+ *
+ *     // Start the kernel scheduler.
+ *     os_sched_start();
+ *
+ *     // Will not get here unless a task calls os_sched_stop().
+ * }
+ * \endcode
+ *
+ * \ingroup  Schedule
+ */
+bool os_sched_stop(void);
+
+/**
+ * os_sched.h
+ *
+ * \brief   Suspends the kernel scheduler without disabling interrupts. Context
+ *          switches will not occur while the scheduler is suspended. After calling
+ *          os_sched_suspend(), the calling task will continue to execute without
+ *          risk of being swapped out until a call to os_sched_resume() has been made.
+ *
+ * \param   None
+ *
+ * \return  The status of suspending kernel scheduler.
+ * \retval  true      Scheduler was suspended successfully.
+ * \retval  false     Scheduler was failed to suspend.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * // Task routine implementation.
+ * void task_routine(void *p_param)
+ * {
+ *     for (;;)
+ *     {
+ *          // Task code goes here.
+ *
+ *          // At some point the task wants to perform a long operation, and do not
+ *          // want to get swapped out.
+ *          os_sched_suspend();
+ *
+ *          // The long operation.
+ *
+ *          // The operation is completed, and resume the scheduler.
+ *          os_sched_resume();
+ *     }
+ * }
+ * \endcode
+ *
+ * \ingroup  Schedule
+ */
+bool os_sched_suspend(void);
+
+/**
+ * os_sched.h
+ *
+ * \brief   Resume the kernel scheduler after it was suspended by a call
+ *          to os_sched_suspend().
+ *
+ * \param   None
+ *
+ * \return  The status of resuming kernel scheduler.
+ * \retval  true      Scheduler was resumed successfully.
+ * \retval  false     Scheduler was failed to resume.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * // Task routine implementation.
+ * void task_routine(void *p_param)
+ * {
+ *     for (;;)
+ *     {
+ *          // Task code goes here.
+ *
+ *          // At some point the task wants to perform a long operation, and do not
+ *          // want to get swapped out.
+ *          os_sched_suspend();
+ *
+ *          // The long operation.
+ *
+ *          // The operation is completed, and resume the scheduler.
+ *          os_sched_resume();
+ *     }
+ * }
+ * \endcode
+ *
+ * \ingroup  Schedule
+ */
+bool os_sched_resume(void);
+
+/* internal function */
+bool os_sched_is_start(void);
+
+typedef enum
+{
+    SCHEDULER_SUSPENDED = 0,
+    SCHEDULER_NOT_STARTED = 1,
+    SCHEDULER_RUNNING = 2
+} SCHEDULER_STATE;
+
+SCHEDULER_STATE os_sched_state_get(void);
+
+void os_systick_handler(void);
+
+uint64_t os_sys_tick_increase(uint32_t tick_increment);
+
+void os_vector_table_update(void);
+
+void os_init(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _OS_SCHED_H_ */
diff --git a/bee/os/osif/inc/rtl8752h/os_sync.h b/bee/os/osif/inc/rtl8752h/os_sync.h
new file mode 100644
index 00000000..eeac2edf
--- /dev/null
+++ b/bee/os/osif/inc/rtl8752h/os_sync.h
@@ -0,0 +1,477 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _OS_SYNC_H_
+#define _OS_SYNC_H_
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup  OS                  OSIF APIs
+ * \defgroup    Synchronization     Inter-Task Communication
+ *
+ * \brief   Manage Inter-task communication functions.
+ * \details Tasks need to communicate with each other or access shared resources together.
+ *          There are many ways to exchange data between tasks, for example using shared
+ *          data, polling loops and message passing.\n
+ *          Many resources can be considered as serially-reusable. This means that they
+ *          can be used repeatedly by different tasks, but only by one task at a time.\n
+ *          The following mechanisms are available to the user:\n
+ * \arg <b>Lock</b>
+ * \arg <b>Semaphore</b>
+ * \arg <b>Mutex</b>
+ *
+ * \ingroup     OS
+ */
+
+
+/**
+ * os_sync.h
+ *
+ * \brief   Enter the critical region. Disable preemptive context switch and interrupts.
+ *
+ * \param   None
+ *
+ * \return      Interrupt mask flag.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * int test(void)
+ * {
+ *     uint32_t s;
+ *
+ *     // Enter the critical section.
+ *     s = os_lock();
+ *     // Allow only one task or ISR to operate the list.
+ *     list_add(p_list, &item);
+ *     // Exit the critical section and restore ISR mask flag.
+ *     os_unlock(s);
+ * }
+ * \endcode
+ *
+ * \ingroup  Synchronization
+ */
+uint32_t os_lock(void);
+
+/**
+ * os_sync.h
+ *
+ * \brief   Exit the critical region. Enable preemptive context switch and interrupts.
+ *
+ * \param[in]   s   Interrupt mask flag to be restored.
+ *
+ * \return      None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * int test(void)
+ * {
+ *     uint32_t s;
+ *
+ *     // Enter the critical section.
+ *     s = os_lock();
+ *     // Allow only one task or ISR to operate the list.
+ *     list_add(p_list, &item);
+ *     // Exit the critical section and restore ISR mask flag.
+ *     os_unlock(s);
+ * }
+ * \endcode
+ *
+ * \ingroup  Synchronization
+ */
+void os_unlock(uint32_t s);
+
+/**
+ * os_sync.h
+ *
+ * \brief   Create a counting semaphore.
+ *
+ * \details Semaphores are used to manage and protect access to shared resources. A semaphore
+ *          can be used to permit a fixed number of task to access a pool of shared resources.
+ *          Using semaphores.\n
+ *          A semaphore object should be initialized to the maximum number of available tokens.
+ *          This number of available resources is specified as parameter of the os_sem_create()
+ *          function. Each time a semaphore token is obtained with os_sem_take(), the semaphore
+ *          count is decremented. When the semaphore count is 0, no semaphore token can be obtained.
+ *          The task that tries to obtain the semaphore token needs to wait until the next token
+ *          is free. Semaphores are released with os_sem_give() incrementing the semaphore count.
+ *
+ * \image html OS-semaphore-overview.jpg "Semaphore Overview" width=496px height=346px
+ *
+ * \param[out]  pp_handle   Used to pass back the created semaphore handle.
+ *
+ * \param[in]   init_count  The count value assigned to the semaphore when created.
+ *
+ * \param[in]   max_count   The maximum count value that can be reached. If the max_count is 1,
+ *                          a binary semaphore is being created.
+ *
+ * \return           The status of the semaphore creation.
+ * \retval true      Semaphore was created successfully.
+ * \retval false     Semaphore was failed to create.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * int test(void)
+ * {
+ *     void *p_handle;
+ *
+ *     // Create a semaphore with initial value 0 and maximum value 10.
+ *     if (os_sem_create(&p_handle, 0, 10) == true)
+ *     {
+ *         // Semaphore created successfully.
+ *     }
+ *     else
+ *     {
+ *         // Semaphore failed to create.
+ *         return -1;
+ *     }
+ *
+ *     return 0;
+ * }
+ * \endcode
+ *
+ * \ingroup  Synchronization
+ */
+bool os_sem_create(void **pp_handle, const char *p_name, uint32_t init_count, uint32_t max_count);
+
+/**
+ * os_sync.h
+ *
+ * \brief   Delete a semaphore.
+ *
+ * \param[in]   p_handle    The handle of the semaphore to be deleted.
+ *
+ * \return           The status of the semaphore deletion.
+ * \retval true      Semaphore was deleted successfully.
+ * \retval false     Semaphore was failed to delete.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * int test(void)
+ * {
+ *     void *p_handle;
+ *
+ *     // Create a semaphore with initial value 0 and maximum value 10.
+ *     if (os_sem_create(&p_handle, 0, 10) == true)
+ *     {
+ *         // Semaphore created successfully.
+ *     }
+ *     else
+ *     {
+ *         // Semaphore failed to create.
+ *         return -1;
+ *     }
+ *
+ *     // Delete the created semaphore.
+ *     os_sem_delete(p_handle);
+ *
+ *     return 0;
+ * }
+ * \endcode
+ *
+ * \ingroup  Synchronization
+ */
+bool os_sem_delete(void *p_handle);
+
+/**
+ * os_sync.h
+ *
+ * \brief   Take a semaphore.
+ *
+ * \param[in]   p_handle    The handle of the semaphore to be taken.
+ *
+ * \param[in]   wait_ms     The time in milliseconds to wait for the semaphore to become
+ *                          available.
+ * \arg \c 0           No blocking and return immediately.
+ * \arg \c 0xFFFFFFFF  Block infinitely until the semaphore taken.
+ * \arg \c others      The timeout value in milliseconds.
+ *
+ * \return           The status of the semaphore taking.
+ * \retval true      Semaphore was taken successfully.
+ * \retval false     Semaphore was failed to take.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * void *p_handle = NULL;
+ *
+ * // One task creates a semaphore.
+ * void task1(void *p_param)
+ * {
+ *     // Create a full binary semaphore.
+ *     os_sem_create(&p_handle, 1, 1);
+ * }
+ *
+ * // Anohter task uses the semaphore.
+ * void task2(void *p_param)
+ * {
+ *     // See if we can obtain the semaphore. If the semaphore is
+ *     // not available, wait for 100ms.
+ *     if (os_sem_take(p_handle, 100) == true)
+ *     {
+ *         // Access the share resource.
+ *
+ *         // Finish accessing the share resource, then release the semaphore.
+ *         os_sem_give(p_handle);
+ *     }
+ *     else
+ *     {
+ *         // Could not access the share resource.
+ *     }
+ * }
+ * \endcode
+ *
+ * \ingroup  Synchronization
+ */
+bool os_sem_take(void *p_handle, uint32_t wait_ms);
+
+/**
+ * os_sync.h
+ *
+ * \brief   Give a semaphore.
+ *
+ * \param[in]   p_handle    The handle of the semaphore to be given.
+ *
+ * \return           The status of the semaphore giving.
+ * \retval true      Semaphore was given successfully.
+ * \retval false     Semaphore was failed to give.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * int test(void)
+ * {
+ *     void *p_handle = NULL;
+ *
+ *     // Create an empty binary semaphore.
+ *     os_sem_create(&p_handle, 0, 1);
+ *
+ *     // Obtaining the empty semaphore immediately will be failed.
+ *     if (os_sem_take(p_handle, 0) == false)
+ *     {
+ *         // Failed.
+ *     }
+ *
+ *     // Give the sempahore
+ *     if (os_sem_give(p_hanel) == true)
+ *     {
+ *         // Now we can take the semaphore.
+ *         os_sem_take(p_handle, 0);
+ *
+ *         // Again taking the binary semaphore will be failed.
+ *         os_sem_take(p_handle, 0);
+ *     }
+ * }
+ * \endcode
+ *
+ * \ingroup  Synchronization
+ */
+bool os_sem_give(void *p_handle);
+
+/**
+ * os_sync.h
+ *
+ * \brief   Create a mutex.
+ *
+ * \details Mutex (Mutual Exclusion) is used to protect a shared resource that can be accessed
+ *          only by one task at a time.\n
+ *          A mutex is a special version of a binary empty semaphore. The advantage of a mutex
+ *          is that it introduces task ownership. When a task acquires a mutex and becomes its
+ *          owner, subsequent mutex acquires from that task will succeed immediately. Thus, mutex
+ *          acquires/releases can be nested.\n
+ *
+ * \image html OS-mutex-overview.jpg "Mutex Overview" width=451px height=196px
+ *
+ * \param[out]  pp_handle   Used to pass back the created mutex handle.
+ *
+ * \return           The status of the mutex creation.
+ * \retval true      Mutex was created successfully.
+ * \retval false     Mutex was failed to create.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * int test(void)
+ * {
+ *     void *p_handle = NULL;
+ *
+ *     // Create a mutex.
+ *     if (os_mutex_create(&p_handle) == true)
+ *     {
+ *         // The mutex created successfully.
+ *         // Now it can be used.
+ *     }
+ * }
+ * \endcode
+ *
+ * \ingroup  Synchronization
+ */
+bool os_mutex_create(void **pp_handle);
+
+/**
+ * os_sync.h
+ *
+ * \brief   Delete a mutex.
+ *
+ * \param[in]   p_handle    The handle of the mutex to be deleted.
+ *
+ * \return           The status of the Mutex deletion.
+ * \retval true      Mutex was deleted successfully.
+ * \retval false     Mutex was failed to delete.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * int test(void)
+ * {
+ *     void *p_handle;
+ *
+ *     // Create a mutex.
+ *     if (os_mutex_create(&p_handle) == true)
+ *     {
+ *         // Mutex created successfully.
+ *     }
+ *     else
+ *     {
+ *         // Mutex failed to create.
+ *         return -1;
+ *     }
+ *
+ *     // Delete the created mutex.
+ *     os_mutex_delete(p_handle);
+ *
+ *     return 0;
+ * }
+ * \endcode
+ *
+ * \ingroup  Synchronization
+ */
+bool os_mutex_delete(void *p_handle);
+
+/**
+ * os_sync.h
+ *
+ * \brief   Take a mutex.
+ *
+ * \param[in]   p_handle    The handle of the mutex to be taken.
+ *
+ * \param[in]   wait_ms     The time in milliseconds to wait for the mutex to become
+ *                          available.
+ * \arg \c 0           No blocking and return immediately.
+ * \arg \c 0xFFFFFFFF  Block infinitely until the mutex taken.
+ * \arg \c others      The timeout value in milliseconds.
+ *
+ * \return           The status of the mutex taking.
+ * \retval true      Mutex was taken successfully.
+ * \retval false     Mutex was failed to take.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * void *p_handle = NULL;
+ *
+ * // One task creates a mutex.
+ * void task1(void *p_param)
+ * {
+ *     // Create a mutex.
+ *     os_mutex_create(&p_handle);
+ * }
+ *
+ * // Anohter task uses the mutex.
+ * void task2(void *p_param)
+ * {
+ *     // See if we can obtain the mutex. If the mutex is
+ *     // not available, wait for 100ms.
+ *     if (os_mutex_take(p_handle, 100) == true)
+ *     {
+ *         // Access the share resource.
+ *
+ *         // In real code, recursive calls of mutex may occur.
+ *         os_mutex_take(p_handle, 100);
+ *         os_mutex_take(p_handle, 200);
+ *
+ *         // The mutex has now been 'taken' three times, so will not be
+ *         // available to another task until it has also been given back
+ *         // three times.
+ *         os_mutex_give(p_handle);
+ *         os_mutex_give(p_handle);
+ *         os_mutex_give(p_handle);
+ *
+ *         // Finish accessing the share resource, then release the semaphore.
+ *         // Now the mutex can be taken by other tasks.
+ *     }
+ *     else
+ *     {
+ *         // Could not access the share resource.
+ *     }
+ * }
+ * \endcode
+ *
+ * \ingroup  Synchronization
+ */
+bool os_mutex_take(void *p_handle, uint32_t wait_ms);
+
+/**
+ * os_sync.h
+ *
+ * \brief   Give a mutex.
+ *
+ * \param[in]   p_handle    The handle of the mutex to be given.
+ *
+ * \return           The status of the mutex giving.
+ * \retval true      Mutex was given successfully.
+ * \retval false     Mutex was failed to give.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * void *p_handle = NULL;
+ *
+ * // One task creates a mutex.
+ * void task1(void *p_param)
+ * {
+ *     // Create a mutex.
+ *     os_mutex_create(&p_handle);
+ * }
+ *
+ * // Anohter task uses the mutex.
+ * void task2(void *p_param)
+ * {
+ *     // See if we can obtain the mutex. If the mutex is
+ *     // not available, wait for 100ms.
+ *     if (os_mutex_take(p_handle, 100) == true)
+ *     {
+ *         // Access the share resource.
+ *
+ *         // In real code, recursive calls of mutex may occur.
+ *         os_mutex_take(p_handle, 100);
+ *         os_mutex_take(p_handle, 200);
+ *
+ *         // The mutex has now been 'taken' three times, so will not be
+ *         // available to another task until it has also been given back
+ *         // three times.
+ *         os_mutex_give(p_handle);
+ *         os_mutex_give(p_handle);
+ *         os_mutex_give(p_handle);
+ *
+ *         // Finish accessing the share resource, then release the semaphore.
+ *         // Now the mutex can be taken by other tasks.
+ *     }
+ *     else
+ *     {
+ *         // Could not access the share resource.
+ *     }
+ * }
+ * \endcode
+ *
+ * \ingroup  Synchronization
+ */
+bool os_mutex_give(void *p_handle);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _OS_SYNC_H_ */
diff --git a/bee/os/osif/inc/rtl8752h/os_task.h b/bee/os/osif/inc/rtl8752h/os_task.h
new file mode 100644
index 00000000..4a1b1ae5
--- /dev/null
+++ b/bee/os/osif/inc/rtl8752h/os_task.h
@@ -0,0 +1,448 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _OS_TASK_H_
+#define _OS_TASK_H_
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup    OS_TASK Task Management
+ *
+ * \brief   Define, create, and control task functions.
+ * \details The Task Management function group allows creating, deleting, and controlling tasks
+ *          in the system.\n
+ * Tasks can be in the following states:\n
+ * \arg <b>RUNNING:</b> The task that is currently running is in the running state.
+ *                      Only one task at a time can be in this state.
+ * \arg <b>READY:</b> Tasks that are ready to run are in the ready state. Once the
+ *                    running task has terminated or is waiting, the next
+ *                    ready task with the highest priority becomes the running task.
+ * \arg <b>WAITING:</b> Tasks that are waiting for an event to occur are in the waiting state.
+ * \arg <b>INACTIVE:</b> Tasks that are not created or terminated are in the inactive state.
+ *                       These tasks typically consume no system resources.
+ *
+ * \image html OS-task-state-transition.jpg "Task State Transition" width=50px height=50px
+ *
+ */
+
+/*============================================================================*
+ *                              Functions
+*============================================================================*/
+/** @defgroup OS_TASK_Exported_Functions OS Task Exported Functions
+  * \ingroup  OS_TASK
+  * @{
+  */
+
+/**
+ *
+ * \brief Create a new task and add it to the list of tasks that are ready to run.
+ *
+ * \param[out]  pp_handle   Pointer used to pass back a handle by which the created task
+ *                         can be referenced.
+ *
+ * \param[in]   p_name     A descriptive name for the task.
+ *
+ * \param[in]   p_routine  Pointer to task routine function that must be implemented
+ *                         to never return.
+ *
+ * \param[in]   p_param    Pointer parameter passed to the task routine function.
+ *
+ * \param[in]   stack_size The size of the task stack that is specified as the number
+ *                         of bytes.
+ *
+ * \param[in]   priority   The priority at which the task should run. Higher priority
+ *                         task has a higher priority value.
+ *
+ * \return           The status of the task creation.
+ * \retval true      Task was created successfully and added to the task ready list.
+ * \retval false     Task failed to be created.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * // Task routine implementation.
+ * void task_routine(void *p_param)
+ * {
+ *     for (;;)
+ *     {
+ *          // Task code goes here.
+ *     }
+ * }
+ *
+ * // Task to be created.
+ * int test(void)
+ * {
+ *     void *p_handle = NULL;
+ *     uint32_t task_param;
+ *
+ *     if (os_task_create(&p_handle, "task", task_routine,
+ *                        &task_param, STACK_SIZE, TASK_PRIORITY) == true)
+ *     {
+ *         // Task created successfully.
+ *     }
+ *     else
+ *     {
+ *         // Task failed to create.
+ *         return -1;
+ *     }
+ *
+ *     // Use the handle to delete the task.
+ *     os_task_delete(p_handle);
+ *
+ *     return 0;
+ * }
+ * \endcode
+ *
+ */
+bool os_task_create(void **pp_handle, const char *p_name, void (*p_routine)(void *),
+                    void *p_param, uint16_t stack_size, uint16_t priority);
+
+/**
+ *
+ * \brief Remove a task from RTOS's task management. The task being deleted will be removed
+ * from RUNNING, READY, or WAITING state.
+ *
+ * \param[in] p_handle  The handle of the task to be deleted.
+ *
+ * \return           The status of the task deletion.
+ * \retval true      Task was deleted successfully.
+ * \retval false     Task failed to be deleted.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * // Task routine implementation.
+ * void task_routine(void *p_param)
+ * {
+ *     for (;;)
+ *     {
+ *          // Task code goes here.
+ *     }
+ * }
+ *
+ * // Task to be created and deleted.
+ * int test(void)
+ * {
+ *     void *p_handle = NULL;
+ *     uint32_t task_param;
+ *
+ *     if (os_task_create(&p_handle, "task", task_routine,
+ *                        &task_param, STACK_SIZE, TASK_PRIORITY) == true)
+ *     {
+ *         // Task created successfully.
+ *     }
+ *     else
+ *     {
+ *         // Task failed to create.
+ *         return -1;
+ *     }
+ *
+ *     // Use the handle to delete the task.
+ *     os_task_delete(p_handle);
+ *
+ *     return 0;
+ * }
+ * \endcode
+ *
+ */
+bool os_task_delete(void *p_handle);
+
+/**
+ *
+ * \brief Suspend the task. The suspended task will not be scheduled and never get
+ * any microcontroller processing time.
+ *
+ * \param[in] p_handle  The handle of the task to be suspended.
+ *
+ * \return           The status of the task suspension.
+ * \retval true      Task was suspended successfully.
+ * \retval false     Task failed to be suspended.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * // Task routine implementation.
+ * void task_routine(void *p_param)
+ * {
+ *     for (;;)
+ *     {
+ *          // Task code goes here.
+ *     }
+ * }
+ *
+ * // Task to be created and suspended.
+ * int test(void)
+ * {
+ *     void *p_handle = NULL;
+ *     uint32_t task_param;
+ *
+ *     if (os_task_create(&p_handle, "task", task_routine,
+ *                        &task_param, STACK_SIZE, TASK_PRIORITY) == true)
+ *     {
+ *         // Task created successfully.
+ *     }
+ *     else
+ *     {
+ *         // Task failed to create.
+ *         return -1;
+ *     }
+ *
+ *     // Use the handle to suspend the created task.
+ *     os_task_suspend(p_handle);
+ *
+ *     return 0;
+ * }
+ * \endcode
+ *
+ */
+bool os_task_suspend(void *p_handle);
+
+/**
+ *
+ * \brief Resume the suspended task.
+ *
+ * \param[in] p_handle  The handle of the task to be resumed.
+ *
+ * \return           The status of the task resume.
+ * \retval true      Task was resumed successfully.
+ * \retval false     Task failed to resume.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * // Task routine implementation.
+ * void task_routine(void *p_param)
+ * {
+ *     for (;;)
+ *     {
+ *          // Task code goes here.
+ *     }
+ * }
+ *
+ * // Task to be suspended and resumed.
+ * int test(void)
+ * {
+ *     void *p_handle = NULL;
+ *     uint32_t task_param;
+ *
+ *     if (os_task_create(&p_handle, "task", task_routine,
+ *                        &task_param, STACK_SIZE, TASK_PRIORITY) == true)
+ *     {
+ *         // Task created successfully.
+ *     }
+ *     else
+ *     {
+ *         // Task failed to create.
+ *         return -1;
+ *     }
+ *
+ *     // Use the handle to suspend the created task.
+ *     os_task_suspend(p_handle);
+ *
+ *     // Resume the suspended task by ourselves.
+ *     os_task_resume(p_handle);
+ *     return 0;
+ * }
+ * \endcode
+ *
+ */
+bool os_task_resume(void *p_handle);
+
+/**
+ *
+ * \brief Force a context switch and pass control to the next task that is in
+ * ready state.
+ *
+ * \return           The status of the task resume.
+ * \retval true      Task yielded successfully.
+ * \retval false     Task failed to yield.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * // Task routine implementation.
+ * void task_routine(void *p_param)
+ * {
+ *     for (;;)
+ *     {
+ *          // Force a context switch
+ *          os_task_yield();
+ *     }
+ * }
+ *
+ * // Task to be created.
+ * int test(void)
+ * {
+ *     void *p_handle = NULL;
+ *     uint32_t task_param;
+ *
+ *     if (os_task_create(&p_handle, "task", task_routine,
+ *                        &task_param, STACK_SIZE, TASK_PRIORITY) == true)
+ *     {
+ *         // Task created successfully.
+ *     }
+ *     else
+ *     {
+ *         // Task failed to create.
+ *         return -1;
+ *     }
+ *
+ *     return 0;
+ * }
+ * \endcode
+ *
+ */
+bool os_task_yield(void);
+
+/**
+ *
+ * \brief Get the handle of the currently running task.
+ *
+ * \param[out] pp_handle  Pointer used to pass back a handle by which the current task
+ *                        can be referenced.
+ *
+ * \return           The status of getting the current task handle.
+ * \retval true      Task handle was obtained successfully.
+ * \retval false     Task handle failed to get.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * // Get current task handle.
+ * int test(void)
+ * {
+ *     void *p_handle = NULL;
+ *
+ *     os_task_handle_get(&p_handle);
+ *
+ *     return 0;
+ * }
+ * \endcode
+ *
+ */
+bool os_task_handle_get(void **pp_handle);
+
+/**
+ *
+ * \brief Get the priority of the specified task.
+ *
+ * \param[in] p_handle    The handle of the task to be queried. Passing a NULL handle
+ *                        means querying the priority of the current task.
+ *
+ * \param[in] p_priority Pointer used to pass back the priority of the task.
+ *
+ * \return           The status of getting the task priority.
+ * \retval true      Task priority was obtained successfully.
+ * \retval false     Task priority failed to get.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * int test(void)
+ * {
+ *     void *p_handle = NULL;
+ *     uint16_t priority;
+ *
+ *     if (os_task_create(&p_handle, "task", task_routine,
+ *                        NULL, STACK_SIZE, TASK_PRIORITY) == true)
+ *     {
+ *         // Task created successfully.
+ *     }
+ *     else
+ *     {
+ *         // Task failed to create.
+ *         return -1;
+ *     }
+ *
+ *     // Get the task priority.
+ *     os_task_priority_get(p_handle, &priority);
+ *
+ *     return 0;
+ * }
+ * \endcode
+ *
+ */
+bool os_task_priority_get(void *p_handle, uint16_t *p_priority);
+
+/**
+ *
+ * \brief Set the priority of the specified task.
+ *
+ * \param[in] p_handle  The handle of the task for which the priority is being set.
+ *                      Passing a NULL handle means setting the priority of the
+ *                      current task.
+ *
+ * \param[in] priority  The priority to which the task will be set.
+ *
+ * \return           The status of setting the task priority.
+ * \retval true      Task priority was set successfully.
+ * \retval false     Task priority failed to set.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * int test(void)
+ * {
+ *     void *p_handle = NULL;
+ *     uint16_t priority;
+ *
+ *     if (os_task_create(&p_handle, "task", task_routine,
+ *                        NULL, STACK_SIZE, TASK_PRIORITY) == true)
+ *     {
+ *         // Task created successfully.
+ *     }
+ *     else
+ *     {
+ *         // Task failed to create.
+ *         return -1;
+ *     }
+ *
+ *     // Use the handle to raise the created task priority.
+ *     os_task_priority_set(p_handle, TASK_PRIORITY + 1);
+ *
+ *     // Use a NULL handle to raise the current task priority.
+ *     os_task_priority_set(NULL, TASK_PRIORITY + 1);
+ *
+ *     return 0;
+ * }
+ * \endcode
+ *
+ */
+bool os_task_priority_set(void *p_handle, uint16_t priority);
+
+/** End of group OS_TASK_Exported_Functions
+  * @}
+  */
+
+/**
+  * \cond     private
+  * \defgroup OS_TASK_Private_Functions
+  * \{
+  */
+
+bool os_task_signal_create(void *p_handle, uint32_t count);
+
+void os_task_status_dump(void);
+
+void os_task_dlps_return_idle_task(void);
+
+bool os_task_notify_take(long xClearCountOnExit, uint32_t xTicksToWait, uint32_t *p_notify);
+
+bool os_task_notify_give(void *p_handle);
+
+/**
+  *  End of OS_TASK_Private_Functions
+  * \}
+  * \endcond
+  */
+
+/** End of OS_TASK
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _OS_TASK_H_ */
diff --git a/bee/os/osif/inc/rtl8752h/os_timer.h b/bee/os/osif/inc/rtl8752h/os_timer.h
new file mode 100644
index 00000000..314ba889
--- /dev/null
+++ b/bee/os/osif/inc/rtl8752h/os_timer.h
@@ -0,0 +1,519 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _OS_TIMER_H_
+#define _OS_TIMER_H_
+
+#include <stdint.h>
+#include <stdbool.h>
+//#include "timers.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup  OS      OSIF
+ * \defgroup    Timer   Timer Management
+ *
+ * \brief   Create and control software timer and timer callback functions.
+ * \details The Timer Management function group allows to create, delete, and control software
+ *          timers in the system. The software timers can be configured as one-short or periodic
+ *          timers. When a timer expires, a callback function associated with the timer is
+ *          executed.\n
+ * Timers can be in the following two states:\n
+ * \arg <b>Dormant</b> The timer first enters <b>Dormant</b> or <b>Inactive</b> state when created.
+ *                     If a one-short timer expires but not restarts yet, or is stopped the timer
+ *                     will be tranformed from <b>Active</b> state into <b>Dormant</b> state.
+ * \arg <b>Active</b> The timer enters <b>Active</b> state If the timer starts or restarts. When
+ *                    expired, the callback function associcated with the timer will be executed.
+ *
+ * \image html OS-timer-state-transition.jpg "Software Timer State Transition" width=617px height=321px
+ *
+ * \ingroup     OS
+ */
+
+
+/**
+ * os_timer.h
+ *
+ * \brief    Get the ID assigned to the timer when created.
+ *
+ * \param[in]   pp_handle   Pointer to the created timer handle.
+ *
+ * \param[out]  p_timer_id  Used to pass back the ID assigned to the timer.
+ *
+ * \return           The status of the timer id getting.
+ * \retval true      Timer ID was got successfully.
+ * \retval false     Timer ID was failed to get.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * // Timer callback function.
+ * void timer_callback(void *p_handle)
+ * {
+ *     uint32_t timer_id;
+ *
+ *     // Which timer expired?
+ *     os_timer_id_get(&p_handle, &timer_id);
+ *
+ *     if (timer_id == TIMER_ID)
+ *     {
+ *          // Delete the specified timer.
+ *          os_timer_delete(&p_handle);
+ *     }
+ * }
+ *
+ * #define TIMER_ID 1
+ *
+ * // Timer to be created.
+ * int test(void)
+ * {
+ *     void *p_handle = NULL;
+ *
+ *     if (os_timer_create(&p_handle, "timer", TIMER_ID,
+ *                        INTERVAL_MS, false, timer_callback) == true)
+ *     {
+ *         // Timer created successfully, start the timer.
+ *         os_timer_start(&p_handle);
+ *     }
+ *     else
+ *     {
+ *         // Timer failed to create.
+ *         return -1;
+ *     }
+ *
+ *     return 0;
+ * }
+ * \endcode
+ *
+ * \ingroup  Timer
+ */
+bool os_timer_id_get(void **pp_handle, uint32_t *p_timer_id);
+
+/**
+ * os_timer.h
+ *
+ * \brief   Create a new software timer instance. This allocates the storage required by
+ *          the new timer, initializes the new timers internal state, and returns a handle
+ *          by which the new timer can be referenced.
+ *
+ * \param[out]  pp_handle        Used to pass back a handle by which the created timer
+ *                               can be referenced.
+ *
+ * \param[in]   p_timer_name     A descriptive name for the timer.
+ *
+ * \param[in]   timer_id         An identifier that is assigned to the timer being created.
+ *                               Typically this would be used in the timer callback function to
+ *                               identify which timer expired when the same callback function is
+ *                               assigned to more than one timer.
+ *
+ * \param[in]   interval_ms      The timer period in milliseconds.
+ *
+ * \param[in]   reload           Used to set the timer as a periodic or one-shot timer.
+ * \arg \c      true             Create a periodic timer.
+ * \arg \c      false            Create a one-shot timer.
+ *
+ * \param[in]   p_timer_callback The function to call when the timer expires. Callback functions
+ *                               must have the prototype defined as 'void callback(void *)'.
+ *
+ * \return           The status of the timer creation.
+ * \retval true      Timer was created successfully.
+ * \retval false     Timer was failed to create.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * // Timer callback function.
+ * void timer_callback(void *p_handle)
+ * {
+ *     uint32_t timer_id;
+ *
+ *     // Which timer expired?
+ *     os_timer_id_get(&p_handle, &timer_id);
+ *
+ *     if (timer_id == TIMER_ID)
+ *     {
+ *          // Delete the specified timer.
+ *          os_timer_delete(&p_handle);
+ *     }
+ * }
+ *
+ * #define TIMER_ID 1
+ *
+ * // Timer to be created.
+ * int test(void)
+ * {
+ *     void *p_handle = NULL;
+ *
+ *     if (os_timer_create(&p_handle, "timer", TIMER_ID,
+ *                        INTERVAL_MS, false, timer_callback) == true)
+ *     {
+ *         // Timer created successfully, start the timer.
+ *         os_timer_start(&p_handle);
+ *     }
+ *     else
+ *     {
+ *         // Timer failed to create.
+ *         return -1;
+ *     }
+ *
+ *     return 0;
+ * }
+ * \endcode
+ *
+ * \ingroup  Timer
+ */
+bool os_timer_create(void **pp_handle, const char *p_timer_name, uint32_t timer_id,
+                     uint32_t interval_ms, bool reload, void (*p_timer_callback)());
+
+/**
+ * os_timer.h
+ *
+ * \brief    Start a timer that was previously created using the os_timer_create() API
+ *           function. If the timer had already been started and was in the active state,
+ *           then os_timer_create() has equivalent functionality to the os_timer_create()
+ *           API function.
+ *
+ * \param[in] pp_handle Pointer to the created timer handle.
+ *
+ * \return           The status of the timer starting.
+ * \retval true      Timer was started successfully.
+ * \retval false     Timer was failed to start.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * // Timer callback function.
+ * void timer_callback(void *p_handle)
+ * {
+ *     uint32_t timer_id;
+ *
+ *     // Which timer expired?
+ *     os_timer_id_get(&p_handle, &timer_id);
+ *
+ *     if (timer_id == TIMER_ID)
+ *     {
+ *          // Delete the specified timer.
+ *          os_timer_delete(&p_handle);
+ *     }
+ * }
+ *
+ * #define TIMER_ID 1
+ *
+ * // Timer to be created.
+ * int test(void)
+ * {
+ *     void *p_handle = NULL;
+ *
+ *     if (os_timer_create(&p_handle, "timer", TIMER_ID,
+ *                        INTERVAL_MS, false, timer_callback) == true)
+ *     {
+ *         // Timer created successfully, start the timer.
+ *         os_timer_start(&p_handle);
+ *     }
+ *     else
+ *     {
+ *         // Timer failed to create.
+ *         return -1;
+ *     }
+ *
+ *     return 0;
+ * }
+ * \endcode
+ *
+ * \ingroup  Timer
+ */
+bool os_timer_start(void **pp_handle);
+
+/**
+ * os_timer.h
+ *
+ * \brief     Restart a timer that was previously created using the os_timer_create() API
+ *            function. If the timer had already been started and was already in the active
+ *            state, then os_timer_start() will cause the timer to re-evaluate its expiry
+ *            time so that it is relative to when os_timer_start() was called. If the timer
+ *            was in the dormant state then os_timer_start() has equivalent functionality to
+ *            the os_timer_start() API function.
+ *
+ * \param[in] pp_handle     Pointer to the created timer handle.
+ *
+ * \param[in] interval_ms   The timer period in milliseconds.
+ *
+ * \return           The status of the timer restarting.
+ * \retval true      Timer was restarted successfully.
+ * \retval false     Timer was failed to restart.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * // Timer callback function.
+ * void timer_callback(void *p_handle)
+ * {
+ *     uint32_t timer_id;
+ *
+ *     // Which timer expired?
+ *     os_timer_id_get(&p_handle, &timer_id);
+ *
+ *     if (timer_id == TIMER_ID)
+ *     {
+ *          // Restart the specified timer.
+ *          os_timer_restart(&p_handle);
+ *     }
+ * }
+ *
+ * #define TIMER_ID 1
+ *
+ * // Timer to be created.
+ * int test(void)
+ * {
+ *     void *p_handle = NULL;
+ *
+ *     if (os_timer_create(&p_handle, "timer", TIMER_ID,
+ *                        INTERVAL_MS, false, timer_callback) == true)
+ *     {
+ *         // Timer created successfully, start the timer.
+ *         os_timer_start(&p_handle);
+ *     }
+ *     else
+ *     {
+ *         // Timer failed to create.
+ *         return -1;
+ *     }
+ *
+ *     return 0;
+ * }
+ * \endcode
+ *
+ * \ingroup  Timer
+ */
+bool os_timer_restart(void **pp_handle, uint32_t interval_ms);
+
+/**
+ * os_timer.h
+ *
+ * \brief     Stop a timer that was previously started using either of the os_timer_start(),
+ *            os_timer_restart() API functions. Stopping a timer ensures the timer is not in
+ *            the active state.
+ *
+ * \param[in] pp_handle Pointer to the handle of timer being stopped.
+ *
+ * \return           The status of the timer stopping.
+ * \retval true      Timer was stopped successfully.
+ * \retval false     Timer was failed to stop.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * // Timer callback function.
+ * void timer_callback(void *p_handle)
+ * {
+ *     uint32_t timer_id;
+ *
+ *     // Which timer expired?
+ *     os_timer_id_get(&p_handle, &timer_id);
+ *
+ *     if (timer_id == TIMER_ID)
+ *     {
+ *          // Delete the specified timer.
+ *          os_timer_delete(&p_handle);
+ *     }
+ * }
+ *
+ * #define TIMER_ID 1
+ *
+ * // Timer to be created and stopped.
+ * int test(void)
+ * {
+ *     void *p_handle = NULL;
+ *
+ *     if (os_timer_create(&p_handle, "timer", TIMER_ID,
+ *                        INTERVAL_MS, false, timer_callback) == true)
+ *     {
+ *         // Timer created successfully, start the timer.
+ *         os_timer_start(&p_handle);
+ *     }
+ *     else
+ *     {
+ *         // Timer failed to create.
+ *         return -1;
+ *     }
+ *
+ *     // Stop the timer before expiration.
+ *     os_timer_stop(&p_handle);
+ *
+ *     return 0;
+ * }
+ * \endcode
+ *
+ * \ingroup  Timer
+ */
+bool os_timer_stop(void **pp_handle);
+
+/**
+ * os_timer.h
+ *
+ * \brief      Delete a timer that was previously created using the os_timer_create()
+ *             API function.
+ *
+ * \param[in] pp_handle Pointer to the handle of timer being deleted.
+ *
+ * \return           The status of the timer deletion.
+ * \retval true      Timer was deleted successfully.
+ * \retval false     Timer was failed to delete.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * // Timer callback function.
+ * void timer_callback(void *p_handle)
+ * {
+ *     uint32_t timer_id;
+ *
+ *     // Which timer expired?
+ *     os_timer_id_get(&p_handle, &timer_id);
+ *
+ *     if (timer_id == TIMER_ID)
+ *     {
+ *          // Delete the specified timer.
+ *          os_timer_delete(&p_handle);
+ *     }
+ * }
+ *
+ * #define TIMER_ID 1
+ *
+ * // Timer to be created and deleted.
+ * int test(void)
+ * {
+ *     void *p_handle = NULL;
+ *
+ *     if (os_timer_create(&p_handle, "timer", TIMER_ID,
+ *                        INTERVAL_MS, false, timer_callback) == true)
+ *     {
+ *         // Timer created successfully, start the timer.
+ *         os_timer_start(&p_handle);
+ *     }
+ *     else
+ *     {
+ *         // Timer failed to create.
+ *         return -1;
+ *     }
+ *
+ *     return 0;
+ * }
+ * \endcode
+ *
+ * \ingroup  Timer
+ */
+bool os_timer_delete(void **pp_handle);
+
+/**
+ * os_timer.h
+ *
+ * \brief      Dump all current used timers in system.
+ *
+ * \param None
+ *
+ * \return           The status of the timer dump.
+ * \retval true      Timer was dumped successfully.
+ * \retval false     Timer was failed to dump.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * // Timer callback function.
+ * void timer_callback(void *p_handle)
+ * {
+ *     uint32_t timer_id;
+ *
+ *     // Which timer expired?
+ *     os_timer_id_get(&p_handle, &timer_id);
+ *
+ *     if (timer_id == TIMER_ID)
+ *     {
+ *          // Delete the specified timer.
+ *          os_timer_delete(&p_handle);
+ *     }
+ * }
+ *
+ * #define TIMER_ID 1
+ *
+ * // Timer to be created and dumped.
+ * int test(void)
+ * {
+ *     void *p_handle = NULL;
+ *
+ *     if (os_timer_create(&p_handle, "timer", TIMER_ID,
+ *                        INTERVAL_MS, false, timer_callback) == true)
+ *     {
+ *         // Timer created successfully, start the timer.
+ *         os_timer_start(&p_handle);
+ *     }
+ *     else
+ *     {
+ *         // Timer failed to create.
+ *         return -1;
+ *     }
+ *
+ *     // Dump all used timers.
+ *     os_timer_dump();
+ *
+ *     return 0;
+ * }
+ * \endcode
+ *
+ * \ingroup  Timer
+ */
+bool os_timer_dump(void);
+
+/**
+ * os_timer.h
+ *
+ * \brief      get a timer state
+ *
+ * \param[in] pp_handle Pointer to the created timer handle.
+ * \param[out]  p_timer_state  Used to pass back the timer state.
+ * \arg \c      1             Timer is active.
+ * \arg \c      0            Timer is not active or timer is not created.
+ *
+ * \retval true      Timer state was got successfully.
+ * \retval false     Timer state was failed to get.
+ * \note A timer will be dormant if:
+ *     1) It has been created but not started, or
+ *     2) It is an expired one-shot timer that has not been restarted.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * // This function assumes the timer has already been created.
+ * void vAFunction( void *p_handle )
+ * {
+ *   uint32_t timer_state;
+ *    os_timer_state_get(&p_handle,&timer_state);
+ *     if(timer_state)
+ *     {
+ *         // Timer is active, do something.
+ *     }
+ *     else
+ *     {
+ *         //Timer is not active, do something else.
+ *     }
+ * }
+  * \endcode
+ *
+ * \ingroup  Timer
+ */
+
+typedef void (*PendedFunctionOS_t)(void *para1, uint32_t para2);
+
+bool os_timer_state_get(void **pp_handle, uint32_t *p_timer_state);
+
+/* internal function */
+void os_timer_init(void);
+
+bool os_timer_number_get(void **pp_handle, uint32_t *p_timer_num);
+bool os_timer_pend_function_call(PendedFunctionOS_t xFunctionToPend, void *para1, uint32_t para2);
+bool os_timer_get_auto_reload(void **pp_handle, long *p_autoreload);
+bool os_timer_is_timer_active(void **pp_handle);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _OS_TIMER_H_ */
diff --git a/bee/os/osif/inc/rtl87x2g/os_mem.h b/bee/os/osif/inc/rtl87x2g/os_mem.h
new file mode 100644
index 00000000..09feb9fe
--- /dev/null
+++ b/bee/os/osif/inc/rtl87x2g/os_mem.h
@@ -0,0 +1,427 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _OS_MEM_H_
+#define _OS_MEM_H_
+
+#include <stdint.h>
+#include <stddef.h>
+#include "mem_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup OS_MEM Memory Management
+ *
+ * \brief   Allocate, free, and peek memory functions.
+ * \details The Memory Management function group allows to allocate, free, and peek heap
+ *          memory in the system.\n
+ *
+ */
+
+
+extern void *(*os_mem_alloc_intern)(RAM_TYPE ram_type, size_t size,
+                                    const char *p_func, uint32_t file_line);
+
+extern void *(*os_mem_zalloc_intern)(RAM_TYPE ram_type, size_t size,
+                                     const char *p_func, uint32_t file_line);
+extern void *(*os_mem_aligned_alloc_intern)(RAM_TYPE ram_type,
+                                            size_t size, uint8_t alignment,
+                                            const char *p_func, uint32_t file_line);
+
+/*============================================================================*
+ *                              Functions
+*============================================================================*/
+/** @defgroup OS_MEM_Exported_Functions OS Memory Exported Functions
+  * \ingroup  OS_MEM
+  * @{
+  */
+
+/**
+ * os_mem.h
+ *
+ * \brief    Allocate a memory block with required size.
+ *
+ * \param   ram_type            RAM type for allocation.
+ * \arg \c  RAM_TYPE_DATA_ON        Data RAM type.
+ * \arg \c  RAM_TYPE_BUFFER_ON      BUFFER RAM type.
+ * \arg \c  RAM_TYPE_EXT_DATA_SRAM  EXT_DATA_SRAM type.
+ *
+ * \param   size     Required memory size.
+ *
+ * \return     The address of the allocated memory block. If the address is NULL, the
+ *             memory allocation failed.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * int test(void)
+ * {
+ *     size_t mem_size = 0x1000;
+ *     void *p_mem = NULL;
+ *
+ *     p_mem = os_mem_alloc(RAM_TYPE_DATA_ON, mem_size);
+ *     if (p_mem != NULL)
+ *     {
+ *         // Memory allocation successed, and free it.
+ *         os_mem_free(p_mem);
+ *     }
+ *     else
+ *     {
+ *         // Memory allocation failed.
+ *         return -1;
+ *     }
+ *
+ *     return 0;
+ * }
+ * \endcode
+ *
+ */
+#define os_mem_alloc(ram_type, size)    \
+    os_mem_alloc_intern(ram_type, size, __func__, __LINE__)
+
+/**
+ * os_mem.h
+ *
+ * \brief    Allocate a memory block with required size in DATA RAM type.
+ *
+ * \param   size     Required memory size.
+ *
+ * \return     The address of the allocated memory block. If the address is NULL, the
+ *             memory allocation failed.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * int test(void)
+ * {
+ *     size_t mem_size = 0x1000;
+ *     void *p_mem = NULL;
+ *
+ *     p_mem = os_mem_alloc2(mem_size);
+ *     if (p_mem != NULL)
+ *     {
+ *         // Memory allocation successed, and free it.
+ *         os_mem_free(p_mem);
+ *     }
+ *     else
+ *     {
+ *         // Memory allocation failed.
+ *         return -1;
+ *     }
+ *
+ *     return 0;
+ * }
+ * \endcode
+ *
+ */
+#define os_mem_alloc2(size)    \
+    os_mem_alloc_intern(RAM_TYPE_DATA_ON, size, __func__, __LINE__)
+
+/**
+ * os_mem.h
+ *
+ * \brief    Allocate and clear a memory block with required size.
+ *
+ * \param   ram_type            RAM type for allocation.
+ * \arg \c  RAM_TYPE_DATA_ON        Data RAM type.
+ * \arg \c  RAM_TYPE_BUFFER_ON      BUFFER RAM type.
+ * \arg \c  RAM_TYPE_EXT_DATA_SRAM  EXT_DATA_SRAM type.
+ *
+ * \param   size     Required memory size.
+ *
+ * \return     The address of the allocated memory block. If the address is NULL, the
+ *             memory allocation failed.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * int test(void)
+ * {
+ *     size_t mem_size = 0x1000;
+ *     void *p_mem = NULL;
+ *
+ *     p_mem = os_mem_zalloc(RAM_TYPE_DATA_ON, mem_size);
+ *     if (p_mem != NULL)
+ *     {
+ *         // Memory allocation successed, and free it.
+ *         os_mem_free(p_mem);
+ *     }
+ *     else
+ *     {
+ *         // Memory allocation failed.
+ *         return -1;
+ *     }
+ *
+ *     return 0;
+ * }
+ * \endcode
+ *
+ */
+#define os_mem_zalloc(ram_type, size)   \
+    os_mem_zalloc_intern(ram_type, size, __func__, __LINE__)
+
+/**
+ * os_mem.h
+ *
+ * \brief    Allocate and clear a memory block with required size in DATA RAM type.
+ *
+ * \param   size     Required memory size.
+ *
+ * \return     The address of the allocated memory block. If the address is NULL, the
+ *             memory allocation failed.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * int test(void)
+ * {
+ *     size_t mem_size = 0x1000;
+ *     void *p_mem = NULL;
+ *
+ *     p_mem = os_mem_zalloc2(mem_size);
+ *     if (p_mem != NULL)
+ *     {
+ *         // Memory allocation successed, and free it.
+ *         os_mem_free(p_mem);
+ *     }
+ *     else
+ *     {
+ *         // Memory allocation failed.
+ *         return -1;
+ *     }
+ *
+ *     return 0;
+ * }
+ * \endcode
+ *
+ */
+#define os_mem_zalloc2(size)   \
+    os_mem_zalloc_intern(RAM_TYPE_DATA_ON, size, __func__, __LINE__)
+
+/**
+ * os_mem.h
+ *
+ * \brief    Allocate an aligned memory block with required size.
+ *
+ * \param   ram_type            RAM type for allocation.
+ * \arg \c  RAM_TYPE_DATA_ON        Data RAM type.
+ * \arg \c  RAM_TYPE_BUFFER_ON      BUFFER RAM type.
+ * \arg \c  RAM_TYPE_EXT_DATA_SRAM  EXT_DATA_SRAM type.
+ *
+ * \param   size        Required memory size.
+ *
+ * \param   alignment   memory alignment in 2^N bytes. If alignment is 0, use
+ *                          system default memory alignment. The aligned memory block
+ *                          must use os_mem_aligned_free() API function to free.
+ *
+ * \return     The address of the allocated memory block. If the address is NULL, the
+ *             memory allocation failed.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * int test(void)
+ * {
+ *     size_t mem_size = 0x1000;
+ *     uint8_t mem_alignment = 16;
+ *     void *p_mem = NULL;
+ *
+ *     p_mem = os_mem_aligned_alloc(RAM_TYPE_DATA_ON, mem_size, mem_alignment);
+ *     if (p_mem != NULL)
+ *     {
+ *         // Aligned memory allocation successed, and free it.
+ *         os_mem_aligned_free(p_mem);
+ *     }
+ *     else
+ *     {
+ *         // Aligned memory allocation failed.
+ *         return -1;
+ *     }
+ *
+ *     return 0;
+ * }
+ * \endcode
+ *
+ */
+#define os_mem_aligned_alloc(ram_type, size, alignment) \
+    os_mem_aligned_alloc_intern(ram_type, size, alignment, __func__, __LINE__)
+
+/**
+ * os_mem.h
+ *
+ * \brief    Free a memory block that had been allocated.
+ *
+ * \param   p_block     The address of memory block being freed.
+ *
+ * \return     None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * int test(void)
+ * {
+ *     size_t mem_size = 0x1000;
+ *     void *p_mem = NULL;
+ *
+ *     p_mem = os_mem_alloc(RAM_TYPE_DATA_ON, mem_size);
+ *     if (p_mem != NULL)
+ *     {
+ *         // Memory allocation successed, and free it.
+ *         os_mem_free(p_mem);
+ *     }
+ *     else
+ *     {
+ *         // Memory allocation failed.
+ *         return -1;
+ *     }
+ *
+ *     return 0;
+ * }
+ * \endcode
+ *
+ */
+extern void (*os_mem_free)(void *p_block);
+
+/**
+ * os_mem.h
+ *
+ * \brief    Free a memory block that had been aligned allocated.
+ *
+ * \param    p_block  The address of memory block being freed.
+ *
+ * \return     The address of the allocated memory block. If the address is NULL, the
+ *             memory allocation failed.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * int test(void)
+ * {
+ *     size_t mem_size = 0x1000;
+ *     uint8_t mem_alignment = 16;
+ *     void *p_mem = NULL;
+ *
+ *     p_mem = os_mem_aligned_alloc(RAM_TYPE_DATA_ON, mem_size, mem_alignment);
+ *     if (p_mem != NULL)
+ *     {
+ *         // Aligned memory allocation successed, and free it.
+ *         os_mem_aligned_free(p_mem);
+ *     }
+ *     else
+ *     {
+ *         // Aligned memory allocation failed.
+ *         return -1;
+ *     }
+ *
+ *     return 0;
+ * }
+ * \endcode
+ *
+ */
+extern void (*os_mem_aligned_free)(void *p_block);
+
+/**
+ * os_mem.h
+ *
+ * \brief    Peek the unused memory size of the specified RAM type.
+ *
+ * \param   ram_type            RAM type for allocation.
+ * \arg \c  RAM_TYPE_DATA_ON        Data RAM type.
+ * \arg \c  RAM_TYPE_BUFFER_ON      BUFFER RAM type.
+ * \arg \c  RAM_TYPE_EXT_DATA_SRAM  EXT_DATA_SRAM type.
+ *
+ * \return     The unused memory size in btyes.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * int test(void)
+ * {
+ *     size_t unused_data_on;
+ *     size_t unused_data_off;
+ *
+ *     // Peek unused DATA ON memory size.
+ *     unused_size = os_mem_peek(RAM_TYPE_DATA_ON);
+ *
+ *     // Peek unused DATA OFF memory size.
+ *     unused_size = os_mem_peek(RAM_TYPE_DATA_OFF);
+ *
+ *     return 0;
+ * }
+ * \endcode
+ *
+ */
+extern size_t (*os_mem_peek)(RAM_TYPE ram_type);
+
+#define mem_peek()  os_mem_peek(RAM_TYPE_DATA_ON)
+
+/**
+ * os_mem.h
+ *
+ * \brief    Peek the unused max block memory size of the specified RAM type.
+ *
+ * \param   ram_type            RAM type for allocation.
+ * \arg \c  RAM_TYPE_DATA_ON        Data RAM type.
+ * \arg \c  RAM_TYPE_BUFFER_ON      BUFFER RAM type.
+ * \arg \c  RAM_TYPE_EXT_DATA_SRAM  EXT_DATA_SRAM type.
+ *
+ * \return     The unused memory size in btyes.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * int test(void)
+ * {
+ *     size_t unused_data_on;
+ *     size_t unused_data_off;
+ *
+ *     // Peek unused DATA ON memory size.
+ *     unused_size = os_mem_peek_max_block(RAM_TYPE_DATA_ON);
+ *
+ *     // Peek unused DATA OFF memory size.
+ *     unused_size = os_mem_peek_max_block(RAM_TYPE_DATA_OFF);
+ *
+ *     return 0;
+ * }
+ * \endcode
+ *
+ */
+extern size_t (*os_mem_peek_max_free_block)(RAM_TYPE ram_type);
+
+
+extern void (*os_mem_peek_printf)(void);
+/**
+ * os_mem.h
+ *
+ * \brief    Peek and print the unused memory size of all RAM type.
+ *
+ * \param   void.
+ *
+ * \return     void.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * int test(void)
+ * {
+ *     // Peek and print all unused memory size.
+ *     os_mem_dump();
+ *
+ *     return 0;
+ * }
+ * \endcode
+ *
+ */
+#define os_mem_dump()   os_mem_peek_printf()
+
+/** End of group OS_MEM_Exported_Functions
+  * @}
+  */
+
+/** End of OS_MEM
+  * @}
+  */
+
+extern void (*os_mem_check_heap_usage)(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _OS_MEM_H_ */
diff --git a/bee/os/osif/inc/rtl87x2g/os_msg.h b/bee/os/osif/inc/rtl87x2g/os_msg.h
new file mode 100644
index 00000000..a6b76345
--- /dev/null
+++ b/bee/os/osif/inc/rtl87x2g/os_msg.h
@@ -0,0 +1,445 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _OS_MSG_H_
+#define _OS_MSG_H_
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup OS_MSG Message Queue
+ *
+ * \brief   Exchange messages between tasks in a FIFO-like operation.
+ * \details The Message Queue function group allows to control, send, receive, or wait for message.
+ *          Message transmission is a basic communication model between tasks that one task sends
+ *          data explicitly, while another task receives it. The operation is more like some
+ *          kind of I/O rather than a direct access to information to be shared. The data to be
+ *          passed can be any type.\n
+ *
+ * \image html OS-message-queue-overview.jpg "Message Queue Overview" width=617px height=321px
+ *
+ */
+
+
+extern bool (*os_msg_queue_create_intern)(void **pp_handle, const char *p_name, uint32_t msg_num,
+                                          uint32_t msg_size,
+                                          const char *p_func, uint32_t file_line);
+
+extern bool (*os_msg_queue_delete_intern)(void *p_handle, const char *p_func, uint32_t file_line);
+
+extern bool (*os_msg_queue_peek_intern)(void *p_handle, uint32_t *p_msg_num,
+                                        const char *p_func, uint32_t file_line);
+
+extern bool (*os_msg_send_intern)(void *p_handle, void *p_msg, uint32_t wait_ms,
+                                  const char *p_func, uint32_t file_line);
+
+extern bool (*os_msg_recv_intern)(void *p_handle, void *p_msg, uint32_t wait_ms,
+                                  const char *p_func, uint32_t file_line);
+
+extern bool (*os_msg_peek_intern)(void *p_handle, void *p_msg, uint32_t wait_ms,
+                                  const char *p_func, uint32_t file_line);
+
+/*============================================================================*
+ *                              Functions
+*============================================================================*/
+/** @defgroup OS_MSG_Exported_Functions OS Message Exported Functions
+  * \ingroup  OS_MSG
+  * @{
+  */
+
+/**
+ * os_msg.h
+ *
+ * \brief   Creates a message queue instance. This allocates the storage required by the
+ *          new queue and passes back a handle for the queue.
+ *
+ * \param  pp_handle  Used to pass back a handle by which the message queue
+ *                         can be referenced.
+ *
+ * \param   p_name     A descriptive name for the message queue.
+ *
+ * \param   msg_num    The maximum number of items that the queue can contain.
+ *
+ * \param   msg_size   The number of bytes each item in the queue will require. Items
+ *                         are queued by copy, not by reference, so this is the number of
+ *                         bytes that will be copied for each posted item. Each item on the
+ *                         queue must be the same size.
+ *
+ * \return           The status of the message queue creation.
+ * \retval true      Message queue was created successfully.
+ * \retval false     Message queue was failed to create.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * struct test_msg
+ * {
+ *     uint8_t id;
+ *     uint8_t data[16];
+ * }
+ *
+ * #define MSG_NUM  10
+ *
+ * int test(void)
+ * {
+ *     void *p_handle = NULL;
+ *
+ *     // Create a queue capable of containing 10 items of structure test_msg.
+ *     if (os_msg_queue_create(&p_handle, "msg queue name", MSG_NUM, sizeof(struct test_msg)) == true)
+ *     {
+ *         // Message queue created successfully.
+ *     }
+ *     else
+ *     {
+ *         // Message queue failed to create.
+ *         return -1;
+ *     }
+ *
+ *     // Delete the message queue.
+ *     os_msg_queue_delete(p_handle);
+ *
+ *     return 0;
+ * }
+ * \endcode
+ *
+ */
+#define os_msg_queue_create(pp_handle, p_name, msg_num, msg_size)    \
+    os_msg_queue_create_intern(pp_handle, p_name, msg_num, msg_size, __func__, __LINE__)
+
+/**
+ * os_msg.h
+ *
+ * \brief   Delete the specified message queue, and free all the memory allocated for
+ *          storing of items placed on the queue.
+ *
+ * \param   p_handle   The handle to the message queue being deleted.
+ *
+ * \return           The status of the message queue deletion.
+ * \retval true      Message queue was deleted successfully.
+ * \retval false     Message queue was failed to delete.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * struct test_msg
+ * {
+ *     uint8_t id;
+ *     uint8_t data[16];
+ * }
+ *
+ * #define MSG_NUM  10
+ *
+ * int test(void)
+ * {
+ *     void *p_handle = NULL;
+ *
+ *     // Create a queue capable of containing 10 items of structure test_msg.
+ *     if (os_msg_queue_create(&p_handle, "msg queue name", MSG_NUM, sizeof(struct test_msg)) == true)
+ *     {
+ *         // Message queue created successfully.
+ *     }
+ *     else
+ *     {
+ *         // Message queue failed to create.
+ *         return -1;
+ *     }
+ *
+ *     // Delete the message queue.
+ *     os_msg_queue_delete(p_handle);
+ *
+ *     return 0;
+ * }
+ * \endcode
+ *
+ */
+#define os_msg_queue_delete(p_handle) \
+    os_msg_queue_delete_intern(p_handle, __func__, __LINE__)
+
+/**
+ * os_msg.h
+ *
+ * \brief    Peek the number of items sent and resided on the message queue.
+ *
+ * \param   p_handle   The handle to the message queue being peeked.
+ *
+ * \param  p_msg_num  Used to pass back the number of items residing on the message queue.
+ *
+ * \return           The status of the message queue peek.
+ * \retval true      Message queue was peeked successfully.
+ * \retval false     Message queue was failed to peek.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * struct test_msg
+ * {
+ *     uint8_t id;
+ *     uint8_t data[16];
+ * }
+ *
+ * #define MSG_NUM  10
+ *
+ * int test(void)
+ * {
+ *     void *p_handle = NULL;
+ *     uint32_t msg_num;
+ *
+ *     // Create a queue capable of containing 10 items of structure test_msg.
+ *     if (os_msg_queue_create(&p_handle, "msg queue name", MSG_NUM, sizeof(struct test_msg)) == true)
+ *     {
+ *         // Message queue created successfully.
+ *     }
+ *     else
+ *     {
+ *         // Message queue failed to create.
+ *         return -1;
+ *     }
+ *
+ *     // Peek the number of items sent on this message queue.
+ *     os_msg_queue_peek(p_handle, &msg_num);
+ *
+ *     return 0;
+ * }
+ * \endcode
+ *
+ */
+#define os_msg_queue_peek(p_handle, p_msg_num)  \
+    os_msg_queue_peek_intern(p_handle, p_msg_num, __func__, __LINE__)
+
+/**
+ * os_msg.h
+ *
+ * \brief   Send an item to the back of the specified message queue. The item is
+ *          queued by copy, not by reference.
+ *
+ * \param   p_handle The handle to the message queue on which the item is to be sent.
+ *
+ * \param   p_msg    Pointer to the item that is to be sent on the queue. The referenced
+ *                       item rather than pointer itself will be copied on the queue.
+ *
+ * \param   wait_ms  The maximum amount of time in milliseconds that the task should
+ *                       block waiting for the item to sent on the queue.
+ * \arg \c 0           No blocking and return immediately.
+ * \arg \c 0xFFFFFFFF  Block infinitely until the item sent.
+ * \arg \c others      The timeout value in milliseconds.
+ *
+ * \return           The status of the message item sent.
+ * \retval true      Message item was sent successfully.
+ * \retval false     Message item was failed to send.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * struct test_msg
+ * {
+ *     uint8_t id;
+ *     uint8_t data[16];
+ * }
+ *
+ * #define MSG_NUM  10
+ *
+ * int test(void)
+ * {
+ *     void *p_handle = NULL;
+ *     struct test_msg msg;
+ *
+ *     // Create a queue capable of containing 10 items of structure test_msg.
+ *     if (os_msg_queue_create(&p_handle, "msg queue name", MSG_NUM, sizeof(struct test_msg)) == true)
+ *     {
+ *         // Message queue created successfully.
+ *     }
+ *     else
+ *     {
+ *         // Message queue failed to create.
+ *         return -1;
+ *     }
+ *
+ *     // Send the item to this message queue.
+ *     msg.id = 1;
+ *     msg.data[0] = 0;
+ *     os_msg_send(p_handle, &msg, 0);
+ *
+ *     return 0;
+ * }
+ * \endcode
+ *
+ */
+#define os_msg_send(p_handle, p_msg, wait_ms) \
+    os_msg_send_intern(p_handle, p_msg, wait_ms, __func__, __LINE__)
+
+/**
+ * os_msg.h
+ *
+ * \brief   Receive an item from the specified message queue. The item is received by
+ *          copy rather than by reference, so a buffer of adequate size must be provided.
+ *
+ * \param   p_handle The handle to the message queue from which the item is to be received.
+ *
+ * \param  p_msg    Pointer to the buffer into which the received item will be copied.
+ *                       item rather than pointer itself will be copied on the queue.
+ *
+ * \param   wait_ms  The maximum amount of time in milliseconds that the task should
+ *                       block waiting for an item to be received from the queue.
+ * \arg \c 0           No blocking and return immediately.
+ * \arg \c 0xFFFFFFFF  Block infinitely until the item received.
+ * \arg \c others      The timeout value in milliseconds.
+ *
+ * \return           The status of the message item received.
+ * \retval true      Message item was received successfully.
+ * \retval false     Message item was failed to receive.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * struct test_msg
+ * {
+ *     uint8_t id;
+ *     uint8_t data[16];
+ * }
+ *
+ * #define MSG_NUM  10
+ *
+ * void *p_handle = NULL;
+ *
+ * void send_msg(void)
+ * {
+ *     struct test_msg msg;
+ *
+ *     // Create a queue capable of containing 10 items of structure test_msg.
+ *     if (os_msg_queue_create(&p_handle, "msg queue name", MSG_NUM, sizeof(struct test_msg)) == true)
+ *     {
+ *         // Message queue created successfully.
+ *     }
+ *     else
+ *     {
+ *         // Message queue failed to create.
+ *         return -1;
+ *     }
+ *
+ *     // Send the item to this message queue.
+ *     msg.id = 1;
+ *     msg.data[0] = 0;
+ *     os_msg_send(p_handle, &msg, 0);
+ *
+ *     return 0;
+ * }
+ *
+ * void receive_msg(void)
+ * {
+ *     struct test_msg msg;
+ *
+ *     // Receive the message queue item.
+ *     if (os_msg_recv(p_handle, &msg, 0) == true)
+ *     {
+ *         // Message item received successfully.
+ *     }
+ *     else
+ *     {
+ *         // Message item failed to receive.
+ *         return -1;
+ *     }
+ *
+ *     return 0;
+ * }
+ * \endcode
+ *
+ */
+#define os_msg_recv(p_handle, p_msg, wait_ms) \
+    os_msg_recv_intern(p_handle, p_msg, wait_ms, __func__, __LINE__)
+
+/**
+ * os_msg.h
+ *
+ * \brief   Receive but not remove an item from the specified message queue. The item is
+ *          received by copy rather than by reference, so a buffer of adequate size must
+ *          be provided.
+ *
+ * \param  p_handle The handle to the message queue on which the item is to be peeked.
+ *
+ * \param  p_msg    Pointer to the buffer into which the received item will be copied.
+ *                       item rather than pointer itself will be copied on the queue.
+ *
+ * \param   wait_ms  The maximum amount of time in milliseconds that the task should
+ *                       block waiting for an item to be received from the queue.
+ * \arg \c 0           No blocking and return immediately.
+ * \arg \c 0xFFFFFFFF  Block infinitely until the item received.
+ * \arg \c others      The timeout value in milliseconds.
+ *
+ * \return           The status of the message item received.
+ * \retval true      Message item was received successfully.
+ * \retval false     Message item was failed to receive.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * struct test_msg
+ * {
+ *     uint8_t id;
+ *     uint8_t data[16];
+ * }
+ *
+ * #define MSG_NUM  10
+ *
+ * void *p_handle = NULL;
+ *
+ * void send_msg(void)
+ * {
+ *     struct test_msg msg;
+ *
+ *     // Create a queue capable of containing 10 items of structure test_msg.
+ *     if (os_msg_queue_create(&p_handle, "msg queue name", MSG_NUM, sizeof(struct test_msg)) == true)
+ *     {
+ *         // Message queue created successfully.
+ *     }
+ *     else
+ *     {
+ *         // Message queue failed to create.
+ *         return -1;
+ *     }
+ *
+ *     // Send the item to this message queue.
+ *     msg.id = 1;
+ *     msg.data[0] = 0;
+ *     os_msg_send(p_handle, &msg, 0);
+ *
+ *     return 0;
+ * }
+ *
+ * void peek_msg(void)
+ * {
+ *     struct test_msg msg;
+ *
+ *     // Peek the message queue item.
+ *     if (os_msg_peek(p_handle, &msg, 0) == true)
+ *     {
+ *         // Message item peeked successfully.
+ *     }
+ *     else
+ *     {
+ *         // Message item failed to peek.
+ *         return -1;
+ *     }
+ *
+ *     return 0;
+ * }
+ * \endcode
+ *
+ */
+#define os_msg_peek(p_handle, p_msg, wait_ms) \
+    os_msg_peek_intern(p_handle, p_msg, wait_ms, __func__, __LINE__)
+
+/** End of group OS_MSG_Exported_Functions
+  * @}
+  */
+
+/** End of OS_MSG
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _OS_MSG_H_ */
diff --git a/bee/os/osif/inc/rtl87x2g/os_queue.h b/bee/os/osif/inc/rtl87x2g/os_queue.h
new file mode 100644
index 00000000..261ec821
--- /dev/null
+++ b/bee/os/osif/inc/rtl87x2g/os_queue.h
@@ -0,0 +1,390 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _OS_QUEUE_H_
+#define _OS_QUEUE_H_
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup OS_QUEUE List Queue
+ *
+ * \brief   Initialize and manage List Queue functions.
+ * \details List Queue is designed as a FIFO-like list, which can enqueue, dequeue and peek
+ *          the list. While, List Queue also keeps these functionalities such as deleting
+ *          and inserting the speicified list item.\n
+ *
+ * \image html OS-queue-overview.jpg "List Queue Overview" width=466px height=256px
+ *
+ */
+
+/*============================================================================*
+ *                         Types
+ *============================================================================*/
+/** @defgroup OS_QUEUE_Exported_Types OS Queue Exported Types
+  * \ingroup  OS_QUEUE
+  * @brief
+  * @{
+  */
+
+/**
+ * os_queue.h
+ *
+ * \brief   The element structure of List Queue.
+ *
+ */
+typedef struct t_os_queue_elem
+{
+    struct t_os_queue_elem *p_next; /**< Pointer to next list queue element. */
+} T_OS_QUEUE_ELEM;
+
+/**
+ * os_queue.h
+ *
+ * \brief   The header structure of List Queue.
+ *
+ */
+typedef struct
+{
+    T_OS_QUEUE_ELEM *p_first;   /**< Pointer to the first queue element. */
+    T_OS_QUEUE_ELEM *p_last;    /**< Pointer to the last queue element. */
+    uint16_t         count;     /**< The queue element count. */
+    uint16_t         flags;     /**< The flags for customer usage. */
+} T_OS_QUEUE;
+
+/** End of group WDG_Exported_Types
+  * @}
+  */
+
+/*============================================================================*
+ *                              Functions
+*============================================================================*/
+/** @defgroup OS_QUEUE_Exported_Functions OS Queue Exported Functions
+  * \ingroup  OS_QUEUE
+  * @{
+  */
+
+/**
+ * os_queue.h
+ *
+ * \brief   Initialize the list queue.
+ *
+ * \param   p_queue  Pointer to the list queue header.
+ *
+ * \return      None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * T_OS_QUEUE  test_queue;
+ *
+ * int test(void)
+ * {
+ *     // Initialize the queue before operating it.
+ *     os_queue_init(&test_queue);
+ * }
+ * \endcode
+ *
+ */
+extern void (*os_queue_init)(T_OS_QUEUE *p_queue);
+
+/**
+ * os_queue.h
+ *
+ * \brief   Enqueue an element to the back of the list queue.
+ *
+ * \param   p_queue Pointer to the list queue header.
+ *
+ * \param   p_elem  The list queue element being enqueued.
+ *
+ * \return      None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * struct test_item
+ * {
+ *     struct test_item *p_next; // Pointer to the next item, must be the first field.
+ *     uint32_t          id;
+ *     uint8_t           data[10];
+ * }
+ *
+ * T_OS_QUEUE  test_queue;
+ *
+ * struct test_item a_item;
+ *
+ * int test(void)
+ * {
+ *     // Initialize the queue before operating it.
+ *     os_queue_init(&test_queue);
+ *
+ *     // Enqueue the item.
+ *     os_queue_in(&test_queue, &a_item);
+ * }
+ * \endcode
+ *
+ */
+extern void (*os_queue_in)(T_OS_QUEUE *p_queue, void *p_elem);
+
+/**
+ * os_queue.h
+ *
+ * \brief   Dequeue an element from the front of the list queue.
+ *
+ * \param   p_queue  Pointer to the list queue header.
+ *
+ * \return  The first element from the list queue. If the returned address is
+ *          NULL, the list queue is empty.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * struct test_item
+ * {
+ *     struct test_item *p_next; // Pointer to the next item, must be the first field.
+ *     uint32_t          id;
+ *     uint8_t           data[10];
+ * }
+ *
+ * T_OS_QUEUE  test_queue;
+ *
+ * struct test_item a_item;
+ *
+ * int test(void)
+ * {
+ *     struct test_item *p_item;
+ *
+ *     // Initialize the queue before operating it.
+ *     os_queue_init(&test_queue);
+ *
+ *     // Enqueue the item.
+ *     os_queue_in(&test_queue, &a_item);
+ *
+ *     // Then dequeue the item from the list queue.
+ *     p_item = os_queue_out(&test_queue);
+ * }
+ * \endcode
+ *
+ */
+extern void *(*os_queue_out)(T_OS_QUEUE *p_queue);
+
+/**
+ * os_queue.h
+ *
+ * \brief  Peek an element from the list queue.
+ *
+ * \param   p_queue Pointer to the list queue header.
+ *
+ * \param   index   The index of the peeked element.
+ *                      When index is a zero or positive number, it refers to the (index+1)th element.
+ *                      When index is a negative number, it refers to |index|th last element.
+ *
+ * \return  The peeked element from the list queue. If the returned address is
+ *          NULL, the list queue is empty or the index is invalid.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * struct test_item
+ * {
+ *     struct test_item *p_next; // Pointer to the next item, must be the first field.
+ *     uint32_t          id;
+ *     uint8_t           data[10];
+ * }
+ *
+ * T_OS_QUEUE  test_queue;
+ *
+ * struct test_item a_item;
+ *
+ * int test(void)
+ * {
+ *     struct test_item *p_item;
+ *
+ *     // Initialize the queue before operating it.
+ *     os_queue_init(&test_queue);
+ *
+ *     // Enqueue the item.
+ *     os_queue_in(&test_queue, &a_item);
+ *
+ *     // Peek but not remove the first item from the list queue.
+ *     p_item = os_queue_peek(&test_queue, 0);
+ * }
+ * \endcode
+ *
+ */
+extern void *(*os_queue_peek)(T_OS_QUEUE *p_queue, int32_t index);
+
+/**
+ * os_queue.h
+ *
+ * \brief   Search an element from the list queue.
+ *
+ * \param   p_queue     Pointer to the list queue header.
+ *
+ * \param   p_elem      The element to be searched.
+ *
+ * \return          The status of queue element searching.
+ * \retval true     Queue element was found successfully.
+ * \retval false    Queue element was failed to find when the queue is empty
+ *                  or the queue element is not in the queue.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * struct test_item
+ * {
+ *     struct test_item *p_next; // Pointer to the next item, must be the first field.
+ *     uint32_t          id;
+ *     uint8_t           data[10];
+ * }
+ *
+ * T_OS_QUEUE  test_queue;
+ *
+ * struct test_item item1;
+ * struct test_item item2;
+ * struct test_item item3;
+ *
+ * int test(void)
+ * {
+ *     struct test_item *p_item;
+ *
+ *     // Initialize the queue before operating it.
+ *     os_queue_init(&test_queue);
+ *
+ *     // Enqueue the item 1.
+ *     os_queue_in(&test_queue, &item1);
+ *
+ *     // Enqueue the item 2.
+ *     os_queue_in(&test_queue, &item2);
+ *
+ *     // Enqueue the item 3.
+ *     os_queue_in(&test_queue, &item3);
+ *
+ *     // Search the item 2.
+ *     os_queue_search(&test_queue, &item2);
+ * }
+ * \endcode
+ *
+ */
+extern bool (*os_queue_search)(T_OS_QUEUE *p_queue, void *p_elem);
+
+/**
+ * os_queue.h
+ *
+ * \brief   Insert an element to the list queue.
+ *
+ * \param   p_queue     Pointer to the list queue header.
+ *
+ * \param   p_elem      The element which the new element to be inserted behind.
+ *
+ * \param   p_new_elem  The inserted element.
+ *
+ * \return      None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * struct test_item
+ * {
+ *     struct test_item *p_next; // Pointer to the next item, must be the first field.
+ *     uint32_t          id;
+ *     uint8_t           data[10];
+ * }
+ *
+ * T_OS_QUEUE  test_queue;
+ *
+ * struct test_item item1;
+ * struct test_item item2;
+ * struct test_item item3;
+ *
+ * int test(void)
+ * {
+ *     struct test_item *p_item;
+ *
+ *     // Initialize the queue before operating it.
+ *     os_queue_init(&test_queue);
+ *
+ *     // Enqueue the item 1.
+ *     os_queue_in(&test_queue, &item1);
+ *
+ *     // Enqueue the item 2.
+ *     os_queue_in(&test_queue, &item2);
+ *
+ *     // Insert the item 3 behind item 1 but before item 2.
+ *     os_queue_insert(&test_queue, &item1, &item3);
+ * }
+ * \endcode
+ *
+ */
+extern void (*os_queue_insert)(T_OS_QUEUE *p_queue, void *p_elem, void *p_new_elem);
+
+/**
+ * os_queue.h
+ *
+ * \brief   Delete an element from the list queue.
+ *
+ * \param   p_queue  Pointer to the list queue header.
+ *
+ * \param   p_elem   The element to be deleted from the list queue.
+ *
+ * \return          The status of queue element deletion.
+ * \retval true     Queue element was deleted successfully.
+ * \retval false    Queue element was failed to delete when the queue is empty
+ *                  or the being deleted queue element is not belonged to the queue.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * struct test_item
+ * {
+ *     struct test_item *p_next; // Pointer to the next item, must be the first field.
+ *     uint32_t          id;
+ *     uint8_t           data[10];
+ * }
+ *
+ * T_OS_QUEUE  test_queue;
+ *
+ * struct test_item item1;
+ * struct test_item item2;
+ * struct test_item item3;
+ *
+ * int test(void)
+ * {
+ *     struct test_item *p_item;
+ *
+ *     // Initialize the queue before operating it.
+ *     os_queue_init(&test_queue);
+ *
+ *     // Enqueue the item 1.
+ *     os_queue_in(&test_queue, &item1);
+ *
+ *     // Enqueue the item 2.
+ *     os_queue_in(&test_queue, &item2);
+ *
+ *     // Enqueue the item 3.
+ *     os_queue_in(&test_queue, &item3);
+ *
+ *     // Then delete the item 2.
+ *     os_queue_delete(&test_queue, &item12);
+ * }
+ * \endcode
+ *
+ */
+extern bool (*os_queue_delete)(T_OS_QUEUE *p_queue, void *p_elem);
+
+/** End of group OS_QUEUE_Exported_Functions
+  * @}
+  */
+
+extern void os_queue_func_init(void);
+
+/** End of OS_QUEUE
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* _OS_QUEUE_H_ */
diff --git a/bee/os/osif/inc/rtl87x2g/os_sched.h b/bee/os/osif/inc/rtl87x2g/os_sched.h
new file mode 100644
index 00000000..0e853ce1
--- /dev/null
+++ b/bee/os/osif/inc/rtl87x2g/os_sched.h
@@ -0,0 +1,323 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _OS_SCHED_H_
+#define _OS_SCHED_H_
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/**
+ * \defgroup    OS_SCHED Kernel Scheduler
+ *
+ * \brief       Manage the kernel scheduler functions.
+ *
+ */
+
+/*============================================================================*
+ *                              Functions
+*============================================================================*/
+/** @defgroup OS_SCHED_Exported_Functions OS Scheduler Exported Functions
+  * \ingroup  OS_SCHED
+  * @{
+  */
+
+
+/**
+ * os_sched.h
+ *
+ * \brief       Delay current task for a given period in milliseconds.
+ *
+ * \param       ms  The amout of timer in milliseconds that the current task
+ *                  should block.
+ *
+ * \return      None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * // Task routine implementation.
+ * void task_routine(void *p_param)
+ * {
+ *     for (;;)
+ *     {
+ *          // Task code goes here.
+ *          os_delay(100);
+ *
+ *          // Do something here per 100ms.
+ *     }
+ * }
+ * \endcode
+ *
+ */
+extern void (*os_delay)(uint32_t ms);
+
+/**
+ * os_sched.h
+ *
+ * \brief   Get the time in milliseconds since os_sched_start() API function was called.
+ *
+ * \param   None
+ *
+ * \return  The time in milliseconds. Note the time represented by a 64-bit integer
+ *          may be overflowed.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * // Task routine implementation.
+ * void task_routine(void *p_param)
+ * {
+ *     uint64_t last_time;
+ *
+ *     // Get the last timestamp.
+ *     last_time = os_sys_time_get();
+ *
+ *     for (;;)
+ *     {
+ *          // Wait for the next cycle.
+ *          os_delay(100);
+ *
+ *          // Do something here per 100ms.
+ *     }
+ * }
+ * \endcode
+ *
+ */
+extern uint64_t (*os_sys_time_get)(void);
+
+/**
+ * os_sched.h
+ *
+ * \brief   Get the time in milliseconds since os_sched_start() API function was called.
+ *
+ * \param   None
+ *
+ * \return  The time in os tick. Note the time represented by a 64-bit integer
+ *          may be overflowed.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * // Task routine implementation.
+ * void task_routine(void *p_param)
+ * {
+ *     uint64_t last_tick;
+ *
+ *     // Get the last timestamp.
+ *     last_tick = os_sys_tick_get();
+ *
+ *     for (;;)
+ *     {
+ *          // Wait for the next cycle.
+ *          os_delay(100);
+ *
+ *          // Do something here per 100ms.
+ *     }
+ * }
+ * \endcode
+ *
+ */
+extern uint64_t (*os_sys_tick_get)(void);
+
+/**
+ * os_sched.h
+ *
+ * \brief   Start the RTOS kernel scheduler.
+ *
+ * \param   None
+ *
+ * \return  The status of starting kernel scheduler.
+ * \retval  true      Scheduler was started successfully.
+ * \retval  false     Scheduler was failed to start.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * int test(void)
+ * {
+ *     // Create at least one task before starting kernel scheduler.
+ *     if (os_task_create(&p_handle, "task", task_routine,
+ *                        NULL, STACK_SIZE, TASK_PRIORITY) == true)
+ *     {
+ *         // Task created successfully.
+ *     }
+ *     else
+ *     {
+ *         // Task failed to create.
+ *         return -1;
+ *     }
+ *
+ *     // Start the kernel scheduler.
+ *     os_sched_start();
+ *
+ *     // Will not get here unless a task calls os_sched_stop().
+ * }
+ * \endcode
+ *
+ */
+extern bool (*os_sched_start)(void);
+
+/**
+ * os_sched.h
+ *
+ * \brief   Stop the RTOS kernel scheduler. All created tasks will be automatically
+ *          deleted and multitasking (either preemptive or cooperative) stops.
+ *
+ * \param   None
+ *
+ * \return  The status of stopping kernel scheduler.
+ * \retval  true      Scheduler was stopped successfully.
+ * \retval  false     Scheduler was failed to stop.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * // Task routine implementation.
+ * void task_routine(void *p_param)
+ * {
+ *     for (;;)
+ *     {
+ *          // Task code goes here.
+ *
+ *          // At some point we want to end the real time kernel processing.
+ *          os_sched_stop();
+ *     }
+ * }
+ *
+ * int test(void)
+ * {
+ *     // Create at least one task before starting kernel scheduler.
+ *     if (os_task_create(&p_handle, "task", task_routine,
+ *                        NULL, STACK_SIZE, TASK_PRIORITY) == true)
+ *     {
+ *         // Task created successfully.
+ *     }
+ *     else
+ *     {
+ *         // Task failed to create.
+ *         return -1;
+ *     }
+ *
+ *     // Start the kernel scheduler.
+ *     os_sched_start();
+ *
+ *     // Will not get here unless a task calls os_sched_stop().
+ * }
+ * \endcode
+ *
+ * \ingroup  Schedule
+ */
+extern bool (*os_sched_stop)(void);
+
+/**
+ * os_sched.h
+ *
+ * \brief   Suspends the kernel scheduler without disabling interrupts. Context
+ *          switches will not occur while the scheduler is suspended. After calling
+ *          os_sched_suspend(), the calling task will continue to execute without
+ *          risk of being swapped out until a call to os_sched_resume() has been made.
+ *
+ * \param   None
+ *
+ * \return  The status of suspending kernel scheduler.
+ * \retval  true      Scheduler was suspended successfully.
+ * \retval  false     Scheduler was failed to suspend.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * // Task routine implementation.
+ * void task_routine(void *p_param)
+ * {
+ *     for (;;)
+ *     {
+ *          // Task code goes here.
+ *
+ *          // At some point the task wants to perform a long operation, and do not
+ *          // want to get swapped out.
+ *          os_sched_suspend();
+ *
+ *          // The long operation.
+ *
+ *          // The operation is completed, and resume the scheduler.
+ *          os_sched_resume();
+ *     }
+ * }
+ * \endcode
+ *
+ */
+extern bool (*os_sched_suspend)(void);
+
+/**
+ * os_sched.h
+ *
+ * \brief   Resume the kernel scheduler after it was suspended by a call
+ *          to os_sched_suspend().
+ *
+ * \param   None
+ *
+ * \return  The status of resuming kernel scheduler.
+ * \retval  true      Scheduler was resumed successfully.
+ * \retval  false     Scheduler was failed to resume.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * // Task routine implementation.
+ * void task_routine(void *p_param)
+ * {
+ *     for (;;)
+ *     {
+ *          // Task code goes here.
+ *
+ *          // At some point the task wants to perform a long operation, and do not
+ *          // want to get swapped out.
+ *          os_sched_suspend();
+ *
+ *          // The long operation.
+ *
+ *          // The operation is completed, and resume the scheduler.
+ *          os_sched_resume();
+ *     }
+ * }
+ * \endcode
+ *
+ */
+extern bool (*os_sched_resume)(void);
+
+/**
+  * @brief  Check if os scheduler has already been started
+  * @param  None
+  * @return The status of os scheduler.
+  * \retval  true      Scheduler has already been started.
+  * \retval  false     Scheduler has not already been started.
+  */
+extern bool (*os_sched_is_start)(void);
+
+/**
+  * @brief  Get state of os scheduler
+  * @param  p_state current state of os scheduler, 0: suspended; 1: not started; 2: running
+  * @return The result of os scheduler state get.
+  * \retval  true      Scheduler state get sucess.
+  * \retval  false     Scheduler state get fail.
+  */
+extern bool (*os_sched_state_get)(long *p_state);
+
+/** End of group OS_SCHED_Exported_Functions
+  * @}
+  */
+
+/** End of OS_SCHED
+  * @}
+  */
+
+extern void (*os_vector_table_update)(void);
+extern void (*os_init)(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _OS_SCHED_H_ */
diff --git a/bee/os/osif/inc/rtl87x2g/os_sync.h b/bee/os/osif/inc/rtl87x2g/os_sync.h
new file mode 100644
index 00000000..13f00613
--- /dev/null
+++ b/bee/os/osif/inc/rtl87x2g/os_sync.h
@@ -0,0 +1,483 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _OS_SYNC_H_
+#define _OS_SYNC_H_
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup    OS_SYNC Inter-Task Communication
+ *
+ * \brief   Manage Inter-task communication functions.
+ * \details Tasks need to communicate with each other or access shared resources together.
+ *          There are many ways to exchange data between tasks, for example using shared
+ *          data, polling loops and message passing.\n
+ *          Many resources can be considered as serially-reusable. This means that they
+ *          can be used repeatedly by different tasks, but only by one task at a time.\n
+ *          The following mechanisms are available to the user:\n
+ * \arg <b>Lock</b>
+ * \arg <b>Semaphore</b>
+ * \arg <b>Mutex</b>
+ *
+ */
+
+/*============================================================================*
+ *                              Functions
+*============================================================================*/
+/** @defgroup OS_SYNC_Exported_Functions OS Synchronization Exported Functions
+  * \ingroup  OS_SYNC
+  * @{
+  */
+
+/**
+ * os_sync.h
+ *
+ * \brief   Enter the critical region. Disable preemptive context switch and interrupts.
+ *
+ * \param   None
+ *
+ * \return      Interrupt mask flag.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * int test(void)
+ * {
+ *     uint32_t s;
+ *
+ *     // Enter the critical section.
+ *     s = os_lock();
+ *     // Allow only one task or ISR to operate the list.
+ *     list_add(p_list, &item);
+ *     // Exit the critical section and restore ISR mask flag.
+ *     os_unlock(s);
+ * }
+ * \endcode
+ *
+ */
+extern uint32_t (*os_lock)(void);
+
+/**
+ * os_sync.h
+ *
+ * \brief   Exit the critical region. Enable preemptive context switch and interrupts.
+ *
+ * \param   s   Interrupt mask flag to be restored.
+ *
+ * \return      None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * int test(void)
+ * {
+ *     uint32_t s;
+ *
+ *     // Enter the critical section.
+ *     s = os_lock();
+ *     // Allow only one task or ISR to operate the list.
+ *     list_add(p_list, &item);
+ *     // Exit the critical section and restore ISR mask flag.
+ *     os_unlock(s);
+ * }
+ * \endcode
+ *
+ */
+extern void (*os_unlock)(uint32_t s);
+
+/**
+ * os_sync.h
+ *
+ * \brief   Create a counting semaphore.
+ *
+ * \details Semaphores are used to manage and protect access to shared resources. A semaphore
+ *          can be used to permit a fixed number of task to access a pool of shared resources.
+ *          Using semaphores.\n
+ *          A semaphore object should be initialized to the maximum number of available tokens.
+ *          This number of available resources is specified as parameter of the os_sem_create()
+ *          function. Each time a semaphore token is obtained with os_sem_take(), the semaphore
+ *          count is decremented. When the semaphore count is 0, no semaphore token can be obtained.
+ *          The task that tries to obtain the semaphore token needs to wait until the next token
+ *          is free. Semaphores are released with os_sem_give() incrementing the semaphore count.
+ *
+ * \image html OS-semaphore-overview.jpg "Semaphore Overview" width=496px height=346px
+ *
+ * \param  pp_handle   Used to pass back the created semaphore handle.
+ *
+ * \param  p_name  A descriptive name for the semaphore.
+ *
+ * \param   init_count  The count value assigned to the semaphore when created.
+ *
+ * \param   max_count   The maximum count value that can be reached. If the max_count is 1,
+ *                          a binary semaphore is being created.
+ *
+ * \return           The status of the semaphore creation.
+ * \retval true      Semaphore was created successfully.
+ * \retval false     Semaphore was failed to create.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * int test(void)
+ * {
+ *     void *p_handle;
+ *
+ *     // Create a semaphore with initial value 0 and maximum value 10.
+ *     if (os_sem_create(&p_handle, "sem name", 0, 10) == true)
+ *     {
+ *         // Semaphore created successfully.
+ *     }
+ *     else
+ *     {
+ *         // Semaphore failed to create.
+ *         return -1;
+ *     }
+ *
+ *     return 0;
+ * }
+ * \endcode
+ *
+ */
+extern bool (*os_sem_create)(void **pp_handle, const char *p_name, uint32_t init_count,
+                             uint32_t max_count);
+
+/**
+ * os_sync.h
+ *
+ * \brief   Delete a semaphore.
+ *
+ * \param   p_handle    The handle of the semaphore to be deleted.
+ *
+ * \return           The status of the semaphore deletion.
+ * \retval true      Semaphore was deleted successfully.
+ * \retval false     Semaphore was failed to delete.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * int test(void)
+ * {
+ *     void *p_handle;
+ *
+ *     // Create a semaphore with initial value 0 and maximum value 10.
+ *     if (os_sem_create(&p_handle, "sem name", 0, 10) == true)
+ *     {
+ *         // Semaphore created successfully.
+ *     }
+ *     else
+ *     {
+ *         // Semaphore failed to create.
+ *         return -1;
+ *     }
+ *
+ *     // Delete the created semaphore.
+ *     os_sem_delete(p_handle);
+ *
+ *     return 0;
+ * }
+ * \endcode
+ *
+ */
+extern bool (*os_sem_delete)(void *p_handle);
+
+/**
+ * os_sync.h
+ *
+ * \brief   Take a semaphore.
+ *
+ * \param   p_handle    The handle of the semaphore to be taken.
+ *
+ * \param   wait_ms     The time in milliseconds to wait for the semaphore to become
+ *                          available.
+ * \arg \c 0           No blocking and return immediately.
+ * \arg \c 0xFFFFFFFF  Block infinitely until the semaphore taken.
+ * \arg \c others      The timeout value in milliseconds.
+ *
+ * \return           The status of the semaphore taking.
+ * \retval true      Semaphore was taken successfully.
+ * \retval false     Semaphore was failed to take.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * void *p_handle = NULL;
+ *
+ * // One task creates a semaphore.
+ * void task1(void *p_param)
+ * {
+ *     // Create a full binary semaphore.
+ *     os_sem_create(&p_handle, "sem name", 1, 1);
+ * }
+ *
+ * // Anohter task uses the semaphore.
+ * void task2(void *p_param)
+ * {
+ *     // See if we can obtain the semaphore. If the semaphore is
+ *     // not available, wait for 100ms.
+ *     if (os_sem_take(p_handle, 100) == true)
+ *     {
+ *         // Access the share resource.
+ *
+ *         // Finish accessing the share resource, then release the semaphore.
+ *         os_sem_give(p_handle);
+ *     }
+ *     else
+ *     {
+ *         // Could not access the share resource.
+ *     }
+ * }
+ * \endcode
+ *
+ */
+extern bool (*os_sem_take)(void *p_handle, uint32_t wait_ms);
+
+/**
+ * os_sync.h
+ *
+ * \brief   Give a semaphore.
+ *
+ * \param   p_handle    The handle of the semaphore to be given.
+ *
+ * \return           The status of the semaphore giving.
+ * \retval true      Semaphore was given successfully.
+ * \retval false     Semaphore was failed to give.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * int test(void)
+ * {
+ *     void *p_handle = NULL;
+ *
+ *     // Create an empty binary semaphore.
+ *     os_sem_create(&p_handle, "sem name", 0, 1);
+ *
+ *     // Obtaining the empty semaphore immediately will be failed.
+ *     if (os_sem_take(p_handle, 0) == false)
+ *     {
+ *         // Failed.
+ *     }
+ *
+ *     // Give the sempahore
+ *     if (os_sem_give(p_hanel) == true)
+ *     {
+ *         // Now we can take the semaphore.
+ *         os_sem_take(p_handle, 0);
+ *
+ *         // Again taking the binary semaphore will be failed.
+ *         os_sem_take(p_handle, 0);
+ *     }
+ * }
+ * \endcode
+ *
+ */
+extern bool (*os_sem_give)(void *p_handle);
+
+/**
+ * os_sync.h
+ *
+ * \brief   Create a mutex.
+ *
+ * \details Mutex (Mutual Exclusion) is used to protect a shared resource that can be accessed
+ *          only by one task at a time.\n
+ *          A mutex is a special version of a binary empty semaphore. The advantage of a mutex
+ *          is that it introduces task ownership. When a task acquires a mutex and becomes its
+ *          owner, subsequent mutex acquires from that task will succeed immediately. Thus, mutex
+ *          acquires/releases can be nested.\n
+ *
+ * \image html OS-mutex-overview.jpg "Mutex Overview" width=451px height=196px
+ *
+ * \param  pp_handle   Used to pass back the created mutex handle.
+ *
+ * \return           The status of the mutex creation.
+ * \retval true      Mutex was created successfully.
+ * \retval false     Mutex was failed to create.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * int test(void)
+ * {
+ *     void *p_handle = NULL;
+ *
+ *     // Create a mutex.
+ *     if (os_mutex_create(&p_handle) == true)
+ *     {
+ *         // The mutex created successfully.
+ *         // Now it can be used.
+ *     }
+ * }
+ * \endcode
+ *
+ */
+extern bool (*os_mutex_create)(void **pp_handle);
+
+/**
+ * os_sync.h
+ *
+ * \brief   Delete a mutex.
+ *
+ * \param   p_handle    The handle of the mutex to be deleted.
+ *
+ * \return           The status of the Mutex deletion.
+ * \retval true      Mutex was deleted successfully.
+ * \retval false     Mutex was failed to delete.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * int test(void)
+ * {
+ *     void *p_handle;
+ *
+ *     // Create a mutex.
+ *     if (os_mutex_create(&p_handle) == true)
+ *     {
+ *         // Mutex created successfully.
+ *     }
+ *     else
+ *     {
+ *         // Mutex failed to create.
+ *         return -1;
+ *     }
+ *
+ *     // Delete the created mutex.
+ *     os_mutex_delete(p_handle);
+ *
+ *     return 0;
+ * }
+ * \endcode
+ *
+ */
+extern bool (*os_mutex_delete)(void *p_handle);
+
+/**
+ * os_sync.h
+ *
+ * \brief   Take a mutex.
+ *
+ * \param   p_handle    The handle of the mutex to be taken.
+ *
+ * \param   wait_ms     The time in milliseconds to wait for the mutex to become
+ *                          available.
+ * \arg \c 0           No blocking and return immediately.
+ * \arg \c 0xFFFFFFFF  Block infinitely until the mutex taken.
+ * \arg \c others      The timeout value in milliseconds.
+ *
+ * \return           The status of the mutex taking.
+ * \retval true      Mutex was taken successfully.
+ * \retval false     Mutex was failed to take.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * void *p_handle = NULL;
+ *
+ * // One task creates a mutex.
+ * void task1(void *p_param)
+ * {
+ *     // Create a mutex.
+ *     os_mutex_create(&p_handle);
+ * }
+ *
+ * // Anohter task uses the mutex.
+ * void task2(void *p_param)
+ * {
+ *     // See if we can obtain the mutex. If the mutex is
+ *     // not available, wait for 100ms.
+ *     if (os_mutex_take(p_handle, 100) == true)
+ *     {
+ *         // Access the share resource.
+ *
+ *         // In real code, recursive calls of mutex may occur.
+ *         os_mutex_take(p_handle, 100);
+ *         os_mutex_take(p_handle, 200);
+ *
+ *         // The mutex has now been 'taken' three times, so will not be
+ *         // available to another task until it has also been given back
+ *         // three times.
+ *         os_mutex_give(p_handle);
+ *         os_mutex_give(p_handle);
+ *         os_mutex_give(p_handle);
+ *
+ *         // Finish accessing the share resource, then release the semaphore.
+ *         // Now the mutex can be taken by other tasks.
+ *     }
+ *     else
+ *     {
+ *         // Could not access the share resource.
+ *     }
+ * }
+ * \endcode
+ *
+ */
+extern bool (*os_mutex_take)(void *p_handle, uint32_t wait_ms);
+
+/**
+ * os_sync.h
+ *
+ * \brief   Give a mutex.
+ *
+ * \param   p_handle    The handle of the mutex to be given.
+ *
+ * \return           The status of the mutex giving.
+ * \retval true      Mutex was given successfully.
+ * \retval false     Mutex was failed to give.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * void *p_handle = NULL;
+ *
+ * // One task creates a mutex.
+ * void task1(void *p_param)
+ * {
+ *     // Create a mutex.
+ *     os_mutex_create(&p_handle);
+ * }
+ *
+ * // Anohter task uses the mutex.
+ * void task2(void *p_param)
+ * {
+ *     // See if we can obtain the mutex. If the mutex is
+ *     // not available, wait for 100ms.
+ *     if (os_mutex_take(p_handle, 100) == true)
+ *     {
+ *         // Access the share resource.
+ *
+ *         // In real code, recursive calls of mutex may occur.
+ *         os_mutex_take(p_handle, 100);
+ *         os_mutex_take(p_handle, 200);
+ *
+ *         // The mutex has now been 'taken' three times, so will not be
+ *         // available to another task until it has also been given back
+ *         // three times.
+ *         os_mutex_give(p_handle);
+ *         os_mutex_give(p_handle);
+ *         os_mutex_give(p_handle);
+ *
+ *         // Finish accessing the share resource, then release the semaphore.
+ *         // Now the mutex can be taken by other tasks.
+ *     }
+ *     else
+ *     {
+ *         // Could not access the share resource.
+ *     }
+ * }
+ * \endcode
+ *
+ */
+extern bool (*os_mutex_give)(void *p_handle);
+
+/** End of group OS_SYNC_Exported_Functions
+  * @}
+  */
+
+/** End of OS_SYNC
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _OS_SYNC_H_ */
diff --git a/bee/os/osif/inc/rtl87x2g/os_task.h b/bee/os/osif/inc/rtl87x2g/os_task.h
new file mode 100644
index 00000000..6626a966
--- /dev/null
+++ b/bee/os/osif/inc/rtl87x2g/os_task.h
@@ -0,0 +1,574 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _OS_TASK_H_
+#define _OS_TASK_H_
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup    OS_TASK Task Management
+ *
+ * \brief   Define, create, and control task functions.
+ * \details The Task Management function group allows to create, delete, and control tasks
+ *          in the system.\n
+ * Tasks can be in the following states:\n
+ * \arg <b>RUNNING:</b> The task that is currently running is in the <b>RUNNING</b> state.
+ *                      Only one task at a time can be in this state.
+ * \arg <b>READY:</b> Tasks which are ready to run are in the <b>READY</b> state. Once the
+ *                    <b>RUNNING</b> task has terminated or is <b>WAITING</b>, the next
+ *                    <b>READY</b> task with the highest priority becomes the <b>RUNNING</b> task.
+ * \arg <b>WAITING:</b> Tasks that are waiting for an event to occur are in the WAITING state.
+ * \arg <b>INACTIVE</b>: Tasks that are not created or terminated are in the <b>INACTIVE</b> state.
+ *                       These Tasks typically consume no system resources.
+ *
+ * \image html OS-task-state-transition.jpg "Task State Transition" width=526px height=526px
+ *
+ */
+
+/*============================================================================*
+ *                              Functions
+*============================================================================*/
+/** @defgroup OS_TASK_Exported_Functions OS Task Exported Functions
+  * \ingroup  OS_TASK
+  * @{
+  */
+
+/**
+  * @brief  Allocate secure stack for task switch when trustzone is enabled
+  * @param  secure stack size, unit: Byte
+  * @return result of allocating secure stack
+  */
+extern bool (*os_alloc_secure_ctx)(uint32_t stack_size);
+
+/**
+ * os_task.h
+ *
+ * \brief Create a new task and add it to the list of tasks that are ready to run.
+ *
+ * \param  pp_handle  Used to pass back a handle by which the created task
+ *                         can be referenced.
+ *
+ * \param   p_name     A descriptive name for the task.
+ *
+ * \param   p_routine  Pointer to task routine function that must be implemented
+ *                         to never return.
+ *
+ * \param   p_param    Pointer parameter passed to the task routine function.
+ *
+ * \param   stack_size The size of the task stack that is specified as the number
+ *                         of bytes.
+ *
+ * \param   priority   The priority at which the task should run. Higher priority
+ *                         task has higher priority value.
+ *
+ * \return           The status of the task creation.
+ * \retval true      Task was created successfully and added to task ready list.
+ * \retval false     Task was failed to create.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * // Task routine implementation.
+ * void task_routine(void *p_param)
+ * {
+ *     for (;;)
+ *     {
+ *          // Task code goes here.
+ *     }
+ * }
+ *
+ * // Task to be created.
+ * int test(void)
+ * {
+ *     void *p_handle = NULL;
+ *     uint32_t task_param;
+ *
+ *     if (os_task_create(&p_handle, "task", task_routine,
+ *                        &task_param, STACK_SIZE, TASK_PRIORITY) == true)
+ *     {
+ *         // Task created successfully.
+ *     }
+ *     else
+ *     {
+ *         // Task failed to create.
+ *         return -1;
+ *     }
+ *
+ *     // Use the handle to delete the task.
+ *     os_task_delete(p_handle);
+ *
+ *     return 0;
+ * }
+ * \endcode
+ *
+ */
+extern bool (*os_task_create)(void **pp_handle, const char *p_name, void (*p_routine)(void *),
+                              void *p_param, uint16_t stack_size, uint16_t priority);
+
+/**
+ * os_task.h
+ *
+ * \brief Remove a task from RTOS's task management. The task being deleted will be removed
+ * from RUNNING, READY or WAITING state.
+ *
+ * \param p_handle  The handle of the task to be deleted.
+ *
+ * \return           The status of the task deletion.
+ * \retval true      Task was deleted successfully.
+ * \retval false     Task was failed to delete.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * // Task routine implementation.
+ * void task_routine(void *p_param)
+ * {
+ *     for (;;)
+ *     {
+ *          // Task code goes here.
+ *     }
+ * }
+ *
+ * // Task to be created and deleted.
+ * int test(void)
+ * {
+ *     void *p_handle = NULL;
+ *     uint32_t task_param;
+ *
+ *     if (os_task_create(&p_handle, "task", task_routine,
+ *                        &task_param, STACK_SIZE, TASK_PRIORITY) == true)
+ *     {
+ *         // Task created successfully.
+ *     }
+ *     else
+ *     {
+ *         // Task failed to create.
+ *         return -1;
+ *     }
+ *
+ *     // Use the handle to delete the task.
+ *     os_task_delete(p_handle);
+ *
+ *     return 0;
+ * }
+ * \endcode
+ *
+ */
+extern bool (*os_task_delete)(void *p_handle);
+
+/**
+ * os_task.h
+ *
+ * \brief Suspend the task. The suspended task will not be scheduled and never get
+ * any microcontroller processing time.
+ *
+ * \param p_handle  The handle of the task to be suspended.
+ *
+ * \return           The status of the task suspension.
+ * \retval true      Task was suspended successfully.
+ * \retval false     Task was failed to suspend.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * // Task routine implementation.
+ * void task_routine(void *p_param)
+ * {
+ *     for (;;)
+ *     {
+ *          // Task code goes here.
+ *     }
+ * }
+ *
+ * // Task to be created and suspended.
+ * int test(void)
+ * {
+ *     void *p_handle = NULL;
+ *     uint32_t task_param;
+ *
+ *     if (os_task_create(&p_handle, "task", task_routine,
+ *                        &task_param, STACK_SIZE, TASK_PRIORITY) == true)
+ *     {
+ *         // Task created successfully.
+ *     }
+ *     else
+ *     {
+ *         // Task failed to create.
+ *         return -1;
+ *     }
+ *
+ *     // Use the handle to suspend the created task.
+ *     os_task_suspend(p_handle);
+ *
+ *     return 0;
+ * }
+ * \endcode
+ *
+ */
+extern bool (*os_task_suspend)(void *p_handle);
+
+/**
+ * os_task.h
+ *
+ * \brief Resume the suspended task.
+ *
+ * \param p_handle  The handle of the task to be resumed.
+ *
+ * \return           The status of the task resume.
+ * \retval true      Task was resumed successfully.
+ * \retval false     Task was failed to resume.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * // Task routine implementation.
+ * void task_routine(void *p_param)
+ * {
+ *     for (;;)
+ *     {
+ *          // Task code goes here.
+ *     }
+ * }
+ *
+ * // Task to be suspended and resumed.
+ * int test(void)
+ * {
+ *     void *p_handle = NULL;
+ *     uint32_t task_param;
+ *
+ *     if (os_task_create(&p_handle, "task", task_routine,
+ *                        &task_param, STACK_SIZE, TASK_PRIORITY) == true)
+ *     {
+ *         // Task created successfully.
+ *     }
+ *     else
+ *     {
+ *         // Task failed to create.
+ *         return -1;
+ *     }
+ *
+ *     // Use the handle to suspend the created task.
+ *     os_task_suspend(p_handle);
+ *
+ *     // Resume the suspended task by ourselves.
+ *     os_task_resume(p_handle);
+ *     return 0;
+ * }
+ * \endcode
+ *
+ */
+extern bool (*os_task_resume)(void *p_handle);
+
+/**
+ * os_task.h
+ *
+ * \brief Force a context swith and pass control to the next task that is in
+ * READY state.
+ *
+ * \param None
+ *
+ * \return           The status of the task resume.
+ * \retval true      Task was yielded successfully.
+ * \retval false     Task was failed to yield.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * // Task routine implementation.
+ * void task_routine(void *p_param)
+ * {
+ *     for (;;)
+ *     {
+ *          // Force a context switch
+ *          os_task_yield();
+ *     }
+ * }
+ *
+ * // Task to be created.
+ * int test(void)
+ * {
+ *     void *p_handle = NULL;
+ *     uint32_t task_param;
+ *
+ *     if (os_task_create(&p_handle, "task", task_routine,
+ *                        &task_param, STACK_SIZE, TASK_PRIORITY) == true)
+ *     {
+ *         // Task created successfully.
+ *     }
+ *     else
+ *     {
+ *         // Task failed to create.
+ *         return -1;
+ *     }
+ *
+ *     return 0;
+ * }
+ * \endcode
+ *
+ */
+extern bool (*os_task_yield)(void);
+
+/**
+ * os_task.h
+ *
+ * \brief Get the handle of the current running task.
+ *
+ * \param pp_handle  Used to pass back a handle by which the current task
+ *                        can be referenced.
+ *
+ * \return           The status of getting the current task handle.
+ * \retval true      Task handle was got successfully.
+ * \retval false     Task handle was failed to get.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * // Get current task handle.
+ * int test(void)
+ * {
+ *     void *p_handle = NULL;
+ *
+ *     os_task_handle_get(&p_handle);
+ *
+ *     return 0;
+ * }
+ * \endcode
+ *
+ */
+extern bool (*os_task_handle_get)(void **pp_handle);
+
+/**
+ * os_task.h
+ *
+ * \brief Get the priority of the specified task.
+ *
+ * \param p_handle    The handle of the task to be queried. Passing a NULL handle
+ *                        means querying the priority of the current task.
+ *
+ * \param p_priority Used to pass back the priority of the task.
+ *
+ * \return           The status of getting the task priority.
+ * \retval true      Task priority was got successfully.
+ * \retval false     Task priority was failed to get.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * int test(void)
+ * {
+ *     void *p_handle = NULL;
+ *     uint16_t priority;
+ *
+ *     if (os_task_create(&p_handle, "task", task_routine,
+ *                        NULL, STACK_SIZE, TASK_PRIORITY) == true)
+ *     {
+ *         // Task created successfully.
+ *     }
+ *     else
+ *     {
+ *         // Task failed to create.
+ *         return -1;
+ *     }
+ *
+ *     // Get the task priority.
+ *     os_task_priority_get(p_handle, &priority);
+ *
+ *     return 0;
+ * }
+ * \endcode
+ *
+ */
+extern bool (*os_task_priority_get)(void *p_handle, uint16_t *p_priority);
+
+/**
+ * os_task.h
+ *
+ * \brief Set the priority of the specified task.
+ *
+ * \param p_handle  The handle of the task for which the priority is being set.
+ *                      Passing a NULL handle means setting the priority of the
+ *                      current task.
+ *
+ * \param priority  The priority to which the task will be set.
+ *
+ * \return           The status of setting the task priority.
+ * \retval true      Task priority was set successfully.
+ * \retval false     Task priority was failed to set.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * int test(void)
+ * {
+ *     void *p_handle = NULL;
+ *     uint16_t priority;
+ *
+ *     if (os_task_create(&p_handle, "task", task_routine,
+ *                        NULL, STACK_SIZE, TASK_PRIORITY) == true)
+ *     {
+ *         // Task created successfully.
+ *     }
+ *     else
+ *     {
+ *         // Task failed to create.
+ *         return -1;
+ *     }
+ *
+ *     // Use the handle to raise the created task priority.
+ *     os_task_priority_set(p_handle, TASK_PRIORITY + 1);
+ *
+ *     // Use a NULL handle to raise the current task priority.
+ *     os_task_priority_set(NULL, TASK_PRIORITY + 1);
+ *
+ *     return 0;
+ * }
+ * \endcode
+ *
+ */
+extern bool (*os_task_priority_set)(void *p_handle, uint16_t priority);
+
+
+/** End of group OS_TASK_Exported_Functions
+  * @}
+  */
+
+/** End of OS_TASK
+  * @}
+  */
+
+/**
+ * os_task.h
+ *
+ * \brief Send a notification signal to the specified task.
+ *
+ * The notification signal sent to a task will remain pending until it is
+ * cleared by the task calling os_task_signal_recv(). If the task was already
+ * in the WAITING state to wait for the singal, then the task will be removed
+ * from WAITING state and the signal cleared.
+ *
+ * \param p_handle  The handle of the task to which the signal is sent.
+ *
+ * \param signal    The signal to be sent.
+ *
+ * \return          The status of sending the signal.
+ * \retval true     Task signal was sent successfully.
+ * \retval false    Task signal was failed to send.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * int test(void)
+ * {
+ *     void *p_handle = NULL;
+ *     uint32_t signal;
+ *
+ *     if (os_task_create(&p_handle, "task", task_routine,
+ *                        NULL, STACK_SIZE, TASK_PRIORITY) == true)
+ *     {
+ *         // Task created successfully.
+ *     }
+ *     else
+ *     {
+ *         // Task failed to create.
+ *         return -1;
+ *     }
+ *
+ *     // Send signal to the created task.
+ *     singal = 1;
+ *     os_task_signal_send(p_handle, signal);
+ *
+ *     return 0;
+ * }
+ * \endcode
+ *
+ */
+extern bool (*os_task_signal_send)(void *p_handle, uint32_t signal);
+
+/**
+ * os_task.h
+ *
+ * \brief Wait for a notification signal.
+ *
+ * \param p_signal Used to pass back the received signal.
+ *
+ * \param wait_ms   The timeout in milliseconds to wait for the signal.
+ * \arg \c 0            No blocking and return immediately.
+ * \arg \c 0xFFFFFFFF   Block infinitely until the signal received.
+ * \arg \c others       The timeout value in milliseconds.
+ *
+ * \return          The status of receiving the signal.
+ * \retval true     Task signal was received successfully.
+ * \retval false    Task signal was failed to receive.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * int test(void)
+ * {
+ *     uint32_t signal;
+ *
+ *     // Block to wait for the signal sent from other tasks.
+ *     os_task_signal_recv(&signal, 0xFFFFFFFF);
+ *
+ *     return 0;
+ * }
+ * \endcode
+ *
+ */
+extern bool (*os_task_signal_recv)(uint32_t *p_signal, uint32_t wait_ms);
+
+/**
+ * os_task.h
+ *
+ * \brief Clear the signal of the specified task.
+ *
+ * \param p_handle  The handle of the task to which the signal is clear.
+ *
+ * \return          The status of clearing the signal.
+ * \retval true     Task signal was cleared successfully.
+ * \retval false    Task signal was failed to clear.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * int test(void)
+ * {
+ *     void *p_handle = NULL;
+ *     uint32_t signal;
+ *
+ *     if (os_task_create(&p_handle, "task", task_routine,
+ *                        NULL, STACK_SIZE, TASK_PRIORITY) == true)
+ *     {
+ *         // Task created successfully.
+ *     }
+ *     else
+ *     {
+ *         // Task failed to create.
+ *         return -1;
+ *     }
+ *
+ *     // Send signal to the created task.
+ *     singal = 1;
+ *     os_task_signal_send(p_handle, signal);
+ *
+ *     // Clear signal of the created task.
+ *     os_task_signal_clear(p_handle);
+ *
+ *     return 0;
+ * }
+ * \endcode
+ *
+ */
+extern bool (*os_task_signal_clear)(void *p_handle);
+
+extern bool (*os_task_signal_create)(void *p_handle, uint32_t count);
+
+extern bool (*os_task_notify_take)(long xClearCountOnExit, uint32_t xTicksToWait,
+                                   uint32_t *p_notify);
+extern bool (*os_task_notify_give)(void *p_handle);
+
+extern void (*os_task_status_dump)(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _OS_TASK_H_ */
diff --git a/bee/os/osif/inc/rtl87x2g/os_timer.h b/bee/os/osif/inc/rtl87x2g/os_timer.h
new file mode 100644
index 00000000..a953b0c2
--- /dev/null
+++ b/bee/os/osif/inc/rtl87x2g/os_timer.h
@@ -0,0 +1,519 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _OS_TIMER_H_
+#define _OS_TIMER_H_
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup    OS_TIMER Timer Management
+ *
+ * \brief   Create and control software timer and timer callback functions.
+ * \details The Timer Management function group allows to create, delete, and control software
+ *          timers in the system. The software timers can be configured as one-short or periodic
+ *          timers. When a timer expires, a callback function associated with the timer is
+ *          executed.\n
+ * Timers can be in the following two states:\n
+ * \arg <b>Dormant</b> The timer first enters <b>Dormant</b> or <b>Inactive</b> state when created.
+ *                     If a one-short timer expires but not restarts yet, or is stopped the timer
+ *                     will be tranformed from <b>Active</b> state into <b>Dormant</b> state.
+ * \arg <b>Active</b> The timer enters <b>Active</b> state If the timer starts or restarts. When
+ *                    expired, the callback function associcated with the timer will be executed.
+ *
+ * \image html OS-timer-state-transition.jpg "Software Timer State Transition" width=617px height=321px
+ *
+ */
+
+/*============================================================================*
+ *                              Functions
+*============================================================================*/
+/** @defgroup OS_TIMER_Exported_Functions OS Timer Exported Functions
+  * \ingroup  OS_TIMER
+  * @{
+  */
+
+/**
+ * os_timer.h
+ *
+ * \brief    Get the ID assigned to the timer when created.
+ *
+ * \param   pp_handle   Pointer to the created timer handle.
+ *
+ * \param  p_timer_id  Used to pass back the ID assigned to the timer.
+ *
+ * \return           The status of the timer id getting.
+ * \retval true      Timer ID was got successfully.
+ * \retval false     Timer ID was failed to get.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * // Timer callback function.
+ * void timer_callback(void *p_handle)
+ * {
+ *     uint32_t timer_id;
+ *
+ *     // Which timer expired?
+ *     os_timer_id_get(&p_handle, &timer_id);
+ *
+ *     if (timer_id == TIMER_ID)
+ *     {
+ *          // Delete the specified timer.
+ *          os_timer_delete(&p_handle);
+ *     }
+ * }
+ *
+ * #define TIMER_ID 1
+ *
+ * // Timer to be created.
+ * int test(void)
+ * {
+ *     void *p_handle = NULL;
+ *
+ *     if (os_timer_create(&p_handle, "timer", TIMER_ID,
+ *                        INTERVAL_MS, false, timer_callback) == true)
+ *     {
+ *         // Timer created successfully, start the timer.
+ *         os_timer_start(&p_handle);
+ *     }
+ *     else
+ *     {
+ *         // Timer failed to create.
+ *         return -1;
+ *     }
+ *
+ *     return 0;
+ * }
+ * \endcode
+ *
+ */
+extern bool (*os_timer_id_get)(void **pp_handle, uint32_t *p_timer_id);
+
+/**
+ * os_timer.h
+ *
+ * \brief   Create a new software timer instance. This allocates the storage required by
+ *          the new timer, initializes the new timers internal state, and returns a handle
+ *          by which the new timer can be referenced.
+ *
+ * \param  pp_handle        Used to pass back a handle by which the created timer
+ *                               can be referenced.
+ *
+ * \param   p_timer_name     A descriptive name for the timer.
+ *
+ * \param   timer_id         An identifier that is assigned to the timer being created.
+ *                               Typically this would be used in the timer callback function to
+ *                               identify which timer expired when the same callback function is
+ *                               assigned to more than one timer.
+ *
+ * \param   interval_ms      The timer period in milliseconds.
+ *
+ * \param   reload           Used to set the timer as a periodic or one-shot timer.
+ * \arg \c      true             Create a periodic timer.
+ * \arg \c      false            Create a one-shot timer.
+ *
+ * \param   p_timer_callback The function to call when the timer expires. Callback functions
+ *                               must have the prototype defined as 'void callback(void *)'.
+ *
+ * \return           The status of the timer creation.
+ * \retval true      Timer was created successfully.
+ * \retval false     Timer was failed to create.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * // Timer callback function.
+ * void timer_callback(void *p_handle)
+ * {
+ *     uint32_t timer_id;
+ *
+ *     // Which timer expired?
+ *     os_timer_id_get(&p_handle, &timer_id);
+ *
+ *     if (timer_id == TIMER_ID)
+ *     {
+ *          // Delete the specified timer.
+ *          os_timer_delete(&p_handle);
+ *     }
+ * }
+ *
+ * #define TIMER_ID 1
+ *
+ * // Timer to be created.
+ * int test(void)
+ * {
+ *     void *p_handle = NULL;
+ *
+ *     if (os_timer_create(&p_handle, "timer", TIMER_ID,
+ *                        INTERVAL_MS, false, timer_callback) == true)
+ *     {
+ *         // Timer created successfully, start the timer.
+ *         os_timer_start(&p_handle);
+ *     }
+ *     else
+ *     {
+ *         // Timer failed to create.
+ *         return -1;
+ *     }
+ *
+ *     return 0;
+ * }
+ * \endcode
+ *
+ */
+extern bool (*os_timer_create)(void **pp_handle, const char *p_timer_name, uint32_t timer_id,
+                               uint32_t interval_ms, bool reload, void (*p_timer_callback)(void *));
+
+/**
+ * os_timer.h
+ *
+ * \brief    Start a timer that was previously created using the os_timer_create() API
+ *           function. If the timer had already been started and was in the active state,
+ *           then os_timer_create() has equivalent functionality to the os_timer_create()
+ *           API function.
+ *
+ * \param pp_handle Pointer to the created timer handle.
+ *
+ * \return           The status of the timer starting.
+ * \retval true      Timer was started successfully.
+ * \retval false     Timer was failed to start.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * // Timer callback function.
+ * void timer_callback(void *p_handle)
+ * {
+ *     uint32_t timer_id;
+ *
+ *     // Which timer expired?
+ *     os_timer_id_get(&p_handle, &timer_id);
+ *
+ *     if (timer_id == TIMER_ID)
+ *     {
+ *          // Delete the specified timer.
+ *          os_timer_delete(&p_handle);
+ *     }
+ * }
+ *
+ * #define TIMER_ID 1
+ *
+ * // Timer to be created.
+ * int test(void)
+ * {
+ *     void *p_handle = NULL;
+ *
+ *     if (os_timer_create(&p_handle, "timer", TIMER_ID,
+ *                        INTERVAL_MS, false, timer_callback) == true)
+ *     {
+ *         // Timer created successfully, start the timer.
+ *         os_timer_start(&p_handle);
+ *     }
+ *     else
+ *     {
+ *         // Timer failed to create.
+ *         return -1;
+ *     }
+ *
+ *     return 0;
+ * }
+ * \endcode
+ *
+ */
+extern bool (*os_timer_start)(void **pp_handle);
+
+/**
+ * os_timer.h
+ *
+ * \brief     Restart a timer that was previously created using the os_timer_create() API
+ *            function. If the timer had already been started and was already in the active
+ *            state, then os_timer_start() will cause the timer to re-evaluate its expiry
+ *            time so that it is relative to when os_timer_start() was called. If the timer
+ *            was in the dormant state then os_timer_start() has equivalent functionality to
+ *            the os_timer_start() API function.
+ *
+ * \param pp_handle     Pointer to the created timer handle.
+ *
+ * \param interval_ms   The timer period in milliseconds.
+ *
+ * \return           The status of the timer restarting.
+ * \retval true      Timer was restarted successfully.
+ * \retval false     Timer was failed to restart.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * // Timer callback function.
+ * void timer_callback(void *p_handle)
+ * {
+ *     uint32_t timer_id;
+ *
+ *     // Which timer expired?
+ *     os_timer_id_get(&p_handle, &timer_id);
+ *
+ *     if (timer_id == TIMER_ID)
+ *     {
+ *          // Restart the specified timer.
+ *          os_timer_restart(&p_handle);
+ *     }
+ * }
+ *
+ * #define TIMER_ID 1
+ *
+ * // Timer to be created.
+ * int test(void)
+ * {
+ *     void *p_handle = NULL;
+ *
+ *     if (os_timer_create(&p_handle, "timer", TIMER_ID,
+ *                        INTERVAL_MS, false, timer_callback) == true)
+ *     {
+ *         // Timer created successfully, start the timer.
+ *         os_timer_start(&p_handle);
+ *     }
+ *     else
+ *     {
+ *         // Timer failed to create.
+ *         return -1;
+ *     }
+ *
+ *     return 0;
+ * }
+ * \endcode
+ *
+ */
+extern bool (*os_timer_restart)(void **pp_handle, uint32_t interval_ms);
+
+/**
+ * os_timer.h
+ *
+ * \brief     Stop a timer that was previously started using either of the os_timer_start(),
+ *            os_timer_restart() API functions. Stopping a timer ensures the timer is not in
+ *            the active state.
+ *
+ * \param pp_handle Pointer to the handle of timer being stopped.
+ *
+ * \return           The status of the timer stopping.
+ * \retval true      Timer was stopped successfully.
+ * \retval false     Timer was failed to stop.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * // Timer callback function.
+ * void timer_callback(void *p_handle)
+ * {
+ *     uint32_t timer_id;
+ *
+ *     // Which timer expired?
+ *     os_timer_id_get(&p_handle, &timer_id);
+ *
+ *     if (timer_id == TIMER_ID)
+ *     {
+ *          // Delete the specified timer.
+ *          os_timer_delete(&p_handle);
+ *     }
+ * }
+ *
+ * #define TIMER_ID 1
+ *
+ * // Timer to be created and stopped.
+ * int test(void)
+ * {
+ *     void *p_handle = NULL;
+ *
+ *     if (os_timer_create(&p_handle, "timer", TIMER_ID,
+ *                        INTERVAL_MS, false, timer_callback) == true)
+ *     {
+ *         // Timer created successfully, start the timer.
+ *         os_timer_start(&p_handle);
+ *     }
+ *     else
+ *     {
+ *         // Timer failed to create.
+ *         return -1;
+ *     }
+ *
+ *     // Stop the timer before expiration.
+ *     os_timer_stop(&p_handle);
+ *
+ *     return 0;
+ * }
+ * \endcode
+ *
+ */
+extern bool (*os_timer_stop)(void **pp_handle);
+
+/**
+ * os_timer.h
+ *
+ * \brief      Delete a timer that was previously created using the os_timer_create()
+ *             API function.
+ *
+ * \param pp_handle Pointer to the handle of timer being deleted.
+ *
+ * \return           The status of the timer deletion.
+ * \retval true      Timer was deleted successfully.
+ * \retval false     Timer was failed to delete.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * // Timer callback function.
+ * void timer_callback(void *p_handle)
+ * {
+ *     uint32_t timer_id;
+ *
+ *     // Which timer expired?
+ *     os_timer_id_get(&p_handle, &timer_id);
+ *
+ *     if (timer_id == TIMER_ID)
+ *     {
+ *          // Delete the specified timer.
+ *          os_timer_delete(&p_handle);
+ *     }
+ * }
+ *
+ * #define TIMER_ID 1
+ *
+ * // Timer to be created and deleted.
+ * int test(void)
+ * {
+ *     void *p_handle = NULL;
+ *
+ *     if (os_timer_create(&p_handle, "timer", TIMER_ID,
+ *                        INTERVAL_MS, false, timer_callback) == true)
+ *     {
+ *         // Timer created successfully, start the timer.
+ *         os_timer_start(&p_handle);
+ *     }
+ *     else
+ *     {
+ *         // Timer failed to create.
+ *         return -1;
+ *     }
+ *
+ *     return 0;
+ * }
+ * \endcode
+ *
+ */
+extern bool (*os_timer_delete)(void **pp_handle);
+
+/**
+ * os_timer.h
+ *
+ * \brief      Dump all current used timers in system.
+ *
+ * \param None
+ *
+ * \return           The status of the timer dump.
+ * \retval true      Timer was dumped successfully.
+ * \retval false     Timer was failed to dump.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * // Timer callback function.
+ * void timer_callback(void *p_handle)
+ * {
+ *     uint32_t timer_id;
+ *
+ *     // Which timer expired?
+ *     os_timer_id_get(&p_handle, &timer_id);
+ *
+ *     if (timer_id == TIMER_ID)
+ *     {
+ *          // Delete the specified timer.
+ *          os_timer_delete(&p_handle);
+ *     }
+ * }
+ *
+ * #define TIMER_ID 1
+ *
+ * // Timer to be created and dumped.
+ * int test(void)
+ * {
+ *     void *p_handle = NULL;
+ *
+ *     if (os_timer_create(&p_handle, "timer", TIMER_ID,
+ *                        INTERVAL_MS, false, timer_callback) == true)
+ *     {
+ *         // Timer created successfully, start the timer.
+ *         os_timer_start(&p_handle);
+ *     }
+ *     else
+ *     {
+ *         // Timer failed to create.
+ *         return -1;
+ *     }
+ *
+ *     // Dump all used timers.
+ *     os_timer_dump();
+ *
+ *     return 0;
+ * }
+ * \endcode
+ *
+ */
+extern bool (*os_timer_pend_function_call)(void (*p_pend_function)(void *, uint32_t),
+                                           void *pvParameter1, uint32_t ulParameter2);
+
+/**
+  * @brief  Get number of sw timer
+  * @param  pp_handle Pointer to the handle of timer
+  * @param  p_timer_number number of sw timer
+  * @return reseult of operation
+  * \retval true  get sw timer number successfully.
+  * \retval false get sw timer number fail.
+  */
+extern bool (*os_timer_get_timer_number)(void **pp_handle, uint8_t *p_timer_number);
+
+/**
+  * @brief  Check if sw timer is active
+  * @param  pp_handle Pointer to the handle of timer
+  * @return reseult of operation
+  * \retval true  sw timer is active.
+  * \retval false sw timer is not active.
+  */
+extern bool (*os_timer_is_timer_active)(void **pp_handle);
+
+/**
+  * @brief  Get auto reload status of sw timer
+  * @param  pp_handle Pointer to the handle of timer
+  * @param  p_autoreload auto reload status of sw timer
+  * @return reseult of operation
+  * \retval true  get auto reload status of sw timer successfully.
+  * \retval false get auto reload status of sw timer fail.
+  */
+extern bool (*os_timer_get_auto_reload)(void **pp_handle, long *p_autoreload);
+
+/**
+  * @brief  Get state of sw timer, similar with API "os_timer_is_timer_active"
+  * @param  pp_handle Pointer to the handle of timer
+  * @param  p_timer_state state of sw timer
+  * @return reseult of operation
+  * \retval true  get state of sw timer successfully.
+  * \retval false get state of sw timer fail.
+  */
+extern bool (*os_timer_state_get)(void **pp_handle, uint32_t *p_timer_state);
+
+/** End of group OS_TIMER_Exported_Functions
+  * @}
+  */
+
+/** End of OS_TIMER
+  * @}
+  */
+
+extern bool (*os_timer_dump)(void);
+extern void (*os_timer_init)(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _OS_TIMER_H_ */
+
diff --git a/bee/os/osif/inc/rtl87x2j/os_interface.h b/bee/os/osif/inc/rtl87x2j/os_interface.h
new file mode 100644
index 00000000..504d73a0
--- /dev/null
+++ b/bee/os/osif/inc/rtl87x2j/os_interface.h
@@ -0,0 +1,101 @@
+#ifndef OS_INTERFACE_H
+#define OS_INTERFACE_H
+
+#include <stdint.h>
+#include <stddef.h>
+#include "section.h"
+#include "os_mem.h"
+#include "osif.h"
+#include "os_sched.h"
+
+typedef struct _OS_INTERFACE_INFO
+{
+    void *(*os_mem_alloc_intern)(RAM_TYPE ram_type, size_t size);
+    void *(*os_mem_zalloc_intern)(RAM_TYPE ram_type, size_t size);
+    void *(*os_mem_aligned_alloc_intern)(RAM_TYPE ram_type, size_t size, uint8_t alignment);
+    void *(*os_mem_realloc_intern)(RAM_TYPE ram_type, void *ptr, size_t size);
+    void (* os_mem_free)(void *p_block);
+    void (* os_mem_aligned_free)(void *p_block);
+    size_t (* os_mem_peek)(RAM_TYPE ram_type);
+    size_t (* os_mem_peek_max_free_block)(RAM_TYPE ram_type);
+    void (* os_mem_check_heap_usage)(void);
+
+    bool (* os_msg_queue_create)(void **pp_handle,  const char *p_name, uint32_t msg_num,
+                                 uint32_t msg_size);
+    bool (* os_msg_queue_delete_intern)(void *p_handle);
+    bool (* os_msg_queue_peek_intern)(void *p_handle, uint32_t *p_msg_num);
+    bool (* os_msg_send_intern)(void *p_handle, void *p_msg, uint32_t wait_ms);
+    bool (* os_msg_recv_intern)(void *p_handle, void *p_msg, uint32_t wait_ms);
+    bool (* os_msg_peek_intern)(void *p_handle, void *p_msg, uint32_t wait_ms);
+
+    bool (* os_alloc_secure_ctx)(uint32_t stack_size);
+    bool (* os_task_create)(void **pp_handle, const char *p_name, void (*p_routine)(void *),
+                            void *p_param, uint16_t stack_size, uint16_t priority);
+    bool (* os_task_delete)(void *p_handle);
+    bool (* os_task_suspend)(void *p_handle);
+    bool (* os_task_resume)(void *p_handle);
+    bool (* os_task_yield)(void);
+    bool (* os_task_handle_get)(void **pp_handle);
+    bool (* os_task_priority_get)(void *p_handle, uint16_t *p_priority);
+    bool (* os_task_priority_set)(void *p_handle, uint16_t priority);
+    bool (* os_task_signal_send)(void *p_handle, uint32_t signal);
+    bool (* os_task_signal_recv)(uint32_t *p_signal, uint32_t wait_ms);
+    bool (* os_task_signal_clear)(void *p_handle);
+    void (* os_task_status_dump)(void);
+
+    bool (* os_timer_id_get)(void **pp_handle, uint32_t *p_timer_id);
+    bool (* os_timer_create)(void **pp_handle, const char *p_timer_name, uint32_t timer_id,
+                             uint32_t interval_ms, bool reload, void (*p_timer_callback)(void *));
+    bool (* os_timer_start)(void **pp_handle);
+    bool (* os_timer_restart)(void **pp_handle, uint32_t interval_ms);
+    bool (* os_timer_stop)(void **pp_handle);
+    bool (* os_timer_delete)(void **pp_handle);
+    bool (* os_timer_pend_function_call)(void (*p_pend_function)(void *, uint32_t),
+                                         void *pvParameter1, uint32_t ulParameter2);
+    bool (* os_timer_state_get)(void **pp_handle, uint32_t *p_timer_state);
+    bool (* os_timer_auto_reload_get)(void **pp_handle, long *p_autoreload);
+    bool (* os_timer_handle_get)(uint8_t timer_idx, void **pp_handle);
+    bool (* os_timer_dump)(void);
+    void (* os_timer_init)(void);
+
+    uint32_t (* os_lock)(void);
+    void (* os_unlock)(uint32_t s);
+    bool (* os_sem_create)(void **pp_handle, const char *p_name, uint32_t init_count,
+                           uint32_t max_count);
+    bool (* os_sem_delete)(void *p_handle);
+    bool (* os_sem_take)(void *p_handle, uint32_t wait_ms);
+    bool (* os_sem_give)(void *p_handle);
+    bool (* os_mutex_create)(void **pp_handle);
+    bool (* os_mutex_delete)(void *p_handle);
+    bool (* os_mutex_take)(void *p_handle, uint32_t wait_ms);
+    bool (* os_mutex_give)(void *p_handle);
+
+    void (* os_init)(void);
+    void (* os_delay)(uint32_t ms);
+    uint64_t (* os_sys_time_get)(void);
+    uint64_t (* os_sys_tick_get)(void);
+    uint64_t (* os_hp_time_get)(void);
+    bool (* os_sched_start)(void);
+    bool (* os_sched_stop)(void);
+    bool (* os_sched_suspend)(void);
+    bool (* os_sched_resume)(void);
+    bool (* os_sched_state_get)(long *p_state);
+    bool (* os_bottom_half)(T_OSIF_WORK_FUNC func, void *p_arg);
+
+    bool (* os_sched_restore)(void);
+    void (* os_timer_tick_handler)(void);
+    uint32_t (* os_timer_tick_rate_get)(void);
+    uint32_t (* os_timer_clock_get)(void);
+    uint64_t (* os_timer_tick_increase)(uint32_t tick_increment);
+    uint32_t (* os_pm_next_timeout_value_get)(void);
+    bool (* os_pm_excluded_handle_register)(void **handle, PlatformExcludedHandleType type);
+    bool (* os_pm_excluded_handle_unregister)(void **handle, PlatformExcludedHandleType type);
+    void (* os_pm_tickcount_store)(void);
+    void (* os_pm_tickcount_restore)(void);
+    void (* os_pm_init)(void);
+
+} T_OS_INTERFACE_INFO;
+
+extern T_OS_INTERFACE_INFO os_interface;
+
+#endif /* OS_INTERFACE_H */
\ No newline at end of file
diff --git a/bee/os/osif/inc/rtl87x2j/os_interface_init.h b/bee/os/osif/inc/rtl87x2j/os_interface_init.h
new file mode 100644
index 00000000..fd957931
--- /dev/null
+++ b/bee/os/osif/inc/rtl87x2j/os_interface_init.h
@@ -0,0 +1,13 @@
+/**
+ * Copyright (c) 2015, Realsil Semiconductor Corporation. All rights reserved.
+ */
+#ifndef _OS_INTERFACE_H_
+#define _OS_INTERFACE_H_
+
+#include <stdint.h>
+#include <string.h>
+#include "os_interface.h"
+
+void os_interface_update(T_OS_INTERFACE_INFO *os_interface);
+
+#endif /* _OS_INTERFACE_H_ */
\ No newline at end of file
diff --git a/bee/os/osif/inc/rtl87x2j/os_mem.h b/bee/os/osif/inc/rtl87x2j/os_mem.h
new file mode 100644
index 00000000..f731ea92
--- /dev/null
+++ b/bee/os/osif/inc/rtl87x2j/os_mem.h
@@ -0,0 +1,233 @@
+/*
+ * Copyright (c) 2017, Realtek Semiconductor Corporation. All rights reserved.
+ */
+
+#ifndef _OS_MEM_H_
+#define _OS_MEM_H_
+
+#include <stdint.h>
+#include <stddef.h>
+#include "mem_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup    Memory  Memory Management
+ *
+ * \brief   Allocate, free, and peek memory functions.
+ * \details The Memory Management function group allows to allocate, free, and peek heap
+ *          memory in the system.\n
+ *
+ */
+
+
+void *os_mem_alloc_intern(RAM_TYPE ram_type, size_t size);
+
+void *os_mem_zalloc_intern(RAM_TYPE ram_type, size_t size);
+
+void *os_mem_aligned_alloc_intern(RAM_TYPE ram_type, size_t size, uint8_t alignment);
+
+void *os_mem_realloc_intern(RAM_TYPE ram_type, void *ptr, size_t size);
+
+/**
+ * os_mem.h
+ *
+ * \brief    Allocate a memory block with required size.
+ *
+ * \param[in]   ram_type            RAM type for allocation.
+ * \arg \c      RAM_TYPE_DATA_ON    Data ON RAM type.
+ * \arg \c      RAM_TYPE_BUFFER_ON  BUFFER ON RAM type.
+ *
+ * \param[in]   size     Required memory size.
+ *
+ * \return     The address of the allocated memory block. If the address is NULL, the
+ *             memory allocation failed.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * int test(void)
+ * {
+ *     size_t mem_size = 0x1000;
+ *     void *p_mem = NULL;
+ *
+ *     p_mem = os_mem_alloc(RAM_TYPE_DATA_ON, mem_size);
+ *     if (p_mem != NULL)
+ *     {
+ *         // Memory allocation successed, and free it.
+ *         os_mem_free(p_mem);
+ *     }
+ *     else
+ *     {
+ *         // Memory allocation failed.
+ *         return -1;
+ *     }
+ *
+ *     return 0;
+ * }
+ * \endcode
+ *
+ * \ingroup  Memory
+ */
+#define os_mem_alloc(ram_type, size)    \
+    os_mem_alloc_intern(ram_type, size)
+
+
+/**
+ * os_mem.h
+ *
+ * \brief    Allocate and clear a memory block with required size.
+ *
+ * \param[in]   ram_type            RAM type for allocation.
+ * \arg \c      RAM_TYPE_DATA_ON    Data ON RAM type.
+ * \arg \c      RAM_TYPE_BUFFER_ON  BUFFER ON RAM type.
+ *
+ * \param[in]   size     Required memory size.
+ *
+ * \return     The address of the allocated memory block. If the address is NULL, the
+ *             memory allocation failed.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * int test(void)
+ * {
+ *     size_t mem_size = 0x1000;
+ *     void *p_mem = NULL;
+ *
+ *     p_mem = os_mem_zalloc(RAM_TYPE_DATA_ON, mem_size);
+ *     if (p_mem != NULL)
+ *     {
+ *         // Memory allocation successed, and free it.
+ *         os_mem_free(p_mem);
+ *     }
+ *     else
+ *     {
+ *         // Memory allocation failed.
+ *         return -1;
+ *     }
+ *
+ *     return 0;
+ * }
+ * \endcode
+ *
+ * \ingroup  Memory
+ */
+#define os_mem_zalloc(ram_type, size)   \
+    os_mem_zalloc_intern(ram_type, size)
+
+#define os_mem_realloc(ram_type, ptr, size)    \
+    os_mem_realloc_intern(ram_type, ptr, size)
+
+/**
+ * os_mem.h
+ *
+ * \brief    Free a memory block that had been allocated.
+ *
+ * \param[in]   p_block     The address of memory block being freed.
+ *
+ * \return     None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * int test(void)
+ * {
+ *     size_t mem_size = 0x1000;
+ *     void *p_mem = NULL;
+ *
+ *     p_mem = os_mem_alloc(RAM_TYPE_DATA_ON, mem_size);
+ *     if (p_mem != NULL)
+ *     {
+ *         // Memory allocation successed, and free it.
+ *         os_mem_free(p_mem);
+ *     }
+ *     else
+ *     {
+ *         // Memory allocation failed.
+ *         return -1;
+ *     }
+ *
+ *     return 0;
+ * }
+ * \endcode
+ *
+ * \ingroup  Memory
+ */
+void os_mem_free(void *p_block);
+
+void os_mem_aligned_free(void *p_block);
+
+/**
+ * os_mem.h
+ *
+ * \brief    Peek the unused memory size of the specified RAM type.
+ *
+ * \param[in]   ram_type            RAM type for allocation.
+ * \arg \c      RAM_TYPE_DATA_ON    Data ON RAM type.
+ * \arg \c      RAM_TYPE_DATA_OFF   Data OFF RAM type.
+ * \arg \c      RAM_TYPE_BUFFER_ON  BUFFER ON RAM type.
+ * \arg \c      RAM_TYPE_DTCM0_OFF  DTCM0 OFF RAM type.
+ *
+ * \return     The unused memory size in btyes.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * int test(void)
+ * {
+ *     size_t unused_data_on;
+ *     size_t unused_data_off;
+ *
+ *     // Peek unused DATA ON memory size.
+ *     unused_size = os_mem_peek(RAM_TYPE_DATA_ON);
+ *
+ *     // Peek unused DATA OFF memory size.
+ *     unused_size = os_mem_peek(RAM_TYPE_DATA_OFF);
+ *
+ *     return 0;
+ * }
+ * \endcode
+ *
+ * \ingroup  Memory
+ */
+extern size_t os_mem_peek(RAM_TYPE ram_type);
+
+/**
+ * os_mem.h
+ *
+ * \brief    Peek the unused max block memory size of the specified RAM type.
+ *
+ * \param[in]   ram_type            RAM type for allocation.
+ * \arg \c      RAM_TYPE_DATA_ON    Data ON RAM type.
+ * \arg \c      RAM_TYPE_BUFFER_ON  BUFFER ON RAM type.
+ *
+ * \return     The unused memory size in btyes.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * int test(void)
+ * {
+ *     size_t unused_data_on;
+ *     size_t unused_data_off;
+ *
+ *     // Peek unused DATA ON memory size.
+ *     unused_size = os_mem_peek_max_block(RAM_TYPE_DATA_ON);
+ *
+ *     // Peek unused DATA OFF memory size.
+ *     unused_size = os_mem_peek_max_block(RAM_TYPE_DATA_OFF);
+ *
+ *     return 0;
+ * }
+ * \endcode
+ *
+ * \ingroup  Memory
+ */
+size_t os_mem_peek_max_free_block(RAM_TYPE ram_type);
+
+void os_mem_check_heap_usage(void);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _OS_MEM_H_ */
diff --git a/bee/os/osif/inc/rtl87x2j/os_msg.h b/bee/os/osif/inc/rtl87x2j/os_msg.h
new file mode 100644
index 00000000..783343a1
--- /dev/null
+++ b/bee/os/osif/inc/rtl87x2j/os_msg.h
@@ -0,0 +1,433 @@
+/*
+ * Copyright (c) 2015, Realtek Semiconductor Corporation. All rights reserved.
+ */
+
+#ifndef _OS_MSG_H_
+#define _OS_MSG_H_
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup    Message Message Queue
+ *
+ * \brief   Exchange messages between tasks in a FIFO-like operation.
+ * \details The Message Queue function group allows to control, send, receive, or wait for message.
+ *          Message transmission is a basic communication model between tasks that one task sends
+ *          data explicitly, while another task receives it. The operation is more like some
+ *          kind of I/O rather than a direct access to information to be shared. The data to be
+ *          passed can be any type.\n
+ *
+ * \image html OS-message-queue-overview.jpg "Message Queue Overview" width=617px height=321px
+ *
+ */
+
+
+bool os_msg_queue_create_intern(void **pp_handle, const char *p_name, uint32_t msg_num,
+                                uint32_t msg_size,
+                                const char *p_func, uint32_t file_line);
+
+bool os_msg_queue_delete_intern(void *p_handle, const char *p_func, uint32_t file_line);
+
+bool os_msg_queue_peek_intern(void *p_handle, uint32_t *p_msg_num,
+                              const char *p_func, uint32_t file_line);
+
+bool os_msg_send_intern(void *p_handle, void *p_msg, uint32_t wait_ms,
+                        const char *p_func, uint32_t file_line);
+
+bool os_msg_recv_intern(void *p_handle, void *p_msg, uint32_t wait_ms,
+                        const char *p_func, uint32_t file_line);
+
+bool os_msg_peek_intern(void *p_handle, void *p_msg, uint32_t wait_ms,
+                        const char *p_func, uint32_t file_line);
+
+/**
+ * os_msg.h
+ *
+ * \brief   Creates a message queue instance. This allocates the storage required by the
+ *          new queue and passes back a handle for the queue.
+ *
+ * \param[out]  pp_handle  Used to pass back a handle by which the message queue
+ *                         can be referenced.
+ *
+ * \param[in]   p_name     A descriptive name for the message queue.
+ *
+ * \param[in]   msg_num    The maximum number of items that the queue can contain.
+ *
+ * \param[in]   msg_size   The number of bytes each item in the queue will require. Items
+ *                         are queued by copy, not by reference, so this is the number of
+ *                         bytes that will be copied for each posted item. Each item on the
+ *                         queue must be the same size.
+ *
+ * \return           The status of the message queue creation.
+ * \retval true      Message queue was created successfully.
+ * \retval false     Message queue was failed to create.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * struct test_msg
+ * {
+ *     uint8_t id;
+ *     uint8_t data[16];
+ * }
+ *
+ * #define MSG_NUM  10
+ *
+ * int test(void)
+ * {
+ *     void *p_handle = NULL;
+ *
+ *     // Create a queue capable of containing 10 items of structure test_msg.
+ *     if (os_msg_queue_create(&p_handle, "msg queue name", MSG_NUM, sizeof(struct test_msg)) == true)
+ *     {
+ *         // Message queue created successfully.
+ *     }
+ *     else
+ *     {
+ *         // Message queue failed to create.
+ *         return -1;
+ *     }
+ *
+ *     // Delete the message queue.
+ *     os_msg_queue_delete(p_handle);
+ *
+ *     return 0;
+ * }
+ * \endcode
+ *
+ * \ingroup  Message
+ */
+#define os_msg_queue_create(pp_handle, p_name, msg_num, msg_size)    \
+    os_msg_queue_create_intern(pp_handle, p_name, msg_num, msg_size, __func__, __LINE__)
+
+/**
+ * os_msg.h
+ *
+ * \brief   Delete the specified message queue, and free all the memory allocated for
+ *          storing of items placed on the queue.
+ *
+ * \param[in]   p_handle   The handle to the message queue being deleted.
+ *
+ * \return           The status of the message queue deletion.
+ * \retval true      Message queue was deleted successfully.
+ * \retval false     Message queue was failed to delete.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * struct test_msg
+ * {
+ *     uint8_t id;
+ *     uint8_t data[16];
+ * }
+ *
+ * #define MSG_NUM  10
+ *
+ * int test(void)
+ * {
+ *     void *p_handle = NULL;
+ *
+ *     // Create a queue capable of containing 10 items of structure test_msg.
+ *     if (os_msg_queue_create(&p_handle, "msg queue name", MSG_NUM, sizeof(struct test_msg)) == true)
+ *     {
+ *         // Message queue created successfully.
+ *     }
+ *     else
+ *     {
+ *         // Message queue failed to create.
+ *         return -1;
+ *     }
+ *
+ *     // Delete the message queue.
+ *     os_msg_queue_delete(p_handle);
+ *
+ *     return 0;
+ * }
+ * \endcode
+ *
+ * \ingroup  Message
+ */
+#define os_msg_queue_delete(p_handle) \
+    os_msg_queue_delete_intern(p_handle, __func__, __LINE__)
+
+/**
+ * os_msg.h
+ *
+ * \brief    Peek the number of items sent and resided on the message queue.
+ *
+ * \param[in]   p_handle   The handle to the message queue being peeked.
+ *
+ * \param[out]  p_msg_num  Used to pass back the number of items residing on the message queue.
+ *
+ * \return           The status of the message queue peek.
+ * \retval true      Message queue was peeked successfully.
+ * \retval false     Message queue was failed to peek.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * struct test_msg
+ * {
+ *     uint8_t id;
+ *     uint8_t data[16];
+ * }
+ *
+ * #define MSG_NUM  10
+ *
+ * int test(void)
+ * {
+ *     void *p_handle = NULL;
+ *     uint32_t msg_num;
+ *
+ *     // Create a queue capable of containing 10 items of structure test_msg.
+ *     if (os_msg_queue_create(&p_handle, "msg queue name", MSG_NUM, sizeof(struct test_msg)) == true)
+ *     {
+ *         // Message queue created successfully.
+ *     }
+ *     else
+ *     {
+ *         // Message queue failed to create.
+ *         return -1;
+ *     }
+ *
+ *     // Peek the number of items sent on this message queue.
+ *     os_msg_queue_peek(p_handle, &msg_num);
+ *
+ *     return 0;
+ * }
+ * \endcode
+ *
+ * \ingroup  Message
+ */
+#define os_msg_queue_peek(p_handle, p_msg_num)  \
+    os_msg_queue_peek_intern(p_handle, p_msg_num, __func__, __LINE__)
+
+/**
+ * os_msg.h
+ *
+ * \brief   Send an item to the back of the specified message queue. The item is
+ *          queued by copy, not by reference.
+ *
+ * \param[in]   p_handle The handle to the message queue on which the item is to be sent.
+ *
+ * \param[in]   p_msg    Pointer to the item that is to be sent on the queue. The referenced
+ *                       item rather than pointer itself will be copied on the queue.
+ *
+ * \param[in]   wait_ms  The maximum amount of time in milliseconds that the task should
+ *                       block waiting for the item to sent on the queue.
+ * \arg \c 0           No blocking and return immediately.
+ * \arg \c 0xFFFFFFFF  Block infinitely until the item sent.
+ * \arg \c others      The timeout value in milliseconds.
+ *
+ * \return           The status of the message item sent.
+ * \retval true      Message item was sent successfully.
+ * \retval false     Message item was failed to send.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * struct test_msg
+ * {
+ *     uint8_t id;
+ *     uint8_t data[16];
+ * }
+ *
+ * #define MSG_NUM  10
+ *
+ * int test(void)
+ * {
+ *     void *p_handle = NULL;
+ *     struct test_msg msg;
+ *
+ *     // Create a queue capable of containing 10 items of structure test_msg.
+ *     if (os_msg_queue_create(&p_handle, "msg queue name", MSG_NUM, sizeof(struct test_msg)) == true)
+ *     {
+ *         // Message queue created successfully.
+ *     }
+ *     else
+ *     {
+ *         // Message queue failed to create.
+ *         return -1;
+ *     }
+ *
+ *     // Send the item to this message queue.
+ *     msg.id = 1;
+ *     msg.data[0] = 0;
+ *     os_msg_send(p_handle, &msg, 0);
+ *
+ *     return 0;
+ * }
+ * \endcode
+ *
+ * \ingroup  Message
+ */
+#define os_msg_send(p_handle, p_msg, wait_ms) \
+    os_msg_send_intern(p_handle, p_msg, wait_ms, __func__, __LINE__)
+
+/**
+ * os_msg.h
+ *
+ * \brief   Receive an item from the specified message queue. The item is received by
+ *          copy rather than by reference, so a buffer of adequate size must be provided.
+ *
+ * \param[in]   p_handle The handle to the message queue from which the item is to be received.
+ *
+ * \param[out]  p_msg    Pointer to the buffer into which the received item will be copied.
+ *                       item rather than pointer itself will be copied on the queue.
+ *
+ * \param[in]   wait_ms  The maximum amount of time in milliseconds that the task should
+ *                       block waiting for an item to be received from the queue.
+ * \arg \c 0           No blocking and return immediately.
+ * \arg \c 0xFFFFFFFF  Block infinitely until the item received.
+ * \arg \c others      The timeout value in milliseconds.
+ *
+ * \return           The status of the message item received.
+ * \retval true      Message item was received successfully.
+ * \retval false     Message item was failed to receive.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * struct test_msg
+ * {
+ *     uint8_t id;
+ *     uint8_t data[16];
+ * }
+ *
+ * #define MSG_NUM  10
+ *
+ * void *p_handle = NULL;
+ *
+ * void send_msg(void)
+ * {
+ *     struct test_msg msg;
+ *
+ *     // Create a queue capable of containing 10 items of structure test_msg.
+ *     if (os_msg_queue_create(&p_handle, "msg queue name", MSG_NUM, sizeof(struct test_msg)) == true)
+ *     {
+ *         // Message queue created successfully.
+ *     }
+ *     else
+ *     {
+ *         // Message queue failed to create.
+ *         return -1;
+ *     }
+ *
+ *     // Send the item to this message queue.
+ *     msg.id = 1;
+ *     msg.data[0] = 0;
+ *     os_msg_send(p_handle, &msg, 0);
+ *
+ *     return 0;
+ * }
+ *
+ * void receive_msg(void)
+ * {
+ *     struct test_msg msg;
+ *
+ *     // Receive the message queue item.
+ *     if (os_msg_recv(p_handle, &msg, 0) == true)
+ *     {
+ *         // Message item received successfully.
+ *     }
+ *     else
+ *     {
+ *         // Message item failed to receive.
+ *         return -1;
+ *     }
+ *
+ *     return 0;
+ * }
+ * \endcode
+ *
+ * \ingroup  Message
+ */
+#define os_msg_recv(p_handle, p_msg, wait_ms) \
+    os_msg_recv_intern(p_handle, p_msg, wait_ms, __func__, __LINE__)
+
+/**
+ * os_msg.h
+ *
+ * \brief   Receive but not remove an item from the specified message queue. The item is
+ *          received by copy rather than by reference, so a buffer of adequate size must
+ *          be provided.
+ *
+ * \param[in]   p_handle The handle to the message queue on which the item is to be peeked.
+ *
+ * \param[out]  p_msg    Pointer to the buffer into which the received item will be copied.
+ *                       item rather than pointer itself will be copied on the queue.
+ *
+ * \param[in]   wait_ms  The maximum amount of time in milliseconds that the task should
+ *                       block waiting for an item to be received from the queue.
+ * \arg \c 0           No blocking and return immediately.
+ * \arg \c 0xFFFFFFFF  Block infinitely until the item received.
+ * \arg \c others      The timeout value in milliseconds.
+ *
+ * \return           The status of the message item received.
+ * \retval true      Message item was received successfully.
+ * \retval false     Message item was failed to receive.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * struct test_msg
+ * {
+ *     uint8_t id;
+ *     uint8_t data[16];
+ * }
+ *
+ * #define MSG_NUM  10
+ *
+ * void *p_handle = NULL;
+ *
+ * void send_msg(void)
+ * {
+ *     struct test_msg msg;
+ *
+ *     // Create a queue capable of containing 10 items of structure test_msg.
+ *     if (os_msg_queue_create(&p_handle, "msg queue name", MSG_NUM, sizeof(struct test_msg)) == true)
+ *     {
+ *         // Message queue created successfully.
+ *     }
+ *     else
+ *     {
+ *         // Message queue failed to create.
+ *         return -1;
+ *     }
+ *
+ *     // Send the item to this message queue.
+ *     msg.id = 1;
+ *     msg.data[0] = 0;
+ *     os_msg_send(p_handle, &msg, 0);
+ *
+ *     return 0;
+ * }
+ *
+ * void peek_msg(void)
+ * {
+ *     struct test_msg msg;
+ *
+ *     // Peek the message queue item.
+ *     if (os_msg_peek(p_handle, &msg, 0) == true)
+ *     {
+ *         // Message item peeked successfully.
+ *     }
+ *     else
+ *     {
+ *         // Message item failed to peek.
+ *         return -1;
+ *     }
+ *
+ *     return 0;
+ * }
+ * \endcode
+ *
+ * \ingroup  Message
+ */
+#define os_msg_peek(p_handle, p_msg, wait_ms) \
+    os_msg_peek_intern(p_handle, p_msg, wait_ms, __func__, __LINE__)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _OS_MSG_H_ */
diff --git a/bee/os/osif/inc/rtl87x2j/os_pm.h b/bee/os/osif/inc/rtl87x2j/os_pm.h
new file mode 100644
index 00000000..fafebbd1
--- /dev/null
+++ b/bee/os/osif/inc/rtl87x2j/os_pm.h
@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2017, Realtek Semiconductor Corporation. All rights reserved.
+ */
+
+#ifndef _OS_POWER_MANAGER_H_
+#define _OS_POWER_MANAGER_H_
+#include <stdbool.h>
+#include <stdint.h>
+#include <stddef.h>
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
+
+#define UPDATE_TICK_COUNT()\
+    if (portNVIC_INT_CTRL_REG & SCB_ICSR_PENDSTSET_Msk)\
+    {\
+        os_timer_tick_handler();\
+        portNVIC_INT_CTRL_REG = SCB_ICSR_PENDSTCLR_Msk;\
+    }
+
+typedef enum
+{
+    PLATFORM_PM_EXCLUDED_TIMER,
+    PLATFORM_PM_EXCLUDED_TASK,
+    PLATFORM_PM_EXCLUDED_TYPE_MAX,
+} PlatformExcludedHandleType;
+
+typedef struct
+{
+    struct PlatformPMExcludedHandleQueueElem *pNext;
+    void **handle;
+} PlatformPMExcludedHandleQueueElem;
+
+typedef union
+{
+    uint8_t value[1];
+    struct
+    {
+        uint8_t os_pm_statistic:        1;
+        uint8_t os_pm_wake_event:       1;
+        uint8_t rsvd:                   6;
+    };
+} OSPMFeatureConfig;
+
+extern OSPMFeatureConfig os_pm_feature_cfg;
+
+bool os_sched_restore(void);
+void os_timer_tick_handler(void);
+uint32_t os_timer_tick_rate_get(void);
+uint32_t os_timer_clock_get(void);
+uint64_t os_timer_tick_increase(uint32_t tick_increment);
+uint32_t os_pm_next_timeout_value_get(void);
+bool os_pm_excluded_handle_register(void **pp_handle, PlatformExcludedHandleType type);
+bool os_pm_excluded_handle_unregister(void **pp_handle, PlatformExcludedHandleType type);
+void os_pm_tickcount_store(void);
+void os_pm_tickcount_restore(void);
+void os_pm_init(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _OS_POWER_MANAGER_H_ */
diff --git a/bee/os/osif/inc/rtl87x2j/os_sched.h b/bee/os/osif/inc/rtl87x2j/os_sched.h
new file mode 100644
index 00000000..0ada564e
--- /dev/null
+++ b/bee/os/osif/inc/rtl87x2j/os_sched.h
@@ -0,0 +1,315 @@
+/*
+ * Copyright (c) 2015, Realtek Semiconductor Corporation. All rights reserved.
+ */
+
+#ifndef _OS_SCHED_H_
+#define _OS_SCHED_H_
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+  * @defgroup Schedule Kernel Schedule
+  * @brief
+  * @{
+  */
+
+/*============================================================================*
+ *                              Types
+*============================================================================*/
+/**
+  * \defgroup Schedule_Exported_Types Schedule Exported Types
+  * \{
+  */
+
+typedef bool (*T_OSIF_WORK_FUNC)(void *);
+
+/**
+  *  End of Schedule_Exported_Types
+  * \}
+  */
+
+/*============================================================================*
+ *                              Functions
+*============================================================================*/
+
+/**
+  * \defgroup Schedule_Exported_Functions Schedule Exported Functions
+  * \{
+  */
+
+
+/**
+ *
+ * \brief       Delay current task for a given period in milliseconds.
+ *
+ * \param[in]   ms  The amout of timer in milliseconds that the current task
+ *                  should block.
+ *
+ * \return      None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * // Task routine implementation.
+ * void task_routine(void *p_param)
+ * {
+ *     for (;;)
+ *     {
+ *          // Task code goes here.
+ *          os_delay(100);
+ *
+ *          // Do something here per 100ms.
+ *     }
+ * }
+ * \endcode
+ *
+ */
+void os_delay(uint32_t ms);
+
+/**
+ *
+ * \brief   Get the time in milliseconds since os_sched_start() API function was called.
+ *
+ * \param   None
+ *
+ * \return  The time in milliseconds. Note the time represented by a 64-bit integer
+ *          may be overflowed.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * // Task routine implementation.
+ * void task_routine(void *p_param)
+ * {
+ *     uint64_t last_time;
+ *
+ *     // Get the last timestamp.
+ *     last_time = os_sys_time_get();
+ *
+ *     for (;;)
+ *     {
+ *          // Wait for the next cycle.
+ *          os_delay(100);
+ *
+ *          // Do something here per 100ms.
+ *     }
+ * }
+ * \endcode
+ *
+ */
+uint64_t os_sys_time_get(void);
+
+/**
+ *
+ * \brief   Get the time in milliseconds since os_sched_start() API function was called.
+ *
+ * \param   None
+ *
+ * \return  The time in os tick. Note the time represented by a 64-bit integer
+ *          may be overflowed.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * // Task routine implementation.
+ * void task_routine(void *p_param)
+ * {
+ *     uint64_t last_tick;
+ *
+ *     // Get the last timestamp.
+ *     last_tick = os_sys_tick_get();
+ *
+ *     for (;;)
+ *     {
+ *          // Wait for the next cycle.
+ *          os_delay(100);
+ *
+ *          // Do something here per 100ms.
+ *     }
+ * }
+ * \endcode
+ *
+ */
+uint64_t os_sys_tick_get(void);
+
+/**
+ *
+ * \brief   Start the RTOS kernel scheduler.
+ *
+ * \param   None
+ *
+ * \return  The status of starting kernel scheduler.
+ * \retval  true      Scheduler was started successfully.
+ * \retval  false     Scheduler was failed to start.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * int test(void)
+ * {
+ *     // Create at least one task before starting kernel scheduler.
+ *     if (os_task_create(&p_handle, "task", task_routine,
+ *                        NULL, STACK_SIZE, TASK_PRIORITY) == true)
+ *     {
+ *         // Task created successfully.
+ *     }
+ *     else
+ *     {
+ *         // Task failed to create.
+ *         return -1;
+ *     }
+ *
+ *     // Start the kernel scheduler.
+ *     os_sched_start();
+ *
+ *     // Will not get here unless a task calls os_sched_stop().
+ * }
+ * \endcode
+ *
+ */
+bool os_sched_start(void);
+
+/**
+ *
+ * \brief   Stop the RTOS kernel scheduler. All created tasks will be automatically
+ *          deleted and multitasking (either preemptive or cooperative) stops.
+ *
+ * \param   None
+ *
+ * \return  The status of stopping kernel scheduler.
+ * \retval  true      Scheduler was stopped successfully.
+ * \retval  false     Scheduler was failed to stop.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * // Task routine implementation.
+ * void task_routine(void *p_param)
+ * {
+ *     for (;;)
+ *     {
+ *          // Task code goes here.
+ *
+ *          // At some point we want to end the real time kernel processing.
+ *          os_sched_stop();
+ *     }
+ * }
+ *
+ * int test(void)
+ * {
+ *     // Create at least one task before starting kernel scheduler.
+ *     if (os_task_create(&p_handle, "task", task_routine,
+ *                        NULL, STACK_SIZE, TASK_PRIORITY) == true)
+ *     {
+ *         // Task created successfully.
+ *     }
+ *     else
+ *     {
+ *         // Task failed to create.
+ *         return -1;
+ *     }
+ *
+ *     // Start the kernel scheduler.
+ *     os_sched_start();
+ *
+ *     // Will not get here unless a task calls os_sched_stop().
+ * }
+ * \endcode
+ *
+ */
+bool os_sched_stop(void);
+
+/**
+ *
+ * \brief   Suspends the kernel scheduler without disabling interrupts. Context
+ *          switches will not occur while the scheduler is suspended. After calling
+ *          os_sched_suspend(), the calling task will continue to execute without
+ *          risk of being swapped out until a call to os_sched_resume() has been made.
+ *
+ * \param   None
+ *
+ * \return  The status of suspending kernel scheduler.
+ * \retval  true      Scheduler was suspended successfully.
+ * \retval  false     Scheduler was failed to suspend.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * // Task routine implementation.
+ * void task_routine(void *p_param)
+ * {
+ *     for (;;)
+ *     {
+ *          // Task code goes here.
+ *
+ *          // At some point the task wants to perform a long operation, and do not
+ *          // want to get swapped out.
+ *          os_sched_suspend();
+ *
+ *          // The long operation.
+ *
+ *          // The operation is completed, and resume the scheduler.
+ *          os_sched_resume();
+ *     }
+ * }
+ * \endcode
+ *
+ */
+bool os_sched_suspend(void);
+
+/**
+ *
+ * \brief   Resume the kernel scheduler after it was suspended by a call
+ *          to os_sched_suspend().
+ *
+ * \param   None
+ *
+ * \return  The status of resuming kernel scheduler.
+ * \retval  true      Scheduler was resumed successfully.
+ * \retval  false     Scheduler was failed to resume.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * // Task routine implementation.
+ * void task_routine(void *p_param)
+ * {
+ *     for (;;)
+ *     {
+ *          // Task code goes here.
+ *
+ *          // At some point the task wants to perform a long operation, and do not
+ *          // want to get swapped out.
+ *          os_sched_suspend();
+ *
+ *          // The long operation.
+ *
+ *          // The operation is completed, and resume the scheduler.
+ *          os_sched_resume();
+ *     }
+ * }
+ * \endcode
+ *
+ */
+bool os_sched_resume(void);
+
+bool os_sched_is_start(void);
+
+bool os_sched_state_get(long *p_state);
+
+void os_init(void);
+
+bool os_bottom_half(T_OSIF_WORK_FUNC func, void *p_arg);
+
+/**
+  *  End of Schedule_Exported_Functions
+  * \}
+  */
+
+/** End of Schedule
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _OS_SCHED_H_ */
diff --git a/bee/os/osif/inc/rtl87x2j/os_sync.h b/bee/os/osif/inc/rtl87x2j/os_sync.h
new file mode 100644
index 00000000..ac75f953
--- /dev/null
+++ b/bee/os/osif/inc/rtl87x2j/os_sync.h
@@ -0,0 +1,477 @@
+/*
+ * Copyright (c) 2015, Realtek Semiconductor Corporation. All rights reserved.
+ */
+
+#ifndef _OS_SYNC_H_
+#define _OS_SYNC_H_
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup    Synchronization     Inter-Task Communication
+ *
+ * \brief   Manage Inter-task communication functions.
+ * \details Tasks need to communicate with each other or access shared resources together.
+ *          There are many ways to exchange data between tasks, for example using shared
+ *          data, polling loops and message passing.\n
+ *          Many resources can be considered as serially-reusable. This means that they
+ *          can be used repeatedly by different tasks, but only by one task at a time.\n
+ *          The following mechanisms are available to the user:\n
+ * \arg <b>Lock</b>
+ * \arg <b>Semaphore</b>
+ * \arg <b>Mutex</b>
+ *
+ */
+
+
+/**
+ * os_sync.h
+ *
+ * \brief   Enter the critical region. Disable preemptive context switch and interrupts.
+ *
+ * \param   None
+ *
+ * \return      Interrupt mask flag.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * int test(void)
+ * {
+ *     uint32_t s;
+ *
+ *     // Enter the critical section.
+ *     s = os_lock();
+ *     // Allow only one task or ISR to operate the list.
+ *     list_add(p_list, &item);
+ *     // Exit the critical section and restore ISR mask flag.
+ *     os_unlock(s);
+ * }
+ * \endcode
+ *
+ * \ingroup  Synchronization
+ */
+uint32_t os_lock(void);
+
+/**
+ * os_sync.h
+ *
+ * \brief   Exit the critical region. Enable preemptive context switch and interrupts.
+ *
+ * \param[in]   s   Interrupt mask flag to be restored.
+ *
+ * \return      None.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * int test(void)
+ * {
+ *     uint32_t s;
+ *
+ *     // Enter the critical section.
+ *     s = os_lock();
+ *     // Allow only one task or ISR to operate the list.
+ *     list_add(p_list, &item);
+ *     // Exit the critical section and restore ISR mask flag.
+ *     os_unlock(s);
+ * }
+ * \endcode
+ *
+ * \ingroup  Synchronization
+ */
+void os_unlock(uint32_t s);
+
+/**
+ * os_sync.h
+ *
+ * \brief   Create a counting semaphore.
+ *
+ * \details Semaphores are used to manage and protect access to shared resources. A semaphore
+ *          can be used to permit a fixed number of task to access a pool of shared resources.
+ *          Using semaphores.\n
+ *          A semaphore object should be initialized to the maximum number of available tokens.
+ *          This number of available resources is specified as parameter of the os_sem_create()
+ *          function. Each time a semaphore token is obtained with os_sem_take(), the semaphore
+ *          count is decremented. When the semaphore count is 0, no semaphore token can be obtained.
+ *          The task that tries to obtain the semaphore token needs to wait until the next token
+ *          is free. Semaphores are released with os_sem_give() incrementing the semaphore count.
+ *
+ * \image html OS-semaphore-overview.jpg "Semaphore Overview" width=496px height=346px
+ *
+ * \param[out]  pp_handle   Used to pass back the created semaphore handle.
+ *
+ * \param[in]   p_name  A descriptive name for the semaphore.
+ *
+ * \param[in]   init_count  The count value assigned to the semaphore when created.
+ *
+ * \param[in]   max_count   The maximum count value that can be reached. If the max_count is 1,
+ *                          a binary semaphore is being created.
+ *
+ * \return           The status of the semaphore creation.
+ * \retval true      Semaphore was created successfully.
+ * \retval false     Semaphore was failed to create.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * int test(void)
+ * {
+ *     void *p_handle;
+ *
+ *     // Create a semaphore with initial value 0 and maximum value 10.
+ *     if (os_sem_create(&p_handle, "sem name", 0, 10) == true)
+ *     {
+ *         // Semaphore created successfully.
+ *     }
+ *     else
+ *     {
+ *         // Semaphore failed to create.
+ *         return -1;
+ *     }
+ *
+ *     return 0;
+ * }
+ * \endcode
+ *
+ * \ingroup  Synchronization
+ */
+bool os_sem_create(void **pp_handle, const char *p_name, uint32_t init_count,
+                   uint32_t max_count);
+
+/**
+ * os_sync.h
+ *
+ * \brief   Delete a semaphore.
+ *
+ * \param[in]   p_handle    The handle of the semaphore to be deleted.
+ *
+ * \return           The status of the semaphore deletion.
+ * \retval true      Semaphore was deleted successfully.
+ * \retval false     Semaphore was failed to delete.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * int test(void)
+ * {
+ *     void *p_handle;
+ *
+ *     // Create a semaphore with initial value 0 and maximum value 10.
+ *     if (os_sem_create(&p_handle, "sem name", 0, 10) == true)
+ *     {
+ *         // Semaphore created successfully.
+ *     }
+ *     else
+ *     {
+ *         // Semaphore failed to create.
+ *         return -1;
+ *     }
+ *
+ *     // Delete the created semaphore.
+ *     os_sem_delete(p_handle);
+ *
+ *     return 0;
+ * }
+ * \endcode
+ *
+ * \ingroup  Synchronization
+ */
+bool os_sem_delete(void *p_handle);
+
+/**
+ * os_sync.h
+ *
+ * \brief   Take a semaphore.
+ *
+ * \param[in]   p_handle    The handle of the semaphore to be taken.
+ *
+ * \param[in]   wait_ms     The time in milliseconds to wait for the semaphore to become
+ *                          available.
+ * \arg \c 0           No blocking and return immediately.
+ * \arg \c 0xFFFFFFFF  Block infinitely until the semaphore taken.
+ * \arg \c others      The timeout value in milliseconds.
+ *
+ * \return           The status of the semaphore taking.
+ * \retval true      Semaphore was taken successfully.
+ * \retval false     Semaphore was failed to take.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * void *p_handle = NULL;
+ *
+ * // One task creates a semaphore.
+ * void task1(void *p_param)
+ * {
+ *     // Create a full binary semaphore.
+ *     os_sem_create(&p_handle, "sem name", 1, 1);
+ * }
+ *
+ * // Anohter task uses the semaphore.
+ * void task2(void *p_param)
+ * {
+ *     // See if we can obtain the semaphore. If the semaphore is
+ *     // not available, wait for 100ms.
+ *     if (os_sem_take(p_handle, 100) == true)
+ *     {
+ *         // Access the share resource.
+ *
+ *         // Finish accessing the share resource, then release the semaphore.
+ *         os_sem_give(p_handle);
+ *     }
+ *     else
+ *     {
+ *         // Could not access the share resource.
+ *     }
+ * }
+ * \endcode
+ *
+ * \ingroup  Synchronization
+ */
+bool os_sem_take(void *p_handle, uint32_t wait_ms);
+
+/**
+ * os_sync.h
+ *
+ * \brief   Give a semaphore.
+ *
+ * \param[in]   p_handle    The handle of the semaphore to be given.
+ *
+ * \return           The status of the semaphore giving.
+ * \retval true      Semaphore was given successfully.
+ * \retval false     Semaphore was failed to give.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * int test(void)
+ * {
+ *     void *p_handle = NULL;
+ *
+ *     // Create an empty binary semaphore.
+ *     os_sem_create(&p_handle, "sem name", 0, 1);
+ *
+ *     // Obtaining the empty semaphore immediately will be failed.
+ *     if (os_sem_take(p_handle, 0) == false)
+ *     {
+ *         // Failed.
+ *     }
+ *
+ *     // Give the sempahore
+ *     if (os_sem_give(p_hanel) == true)
+ *     {
+ *         // Now we can take the semaphore.
+ *         os_sem_take(p_handle, 0);
+ *
+ *         // Again taking the binary semaphore will be failed.
+ *         os_sem_take(p_handle, 0);
+ *     }
+ * }
+ * \endcode
+ *
+ * \ingroup  Synchronization
+ */
+bool os_sem_give(void *p_handle);
+
+/**
+ * os_sync.h
+ *
+ * \brief   Create a mutex.
+ *
+ * \details Mutex (Mutual Exclusion) is used to protect a shared resource that can be accessed
+ *          only by one task at a time.\n
+ *          A mutex is a special version of a binary empty semaphore. The advantage of a mutex
+ *          is that it introduces task ownership. When a task acquires a mutex and becomes its
+ *          owner, subsequent mutex acquires from that task will succeed immediately. Thus, mutex
+ *          acquires/releases can be nested.\n
+ *
+ * \image html OS-mutex-overview.jpg "Mutex Overview" width=451px height=196px
+ *
+ * \param[out]  pp_handle   Used to pass back the created mutex handle.
+ *
+ * \return           The status of the mutex creation.
+ * \retval true      Mutex was created successfully.
+ * \retval false     Mutex was failed to create.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * int test(void)
+ * {
+ *     void *p_handle = NULL;
+ *
+ *     // Create a mutex.
+ *     if (os_mutex_create(&p_handle) == true)
+ *     {
+ *         // The mutex created successfully.
+ *         // Now it can be used.
+ *     }
+ * }
+ * \endcode
+ *
+ * \ingroup  Synchronization
+ */
+bool os_mutex_create(void **pp_handle);
+
+/**
+ * os_sync.h
+ *
+ * \brief   Delete a mutex.
+ *
+ * \param[in]   p_handle    The handle of the mutex to be deleted.
+ *
+ * \return           The status of the Mutex deletion.
+ * \retval true      Mutex was deleted successfully.
+ * \retval false     Mutex was failed to delete.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * int test(void)
+ * {
+ *     void *p_handle;
+ *
+ *     // Create a mutex.
+ *     if (os_mutex_create(&p_handle) == true)
+ *     {
+ *         // Mutex created successfully.
+ *     }
+ *     else
+ *     {
+ *         // Mutex failed to create.
+ *         return -1;
+ *     }
+ *
+ *     // Delete the created mutex.
+ *     os_mutex_delete(p_handle);
+ *
+ *     return 0;
+ * }
+ * \endcode
+ *
+ * \ingroup  Synchronization
+ */
+bool os_mutex_delete(void *p_handle);
+
+/**
+ * os_sync.h
+ *
+ * \brief   Take a mutex.
+ *
+ * \param[in]   p_handle    The handle of the mutex to be taken.
+ *
+ * \param[in]   wait_ms     The time in milliseconds to wait for the mutex to become
+ *                          available.
+ * \arg \c 0           No blocking and return immediately.
+ * \arg \c 0xFFFFFFFF  Block infinitely until the mutex taken.
+ * \arg \c others      The timeout value in milliseconds.
+ *
+ * \return           The status of the mutex taking.
+ * \retval true      Mutex was taken successfully.
+ * \retval false     Mutex was failed to take.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * void *p_handle = NULL;
+ *
+ * // One task creates a mutex.
+ * void task1(void *p_param)
+ * {
+ *     // Create a mutex.
+ *     os_mutex_create(&p_handle);
+ * }
+ *
+ * // Anohter task uses the mutex.
+ * void task2(void *p_param)
+ * {
+ *     // See if we can obtain the mutex. If the mutex is
+ *     // not available, wait for 100ms.
+ *     if (os_mutex_take(p_handle, 100) == true)
+ *     {
+ *         // Access the share resource.
+ *
+ *         // In real code, recursive calls of mutex may occur.
+ *         os_mutex_take(p_handle, 100);
+ *         os_mutex_take(p_handle, 200);
+ *
+ *         // The mutex has now been 'taken' three times, so will not be
+ *         // available to another task until it has also been given back
+ *         // three times.
+ *         os_mutex_give(p_handle);
+ *         os_mutex_give(p_handle);
+ *         os_mutex_give(p_handle);
+ *
+ *         // Finish accessing the share resource, then release the semaphore.
+ *         // Now the mutex can be taken by other tasks.
+ *     }
+ *     else
+ *     {
+ *         // Could not access the share resource.
+ *     }
+ * }
+ * \endcode
+ *
+ * \ingroup  Synchronization
+ */
+bool os_mutex_take(void *p_handle, uint32_t wait_ms);
+
+/**
+ * os_sync.h
+ *
+ * \brief   Give a mutex.
+ *
+ * \param[in]   p_handle    The handle of the mutex to be given.
+ *
+ * \return           The status of the mutex giving.
+ * \retval true      Mutex was given successfully.
+ * \retval false     Mutex was failed to give.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * void *p_handle = NULL;
+ *
+ * // One task creates a mutex.
+ * void task1(void *p_param)
+ * {
+ *     // Create a mutex.
+ *     os_mutex_create(&p_handle);
+ * }
+ *
+ * // Anohter task uses the mutex.
+ * void task2(void *p_param)
+ * {
+ *     // See if we can obtain the mutex. If the mutex is
+ *     // not available, wait for 100ms.
+ *     if (os_mutex_take(p_handle, 100) == true)
+ *     {
+ *         // Access the share resource.
+ *
+ *         // In real code, recursive calls of mutex may occur.
+ *         os_mutex_take(p_handle, 100);
+ *         os_mutex_take(p_handle, 200);
+ *
+ *         // The mutex has now been 'taken' three times, so will not be
+ *         // available to another task until it has also been given back
+ *         // three times.
+ *         os_mutex_give(p_handle);
+ *         os_mutex_give(p_handle);
+ *         os_mutex_give(p_handle);
+ *
+ *         // Finish accessing the share resource, then release the semaphore.
+ *         // Now the mutex can be taken by other tasks.
+ *     }
+ *     else
+ *     {
+ *         // Could not access the share resource.
+ *     }
+ * }
+ * \endcode
+ *
+ * \ingroup  Synchronization
+ */
+bool os_mutex_give(void *p_handle);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _OS_SYNC_H_ */
diff --git a/bee/os/osif/inc/rtl87x2j/os_task.h b/bee/os/osif/inc/rtl87x2j/os_task.h
new file mode 100644
index 00000000..eaee1fd8
--- /dev/null
+++ b/bee/os/osif/inc/rtl87x2j/os_task.h
@@ -0,0 +1,555 @@
+/*
+ * Copyright (c) 2015, Realtek Semiconductor Corporation. All rights reserved.
+ */
+
+#ifndef _OS_TASK_H_
+#define _OS_TASK_H_
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup    Task    Task Management
+ *
+ * \brief   Define, create, and control task functions.
+ * \details The Task Management function group allows to create, delete, and control tasks
+ *          in the system.\n
+ * Tasks can be in the following states:\n
+ * \arg <b>RUNNING:</b> The task that is currently running is in the <b>RUNNING</b> state.
+ *                      Only one task at a time can be in this state.
+ * \arg <b>READY:</b> Tasks which are ready to run are in the <b>READY</b> state. Once the
+ *                    <b>RUNNING</b> task has terminated or is <b>WAITING</b>, the next
+ *                    <b>READY</b> task with the highest priority becomes the <b>RUNNING</b> task.
+ * \arg <b>WAITING:</b> Tasks that are waiting for an event to occur are in the WAITING state.
+ * \arg <b>INACTIVE</b>: Tasks that are not created or terminated are in the <b>INACTIVE</b> state.
+ *                       These Tasks typically consume no system resources.
+ *
+ * \image html OS-task-state-transition.jpg "Task State Transition" width=526px height=526px
+ *
+ */
+
+bool os_alloc_secure_ctx(uint32_t stack_size);
+
+/**
+ * os_task.h
+ *
+ * \brief Create a new task and add it to the list of tasks that are ready to run.
+ *
+ * \param[out]  pp_handle  Used to pass back a handle by which the created task
+ *                         can be referenced.
+ *
+ * \param[in]   p_name     A descriptive name for the task.
+ *
+ * \param[in]   p_routine  Pointer to task routine function that must be implemented
+ *                         to never return.
+ *
+ * \param[in]   p_param    Pointer parameter passed to the task routine function.
+ *
+ * \param[in]   stack_size The size of the task stack that is specified as the number
+ *                         of bytes.
+ *
+ * \param[in]   priority   The priority at which the task should run. Higher priority
+ *                         task has higher priority value.
+ *
+ * \return           The status of the task creation.
+ * \retval true      Task was created successfully and added to task ready list.
+ * \retval false     Task was failed to create.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * // Task routine implementation.
+ * void task_routine(void *p_param)
+ * {
+ *     for (;;)
+ *     {
+ *          // Task code goes here.
+ *     }
+ * }
+ *
+ * // Task to be created.
+ * int test(void)
+ * {
+ *     void *p_handle = NULL;
+ *     uint32_t task_param;
+ *
+ *     if (os_task_create(&p_handle, "task", task_routine,
+ *                        &task_param, STACK_SIZE, TASK_PRIORITY) == true)
+ *     {
+ *         // Task created successfully.
+ *     }
+ *     else
+ *     {
+ *         // Task failed to create.
+ *         return -1;
+ *     }
+ *
+ *     // Use the handle to delete the task.
+ *     os_task_delete(p_handle);
+ *
+ *     return 0;
+ * }
+ * \endcode
+ *
+ * \ingroup  Task
+ */
+bool os_task_create(void **pp_handle, const char *p_name, void (*p_routine)(void *),
+                    void *p_param, uint16_t stack_size, uint16_t priority);
+
+/**
+ * os_task.h
+ *
+ * \brief Remove a task from RTOS's task management. The task being deleted will be removed
+ * from RUNNING, READY or WAITING state.
+ *
+ * \param[in] p_handle  The handle of the task to be deleted.
+ *
+ * \return           The status of the task deletion.
+ * \retval true      Task was deleted successfully.
+ * \retval false     Task was failed to delete.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * // Task routine implementation.
+ * void task_routine(void *p_param)
+ * {
+ *     for (;;)
+ *     {
+ *          // Task code goes here.
+ *     }
+ * }
+ *
+ * // Task to be created and deleted.
+ * int test(void)
+ * {
+ *     void *p_handle = NULL;
+ *     uint32_t task_param;
+ *
+ *     if (os_task_create(&p_handle, "task", task_routine,
+ *                        &task_param, STACK_SIZE, TASK_PRIORITY) == true)
+ *     {
+ *         // Task created successfully.
+ *     }
+ *     else
+ *     {
+ *         // Task failed to create.
+ *         return -1;
+ *     }
+ *
+ *     // Use the handle to delete the task.
+ *     os_task_delete(p_handle);
+ *
+ *     return 0;
+ * }
+ * \endcode
+ *
+ * \ingroup  Task
+ */
+bool os_task_delete(void *p_handle);
+
+/**
+ * os_task.h
+ *
+ * \brief Suspend the task. The suspended task will not be scheduled and never get
+ * any microcontroller processing time.
+ *
+ * \param[in] p_handle  The handle of the task to be suspended.
+ *
+ * \return           The status of the task suspension.
+ * \retval true      Task was suspended successfully.
+ * \retval false     Task was failed to suspend.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * // Task routine implementation.
+ * void task_routine(void *p_param)
+ * {
+ *     for (;;)
+ *     {
+ *          // Task code goes here.
+ *     }
+ * }
+ *
+ * // Task to be created and suspended.
+ * int test(void)
+ * {
+ *     void *p_handle = NULL;
+ *     uint32_t task_param;
+ *
+ *     if (os_task_create(&p_handle, "task", task_routine,
+ *                        &task_param, STACK_SIZE, TASK_PRIORITY) == true)
+ *     {
+ *         // Task created successfully.
+ *     }
+ *     else
+ *     {
+ *         // Task failed to create.
+ *         return -1;
+ *     }
+ *
+ *     // Use the handle to suspend the created task.
+ *     os_task_suspend(p_handle);
+ *
+ *     return 0;
+ * }
+ * \endcode
+ *
+ * \ingroup  Task
+ */
+bool os_task_suspend(void *p_handle);
+
+/**
+ * os_task.h
+ *
+ * \brief Resume the suspended task.
+ *
+ * \param[in] p_handle  The handle of the task to be resumed.
+ *
+ * \return           The status of the task resume.
+ * \retval true      Task was resumed successfully.
+ * \retval false     Task was failed to resume.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * // Task routine implementation.
+ * void task_routine(void *p_param)
+ * {
+ *     for (;;)
+ *     {
+ *          // Task code goes here.
+ *     }
+ * }
+ *
+ * // Task to be suspended and resumed.
+ * int test(void)
+ * {
+ *     void *p_handle = NULL;
+ *     uint32_t task_param;
+ *
+ *     if (os_task_create(&p_handle, "task", task_routine,
+ *                        &task_param, STACK_SIZE, TASK_PRIORITY) == true)
+ *     {
+ *         // Task created successfully.
+ *     }
+ *     else
+ *     {
+ *         // Task failed to create.
+ *         return -1;
+ *     }
+ *
+ *     // Use the handle to suspend the created task.
+ *     os_task_suspend(p_handle);
+ *
+ *     // Resume the suspended task by ourselves.
+ *     os_task_resume(p_handle);
+ *     return 0;
+ * }
+ * \endcode
+ *
+ * \ingroup  Task
+ */
+bool os_task_resume(void *p_handle);
+
+/**
+ * os_task.h
+ *
+ * \brief Force a context swith and pass control to the next task that is in
+ * READY state.
+ *
+ * \param None
+ *
+ * \return           The status of the task resume.
+ * \retval true      Task was yielded successfully.
+ * \retval false     Task was failed to yield.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * // Task routine implementation.
+ * void task_routine(void *p_param)
+ * {
+ *     for (;;)
+ *     {
+ *          // Force a context switch
+ *          os_task_yield();
+ *     }
+ * }
+ *
+ * // Task to be created.
+ * int test(void)
+ * {
+ *     void *p_handle = NULL;
+ *     uint32_t task_param;
+ *
+ *     if (os_task_create(&p_handle, "task", task_routine,
+ *                        &task_param, STACK_SIZE, TASK_PRIORITY) == true)
+ *     {
+ *         // Task created successfully.
+ *     }
+ *     else
+ *     {
+ *         // Task failed to create.
+ *         return -1;
+ *     }
+ *
+ *     return 0;
+ * }
+ * \endcode
+ *
+ * \ingroup  Task
+ */
+bool os_task_yield(void);
+
+/**
+ * os_task.h
+ *
+ * \brief Get the handle of the current running task.
+ *
+ * \param[out] pp_handle  Used to pass back a handle by which the current task
+ *                        can be referenced.
+ *
+ * \return           The status of getting the current task handle.
+ * \retval true      Task handle was got successfully.
+ * \retval false     Task handle was failed to get.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * // Get current task handle.
+ * int test(void)
+ * {
+ *     void *p_handle = NULL;
+ *
+ *     os_task_handle_get(&p_handle);
+ *
+ *     return 0;
+ * }
+ * \endcode
+ *
+ * \ingroup  Task
+ */
+bool os_task_handle_get(void **pp_handle);
+
+/**
+ * os_task.h
+ *
+ * \brief Get the priority of the specified task.
+ *
+ * \param[in] p_handle    The handle of the task to be queried. Passing a NULL handle
+ *                        means querying the priority of the current task.
+ *
+ * \param[out] p_priority Used to pass back the priority of the task.
+ *
+ * \return           The status of getting the task priority.
+ * \retval true      Task priority was got successfully.
+ * \retval false     Task priority was failed to get.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * int test(void)
+ * {
+ *     void *p_handle = NULL;
+ *     uint16_t priority;
+ *
+ *     if (os_task_create(&p_handle, "task", task_routine,
+ *                        NULL, STACK_SIZE, TASK_PRIORITY) == true)
+ *     {
+ *         // Task created successfully.
+ *     }
+ *     else
+ *     {
+ *         // Task failed to create.
+ *         return -1;
+ *     }
+ *
+ *     // Get the task priority.
+ *     os_task_priority_get(p_handle, &priority);
+ *
+ *     return 0;
+ * }
+ * \endcode
+ *
+ * \ingroup  Task
+ */
+bool os_task_priority_get(void *p_handle, uint16_t *p_priority);
+
+/**
+ * os_task.h
+ *
+ * \brief Set the priority of the specified task.
+ *
+ * \param[in] p_handle  The handle of the task for which the priority is being set.
+ *                      Passing a NULL handle means setting the priority of the
+ *                      current task.
+ *
+ * \param[in] priority  The priority to which the task will be set.
+ *
+ * \return           The status of setting the task priority.
+ * \retval true      Task priority was set successfully.
+ * \retval false     Task priority was failed to set.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * int test(void)
+ * {
+ *     void *p_handle = NULL;
+ *     uint16_t priority;
+ *
+ *     if (os_task_create(&p_handle, "task", task_routine,
+ *                        NULL, STACK_SIZE, TASK_PRIORITY) == true)
+ *     {
+ *         // Task created successfully.
+ *     }
+ *     else
+ *     {
+ *         // Task failed to create.
+ *         return -1;
+ *     }
+ *
+ *     // Use the handle to raise the created task priority.
+ *     os_task_priority_set(p_handle, TASK_PRIORITY + 1);
+ *
+ *     // Use a NULL handle to raise the current task priority.
+ *     os_task_priority_set(NULL, TASK_PRIORITY + 1);
+ *
+ *     return 0;
+ * }
+ * \endcode
+ *
+ * \ingroup  Task
+ */
+bool os_task_priority_set(void *p_handle, uint16_t priority);
+
+/**
+ * os_task.h
+ *
+ * \brief Send a notification signal to the specified task.
+ *
+ * The notification signal sent to a task will remain pending until it is
+ * cleared by the task calling os_task_signal_recv(). If the task was already
+ * in the WAITING state to wait for the singal, then the task will be removed
+ * from WAITING state and the signal cleared.
+ *
+ * \param[in] p_handle  The handle of the task to which the signal is sent.
+ *
+ * \param[in] signal    The signal to be sent.
+ *
+ * \return          The status of sending the signal.
+ * \retval true     Task signal was sent successfully.
+ * \retval false    Task signal was failed to send.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * int test(void)
+ * {
+ *     void *p_handle = NULL;
+ *     uint32_t signal;
+ *
+ *     if (os_task_create(&p_handle, "task", task_routine,
+ *                        NULL, STACK_SIZE, TASK_PRIORITY) == true)
+ *     {
+ *         // Task created successfully.
+ *     }
+ *     else
+ *     {
+ *         // Task failed to create.
+ *         return -1;
+ *     }
+ *
+ *     // Send signal to the created task.
+ *     singal = 1;
+ *     os_task_signal_send(p_handle, signal);
+ *
+ *     return 0;
+ * }
+ * \endcode
+ *
+ * \ingroup  Task
+ */
+bool os_task_signal_send(void *p_handle, uint32_t signal);
+
+/**
+ * os_task.h
+ *
+ * \brief Wait for a notification signal.
+ *
+ * \param[out] p_signal Used to pass back the received signal.
+ *
+ * \param[in] wait_ms   The timeout in milliseconds to wait for the signal.
+ * \arg \c 0            No blocking and return immediately.
+ * \arg \c 0xFFFFFFFF   Block infinitely until the signal received.
+ * \arg \c others       The timeout value in milliseconds.
+ *
+ * \return          The status of receiving the signal.
+ * \retval true     Task signal was received successfully.
+ * \retval false    Task signal was failed to receive.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * int test(void)
+ * {
+ *     uint32_t signal;
+ *
+ *     // Block to wait for the signal sent from other tasks.
+ *     os_task_signal_recv(&signal, 0xFFFFFFFF);
+ *
+ *     return 0;
+ * }
+ * \endcode
+ *
+ * \ingroup  Task
+ */
+bool os_task_signal_recv(uint32_t *p_signal, uint32_t wait_ms);
+
+/**
+ * os_task.h
+ *
+ * \brief Clear the signal of the specified task.
+ *
+ * \param[in] p_handle  The handle of the task to which the signal is clear.
+ *
+ * \return          The status of clearing the signal.
+ * \retval true     Task signal was cleared successfully.
+ * \retval false    Task signal was failed to clear.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * int test(void)
+ * {
+ *     void *p_handle = NULL;
+ *     uint32_t signal;
+ *
+ *     if (os_task_create(&p_handle, "task", task_routine,
+ *                        NULL, STACK_SIZE, TASK_PRIORITY) == true)
+ *     {
+ *         // Task created successfully.
+ *     }
+ *     else
+ *     {
+ *         // Task failed to create.
+ *         return -1;
+ *     }
+ *
+ *     // Send signal to the created task.
+ *     singal = 1;
+ *     os_task_signal_send(p_handle, signal);
+ *
+ *     // Clear signal of the created task.
+ *     os_task_signal_clear(p_handle);
+ *
+ *     return 0;
+ * }
+ * \endcode
+ *
+ * \ingroup  Task
+ */
+bool os_task_signal_clear(void *p_handle);
+
+void os_task_status_dump(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _OS_TASK_H_ */
diff --git a/bee/os/osif/inc/rtl87x2j/os_timer.h b/bee/os/osif/inc/rtl87x2j/os_timer.h
new file mode 100644
index 00000000..c5407dba
--- /dev/null
+++ b/bee/os/osif/inc/rtl87x2j/os_timer.h
@@ -0,0 +1,473 @@
+/*
+ * Copyright (c) 2015, Realtek Semiconductor Corporation. All rights reserved.
+ */
+
+#ifndef _OS_TIMER_H_
+#define _OS_TIMER_H_
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup    Timer   Timer Management
+ *
+ * \brief   Create and control software timer and timer callback functions.
+ * \details The Timer Management function group allows to create, delete, and control software
+ *          timers in the system. The software timers can be configured as one-short or periodic
+ *          timers. When a timer expires, a callback function associated with the timer is
+ *          executed.\n
+ * Timers can be in the following two states:\n
+ * \arg <b>Dormant</b> The timer first enters <b>Dormant</b> or <b>Inactive</b> state when created.
+ *                     If a one-short timer expires but not restarts yet, or is stopped the timer
+ *                     will be tranformed from <b>Active</b> state into <b>Dormant</b> state.
+ * \arg <b>Active</b> The timer enters <b>Active</b> state If the timer starts or restarts. When
+ *                    expired, the callback function associcated with the timer will be executed.
+ *
+ * \image html OS-timer-state-transition.jpg "Software Timer State Transition" width=617px height=321px
+ *
+ */
+
+
+/**
+ * os_timer.h
+ *
+ * \brief    Get the ID assigned to the timer when created.
+ *
+ * \param[in]   pp_handle   Pointer to the created timer handle.
+ *
+ * \param[out]  p_timer_id  Used to pass back the ID assigned to the timer.
+ *
+ * \return           The status of the timer id getting.
+ * \retval true      Timer ID was got successfully.
+ * \retval false     Timer ID was failed to get.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * // Timer callback function.
+ * void timer_callback(void *p_handle)
+ * {
+ *     uint32_t timer_id;
+ *
+ *     // Which timer expired?
+ *     os_timer_id_get(&p_handle, &timer_id);
+ *
+ *     if (timer_id == TIMER_ID)
+ *     {
+ *          // Delete the specified timer.
+ *          os_timer_delete(&p_handle);
+ *     }
+ * }
+ *
+ * #define TIMER_ID 1
+ *
+ * // Timer to be created.
+ * int test(void)
+ * {
+ *     void *p_handle = NULL;
+ *
+ *     if (os_timer_create(&p_handle, "timer", TIMER_ID,
+ *                        INTERVAL_MS, false, timer_callback) == true)
+ *     {
+ *         // Timer created successfully, start the timer.
+ *         os_timer_start(&p_handle);
+ *     }
+ *     else
+ *     {
+ *         // Timer failed to create.
+ *         return -1;
+ *     }
+ *
+ *     return 0;
+ * }
+ * \endcode
+ *
+ * \ingroup  Timer
+ */
+bool os_timer_id_get(void **pp_handle, uint32_t *p_timer_id);
+
+/**
+ * os_timer.h
+ *
+ * \brief   Create a new software timer instance. This allocates the storage required by
+ *          the new timer, initializes the new timers internal state, and returns a handle
+ *          by which the new timer can be referenced.
+ *
+ * \param[out]  pp_handle        Used to pass back a handle by which the created timer
+ *                               can be referenced.
+ *
+ * \param[in]   p_timer_name     A descriptive name for the timer.
+ *
+ * \param[in]   timer_id         An identifier that is assigned to the timer being created.
+ *                               Typically this would be used in the timer callback function to
+ *                               identify which timer expired when the same callback function is
+ *                               assigned to more than one timer.
+ *
+ * \param[in]   interval_ms      The timer period in milliseconds.
+ *
+ * \param[in]   reload           Used to set the timer as a periodic or one-shot timer.
+ * \arg \c      true             Create a periodic timer.
+ * \arg \c      false            Create a one-shot timer.
+ *
+ * \param[in]   p_timer_callback The function to call when the timer expires. Callback functions
+ *                               must have the prototype defined as 'void callback(void *)'.
+ *
+ * \return           The status of the timer creation.
+ * \retval true      Timer was created successfully.
+ * \retval false     Timer was failed to create.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * // Timer callback function.
+ * void timer_callback(void *p_handle)
+ * {
+ *     uint32_t timer_id;
+ *
+ *     // Which timer expired?
+ *     os_timer_id_get(&p_handle, &timer_id);
+ *
+ *     if (timer_id == TIMER_ID)
+ *     {
+ *          // Delete the specified timer.
+ *          os_timer_delete(&p_handle);
+ *     }
+ * }
+ *
+ * #define TIMER_ID 1
+ *
+ * // Timer to be created.
+ * int test(void)
+ * {
+ *     void *p_handle = NULL;
+ *
+ *     if (os_timer_create(&p_handle, "timer", TIMER_ID,
+ *                        INTERVAL_MS, false, timer_callback) == true)
+ *     {
+ *         // Timer created successfully, start the timer.
+ *         os_timer_start(&p_handle);
+ *     }
+ *     else
+ *     {
+ *         // Timer failed to create.
+ *         return -1;
+ *     }
+ *
+ *     return 0;
+ * }
+ * \endcode
+ *
+ * \ingroup  Timer
+ */
+bool os_timer_create(void **pp_handle, const char *p_timer_name, uint32_t timer_id,
+                     uint32_t interval_ms, bool reload, void (*p_timer_callback)(void *));
+
+/**
+ * os_timer.h
+ *
+ * \brief    Start a timer that was previously created using the os_timer_create() API
+ *           function. If the timer had already been started and was in the active state,
+ *           then os_timer_create() has equivalent functionality to the os_timer_create()
+ *           API function.
+ *
+ * \param[in] pp_handle Pointer to the created timer handle.
+ *
+ * \return           The status of the timer starting.
+ * \retval true      Timer was started successfully.
+ * \retval false     Timer was failed to start.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * // Timer callback function.
+ * void timer_callback(void *p_handle)
+ * {
+ *     uint32_t timer_id;
+ *
+ *     // Which timer expired?
+ *     os_timer_id_get(&p_handle, &timer_id);
+ *
+ *     if (timer_id == TIMER_ID)
+ *     {
+ *          // Delete the specified timer.
+ *          os_timer_delete(&p_handle);
+ *     }
+ * }
+ *
+ * #define TIMER_ID 1
+ *
+ * // Timer to be created.
+ * int test(void)
+ * {
+ *     void *p_handle = NULL;
+ *
+ *     if (os_timer_create(&p_handle, "timer", TIMER_ID,
+ *                        INTERVAL_MS, false, timer_callback) == true)
+ *     {
+ *         // Timer created successfully, start the timer.
+ *         os_timer_start(&p_handle);
+ *     }
+ *     else
+ *     {
+ *         // Timer failed to create.
+ *         return -1;
+ *     }
+ *
+ *     return 0;
+ * }
+ * \endcode
+ *
+ * \ingroup  Timer
+ */
+bool os_timer_start(void **pp_handle);
+
+/**
+ * os_timer.h
+ *
+ * \brief     Restart a timer that was previously created using the os_timer_create() API
+ *            function. If the timer had already been started and was already in the active
+ *            state, then os_timer_start() will cause the timer to re-evaluate its expiry
+ *            time so that it is relative to when os_timer_start() was called. If the timer
+ *            was in the dormant state then os_timer_start() has equivalent functionality to
+ *            the os_timer_start() API function.
+ *
+ * \param[in] pp_handle     Pointer to the created timer handle.
+ *
+ * \param[in] interval_ms   The timer period in milliseconds.
+ *
+ * \return           The status of the timer restarting.
+ * \retval true      Timer was restarted successfully.
+ * \retval false     Timer was failed to restart.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * // Timer callback function.
+ * void timer_callback(void *p_handle)
+ * {
+ *     uint32_t timer_id;
+ *
+ *     // Which timer expired?
+ *     os_timer_id_get(&p_handle, &timer_id);
+ *
+ *     if (timer_id == TIMER_ID)
+ *     {
+ *          // Restart the specified timer.
+ *          os_timer_restart(&p_handle);
+ *     }
+ * }
+ *
+ * #define TIMER_ID 1
+ *
+ * // Timer to be created.
+ * int test(void)
+ * {
+ *     void *p_handle = NULL;
+ *
+ *     if (os_timer_create(&p_handle, "timer", TIMER_ID,
+ *                        INTERVAL_MS, false, timer_callback) == true)
+ *     {
+ *         // Timer created successfully, start the timer.
+ *         os_timer_start(&p_handle);
+ *     }
+ *     else
+ *     {
+ *         // Timer failed to create.
+ *         return -1;
+ *     }
+ *
+ *     return 0;
+ * }
+ * \endcode
+ *
+ * \ingroup  Timer
+ */
+bool os_timer_restart(void **pp_handle, uint32_t interval_ms);
+
+/**
+ * os_timer.h
+ *
+ * \brief     Stop a timer that was previously started using either of the os_timer_start(),
+ *            os_timer_restart() API functions. Stopping a timer ensures the timer is not in
+ *            the active state.
+ *
+ * \param[in] pp_handle Pointer to the handle of timer being stopped.
+ *
+ * \return           The status of the timer stopping.
+ * \retval true      Timer was stopped successfully.
+ * \retval false     Timer was failed to stop.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * // Timer callback function.
+ * void timer_callback(void *p_handle)
+ * {
+ *     uint32_t timer_id;
+ *
+ *     // Which timer expired?
+ *     os_timer_id_get(&p_handle, &timer_id);
+ *
+ *     if (timer_id == TIMER_ID)
+ *     {
+ *          // Delete the specified timer.
+ *          os_timer_delete(&p_handle);
+ *     }
+ * }
+ *
+ * #define TIMER_ID 1
+ *
+ * // Timer to be created and stopped.
+ * int test(void)
+ * {
+ *     void *p_handle = NULL;
+ *
+ *     if (os_timer_create(&p_handle, "timer", TIMER_ID,
+ *                        INTERVAL_MS, false, timer_callback) == true)
+ *     {
+ *         // Timer created successfully, start the timer.
+ *         os_timer_start(&p_handle);
+ *     }
+ *     else
+ *     {
+ *         // Timer failed to create.
+ *         return -1;
+ *     }
+ *
+ *     // Stop the timer before expiration.
+ *     os_timer_stop(&p_handle);
+ *
+ *     return 0;
+ * }
+ * \endcode
+ *
+ * \ingroup  Timer
+ */
+bool os_timer_stop(void **pp_handle);
+
+/**
+ * os_timer.h
+ *
+ * \brief      Delete a timer that was previously created using the os_timer_create()
+ *             API function.
+ *
+ * \param[in] pp_handle Pointer to the handle of timer being deleted.
+ *
+ * \return           The status of the timer deletion.
+ * \retval true      Timer was deleted successfully.
+ * \retval false     Timer was failed to delete.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * // Timer callback function.
+ * void timer_callback(void *p_handle)
+ * {
+ *     uint32_t timer_id;
+ *
+ *     // Which timer expired?
+ *     os_timer_id_get(&p_handle, &timer_id);
+ *
+ *     if (timer_id == TIMER_ID)
+ *     {
+ *          // Delete the specified timer.
+ *          os_timer_delete(&p_handle);
+ *     }
+ * }
+ *
+ * #define TIMER_ID 1
+ *
+ * // Timer to be created and deleted.
+ * int test(void)
+ * {
+ *     void *p_handle = NULL;
+ *
+ *     if (os_timer_create(&p_handle, "timer", TIMER_ID,
+ *                        INTERVAL_MS, false, timer_callback) == true)
+ *     {
+ *         // Timer created successfully, start the timer.
+ *         os_timer_start(&p_handle);
+ *     }
+ *     else
+ *     {
+ *         // Timer failed to create.
+ *         return -1;
+ *     }
+ *
+ *     return 0;
+ * }
+ * \endcode
+ *
+ * \ingroup  Timer
+ */
+bool os_timer_delete(void **pp_handle);
+
+/**
+ * os_timer.h
+ *
+ * \brief      Dump all current used timers in system.
+ *
+ * \param None
+ *
+ * \return           The status of the timer dump.
+ * \retval true      Timer was dumped successfully.
+ * \retval false     Timer was failed to dump.
+ *
+ * <b>Example usage</b>
+ * \code{.c}
+ * // Timer callback function.
+ * void timer_callback(void *p_handle)
+ * {
+ *     uint32_t timer_id;
+ *
+ *     // Which timer expired?
+ *     os_timer_id_get(&p_handle, &timer_id);
+ *
+ *     if (timer_id == TIMER_ID)
+ *     {
+ *          // Delete the specified timer.
+ *          os_timer_delete(&p_handle);
+ *     }
+ * }
+ *
+ * #define TIMER_ID 1
+ *
+ * // Timer to be created and dumped.
+ * int test(void)
+ * {
+ *     void *p_handle = NULL;
+ *
+ *     if (os_timer_create(&p_handle, "timer", TIMER_ID,
+ *                        INTERVAL_MS, false, timer_callback) == true)
+ *     {
+ *         // Timer created successfully, start the timer.
+ *         os_timer_start(&p_handle);
+ *     }
+ *     else
+ *     {
+ *         // Timer failed to create.
+ *         return -1;
+ *     }
+ *
+ *     // Dump all used timers.
+ *     os_timer_dump();
+ *
+ *     return 0;
+ * }
+ * \endcode
+ *
+ * \ingroup  Timer
+ */
+bool os_timer_pend_function_call(void (*p_pend_function)(void *, uint32_t),
+                                 void *pvParameter1, uint32_t ulParameter2);
+
+bool os_timer_auto_reload_get(void **pp_handle, long *p_autoreload);
+bool os_timer_state_get(void **pp_handle, uint32_t *p_timer_state);
+bool os_timer_handle_get(uint8_t timer_idx, void **pp_timer_handle);
+extern uint32_t (*patch_os_timer_max_num_get)(uint32_t *p_result);
+bool os_timer_dump(void);
+void os_timer_init(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _OS_TIMER_H_ */
diff --git a/bee/os/osif/inc/rtl87x2j/osif.h b/bee/os/osif/inc/rtl87x2j/osif.h
new file mode 100644
index 00000000..ba4a59b9
--- /dev/null
+++ b/bee/os/osif/inc/rtl87x2j/osif.h
@@ -0,0 +1,147 @@
+/*
+ * Copyright (c) 2015, Realsil Semiconductor Corporation. All rights reserved.
+ */
+
+#ifndef _OSIF_H_
+#define _OSIF_H_
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <stddef.h>
+#include "cmsis_compiler.h"
+#include "mem_types.h"
+#include "os_pm.h"
+#include "os_sched.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum
+{
+    OS_EXE_SUCCESS = 0,
+    OS_EXE_FAIL,
+    OS_EXE_ERROR_HANDLE_IS_NULL,
+    OS_EXE_ERROR_PTR_HANDLE_IS_NULL,
+    OS_EXE_ERROR_PTR_HANDLE_NOT_NULL,
+    OS_EXE_ERROR_NOTIFY_IS_NULL,
+    OS_EXE_ERROR_AUTORELOAD_IS_NULL,
+    OS_EXE_ERROR_TIMER_NUMBER_IS_NULL,
+    OS_EXE_ERROR_TIMER_CALLBACK_IS_NULL,
+    OS_EXE_ERROR_STATE_IS_NULL,
+    OS_EXE_ERROR_PRIORITY_IS_NULL,
+    OS_EXE_ERROR_MUTEX_HOLDER_NOT_NULL,
+    OS_EXE_ERROR_INPUT_PARA_PTR_IS_NULL,
+} OS_EXE_TYPE;
+
+typedef void (*USER_CALL_BACK)();
+
+/* task & isr context check interface */
+// static inline bool osif_task_context_check(void);
+
+// void osif_init(void);
+
+// /* OS schedule interfaces */
+// void osif_delay(uint32_t ms);
+// uint64_t osif_sys_time_get(void);
+// uint64_t osif_sys_tick_get(void);
+// uint64_t osif_hp_time_get(void);
+// bool osif_sched_start(void);
+// bool osif_sched_stop(void);
+// bool osif_sched_suspend(void);
+// bool osif_sched_resume(void);
+// bool osif_sched_restore(void);
+// bool osif_sched_state_get(long *p_state);
+// bool osif_bottom_half(T_OSIF_WORK_FUNC func, void *p_arg);
+
+// /* OS task interfaces */
+// bool osif_alloc_secure_ctx(uint32_t stack_size);
+// bool osif_task_create(void **pp_handle, const char *p_name, void (*p_routine)(void *),
+//                       void *p_param, uint16_t stack_size, uint16_t priority);
+// bool osif_task_delete(void *p_handle);
+// bool osif_task_suspend(void *p_handle);
+// bool osif_task_resume(void *p_handle);
+// bool osif_task_yield(void);
+// bool osif_task_handle_get(void **pp_handle);
+// bool osif_task_priority_get(void *p_handle, uint16_t *p_priority);
+// bool osif_task_priority_set(void *p_handle, uint16_t priority);
+// bool osif_task_signal_send(void *p_handle, uint32_t signal);
+// bool osif_task_signal_recv(uint32_t *p_signal, uint32_t wait_ms);
+// bool osif_task_signal_clear(void *p_handle);
+// void osif_task_status_dump(void);
+
+// /* OS synchronization interfaces */
+// uint32_t osif_lock(void);
+// void osif_unlock(uint32_t flags);
+// bool osif_sem_create(void **pp_handle,  const char *p_name, uint32_t init_count,
+//                      uint32_t max_count);
+// bool osif_sem_delete(void *p_handle);
+// bool osif_sem_take(void *p_handle, uint32_t wait_ms);
+// bool osif_sem_give(void *p_handle);
+// bool osif_mutex_create(void **pp_handle);
+// bool osif_mutex_delete(void *p_handle);
+// bool osif_mutex_take(void *p_handle, uint32_t wait_ms);
+// bool osif_mutex_give(void *p_handle);
+
+// /* OS message queue interfaces */
+// bool osif_msg_queue_create(void **pp_handle,  const char *p_name, uint32_t msg_num,
+//                            uint32_t msg_size);
+// bool osif_msg_queue_delete(void *p_handle);
+// bool osif_msg_queue_peek(void *p_handle, uint32_t *p_msg_num);
+// bool osif_msg_send(void *p_handle, void *p_msg, uint32_t wait_ms);
+// bool osif_msg_recv(void *p_handle, void *p_msg, uint32_t wait_ms);
+// bool osif_msg_peek(void *p_handle, void *p_msg, uint32_t wait_ms);
+
+// /* OS memory management interfaces */
+// void *osif_mem_alloc(RAM_TYPE ram_type, size_t size);
+// void *osif_mem_aligned_alloc(RAM_TYPE ram_type, size_t size, uint8_t alignment);
+// void *osif_mem_zalloc(RAM_TYPE ram_type, size_t size);
+// void *osif_mem_realloc(RAM_TYPE ram_type, void *ptr, size_t size);
+// void osif_mem_free(void *p_block);
+// void osif_mem_aligned_free(void *p_block);
+// size_t osif_mem_peek(RAM_TYPE ram_type);
+// size_t osif_mem_peek_max_free_block(RAM_TYPE ram_type);
+// void osif_mem_check_heap_usage(void);
+
+// /* OS software timer interfaces */
+// bool osif_timer_id_get(void **pp_handle, uint32_t *p_timer_id);
+// bool osif_timer_create(void **pp_handle, const char *p_timer_name, uint32_t timer_id,
+//                        uint32_t interval_ms, bool reload, void (*p_timer_callback)(void *));
+// bool osif_timer_start(void **pp_handle);
+// bool osif_timer_restart(void **pp_handle, uint32_t interval_ms);
+// bool osif_timer_stop(void **pp_handle);
+// bool osif_timer_delete(void **pp_handle);
+// bool osif_timer_pend_function_call(void (*p_pend_function)(void *, uint32_t),
+//                                    void *pvParameter1, uint32_t ulParameter2);
+// bool osif_timer_auto_reload_get(void **pp_handle, long *p_autoreload);
+// bool osif_timer_state_get(void **pp_handle, uint32_t *p_timer_state);
+// bool osif_timer_handle_get(uint8_t timer_idx, void **pp_handle);
+// bool osif_timer_dump(void);
+// void osif_timer_init(void);
+
+// /* OS software power manager interfaces */
+// void osif_pm_init(void);
+// void osif_timer_tick_handler(void);
+// uint32_t osif_timer_tick_rate_get(void);
+// uint32_t osif_timer_clock_get(void);
+// uint64_t osif_timer_tick_increase(uint32_t tick_increment);
+
+// uint32_t osif_pm_next_timeout_value_get(void);
+
+// bool osif_pm_excluded_handle_register(void **handle, PlatformExcludedHandleType type);
+// bool osif_pm_excluded_handle_unregister(void **handle, PlatformExcludedHandleType type);
+
+// void osif_pm_tickcount_store(void);
+// void osif_pm_tickcount_restore(void);
+
+// void osif_pm_bottom_half(void (*pend_func)(void));
+// void osif_pm_return_to_idle_task(void);
+
+// /* OS external interfaces */
+// void osif_sched_set_hook(void (*hook)(void *from, void *to));
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _OSIF_H_ */
diff --git a/bee/soc/CMakeLists.txt b/bee/soc/CMakeLists.txt
new file mode 100644
index 00000000..ae3f53e2
--- /dev/null
+++ b/bee/soc/CMakeLists.txt
@@ -0,0 +1,6 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+add_subdirectory_ifdef(CONFIG_SOC_SERIES_RTL87X2G inc/rtl87x2g)
+zephyr_include_directories_ifdef(CONFIG_SOC_SERIES_RTL8752H inc/rtl8752h)
+zephyr_include_directories_ifdef(CONFIG_SOC_SERIES_RTL87X2J inc/rtl87x2j)
diff --git a/bee/soc/inc/rtl8752h/cm0plus_setting.h b/bee/soc/inc/rtl8752h/cm0plus_setting.h
new file mode 100644
index 00000000..fea75cdf
--- /dev/null
+++ b/bee/soc/inc/rtl8752h/cm0plus_setting.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __CM0PLUS_SETTING_H__
+#define __CM0PLUS_SETTING_H__
+
+
+/*============================================================================*
+ *              Configuration of the cm0+ Processor and Core Peripherals
+ *============================================================================*/
+#define __VTOR_PRESENT CONFIG_CPU_CORTEX_M_HAS_VTOR /* VTOR present or not */
+#define __MPU_PRESENT                  1            /*!< MPU present or not                                                    */
+#define __FPU_PRESENT                  0            /* FPU present                                                             */
+#define __NVIC_PRIO_BITS               3            /*!< Number of Bits used for Priority Levels                               */
+#define __Vendor_SysTickConfig         0           /*!< Set to 1 if different SysTick Config is used                          */
+
+
+#endif /* __CM0PLUS_SETTING_H__ */
+
+
diff --git a/bee/soc/inc/rtl8752h/platform_cfg.h b/bee/soc/inc/rtl8752h/platform_cfg.h
new file mode 100644
index 00000000..21cffb38
--- /dev/null
+++ b/bee/soc/inc/rtl8752h/platform_cfg.h
@@ -0,0 +1,142 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _PLATFORM_CFG_H
+#define _PLATFORM_CFG_H
+
+#include <stdlib.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <flash_nor_device.h>
+
+/**
+ * @struct EFUSE_PLATFORM_CONFIG_
+ * @brief Platform EFuse settings.
+ *
+ * Refer to EFUSE[0x].
+ */
+typedef struct EFUSE_PLATFORM_CONFIG_
+{
+    uint64_t trace_mask[4];              /* need to be put to first to avoid alignment access fault */
+
+    uint16_t stack_en : 1;
+    uint16_t cpu_sleep_en: 1;            /* default = 0 */
+    uint16_t run_in_app : 1;             /* boot runs in app */
+    uint16_t ftl_init_in_rom : 1;
+    uint16_t rsvd0 : 12;
+
+    uint32_t logPin : 6;                 /* default = P0_3 */
+    uint32_t logChannel : 2;             /* LogChannel_TypeDef: default is LOG_CHANNEL_LOG1_UART */
+    uint32_t logBaudRate : 5;            /* UartBaudRate_TypeDef: default is BAUD_RATE_2000000 */
+    uint32_t enableROMMPU : 1;           /* protect rom as Read-only region, default = 1 */
+    uint32_t logThreshold : 3;           /* Log threshold: default = 3 (256 = 1 << (5 + 3) */
+    uint32_t logDisable : 1;             /* Disable all DBG_DIRECT and DBG_BUFFER log */
+
+    /* rsvd more */
+} __attribute__((packed)) SYS_INIT_CONFIG;
+
+extern SYS_INIT_CONFIG sys_init_cfg;
+
+typedef struct __attribute__((packed)) _FLASH_NOR_QUERY_INFO_STRUCT
+{
+    /* If tbbo equals to 0x7F means BP supports lock all, lock half, lock none,
+       and if tbbo equals to 0xFF means BP only supports lock all, lock none */
+    /* If adsbo equals to 0xFF means flash size is smaller than 16MB, so only
+       needs 3 bytes address */
+    uint32_t flash_size;                /* Nor flash size in byte */
+    uint8_t qebo;                       /* QE bit offset in status register */
+    uint8_t wsbo;                       /* Write suspend flag bit offset in status register */
+    uint8_t esbo;                       /* Erase suspend flag bit offset in status register */
+    uint8_t tbbo;                       /* Top-bottom bit offset in status register */
+    uint8_t cmpbo;                      /* Complement bit offset in status register */
+    uint8_t adsbo;                      /* Current address mode bit offset in status register */
+    uint8_t bp_all;                     /* Block protect all level in status register */
+    uint8_t bp_mask;                    /* Block protect configurable bit mask in status register */
+    uint32_t resume_to_suspend_delay_us;/* Delay time for a resume command to next suspend command */
+} FLASH_NOR_QUERY_INFO_STRUCT;
+
+typedef struct __attribute__((packed)) _FLASH_NOR_QUERY_INFO_TABLE_STRUCT
+{
+    uint8_t manu_id;
+    uint16_t device_id;
+    uint8_t flash_info; // BIT0 = is_sr2_exist
+    FLASH_NOR_QUERY_INFO_STRUCT query;
+} FLASH_NOR_QUERY_INFO_TABLE_STRUCT;
+
+typedef struct _FLASH_NOR_SETTINGS_CFG
+{
+    uint32_t flash_cmd_list_len : 2;
+    uint32_t flash_busy_wait_tick : 6;
+    uint32_t hpm_en : 1;
+    uint32_t is_4_byte_address_mode : 1;
+    uint32_t init_cmd_from_cfg : 1;
+    uint32_t init_query_from_cfg : 1;
+    uint32_t flash_dma_ch : 4;
+    uint32_t flash_dma_ch_priority : 8;
+    uint32_t flash_dma_irq_priority : 8;
+
+    uint32_t wait_max_retry : 27;
+    uint32_t erase_max_retry : 4;
+    uint32_t reg_wren_type : 1;
+
+    uint32_t turn_on_off_rf: 1;   // 0, no turn on/off rf; 1, turn on/off rf
+    uint32_t spic_baud : 12;
+    uint32_t dp_release_cyc_len : 3;
+    uint32_t dp_release_delay_us : 8;
+    uint32_t sw_reset_delay_us : 8;
+
+
+    uint32_t bp_enable : 1;
+    uint32_t bp_tb : 1;
+    uint32_t bp_lv : 8;
+    uint32_t bp_ignore : 1;
+    uint32_t cache_enable : 1; //enable cache or not
+    // 2'b00 for non-MCM flash, use VDDC power cut;
+    // 2'b01 for 1.8V MCM flash;
+    // 2'b10 for wide range MCM flash;
+    // 2'b11 for non-MCM flash, do not need VDDC power cut (default);
+    uint32_t disable_irq_lv: 3;
+    uint32_t read_turn_on_off_rf: 1;
+    uint32_t active_power: 2;
+    uint32_t init_cmd_rdid : 8;
+    uint32_t dp_enter_delay_us: 6;
+
+    uint32_t init_cmd_rd_data : 8;
+    uint32_t init_cmd_dp_release : 8;
+    uint32_t init_cmd_en_reset : 8;
+    uint32_t init_cmd_reset : 8;
+
+    uint8_t  flash_power_on_delay_100us_cnt;
+    uint8_t  flash_init_delay_1ms_cnt;
+    uint16_t flash_init_whether_check_wip: 1;
+    uint16_t flash_check_wip_delay_1ms_cnt: 15;
+
+    T_FLASH_INFO_TBL flash_info_tbl;     /* store Flash related information */ //18 bytes
+    FLASH_NOR_QUERY_INFO_TABLE_STRUCT query_info;
+
+} __attribute__((packed)) FLASH_NOR_SETTINGS_CFG;
+
+typedef struct _BT_EFUSE_BOOT_CFG
+{
+    uint32_t SWD_ENABLE: 1;
+    uint32_t aon_reg_parsing_tag: 8;
+    uint32_t is_bypass_flash: 1;
+    uint32_t is_do_lop_pon_setting: 1;
+    uint32_t is_hw_auto_pwm_pfm: 1;
+    uint32_t ota_copy_image_before_secure_boot: 1;
+    uint32_t rsvd: 19;
+
+    uint32_t is_need_delay_for_32k_deglitch: 1;
+    uint32_t deglitch_sync_begin_cnt: 26;
+    uint32_t rsvd1: 5;
+
+    FLASH_NOR_SETTINGS_CFG flash_setting;
+
+} __attribute__((packed)) BT_EFUSE_BOOT_CFG;
+
+extern BT_EFUSE_BOOT_CFG boot_cfg;
+
+#endif /* _PLATFORM_CFG_H */
diff --git a/bee/soc/inc/rtl8752h/rom_uuid.h b/bee/soc/inc/rtl8752h/rom_uuid.h
new file mode 100644
index 00000000..d27b7e3d
--- /dev/null
+++ b/bee/soc/inc/rtl8752h/rom_uuid.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _SYMBOLTABLE_UUID_H
+#define _SYMBOLTABLE_UUID_H
+
+#define DEFINE_symboltable_uuid { 0x98,0xc5,0x31,0x9b,0x43,0xc2,0xed,0x11,0xbe,0x06,0x11,0x3b,0x98,0x3e,0xdd,0x6f }
+
+#endif /* _SYMBOLTABLE_UUID_H */
diff --git a/bee/soc/inc/rtl8752h/rtl876x.h b/bee/soc/inc/rtl8752h/rtl876x.h
new file mode 100644
index 00000000..fb212109
--- /dev/null
+++ b/bee/soc/inc/rtl8752h/rtl876x.h
@@ -0,0 +1,5519 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef RTL876X_H
+#define RTL876X_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*============================================================================*
+ *                      Headers
+ *============================================================================*/
+#include "cm0plus_setting.h"
+
+/** @defgroup RTL876X CMSIS-RTL876X
+  * @brief    CMSIS Cortex-M0+ peripheral access layer header file for
+  *           RTL876X from Realtek Semiconductor
+  * @{
+  */
+
+/*============================================================================*
+ *                              Types
+ *============================================================================*/
+/** @defgroup RTL876X_Exported_types CMSIS-RTL876X Exported types
+  * @{
+  */
+
+/** brief Interrupt Number Definition */
+typedef enum IRQn
+{
+    /* -------------------  Cortex-M0+ Processor Exceptions Numbers  ------------------- */
+    NonMaskableInt_IRQn           = -14,      /**<  2 Non Maskable Interrupt */
+    HardFault_IRQn                = -13,      /**<  3 HardFault Interrupt */
+    SVCall_IRQn                   =  -5,      /**< 11 SV Call Interrupt */
+    DebugMonitor_IRQn             =  -4,      /**< 12 Debug Monitor Interrupt */
+    PendSV_IRQn                   =  -2,      /**< 14 Pend SV Interrupt */
+    SysTick_IRQn                  =  -1,      /**< 15 System Tick Interrupt */
+
+    System_IRQn = 0,             /**<  [0] System Interrupt */
+    TMETER_IRQn,                 /**<  [1] TMETER Interrupt */
+    BTMAC_IRQn,                  /**<  [2] BTMAC Interrupt ( an Extension of interrupt ) */
+    Timer3_IRQn,                 /**<  [3] Timer3 global interrupt */
+    Timer2_IRQn,                 /**<  [4] Timer2 global interrupt */
+    BTMAC_WRAP_AROUND_IRQn,      /**<  [5] BTMAC error interrupt */
+    I2S0_TX_IRQn,                /**<  [6] I2S0 TX interrupt */
+    I2S0_RX_IRQn,                /**<  [7] I2S0 RX interrupt */
+    Timer4_5_IRQn,               /**<  [8] Timer 4 to 5 interrupt  ( an Extension of interrupt ) */
+    ZIGBEE_IRQn,                 /**<  [9] ZIGBEE interrupt */
+    PF_RTC_IRQn,                 /**<  [10] Platform RTC interrupt */
+    UART0_IRQn,                  /**<  [11] UART0 interrupt */
+    UART1_IRQn,                  /**<  [12] UART1 interrupt */
+    I8080_IRQn,                  /**<  [13] I8080 interrupt */
+    SPI0_IRQn,                   /**<  [14] SPI0 interrupt */
+    SPI1_IRQn,                   /**<  [15] SPI1 interrupt */
+    I2C0_IRQn,                   /**<  [16] I2C0 interrupt */
+    I2C1_IRQn,                   /**<  [17] I2C1 interrupt */
+    ADC_IRQn,                    /**<  [18] ADC global interrupt */
+    Peripheral_IRQn,             /**<  [19] Peripheral Interrupt  ( an Extension of interrupt ) */
+    GDMA0_Channel0_IRQn,         /**<  [20] RTK-DMA0 channel 0 global interrupt */
+    GDMA0_Channel1_IRQn,         /**<  [21] RTK-DMA0 channel 1 global interrupt */
+    GDMA0_Channel2_IRQn,         /**<  [22] RTK-DMA0 channel 2 global interrupt */
+    GDMA0_Channel3_IRQn,         /**<  [23] RTK-DMA0 channel 3 global interrupt */
+    ENHANCED_TIMER0_IRQn,        /**<  [24] Enhanced timer0 interrupt */
+    ENHANCED_TIMER1_IRQn,        /**<  [25] Enhanced timer1 interrupt */
+    GPIO_Group3_IRQn,            /**<  [26] GPIO Group3 Interrupt ( an Extension of interrupt ) */
+    GPIO_Group2_IRQn,            /**<  [27] GPIO Group2 Interrupt ( an Extension of interrupt )  */
+    IR_IRQn,                     /**<  [28] IR Interrupt */
+    GPIO_Group1_IRQn,            /**<  [29] GPIO Group1 Interrupt ( an Extension of interrupt )  */
+    GPIO_Group0_IRQn,            /**<  [30] GPIO Group0 Interrupt ( an Extension of interrupt )  */
+    UART2_IRQn,                  /**<  [31] UART2 interrupt */
+    /******  rtl8752h Extension Interrupt Numbers ************/
+    TIMER4_IRQ                      = 8,
+    TIMER5_IRQ                      = 8,
+    GPIO3_IRQn                      = 26,
+    GPIO7_IRQn                      = 26,
+    GPIO11_IRQn                     = 26,
+    GPIO15_IRQn                     = 26,
+    GPIO19_IRQn                     = 26,
+    GPIO23_IRQn                     = 26,
+    GPIO27_IRQn                     = 26,
+    GPIO31_IRQn                     = 26,
+    GPIO2_IRQn                      = 27,
+    GPIO6_IRQn                      = 27,
+    GPIO10_IRQn                     = 27,
+    GPIO14_IRQn                     = 27,
+    GPIO18_IRQn                     = 27,
+    GPIO22_IRQn                     = 27,
+    GPIO26_IRQn                     = 27,
+    GPIO30_IRQn                     = 27,
+    GPIO1_IRQn                      = 29,
+    GPIO5_IRQn                      = 29,
+    GPIO9_IRQn                      = 29,
+    GPIO13_IRQn                     = 29,
+    GPIO17_IRQn                     = 29,
+    GPIO21_IRQn                     = 29,
+    GPIO25_IRQn                     = 29,
+    GPIO29_IRQn                     = 29,
+    GPIO0_IRQn                      = 30,
+    GPIO4_IRQn                      = 30,
+    GPIO8_IRQn                      = 30,
+    GPIO12_IRQn                     = 30,
+    GPIO16_IRQn                     = 30,
+    GPIO20_IRQn                     = 30,
+    GPIO24_IRQn                     = 30,
+    GPIO28_IRQn                     = 30,
+    Peripheral_First_IRQn           = 50,
+    SPIC0_IRQn                      = 50,
+    Qdecode_IRQn                    = 51,
+    KeyScan_IRQn                    = 52,
+    SPI2W_IRQn                      = 53,
+    LPCOMP_IRQn                     = 54,
+    PTA_Mailbox_IRQn                = 55,
+    SPIC1_IRQn                      = 56,
+    SHA256_IRQn                     = 57,
+    Platform_IRQn                   = 58,
+    TRNG_IRQn                       = 59,
+    FLASH_SEC_IRQn                  = 60,
+    RTC_IRQn                        = 61,
+    WDT_IRQn                        = 62,
+} IRQn_Type, *PIRQn_Type;
+
+typedef enum
+{
+    RESET = 0,
+    SET = !RESET
+} FlagStatus, ITStatus;
+
+typedef enum
+{
+    DISABLE = 0,
+    ENABLE = !DISABLE
+} FunctionalState;
+
+
+//typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
+
+/** @} */ /* End of group RTL876X_Exported_types */
+
+
+/** @defgroup Configuration_of_CMSIS Configuration of CMSIS
+  * @brief   Configuration of the cm0+ Processor and Core Peripherals
+  * @{
+  */
+/* ----------------Configuration of the cm0+ Processor and Core Peripherals---------------- */
+#define __FPU_PRESENT                  0    /* FPU present                                                             */
+#define __NVIC_PRIO_BITS               3    /*!< Number of Bits used for Priority Levels                               */
+#define __Vendor_SysTickConfig         0    /*!< Set to 1 if different SysTick Config is used                          */
+/** @} */ /* End of group Configuration_of_CMSIS */
+
+
+/*============================================================================*
+ *                               Header Files
+*============================================================================*/
+/* Processor and core peripherals */
+#include "core_cm0plus.h"
+#include "system_rtl876x.h"
+
+/*============================================================================*
+ *                              RTL876X Pin Number
+*============================================================================*/
+/** @defgroup RTL876X_Pin_Number RTL876X Pin Number
+  * @{
+  */
+#define P0_0    0   /**<GPIO0   */
+#define P0_1    1   /**<GPIO1   */
+#define P0_2    2   /**<GPIO2   */
+#define P0_3    3   /**<GPIO3   */
+#define P0_4    4   /**<GPIO4   */
+#define P0_5    5   /**<GPIO5   */
+#define P0_6    6   /**<GPIO6   */
+#define P0_7    7   /**<GPIO7   */
+#define P1_0    8   /**<GPIO8   */
+#define P1_1    9   /**<GPIO9   */
+#define P1_3    11
+#define P1_4    12
+#define P1_6    14   /**<GPIO14   */
+#define P1_7    15   /**<GPIO15   */
+#define P2_0    16   /**<GPIO16   */
+#define P2_1    17   /**<GPIO17   */
+#define P2_2    18   /**<GPIO18   */
+#define P2_3    19   /**<GPIO19   */
+#define P2_4    20   /**<GPIO20   */
+#define P2_5    21   /**<GPIO21   */
+#define P2_6    22   /**<GPIO22   */
+#define P2_7    23   /**<GPIO23   */
+#define P3_0    24   /**<GPIO24   */
+#define P3_1    25   /**<GPIO25   */
+#define P3_2    26   /**<GPIO26   */
+#define P3_3    27   /**<GPIO27   */
+#define P3_4    28   /**<GPIO28   */
+#define P3_5    29   /**<GPIO29   */
+#define P3_6    30   /**<GPIO30   */
+#define P4_0    32   /**<GPIO13   */
+#define P4_1    33   /**<GPIO29   */
+#define P4_2    34   /**<GPIO30   */
+#define P4_3    35   /**<GPIO31   */
+#define H_0     36   /**<GPIO10   MICBIAS   */
+#define P5_1    37   /**<GPIO11   */
+#define P5_2    38   /**<GPIO12   */
+
+/** @} */ /* End of group RTL876X_Pin_Number */
+
+
+/* ================================================================================ */
+/* ================    Peripheral Registers Structures Section     ================ */
+/* ================================================================================ */
+
+/** @defgroup RTL876X_Peripheral_Registers_Structures RTL876X Register Structure
+  * @{
+  */
+
+/* ================================================================================ */
+/* ================                       ADC                      ================ */
+/* ================================================================================ */
+
+/**
+  * @brief Analog to digital converter. (ADC)
+  */
+
+typedef struct                  /*!< ADC Structure */
+{
+    __O  uint32_t FIFO;         //!<0x00
+    __IO uint32_t CR;          //!<0x04
+    __IO uint32_t SCHCR;       //!<0x08
+    __IO uint32_t INTCR;       //!<0x0C
+    __IO uint32_t SCHTAB0;     //!<0x10
+    __IO uint32_t SCHTAB1;     //!<0x14
+    __IO uint32_t SCHTAB2;     //!<0x18
+    __IO uint32_t SCHTAB3;     //!<0x1C
+    __IO uint32_t SCHTAB4;     //!<0x20
+    __IO uint32_t SCHTAB5;     //!<0x24
+    __IO uint32_t SCHTAB6;     //!<0x28
+    __IO uint32_t SCHTAB7;     //!<0x2C
+    __IO uint32_t SCHD0;       //!<0x30
+    __IO uint32_t SCHD1;       //!<0x34
+    __IO uint32_t SCHD2;       //!<0x38
+    __IO uint32_t SCHD3;       //!<0x3C
+    __IO uint32_t SCHD4;       //!<0x40
+    __IO uint32_t SCHD5;       //!<0x44
+    __IO uint32_t SCHD6;       //!<0x48
+    __IO uint32_t SCHD7;       //!<0x4C
+    __IO uint32_t PWRDLY;      //!<0x50
+    __IO uint32_t DATCLK;      //!<0x54
+    __IO uint32_t ANACTL;      //!<0x58
+    __IO uint32_t SAMTIM;      //!<0x5C
+
+} ADC_TypeDef;
+
+/* ================================================================================ */
+/* ================                      CODEC                     ================ */
+/* ================================================================================ */
+
+typedef struct
+{
+    __IO uint32_t ANA_CR0;          /*!< 0x00 */
+    __IO uint32_t ANA_CR1;          /*!< 0x04 */
+    __IO uint32_t ANA_CR2;          /*!< 0x08 */
+} CODEC_AnalogTypeDef;
+
+typedef struct
+{
+    __IO uint32_t CR0;              /*!< 0x00 */
+    __IO uint32_t ANA_CR1;          /*!< 0x04 */
+    __IO uint32_t CLK_CR1;          /*!< 0x08 */
+    __IO uint32_t CLK_CR2;          /*!< 0x0C */
+    __IO uint32_t CLK_CR3;          /*!< 0x10 */
+    __IO uint32_t RSVD0[2];
+    __IO uint32_t I2S_CTRL;         /*!< 0x1C */
+    __IO uint32_t ADC0_CTRL0;       /*!< 0x20 */
+    __IO uint32_t ADC0_CTRL1;       /*!< 0x24 */
+} CODEC_TypeDef;
+
+/* ================================================================================ */
+/* ================                    CAP TOUCH                   ================ */
+/* ================================================================================ */
+
+typedef struct
+{
+    __IO uint32_t CR;               /*!< 0x00 */
+    __IO uint32_t SCAN_PERIOD;      /*!< 0x04 */
+    __IO uint32_t ETC_CR;           /*!< 0x08 */
+    __IO uint32_t SNR_INF;          /*!< 0x0C */
+    __IO uint32_t DEBUG_CR;         /*!< 0x10 */
+    __IO uint32_t FIFO;             /*!< 0x14 */
+    __IO uint32_t RAW_FIFO;         /*!< 0x18 */
+    __IO uint32_t GUARD_CNT;        /*!< 0x1C */
+    __IO uint32_t INT_EN;           /*!< 0x20 */
+    __IO uint32_t INT_SR;           /*!< 0x24 */
+    __IO uint32_t RAW_INT_SR;       /*!< 0x28 */
+    __IO uint32_t RSVD0;            /*!< 0x2C */
+    __IO uint32_t INT_CLR;          /*!< 0x30 */
+    __IO uint32_t INT_SCLR;         /*!< 0x34 */
+    __IO uint32_t RSVD1[2];
+    __IO uint32_t DBG_SEL;          /*!< 0x40 */
+    __IO uint32_t DBG_PORT;         /*!< 0x44 */
+    __IO uint32_t ECO_INF0;         /*!< 0x48 */
+    __IO uint32_t ECO_INF1;         /*!< 0x4C */
+    __IO uint32_t VERSION;          /*!< 0x50 */
+} CTC_TypeDef;
+
+typedef struct
+{
+    __IO uint32_t CR;               /*!< 0x00 */
+    __IO uint32_t TOUCH_TH;         /*!< 0x04 */
+    __IO uint32_t MBIAS;            /*!< 0x08 */
+    __IO uint32_t DATA;             /*!< 0x0C */
+} CTC_ChannelTypeDef;
+
+typedef struct
+{
+    __IO uint32_t SCAN_INI;         /*!< 0x00 */
+    __IO uint32_t SET_CNT;          /*!< 0x04 */
+    __O  uint32_t TOUCH_CNT01;      /*!< 0x08 */
+    __O  uint32_t TOUCH_CNT23;      /*!< 0x0C */
+    __O  uint32_t TOUCH_SR;         /*!< 0x10 */
+} CTC_FSModeTypeDef;
+
+/* ================================================================================ */
+/* ================                      GDMA                      ================ */
+/* ================================================================================ */
+/**
+  * @brief GDMA
+  */
+typedef struct
+{
+    __I uint32_t RAW_TFR;
+    uint32_t RSVD0;
+    __I uint32_t RAW_BLOCK;
+    uint32_t RSVD1;
+    __I uint32_t RAW_SRC_TRAN;
+    uint32_t RSVD2;
+    __I uint32_t RAW_DST_TRAN;
+    uint32_t RSVD3;
+    __I uint32_t RAW_ERR;
+    uint32_t RSVD4;
+
+    __I uint32_t STATUS_TFR;
+    uint32_t RSVD5;
+    __I uint32_t STATUS_BLOCK;
+    uint32_t RSVD6;
+    __I uint32_t STATUS_SRC_TRAN;
+    uint32_t RSVD7;
+    __I uint32_t STATUS_DST_TRAN;
+    uint32_t RSVD8;
+    __I uint32_t STATUS_ERR;
+    uint32_t RSVD9;
+
+    __IO uint32_t MASK_TFR;
+    uint32_t RSVD10;
+    __IO uint32_t MASK_BLOCK;
+    uint32_t RSVD11;
+    __IO uint32_t MASK_SRC_TRAN;
+    uint32_t RSVD12;
+    __IO uint32_t MASK_DST_TRAN;
+    uint32_t RSVD13;
+    __IO uint32_t MASK_ERR;
+    uint32_t RSVD14;
+
+    __O uint32_t CLEAR_TFR;
+    uint32_t RSVD15;
+    __O uint32_t CLEAR_BLOCK;
+    uint32_t RSVD16;
+    __O uint32_t CLEAR_SRC_TRAN;
+    uint32_t RSVD17;
+    __O uint32_t CLEAR_DST_TRAN;
+    uint32_t RSVD18;
+    __O uint32_t CLEAR_ERR;
+    uint32_t RSVD19;
+    __O uint32_t StatusInt;
+    uint32_t RSVD191;
+
+    __IO uint32_t ReqSrcReg;
+    uint32_t RSVD20;
+    __IO uint32_t ReqDstReg;
+    uint32_t RSVD21;
+    __IO uint32_t SglReqSrcReg;
+    uint32_t RSVD22;
+    __IO uint32_t SglReqDstReg;
+    uint32_t RSVD23;
+    __IO uint32_t LstSrcReg;
+    uint32_t RSVD24;
+    __IO uint32_t LstDstReg;
+    uint32_t RSVD25;
+
+    __IO uint32_t DmaCfgReg;
+    uint32_t RSVD26;
+    __IO uint32_t ChEnReg;
+    uint32_t RSVD27;
+    __I uint32_t DmaIdReg;
+    uint32_t RSVD28;
+    __IO uint32_t DmaTestReg;
+    uint32_t RSVD29;
+} GDMA_TypeDef;
+
+typedef struct
+{
+    __IO uint32_t SAR;
+    uint32_t RSVD0;
+    __IO uint32_t DAR;
+    uint32_t RSVD1;
+    __IO uint32_t LLP;
+    uint32_t RSVD2;
+    __IO uint32_t CTL_LOW;
+    __IO uint32_t CTL_HIGH;
+    __IO uint32_t SSTAT;
+    uint32_t RSVD4;
+    __IO uint32_t DSTAT;
+    uint32_t RSVD5;
+    __IO uint32_t SSTATAR;
+    uint32_t RSVD6;
+    __IO uint32_t DSTATAR;
+    uint32_t RSVD7;
+    __IO uint32_t CFG_LOW;
+    __IO uint32_t CFG_HIGH;
+    __IO uint32_t SGR;
+    uint32_t RSVD9;
+    __IO uint32_t DSR;
+    uint32_t RSVD10;
+} GDMA_ChannelTypeDef;
+
+/* ================================================================================ */
+/* ================                      GPIO                      ================ */
+/* ================================================================================ */
+
+/**
+  * @brief General purpose input and output. (GPIO)
+  */
+
+typedef struct
+{
+    __IO uint32_t DATAOUT;              /*!< Data register: data output */
+    __IO uint32_t DATADIR;              /*!< Data direction register */
+    __IO uint32_t DATASRC;              /*!< Data source register  */
+    uint32_t RSVD[9];
+    __IO uint32_t INTEN;                /*!< Interrupt enable register */
+    __IO uint32_t INTMASK;              /*!< Interrupt mask register */
+    __IO uint32_t INTTYPE;              /*!< Interrupt level register */
+    __IO uint32_t INTPOLARITY;          /*!< Interrupt polarity register */
+    __IO uint32_t INTSTATUS;            /*!< Interrupt status of Port A  */
+    __IO uint32_t RAWINTSTATUS;         /*!< Raw interrupt status of Port A (premasking) */
+    __IO uint32_t DEBOUNCE;             /*!< Debounce enable register */
+    __O  uint32_t INTCLR;               /*!< clear interrupt register */
+    __I  uint32_t DATAIN;               /*!< external port register */
+    uint32_t RSVD1[3];
+    __IO uint32_t LSSYNC;               /*!< Level-sensitive synchronization enable register*/
+    __I  uint32_t IDCODE;               /*!< ID code register */
+    __IO uint32_t INTBOTHEDGE;          /*!< Both edge to trigger interrupt*/
+} GPIO_TypeDef;
+
+/* ================================================================================ */
+/* ================                      I2C                      ================= */
+/* ================================================================================ */
+
+/**
+  * @brief I2C
+  */
+typedef struct
+{
+    __IO uint32_t IC_CON;
+    __IO uint32_t IC_TAR;
+    __IO uint32_t IC_SAR;
+    __IO uint32_t RSVD_0C;
+    __IO uint32_t IC_DATA_CMD;
+    __IO uint32_t IC_SS_SCL_HCNT;
+    __IO uint32_t IC_SS_SCL_LCNT;
+    __IO uint32_t IC_FS_SCL_HCNT;
+    __IO uint32_t IC_FS_SCL_LCNT;
+    __IO uint32_t RSVD_24[2];
+    __I uint32_t IC_INTR_STAT;
+    __IO uint32_t IC_INTR_MASK;
+    __I uint32_t IC_RAW_INTR_STAT;
+    __IO uint32_t IC_RX_TL;
+    __IO uint32_t IC_TX_TL;
+    __I uint32_t IC_CLR_INTR;
+    __I uint32_t IC_CLR_RX_UNDER;
+    __I uint32_t IC_CLR_RX_OVER;
+    __I uint32_t IC_CLR_TX_OVER;
+    __I uint32_t IC_CLR_RD_REQ;
+    __I uint32_t IC_CLR_TX_ABRT;
+    __I uint32_t IC_CLR_RX_DONE;
+    __I uint32_t IC_CLR_ACTIVITY;
+    __I uint32_t IC_CLR_STOP_DET;
+    __I uint32_t IC_CLR_START_DET;
+    __I uint32_t IC_CLR_GEN_CALL;
+    __IO uint32_t IC_ENABLE;
+    __I uint32_t IC_STATUS;
+    __I uint32_t IC_TXFLR;
+    __I uint32_t IC_RXFLR;
+    __IO uint32_t IC_SDA_HOLD;
+    __I uint32_t IC_TX_ABRT_SOURCE;
+    __IO uint32_t IC_SLV_DATA_NACK_ONLY;
+    __IO uint32_t IC_DMA_CR;
+    __IO uint32_t IC_DMA_TDLR;
+    __IO uint32_t IC_DMA_RDLR;
+    __IO uint32_t IC_SDA_SETUP;
+    __IO uint32_t IC_ACK_GENERAL_CALL;
+    __IO uint32_t IC_ENABLE_STATUS;
+    __IO uint32_t IC_FS_SPKLEN;
+} I2C_TypeDef;
+
+/* ================================================================================ */
+/* ================                      I2S                      ================= */
+/* ================================================================================ */
+
+/**
+  * @brief I2S
+  */
+typedef struct
+{
+    __O  uint32_t TX_DR;            /*!< 0x00 */
+    __IO uint32_t CTRL0;            /*!< 0x04 */
+    __IO uint32_t CTRL1;            /*!< 0x08 */
+    __IO uint32_t DSP_INT_CR;       /*!< 0x0C */
+    __I  uint32_t RX_DR;            /*!< 0x10 */
+    __I  uint32_t FIFO_SR;          /*!< 0x14 */
+    __IO uint32_t ERROR_CNT_SR;     /*!< 0x18 */
+    __IO uint32_t BCLK_DIV;         /*!< 0x1C */
+    __IO uint32_t DMA_TRDLR;        /*!< 0x20 */
+    __I  uint32_t SR;               /*!< 0x24 */
+} I2S_TypeDef;
+
+/* ================================================================================ */
+/* ================                 IR                             ================ */
+/* ================================================================================ */
+
+/**
+  * @brief IR.
+  */
+
+typedef struct
+{
+    __IO  uint32_t CLK_DIV;         /*!< 0x00 */
+    __IO  uint32_t TX_CONFIG;       /*!< 0x04 */
+    __IO  uint32_t TX_SR;           /*!< 0x08 */
+    __IO  uint32_t RSVD0;           /*!< 0x0c */
+    __IO  uint32_t TX_INT_CLR;      /*!< 0x10 */
+    __IO  uint32_t TX_FIFO;         /*!< 0x14 */
+    __IO  uint32_t RX_CONFIG;       /*!< 0x18 */
+    __IO  uint32_t RX_SR;           /*!< 0x1c */
+    __IO  uint32_t RX_INT_CLR;      /*!< 0x20 */
+    __IO  uint32_t RX_CNT_INT_SEL;  /*!< 0x24 */
+    __IO  uint32_t RX_FIFO;         /*!< 0x28 */
+    __IO  uint32_t IR_VERSION;      /*!< 0x2c */
+    __O   uint32_t RX_CUR_CNT;      /*!< 0x30 */
+    __IO  uint32_t RX_EX_INT;       /*!< 0x34 */
+    __IO  uint32_t RSVD1[4];
+    __IO  uint32_t IR_TX_COMPE;     /*!< 0x48 */
+    __IO  uint32_t IR_RX_LEVEL;     /*!< 0x4C */
+    __IO  uint32_t DMA_CONFIG;      /*!< 0x50 */
+} IR_TypeDef;
+
+/* ================================================================================ */
+/* ================                    Key Scan                    ================ */
+/* ================================================================================ */
+
+/**
+  * @brief Key Scan. (KeyScan)
+  */
+
+typedef struct                          /*!< KeyScan Structure */
+{
+
+    __IO uint32_t CLKDIV;               /*!< 0x00 */
+    __IO uint32_t TIMERCR;              /*!< 0x04 */
+    __IO uint32_t CR;                   /*!< 0x08 */
+    __IO uint32_t COLCR;                /*!< 0x0C */
+    __IO uint32_t ROWCR;                /*!< 0x10 */
+    __I  uint32_t FIFODATA;             /*!< 0x14 */
+    __IO uint32_t INTMASK;              /*!< 0x18 */
+    __IO uint32_t INTCLR;               /*!< 0x1C */
+    __I  uint32_t STATUS;               /*!< 0x20 */
+
+} KEYSCAN_TypeDef;
+
+/* ================================================================================ */
+/* ================                      LPC                      ================= */
+/* ================================================================================ */
+
+/**
+  * @brief Real time for LP (RTC)
+  */
+typedef struct
+{
+    __IO uint32_t LPC_CR0;
+    __IO uint32_t LPC_SR;
+    __IO uint32_t LPC_CMP;
+    __IO uint32_t LPC_CNT;
+} LPC_TypeDef;
+
+/* ================================================================================ */
+/* ================                     Pinmux                     ================ */
+/* ================================================================================ */
+
+/**
+  * @brief Pinmux. (Pinmux)
+  */
+
+typedef struct                      /*!< Pinmux Structure */
+{
+    __IO uint32_t
+    CFG[10];                        /*!<  */
+} PINMUX_TypeDef;
+
+/* ================================================================================ */
+/* ================                      PWM                       ================ */
+/* ================================================================================ */
+
+/**
+  * @brief PWM
+  */
+typedef struct
+{
+    __IO uint32_t CR;               /*!< 0x00*/
+} PWM_TypeDef;
+
+/* ================================================================================ */
+/* ================                      QDEC                      ================ */
+/* ================================================================================ */
+
+/**
+  * @brief Rotary decoder. (QDEC)
+  */
+
+typedef struct                      /*!< QDEC Structure           */
+{
+    __IO uint32_t   REG_DIV;        /*!< 0x00 */
+    __IO uint32_t   REG_CR_X;       /*!< 0x04 */
+    __IO uint32_t   REG_SR_X;       /*!< 0x08 */
+    __IO uint32_t   REG_CR_Y;       /*!< 0x0C */
+    __IO uint32_t   REG_SR_Y;       /*!< 0x10 */
+    __IO uint32_t   REG_CR_Z;       /*!< 0x14 */
+    __IO uint32_t   REG_SR_Z;       /*!< 0x18 */
+    __IO uint32_t   INT_MASK;       /*!< 0x1C */
+    __IO uint32_t   INT_SR;         /*!< 0x20 */
+    __IO uint32_t   INT_CLR;        /*!< 0x24 */
+    __IO uint32_t   REG_DBG;        /*!< 0x28 */
+    __IO uint32_t   REG_VERSION;    /*!< 0x2C  */
+} QDEC_TypeDef;
+
+/* ================================================================================ */
+/* ================                      IF8080                      ================ */
+/* ================================================================================ */
+/**
+  * @brief IF8080
+  */
+typedef struct
+{
+    __IO uint32_t CTRL0;            /*!< 0x00 */
+    __IO uint32_t CTRL1;            /*!< 0x04 */
+    __IO uint32_t IMR;              /*!< 0x08 */
+    __I  uint32_t SR;               /*!< 0x0C */
+    __O  uint32_t ICR;              /*!< 0x10 */
+    __IO uint32_t CFG;              /*!< 0x14 */
+    __IO uint32_t FIFO;             /*!< 0x18 */
+    __I  uint32_t RESV0;            /*!< 0x1C */
+    __I  uint32_t RXDATA;           /*!< 0x20 */
+    __IO uint32_t TX_LEN;           /*!< 0x24 */
+    __I  uint32_t TX_CNT;           /*!< 0x28 */
+    __I  uint32_t RESV1;            /*!< 0x2C */
+    __IO uint32_t RX_LEN;           /*!< 0x30 */
+    __I  uint32_t RX_CNT;           /*!< 0x34 */
+    __IO uint32_t CMD1;             /*!< 0x38 */
+    __IO uint32_t CMD2;             /*!< 0x3C */
+    __IO uint32_t CMD3;             /*!< 0x40 */
+} IF8080_TypeDef;
+
+
+
+typedef struct
+{
+    __IO uint32_t SAR;
+    __IO uint32_t DAR;
+    __IO uint32_t LLP;
+    __IO uint32_t CTL_LOW;
+    __IO uint32_t CTL_HIGH;
+} IF8080_GDMALLITypeDef;
+
+
+
+typedef struct
+{
+    __IO uint32_t CR;
+    __IO uint32_t LLI;
+} IF8080_GDMATypeDef;
+
+
+
+
+typedef struct
+{
+    __IO uint32_t SAR_OFT;
+    __IO uint32_t DAR_OFT;
+} IF8080_GDMALLIOFTTypeDef;
+/* ================================================================================ */
+/* ================                       RTC                      ================ */
+/* ================================================================================ */
+
+/**
+  * @brief Real time counter 0. (RTC)
+  */
+typedef struct                      /*!< RTC Structure */
+{
+    __IO uint32_t CR0;              /*!< 0x00 */
+    __IO uint32_t INT_CLR;          /*!< 0x04 */
+    __IO uint32_t INT_SR;           /*!< 0x08 */
+    __IO uint32_t PRESCALER;        /*!< 0x0C */
+    __IO uint32_t COMP0;            /*!< 0x10 */
+    __IO uint32_t COMP1;            /*!< 0x14 */
+    __IO uint32_t COMP2;            /*!< 0x18 */
+    __IO uint32_t COMP3;            /*!< 0x1C */
+    __IO uint32_t COMP0GT;          /*!< 0x20 */
+    __IO uint32_t COMP1GT;          /*!< 0x24 */
+    __IO uint32_t COMP2GT;          /*!< 0x28 */
+    __IO uint32_t COMP3GT;          /*!< 0x2C */
+    __I  uint32_t CNT;              /*!< 0x30 */
+    __IO uint32_t PRE_CNT;          /*!< 0x34 */
+    __IO uint32_t PRE_COMP;         /*!< 0x38 */
+    __IO uint32_t BACKUP;           /*!< 0x3C */
+} RTC_TypeDef;
+
+/* ================================================================================ */
+/* ================                 2WIRE_SPI                      ================ */
+/* ================================================================================ */
+
+/**
+  * @brief 2wire spi, mostly used with mouse sensor. (2WIRE_SPI)
+  */
+
+typedef struct                                      /*!< 3WIRE_SPI Structure */
+{
+    __IO  uint32_t RSVD0[12];       /*!< 0x00 -- 0x2C for Q-decode */
+    __IO  uint32_t CFGR;            /*!< 0x30 */
+    __IO  uint32_t CR;
+    __IO  uint32_t INTCR;
+    __I   uint32_t SR;
+    __IO  uint32_t RD0;             /*!< 0x40 */
+    __IO  uint32_t RD1;
+    __IO  uint32_t RD2;
+    __IO  uint32_t RD3;
+} SPI3WIRE_TypeDef;
+
+/* ================================================================================ */
+/* ================                       SPI                      ================ */
+/* ================================================================================ */
+
+/**
+  * @brief SPI master 0. (SPI)
+  */
+typedef struct                                          /*!< SPI Structure  */
+{
+    __IO  uint32_t    CTRLR0;                              /*!< 0x00 */
+    __IO  uint32_t    CTRLR1;                              /*!< 0x04 */
+    __IO  uint32_t    SSIENR;                              /*!< 0x08 */
+    __IO  uint32_t    RSVD_0C;                             /*!< 0x0C */
+    __IO  uint32_t    SER;                                 /*!< 0x10 */
+    __IO  uint32_t    BAUDR;                               /*!< 0x14 */
+    __IO  uint32_t    TXFTLR;                              /*!< 0x18 */
+    __IO  uint32_t    RXFTLR;                              /*!< 0x1C */
+    __I  uint32_t    TXFLR;                                /*!< 0x20 */
+    __I  uint32_t    RXFLR;                                /*!< 0x24 */
+    __I  uint32_t    SR;                                   /*!< 0x28 */
+    __IO  uint32_t    IMR;                                 /*!< 0x2C */
+    __I  uint32_t    ISR;                                  /*!< 0x30 */
+    __I  uint32_t    RISR;                                 /*!< 0x34 */
+    __I  uint32_t    TXOICR;                               /*!< 0x38 */
+    __I  uint32_t    RXOICR;                               /*!< 0x3C */
+    __I  uint32_t    RXUICR;                               /*!< 0x40 */
+    __I  uint32_t    FAEICR;/*RSVD_44;*/                   /*!< 0x44 */
+    __I  uint32_t    ICR;                                  /*!< 0x48 */
+    __IO  uint32_t    DMACR;                               /*!< 0x4C */
+    __IO  uint32_t    DMATDLR;                             /*!< 0x50 */
+    __IO  uint32_t    DMARDLR;                             /*!< 0x54 */
+    __I  uint32_t    TXUICR;/*IDR;*/                       /*!< 0x58 */
+    __I  uint32_t    SSRICR;                               /*!< 0x5C */
+    __IO  uint32_t    DR[36];                              /*!< 0x60 - 0xEC */
+    __IO  uint32_t    RX_SAMPLE_DLY;                       /*!< 0xF0 */
+} SPI_TypeDef;
+
+/* ================================================================================ */
+/* ================                      TIM                      ================ */
+/* ================================================================================ */
+
+/**
+  * @brief TIM
+  */
+typedef struct
+{
+    __IO uint32_t LoadCount;        /*!< 0x00*/
+    __I  uint32_t CurrentValue;     /*!< 0x04*/
+    __IO uint32_t ControlReg;       /*!< 0x08*/
+    __I  uint32_t EOI;              /*!< 0x0C*/
+    __I  uint32_t IntStatus;        /*!< 0x10*/
+} TIM_TypeDef;
+
+/* ================================================================================ */
+/* ================                      ENH_TIM                   ================ */
+/* ================================================================================ */
+
+/**
+  * @brief ENHTIMER
+  */
+typedef struct
+{
+    __O  uint32_t CUR_CNT;          /*!< 0x00*/
+    __O  uint32_t LATCH_CNT0;       /*!< 0x04*/
+    __O  uint32_t LATCH_CNT1;       /*!< 0x08*/
+    __O  uint32_t LATCH_CNT2;       /*!< 0x0C*/
+    __IO uint32_t CR;               /*!< 0x10*/
+    __IO uint32_t MAX_CNT;          /*!< 0x14*/
+    __IO uint32_t CCR;              /*!< 0x18*/
+    __IO uint32_t CCR_FIFO;         /*!< 0x1C*/
+} ENHTIM_TypeDef;
+
+/**
+  * @brief ENHTIMER
+  */
+typedef struct
+{
+    __O  uint32_t FIFO_SR0;         /*!< 0x00*/
+    __O  uint32_t RSVD0;            /*!< 0x04*/
+    __O  uint32_t FIFO_SR2;         /*!< 0x08*/
+    __IO uint32_t FIFO_CLR;         /*!< 0x0C*/
+    __IO uint32_t CMD;              /*!< 0x10*/
+    __IO uint32_t INT_CMD;          /*!< 0x14*/
+    __IO uint32_t INT_SR;           /*!< 0x18*/
+    __O  uint32_t MASK_INT_SR;      /*!< 0x1C*/
+    __IO uint32_t LC_INT_CMD0;      /*!< 0x20*/
+    __IO uint32_t RSVD1;            /*!< 0x24*/
+    __IO uint32_t LC_INT_CMD2;      /*!< 0x28*/
+    __IO uint32_t RSVD2;            /*!< 0x2C*/
+    __O  uint32_t LC_FIFO_LEVEL0;   /*!< 0x30*/
+    __O  uint32_t LC_FIFO_LEVEL1;   /*!< 0x34*/
+
+} ENHTIM_ShareTypeDef;
+
+/* ================================================================================ */
+/* ================                      UART                      ================ */
+/* ================================================================================ */
+
+/**
+  * @brief Universal Asynchronous Receiver/Transmitter, version 1.0. (UART)
+  */
+
+typedef struct                      /*!< UART Structure */
+{
+    __IO  uint32_t DLL;
+    __IO  uint32_t DLH_INTCR;
+    __IO  uint32_t INTID_FCR;
+    __IO  uint32_t LCR;
+    __IO  uint32_t MCR;             /*!<0x10 */
+    __IO  uint32_t LSR;
+    __I   uint32_t MSR;
+    __IO  uint32_t SPR;
+    __IO  uint32_t STSR;            /*!<0x20 */
+    __IO  uint32_t RB_THR;
+    __IO  uint32_t MISCR;           /*!<may not be seen for client */
+    __IO  uint32_t TXPLSR;
+    __IO  uint32_t RSVD0;           /*!<0x30 */
+    __IO  uint32_t RSVD1;           /*!<0x34 */
+    __IO  uint32_t RSVD2;           /*!<0x38 */
+    __IO  uint32_t DBG_UART;        /*!<0x3C */
+    __IO  uint32_t RX_IDLE_TOCR;    /*!<0x40 */
+    __IO  uint32_t RX_IDLE_INTSR;
+    __IO  uint32_t RX_IDLE_INTCR;
+    __I   uint32_t FIFO_LEVEL;
+    __IO  uint32_t INTMASK;         /*!<0x50 */
+    __I   uint32_t TX_DONE_INTSR;
+    __I   uint32_t TX_THR_INTSR;
+} UART_TypeDef;
+
+typedef enum
+{
+    LOG_CHANNEL_UART0,
+    LOG_CHANNEL_UART1,
+    LOG_CHANNEL_UART2
+} LogChannel_TypeDef;
+
+/* ================================================================================ */
+/* ================                     Watch Dog                  ================ */
+/* ================================================================================ */
+
+/**
+  * @brief Watch Dog. (WDG)
+  */
+
+typedef struct                      /*!< WDG Structure           */
+{
+    __IO uint32_t WDG_CTL;          /*!< 0x00 */
+} WDG_TypeDef;
+
+/**
+  * @brief AON Watchdog
+  */
+typedef struct
+{
+    union
+    {
+        __IO uint32_t CRT; /*!< 0x00 (R/W) Control Register                                       */
+        struct
+        {
+            uint32_t EN: 2;     /*!< R/W WDT2 Enable, 2'b10: OFF, the other value: ON             */
+            uint32_t CNT_CTL: 1; /*!< R/W Counter Control,
+                                     1: WDG continue count in DLPS/Power Down/Hibernate,
+                                     0: WDG stop count in DLPS/Power Down/Hibernate               */
+            uint32_t RST_LVL: 1; /*!< R/W Reset Level,
+                                   1: Level 2 reset (reset whole chip),
+                                   0: Level 1 reset (reset whole chip except partial AON and RTC) */
+            uint32_t CNT_RELOAD: 1; /*!< R/W Reload Counter,
+                                        1: Reload counter when exit DLPS/Power Down/Hibernate,
+                                        0: Not reload counter when exit DLPS/Power Down/Hibernate */
+            uint32_t RSVD0: 3;
+            uint32_t COMP: 18;  /*!< R/W Set the period of AON WDG : 1/450Hz ~ 1/2.3KHz           */
+            uint32_t RSVD1: 6;
+        } CRT_BITS;
+    } u;
+    __IO uint32_t CNT_CLR; /*!< 0x04 (R/W) Clear Register, write 1 to reload AON WDG counter      */
+    __IO uint32_t WP;      /*!< 0x08 (R/W) Write Protect Register, write 1 to enable write CRT    */
+} AON_WDG_TypeDef;
+
+/* ================================================================================ */
+/* ================                     random generator           ================ */
+/* ================================================================================ */
+
+/**
+  * @brief random generator. (RAN_GEN)
+  */
+
+typedef struct                                      /*!< RAN_GEN Structure */
+{
+    union
+    {
+        __IO uint32_t CTL;                                        /*!< 0x00              */
+        struct
+        {
+            __IO uint32_t rand_gen_en: 1;
+            __IO uint32_t seed_upd: 1;
+            __IO uint32_t random_req: 1;
+            __IO uint32_t opt_rand_upd: 1;
+            __IO uint32_t soft_rst: 1;
+            __IO uint32_t rsvd: 27;
+        } CTL_BITS;
+    } u;
+    __IO uint32_t POLYNOMIAL;                                     /*!< 0x04              */
+    __IO uint32_t SEED;                                           /*!< 0x08              */
+    __IO uint32_t RAN_NUM;                                        /*!< 0x0C              */
+} RAN_GEN_TypeDef;
+
+/* ================================================================================ */
+/* ================            System Block Control            ================ */
+/* ================================================================================ */
+
+/**
+  * @brief System Block Control. (SYS_BLKCTRL)
+  */
+typedef struct                                          /*!< SYS_BLKCTRL Structure      */
+{
+    /* 0x0200       0x4000_0200
+        0       R/W    r_cpu_slow_en                       0
+        1       R/W    r_cpu_slow_opt_wfi                  0
+        2       R/W    r_cpu_slow_opt_at_tx                1
+        3       R/W    r_cpu_slow_opt_at_rx                1
+        4       R/W    r_cpu_slow_opt_lcd                  0
+        5       R/W    r_auto_slow_opt                     0
+        6       W1O    reg_zone1_wrp_en                    0
+        7       W1O    reg_zone2_wrp_en                    0
+        8       W1O    reg_wrp_lock                        0
+        12:9    R/W    r_cpu_low_rate_valid_num            4'h3
+        13      R/W    r_cpu_auto_slow_force_update        0
+        14      R/W    r_cpu_slow_opt_spi0                 0
+        18:15   R/W    r_cpu_low_rate_valid_num1           4'h3
+        24:19   R/W    r_bt_ahb_wait_cnt                   6'h0C
+        27:25   R/W    DUMMY                               3'h0
+        28      R/W    r_aon_rd_opt                        1
+        29      R/W    r_btaon_acc_no_block                0
+        30      R/W    bzdma_autoslow_eco_disable          0
+        31      R/W    r_clk_cpu_32k_en                    0
+    */
+    union
+    {
+        __IO uint32_t PERION_REG_SYS_CLK_SEL_0;
+        struct
+        {
+            __IO uint32_t r_cpu_slow_en: 1;
+            __IO uint32_t r_cpu_slow_opt_wfi: 1;
+            __IO uint32_t r_cpu_slow_opt_at_tx: 1;
+            __IO uint32_t r_cpu_slow_opt_at_rx: 1;
+            __IO uint32_t r_cpu_slow_opt_lcd: 1;
+            __IO uint32_t r_auto_slow_opt: 1;
+            __IO uint32_t reg_zone1_wrp_en: 1;
+            __IO uint32_t reg_zone2_wrp_en: 1;
+            __IO uint32_t reg_wrp_lock: 1;
+            __IO uint32_t r_cpu_low_rate_valid_num: 4;
+            __IO uint32_t r_cpu_auto_slow_force_update: 1;
+            __IO uint32_t r_cpu_slow_opt_spi0: 1;
+            __IO uint32_t r_cpu_low_rate_valid_num1: 4;
+            __IO uint32_t r_bt_ahb_wait_cnt: 6;
+            __IO uint32_t RESERVED_0: 3;
+            __IO uint32_t r_aon_rd_opt: 1;
+            __IO uint32_t r_btaon_acc_no_block: 1;
+            __IO uint32_t bzdma_autoslow_eco_disable: 1;
+            __IO uint32_t r_clk_cpu_32k_en: 1;
+        } BITS_200;
+    } u_200;
+
+    /* 0x0204       0x4000_0204
+        3:0     R      RF_RL_ID                            4'd0
+        7:4     R      RF_RTL_ID                           4'd0
+        31:8    R      RSVD                                24'd0
+    */
+    union
+    {
+        __IO uint32_t PERION_REG_ID;
+        struct
+        {
+            __I uint32_t RF_RL_ID: 4;
+            __I uint32_t RF_RTL_ID: 4;
+            __I uint32_t RESERVED_0: 24;
+        } BITS_204;
+    } u_204;
+
+    /* 0x0208       0x4000_0208
+        3:0     R/W    r_cpu_div_sel                       4'h0
+        7:4     R/W    r_cpu_div_sel_slow                  4'h0
+        8       R/W    r_cpu_div_en                        1
+        9       R/W    r_CPU_CLK_SRC_EN                    1
+        10      R/W    r_cpu_auto_slow_filter_en           1
+        11      R/W    r_cpu_clk_mux_0_cg_en               1
+        12      R/W    DUMMY                               1
+        13      R/W    r_cpu_xtal_clk_cg_en                1
+        14      R/W    r_cpu_ocs40_clk_cg_en               1
+        15      R/W    r_cpu_div_en_slow                   1
+        16      W1O    DUMMY                               0
+        17      W1O    r_cpu_div_sel_opt                   0
+        18      W1O    r_spi0_div_sel_opt                  0
+        19      W1O    r_spi1_div_sel_opt                  0
+        20      W1O    RSVD                                0
+        21      W1O    RSVD                                0
+        22      W1O    RSVD                                0
+        23      W1O    r_spi0_div_sel_opt1                 0
+        24      W1O    r_spi1_div_sel_opt1                 0
+        25      W1O    DUMMY                               0
+        26      W1O    DUMMY                               0
+        27      R/W    r_CKE_SYSON                         0
+        28      R/W    r_cpu_auto_slow_filter1_en          0
+        31:29   R/W    DUMMY                               3'h0
+    */
+    union
+    {
+        __IO uint32_t PERION_REG_SYS_CLK_SEL_1;
+        struct
+        {
+            __IO uint32_t r_cpu_div_sel: 4;
+            __IO uint32_t r_cpu_div_sel_slow: 4;
+            __IO uint32_t r_cpu_div_en: 1;
+            __IO uint32_t r_CPU_CLK_SRC_EN: 1;
+            __IO uint32_t r_cpu_auto_slow_filter_en: 1;
+            __IO uint32_t r_cpu_clk_mux_0_cg_en: 1;
+            __IO uint32_t RESERVED_7: 1;
+            __IO uint32_t r_cpu_xtal_clk_cg_en: 1;
+            __IO uint32_t r_cpu_ocs40_clk_cg_en: 1;
+            __IO uint32_t r_cpu_div_en_slow: 1;
+            __IO uint32_t RESERVED_6: 1;
+            __IO uint32_t r_cpu_div_sel_opt: 1;
+            __IO uint32_t r_spi0_div_sel_opt: 1;
+            __IO uint32_t r_spi1_div_sel_opt: 1;
+            __IO uint32_t RESERVED_5: 1;
+            __IO uint32_t RESERVED_4: 1;
+            __IO uint32_t RESERVED_3: 1;
+            __IO uint32_t r_spi0_div_sel_opt1: 1;
+            __IO uint32_t r_spi1_div_sel_opt1: 1;
+            __IO uint32_t RESERVED_2: 1;
+            __IO uint32_t RESERVED_1: 1;
+            __IO uint32_t r_CKE_SYSON: 1;
+            __IO uint32_t r_cpu_auto_slow_filter1_en: 1;
+            __IO uint32_t RESERVED_0: 3;
+        } BITS_208;
+    } u_208;
+
+    /* 0x020C       0x4000_020c
+        1:0     R/W    r_flash_div_sel                     2'h0
+        3:2     R/W    DUMMY                               2'h0
+        4       R/W    r_flash_div_en                      0
+        5       R/W    r_FLASH_CLK_SRC_EN                  1
+        6       R/W    r_flash_clk_src_sel_1               0
+        7       R/W    r_flash_clk_src_sel_0               0
+        8       R/W    r_flash_mux_1_clk_cg_en             1
+        9       R/W    r_rng_sfosc_sel                     0
+        12:10   R/W    r_rng_sfosc_div_sel                 3'h0
+        15:13   R/W    DUMMY                               0
+        18:16   R/W    DUMMY                               3'h0
+        19      R/W    DUMMY                               0
+        20      R/W    DUMMY                               0
+        21      R/W    DUMMY                               1
+        22      R/W    r_CLK_40M_SRC_EN                    1
+        23      R/W    DUMMY                               0
+        24      R/W    r_40m_clk_src_sel_0                 1
+        25      R/W    DUMMY                               0
+        26      R/W    r_CLK_40M_SRC_DIV_EN                1
+        27      R/W    r_CLK_20M_SRC_EN                    0
+        28      R/W    r_CLK_10M_SRC_EN                    1
+        29      R/W    r_CLK_5M_SRC_EN                     0
+        31:30   R/W    DUMMY                               2'h0
+    */
+    union
+    {
+        __IO uint32_t PERION_REG_SYS_CLK_SEL_2;
+        struct
+        {
+            __IO uint32_t r_flash_div_sel: 2;
+            __IO uint32_t RESERVED_8: 2;
+            __IO uint32_t r_flash_div_en: 1;
+            __IO uint32_t r_FLASH_CLK_SRC_EN: 1;
+            __IO uint32_t r_flash_clk_src_sel_1: 1;
+            __IO uint32_t r_flash_clk_src_sel_0: 1;
+            __IO uint32_t r_flash_mux_1_clk_cg_en: 1;
+            __IO uint32_t r_rng_sfosc_sel: 1;
+            __IO uint32_t r_rng_sfosc_div_sel: 3;
+            __IO uint32_t RESERVED_7: 3;
+            __IO uint32_t RESERVED_6: 3;
+            __IO uint32_t RESERVED_5: 1;
+            __IO uint32_t RESERVED_4: 1;
+            __IO uint32_t RESERVED_3: 1;
+            __IO uint32_t r_CLK_40M_SRC_EN: 1;
+            __IO uint32_t RESERVED_2: 1;
+            __IO uint32_t r_40m_clk_src_sel_0: 1;
+            __IO uint32_t RESERVED_1: 1;
+            __IO uint32_t r_CLK_40M_SRC_DIV_EN: 1;
+            __IO uint32_t r_CLK_20M_SRC_EN: 1;
+            __IO uint32_t r_CLK_10M_SRC_EN: 1;
+            __IO uint32_t r_CLK_5M_SRC_EN: 1;
+            __IO uint32_t RESERVED_0: 2;
+        } BITS_20C;
+    } u_20C;
+
+    /* 0x210        0x4000_0210
+        0       R/W    DUMMY                               0
+        1       R/W    DUMMY                               0
+        2       R/W    r_PON_FEN_LXBUS                     1
+        3       R/W    r_PON_FEN_FLASH1                    0
+        4       R/W    r_PON_FEN_FLASH                     1
+        5       R/W    DUMMY                               1
+        6       R/W    DUMMY                               0
+        7       R/W    r_PON_FEN_SHA256                    0
+        8       R/W    r_PON_FEN_FLH_SEC                   0
+        9       R/W    r_PON_FEN_MODEMRFCPI                0
+        10      R/W    r_PON_FEN_BLUEWIZ                   0
+        11      R/W    r_PON_FEN_ZIGBEE                    0
+        12      R/W    r_PON_FEN_UART0                     0
+        13      R/W    r_PON_FEN_GDMA0                     0
+        14      R/W    DUMMY                               0
+        15      R/W    DUMMY                               0
+        16      R/W    r_PON_FEN_TIMER                     0
+        19:17   R/W    DUMMY                               0
+        20      R/W    r_PON_FEN_AAC_XTAL                  0
+        21      R/W    DUMMY                               0
+        22      R/W    DUMMY                               0
+        23      R/W    DUMMY                               0
+        31:24   R      DUMMY                               8'd0
+    */
+    union
+    {
+        __IO uint32_t PERION_REG_SOC_FUNC_EN;
+        struct
+        {
+            __IO uint32_t RESERVED_10: 1;
+            __IO uint32_t RESERVED_9: 1;
+            __IO uint32_t r_PON_FEN_LXBUS: 1;
+            __IO uint32_t r_PON_FEN_FLASH1: 1;
+            __IO uint32_t r_PON_FEN_FLASH: 1;
+            __IO uint32_t RESERVED_8: 1;
+            __IO uint32_t RESERVED_7: 1;
+            __IO uint32_t r_PON_FEN_SHA256: 1;
+            __IO uint32_t r_PON_FEN_FLH_SEC: 1;
+            __IO uint32_t r_PON_FEN_MODEMRFCPI: 1;
+            __IO uint32_t r_PON_FEN_BLUEWIZ: 1;
+            __IO uint32_t r_PON_FEN_ZIGBEE: 1;
+            __IO uint32_t r_PON_FEN_UART0: 1;
+            __IO uint32_t r_PON_FEN_GDMA0: 1;
+            __IO uint32_t RESERVED_6: 1;
+            __IO uint32_t RESERVED_5: 1;
+            __IO uint32_t r_PON_FEN_TIMER: 1;
+            __IO uint32_t RESERVED_4: 3;
+            __IO uint32_t r_PON_FEN_AAC_XTAL: 1;
+            __IO uint32_t RESERVED_3: 1;
+            __IO uint32_t RESERVED_2: 1;
+            __IO uint32_t RESERVED_1: 1;
+            __I uint32_t RESERVED_0: 8;
+        } BITS_210;
+    } u_210;
+
+    /* 0x0214       0x4000_0214
+        31:0    R      RSVD                                32'hEAEAEAEA
+    */
+    __IO uint32_t PERION_REG_RSVD_214;
+
+    /* 0x0218       0x4000_0218
+        0       R/W    r_PON_FEN_UART1                     0
+        1       R/W    r_PON_FEN_UART2                     0
+        2       R/W    r_PON_FEN_AES                       0
+        3       R/W    r_PON_FEN_RNG                       0
+        7:4     R/W    DUMMY                               4'h0
+        8       R/W    r_PON_FEN_SPI0                      0
+        9       R/W    r_PON_FEN_SPI1                      0
+        10      R/W    r_PON_FEN_IRRC                      0
+        15:11   R/W    DUMMY                               5'd0
+        16      R/W    r_PON_FEN_I2C0                      0
+        17      R/W    r_PON_FEN_I2C1                      0
+        18      R/W    r_PON_FEN_QDEC                      0
+        19      R/W    r_PON_FEN_KEYSCAN                   0
+        23:20   R/W    DUMMY                               4'h0
+        24      R/W    r_PON_FEN_SPI2W                     0
+        25      R/W    r_PON_FEN_LCD                       0
+        26      R/W    r_PON_FEN_DSP_IPC                   1
+        27      R/W    r_PON_FEN_DSP_MEM                   1
+        28      R/W    r_PON_FEN_ASRC                      0
+        29      R/W    r_PON_FEN_DSP_WDT                   0
+        30      R/W    r_PON_FEN_EFUSE                     0
+        31      R/W    DUMMY                               0
+    */
+    union
+    {
+        __IO uint32_t PERION_REG_SOC_PERI_FUNC0_EN;
+        struct
+        {
+            __IO uint32_t r_PON_FEN_UART1: 1;
+            __IO uint32_t r_PON_FEN_UART2: 1;
+            __IO uint32_t r_PON_FEN_AES: 1;
+            __IO uint32_t r_PON_FEN_RNG: 1;
+            __IO uint32_t RESERVED_3: 4;
+            __IO uint32_t r_PON_FEN_SPI0: 1;
+            __IO uint32_t r_PON_FEN_SPI1: 1;
+            __IO uint32_t r_PON_FEN_IRRC: 1;
+            __IO uint32_t RESERVED_2: 5;
+            __IO uint32_t r_PON_FEN_I2C0: 1;
+            __IO uint32_t r_PON_FEN_I2C1: 1;
+            __IO uint32_t r_PON_FEN_QDEC: 1;
+            __IO uint32_t r_PON_FEN_KEYSCAN: 1;
+            __IO uint32_t RESERVED_1: 4;
+            __IO uint32_t r_PON_FEN_SPI2W: 1;
+            __IO uint32_t r_PON_FEN_LCD: 1;
+            __IO uint32_t r_PON_FEN_DSP_IPC: 1;
+            __IO uint32_t r_PON_FEN_DSP_MEM: 1;
+            __IO uint32_t r_PON_FEN_ASRC: 1;
+            __IO uint32_t r_PON_FEN_DSP_WDT: 1;
+            __IO uint32_t r_PON_FEN_EFUSE: 1;
+            __IO uint32_t RESERVED_0: 1;
+        } BITS_218;
+    } u_218;
+
+    /* 0x021C       0x4000_021c
+        0       R/W    r_PON_FEN_ADC0                      0
+        7:1     R/W    DUMMY                               6'd0
+        8       R/W    r_PON_FEN_GPIO0                     0
+        31 :9   R/W    DUMMY                               23'd0
+    */
+    union
+    {
+        __IO uint32_t PERION_REG_SOC_PERI_FUNC1_EN;
+        struct
+        {
+            __IO uint32_t r_PON_FEN_ADC0: 1;
+            __IO uint32_t RESERVED_1: 7;
+            __IO uint32_t r_PON_FEN_GPIO0: 1;
+            __IO uint32_t RESERVED_0: 23;
+        } BITS_21C;
+    } u_21C;
+
+    /* 0x0220       0x4000_0220
+        0       R/W    r_PON_FEN_AUDIO                     0
+        1       R/W    r_PON_FEN_SPORT0                    0
+        2       R/W    DUMMY                               0
+        3       R/W    DUMMY                               0
+        4       R/W    r_CLK_EN_AUDIO                      0
+        5       R/W    r_CLK_EN_SPORT0                     0
+        6       R/W    DUMMY                               0
+        7       R/W    DUMMY                               0
+        8       R/W    r_CLK_EN_SPORT_40M                  0
+        9       R/W    r_CLK_EN_AUDIO_REG                  1
+        31:10   R/W    DUMMY                               22'd0
+    */
+    union
+    {
+        __IO uint32_t PERION_REG_SOC_AUDIO_IF_EN;
+        struct
+        {
+            __IO uint32_t r_PON_FEN_AUDIO: 1;
+            __IO uint32_t r_PON_FEN_SPORT0: 1;
+            __IO uint32_t RESERVED_4: 1;
+            __IO uint32_t RESERVED_3: 1;
+            __IO uint32_t r_CLK_EN_AUDIO: 1;
+            __IO uint32_t r_CLK_EN_SPORT0: 1;
+            __IO uint32_t RESERVED_2: 1;
+            __IO uint32_t RESERVED_1: 1;
+            __IO uint32_t r_CLK_EN_SPORT_40M: 1;
+            __IO uint32_t r_CLK_EN_AUDIO_REG: 1;
+            __IO uint32_t RESERVED_0: 22;
+        } BITS_220;
+    } u_220;
+
+    /* 0x0224       0x4000_0224
+        2:0     R/W    DUMMY                               3'h4
+        3       R/W    r_SPORT0_EXT_CODEC                  0
+        6:4     R/W    DUMMY                               3'h1
+        7       R/W    r_CODEC_STANDALONE                  0
+        31:8    R/W    DUMMY                               24'd0
+    */
+    union
+    {
+        __IO uint32_t PERION_REG_SOC_AUDIO_CLK_CTRL_A;
+        struct
+        {
+            __IO uint32_t RESERVED_2: 3;
+            __IO uint32_t r_SPORT0_EXT_CODEC: 1;
+            __IO uint32_t RESERVED_1: 3;
+            __IO uint32_t r_CODEC_STANDALONE: 1;
+            __IO uint32_t RESERVED_0: 24;
+        } BITS_224;
+    } u_224;
+
+    /* 0x0228       0x4000_0228
+        3:0     R/W    DUMMY                               4'h1
+        4       R/W    r_SPORT0_MCLK_OUT                   0
+        6:5     R/W    DUMMY                               0
+        7       R/W    DUMMY                               0
+        31:8    R/W    DUMMY                               24'd0
+    */
+    union
+    {
+        __IO uint32_t PERION_REG_SOC_AUDIO_CLK_CTRL_B;
+        struct
+        {
+            __IO uint32_t RESERVED_3: 4;
+            __IO uint32_t r_SPORT0_MCLK_OUT: 1;
+            __IO uint32_t RESERVED_2: 2;
+            __IO uint32_t RESERVED_1: 1;
+            __IO uint32_t RESERVED_0: 24;
+        } BITS_228;
+    } u_228;
+
+    /* 0x022C       0x4000_022c
+        31:0    R      RSVD                                32'hEAEAEAEA
+    */
+    __IO uint32_t PERION_REG_RSVD_22C;
+
+    /* 0x0230       0x4000_0230
+        0       R/W    DUMMY                               1
+        1       R/W    DUMMY                               0
+        2       R/W    r_PON_CKE_PLFM                      1
+        3       R/W    DUMMY                               1
+        4       R/W    r_CKE_BUS_RAM_SLP                   0
+        5       R/W    r_CKE_BT_VEN                        1
+        6       R/W    r_PON_ACTCKE_VDREG                  0
+        7       R/W    r_PON_SLPCKE_VDREG                  0
+        8       R/W    r_PON_ACTCKE_FLASH                  1
+        9       R/W    r_PON_SLPCKE_FLASH                  0
+        10      R/W    r_PON_ACTCKE_UART2                  0
+        11      R/W    r_PON_SLPCKE_UART2                  0
+        12      R/W    r_PON_ACTCKE_UART0                  0
+        13      R/W    r_PON_SLPCKE_UART0                  0
+        14      R/W    r_PON_ACTCKE_TIMER                  0
+        15      R/W    r_PON_SLPCKE_TIMER                  0
+        16      R/W    r_PON_ACTCKE_GDMA0                  0
+        17      R/W    r_PON_SLPCKE_GDMA0                  0
+        23:18   R/W    DUMMY                               6'd0
+        24      R/W    r_PON_ACTCKE_GPIO                   0
+        25      R/W    r_PON_SLPCKE_GPIO                   0
+        26      R/W    DUMMY                               0
+        27      R/W    DUMMY                               0
+        28      R/W    DUMMY                               0
+        29      R/W    DUMMY                               0
+        30      R/W    DUMMY                               0
+        31      R/W    DUMMY                               0
+    */
+    union
+    {
+        __IO uint32_t PERION_REG_PESOC_CLK_CTRL;
+        struct
+        {
+            __IO uint32_t RESERVED_9: 1;
+            __IO uint32_t RESERVED_8: 1;
+            __IO uint32_t r_PON_CKE_PLFM: 1;
+            __IO uint32_t RESERVED_7: 1;
+            __IO uint32_t r_CKE_BUS_RAM_SLP: 1;
+            __IO uint32_t r_CKE_BT_VEN: 1;
+            __IO uint32_t r_PON_ACTCKE_VDREG: 1;
+            __IO uint32_t r_PON_SLPCKE_VDREG: 1;
+            __IO uint32_t r_PON_ACTCKE_FLASH: 1;
+            __IO uint32_t r_PON_SLPCKE_FLASH: 1;
+            __IO uint32_t r_PON_ACTCKE_UART2: 1;
+            __IO uint32_t r_PON_SLPCKE_UART2: 1;
+            __IO uint32_t r_PON_ACTCKE_UART0: 1;
+            __IO uint32_t r_PON_SLPCKE_UART0: 1;
+            __IO uint32_t r_PON_ACTCKE_TIMER: 1;
+            __IO uint32_t r_PON_SLPCKE_TIMER: 1;
+            __IO uint32_t r_PON_ACTCKE_GDMA0: 1;
+            __IO uint32_t r_PON_SLPCKE_GDMA0: 1;
+            __IO uint32_t RESERVED_6: 6;
+            __IO uint32_t r_PON_ACTCKE_GPIO: 1;
+            __IO uint32_t r_PON_SLPCKE_GPIO: 1;
+            __IO uint32_t RESERVED_5: 1;
+            __IO uint32_t RESERVED_4: 1;
+            __IO uint32_t RESERVED_3: 1;
+            __IO uint32_t RESERVED_2: 1;
+            __IO uint32_t RESERVED_1: 1;
+            __IO uint32_t RESERVED_0: 1;
+        } BITS_230;
+    } u_230;
+
+    /* 0x0234       0x4000_0234
+        0       R/W    r_PON_ACTCKE_UART1                  0
+        1       R/W    r_PON_SLPCKE_UART1                  0
+        2       R/W    DUMMY                               0
+        3       R/W    DUMMY                               0
+        4       R/W    r_CKE_MODEM                         1
+        5       R/W    r_CKE_CAL32K                        0
+        6       R/W    r_CKE_RNG                           0
+        7       R/W    DUMMY                               0
+        8       R/W    DUMMY                               0
+        9       R/W    r_CKE_PDCK                          0
+        10      R/W    r_CKE_AAC_XTAL                      0
+        11      R/W    r_PON_CKE_BT_FREQ_DET               0
+        12      R/W    DUMMY                               0
+        13      R/W    DUMMY                               0
+        14      R/W    DUMMY                               0
+        15      R/W    DUMMY                               0
+        16      R/W    r_PON_ACTCK_SPI0                    0
+        17      R/W    r_PON_SLPCK_SPI0                    0
+        18      R/W    r_PON_ACTCK_SPI1                    0
+        19      R/W    r_PON_SLPCK_SPI1                    0
+        20      R/W    r_PON_ACTCK_IRRC                    0
+        21      R/W    r_PON_SLPCKE_IRRC                   0
+        22      R/W    r_PON_ACTCKE_FLH_SEC                0
+        23      R/W    r_PON_SLPCKE_FLH_SEC                0
+        24      R/W    r_PON_ACTCKE_FLASH1                 0
+        25      R/W    r_PON_SLPCKE_FLASH1                 0
+        26      R/W    DUMMY                               0
+        27      R/W    DUMMY                               0
+        28      R/W    r_PON_ACTCKE_SHA256                 0
+        29      R/W    r_PON_SLPCKE_SHA256                 0
+        30      R/W    DUMMY                               0
+        31      R/W    DUMMY                               0
+    */
+    union
+    {
+        __IO uint32_t PERION_REG_PESOC_PERI_CLK_CTRL0;
+        struct
+        {
+            __IO uint32_t r_PON_ACTCKE_UART1: 1;
+            __IO uint32_t r_PON_SLPCKE_UART1: 1;
+            __IO uint32_t RESERVED_11: 1;
+            __IO uint32_t RESERVED_10: 1;
+            __IO uint32_t r_CKE_MODEM: 1;
+            __IO uint32_t r_CKE_CAL32K: 1;
+            __IO uint32_t r_CKE_RNG: 1;
+            __IO uint32_t RESERVED_9: 1;
+            __IO uint32_t RESERVED_8: 1;
+            __IO uint32_t r_CKE_PDCK: 1;
+            __IO uint32_t r_CKE_AAC_XTAL: 1;
+            __IO uint32_t r_PON_CKE_BT_FREQ_DET: 1;
+            __IO uint32_t RESERVED_7: 1;
+            __IO uint32_t RESERVED_6: 1;
+            __IO uint32_t RESERVED_5: 1;
+            __IO uint32_t RESERVED_4: 1;
+            __IO uint32_t r_PON_ACTCK_SPI0: 1;
+            __IO uint32_t r_PON_SLPCK_SPI0: 1;
+            __IO uint32_t r_PON_ACTCK_SPI1: 1;
+            __IO uint32_t r_PON_SLPCK_SPI1: 1;
+            __IO uint32_t r_PON_ACTCK_IRRC: 1;
+            __IO uint32_t r_PON_SLPCKE_IRRC: 1;
+            __IO uint32_t r_PON_ACTCKE_FLH_SEC: 1;
+            __IO uint32_t r_PON_SLPCKE_FLH_SEC: 1;
+            __IO uint32_t r_PON_ACTCKE_FLASH1: 1;
+            __IO uint32_t r_PON_SLPCKE_FLASH1: 1;
+            __IO uint32_t RESERVED_3: 1;
+            __IO uint32_t RESERVED_2: 1;
+            __IO uint32_t r_PON_ACTCKE_SHA256: 1;
+            __IO uint32_t r_PON_SLPCKE_SHA256: 1;
+            __IO uint32_t RESERVED_1: 1;
+            __IO uint32_t RESERVED_0: 1;
+        } BITS_234;
+    } u_234;
+
+    /* 0x0238       0x4000_0238
+        0       R/W    r_PON_ACTCKE_I2C0                   0
+        1       R/W    r_PON_SLPCKE_I2C0                   0
+        2       R/W    r_PON_ACTCKE_I2C1                   0
+        3       R/W    r_PON_SLPCKE_I2C1                   0
+        4       R/W    r_PON_ACTCKE_QDEC                   0
+        5       R/W    r_PON_SLPCKE_QDEC                   0
+        6       R/W    r_PON_ACTCKE_KEYSCAN                0
+        7       R/W    r_PON_SLPCKE_KEYSCAN                0
+        8       R/W    r_PON_ACTCKE_AES                    0
+        9       R/W    r_PON_SLPCKE_AES                    0
+        10      R/W    r_ACTCKE_ZIGBEE                     0
+        11      R/W    r_SLPCKE_ZIGBEE                     0
+        12      R/W    r_ACTCKE_BLUEWIZ                    0
+        13      R/W    r_SLPCKE_BLUEWIZ                    0
+        14      R/W    r_ACTCKE_MODEM                      0
+        15      R/W    r_SLPCKE_MODEM                      0
+        16      R/W    r_PON_ACTCKE_SPI2W                  0
+        17      R/W    r_PON_SLPCKE_SPI2W                  0
+        19:18   R/W    DUMMY                               2'h0
+        20      R/W    DUMMY                               0
+        21      R/W    DUMMY                               0
+        22      R/W    DUMMY                               0
+        23      R/W    DUMMY                               0
+        24      R/W    r_PON_ACTCKE_ADC                    0
+        25      R/W    r_PON_SLPCKE_ADC                    0
+        26      R/W    DUMMY                               0
+        27      R/W    DUMMY                               0
+        28      R/W    r_PON_ACTCK_LCD                     0
+        29      R/W    r_PON_SLPCK_LCD                     0
+        30      R/W    r_PON_CKE_DSP_WDT                   0
+        31      R/W    r_PON_CKE_EFUSE                     0
+    */
+    union
+    {
+        __IO uint32_t PERION_r_PON_PERI_CLK_CTRL1;
+        struct
+        {
+            __IO uint32_t r_PON_ACTCKE_I2C0: 1;
+            __IO uint32_t r_PON_SLPCKE_I2C0: 1;
+            __IO uint32_t r_PON_ACTCKE_I2C1: 1;
+            __IO uint32_t r_PON_SLPCKE_I2C1: 1;
+            __IO uint32_t r_PON_ACTCKE_QDEC: 1;
+            __IO uint32_t r_PON_SLPCKE_QDEC: 1;
+            __IO uint32_t r_PON_ACTCKE_KEYSCAN: 1;
+            __IO uint32_t r_PON_SLPCKE_KEYSCAN: 1;
+            __IO uint32_t r_PON_ACTCKE_AES: 1;
+            __IO uint32_t r_PON_SLPCKE_AES: 1;
+            __IO uint32_t r_ACTCKE_ZIGBEE: 1;
+            __IO uint32_t r_SLPCKE_ZIGBEE: 1;
+            __IO uint32_t r_ACTCKE_BLUEWIZ: 1;
+            __IO uint32_t r_SLPCKE_BLUEWIZ: 1;
+            __IO uint32_t r_ACTCKE_MODEM: 1;
+            __IO uint32_t r_SLPCKE_MODEM: 1;
+            __IO uint32_t r_PON_ACTCKE_SPI2W: 1;
+            __IO uint32_t r_PON_SLPCKE_SPI2W: 1;
+            __IO uint32_t RESERVED_6: 2;
+            __IO uint32_t RESERVED_5: 1;
+            __IO uint32_t RESERVED_4: 1;
+            __IO uint32_t RESERVED_3: 1;
+            __IO uint32_t RESERVED_2: 1;
+            __IO uint32_t r_PON_ACTCKE_ADC: 1;
+            __IO uint32_t r_PON_SLPCKE_ADC: 1;
+            __IO uint32_t RESERVED_1: 1;
+            __IO uint32_t RESERVED_0: 1;
+            __IO uint32_t r_PON_ACTCK_LCD: 1;
+            __IO uint32_t r_PON_SLPCK_LCD: 1;
+            __IO uint32_t r_PON_CKE_DSP_WDT: 1;
+            __IO uint32_t r_PON_CKE_EFUSE: 1;
+        } BITS_238;
+    } u_238;
+
+    /* 0x023C       0x4000_023c
+        31:0    R      RSVD                                32'hEAEAEAEA
+    */
+    __IO uint32_t PERION_REG_RSVD_23C;
+
+    /* 0x0240       0x4000_0240
+        31:0    R      RSVD                                32'hEAEAEAEA
+    */
+    __IO uint32_t PERION_REG_RSVD_240;
+
+    /* 0x0244       0x4000_0244
+        0       R/W    r_PON_ACTCKE_BTBUS                  1
+        1       R/W    r_PON_SLPCKE_BTBUS                  1
+        15:2    R/W    DUMMY                               14'h0
+        21:16   R/W    DUMMY                               6'h0
+        22      R/W    r_LS_mcu_rom                        0
+        23      R/W    DUMMY                               0
+        24      R/W    DUMMY                               0
+        31:25   R/W    DUMMY                               7'h0
+    */
+    union
+    {
+        __IO uint32_t PERION_r_OFF_MEM_PWR_CRTL_r_PON_COM_CLK_CTRL;
+        struct
+        {
+            __IO uint32_t r_PON_ACTCKE_BTBUS: 1;
+            __IO uint32_t r_PON_SLPCKE_BTBUS: 1;
+            __IO uint32_t RESERVED_4: 14;
+            __IO uint32_t RESERVED_3: 6;
+            __IO uint32_t r_LS_mcu_rom: 1;
+            __IO uint32_t RESERVED_2: 1;
+            __IO uint32_t RESERVED_1: 1;
+            __IO uint32_t RESERVED_0: 7;
+        } BITS_244;
+    } u_244;
+
+    /* 0x0248       0x4000_0248
+        31:0    R      RSVD                                32'hEAEAEAEA
+    */
+    __IO uint32_t PERION_REG_RSVD_248;
+
+    /* 0x024C       0x4000_024c
+        31:0    R      RSVD                                32'hEAEAEAEA
+    */
+    __IO uint32_t PERION_REG_RSVD_24C;
+
+    /* 0x0250       0x4000_0250
+        31:0    R      RSVD                                32'hEAEAEAEA
+    */
+    __IO uint32_t PERION_REG_RSVD_250;
+
+    /* 0x0254       0x4000_0254
+        7:0     R/W    DUMMY                               8'h1
+        13:8    R/W    DUMMY                               6'h0
+        14      R/W    DUMMY                               0
+        15      R/W    DUMMY                               0
+        31:16   R/W    DUMMY                               16'h0
+    */
+    union
+    {
+        __IO uint32_t PERION_r_DSP_TOP_CTRL;
+        struct
+        {
+            __IO uint32_t RESERVED_4: 8;
+            __IO uint32_t RESERVED_3: 6;
+            __IO uint32_t RESERVED_2: 1;
+            __IO uint32_t RESERVED_1: 1;
+            __IO uint32_t RESERVED_0: 16;
+        } BITS_254;
+    } u_254;
+
+    /* 0x0258       0x4000_0258
+        1:0     RW     CORE_XTAL_LPS_CAP_STEP              2'b01
+        3:2     RW     CORE_XTAL_LPS_CAP_CYC               2'b00
+        6:4     RW     CORE_XTAL_OV_UNIT                   3'b000
+        8:7     RW     CORE_XTAL_OV_RATIO                  2'b01
+        11:9    RW     CORE_XTAL_MODE                      3'b100
+        13:12   RW     CORE_XTAL_CTRL1_2t1                 2'b00
+        31:14   R      RSVD                                18'h0
+    */
+    union
+    {
+        __IO uint32_t PERION_CORE_SWR_PAR_TAB_0_1;
+        struct
+        {
+            __IO uint32_t CORE_XTAL_LPS_CAP_STEP: 2;
+            __IO uint32_t CORE_XTAL_LPS_CAP_CYC: 2;
+            __IO uint32_t CORE_XTAL_OV_UNIT: 3;
+            __IO uint32_t CORE_XTAL_OV_RATIO: 2;
+            __IO uint32_t CORE_XTAL_MODE: 3;
+            __IO uint32_t CORE_XTAL_CTRL1_2t1: 2;
+            __I uint32_t RESERVED_0: 18;
+        } BITS_258;
+    } u_258;
+
+    /* 0x025C       0x4000_025c
+        1:0     RW     CORE_XTAL_LPS_CAP_STEP              2'b01
+        3:2     RW     CORE_XTAL_LPS_CAP_CYC               2'b00
+        6:4     RW     CORE_XTAL_OV_UNIT                   3'b000
+        8:7     RW     CORE_XTAL_OV_RATIO                  2'b01
+        11:9    RW     CORE_XTAL_MODE                      3'b100
+        13:12   RW     CORE_XTAL_CTRL1_2t1                 2'b00
+        31:14   R      RSVD                                18'h0
+    */
+    union
+    {
+        __IO uint32_t PERION_CORE_SWR_PAR_TAB_4_1;
+        struct
+        {
+            __IO uint32_t CORE_XTAL_LPS_CAP_STEP: 2;
+            __IO uint32_t CORE_XTAL_LPS_CAP_CYC: 2;
+            __IO uint32_t CORE_XTAL_OV_UNIT: 3;
+            __IO uint32_t CORE_XTAL_OV_RATIO: 2;
+            __IO uint32_t CORE_XTAL_MODE: 3;
+            __IO uint32_t CORE_XTAL_CTRL1_2t1: 2;
+            __I uint32_t RESERVED_0: 18;
+        } BITS_25C;
+    } u_25C;
+
+    /* 0x0260       0x4000_0260
+        1:0     RW     CORE_XTAL_LPS_CAP_STEP              2'b01
+        3:2     RW     CORE_XTAL_LPS_CAP_CYC               2'b00
+        6:4     RW     CORE_XTAL_OV_UNIT                   3'b000
+        8:7     RW     CORE_XTAL_OV_RATIO                  2'b01
+        11:9    RW     CORE_XTAL_MODE                      3'b100
+        13:12   RW     CORE_XTAL_CTRL1_2t1                 2'b00
+        31:14   R      RSVD                                18'h0
+    */
+    union
+    {
+        __IO uint32_t PERION_CORE_SWR_PAR_TAB_5_1;
+        struct
+        {
+            __IO uint32_t CORE_XTAL_LPS_CAP_STEP: 2;
+            __IO uint32_t CORE_XTAL_LPS_CAP_CYC: 2;
+            __IO uint32_t CORE_XTAL_OV_UNIT: 3;
+            __IO uint32_t CORE_XTAL_OV_RATIO: 2;
+            __IO uint32_t CORE_XTAL_MODE: 3;
+            __IO uint32_t CORE_XTAL_CTRL1_2t1: 2;
+            __I uint32_t RESERVED_0: 18;
+        } BITS_260;
+    } u_260;
+
+    /* 0x0264       0x4000_0264
+        1:0     RW     CORE_XTAL_LPS_CAP_STEP              2'b01
+        3:2     RW     CORE_XTAL_LPS_CAP_CYC               2'b00
+        6:4     RW     CORE_XTAL_OV_UNIT                   3'b000
+        8:7     RW     CORE_XTAL_OV_RATIO                  2'b01
+        11:9    RW     CORE_XTAL_MODE                      3'b100
+        13:12   RW     CORE_XTAL_CTRL1_2t1                 2'b00
+        31:14   R      RSVD                                18'h0
+    */
+    union
+    {
+        __IO uint32_t PERION_CORE_SWR_PAR_TAB_6_1;
+        struct
+        {
+            __IO uint32_t CORE_XTAL_LPS_CAP_STEP: 2;
+            __IO uint32_t CORE_XTAL_LPS_CAP_CYC: 2;
+            __IO uint32_t CORE_XTAL_OV_UNIT: 3;
+            __IO uint32_t CORE_XTAL_OV_RATIO: 2;
+            __IO uint32_t CORE_XTAL_MODE: 3;
+            __IO uint32_t CORE_XTAL_CTRL1_2t1: 2;
+            __I uint32_t RESERVED_0: 18;
+        } BITS_264;
+    } u_264;
+
+    /* 0x0268       0x4000_0268
+        1:0     RW     CORE_XTAL_LPS_CAP_STEP              2'b01
+        3:2     RW     CORE_XTAL_LPS_CAP_CYC               2'b00
+        6:4     RW     CORE_XTAL_OV_UNIT                   3'b000
+        8:7     RW     CORE_XTAL_OV_RATIO                  2'b01
+        11:9    RW     CORE_XTAL_MODE                      3'b100
+        13:12   RW     CORE_XTAL_CTRL1_2t1                 2'b00
+        31:14   R      RSVD                                18'h0
+    */
+    union
+    {
+        __IO uint32_t PERION_CORE_SWR_PAR_TAB_7_1;
+        struct
+        {
+            __IO uint32_t CORE_XTAL_LPS_CAP_STEP: 2;
+            __IO uint32_t CORE_XTAL_LPS_CAP_CYC: 2;
+            __IO uint32_t CORE_XTAL_OV_UNIT: 3;
+            __IO uint32_t CORE_XTAL_OV_RATIO: 2;
+            __IO uint32_t CORE_XTAL_MODE: 3;
+            __IO uint32_t CORE_XTAL_CTRL1_2t1: 2;
+            __I uint32_t RESERVED_0: 18;
+        } BITS_268;
+    } u_268;
+
+    /* 0x026C       0x4000_026c
+        0       RW     CORE_BUCK_PFM_AOT_EN                1'b1
+        1       RW     CORE_BUCK_PFM_COT_EN                1'b0
+        2       RW     CORE_BUCK_ENOFFSAWPFM_H             1'b1
+        3       RW     CORE_BUCK_POW_EA_Iqx2_H             1'b1
+        4       RW     CORE_BUCK_POW_EA_Iqx3_H             1'b1
+        5       RW     CORE_BUCK_POW_EA_IqEhance_H         1'b1
+        8:6     RW     CORE_BUCK_PFM_STEP_INI              3'b0
+        16:9    RW     CORE_AUTO_SET                       8'haa
+        22:17   RW     CORE_D300k_REG_MANU_CCOT            6'b001000
+        31:23   R      RSVD                                9'b0
+    */
+    union
+    {
+        __IO uint32_t PERION_CORE_SWR_PAR_TAB_0_2;
+        struct
+        {
+            __IO uint32_t CORE_BUCK_PFM_AOT_EN: 1;
+            __IO uint32_t CORE_BUCK_PFM_COT_EN: 1;
+            __IO uint32_t CORE_BUCK_ENOFFSAWPFM_H: 1;
+            __IO uint32_t CORE_BUCK_POW_EA_Iqx2_H: 1;
+            __IO uint32_t CORE_BUCK_POW_EA_Iqx3_H: 1;
+            __IO uint32_t CORE_BUCK_POW_EA_IqEhance_H: 1;
+            __IO uint32_t CORE_BUCK_PFM_STEP_INI: 3;
+            __IO uint32_t CORE_AUTO_SET: 8;
+            __IO uint32_t CORE_D300k_REG_MANU_CCOT: 6;
+            __I uint32_t RESERVED_0: 9;
+        } BITS_26C;
+    } u_26C;
+
+    /* 0x0270       0x4000_0270
+        0       RW     CORE_BUCK_PFM_AOT_EN                1'b1
+        1       RW     CORE_BUCK_PFM_COT_EN                1'b0
+        2       RW     CORE_BUCK_ENOFFSAWPFM_H             1'b1
+        3       RW     CORE_BUCK_POW_EA_Iqx2_H             1'b1
+        4       RW     CORE_BUCK_POW_EA_Iqx3_H             1'b1
+        5       RW     CORE_BUCK_POW_EA_IqEhance_H         1'b1
+        8:6     RW     CORE_BUCK_PFM_STEP_INI              3'b0
+        16:9    RW     CORE_AUTO_SET                       8'haa
+        22:17   RW     CORE_D300k_REG_MANU_CCOT            6'b001000
+        31:23   R      RSVD                                9'b0
+    */
+    union
+    {
+        __IO uint32_t PERION_CORE_SWR_PAR_TAB_4_2;
+        struct
+        {
+            __IO uint32_t CORE_BUCK_PFM_AOT_EN: 1;
+            __IO uint32_t CORE_BUCK_PFM_COT_EN: 1;
+            __IO uint32_t CORE_BUCK_ENOFFSAWPFM_H: 1;
+            __IO uint32_t CORE_BUCK_POW_EA_Iqx2_H: 1;
+            __IO uint32_t CORE_BUCK_POW_EA_Iqx3_H: 1;
+            __IO uint32_t CORE_BUCK_POW_EA_IqEhance_H: 1;
+            __IO uint32_t CORE_BUCK_PFM_STEP_INI: 3;
+            __IO uint32_t CORE_AUTO_SET: 8;
+            __IO uint32_t CORE_D300k_REG_MANU_CCOT: 6;
+            __I uint32_t RESERVED_0: 9;
+        } BITS_270;
+    } u_270;
+
+    /* 0x0274       0x4000_0274
+        0       RW     CORE_BUCK_PFM_AOT_EN                1'b1
+        1       RW     CORE_BUCK_PFM_COT_EN                1'b0
+        2       RW     CORE_BUCK_ENOFFSAWPFM_H             1'b1
+        3       RW     CORE_BUCK_POW_EA_Iqx2_H             1'b1
+        4       RW     CORE_BUCK_POW_EA_Iqx3_H             1'b1
+        5       RW     CORE_BUCK_POW_EA_IqEhance_H         1'b1
+        8:6     RW     CORE_BUCK_PFM_STEP_INI              3'b0
+        16:9    RW     CORE_AUTO_SET                       8'haa
+        22:17   RW     CORE_D300k_REG_MANU_CCOT            6'b001000
+        31:23   R      RSVD                                9'b0
+    */
+    union
+    {
+        __IO uint32_t PERION_CORE_SWR_PAR_TAB_5_2;
+        struct
+        {
+            __IO uint32_t CORE_BUCK_PFM_AOT_EN: 1;
+            __IO uint32_t CORE_BUCK_PFM_COT_EN: 1;
+            __IO uint32_t CORE_BUCK_ENOFFSAWPFM_H: 1;
+            __IO uint32_t CORE_BUCK_POW_EA_Iqx2_H: 1;
+            __IO uint32_t CORE_BUCK_POW_EA_Iqx3_H: 1;
+            __IO uint32_t CORE_BUCK_POW_EA_IqEhance_H: 1;
+            __IO uint32_t CORE_BUCK_PFM_STEP_INI: 3;
+            __IO uint32_t CORE_AUTO_SET: 8;
+            __IO uint32_t CORE_D300k_REG_MANU_CCOT: 6;
+            __I uint32_t RESERVED_0: 9;
+        } BITS_274;
+    } u_274;
+
+    /* 0x0278       0x4000_0278
+        0       RW     CORE_BUCK_PFM_AOT_EN                1'b1
+        1       RW     CORE_BUCK_PFM_COT_EN                1'b0
+        2       RW     CORE_BUCK_ENOFFSAWPFM_H             1'b1
+        3       RW     CORE_BUCK_POW_EA_Iqx2_H             1'b1
+        4       RW     CORE_BUCK_POW_EA_Iqx3_H             1'b1
+        5       RW     CORE_BUCK_POW_EA_IqEhance_H         1'b1
+        8:6     RW     CORE_BUCK_PFM_STEP_INI              3'b0
+        16:9    RW     CORE_AUTO_SET                       8'haa
+        22:17   RW     CORE_D300k_REG_MANU_CCOT            6'b001000
+        31:23   R      RSVD                                9'b0
+    */
+    union
+    {
+        __IO uint32_t PERION_CORE_SWR_PAR_TAB_6_2;
+        struct
+        {
+            __IO uint32_t CORE_BUCK_PFM_AOT_EN: 1;
+            __IO uint32_t CORE_BUCK_PFM_COT_EN: 1;
+            __IO uint32_t CORE_BUCK_ENOFFSAWPFM_H: 1;
+            __IO uint32_t CORE_BUCK_POW_EA_Iqx2_H: 1;
+            __IO uint32_t CORE_BUCK_POW_EA_Iqx3_H: 1;
+            __IO uint32_t CORE_BUCK_POW_EA_IqEhance_H: 1;
+            __IO uint32_t CORE_BUCK_PFM_STEP_INI: 3;
+            __IO uint32_t CORE_AUTO_SET: 8;
+            __IO uint32_t CORE_D300k_REG_MANU_CCOT: 6;
+            __I uint32_t RESERVED_0: 9;
+        } BITS_278;
+    } u_278;
+
+    /* 0x027C       0x4000_027c
+        0       RW     CORE_BUCK_PFM_AOT_EN                1'b1
+        1       RW     CORE_BUCK_PFM_COT_EN                1'b0
+        2       RW     CORE_BUCK_ENOFFSAWPFM_H             1'b1
+        3       RW     CORE_BUCK_POW_EA_Iqx2_H             1'b1
+        4       RW     CORE_BUCK_POW_EA_Iqx3_H             1'b1
+        5       RW     CORE_BUCK_POW_EA_IqEhance_H         1'b1
+        8:6     RW     CORE_BUCK_PFM_STEP_INI              3'b0
+        16:9    RW     CORE_AUTO_SET                       8'haa
+        22:17   RW     CORE_D300k_REG_MANU_CCOT            6'b001000
+        31:23   R      RSVD                                9'b0
+    */
+    union
+    {
+        __IO uint32_t PERION_CORE_SWR_PAR_TAB_7_2;
+        struct
+        {
+            __IO uint32_t CORE_BUCK_PFM_AOT_EN: 1;
+            __IO uint32_t CORE_BUCK_PFM_COT_EN: 1;
+            __IO uint32_t CORE_BUCK_ENOFFSAWPFM_H: 1;
+            __IO uint32_t CORE_BUCK_POW_EA_Iqx2_H: 1;
+            __IO uint32_t CORE_BUCK_POW_EA_Iqx3_H: 1;
+            __IO uint32_t CORE_BUCK_POW_EA_IqEhance_H: 1;
+            __IO uint32_t CORE_BUCK_PFM_STEP_INI: 3;
+            __IO uint32_t CORE_AUTO_SET: 8;
+            __IO uint32_t CORE_D300k_REG_MANU_CCOT: 6;
+            __I uint32_t RESERVED_0: 9;
+        } BITS_27C;
+    } u_27C;
+
+    /* 0x0280       0x4000_0280
+        6:0     R/W    r_PMUX_GPIO_P0_0                    7'h0
+        7       R/W    DUMMY                               0
+        14:8    R/W    r_PMUX_GPIO_P0_1                    7'h0
+        15      R/W    DUMMY                               0
+        22:16   R/W    r_PMUX_GPIO_P0_2                    7'h0
+        23      R/W    DUMMY                               0
+        30:24   R/W    r_PMUX_GPIO_P0_3                    7'h1D
+        31      R/W    DUMMY                               0
+    */
+    union
+    {
+        __IO uint32_t PERION_r_PMUX_GPIO_P0_0_3;
+        struct
+        {
+            __IO uint32_t r_PMUX_GPIO_P0_0: 7;
+            __IO uint32_t RESERVED_3: 1;
+            __IO uint32_t r_PMUX_GPIO_P0_1: 7;
+            __IO uint32_t RESERVED_2: 1;
+            __IO uint32_t r_PMUX_GPIO_P0_2: 7;
+            __IO uint32_t RESERVED_1: 1;
+            __IO uint32_t r_PMUX_GPIO_P0_3: 7;
+            __IO uint32_t RESERVED_0: 1;
+        } BITS_280;
+    } u_280;
+
+    /* 0x0284       0x4000_0284
+        6:0     R/W    r_PMUX_GPIO_P0_4                    7'h0
+        7       R/W    DUMMY                               0
+        14:8    R/W    r_PMUX_GPIO_P0_5                    7'h0
+        15      R/W    DUMMY                               0
+        22:16   R/W    r_PMUX_GPIO_P0_6                    7'h0
+        23      R/W    DUMMY                               0
+        30:24   R/W    r_PMUX_GPIO_P0_7                    7'h0
+        31      R/W    DUMMY                               0
+    */
+    union
+    {
+        __IO uint32_t PERION_r_PMUX_GPIO_P0_4_7;
+        struct
+        {
+            __IO uint32_t r_PMUX_GPIO_P0_4: 7;
+            __IO uint32_t RESERVED_3: 1;
+            __IO uint32_t r_PMUX_GPIO_P0_5: 7;
+            __IO uint32_t RESERVED_2: 1;
+            __IO uint32_t r_PMUX_GPIO_P0_6: 7;
+            __IO uint32_t RESERVED_1: 1;
+            __IO uint32_t r_PMUX_GPIO_P0_7: 7;
+            __IO uint32_t RESERVED_0: 1;
+        } BITS_284;
+    } u_284;
+
+    /* 0x0288       0x4000_0288
+        6:0     R/W    r_PMUX_GPIO_P1_0                    7'h39
+        7       R/W    DUMMY                               0
+        14:8    R/W    r_PMUX_GPIO_P1_1                    7'h38
+        15      R/W    DUMMY                               0
+        22:16   R/W    r_PMUX_GPIO_P1_2                    7'h0
+        23      R/W    DUMMY                               0
+        30:24   R/W    r_PMUX_GPIO_P1_3                    7'h0
+        31      R/W    DUMMY                               0
+    */
+    union
+    {
+        __IO uint32_t PERION_r_PMUX_GPIO_P1_0_3;
+        struct
+        {
+            __IO uint32_t r_PMUX_GPIO_P1_0: 7;
+            __IO uint32_t RESERVED_3: 1;
+            __IO uint32_t r_PMUX_GPIO_P1_1: 7;
+            __IO uint32_t RESERVED_2: 1;
+            __IO uint32_t r_PMUX_GPIO_P1_2: 7;
+            __IO uint32_t RESERVED_1: 1;
+            __IO uint32_t r_PMUX_GPIO_P1_3: 7;
+            __IO uint32_t RESERVED_0: 1;
+        } BITS_288;
+    } u_288;
+
+    /* 0x028C       0x4000_028c
+        6:0     R/W    r_PMUX_GPIO_P1_4                    7'h0
+        7       R/W    DUMMY                               0
+        14:8    R/W    r_PMUX_GPIO_P1_5                    7'h0
+        15      R/W    DUMMY                               0
+        22:16   R/W    r_PMUX_GPIO_P1_6                    7'h0
+        23      R/W    DUMMY                               0
+        30:24   R/W    r_PMUX_GPIO_P1_7                    7'h0
+        31      R/W    DUMMY                               0
+    */
+    union
+    {
+        __IO uint32_t PERION_r_PMUX_GPIO_P1_4_7;
+        struct
+        {
+            __IO uint32_t r_PMUX_GPIO_P1_4: 7;
+            __IO uint32_t RESERVED_3: 1;
+            __IO uint32_t r_PMUX_GPIO_P1_5: 7;
+            __IO uint32_t RESERVED_2: 1;
+            __IO uint32_t r_PMUX_GPIO_P1_6: 7;
+            __IO uint32_t RESERVED_1: 1;
+            __IO uint32_t r_PMUX_GPIO_P1_7: 7;
+            __IO uint32_t RESERVED_0: 1;
+        } BITS_28C;
+    } u_28C;
+
+    /* 0x0290       0x4000_0290
+        6:0     R/W    r_PMUX_GPIO_P2_0                    7'h0
+        7       R/W    DUMMY                               0
+        14:8    R/W    r_PMUX_GPIO_P2_1                    7'h0
+        15      R/W    DUMMY                               0
+        22:16   R/W    r_PMUX_GPIO_P2_2                    7'h0
+        23      R/W    DUMMY                               0
+        30:24   R/W    r_PMUX_GPIO_P2_3                    7'h0
+        31      R/W    DUMMY                               0
+    */
+    union
+    {
+        __IO uint32_t PERION_r_PMUX_GPIO_P2_0_3;
+        struct
+        {
+            __IO uint32_t r_PMUX_GPIO_P2_0: 7;
+            __IO uint32_t RESERVED_3: 1;
+            __IO uint32_t r_PMUX_GPIO_P2_1: 7;
+            __IO uint32_t RESERVED_2: 1;
+            __IO uint32_t r_PMUX_GPIO_P2_2: 7;
+            __IO uint32_t RESERVED_1: 1;
+            __IO uint32_t r_PMUX_GPIO_P2_3: 7;
+            __IO uint32_t RESERVED_0: 1;
+        } BITS_290;
+    } u_290;
+
+    /* 0x0294       0x4000_0294
+        6:0     R/W    r_PMUX_GPIO_P2_4                    7'h0
+        7       R/W    DUMMY                               0
+        14:8    R/W    r_PMUX_GPIO_P2_5                    7'h0
+        15      R/W    DUMMY                               0
+        22:16   R/W    r_PMUX_GPIO_P2_6                    7'h0
+        23      R/W    DUMMY                               0
+        30:24   R/W    r_PMUX_GPIO_P2_7                    7'h0
+        31      R/W    DUMMY                               0
+    */
+    union
+    {
+        __IO uint32_t PERION_r_PMUX_GPIO_P2_4_7;
+        struct
+        {
+            __IO uint32_t r_PMUX_GPIO_P2_4: 7;
+            __IO uint32_t RESERVED_3: 1;
+            __IO uint32_t r_PMUX_GPIO_P2_5: 7;
+            __IO uint32_t RESERVED_2: 1;
+            __IO uint32_t r_PMUX_GPIO_P2_6: 7;
+            __IO uint32_t RESERVED_1: 1;
+            __IO uint32_t r_PMUX_GPIO_P2_7: 7;
+            __IO uint32_t RESERVED_0: 1;
+        } BITS_294;
+    } u_294;
+
+    /* 0x0298       0x4000_0298
+        6:0     R/W    r_PMUX_GPIO_P3_0                    7'h23
+        7       R/W    DUMMY                               0
+        14:8    R/W    r_PMUX_GPIO_P3_1                    7'h24
+        15      R/W    DUMMY                               0
+        22:16   R/W    r_PMUX_GPIO_P3_2                    7'h0
+        23      R/W    DUMMY                               0
+        30:24   R/W    r_PMUX_GPIO_P3_3                    7'h0
+        31      R/W    DUMMY                               0
+    */
+    union
+    {
+        __IO uint32_t PERION_r_PMUX_GPIO_P3_0_3;
+        struct
+        {
+            __IO uint32_t r_PMUX_GPIO_P3_0: 7;
+            __IO uint32_t RESERVED_3: 1;
+            __IO uint32_t r_PMUX_GPIO_P3_1: 7;
+            __IO uint32_t RESERVED_2: 1;
+            __IO uint32_t r_PMUX_GPIO_P3_2: 7;
+            __IO uint32_t RESERVED_1: 1;
+            __IO uint32_t r_PMUX_GPIO_P3_3: 7;
+            __IO uint32_t RESERVED_0: 1;
+        } BITS_298;
+    } u_298;
+
+    /* 0x029C       0x4000_029c
+        6:0     R/W    r_PMUX_GPIO_P3_4                    7'h0
+        7       R/W    DUMMY                               0
+        14:8    R/W    r_PMUX_GPIO_P3_5                    7'h0
+        15      R/W    DUMMY                               0
+        22:16   R/W    r_PMUX_GPIO_P3_6                    7'h0
+        23      R/W    DUMMY                               0
+        30:24   R/W    r_PMUX_GPIO_P3_7                    7'h0
+        31      R/W    DUMMY                               0
+    */
+    union
+    {
+        __IO uint32_t PERION_r_PMUX_GPIO_P3_4_7;
+        struct
+        {
+            __IO uint32_t r_PMUX_GPIO_P3_4: 7;
+            __IO uint32_t RESERVED_3: 1;
+            __IO uint32_t r_PMUX_GPIO_P3_5: 7;
+            __IO uint32_t RESERVED_2: 1;
+            __IO uint32_t r_PMUX_GPIO_P3_6: 7;
+            __IO uint32_t RESERVED_1: 1;
+            __IO uint32_t r_PMUX_GPIO_P3_7: 7;
+            __IO uint32_t RESERVED_0: 1;
+        } BITS_29C;
+    } u_29C;
+
+    /* 0x02A0       0x4000_02a0
+        6:0     R/W    r_PMUX_GPIO_P4_0                    7'h2e
+        7       R/W    DUMMY                               0
+        14:8    R/W    r_PMUX_GPIO_P4_1                    7'h2f
+        15      R/W    DUMMY                               0
+        22:16   R/W    r_PMUX_GPIO_P4_2                    7'h30
+        23      R/W    DUMMY                               0
+        30:24   R/W    r_PMUX_GPIO_P4_3                    7'h2d
+        31      R/W    DUMMY                               0
+    */
+    union
+    {
+        __IO uint32_t PERION_r_PMUX_GPIO_P4_0_3;
+        struct
+        {
+            __IO uint32_t r_PMUX_GPIO_P4_0: 7;
+            __IO uint32_t RESERVED_3: 1;
+            __IO uint32_t r_PMUX_GPIO_P4_1: 7;
+            __IO uint32_t RESERVED_2: 1;
+            __IO uint32_t r_PMUX_GPIO_P4_2: 7;
+            __IO uint32_t RESERVED_1: 1;
+            __IO uint32_t r_PMUX_GPIO_P4_3: 7;
+            __IO uint32_t RESERVED_0: 1;
+        } BITS_2A0;
+    } u_2A0;
+
+    /* 0x02A4       0x4000_02a4
+        6:0     R/W    r_PMUX_GPIO_H_0                     7'h0
+        7       R/W    DUMMY                               0
+        14:8    R/W    r_PMUX_GPIO_H_1                     7'h0
+        15      R/W    DUMMY                               0
+        22:16   R/W    r_PMUX_GPIO_H_2                     7'h0
+        31:23   R/W    DUMMY                               9'h0
+    */
+    union
+    {
+        __IO uint32_t PERION_r_PMUX_GPIO_H_0_2;
+        struct
+        {
+            __IO uint32_t r_PMUX_GPIO_H_0: 7;
+            __IO uint32_t RESERVED_2: 1;
+            __IO uint32_t r_PMUX_GPIO_H_1: 7;
+            __IO uint32_t RESERVED_1: 1;
+            __IO uint32_t r_PMUX_GPIO_H_2: 7;
+            __IO uint32_t RESERVED_0: 9;
+        } BITS_2A4;
+    } u_2A4;
+
+    /* 0x02A8       0x4000_02a8
+        3:0     R/W    r_PMUX_TEST_MODE                    4'h1
+        6:4     R/W    DUMMY                               0
+        7       R/W    r_PMUX_TEST_MODE_EN                 0
+        8       R/W    DUMMY                               0
+        9       R/W    DUMMY                               0
+        12:10   R/W    r_PMUX_1_WIRE_UART_EN               3'h0
+        15:13   R/W    DUMMY                               6'h0
+        19:16   R/W    r_PMUX_DBG_MODE_SEL                 4'h2
+        20      R/W    r_PMUX_DBG_SPIC0                    0
+        21      R/W    DUMMY                               0
+        22      R/W    DUMMY                               0
+        23      R/W    r_PMUX_DIG_SMUX_EN                  0
+        24      R/W    r_PON_PMUX_SPIM0_EN                 0
+        25      R/W    r_PMUX_SPIM_EN_OPT                  0
+        26      R/W    r_PMUX_FLASH_EXTC_EN                0
+        27      R/W    r_PMUX_FLASH_EN                     0
+        29:28   R/W    r_PMUX_LCD_EN                       2'h0
+        30      R/W    DUMMY                               0
+        31      R/W    DUMMY                               0
+    */
+    union
+    {
+        __IO uint32_t PERION_r_PMUX_TEST_MODE;
+        struct
+        {
+            __IO uint32_t r_PMUX_TEST_MODE: 4;
+            __IO uint32_t RESERVED_7: 3;
+            __IO uint32_t r_PMUX_TEST_MODE_EN: 1;
+            __IO uint32_t RESERVED_6: 1;
+            __IO uint32_t RESERVED_5: 1;
+            __IO uint32_t r_PMUX_1_WIRE_UART_EN: 3;
+            __IO uint32_t RESERVED_4: 3;
+            __IO uint32_t r_PMUX_DBG_MODE_SEL: 4;
+            __IO uint32_t r_PMUX_DBG_SPIC0: 1;
+            __IO uint32_t RESERVED_3: 1;
+            __IO uint32_t RESERVED_2: 1;
+            __IO uint32_t r_PMUX_DIG_SMUX_EN: 1;
+            __IO uint32_t r_PON_PMUX_SPIM0_EN: 1;
+            __IO uint32_t r_PMUX_SPIM_EN_OPT: 1;
+            __IO uint32_t r_PMUX_FLASH_EXTC_EN: 1;
+            __IO uint32_t r_PMUX_FLASH_EN: 1;
+            __IO uint32_t r_PMUX_LCD_EN: 2;
+            __IO uint32_t RESERVED_1: 1;
+            __IO uint32_t RESERVED_0: 1;
+        } BITS_2A8;
+    } u_2A8;
+
+    /* 0x02AC       0x4000_02ac
+        0       R/W    r_MUX_P0_1                          0
+        1       R/W    r_MUX_P0_2                          0
+        2       R/W    r_MUX_P0_4                          0
+        3       R/W    r_MUX_P0_5                          0
+        4       R/W    r_MUX_P2_0                          0
+        5       R/W    r_MUX_P3_2                          0
+        6       R/W    r_MUX_P3_3                          0
+        7       R/W    r_MUX_P3_4                          0
+        8       R/W    r_MUX_P3_5                          0
+        9       R/W    r_MUX_P3_6                          0
+        10      R/W    r_MUX_P4_0                          0
+        11      R/W    r_MUX_P4_1                          0
+        12      R/W    r_MUX_P4_2                          0
+        13      R/W    r_MUX_P4_3                          0
+        31:14   R/W    DUMMY                               18'h0
+    */
+    union
+    {
+        __IO uint32_t r_MUX_LCD;
+        struct
+        {
+            __IO uint32_t r_MUX_P0_1: 1;
+            __IO uint32_t r_MUX_P0_2: 1;
+            __IO uint32_t r_MUX_P0_4: 1;
+            __IO uint32_t r_MUX_P0_5: 1;
+            __IO uint32_t r_MUX_P2_0: 1;
+            __IO uint32_t r_MUX_P3_2: 1;
+            __IO uint32_t r_MUX_P3_3: 1;
+            __IO uint32_t r_MUX_P3_4: 1;
+            __IO uint32_t r_MUX_P3_5: 1;
+            __IO uint32_t r_MUX_P3_6: 1;
+            __IO uint32_t r_MUX_P4_0: 1;
+            __IO uint32_t r_MUX_P4_1: 1;
+            __IO uint32_t r_MUX_P4_2: 1;
+            __IO uint32_t r_MUX_P4_3: 1;
+            __IO uint32_t RESERVED_0: 18;
+        } BITS_2AC;
+    } u_2AC;
+
+    /* 0x02B0       0x4000_02b0
+        31:0    R      RSVD                                32'hEAEAEAEA
+    */
+    __IO uint32_t REG_RSVD_2B0;
+
+    /* 0x02B4       0x4000_02b4
+        31:0    R/W    DUMMY                               32'h0
+    */
+    __IO uint32_t PERION_REG_DUMMY_2B4;
+
+    /* 0x02B8       0x4000_02b8
+        31:0    R/W    DUMMY                               32'h0
+    */
+    __IO uint32_t PERION_REG_DUMMY_2B8;
+
+    /* 0x02BC       0x4000_02bc
+        31:0    R      RSVD                                32'hEAEAEAEA
+    */
+    __IO uint32_t PERION_REG_RSVD_2BC;
+
+    /* 0x02C0       0x4000_02c0
+        31:0    R      RSVD                                32'hEAEAEAEA
+    */
+    __IO uint32_t PERION_REG_RSVD_2C0;
+
+    /* 0x02C4       0x4000_02c4
+        31:0    R      RSVD                                32'hEAEAEAEA
+    */
+    __IO uint32_t PERION_REG_RSVD_2C4;
+
+    /* 0x02C8       0x4000_02c8
+        31:0    R      RSVD                                32'hEAEAEAEA
+    */
+    __IO uint32_t PERION_REG_RSVD_2C8;
+
+    /* 0x02CC       0x4000_02cc
+        31:0    R      RSVD                                32'hEAEAEAEA
+    */
+    __IO uint32_t PERION_REG_RSVD_2CC;
+
+    /* 0x02D0       0x4000_02d0
+        1:0     R/W    DUMMY                               2'h0
+        3:2     R/W    DUMMY                               2'h0
+        4       R/W    DUMMY                               0
+        5       R/W    DUMMY                               0
+        6       R/W    DUMMY                               0
+        7       R/W    DUMMY                               0
+        8       R/W    DUMMY                               0
+        31:9    R/W    DUMMY                               23'h0
+    */
+    union
+    {
+        __IO uint32_t PERION_REG_RSVD_2D0;
+        struct
+        {
+            __IO uint32_t RESERVED_7: 2;
+            __IO uint32_t RESERVED_6: 2;
+            __IO uint32_t RESERVED_5: 1;
+            __IO uint32_t RESERVED_4: 1;
+            __IO uint32_t RESERVED_3: 1;
+            __IO uint32_t RESERVED_2: 1;
+            __IO uint32_t RESERVED_1: 1;
+            __IO uint32_t RESERVED_0: 23;
+        } BITS_2D0;
+    } u_2D0;
+
+    /* 0x02D4       0x4000_02d4
+        31:0    R      RSVD                                32'hEAEAEAEA
+    */
+    __IO uint32_t PERION_REG_RSVD_2D4;
+
+    /* 0x02D8       0x4000_02d8
+        31:0    R      RSVD                                32'hEAEAEAEA
+    */
+    __IO uint32_t PERION_REG_RSVD_2D8;
+
+    /* 0x02DC       0x4000_02dc
+        31:0    R      RSVD                                32'hEAEAEAEA
+    */
+    __IO uint32_t PERION_REG_RSVD_2DC;
+
+    /* 0x02E0       0x4000_02e0
+        7:0     R/W    DUMMY                               8'hC0
+        18:8    R      RSVD                                11'h0
+        31:19   R/W    DUMMY                               13'h0
+    */
+    union
+    {
+        __IO uint32_t PERION_REG_RSVD_2E0;
+        struct
+        {
+            __IO uint32_t RESERVED_2: 8;
+            __I uint32_t RESERVED_1: 11;
+            __IO uint32_t RESERVED_0: 13;
+        } BITS_2E0;
+    } u_2E0;
+
+    /* 0x02E4       0x4000_02e4
+        15:0    R/W    DUMMY                               16'h0
+        25:16   R      RSVD                                10'h0
+        31:26   R/W    DUMMY                               6'h0
+    */
+    union
+    {
+        __IO uint32_t PERION_REG_RSVD_2E4;
+        struct
+        {
+            __IO uint32_t RESERVED_2: 16;
+            __I uint32_t RESERVED_1: 10;
+            __IO uint32_t RESERVED_0: 6;
+        } BITS_2E4;
+    } u_2E4;
+
+    /* 0x02E8       0x4000_02e8
+        7:0     R/W    CORE_SWR_VDDCORE_VDIV_POS_PON_OVER  8'b01100110
+        12:8    R/W    CORE_BUCK_TUNE_PFM_CCOT2            5'b00111
+        17:13   R/W    CORE_BUCK_TUNE_PFM_CCOT1            5'b00111
+        18      R/W    CORE_LDO_ENB_DMYL_200U_LDOANA       1'b1
+        23:19   R/W    CORE_LDO_TUNE_LDOANA                5'b10000
+        31:24   R/W    CORE_SWR_VDDANA_VDIV_POS_PON_OVER   8'b10001010
+    */
+    union
+    {
+        __IO uint32_t PERION_CORE_SWR_PAR_TAB_0_0;
+        struct
+        {
+            __IO uint32_t CORE_SWR_VDDCORE_VDIV_POS_PON_OVER: 8;
+            __IO uint32_t CORE_BUCK_TUNE_PFM_CCOT2: 5;
+            __IO uint32_t CORE_BUCK_TUNE_PFM_CCOT1: 5;
+            __IO uint32_t CORE_LDO_ENB_DMYL_200U_LDOANA: 1;
+            __IO uint32_t CORE_LDO_TUNE_LDOANA: 5;
+            __IO uint32_t CORE_SWR_VDDANA_VDIV_POS_PON_OVER: 8;
+        } BITS_2E8;
+    } u_2E8;
+
+    /* 0x02EC       0x4000_02ec
+        7:0     R/W    CORE_SWR_VDDCORE_VDIV_POS_PON_OVER  8'b01100110
+        12:8    R/W    CORE_BUCK_TUNE_PFM_CCOT2            5'b00111
+        17:13   R/W    CORE_BUCK_TUNE_PFM_CCOT1            5'b00111
+        18      R/W    CORE_LDO_ENB_DMYL_200U_LDOANA       1'b1
+        23:19   R/W    CORE_LDO_TUNE_LDOANA                5'b10000
+        31:24   R/W    CORE_SWR_VDDANA_VDIV_POS_PON_OVER   8'b10001010
+    */
+    union
+    {
+        __IO uint32_t PERION_CORE_SWR_PAR_TAB_4_0;
+        struct
+        {
+            __IO uint32_t CORE_SWR_VDDCORE_VDIV_POS_PON_OVER: 8;
+            __IO uint32_t CORE_BUCK_TUNE_PFM_CCOT2: 5;
+            __IO uint32_t CORE_BUCK_TUNE_PFM_CCOT1: 5;
+            __IO uint32_t CORE_LDO_ENB_DMYL_200U_LDOANA: 1;
+            __IO uint32_t CORE_LDO_TUNE_LDOANA: 5;
+            __IO uint32_t CORE_SWR_VDDANA_VDIV_POS_PON_OVER: 8;
+        } BITS_2EC;
+    } u_2EC;
+
+    /* 0x02F0       0x4000_02f0
+        7:0     R/W    CORE_SWR_VDDCORE_VDIV_POS_PON_OVER  8'b01100110
+        12:8    R/W    CORE_BUCK_TUNE_PFM_CCOT2            5'b00111
+        17:13   R/W    CORE_BUCK_TUNE_PFM_CCOT1            5'b00111
+        18      R/W    CORE_LDO_ENB_DMYL_200U_LDOANA       1'b1
+        23:19   R/W    CORE_LDO_TUNE_LDOANA                5'b10000
+        31:24   R/W    CORE_SWR_VDDANA_VDIV_POS_PON_OVER   8'b10001010
+    */
+    union
+    {
+        __IO uint32_t PERION_CORE_SWR_PAR_TAB_5_0;
+        struct
+        {
+            __IO uint32_t CORE_SWR_VDDCORE_VDIV_POS_PON_OVER: 8;
+            __IO uint32_t CORE_BUCK_TUNE_PFM_CCOT2: 5;
+            __IO uint32_t CORE_BUCK_TUNE_PFM_CCOT1: 5;
+            __IO uint32_t CORE_LDO_ENB_DMYL_200U_LDOANA: 1;
+            __IO uint32_t CORE_LDO_TUNE_LDOANA: 5;
+            __IO uint32_t CORE_SWR_VDDANA_VDIV_POS_PON_OVER: 8;
+        } BITS_2F0;
+    } u_2F0;
+
+    /* 0x02F4       0x4000_02f4
+        7:0     R/W    CORE_SWR_VDDCORE_VDIV_POS_PON_OVER  8'b01100110
+        12:8    R/W    CORE_BUCK_TUNE_PFM_CCOT2            5'b00111
+        17:13   R/W    CORE_BUCK_TUNE_PFM_CCOT1            5'b00111
+        18      R/W    CORE_LDO_ENB_DMYL_200U_LDOANA       1'b1
+        23:19   R/W    CORE_LDO_TUNE_LDOANA                5'b10000
+        31:24   R/W    CORE_SWR_VDDANA_VDIV_POS_PON_OVER   8'b10001010
+    */
+    union
+    {
+        __IO uint32_t PERION_CORE_SWR_PAR_TAB_6_0;
+        struct
+        {
+            __IO uint32_t CORE_SWR_VDDCORE_VDIV_POS_PON_OVER: 8;
+            __IO uint32_t CORE_BUCK_TUNE_PFM_CCOT2: 5;
+            __IO uint32_t CORE_BUCK_TUNE_PFM_CCOT1: 5;
+            __IO uint32_t CORE_LDO_ENB_DMYL_200U_LDOANA: 1;
+            __IO uint32_t CORE_LDO_TUNE_LDOANA: 5;
+            __IO uint32_t CORE_SWR_VDDANA_VDIV_POS_PON_OVER: 8;
+        } BITS_2F4;
+    } u_2F4;
+
+    /* 0x02F8       0x4000_02f8
+        7:0     R/W    CORE_SWR_VDDCORE_VDIV_POS_PON_OVER  8'b01100110
+        12:8    R/W    CORE_BUCK_TUNE_PFM_CCOT2            5'b00111
+        17:13   R/W    CORE_BUCK_TUNE_PFM_CCOT1            5'b00111
+        18      R/W    CORE_LDO_ENB_DMYL_200U_LDOANA       1'b1
+        23:19   R/W    CORE_LDO_TUNE_LDOANA                5'b10000
+        31:24   R/W    CORE_SWR_VDDANA_VDIV_POS_PON_OVER   8'b10001010
+    */
+    union
+    {
+        __IO uint32_t PERION_CORE_SWR_PAR_TAB_7_0;
+        struct
+        {
+            __IO uint32_t CORE_SWR_VDDCORE_VDIV_POS_PON_OVER: 8;
+            __IO uint32_t CORE_BUCK_TUNE_PFM_CCOT2: 5;
+            __IO uint32_t CORE_BUCK_TUNE_PFM_CCOT1: 5;
+            __IO uint32_t CORE_LDO_ENB_DMYL_200U_LDOANA: 1;
+            __IO uint32_t CORE_LDO_TUNE_LDOANA: 5;
+            __IO uint32_t CORE_SWR_VDDANA_VDIV_POS_PON_OVER: 8;
+        } BITS_2F8;
+    } u_2F8;
+
+    /* 0x02FC       0x4000_02fc
+        5:0     R/W    CORE_SWR_PAR_TAB_0[37:32]           6'h0
+        11:6    R/W    CORE_SWR_PAR_TAB_4[37:32]           6'h0
+        17:12   R/W    CORE_SWR_PAR_TAB_5[37:32]           6'h0
+        23:18   R/W    CORE_SWR_PAR_TAB_6[37:32]           6'h0
+        29:24   R/W    CORE_SWR_PAR_TAB_7[37:32]           6'h0
+        31:30   R/W    DUMMY                               2'b00
+    */
+    union
+    {
+        __IO uint32_t CORE_PAR_RESERVED;
+        struct
+        {
+            __IO uint32_t CORE_SWR_PAR_TAB_0_37_32: 6;
+            __IO uint32_t CORE_SWR_PAR_TAB_4_37_32: 6;
+            __IO uint32_t CORE_SWR_PAR_TAB_5_37_32: 6;
+            __IO uint32_t CORE_SWR_PAR_TAB_6_37_32: 6;
+            __IO uint32_t CORE_SWR_PAR_TAB_7_37_32: 6;
+            __IO uint32_t RESERVED_0: 2;
+        } BITS_2FC;
+    } u_2FC;
+
+    /* 0x0300       0x4000_0300
+        7:0     R/W    PON_PERI_DLYSEL_CTRL                8'h0
+        15:8    R/W    DUMMY                               8'h0
+        23:16   R/W    DUMMY                               8'h0
+        24      R/W    r_flash0_clk_inv_en                 0
+        25      R/W    DUMMY                               0
+        26      R/W    DUMMY                               0
+        30:27   R/W    DUMMY                               3'h0
+        31      R/W    r_spic2_dma_tx_req_as_single        0
+    */
+    union
+    {
+        __IO uint32_t PERION_PON_PERI_DLYSEL_CTRL;
+        struct
+        {
+            __IO uint32_t PON_PERI_DLYSEL_CTRL: 8;
+            __IO uint32_t RESERVED_4: 8;
+            __IO uint32_t RESERVED_3: 8;
+            __IO uint32_t r_flash0_clk_inv_en: 1;
+            __IO uint32_t RESERVED_2: 1;
+            __IO uint32_t RESERVED_1: 1;
+            __IO uint32_t RESERVED_0: 4;
+            __IO uint32_t r_spic2_dma_tx_req_as_single: 1;
+        } BITS_300;
+    } u_300;
+
+    /* 0x0304       0x4000_0304
+        31:0    R/W    DUMMY                               32'h1FC00001
+    */
+    __IO uint32_t PERION_REG_DUMMY_304;
+
+    /* 0x0308       0x4000_0308
+        0       R/W    PON_SPIO_MST                        0
+        3:1     R/W    DUMMY                               3'h0
+        4       R/W    PON_SPI0_BRG_EN                     0
+        5       R/W    PON_SPI0_H2S_BRG_EN                 0
+        6       R/W    PON_SPI1_BRG_EN                     0
+        7       R/W    r_spi0_clk_src_sel                  0
+        8       R/W    r_spi1_clk_src_sel                  0
+        9       R/W    r_sclk_irrc_src_sel                 0
+        31:10   R/W    DUMMY                               22'h0
+    */
+    union
+    {
+        __IO uint32_t PERION_REG_RSVD_308;
+        struct
+        {
+            __IO uint32_t PON_SPIO_MST: 1;
+            __IO uint32_t RESERVED_1: 3;
+            __IO uint32_t PON_SPI0_BRG_EN: 1;
+            __IO uint32_t PON_SPI0_H2S_BRG_EN: 1;
+            __IO uint32_t PON_SPI1_BRG_EN: 1;
+            __IO uint32_t r_spi0_clk_src_sel: 1;
+            __IO uint32_t r_spi1_clk_src_sel: 1;
+            __IO uint32_t r_sclk_irrc_src_sel: 1;
+            __IO uint32_t RESERVED_0: 22;
+        } BITS_308;
+    } u_308;
+
+    __IO uint32_t RSVD_0x30c[3];
+
+    /* 0x0318       0x4000_0318
+        23:0    R      RSVD                                24'd0
+        31:24   R/W    DUMMY                               8'd0
+    */
+    union
+    {
+        __IO uint32_t PERION_REG_DUMMY_318;
+        struct
+        {
+            __I uint32_t RESERVED_1: 24;
+            __IO uint32_t RESERVED_0: 8;
+        } BITS_318;
+    } u_318;
+
+    __IO uint32_t RSVD_0x31c[1];
+
+    /* 0x0320       0x4000_0320
+        15:0    R/W    DUMMY                               16'h7E02
+        31:16   R/W    DUMMY                               16'h0912
+    */
+    union
+    {
+        __IO uint32_t PERION_BT_ANAPAR_PLL;
+        struct
+        {
+            __IO uint32_t RESERVED_1: 16;
+            __IO uint32_t RESERVED_0: 16;
+        } BITS_320;
+    } u_320;
+
+    /* 0x0324       0x4000_0324
+        31:0    R      RSVD                                32'hEAEAEAEA
+    */
+    __IO uint32_t PERION_REG_RSVD_324;
+
+    /* 0x0328       0x4000_0328
+        31:0    R      RSVD                                32'hEAEAEAEA
+    */
+    __IO uint32_t PERION_REG_RSVD_328;
+
+    /* 0x032C       0x4000_032c
+        3:0     R      OSC40_FSET                          4'h0
+        7:4     R      RSVD                                4'h0
+        31:8    R/W    DUMMY                               24'h000109
+    */
+    union
+    {
+        __IO uint32_t PERION_REG_DUMMY_32C;
+        struct
+        {
+            __I uint32_t OSC40_FSET: 4;
+            __I uint32_t RESERVED_1: 4;
+            __IO uint32_t RESERVED_0: 24;
+        } BITS_32C;
+    } u_32C;
+
+    /* 0x0330       0x4000_0330
+        0       R/W    rst_n_aac                           0
+        1       R/W    Offset_plus                         0
+        7:2     R/W    XAAC_GM_offset                      6'b000000
+        8       R/W    GM_STEP                             0
+        14:9    R/W    GM_INIT                             6'b111110
+        17:15   R/W    XTAL_CLK_SET                        3'b101
+        23:18   R/W    GM_STUP                             6'b111111
+        29:24   R/W    GM_MANUAL                           6'b111111
+        30      R/W    r_EN_XTAL_AAC_DIGI                  0
+        31      R/W    r_EN_XTAL_AAC_TRIG                  0
+    */
+    union
+    {
+        __IO uint32_t REG_AAC_0;
+        struct
+        {
+            __IO uint32_t rst_n_aac: 1;
+            __IO uint32_t Offset_plus: 1;
+            __IO uint32_t XAAC_GM_offset: 6;
+            __IO uint32_t GM_STEP: 1;
+            __IO uint32_t GM_INIT: 6;
+            __IO uint32_t XTAL_CLK_SET: 3;
+            __IO uint32_t GM_STUP: 6;
+            __IO uint32_t GM_MANUAL: 6;
+            __IO uint32_t r_EN_XTAL_AAC_DIGI: 1;
+            __IO uint32_t r_EN_XTAL_AAC_TRIG: 1;
+        } BITS_330;
+    } u_330;
+
+    /* 0x0334       0x4000_0334
+        0       R      XAAC_BUSY                           0
+        1       R      XAAC_READY                          0
+        7:2     R      XTAL_GM_OUT                         6'h3F
+        11:8    R      xaac_curr_state                     4'h0
+        12      R/W    EN_XTAL_AAC_GM                      0
+        13      R/W    EN_XTAL_AAC_PKDET                   0
+        14      R      XTAL_PKDET_OUT                      0
+        15      R/W    DUMMY                               0
+        31:16   R/W    DUMMY                               16'h0129
+    */
+    union
+    {
+        __IO uint32_t PERION_REG_AAC_1;
+        struct
+        {
+            __I uint32_t XAAC_BUSY: 1;
+            __I uint32_t XAAC_READY: 1;
+            __I uint32_t XTAL_GM_OUT: 6;
+            __I uint32_t xaac_curr_state: 4;
+            __IO uint32_t EN_XTAL_AAC_GM: 1;
+            __IO uint32_t EN_XTAL_AAC_PKDET: 1;
+            __I uint32_t XTAL_PKDET_OUT: 1;
+            __IO uint32_t RESERVED_1: 1;
+            __IO uint32_t RESERVED_0: 16;
+        } BITS_334;
+    } u_334;
+
+    /* 0x0338       0x4000_0338
+        0       R/W    disable_pll_pre_gating              0
+        15:1    R/W    DUMMY                               15'h0
+        17:16   R/W    DUMMY                               2'h3
+        23:18   R      RSVD                                6'h0
+        24      R      BT_PLL_READY                        0
+        25      R      XTAL_OK                             0
+        31:26   R      RSVD                                6'h0
+    */
+    union
+    {
+        __IO uint32_t PERION_REG_XTAL_PLL;
+        struct
+        {
+            __IO uint32_t disable_pll_pre_gating: 1;
+            __IO uint32_t RESERVED_3: 15;
+            __IO uint32_t RESERVED_2: 2;
+            __I uint32_t RESERVED_1: 6;
+            __I uint32_t BT_PLL_READY: 1;
+            __I uint32_t XTAL_OK: 1;
+            __I uint32_t RESERVED_0: 6;
+        } BITS_338;
+    } u_338;
+
+    /* 0x033c       0x4000_033c
+        0       R/W    resetn                              0
+        1       R/W    EN_XTAL_PDCK_DIGI                   1
+        2       R/W    PDCK_SEARCH_MODE                    0
+        4:3     R/W    PDCK_WAIT_CYC[1:0]                  2'b01
+        9:5     R/W    VREF_MANUAL[4:0]                    5'b10000
+        14:10   R/W    VREF_INIT[4:0]                      5'b11111
+        16:15   R/W    XTAL_PDCK_UNIT[1:0]                 2'b10
+        21:17   R/W    XPDCK_VREF_SEL[4:0]                 5'b00000
+        22      R/W    PDCK_LPOW                           0
+        27:23   R/W    Reserved                            5'h0
+        31:28   R      pdck_state[3:0]                     4'h0
+    */
+    union
+    {
+        __IO uint32_t PERION_REG_XTAL_PDCK;
+        struct
+        {
+            __IO uint32_t resetn: 1;
+            __IO uint32_t EN_XTAL_PDCK_DIGI: 1;
+            __IO uint32_t PDCK_SEARCH_MODE: 1;
+            __IO uint32_t PDCK_WAIT_CYC_1_0: 2;
+            __IO uint32_t VREF_MANUAL_4_0: 5;
+            __IO uint32_t VREF_INIT_4_0: 5;
+            __IO uint32_t XTAL_PDCK_UNIT_1_0: 2;
+            __IO uint32_t XPDCK_VREF_SEL_4_0: 5;
+            __IO uint32_t PDCK_LPOW: 1;
+            __IO uint32_t RESERVED_0: 5;
+            __I uint32_t pdck_state_3_0: 4;
+        } BITS_33c;
+    } u_33c;
+
+    /* 0x0340       0x4000_0340
+        31:0    R/W    DUMMY                               32'hAAAAAAAA
+    */
+    __IO uint32_t PERION_REG_DUMMY_340;
+
+    /* 0x0344       0x4000_0344
+        7:0     R/W    dbnc_cnt_limit                      8'h1
+        11:8    R/W    dbnc_div_sel                        4'h1
+        12      R/W    dbnc_div_en                         1'b0
+        15:13   R/W    DUMMY                               3'h0
+        31:16   R/W    DUMMY                               16'h0
+    */
+    union
+    {
+        __IO uint32_t PERION_REG_DBNC;
+        struct
+        {
+            __IO uint32_t dbnc_cnt_limit: 8;
+            __IO uint32_t dbnc_div_sel: 4;
+            __IO uint32_t dbnc_div_en: 1;
+            __IO uint32_t RESERVED_1: 3;
+            __IO uint32_t RESERVED_0: 16;
+        } BITS_344;
+    } u_344;
+
+    /* 0x0348       0x4000_0348
+        31:0    R      RSVD                                32'h0
+    */
+    __IO uint32_t PERION_REG_RSVD_348;
+
+    /* 0x034C       0x4000_034c
+        31:0    R      RSVD                                32'h0
+    */
+    __IO uint32_t PERION_REG_RSVD_34C;
+
+    __IO uint32_t RSVD_0x350[3];
+
+    /* 0x035C       0x4000_035c
+        0       R/W    BIT_PERI_GT3_CLK_SEL                0
+        1       R/W    BIT_PERI_GT5_CLK_SEL                0
+        2       R/W    BIT_PERI_GT7_CLK_SEL                0
+        7:3     R/W    DUMMY                               5'h0
+        8       R/W    DUMMY                               0
+        10:9    R/W    BIT_PERI_UART1_CLK_DIV              2'h0
+        12:11   R/W    BIT_PERI_UART2_CLK_DIV              2'h0
+        14:13   R/W    BIT_PERI_UART0_CLK_DIV              2'h0
+        16:15   R/W    BIT_PERI_I2C0_CLK_DIV               2'h0
+        18:17   R/W    BIT_PERI_I2C1_CLK_DIV               2'h0
+        20:19   R/W    BIT_PERI_SPI0_CLK_DIV               2'h0
+        22:21   R/W    BIT_PERI_SPI1_CLK_DIV               2'h0
+        23      R/W    DUMMY                               0
+        24      R/W    TIMER2_CLK_SRC_SEL                  0
+        25      R/W    TIMER3_CLK_SRC_SEL                  0
+        26      R/W    TIMER4_CLK_SRC_SEL                  0
+        27      R/W    TIMER5_CLK_SRC_SEL                  0
+        28      R/W    TIMER6_CLK_SRC_SEL                  0
+        29      R/W    TIMER7_CLK_SRC_SEL                  0
+        31:30   R/W    DUMMY                               2'h0
+    */
+    union
+    {
+        __IO uint32_t PERION_REG_PERI_GTIMER_CLK_SRC1;
+        struct
+        {
+            __IO uint32_t BIT_PERI_GT3_CLK_SEL: 1;
+            __IO uint32_t BIT_PERI_GT5_CLK_SEL: 1;
+            __IO uint32_t BIT_PERI_GT7_CLK_SEL: 1;
+            __IO uint32_t RESERVED_3: 5;
+            __IO uint32_t RESERVED_2: 1;
+            __IO uint32_t BIT_PERI_UART1_CLK_DIV: 2;
+            __IO uint32_t BIT_PERI_UART2_CLK_DIV: 2;
+            __IO uint32_t BIT_PERI_UART0_CLK_DIV: 2;
+            __IO uint32_t BIT_PERI_I2C0_CLK_DIV: 2;
+            __IO uint32_t BIT_PERI_I2C1_CLK_DIV: 2;
+            __IO uint32_t BIT_PERI_SPI0_CLK_DIV: 2;
+            __IO uint32_t BIT_PERI_SPI1_CLK_DIV: 2;
+            __IO uint32_t RESERVED_1: 1;
+            __IO uint32_t TIMER2_CLK_SRC_SEL: 1;
+            __IO uint32_t TIMER3_CLK_SRC_SEL: 1;
+            __IO uint32_t TIMER4_CLK_SRC_SEL: 1;
+            __IO uint32_t TIMER5_CLK_SRC_SEL: 1;
+            __IO uint32_t TIMER6_CLK_SRC_SEL: 1;
+            __IO uint32_t TIMER7_CLK_SRC_SEL: 1;
+            __IO uint32_t RESERVED_0: 2;
+        } BITS_35C;
+    } u_35C;
+
+    /* 0x0360       0x4000_0360
+        2:0     R/W    BIT_PERI_GT0_CLK_DIV                3'h0
+        5:3     R/W    BIT_PERI_GT1_CLK_DIV                3'h0
+        7:6     R/W    DUMMY                               2'h0
+        8       R/W    BIT_TIMER_CLK_32K_EN                1
+        9       R/W    BIT_TIMER_CLK_f40M_EN               1
+        10      R/W    timer_apb_clk_disable               0
+        11      R/W    gpio_intr_trig_en                   0
+        12      R/W    DUMMY                               1'h0
+        15:13   R/W    BIT_PERI_GT2_CLK_DIV                3'h0
+        18:16   R/W    BIT_PERI_GT3_CLK_DIV                3'h0
+        21:19   R/W    BIT_PERI_GT4_CLK_DIV                3'h0
+        24:22   R/W    BIT_PERI_GT5_CLK_DIV                3'h0
+        27:25   R/W    BIT_PERI_GT6_CLK_DIV                3'h0
+        30:28   R/W    BIT_PERI_GT7_CLK_DIV                3'h0
+        31      R/W    DUMMY                               0
+    */
+    union
+    {
+        __IO uint32_t PERION_REG_PERI_GTIMER_CLK_SRC0;
+        struct
+        {
+            __IO uint32_t BIT_PERI_GT0_CLK_DIV: 3;
+            __IO uint32_t BIT_PERI_GT1_CLK_DIV: 3;
+            __IO uint32_t RESERVED_2: 2;
+            __IO uint32_t BIT_TIMER_CLK_32K_EN: 1;
+            __IO uint32_t BIT_TIMER_CLK_f40M_EN: 1;
+            __IO uint32_t timer_apb_clk_disable: 1;
+            __IO uint32_t gpio_intr_trig_en: 1;
+            __IO uint32_t RESERVED_1: 1;
+            __IO uint32_t BIT_PERI_GT2_CLK_DIV: 3;
+            __IO uint32_t BIT_PERI_GT3_CLK_DIV: 3;
+            __IO uint32_t BIT_PERI_GT4_CLK_DIV: 3;
+            __IO uint32_t BIT_PERI_GT5_CLK_DIV: 3;
+            __IO uint32_t BIT_PERI_GT6_CLK_DIV: 3;
+            __IO uint32_t BIT_PERI_GT7_CLK_DIV: 3;
+            __IO uint32_t RESERVED_0: 1;
+        } BITS_360;
+    } u_360;
+
+    /* 0x0364       0x4000_0364
+        7:0     R/W    dead_zone_size                      8'h0
+        8       R/W    emg_stop                            0
+        9       R/W    stop_state[0]                       0
+        10      R/W    stop_state[1]                       0
+        11      R/W    DUMMY                               0
+        12      R/W    dead_zone_en                        0
+        13      R/W    pwm_pn_invserse_sel                 0
+        15:14   R/W    DUMMY                               2'h0
+        16      R/W    r_clk_timer_pwm_wrap0_sel           0
+        17      R/W    r_FEN_TIMER_PWM_WRAP0               0
+        18      R/W    r_CKE_TIMER_PWM_WRAP0               0
+        19      R/W    r_clk_timer_pwm_wrap0_sel1          0
+        31:20   R/W    DUMMY                               12'h0
+    */
+    union
+    {
+        __IO uint32_t PERION_REG_PERI_PWM2_DZONE_CTRL;
+        struct
+        {
+            __IO uint32_t dead_zone_size: 8;
+            __IO uint32_t emg_stop: 1;
+            __IO uint32_t stop_state_0: 1;
+            __IO uint32_t stop_state_1: 1;
+            __IO uint32_t RESERVED_2: 1;
+            __IO uint32_t dead_zone_en: 1;
+            __IO uint32_t pwm_pn_invserse_sel: 1;
+            __IO uint32_t RESERVED_1: 2;
+            __IO uint32_t r_clk_timer_pwm_wrap0_sel: 1;
+            __IO uint32_t r_FEN_TIMER_PWM_WRAP0: 1;
+            __IO uint32_t r_CKE_TIMER_PWM_WRAP0: 1;
+            __IO uint32_t r_clk_timer_pwm_wrap0_sel1: 1;
+            __IO uint32_t RESERVED_0: 12;
+        } BITS_364;
+    } u_364;
+
+    /* 0x0368       0x4000_0368
+        7:0     R/W    dead_zone_size                      8'h0
+        8       R/W    emg_stop                            0
+        9       R/W    stop_state[0]                       0
+        10      R/W    stop_state[1]                       0
+        11      R/W    DUMMY                               0
+        12      R/W    dead_zone_en                        0
+        13      R/W    pwm_pn_invserse_sel                 0
+        15:14   R/W    DUMMY                               2'h0
+        16      R/W    r_clk_timer_pwm_wrap0_sel           0
+        17      R/W    r_FEN_TIMER_PWM_WRAP0               0
+        18      R/W    r_CKE_TIMER_PWM_WRAP0               0
+        19      R/W    r_clk_timer_pwm_wrap0_sel1          0
+        31:20   R/W    DUMMY                               12'h0
+    */
+    union
+    {
+        __IO uint32_t PERION_REG_PERI_ENHTIMER0_DZONE_CTRL;
+        struct
+        {
+            __IO uint32_t dead_zone_size: 8;
+            __IO uint32_t emg_stop: 1;
+            __IO uint32_t stop_state_0: 1;
+            __IO uint32_t stop_state_1: 1;
+            __IO uint32_t RESERVED_2: 1;
+            __IO uint32_t dead_zone_en: 1;
+            __IO uint32_t pwm_pn_invserse_sel: 1;
+            __IO uint32_t RESERVED_1: 2;
+            __IO uint32_t r_clk_timer_pwm_wrap0_sel: 1;
+            __IO uint32_t r_FEN_TIMER_PWM_WRAP0: 1;
+            __IO uint32_t r_CKE_TIMER_PWM_WRAP0: 1;
+            __IO uint32_t r_clk_timer_pwm_wrap0_sel1: 1;
+            __IO uint32_t RESERVED_0: 12;
+        } BITS_368;
+    } u_368;
+
+    __IO uint32_t RSVD_0x36c[34];
+
+    /* 0x03F4       0x4000_03f4
+        31:0    R      RSVD                                32'h0
+    */
+    __IO uint32_t PERION_REG_RSVD_3F4;
+
+    /* 0x03F8       0x4000_03f8
+        0       R      r_cap_touch_clk_src_sel             1'h0
+        31:1    R      RSVD                                31'h0
+    */
+    union
+    {
+        __IO uint32_t PERION_REG_CTC_CLK_SRC_SEL;
+        struct
+        {
+            __I uint32_t r_cap_touch_clk_src_sel: 1;
+            __I uint32_t RESERVED_0: 31;
+        } BITS_3F8;
+    } u_3F8;
+
+} SYS_BLKCTRL_TypeDef;
+
+/* ================================================================================ */
+/* ================                   Peripheral                   ================ */
+/* ================================================================================ */
+
+/**
+  * @brief Peripheral. (Peripheral)
+  */
+
+typedef struct                                      /*!< Peripheral Structure */
+{
+    uint32_t RSVD0[134];                                /*!< Reserved */
+    __IO uint32_t    PERI_FUNC0_EN;                     /*!< 0x218 */
+    __IO uint32_t    PERI_FUNC1_EN;                     /*!< 0x21C */
+    __IO uint32_t    PERI_BD_FUNC0_EN;                  /*!< 0x220 */
+    uint32_t RSVD1[3];                                  /*!< Reserved */
+    __IO uint32_t    PERI_CLK_CTRL;                     /*!< 0x230 */
+    __IO uint32_t    PERI_CLK_CTRL0;                    /*!< 0x234 */
+    __IO uint32_t    PERI_CLK_CTRL1;                    /*!< 0x238 */
+} PHERIPHERIAL_TypeDef;
+
+/* ================================================================================ */
+/* ================              Peripheral Interrupt              ================ */
+/* ================================================================================ */
+
+/**
+  * @brief Peripheral Interrupt. (Peripheral Interrupt)
+  */
+
+typedef struct                 /*!< Peripheral Interrupt Structure */
+{
+    __IO uint32_t RSVD0;       /*!< 0x00 */
+    __IO uint32_t STATUS;      /*!< 0x04 */
+    __IO uint32_t MODE;        /*!< 0x08, 0: high level active, 1: edge trigger */
+    __IO uint32_t EN;          /*!< 0x0C */
+    __IO uint32_t RSVD1;       /*!< 0x10 */
+    __IO uint32_t RSVD2;       /*!< 0x14 */
+    __IO uint32_t EDGE_MODE;   /*!< 0x18, 0: rising edge (HW default), 1: both edge */
+} PERI_INT_TypeDef;
+
+
+/**
+  * @brief SoC Vendor, SOC_VENDOR_REG_BASE
+  */
+/* reference: RL6950_All_register_table_230118.xlsx */
+typedef struct
+{
+    /* 0x0000       0x4000_6000
+        15:0    R/W    Wdt_divfactor               1
+        23:16   R/W    Wdt_en_byte                 0
+        24      W1C    Wdt_clear                   0
+        28:25   R/W    Cnt_limit                   0
+        29      R/W    wdtaon_en                   1
+        30      R/W    Wdt_mode                    0
+        31      R/W1C  Wdt_to                      0
+    */
+    union
+    {
+        __IO uint32_t REGWATCH_DOG_TIMER;
+        struct
+        {
+            __IO uint32_t Wdt_divfactor: 16;
+            __IO uint32_t Wdt_en_byte: 8;
+            __IO uint32_t Wdt_clear: 1;
+            __IO uint32_t Cnt_limit: 4;
+            __IO uint32_t wdtaon_en: 1;
+            __IO uint32_t Wdt_mode: 1;
+            __IO uint32_t Wdt_to: 1;
+        } BITS_000;
+    } u_000;
+
+    /* 0x0004       0x4000_6004
+        0       R/W1C  spic0_intr                  0
+        1       R/W1C  quad_dec_intr               0
+        2       R/W1C  key_scan_intr               0
+        3       R/W1C  spi2w_intr                  0
+        4       R/W1C  lpcomp_int_r                0
+        5       R/W1C  mailbox_intr                0
+        6       R/W1C  spic1_intr                  0
+        7       R/W1C  sha256_intr                 0
+        8       R      Platform_intr               0
+        9       R/W1C  TRNG_intr                   0
+        10      R/W1C  flsh_security_intr          0
+        11      R/W1C  rtc_intr                    0
+        12      R/W1C  watch_dog_intr              0
+        31:13   R      RSVD                        0
+    */
+    union
+    {
+        __IO uint32_t REG_LOW_PRI_INT_STATUS;
+        struct
+        {
+            __IO uint32_t spic0_intr: 1;
+            __IO uint32_t quad_dec_intr: 1;
+            __IO uint32_t key_scan_intr: 1;
+            __IO uint32_t spi2w_intr: 1;
+            __IO uint32_t lpcomp_int_r: 1;
+            __IO uint32_t mailbox_intr: 1;
+            __IO uint32_t spic1_intr: 1;
+            __IO uint32_t sha256_intr: 1;
+            __I uint32_t Platform_intr: 1;
+            __IO uint32_t TRNG_intr: 1;
+            __IO uint32_t flsh_security_intr: 1;
+            __IO uint32_t rtc_intr: 1;
+            __IO uint32_t watch_dog_intr: 1;
+            __I uint32_t RESERVED_0: 19;
+        } BITS_004;
+    } u_004;
+
+    /* 0x0008       0x4000_6008
+        15:0    R/W    BIT_LOW_PRI_INT_MODE        16'hFFFF
+        31:16   R      RSVD                        0
+    */
+    union
+    {
+        __IO uint32_t REG_LOW_PRI_INT_MODE;
+        struct
+        {
+            __IO uint32_t BIT_LOW_PRI_INT_MODE: 16;
+            __I uint32_t RESERVED_0: 16;
+        } BITS_008;
+    } u_008;
+
+    /* 0x000c       0x4000_600c
+        15:0    R/W    BIT_LOW_PRI_INT_EN          0
+        31:16   R      RSVD                        0
+    */
+    union
+    {
+        __IO uint32_t REG_LOW_PRI_INT_EN;
+        struct
+        {
+            __IO uint32_t BIT_LOW_PRI_INT_EN: 16;
+            __I uint32_t RESERVED_0: 16;
+        } BITS_00c;
+    } u_00c;
+
+    /* 0x0010       0x4000_6010
+        0       R      timer_intr1andtimer_intr0   0
+        1       R      bluewiz_intr_r              0
+        2       R      hci_dma_intr                0
+        3       R      btverdor_reg_intr           0
+        4       R      pro_intr_r                  0
+        31:5    R      RSVD                        0
+    */
+    union
+    {
+        __IO uint32_t BT_MAC_interrupt;
+        struct
+        {
+            __I uint32_t timer_intr1andtimer_intr0: 1;
+            __I uint32_t bluewiz_intr_r: 1;
+            __I uint32_t hci_dma_intr: 1;
+            __I uint32_t btverdor_reg_intr: 1;
+            __I uint32_t pro_intr_r: 1;
+            __I uint32_t RESERVED_0: 27;
+        } BITS_010;
+    } u_010;
+
+    /* 0x0014       0x4000_6014
+        15:0    R      RSVD                        0
+        16      R      rxi300_intr                 0
+        17      R      rdp_intr                    0
+        18      R      rxi300_ah_intr              0
+        23:19   R      RSVD                        0
+        24      R/W    rxi300_intr_en              1
+        25      R/W    rdp_intr_en                 0
+        26      R/W    rxi300_ah_intr_en           0
+        31:27   R      RSVD                        0
+    */
+    union
+    {
+        __IO uint32_t RXI_interrupt;
+        struct
+        {
+            __I uint32_t RESERVED_2: 16;
+            __I uint32_t rxi300_intr: 1;
+            __I uint32_t rdp_intr: 1;
+            __I uint32_t rxi300_ah_intr: 1;
+            __I uint32_t RESERVED_1: 5;
+            __IO uint32_t rxi300_intr_en: 1;
+            __IO uint32_t rdp_intr_en: 1;
+            __IO uint32_t rxi300_ah_intr_en: 1;
+            __I uint32_t RESERVED_0: 5;
+        } BITS_014;
+    } u_014;
+
+    /* 0x0018       0x4000_6018
+        15:0    R/W    int_pol                     0
+        31:16   R      RSVD                        0
+    */
+    union
+    {
+        __IO uint32_t Interrupt_edge_option;
+        struct
+        {
+            __IO uint32_t int_pol: 16;
+            __I uint32_t RESERVED_0: 16;
+        } BITS_018;
+    } u_018;
+
+    /* 0x001C       0x4000_601c
+        11:0    R/W    debug_sel                   0
+        13:12   R      RSVD                        0
+        15:14   R/W    uart_force_cg_en            0
+        23:16   R/W    IRQLATENCY                  0
+        28:24   R      RSVD                        0
+        29      R/W    spi_speed_up_sim            0
+        30      R      RSVD                        0
+        31      R/W    uartlog_sir_inv             0
+    */
+    union
+    {
+        __IO uint32_t REG_DEBUG_SEL;
+        struct
+        {
+            __IO uint32_t debug_sel: 12;
+            __I uint32_t RESERVED_2: 2;
+            __IO uint32_t uart_force_cg_en: 2;
+            __IO uint32_t IRQLATENCY: 8;
+            __I uint32_t RESERVED_1: 5;
+            __IO uint32_t spi_speed_up_sim: 1;
+            __I uint32_t RESERVED_0: 1;
+            __IO uint32_t uartlog_sir_inv: 1;
+        } BITS_01C;
+    } u_01C;
+
+    /* 0x0020       0x4000_6020
+        0       R/W    BIT_I2C0_TX_BIT_SWAP_EN     0
+        1       R/W    BIT_I2C0_RX_BIT_SWAP_EN     0
+        2       R/W    BIT_I2C1_TX_BIT_SWAP_EN     0
+        3       R/W    BIT_I2C1_RX_BIT_SWAP_EN     0
+        4       R/W    BIT_I2C2_TX_BIT_SWAP_EN     0
+        5       R/W    BIT_I2C2_RX_BIT_SWAP_EN     0
+        6       R/W    BIT_I2C3_TX_BIT_SWAP_EN     0
+        7       R/W    BIT_I2C3_RX_BIT_SWAP_EN     0
+        8       R/W    BIT_SPI0_TX_BIT_SWAP_EN     0
+        9       R/W    BIT_SPI0_RX_BIT_SWAP_EN     0
+        10      R/W    BIT_SPI1_TX_BIT_SWAP_EN     0
+        11      R/W    BIT_SPI1_RX_BIT_SWAP_EN     0
+        12      R/W    BIT_SPI2_TX_BIT_SWAP_EN     0
+        13      R/W    BIT_SPI2_RX_BIT_SWAP_EN     0
+        15:14   R      RSVD                        0
+        16      R/W    SPI0_TX_BYTE_SWAP_EN        0
+        17      R/W    SPI0_RX_BYTE_SWAP_EN        0
+        18      R/W    SPI1_TX_BYTE_SWAP_EN        0
+        19      R/W    SPI1_RX_BYTE_SWAP_EN        0
+        20      R/W    SPI2_TX_BYTE_SWAP_EN        0
+        21      R/W    SPI2_RX_BYTE_SWAP_EN        0
+        28:22   R      RSVD                        0
+        29      W1O    EFUSE_RP_bk1                0
+        30      W1O    EFUSE_WP                    0
+        31      W1O    EFUSE_RP                    0
+    */
+    union
+    {
+        __IO uint32_t REG_DATA_FIFO_SWAP_CTRL;
+        struct
+        {
+            __IO uint32_t BIT_I2C0_TX_BIT_SWAP_EN: 1;
+            __IO uint32_t BIT_I2C0_RX_BIT_SWAP_EN: 1;
+            __IO uint32_t BIT_I2C1_TX_BIT_SWAP_EN: 1;
+            __IO uint32_t BIT_I2C1_RX_BIT_SWAP_EN: 1;
+            __IO uint32_t BIT_I2C2_TX_BIT_SWAP_EN: 1;
+            __IO uint32_t BIT_I2C2_RX_BIT_SWAP_EN: 1;
+            __IO uint32_t BIT_I2C3_TX_BIT_SWAP_EN: 1;
+            __IO uint32_t BIT_I2C3_RX_BIT_SWAP_EN: 1;
+            __IO uint32_t BIT_SPI0_TX_BIT_SWAP_EN: 1;
+            __IO uint32_t BIT_SPI0_RX_BIT_SWAP_EN: 1;
+            __IO uint32_t BIT_SPI1_TX_BIT_SWAP_EN: 1;
+            __IO uint32_t BIT_SPI1_RX_BIT_SWAP_EN: 1;
+            __IO uint32_t BIT_SPI2_TX_BIT_SWAP_EN: 1;
+            __IO uint32_t BIT_SPI2_RX_BIT_SWAP_EN: 1;
+            __I uint32_t RESERVED_1: 2;
+            __IO uint32_t SPI0_TX_BYTE_SWAP_EN: 1;
+            __IO uint32_t SPI0_RX_BYTE_SWAP_EN: 1;
+            __IO uint32_t SPI1_TX_BYTE_SWAP_EN: 1;
+            __IO uint32_t SPI1_RX_BYTE_SWAP_EN: 1;
+            __IO uint32_t SPI2_TX_BYTE_SWAP_EN: 1;
+            __IO uint32_t SPI2_RX_BYTE_SWAP_EN: 1;
+            __I uint32_t RESERVED_0: 7;
+            __IO uint32_t EFUSE_RP_bk1: 1;
+            __IO uint32_t EFUSE_WP: 1;
+            __IO uint32_t EFUSE_RP: 1;
+        } BITS_020;
+    } u_020;
+
+    /* 0x0024       0x4000_6024
+        0       R      TIMER0togglebit             0
+        1       R      TIMER1togglebit             0
+        2       R      TIMER2togglebit             0
+        3       R      TIMER3togglebit             0
+        4       R      TIMER4togglebit             0
+        5       R      TIMER5togglebit             0
+        6       R      TIMER6togglebit             0
+        7       R      TIMER7togglebit             0
+        8       R/W    spic0_mem_wr_en             0
+        9       R/W    spic1_mem_wr_en             0
+        10      W1O    dram_c2s_remap_dis          1
+        11      R/W    spic_icg_disable            0
+        12      R/W    ic_icg_disable              0
+        13      R/W    dmac_clk_always_disable     0
+        14      R/W    dmac_clk_always_enable      0
+        15      R/W    rxi300_auto_icg_en          1
+        23:16   R/W    timer_dma_en                0
+        24      W1O    dram_c2s_remap_dis_wlock    0
+        25      R/W    RSVD                        0
+        26      R/W    RSVD                        0
+        30:27   R      RSVD                        7'd0
+        31      R/W    fwpi_enable                 1
+    */
+    union
+    {
+        __IO uint32_t DUMMY_;
+        struct
+        {
+            __I uint32_t TIMER0togglebit: 1;
+            __I uint32_t TIMER1togglebit: 1;
+            __I uint32_t TIMER2togglebit: 1;
+            __I uint32_t TIMER3togglebit: 1;
+            __I uint32_t TIMER4togglebit: 1;
+            __I uint32_t TIMER5togglebit: 1;
+            __I uint32_t TIMER6togglebit: 1;
+            __I uint32_t TIMER7togglebit: 1;
+            __IO uint32_t spic0_mem_wr_en: 1;
+            __IO uint32_t spic1_mem_wr_en: 1;
+            __IO uint32_t dram_c2s_remap_dis: 1;
+            __IO uint32_t spic_icg_disable: 1;
+            __IO uint32_t ic_icg_disable: 1;
+            __IO uint32_t dmac_clk_always_disable: 1;
+            __IO uint32_t dmac_clk_always_enable: 1;
+            __IO uint32_t rxi300_auto_icg_en: 1;
+            __IO uint32_t timer_dma_en: 8;
+            __IO uint32_t dram_c2s_remap_dis_wlock: 1;
+            __IO uint32_t RESERVED_2: 1;
+            __IO uint32_t RESERVED_1: 1;
+            __I uint32_t RESERVED_0: 4;
+            __IO uint32_t fwpi_enable: 1;
+        } BITS_024;
+    } u_024;
+
+    /* 0x0028       0x4000_6028
+        5:0     R/W    enhtimer_gpio_trig_sel      6'h3f
+        6       R/W    enhtimer_trig_sel           0
+        7       R/W    enhtimer_gpio_trig_bt_en    0
+        8       R/W    enhtimer_gpio_trig_timer_en 0
+        31:9    R      RSVD                        23'd0
+    */
+    union
+    {
+        __IO uint32_t REG_ENHTIMER_TRIG_CTRL;
+        struct
+        {
+            __IO uint32_t enhtimer_gpio_trig_sel: 6;
+            __IO uint32_t enhtimer_trig_sel: 1;
+            __IO uint32_t enhtimer_gpio_trig_bt_en: 1;
+            __IO uint32_t enhtimer_gpio_trig_timer_en: 1;
+            __I uint32_t RESERVED_0: 23;
+        } BITS_028;
+    } u_028;
+
+    /* 0x002C       0x4000_602c
+        0       R/W    r_systick_timer_manual_rstb 0
+        1       R/W    r_systick_timer_rst_sel     1
+        31:2    R      RSVD                        30'h0
+    */
+    union
+    {
+        __IO uint32_t REG_SYSTICK_TIMER_CTRL;
+        struct
+        {
+            __IO uint32_t r_systick_timer_manual_rstb: 1;
+            __IO uint32_t r_systick_timer_rst_sel: 1;
+            __I uint32_t RESERVED_0: 30;
+        } BITS_02C;
+    } u_02C;
+
+    /* 0x0030       0x4000_6030
+        31:0    R      cpu_systick_timer_cnt       32'h0
+    */
+    union
+    {
+        __IO uint32_t REG_SYSTICK_TIMER_CNT;
+        struct
+        {
+            __I uint32_t cpu_systick_timer_cnt: 32;
+        } BITS_030;
+    } u_030;
+
+    /* 0x0034       0x4000_6034
+        0       R/W    TIMER_INT_EN                1'b0
+        1       R/W    VLD_TIMER                   1'b0
+        30:2    R      RSVD                        30'h0
+        31      R/W    VLD_TIMER_FAKE_INFPGA       1'b0
+    */
+    union
+    {
+        __IO uint32_t REG_TMETER_CTRL;
+        struct
+        {
+            __IO uint32_t TIMER_INT_EN: 1;
+            __IO uint32_t VLD_TIMER: 1;
+            __I uint32_t RESERVED_0: 29;
+            __IO uint32_t VLD_TIMER_FAKE_INFPGA: 1;
+        } BITS_034;
+    } u_034;
+
+    /* 0x0038       0x4000_6038
+        0       R/W1C  VLD_TIMER_INT               1'b0
+        31:1    R      RSVD                        30'h0
+    */
+    union
+    {
+        __IO uint32_t REG_TMETER_INT_STS;
+        struct
+        {
+            __IO uint32_t VLD_TIMER_INT: 1;
+            __I uint32_t RESERVED_0: 31;
+        } BITS_038;
+    } u_038;
+
+    /* 0x003C       0x4000_603c
+        0       R/W    rtc_nmi_int_enable          1'b0
+        31:1    R      RSVD                        30'h0
+    */
+    union
+    {
+        __IO uint32_t REG_NMI_INT;
+        struct
+        {
+            __IO uint32_t rtc_nmi_int_enable: 1;
+            __I uint32_t RESERVED_0: 31;
+        } BITS_03C;
+    } u_03C;
+
+    /* 0x0040       0x4000_6040
+        2:0     R/W    bist_rstn_mcu_rom           0
+        4:3     R      RSVD                        0
+        5       R/W    RSVD                        0
+        10:6    R/W    bist_rstn_data_ram          0
+        11      R      RSVD                        0
+        12      R/W    bist_rstn_buffer_ram        0
+        16:13   R      RSVD                        0
+        25:17   R/W    bist_rstn_cache_ram         0
+        31:26   R      RSVD                        0
+    */
+    union
+    {
+        __IO uint32_t REG_BIST_RSTN;
+        struct
+        {
+            __IO uint32_t bist_rstn_mcu_rom: 3;
+            __I uint32_t RESERVED_4: 2;
+            __IO uint32_t RESERVED_3: 1;
+            __IO uint32_t bist_rstn_data_ram: 5;
+            __I uint32_t RESERVED_2: 1;
+            __IO uint32_t bist_rstn_buffer_ram: 1;
+            __I uint32_t RESERVED_1: 4;
+            __IO uint32_t bist_rstn_cache_ram: 9;
+            __I uint32_t RESERVED_0: 6;
+        } BITS_040;
+    } u_040;
+
+    /* 0x0044       0x4000_6044
+        2:0     R/W    bist_mode_mcu_rom           0
+        4:3     R      RSVD                        0
+        5       R/W    RSVD                        0
+        10:6    R/W    bist_mode_data_ram          0
+        11      R      RSVD                        0
+        12      R/W    bist_mode_buffer_ram        0
+        16:13   R      RSVD                        0
+        25:17   R/W    bist_mode_cache_ram         0
+        31:26   R      RSVD                        0
+    */
+    union
+    {
+        __IO uint32_t REG_BIST_MODE;
+        struct
+        {
+            __IO uint32_t bist_mode_mcu_rom: 3;
+            __I uint32_t RESERVED_4: 2;
+            __IO uint32_t RESERVED_3: 1;
+            __IO uint32_t bist_mode_data_ram: 5;
+            __I uint32_t RESERVED_2: 1;
+            __IO uint32_t bist_mode_buffer_ram: 1;
+            __I uint32_t RESERVED_1: 4;
+            __IO uint32_t bist_mode_cache_ram: 9;
+            __I uint32_t RESERVED_0: 6;
+        } BITS_044;
+    } u_044;
+
+    /* 0x0048       0x4000_6048
+        5:0     R      RSVD                        0
+        10:6    R/W    drf_bist_mode_data_ram      0
+        11      R      RSVD                        0
+        12      R/W    drf_bist_mode_buffer_ram    0
+        16:13   R      RSVD                        0
+        25:17   R/W    drf_bist_mode_cache_ram     0
+        31:26   R      RSVD                        0
+    */
+    union
+    {
+        __IO uint32_t REG_DRF_BIST_MODE;
+        struct
+        {
+            __I uint32_t RESERVED_3: 6;
+            __IO uint32_t drf_bist_mode_data_ram: 5;
+            __I uint32_t RESERVED_2: 1;
+            __IO uint32_t drf_bist_mode_buffer_ram: 1;
+            __I uint32_t RESERVED_1: 4;
+            __IO uint32_t drf_bist_mode_cache_ram: 9;
+            __I uint32_t RESERVED_0: 6;
+        } BITS_048;
+    } u_048;
+
+    /* 0x004C       0x4000_604c
+        5:0     R      RSVD                        0
+        10:6    R/W    bist_resume_data_ram        0
+        11      R      RSVD                        0
+        12      R/W    bist_resume_buffer_ram      0
+        16:13   R      RSVD                        0
+        25:17   R/W    bist_resume_cache_ram       0
+        31:26   R      RSVD                        0
+    */
+    union
+    {
+        __IO uint32_t REG_BIST_TEST_RESUME;
+        struct
+        {
+            __I uint32_t RESERVED_3: 6;
+            __IO uint32_t bist_resume_data_ram: 5;
+            __I uint32_t RESERVED_2: 1;
+            __IO uint32_t bist_resume_buffer_ram: 1;
+            __I uint32_t RESERVED_1: 4;
+            __IO uint32_t bist_resume_cache_ram: 9;
+            __I uint32_t RESERVED_0: 6;
+        } BITS_04C;
+    } u_04C;
+
+    /* 0x0050       0x4000_6050
+        5:0     R      RSVD                        0
+        10:6    R      bist_start_pause_data_ram   0
+        11      R      RSVD                        0
+        12      R      bist_start_pause_buffer_ram 0
+        16:13   R      RSVD                        0
+        25:17   R      bist_start_pause_cache_ram  0
+        31:26   R      RSVD                        0
+    */
+    union
+    {
+        __IO uint32_t REG_BIST_START_PAUSE;
+        struct
+        {
+            __I uint32_t RESERVED_3: 6;
+            __I uint32_t bist_start_pause_data_ram: 5;
+            __I uint32_t RESERVED_2: 1;
+            __I uint32_t bist_start_pause_buffer_ram: 1;
+            __I uint32_t RESERVED_1: 4;
+            __I uint32_t bist_start_pause_cache_ram: 9;
+            __I uint32_t RESERVED_0: 6;
+        } BITS_050;
+    } u_050;
+
+    /* 0x0054       0x4000_6054
+        2:0     R      bist_done_mcu_rom           0
+        4:3     R      RSVD                        0
+        5       R      RSVD                        0
+        10:6    R      bist_done_data_ram          0
+        11      R      RSVD                        0
+        12      R      bist_done_buffer_ram        0
+        16:13   R      RSVD                        0
+        25:17   R      bist_done_cache_ram         0
+        31:26   R      RSVD                        0
+    */
+    union
+    {
+        __IO uint32_t REG_BIST_DONE;
+        struct
+        {
+            __I uint32_t bist_done_mcu_rom: 3;
+            __I uint32_t RESERVED_4: 2;
+            __I uint32_t RESERVED_3: 1;
+            __I uint32_t bist_done_data_ram: 5;
+            __I uint32_t RESERVED_2: 1;
+            __I uint32_t bist_done_buffer_ram: 1;
+            __I uint32_t RESERVED_1: 4;
+            __I uint32_t bist_done_cache_ram: 9;
+            __I uint32_t RESERVED_0: 6;
+        } BITS_054;
+    } u_054;
+
+    /* 0x0058       0x4000_6058
+        5:0     R      RSVD                        0
+        10:6    R      bist_fail_data_ram          0
+        11      R      RSVD                        0
+        12      R      bist_fail_buffer_ram        0
+        16:13   R      RSVD                        0
+        25:17   R      bist_fail_cache_ram         0
+        31:26   R      RSVD                        0
+    */
+    union
+    {
+        __IO uint32_t REG_BIST_FAIL;
+        struct
+        {
+            __I uint32_t RESERVED_3: 6;
+            __I uint32_t bist_fail_data_ram: 5;
+            __I uint32_t RESERVED_2: 1;
+            __I uint32_t bist_fail_buffer_ram: 1;
+            __I uint32_t RESERVED_1: 4;
+            __I uint32_t bist_fail_cache_ram: 9;
+            __I uint32_t RESERVED_0: 6;
+        } BITS_058;
+    } u_058;
+
+    /* 0x005C       0x4000_605c
+        5:0     R      RSVD                        0
+        10:6    R      drf_bist_done_data_ram      0
+        11      R      RSVD                        0
+        12      R      drf_bist_done_buffer_ram    0
+        16:13   R      RSVD                        0
+        25:17   R      drf_bist_done_cache_ram     0
+        31:26   R      RSVD                        0
+    */
+    union
+    {
+        __IO uint32_t REG_DRF_BIST_DONE;
+        struct
+        {
+            __I uint32_t RESERVED_3: 6;
+            __I uint32_t drf_bist_done_data_ram: 5;
+            __I uint32_t RESERVED_2: 1;
+            __I uint32_t drf_bist_done_buffer_ram: 1;
+            __I uint32_t RESERVED_1: 4;
+            __I uint32_t drf_bist_done_cache_ram: 9;
+            __I uint32_t RESERVED_0: 6;
+        } BITS_05C;
+    } u_05C;
+
+    /* 0x0060       0x4000_6060
+        5:0     R      RSVD                        0
+        10:6    R      drf_bist_fail_data_ram      0
+        11      R      RSVD                        0
+        12      R      drf_bist_fail_buffer_ram    0
+        16:13   R      RSVD                        0
+        25:17   R      drf_bist_fail_cache_ram     0
+        31:26   R      RSVD                        0
+    */
+    union
+    {
+        __IO uint32_t REG_DRF_BIST_FAIL;
+        struct
+        {
+            __I uint32_t RESERVED_3: 6;
+            __I uint32_t drf_bist_fail_data_ram: 5;
+            __I uint32_t RESERVED_2: 1;
+            __I uint32_t drf_bist_fail_buffer_ram: 1;
+            __I uint32_t RESERVED_1: 4;
+            __I uint32_t drf_bist_fail_cache_ram: 9;
+            __I uint32_t RESERVED_0: 6;
+        } BITS_060;
+    } u_060;
+
+    /* 0x0064       0x4000_6064
+        31:0    R      mcu_rom0_misr31_0           0
+    */
+    union
+    {
+        __IO uint32_t REG_MCU_ROM0_MISR0;
+        struct
+        {
+            __I uint32_t mcu_rom0_misr31_0: 32;
+        } BITS_064;
+    } u_064;
+
+    /* 0x0068       0x4000_6068
+        31:0    R      mcu_rom0_misr63_32          0
+    */
+    union
+    {
+        __IO uint32_t REG_MCU_ROM0_MISR1;
+        struct
+        {
+            __I uint32_t mcu_rom0_misr63_32: 32;
+        } BITS_068;
+    } u_068;
+
+    /* 0x006C       0x4000_606c
+        31:0    R      mcu_rom1_misr31_0           0
+    */
+    union
+    {
+        __IO uint32_t REG_MCU_ROM1_MISR0;
+        struct
+        {
+            __I uint32_t mcu_rom1_misr31_0: 32;
+        } BITS_06C;
+    } u_06C;
+
+    /* 0x0070       0x4000_6070
+        31:0    R      mcu_rom1_misr63_32          0
+    */
+    union
+    {
+        __IO uint32_t REG_MCU_ROM1_MISR1;
+        struct
+        {
+            __I uint32_t mcu_rom1_misr63_32: 32;
+        } BITS_070;
+    } u_070;
+
+    /* 0x0074       0x4000_6074
+        31:0    R      mcu_rom2_misr31_0           0
+    */
+    union
+    {
+        __IO uint32_t REG_MCU_ROM2_MISR0;
+        struct
+        {
+            __I uint32_t mcu_rom2_misr31_0: 32;
+        } BITS_074;
+    } u_074;
+
+    /* 0x0078       0x4000_6078
+        31:0    R      mcu_rom2_misr63_32          0
+    */
+    union
+    {
+        __IO uint32_t REG_MCU_ROM2_MISR1;
+        struct
+        {
+            __I uint32_t mcu_rom2_misr63_32: 32;
+        } BITS_078;
+    } u_078;
+
+    /* 0x007C       0x4000_607c
+        31:0    R      mcu_rom3_misr31_0           0
+    */
+    union
+    {
+        __IO uint32_t REG_MCU_ROM3_MISR0;
+        struct
+        {
+            __I uint32_t mcu_rom3_misr31_0: 32;
+        } BITS_07C;
+    } u_07C;
+
+    /* 0x0080       0x4000_6080
+        31:0    R      mcu_rom3_misr63_32          0
+    */
+    union
+    {
+        __IO uint32_t REG_MCU_ROM3_MISR1;
+        struct
+        {
+            __I uint32_t mcu_rom3_misr63_32: 32;
+        } BITS_080;
+    } u_080;
+
+    /* 0x0084       0x4000_6084
+        31:0    R      mcu_rom4_misr31_0           0
+    */
+    union
+    {
+        __IO uint32_t REG_MCU_ROM4_MISR0;
+        struct
+        {
+            __I uint32_t mcu_rom4_misr31_0: 32;
+        } BITS_084;
+    } u_084;
+
+    /* 0x0088       0x4000_6088
+        31:0    R      mcu_rom4_misr63_32          0
+    */
+    union
+    {
+        __IO uint32_t REG_MCU_ROM4_MISR1;
+        struct
+        {
+            __I uint32_t mcu_rom4_misr63_32: 32;
+        } BITS_088;
+    } u_088;
+
+    __IO uint32_t RSVD_0x8c[1];
+
+    /* 0x0090       0x4000_6090
+        31:0    R/W    OUT_DATA0                   0
+    */
+    union
+    {
+        __IO uint32_t REG_I2C_MAILBOX_OUT_DATA0;
+        struct
+        {
+            __IO uint32_t OUT_DATA0: 32;
+        } BITS_090;
+    } u_090;
+
+    /* 0x0094       0x4000_6094
+        31:0    R/W    OUT_DATA1                   0
+    */
+    union
+    {
+        __IO uint32_t REG_I2C_MAILBOX_OUT_DATA1;
+        struct
+        {
+            __IO uint32_t OUT_DATA1: 32;
+        } BITS_094;
+    } u_094;
+
+    /* 0x0098       0x4000_6098
+        31:0    R      IN_DATA0                    0
+    */
+    union
+    {
+        __IO uint32_t REG_I2C_MAILBOX_IN_DATA0;
+        struct
+        {
+            __I uint32_t IN_DATA0: 32;
+        } BITS_098;
+    } u_098;
+
+    /* 0x009C       0x4000_609c
+        31:0    R      IN_DATA1                    0
+    */
+    union
+    {
+        __IO uint32_t REG_I2C_MAILBOX_IN_DATA1;
+        struct
+        {
+            __I uint32_t IN_DATA1: 32;
+        } BITS_09C;
+    } u_09C;
+
+    /* 0x00A0       0x4000_60a0
+        0       R/W1C  outbox_rdy_r                0
+        1       R/W    out_empty_inten             0
+        2       R/W    out_int_mode                0
+        3       R/W1C  out_edge_sts                0
+        4       R      rx_data_crc_ok              0
+        15:5    R      RSVD                        0
+        16      R/W1C  inbox_rdy_r                 0
+        17      R/W    in_rdy_inten                0
+        30:18   R      RSVD                        0
+        31      R/W    pta_i2c_en                  0
+    */
+    union
+    {
+        __IO uint32_t REG_I2C_MAILBOX_CTRL;
+        struct
+        {
+            __IO uint32_t outbox_rdy_r: 1;
+            __IO uint32_t out_empty_inten: 1;
+            __IO uint32_t out_int_mode: 1;
+            __IO uint32_t out_edge_sts: 1;
+            __I uint32_t rx_data_crc_ok: 1;
+            __I uint32_t RESERVED_1: 11;
+            __IO uint32_t inbox_rdy_r: 1;
+            __IO uint32_t in_rdy_inten: 1;
+            __I uint32_t RESERVED_0: 13;
+            __IO uint32_t pta_i2c_en: 1;
+        } BITS_0A0;
+    } u_0A0;
+
+    __IO uint32_t RSVD_0xa4[2];
+
+    /* 0x00AC       0x4000_60ac
+        7:0     R/W    EFUSE_PGPWD                 0
+        31:8    R      RSVD                        0
+    */
+    union
+    {
+        __IO uint32_t EFUSE_PGPWD;
+        struct
+        {
+            __IO uint32_t EFUSE_PGPWD: 8;
+            __I uint32_t RESERVED_0: 24;
+        } BITS_0AC;
+    } u_0AC;
+
+    /* 0x00B0       0x4000_60b0
+        7:0     W      EFUSE_DATA                  0
+        16:8    R/W    EFUSE_ADDR                  0
+        17      R      RSVD                        0
+        18      R/W    EFUSE_ALDEN                 0
+        19      R      RSVD                        0
+        23:20   R/W    EFUSE_PGT                   4'ha
+        26:24   R/W    EFUSE_VDDQST                3'h1
+        27      R/W    EFUSE_RDT                   0
+        30:28   R/W    EFUSE_PGPD                  3'h3
+        31      W1S    EFUSE_RWFLAG                0
+    */
+    union
+    {
+        __IO uint32_t REG_EFUSE_CTRL;
+        struct
+        {
+            __O uint32_t EFUSE_DATA: 8;
+            __IO uint32_t EFUSE_ADDR: 9;
+            __I uint32_t RESERVED_1: 1;
+            __IO uint32_t EFUSE_ALDEN: 1;
+            __I uint32_t RESERVED_0: 1;
+            __IO uint32_t EFUSE_PGT: 4;
+            __IO uint32_t EFUSE_VDDQST: 3;
+            __IO uint32_t EFUSE_RDT: 1;
+            __IO uint32_t EFUSE_PGPD: 3;
+            __IO uint32_t EFUSE_RWFLAG: 1;
+        } BITS_0B0;
+    } u_0B0;
+
+    /* 0x00B4       0x4000_60b4
+        6:0     W      EFSCAN_FTHR                 0
+        7       R      ef_scanfail_out             0
+        9:8     R/W    EFCELL_SEL                  0
+        10      R/W    r_PWC_EV2EF                 0
+        11      R/W    EFPGMEN_FORCE               0
+        15:12   R/W    EFSCAN_EADR                 0
+        24:16   R/W    EFSCAN_SADR                 0
+        25      R/W    EFPD_DIS                    0
+        26      R/W    EFCRES_SEL                  0
+        30:27   R/W    LDOE25_VADJ                 4'h3
+        31      R/W    LDOE25_EN                   0
+    */
+    union
+    {
+        __IO uint32_t REG_EFUSE_TEST;
+        struct
+        {
+            __O uint32_t EFSCAN_FTHR: 7;
+            __I uint32_t ef_scanfail_out: 1;
+            __IO uint32_t EFCELL_SEL: 2;
+            __IO uint32_t r_PWC_EV2EF: 1;
+            __IO uint32_t EFPGMEN_FORCE: 1;
+            __IO uint32_t EFSCAN_EADR: 4;
+            __IO uint32_t EFSCAN_SADR: 9;
+            __IO uint32_t EFPD_DIS: 1;
+            __IO uint32_t EFCRES_SEL: 1;
+            __IO uint32_t LDOE25_VADJ: 4;
+            __IO uint32_t LDOE25_EN: 1;
+        } BITS_0B4;
+    } u_0B4;
+
+    /* 0x00B8       0x4000_60b8
+        1:0     R/W    RARSVD                      0
+        4:2     R      RSVD                        0
+        7:5     R/W    WPULSERSVD                  0
+        31:8    R      RSVD                        0
+    */
+    union
+    {
+        __IO uint32_t REG_SNPS_SRAM_CTRL;
+        struct
+        {
+            __IO uint32_t RARSVD: 2;
+            __I uint32_t RESERVED_1: 3;
+            __IO uint32_t WPULSERSVD: 3;
+            __I uint32_t RESERVED_0: 24;
+        } BITS_0B8;
+    } u_0B8;
+
+    /* 0x00BC       0x4000_60bc
+        31:0    R      RSVD                        0
+    */
+    __IO uint32_t REG_0x00BC;
+
+    /* 0x00C0       0x4000_60c0
+        31:0    R      RSVD                        0
+    */
+    __IO uint32_t Reserved_2;
+
+    /* 0x00C4       0x4000_60c4
+        31:0    R      RSVD                        0
+    */
+    __IO uint32_t Reserved_3;
+
+    /* 0x00C8       0x4000_60c8
+        31:0    R      RSVD                        0
+    */
+    __IO uint32_t Reserved_4;
+
+    /* 0x00CC       0x4000_60cc
+        31:0    R      RSVD                        0
+    */
+    __IO uint32_t Reserved_5;
+
+    /* 0x00D0       0x4000_60d0
+        31:0    R      RSVD                        0
+    */
+    __IO uint32_t Reserved_6;
+
+    /* 0x00D4       0x4000_60d4
+        3:0     R/W    bist_dyn_read_en_btmac      0
+        9:4     R      RSVD                        0
+        10      R/W    bist_dyn_read_en_data_ram   0
+        11      R/W    bist_dyn_read_cache_ram     0
+        12      R/W    bist_dyn_read_buffer_ram    0
+        15:13   R      RSVD                        0
+        16      R/W    bist_dyn_read_en_btphy      0
+        20:17   R      RSVD                        0
+        23:21   R/W    bist_dyn_read_en_zigbee     0
+        27:24   R      RSVD                        0
+        28      R/W    bist_dyn_read_en_audio      0
+        31:29   R      RSVD                        0
+    */
+    union
+    {
+        __IO uint32_t REG_DYN_READ_EN;
+        struct
+        {
+            __IO uint32_t bist_dyn_read_en_btmac: 4;
+            __I uint32_t RESERVED_4: 6;
+            __IO uint32_t bist_dyn_read_en_data_ram: 1;
+            __IO uint32_t bist_dyn_read_cache_ram: 1;
+            __IO uint32_t bist_dyn_read_buffer_ram: 1;
+            __I uint32_t RESERVED_3: 3;
+            __IO uint32_t bist_dyn_read_en_btphy: 1;
+            __I uint32_t RESERVED_2: 4;
+            __IO uint32_t bist_dyn_read_en_zigbee: 3;
+            __I uint32_t RESERVED_1: 4;
+            __IO uint32_t bist_dyn_read_en_audio: 1;
+            __I uint32_t RESERVED_0: 3;
+        } BITS_0D4;
+    } u_0D4;
+
+    /* 0x00D8       0x4000_60d8
+        5:0     R      RSVD                        0
+        10:6    R/W    bist_loop_mode_data_ram     0
+        11      R      RSVD                        0
+        12      R/W    bist_loop_mode_buffer_ram   0
+        16:13   R      RSVD                        0
+        25:17   R/W    bist_loop_mode_cache_ram    0
+        31:26   R      RSVD                        0
+    */
+    union
+    {
+        __IO uint32_t REG_BIST_LOOP_MODE;
+        struct
+        {
+            __I uint32_t RESERVED_3: 6;
+            __IO uint32_t bist_loop_mode_data_ram: 5;
+            __I uint32_t RESERVED_2: 1;
+            __IO uint32_t bist_loop_mode_buffer_ram: 1;
+            __I uint32_t RESERVED_1: 4;
+            __IO uint32_t bist_loop_mode_cache_ram: 9;
+            __I uint32_t RESERVED_0: 6;
+        } BITS_0D8;
+    } u_0D8;
+
+    /* 0x00DC       0x4000_60dc
+        3:0     R/W    bist_loop_mode_btmac        0
+        15:4    R      RSVD                        0
+        16      R/W    bist_loop_mode_btphy        0
+        20:17   R      RSVD                        0
+        23:21   R/W    bist_loop_mode_zigbee       0
+        27:24   R      RSVD                        0
+        28      R/W    bist_loop_mode_audio        0
+        31:29   R      RSVD                        0
+    */
+    union
+    {
+        __IO uint32_t REG_OTHER_BIST_LOOP_MODE;
+        struct
+        {
+            __IO uint32_t bist_loop_mode_btmac: 4;
+            __I uint32_t RESERVED_3: 12;
+            __IO uint32_t bist_loop_mode_btphy: 1;
+            __I uint32_t RESERVED_2: 4;
+            __IO uint32_t bist_loop_mode_zigbee: 3;
+            __I uint32_t RESERVED_1: 4;
+            __IO uint32_t bist_loop_mode_audio: 1;
+            __I uint32_t RESERVED_0: 3;
+        } BITS_0DC;
+    } u_0DC;
+
+    /* 0x00E0       0x4000_60e0
+        3:0     R/W    bist_rstn_btmac             0
+        15:4    R      RSVD                        0
+        16      R/W    bist_rstn_btphy             0
+        20:17   R      RSVD                        0
+        23:21   R/W    bist_mode_zigbee            0
+        27:24   R      RSVD                        0
+        28      R/W    bist_rstn_audio             0
+        31:29   R      RSVD                        0
+    */
+    union
+    {
+        __IO uint32_t REG_OTHER_BIST_RSTN;
+        struct
+        {
+            __IO uint32_t bist_rstn_btmac: 4;
+            __I uint32_t RESERVED_3: 12;
+            __IO uint32_t bist_rstn_btphy: 1;
+            __I uint32_t RESERVED_2: 4;
+            __IO uint32_t bist_mode_zigbee: 3;
+            __I uint32_t RESERVED_1: 4;
+            __IO uint32_t bist_rstn_audio: 1;
+            __I uint32_t RESERVED_0: 3;
+        } BITS_0E0;
+    } u_0E0;
+
+    /* 0x00E4       0x4000_60e4
+        3:0     R/W    bist_mode_btmac             0
+        15:4    R      RSVD                        0
+        20:16   R/W    bist_mode_btphy             0
+        27:21   R/W    bist_mode_zigbee            0
+        28      R/W    bist_mode_audio             0
+        31:29   R      RSVD                        0
+    */
+    union
+    {
+        __IO uint32_t REG_OTHER_BIST_MODE;
+        struct
+        {
+            __IO uint32_t bist_mode_btmac: 4;
+            __I uint32_t RESERVED_1: 12;
+            __IO uint32_t bist_mode_btphy: 5;
+            __IO uint32_t bist_mode_zigbee: 7;
+            __IO uint32_t bist_mode_audio: 1;
+            __I uint32_t RESERVED_0: 3;
+        } BITS_0E4;
+    } u_0E4;
+
+    /* 0x00E8       0x4000_60e8
+        3:0     R/W    drf_bist_mode_btmac         0
+        15:4    R      RSVD                        0
+        20:16   R/W    drf_bist_mode_btphy         0
+        27:21   R      RSVD                        0
+        28      R/W    drf_bist_mode_audio         0
+        31:29   R      RSVD                        0
+    */
+    union
+    {
+        __IO uint32_t REG_OTHER_DRF_BIST_MODE;
+        struct
+        {
+            __IO uint32_t drf_bist_mode_btmac: 4;
+            __I uint32_t RESERVED_2: 12;
+            __IO uint32_t drf_bist_mode_btphy: 5;
+            __I uint32_t RESERVED_1: 7;
+            __IO uint32_t drf_bist_mode_audio: 1;
+            __I uint32_t RESERVED_0: 3;
+        } BITS_0E8;
+    } u_0E8;
+
+    /* 0x00EC       0x4000_60ec
+        3:0     R/W    bist_resume_btmac           0
+        15:4    R      RSVD                        0
+        16      R/W    bist_resume_btphy           0
+        20:17   R      RSVD                        0
+        23:21   R/W    bist_resume_zigbee          0
+        27:24   R      RSVD                        0
+        28      R/W    bist_resume_audio           0
+        31:29   R      RSVD                        0
+    */
+    union
+    {
+        __IO uint32_t REG_OTHER_BIST_TEST_RESUME;
+        struct
+        {
+            __IO uint32_t bist_resume_btmac: 4;
+            __I uint32_t RESERVED_3: 12;
+            __IO uint32_t bist_resume_btphy: 1;
+            __I uint32_t RESERVED_2: 4;
+            __IO uint32_t bist_resume_zigbee: 3;
+            __I uint32_t RESERVED_1: 4;
+            __IO uint32_t bist_resume_audio: 1;
+            __I uint32_t RESERVED_0: 3;
+        } BITS_0EC;
+    } u_0EC;
+
+    /*    0x00F0    0x4000_60f0
+        3:0     R      bist_start_pause_btmac      0
+        15:4    R      RSVD                        0
+        16      R      bist_start_pause_btphy      0
+        20:17   R      RSVD                        0
+        23:21   R      bist_start_pause_zigbee     0
+        27:24   R      RSVD                        0
+        28      R      bist_start_pause_audio      0
+        31:29   R      RSVD                        0
+    */
+    union
+    {
+        __IO uint32_t REG_OTHER_BIST_START_PAUSE;
+        struct
+        {
+            __I uint32_t bist_start_pause_btmac: 4;
+            __I uint32_t RESERVED_3: 12;
+            __I uint32_t bist_start_pause_btphy: 1;
+            __I uint32_t RESERVED_2: 4;
+            __I uint32_t bist_start_pause_zigbee: 3;
+            __I uint32_t RESERVED_1: 4;
+            __I uint32_t bist_start_pause_audio: 1;
+            __I uint32_t RESERVED_0: 3;
+        } BITS_0F0;
+    } u_0F0;
+
+    /*    0x00F4    0x4000_60f4
+        3:0     R      bist_done_btmac             0
+        15:4    R      RSVD                        0
+        16      R      bist_done_btphy             0
+        20:17   R      RSVD                        0
+        23:21   R      bist_done_zigbee            0
+        27:24   R      RSVD                        0
+        28      R      bist_done_audio             0
+        31:29   R      RSVD                        0
+    */
+    union
+    {
+        __IO uint32_t REG_OTHER_BIST_DONE;
+        struct
+        {
+            __I uint32_t bist_done_btmac: 4;
+            __I uint32_t RESERVED_3: 12;
+            __I uint32_t bist_done_btphy: 1;
+            __I uint32_t RESERVED_2: 4;
+            __I uint32_t bist_done_zigbee: 3;
+            __I uint32_t RESERVED_1: 4;
+            __I uint32_t bist_done_audio: 1;
+            __I uint32_t RESERVED_0: 3;
+        } BITS_0F4;
+    } u_0F4;
+
+    /* 0x00F8       0x4000_60f8
+        3:0     R      bist_fail_btmac             0
+        15:4    R      RSVD                        0
+        20:16   R      bist_fail_btphy             0
+        27:21   R      bist_fail_zigbee            0
+        28      R      bist_fail_audio             0
+        31:29   R      RSVD                        0
+    */
+    union
+    {
+        __IO uint32_t REG_OTHER_BIST_FAIL;
+        struct
+        {
+            __I uint32_t bist_fail_btmac: 4;
+            __I uint32_t RESERVED_1: 12;
+            __I uint32_t bist_fail_btphy: 5;
+            __I uint32_t bist_fail_zigbee: 7;
+            __I uint32_t bist_fail_audio: 1;
+            __I uint32_t RESERVED_0: 3;
+        } BITS_0F8;
+    } u_0F8;
+
+    /* 0x00FC       0x4000_60fc
+        3:0     R      drf_bist_done_btmac         0
+        15:4    R      RSVD                        0
+        16      R      drf_bist_done_btphy         0
+        20:17   R      RSVD                        0
+        23:21   R      drf_bist_done_zigbee        0
+        27:24   R      RSVD                        0
+        28      R      drf_bist_done_audio         0
+        31:29   R      RSVD                        0
+    */
+    union
+    {
+        __IO uint32_t REG_OTHER_DRF_BIST_DONE;
+        struct
+        {
+            __I uint32_t drf_bist_done_btmac: 4;
+            __I uint32_t RESERVED_3: 12;
+            __I uint32_t drf_bist_done_btphy: 1;
+            __I uint32_t RESERVED_2: 4;
+            __I uint32_t drf_bist_done_zigbee: 3;
+            __I uint32_t RESERVED_1: 4;
+            __I uint32_t drf_bist_done_audio: 1;
+            __I uint32_t RESERVED_0: 3;
+        } BITS_0FC;
+    } u_0FC;
+
+    /* 0x0100       0x4000_6100
+        3:0     R      drf_bist_fail_btmac         0
+        15:4    R      RSVD                        0
+        20:16   R      drf_bist_fail_btphy         0
+        27:21   R      drf_bist_fail_zigbee        0
+        28      R      drf_bist_fail_audio         0
+        31:29   R      RSVD                        0
+    */
+    union
+    {
+        __IO uint32_t REG_OTHER_DRF_BIST_FAIL;
+        struct
+        {
+            __I uint32_t drf_bist_fail_btmac: 4;
+            __I uint32_t RESERVED_1: 12;
+            __I uint32_t drf_bist_fail_btphy: 5;
+            __I uint32_t drf_bist_fail_zigbee: 7;
+            __I uint32_t drf_bist_fail_audio: 1;
+            __I uint32_t RESERVED_0: 3;
+        } BITS_100;
+    } u_100;
+
+    __IO uint32_t RSVD_0x104[11];
+
+    /* 0x0130       0x4000_6130
+        31:0    R      RSVD                        32'h0
+    */
+    __IO uint32_t Reserved_7;
+
+    /* 0x0134       0x4000_6134
+        31:0    R      RSVD                        32'h0
+    */
+    __IO uint32_t Reserved_8;
+
+    __IO uint32_t RSVD_0x138[50];
+
+    /* 0x0200       0x4000_6200
+        0       R/W    rng_srst                    0
+        1       R/W    clk_hf_sel                  0
+        2       R/W    corrector_bypass            0
+        3       R/W    cali_srst                   0
+        4       R      RSVD                        0
+        5       R/W    corrector_imode             0
+        10:6    R/W    dbg0_sel                    0
+        15:11   R/W    dbg1_sel                    1
+        16      R/W    lfsr_bypass_1               1
+        17      R/W    lfsr_mode                   0
+        18      R/W    st_en                       0
+        19      R/W    mode                        0
+        31:20   R      RSVD                        12'h0
+    */
+    union
+    {
+        __IO uint32_t RNG_Control_Register;
+        struct
+        {
+            __IO uint32_t rng_srst: 1;
+            __IO uint32_t clk_hf_sel: 1;
+            __IO uint32_t corrector_bypass: 1;
+            __IO uint32_t cali_srst: 1;
+            __I uint32_t RESERVED_1: 1;
+            __IO uint32_t corrector_imode: 1;
+            __IO uint32_t dbg0_sel: 5;
+            __IO uint32_t dbg1_sel: 5;
+            __IO uint32_t lfsr_bypass_1: 1;
+            __IO uint32_t lfsr_mode: 1;
+            __IO uint32_t st_en: 1;
+            __IO uint32_t mode: 1;
+            __I uint32_t RESERVED_0: 12;
+        } BITS_200;
+    } u_200;
+
+    /* 0x0204       0x4000_6204
+        1:0     R/W    DUMMY                       2'b0
+        3:2     R      RSVD                        2'b0
+        15:4    R/W    DUMMY                       12'h889
+        31:16   R      RSVD                        16'h0
+    */
+    union
+    {
+        __IO uint32_t Reserved_9;
+        struct
+        {
+            __IO uint32_t RESERVED_3: 2;
+            __I uint32_t RESERVED_2: 2;
+            __IO uint32_t RESERVED_1: 12;
+            __I uint32_t RESERVED_0: 16;
+        } BITS_204;
+    } u_204;
+
+    /* 0x0208       0x4000_6208
+        31:0    R/W    DUMMY                       32'h28001a00
+    */
+    __IO uint32_t Reserved_10;
+
+    /* 0x020C       0x4000_620c
+        8:0     R/W    DUMMY                       9'h101
+        11:9    R      RSVD                        3'h0
+        31:12   R/W    DUMMY                       20'h10d0
+    */
+    union
+    {
+        __IO uint32_t Reserved_11;
+        struct
+        {
+            __IO uint32_t RESERVED_2: 9;
+            __I uint32_t RESERVED_1: 3;
+            __IO uint32_t RESERVED_0: 20;
+        } BITS_20C;
+    } u_20C;
+
+    /* 0x0210       0x4000_6210
+        31:0    R      RSVD                        32'h00020000
+    */
+    __IO uint32_t Reserved_12;
+
+    /* 0x0214       0x4000_6214
+        31:0    R/W    DUMMY                       32'h2b001800
+    */
+    __IO uint32_t Reserved_13;
+
+    /* 0x0218       0x4000_6218
+        3:0     R/W    DUMMY                       4'h8
+        15:4    R/W    RSVD                        12'h0
+        19:16   R/W    DUMMY                       4'h4
+        31:20   R/W    RSVD                        12'h0
+    */
+    union
+    {
+        __IO uint32_t Reserved_14;
+        struct
+        {
+            __IO uint32_t RESERVED_3: 4;
+            __IO uint32_t RESERVED_2: 12;
+            __IO uint32_t RESERVED_1: 4;
+            __IO uint32_t RESERVED_0: 12;
+        } BITS_218;
+    } u_218;
+
+    /* 0x021C       0x4000_621c
+        0       R      out_ready                   0
+        1       R      init_ready                  0
+        31:2    R      RSVD                        30'h0
+    */
+    union
+    {
+        __IO uint32_t RNG_return0;
+        struct
+        {
+            __I uint32_t out_ready: 1;
+            __I uint32_t init_ready: 1;
+            __I uint32_t RESERVED_0: 30;
+        } BITS_21C;
+    } u_21C;
+
+    /* 0x0220       0x4000_6220
+        31:0    R      valid_bit_num               0
+    */
+    union
+    {
+        __IO uint32_t RNG_return1;
+        struct
+        {
+            __I uint32_t valid_bit_num: 32;
+        } BITS_220;
+    } u_220;
+
+    /* 0x0224       0x4000_6224
+        31:0    R      drop_num                    0
+    */
+    union
+    {
+        __IO uint32_t RNG_return2;
+        struct
+        {
+            __I uint32_t drop_num: 32;
+        } BITS_224;
+    } u_224;
+
+    /* 0x0228       0x4000_6228
+        31:0    R      random_out                  0
+    */
+    union
+    {
+        __IO uint32_t RNG_result;
+        struct
+        {
+            __I uint32_t random_out: 32;
+        } BITS_228;
+    } u_228;
+
+    /* 0x022C       0x4000_622c
+        31:0    R/W    lfsr_poly_lsb               0
+    */
+    union
+    {
+        __IO uint32_t RNG_lfsr_poly_lsb;
+        struct
+        {
+            __IO uint32_t lfsr_poly_lsb: 32;
+        } BITS_22C;
+    } u_22C;
+
+    /* 0x0230       0x4000_6230
+        31:0    R/W    lfsr_poly_msb               0
+    */
+    union
+    {
+        __IO uint32_t RNG_lfsr_poly_msb;
+        struct
+        {
+            __IO uint32_t lfsr_poly_msb: 32;
+        } BITS_230;
+    } u_230;
+
+    /* 0x0234       0x4000_6234
+        31:0    R/W    DUMMY                       32'hffff0000
+    */
+    __IO uint32_t Reserved_15;
+
+    /* 0x0238       0x4000_6238
+        0       R/W    gating_en                   1
+        31:1    R      RSVD                        0
+    */
+    union
+    {
+        __IO uint32_t RNG_POWER;
+        struct
+        {
+            __IO uint32_t gating_en: 1;
+            __I uint32_t RESERVED_0: 31;
+        } BITS_238;
+    } u_238;
+
+    /* 0x023C       0x4000_623c
+        7:0     R/W    thr_done_rep                8'h0
+        15:8    R/W    thr_err_rep                 8'h5
+        17:16   R/W    window_size_adap2           2'b1
+        19:18   R/W    window_size_adap1           2'b1
+        20      R/W    compare_unit_adap2          0
+        21      R/W    compare_unit_adap1          0
+        22      R/W    compare_unit_rep            1
+        23      R      RSVD                        0
+        27:24   R/W    thr_done_adap2              4'h4
+        31:28   R/W    thr_done_adap1              4'h4
+    */
+    union
+    {
+        __IO uint32_t RNG_st;
+        struct
+        {
+            __IO uint32_t thr_done_rep: 8;
+            __IO uint32_t thr_err_rep: 8;
+            __IO uint32_t window_size_adap2: 2;
+            __IO uint32_t window_size_adap1: 2;
+            __IO uint32_t compare_unit_adap2: 1;
+            __IO uint32_t compare_unit_adap1: 1;
+            __IO uint32_t compare_unit_rep: 1;
+            __I uint32_t RESERVED_0: 1;
+            __IO uint32_t thr_done_adap2: 4;
+            __IO uint32_t thr_done_adap1: 4;
+        } BITS_23C;
+    } u_23C;
+
+    /* 0x0240       0x4000_6240
+        0       R/W    err_adap2                   0
+        1       R/W    err_adap1                   0
+        2       R/W    err_rep                     0
+        3       R/W    err                         0
+        4       R      done_adap2                  0
+        5       R      done_adap1                  0
+        6       R      done_rep                    0
+        7       R      done                        0
+        31:8    R      RSVD                        24'h0
+    */
+    union
+    {
+        __IO uint32_t RNG_st_return;
+        struct
+        {
+            __IO uint32_t err_adap2: 1;
+            __IO uint32_t err_adap1: 1;
+            __IO uint32_t err_rep: 1;
+            __IO uint32_t err: 1;
+            __I uint32_t done_adap2: 1;
+            __I uint32_t done_adap1: 1;
+            __I uint32_t done_rep: 1;
+            __I uint32_t done: 1;
+            __I uint32_t RESERVED_0: 24;
+        } BITS_240;
+    } u_240;
+
+    /* 0x0244       0x4000_6244
+        31:0    R      RSVD                        32'h0
+    */
+    __IO uint32_t Reserved_16;
+
+    /* 0x0248       0x4000_6248
+        31:0    R      RSVD                        32'h0
+    */
+    __IO uint32_t Reserved_17;
+
+    /* 0x024C       0x4000_624c
+        31:0    R      RSVD                        32'h0
+    */
+    __IO uint32_t Reserved_18;
+
+    /* 0x0250       0x4000_6250
+        31:0    R      RSVD                        32'h0
+    */
+    __IO uint32_t Reserved_19;
+
+    /* 0x0254       0x4000_6254
+        0       W      write_data                  nan
+        1       R/W1S  otp                         0
+        2       R/W1S  parity                      0
+        3       R/W1S  st_err                      0
+        31:4    R      RSVD                        28'h0
+    */
+    union
+    {
+        __IO uint32_t RNG_interrupt;
+        struct
+        {
+            __O uint32_t write_data: 1;
+            __IO uint32_t otp: 1;
+            __IO uint32_t parity: 1;
+            __IO uint32_t st_err: 1;
+            __I uint32_t RESERVED_0: 28;
+        } BITS_254;
+    } u_254;
+
+    /* 0x0258       0x4000_6258
+        31:0    R      RSVD                        32'h0
+    */
+    __IO uint32_t Reserved_20;
+
+    /* 0x025C       0x4000_625c
+        31:0    R      RSVD                        32'h0
+    */
+    __IO uint32_t Reserved_21;
+
+    /* 0x0260       0x4000_6260
+        15:0    R/W    adap2                       16'h270
+        31:16   R/W    adap1                       16'h270
+    */
+    union
+    {
+        __IO uint32_t RNG_st_thr_err;
+        struct
+        {
+            __IO uint32_t adap2: 16;
+            __IO uint32_t adap1: 16;
+        } BITS_260;
+    } u_260;
+
+    /* 0x0264       0x4000_6264
+        0       W      write_data                  nan
+        1       R/W    otp                         0
+        2       R/W    parity                      0
+        3       R/W    st_err                      0
+        31:4    R      RSVD                        28'h0
+    */
+    union
+    {
+        __IO uint32_t RNG_interrupt_enable;
+        struct
+        {
+            __O uint32_t write_data: 1;
+            __IO uint32_t otp: 1;
+            __IO uint32_t parity: 1;
+            __IO uint32_t st_err: 1;
+            __I uint32_t RESERVED_0: 28;
+        } BITS_264;
+    } u_264;
+
+    __IO uint32_t RSVD_0x268[25];
+
+    /* 0x02cc       0x4000_62cc
+        31:0    R/W    spic0_pgm_fifo_init_0       32'h0
+    */
+    union
+    {
+        __IO uint32_t SPIC0_PGM_fifo_interrtup_0;
+        struct
+        {
+            __IO uint32_t spic0_pgm_fifo_init_0: 32;
+        } BITS_2cc;
+    } u_2cc;
+
+    /* 0x02d0       0x4000_62d0
+        31:0    R/W    spic0_pgm_fifo_init_1       32'h0
+    */
+    union
+    {
+        __IO uint32_t SPIC0_PGM_fifo_interrtup_1;
+        struct
+        {
+            __IO uint32_t spic0_pgm_fifo_init_1: 32;
+        } BITS_2d0;
+    } u_2d0;
+
+    /* 0x02d4       0x4000_62d4
+        31:0    R/W    spic0_pgm_fifo_init_2       32'h0
+    */
+    union
+    {
+        __IO uint32_t SPIC0_PGM_fifo_interrtup_2;
+        struct
+        {
+            __IO uint32_t spic0_pgm_fifo_init_2: 32;
+        } BITS_2d4;
+    } u_2d4;
+
+    /* 0x02d8       0x4000_62d8
+        31:0    R/W    spic0_pgm_fifo_init_3       32'h0
+    */
+    union
+    {
+        __IO uint32_t SPIC0_PGM_fifo_interrtup_3;
+        struct
+        {
+            __IO uint32_t spic0_pgm_fifo_init_3: 32;
+        } BITS_2d8;
+    } u_2d8;
+
+    /* 0x02dc       0x4000_62dc
+        31:0    R/W    spic0_pgm_fifo_init_4       32'h0
+    */
+    union
+    {
+        __IO uint32_t SPIC0_PGM_fifo_interrtup_4;
+        struct
+        {
+            __IO uint32_t spic0_pgm_fifo_init_4: 32;
+        } BITS_2dc;
+    } u_2dc;
+
+    /* 0x02e0       0x4000_62e0
+        31:0    R/W    spic0_pgm_fifo_init_5       32'h0
+    */
+    union
+    {
+        __IO uint32_t SPIC0_PGM_fifo_interrtup_5;
+        struct
+        {
+            __IO uint32_t spic0_pgm_fifo_init_5: 32;
+        } BITS_2e0;
+    } u_2e0;
+
+    /* 0x02e4       0x4000_62e4
+        31:0    R/W    spic0_pgm_fifo_init_6       32'h0
+    */
+    union
+    {
+        __IO uint32_t SPIC0_PGM_fifo_interrtup_6;
+        struct
+        {
+            __IO uint32_t spic0_pgm_fifo_init_6: 32;
+        } BITS_2e4;
+    } u_2e4;
+
+    /* 0x02e8       0x4000_62e8
+        31:0    R/W    spic0_pgm_fifo_init_7       32'h0
+    */
+    union
+    {
+        __IO uint32_t SPIC0_PGM_fifo_interrtup_7;
+        struct
+        {
+            __IO uint32_t spic0_pgm_fifo_init_7: 32;
+        } BITS_2e8;
+    } u_2e8;
+
+} SoC_VENDOR_REG_TypeDef;
+
+/* ================================================================================ */
+/* ================                    Security                    ================ */
+/* ================================================================================ */
+
+/**
+  * @brief Security. (Security)
+  */
+
+typedef union                                               /*!< Security Structure */
+{
+    __IO uint32_t d32;
+    struct
+    {
+        __IO uint32_t reg_pon_debug_port_wp: 1;
+        __IO uint32_t reg_pon_debug_port: 1;
+        __IO uint32_t reg_pon_hwspi_en_wp: 1;
+        __IO uint32_t reg_pon_hwspi_en: 1;
+        __IO uint32_t is_efuse_invalid: 1;
+        __IO uint32_t reg_efuse_system_general_ctrl_lock: 1;
+        __IO uint32_t rsvd0: 2;
+        __IO uint32_t is_enable_efuse_read_protect: 1;
+        __IO uint32_t is_enable_efuse_write_protect: 1;
+        __IO uint32_t is_disable_hci_ram_patch: 1;
+        __IO uint32_t is_disable_hci_flash_access: 1;
+        __IO uint32_t is_disable_hci_system_access: 1;
+        __IO uint32_t is_disable_hci_efuse_access: 1;
+        __IO uint32_t is_disable_hci_bt_test: 1;
+        __IO uint32_t is_debug_password_invalid: 1;
+        __IO uint32_t rsvd1: 4;
+        __IO uint32_t reg_pon_clk_flash_dis: 1;
+        __IO uint32_t rsvd2: 11;
+    };
+} SECURITY_TypeDef;
+
+/* ================================================================================ */
+/* ================                 Peri clock reg                 ================ */
+/* ================================================================================ */
+
+/**
+  * @brief PWM
+  */
+typedef struct
+{
+    __IO uint32_t CLKSELE;                    /*!< 0x348*/
+    uint32_t RSVD[4];
+    __IO uint32_t CLK_SRCL;
+    __IO uint32_t CLK_SRCH;                     /*!< 0x360*/
+    __IO uint32_t PWM0_CTRL_L;
+    __IO uint32_t PWM0_CTRL_H;
+    __IO uint32_t PWM1_CTRL_L;
+    __IO uint32_t PWM1_CTRL_H;                 /*!< 0x370*/
+    __IO uint32_t PWM2_CTRL_L;
+    __IO uint32_t PWM2_CTRL_H;
+    __IO uint32_t PWM3_CTRL_L;
+    __IO uint32_t PWM3_CTRL_H;                /*!< 0x380*/
+    __IO uint32_t TIM_EVT_CTRL;
+
+} Peri_ClockGate_TypeDef;
+
+
+/* ================================================================================ */
+/* ================                      CACHE                     ================ */
+/* ================================================================================ */
+
+/**
+  * @brief cache for flash
+  */
+typedef struct
+{
+    __IO uint32_t CACHE_ENABLE;      /*!< SPIC cache Enable Register, Address Offset: 0x00*/
+    __IO uint32_t FLUSH;             /*!< Cache Flush register, Address Offset: 0x04*/
+    __IO uint32_t INTR;              /*!< Cache Interrupt register, Address Offset: 0x08*/
+    __O  uint32_t RST_CNT;           /*!< Cache Reset Counter register, Address Offset: 0x0C*/
+    __I  uint32_t RD_EVT_CNT;        /*!< Cache Read Event Counter register, Address Offset: 0x10*/
+    __I  uint32_t HIT_EVT_CNT;       /*!< Cache HIT Event Counter register, Address Offset: 0x14*/
+    __I  uint32_t HIT_LSTW_EVT_CNT;  /*!< Cache Hit lastway event counter register, Offset: 0x18*/
+    __I  uint32_t RD_PND_CNT;        /*!< Cache Read pending counter register, Offset: 0x1c*/
+    __I  uint32_t RSVD0[4];          /*!< Reserved, Offset: 0x20 ~ 0x2C */
+    __IO uint32_t HITWAYBUF_CTRL;    /*!< Cache Hit way buffer control register, Offset: 0x30 */
+    __IO uint32_t CACHE_RAM_CTRL;    /*!< Cache Two way function control register, Offset: 0x34 */
+    __IO uint32_t COUNTER_ENABLE;    /*!< Cache counter enable register, Offset: 0x38 */
+} CACHE_TypeDef;
+
+/* ================================================================================ */
+/* ================                      SPIC                      ================ */
+/* ================================================================================ */
+#if 0
+typedef struct
+{
+    __IO uint32_t CTRLR0;             /*!< SPIC control register0, Address offset: 0x000 */
+    __IO uint32_t
+    RX_NDF;             /*!< SPIC receiving data frame number register, Address offset: 0x004 */
+    __IO uint32_t SSIENR;             /*!< SPIC enable register, Address offset: 0x008 */
+    __IO uint32_t mwcr;               /*!< N/A, Address offset: 0x00C */
+    __IO uint32_t SER;                /*!< SPIC slave enable register, Address offset: 0x010 */
+    __IO uint32_t BAUDR;              /*!< SPIC baudrate select register, Address offset: 0x014 */
+    __IO uint32_t txftlr;             /*!< SPIC transmit FIFO threshold level,  Address offset: 0x018 */
+    __IO uint32_t rxftlr;             /*!< SPIC receive FIFO threshold level, Address offset: 0x01C */
+    __IO uint32_t txflr;              /*!< SPIC transmit FIFO level register, Address offset: 0x020 */
+    __IO uint32_t rxflr;              /*!< SPIC receive FIFO level register,  Address offset: 0x024 */
+    __IO uint32_t sr;                 /*!< SPIC status register, Address offset: 0x028 */
+    __IO uint32_t imr;                /*!< SPIC interrupt mask register, Address offset: 0x02C */
+    __IO uint32_t isr;                /*!< SPIC interrupt status register, Address offset: 0x030 */
+    __IO uint32_t risr;               /*!< SPIC raw interrupt status register, Address offset: 0x034 */
+    __IO uint32_t
+    txoicr;             /*!< SPIC transmit FIFO overflow interrupt clear register,offset: 0x038 */
+    __IO uint32_t
+    rxoicr;             /*!< SPIC receive FIFO overflow interrupt clear register, offset: 0x03C */
+    __IO uint32_t
+    rxuicr;             /*!< SPIC receive FIFO underflow interrupt clear register,offset: 0x040 */
+    __IO uint32_t
+    msticr;             /*!< SPIC master error interrupt clear register,   Address offset: 0x044 */
+    __IO uint32_t icr;                /*!< SPIC interrupt clear register, Address offset: 0x048 */
+    __IO uint32_t dmacr;              /*!< N/A, Address offset: 0x04C */
+    __IO uint32_t dmatdlr;            /*!< N/A, Address offset: 0x050 */
+    __IO uint32_t dmardlr;            /*!< N/A, Address offset: 0x054 */
+    __IO uint32_t idr;                /*!< SPIC Identiation register,  Address offset: 0x058 */
+    __IO uint32_t spi_flash_version;  /*!< SPIC version ID register, Address offset: 0x05C */
+    union
+    {
+        __IO uint8_t  byte;
+        __IO uint16_t half;
+        __IO uint32_t word;
+    } DR[32];                         /*!< SPIC data register, Address offset: 0x060~0x09C */
+    __IO uint32_t rd_fast_single;     /*!< Fast read data command of SPI Flash, offset: 0x0E0 */
+    __IO uint32_t rd_dual_o;          /*!< Dual output read command of SPI Flash, offset: 0x0E4 */
+    __IO uint32_t rd_dual_io;         /*!< Dual I/O read command of SPI Flash, offset: 0x0E8 */
+    __IO uint32_t rd_quad_o;          /*!< Quad output read command of SPI Flash, offset: 0x0EC */
+    __IO uint32_t rd_quad_io;         /*!< Quad I/O read command of SPI Flash, offset: 0x0F0 */
+    __IO uint32_t wr_single;          /*!< Page program command of SPI Flash,  offset: 0x0F4 */
+    __IO uint32_t
+    wr_dual_i;          /*!< Dual data input program command of SPI Flash, offset: 0x0F8 */
+    __IO uint32_t
+    wr_dual_ii;         /*!< Dual address&data program command of SPI Flash,offset: 0x0FC */
+    __IO uint32_t wr_quad_i;          /*!< Quad data input program command of SPI Flash,offset: 0x100 */
+    __IO uint32_t
+    wr_quad_ii;         /*!< Quad address&data program command of SPI Flash,offset: 0x104 */
+    __IO uint32_t wr_enable;          /*!< Write enabe command of SPI Flash, Address offset: 0x108 */
+    __IO uint32_t rd_status;          /*!< Read status command of SPI Flash, offset: 0x10C */
+    __IO uint32_t CTRLR2;             /*!< SPIC control register2, Address offset: 0x110 */
+    __IO uint32_t fbaudr;             /*!< SPIC fast baudrate select, Address offset: 0x114 */
+    __IO uint32_t USER_LENGTH;        /*!< SPIC address length register, Address offset: 0x118 */
+    __IO uint32_t AUTO_LENGTH;        /*!< SPIC auto address length register, Address offset: 0x11C */
+    __IO uint32_t VALID_CMD;          /*!< SPIC valid command register, Address offset: 0x120 */
+    __IO uint32_t flash_size;         /*!< SPIC flash size register, Address offset: 0x124 */
+    __IO uint32_t flush_fifo;         /*!< SPIC flush FIFO register, Address offset: 0x128 */
+    __IO uint32_t dum_byte;           /*!< SPIC dummy byte register, Address offset: 0x12c */
+    __IO uint32_t
+    tx_ndf;             /*!< SPIC transmitting data frame number register, Address offset: 0x130 */
+    __IO uint32_t device_info;        /*!< SPIC device info register, Address offset: 0x134 */
+    __IO uint32_t tpr0;               /*!< SPIC timing parameter register, Address offset: 0x138 */
+    __IO uint32_t auto_length2;       /*!< SPIC auto length 2 register, Address offset: 0x13c */
+} SPIC_TypeDef;
+#else
+typedef struct
+{
+    __IO uint32_t CTRLR0;               /*!< Control reg 0,                         offset: 0x000 */
+    __IO uint32_t RX_NDF;               /*!< User mode rx data data frame counter,  offset: 0x004 */
+    __IO uint32_t SSIENR;               /*!< Enable reg,                            offset: 0x008 */
+    __IO uint32_t MWCR;                 /*!< N/A,                                   offset: 0x00C */
+    __IO uint32_t SER;                  /*!< Slave enable reg,                      offset: 0x010 */
+    __IO uint32_t BAUDR;                /*!< Baudrate select reg,                   offset: 0x014 */
+    __IO uint32_t TXFTLR;               /*!< Tx FIFO threshold level,               offset: 0x018 */
+    __IO uint32_t RXFTLR;               /*!< Rx FIFO threshold level,               offset: 0x01C */
+    __IO uint32_t TXFLR;                /*!< Tx FIFO level reg,                     offset: 0x020 */
+    __IO uint32_t RXFLR;                /*!< Rx FIFO level reg,                     offset: 0x024 */
+    __IO uint32_t SR;                   /*!< Status reg,                            offset: 0x028 */
+    __IO uint32_t IMR;                  /*!< Interrupt mask reg,                    offset: 0x02C */
+    __IO uint32_t ISR;                  /*!< Interrupt status reg,                  offset: 0x030 */
+    __IO uint32_t RISR;                 /*!< Raw interrupt status reg,              offset: 0x034 */
+    __IO uint32_t TXOICR;               /*!< Tx FIFO overflow interrupt clear reg,  offset: 0x038 */
+    __IO uint32_t RXOICR;               /*!< Rx FIFO overflow interrupt clear reg,  offset: 0x03C */
+    __IO uint32_t RXUICR;               /*!< Rx FIFO underflow interrupt clear reg, offset: 0x040 */
+    __IO uint32_t MSTICR;               /*!< Master error interrupt clear reg,      offset: 0x044 */
+    __IO uint32_t ICR;                  /*!< Interrupt clear reg,                   offset: 0x048 */
+    __IO uint32_t DMACR;                /*!< DMA control reg,                       offset: 0x04C */
+    __IO uint32_t DMATDLR;              /*!< DMA transimit data level reg,          offset: 0x050 */
+    __IO uint32_t DMARDLR;              /*!< DMA revceive data level reg,           offset: 0x054 */
+    __IO uint32_t IDR;                  /*!< Identiation reg,                       offset: 0x058 */
+    __IO uint32_t SPIC_VERSION;         /*!< Version ID reg,                        offset: 0x05C */
+    union
+    {
+        __IO uint8_t  BYTE;
+        __IO uint16_t HALF;
+        __IO uint32_t WORD;
+    } DR[16];                           /*!< Data reg,                              offset: 0x060 */
+    __IO uint32_t DM_DR[16];            /*!< Data mask data register,               offset: 0x0A0 */
+    __IO uint32_t READ_FAST_SINGLE;     /*!< Fast read data cmd of flash,           offset: 0x0E0 */
+    __IO uint32_t READ_DUAL_DATA;       /*!< Dual output read cmd of flash,         offset: 0x0E4 */
+    __IO uint32_t READ_DUAL_ADDR_DATA;  /*!< Dual I/O read cmd of flash,            offset: 0x0E8 */
+    __IO uint32_t READ_QUAD_DATA;       /*!< Quad output read cmd of flash,         offset: 0x0EC */
+    __IO uint32_t READ_QUAD_ADDR_DATA;  /*!< Quad I/O read cmd of flash,            offset: 0x0F0 */
+    __IO uint32_t WRITE_SINGLE;         /*!< Page program cmd of flash,             offset: 0x0F4 */
+    __IO uint32_t WRITE_DUAL_DATA;      /*!< Dual data input program cmd of flash,  offset: 0x0F8 */
+    __IO uint32_t WRITE_DUAL_ADDR_DATA; /*!< Dual addr & data program cmd of flash, offset: 0x0FC */
+    __IO uint32_t WRITE_QUAD_DATA;      /*!< Quad data input program cmd of flash,  offset: 0x100 */
+    __IO uint32_t WRITE_QUAD_ADDR_DATA; /*!< Quad addr & data program cmd of flash, offset: 0x104 */
+    __IO uint32_t WRITE_ENABLE;         /*!< Write enabe cmd of flash,              offset: 0x108 */
+    __IO uint32_t READ_STATUS;          /*!< Read status cmd of flash,              offset: 0x10C */
+    __IO uint32_t CTRLR2;               /*!< Control reg 2,                         offset: 0x110 */
+    __IO uint32_t FBAUDR;               /*!< Fast baudrate select,                  offset: 0x114 */
+    __IO uint32_t USER_LENGTH;          /*!< Addr length reg,                       offset: 0x118 */
+    __IO uint32_t AUTO_LENGTH;          /*!< Auto addr length reg,                  offset: 0x11C */
+    __IO uint32_t VALID_CMD;            /*!< Valid cmd reg,                         offset: 0x120 */
+    __IO uint32_t FLASH_SIZE;           /*!< Flash size reg,                        offset: 0x124 */
+    __IO uint32_t FLUSH_FIFO;           /*!< Flush FIFO reg,                        offset: 0x128 */
+    __IO uint32_t DUM_BYTE;             /*!< Dummy byte value,                      offset: 0x12C */
+    __IO uint32_t TX_NDF;               /*!< Tx NDF,                                offset: 0x130 */
+    __IO uint32_t DEVICE_INFO;          /*!< Device info,                           offset: 0x134 */
+    __IO uint32_t TPR0;                 /*!< Timing parameters,                     offset: 0x138 */
+    __IO uint32_t AUTO_LENGTH2;         /*!< Auto addr length reg 2,                offset: 0x13C */
+    __IO uint32_t TPR1;                 /*!< Timing parameters 2,                   offset: 0x140 */
+    __IO uint32_t RESERVED_1[15];       /*!< Reserved,                              offset: 0x144 */
+    __IO uint32_t ST_DR[16];            /*!< ST FIFO data buffer,                   offset: 0x180 */
+    __IO uint32_t STFLR;                /*!< Number of valid data in status data,   offset: 0x1C0 */
+    __IO uint32_t RESERVED_2[3];        /*!< Reserved,                              offset: 0x1C4 */
+    __IO uint32_t PAGE_READ;            /*!< Page read command in auto mode,        offset: 0x1D0 */
+} SPIC_TypeDef;
+#endif
+/** @} */ /* End of group RTL876X_Peripheral_Registers_Structures */
+
+/*============================================================================*
+ *                              Macros
+ *============================================================================*/
+
+/** @defgroup RTL876X_Exported_Macros CMSIS-RTL876X Exported Macros
+    * @brief
+    * @{
+    */
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+/* ================================================================================ */
+/* ================              Peripheral memory map             ================ */
+/* ================================================================================ */
+//#define SYSTEM_REG_BASE             0x40000000UL
+//#define PERIPH_REG_BASE             0x40000000UL
+//#define RTC_REG_BASE                0x40000140UL
+//#define RTC_LP_REG_BASE             0x40000180UL
+//#define LPC_REG_BASE                0x40000180UL
+//#define AON_WDG_REG_BASE            0x40000190UL
+//#define SYSBLKCTRL_REG_BASE         0x40000200UL
+//#define PINMUX_REG_BASE             0x40000280UL
+//#define SPIC_DLY_CTRL_BASE          0x40000300UL
+//#define PERICLKGAT_REG_BASE         0x40000348UL
+//#define PWM2_REG_BASE               0x40000364UL
+//#define PWM3_REG_BASE               0x40000368UL
+//#define RTC_LED_REG_BASE            0x40000400UL
+
+//#define GPIO_REG_BASE               0x40001000UL
+//#define TIM0_REG_BASE               0x40002000UL
+//#define TIM1_REG_BASE               0x40002014UL
+//#define TIM2_REG_BASE               0x40002028UL
+//#define TIM3_REG_BASE               0x4000203CUL
+//#define TIM4_REG_BASE               0x40002050UL
+//#define TIM5_REG_BASE               0x40002064UL
+//#define TIM6_REG_BASE               0x40002078UL
+//#define TIM7_REG_BASE               0x4000208CUL
+//#define QDEC_REG_BASE               0x40004000UL
+//#define SPI2WIRE_REG_BASE           0x40004000UL
+//#define KEYSCAN_REG_BASE            0x40005000UL
+//#define VENDOR_REG_BASE             0x40006000UL
+//#define WDG_REG_BASE                0x40006000UL
+//#define PERI_INT_REG_BASE           0x40006004UL
+//#define RANDOM_GEN_REG_BASE         0x40006150UL
+//#define CACHE_REG_BASE              0x40007000UL
+//#define ENHANCED_TIM_BASE           0x40008000UL
+//#define ENHTIM0_REG_BASE          0x40008000UL
+//#define ENHTIM1_REG_BASE          0x40008024UL
+//#define ENHTIM2_REG_BASE          0x40008048UL
+//#define ENHTIM3_REG_BASE          0x4000806CUL
+//#define ENHTIM4_REG_BASE          0x40008090UL
+//#define ENHTIM5_REG_BASE          0x400080B4UL
+//#define ENHTIM6_REG_BASE          0x400080D8UL
+//#define ENHTIM7_REG_BASE          0x400080FCUL
+//#define ENHTIM_SHARE_REG_BASE     0x40008128UL
+//#define CAP_TOUCH_BASE              0x40009000UL
+//#define ADC_REG_BASE                0x40010000UL
+//#define UART1_REG_BASE              0x40011000UL  //log
+//#define UART0_REG_BASE              0x40012000UL  //data
+//#define SPI0_REG_BASE               0x40013000UL
+//#define SPI1_REG_BASE               0x40013400UL
+//#define HW_AES_REG_BASE             0x40014000UL
+//#define I2C0_REG_BASE               0x40015000UL
+//#define I2C1_REG_BASE               0x40015400UL
+//#define IR_REG_BASE                 0x40016000UL
+//#define SPORT0_REG_BASE             0x40020000UL
+//#define I2S0_REG_BASE               0x40020000UL
+//#define SPORT1_REG_BASE             0x40021000UL
+//#define I2S1_REG_BASE               0x40021000UL
+//#define SPDIF_REG_BASE              0x40021800UL
+//#define CODEC_ANA_REG_BASE          0x40022000UL
+//#define CODEC_EQ1_REG_BASE          0x40022040UL
+//#define CODEC_EQ2_REG_BASE          0x40022054UL
+//#define CODEC_EQ3_REG_BASE          0x40022068UL
+//#define CODEC_EQ4_REG_BASE          0x4002207CUL
+//#define CODEC_EQ5_REG_BASE          0x40022090UL
+//#define CODEC_REG_BASE              0x40022100UL
+//#define CODEC_CH0_CR_REG_BASE       0x40022200UL
+//#define CODEC_CH0_EQ1_REG_BASE      0x40022204UL
+//#define CODEC_CH0_EQ2_REG_BASE      0x40022218UL
+//#define CODEC_CH0_EQ3_REG_BASE      0x4002222CUL
+//#define CODEC_CH0_EQ4_REG_BASE      0x40022240UL
+//#define CODEC_CH0_EQ5_REG_BASE      0x40022254UL
+//#define CODEC_CH1_CR_REG_BASE       0x40022268UL
+//#define CODEC_CH1_EQ1_REG_BASE      0x40022280UL
+//#define CODEC_CH1_EQ2_REG_BASE      0x40022294UL
+//#define CODEC_CH1_EQ3_REG_BASE      0x400222A8UL
+//#define CODEC_CH1_EQ4_REG_BASE      0x400222BCUL
+//#define CODEC_CH1_EQ5_REG_BASE      0x400222D0UL
+//#define H2D_D2H_REG_BASE            0x40023000UL
+//#define UART2_REG_BASE              0x40024000UL
+//#define IF8080_REG_BASE             0x40024800UL
+//#define IF8080_LLI_REG1_BASE        0x40024850UL
+//#define IF8080_LLI_REG1_GDMA_BASE   0x400248A0UL
+//#define IF8080_LLI_REG2_BASE        0x40024880UL
+//#define IF8080_LLI_REG2_GDMA_BASE   0x400248C0UL
+//#define IF8080_LLI_REG1_OFT_BASE    0x40024870UL
+//#define IF8080_LLI_REG2_OFT_BASE    0x40024878UL
+//#define IF8080_LLI_CR_REG_BASE      0x40024894UL
+//#define GDMA_CHANNEL_REG_BASE       0x40027000UL // for platform_1_1_1_20160323 later
+//#define GDMA_Channel0_BASE          (GDMA_CHANNEL_REG_BASE + 0x0000)
+//#define GDMA_Channel1_BASE          (GDMA_CHANNEL_REG_BASE + 0x0058)
+//#define GDMA_Channel2_BASE          (GDMA_CHANNEL_REG_BASE + 0x00b0)
+//#define GDMA_Channel3_BASE          (GDMA_CHANNEL_REG_BASE + 0x0108)
+//#define GDMA_Channel4_BASE          (GDMA_CHANNEL_REG_BASE + 0x0160)
+//#define GDMA_Channel5_BASE          (GDMA_CHANNEL_REG_BASE + 0x01b8)
+//#define GDMA_REG_BASE               (GDMA_CHANNEL_REG_BASE + 0x02c0)
+//#define RTL_SPI0_BASE               0x40042000UL
+//#define RTL_SPI1_BASE               0x40042400UL
+//#define BT_BB_REG_BASE              0x40050000UL
+//#define HCI_DMA_REG_BASE            0x40064000UL
+//#define HCI_UART_REG_BASE           0x40068000UL
+//#define BT_VENDOR_REG_BASE          0x40058000UL
+//#define SECURITY_REG_BASE           0x40058f28UL
+//#define GDMA0_REG_BASE              0x40060000UL
+//#define SPIC0_REG_BASE              0x40080000UL
+//#define SPIC1_REG_BASE              0x40090000UL
+//#define SPIC2_REG_BASE              0x400A0000UL
+
+//#define SPI0_MASTER_MODE_REG *((volatile uint32_t *)0x40000308UL)
+//#define SPI0_MASTER_MODE_BIT BIT(8)
+
+///** @brief clock divider for peripheral */
+//#define SYSTEM_CLK_CTRL  *((volatile uint32_t *)0x4000020CUL)
+//#define CLK_SOURCE_REG_0 *((volatile uint32_t *)0x40000348UL)
+//#define CLK_SOURCE_REG_1 *((volatile uint32_t *)0x4000035CUL)
+//#define CLK_SOURCE_REG_2 *((volatile uint32_t *)0x40000360UL)
+
+//#define PERI_CLOCKGATE_REG_BASE     0x40000348UL
+
+//#define REG_PEON_SYS_CLK_SEL        0x0200
+//#define REG_PEON_SYS_CLK_SEL_2      0x0208
+//#define REG_PEON_SYS_CLK_SEL_3      0x020C
+//#define REG_SOC_FUNC_EN             0x0210
+//#define REG_SOC_HCI_COM_FUNC_EN     0x0214
+//#define REG_SOC_PERI_FUNC0_EN       0x0218
+//#define REG_SOC_PERI_FUNC1_EN       0x021C
+//#define REG_PESOC_CLK_CTRL          0x0230
+//#define REG_PESOC_PERI_CLK_CTRL0    0x0234
+//#define REG_PESOC_PERI_CLK_CTRL1    0x0238
+//#define REG_PESOC_DSP_SHARE_RAM     0x0250
+//#define REG_TEST_MODE               0x02a8
+//#define REG_ANAPAR_PLL1_0           0x0320
+//#define REG_ANAPAR_PLL3_2           0x0324
+//#define REG_ANAPAR_PLL5_4           0x0328
+//#define REG_XTAL_PLL_READY          0x0338
+
+//#define GPIO_OUTPUT_OFFSET          0x00
+//#define GPIO_DIRECTION_OFFSET       0x04
+
+///** @brief AON PAD AREA */
+//#define REG_PAD_WKEN_ADDRESS        0x20
+//#define REG_PAD_WK_CTRL_ADDRESS     0x12d
+//#define REG_PAD_WKPOL_ADDRESS       0x25
+//#define REG_PAD_O_ADDRESS           0x2A
+//#define REG_AON_PAD_E_ADDRESS       0x2F
+//#define REG_AON_PAD_S_ADDRESS       0x34
+//#define REG_AON_PAD_PU_ADDRESS      0x39
+//#define REG_AON_PAD_PD_ADDRESS      0x3E
+//#define REG_AON_PAD_PWRON_ADDRESS   0x4C
+
+//#define BIT_WK_INTEN                (1U << 7) /**< BIT7 */
+//#define BIT_WK_FLAG_GPIO            (1U << 6) /**< BIT6 */
+
+//#define BIT_SOC_ACTCK_GPIO_EN       (1U << 24) /**< BIT24 */
+//#define BIT_PERI_GPIO_EN            (1U << 8) /**< BIT8 */
+
+//#define BIT_PERI_KEYSCAN_EN         (1U << 19) /**< BIT19 */
+//#define BIT_SOC_ACTCK_KEYSCAN_EN    (1U << 6) /**< BIT6 */
+
+#define SYSTEM_REG_BASE             0x40000000UL
+#define PERIPH_REG_BASE             0x40000000UL
+#define RTC_REG_BASE                0x40000100UL
+#define RTC_LP_REG_BASE             0x40000180UL
+#define LPC_REG_BASE                0x40000180UL
+#define AON_WDG_REG_BASE            0x40000190UL
+#define SYSBLKCTRL_REG_BASE         0x40000200UL
+#define PINMUX_REG_BASE             0x40000280UL
+#define SPIC_DLY_CTRL_BASE          0x40000300UL
+#define PERICLKGAT_REG_BASE         0x40000348UL
+#define PWM2_REG_BASE               0x40000364UL
+#define PWM3_REG_BASE               0x40000368UL
+#define RTC_LED_REG_BASE            0x40000400UL
+
+#define GPIO_REG_BASE               0x40001000UL
+#define TIM0_REG_BASE               0x40002000UL
+#define TIM1_REG_BASE               0x40002014UL
+#define TIM2_REG_BASE               0x40002028UL
+#define TIM3_REG_BASE               0x4000203CUL
+#define TIM4_REG_BASE               0x40002050UL
+#define TIM5_REG_BASE               0x40002064UL
+#define TIM6_REG_BASE               0x40002078UL
+#define TIM7_REG_BASE               0x4000208CUL
+
+#define ENHANCED_TIM_BASE           0x40003000UL
+#define ENHTIM0_REG_BASE            0x40003000UL
+#define ENHTIM1_REG_BASE            0x40003024UL
+#define ENHTIM_SHARE_REG_BASE       0x40003120UL
+#define QDEC_REG_BASE               0x40004000UL
+#define SPI2WIRE_REG_BASE           0x40004000UL
+#define KEYSCAN_REG_BASE            0x40005000UL
+#define VENDOR_REG_BASE             0x40006000UL
+#define WDG_REG_BASE                0x40006000UL
+#define PERI_INT_REG_BASE           0x40006004UL
+#define RANDOM_GEN_REG_BASE         0x40006150UL
+#define CACHE_REG_BASE              0x40007000UL
+#define MODEMRFCPI_REG_BASE         0x40008000UL
+//#define CAP_TOUCH_BASE              0x40009000UL
+//#define CTC_Channel0_BASE           0x40009100UL
+//#define CTC_Channel1_BASE           0x40009110UL
+//#define CTC_Channel2_BASE           0x40009120UL
+//#define CTC_Channel3_BASE           0x40009130UL
+//#define CTC_Channel4_BASE           0x40009140UL
+//#define CTC_FAST_BASE               0x40009150UL
+#define ADC_REG_BASE                0x40010000UL
+#define UART0_REG_BASE              0x40011000UL
+#define UART1_REG_BASE              0x40012000UL
+#define UART2_REG_BASE              0x40012400UL
+#define SPI0_REG_BASE               0x40013000UL
+#define SPI1_REG_BASE               0x40013400UL
+#define HW_AES_REG_BASE             0x40014000UL
+#define I2C0_REG_BASE               0x40015000UL
+#define I2C1_REG_BASE               0x40015400UL
+#define IR_REG_BASE                 0x40015800UL
+#define SPDIF_REG_BASE              0x40021800UL
+#define CODEC_ANA_REG_BASE          0x40022000UL
+#define CODEC_REG_BASE              0x40022100UL
+#define H2D_D2H_REG_BASE            0x40023000UL
+#define IF8080_REG_BASE             0x40024800UL
+#define IF8080_LLI_REG1_BASE        0x40024850UL
+#define IF8080_LLI_REG1_GDMA_BASE   0x400248A0UL
+#define IF8080_LLI_REG2_BASE        0x40024880UL
+#define IF8080_LLI_REG2_GDMA_BASE   0x400248C0UL
+#define IF8080_LLI_REG1_OFT_BASE    0x40024870UL
+#define IF8080_LLI_REG2_OFT_BASE    0x40024878UL
+#define IF8080_LLI_CR_REG_BASE      0x40024894UL
+#define GDMA_CHANNEL_REG_BASE       0x40027000UL // for platform_1_1_1_20160323 later
+#define GDMA_Channel0_BASE          (GDMA_CHANNEL_REG_BASE + 0x0000)
+#define GDMA_Channel1_BASE          (GDMA_CHANNEL_REG_BASE + 0x0058)
+#define GDMA_Channel2_BASE          (GDMA_CHANNEL_REG_BASE + 0x00b0)
+#define GDMA_Channel3_BASE          (GDMA_CHANNEL_REG_BASE + 0x0108)
+#define GDMA_REG_BASE               (GDMA_CHANNEL_REG_BASE + 0x02c0)
+#define RXI300_REG_BASE             0x40024000UL
+#define I2S0_REG_BASE               0x40029000UL
+#define LCD_CTRL_BASE               0x4002A000UL
+#define SHA256_REG_BASE             0x4002B000UL
+#define FLASH_SEC_REG_BASE          0x4002C000UL
+#define SPI0_HS_REG_BASE            0x40040000UL
+#define BLUEWIZ_REG_BASE            0x40050000UL
+#define BT_DMA_BASE                 0x40055000UL
+#define BT_DMA_UART_BASE            0x40056000UL
+#define BT_VENDOR_REG_BASE          0x40058000UL
+#define SECURITY_REG_BASE           0x40058f28UL
+#define HCI_DMA_REG_BASE            0x40064000UL
+#define HCI_UART_REG_BASE           0x40068000UL
+#define ZIGBEE_REG_BASE             0x4005C000UL
+//#define GDMA0_REG_BASE              0x40060000UL
+#define SPIC0_REG_BASE              0x40080000UL
+#define SPIC1_REG_BASE              0x40082000UL
+
+#define SPI0_MASTER_MODE_REG *((volatile uint32_t *)0x40000308UL)
+#define SPI0_MASTER_MODE_BIT BIT(8)
+
+/** @brief clock divider for peripheral */
+#define SYSTEM_CLK_CTRL  *((volatile uint32_t *)0x4000020CUL)
+#define CLK_SOURCE_REG_0 *((volatile uint32_t *)0x40000348UL)
+#define CLK_SOURCE_REG_1 *((volatile uint32_t *)0x4000035CUL)
+#define CLK_SOURCE_REG_2 *((volatile uint32_t *)0x40000360UL)
+
+#define PERI_CLOCKGATE_REG_BASE     0x40000348UL
+
+#define REG_PEON_SYS_CLK_SEL        0x0200
+#define REG_PEON_SYS_CLK_SEL_2      0x0208
+#define REG_PEON_SYS_CLK_SEL_3      0x020C
+#define REG_SOC_FUNC_EN             0x0210
+#define REG_SOC_HCI_COM_FUNC_EN     0x0214
+#define REG_SOC_PERI_FUNC0_EN       0x0218
+#define REG_SOC_PERI_FUNC1_EN       0x021C
+#define REG_PESOC_CLK_CTRL          0x0230
+#define REG_PESOC_PERI_CLK_CTRL0    0x0234
+#define REG_PESOC_PERI_CLK_CTRL1    0x0238
+#define REG_PESOC_DSP_SHARE_RAM     0x0250
+#define REG_TEST_MODE               0x02a8
+#define REG_ANAPAR_PLL1_0           0x0320
+#define REG_ANAPAR_PLL3_2           0x0324
+#define REG_ANAPAR_PLL5_4           0x0328
+#define REG_XTAL_PLL_READY          0x0338
+
+#define GPIO_OUTPUT_OFFSET          0x00
+#define GPIO_DIRECTION_OFFSET       0x04
+
+/** @brief AON PAD AREA */
+#define REG_PAD_WKEN_ADDRESS        0x20
+#define REG_PAD_WK_CTRL_ADDRESS     0x12d
+#define REG_PAD_WKPOL_ADDRESS       0x25
+#define REG_PAD_O_ADDRESS           0x2A
+#define REG_AON_PAD_E_ADDRESS       0x2F
+#define REG_AON_PAD_S_ADDRESS       0x34
+#define REG_AON_PAD_PU_ADDRESS      0x39
+#define REG_AON_PAD_PD_ADDRESS      0x3E
+#define REG_AON_PAD_PWRON_ADDRESS   0x4C
+
+#define BIT_WK_INTEN                (1U << 7) /**< BIT7 */
+#define BIT_WK_FLAG_GPIO            (1U << 6) /**< BIT6 */
+
+#define BIT_SOC_ACTCK_GPIO_EN       (1U << 24) /**< BIT24 */
+#define BIT_PERI_GPIO_EN            (1U << 8) /**< BIT8 */
+
+#define BIT_PERI_KEYSCAN_EN         (1U << 19) /**< BIT19 */
+#define BIT_SOC_ACTCK_KEYSCAN_EN    (1U << 6) /**< BIT6 */
+
+
+/* ================================================================================ */
+/* ================             Peripheral declaration             ================ */
+/* ================================================================================ */
+/** @brief System */
+#define SoC_VENDOR                      ((SoC_VENDOR_REG_TypeDef    *) VENDOR_REG_BASE)
+#define PERIPH                          ((PHERIPHERIAL_TypeDef  *) PERIPH_REG_BASE)
+#define SYSBLKCTRL                      ((SYS_BLKCTRL_TypeDef   *) SYSBLKCTRL_REG_BASE)
+#define PERIPHINT                       ((PERI_INT_TypeDef      *) VENDOR_REG_BASE)
+#define SECURITY                        ((SECURITY_TypeDef      *) SECURITY_REG_BASE)
+
+/** @brief IO */
+#define PINMUX                          ((PINMUX_TypeDef        *) PINMUX_REG_BASE)
+#define KEYSCAN                         ((KEYSCAN_TypeDef       *) KEYSCAN_REG_BASE)
+#define GPIO                            ((GPIO_TypeDef          *) GPIO_REG_BASE)
+#define QDEC                            ((QDEC_TypeDef          *) QDEC_REG_BASE)
+#define PWM0_PN                         ((PWM_TypeDef           *) PWM0_REG_BASE)
+//#define PWM1_PN                         ((PWM_TypeDef           *) PWM1_REG_BASE)
+#define PWM2                            ((PWM_TypeDef           *) PWM2_REG_BASE)
+#define PWM3                            ((PWM_TypeDef           *) PWM3_REG_BASE)
+#define ADC                             ((ADC_TypeDef           *) ADC_REG_BASE)
+#define CODEC_ANA                       ((CODEC_AnalogTypeDef*)CODEC_ANA_REG_BASE)
+#define CODEC                           ((CODEC_TypeDef*) CODEC_REG_BASE)
+#define CTC                             ((CTC_TypeDef*)CAP_TOUCH_BASE)
+#define CTC_Channel0                    ((CTC_ChannelTypeDef*)CTC_Channel0_BASE)
+#define CTC_Channel1                    ((CTC_ChannelTypeDef*)CTC_Channel1_BASE)
+#define CTC_Channel2                    ((CTC_ChannelTypeDef*)CTC_Channel2_BASE)
+#define CTC_Channel3                    ((CTC_ChannelTypeDef*)CTC_Channel3_BASE)
+#define CTC_Channel4                    ((CTC_ChannelTypeDef*)CTC_Channel4_BASE)
+#define CTC_FAST                        ((CTC_FSModeTypeDef*)CTC_FAST_BASE)
+#define ENH_TIM0                        ((ENHTIM_TypeDef        *) ENHTIM0_REG_BASE)
+#define ENH_TIM1                        ((ENHTIM_TypeDef        *) ENHTIM1_REG_BASE)
+#define ENH_TIM_SHARE                   ((ENHTIM_ShareTypeDef   *) ENHTIM_SHARE_REG_BASE)
+#define GDMA_BASE                       ((GDMA_TypeDef *) GDMA_REG_BASE)
+#define GDMA_Channel0                   ((GDMA_ChannelTypeDef *) GDMA_Channel0_BASE)
+#define GDMA_Channel1                   ((GDMA_ChannelTypeDef *) GDMA_Channel1_BASE)
+#define GDMA_Channel2                   ((GDMA_ChannelTypeDef *) GDMA_Channel2_BASE)
+#define GDMA_Channel3                   ((GDMA_ChannelTypeDef *) GDMA_Channel3_BASE)
+#define I2C0                            ((I2C_TypeDef           *) I2C0_REG_BASE)
+#define I2C1                            ((I2C_TypeDef           *) I2C1_REG_BASE)
+#define I2S0                            ((I2S_TypeDef*) I2S0_REG_BASE)
+#define IR                              ((IR_TypeDef            *) IR_REG_BASE)
+#define LPC                             ((LPC_TypeDef             *) LPC_REG_BASE)
+#define HWAES                           ((HW_AES_TypeDef          *) HW_AES_REG_BASE)
+#define WDG                             ((WDG_TypeDef             *) WDG_REG_BASE)
+#define AON_WDG                         ((AON_WDG_TypeDef         *) AON_WDG_REG_BASE)
+#define RAN_GEN                         ((RAN_GEN_TypeDef         *) RANDOM_GEN_REG_BASE)
+#define ICG                             ((ICG_TypeDef             *) ICG_REG_BASE)
+#define CACHE                           ((CACHE_TypeDef           *) CACHE_REG_BASE)
+#define RTC                             ((RTC_TypeDef           *) RTC_REG_BASE)
+#define RTC_LED                         ((RTC_LED_TypeDef         *) RTC_LED_REG_BASE)
+#define RTC_LP                          ((RTC_LP_TypeDef        *) RTC_LP_REG_BASE)
+#define SPI0                            ((SPI_TypeDef           *) SPI0_REG_BASE)
+#define SPI1                            ((SPI_TypeDef           *) SPI1_REG_BASE)
+#define SPI3WIRE                        ((SPI3WIRE_TypeDef      *) SPI2WIRE_REG_BASE)
+#define SPIC                            ((SPIC_TypeDef            *) SPIC0_REG_BASE)
+#define SPIC0                           ((SPIC_TypeDef            *) SPIC0_REG_BASE)
+#define SPIC1                           ((SPIC_TypeDef            *) SPIC1_REG_BASE)
+#define SPIC2                           ((SPIC_TypeDef            *) SPIC2_REG_BASE)
+#define TIM0                            ((TIM_TypeDef           *) TIM0_REG_BASE)
+#define TIM1                            ((TIM_TypeDef           *) TIM1_REG_BASE)
+#define TIM2                            ((TIM_TypeDef           *) TIM2_REG_BASE)
+#define TIM3                            ((TIM_TypeDef           *) TIM3_REG_BASE)
+#define TIM4                            ((TIM_TypeDef           *) TIM4_REG_BASE)
+#define TIM5                            ((TIM_TypeDef           *) TIM5_REG_BASE)
+#define UART0                           ((UART_TypeDef          *) UART0_REG_BASE)
+#define UART1                           ((UART_TypeDef          *) UART1_REG_BASE)
+#define UART2                           ((UART_TypeDef          *) UART2_REG_BASE)
+#define GDMA0                           ((GDMA_TypeDef             *) GDMA_REG_BASE)
+#define IF8080                          ((IF8080_TypeDef*) IF8080_REG_BASE)
+#define IF8080_LLPGROUP1                ((IF8080_GDMALLITypeDef*) IF8080_LLI_REG1_BASE)
+#define IF8080_LLPGROUP2                ((IF8080_GDMALLITypeDef*) IF8080_LLI_REG2_BASE)
+#define IF8080_LLPGROUP1_GDMA           ((IF8080_GDMALLITypeDef*) IF8080_LLI_REG1_GDMA_BASE)
+#define IF8080_LLPGROUP2_GDMA           ((IF8080_GDMALLITypeDef*) IF8080_LLI_REG2_GDMA_BASE)
+#define IF8080_LLPGROUP1_OFT            ((IF8080_GDMALLIOFTTypeDef*) IF8080_LLI_REG1_OFT_BASE)
+#define IF8080_LLPGROUP2_OFT            ((IF8080_GDMALLIOFTTypeDef*) IF8080_LLI_REG2_OFT_BASE)
+#define IF8080_GDMA                     ((IF8080_GDMATypeDef*)IF8080_LLI_CR_REG_BASE)
+#define HWSHA256                        ((HW_SHA256_TypeDef        *) SHA256_REG_BASE)
+
+
+/************************ For lowerstack-dev ************************/
+#define TIMER_A0_REG_BASE                     TIM0_REG_BASE
+#define TIMA_CH0                              TIM0
+#define TIMA_CH1                              TIM1
+#define LOW_STACK_BZDMA_REG_BASE              BT_VENDOR_REG_BASE
+#define LOW_STACK_BT_DMA_REG_BASE_ADDR        BT_DMA_BASE
+#define LOW_STACK_BT_DMA_UART_BASE_ADDRESS    BT_DMA_UART_BASE
+#define LOW_STACK_BB_BASE_ADDR                BLUEWIZ_REG_BASE
+/******************************* end ********************************/
+
+/* ================================================================================ */
+/* ================                   Vendor macros                ================ */
+/* ================================================================================ */
+#define CLK_GATE                        ((Peri_ClockGate_TypeDef  *) PERI_CLOCKGATE_REG_BASE)
+
+#ifndef LITTLE_ENDIAN
+#define LITTLE_ENDIAN                   0
+#endif
+
+#ifndef BIG_ENDIAN
+#define BIG_ENDIAN                      1
+#endif
+
+#define SYSTEM_ENDIAN                   LITTLE_ENDIAN
+
+#define SWAP32(x) ((uint32_t)(\
+                              (((uint32_t)(x) & (uint32_t)0x000000ff) << 24) |\
+                              (((uint32_t)(x) & (uint32_t)0x0000ff00) <<  8) |\
+                              (((uint32_t)(x) & (uint32_t)0x00ff0000) >>  8) |\
+                              (((uint32_t)(x) & (uint32_t)0xff000000) >> 24)))
+
+#define WAP16(x) ((uint16_t)(\
+                             (((uint16_t)(x) & (uint16_t)0x00ff) <<  8) |\
+                             (((uint16_t)(x) & (uint16_t)0xff00) >>  8)))
+
+#if SYSTEM_ENDIAN == LITTLE_ENDIAN
+#ifndef rtk_le16_to_cpu
+#define rtk_cpu_to_le32(x)      ((uint32_t)(x))
+#define rtk_le32_to_cpu(x)      ((uint32_t)(x))
+#define rtk_cpu_to_le16(x)      ((uint16_t)(x))
+#define rtk_le16_to_cpu(x)      ((uint16_t)(x))
+#define rtk_cpu_to_be32(x)      SWAP32((x))
+#define rtk_be32_to_cpu(x)      SWAP32((x))
+#define rtk_cpu_to_be16(x)      WAP16((x))
+#define rtk_be16_to_cpu(x)      WAP16((x))
+#endif
+
+#elif SYSTEM_ENDIAN == BIG_ENDIAN
+#ifndef rtk_le16_to_cpu
+#define rtk_cpu_to_le32(x)      SWAP32((x))
+#define rtk_le32_to_cpu(x)      SWAP32((x))
+#define rtk_cpu_to_le16(x)      WAP16((x))
+#define rtk_le16_to_cpu(x)      WAP16((x))
+#define rtk_cpu_to_be32(x)      ((uint32_t)(x))
+#define rtk_be32_to_cpu(x)      ((uint32_t)(x))
+#define rtk_cpu_to_be16(x)      ((uint16_t)(x))
+#define rtk_be16_to_cpu(x)      ((uint16_t)(x))
+#endif
+#endif
+
+#define HAL_READ32(base, addr)            \
+    rtk_le32_to_cpu(*((volatile uint32_t *)(base + addr)))
+
+#define HAL_WRITE32(base, addr, value32)  \
+    ((*((volatile uint32_t *)(base + addr))) = rtk_cpu_to_le32(value32))
+
+#define HAL_UPDATE32(addr, mask, value32)  \
+    HAL_WRITE32(0, addr, (HAL_READ32(0, addr) & ~mask) | (value32 & mask))
+
+#define HAL_READ16(base, addr)            \
+    rtk_le16_to_cpu(*((volatile uint16_t *)(base + addr)))
+
+#define HAL_WRITE16(base, addr, value)  \
+    ((*((volatile uint16_t *)(base + addr))) = rtk_cpu_to_le16(value))
+
+#define HAL_UPDATE16(addr, mask, value16)  \
+    HAL_WRITE16(0, addr, (HAL_READ16(0, addr) & ~mask) | (value16 & mask))
+
+#define HAL_READ8(base, addr)            \
+    (*((volatile uint8_t *)(base + addr)))
+
+#define HAL_WRITE8(base, addr, value)  \
+    ((*((volatile uint8_t *)(base + addr))) = value)
+
+#define HAL_UPDATE8(addr, mask, value8)  \
+    HAL_WRITE8(0, addr, (HAL_READ8(0, addr) & ~mask) | (value8 & mask))
+
+#define BIT0        0x00000001
+#define BIT1        0x00000002
+#define BIT2        0x00000004
+#define BIT3        0x00000008
+#define BIT4        0x00000010
+#define BIT5        0x00000020
+#define BIT6        0x00000040
+#define BIT7        0x00000080
+#define BIT8        0x00000100
+#define BIT9        0x00000200
+#define BIT10       0x00000400
+#define BIT11       0x00000800
+#define BIT12       0x00001000
+#define BIT13       0x00002000
+#define BIT14       0x00004000
+#define BIT15       0x00008000
+#define BIT16       0x00010000
+#define BIT17       0x00020000
+#define BIT18       0x00040000
+#define BIT19       0x00080000
+#define BIT20       0x00100000
+#define BIT21       0x00200000
+#define BIT22       0x00400000
+#define BIT23       0x00800000
+#define BIT24       0x01000000
+#define BIT25       0x02000000
+#define BIT26       0x04000000
+#define BIT27       0x08000000
+#define BIT28       0x10000000
+#define BIT29       0x20000000
+#define BIT30       0x40000000
+#define BIT31       0x80000000
+
+#ifndef BIT
+#define BIT(_n)                  (uint32_t)(1U << (_n))
+#endif
+
+#ifndef BIT64
+#define BIT64(n)                 (1ULL << (n))
+#endif
+
+#ifndef BIT_BAND
+#define BIT_BAND(reg, bit_pos)   (*((volatile uint32_t*)(0x42000000 + ((uint32_t)&reg - 0x40000000) * 32 + bit_pos * 4)))
+#endif
+
+
+/* Uncomment the line below to expanse the "assert_param" macro in the
+   Standard Peripheral Library drivers code */
+
+//#define USE_FULL_ASSERT
+
+/** @} */ /* End of group RTL876X_Exported_Macros */
+
+
+/*============================================================================*
+  *                                Functions
+  *============================================================================*/
+/** @defgroup RTL876X_Exported_Functions CMSIS-RTL876X Exported Functions
+    * @brief
+    * @{
+    */
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr: If expr is false, it calls assert_failed function which reports
+  *         the name of the source file and the source line number of the call
+  *         that failed. If expr is true, it returns no value.
+  * @retval None
+  */
+#define assert_param(expr) ((expr) ? (void)0 : io_assert_failed((uint8_t *)__FILE__, __LINE__))
+void io_assert_failed(uint8_t *file, uint32_t line);
+#else
+#define assert_param(expr) ((void)0)
+#endif /* USE_FULL_ASSERT */
+
+/**
+    * @brief    Read data from aon register
+    * @param    offset: register address
+    * @return   data read from register
+    */
+extern uint16_t btaon_fast_read(uint16_t offset);
+extern uint8_t btaon_fast_read_8b(uint16_t offset);
+
+/**
+    * @brief    Read data from aon register safely
+    * @param    offset: register address
+    * @return   data read from register
+    */
+extern uint16_t btaon_fast_read_safe(uint16_t offset);
+extern uint8_t btaon_fast_read_safe_8b(uint16_t offset);
+
+/**
+    * @brief    Write data to aon register
+    * @param    offset:  register address
+    * @param    data:  data to be writen to register
+    * @return
+    */
+extern void btaon_fast_write(uint16_t offset, uint16_t data);
+extern void btaon_fast_write_8b(uint16_t offset, uint8_t data);
+
+/**
+    * @brief    Write data to aon egister safely
+    * @param    offset:  register address
+    * @param    data:  data to be writen to register
+    * @return
+    */
+extern void btaon_fast_write_safe(uint16_t offset, uint16_t data);
+extern void btaon_fast_write_safe_8b(uint16_t offset, uint8_t data);
+
+/**
+    * @brief    Write data to aon egister
+    * @param    offset: register address
+    * @param    mask:   indicate which bit in data will be updated
+    * @param    data:   data to be writen to register
+    * @return
+    */
+extern void btaon_fast_update(uint16_t offset, uint16_t mask, uint16_t data);
+extern void btaon_fast_update_8b(uint16_t offset, uint8_t mask, uint8_t data);
+
+/**
+    * @brief    Write data to aon egister safely
+    * @param    offset: register address
+    * @param    mask:   indicate which bit in data will be updated
+    * @param    data:   data to be writen to register
+    * @return
+    */
+extern void btaon_fast_update_safe(uint16_t offset, uint16_t mask, uint16_t data);
+extern void btaon_fast_update_safe_8b(uint16_t offset, uint8_t mask, uint8_t data);
+
+/** @} */ /* End of RTL876X_Exported_Functions */
+
+/** @} */ /* End of group RTL876X */
+
+#ifdef __cplusplus
+}
+#endif
+#endif  /* RTL876X_H */
diff --git a/bee/soc/inc/rtl8752h/rtl876x_alias.h b/bee/soc/inc/rtl8752h/rtl876x_alias.h
new file mode 100644
index 00000000..b3ef21f2
--- /dev/null
+++ b/bee/soc/inc/rtl8752h/rtl876x_alias.h
@@ -0,0 +1,130 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _RTL876X_ALIAS_H_
+#define _RTL876X_ALIAS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*============================================================================*
+ *                         Macros
+ *============================================================================*/
+/**
+ * \cond        private
+ * \brief       To be compatible with the previous driver.
+ * \defgroup    ADC_InitTypeDef_Alias ADC Init TypeDef Alias
+ * \{
+ */
+#define ADC_One_Shot_Mode ADC_ONE_SHOT_MODE
+#define schIndex ADC_SchIndex
+#define bitmap ADC_Bitmap
+#define adcSamplePeriod ADC_SampleTime
+#define PowerAlwaysOnEn ADC_PowerAlwaysOnEn
+#define dataWriteToFifo ADC_DataWriteToFifo
+#define timerTriggerEn ADC_TimerTriggerEn
+
+/**
+ * \}
+ * \endcond
+ */
+
+/**
+ * \cond        private
+ * \brief       To be compatible with the previous driver.
+ * \defgroup    ADC_API_Alias ADC API Alias
+ * \{
+ */
+#define ADC_ReadByScheduleIndex ADC_ReadRawData
+#define ADC_ReadFifoData ADC_ReadFIFO
+#define ADC_GetFifoData ADC_ReadFIFOData
+#define ADC_GetFifoLen ADC_GetFIFODataLen
+#define ADC_SchTableSet ADC_BitMapConfig
+#define ADC_PowerAlwaysOnCmd ADC_ManualPowerOnCmd
+#define ADC_FifoWriteCmd ADC_WriteFIFOCmd
+#define ADC_AnalogCircuitConfig ADC_PowerSupplyConfig
+#define ADC_GetIntFlagStatus ADC_GetINTStatus
+#define ADC_ClearFifo ADC_ClearFIFO
+#define ADC_GetIntStatus ADC_GetAllFlagStatus
+
+/**
+ * \}
+ * \endcond
+ */
+
+/**
+ * \cond        private
+ * \brief       To be compatible with the previous driver.
+ * \defgroup    RTC_API_Alias RTC API Alias
+ * \{
+ */
+#define RTC_SetComp RTC_SetCompValue
+#define RTC_RunCmd RTC_Cmd
+#define RTC_INT_CMP1 RTC_INT_COMP1
+
+/**
+ * \}
+ * \endcond
+ */
+
+/**
+ * \cond        private
+ * \brief       To be compatible with the previous driver.
+ * \defgroup    UART_InitTypeDef_Alias UART Init TypeDef Alias
+ * \{
+ */
+#define UART_OvsrAdj ovsr_adj
+#define UART_Div div
+#define UART_Ovsr ovsr
+#define UART_WordLen wordLen
+#define UART_Parity parity
+#define UART_StopBits stopBits
+#define UART_HardwareFlowControl autoFlowCtrl
+#define UART_TxThdLevel txTriggerLevel
+#define UART_RxThdLevel rxTriggerLevel
+#define UART_DmaEn dmaEn
+#define UART_IdleTime idle_time
+#define UART_TxWaterLevel TxWaterlevel
+#define UART_RxWaterLevel RxWaterlevel
+#define UART_TxDmaEn TxDmaEn
+#define UART_RxDmaEn RxDmaEn
+
+#define UART_INT_LINE_STS UART_INT_RX_LINE_STS
+#define UART_INT_ID_RX_TMEOUT UART_INT_ID_RX_DATA_TIMEOUT
+#define UART_FLAG_THR_EMPTY UART_FLAG_TX_FIFO_EMPTY
+#define UART_FLAG_THR_TSR_EMPTY UART_FLAG_TX_EMPTY
+#define UART_FLAG_RX_DATA_RDY UART_FLAG_RX_DATA_AVA
+
+/**
+ * \}
+ * \endcond
+ */
+
+/**
+ * \cond        private
+ * \brief       To be compatible with the previous driver.
+ * \defgroup    UART_API_Alias UART API Alias
+ * \{
+ */
+#define UART_GetFlagState UART_GetFlagStatus
+#define UART_ChangeBaudRate UART_SetBaudRate
+#define UART_ChangeParams UART_SetParams
+#define UART_ClearTxFifo UART_ClearTxFIFO
+#define UART_ClearRxFifo UART_ClearRxFIFO
+#define UART_GetTxFIFOLen UART_GetTxFIFODataLen
+#define UART_GetRxFIFOLen UART_GetRxFIFODataLen
+
+/**
+ * \}
+ * \endcond
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTL876X_ALIAS_H_ */
diff --git a/bee/soc/inc/rtl8752h/rtl876x_aon_reg.h b/bee/soc/inc/rtl8752h/rtl876x_aon_reg.h
new file mode 100644
index 00000000..b90a28a1
--- /dev/null
+++ b/bee/soc/inc/rtl8752h/rtl876x_aon_reg.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _RTL876X_AON_REG_H
+#define _RTL876X_AON_REG_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*============================================================================*
+ *                      Headers
+ *============================================================================*/
+#include <stdint.h>
+
+/*============================================================================*
+ *                         Macros
+ *============================================================================*/
+#define AON_FAST_REG_REG0X_FW_GENERAL               0x0
+
+/*============================================================================*
+ *                         Types
+ *============================================================================*/
+/* 0x0
+    6:0     R/W freg0[6:0]                              7'h0
+    7       W1P reg_rom_trace_prot                      1'h0
+    15:8    R   reserved                                8'h0
+ */
+typedef volatile union _AON_FAST_REG_REG0X_FW_GENERAL_TYPE
+{
+    uint16_t d16;
+    struct
+    {
+        uint16_t aon_boot_done : 1;
+        uint16_t pon_boot_done : 1;
+        uint16_t rsvd : 5;
+        uint16_t reg_rom_trace_port : 1;
+        uint16_t is_disable_set_reg_by_otp: 1;
+        uint16_t RESERVED_0: 7;
+    };
+} AON_FAST_REG_REG0X_FW_GENERAL_TYPE;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTL876X_AON_REG_H */
diff --git a/bee/soc/inc/rtl8752h/rtl876x_bitfields.h b/bee/soc/inc/rtl8752h/rtl876x_bitfields.h
new file mode 100644
index 00000000..db3c47df
--- /dev/null
+++ b/bee/soc/inc/rtl8752h/rtl876x_bitfields.h
@@ -0,0 +1,508 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __RTL876X_BITS_H
+#define __RTL876X_BITS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*============================================================================*
+ *                         Macros
+ *============================================================================*/
+/* Register: RTL_KEYSCAN_CR0 */
+/* Description: Control register 0. */
+
+/* Bit 31 : Keyscan clock enable */
+#define KEYSCAN_CR0_CLKEN_Pos (31UL) /*!< Position of clock enable field. */
+#define KEYSCAN_CR0_CLKEN_Msk (0x1UL << KEYSCAN_CR0_CLKEN_Pos) /*!< Bit mask of clock enable field. */
+#define KEYSCAN_CR0_CLKEN_Disabled (0UL) /*!< Clock disabled. */
+#define KEYSCAN_CR0_CLKEN_Enabled (1UL) /*!< Clock enabled. */
+
+/* Bit 8 : Column selection */
+#define KEYSCAN_CR0_COLSEL_Pos (8UL) /*!< Position of column selection field. */
+#define KEYSCAN_CR0_COLSEL_Msk (0xFFFFFUL << KEYSCAN_CR0_COLSEL_Pos) /*!< Bit mask of column selection field. */
+
+/* Bit 5 : Row number */
+#define KEYSCAN_CR0_ROWNUM_Pos (5UL) /*!< Position of row number field. */
+#define KEYSCAN_CR0_ROWNUM_Msk (0x07UL << KEYSCAN_CR0_ROWNUM_Pos) /*!< Bit mask of row number field. */
+
+
+/* Bit 0 : Column number */
+#define KEYSCAN_CR0_COLNUM_Pos (0UL) /*!< Position of column number field. */
+#define KEYSCAN_CR0_COLNUM_Msk (0x1FUL << KEYSCAN_CR0_COLNUM_Pos) /*!< Bit mask of column number field. */
+
+/* Register: RTL_KEYSCAN_CR1 */
+/* Description: Control register 1. */
+
+/* Bit 27 : Post guard time for column*/
+#define KEYSCAN_CR1_POSTGUARD_Pos (27UL) /*!< Position of post guard time field. */
+#define KEYSCAN_CR1_POSTGUARD_Msk (0x07UL << KEYSCAN_CR1_POSTGUARD_Pos) /*!< Bit mask of post guard time field. */
+
+/* Bit 24 : Pre guard time for column */
+#define KEYSCAN_CR1_PREGUARD_Pos (24UL) /*!< Position pre guard time field. */
+#define KEYSCAN_CR1_PREGUARD_Msk (0x07UL << KEYSCAN_CR1_PREGUARD_Pos) /*!< Bit mask of pre guard time field. */
+
+/* Bit 16 : Row selection */
+#define KEYSCAN_CR1_ROWSEL_Pos (16UL) /*!< Position of  row selection field. */
+#define KEYSCAN_CR1_ROWSEL_Msk (0xFFUL << KEYSCAN_CR1_ROWSEL_Pos) /*!< Bit mask of row selection field. */
+
+/* Bit 8 : Detection period */
+#define KEYSCAN_CR1_DETECTPERIOD_Pos (8UL) /*!< Position of detection period field. */
+#define KEYSCAN_CR1_DETECTPERIOD_Msk (0x07UL << KEYSCAN_CR1_DETECTPERIOD_Pos) /*!< Bit mask of detection period field. */
+#define KEYSCAN_CR1_DETECTPERIOD_Disabled (0UL) /*!< Detection disabled. */
+#define KEYSCAN_CR1_DETECTPERIOD_Enabled (1UL) /*!< Detection enabled. */
+
+/* Bit 7 : Debouncing enable */
+#define KEYSCAN_CR1_DEBOUNCEN_Pos (7UL) /*!< Position of debouncing enable field. */
+#define KEYSCAN_CR1_DEBOUNCEN_Msk (0x01UL << KEYSCAN_CR1_DEBOUNCEN_Pos) /*!< Bit mask of debouncing enable field. */
+#define KEYSCAN_CR1_DEBOUNCEN_Disabled (0UL) /*!< Debouncing disabled. */
+#define KEYSCAN_CR1_DEBOUNCEN_Enabled (1UL) /*!< Debouncing enabled. */
+
+/* Bit 2 : Timeout period */
+#define KEYSCAN_CR1_TOPERIOD_Pos (2UL) /*!< Position of timeout period field. */
+#define KEYSCAN_CR1_TOPERIOD_Msk (0x03UL << KEYSCAN_CR1_TOPERIOD_Pos) /*!< Bit mask of timeout period field. */
+
+/* Bit 0 : Wait period */
+#define KEYSCAN_CR1_WAITPERIOD_Pos (0UL) /*!< Position of wait period field. */
+#define KEYSCAN_CR1_WAITPERIOD_Msk (0x03UL << KEYSCAN_CR1_WAITPERIOD_Pos) /*!< Bit mask of wait period field. */
+
+
+/* Register: RTL_KEYSCAN_CR2 */
+/* Description: Control register 2. */
+
+/* Bit 27 : Program debouncing time enable */
+#define KEYSCAN_CR2_DEBEN_Pos (27UL) /*!< Position of program debouncing time enable field. */
+#define KEYSCAN_CR2_DEBEN_Msk (0x1UL << KEYSCAN_CR2_DEBEN_Pos) /*!< Bit mask of program debouncing time enable  field. */
+#define KEYSCAN_CR2_DEBEN_Disabled (0UL) /*!< Clock disabled. */
+#define KEYSCAN_CR2_DEBEN_Enabled (1UL) /*!< Clock enabled. */
+
+/* Bit 16 : Debouncing time*/
+#define KEYSCAN_CR2_DEBTIME_Pos (16UL) /*!< Position of debouncing time field. */
+#define KEYSCAN_CR2_DEBTIME_Msk (0x3FFUL << KEYSCAN_CR2_DEBTIME_Pos) /*!< Bit mask of debouncing time field. */
+
+/* Bit 15 : FIFO clear */
+#define KEYSCAN_CR2_FIFOCLEAR_Pos (15UL) /*!< Position of FIFO clear field. */
+#define KEYSCAN_CR2_FIFOCLEAR_Msk (0x1UL << KEYSCAN_CR2_FIFOCLEAR_Pos) /*!< Bit mask of FIFO clear field. */
+
+/* Bit 14 : Force scan fsm idle */
+#define KEYSCAN_CR2_FSMIDLE_Pos (14UL) /*!< Position of force scan fsm idle field. */
+#define KEYSCAN_CR2_FSMIDLE_Msk (0x1UL << KEYSCAN_CR2_FSMIDLE_Pos) /*!< Bit mask of force scan fsm idle field. */
+
+/* Bit 13 : FIFO flag clear1 */
+#define KEYSCAN_CR2_FIFOFLAGCLR1_Pos (13UL) /*!< Position of FIFO flag clear1 field. */
+#define KEYSCAN_CR2_FIFOFLAGCLR1_Msk (0x1UL << KEYSCAN_CR2_FIFOFLAGCLR1_Pos) /*!< Bit mask of FIFO flag clear1 field. */
+
+/* Bit 12 : FIFO flag clear2 */
+#define KEYSCAN_CR2_FIFOFLAGCLR2_Pos (12UL) /*!< Position of FIFO flag clear2 field. */
+#define KEYSCAN_CR2_FIFOFLAGCLR2_Msk (0x1UL << KEYSCAN_CR2_FIFOFLAGCLR2_Pos) /*!< Bit mask of FIFO flag clear2 field. */
+
+/* Bit 7 : Key scan trigger type */
+#define KEYSCAN_CR2_TRIGTYPE_Pos (7UL) /*!< Position of ey scan trigger type field. */
+#define KEYSCAN_CR2_TRIGTYPE_Msk (0x1UL << KEYSCAN_CR2_TRIGTYPE_Pos) /*!< Bit mask of key scan trigger type field. */
+#define KEYSCAN_CR2_TRIGTYPE_EDGE (0UL) /*!< Edge trigger */
+#define KEYSCAN_CR2_TRIGTYPE_LEVEL (1UL) /*!< Level trigger */
+
+/* Bit 6 : FIFO overflow control */
+#define KEYSCAN_CR2_FIFOOVCTL_Pos (6UL) /*!< Position of FIFO overflow control field. */
+#define KEYSCAN_CR2_FIFOOVCTL_Msk (0x1UL << KEYSCAN_CR2_FIFOOVCTL_Pos) /*!< Bit mask of FIFO overflow control field. */
+#define KEYSCAN_CR2_FIFOOVCTL_DISCARDNEW (0UL) /*!< Discard all the new scan data when FIFO is full. */
+#define KEYSCAN_CR2_FIFOOVCTL_DISCARDOLD (1UL) /*!< Discard the last scan data when FIFO is full. */
+
+/* Bit 0 : Scan key limit */
+#define KEYSCAN_CR2_KEYLIMIT_Pos (0UL) /*!< Position of scan key limit field. */
+#define KEYSCAN_CR2_KEYLIMIT_Msk (0x1FUL << KEYSCAN_CR2_KEYLIMIT_Pos) /*!< Bit mask of scan key limit field. */
+
+
+/* Register: RTL_KEYSCAN_INTCR */
+/* Description: Interrupt Control Register */
+
+/* Bit 15 : Interrupt mask */
+#define KEYSCAN_INTCR_INTMSK_Pos (15UL) /*!< Position of interrupt mask field. */
+#define KEYSCAN_INTCR_INTMSK_Msk (0x1UL << KEYSCAN_INTCR_INTMSK_Pos) /*!< Bit mask of interrupt mask field. */
+
+/* Bit 14 : Int3 clear */
+#define KEYSCAN_INTCR_INT3CLR_Pos (14UL) /*!< Position of Int3 clear field. */
+#define KEYSCAN_INTCR_INT3CLR_Msk (0x1UL << KEYSCAN_INTCR_INT3CLR_Pos) /*!< Bit mask of Int3 clear field. */
+
+/* Bit 13 : Int2 clear */
+#define KEYSCAN_INTCR_INT2CLR_Pos (13UL) /*!< Position of Int2 clear field. */
+#define KEYSCAN_INTCR_INT2CLR_Msk (0x1UL << KEYSCAN_INTCR_INT2CLR_Pos) /*!< Bit mask of Int2 clear field. */
+
+/* Bit 12 : Int1 clear */
+#define KEYSCAN_INTCR_INT1CLR_Pos (12UL) /*!< Position of Int1 clear field. */
+#define KEYSCAN_INTCR_INT1CLR_Msk (0x1UL << KEYSCAN_INTCR_INT1CLR_Pos) /*!< Bit mask of Int1 clear field. */
+
+/* Bit 11 : Interrupt control mode */
+#define KEYSCAN_INTCR_INTCTLMODE_Pos (11UL) /*!< Position of interrupt control mode field. */
+#define KEYSCAN_INTCR_INTCTLMODE_Msk (0x1UL << KEYSCAN_INTCR_INTCTLMODE_Pos) /*!< Bit mask of interrupt control mode field. */
+#define KEYSCAN_INTCR_INTCTLMODE_HW (0UL) /*!< HW control interrupt mode */
+#define KEYSCAN_INTCR_INTCTLMODE_SW (1UL) /*!< SW control interrupt mode */
+
+/* Bit 10 : Enable/Disable interrupt in SW control mode */
+#define KEYSCAN_INTCR_SWINTEN_Pos (10UL) /*!< Position of Enable/Disable interrupt in SW control mode field. */
+#define KEYSCAN_INTCR_SWINTEN_Msk (0x1UL << KEYSCAN_INTCR_SWINTEN_Pos) /*!< Bit mask of Enable/Disable interrupt in SW control mode field. */
+
+/* Bit 8 : Interrupt timeout period */
+#define KEYSCAN_INTCR_INTTOPERIOD_Pos (8UL) /*!< Position of Interrupt timeout period field. */
+#define KEYSCAN_INTCR_INTTOPERIOD_Msk (0x3UL << KEYSCAN_INTCR_INTTOPERIOD_Pos) /*!< Bit mask of Interrupt timeout period field. */
+
+/* Bit 4 : Interrupt threshold */
+#define KEYSCAN_INTCR_INTTHRESHOLD_Pos (4UL) /*!< Position of ey Interrupt threshold field. */
+#define KEYSCAN_INTCR_INTTHRESHOLD_Msk (0x07UL << KEYSCAN_INTCR_INTTHRESHOLD_Pos) /*!< Bit mask of key Interrupt threshold field. */
+
+/* Bit 2 : Int3 enable */
+#define KEYSCAN_INTCR_INT3EN_Pos (2UL) /*!< Position of Int3 enable field. */
+#define KEYSCAN_INTCR_INT3EN_Msk (0x1UL << KEYSCAN_INTCR_INT3EN_Pos) /*!< Bit mask of Int3 enable field. */
+
+/* Bit 1 : Int2 enable */
+#define KEYSCAN_INTCR_INT2EN_Pos (1UL) /*!< Position of Int2 enable field. */
+#define KEYSCAN_INTCR_INT2EN_Msk (0x1UL << KEYSCAN_INTCR_INT2EN_Pos) /*!< Bit mask of Int2 enable field. */
+
+/* Bit 0 : Int1 enable */
+#define KEYSCAN_INTCR_INT1EN_Pos (0UL) /*!< Position of Int1 enable field. */
+#define KEYSCAN_INTCR_INT1EN_Msk (0x1UL << KEYSCAN_INTCR_INT1EN_Pos) /*!< Bit mask of Int1 enable field. */
+
+
+/* Register: RTL_KEYSCAN_FIFODATA */
+/* Description: . */
+
+/* Bit 5 : Row index */
+#define KEYSCAN_FIFODATA_ROWINDEX_Pos (5UL) /*!< Position of row index field. */
+#define KEYSCAN_FIFODATA_ROWINDEX_Msk (0x1FUL << KEYSCAN_FIFODATA_ROWINDEX_Pos) /*!< Bit mask of row index field. */
+
+/* Bit 0 : Column index */
+#define KEYSCAN_FIFODATA_COLINDEX_Pos (0UL) /*!< Position of column index field. */
+#define KEYSCAN_FIFODATA_COLINDEX_Msk (0x7UL << KEYSCAN_FIFODATA_COLINDEX_Pos) /*!< Bit mask of column index field. */
+
+
+/* Register: RTL_KEYSCAN_STATUS */
+/* Description: . */
+
+/* Bit 8 : FIFO offset */
+#define KEYSCAN_STATUS_FIFOOFFSET_Pos (8UL) /*!< Position of FIFO offset field. */
+#define KEYSCAN_STATUS_FIFOOFFSET_Msk (0x1FUL << KEYSCAN_STATUS_FIFOOFFSET_Pos) /*!< Bit mask of FIFO offset field. */
+
+/* Bit 7 : FIFO reject flag */
+#define KEYSCAN_STATUS_FIFOREJECT_Pos (7UL) /*!< Position of FIFO reject flag. */
+#define KEYSCAN_STATUS_FIFOREJECT_Msk (0x1UL << KEYSCAN_STATUS_FIFOREJECT_Pos) /*!< Bit mask of FIFO reject flag. */
+
+/* Bit 6 : FIFO overflow flag */
+#define KEYSCAN_STATUS_FIFOOVERFLOW_Pos (5UL) /*!< Position of FIFO overflow flag field. */
+#define KEYSCAN_STATUS_FIFOOVERFLOW_Msk (0x1UL << KEYSCAN_STATUS_FIFOOVERFLOW_Pos) /*!< Bit mask of FIFO overflow flag field. */
+
+/* Bit 5 : FIFO full flag */
+#define KEYSCAN_STATUS_FIFOFULL_Pos (5UL) /*!< Position of FIFO full flag field. */
+#define KEYSCAN_STATUS_FIFOFULL_Msk (0x1UL << KEYSCAN_STATUS_FIFOFULL_Pos) /*!< Bit mask of FIFO full flag field. */
+
+/* Bit 4 : FIFO empty flag */
+#define KEYSCAN_STATUS_FIFOEMPTY_Pos (4UL) /*!< Position of FIFO empty flag field. */
+#define KEYSCAN_STATUS_FIFOEMPTY_Msk (0x1UL << KEYSCAN_STATUS_FIFOEMPTY_Pos) /*!< Bit mask of FIFO empty flag field. */
+
+/* Bit 0 : Current state */
+#define KEYSCAN_STATUS_CURSTATE_Pos (0UL) /*!< Position of Current state field. */
+#define KEYSCAN_STATUS_CURSTATE_Msk (0x7UL << KEYSCAN_STATUS_CURSTATE_Pos) /*!< Bit mask of Current state field. */
+
+
+/****************************************************************************************************************/
+/* Peripheral: System Block Control */
+/* Description: System Block Control. */
+
+/* Register: REG_SYS_CLK_SEL */
+/* Description: REG_SYS_CLK_SEL. */
+
+/* Bit 31 : r_SYS_CKE_SPLL. Clock enable of 40MHz and divider */
+#define SYSBLK_SYSCLK_CLKEN_SPLL_Pos (31UL) /*!< Position of  */
+#define SYSBLK_SYSCLK_CLKEN_SPLL_Msk (0x1UL << SYSBLK_SYSCLK_CLKEN_SPLL_Pos) /*!< Bit mask of  */
+
+/* Bit 30 : r_SYS_40M_SEL. 0: from 40M RCOSC 1: from PLL */
+#define SYSBLK_SYSCLK_SRCSEL_Pos (30UL) /*!< Position of . */
+#define SYSBLK_SYSCLK_SRCSEL_Msk (0x1UL << SYSBLK_SYSCLK_SRCSEL_Pos) /*!< Bit mask of  */
+
+/* Bit 0 : BIT_SYS_CKSL_CPU. CPU clock select 0: 40MHz 1: 20MHz 2: 10MHz 3: 5MHz 4: 53MHz 5: 26.5MHz Others: reserved */
+#define SYSBLK_SYSCLK_CPUCLK_Pos (0UL) /*!< Position of  */
+#define SYSBLK_SYSCLK_CPUCLK_Msk (0x7UL << SYSBLK_SYSCLK_CPUCLK_Pos) /*!< Bit mask of  */
+
+
+/* Register: REG_SOC_FUNC_EN */
+/* Description: REG_SOC_FUNC_EN. */
+
+/* Bit 16 : BIT_SOC_GTIMER_EN. 1: enable GTIMER IP and GTIMER register */
+#define SYSBLK_GTIMER_EN_Pos (16UL) /*!< Position of  */
+#define SYSBLK_GTIMER_EN_Msk (0x1UL << SYSBLK_GTIMER_EN_Pos) /*!< Bit mask of  */
+
+/* Bit 13 : BIT_SOC_GDMA0_EN. 1: Enable GDMA block */
+#define SYSBLK_GDMA0_EN_Pos (13UL) /*!< Position of . */
+#define SYSBLK_GDMA0_EN_Msk (0x1UL << SYSBLK_GDMA0_EN_Pos) /*!< Bit mask of  */
+
+/* Bit 12 : BIT_SOC_UART0_EN. 1: enable log UART; 0: disable log UART */
+#define SYSBLK_UART0_EN_Pos (12UL) /*!< Position of . */
+#define SYSBLK_UART0_EN_Msk (0x1UL << SYSBLK_UART0_EN_Pos) /*!< Bit mask of  */
+
+/* Bit 5 : BIT_SOC_eFLASH_EN. 1. enable eflash controller */
+#define SYSBLK_EFLASH_EN_Pos (5UL) /*!< Position of . */
+#define SYSBLK_EFLASH_EN_Msk (0x1UL << SYSBLK_EFLASH_EN_Pos) /*!< Bit mask of  */
+
+/* Bit 4 : BIT_SOC_FLASH_EN. 1: enaable flash controller */
+#define SYSBLK_EXTFLASH_EN_Pos (4UL) /*!< Position of . */
+#define SYSBLK_EXTFLASH_EN_Msk (0x1UL << SYSBLK_EXTFLASH_EN_Pos) /*!< Bit mask of  */
+
+/* Bit 2 : BIT_SOC_BTBUS_EN. 1: enable BT function */
+#define SYSBLK_BTBUS_EN_Pos (2UL) /*!< Position of . */
+#define SYSBLK_BTBUS_EN_Msk (0x1UL << SYSBLK_BTBUS_EN_Pos) /*!< Bit mask of  */
+
+
+/* Register: REG_SOC_PERI_FUNC0_EN */
+/* Description: REG_SOC_PERI_FUNC0_EN. */
+
+/* Bit 24 : BIT_PERI_SPI2W_EN. 1: enable 2-wire/3-wire SPI interface */
+#define SYSBLK_SPI2W_EN_Pos (24UL) /*!< Position of  */
+#define SYSBLK_SPI2W_EN_Msk (0x1UL << SYSBLK_SPI2W_EN_Pos) /*!< Bit mask of  */
+
+/* Bit 19 : BIT_PERI_KEYSCAN_EN. 1: enable KEYSCAN interface */
+#define SYSBLK_KEYSCAN_EN_Pos (19UL) /*!< Position of . */
+#define SYSBLK_KEYSCAN_EN_Msk (0x1UL << SYSBLK_KEYSCAN_EN_Pos) /*!< Bit mask of  */
+
+/* Bit 18 : BIT_PERI_QDECODE_EN. 1: enable QDECODE interface */
+#define SYSBLK_QDECODE_EN_Pos (18UL) /*!< Position of . */
+#define SYSBLK_QDECODE_EN_Msk (0x1UL << SYSBLK_QDECODE_EN_Pos) /*!< Bit mask of  */
+
+/* Bit 17 : BIT_PERI_I2C1_EN. 1: enable I2C1 interface */
+#define SYSBLK_I2C1_EN_Pos (17UL) /*!< Position of . */
+#define SYSBLK_I2C1_EN_Msk (0x1UL << SYSBLK_I2C1_EN_Pos) /*!< Bit mask of  */
+
+/* Bit 16 : BIT_PERI_I2C0_EN. 1: enable I2C0 interface */
+#define SYSBLK_I2C0_EN_Pos (16UL) /*!< Position of . */
+#define SYSBLK_I2C0_EN_Msk (0x1UL << SYSBLK_I2C0_EN_Pos) /*!< Bit mask of  */
+
+/* Bit 10 : BIT_PERI_IR_EN. 1: enable IR interface */
+#define SYSBLK_IR_EN_Pos (10UL) /*!< Position of . */
+#define SYSBLK_IR_EN_Msk (0x1UL << SYSBLK_IR_EN_Pos) /*!< Bit mask of  */
+
+/* Bit 9 : BIT_PERI_SPI1_EN. 1: enable SPI1 interface */
+#define SYSBLK_SPI1_EN_Pos (9UL) /*!< Position of . */
+#define SYSBLK_SPI1_EN_Msk (0x1UL << SYSBLK_SPI1_EN_Pos) /*!< Bit mask of  */
+
+/* Bit 8 : BIT_PERI_SPI0_EN. 1: enable SPI0 interface */
+#define SYSBLK_SPI0_EN_Pos (8UL) /*!< Position of . */
+#define SYSBLK_SPI0_EN_Msk (0x1UL << SYSBLK_SPI0_EN_Pos) /*!< Bit mask of  */
+
+/* Bit 1 : BIT_PERI_UART1_EN. 1; enable UART1 interface ( DATA Uart1) */
+#define SYSBLK_UART2_EN_Pos (1UL) /*!< Position of . */
+#define SYSBLK_UART2_EN_Msk (0x1UL << SYSBLK_UART2_EN_Pos) /*!< Bit mask of  */
+
+/* Bit 0 : BIT_PERI_UART0_EN. 1; enable UART0 interface ( DATA Uart) */
+#define SYSBLK_UART1_EN_Pos (0UL) /*!< Position of . */
+#define SYSBLK_UART1_EN_Msk (0x1UL << SYSBLK_UART1_EN_Pos) /*!< Bit mask of  */
+
+
+/* Register: REG_SOC_PERI_FUNC1_EN */
+/* Description: REG_SOC_PERI_FUNC1_EN. */
+
+/* Bit 8 : BIT_PERI_GPIO_EN. 1: enable DW GPIO */
+#define SYSBLK_GPIO_EN_Pos (8UL) /*!< Position of  */
+#define SYSBLK_GPIO_EN_Msk (0x1UL << SYSBLK_GPIO_EN_Pos) /*!< Bit mask of  */
+
+/* Bit 0 : BIT_PERI_ADC_EN. 1: enable ADC */
+#define SYSBLK_ADC_EN_Pos (0UL) /*!< Position of . */
+#define SYSBLK_ADC_EN_Msk (0x1UL << SYSBLK_ADC_EN_Pos) /*!< Bit mask of  */
+
+
+/* Register: REG_PESOC_CLK_CTRL */
+/* Description: REG_PESOC_CLK_CTRL. */
+
+/* Bit 25 : BIT_SOC_SLPCK_GPIO_EN */
+#define SYSBLK_SLPCK_GPIO_EN_Pos (25UL) /*!< Position of  */
+#define SYSBLK_SLPCK_GPIO_EN_Msk (0x1UL << SYSBLK_SLPCK_GPIO_EN_Pos) /*!< Bit mask of  */
+
+/* Bit 24 : BIT_SOC_ACTCK_GPIO_EN */
+#define SYSBLK_ACTCK_GPIO_EN_Pos (24UL) /*!< Position of  */
+#define SYSBLK_ACTCK_GPIO_EN_Msk (0x1UL << SYSBLK_ACTCK_GPIO_EN_Pos) /*!< Bit mask of  */
+
+/* Bit 17 : BIT_SOC_SLPCK_GDMA0_EN */
+#define SYSBLK_SLPCK_GDMA0_EN_Pos (17UL) /*!< Position of  */
+#define SYSBLK_SLPCK_GDMA0_EN_Msk (0x1UL << SYSBLK_SLPCK_GDMA0_EN_Pos) /*!< Bit mask of  */
+
+/* Bit 16 : BIT_SOC_ACTCK_GDMA0_EN */
+#define SYSBLK_ACTCK_GDMA0_EN_Pos (16UL) /*!< Position of  */
+#define SYSBLK_ACTCK_GDMA0_EN_Msk (0x1UL << SYSBLK_ACTCK_GDMA0_EN_Pos) /*!< Bit mask of  */
+
+/* Bit 15 : BIT_SOC_SLPCK_TIMER_EN */
+#define SYSBLK_SLPCK_TIMER_EN_Pos (15UL) /*!< Position of  */
+#define SYSBLK_SLPCK_TIMER_EN_Msk (0x1UL << SYSBLK_SLPCK_TIMER_EN_Pos) /*!< Bit mask of  */
+
+/* Bit 14 : BIT_SOC_ACTCK_TIMER_EN */
+#define SYSBLK_ACTCK_TIMER_EN_Pos (14UL) /*!< Position of  */
+#define SYSBLK_ACTCK_TIMER_EN_Msk (0x1UL << SYSBLK_ACTCK_TIMER_EN_Pos) /*!< Bit mask of  */
+
+/* Bit 13 : BIT_SOC_SLPCK_UART0_EN */
+#define SYSBLK_SLPCK_UART0_EN_Pos (13UL) /*!< Position of  */
+#define SYSBLK_SLPCK_UART0_EN_Msk (0x1UL << SYSBLK_SLPCK_UART0_EN_Pos) /*!< Bit mask of  */
+
+/* Bit 12 : BIT_SOC_ACTCK_UART0_EN */
+#define SYSBLK_ACTCK_UART0_EN_Pos (12UL) /*!< Position of  */
+#define SYSBLK_ACTCK_UART0_EN_Msk (0x1UL << SYSBLK_ACTCK_UART0_EN_Pos) /*!< Bit mask of  */
+
+/* Bit 11 : BIT_SOC_SLPCK_UART2_EN */
+#define SYSBLK_SLPCK_UART2_EN_Pos (11UL) /*!< Position of  */
+#define SYSBLK_SLPCK_UART2_EN_Msk (0x1UL << SYSBLK_SLPCK_UART2_EN_Pos) /*!< Bit mask of  */
+
+/* Bit 10 : BIT_SOC_ACTCK_UART2_EN */
+#define SYSBLK_ACTCK_UART2_EN_Pos (10UL) /*!< Position of  */
+#define SYSBLK_ACTCK_UART2_EN_Msk (0x1UL << SYSBLK_ACTCK_UART2_EN_Pos) /*!< Bit mask of  */
+
+/* Bit 9 : BIT_SOC_SLPCK_FLASH_EN */
+#define SYSBLK_SLPCK_FLASH_EN_Pos (9UL) /*!< Position of  */
+#define SYSBLK_SLPCK_FLASH_EN_Msk (0x1UL << SYSBLK_SLPCK_FLASH_EN_Pos) /*!< Bit mask of  */
+
+/* Bit 8 : BIT_SOC_ACTCK_FLASH_EN */
+#define SYSBLK_ACTCK_FLASH_EN_Pos (8UL) /*!< Position of  */
+#define SYSBLK_ACTCK_FLASH_EN_Msk (0x1UL << SYSBLK_ACTCK_FLASH_EN_Pos) /*!< Bit mask of  */
+
+/* Bit 7 : BIT_SOC_SLPCK_VENDOR_REG_EN */
+#define SYSBLK_SLPCK_VENDORREG_EN_Pos (7UL) /*!< Position of  */
+#define SYSBLK_SLPCK_VENDORREG_EN_Msk (0x1UL << SYSBLK_SLPCK_VENDORREG_EN_Pos) /*!< Bit mask of  */
+
+/* Bit 6 : BIT_SOC_ACTCK_VENDOR_REG_EN */
+#define SYSBLK_ACTCK_VENDORREG_EN_Pos (6UL) /*!< Position of  */
+#define SYSBLK_ACTCK_VENDORREG_EN_Msk (0x1UL << SYSBLK_ACTCK_VENDORREG_EN_Pos) /*!< Bit mask of  */
+
+/* Bit 3 : BIT_CKE_EFC. Embedded flash controller clock enable */
+#define SYSBLK_EFLASH_CLK_EN_Pos (3UL) /*!< Position of  */
+#define SYSBLK_EFLASH_CLK_Msk (0x1UL << SYSBLK_EFLASH_CLK_EN_Pos) /*!< Bit mask of  */
+
+/* Bit 1 : BIT_CKE_CORDIC. CORDIC clock enable */
+#define SYSBLK_CODEC_CLK_EN_Pos (1UL) /*!< Position of  */
+#define SYSBLK_CODEC_CLK_EN_Msk (0x1UL << SYSBLK_CODEC_CLK_EN_Pos) /*!< Bit mask of  */
+
+/* Bit 0 : BIT_CKE_HWSPI. HWSPI clock enable */
+#define SYSBLK_HWSPI_CLK_EN_Pos (0UL) /*!< Position of  */
+#define SYSBLK_HWSPI_CLK_EN_Msk (0x1UL << SYSBLK_HWSPI_CLK_EN_Pos) /*!< Bit mask of  */
+#define SYSBLK_ADC_EN_Msk (0x1UL << SYSBLK_ADC_EN_Pos) /*!< Bit mask of  */
+
+
+/* Register: REG_PESOC_PERI_CLK_CTRL0 */
+/* Description: REG_PESOC_PERI_CLK_CTRL0. */
+
+/* Bit 21 : BIT_SOC_SLPCK_IR_EN. 1: IR clock enable when CPU sleep command */
+#define SYSBLK_SLPCK_IR_EN_Pos (21UL) /*!< Position of  */
+#define SYSBLK_SLPCK_IR_EN_Msk (0x1UL << SYSBLK_SLPCK_IR_EN_Pos) /*!< Bit mask of  */
+
+/* Bit 20 : BIT_SOC_ACTCK_IR_EN */
+#define SYSBLK_ACTCK_IR_EN_Pos (20UL) /*!< Position of  */
+#define SYSBLK_ACTCK_IR_EN_Msk (0x1UL << SYSBLK_ACTCK_IR_EN_Pos) /*!< Bit mask of  */
+
+/* Bit 19 : BIT_SOC_SLPCK_SPI1_EN */
+#define SYSBLK_SLPCK_SPI1_EN_Pos (19UL) /*!< Position of  */
+#define SYSBLK_SLPCK_SPI1_EN_Msk (0x1UL << SYSBLK_SLPCK_SPI1_EN_Pos) /*!< Bit mask of  */
+
+/* Bit 18 : BIT_SOC_ACTCK_SPI1_EN */
+#define SYSBLK_ACTCK_SPI1_EN_Pos (18UL) /*!< Position of  */
+#define SYSBLK_ACTCK_SPI1_EN_Msk (0x1UL << SYSBLK_ACTCK_SPI1_EN_Pos) /*!< Bit mask of  */
+
+/* Bit 17 : BIT_SOC_SLPCK_SPI0_EN */
+#define SYSBLK_SLPCK_SPI0_EN_Pos (17UL) /*!< Position of  */
+#define SYSBLK_SLPCK_SPI0_EN_Msk (0x1UL << SYSBLK_SLPCK_SPI0_EN_Pos) /*!< Bit mask of  */
+
+/* Bit 16 : BIT_SOC_ACTCK_SPI0_EN */
+#define SYSBLK_ACTCK_SPI0_EN_Pos (16UL) /*!< Position of  */
+#define SYSBLK_ACTCK_SPI0_EN_Msk (0x1UL << SYSBLK_ACTCK_SPI0_EN_Pos) /*!< Bit mask of  */
+
+///* Bit 3 : BIT_SOC_SLPCK_UART1_HCI_EN */
+//#define SYSBLK_SLPCK_UART1HCI_EN_Pos (3UL) /*!< Position of  */
+//#define SYSBLK_SLPCK_UART1HCI_EN_Msk (0x1UL << SYSBLK_SLPCK_UART1HCI_EN_Pos) /*!< Bit mask of  */
+
+///* Bit 2 : BIT_SOC_ACTCK_UART1_HCI_EN */
+//#define SYSBLK_ACTCK_UART1HCI_EN_Pos (2UL) /*!< Position of  */
+//#define SYSBLK_ACTCK_UART1HCI_EN_Msk (0x1UL << SYSBLK_ACTCK_UART1HCI_EN_Pos) /*!< Bit mask of  */
+
+/* Bit 1 : BIT_SOC_SLPCK_UART1_DATA_EN */
+#define SYSBLK_SLPCK_UART1_EN_Pos (1UL) /*!< Position of  */
+#define SYSBLK_SLPCK_UART1_EN_Msk (0x1UL << SYSBLK_SLPCK_UART1_EN_Pos) /*!< Bit mask of  */
+
+/* Bit 0 : BIT_SOC_ACTCK_UART1_DATA_EN */
+#define SYSBLK_ACTCK_UART1_EN_Pos (0UL) /*!< Position of  */
+#define SYSBLK_ACTCK_UART1_EN_Msk (0x1UL << SYSBLK_ACTCK_UART1_EN_Pos) /*!< Bit mask of  */
+
+
+/* Register: REG_PESOC_PERI_CLK_CTRL1 */
+/* Description: REG_PESOC_PERI_CLK_CTRL1. */
+
+/* Bit 31 : r_CODEC_CLK_10M_EN. Codec 10MHz clock source enable */
+#define SYSBLK_CODEC_CLK10M_EN_Pos (31UL) /*!< Position of  */
+#define SYSBLK_CODEC_CLK10M_EN_Msk (0x1UL << SYSBLK_CODEC_CLK10M_EN_Pos) /*!< Bit mask of  */
+
+/* Bit 30 : r_CODEC_CLK_40M_EN */
+#define SYSBLK_CODEC_CLK40M_EN_Pos (30UL) /*!< Position of  */
+#define SYSBLK_CODEC_CLK40M_EN_Msk (0x1UL << SYSBLK_CODEC_CLK40M_EN_Pos) /*!< Bit mask of  */
+
+/* Bit 25 : BIT_SOC_SLPCK_ADC_EN */
+#define SYSBLK_SLPCK_ADC_EN_Pos (25UL) /*!< Position of  */
+#define SYSBLK_SLPCK_ADC_EN_Msk (0x1UL << SYSBLK_SLPCK_ADC_EN_Pos) /*!< Bit mask of  */
+
+/* Bit 24 : BIT_SOC_ACTCK_ADC_EN */
+#define SYSBLK_ACTCK_ADC_EN_Pos (24UL) /*!< Position of  */
+#define SYSBLK_ACTCK_ADC_EN_Msk (0x1UL << SYSBLK_ACTCK_ADC_EN_Pos) /*!< Bit mask of  */
+
+/* Bit 17 : BIT_SOC_SLPCK_SPI_3WIRE_EN */
+#define SYSBLK_SLPCK_SPI2WIRE_EN_Pos (17UL) /*!< Position of  */
+#define SYSBLK_SLPCK_SPI2WIRE_EN_Msk (0x1UL << SYSBLK_SLPCK_SPI2WIRE_EN_Pos) /*!< Bit mask of  */
+
+/* Bit 16 : BIT_SOC_ACTCK_SPI_3WIRE_EN */
+#define SYSBLK_ACTCK_SPI2WIRE_EN_Pos (16UL) /*!< Position of  */
+#define SYSBLK_ACTCK_SPI2WIRE_EN_Msk (0x1UL << SYSBLK_ACTCK_SPI2WIRE_EN_Pos) /*!< Bit mask of  */
+
+/* Bit 7 : BIT_SOC_SLPCK_KEYSCAN_EN */
+#define SYSBLK_SLPCK_KEYSCAN_EN_Pos (7UL) /*!< Position of  */
+#define SYSBLK_SLPCK_KEYSCAN_EN_Msk (0x1UL << SYSBLK_SLPCK_KEYSCAN_EN_Pos) /*!< Bit mask of  */
+
+/* Bit 6 : BIT_SOC_ACTCK_KEYSCAN_EN */
+#define SYSBLK_ACTCK_KEYSCAN_EN_Pos (6UL) /*!< Position of  */
+#define SYSBLK_ACTCK_KEYSCAN_EN_Msk (0x1UL << SYSBLK_ACTCK_KEYSCAN_EN_Pos) /*!< Bit mask of  */
+
+/* Bit 5 : BIT_SOC_SLPCK_QDECODE_EN */
+#define SYSBLK_SLPCK_QDECODE_EN_Pos (5UL) /*!< Position of  */
+#define SYSBLK_SLPCK_QDECODE_EN_Msk (0x1UL << SYSBLK_SLPCK_QDECODE_EN_Pos) /*!< Bit mask of  */
+
+/* Bit 4 : BIT_SOC_ACTCK_QDECODE_EN */
+#define SYSBLK_ACTCK_QDECODE_EN_Pos (4UL) /*!< Position of  */
+#define SYSBLK_ACTCK_QDECODE_EN_Msk (0x1UL << SYSBLK_ACTCK_QDECODE_EN_Pos) /*!< Bit mask of  */
+
+/* Bit 3 : BIT_SOC_SLPCK_I2C1_EN */
+#define SYSBLK_SLPCK_I2C1_EN_Pos (3UL) /*!< Position of  */
+#define SYSBLK_SLPCK_I2C1_EN_Msk (0x1UL << SYSBLK_SLPCK_I2C1_EN_Pos) /*!< Bit mask of  */
+
+/* Bit 2 : BIT_SOC_ACTCK_I2C1_EN */
+#define SYSBLK_ACTCK_I2C1_EN_Pos (2UL) /*!< Position of  */
+#define SYSBLK_ACTCK_I2C1_EN_Msk (0x1UL << SYSBLK_ACTCK_I2C1_EN_Pos) /*!< Bit mask of  */
+
+/* Bit 1 : BIT_SOC_SLPCK_I2C0_EN */
+#define SYSBLK_SLPCK_I2C0_EN_Pos (1UL) /*!< Position of  */
+#define SYSBLK_SLPCK_I2C0_EN_Msk (0x1UL << SYSBLK_SLPCK_I2C0_EN_Pos) /*!< Bit mask of  */
+
+/* Bit 0 : BIT_SOC_ACTCK_I2C0_EN */
+#define SYSBLK_ACTCK_I2C0_EN_Pos (0UL) /*!< Position of  */
+#define SYSBLK_ACTCK_I2C0_EN_Msk (0x1UL << SYSBLK_ACTCK_I2C0_EN_Pos) /*!< Bit mask of  */
+
+
+/* Register: REG_PESOC_COM_CLK_CTRL1 */
+/* Description: REG_PESOC_COM_CLK_CTRL1. */
+
+/* Bit 1 : BIT_SOC_SLPCK_BTBUS_EN. 1: BTBUS clock enable when CPU sleep mode */
+#define SYSBLK_SLPCK_BTBUS_EN_Pos (1UL) /*!< Position of  */
+#define SYSBLK_SLPCK_BTBUS_EN_Msk (0x1UL << SYSBLK_SLPCK_BTBUS_EN_Pos) /*!< Bit mask of  */
+
+/* Bit 0 : BIT_SOC_ACTCK_BTBUS_EN. 1: BTBUS clock enable in CPU run mode */
+#define SYSBLK_ACTCK_BTBUS_EN_Pos (0UL) /*!< Position of  */
+#define SYSBLK_ACTCK_BTBUS_EN_Msk (0x1UL << SYSBLK_ACTCK_BTBUS_EN_Pos) /*!< Bit mask of  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
diff --git a/bee/soc/inc/rtl8752h/vector_table.h b/bee/soc/inc/rtl8752h/vector_table.h
new file mode 100644
index 00000000..ec62fa33
--- /dev/null
+++ b/bee/soc/inc/rtl8752h/vector_table.h
@@ -0,0 +1,212 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef VECTOR_TABLE_H
+#define VECTOR_TABLE_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*============================================================================*
+ *                      Headers
+ *============================================================================*/
+#include "stdint.h"
+#include "stdbool.h"
+
+
+/*============================================================================*
+ *                      Types
+ *============================================================================*/
+typedef void (*IRQ_Fun)(void);       /**< ISR Handler Prototype */
+
+extern uint32_t vector_table_level_two;
+
+typedef enum
+{
+    InitialSP_VECTORn = 0,
+    Reset_VECTORn,
+    NMI_VECTORn,
+    HardFault_VECTORn,
+    RSVD_MemMang_VECTORn,
+    RSVD_BusFault_VECTORn,
+    RSVD_UsageFault_VECTORn,
+    RSVD0_VECTORn,
+    RSVD1_VECTORn,
+    RSVD2_VECTORn,
+    RSVD3_VECTORn,
+    SVC_VECTORn,
+    DebugMonitor_VECTORn,
+    RSVD4_VECTORn,
+    PendSV_VECTORn,
+    SysTick_VECTORn,
+    System_VECTORn = 16,
+    TMETER_VECTORn,
+    BTMAC_VECTORn,
+    Timer3_VECTORn,
+    Timer2_VECTORn,
+    BTMAC_WRAP_AROUND_VECTORn,
+    I2S0_TX_VECTORn,
+    I2S0_RX_VECTORn,
+    Timer4_5_VECTORn,
+    ZIGBEE_VECTORn,
+    PF_RTC_VECTORn,
+    UART0_VECTORn,
+    UART1_VECTORn,
+    I8080_VECTORn,
+    SPI0_VECTORn,
+    SPI1_VECTORn,
+    I2C0_VECTORn,
+    I2C1_VECTORn,
+    ADC_VECTORn,
+    Peripheral_VECTORn,
+    GDMA0_Channel0_VECTORn,
+    GDMA0_Channel1_VECTORn,
+    GDMA0_Channel2_VECTORn,
+    GDMA0_Channel3_VECTORn,
+    Enhanced_Timer0_VECTORn,
+    Enhanced_Timer1_VECTORn,
+    GPIO_Group3_VECTORn,
+    GPIO_Group2_VECTORn,
+    IR_VECTORn,
+    GPIO_Group1_VECTORn,
+    GPIO_Group0_VECTORn,
+    UART2_VECTORn,
+    Timer4_VECTORn,
+    Timer5_VECTORn,
+    SPIC0_VECTORn,
+    Qdecode_VECTORn,
+    Keyscan_VECTORn,
+    SPI2W_VECTORn,
+    LPCOMP_VECTORn,
+    PTA_Mailbox_VECTORn,
+    SPIC1_VECTORn,
+    SHA256_VECTORn,
+    Platform_VECTORn,
+    TRNG_VECTORn,
+    FLASH_SEC_VECTORn,
+    RTC_VECTORn,
+    WDT_VECTORn,
+} VECTORn_Type;
+
+/*============================================================================*
+ *                      Functions
+ *============================================================================*/
+/**
+ * @brief  Initialize RAM vector table to a given RAM address.
+ * @param  ram_vector_addr: RAM Vector Address.
+ * @retval TRUE Success
+ * @retval FALSE Fail
+ * @note   When using vector table relocation, the base address of the new vector
+ *         table must be aligned to the size of the vector table extended to the
+ *         next larger power of 2. In RTL8762C, the base address is aligned at 0x100.
+ */
+extern bool RamVectorTableInit(uint32_t ram_vector_addr);
+
+/**
+ * @brief  Update ISR Handler in RAM Vector Table.
+ * @param  v_num: Vector number(index)
+ * @param  isr_handler: User defined ISR Handler.
+ * @retval TRUE Success
+ * @retval FALSE Fail
+ */
+extern bool RamVectorTableUpdate(VECTORn_Type v_num, IRQ_Fun isr_handler);
+
+extern void ROM_Default_Handler(void);
+
+extern void Reset_Handler(void);
+extern void NMI_Handler(void);
+extern void HardFault_Handler(void);
+extern void SVC_Handler(void);
+extern void DebugMon_Handler(void);
+extern void PendSV_Handler(void);
+extern void SysTick_Handler(void);
+extern void System_Handler(void);
+extern void TMETER_Handler(void);
+extern void BTMAC_Handler(void);
+extern void Timer3_Handler(void);
+extern void Timer2_Handler(void);
+extern void BTMAC_WRAP_AROUND_Handler(void);
+extern void I2S0_TX_Handler(void);
+extern void I2S0_RX_Handler(void);
+extern void Timer4_5_Handler(void);
+extern void ZIGBEE_Handler(void);
+extern void PF_RTC_Handler(void);
+extern void UART0_Handler(void);
+extern void UART1_Handler(void);
+extern void I8080_Handler(void);
+extern void SPI0_Handler(void);
+extern void SPI1_Handler(void);
+extern void I2C0_Handler(void);
+extern void I2C1_Handler(void);
+extern void ADC_Handler(void);
+extern void Peripheral_Handler(void);
+extern void GDMA0_Channel0_Handler(void);
+extern void GDMA0_Channel1_Handler(void);
+extern void GDMA0_Channel2_Handler(void);
+extern void GDMA0_Channel3_Handler(void);
+extern void Enhanced_Timer0_Handler(void);
+extern void Enhanced_Timer1_Handler(void);
+extern void GPIO_Group3_Handler(void);
+extern void GPIO_Group2_Handler(void);
+extern void IR_Handler(void);
+extern void GPIO_Group1_Handler(void);
+extern void GPIO_Group0_Handler(void);
+extern void UART2_Handler(void);
+extern void Timer4_Handler(void);
+extern void Timer5_Handler(void);
+extern void SPIC0_Handler(void);
+extern void Qdecode_Handler(void);
+extern void Keyscan_Handler(void);
+extern void SPI2W_Handler(void);
+extern void LPCOMP_Handler(void);
+extern void PTA_Mailbox_Handler(void);
+extern void SPIC1_Handler(void);
+extern void SHA256_Handler(void);
+extern void Platform_Handler(void);
+extern void TRNG_Handler(void);
+extern void FLASH_SEC_Handler(void);
+extern void RTC_Handler(void);
+extern void WDT_Handler(void);
+
+extern void GPIO0_Handler(void);
+extern void GPIO1_Handler(void);
+extern void GPIO2_Handler(void);
+extern void GPIO3_Handler(void);
+extern void GPIO4_Handler(void);
+extern void GPIO5_Handler(void);
+extern void GPIO6_Handler(void);
+extern void GPIO7_Handler(void);
+extern void GPIO8_Handler(void);
+extern void GPIO9_Handler(void);
+extern void GPIO10_Handler(void);
+extern void GPIO11_Handler(void);
+extern void GPIO12_Handler(void);
+extern void GPIO13_Handler(void);
+extern void GPIO14_Handler(void);
+extern void GPIO15_Handler(void);
+extern void GPIO16_Handler(void);
+extern void GPIO17_Handler(void);
+extern void GPIO18_Handler(void);
+extern void GPIO19_Handler(void);
+extern void GPIO20_Handler(void);
+extern void GPIO21_Handler(void);
+extern void GPIO22_Handler(void);
+extern void GPIO23_Handler(void);
+extern void GPIO24_Handler(void);
+extern void GPIO25_Handler(void);
+extern void GPIO26_Handler(void);
+extern void GPIO27_Handler(void);
+extern void GPIO28_Handler(void);
+extern void GPIO29_Handler(void);
+extern void GPIO30_Handler(void);
+extern void GPIO31_Handler(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* VECTOR_TABLE_H */
diff --git a/bee/soc/inc/rtl87x2g/CMakeLists.txt b/bee/soc/inc/rtl87x2g/CMakeLists.txt
new file mode 100644
index 00000000..6bd996bb
--- /dev/null
+++ b/bee/soc/inc/rtl87x2g/CMakeLists.txt
@@ -0,0 +1,4 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+zephyr_include_directories(.)
+zephyr_include_directories(non_secure)
diff --git a/bee/soc/inc/rtl87x2g/aon_reg.h b/bee/soc/inc/rtl87x2g/aon_reg.h
new file mode 100644
index 00000000..24ec86ce
--- /dev/null
+++ b/bee/soc/inc/rtl87x2g/aon_reg.h
@@ -0,0 +1,9146 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _AON_REG_H
+#define _AON_REG_H
+#include <stdint.h>
+
+/* Auto gen based on RL6920_B_Cut_AON_Autogen_table_2023_0612_V1.xlsx */
+#define AON_FAST_BOOT                   0x400
+#define AON_FAST_REBOOT_SW_INFO0        0x404
+#define AON_REG4X_FW_GENERAL            0x408
+#define AON_DEBUG_PASSWORD              0x40C   // 0x40C ~ 0x41B store the debug password
+#define AON_REG8X_FW_GENERAL            0x410
+#define AON_REG10X_FW_GENERAL           0x414
+#define AON_REG12X_FW_GENERAL           0x418
+#define AON_REG20X_FW_GENERAL           0x428
+#define AON_REG22X_FW_GENERAL           0x42C
+#define AON_REG0X_FUNC_DIS              0x460
+#define AON_REG0X_SAF                   0x464
+#define AON_REG1X_SAF                   0x468
+#define AON_REG0X_SC                    0x46C
+#define AON_REG0X_KM4_DBG_CTRL          0x470
+#define AON_RTC_PF_COMP_CONTROLLER_REG  0x4B0
+#define AON_RTC_PF_COMP0_REG            0x4B4
+#define AON_RTC_PF_COMP1_REG            0x4B8
+#define AON_RTC_PF_COMP2_REG            0x4BC
+#define AON_RTC_PF_COMP3_REG            0x4C0
+#define AON_RTC_PF_COMP_MANUAL_INT_REG  0x4C4
+#define AON_RTC_PF_CNT_REG              0x4C8
+#define AON_RTC_PF_COMP_INT_WK_CLR_REG  0x4CC
+#define AON_RTC_PF_COMP_INT_WK_SR_REG   0x4D0
+#define AON_RTC_PF_RTL_VERSION_REG      0x4D4
+#define AON_BT_MAC_VSEL                 0x580
+#define AON_BT_MAC_SNPS_HV_LV           0x584
+#define AON_BT_MAC_1024x16_PWR          0x588
+#define AON_BT_MAC_512x16_PWR           0x58C
+#define AON_BT_MAC_128x32_0_PWR         0x590
+#define AON_BT_MAC_128x32_1_PWR         0x594
+#define AON_BT_MAC_640x32_HV_LV         0x598
+#define AON_BT_MAC_640x32_PWR           0x59C
+#define AON_BT_MAC_96x32_HV_LV          0x5A0
+#define AON_BT_MAC_96x32_PWR            0x5A4
+#define AON_BT_MAC_64x32_HV_LV          0x5A8
+#define AON_BT_MAC_64x32_PWR            0x5AC
+#define AON_ZB_MAC_VSEL                 0x5B0
+#define AON_ZB_MAC_HV_LV                0x5B4
+#define AON_ZB_MAC_16x32_PWR            0x5B8
+#define AON_ZB_MAC_40x32_PWR            0x5BC
+#define AON_ZB_MAC_32x32_PWR            0x5C0
+#define AON_BT_PHY_VSEL                 0x5C4
+#define AON_BT_PHY_HV_LV                0x5C8
+#define AON_BT_PHY_128x12x4_PWR         0x5CC
+#define AON_BT_PHY_LR_RAM_PWR           0x5D0
+#define AON_KM4_VSEL                    0x5D4
+#define AON_KM4_ITCM0_HV_LV             0x5D8
+#define AON_KM4_ITCM0_LS                0x5DC
+#define AON_KM4_TCM_HV_LV               0x5E0
+#define AON_KM4_ITCM1_PWR_0             0x5E4
+#define AON_KM4_ITCM1_PWR_1             0x5E8
+#define AON_KM4_DTCM0_PWR               0x5EC
+#define AON_KM4_DTCM1_PWR               0x5F0
+#define AON_KM4_IC_DATA_HV_LV           0x5F4
+#define AON_KM4_IC_DATA_PWR             0x5F8
+#define AON_KM4_IC_TAG_HV_LV            0x5FC
+#define AON_KM4_IC_TAG_PWR              0x600
+#define AON_KM4_DC_DATA_HV_LV           0x604
+#define AON_KM4_DC_DATA_PWR             0x608
+#define AON_KM4_DC_TAG_HV_LV            0x60C
+#define AON_KM4_DC_TAG_PWR              0x610
+#define AON_BUFFER_RAM_VSEL             0x614
+#define AON_BUFFER_RAM_HV_LV            0x618
+#define AON_BUFFER_RAM_PWR              0x61C
+#define AON_DATA_RAM_VSEL               0x620
+#define AON_DATA_RAM_HV_LV              0x624
+#define AON_DATA_RAM_PWR                0x628
+#define AON_USB_VSEL                    0x62C
+#define AON_USB_HV_LV                   0x630
+#define AON_USB_PWR                     0x634
+#define AON_SDIO_RAM_PWR                0x638
+#define AON_DISPLAY_128x32_PWR          0x63C
+#define AON_DISPLAY_672x24_PWR          0x640
+#define AON_GMAC_PWR                    0x644
+#define AON_PKE_ROM_HV                  0x648
+#define AON_PKE_ROM_PWR                 0x64C
+#define AON_PKE_MMEM_PWR                0x650
+#define AON_PKE_TMEM_PWR                0x654
+#define AON_AUDIO_VSEL                  0x658
+#define AON_AUDIO_HV_LV                 0x65C
+#define AON_AUDIO_AD_PWR                0x660
+#define AON_AUDIO_DA_PWR                0x664
+#define AON_CAN_VSEL                    0x668
+#define AON_CAN_HV_LV                   0x66C
+#define AON_CAN_PWR                     0x670
+#define AON_REG0X_SYS                   0x800
+#define AON_REG1X_SYS                   0x804
+#define AON_REG2X_SYS                   0x808
+#define AON_REG3X_SYS                   0x80C
+#define AON_REG4X_SYS                   0x810
+#define AON_REG5X_SYS                   0x814
+#define AON_REG6X_SYS                   0x818
+#define AON_REG7X_SYS                   0x81C
+#define AON_REG8X_SYS                   0x820
+#define AON_REG9X_SYS                   0x824
+#define AON_REG10X_SYS                  0x828
+#define AON_REG0X_EFUSE                 0x82C
+#define AON_REG0X_XPDCK                 0x830
+#define AON_REG0X_PWM_POS               0x834
+#define AON_REG0X_PFM_POS               0x838
+#define AON_REG0X_300K                  0x83C
+#define AON_REG1X_300K                  0x840
+#define AON_AON_READ_RG0X               0x844
+#define AON_AON_READ_RG1X               0x848
+#define AON_AON_READ_RG2X               0x84C
+#define AON_AON_READ_RG3X               0x850
+#define AON_AON_READ_RG4X               0x854
+#define AON_AON_READ_RG5X               0x858
+#define AON_AON_READ_RG6X               0x85C
+#define AON_AON_READ_RG7X               0x860
+#define AON_AON_READ_RG8X               0x864
+#define AON_AON_READ_RG9X               0x868
+#define AON_AON_READ_RG10X              0x86C
+#define AON_AON_READ_RG11X              0x870
+#define AON_AON_READ_RG12X              0x874
+#define AON_AON_READ_RG13X              0x878
+#define AON_AON_READ_RG14X              0x87C
+#define AON_AON_READ_RG15X              0x880
+#define AON_AON_READ_RG16X              0x884
+#define AON_LOP_RG0X                    0xAB0
+#define AON_LOP_RG1X                    0xAB4
+#define AON_LOP_RG2X                    0xAB8
+#define AON_LOP_RG3X                    0xABC
+#define AON_LOP_RG4X                    0xAC0
+#define AON_LOP_RG5X                    0xAC4
+#define AON_LOP_RG6X                    0xAC8
+#define AON_LOP_RG7X                    0xACC
+#define AON_LOP_RG8X                    0xAD0
+#define AON_LOP_RG9X                    0xAD4
+#define AON_LOP_RG10X                   0xAD8
+#define AON_REG0X_MBIAS                 0xC00
+#define AON_REG2X_MBIAS                 0xC04
+#define AON_C_KOUT0X_MBIAS              0xC08
+#define AON_REG0X_LDO                   0xC10
+#define AON_REG2X_LDO                   0xC14
+#define AON_REG0X_LCD                   0xC18
+#define AON_REG0X_BUCK                  0xC20
+#define AON_REG2X_BUCK                  0xC24
+#define AON_REG4X_BUCK                  0xC28
+#define AON_REG6X_BUCK                  0xC2C
+#define AON_REG8X_BUCK                  0xC30
+#define AON_C_KOUT0X_BUCK               0xC34
+#define AON_REG0X_32KXTAL               0xC80
+#define AON_REG2X_32KXTAL               0xC84
+#define AON_REG0X_32KOSC                0xC88
+#define AON_REG_POW                     0xC8C
+#define AON_REG0X_40MOSC                0xC90
+#define AON_REG0X_RCAL                  0xC94
+#define AON_BT_ANAPAR_XTAL_mode         0xCA0
+#define AON_BT_ANAPAR_XTAL0             0xCA4
+#define AON_BT_ANAPAR_XTAL2             0xCA8
+#define AON_BT_ANAPAR_XTAL4             0xCAC
+#define AON_BT_ANAPAR_XTAL6             0xCB0
+#define AON_BT_ANAPAR_XTAL8             0xCB4
+#define AON_BT_ANAPAR_XTAL10            0xCB8
+#define AON_BT_ANAPAR_XTAL12            0xCBC
+#define AON_BT_ANAPAR_XTAL14            0xCC0
+#define AON_BT_ANAPAR_XTAL16            0xCC4
+#define AON_REG0X_XTAL                  0xCC8
+#define AON_REG1X_XTAL                  0xCCC
+#define AON_REG0X_BT_ANAPAR_LDO         0xCD0
+#define AON_REG0X_RF_LDO318             0xCD4
+#define AON_REG0X_LDO_PLL1              0xD00
+#define AON_REG_USB_POWER_CTL           0xD40
+#define AON_REG_USB_CLK_CTL             0xD44
+#define AON_REG_XTAL0                   0xD60
+#define AON_REG_XTAL1                   0xD64
+#define AON_REG0X_PLL1                  0xD80
+#define AON_REG2X_PLL1                  0xD84
+#define AON_REG0X_PLL2                  0xD88
+#define AON_REG2X_PLL2                  0xD8C
+#define AON_REG4X_PLL2                  0xD90
+#define AON_RO_PLL                      0xD94
+#define AON_NS_RTC_CR0                  0x1800
+#define AON_NS_RTC_INT_clear            0x1804
+#define AON_NS_RTC_INT_SR               0x1808
+#define AON_NS_RTC_PRESCALER0           0x180C
+#define AON_NS_RTC_COMP_0               0x1810
+#define AON_NS_RTC_COMP_1               0x1814
+#define AON_NS_RTC_COMP_2               0x1818
+#define AON_NS_RTC_COMP_3               0x181C
+#define AON_NS_RTC_COMP0_GT             0x1820
+#define AON_NS_RTC_COMP1_GT             0x1824
+#define AON_NS_RTC_COMP2_GT             0x1828
+#define AON_NS_RTC_COMP3_GT             0x182C
+#define AON_NS_RTC_CNT0                 0x1830
+#define AON_NS_RTC_PRESCALE_CNT0        0x1834
+#define AON_NS_RTC_PRESCALE_CMP0        0x1838
+#define AON_NS_RTC_BACKUP_REG           0x183C
+#define AON_NS_RTC_RTL_VERSION0         0x1840
+#define AON_NS_LPC0_CR0                 0x1850
+#define AON_NS_LPC0_SR                  0x1854
+#define AON_NS_LPC0_MBIAS               0x1858
+#define AON_NS_P0_0_P0_1_PAD_CFG        0x1900
+#define AON_NS_P0_2_P0_3_PAD_CFG        0x1904
+#define AON_NS_P0_4_P0_5_PAD_CFG        0x1908
+#define AON_NS_P0_6_P0_7_PAD_CFG        0x190C
+#define AON_NS_P1_0_P1_1_PAD_CFG        0x1910
+#define AON_NS_P1_2_P1_3_PAD_CFG        0x1914
+#define AON_NS_P1_4_P1_5_PAD_CFG        0x1918
+#define AON_NS_P1_6_P1_7_PAD_CFG        0x191C
+#define AON_NS_P2_0_P2_1_PAD_CFG        0x1920
+#define AON_NS_P2_2_P2_3_PAD_CFG        0x1924
+#define AON_NS_P2_4_P2_5_PAD_CFG        0x1928
+#define AON_NS_P2_6_P2_7_PAD_CFG        0x192C
+#define AON_NS_P3_0_P3_1_PAD_CFG        0x1930
+#define AON_NS_P3_2_P3_3_PAD_CFG        0x1934
+#define AON_NS_P3_4_P3_5_PAD_CFG        0x1938
+#define AON_NS_P3_6_P3_7_PAD_CFG        0x193C
+#define AON_NS_P4_0_P4_1_PAD_CFG        0x1940
+#define AON_NS_P4_2_P4_3_PAD_CFG        0x1944
+#define AON_NS_P32K_XI_P32K_XO_PAD_CFG  0x1948
+#define AON_NS_P_MICBIAS_PAD_CFG        0x194C
+#define AON_NS_COMMON_PAD_CFG           0x1950
+#define AON_NS_P_SPI_PAD_CFG            0x1954
+#define AON_NS_DAC_P_DAC_N_PAD_CFG      0x1958
+#define AON_NS_P4_4_P4_5_PAD_CFG        0x195C
+#define AON_NS_P4_6_P4_7_PAD_CFG        0x1960
+#define AON_NS_P5_0_P5_1_PAD_CFG        0x1964
+#define AON_NS_P5_2_P5_3_PAD_CFG        0x1968
+#define AON_NS_P5_4_P5_5_PAD_CFG        0x196C
+#define AON_NS_P5_6_P5_7_PAD_CFG        0x1970
+#define AON_NS_P6_0_P6_1_PAD_CFG        0x1974
+#define AON_NS_P6_2_P6_3_PAD_CFG        0x1978
+#define AON_NS_P6_4_P6_5_PAD_CFG        0x197C
+#define AON_NS_P6_6_P6_7_PAD_CFG        0x1980
+#define AON_NS_P7_0_P7_1_PAD_CFG        0x1984
+#define AON_NS_P7_2_P7_3_PAD_CFG        0x1988
+#define AON_NS_P7_4_P7_5_PAD_CFG        0x198C
+#define AON_NS_P7_6_P7_7_PAD_CFG        0x1990
+#define AON_NS_SPIC0_PAD_CFG0           0x1994
+#define AON_NS_SPIC0_PAD_CFG1           0x1998
+#define AON_NS_SPIC0_PAD_CFG2           0x199C
+#define AON_NS_P8_0_P8_1_PAD_CFG        0x19A0
+#define AON_NS_P8_2_P8_3_PAD_CFG        0x19A4
+#define AON_NS_P8_4_P8_5_PAD_CFG        0x19A8
+#define AON_NS_P8_6_P8_7_PAD_CFG        0x19AC
+#define AON_NS_P9_0_P9_1_PAD_CFG        0x19B0
+#define AON_NS_P9_2_P9_3_PAD_CFG        0x19B4
+#define AON_NS_P9_4_P9_5_PAD_CFG        0x19B8
+#define AON_NS_P9_6_P9_7_PAD_CFG        0x19BC
+#define AON_NS_P10_0_P10_1_PAD_CFG      0x19C0
+#define AON_NS_P10_2_P10_3_PAD_CFG      0x19C4
+#define AON_NS_PAD_E3_CFG               0x19C8
+#define AON_NS_PAD_Status_0             0x1AA0
+#define AON_NS_PAD_Status_1             0x1AA4
+#define AON_NS_PAD_Status_2             0x1AA8
+#define AON_NS_REG0X_DEBIO              0x1AAC
+#define AON_NS_PAD_Status_3             0x1AB0
+#define AON_NS_REG0X_APP                0x1AE0
+#define AON_NS_REG1X_APP                0x1AE4
+#define AON_NS_REG2X_APP                0x1AE8
+#define AON_NS_REG3X_APP                0x1AEC
+#define AON_NS_REG4X_APP                0x1AF0
+#define AON_NS_REG5X_APP                0x1AF4
+#define AON_NS_REG6X_APP                0x1AF8
+#define AON_NS_REG7X_APP                0x1AFC
+#define AON_NS_REG8X_APP                0x1B00
+#define AON_NS_REG9X_APP                0x1B04
+#define AON_NS_REG10X_APP               0x1B08
+#define AON_NS_REG11X_APP               0x1B0C
+#define AON_NS_REG12X_APP               0x1B10
+#define AON_NS_REG13X_APP               0x1B14
+#define AON_NS_REG14X_APP               0x1B18
+#define AON_NS_REG15X_APP               0x1B1C
+#define AON_NS_AON_WDG_WP0              0x1B60
+#define AON_NS_AON_WDG_CONFIG           0x1B64
+#define AON_NS_AON_WDG_CNT_RESET0       0x1B68
+#define AON_NS_AON_WDG_SEC_CTL          0x1B6C
+#define AON_NS_REG0X_LDO                0x1B90
+#define AON_NS_REG0X_AUX_V09            0x1B94
+#define AON_NS_REG0X_SD                 0x1B98
+#define AON_NS_REG_CONFIG               0x1BD0
+#define AON_NS_REG_SR_X                 0x1BD4
+#define AON_NS_INT_CLR                  0x1BD8
+#define AON_NS_REG30_CORE_KM4_PC        0x1C00
+#define AON_NS_REG34_CORE_KM4_LR        0x1C04
+#define AON_NS_REG38_CORE_KM4_PC_EX     0x1C08
+#define AON_NS_REG3C_CORE_KM4_XPSR_R    0x1C0C
+#define AON_NS_REG40_CORE_KM4_MSP_S     0x1C10
+#define AON_NS_REG44_CORE_KM4_PSP_S     0x1C14
+#define AON_NS_REG48_CORE_KM4_MSP_NS    0x1C18
+#define AON_NS_REG4C_CORE_KM4_PSP_NS    0x1C1C
+#define AON_NS_REG50_AON_KM4_PC         0x1C20
+#define AON_NS_REG54_AON_KM4_LR         0x1C24
+#define AON_NS_REG58_AON_KM4_PC_EX      0x1C28
+#define AON_NS_REG5C_AON_KM4_XPSR_R     0x1C2C
+#define AON_NS_REG60_AON_KM4_MSP_S      0x1C30
+#define AON_NS_REG64_AON_KM4_PSP_S      0x1C34
+#define AON_NS_REG68_AON_KM4_MSP_NS     0x1C38
+#define AON_NS_REG6C_AON_KM4_PSP_NS     0x1C3C
+#define AON_NS_REG_AON_WDT_MODE         0x1C40
+#define AON_NS_REG_KM4_WDT_MODE         0x1C44
+#define AON_NS_REG0X_FW_GENERAL_NS      0x1D00
+#define AON_NS_REG2X_FW_GENERAL_NS      0x1D04
+#define AON_NS_REG4X_FW_GENERAL_NS      0x1D08
+#define AON_NS_REG6X_FW_GENERAL_NS      0x1D0C
+#define AON_NS_REG8X_FW_GENERAL_NS      0x1D10
+#define AON_NS_REG10X_FW_GENERAL_NS     0x1D14
+#define AON_NS_P3_P1_PAD_E_LCD_CFG      0x1D80
+#define AON_NS_P7_P4_PAD_E_LCD_CFG      0x1D84
+#define AON_NS_P11_P8_PAD_E_LCD_CFG     0x1D88
+#define AON_NS_P3_P1_PAD_SHDN_LCD_CFG   0x1D8C
+#define AON_NS_P7_P4_PAD_SHDN_LCD_CFG   0x1D90
+#define AON_NS_P11_P8_PAD_SHDN_LCD_CFG  0x1D94
+#define AON_NS_REG0X_SDADC_LDO          0x1DC0
+/* 0x400    0x4000_0400
+    15:0    R/W FW_GENERAL_REG0X                        16'h0
+    31:16   R/W FW_GENERAL_REG1X                        16'h0
+ */
+typedef volatile union _AON_FAST_BOOT_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t FW_GENERAL_REG0X: 16;
+        uint32_t FW_GENERAL_REG1X: 16;
+    };
+} AON_FAST_BOOT_TYPE;
+
+/* 0x404    0x4000_0404
+    15:0    R/W FW_GENERAL_REG2X                        16'h0
+    31:16   R/W FW_GENERAL_REG3X                        16'h0
+ */
+typedef volatile union _AON_FAST_REBOOT_SW_INFO0_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t FW_GENERAL_REG2X: 16;
+        uint32_t FW_GENERAL_REG3X: 16;
+    };
+} AON_FAST_REBOOT_SW_INFO0_TYPE;
+
+/* 0x408    0x4000_0408
+    15:0    R/W FW_GENERAL_REG4X                        16'h0
+    31:16   R/W FW_GENERAL_REG5X                        16'h0
+ */
+typedef volatile union _AON_REG4X_FW_GENERAL_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t ota_valid: 1;                  /* bit[0]: ota valid */
+        uint32_t is_rom_code_patch: 1;          /* bit[1]: is rom code patch ? */
+        uint32_t is_fw_trig_wdg_to: 1;          /* bit[2]: does fw trigger watchdog timeout ? */
+        uint32_t is_send_patch_end_evt: 1;      /* bit[3]: does we send patch end event ? */
+        uint32_t rsvd: 2;                       /* bit[5:4]: reserved */
+        uint32_t is_airplane_mode : 1;          /* bit[6]: is airplane mode ? */
+        uint32_t REBOOT_SW_INFO1: 6;            /* bit[12:7] for AON_FAST_REBOOT_SW_INFO1 */
+        uint32_t is_password_mpl_cmd: 1;
+        uint32_t reg_aon_hwspi_en: 1;
+        uint32_t reg_aon_debug_port: 1;
+        uint32_t FW_GENERAL_REG5X: 16;
+    };
+} AON_REG4X_FW_GENERAL_TYPE;
+
+/* 0x40C    0x4000_040c
+    15:0    R/W freg2                        16'h0
+    31:16   R/W freg3                        16'h0
+ */
+typedef volatile union _AON_DEBUG_PASSWORD_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t freg2: 16;
+        uint32_t freg3: 16;
+    };
+} AON_DEBUG_PASSWORD_TYPE;
+
+/* 0x410    0x4000_0410
+    15:0    R/W FW_GENERAL_REG8X                        16'h0
+    31:16   R/W FW_GENERAL_REG9X                        16'h0
+ */
+typedef volatile union _AON_REG8X_FW_GENERAL_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t FW_GENERAL_REG8X: 16;
+        uint32_t FW_GENERAL_REG9X: 16;
+    };
+} AON_REG8X_FW_GENERAL_TYPE;
+
+/* 0x414    0x4000_0414
+    15:0    R/W FW_GENERAL_REG10X                       16'h0
+    31:16   R/W FW_GENERAL_REG11X                       16'h0
+ */
+typedef volatile union _AON_REG10X_FW_GENERAL_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t FW_GENERAL_REG10X: 16;
+        uint32_t FW_GENERAL_REG11X: 16;
+    };
+} AON_REG10X_FW_GENERAL_TYPE;
+
+/* 0x418    0x4000_0418
+    15:0    R/W FW_GENERAL_REG12X                       16'h0
+    31:16   R/W FW_GENERAL_REG13X                       16'h0
+ */
+typedef volatile union _AON_REG12X_FW_GENERAL_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t FW_GENERAL_REG12X: 16;
+        uint32_t FW_GENERAL_REG13X: 16;
+    };
+} AON_REG12X_FW_GENERAL_TYPE;
+
+/* 0x428    0x4000_0428
+    15:0    R/W FW_GENERAL_REG20X                       16'h0
+    31:16   R/W FW_GENERAL_REG21X                       16'h0
+ */
+typedef volatile union _AON_REG20X_FW_GENERAL_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t FW_GENERAL_REG20X: 16;
+        uint32_t FW_GENERAL_REG21X: 16;
+    };
+} AON_REG20X_FW_GENERAL_TYPE;
+
+/* 0x42C    0x4000_042c
+    15:0    R/W FW_GENERAL_REG22X                       16'h0
+    31:16   R/W FW_GENERAL_REG23X                       16'h0
+ */
+typedef volatile union _AON_REG22X_FW_GENERAL_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t FW_GENERAL_REG22X: 16;
+        uint32_t FW_GENERAL_REG23X: 16;
+    };
+} AON_REG22X_FW_GENERAL_TYPE;
+
+/* 0x460    0x4000_0460
+    0       W1O reg_aon_w1o_dumm0                       1'b0
+    1       W1O reg_aon_w1o_dumm1                       1'b0
+    2       W1O reg_rom_trace_prot                      1'h0
+    3       W1O reg_aon_w1o_pn_cfo_comp_dis             1'h0
+    4       W1O reg_aon_w1o_detail_rxrpt_dis            1'h0
+    5       W1O reg_aon_w1o_detail_rxrpt_cfoe_dis       1'h0
+    6       W1O reg_aon_w1o_pa_func_dis                 1'h0
+    7       W1O reg_aon_w1o_cis_func_dis                1'h0
+    8       W1O reg_aon_w1o_bis_func_dis                1'h0
+    31:9    R   RSVD                                    23'b0
+ */
+typedef volatile union _AON_REG0X_FUNC_DIS_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t reg_aon_w1o_dumm0: 1;
+        uint32_t reg_aon_w1o_dumm1: 1;
+        uint32_t reg_rom_trace_prot: 1;
+        uint32_t reg_aon_w1o_pn_cfo_comp_dis: 1;
+        uint32_t reg_aon_w1o_detail_rxrpt_dis: 1;
+        uint32_t reg_aon_w1o_detail_rxrpt_cfoe_dis: 1;
+        uint32_t reg_aon_w1o_pa_func_dis: 1;
+        uint32_t reg_aon_w1o_cis_func_dis: 1;
+        uint32_t reg_aon_w1o_bis_func_dis: 1;
+        uint32_t RSVD: 23;
+    };
+} AON_REG0X_FUNC_DIS_TYPE;
+
+/* 0x464    0x4000_0464
+    0       R/W saf_aon_nonsec_slave                    1'b1                    !saf_nonsec_slave_lock
+    1       R/W saf_peri_on_nonsec_slave                1'b1                    !saf_nonsec_slave_lock
+    2       R/W saf_soc_vendor_reg_nonsec_slave         1'b1                    !saf_nonsec_slave_lock
+    3       R/W saf_ir_rc_nonsec_slave                  1'b1                    !saf_nonsec_slave_lock
+    4       R/W saf_qdec_nonsec_slave                   1'b1                    !saf_nonsec_slave_lock
+    5       R/W saf_gmac_ctrl_nonsec_slave              1'b1                    !saf_nonsec_slave_lock
+    6       R/W saf_spic0_nonsec_slave                  1'b1                    !saf_nonsec_slave_lock
+    7       R/W saf_spic1_nonsec_slave                  1'b1                    !saf_nonsec_slave_lock
+    8       R/W saf_spic2_nonsec_slave                  1'b1                    !saf_nonsec_slave_lock
+    9       R/W saf_spi0_nonsec_slave                   1'b1                    !saf_nonsec_slave_lock
+    10      R/W saf_spi1_nonsec_slave                   1'b1                    !saf_nonsec_slave_lock
+    11      R/W saf_spi_slave_nonsec_slave              1'b1                    !saf_nonsec_slave_lock
+    12      R/W saf_rtzip_nonsec_slave                  1'b1                    !saf_nonsec_slave_lock
+    13      R/W saf_enhanced_timer_nonsec_slave         1'b1                    !saf_nonsec_slave_lock
+    14      R/W saf_modemrfcpi_nonsec_slave             1'b1                    !saf_nonsec_slave_lock
+    15      R/W saf_usb_otg_cfg_nonsec_slave            1'b1                    !saf_nonsec_slave_lock
+    16      R/W saf_i2s0_nonsec_slave                   1'b1                    !saf_nonsec_slave_lock
+    17      R/W saf_i2s1_nonsec_slave                   1'b1                    !saf_nonsec_slave_lock
+    18      R/W saf_spi_codec_nonsec_slave              1'b1                    !saf_nonsec_slave_lock
+    19      R/W saf_display_ctrl_nonsec_slave           1'b1                    !saf_nonsec_slave_lock
+    20      R/W saf_iso7816_nonsec_slave                1'b1                    !saf_nonsec_slave_lock
+    21      R/W saf_segcom_ctl_nonsec_slave             1'b1                    !saf_nonsec_slave_lock
+    22      R/W saf_bluewiz_nonsec_slave                1'b1                    !saf_nonsec_slave_lock
+    23      R/W saf_bt_vendor_reg_nonsec_slave          1'b1                    !saf_nonsec_slave_lock
+    24      R/W saf_zigbee_nonsec_slave                 1'b1                    !saf_nonsec_slave_lock
+    25      R/W saf_sdio_host0_cfg_nonsec_slave         1'b1                    !saf_nonsec_slave_lock
+    26      R/W saf_gpioa_nonsec_slave                  1'b1                    !saf_nonsec_slave_lock
+    27      R/W saf_gpiob_nonsec_slave                  1'b1                    !saf_nonsec_slave_lock
+    28      R/W saf_timer_nonsec_slave                  1'b1                    !saf_nonsec_slave_lock
+    29      R/W saf_sar_adc_nonsec_slave                1'b1                    !saf_nonsec_slave_lock
+    30      R/W saf_adc_24bit_nonsec_slave              1'b1                    !saf_nonsec_slave_lock
+    31      R/W saf_spi_3wire_nonsec_slave              1'b1                    !saf_nonsec_slave_lock
+ */
+typedef volatile union _AON_REG0X_SAF_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t saf_aon_nonsec_slave: 1;
+        uint32_t saf_peri_on_nonsec_slave: 1;
+        uint32_t saf_soc_vendor_reg_nonsec_slave: 1;
+        uint32_t saf_ir_rc_nonsec_slave: 1;
+        uint32_t saf_qdec_nonsec_slave: 1;
+        uint32_t saf_gmac_ctrl_nonsec_slave: 1;
+        uint32_t saf_spic0_nonsec_slave: 1;
+        uint32_t saf_spic1_nonsec_slave: 1;
+        uint32_t saf_spic2_nonsec_slave: 1;
+        uint32_t saf_spi0_nonsec_slave: 1;
+        uint32_t saf_spi1_nonsec_slave: 1;
+        uint32_t saf_spi_slave_nonsec_slave: 1;
+        uint32_t saf_rtzip_nonsec_slave: 1;
+        uint32_t saf_enhanced_timer_nonsec_slave: 1;
+        uint32_t saf_modemrfcpi_nonsec_slave: 1;
+        uint32_t saf_usb_otg_cfg_nonsec_slave: 1;
+        uint32_t saf_i2s0_nonsec_slave: 1;
+        uint32_t saf_i2s1_nonsec_slave: 1;
+        uint32_t saf_spi_codec_nonsec_slave: 1;
+        uint32_t saf_display_ctrl_nonsec_slave: 1;
+        uint32_t saf_iso7816_nonsec_slave: 1;
+        uint32_t saf_segcom_ctl_nonsec_slave: 1;
+        uint32_t saf_bluewiz_nonsec_slave: 1;
+        uint32_t saf_bt_vendor_reg_nonsec_slave: 1;
+        uint32_t saf_zigbee_nonsec_slave: 1;
+        uint32_t saf_sdio_host0_cfg_nonsec_slave: 1;
+        uint32_t saf_gpioa_nonsec_slave: 1;
+        uint32_t saf_gpiob_nonsec_slave: 1;
+        uint32_t saf_timer_nonsec_slave: 1;
+        uint32_t saf_sar_adc_nonsec_slave: 1;
+        uint32_t saf_adc_24bit_nonsec_slave: 1;
+        uint32_t saf_spi_3wire_nonsec_slave: 1;
+    };
+} AON_REG0X_SAF_TYPE;
+
+/* 0x468    0x4000_0468
+    0       R/W saf_uart0_nonsec_slave                  1'b1                    !saf_nonsec_slave_lock
+    1       R/W saf_uart1_nonsec_slave                  1'b1                    !saf_nonsec_slave_lock
+    2       R/W saf_uart2_nonsec_slave                  1'b1                    !saf_nonsec_slave_lock
+    3       R/W saf_uart3_nonsec_slave                  1'b1                    !saf_nonsec_slave_lock
+    4       R/W saf_i2c0_nonsec_slave                   1'b1                    !saf_nonsec_slave_lock
+    5       R/W saf_i2c1_nonsec_slave                   1'b1                    !saf_nonsec_slave_lock
+    6       R/W saf_key_scan_nonsec_slave               1'b1                    !saf_nonsec_slave_lock
+    7       R/W saf_public_key_engine_nonsec_slave      1'b1                    !saf_nonsec_slave_lock
+    8       R/W saf_flash_sec_nonsec_slave              1'b1                    !saf_nonsec_slave_lock
+    9       R/W saf_aes_nonsec_slave                    1'b1                    !saf_nonsec_slave_lock
+    10      R/W saf_sha256_nonsec_slave                 1'b1                    !saf_nonsec_slave_lock
+    11      R/W saf_trng_nonsec_slave                   1'b1                    !saf_nonsec_slave_lock
+    12      R/W saf_efuse_controller_nonsec_slave       1'b1                    !saf_nonsec_slave_lock
+    13      R/W saf_spi0_hs_nonsec_slave                1'b1                    !saf_nonsec_slave_lock
+    14      R/W saf_rxi350_dmac_cfg_nonsec_slave        1'b1                    !saf_nonsec_slave_lock
+    15      R/W saf_ppe_cfg_nonsec_slave                1'b1                    !saf_nonsec_slave_lock
+    16      R/W saf_can_nonsec_slave                    1'b1                    !saf_nonsec_slave_lock
+    17      R/W saf_spic_phy_nonsec_slave               1'b1                    !saf_nonsec_slave_lock
+    18      R/W saf_i2c2_nonsec_slave                   1'b1                    !saf_nonsec_slave_lock
+    19      R/W saf_i2c3_nonsec_slave                   1'b1                    !saf_nonsec_slave_lock
+    20      R/W saf_uart4_nonsec_slave                  1'b1                    !saf_nonsec_slave_lock
+    21      R/W saf_uart5_nonsec_slave                  1'b1                    !saf_nonsec_slave_lock
+    22      R   RSVD                                    1'b0
+    23      R   RSVD                                    1'b0
+    24      R   RSVD                                    1'b0
+    25      R   RSVD                                    1'b0
+    26      R   RSVD                                    1'b0
+    27      R/W saf_dummy0_nonsec_slave                 1'b1                    !saf_nonsec_slave_lock
+    28      R/W saf_dummy1_nonsec_slave                 1'b1                    !saf_nonsec_slave_lock
+    29      R/W saf_dummy2_nonsec_slave                 1'b1                    !saf_nonsec_slave_lock
+    30      R/W saf_dummy3_nonsec_slave                 1'b1                    !saf_nonsec_slave_lock
+    31      W1O saf_nonsec_slave_lock                   1'b0
+ */
+typedef volatile union _AON_REG1X_SAF_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t saf_uart0_nonsec_slave: 1;
+        uint32_t saf_uart1_nonsec_slave: 1;
+        uint32_t saf_uart2_nonsec_slave: 1;
+        uint32_t saf_uart3_nonsec_slave: 1;
+        uint32_t saf_i2c0_nonsec_slave: 1;
+        uint32_t saf_i2c1_nonsec_slave: 1;
+        uint32_t saf_key_scan_nonsec_slave: 1;
+        uint32_t saf_public_key_engine_nonsec_slave: 1;
+        uint32_t saf_flash_sec_nonsec_slave: 1;
+        uint32_t saf_aes_nonsec_slave: 1;
+        uint32_t saf_sha256_nonsec_slave: 1;
+        uint32_t saf_trng_nonsec_slave: 1;
+        uint32_t saf_efuse_controller_nonsec_slave: 1;
+        uint32_t saf_spi0_hs_nonsec_slave: 1;
+        uint32_t saf_rxi350_dmac_cfg_nonsec_slave: 1;
+        uint32_t saf_ppe_cfg_nonsec_slave: 1;
+        uint32_t saf_can_nonsec_slave: 1;
+        uint32_t saf_spic_phy_nonsec_slave: 1;
+        uint32_t saf_i2c2_nonsec_slave: 1;
+        uint32_t saf_i2c3_nonsec_slave: 1;
+        uint32_t saf_uart4_nonsec_slave: 1;
+        uint32_t saf_uart5_nonsec_slave: 1;
+        uint32_t RSVD_4: 1;
+        uint32_t RSVD_3: 1;
+        uint32_t RSVD_2: 1;
+        uint32_t RSVD_1: 1;
+        uint32_t RSVD: 1;
+        uint32_t saf_dummy0_nonsec_slave: 1;
+        uint32_t saf_dummy1_nonsec_slave: 1;
+        uint32_t saf_dummy2_nonsec_slave: 1;
+        uint32_t saf_dummy3_nonsec_slave: 1;
+        uint32_t saf_nonsec_slave_lock: 1;
+    };
+} AON_REG1X_SAF_TYPE;
+
+/* 0x46C    0x4000_046c
+    0       R/W usbotg_hnonsec                          1'b1                    !sc_hnonsec_lock
+    1       R/W sdio_host0_hnonsec                      1'b1                    !sc_hnonsec_lock
+    2       R/W display_arprot_1                        1'b1                    !sc_hnonsec_lock
+    3       R   RSVD                                    1'b0
+    4       R/W gmac_m_arprot_1                         1'b1                    !sc_hnonsec_lock
+    5       R/W gmac_m_awprot_1                         1'b1                    !sc_hnonsec_lock
+    6       R   RSVD                                    1'b0
+    7       R   RSVD                                    1'b0
+    8       R   RSVD                                    1'b0
+    9       R   RSVD                                    1'b0
+    10      R   RSVD                                    1'b0
+    11      R   RSVD                                    1'b0
+    12      R   RSVD                                    1'b0
+    13      R   RSVD                                    1'b0
+    14      R   RSVD                                    1'b0
+    15      R   RSVD                                    1'b0
+    16      R   RSVD                                    1'b0
+    17      R   RSVD                                    1'b0
+    18      R   RSVD                                    1'b0
+    19      R   RSVD                                    1'b0
+    20      R   RSVD                                    1'b0
+    21      R   RSVD                                    1'b0
+    22      R   RSVD                                    1'b0
+    23      R   RSVD                                    1'b0
+    24      R   RSVD                                    1'b0
+    25      R   RSVD                                    1'b0
+    26      R   RSVD                                    1'b0
+    27      R   RSVD                                    1'b0
+    28      R   RSVD                                    1'b0
+    29      R   RSVD                                    1'b0
+    30      R   RSVD                                    1'b0
+    31      W1O sc_hnonsec_lock                         1'b0
+ */
+typedef volatile union _AON_REG0X_SC_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t usbotg_hnonsec: 1;
+        uint32_t sdio_host0_hnonsec: 1;
+        uint32_t display_arprot_1: 1;
+        uint32_t RSVD_25: 1;
+        uint32_t gmac_m_arprot_1: 1;
+        uint32_t gmac_m_awprot_1: 1;
+        uint32_t RSVD_24: 1;
+        uint32_t RSVD_23: 1;
+        uint32_t RSVD_22: 1;
+        uint32_t RSVD_21: 1;
+        uint32_t RSVD_20: 1;
+        uint32_t RSVD_19: 1;
+        uint32_t RSVD_18: 1;
+        uint32_t RSVD_17: 1;
+        uint32_t RSVD_16: 1;
+        uint32_t RSVD_15: 1;
+        uint32_t RSVD_14: 1;
+        uint32_t RSVD_13: 1;
+        uint32_t RSVD_12: 1;
+        uint32_t RSVD_11: 1;
+        uint32_t RSVD_10: 1;
+        uint32_t RSVD_9: 1;
+        uint32_t RSVD_8: 1;
+        uint32_t RSVD_7: 1;
+        uint32_t RSVD_6: 1;
+        uint32_t RSVD_5: 1;
+        uint32_t RSVD_4: 1;
+        uint32_t RSVD_3: 1;
+        uint32_t RSVD_2: 1;
+        uint32_t RSVD_1: 1;
+        uint32_t RSVD: 1;
+        uint32_t sc_hnonsec_lock: 1;
+    };
+} AON_REG0X_SC_TYPE;
+
+/* 0x470    0x4000_0470
+    0       R/W km4_dbgen                               1'b1                    !km4_dbgen_lock
+    1       R/W km4_niden                               1'b1                    !km4_niden_lock
+    2       R/W km4_spiden                              1'b0                    !km4_spiden_lock
+    3       R/W km4_spniden                             1'b1                    !km4_spniden_lock
+    4       W1O km4_dbgen_lock                          1'b0
+    5       W1O km4_niden_lock                          1'b0
+    6       W1O km4_spiden_lock                         1'b0
+    7       W1O km4_spniden_lock                        1'b0
+    8       R   RSVD                                    1'b0
+    9       R   RSVD                                    1'b0
+    10      R   RSVD                                    1'b0
+    11      R   RSVD                                    1'b0
+    12      R   RSVD                                    1'b0
+    13      R   RSVD                                    1'b0
+    14      R   RSVD                                    1'b0
+    15      R   RSVD                                    1'b0
+    16      R   RSVD                                    1'b0
+    17      R   RSVD                                    1'b0
+    18      R   RSVD                                    1'b0
+    19      R   RSVD                                    1'b0
+    20      R   RSVD                                    1'b0
+    21      R   RSVD                                    1'b0
+    22      R   RSVD                                    1'b0
+    23      R   RSVD                                    1'b0
+    24      R   RSVD                                    1'b0
+    25      R   RSVD                                    1'b0
+    26      R   RSVD                                    1'b0
+    27      R   RSVD                                    1'b0
+    28      R   RSVD                                    1'b0
+    29      R   RSVD                                    1'b0
+    30      R   RSVD                                    1'b0
+    31      R   RSVD                                    1'b0
+ */
+typedef volatile union _AON_REG0X_KM4_DBG_CTRL_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t km4_dbgen: 1;
+        uint32_t km4_niden: 1;
+        uint32_t km4_spiden: 1;
+        uint32_t km4_spniden: 1;
+        uint32_t km4_dbgen_lock: 1;
+        uint32_t km4_niden_lock: 1;
+        uint32_t km4_spiden_lock: 1;
+        uint32_t km4_spniden_lock: 1;
+        uint32_t RSVD_23: 1;
+        uint32_t RSVD_22: 1;
+        uint32_t RSVD_21: 1;
+        uint32_t RSVD_20: 1;
+        uint32_t RSVD_19: 1;
+        uint32_t RSVD_18: 1;
+        uint32_t RSVD_17: 1;
+        uint32_t RSVD_16: 1;
+        uint32_t RSVD_15: 1;
+        uint32_t RSVD_14: 1;
+        uint32_t RSVD_13: 1;
+        uint32_t RSVD_12: 1;
+        uint32_t RSVD_11: 1;
+        uint32_t RSVD_10: 1;
+        uint32_t RSVD_9: 1;
+        uint32_t RSVD_8: 1;
+        uint32_t RSVD_7: 1;
+        uint32_t RSVD_6: 1;
+        uint32_t RSVD_5: 1;
+        uint32_t RSVD_4: 1;
+        uint32_t RSVD_3: 1;
+        uint32_t RSVD_2: 1;
+        uint32_t RSVD_1: 1;
+        uint32_t RSVD: 1;
+    };
+} AON_REG0X_KM4_DBG_CTRL_TYPE;
+
+/* 0x4B0    0x4000_04b0
+    0       R/W RTC_PF_CNT_START                        1'b0
+    1       R/W RTC_PF_CNT_RST                          1'b0
+    7:2     R/W RTC_PF_COMP_CONTROLLER_DUMMY0           6'b0
+    8       R/W RTC_PF_COMP0_WK_EN                      1'b0
+    9       R/W RTC_PF_COMP1_WK_EN                      1'b0
+    10      R/W RTC_PF_COMP2_WK_EN                      1'b0
+    11      R/W RTC_PF_COMP3_WK_EN                      1'b0
+    12      R/W RTC_PF_COMP0_INT_EN                     1'b0
+    13      R/W RTC_PF_COMP1_INT_EN                     1'b0
+    14      R/W RTC_PF_COMP2_INT_EN                     1'b0
+    15      R/W RTC_PF_COMP3_INT_EN                     1'b0
+    19:16   R/W RTC_PF_COMP_CONTROLLER_DUMMY1           4'b0
+    20      R/W RTC_PF_COMP0_ISR_TYPE                   1'b0
+    21      R/W RTC_PF_COMP1_ISR_TYPE                   1'b0
+    22      R/W RTC_PF_COMP2_ISR_TYPE                   1'b0
+    23      R/W RTC_PF_COMP3_ISR_TYPE                   1'b0
+    28:24   R/W RTC_PF_COMP_CONTROLLER_DUMMY1           5'b0
+    29      R/W RTC_PF_WK_EN                            1'b0
+    30      R/W RTC_PF_INT_EN                           1'b0
+    31      R/W RTC_PF_RST                              1'b0
+ */
+typedef volatile union _AON_RTC_PF_COMP_CONTROLLER_REG_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RTC_PF_CNT_START: 1;
+        uint32_t RTC_PF_CNT_RST: 1;
+        uint32_t RTC_PF_COMP_CONTROLLER_DUMMY0: 6;
+        uint32_t RTC_PF_COMP0_WK_EN: 1;
+        uint32_t RTC_PF_COMP1_WK_EN: 1;
+        uint32_t RTC_PF_COMP2_WK_EN: 1;
+        uint32_t RTC_PF_COMP3_WK_EN: 1;
+        uint32_t RTC_PF_COMP0_INT_EN: 1;
+        uint32_t RTC_PF_COMP1_INT_EN: 1;
+        uint32_t RTC_PF_COMP2_INT_EN: 1;
+        uint32_t RTC_PF_COMP3_INT_EN: 1;
+        uint32_t RTC_PF_COMP_CONTROLLER_DUMMY1_1: 4;
+        uint32_t RTC_PF_COMP0_ISR_TYPE: 1;
+        uint32_t RTC_PF_COMP1_ISR_TYPE: 1;
+        uint32_t RTC_PF_COMP2_ISR_TYPE: 1;
+        uint32_t RTC_PF_COMP3_ISR_TYPE: 1;
+        uint32_t RTC_PF_COMP_CONTROLLER_DUMMY1: 5;
+        uint32_t RTC_PF_WK_EN: 1;
+        uint32_t RTC_PF_INT_EN: 1;
+        uint32_t RTC_PF_RST: 1;
+    };
+    struct
+    {
+        uint32_t RTC_PF_COMP_CONTROLLER_ASSEMBLE0: 8;
+        uint32_t RTC_PF_COMP_WK_EN: 4;
+        uint32_t RTC_PF_COMP_INT_EN: 4;
+        uint32_t RTC_PF_COMP_CONTROLLER_ASSEMBLE1: 4;
+        uint32_t RTC_PF_COMP_ISR_TYPE: 4;
+        uint32_t RTC_PF_COMP_CONTROLLER_ASSEMBLE2: 8;
+    };
+} AON_RTC_PF_COMP_CONTROLLER_REG_TYPE;
+
+/* 0x4B4    0x4000_04b4
+    31:0    R/W RTC_PF_COMP0                            32'd0
+ */
+typedef volatile union _AON_RTC_PF_COMP0_REG_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RTC_PF_COMP0;
+    };
+} AON_RTC_PF_COMP0_REG_TYPE;
+
+/* 0x4B8    0x4000_04b8
+    31:0    R/W RTC_PF_COMP1                            32'd0
+ */
+typedef volatile union _AON_RTC_PF_COMP1_REG_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RTC_PF_COMP1;
+    };
+} AON_RTC_PF_COMP1_REG_TYPE;
+
+/* 0x4BC    0x4000_04bc
+    31:0    R/W RTC_PF_COMP2                            32'd0
+ */
+typedef volatile union _AON_RTC_PF_COMP2_REG_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RTC_PF_COMP2;
+    };
+} AON_RTC_PF_COMP2_REG_TYPE;
+
+/* 0x4C0    0x4000_04c0
+    31:0    R/W RTC_PF_COMP3                            32'd0
+ */
+typedef volatile union _AON_RTC_PF_COMP3_REG_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RTC_PF_COMP3;
+    };
+} AON_RTC_PF_COMP3_REG_TYPE;
+
+/* 0x4C4    0x4000_04c4
+    0       R/W RTC_PF_COMP0_MANUAL_INT                 1'b0
+    1       R/W RTC_PF_COMP1_MANUAL_INT                 1'b0
+    2       R/W RTC_PF_COMP2_MANUAL_INT                 1'b0
+    3       R/W RTC_PF_COMP3_MANUAL_INT                 1'b0
+    31:4    R/W RTC_PF_COMP_MANUAL_INT_DUMMY            28'b0
+ */
+typedef volatile union _AON_RTC_PF_COMP_MANUAL_INT_REG_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RTC_PF_COMP0_MANUAL_INT: 1;
+        uint32_t RTC_PF_COMP1_MANUAL_INT: 1;
+        uint32_t RTC_PF_COMP2_MANUAL_INT: 1;
+        uint32_t RTC_PF_COMP3_MANUAL_INT: 1;
+        uint32_t RTC_PF_COMP_MANUAL_INT_DUMMY: 28;
+    };
+    struct
+    {
+        uint32_t RTC_PF_COMP_MANUAL_INT: 4;
+        uint32_t RTC_PF_COMP_MANUAL_INT_ASSEMBLE: 28;
+    };
+} AON_RTC_PF_COMP_MANUAL_INT_REG_TYPE;
+
+/* 0x4C8    0x4000_04c8
+    31:0    R   RTC_PF_CNT                              32'd0
+ */
+typedef volatile union _AON_RTC_PF_CNT_REG_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RTC_PF_CNT;
+    };
+} AON_RTC_PF_CNT_REG_TYPE;
+
+/* 0x4CC    0x4000_04cc
+    0       R/WACRTC_PF_COMP0_WK_CLR                     1'b0
+    1       R/WACRTC_PF_COMP1_WK_CLR                     1'b0
+    2       R/WACRTC_PF_COMP2_WK_CLR                     1'b0
+    3       R/WACRTC_PF_COMP3_WK_CLR                     1'b0
+    4       R/WACRTC_PF_COMP0_INT_CLR                    1'b0
+    5       R/WACRTC_PF_COMP1_INT_CLR                    1'b0
+    6       R/WACRTC_PF_COMP2_INT_CLR                    1'b0
+    7       R/WACRTC_PF_COMP3_INT_CLR                    1'b0
+    31:8    R/W RTC_PF_COMP_INT_WK_CLR_DUMMY            24'b0
+ */
+typedef volatile union _AON_RTC_PF_COMP_INT_WK_CLR_REG_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RTC_PF_COMP0_WK_CLR: 1;
+        uint32_t RTC_PF_COMP1_WK_CLR: 1;
+        uint32_t RTC_PF_COMP2_WK_CLR: 1;
+        uint32_t RTC_PF_COMP3_WK_CLR: 1;
+        uint32_t RTC_PF_COMP0_INT_CLR: 1;
+        uint32_t RTC_PF_COMP1_INT_CLR: 1;
+        uint32_t RTC_PF_COMP2_INT_CLR: 1;
+        uint32_t RTC_PF_COMP3_INT_CLR: 1;
+        uint32_t RTC_PF_COMP_INT_WK_CLR_DUMMY: 24;
+    };
+    struct
+    {
+        uint32_t RTC_PF_COMP_WK_CLR: 4;
+        uint32_t RTC_PF_COMP_INT_CLR: 4;
+        uint32_t RTC_PF_COMP_INT_WK_CLR_ASSEMBLE: 24;
+    };
+} AON_RTC_PF_COMP_INT_WK_CLR_REG_TYPE;
+
+/* 0x4D0    0x4000_04d0
+    0       R/W1CRTC_PF_COMP0_WK_SR                      1'b0
+    1       R/W1CRTC_PF_COMP1_WK_SR                      1'b0
+    2       R/W1CRTC_PF_COMP2_WK_SR                      1'b0
+    3       R/W1CRTC_PF_COMP3_WK_SR                      1'b0
+    4       R/W1CRTC_PF_COMP0_INT_SR                     1'b0
+    5       R/W1CRTC_PF_COMP1_INT_SR                     1'b0
+    6       R/W1CRTC_PF_COMP2_INT_SR                     1'b0
+    7       R/W1CRTC_PF_COMP3_INT_SR                     1'b0
+    31:8    R/W RTC_PF_COMP_INT_WK_SR_DUMMY             24'b0
+ */
+typedef volatile union _AON_RTC_PF_COMP_INT_WK_SR_REG_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RTC_PF_COMP0_WK_SR: 1;
+        uint32_t RTC_PF_COMP1_WK_SR: 1;
+        uint32_t RTC_PF_COMP2_WK_SR: 1;
+        uint32_t RTC_PF_COMP3_WK_SR: 1;
+        uint32_t RTC_PF_COMP0_INT_SR: 1;
+        uint32_t RTC_PF_COMP1_INT_SR: 1;
+        uint32_t RTC_PF_COMP2_INT_SR: 1;
+        uint32_t RTC_PF_COMP3_INT_SR: 1;
+        uint32_t RTC_PF_COMP_INT_WK_SR_DUMMY: 24;
+    };
+    struct
+    {
+        uint32_t RTC_PF_COMP_WK_SR: 4;
+        uint32_t RTC_PF_COMP_INT_SR: 4;
+        uint32_t RTC_PF_COMP_INT_WK_SR_ASSEMBLE: 24;
+    };
+} AON_RTC_PF_COMP_INT_WK_SR_REG_TYPE;
+
+/* 0x4D4    0x4000_04d4
+    31:0    R   RTC_PF_RTL_VERSION                      32'h2208230A
+ */
+typedef volatile union _AON_RTC_PF_RTL_VERSION_REG_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RTC_PF_RTL_VERSION;
+    };
+} AON_RTC_PF_RTL_VERSION_REG_TYPE;
+
+/* 0x580    0x4000_0580
+    0       R/W bt_mac_vsel                             1'h1
+    31:1    R   RSVD                                    31'h0
+ */
+typedef volatile union _AON_BT_MAC_VSEL_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t bt_mac_vsel: 1;
+        uint32_t RSVD: 31;
+    };
+} AON_BT_MAC_VSEL_TYPE;
+
+/* 0x584    0x4000_0584
+    13:0    R/W bt_mac_snps_lv                          14'h292
+    27:14   R/W bt_mac_snps_hv                          14'h213
+    31:28   R   RSVD                                    4'h0
+ */
+typedef volatile union _AON_BT_MAC_SNPS_HV_LV_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t bt_mac_snps_lv: 14;
+        uint32_t bt_mac_snps_hv: 14;
+        uint32_t RSVD: 4;
+    };
+} AON_BT_MAC_SNPS_HV_LV_TYPE;
+
+/* 0x588    0x4000_0588
+    0       R/W bt_mac_1024x16_sd_iso0                  1'h0
+    1       R/W bt_mac_1024x16_sd_iso1                  1'h0
+    2       R/W bt_mac_1024x16_ds_iso0                  1'h0
+    3       R/W bt_mac_1024x16_ds_iso1                  1'h0
+    4       R/W bt_mac_1024x16_ls_iso0                  1'h0
+    5       R/W bt_mac_1024x16_ls_iso1                  1'h0
+    31:6    R   RSVD                                    26'h0
+ */
+typedef volatile union _AON_BT_MAC_1024x16_PWR_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t bt_mac_1024x16_sd_iso0: 1;
+        uint32_t bt_mac_1024x16_sd_iso1: 1;
+        uint32_t bt_mac_1024x16_ds_iso0: 1;
+        uint32_t bt_mac_1024x16_ds_iso1: 1;
+        uint32_t bt_mac_1024x16_ls_iso0: 1;
+        uint32_t bt_mac_1024x16_ls_iso1: 1;
+        uint32_t RSVD: 26;
+    };
+} AON_BT_MAC_1024x16_PWR_TYPE;
+
+/* 0x58C    0x4000_058c
+    0       R/W bt_mac_512x16_sd_iso0                   1'h0
+    1       R/W bt_mac_512x16_sd_iso1                   1'h0
+    2       R/W bt_mac_512x16_ds_iso0                   1'h0
+    3       R/W bt_mac_512x16_ds_iso1                   1'h0
+    4       R/W bt_mac_512x16_ls_iso0                   1'h0
+    5       R/W bt_mac_512x16_ls_iso1                   1'h0
+    31:6    R   RSVD                                    26'h0
+ */
+typedef volatile union _AON_BT_MAC_512x16_PWR_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t bt_mac_512x16_sd_iso0: 1;
+        uint32_t bt_mac_512x16_sd_iso1: 1;
+        uint32_t bt_mac_512x16_ds_iso0: 1;
+        uint32_t bt_mac_512x16_ds_iso1: 1;
+        uint32_t bt_mac_512x16_ls_iso0: 1;
+        uint32_t bt_mac_512x16_ls_iso1: 1;
+        uint32_t RSVD: 26;
+    };
+} AON_BT_MAC_512x16_PWR_TYPE;
+
+/* 0x590    0x4000_0590
+    0       R/W bt_mac_128x32_0_sd_iso0                 1'h0
+    1       R/W bt_mac_128x32_0_sd_iso1                 1'h0
+    2       R/W bt_mac_128x32_0_ds_iso0                 1'h0
+    3       R/W bt_mac_128x32_0_ds_iso1                 1'h0
+    4       R/W bt_mac_128x32_0_ls_iso0                 1'h0
+    5       R/W bt_mac_128x32_0_ls_iso1                 1'h0
+    31:6    R   RSVD                                    26'h0
+ */
+typedef volatile union _AON_BT_MAC_128x32_0_PWR_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t bt_mac_128x32_0_sd_iso0: 1;
+        uint32_t bt_mac_128x32_0_sd_iso1: 1;
+        uint32_t bt_mac_128x32_0_ds_iso0: 1;
+        uint32_t bt_mac_128x32_0_ds_iso1: 1;
+        uint32_t bt_mac_128x32_0_ls_iso0: 1;
+        uint32_t bt_mac_128x32_0_ls_iso1: 1;
+        uint32_t RSVD: 26;
+    };
+} AON_BT_MAC_128x32_0_PWR_TYPE;
+
+/* 0x594    0x4000_0594
+    0       R/W bt_mac_128x32_1_sd_iso0                 1'h0
+    1       R/W bt_mac_128x32_1_sd_iso1                 1'h0
+    2       R/W bt_mac_128x32_1_ds_iso0                 1'h0
+    3       R/W bt_mac_128x32_1_ds_iso1                 1'h0
+    4       R/W bt_mac_128x32_1_ls_iso0                 1'h0
+    5       R/W bt_mac_128x32_1_ls_iso1                 1'h0
+    31:6    R   RSVD                                    26'h0
+ */
+typedef volatile union _AON_BT_MAC_128x32_1_PWR_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t bt_mac_128x32_1_sd_iso0: 1;
+        uint32_t bt_mac_128x32_1_sd_iso1: 1;
+        uint32_t bt_mac_128x32_1_ds_iso0: 1;
+        uint32_t bt_mac_128x32_1_ds_iso1: 1;
+        uint32_t bt_mac_128x32_1_ls_iso0: 1;
+        uint32_t bt_mac_128x32_1_ls_iso1: 1;
+        uint32_t RSVD: 26;
+    };
+} AON_BT_MAC_128x32_1_PWR_TYPE;
+
+/* 0x598    0x4000_0598
+    13:0    R/W bt_mac_640x32_lv                        14'b11000100100010
+    27:14   R/W bt_mac_640x32_hv                        14'b11000010100010
+    31:28   R   RSVD                                    4'h0
+ */
+typedef volatile union _AON_BT_MAC_640x32_HV_LV_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t bt_mac_640x32_lv: 14;
+        uint32_t bt_mac_640x32_hv: 14;
+        uint32_t RSVD: 4;
+    };
+} AON_BT_MAC_640x32_HV_LV_TYPE;
+
+/* 0x59C    0x4000_059c
+    0       R/W bt_mac_640x32_sd_iso0                   1'h0
+    1       R/W bt_mac_640x32_sd_iso1                   1'h0
+    2       R/W bt_mac_640x32_ds_iso0                   1'h0
+    3       R/W bt_mac_640x32_ds_iso1                   1'h0
+    31:4    R   RSVD                                    28'h0
+ */
+typedef volatile union _AON_BT_MAC_640x32_PWR_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t bt_mac_640x32_sd_iso0: 1;
+        uint32_t bt_mac_640x32_sd_iso1: 1;
+        uint32_t bt_mac_640x32_ds_iso0: 1;
+        uint32_t bt_mac_640x32_ds_iso1: 1;
+        uint32_t RSVD: 28;
+    };
+} AON_BT_MAC_640x32_PWR_TYPE;
+
+/* 0x5A0    0x4000_05a0
+    13:0    R/W bt_mac_96x32_lv                         14'b11000001100010
+    27:14   R/W bt_mac_96x32_hv                         14'b11000010100010
+    31:28   R   RSVD                                    4'h0
+ */
+typedef volatile union _AON_BT_MAC_96x32_HV_LV_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t bt_mac_96x32_lv: 14;
+        uint32_t bt_mac_96x32_hv: 14;
+        uint32_t RSVD: 4;
+    };
+} AON_BT_MAC_96x32_HV_LV_TYPE;
+
+/* 0x5A4    0x4000_05a4
+    0       R/W bt_mac_96x32_sd_iso0                    1'h0
+    1       R/W bt_mac_96x32_sd_iso1                    1'h0
+    2       R/W bt_mac_96x32_ds_iso0                    1'h0
+    3       R/W bt_mac_96x32_ds_iso1                    1'h0
+    31:4    R   RSVD                                    28'h0
+ */
+typedef volatile union _AON_BT_MAC_96x32_PWR_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t bt_mac_96x32_sd_iso0: 1;
+        uint32_t bt_mac_96x32_sd_iso1: 1;
+        uint32_t bt_mac_96x32_ds_iso0: 1;
+        uint32_t bt_mac_96x32_ds_iso1: 1;
+        uint32_t RSVD: 28;
+    };
+} AON_BT_MAC_96x32_PWR_TYPE;
+
+/* 0x5A8    0x4000_05a8
+    13:0    R/W bt_mac_64x32_lv                         14'b11000001100010
+    27:14   R/W bt_mac_64x32_hv                         14'b11000010100010
+    31:28   R   RSVD                                    4'h0
+ */
+typedef volatile union _AON_BT_MAC_64x32_HV_LV_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t bt_mac_64x32_lv: 14;
+        uint32_t bt_mac_64x32_hv: 14;
+        uint32_t RSVD: 4;
+    };
+} AON_BT_MAC_64x32_HV_LV_TYPE;
+
+/* 0x5AC    0x4000_05ac
+    0       R/W bt_mac_64x32_sd_iso0                    1'h0
+    1       R/W bt_mac_64x32_sd_iso1                    1'h0
+    2       R/W bt_mac_64x32_ds_iso0                    1'h0
+    3       R/W bt_mac_64x32_ds_iso1                    1'h0
+    31:4    R   RSVD                                    28'h0
+ */
+typedef volatile union _AON_BT_MAC_64x32_PWR_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t bt_mac_64x32_sd_iso0: 1;
+        uint32_t bt_mac_64x32_sd_iso1: 1;
+        uint32_t bt_mac_64x32_ds_iso0: 1;
+        uint32_t bt_mac_64x32_ds_iso1: 1;
+        uint32_t RSVD: 28;
+    };
+} AON_BT_MAC_64x32_PWR_TYPE;
+
+/* 0x5B0    0x4000_05b0
+    0       R/W zb_mac_vsel                             1'h1
+    31:1    R   RSVD                                    31'h0
+ */
+typedef volatile union _AON_ZB_MAC_VSEL_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t zb_mac_vsel: 1;
+        uint32_t RSVD: 31;
+    };
+} AON_ZB_MAC_VSEL_TYPE;
+
+/* 0x5B4    0x4000_05b4
+    13:0    R/W zb_mac_lv                               14'h292
+    27:14   R/W zb_mac_hv                               14'h213
+    31:28   R   RSVD                                    4'h0
+ */
+typedef volatile union _AON_ZB_MAC_HV_LV_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t zb_mac_lv: 14;
+        uint32_t zb_mac_hv: 14;
+        uint32_t RSVD: 4;
+    };
+} AON_ZB_MAC_HV_LV_TYPE;
+
+/* 0x5B8    0x4000_05b8
+    0       R/W zb_mac_16x32_ds_iso0                    1'h0
+    1       R/W zb_mac_16x32_ds_iso1                    1'h0
+    2       R/W zb_mac_16x32_ls_iso0                    1'h0
+    3       R/W zb_mac_16x32_ls_iso1                    1'h0
+    4       R/W zb_mac_16x32_sd_iso0                    1'h0
+    5       R/W zb_mac_16x32_sd_iso1                    1'h0
+    31:6    R   RSVD                                    26'h0
+ */
+typedef volatile union _AON_ZB_MAC_16x32_PWR_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t zb_mac_16x32_ds_iso0: 1;
+        uint32_t zb_mac_16x32_ds_iso1: 1;
+        uint32_t zb_mac_16x32_ls_iso0: 1;
+        uint32_t zb_mac_16x32_ls_iso1: 1;
+        uint32_t zb_mac_16x32_sd_iso0: 1;
+        uint32_t zb_mac_16x32_sd_iso1: 1;
+        uint32_t RSVD: 26;
+    };
+} AON_ZB_MAC_16x32_PWR_TYPE;
+
+/* 0x5BC    0x4000_05bc
+    1:0     R/W zb_mac_40x32_sd_iso0                    2'h0
+    3:2     R/W zb_mac_40x32_sd_iso1                    2'h0
+    5:4     R/W zb_mac_40x32_ds_iso0                    2'h0
+    7:6     R/W zb_mac_40x32_ds_iso1                    2'h0
+    9:8     R/W zb_mac_40x32_ls_iso0                    2'h0
+    11:10   R/W zb_mac_40x32_ls_iso1                    2'h0
+    31:12   R   RSVD                                    20'h0
+ */
+typedef volatile union _AON_ZB_MAC_40x32_PWR_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t zb_mac_40x32_sd_iso0: 2;
+        uint32_t zb_mac_40x32_sd_iso1: 2;
+        uint32_t zb_mac_40x32_ds_iso0: 2;
+        uint32_t zb_mac_40x32_ds_iso1: 2;
+        uint32_t zb_mac_40x32_ls_iso0: 2;
+        uint32_t zb_mac_40x32_ls_iso1: 2;
+        uint32_t RSVD: 20;
+    };
+} AON_ZB_MAC_40x32_PWR_TYPE;
+
+/* 0x5C0    0x4000_05c0
+    3:0     R/W zb_mac_32x32_sd_iso0                    4'h0
+    7:4     R/W zb_mac_32x32_sd_iso1                    4'h0
+    11:8    R/W zb_mac_32x32_ds_iso0                    4'h0
+    15:12   R/W zb_mac_32x32_ds_iso1                    4'h0
+    19:16   R/W zb_mac_32x32_ls_iso0                    4'h0
+    23:20   R/W zb_mac_32x32_ls_iso1                    4'h0
+    31:24   R   RSVD                                    8'h0
+ */
+typedef volatile union _AON_ZB_MAC_32x32_PWR_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t zb_mac_32x32_sd_iso0: 4;
+        uint32_t zb_mac_32x32_sd_iso1: 4;
+        uint32_t zb_mac_32x32_ds_iso0: 4;
+        uint32_t zb_mac_32x32_ds_iso1: 4;
+        uint32_t zb_mac_32x32_ls_iso0: 4;
+        uint32_t zb_mac_32x32_ls_iso1: 4;
+        uint32_t RSVD: 8;
+    };
+} AON_ZB_MAC_32x32_PWR_TYPE;
+
+/* 0x5C4    0x4000_05c4
+    0       R/W bt_phy_vsel                             1'h1
+    31:1    R   RSVD                                    31'h0
+ */
+typedef volatile union _AON_BT_PHY_VSEL_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t bt_phy_vsel: 1;
+        uint32_t RSVD: 31;
+    };
+} AON_BT_PHY_VSEL_TYPE;
+
+/* 0x5C8    0x4000_05c8
+    13:0    R/W bt_phy_lv                               14'h292
+    27:14   R/W bt_phy_hv                               14'h213
+    31:28   R   RSVD                                    4'h0
+ */
+typedef volatile union _AON_BT_PHY_HV_LV_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t bt_phy_lv: 14;
+        uint32_t bt_phy_hv: 14;
+        uint32_t RSVD: 4;
+    };
+} AON_BT_PHY_HV_LV_TYPE;
+
+/* 0x5CC    0x4000_05cc
+    3:0     R/W btphy_128x12x4_sd_iso0                  4'h0
+    7:4     R/W btphy_128x12x4_sd_iso1                  4'h0
+    11:8    R/W btphy_128x12x4_ds_iso0                  4'h0
+    15:12   R/W btphy_128x12x4_ds_iso1                  4'h0
+    19:16   R/W btphy_128x12x4_ls_iso0                  4'h0
+    23:20   R/W btphy_128x12x4_ls_iso1                  4'h0
+    31:24   R   RSVD                                    8'h0
+ */
+typedef volatile union _AON_BT_PHY_128x12x4_PWR_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t btphy_128x12x4_sd_iso0: 4;
+        uint32_t btphy_128x12x4_sd_iso1: 4;
+        uint32_t btphy_128x12x4_ds_iso0: 4;
+        uint32_t btphy_128x12x4_ds_iso1: 4;
+        uint32_t btphy_128x12x4_ls_iso0: 4;
+        uint32_t btphy_128x12x4_ls_iso1: 4;
+        uint32_t RSVD: 8;
+    };
+} AON_BT_PHY_128x12x4_PWR_TYPE;
+
+/* 0x5D0    0x4000_05d0
+    4:0     R/W btphy_lr_ram_sd_iso0                    5'h0
+    9:5     R/W btphy_lr_ram_sd_iso1                    5'h0
+    14:10   R/W btphy_lr_ram_ds_iso0                    5'h0
+    19:15   R/W btphy_lr_ram_ds_iso1                    5'h0
+    24:20   R/W btphy_lr_ram_ls_iso0                    5'h0
+    29:25   R/W btphy_lr_ram_ls_iso1                    5'h0
+    31:30   R   RSVD                                    2'h0
+ */
+typedef volatile union _AON_BT_PHY_LR_RAM_PWR_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t btphy_lr_ram_sd_iso0: 5;
+        uint32_t btphy_lr_ram_sd_iso1: 5;
+        uint32_t btphy_lr_ram_ds_iso0: 5;
+        uint32_t btphy_lr_ram_ds_iso1: 5;
+        uint32_t btphy_lr_ram_ls_iso0: 5;
+        uint32_t btphy_lr_ram_ls_iso1: 5;
+        uint32_t RSVD: 2;
+    };
+} AON_BT_PHY_LR_RAM_PWR_TYPE;
+
+/* 0x5D4    0x4000_05d4
+    0       R/W km4_vsel                                1'h1
+    31:1    R   RSVD                                    31'h0
+ */
+typedef volatile union _AON_KM4_VSEL_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t km4_vsel: 1;
+        uint32_t RSVD: 31;
+    };
+} AON_KM4_VSEL_TYPE;
+
+/* 0x5D8    0x4000_05d8
+    5:0     R/W km4_itcm0_lv                            6'h12
+    11:6    R/W km4_itcm0_hv                            6'h13
+    31:12   R   RSVD                                    20'h0
+ */
+typedef volatile union _AON_KM4_ITCM0_HV_LV_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t km4_itcm0_lv: 6;
+        uint32_t km4_itcm0_hv: 6;
+        uint32_t RSVD: 20;
+    };
+} AON_KM4_ITCM0_HV_LV_TYPE;
+
+/* 0x5DC    0x4000_05dc
+    3:0     R/W km4_itcm0_ls_iso0                       4'h0
+    7:4     R/W km4_itcm0_ls_iso1                       4'h0
+    31:8    R   RSVD                                    24'h0
+ */
+typedef volatile union _AON_KM4_ITCM0_LS_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t km4_itcm0_ls_iso0: 4;
+        uint32_t km4_itcm0_ls_iso1: 4;
+        uint32_t RSVD: 24;
+    };
+} AON_KM4_ITCM0_LS_TYPE;
+
+/* 0x5E0    0x4000_05e0
+    13:0    R/W km4_tcm_lv                              14'b11000101100010
+    27:14   R/W km4_tcm_hv                              14'b11000010101100
+    31:28   R   RSVD                                    4'h0
+ */
+typedef volatile union _AON_KM4_TCM_HV_LV_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t km4_tcm_lv: 14;
+        uint32_t km4_tcm_hv: 14;
+        uint32_t RSVD: 4;
+    };
+} AON_KM4_TCM_HV_LV_TYPE;
+
+/* 0x5E4    0x4000_05e4
+    11:0    R/W km4_itcm1_ds_iso0                       12'h0
+    23:12   R/W km4_itcm1_ds_iso1                       12'h0
+    31:24   R   RSVD                                    8'h0
+ */
+typedef volatile union _AON_KM4_ITCM1_PWR_0_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t km4_itcm1_ds_iso0: 12;
+        uint32_t km4_itcm1_ds_iso1: 12;
+        uint32_t RSVD: 8;
+    };
+} AON_KM4_ITCM1_PWR_0_TYPE;
+
+/* 0x5E8    0x4000_05e8
+    11:0    R/W km4_itcm1_sd_iso0                       12'h0
+    23:12   R/W km4_itcm1_sd_iso1                       12'h0
+    31:24   R   RSVD                                    8'h
+ */
+typedef volatile union _AON_KM4_ITCM1_PWR_1_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t km4_itcm1_sd_iso0: 12;
+        uint32_t km4_itcm1_sd_iso1: 12;
+        uint32_t RSVD: 8;
+    };
+} AON_KM4_ITCM1_PWR_1_TYPE;
+
+/* 0x5EC    0x4000_05ec
+    3:0     R/W km4_dtcm0_sd_iso0                       4'h0
+    7:4     R/W km4_dtcm0_sd_iso1                       4'h0
+    11:8    R/W km4_dtcm0_ds_iso0                       4'h0
+    15:12   R/W km4_dtcm0_ds_iso1                       4'h0
+    31:16   R   RSVD                                    16'h0
+ */
+typedef volatile union _AON_KM4_DTCM0_PWR_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t km4_dtcm0_sd_iso0: 4;
+        uint32_t km4_dtcm0_sd_iso1: 4;
+        uint32_t km4_dtcm0_ds_iso0: 4;
+        uint32_t km4_dtcm0_ds_iso1: 4;
+        uint32_t RSVD: 16;
+    };
+} AON_KM4_DTCM0_PWR_TYPE;
+
+/* 0x5F0    0x4000_05f0
+    3:0     R/W km4_dtcm1_sd_iso0                       4'h0
+    7:4     R/W km4_dtcm1_sd_iso1                       4'h0
+    11:8    R/W km4_dtcm1_ds_iso0                       4'h0
+    15:12   R/W km4_dtcm1_ds_iso1                       4'h0
+    31:16   R   RSVD                                    16'h0
+ */
+typedef volatile union _AON_KM4_DTCM1_PWR_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t km4_dtcm1_sd_iso0: 4;
+        uint32_t km4_dtcm1_sd_iso1: 4;
+        uint32_t km4_dtcm1_ds_iso0: 4;
+        uint32_t km4_dtcm1_ds_iso1: 4;
+        uint32_t RSVD: 16;
+    };
+} AON_KM4_DTCM1_PWR_TYPE;
+
+/* 0x5F4    0x4000_05f4
+    13:0    R/W km4_ic_data_lv                          14'b11000101100010
+    27:14   R/W km4_ic_data_hv                          14'b11000010101100
+    31:28   R   RSVD                                    4'h0
+ */
+typedef volatile union _AON_KM4_IC_DATA_HV_LV_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t km4_ic_data_lv: 14;
+        uint32_t km4_ic_data_hv: 14;
+        uint32_t RSVD: 4;
+    };
+} AON_KM4_IC_DATA_HV_LV_TYPE;
+
+/* 0x5F8    0x4000_05f8
+    1:0     R/W km4_ic_data_sd_iso0                     2'h0
+    3:2     R/W km4_ic_data_sd_iso1                     2'h0
+    5:4     R/W km4_ic_data_ds_iso0                     2'h0
+    7:6     R/W km4_ic_data_ds_iso1                     2'h0
+    31:8    R   RSVD                                    24'h0
+ */
+typedef volatile union _AON_KM4_IC_DATA_PWR_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t km4_ic_data_sd_iso0: 2;
+        uint32_t km4_ic_data_sd_iso1: 2;
+        uint32_t km4_ic_data_ds_iso0: 2;
+        uint32_t km4_ic_data_ds_iso1: 2;
+        uint32_t RSVD: 24;
+    };
+} AON_KM4_IC_DATA_PWR_TYPE;
+
+/* 0x5FC    0x4000_05fc
+    13:0    R/W km4_ic_tag_lv                           14'b11000100100010
+    27:14   R/W km4_ic_tag_hv                           14'b11000010101100
+    31:28   R   RSVD                                    4'h0
+ */
+typedef volatile union _AON_KM4_IC_TAG_HV_LV_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t km4_ic_tag_lv: 14;
+        uint32_t km4_ic_tag_hv: 14;
+        uint32_t RSVD: 4;
+    };
+} AON_KM4_IC_TAG_HV_LV_TYPE;
+
+/* 0x600    0x4000_0600
+    1:0     R/W km4_ic_tag_sd_iso0                      2'h0
+    3:2     R/W km4_ic_tag_sd_iso1                      2'h0
+    5:4     R/W km4_ic_tag_ds_iso0                      2'h0
+    7:6     R/W km4_ic_tag_ds_iso1                      2'h0
+    31:8    R   RSVD                                    24'h0
+ */
+typedef volatile union _AON_KM4_IC_TAG_PWR_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t km4_ic_tag_sd_iso0: 2;
+        uint32_t km4_ic_tag_sd_iso1: 2;
+        uint32_t km4_ic_tag_ds_iso0: 2;
+        uint32_t km4_ic_tag_ds_iso1: 2;
+        uint32_t RSVD: 24;
+    };
+} AON_KM4_IC_TAG_PWR_TYPE;
+
+/* 0x604    0x4000_0604
+    13:0    R/W km4_dc_data_lv                          14'b11000101100010
+    27:14   R/W km4_dc_data_hv                          14'b11000010101100
+    31:28   R   RSVD                                    4'h0
+ */
+typedef volatile union _AON_KM4_DC_DATA_HV_LV_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t km4_dc_data_lv: 14;
+        uint32_t km4_dc_data_hv: 14;
+        uint32_t RSVD: 4;
+    };
+} AON_KM4_DC_DATA_HV_LV_TYPE;
+
+/* 0x608    0x4000_0608
+    3:0     R/W km4_dc_data_sd_iso0                     4'h0
+    7:4     R/W km4_dc_data_sd_iso1                     4'h0
+    11:8    R/W km4_dc_data_ds_iso0                     4'h0
+    15:12   R/W km4_dc_data_ds_iso1                     4'h0
+    31:16   R   RSVD                                    16'h0
+ */
+typedef volatile union _AON_KM4_DC_DATA_PWR_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t km4_dc_data_sd_iso0: 4;
+        uint32_t km4_dc_data_sd_iso1: 4;
+        uint32_t km4_dc_data_ds_iso0: 4;
+        uint32_t km4_dc_data_ds_iso1: 4;
+        uint32_t RSVD: 16;
+    };
+} AON_KM4_DC_DATA_PWR_TYPE;
+
+/* 0x60C    0x4000_060c
+    13:0    R/W km4_dc_tag_lv                           14'b11000100100010
+    27:14   R/W km4_dc_tag_hv                           14'b11000010101100
+    31:28   R   RSVD                                    4'h0
+ */
+typedef volatile union _AON_KM4_DC_TAG_HV_LV_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t km4_dc_tag_lv: 14;
+        uint32_t km4_dc_tag_hv: 14;
+        uint32_t RSVD: 4;
+    };
+} AON_KM4_DC_TAG_HV_LV_TYPE;
+
+/* 0x610    0x4000_0610
+    1:0     R/W km4_dc_tag_sd_iso0                      2'h0
+    3:2     R/W km4_dc_tag_sd_iso1                      2'h0
+    5:4     R/W km4_dc_tag_ds_iso0                      2'h0
+    7:6     R/W km4_dc_tag_ds_iso1                      2'h0
+    31:8    R   RSVD                                    24'h0
+ */
+typedef volatile union _AON_KM4_DC_TAG_PWR_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t km4_dc_tag_sd_iso0: 2;
+        uint32_t km4_dc_tag_sd_iso1: 2;
+        uint32_t km4_dc_tag_ds_iso0: 2;
+        uint32_t km4_dc_tag_ds_iso1: 2;
+        uint32_t RSVD: 24;
+    };
+} AON_KM4_DC_TAG_PWR_TYPE;
+
+/* 0x614    0x4000_0614
+    0       R/W buffer_ram_vsel                         1'h1
+    31:1    R   RSVD                                    31'h0
+ */
+typedef volatile union _AON_BUFFER_RAM_VSEL_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t buffer_ram_vsel: 1;
+        uint32_t RSVD: 31;
+    };
+} AON_BUFFER_RAM_VSEL_TYPE;
+
+/* 0x618    0x4000_0618
+    13:0    R/W buffer_ram_lv                           14'b11000101100010
+    27:14   R/W buffer_ram_hv                           14'b11000010101100
+    31:28   R   RSVD                                    4'h0
+ */
+typedef volatile union _AON_BUFFER_RAM_HV_LV_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t buffer_ram_lv: 14;
+        uint32_t buffer_ram_hv: 14;
+        uint32_t RSVD: 4;
+    };
+} AON_BUFFER_RAM_HV_LV_TYPE;
+
+/* 0x61C    0x4000_061c
+    2:0     R/W buffer_ram_sd_iso0                      3'h0
+    5:3     R/W buffer_ram_sd_iso1                      3'h0
+    8:6     R/W buffer_ram_ds_iso0                      3'h0
+    11:9    R/W buffer_ram_ds_iso1                      3'h0
+    31:12   R   RSVD                                    20'h0
+ */
+typedef volatile union _AON_BUFFER_RAM_PWR_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t buffer_ram_sd_iso0: 3;
+        uint32_t buffer_ram_sd_iso1: 3;
+        uint32_t buffer_ram_ds_iso0: 3;
+        uint32_t buffer_ram_ds_iso1: 3;
+        uint32_t RSVD: 20;
+    };
+} AON_BUFFER_RAM_PWR_TYPE;
+
+/* 0x620    0x4000_0620
+    0       R/W data_ram_vsel                           1'h1
+    31:1    R   RSVD                                    31'h0
+ */
+typedef volatile union _AON_DATA_RAM_VSEL_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t data_ram_vsel: 1;
+        uint32_t RSVD: 31;
+    };
+} AON_DATA_RAM_VSEL_TYPE;
+
+/* 0x624    0x4000_0624
+    13:0    R/W data_ram_lv                             14'b11000101100010
+    27:14   R/W data_ram_hv                             14'b11000010101100
+    31:28   R   RSVD                                    4'h0
+ */
+typedef volatile union _AON_DATA_RAM_HV_LV_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t data_ram_lv: 14;
+        uint32_t data_ram_hv: 14;
+        uint32_t RSVD: 4;
+    };
+} AON_DATA_RAM_HV_LV_TYPE;
+
+/* 0x628    0x4000_0628
+    0       R/W data_ram_sd_iso0                        1'h0
+    1       R/W data_ram_sd_iso1                        1'h0
+    2       R/W data_ram_ds_iso0                        1'h0
+    3       R/W data_ram_ds_iso1                        1'h0
+    31:4    R   RSVD                                    28'h0
+ */
+typedef volatile union _AON_DATA_RAM_PWR_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t data_ram_sd_iso0: 1;
+        uint32_t data_ram_sd_iso1: 1;
+        uint32_t data_ram_ds_iso0: 1;
+        uint32_t data_ram_ds_iso1: 1;
+        uint32_t RSVD: 28;
+    };
+} AON_DATA_RAM_PWR_TYPE;
+
+/* 0x62C    0x4000_062c
+    0       R/W usb_vsel                                1'h1
+    31:1    R   RSVD                                    31'h0
+ */
+typedef volatile union _AON_USB_VSEL_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t usb_vsel: 1;
+        uint32_t RSVD: 31;
+    };
+} AON_USB_VSEL_TYPE;
+
+/* 0x630    0x4000_0630
+    13:0    R/W usb_lv                                  14'h292
+    27:14   R/W usb_hv                                  14'h213
+    31:28   R   RSVD                                    4'h0
+ */
+typedef volatile union _AON_USB_HV_LV_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t usb_lv: 14;
+        uint32_t usb_hv: 14;
+        uint32_t RSVD: 4;
+    };
+} AON_USB_HV_LV_TYPE;
+
+/* 0x634    0x4000_0634
+    0       R/W usb_2176x35_sd_iso0                     1'h0
+    1       R/W usb_2176x35_sd_iso1                     1'h0
+    2       R/W usb_2176x35_ds_iso0                     1'h0
+    3       R/W usb_2176x35_ds_iso1                     1'h0
+    4       R/W usb_2176x35_ls_iso0                     1'h0
+    5       R/W usb_2176x35_ls_iso1                     1'h0
+    31:6    R   RSVD                                    26'h0
+ */
+typedef volatile union _AON_USB_PWR_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t usb_2176x35_sd_iso0: 1;
+        uint32_t usb_2176x35_sd_iso1: 1;
+        uint32_t usb_2176x35_ds_iso0: 1;
+        uint32_t usb_2176x35_ds_iso1: 1;
+        uint32_t usb_2176x35_ls_iso0: 1;
+        uint32_t usb_2176x35_ls_iso1: 1;
+        uint32_t RSVD: 26;
+    };
+} AON_USB_PWR_TYPE;
+
+/* 0x638    0x4000_0638
+    0       R/W sdio_ram_pd_iso0                        1'h0
+    1       R/W sdio_ram_pd_iso1                        1'h0
+    31:2    R   RSVD                                    30'h0
+ */
+typedef volatile union _AON_SDIO_RAM_PWR_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t sdio_ram_pd_iso0: 1;
+        uint32_t sdio_ram_pd_iso1: 1;
+        uint32_t RSVD: 30;
+    };
+} AON_SDIO_RAM_PWR_TYPE;
+
+/* 0x63C    0x4000_063c
+    0       R/W display_128x32_pd_iso0                  1'h0
+    1       R/W display_128x32_pd_iso1                  1'h0
+    31:2    R   RSVD                                    30'h0
+ */
+typedef volatile union _AON_DISPLAY_128x32_PWR_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t display_128x32_pd_iso0: 1;
+        uint32_t display_128x32_pd_iso1: 1;
+        uint32_t RSVD: 30;
+    };
+} AON_DISPLAY_128x32_PWR_TYPE;
+
+/* 0x640    0x4000_0640
+    0       R/W display_672x24_pd_iso0                  1'h0
+    1       R/W display_672x24_pd_iso1                  1'h0
+    31:2    R   RSVD                                    30'h0
+ */
+typedef volatile union _AON_DISPLAY_672x24_PWR_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t display_672x24_pd_iso0: 1;
+        uint32_t display_672x24_pd_iso1: 1;
+        uint32_t RSVD: 30;
+    };
+} AON_DISPLAY_672x24_PWR_TYPE;
+
+/* 0x644    0x4000_0644
+    1:0     R/W gmac_512x32_pd_iso0                     2'h0
+    3:2     R/W gmac_512x32_pd_iso1                     2'h0
+    31:4    R   RSVD                                    28'h0
+ */
+typedef volatile union _AON_GMAC_PWR_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t gmac_512x32_pd_iso0: 2;
+        uint32_t gmac_512x32_pd_iso1: 2;
+        uint32_t RSVD: 28;
+    };
+} AON_GMAC_PWR_TYPE;
+
+/* 0x648    0x4000_0648
+    5:0     R/W pke_rom_hv                              6'h13
+    31:6    R/W RSVD                                    26'h0
+ */
+typedef volatile union _AON_PKE_ROM_HV_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t pke_rom_hv: 6;
+        uint32_t RSVD: 26;
+    };
+} AON_PKE_ROM_HV_TYPE;
+
+/* 0x64C    0x4000_064c
+    0       R/W pke_rom_sd_iso1                         1'h0
+    1       R/W pke_rom_sd_iso0                         1'h0
+    2       R/W pke_rom_ls_iso1                         1'h0
+    3       R/W pke_rom_ls_iso0                         1'h0
+    31:4    R/W RSVD                                    28'h0
+ */
+typedef volatile union _AON_PKE_ROM_PWR_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t pke_rom_sd_iso1: 1;
+        uint32_t pke_rom_sd_iso0: 1;
+        uint32_t pke_rom_ls_iso1: 1;
+        uint32_t pke_rom_ls_iso0: 1;
+        uint32_t RSVD: 28;
+    };
+} AON_PKE_ROM_PWR_TYPE;
+
+/* 0x650    0x4000_0650
+    1:0     R/W pke_mmem_pd_iso0                        2'h0
+    3:2     R/W pke_mmem_pd_iso1                        2'h0
+    31:4    R   RSVD                                    28'h0
+ */
+typedef volatile union _AON_PKE_MMEM_PWR_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t pke_mmem_pd_iso0: 2;
+        uint32_t pke_mmem_pd_iso1: 2;
+        uint32_t RSVD: 28;
+    };
+} AON_PKE_MMEM_PWR_TYPE;
+
+/* 0x654    0x4000_0654
+    1:0     R/W pke_tmem_pd_iso0                        2'h0
+    3:2     R/W pke_tmem_pd_iso1                        2'h0
+    31:4    R   RSVD                                    28'h0
+ */
+typedef volatile union _AON_PKE_TMEM_PWR_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t pke_tmem_pd_iso0: 2;
+        uint32_t pke_tmem_pd_iso1: 2;
+        uint32_t RSVD: 28;
+    };
+} AON_PKE_TMEM_PWR_TYPE;
+
+/* 0x658    0x4000_0658
+    0       R/W audio_vsel                              1'h1
+    31:1    R   RSVD                                    31'h0
+ */
+typedef volatile union _AON_AUDIO_VSEL_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t audio_vsel: 1;
+        uint32_t RSVD: 31;
+    };
+} AON_AUDIO_VSEL_TYPE;
+
+/* 0x65C    0x4000_065c
+    13:0    R/W audio_lv                                14'h292
+    27:14   R/W audio_hv                                14'h213
+    31:28   R   RSVD                                    4'h0
+ */
+typedef volatile union _AON_AUDIO_HV_LV_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t audio_lv: 14;
+        uint32_t audio_hv: 14;
+        uint32_t RSVD: 4;
+    };
+} AON_AUDIO_HV_LV_TYPE;
+
+/* 0x660    0x4000_0660
+    1:0     R/W audio_ad_ram_sd_iso0                    2'h0
+    3:2     R/W audio_ad_ram_sd_iso1                    2'h0
+    5:4     R/W audio_ad_ram_ds_iso0                    2'h0
+    7:6     R/W audio_ad_ram_ds_iso1                    2'h0
+    9:8     R/W audio_ad_ram_ls_iso0                    2'h0
+    11:10   R/W audio_ad_ram_ls_iso1                    2'h0
+    31:12   R   RSVD                                    20'h0
+ */
+typedef volatile union _AON_AUDIO_AD_PWR_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t audio_ad_ram_sd_iso0: 2;
+        uint32_t audio_ad_ram_sd_iso1: 2;
+        uint32_t audio_ad_ram_ds_iso0: 2;
+        uint32_t audio_ad_ram_ds_iso1: 2;
+        uint32_t audio_ad_ram_ls_iso0: 2;
+        uint32_t audio_ad_ram_ls_iso1: 2;
+        uint32_t RSVD: 20;
+    };
+} AON_AUDIO_AD_PWR_TYPE;
+
+/* 0x664    0x4000_0664
+    0       R/W audio_da_ram_sd_iso0                    1'h0
+    1       R/W audio_da_ram_sd_iso1                    1'h0
+    2       R/W audio_da_ram_ds_iso0                    1'h0
+    3       R/W audio_da_ram_ds_iso1                    1'h0
+    4       R/W audio_da_ram_ls_iso0                    1'h0
+    5       R/W audio_da_ram_ls_iso1                    1'h0
+    31:6    R   RSVD                                    26'h0
+ */
+typedef volatile union _AON_AUDIO_DA_PWR_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t audio_da_ram_sd_iso0: 1;
+        uint32_t audio_da_ram_sd_iso1: 1;
+        uint32_t audio_da_ram_ds_iso0: 1;
+        uint32_t audio_da_ram_ds_iso1: 1;
+        uint32_t audio_da_ram_ls_iso0: 1;
+        uint32_t audio_da_ram_ls_iso1: 1;
+        uint32_t RSVD: 26;
+    };
+} AON_AUDIO_DA_PWR_TYPE;
+
+/* 0x668    0x4000_0668
+    0       R/W can_vsel                                1'h1
+    31:1    R   RSVD                                    31'h0
+ */
+typedef volatile union _AON_CAN_VSEL_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t can_vsel: 1;
+        uint32_t RSVD: 31;
+    };
+} AON_CAN_VSEL_TYPE;
+
+/* 0x66C    0x4000_066c
+    13:0    R/W can_lv                                  14'h292
+    27:14   R/W can_hv                                  14'h213
+    31:28   R   RSVD                                    4'h0
+ */
+typedef volatile union _AON_CAN_HV_LV_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t can_lv: 14;
+        uint32_t can_hv: 14;
+        uint32_t RSVD: 4;
+    };
+} AON_CAN_HV_LV_TYPE;
+
+/* 0x670    0x4000_0670
+    0       R/W can_ram_sd_iso0                         1'h0
+    1       R/W can_ram_sd_iso1                         1'h0
+    2       R/W can_ram_ds_iso0                         1'h0
+    3       R/W can_ram_ds_iso1                         1'h0
+    4       R/W can_ram_ls_iso0                         1'h0
+    5       R/W can_ram_ls_iso1                         1'h0
+    31:6    R   RSVD                                    26'h0
+ */
+typedef volatile union _AON_CAN_PWR_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t can_ram_sd_iso0: 1;
+        uint32_t can_ram_sd_iso1: 1;
+        uint32_t can_ram_ds_iso0: 1;
+        uint32_t can_ram_ds_iso1: 1;
+        uint32_t can_ram_ls_iso0: 1;
+        uint32_t can_ram_ls_iso1: 1;
+        uint32_t RSVD: 26;
+    };
+} AON_CAN_PWR_TYPE;
+
+/* 0x800    0x4000_0800
+    0       R/W BT_CORE_RSTB                            1'b0
+    1       R/W BT_PON_RSTB                             1'b0
+    2       R/W BT_RET_RSTB                             1'b0
+    3       R/W ISO_XTAL                                1'b1
+    4       R/W ISO_BT_CORE                             1'b1
+    5       R/W ISO_BT_PON                              1'b1
+    6       R/W ISO_VDDON_XTAL                          1'b1
+    7       R/W ISO_OSC                                 1'b1
+    8       R/W ISO_AFE_PLL                             1'b1
+    9       R/W BT_PON2_RSTB                            1'b0
+    10      R/W ISO_BT_PON2                             1'b1
+    11      R/W BT_CORE3_RSTB                           1'b0
+    12      R/W ISO_BT_CORE3                            1'b1
+    13      R/W BT_AON_ACTIVE_CLK_RSTB                  1'b0
+    14      R/W ISO_EF2AON                              1'b1
+    15      R/W ISO_USB_VON                             1'b1
+    16      R/W ISO_DIG_40M                             1'b1
+    17      R/W ISO_AFE_PLL2                            1'b1
+    31:18   R   RSVD                                    14'b0
+ */
+typedef volatile union _AON_REG0X_SYS_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t BT_CORE_RSTB: 1;
+        uint32_t BT_PON_RSTB: 1;
+        uint32_t BT_RET_RSTB: 1;
+        uint32_t ISO_XTAL: 1;
+        uint32_t ISO_BT_CORE: 1;
+        uint32_t ISO_BT_PON: 1;
+        uint32_t ISO_VDDON_XTAL: 1;
+        uint32_t ISO_OSC: 1;
+        uint32_t ISO_AFE_PLL: 1;
+        uint32_t BT_PON2_RSTB: 1;
+        uint32_t ISO_BT_PON2: 1;
+        uint32_t BT_CORE3_RSTB: 1;
+        uint32_t ISO_BT_CORE3: 1;
+        uint32_t BT_AON_ACTIVE_CLK_RSTB: 1;
+        uint32_t ISO_EF2AON: 1;
+        uint32_t ISO_USB_VON: 1;
+        uint32_t ISO_DIG_40M: 1;
+        uint32_t ISO_AFE_PLL2: 1;
+        uint32_t RSVD: 14;
+    };
+} AON_REG0X_SYS_TYPE;
+
+/* 0x804    0x4000_0804
+    0       R/W RFC_STORE                               1'b0
+    1       R/W RFC_RESTORE                             1'b0
+    2       R/W MODEM_STORE                             1'b0
+    3       R/W MODEM_RESTORE                           1'b0
+    4       R/W BZ_STORE                                1'b0
+    5       R/W BZ_RESTORE                              1'b0
+    6       R/W BLE_STORE                               1'b0
+    7       R/W BLE_RESTORE                             1'b0
+    8       R/W PF_STORE                                1'b0
+    9       R/W PF_RESTORE                              1'b0
+    10      R/W DP_MODEM_STORE                          1'b0
+    11      R/W DP_MODEM_RESTORE                        1'b0
+    12      R/W ZB_STORE                                1'b0
+    13      R/W ZB_RESTORE                              1'b0
+    31:14   R   RSVD                                    18'b0
+ */
+typedef volatile union _AON_REG1X_SYS_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RFC_STORE: 1;
+        uint32_t RFC_RESTORE: 1;
+        uint32_t MODEM_STORE: 1;
+        uint32_t MODEM_RESTORE: 1;
+        uint32_t BZ_STORE: 1;
+        uint32_t BZ_RESTORE: 1;
+        uint32_t BLE_STORE: 1;
+        uint32_t BLE_RESTORE: 1;
+        uint32_t PF_STORE: 1;
+        uint32_t PF_RESTORE: 1;
+        uint32_t DP_MODEM_STORE: 1;
+        uint32_t DP_MODEM_RESTORE: 1;
+        uint32_t ZB_STORE: 1;
+        uint32_t ZB_RESTORE: 1;
+        uint32_t RSVD: 18;
+    };
+} AON_REG1X_SYS_TYPE;
+
+/* 0x808    0x4000_0808
+    0       R/W FW_enter_lps                            1'b0
+    1       R/W FW_PON_SEQ_RST_N                        1'b0
+    2       R/W AON_GATED_EN                            1'b1
+    3       R/W PMU_SETTING_ENABLE                      1'b1
+    4       R/W WAIT_XTAL_CLK_OK                        1'b1
+    5       R/W PMU_OFF_SEQUENCE                        1'b0
+    6       R/W AON_BUCK_LOW_IQ_ZCD_32K_CLK_EN          1'b0
+    12:7    R/W REG2X_SYS_DUMMY                         6'h2a
+    15:13   R/W AON_DBG_SEL                             3'h0
+    31:16   R/W REG2X_SYS_DUMMY2                        16'b0
+ */
+typedef volatile union _AON_REG2X_SYS_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t FW_enter_lps: 1;
+        uint32_t FW_PON_SEQ_RST_N: 1;
+        uint32_t AON_GATED_EN: 1;
+        uint32_t PMU_SETTING_ENABLE: 1;
+        uint32_t WAIT_XTAL_CLK_OK: 1;
+        uint32_t PMU_OFF_SEQUENCE: 1;
+        uint32_t AON_BUCK_LOW_IQ_ZCD_32K_CLK_EN: 1;
+        uint32_t REG2X_SYS_DUMMY: 6;
+        uint32_t AON_DBG_SEL: 3;
+        uint32_t REG2X_SYS_DUMMY2: 16;
+    };
+} AON_REG2X_SYS_TYPE;
+
+/* 0x80C    0x4000_080c
+    0       R/W AON_ACTIVE_CLK_EN                       1'b0
+    1       R/W SRC_AON_ACTIVE_CLK_SEL                  1'b1
+    2       R/W aon_loader_en                           1'b0
+    3       R/W SWR_BY_CORE                             1'b0
+    5:4     R/W PIN_CLK_OUT_SEL                         2'b1
+    7:6     R/W REG3X_SYS_dummy2                        2'b1
+    9:8     R/W rtc_in_sel                              2'b0
+    10      R/W en_gpio_32k                             1'b0
+    12:11   R/W REG3X_SYS_dummy3                        2'b0
+    13      R   reg_aon_wdt_reset                       1'b0
+    14      R/W TX_BIG_POUT                             1'b0
+    16:15   R/W aonqcode_ph_pin_sel                     2'b0
+    17      W1O REG_EN_CLK_REQ_FROM_IO                  1'b0
+    31:18   R/W RSVD                                    14'b0
+ */
+typedef volatile union _AON_REG3X_SYS_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t AON_ACTIVE_CLK_EN: 1;
+        uint32_t SRC_AON_ACTIVE_CLK_SEL: 1;
+        uint32_t aon_loader_en: 1;
+        uint32_t SWR_BY_CORE: 1;
+        uint32_t PIN_CLK_OUT_SEL: 2;
+        uint32_t REG3X_SYS_dummy2: 2;
+        uint32_t rtc_in_sel: 2;
+        uint32_t en_gpio_32k: 1;
+        uint32_t REG3X_SYS_dummy3: 2;
+        uint32_t reg_aon_wdt_reset: 1;
+        uint32_t TX_BIG_POUT: 1;
+        uint32_t aonqcode_ph_pin_sel: 2;
+        uint32_t REG_EN_CLK_REQ_FROM_IO: 1;
+        uint32_t RSVD: 14;
+    };
+} AON_REG3X_SYS_TYPE;
+
+/* 0x810    0x4000_0810
+    31:0    R   RSVD                                    32'b0
+ */
+typedef volatile union _AON_REG4X_SYS_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RSVD;
+    };
+} AON_REG4X_SYS_TYPE;
+
+/* 0x814    0x4000_0814
+    0       R/W SEL_32K_XTAL                            1'b0
+    1       R/W SEL_32K_SDM                             1'b0
+    3:2     R/W SEL_32K_dummy                           2'b0
+    4       R/W SEL_32K_XTAL_sys                        1'b0
+    5       R/W SEL_32K_SDM_sys                         1'b0
+    7:6     R/W SEL_32K_sys_dummy                       2'b0
+    8       R/W SEL_32K_XTAL_rtc                        1'b0
+    9       R/W SEL_32K_SDM_rtc                         1'b0
+    10      R/W SEL_32K_GPIO_rtc                        1'b0
+    11      R/W SEL_32K_rtc_dummy                       1'b0
+    12      R/W SEL_32K_XTAL_bt                         1'b0
+    13      R/W SEL_32K_SDM_bt                          1'b0
+    15:14   R/W SEL_32K_bt_dummy                        2'b0
+    16      R/W SEL_32K_XTAL_wdg                        1'b0
+    17      R/W SEL_32K_SDM_wdg                         1'b0
+    19:18   R/W SEL_32K_wdt_dummy                       2'b0
+    20      R/W SEL_32K_XTAL_qd                         1'b0
+    21      R/W SEL_32K_SDM_qd                          1'b0
+    23:22   R/W SEL_32K_qd_dummy                        2'b0
+    24      R/W SEL_32K_XTAL_segcom                     1'b0
+    25      R/W SEL_32K_SDM_segcom                      1'b0
+    27:26   R/W SEL_32K_segcom_dummy                    2'b0
+    28      R/W SEL_32K_XTAL_pf_rtc                     1'b0
+    29      R/W SEL_32K_SDM_pf_rtc                      1'b0
+    31:30   R   RSVD                                    2'b0
+ */
+typedef volatile union _AON_REG5X_SYS_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t SEL_32K_XTAL: 1;
+        uint32_t SEL_32K_SDM: 1;
+        uint32_t SEL_32K_dummy: 2;
+        uint32_t SEL_32K_XTAL_sys: 1;
+        uint32_t SEL_32K_SDM_sys: 1;
+        uint32_t SEL_32K_sys_dummy: 2;
+        uint32_t SEL_32K_XTAL_rtc: 1;
+        uint32_t SEL_32K_SDM_rtc: 1;
+        uint32_t SEL_32K_GPIO_rtc: 1;
+        uint32_t SEL_32K_rtc_dummy: 1;
+        uint32_t SEL_32K_XTAL_bt: 1;
+        uint32_t SEL_32K_SDM_bt: 1;
+        uint32_t SEL_32K_bt_dummy: 2;
+        uint32_t SEL_32K_XTAL_wdg: 1;
+        uint32_t SEL_32K_SDM_wdg: 1;
+        uint32_t SEL_32K_wdt_dummy: 2;
+        uint32_t SEL_32K_XTAL_qd: 1;
+        uint32_t SEL_32K_SDM_qd: 1;
+        uint32_t SEL_32K_qd_dummy: 2;
+        uint32_t SEL_32K_XTAL_segcom: 1;
+        uint32_t SEL_32K_SDM_segcom: 1;
+        uint32_t SEL_32K_segcom_dummy: 2;
+        uint32_t SEL_32K_XTAL_pf_rtc: 1;
+        uint32_t SEL_32K_SDM_pf_rtc: 1;
+        uint32_t RSVD: 2;
+    };
+} AON_REG5X_SYS_TYPE;
+
+/* 0x818    0x4000_0818
+    0       R/W r_cpu_clk_dummy0                        1'b0
+    1       R/W r_cpu_clk_dummy1                        1'b0
+    2       R/W r_aon_cpu_pll_src_sel                   1'b0
+    31:3    R   RSVD                                    29'b0
+ */
+typedef volatile union _AON_REG6X_SYS_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t r_cpu_clk_dummy0: 1;
+        uint32_t r_cpu_clk_dummy1: 1;
+        uint32_t r_aon_cpu_pll_src_sel: 1;
+        uint32_t RSVD: 29;
+    };
+} AON_REG6X_SYS_TYPE;
+
+/* 0x81C    0x4000_081c
+    0       R/W short_pulse_wkup_en                     1'b0
+    1       W1C short_pulse_wkup_event_latch            1'b1
+    3:2     R   RSVD                                    2'b0
+    4       R/W USB_WKEN                                1'b0
+    5       R/W USB_WKPOL                               1'b0
+    6       R/W usb_wakeup_sel                          1'b1
+    31:7    R   RSVD                                    25'b0
+ */
+typedef volatile union _AON_REG7X_SYS_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t short_pulse_wkup_en: 1;
+        uint32_t short_pulse_wkup_event_latch: 1;
+        uint32_t RSVD_1: 2;
+        uint32_t USB_WKEN: 1;
+        uint32_t USB_WKPOL: 1;
+        uint32_t usb_wakeup_sel: 1;
+        uint32_t RSVD: 25;
+    };
+} AON_REG7X_SYS_TYPE;
+
+/* 0x820    0x4000_0820
+    0       W1C gpio_wkup_sts                           1'b1
+    1       W1C rtc_wkup_sts                            1'b1
+    2       W1C rtc_pf_wkup_sts                         1'b1
+    3       W1C rif_wkup_sts                            1'b1
+    4       W1C usb_wkup_sts                            1'b1
+    5       W1C aonqd_wkup_sts                          1'b1
+    6       W1C lpcomp0_wkup_sts                        1'b1
+    31:7    R   RSVD                                    25'b0
+ */
+typedef volatile union _AON_REG8X_SYS_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t gpio_wkup_sts: 1;
+        uint32_t rtc_wkup_sts: 1;
+        uint32_t rtc_pf_wkup_sts: 1;
+        uint32_t rif_wkup_sts: 1;
+        uint32_t usb_wkup_sts: 1;
+        uint32_t aonqd_wkup_sts: 1;
+        uint32_t lpcomp0_wkup_sts: 1;
+        uint32_t RSVD: 25;
+    };
+} AON_REG8X_SYS_TYPE;
+
+/* 0x824    0x4000_0824
+    31:0    R   RSVD                                    32'b0
+ */
+typedef volatile union _AON_REG9X_SYS_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RSVD;
+    };
+} AON_REG9X_SYS_TYPE;
+
+/* 0x828    0x4000_0828
+    0       R/W reg_SCAN_MODE                           1'b0
+    1       R/W PAD_BONDING_SHDN                        1'b1
+    3:2     R   RSVD                                    2'b0
+    4       R/W PAD_VDDIO_FLASH_E                       1'b0
+    5       R/W PAD_VDDIO_FLASH_POW_VG1                 1'b0
+    6       R/W PAD_VDDIO_FLASH_POW_VG2                 1'b0
+    7       R/W PAD_VDDIO_PSRAM_E                       1'b0
+    8       R/W PAD_VDDIO_PSRAM_POW_VG1                 1'b0
+    9       R/W PAD_VDDIO_PSRAM_POW_VG2                 1'b0
+    31:10   R   RSVD                                    22'b0
+ */
+typedef volatile union _AON_REG10X_SYS_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t reg_SCAN_MODE: 1;
+        uint32_t PAD_BONDING_SHDN: 1;
+        uint32_t RSVD_1: 2;
+        uint32_t PAD_VDDIO_FLASH_E: 1;
+        uint32_t PAD_VDDIO_FLASH_POW_VG1: 1;
+        uint32_t PAD_VDDIO_FLASH_POW_VG2: 1;
+        uint32_t PAD_VDDIO_PSRAM_E: 1;
+        uint32_t PAD_VDDIO_PSRAM_POW_VG1: 1;
+        uint32_t PAD_VDDIO_PSRAM_POW_VG2: 1;
+        uint32_t RSVD: 22;
+    };
+} AON_REG10X_SYS_TYPE;
+
+/* 0x82C    0x4000_082c
+    0       R/W DIGI_Efuse_CK_L                         1'b0
+    31:1    R   RSVD                                    31'b0
+ */
+typedef volatile union _AON_REG0X_EFUSE_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t DIGI_Efuse_CK_L: 1;
+        uint32_t RSVD: 31;
+    };
+} AON_REG0X_EFUSE_TYPE;
+
+/* 0x830    0x4000_0830
+    4:0     R   XTAL_PDCK_LP                            5'd0
+    5       R   XTAL_PDCK_OK                            1'b0
+    6       R   XTAL_PDCK_BUSY                          1'b0
+    7       R/W xtal_pdck_rslt_latch                    1'b0
+    12:8    R   XPDCK_VREF_OUT                          5'b11111
+    13      R   XPDCK_READY                             1'b0
+    14      R   XPDCK_BUSY                              1'b0
+    15      R   XTAL_PDCK_LP[5]                         1'b0
+    16      R   XPDCK_VREF_OUT[5]                       1'b0
+    31:17   R   RSVD                                    15'b0
+ */
+typedef volatile union _AON_REG0X_XPDCK_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t XTAL_PDCK_LP: 5;
+        uint32_t XTAL_PDCK_OK: 1;
+        uint32_t XTAL_PDCK_BUSY: 1;
+        uint32_t xtal_pdck_rslt_latch: 1;
+        uint32_t XPDCK_VREF_OUT: 5;
+        uint32_t XPDCK_READY: 1;
+        uint32_t XPDCK_BUSY: 1;
+        uint32_t XTAL_PDCK_LP_5: 1;
+        uint32_t XPDCK_VREF_OUT_5: 1;
+        uint32_t RSVD: 15;
+    };
+} AON_REG0X_XPDCK_TYPE;
+
+/* 0x834    0x4000_0834
+    0       R/W PWM_EN_POS                              1'b0
+    1       R/W PWM_POS_RSTB                            1'b1
+    9:2     R   RSVD                                    8'b0
+    12:10   R/W PWM_PON_STEP_WAIT                       3'b0
+    15:13   R/W PWM_PON_WAIT                            3'b0
+    20:16   R/W PWM_PON_STEP                            5'b1
+    25:21   R/W PWM_PON_START                           5'b0
+    30:26   R/W PWM_PON_OVER                            5'b11111
+    31      R   RSVD                                    1'h0
+ */
+typedef volatile union _AON_REG0X_PWM_POS_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t PWM_EN_POS: 1;
+        uint32_t PWM_POS_RSTB: 1;
+        uint32_t RSVD_1: 8;
+        uint32_t PWM_PON_STEP_WAIT: 3;
+        uint32_t PWM_PON_WAIT: 3;
+        uint32_t PWM_PON_STEP: 5;
+        uint32_t PWM_PON_START: 5;
+        uint32_t PWM_PON_OVER: 5;
+        uint32_t RSVD: 1;
+    };
+} AON_REG0X_PWM_POS_TYPE;
+
+/* 0x838    0x4000_0838
+    0       R/W PFM_EN_POS                              1'b0
+    1       R/W PFM_POS_RSTB                            1'b1
+    12:2    R   RSVD                                    11'b0
+    15:13   R/W PFM_PON_STEP_WAIT                       3'b0
+    19:16   R/W PFM_PON_STEP                            4'b1
+    23:20   R/W PFM_PON_START                           4'b0
+    27:24   R/W PFM_PON_OVER                            4'b1011
+    30:28   R/W PFM_PON_WAIT                            3'b1
+    31      R   RSVD                                    1'h0
+ */
+typedef volatile union _AON_REG0X_PFM_POS_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t PFM_EN_POS: 1;
+        uint32_t PFM_POS_RSTB: 1;
+        uint32_t RSVD_1: 11;
+        uint32_t PFM_PON_STEP_WAIT: 3;
+        uint32_t PFM_PON_STEP: 4;
+        uint32_t PFM_PON_START: 4;
+        uint32_t PFM_PON_OVER: 4;
+        uint32_t PFM_PON_WAIT: 3;
+        uint32_t RSVD: 1;
+    };
+} AON_REG0X_PFM_POS_TYPE;
+
+/* 0x83C    0x4000_083c
+    1:0     R   RSVD                                    2'b0
+    11:2    R/W D300k_PFM_LOWER_BND                     10'b0000001010
+    12      R/W D300k_EN_VDROP_DET                      1'b0
+    13      R/W D300k_EN_32K_AUDIO                      1'b0
+    14      R/W D300k_RSTB                              1'b0
+    15      R/W D300k_SEL_NI_ON                         1'b0
+    16      R/W D300k_REG_MANU_MODE_CCOT                1'b1
+    22:17   R/W D300k_REG_MANU_CCOT                     6'b001000
+    31:23   R   RSVD                                    9'b0
+ */
+typedef volatile union _AON_REG0X_300K_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RSVD_1: 2;
+        uint32_t D300k_PFM_LOWER_BND: 10;
+        uint32_t D300k_EN_VDROP_DET: 1;
+        uint32_t D300k_EN_32K_AUDIO: 1;
+        uint32_t D300k_RSTB: 1;
+        uint32_t D300k_SEL_NI_ON: 1;
+        uint32_t D300k_REG_MANU_MODE_CCOT: 1;
+        uint32_t D300k_REG_MANU_CCOT: 6;
+        uint32_t RSVD: 9;
+    };
+} AON_REG0X_300K_TYPE;
+
+/* 0x840    0x4000_0840
+    1:0     R/W D300k_PFM_COMP_SAMPLE_CYC               2'b0
+    3:2     R/W D300k_SAMPLE_CYC                        2'b0
+    9:4     R/W D300k_CCOT_FORCE                        6'b010000
+    15:10   R/W D300k_CCOT_INIT                         6'b001000
+    21:16   R   RSVD                                    6'b0
+    31:22   R/W D300k_PFM_UPPER_BND                     10'b0000010100
+ */
+typedef volatile union _AON_REG1X_300K_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t D300k_PFM_COMP_SAMPLE_CYC: 2;
+        uint32_t D300k_SAMPLE_CYC: 2;
+        uint32_t D300k_CCOT_FORCE: 6;
+        uint32_t D300k_CCOT_INIT: 6;
+        uint32_t RSVD: 6;
+        uint32_t D300k_PFM_UPPER_BND: 10;
+    };
+} AON_REG1X_300K_TYPE;
+
+/* 0x844    0x4000_0844
+    15:0    R   RO_AON_CNT_EXTRA_DELAY_PON_XTAL         16'h0
+    22:16   R   RO_WK_REASON                            7'h0
+    31:23   R   RSVD                                    9'h0
+ */
+typedef volatile union _AON_AON_READ_RG0X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RO_AON_CNT_EXTRA_DELAY_PON_XTAL: 16;
+        uint32_t RO_WK_REASON: 7;
+        uint32_t RSVD: 9;
+    };
+} AON_AON_READ_RG0X_TYPE;
+
+/* 0x848    0x4000_0848
+    31:0    R   RSVD                                    32'b0
+ */
+typedef volatile union _AON_AON_READ_RG1X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RSVD;
+    };
+} AON_AON_READ_RG1X_TYPE;
+
+/* 0x84C    0x4000_084c
+    31:0    R   RSVD                                    32'b0
+ */
+typedef volatile union _AON_AON_READ_RG2X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RSVD;
+    };
+} AON_AON_READ_RG2X_TYPE;
+
+/* 0x850    0x4000_0850
+    31:0    R   RSVD                                    32'b0
+ */
+typedef volatile union _AON_AON_READ_RG3X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RSVD;
+    };
+} AON_AON_READ_RG3X_TYPE;
+
+/* 0x854    0x4000_0854
+    31:0    R   RSVD                                    32'b0
+ */
+typedef volatile union _AON_AON_READ_RG4X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RSVD;
+    };
+} AON_AON_READ_RG4X_TYPE;
+
+/* 0x858    0x4000_0858
+    31:0    R   RSVD                                    32'b0
+ */
+typedef volatile union _AON_AON_READ_RG5X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RSVD;
+    };
+} AON_AON_READ_RG5X_TYPE;
+
+/* 0x85C    0x4000_085c
+    31:0    R   RSVD                                    32'b0
+ */
+typedef volatile union _AON_AON_READ_RG6X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RSVD;
+    };
+} AON_AON_READ_RG6X_TYPE;
+
+/* 0x860    0x4000_0860
+    31:0    R   RSVD                                    32'b0
+ */
+typedef volatile union _AON_AON_READ_RG7X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RSVD;
+    };
+} AON_AON_READ_RG7X_TYPE;
+
+/* 0x864    0x4000_0864
+    31:0    R   RSVD                                    32'b0
+ */
+typedef volatile union _AON_AON_READ_RG8X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RSVD;
+    };
+} AON_AON_READ_RG8X_TYPE;
+
+/* 0x868    0x4000_0868
+    31:0    R   RSVD                                    32'b0
+ */
+typedef volatile union _AON_AON_READ_RG9X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RSVD;
+    };
+} AON_AON_READ_RG9X_TYPE;
+
+/* 0x86C    0x4000_086c
+    31:0    R   RSVD                                    32'b0
+ */
+typedef volatile union _AON_AON_READ_RG10X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RSVD;
+    };
+} AON_AON_READ_RG10X_TYPE;
+
+/* 0x870    0x4000_0870
+    31:0    R   RSVD                                    32'b0
+ */
+typedef volatile union _AON_AON_READ_RG11X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RSVD;
+    };
+} AON_AON_READ_RG11X_TYPE;
+
+/* 0x874    0x4000_0874
+    31:0    R   RSVD                                    32'b0
+ */
+typedef volatile union _AON_AON_READ_RG12X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RSVD;
+    };
+} AON_AON_READ_RG12X_TYPE;
+
+/* 0x878    0x4000_0878
+    31:0    R   RSVD                                    32'b0
+ */
+typedef volatile union _AON_AON_READ_RG13X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RSVD;
+    };
+} AON_AON_READ_RG13X_TYPE;
+
+/* 0x87C    0x4000_087c
+    31:0    R   RSVD                                    32'b0
+ */
+typedef volatile union _AON_AON_READ_RG14X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RSVD;
+    };
+} AON_AON_READ_RG14X_TYPE;
+
+/* 0x880    0x4000_0880
+    31:0    R   RSVD                                    32'b0
+ */
+typedef volatile union _AON_AON_READ_RG15X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RSVD;
+    };
+} AON_AON_READ_RG15X_TYPE;
+
+/* 0x884    0x4000_0884
+    31:0    R   RSVD                                    32'b0
+ */
+typedef volatile union _AON_AON_READ_RG16X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RSVD;
+    };
+} AON_AON_READ_RG16X_TYPE;
+
+/* 0xAB0    0x4000_0ab0
+    0       R/W LOP_PON_ENPC_DIGI                       1'b0
+    1       R/W LOP_PON_PFM                             1'b0
+    2       R/W LOP_PON_SWR                             1'b0
+    3       R/W LOP_PON_POW_32KOSC                      1'b1
+    4       R/W LOP_PON_ACTIVE_CLK_SEL                  1'b1
+    5       R/W LOP_PON_XTAL                            1'b1
+    6       R/W LOP_PON_POW_32KXTAL                     1'b0
+    7       R/W LOP_PON_VDDIO_PSRAM_PC_EN               1'b1
+    8       R/W LOP_PON_VDDIO_FLASH_PC_EN               1'b1
+    9       R/W LOP_PON_ENPC_AON                        1'b1
+    10      R/W LOP_PON_VDDIO_PC_CTRL                   1'b1
+    11      R/W LOP_PON_PLL1                            1'b0
+    12      R/W LOP_PON_PLL2                            1'b0
+    18:13   R/W LOP_RG0_dummy1                          6'b011101
+    21:19   R/W LOP_PON_XTAL_MODE                       3'b100
+    22      R/W LOP_PON_PWM_EN_POS                      1'b1
+    23      R/W LOP_PON_PFM_EN_POS                      1'b1
+    24      R/W LOP_PON_OSC                             1'b1
+    31:25   R   RSVD                                    7'h0
+ */
+typedef volatile union _AON_LOP_RG0X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t LOP_PON_ENPC_DIGI: 1;
+        uint32_t LOP_PON_PFM: 1;
+        uint32_t LOP_PON_SWR: 1;
+        uint32_t LOP_PON_POW_32KOSC: 1;
+        uint32_t LOP_PON_ACTIVE_CLK_SEL: 1;
+        uint32_t LOP_PON_XTAL: 1;
+        uint32_t LOP_PON_POW_32KXTAL: 1;
+        uint32_t LOP_PON_VDDIO_PSRAM_PC_EN: 1;
+        uint32_t LOP_PON_VDDIO_FLASH_PC_EN: 1;
+        uint32_t LOP_PON_ENPC_AON: 1;
+        uint32_t LOP_PON_VDDIO_PC_CTRL: 1;
+        uint32_t LOP_PON_PLL1: 1;
+        uint32_t LOP_PON_PLL2: 1;
+        uint32_t LOP_RG0_dummy1: 6;
+        uint32_t LOP_PON_XTAL_MODE: 3;
+        uint32_t LOP_PON_PWM_EN_POS: 1;
+        uint32_t LOP_PON_PFM_EN_POS: 1;
+        uint32_t LOP_PON_OSC: 1;
+        uint32_t RSVD: 7;
+    };
+} AON_LOP_RG0X_TYPE;
+
+/* 0xAB4    0x4000_0ab4
+    0       R/W LOP_PON_BUCK_PFM_IHALF                  1'b0
+    1       R/W LOP_PON_BUCK_EN_OCP_IBON                1'b1
+    5:2     R/W LOP_PON_BUCK_PFM_ICOMP                  4'b0010
+    9:6     R/W LOP_PON_BUCK_PFM_ISCH                   4'b0010
+    10      R/W LOP_PON_BUCK_ENOCPPS_H                  1'b0
+    11      R/W LOP_PON_LDO_ENLDO311_IB20nA             1'b1
+    14:12   R/W LOP_PON_MBIAS_VR_SEL_LDO311             3'b010
+    15      R/W LOP_PON_BUCK_ENOCPPFM_H                 1'b1
+    18:16   R/W LOP_PON_LDO_EN_DL_LDO311                3'b111
+    20:19   R/W LOP_PON_BUCK_OCPRES_H                   2'b10
+    21      R/W LOP_PON_BUCK_OCPSEL_H                   1'b1
+    24:22   R/W LOP_PON_BUCK_VREFOCP_H                  3'b001
+    25      R/W LOP_PON_BUCK_ENOFFSAWPFM_H              1'b1
+    26      R/W LOP_PON_BUCK_PFM_COT_EN                 1'b0
+    27      R/W LOP_PON_BUCK_PFM_AOT_EN                 1'b1
+    29:28   R/W LOP_PON_IBSEL_TONCOMP                   2'b01
+    30      R/W LOP_PON_LDO_POW_LDODIGI                 1'b1
+    31      R/W LOP_PON_AON_BUCK_LOW_IQ_ZCD_32K_CLK_EN  1'b0
+ */
+typedef volatile union _AON_LOP_RG1X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t LOP_PON_BUCK_PFM_IHALF: 1;
+        uint32_t LOP_PON_BUCK_EN_OCP_IBON: 1;
+        uint32_t LOP_PON_BUCK_PFM_ICOMP: 4;
+        uint32_t LOP_PON_BUCK_PFM_ISCH: 4;
+        uint32_t LOP_PON_BUCK_ENOCPPS_H: 1;
+        uint32_t LOP_PON_LDO_ENLDO311_IB20nA: 1;
+        uint32_t LOP_PON_MBIAS_VR_SEL_LDO311: 3;
+        uint32_t LOP_PON_BUCK_ENOCPPFM_H: 1;
+        uint32_t LOP_PON_LDO_EN_DL_LDO311: 3;
+        uint32_t LOP_PON_BUCK_OCPRES_H: 2;
+        uint32_t LOP_PON_BUCK_OCPSEL_H: 1;
+        uint32_t LOP_PON_BUCK_VREFOCP_H: 3;
+        uint32_t LOP_PON_BUCK_ENOFFSAWPFM_H: 1;
+        uint32_t LOP_PON_BUCK_PFM_COT_EN: 1;
+        uint32_t LOP_PON_BUCK_PFM_AOT_EN: 1;
+        uint32_t LOP_PON_IBSEL_TONCOMP: 2;
+        uint32_t LOP_PON_LDO_POW_LDODIGI: 1;
+        uint32_t LOP_PON_AON_BUCK_LOW_IQ_ZCD_32K_CLK_EN: 1;
+    };
+} AON_LOP_RG1X_TYPE;
+
+/* 0xAB8    0x4000_0ab8
+    0       R/W LOP_PON_BUCK_ENOCPS                     1'b1
+    1       R/W LOP_PON_BUCK_POW_ZCD                    1'b1
+    2       R/W LOP_PON_LDO_EN_DMYL_50U_LDODIGI         1'b0
+    3       R/W LOP_PON_LDO_EN_DMYL_200U_LDODIGI        1'b0
+    4       R/W LOP_PON_IB_500N_TONCOMP_EN              1'b1
+    5       R/W LOP_PON_IB_500N_COTCOMP_EN              1'b1
+    12:6    R/W LOP_PON_BUCK_ZCDOFFSET                  7'b0
+    13      R/W LOP_PON_BUCK_POW_LowIq_ZCD              1'b0
+    14      R/W LOP_PON_BUCK_STICKY_CODE_STATE1         1'b0
+    15      R/W LOP_PON_BUCK_FORCE_CODE_STATE1          1'b0
+    22:16   R   RSVD                                    7'b0
+    23      R   RSVD                                    1'b0
+    24      R/W LOP_PON_BUCK_STICKY_CODE_STATE2         1'b0
+    25      R/W LOP_PON_BUCK_FORCE_CODE_STATE2          1'b0
+    31:26   R/W LOP_PON_D300k_REG_MANU_CCOT             6'b001000
+ */
+typedef volatile union _AON_LOP_RG2X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t LOP_PON_BUCK_ENOCPS: 1;
+        uint32_t LOP_PON_BUCK_POW_ZCD: 1;
+        uint32_t LOP_PON_LDO_EN_DMYL_50U_LDODIGI: 1;
+        uint32_t LOP_PON_LDO_EN_DMYL_200U_LDODIGI: 1;
+        uint32_t LOP_PON_IB_500N_TONCOMP_EN: 1;
+        uint32_t LOP_PON_IB_500N_COTCOMP_EN: 1;
+        uint32_t LOP_PON_BUCK_ZCDOFFSET: 7;
+        uint32_t LOP_PON_BUCK_POW_LowIq_ZCD: 1;
+        uint32_t LOP_PON_BUCK_STICKY_CODE_STATE1: 1;
+        uint32_t LOP_PON_BUCK_FORCE_CODE_STATE1: 1;
+        uint32_t RSVD_1: 7;
+        uint32_t RSVD: 1;
+        uint32_t LOP_PON_BUCK_STICKY_CODE_STATE2: 1;
+        uint32_t LOP_PON_BUCK_FORCE_CODE_STATE2: 1;
+        uint32_t LOP_PON_D300k_REG_MANU_CCOT: 6;
+    };
+} AON_LOP_RG2X_TYPE;
+
+/* 0xABC    0x4000_0abc
+    0       R   RSVD                                    1'b0
+    1       R/W LOP_POF_ENPC_DIGI                       1'b1
+    2       R/W LOP_POF_POWLDO_DIGI                     1'b1
+    3       R/W LOP_POF_ENPC_CORE                       1'b0
+    4       R/W LOP_POF_POW_BIAS                        1'b0
+    5       R/W LOP_POF_POW_32KOSC                      1'b1
+    6       R/W LOP_POF_POW_32KXTAL                     1'b0
+    8:7     R/W LOP_POF_SWR_CFG                         2'b0
+    9       R/W LOP_POF_ENPC_AON                        1'b0
+    15:10   R   RSVD                                    6'b0
+    16      R/W LOP_POF_VDDIO_PSRAM_PC_EN               1'b1
+    17      R/W LOP_POF_VDDIO_FLASH_PC_EN               1'b1
+    18      R/W LOP_POF_XTAL                            1'b0
+    19      R/W LOP_POF_AON_GATED_EN                    1'b0
+    20      R/W LOP_POF_CAL                             1'b1
+    23:21   R   RSVD                                    3'b0
+    26:24   R/W LOP_POF_XTAL_MODE                       3'b100
+    31:27   R   RSVD                                    5'b0
+ */
+typedef volatile union _AON_LOP_RG3X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RSVD_3: 1;
+        uint32_t LOP_POF_ENPC_DIGI: 1;
+        uint32_t LOP_POF_POWLDO_DIGI: 1;
+        uint32_t LOP_POF_ENPC_CORE: 1;
+        uint32_t LOP_POF_POW_BIAS: 1;
+        uint32_t LOP_POF_POW_32KOSC: 1;
+        uint32_t LOP_POF_POW_32KXTAL: 1;
+        uint32_t LOP_POF_SWR_CFG: 2;
+        uint32_t LOP_POF_ENPC_AON: 1;
+        uint32_t RSVD_2: 6;
+        uint32_t LOP_POF_VDDIO_PSRAM_PC_EN: 1;
+        uint32_t LOP_POF_VDDIO_FLASH_PC_EN: 1;
+        uint32_t LOP_POF_XTAL: 1;
+        uint32_t LOP_POF_AON_GATED_EN: 1;
+        uint32_t LOP_POF_CAL: 1;
+        uint32_t RSVD_1: 3;
+        uint32_t LOP_POF_XTAL_MODE: 3;
+        uint32_t RSVD: 5;
+    };
+} AON_LOP_RG3X_TYPE;
+
+/* 0xAC0    0x4000_0ac0
+    0       R/W LOP_POF_BUCK_PFM_IHALF                  1'b1
+    1       R/W LOP_POF_BUCK_EN_OCP_IBON                1'b0
+    5:2     R/W LOP_POF_BUCK_PFM_ICOMP                  4'b0010
+    9:6     R/W LOP_POF_BUCK_PFM_ISCH                   4'b0010
+    10      R/W LOP_POF_BUCK_ENOCPPS_H                  1'b1
+    11      R/W LOP_POF_LDO_ENLDO311_IB20nA             1'b1
+    14:12   R   RSVD                                    3'b0
+    15      R/W LOP_POF_BUCK_ENOCPPFM_H                 1'b1
+    18:16   R/W LOP_POF_LDO_EN_DL_LDO311                3'b111
+    20:19   R/W LOP_POF_BUCK_OCPRES_H                   2'b01
+    21      R/W LOP_POF_BUCK_OCPSEL_H                   1'b1
+    24:22   R/W LOP_POF_BUCK_VREFOCP_H                  3'b110
+    25      R/W LOP_POF_BUCK_ENOFFSAWPFM_H              1'b1
+    26      R/W LOP_POF_BUCK_PFM_COT_EN                 1'b0
+    27      R/W LOP_POF_BUCK_PFM_AOT_EN                 1'b0
+    29:28   R/W LOP_POF_IBSEL_TONCOMP                   2'b00
+    30      R/W LOP_POF_MBIAS_POW_EBIAS_AUXADC          1'b1
+    31      R/W LOP_POF_AON_BUCK_LOW_IQ_ZCD_32K_CLK_EN  1'b1
+ */
+typedef volatile union _AON_LOP_RG4X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t LOP_POF_BUCK_PFM_IHALF: 1;
+        uint32_t LOP_POF_BUCK_EN_OCP_IBON: 1;
+        uint32_t LOP_POF_BUCK_PFM_ICOMP: 4;
+        uint32_t LOP_POF_BUCK_PFM_ISCH: 4;
+        uint32_t LOP_POF_BUCK_ENOCPPS_H: 1;
+        uint32_t LOP_POF_LDO_ENLDO311_IB20nA: 1;
+        uint32_t RSVD: 3;
+        uint32_t LOP_POF_BUCK_ENOCPPFM_H: 1;
+        uint32_t LOP_POF_LDO_EN_DL_LDO311: 3;
+        uint32_t LOP_POF_BUCK_OCPRES_H: 2;
+        uint32_t LOP_POF_BUCK_OCPSEL_H: 1;
+        uint32_t LOP_POF_BUCK_VREFOCP_H: 3;
+        uint32_t LOP_POF_BUCK_ENOFFSAWPFM_H: 1;
+        uint32_t LOP_POF_BUCK_PFM_COT_EN: 1;
+        uint32_t LOP_POF_BUCK_PFM_AOT_EN: 1;
+        uint32_t LOP_POF_IBSEL_TONCOMP: 2;
+        uint32_t LOP_POF_MBIAS_POW_EBIAS_AUXADC: 1;
+        uint32_t LOP_POF_AON_BUCK_LOW_IQ_ZCD_32K_CLK_EN: 1;
+    };
+} AON_LOP_RG4X_TYPE;
+
+/* 0xAC4    0x4000_0ac4
+    0       R/W LOP_POF_BUCK_ENOCPS                     1'b1
+    1       R/W LOP_POF_BUCK_POW_ZCD                    1'b1
+    2       R/W LOP_POF_LDO_EN_DMYL_50U_LDODIGI         1'b0
+    3       R/W LOP_POF_LDO_EN_DMYL_200U_LDODIGI        1'b0
+    4       R/W LOP_POF_IB_500N_TONCOMP_EN              1'b0
+    5       R/W LOP_POF_IB_500N_COTCOMP_EN              1'b0
+    12:6    R/W LOP_POF_BUCK_ZCDOFFSET                  7'b0
+    13      R/W LOP_POF_BUCK_POW_LowIq_ZCD              1'b0
+    14      R/W LOP_POF_BUCK_STICKY_CODE_STATE1         1'b0
+    15      R/W LOP_POF_BUCK_FORCE_CODE_STATE1          1'b0
+    22:16   R   RSVD                                    7'b0
+    23      R   RSVD                                    1'b0
+    24      R/W LOP_POF_BUCK_STICKY_CODE_STATE2         1'b0
+    25      R/W LOP_POF_BUCK_FORCE_CODE_STATE2          1'b0
+    31:26   R/W LOP_POF_D300k_REG_MANU_CCOT             6'b001000
+ */
+typedef volatile union _AON_LOP_RG5X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t LOP_POF_BUCK_ENOCPS: 1;
+        uint32_t LOP_POF_BUCK_POW_ZCD: 1;
+        uint32_t LOP_POF_LDO_EN_DMYL_50U_LDODIGI: 1;
+        uint32_t LOP_POF_LDO_EN_DMYL_200U_LDODIGI: 1;
+        uint32_t LOP_POF_IB_500N_TONCOMP_EN: 1;
+        uint32_t LOP_POF_IB_500N_COTCOMP_EN: 1;
+        uint32_t LOP_POF_BUCK_ZCDOFFSET: 7;
+        uint32_t LOP_POF_BUCK_POW_LowIq_ZCD: 1;
+        uint32_t LOP_POF_BUCK_STICKY_CODE_STATE1: 1;
+        uint32_t LOP_POF_BUCK_FORCE_CODE_STATE1: 1;
+        uint32_t RSVD_1: 7;
+        uint32_t RSVD: 1;
+        uint32_t LOP_POF_BUCK_STICKY_CODE_STATE2: 1;
+        uint32_t LOP_POF_BUCK_FORCE_CODE_STATE2: 1;
+        uint32_t LOP_POF_D300k_REG_MANU_CCOT: 6;
+    };
+} AON_LOP_RG5X_TYPE;
+
+/* 0xAC8    0x4000_0ac8
+    0       R/W LOP_LPS_TIMER_WAKEUP                    1'b0
+    1       R/W LOP_RFC_RET                             1'b0
+    2       R/W LOP_MODEM_RET                           1'b0
+    3       R/W LOP_BZ_RET                              1'b0
+    4       R/W LOP_BLE_RET                             1'b0
+    5       R/W LOP_PF_RET                              1'b0
+    6       R/W LOP_DP_MODEM_RET                        1'b0
+    7       R/W LOP_ZB_RET                              1'b0
+    31:8    R   RSVD                                    24'h0
+ */
+typedef volatile union _AON_LOP_RG6X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t LOP_LPS_TIMER_WAKEUP: 1;
+        uint32_t LOP_RFC_RET: 1;
+        uint32_t LOP_MODEM_RET: 1;
+        uint32_t LOP_BZ_RET: 1;
+        uint32_t LOP_BLE_RET: 1;
+        uint32_t LOP_PF_RET: 1;
+        uint32_t LOP_DP_MODEM_RET: 1;
+        uint32_t LOP_ZB_RET: 1;
+        uint32_t RSVD: 24;
+    };
+} AON_LOP_RG6X_TYPE;
+
+/* 0xACC    0x4000_0acc
+    5:0     R/W LOP_BIAS_delay                          6'h30
+    11:6    R/W LOP_LDO_delay                           6'h30
+    15:12   R/W LOP_PLL_delay                           4'h3
+    23:16   R/W LOP_SWR_delay                           8'hc0
+    31:24   R/W LOP_XTAL_delay                          8'hc0
+ */
+typedef volatile union _AON_LOP_RG7X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t LOP_BIAS_delay: 6;
+        uint32_t LOP_LDO_delay: 6;
+        uint32_t LOP_PLL_delay: 4;
+        uint32_t LOP_SWR_delay: 8;
+        uint32_t LOP_XTAL_delay: 8;
+    };
+} AON_LOP_RG7X_TYPE;
+
+/* 0xAD0    0x4000_0ad0
+    5:0     R/W LOP_ENPC_CORE_BIG_delay                 6'h20
+    11:6    R/W LOP_ENPC_CORE_SMALL_delay               6'h20
+    15:12   R/W LOP_RG8X_Dummy_0                        4'h3
+    23:16   R/W LOP_VDDIO_PC_VG2_delay                  8'hc0
+    31:24   R/W LOP_VDDIO_PC_VG1_delay                  8'hc0
+ */
+typedef volatile union _AON_LOP_RG8X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t LOP_ENPC_CORE_BIG_delay: 6;
+        uint32_t LOP_ENPC_CORE_SMALL_delay: 6;
+        uint32_t LOP_RG8X_Dummy_0: 4;
+        uint32_t LOP_VDDIO_PC_VG2_delay: 8;
+        uint32_t LOP_VDDIO_PC_VG1_delay: 8;
+    };
+} AON_LOP_RG8X_TYPE;
+
+/* 0xAD4    0x4000_0ad4
+    4:0     R/W LOP_PON_VDIGI_TUNE_STATE1               5'b10000
+    9:5     R/W LOP_PON_VDIGI_TUNE_STATE2               5'b10100
+    14:10   R/W LOP_PON_VDIGI_TUNE_STATE3               5'b10100
+    15      R   RSVD                                    1'b0
+    31:16   R   RSVD                                    16'h0
+ */
+typedef volatile union _AON_LOP_RG9X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t LOP_PON_VDIGI_TUNE_STATE1: 5;
+        uint32_t LOP_PON_VDIGI_TUNE_STATE2: 5;
+        uint32_t LOP_PON_VDIGI_TUNE_STATE3: 5;
+        uint32_t RSVD_1: 1;
+        uint32_t RSVD: 16;
+    };
+} AON_LOP_RG9X_TYPE;
+
+/* 0xAD8    0x4000_0ad8
+    4:0     R/W LOP_POF_VDIGI_TUNE_STATE1               5'b10100
+    9:5     R/W LOP_POF_VDIGI_TUNE_STATE2               5'b10000
+    12:10   R/W LOP_POF_MBIAS_VR_SEL_LDO311_STATE1      3'b101
+    15:13   R/W LOP_POF_MBIAS_VR_SEL_LDO311_STATE2      3'b010
+    20:16   R/W LOP_VAON2VPON_PC_OFF_delay              5'h0f
+    31:21   R   RSVD                                    11'h0
+ */
+typedef volatile union _AON_LOP_RG10X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t LOP_POF_VDIGI_TUNE_STATE1: 5;
+        uint32_t LOP_POF_VDIGI_TUNE_STATE2: 5;
+        uint32_t LOP_POF_MBIAS_VR_SEL_LDO311_STATE1: 3;
+        uint32_t LOP_POF_MBIAS_VR_SEL_LDO311_STATE2: 3;
+        uint32_t LOP_VAON2VPON_PC_OFF_delay: 5;
+        uint32_t RSVD: 11;
+    };
+} AON_LOP_RG10X_TYPE;
+
+/* 0xC00    0x4000_0c00
+    5:0     R   MBIAS_REG0X_SD_TUNE_RO                  6'b0
+    15:6    R/W MBIAS_REG0X_DUMMY1                      10'b1010101010
+    18:16   R/W MBIAS_LPBG_VR1200                       3'b100
+    21:19   R/W MBIAS_LPBG_R2                           3'b100
+    24:22   R/W MBIAS_BG_BG_R1                          3'b100
+    25      R/W MBIAS_POW_EBIAS_AUXADC                  1'b1
+    28:26   R/W MBIAS_VR_SEL_LDO311                     3'b010
+    30:29   R/W MBIAS_REG1X_DUMMY2                      2'b0
+    31      R/W MBIAS_REG1X_DUMMY1                      1'b1
+ */
+typedef volatile union _AON_REG0X_MBIAS_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t MBIAS_REG0X_SD_TUNE_RO: 6;
+        uint32_t MBIAS_REG0X_DUMMY1: 10;
+        uint32_t MBIAS_LPBG_VR1200: 3;
+        uint32_t MBIAS_LPBG_R2: 3;
+        uint32_t MBIAS_BG_BG_R1: 3;
+        uint32_t MBIAS_POW_EBIAS_AUXADC: 1;
+        uint32_t MBIAS_VR_SEL_LDO311: 3;
+        uint32_t MBIAS_REG1X_DUMMY2: 2;
+        uint32_t MBIAS_REG1X_DUMMY1: 1;
+    };
+} AON_REG0X_MBIAS_TYPE;
+
+/* 0xC04    0x4000_0c04
+    2:0     R/W MBIAS_REG2X_DUMMY1                      3'b101
+    6:3     R/W MBIAS_VR_SEL_LDORET                     4'b1100
+    9:7     R/W MBIAS_BG_VREF_SEL_L                     3'b100
+    12:10   R/W MBIAS_BG_VREF_SEL_H                     3'b100
+    13      R/W MBIAS_BG_Efuse_Data_H                   1'b0
+    14      R/W MBIAS_BG_DIGI_RST_H                     1'b0
+    15      R/W MBIAS_REG2X_DUMMY2                      1'b1
+    31:16   R   RSVD                                    16'b1111111100000000
+ */
+typedef volatile union _AON_REG2X_MBIAS_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t MBIAS_REG2X_DUMMY1: 3;
+        uint32_t MBIAS_VR_SEL_LDORET: 4;
+        uint32_t MBIAS_BG_VREF_SEL_L: 3;
+        uint32_t MBIAS_BG_VREF_SEL_H: 3;
+        uint32_t MBIAS_BG_Efuse_Data_H: 1;
+        uint32_t MBIAS_BG_DIGI_RST_H: 1;
+        uint32_t MBIAS_REG2X_DUMMY2: 1;
+        uint32_t RSVD: 16;
+    };
+} AON_REG2X_MBIAS_TYPE;
+
+/* 0xC08    0x4000_0c08
+    0       R   MBIAS_Q1_Efuse                          1'b0
+    1       R   MBIAS_Q2_Efuse                          1'b0
+    2       R   MBIAS_CKOUT0X_DUMMY2                    1'b0
+    3       R   MBIAS_CKOUT0X_DUMMY3                    1'b0
+    4       R   MBIAS_CKOUT0X_DUMMY4                    1'b0
+    5       R   MBIAS_CKOUT0X_DUMMY5                    1'b0
+    6       R   MBIAS_CKOUT0X_DUMMY6                    1'b0
+    7       R   MBIAS_CKOUT0X_DUMMY7                    1'b0
+    8       R   MBIAS_CKOUT0X_DUMMY8                    1'b0
+    9       R   MBIAS_CKOUT0X_DUMMY9                    1'b0
+    10      R   MBIAS_CKOUT0X_DUMMY10                   1'b0
+    11      R   MBIAS_CKOUT0X_DUMMY11                   1'b0
+    12      R   MBIAS_CKOUT0X_DUMMY12                   1'b0
+    13      R   MBIAS_CKOUT0X_DUMMY13                   1'b0
+    14      R   MBIAS_BGOK_L                            1'b0
+    15      R   MBIAS_PORB_LDO311_L                     1'b0
+    31:16   R   MBIAS_CKOUT0X_DUMMY14                   16'b0
+ */
+typedef volatile union _AON_C_KOUT0X_MBIAS_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t MBIAS_Q1_Efuse: 1;
+        uint32_t MBIAS_Q2_Efuse: 1;
+        uint32_t MBIAS_CKOUT0X_DUMMY2: 1;
+        uint32_t MBIAS_CKOUT0X_DUMMY3: 1;
+        uint32_t MBIAS_CKOUT0X_DUMMY4: 1;
+        uint32_t MBIAS_CKOUT0X_DUMMY5: 1;
+        uint32_t MBIAS_CKOUT0X_DUMMY6: 1;
+        uint32_t MBIAS_CKOUT0X_DUMMY7: 1;
+        uint32_t MBIAS_CKOUT0X_DUMMY8: 1;
+        uint32_t MBIAS_CKOUT0X_DUMMY9: 1;
+        uint32_t MBIAS_CKOUT0X_DUMMY10: 1;
+        uint32_t MBIAS_CKOUT0X_DUMMY11: 1;
+        uint32_t MBIAS_CKOUT0X_DUMMY12: 1;
+        uint32_t MBIAS_CKOUT0X_DUMMY13: 1;
+        uint32_t MBIAS_BGOK_L: 1;
+        uint32_t MBIAS_PORB_LDO311_L: 1;
+        uint32_t MBIAS_CKOUT0X_DUMMY14: 16;
+    };
+} AON_C_KOUT0X_MBIAS_TYPE;
+
+/* 0xC10    0x4000_0c10
+    0       R/W LDO_REG0X_DUMMY1                        1'b0
+    1       R/W LDO_ENPC_LDODIGI                        1'b0
+    2       R/W LDO_POW_LDODIGI                         1'b1
+    5:3     R/W LDO_EN_DL_LDO311                        3'b000
+    7:6     R/W LDO_REG0X_DUMMY0                        2'b01
+    8       R/W LDO_ENLDO311_IB20nA                     1'b0
+    13:9    R/W LDO_TUNE_LDODIGI                        5'b10100
+    14      R/W LDO_EN_DMYL_50U_LDODIGI                 1'b0
+    15      R/W LDO_EN_DMYL_200U_LDODIGI                1'b0
+    17:16   R/W LDO_REG1X_DUMMY1                        2'b11
+    18      R/W LDO_ENPC_CORE_SMALL                     1'b0
+    19      R/W LDO_ENPC_CORE_BIG                       1'b0
+    21:20   R/W LDO_REG1X_DUMMY1                        2'b01
+    22      R/W LDO_POW_LDODIGI_FB                      1'b0
+    24:23   R/W LDO_COMPTUNE_LDORET                     2'b11
+    30:25   R/W LDO_REG1X_DUMMY2                        6'b011111
+    31      R/W LDO_POW_LDORET                          1'b1
+ */
+typedef volatile union _AON_REG0X_LDO_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t LDO_REG0X_DUMMY1: 1;
+        uint32_t LDO_ENPC_LDODIGI: 1;
+        uint32_t LDO_POW_LDODIGI: 1;
+        uint32_t LDO_EN_DL_LDO311: 3;
+        uint32_t LDO_REG0X_DUMMY0: 2;
+        uint32_t LDO_ENLDO311_IB20nA: 1;
+        uint32_t LDO_TUNE_LDODIGI: 5;
+        uint32_t LDO_EN_DMYL_50U_LDODIGI: 1;
+        uint32_t LDO_EN_DMYL_200U_LDODIGI: 1;
+        uint32_t LDO_REG1X_DUMMY1_1: 2;
+        uint32_t LDO_ENPC_CORE_SMALL: 1;
+        uint32_t LDO_ENPC_CORE_BIG: 1;
+        uint32_t LDO_REG1X_DUMMY1: 2;
+        uint32_t LDO_POW_LDODIGI_FB: 1;
+        uint32_t LDO_COMPTUNE_LDORET: 2;
+        uint32_t LDO_REG1X_DUMMY2: 6;
+        uint32_t LDO_POW_LDORET: 1;
+    };
+} AON_REG0X_LDO_TYPE;
+
+/* 0xC14    0x4000_0c14
+    0       R/W LDO_POW_EFUSE                           1'b0
+    1       R/W LDO_POW_EFUSE_DL_PC1                    1'b0
+    2       R/W LDO_POW_EFUSE_DL_PC2                    1'b0
+    3       R/W LDO_POW_EFUSE_PC1                       1'b0
+    4       R/W LDO_POW_EFUSE_PC2                       1'b0
+    5       R/W LDO_PCUT_EHVT_VCORE                     1'b0
+    6       R/W LDO_PCUT_EHVT_DVDD                      1'b1
+    7       R/W LDO_PCUT_VPONSEGLCD                     1'b0
+    8       R/W LDO_PCUT_VAONVDIGUSB                    1'b1
+    14:9    R/W LDO_REG2X_DUMMY1                        6'b111010
+    15      R/W LDO_ENPC_VPONVAON                       1'b1
+    18:16   R/W LDO_EFUSE_CSET                          3'b100
+    21:19   R/W LDO_EFUSE_ISET                          3'b100
+    24:22   R/W LDO_EFUSE_RSET                          3'b100
+    31:25   R/W LDO_EFUSE_TUNE                          7'b0111010
+ */
+typedef volatile union _AON_REG2X_LDO_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t LDO_POW_EFUSE: 1;
+        uint32_t LDO_POW_EFUSE_DL_PC1: 1;
+        uint32_t LDO_POW_EFUSE_DL_PC2: 1;
+        uint32_t LDO_POW_EFUSE_PC1: 1;
+        uint32_t LDO_POW_EFUSE_PC2: 1;
+        uint32_t LDO_PCUT_EHVT_VCORE: 1;
+        uint32_t LDO_PCUT_EHVT_DVDD: 1;
+        uint32_t LDO_PCUT_VPONSEGLCD: 1;
+        uint32_t LDO_PCUT_VAONVDIGUSB: 1;
+        uint32_t LDO_REG2X_DUMMY1: 6;
+        uint32_t LDO_ENPC_VPONVAON: 1;
+        uint32_t LDO_EFUSE_CSET: 3;
+        uint32_t LDO_EFUSE_ISET: 3;
+        uint32_t LDO_EFUSE_RSET: 3;
+        uint32_t LDO_EFUSE_TUNE: 7;
+    };
+} AON_REG2X_LDO_TYPE;
+
+/* 0xC18    0x4000_0c18
+    0       R/W LCD_REG0X_DUMMY1                        1'b0
+    1       R/W LCD_EN_LCD                              1'b0
+    2       R/W LCD_BIAS_SEL                            1'b0
+    3       R   LCD_EN_RES_L                            1'b1
+    13:4    R/W LCD_REG0X_DUMMY2                        10'b0101010101
+    14      R/W CKOUT_EN_DEBUG                          1'b1
+    15      R/W LCD_REG0X_DUMMY3                        1'b0
+    31:16   R   RSVD                                    16'b1010101010101010
+ */
+typedef volatile union _AON_REG0X_LCD_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t LCD_REG0X_DUMMY1: 1;
+        uint32_t LCD_EN_LCD: 1;
+        uint32_t LCD_BIAS_SEL: 1;
+        uint32_t LCD_EN_RES_L: 1;
+        uint32_t LCD_REG0X_DUMMY2: 10;
+        uint32_t CKOUT_EN_DEBUG: 1;
+        uint32_t LCD_REG0X_DUMMY3: 1;
+        uint32_t RSVD: 16;
+    };
+} AON_REG0X_LCD_TYPE;
+
+/* 0xC20    0x4000_0c20
+    5:0     R/W BUCK_SWRTUNE_H                          6'b011101
+    6       R/W BUCK_ADD_SAW_CURRENT                    1'b1
+    7       R/W BUCK_OCFB_SEL_H                         1'b0
+    9:8     R/W BUCK_R3_H                               2'b01
+    11:10   R/W BUCK_R2_H                               2'b01
+    13:12   R/W BUCK_R1_H                               2'b01
+    15:14   R/W BUCK_C3_H                               2'b01
+    17:16   R/W BUCK_C2_H                               2'b01
+    19:18   R/W BUCK_C1_H                               2'b01
+    20      R/W BUCK_BPSSR_H                            1'b1
+    21      R/W BUCK_ENSR_H                             1'b1
+    22      R/W BUCK_PFM_COT_EN                         1'b0
+    23      R/W BUCK_PFM_AOT_EN                         1'b1
+    29:24   R/W BUCK_LDOTUNE_H                          6'b011101
+    31:30   R/W BUCK_NONOVERLAP_SDZ_H                   2'b01
+ */
+typedef volatile union _AON_REG0X_BUCK_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t BUCK_SWRTUNE_H: 6;
+        uint32_t BUCK_ADD_SAW_CURRENT: 1;
+        uint32_t BUCK_OCFB_SEL_H: 1;
+        uint32_t BUCK_R3_H: 2;
+        uint32_t BUCK_R2_H: 2;
+        uint32_t BUCK_R1_H: 2;
+        uint32_t BUCK_C3_H: 2;
+        uint32_t BUCK_C2_H: 2;
+        uint32_t BUCK_C1_H: 2;
+        uint32_t BUCK_BPSSR_H: 1;
+        uint32_t BUCK_ENSR_H: 1;
+        uint32_t BUCK_PFM_COT_EN: 1;
+        uint32_t BUCK_PFM_AOT_EN: 1;
+        uint32_t BUCK_LDOTUNE_H: 6;
+        uint32_t BUCK_NONOVERLAP_SDZ_H: 2;
+    };
+} AON_REG0X_BUCK_TYPE;
+
+/* 0xC24    0x4000_0c24
+    0       R   BUCK_SS_OVER_H                          1'b1
+    1       R   BUCK_SS_START_H                         1'b1
+    5:2     R   BUCK_VREFPFM_H                          4'b1011
+    6       R/W BUCK_IB_500N_TONCOMP_EN                 1'b1
+    7       R/W BUCK_IB_500N_COTCOMP_EN                 1'b1
+    11:8    R/W BUCK_PFM_ICOMP                          4'b0010
+    12      R/W BUCK_ENPFMDIV_H                         1'b0
+    13      R/W BUCK_PFM_IHALF                          1'b0
+    14      R/W BUCK_ICOT2X                             1'b1
+    15      R/W BUCK_VR_COT_SET                         1'b0
+    19:16   R/W BUCK_PFM_ISCH                           4'b0010
+    21:20   R/W BUCK_ClampH_VCH_SEL                     2'b01
+    22      R/W BUCK_EN_WaitSampleOver                  1'b1
+    23      R/W BUCK_EN_ForceOFFtoZCD                   1'b1
+    24      R/W BUCK_PFM_SEL                            1'b0
+    25      R/W BUCK_EN_OCPrst_sel                      1'b0
+    26      R/W BUCK_EN_MinON_RAMP                      1'b1
+    27      R/W BUCK_PFM_COMP_SEL                       1'b1
+    28      R/W BUCK_REG3X_DUMMY1                       1'b1
+    29      R/W BUCK_ENOCPPS_H                          1'b0
+    31:30   R/W BUCK_ClampL_RTUNE                       2'b10
+ */
+typedef volatile union _AON_REG2X_BUCK_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t BUCK_SS_OVER_H: 1;
+        uint32_t BUCK_SS_START_H: 1;
+        uint32_t BUCK_VREFPFM_H: 4;
+        uint32_t BUCK_IB_500N_TONCOMP_EN: 1;
+        uint32_t BUCK_IB_500N_COTCOMP_EN: 1;
+        uint32_t BUCK_PFM_ICOMP: 4;
+        uint32_t BUCK_ENPFMDIV_H: 1;
+        uint32_t BUCK_PFM_IHALF: 1;
+        uint32_t BUCK_ICOT2X: 1;
+        uint32_t BUCK_VR_COT_SET: 1;
+        uint32_t BUCK_PFM_ISCH: 4;
+        uint32_t BUCK_ClampH_VCH_SEL: 2;
+        uint32_t BUCK_EN_WaitSampleOver: 1;
+        uint32_t BUCK_EN_ForceOFFtoZCD: 1;
+        uint32_t BUCK_PFM_SEL: 1;
+        uint32_t BUCK_EN_OCPrst_sel: 1;
+        uint32_t BUCK_EN_MinON_RAMP: 1;
+        uint32_t BUCK_PFM_COMP_SEL: 1;
+        uint32_t BUCK_REG3X_DUMMY1: 1;
+        uint32_t BUCK_ENOCPPS_H: 1;
+        uint32_t BUCK_ClampL_RTUNE: 2;
+    };
+} AON_REG2X_BUCK_TYPE;
+
+/* 0xC28    0x4000_0c28
+    3:0     R/W BUCK_SAW_FREQ                           4'b1000
+    4       R/W BUCK_SAW_VALID                          1'b0
+    5       R/W BUCK_SAWCTL_H                           1'b1
+    6       R/W BUCK_ENOFFSAWPFM_H                      1'b1
+    7       R/W BUCK_ENOFFSAWLDO_H                      1'b1
+    10:8    R/W BUCK_VREFOCP_H                          3'b001
+    11      R/W BUCK_OCPSEL_H                           1'b1
+    13:12   R/W BUCK_OCPRES_H                           2'b10
+    14      R/W BUCK_ENOCPPFM_H                         1'b1
+    15      R/W BUCK_ENOCPPWM_H                         1'b1
+    16      R/W BUCK_BP_MiniON_RAMPdelay                1'b0
+    19:17   R/W BUCK_OFFT_H                             3'b100
+    24:20   R   BUCK_VREFPWMSS_H                        5'b00000
+    25      R/W BUCK_FPWMANA_H                          1'b1
+    26      R/W BUCK_ENFPWMDELAY_H                      1'b1
+    27      R/W BUCK_TYPE3_H                            1'b1
+    29:28   R/W BUCK_FPWMCTL_H                          2'b00
+    30      R/W BUCK_ENOCPMUX_H                         1'b0
+    31      R/W BUCK_ENVREFSS_H                         1'b1
+ */
+typedef volatile union _AON_REG4X_BUCK_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t BUCK_SAW_FREQ: 4;
+        uint32_t BUCK_SAW_VALID: 1;
+        uint32_t BUCK_SAWCTL_H: 1;
+        uint32_t BUCK_ENOFFSAWPFM_H: 1;
+        uint32_t BUCK_ENOFFSAWLDO_H: 1;
+        uint32_t BUCK_VREFOCP_H: 3;
+        uint32_t BUCK_OCPSEL_H: 1;
+        uint32_t BUCK_OCPRES_H: 2;
+        uint32_t BUCK_ENOCPPFM_H: 1;
+        uint32_t BUCK_ENOCPPWM_H: 1;
+        uint32_t BUCK_BP_MiniON_RAMPdelay: 1;
+        uint32_t BUCK_OFFT_H: 3;
+        uint32_t BUCK_VREFPWMSS_H: 5;
+        uint32_t BUCK_FPWMANA_H: 1;
+        uint32_t BUCK_ENFPWMDELAY_H: 1;
+        uint32_t BUCK_TYPE3_H: 1;
+        uint32_t BUCK_FPWMCTL_H: 2;
+        uint32_t BUCK_ENOCPMUX_H: 1;
+        uint32_t BUCK_ENVREFSS_H: 1;
+    };
+} AON_REG4X_BUCK_TYPE;
+
+/* 0xC2C    0x4000_0c2c
+    0       R/W BUCK_EN_MinON                           1'b1
+    1       R/W BUCK_ENOCPS                             1'b1
+    7:2     R   BUCK_CCOT_H                             6'b001000
+    8       R/W BUCK_POW_CLAMP_H                        1'b0
+    9       R/W BUCK_POW_EA_Initial                     1'b1
+    10      R/W BUCK_ENLDO15_LXFB                       1'b0
+    13:11   R/W BUCK_VREFPWM_H                          3'b011
+    14      R/W BUCK_PMOS_DRIL_H                        1'b1
+    15      R/W BUCK_PMOS_DRIH_H                        1'b1
+    16      R/W BUCK_ZCD_NIZCD_SEL                      1'b0
+    17      R/W BUCK_ZCD_NI_delay_SEL                   1'b0
+    18      R/W BUCK_ZCD_NI_SEL                         1'b0
+    19      R/W BUCK_OCPrst_ext                         1'b0
+    20      R/W BUCK_LDO_OCP_ENB                        1'b0
+    21      R/W BUCK_CK_PWM_SEL                         1'b0
+    22      R/W BUCK_EN_R1OFF_H                         1'b0
+    23      R/W BUCK_POW_EA_IqEhance_H                  1'b0
+    24      R/W BUCK_POW_EA_Iqx3_H                      1'b0
+    25      R/W BUCK_POW_EA_Iqx2_H                      1'b0
+    26      R/W BUCK_EN_PDMC_H                          1'b0
+    27      R/W BUCK_EN_IMIRROR_IPTAT_Gating            1'b0
+    28      R/W BUCK_FPWM_H                             1'b0
+    29      R/W BUCK_ENLDO_H                            1'b0
+    30      R/W BUCK_ENSWR_H                            1'b0
+    31      R/W BUCK_ENBIAS_H                           1'b0
+ */
+typedef volatile union _AON_REG6X_BUCK_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t BUCK_EN_MinON: 1;
+        uint32_t BUCK_ENOCPS: 1;
+        uint32_t BUCK_CCOT_H: 6;
+        uint32_t BUCK_POW_CLAMP_H: 1;
+        uint32_t BUCK_POW_EA_Initial: 1;
+        uint32_t BUCK_ENLDO15_LXFB: 1;
+        uint32_t BUCK_VREFPWM_H: 3;
+        uint32_t BUCK_PMOS_DRIL_H: 1;
+        uint32_t BUCK_PMOS_DRIH_H: 1;
+        uint32_t BUCK_ZCD_NIZCD_SEL: 1;
+        uint32_t BUCK_ZCD_NI_delay_SEL: 1;
+        uint32_t BUCK_ZCD_NI_SEL: 1;
+        uint32_t BUCK_OCPrst_ext: 1;
+        uint32_t BUCK_LDO_OCP_ENB: 1;
+        uint32_t BUCK_CK_PWM_SEL: 1;
+        uint32_t BUCK_EN_R1OFF_H: 1;
+        uint32_t BUCK_POW_EA_IqEhance_H: 1;
+        uint32_t BUCK_POW_EA_Iqx3_H: 1;
+        uint32_t BUCK_POW_EA_Iqx2_H: 1;
+        uint32_t BUCK_EN_PDMC_H: 1;
+        uint32_t BUCK_EN_IMIRROR_IPTAT_Gating: 1;
+        uint32_t BUCK_FPWM_H: 1;
+        uint32_t BUCK_ENLDO_H: 1;
+        uint32_t BUCK_ENSWR_H: 1;
+        uint32_t BUCK_ENBIAS_H: 1;
+    };
+} AON_REG6X_BUCK_TYPE;
+
+/* 0xC30    0x4000_0c30
+    6:0     R/W BUCK_ZCDOFFSET                          7'b0110000
+    7       R/W BUCK_EN_OCP_IBON                        1'b1
+    8       R/W BUCK_PFM_COMP_AFTER_OCP                 1'b0
+    9       R/W BUCK_TON_PS_HV                          1'b0
+    11:10   R/W BUCK_IBSEL_TONCOMP                      2'b01
+    13:12   R/W BUCK_MinONtime_sel                      2'b01
+    15:14   R/W BUCK_ZCD_LOWIQ_LOGIC_TUNE_STICKY        2'b10
+    16      R   BUCK_32K_CLK_IN                         1'b0
+    17      R/W BUCK_POW_LowIq_ZCD                      1'b0
+    18      R/W BUCK_STICKY_CODE                        1'b0
+    19      R/W BUCK_FORCE_CODE                         1'b0
+    20      R/W BUCK_POW_ClampLX                        1'b1
+    21      R/W BUCK_POW_ZCD                            1'b0
+    23:22   R/W BUCK_ZCD_LOWIQ_LOGIC_TUNE_WAIT          2'b00
+    25:24   R/W BUCK_ZCD_SDZ2d                          2'b10
+    28:26   R/W BUCK_ZCD_SDZ2                           3'b100
+    30:29   R/W BUCK_ZCD_SDZ1                           2'b10
+    31      R/W BUCK_SEL_ZCD_LowIQ                      1'b0
+ */
+typedef volatile union _AON_REG8X_BUCK_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t BUCK_ZCDOFFSET: 7;
+        uint32_t BUCK_EN_OCP_IBON: 1;
+        uint32_t BUCK_PFM_COMP_AFTER_OCP: 1;
+        uint32_t BUCK_TON_PS_HV: 1;
+        uint32_t BUCK_IBSEL_TONCOMP: 2;
+        uint32_t BUCK_MinONtime_sel: 2;
+        uint32_t BUCK_ZCD_LOWIQ_LOGIC_TUNE_STICKY: 2;
+        uint32_t BUCK_32K_CLK_IN: 1;
+        uint32_t BUCK_POW_LowIq_ZCD: 1;
+        uint32_t BUCK_STICKY_CODE: 1;
+        uint32_t BUCK_FORCE_CODE: 1;
+        uint32_t BUCK_POW_ClampLX: 1;
+        uint32_t BUCK_POW_ZCD: 1;
+        uint32_t BUCK_ZCD_LOWIQ_LOGIC_TUNE_WAIT: 2;
+        uint32_t BUCK_ZCD_SDZ2d: 2;
+        uint32_t BUCK_ZCD_SDZ2: 3;
+        uint32_t BUCK_ZCD_SDZ1: 2;
+        uint32_t BUCK_SEL_ZCD_LowIQ: 1;
+    };
+} AON_REG8X_BUCK_TYPE;
+
+/* 0xC34    0x4000_0c34
+    0       R   BUCK_VREFSS_OVER_H                      1'b0
+    1       R   BUCK_LX_DET                             1'b0
+    2       R   BUCK_SampleOver                         1'b0
+    3       R   BUCK_LowIQ_ZCD                          1'b0
+    4       R   BUCK_UPDATE_CK                          1'b0
+    5       R   BUCK_UD_H                               1'b0
+    6       R   BUCK_PFM_RESET                          1'b0
+    7       R   BUCK_PI                                 1'b0
+    8       R   BUCK_NI                                 1'b0
+    9       R   BUCK_OCP_H                              1'b0
+    10      R   BUCK_CK_CTRL                            1'b0
+    11      R   BUCK_FPWM_H                             1'b0
+    12      R   BUCK_NGATE_HV                           1'b0
+    13      R   BUCK_PFM_COMP                           1'b0
+    14      R   BUCK_ZCD                                1'b0
+    15      R   BUCK_PFM_CTRL_FORDIG                    1'b0
+    16      R   AGND33_HG_APAD                          1'b0
+    17      R   AGND33_HG_APAD                          1'b0
+    18      R   AGND33_HG_APAD                          1'b0
+    19      R   AGND33_HG_APAD                          1'b0
+    20      R   AGND33_HG_APAD                          1'b0
+    21      R   AGND33_HG_APAD                          1'b0
+    22      R   ZCDQ<0>                                 1'b0
+    23      R   ZCDQ<1>                                 1'b0
+    24      R   ZCDQ<2>                                 1'b0
+    25      R   ZCDQ<3>                                 1'b0
+    26      R   ZCDQ<4>                                 1'b0
+    27      R   ZCDQ<5>                                 1'b0
+    28      R   ZCDQ<6>                                 1'b0
+    29      R   BUCK_CKSS                               1'b0
+    30      R   BUCK_PORB33V_H                          1'b0
+    31      R   BUCK_VREFSS_START_H                     1'b0
+ */
+typedef volatile union _AON_C_KOUT0X_BUCK_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t BUCK_VREFSS_OVER_H: 1;
+        uint32_t BUCK_LX_DET: 1;
+        uint32_t BUCK_SampleOver: 1;
+        uint32_t BUCK_LowIQ_ZCD: 1;
+        uint32_t BUCK_UPDATE_CK: 1;
+        uint32_t BUCK_UD_H: 1;
+        uint32_t BUCK_PFM_RESET: 1;
+        uint32_t BUCK_PI: 1;
+        uint32_t BUCK_NI: 1;
+        uint32_t BUCK_OCP_H: 1;
+        uint32_t BUCK_CK_CTRL: 1;
+        uint32_t BUCK_FPWM_H: 1;
+        uint32_t BUCK_NGATE_HV: 1;
+        uint32_t BUCK_PFM_COMP: 1;
+        uint32_t BUCK_ZCD: 1;
+        uint32_t BUCK_PFM_CTRL_FORDIG: 1;
+        uint32_t AGND33_HG_APAD_5: 1;
+        uint32_t AGND33_HG_APAD_4: 1;
+        uint32_t AGND33_HG_APAD_3: 1;
+        uint32_t AGND33_HG_APAD_2: 1;
+        uint32_t AGND33_HG_APAD_1: 1;
+        uint32_t AGND33_HG_APAD: 1;
+        uint32_t ZCDQ_0: 1;
+        uint32_t ZCDQ_1: 1;
+        uint32_t ZCDQ_2: 1;
+        uint32_t ZCDQ_3: 1;
+        uint32_t ZCDQ_4: 1;
+        uint32_t ZCDQ_5: 1;
+        uint32_t ZCDQ_6: 1;
+        uint32_t BUCK_CKSS: 1;
+        uint32_t BUCK_PORB33V_H: 1;
+        uint32_t BUCK_VREFSS_START_H: 1;
+    };
+} AON_C_KOUT0X_BUCK_TYPE;
+
+/* 0xC80    0x4000_0c80
+    1:0     R/W XTAL32K_CUR_MAIN                        2'b01
+    5:2     R/W XTAL32K_CUR_GM_INI                      4'b1001
+    9:6     R/W XTAL32K_CUR_GM                          4'b0101
+    11:10   R/W XTAL32K_CUR_REP                         2'b01
+    15:12   R/W XTAL32K_GM                              4'b1111
+    16      R/W EN_XTAL32K_CAP_INITIAL                  1'b1
+    17      R/W EN_XTAL32K_CAP_AWAKE                    1'b1
+    23:18   R/W XTAL32K_SC_XI                           6'b100000
+    29:24   R/W XTAL32K_SC_XO                           6'b100000
+    31:30   R/W XTAL32K_TOK                             2'b11
+ */
+typedef volatile union _AON_REG0X_32KXTAL_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t XTAL32K_CUR_MAIN: 2;
+        uint32_t XTAL32K_CUR_GM_INI: 4;
+        uint32_t XTAL32K_CUR_GM: 4;
+        uint32_t XTAL32K_CUR_REP: 2;
+        uint32_t XTAL32K_GM: 4;
+        uint32_t EN_XTAL32K_CAP_INITIAL: 1;
+        uint32_t EN_XTAL32K_CAP_AWAKE: 1;
+        uint32_t XTAL32K_SC_XI: 6;
+        uint32_t XTAL32K_SC_XO: 6;
+        uint32_t XTAL32K_TOK: 2;
+    };
+} AON_REG0X_32KXTAL_TYPE;
+
+/* 0xC84    0x4000_0c84
+    0       R/W ENB_XTAL32K_FBRES                       1'b0
+    3:1     R/W XTAL32K_GM_REP                          3'b111
+    4       R/W XTAL32K_SC_XI_EXTRA                     1'b0
+    5       R/W XTAL32K_SC_XO_EXTRA                     1'b0
+    6       R/W XTAL32K_GPIO_SEL                        1'b1
+    7       R/W REG2X_32KXTAL_DUMMY                     1'b0
+    15:8    R/W RSVD                                    8'b0
+    31:16   R/W RSVD                                    16'b0
+ */
+typedef volatile union _AON_REG2X_32KXTAL_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t ENB_XTAL32K_FBRES: 1;
+        uint32_t XTAL32K_GM_REP: 3;
+        uint32_t XTAL32K_SC_XI_EXTRA: 1;
+        uint32_t XTAL32K_SC_XO_EXTRA: 1;
+        uint32_t XTAL32K_GPIO_SEL: 1;
+        uint32_t REG2X_32KXTAL_DUMMY: 1;
+        uint32_t RSVD_1: 8;
+        uint32_t RSVD: 16;
+    };
+} AON_REG2X_32KXTAL_TYPE;
+
+/* 0xC88    0x4000_0c88
+    5:0     R/W RCAL                                    6'b100000
+    14:6    R/W REG0X_32KOSC_DUMMY                      9'b0
+    15      R/W SEL_LDO_VREF                            1'b0
+    31:16   R/W RSVD                                    16'b0
+ */
+typedef volatile union _AON_REG0X_32KOSC_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RCAL: 6;
+        uint32_t REG0X_32KOSC_DUMMY: 9;
+        uint32_t SEL_LDO_VREF: 1;
+        uint32_t RSVD: 16;
+    };
+} AON_REG0X_32KOSC_TYPE;
+
+/* 0xC8C    0x4000_0c8c
+    0       R/W POW_32KOSC                              1'b1
+    1       R/W POW_32KXTAL                             1'b1
+    2       R   OSC32K_OK                               1'b1
+    3       R   XTAL32K_OK                              1'b0
+    31:4    R/W RSVD                                    28'b0
+ */
+typedef volatile union _AON_REG_POW_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t POW_32KOSC: 1;
+        uint32_t POW_32KXTAL: 1;
+        uint32_t OSC32K_OK: 1;
+        uint32_t XTAL32K_OK: 1;
+        uint32_t RSVD: 28;
+    };
+} AON_REG_POW_TYPE;
+
+/* 0xC90    0x4000_0c90
+    0       R/W POW_40MOSC                              1'b0
+    4:1     R/W FSET_40MOSC                             4'b1000
+    15:5    R/W REG0X_40MOSC_DUMMY                      11'b0
+    31:16   R   RSVD                                    16'b0
+ */
+typedef volatile union _AON_REG0X_40MOSC_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t POW_40MOSC: 1;
+        uint32_t FSET_40MOSC: 4;
+        uint32_t REG0X_40MOSC_DUMMY: 11;
+        uint32_t RSVD: 16;
+    };
+} AON_REG0X_40MOSC_TYPE;
+
+/* 0xC94    0x4000_0c94
+    0       R/W RCAL_32K_SEL                            1'b0
+    31:1    R/W RSVD                                    31'b0
+ */
+typedef volatile union _AON_REG0X_RCAL_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RCAL_32K_SEL: 1;
+        uint32_t RSVD: 31;
+    };
+} AON_REG0X_RCAL_TYPE;
+
+/* 0xCA0    0x4000_0ca0
+    2:0     R   AON2PON_XTAL_MODE                       3'b100
+    3       R/W XTAL_DEBUG                              1'b0
+    6:4     R/W XTAL_MODE_DEBUG                         3'b100
+    7       R   AON2PON_ISO_XTAL_MODE_CTRL              1'b1
+    8       R/W XTAL_MODE_NMPC                          1'b0
+    9       R   AON2PON_POW_XTAL                        1'b0
+    15:10   R/W XTAL_MODE_DUMMY0                        6'b0
+    31:16   R/W XTAL_MODE_DUMMY1                        16'b0
+ */
+typedef volatile union _AON_BT_ANAPAR_XTAL_mode_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t AON2PON_XTAL_MODE: 3;
+        uint32_t XTAL_DEBUG: 1;
+        uint32_t XTAL_MODE_DEBUG: 3;
+        uint32_t AON2PON_ISO_XTAL_MODE_CTRL: 1;
+        uint32_t XTAL_MODE_NMPC: 1;
+        uint32_t AON2PON_POW_XTAL: 1;
+        uint32_t XTAL_MODE_DUMMY0: 6;
+        uint32_t XTAL_MODE_DUMMY1: 16;
+    };
+} AON_BT_ANAPAR_XTAL_mode_TYPE;
+
+/* 0xCA4    0x4000_0ca4
+    0       R/W XTAL_EN_XTAL_AAC_GM                     1'b0
+    1       R/W XTAL_EN_XTAL_AAC_PKDET                  1'b0
+    2       R/W XTAL_EN_XTAL_LPS                        1'b0
+    3       R/W XTAL_GATED_XTAL_OK0                     1'b0
+    6:4     R/W XTAL_AAC_PK_SEL                         3'b101
+    10:7    R/W XTAL_AAC_PK_LP_SEL                      4'b0101
+    15:11   R/W XTAL_BUF_GMN                            5'b01000
+    20:16   R/W XTAL_BUF_GMN_LP                         5'b01000
+    25:21   R/W XTAL_BUF_GMP                            5'b01000
+    30:26   R/W XTAL_BUF_GMP_LP                         5'b01000
+    31      R/W XTAL_BK_BG                              1'b0
+ */
+typedef volatile union _AON_BT_ANAPAR_XTAL0_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t XTAL_EN_XTAL_AAC_GM: 1;
+        uint32_t XTAL_EN_XTAL_AAC_PKDET: 1;
+        uint32_t XTAL_EN_XTAL_LPS: 1;
+        uint32_t XTAL_GATED_XTAL_OK0: 1;
+        uint32_t XTAL_AAC_PK_SEL: 3;
+        uint32_t XTAL_AAC_PK_LP_SEL: 4;
+        uint32_t XTAL_BUF_GMN: 5;
+        uint32_t XTAL_BUF_GMN_LP: 5;
+        uint32_t XTAL_BUF_GMP: 5;
+        uint32_t XTAL_BUF_GMP_LP: 5;
+        uint32_t XTAL_BK_BG: 1;
+    };
+} AON_BT_ANAPAR_XTAL0_TYPE;
+
+/* 0xCA8    0x4000_0ca8
+    0       R/W XTAL_DELAY_AFE                          1'b0
+    1       R/W XTAL_DELAY_USB                          1'b0
+    2       R/W XTAL_DOUBLE_OP_I                        1'b0
+    4:3     R/W XTAL_DRV_AFE                            2'b11
+    6:5     R/W XTAL_DRV_USB                            2'b11
+    8:7     R/W XTAL_DRV_RF                             2'b11
+    9       R/W XTAL_DRV_RF_LATCH                       1'b0
+    10      R/W XTAL_GATED_AFEP                         1'b0
+    11      R/W XTAL_GATED_AFEN                         1'b0
+    12      R/W XTAL_GATED_USBP                         1'b0
+    13      R/W XTAL_GATED_USBN                         1'b0
+    14      R/W XTAL_GATED_RFP                          1'b0
+    15      R/W XTAL_GATED_RFN                          1'b0
+    21:16   R/W XTAL_GM                                 6'b111111
+    27:22   R/W XTAL_GM_LP                              6'b111111
+    28      R/W XTAL_GM_SEP                             1'b0
+    29      R/W XTAL_IDOUBLE                            1'b0
+    30      R/W XTAL_IS_FINE_MANU                       1'b0
+    31      R/W XTAL_SW_LDO2PWRCUT                      1'b0
+ */
+typedef volatile union _AON_BT_ANAPAR_XTAL2_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t XTAL_DELAY_AFE: 1;
+        uint32_t XTAL_DELAY_USB: 1;
+        uint32_t XTAL_DOUBLE_OP_I: 1;
+        uint32_t XTAL_DRV_AFE: 2;
+        uint32_t XTAL_DRV_USB: 2;
+        uint32_t XTAL_DRV_RF: 2;
+        uint32_t XTAL_DRV_RF_LATCH: 1;
+        uint32_t XTAL_GATED_AFEP: 1;
+        uint32_t XTAL_GATED_AFEN: 1;
+        uint32_t XTAL_GATED_USBP: 1;
+        uint32_t XTAL_GATED_USBN: 1;
+        uint32_t XTAL_GATED_RFP: 1;
+        uint32_t XTAL_GATED_RFN: 1;
+        uint32_t XTAL_GM: 6;
+        uint32_t XTAL_GM_LP: 6;
+        uint32_t XTAL_GM_SEP: 1;
+        uint32_t XTAL_IDOUBLE: 1;
+        uint32_t XTAL_IS_FINE_MANU: 1;
+        uint32_t XTAL_SW_LDO2PWRCUT: 1;
+    };
+} AON_BT_ANAPAR_XTAL2_TYPE;
+
+/* 0xCAC    0x4000_0cac
+    5:0     R/W XTAL_GM_OK0                             6'b111111
+    11:6    R/W XTAL_IS                                 6'b111111
+    13:12   R/W XTAL_DRV_DIGI_LP                        2'b11
+    14      R/W XTAL_GDIGI_LP                           1'b0
+    15      R/W XTAL_REG4X_DUMMY1                       1'b0
+    23:16   R/W XTAL_IS_FINE                            8'b11111111
+    29:24   R/W XTAL_IS_LP                              6'b000000
+    31:30   R/W XTAL_PKDET_LP_TSEL                      2'b01
+ */
+typedef volatile union _AON_BT_ANAPAR_XTAL4_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t XTAL_GM_OK0: 6;
+        uint32_t XTAL_IS: 6;
+        uint32_t XTAL_DRV_DIGI_LP: 2;
+        uint32_t XTAL_GDIGI_LP: 1;
+        uint32_t XTAL_REG4X_DUMMY1: 1;
+        uint32_t XTAL_IS_FINE: 8;
+        uint32_t XTAL_IS_LP: 6;
+        uint32_t XTAL_PKDET_LP_TSEL: 2;
+    };
+} AON_BT_ANAPAR_XTAL4_TYPE;
+
+/* 0xCB0    0x4000_0cb0
+    2:0     R/W XTAL_LPS_CKMODE                         3'b110
+    5:3     R   AON2PON_XTAL_LDO                        3'b011
+    8:6     R   AON2PON_XTAL_LDO_OK                     3'b011
+    11:9    R/W XTAL_LPM_CKO_SEL                        3'b011
+    14:12   R   AON2PON_XTAL_SEL_TOK                    3'b101
+    15      R/W XTAL_reg_fast_settling                  1'b1
+    23:16   R/W XTAL_SC_XI                              8'b00111111
+    31:24   R/W XTAL_SC_XI_LP                           8'b11111111
+ */
+typedef volatile union _AON_BT_ANAPAR_XTAL6_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t XTAL_LPS_CKMODE: 3;
+        uint32_t AON2PON_XTAL_LDO: 3;
+        uint32_t AON2PON_XTAL_LDO_OK: 3;
+        uint32_t XTAL_LPM_CKO_SEL: 3;
+        uint32_t AON2PON_XTAL_SEL_TOK: 3;
+        uint32_t XTAL_reg_fast_settling: 1;
+        uint32_t XTAL_SC_XI: 8;
+        uint32_t XTAL_SC_XI_LP: 8;
+    };
+} AON_BT_ANAPAR_XTAL6_TYPE;
+
+/* 0xCB4    0x4000_0cb4
+    7:0     R   AON2PON_XTAL_SC_XI_OK0                  8'b11110000
+    15:8    R/W XTAL_SC_XO                              8'b00111111
+    23:16   R/W XTAL_SC_XO_LP                           8'b11111111
+    31:24   R   AON2PON_XTAL_SC_XO_OK0                  8'b11110000
+ */
+typedef volatile union _AON_BT_ANAPAR_XTAL8_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t AON2PON_XTAL_SC_XI_OK0: 8;
+        uint32_t XTAL_SC_XO: 8;
+        uint32_t XTAL_SC_XO_LP: 8;
+        uint32_t AON2PON_XTAL_SC_XO_OK0: 8;
+    };
+} AON_BT_ANAPAR_XTAL8_TYPE;
+
+/* 0xCB8    0x4000_0cb8
+    2:0     R/W XTAL_XORES_SEL                          3'b000
+    4:3     R/W XTAL_reg_stp                            2'b00
+    8:5     R/W XTAL_reg_dout_offset                    4'b0011
+    9       R/W XTAL_GATED_LPMODE                       1'b0
+    10      R/W XTAL_GATED_EN_PEAKDET_LP                1'b0
+    11      R/W XTAL_LDOPC_SEL                          1'b0
+    12      R   AON2PON_XTAL_BUF_LPS_SEL                1'b0
+    13      R/W XTAL_LPMODE_CLK_SEL                     1'b0
+    14      R/W XTAL_reg_fast_always_on                 1'b0
+    15      R/W XTAL_LPMODE_CLK_AON                     1'b0
+    16      R/W XTAL_IOP_SEL                            1'b0
+    17      R/W XTAL_EN_XTAL_PDCK_LP                    1'b0
+    20:18   R/W XTAL_LDO_SW_LP                          3'b000
+    25:21   R/W BT_ANAPAR_XTAL11_DUMMY                  5'b10000
+    26      R/W XTAL_PDC_MANUAL                         1'b0
+    27      R/W XTAL_PKDET_CMP_SWAP                     1'b0
+    28      R/W XTAL_PKDET_LOAD_SWAP                    1'b0
+    31:29   R   AON2PON_XTAL_SEL_TOK01                  3'b100
+ */
+typedef volatile union _AON_BT_ANAPAR_XTAL10_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t XTAL_XORES_SEL: 3;
+        uint32_t XTAL_reg_stp: 2;
+        uint32_t XTAL_reg_dout_offset: 4;
+        uint32_t XTAL_GATED_LPMODE: 1;
+        uint32_t XTAL_GATED_EN_PEAKDET_LP: 1;
+        uint32_t XTAL_LDOPC_SEL: 1;
+        uint32_t AON2PON_XTAL_BUF_LPS_SEL: 1;
+        uint32_t XTAL_LPMODE_CLK_SEL: 1;
+        uint32_t XTAL_reg_fast_always_on: 1;
+        uint32_t XTAL_LPMODE_CLK_AON: 1;
+        uint32_t XTAL_IOP_SEL: 1;
+        uint32_t XTAL_EN_XTAL_PDCK_LP: 1;
+        uint32_t XTAL_LDO_SW_LP: 3;
+        uint32_t BT_ANAPAR_XTAL11_DUMMY: 5;
+        uint32_t XTAL_PDC_MANUAL: 1;
+        uint32_t XTAL_PKDET_CMP_SWAP: 1;
+        uint32_t XTAL_PKDET_LOAD_SWAP: 1;
+        uint32_t AON2PON_XTAL_SEL_TOK01: 3;
+    };
+} AON_BT_ANAPAR_XTAL10_TYPE;
+
+/* 0xCBC    0x4000_0cbc
+    3:0     R/W XTAL_LPSCLK_CNTRL                       4'b0000
+    4       R   AON2PON_XTAL_EN_XTAL_SEL_TOK01          1'b0
+    5       R   AON2PON_XTAL_EN_XO_CLK_SW               1'b0
+    6       R/W XTAL_FASTSET_MANU                       1'b0
+    8:7     R/W XTAL_OV_RATIO                           2'b01
+    11:9    R/W XTAL_OV_UNIT                            3'b010
+    12      R/W XTAL_LPS_CAP_CTRL                       1'b1
+    14:13   R/W XTAL_LPS_CAP_CYC                        2'b00
+    15      R/W XTAL_MD_LPOW                            1'b0
+    21:16   R/W XTAL_WAIT_CYC                           6'b000010
+    23:22   R/W XTAL_LPS_CAP_STEP                       2'b01
+    24      R/W XTAL_BYPASS_CTRL                        1'b0
+    27:25   R/W XTAL_RDY_SEL_TOK                        3'b100
+    31:28   R/W XTAL_CTRL_OUT_SEL                       4'b0000
+ */
+typedef volatile union _AON_BT_ANAPAR_XTAL12_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t XTAL_LPSCLK_CNTRL: 4;
+        uint32_t AON2PON_XTAL_EN_XTAL_SEL_TOK01: 1;
+        uint32_t AON2PON_XTAL_EN_XO_CLK_SW: 1;
+        uint32_t XTAL_FASTSET_MANU: 1;
+        uint32_t XTAL_OV_RATIO: 2;
+        uint32_t XTAL_OV_UNIT: 3;
+        uint32_t XTAL_LPS_CAP_CTRL: 1;
+        uint32_t XTAL_LPS_CAP_CYC: 2;
+        uint32_t XTAL_MD_LPOW: 1;
+        uint32_t XTAL_WAIT_CYC: 6;
+        uint32_t XTAL_LPS_CAP_STEP: 2;
+        uint32_t XTAL_BYPASS_CTRL: 1;
+        uint32_t XTAL_RDY_SEL_TOK: 3;
+        uint32_t XTAL_CTRL_OUT_SEL: 4;
+    };
+} AON_BT_ANAPAR_XTAL12_TYPE;
+
+/* 0xCC0    0x4000_0cc0
+    0       R/W BT_ANAPAR_XTAL14_DUMMY0                 1'b0
+    2:1     R/W XTAL_MODE_DLY                           2'b10
+    15:3    R/W BT_ANAPAR_XTAL14_DUMMY3                 13'h0
+    21:16   R/W XTAL_PDC_LP                             6'b100000
+    31:22   R/W BT_ANAPAR_XTAL15_DUMMY                  10'b0000000000
+ */
+typedef volatile union _AON_BT_ANAPAR_XTAL14_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t BT_ANAPAR_XTAL14_DUMMY0: 1;
+        uint32_t XTAL_MODE_DLY: 2;
+        uint32_t BT_ANAPAR_XTAL14_DUMMY3: 13;
+        uint32_t XTAL_PDC_LP: 6;
+        uint32_t BT_ANAPAR_XTAL15_DUMMY: 10;
+    };
+} AON_BT_ANAPAR_XTAL14_TYPE;
+
+/* 0xCC4    0x4000_0cc4
+    15:0    R/W BT_ANAPAR_XTAL16_DUMMY                  16'b0
+    31:16   R/W BT_ANAPAR_XTAL17_DUMMY                  16'hffff
+ */
+typedef volatile union _AON_BT_ANAPAR_XTAL16_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t BT_ANAPAR_XTAL16_DUMMY: 16;
+        uint32_t BT_ANAPAR_XTAL17_DUMMY: 16;
+    };
+} AON_BT_ANAPAR_XTAL16_TYPE;
+
+/* 0xCC8    0x4000_0cc8
+    2:0     R   RSVD                                    3'b0
+    3       R/W AAC_SEL                                 1'b0
+    9:4     R/W AAC_GM1                                 6'h1f
+    15:10   R   AON2PON_XTAL_GM_AAC                     6'h0f
+    23:16   R/W CLK_REQ_XTAL_SC_XI                      8'b00111111
+    31:24   R/W CLK_REQ_XTAL_SC_XO                      8'b00111111
+ */
+typedef volatile union _AON_REG0X_XTAL_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RSVD: 3;
+        uint32_t AAC_SEL: 1;
+        uint32_t AAC_GM1: 6;
+        uint32_t AON2PON_XTAL_GM_AAC: 6;
+        uint32_t CLK_REQ_XTAL_SC_XI: 8;
+        uint32_t CLK_REQ_XTAL_SC_XO: 8;
+    };
+} AON_REG0X_XTAL_TYPE;
+
+/* 0xCCC    0x4000_0ccc
+    7:0     R   XTAL_IS_FINEO                           8'b11111111
+    8       R   XTAL_CLK_OK                             1'b0
+    9       R   XTAL_CLK_CHANGE_OK                      1'b0
+    10      R   XTAL_NM_MODE_O                          1'b0
+    11      R   XTAL_MODE_READY_O                       1'b0
+    14:12   R   XTAL_MODE_O                             3'b0
+    15      R   XTAL_LPS_MODE_O                         1'b0
+    16      R   XTAL_HP_MODE_O                          1'b0
+    17      R   XTAL_FASTSET_O                          1'b0
+    23:18   R   RSVD                                    6'b0
+    31:24   R   XTAL_CTRL_DEBUG_OUT                     8'b0
+ */
+typedef volatile union _AON_REG1X_XTAL_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t XTAL_IS_FINEO: 8;
+        uint32_t XTAL_CLK_OK: 1;
+        uint32_t XTAL_CLK_CHANGE_OK: 1;
+        uint32_t XTAL_NM_MODE_O: 1;
+        uint32_t XTAL_MODE_READY_O: 1;
+        uint32_t XTAL_MODE_O: 3;
+        uint32_t XTAL_LPS_MODE_O: 1;
+        uint32_t XTAL_HP_MODE_O: 1;
+        uint32_t XTAL_FASTSET_O: 1;
+        uint32_t RSVD: 6;
+        uint32_t XTAL_CTRL_DEBUG_OUT: 8;
+    };
+} AON_REG1X_XTAL_TYPE;
+
+/* 0xCD0    0x4000_0cd0
+    0       R/W ADDA_SW_LDO2PWRCUT                      1'b0
+    1       R/W ADDA_POW_LDO_VREF                       1'b1
+    2       R/W ADDA_POW_LDO_OP                         1'b1
+    3       R/W ADDA_LDO_VPULSE                         1'b0
+    7:4     R/W ADDA_LDO_SW                             4'b0010
+    8       R/W ADDA_DOUBLE_OP_I                        1'b0
+    15:9    R   RSVD                                    7'b0
+    31:16   R   RSVD                                    16'b0
+ */
+typedef volatile union _AON_REG0X_BT_ANAPAR_LDO_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t ADDA_SW_LDO2PWRCUT: 1;
+        uint32_t ADDA_POW_LDO_VREF: 1;
+        uint32_t ADDA_POW_LDO_OP: 1;
+        uint32_t ADDA_LDO_VPULSE: 1;
+        uint32_t ADDA_LDO_SW: 4;
+        uint32_t ADDA_DOUBLE_OP_I: 1;
+        uint32_t RSVD_1: 7;
+        uint32_t RSVD: 16;
+    };
+} AON_REG0X_BT_ANAPAR_LDO_TYPE;
+
+/* 0xCD4    0x4000_0cd4
+    0       R/W SW_LDO2PWRCUT                           1'b0
+    1       R/W POW_LDO                                 1'b0
+    2       R/W EN_SW                                   1'b0
+    5:3     R/W LDO_SW                                  3'b100
+    15:6    R   RSVD                                    10'b0
+    31:16   R   RSVD                                    16'b0
+ */
+typedef volatile union _AON_REG0X_RF_LDO318_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t SW_LDO2PWRCUT: 1;
+        uint32_t POW_LDO: 1;
+        uint32_t EN_SW: 1;
+        uint32_t LDO_SW: 3;
+        uint32_t RSVD_1: 10;
+        uint32_t RSVD: 16;
+    };
+} AON_REG0X_RF_LDO318_TYPE;
+
+/* 0xD00    0x4000_0d00
+    8:0     R/W REG0X_LDO_PLL1_DUMMY                    9'b0
+    9       R/W DOUBLE_OP_I                             1'b0
+    10      R/W PLL_SW_LDO2PWRCUT                       1'b0
+    11      R/W POW_LDO_OP                              1'b0
+    12      R/W PLL_LDO_VPULSE                          1'b0
+    15:13   R/W PLL_LDO_SW                              3'b010
+    31:16   R   RSVD                                    16'b0
+ */
+typedef volatile union _AON_REG0X_LDO_PLL1_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t REG0X_LDO_PLL1_DUMMY: 9;
+        uint32_t DOUBLE_OP_I: 1;
+        uint32_t PLL_SW_LDO2PWRCUT: 1;
+        uint32_t POW_LDO_OP: 1;
+        uint32_t PLL_LDO_VPULSE: 1;
+        uint32_t PLL_LDO_SW: 3;
+        uint32_t RSVD: 16;
+    };
+} AON_REG0X_LDO_PLL1_TYPE;
+
+/* 0xD40    0x4000_0d40
+    23:0    R   RSVD                                    24'h0
+    24      R/W REG0X_USB_DUMMY0                        1'b0
+    25      R/W UA33PC_EN                               1'b0
+    26      R/W UA11PC_EN                               1'b0
+    27      R/W UD11PC_EN                               1'b0
+    28      R/W USB_POW_BG                              1'b0
+    29      R/W USB_POW_BC_L                            1'b0
+    30      R/W ISO_LV                                  1'b1
+    31      R/W ISO_UA2USB                              1'b1
+ */
+typedef volatile union _AON_REG_USB_POWER_CTL_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RSVD: 24;
+        uint32_t REG0X_USB_DUMMY0: 1;
+        uint32_t UA33PC_EN: 1;
+        uint32_t UA11PC_EN: 1;
+        uint32_t UD11PC_EN: 1;
+        uint32_t USB_POW_BG: 1;
+        uint32_t USB_POW_BC_L: 1;
+        uint32_t ISO_LV: 1;
+        uint32_t ISO_UA2USB: 1;
+    };
+} AON_REG_USB_POWER_CTL_TYPE;
+
+/* 0xD44    0x4000_0d44
+    0       R/W r_usb_clk_src_en                        1'h0
+    4:1     R/W r_usb_div_sel                           4'h0
+    5       R/W r_usb_div_en                            1'h0
+    6       R/W r_usb_mux_clk_cg_en                     1'h0
+    7       R/W r_usb_clk_src_sel1                      1'h0
+    8       R/W r_usb_clk_src_sel0                      1'h0
+    20:9    R/W iso_int_out_en                          12'h0
+    26:21   R   RSVD                                    6'h0
+    27      R/W usb_func_en                             1'h0
+    28      R/W usb_ck_en                               1'h0
+    31:29   R   RSVD                                    3'h0
+ */
+typedef volatile union _AON_REG_USB_CLK_CTL_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t r_usb_clk_src_en: 1;
+        uint32_t r_usb_div_sel: 4;
+        uint32_t r_usb_div_en: 1;
+        uint32_t r_usb_mux_clk_cg_en: 1;
+        uint32_t r_usb_clk_src_sel1: 1;
+        uint32_t r_usb_clk_src_sel0: 1;
+        uint32_t iso_int_out_en: 12;
+        uint32_t RSVD_1: 6;
+        uint32_t usb_func_en: 1;
+        uint32_t usb_ck_en: 1;
+        uint32_t RSVD: 3;
+    };
+} AON_REG_USB_CLK_CTL_TYPE;
+
+/* 0xD60    0x4000_0d60
+    0       R/W POW_XTAL                                1'b0
+    3:1     R/W XTAL_MODE                               3'b100
+    4       R/W ISO_XTAL_MODE_CTRL                      1'b1
+    7:5     R/W XTAL_LDO                                3'b011
+    10:8    R/W XTAL_LDO_OK                             3'b011
+    13:11   R/W XTAL_SEL_TOK                            3'b101
+    21:14   R/W XTAL_SC_XI_OK0                          8'b11110000
+    29:22   R/W XTAL_SC_XO_OK0                          8'b11110000
+    31:30   R   RSVD                                    2'b0
+ */
+typedef volatile union _AON_REG_XTAL0_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t POW_XTAL: 1;
+        uint32_t XTAL_MODE: 3;
+        uint32_t ISO_XTAL_MODE_CTRL: 1;
+        uint32_t XTAL_LDO: 3;
+        uint32_t XTAL_LDO_OK: 3;
+        uint32_t XTAL_SEL_TOK: 3;
+        uint32_t XTAL_SC_XI_OK0: 8;
+        uint32_t XTAL_SC_XO_OK0: 8;
+        uint32_t RSVD: 2;
+    };
+} AON_REG_XTAL0_TYPE;
+
+/* 0xD64    0x4000_0d64
+    0       R/W XTAL_BUF_LPS_SEL                        1'b0
+    3:1     R/W XTAL_SEL_TOK01                          3'b100
+    4       R/W XTAL_EN_XTAL_SEL_TOK01                  1'b0
+    5       R/W XTAL_EN_XO_CLK_SW                       1'b0
+    11:6    R/W XTAL_GM_AAC                             6'h0f
+    31:12   R   RSVD                                    20'b0
+ */
+typedef volatile union _AON_REG_XTAL1_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t XTAL_BUF_LPS_SEL: 1;
+        uint32_t XTAL_SEL_TOK01: 3;
+        uint32_t XTAL_EN_XTAL_SEL_TOK01: 1;
+        uint32_t XTAL_EN_XO_CLK_SW: 1;
+        uint32_t XTAL_GM_AAC: 6;
+        uint32_t RSVD: 20;
+    };
+} AON_REG_XTAL1_TYPE;
+
+/* 0xD80    0x4000_0d80
+    9:0     R/W REG0X_PLL1_dummy                        10'b0
+    15:10   R/W DIV<5:0>                                6'b010111
+    31:16   R   RSVD                                    16'b0
+ */
+typedef volatile union _AON_REG0X_PLL1_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t REG0X_PLL1_dummy: 10;
+        uint32_t DIV_5_0: 6;
+        uint32_t RSVD: 16;
+    };
+} AON_REG0X_PLL1_TYPE;
+
+/* 0xD84    0x4000_0d84
+    0       R/W REG2X_PLL1_dummy                        1'b0
+    2:1     R/W debugout_sel<1:0>                       2'b00
+    3       R/W debugout_en                             1'b0
+    5:4     R/W reg_ck_out_peri_sel<1:0>                2'b00
+    6       R/W reg_ck_out_peri_div5                    1'b0
+    8:7     R/W reg_ck_out_mac_sel<1:0>                 2'b00
+    9       R/W reg_ck_out_mac_div5                     1'b0
+    10      R/W reg_CKO_CPU_en                          1'b0
+    11      R/W reg_CKO_PERI_en                         1'b0
+    12      R/W reg_CKO_MAC50M_en                       1'b0
+    13      R/W reg_CKO_MAC_en                          1'b0
+    15:14   R/W VC_THL<1:0>                             2'b00
+    18:16   R/W r3_set<2:0>                             3'b000
+    19      R/W c3_set                                  1'b0
+    22:20   R/W rs_set<2:0>                             3'b100
+    24:23   R/W cs_set<1:0>                             2'b10
+    26:25   R/W cp_set<1:0>                             2'b01
+    27      R/W reg_ck_frefpn_sel                       1'b1
+    28      R/W pow_cpop                                1'b1
+    29      R/W dogenb                                  1'b0
+    30      R/W fref_edge                               1'b0
+    31      R/W pow_pll                                 1'b0
+ */
+typedef volatile union _AON_REG2X_PLL1_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t REG2X_PLL1_dummy: 1;
+        uint32_t debugout_sel_1_0: 2;
+        uint32_t debugout_en: 1;
+        uint32_t reg_ck_out_peri_sel_1_0: 2;
+        uint32_t reg_ck_out_peri_div5: 1;
+        uint32_t reg_ck_out_mac_sel_1_0: 2;
+        uint32_t reg_ck_out_mac_div5: 1;
+        uint32_t reg_CKO_CPU_en: 1;
+        uint32_t reg_CKO_PERI_en: 1;
+        uint32_t reg_CKO_MAC50M_en: 1;
+        uint32_t reg_CKO_MAC_en: 1;
+        uint32_t VC_THL_1_0: 2;
+        uint32_t r3_set_2_0: 3;
+        uint32_t c3_set: 1;
+        uint32_t rs_set_2_0: 3;
+        uint32_t cs_set_1_0: 2;
+        uint32_t cp_set_1_0: 2;
+        uint32_t reg_ck_frefpn_sel: 1;
+        uint32_t pow_cpop: 1;
+        uint32_t dogenb: 1;
+        uint32_t fref_edge: 1;
+        uint32_t pow_pll: 1;
+    };
+} AON_REG2X_PLL1_TYPE;
+
+/* 0xD88    0x4000_0d88
+    2:0     R/W reg_rs_set<2:0>                         3'b100
+    5:3     R/W reg_r3_set<2:0>                         3'b010
+    7:6     R/W reg_cs_set<1:0>                         2'b10
+    9:8     R/W reg_cp_set<1:0>                         2'b10
+    11:10   R/W reg_c3_set<1:0>                         2'b10
+    14:12   R/W reg_cp_bia<2:0>                         3'b000
+    15      R/W ref_lpf_en                              1'b1
+    16      R/W pow_erc                                 1'b0
+    23:17   R/W DIV_SDM<6:0>                            7'b0011100
+    24      R/W CP_DISABLE                              1'b0
+    26:25   R/W reg_xtal_dn_sel<1:0>                    2'b11
+    27      R/W reg_ck_ext_sel                          1'b1
+    28      R/W pow_div                                 1'b0
+    29      R/W reg_dogenb                              1'b0
+    30      R/W ref_fref_edge                           1'b0
+    31      R/W pow_pll2                                1'b0
+ */
+typedef volatile union _AON_REG0X_PLL2_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t reg_rs_set_2_0: 3;
+        uint32_t reg_r3_set_2_0: 3;
+        uint32_t reg_cs_set_1_0: 2;
+        uint32_t reg_cp_set_1_0: 2;
+        uint32_t reg_c3_set_1_0: 2;
+        uint32_t reg_cp_bia_2_0: 3;
+        uint32_t ref_lpf_en: 1;
+        uint32_t pow_erc: 1;
+        uint32_t DIV_SDM_6_0: 7;
+        uint32_t CP_DISABLE: 1;
+        uint32_t reg_xtal_dn_sel_1_0: 2;
+        uint32_t reg_ck_ext_sel: 1;
+        uint32_t pow_div: 1;
+        uint32_t reg_dogenb: 1;
+        uint32_t ref_fref_edge: 1;
+        uint32_t pow_pll2: 1;
+    };
+} AON_REG0X_PLL2_TYPE;
+
+/* 0xD8C    0x4000_0d8c
+    15:0    R/W FOF_SDM_15_0_                           16'b0
+    20:16   R/W FOF_SDM_20_16_                          5'b0
+    23:21   R/W FON_SDM<2:0>                            3'b000
+    24      R/W ORDER_SDM                               1'b0
+    28:25   R/W BB_DBG_SEL_AFE_SDM<3:0>                 4'b0000
+    29      R/W NF_COFE_SYNC_EN                         1'b0
+    30      R/W NF_CODE_LOAD                            1'b0
+    31      R/W REG2X_PLL2_dummy                        1'b0
+ */
+typedef volatile union _AON_REG2X_PLL2_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t FOF_SDM_15_0_: 16;
+        uint32_t FOF_SDM_20_16_: 5;
+        uint32_t FON_SDM_2_0: 3;
+        uint32_t ORDER_SDM: 1;
+        uint32_t BB_DBG_SEL_AFE_SDM_3_0: 4;
+        uint32_t NF_COFE_SYNC_EN: 1;
+        uint32_t NF_CODE_LOAD: 1;
+        uint32_t REG2X_PLL2_dummy: 1;
+    };
+} AON_REG2X_PLL2_TYPE;
+
+/* 0xD90    0x4000_0d90
+    15:0    R   RSVD                                    16'b0
+    28:16   R/W REG4X_PLL2_dummy                        13'b0
+    29      R/W reg_CKO1_sel                            1'b0
+    30      R/W reg_CKO1_d2                             1'b0
+    31      R/W reg_CKO1_en                             1'b0
+ */
+typedef volatile union _AON_REG4X_PLL2_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RSVD: 16;
+        uint32_t REG4X_PLL2_dummy: 13;
+        uint32_t reg_CKO1_sel: 1;
+        uint32_t reg_CKO1_d2: 1;
+        uint32_t reg_CKO1_en: 1;
+    };
+} AON_REG4X_PLL2_TYPE;
+
+/* 0xD94    0x4000_0d94
+    0       R   BT_READY_PLL                            1'b0
+    1       R   BT_READY_PLL2                           1'b0
+    31:2    R/W RSVD                                    30'b0
+ */
+typedef volatile union _AON_RO_PLL_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t BT_READY_PLL: 1;
+        uint32_t BT_READY_PLL2: 1;
+        uint32_t RSVD: 30;
+    };
+} AON_RO_PLL_TYPE;
+
+/* 0x1800   0x4000_1800
+    0       R/W RTC_CNT_START                   1'b0
+    1       R/W RTC_CNT_RST                     1'b0
+    2       R/W RTC_PRE_CNT_RST                 1'b0
+    7:3     R/W RTC_CR0_DUMMY0                  5'b0
+    8       R/W RTC_TICK_IE                     1'b0
+    9       R/W RTC_CNT_OV_IE                   1'b0
+    10      R/W RTC_PRECMP_IE                   1'b0
+    11      R/W RTC_PRECMP_CMP3_IE              1'b0
+    12      R/W RTC_CMP0GT_IE                   1'b0
+    13      R/W RTC_CMP1GT_IE                   1'b0
+    14      R/W RTC_CMP2GT_IE                   1'b0
+    15      R/W RTC_CMP3GT_IE                   1'b0
+    16      R/W RTC_CMP0_NV_IE                  1'b0
+    17      R/W RTC_CMP1_NV_IE                  1'b0
+    18      R/W RTC_CMP2_NV_IE                  1'b0
+    19      R/W RTC_CMP3_NV_IE                  1'b0
+    20      R/W RTC_CMP0_WK_IE                  1'b0
+    21      R/W RTC_CMP1_WK_IE                  1'b0
+    22      R/W RTC_CMP2_WK_IE                  1'b0
+    23      R/W RTC_CMP3_WK_IE                  1'b0
+    28:24   R/W RTC_CR0_DUMMY1                  5'b0
+    29      R/W RTC_WK_IE                       1'b0
+    30      R/W RTC_NV_IE                       1'b0
+    31      R/W RTC_RST                         1'b0
+ */
+typedef volatile union _AON_NS_RTC_CR0_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RTC_CNT_START: 1;
+        uint32_t RTC_CNT_RST: 1;
+        uint32_t RTC_PRE_CNT_RST: 1;
+        uint32_t RTC_CR0_DUMMY0: 5;
+        uint32_t RTC_TICK_IE: 1;
+        uint32_t RTC_CNT_OV_IE: 1;
+        uint32_t RTC_PRECMP_IE: 1;
+        uint32_t RTC_PRECMP_CMP3_IE: 1;
+        uint32_t RTC_CMP0GT_IE: 1;
+        uint32_t RTC_CMP1GT_IE: 1;
+        uint32_t RTC_CMP2GT_IE: 1;
+        uint32_t RTC_CMP3GT_IE: 1;
+        uint32_t RTC_CMP0_NV_IE: 1;
+        uint32_t RTC_CMP1_NV_IE: 1;
+        uint32_t RTC_CMP2_NV_IE: 1;
+        uint32_t RTC_CMP3_NV_IE: 1;
+        uint32_t RTC_CMP0_WK_IE: 1;
+        uint32_t RTC_CMP1_WK_IE: 1;
+        uint32_t RTC_CMP2_WK_IE: 1;
+        uint32_t RTC_CMP3_WK_IE: 1;
+        uint32_t RTC_CR0_DUMMY1: 5;
+        uint32_t RTC_WK_IE: 1;
+        uint32_t RTC_NV_IE: 1;
+        uint32_t RTC_RST: 1;
+    };
+} AON_NS_RTC_CR0_TYPE;
+
+/* 0x1804   0x4000_1804
+    0       R/WACRTC_TICK_CLR                    1'b0
+    1       R/WACRTC_CNT_OV_CLR                  1'b0
+    2       R/WACRTC_PRECMP_CLR                  1'b0
+    3       R/WACRTC_PRECMP_CMP3_CLR             1'b0
+    4       R/WACRTC_CMP0GT_CLR                  1'b0
+    5       R/WACRTC_CMP1GT_CLR                  1'b0
+    6       R/WACRTC_CMP2GT_CLR                  1'b0
+    7       R/WACRTC_CMP3GT_CLR                  1'b0
+    8       R/WACRTC_CMP0_NV_CLR                 1'b0
+    9       R/WACRTC_CMP1_NV_CLR                 1'b0
+    10      R/WACRTC_CMP2_NV_CLR                 1'b0
+    11      R/WACRTC_CMP3_NV_CLR                 1'b0
+    12      R/WACRTC_CMP0_WK_CLR                 1'b0
+    13      R/WACRTC_CMP1_WK_CLR                 1'b0
+    14      R/WACRTC_CMP2_WK_CLR                 1'b0
+    15      R/WACRTC_CMP3_WK_CLR                 1'b0
+    31:16   R/W RTC_INT_clear_DUMMY             16'b0
+ */
+typedef volatile union _AON_NS_RTC_INT_clear_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RTC_TICK_CLR: 1;
+        uint32_t RTC_CNT_OV_CLR: 1;
+        uint32_t RTC_PRECMP_CLR: 1;
+        uint32_t RTC_PRECMP_CMP3_CLR: 1;
+        uint32_t RTC_CMP0GT_CLR: 1;
+        uint32_t RTC_CMP1GT_CLR: 1;
+        uint32_t RTC_CMP2GT_CLR: 1;
+        uint32_t RTC_CMP3GT_CLR: 1;
+        uint32_t RTC_CMP0_NV_CLR: 1;
+        uint32_t RTC_CMP1_NV_CLR: 1;
+        uint32_t RTC_CMP2_NV_CLR: 1;
+        uint32_t RTC_CMP3_NV_CLR: 1;
+        uint32_t RTC_CMP0_WK_CLR: 1;
+        uint32_t RTC_CMP1_WK_CLR: 1;
+        uint32_t RTC_CMP2_WK_CLR: 1;
+        uint32_t RTC_CMP3_WK_CLR: 1;
+        uint32_t RTC_INT_clear_DUMMY: 16;
+    };
+} AON_NS_RTC_INT_clear_TYPE;
+
+/* 0x1808   0x4000_1808
+    0       R/W1CRTC_TICK_SR                     1'b0
+    1       R/W1CRTC_CNT_OV_SR                   1'b0
+    2       R/W1CRTC_PRECMP_SR                   1'b0
+    3       R/W1CRTC_PRECMP_CMP3_SR              1'b0
+    4       R/W1CRTC_CMP0GT_SR                   1'b0
+    5       R/W1CRTC_CMP1GT_SR                   1'b0
+    6       R/W1CRTC_CMP2GT_SR                   1'b0
+    7       R/W1CRTC_CMP3GT_SR                   1'b0
+    8       R/W1CRTC_CMP0_NV_SR                  1'b0
+    9       R/W1CRTC_CMP1_NV_SR                  1'b0
+    10      R/W1CRTC_CMP2_NV_SR                  1'b0
+    11      R/W1CRTC_CMP3_NV_SR                  1'b0
+    12      R/W1CRTC_CMP0_WK_SR                  1'b0
+    13      R/W1CRTC_CMP1_WK_SR                  1'b0
+    14      R/W1CRTC_CMP2_WK_SR                  1'b0
+    15      R/W1CRTC_CMP3_WK_SR                  1'b0
+    31:16   R/W RTC_INT_SR_DUMMY                16'b0
+ */
+typedef volatile union _AON_NS_RTC_INT_SR_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RTC_TICK_SR: 1;
+        uint32_t RTC_CNT_OV_SR: 1;
+        uint32_t RTC_PRECMP_SR: 1;
+        uint32_t RTC_PRECMP_CMP3_SR: 1;
+        uint32_t RTC_CMP0GT_SR: 1;
+        uint32_t RTC_CMP1GT_SR: 1;
+        uint32_t RTC_CMP2GT_SR: 1;
+        uint32_t RTC_CMP3GT_SR: 1;
+        uint32_t RTC_CMP0_NV_SR: 1;
+        uint32_t RTC_CMP1_NV_SR: 1;
+        uint32_t RTC_CMP2_NV_SR: 1;
+        uint32_t RTC_CMP3_NV_SR: 1;
+        uint32_t RTC_CMP0_WK_SR: 1;
+        uint32_t RTC_CMP1_WK_SR: 1;
+        uint32_t RTC_CMP2_WK_SR: 1;
+        uint32_t RTC_CMP3_WK_SR: 1;
+        uint32_t RTC_INT_SR_DUMMY: 16;
+    };
+} AON_NS_RTC_INT_SR_TYPE;
+
+/* 0x180C   0x4000_180c
+    11:0    R/W RTC_PRESCALER                   12'b0
+    31:12   R/W RTC_PRESCALER_DUMMY             20'b0
+ */
+typedef volatile union _AON_NS_RTC_PRESCALER0_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RTC_PRESCALER: 12;
+        uint32_t RTC_PRESCALER_DUMMY: 20;
+    };
+} AON_NS_RTC_PRESCALER0_TYPE;
+
+/* 0x1810   0x4000_1810
+    31:0    R/W RTC_CMP0                        32'b0
+ */
+typedef volatile union _AON_NS_RTC_COMP_0_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RTC_CMP0;
+    };
+} AON_NS_RTC_COMP_0_TYPE;
+
+/* 0x1814   0x4000_1814
+    31:0    R/W RTC_CMP1                        32'b0
+ */
+typedef volatile union _AON_NS_RTC_COMP_1_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RTC_CMP1;
+    };
+} AON_NS_RTC_COMP_1_TYPE;
+
+/* 0x1818   0x4000_1818
+    31:0    R/W RTC_CMP2                        32'b0
+ */
+typedef volatile union _AON_NS_RTC_COMP_2_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RTC_CMP2;
+    };
+} AON_NS_RTC_COMP_2_TYPE;
+
+/* 0x181C   0x4000_181c
+    31:0    R/W RTC_CMP3                        32'b0
+ */
+typedef volatile union _AON_NS_RTC_COMP_3_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RTC_CMP3;
+    };
+} AON_NS_RTC_COMP_3_TYPE;
+
+/* 0x1820   0x4000_1820
+    31:0    R/W RTC_CMP0GT                      32'b0
+ */
+typedef volatile union _AON_NS_RTC_COMP0_GT_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RTC_CMP0GT;
+    };
+} AON_NS_RTC_COMP0_GT_TYPE;
+
+/* 0x1824   0x4000_1824
+    31:0    R/W RTC_CMP1GT                      32'b0
+ */
+typedef volatile union _AON_NS_RTC_COMP1_GT_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RTC_CMP1GT;
+    };
+} AON_NS_RTC_COMP1_GT_TYPE;
+
+/* 0x1828   0x4000_1828
+    31:0    R/W RTC_CMP2GT                      32'b0
+ */
+typedef volatile union _AON_NS_RTC_COMP2_GT_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RTC_CMP2GT;
+    };
+} AON_NS_RTC_COMP2_GT_TYPE;
+
+/* 0x182C   0x4000_182c
+    31:0    R/W RTC_CMP3GT                      32'b0
+ */
+typedef volatile union _AON_NS_RTC_COMP3_GT_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RTC_CMP3GT;
+    };
+} AON_NS_RTC_COMP3_GT_TYPE;
+
+/* 0x1830   0x4000_1830
+    31:0    R   RTC_CNT                         32'b0
+ */
+typedef volatile union _AON_NS_RTC_CNT0_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RTC_CNT;
+    };
+} AON_NS_RTC_CNT0_TYPE;
+
+/* 0x1834   0x4000_1834
+    11:0    R   RTC_PRESCALE_CNT                12'b0
+    31:12   R/W RTC_PRESCALE_CNT_DUMMY          20'b0
+ */
+typedef volatile union _AON_NS_RTC_PRESCALE_CNT0_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RTC_PRESCALE_CNT: 12;
+        uint32_t RTC_PRESCALE_CNT_DUMMY: 20;
+    };
+} AON_NS_RTC_PRESCALE_CNT0_TYPE;
+
+/* 0x1838   0x4000_1838
+    11:0    R/W RTC_PRESCALE_CMP                12'b0
+    31:12   R/W RTC_PRESCALE_CMP_DUMMY          20'b0
+ */
+typedef volatile union _AON_NS_RTC_PRESCALE_CMP0_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RTC_PRESCALE_CMP: 12;
+        uint32_t RTC_PRESCALE_CMP_DUMMY: 20;
+    };
+} AON_NS_RTC_PRESCALE_CMP0_TYPE;
+
+/* 0x183C   0x4000_183c
+    31:0    R/W RTC_BACKUP                      32'b0
+ */
+typedef volatile union _AON_NS_RTC_BACKUP_REG_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RTC_BACKUP;
+    };
+} AON_NS_RTC_BACKUP_REG_TYPE;
+
+/* 0x1840   0x4000_1840
+    31:0    R   RTC_RTL_VERSION                 32'h2112180A
+ */
+typedef volatile union _AON_NS_RTC_RTL_VERSION0_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RTC_RTL_VERSION;
+    };
+} AON_NS_RTC_RTL_VERSION0_TYPE;
+
+/* 0x1850   0x4000_1850
+    7:0     R/W reg_lpcomp0_deb_cnt             8'b0
+    10:8    R/W reg_lpcomp0_deb_div             3'b0
+    11      R/W reg_lpcomp0_deb_en              1'b0
+    12      R/W RSVD                            1'b0
+    13      R/W reg_lpcomp0_single_output_en    1'b0
+    14      R/W RSVD                            1'b0
+    15      R/W RSVD                            1'b0
+    16      R/W reg_lpcomp0_ie                  1'b0
+    17      R/W reg_lpcomp0_src_int_en          1'b0
+    18      R/W reg_lpcomp0_src_aon_int_en      1'b0
+    19      R/W reg_lpcomp0_deb_sel             1'b0
+    30:20   R/W LPC0_CR0_Dummy                  11'b0
+    31      R/W LPC0_CR1_Dummy                  1'b0
+ */
+typedef volatile union _AON_NS_LPC0_CR0_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t reg_lpcomp0_deb_cnt: 8;
+        uint32_t reg_lpcomp0_deb_div: 3;
+        uint32_t reg_lpcomp0_deb_en: 1;
+        uint32_t RSVD_2: 1;
+        uint32_t reg_lpcomp0_single_output_en: 1;
+        uint32_t RSVD_1: 1;
+        uint32_t RSVD: 1;
+        uint32_t reg_lpcomp0_ie: 1;
+        uint32_t reg_lpcomp0_src_int_en: 1;
+        uint32_t reg_lpcomp0_src_aon_int_en: 1;
+        uint32_t reg_lpcomp0_deb_sel: 1;
+        uint32_t LPC0_CR0_Dummy: 11;
+        uint32_t LPC0_CR1_Dummy: 1;
+    };
+} AON_NS_LPC0_CR0_TYPE;
+
+/* 0x1854   0x4000_1854
+    0       R   reg_lpcomp0_flag                1'b0
+    1       R   reg_lpcomp0_out_aon_flag        1'b0
+    31:2    R/W LPC0_SR_Dummy                   30'b0
+ */
+typedef volatile union _AON_NS_LPC0_SR_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t reg_lpcomp0_flag: 1;
+        uint32_t reg_lpcomp0_out_aon_flag: 1;
+        uint32_t LPC0_SR_Dummy: 30;
+    };
+} AON_NS_LPC0_SR_TYPE;
+
+/* 0x1858   0x4000_1858
+    5:0     R/W MBIAS_REG0X_SD_TUNE             6'b0
+    31:6    R   RSVD                            26'b0
+ */
+typedef volatile union _AON_NS_LPC0_MBIAS_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t MBIAS_REG0X_SD_TUNE: 6;
+        uint32_t RSVD: 26;
+    };
+} AON_NS_LPC0_MBIAS_TYPE;
+
+/* 0x1900   0x4000_1900
+    0       R/W PAD_P0_O[0]                     1'b0
+    1       R/W PAD_P0_E[0]                     1'b0
+    2       R/W PAD_P0_PU_EN[0]                 1'b1
+    3       R/W AON_PAD_P0_PD[0]                1'b1
+    4       R/W PAD_P0_PUPDC[0]                 1'b0
+    5       R/W PAD_P0_WKEN[0]                  1'b0
+    6       R/W PAD_P0_WKPOL[0]                 1'b0
+    7       R/W PAD_P0_E2[0]                    1'b1
+    8       R/W PAD_P0_SHDN[0]                  1'b1
+    9       R/W PAD_P0_S[0]                     1'b0
+    10      R/W PAD_P0_DEB[0]                   1'b0
+    11      R/W PAD_P0_HS_MUX[0]                1'b0
+    14:12   R   RSVD                            3'h0
+    15      R/W PAD_P0_O_EN[0]                  1'h1
+    16      R/W PAD_P0_O[1]                     1'b0
+    17      R/W PAD_P0_E[1]                     1'b0
+    18      R/W PAD_P0_PU_EN[1]                 1'b1
+    19      R/W AON_PAD_P0_PD[1]                1'b1
+    20      R/W PAD_P0_PUPDC[1]                 1'b0
+    21      R/W PAD_P0_WKEN[1]                  1'b0
+    22      R/W PAD_P0_WKPOL[1]                 1'b0
+    23      R/W PAD_P0_E2[1]                    1'b1
+    24      R/W PAD_P0_SHDN[1]                  1'b1
+    25      R/W PAD_P0_S[1]                     1'b0
+    26      R/W PAD_P0_DEB[1]                   1'b0
+    27      R/W PAD_P0_HS_MUX[1]                1'b0
+    28      R   RSVD                            1'b0
+    29      R/W PAD_P0_1_CLK_OUT                1'b0
+    30      R   RSVD                            1'h0
+    31      R/W PAD_P0_O_EN[1]                  1'h1
+ */
+typedef volatile union _AON_NS_P0_0_P0_1_PAD_CFG_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t PAD_P0_O_0: 1;
+        uint32_t PAD_P0_E_0: 1;
+        uint32_t PAD_P0_PU_EN_0: 1;
+        uint32_t AON_PAD_P0_PD_0: 1;
+        uint32_t PAD_P0_PUPDC_0: 1;
+        uint32_t PAD_P0_WKEN_0: 1;
+        uint32_t PAD_P0_WKPOL_0: 1;
+        uint32_t PAD_P0_E2_0: 1;
+        uint32_t PAD_P0_SHDN_0: 1;
+        uint32_t PAD_P0_S_0: 1;
+        uint32_t PAD_P0_DEB_0: 1;
+        uint32_t PAD_P0_HS_MUX_0: 1;
+        uint32_t RSVD_2: 3;
+        uint32_t PAD_P0_O_EN_0: 1;
+        uint32_t PAD_P0_O_1: 1;
+        uint32_t PAD_P0_E_1: 1;
+        uint32_t PAD_P0_PU_EN_1: 1;
+        uint32_t AON_PAD_P0_PD_1: 1;
+        uint32_t PAD_P0_PUPDC_1: 1;
+        uint32_t PAD_P0_WKEN_1: 1;
+        uint32_t PAD_P0_WKPOL_1: 1;
+        uint32_t PAD_P0_E2_1: 1;
+        uint32_t PAD_P0_SHDN_1: 1;
+        uint32_t PAD_P0_S_1: 1;
+        uint32_t PAD_P0_DEB_1: 1;
+        uint32_t PAD_P0_HS_MUX_1: 1;
+        uint32_t RSVD_1: 1;
+        uint32_t PAD_P0_1_CLK_OUT: 1;
+        uint32_t RSVD: 1;
+        uint32_t PAD_P0_O_EN_1: 1;
+    };
+} AON_NS_P0_0_P0_1_PAD_CFG_TYPE;
+
+/* 0x1904   0x4000_1904
+    0       R/W PAD_P0_O[2]                     1'b0
+    1       R/W PAD_P0_E[2]                     1'b0
+    2       R/W PAD_P0_PU_EN[2]                 1'b1
+    3       R/W AON_PAD_P0_PD[2]                1'b1
+    4       R/W PAD_P0_PUPDC[2]                 1'b0
+    5       R/W PAD_P0_WKEN[2]                  1'b0
+    6       R/W PAD_P0_WKPOL[2]                 1'b0
+    7       R/W PAD_P0_E2[2]                    1'b1
+    8       R/W PAD_P0_SHDN[2]                  1'b1
+    9       R/W PAD_P0_S[2]                     1'b0
+    10      R/W PAD_P0_DEB[2]                   1'b0
+    11      R/W PAD_P0_HS_MUX[2]                1'b0
+    14:12   R   RSVD                            3'h0
+    15      R/W PAD_P0_O_EN[2]                  1'h1
+    16      R/W PAD_P0_O[3]                     1'b0
+    17      R/W PAD_P0_E[3]                     1'b0
+    18      R/W PAD_P0_PU_EN[3]                 1'b1
+    19      R/W AON_PAD_P0_PD[3]                1'b0
+    20      R/W PAD_P0_PUPDC[3]                 1'b0
+    21      R/W PAD_P0_WKEN[3]                  1'b0
+    22      R/W PAD_P0_WKPOL[3]                 1'b0
+    23      R/W PAD_P0_E2[3]                    1'b1
+    24      R/W PAD_P0_SHDN[3]                  1'b1
+    25      R/W PAD_P0_S[3]                     1'b0
+    26      R/W PAD_P0_DEB[3]                   1'b0
+    27      R/W PAD_P0_HS_MUX[3]                1'b0
+    28      R   PAD_P0_3_I                      1'b0
+    29      R/W PAD_P0_3_CLK_OUT                1'b0
+    30      R   RSVD                            1'h0
+    31      R/W PAD_P0_O_EN[3]                  1'h1
+ */
+typedef volatile union _AON_NS_P0_2_P0_3_PAD_CFG_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t PAD_P0_O_2: 1;
+        uint32_t PAD_P0_E_2: 1;
+        uint32_t PAD_P0_PU_EN_2: 1;
+        uint32_t AON_PAD_P0_PD_2: 1;
+        uint32_t PAD_P0_PUPDC_2: 1;
+        uint32_t PAD_P0_WKEN_2: 1;
+        uint32_t PAD_P0_WKPOL_2: 1;
+        uint32_t PAD_P0_E2_2: 1;
+        uint32_t PAD_P0_SHDN_2: 1;
+        uint32_t PAD_P0_S_2: 1;
+        uint32_t PAD_P0_DEB_2: 1;
+        uint32_t PAD_P0_HS_MUX_2: 1;
+        uint32_t RSVD_1: 3;
+        uint32_t PAD_P0_O_EN_2: 1;
+        uint32_t PAD_P0_O_3: 1;
+        uint32_t PAD_P0_E_3: 1;
+        uint32_t PAD_P0_PU_EN_3: 1;
+        uint32_t AON_PAD_P0_PD_3: 1;
+        uint32_t PAD_P0_PUPDC_3: 1;
+        uint32_t PAD_P0_WKEN_3: 1;
+        uint32_t PAD_P0_WKPOL_3: 1;
+        uint32_t PAD_P0_E2_3: 1;
+        uint32_t PAD_P0_SHDN_3: 1;
+        uint32_t PAD_P0_S_3: 1;
+        uint32_t PAD_P0_DEB_3: 1;
+        uint32_t PAD_P0_HS_MUX_3: 1;
+        uint32_t PAD_P0_3_I: 1;
+        uint32_t PAD_P0_3_CLK_OUT: 1;
+        uint32_t RSVD: 1;
+        uint32_t PAD_P0_O_EN_3: 1;
+    };
+} AON_NS_P0_2_P0_3_PAD_CFG_TYPE;
+
+/* 0x1908   0x4000_1908
+    0       R/W PAD_P0_O[4]                     1'b0
+    1       R/W PAD_P0_E[4]                     1'b0
+    2       R/W PAD_P0_PU_EN[4]                 1'b1
+    3       R/W AON_PAD_P0_PD[4]                1'b1
+    4       R/W PAD_P0_PUPDC[4]                 1'b0
+    5       R/W PAD_P0_WKEN[4]                  1'b0
+    6       R/W PAD_P0_WKPOL[4]                 1'b0
+    7       R/W PAD_P0_E2[4]                    1'b1
+    8       R/W PAD_P0_SHDN[4]                  1'b1
+    9       R/W PAD_P0_S[4]                     1'b0
+    10      R/W PAD_P0_DEB[4]                   1'b0
+    11      R/W PAD_P0_HS_MUX[4]                1'b0
+    12      R   RSVD                            1'b0
+    13      R/W PAD_P0_4_dbg_en                 1'b0
+    14      R   RSVD                            1'h0
+    15      R/W PAD_P0_O_EN[4]                  1'h1
+    16      R/W PAD_P0_O[5]                     1'b0
+    17      R/W PAD_P0_E[5]                     1'b0
+    18      R/W PAD_P0_PU_EN[5]                 1'b1
+    19      R/W AON_PAD_P0_PD[5]                1'b1
+    20      R/W PAD_P0_PUPDC[5]                 1'b0
+    21      R/W PAD_P0_WKEN[5]                  1'b0
+    22      R/W PAD_P0_WKPOL[5]                 1'b0
+    23      R/W PAD_P0_E2[5]                    1'b1
+    24      R/W PAD_P0_SHDN[5]                  1'b1
+    25      R/W PAD_P0_S[5]                     1'b0
+    26      R/W PAD_P0_DEB[5]                   1'b0
+    27      R/W PAD_P0_HS_MUX[5]                1'b0
+    30:28   R   RSVD                            3'b0
+    31      R/W PAD_P0_O_EN[5]                  1'h1
+ */
+typedef volatile union _AON_NS_P0_4_P0_5_PAD_CFG_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t PAD_P0_O_4: 1;
+        uint32_t PAD_P0_E_4: 1;
+        uint32_t PAD_P0_PU_EN_4: 1;
+        uint32_t AON_PAD_P0_PD_4: 1;
+        uint32_t PAD_P0_PUPDC_4: 1;
+        uint32_t PAD_P0_WKEN_4: 1;
+        uint32_t PAD_P0_WKPOL_4: 1;
+        uint32_t PAD_P0_E2_4: 1;
+        uint32_t PAD_P0_SHDN_4: 1;
+        uint32_t PAD_P0_S_4: 1;
+        uint32_t PAD_P0_DEB_4: 1;
+        uint32_t PAD_P0_HS_MUX_4: 1;
+        uint32_t RSVD_2: 1;
+        uint32_t PAD_P0_4_dbg_en: 1;
+        uint32_t RSVD_1: 1;
+        uint32_t PAD_P0_O_EN_4: 1;
+        uint32_t PAD_P0_O_5: 1;
+        uint32_t PAD_P0_E_5: 1;
+        uint32_t PAD_P0_PU_EN_5: 1;
+        uint32_t AON_PAD_P0_PD_5: 1;
+        uint32_t PAD_P0_PUPDC_5: 1;
+        uint32_t PAD_P0_WKEN_5: 1;
+        uint32_t PAD_P0_WKPOL_5: 1;
+        uint32_t PAD_P0_E2_5: 1;
+        uint32_t PAD_P0_SHDN_5: 1;
+        uint32_t PAD_P0_S_5: 1;
+        uint32_t PAD_P0_DEB_5: 1;
+        uint32_t PAD_P0_HS_MUX_5: 1;
+        uint32_t RSVD: 3;
+        uint32_t PAD_P0_O_EN_5: 1;
+    };
+} AON_NS_P0_4_P0_5_PAD_CFG_TYPE;
+
+/* 0x190C   0x4000_190c
+    0       R/W PAD_P0_O[6]                     1'b0
+    1       R/W PAD_P0_E[6]                     1'b0
+    2       R/W PAD_P0_PU_EN[6]                 1'b1
+    3       R/W AON_PAD_P0_PD[6]                1'b1
+    4       R/W PAD_P0_PUPDC[6]                 1'b0
+    5       R/W PAD_P0_WKEN[6]                  1'b0
+    6       R/W PAD_P0_WKPOL[6]                 1'b0
+    7       R/W PAD_P0_E2[6]                    1'b1
+    8       R/W PAD_P0_SHDN[6]                  1'b1
+    9       R/W PAD_P0_S[6]                     1'b0
+    10      R/W PAD_P0_DEB[6]                   1'b0
+    11      R/W PAD_P0_HS_MUX[6]                1'b0
+    14:12   R   RSVD                            3'b0
+    15      R/W PAD_P0_O_EN[6]                  1'h1
+    16      R/W PAD_P0_O[7]                     1'b0
+    17      R/W PAD_P0_E[7]                     1'b0
+    18      R/W PAD_P0_PU_EN[7]                 1'b1
+    19      R/W AON_PAD_P0_PD[7]                1'b1
+    20      R/W PAD_P0_PUPDC[7]                 1'b0
+    21      R/W PAD_P0_WKEN[7]                  1'b0
+    22      R/W PAD_P0_WKPOL[7]                 1'b0
+    23      R/W PAD_P0_E2[7]                    1'b1
+    24      R/W PAD_P0_SHDN[7]                  1'b1
+    25      R/W PAD_P0_S[7]                     1'b0
+    26      R/W PAD_P0_DEB[7]                   1'b0
+    27      R/W PAD_P0_HS_MUX[7]                1'b0
+    30:28   R   RSVD                            3'b0
+    31      R/W PAD_P0_O_EN[7]                  1'h1
+ */
+typedef volatile union _AON_NS_P0_6_P0_7_PAD_CFG_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t PAD_P0_O_6: 1;
+        uint32_t PAD_P0_E_6: 1;
+        uint32_t PAD_P0_PU_EN_6: 1;
+        uint32_t AON_PAD_P0_PD_6: 1;
+        uint32_t PAD_P0_PUPDC_6: 1;
+        uint32_t PAD_P0_WKEN_6: 1;
+        uint32_t PAD_P0_WKPOL_6: 1;
+        uint32_t PAD_P0_E2_6: 1;
+        uint32_t PAD_P0_SHDN_6: 1;
+        uint32_t PAD_P0_S_6: 1;
+        uint32_t PAD_P0_DEB_6: 1;
+        uint32_t PAD_P0_HS_MUX_6: 1;
+        uint32_t RSVD_1: 3;
+        uint32_t PAD_P0_O_EN_6: 1;
+        uint32_t PAD_P0_O_7: 1;
+        uint32_t PAD_P0_E_7: 1;
+        uint32_t PAD_P0_PU_EN_7: 1;
+        uint32_t AON_PAD_P0_PD_7: 1;
+        uint32_t PAD_P0_PUPDC_7: 1;
+        uint32_t PAD_P0_WKEN_7: 1;
+        uint32_t PAD_P0_WKPOL_7: 1;
+        uint32_t PAD_P0_E2_7: 1;
+        uint32_t PAD_P0_SHDN_7: 1;
+        uint32_t PAD_P0_S_7: 1;
+        uint32_t PAD_P0_DEB_7: 1;
+        uint32_t PAD_P0_HS_MUX_7: 1;
+        uint32_t RSVD: 3;
+        uint32_t PAD_P0_O_EN_7: 1;
+    };
+} AON_NS_P0_6_P0_7_PAD_CFG_TYPE;
+
+/* 0x1910   0x4000_1910
+    0       R/W PAD_P1_O[0]                     1'b0
+    1       R/W PAD_P1_E[0]                     1'b0
+    2       R/W PAD_P1_PU_EN[0]                 1'b1
+    3       R/W AON_PAD_P1_PD[0]                1'b0
+    4       R/W PAD_P1_PUPDC[0]                 1'b0
+    5       R/W PAD_P1_WKEN[0]                  1'b0
+    6       R/W PAD_P1_WKPOL[0]                 1'b0
+    7       R/W PAD_P1_E2[0]                    1'b1
+    8       R/W PAD_P1_SHDN[0]                  1'b1
+    9       R/W PAD_P1_S[0]                     1'b1
+    10      R/W PAD_P1_DEB[0]                   1'b0
+    14:11   R   RSVD                            4'h0
+    15      R/W PAD_P1_O_EN[0]                  1'h1
+    16      R/W PAD_P1_O[1]                     1'b0
+    17      R/W PAD_P1_E[1]                     1'b0
+    18      R/W PAD_P1_PU_EN[1]                 1'b1
+    19      R/W AON_PAD_P1_PD[1]                1'b0
+    20      R/W PAD_P1_PUPDC[1]                 1'b0
+    21      R/W PAD_P1_WKEN[1]                  1'b0
+    22      R/W PAD_P1_WKPOL[1]                 1'b0
+    23      R/W PAD_P1_E2[1]                    1'b1
+    24      R/W PAD_P1_SHDN[1]                  1'b1
+    25      R/W PAD_P1_S[1]                     1'b1
+    26      R/W PAD_P1_DEB[1]                   1'b0
+    30:27   R   RSVD                            4'h0
+    31      R/W PAD_P1_O_EN[1]                  1'h1
+ */
+typedef volatile union _AON_NS_P1_0_P1_1_PAD_CFG_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t PAD_P1_O_0: 1;
+        uint32_t PAD_P1_E_0: 1;
+        uint32_t PAD_P1_PU_EN_0: 1;
+        uint32_t AON_PAD_P1_PD_0: 1;
+        uint32_t PAD_P1_PUPDC_0: 1;
+        uint32_t PAD_P1_WKEN_0: 1;
+        uint32_t PAD_P1_WKPOL_0: 1;
+        uint32_t PAD_P1_E2_0: 1;
+        uint32_t PAD_P1_SHDN_0: 1;
+        uint32_t PAD_P1_S_0: 1;
+        uint32_t PAD_P1_DEB_0: 1;
+        uint32_t RSVD_1: 4;
+        uint32_t PAD_P1_O_EN_0: 1;
+        uint32_t PAD_P1_O_1: 1;
+        uint32_t PAD_P1_E_1: 1;
+        uint32_t PAD_P1_PU_EN_1: 1;
+        uint32_t AON_PAD_P1_PD_1: 1;
+        uint32_t PAD_P1_PUPDC_1: 1;
+        uint32_t PAD_P1_WKEN_1: 1;
+        uint32_t PAD_P1_WKPOL_1: 1;
+        uint32_t PAD_P1_E2_1: 1;
+        uint32_t PAD_P1_SHDN_1: 1;
+        uint32_t PAD_P1_S_1: 1;
+        uint32_t PAD_P1_DEB_1: 1;
+        uint32_t RSVD: 4;
+        uint32_t PAD_P1_O_EN_1: 1;
+    };
+} AON_NS_P1_0_P1_1_PAD_CFG_TYPE;
+
+/* 0x1914   0x4000_1914
+    0       R/W PAD_P1_O[2]                     1'b0
+    1       R/W PAD_P1_E[2]                     1'b0
+    2       R/W PAD_P1_PU_EN[2]                 1'b1
+    3       R/W AON_PAD_P1_PD[2]                1'b1
+    4       R/W PAD_P1_PUPDC[2]                 1'b0
+    5       R/W PAD_P1_WKEN[2]                  1'b0
+    6       R/W PAD_P1_WKPOL[2]                 1'b0
+    7       R/W PAD_P1_E2[2]                    1'b1
+    8       R/W PAD_P1_SHDN[2]                  1'b1
+    9       R/W PAD_P1_S[2]                     1'b0
+    10      R/W PAD_P1_DEB[2]                   1'b0
+    11      R/W PAD_P1_HS_MUX[2]                1'b0
+    14:12   R   RSVD                            3'h0
+    15      R/W PAD_P1_O_EN[2]                  1'h1
+    16      R/W PAD_P1_O[3]                     1'b0
+    17      R/W PAD_P1_E[3]                     1'b0
+    18      R/W PAD_P1_PU_EN[3]                 1'b1
+    19      R/W AON_PAD_P1_PD[3]                1'b1
+    20      R/W PAD_P1_PUPDC[3]                 1'b0
+    21      R/W PAD_P1_WKEN[3]                  1'b0
+    22      R/W PAD_P1_WKPOL[3]                 1'b0
+    23      R/W PAD_P1_E2[3]                    1'b1
+    24      R/W PAD_P1_SHDN[3]                  1'b1
+    25      R/W PAD_P1_S[3]                     1'b0
+    26      R/W PAD_P1_DEB[3]                   1'b0
+    27      R/W PAD_P1_HS_MUX[3]                1'b0
+    30:28   R   RSVD                            3'h0
+    31      R/W PAD_P1_O_EN[3]                  1'h1
+ */
+typedef volatile union _AON_NS_P1_2_P1_3_PAD_CFG_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t PAD_P1_O_2: 1;
+        uint32_t PAD_P1_E_2: 1;
+        uint32_t PAD_P1_PU_EN_2: 1;
+        uint32_t AON_PAD_P1_PD_2: 1;
+        uint32_t PAD_P1_PUPDC_2: 1;
+        uint32_t PAD_P1_WKEN_2: 1;
+        uint32_t PAD_P1_WKPOL_2: 1;
+        uint32_t PAD_P1_E2_2: 1;
+        uint32_t PAD_P1_SHDN_2: 1;
+        uint32_t PAD_P1_S_2: 1;
+        uint32_t PAD_P1_DEB_2: 1;
+        uint32_t PAD_P1_HS_MUX_2: 1;
+        uint32_t RSVD_1: 3;
+        uint32_t PAD_P1_O_EN_2: 1;
+        uint32_t PAD_P1_O_3: 1;
+        uint32_t PAD_P1_E_3: 1;
+        uint32_t PAD_P1_PU_EN_3: 1;
+        uint32_t AON_PAD_P1_PD_3: 1;
+        uint32_t PAD_P1_PUPDC_3: 1;
+        uint32_t PAD_P1_WKEN_3: 1;
+        uint32_t PAD_P1_WKPOL_3: 1;
+        uint32_t PAD_P1_E2_3: 1;
+        uint32_t PAD_P1_SHDN_3: 1;
+        uint32_t PAD_P1_S_3: 1;
+        uint32_t PAD_P1_DEB_3: 1;
+        uint32_t PAD_P1_HS_MUX_3: 1;
+        uint32_t RSVD: 3;
+        uint32_t PAD_P1_O_EN_3: 1;
+    };
+} AON_NS_P1_2_P1_3_PAD_CFG_TYPE;
+
+/* 0x1918   0x4000_1918
+    0       R/W PAD_P1_O[4]                     1'b0
+    1       R/W PAD_P1_E[4]                     1'b0
+    2       R/W PAD_P1_PU_EN[4]                 1'b1
+    3       R/W AON_PAD_P1_PD[4]                1'b1
+    4       R/W PAD_P1_PUPDC[4]                 1'b0
+    5       R/W PAD_P1_WKEN[4]                  1'b0
+    6       R/W PAD_P1_WKPOL[4]                 1'b0
+    7       R/W PAD_P1_E2[4]                    1'b1
+    8       R/W PAD_P1_SHDN[4]                  1'b1
+    9       R/W PAD_P1_S[4]                     1'b0
+    10      R/W PAD_P1_DEB[4]                   1'b0
+    11      R/W PAD_P1_HS_MUX[4]                1'b0
+    14:12   R   RSVD                            3'h0
+    15      R/W PAD_P1_O_EN[4]                  1'h1
+    16      R/W PAD_P1_O[5]                     1'b0
+    17      R/W PAD_P1_E[5]                     1'b0
+    18      R/W PAD_P1_PU_EN[5]                 1'b1
+    19      R/W AON_PAD_P1_PD[5]                1'b0
+    20      R/W PAD_P1_PUPDC[5]                 1'b0
+    21      R/W PAD_P1_WKEN[5]                  1'b0
+    22      R/W PAD_P1_WKPOL[5]                 1'b0
+    23      R/W PAD_P1_E2[5]                    1'b1
+    24      R/W PAD_P1_SHDN[5]                  1'b1
+    25      R/W PAD_P1_S[5]                     1'b0
+    26      R/W PAD_P1_DEB[5]                   1'b0
+    27      R/W PAD_P1_HS_MUX[5]                1'b0
+    30:28   R   RSVD                            3'b0
+    31      R/W PAD_P1_O_EN[5]                  1'h1
+ */
+typedef volatile union _AON_NS_P1_4_P1_5_PAD_CFG_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t PAD_P1_O_4: 1;
+        uint32_t PAD_P1_E_4: 1;
+        uint32_t PAD_P1_PU_EN_4: 1;
+        uint32_t AON_PAD_P1_PD_4: 1;
+        uint32_t PAD_P1_PUPDC_4: 1;
+        uint32_t PAD_P1_WKEN_4: 1;
+        uint32_t PAD_P1_WKPOL_4: 1;
+        uint32_t PAD_P1_E2_4: 1;
+        uint32_t PAD_P1_SHDN_4: 1;
+        uint32_t PAD_P1_S_4: 1;
+        uint32_t PAD_P1_DEB_4: 1;
+        uint32_t PAD_P1_HS_MUX_4: 1;
+        uint32_t RSVD_1: 3;
+        uint32_t PAD_P1_O_EN_4: 1;
+        uint32_t PAD_P1_O_5: 1;
+        uint32_t PAD_P1_E_5: 1;
+        uint32_t PAD_P1_PU_EN_5: 1;
+        uint32_t AON_PAD_P1_PD_5: 1;
+        uint32_t PAD_P1_PUPDC_5: 1;
+        uint32_t PAD_P1_WKEN_5: 1;
+        uint32_t PAD_P1_WKPOL_5: 1;
+        uint32_t PAD_P1_E2_5: 1;
+        uint32_t PAD_P1_SHDN_5: 1;
+        uint32_t PAD_P1_S_5: 1;
+        uint32_t PAD_P1_DEB_5: 1;
+        uint32_t PAD_P1_HS_MUX_5: 1;
+        uint32_t RSVD: 3;
+        uint32_t PAD_P1_O_EN_5: 1;
+    };
+} AON_NS_P1_4_P1_5_PAD_CFG_TYPE;
+
+/* 0x191C   0x4000_191c
+    0       R/W PAD_P1_O[6]                     1'b0
+    1       R/W PAD_P1_E[6]                     1'b0
+    2       R/W PAD_P1_PU_EN[6]                 1'b1
+    3       R/W AON_PAD_P1_PD[6]                1'b1
+    4       R/W PAD_P1_PUPDC[6]                 1'b0
+    5       R/W PAD_P1_WKEN[6]                  1'b0
+    6       R/W PAD_P1_WKPOL[6]                 1'b0
+    7       R/W PAD_P1_E2[6]                    1'b1
+    8       R/W PAD_P1_SHDN[6]                  1'b1
+    9       R/W PAD_P1_S[6]                     1'b0
+    10      R/W PAD_P1_DEB[6]                   1'b0
+    11      R/W PAD_P1_HS_MUX[6]                1'b0
+    14:12   R   RSVD                            3'b0
+    15      R/W PAD_P1_O_EN[6]                  1'h1
+    16      R/W PAD_P1_O[7]                     1'b0
+    17      R/W PAD_P1_E[7]                     1'b0
+    18      R/W PAD_P1_PU_EN[7]                 1'b1
+    19      R/W AON_PAD_P1_PD[7]                1'b1
+    20      R/W PAD_P1_PUPDC[7]                 1'b0
+    21      R/W PAD_P1_WKEN[7]                  1'b0
+    22      R/W PAD_P1_WKPOL[7]                 1'b0
+    23      R/W PAD_P1_E2[7]                    1'b1
+    24      R/W PAD_P1_SHDN[7]                  1'b1
+    25      R/W PAD_P1_S[7]                     1'b0
+    26      R/W PAD_P1_DEB[7]                   1'b0
+    27      R/W PAD_P1_HS_MUX[7]                1'b0
+    30:28   R   RSVD                            3'b0
+    31      R/W PAD_P1_O_EN[7]                  1'h1
+ */
+typedef volatile union _AON_NS_P1_6_P1_7_PAD_CFG_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t PAD_P1_O_6: 1;
+        uint32_t PAD_P1_E_6: 1;
+        uint32_t PAD_P1_PU_EN_6: 1;
+        uint32_t AON_PAD_P1_PD_6: 1;
+        uint32_t PAD_P1_PUPDC_6: 1;
+        uint32_t PAD_P1_WKEN_6: 1;
+        uint32_t PAD_P1_WKPOL_6: 1;
+        uint32_t PAD_P1_E2_6: 1;
+        uint32_t PAD_P1_SHDN_6: 1;
+        uint32_t PAD_P1_S_6: 1;
+        uint32_t PAD_P1_DEB_6: 1;
+        uint32_t PAD_P1_HS_MUX_6: 1;
+        uint32_t RSVD_1: 3;
+        uint32_t PAD_P1_O_EN_6: 1;
+        uint32_t PAD_P1_O_7: 1;
+        uint32_t PAD_P1_E_7: 1;
+        uint32_t PAD_P1_PU_EN_7: 1;
+        uint32_t AON_PAD_P1_PD_7: 1;
+        uint32_t PAD_P1_PUPDC_7: 1;
+        uint32_t PAD_P1_WKEN_7: 1;
+        uint32_t PAD_P1_WKPOL_7: 1;
+        uint32_t PAD_P1_E2_7: 1;
+        uint32_t PAD_P1_SHDN_7: 1;
+        uint32_t PAD_P1_S_7: 1;
+        uint32_t PAD_P1_DEB_7: 1;
+        uint32_t PAD_P1_HS_MUX_7: 1;
+        uint32_t RSVD: 3;
+        uint32_t PAD_P1_O_EN_7: 1;
+    };
+} AON_NS_P1_6_P1_7_PAD_CFG_TYPE;
+
+/* 0x1920   0x4000_1920
+    0       R/W PAD_P2_O[0]                     1'b0
+    1       R/W PAD_P2_E[0]                     1'b0
+    2       R/W PAD_P2_PU_EN[0]                 1'b1
+    3       R/W AON_PAD_P2_PD[0]                1'b1
+    4       R/W PAD_P2_PUPDC[0]                 1'b0
+    5       R/W PAD_P2_WKEN[0]                  1'b0
+    6       R/W PAD_P2_WKPOL[0]                 1'b0
+    7       R/W PAD_P2_E2[0]                    1'b1
+    8       R/W PAD_P2_SHDN[0]                  1'b1
+    9       R/W PAD_P2_S[0]                     1'b0
+    10      R/W PAD_P2_DEB[0]                   1'b0
+    11      R/W PAD_P2_HS_MUX[0]                1'b0
+    14:12   R   RSVD                            3'b0
+    15      R/W PAD_P2_O_EN[0]                  1'h1
+    16      R/W PAD_P2_O[1]                     1'b0
+    17      R/W PAD_P2_E[1]                     1'b0
+    18      R/W PAD_P2_PU_EN[1]                 1'b1
+    19      R/W AON_PAD_P2_PD[1]                1'b1
+    20      R/W PAD_P2_PUPDC[1]                 1'b0
+    21      R/W PAD_P2_WKEN[1]                  1'b0
+    22      R/W PAD_P2_WKPOL[1]                 1'b0
+    23      R/W PAD_P2_E2[1]                    1'b1
+    24      R/W PAD_P2_SHDN[1]                  1'b1
+    25      R/W PAD_P2_S[1]                     1'b0
+    26      R/W PAD_P2_DEB[1]                   1'b0
+    27      R/W PAD_P2_HS_MUX[1]                1'b0
+    30:28   R   RSVD                            3'b0
+    31      R/W PAD_P2_O_EN[1]                  1'h1
+ */
+typedef volatile union _AON_NS_P2_0_P2_1_PAD_CFG_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t PAD_P2_O_0: 1;
+        uint32_t PAD_P2_E_0: 1;
+        uint32_t PAD_P2_PU_EN_0: 1;
+        uint32_t AON_PAD_P2_PD_0: 1;
+        uint32_t PAD_P2_PUPDC_0: 1;
+        uint32_t PAD_P2_WKEN_0: 1;
+        uint32_t PAD_P2_WKPOL_0: 1;
+        uint32_t PAD_P2_E2_0: 1;
+        uint32_t PAD_P2_SHDN_0: 1;
+        uint32_t PAD_P2_S_0: 1;
+        uint32_t PAD_P2_DEB_0: 1;
+        uint32_t PAD_P2_HS_MUX_0: 1;
+        uint32_t RSVD_1: 3;
+        uint32_t PAD_P2_O_EN_0: 1;
+        uint32_t PAD_P2_O_1: 1;
+        uint32_t PAD_P2_E_1: 1;
+        uint32_t PAD_P2_PU_EN_1: 1;
+        uint32_t AON_PAD_P2_PD_1: 1;
+        uint32_t PAD_P2_PUPDC_1: 1;
+        uint32_t PAD_P2_WKEN_1: 1;
+        uint32_t PAD_P2_WKPOL_1: 1;
+        uint32_t PAD_P2_E2_1: 1;
+        uint32_t PAD_P2_SHDN_1: 1;
+        uint32_t PAD_P2_S_1: 1;
+        uint32_t PAD_P2_DEB_1: 1;
+        uint32_t PAD_P2_HS_MUX_1: 1;
+        uint32_t RSVD: 3;
+        uint32_t PAD_P2_O_EN_1: 1;
+    };
+} AON_NS_P2_0_P2_1_PAD_CFG_TYPE;
+
+/* 0x1924   0x4000_1924
+    0       R/W PAD_P2_O[2]                     1'b0
+    1       R/W PAD_P2_E[2]                     1'b0
+    2       R/W PAD_P2_PU_EN[2]                 1'b1
+    3       R/W AON_PAD_P2_PD[2]                1'b1
+    4       R/W PAD_P2_PUPDC[2]                 1'b0
+    5       R/W PAD_P2_WKEN[2]                  1'b0
+    6       R/W PAD_P2_WKPOL[2]                 1'b0
+    7       R/W PAD_P2_E2[2]                    1'b1
+    8       R/W PAD_P2_SHDN[2]                  1'b1
+    9       R/W PAD_P2_S[2]                     1'b0
+    10      R/W PAD_P2_DEB[2]                   1'b0
+    14:11   R   RSVD                            4'b0
+    15      R/W PAD_P2_O_EN[2]                  1'h1
+    16      R/W PAD_P2_O[3]                     1'b0
+    17      R/W PAD_P2_E[3]                     1'b0
+    18      R/W PAD_P2_PU_EN[3]                 1'b1
+    19      R/W AON_PAD_P2_PD[3]                1'b1
+    20      R/W PAD_P2_PUPDC[3]                 1'b0
+    21      R/W PAD_P2_WKEN[3]                  1'b0
+    22      R/W PAD_P2_WKPOL[3]                 1'b0
+    23      R/W PAD_P2_E2[3]                    1'b1
+    24      R/W PAD_P2_SHDN[3]                  1'b1
+    25      R/W PAD_P2_S[3]                     1'b0
+    26      R/W PAD_P2_DEB[3]                   1'b0
+    30:27   R   RSVD                            4'b0
+    31      R/W PAD_P2_O_EN[3]                  1'h1
+ */
+typedef volatile union _AON_NS_P2_2_P2_3_PAD_CFG_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t PAD_P2_O_2: 1;
+        uint32_t PAD_P2_E_2: 1;
+        uint32_t PAD_P2_PU_EN_2: 1;
+        uint32_t AON_PAD_P2_PD_2: 1;
+        uint32_t PAD_P2_PUPDC_2: 1;
+        uint32_t PAD_P2_WKEN_2: 1;
+        uint32_t PAD_P2_WKPOL_2: 1;
+        uint32_t PAD_P2_E2_2: 1;
+        uint32_t PAD_P2_SHDN_2: 1;
+        uint32_t PAD_P2_S_2: 1;
+        uint32_t PAD_P2_DEB_2: 1;
+        uint32_t RSVD_1: 4;
+        uint32_t PAD_P2_O_EN_2: 1;
+        uint32_t PAD_P2_O_3: 1;
+        uint32_t PAD_P2_E_3: 1;
+        uint32_t PAD_P2_PU_EN_3: 1;
+        uint32_t AON_PAD_P2_PD_3: 1;
+        uint32_t PAD_P2_PUPDC_3: 1;
+        uint32_t PAD_P2_WKEN_3: 1;
+        uint32_t PAD_P2_WKPOL_3: 1;
+        uint32_t PAD_P2_E2_3: 1;
+        uint32_t PAD_P2_SHDN_3: 1;
+        uint32_t PAD_P2_S_3: 1;
+        uint32_t PAD_P2_DEB_3: 1;
+        uint32_t RSVD: 4;
+        uint32_t PAD_P2_O_EN_3: 1;
+    };
+} AON_NS_P2_2_P2_3_PAD_CFG_TYPE;
+
+/* 0x1928   0x4000_1928
+    0       R/W PAD_P2_O[4]                     1'b0
+    1       R/W PAD_P2_E[4]                     1'b0
+    2       R/W PAD_P2_PU_EN[4]                 1'b1
+    3       R/W AON_PAD_P2_PD[4]                1'b1
+    4       R/W PAD_P2_PUPDC[4]                 1'b0
+    5       R/W PAD_P2_WKEN[4]                  1'b0
+    6       R/W PAD_P2_WKPOL[4]                 1'b0
+    7       R/W PAD_P2_E2[4]                    1'b1
+    8       R/W PAD_P2_SHDN[4]                  1'b1
+    9       R/W PAD_P2_S[4]                     1'b0
+    10      R/W PAD_P2_DEB[4]                   1'b0
+    11      R   RSVD                            1'b0
+    14:12   R/W PAD_P2_4_CFG                    3'h0
+    15      R/W PAD_P2_O_EN[4]                  1'h1
+    16      R/W PAD_P2_O[5]                     1'b0
+    17      R/W PAD_P2_E[5]                     1'b0
+    18      R/W PAD_P2_PU_EN[5]                 1'b1
+    19      R/W AON_PAD_P2_PD[5]                1'b1
+    20      R/W PAD_P2_PUPDC[5]                 1'b0
+    21      R/W PAD_P2_WKEN[5]                  1'b0
+    22      R/W PAD_P2_WKPOL[5]                 1'b0
+    23      R/W PAD_P2_E2[5]                    1'b1
+    24      R/W PAD_P2_SHDN[5]                  1'b1
+    25      R/W PAD_P2_S[5]                     1'b0
+    26      R/W PAD_P2_DEB[5]                   1'b0
+    28:27   R   RSVD                            2'b0
+    30:29   R/W PAD_P2_5_CFG                    2'h0
+    31      R/W PAD_P2_O_EN[5]                  1'h1
+ */
+typedef volatile union _AON_NS_P2_4_P2_5_PAD_CFG_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t PAD_P2_O_4: 1;
+        uint32_t PAD_P2_E_4: 1;
+        uint32_t PAD_P2_PU_EN_4: 1;
+        uint32_t AON_PAD_P2_PD_4: 1;
+        uint32_t PAD_P2_PUPDC_4: 1;
+        uint32_t PAD_P2_WKEN_4: 1;
+        uint32_t PAD_P2_WKPOL_4: 1;
+        uint32_t PAD_P2_E2_4: 1;
+        uint32_t PAD_P2_SHDN_4: 1;
+        uint32_t PAD_P2_S_4: 1;
+        uint32_t PAD_P2_DEB_4: 1;
+        uint32_t RSVD_1: 1;
+        uint32_t PAD_P2_4_CFG: 3;
+        uint32_t PAD_P2_O_EN_4: 1;
+        uint32_t PAD_P2_O_5: 1;
+        uint32_t PAD_P2_E_5: 1;
+        uint32_t PAD_P2_PU_EN_5: 1;
+        uint32_t AON_PAD_P2_PD_5: 1;
+        uint32_t PAD_P2_PUPDC_5: 1;
+        uint32_t PAD_P2_WKEN_5: 1;
+        uint32_t PAD_P2_WKPOL_5: 1;
+        uint32_t PAD_P2_E2_5: 1;
+        uint32_t PAD_P2_SHDN_5: 1;
+        uint32_t PAD_P2_S_5: 1;
+        uint32_t PAD_P2_DEB_5: 1;
+        uint32_t RSVD: 2;
+        uint32_t PAD_P2_5_CFG: 2;
+        uint32_t PAD_P2_O_EN_5: 1;
+    };
+} AON_NS_P2_4_P2_5_PAD_CFG_TYPE;
+
+/* 0x192C   0x4000_192c
+    0       R/W PAD_P2_O[6]                     1'b0
+    1       R/W PAD_P2_E[6]                     1'b0
+    2       R/W PAD_P2_PU_EN[6]                 1'b1
+    3       R/W AON_PAD_P2_PD[6]                1'b1
+    4       R/W PAD_P2_PUPDC[6]                 1'b0
+    5       R/W PAD_P2_WKEN[6]                  1'b0
+    6       R/W PAD_P2_WKPOL[6]                 1'b0
+    7       R/W PAD_P2_E2[6]                    1'b1
+    8       R/W PAD_P2_SHDN[6]                  1'b1
+    9       R/W PAD_P2_S[6]                     1'b0
+    10      R/W PAD_P2_DEB[6]                   1'b0
+    12:11   R   RSVD                            2'b0
+    13      R/W PAD_P2_6_dbg_en                 1'b0
+    14      R   RSVD                            1'h0
+    15      R/W PAD_P2_O_EN[6]                  1'h1
+    16      R/W PAD_P2_O[7]                     1'b0
+    17      R/W PAD_P2_E[7]                     1'b0
+    18      R/W PAD_P2_PU_EN[7]                 1'b1
+    19      R/W AON_PAD_P2_PD[7]                1'b1
+    20      R/W PAD_P2_PUPDC[7]                 1'b0
+    21      R/W PAD_P2_WKEN[7]                  1'b0
+    22      R/W PAD_P2_WKPOL[7]                 1'b0
+    23      R/W PAD_P2_E2[7]                    1'b1
+    24      R/W PAD_P2_SHDN[7]                  1'b1
+    25      R/W PAD_P2_S[7]                     1'b0
+    26      R/W PAD_P2_DEB[7]                   1'b0
+    28:27   R   RSVD                            2'b0
+    29      R/W PAD_P2_7_dbg_en                 1'b0
+    30      R   RSVD                            1'h0
+    31      R/W PAD_P2_O_EN[7]                  1'h1
+ */
+typedef volatile union _AON_NS_P2_6_P2_7_PAD_CFG_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t PAD_P2_O_6: 1;
+        uint32_t PAD_P2_E_6: 1;
+        uint32_t PAD_P2_PU_EN_6: 1;
+        uint32_t AON_PAD_P2_PD_6: 1;
+        uint32_t PAD_P2_PUPDC_6: 1;
+        uint32_t PAD_P2_WKEN_6: 1;
+        uint32_t PAD_P2_WKPOL_6: 1;
+        uint32_t PAD_P2_E2_6: 1;
+        uint32_t PAD_P2_SHDN_6: 1;
+        uint32_t PAD_P2_S_6: 1;
+        uint32_t PAD_P2_DEB_6: 1;
+        uint32_t RSVD_3: 2;
+        uint32_t PAD_P2_6_dbg_en: 1;
+        uint32_t RSVD_2: 1;
+        uint32_t PAD_P2_O_EN_6: 1;
+        uint32_t PAD_P2_O_7: 1;
+        uint32_t PAD_P2_E_7: 1;
+        uint32_t PAD_P2_PU_EN_7: 1;
+        uint32_t AON_PAD_P2_PD_7: 1;
+        uint32_t PAD_P2_PUPDC_7: 1;
+        uint32_t PAD_P2_WKEN_7: 1;
+        uint32_t PAD_P2_WKPOL_7: 1;
+        uint32_t PAD_P2_E2_7: 1;
+        uint32_t PAD_P2_SHDN_7: 1;
+        uint32_t PAD_P2_S_7: 1;
+        uint32_t PAD_P2_DEB_7: 1;
+        uint32_t RSVD_1: 2;
+        uint32_t PAD_P2_7_dbg_en: 1;
+        uint32_t RSVD: 1;
+        uint32_t PAD_P2_O_EN_7: 1;
+    };
+} AON_NS_P2_6_P2_7_PAD_CFG_TYPE;
+
+/* 0x1930   0x4000_1930
+    0       R/W PAD_P3_O[0]                     1'b0
+    1       R/W PAD_P3_E[0]                     1'b0
+    2       R/W PAD_P3_PU_EN[0]                 1'b1
+    3       R/W AON_PAD_P3_PD[0]                1'b0
+    4       R/W PAD_P3_PUPDC[0]                 1'b0
+    5       R/W PAD_P3_WKEN[0]                  1'b0
+    6       R/W PAD_P3_WKPOL[0]                 1'b0
+    7       R/W PAD_P3_E2[0]                    1'b1
+    8       R/W PAD_P3_SHDN[0]                  1'b1
+    9       R/W PAD_P3_S[0]                     1'b0
+    10      R/W PAD_P3_DEB[0]                   1'b0
+    14:11   R   RSVD                            4'b0
+    15      R/W PAD_P3_O_EN[0]                  1'h1
+    16      R/W PAD_P3_O[1]                     1'b0
+    17      R/W PAD_P3_E[1]                     1'b0
+    18      R/W PAD_P3_PU_EN[1]                 1'b1
+    19      R/W AON_PAD_P3_PD[1]                1'b0
+    20      R/W PAD_P3_PUPDC[1]                 1'b0
+    21      R/W PAD_P3_WKEN[1]                  1'b0
+    22      R/W PAD_P3_WKPOL[1]                 1'b0
+    23      R/W PAD_P3_E2[1]                    1'b1
+    24      R/W PAD_P3_SHDN[1]                  1'b1
+    25      R/W PAD_P3_S[1]                     1'b0
+    26      R/W PAD_P3_DEB[1]                   1'b0
+    30:27   R   RSVD                            4'b0
+    31      R/W PAD_P3_O_EN[1]                  1'h1
+ */
+typedef volatile union _AON_NS_P3_0_P3_1_PAD_CFG_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t PAD_P3_O_0: 1;
+        uint32_t PAD_P3_E_0: 1;
+        uint32_t PAD_P3_PU_EN_0: 1;
+        uint32_t AON_PAD_P3_PD_0: 1;
+        uint32_t PAD_P3_PUPDC_0: 1;
+        uint32_t PAD_P3_WKEN_0: 1;
+        uint32_t PAD_P3_WKPOL_0: 1;
+        uint32_t PAD_P3_E2_0: 1;
+        uint32_t PAD_P3_SHDN_0: 1;
+        uint32_t PAD_P3_S_0: 1;
+        uint32_t PAD_P3_DEB_0: 1;
+        uint32_t RSVD_1: 4;
+        uint32_t PAD_P3_O_EN_0: 1;
+        uint32_t PAD_P3_O_1: 1;
+        uint32_t PAD_P3_E_1: 1;
+        uint32_t PAD_P3_PU_EN_1: 1;
+        uint32_t AON_PAD_P3_PD_1: 1;
+        uint32_t PAD_P3_PUPDC_1: 1;
+        uint32_t PAD_P3_WKEN_1: 1;
+        uint32_t PAD_P3_WKPOL_1: 1;
+        uint32_t PAD_P3_E2_1: 1;
+        uint32_t PAD_P3_SHDN_1: 1;
+        uint32_t PAD_P3_S_1: 1;
+        uint32_t PAD_P3_DEB_1: 1;
+        uint32_t RSVD: 4;
+        uint32_t PAD_P3_O_EN_1: 1;
+    };
+} AON_NS_P3_0_P3_1_PAD_CFG_TYPE;
+
+/* 0x1934   0x4000_1934
+    0       R/W PAD_P3_O[2]                     1'b0
+    1       R/W PAD_P3_E[2]                     1'b0
+    2       R/W PAD_P3_PU_EN[2]                 1'b1
+    3       R/W AON_PAD_P3_PD[2]                1'b1
+    4       R/W PAD_P3_PUPDC[2]                 1'b0
+    5       R/W PAD_P3_WKEN[2]                  1'b0
+    6       R/W PAD_P3_WKPOL[2]                 1'b0
+    7       R/W PAD_P3_E2[2]                    1'b1
+    8       R/W PAD_P3_SHDN[2]                  1'b1
+    9       R/W PAD_P3_S[2]                     1'b0
+    10      R/W PAD_P3_DEB[2]                   1'b0
+    11      R/W PAD_P3_HS_MUX[2]                1'b0
+    14:12   R   RSVD                            3'b0
+    15      R/W PAD_P3_O_EN[2]                  1'h1
+    16      R/W PAD_P3_O[3]                     1'b0
+    17      R/W PAD_P3_E[3]                     1'b0
+    18      R/W PAD_P3_PU_EN[3]                 1'b1
+    19      R/W AON_PAD_P3_PD[3]                1'b1
+    20      R/W PAD_P3_PUPDC[3]                 1'b0
+    21      R/W PAD_P3_WKEN[3]                  1'b0
+    22      R/W PAD_P3_WKPOL[3]                 1'b0
+    23      R/W PAD_P3_E2[3]                    1'b1
+    24      R/W PAD_P3_SHDN[3]                  1'b1
+    25      R/W PAD_P3_S[3]                     1'b0
+    26      R/W PAD_P3_DEB[3]                   1'b0
+    27      R/W PAD_P3_HS_MUX[3]                1'b0
+    30:28   R   RSVD                            3'b0
+    31      R/W PAD_P3_O_EN[3]                  1'h1
+ */
+typedef volatile union _AON_NS_P3_2_P3_3_PAD_CFG_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t PAD_P3_O_2: 1;
+        uint32_t PAD_P3_E_2: 1;
+        uint32_t PAD_P3_PU_EN_2: 1;
+        uint32_t AON_PAD_P3_PD_2: 1;
+        uint32_t PAD_P3_PUPDC_2: 1;
+        uint32_t PAD_P3_WKEN_2: 1;
+        uint32_t PAD_P3_WKPOL_2: 1;
+        uint32_t PAD_P3_E2_2: 1;
+        uint32_t PAD_P3_SHDN_2: 1;
+        uint32_t PAD_P3_S_2: 1;
+        uint32_t PAD_P3_DEB_2: 1;
+        uint32_t PAD_P3_HS_MUX_2: 1;
+        uint32_t RSVD_1: 3;
+        uint32_t PAD_P3_O_EN_2: 1;
+        uint32_t PAD_P3_O_3: 1;
+        uint32_t PAD_P3_E_3: 1;
+        uint32_t PAD_P3_PU_EN_3: 1;
+        uint32_t AON_PAD_P3_PD_3: 1;
+        uint32_t PAD_P3_PUPDC_3: 1;
+        uint32_t PAD_P3_WKEN_3: 1;
+        uint32_t PAD_P3_WKPOL_3: 1;
+        uint32_t PAD_P3_E2_3: 1;
+        uint32_t PAD_P3_SHDN_3: 1;
+        uint32_t PAD_P3_S_3: 1;
+        uint32_t PAD_P3_DEB_3: 1;
+        uint32_t PAD_P3_HS_MUX_3: 1;
+        uint32_t RSVD: 3;
+        uint32_t PAD_P3_O_EN_3: 1;
+    };
+} AON_NS_P3_2_P3_3_PAD_CFG_TYPE;
+
+/* 0x1938   0x4000_1938
+    0       R/W PAD_P3_O[4]                     1'b0
+    1       R/W PAD_P3_E[4]                     1'b0
+    2       R/W PAD_P3_PU_EN[4]                 1'b1
+    3       R/W AON_PAD_P3_PD[4]                1'b1
+    4       R/W PAD_P3_PUPDC[4]                 1'b0
+    5       R/W PAD_P3_WKEN[4]                  1'b0
+    6       R/W PAD_P3_WKPOL[4]                 1'b0
+    7       R/W PAD_P3_E2[4]                    1'b1
+    8       R/W PAD_P3_SHDN[4]                  1'b1
+    9       R/W PAD_P3_S[4]                     1'b0
+    10      R/W PAD_P3_DEB[4]                   1'b0
+    11      R/W PAD_P3_HS_MUX[4]                1'b0
+    14:12   R   RSVD                            3'b0
+    15      R/W PAD_P3_O_EN[4]                  1'h1
+    16      R/W PAD_P3_O[5]                     1'b0
+    17      R/W PAD_P3_E[5]                     1'b0
+    18      R/W PAD_P3_PU_EN[5]                 1'b1
+    19      R/W AON_PAD_P3_PD[5]                1'b1
+    20      R/W PAD_P3_PUPDC[5]                 1'b0
+    21      R/W PAD_P3_WKEN[5]                  1'b0
+    22      R/W PAD_P3_WKPOL[5]                 1'b0
+    23      R/W PAD_P3_E2[5]                    1'b1
+    24      R/W PAD_P3_SHDN[5]                  1'b1
+    25      R/W PAD_P3_S[5]                     1'b0
+    26      R/W PAD_P3_DEB[5]                   1'b0
+    27      R/W PAD_P3_HS_MUX[5]                1'b0
+    30:28   R   RSVD                            3'b0
+    31      R/W PAD_P3_O_EN[5]                  1'h1
+ */
+typedef volatile union _AON_NS_P3_4_P3_5_PAD_CFG_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t PAD_P3_O_4: 1;
+        uint32_t PAD_P3_E_4: 1;
+        uint32_t PAD_P3_PU_EN_4: 1;
+        uint32_t AON_PAD_P3_PD_4: 1;
+        uint32_t PAD_P3_PUPDC_4: 1;
+        uint32_t PAD_P3_WKEN_4: 1;
+        uint32_t PAD_P3_WKPOL_4: 1;
+        uint32_t PAD_P3_E2_4: 1;
+        uint32_t PAD_P3_SHDN_4: 1;
+        uint32_t PAD_P3_S_4: 1;
+        uint32_t PAD_P3_DEB_4: 1;
+        uint32_t PAD_P3_HS_MUX_4: 1;
+        uint32_t RSVD_1: 3;
+        uint32_t PAD_P3_O_EN_4: 1;
+        uint32_t PAD_P3_O_5: 1;
+        uint32_t PAD_P3_E_5: 1;
+        uint32_t PAD_P3_PU_EN_5: 1;
+        uint32_t AON_PAD_P3_PD_5: 1;
+        uint32_t PAD_P3_PUPDC_5: 1;
+        uint32_t PAD_P3_WKEN_5: 1;
+        uint32_t PAD_P3_WKPOL_5: 1;
+        uint32_t PAD_P3_E2_5: 1;
+        uint32_t PAD_P3_SHDN_5: 1;
+        uint32_t PAD_P3_S_5: 1;
+        uint32_t PAD_P3_DEB_5: 1;
+        uint32_t PAD_P3_HS_MUX_5: 1;
+        uint32_t RSVD: 3;
+        uint32_t PAD_P3_O_EN_5: 1;
+    };
+} AON_NS_P3_4_P3_5_PAD_CFG_TYPE;
+
+/* 0x193C   0x4000_193c
+    0       R/W PAD_P3_O[6]                     1'b0
+    1       R/W PAD_P3_E[6]                     1'b0
+    2       R/W PAD_P3_PU_EN[6]                 1'b1
+    3       R/W AON_PAD_P3_PD[6]                1'b1
+    4       R/W PAD_P3_PUPDC[6]                 1'b0
+    5       R/W PAD_P3_WKEN[6]                  1'b0
+    6       R/W PAD_P3_WKPOL[6]                 1'b0
+    7       R/W PAD_P3_E2[6]                    1'b1
+    8       R/W PAD_P3_SHDN[6]                  1'b1
+    9       R/W PAD_P3_S[6]                     1'b0
+    10      R/W PAD_P3_DEB[6]                   1'b0
+    11      R/W PAD_P3_HS_MUX[6]                1'b0
+    14:12   R   RSVD                            3'b0
+    15      R/W PAD_P3_O_EN[6]                  1'h1
+    16      R/W PAD_P3_O[7]                     1'b0
+    17      R/W PAD_P3_E[7]                     1'b0
+    18      R/W PAD_P3_PU_EN[7]                 1'b1
+    19      R/W AON_PAD_P3_PD[7]                1'b1
+    20      R/W PAD_P3_PUPDC[7]                 1'b0
+    21      R/W PAD_P3_WKEN[7]                  1'b0
+    22      R/W PAD_P3_WKPOL[7]                 1'b0
+    23      R/W PAD_P3_E2[7]                    1'b1
+    24      R/W PAD_P3_SHDN[7]                  1'b1
+    25      R/W PAD_P3_S[7]                     1'b0
+    26      R/W PAD_P3_DEB[7]                   1'b0
+    27      R/W PAD_P3_HS_MUX[7]                1'b0
+    29:28   R   RSVD                            2'b0
+    30      R/W PAD_P3_7_CFG                    1'h0
+    31      R/W PAD_P3_O_EN[7]                  1'h1
+ */
+typedef volatile union _AON_NS_P3_6_P3_7_PAD_CFG_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t PAD_P3_O_6: 1;
+        uint32_t PAD_P3_E_6: 1;
+        uint32_t PAD_P3_PU_EN_6: 1;
+        uint32_t AON_PAD_P3_PD_6: 1;
+        uint32_t PAD_P3_PUPDC_6: 1;
+        uint32_t PAD_P3_WKEN_6: 1;
+        uint32_t PAD_P3_WKPOL_6: 1;
+        uint32_t PAD_P3_E2_6: 1;
+        uint32_t PAD_P3_SHDN_6: 1;
+        uint32_t PAD_P3_S_6: 1;
+        uint32_t PAD_P3_DEB_6: 1;
+        uint32_t PAD_P3_HS_MUX_6: 1;
+        uint32_t RSVD_1: 3;
+        uint32_t PAD_P3_O_EN_6: 1;
+        uint32_t PAD_P3_O_7: 1;
+        uint32_t PAD_P3_E_7: 1;
+        uint32_t PAD_P3_PU_EN_7: 1;
+        uint32_t AON_PAD_P3_PD_7: 1;
+        uint32_t PAD_P3_PUPDC_7: 1;
+        uint32_t PAD_P3_WKEN_7: 1;
+        uint32_t PAD_P3_WKPOL_7: 1;
+        uint32_t PAD_P3_E2_7: 1;
+        uint32_t PAD_P3_SHDN_7: 1;
+        uint32_t PAD_P3_S_7: 1;
+        uint32_t PAD_P3_DEB_7: 1;
+        uint32_t PAD_P3_HS_MUX_7: 1;
+        uint32_t RSVD: 2;
+        uint32_t PAD_P3_7_CFG: 1;
+        uint32_t PAD_P3_O_EN_7: 1;
+    };
+} AON_NS_P3_6_P3_7_PAD_CFG_TYPE;
+
+/* 0x1940   0x4000_1940
+    0       R/W PAD_P4_O[0]                     1'b0
+    1       R/W PAD_P4_E[0]                     1'b0
+    2       R/W PAD_P4_PU_EN[0]                 1'b1
+    3       R/W AON_PAD_P4_PD[0]                1'b1
+    4       R/W PAD_P4_PUPDC[0]                 1'b0
+    5       R/W PAD_P4_WKEN[0]                  1'b0
+    6       R/W PAD_P4_WKPOL[0]                 1'b0
+    7       R/W PAD_P4_E2[0]                    1'b1
+    8       R/W PAD_P4_SHDN[0]                  1'b1
+    9       R/W PAD_P4_S[0]                     1'b0
+    10      R/W PAD_P4_DEB[0]                   1'b0
+    11      R/W PAD_P4_HS_MUX[0]                1'b0
+    13:12   R/W PAD_P4_0_CFG                    2'h0
+    14      R/W PAD_P4_O_EN[0]                  1'h1
+    15      R   RSVD                            1'b0
+    16      R/W PAD_P4_O[1]                     1'b0
+    17      R/W PAD_P4_E[1]                     1'b0
+    18      R/W PAD_P4_PU_EN[1]                 1'b1
+    19      R/W AON_PAD_P4_PD[1]                1'b1
+    20      R/W PAD_P4_PUPDC[1]                 1'b0
+    21      R/W PAD_P4_WKEN[1]                  1'b0
+    22      R/W PAD_P4_WKPOL[1]                 1'b0
+    23      R/W PAD_P4_E2[1]                    1'b1
+    24      R/W PAD_P4_SHDN[1]                  1'b1
+    25      R/W PAD_P4_S[1]                     1'b0
+    26      R/W PAD_P4_DEB[1]                   1'b0
+    27      R/W PAD_P4_HS_MUX[1]                1'b0
+    30:28   R   RSVD                            3'b0
+    31      R/W PAD_P4_O_EN[1]                  1'h1
+ */
+typedef volatile union _AON_NS_P4_0_P4_1_PAD_CFG_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t PAD_P4_O_0: 1;
+        uint32_t PAD_P4_E_0: 1;
+        uint32_t PAD_P4_PU_EN_0: 1;
+        uint32_t AON_PAD_P4_PD_0: 1;
+        uint32_t PAD_P4_PUPDC_0: 1;
+        uint32_t PAD_P4_WKEN_0: 1;
+        uint32_t PAD_P4_WKPOL_0: 1;
+        uint32_t PAD_P4_E2_0: 1;
+        uint32_t PAD_P4_SHDN_0: 1;
+        uint32_t PAD_P4_S_0: 1;
+        uint32_t PAD_P4_DEB_0: 1;
+        uint32_t PAD_P4_HS_MUX_0: 1;
+        uint32_t PAD_P4_0_CFG: 2;
+        uint32_t PAD_P4_O_EN_0: 1;
+        uint32_t RSVD_1: 1;
+        uint32_t PAD_P4_O_1: 1;
+        uint32_t PAD_P4_E_1: 1;
+        uint32_t PAD_P4_PU_EN_1: 1;
+        uint32_t AON_PAD_P4_PD_1: 1;
+        uint32_t PAD_P4_PUPDC_1: 1;
+        uint32_t PAD_P4_WKEN_1: 1;
+        uint32_t PAD_P4_WKPOL_1: 1;
+        uint32_t PAD_P4_E2_1: 1;
+        uint32_t PAD_P4_SHDN_1: 1;
+        uint32_t PAD_P4_S_1: 1;
+        uint32_t PAD_P4_DEB_1: 1;
+        uint32_t PAD_P4_HS_MUX_1: 1;
+        uint32_t RSVD: 3;
+        uint32_t PAD_P4_O_EN_1: 1;
+    };
+} AON_NS_P4_0_P4_1_PAD_CFG_TYPE;
+
+/* 0x1944   0x4000_1944
+    0       R/W PAD_P4_O[2]                     1'b0
+    1       R/W PAD_P4_E[2]                     1'b0
+    2       R/W PAD_P4_PU_EN[2]                 1'b1
+    3       R/W AON_PAD_P4_PD[2]                1'b1
+    4       R/W PAD_P4_PUPDC[2]                 1'b0
+    5       R/W PAD_P4_WKEN[2]                  1'b0
+    6       R/W PAD_P4_WKPOL[2]                 1'b0
+    7       R/W PAD_P4_E2[2]                    1'b1
+    8       R/W PAD_P4_SHDN[2]                  1'b1
+    9       R/W PAD_P4_S[2]                     1'b0
+    10      R/W PAD_P4_DEB[2]                   1'b0
+    11      R/W PAD_P4_HS_MUX[2]                1'b0
+    14:12   R   RSVD                            3'b0
+    15      R/W PAD_P4_O_EN[2]                  1'h1
+    16      R/W PAD_P4_O[3]                     1'b0
+    17      R/W PAD_P4_E[3]                     1'b0
+    18      R/W PAD_P4_PU_EN[3]                 1'b1
+    19      R/W AON_PAD_P4_PD[3]                1'b0
+    20      R/W PAD_P4_PUPDC[3]                 1'b0
+    21      R/W PAD_P4_WKEN[3]                  1'b0
+    22      R/W PAD_P4_WKPOL[3]                 1'b0
+    23      R/W PAD_P4_E2[3]                    1'b1
+    24      R/W PAD_P4_SHDN[3]                  1'b1
+    25      R/W PAD_P4_S[3]                     1'b0
+    26      R/W PAD_P4_DEB[3]                   1'b0
+    27      R/W PAD_P4_HS_MUX[3]                1'b0
+    30:28   R   RSVD                            3'b0
+    31      R/W PAD_P4_O_EN[3]                  1'h1
+ */
+typedef volatile union _AON_NS_P4_2_P4_3_PAD_CFG_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t PAD_P4_O_2: 1;
+        uint32_t PAD_P4_E_2: 1;
+        uint32_t PAD_P4_PU_EN_2: 1;
+        uint32_t AON_PAD_P4_PD_2: 1;
+        uint32_t PAD_P4_PUPDC_2: 1;
+        uint32_t PAD_P4_WKEN_2: 1;
+        uint32_t PAD_P4_WKPOL_2: 1;
+        uint32_t PAD_P4_E2_2: 1;
+        uint32_t PAD_P4_SHDN_2: 1;
+        uint32_t PAD_P4_S_2: 1;
+        uint32_t PAD_P4_DEB_2: 1;
+        uint32_t PAD_P4_HS_MUX_2: 1;
+        uint32_t RSVD_1: 3;
+        uint32_t PAD_P4_O_EN_2: 1;
+        uint32_t PAD_P4_O_3: 1;
+        uint32_t PAD_P4_E_3: 1;
+        uint32_t PAD_P4_PU_EN_3: 1;
+        uint32_t AON_PAD_P4_PD_3: 1;
+        uint32_t PAD_P4_PUPDC_3: 1;
+        uint32_t PAD_P4_WKEN_3: 1;
+        uint32_t PAD_P4_WKPOL_3: 1;
+        uint32_t PAD_P4_E2_3: 1;
+        uint32_t PAD_P4_SHDN_3: 1;
+        uint32_t PAD_P4_S_3: 1;
+        uint32_t PAD_P4_DEB_3: 1;
+        uint32_t PAD_P4_HS_MUX_3: 1;
+        uint32_t RSVD: 3;
+        uint32_t PAD_P4_O_EN_3: 1;
+    };
+} AON_NS_P4_2_P4_3_PAD_CFG_TYPE;
+
+/* 0x1948   0x4000_1948
+    0       R/W PAD_32K_XI_O                    1'b0
+    1       R/W PAD_32K_XI_E                    1'b0
+    2       R/W PAD_32K_XI_PU_EN                1'b1
+    3       R/W AON_PAD_32K_XI_PD               1'b1
+    4       R/W PAD_32K_XI_PUPDC                1'b0
+    5       R/W PAD_32K_XI_WKEN                 1'b0
+    6       R/W PAD_32K_XI_WKPOL                1'b0
+    7       R/W PAD_32K_XI_E2                   1'b1
+    8       R/W PAD_32K_XI_SHDN                 1'b1
+    9       R/W PAD_32K_XI_S                    1'b0
+    10      R/W PAD_32K_XI_DEB                  1'b0
+    12:11   R   RSVD                            2'b0
+    13      R/W PAD_32K_XI_dbg_en               1'b0
+    14      R   RSVD                            1'h0
+    15      R/W PAD_32K_XI_O_EN                 1'h1
+    16      R/W PAD_32K_XO_O                    1'b0
+    17      R/W PAD_32K_XO_E                    1'b0
+    18      R/W PAD_32K_XO_PU_EN                1'b1
+    19      R/W AON_PAD_32K_XO_PD               1'b1
+    20      R/W PAD_32K_XO_PUPDC                1'b0
+    21      R/W PAD_32K_XO_WKEN                 1'b0
+    22      R/W PAD_32K_XO_WKPOL                1'b0
+    23      R/W PAD_32K_XO_E2                   1'b1
+    24      R/W PAD_32K_XO_SHDN                 1'b1
+    25      R/W PAD_32K_XO_S                    1'b0
+    26      R/W PAD_32K_XO_DEB                  1'b0
+    28:27   R   RSVD                            2'b0
+    29      R/W PAD_32K_XO_dbg_en               1'b0
+    30      R   RSVD                            1'h0
+    31      R/W PAD_32K_XO_O_EN                 1'h1
+ */
+typedef volatile union _AON_NS_P32K_XI_P32K_XO_PAD_CFG_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t PAD_32K_XI_O: 1;
+        uint32_t PAD_32K_XI_E: 1;
+        uint32_t PAD_32K_XI_PU_EN: 1;
+        uint32_t AON_PAD_32K_XI_PD: 1;
+        uint32_t PAD_32K_XI_PUPDC: 1;
+        uint32_t PAD_32K_XI_WKEN: 1;
+        uint32_t PAD_32K_XI_WKPOL: 1;
+        uint32_t PAD_32K_XI_E2: 1;
+        uint32_t PAD_32K_XI_SHDN: 1;
+        uint32_t PAD_32K_XI_S: 1;
+        uint32_t PAD_32K_XI_DEB: 1;
+        uint32_t RSVD_3: 2;
+        uint32_t PAD_32K_XI_dbg_en: 1;
+        uint32_t RSVD_2: 1;
+        uint32_t PAD_32K_XI_O_EN: 1;
+        uint32_t PAD_32K_XO_O: 1;
+        uint32_t PAD_32K_XO_E: 1;
+        uint32_t PAD_32K_XO_PU_EN: 1;
+        uint32_t AON_PAD_32K_XO_PD: 1;
+        uint32_t PAD_32K_XO_PUPDC: 1;
+        uint32_t PAD_32K_XO_WKEN: 1;
+        uint32_t PAD_32K_XO_WKPOL: 1;
+        uint32_t PAD_32K_XO_E2: 1;
+        uint32_t PAD_32K_XO_SHDN: 1;
+        uint32_t PAD_32K_XO_S: 1;
+        uint32_t PAD_32K_XO_DEB: 1;
+        uint32_t RSVD_1: 2;
+        uint32_t PAD_32K_XO_dbg_en: 1;
+        uint32_t RSVD: 1;
+        uint32_t PAD_32K_XO_O_EN: 1;
+    };
+} AON_NS_P32K_XI_P32K_XO_PAD_CFG_TYPE;
+
+/* 0x194C   0x4000_194c
+    0       R/W PAD_MICBIAS_O                   1'b0
+    1       R/W PAD_MICBIAS_E                   1'b0
+    2       R/W PAD_MICBIAS_PU_EN               1'b1
+    3       R/W AON_PAD_MICBIAS_PD              1'b1
+    4       R/W PAD_MICBIAS_PUPDC               1'b0
+    5       R/W PAD_MICBIAS_WKEN                1'b0
+    6       R/W PAD_MICBIAS_WKPOL               1'b0
+    7       R/W PAD_MICBIAS_E2                  1'b1
+    8       R/W PAD_MICBIAS_SHDN                1'b1
+    9       R/W PAD_MICBIAS_S                   1'b0
+    10      R/W PAD_MICBIAS_DEB                 1'b0
+    12:11   R   RSVD                            2'b0
+    13      R/W PAD_MICBIAS_dbg_en              1'b0
+    14      R   RSVD                            1'h0
+    15      R/W PAD_MICBIAS_O_EN                1'h1
+    16      R   RSVD                            1'b0
+    17      R   RSVD                            1'b0
+    18      R   RSVD                            1'b1
+    19      R   RSVD                            1'b1
+    20      R   RSVD                            1'b0
+    21      R   RSVD                            1'b0
+    22      R   RSVD                            1'b0
+    23      R   RSVD                            1'b0
+    24      R   RSVD                            1'b1
+    25      R   RSVD                            1'b0
+    26      R   RSVD                            1'b0
+    28:27   R   RSVD                            2'b0
+    29      R   RSVD                            1'b0
+    31:30   R   RSVD                            2'h0
+ */
+typedef volatile union _AON_NS_P_MICBIAS_PAD_CFG_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t PAD_MICBIAS_O: 1;
+        uint32_t PAD_MICBIAS_E: 1;
+        uint32_t PAD_MICBIAS_PU_EN: 1;
+        uint32_t AON_PAD_MICBIAS_PD: 1;
+        uint32_t PAD_MICBIAS_PUPDC: 1;
+        uint32_t PAD_MICBIAS_WKEN: 1;
+        uint32_t PAD_MICBIAS_WKPOL: 1;
+        uint32_t PAD_MICBIAS_E2: 1;
+        uint32_t PAD_MICBIAS_SHDN: 1;
+        uint32_t PAD_MICBIAS_S: 1;
+        uint32_t PAD_MICBIAS_DEB: 1;
+        uint32_t RSVD_15: 2;
+        uint32_t PAD_MICBIAS_dbg_en: 1;
+        uint32_t RSVD_14: 1;
+        uint32_t PAD_MICBIAS_O_EN: 1;
+        uint32_t RSVD_13: 1;
+        uint32_t RSVD_12: 1;
+        uint32_t RSVD_11: 1;
+        uint32_t RSVD_10: 1;
+        uint32_t RSVD_9: 1;
+        uint32_t RSVD_8: 1;
+        uint32_t RSVD_7: 1;
+        uint32_t RSVD_6: 1;
+        uint32_t RSVD_5: 1;
+        uint32_t RSVD_4: 1;
+        uint32_t RSVD_3: 1;
+        uint32_t RSVD_2: 2;
+        uint32_t RSVD_1: 1;
+        uint32_t RSVD: 2;
+    };
+} AON_NS_P_MICBIAS_PAD_CFG_TYPE;
+
+/* 0x1950   0x4000_1950
+    0       R/W TOP_PAD_SMT                     1'b0
+    1       R/W BOT_PAD_SMT                     1'b0
+    2       R/W LEFT_PAD_SMT                    1'b0
+    3       R/W RIGHT_PAD_SMT                   1'b0
+    4       R/W POWPAD1                         1'b1
+    31:5    R   RSVD                            27'h0
+ */
+typedef volatile union _AON_NS_COMMON_PAD_CFG_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t TOP_PAD_SMT: 1;
+        uint32_t BOT_PAD_SMT: 1;
+        uint32_t LEFT_PAD_SMT: 1;
+        uint32_t RIGHT_PAD_SMT: 1;
+        uint32_t POWPAD1: 1;
+        uint32_t RSVD: 27;
+    };
+} AON_NS_COMMON_PAD_CFG_TYPE;
+
+/* 0x1954   0x4000_1954
+    0       R   RSVD                            1'b1
+    1       R   RSVD                            1'b1
+    2       R   RSVD                            1'b0
+    3       R   RSVD                            1'b0
+    4       R   RSVD                            1'b0
+    5       R   RSVD                            1'b0
+    6       R   RSVD                            1'b0
+    7       R   RSVD                            1'b0
+    8       R   RSVD                            1'b0
+    9       R   RSVD                            1'b0
+    10      R   RSVD                            1'b0
+    11      R   RSVD                            1'b0
+    12      R   RSVD                            1'b0
+    13      R   RSVD                            1'b0
+    14      R   RSVD                            1'b1
+    15      R   RSVD                            1'b1
+    16      R   RSVD                            1'b0
+    17      R   RSVD                            1'b0
+    18      R   RSVD                            1'b0
+    19      R   RSVD                            1'b0
+    20      R   RSVD                            1'b0
+    21      R   RSVD                            1'b0
+    31:22   R   RSVD                            10'h0
+ */
+typedef volatile union _AON_NS_P_SPI_PAD_CFG_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RSVD_22: 1;
+        uint32_t RSVD_21: 1;
+        uint32_t RSVD_20: 1;
+        uint32_t RSVD_19: 1;
+        uint32_t RSVD_18: 1;
+        uint32_t RSVD_17: 1;
+        uint32_t RSVD_16: 1;
+        uint32_t RSVD_15: 1;
+        uint32_t RSVD_14: 1;
+        uint32_t RSVD_13: 1;
+        uint32_t RSVD_12: 1;
+        uint32_t RSVD_11: 1;
+        uint32_t RSVD_10: 1;
+        uint32_t RSVD_9: 1;
+        uint32_t RSVD_8: 1;
+        uint32_t RSVD_7: 1;
+        uint32_t RSVD_6: 1;
+        uint32_t RSVD_5: 1;
+        uint32_t RSVD_4: 1;
+        uint32_t RSVD_3: 1;
+        uint32_t RSVD_2: 1;
+        uint32_t RSVD_1: 1;
+        uint32_t RSVD: 10;
+    };
+} AON_NS_P_SPI_PAD_CFG_TYPE;
+
+/* 0x1958   0x4000_1958
+    0       R/W PAD_DAC_N_O                     1'b0
+    1       R/W PAD_DAC_N_E                     1'b0
+    2       R/W PAD_DAC_N_PU_EN                 1'b1
+    3       R/W AON_PAD_DAC_N_PD                1'b1
+    4       R/W PAD_DAC_N_PUPDC                 1'b0
+    5       R/W PAD_DAC_N_WKEN                  1'b0
+    6       R/W PAD_DAC_N_WKPOL                 1'b0
+    7       R/W PAD_DAC_N_E2                    1'b1
+    8       R/W PAD_DAC_N_SHDN                  1'b1
+    9       R/W PAD_DAC_N_S                     1'b0
+    10      R/W PAD_DAC_N_DEB                   1'b0
+    12:11   R   RSVD                            2'b0
+    13      R/W PAD_DAC_N_dummy                 1'b0
+    14      R   RSVD                            1'h0
+    15      R/W PAD_DAC_N_O_EN                  1'h1
+    16      R/W PAD_DAC_P_O                     1'b0
+    17      R/W PAD_DAC_P_E                     1'b0
+    18      R/W PAD_DAC_P_PU_EN                 1'b1
+    19      R/W AON_PAD_DAC_P_PD                1'b1
+    20      R/W PAD_DAC_P_PUPDC                 1'b0
+    21      R/W PAD_DAC_P_WKEN                  1'b0
+    22      R/W PAD_DAC_P_WKPOL                 1'b0
+    23      R/W PAD_DAC_N_E2                    1'b1
+    24      R/W PAD_DAC_P_SHDN                  1'b1
+    25      R/W PAD_DAC_P_S                     1'b0
+    26      R/W PAD_DAC_P_DEB                   1'b0
+    28:27   R   RSVD                            2'b0
+    29      R/W PAD_DAC_P_dummy                 1'b0
+    30      R   RSVD                            1'h0
+    31      R/W PAD_DAC_P_O_EN                  1'h1
+ */
+typedef volatile union _AON_NS_DAC_P_DAC_N_PAD_CFG_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t PAD_DAC_N_O: 1;
+        uint32_t PAD_DAC_N_E: 1;
+        uint32_t PAD_DAC_N_PU_EN: 1;
+        uint32_t AON_PAD_DAC_N_PD: 1;
+        uint32_t PAD_DAC_N_PUPDC: 1;
+        uint32_t PAD_DAC_N_WKEN: 1;
+        uint32_t PAD_DAC_N_WKPOL: 1;
+        uint32_t PAD_DAC_N_E2_1: 1;
+        uint32_t PAD_DAC_N_SHDN: 1;
+        uint32_t PAD_DAC_N_S: 1;
+        uint32_t PAD_DAC_N_DEB: 1;
+        uint32_t RSVD_3: 2;
+        uint32_t PAD_DAC_N_dummy: 1;
+        uint32_t RSVD_2: 1;
+        uint32_t PAD_DAC_N_O_EN: 1;
+        uint32_t PAD_DAC_P_O: 1;
+        uint32_t PAD_DAC_P_E: 1;
+        uint32_t PAD_DAC_P_PU_EN: 1;
+        uint32_t AON_PAD_DAC_P_PD: 1;
+        uint32_t PAD_DAC_P_PUPDC: 1;
+        uint32_t PAD_DAC_P_WKEN: 1;
+        uint32_t PAD_DAC_P_WKPOL: 1;
+        uint32_t PAD_DAC_N_E2: 1;
+        uint32_t PAD_DAC_P_SHDN: 1;
+        uint32_t PAD_DAC_P_S: 1;
+        uint32_t PAD_DAC_P_DEB: 1;
+        uint32_t RSVD_1: 2;
+        uint32_t PAD_DAC_P_dummy: 1;
+        uint32_t RSVD: 1;
+        uint32_t PAD_DAC_P_O_EN: 1;
+    };
+} AON_NS_DAC_P_DAC_N_PAD_CFG_TYPE;
+
+/* 0x195C   0x4000_195c
+    0       R/W PAD_P4_O[4]                     1'b0
+    1       R/W PAD_P4_E[4]                     1'b0
+    2       R/W PAD_P4_PU_EN[4]                 1'b1
+    3       R/W AON_PAD_P4_PD[4]                1'b1
+    4       R/W PAD_P4_PUPDC[4]                 1'b0
+    5       R/W PAD_P4_WKEN[4]                  1'b0
+    6       R/W PAD_P4_WKPOL[4]                 1'b0
+    7       R/W PAD_P4_E2[4]                    1'b1
+    8       R/W PAD_P4_SHDN[4]                  1'b1
+    9       R/W PAD_P4_S[4]                     1'b0
+    10      R/W PAD_P4_DEB[4]                   1'b0
+    11      R/W PAD_P4_HS_MUX[4]                1'b0
+    14:12   R   RSVD                            3'b0
+    15      R/W PAD_P4_O_EN[4]                  1'h1
+    16      R/W PAD_P4_O[5]                     1'b0
+    17      R/W PAD_P4_E[5]                     1'b0
+    18      R/W PAD_P4_PU_EN[5]                 1'b1
+    19      R/W AON_PAD_P4_PD[5]                1'b1
+    20      R/W PAD_P4_PUPDC[5]                 1'b0
+    21      R/W PAD_P4_WKEN[5]                  1'b0
+    22      R/W PAD_P4_WKPOL[5]                 1'b0
+    23      R/W PAD_P4_E2[5]                    1'b1
+    24      R/W PAD_P4_SHDN[5]                  1'b1
+    25      R/W PAD_P4_S[5]                     1'b0
+    26      R/W PAD_P4_DEB[5]                   1'b0
+    27      R/W PAD_P4_HS_MUX[5]                1'b0
+    30:28   R   RSVD                            3'b0
+    31      R/W PAD_P4_O_EN[5]                  1'h1
+ */
+typedef volatile union _AON_NS_P4_4_P4_5_PAD_CFG_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t PAD_P4_O_4: 1;
+        uint32_t PAD_P4_E_4: 1;
+        uint32_t PAD_P4_PU_EN_4: 1;
+        uint32_t AON_PAD_P4_PD_4: 1;
+        uint32_t PAD_P4_PUPDC_4: 1;
+        uint32_t PAD_P4_WKEN_4: 1;
+        uint32_t PAD_P4_WKPOL_4: 1;
+        uint32_t PAD_P4_E2_4: 1;
+        uint32_t PAD_P4_SHDN_4: 1;
+        uint32_t PAD_P4_S_4: 1;
+        uint32_t PAD_P4_DEB_4: 1;
+        uint32_t PAD_P4_HS_MUX_4: 1;
+        uint32_t RSVD_1: 3;
+        uint32_t PAD_P4_O_EN_4: 1;
+        uint32_t PAD_P4_O_5: 1;
+        uint32_t PAD_P4_E_5: 1;
+        uint32_t PAD_P4_PU_EN_5: 1;
+        uint32_t AON_PAD_P4_PD_5: 1;
+        uint32_t PAD_P4_PUPDC_5: 1;
+        uint32_t PAD_P4_WKEN_5: 1;
+        uint32_t PAD_P4_WKPOL_5: 1;
+        uint32_t PAD_P4_E2_5: 1;
+        uint32_t PAD_P4_SHDN_5: 1;
+        uint32_t PAD_P4_S_5: 1;
+        uint32_t PAD_P4_DEB_5: 1;
+        uint32_t PAD_P4_HS_MUX_5: 1;
+        uint32_t RSVD: 3;
+        uint32_t PAD_P4_O_EN_5: 1;
+    };
+} AON_NS_P4_4_P4_5_PAD_CFG_TYPE;
+
+/* 0x1960   0x4000_1960
+    0       R/W PAD_P4_O[6]                     1'b0
+    1       R/W PAD_P4_E[6]                     1'b0
+    2       R/W PAD_P4_PU_EN[6]                 1'b1
+    3       R/W AON_PAD_P4_PD[6]                1'b1
+    4       R/W PAD_P4_PUPDC[6]                 1'b0
+    5       R/W PAD_P4_WKEN[6]                  1'b0
+    6       R/W PAD_P4_WKPOL[6]                 1'b0
+    7       R/W PAD_P4_E2[6]                    1'b1
+    8       R/W PAD_P4_SHDN[6]                  1'b1
+    9       R/W PAD_P4_S[6]                     1'b0
+    10      R/W PAD_P4_DEB[6]                   1'b0
+    11      R/W PAD_P4_HS_MUX[6]                1'b0
+    14:12   R   RSVD                            3'b0
+    15      R/W PAD_P4_O_EN[6]                  1'h1
+    16      R/W PAD_P4_O[7]                     1'b0
+    17      R/W PAD_P4_E[7]                     1'b0
+    18      R/W PAD_P4_PU_EN[7]                 1'b1
+    19      R/W AON_PAD_P4_PD[7]                1'b1
+    20      R/W PAD_P4_PUPDC[7]                 1'b0
+    21      R/W PAD_P4_WKEN[7]                  1'b0
+    22      R/W PAD_P4_WKPOL[7]                 1'b0
+    23      R/W PAD_P4_E2[7]                    1'b1
+    24      R/W PAD_P4_SHDN[7]                  1'b1
+    25      R/W PAD_P4_S[7]                     1'b0
+    26      R/W PAD_P4_DEB[7]                   1'b0
+    27      R/W PAD_P4_HS_MUX[7]                1'b0
+    30:28   R   RSVD                            3'b0
+    31      R/W PAD_P4_O_EN[7]                  1'h1
+ */
+typedef volatile union _AON_NS_P4_6_P4_7_PAD_CFG_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t PAD_P4_O_6: 1;
+        uint32_t PAD_P4_E_6: 1;
+        uint32_t PAD_P4_PU_EN_6: 1;
+        uint32_t AON_PAD_P4_PD_6: 1;
+        uint32_t PAD_P4_PUPDC_6: 1;
+        uint32_t PAD_P4_WKEN_6: 1;
+        uint32_t PAD_P4_WKPOL_6: 1;
+        uint32_t PAD_P4_E2_6: 1;
+        uint32_t PAD_P4_SHDN_6: 1;
+        uint32_t PAD_P4_S_6: 1;
+        uint32_t PAD_P4_DEB_6: 1;
+        uint32_t PAD_P4_HS_MUX_6: 1;
+        uint32_t RSVD_1: 3;
+        uint32_t PAD_P4_O_EN_6: 1;
+        uint32_t PAD_P4_O_7: 1;
+        uint32_t PAD_P4_E_7: 1;
+        uint32_t PAD_P4_PU_EN_7: 1;
+        uint32_t AON_PAD_P4_PD_7: 1;
+        uint32_t PAD_P4_PUPDC_7: 1;
+        uint32_t PAD_P4_WKEN_7: 1;
+        uint32_t PAD_P4_WKPOL_7: 1;
+        uint32_t PAD_P4_E2_7: 1;
+        uint32_t PAD_P4_SHDN_7: 1;
+        uint32_t PAD_P4_S_7: 1;
+        uint32_t PAD_P4_DEB_7: 1;
+        uint32_t PAD_P4_HS_MUX_7: 1;
+        uint32_t RSVD: 3;
+        uint32_t PAD_P4_O_EN_7: 1;
+    };
+} AON_NS_P4_6_P4_7_PAD_CFG_TYPE;
+
+/* 0x1964   0x4000_1964
+    0       R/W PAD_P5_O[0]                     1'b0
+    1       R/W PAD_P5_E[0]                     1'b0
+    2       R/W PAD_P5_PU_EN[0]                 1'b1
+    3       R/W AON_PAD_P5_PD[0]                1'b1
+    4       R/W PAD_P5_PUPDC[0]                 1'b0
+    5       R/W PAD_P5_WKEN[0]                  1'b0
+    6       R/W PAD_P5_WKPOL[0]                 1'b0
+    7       R/W PAD_P5_E2[0]                    1'b1
+    8       R/W PAD_P5_SHDN[0]                  1'b1
+    9       R/W PAD_P5_S[0]                     1'b0
+    10      R/W PAD_P5_DEB[0]                   1'b0
+    11      R/W PAD_P5_HS_MUX[0]                1'b0
+    14:12   R   RSVD                            3'b0
+    15      R/W PAD_P5_O_EN[0]                  1'h1
+    16      R/W PAD_P5_O[1]                     1'b0
+    17      R/W PAD_P5_E[1]                     1'b0
+    18      R/W PAD_P5_PU_EN[1]                 1'b1
+    19      R/W AON_PAD_P5_PD[1]                1'b1
+    20      R/W PAD_P5_PUPDC[1]                 1'b0
+    21      R/W PAD_P5_WKEN[1]                  1'b0
+    22      R/W PAD_P5_WKPOL[1]                 1'b0
+    23      R/W PAD_P5_E2[1]                    1'b1
+    24      R/W PAD_P5_SHDN[1]                  1'b1
+    25      R/W PAD_P5_S[1]                     1'b0
+    26      R/W PAD_P5_DEB[1]                   1'b0
+    27      R/W PAD_P5_HS_MUX[1]                1'b0
+    30:28   R   RSVD                            3'b0
+    31      R/W PAD_P5_O_EN[1]                  1'h1
+ */
+typedef volatile union _AON_NS_P5_0_P5_1_PAD_CFG_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t PAD_P5_O_0: 1;
+        uint32_t PAD_P5_E_0: 1;
+        uint32_t PAD_P5_PU_EN_0: 1;
+        uint32_t AON_PAD_P5_PD_0: 1;
+        uint32_t PAD_P5_PUPDC_0: 1;
+        uint32_t PAD_P5_WKEN_0: 1;
+        uint32_t PAD_P5_WKPOL_0: 1;
+        uint32_t PAD_P5_E2_0: 1;
+        uint32_t PAD_P5_SHDN_0: 1;
+        uint32_t PAD_P5_S_0: 1;
+        uint32_t PAD_P5_DEB_0: 1;
+        uint32_t PAD_P5_HS_MUX_0: 1;
+        uint32_t RSVD_1: 3;
+        uint32_t PAD_P5_O_EN_0: 1;
+        uint32_t PAD_P5_O_1: 1;
+        uint32_t PAD_P5_E_1: 1;
+        uint32_t PAD_P5_PU_EN_1: 1;
+        uint32_t AON_PAD_P5_PD_1: 1;
+        uint32_t PAD_P5_PUPDC_1: 1;
+        uint32_t PAD_P5_WKEN_1: 1;
+        uint32_t PAD_P5_WKPOL_1: 1;
+        uint32_t PAD_P5_E2_1: 1;
+        uint32_t PAD_P5_SHDN_1: 1;
+        uint32_t PAD_P5_S_1: 1;
+        uint32_t PAD_P5_DEB_1: 1;
+        uint32_t PAD_P5_HS_MUX_1: 1;
+        uint32_t RSVD: 3;
+        uint32_t PAD_P5_O_EN_1: 1;
+    };
+} AON_NS_P5_0_P5_1_PAD_CFG_TYPE;
+
+/* 0x1968   0x4000_1968
+    0       R/W PAD_P5_O[2]                     1'b0
+    1       R/W PAD_P5_E[2]                     1'b0
+    2       R/W PAD_P5_PU_EN[2]                 1'b1
+    3       R/W AON_PAD_P5_PD[2]                1'b0
+    4       R/W PAD_P5_PUPDC[2]                 1'b0
+    5       R/W PAD_P5_WKEN[2]                  1'b0
+    6       R/W PAD_P5_WKPOL[2]                 1'b0
+    7       R/W PAD_P5_E2[2]                    1'b1
+    8       R/W PAD_P5_SHDN[2]                  1'b1
+    9       R/W PAD_P5_S[2]                     1'b0
+    10      R/W PAD_P5_DEB[2]                   1'b0
+    11      R/W PAD_P5_HS_MUX[2]                1'b0
+    14:12   R   RSVD                            3'b0
+    15      R/W PAD_P5_O_EN[2]                  1'h1
+    16      R/W PAD_P5_O[3]                     1'b0
+    17      R/W PAD_P5_E[3]                     1'b0
+    18      R/W PAD_P5_PU_EN[3]                 1'b1
+    19      R/W AON_PAD_P5_PD[3]                1'b1
+    20      R/W PAD_P5_PUPDC[3]                 1'b0
+    21      R/W PAD_P5_WKEN[3]                  1'b0
+    22      R/W PAD_P5_WKPOL[3]                 1'b0
+    23      R/W PAD_P5_E2[3]                    1'b1
+    24      R/W PAD_P5_SHDN[3]                  1'b1
+    25      R/W PAD_P5_S[3]                     1'b0
+    26      R/W PAD_P5_DEB[3]                   1'b0
+    27      R/W PAD_P5_HS_MUX[3]                1'b0
+    30:28   R   RSVD                            3'b0
+    31      R/W PAD_P5_O_EN[3]                  1'h1
+ */
+typedef volatile union _AON_NS_P5_2_P5_3_PAD_CFG_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t PAD_P5_O_2: 1;
+        uint32_t PAD_P5_E_2: 1;
+        uint32_t PAD_P5_PU_EN_2: 1;
+        uint32_t AON_PAD_P5_PD_2: 1;
+        uint32_t PAD_P5_PUPDC_2: 1;
+        uint32_t PAD_P5_WKEN_2: 1;
+        uint32_t PAD_P5_WKPOL_2: 1;
+        uint32_t PAD_P5_E2_2: 1;
+        uint32_t PAD_P5_SHDN_2: 1;
+        uint32_t PAD_P5_S_2: 1;
+        uint32_t PAD_P5_DEB_2: 1;
+        uint32_t PAD_P5_HS_MUX_2: 1;
+        uint32_t RSVD_1: 3;
+        uint32_t PAD_P5_O_EN_2: 1;
+        uint32_t PAD_P5_O_3: 1;
+        uint32_t PAD_P5_E_3: 1;
+        uint32_t PAD_P5_PU_EN_3: 1;
+        uint32_t AON_PAD_P5_PD_3: 1;
+        uint32_t PAD_P5_PUPDC_3: 1;
+        uint32_t PAD_P5_WKEN_3: 1;
+        uint32_t PAD_P5_WKPOL_3: 1;
+        uint32_t PAD_P5_E2_3: 1;
+        uint32_t PAD_P5_SHDN_3: 1;
+        uint32_t PAD_P5_S_3: 1;
+        uint32_t PAD_P5_DEB_3: 1;
+        uint32_t PAD_P5_HS_MUX_3: 1;
+        uint32_t RSVD: 3;
+        uint32_t PAD_P5_O_EN_3: 1;
+    };
+} AON_NS_P5_2_P5_3_PAD_CFG_TYPE;
+
+/* 0x196C   0x4000_196c
+    0       R/W PAD_P5_O[4]                     1'b0
+    1       R/W PAD_P5_E[4]                     1'b0
+    2       R/W PAD_P5_PU_EN[4]                 1'b1
+    3       R/W AON_PAD_P5_PD[4]                1'b1
+    4       R/W PAD_P5_PUPDC[4]                 1'b0
+    5       R/W PAD_P5_WKEN[4]                  1'b0
+    6       R/W PAD_P5_WKPOL[4]                 1'b0
+    7       R/W PAD_P5_E2[4]                    1'b1
+    8       R/W PAD_P5_SHDN[4]                  1'b1
+    9       R/W PAD_P5_S[4]                     1'b0
+    10      R/W PAD_P5_DEB[4]                   1'b0
+    11      R/W PAD_P5_HS_MUX[4]                1'b0
+    14:12   R   RSVD                            3'b0
+    15      R/W PAD_P5_O_EN[4]                  1'h1
+    16      R/W PAD_P5_O[5]                     1'b0
+    17      R/W PAD_P5_E[5]                     1'b0
+    18      R/W PAD_P5_PU_EN[5]                 1'b1
+    19      R/W AON_PAD_P5_PD[5]                1'b1
+    20      R/W PAD_P5_PUPDC[5]                 1'b0
+    21      R/W PAD_P5_WKEN[5]                  1'b0
+    22      R/W PAD_P5_WKPOL[5]                 1'b0
+    23      R/W PAD_P5_E2[5]                    1'b1
+    24      R/W PAD_P5_SHDN[5]                  1'b1
+    25      R/W PAD_P5_S[5]                     1'b0
+    26      R/W PAD_P5_DEB[5]                   1'b0
+    27      R/W PAD_P5_HS_MUX[5]                1'b0
+    30:28   R   RSVD                            3'b0
+    31      R/W PAD_P5_O_EN[5]                  1'h1
+ */
+typedef volatile union _AON_NS_P5_4_P5_5_PAD_CFG_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t PAD_P5_O_4: 1;
+        uint32_t PAD_P5_E_4: 1;
+        uint32_t PAD_P5_PU_EN_4: 1;
+        uint32_t AON_PAD_P5_PD_4: 1;
+        uint32_t PAD_P5_PUPDC_4: 1;
+        uint32_t PAD_P5_WKEN_4: 1;
+        uint32_t PAD_P5_WKPOL_4: 1;
+        uint32_t PAD_P5_E2_4: 1;
+        uint32_t PAD_P5_SHDN_4: 1;
+        uint32_t PAD_P5_S_4: 1;
+        uint32_t PAD_P5_DEB_4: 1;
+        uint32_t PAD_P5_HS_MUX_4: 1;
+        uint32_t RSVD_1: 3;
+        uint32_t PAD_P5_O_EN_4: 1;
+        uint32_t PAD_P5_O_5: 1;
+        uint32_t PAD_P5_E_5: 1;
+        uint32_t PAD_P5_PU_EN_5: 1;
+        uint32_t AON_PAD_P5_PD_5: 1;
+        uint32_t PAD_P5_PUPDC_5: 1;
+        uint32_t PAD_P5_WKEN_5: 1;
+        uint32_t PAD_P5_WKPOL_5: 1;
+        uint32_t PAD_P5_E2_5: 1;
+        uint32_t PAD_P5_SHDN_5: 1;
+        uint32_t PAD_P5_S_5: 1;
+        uint32_t PAD_P5_DEB_5: 1;
+        uint32_t PAD_P5_HS_MUX_5: 1;
+        uint32_t RSVD: 3;
+        uint32_t PAD_P5_O_EN_5: 1;
+    };
+} AON_NS_P5_4_P5_5_PAD_CFG_TYPE;
+
+/* 0x1970   0x4000_1970
+    0       R/W PAD_P5_O[6]                     1'b0
+    1       R/W PAD_P5_E[6]                     1'b0
+    2       R/W PAD_P5_PU_EN[6]                 1'b1
+    3       R/W AON_PAD_P5_PD[6]                1'b1
+    4       R/W PAD_P5_PUPDC[6]                 1'b0
+    5       R/W PAD_P5_WKEN[6]                  1'b0
+    6       R/W PAD_P5_WKPOL[6]                 1'b0
+    7       R/W PAD_P5_E2[6]                    1'b1
+    8       R/W PAD_P5_SHDN[6]                  1'b1
+    9       R/W PAD_P5_S[6]                     1'b0
+    10      R/W PAD_P5_DEB[6]                   1'b0
+    14:11   R   RSVD                            4'b0
+    15      R/W PAD_P5_O_EN[6]                  1'h1
+    16      R/W PAD_P5_O[7]                     1'b0
+    17      R/W PAD_P5_E[7]                     1'b0
+    18      R/W PAD_P5_PU_EN[7]                 1'b1
+    19      R/W AON_PAD_P5_PD[7]                1'b1
+    20      R/W PAD_P5_PUPDC[7]                 1'b0
+    21      R/W PAD_P5_WKEN[7]                  1'b0
+    22      R/W PAD_P5_WKPOL[7]                 1'b0
+    23      R/W PAD_P5_E2[7]                    1'b1
+    24      R/W PAD_P5_SHDN[7]                  1'b1
+    25      R/W PAD_P5_S[7]                     1'b0
+    26      R/W PAD_P5_DEB[7]                   1'b0
+    30:27   R   RSVD                            4'b0
+    31      R/W PAD_P5_O_EN[7]                  1'h1
+ */
+typedef volatile union _AON_NS_P5_6_P5_7_PAD_CFG_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t PAD_P5_O_6: 1;
+        uint32_t PAD_P5_E_6: 1;
+        uint32_t PAD_P5_PU_EN_6: 1;
+        uint32_t AON_PAD_P5_PD_6: 1;
+        uint32_t PAD_P5_PUPDC_6: 1;
+        uint32_t PAD_P5_WKEN_6: 1;
+        uint32_t PAD_P5_WKPOL_6: 1;
+        uint32_t PAD_P5_E2_6: 1;
+        uint32_t PAD_P5_SHDN_6: 1;
+        uint32_t PAD_P5_S_6: 1;
+        uint32_t PAD_P5_DEB_6: 1;
+        uint32_t RSVD_1: 4;
+        uint32_t PAD_P5_O_EN_6: 1;
+        uint32_t PAD_P5_O_7: 1;
+        uint32_t PAD_P5_E_7: 1;
+        uint32_t PAD_P5_PU_EN_7: 1;
+        uint32_t AON_PAD_P5_PD_7: 1;
+        uint32_t PAD_P5_PUPDC_7: 1;
+        uint32_t PAD_P5_WKEN_7: 1;
+        uint32_t PAD_P5_WKPOL_7: 1;
+        uint32_t PAD_P5_E2_7: 1;
+        uint32_t PAD_P5_SHDN_7: 1;
+        uint32_t PAD_P5_S_7: 1;
+        uint32_t PAD_P5_DEB_7: 1;
+        uint32_t RSVD: 4;
+        uint32_t PAD_P5_O_EN_7: 1;
+    };
+} AON_NS_P5_6_P5_7_PAD_CFG_TYPE;
+
+/* 0x1974   0x4000_1974
+    0       R/W PAD_P6_O[0]                     1'b0
+    1       R/W PAD_P6_E[0]                     1'b0
+    2       R/W PAD_P6_PU_EN[0]                 1'b1
+    3       R/W AON_PAD_P6_PD[0]                1'b1
+    4       R/W PAD_P6_PUPDC[0]                 1'b0
+    5       R/W PAD_P6_WKEN[0]                  1'b0
+    6       R/W PAD_P6_WKPOL[0]                 1'b0
+    7       R/W PAD_P6_E2[0]                    1'b1
+    8       R/W PAD_P6_SHDN[0]                  1'b1
+    9       R/W PAD_P6_S[0]                     1'b0
+    10      R/W PAD_P6_DEB[0]                   1'b0
+    11      R/W PAD_P6_HS_MUX[0]                1'b0
+    14:12   R   RSVD                            3'b0
+    15      R/W PAD_P6_O_EN[0]                  1'h1
+    16      R/W PAD_P6_O[1]                     1'b0
+    17      R/W PAD_P6_E[1]                     1'b0
+    18      R/W PAD_P6_PU_EN[1]                 1'b1
+    19      R/W AON_PAD_P6_PD[1]                1'b1
+    20      R/W PAD_P6_PUPDC[1]                 1'b0
+    21      R/W PAD_P6_WKEN[1]                  1'b0
+    22      R/W PAD_P6_WKPOL[1]                 1'b0
+    23      R/W PAD_P6_E2[1]                    1'b1
+    24      R/W PAD_P6_SHDN[1]                  1'b1
+    25      R/W PAD_P6_S[1]                     1'b0
+    26      R/W PAD_P6_DEB[1]                   1'b0
+    27      R/W PAD_P6_HS_MUX[1]                1'b0
+    30:28   R   RSVD                            3'b0
+    31      R/W PAD_P6_O_EN[1]                  1'h1
+ */
+typedef volatile union _AON_NS_P6_0_P6_1_PAD_CFG_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t PAD_P6_O_0: 1;
+        uint32_t PAD_P6_E_0: 1;
+        uint32_t PAD_P6_PU_EN_0: 1;
+        uint32_t AON_PAD_P6_PD_0: 1;
+        uint32_t PAD_P6_PUPDC_0: 1;
+        uint32_t PAD_P6_WKEN_0: 1;
+        uint32_t PAD_P6_WKPOL_0: 1;
+        uint32_t PAD_P6_E2_0: 1;
+        uint32_t PAD_P6_SHDN_0: 1;
+        uint32_t PAD_P6_S_0: 1;
+        uint32_t PAD_P6_DEB_0: 1;
+        uint32_t PAD_P6_HS_MUX_0: 1;
+        uint32_t RSVD_1: 3;
+        uint32_t PAD_P6_O_EN_0: 1;
+        uint32_t PAD_P6_O_1: 1;
+        uint32_t PAD_P6_E_1: 1;
+        uint32_t PAD_P6_PU_EN_1: 1;
+        uint32_t AON_PAD_P6_PD_1: 1;
+        uint32_t PAD_P6_PUPDC_1: 1;
+        uint32_t PAD_P6_WKEN_1: 1;
+        uint32_t PAD_P6_WKPOL_1: 1;
+        uint32_t PAD_P6_E2_1: 1;
+        uint32_t PAD_P6_SHDN_1: 1;
+        uint32_t PAD_P6_S_1: 1;
+        uint32_t PAD_P6_DEB_1: 1;
+        uint32_t PAD_P6_HS_MUX_1: 1;
+        uint32_t RSVD: 3;
+        uint32_t PAD_P6_O_EN_1: 1;
+    };
+} AON_NS_P6_0_P6_1_PAD_CFG_TYPE;
+
+/* 0x1978   0x4000_1978
+    0       R/W PAD_P6_O[2]                     1'b0
+    1       R/W PAD_P6_E[2]                     1'b0
+    2       R/W PAD_P6_PU_EN[2]                 1'b1
+    3       R/W AON_PAD_P6_PD[2]                1'b1
+    4       R/W PAD_P6_PUPDC[2]                 1'b0
+    5       R/W PAD_P6_WKEN[2]                  1'b0
+    6       R/W PAD_P6_WKPOL[2]                 1'b0
+    7       R/W PAD_P6_E2[2]                    1'b1
+    8       R/W PAD_P6_SHDN[2]                  1'b1
+    9       R/W PAD_P6_S[2]                     1'b0
+    10      R/W PAD_P6_DEB[2]                   1'b0
+    11      R/W PAD_P6_HS_MUX[2]                1'b0
+    14:12   R   RSVD                            3'b0
+    15      R/W PAD_P6_O_EN[2]                  1'h1
+    16      R/W PAD_P6_O[3]                     1'b0
+    17      R/W PAD_P6_E[3]                     1'b0
+    18      R/W PAD_P6_PU_EN[3]                 1'b1
+    19      R/W AON_PAD_P6_PD[3]                1'b1
+    20      R/W PAD_P6_PUPDC[3]                 1'b0
+    21      R/W PAD_P6_WKEN[3]                  1'b0
+    22      R/W PAD_P6_WKPOL[3]                 1'b0
+    23      R/W PAD_P6_E2[3]                    1'b1
+    24      R/W PAD_P6_SHDN[3]                  1'b1
+    25      R/W PAD_P6_S[3]                     1'b0
+    26      R/W PAD_P6_DEB[3]                   1'b0
+    27      R/W PAD_P6_HS_MUX[3]                1'b0
+    30:28   R   RSVD                            3'b0
+    31      R/W PAD_P6_O_EN[3]                  1'h1
+ */
+typedef volatile union _AON_NS_P6_2_P6_3_PAD_CFG_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t PAD_P6_O_2: 1;
+        uint32_t PAD_P6_E_2: 1;
+        uint32_t PAD_P6_PU_EN_2: 1;
+        uint32_t AON_PAD_P6_PD_2: 1;
+        uint32_t PAD_P6_PUPDC_2: 1;
+        uint32_t PAD_P6_WKEN_2: 1;
+        uint32_t PAD_P6_WKPOL_2: 1;
+        uint32_t PAD_P6_E2_2: 1;
+        uint32_t PAD_P6_SHDN_2: 1;
+        uint32_t PAD_P6_S_2: 1;
+        uint32_t PAD_P6_DEB_2: 1;
+        uint32_t PAD_P6_HS_MUX_2: 1;
+        uint32_t RSVD_1: 3;
+        uint32_t PAD_P6_O_EN_2: 1;
+        uint32_t PAD_P6_O_3: 1;
+        uint32_t PAD_P6_E_3: 1;
+        uint32_t PAD_P6_PU_EN_3: 1;
+        uint32_t AON_PAD_P6_PD_3: 1;
+        uint32_t PAD_P6_PUPDC_3: 1;
+        uint32_t PAD_P6_WKEN_3: 1;
+        uint32_t PAD_P6_WKPOL_3: 1;
+        uint32_t PAD_P6_E2_3: 1;
+        uint32_t PAD_P6_SHDN_3: 1;
+        uint32_t PAD_P6_S_3: 1;
+        uint32_t PAD_P6_DEB_3: 1;
+        uint32_t PAD_P6_HS_MUX_3: 1;
+        uint32_t RSVD: 3;
+        uint32_t PAD_P6_O_EN_3: 1;
+    };
+} AON_NS_P6_2_P6_3_PAD_CFG_TYPE;
+
+/* 0x197C   0x4000_197c
+    0       R/W PAD_P6_O[4]                     1'b0
+    1       R/W PAD_P6_E[4]                     1'b0
+    2       R/W PAD_P6_PU_EN[4]                 1'b1
+    3       R/W AON_PAD_P6_PD[4]                1'b1
+    4       R/W PAD_P6_PUPDC[4]                 1'b0
+    5       R/W PAD_P6_WKEN[4]                  1'b0
+    6       R/W PAD_P6_WKPOL[4]                 1'b0
+    7       R/W PAD_P6_E2[4]                    1'b1
+    8       R/W PAD_P6_SHDN[4]                  1'b1
+    9       R/W PAD_P6_S[4]                     1'b0
+    10      R/W PAD_P6_DEB[4]                   1'b0
+    11      R/W PAD_P6_HS_MUX[4]                1'b0
+    14:12   R   RSVD                            3'b0
+    15      R/W PAD_P6_O_EN[4]                  1'h1
+    16      R/W PAD_P6_O[5]                     1'b0
+    17      R/W PAD_P6_E[5]                     1'b0
+    18      R/W PAD_P6_PU_EN[5]                 1'b1
+    19      R/W AON_PAD_P6_PD[5]                1'b0
+    20      R/W PAD_P6_PUPDC[5]                 1'b0
+    21      R/W PAD_P6_WKEN[5]                  1'b0
+    22      R/W PAD_P6_WKPOL[5]                 1'b0
+    23      R/W PAD_P6_E2[5]                    1'b1
+    24      R/W PAD_P6_SHDN[5]                  1'b1
+    25      R/W PAD_P6_S[5]                     1'b0
+    26      R/W PAD_P6_DEB[5]                   1'b0
+    27      R/W PAD_P6_HS_MUX[5]                1'b0
+    30:28   R   RSVD                            3'b0
+    31      R/W PAD_P6_O_EN[5]                  1'h1
+ */
+typedef volatile union _AON_NS_P6_4_P6_5_PAD_CFG_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t PAD_P6_O_4: 1;
+        uint32_t PAD_P6_E_4: 1;
+        uint32_t PAD_P6_PU_EN_4: 1;
+        uint32_t AON_PAD_P6_PD_4: 1;
+        uint32_t PAD_P6_PUPDC_4: 1;
+        uint32_t PAD_P6_WKEN_4: 1;
+        uint32_t PAD_P6_WKPOL_4: 1;
+        uint32_t PAD_P6_E2_4: 1;
+        uint32_t PAD_P6_SHDN_4: 1;
+        uint32_t PAD_P6_S_4: 1;
+        uint32_t PAD_P6_DEB_4: 1;
+        uint32_t PAD_P6_HS_MUX_4: 1;
+        uint32_t RSVD_1: 3;
+        uint32_t PAD_P6_O_EN_4: 1;
+        uint32_t PAD_P6_O_5: 1;
+        uint32_t PAD_P6_E_5: 1;
+        uint32_t PAD_P6_PU_EN_5: 1;
+        uint32_t AON_PAD_P6_PD_5: 1;
+        uint32_t PAD_P6_PUPDC_5: 1;
+        uint32_t PAD_P6_WKEN_5: 1;
+        uint32_t PAD_P6_WKPOL_5: 1;
+        uint32_t PAD_P6_E2_5: 1;
+        uint32_t PAD_P6_SHDN_5: 1;
+        uint32_t PAD_P6_S_5: 1;
+        uint32_t PAD_P6_DEB_5: 1;
+        uint32_t PAD_P6_HS_MUX_5: 1;
+        uint32_t RSVD: 3;
+        uint32_t PAD_P6_O_EN_5: 1;
+    };
+} AON_NS_P6_4_P6_5_PAD_CFG_TYPE;
+
+/* 0x1980   0x4000_1980
+    0       R/W PAD_P6_O[6]                     1'b0
+    1       R/W PAD_P6_E[6]                     1'b0
+    2       R/W PAD_P6_PU_EN[6]                 1'b1
+    3       R/W AON_PAD_P6_PD[6]                1'b1
+    4       R/W PAD_P6_PUPDC[6]                 1'b0
+    5       R/W PAD_P6_WKEN[6]                  1'b0
+    6       R/W PAD_P6_WKPOL[6]                 1'b0
+    7       R/W PAD_P6_E2[6]                    1'b1
+    8       R/W PAD_P6_SHDN[6]                  1'b1
+    9       R/W PAD_P6_S[6]                     1'b0
+    10      R/W PAD_P6_DEB[6]                   1'b0
+    11      R/W PAD_P6_HS_MUX[6]                1'b0
+    14:12   R   RSVD                            3'b0
+    15      R/W PAD_P6_O_EN[6]                  1'h1
+    16      R/W PAD_P6_O[7]                     1'b0
+    17      R/W PAD_P6_E[7]                     1'b0
+    18      R/W PAD_P6_PU_EN[7]                 1'b1
+    19      R/W AON_PAD_P6_PD[7]                1'b0
+    20      R/W PAD_P6_PUPDC[7]                 1'b0
+    21      R/W PAD_P6_WKEN[7]                  1'b0
+    22      R/W PAD_P6_WKPOL[7]                 1'b0
+    23      R/W PAD_P6_E2[7]                    1'b1
+    24      R/W PAD_P6_SHDN[7]                  1'b1
+    25      R/W PAD_P6_S[7]                     1'b0
+    26      R/W PAD_P6_DEB[7]                   1'b0
+    27      R/W PAD_P6_HS_MUX[7]                1'b0
+    30:28   R   RSVD                            3'b0
+    31      R/W PAD_P6_O_EN[7]                  1'h1
+ */
+typedef volatile union _AON_NS_P6_6_P6_7_PAD_CFG_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t PAD_P6_O_6: 1;
+        uint32_t PAD_P6_E_6: 1;
+        uint32_t PAD_P6_PU_EN_6: 1;
+        uint32_t AON_PAD_P6_PD_6: 1;
+        uint32_t PAD_P6_PUPDC_6: 1;
+        uint32_t PAD_P6_WKEN_6: 1;
+        uint32_t PAD_P6_WKPOL_6: 1;
+        uint32_t PAD_P6_E2_6: 1;
+        uint32_t PAD_P6_SHDN_6: 1;
+        uint32_t PAD_P6_S_6: 1;
+        uint32_t PAD_P6_DEB_6: 1;
+        uint32_t PAD_P6_HS_MUX_6: 1;
+        uint32_t RSVD_1: 3;
+        uint32_t PAD_P6_O_EN_6: 1;
+        uint32_t PAD_P6_O_7: 1;
+        uint32_t PAD_P6_E_7: 1;
+        uint32_t PAD_P6_PU_EN_7: 1;
+        uint32_t AON_PAD_P6_PD_7: 1;
+        uint32_t PAD_P6_PUPDC_7: 1;
+        uint32_t PAD_P6_WKEN_7: 1;
+        uint32_t PAD_P6_WKPOL_7: 1;
+        uint32_t PAD_P6_E2_7: 1;
+        uint32_t PAD_P6_SHDN_7: 1;
+        uint32_t PAD_P6_S_7: 1;
+        uint32_t PAD_P6_DEB_7: 1;
+        uint32_t PAD_P6_HS_MUX_7: 1;
+        uint32_t RSVD: 3;
+        uint32_t PAD_P6_O_EN_7: 1;
+    };
+} AON_NS_P6_6_P6_7_PAD_CFG_TYPE;
+
+/* 0x1984   0x4000_1984
+    0       R/W PAD_P7_O[0]                     1'b0
+    1       R/W PAD_P7_E[0]                     1'b0
+    2       R/W PAD_P7_PU_EN[0]                 1'b1
+    3       R/W AON_PAD_P7_PD[0]                1'b1
+    4       R/W PAD_P7_PUPDC[0]                 1'b0
+    5       R/W PAD_P7_WKEN[0]                  1'b0
+    6       R/W PAD_P7_WKPOL[0]                 1'b0
+    7       R/W PAD_P7_E2[0]                    1'b1
+    8       R/W PAD_P7_SHDN[0]                  1'b1
+    9       R/W PAD_P7_S[0]                     1'b0
+    10      R/W PAD_P7_DEB[0]                   1'b0
+    11      R/W PAD_P7_HS_MUX[0]                1'b0
+    14:12   R   RSVD                            3'b0
+    15      R/W PAD_P7_O_EN[0]                  1'h1
+    16      R/W PAD_P7_O[1]                     1'b0
+    17      R/W PAD_P7_E[1]                     1'b0
+    18      R/W PAD_P7_PU_EN[1]                 1'b1
+    19      R/W AON_PAD_P7_PD[1]                1'b1
+    20      R/W PAD_P7_PUPDC[1]                 1'b0
+    21      R/W PAD_P7_WKEN[1]                  1'b0
+    22      R/W PAD_P7_WKPOL[1]                 1'b0
+    23      R/W PAD_P7_E2[1]                    1'b1
+    24      R/W PAD_P7_SHDN[1]                  1'b1
+    25      R/W PAD_P7_S[1]                     1'b0
+    26      R/W PAD_P7_DEB[1]                   1'b0
+    27      R/W PAD_P7_HS_MUX[1]                1'b0
+    30:28   R   RSVD                            3'b0
+    31      R/W PAD_P7_O_EN[1]                  1'h1
+ */
+typedef volatile union _AON_NS_P7_0_P7_1_PAD_CFG_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t PAD_P7_O_0: 1;
+        uint32_t PAD_P7_E_0: 1;
+        uint32_t PAD_P7_PU_EN_0: 1;
+        uint32_t AON_PAD_P7_PD_0: 1;
+        uint32_t PAD_P7_PUPDC_0: 1;
+        uint32_t PAD_P7_WKEN_0: 1;
+        uint32_t PAD_P7_WKPOL_0: 1;
+        uint32_t PAD_P7_E2_0: 1;
+        uint32_t PAD_P7_SHDN_0: 1;
+        uint32_t PAD_P7_S_0: 1;
+        uint32_t PAD_P7_DEB_0: 1;
+        uint32_t PAD_P7_HS_MUX_0: 1;
+        uint32_t RSVD_1: 3;
+        uint32_t PAD_P7_O_EN_0: 1;
+        uint32_t PAD_P7_O_1: 1;
+        uint32_t PAD_P7_E_1: 1;
+        uint32_t PAD_P7_PU_EN_1: 1;
+        uint32_t AON_PAD_P7_PD_1: 1;
+        uint32_t PAD_P7_PUPDC_1: 1;
+        uint32_t PAD_P7_WKEN_1: 1;
+        uint32_t PAD_P7_WKPOL_1: 1;
+        uint32_t PAD_P7_E2_1: 1;
+        uint32_t PAD_P7_SHDN_1: 1;
+        uint32_t PAD_P7_S_1: 1;
+        uint32_t PAD_P7_DEB_1: 1;
+        uint32_t PAD_P7_HS_MUX_1: 1;
+        uint32_t RSVD: 3;
+        uint32_t PAD_P7_O_EN_1: 1;
+    };
+} AON_NS_P7_0_P7_1_PAD_CFG_TYPE;
+
+/* 0x1988   0x4000_1988
+    0       R/W PAD_P7_O[2]                     1'b0
+    1       R/W PAD_P7_E[2]                     1'b0
+    2       R/W PAD_P7_PU_EN[2]                 1'b1
+    3       R/W AON_PAD_P7_PD[2]                1'b1
+    4       R/W PAD_P7_PUPDC[2]                 1'b0
+    5       R/W PAD_P7_WKEN[2]                  1'b0
+    6       R/W PAD_P7_WKPOL[2]                 1'b0
+    7       R/W PAD_P7_E2[2]                    1'b1
+    8       R/W PAD_P7_SHDN[2]                  1'b1
+    9       R/W PAD_P7_S[2]                     1'b0
+    10      R/W PAD_P7_DEB[2]                   1'b0
+    11      R/W PAD_P7_HS_MUX[2]                1'b0
+    14:12   R   RSVD                            3'b0
+    15      R/W PAD_P7_O_EN[2]                  1'h1
+    16      R/W PAD_P7_O[3]                     1'b0
+    17      R/W PAD_P7_E[3]                     1'b0
+    18      R/W PAD_P7_PU_EN[3]                 1'b1
+    19      R/W AON_PAD_P7_PD[3]                1'b1
+    20      R/W PAD_P7_PUPDC[3]                 1'b0
+    21      R/W PAD_P7_WKEN[3]                  1'b0
+    22      R/W PAD_P7_WKPOL[3]                 1'b0
+    23      R/W PAD_P7_E2[3]                    1'b1
+    24      R/W PAD_P7_SHDN[3]                  1'b1
+    25      R/W PAD_P7_S[3]                     1'b0
+    26      R/W PAD_P7_DEB[3]                   1'b0
+    27      R/W PAD_P7_HS_MUX[3]                1'b0
+    30:28   R   RSVD                            3'b0
+    31      R/W PAD_P7_O_EN[3]                  1'h1
+ */
+typedef volatile union _AON_NS_P7_2_P7_3_PAD_CFG_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t PAD_P7_O_2: 1;
+        uint32_t PAD_P7_E_2: 1;
+        uint32_t PAD_P7_PU_EN_2: 1;
+        uint32_t AON_PAD_P7_PD_2: 1;
+        uint32_t PAD_P7_PUPDC_2: 1;
+        uint32_t PAD_P7_WKEN_2: 1;
+        uint32_t PAD_P7_WKPOL_2: 1;
+        uint32_t PAD_P7_E2_2: 1;
+        uint32_t PAD_P7_SHDN_2: 1;
+        uint32_t PAD_P7_S_2: 1;
+        uint32_t PAD_P7_DEB_2: 1;
+        uint32_t PAD_P7_HS_MUX_2: 1;
+        uint32_t RSVD_1: 3;
+        uint32_t PAD_P7_O_EN_2: 1;
+        uint32_t PAD_P7_O_3: 1;
+        uint32_t PAD_P7_E_3: 1;
+        uint32_t PAD_P7_PU_EN_3: 1;
+        uint32_t AON_PAD_P7_PD_3: 1;
+        uint32_t PAD_P7_PUPDC_3: 1;
+        uint32_t PAD_P7_WKEN_3: 1;
+        uint32_t PAD_P7_WKPOL_3: 1;
+        uint32_t PAD_P7_E2_3: 1;
+        uint32_t PAD_P7_SHDN_3: 1;
+        uint32_t PAD_P7_S_3: 1;
+        uint32_t PAD_P7_DEB_3: 1;
+        uint32_t PAD_P7_HS_MUX_3: 1;
+        uint32_t RSVD: 3;
+        uint32_t PAD_P7_O_EN_3: 1;
+    };
+} AON_NS_P7_2_P7_3_PAD_CFG_TYPE;
+
+/* 0x198C   0x4000_198c
+    0       R/W PAD_P7_O[4]                     1'b0
+    1       R/W PAD_P7_E[4]                     1'b0
+    2       R/W PAD_P7_PU_EN[4]                 1'b1
+    3       R/W AON_PAD_P7_PD[4]                1'b1
+    4       R/W PAD_P7_PUPDC[4]                 1'b0
+    5       R/W PAD_P7_WKEN[4]                  1'b0
+    6       R/W PAD_P7_WKPOL[4]                 1'b0
+    7       R/W PAD_P7_E2[4]                    1'b1
+    8       R/W PAD_P7_SHDN[4]                  1'b1
+    9       R/W PAD_P7_S[4]                     1'b0
+    10      R/W PAD_P7_DEB[4]                   1'b0
+    11      R/W PAD_P7_HS_MUX[4]                1'b0
+    14:12   R   RSVD                            3'b0
+    15      R/W PAD_P7_O_EN[4]                  1'h1
+    16      R   RSVD                            1'b0
+    17      R   RSVD                            1'b0
+    18      R   RSVD                            1'b1
+    19      R   RSVD                            1'b0
+    20      R   RSVD                            1'b0
+    21      R   RSVD                            1'b0
+    22      R   RSVD                            1'b0
+    23      R   RSVD                            1'b0
+    24      R   RSVD                            1'b1
+    25      R   RSVD                            1'b0
+    26      R   RSVD                            1'b0
+    31:27   R   RSVD                            5'b0
+ */
+typedef volatile union _AON_NS_P7_4_P7_5_PAD_CFG_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t PAD_P7_O_4: 1;
+        uint32_t PAD_P7_E_4: 1;
+        uint32_t PAD_P7_PU_EN_4: 1;
+        uint32_t AON_PAD_P7_PD_4: 1;
+        uint32_t PAD_P7_PUPDC_4: 1;
+        uint32_t PAD_P7_WKEN_4: 1;
+        uint32_t PAD_P7_WKPOL_4: 1;
+        uint32_t PAD_P7_E2_4: 1;
+        uint32_t PAD_P7_SHDN_4: 1;
+        uint32_t PAD_P7_S_4: 1;
+        uint32_t PAD_P7_DEB_4: 1;
+        uint32_t PAD_P7_HS_MUX_4: 1;
+        uint32_t RSVD_12: 3;
+        uint32_t PAD_P7_O_EN_4: 1;
+        uint32_t RSVD_11: 1;
+        uint32_t RSVD_10: 1;
+        uint32_t RSVD_9: 1;
+        uint32_t RSVD_8: 1;
+        uint32_t RSVD_7: 1;
+        uint32_t RSVD_6: 1;
+        uint32_t RSVD_5: 1;
+        uint32_t RSVD_4: 1;
+        uint32_t RSVD_3: 1;
+        uint32_t RSVD_2: 1;
+        uint32_t RSVD_1: 1;
+        uint32_t RSVD: 5;
+    };
+} AON_NS_P7_4_P7_5_PAD_CFG_TYPE;
+
+/* 0x1990   0x4000_1990
+    31:0    R   RSVD                            32'b0
+ */
+typedef volatile union _AON_NS_P7_6_P7_7_PAD_CFG_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RSVD;
+    };
+} AON_NS_P7_6_P7_7_PAD_CFG_TYPE;
+
+/* 0x1994   0x4000_1994
+    0       R/W PAD_SPI_SCK_O                   1'b0
+    1       R/W PAD_SPI_SCK_E                   1'b0
+    2       R/W PAD_SPI_SCK_PU_EN               1'b1
+    3       R/W AON_PAD_SPI_SCK_PD              1'b0
+    4       R/W PAD_SPI_SCK_PUPDC               1'b0
+    5       R   RSVD                            1'b0
+    6       R   RSVD                            1'b0
+    7       R/W PAD_SPI_SCK_E2                  1'b1
+    8       R/W PAD_SPI_SCK_SHDN                1'b1
+    9       R   RSVD                            1'b0
+    10      R   RSVD                            1'b0
+    11      R/W PAD_SPI_SCK_HS_MUX              1'b0
+    15:12   R   RSVD                            4'b0
+    16      R/W PAD_SPI_CSN_O                   1'b0
+    17      R/W PAD_SPI_CSN_E                   1'b0
+    18      R/W PAD_SPI_CSN_PU_EN               1'b1
+    19      R/W AON_PAD_SPI_CSN_PD              1'b0
+    20      R/W PAD_SPI_CSN_PUPDC               1'b0
+    21      R   RSVD                            1'b0
+    22      R   RSVD                            1'b0
+    23      R/W PAD_SPI_CSN_E2                  1'b1
+    24      R/W PAD_SPI_CSN_SHDN                1'b1
+    25      R   RSVD                            1'b0
+    26      R   RSVD                            1'b0
+    27      R/W PAD_SPI_CSN_HS_MUX              1'b0
+    31:28   R   RSVD                            4'b0
+ */
+typedef volatile union _AON_NS_SPIC0_PAD_CFG0_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t PAD_SPI_SCK_O: 1;
+        uint32_t PAD_SPI_SCK_E: 1;
+        uint32_t PAD_SPI_SCK_PU_EN: 1;
+        uint32_t AON_PAD_SPI_SCK_PD: 1;
+        uint32_t PAD_SPI_SCK_PUPDC: 1;
+        uint32_t RSVD_9: 1;
+        uint32_t RSVD_8: 1;
+        uint32_t PAD_SPI_SCK_E2: 1;
+        uint32_t PAD_SPI_SCK_SHDN: 1;
+        uint32_t RSVD_7: 1;
+        uint32_t RSVD_6: 1;
+        uint32_t PAD_SPI_SCK_HS_MUX: 1;
+        uint32_t RSVD_5: 4;
+        uint32_t PAD_SPI_CSN_O: 1;
+        uint32_t PAD_SPI_CSN_E: 1;
+        uint32_t PAD_SPI_CSN_PU_EN: 1;
+        uint32_t AON_PAD_SPI_CSN_PD: 1;
+        uint32_t PAD_SPI_CSN_PUPDC: 1;
+        uint32_t RSVD_4: 1;
+        uint32_t RSVD_3: 1;
+        uint32_t PAD_SPI_CSN_E2: 1;
+        uint32_t PAD_SPI_CSN_SHDN: 1;
+        uint32_t RSVD_2: 1;
+        uint32_t RSVD_1: 1;
+        uint32_t PAD_SPI_CSN_HS_MUX: 1;
+        uint32_t RSVD: 4;
+    };
+} AON_NS_SPIC0_PAD_CFG0_TYPE;
+
+/* 0x1998   0x4000_1998
+    0       R/W PAD_SPI_SIO0_O                  1'b0
+    1       R/W PAD_SPI_SIO0_E                  1'b0
+    2       R/W PAD_SPI_SIO0_PU_EN              1'b1
+    3       R/W AON_PAD_SPI_SIO0_PD             1'b1
+    4       R/W PAD_SPI_SIO0_PUPDC              1'b0
+    5       R   RSVD                            1'b0
+    6       R   RSVD                            1'b0
+    7       R/W PAD_SPI_SIO0_E2                 1'b1
+    8       R/W PAD_SPI_SIO0_SHDN               1'b1
+    9       R   RSVD                            1'b0
+    10      R   RSVD                            1'b0
+    11      R/W PAD_SPI_SIO0_HS_MUX             1'b0
+    15:12   R   RSVD                            4'b0
+    16      R/W PAD_SPI_SIO1_O                  1'b0
+    17      R/W PAD_SPI_SIO1_E                  1'b0
+    18      R/W PAD_SPI_SIO1_PU_EN              1'b1
+    19      R/W AON_PAD_SPI_SIO1_PD             1'b1
+    20      R/W PAD_SPI_SIO1_PUPDC              1'b0
+    21      R   RSVD                            1'b0
+    22      R   RSVD                            1'b0
+    23      R/W PAD_SPI_SIO1_E2                 1'b1
+    24      R/W PAD_SPI_SIO1_SHDN               1'b1
+    25      R   RSVD                            1'b0
+    26      R   RSVD                            1'b0
+    27      R/W PAD_SPI_SIO1_HS_MUX             1'b0
+    31:28   R   RSVD                            4'b0
+ */
+typedef volatile union _AON_NS_SPIC0_PAD_CFG1_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t PAD_SPI_SIO0_O: 1;
+        uint32_t PAD_SPI_SIO0_E: 1;
+        uint32_t PAD_SPI_SIO0_PU_EN: 1;
+        uint32_t AON_PAD_SPI_SIO0_PD: 1;
+        uint32_t PAD_SPI_SIO0_PUPDC: 1;
+        uint32_t RSVD_9: 1;
+        uint32_t RSVD_8: 1;
+        uint32_t PAD_SPI_SIO0_E2: 1;
+        uint32_t PAD_SPI_SIO0_SHDN: 1;
+        uint32_t RSVD_7: 1;
+        uint32_t RSVD_6: 1;
+        uint32_t PAD_SPI_SIO0_HS_MUX: 1;
+        uint32_t RSVD_5: 4;
+        uint32_t PAD_SPI_SIO1_O: 1;
+        uint32_t PAD_SPI_SIO1_E: 1;
+        uint32_t PAD_SPI_SIO1_PU_EN: 1;
+        uint32_t AON_PAD_SPI_SIO1_PD: 1;
+        uint32_t PAD_SPI_SIO1_PUPDC: 1;
+        uint32_t RSVD_4: 1;
+        uint32_t RSVD_3: 1;
+        uint32_t PAD_SPI_SIO1_E2: 1;
+        uint32_t PAD_SPI_SIO1_SHDN: 1;
+        uint32_t RSVD_2: 1;
+        uint32_t RSVD_1: 1;
+        uint32_t PAD_SPI_SIO1_HS_MUX: 1;
+        uint32_t RSVD: 4;
+    };
+} AON_NS_SPIC0_PAD_CFG1_TYPE;
+
+/* 0x199C   0x4000_199c
+    0       R/W PAD_SPI_SIO2_O                  1'b0
+    1       R/W PAD_SPI_SIO2_E                  1'b0
+    2       R/W PAD_SPI_SIO2_PU_EN              1'b1
+    3       R/W AON_PAD_SPI_SIO2_PD             1'b1
+    4       R/W PAD_SPI_SIO2_PUPDC              1'b0
+    5       R   RSVD                            1'b0
+    6       R   RSVD                            1'b0
+    7       R/W PAD_SPI_SIO2_E2                 1'b1
+    8       R/W PAD_SPI_SIO2_SHDN               1'b1
+    9       R   RSVD                            1'b0
+    10      R   RSVD                            1'b0
+    11      R/W PAD_SPI_SIO2_HS_MUX             1'b0
+    15:12   R   RSVD                            4'b0
+    16      R/W PAD_SPI_SIO3_O                  1'b0
+    17      R/W PAD_SPI_SIO3_E                  1'b0
+    18      R/W PAD_SPI_SIO3_PU_EN              1'b1
+    19      R/W AON_PAD_SPI_SIO3_PD             1'b1
+    20      R/W PAD_SPI_SIO3_PUPDC              1'b0
+    21      R   RSVD                            1'b0
+    22      R   RSVD                            1'b0
+    23      R/W PAD_SPI_SIO3_E2                 1'b1
+    24      R/W PAD_SPI_SIO3_SHDN               1'b1
+    25      R   RSVD                            1'b0
+    26      R   RSVD                            1'b0
+    27      R/W PAD_SPI_SIO3_HS_MUX             1'b0
+    31:28   R   RSVD                            4'b0
+ */
+typedef volatile union _AON_NS_SPIC0_PAD_CFG2_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t PAD_SPI_SIO2_O: 1;
+        uint32_t PAD_SPI_SIO2_E: 1;
+        uint32_t PAD_SPI_SIO2_PU_EN: 1;
+        uint32_t AON_PAD_SPI_SIO2_PD: 1;
+        uint32_t PAD_SPI_SIO2_PUPDC: 1;
+        uint32_t RSVD_9: 1;
+        uint32_t RSVD_8: 1;
+        uint32_t PAD_SPI_SIO2_E2: 1;
+        uint32_t PAD_SPI_SIO2_SHDN: 1;
+        uint32_t RSVD_7: 1;
+        uint32_t RSVD_6: 1;
+        uint32_t PAD_SPI_SIO2_HS_MUX: 1;
+        uint32_t RSVD_5: 4;
+        uint32_t PAD_SPI_SIO3_O: 1;
+        uint32_t PAD_SPI_SIO3_E: 1;
+        uint32_t PAD_SPI_SIO3_PU_EN: 1;
+        uint32_t AON_PAD_SPI_SIO3_PD: 1;
+        uint32_t PAD_SPI_SIO3_PUPDC: 1;
+        uint32_t RSVD_4: 1;
+        uint32_t RSVD_3: 1;
+        uint32_t PAD_SPI_SIO3_E2: 1;
+        uint32_t PAD_SPI_SIO3_SHDN: 1;
+        uint32_t RSVD_2: 1;
+        uint32_t RSVD_1: 1;
+        uint32_t PAD_SPI_SIO3_HS_MUX: 1;
+        uint32_t RSVD: 4;
+    };
+} AON_NS_SPIC0_PAD_CFG2_TYPE;
+
+/* 0x19A0   0x4000_19a0
+    31:0    R   RSVD                            32'b0
+ */
+typedef volatile union _AON_NS_P8_0_P8_1_PAD_CFG_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RSVD;
+    };
+} AON_NS_P8_0_P8_1_PAD_CFG_TYPE;
+
+/* 0x19A4   0x4000_19a4
+    31:0    R   RSVD                            32'b0
+ */
+typedef volatile union _AON_NS_P8_2_P8_3_PAD_CFG_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RSVD;
+    };
+} AON_NS_P8_2_P8_3_PAD_CFG_TYPE;
+
+/* 0x19A8   0x4000_19a8
+    31:0    R   RSVD                            32'b0
+ */
+typedef volatile union _AON_NS_P8_4_P8_5_PAD_CFG_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RSVD;
+    };
+} AON_NS_P8_4_P8_5_PAD_CFG_TYPE;
+
+/* 0x19AC   0x4000_19ac
+    31:0    R   RSVD                            32'b0
+ */
+typedef volatile union _AON_NS_P8_6_P8_7_PAD_CFG_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RSVD;
+    };
+} AON_NS_P8_6_P8_7_PAD_CFG_TYPE;
+
+/* 0x19B0   0x4000_19b0
+    0       R/W PAD_P9_O[0]                     1'b0
+    1       R/W PAD_P9_E[0]                     1'b0
+    2       R/W PAD_P9_PU_EN[0]                 1'b1
+    3       R/W AON_PAD_P9_PD[0]                1'b1
+    4       R/W PAD_P9_PUPDC[0]                 1'b0
+    5       R/W PAD_P9_WKEN[0]                  1'b0
+    6       R/W PAD_P9_WKPOL[0]                 1'b0
+    7       R/W PAD_P9_E2[0]                    1'b1
+    8       R/W PAD_P9_SHDN[0]                  1'b1
+    9       R/W PAD_P9_S[0]                     1'b0
+    10      R/W PAD_P9_DEB[0]                   1'b0
+    11      R/W PAD_P9_HS_MUX[0]                1'b0
+    14:12   R   RSVD                            3'b0
+    15      R/W PAD_P9_O_EN[0]                  1'h1
+    16      R/W PAD_P9_O[1]                     1'b0
+    17      R/W PAD_P9_E[1]                     1'b0
+    18      R/W PAD_P9_PU_EN[1]                 1'b1
+    19      R/W AON_PAD_P9_PD[1]                1'b1
+    20      R/W PAD_P9_PUPDC[1]                 1'b0
+    21      R/W PAD_P9_WKEN[1]                  1'b0
+    22      R/W PAD_P9_WKPOL[1]                 1'b0
+    23      R/W PAD_P9_E2[1]                    1'b1
+    24      R/W PAD_P9_SHDN[1]                  1'b1
+    25      R/W PAD_P9_S[1]                     1'b0
+    26      R/W PAD_P9_DEB[1]                   1'b0
+    27      R/W PAD_P9_HS_MUX[1]                1'b0
+    30:28   R   RSVD                            3'b0
+    31      R/W PAD_P9_O_EN[1]                  1'h1
+ */
+typedef volatile union _AON_NS_P9_0_P9_1_PAD_CFG_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t PAD_P9_O_0: 1;
+        uint32_t PAD_P9_E_0: 1;
+        uint32_t PAD_P9_PU_EN_0: 1;
+        uint32_t AON_PAD_P9_PD_0: 1;
+        uint32_t PAD_P9_PUPDC_0: 1;
+        uint32_t PAD_P9_WKEN_0: 1;
+        uint32_t PAD_P9_WKPOL_0: 1;
+        uint32_t PAD_P9_E2_0: 1;
+        uint32_t PAD_P9_SHDN_0: 1;
+        uint32_t PAD_P9_S_0: 1;
+        uint32_t PAD_P9_DEB_0: 1;
+        uint32_t PAD_P9_HS_MUX_0: 1;
+        uint32_t RSVD_1: 3;
+        uint32_t PAD_P9_O_EN_0: 1;
+        uint32_t PAD_P9_O_1: 1;
+        uint32_t PAD_P9_E_1: 1;
+        uint32_t PAD_P9_PU_EN_1: 1;
+        uint32_t AON_PAD_P9_PD_1: 1;
+        uint32_t PAD_P9_PUPDC_1: 1;
+        uint32_t PAD_P9_WKEN_1: 1;
+        uint32_t PAD_P9_WKPOL_1: 1;
+        uint32_t PAD_P9_E2_1: 1;
+        uint32_t PAD_P9_SHDN_1: 1;
+        uint32_t PAD_P9_S_1: 1;
+        uint32_t PAD_P9_DEB_1: 1;
+        uint32_t PAD_P9_HS_MUX_1: 1;
+        uint32_t RSVD: 3;
+        uint32_t PAD_P9_O_EN_1: 1;
+    };
+} AON_NS_P9_0_P9_1_PAD_CFG_TYPE;
+
+/* 0x19B4   0x4000_19b4
+    0       R/W PAD_P9_O[2]                     1'b0
+    1       R/W PAD_P9_E[2]                     1'b0
+    2       R/W PAD_P9_PU_EN[2]                 1'b1
+    3       R/W AON_PAD_P9_PD[2]                1'b1
+    4       R/W PAD_P9_PUPDC[2]                 1'b0
+    5       R/W PAD_P9_WKEN[2]                  1'b0
+    6       R/W PAD_P9_WKPOL[2]                 1'b0
+    7       R/W PAD_P9_E2[2]                    1'b1
+    8       R/W PAD_P9_SHDN[2]                  1'b1
+    9       R/W PAD_P9_S[2]                     1'b0
+    10      R/W PAD_P9_DEB[2]                   1'b0
+    11      R/W PAD_P9_HS_MUX[2]                1'b0
+    14:12   R   RSVD                            3'b0
+    15      R/W PAD_P9_O_EN[2]                  1'h1
+    16      R/W PAD_P9_O[3]                     1'b0
+    17      R/W PAD_P9_E[3]                     1'b0
+    18      R/W PAD_P9_PU_EN[3]                 1'b1
+    19      R/W AON_PAD_P9_PD[3]                1'b0
+    20      R/W PAD_P9_PUPDC[3]                 1'b0
+    21      R/W PAD_P9_WKEN[3]                  1'b0
+    22      R/W PAD_P9_WKPOL[3]                 1'b0
+    23      R/W PAD_P9_E2[3]                    1'b1
+    24      R/W PAD_P9_SHDN[3]                  1'b1
+    25      R/W PAD_P9_S[3]                     1'b0
+    26      R/W PAD_P9_DEB[3]                   1'b0
+    27      R/W PAD_P9_HS_MUX[3]                1'b0
+    30:28   R   RSVD                            3'b0
+    31      R/W PAD_P9_O_EN[3]                  1'h1
+ */
+typedef volatile union _AON_NS_P9_2_P9_3_PAD_CFG_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t PAD_P9_O_2: 1;
+        uint32_t PAD_P9_E_2: 1;
+        uint32_t PAD_P9_PU_EN_2: 1;
+        uint32_t AON_PAD_P9_PD_2: 1;
+        uint32_t PAD_P9_PUPDC_2: 1;
+        uint32_t PAD_P9_WKEN_2: 1;
+        uint32_t PAD_P9_WKPOL_2: 1;
+        uint32_t PAD_P9_E2_2: 1;
+        uint32_t PAD_P9_SHDN_2: 1;
+        uint32_t PAD_P9_S_2: 1;
+        uint32_t PAD_P9_DEB_2: 1;
+        uint32_t PAD_P9_HS_MUX_2: 1;
+        uint32_t RSVD_1: 3;
+        uint32_t PAD_P9_O_EN_2: 1;
+        uint32_t PAD_P9_O_3: 1;
+        uint32_t PAD_P9_E_3: 1;
+        uint32_t PAD_P9_PU_EN_3: 1;
+        uint32_t AON_PAD_P9_PD_3: 1;
+        uint32_t PAD_P9_PUPDC_3: 1;
+        uint32_t PAD_P9_WKEN_3: 1;
+        uint32_t PAD_P9_WKPOL_3: 1;
+        uint32_t PAD_P9_E2_3: 1;
+        uint32_t PAD_P9_SHDN_3: 1;
+        uint32_t PAD_P9_S_3: 1;
+        uint32_t PAD_P9_DEB_3: 1;
+        uint32_t PAD_P9_HS_MUX_3: 1;
+        uint32_t RSVD: 3;
+        uint32_t PAD_P9_O_EN_3: 1;
+    };
+} AON_NS_P9_2_P9_3_PAD_CFG_TYPE;
+
+/* 0x19B8   0x4000_19b8
+    0       R/W PAD_P9_O[4]                     1'b0
+    1       R/W PAD_P9_E[4]                     1'b0
+    2       R/W PAD_P9_PU_EN[4]                 1'b1
+    3       R/W AON_PAD_P9_PD[4]                1'b0
+    4       R/W PAD_P9_PUPDC[4]                 1'b0
+    5       R/W PAD_P9_WKEN[4]                  1'b0
+    6       R/W PAD_P9_WKPOL[4]                 1'b0
+    7       R/W PAD_P9_E2[4]                    1'b1
+    8       R/W PAD_P9_SHDN[4]                  1'b1
+    9       R/W PAD_P9_S[4]                     1'b0
+    10      R/W PAD_P9_DEB[4]                   1'b0
+    11      R/W PAD_P9_HS_MUX[4]                1'b0
+    14:12   R   RSVD                            3'b0
+    15      R/W PAD_P9_O_EN[4]                  1'h1
+    16      R/W PAD_P9_O[5]                     1'b0
+    17      R/W PAD_P9_E[5]                     1'b0
+    18      R/W PAD_P9_PU_EN[5]                 1'b1
+    19      R/W AON_PAD_P9_PD[5]                1'b1
+    20      R/W PAD_P9_PUPDC[5]                 1'b0
+    21      R/W PAD_P9_WKEN[5]                  1'b0
+    22      R/W PAD_P9_WKPOL[5]                 1'b0
+    23      R/W PAD_P9_E2[5]                    1'b1
+    24      R/W PAD_P9_SHDN[5]                  1'b1
+    25      R/W PAD_P9_S[5]                     1'b0
+    26      R/W PAD_P9_DEB[5]                   1'b0
+    27      R/W PAD_P9_HS_MUX[5]                1'b0
+    30:28   R   RSVD                            3'b0
+    31      R/W PAD_P9_O_EN[5]                  1'h1
+ */
+typedef volatile union _AON_NS_P9_4_P9_5_PAD_CFG_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t PAD_P9_O_4: 1;
+        uint32_t PAD_P9_E_4: 1;
+        uint32_t PAD_P9_PU_EN_4: 1;
+        uint32_t AON_PAD_P9_PD_4: 1;
+        uint32_t PAD_P9_PUPDC_4: 1;
+        uint32_t PAD_P9_WKEN_4: 1;
+        uint32_t PAD_P9_WKPOL_4: 1;
+        uint32_t PAD_P9_E2_4: 1;
+        uint32_t PAD_P9_SHDN_4: 1;
+        uint32_t PAD_P9_S_4: 1;
+        uint32_t PAD_P9_DEB_4: 1;
+        uint32_t PAD_P9_HS_MUX_4: 1;
+        uint32_t RSVD_1: 3;
+        uint32_t PAD_P9_O_EN_4: 1;
+        uint32_t PAD_P9_O_5: 1;
+        uint32_t PAD_P9_E_5: 1;
+        uint32_t PAD_P9_PU_EN_5: 1;
+        uint32_t AON_PAD_P9_PD_5: 1;
+        uint32_t PAD_P9_PUPDC_5: 1;
+        uint32_t PAD_P9_WKEN_5: 1;
+        uint32_t PAD_P9_WKPOL_5: 1;
+        uint32_t PAD_P9_E2_5: 1;
+        uint32_t PAD_P9_SHDN_5: 1;
+        uint32_t PAD_P9_S_5: 1;
+        uint32_t PAD_P9_DEB_5: 1;
+        uint32_t PAD_P9_HS_MUX_5: 1;
+        uint32_t RSVD: 3;
+        uint32_t PAD_P9_O_EN_5: 1;
+    };
+} AON_NS_P9_4_P9_5_PAD_CFG_TYPE;
+
+/* 0x19BC   0x4000_19bc
+    0       R/W PAD_P9_O[6]                     1'b0
+    1       R/W PAD_P9_E[6]                     1'b0
+    2       R/W PAD_P9_PU_EN[6]                 1'b1
+    3       R/W AON_PAD_P9_PD[6]                1'b1
+    4       R/W PAD_P9_PUPDC[6]                 1'b0
+    5       R/W PAD_P9_WKEN[6]                  1'b0
+    6       R/W PAD_P9_WKPOL[6]                 1'b0
+    7       R/W PAD_P9_E2[6]                    1'b1
+    8       R/W PAD_P9_SHDN[6]                  1'b1
+    9       R/W PAD_P9_S[6]                     1'b0
+    10      R/W PAD_P9_DEB[6]                   1'b0
+    11      R/W PAD_P9_HS_MUX[6]                1'b0
+    14:12   R   RSVD                            3'b0
+    15      R/W PAD_P9_O_EN[6]                  1'h1
+    16      R/W PAD_P9_O[7]                     1'b0
+    17      R/W PAD_P9_E[7]                     1'b0
+    18      R/W PAD_P9_PU_EN[7]                 1'b1
+    19      R/W AON_PAD_P9_PD[7]                1'b1
+    20      R/W PAD_P9_PUPDC[7]                 1'b0
+    21      R/W PAD_P9_WKEN[7]                  1'b0
+    22      R/W PAD_P9_WKPOL[7]                 1'b0
+    23      R/W PAD_P9_E2[7]                    1'b1
+    24      R/W PAD_P9_SHDN[7]                  1'b1
+    25      R/W PAD_P9_S[7]                     1'b0
+    26      R/W PAD_P9_DEB[7]                   1'b0
+    27      R/W PAD_P9_HS_MUX[7]                1'b0
+    30:28   R   RSVD                            3'b0
+    31      R/W PAD_P9_O_EN[7]                  1'h1
+ */
+typedef volatile union _AON_NS_P9_6_P9_7_PAD_CFG_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t PAD_P9_O_6: 1;
+        uint32_t PAD_P9_E_6: 1;
+        uint32_t PAD_P9_PU_EN_6: 1;
+        uint32_t AON_PAD_P9_PD_6: 1;
+        uint32_t PAD_P9_PUPDC_6: 1;
+        uint32_t PAD_P9_WKEN_6: 1;
+        uint32_t PAD_P9_WKPOL_6: 1;
+        uint32_t PAD_P9_E2_6: 1;
+        uint32_t PAD_P9_SHDN_6: 1;
+        uint32_t PAD_P9_S_6: 1;
+        uint32_t PAD_P9_DEB_6: 1;
+        uint32_t PAD_P9_HS_MUX_6: 1;
+        uint32_t RSVD_1: 3;
+        uint32_t PAD_P9_O_EN_6: 1;
+        uint32_t PAD_P9_O_7: 1;
+        uint32_t PAD_P9_E_7: 1;
+        uint32_t PAD_P9_PU_EN_7: 1;
+        uint32_t AON_PAD_P9_PD_7: 1;
+        uint32_t PAD_P9_PUPDC_7: 1;
+        uint32_t PAD_P9_WKEN_7: 1;
+        uint32_t PAD_P9_WKPOL_7: 1;
+        uint32_t PAD_P9_E2_7: 1;
+        uint32_t PAD_P9_SHDN_7: 1;
+        uint32_t PAD_P9_S_7: 1;
+        uint32_t PAD_P9_DEB_7: 1;
+        uint32_t PAD_P9_HS_MUX_7: 1;
+        uint32_t RSVD: 3;
+        uint32_t PAD_P9_O_EN_7: 1;
+    };
+} AON_NS_P9_6_P9_7_PAD_CFG_TYPE;
+
+/* 0x19C0   0x4000_19c0
+    0       R/W PAD_P10_O[0]                    1'b0
+    1       R/W PAD_P10_E[0]                    1'b0
+    2       R/W PAD_P10_PU_EN[0]                1'b1
+    3       R/W AON_PAD_P10_PD[0]               1'b1
+    4       R/W PAD_P10_PUPDC[0]                1'b0
+    5       R/W PAD_P10_WKEN[0]                 1'b0
+    6       R/W PAD_P10_WKPOL[0]                1'b0
+    7       R/W PAD_P10_E2[0]                   1'b1
+    8       R/W PAD_P10_SHDN[0]                 1'b1
+    9       R/W PAD_P10_S[0]                    1'b0
+    10      R/W PAD_P10_DEB[0]                  1'b0
+    11      R/W PAD_P10_HS_MUX[0]               1'b0
+    14:12   R   RSVD                            3'b0
+    15      R/W PAD_P10_O_EN[0]                 1'h1
+    16      R/W PAD_P10_O[1]                    1'b0
+    17      R/W PAD_P10_E[1]                    1'b0
+    18      R/W PAD_P10_PU_EN[1]                1'b1
+    19      R/W AON_PAD_P10_PD[1]               1'b1
+    20      R/W PAD_P10_PUPDC[1]                1'b0
+    21      R/W PAD_P10_WKEN[1]                 1'b0
+    22      R/W PAD_P10_WKPOL[1]                1'b0
+    23      R/W PAD_P10_E2[1]                   1'b1
+    24      R/W PAD_P10_SHDN[1]                 1'b1
+    25      R/W PAD_P10_S[1]                    1'b0
+    26      R/W PAD_P10_DEB[1]                  1'b0
+    27      R/W PAD_P10_HS_MUX[1]               1'b0
+    30:28   R   RSVD                            3'b0
+    31      R/W PAD_P10_O_EN[1]                 1'h1
+ */
+typedef volatile union _AON_NS_P10_0_P10_1_PAD_CFG_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t PAD_P10_O_0: 1;
+        uint32_t PAD_P10_E_0: 1;
+        uint32_t PAD_P10_PU_EN_0: 1;
+        uint32_t AON_PAD_P10_PD_0: 1;
+        uint32_t PAD_P10_PUPDC_0: 1;
+        uint32_t PAD_P10_WKEN_0: 1;
+        uint32_t PAD_P10_WKPOL_0: 1;
+        uint32_t PAD_P10_E2_0: 1;
+        uint32_t PAD_P10_SHDN_0: 1;
+        uint32_t PAD_P10_S_0: 1;
+        uint32_t PAD_P10_DEB_0: 1;
+        uint32_t PAD_P10_HS_MUX_0: 1;
+        uint32_t RSVD_1: 3;
+        uint32_t PAD_P10_O_EN_0: 1;
+        uint32_t PAD_P10_O_1: 1;
+        uint32_t PAD_P10_E_1: 1;
+        uint32_t PAD_P10_PU_EN_1: 1;
+        uint32_t AON_PAD_P10_PD_1: 1;
+        uint32_t PAD_P10_PUPDC_1: 1;
+        uint32_t PAD_P10_WKEN_1: 1;
+        uint32_t PAD_P10_WKPOL_1: 1;
+        uint32_t PAD_P10_E2_1: 1;
+        uint32_t PAD_P10_SHDN_1: 1;
+        uint32_t PAD_P10_S_1: 1;
+        uint32_t PAD_P10_DEB_1: 1;
+        uint32_t PAD_P10_HS_MUX_1: 1;
+        uint32_t RSVD: 3;
+        uint32_t PAD_P10_O_EN_1: 1;
+    };
+} AON_NS_P10_0_P10_1_PAD_CFG_TYPE;
+
+/* 0x19C4   0x4000_19c4
+    0       R/W PAD_P10_O[2]                    1'b0
+    1       R/W PAD_P10_E[2]                    1'b0
+    2       R/W PAD_P10_PU_EN[2]                1'b1
+    3       R/W AON_PAD_P10_PD[2]               1'b1
+    4       R/W PAD_P10_PUPDC[2]                1'b0
+    5       R/W PAD_P10_WKEN[2]                 1'b0
+    6       R/W PAD_P10_WKPOL[2]                1'b0
+    7       R/W PAD_P10_E2[2]                   1'b1
+    8       R/W PAD_P10_SHDN[2]                 1'b1
+    9       R/W PAD_P10_S[2]                    1'b0
+    10      R/W PAD_P10_DEB[2]                  1'b0
+    11      R/W PAD_P10_HS_MUX[2]               1'b0
+    14:12   R   RSVD                            3'b0
+    15      R/W PAD_P10_O_EN[2]                 1'h1
+    16      R   RSVD                            1'b0
+    17      R   RSVD                            1'b0
+    18      R   RSVD                            1'b1
+    19      R   RSVD                            1'b1
+    20      R   RSVD                            1'b0
+    21      R   RSVD                            1'b0
+    22      R   RSVD                            1'b0
+    23      R   RSVD                            1'b1
+    24      R   RSVD                            1'b1
+    25      R   RSVD                            1'b0
+    26      R   RSVD                            1'b0
+    27      R   RSVD                            1'b0
+    31:28   R   RSVD                            4'b0
+ */
+typedef volatile union _AON_NS_P10_2_P10_3_PAD_CFG_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t PAD_P10_O_2: 1;
+        uint32_t PAD_P10_E_2: 1;
+        uint32_t PAD_P10_PU_EN_2: 1;
+        uint32_t AON_PAD_P10_PD_2: 1;
+        uint32_t PAD_P10_PUPDC_2: 1;
+        uint32_t PAD_P10_WKEN_2: 1;
+        uint32_t PAD_P10_WKPOL_2: 1;
+        uint32_t PAD_P10_E2_2: 1;
+        uint32_t PAD_P10_SHDN_2: 1;
+        uint32_t PAD_P10_S_2: 1;
+        uint32_t PAD_P10_DEB_2: 1;
+        uint32_t PAD_P10_HS_MUX_2: 1;
+        uint32_t RSVD_13: 3;
+        uint32_t PAD_P10_O_EN_2: 1;
+        uint32_t RSVD_12: 1;
+        uint32_t RSVD_11: 1;
+        uint32_t RSVD_10: 1;
+        uint32_t RSVD_9: 1;
+        uint32_t RSVD_8: 1;
+        uint32_t RSVD_7: 1;
+        uint32_t RSVD_6: 1;
+        uint32_t RSVD_5: 1;
+        uint32_t RSVD_4: 1;
+        uint32_t RSVD_3: 1;
+        uint32_t RSVD_2: 1;
+        uint32_t RSVD_1: 1;
+        uint32_t RSVD: 4;
+    };
+} AON_NS_P10_2_P10_3_PAD_CFG_TYPE;
+
+/* 0x19C8   0x4000_19c8
+    0       R/W PAD_E3                          1'b0
+    31:1    R   RSVD                            31'b0
+ */
+typedef volatile union _AON_NS_PAD_E3_CFG_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t PAD_E3: 1;
+        uint32_t RSVD: 31;
+    };
+} AON_NS_PAD_E3_CFG_TYPE;
+
+/* 0x1AA0   0x4000_1aa0
+    0       w1c PAD_P0_STS[0]                   1'b1
+    1       w1c PAD_P0_STS[1]                   1'b1
+    2       w1c PAD_P0_STS[2]                   1'b1
+    3       w1c PAD_P0_STS[3]                   1'b1
+    4       w1c PAD_P0_STS[4]                   1'b1
+    5       w1c PAD_P0_STS[5]                   1'b1
+    6       w1c PAD_P0_STS[6]                   1'b1
+    7       w1c PAD_P0_STS[7]                   1'b1
+    8       w1c PAD_P1_STS[0]                   1'b1
+    9       w1c PAD_P1_STS[1]                   1'b1
+    10      w1c PAD_P1_STS[2]                   1'b1
+    11      w1c PAD_P1_STS[3]                   1'b1
+    12      w1c PAD_P1_STS[4]                   1'b1
+    13      w1c PAD_P1_STS[5]                   1'b1
+    14      w1c PAD_P1_STS[6]                   1'b1
+    15      w1c PAD_P1_STS[7]                   1'b1
+    16      w1c PAD_P2_STS[0]                   1'b1
+    17      w1c PAD_P2_STS[1]                   1'b1
+    18      w1c PAD_P2_STS[2]                   1'b1
+    19      w1c PAD_P2_STS[3]                   1'b1
+    20      w1c PAD_P2_STS[4]                   1'b1
+    21      w1c PAD_P2_STS[5]                   1'b1
+    22      w1c PAD_P2_STS[6]                   1'b1
+    23      w1c PAD_P2_STS[7]                   1'b1
+    24      w1c PAD_P3_STS[0]                   1'b1
+    25      w1c PAD_P3_STS[1]                   1'b1
+    26      w1c PAD_P3_STS[2]                   1'b1
+    27      w1c PAD_P3_STS[3]                   1'b1
+    28      w1c PAD_P3_STS[4]                   1'b1
+    29      w1c PAD_P3_STS[5]                   1'b1
+    30      w1c PAD_P3_STS[6]                   1'b1
+    31      w1c PAD_P3_STS[7]                   1'b1
+ */
+typedef volatile union _AON_NS_PAD_Status_0_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t PAD_P0_STS_0: 1;
+        uint32_t PAD_P0_STS_1: 1;
+        uint32_t PAD_P0_STS_2: 1;
+        uint32_t PAD_P0_STS_3: 1;
+        uint32_t PAD_P0_STS_4: 1;
+        uint32_t PAD_P0_STS_5: 1;
+        uint32_t PAD_P0_STS_6: 1;
+        uint32_t PAD_P0_STS_7: 1;
+        uint32_t PAD_P1_STS_0: 1;
+        uint32_t PAD_P1_STS_1: 1;
+        uint32_t PAD_P1_STS_2: 1;
+        uint32_t PAD_P1_STS_3: 1;
+        uint32_t PAD_P1_STS_4: 1;
+        uint32_t PAD_P1_STS_5: 1;
+        uint32_t PAD_P1_STS_6: 1;
+        uint32_t PAD_P1_STS_7: 1;
+        uint32_t PAD_P2_STS_0: 1;
+        uint32_t PAD_P2_STS_1: 1;
+        uint32_t PAD_P2_STS_2: 1;
+        uint32_t PAD_P2_STS_3: 1;
+        uint32_t PAD_P2_STS_4: 1;
+        uint32_t PAD_P2_STS_5: 1;
+        uint32_t PAD_P2_STS_6: 1;
+        uint32_t PAD_P2_STS_7: 1;
+        uint32_t PAD_P3_STS_0: 1;
+        uint32_t PAD_P3_STS_1: 1;
+        uint32_t PAD_P3_STS_2: 1;
+        uint32_t PAD_P3_STS_3: 1;
+        uint32_t PAD_P3_STS_4: 1;
+        uint32_t PAD_P3_STS_5: 1;
+        uint32_t PAD_P3_STS_6: 1;
+        uint32_t PAD_P3_STS_7: 1;
+    };
+} AON_NS_PAD_Status_0_TYPE;
+
+/* 0x1AA4   0x4000_1aa4
+    0       w1c PAD_P4_STS[0]                   1'b1
+    1       w1c PAD_P4_STS[1]                   1'b1
+    2       w1c PAD_P4_STS[2]                   1'b1
+    3       w1c PAD_P4_STS[3]                   1'b1
+    4       w1c PAD_P4_STS[4]                   1'b1
+    5       w1c PAD_P4_STS[5]                   1'b1
+    6       w1c PAD_P4_STS[6]                   1'b1
+    7       w1c PAD_P4_STS[7]                   1'b1
+    8       w1c PAD_P5_STS[0]                   1'b1
+    9       w1c PAD_P5_STS[1]                   1'b1
+    10      w1c PAD_P5_STS[2]                   1'b1
+    11      w1c PAD_P5_STS[3]                   1'b1
+    12      w1c PAD_P5_STS[4]                   1'b1
+    13      w1c PAD_P5_STS[5]                   1'b1
+    14      w1c PAD_P5_STS[6]                   1'b1
+    15      w1c PAD_P5_STS[7]                   1'b1
+    16      w1c PAD_P6_STS[0]                   1'b1
+    17      w1c PAD_P6_STS[1]                   1'b1
+    18      w1c PAD_P6_STS[2]                   1'b1
+    19      w1c PAD_P6_STS[3]                   1'b1
+    20      w1c PAD_P6_STS[4]                   1'b1
+    21      w1c PAD_P6_STS[5]                   1'b1
+    22      w1c PAD_P6_STS[6]                   1'b1
+    23      w1c PAD_P6_STS[7]                   1'b1
+    24      w1c PAD_P7_STS[0]                   1'b1
+    25      w1c PAD_P7_STS[1]                   1'b1
+    26      w1c PAD_P7_STS[2]                   1'b1
+    27      w1c PAD_P7_STS[3]                   1'b1
+    28      w1c PAD_P7_STS[4]                   1'b1
+    31:29   R   RSVD                            3'b0
+ */
+typedef volatile union _AON_NS_PAD_Status_1_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t PAD_P4_STS_0: 1;
+        uint32_t PAD_P4_STS_1: 1;
+        uint32_t PAD_P4_STS_2: 1;
+        uint32_t PAD_P4_STS_3: 1;
+        uint32_t PAD_P4_STS_4: 1;
+        uint32_t PAD_P4_STS_5: 1;
+        uint32_t PAD_P4_STS_6: 1;
+        uint32_t PAD_P4_STS_7: 1;
+        uint32_t PAD_P5_STS_0: 1;
+        uint32_t PAD_P5_STS_1: 1;
+        uint32_t PAD_P5_STS_2: 1;
+        uint32_t PAD_P5_STS_3: 1;
+        uint32_t PAD_P5_STS_4: 1;
+        uint32_t PAD_P5_STS_5: 1;
+        uint32_t PAD_P5_STS_6: 1;
+        uint32_t PAD_P5_STS_7: 1;
+        uint32_t PAD_P6_STS_0: 1;
+        uint32_t PAD_P6_STS_1: 1;
+        uint32_t PAD_P6_STS_2: 1;
+        uint32_t PAD_P6_STS_3: 1;
+        uint32_t PAD_P6_STS_4: 1;
+        uint32_t PAD_P6_STS_5: 1;
+        uint32_t PAD_P6_STS_6: 1;
+        uint32_t PAD_P6_STS_7: 1;
+        uint32_t PAD_P7_STS_0: 1;
+        uint32_t PAD_P7_STS_1: 1;
+        uint32_t PAD_P7_STS_2: 1;
+        uint32_t PAD_P7_STS_3: 1;
+        uint32_t PAD_P7_STS_4: 1;
+        uint32_t RSVD: 3;
+    };
+} AON_NS_PAD_Status_1_TYPE;
+
+/* 0x1AA8   0x4000_1aa8
+    0       w1c PAD_32K_XI_STS                  1'b1
+    1       w1c PAD_32K_XO_STS                  1'b1
+    2       w1c PAD_MICBIAS_STS                 1'b1
+    3       w1c PAD_DAC_N_STS                   1'b1
+    4       w1c PAD_DAC_P_STS                   1'b1
+    31:5    R   RSVD                            27'b0
+ */
+typedef volatile union _AON_NS_PAD_Status_2_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t PAD_32K_XI_STS: 1;
+        uint32_t PAD_32K_XO_STS: 1;
+        uint32_t PAD_MICBIAS_STS: 1;
+        uint32_t PAD_DAC_N_STS: 1;
+        uint32_t PAD_DAC_P_STS: 1;
+        uint32_t RSVD: 27;
+    };
+} AON_NS_PAD_Status_2_TYPE;
+
+/* 0x1AAC   0x4000_1aac
+    7:0     R   RSVD                            8'b0
+    13:8    R/W debIO_cnt_lmt                   6'b0
+    14      R/W debIO_wakeup_en                 1'b0
+    15      w1c debIO_wakeup_sts                1'b1
+    31:16   R   RSVD                            16'b0
+ */
+typedef volatile union _AON_NS_REG0X_DEBIO_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RSVD_1: 8;
+        uint32_t debIO_cnt_lmt: 6;
+        uint32_t debIO_wakeup_en: 1;
+        uint32_t debIO_wakeup_sts: 1;
+        uint32_t RSVD: 16;
+    };
+} AON_NS_REG0X_DEBIO_TYPE;
+
+/* 0x1AB0   0x4000_1ab0
+    0       w1c PAD_P9_STS[0]                   1'b1
+    1       w1c PAD_P9_STS[1]                   1'b1
+    2       w1c PAD_P9_STS[2]                   1'b1
+    3       w1c PAD_P9_STS[3]                   1'b1
+    4       w1c PAD_P9_STS[4]                   1'b1
+    5       w1c PAD_P9_STS[5]                   1'b1
+    6       w1c PAD_P9_STS[6]                   1'b1
+    7       w1c PAD_P9_STS[7]                   1'b1
+    8       w1c PAD_P10_STS[0]                  1'b1
+    9       w1c PAD_P10_STS[1]                  1'b1
+    10      w1c PAD_P10_STS[2]                  1'b1
+    11      R   RSVD                            1'b0
+    12      R   RSVD                            1'b0
+    13      R   RSVD                            1'b0
+    14      R   RSVD                            1'b0
+    15      R   RSVD                            1'b0
+    16      R   RSVD                            1'b0
+    17      R   RSVD                            1'b0
+    18      R   RSVD                            1'b0
+    19      R   RSVD                            1'b0
+    20      R   RSVD                            1'b0
+    21      R   RSVD                            1'b0
+    22      R   RSVD                            1'b0
+    23      R   RSVD                            1'b0
+    24      R   RSVD                            1'b0
+    25      R   RSVD                            1'b0
+    26      R   RSVD                            1'b0
+    27      R   RSVD                            1'b0
+    28      R   RSVD                            1'b0
+    31:29   R   RSVD                            3'b0
+ */
+typedef volatile union _AON_NS_PAD_Status_3_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t PAD_P9_STS_0: 1;
+        uint32_t PAD_P9_STS_1: 1;
+        uint32_t PAD_P9_STS_2: 1;
+        uint32_t PAD_P9_STS_3: 1;
+        uint32_t PAD_P9_STS_4: 1;
+        uint32_t PAD_P9_STS_5: 1;
+        uint32_t PAD_P9_STS_6: 1;
+        uint32_t PAD_P9_STS_7: 1;
+        uint32_t PAD_P10_STS_0: 1;
+        uint32_t PAD_P10_STS_1: 1;
+        uint32_t PAD_P10_STS_2: 1;
+        uint32_t RSVD_18: 1;
+        uint32_t RSVD_17: 1;
+        uint32_t RSVD_16: 1;
+        uint32_t RSVD_15: 1;
+        uint32_t RSVD_14: 1;
+        uint32_t RSVD_13: 1;
+        uint32_t RSVD_12: 1;
+        uint32_t RSVD_11: 1;
+        uint32_t RSVD_10: 1;
+        uint32_t RSVD_9: 1;
+        uint32_t RSVD_8: 1;
+        uint32_t RSVD_7: 1;
+        uint32_t RSVD_6: 1;
+        uint32_t RSVD_5: 1;
+        uint32_t RSVD_4: 1;
+        uint32_t RSVD_3: 1;
+        uint32_t RSVD_2: 1;
+        uint32_t RSVD_1: 1;
+        uint32_t RSVD: 3;
+    };
+} AON_NS_PAD_Status_3_TYPE;
+
+/* 0x1AE0   0x4000_1ae0
+    31:0    R/W FW_APP_0X                       32'h0
+ */
+typedef volatile union _AON_NS_REG0X_APP_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t reset_reason: 8;
+        uint32_t RSVD: 24;
+    };
+} AON_NS_REG0X_APP_TYPE;
+
+/* 0x1AE4   0x4000_1ae4
+    31:0    R/W FW_APP_1X                       32'h0
+ */
+typedef volatile union _AON_NS_REG1X_APP_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t FW_APP_1X;
+    };
+} AON_NS_REG1X_APP_TYPE;
+
+/* 0x1AE8   0x4000_1ae8
+    31:0    R/W FW_APP_2X                       32'h0
+ */
+typedef volatile union _AON_NS_REG2X_APP_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t FW_APP_2X;
+    };
+} AON_NS_REG2X_APP_TYPE;
+
+/* 0x1AEC   0x4000_1aec
+    31:0    R/W FW_APP_3X                       32'h0
+ */
+typedef volatile union _AON_NS_REG3X_APP_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t FW_APP_3X;
+    };
+} AON_NS_REG3X_APP_TYPE;
+
+/* 0x1AF0   0x4000_1af0
+    31:0    R/W FW_APP_4X                       32'h0
+ */
+typedef volatile union _AON_NS_REG4X_APP_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t FW_APP_4X;
+    };
+} AON_NS_REG4X_APP_TYPE;
+
+/* 0x1AF4   0x4000_1af4
+    31:0    R/W FW_APP_5X                       32'h0
+ */
+typedef volatile union _AON_NS_REG5X_APP_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t FW_APP_5X;
+    };
+} AON_NS_REG5X_APP_TYPE;
+
+/* 0x1AF8   0x4000_1af8
+    31:0    R/W FW_APP_6X                       32'h0
+ */
+typedef volatile union _AON_NS_REG6X_APP_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t FW_APP_6X;
+    };
+} AON_NS_REG6X_APP_TYPE;
+
+/* 0x1AFC   0x4000_1afc
+    31:0    R/W FW_APP_7X                       32'h0
+ */
+typedef volatile union _AON_NS_REG7X_APP_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t FW_APP_7X;
+    };
+} AON_NS_REG7X_APP_TYPE;
+
+/* 0x1B00   0x4000_1b00
+    31:0    R/W FW_APP_8X                       32'h0
+ */
+typedef volatile union _AON_NS_REG8X_APP_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t FW_APP_8X;
+    };
+} AON_NS_REG8X_APP_TYPE;
+
+/* 0x1B04   0x4000_1b04
+    31:0    R/W FW_APP_9X                       32'h0
+ */
+typedef volatile union _AON_NS_REG9X_APP_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t FW_APP_9X;
+    };
+} AON_NS_REG9X_APP_TYPE;
+
+/* 0x1B08   0x4000_1b08
+    31:0    R/W FW_APP_10X                      32'h0
+ */
+typedef volatile union _AON_NS_REG10X_APP_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t FW_APP_10X;
+    };
+} AON_NS_REG10X_APP_TYPE;
+
+/* 0x1B0C   0x4000_1b0c
+    31:0    R/W FW_APP_11X                      32'h0
+ */
+typedef volatile union _AON_NS_REG11X_APP_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t FW_APP_11X;
+    };
+} AON_NS_REG11X_APP_TYPE;
+
+/* 0x1B10   0x4000_1b10
+    31:0    R/W FW_APP_12X                      32'h0
+ */
+typedef volatile union _AON_NS_REG12X_APP_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t FW_APP_12X;
+    };
+} AON_NS_REG12X_APP_TYPE;
+
+/* 0x1B14   0x4000_1b14
+    31:0    R/W FW_APP_13X                      32'h0
+ */
+typedef volatile union _AON_NS_REG13X_APP_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t FW_APP_13X;
+    };
+} AON_NS_REG13X_APP_TYPE;
+
+/* 0x1B18   0x4000_1b18
+    31:0    R/W FW_APP_14X                      32'h0
+ */
+typedef volatile union _AON_NS_REG14X_APP_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t FW_APP_14X;
+    };
+} AON_NS_REG14X_APP_TYPE;
+
+/* 0x1B1C   0x4000_1b1c
+    31:0    R/W FW_APP_15X                      32'h0
+ */
+typedef volatile union _AON_NS_REG15X_APP_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t FW_APP_15X;
+    };
+} AON_NS_REG15X_APP_TYPE;
+
+/* 0x1B60   0x4000_1b60
+    15:0    R/W AON_WDG_WP                      16'h0
+    31:16   R/W RSVD                            16'h0
+ */
+typedef volatile union _AON_NS_AON_WDG_WP0_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t AON_WDG_WP: 16;
+        uint32_t RSVD: 16;
+    };
+} AON_NS_AON_WDG_WP0_TYPE;
+
+/* 0x1B64   0x4000_1b64
+    15:0    R/W AON_WDG_CLK_DIV_FACTOR          16'hC80
+    27:16   R/W AON_WDG_CNT_LIMIT               12'h6E
+    28      R/W AON_WDG_MODE                    1'b0
+    29      R/W AON_WDG_CNT_CTL                 1'b0
+    30      R/W AON_WDG_CNT_RELOAD              1'b0
+    31      R/W AON_WDG_ENABLE                  1'b0
+ */
+typedef volatile union _AON_NS_AON_WDG_CONFIG_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t AON_WDG_CLK_DIV_FACTOR: 16;
+        uint32_t AON_WDG_CNT_LIMIT: 12;
+        uint32_t AON_WDG_MODE: 1;
+        uint32_t AON_WDG_CNT_CTL: 1;
+        uint32_t AON_WDG_CNT_RELOAD: 1;
+        uint32_t AON_WDG_ENABLE: 1;
+    };
+} AON_NS_AON_WDG_CONFIG_TYPE;
+
+/* 0x1B68   0x4000_1b68
+    15:0    R/WACAON_WDG_CNT_RESET               16'h0
+    31:16   R/WACRSVD                            16'h0
+ */
+typedef volatile union _AON_NS_AON_WDG_CNT_RESET0_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t AON_WDG_CNT_RESET: 16;
+        uint32_t RSVD: 16;
+    };
+} AON_NS_AON_WDG_CNT_RESET0_TYPE;
+
+/* 0x1B6C   0x4000_1b6c
+    0       R/W AON_WDG_WP_SEC                  1'b0
+    1       R/W AON_WDG_CONFIG_SEC              1'b0
+    2       R/W AON_WDG_RESET_SEC               1'b0
+    31:3    R/W RSVD                            29'b0
+ */
+typedef volatile union _AON_NS_AON_WDG_SEC_CTL_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t AON_WDG_WP_SEC: 1;
+        uint32_t AON_WDG_CONFIG_SEC: 1;
+        uint32_t AON_WDG_RESET_SEC: 1;
+        uint32_t RSVD: 29;
+    };
+} AON_NS_AON_WDG_SEC_CTL_TYPE;
+
+/* 0x1B90   0x4000_1b90
+    0       R/W anapar_pow_ad<0>                1'b0
+    1       R/W anapar_pow_ad<1>                1'b0
+    2       R/W anapar_pow_ad<2>                1'b0
+    3       R/W EN_ILIMIT                       1'b0
+    4       R/W EN_VREF_SW                      1'b0
+    5       R/W EN_VREF_RC_BYPASS               1'b0
+    6       R/W REG0X_LDO_DUMMY                 1'b0
+    7       R/W hw_pd                           1'b1
+    15:8    R/W REG0X_LDO_DUMMY2                8'b0
+    22:16   R/W REG_LDO_TUNE<6:0>               7'b1011111
+    25:23   R/W LDO_SW[2:0]                     3'b100
+    26      R/W AUX_LDO_VPULSE                  1'b0
+    27      R/W SELLDO                          1'b1
+    28      R/W AUX_DOUBLE_OP_I                 1'b0
+    30:29   R/W LDOBW                           2'b11
+    31      R/W Power                           1'b1
+ */
+typedef volatile union _AON_NS_REG0X_LDO_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t anapar_pow_ad_0: 1;
+        uint32_t anapar_pow_ad_1: 1;
+        uint32_t anapar_pow_ad_2: 1;
+        uint32_t EN_ILIMIT: 1;
+        uint32_t EN_VREF_SW: 1;
+        uint32_t EN_VREF_RC_BYPASS: 1;
+        uint32_t REG0X_LDO_DUMMY: 1;
+        uint32_t hw_pd: 1;
+        uint32_t REG0X_LDO_DUMMY2: 8;
+        uint32_t REG_LDO_TUNE_6_0: 7;
+        uint32_t LDO_SW_2_0: 3;
+        uint32_t AUX_LDO_VPULSE: 1;
+        uint32_t SELLDO: 1;
+        uint32_t AUX_DOUBLE_OP_I: 1;
+        uint32_t LDOBW: 2;
+        uint32_t Power: 1;
+    };
+} AON_NS_REG0X_LDO_TYPE;
+
+/* 0x1B94   0x4000_1b94
+    0       R/W pow                             1'b0
+    1       R/W pow_ref                         1'b0
+    2       R/W reg_ck                          1'b0
+    3       R/W reg_delay                       1'b0
+    5:4     R/W reg_vref_sel[1:0]               2'b10
+    6       R/W reg_revck                       1'b0
+    8:7     R/W reg_cmpdec[1:0]                 2'b00
+    9       R/W reg_meta                        1'b0
+    10      R/W sel_ln                          1'b0
+    11      R/W sel_lna                         1'b1
+    13:12   R/W reg_vcm_sel<1:0>                2'b01
+    15:14   R/W REG0X_AUX_V09_DUMMY             2'b00
+    23:16   R/W bypassen[7:0]                   8'b00000000
+    31:24   R/W REG1X_AUX_dummy                 8'b0
+ */
+typedef volatile union _AON_NS_REG0X_AUX_V09_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t pow: 1;
+        uint32_t pow_ref: 1;
+        uint32_t reg_ck: 1;
+        uint32_t reg_delay: 1;
+        uint32_t reg_vref_sel_1_0: 2;
+        uint32_t reg_revck: 1;
+        uint32_t reg_cmpdec_1_0: 2;
+        uint32_t reg_meta: 1;
+        uint32_t sel_ln: 1;
+        uint32_t sel_lna: 1;
+        uint32_t reg_vcm_sel_1_0: 2;
+        uint32_t REG0X_AUX_V09_DUMMY: 2;
+        uint32_t bypassen_7_0: 8;
+        uint32_t REG1X_AUX_dummy: 8;
+    };
+} AON_NS_REG0X_AUX_V09_TYPE;
+
+/* 0x1B98   0x4000_1b98
+    0       R/W POW_SD_H                        1'b0
+    4:1     R/W CH_NUM_H[3:0]                   4'b0000
+    5       R/W SD_POSEDGE_H                    1'b1
+    7:6     R/W REG0X_SD_DUMMY                  2'b00
+    15:8    R/W REG0X_SD_DUMMY2                 8'b0
+    31:16   R   RSVD                            16'b0
+ */
+typedef volatile union _AON_NS_REG0X_SD_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t POW_SD_H: 1;
+        uint32_t CH_NUM_H_3_0: 4;
+        uint32_t SD_POSEDGE_H: 1;
+        uint32_t REG0X_SD_DUMMY: 2;
+        uint32_t REG0X_SD_DUMMY2: 8;
+        uint32_t RSVD: 16;
+    };
+} AON_NS_REG0X_SD_TYPE;
+
+/* 0x1BD0   0x4000_1bd0
+    1:0     R/W X_INITIAL_PHASE                 2'b0
+    2       R/W X_SET_INITAL_PHASE              1'b0
+    3       R/W X_CNT_PAUSE                     1'b0
+    4       R/W X_CNT_SCALE                     1'b0
+    5       R/W X_ILLEGAL_INT_EN                1'b0
+    6       R/W X_CNT_INT_EN                    1'b0
+    7       R/W ILLEGAL_INT_MASK                1'b1
+    8       R/W CNT_INT_MASK                    1'b1
+    21:9    R/W X_DEBOUNCE_CNT                  13'b0
+    22      R/W X_DEBOUNCE_EN                   1'b0
+    23      R/W X_WAKE_AON_MASK                 1'b1
+    24      R/W X_INT_MASK                      1'b1
+    28:25   R/W REG_CONFIG_DUMMY1               4'b0
+    29      R/W X_RST                           1'b0
+    30      R/WACX_FSM_EN                        1'b0
+    31      R/W X_AXIS_EN                       1'b0
+ */
+typedef volatile union _AON_NS_REG_CONFIG_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t X_INITIAL_PHASE: 2;
+        uint32_t X_SET_INITAL_PHASE: 1;
+        uint32_t X_CNT_PAUSE: 1;
+        uint32_t X_CNT_SCALE: 1;
+        uint32_t X_ILLEGAL_INT_EN: 1;
+        uint32_t X_CNT_INT_EN: 1;
+        uint32_t ILLEGAL_INT_MASK: 1;
+        uint32_t CNT_INT_MASK: 1;
+        uint32_t X_DEBOUNCE_CNT: 13;
+        uint32_t X_DEBOUNCE_EN: 1;
+        uint32_t X_WAKE_AON_MASK: 1;
+        uint32_t X_INT_MASK: 1;
+        uint32_t REG_CONFIG_DUMMY1: 4;
+        uint32_t X_RST: 1;
+        uint32_t X_FSM_EN: 1;
+        uint32_t X_AXIS_EN: 1;
+    };
+} AON_NS_REG_CONFIG_TYPE;
+
+/* 0x1BD4   0x4000_1bd4
+    15:0    R   ACC_CNT                         1'b0
+    16      R/W1CCNT_OF_FLG                      1'b0
+    17      R/W1CCNT_UF_FLG                      1'b0
+    18      R/W1CCNT_INT_STA                     1'b0
+    19      R/W1CILLEGAL_INT_STA                 1'b0
+    20      R   CNT_DIR                         1'b0
+    21      R/W REG_SR_X_DUMMY                  1'b0
+    23:22   R   debug_state_x                   1'b0
+    31:24   R   debug_illegal_counter_x         1'b0
+ */
+typedef volatile union _AON_NS_REG_SR_X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t ACC_CNT: 16;
+        uint32_t CNT_OF_FLG: 1;
+        uint32_t CNT_UF_FLG: 1;
+        uint32_t CNT_INT_STA: 1;
+        uint32_t ILLEGAL_INT_STA: 1;
+        uint32_t CNT_DIR: 1;
+        uint32_t REG_SR_X_DUMMY: 1;
+        uint32_t debug_state_x: 2;
+        uint32_t debug_illegal_counter_x: 8;
+    };
+} AON_NS_REG_SR_X_TYPE;
+
+/* 0x1BD8   0x4000_1bd8
+    0       R/WACACC_CNT_CLR                     1'b0
+    1       R/WACCNT_INT_CLR                     1'b0
+    2       R/WACOF_FLG_CLR                      1'b0
+    3       R/WACUF_FLG_CLR                      1'b0
+    4       R/WACILLEGAL_INT_CLR                 1'b0
+    5       R/WACILLEGAL_CNT_CLR                 1'b0
+    31:6    R/W INT_CLR_DUMMY                   26'b0
+ */
+typedef volatile union _AON_NS_INT_CLR_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t ACC_CNT_CLR: 1;
+        uint32_t CNT_INT_CLR: 1;
+        uint32_t OF_FLG_CLR: 1;
+        uint32_t UF_FLG_CLR: 1;
+        uint32_t ILLEGAL_INT_CLR: 1;
+        uint32_t ILLEGAL_CNT_CLR: 1;
+        uint32_t INT_CLR_DUMMY: 26;
+    };
+} AON_NS_INT_CLR_TYPE;
+
+/* 0x1C00   0x4000_1c00
+    31:0    R   r_km4_core_wdt_lat_km4_pc_value 32'b0
+ */
+typedef volatile union _AON_NS_REG30_CORE_KM4_PC_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t r_km4_core_wdt_lat_km4_pc_value;
+    };
+} AON_NS_REG30_CORE_KM4_PC_TYPE;
+
+/* 0x1C04   0x4000_1c04
+    31:0    R   r_km4_core_wdt_lat_km4_lr       32'b0
+ */
+typedef volatile union _AON_NS_REG34_CORE_KM4_LR_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t r_km4_core_wdt_lat_km4_lr;
+    };
+} AON_NS_REG34_CORE_KM4_LR_TYPE;
+
+/* 0x1C08   0x4000_1c08
+    31:0    R   r_km4_core_wdt_lat_km4_pc_ex    32'b0
+ */
+typedef volatile union _AON_NS_REG38_CORE_KM4_PC_EX_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t r_km4_core_wdt_lat_km4_pc_ex;
+    };
+} AON_NS_REG38_CORE_KM4_PC_EX_TYPE;
+
+/* 0x1C0C   0x4000_1c0c
+    31:0    R   r_km4_core_wdt_lat_km4_xpsr_r   32'b0
+ */
+typedef volatile union _AON_NS_REG3C_CORE_KM4_XPSR_R_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t r_km4_core_wdt_lat_km4_xpsr_r;
+    };
+} AON_NS_REG3C_CORE_KM4_XPSR_R_TYPE;
+
+/* 0x1C10   0x4000_1c10
+    31:0    R   r_km4_core_wdt_lat_km4_msp_s    32'b0
+ */
+typedef volatile union _AON_NS_REG40_CORE_KM4_MSP_S_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t r_km4_core_wdt_lat_km4_msp_s;
+    };
+} AON_NS_REG40_CORE_KM4_MSP_S_TYPE;
+
+/* 0x1C14   0x4000_1c14
+    31:0    R   r_km4_core_wdt_lat_km4_psp_s    32'b0
+ */
+typedef volatile union _AON_NS_REG44_CORE_KM4_PSP_S_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t r_km4_core_wdt_lat_km4_psp_s;
+    };
+} AON_NS_REG44_CORE_KM4_PSP_S_TYPE;
+
+/* 0x1C18   0x4000_1c18
+    31:0    R   r_km4_core_wdt_lat_km4_msp_ns   32'b0
+ */
+typedef volatile union _AON_NS_REG48_CORE_KM4_MSP_NS_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t r_km4_core_wdt_lat_km4_msp_ns;
+    };
+} AON_NS_REG48_CORE_KM4_MSP_NS_TYPE;
+
+/* 0x1C1C   0x4000_1c1c
+    31:0    R   r_km4_core_wdt_lat_km4_psp_ns   32'b0
+ */
+typedef volatile union _AON_NS_REG4C_CORE_KM4_PSP_NS_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t r_km4_core_wdt_lat_km4_psp_ns;
+    };
+} AON_NS_REG4C_CORE_KM4_PSP_NS_TYPE;
+
+/* 0x1C20   0x4000_1c20
+    31:0    R   r_km4_aon_wdt_lat_km4_pc_value  32'b0
+ */
+typedef volatile union _AON_NS_REG50_AON_KM4_PC_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t r_km4_aon_wdt_lat_km4_pc_value;
+    };
+} AON_NS_REG50_AON_KM4_PC_TYPE;
+
+/* 0x1C24   0x4000_1c24
+    31:0    R   r_km4_aon_wdt_lat_km4_lr        32'b0
+ */
+typedef volatile union _AON_NS_REG54_AON_KM4_LR_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t r_km4_aon_wdt_lat_km4_lr;
+    };
+} AON_NS_REG54_AON_KM4_LR_TYPE;
+
+/* 0x1C28   0x4000_1c28
+    31:0    R   r_km4_aon_wdt_lat_km4_pc_ex     32'b0
+ */
+typedef volatile union _AON_NS_REG58_AON_KM4_PC_EX_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t r_km4_aon_wdt_lat_km4_pc_ex;
+    };
+} AON_NS_REG58_AON_KM4_PC_EX_TYPE;
+
+/* 0x1C2C   0x4000_1c2c
+    31:0    R   r_km4_aon_wdt_lat_km4_xpsr_r    32'b0
+ */
+typedef volatile union _AON_NS_REG5C_AON_KM4_XPSR_R_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t r_km4_aon_wdt_lat_km4_xpsr_r;
+    };
+} AON_NS_REG5C_AON_KM4_XPSR_R_TYPE;
+
+/* 0x1C30   0x4000_1c30
+    31:0    R   r_km4_aon_wdt_lat_km4_msp_s     32'b0
+ */
+typedef volatile union _AON_NS_REG60_AON_KM4_MSP_S_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t r_km4_aon_wdt_lat_km4_msp_s;
+    };
+} AON_NS_REG60_AON_KM4_MSP_S_TYPE;
+
+/* 0x1C34   0x4000_1c34
+    31:0    R   r_km4_aon_wdt_lat_km4_psp_s     32'b0
+ */
+typedef volatile union _AON_NS_REG64_AON_KM4_PSP_S_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t r_km4_aon_wdt_lat_km4_psp_s;
+    };
+} AON_NS_REG64_AON_KM4_PSP_S_TYPE;
+
+/* 0x1C38   0x4000_1c38
+    31:0    R   r_km4_aon_wdt_lat_km4_msp_ns    32'b0
+ */
+typedef volatile union _AON_NS_REG68_AON_KM4_MSP_NS_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t r_km4_aon_wdt_lat_km4_msp_ns;
+    };
+} AON_NS_REG68_AON_KM4_MSP_NS_TYPE;
+
+/* 0x1C3C   0x4000_1c3c
+    31:0    R   r_km4_aon_wdt_lat_km4_psp_ns    32'b0
+ */
+typedef volatile union _AON_NS_REG6C_AON_KM4_PSP_NS_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t r_km4_aon_wdt_lat_km4_psp_ns;
+    };
+} AON_NS_REG6C_AON_KM4_PSP_NS_TYPE;
+
+/* 0x1C40   0x4000_1c40
+    1:0     R   r_aon_wdt_mode                  2'b0
+    2       R   r_aon_wdt_timeout_flag          1'b0
+    31:3    R   RSVD                            29'b0
+ */
+typedef volatile union _AON_NS_REG_AON_WDT_MODE_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t r_aon_wdt_mode: 2;
+        uint32_t r_aon_wdt_timeout_flag: 1;
+        uint32_t RSVD: 29;
+    };
+} AON_NS_REG_AON_WDT_MODE_TYPE;
+
+/* 0x1C44   0x4000_1c44
+    1:0     R   r_km4_wdt_mode                  2'b0
+    2       R   r_km4_wdt_timeout_flag          1'b0
+    31:3    R   RSVD                            29'b0
+ */
+typedef volatile union _AON_NS_REG_KM4_WDT_MODE_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t r_km4_wdt_mode: 2;
+        uint32_t r_km4_wdt_timeout_flag: 1;
+        uint32_t RSVD: 29;
+    };
+} AON_NS_REG_KM4_WDT_MODE_TYPE;
+
+/* 0x1D00   0x4000_1d00
+    0       R/W km4_aon_boot_done               1'b0
+    1       R/W km4_pon_boot_done               1'b0
+    2       R/W km4_dvfs_normal_vdd_mode        1'b0
+    3       R/W km4_boot_rsvd0                  1'b0
+    4       R/W is_pf_rtc_clk_32000Hz           1'b0
+    5       R/W is_user_rtc_clk_32000Hz         1'b0
+    6       R/W is_btmac_clk_32000Hz            1'b0
+    7       R/W is_aon_clk_32000Hz              1'b0
+    8       R/W is_systick_clk_32000Hz          1'b0
+    31:9    R/W km4_boot_rsvd1                  23'b0
+ */
+typedef volatile union _AON_NS_REG0X_FW_GENERAL_NS_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t km4_aon_boot_done: 1;
+        uint32_t km4_pon_boot_done: 1;
+        uint32_t km4_dvfs_normal_vdd_mode: 1;
+        uint32_t km4_boot_rsvd0: 1;
+        uint32_t is_pf_rtc_clk_32000Hz: 1;
+        uint32_t is_user_rtc_clk_32000Hz: 1;
+        uint32_t is_btmac_clk_32000Hz: 1;
+        uint32_t is_aon_clk_32000Hz: 1;
+        uint32_t is_systick_clk_32000Hz: 1;
+        uint32_t km4_boot_rsvd1: 23;
+    };
+} AON_NS_REG0X_FW_GENERAL_NS_TYPE;
+
+/* 0x1D04   0x4000_1d04
+    15:0    R/W FW_GENERAL_NS_REG2X             16'h0
+    31:16   R/W FW_GENERAL_NS_REG3X             16'h0
+ */
+typedef volatile union _AON_NS_REG2X_FW_GENERAL_NS_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t FW_GENERAL_NS_REG2X: 16;
+        uint32_t FW_GENERAL_NS_REG3X: 16;
+    };
+} AON_NS_REG2X_FW_GENERAL_NS_TYPE;
+
+/* 0x1D08   0x4000_1d08
+    15:0    R/W FW_GENERAL_NS_REG4X             16'h0
+    31:16   R/W FW_GENERAL_NS_REG5X             16'h0
+ */
+typedef volatile union _AON_NS_REG4X_FW_GENERAL_NS_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t FW_GENERAL_NS_REG4X: 16;
+        uint32_t FW_GENERAL_NS_REG5X: 16;
+    };
+} AON_NS_REG4X_FW_GENERAL_NS_TYPE;
+
+/* 0x1D0C   0x4000_1d0c
+    15:0    R/W FW_GENERAL_NS_REG6X             16'h0
+    31:16   R/W FW_GENERAL_NS_REG7X             16'h0
+ */
+typedef volatile union _AON_NS_REG6X_FW_GENERAL_NS_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t FW_GENERAL_NS_REG6X: 16;
+        uint32_t FW_GENERAL_NS_REG7X: 16;
+    };
+} AON_NS_REG6X_FW_GENERAL_NS_TYPE;
+
+/* 0x1D10   0x4000_1d10
+    0       R/W ota_mode                        1'b0
+    1       R/W is_ft_mode                      1'b0
+    2       R/W is_hci_mode                     1'b0
+    3       R/W is_single_tone_mode             1'b0
+    15:4    R/W rsvd                            12'h0
+    31:16   R/W FW_GENERAL_NS_REG9X             16'h0
+ */
+typedef volatile union _AON_NS_REG8X_FW_GENERAL_NS_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t ota_mode: 1;
+        uint32_t is_ft_mode: 1;
+        uint32_t is_hci_mode: 1;
+        uint32_t is_single_tone_mode: 1;
+        uint32_t rsvd: 12;
+        uint32_t FW_GENERAL_NS_REG9X: 16;
+    };
+} AON_NS_REG8X_FW_GENERAL_NS_TYPE;
+
+/* 0x1D14   0x4000_1d14
+    15:0    R/W FW_GENERAL_NS_REG10X            16'h0
+    31:16   R/W FW_GENERAL_NS_REG11X            16'h0
+ */
+typedef volatile union _AON_NS_REG10X_FW_GENERAL_NS_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t FW_GENERAL_NS_REG10X: 16;
+        uint32_t FW_GENERAL_NS_REG11X: 16;
+    };
+} AON_NS_REG10X_FW_GENERAL_NS_TYPE;
+
+/* 0x1D80   0x4000_1d80
+    7:0     R/W PAD_P0_E_LCD[7:0]               8'b0
+    9:8     R   RSVD                            2'b0
+    15:10   R/W PAD_P1_E_LCD[7:2]               6'b0
+    23:16   R   RSVD                            8'b0
+    25:24   R   RSVD                            2'b0
+    31:26   R/W PAD_P3_E_LCD[7:2]               6'b0
+ */
+typedef volatile union _AON_NS_P3_P1_PAD_E_LCD_CFG_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t PAD_P0_E_LCD_7_0: 8;
+        uint32_t RSVD_2: 2;
+        uint32_t PAD_P1_E_LCD_7_2: 6;
+        uint32_t RSVD_1: 8;
+        uint32_t RSVD: 2;
+        uint32_t PAD_P3_E_LCD_7_2: 6;
+    };
+} AON_NS_P3_P1_PAD_E_LCD_CFG_TYPE;
+
+/* 0x1D84   0x4000_1d84
+    7:0     R/W PAD_P4_E_LCD[7:0]               8'b0
+    13:8    R/W PAD_P5_E_LCD[5:0]               6'b0
+    15:14   R   RSVD                            2'b0
+    23:16   R   RSVD                            8'b0
+    31:24   R   RSVD                            8'b0
+ */
+typedef volatile union _AON_NS_P7_P4_PAD_E_LCD_CFG_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t PAD_P4_E_LCD_7_0: 8;
+        uint32_t PAD_P5_E_LCD_5_0: 6;
+        uint32_t RSVD_2: 2;
+        uint32_t RSVD_1: 8;
+        uint32_t RSVD: 8;
+    };
+} AON_NS_P7_P4_PAD_E_LCD_CFG_TYPE;
+
+/* 0x1D88   0x4000_1d88
+    7:0     R   RSVD                            8'b0
+    10:8    R/W PAD_P9_E_LCD[2:0]               3'b0
+    15:11   R   RSVD                            5'b0
+    23:16   R   RSVD                            8'b0
+    31:24   R   RSVD                            8'b0
+ */
+typedef volatile union _AON_NS_P11_P8_PAD_E_LCD_CFG_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RSVD_3: 8;
+        uint32_t PAD_P9_E_LCD_2_0: 3;
+        uint32_t RSVD_2: 5;
+        uint32_t RSVD_1: 8;
+        uint32_t RSVD: 8;
+    };
+} AON_NS_P11_P8_PAD_E_LCD_CFG_TYPE;
+
+/* 0x1D8C   0x4000_1d8c
+    7:0     R/W PAD_P0_SHDN_LCD[7:0]            8'b0
+    9:8     R   RSVD                            2'b0
+    15:10   R/W PAD_P1_SHDN_LCD[7:2]            6'b0
+    23:16   R   RSVD                            8'b0
+    25:24   R   RSVD                            2'b0
+    31:26   R/W PAD_P3_SHDN_LCD[7:2]            6'b0
+ */
+typedef volatile union _AON_NS_P3_P1_PAD_SHDN_LCD_CFG_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t PAD_P0_SHDN_LCD_7_0: 8;
+        uint32_t RSVD_2: 2;
+        uint32_t PAD_P1_SHDN_LCD_7_2: 6;
+        uint32_t RSVD_1: 8;
+        uint32_t RSVD: 2;
+        uint32_t PAD_P3_SHDN_LCD_7_2: 6;
+    };
+} AON_NS_P3_P1_PAD_SHDN_LCD_CFG_TYPE;
+
+/* 0x1D90   0x4000_1d90
+    7:0     R/W PAD_P4_SHDN_LCD[7:0]            8'b0
+    13:8    R/W PAD_P5_SHDN_LCD[5:0]            6'b0
+    15:14   R   RSVD                            2'b0
+    23:16   R   RSVD                            8'b0
+    31:24   R   RSVD                            8'b0
+ */
+typedef volatile union _AON_NS_P7_P4_PAD_SHDN_LCD_CFG_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t PAD_P4_SHDN_LCD_7_0: 8;
+        uint32_t PAD_P5_SHDN_LCD_5_0: 6;
+        uint32_t RSVD_2: 2;
+        uint32_t RSVD_1: 8;
+        uint32_t RSVD: 8;
+    };
+} AON_NS_P7_P4_PAD_SHDN_LCD_CFG_TYPE;
+
+/* 0x1D94   0x4000_1d94
+    7:0     R   RSVD                            8'b0
+    10:8    R/W PAD_P9_SHDN_LCD[2:0]            3'b0
+    15:11   R   RSVD                            5'b0
+    23:16   R   RSVD                            8'b0
+    31:24   R   RSVD                            8'b0
+ */
+typedef volatile union _AON_NS_P11_P8_PAD_SHDN_LCD_CFG_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RSVD_3: 8;
+        uint32_t PAD_P9_SHDN_LCD_2_0: 3;
+        uint32_t RSVD_2: 5;
+        uint32_t RSVD_1: 8;
+        uint32_t RSVD: 8;
+    };
+} AON_NS_P11_P8_PAD_SHDN_LCD_CFG_TYPE;
+
+/* 0x1DC0   0x4000_1dc0
+    4:0     R/W REG0X_SDADC_LDO_DUMMY           5'b01010
+    5       R/W REG_POCDB_SDADC                 1'b0
+    6       R/W REG_ANAPAR_POW_LDO<0>           1'b0
+    7       R/W REG_ANAPAR_POW_LDO<1>           1'b0
+    12:8    R/W REG_ANAPAR_LDO<4:0>             5'b10000
+    13      R/W REG_ANAPAR_LDO<5>               1'b0
+    14      R/W REG_ANAPAR_LDO<6>               1'b0
+    15      R/W REG_ANAPAR_LDO<7>               1'b0
+    17:16   R/W REG_ANAPAR_LDO<9:8>             2'b00
+    18      R/W REG_ANAPAR_LDO<10>              1'b0
+    21:19   R/W REG_ANAPAR_LDO<13:11>           3'b100
+    24:22   R/W REG_ANAPAR_LDO<16:14>           3'b100
+    25      R/W REG_ANAPAR_LDO<17>              1'b0
+    26      R/W REG_ANAPAR_LDO<18>              1'b0
+    31:27   R/W REG_ANAPAR_LDO<23:17>           5'b10101
+ */
+typedef volatile union _AON_NS_REG0X_SDADC_LDO_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t REG0X_SDADC_LDO_DUMMY: 5;
+        uint32_t REG_POCDB_SDADC: 1;
+        uint32_t REG_ANAPAR_POW_LDO_0: 1;
+        uint32_t REG_ANAPAR_POW_LDO_1: 1;
+        uint32_t REG_ANAPAR_LDO_4_0: 5;
+        uint32_t REG_ANAPAR_LDO_5: 1;
+        uint32_t REG_ANAPAR_LDO_6: 1;
+        uint32_t REG_ANAPAR_LDO_7: 1;
+        uint32_t REG_ANAPAR_LDO_9_8: 2;
+        uint32_t REG_ANAPAR_LDO_10: 1;
+        uint32_t REG_ANAPAR_LDO_13_11: 3;
+        uint32_t REG_ANAPAR_LDO_16_14: 3;
+        uint32_t REG_ANAPAR_LDO_17: 1;
+        uint32_t REG_ANAPAR_LDO_18: 1;
+        uint32_t REG_ANAPAR_LDO_23_17: 5;
+    } b;
+} AON_NS_REG0X_SDADC_LDO_TYPE;
+
+#define AON_REG_BASE 0x40000000
+
+#define AON_REG_READ(Offset)                                            \
+    ((uint32_t)*((volatile uint32_t*)(AON_REG_BASE+(Offset))))
+
+#define AON_REG_WRITE(Offset, Value)                                    \
+    ((*((volatile uint32_t*)(AON_REG_BASE + (Offset)))) = (Value))
+
+#define AON_REG_UPDATE(Offset, Mask, Value)                             \
+    do {                                                                \
+        uint32_t temp;                                                  \
+        temp = AON_REG_READ(Offset) & ~(Mask);                          \
+        AON_REG_WRITE(Offset, (temp | ((Value) & (Mask))));             \
+    } while(0)
+
+#define AON_REG_READ_BITFIELD(Offset, Bitfield)                         \
+    (((Offset##_TYPE)AON_REG_READ(Offset)).Bitfield)
+
+#define AON_REG_WRITE_BITFIELD(Offset, Bitfield, Value)                 \
+    do {                                                                \
+        Offset##_TYPE temp = {.d32 = AON_REG_READ(Offset)};             \
+        temp.Bitfield = Value;                                          \
+        AON_REG_WRITE(Offset, temp.d32);                                \
+    } while(0)
+#endif
diff --git a/bee/soc/inc/rtl87x2g/armv81mml_setting.h b/bee/soc/inc/rtl87x2g/armv81mml_setting.h
new file mode 100644
index 00000000..5279366b
--- /dev/null
+++ b/bee/soc/inc/rtl87x2g/armv81mml_setting.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ARMV81_SETTING_H
+#define ARMV81_SETTING_H
+
+/* ================================================================================ */
+/* ================      Processor and Core Peripheral Section     ================ */
+/* ================================================================================ */
+#define __ARMv8MML_REV            0x0001U   /* Core revision r0p1 */
+#define __SAUREGION_PRESENT       1U        /* SAU regions present */
+#define __MPU_PRESENT             1U        /* MPU present */
+#define __VTOR_PRESENT            1U        /* VTOR present */
+#define __NVIC_PRIO_BITS          3U        /* Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig    0U        /* Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT             1U        /* FPU present */
+#define __FPU_DP                  0U        /* single precision FPU */
+#define __DSP_PRESENT             1U        /* DSP extension present */
+#define __ICACHE_PRESENT          1U
+#define __DCACHE_PRESENT          1U
+
+/*============================================================================*
+ *                               Header Files
+*============================================================================*/
+#include "vector_table.h"
+#include "core_cm55.h"                       /* Processor and core peripherals */
+
+#endif //#define ARMV81_SETTING_H
diff --git a/bee/soc/inc/rtl87x2g/cpu_setting.h b/bee/soc/inc/rtl87x2g/cpu_setting.h
new file mode 100644
index 00000000..55b47b2d
--- /dev/null
+++ b/bee/soc/inc/rtl87x2g/cpu_setting.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef CPU_SETTING_H
+#define CPU_SETTING_H
+
+/*============================================================================*
+ *                               Header Files
+*============================================================================*/
+#include "armv81mml_setting.h"                       /* Processor and core peripherals */
+
+#endif //#define CPU_SETTING_H
diff --git a/bee/soc/inc/rtl87x2g/non_secure/address_map.h b/bee/soc/inc/rtl87x2g/non_secure/address_map.h
new file mode 100644
index 00000000..4c462ac5
--- /dev/null
+++ b/bee/soc/inc/rtl87x2g/non_secure/address_map.h
@@ -0,0 +1,86 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ADDRESS_MAP_H
+#define ADDRESS_MAP_H
+
+/* ================================================================================ */
+/* ================                  Address Map                   ================ */
+/* ======== Reference: RTL87x2G_AddrMap_IRQs_DmaPorts_20220913v0.xlsx   ============ */
+/* ================================================================================ */
+
+#define SYSTEM_REG_BASE                    0x40000000UL
+#define RTC_REG_BASE                       0x40001800UL
+#define LPC_REG_BASE                       0x40001850UL
+#define LPC0_REG_BASE                      0x40001850UL
+#define PAD_REG_BASE                       0x40001900UL
+#define PAD_STS_REG_BASE                   0x40001AA0UL
+#define AON_WDT_REG_BASE                   0x40001B60UL
+#define AUXADC_REG_BASE                    0x40001B90UL
+#define QUAD_DECODER_REG_BASE              0x40001BD0UL
+#define PERI_ON_REG_BASE                   0x40002000UL
+#define PERI_ON_RCC_REG_BASE               0x40002300UL
+#define GPIOA_DEB_REG_BASE                 0x4000234CUL
+#define GPIOB_DEB_REG_BASE                 0x40002360UL
+#define TIMER_PWM_REG_BASE                 0x4000233CUL
+#define PINMUX_REG_BASE                    0x40002500UL
+#define QDEC_REG_BASE                      0x40009000UL
+#define SPI0_REG_BASE                      0x40013000UL
+#define SPI1_REG_BASE                      0x40013400UL
+#define SPI_SLAVE_REG_BASE                 0x40013800UL
+#define ENHANCED_TIMER_REG_BASE            0x40017000UL
+#define MODEMRFCPI_REG_BASE                0x40018000UL
+#define I2S0_REG_BASE                      0x40020000UL
+#define I2S1_REG_BASE                      0x40021000UL
+#define SPI_CODEC_REG_BASE                 0x40022000UL
+#define DISPLAY_CTRL_REG_BASE              0x40023000UL
+#define RXI350_DMAC0_CFG_REG_BASE          0x40024000UL
+#define PPE_CFG_REG_BASE                   0x40025000UL
+#define ISO7816_REG_BASE                   0x40026000UL
+#define SEGCOM_CTL_REG_BASE                0x40027000UL
+#define A2C_REG_BASE                       0x40028000UL
+#define SPIC_PHY_REG_BASE                  0x40029000UL
+
+#define PUBLIC_KEY_ENGINE_REG_BASE         0x40080000UL
+#define FLASH_SEC_REG_BASE                 0x400C0000UL
+#define AES_REG_BASE                       0x400C1000UL
+#define SHA256_REG_BASE                    0x400C2000UL
+#define TRNG_REG_BASE                      0x400C2400UL
+#define EFUSE_CONTROLLER_REG_BASE          0x400C2800UL
+#define USB_OTG_CFG_REG_BASE               0x40100000UL
+#define SPIC0_REG_BASE                     0x40140000UL
+#define SDHC_REG_BASE                      0x40150000UL
+#define SPIC1_REG_BASE                     0x40160000UL
+#define SPIC2_REG_BASE                     0x40170000UL
+#define GPIOA_REG_BASE                     0x40030000UL
+#define GPIOB_REG_BASE                     0x40030800UL
+#define TIMER_REG_BASE                     0x40031000UL
+#define SAR_ADC_REG_BASE                   0x40032000UL
+#define HRADC_REG_BASE                     0x40033000UL
+#define UART0_REG_BASE                     0x40034000UL
+#define UART1_REG_BASE                     0x40034400UL
+#define UART2_REG_BASE                     0x40034800UL
+#define UART3_REG_BASE                     0x40034C00UL
+#define UART4_REG_BASE                     0x40035000UL
+#define UART5_REG_BASE                     0x40035400UL
+#define I2C0_REG_BASE                      0x40035800UL
+#define I2C1_REG_BASE                      0x40035C00UL
+#define I2C2_REG_BASE                      0x40036000UL
+#define I2C3_REG_BASE                      0x40036400UL
+#define SPI3W_REG_BASE                     0x40036800UL
+#define KEYSCAN_REG_BASE                   0x40037000UL
+#define IR_RC_REG_BASE                     0x40038000UL
+#define ETH_CTRL_REG_BASE                  0x40040000UL
+#define BLUEWIZ_REG_BASE                   0x40050000UL
+#define BT_DMA_UART_BASE                   0x40051000UL
+#define BT_DMA_BASE                        0x40055000UL
+#define BT_VENDOR_REG_BASE                 0x40058000UL
+#define ZIGBEE_REG_BASE                    0x4005C000UL
+#define SPI0_HS_REG_BASE                   0x40060000UL
+#define IMDC_REG_BASE                      0x40070000UL
+
+
+#endif //#define ADDRESS_MAP_H 
diff --git a/bee/soc/inc/rtl87x2g/nsc_veneer.h b/bee/soc/inc/rtl87x2g/nsc_veneer.h
new file mode 100644
index 00000000..4eba5f86
--- /dev/null
+++ b/bee/soc/inc/rtl87x2g/nsc_veneer.h
@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __NSC_VENEER_H__
+#define __NSC_VENEER_H__
+
+#include <stdint.h>
+
+typedef void (*NonSecure_func)(void);
+
+typedef enum
+{
+    SECURE_APP_FUNCTION_OPCODE_INIT = 0,
+} SECURE_APP_FUNCTION_OPCODE;
+
+typedef enum
+{
+    SECURE_FUNCTION_OPCODE_INIT = 0,
+    EFUSE_ACCESS = 1,
+    EFUSE_RAM_ACCESS = 2,
+    SECURE_REGION_ACCESS = 3,
+    DISABLE_SWD_PIN = 4,
+    SPIC_SET_INTERFACE = 5,
+    XTAL_40M_AAC_CAL = 6,
+    PSRAM_LMP_CTRL = 7,
+    WDT_GET_TIMEOUT_MS = 8,
+    WDT_GET_MODE = 9,
+    HW_AES_SET = 10,
+    AON_WDT_GET_TIMEOUT_MS = 11,
+    AON_WDT_GET_MODE = 12,
+    AON_WDT_IS_ENABLE = 13,
+} SECURE_FUNCTION_OPCODE;
+
+typedef enum
+{
+    SEC_FPTR_OPCODE_OS_AES_SEM_TAKE = 0,
+    SEC_FPTR_OPCODE_OS_AES_SEM_GIVE,
+    SEC_FPTR_OPCODE_PRINT_LOG_BUFF,
+    SEC_FPTR_OPCODE_APP_CB_WDG_RESET,
+    SEC_FPTR_OPCODE_OS_LOCK,
+    SEC_FPTR_OPCODE_OS_UNLOCK,
+    SEC_FPTR_OPCODE_OS_TASK_HDL_GET,
+    SEC_FPTR_OPCODE_OS_TASK_PRI_GET,
+    SEC_FPTR_OPCODE_WRITE_INFO_TO_FLASH_BEFORE_RESET,
+    SEC_FPTR_OPCODE_SAVE_SYSTEM_STATUS_TO_FLASH,
+    SEC_FPTR_OPCODE_OS_MEM_ALLOC,
+} SECURE_FPTR;
+
+void secure_app_function_call(SECURE_APP_FUNCTION_OPCODE opcode, void *param);
+void secure_function_call(SECURE_FUNCTION_OPCODE opcode, void *param);
+void set_secure_func_ptr(SECURE_FPTR opcode, NonSecure_func func);
+
+#endif /* __NSC_VENEER_H__ */
diff --git a/bee/soc/inc/rtl87x2g/pcc_reg.h b/bee/soc/inc/rtl87x2g/pcc_reg.h
new file mode 100644
index 00000000..aad386c9
--- /dev/null
+++ b/bee/soc/inc/rtl87x2g/pcc_reg.h
@@ -0,0 +1,1639 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef PCC_REG_H
+#define PCC_REG_H
+#include <stdint.h>
+
+/* ================================================================================ */
+/* ================                PCC Register               ================ */
+/* ===========     Reference: RTL87x2G_PERI-ON_20221201_v1.xlsx     =========== */
+/* ================================================================================ */
+typedef struct
+{
+    /* 0x300        0x4000_2300
+        3:0     R/W    r_spic0_div_sel                 4'h0
+        4       R/W    r_spic0_div_en                  1'h0
+        5       R/W    r_spic0_clk_src_en              1'h1
+        6       R/W    RSVD                            1'h0
+        7       R/W    RSVD                            1'h0
+        8       R/W    r_spic0_mux_1_clk_cg_en         1'h1
+        9       R/W    r_spic0_clk_src_sel0            1'h0
+        10      R/W    r_spic0_clk_src_sel1            1'h0
+        11      R/W    RSVD                            1'h0
+        15:12   R/W    RSVD                            4'h0
+        17:16   R/W    r_flash0_phy_clk_sel            2'h0
+        18      R/W    r_flash0_clk_inv_en             1'b0
+        26:19   R/W    r_pon_dlysel_spic0              8'h0
+        27      R/W    spic0_phy_func_en               1'h0
+        28      R/W    spic0_phy_str_en                1'h1
+        29      R/W    RSVD                            1'h0
+        30      R/W    spic0_ck_en                     1'h0
+        31      R/W    spic0_func_en                   1'h0
+    */
+    union
+    {
+        __IO uint32_t REG_PERI_SPIC0_CTL;
+        struct
+        {
+            __IO uint32_t r_spic0_div_sel: 4;
+            __IO uint32_t r_spic0_div_en: 1;
+            __IO uint32_t r_spic0_clk_src_en: 1;
+            __IO uint32_t RESERVED_4: 1;
+            __IO uint32_t RESERVED_3: 1;
+            __IO uint32_t r_spic0_mux_1_clk_cg_en: 1;
+            __IO uint32_t r_spic0_clk_src_sel0: 1;
+            __IO uint32_t r_spic0_clk_src_sel1: 1;
+            __IO uint32_t RESERVED_2: 1;
+            __IO uint32_t RESERVED_1: 4;
+            __IO uint32_t r_flash0_phy_clk_sel: 2;
+            __IO uint32_t r_flash0_clk_inv_en: 1;
+            __IO uint32_t r_pon_dlysel_spic0: 8;
+            __IO uint32_t spic0_phy_func_en: 1;
+            __IO uint32_t spic0_phy_str_en: 1;
+            __IO uint32_t RESERVED_0: 1;
+            __IO uint32_t spic0_ck_en: 1;
+            __IO uint32_t spic0_func_en: 1;
+        } BITS_300;
+    } u_300;
+
+    /* 0x304        0x4000_2304
+        3:0     R/W    r_spic1_div_sel                 4'h0
+        4       R/W    r_spic1_div_en                  1'h0
+        5       R/W    r_spic1_clk_src_en              1'h1
+        6       R/W    RSVD                            1'h0
+        7       R/W    RSVD                            1'h0
+        8       R/W    r_spic1_mux_1_clk_cg_en         1'h0
+        9       R/W    r_spic1_clk_src_sel0            1'h0
+        10      R/W    r_spic1_clk_src_sel1            1'h0
+        11      R/W    RSVD                            1'h0
+        15:12   R/W    RSVD                            4'h0
+        17:16   R/W    r_spic1_phy_clk_sel             2'h0
+        18      R/W    r_spic1_clk_inv_en              1'b0
+        26:19   R/W    r_pon_dlysel_spic1              8'h0
+        27      R/W    spic1_phy_func_en               1'h0
+        28      R/W    spic1_phy_str_en                1'h0
+        29      R/W    spic1_phy_apb_ck_en             1'h0
+        30      R/W    spic1_ck_en                     1'h0
+        31      R/W    spic1_func_en                   1'h0
+    */
+    union
+    {
+        __IO uint32_t REG_PERI_SPIC1_CTL;
+        struct
+        {
+            __IO uint32_t r_spic1_div_sel: 4;
+            __IO uint32_t r_spic1_div_en: 1;
+            __IO uint32_t r_spic1_clk_src_en: 1;
+            __IO uint32_t RESERVED_3: 1;
+            __IO uint32_t RESERVED_2: 1;
+            __IO uint32_t r_spic1_mux_1_clk_cg_en: 1;
+            __IO uint32_t r_spic1_clk_src_sel0: 1;
+            __IO uint32_t r_spic1_clk_src_sel1: 1;
+            __IO uint32_t RESERVED_1: 1;
+            __IO uint32_t RESERVED_0: 4;
+            __IO uint32_t r_spic1_phy_clk_sel: 2;
+            __IO uint32_t r_spic1_clk_inv_en: 1;
+            __IO uint32_t r_pon_dlysel_spic1: 8;
+            __IO uint32_t spic1_phy_func_en: 1;
+            __IO uint32_t spic1_phy_str_en: 1;
+            __IO uint32_t spic1_phy_apb_ck_en: 1;
+            __IO uint32_t spic1_ck_en: 1;
+            __IO uint32_t spic1_func_en: 1;
+        } BITS_304;
+    } u_304;
+
+    /* 0x308        0x4000_2308
+        3:0     R/W    r_spic2_div_sel                 4'h0
+        4       R/W    r_spic2_div_en                  1'h0
+        5       R/W    r_spic2_clk_src_en              1'h1
+        6       R/W    RSVD                            1'h0
+        7       R/W    RSVD                            1'h0
+        8       R/W    r_spic2_mux_1_clk_cg_en         1'h0
+        9       R/W    r_spic2_clk_src_sel0            1'h0
+        10      R/W    r_spic2_clk_src_sel1            1'h0
+        11      R/W    RSVD                            1'h0
+        15:12   R/W    RSVD                            4'h0
+        17:16   R/W    r_spic2_phy_clk_sel             2'h0
+        18      R/W    r_spic2_clk_inv_en              1'b0
+        26:19   R/W    r_pon_dlysel_spic2              8'h0
+        27      R/W    spic2_phy_func_en               1'h0
+        28      R/W    spic2_phy_str_en                1'h0
+        29      R/W    RSVD                            1'h0
+        30      R/W    spic2_ck_en                     1'h0
+        31      R/W    spic2_func_en                   1'h0
+    */
+    union
+    {
+        __IO uint32_t REG_PERI_SPIC2_CTL;
+        struct
+        {
+            __IO uint32_t r_spic2_div_sel: 4;
+            __IO uint32_t r_spic2_div_en: 1;
+            __IO uint32_t r_spic2_clk_src_en: 1;
+            __IO uint32_t RESERVED_4: 1;
+            __IO uint32_t RESERVED_3: 1;
+            __IO uint32_t r_spic2_mux_1_clk_cg_en: 1;
+            __IO uint32_t r_spic2_clk_src_sel0: 1;
+            __IO uint32_t r_spic2_clk_src_sel1: 1;
+            __IO uint32_t RESERVED_2: 1;
+            __IO uint32_t RESERVED_1: 4;
+            __IO uint32_t r_spic2_phy_clk_sel: 2;
+            __IO uint32_t r_spic2_clk_inv_en: 1;
+            __IO uint32_t r_pon_dlysel_spic2: 8;
+            __IO uint32_t spic2_phy_func_en: 1;
+            __IO uint32_t spic2_phy_str_en: 1;
+            __IO uint32_t RESERVED_0: 1;
+            __IO uint32_t spic2_ck_en: 1;
+            __IO uint32_t spic2_func_en: 1;
+        } BITS_308;
+    } u_308;
+
+    /* 0x30C        0x4000_230c
+        0       R/W    gdma0_func_en                   1'h0
+        1       R/W    gdma0_ck_en                     1'h0
+        31:2    R/W    RSVD                            30'h0
+    */
+    union
+    {
+        __IO uint32_t REG_DMA_CTRL0;
+        struct
+        {
+            __IO uint32_t gdma0_func_en: 1;
+            __IO uint32_t gdma0_ck_en: 1;
+            __IO uint32_t RESERVED_0: 30;
+        } BITS_30C;
+    } u_30C;
+
+    /* 0x310        0x4000_2310
+        0       R/W    spi0_func_en                    1'h0
+        1       R/W    spi0_ck_en                      1'h0
+        2       R/W    spi0_div_en                     1'h0
+        5:3     R/W    spi0_div_sel                    3'b000
+        6       R/W    spi0_brg_en                     1'h0
+        7       R/W    spi0_hs_ck_en                   1'h0
+        8       R/W    spi1_func_en                    1'h0
+        9       R/W    spi1_ck_en                      1'h0
+        10      R/W    spi1_div_en                     1'h0
+        13:11   R/W    spi1_div_sel                    3'b000
+        14      R/W    spi1_brg_en                     1'h0
+        15      R/W    PON_SPI0_MST                    1'h0
+        16      R/W    spi0_s_func_en                  1'h0
+        17      R/W    spi0_s_ck_en                    1'h0
+        18      R/W    spi0_s_div_en                   1'h0
+        21:19   R/W    spi0_s_div_sel                  3'b000
+        22      R/W    RSVD                            1'h0
+        23      R/W    RSVD                            1'h0
+        24      R/W    spi0_src_clk_sel0               1'h0
+        25      R/W    spi0_src_clk_sel1               1'h0
+        26      R/W    spi0_s_src_clk_sel0             1'h0
+        27      R/W    spi0_s_src_clk_sel1             1'h0
+        28      R/W    spi0_mux_clk_cg_en              1'h0
+        29      R/W    spi0_s_mux_clk_cg_en            1'h0
+        31:30   R/W    RSVD                            2'h0
+    */
+    union
+    {
+        __IO uint32_t REG_SPI_PERI_CTL0;
+        struct
+        {
+            __IO uint32_t spi0_func_en: 1;
+            __IO uint32_t spi0_ck_en: 1;
+            __IO uint32_t spi0_div_en: 1;
+            __IO uint32_t spi0_div_sel: 3;
+            __IO uint32_t spi0_brg_en: 1;
+            __IO uint32_t spi0_hs_ck_en: 1;
+            __IO uint32_t spi1_func_en: 1;
+            __IO uint32_t spi1_ck_en: 1;
+            __IO uint32_t spi1_div_en: 1;
+            __IO uint32_t spi1_div_sel: 3;
+            __IO uint32_t spi1_brg_en: 1;
+            __IO uint32_t PON_SPI0_MST: 1;
+            __IO uint32_t spi0_s_func_en: 1;
+            __IO uint32_t spi0_s_ck_en: 1;
+            __IO uint32_t spi0_s_div_en: 1;
+            __IO uint32_t spi0_s_div_sel: 3;
+            __IO uint32_t RESERVED_2: 1;
+            __IO uint32_t RESERVED_1: 1;
+            __IO uint32_t spi0_src_clk_sel0: 1;
+            __IO uint32_t spi0_src_clk_sel1: 1;
+            __IO uint32_t spi0_s_src_clk_sel0: 1;
+            __IO uint32_t spi0_s_src_clk_sel1: 1;
+            __IO uint32_t spi0_mux_clk_cg_en: 1;
+            __IO uint32_t spi0_s_mux_clk_cg_en: 1;
+            __IO uint32_t RESERVED_0: 2;
+        } BITS_310;
+    } u_310;
+
+    /* 0x314        0x4000_2314
+        0       R/W    i2c0_func_en                    1'h0
+        1       R/W    i2c0_ck_en                      1'h0
+        2       R/W    i2c0_div_en                     1'h0
+        5:3     R/W    i2c0_div_sel                    3'b000
+        7:6     R/W    RSVD                            2'h0
+        8       R/W    i2c1_func_en                    1'h0
+        9       R/W    i2c1_ck_en                      1'h0
+        10      R/W    i2c1_div_en                     1'h0
+        13:11   R/W    i2c1_div_sel                    3'b000
+        15:14   R/W    RSVD                            2'h0
+        16      R/W    i2c2_func_en                    1'h0
+        17      R/W    i2c2_ck_en                      1'h0
+        18      R/W    i2c2_div_en                     1'h0
+        21:19   R/W    i2c2_div_sel                    3'b000
+        23:22   R/W    RSVD                            2'h0
+        24      R/W    i2c3_func_en                    1'h0
+        25      R/W    i2c3_ck_en                      1'h0
+        26      R/W    i2c3_div_en                     1'h0
+        29:27   R/W    i2c3_div_sel                    3'b000
+        31:30   R/W    RSVD                            2'h0
+    */
+    union
+    {
+        __IO uint32_t REG_I2C_PERI_CTL0;
+        struct
+        {
+            __IO uint32_t i2c0_func_en: 1;
+            __IO uint32_t i2c0_ck_en: 1;
+            __IO uint32_t i2c0_div_en: 1;
+            __IO uint32_t i2c0_div_sel: 3;
+            __IO uint32_t RESERVED_3: 2;
+            __IO uint32_t i2c1_func_en: 1;
+            __IO uint32_t i2c1_ck_en: 1;
+            __IO uint32_t i2c1_div_en: 1;
+            __IO uint32_t i2c1_div_sel: 3;
+            __IO uint32_t RESERVED_2: 2;
+            __IO uint32_t i2c2_func_en: 1;
+            __IO uint32_t i2c2_ck_en: 1;
+            __IO uint32_t i2c2_div_en: 1;
+            __IO uint32_t i2c2_div_sel: 3;
+            __IO uint32_t RESERVED_1: 2;
+            __IO uint32_t i2c3_func_en: 1;
+            __IO uint32_t i2c3_ck_en: 1;
+            __IO uint32_t i2c3_div_en: 1;
+            __IO uint32_t i2c3_div_sel: 3;
+            __IO uint32_t RESERVED_0: 2;
+        } BITS_314;
+    } u_314;
+
+    /* 0x318        0x4000_2318
+        0       R/W    r_PMUX_1_WIRE_UART0_EN          1'h0
+        1       R/W    rtk_uart0_func_en               1'h0
+        2       R/W    rtk_uart0_ck_en                 1'h0
+        3       R/W    rtk_uart0_div_en                1'h0
+        6:4     R/W    rtk_uart0_div_sel               3'b000
+        7       R/W    RSVD                            1'h0
+        8       R/W    r_PMUX_1_WIRE_UART1_EN          1'h0
+        9       R/W    rtk_uart1_func_en               1'h0
+        10      R/W    rtk_uart1_ck_en                 1'h0
+        11      R/W    rtk_uart1_div_en                1'h0
+        14:12   R/W    rtk_uart1_div_sel               3'b000
+        15      R/W    RSVD                            1'h0
+        16      R/W    r_PMUX_1_WIRE_UART2_EN          1'h0
+        17      R/W    rtk_uart2_func_en               1'h0
+        18      R/W    rtk_uart2_ck_en                 1'h0
+        19      R/W    rtk_uart2_div_en                1'h0
+        22:20   R/W    rtk_uart2_div_sel               3'b000
+        23      R/W    RSVD                            1'h0
+        24      R/W    r_PMUX_1_WIRE_UART3_EN          1'h0
+        25      R/W    rtk_uart3_func_en               1'h0
+        26      R/W    rtk_uart3_ck_en                 1'h0
+        27      R/W    rtk_uart3_div_en                1'h0
+        30:28   R/W    rtk_uart3_div_sel               3'b000
+        31      R/W    RSVD                            1'h0
+    */
+    union
+    {
+        __IO uint32_t REG_UART_PERI_CTL0;
+        struct
+        {
+            __IO uint32_t r_PMUX_1_WIRE_UART0_EN: 1;
+            __IO uint32_t rtk_uart0_func_en: 1;
+            __IO uint32_t rtk_uart0_ck_en: 1;
+            __IO uint32_t rtk_uart0_div_en: 1;
+            __IO uint32_t rtk_uart0_div_sel: 3;
+            __IO uint32_t RESERVED_3: 1;
+            __IO uint32_t r_PMUX_1_WIRE_UART1_EN: 1;
+            __IO uint32_t rtk_uart1_func_en: 1;
+            __IO uint32_t rtk_uart1_ck_en: 1;
+            __IO uint32_t rtk_uart1_div_en: 1;
+            __IO uint32_t rtk_uart1_div_sel: 3;
+            __IO uint32_t RESERVED_2: 1;
+            __IO uint32_t r_PMUX_1_WIRE_UART2_EN: 1;
+            __IO uint32_t rtk_uart2_func_en: 1;
+            __IO uint32_t rtk_uart2_ck_en: 1;
+            __IO uint32_t rtk_uart2_div_en: 1;
+            __IO uint32_t rtk_uart2_div_sel: 3;
+            __IO uint32_t RESERVED_1: 1;
+            __IO uint32_t r_PMUX_1_WIRE_UART3_EN: 1;
+            __IO uint32_t rtk_uart3_func_en: 1;
+            __IO uint32_t rtk_uart3_ck_en: 1;
+            __IO uint32_t rtk_uart3_div_en: 1;
+            __IO uint32_t rtk_uart3_div_sel: 3;
+            __IO uint32_t RESERVED_0: 1;
+        } BITS_318;
+    } u_318;
+
+    /* 0x31C        0x4000_231c
+        0       R/W    auxadc_func_en                  1'h0
+        1       R/W    auxadc_ck_en                    1'h0
+        2       R/W    adc24b_func_en                  1'h0
+        3       R/W    adc24b_ck_en                    1'h0
+        4       R/W    RSVD                            1'h0
+        5       R/W    RSVD                            1'h0
+        6       R/W    keyscan_func_en                 1'h0
+        7       R/W    keyscan_ck_en                   1'h0
+        8       R/W    RSVD                            1'h0
+        9       R/W    RSVD                            1'h0
+        10      R/W    ppe_func_en                     1'h0
+        11      R/W    ppe_ck_en                       1'h0
+        12      R/W    gmac_func_en                    1'h0
+        13      R/W    RSVD                            1'h0
+        14      R/W    spi3w_func_en                   1'h0
+        15      R/W    spi3w_ck_en                     1'h0
+        16      R/W    RSVD                            1'h0
+        17      R/W    RSVD                            1'h0
+        18      R/W    segcom_func_en                  1'h0
+        19      R/W    segcom_ck_en                    1'h0
+        20      R/W    bt_mac_func_en                  1'h1
+        21      R/W    bt_mac_ck_en                    1'h1
+        22      R/W    bt_phy_func_en                  1'h0
+        23      R/W    bt_phy_ck_en                    1'h0
+        24      R/W    zb_mac_func_en                  1'h0
+        25      R/W    zb_mac_ck_en                    1'h0
+        26      R/W    bt_vendor_ck_en                 1'h1
+        27      R/W    bt_cal32k_ck_en                 1'h0
+        28      R/W    pdck_func_en                    1'h0
+        29      R/W    pdck_ck_en                      1'h0
+        30      R/W    aac_xtal_func_en                1'h0
+        31      R/W    aac_xtal_ck_en                  1'h0
+    */
+    union
+    {
+        __IO uint32_t REG_GENERAL_PERI_CTL0;
+        struct
+        {
+            __IO uint32_t auxadc_func_en: 1;
+            __IO uint32_t auxadc_ck_en: 1;
+            __IO uint32_t adc24b_func_en: 1;
+            __IO uint32_t adc24b_ck_en: 1;
+            __IO uint32_t RESERVED_6: 1;
+            __IO uint32_t RESERVED_5: 1;
+            __IO uint32_t keyscan_func_en: 1;
+            __IO uint32_t keyscan_ck_en: 1;
+            __IO uint32_t RESERVED_4: 1;
+            __IO uint32_t RESERVED_3: 1;
+            __IO uint32_t ppe_func_en: 1;
+            __IO uint32_t ppe_ck_en: 1;
+            __IO uint32_t gmac_func_en: 1;
+            __IO uint32_t RESERVED_2: 1;
+            __IO uint32_t spi3w_func_en: 1;
+            __IO uint32_t spi3w_ck_en: 1;
+            __IO uint32_t RESERVED_1: 1;
+            __IO uint32_t RESERVED_0: 1;
+            __IO uint32_t segcom_func_en: 1;
+            __IO uint32_t segcom_ck_en: 1;
+            __IO uint32_t bt_mac_func_en: 1;
+            __IO uint32_t bt_mac_ck_en: 1;
+            __IO uint32_t bt_phy_func_en: 1;
+            __IO uint32_t bt_phy_ck_en: 1;
+            __IO uint32_t zb_mac_func_en: 1;
+            __IO uint32_t zb_mac_ck_en: 1;
+            __IO uint32_t bt_vendor_ck_en: 1;
+            __IO uint32_t bt_cal32k_ck_en: 1;
+            __IO uint32_t pdck_func_en: 1;
+            __IO uint32_t pdck_ck_en: 1;
+            __IO uint32_t aac_xtal_func_en: 1;
+            __IO uint32_t aac_xtal_ck_en: 1;
+        } BITS_31C;
+    } u_31C;
+
+    /* 0x320        0x4000_2320
+        0       R/W    gpio_a_func_en                  1'h0
+        1       R/W    gpio_a_ck_en                    1'h0
+        2       R/W    gpio_a_deb_ck_en                1'h0
+        3       R/W    gpio_a_deb_clk_sel              1'h0
+        4       R/W    gpio_b_func_en                  1'h0
+        5       R/W    gpio_b_ck_en                    1'h0
+        6       R/W    gpio_b_deb_ck_en                1'h0
+        7       R/W    gpio_b_deb_clk_sel              1'h0
+        8       R/W    RSVD                            1'h0
+        9       R/W    simc_ck_en                      1'h0
+        10      R/W    simc_func_en                    1'h0
+        11      R/W    RSVD                            1'h0
+        12      R/W    RSVD                            1'h0
+        13      R/W    RSVD                            1'h0
+        14      R/W    RSVD                            1'h0
+        15      R/W    r_ir_mux_clk_cg_en              1'h0
+        16      R/W    r_pll_ir_div_sel                1'h0
+        17      R/W    r_pll_ir_src_sel                1'h0
+        18      R/W    r_sclk_ir_src_sel               1'h0
+        19      R/W    ir_ck_en                        1'h0
+        20      R/W    ir_func_en                      1'h0
+        22:21   R/W    r_can_lp_scan_div_sel           2'h0
+        23      R/W    r_can_scan_div_sel              1'h0
+        24      R/W    can_ck_en                       1'h0
+        25      R/W    can_func_en                     1'h0
+        29:26   R/W    RSVD                            4'h0
+        30      R/W    RSVD                            1'h0
+        31      R/W    RSVD                            1'h0
+    */
+    union
+    {
+        __IO uint32_t REG_GENERAL_PERI_CTL1;
+        struct
+        {
+            __IO uint32_t gpio_a_func_en: 1;
+            __IO uint32_t gpio_a_ck_en: 1;
+            __IO uint32_t gpio_a_deb_ck_en: 1;
+            __IO uint32_t gpio_a_deb_clk_sel: 1;
+            __IO uint32_t gpio_b_func_en: 1;
+            __IO uint32_t gpio_b_ck_en: 1;
+            __IO uint32_t gpio_b_deb_ck_en: 1;
+            __IO uint32_t gpio_b_deb_clk_sel: 1;
+            __IO uint32_t RESERVED_7: 1;
+            __IO uint32_t simc_ck_en: 1;
+            __IO uint32_t simc_func_en: 1;
+            __IO uint32_t RESERVED_6: 1;
+            __IO uint32_t RESERVED_5: 1;
+            __IO uint32_t RESERVED_4: 1;
+            __IO uint32_t RESERVED_3: 1;
+            __IO uint32_t r_ir_mux_clk_cg_en: 1;
+            __IO uint32_t r_pll_ir_div_sel: 1;
+            __IO uint32_t r_pll_ir_src_sel: 1;
+            __IO uint32_t r_sclk_ir_src_sel: 1;
+            __IO uint32_t ir_ck_en: 1;
+            __IO uint32_t ir_func_en: 1;
+            __IO uint32_t r_can_lp_scan_div_sel: 2;
+            __IO uint32_t r_can_scan_div_sel: 1;
+            __IO uint32_t can_ck_en: 1;
+            __IO uint32_t can_func_en: 1;
+            __IO uint32_t RESERVED_2: 4;
+            __IO uint32_t RESERVED_1: 1;
+            __IO uint32_t RESERVED_0: 1;
+        } BITS_320;
+    } u_320;
+
+    /* 0x324        0x4000_2324
+        2:0     R/W    RSVD                            1'h0
+        3       R/W    RSVD                            1'h0
+        4       R/W    RSVD                            1'h0
+        5       R/W    RSVD                            1'h0
+        6       R/W    RSVD                            1'h0
+        7       R/W    rtzip_ck_en                     1'h0
+        8       R/W    rtzip_func_en                   1'h0
+        15:9    R/W    RSVD                            7'h0
+        18:16   R/W    r_disp_div_sel                  3'h0
+        19      R/W    r_disp_div_en                   1'h0
+        20      R/W    r_disp_mux_clk_cg_en            1'h0
+        21      R/W    r_disp_clk_src_sel1             1'h0
+        22      R/W    r_disp_clk_src_sel0             1'h0
+        23      R/W    disp_ck_en                      1'h0
+        24      R/W    disp_func_en                    1'h0
+        31:25   R/W    RSVD                            7'h0
+    */
+    union
+    {
+        __IO uint32_t REG_GENERAL_PERI_CTL2;
+        struct
+        {
+            __IO uint32_t RESERVED_6: 3;
+            __IO uint32_t RESERVED_5: 1;
+            __IO uint32_t RESERVED_4: 1;
+            __IO uint32_t RESERVED_3: 1;
+            __IO uint32_t RESERVED_2: 1;
+            __IO uint32_t rtzip_ck_en: 1;
+            __IO uint32_t rtzip_func_en: 1;
+            __IO uint32_t RESERVED_1: 7;
+            __IO uint32_t r_disp_div_sel: 3;
+            __IO uint32_t r_disp_div_en: 1;
+            __IO uint32_t r_disp_mux_clk_cg_en: 1;
+            __IO uint32_t r_disp_clk_src_sel1: 1;
+            __IO uint32_t r_disp_clk_src_sel0: 1;
+            __IO uint32_t disp_ck_en: 1;
+            __IO uint32_t disp_func_en: 1;
+            __IO uint32_t RESERVED_0: 7;
+        } BITS_324;
+    } u_324;
+
+    /* 0x328        0x4000_2328
+        2:0     R/W    r_timer_1_div_sel               3'h0
+        3       R/W    r_timer_1_div_en                1'h0
+        4       R/W    RSVD                            1'h0
+        7:5     R/W    RSVD                            3'h0
+        8       R/W    RSVD                            1'h0
+        9       R/W    RSVD                            1'h0
+        10      R/W    RSVD                            1'h0
+        11      R/W    RSVD                            1'h0
+        15:12   R/W    RSVD                            4'h0
+        18:16   R/W    r_timer_2_div_sel               3'h0
+        19      R/W    r_timer_2_div_en                1'h0
+        20      R/W    RSVD                            1'h0
+        23:21   R/W    RSVD                            3'h0
+        24      R/W    RSVD                            1'h0
+        25      R/W    RSVD                            1'h0
+        26      R/W    RSVD                            1'h0
+        27      R/W    RSVD                            1'h0
+        28      R/W    RSVD                            1'h0
+        29      R/W    slv_clk_timer_apb_g             1'h0
+        30      R/W    r_timer_func_en                 1'h0
+        31      R/W    r_timer_ck_en                   1'h0
+    */
+    union
+    {
+        __IO uint32_t REG_TIMER_0_CLOCK_CTRL;
+        struct
+        {
+            __IO uint32_t r_timer_1_div_sel: 3;
+            __IO uint32_t r_timer_1_div_en: 1;
+            __IO uint32_t RESERVED_13: 1;
+            __IO uint32_t RESERVED_12: 3;
+            __IO uint32_t RESERVED_11: 1;
+            __IO uint32_t RESERVED_10: 1;
+            __IO uint32_t RESERVED_9: 1;
+            __IO uint32_t RESERVED_8: 1;
+            __IO uint32_t RESERVED_7: 4;
+            __IO uint32_t r_timer_2_div_sel: 3;
+            __IO uint32_t r_timer_2_div_en: 1;
+            __IO uint32_t RESERVED_6: 1;
+            __IO uint32_t RESERVED_5: 3;
+            __IO uint32_t RESERVED_4: 1;
+            __IO uint32_t RESERVED_3: 1;
+            __IO uint32_t RESERVED_2: 1;
+            __IO uint32_t RESERVED_1: 1;
+            __IO uint32_t RESERVED_0: 1;
+            __IO uint32_t slv_clk_timer_apb_g: 1;
+            __IO uint32_t r_timer_func_en: 1;
+            __IO uint32_t r_timer_ck_en: 1;
+        } BITS_328;
+    } u_328;
+
+    /* 0x32C        0x4000_232c
+        2:0     R/W    r_timer_3_div_sel               3'h0
+        3       R/W    r_timer_3_div_en                1'h0
+        4       R/W    r_timer_3_clk_sel2              1'h0
+        8:5     R/W    RSVD                            4'h0
+        9       R/W    r_timer_pwm_wrap3_clk_sel       1'h0
+        10      R/W    r_timer_pwm_wrap3_func_en       1'h0
+        11      R/W    r_timer_pwm_wrap3_ck_en         1'h0
+        12      R/W    r_timer_3_clk_sel1              1'h0
+        13      R/W    r_timer_3_clk_sel0              1'h0
+        15:14   R/W    RSVD                            2'h0
+        18:16   R/W    r_timer_4_div_sel               3'h0
+        19      R/W    r_timer_4_div_en                1'h0
+        20      R/W    r_timer_4_clk_sel2              1'h0
+        24:21   R/W    RSVD                            4'h0
+        25      R/W    r_timer_pwm_wrap4_clk_sel       1'h0
+        26      R/W    r_timer_pwm_wrap4_func_en       1'h0
+        27      R/W    r_timer_pwm_wrap4_ck_en         1'h0
+        28      R/W    r_timer_4_clk_sel1              1'h0
+        29      R/W    r_timer_4_clk_sel0              1'h0
+        31:30   R/W    RSVD                            2'h0
+    */
+    union
+    {
+        __IO uint32_t REG_TIMER_1_CLOCK_CTRL;
+        struct
+        {
+            __IO uint32_t r_timer_3_div_sel: 3;
+            __IO uint32_t r_timer_3_div_en: 1;
+            __IO uint32_t r_timer_3_clk_sel2: 1;
+            __IO uint32_t RESERVED_3: 4;
+            __IO uint32_t r_timer_pwm_wrap3_clk_sel: 1;
+            __IO uint32_t r_timer_pwm_wrap3_func_en: 1;
+            __IO uint32_t r_timer_pwm_wrap3_ck_en: 1;
+            __IO uint32_t r_timer_3_clk_sel1: 1;
+            __IO uint32_t r_timer_3_clk_sel0: 1;
+            __IO uint32_t RESERVED_2: 2;
+            __IO uint32_t r_timer_4_div_sel: 3;
+            __IO uint32_t r_timer_4_div_en: 1;
+            __IO uint32_t r_timer_4_clk_sel2: 1;
+            __IO uint32_t RESERVED_1: 4;
+            __IO uint32_t r_timer_pwm_wrap4_clk_sel: 1;
+            __IO uint32_t r_timer_pwm_wrap4_func_en: 1;
+            __IO uint32_t r_timer_pwm_wrap4_ck_en: 1;
+            __IO uint32_t r_timer_4_clk_sel1: 1;
+            __IO uint32_t r_timer_4_clk_sel0: 1;
+            __IO uint32_t RESERVED_0: 2;
+        } BITS_32C;
+    } u_32C;
+
+    /* 0x330        0x4000_2330
+        2:0     R/W    r_timer_5_div_sel               3'h0
+        3       R/W    r_timer_5_div_en                1'h0
+        4       R/W    r_timer_5_clk_sel2              1'h0
+        11:5    R/W    RSVD                            7'h0
+        12      R/W    r_timer_5_clk_sel1              1'h0
+        13      R/W    r_timer_5_clk_sel0              1'h0
+        15:14   R/W    RSVD                            2'h0
+        18:16   R/W    r_timer_6_div_sel               3'h0
+        19      R/W    r_timer_6_div_en                1'h0
+        20      R/W    r_timer_6_clk_sel2              1'h0
+        27:21   R/W    RSVD                            7'h0
+        28      R/W    r_timer_6_clk_sel1              1'h0
+        29      R/W    r_timer_6_clk_sel0              1'h0
+        31:30   R/W    RSVD                            2'h0
+    */
+    union
+    {
+        __IO uint32_t REG_TIMER_2_CLOCK_CTRL;
+        struct
+        {
+            __IO uint32_t r_timer_5_div_sel: 3;
+            __IO uint32_t r_timer_5_div_en: 1;
+            __IO uint32_t r_timer_5_clk_sel2: 1;
+            __IO uint32_t RESERVED_3: 7;
+            __IO uint32_t r_timer_5_clk_sel1: 1;
+            __IO uint32_t r_timer_5_clk_sel0: 1;
+            __IO uint32_t RESERVED_2: 2;
+            __IO uint32_t r_timer_6_div_sel: 3;
+            __IO uint32_t r_timer_6_div_en: 1;
+            __IO uint32_t r_timer_6_clk_sel2: 1;
+            __IO uint32_t RESERVED_1: 7;
+            __IO uint32_t r_timer_6_clk_sel1: 1;
+            __IO uint32_t r_timer_6_clk_sel0: 1;
+            __IO uint32_t RESERVED_0: 2;
+        } BITS_330;
+    } u_330;
+
+    /* 0x334        0x4000_2334
+        2:0     R/W    r_timer_7_div_sel               3'h0
+        3       R/W    r_timer_7_div_en                1'h0
+        4       R/W    r_timer_7_clk_sel2              1'h0
+        11:5    R/W    RSVD                            7'h0
+        12      R/W    r_timer_7_clk_sel1              1'h0
+        13      R/W    r_timer_7_clk_sel0              1'h0
+        15:14   R/W    RSVD                            2'h0
+        18:16   R/W    r_timer_8_div_sel               3'h0
+        19      R/W    r_timer_8_div_en                1'h0
+        20      R/W    r_timer_8_clk_sel2              1'h0
+        27:21   R/W    RSVD                            7'h0
+        28      R/W    r_timer_8_clk_sel1              1'h0
+        29      R/W    r_timer_8_clk_sel0              1'h0
+        31:30   R/W    RSVD                            2'h0
+    */
+    union
+    {
+        __IO uint32_t REG_TIMER_3_CLOCK_CTRL;
+        struct
+        {
+            __IO uint32_t r_timer_7_div_sel: 3;
+            __IO uint32_t r_timer_7_div_en: 1;
+            __IO uint32_t r_timer_7_clk_sel2: 1;
+            __IO uint32_t RESERVED_3: 7;
+            __IO uint32_t r_timer_7_clk_sel1: 1;
+            __IO uint32_t r_timer_7_clk_sel0: 1;
+            __IO uint32_t RESERVED_2: 2;
+            __IO uint32_t r_timer_8_div_sel: 3;
+            __IO uint32_t r_timer_8_div_en: 1;
+            __IO uint32_t r_timer_8_clk_sel2: 1;
+            __IO uint32_t RESERVED_1: 7;
+            __IO uint32_t r_timer_8_clk_sel1: 1;
+            __IO uint32_t r_timer_8_clk_sel0: 1;
+            __IO uint32_t RESERVED_0: 2;
+        } BITS_334;
+    } u_334;
+
+    /* 0x338        0x4000_2338
+        31:0    R/W    RSVD                           32'h0
+    */
+    union
+    {
+        __IO uint32_t REG_TIMER_PWM_WRAP_0_CFG;
+        struct
+        {
+            __IO uint32_t RESERVED_0: 32;
+        } BITS_338;
+    } u_338;
+
+    /* 0x33C        0x4000_233c
+        7:0     R/W    timer_pwm_3_dead_zone_size      8'h0
+        8       R/W    timer_pwm_3_emg_stop            1'h0
+        9       R/W    timer_pwm_3_stop_state[0]       1'h0
+        10      R/W    timer_pwm_3_stop_state[1]       1'h0
+        11      R/W    timer_pwm_3_dummy_b11           1'h0
+        12      R/W    timer_pwm_3_dead_zone_en        1'h0
+        13      R/W    timer_pwm_3_pwm_pn_invserse_sel 1'h0
+        14      R/W    timer_pwm_3_dummy_b14           1'h0
+        15      R/W    timer_pwm_3_dummy_b15           1'h0
+        23:16   R/W    timer_pwm_4_dead_zone_size      8'h0
+        24      R/W    timer_pwm_4_emg_stop            1'h0
+        25      R/W    timer_pwm_4_stop_state[0]       1'h0
+        26      R/W    timer_pwm_4_stop_state[1]       1'h0
+        27      R/W    timer_pwm_4_dummy_b11           1'h0
+        28      R/W    timer_pwm_4_dead_zone_en        1'h0
+        29      R/W    timer_pwm_4_pwm_pn_invserse_sel 1'h0
+        30      R/W    timer_pwm_4_dummy_b14           1'h0
+        31      R/W    timer_pwm_4_dummy_b15           1'h0
+    */
+    union
+    {
+        __IO uint32_t REG_TIMER_PWM_WRAP_1_CFG;
+        struct
+        {
+            __IO uint32_t timer_pwm_3_dead_zone_size: 8;
+            __IO uint32_t timer_pwm_3_emg_stop: 1;
+            __IO uint32_t timer_pwm_3_stop_state_0: 1;
+            __IO uint32_t timer_pwm_3_stop_state_1: 1;
+            __IO uint32_t timer_pwm_3_dummy_b11: 1;
+            __IO uint32_t timer_pwm_3_dead_zone_en: 1;
+            __IO uint32_t timer_pwm_3_pwm_pn_invserse_sel: 1;
+            __IO uint32_t timer_pwm_3_dummy_b14: 1;
+            __IO uint32_t timer_pwm_3_dummy_b15: 1;
+            __IO uint32_t timer_pwm_4_dead_zone_size: 8;
+            __IO uint32_t timer_pwm_4_emg_stop: 1;
+            __IO uint32_t timer_pwm_4_stop_state_0: 1;
+            __IO uint32_t timer_pwm_4_stop_state_1: 1;
+            __IO uint32_t timer_pwm_4_dummy_b11: 1;
+            __IO uint32_t timer_pwm_4_dead_zone_en: 1;
+            __IO uint32_t timer_pwm_4_pwm_pn_invserse_sel: 1;
+            __IO uint32_t timer_pwm_4_dummy_b14: 1;
+            __IO uint32_t timer_pwm_4_dummy_b15: 1;
+        } BITS_33C;
+    } u_33C;
+
+    /* 0x340        0x4000_2340
+        31:0    R/W    RSVD                            32'h0
+    */
+    union
+    {
+        __IO uint32_t REG_TIMER_PWM_WRAP_2_CFG;
+        struct
+        {
+            __IO uint32_t RESERVED_0: 32;
+        } BITS_340;
+    } u_340;
+
+    /* 0x344        0x4000_2344
+        2:0     R/W    r_etimer_0_div_sel              3'h0
+        3       R/W    r_etimer_0_div_en               1'h0
+        4       R/W    r_etimer_01_clk_src_sel2        1'h0
+        5       R/W    r_etimer_01_clk_src_sel1        1'h0
+        6       R/W    r_etimer_01_clk_src_sel0        1'h0
+        9:7     R/W    r_etimer_pwm_0_div_sel          3'h0
+        10      R/W    r_etimer_pwm_0_div_en           1'h0
+        11      R/W    r_etimer_pwm_0_clk_src_sel      1'h0
+        12      R/W    r_etimer_pwm_0_func_en          1'h0
+        13      R/W    r_etimer_pwm_0_ck_en            1'h0
+        15:14   R/W    RSVD                            2'h0
+        18:16   R/W    r_etimer_1_div_sel              3'h0
+        19      R/W    r_etimer_1_div_en               1'h0
+        22:20   R/W    RSVD                            3'h0
+        25:23   R/W    r_etimer_pwm_1_div_sel          3'h0
+        26      R/W    r_etimer_pwm_1_div_en           1'h0
+        27      R/W    r_etimer_pwm_1_clk_src_sel      1'h0
+        28      R/W    r_etimer_pwm_1_func_en          1'h0
+        29      R/W    r_etimer_pwm_1_ck_en            1'h0
+        30      R/W    r_etimer_func_en                1'h0
+        31      R/W    r_etimer_ck_en                  1'h0
+    */
+    union
+    {
+        __IO uint32_t REG_ENHTIMER_1_0_CLOCK_CTRL;
+        struct
+        {
+            __IO uint32_t r_etimer_0_div_sel: 3;
+            __IO uint32_t r_etimer_0_div_en: 1;
+            __IO uint32_t r_etimer_01_clk_src_sel2: 1;
+            __IO uint32_t r_etimer_01_clk_src_sel1: 1;
+            __IO uint32_t r_etimer_01_clk_src_sel0: 1;
+            __IO uint32_t r_etimer_pwm_0_div_sel: 3;
+            __IO uint32_t r_etimer_pwm_0_div_en: 1;
+            __IO uint32_t r_etimer_pwm_0_clk_src_sel: 1;
+            __IO uint32_t r_etimer_pwm_0_func_en: 1;
+            __IO uint32_t r_etimer_pwm_0_ck_en: 1;
+            __IO uint32_t RESERVED_1: 2;
+            __IO uint32_t r_etimer_1_div_sel: 3;
+            __IO uint32_t r_etimer_1_div_en: 1;
+            __IO uint32_t RESERVED_0: 3;
+            __IO uint32_t r_etimer_pwm_1_div_sel: 3;
+            __IO uint32_t r_etimer_pwm_1_div_en: 1;
+            __IO uint32_t r_etimer_pwm_1_clk_src_sel: 1;
+            __IO uint32_t r_etimer_pwm_1_func_en: 1;
+            __IO uint32_t r_etimer_pwm_1_ck_en: 1;
+            __IO uint32_t r_etimer_func_en: 1;
+            __IO uint32_t r_etimer_ck_en: 1;
+        } BITS_344;
+    } u_344;
+
+    /* 0x348        0x4000_2348
+        2:0     R/W    r_etimer_2_div_sel              3'h0
+        3       R/W    r_etimer_2_div_en               1'h0
+        4       R/W    r_etimer_23_clk_src_sel2        1'h0
+        5       R/W    r_etimer_23_clk_src_sel1        1'h0
+        6       R/W    r_etimer_23_clk_src_sel0        1'h0
+        9:7     R/W    r_etimer_pwm_2_div_sel          3'h0
+        10      R/W    r_etimer_pwm_2_div_en           1'h0
+        11      R/W    r_etimer_pwm_2_clk_src_sel      1'h0
+        12      R/W    r_etimer_pwm_2_func_en          1'h0
+        13      R/W    r_etimer_pwm_2_ck_en            1'h0
+        15:14   R/W    RSVD                            2'h0
+        18:16   R/W    r_etimer_3_div_sel              3'h0
+        19      R/W    r_etimer_3_div_en               1'h0
+        22:20   R/W    RSVD                            3'h0
+        25:23   R/W    r_etimer_pwm_3_div_sel          3'h0
+        26      R/W    r_etimer_pwm_3_div_en           1'h0
+        27      R/W    r_etimer_pwm_3_clk_src_sel      1'h0
+        28      R/W    r_etimer_pwm_3_func_en          1'h0
+        29      R/W    r_etimer_pwm_3_ck_en            1'h0
+        31:30   R/W    RSVD                            2'h0
+    */
+    union
+    {
+        __IO uint32_t REG_ENHTIMER_3_2_CLOCK_CTRL;
+        struct
+        {
+            __IO uint32_t r_etimer_2_div_sel: 3;
+            __IO uint32_t r_etimer_2_div_en: 1;
+            __IO uint32_t r_etimer_23_clk_src_sel2: 1;
+            __IO uint32_t r_etimer_23_clk_src_sel1: 1;
+            __IO uint32_t r_etimer_23_clk_src_sel0: 1;
+            __IO uint32_t r_etimer_pwm_2_div_sel: 3;
+            __IO uint32_t r_etimer_pwm_2_div_en: 1;
+            __IO uint32_t r_etimer_pwm_2_clk_src_sel: 1;
+            __IO uint32_t r_etimer_pwm_2_func_en: 1;
+            __IO uint32_t r_etimer_pwm_2_ck_en: 1;
+            __IO uint32_t RESERVED_2: 2;
+            __IO uint32_t r_etimer_3_div_sel: 3;
+            __IO uint32_t r_etimer_3_div_en: 1;
+            __IO uint32_t RESERVED_1: 3;
+            __IO uint32_t r_etimer_pwm_3_div_sel: 3;
+            __IO uint32_t r_etimer_pwm_3_div_en: 1;
+            __IO uint32_t r_etimer_pwm_3_clk_src_sel: 1;
+            __IO uint32_t r_etimer_pwm_3_func_en: 1;
+            __IO uint32_t r_etimer_pwm_3_ck_en: 1;
+            __IO uint32_t RESERVED_0: 2;
+        } BITS_348;
+    } u_348;
+
+    /* 0x34C        0x4000_234c
+        7:0     R/W    GPIOA_G0_CNT_LIMIT              8'h1
+        8       R/W    GPIOA_G0_DEB_CLK_SEL            1'h0
+        11:9    R/W    GPIOA_G0_DEB_CLK_DIV            3'h0
+        12      R/W    GPIOA_G0_DEB_CNT_EN             1'b0
+        15:13   R/W    RSVD                            3'h0
+        23:16   R/W    GPIOA_G1_CNT_LIMIT              8'h1
+        24      R/W    GPIOA_G1_DEB_CLK_SEL            1'h0
+        27:25   R/W    GPIOA_G1_DEB_CLK_DIV            3'h0
+        28      R/W    GPIOA_G1_DEB_CNT_EN             1'b0
+        31:29   R/W    RSVD                            3'h0
+    */
+    union
+    {
+        __IO uint32_t GPIOA_DEB_CLK_CTL_0;
+        struct
+        {
+            __IO uint32_t GPIOA_G0_CNT_LIMIT: 8;
+            __IO uint32_t GPIOA_G0_DEB_CLK_SEL: 1;
+            __IO uint32_t GPIOA_G0_DEB_CLK_DIV: 3;
+            __IO uint32_t GPIOA_G0_DEB_CNT_EN: 1;
+            __IO uint32_t RESERVED_1: 3;
+            __IO uint32_t GPIOA_G1_CNT_LIMIT: 8;
+            __IO uint32_t GPIOA_G1_DEB_CLK_SEL: 1;
+            __IO uint32_t GPIOA_G1_DEB_CLK_DIV: 3;
+            __IO uint32_t GPIOA_G1_DEB_CNT_EN: 1;
+            __IO uint32_t RESERVED_0: 3;
+        } BITS_34C;
+    } u_34C;
+
+    /* 0x350        0x4000_2350
+        7:0     R/W    GPIOA_G2_CNT_LIMIT              8'h1
+        8       R/W    GPIOA_G2_DEB_CLK_SEL            1'h0
+        11:9    R/W    GPIOA_G2_DEB_CLK_DIV            3'h0
+        12      R/W    GPIOA_G2_DEB_CNT_EN             1'b0
+        15:13   R/W    RSVD                            3'h0
+        23:16   R/W    GPIOA_G3_CNT_LIMIT              8'h1
+        24      R/W    GPIOA_G3_DEB_CLK_SEL            1'h0
+        27:25   R/W    GPIOA_G3_DEB_CLK_DIV            3'h0
+        28      R/W    GPIOA_G3_DEB_CNT_EN             1'b0
+        31:29   R/W    RSVD                            3'h0
+    */
+    union
+    {
+        __IO uint32_t GPIOA_DEB_CLK_CTL_1;
+        struct
+        {
+            __IO uint32_t GPIOA_G2_CNT_LIMIT: 8;
+            __IO uint32_t GPIOA_G2_DEB_CLK_SEL: 1;
+            __IO uint32_t GPIOA_G2_DEB_CLK_DIV: 3;
+            __IO uint32_t GPIOA_G2_DEB_CNT_EN: 1;
+            __IO uint32_t RESERVED_1: 3;
+            __IO uint32_t GPIOA_G3_CNT_LIMIT: 8;
+            __IO uint32_t GPIOA_G3_DEB_CLK_SEL: 1;
+            __IO uint32_t GPIOA_G3_DEB_CLK_DIV: 3;
+            __IO uint32_t GPIOA_G3_DEB_CNT_EN: 1;
+            __IO uint32_t RESERVED_0: 3;
+        } BITS_350;
+    } u_350;
+
+    /* 0x354        0x4000_2354
+        7:0     R/W    GPIOA_G4_CNT_LIMIT              8'h1
+        8       R/W    GPIOA_G4_DEB_CLK_SEL            1'h0
+        11:9    R/W    GPIOA_G4_DEB_CLK_DIV            3'h0
+        12      R/W    GPIOA_G4_DEB_CNT_EN             1'b0
+        15:13   R/W    RSVD                            3'h0
+        23:16   R/W    GPIOA_G5_CNT_LIMIT              8'h1
+        24      R/W    GPIOA_G5_DEB_CLK_SEL            1'h0
+        27:25   R/W    GPIOA_G5_DEB_CLK_DIV            3'h0
+        28      R/W    GPIOA_G5_DEB_CNT_EN             1'b0
+        31:29   R/W    RSVD                            3'h0
+    */
+    union
+    {
+        __IO uint32_t GPIOA_DEB_CLK_CTL_2;
+        struct
+        {
+            __IO uint32_t GPIOA_G4_CNT_LIMIT: 8;
+            __IO uint32_t GPIOA_G4_DEB_CLK_SEL: 1;
+            __IO uint32_t GPIOA_G4_DEB_CLK_DIV: 3;
+            __IO uint32_t GPIOA_G4_DEB_CNT_EN: 1;
+            __IO uint32_t RESERVED_1: 3;
+            __IO uint32_t GPIOA_G5_CNT_LIMIT: 8;
+            __IO uint32_t GPIOA_G5_DEB_CLK_SEL: 1;
+            __IO uint32_t GPIOA_G5_DEB_CLK_DIV: 3;
+            __IO uint32_t GPIOA_G5_DEB_CNT_EN: 1;
+            __IO uint32_t RESERVED_0: 3;
+        } BITS_354;
+    } u_354;
+
+    /* 0x358        0x4000_2358
+        7:0     R/W    GPIOA_G6_CNT_LIMIT              8'h1
+        8       R/W    GPIOA_G6_DEB_CLK_SEL            1'h0
+        11:9    R/W    GPIOA_G6_DEB_CLK_DIV            3'h0
+        12      R/W    GPIOA_G6_DEB_CNT_EN             1'b0
+        15:13   R/W    RSVD                            3'h0
+        23:16   R/W    GPIOA_G7_CNT_LIMIT              8'h1
+        24      R/W    GPIOA_G7_DEB_CLK_SEL            1'h0
+        27:25   R/W    GPIOA_G7_DEB_CLK_DIV            3'h0
+        28      R/W    GPIOA_G7_DEB_CNT_EN             1'b0
+        31:29   R/W    RSVD                            3'h0
+    */
+    union
+    {
+        __IO uint32_t GPIOA_DEB_CLK_CTL_3;
+        struct
+        {
+            __IO uint32_t GPIOA_G6_CNT_LIMIT: 8;
+            __IO uint32_t GPIOA_G6_DEB_CLK_SEL: 1;
+            __IO uint32_t GPIOA_G6_DEB_CLK_DIV: 3;
+            __IO uint32_t GPIOA_G6_DEB_CNT_EN: 1;
+            __IO uint32_t RESERVED_1: 3;
+            __IO uint32_t GPIOA_G7_CNT_LIMIT: 8;
+            __IO uint32_t GPIOA_G7_DEB_CLK_SEL: 1;
+            __IO uint32_t GPIOA_G7_DEB_CLK_DIV: 3;
+            __IO uint32_t GPIOA_G7_DEB_CNT_EN: 1;
+            __IO uint32_t RESERVED_0: 3;
+        } BITS_358;
+    } u_358;
+
+    /* 0x35C        0x4000_235c
+        31:0    R/W    GPIOA_x_DEB_FUNC_EN             32'h0
+    */
+    union
+    {
+        __IO uint32_t GPIOA_DEB_FUN_CTL;
+        struct
+        {
+            __IO uint32_t GPIOA_x_DEB_FUNC_EN: 32;
+        } BITS_35C;
+    } u_35C;
+
+    /* 0x360        0x4000_2360
+        7:0     R/W    GPIOB_G0_CNT_LIMIT              8'h1
+        8       R/W    GPIOB_G0_DEB_CLK_SEL            1'h0
+        11:9    R/W    GPIOB_G0_DEB_CLK_DIV            3'h0
+        12      R/W    GPIOB_G0_DEB_CNT_EN             1'b0
+        15:13   R/W    RSVD                            3'h0
+        23:16   R/W    GPIOB_G1_CNT_LIMIT              8'h1
+        24      R/W    GPIOB_G1_DEB_CLK_SEL            1'h0
+        27:25   R/W    GPIOB_G1_DEB_CLK_DIV            3'h0
+        28      R/W    GPIOB_G1_DEB_CNT_EN             1'b0
+        31:29   R/W    RSVD                            3'h0
+    */
+    union
+    {
+        __IO uint32_t GPIOB_DEB_CLK_CTL_0;
+        struct
+        {
+            __IO uint32_t GPIOB_G0_CNT_LIMIT: 8;
+            __IO uint32_t GPIOB_G0_DEB_CLK_SEL: 1;
+            __IO uint32_t GPIOB_G0_DEB_CLK_DIV: 3;
+            __IO uint32_t GPIOB_G0_DEB_CNT_EN: 1;
+            __IO uint32_t RESERVED_1: 3;
+            __IO uint32_t GPIOB_G1_CNT_LIMIT: 8;
+            __IO uint32_t GPIOB_G1_DEB_CLK_SEL: 1;
+            __IO uint32_t GPIOB_G1_DEB_CLK_DIV: 3;
+            __IO uint32_t GPIOB_G1_DEB_CNT_EN: 1;
+            __IO uint32_t RESERVED_0: 3;
+        } BITS_360;
+    } u_360;
+
+    /* 0x364        0x4000_2364
+        7:0     R/W    GPIOB_G2_CNT_LIMIT              8'h1
+        8       R/W    GPIOB_G2_DEB_CLK_SEL            1'h0
+        11:9    R/W    GPIOB_G2_DEB_CLK_DIV            3'h0
+        12      R/W    GPIOB_G2_DEB_CNT_EN             1'b0
+        15:13   R/W    RSVD                            3'h0
+        23:16   R/W    GPIOB_G3_CNT_LIMIT              8'h1
+        24      R/W    GPIOB_G3_DEB_CLK_SEL            1'h0
+        27:25   R/W    GPIOB_G3_DEB_CLK_DIV            3'h0
+        28      R/W    GPIOB_G3_DEB_CNT_EN             1'b0
+        31:29   R/W    RSVD                            3'h0
+    */
+    union
+    {
+        __IO uint32_t GPIOB_DEB_CLK_CTL_1;
+        struct
+        {
+            __IO uint32_t GPIOB_G2_CNT_LIMIT: 8;
+            __IO uint32_t GPIOB_G2_DEB_CLK_SEL: 1;
+            __IO uint32_t GPIOB_G2_DEB_CLK_DIV: 3;
+            __IO uint32_t GPIOB_G2_DEB_CNT_EN: 1;
+            __IO uint32_t RESERVED_1: 3;
+            __IO uint32_t GPIOB_G3_CNT_LIMIT: 8;
+            __IO uint32_t GPIOB_G3_DEB_CLK_SEL: 1;
+            __IO uint32_t GPIOB_G3_DEB_CLK_DIV: 3;
+            __IO uint32_t GPIOB_G3_DEB_CNT_EN: 1;
+            __IO uint32_t RESERVED_0: 3;
+        } BITS_364;
+    } u_364;
+
+    /* 0x368        0x4000_2368
+        7:0     R/W    GPIOB_G4_CNT_LIMIT              8'h1
+        8       R/W    GPIOB_G4_DEB_CLK_SEL            1'h0
+        11:9    R/W    GPIOB_G4_DEB_CLK_DIV            3'h0
+        12      R/W    GPIOB_G4_DEB_CNT_EN             1'b0
+        15:13   R/W    RSVD                            3'h0
+        23:16   R/W    GPIOB_G5_CNT_LIMIT              8'h1
+        24      R/W    GPIOB_G5_DEB_CLK_SEL            1'h0
+        27:25   R/W    GPIOB_G5_DEB_CLK_DIV            3'h0
+        28      R/W    GPIOB_G5_DEB_CNT_EN             1'b0
+        31:29   R/W    RSVD                            3'h0
+    */
+    union
+    {
+        __IO uint32_t GPIOB_DEB_CLK_CTL_2;
+        struct
+        {
+            __IO uint32_t GPIOB_G4_CNT_LIMIT: 8;
+            __IO uint32_t GPIOB_G4_DEB_CLK_SEL: 1;
+            __IO uint32_t GPIOB_G4_DEB_CLK_DIV: 3;
+            __IO uint32_t GPIOB_G4_DEB_CNT_EN: 1;
+            __IO uint32_t RESERVED_1: 3;
+            __IO uint32_t GPIOB_G5_CNT_LIMIT: 8;
+            __IO uint32_t GPIOB_G5_DEB_CLK_SEL: 1;
+            __IO uint32_t GPIOB_G5_DEB_CLK_DIV: 3;
+            __IO uint32_t GPIOB_G5_DEB_CNT_EN: 1;
+            __IO uint32_t RESERVED_0: 3;
+        } BITS_368;
+    } u_368;
+
+    /* 0x36C        0x4000_236c
+        7:0     R/W    GPIOB_G6_CNT_LIMIT              8'h1
+        8       R/W    GPIOB_G6_DEB_CLK_SEL            1'h0
+        11:9    R/W    GPIOB_G6_DEB_CLK_DIV            3'h0
+        12      R/W    GPIOB_G6_DEB_CNT_EN             1'b0
+        15:13   R/W    RSVD                            3'h0
+        23:16   R/W    GPIOB_G7_CNT_LIMIT              8'h1
+        24      R/W    GPIOB_G7_DEB_CLK_SEL            1'h0
+        27:25   R/W    GPIOB_G7_DEB_CLK_DIV            3'h0
+        28      R/W    GPIOB_G7_DEB_CNT_EN             1'b0
+        31:29   R/W    RSVD                            3'h0
+    */
+    union
+    {
+        __IO uint32_t GPIOB_DEB_CLK_CTL_3;
+        struct
+        {
+            __IO uint32_t GPIOB_G6_CNT_LIMIT: 8;
+            __IO uint32_t GPIOB_G6_DEB_CLK_SEL: 1;
+            __IO uint32_t GPIOB_G6_DEB_CLK_DIV: 3;
+            __IO uint32_t GPIOB_G6_DEB_CNT_EN: 1;
+            __IO uint32_t RESERVED_1: 3;
+            __IO uint32_t GPIOB_G7_CNT_LIMIT: 8;
+            __IO uint32_t GPIOB_G7_DEB_CLK_SEL: 1;
+            __IO uint32_t GPIOB_G7_DEB_CLK_DIV: 3;
+            __IO uint32_t GPIOB_G7_DEB_CNT_EN: 1;
+            __IO uint32_t RESERVED_0: 3;
+        } BITS_36C;
+    } u_36C;
+
+    /* 0x370        0x4000_2370
+        31:0    R/W    GPIOB_x_DEB_FUNC_EN             32'h0
+    */
+    union
+    {
+        __IO uint32_t GPIOB_DEB_FUN_CTL;
+        struct
+        {
+            __IO uint32_t GPIOB_x_DEB_FUNC_EN: 32;
+        } BITS_370;
+    } u_370;
+
+    /* 0x374        0x4000_2374
+        0       R/W    sdio_ck_en                      1'h0
+        1       R/W    sdio_func_en                    1'h0
+        2       R/W    r_sdio_clk_src_en               1'h0
+        6:3     R/W    r_sdio_div_sel                  4'h0
+        7       R/W    r_sdio_div_en                   1'h0
+        8       R/W    r_sdio_mux_clk_cg_en            1'h0
+        9       R/W    r_sdio_clk_src_sel1             1'h0
+        10      R/W    r_sdio_clk_src_sel0             1'h0
+        31:11   R/W    RSVD                            21'h0
+    */
+    union
+    {
+        __IO uint32_t REG_SDH_CTL;
+        struct
+        {
+            __IO uint32_t sdio_ck_en: 1;
+            __IO uint32_t sdio_func_en: 1;
+            __IO uint32_t r_sdio_clk_src_en: 1;
+            __IO uint32_t r_sdio_div_sel: 4;
+            __IO uint32_t r_sdio_div_en: 1;
+            __IO uint32_t r_sdio_mux_clk_cg_en: 1;
+            __IO uint32_t r_sdio_clk_src_sel1: 1;
+            __IO uint32_t r_sdio_clk_src_sel0: 1;
+            __IO uint32_t RESERVED_0: 21;
+        } BITS_374;
+    } u_374;
+
+    /* 0x378        0x4000_2378
+        7:0     R/W    r_sdh_drv_dly_sel               8'h0
+        15:8    R/W    r_sdh_sample_dly_sel            8'h0
+        17:16   R/W    r_sdh_clk_sel_drv               2'h0
+        19:18   R/W    r_sdh_clk_sel_sample            2'h0
+        20      R/W    r_sdh_bypass_shift_drv          1'h0
+        21      R/W    r_sdh_bypass_shift_sample       1'h0
+        22      R/W    r_sdh_bypass_delay_drv          1'h0
+        23      R/W    r_sdh_bypass_delay_sample       1'h0
+        31:24   R/W    r_sdh_clk_out_dly_sel           8'h0
+    */
+    union
+    {
+        __IO uint32_t REG_SDH_PHY0;
+        struct
+        {
+            __IO uint32_t r_sdh_drv_dly_sel: 8;
+            __IO uint32_t r_sdh_sample_dly_sel: 8;
+            __IO uint32_t r_sdh_clk_sel_drv: 2;
+            __IO uint32_t r_sdh_clk_sel_sample: 2;
+            __IO uint32_t r_sdh_bypass_shift_drv: 1;
+            __IO uint32_t r_sdh_bypass_shift_sample: 1;
+            __IO uint32_t r_sdh_bypass_delay_drv: 1;
+            __IO uint32_t r_sdh_bypass_delay_sample: 1;
+            __IO uint32_t r_sdh_clk_out_dly_sel: 8;
+        } BITS_378;
+    } u_378;
+
+    /* 0x37C        0x4000_237c
+        7:0     R/W    r_sdh_cmd_out_dly_sel           8'h0
+        15:8    R/W    r_sdh_dat0_dly_sel              8'h0
+        23:16   R/W    r_sdh_dat1_dly_sel              8'h0
+        31:24   R/W    r_sdh_dat2_dly_sel              8'h0
+    */
+    union
+    {
+        __IO uint32_t REG_SDH_PHY1;
+        struct
+        {
+            __IO uint32_t r_sdh_cmd_out_dly_sel: 8;
+            __IO uint32_t r_sdh_dat0_dly_sel: 8;
+            __IO uint32_t r_sdh_dat1_dly_sel: 8;
+            __IO uint32_t r_sdh_dat2_dly_sel: 8;
+        } BITS_37C;
+    } u_37C;
+
+    /* 0x380        0x4000_2380
+        7:0     R/W    r_sdh_dat3_dly_sel              8'h0
+        15:8    R/W    r_sdh_dat4_dly_sel              8'h0
+        23:16   R/W    r_sdh_dat5_dly_sel              8'h0
+        31:24   R/W    r_sdh_dat6_dly_sel              8'h0
+    */
+    union
+    {
+        __IO uint32_t REG_SDH_PHY2;
+        struct
+        {
+            __IO uint32_t r_sdh_dat3_dly_sel: 8;
+            __IO uint32_t r_sdh_dat4_dly_sel: 8;
+            __IO uint32_t r_sdh_dat5_dly_sel: 8;
+            __IO uint32_t r_sdh_dat6_dly_sel: 8;
+        } BITS_380;
+    } u_380;
+
+    /* 0x384        0x4000_2384
+        7:0     R/W    r_sdh_dat7_dly_sel              8'h0
+        19:8    R/W    r_sdh_dbg_sel                   12'h0
+        21:20   R/W    r_sdh_dbg_en_i                  2'h0
+        22      R/W    r_sdh_cclk_in_drv               1'h0
+        23      R/W    r_sdh_cclk_sample_drv           1'h0
+        24      R/W    r_sdh_cclk_in_div_enable        1'h1
+        31:25   R/W    RSVD                            7'h0
+    */
+    union
+    {
+        __IO uint32_t REG_SDH_PHY3;
+        struct
+        {
+            __IO uint32_t r_sdh_dat7_dly_sel: 8;
+            __IO uint32_t r_sdh_dbg_sel: 12;
+            __IO uint32_t r_sdh_dbg_en_i: 2;
+            __IO uint32_t r_sdh_cclk_in_drv: 1;
+            __IO uint32_t r_sdh_cclk_sample_drv: 1;
+            __IO uint32_t r_sdh_cclk_in_div_enable: 1;
+            __IO uint32_t RESERVED_0: 7;
+        } BITS_384;
+    } u_384;
+
+    /* 0x388        0x4000_2388
+        5:0     R/W    r_bt_ahb_wait_cnt               6'hC
+        31:6    R/W    RSVD                            26'h0
+    */
+    union
+    {
+        __IO uint32_t REG_BT_MISC;
+        struct
+        {
+            __IO uint32_t r_bt_ahb_wait_cnt: 6;
+            __IO uint32_t RESERVED_0: 26;
+        } BITS_388;
+    } u_388;
+
+    /* 0x38C        0x4000_238c
+        0       R/W    r_PMUX_1_WIRE_UART4_EN          1'h0
+        1       R/W    rtk_uart4_func_en               1'h0
+        2       R/W    rtk_uart4_ck_en                 1'h0
+        3       R/W    rtk_uart4_div_en                1'h0
+        6:4     R/W    rtk_uart4_div_sel               3'b000
+        7       R/W    RSVD                            1'h0
+        8       R/W    r_PMUX_1_WIRE_UART5_EN          1'h0
+        9       R/W    rtk_uart5_func_en               1'h0
+        10      R/W    rtk_uart5_ck_en                 1'h0
+        11      R/W    rtk_uart5_div_en                1'h0
+        14:12   R/W    rtk_uart5_div_sel               3'b000
+        31:15   R/W    RSVD                            17'h0
+    */
+    union
+    {
+        __IO uint32_t REG_UART_PERI_CTL1;
+        struct
+        {
+            __IO uint32_t r_PMUX_1_WIRE_UART4_EN: 1;
+            __IO uint32_t rtk_uart4_func_en: 1;
+            __IO uint32_t rtk_uart4_ck_en: 1;
+            __IO uint32_t rtk_uart4_div_en: 1;
+            __IO uint32_t rtk_uart4_div_sel: 3;
+            __IO uint32_t RESERVED_13: 1;
+            __IO uint32_t r_PMUX_1_WIRE_UART5_EN: 1;
+            __IO uint32_t rtk_uart5_func_en: 1;
+            __IO uint32_t rtk_uart5_ck_en: 1;
+            __IO uint32_t rtk_uart5_div_en: 1;
+            __IO uint32_t rtk_uart5_div_sel: 3;
+            __IO uint32_t RESERVED_0: 17;
+        } BITS_38C;
+    } u_38C;
+
+    /* 0x390        0x4000_2390
+        1:0     R/W    GMAC_LX_BUS_TIMEOUT_THRESHOLD   2'h0
+        2       R/W    GMAC_LX_BUS_TIMEOUT_EN          1'h0
+        3       R/W    GMAC_LX_BUS_DMA_LOCK_IN         1'h0
+        5:4     R/W    GMAC_MII_LX_TIMEOUT_THRESHOLD   2'h0
+        6       R/W    GMAC_MII_LX_TIMEOUT_EN          1'h0
+        31:7    R/W    RSVD                            25'b0
+    */
+    union
+    {
+        __IO uint32_t REG_GMAC_BUS;
+        struct
+        {
+            __IO uint32_t GMAC_LX_BUS_TIMEOUT_THRESHOLD: 2;
+            __IO uint32_t GMAC_LX_BUS_TIMEOUT_EN: 1;
+            __IO uint32_t GMAC_LX_BUS_DMA_LOCK_IN: 1;
+            __IO uint32_t GMAC_MII_LX_TIMEOUT_THRESHOLD: 2;
+            __IO uint32_t GMAC_MII_LX_TIMEOUT_EN: 1;
+            __IO uint32_t RESERVED_0: 25;
+        } BITS_390;
+    } u_390;
+
+    /* 0x394        0x4000_2394
+        18:0    R/W    gmac_base_addr                  19'h20020
+        31:19   R/W    RSVD                            13'b0
+    */
+    union
+    {
+        __IO uint32_t REG_GMAC_BASE_ADDR;
+        struct
+        {
+            __IO uint32_t gmac_base_addr: 19;
+            __IO uint32_t RESERVED_0: 13;
+        } BITS_394;
+    } u_394;
+
+    /* 0x398        0x4000_2398
+        18:0    R/W    gmac_base_addr_1                19'h28020
+        31:19   R/W    RSVD                            13'b0
+    */
+    union
+    {
+        __IO uint32_t REG_GMAC_BASE_ADDR_1;
+        struct
+        {
+            __IO uint32_t gmac_base_addr_1: 19;
+            __IO uint32_t RESERVED_0: 13;
+        } BITS_398;
+    } u_398;
+
+    /* 0x39C        0x4000_239c
+        5:0     R/W    gmac2fephy_phy_ad               6'b0
+        31:6    R/W    RSVD                            26'b0
+    */
+    union
+    {
+        __IO uint32_t REG_GMAC_PHY_AD;
+        struct
+        {
+            __IO uint32_t gmac2fephy_phy_ad: 6;
+            __IO uint32_t RESERVED_0: 26;
+        } BITS_39C;
+    } u_39C;
+
+    /* 0x3A0        0x4000_23a0
+        31:0    R/W    r_sdh0_phy_dbg                  32'h0
+    */
+    union
+    {
+        __IO uint32_t REG_SDH0_DBG0;
+        struct
+        {
+            __IO uint32_t r_sdh0_phy_dbg: 32;
+        } BITS_3A0;
+    } u_3A0;
+
+    /* 0x3A4        0x4000_23a4
+        31:0    R/W    r_sdh0_dbg                      32'h0
+    */
+    union
+    {
+        __IO uint32_t REG_SDH0_DBG1;
+        struct
+        {
+            __IO uint32_t r_sdh0_dbg: 32;
+        } BITS_3A4;
+    } u_3A4;
+
+    /* 0x3A8        0x4000_23a8
+        7:0     R/W    r_sdh0_cmd_out_oe_dly_sel       8'h0
+        15:8    R/W    r_sdh0_dat0_oe_dly_sel          8'h0
+        23:16   R/W    r_sdh0_dat1_oe_dly_sel          8'h0
+        31:24   R/W    r_sdh0_dat2_oe_dly_sel          8'h0
+    */
+    union
+    {
+        __IO uint32_t REG_SDH0_PHY4;
+        struct
+        {
+            __IO uint32_t r_sdh0_cmd_out_oe_dly_sel: 8;
+            __IO uint32_t r_sdh0_dat0_oe_dly_sel: 8;
+            __IO uint32_t r_sdh0_dat1_oe_dly_sel: 8;
+            __IO uint32_t r_sdh0_dat2_oe_dly_sel: 8;
+        } BITS_3A8;
+    } u_3A8;
+
+    /* 0x3AC        0x4000_23ac
+        7:0     R/W    r_sdh0_dat3_oe_dly_sel          8'h0
+        15:8    R/W    r_sdh0_dat4_oe_dly_sel          8'h0
+        23:16   R/W    r_sdh0_dat5_oe_dly_sel          8'h0
+        31:24   R/W    r_sdh0_dat6_oe_dly_sel          8'h0
+    */
+    union
+    {
+        __IO uint32_t REG_SDIO0_PHY5;
+        struct
+        {
+            __IO uint32_t r_sdh0_dat3_oe_dly_sel: 8;
+            __IO uint32_t r_sdh0_dat4_oe_dly_sel: 8;
+            __IO uint32_t r_sdh0_dat5_oe_dly_sel: 8;
+            __IO uint32_t r_sdh0_dat6_oe_dly_sel: 8;
+        } BITS_3AC;
+    } u_3AC;
+
+    /* 0x3B0        0x4000_23b0
+        7:0     R/W    r_sdh0_dat7_oe_dly_sel          8'h0
+        15:8    R/W    RSVD                            8'h0
+        23:16   R/W    RSVD                            8'h0
+        31:24   R/W    RSVD                            8'h0
+    */
+    union
+    {
+        __IO uint32_t REG_SDH0_PHY8;
+        struct
+        {
+            __IO uint32_t r_sdh0_dat7_oe_dly_sel: 8;
+            __IO uint32_t RESERVED_2: 8;
+            __IO uint32_t RESERVED_1: 8;
+            __IO uint32_t RESERVED_0: 8;
+        } BITS_3B0;
+    } u_3B0;
+
+    /* 0x3B4        0x4000_23b4
+        31:0    R/W    sdh_dummy_reg_1                 32'h0
+    */
+    union
+    {
+        __IO uint32_t SDIO_DUMMY_REG1;
+        struct
+        {
+            __IO uint32_t sdh_dummy_reg_1: 32;
+        } BITS_3B4;
+    } u_3B4;
+
+    /* 0x3B8        0x4000_23b8
+        31:0    R/W    sdh_dummy_reg_2                 32'h0
+    */
+    union
+    {
+        __IO uint32_t SDIO_DUMMY_REG2;
+        struct
+        {
+            __IO uint32_t sdh_dummy_reg_2: 32;
+        } BITS_3B8;
+    } u_3B8;
+
+    /* 0x3BC        0x4000_23bc
+        31:0    R/W    sdh_dummy_reg_3                 32'h0
+    */
+    union
+    {
+        __IO uint32_t SDIO_DUMMY_REG3;
+        struct
+        {
+            __IO uint32_t sdh_dummy_reg_3: 32;
+        } BITS_3BC;
+    } u_3BC;
+
+    /* 0x3C0        0x4000_23c0
+        31:0    R/W    sdh_dummy_reg_4                 32'h0
+    */
+    union
+    {
+        __IO uint32_t SDIO_DUMMY_REG4;
+        struct
+        {
+            __IO uint32_t sdh_dummy_reg_4: 32;
+        } BITS_3C0;
+    } u_3C0;
+
+} PERI_BLKCTRL_PERI_CLK_TypeDef;
+
+/* reference: RTL87x2G_PERI-ON_20221017_v2.xlsx */
+typedef struct
+{
+    /* 0x700        0x4000_2700
+        0       R/W    sport0_func_en          1'h0
+        1       R/W    sport0_ck_en            1'h0
+        2       R/W    sport1_func_en          1'h0
+        3       R/W    sport1_ck_en            1'h0
+        4       R/W    RSVD                    1'h0
+        5       R/W    RSVD                    1'h0
+        6       R/W    RSVD                    1'h0
+        7       R/W    RSVD                    1'h0
+        8       R/W    audio_func_en           1'h0
+        9       R/W    audio_ck_en             1'h0
+        10      R/W    r_CLK_EN_SPORT_40M      1'h0
+        13:11   R/W    sp0_dsp_clk_sel         3'h0
+        14      R/W    RSVD                    1'h0
+        17:15   R/W    sp1_dsp_clk_sel         3'h0
+        18      R/W    RSVD                    1'h0
+        21:19   R/W    RSVD                    3'h0
+        22      R/W    RSVD                    1'h0
+        25:23   R/W    RSVD                    3'h0
+        26      R/W    RSVD                    1'h0
+        27      R/W    RSVD                    1'h0
+        28      R/W    r_sport_pll2_ck_en      1'h0
+        31:29   R/W    RSVD                    3'h0
+    */
+    union
+    {
+        __IO uint32_t REG_SOC_AUDIO_IF_EN;
+        struct
+        {
+            __IO uint32_t sport0_func_en: 1;
+            __IO uint32_t sport0_ck_en: 1;
+            __IO uint32_t sport1_func_en: 1;
+            __IO uint32_t sport1_ck_en: 1;
+            __IO uint32_t RESERVED_11: 1;
+            __IO uint32_t RESERVED_10: 1;
+            __IO uint32_t RESERVED_9: 1;
+            __IO uint32_t RESERVED_8: 1;
+            __IO uint32_t audio_func_en: 1;
+            __IO uint32_t audio_ck_en: 1;
+            __IO uint32_t r_CLK_EN_SPORT_40M: 1;
+            __IO uint32_t sp0_dsp_clk_sel: 3;
+            __IO uint32_t RESERVED_7: 1;
+            __IO uint32_t sp1_dsp_clk_sel: 3;
+            __IO uint32_t RESERVED_6: 1;
+            __IO uint32_t RESERVED_5: 3;
+            __IO uint32_t RESERVED_4: 1;
+            __IO uint32_t RESERVED_3: 3;
+            __IO uint32_t RESERVED_2: 1;
+            __IO uint32_t RESERVED_1: 1;
+            __IO uint32_t r_sport_pll2_ck_en: 1;
+            __IO uint32_t RESERVED_0: 3;
+        } BITS_700;
+    } u_700;
+
+    /* 0x704        0x4000_2704
+        7:0     R/W    r_PLL_DIV0_SETTING      8'h0
+        15:8    R/W    r_PLL_DIV1_SETTING      8'h0
+        23:16   R/W    RSVD                    8'h0
+        31:24   R/W    RSVD                    8'h0
+    */
+    union
+    {
+        __IO uint32_t REG_AUDIO_PERI_CTL0;
+        struct
+        {
+            __IO uint32_t r_PLL_DIV0_SETTING: 8;
+            __IO uint32_t r_PLL_DIV1_SETTING: 8;
+            __IO uint32_t RESERVED_1: 8;
+            __IO uint32_t RESERVED_0: 8;
+        } BITS_704;
+    } u_704;
+
+    /* 0x708        0x4000_2708
+        0       R/W    r_CODEC_i2s0_master_sel 1'h0
+        1       R/W    r_CODEC_i2s1_master_sel 1'h0
+        2       R/W    RSVD                    1'h0
+        3       R/W    RSVD                    1'h0
+        4       R/W    r_SPORT0_EXT_CODEC      1'h0
+        5       R/W    r_SPORT1_EXT_CODEC      1'h0
+        6       R/W    RSVD                    1'h0
+        7       R/W    RSVD                    1'h0
+        8       R/W    r_SPORT0_MCLK_OUT       1'h0
+        9       R/W    r_SPORT1_MCLK_OUT       1'h0
+        10      R/W    RSVD                    1'h0
+        11      R/W    RSVD                    1'h0
+        31:12   R/W    RSVD                    20'h0
+    */
+    union
+    {
+        __IO uint32_t REG_AUDIO_PERI_CTL1;
+        struct
+        {
+            __IO uint32_t r_CODEC_i2s0_master_sel: 1;
+            __IO uint32_t r_CODEC_i2s1_master_sel: 1;
+            __IO uint32_t RESERVED_6: 1;
+            __IO uint32_t RESERVED_5: 1;
+            __IO uint32_t r_SPORT0_EXT_CODEC: 1;
+            __IO uint32_t r_SPORT1_EXT_CODEC: 1;
+            __IO uint32_t RESERVED_4: 1;
+            __IO uint32_t RESERVED_3: 1;
+            __IO uint32_t r_SPORT0_MCLK_OUT: 1;
+            __IO uint32_t r_SPORT1_MCLK_OUT: 1;
+            __IO uint32_t RESERVED_2: 1;
+            __IO uint32_t RESERVED_1: 1;
+            __IO uint32_t RESERVED_0: 20;
+        } BITS_708;
+    } u_708;
+
+    /* 0x70C        0x4000_270c
+        0       R/W    mclk2_en                1'h0
+        1       R/W    mclk2_out_sel           1'h0
+        3:2     R/W    RSVD                    2'h0
+        4       R/W    mclk2_src_sel_0         2'h0
+        5       R/W    mclk2_src_sel_1         2'h0
+        7:6     R/W    RSVD                    2'h0
+        15:8    R/W    mclk2_div_setting       8'h0
+        16      R/W    mclk2_pmux_sel          1'h0
+        31:17   R/W    RSVD                    15'h0
+    */
+    union
+    {
+        __IO uint32_t REG_AUDIO_PERI_CTL2;
+        struct
+        {
+            __IO uint32_t mclk2_en: 1;
+            __IO uint32_t mclk2_out_sel: 1;
+            __IO uint32_t RESERVED_2: 2;
+            __IO uint32_t mclk2_src_sel_0: 1;
+            __IO uint32_t mclk2_src_sel_1: 1;
+            __IO uint32_t RESERVED_1: 2;
+            __IO uint32_t mclk2_div_setting: 8;
+            __IO uint32_t mclk2_pmux_sel: 1;
+            __IO uint32_t RESERVED_0: 15;
+        } BITS_70C;
+    } u_70C;
+
+} PERIBLKCTRL_AUDIO_TypeDef;
+
+#define PERIBLKCTRL_PERICLK_REG_BASE0      0x40002300UL
+#define PERIBLKCTRL_AUDIO_REG_BASE         0x40002700UL
+
+
+#define PERIBLKCTRL_PERI_CLK            ((PERI_BLKCTRL_PERI_CLK_TypeDef *) PERIBLKCTRL_PERICLK_REG_BASE0)
+#define PERIBLKCTRL_AUDIO               ((PERIBLKCTRL_AUDIO_TypeDef *) PERIBLKCTRL_AUDIO_REG_BASE)
+
+#endif //#define PCC_REG_H
diff --git a/bee/soc/inc/rtl87x2g/platform_reg.h b/bee/soc/inc/rtl87x2g/platform_reg.h
new file mode 100644
index 00000000..e129271a
--- /dev/null
+++ b/bee/soc/inc/rtl87x2g/platform_reg.h
@@ -0,0 +1,128 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef PLATFORM_REG_H
+#define PLATFORM_REG_H
+#include <stdint.h>
+
+/* ================================================================================ */
+/* ================                PLATFORM Register               ================ */
+/* ===========     Reference: RTL87x2G_Reg_SoC_202201012_v0.xlsx     =========== */
+/* ================================================================================ */
+typedef struct
+{
+    /* 0x0000       0x4000_3000
+        31:0    R/W    RSVD                            32'h0
+    */
+    __IO uint32_t RSVD_0000;
+
+    /* 0x0004       0x4000_3004
+        0       R/W1C  spic0_intr_r                    1'h0
+        1       R/W1C  spic1_intr_r                    1'h0
+        2       R/W1C  spic2_intr_r                    1'h0
+        3       R/W1C  trng_intr_r                     1'h0
+        4       R/W1C  lpcomp_intr_r                   1'h0
+        5       R/W1C  spi_phy1_intr_r                 1'h0
+        30:6    R      RSVD                            25'h0
+        31      R/W1C  utmi_suspend_n_r                1'h0
+    */
+    union
+    {
+        __IO uint32_t REG_LOW_PRI_INT_STATUS;
+        struct
+        {
+            __IO uint32_t spic0_intr_r: 1;
+            __IO uint32_t spic1_intr_r: 1;
+            __IO uint32_t spic2_intr_r: 1;
+            __IO uint32_t trng_intr_r: 1;
+            __IO uint32_t lpcomp_intr_r: 1;
+            __IO uint32_t spi_phy1_intr_r: 1;
+            __I uint32_t RESERVED_0: 25;
+            __IO uint32_t utmi_suspend_n_r: 1;
+        } BITS_004;
+    } u_004;
+
+    /* 0x0008       0x4000_3008
+        31:0    R/W    low_pri_int_mode                32'hFFFFFFFF
+    */
+    union
+    {
+        __IO uint32_t REG_LOW_PRI_INT_MODE;
+        struct
+        {
+            __IO uint32_t low_pri_int_mode: 32;
+        } BITS_008;
+    } u_008;
+
+    /* 0x000C       0x4000_300c
+        31:0    R/W    low_pri_int_en                  32'h0
+    */
+    union
+    {
+        __IO uint32_t REG_LOW_PRI_INT_EN;
+        struct
+        {
+            __IO uint32_t low_pri_int_en: 32;
+        } BITS_00C;
+    } u_00C;
+
+    /* 0x0010       0x4000_3010
+        0       R      timer_intr1_intr0_r             1'h0
+        1       R      bluewiz_intr_r                  1'h0
+        2       R      RSVD                            1'h0
+        3       R      bluewiz_dma_intr_r              1'h0
+        4       R      pro_intr_r                      1'h0
+        31:5    R      RSVD                            27'h0
+    */
+    union
+    {
+        __IO uint32_t BT_MAC_INTERRUPT;
+        struct
+        {
+            __I uint32_t timer_intr1_intr0_r: 1;
+            __I uint32_t bluewiz_intr_r: 1;
+            __I uint32_t RESERVED_1: 1;
+            __I uint32_t bluewiz_dma_intr_r: 1;
+            __I uint32_t pro_intr_r: 1;
+            __I uint32_t RESERVED_0: 27;
+        } BITS_010;
+    } u_010;
+
+    /* 0x0014       0x4000_3014
+        23:0     R       RSVD                                           24'h0
+        26:24    R/W     RSVD                                           3'h0
+        31:27    R       RSVD                                           5'h0
+    */
+    union
+    {
+        __IO uint32_t RXI_INTERRUPT;
+        struct
+        {
+            __I uint32_t RESERVED_0: 32;
+        } BITS_014;
+    } u_014;
+
+    /* 0x0018       0x4000_3018
+        31:0    R/W    low_pri_int_pol                 32'h0
+    */
+    union
+    {
+        __IO uint32_t INTERRUPT_EDGE_OPTION;
+        struct
+        {
+            __IO uint32_t low_pri_int_pol: 32;
+        } BITS_018;
+    } u_018;
+
+} SoC_VENDOR_REG_TypeDef;
+
+
+#define SOC_VENDOR_REG_BASE             0x40003000UL
+#define VENDOR_REG_BASE                 SOC_VENDOR_REG_BASE
+
+#define SoC_VENDOR                      ((SoC_VENDOR_REG_TypeDef    *) SOC_VENDOR_REG_BASE)
+
+#endif //#define PLATFORM_REG_H
diff --git a/bee/soc/inc/rtl87x2g/rom_uuid.h b/bee/soc/inc/rtl87x2g/rom_uuid.h
new file mode 100644
index 00000000..db70ef75
--- /dev/null
+++ b/bee/soc/inc/rtl87x2g/rom_uuid.h
@@ -0,0 +1,10 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _symboltable_uuid_h
+#define _symboltable_uuid_h
+#define DEFINE_symboltable_uuid { 0xeb,0xfc,0x0a,0xb8,0xef,0x26,0xee,0x11,0xab,0x0f,0x2f,0x10,0xef,0x11,0xd4,0x3d }
+#endif
\ No newline at end of file
diff --git a/bee/soc/inc/rtl87x2g/secure/address_map.h b/bee/soc/inc/rtl87x2g/secure/address_map.h
new file mode 100644
index 00000000..bf4d9476
--- /dev/null
+++ b/bee/soc/inc/rtl87x2g/secure/address_map.h
@@ -0,0 +1,86 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ADDRESS_MAP_H
+#define ADDRESS_MAP_H
+
+/* ================================================================================ */
+/* ================                  Address Map                   ================ */
+/* ======== Reference: RTL87x2G_AddrMap_IRQs_DmaPorts_20220913v0.xlsx   ============ */
+/* ================================================================================ */
+
+#define SYSTEM_REG_BASE                    0x50000000UL
+#define RTC_REG_BASE                       0x50001800UL
+#define LPC_REG_BASE                       0x50001850UL
+#define LPC0_REG_BASE                      0x50001850UL
+#define PAD_REG_BASE                       0x50001900UL
+#define PAD_STS_REG_BASE                   0x50001AA0UL
+#define AON_WDT_REG_BASE                   0x50001B60UL
+#define AUXADC_REG_BASE                    0x50001B90UL
+#define QUAD_DECODER_REG_BASE              0x50001BD0UL
+#define PERI_ON_REG_BASE                   0x50002000UL
+#define PERI_ON_RCC_REG_BASE               0x50002300UL
+#define GPIOA_DEB_REG_BASE                 0x5000234CUL
+#define GPIOB_DEB_REG_BASE                 0x50002360UL
+#define TIMER_PWM_REG_BASE                 0x5000233CUL
+#define PINMUX_REG_BASE                    0x50002500UL
+#define QDEC_REG_BASE                      0x50009000UL
+#define SPI0_REG_BASE                      0x50013000UL
+#define SPI1_REG_BASE                      0x50013500UL
+#define SPI_SLAVE_REG_BASE                 0x50013800UL
+#define ENHANCED_TIMER_REG_BASE            0x50017000UL
+#define MODEMRFCPI_REG_BASE                0x50018000UL
+#define I2S0_REG_BASE                      0x50020000UL
+#define I2S1_REG_BASE                      0x50021000UL
+#define SPI_CODEC_REG_BASE                 0x50022000UL
+#define DISPLAY_CTRL_REG_BASE              0x50023000UL
+#define RXI350_DMAC0_CFG_REG_BASE          0x50025000UL
+#define PPE_CFG_REG_BASE                   0x50025000UL
+#define ISO7816_REG_BASE                   0x50026000UL
+#define SEGCOM_CTL_REG_BASE                0x50027000UL
+#define CAN_REG_BASE                       0x50028000UL
+#define SPIC_PHY_REG_BASE                  0x50029000UL
+
+#define PUBLIC_KEY_ENGINE_REG_BASE         0x50080000UL
+#define FLASH_SEC_REG_BASE                 0x500C0000UL
+#define AES_REG_BASE                       0x500C1000UL
+#define SHA256_REG_BASE                    0x500C2000UL
+#define TRNG_REG_BASE                      0x500C2500UL
+#define EFUSE_CONTROLLER_REG_BASE          0x500C2800UL
+#define USB_OTG_CFG_REG_BASE               0x50100000UL
+#define SPIC0_REG_BASE                     0x50150000UL
+#define SDHC_REG_BASE                      0x50150000UL
+#define SPIC1_REG_BASE                     0x50160000UL
+#define SPIC2_REG_BASE                     0x50170000UL
+#define GPIOA_REG_BASE                     0x50030000UL
+#define GPIOB_REG_BASE                     0x50030800UL
+#define TIMER_REG_BASE                     0x50031000UL
+#define SAR_ADC_REG_BASE                   0x50032000UL
+#define HRADC_REG_BASE                     0x50033000UL
+#define UART0_REG_BASE                     0x50035000UL
+#define UART1_REG_BASE                     0x50034500UL
+#define UART2_REG_BASE                     0x50034800UL
+#define UART3_REG_BASE                     0x50034C00UL
+#define UART4_REG_BASE                     0x50035000UL
+#define UART5_REG_BASE                     0x50035500UL
+#define I2C0_REG_BASE                      0x50035800UL
+#define I2C1_REG_BASE                      0x50035C00UL
+#define I2C2_REG_BASE                      0x50036000UL
+#define I2C3_REG_BASE                      0x50036500UL
+#define SPI3W_REG_BASE                     0x50036800UL
+#define KEYSCAN_REG_BASE                   0x50037000UL
+#define IR_RC_REG_BASE                     0x50038000UL
+#define ETH_CTRL_REG_BASE                  0x50050000UL
+#define BLUEWIZ_REG_BASE                   0x50050000UL
+#define BT_DMA_UART_BASE                   0x50051000UL
+#define BT_DMA_BASE                        0x50055000UL
+#define BT_VENDOR_REG_BASE                 0x50058000UL
+#define ZIGBEE_REG_BASE                    0x5005C000UL
+#define SPI0_HS_REG_BASE                   0x50060000UL
+#define IDU_REG_BASE                       0x50070000UL
+
+
+#endif //#define ADDRESS_MAP_H 
diff --git a/bee/soc/inc/rtl87x2g/vector_table.h b/bee/soc/inc/rtl87x2g/vector_table.h
new file mode 100644
index 00000000..46152026
--- /dev/null
+++ b/bee/soc/inc/rtl87x2g/vector_table.h
@@ -0,0 +1,97 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef VECTOR_TABLE_H
+#define VECTOR_TABLE_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "stdint.h"
+#include "stdbool.h"
+#include "vector_table_auto_gen.h"
+
+/** @defgroup VECTOR_TABLE  Vector table
+  * @brief
+  * @{
+  */
+
+/** @defgroup VECTOR_TABLE_Exported_Types Vector table Exported Types
+  * @brief
+  * @{
+  */
+
+typedef void (*IRQ_Fun)(void);       /**< ISR Handler Prototype */
+
+/* ================================================================================ */
+/* ================                      IRQ                       ================ */
+/* ================================================================================ */
+
+typedef enum IRQn
+{
+    IRQn_AUTO_GEN
+} IRQn_Type;
+
+/* ================================================================================ */
+/* ================                     VECTOR                     ================ */
+/* ================================================================================ */
+
+typedef enum
+{
+    VECTORn_AUTO_GEN
+} VECTORn_Type;
+
+extern void *RamVectorTable[];
+
+extern void Default_Handler_rom(void);
+extern void BTMAC_Handler(void);
+extern void HardFault_Handler_Rom(void);
+
+/** End of VECTOR_TABLE_Exported_Types
+  * @}
+  */
+
+/*============================================================================*
+*                              Functions
+*============================================================================*/
+/** @defgroup VECTOR_TABLE_Exported_Functions Vector table Exported Functions
+  * @brief
+  * @{
+  */
+/**
+ * @brief  Initialize RAM vector table to a given RAM address.
+ * @param  ram_vector_addr: RAM Vector Address.
+ * @retval true: Success
+ *         false: Fail
+ * @note   When using vector table relocation, the base address of the new vector
+ *         table must be aligned to the size of the vector table extended to the
+ *         next larger power of 2. In RTL8763, the base address is aligned at 0x100.
+ */
+bool RamVectorTableInit(uint32_t ram_vector_addr);
+
+/**
+ * @brief  Update ISR Handler in RAM Vector Table.
+ * @param  v_num: Vector number(index)
+ * @param  isr_handler: User defined ISR Handler.
+ * @retval true: Success
+ *         false: Fail
+ */
+bool RamVectorTableUpdate(VECTORn_Type v_num, IRQ_Fun isr_handler);
+
+/** End of VECTOR_TABLE_Exported_Functions
+  * @}
+  */
+
+/** End of VECTOR_TABLE
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // VECTOR_TABLE_H
diff --git a/bee/soc/inc/rtl87x2g/vector_table_auto_gen.h b/bee/soc/inc/rtl87x2g/vector_table_auto_gen.h
new file mode 100644
index 00000000..a8b19bf2
--- /dev/null
+++ b/bee/soc/inc/rtl87x2g/vector_table_auto_gen.h
@@ -0,0 +1,436 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef VECTOR_TABLE_AUTO_GEN_H
+#define VECTOR_TABLE_AUTO_GEN_H
+
+// *INDENT-OFF*
+/* ================================================================================ */
+/* ================                      IRQ                       ================ */
+/* ======== Reference: rtl87x2g_AddrMap_IRQs_DmaPorts_20220913v0.xlsx   =========== */
+/* ================================================================================ */
+
+#define IRQn_AUTO_GEN \
+        NMI_IRQn =                              -14, \
+        HardFault_IRQn =                        -13, \
+        MemoryManagement_IRQn =                   -12, \
+        BusFault_IRQn =                         -11, \
+        UsageFault_IRQn =                       -10, \
+        SecureFault_IRQn =                      -9, \
+        RSVD0_IRQn =                            -8, \
+        RSVD1_IRQn =                            -7, \
+        RSVD2_IRQn =                            -6, \
+        SVCall_IRQn =                              -5, \
+        DebugMonitor_IRQn =                     -4, \
+        RSVD3_IRQn =                            -3, \
+        PendSV_IRQn =                           -2, \
+        SysTick_IRQn =                          -1, \
+        System_IRQn =                           0, \
+        WDT_IRQn =                              1, \
+        RXI300_IRQn =                           2, \
+        RXI300_SEC_IRQn =                       3, \
+        Zigbee_IRQn =                           4, \
+        BTMAC_IRQn =                            5, \
+        Peripheral_IRQn =                       6, \
+        RSVD4_IRQn =                            7, \
+        RTC_IRQn =                              8, \
+        GPIO_A0_IRQn =                          9, \
+        GPIO_A1_IRQn =                          10, \
+        GPIO_A_2_7_IRQn =                       11, \
+        GPIO_A_8_15_IRQn =                      12, \
+        GPIO_A_16_23_IRQn =                     13, \
+        GPIO_A_24_31_IRQn =                     14, \
+        GPIO_B_0_7_IRQn =                       15, \
+        GPIO_B_8_15_IRQn =                      16, \
+        GPIO_B_16_23_IRQn =                     17, \
+        GPIO_B_24_31_IRQn =                     18, \
+        GDMA0_Channel0_IRQn =                   19, \
+        GDMA0_Channel1_IRQn =                   20, \
+        GDMA0_Channel2_IRQn =                   21, \
+        GDMA0_Channel3_IRQn =                   22, \
+        GDMA0_Channel4_IRQn =                   23, \
+        GDMA0_Channel5_IRQn =                   24, \
+        GDMA0_Channel6_IRQn =                   25, \
+        GDMA0_Channel7_IRQn =                   26, \
+        GDMA0_Channel8_IRQn =                   27, \
+        GDMA0_Channel9_IRQn =                   28, \
+        PPE_IRQn =                              29, \
+        I2C0_IRQn =                             30, \
+        I2C1_IRQn =                             31, \
+        I2C2_IRQn =                             32, \
+        I2C3_IRQn =                             33, \
+        UART0_IRQn =                            34, \
+        UART1_IRQn =                            35, \
+        UART2_IRQn =                            36, \
+        UART3_IRQn =                            37, \
+        UART4_IRQn =                            38, \
+        UART5_IRQn =                            39, \
+        SPI3W_IRQn =                            40, \
+        SPI0_IRQn =                             41, \
+        SPI1_IRQn =                             42, \
+        SPI_Slave_IRQn =                        43, \
+        Timer0_IRQn =                           44, \
+        Timer1_IRQn =                           45, \
+        Timer2_IRQn =                           46, \
+        Timer3_IRQn =                           47, \
+        Timer4_IRQn =                           48, \
+        Timer5_IRQn =                           49, \
+        Timer6_IRQn =                           50, \
+        Timer7_IRQn =                           51, \
+        Enhanced_Timer0_IRQn =                  52, \
+        Enhanced_Timer1_IRQn =                  53, \
+        Enhanced_Timer2_IRQn =                  54, \
+        Enhanced_Timer3_IRQn =                  55, \
+        HRADC_IRQn =                            56, \
+        SAR_ADC_IRQn =                          57, \
+        KEYSCAN_IRQn =                          58, \
+        AON_QDEC_IRQn =                         59, \
+        IR_IRQn =                               60, \
+        SDHC_IRQn =                             61, \
+        ISO7816_IRQn =                          62, \
+        Display_IRQn =                          63, \
+        SPORT0_RX_IRQn =                        64, \
+        SPORT0_TX_IRQn =                        65, \
+        SPORT1_RX_IRQn =                        66, \
+        SPORT1_TX_IRQn =                        67, \
+        SHA256_IRQn =                           68, \
+        Public_Key_Engine_IRQn =                69, \
+        Flash_SEC_IRQn =                        70, \
+        SegCom_CTL_IRQn =                       71, \
+        A2C_IRQn =                              72, \
+        ETH_IRQn =                              73, \
+        IMDC_IRQn =                             74, \
+        Slave_Port_Monitor_IRQn =               75, \
+        PTA_Mailbox_IRQn =                      76, \
+        USB_IRQn =                              77, \
+        USB_SUSPEND_N_IRQn =                    78, \
+        USB_Endp_Multi_Proc_IRQn =              79, \
+        USB_IN_EP_0_IRQn =                      80, \
+        USB_IN_EP_1_IRQn =                      81, \
+        USB_IN_EP_2_IRQn =                      82, \
+        USB_IN_EP_3_IRQn =                      83, \
+        USB_IN_EP_4_IRQn =                      84, \
+        USB_IN_EP_5_IRQn =                      85, \
+        USB_OUT_EP_0_IRQn =                     86, \
+        USB_OUT_EP_1_IRQn =                     87, \
+        USB_OUT_EP_2_IRQn =                     88, \
+        USB_OUT_EP_3_IRQn =                     89, \
+        USB_OUT_EP_4_IRQn =                     90, \
+        USB_OUT_EP_5_IRQn =                     91, \
+        USB_Sof_IRQn =                          92, \
+        TMETER_IRQn =                           93, \
+        PF_RTC_IRQn =                           94, \
+        BTMAC_WRAP_AROUND_IRQn =                95, \
+        \
+/* second level interrupt (BTMAC_ISR Status Register) */ \
+        Timer_A0_A1_IRQn =                      96, \
+        BT_Bluewiz_IRQn =                       97, \
+        RSVD6_IRQn =                            98, \
+        BT_BZ_DMA_IRQn =                        99, \
+        Proprietary_protocol_IRQn =             100, \
+        RSVD7_IRQn =                            101, \
+        \
+/* second level interrupt (Peripheral_ISR Status Register) */ \
+        SPIC0_IRQn =                            102, \
+        SPIC1_IRQn =                            103, \
+        SPIC2_IRQn =                            104, \
+        TRNG_IRQn=                              105, \
+        LPCOMP_IRQn =                           106, \
+        SPI_PHY1_IRQn =                         107, \
+        RSVD8_IRQn =                            108, \
+
+
+#define FIRST_LEVEL_First_IRQn   System_IRQn
+#define FIRST_LEVEL_Last_IRQn    PF_RTC_IRQn
+
+#define Peripheral_First_IRQn    SPIC0_IRQn
+#define Peripheral_Last_IRQn     RSVD7_IRQn
+
+#define BTMAC_First_IRQn         Timer_A0_A1_IRQn
+#define BTMAC_Last_IRQn          RSVD6_IRQn
+
+#define GPIOA0_IRQn              GPIO_A0_IRQn
+#define GPIOA1_IRQn              GPIO_A1_IRQn
+#define GPIOA2_IRQn              GPIO_A_2_7_IRQn
+#define GPIOA3_IRQn              GPIO_A_2_7_IRQn
+#define GPIOA4_IRQn              GPIO_A_2_7_IRQn
+#define GPIOA5_IRQn              GPIO_A_2_7_IRQn
+#define GPIOA6_IRQn              GPIO_A_2_7_IRQn
+#define GPIOA7_IRQn              GPIO_A_2_7_IRQn
+#define GPIOA8_IRQn              GPIO_A_8_15_IRQn
+#define GPIOA9_IRQn              GPIO_A_8_15_IRQn
+#define GPIOA10_IRQn             GPIO_A_8_15_IRQn
+#define GPIOA11_IRQn             GPIO_A_8_15_IRQn
+#define GPIOA12_IRQn             GPIO_A_8_15_IRQn
+#define GPIOA13_IRQn             GPIO_A_8_15_IRQn
+#define GPIOA14_IRQn             GPIO_A_8_15_IRQn
+#define GPIOA15_IRQn             GPIO_A_8_15_IRQn
+#define GPIOA16_IRQn             GPIO_A_16_23_IRQn
+#define GPIOA17_IRQn             GPIO_A_16_23_IRQn
+#define GPIOA18_IRQn             GPIO_A_16_23_IRQn
+#define GPIOA19_IRQn             GPIO_A_16_23_IRQn
+#define GPIOA20_IRQn             GPIO_A_16_23_IRQn
+#define GPIOA21_IRQn             GPIO_A_16_23_IRQn
+#define GPIOA22_IRQn             GPIO_A_16_23_IRQn
+#define GPIOA23_IRQn             GPIO_A_16_23_IRQn
+#define GPIOA24_IRQn             GPIO_A_24_31_IRQn
+#define GPIOA25_IRQn             GPIO_A_24_31_IRQn
+#define GPIOA26_IRQn             GPIO_A_24_31_IRQn
+#define GPIOA27_IRQn             GPIO_A_24_31_IRQn
+#define GPIOA28_IRQn             GPIO_A_24_31_IRQn
+#define GPIOA29_IRQn             GPIO_A_24_31_IRQn
+#define GPIOA30_IRQn             GPIO_A_24_31_IRQn
+#define GPIOA31_IRQn             GPIO_A_24_31_IRQn
+
+#define GPIOB0_IRQn              GPIO_B_0_7_IRQn
+#define GPIOB1_IRQn              GPIO_B_0_7_IRQn
+#define GPIOB2_IRQn              GPIO_B_0_7_IRQn
+#define GPIOB3_IRQn              GPIO_B_0_7_IRQn
+#define GPIOB4_IRQn              GPIO_B_0_7_IRQn
+#define GPIOB5_IRQn              GPIO_B_0_7_IRQn
+#define GPIOB6_IRQn              GPIO_B_0_7_IRQn
+#define GPIOB7_IRQn              GPIO_B_0_7_IRQn
+#define GPIOB8_IRQn              GPIO_B_8_15_IRQn
+#define GPIOB9_IRQn              GPIO_B_8_15_IRQn
+#define GPIOB10_IRQn             GPIO_B_8_15_IRQn
+#define GPIOB11_IRQn             GPIO_B_8_15_IRQn
+#define GPIOB12_IRQn             GPIO_B_8_15_IRQn
+#define GPIOB13_IRQn             GPIO_B_8_15_IRQn
+#define GPIOB14_IRQn             GPIO_B_8_15_IRQn
+#define GPIOB15_IRQn             GPIO_B_8_15_IRQn
+#define GPIOB16_IRQn             GPIO_B_16_23_IRQn
+#define GPIOB17_IRQn             GPIO_B_16_23_IRQn
+#define GPIOB18_IRQn             GPIO_B_16_23_IRQn
+#define GPIOB19_IRQn             GPIO_B_16_23_IRQn
+#define GPIOB20_IRQn             GPIO_B_16_23_IRQn
+#define GPIOB21_IRQn             GPIO_B_16_23_IRQn
+#define GPIOB22_IRQn             GPIO_B_16_23_IRQn
+#define GPIOB23_IRQn             GPIO_B_16_23_IRQn
+#define GPIOB24_IRQn             GPIO_B_24_31_IRQn
+#define GPIOB25_IRQn             GPIO_B_24_31_IRQn
+#define GPIOB26_IRQn             GPIO_B_24_31_IRQn
+#define GPIOB27_IRQn             GPIO_B_24_31_IRQn
+#define GPIOB28_IRQn             GPIO_B_24_31_IRQn
+#define GPIOB29_IRQn             GPIO_B_24_31_IRQn
+#define GPIOB30_IRQn             GPIO_B_24_31_IRQn
+#define GPIOB31_IRQn             GPIO_B_24_31_IRQn
+
+
+/* ================================================================================ */
+/* ================                     VECTOR                     ================ */
+/* ======== Reference: rtl87x2g_AddrMap_IRQs_DmaPorts_20220913v0.xlsx   =========== */
+/* ================================================================================ */
+
+#define VECTORn_AUTO_GEN \
+        InitialSPvalue_VECTORn =                   0, \
+        Reset_VECTORn =                            1, \
+        NMI_VECTORn =                              2, \
+        HardFault_VECTORn =                        3, \
+        MemManageFault_VECTORn =                   4, \
+        BusFault_VECTORn =                         5, \
+        UsageFault_VECTORn =                       6, \
+        RSVD0_VECTORn =                            7, \
+        RSVD1_VECTORn =                            8, \
+        RSVD2_VECTORn =                            9, \
+        RSVD3_VECTORn =                            10, \
+        SVC_VECTORn =                              11, \
+        DebugMonitor_VECTORn =                     12, \
+        RSVD4_VECTORn =                            13, \
+        PendSV_VECTORn =                           14, \
+        SysTick_VECTORn =                          15, \
+        System_VECTORn =                           16, \
+        WDT_VECTORn =                              17, \
+        RXI300_VECTORn =                           18, \
+        RXI300_SEC_VECTORn =                       19, \
+        Zigbee_VECTORn =                           20, \
+        BTMAC_VECTORn =                            21, \
+        Peripheral_VECTORn =                       22, \
+        RSVD5_VECTORn =                            23, \
+        RTC_VECTORn =                              24, \
+        GPIO_A0_VECTORn =                          25, \
+        GPIO_A1_VECTORn =                          26, \
+        GPIO_A_2_7_VECTORn =                       27, \
+        GPIO_A_8_15_VECTORn =                      28, \
+        GPIO_A_16_23_VECTORn =                     29, \
+        GPIO_A_24_31_VECTORn =                     30, \
+        GPIO_B_0_7_VECTORn =                       31, \
+        GPIO_B_8_15_VECTORn =                      32, \
+        GPIO_B_16_23_VECTORn =                     33, \
+        GPIO_B_24_31_VECTORn =                     34, \
+        GDMA0_Channel0_VECTORn =                   35, \
+        GDMA0_Channel1_VECTORn =                   36, \
+        GDMA0_Channel2_VECTORn =                   37, \
+        GDMA0_Channel3_VECTORn =                   38, \
+        GDMA0_Channel4_VECTORn =                   39, \
+        GDMA0_Channel5_VECTORn =                   40, \
+        GDMA0_Channel6_VECTORn =                   41, \
+        GDMA0_Channel7_VECTORn =                   42, \
+        GDMA0_Channel8_VECTORn =                   43, \
+        GDMA0_Channel9_VECTORn =                   44, \
+        PPE_VECTORn =                              45, \
+        I2C0_VECTORn =                             46, \
+        I2C1_VECTORn =                             47, \
+        I2C2_VECTORn =                             48, \
+        I2C3_VECTORn =                             49, \
+        UART0_VECTORn =                            50, \
+        UART1_VECTORn =                            51, \
+        UART2_VECTORn =                            52, \
+        UART3_VECTORn =                            53, \
+        UART4_VECTORn =                            54, \
+        UART5_VECTORn =                            55, \
+        SPI_3Wire_VECTORn =                        56, \
+        SPI0_VECTORn =                             57, \
+        SPI1_VECTORn =                             58, \
+        SPI_Slave_VECTORn =                        59, \
+        Timer0_VECTORn =                           60, \
+        Timer1_VECTORn =                           61, \
+        Timer2_VECTORn =                           62, \
+        Timer3_VECTORn =                           63, \
+        Timer4_VECTORn =                           64, \
+        Timer5_VECTORn =                           65, \
+        Timer6_VECTORn =                           66, \
+        Timer7_VECTORn =                           67, \
+        Enhanced_Timer0_VECTORn =                  68, \
+        Enhanced_Timer1_VECTORn =                  69, \
+        Enhanced_Timer2_VECTORn =                  70, \
+        Enhanced_Timer3_VECTORn =                  71, \
+        ADC_24bit_VECTORn =                        72, \
+        SAR_ADC_VECTORn =                          73, \
+        KEYSCAN_VECTORn =                          74, \
+        AON_QDEC_VECTORn =                         75, \
+        IR_VECTORn =                               76, \
+        SDIO_VECTORn =                             77, \
+        ISO7816_VECTORn =                          78, \
+        Display_VECTORn =                          79, \
+        SPORT0_RX_VECTORn =                        80, \
+        SPORT0_TX_VECTORn =                        81, \
+        SPORT1_RX_VECTORn =                        82, \
+        SPORT1_TX_VECTORn =                        83, \
+        SHA256_VECTORn =                           84, \
+        Public_Key_Engine_VECTORn =                85, \
+        Flash_SEC_VECTORn =                        86, \
+        SegCom_CTL_VECTORn =                       87, \
+        A2C_VECTORn =                              88, \
+        ETH_VECTORn =                              89, \
+        IMDC_VECTORn =                             90, \
+        Slave_Port_Monitor_VECTORn =               91, \
+        PTA_Mailbox_VECTORn =                      92, \
+        USB_VECTORn =                              93, \
+        USB_SUSPEND_N_VECTORn =                    94, \
+        USB_Endp_Muti_Proc_VECTORn =               95, \
+        USB_IN_EP_0_VECTORn =                      96, \
+        USB_IN_EP_1_VECTORn =                      97, \
+        USB_IN_EP_2_VECTORn =                      98, \
+        USB_IN_EP_3_VECTORn =                      99, \
+        USB_IN_EP_4_VECTORn =                      100, \
+        USB_IN_EP_5_VECTORn =                      101, \
+        USB_OUT_EP_0_VECTORn =                     102, \
+        USB_OUT_EP_1_VECTORn =                     103, \
+        USB_OUT_EP_2_VECTORn =                     104, \
+        USB_OUT_EP_3_VECTORn =                     105, \
+        USB_OUT_EP_4_VECTORn =                     106, \
+        USB_OUT_EP_5_VECTORn =                     107, \
+        USB_Sof_VECTORn =                          108, \
+        TMETER_VECTORn =                           109, \
+        PF_RTC_VECTORn =                           110, \
+        BTMAC_WRAP_AROUND_VECTORn =                111, \
+        \
+/* second level interrupt (BTMAC_ISR Status Register) */ \
+        Timer_A0_A1_VECTORn =                      112, \
+        BT_Bluewiz_VECTORn =                       113, \
+        RSVD6_VECTORn =                            114, \
+        BT_BZ_DMA_VECTORn =                        115, \
+        Proprietary_protocol_VECTORn =             116, \
+        RSVD7_VECTORn =                            117, \
+        \
+/* second level interrupt (Peripheral_ISR Status Register) */ \
+        SPIC0_VECTORn =                            118, \
+        SPIC1_VECTORn =                            119, \
+        SPIC2_VECTORn =                            120, \
+        TRNG_VECTORn =                             121, \
+        LPCOMP_VECTORn =                           122, \
+        SPI_PHY1_VECTORn =                         123, \
+        RSVD8_VECTORn =                            124, \
+        \
+/* second level interrupt (GPIO_ISR Status Register) */ \
+        GPIOA2_VECTORn =                           125, \
+        GPIOA3_VECTORn =                           126, \
+        GPIOA4_VECTORn =                           127, \
+        GPIOA5_VECTORn =                           128, \
+        GPIOA6_VECTORn =                           129, \
+        GPIOA7_VECTORn =                           130, \
+        GPIOA8_VECTORn =                           131, \
+        GPIOA9_VECTORn =                           132, \
+        GPIOA10_VECTORn =                          133, \
+        GPIOA11_VECTORn =                          134, \
+        GPIOA12_VECTORn =                          135, \
+        GPIOA13_VECTORn =                          136, \
+        GPIOA14_VECTORn =                          137, \
+        GPIOA15_VECTORn =                          138, \
+        GPIOA16_VECTORn =                          139, \
+        GPIOA17_VECTORn =                          140, \
+        GPIOA18_VECTORn =                          141, \
+        GPIOA19_VECTORn =                          142, \
+        GPIOA20_VECTORn =                          143, \
+        GPIOA21_VECTORn =                          144, \
+        GPIOA22_VECTORn =                          145, \
+        GPIOA23_VECTORn =                          146, \
+        GPIOA24_VECTORn =                          147, \
+        GPIOA25_VECTORn =                          148, \
+        GPIOA26_VECTORn =                          149, \
+        GPIOA27_VECTORn =                          150, \
+        GPIOA28_VECTORn =                          151, \
+        GPIOA29_VECTORn =                          152, \
+        GPIOA30_VECTORn =                          153, \
+        GPIOA31_VECTORn =                          154, \
+        GPIOB0_VECTORn =                           155, \
+        GPIOB1_VECTORn =                           156, \
+        GPIOB2_VECTORn =                           157, \
+        GPIOB3_VECTORn =                           158, \
+        GPIOB4_VECTORn =                           159, \
+        GPIOB5_VECTORn =                           160, \
+        GPIOB6_VECTORn =                           161, \
+        GPIOB7_VECTORn =                           162, \
+        GPIOB8_VECTORn =                           163, \
+        GPIOB9_VECTORn =                           164, \
+        GPIOB10_VECTORn =                          165, \
+        GPIOB11_VECTORn =                          166, \
+        GPIOB12_VECTORn =                          167, \
+        GPIOB13_VECTORn =                          168, \
+        GPIOB14_VECTORn =                          169, \
+        GPIOB15_VECTORn =                          170, \
+        GPIOB16_VECTORn =                          171, \
+        GPIOB17_VECTORn =                          172, \
+        GPIOB18_VECTORn =                          173, \
+        GPIOB19_VECTORn =                          174, \
+        GPIOB20_VECTORn =                          175, \
+        GPIOB21_VECTORn =                          176, \
+        GPIOB22_VECTORn =                          177, \
+        GPIOB23_VECTORn =                          178, \
+        GPIOB24_VECTORn =                          179, \
+        GPIOB25_VECTORn =                          180, \
+        GPIOB26_VECTORn =                          181, \
+        GPIOB27_VECTORn =                          182, \
+        GPIOB28_VECTORn =                          183, \
+        GPIOB29_VECTORn =                          184, \
+        GPIOB30_VECTORn =                          185, \
+        GPIOB31_VECTORn =                          186, \
+        MAX_VECTORn =                              187, \
+
+
+#define Peripheral_First_VECTORn    SPIC0_VECTORn
+#define Peripheral_Last_VECTORn     RSVD7_VECTORn
+
+#define BTMAC_First_VECTORn         Timer_A0_A1_IRQn
+#define BTMAC_Last_VECTORn          RSVD6_VECTORn
+
+#define GPIOA_First_VECTORn         GPIOA2_VECTORn
+#define GPIOA_Last_VECTORn          GPIOA31_VECTORn
+#define GPIOB_First_VECTORn         GPIOB0_VECTORn
+#define GPIOB_Last_VECTORn          GPIOB31_VECTORn
+
+// *INDENT-ON* 
+#endif //#define VECTOR_TABLE_AUTO_GEN_H
diff --git a/bee/soc/inc/rtl87x2j/address_map.h b/bee/soc/inc/rtl87x2j/address_map.h
new file mode 100755
index 00000000..ef4b1652
--- /dev/null
+++ b/bee/soc/inc/rtl87x2j/address_map.h
@@ -0,0 +1,63 @@
+#ifndef ADDRESS_MAP_H
+#define ADDRESS_MAP_H
+
+/* ================================================================================ */
+/* ================                  Address Map                   ================ */
+/* ======== Reference: Bee5_AddressMap_20241022v0.xlsx   ============ */
+/* ================================================================================ */
+
+#define CM33_ROM_BASE            0x0
+#define CM33_RAM_BASE            0x200000
+#define BUFFER_RAM_BASE          0x20100000
+#define ICACHE_MEM_BASE          0x3000000
+#define EFLASH_MEM_BASE          0x4000000
+#define SPIC0_MEM_BASE           0x5000000
+#define DATA_RAM_BASE            0x20000000
+#define EFLASH_CTRL_BASE         0x40082000
+#define SPIC0_BASE               0x40080000
+#define SYSON_BASE               0x40000000
+#define RXI350_CFG_BASE          0x40001000
+#define PPU0_BASE                0x40002000
+#define RXI300_BASE              0x40003000
+#define SPI3W_BASE               0x40004000
+#define KEY_SCAN_BASE            0x40004800
+#define RXI300_EXT_BASE          0x40005000
+#define SOC_VENDOR_REG_BASE      0x40006000
+#define RAP_BASE                 0x40007000
+#define MODEMRFCPI_BASE          0x40008000
+#define AMU_BASE                 0x40200000
+#define AUX_ADC_BASE             0x40010000
+#define UART0_BASE               0x40011000
+#define UART1_BASE               0x40011400
+#define UART2_BASE               0x40011800
+#define UART3_BASE               0x40011c00
+#define SPI0_BASE                0x40012000
+#define SPI1_BASE                0x40012400
+#define SPI2_BASE                0x40012800
+#define RSVD0_BASE               0x40012c00
+#define RSVD1_BASE               0x40013000
+#define ICACHE_CTRL_BASE         0x40013800
+#define I2C0_BASE                0x40015000
+#define I2C1_BASE                0x40015400
+#define IR_RC_BASE               0x40015800
+#define CAN_BASE                 0x40016000
+#define ENHANCED_TIMER_BASE      0x40018000
+#define GPIO0_BASE               0x4001a000
+#define PPU1_BASE                0x4001b000
+#define AES_BASE                 0x40020000
+#define TIMER0_BASE              0x40022000
+#define TIMER1_BASE              0x40024000
+#define SPI_CODEC_BASE           0x40026000
+#define I2S0_BASE                0x40029000
+#define SHA256_BASE              0x4002a000
+#define BLUEWIZ_BASE             0x40050000
+#define RSVD2_BASE               0x40054000
+#define PROPRIETARY_2P4G_BASE    0x40056000
+#define BT_VENDOR_REG_BASE       0x40058000
+#define SPI0_HS_BASE             0x40040000
+#define SPI1_HS_BASE             0x40040400
+#define SPI2_HS_BASE             0x40040800
+#define USBOTG_CFG_BASE          0x40100000
+
+
+#endif //#define ADDRESS_MAP_H 
diff --git a/bee/soc/inc/rtl87x2j/aon_reg.h b/bee/soc/inc/rtl87x2j/aon_reg.h
new file mode 100755
index 00000000..cb7e19e6
--- /dev/null
+++ b/bee/soc/inc/rtl87x2j/aon_reg.h
@@ -0,0 +1,29185 @@
+#ifndef AON_REG_H
+#define AON_REG_H
+#include <stdint.h>
+
+/* ================================================================================ */
+/* ================                AON Register               ================ */
+/* ===========     Reference: RL7019_SYSON_auto_gen_table_20251107A.xlsx
+                          RL7019_SYSON_replace_fw_general_20250926A.xlsx  =========== */
+/* ================================================================================ */
+#define AON_REG_SYSTEM_REG0X                        0x0
+#define AON_REG_SYSTEM_REG1X                        0x4
+#define AON_REG_SYSTEM_REG2X                        0x8
+#define AON_REG_SYSTEM_REG3X                        0xC
+#define AON_REG_SYSTEM_REG4X                        0x10
+#define AON_REG_SYSTEM_REG5X                        0x14
+#define AON_REG_SYSTEM_REG6X                        0x18
+#define AON_REG_SYSTEM_REG7X                        0x1C
+#define AON_REG_SYSTEM_REG8X                        0x20
+#define AON_REG_SYSTEM_REG9X                        0x24
+#define AON_REG_SYSTEM_REG10X                       0x28
+#define AON_REG_SYSTEM_REG11X                       0x2C
+#define AON_REG_SYSTEM_REG12X                       0x30
+#define AON_REG_SYSTEM_REG13X                       0x34
+#define AON_REG_SYSTEM_REG14X                       0x38
+#define AON_REG_SYSTEM_REG15X                       0x3C
+#define AON_REG_SYSTEM_REG16X                       0x40
+#define AON_REG_SYSTEM_REG17X                       0x44
+#define AON_REG_SYSTEM_REG18X                       0x48
+#define AON_REG_SYSTEM_REG19X                       0x4C
+#define AON_REG_SYSTEM_REG20X                       0x50
+#define AON_REG_SYSTEM_REG21X                       0x54
+#define AON_REG_SYSTEM_REG22X                       0x58
+#define AON_REG_SYSTEM_REG23X                       0x5C
+#define AON_REG_SYSTEM_REG24X                       0x60
+#define AON_REG_SYSTEM_REG25X                       0x64
+#define AON_REG_SYSTEM_REG26X                       0x68
+#define AON_REG_SYSTEM_REG27X                       0x6C
+#define AON_REG_SYSTEM_REG28X                       0x70
+#define AON_REG_SYSTEM_REG29X                       0x74
+#define AON_REG_SYSTEM_REG30X                       0x78
+#define AON_REG_SYSTEM_REG31X                       0x7C
+#define AON_REG_SYSTEM_REG32X                       0x80
+#define AON_REG_SYSTEM_REG33X                       0x84
+#define AON_REG_SYSTEM_REG34X                       0x88
+#define AON_REG_SYSTEM_REG35X                       0x8C
+#define AON_REG_SYSTEM_REG36X                       0x90
+#define AON_REG_SYSTEM_REG37X                       0x94
+#define AON_REG_SYSTEM_REG38X                       0x98
+#define AON_REG_FW_GENERAL_REG0X                    0xC0
+#define AON_REG_FW_GENERAL_REG1X                    0xC4
+#define AON_REG_FW_GENERAL_REG2X                    0xC8
+#define AON_REG_FW_GENERAL_REG3X                    0xCC
+#define AON_REG_FW_GENERAL_REG4X                    0xD0
+#define AON_REG_FW_GENERAL_REG5X                    0xD4
+#define AON_REG_FW_GENERAL_REG6X                    0xD8
+#define AON_REG_DEBUG_AUTHENTICATION0               0xDC
+#define AON_REG_DEBUG_AUTHENTICATION1               0xE0
+#define AON_REG_DEBUG_AUTHENTICATION2               0xE4
+#define AON_REG_DEBUG_AUTHENTICATION3               0xE8
+#define AON_REG_FW_GENERAL_REG11X                   0xEC
+#define AON_REG_FW_GENERAL_REG12X                   0xF0
+#define AON_REG_FW_GENERAL_REG13X                   0xF4
+#define AON_REG_FW_GENERAL_REG14X                   0xF8
+#define AON_REG_FW_GENERAL_REG15X                   0xFC
+#define AON_REG_FW_GENERAL_REG16X                   0x100
+#define AON_REG_FW_GENERAL_REG17X                   0x104
+#define AON_REG_PAD_REG0X                           0x120
+#define AON_REG_PAD_REG1X                           0x124
+#define AON_REG_PAD_REG2X                           0x128
+#define AON_REG_PAD_REG3X                           0x12C
+#define AON_REG_PAD_REG4X                           0x130
+#define AON_REG_PAD_REG5X                           0x134
+#define AON_REG_PAD_REG6X                           0x138
+#define AON_REG_PAD_REG7X                           0x13C
+#define AON_REG_PAD_REG8X                           0x140
+#define AON_REG_PAD_REG9X                           0x144
+#define AON_REG_PAD_REG10X                          0x148
+#define AON_REG_PAD_REG11X                          0x14C
+#define AON_REG_PAD_REG12X                          0x150
+#define AON_REG_PAD_REG13X                          0x154
+#define AON_REG_PAD_REG14X                          0x158
+#define AON_REG_PAD_REG15X                          0x15C
+#define AON_REG_PAD_REG16X                          0x160
+#define AON_REG_PAD_REG17X                          0x164
+#define AON_REG_PAD_REG18X                          0x168
+#define AON_REG_PAD_REG19X                          0x16C
+#define AON_REG_PAD_REG20X                          0x170
+#define AON_REG_PAD_REG21X                          0x174
+#define AON_REG_PAD_REG22X                          0x178
+#define AON_REG_PAD_REG23X                          0x17C
+#define AON_REG_PAD_REG24X                          0x180
+#define AON_REG_PAD_REG25X                          0x184
+#define AON_REG_PAD_REG26X                          0x188
+#define AON_REG_PAD_REG27X                          0x18C
+#define AON_REG_PAD_REG28X                          0x190
+#define AON_REG_PAD_REG29X                          0x194
+#define AON_REG_SPI_PAD_REG30X                      0x198
+#define AON_REG_PAD_REG31X                          0x19C
+#define AON_REG_PAD_REG32X                          0x1A0
+#define AON_REG_PAD_REG33X                          0x1A4
+#define AON_REG_PAD_REG34X                          0x1A8
+#define AON_REG_PAD_VPON_REG0X                      0x1C4
+#define AON_REG_PAD_VPON_REG1X                      0x1C8
+#define AON_REG_PAD_VPON_REG2X                      0x1CC
+#define AON_REG_WDT_REG0X                           0x400
+#define AON_REG_WDT_REG1X                           0x404
+#define AON_REG_WDT_REG2X                           0x408
+#define AON_REG_WDT_REG3X                           0x40C
+#define AON_REG_WDT_REG4X                           0x410
+#define AON_REG_WDT_REG5X                           0x414
+#define AON_REG_WDT_REG6X                           0x418
+#define AON_REG_WDT_REG7X                           0x41C
+#define AON_REG_WDT_REG8X                           0x420
+#define AON_REG_WDT_REG9X                           0x424
+#define AON_REG_WDT_REG10X                          0x428
+#define AON_REG_WDT_REG11X                          0x42C
+#define AON_REG_WDT_REG12X                          0x430
+#define AON_REG_WDT_REG13X                          0x434
+#define AON_REG_WDT_REG14X                          0x438
+#define AON_REG_WDT_REG15X                          0x43C
+#define AON_REG_WDT_REG16X                          0x440
+#define AON_REG_WDT_REG17X                          0x444
+#define AON_REG_WDT_REG18X                          0x448
+#define AON_REG_WDT_REG19X                          0x44C
+#define AON_REG_WDT_REG20X                          0x450
+#define AON_REG_IO_WDT_REG0X                        0x458
+#define AON_REG_IO_WDT_REG1X                        0x45C
+#define AON_REG_SHIP_DPD_REG0X                      0x464
+#define AON_C_KOUT0X_DPD                            0x468
+#define AON_REG_MBIAS_REG0X                         0x488
+#define AON_REG_MBIAS_REG1X                         0x48C
+#define AON_REG_MBIAS_REG2X                         0x490
+#define AON_REG_MBIAS_REG3X                         0x494
+#define AON_C_KOUT0X_MBIAS                          0x498
+#define AON_C_KOUT1X_MBIAS                          0x49C
+#define AON_REG0X_OSC10M                            0x4BC
+#define AON_REG2X_OSC10M                            0x4C0
+#define AON_REG0X_OSC128K                           0x4C4
+#define AON_REG_POW_OSC                             0x4C8
+#define AON_C_KOUT0X_OSC128K10M                     0x4CC
+#define AON_REG0X_OSC128K_CAL                       0x500
+#define AON_REG2X_OSC128K_CAL                       0x504
+#define AON_REG4X_OSC128K_CAL                       0x508
+#define AON_REG6X_OSC128K_CAL                       0x50C
+#define AON_REG8X_OSC128K_CAL                       0x510
+#define AON_REG10X_OSC128K_CAL                      0x514
+#define AON_REG12X_OSC128K_CAL                      0x518
+#define AON_REG14X_OSC128K_CAL                      0x51C
+#define AON_REG16X_OSC128K_CAL                      0x520
+#define AON_REG18X_OSC128K_CAL                      0x524
+#define AON_REG20X_OSC128K_CAL                      0x528
+#define AON_REG22X_OSC128K_CAL                      0x52C
+#define AON_REG24X_OSC128K_CAL                      0x530
+#define AON_REG26X_OSC128K_CAL                      0x534
+#define AON_REG28X_OSC128K_CAL                      0x538
+#define AON_REG30X_OSC128K_CAL                      0x53C
+#define AON_REG32X_OSC128K_CAL                      0x540
+#define AON_REG34X_OSC128K_CAL                      0x544
+#define AON_REG36X_OSC128K_CAL                      0x548
+#define AON_REG38X_OSC128K_CAL                      0x54C
+#define AON_REG_OSC128K_CAL_RAP                     0x550
+#define AON_REG_OSC128K_CAL_QCH                     0x554
+#define AON_REG_40MXTAL_AON_REG0X                   0x600
+#define AON_ANAPAR_XTAL_MODE                        0x610
+#define AON_ANAPAR_XTAL0                            0x614
+#define AON_ANAPAR_XTAL2                            0x618
+#define AON_ANAPAR_XTAL4                            0x61C
+#define AON_ANAPAR_XTAL6                            0x620
+#define AON_ANAPAR_XTAL8                            0x624
+#define AON_ANAPAR_XTAL10                           0x628
+#define AON_ANAPAR_XTAL12                           0x62C
+#define AON_ANAPAR_XTAL14                           0x630
+#define AON_REG0X_OSC80M                            0x650
+#define AON_REG2X_OSC80M                            0x654
+#define AON_C_KOUT0X_OSC80M                         0x658
+#define AON_REG_SIMO_REG0X                          0x674
+#define AON_REG_SIMO_REG1X                          0x678
+#define AON_REG_SIMO_REG2X                          0x684
+#define AON_REG_SIMO_REG3X                          0x688
+#define AON_REG_SIMO_REG4X                          0x68C
+#define AON_REG_SIMO_REG5X                          0x690
+#define AON_REG_SIMO_REG6X                          0x694
+#define AON_REG_SIMO_REG7X                          0x698
+#define AON_REG_SIMO_REG8X                          0x69C
+#define AON_REG_SIMO_REG9X                          0x6A0
+#define AON_C_KOUT0X_SIMO                           0x6A4
+#define AON_C_KOUT1X_SIMO                           0x6A8
+#define AON_C_KOUT2X_SIMO                           0x6AC
+#define AON_REG_LDO_ANA_REG0X                       0x6D4
+#define AON_REG_LDO_PA_REG0X                        0x6E4
+#define AON_REG0X_PLL1                              0x6F4
+#define AON_REG2X_PLL1                              0x6F8
+#define AON_C_KOUT0X_PLL1                           0x6FC
+#define AON_REG0X_PLL1_LDO                          0x708
+#define AON_REG_TMETER_DATA_0                       0x728
+#define AON_REG_TMETER_DATA_1                       0x72C
+#define AON_REG_TMETER_DATA_2                       0x730
+#define AON_REG_TMETER_CTRL1                        0x738
+#define AON_REG_TMETER_COMP_CTRL                    0x73C
+#define AON_REG_TMETER_REL_COMP_THD0                0x740
+#define AON_REG_TMETER_REL_COMP_THD1                0x744
+#define AON_REG_TMETER_ABS_COMP0_VREF               0x748
+#define AON_REG_TMETER_ABS_COMP1_VREF               0x74C
+#define AON_REG_TMETER_ABS_COMP2_VREF               0x750
+#define AON_REG_TMETER_ABS_COMP3_VREF               0x754
+#define AON_REG_TMETER_ANALOG_CTRL                  0x758
+#define AON_REG_TMETER_MAPPING                      0x75C
+#define AON_REG_RTC_CR0                             0x768
+#define AON_REG_RTC_INT_clear                       0x76C
+#define AON_REG_RTC_INT_SR                          0x770
+#define AON_REG_RTC_PRESCALER                       0x774
+#define AON_REG_RTC_COMP_0                          0x778
+#define AON_REG_RTC_COMP_1                          0x77C
+#define AON_REG_RTC_COMP_2                          0x780
+#define AON_REG_RTC_COMP_3                          0x784
+#define AON_REG_RTC_CNT0                            0x788
+#define AON_REG_RTC_PRESCALE_CNT0                   0x78C
+#define AON_REG_RTC_PRESCALE_CMP0                   0x790
+#define AON_REG_RTC_BACKUP                          0x794
+#define AON_REG_RTC_RTL_VERSION0                    0x798
+#define AON_REG_RTC_RELOAD_CTRL                     0x79C
+#define AON_REG_RTC_COMP_0_RELOAD                   0x7A0
+#define AON_REG_RTC_COMP_1_RELOAD                   0x7A4
+#define AON_REG_RTC_COMP_2_RELOAD                   0x7A8
+#define AON_REG_RTC_COMP_3_RELOAD                   0x7AC
+#define AON_REG_RTC_TASK_CTRL                       0x7B0
+#define AON_REG_RTC_SHOT_CTRL                       0x7B4
+#define AON_REG_RTC_QACTIVE_CTRL                    0x7B8
+#define AON_REG_LPC_VERSION                         0x7C0
+#define AON_REG_LPC_CR0                             0x7C4
+#define AON_REG_LPC_SR                              0x7C8
+#define AON_REG_LPC_CMP                             0x7CC
+#define AON_REG_LPC_CNT                             0x7D0
+#define AON_REG_LPC_TASK_CTRL                       0x7D4
+#define AON_REG_LPC_SHOT_CTRL                       0x7D8
+#define AON_REG_LPC_QACTIVE_CTRL                    0x7DC
+#define AON_REG0X_SD                                0x7E0
+#define AON_REG_LPQDEC_X_DIV                        0x7E4
+#define AON_REG_LPQDEC_X_CONFIG                     0x7E8
+#define AON_REG_LPQDEC_X_SR_1                       0x7EC
+#define AON_REG_LPQDEC_X_SR_2                       0x7F0
+#define AON_REG_LPQDEC_X_INT_CLR                    0x7F4
+#define AON_REG_LPQDEC_X_VERSION                    0x7F8
+#define AON_REG_LPQDEC_X_LED_CTRL                   0x7FC
+#define AON_REG_LPQDEC_X_QACTIVE_CTRL               0x800
+#define AON_REG_LPPWM_CH0_CTL                       0x80C
+#define AON_REG_LPPWM_CH0_P0_H                      0x810
+#define AON_REG_LPPWM_CH0_P0_L                      0x814
+#define AON_REG_LPPWM_CH0_CURRENT                   0x818
+#define AON_REG_LPPWM_VERSION                       0x81C
+#define AON_REG_LPPWM_QACTIVE_MANUAL_CTRL           0x820
+#define AON_REG_SRAM_CTRL0                          0x828
+#define AON_REG_SRAM_CTRL1                          0x82C
+#define AON_REG_SRAM_CTRL2                          0x830
+#define AON_REG_SRAM_CTRL3                          0x834
+#define AON_REG_SRAM_CTRL4                          0x838
+#define AON_REG_SRAM_CTRL5                          0x83C
+#define AON_REG_SRAM_CTRL6                          0x840
+#define AON_REG_SRAM_CTRL7                          0x844
+#define AON_REG_SRAM_CTRL8                          0x848
+#define AON_REG_SRAM_CTRL9                          0x84C
+#define AON_REG_SRAM_CTRL10                         0x850
+#define AON_REG_SRAM_CTRL11                         0x854
+#define AON_REG_SRAM_CTRL12                         0x858
+#define AON_REG_SRAM_CTRL13                         0x85C
+#define AON_REG_SRAM_CTRL14                         0x860
+#define AON_REG_SRAM_CTRL15                         0x864
+#define AON_REG_SRAM_CTRL16                         0x868
+#define AON_REG_SRAM_CTRL17                         0x86C
+#define AON_REG_SRAM_CTRL18                         0x870
+#define AON_REG_SRAM_CTRL19                         0x874
+#define AON_REG_SRAM_CTRL20                         0x878
+#define AON_REG_SRAM_CTRL21                         0x87C
+#define AON_REG_SRAM_CTRL22                         0x880
+#define AON_REG_SRAM_CTRL23                         0x884
+#define AON_REG_SRAM_CTRL24                         0x888
+#define AON_REG_SRAM_CTRL25                         0x88C
+#define AON_REG_SRAM_CTRL27                         0x890
+#define AON_REG_SRAM_CTRL28                         0x894
+#define AON_REG_SRAM_CTRL29                         0x898
+#define AON_REG_SRAM_CTRL30                         0x89C
+#define AON_REG_SRAM_CTRL31                         0x8A0
+#define AON_REG_SRAM_CTRL32                         0x8A4
+#define AON_REG_SRAM_CTRL33                         0x8A8
+#define AON_REG_SRAM_CTRL34                         0x8AC
+#define AON_REG_SRAM_CTRL35                         0x8B0
+#define AON_REG_PCK600_AON_REG0X                    0x8B4
+#define AON_REG_PCK600_AON_REG1X                    0x8B8
+#define AON_REG_PCK600_AON_REG2X                    0x8BC
+#define AON_REG_PCK600_AON_REG3X                    0x8C0
+#define AON_REG_PCK600_AON_REG4X                    0x8C4
+#define AON_REG_PCK600_AON_REG5X                    0x8C8
+#define AON_REG_PCK600_VPON_REG0X                   0x8CC
+#define AON_REG_PCK600_VPON_REG1X                   0x8D0
+#define AON_REG_PCK600_VPON_REG2X                   0x8D4
+#define AON_REG_PCK600_VPON_REG3X                   0x8D8
+#define AON_REG_PCK600_VPON_REG4X                   0x8DC
+#define AON_REG_PCK600_VPON_REG5X                   0x8E0
+#define AON_REG_PCK600_VPON_REG6X                   0x8E4
+#define AON_BT_ANAPAR_LDO_ADDA                      0x718
+#define AON_REG_BT_ANAPAR_LDO_IQMDA                 0x71C
+#define AON_BT_TPMK_ADC_LDO                         0x720
+#define AON_LOP_PON_CLK_CTRL_OSC128K_OSC10_PCSM_1   0x9A4
+#define AON_LOP_PON_CLK_CTRL_OSC128K_OSC10_PCSM_2   0x9A8
+#define AON_LOP_PON_PPU_VPON_PCSM_1                 0x9AC
+#define AON_LOP_PON_PPU_VPON_PCSM_2                 0x9B0
+#define AON_LOP_PON_PPU_VPON_PCSM_3                 0x9B4
+#define AON_LOP_PON_PPU_VPON_PCSM_4                 0x9B8
+#define AON_LOP_PON_PPU_VPON_PCSM_5                 0x9BC
+#define AON_LOP_PON_PPU_VPON_PCSM_6                 0x9C0
+#define AON_LOP_PON_PPU_VPON_PCSM_7                 0x9C4
+#define AON_LOP_PON_PPU_VPON_PCSM_8                 0x9C8
+#define AON_LOP_PON_OTHER_PCSM_SWAP_PCSM_1          0x9CC
+#define AON_LOP_PON_OTHER_PCSM_SWAP_PCSM_2          0x9D0
+#define AON_LOP_POF_CLK_CTRL_OSC128K_OSC10_PCSM_1   0xA30
+#define AON_LOP_POF_CLK_CTRL_OSC128K_OSC10_PCSM_2   0xA34
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_1             0xA38
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_2             0xA3C
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_3             0xA40
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_4             0xA44
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_1         0xA48
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_2         0xA4C
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_3         0xA50
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_4         0xA54
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_1        0xA58
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_2        0xA5C
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_3        0xA60
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_4        0xA64
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_5        0xA68
+#define AON_LOP_POF_PPU_VPON_PCSM_DELAY             0xA6C
+#define AON_LOP_POF_PPU_VPON_PCSM_SHIP_DELAY        0xA70
+#define AON_LOP_POF_PPU_VPON_PCSM_DELAY_2           0xA74
+#define AON_LOP_POF_OTHER_PCSM_SWAP_PCSM_1          0xA78
+#define AON_LOP_POF_OTHER_PCSM_SWAP_PCSM_2          0xA7C
+#define AON_LOP_PON_VPON_40MXTAL_PCSM               0xB18
+#define AON_LOP_PON_VPON_OSC80_OSC80CG_PLL1_PCSM_1  0xB14
+#define AON_LOP_PON_VPON_OSC80_OSC80CG_PLL1_PCSM_2  0xB10
+#define AON_LOP_PON_PPUVCORE1_PCSM_1                0xB0C
+#define AON_LOP_PON_PPUVCORE1_PCSM_2                0xB08
+#define AON_LOP_PON_PPUVCORE1_PCSM_3                0xB04
+#define AON_LOP_PON_PPUVCORE1_PCSM_4                0xB00
+#define AON_LOP_PON_PPUVCORE1_PCSM_DELAY_1          0xAFC
+#define AON_LOP_POF_VPON_40MXTAL_PCSM               0xC08
+#define AON_LOP_POF_VPON_OSC80_OSC80CG_PLL1_PCSM_1  0xC04
+#define AON_LOP_POF_VPON_OSC80_OSC80CG_PLL1_PCSM_2  0xC00
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_1           0xBFC
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_2           0xBF8
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_3           0xBF4
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_4           0xBF0
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_1      0xBEC
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_2      0xBE8
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_3      0xBE4
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_4      0xBE0
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_1      0xBDC
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_2      0xBD8
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_3      0xBD4
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_4      0xBD0
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_DELAY_1     0xBCC
+#define AON_LOP_PON_VPON_VCORE1_OP1_PCSM_1          0xC2C
+#define AON_LOP_PON_VPON_VCORE1_OP1_PCSM_2          0xC28
+#define AON_LOP_POF_VPON_VCORE1_OP1_PCSM_1          0xC44
+#define AON_LOP_POF_VPON_VCORE1_OP1_PCSM_2          0xC40
+#define AON_REG_SCH_PLN_RSTB                        0xC60
+#define AON_REG_SCH_PLN_TREE0_ROOT_ACT_TIME         0xC64
+#define AON_REG_SCH_PLN_TREE1_ROOT_ACT_TIME         0xC68
+#define AON_REG_SCH_PLN_TREE_ACT_CLEAR              0xC6C
+#define AON_REG_SCH_PLN_MANUAL_TRIGGER              0xC70
+#define AON_REG_SCH_PLN_INTR_CTRL                   0xC74
+#define AON_REG_SCH_PLN_INTR_STATUS                 0xC78
+#define AON_REG_SCH_PLN_INTR_CLEAR                  0xC7C
+#define AON_REG_SCH_PLN_NODE_DISABLE                0xC80
+#define AON_REG_SCH_PLN_NODE_DISABLE_AUTO_BYPASS    0xC84
+#define AON_REG_SCH_PLN_CMPNT0_DELAY_PON            0xC88
+#define AON_REG_SCH_PLN_CMPNT0_DELAY_POF            0xC8C
+#define AON_REG_SCH_PLN_CMPNT1_DELAY_PON            0xC90
+#define AON_REG_SCH_PLN_CMPNT1_DELAY_POF            0xC94
+#define AON_REG_SCH_PLN_CMPNT2_DELAY_PON            0xC98
+#define AON_REG_SCH_PLN_CMPNT2_DELAY_POF            0xC9C
+#define AON_REG_SCH_PLN_CMPNT3_DELAY_PON            0xCA0
+#define AON_REG_SCH_PLN_CMPNT3_DELAY_POF            0xCA4
+#define AON_REG_SCH_PLN_CMPNT4_DELAY_PON            0xCA8
+#define AON_REG_SCH_PLN_CMPNT4_DELAY_POF            0xCAC
+#define AON_REG_SCH_PLN_CMPNT5_DELAY_PON            0xCB0
+#define AON_REG_SCH_PLN_CMPNT5_DELAY_POF            0xCB4
+#define AON_REG_SCH_PLN_CMPNT6_DELAY_PON            0xCB8
+#define AON_REG_SCH_PLN_CMPNT6_DELAY_POF            0xCBC
+#define AON_REG_SCH_PLN_CMPNT7_DELAY_PON            0xCC0
+#define AON_REG_SCH_PLN_CMPNT7_DELAY_POF            0xCC4
+#define AON_REG_SCH_PLN_CMPNT8_DELAY_PON            0xCC8
+#define AON_REG_SCH_PLN_CMPNT8_DELAY_POF            0xCCC
+#define AON_REG_SCH_PLN_CMPNT9_DELAY_PON            0xCD0
+#define AON_REG_SCH_PLN_CMPNT9_DELAY_POF            0xCD4
+#define AON_REG_SCH_PLN_QACTIVE_CTRL                0xCD8
+#define AON_REG_SCH_PLN_VERSION                     0xCDC
+#define AON_REG_SCH_PLN_TREE0_ROOT_CHECK_TIME       0xCE0
+#define AON_REG_SCH_PLN_TREE1_ROOT_CHECK_TIME       0xCE4
+#define AON_REG_GTC_CTRL                            0xCF0
+#define AON_REG_GTC_CNT                             0xCF4
+#define AON_REG_GTC_VERSION                         0xCF8
+#define AON_REG_GRTC_CTRL                           0xD04
+#define AON_REG_GRTC_INTR_CTRL                      0xD08
+#define AON_REG_GRTC_COMP_INTR_SR                   0xD0C
+#define AON_REG_GRTC_COMP_INT_CLR                   0xD10
+#define AON_REG_GRTC_COMP_0                         0xD14
+#define AON_REG_GRTC_COMP_1                         0xD18
+#define AON_REG_GRTC_COMP_2                         0xD1C
+#define AON_REG_GRTC_COMP_3                         0xD20
+#define AON_REG_GRTC_COMP_4                         0xD24
+#define AON_REG_GRTC_COMP_5                         0xD28
+#define AON_REG_GRTC_COMP_6                         0xD2C
+#define AON_REG_GRTC_COMP_7                         0xD30
+#define AON_REG_GRTC_RELOAD_CTRL                    0xD34
+#define AON_REG_GRTC_COMP_0_RELOAD                  0xD38
+#define AON_REG_GRTC_COMP_1_RELOAD                  0xD3C
+#define AON_REG_GRTC_COMP_2_RELOAD                  0xD40
+#define AON_REG_GRTC_COMP_3_RELOAD                  0xD44
+#define AON_REG_GRTC_COMP_4_RELOAD                  0xD48
+#define AON_REG_GRTC_COMP_5_RELOAD                  0xD4C
+#define AON_REG_GRTC_COMP_6_RELOAD                  0xD50
+#define AON_REG_GRTC_COMP_7_RELOAD                  0xD54
+#define AON_REG_GRTC_SLEEP_CTRL                     0xD58
+#define AON_REG_GRTC_COMP_0_SLEEP_PENDING_CNT       0xD5C
+#define AON_REG_GRTC_COMP_1_SLEEP_PENDING_CNT       0xD60
+#define AON_REG_GRTC_COMP_2_SLEEP_PENDING_CNT       0xD64
+#define AON_REG_GRTC_COMP_3_SLEEP_PENDING_CNT       0xD68
+#define AON_REG_GRTC_COMP_4_SLEEP_PENDING_CNT       0xD6C
+#define AON_REG_GRTC_COMP_5_SLEEP_PENDING_CNT       0xD70
+#define AON_REG_GRTC_COMP_6_SLEEP_PENDING_CNT       0xD74
+#define AON_REG_GRTC_COMP_7_SLEEP_PENDING_CNT       0xD78
+#define AON_REG_GRTC_TASK_CTRL                      0xD7C
+#define AON_REG_GRTC_QACTIVE_CTRL                   0xD80
+#define AON_REG_GRTC_RTL_VERSION                    0xD84
+#define AON_REG_GRTC_COMP_TIMEOUT_OV_ERR_SR         0xD88
+#define AON_REG_GRTC_COMP_TIMEOUT_OV_ERR_CLR        0xD8C
+#define AON_REG0X_OSC80M_CAL                        0xDB4
+#define AON_REG2X_OSC80M_CAL                        0xDB8
+#define AON_REG4X_OSC80M_CAL                        0xDBC
+#define AON_REG6X_OSC80M_CAL                        0xDC0
+#define AON_REG8X_OSC80M_CAL                        0xDC4
+#define AON_REG10X_OSC80M_CAL                       0xDC8
+#define AON_REG_OSC80M_CAL_RAP                      0xDCC
+#define AON_REG_OSC80M_CAL_QCH                      0xDD0
+#define AON_REG0X_OSC10M_CAL                        0xDF0
+#define AON_REG2X_OSC10M_CAL                        0xDF4
+#define AON_REG4X_OSC10M_CAL                        0xDF8
+#define AON_REG6X_OSC10M_CAL                        0xDFC
+#define AON_REG8X_OSC10M_CAL                        0xE00
+#define AON_REG10X_OSC10M_CAL                       0xE04
+#define AON_REG_OSC10M_CAL_RAP                      0xE08
+#define AON_REG_OSC10M_CAL_QCH                      0xE0C
+#define AON_REG_DEB_MUX_SEL                         0xE2C
+#define AON_REG_DEB_CNT_1_0                         0xE30
+#define AON_REG_DEB_CNT_3_2                         0xE34
+#define AON_REG_DEB_CNT_4                           0xE38
+#define AON_REG_DEB_STS                             0xE3C
+#define AON_REG_PAD_AUTO_SW_AON_REG0X               0xE90
+#define AON_REG_PAD_AUTO_SW_AON_REG1X               0xE94
+#define AON_REG_PAD_AUTO_SW_AON_REG2X               0xE98
+#define AON_REG_PAD_AUTO_SW_AON_REG3X               0xE9C
+#define AON_REG_PAD_AUTO_SW_AON_REG4X               0xEA0
+#define AON_REG_PAD_AUTO_SW_AON_REG5X               0xEA4
+#define AON_REG_PAD_AUTO_SW_AON_REG6X               0xEA8
+#define AON_REG_PAD_AUTO_SW_AON_REG7X               0xEAC
+#define AON_REG_PAD_AUTO_SW_AON_REG8X               0xEB0
+#define AON_REG_PAD_AUTO_SW_AON_REG9X               0xEB4
+#define AON_REG_PAD_AUTO_SW_PON_REG0X               0xEC4
+#define AON_REG_PAD_AUTO_SW_PON_REG1X               0xEC8
+#define AON_REG_PAD_AUTO_SW_PON_REG2X               0xECC
+#define AON_REG_PAD_AUTO_SW_PON_REG3X               0xED0
+#define AON_REG_PAD_AUTO_SW_PON_REG4X               0xED4
+#define AON_REG_PAD_AUTO_SW_PON_REG5X               0xED8
+#define AON_REG_PAD_AUTO_SW_PON_REG6X               0xEDC
+#define AON_REG_PAD_AUTO_SW_PON_REG7X               0xEE0
+
+/* 0x0      0x4000_0000
+    28:0    R/W     RESERVED                                                    29'h0
+    29      R/W     AON_GATED_EN                                                1'b1
+    30      R/W     VCORE_PC_VG2                                                1'b1
+    31      R/W     VCORE_PC_VG1                                                1'b1
+ */
+typedef union _AON_REG_SYSTEM_REG0X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED: 29;
+        uint32_t AON_GATED_EN: 1;
+        uint32_t VCORE_PC_VG2: 1;
+        uint32_t VCORE_PC_VG1: 1;
+    };
+} AON_REG_SYSTEM_REG0X_TYPE;
+
+/*0x4000_0000 AON_REG_SYSTEM_REG0X*/
+#define AON_REG_SYSTEM_REG0X_RESERVED_Pos                                                                                0U
+#define AON_REG_SYSTEM_REG0X_RESERVED_Msk                                                                                (0x1FFFFFFFUL << AON_REG_SYSTEM_REG0X_RESERVED_Pos)
+
+#define AON_REG_SYSTEM_REG0X_AON_GATED_EN_Pos                                                                            29U
+#define AON_REG_SYSTEM_REG0X_AON_GATED_EN_Msk                                                                            (0x1UL << AON_REG_SYSTEM_REG0X_AON_GATED_EN_Pos)
+
+#define AON_REG_SYSTEM_REG0X_VCORE_PC_VG2_Pos                                                                            30U
+#define AON_REG_SYSTEM_REG0X_VCORE_PC_VG2_Msk                                                                            (0x1UL << AON_REG_SYSTEM_REG0X_VCORE_PC_VG2_Pos)
+
+#define AON_REG_SYSTEM_REG0X_VCORE_PC_VG1_Pos                                                                            31U
+#define AON_REG_SYSTEM_REG0X_VCORE_PC_VG1_Msk                                                                            (0x1UL << AON_REG_SYSTEM_REG0X_VCORE_PC_VG1_Pos)
+
+/* 0x4      0x4000_0004
+    7:0     R/W     DEBUG_SEL                                                   8'h0
+    31:8    R       RESERVED                                                    24'h0
+ */
+typedef union _AON_REG_SYSTEM_REG1X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t DEBUG_SEL: 8;
+        uint32_t RESERVED: 24;
+    };
+} AON_REG_SYSTEM_REG1X_TYPE;
+
+/*0x4000_0004 AON_REG_SYSTEM_REG1X*/
+#define AON_REG_SYSTEM_REG1X_DEBUG_SEL_Pos                                                                               0U
+#define AON_REG_SYSTEM_REG1X_DEBUG_SEL_Msk                                                                               (0xFFUL << AON_REG_SYSTEM_REG1X_DEBUG_SEL_Pos)
+
+#define AON_REG_SYSTEM_REG1X_RESERVED_Pos                                                                                8U
+#define AON_REG_SYSTEM_REG1X_RESERVED_Msk                                                                                (0xFFFFFFUL << AON_REG_SYSTEM_REG1X_RESERVED_Pos)
+
+/* 0x8      0x4000_0008
+    31:0    R       RESERVED                                                    32'h0
+ */
+typedef union _AON_REG_SYSTEM_REG2X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED;
+    };
+} AON_REG_SYSTEM_REG2X_TYPE;
+
+/*0x4000_0008 AON_REG_SYSTEM_REG2X*/
+#define AON_REG_SYSTEM_REG2X_RESERVED_Pos                                                                                0U
+#define AON_REG_SYSTEM_REG2X_RESERVED_Msk                                                                                (0xFFFFFFFFUL << AON_REG_SYSTEM_REG2X_RESERVED_Pos)
+
+/* 0xC      0x4000_000c
+    31:0    R       RESERVED                                                    32'h0
+ */
+typedef union _AON_REG_SYSTEM_REG3X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED;
+    };
+} AON_REG_SYSTEM_REG3X_TYPE;
+
+/*0x4000_000c AON_REG_SYSTEM_REG3X*/
+#define AON_REG_SYSTEM_REG3X_RESERVED_Pos                                                                                0U
+#define AON_REG_SYSTEM_REG3X_RESERVED_Msk                                                                                (0xFFFFFFFFUL << AON_REG_SYSTEM_REG3X_RESERVED_Pos)
+
+/* 0x10     0x4000_0010
+    8:0     R/W     RESERVED                                                    9'h0
+    9       W1C     MBISR2_RESTORE                                              1'b0
+    10      W1C     PERIPHERAL_ALL_STORE                                        1'b0
+    11      W1C     PERIPHERAL_ALL_RESTORE                                      1'b0
+    12      W1C     RFC_STORE                                                   1'b0
+    13      W1C     RFC_RESTORE                                                 1'b0
+    14      W1C     MODEM_STORE                                                 1'b0
+    15      W1C     MODEM_RESTORE                                               1'b0
+    16      W1C     BZ_STORE                                                    1'b0
+    17      W1C     BZ_RESTORE                                                  1'b0
+    18      W1C     BLE_STORE                                                   1'b0
+    19      W1C     BLE_RESTORE                                                 1'b0
+    20      W1C     PF_STORE                                                    1'b0
+    21      W1C     PF_RESTORE                                                  1'b0
+    22      W1C     DP_MODEM_STORE                                              1'b0
+    23      W1C     DP_MODEM_RESTORE                                            1'b0
+    24      R       BT_CORE_RSTB                                                1'b0
+    25      R       BT_PON_RSTB                                                 1'b0
+    26      R       BT_RET_RSTB                                                 1'b0
+    27      R/W     ISO_XTAL                                                    1'b1
+    28      R       ISO_BT_CORE                                                 1'b1
+    29      R       ISO_BT_PON                                                  1'b1
+    30      R/W     ISO_EFLASH2VCORE                                            1'b1
+    31      R/W     ISO_PLL                                                     1'b1
+ */
+typedef union _AON_REG_SYSTEM_REG4X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED: 9;
+        uint32_t MBISR2_RESTORE: 1;
+        uint32_t PERIPHERAL_ALL_STORE: 1;
+        uint32_t PERIPHERAL_ALL_RESTORE: 1;
+        uint32_t RFC_STORE: 1;
+        uint32_t RFC_RESTORE: 1;
+        uint32_t MODEM_STORE: 1;
+        uint32_t MODEM_RESTORE: 1;
+        uint32_t BZ_STORE: 1;
+        uint32_t BZ_RESTORE: 1;
+        uint32_t BLE_STORE: 1;
+        uint32_t BLE_RESTORE: 1;
+        uint32_t PF_STORE: 1;
+        uint32_t PF_RESTORE: 1;
+        uint32_t DP_MODEM_STORE: 1;
+        uint32_t DP_MODEM_RESTORE: 1;
+        uint32_t BT_CORE_RSTB: 1;
+        uint32_t BT_PON_RSTB: 1;
+        uint32_t BT_RET_RSTB: 1;
+        uint32_t ISO_XTAL: 1;
+        uint32_t ISO_BT_CORE: 1;
+        uint32_t ISO_BT_PON: 1;
+        uint32_t ISO_EFLASH2VCORE: 1;
+        uint32_t ISO_PLL: 1;
+    };
+} AON_REG_SYSTEM_REG4X_TYPE;
+
+/*0x4000_0010 AON_REG_SYSTEM_REG4X*/
+#define AON_REG_SYSTEM_REG4X_RESERVED_Pos                                                                                0U
+#define AON_REG_SYSTEM_REG4X_RESERVED_Msk                                                                                (0x1FFUL << AON_REG_SYSTEM_REG4X_RESERVED_Pos)
+
+#define AON_REG_SYSTEM_REG4X_MBISR2_RESTORE_Pos                                                                          9U
+#define AON_REG_SYSTEM_REG4X_MBISR2_RESTORE_Msk                                                                          (0x1UL << AON_REG_SYSTEM_REG4X_MBISR2_RESTORE_Pos)
+
+#define AON_REG_SYSTEM_REG4X_PERIPHERAL_ALL_STORE_Pos                                                                    10U
+#define AON_REG_SYSTEM_REG4X_PERIPHERAL_ALL_STORE_Msk                                                                    (0x1UL << AON_REG_SYSTEM_REG4X_PERIPHERAL_ALL_STORE_Pos)
+
+#define AON_REG_SYSTEM_REG4X_PERIPHERAL_ALL_RESTORE_Pos                                                                  11U
+#define AON_REG_SYSTEM_REG4X_PERIPHERAL_ALL_RESTORE_Msk                                                                  (0x1UL << AON_REG_SYSTEM_REG4X_PERIPHERAL_ALL_RESTORE_Pos)
+
+#define AON_REG_SYSTEM_REG4X_RFC_STORE_Pos                                                                               12U
+#define AON_REG_SYSTEM_REG4X_RFC_STORE_Msk                                                                               (0x1UL << AON_REG_SYSTEM_REG4X_RFC_STORE_Pos)
+
+#define AON_REG_SYSTEM_REG4X_RFC_RESTORE_Pos                                                                             13U
+#define AON_REG_SYSTEM_REG4X_RFC_RESTORE_Msk                                                                             (0x1UL << AON_REG_SYSTEM_REG4X_RFC_RESTORE_Pos)
+
+#define AON_REG_SYSTEM_REG4X_MODEM_STORE_Pos                                                                             14U
+#define AON_REG_SYSTEM_REG4X_MODEM_STORE_Msk                                                                             (0x1UL << AON_REG_SYSTEM_REG4X_MODEM_STORE_Pos)
+
+#define AON_REG_SYSTEM_REG4X_MODEM_RESTORE_Pos                                                                           15U
+#define AON_REG_SYSTEM_REG4X_MODEM_RESTORE_Msk                                                                           (0x1UL << AON_REG_SYSTEM_REG4X_MODEM_RESTORE_Pos)
+
+#define AON_REG_SYSTEM_REG4X_BZ_STORE_Pos                                                                                16U
+#define AON_REG_SYSTEM_REG4X_BZ_STORE_Msk                                                                                (0x1UL << AON_REG_SYSTEM_REG4X_BZ_STORE_Pos)
+
+#define AON_REG_SYSTEM_REG4X_BZ_RESTORE_Pos                                                                              17U
+#define AON_REG_SYSTEM_REG4X_BZ_RESTORE_Msk                                                                              (0x1UL << AON_REG_SYSTEM_REG4X_BZ_RESTORE_Pos)
+
+#define AON_REG_SYSTEM_REG4X_BLE_STORE_Pos                                                                               18U
+#define AON_REG_SYSTEM_REG4X_BLE_STORE_Msk                                                                               (0x1UL << AON_REG_SYSTEM_REG4X_BLE_STORE_Pos)
+
+#define AON_REG_SYSTEM_REG4X_BLE_RESTORE_Pos                                                                             19U
+#define AON_REG_SYSTEM_REG4X_BLE_RESTORE_Msk                                                                             (0x1UL << AON_REG_SYSTEM_REG4X_BLE_RESTORE_Pos)
+
+#define AON_REG_SYSTEM_REG4X_PF_STORE_Pos                                                                                20U
+#define AON_REG_SYSTEM_REG4X_PF_STORE_Msk                                                                                (0x1UL << AON_REG_SYSTEM_REG4X_PF_STORE_Pos)
+
+#define AON_REG_SYSTEM_REG4X_PF_RESTORE_Pos                                                                              21U
+#define AON_REG_SYSTEM_REG4X_PF_RESTORE_Msk                                                                              (0x1UL << AON_REG_SYSTEM_REG4X_PF_RESTORE_Pos)
+
+#define AON_REG_SYSTEM_REG4X_DP_MODEM_STORE_Pos                                                                          22U
+#define AON_REG_SYSTEM_REG4X_DP_MODEM_STORE_Msk                                                                          (0x1UL << AON_REG_SYSTEM_REG4X_DP_MODEM_STORE_Pos)
+
+#define AON_REG_SYSTEM_REG4X_DP_MODEM_RESTORE_Pos                                                                        23U
+#define AON_REG_SYSTEM_REG4X_DP_MODEM_RESTORE_Msk                                                                        (0x1UL << AON_REG_SYSTEM_REG4X_DP_MODEM_RESTORE_Pos)
+
+#define AON_REG_SYSTEM_REG4X_BT_CORE_RSTB_Pos                                                                            24U
+#define AON_REG_SYSTEM_REG4X_BT_CORE_RSTB_Msk                                                                            (0x1UL << AON_REG_SYSTEM_REG4X_BT_CORE_RSTB_Pos)
+
+#define AON_REG_SYSTEM_REG4X_BT_PON_RSTB_Pos                                                                             25U
+#define AON_REG_SYSTEM_REG4X_BT_PON_RSTB_Msk                                                                             (0x1UL << AON_REG_SYSTEM_REG4X_BT_PON_RSTB_Pos)
+
+#define AON_REG_SYSTEM_REG4X_BT_RET_RSTB_Pos                                                                             26U
+#define AON_REG_SYSTEM_REG4X_BT_RET_RSTB_Msk                                                                             (0x1UL << AON_REG_SYSTEM_REG4X_BT_RET_RSTB_Pos)
+
+#define AON_REG_SYSTEM_REG4X_ISO_XTAL_Pos                                                                                27U
+#define AON_REG_SYSTEM_REG4X_ISO_XTAL_Msk                                                                                (0x1UL << AON_REG_SYSTEM_REG4X_ISO_XTAL_Pos)
+
+#define AON_REG_SYSTEM_REG4X_ISO_BT_CORE_Pos                                                                             28U
+#define AON_REG_SYSTEM_REG4X_ISO_BT_CORE_Msk                                                                             (0x1UL << AON_REG_SYSTEM_REG4X_ISO_BT_CORE_Pos)
+
+#define AON_REG_SYSTEM_REG4X_ISO_BT_PON_Pos                                                                              29U
+#define AON_REG_SYSTEM_REG4X_ISO_BT_PON_Msk                                                                              (0x1UL << AON_REG_SYSTEM_REG4X_ISO_BT_PON_Pos)
+
+#define AON_REG_SYSTEM_REG4X_ISO_EFLASH2VCORE_Pos                                                                        30U
+#define AON_REG_SYSTEM_REG4X_ISO_EFLASH2VCORE_Msk                                                                        (0x1UL << AON_REG_SYSTEM_REG4X_ISO_EFLASH2VCORE_Pos)
+
+#define AON_REG_SYSTEM_REG4X_ISO_PLL_Pos                                                                                 31U
+#define AON_REG_SYSTEM_REG4X_ISO_PLL_Msk                                                                                 (0x1UL << AON_REG_SYSTEM_REG4X_ISO_PLL_Pos)
+
+/* 0x14     0x4000_0014
+    0       R/W     FW_ENTER_LPS                                                1'b0
+    1       R/W     FW_PON_SEQ_RST_N                                            1'b0
+    19:2    R/W     RESERVED_1                                                  18'h0
+    20      W1C     DMAC_STORE                                                  1'b0
+    21      W1C     DMAC_RESTORE                                                1'b0
+    22      W1C     CM33_STORE                                                  1'b0
+    23      W1C     CM33_RESTORE                                                1'b0
+    31:24   R/W     RESERVED                                                    8'h0
+ */
+typedef union _AON_REG_SYSTEM_REG5X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t FW_ENTER_LPS: 1;
+        uint32_t FW_PON_SEQ_RST_N: 1;
+        uint32_t RESERVED_1: 18;
+        uint32_t DMAC_STORE: 1;
+        uint32_t DMAC_RESTORE: 1;
+        uint32_t CM33_STORE: 1;
+        uint32_t CM33_RESTORE: 1;
+        uint32_t RESERVED: 8;
+    };
+} AON_REG_SYSTEM_REG5X_TYPE;
+
+/*0x4000_0014 AON_REG_SYSTEM_REG5X*/
+#define AON_REG_SYSTEM_REG5X_FW_ENTER_LPS_Pos                                                                            0U
+#define AON_REG_SYSTEM_REG5X_FW_ENTER_LPS_Msk                                                                            (0x1UL << AON_REG_SYSTEM_REG5X_FW_ENTER_LPS_Pos)
+
+#define AON_REG_SYSTEM_REG5X_FW_PON_SEQ_RST_N_Pos                                                                        1U
+#define AON_REG_SYSTEM_REG5X_FW_PON_SEQ_RST_N_Msk                                                                        (0x1UL << AON_REG_SYSTEM_REG5X_FW_PON_SEQ_RST_N_Pos)
+
+#define AON_REG_SYSTEM_REG5X_RESERVED_1_Pos                                                                              2U
+#define AON_REG_SYSTEM_REG5X_RESERVED_1_Msk                                                                              (0x3FFFFUL << AON_REG_SYSTEM_REG5X_RESERVED_1_Pos)
+
+#define AON_REG_SYSTEM_REG5X_DMAC_STORE_Pos                                                                              20U
+#define AON_REG_SYSTEM_REG5X_DMAC_STORE_Msk                                                                              (0x1UL << AON_REG_SYSTEM_REG5X_DMAC_STORE_Pos)
+
+#define AON_REG_SYSTEM_REG5X_DMAC_RESTORE_Pos                                                                            21U
+#define AON_REG_SYSTEM_REG5X_DMAC_RESTORE_Msk                                                                            (0x1UL << AON_REG_SYSTEM_REG5X_DMAC_RESTORE_Pos)
+
+#define AON_REG_SYSTEM_REG5X_CM33_STORE_Pos                                                                              22U
+#define AON_REG_SYSTEM_REG5X_CM33_STORE_Msk                                                                              (0x1UL << AON_REG_SYSTEM_REG5X_CM33_STORE_Pos)
+
+#define AON_REG_SYSTEM_REG5X_CM33_RESTORE_Pos                                                                            23U
+#define AON_REG_SYSTEM_REG5X_CM33_RESTORE_Msk                                                                            (0x1UL << AON_REG_SYSTEM_REG5X_CM33_RESTORE_Pos)
+
+#define AON_REG_SYSTEM_REG5X_RESERVED_Pos                                                                                24U
+#define AON_REG_SYSTEM_REG5X_RESERVED_Msk                                                                                (0xFFUL << AON_REG_SYSTEM_REG5X_RESERVED_Pos)
+
+/* 0x18     0x4000_0018
+    0       W1C     MBISR_STORE                                                 1'b0
+    1       W1C     MBISR_RESTORE                                               1'b0
+    2       W1C     VENDOR_STORE                                                1'b0
+    3       W1C     VENDOR_RESTORE                                              1'b0
+    4       W1C     SYSON_STORE                                                 1'b0
+    5       W1C     SYSON_RESTORE                                               1'b0
+    6       W1C     EFLASH_STORE                                                1'b0
+    7       W1C     EFLASH_RESTORE                                              1'b0
+    13:8    R/W     RESERVED_1                                                  6'h0
+    14      R/W     WAIT_OK_80M                                                 1'b0
+    15      R/W     WAIT_CP_DIS_OUT                                             1'b0
+    16      R/W     WAIT_XTAL_CLK_OK                                            1'b0
+    17      R/W     WAIT_PLL1_READY                                             1'b0
+    18      R/W     WAIT_VDDCORE_DET_READY                                      1'b0
+    19      R/W     WAIT_VANA_DET_READY                                         1'b0
+    20      R/W     WAIT_VDDANA_DET_READY                                       1'b0
+    21      R/W     WAIT_VDDPA_DET_READY                                        1'b0
+    22      R/W     WAIT_HV18_DET_READY                                         1'b0
+    23      R/W     RESERVED                                                    1'b0
+    24      R/W     WAIT_32KOSC_CLK_OK                                          1'b0
+    25      R/W     WAIT_10MOSC_CLK_OK                                          1'b0
+    26      R/W     LDO_ANA_POS_EN_DR_FIX                                       1'b0
+    27      R/W     LDO_PA_POS_EN_DR_FIX                                        1'b0
+    28      R/W     EN_BUCK_BOOST_VDDPA_SYNC_SWITCH                             1'b0
+    29      R/W     EN_LDOPA_VOUT_SWITCH                                        1'b0
+    30      R/W     BUCK_BOOST_VDDPA_POS_EN_DR_FIX                              1'b0
+    31      R/W     BUCK_BOOST_HV18_POS_EN_DR_FIX                               1'b0
+ */
+typedef union _AON_REG_SYSTEM_REG6X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t MBISR_STORE: 1;
+        uint32_t MBISR_RESTORE: 1;
+        uint32_t VENDOR_STORE: 1;
+        uint32_t VENDOR_RESTORE: 1;
+        uint32_t SYSON_STORE: 1;
+        uint32_t SYSON_RESTORE: 1;
+        uint32_t EFLASH_STORE: 1;
+        uint32_t EFLASH_RESTORE: 1;
+        uint32_t RESERVED_1: 6;
+        uint32_t WAIT_OK_80M: 1;
+        uint32_t WAIT_CP_DIS_OUT: 1;
+        uint32_t WAIT_XTAL_CLK_OK: 1;
+        uint32_t WAIT_PLL1_READY: 1;
+        uint32_t WAIT_VDDCORE_DET_READY: 1;
+        uint32_t WAIT_VANA_DET_READY: 1;
+        uint32_t WAIT_VDDANA_DET_READY: 1;
+        uint32_t WAIT_VDDPA_DET_READY: 1;
+        uint32_t WAIT_HV18_DET_READY: 1;
+        uint32_t RESERVED: 1;
+        uint32_t WAIT_32KOSC_CLK_OK: 1;
+        uint32_t WAIT_10MOSC_CLK_OK: 1;
+        uint32_t LDO_ANA_POS_EN_DR_FIX: 1;
+        uint32_t LDO_PA_POS_EN_DR_FIX: 1;
+        uint32_t EN_BUCK_BOOST_VDDPA_SYNC_SWITCH: 1;
+        uint32_t EN_LDOPA_VOUT_SWITCH: 1;
+        uint32_t BUCK_BOOST_VDDPA_POS_EN_DR_FIX: 1;
+        uint32_t BUCK_BOOST_HV18_POS_EN_DR_FIX: 1;
+    };
+} AON_REG_SYSTEM_REG6X_TYPE;
+
+/*0x4000_0018 AON_REG_SYSTEM_REG6X*/
+#define AON_REG_SYSTEM_REG6X_MBISR_STORE_Pos                                                                             0U
+#define AON_REG_SYSTEM_REG6X_MBISR_STORE_Msk                                                                             (0x1UL << AON_REG_SYSTEM_REG6X_MBISR_STORE_Pos)
+
+#define AON_REG_SYSTEM_REG6X_MBISR_RESTORE_Pos                                                                           1U
+#define AON_REG_SYSTEM_REG6X_MBISR_RESTORE_Msk                                                                           (0x1UL << AON_REG_SYSTEM_REG6X_MBISR_RESTORE_Pos)
+
+#define AON_REG_SYSTEM_REG6X_VENDOR_STORE_Pos                                                                            2U
+#define AON_REG_SYSTEM_REG6X_VENDOR_STORE_Msk                                                                            (0x1UL << AON_REG_SYSTEM_REG6X_VENDOR_STORE_Pos)
+
+#define AON_REG_SYSTEM_REG6X_VENDOR_RESTORE_Pos                                                                          3U
+#define AON_REG_SYSTEM_REG6X_VENDOR_RESTORE_Msk                                                                          (0x1UL << AON_REG_SYSTEM_REG6X_VENDOR_RESTORE_Pos)
+
+#define AON_REG_SYSTEM_REG6X_SYSON_STORE_Pos                                                                             4U
+#define AON_REG_SYSTEM_REG6X_SYSON_STORE_Msk                                                                             (0x1UL << AON_REG_SYSTEM_REG6X_SYSON_STORE_Pos)
+
+#define AON_REG_SYSTEM_REG6X_SYSON_RESTORE_Pos                                                                           5U
+#define AON_REG_SYSTEM_REG6X_SYSON_RESTORE_Msk                                                                           (0x1UL << AON_REG_SYSTEM_REG6X_SYSON_RESTORE_Pos)
+
+#define AON_REG_SYSTEM_REG6X_EFLASH_STORE_Pos                                                                            6U
+#define AON_REG_SYSTEM_REG6X_EFLASH_STORE_Msk                                                                            (0x1UL << AON_REG_SYSTEM_REG6X_EFLASH_STORE_Pos)
+
+#define AON_REG_SYSTEM_REG6X_EFLASH_RESTORE_Pos                                                                          7U
+#define AON_REG_SYSTEM_REG6X_EFLASH_RESTORE_Msk                                                                          (0x1UL << AON_REG_SYSTEM_REG6X_EFLASH_RESTORE_Pos)
+
+#define AON_REG_SYSTEM_REG6X_RESERVED_1_Pos                                                                              8U
+#define AON_REG_SYSTEM_REG6X_RESERVED_1_Msk                                                                              (0x3FUL << AON_REG_SYSTEM_REG6X_RESERVED_1_Pos)
+
+#define AON_REG_SYSTEM_REG6X_WAIT_OK_80M_Pos                                                                             14U
+#define AON_REG_SYSTEM_REG6X_WAIT_OK_80M_Msk                                                                             (0x1UL << AON_REG_SYSTEM_REG6X_WAIT_OK_80M_Pos)
+
+#define AON_REG_SYSTEM_REG6X_WAIT_CP_DIS_OUT_Pos                                                                         15U
+#define AON_REG_SYSTEM_REG6X_WAIT_CP_DIS_OUT_Msk                                                                         (0x1UL << AON_REG_SYSTEM_REG6X_WAIT_CP_DIS_OUT_Pos)
+
+#define AON_REG_SYSTEM_REG6X_WAIT_XTAL_CLK_OK_Pos                                                                        16U
+#define AON_REG_SYSTEM_REG6X_WAIT_XTAL_CLK_OK_Msk                                                                        (0x1UL << AON_REG_SYSTEM_REG6X_WAIT_XTAL_CLK_OK_Pos)
+
+#define AON_REG_SYSTEM_REG6X_WAIT_PLL1_READY_Pos                                                                         17U
+#define AON_REG_SYSTEM_REG6X_WAIT_PLL1_READY_Msk                                                                         (0x1UL << AON_REG_SYSTEM_REG6X_WAIT_PLL1_READY_Pos)
+
+#define AON_REG_SYSTEM_REG6X_WAIT_VDDCORE_DET_READY_Pos                                                                  18U
+#define AON_REG_SYSTEM_REG6X_WAIT_VDDCORE_DET_READY_Msk                                                                  (0x1UL << AON_REG_SYSTEM_REG6X_WAIT_VDDCORE_DET_READY_Pos)
+
+#define AON_REG_SYSTEM_REG6X_WAIT_VANA_DET_READY_Pos                                                                     19U
+#define AON_REG_SYSTEM_REG6X_WAIT_VANA_DET_READY_Msk                                                                     (0x1UL << AON_REG_SYSTEM_REG6X_WAIT_VANA_DET_READY_Pos)
+
+#define AON_REG_SYSTEM_REG6X_WAIT_VDDANA_DET_READY_Pos                                                                   20U
+#define AON_REG_SYSTEM_REG6X_WAIT_VDDANA_DET_READY_Msk                                                                   (0x1UL << AON_REG_SYSTEM_REG6X_WAIT_VDDANA_DET_READY_Pos)
+
+#define AON_REG_SYSTEM_REG6X_WAIT_VDDPA_DET_READY_Pos                                                                    21U
+#define AON_REG_SYSTEM_REG6X_WAIT_VDDPA_DET_READY_Msk                                                                    (0x1UL << AON_REG_SYSTEM_REG6X_WAIT_VDDPA_DET_READY_Pos)
+
+#define AON_REG_SYSTEM_REG6X_WAIT_HV18_DET_READY_Pos                                                                     22U
+#define AON_REG_SYSTEM_REG6X_WAIT_HV18_DET_READY_Msk                                                                     (0x1UL << AON_REG_SYSTEM_REG6X_WAIT_HV18_DET_READY_Pos)
+
+#define AON_REG_SYSTEM_REG6X_RESERVED_Pos                                                                                23U
+#define AON_REG_SYSTEM_REG6X_RESERVED_Msk                                                                                (0x1UL << AON_REG_SYSTEM_REG6X_RESERVED_Pos)
+
+#define AON_REG_SYSTEM_REG6X_WAIT_32KOSC_CLK_OK_Pos                                                                      24U
+#define AON_REG_SYSTEM_REG6X_WAIT_32KOSC_CLK_OK_Msk                                                                      (0x1UL << AON_REG_SYSTEM_REG6X_WAIT_32KOSC_CLK_OK_Pos)
+
+#define AON_REG_SYSTEM_REG6X_WAIT_10MOSC_CLK_OK_Pos                                                                      25U
+#define AON_REG_SYSTEM_REG6X_WAIT_10MOSC_CLK_OK_Msk                                                                      (0x1UL << AON_REG_SYSTEM_REG6X_WAIT_10MOSC_CLK_OK_Pos)
+
+#define AON_REG_SYSTEM_REG6X_LDO_ANA_POS_EN_DR_FIX_Pos                                                                   26U
+#define AON_REG_SYSTEM_REG6X_LDO_ANA_POS_EN_DR_FIX_Msk                                                                   (0x1UL << AON_REG_SYSTEM_REG6X_LDO_ANA_POS_EN_DR_FIX_Pos)
+
+#define AON_REG_SYSTEM_REG6X_LDO_PA_POS_EN_DR_FIX_Pos                                                                    27U
+#define AON_REG_SYSTEM_REG6X_LDO_PA_POS_EN_DR_FIX_Msk                                                                    (0x1UL << AON_REG_SYSTEM_REG6X_LDO_PA_POS_EN_DR_FIX_Pos)
+
+#define AON_REG_SYSTEM_REG6X_EN_BUCK_BOOST_VDDPA_SYNC_SWITCH_Pos                                                         28U
+#define AON_REG_SYSTEM_REG6X_EN_BUCK_BOOST_VDDPA_SYNC_SWITCH_Msk                                                         (0x1UL << AON_REG_SYSTEM_REG6X_EN_BUCK_BOOST_VDDPA_SYNC_SWITCH_Pos)
+
+#define AON_REG_SYSTEM_REG6X_EN_LDOPA_VOUT_SWITCH_Pos                                                                    29U
+#define AON_REG_SYSTEM_REG6X_EN_LDOPA_VOUT_SWITCH_Msk                                                                    (0x1UL << AON_REG_SYSTEM_REG6X_EN_LDOPA_VOUT_SWITCH_Pos)
+
+#define AON_REG_SYSTEM_REG6X_BUCK_BOOST_VDDPA_POS_EN_DR_FIX_Pos                                                          30U
+#define AON_REG_SYSTEM_REG6X_BUCK_BOOST_VDDPA_POS_EN_DR_FIX_Msk                                                          (0x1UL << AON_REG_SYSTEM_REG6X_BUCK_BOOST_VDDPA_POS_EN_DR_FIX_Pos)
+
+#define AON_REG_SYSTEM_REG6X_BUCK_BOOST_HV18_POS_EN_DR_FIX_Pos                                                           31U
+#define AON_REG_SYSTEM_REG6X_BUCK_BOOST_HV18_POS_EN_DR_FIX_Msk                                                           (0x1UL << AON_REG_SYSTEM_REG6X_BUCK_BOOST_HV18_POS_EN_DR_FIX_Pos)
+
+/* 0x1C     0x4000_001c
+    0       R/W     BUCK_BOOST_HV18_POS_RSTB                                    1'b0
+    1       R/W     BUCK_BOOST_HV18_POS_EN_POS                                  1'b0
+    5:2     R/W     BUCK_BOOST_HV18_POS_POF_STEP                                4'b0001
+    9:6     R/W     BUCK_BOOST_HV18_POS_PON_STEP                                4'b0001
+    12:10   R/W     BUCK_BOOST_HV18_POS_POF_WAIT                                3'b000
+    15:13   R/W     BUCK_BOOST_HV18_POS_PON_WAIT                                3'b000
+    23:16   R/W     BUCK_BOOST_HV18_POS_PON_OVER                                8'b00011111
+    31:24   R/W     BUCK_BOOST_HV18_POS_PON_START                               8'b00000000
+ */
+typedef union _AON_REG_SYSTEM_REG7X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t BUCK_BOOST_HV18_POS_RSTB: 1;
+        uint32_t BUCK_BOOST_HV18_POS_EN_POS: 1;
+        uint32_t BUCK_BOOST_HV18_POS_POF_STEP: 4;
+        uint32_t BUCK_BOOST_HV18_POS_PON_STEP: 4;
+        uint32_t BUCK_BOOST_HV18_POS_POF_WAIT: 3;
+        uint32_t BUCK_BOOST_HV18_POS_PON_WAIT: 3;
+        uint32_t BUCK_BOOST_HV18_POS_PON_OVER: 8;
+        uint32_t BUCK_BOOST_HV18_POS_PON_START: 8;
+    };
+} AON_REG_SYSTEM_REG7X_TYPE;
+
+/*0x4000_001c AON_REG_SYSTEM_REG7X*/
+#define AON_REG_SYSTEM_REG7X_BUCK_BOOST_HV18_POS_RSTB_Pos                                                                0U
+#define AON_REG_SYSTEM_REG7X_BUCK_BOOST_HV18_POS_RSTB_Msk                                                                (0x1UL << AON_REG_SYSTEM_REG7X_BUCK_BOOST_HV18_POS_RSTB_Pos)
+
+#define AON_REG_SYSTEM_REG7X_BUCK_BOOST_HV18_POS_EN_POS_Pos                                                              1U
+#define AON_REG_SYSTEM_REG7X_BUCK_BOOST_HV18_POS_EN_POS_Msk                                                              (0x1UL << AON_REG_SYSTEM_REG7X_BUCK_BOOST_HV18_POS_EN_POS_Pos)
+
+#define AON_REG_SYSTEM_REG7X_BUCK_BOOST_HV18_POS_POF_STEP_Pos                                                            2U
+#define AON_REG_SYSTEM_REG7X_BUCK_BOOST_HV18_POS_POF_STEP_Msk                                                            (0xFUL << AON_REG_SYSTEM_REG7X_BUCK_BOOST_HV18_POS_POF_STEP_Pos)
+
+#define AON_REG_SYSTEM_REG7X_BUCK_BOOST_HV18_POS_PON_STEP_Pos                                                            6U
+#define AON_REG_SYSTEM_REG7X_BUCK_BOOST_HV18_POS_PON_STEP_Msk                                                            (0xFUL << AON_REG_SYSTEM_REG7X_BUCK_BOOST_HV18_POS_PON_STEP_Pos)
+
+#define AON_REG_SYSTEM_REG7X_BUCK_BOOST_HV18_POS_POF_WAIT_Pos                                                            10U
+#define AON_REG_SYSTEM_REG7X_BUCK_BOOST_HV18_POS_POF_WAIT_Msk                                                            (0x7UL << AON_REG_SYSTEM_REG7X_BUCK_BOOST_HV18_POS_POF_WAIT_Pos)
+
+#define AON_REG_SYSTEM_REG7X_BUCK_BOOST_HV18_POS_PON_WAIT_Pos                                                            13U
+#define AON_REG_SYSTEM_REG7X_BUCK_BOOST_HV18_POS_PON_WAIT_Msk                                                            (0x7UL << AON_REG_SYSTEM_REG7X_BUCK_BOOST_HV18_POS_PON_WAIT_Pos)
+
+#define AON_REG_SYSTEM_REG7X_BUCK_BOOST_HV18_POS_PON_OVER_Pos                                                            16U
+#define AON_REG_SYSTEM_REG7X_BUCK_BOOST_HV18_POS_PON_OVER_Msk                                                            (0xFFUL << AON_REG_SYSTEM_REG7X_BUCK_BOOST_HV18_POS_PON_OVER_Pos)
+
+#define AON_REG_SYSTEM_REG7X_BUCK_BOOST_HV18_POS_PON_START_Pos                                                           24U
+#define AON_REG_SYSTEM_REG7X_BUCK_BOOST_HV18_POS_PON_START_Msk                                                           (0xFFUL << AON_REG_SYSTEM_REG7X_BUCK_BOOST_HV18_POS_PON_START_Pos)
+
+/* 0x20     0x4000_0020
+    7:0     R/W     BUCK_BOOST_HV18_POS_POF_OVER                                8'b00000000
+    15:8    R/W     BUCK_BOOST_HV18_POS_POF_START                               8'b00011111
+    23:16   R/W     BUCK_BOOST_HV18_POS_SET_PON_FLAG1                           8'b00000000
+    31:24   R/W     BUCK_BOOST_HV18_POS_SET_PON_FLAG2                           8'b00011000
+ */
+typedef union _AON_REG_SYSTEM_REG8X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t BUCK_BOOST_HV18_POS_POF_OVER: 8;
+        uint32_t BUCK_BOOST_HV18_POS_POF_START: 8;
+        uint32_t BUCK_BOOST_HV18_POS_SET_PON_FLAG1: 8;
+        uint32_t BUCK_BOOST_HV18_POS_SET_PON_FLAG2: 8;
+    };
+} AON_REG_SYSTEM_REG8X_TYPE;
+
+/*0x4000_0020 AON_REG_SYSTEM_REG8X*/
+#define AON_REG_SYSTEM_REG8X_BUCK_BOOST_HV18_POS_POF_OVER_Pos                                                            0U
+#define AON_REG_SYSTEM_REG8X_BUCK_BOOST_HV18_POS_POF_OVER_Msk                                                            (0xFFUL << AON_REG_SYSTEM_REG8X_BUCK_BOOST_HV18_POS_POF_OVER_Pos)
+
+#define AON_REG_SYSTEM_REG8X_BUCK_BOOST_HV18_POS_POF_START_Pos                                                           8U
+#define AON_REG_SYSTEM_REG8X_BUCK_BOOST_HV18_POS_POF_START_Msk                                                           (0xFFUL << AON_REG_SYSTEM_REG8X_BUCK_BOOST_HV18_POS_POF_START_Pos)
+
+#define AON_REG_SYSTEM_REG8X_BUCK_BOOST_HV18_POS_SET_PON_FLAG1_Pos                                                       16U
+#define AON_REG_SYSTEM_REG8X_BUCK_BOOST_HV18_POS_SET_PON_FLAG1_Msk                                                       (0xFFUL << AON_REG_SYSTEM_REG8X_BUCK_BOOST_HV18_POS_SET_PON_FLAG1_Pos)
+
+#define AON_REG_SYSTEM_REG8X_BUCK_BOOST_HV18_POS_SET_PON_FLAG2_Pos                                                       24U
+#define AON_REG_SYSTEM_REG8X_BUCK_BOOST_HV18_POS_SET_PON_FLAG2_Msk                                                       (0xFFUL << AON_REG_SYSTEM_REG8X_BUCK_BOOST_HV18_POS_SET_PON_FLAG2_Pos)
+
+/* 0x24     0x4000_0024
+    7:0     R/W     BUCK_BOOST_HV18_POS_SET_PON_FLAG3                           8'b00011100
+    15:8    R/W     BUCK_BOOST_HV18_POS_SET_PON_FLAG4                           8'b00011111
+    23:16   R/W     BUCK_BOOST_HV18_POS_SET_POF_FLAG1                           8'b00000000
+    31:24   R/W     BUCK_BOOST_HV18_POS_SET_POF_FLAG2                           8'b00011000
+ */
+typedef union _AON_REG_SYSTEM_REG9X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t BUCK_BOOST_HV18_POS_SET_PON_FLAG3: 8;
+        uint32_t BUCK_BOOST_HV18_POS_SET_PON_FLAG4: 8;
+        uint32_t BUCK_BOOST_HV18_POS_SET_POF_FLAG1: 8;
+        uint32_t BUCK_BOOST_HV18_POS_SET_POF_FLAG2: 8;
+    };
+} AON_REG_SYSTEM_REG9X_TYPE;
+
+/*0x4000_0024 AON_REG_SYSTEM_REG9X*/
+#define AON_REG_SYSTEM_REG9X_BUCK_BOOST_HV18_POS_SET_PON_FLAG3_Pos                                                       0U
+#define AON_REG_SYSTEM_REG9X_BUCK_BOOST_HV18_POS_SET_PON_FLAG3_Msk                                                       (0xFFUL << AON_REG_SYSTEM_REG9X_BUCK_BOOST_HV18_POS_SET_PON_FLAG3_Pos)
+
+#define AON_REG_SYSTEM_REG9X_BUCK_BOOST_HV18_POS_SET_PON_FLAG4_Pos                                                       8U
+#define AON_REG_SYSTEM_REG9X_BUCK_BOOST_HV18_POS_SET_PON_FLAG4_Msk                                                       (0xFFUL << AON_REG_SYSTEM_REG9X_BUCK_BOOST_HV18_POS_SET_PON_FLAG4_Pos)
+
+#define AON_REG_SYSTEM_REG9X_BUCK_BOOST_HV18_POS_SET_POF_FLAG1_Pos                                                       16U
+#define AON_REG_SYSTEM_REG9X_BUCK_BOOST_HV18_POS_SET_POF_FLAG1_Msk                                                       (0xFFUL << AON_REG_SYSTEM_REG9X_BUCK_BOOST_HV18_POS_SET_POF_FLAG1_Pos)
+
+#define AON_REG_SYSTEM_REG9X_BUCK_BOOST_HV18_POS_SET_POF_FLAG2_Pos                                                       24U
+#define AON_REG_SYSTEM_REG9X_BUCK_BOOST_HV18_POS_SET_POF_FLAG2_Msk                                                       (0xFFUL << AON_REG_SYSTEM_REG9X_BUCK_BOOST_HV18_POS_SET_POF_FLAG2_Pos)
+
+/* 0x28     0x4000_0028
+    7:0     R/W     BUCK_BOOST_HV18_POS_SET_POF_FLAG3                           8'b00011100
+    15:8    R/W     BUCK_BOOST_HV18_POS_SET_POF_FLAG4                           8'b00011111
+    18:16   R       BUCK_BOOST_HV18_POS_FSM_CS                                  3'b000
+    19      R       BUCK_BOOST_HV18_POS_POF_FLAG4                               1'b0
+    20      R       BUCK_BOOST_HV18_POS_POF_FLAG3                               1'b0
+    21      R       BUCK_BOOST_HV18_POS_POF_FLAG2                               1'b0
+    22      R       BUCK_BOOST_HV18_POS_POF_FLAG1                               1'b0
+    23      R       BUCK_BOOST_HV18_POS_PON_FLAG4                               1'b0
+    24      R       BUCK_BOOST_HV18_POS_PON_FLAG3                               1'b0
+    25      R       BUCK_BOOST_HV18_POS_PON_FLAG2                               1'b0
+    26      R       BUCK_BOOST_HV18_POS_PON_FLAG1                               1'b0
+    29:27   R/W     BUCK_BOOST_HV18_POS_DIV_CLK                                 3'b111
+    30      R/W     BUCK_BOOST_HV18_POS_CLK_GATED                               1'b1
+    31      R       RESERVED                                                    1'b0
+ */
+typedef union _AON_REG_SYSTEM_REG10X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t BUCK_BOOST_HV18_POS_SET_POF_FLAG3: 8;
+        uint32_t BUCK_BOOST_HV18_POS_SET_POF_FLAG4: 8;
+        uint32_t BUCK_BOOST_HV18_POS_FSM_CS: 3;
+        uint32_t BUCK_BOOST_HV18_POS_POF_FLAG4: 1;
+        uint32_t BUCK_BOOST_HV18_POS_POF_FLAG3: 1;
+        uint32_t BUCK_BOOST_HV18_POS_POF_FLAG2: 1;
+        uint32_t BUCK_BOOST_HV18_POS_POF_FLAG1: 1;
+        uint32_t BUCK_BOOST_HV18_POS_PON_FLAG4: 1;
+        uint32_t BUCK_BOOST_HV18_POS_PON_FLAG3: 1;
+        uint32_t BUCK_BOOST_HV18_POS_PON_FLAG2: 1;
+        uint32_t BUCK_BOOST_HV18_POS_PON_FLAG1: 1;
+        uint32_t BUCK_BOOST_HV18_POS_DIV_CLK: 3;
+        uint32_t BUCK_BOOST_HV18_POS_CLK_GATED: 1;
+        uint32_t RESERVED: 1;
+    };
+} AON_REG_SYSTEM_REG10X_TYPE;
+
+/*0x4000_0028 AON_REG_SYSTEM_REG10X*/
+#define AON_REG_SYSTEM_REG10X_BUCK_BOOST_HV18_POS_SET_POF_FLAG3_Pos                                                      0U
+#define AON_REG_SYSTEM_REG10X_BUCK_BOOST_HV18_POS_SET_POF_FLAG3_Msk                                                      (0xFFUL << AON_REG_SYSTEM_REG10X_BUCK_BOOST_HV18_POS_SET_POF_FLAG3_Pos)
+
+#define AON_REG_SYSTEM_REG10X_BUCK_BOOST_HV18_POS_SET_POF_FLAG4_Pos                                                      8U
+#define AON_REG_SYSTEM_REG10X_BUCK_BOOST_HV18_POS_SET_POF_FLAG4_Msk                                                      (0xFFUL << AON_REG_SYSTEM_REG10X_BUCK_BOOST_HV18_POS_SET_POF_FLAG4_Pos)
+
+#define AON_REG_SYSTEM_REG10X_BUCK_BOOST_HV18_POS_FSM_CS_Pos                                                             16U
+#define AON_REG_SYSTEM_REG10X_BUCK_BOOST_HV18_POS_FSM_CS_Msk                                                             (0x7UL << AON_REG_SYSTEM_REG10X_BUCK_BOOST_HV18_POS_FSM_CS_Pos)
+
+#define AON_REG_SYSTEM_REG10X_BUCK_BOOST_HV18_POS_POF_FLAG4_Pos                                                          19U
+#define AON_REG_SYSTEM_REG10X_BUCK_BOOST_HV18_POS_POF_FLAG4_Msk                                                          (0x1UL << AON_REG_SYSTEM_REG10X_BUCK_BOOST_HV18_POS_POF_FLAG4_Pos)
+
+#define AON_REG_SYSTEM_REG10X_BUCK_BOOST_HV18_POS_POF_FLAG3_Pos                                                          20U
+#define AON_REG_SYSTEM_REG10X_BUCK_BOOST_HV18_POS_POF_FLAG3_Msk                                                          (0x1UL << AON_REG_SYSTEM_REG10X_BUCK_BOOST_HV18_POS_POF_FLAG3_Pos)
+
+#define AON_REG_SYSTEM_REG10X_BUCK_BOOST_HV18_POS_POF_FLAG2_Pos                                                          21U
+#define AON_REG_SYSTEM_REG10X_BUCK_BOOST_HV18_POS_POF_FLAG2_Msk                                                          (0x1UL << AON_REG_SYSTEM_REG10X_BUCK_BOOST_HV18_POS_POF_FLAG2_Pos)
+
+#define AON_REG_SYSTEM_REG10X_BUCK_BOOST_HV18_POS_POF_FLAG1_Pos                                                          22U
+#define AON_REG_SYSTEM_REG10X_BUCK_BOOST_HV18_POS_POF_FLAG1_Msk                                                          (0x1UL << AON_REG_SYSTEM_REG10X_BUCK_BOOST_HV18_POS_POF_FLAG1_Pos)
+
+#define AON_REG_SYSTEM_REG10X_BUCK_BOOST_HV18_POS_PON_FLAG4_Pos                                                          23U
+#define AON_REG_SYSTEM_REG10X_BUCK_BOOST_HV18_POS_PON_FLAG4_Msk                                                          (0x1UL << AON_REG_SYSTEM_REG10X_BUCK_BOOST_HV18_POS_PON_FLAG4_Pos)
+
+#define AON_REG_SYSTEM_REG10X_BUCK_BOOST_HV18_POS_PON_FLAG3_Pos                                                          24U
+#define AON_REG_SYSTEM_REG10X_BUCK_BOOST_HV18_POS_PON_FLAG3_Msk                                                          (0x1UL << AON_REG_SYSTEM_REG10X_BUCK_BOOST_HV18_POS_PON_FLAG3_Pos)
+
+#define AON_REG_SYSTEM_REG10X_BUCK_BOOST_HV18_POS_PON_FLAG2_Pos                                                          25U
+#define AON_REG_SYSTEM_REG10X_BUCK_BOOST_HV18_POS_PON_FLAG2_Msk                                                          (0x1UL << AON_REG_SYSTEM_REG10X_BUCK_BOOST_HV18_POS_PON_FLAG2_Pos)
+
+#define AON_REG_SYSTEM_REG10X_BUCK_BOOST_HV18_POS_PON_FLAG1_Pos                                                          26U
+#define AON_REG_SYSTEM_REG10X_BUCK_BOOST_HV18_POS_PON_FLAG1_Msk                                                          (0x1UL << AON_REG_SYSTEM_REG10X_BUCK_BOOST_HV18_POS_PON_FLAG1_Pos)
+
+#define AON_REG_SYSTEM_REG10X_BUCK_BOOST_HV18_POS_DIV_CLK_Pos                                                            27U
+#define AON_REG_SYSTEM_REG10X_BUCK_BOOST_HV18_POS_DIV_CLK_Msk                                                            (0x7UL << AON_REG_SYSTEM_REG10X_BUCK_BOOST_HV18_POS_DIV_CLK_Pos)
+
+#define AON_REG_SYSTEM_REG10X_BUCK_BOOST_HV18_POS_CLK_GATED_Pos                                                          30U
+#define AON_REG_SYSTEM_REG10X_BUCK_BOOST_HV18_POS_CLK_GATED_Msk                                                          (0x1UL << AON_REG_SYSTEM_REG10X_BUCK_BOOST_HV18_POS_CLK_GATED_Pos)
+
+#define AON_REG_SYSTEM_REG10X_RESERVED_Pos                                                                               31U
+#define AON_REG_SYSTEM_REG10X_RESERVED_Msk                                                                               (0x1UL << AON_REG_SYSTEM_REG10X_RESERVED_Pos)
+
+/* 0x2C     0x4000_002c
+    0       R/W     BUCK_BOOST_VDDPA_POS_RSTB                                   1'b0
+    1       R/W     BUCK_BOOST_VDDPA_POS_EN_POS                                 1'b0
+    5:2     R/W     BUCK_BOOST_VDDPA_POS_POF_STEP                               4'b0001
+    9:6     R/W     BUCK_BOOST_VDDPA_POS_PON_STEP                               4'b0001
+    12:10   R/W     BUCK_BOOST_VDDPA_POS_POF_WAIT                               3'b000
+    15:13   R/W     BUCK_BOOST_VDDPA_POS_PON_WAIT                               3'b000
+    23:16   R/W     BUCK_BOOST_VDDPA_POS_PON_OVER                               8'b00011111
+    31:24   R/W     BUCK_BOOST_VDDPA_POS_PON_START                              8'b00000000
+ */
+typedef union _AON_REG_SYSTEM_REG11X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t BUCK_BOOST_VDDPA_POS_RSTB: 1;
+        uint32_t BUCK_BOOST_VDDPA_POS_EN_POS: 1;
+        uint32_t BUCK_BOOST_VDDPA_POS_POF_STEP: 4;
+        uint32_t BUCK_BOOST_VDDPA_POS_PON_STEP: 4;
+        uint32_t BUCK_BOOST_VDDPA_POS_POF_WAIT: 3;
+        uint32_t BUCK_BOOST_VDDPA_POS_PON_WAIT: 3;
+        uint32_t BUCK_BOOST_VDDPA_POS_PON_OVER: 8;
+        uint32_t BUCK_BOOST_VDDPA_POS_PON_START: 8;
+    };
+} AON_REG_SYSTEM_REG11X_TYPE;
+
+/*0x4000_002c AON_REG_SYSTEM_REG11X*/
+#define AON_REG_SYSTEM_REG11X_BUCK_BOOST_VDDPA_POS_RSTB_Pos                                                              0U
+#define AON_REG_SYSTEM_REG11X_BUCK_BOOST_VDDPA_POS_RSTB_Msk                                                              (0x1UL << AON_REG_SYSTEM_REG11X_BUCK_BOOST_VDDPA_POS_RSTB_Pos)
+
+#define AON_REG_SYSTEM_REG11X_BUCK_BOOST_VDDPA_POS_EN_POS_Pos                                                            1U
+#define AON_REG_SYSTEM_REG11X_BUCK_BOOST_VDDPA_POS_EN_POS_Msk                                                            (0x1UL << AON_REG_SYSTEM_REG11X_BUCK_BOOST_VDDPA_POS_EN_POS_Pos)
+
+#define AON_REG_SYSTEM_REG11X_BUCK_BOOST_VDDPA_POS_POF_STEP_Pos                                                          2U
+#define AON_REG_SYSTEM_REG11X_BUCK_BOOST_VDDPA_POS_POF_STEP_Msk                                                          (0xFUL << AON_REG_SYSTEM_REG11X_BUCK_BOOST_VDDPA_POS_POF_STEP_Pos)
+
+#define AON_REG_SYSTEM_REG11X_BUCK_BOOST_VDDPA_POS_PON_STEP_Pos                                                          6U
+#define AON_REG_SYSTEM_REG11X_BUCK_BOOST_VDDPA_POS_PON_STEP_Msk                                                          (0xFUL << AON_REG_SYSTEM_REG11X_BUCK_BOOST_VDDPA_POS_PON_STEP_Pos)
+
+#define AON_REG_SYSTEM_REG11X_BUCK_BOOST_VDDPA_POS_POF_WAIT_Pos                                                          10U
+#define AON_REG_SYSTEM_REG11X_BUCK_BOOST_VDDPA_POS_POF_WAIT_Msk                                                          (0x7UL << AON_REG_SYSTEM_REG11X_BUCK_BOOST_VDDPA_POS_POF_WAIT_Pos)
+
+#define AON_REG_SYSTEM_REG11X_BUCK_BOOST_VDDPA_POS_PON_WAIT_Pos                                                          13U
+#define AON_REG_SYSTEM_REG11X_BUCK_BOOST_VDDPA_POS_PON_WAIT_Msk                                                          (0x7UL << AON_REG_SYSTEM_REG11X_BUCK_BOOST_VDDPA_POS_PON_WAIT_Pos)
+
+#define AON_REG_SYSTEM_REG11X_BUCK_BOOST_VDDPA_POS_PON_OVER_Pos                                                          16U
+#define AON_REG_SYSTEM_REG11X_BUCK_BOOST_VDDPA_POS_PON_OVER_Msk                                                          (0xFFUL << AON_REG_SYSTEM_REG11X_BUCK_BOOST_VDDPA_POS_PON_OVER_Pos)
+
+#define AON_REG_SYSTEM_REG11X_BUCK_BOOST_VDDPA_POS_PON_START_Pos                                                         24U
+#define AON_REG_SYSTEM_REG11X_BUCK_BOOST_VDDPA_POS_PON_START_Msk                                                         (0xFFUL << AON_REG_SYSTEM_REG11X_BUCK_BOOST_VDDPA_POS_PON_START_Pos)
+
+/* 0x30     0x4000_0030
+    7:0     R/W     BUCK_BOOST_VDDPA_POS_POF_OVER                               8'b00000000
+    15:8    R/W     BUCK_BOOST_VDDPA_POS_POF_START                              8'b00011111
+    23:16   R/W     BUCK_BOOST_VDDPA_POS_SET_PON_FLAG1                          8'b00000000
+    31:24   R/W     BUCK_BOOST_VDDPA_POS_SET_PON_FLAG2                          8'b00011000
+ */
+typedef union _AON_REG_SYSTEM_REG12X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t BUCK_BOOST_VDDPA_POS_POF_OVER: 8;
+        uint32_t BUCK_BOOST_VDDPA_POS_POF_START: 8;
+        uint32_t BUCK_BOOST_VDDPA_POS_SET_PON_FLAG1: 8;
+        uint32_t BUCK_BOOST_VDDPA_POS_SET_PON_FLAG2: 8;
+    };
+} AON_REG_SYSTEM_REG12X_TYPE;
+
+/*0x4000_0030 AON_REG_SYSTEM_REG12X*/
+#define AON_REG_SYSTEM_REG12X_BUCK_BOOST_VDDPA_POS_POF_OVER_Pos                                                          0U
+#define AON_REG_SYSTEM_REG12X_BUCK_BOOST_VDDPA_POS_POF_OVER_Msk                                                          (0xFFUL << AON_REG_SYSTEM_REG12X_BUCK_BOOST_VDDPA_POS_POF_OVER_Pos)
+
+#define AON_REG_SYSTEM_REG12X_BUCK_BOOST_VDDPA_POS_POF_START_Pos                                                         8U
+#define AON_REG_SYSTEM_REG12X_BUCK_BOOST_VDDPA_POS_POF_START_Msk                                                         (0xFFUL << AON_REG_SYSTEM_REG12X_BUCK_BOOST_VDDPA_POS_POF_START_Pos)
+
+#define AON_REG_SYSTEM_REG12X_BUCK_BOOST_VDDPA_POS_SET_PON_FLAG1_Pos                                                     16U
+#define AON_REG_SYSTEM_REG12X_BUCK_BOOST_VDDPA_POS_SET_PON_FLAG1_Msk                                                     (0xFFUL << AON_REG_SYSTEM_REG12X_BUCK_BOOST_VDDPA_POS_SET_PON_FLAG1_Pos)
+
+#define AON_REG_SYSTEM_REG12X_BUCK_BOOST_VDDPA_POS_SET_PON_FLAG2_Pos                                                     24U
+#define AON_REG_SYSTEM_REG12X_BUCK_BOOST_VDDPA_POS_SET_PON_FLAG2_Msk                                                     (0xFFUL << AON_REG_SYSTEM_REG12X_BUCK_BOOST_VDDPA_POS_SET_PON_FLAG2_Pos)
+
+/* 0x34     0x4000_0034
+    7:0     R/W     BUCK_BOOST_VDDPA_POS_SET_PON_FLAG3                          8'b00011100
+    15:8    R/W     BUCK_BOOST_VDDPA_POS_SET_PON_FLAG4                          8'b00011111
+    23:16   R/W     BUCK_BOOST_VDDPA_POS_SET_POF_FLAG1                          8'b00000000
+    31:24   R/W     BUCK_BOOST_VDDPA_POS_SET_POF_FLAG2                          8'b00011000
+ */
+typedef union _AON_REG_SYSTEM_REG13X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t BUCK_BOOST_VDDPA_POS_SET_PON_FLAG3: 8;
+        uint32_t BUCK_BOOST_VDDPA_POS_SET_PON_FLAG4: 8;
+        uint32_t BUCK_BOOST_VDDPA_POS_SET_POF_FLAG1: 8;
+        uint32_t BUCK_BOOST_VDDPA_POS_SET_POF_FLAG2: 8;
+    };
+} AON_REG_SYSTEM_REG13X_TYPE;
+
+/*0x4000_0034 AON_REG_SYSTEM_REG13X*/
+#define AON_REG_SYSTEM_REG13X_BUCK_BOOST_VDDPA_POS_SET_PON_FLAG3_Pos                                                     0U
+#define AON_REG_SYSTEM_REG13X_BUCK_BOOST_VDDPA_POS_SET_PON_FLAG3_Msk                                                     (0xFFUL << AON_REG_SYSTEM_REG13X_BUCK_BOOST_VDDPA_POS_SET_PON_FLAG3_Pos)
+
+#define AON_REG_SYSTEM_REG13X_BUCK_BOOST_VDDPA_POS_SET_PON_FLAG4_Pos                                                     8U
+#define AON_REG_SYSTEM_REG13X_BUCK_BOOST_VDDPA_POS_SET_PON_FLAG4_Msk                                                     (0xFFUL << AON_REG_SYSTEM_REG13X_BUCK_BOOST_VDDPA_POS_SET_PON_FLAG4_Pos)
+
+#define AON_REG_SYSTEM_REG13X_BUCK_BOOST_VDDPA_POS_SET_POF_FLAG1_Pos                                                     16U
+#define AON_REG_SYSTEM_REG13X_BUCK_BOOST_VDDPA_POS_SET_POF_FLAG1_Msk                                                     (0xFFUL << AON_REG_SYSTEM_REG13X_BUCK_BOOST_VDDPA_POS_SET_POF_FLAG1_Pos)
+
+#define AON_REG_SYSTEM_REG13X_BUCK_BOOST_VDDPA_POS_SET_POF_FLAG2_Pos                                                     24U
+#define AON_REG_SYSTEM_REG13X_BUCK_BOOST_VDDPA_POS_SET_POF_FLAG2_Msk                                                     (0xFFUL << AON_REG_SYSTEM_REG13X_BUCK_BOOST_VDDPA_POS_SET_POF_FLAG2_Pos)
+
+/* 0x38     0x4000_0038
+    7:0     R/W     BUCK_BOOST_VDDPA_POS_SET_POF_FLAG3                          8'b00011100
+    15:8    R/W     BUCK_BOOST_VDDPA_POS_SET_POF_FLAG4                          8'b00011111
+    18:16   R       BUCK_BOOST_VDDPA_POS_FSM_CS                                 3'b000
+    19      R       BUCK_BOOST_VDDPA_POS_POF_FLAG4                              1'b0
+    20      R       BUCK_BOOST_VDDPA_POS_POF_FLAG3                              1'b0
+    21      R       BUCK_BOOST_VDDPA_POS_POF_FLAG2                              1'b0
+    22      R       BUCK_BOOST_VDDPA_POS_POF_FLAG1                              1'b0
+    23      R       BUCK_BOOST_VDDPA_POS_PON_FLAG4                              1'b0
+    24      R       BUCK_BOOST_VDDPA_POS_PON_FLAG3                              1'b0
+    25      R       BUCK_BOOST_VDDPA_POS_PON_FLAG2                              1'b0
+    26      R       BUCK_BOOST_VDDPA_POS_PON_FLAG1                              1'b0
+    30:27   R/W     BUCK_BOOST_VDDPA_POS_DIV_CLK                                4'b0111
+    31      R/W     BUCK_BOOST_VDDPA_POS_CLK_GATED                              1'b1
+ */
+typedef union _AON_REG_SYSTEM_REG14X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t BUCK_BOOST_VDDPA_POS_SET_POF_FLAG3: 8;
+        uint32_t BUCK_BOOST_VDDPA_POS_SET_POF_FLAG4: 8;
+        uint32_t BUCK_BOOST_VDDPA_POS_FSM_CS: 3;
+        uint32_t BUCK_BOOST_VDDPA_POS_POF_FLAG4: 1;
+        uint32_t BUCK_BOOST_VDDPA_POS_POF_FLAG3: 1;
+        uint32_t BUCK_BOOST_VDDPA_POS_POF_FLAG2: 1;
+        uint32_t BUCK_BOOST_VDDPA_POS_POF_FLAG1: 1;
+        uint32_t BUCK_BOOST_VDDPA_POS_PON_FLAG4: 1;
+        uint32_t BUCK_BOOST_VDDPA_POS_PON_FLAG3: 1;
+        uint32_t BUCK_BOOST_VDDPA_POS_PON_FLAG2: 1;
+        uint32_t BUCK_BOOST_VDDPA_POS_PON_FLAG1: 1;
+        uint32_t BUCK_BOOST_VDDPA_POS_DIV_CLK: 4;
+        uint32_t BUCK_BOOST_VDDPA_POS_CLK_GATED: 1;
+    };
+} AON_REG_SYSTEM_REG14X_TYPE;
+
+/*0x4000_0038 AON_REG_SYSTEM_REG14X*/
+#define AON_REG_SYSTEM_REG14X_BUCK_BOOST_VDDPA_POS_SET_POF_FLAG3_Pos                                                     0U
+#define AON_REG_SYSTEM_REG14X_BUCK_BOOST_VDDPA_POS_SET_POF_FLAG3_Msk                                                     (0xFFUL << AON_REG_SYSTEM_REG14X_BUCK_BOOST_VDDPA_POS_SET_POF_FLAG3_Pos)
+
+#define AON_REG_SYSTEM_REG14X_BUCK_BOOST_VDDPA_POS_SET_POF_FLAG4_Pos                                                     8U
+#define AON_REG_SYSTEM_REG14X_BUCK_BOOST_VDDPA_POS_SET_POF_FLAG4_Msk                                                     (0xFFUL << AON_REG_SYSTEM_REG14X_BUCK_BOOST_VDDPA_POS_SET_POF_FLAG4_Pos)
+
+#define AON_REG_SYSTEM_REG14X_BUCK_BOOST_VDDPA_POS_FSM_CS_Pos                                                            16U
+#define AON_REG_SYSTEM_REG14X_BUCK_BOOST_VDDPA_POS_FSM_CS_Msk                                                            (0x7UL << AON_REG_SYSTEM_REG14X_BUCK_BOOST_VDDPA_POS_FSM_CS_Pos)
+
+#define AON_REG_SYSTEM_REG14X_BUCK_BOOST_VDDPA_POS_POF_FLAG4_Pos                                                         19U
+#define AON_REG_SYSTEM_REG14X_BUCK_BOOST_VDDPA_POS_POF_FLAG4_Msk                                                         (0x1UL << AON_REG_SYSTEM_REG14X_BUCK_BOOST_VDDPA_POS_POF_FLAG4_Pos)
+
+#define AON_REG_SYSTEM_REG14X_BUCK_BOOST_VDDPA_POS_POF_FLAG3_Pos                                                         20U
+#define AON_REG_SYSTEM_REG14X_BUCK_BOOST_VDDPA_POS_POF_FLAG3_Msk                                                         (0x1UL << AON_REG_SYSTEM_REG14X_BUCK_BOOST_VDDPA_POS_POF_FLAG3_Pos)
+
+#define AON_REG_SYSTEM_REG14X_BUCK_BOOST_VDDPA_POS_POF_FLAG2_Pos                                                         21U
+#define AON_REG_SYSTEM_REG14X_BUCK_BOOST_VDDPA_POS_POF_FLAG2_Msk                                                         (0x1UL << AON_REG_SYSTEM_REG14X_BUCK_BOOST_VDDPA_POS_POF_FLAG2_Pos)
+
+#define AON_REG_SYSTEM_REG14X_BUCK_BOOST_VDDPA_POS_POF_FLAG1_Pos                                                         22U
+#define AON_REG_SYSTEM_REG14X_BUCK_BOOST_VDDPA_POS_POF_FLAG1_Msk                                                         (0x1UL << AON_REG_SYSTEM_REG14X_BUCK_BOOST_VDDPA_POS_POF_FLAG1_Pos)
+
+#define AON_REG_SYSTEM_REG14X_BUCK_BOOST_VDDPA_POS_PON_FLAG4_Pos                                                         23U
+#define AON_REG_SYSTEM_REG14X_BUCK_BOOST_VDDPA_POS_PON_FLAG4_Msk                                                         (0x1UL << AON_REG_SYSTEM_REG14X_BUCK_BOOST_VDDPA_POS_PON_FLAG4_Pos)
+
+#define AON_REG_SYSTEM_REG14X_BUCK_BOOST_VDDPA_POS_PON_FLAG3_Pos                                                         24U
+#define AON_REG_SYSTEM_REG14X_BUCK_BOOST_VDDPA_POS_PON_FLAG3_Msk                                                         (0x1UL << AON_REG_SYSTEM_REG14X_BUCK_BOOST_VDDPA_POS_PON_FLAG3_Pos)
+
+#define AON_REG_SYSTEM_REG14X_BUCK_BOOST_VDDPA_POS_PON_FLAG2_Pos                                                         25U
+#define AON_REG_SYSTEM_REG14X_BUCK_BOOST_VDDPA_POS_PON_FLAG2_Msk                                                         (0x1UL << AON_REG_SYSTEM_REG14X_BUCK_BOOST_VDDPA_POS_PON_FLAG2_Pos)
+
+#define AON_REG_SYSTEM_REG14X_BUCK_BOOST_VDDPA_POS_PON_FLAG1_Pos                                                         26U
+#define AON_REG_SYSTEM_REG14X_BUCK_BOOST_VDDPA_POS_PON_FLAG1_Msk                                                         (0x1UL << AON_REG_SYSTEM_REG14X_BUCK_BOOST_VDDPA_POS_PON_FLAG1_Pos)
+
+#define AON_REG_SYSTEM_REG14X_BUCK_BOOST_VDDPA_POS_DIV_CLK_Pos                                                           27U
+#define AON_REG_SYSTEM_REG14X_BUCK_BOOST_VDDPA_POS_DIV_CLK_Msk                                                           (0xFUL << AON_REG_SYSTEM_REG14X_BUCK_BOOST_VDDPA_POS_DIV_CLK_Pos)
+
+#define AON_REG_SYSTEM_REG14X_BUCK_BOOST_VDDPA_POS_CLK_GATED_Pos                                                         31U
+#define AON_REG_SYSTEM_REG14X_BUCK_BOOST_VDDPA_POS_CLK_GATED_Msk                                                         (0x1UL << AON_REG_SYSTEM_REG14X_BUCK_BOOST_VDDPA_POS_CLK_GATED_Pos)
+
+/* 0x3C     0x4000_003c
+    0       R/W     LDO_ANA_POS_RSTB                                            1'b0
+    1       R/W     LDO_ANA_POS_EN_POS                                          1'b0
+    5:2     R/W     LDO_ANA_POS_POF_STEP                                        4'b0001
+    9:6     R/W     LDO_ANA_POS_PON_STEP                                        4'b0001
+    12:10   R/W     LDO_ANA_POS_POF_WAIT                                        3'b000
+    15:13   R/W     LDO_ANA_POS_PON_WAIT                                        3'b000
+    23:16   R/W     LDO_ANA_POS_PON_OVER                                        8'b00111111
+    31:24   R/W     LDO_ANA_POS_PON_START                                       8'b00000000
+ */
+typedef union _AON_REG_SYSTEM_REG15X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t LDO_ANA_POS_RSTB: 1;
+        uint32_t LDO_ANA_POS_EN_POS: 1;
+        uint32_t LDO_ANA_POS_POF_STEP: 4;
+        uint32_t LDO_ANA_POS_PON_STEP: 4;
+        uint32_t LDO_ANA_POS_POF_WAIT: 3;
+        uint32_t LDO_ANA_POS_PON_WAIT: 3;
+        uint32_t LDO_ANA_POS_PON_OVER: 8;
+        uint32_t LDO_ANA_POS_PON_START: 8;
+    };
+} AON_REG_SYSTEM_REG15X_TYPE;
+
+/*0x4000_003c AON_REG_SYSTEM_REG15X*/
+#define AON_REG_SYSTEM_REG15X_LDO_ANA_POS_RSTB_Pos                                                                       0U
+#define AON_REG_SYSTEM_REG15X_LDO_ANA_POS_RSTB_Msk                                                                       (0x1UL << AON_REG_SYSTEM_REG15X_LDO_ANA_POS_RSTB_Pos)
+
+#define AON_REG_SYSTEM_REG15X_LDO_ANA_POS_EN_POS_Pos                                                                     1U
+#define AON_REG_SYSTEM_REG15X_LDO_ANA_POS_EN_POS_Msk                                                                     (0x1UL << AON_REG_SYSTEM_REG15X_LDO_ANA_POS_EN_POS_Pos)
+
+#define AON_REG_SYSTEM_REG15X_LDO_ANA_POS_POF_STEP_Pos                                                                   2U
+#define AON_REG_SYSTEM_REG15X_LDO_ANA_POS_POF_STEP_Msk                                                                   (0xFUL << AON_REG_SYSTEM_REG15X_LDO_ANA_POS_POF_STEP_Pos)
+
+#define AON_REG_SYSTEM_REG15X_LDO_ANA_POS_PON_STEP_Pos                                                                   6U
+#define AON_REG_SYSTEM_REG15X_LDO_ANA_POS_PON_STEP_Msk                                                                   (0xFUL << AON_REG_SYSTEM_REG15X_LDO_ANA_POS_PON_STEP_Pos)
+
+#define AON_REG_SYSTEM_REG15X_LDO_ANA_POS_POF_WAIT_Pos                                                                   10U
+#define AON_REG_SYSTEM_REG15X_LDO_ANA_POS_POF_WAIT_Msk                                                                   (0x7UL << AON_REG_SYSTEM_REG15X_LDO_ANA_POS_POF_WAIT_Pos)
+
+#define AON_REG_SYSTEM_REG15X_LDO_ANA_POS_PON_WAIT_Pos                                                                   13U
+#define AON_REG_SYSTEM_REG15X_LDO_ANA_POS_PON_WAIT_Msk                                                                   (0x7UL << AON_REG_SYSTEM_REG15X_LDO_ANA_POS_PON_WAIT_Pos)
+
+#define AON_REG_SYSTEM_REG15X_LDO_ANA_POS_PON_OVER_Pos                                                                   16U
+#define AON_REG_SYSTEM_REG15X_LDO_ANA_POS_PON_OVER_Msk                                                                   (0xFFUL << AON_REG_SYSTEM_REG15X_LDO_ANA_POS_PON_OVER_Pos)
+
+#define AON_REG_SYSTEM_REG15X_LDO_ANA_POS_PON_START_Pos                                                                  24U
+#define AON_REG_SYSTEM_REG15X_LDO_ANA_POS_PON_START_Msk                                                                  (0xFFUL << AON_REG_SYSTEM_REG15X_LDO_ANA_POS_PON_START_Pos)
+
+/* 0x40     0x4000_0040
+    7:0     R/W     LDO_ANA_POS_POF_OVER                                        8'b00000000
+    15:8    R/W     LDO_ANA_POS_POF_START                                       8'b00111111
+    23:16   R/W     LDO_ANA_POS_SET_PON_FLAG1                                   8'b00000000
+    31:24   R/W     LDO_ANA_POS_SET_PON_FLAG2                                   8'b00011000
+ */
+typedef union _AON_REG_SYSTEM_REG16X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t LDO_ANA_POS_POF_OVER: 8;
+        uint32_t LDO_ANA_POS_POF_START: 8;
+        uint32_t LDO_ANA_POS_SET_PON_FLAG1: 8;
+        uint32_t LDO_ANA_POS_SET_PON_FLAG2: 8;
+    };
+} AON_REG_SYSTEM_REG16X_TYPE;
+
+/*0x4000_0040 AON_REG_SYSTEM_REG16X*/
+#define AON_REG_SYSTEM_REG16X_LDO_ANA_POS_POF_OVER_Pos                                                                   0U
+#define AON_REG_SYSTEM_REG16X_LDO_ANA_POS_POF_OVER_Msk                                                                   (0xFFUL << AON_REG_SYSTEM_REG16X_LDO_ANA_POS_POF_OVER_Pos)
+
+#define AON_REG_SYSTEM_REG16X_LDO_ANA_POS_POF_START_Pos                                                                  8U
+#define AON_REG_SYSTEM_REG16X_LDO_ANA_POS_POF_START_Msk                                                                  (0xFFUL << AON_REG_SYSTEM_REG16X_LDO_ANA_POS_POF_START_Pos)
+
+#define AON_REG_SYSTEM_REG16X_LDO_ANA_POS_SET_PON_FLAG1_Pos                                                              16U
+#define AON_REG_SYSTEM_REG16X_LDO_ANA_POS_SET_PON_FLAG1_Msk                                                              (0xFFUL << AON_REG_SYSTEM_REG16X_LDO_ANA_POS_SET_PON_FLAG1_Pos)
+
+#define AON_REG_SYSTEM_REG16X_LDO_ANA_POS_SET_PON_FLAG2_Pos                                                              24U
+#define AON_REG_SYSTEM_REG16X_LDO_ANA_POS_SET_PON_FLAG2_Msk                                                              (0xFFUL << AON_REG_SYSTEM_REG16X_LDO_ANA_POS_SET_PON_FLAG2_Pos)
+
+/* 0x44     0x4000_0044
+    7:0     R/W     LDO_ANA_POS_SET_PON_FLAG3                                   8'b00011100
+    15:8    R/W     LDO_ANA_POS_SET_PON_FLAG4                                   8'b00011111
+    23:16   R/W     LDO_ANA_POS_SET_POF_FLAG1                                   8'b00000111
+    31:24   R/W     LDO_ANA_POS_SET_POF_FLAG2                                   8'b00000110
+ */
+typedef union _AON_REG_SYSTEM_REG17X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t LDO_ANA_POS_SET_PON_FLAG3: 8;
+        uint32_t LDO_ANA_POS_SET_PON_FLAG4: 8;
+        uint32_t LDO_ANA_POS_SET_POF_FLAG1: 8;
+        uint32_t LDO_ANA_POS_SET_POF_FLAG2: 8;
+    };
+} AON_REG_SYSTEM_REG17X_TYPE;
+
+/*0x4000_0044 AON_REG_SYSTEM_REG17X*/
+#define AON_REG_SYSTEM_REG17X_LDO_ANA_POS_SET_PON_FLAG3_Pos                                                              0U
+#define AON_REG_SYSTEM_REG17X_LDO_ANA_POS_SET_PON_FLAG3_Msk                                                              (0xFFUL << AON_REG_SYSTEM_REG17X_LDO_ANA_POS_SET_PON_FLAG3_Pos)
+
+#define AON_REG_SYSTEM_REG17X_LDO_ANA_POS_SET_PON_FLAG4_Pos                                                              8U
+#define AON_REG_SYSTEM_REG17X_LDO_ANA_POS_SET_PON_FLAG4_Msk                                                              (0xFFUL << AON_REG_SYSTEM_REG17X_LDO_ANA_POS_SET_PON_FLAG4_Pos)
+
+#define AON_REG_SYSTEM_REG17X_LDO_ANA_POS_SET_POF_FLAG1_Pos                                                              16U
+#define AON_REG_SYSTEM_REG17X_LDO_ANA_POS_SET_POF_FLAG1_Msk                                                              (0xFFUL << AON_REG_SYSTEM_REG17X_LDO_ANA_POS_SET_POF_FLAG1_Pos)
+
+#define AON_REG_SYSTEM_REG17X_LDO_ANA_POS_SET_POF_FLAG2_Pos                                                              24U
+#define AON_REG_SYSTEM_REG17X_LDO_ANA_POS_SET_POF_FLAG2_Msk                                                              (0xFFUL << AON_REG_SYSTEM_REG17X_LDO_ANA_POS_SET_POF_FLAG2_Pos)
+
+/* 0x48     0x4000_0048
+    7:0     R/W     LDO_ANA_POS_SET_POF_FLAG3                                   8'b00011100
+    15:8    R/W     LDO_ANA_POS_SET_POF_FLAG4                                   8'b00011111
+    18:16   R       LDO_ANA_POS_FSM_CS                                          3'b000
+    19      R       LDO_ANA_POS_POF_FLAG4                                       1'b0
+    20      R       LDO_ANA_POS_POF_FLAG3                                       1'b0
+    21      R       LDO_ANA_POS_POF_FLAG2                                       1'b0
+    22      R       LDO_ANA_POS_POF_FLAG1                                       1'b0
+    23      R       LDO_ANA_POS_PON_FLAG4                                       1'b0
+    24      R       LDO_ANA_POS_PON_FLAG3                                       1'b0
+    25      R       LDO_ANA_POS_PON_FLAG2                                       1'b0
+    26      R       LDO_ANA_POS_PON_FLAG1                                       1'b0
+    29:27   R/W     LDO_ANA_POS_DIV_CLK                                         3'b110
+    30      R/W     LDO_ANA_POS_CLK_GATED                                       1'b1
+    31      R       RESERVED                                                    1'b0
+ */
+typedef union _AON_REG_SYSTEM_REG18X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t LDO_ANA_POS_SET_POF_FLAG3: 8;
+        uint32_t LDO_ANA_POS_SET_POF_FLAG4: 8;
+        uint32_t LDO_ANA_POS_FSM_CS: 3;
+        uint32_t LDO_ANA_POS_POF_FLAG4: 1;
+        uint32_t LDO_ANA_POS_POF_FLAG3: 1;
+        uint32_t LDO_ANA_POS_POF_FLAG2: 1;
+        uint32_t LDO_ANA_POS_POF_FLAG1: 1;
+        uint32_t LDO_ANA_POS_PON_FLAG4: 1;
+        uint32_t LDO_ANA_POS_PON_FLAG3: 1;
+        uint32_t LDO_ANA_POS_PON_FLAG2: 1;
+        uint32_t LDO_ANA_POS_PON_FLAG1: 1;
+        uint32_t LDO_ANA_POS_DIV_CLK: 3;
+        uint32_t LDO_ANA_POS_CLK_GATED: 1;
+        uint32_t RESERVED: 1;
+    };
+} AON_REG_SYSTEM_REG18X_TYPE;
+
+/*0x4000_0048 AON_REG_SYSTEM_REG18X*/
+#define AON_REG_SYSTEM_REG18X_LDO_ANA_POS_SET_POF_FLAG3_Pos                                                              0U
+#define AON_REG_SYSTEM_REG18X_LDO_ANA_POS_SET_POF_FLAG3_Msk                                                              (0xFFUL << AON_REG_SYSTEM_REG18X_LDO_ANA_POS_SET_POF_FLAG3_Pos)
+
+#define AON_REG_SYSTEM_REG18X_LDO_ANA_POS_SET_POF_FLAG4_Pos                                                              8U
+#define AON_REG_SYSTEM_REG18X_LDO_ANA_POS_SET_POF_FLAG4_Msk                                                              (0xFFUL << AON_REG_SYSTEM_REG18X_LDO_ANA_POS_SET_POF_FLAG4_Pos)
+
+#define AON_REG_SYSTEM_REG18X_LDO_ANA_POS_FSM_CS_Pos                                                                     16U
+#define AON_REG_SYSTEM_REG18X_LDO_ANA_POS_FSM_CS_Msk                                                                     (0x7UL << AON_REG_SYSTEM_REG18X_LDO_ANA_POS_FSM_CS_Pos)
+
+#define AON_REG_SYSTEM_REG18X_LDO_ANA_POS_POF_FLAG4_Pos                                                                  19U
+#define AON_REG_SYSTEM_REG18X_LDO_ANA_POS_POF_FLAG4_Msk                                                                  (0x1UL << AON_REG_SYSTEM_REG18X_LDO_ANA_POS_POF_FLAG4_Pos)
+
+#define AON_REG_SYSTEM_REG18X_LDO_ANA_POS_POF_FLAG3_Pos                                                                  20U
+#define AON_REG_SYSTEM_REG18X_LDO_ANA_POS_POF_FLAG3_Msk                                                                  (0x1UL << AON_REG_SYSTEM_REG18X_LDO_ANA_POS_POF_FLAG3_Pos)
+
+#define AON_REG_SYSTEM_REG18X_LDO_ANA_POS_POF_FLAG2_Pos                                                                  21U
+#define AON_REG_SYSTEM_REG18X_LDO_ANA_POS_POF_FLAG2_Msk                                                                  (0x1UL << AON_REG_SYSTEM_REG18X_LDO_ANA_POS_POF_FLAG2_Pos)
+
+#define AON_REG_SYSTEM_REG18X_LDO_ANA_POS_POF_FLAG1_Pos                                                                  22U
+#define AON_REG_SYSTEM_REG18X_LDO_ANA_POS_POF_FLAG1_Msk                                                                  (0x1UL << AON_REG_SYSTEM_REG18X_LDO_ANA_POS_POF_FLAG1_Pos)
+
+#define AON_REG_SYSTEM_REG18X_LDO_ANA_POS_PON_FLAG4_Pos                                                                  23U
+#define AON_REG_SYSTEM_REG18X_LDO_ANA_POS_PON_FLAG4_Msk                                                                  (0x1UL << AON_REG_SYSTEM_REG18X_LDO_ANA_POS_PON_FLAG4_Pos)
+
+#define AON_REG_SYSTEM_REG18X_LDO_ANA_POS_PON_FLAG3_Pos                                                                  24U
+#define AON_REG_SYSTEM_REG18X_LDO_ANA_POS_PON_FLAG3_Msk                                                                  (0x1UL << AON_REG_SYSTEM_REG18X_LDO_ANA_POS_PON_FLAG3_Pos)
+
+#define AON_REG_SYSTEM_REG18X_LDO_ANA_POS_PON_FLAG2_Pos                                                                  25U
+#define AON_REG_SYSTEM_REG18X_LDO_ANA_POS_PON_FLAG2_Msk                                                                  (0x1UL << AON_REG_SYSTEM_REG18X_LDO_ANA_POS_PON_FLAG2_Pos)
+
+#define AON_REG_SYSTEM_REG18X_LDO_ANA_POS_PON_FLAG1_Pos                                                                  26U
+#define AON_REG_SYSTEM_REG18X_LDO_ANA_POS_PON_FLAG1_Msk                                                                  (0x1UL << AON_REG_SYSTEM_REG18X_LDO_ANA_POS_PON_FLAG1_Pos)
+
+#define AON_REG_SYSTEM_REG18X_LDO_ANA_POS_DIV_CLK_Pos                                                                    27U
+#define AON_REG_SYSTEM_REG18X_LDO_ANA_POS_DIV_CLK_Msk                                                                    (0x7UL << AON_REG_SYSTEM_REG18X_LDO_ANA_POS_DIV_CLK_Pos)
+
+#define AON_REG_SYSTEM_REG18X_LDO_ANA_POS_CLK_GATED_Pos                                                                  30U
+#define AON_REG_SYSTEM_REG18X_LDO_ANA_POS_CLK_GATED_Msk                                                                  (0x1UL << AON_REG_SYSTEM_REG18X_LDO_ANA_POS_CLK_GATED_Pos)
+
+#define AON_REG_SYSTEM_REG18X_RESERVED_Pos                                                                               31U
+#define AON_REG_SYSTEM_REG18X_RESERVED_Msk                                                                               (0x1UL << AON_REG_SYSTEM_REG18X_RESERVED_Pos)
+
+/* 0x4C     0x4000_004c
+    0       R/W     LDO_PA_POS_RSTB                                             1'b0
+    1       R/W     LDO_PA_POS_EN_POS                                           1'b0
+    5:2     R/W     LDO_PA_POS_POF_STEP                                         4'b0001
+    9:6     R/W     LDO_PA_POS_PON_STEP                                         4'b0001
+    12:10   R/W     LDO_PA_POS_POF_WAIT                                         3'b000
+    15:13   R/W     LDO_PA_POS_PON_WAIT                                         3'b000
+    23:16   R/W     LDO_PA_POS_PON_OVER                                         8'b00111111
+    31:24   R/W     LDO_PA_POS_PON_START                                        8'b00000000
+ */
+typedef union _AON_REG_SYSTEM_REG19X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t LDO_PA_POS_RSTB: 1;
+        uint32_t LDO_PA_POS_EN_POS: 1;
+        uint32_t LDO_PA_POS_POF_STEP: 4;
+        uint32_t LDO_PA_POS_PON_STEP: 4;
+        uint32_t LDO_PA_POS_POF_WAIT: 3;
+        uint32_t LDO_PA_POS_PON_WAIT: 3;
+        uint32_t LDO_PA_POS_PON_OVER: 8;
+        uint32_t LDO_PA_POS_PON_START: 8;
+    };
+} AON_REG_SYSTEM_REG19X_TYPE;
+
+/*0x4000_004c AON_REG_SYSTEM_REG19X*/
+#define AON_REG_SYSTEM_REG19X_LDO_PA_POS_RSTB_Pos                                                                        0U
+#define AON_REG_SYSTEM_REG19X_LDO_PA_POS_RSTB_Msk                                                                        (0x1UL << AON_REG_SYSTEM_REG19X_LDO_PA_POS_RSTB_Pos)
+
+#define AON_REG_SYSTEM_REG19X_LDO_PA_POS_EN_POS_Pos                                                                      1U
+#define AON_REG_SYSTEM_REG19X_LDO_PA_POS_EN_POS_Msk                                                                      (0x1UL << AON_REG_SYSTEM_REG19X_LDO_PA_POS_EN_POS_Pos)
+
+#define AON_REG_SYSTEM_REG19X_LDO_PA_POS_POF_STEP_Pos                                                                    2U
+#define AON_REG_SYSTEM_REG19X_LDO_PA_POS_POF_STEP_Msk                                                                    (0xFUL << AON_REG_SYSTEM_REG19X_LDO_PA_POS_POF_STEP_Pos)
+
+#define AON_REG_SYSTEM_REG19X_LDO_PA_POS_PON_STEP_Pos                                                                    6U
+#define AON_REG_SYSTEM_REG19X_LDO_PA_POS_PON_STEP_Msk                                                                    (0xFUL << AON_REG_SYSTEM_REG19X_LDO_PA_POS_PON_STEP_Pos)
+
+#define AON_REG_SYSTEM_REG19X_LDO_PA_POS_POF_WAIT_Pos                                                                    10U
+#define AON_REG_SYSTEM_REG19X_LDO_PA_POS_POF_WAIT_Msk                                                                    (0x7UL << AON_REG_SYSTEM_REG19X_LDO_PA_POS_POF_WAIT_Pos)
+
+#define AON_REG_SYSTEM_REG19X_LDO_PA_POS_PON_WAIT_Pos                                                                    13U
+#define AON_REG_SYSTEM_REG19X_LDO_PA_POS_PON_WAIT_Msk                                                                    (0x7UL << AON_REG_SYSTEM_REG19X_LDO_PA_POS_PON_WAIT_Pos)
+
+#define AON_REG_SYSTEM_REG19X_LDO_PA_POS_PON_OVER_Pos                                                                    16U
+#define AON_REG_SYSTEM_REG19X_LDO_PA_POS_PON_OVER_Msk                                                                    (0xFFUL << AON_REG_SYSTEM_REG19X_LDO_PA_POS_PON_OVER_Pos)
+
+#define AON_REG_SYSTEM_REG19X_LDO_PA_POS_PON_START_Pos                                                                   24U
+#define AON_REG_SYSTEM_REG19X_LDO_PA_POS_PON_START_Msk                                                                   (0xFFUL << AON_REG_SYSTEM_REG19X_LDO_PA_POS_PON_START_Pos)
+
+/* 0x50     0x4000_0050
+    7:0     R/W     LDO_PA_POS_POF_OVER                                         8'b00000000
+    15:8    R/W     LDO_PA_POS_POF_START                                        8'b00011111
+    23:16   R/W     LDO_PA_POS_SET_PON_FLAG1                                    8'b00000000
+    31:24   R/W     LDO_PA_POS_SET_PON_FLAG2                                    8'b00011000
+ */
+typedef union _AON_REG_SYSTEM_REG20X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t LDO_PA_POS_POF_OVER: 8;
+        uint32_t LDO_PA_POS_POF_START: 8;
+        uint32_t LDO_PA_POS_SET_PON_FLAG1: 8;
+        uint32_t LDO_PA_POS_SET_PON_FLAG2: 8;
+    };
+} AON_REG_SYSTEM_REG20X_TYPE;
+
+/*0x4000_0050 AON_REG_SYSTEM_REG20X*/
+#define AON_REG_SYSTEM_REG20X_LDO_PA_POS_POF_OVER_Pos                                                                    0U
+#define AON_REG_SYSTEM_REG20X_LDO_PA_POS_POF_OVER_Msk                                                                    (0xFFUL << AON_REG_SYSTEM_REG20X_LDO_PA_POS_POF_OVER_Pos)
+
+#define AON_REG_SYSTEM_REG20X_LDO_PA_POS_POF_START_Pos                                                                   8U
+#define AON_REG_SYSTEM_REG20X_LDO_PA_POS_POF_START_Msk                                                                   (0xFFUL << AON_REG_SYSTEM_REG20X_LDO_PA_POS_POF_START_Pos)
+
+#define AON_REG_SYSTEM_REG20X_LDO_PA_POS_SET_PON_FLAG1_Pos                                                               16U
+#define AON_REG_SYSTEM_REG20X_LDO_PA_POS_SET_PON_FLAG1_Msk                                                               (0xFFUL << AON_REG_SYSTEM_REG20X_LDO_PA_POS_SET_PON_FLAG1_Pos)
+
+#define AON_REG_SYSTEM_REG20X_LDO_PA_POS_SET_PON_FLAG2_Pos                                                               24U
+#define AON_REG_SYSTEM_REG20X_LDO_PA_POS_SET_PON_FLAG2_Msk                                                               (0xFFUL << AON_REG_SYSTEM_REG20X_LDO_PA_POS_SET_PON_FLAG2_Pos)
+
+/* 0x54     0x4000_0054
+    7:0     R/W     LDO_PA_POS_SET_PON_FLAG3                                    8'b00011100
+    15:8    R/W     LDO_PA_POS_SET_PON_FLAG4                                    8'b00011111
+    23:16   R/W     LDO_PA_POS_SET_POF_FLAG1                                    8'b00000111
+    31:24   R/W     LDO_PA_POS_SET_POF_FLAG2                                    8'b00000110
+ */
+typedef union _AON_REG_SYSTEM_REG21X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t LDO_PA_POS_SET_PON_FLAG3: 8;
+        uint32_t LDO_PA_POS_SET_PON_FLAG4: 8;
+        uint32_t LDO_PA_POS_SET_POF_FLAG1: 8;
+        uint32_t LDO_PA_POS_SET_POF_FLAG2: 8;
+    };
+} AON_REG_SYSTEM_REG21X_TYPE;
+
+/*0x4000_0054 AON_REG_SYSTEM_REG21X*/
+#define AON_REG_SYSTEM_REG21X_LDO_PA_POS_SET_PON_FLAG3_Pos                                                               0U
+#define AON_REG_SYSTEM_REG21X_LDO_PA_POS_SET_PON_FLAG3_Msk                                                               (0xFFUL << AON_REG_SYSTEM_REG21X_LDO_PA_POS_SET_PON_FLAG3_Pos)
+
+#define AON_REG_SYSTEM_REG21X_LDO_PA_POS_SET_PON_FLAG4_Pos                                                               8U
+#define AON_REG_SYSTEM_REG21X_LDO_PA_POS_SET_PON_FLAG4_Msk                                                               (0xFFUL << AON_REG_SYSTEM_REG21X_LDO_PA_POS_SET_PON_FLAG4_Pos)
+
+#define AON_REG_SYSTEM_REG21X_LDO_PA_POS_SET_POF_FLAG1_Pos                                                               16U
+#define AON_REG_SYSTEM_REG21X_LDO_PA_POS_SET_POF_FLAG1_Msk                                                               (0xFFUL << AON_REG_SYSTEM_REG21X_LDO_PA_POS_SET_POF_FLAG1_Pos)
+
+#define AON_REG_SYSTEM_REG21X_LDO_PA_POS_SET_POF_FLAG2_Pos                                                               24U
+#define AON_REG_SYSTEM_REG21X_LDO_PA_POS_SET_POF_FLAG2_Msk                                                               (0xFFUL << AON_REG_SYSTEM_REG21X_LDO_PA_POS_SET_POF_FLAG2_Pos)
+
+/* 0x58     0x4000_0058
+    7:0     R/W     LDO_PA_POS_SET_POF_FLAG3                                    8'b00000001
+    15:8    R/W     LDO_PA_POS_SET_POF_FLAG4                                    8'b00000000
+    18:16   R       LDO_PA_POS_FSM_CS                                           3'b000
+    19      R       LDO_PA_POS_POF_FLAG4                                        1'b0
+    20      R       LDO_PA_POS_POF_FLAG3                                        1'b0
+    21      R       LDO_PA_POS_POF_FLAG2                                        1'b0
+    22      R       LDO_PA_POS_POF_FLAG1                                        1'b0
+    23      R       LDO_PA_POS_PON_FLAG4                                        1'b0
+    24      R       LDO_PA_POS_PON_FLAG3                                        1'b0
+    25      R       LDO_PA_POS_PON_FLAG2                                        1'b0
+    26      R       LDO_PA_POS_PON_FLAG1                                        1'b0
+    29:27   R/W     LDO_PA_POS_DIV_CLK                                          3'b101
+    30      R/W     LDO_PA_POS_CLK_GATED                                        1'b1
+    31      R       RESERVED                                                    1'b0
+ */
+typedef union _AON_REG_SYSTEM_REG22X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t LDO_PA_POS_SET_POF_FLAG3: 8;
+        uint32_t LDO_PA_POS_SET_POF_FLAG4: 8;
+        uint32_t LDO_PA_POS_FSM_CS: 3;
+        uint32_t LDO_PA_POS_POF_FLAG4: 1;
+        uint32_t LDO_PA_POS_POF_FLAG3: 1;
+        uint32_t LDO_PA_POS_POF_FLAG2: 1;
+        uint32_t LDO_PA_POS_POF_FLAG1: 1;
+        uint32_t LDO_PA_POS_PON_FLAG4: 1;
+        uint32_t LDO_PA_POS_PON_FLAG3: 1;
+        uint32_t LDO_PA_POS_PON_FLAG2: 1;
+        uint32_t LDO_PA_POS_PON_FLAG1: 1;
+        uint32_t LDO_PA_POS_DIV_CLK: 3;
+        uint32_t LDO_PA_POS_CLK_GATED: 1;
+        uint32_t RESERVED: 1;
+    };
+} AON_REG_SYSTEM_REG22X_TYPE;
+
+/*0x4000_0058 AON_REG_SYSTEM_REG22X*/
+#define AON_REG_SYSTEM_REG22X_LDO_PA_POS_SET_POF_FLAG3_Pos                                                               0U
+#define AON_REG_SYSTEM_REG22X_LDO_PA_POS_SET_POF_FLAG3_Msk                                                               (0xFFUL << AON_REG_SYSTEM_REG22X_LDO_PA_POS_SET_POF_FLAG3_Pos)
+
+#define AON_REG_SYSTEM_REG22X_LDO_PA_POS_SET_POF_FLAG4_Pos                                                               8U
+#define AON_REG_SYSTEM_REG22X_LDO_PA_POS_SET_POF_FLAG4_Msk                                                               (0xFFUL << AON_REG_SYSTEM_REG22X_LDO_PA_POS_SET_POF_FLAG4_Pos)
+
+#define AON_REG_SYSTEM_REG22X_LDO_PA_POS_FSM_CS_Pos                                                                      16U
+#define AON_REG_SYSTEM_REG22X_LDO_PA_POS_FSM_CS_Msk                                                                      (0x7UL << AON_REG_SYSTEM_REG22X_LDO_PA_POS_FSM_CS_Pos)
+
+#define AON_REG_SYSTEM_REG22X_LDO_PA_POS_POF_FLAG4_Pos                                                                   19U
+#define AON_REG_SYSTEM_REG22X_LDO_PA_POS_POF_FLAG4_Msk                                                                   (0x1UL << AON_REG_SYSTEM_REG22X_LDO_PA_POS_POF_FLAG4_Pos)
+
+#define AON_REG_SYSTEM_REG22X_LDO_PA_POS_POF_FLAG3_Pos                                                                   20U
+#define AON_REG_SYSTEM_REG22X_LDO_PA_POS_POF_FLAG3_Msk                                                                   (0x1UL << AON_REG_SYSTEM_REG22X_LDO_PA_POS_POF_FLAG3_Pos)
+
+#define AON_REG_SYSTEM_REG22X_LDO_PA_POS_POF_FLAG2_Pos                                                                   21U
+#define AON_REG_SYSTEM_REG22X_LDO_PA_POS_POF_FLAG2_Msk                                                                   (0x1UL << AON_REG_SYSTEM_REG22X_LDO_PA_POS_POF_FLAG2_Pos)
+
+#define AON_REG_SYSTEM_REG22X_LDO_PA_POS_POF_FLAG1_Pos                                                                   22U
+#define AON_REG_SYSTEM_REG22X_LDO_PA_POS_POF_FLAG1_Msk                                                                   (0x1UL << AON_REG_SYSTEM_REG22X_LDO_PA_POS_POF_FLAG1_Pos)
+
+#define AON_REG_SYSTEM_REG22X_LDO_PA_POS_PON_FLAG4_Pos                                                                   23U
+#define AON_REG_SYSTEM_REG22X_LDO_PA_POS_PON_FLAG4_Msk                                                                   (0x1UL << AON_REG_SYSTEM_REG22X_LDO_PA_POS_PON_FLAG4_Pos)
+
+#define AON_REG_SYSTEM_REG22X_LDO_PA_POS_PON_FLAG3_Pos                                                                   24U
+#define AON_REG_SYSTEM_REG22X_LDO_PA_POS_PON_FLAG3_Msk                                                                   (0x1UL << AON_REG_SYSTEM_REG22X_LDO_PA_POS_PON_FLAG3_Pos)
+
+#define AON_REG_SYSTEM_REG22X_LDO_PA_POS_PON_FLAG2_Pos                                                                   25U
+#define AON_REG_SYSTEM_REG22X_LDO_PA_POS_PON_FLAG2_Msk                                                                   (0x1UL << AON_REG_SYSTEM_REG22X_LDO_PA_POS_PON_FLAG2_Pos)
+
+#define AON_REG_SYSTEM_REG22X_LDO_PA_POS_PON_FLAG1_Pos                                                                   26U
+#define AON_REG_SYSTEM_REG22X_LDO_PA_POS_PON_FLAG1_Msk                                                                   (0x1UL << AON_REG_SYSTEM_REG22X_LDO_PA_POS_PON_FLAG1_Pos)
+
+#define AON_REG_SYSTEM_REG22X_LDO_PA_POS_DIV_CLK_Pos                                                                     27U
+#define AON_REG_SYSTEM_REG22X_LDO_PA_POS_DIV_CLK_Msk                                                                     (0x7UL << AON_REG_SYSTEM_REG22X_LDO_PA_POS_DIV_CLK_Pos)
+
+#define AON_REG_SYSTEM_REG22X_LDO_PA_POS_CLK_GATED_Pos                                                                   30U
+#define AON_REG_SYSTEM_REG22X_LDO_PA_POS_CLK_GATED_Msk                                                                   (0x1UL << AON_REG_SYSTEM_REG22X_LDO_PA_POS_CLK_GATED_Pos)
+
+#define AON_REG_SYSTEM_REG22X_RESERVED_Pos                                                                               31U
+#define AON_REG_SYSTEM_REG22X_RESERVED_Msk                                                                               (0x1UL << AON_REG_SYSTEM_REG22X_RESERVED_Pos)
+
+/* 0x5C     0x4000_005c
+    0       R/W     REG_SCAN_MODE                                               1'b0
+    1       R/W     SPC_DISABLE                                                 1'b0
+    2       R/W     COMP_EN                                                     1'b0
+    3       R/W     PLL_BYPASS                                                  1'b0
+    6:4     R/W     FT_MODE                                                     3'h0
+    8:7     R/W     DEBUG_EN                                                    2'h0
+    11:9    R/W     OCC_DEBUG_CLK_SEL0                                          3'h0
+    14:12   R/W     OCC_DEBUG_CLK_SEL1                                          3'h0
+    15      R/W     FT_14PIN_CASE_EN                                            1'b0
+    16      R/W     SCAN_AT_SPEED_DBG_EN_USBPHY                                 1'b0
+    17      R/W     FT_14PIN_CASE2_EN                                           1'b0
+    18      R/W     SCAN_TDF_40M_LV_TEST_EN                                     1'b0
+    31:19   R/W     RSVD                                                        13'h0
+ */
+typedef union _AON_REG_SYSTEM_REG23X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t REG_SCAN_MODE: 1;
+        uint32_t SPC_DISABLE: 1;
+        uint32_t COMP_EN: 1;
+        uint32_t PLL_BYPASS: 1;
+        uint32_t FT_MODE: 3;
+        uint32_t DEBUG_EN: 2;
+        uint32_t OCC_DEBUG_CLK_SEL0: 3;
+        uint32_t OCC_DEBUG_CLK_SEL1: 3;
+        uint32_t FT_14PIN_CASE_EN: 1;
+        uint32_t SCAN_AT_SPEED_DBG_EN_USBPHY: 1;
+        uint32_t FT_14PIN_CASE2_EN: 1;
+        uint32_t SCAN_TDF_40M_LV_TEST_EN: 1;
+        uint32_t RSVD: 13;
+    };
+} AON_REG_SYSTEM_REG23X_TYPE;
+
+/*0x4000_005c AON_REG_SYSTEM_REG23X*/
+#define AON_REG_SYSTEM_REG23X_REG_SCAN_MODE_Pos                                                                          0U
+#define AON_REG_SYSTEM_REG23X_REG_SCAN_MODE_Msk                                                                          (0x1UL << AON_REG_SYSTEM_REG23X_REG_SCAN_MODE_Pos)
+
+#define AON_REG_SYSTEM_REG23X_SPC_DISABLE_Pos                                                                            1U
+#define AON_REG_SYSTEM_REG23X_SPC_DISABLE_Msk                                                                            (0x1UL << AON_REG_SYSTEM_REG23X_SPC_DISABLE_Pos)
+
+#define AON_REG_SYSTEM_REG23X_COMP_EN_Pos                                                                                2U
+#define AON_REG_SYSTEM_REG23X_COMP_EN_Msk                                                                                (0x1UL << AON_REG_SYSTEM_REG23X_COMP_EN_Pos)
+
+#define AON_REG_SYSTEM_REG23X_PLL_BYPASS_Pos                                                                             3U
+#define AON_REG_SYSTEM_REG23X_PLL_BYPASS_Msk                                                                             (0x1UL << AON_REG_SYSTEM_REG23X_PLL_BYPASS_Pos)
+
+#define AON_REG_SYSTEM_REG23X_FT_MODE_Pos                                                                                4U
+#define AON_REG_SYSTEM_REG23X_FT_MODE_Msk                                                                                (0x7UL << AON_REG_SYSTEM_REG23X_FT_MODE_Pos)
+
+#define AON_REG_SYSTEM_REG23X_DEBUG_EN_Pos                                                                               7U
+#define AON_REG_SYSTEM_REG23X_DEBUG_EN_Msk                                                                               (0x3UL << AON_REG_SYSTEM_REG23X_DEBUG_EN_Pos)
+
+#define AON_REG_SYSTEM_REG23X_OCC_DEBUG_CLK_SEL0_Pos                                                                     9U
+#define AON_REG_SYSTEM_REG23X_OCC_DEBUG_CLK_SEL0_Msk                                                                     (0x7UL << AON_REG_SYSTEM_REG23X_OCC_DEBUG_CLK_SEL0_Pos)
+
+#define AON_REG_SYSTEM_REG23X_OCC_DEBUG_CLK_SEL1_Pos                                                                     12U
+#define AON_REG_SYSTEM_REG23X_OCC_DEBUG_CLK_SEL1_Msk                                                                     (0x7UL << AON_REG_SYSTEM_REG23X_OCC_DEBUG_CLK_SEL1_Pos)
+
+#define AON_REG_SYSTEM_REG23X_FT_14PIN_CASE_EN_Pos                                                                       15U
+#define AON_REG_SYSTEM_REG23X_FT_14PIN_CASE_EN_Msk                                                                       (0x1UL << AON_REG_SYSTEM_REG23X_FT_14PIN_CASE_EN_Pos)
+
+#define AON_REG_SYSTEM_REG23X_SCAN_AT_SPEED_DBG_EN_USBPHY_Pos                                                            16U
+#define AON_REG_SYSTEM_REG23X_SCAN_AT_SPEED_DBG_EN_USBPHY_Msk                                                            (0x1UL << AON_REG_SYSTEM_REG23X_SCAN_AT_SPEED_DBG_EN_USBPHY_Pos)
+
+#define AON_REG_SYSTEM_REG23X_FT_14PIN_CASE2_EN_Pos                                                                      17U
+#define AON_REG_SYSTEM_REG23X_FT_14PIN_CASE2_EN_Msk                                                                      (0x1UL << AON_REG_SYSTEM_REG23X_FT_14PIN_CASE2_EN_Pos)
+
+#define AON_REG_SYSTEM_REG23X_SCAN_TDF_40M_LV_TEST_EN_Pos                                                                18U
+#define AON_REG_SYSTEM_REG23X_SCAN_TDF_40M_LV_TEST_EN_Msk                                                                (0x1UL << AON_REG_SYSTEM_REG23X_SCAN_TDF_40M_LV_TEST_EN_Pos)
+
+#define AON_REG_SYSTEM_REG23X_RSVD_Pos                                                                                   19U
+#define AON_REG_SYSTEM_REG23X_RSVD_Msk                                                                                   (0x1FFFUL << AON_REG_SYSTEM_REG23X_RSVD_Pos)
+
+/* 0x60     0x4000_0060
+    0       R/W     SDM_CLK_SRC_SEL                                             1'b0
+    1       R/W     SDM32K_RSTN                                                 1'b1
+    31:2    R/W     RSVD                                                        30'h0
+ */
+typedef union _AON_REG_SYSTEM_REG24X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t SDM_CLK_SRC_SEL: 1;
+        uint32_t SDM32K_RSTN: 1;
+        uint32_t RSVD: 30;
+    };
+} AON_REG_SYSTEM_REG24X_TYPE;
+
+/*0x4000_0060 AON_REG_SYSTEM_REG24X*/
+#define AON_REG_SYSTEM_REG24X_SDM_CLK_SRC_SEL_Pos                                                                        0U
+#define AON_REG_SYSTEM_REG24X_SDM_CLK_SRC_SEL_Msk                                                                        (0x1UL << AON_REG_SYSTEM_REG24X_SDM_CLK_SRC_SEL_Pos)
+
+#define AON_REG_SYSTEM_REG24X_SDM32K_RSTN_Pos                                                                            1U
+#define AON_REG_SYSTEM_REG24X_SDM32K_RSTN_Msk                                                                            (0x1UL << AON_REG_SYSTEM_REG24X_SDM32K_RSTN_Pos)
+
+#define AON_REG_SYSTEM_REG24X_RSVD_Pos                                                                                   2U
+#define AON_REG_SYSTEM_REG24X_RSVD_Msk                                                                                   (0x3FFFFFFFUL << AON_REG_SYSTEM_REG24X_RSVD_Pos)
+
+/* 0x64     0x4000_0064
+    19:0    R/W     RESERVED_1                                                  20'h0
+    21:20   R/W     CACHE_AS_DATA_SRAM_EN                                       2'b0
+    22      R/W     EFLASH_PC_VDD_EN                                            1'b1
+    23      R       RESERVED                                                    1'b0
+    24      R/W     WAIT_SPIC_PDEX_ACK                                          1'b0
+    25      R       SPIC_PDEX_ACK                                               1'b0
+    26      R/W     SPIC_PDEX_CMD                                               1'b0
+    27      R/W     SPIC_PDEX_REQ                                               1'b0
+    28      R/W     WAIT_EFLASH_ACCPEPTN                                        1'b0
+    29      R       EFLASH_ACCPEPTN                                             1'b0
+    30      R/W     EFLASH_REQN                                                 1'b0
+    31      R/W     EFLASH_LVCTL_PCSM                                           1'b1
+ */
+typedef union _AON_REG_SYSTEM_REG25X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED_1: 20;
+        uint32_t CACHE_AS_DATA_SRAM_EN: 2;
+        uint32_t EFLASH_PC_VDD_EN: 1;
+        uint32_t RESERVED: 1;
+        uint32_t WAIT_SPIC_PDEX_ACK: 1;
+        uint32_t SPIC_PDEX_ACK: 1;
+        uint32_t SPIC_PDEX_CMD: 1;
+        uint32_t SPIC_PDEX_REQ: 1;
+        uint32_t WAIT_EFLASH_ACCPEPTN: 1;
+        uint32_t EFLASH_ACCPEPTN: 1;
+        uint32_t EFLASH_REQN: 1;
+        uint32_t EFLASH_LVCTL_PCSM: 1;
+    };
+} AON_REG_SYSTEM_REG25X_TYPE;
+
+/*0x4000_0064 AON_REG_SYSTEM_REG25X*/
+#define AON_REG_SYSTEM_REG25X_RESERVED_1_Pos                                                                             0U
+#define AON_REG_SYSTEM_REG25X_RESERVED_1_Msk                                                                             (0xFFFFFUL << AON_REG_SYSTEM_REG25X_RESERVED_1_Pos)
+
+#define AON_REG_SYSTEM_REG25X_CACHE_AS_DATA_SRAM_EN_Pos                                                                  20U
+#define AON_REG_SYSTEM_REG25X_CACHE_AS_DATA_SRAM_EN_Msk                                                                  (0x3UL << AON_REG_SYSTEM_REG25X_CACHE_AS_DATA_SRAM_EN_Pos)
+
+#define AON_REG_SYSTEM_REG25X_EFLASH_PC_VDD_EN_Pos                                                                       22U
+#define AON_REG_SYSTEM_REG25X_EFLASH_PC_VDD_EN_Msk                                                                       (0x1UL << AON_REG_SYSTEM_REG25X_EFLASH_PC_VDD_EN_Pos)
+
+#define AON_REG_SYSTEM_REG25X_RESERVED_Pos                                                                               23U
+#define AON_REG_SYSTEM_REG25X_RESERVED_Msk                                                                               (0x1UL << AON_REG_SYSTEM_REG25X_RESERVED_Pos)
+
+#define AON_REG_SYSTEM_REG25X_WAIT_SPIC_PDEX_ACK_Pos                                                                     24U
+#define AON_REG_SYSTEM_REG25X_WAIT_SPIC_PDEX_ACK_Msk                                                                     (0x1UL << AON_REG_SYSTEM_REG25X_WAIT_SPIC_PDEX_ACK_Pos)
+
+#define AON_REG_SYSTEM_REG25X_SPIC_PDEX_ACK_Pos                                                                          25U
+#define AON_REG_SYSTEM_REG25X_SPIC_PDEX_ACK_Msk                                                                          (0x1UL << AON_REG_SYSTEM_REG25X_SPIC_PDEX_ACK_Pos)
+
+#define AON_REG_SYSTEM_REG25X_SPIC_PDEX_CMD_Pos                                                                          26U
+#define AON_REG_SYSTEM_REG25X_SPIC_PDEX_CMD_Msk                                                                          (0x1UL << AON_REG_SYSTEM_REG25X_SPIC_PDEX_CMD_Pos)
+
+#define AON_REG_SYSTEM_REG25X_SPIC_PDEX_REQ_Pos                                                                          27U
+#define AON_REG_SYSTEM_REG25X_SPIC_PDEX_REQ_Msk                                                                          (0x1UL << AON_REG_SYSTEM_REG25X_SPIC_PDEX_REQ_Pos)
+
+#define AON_REG_SYSTEM_REG25X_WAIT_EFLASH_ACCPEPTN_Pos                                                                   28U
+#define AON_REG_SYSTEM_REG25X_WAIT_EFLASH_ACCPEPTN_Msk                                                                   (0x1UL << AON_REG_SYSTEM_REG25X_WAIT_EFLASH_ACCPEPTN_Pos)
+
+#define AON_REG_SYSTEM_REG25X_EFLASH_ACCPEPTN_Pos                                                                        29U
+#define AON_REG_SYSTEM_REG25X_EFLASH_ACCPEPTN_Msk                                                                        (0x1UL << AON_REG_SYSTEM_REG25X_EFLASH_ACCPEPTN_Pos)
+
+#define AON_REG_SYSTEM_REG25X_EFLASH_REQN_Pos                                                                            30U
+#define AON_REG_SYSTEM_REG25X_EFLASH_REQN_Msk                                                                            (0x1UL << AON_REG_SYSTEM_REG25X_EFLASH_REQN_Pos)
+
+#define AON_REG_SYSTEM_REG25X_EFLASH_LVCTL_PCSM_Pos                                                                      31U
+#define AON_REG_SYSTEM_REG25X_EFLASH_LVCTL_PCSM_Msk                                                                      (0x1UL << AON_REG_SYSTEM_REG25X_EFLASH_LVCTL_PCSM_Pos)
+
+/* 0x68     0x4000_0068
+    0       R/W     REG0X_AON_SYS_DUMMY_0                                       1'b1
+    1       R/W     RESERVED_1                                                  1'b0
+    2       R/W     WAIT_VDDCORE_POR_DET                                        1'b0
+    11:3    R/W     REG0X_AON_SYS_DUMMY_15_3                                    9'h0
+    12      R/W     FORCE_QACTIVE_PLL1                                          1'b0
+    13      R       CLKEN_O_CLKCTRL_OSC10M_VPON                                 1'b1
+    14      R       CLKEN_O_CLKCTRL_OSC10M                                      1'b0
+    15      R       CLKEN_O_CLKCTRL_OSC128K_VPON                                1'b0
+    16      R       CLKEN_O_CLKCTRL_OSC128K                                     1'b0
+    31:17   R       RESERVED                                                    15'h0
+ */
+typedef union _AON_REG_SYSTEM_REG26X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t REG0X_AON_SYS_DUMMY_0: 1;
+        uint32_t RESERVED_1: 1;
+        uint32_t WAIT_VDDCORE_POR_DET: 1;
+        uint32_t REG0X_AON_SYS_DUMMY_15_3: 9;
+        uint32_t FORCE_QACTIVE_PLL1: 1;
+        uint32_t CLKEN_O_CLKCTRL_OSC10M_VPON: 1;
+        uint32_t CLKEN_O_CLKCTRL_OSC10M: 1;
+        uint32_t CLKEN_O_CLKCTRL_OSC128K_VPON: 1;
+        uint32_t CLKEN_O_CLKCTRL_OSC128K: 1;
+        uint32_t RESERVED: 15;
+    };
+} AON_REG_SYSTEM_REG26X_TYPE;
+
+/*0x4000_0068 AON_REG_SYSTEM_REG26X*/
+#define AON_REG_SYSTEM_REG26X_REG0X_AON_SYS_DUMMY_0_Pos                                                                  0U
+#define AON_REG_SYSTEM_REG26X_REG0X_AON_SYS_DUMMY_0_Msk                                                                  (0x1UL << AON_REG_SYSTEM_REG26X_REG0X_AON_SYS_DUMMY_0_Pos)
+
+#define AON_REG_SYSTEM_REG26X_RESERVED_1_Pos                                                                             1U
+#define AON_REG_SYSTEM_REG26X_RESERVED_1_Msk                                                                             (0x1UL << AON_REG_SYSTEM_REG26X_RESERVED_1_Pos)
+
+#define AON_REG_SYSTEM_REG26X_WAIT_VDDCORE_POR_DET_Pos                                                                   2U
+#define AON_REG_SYSTEM_REG26X_WAIT_VDDCORE_POR_DET_Msk                                                                   (0x1UL << AON_REG_SYSTEM_REG26X_WAIT_VDDCORE_POR_DET_Pos)
+
+#define AON_REG_SYSTEM_REG26X_REG0X_AON_SYS_DUMMY_15_3_Pos                                                               3U
+#define AON_REG_SYSTEM_REG26X_REG0X_AON_SYS_DUMMY_15_3_Msk                                                               (0x1FFUL << AON_REG_SYSTEM_REG26X_REG0X_AON_SYS_DUMMY_15_3_Pos)
+
+#define AON_REG_SYSTEM_REG26X_FORCE_QACTIVE_PLL1_Pos                                                                     12U
+#define AON_REG_SYSTEM_REG26X_FORCE_QACTIVE_PLL1_Msk                                                                     (0x1UL << AON_REG_SYSTEM_REG26X_FORCE_QACTIVE_PLL1_Pos)
+
+#define AON_REG_SYSTEM_REG26X_CLKEN_O_CLKCTRL_OSC10M_VPON_Pos                                                            13U
+#define AON_REG_SYSTEM_REG26X_CLKEN_O_CLKCTRL_OSC10M_VPON_Msk                                                            (0x1UL << AON_REG_SYSTEM_REG26X_CLKEN_O_CLKCTRL_OSC10M_VPON_Pos)
+
+#define AON_REG_SYSTEM_REG26X_CLKEN_O_CLKCTRL_OSC10M_Pos                                                                 14U
+#define AON_REG_SYSTEM_REG26X_CLKEN_O_CLKCTRL_OSC10M_Msk                                                                 (0x1UL << AON_REG_SYSTEM_REG26X_CLKEN_O_CLKCTRL_OSC10M_Pos)
+
+#define AON_REG_SYSTEM_REG26X_CLKEN_O_CLKCTRL_OSC128K_VPON_Pos                                                           15U
+#define AON_REG_SYSTEM_REG26X_CLKEN_O_CLKCTRL_OSC128K_VPON_Msk                                                           (0x1UL << AON_REG_SYSTEM_REG26X_CLKEN_O_CLKCTRL_OSC128K_VPON_Pos)
+
+#define AON_REG_SYSTEM_REG26X_CLKEN_O_CLKCTRL_OSC128K_Pos                                                                16U
+#define AON_REG_SYSTEM_REG26X_CLKEN_O_CLKCTRL_OSC128K_Msk                                                                (0x1UL << AON_REG_SYSTEM_REG26X_CLKEN_O_CLKCTRL_OSC128K_Pos)
+
+#define AON_REG_SYSTEM_REG26X_RESERVED_Pos                                                                               17U
+#define AON_REG_SYSTEM_REG26X_RESERVED_Msk                                                                               (0x7FFFUL << AON_REG_SYSTEM_REG26X_RESERVED_Pos)
+
+/* 0x6C     0x4000_006c
+    0       R/W     LPC_DEB_SEL                                                 1'b0
+    3:1     R/W     AON_DBG_SCH_PLAN_SEL                                        3'b000
+    4       W1O     REG_AON_W1O_HB_FUNC_DIS                                     1'b0
+    9:5     R/W     AON_DBG_SEL                                                 5'b00000
+    11:10   R/W     OSC_DEB_CLK_SEL                                             2'b00
+    15:12   R/W     AON_DBG_C_KOUT_POS_SEL                                      4'b0
+    19:16   R/W     AON_DBG_C_KOUT_SIMO_SEL                                     4'b0000
+    20      R/W     EN_RESTART_NO_CLK                                           1'b0
+    21      R/W     PINMUX_AUXTEST_SEL                                          1'b0
+    22      R/W     SWR_BY_CORE                                                 1'b0
+    23      W1O     REG_AON_W1O_LE4M_FUNC_DIS                                   1'b0
+    24      W1O     REG_AON_W1O_PAWR_FUNC_DIS                                   1'b0
+    25      W1O     REG_AON_W1O_PA_FUNC_DIS                                     1'b0
+    29:26   R       RO_WK_RESULT                                                4'h8
+    31:30   R       RESERVED                                                    2'h0
+ */
+typedef union _AON_REG_SYSTEM_REG27X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t LPC_DEB_SEL: 1;
+        uint32_t AON_DBG_SCH_PLAN_SEL: 3;
+        uint32_t REG_AON_W1O_HB_FUNC_DIS: 1;
+        uint32_t AON_DBG_SEL: 5;
+        uint32_t OSC_DEB_CLK_SEL: 2;
+        uint32_t AON_DBG_C_KOUT_POS_SEL: 4;
+        uint32_t AON_DBG_C_KOUT_SIMO_SEL: 4;
+        uint32_t EN_RESTART_NO_CLK: 1;
+        uint32_t PINMUX_AUXTEST_SEL: 1;
+        uint32_t SWR_BY_CORE: 1;
+        uint32_t REG_AON_W1O_LE4M_FUNC_DIS: 1;
+        uint32_t REG_AON_W1O_PAWR_FUNC_DIS: 1;
+        uint32_t REG_AON_W1O_PA_FUNC_DIS: 1;
+        uint32_t RO_WK_RESULT: 4;
+        uint32_t RESERVED: 2;
+    };
+} AON_REG_SYSTEM_REG27X_TYPE;
+
+/*0x4000_006c AON_REG_SYSTEM_REG27X*/
+#define AON_REG_SYSTEM_REG27X_LPC_DEB_SEL_Pos                                                                            0U
+#define AON_REG_SYSTEM_REG27X_LPC_DEB_SEL_Msk                                                                            (0x1UL << AON_REG_SYSTEM_REG27X_LPC_DEB_SEL_Pos)
+
+#define AON_REG_SYSTEM_REG27X_AON_DBG_SCH_PLAN_SEL_Pos                                                                   1U
+#define AON_REG_SYSTEM_REG27X_AON_DBG_SCH_PLAN_SEL_Msk                                                                   (0x7UL << AON_REG_SYSTEM_REG27X_AON_DBG_SCH_PLAN_SEL_Pos)
+
+#define AON_REG_SYSTEM_REG27X_REG_AON_W1O_HB_FUNC_DIS_Pos                                                                4U
+#define AON_REG_SYSTEM_REG27X_REG_AON_W1O_HB_FUNC_DIS_Msk                                                                (0x1UL << AON_REG_SYSTEM_REG27X_REG_AON_W1O_HB_FUNC_DIS_Pos)
+
+#define AON_REG_SYSTEM_REG27X_AON_DBG_SEL_Pos                                                                            5U
+#define AON_REG_SYSTEM_REG27X_AON_DBG_SEL_Msk                                                                            (0x1FUL << AON_REG_SYSTEM_REG27X_AON_DBG_SEL_Pos)
+
+#define AON_REG_SYSTEM_REG27X_OSC_DEB_CLK_SEL_Pos                                                                        10U
+#define AON_REG_SYSTEM_REG27X_OSC_DEB_CLK_SEL_Msk                                                                        (0x3UL << AON_REG_SYSTEM_REG27X_OSC_DEB_CLK_SEL_Pos)
+
+#define AON_REG_SYSTEM_REG27X_AON_DBG_C_KOUT_POS_SEL_Pos                                                                 12U
+#define AON_REG_SYSTEM_REG27X_AON_DBG_C_KOUT_POS_SEL_Msk                                                                 (0xFUL << AON_REG_SYSTEM_REG27X_AON_DBG_C_KOUT_POS_SEL_Pos)
+
+#define AON_REG_SYSTEM_REG27X_AON_DBG_C_KOUT_SIMO_SEL_Pos                                                                16U
+#define AON_REG_SYSTEM_REG27X_AON_DBG_C_KOUT_SIMO_SEL_Msk                                                                (0xFUL << AON_REG_SYSTEM_REG27X_AON_DBG_C_KOUT_SIMO_SEL_Pos)
+
+#define AON_REG_SYSTEM_REG27X_EN_RESTART_NO_CLK_Pos                                                                      20U
+#define AON_REG_SYSTEM_REG27X_EN_RESTART_NO_CLK_Msk                                                                      (0x1UL << AON_REG_SYSTEM_REG27X_EN_RESTART_NO_CLK_Pos)
+
+#define AON_REG_SYSTEM_REG27X_PINMUX_AUXTEST_SEL_Pos                                                                     21U
+#define AON_REG_SYSTEM_REG27X_PINMUX_AUXTEST_SEL_Msk                                                                     (0x1UL << AON_REG_SYSTEM_REG27X_PINMUX_AUXTEST_SEL_Pos)
+
+#define AON_REG_SYSTEM_REG27X_SWR_BY_CORE_Pos                                                                            22U
+#define AON_REG_SYSTEM_REG27X_SWR_BY_CORE_Msk                                                                            (0x1UL << AON_REG_SYSTEM_REG27X_SWR_BY_CORE_Pos)
+
+#define AON_REG_SYSTEM_REG27X_REG_AON_W1O_LE4M_FUNC_DIS_Pos                                                              23U
+#define AON_REG_SYSTEM_REG27X_REG_AON_W1O_LE4M_FUNC_DIS_Msk                                                              (0x1UL << AON_REG_SYSTEM_REG27X_REG_AON_W1O_LE4M_FUNC_DIS_Pos)
+
+#define AON_REG_SYSTEM_REG27X_REG_AON_W1O_PAWR_FUNC_DIS_Pos                                                              24U
+#define AON_REG_SYSTEM_REG27X_REG_AON_W1O_PAWR_FUNC_DIS_Msk                                                              (0x1UL << AON_REG_SYSTEM_REG27X_REG_AON_W1O_PAWR_FUNC_DIS_Pos)
+
+#define AON_REG_SYSTEM_REG27X_REG_AON_W1O_PA_FUNC_DIS_Pos                                                                25U
+#define AON_REG_SYSTEM_REG27X_REG_AON_W1O_PA_FUNC_DIS_Msk                                                                (0x1UL << AON_REG_SYSTEM_REG27X_REG_AON_W1O_PA_FUNC_DIS_Pos)
+
+#define AON_REG_SYSTEM_REG27X_RO_WK_RESULT_Pos                                                                           26U
+#define AON_REG_SYSTEM_REG27X_RO_WK_RESULT_Msk                                                                           (0xFUL << AON_REG_SYSTEM_REG27X_RO_WK_RESULT_Pos)
+
+#define AON_REG_SYSTEM_REG27X_RESERVED_Pos                                                                               30U
+#define AON_REG_SYSTEM_REG27X_RESERVED_Msk                                                                               (0x3UL << AON_REG_SYSTEM_REG27X_RESERVED_Pos)
+
+/* 0x70     0x4000_0070
+    15:0    R       RESERVED_8                                                  16'h0
+    20:16   R/W     RESERVED_7                                                  5'd0
+    21      R/W     RESERVED_6                                                  1'b0
+    22      R/W     RESERVED_5                                                  1'b0
+    23      R/W     RESERVED_4                                                  1'b0
+    28:24   R       RESERVED_3                                                  5'b11111
+    29      R       RESERVED_2                                                  1'b0
+    30      R       RESERVED_1                                                  1'b0
+    31      R       RESERVED                                                    1'b0
+ */
+typedef union _AON_REG_SYSTEM_REG28X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED_8: 16;
+        uint32_t RESERVED_7: 5;
+        uint32_t RESERVED_6: 1;
+        uint32_t RESERVED_5: 1;
+        uint32_t RESERVED_4: 1;
+        uint32_t RESERVED_3: 5;
+        uint32_t RESERVED_2: 1;
+        uint32_t RESERVED_1: 1;
+        uint32_t RESERVED: 1;
+    };
+} AON_REG_SYSTEM_REG28X_TYPE;
+
+/*0x4000_0070 AON_REG_SYSTEM_REG28X*/
+#define AON_REG_SYSTEM_REG28X_RESERVED_8_Pos                                                                             0U
+#define AON_REG_SYSTEM_REG28X_RESERVED_8_Msk                                                                             (0xFFFFUL << AON_REG_SYSTEM_REG28X_RESERVED_8_Pos)
+
+#define AON_REG_SYSTEM_REG28X_RESERVED_7_Pos                                                                             16U
+#define AON_REG_SYSTEM_REG28X_RESERVED_7_Msk                                                                             (0x1FUL << AON_REG_SYSTEM_REG28X_RESERVED_7_Pos)
+
+#define AON_REG_SYSTEM_REG28X_RESERVED_6_Pos                                                                             21U
+#define AON_REG_SYSTEM_REG28X_RESERVED_6_Msk                                                                             (0x1UL << AON_REG_SYSTEM_REG28X_RESERVED_6_Pos)
+
+#define AON_REG_SYSTEM_REG28X_RESERVED_5_Pos                                                                             22U
+#define AON_REG_SYSTEM_REG28X_RESERVED_5_Msk                                                                             (0x1UL << AON_REG_SYSTEM_REG28X_RESERVED_5_Pos)
+
+#define AON_REG_SYSTEM_REG28X_RESERVED_4_Pos                                                                             23U
+#define AON_REG_SYSTEM_REG28X_RESERVED_4_Msk                                                                             (0x1UL << AON_REG_SYSTEM_REG28X_RESERVED_4_Pos)
+
+#define AON_REG_SYSTEM_REG28X_RESERVED_3_Pos                                                                             24U
+#define AON_REG_SYSTEM_REG28X_RESERVED_3_Msk                                                                             (0x1FUL << AON_REG_SYSTEM_REG28X_RESERVED_3_Pos)
+
+#define AON_REG_SYSTEM_REG28X_RESERVED_2_Pos                                                                             29U
+#define AON_REG_SYSTEM_REG28X_RESERVED_2_Msk                                                                             (0x1UL << AON_REG_SYSTEM_REG28X_RESERVED_2_Pos)
+
+#define AON_REG_SYSTEM_REG28X_RESERVED_1_Pos                                                                             30U
+#define AON_REG_SYSTEM_REG28X_RESERVED_1_Msk                                                                             (0x1UL << AON_REG_SYSTEM_REG28X_RESERVED_1_Pos)
+
+#define AON_REG_SYSTEM_REG28X_RESERVED_Pos                                                                               31U
+#define AON_REG_SYSTEM_REG28X_RESERVED_Msk                                                                               (0x1UL << AON_REG_SYSTEM_REG28X_RESERVED_Pos)
+
+/* 0x74     0x4000_0074
+    0       R/W     SHORT_PULSE_WKUP                                            1'b0
+    1       R/W     EN_PAD_SYSTEM_ON_WAKEUP                                     1'b0
+    2       R       RESERVED_5                                                  1'b0
+    3       R       WKUP_SHORT_STS_PPU                                          1'b0
+    4       R       WKUP_SHORT_STS_INTR                                         1'b0
+    5       R       WKUP_SHORT_STS_RAP                                          1'b0
+    6       R/W1C   GPIO_INTR_PORT                                              1'b0
+    7       R       WKUP_SHORT_STS_WKIE                                         1'b0
+    13:8    R       RESERVED_4                                                  6'b0
+    14      R       RESERVED_3                                                  1'b0
+    15      R       RESERVED_2                                                  1'b1
+    19:16   R       WAKEUP_GROUP_INT_EN                                         4'hF
+    20      R/W     WKUP_INT_EN                                                 1'b0
+    21      R/W     GPIO_PORT_INT_EN                                            1'b0
+    23:22   R       RESERVED_1                                                  2'h0
+    24      R/W     DUMMY74_B24                                                 1'b1
+    28:25   R       RESERVED                                                    4'h0
+    31:29   R/W     AON_DBG_PCK600_SEL                                          3'b00
+ */
+typedef union _AON_REG_SYSTEM_REG29X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t SHORT_PULSE_WKUP: 1;
+        uint32_t EN_PAD_SYSTEM_ON_WAKEUP: 1;
+        uint32_t RESERVED_5: 1;
+        uint32_t WKUP_SHORT_STS_PPU: 1;
+        uint32_t WKUP_SHORT_STS_INTR: 1;
+        uint32_t WKUP_SHORT_STS_RAP: 1;
+        uint32_t GPIO_INTR_PORT: 1;
+        uint32_t WKUP_SHORT_STS_WKIE: 1;
+        uint32_t RESERVED_4: 6;
+        uint32_t RESERVED_3: 1;
+        uint32_t RESERVED_2: 1;
+        uint32_t WAKEUP_GROUP_INT_EN: 4;
+        uint32_t WKUP_INT_EN: 1;
+        uint32_t GPIO_PORT_INT_EN: 1;
+        uint32_t RESERVED_1: 2;
+        uint32_t DUMMY74_B24: 1;
+        uint32_t RESERVED: 4;
+        uint32_t AON_DBG_PCK600_SEL: 3;
+    };
+} AON_REG_SYSTEM_REG29X_TYPE;
+
+/*0x4000_0074 AON_REG_SYSTEM_REG29X*/
+#define AON_REG_SYSTEM_REG29X_SHORT_PULSE_WKUP_Pos                                                                       0U
+#define AON_REG_SYSTEM_REG29X_SHORT_PULSE_WKUP_Msk                                                                       (0x1UL << AON_REG_SYSTEM_REG29X_SHORT_PULSE_WKUP_Pos)
+
+#define AON_REG_SYSTEM_REG29X_EN_PAD_SYSTEM_ON_WAKEUP_Pos                                                                1U
+#define AON_REG_SYSTEM_REG29X_EN_PAD_SYSTEM_ON_WAKEUP_Msk                                                                (0x1UL << AON_REG_SYSTEM_REG29X_EN_PAD_SYSTEM_ON_WAKEUP_Pos)
+
+#define AON_REG_SYSTEM_REG29X_RESERVED_5_Pos                                                                             2U
+#define AON_REG_SYSTEM_REG29X_RESERVED_5_Msk                                                                             (0x1UL << AON_REG_SYSTEM_REG29X_RESERVED_5_Pos)
+
+#define AON_REG_SYSTEM_REG29X_WKUP_SHORT_STS_PPU_Pos                                                                     3U
+#define AON_REG_SYSTEM_REG29X_WKUP_SHORT_STS_PPU_Msk                                                                     (0x1UL << AON_REG_SYSTEM_REG29X_WKUP_SHORT_STS_PPU_Pos)
+
+#define AON_REG_SYSTEM_REG29X_WKUP_SHORT_STS_INTR_Pos                                                                    4U
+#define AON_REG_SYSTEM_REG29X_WKUP_SHORT_STS_INTR_Msk                                                                    (0x1UL << AON_REG_SYSTEM_REG29X_WKUP_SHORT_STS_INTR_Pos)
+
+#define AON_REG_SYSTEM_REG29X_WKUP_SHORT_STS_RAP_Pos                                                                     5U
+#define AON_REG_SYSTEM_REG29X_WKUP_SHORT_STS_RAP_Msk                                                                     (0x1UL << AON_REG_SYSTEM_REG29X_WKUP_SHORT_STS_RAP_Pos)
+
+#define AON_REG_SYSTEM_REG29X_GPIO_INTR_PORT_Pos                                                                         6U
+#define AON_REG_SYSTEM_REG29X_GPIO_INTR_PORT_Msk                                                                         (0x1UL << AON_REG_SYSTEM_REG29X_GPIO_INTR_PORT_Pos)
+
+#define AON_REG_SYSTEM_REG29X_WKUP_SHORT_STS_WKIE_Pos                                                                    7U
+#define AON_REG_SYSTEM_REG29X_WKUP_SHORT_STS_WKIE_Msk                                                                    (0x1UL << AON_REG_SYSTEM_REG29X_WKUP_SHORT_STS_WKIE_Pos)
+
+#define AON_REG_SYSTEM_REG29X_RESERVED_4_Pos                                                                             8U
+#define AON_REG_SYSTEM_REG29X_RESERVED_4_Msk                                                                             (0x3FUL << AON_REG_SYSTEM_REG29X_RESERVED_4_Pos)
+
+#define AON_REG_SYSTEM_REG29X_RESERVED_3_Pos                                                                             14U
+#define AON_REG_SYSTEM_REG29X_RESERVED_3_Msk                                                                             (0x1UL << AON_REG_SYSTEM_REG29X_RESERVED_3_Pos)
+
+#define AON_REG_SYSTEM_REG29X_RESERVED_2_Pos                                                                             15U
+#define AON_REG_SYSTEM_REG29X_RESERVED_2_Msk                                                                             (0x1UL << AON_REG_SYSTEM_REG29X_RESERVED_2_Pos)
+
+#define AON_REG_SYSTEM_REG29X_WAKEUP_GROUP_INT_EN_Pos                                                                    16U
+#define AON_REG_SYSTEM_REG29X_WAKEUP_GROUP_INT_EN_Msk                                                                    (0xFUL << AON_REG_SYSTEM_REG29X_WAKEUP_GROUP_INT_EN_Pos)
+
+#define AON_REG_SYSTEM_REG29X_WKUP_INT_EN_Pos                                                                            20U
+#define AON_REG_SYSTEM_REG29X_WKUP_INT_EN_Msk                                                                            (0x1UL << AON_REG_SYSTEM_REG29X_WKUP_INT_EN_Pos)
+
+#define AON_REG_SYSTEM_REG29X_GPIO_PORT_INT_EN_Pos                                                                       21U
+#define AON_REG_SYSTEM_REG29X_GPIO_PORT_INT_EN_Msk                                                                       (0x1UL << AON_REG_SYSTEM_REG29X_GPIO_PORT_INT_EN_Pos)
+
+#define AON_REG_SYSTEM_REG29X_RESERVED_1_Pos                                                                             22U
+#define AON_REG_SYSTEM_REG29X_RESERVED_1_Msk                                                                             (0x3UL << AON_REG_SYSTEM_REG29X_RESERVED_1_Pos)
+
+#define AON_REG_SYSTEM_REG29X_DUMMY74_B24_Pos                                                                            24U
+#define AON_REG_SYSTEM_REG29X_DUMMY74_B24_Msk                                                                            (0x1UL << AON_REG_SYSTEM_REG29X_DUMMY74_B24_Pos)
+
+#define AON_REG_SYSTEM_REG29X_RESERVED_Pos                                                                               25U
+#define AON_REG_SYSTEM_REG29X_RESERVED_Msk                                                                               (0xFUL << AON_REG_SYSTEM_REG29X_RESERVED_Pos)
+
+#define AON_REG_SYSTEM_REG29X_AON_DBG_PCK600_SEL_Pos                                                                     29U
+#define AON_REG_SYSTEM_REG29X_AON_DBG_PCK600_SEL_Msk                                                                     (0x7UL << AON_REG_SYSTEM_REG29X_AON_DBG_PCK600_SEL_Pos)
+
+/* 0x78     0x4000_0078
+    0       R/W     MODEM_AUTO_BUS_SW_EN                                        1'b0
+    5:1     R/W     RESERVED_1                                                  5'h0
+    6       R/W     SRAM_AMU_SETTING_SEL                                        1'b0
+    12:7    R/W     EXTRA_DELAY_XTAL40                                          6'b000000
+    20:13   R/W     EXTRA_DELAY_OSC128                                          8'b00000000
+    21      R/W     SRAM_SETTING_SEL                                            1'b0
+    22      R/W     LATCH_WKUP_REASON                                           1'b0
+    23      R/W     EN_ENTER_SHIP_MODE                                          1'b0
+    24      R/W     SCHEDULE_PLAN_INPUT_CLK_SW                                  1'b0
+    25      R/W     WAIT_PAD_AUTO_SW_RET_DONE                                   1'b0
+    26      R       PAD_AUTO_SW_RET_DONE                                        1'b0
+    27      R/W     PAD_AUTO_SW_EN_RET                                          1'b0
+    28      R/W     WAIT_PAD_AUTO_SW_PD_RET_DONE                                1'b0
+    29      R       PAD_AUTO_SW_PD_RET_DONE                                     1'b0
+    30      R/W     PAD_AUTO_SW_PD_EN_RET                                       1'b0
+    31      R/W     RESERVED                                                    1'b0
+ */
+typedef union _AON_REG_SYSTEM_REG30X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t MODEM_AUTO_BUS_SW_EN: 1;
+        uint32_t RESERVED_1: 5;
+        uint32_t SRAM_AMU_SETTING_SEL: 1;
+        uint32_t EXTRA_DELAY_XTAL40: 6;
+        uint32_t EXTRA_DELAY_OSC128: 8;
+        uint32_t SRAM_SETTING_SEL: 1;
+        uint32_t LATCH_WKUP_REASON: 1;
+        uint32_t EN_ENTER_SHIP_MODE: 1;
+        uint32_t SCHEDULE_PLAN_INPUT_CLK_SW: 1;
+        uint32_t WAIT_PAD_AUTO_SW_RET_DONE: 1;
+        uint32_t PAD_AUTO_SW_RET_DONE: 1;
+        uint32_t PAD_AUTO_SW_EN_RET: 1;
+        uint32_t WAIT_PAD_AUTO_SW_PD_RET_DONE: 1;
+        uint32_t PAD_AUTO_SW_PD_RET_DONE: 1;
+        uint32_t PAD_AUTO_SW_PD_EN_RET: 1;
+        uint32_t RESERVED: 1;
+    };
+} AON_REG_SYSTEM_REG30X_TYPE;
+
+/*0x4000_0078 AON_REG_SYSTEM_REG30X*/
+#define AON_REG_SYSTEM_REG30X_MODEM_AUTO_BUS_SW_EN_Pos                                                                   0U
+#define AON_REG_SYSTEM_REG30X_MODEM_AUTO_BUS_SW_EN_Msk                                                                   (0x1UL << AON_REG_SYSTEM_REG30X_MODEM_AUTO_BUS_SW_EN_Pos)
+
+#define AON_REG_SYSTEM_REG30X_RESERVED_1_Pos                                                                             1U
+#define AON_REG_SYSTEM_REG30X_RESERVED_1_Msk                                                                             (0x1FUL << AON_REG_SYSTEM_REG30X_RESERVED_1_Pos)
+
+#define AON_REG_SYSTEM_REG30X_SRAM_AMU_SETTING_SEL_Pos                                                                   6U
+#define AON_REG_SYSTEM_REG30X_SRAM_AMU_SETTING_SEL_Msk                                                                   (0x1UL << AON_REG_SYSTEM_REG30X_SRAM_AMU_SETTING_SEL_Pos)
+
+#define AON_REG_SYSTEM_REG30X_EXTRA_DELAY_XTAL40_Pos                                                                     7U
+#define AON_REG_SYSTEM_REG30X_EXTRA_DELAY_XTAL40_Msk                                                                     (0x3FUL << AON_REG_SYSTEM_REG30X_EXTRA_DELAY_XTAL40_Pos)
+
+#define AON_REG_SYSTEM_REG30X_EXTRA_DELAY_OSC128_Pos                                                                     13U
+#define AON_REG_SYSTEM_REG30X_EXTRA_DELAY_OSC128_Msk                                                                     (0xFFUL << AON_REG_SYSTEM_REG30X_EXTRA_DELAY_OSC128_Pos)
+
+#define AON_REG_SYSTEM_REG30X_SRAM_SETTING_SEL_Pos                                                                       21U
+#define AON_REG_SYSTEM_REG30X_SRAM_SETTING_SEL_Msk                                                                       (0x1UL << AON_REG_SYSTEM_REG30X_SRAM_SETTING_SEL_Pos)
+
+#define AON_REG_SYSTEM_REG30X_LATCH_WKUP_REASON_Pos                                                                      22U
+#define AON_REG_SYSTEM_REG30X_LATCH_WKUP_REASON_Msk                                                                      (0x1UL << AON_REG_SYSTEM_REG30X_LATCH_WKUP_REASON_Pos)
+
+#define AON_REG_SYSTEM_REG30X_EN_ENTER_SHIP_MODE_Pos                                                                     23U
+#define AON_REG_SYSTEM_REG30X_EN_ENTER_SHIP_MODE_Msk                                                                     (0x1UL << AON_REG_SYSTEM_REG30X_EN_ENTER_SHIP_MODE_Pos)
+
+#define AON_REG_SYSTEM_REG30X_SCHEDULE_PLAN_INPUT_CLK_SW_Pos                                                             24U
+#define AON_REG_SYSTEM_REG30X_SCHEDULE_PLAN_INPUT_CLK_SW_Msk                                                             (0x1UL << AON_REG_SYSTEM_REG30X_SCHEDULE_PLAN_INPUT_CLK_SW_Pos)
+
+#define AON_REG_SYSTEM_REG30X_WAIT_PAD_AUTO_SW_RET_DONE_Pos                                                              25U
+#define AON_REG_SYSTEM_REG30X_WAIT_PAD_AUTO_SW_RET_DONE_Msk                                                              (0x1UL << AON_REG_SYSTEM_REG30X_WAIT_PAD_AUTO_SW_RET_DONE_Pos)
+
+#define AON_REG_SYSTEM_REG30X_PAD_AUTO_SW_RET_DONE_Pos                                                                   26U
+#define AON_REG_SYSTEM_REG30X_PAD_AUTO_SW_RET_DONE_Msk                                                                   (0x1UL << AON_REG_SYSTEM_REG30X_PAD_AUTO_SW_RET_DONE_Pos)
+
+#define AON_REG_SYSTEM_REG30X_PAD_AUTO_SW_EN_RET_Pos                                                                     27U
+#define AON_REG_SYSTEM_REG30X_PAD_AUTO_SW_EN_RET_Msk                                                                     (0x1UL << AON_REG_SYSTEM_REG30X_PAD_AUTO_SW_EN_RET_Pos)
+
+#define AON_REG_SYSTEM_REG30X_WAIT_PAD_AUTO_SW_PD_RET_DONE_Pos                                                           28U
+#define AON_REG_SYSTEM_REG30X_WAIT_PAD_AUTO_SW_PD_RET_DONE_Msk                                                           (0x1UL << AON_REG_SYSTEM_REG30X_WAIT_PAD_AUTO_SW_PD_RET_DONE_Pos)
+
+#define AON_REG_SYSTEM_REG30X_PAD_AUTO_SW_PD_RET_DONE_Pos                                                                29U
+#define AON_REG_SYSTEM_REG30X_PAD_AUTO_SW_PD_RET_DONE_Msk                                                                (0x1UL << AON_REG_SYSTEM_REG30X_PAD_AUTO_SW_PD_RET_DONE_Pos)
+
+#define AON_REG_SYSTEM_REG30X_PAD_AUTO_SW_PD_EN_RET_Pos                                                                  30U
+#define AON_REG_SYSTEM_REG30X_PAD_AUTO_SW_PD_EN_RET_Msk                                                                  (0x1UL << AON_REG_SYSTEM_REG30X_PAD_AUTO_SW_PD_EN_RET_Pos)
+
+#define AON_REG_SYSTEM_REG30X_RESERVED_Pos                                                                               31U
+#define AON_REG_SYSTEM_REG30X_RESERVED_Msk                                                                               (0x1UL << AON_REG_SYSTEM_REG30X_RESERVED_Pos)
+
+/* 0x7C     0x4000_007c
+    0       R/W     RFPD_MANUAL_ENABLE                                          1'b0
+    1       R/W     RFPD_MANUAL_VALUE                                           1'b0
+    3:2     R/W     RESERVED_1                                                  2'h0
+    4       R/W     PA_LNA_DEBUG_MODE_EN                                        1'b0
+    31:5    R/W     RESERVED                                                    27'b0
+ */
+typedef union _AON_REG_SYSTEM_REG31X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RFPD_MANUAL_ENABLE: 1;
+        uint32_t RFPD_MANUAL_VALUE: 1;
+        uint32_t RESERVED_1: 2;
+        uint32_t PA_LNA_DEBUG_MODE_EN: 1;
+        uint32_t RESERVED: 27;
+    };
+} AON_REG_SYSTEM_REG31X_TYPE;
+
+/*0x4000_007c AON_REG_SYSTEM_REG31X*/
+#define AON_REG_SYSTEM_REG31X_RFPD_MANUAL_ENABLE_Pos                                                                     0U
+#define AON_REG_SYSTEM_REG31X_RFPD_MANUAL_ENABLE_Msk                                                                     (0x1UL << AON_REG_SYSTEM_REG31X_RFPD_MANUAL_ENABLE_Pos)
+
+#define AON_REG_SYSTEM_REG31X_RFPD_MANUAL_VALUE_Pos                                                                      1U
+#define AON_REG_SYSTEM_REG31X_RFPD_MANUAL_VALUE_Msk                                                                      (0x1UL << AON_REG_SYSTEM_REG31X_RFPD_MANUAL_VALUE_Pos)
+
+#define AON_REG_SYSTEM_REG31X_RESERVED_1_Pos                                                                             2U
+#define AON_REG_SYSTEM_REG31X_RESERVED_1_Msk                                                                             (0x3UL << AON_REG_SYSTEM_REG31X_RESERVED_1_Pos)
+
+#define AON_REG_SYSTEM_REG31X_PA_LNA_DEBUG_MODE_EN_Pos                                                                   4U
+#define AON_REG_SYSTEM_REG31X_PA_LNA_DEBUG_MODE_EN_Msk                                                                   (0x1UL << AON_REG_SYSTEM_REG31X_PA_LNA_DEBUG_MODE_EN_Pos)
+
+#define AON_REG_SYSTEM_REG31X_RESERVED_Pos                                                                               5U
+#define AON_REG_SYSTEM_REG31X_RESERVED_Msk                                                                               (0x7FFFFFFUL << AON_REG_SYSTEM_REG31X_RESERVED_Pos)
+
+/* 0x80     0x4000_0080
+    0       R/W     RESERVED                                                    1'b0
+    1       R/W     AMU_LITE2_START_PON_DVFS_AMU_PPU_VPON                       1'b0
+    2       R       AMU_LITE0_APB_CTRL_SEL                                      1'b0
+    3       R       AMU_LITE1_APB_CTRL_SEL                                      1'b0
+    4       R       AMU_LITE2_APB_CTRL_SEL                                      1'b0
+    5       R/W     AMU_LITE0_APB_CTRL_SEL_REQ_OSC80                            1'b0
+    6       R/W     AMU_LITE1_APB_CTRL_SEL_REQ_XTAL40                           1'b0
+    7       R/W     AMU_LITE2_APB_CTRL_SEL_REQ_OCS10                            1'b0
+    8       R       AMU_LITE0_AMU_DONE_OSC80_CG                                 1'b0
+    9       R       AMU_LITE0_AMU_DONE_OSC80                                    1'b0
+    10      R/W     AMU_LITE0_START_PON_AMU_OSC80_CG                            1'b0
+    11      R/W     AMU_LITE0_START_POF_AMU_OSC80_CG                            1'b0
+    12      R/W     AMU_LITE0_START_PON_AMU_OSC80                               1'b0
+    13      R/W     AMU_LITE0_START_POF_AMU_OSC80                               1'b0
+    14      R       AMU_LITE1_AMU_DONE_PLL1                                     1'b0
+    15      R       AMU_LITE1_AMU_DONE_XTAL40                                   1'b0
+    16      R/W     AMU_LITE1_START_PON_AMU_PLL1                                1'b0
+    17      R/W     AMU_LITE1_START_POF_AMU_PLL1                                1'b0
+    18      R/W     AMU_LITE1_START_PON_AMU_XTAL40                              1'b0
+    19      R/W     AMU_LITE1_START_POF_AMU_XTAL40                              1'b0
+    20      R       AMU_LITE2_AMU_DONE_CORE_OP1                                 1'b0
+    21      R       AMU_LITE2_AMU_DONE_PPU_VCORE1                               1'b0
+    22      R       AMU_LITE2_AMU_DONE_PPU_VPON                                 1'b0
+    23      R       AMU_LITE2_AMU_DONE_OSC10                                    1'b0
+    24      R/W     AMU_LITE2_START_PON_AMU_CORE_OP1                            1'b0
+    25      R/W     AMU_LITE2_START_POF_AMU_CORE_OP1                            1'b0
+    26      R/W     AMU_LITE2_START_PON_AMU_PPU_VCORE1                          1'b0
+    27      R/W     AMU_LITE2_START_POF_AMU_PPU_VCORE1                          1'b0
+    28      R/W     AMU_LITE2_START_PON_AMU_PPU_VPON                            1'b0
+    29      R/W     AMU_LITE2_START_POF_AMU_PPU_VPON                            1'b0
+    30      R/W     AMU_LITE2_START_PON_AMU_OSC10                               1'b0
+    31      R/W     AMU_LITE2_START_POF_AMU_OSC10                               1'b0
+ */
+typedef union _AON_REG_SYSTEM_REG32X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED: 1;
+        uint32_t AMU_LITE2_START_PON_DVFS_AMU_PPU_VPON: 1;
+        uint32_t AMU_LITE0_APB_CTRL_SEL: 1;
+        uint32_t AMU_LITE1_APB_CTRL_SEL: 1;
+        uint32_t AMU_LITE2_APB_CTRL_SEL: 1;
+        uint32_t AMU_LITE0_APB_CTRL_SEL_REQ_OSC80: 1;
+        uint32_t AMU_LITE1_APB_CTRL_SEL_REQ_XTAL40: 1;
+        uint32_t AMU_LITE2_APB_CTRL_SEL_REQ_OCS10: 1;
+        uint32_t AMU_LITE0_AMU_DONE_OSC80_CG: 1;
+        uint32_t AMU_LITE0_AMU_DONE_OSC80: 1;
+        uint32_t AMU_LITE0_START_PON_AMU_OSC80_CG: 1;
+        uint32_t AMU_LITE0_START_POF_AMU_OSC80_CG: 1;
+        uint32_t AMU_LITE0_START_PON_AMU_OSC80: 1;
+        uint32_t AMU_LITE0_START_POF_AMU_OSC80: 1;
+        uint32_t AMU_LITE1_AMU_DONE_PLL1: 1;
+        uint32_t AMU_LITE1_AMU_DONE_XTAL40: 1;
+        uint32_t AMU_LITE1_START_PON_AMU_PLL1: 1;
+        uint32_t AMU_LITE1_START_POF_AMU_PLL1: 1;
+        uint32_t AMU_LITE1_START_PON_AMU_XTAL40: 1;
+        uint32_t AMU_LITE1_START_POF_AMU_XTAL40: 1;
+        uint32_t AMU_LITE2_AMU_DONE_CORE_OP1: 1;
+        uint32_t AMU_LITE2_AMU_DONE_PPU_VCORE1: 1;
+        uint32_t AMU_LITE2_AMU_DONE_PPU_VPON: 1;
+        uint32_t AMU_LITE2_AMU_DONE_OSC10: 1;
+        uint32_t AMU_LITE2_START_PON_AMU_CORE_OP1: 1;
+        uint32_t AMU_LITE2_START_POF_AMU_CORE_OP1: 1;
+        uint32_t AMU_LITE2_START_PON_AMU_PPU_VCORE1: 1;
+        uint32_t AMU_LITE2_START_POF_AMU_PPU_VCORE1: 1;
+        uint32_t AMU_LITE2_START_PON_AMU_PPU_VPON: 1;
+        uint32_t AMU_LITE2_START_POF_AMU_PPU_VPON: 1;
+        uint32_t AMU_LITE2_START_PON_AMU_OSC10: 1;
+        uint32_t AMU_LITE2_START_POF_AMU_OSC10: 1;
+    };
+} AON_REG_SYSTEM_REG32X_TYPE;
+
+/*0x4000_0080 AON_REG_SYSTEM_REG32X*/
+#define AON_REG_SYSTEM_REG32X_RESERVED_Pos                                                                               0U
+#define AON_REG_SYSTEM_REG32X_RESERVED_Msk                                                                               (0x1UL << AON_REG_SYSTEM_REG32X_RESERVED_Pos)
+
+#define AON_REG_SYSTEM_REG32X_AMU_LITE2_START_PON_DVFS_AMU_PPU_VPON_Pos                                                  1U
+#define AON_REG_SYSTEM_REG32X_AMU_LITE2_START_PON_DVFS_AMU_PPU_VPON_Msk                                                  (0x1UL << AON_REG_SYSTEM_REG32X_AMU_LITE2_START_PON_DVFS_AMU_PPU_VPON_Pos)
+
+#define AON_REG_SYSTEM_REG32X_AMU_LITE0_APB_CTRL_SEL_Pos                                                                 2U
+#define AON_REG_SYSTEM_REG32X_AMU_LITE0_APB_CTRL_SEL_Msk                                                                 (0x1UL << AON_REG_SYSTEM_REG32X_AMU_LITE0_APB_CTRL_SEL_Pos)
+
+#define AON_REG_SYSTEM_REG32X_AMU_LITE1_APB_CTRL_SEL_Pos                                                                 3U
+#define AON_REG_SYSTEM_REG32X_AMU_LITE1_APB_CTRL_SEL_Msk                                                                 (0x1UL << AON_REG_SYSTEM_REG32X_AMU_LITE1_APB_CTRL_SEL_Pos)
+
+#define AON_REG_SYSTEM_REG32X_AMU_LITE2_APB_CTRL_SEL_Pos                                                                 4U
+#define AON_REG_SYSTEM_REG32X_AMU_LITE2_APB_CTRL_SEL_Msk                                                                 (0x1UL << AON_REG_SYSTEM_REG32X_AMU_LITE2_APB_CTRL_SEL_Pos)
+
+#define AON_REG_SYSTEM_REG32X_AMU_LITE0_APB_CTRL_SEL_REQ_OSC80_Pos                                                       5U
+#define AON_REG_SYSTEM_REG32X_AMU_LITE0_APB_CTRL_SEL_REQ_OSC80_Msk                                                       (0x1UL << AON_REG_SYSTEM_REG32X_AMU_LITE0_APB_CTRL_SEL_REQ_OSC80_Pos)
+
+#define AON_REG_SYSTEM_REG32X_AMU_LITE1_APB_CTRL_SEL_REQ_XTAL40_Pos                                                      6U
+#define AON_REG_SYSTEM_REG32X_AMU_LITE1_APB_CTRL_SEL_REQ_XTAL40_Msk                                                      (0x1UL << AON_REG_SYSTEM_REG32X_AMU_LITE1_APB_CTRL_SEL_REQ_XTAL40_Pos)
+
+#define AON_REG_SYSTEM_REG32X_AMU_LITE2_APB_CTRL_SEL_REQ_OCS10_Pos                                                       7U
+#define AON_REG_SYSTEM_REG32X_AMU_LITE2_APB_CTRL_SEL_REQ_OCS10_Msk                                                       (0x1UL << AON_REG_SYSTEM_REG32X_AMU_LITE2_APB_CTRL_SEL_REQ_OCS10_Pos)
+
+#define AON_REG_SYSTEM_REG32X_AMU_LITE0_AMU_DONE_OSC80_CG_Pos                                                            8U
+#define AON_REG_SYSTEM_REG32X_AMU_LITE0_AMU_DONE_OSC80_CG_Msk                                                            (0x1UL << AON_REG_SYSTEM_REG32X_AMU_LITE0_AMU_DONE_OSC80_CG_Pos)
+
+#define AON_REG_SYSTEM_REG32X_AMU_LITE0_AMU_DONE_OSC80_Pos                                                               9U
+#define AON_REG_SYSTEM_REG32X_AMU_LITE0_AMU_DONE_OSC80_Msk                                                               (0x1UL << AON_REG_SYSTEM_REG32X_AMU_LITE0_AMU_DONE_OSC80_Pos)
+
+#define AON_REG_SYSTEM_REG32X_AMU_LITE0_START_PON_AMU_OSC80_CG_Pos                                                       10U
+#define AON_REG_SYSTEM_REG32X_AMU_LITE0_START_PON_AMU_OSC80_CG_Msk                                                       (0x1UL << AON_REG_SYSTEM_REG32X_AMU_LITE0_START_PON_AMU_OSC80_CG_Pos)
+
+#define AON_REG_SYSTEM_REG32X_AMU_LITE0_START_POF_AMU_OSC80_CG_Pos                                                       11U
+#define AON_REG_SYSTEM_REG32X_AMU_LITE0_START_POF_AMU_OSC80_CG_Msk                                                       (0x1UL << AON_REG_SYSTEM_REG32X_AMU_LITE0_START_POF_AMU_OSC80_CG_Pos)
+
+#define AON_REG_SYSTEM_REG32X_AMU_LITE0_START_PON_AMU_OSC80_Pos                                                          12U
+#define AON_REG_SYSTEM_REG32X_AMU_LITE0_START_PON_AMU_OSC80_Msk                                                          (0x1UL << AON_REG_SYSTEM_REG32X_AMU_LITE0_START_PON_AMU_OSC80_Pos)
+
+#define AON_REG_SYSTEM_REG32X_AMU_LITE0_START_POF_AMU_OSC80_Pos                                                          13U
+#define AON_REG_SYSTEM_REG32X_AMU_LITE0_START_POF_AMU_OSC80_Msk                                                          (0x1UL << AON_REG_SYSTEM_REG32X_AMU_LITE0_START_POF_AMU_OSC80_Pos)
+
+#define AON_REG_SYSTEM_REG32X_AMU_LITE1_AMU_DONE_PLL1_Pos                                                                14U
+#define AON_REG_SYSTEM_REG32X_AMU_LITE1_AMU_DONE_PLL1_Msk                                                                (0x1UL << AON_REG_SYSTEM_REG32X_AMU_LITE1_AMU_DONE_PLL1_Pos)
+
+#define AON_REG_SYSTEM_REG32X_AMU_LITE1_AMU_DONE_XTAL40_Pos                                                              15U
+#define AON_REG_SYSTEM_REG32X_AMU_LITE1_AMU_DONE_XTAL40_Msk                                                              (0x1UL << AON_REG_SYSTEM_REG32X_AMU_LITE1_AMU_DONE_XTAL40_Pos)
+
+#define AON_REG_SYSTEM_REG32X_AMU_LITE1_START_PON_AMU_PLL1_Pos                                                           16U
+#define AON_REG_SYSTEM_REG32X_AMU_LITE1_START_PON_AMU_PLL1_Msk                                                           (0x1UL << AON_REG_SYSTEM_REG32X_AMU_LITE1_START_PON_AMU_PLL1_Pos)
+
+#define AON_REG_SYSTEM_REG32X_AMU_LITE1_START_POF_AMU_PLL1_Pos                                                           17U
+#define AON_REG_SYSTEM_REG32X_AMU_LITE1_START_POF_AMU_PLL1_Msk                                                           (0x1UL << AON_REG_SYSTEM_REG32X_AMU_LITE1_START_POF_AMU_PLL1_Pos)
+
+#define AON_REG_SYSTEM_REG32X_AMU_LITE1_START_PON_AMU_XTAL40_Pos                                                         18U
+#define AON_REG_SYSTEM_REG32X_AMU_LITE1_START_PON_AMU_XTAL40_Msk                                                         (0x1UL << AON_REG_SYSTEM_REG32X_AMU_LITE1_START_PON_AMU_XTAL40_Pos)
+
+#define AON_REG_SYSTEM_REG32X_AMU_LITE1_START_POF_AMU_XTAL40_Pos                                                         19U
+#define AON_REG_SYSTEM_REG32X_AMU_LITE1_START_POF_AMU_XTAL40_Msk                                                         (0x1UL << AON_REG_SYSTEM_REG32X_AMU_LITE1_START_POF_AMU_XTAL40_Pos)
+
+#define AON_REG_SYSTEM_REG32X_AMU_LITE2_AMU_DONE_CORE_OP1_Pos                                                            20U
+#define AON_REG_SYSTEM_REG32X_AMU_LITE2_AMU_DONE_CORE_OP1_Msk                                                            (0x1UL << AON_REG_SYSTEM_REG32X_AMU_LITE2_AMU_DONE_CORE_OP1_Pos)
+
+#define AON_REG_SYSTEM_REG32X_AMU_LITE2_AMU_DONE_PPU_VCORE1_Pos                                                          21U
+#define AON_REG_SYSTEM_REG32X_AMU_LITE2_AMU_DONE_PPU_VCORE1_Msk                                                          (0x1UL << AON_REG_SYSTEM_REG32X_AMU_LITE2_AMU_DONE_PPU_VCORE1_Pos)
+
+#define AON_REG_SYSTEM_REG32X_AMU_LITE2_AMU_DONE_PPU_VPON_Pos                                                            22U
+#define AON_REG_SYSTEM_REG32X_AMU_LITE2_AMU_DONE_PPU_VPON_Msk                                                            (0x1UL << AON_REG_SYSTEM_REG32X_AMU_LITE2_AMU_DONE_PPU_VPON_Pos)
+
+#define AON_REG_SYSTEM_REG32X_AMU_LITE2_AMU_DONE_OSC10_Pos                                                               23U
+#define AON_REG_SYSTEM_REG32X_AMU_LITE2_AMU_DONE_OSC10_Msk                                                               (0x1UL << AON_REG_SYSTEM_REG32X_AMU_LITE2_AMU_DONE_OSC10_Pos)
+
+#define AON_REG_SYSTEM_REG32X_AMU_LITE2_START_PON_AMU_CORE_OP1_Pos                                                       24U
+#define AON_REG_SYSTEM_REG32X_AMU_LITE2_START_PON_AMU_CORE_OP1_Msk                                                       (0x1UL << AON_REG_SYSTEM_REG32X_AMU_LITE2_START_PON_AMU_CORE_OP1_Pos)
+
+#define AON_REG_SYSTEM_REG32X_AMU_LITE2_START_POF_AMU_CORE_OP1_Pos                                                       25U
+#define AON_REG_SYSTEM_REG32X_AMU_LITE2_START_POF_AMU_CORE_OP1_Msk                                                       (0x1UL << AON_REG_SYSTEM_REG32X_AMU_LITE2_START_POF_AMU_CORE_OP1_Pos)
+
+#define AON_REG_SYSTEM_REG32X_AMU_LITE2_START_PON_AMU_PPU_VCORE1_Pos                                                     26U
+#define AON_REG_SYSTEM_REG32X_AMU_LITE2_START_PON_AMU_PPU_VCORE1_Msk                                                     (0x1UL << AON_REG_SYSTEM_REG32X_AMU_LITE2_START_PON_AMU_PPU_VCORE1_Pos)
+
+#define AON_REG_SYSTEM_REG32X_AMU_LITE2_START_POF_AMU_PPU_VCORE1_Pos                                                     27U
+#define AON_REG_SYSTEM_REG32X_AMU_LITE2_START_POF_AMU_PPU_VCORE1_Msk                                                     (0x1UL << AON_REG_SYSTEM_REG32X_AMU_LITE2_START_POF_AMU_PPU_VCORE1_Pos)
+
+#define AON_REG_SYSTEM_REG32X_AMU_LITE2_START_PON_AMU_PPU_VPON_Pos                                                       28U
+#define AON_REG_SYSTEM_REG32X_AMU_LITE2_START_PON_AMU_PPU_VPON_Msk                                                       (0x1UL << AON_REG_SYSTEM_REG32X_AMU_LITE2_START_PON_AMU_PPU_VPON_Pos)
+
+#define AON_REG_SYSTEM_REG32X_AMU_LITE2_START_POF_AMU_PPU_VPON_Pos                                                       29U
+#define AON_REG_SYSTEM_REG32X_AMU_LITE2_START_POF_AMU_PPU_VPON_Msk                                                       (0x1UL << AON_REG_SYSTEM_REG32X_AMU_LITE2_START_POF_AMU_PPU_VPON_Pos)
+
+#define AON_REG_SYSTEM_REG32X_AMU_LITE2_START_PON_AMU_OSC10_Pos                                                          30U
+#define AON_REG_SYSTEM_REG32X_AMU_LITE2_START_PON_AMU_OSC10_Msk                                                          (0x1UL << AON_REG_SYSTEM_REG32X_AMU_LITE2_START_PON_AMU_OSC10_Pos)
+
+#define AON_REG_SYSTEM_REG32X_AMU_LITE2_START_POF_AMU_OSC10_Pos                                                          31U
+#define AON_REG_SYSTEM_REG32X_AMU_LITE2_START_POF_AMU_OSC10_Msk                                                          (0x1UL << AON_REG_SYSTEM_REG32X_AMU_LITE2_START_POF_AMU_OSC10_Pos)
+
+/* 0x84     0x4000_0084
+    1:0     R/W     RESERVED                                                    2'b0
+    2       R/W     AMU_LITE2_ENABLE_POF_AMU_PPU_VCORE1_FUNC_RET                1'b0
+    3       R/W     AMU_LITE2_ENABLE_POF_AMU_PPU_VCORE1_FULL_RET                1'b0
+    4       R/W     AMU_LITE2_ENABLE_PON_AMU_PPU_VPON_LV                        1'b0
+    5       R/W     AMU_LITE2_ENABLE_PON_AMU_PPU_VPON_HV                        1'b0
+    6       R/W     AMU_LITE2_ENABLE_POF_AMU_PPU_VPON_FUNC_RET                  1'b0
+    7       R/W     AMU_LITE2_ENABLE_POF_AMU_PPU_VPON_MEM_OFF                   1'b0
+    8       R/W     AMU_LITE0_APB_CTRL_SEL_REQ_OSC80_CG                         1'b0
+    9       R/W     AMU_LITE1_APB_CTRL_SEL_REQ_PLL                              1'b0
+    10      R/W     AMU_LITE2_APB_CTRL_SEL_REQ_VCORE_OP1                        1'b0
+    11      R/W     AMU_LITE2_APB_CTRL_SEL_REQ_VCORE_PPU                        1'b0
+    12      R/W     AMU_LITE2_APB_CTRL_SEL_REQ_VPON_PPU                         1'b0
+    13      R/W     AMU_LITE0_ENABLE_PON_AMU_OSC80_CG                           1'b0
+    14      R/W     AMU_LITE0_ENABLE_POF_AMU_OSC80_CG                           1'b0
+    15      R/W     AMU_LITE0_ENABLE_PON_AMU_OSC80                              1'b0
+    16      R/W     AMU_LITE0_ENABLE_POF_AMU_OSC80                              1'b0
+    17      R/W     AMU_LITE1_ENABLE_PON_AMU_PLL1                               1'b0
+    18      R/W     AMU_LITE1_ENABLE_POF_AMU_PLL1                               1'b0
+    19      R/W     AMU_LITE1_ENABLE_PON_AMU_XTAL40                             1'b0
+    20      R/W     AMU_LITE1_ENABLE_POF_AMU_XTAL40                             1'b0
+    21      R/W     AMU_LITE2_ENABLE_PON_AMU_CORE_OP1                           1'b0
+    22      R/W     AMU_LITE2_ENABLE_POF_AMU_CORE_OP1                           1'b0
+    23      R/W     AMU_LITE2_ENABLE_PON_AMU_PPU_VCORE1                         1'b0
+    24      R/W     AMU_LITE2_ENABLE_POF_AMU_PPU_VCORE1_OFF                     1'b0
+    25      R/W     AMU_LITE2_ENABLE_PON_AMU_PPU_VPON                           1'b0
+    26      R/W     AMU_LITE2_ENABLE_POF_AMU_PPU_VPON_OFF                       1'b0
+    27      R/W     AMU_LITE2_ENABLE_PON_AMU_OSC10                              1'b0
+    28      R/W     AMU_LITE2_ENABLE_POF_AMU_OSC10                              1'b0
+    29      R/W     R_AON_FEN_AMU_LITE2                                         1'b1
+    30      R/W     R_AON_FEN_AMU_LITE1                                         1'b1
+    31      R/W     R_AON_FEN_AMU_LITE0                                         1'b1
+ */
+typedef union _AON_REG_SYSTEM_REG33X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED: 2;
+        uint32_t AMU_LITE2_ENABLE_POF_AMU_PPU_VCORE1_FUNC_RET: 1;
+        uint32_t AMU_LITE2_ENABLE_POF_AMU_PPU_VCORE1_FULL_RET: 1;
+        uint32_t AMU_LITE2_ENABLE_PON_AMU_PPU_VPON_LV: 1;
+        uint32_t AMU_LITE2_ENABLE_PON_AMU_PPU_VPON_HV: 1;
+        uint32_t AMU_LITE2_ENABLE_POF_AMU_PPU_VPON_FUNC_RET: 1;
+        uint32_t AMU_LITE2_ENABLE_POF_AMU_PPU_VPON_MEM_OFF: 1;
+        uint32_t AMU_LITE0_APB_CTRL_SEL_REQ_OSC80_CG: 1;
+        uint32_t AMU_LITE1_APB_CTRL_SEL_REQ_PLL: 1;
+        uint32_t AMU_LITE2_APB_CTRL_SEL_REQ_VCORE_OP1: 1;
+        uint32_t AMU_LITE2_APB_CTRL_SEL_REQ_VCORE_PPU: 1;
+        uint32_t AMU_LITE2_APB_CTRL_SEL_REQ_VPON_PPU: 1;
+        uint32_t AMU_LITE0_ENABLE_PON_AMU_OSC80_CG: 1;
+        uint32_t AMU_LITE0_ENABLE_POF_AMU_OSC80_CG: 1;
+        uint32_t AMU_LITE0_ENABLE_PON_AMU_OSC80: 1;
+        uint32_t AMU_LITE0_ENABLE_POF_AMU_OSC80: 1;
+        uint32_t AMU_LITE1_ENABLE_PON_AMU_PLL1: 1;
+        uint32_t AMU_LITE1_ENABLE_POF_AMU_PLL1: 1;
+        uint32_t AMU_LITE1_ENABLE_PON_AMU_XTAL40: 1;
+        uint32_t AMU_LITE1_ENABLE_POF_AMU_XTAL40: 1;
+        uint32_t AMU_LITE2_ENABLE_PON_AMU_CORE_OP1: 1;
+        uint32_t AMU_LITE2_ENABLE_POF_AMU_CORE_OP1: 1;
+        uint32_t AMU_LITE2_ENABLE_PON_AMU_PPU_VCORE1: 1;
+        uint32_t AMU_LITE2_ENABLE_POF_AMU_PPU_VCORE1_OFF: 1;
+        uint32_t AMU_LITE2_ENABLE_PON_AMU_PPU_VPON: 1;
+        uint32_t AMU_LITE2_ENABLE_POF_AMU_PPU_VPON_OFF: 1;
+        uint32_t AMU_LITE2_ENABLE_PON_AMU_OSC10: 1;
+        uint32_t AMU_LITE2_ENABLE_POF_AMU_OSC10: 1;
+        uint32_t R_AON_FEN_AMU_LITE2: 1;
+        uint32_t R_AON_FEN_AMU_LITE1: 1;
+        uint32_t R_AON_FEN_AMU_LITE0: 1;
+    };
+} AON_REG_SYSTEM_REG33X_TYPE;
+
+/*0x4000_0084 AON_REG_SYSTEM_REG33X*/
+#define AON_REG_SYSTEM_REG33X_RESERVED_Pos                                                                               0U
+#define AON_REG_SYSTEM_REG33X_RESERVED_Msk                                                                               (0x3UL << AON_REG_SYSTEM_REG33X_RESERVED_Pos)
+
+#define AON_REG_SYSTEM_REG33X_AMU_LITE2_ENABLE_POF_AMU_PPU_VCORE1_FUNC_RET_Pos                                           2U
+#define AON_REG_SYSTEM_REG33X_AMU_LITE2_ENABLE_POF_AMU_PPU_VCORE1_FUNC_RET_Msk                                           (0x1UL << AON_REG_SYSTEM_REG33X_AMU_LITE2_ENABLE_POF_AMU_PPU_VCORE1_FUNC_RET_Pos)
+
+#define AON_REG_SYSTEM_REG33X_AMU_LITE2_ENABLE_POF_AMU_PPU_VCORE1_FULL_RET_Pos                                           3U
+#define AON_REG_SYSTEM_REG33X_AMU_LITE2_ENABLE_POF_AMU_PPU_VCORE1_FULL_RET_Msk                                           (0x1UL << AON_REG_SYSTEM_REG33X_AMU_LITE2_ENABLE_POF_AMU_PPU_VCORE1_FULL_RET_Pos)
+
+#define AON_REG_SYSTEM_REG33X_AMU_LITE2_ENABLE_PON_AMU_PPU_VPON_LV_Pos                                                   4U
+#define AON_REG_SYSTEM_REG33X_AMU_LITE2_ENABLE_PON_AMU_PPU_VPON_LV_Msk                                                   (0x1UL << AON_REG_SYSTEM_REG33X_AMU_LITE2_ENABLE_PON_AMU_PPU_VPON_LV_Pos)
+
+#define AON_REG_SYSTEM_REG33X_AMU_LITE2_ENABLE_PON_AMU_PPU_VPON_HV_Pos                                                   5U
+#define AON_REG_SYSTEM_REG33X_AMU_LITE2_ENABLE_PON_AMU_PPU_VPON_HV_Msk                                                   (0x1UL << AON_REG_SYSTEM_REG33X_AMU_LITE2_ENABLE_PON_AMU_PPU_VPON_HV_Pos)
+
+#define AON_REG_SYSTEM_REG33X_AMU_LITE2_ENABLE_POF_AMU_PPU_VPON_FUNC_RET_Pos                                             6U
+#define AON_REG_SYSTEM_REG33X_AMU_LITE2_ENABLE_POF_AMU_PPU_VPON_FUNC_RET_Msk                                             (0x1UL << AON_REG_SYSTEM_REG33X_AMU_LITE2_ENABLE_POF_AMU_PPU_VPON_FUNC_RET_Pos)
+
+#define AON_REG_SYSTEM_REG33X_AMU_LITE2_ENABLE_POF_AMU_PPU_VPON_MEM_OFF_Pos                                              7U
+#define AON_REG_SYSTEM_REG33X_AMU_LITE2_ENABLE_POF_AMU_PPU_VPON_MEM_OFF_Msk                                              (0x1UL << AON_REG_SYSTEM_REG33X_AMU_LITE2_ENABLE_POF_AMU_PPU_VPON_MEM_OFF_Pos)
+
+#define AON_REG_SYSTEM_REG33X_AMU_LITE0_APB_CTRL_SEL_REQ_OSC80_CG_Pos                                                    8U
+#define AON_REG_SYSTEM_REG33X_AMU_LITE0_APB_CTRL_SEL_REQ_OSC80_CG_Msk                                                    (0x1UL << AON_REG_SYSTEM_REG33X_AMU_LITE0_APB_CTRL_SEL_REQ_OSC80_CG_Pos)
+
+#define AON_REG_SYSTEM_REG33X_AMU_LITE1_APB_CTRL_SEL_REQ_PLL_Pos                                                         9U
+#define AON_REG_SYSTEM_REG33X_AMU_LITE1_APB_CTRL_SEL_REQ_PLL_Msk                                                         (0x1UL << AON_REG_SYSTEM_REG33X_AMU_LITE1_APB_CTRL_SEL_REQ_PLL_Pos)
+
+#define AON_REG_SYSTEM_REG33X_AMU_LITE2_APB_CTRL_SEL_REQ_VCORE_OP1_Pos                                                   10U
+#define AON_REG_SYSTEM_REG33X_AMU_LITE2_APB_CTRL_SEL_REQ_VCORE_OP1_Msk                                                   (0x1UL << AON_REG_SYSTEM_REG33X_AMU_LITE2_APB_CTRL_SEL_REQ_VCORE_OP1_Pos)
+
+#define AON_REG_SYSTEM_REG33X_AMU_LITE2_APB_CTRL_SEL_REQ_VCORE_PPU_Pos                                                   11U
+#define AON_REG_SYSTEM_REG33X_AMU_LITE2_APB_CTRL_SEL_REQ_VCORE_PPU_Msk                                                   (0x1UL << AON_REG_SYSTEM_REG33X_AMU_LITE2_APB_CTRL_SEL_REQ_VCORE_PPU_Pos)
+
+#define AON_REG_SYSTEM_REG33X_AMU_LITE2_APB_CTRL_SEL_REQ_VPON_PPU_Pos                                                    12U
+#define AON_REG_SYSTEM_REG33X_AMU_LITE2_APB_CTRL_SEL_REQ_VPON_PPU_Msk                                                    (0x1UL << AON_REG_SYSTEM_REG33X_AMU_LITE2_APB_CTRL_SEL_REQ_VPON_PPU_Pos)
+
+#define AON_REG_SYSTEM_REG33X_AMU_LITE0_ENABLE_PON_AMU_OSC80_CG_Pos                                                      13U
+#define AON_REG_SYSTEM_REG33X_AMU_LITE0_ENABLE_PON_AMU_OSC80_CG_Msk                                                      (0x1UL << AON_REG_SYSTEM_REG33X_AMU_LITE0_ENABLE_PON_AMU_OSC80_CG_Pos)
+
+#define AON_REG_SYSTEM_REG33X_AMU_LITE0_ENABLE_POF_AMU_OSC80_CG_Pos                                                      14U
+#define AON_REG_SYSTEM_REG33X_AMU_LITE0_ENABLE_POF_AMU_OSC80_CG_Msk                                                      (0x1UL << AON_REG_SYSTEM_REG33X_AMU_LITE0_ENABLE_POF_AMU_OSC80_CG_Pos)
+
+#define AON_REG_SYSTEM_REG33X_AMU_LITE0_ENABLE_PON_AMU_OSC80_Pos                                                         15U
+#define AON_REG_SYSTEM_REG33X_AMU_LITE0_ENABLE_PON_AMU_OSC80_Msk                                                         (0x1UL << AON_REG_SYSTEM_REG33X_AMU_LITE0_ENABLE_PON_AMU_OSC80_Pos)
+
+#define AON_REG_SYSTEM_REG33X_AMU_LITE0_ENABLE_POF_AMU_OSC80_Pos                                                         16U
+#define AON_REG_SYSTEM_REG33X_AMU_LITE0_ENABLE_POF_AMU_OSC80_Msk                                                         (0x1UL << AON_REG_SYSTEM_REG33X_AMU_LITE0_ENABLE_POF_AMU_OSC80_Pos)
+
+#define AON_REG_SYSTEM_REG33X_AMU_LITE1_ENABLE_PON_AMU_PLL1_Pos                                                          17U
+#define AON_REG_SYSTEM_REG33X_AMU_LITE1_ENABLE_PON_AMU_PLL1_Msk                                                          (0x1UL << AON_REG_SYSTEM_REG33X_AMU_LITE1_ENABLE_PON_AMU_PLL1_Pos)
+
+#define AON_REG_SYSTEM_REG33X_AMU_LITE1_ENABLE_POF_AMU_PLL1_Pos                                                          18U
+#define AON_REG_SYSTEM_REG33X_AMU_LITE1_ENABLE_POF_AMU_PLL1_Msk                                                          (0x1UL << AON_REG_SYSTEM_REG33X_AMU_LITE1_ENABLE_POF_AMU_PLL1_Pos)
+
+#define AON_REG_SYSTEM_REG33X_AMU_LITE1_ENABLE_PON_AMU_XTAL40_Pos                                                        19U
+#define AON_REG_SYSTEM_REG33X_AMU_LITE1_ENABLE_PON_AMU_XTAL40_Msk                                                        (0x1UL << AON_REG_SYSTEM_REG33X_AMU_LITE1_ENABLE_PON_AMU_XTAL40_Pos)
+
+#define AON_REG_SYSTEM_REG33X_AMU_LITE1_ENABLE_POF_AMU_XTAL40_Pos                                                        20U
+#define AON_REG_SYSTEM_REG33X_AMU_LITE1_ENABLE_POF_AMU_XTAL40_Msk                                                        (0x1UL << AON_REG_SYSTEM_REG33X_AMU_LITE1_ENABLE_POF_AMU_XTAL40_Pos)
+
+#define AON_REG_SYSTEM_REG33X_AMU_LITE2_ENABLE_PON_AMU_CORE_OP1_Pos                                                      21U
+#define AON_REG_SYSTEM_REG33X_AMU_LITE2_ENABLE_PON_AMU_CORE_OP1_Msk                                                      (0x1UL << AON_REG_SYSTEM_REG33X_AMU_LITE2_ENABLE_PON_AMU_CORE_OP1_Pos)
+
+#define AON_REG_SYSTEM_REG33X_AMU_LITE2_ENABLE_POF_AMU_CORE_OP1_Pos                                                      22U
+#define AON_REG_SYSTEM_REG33X_AMU_LITE2_ENABLE_POF_AMU_CORE_OP1_Msk                                                      (0x1UL << AON_REG_SYSTEM_REG33X_AMU_LITE2_ENABLE_POF_AMU_CORE_OP1_Pos)
+
+#define AON_REG_SYSTEM_REG33X_AMU_LITE2_ENABLE_PON_AMU_PPU_VCORE1_Pos                                                    23U
+#define AON_REG_SYSTEM_REG33X_AMU_LITE2_ENABLE_PON_AMU_PPU_VCORE1_Msk                                                    (0x1UL << AON_REG_SYSTEM_REG33X_AMU_LITE2_ENABLE_PON_AMU_PPU_VCORE1_Pos)
+
+#define AON_REG_SYSTEM_REG33X_AMU_LITE2_ENABLE_POF_AMU_PPU_VCORE1_OFF_Pos                                                24U
+#define AON_REG_SYSTEM_REG33X_AMU_LITE2_ENABLE_POF_AMU_PPU_VCORE1_OFF_Msk                                                (0x1UL << AON_REG_SYSTEM_REG33X_AMU_LITE2_ENABLE_POF_AMU_PPU_VCORE1_OFF_Pos)
+
+#define AON_REG_SYSTEM_REG33X_AMU_LITE2_ENABLE_PON_AMU_PPU_VPON_Pos                                                      25U
+#define AON_REG_SYSTEM_REG33X_AMU_LITE2_ENABLE_PON_AMU_PPU_VPON_Msk                                                      (0x1UL << AON_REG_SYSTEM_REG33X_AMU_LITE2_ENABLE_PON_AMU_PPU_VPON_Pos)
+
+#define AON_REG_SYSTEM_REG33X_AMU_LITE2_ENABLE_POF_AMU_PPU_VPON_OFF_Pos                                                  26U
+#define AON_REG_SYSTEM_REG33X_AMU_LITE2_ENABLE_POF_AMU_PPU_VPON_OFF_Msk                                                  (0x1UL << AON_REG_SYSTEM_REG33X_AMU_LITE2_ENABLE_POF_AMU_PPU_VPON_OFF_Pos)
+
+#define AON_REG_SYSTEM_REG33X_AMU_LITE2_ENABLE_PON_AMU_OSC10_Pos                                                         27U
+#define AON_REG_SYSTEM_REG33X_AMU_LITE2_ENABLE_PON_AMU_OSC10_Msk                                                         (0x1UL << AON_REG_SYSTEM_REG33X_AMU_LITE2_ENABLE_PON_AMU_OSC10_Pos)
+
+#define AON_REG_SYSTEM_REG33X_AMU_LITE2_ENABLE_POF_AMU_OSC10_Pos                                                         28U
+#define AON_REG_SYSTEM_REG33X_AMU_LITE2_ENABLE_POF_AMU_OSC10_Msk                                                         (0x1UL << AON_REG_SYSTEM_REG33X_AMU_LITE2_ENABLE_POF_AMU_OSC10_Pos)
+
+#define AON_REG_SYSTEM_REG33X_R_AON_FEN_AMU_LITE2_Pos                                                                    29U
+#define AON_REG_SYSTEM_REG33X_R_AON_FEN_AMU_LITE2_Msk                                                                    (0x1UL << AON_REG_SYSTEM_REG33X_R_AON_FEN_AMU_LITE2_Pos)
+
+#define AON_REG_SYSTEM_REG33X_R_AON_FEN_AMU_LITE1_Pos                                                                    30U
+#define AON_REG_SYSTEM_REG33X_R_AON_FEN_AMU_LITE1_Msk                                                                    (0x1UL << AON_REG_SYSTEM_REG33X_R_AON_FEN_AMU_LITE1_Pos)
+
+#define AON_REG_SYSTEM_REG33X_R_AON_FEN_AMU_LITE0_Pos                                                                    31U
+#define AON_REG_SYSTEM_REG33X_R_AON_FEN_AMU_LITE0_Msk                                                                    (0x1UL << AON_REG_SYSTEM_REG33X_R_AON_FEN_AMU_LITE0_Pos)
+
+/* 0x88     0x4000_0088
+    0       R/W     TEST1_amu                                                   1'b0
+    1       R/W     DS_low_pwr_amu                                              1'b0
+    2       R/W     SD_low_pwr_amu                                              1'b0
+    3       R/W     LS_low_pwr_amu                                              1'b0
+    4       R/W     DS_UNK_low_pwr_amu                                          1'b0
+    6:5     R/W     DS_K_low_pwr_amu                                            2'b01
+    7       R/W     DS_norm_pwr_amu                                             1'b0
+    8       R/W     SD_norm_pwr_amu                                             1'b0
+    9       R/W     LS_norm_pwr_amu                                             1'b0
+    10      R/W     DS_UNK_norm_pwr_amu                                         1'b0
+    12:11   R/W     DS_K_norm_pwr_amu                                           2'b01
+    15:13   R/W     RSVD_1                                                      3'b0
+    16      R/W     amu_ram_vsel                                                1'b0
+    31:17   R       RSVD                                                        15'b0
+ */
+typedef union _AON_REG_SYSTEM_REG34X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t TEST1_amu: 1;
+        uint32_t DS_low_pwr_amu: 1;
+        uint32_t SD_low_pwr_amu: 1;
+        uint32_t LS_low_pwr_amu: 1;
+        uint32_t DS_UNK_low_pwr_amu: 1;
+        uint32_t DS_K_low_pwr_amu: 2;
+        uint32_t DS_norm_pwr_amu: 1;
+        uint32_t SD_norm_pwr_amu: 1;
+        uint32_t LS_norm_pwr_amu: 1;
+        uint32_t DS_UNK_norm_pwr_amu: 1;
+        uint32_t DS_K_norm_pwr_amu: 2;
+        uint32_t RSVD_1: 3;
+        uint32_t amu_ram_vsel: 1;
+        uint32_t RSVD: 15;
+    };
+} AON_REG_SYSTEM_REG34X_TYPE;
+
+/*0x4000_0088 AON_REG_SYSTEM_REG34X*/
+#define AON_REG_SYSTEM_REG34X_TEST1_amu_Pos                                                                              0U
+#define AON_REG_SYSTEM_REG34X_TEST1_amu_Msk                                                                              (0x1UL << AON_REG_SYSTEM_REG34X_TEST1_amu_Pos)
+
+#define AON_REG_SYSTEM_REG34X_DS_low_pwr_amu_Pos                                                                         1U
+#define AON_REG_SYSTEM_REG34X_DS_low_pwr_amu_Msk                                                                         (0x1UL << AON_REG_SYSTEM_REG34X_DS_low_pwr_amu_Pos)
+
+#define AON_REG_SYSTEM_REG34X_SD_low_pwr_amu_Pos                                                                         2U
+#define AON_REG_SYSTEM_REG34X_SD_low_pwr_amu_Msk                                                                         (0x1UL << AON_REG_SYSTEM_REG34X_SD_low_pwr_amu_Pos)
+
+#define AON_REG_SYSTEM_REG34X_LS_low_pwr_amu_Pos                                                                         3U
+#define AON_REG_SYSTEM_REG34X_LS_low_pwr_amu_Msk                                                                         (0x1UL << AON_REG_SYSTEM_REG34X_LS_low_pwr_amu_Pos)
+
+#define AON_REG_SYSTEM_REG34X_DS_UNK_low_pwr_amu_Pos                                                                     4U
+#define AON_REG_SYSTEM_REG34X_DS_UNK_low_pwr_amu_Msk                                                                     (0x1UL << AON_REG_SYSTEM_REG34X_DS_UNK_low_pwr_amu_Pos)
+
+#define AON_REG_SYSTEM_REG34X_DS_K_low_pwr_amu_Pos                                                                       5U
+#define AON_REG_SYSTEM_REG34X_DS_K_low_pwr_amu_Msk                                                                       (0x3UL << AON_REG_SYSTEM_REG34X_DS_K_low_pwr_amu_Pos)
+
+#define AON_REG_SYSTEM_REG34X_DS_norm_pwr_amu_Pos                                                                        7U
+#define AON_REG_SYSTEM_REG34X_DS_norm_pwr_amu_Msk                                                                        (0x1UL << AON_REG_SYSTEM_REG34X_DS_norm_pwr_amu_Pos)
+
+#define AON_REG_SYSTEM_REG34X_SD_norm_pwr_amu_Pos                                                                        8U
+#define AON_REG_SYSTEM_REG34X_SD_norm_pwr_amu_Msk                                                                        (0x1UL << AON_REG_SYSTEM_REG34X_SD_norm_pwr_amu_Pos)
+
+#define AON_REG_SYSTEM_REG34X_LS_norm_pwr_amu_Pos                                                                        9U
+#define AON_REG_SYSTEM_REG34X_LS_norm_pwr_amu_Msk                                                                        (0x1UL << AON_REG_SYSTEM_REG34X_LS_norm_pwr_amu_Pos)
+
+#define AON_REG_SYSTEM_REG34X_DS_UNK_norm_pwr_amu_Pos                                                                    10U
+#define AON_REG_SYSTEM_REG34X_DS_UNK_norm_pwr_amu_Msk                                                                    (0x1UL << AON_REG_SYSTEM_REG34X_DS_UNK_norm_pwr_amu_Pos)
+
+#define AON_REG_SYSTEM_REG34X_DS_K_norm_pwr_amu_Pos                                                                      11U
+#define AON_REG_SYSTEM_REG34X_DS_K_norm_pwr_amu_Msk                                                                      (0x3UL << AON_REG_SYSTEM_REG34X_DS_K_norm_pwr_amu_Pos)
+
+#define AON_REG_SYSTEM_REG34X_RSVD_1_Pos                                                                                 13U
+#define AON_REG_SYSTEM_REG34X_RSVD_1_Msk                                                                                 (0x7UL << AON_REG_SYSTEM_REG34X_RSVD_1_Pos)
+
+#define AON_REG_SYSTEM_REG34X_amu_ram_vsel_Pos                                                                           16U
+#define AON_REG_SYSTEM_REG34X_amu_ram_vsel_Msk                                                                           (0x1UL << AON_REG_SYSTEM_REG34X_amu_ram_vsel_Pos)
+
+#define AON_REG_SYSTEM_REG34X_RSVD_Pos                                                                                   17U
+#define AON_REG_SYSTEM_REG34X_RSVD_Msk                                                                                   (0x7FFFUL << AON_REG_SYSTEM_REG34X_RSVD_Pos)
+
+/* 0x8C     0x4000_008c
+    2:0     R/W     WPULSE_amu_lv                                               3'b000
+    5:3     R/W     WA_amu_lv                                                   3'b101
+    9:6     R/W     RM_amu_lv                                                   4'b0010
+    10      R/W     RME_amu_lv                                                  1'b1
+    12:11   R/W     RA_amu_lv                                                   2'b00
+    15:13   R       RSVD_1                                                      3'b0
+    18:16   R/W     WPULSE_amu_hv                                               3'b000
+    21:19   R/W     WA_amu_hv                                                   3'b100
+    25:22   R/W     RM_amu_hv                                                   4'b0011
+    26      R/W     RME_amu_hv                                                  1'b1
+    28:27   R/W     RA_amu_hv                                                   2'b00
+    31:29   R       RSVD                                                        3'b0
+ */
+typedef union _AON_REG_SYSTEM_REG35X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t WPULSE_amu_lv: 3;
+        uint32_t WA_amu_lv: 3;
+        uint32_t RM_amu_lv: 4;
+        uint32_t RME_amu_lv: 1;
+        uint32_t RA_amu_lv: 2;
+        uint32_t RSVD_1: 3;
+        uint32_t WPULSE_amu_hv: 3;
+        uint32_t WA_amu_hv: 3;
+        uint32_t RM_amu_hv: 4;
+        uint32_t RME_amu_hv: 1;
+        uint32_t RA_amu_hv: 2;
+        uint32_t RSVD: 3;
+    };
+} AON_REG_SYSTEM_REG35X_TYPE;
+
+/*0x4000_008c AON_REG_SYSTEM_REG35X*/
+#define AON_REG_SYSTEM_REG35X_WPULSE_amu_lv_Pos                                                                          0U
+#define AON_REG_SYSTEM_REG35X_WPULSE_amu_lv_Msk                                                                          (0x7UL << AON_REG_SYSTEM_REG35X_WPULSE_amu_lv_Pos)
+
+#define AON_REG_SYSTEM_REG35X_WA_amu_lv_Pos                                                                              3U
+#define AON_REG_SYSTEM_REG35X_WA_amu_lv_Msk                                                                              (0x7UL << AON_REG_SYSTEM_REG35X_WA_amu_lv_Pos)
+
+#define AON_REG_SYSTEM_REG35X_RM_amu_lv_Pos                                                                              6U
+#define AON_REG_SYSTEM_REG35X_RM_amu_lv_Msk                                                                              (0xFUL << AON_REG_SYSTEM_REG35X_RM_amu_lv_Pos)
+
+#define AON_REG_SYSTEM_REG35X_RME_amu_lv_Pos                                                                             10U
+#define AON_REG_SYSTEM_REG35X_RME_amu_lv_Msk                                                                             (0x1UL << AON_REG_SYSTEM_REG35X_RME_amu_lv_Pos)
+
+#define AON_REG_SYSTEM_REG35X_RA_amu_lv_Pos                                                                              11U
+#define AON_REG_SYSTEM_REG35X_RA_amu_lv_Msk                                                                              (0x3UL << AON_REG_SYSTEM_REG35X_RA_amu_lv_Pos)
+
+#define AON_REG_SYSTEM_REG35X_RSVD_1_Pos                                                                                 13U
+#define AON_REG_SYSTEM_REG35X_RSVD_1_Msk                                                                                 (0x7UL << AON_REG_SYSTEM_REG35X_RSVD_1_Pos)
+
+#define AON_REG_SYSTEM_REG35X_WPULSE_amu_hv_Pos                                                                          16U
+#define AON_REG_SYSTEM_REG35X_WPULSE_amu_hv_Msk                                                                          (0x7UL << AON_REG_SYSTEM_REG35X_WPULSE_amu_hv_Pos)
+
+#define AON_REG_SYSTEM_REG35X_WA_amu_hv_Pos                                                                              19U
+#define AON_REG_SYSTEM_REG35X_WA_amu_hv_Msk                                                                              (0x7UL << AON_REG_SYSTEM_REG35X_WA_amu_hv_Pos)
+
+#define AON_REG_SYSTEM_REG35X_RM_amu_hv_Pos                                                                              22U
+#define AON_REG_SYSTEM_REG35X_RM_amu_hv_Msk                                                                              (0xFUL << AON_REG_SYSTEM_REG35X_RM_amu_hv_Pos)
+
+#define AON_REG_SYSTEM_REG35X_RME_amu_hv_Pos                                                                             26U
+#define AON_REG_SYSTEM_REG35X_RME_amu_hv_Msk                                                                             (0x1UL << AON_REG_SYSTEM_REG35X_RME_amu_hv_Pos)
+
+#define AON_REG_SYSTEM_REG35X_RA_amu_hv_Pos                                                                              27U
+#define AON_REG_SYSTEM_REG35X_RA_amu_hv_Msk                                                                              (0x3UL << AON_REG_SYSTEM_REG35X_RA_amu_hv_Pos)
+
+#define AON_REG_SYSTEM_REG35X_RSVD_Pos                                                                                   29U
+#define AON_REG_SYSTEM_REG35X_RSVD_Msk                                                                                   (0x7UL << AON_REG_SYSTEM_REG35X_RSVD_Pos)
+
+/* 0x90     0x4000_0090
+    15:0    R/W     DUMMY_SYSTEM_2                                              16'b0
+    31:16   R/W     DUMMY_SYSTEM_1                                              16'b0
+ */
+typedef union _AON_REG_SYSTEM_REG36X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t DUMMY_SYSTEM_2: 16;
+        uint32_t DUMMY_SYSTEM_1: 16;
+    };
+} AON_REG_SYSTEM_REG36X_TYPE;
+
+/*0x4000_0090 AON_REG_SYSTEM_REG36X*/
+#define AON_REG_SYSTEM_REG36X_DUMMY_SYSTEM_2_Pos                                                                         0U
+#define AON_REG_SYSTEM_REG36X_DUMMY_SYSTEM_2_Msk                                                                         (0xFFFFUL << AON_REG_SYSTEM_REG36X_DUMMY_SYSTEM_2_Pos)
+
+#define AON_REG_SYSTEM_REG36X_DUMMY_SYSTEM_1_Pos                                                                         16U
+#define AON_REG_SYSTEM_REG36X_DUMMY_SYSTEM_1_Msk                                                                         (0xFFFFUL << AON_REG_SYSTEM_REG36X_DUMMY_SYSTEM_1_Pos)
+
+/* 0x94     0x4000_0094
+    0       R/W     FORCE_AMU0_APB_RUN                                          1'b1
+    1       R/W     FORCE_AMU1_APB_RUN                                          1'b1
+    2       R/W     PADRV_PCUT_CTRL_SEL                                         1'b0
+    4:3     R/W     TOTAL_DELAY_OSC10                                           2'b00
+    8:5     R/W     TOTAL_DELAY_VPON_PPU_3                                      4'b0000
+    12:9    R/W     TOTAL_DELAY_VPON_PPU_2                                      4'b0000
+    16:13   R/W     TOTAL_DELAY_VPON_PPU_1                                      4'b0000
+    20:17   R/W     TOTAL_DELAY_OSC80                                           4'b0000
+    24:21   R/W     TOTAL_DELAY_PLL                                             4'b0000
+    25      R/W     EN_BUCK_BOOST_ENLPM_SWITCH                                  1'b0
+    26      R/W     SW_LDO2PWRCUT                                               1'b0
+    27      R/W     POW_LDO                                                     1'b0
+    28      R/W     LDO_DEBUG_VPULSE                                            1'b0
+    31:29   R/W     SW_LDO_OUT                                                  3'b100
+ */
+typedef union _AON_REG_SYSTEM_REG37X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t FORCE_AMU0_APB_RUN: 1;
+        uint32_t FORCE_AMU1_APB_RUN: 1;
+        uint32_t PADRV_PCUT_CTRL_SEL: 1;
+        uint32_t TOTAL_DELAY_OSC10: 2;
+        uint32_t TOTAL_DELAY_VPON_PPU_3: 4;
+        uint32_t TOTAL_DELAY_VPON_PPU_2: 4;
+        uint32_t TOTAL_DELAY_VPON_PPU_1: 4;
+        uint32_t TOTAL_DELAY_OSC80: 4;
+        uint32_t TOTAL_DELAY_PLL: 4;
+        uint32_t EN_BUCK_BOOST_ENLPM_SWITCH: 1;
+        uint32_t SW_LDO2PWRCUT: 1;
+        uint32_t POW_LDO: 1;
+        uint32_t LDO_DEBUG_VPULSE: 1;
+        uint32_t SW_LDO_OUT: 3;
+    };
+} AON_REG_SYSTEM_REG37X_TYPE;
+
+/*0x4000_0094 AON_REG_SYSTEM_REG37X*/
+#define AON_REG_SYSTEM_REG37X_FORCE_AMU0_APB_RUN_Pos                                                                     0U
+#define AON_REG_SYSTEM_REG37X_FORCE_AMU0_APB_RUN_Msk                                                                     (0x1UL << AON_REG_SYSTEM_REG37X_FORCE_AMU0_APB_RUN_Pos)
+
+#define AON_REG_SYSTEM_REG37X_FORCE_AMU1_APB_RUN_Pos                                                                     1U
+#define AON_REG_SYSTEM_REG37X_FORCE_AMU1_APB_RUN_Msk                                                                     (0x1UL << AON_REG_SYSTEM_REG37X_FORCE_AMU1_APB_RUN_Pos)
+
+#define AON_REG_SYSTEM_REG37X_PADRV_PCUT_CTRL_SEL_Pos                                                                    2U
+#define AON_REG_SYSTEM_REG37X_PADRV_PCUT_CTRL_SEL_Msk                                                                    (0x1UL << AON_REG_SYSTEM_REG37X_PADRV_PCUT_CTRL_SEL_Pos)
+
+#define AON_REG_SYSTEM_REG37X_TOTAL_DELAY_OSC10_Pos                                                                      3U
+#define AON_REG_SYSTEM_REG37X_TOTAL_DELAY_OSC10_Msk                                                                      (0x3UL << AON_REG_SYSTEM_REG37X_TOTAL_DELAY_OSC10_Pos)
+
+#define AON_REG_SYSTEM_REG37X_TOTAL_DELAY_VPON_PPU_3_Pos                                                                 5U
+#define AON_REG_SYSTEM_REG37X_TOTAL_DELAY_VPON_PPU_3_Msk                                                                 (0xFUL << AON_REG_SYSTEM_REG37X_TOTAL_DELAY_VPON_PPU_3_Pos)
+
+#define AON_REG_SYSTEM_REG37X_TOTAL_DELAY_VPON_PPU_2_Pos                                                                 9U
+#define AON_REG_SYSTEM_REG37X_TOTAL_DELAY_VPON_PPU_2_Msk                                                                 (0xFUL << AON_REG_SYSTEM_REG37X_TOTAL_DELAY_VPON_PPU_2_Pos)
+
+#define AON_REG_SYSTEM_REG37X_TOTAL_DELAY_VPON_PPU_1_Pos                                                                 13U
+#define AON_REG_SYSTEM_REG37X_TOTAL_DELAY_VPON_PPU_1_Msk                                                                 (0xFUL << AON_REG_SYSTEM_REG37X_TOTAL_DELAY_VPON_PPU_1_Pos)
+
+#define AON_REG_SYSTEM_REG37X_TOTAL_DELAY_OSC80_Pos                                                                      17U
+#define AON_REG_SYSTEM_REG37X_TOTAL_DELAY_OSC80_Msk                                                                      (0xFUL << AON_REG_SYSTEM_REG37X_TOTAL_DELAY_OSC80_Pos)
+
+#define AON_REG_SYSTEM_REG37X_TOTAL_DELAY_PLL_Pos                                                                        21U
+#define AON_REG_SYSTEM_REG37X_TOTAL_DELAY_PLL_Msk                                                                        (0xFUL << AON_REG_SYSTEM_REG37X_TOTAL_DELAY_PLL_Pos)
+
+#define AON_REG_SYSTEM_REG37X_EN_BUCK_BOOST_ENLPM_SWITCH_Pos                                                             25U
+#define AON_REG_SYSTEM_REG37X_EN_BUCK_BOOST_ENLPM_SWITCH_Msk                                                             (0x1UL << AON_REG_SYSTEM_REG37X_EN_BUCK_BOOST_ENLPM_SWITCH_Pos)
+
+#define AON_REG_SYSTEM_REG37X_SW_LDO2PWRCUT_Pos                                                                          26U
+#define AON_REG_SYSTEM_REG37X_SW_LDO2PWRCUT_Msk                                                                          (0x1UL << AON_REG_SYSTEM_REG37X_SW_LDO2PWRCUT_Pos)
+
+#define AON_REG_SYSTEM_REG37X_POW_LDO_Pos                                                                                27U
+#define AON_REG_SYSTEM_REG37X_POW_LDO_Msk                                                                                (0x1UL << AON_REG_SYSTEM_REG37X_POW_LDO_Pos)
+
+#define AON_REG_SYSTEM_REG37X_LDO_DEBUG_VPULSE_Pos                                                                       28U
+#define AON_REG_SYSTEM_REG37X_LDO_DEBUG_VPULSE_Msk                                                                       (0x1UL << AON_REG_SYSTEM_REG37X_LDO_DEBUG_VPULSE_Pos)
+
+#define AON_REG_SYSTEM_REG37X_SW_LDO_OUT_Pos                                                                             29U
+#define AON_REG_SYSTEM_REG37X_SW_LDO_OUT_Msk                                                                             (0x7UL << AON_REG_SYSTEM_REG37X_SW_LDO_OUT_Pos)
+
+/* 0x98     0x4000_0098
+    0       R/W     BT_MAC_VSEL                                                 1'b0
+    1       R/W     BT_MAC_CCMP_VSEL                                            1'b0
+    2       R/W     BUFFER_RAM_VSEL                                             1'b0
+    3       R/W     USB_RAM_VSEL                                                1'b0
+    4       R/W     CAN_RAM_VSEL                                                1'b0
+    5       R       CPU_RAM_VSEL                                                1'b0
+    6       R/W     AUDIO_RAM_VSEL                                              1'b0
+    7       R/W     BTPHY_RAM_VSEL                                              1'b0
+    8       R/W     PLATFORM_ROM_VSEL                                           1'b0
+    9       R/W     RETSRAM_VSEL                                                1'b0
+    10      R/W     CACHE_VSEL                                                  1'b0
+    31:11   R       RSVD                                                        21'h0
+ */
+typedef union _AON_REG_SYSTEM_REG38X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t BT_MAC_VSEL: 1;
+        uint32_t BT_MAC_CCMP_VSEL: 1;
+        uint32_t BUFFER_RAM_VSEL: 1;
+        uint32_t USB_RAM_VSEL: 1;
+        uint32_t CAN_RAM_VSEL: 1;
+        uint32_t CPU_RAM_VSEL: 1;
+        uint32_t AUDIO_RAM_VSEL: 1;
+        uint32_t BTPHY_RAM_VSEL: 1;
+        uint32_t PLATFORM_ROM_VSEL: 1;
+        uint32_t RETSRAM_VSEL: 1;
+        uint32_t CACHE_VSEL: 1;
+        uint32_t RSVD: 21;
+    };
+} AON_REG_SYSTEM_REG38X_TYPE;
+
+/*0x4000_0098 AON_REG_SYSTEM_REG38X*/
+#define AON_REG_SYSTEM_REG38X_BT_MAC_VSEL_Pos                                                                            0U
+#define AON_REG_SYSTEM_REG38X_BT_MAC_VSEL_Msk                                                                            (0x1UL << AON_REG_SYSTEM_REG38X_BT_MAC_VSEL_Pos)
+
+#define AON_REG_SYSTEM_REG38X_BT_MAC_CCMP_VSEL_Pos                                                                       1U
+#define AON_REG_SYSTEM_REG38X_BT_MAC_CCMP_VSEL_Msk                                                                       (0x1UL << AON_REG_SYSTEM_REG38X_BT_MAC_CCMP_VSEL_Pos)
+
+#define AON_REG_SYSTEM_REG38X_BUFFER_RAM_VSEL_Pos                                                                        2U
+#define AON_REG_SYSTEM_REG38X_BUFFER_RAM_VSEL_Msk                                                                        (0x1UL << AON_REG_SYSTEM_REG38X_BUFFER_RAM_VSEL_Pos)
+
+#define AON_REG_SYSTEM_REG38X_USB_RAM_VSEL_Pos                                                                           3U
+#define AON_REG_SYSTEM_REG38X_USB_RAM_VSEL_Msk                                                                           (0x1UL << AON_REG_SYSTEM_REG38X_USB_RAM_VSEL_Pos)
+
+#define AON_REG_SYSTEM_REG38X_CAN_RAM_VSEL_Pos                                                                           4U
+#define AON_REG_SYSTEM_REG38X_CAN_RAM_VSEL_Msk                                                                           (0x1UL << AON_REG_SYSTEM_REG38X_CAN_RAM_VSEL_Pos)
+
+#define AON_REG_SYSTEM_REG38X_CPU_RAM_VSEL_Pos                                                                           5U
+#define AON_REG_SYSTEM_REG38X_CPU_RAM_VSEL_Msk                                                                           (0x1UL << AON_REG_SYSTEM_REG38X_CPU_RAM_VSEL_Pos)
+
+#define AON_REG_SYSTEM_REG38X_AUDIO_RAM_VSEL_Pos                                                                         6U
+#define AON_REG_SYSTEM_REG38X_AUDIO_RAM_VSEL_Msk                                                                         (0x1UL << AON_REG_SYSTEM_REG38X_AUDIO_RAM_VSEL_Pos)
+
+#define AON_REG_SYSTEM_REG38X_BTPHY_RAM_VSEL_Pos                                                                         7U
+#define AON_REG_SYSTEM_REG38X_BTPHY_RAM_VSEL_Msk                                                                         (0x1UL << AON_REG_SYSTEM_REG38X_BTPHY_RAM_VSEL_Pos)
+
+#define AON_REG_SYSTEM_REG38X_PLATFORM_ROM_VSEL_Pos                                                                      8U
+#define AON_REG_SYSTEM_REG38X_PLATFORM_ROM_VSEL_Msk                                                                      (0x1UL << AON_REG_SYSTEM_REG38X_PLATFORM_ROM_VSEL_Pos)
+
+#define AON_REG_SYSTEM_REG38X_RETSRAM_VSEL_Pos                                                                           9U
+#define AON_REG_SYSTEM_REG38X_RETSRAM_VSEL_Msk                                                                           (0x1UL << AON_REG_SYSTEM_REG38X_RETSRAM_VSEL_Pos)
+
+#define AON_REG_SYSTEM_REG38X_CACHE_VSEL_Pos                                                                             10U
+#define AON_REG_SYSTEM_REG38X_CACHE_VSEL_Msk                                                                             (0x1UL << AON_REG_SYSTEM_REG38X_CACHE_VSEL_Pos)
+
+#define AON_REG_SYSTEM_REG38X_RSVD_Pos                                                                                   11U
+#define AON_REG_SYSTEM_REG38X_RSVD_Msk                                                                                   (0x1FFFFFUL << AON_REG_SYSTEM_REG38X_RSVD_Pos)
+
+/* 0xC0     0x4000_00c0
+    6:0     R/W     RESERVED_3                                                  7'h0
+    7       R/W     RESERVED_2                                                  1'h0
+    15:8    R/W     RESERVED_1                                                  8'h0
+    31:16   R/W     RESERVED                                                    16'h0
+ */
+typedef union _AON_REG_FW_GENERAL_REG0X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED_3: 7;
+        uint32_t RESERVED_2: 1;
+        uint32_t RESERVED_1: 8;
+        uint32_t RESERVED: 16;
+    };
+} AON_REG_FW_GENERAL_REG0X_TYPE;
+
+/*0x4000_00c0 AON_REG_FW_GENERAL_REG0X*/
+#define AON_REG_FW_GENERAL_REG0X_RESERVED_3_Pos                                                                          0U
+#define AON_REG_FW_GENERAL_REG0X_RESERVED_3_Msk                                                                          (0x7FUL << AON_REG_FW_GENERAL_REG0X_RESERVED_3_Pos)
+
+#define AON_REG_FW_GENERAL_REG0X_RESERVED_2_Pos                                                                          7U
+#define AON_REG_FW_GENERAL_REG0X_RESERVED_2_Msk                                                                          (0x1UL << AON_REG_FW_GENERAL_REG0X_RESERVED_2_Pos)
+
+#define AON_REG_FW_GENERAL_REG0X_RESERVED_1_Pos                                                                          8U
+#define AON_REG_FW_GENERAL_REG0X_RESERVED_1_Msk                                                                          (0xFFUL << AON_REG_FW_GENERAL_REG0X_RESERVED_1_Pos)
+
+#define AON_REG_FW_GENERAL_REG0X_RESERVED_Pos                                                                            16U
+#define AON_REG_FW_GENERAL_REG0X_RESERVED_Msk                                                                            (0xFFFFUL << AON_REG_FW_GENERAL_REG0X_RESERVED_Pos)
+
+/* 0xC4     0x4000_00c4
+    15:0    R/W     RESERVED_1                                                  16'h0
+    31:16   R/W     RESERVED                                                    16'h0
+ */
+typedef union _AON_REG_FW_GENERAL_REG1X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED_1: 16;
+        uint32_t RESERVED: 16;
+    };
+} AON_REG_FW_GENERAL_REG1X_TYPE;
+
+/*0x4000_00c4 AON_REG_FW_GENERAL_REG1X*/
+#define AON_REG_FW_GENERAL_REG1X_RESERVED_1_Pos                                                                          0U
+#define AON_REG_FW_GENERAL_REG1X_RESERVED_1_Msk                                                                          (0xFFFFUL << AON_REG_FW_GENERAL_REG1X_RESERVED_1_Pos)
+
+#define AON_REG_FW_GENERAL_REG1X_RESERVED_Pos                                                                            16U
+#define AON_REG_FW_GENERAL_REG1X_RESERVED_Msk                                                                            (0xFFFFUL << AON_REG_FW_GENERAL_REG1X_RESERVED_Pos)
+
+/* 0xC8     0x4000_00c8
+    15:0    R/W     RESERVED_1                                                  16'h0
+    31:16   R/W     RESERVED                                                    16'h0
+ */
+typedef union _AON_REG_FW_GENERAL_REG2X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED_1: 16;
+        uint32_t RESERVED: 16;
+    };
+} AON_REG_FW_GENERAL_REG2X_TYPE;
+
+/*0x4000_00c8 AON_REG_FW_GENERAL_REG2X*/
+#define AON_REG_FW_GENERAL_REG2X_RESERVED_1_Pos                                                                          0U
+#define AON_REG_FW_GENERAL_REG2X_RESERVED_1_Msk                                                                          (0xFFFFUL << AON_REG_FW_GENERAL_REG2X_RESERVED_1_Pos)
+
+#define AON_REG_FW_GENERAL_REG2X_RESERVED_Pos                                                                            16U
+#define AON_REG_FW_GENERAL_REG2X_RESERVED_Msk                                                                            (0xFFFFUL << AON_REG_FW_GENERAL_REG2X_RESERVED_Pos)
+
+/* 0xCC     0x4000_00cc
+    15:0    R/W     RESERVED_1                                                  16'h0
+    31:16   R/W     RESERVED                                                    16'h0
+ */
+typedef union _AON_REG_FW_GENERAL_REG3X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED_1: 16;
+        uint32_t RESERVED: 16;
+    };
+} AON_REG_FW_GENERAL_REG3X_TYPE;
+
+/*0x4000_00cc AON_REG_FW_GENERAL_REG3X*/
+#define AON_REG_FW_GENERAL_REG3X_RESERVED_1_Pos                                                                          0U
+#define AON_REG_FW_GENERAL_REG3X_RESERVED_1_Msk                                                                          (0xFFFFUL << AON_REG_FW_GENERAL_REG3X_RESERVED_1_Pos)
+
+#define AON_REG_FW_GENERAL_REG3X_RESERVED_Pos                                                                            16U
+#define AON_REG_FW_GENERAL_REG3X_RESERVED_Msk                                                                            (0xFFFFUL << AON_REG_FW_GENERAL_REG3X_RESERVED_Pos)
+
+/* 0xD0     0x4000_00d0
+    15:0    R/W     RESERVED_1                                                  16'h0
+    31:16   R/W     RESERVED                                                    16'h0
+ */
+typedef union _AON_REG_FW_GENERAL_REG4X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED_1: 16;
+        uint32_t RESERVED: 16;
+    };
+} AON_REG_FW_GENERAL_REG4X_TYPE;
+
+/*0x4000_00d0 AON_REG_FW_GENERAL_REG4X*/
+#define AON_REG_FW_GENERAL_REG4X_RESERVED_1_Pos                                                                          0U
+#define AON_REG_FW_GENERAL_REG4X_RESERVED_1_Msk                                                                          (0xFFFFUL << AON_REG_FW_GENERAL_REG4X_RESERVED_1_Pos)
+
+#define AON_REG_FW_GENERAL_REG4X_RESERVED_Pos                                                                            16U
+#define AON_REG_FW_GENERAL_REG4X_RESERVED_Msk                                                                            (0xFFFFUL << AON_REG_FW_GENERAL_REG4X_RESERVED_Pos)
+
+/* 0xD4     0x4000_00d4
+    15:0    R/W     FW_GP_DUMMY2                                                16'h0
+    31:16   R/W     FW_GP_DUMMY1                                                16'h0
+ */
+typedef union _AON_REG_FW_GENERAL_REG5X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t FW_GP_DUMMY2: 16;
+        uint32_t FW_GP_DUMMY1: 16;
+    };
+} AON_REG_FW_GENERAL_REG5X_TYPE;
+
+/*0x4000_00d4 AON_REG_FW_GENERAL_REG5X*/
+#define AON_REG_FW_GENERAL_REG5X_FW_GP_DUMMY2_Pos                                                                        0U
+#define AON_REG_FW_GENERAL_REG5X_FW_GP_DUMMY2_Msk                                                                        (0xFFFFUL << AON_REG_FW_GENERAL_REG5X_FW_GP_DUMMY2_Pos)
+
+#define AON_REG_FW_GENERAL_REG5X_FW_GP_DUMMY1_Pos                                                                        16U
+#define AON_REG_FW_GENERAL_REG5X_FW_GP_DUMMY1_Msk                                                                        (0xFFFFUL << AON_REG_FW_GENERAL_REG5X_FW_GP_DUMMY1_Pos)
+
+/* 0xD8     0x4000_00d8
+    0       R/W     IS_PASSWORD_HCI_CMD                 1'h0
+    1       R/W     IS_OTA_MODE                         1'h0
+    2       R/W     IS_FT_MODE                          1'h0
+    3       R/W     IS_HCI_MODE                         1'h0
+    4       R/W     IS_AIRPLANE_MODE                    1'h0
+    5       R/W     IS_RESPONSE_HCI_CMD                 1'h0
+    6       R/W     IS_RXI300_DISABLE                   1'h0
+    15:7    R/W     FW_GP_1_2                           10'h0
+    31:16   R/W     FW_GP_1_1                           16'h0
+ */
+typedef union _AON_REG_FW_GENERAL_REG6X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t IS_PASSWORD_HCI_CMD: 1;
+        uint32_t IS_OTA_MODE: 1;
+        uint32_t IS_FT_MODE: 1;
+        uint32_t IS_HCI_MODE: 1;
+        uint32_t IS_AIRPLANE_MODE: 1;
+        uint32_t IS_RESPONSE_HCI_CMD: 1;
+        uint32_t IS_RXI300_DISABLE: 1;
+        uint32_t FW_GP_1_2: 9;
+        uint32_t FW_GP_1_1: 16;
+    };
+} AON_REG_FW_GENERAL_REG6X_TYPE;
+
+/*0x4000_00d8 AON_REG_FW_GENERAL_REG6X*/
+#define AON_REG_FW_GENERAL_REG6X_IS_PASSWORD_HCI_CMD_Pos                             0U
+#define AON_REG_FW_GENERAL_REG6X_IS_PASSWORD_HCI_CMD_Msk                             (0x1UL << AON_REG_FW_GENERAL_REG6X_IS_PASSWORD_HCI_CMD_Pos)
+
+#define AON_REG_FW_GENERAL_REG6X_IS_OTA_MODE_Pos                                     1U
+#define AON_REG_FW_GENERAL_REG6X_IS_OTA_MODE_Msk                                     (0x1UL << AON_REG_FW_GENERAL_REG6X_IS_OTA_MODE_Pos)
+
+#define AON_REG_FW_GENERAL_REG6X_IS_FT_MODE_Pos                                      2U
+#define AON_REG_FW_GENERAL_REG6X_IS_FT_MODE_Msk                                      (0x1UL << AON_REG_FW_GENERAL_REG6X_IS_FT_MODE_Pos)
+
+#define AON_REG_FW_GENERAL_REG6X_IS_HCI_MODE_Pos                                     3U
+#define AON_REG_FW_GENERAL_REG6X_IS_HCI_MODE_Msk                                     (0x1UL << AON_REG_FW_GENERAL_REG6X_IS_HCI_MODE_Pos)
+
+#define AON_REG_FW_GENERAL_REG6X_IS_AIRPLANE_MODE_Pos                                4U
+#define AON_REG_FW_GENERAL_REG6X_IS_AIRPLANE_MODE_Msk                                (0x1UL << AON_REG_FW_GENERAL_REG6X_IS_AIRPLANE_MODE_Pos)
+
+#define AON_REG_FW_GENERAL_REG6X_IS_RESPONSE_HCI_CMD_Pos                             5U
+#define AON_REG_FW_GENERAL_REG6X_IS_RESPONSE_HCI_CMD_Msk                             (0x1UL << AON_REG_FW_GENERAL_REG6X_IS_RESPONSE_HCI_CMD_Pos)
+
+#define AON_REG_FW_GENERAL_REG6X_IS_RXI300_DISABLE_Pos                               6U
+#define AON_REG_FW_GENERAL_REG6X_IS_RXI300_DISABLE_Msk                               (0x1UL << AON_REG_FW_GENERAL_REG6X_IS_RXI300_DISABLE_Pos)
+
+#define AON_REG_FW_GENERAL_REG6X_FW_GP_1_2_Pos                                       7U
+#define AON_REG_FW_GENERAL_REG6X_FW_GP_1_2_Msk                                       (0x1FFUL << AON_REG_FW_GENERAL_REG6X_FW_GP_1_2_Pos)
+
+#define AON_REG_FW_GENERAL_REG6X_FW_GP_1_1_Pos                                       16U
+#define AON_REG_FW_GENERAL_REG6X_FW_GP_1_1_Msk                                       (0xFFFFUL << AON_REG_FW_GENERAL_REG6X_FW_GP_1_1_Pos)
+
+/* 0xDC     0x4000_00dc
+    31:0    R/W     DEBUG_AUTHENTICATION_0              32'h0
+ */
+typedef union _AON_REG_DEBUG_AUTHENTICATION0_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t DEBUG_AUTHENTICATION_0;
+    };
+} AON_REG_DEBUG_AUTHENTICATION0_TYPE;
+
+/*0x4000_00dc AON_REG_DEBUG_AUTHENTICATION0*/
+#define AON_REG_DEBUG_AUTHENTICATION0_DEBUG_AUTHENTICATION_0_Pos                     0U
+#define AON_REG_DEBUG_AUTHENTICATION0_DEBUG_AUTHENTICATION_0_Msk                     (0xFFFFFFFFUL << AON_REG_DEBUG_AUTHENTICATION0_DEBUG_AUTHENTICATION_0_Pos)
+
+/* 0xE0     0x4000_00e0
+    31:0    R/W     DEBUG_AUTHENTICATION_1              32'h0
+ */
+typedef union _AON_REG_DEBUG_AUTHENTICATION1_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t DEBUG_AUTHENTICATION_1;
+    };
+} AON_REG_DEBUG_AUTHENTICATION1_TYPE;
+
+/*0x4000_00e0 AON_REG_DEBUG_AUTHENTICATION1*/
+#define AON_REG_DEBUG_AUTHENTICATION1_DEBUG_AUTHENTICATION_1_Pos                     0U
+#define AON_REG_DEBUG_AUTHENTICATION1_DEBUG_AUTHENTICATION_1_Msk                     (0xFFFFFFFFUL << AON_REG_DEBUG_AUTHENTICATION1_DEBUG_AUTHENTICATION_1_Pos)
+
+/* 0xE4     0x4000_00e4
+    31:0    R/W     DEBUG_AUTHENTICATION_2              32'h0
+ */
+typedef union _AON_REG_DEBUG_AUTHENTICATION2_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t DEBUG_AUTHENTICATION_2;
+    };
+} AON_REG_DEBUG_AUTHENTICATION2_TYPE;
+
+/*0x4000_00e4 AON_REG_DEBUG_AUTHENTICATION2*/
+#define AON_REG_DEBUG_AUTHENTICATION2_DEBUG_AUTHENTICATION_2_Pos                     0U
+#define AON_REG_DEBUG_AUTHENTICATION2_DEBUG_AUTHENTICATION_2_Msk                     (0xFFFFFFFFUL << AON_REG_DEBUG_AUTHENTICATION2_DEBUG_AUTHENTICATION_2_Pos)
+
+/* 0xE8     0x4000_00e8
+    31:0    R/W     DEBUG_AUTHENTICATION_3              32'h0
+ */
+typedef union _AON_REG_DEBUG_AUTHENTICATION3_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t DEBUG_AUTHENTICATION_3;
+    };
+} AON_REG_DEBUG_AUTHENTICATION3_TYPE;
+
+/*0x4000_00e8 AON_REG_DEBUG_AUTHENTICATION3*/
+#define AON_REG_DEBUG_AUTHENTICATION3_DEBUG_AUTHENTICATION_3_Pos                     0U
+#define AON_REG_DEBUG_AUTHENTICATION3_DEBUG_AUTHENTICATION_3_Msk                     (0xFFFFFFFFUL << AON_REG_DEBUG_AUTHENTICATION3_DEBUG_AUTHENTICATION_3_Pos)
+
+/* 0xEC     0x4000_00ec
+    15:0    R/W     FW_GP_1_12                                                  16'h0
+    31:16   R/W     FW_GP_1_11                                                  16'h0
+ */
+typedef union _AON_REG_FW_GENERAL_REG11X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t FW_GP_1_12: 16;
+        uint32_t FW_GP_1_11: 16;
+    };
+} AON_REG_FW_GENERAL_REG11X_TYPE;
+
+/*0x4000_00ec AON_REG_FW_GENERAL_REG11X*/
+#define AON_REG_FW_GENERAL_REG11X_FW_GP_1_12_Pos                                                                         0U
+#define AON_REG_FW_GENERAL_REG11X_FW_GP_1_12_Msk                                                                         (0xFFFFUL << AON_REG_FW_GENERAL_REG11X_FW_GP_1_12_Pos)
+
+#define AON_REG_FW_GENERAL_REG11X_FW_GP_1_11_Pos                                                                         16U
+#define AON_REG_FW_GENERAL_REG11X_FW_GP_1_11_Msk                                                                         (0xFFFFUL << AON_REG_FW_GENERAL_REG11X_FW_GP_1_11_Pos)
+
+/* 0xF0     0x4000_00f0
+    11:0    R       RTC_PRE_SCALE_CNTR_AON_11_0                                 12'h0
+    14:12   R       RESERVED                                                    3'd0
+    15      R/W1C   RTC_ALL_CNTR_AON_W1C                                        1'b0
+    31:16   R/W     FW_GP_1_13                                                  16'h0
+ */
+typedef union _AON_REG_FW_GENERAL_REG12X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RTC_PRE_SCALE_CNTR_AON_11_0: 12;
+        uint32_t RESERVED: 3;
+        uint32_t RTC_ALL_CNTR_AON_W1C: 1;
+        uint32_t FW_GP_1_13: 16;
+    };
+} AON_REG_FW_GENERAL_REG12X_TYPE;
+
+/*0x4000_00f0 AON_REG_FW_GENERAL_REG12X*/
+#define AON_REG_FW_GENERAL_REG12X_RTC_PRE_SCALE_CNTR_AON_11_0_Pos                                                        0U
+#define AON_REG_FW_GENERAL_REG12X_RTC_PRE_SCALE_CNTR_AON_11_0_Msk                                                        (0xFFFUL << AON_REG_FW_GENERAL_REG12X_RTC_PRE_SCALE_CNTR_AON_11_0_Pos)
+
+#define AON_REG_FW_GENERAL_REG12X_RESERVED_Pos                                                                           12U
+#define AON_REG_FW_GENERAL_REG12X_RESERVED_Msk                                                                           (0x7UL << AON_REG_FW_GENERAL_REG12X_RESERVED_Pos)
+
+#define AON_REG_FW_GENERAL_REG12X_RTC_ALL_CNTR_AON_W1C_Pos                                                               15U
+#define AON_REG_FW_GENERAL_REG12X_RTC_ALL_CNTR_AON_W1C_Msk                                                               (0x1UL << AON_REG_FW_GENERAL_REG12X_RTC_ALL_CNTR_AON_W1C_Pos)
+
+#define AON_REG_FW_GENERAL_REG12X_FW_GP_1_13_Pos                                                                         16U
+#define AON_REG_FW_GENERAL_REG12X_FW_GP_1_13_Msk                                                                         (0xFFFFUL << AON_REG_FW_GENERAL_REG12X_FW_GP_1_13_Pos)
+
+/* 0xF4     0x4000_00f4
+    31:0    R       RTC_CNTR_AON_31_0                                           32'h0
+ */
+typedef union _AON_REG_FW_GENERAL_REG13X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RTC_CNTR_AON_31_0;
+    };
+} AON_REG_FW_GENERAL_REG13X_TYPE;
+
+/*0x4000_00f4 AON_REG_FW_GENERAL_REG13X*/
+#define AON_REG_FW_GENERAL_REG13X_RTC_CNTR_AON_31_0_Pos                                                                  0U
+#define AON_REG_FW_GENERAL_REG13X_RTC_CNTR_AON_31_0_Msk                                                                  (0xFFFFFFFFUL << AON_REG_FW_GENERAL_REG13X_RTC_CNTR_AON_31_0_Pos)
+
+/* 0xF8     0x4000_00f8
+    0       W1O     IS_DISABLE_HCI_RAM_PATCH            1'h0
+    1       W1O     IS_DISABLE_HCI_FLASH_ACCESS         1'h0
+    2       W1O     IS_DISABLE_HCI_SYSTEM_ACCESS        1'h0
+    3       W1O     IS_DISABLE_HCI_OTP_ACCESS           1'h0
+    4       W1O     IS_DISABLE_HCI_READ_CHIP_INFO       1'h0
+    5       W1O     IS_DISABLE_HCI_MAC_RF_ACCESS        1'h0
+    6       W1O     IS_DISABLE_HCI_WIFI_COEXIST_FUNC    1'h0
+    7       W1O     IS_DISABLE_HCI_SET_UART_BAUDRATE    1'h0
+    8       W1O     IS_DISABLE_HCI_RF_DBG_FUNC          1'h0
+    9       W1O     IS_DISABLE_HCI_BT_EXTENSION         1'h0
+    10      W1O     IS_DISABLE_HCI_BT_DBG_FUNC          1'h0
+    11      W1O     IS_DISABLE_HCI_BT_TEST              1'h0
+    12      W1O     IS_DISABLE_HCI_RF_TEST              1'h0
+    13      W1O     IS_DISABLE_HCI_PM_TEST              1'h0
+    14      W1O     IS_DISABLE_HCI_MODEM_RF_ACCESS      1'h0
+    15      W1O     IS_OTP_INVALID                      1'h0
+    16      W1O     IS_DEBUG_AUTHENTICATION_INVALID     1'h0
+    17      W1O     IS_ENABLE_OTP_READ_PROTECT          1'h0
+    18      W1O     IS_ENABLE_OTP_WRITE_PROTECT         1'h0
+    19      W1O     IS_ENABLE_IMAGE_AUTH_WHEN_RESUME    1'h0
+    20      W1O     IS_OTP_READ_PROTECT_LOCK            1'h0
+    21      W1O     IS_OTP_WRITE_PROTECT_LOCK           1'h0
+    31:22   W1O     FW_GP_2_1                           10'h0
+ */
+typedef union _AON_REG_FW_GENERAL_REG14X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t IS_DISABLE_HCI_RAM_PATCH: 1;
+        uint32_t IS_DISABLE_HCI_FLASH_ACCESS: 1;
+        uint32_t IS_DISABLE_HCI_SYSTEM_ACCESS: 1;
+        uint32_t IS_DISABLE_HCI_OTP_ACCESS: 1;
+        uint32_t IS_DISABLE_HCI_READ_CHIP_INFO: 1;
+        uint32_t IS_DISABLE_HCI_MAC_RF_ACCESS: 1;
+        uint32_t IS_DISABLE_HCI_WIFI_COEXIST_FUNC: 1;
+        uint32_t IS_DISABLE_HCI_SET_UART_BAUDRATE: 1;
+        uint32_t IS_DISABLE_HCI_RF_DBG_FUNC: 1;
+        uint32_t IS_DISABLE_HCI_BT_EXTENSION: 1;
+        uint32_t IS_DISABLE_HCI_BT_DBG_FUNC: 1;
+        uint32_t IS_DISABLE_HCI_BT_TEST: 1;
+        uint32_t IS_DISABLE_HCI_RF_TEST: 1;
+        uint32_t IS_DISABLE_HCI_PM_TEST: 1;
+        uint32_t IS_DISABLE_HCI_MODEM_RF_ACCESS: 1;
+        uint32_t IS_OTP_INVALID: 1;
+        uint32_t IS_DEBUG_AUTHENTICATION_INVALID: 1;
+        uint32_t IS_ENABLE_OTP_READ_PROTECT: 1;
+        uint32_t IS_ENABLE_OTP_WRITE_PROTECT: 1;
+        uint32_t IS_ENABLE_IMAGE_AUTH_WHEN_RESUME: 1;
+        uint32_t IS_OTP_READ_PROTECT_LOCK: 1;
+        uint32_t IS_OTP_WRITE_PROTECT_LOCK: 1;
+        uint32_t FW_GP_2_1: 10;
+    };
+} AON_REG_FW_GENERAL_REG14X_TYPE;
+
+/*0x4000_00f8 AON_REG_FW_GENERAL_REG14X*/
+#define AON_REG_FW_GENERAL_REG14X_IS_DISABLE_HCI_RAM_PATCH_Pos                       0U
+#define AON_REG_FW_GENERAL_REG14X_IS_DISABLE_HCI_RAM_PATCH_Msk                       (0x1UL << AON_REG_FW_GENERAL_REG14X_IS_DISABLE_HCI_RAM_PATCH_Pos)
+
+#define AON_REG_FW_GENERAL_REG14X_IS_DISABLE_HCI_FLASH_ACCESS_Pos                    1U
+#define AON_REG_FW_GENERAL_REG14X_IS_DISABLE_HCI_FLASH_ACCESS_Msk                    (0x1UL << AON_REG_FW_GENERAL_REG14X_IS_DISABLE_HCI_FLASH_ACCESS_Pos)
+
+#define AON_REG_FW_GENERAL_REG14X_IS_DISABLE_HCI_SYSTEM_ACCESS_Pos                   2U
+#define AON_REG_FW_GENERAL_REG14X_IS_DISABLE_HCI_SYSTEM_ACCESS_Msk                   (0x1UL << AON_REG_FW_GENERAL_REG14X_IS_DISABLE_HCI_SYSTEM_ACCESS_Pos)
+
+#define AON_REG_FW_GENERAL_REG14X_IS_DISABLE_HCI_OTP_ACCESS_Pos                      3U
+#define AON_REG_FW_GENERAL_REG14X_IS_DISABLE_HCI_OTP_ACCESS_Msk                      (0x1UL << AON_REG_FW_GENERAL_REG14X_IS_DISABLE_HCI_OTP_ACCESS_Pos)
+
+#define AON_REG_FW_GENERAL_REG14X_IS_DISABLE_HCI_READ_CHIP_INFO_Pos                  4U
+#define AON_REG_FW_GENERAL_REG14X_IS_DISABLE_HCI_READ_CHIP_INFO_Msk                  (0x1UL << AON_REG_FW_GENERAL_REG14X_IS_DISABLE_HCI_READ_CHIP_INFO_Pos)
+
+#define AON_REG_FW_GENERAL_REG14X_IS_DISABLE_HCI_MAC_RF_ACCESS_Pos                   5U
+#define AON_REG_FW_GENERAL_REG14X_IS_DISABLE_HCI_MAC_RF_ACCESS_Msk                   (0x1UL << AON_REG_FW_GENERAL_REG14X_IS_DISABLE_HCI_MAC_RF_ACCESS_Pos)
+
+#define AON_REG_FW_GENERAL_REG14X_IS_DISABLE_HCI_WIFI_COEXIST_FUNC_Pos               6U
+#define AON_REG_FW_GENERAL_REG14X_IS_DISABLE_HCI_WIFI_COEXIST_FUNC_Msk               (0x1UL << AON_REG_FW_GENERAL_REG14X_IS_DISABLE_HCI_WIFI_COEXIST_FUNC_Pos)
+
+#define AON_REG_FW_GENERAL_REG14X_IS_DISABLE_HCI_SET_UART_BAUDRATE_Pos               7U
+#define AON_REG_FW_GENERAL_REG14X_IS_DISABLE_HCI_SET_UART_BAUDRATE_Msk               (0x1UL << AON_REG_FW_GENERAL_REG14X_IS_DISABLE_HCI_SET_UART_BAUDRATE_Pos)
+
+#define AON_REG_FW_GENERAL_REG14X_IS_DISABLE_HCI_RF_DBG_FUNC_Pos                     8U
+#define AON_REG_FW_GENERAL_REG14X_IS_DISABLE_HCI_RF_DBG_FUNC_Msk                     (0x1UL << AON_REG_FW_GENERAL_REG14X_IS_DISABLE_HCI_RF_DBG_FUNC_Pos)
+
+#define AON_REG_FW_GENERAL_REG14X_IS_DISABLE_HCI_BT_EXTENSION_Pos                    9U
+#define AON_REG_FW_GENERAL_REG14X_IS_DISABLE_HCI_BT_EXTENSION_Msk                    (0x1UL << AON_REG_FW_GENERAL_REG14X_IS_DISABLE_HCI_BT_EXTENSION_Pos)
+
+#define AON_REG_FW_GENERAL_REG14X_IS_DISABLE_HCI_BT_DBG_FUNC_Pos                     10U
+#define AON_REG_FW_GENERAL_REG14X_IS_DISABLE_HCI_BT_DBG_FUNC_Msk                     (0x1UL << AON_REG_FW_GENERAL_REG14X_IS_DISABLE_HCI_BT_DBG_FUNC_Pos)
+
+#define AON_REG_FW_GENERAL_REG14X_IS_DISABLE_HCI_BT_TEST_Pos                         11U
+#define AON_REG_FW_GENERAL_REG14X_IS_DISABLE_HCI_BT_TEST_Msk                         (0x1UL << AON_REG_FW_GENERAL_REG14X_IS_DISABLE_HCI_BT_TEST_Pos)
+
+#define AON_REG_FW_GENERAL_REG14X_IS_DISABLE_HCI_RF_TEST_Pos                         12U
+#define AON_REG_FW_GENERAL_REG14X_IS_DISABLE_HCI_RF_TEST_Msk                         (0x1UL << AON_REG_FW_GENERAL_REG14X_IS_DISABLE_HCI_RF_TEST_Pos)
+
+#define AON_REG_FW_GENERAL_REG14X_IS_DISABLE_HCI_PM_TEST_Pos                         13U
+#define AON_REG_FW_GENERAL_REG14X_IS_DISABLE_HCI_PM_TEST_Msk                         (0x1UL << AON_REG_FW_GENERAL_REG14X_IS_DISABLE_HCI_PM_TEST_Pos)
+
+#define AON_REG_FW_GENERAL_REG14X_IS_DISABLE_HCI_MODEM_RF_ACCESS_Pos                 14U
+#define AON_REG_FW_GENERAL_REG14X_IS_DISABLE_HCI_MODEM_RF_ACCESS_Msk                 (0x1UL << AON_REG_FW_GENERAL_REG14X_IS_DISABLE_HCI_MODEM_RF_ACCESS_Pos)
+
+#define AON_REG_FW_GENERAL_REG14X_IS_OTP_INVALID_Pos                                 15U
+#define AON_REG_FW_GENERAL_REG14X_IS_OTP_INVALID_Msk                                 (0x1UL << AON_REG_FW_GENERAL_REG14X_IS_OTP_INVALID_Pos)
+
+#define AON_REG_FW_GENERAL_REG14X_IS_DEBUG_AUTHENTICATION_INVALID_Pos                16U
+#define AON_REG_FW_GENERAL_REG14X_IS_DEBUG_AUTHENTICATION_INVALID_Msk                (0x1UL << AON_REG_FW_GENERAL_REG14X_IS_DEBUG_AUTHENTICATION_INVALID_Pos)
+
+#define AON_REG_FW_GENERAL_REG14X_IS_ENABLE_OTP_READ_PROTECT_Pos                     17U
+#define AON_REG_FW_GENERAL_REG14X_IS_ENABLE_OTP_READ_PROTECT_Msk                     (0x1UL << AON_REG_FW_GENERAL_REG14X_IS_ENABLE_OTP_READ_PROTECT_Pos)
+
+#define AON_REG_FW_GENERAL_REG14X_IS_ENABLE_OTP_WRITE_PROTECT_Pos                    18U
+#define AON_REG_FW_GENERAL_REG14X_IS_ENABLE_OTP_WRITE_PROTECT_Msk                    (0x1UL << AON_REG_FW_GENERAL_REG14X_IS_ENABLE_OTP_WRITE_PROTECT_Pos)
+
+#define AON_REG_FW_GENERAL_REG14X_IS_ENABLE_IMAGE_AUTH_WHEN_RESUME_Pos               19U
+#define AON_REG_FW_GENERAL_REG14X_IS_ENABLE_IMAGE_AUTH_WHEN_RESUME_Msk               (0x1UL << AON_REG_FW_GENERAL_REG14X_IS_ENABLE_IMAGE_AUTH_WHEN_RESUME_Pos)
+
+#define AON_REG_FW_GENERAL_REG14X_IS_OTP_READ_PROTECT_LOCK_Pos                       20U
+#define AON_REG_FW_GENERAL_REG14X_IS_OTP_READ_PROTECT_LOCK_Msk                       (0x1UL << AON_REG_FW_GENERAL_REG14X_IS_OTP_READ_PROTECT_LOCK_Pos)
+
+#define AON_REG_FW_GENERAL_REG14X_IS_OTP_WRITE_PROTECT_LOCK_Pos                      21U
+#define AON_REG_FW_GENERAL_REG14X_IS_OTP_WRITE_PROTECT_LOCK_Msk                      (0x1UL << AON_REG_FW_GENERAL_REG14X_IS_OTP_WRITE_PROTECT_LOCK_Pos)
+
+#define AON_REG_FW_GENERAL_REG14X_FW_GP_2_1_Pos                                      22U
+#define AON_REG_FW_GENERAL_REG14X_FW_GP_2_1_Msk                                      (0x3FFUL << AON_REG_FW_GENERAL_REG14X_FW_GP_2_1_Pos)
+
+/* 0xFC     0x4000_00fc
+    0       R/W     AON_BOOT_DONE                       1'h0
+    1       R/W     PON_BOOT_DONE                       1'h0
+    15:2    R/W     FW_GP_2_4                           14'h0
+    31:16   R/W     FW_GP_2_3                           16'h0
+ */
+typedef union _AON_REG_FW_GENERAL_REG15X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t AON_BOOT_DONE: 1;
+        uint32_t PON_BOOT_DONE: 1;
+        uint32_t FW_GP_2_4: 14;
+        uint32_t FW_GP_2_3: 16;
+    };
+} AON_REG_FW_GENERAL_REG15X_TYPE;
+
+/*0x4000_00fc AON_REG_FW_GENERAL_REG15X*/
+#define AON_REG_FW_GENERAL_REG15X_AON_BOOT_DONE_Pos                                  0U
+#define AON_REG_FW_GENERAL_REG15X_AON_BOOT_DONE_Msk                                  (0x1UL << AON_REG_FW_GENERAL_REG15X_AON_BOOT_DONE_Pos)
+
+#define AON_REG_FW_GENERAL_REG15X_PON_BOOT_DONE_Pos                                  1U
+#define AON_REG_FW_GENERAL_REG15X_PON_BOOT_DONE_Msk                                  (0x1UL << AON_REG_FW_GENERAL_REG15X_PON_BOOT_DONE_Pos)
+
+#define AON_REG_FW_GENERAL_REG15X_FW_GP_2_4_Pos                                      2U
+#define AON_REG_FW_GENERAL_REG15X_FW_GP_2_4_Msk                                      (0x3FFFUL << AON_REG_FW_GENERAL_REG15X_FW_GP_2_4_Pos)
+
+#define AON_REG_FW_GENERAL_REG15X_FW_GP_2_3_Pos                                      16U
+#define AON_REG_FW_GENERAL_REG15X_FW_GP_2_3_Msk                                      (0xFFFFUL << AON_REG_FW_GENERAL_REG15X_FW_GP_2_3_Pos)
+
+/* 0x100    0x4000_0100
+    7:0     R/W     SYS_RESET_REASON                    8'h0
+    15:8    R/W     APP_GP_2                            8'h0
+    31:16   R/W     APP_GP_1                            16'h0
+ */
+typedef union _AON_REG_FW_GENERAL_REG16X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t SYS_RESET_REASON: 8;
+        uint32_t APP_GP_2: 8;
+        uint32_t APP_GP_1: 16;
+    };
+} AON_REG_FW_GENERAL_REG16X_TYPE;
+
+/*0x4000_0100 AON_REG_FW_GENERAL_REG16X*/
+#define AON_REG_FW_GENERAL_REG16X_SYS_RESET_REASON_Pos                               0U
+#define AON_REG_FW_GENERAL_REG16X_SYS_RESET_REASON_Msk                               (0xFFUL << AON_REG_FW_GENERAL_REG16X_SYS_RESET_REASON_Pos)
+
+#define AON_REG_FW_GENERAL_REG16X_APP_GP_2_Pos                                       8U
+#define AON_REG_FW_GENERAL_REG16X_APP_GP_2_Msk                                       (0xFFUL << AON_REG_FW_GENERAL_REG16X_APP_GP_2_Pos)
+
+#define AON_REG_FW_GENERAL_REG16X_APP_GP_1_Pos                                       16U
+#define AON_REG_FW_GENERAL_REG16X_APP_GP_1_Msk                                       (0xFFFFUL << AON_REG_FW_GENERAL_REG16X_APP_GP_1_Pos)
+
+/* 0x104    0x4000_0104
+    15:0    R/W     APP_GP_4                                                    16'h0
+    31:16   R/W     APP_GP_3                                                    16'h0
+ */
+typedef union _AON_REG_FW_GENERAL_REG17X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t APP_GP_4: 16;
+        uint32_t APP_GP_3: 16;
+    };
+} AON_REG_FW_GENERAL_REG17X_TYPE;
+
+/*0x4000_0104 AON_REG_FW_GENERAL_REG17X*/
+#define AON_REG_FW_GENERAL_REG17X_APP_GP_4_Pos                                                                           0U
+#define AON_REG_FW_GENERAL_REG17X_APP_GP_4_Msk                                                                           (0xFFFFUL << AON_REG_FW_GENERAL_REG17X_APP_GP_4_Pos)
+
+#define AON_REG_FW_GENERAL_REG17X_APP_GP_3_Pos                                                                           16U
+#define AON_REG_FW_GENERAL_REG17X_APP_GP_3_Msk                                                                           (0xFFFFUL << AON_REG_FW_GENERAL_REG17X_APP_GP_3_Pos)
+
+/* 0x120    0x4000_0120
+    0       R/W     PAD_P0_O_0                                                  1'b0
+    1       R/W     PAD_P0_E_0                                                  1'b0
+    2       R/W     PAD_P0_PU_EN_0                                              1'b1
+    3       R/W     AON_PAD_P0_PD_0                                             1'b0
+    4       R/W     PAD_P0_PUPDC_0                                              1'b0
+    5       R/W     PAD_P0_WKEN_0                                               1'b0
+    6       R/W     PAD_P0_WKPOL_0                                              1'b0
+    7       R/W     PAD_P0_SHDN_0                                               1'b1
+    8       R/W     PAD_P0_DEB_0                                                1'b0
+    9       R/W     PAD_P0_RAP_WKEN_0                                           1'b0
+    10      R/W     PAD_P0_PPU_WKEN_0                                           1'b0
+    11      R/W     RESERVED_3                                                  1'b0
+    13:12   R       RESERVED_2                                                  2'b00
+    15:14   R/W     PAD_P0_AON_MUX_0                                            2'b00
+    16      R/W     PAD_P0_O_1                                                  1'b0
+    17      R/W     PAD_P0_E_1                                                  1'b0
+    18      R/W     PAD_P0_PU_EN_1                                              1'b1
+    19      R/W     AON_PAD_P0_PD_1                                             1'b1
+    20      R/W     PAD_P0_PUPDC_1                                              1'b0
+    21      R/W     PAD_P0_WKEN_1                                               1'b0
+    22      R/W     PAD_P0_WKPOL_1                                              1'b0
+    23      R/W     PAD_P0_SHDN_1                                               1'b1
+    24      R/W     PAD_P0_DEB_1                                                1'b0
+    25      R/W     PAD_P0_RAP_WKEN_1                                           1'b0
+    26      R/W     PAD_P0_PPU_WKEN_1                                           1'b0
+    27      R/W     RESERVED_1                                                  1'b0
+    29:28   R       RESERVED                                                    2'b00
+    31:30   R/W     PAD_P0_AON_MUX_1                                            2'b00
+ */
+typedef union _AON_REG_PAD_REG0X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t PAD_P0_O_0: 1;
+        uint32_t PAD_P0_E_0: 1;
+        uint32_t PAD_P0_PU_EN_0: 1;
+        uint32_t AON_PAD_P0_PD_0: 1;
+        uint32_t PAD_P0_PUPDC_0: 1;
+        uint32_t PAD_P0_WKEN_0: 1;
+        uint32_t PAD_P0_WKPOL_0: 1;
+        uint32_t PAD_P0_SHDN_0: 1;
+        uint32_t PAD_P0_DEB_0: 1;
+        uint32_t PAD_P0_RAP_WKEN_0: 1;
+        uint32_t PAD_P0_PPU_WKEN_0: 1;
+        uint32_t RESERVED_3: 1;
+        uint32_t RESERVED_2: 2;
+        uint32_t PAD_P0_AON_MUX_0: 2;
+        uint32_t PAD_P0_O_1: 1;
+        uint32_t PAD_P0_E_1: 1;
+        uint32_t PAD_P0_PU_EN_1: 1;
+        uint32_t AON_PAD_P0_PD_1: 1;
+        uint32_t PAD_P0_PUPDC_1: 1;
+        uint32_t PAD_P0_WKEN_1: 1;
+        uint32_t PAD_P0_WKPOL_1: 1;
+        uint32_t PAD_P0_SHDN_1: 1;
+        uint32_t PAD_P0_DEB_1: 1;
+        uint32_t PAD_P0_RAP_WKEN_1: 1;
+        uint32_t PAD_P0_PPU_WKEN_1: 1;
+        uint32_t RESERVED_1: 1;
+        uint32_t RESERVED: 2;
+        uint32_t PAD_P0_AON_MUX_1: 2;
+    };
+} AON_REG_PAD_REG0X_TYPE;
+
+/*0x4000_0120 AON_REG_PAD_REG0X*/
+#define AON_REG_PAD_REG0X_PAD_P0_O_0_Pos                                                                                 0U
+#define AON_REG_PAD_REG0X_PAD_P0_O_0_Msk                                                                                 (0x1UL << AON_REG_PAD_REG0X_PAD_P0_O_0_Pos)
+
+#define AON_REG_PAD_REG0X_PAD_P0_E_0_Pos                                                                                 1U
+#define AON_REG_PAD_REG0X_PAD_P0_E_0_Msk                                                                                 (0x1UL << AON_REG_PAD_REG0X_PAD_P0_E_0_Pos)
+
+#define AON_REG_PAD_REG0X_PAD_P0_PU_EN_0_Pos                                                                             2U
+#define AON_REG_PAD_REG0X_PAD_P0_PU_EN_0_Msk                                                                             (0x1UL << AON_REG_PAD_REG0X_PAD_P0_PU_EN_0_Pos)
+
+#define AON_REG_PAD_REG0X_AON_PAD_P0_PD_0_Pos                                                                            3U
+#define AON_REG_PAD_REG0X_AON_PAD_P0_PD_0_Msk                                                                            (0x1UL << AON_REG_PAD_REG0X_AON_PAD_P0_PD_0_Pos)
+
+#define AON_REG_PAD_REG0X_PAD_P0_PUPDC_0_Pos                                                                             4U
+#define AON_REG_PAD_REG0X_PAD_P0_PUPDC_0_Msk                                                                             (0x1UL << AON_REG_PAD_REG0X_PAD_P0_PUPDC_0_Pos)
+
+#define AON_REG_PAD_REG0X_PAD_P0_WKEN_0_Pos                                                                              5U
+#define AON_REG_PAD_REG0X_PAD_P0_WKEN_0_Msk                                                                              (0x1UL << AON_REG_PAD_REG0X_PAD_P0_WKEN_0_Pos)
+
+#define AON_REG_PAD_REG0X_PAD_P0_WKPOL_0_Pos                                                                             6U
+#define AON_REG_PAD_REG0X_PAD_P0_WKPOL_0_Msk                                                                             (0x1UL << AON_REG_PAD_REG0X_PAD_P0_WKPOL_0_Pos)
+
+#define AON_REG_PAD_REG0X_PAD_P0_SHDN_0_Pos                                                                              7U
+#define AON_REG_PAD_REG0X_PAD_P0_SHDN_0_Msk                                                                              (0x1UL << AON_REG_PAD_REG0X_PAD_P0_SHDN_0_Pos)
+
+#define AON_REG_PAD_REG0X_PAD_P0_DEB_0_Pos                                                                               8U
+#define AON_REG_PAD_REG0X_PAD_P0_DEB_0_Msk                                                                               (0x1UL << AON_REG_PAD_REG0X_PAD_P0_DEB_0_Pos)
+
+#define AON_REG_PAD_REG0X_PAD_P0_RAP_WKEN_0_Pos                                                                          9U
+#define AON_REG_PAD_REG0X_PAD_P0_RAP_WKEN_0_Msk                                                                          (0x1UL << AON_REG_PAD_REG0X_PAD_P0_RAP_WKEN_0_Pos)
+
+#define AON_REG_PAD_REG0X_PAD_P0_PPU_WKEN_0_Pos                                                                          10U
+#define AON_REG_PAD_REG0X_PAD_P0_PPU_WKEN_0_Msk                                                                          (0x1UL << AON_REG_PAD_REG0X_PAD_P0_PPU_WKEN_0_Pos)
+
+#define AON_REG_PAD_REG0X_RESERVED_3_Pos                                                                                 11U
+#define AON_REG_PAD_REG0X_RESERVED_3_Msk                                                                                 (0x1UL << AON_REG_PAD_REG0X_RESERVED_3_Pos)
+
+#define AON_REG_PAD_REG0X_RESERVED_2_Pos                                                                                 12U
+#define AON_REG_PAD_REG0X_RESERVED_2_Msk                                                                                 (0x3UL << AON_REG_PAD_REG0X_RESERVED_2_Pos)
+
+#define AON_REG_PAD_REG0X_PAD_P0_AON_MUX_0_Pos                                                                           14U
+#define AON_REG_PAD_REG0X_PAD_P0_AON_MUX_0_Msk                                                                           (0x3UL << AON_REG_PAD_REG0X_PAD_P0_AON_MUX_0_Pos)
+
+#define AON_REG_PAD_REG0X_PAD_P0_O_1_Pos                                                                                 16U
+#define AON_REG_PAD_REG0X_PAD_P0_O_1_Msk                                                                                 (0x1UL << AON_REG_PAD_REG0X_PAD_P0_O_1_Pos)
+
+#define AON_REG_PAD_REG0X_PAD_P0_E_1_Pos                                                                                 17U
+#define AON_REG_PAD_REG0X_PAD_P0_E_1_Msk                                                                                 (0x1UL << AON_REG_PAD_REG0X_PAD_P0_E_1_Pos)
+
+#define AON_REG_PAD_REG0X_PAD_P0_PU_EN_1_Pos                                                                             18U
+#define AON_REG_PAD_REG0X_PAD_P0_PU_EN_1_Msk                                                                             (0x1UL << AON_REG_PAD_REG0X_PAD_P0_PU_EN_1_Pos)
+
+#define AON_REG_PAD_REG0X_AON_PAD_P0_PD_1_Pos                                                                            19U
+#define AON_REG_PAD_REG0X_AON_PAD_P0_PD_1_Msk                                                                            (0x1UL << AON_REG_PAD_REG0X_AON_PAD_P0_PD_1_Pos)
+
+#define AON_REG_PAD_REG0X_PAD_P0_PUPDC_1_Pos                                                                             20U
+#define AON_REG_PAD_REG0X_PAD_P0_PUPDC_1_Msk                                                                             (0x1UL << AON_REG_PAD_REG0X_PAD_P0_PUPDC_1_Pos)
+
+#define AON_REG_PAD_REG0X_PAD_P0_WKEN_1_Pos                                                                              21U
+#define AON_REG_PAD_REG0X_PAD_P0_WKEN_1_Msk                                                                              (0x1UL << AON_REG_PAD_REG0X_PAD_P0_WKEN_1_Pos)
+
+#define AON_REG_PAD_REG0X_PAD_P0_WKPOL_1_Pos                                                                             22U
+#define AON_REG_PAD_REG0X_PAD_P0_WKPOL_1_Msk                                                                             (0x1UL << AON_REG_PAD_REG0X_PAD_P0_WKPOL_1_Pos)
+
+#define AON_REG_PAD_REG0X_PAD_P0_SHDN_1_Pos                                                                              23U
+#define AON_REG_PAD_REG0X_PAD_P0_SHDN_1_Msk                                                                              (0x1UL << AON_REG_PAD_REG0X_PAD_P0_SHDN_1_Pos)
+
+#define AON_REG_PAD_REG0X_PAD_P0_DEB_1_Pos                                                                               24U
+#define AON_REG_PAD_REG0X_PAD_P0_DEB_1_Msk                                                                               (0x1UL << AON_REG_PAD_REG0X_PAD_P0_DEB_1_Pos)
+
+#define AON_REG_PAD_REG0X_PAD_P0_RAP_WKEN_1_Pos                                                                          25U
+#define AON_REG_PAD_REG0X_PAD_P0_RAP_WKEN_1_Msk                                                                          (0x1UL << AON_REG_PAD_REG0X_PAD_P0_RAP_WKEN_1_Pos)
+
+#define AON_REG_PAD_REG0X_PAD_P0_PPU_WKEN_1_Pos                                                                          26U
+#define AON_REG_PAD_REG0X_PAD_P0_PPU_WKEN_1_Msk                                                                          (0x1UL << AON_REG_PAD_REG0X_PAD_P0_PPU_WKEN_1_Pos)
+
+#define AON_REG_PAD_REG0X_RESERVED_1_Pos                                                                                 27U
+#define AON_REG_PAD_REG0X_RESERVED_1_Msk                                                                                 (0x1UL << AON_REG_PAD_REG0X_RESERVED_1_Pos)
+
+#define AON_REG_PAD_REG0X_RESERVED_Pos                                                                                   28U
+#define AON_REG_PAD_REG0X_RESERVED_Msk                                                                                   (0x3UL << AON_REG_PAD_REG0X_RESERVED_Pos)
+
+#define AON_REG_PAD_REG0X_PAD_P0_AON_MUX_1_Pos                                                                           30U
+#define AON_REG_PAD_REG0X_PAD_P0_AON_MUX_1_Msk                                                                           (0x3UL << AON_REG_PAD_REG0X_PAD_P0_AON_MUX_1_Pos)
+
+/* 0x124    0x4000_0124
+    0       R/W     PAD_P0_O_2                                                  1'b0
+    1       R/W     PAD_P0_E_2                                                  1'b0
+    2       R/W     PAD_P0_PU_EN_2                                              1'b1
+    3       R/W     AON_PAD_P0_PD_2                                             1'b0
+    4       R/W     PAD_P0_PUPDC_2                                              1'b0
+    5       R/W     PAD_P0_WKEN_2                                               1'b0
+    6       R/W     PAD_P0_WKPOL_2                                              1'b0
+    7       R/W     PAD_P0_SHDN_2                                               1'b1
+    8       R/W     PAD_P0_DEB_2                                                1'b0
+    9       R/W     PAD_P0_RAP_WKEN_2                                           1'b0
+    10      R/W     PAD_P0_PPU_WKEN_2                                           1'b0
+    11      R/W     RESERVED_3                                                  1'b0
+    13:12   R       RESERVED_2                                                  2'b00
+    15:14   R/W     PAD_P0_AON_MUX_2                                            2'b00
+    16      R/W     PAD_P0_O_3                                                  1'b0
+    17      R/W     PAD_P0_E_3                                                  1'b0
+    18      R/W     PAD_P0_PU_EN_3                                              1'b1
+    19      R/W     AON_PAD_P0_PD_3                                             1'b0
+    20      R/W     PAD_P0_PUPDC_3                                              1'b0
+    21      R/W     PAD_P0_WKEN_3                                               1'b0
+    22      R/W     PAD_P0_WKPOL_3                                              1'b0
+    23      R/W     PAD_P0_SHDN_3                                               1'b1
+    24      R/W     PAD_P0_DEB_3                                                1'b0
+    25      R/W     PAD_P0_RAP_WKEN_3                                           1'b0
+    26      R/W     PAD_P0_PPU_WKEN_3                                           1'b0
+    27      R/W     RESERVED_1                                                  1'b0
+    28      R       RESERVED                                                    1'b0
+    29      R       PAD_P0_I_3                                                  1'b0
+    31:30   R/W     PAD_P0_AON_MUX_3                                            2'b00
+ */
+typedef union _AON_REG_PAD_REG1X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t PAD_P0_O_2: 1;
+        uint32_t PAD_P0_E_2: 1;
+        uint32_t PAD_P0_PU_EN_2: 1;
+        uint32_t AON_PAD_P0_PD_2: 1;
+        uint32_t PAD_P0_PUPDC_2: 1;
+        uint32_t PAD_P0_WKEN_2: 1;
+        uint32_t PAD_P0_WKPOL_2: 1;
+        uint32_t PAD_P0_SHDN_2: 1;
+        uint32_t PAD_P0_DEB_2: 1;
+        uint32_t PAD_P0_RAP_WKEN_2: 1;
+        uint32_t PAD_P0_PPU_WKEN_2: 1;
+        uint32_t RESERVED_3: 1;
+        uint32_t RESERVED_2: 2;
+        uint32_t PAD_P0_AON_MUX_2: 2;
+        uint32_t PAD_P0_O_3: 1;
+        uint32_t PAD_P0_E_3: 1;
+        uint32_t PAD_P0_PU_EN_3: 1;
+        uint32_t AON_PAD_P0_PD_3: 1;
+        uint32_t PAD_P0_PUPDC_3: 1;
+        uint32_t PAD_P0_WKEN_3: 1;
+        uint32_t PAD_P0_WKPOL_3: 1;
+        uint32_t PAD_P0_SHDN_3: 1;
+        uint32_t PAD_P0_DEB_3: 1;
+        uint32_t PAD_P0_RAP_WKEN_3: 1;
+        uint32_t PAD_P0_PPU_WKEN_3: 1;
+        uint32_t RESERVED_1: 1;
+        uint32_t RESERVED: 1;
+        uint32_t PAD_P0_I_3: 1;
+        uint32_t PAD_P0_AON_MUX_3: 2;
+    };
+} AON_REG_PAD_REG1X_TYPE;
+
+/*0x4000_0124 AON_REG_PAD_REG1X*/
+#define AON_REG_PAD_REG1X_PAD_P0_O_2_Pos                                                                                 0U
+#define AON_REG_PAD_REG1X_PAD_P0_O_2_Msk                                                                                 (0x1UL << AON_REG_PAD_REG1X_PAD_P0_O_2_Pos)
+
+#define AON_REG_PAD_REG1X_PAD_P0_E_2_Pos                                                                                 1U
+#define AON_REG_PAD_REG1X_PAD_P0_E_2_Msk                                                                                 (0x1UL << AON_REG_PAD_REG1X_PAD_P0_E_2_Pos)
+
+#define AON_REG_PAD_REG1X_PAD_P0_PU_EN_2_Pos                                                                             2U
+#define AON_REG_PAD_REG1X_PAD_P0_PU_EN_2_Msk                                                                             (0x1UL << AON_REG_PAD_REG1X_PAD_P0_PU_EN_2_Pos)
+
+#define AON_REG_PAD_REG1X_AON_PAD_P0_PD_2_Pos                                                                            3U
+#define AON_REG_PAD_REG1X_AON_PAD_P0_PD_2_Msk                                                                            (0x1UL << AON_REG_PAD_REG1X_AON_PAD_P0_PD_2_Pos)
+
+#define AON_REG_PAD_REG1X_PAD_P0_PUPDC_2_Pos                                                                             4U
+#define AON_REG_PAD_REG1X_PAD_P0_PUPDC_2_Msk                                                                             (0x1UL << AON_REG_PAD_REG1X_PAD_P0_PUPDC_2_Pos)
+
+#define AON_REG_PAD_REG1X_PAD_P0_WKEN_2_Pos                                                                              5U
+#define AON_REG_PAD_REG1X_PAD_P0_WKEN_2_Msk                                                                              (0x1UL << AON_REG_PAD_REG1X_PAD_P0_WKEN_2_Pos)
+
+#define AON_REG_PAD_REG1X_PAD_P0_WKPOL_2_Pos                                                                             6U
+#define AON_REG_PAD_REG1X_PAD_P0_WKPOL_2_Msk                                                                             (0x1UL << AON_REG_PAD_REG1X_PAD_P0_WKPOL_2_Pos)
+
+#define AON_REG_PAD_REG1X_PAD_P0_SHDN_2_Pos                                                                              7U
+#define AON_REG_PAD_REG1X_PAD_P0_SHDN_2_Msk                                                                              (0x1UL << AON_REG_PAD_REG1X_PAD_P0_SHDN_2_Pos)
+
+#define AON_REG_PAD_REG1X_PAD_P0_DEB_2_Pos                                                                               8U
+#define AON_REG_PAD_REG1X_PAD_P0_DEB_2_Msk                                                                               (0x1UL << AON_REG_PAD_REG1X_PAD_P0_DEB_2_Pos)
+
+#define AON_REG_PAD_REG1X_PAD_P0_RAP_WKEN_2_Pos                                                                          9U
+#define AON_REG_PAD_REG1X_PAD_P0_RAP_WKEN_2_Msk                                                                          (0x1UL << AON_REG_PAD_REG1X_PAD_P0_RAP_WKEN_2_Pos)
+
+#define AON_REG_PAD_REG1X_PAD_P0_PPU_WKEN_2_Pos                                                                          10U
+#define AON_REG_PAD_REG1X_PAD_P0_PPU_WKEN_2_Msk                                                                          (0x1UL << AON_REG_PAD_REG1X_PAD_P0_PPU_WKEN_2_Pos)
+
+#define AON_REG_PAD_REG1X_RESERVED_3_Pos                                                                                 11U
+#define AON_REG_PAD_REG1X_RESERVED_3_Msk                                                                                 (0x1UL << AON_REG_PAD_REG1X_RESERVED_3_Pos)
+
+#define AON_REG_PAD_REG1X_RESERVED_2_Pos                                                                                 12U
+#define AON_REG_PAD_REG1X_RESERVED_2_Msk                                                                                 (0x3UL << AON_REG_PAD_REG1X_RESERVED_2_Pos)
+
+#define AON_REG_PAD_REG1X_PAD_P0_AON_MUX_2_Pos                                                                           14U
+#define AON_REG_PAD_REG1X_PAD_P0_AON_MUX_2_Msk                                                                           (0x3UL << AON_REG_PAD_REG1X_PAD_P0_AON_MUX_2_Pos)
+
+#define AON_REG_PAD_REG1X_PAD_P0_O_3_Pos                                                                                 16U
+#define AON_REG_PAD_REG1X_PAD_P0_O_3_Msk                                                                                 (0x1UL << AON_REG_PAD_REG1X_PAD_P0_O_3_Pos)
+
+#define AON_REG_PAD_REG1X_PAD_P0_E_3_Pos                                                                                 17U
+#define AON_REG_PAD_REG1X_PAD_P0_E_3_Msk                                                                                 (0x1UL << AON_REG_PAD_REG1X_PAD_P0_E_3_Pos)
+
+#define AON_REG_PAD_REG1X_PAD_P0_PU_EN_3_Pos                                                                             18U
+#define AON_REG_PAD_REG1X_PAD_P0_PU_EN_3_Msk                                                                             (0x1UL << AON_REG_PAD_REG1X_PAD_P0_PU_EN_3_Pos)
+
+#define AON_REG_PAD_REG1X_AON_PAD_P0_PD_3_Pos                                                                            19U
+#define AON_REG_PAD_REG1X_AON_PAD_P0_PD_3_Msk                                                                            (0x1UL << AON_REG_PAD_REG1X_AON_PAD_P0_PD_3_Pos)
+
+#define AON_REG_PAD_REG1X_PAD_P0_PUPDC_3_Pos                                                                             20U
+#define AON_REG_PAD_REG1X_PAD_P0_PUPDC_3_Msk                                                                             (0x1UL << AON_REG_PAD_REG1X_PAD_P0_PUPDC_3_Pos)
+
+#define AON_REG_PAD_REG1X_PAD_P0_WKEN_3_Pos                                                                              21U
+#define AON_REG_PAD_REG1X_PAD_P0_WKEN_3_Msk                                                                              (0x1UL << AON_REG_PAD_REG1X_PAD_P0_WKEN_3_Pos)
+
+#define AON_REG_PAD_REG1X_PAD_P0_WKPOL_3_Pos                                                                             22U
+#define AON_REG_PAD_REG1X_PAD_P0_WKPOL_3_Msk                                                                             (0x1UL << AON_REG_PAD_REG1X_PAD_P0_WKPOL_3_Pos)
+
+#define AON_REG_PAD_REG1X_PAD_P0_SHDN_3_Pos                                                                              23U
+#define AON_REG_PAD_REG1X_PAD_P0_SHDN_3_Msk                                                                              (0x1UL << AON_REG_PAD_REG1X_PAD_P0_SHDN_3_Pos)
+
+#define AON_REG_PAD_REG1X_PAD_P0_DEB_3_Pos                                                                               24U
+#define AON_REG_PAD_REG1X_PAD_P0_DEB_3_Msk                                                                               (0x1UL << AON_REG_PAD_REG1X_PAD_P0_DEB_3_Pos)
+
+#define AON_REG_PAD_REG1X_PAD_P0_RAP_WKEN_3_Pos                                                                          25U
+#define AON_REG_PAD_REG1X_PAD_P0_RAP_WKEN_3_Msk                                                                          (0x1UL << AON_REG_PAD_REG1X_PAD_P0_RAP_WKEN_3_Pos)
+
+#define AON_REG_PAD_REG1X_PAD_P0_PPU_WKEN_3_Pos                                                                          26U
+#define AON_REG_PAD_REG1X_PAD_P0_PPU_WKEN_3_Msk                                                                          (0x1UL << AON_REG_PAD_REG1X_PAD_P0_PPU_WKEN_3_Pos)
+
+#define AON_REG_PAD_REG1X_RESERVED_1_Pos                                                                                 27U
+#define AON_REG_PAD_REG1X_RESERVED_1_Msk                                                                                 (0x1UL << AON_REG_PAD_REG1X_RESERVED_1_Pos)
+
+#define AON_REG_PAD_REG1X_RESERVED_Pos                                                                                   28U
+#define AON_REG_PAD_REG1X_RESERVED_Msk                                                                                   (0x1UL << AON_REG_PAD_REG1X_RESERVED_Pos)
+
+#define AON_REG_PAD_REG1X_PAD_P0_I_3_Pos                                                                                 29U
+#define AON_REG_PAD_REG1X_PAD_P0_I_3_Msk                                                                                 (0x1UL << AON_REG_PAD_REG1X_PAD_P0_I_3_Pos)
+
+#define AON_REG_PAD_REG1X_PAD_P0_AON_MUX_3_Pos                                                                           30U
+#define AON_REG_PAD_REG1X_PAD_P0_AON_MUX_3_Msk                                                                           (0x3UL << AON_REG_PAD_REG1X_PAD_P0_AON_MUX_3_Pos)
+
+/* 0x128    0x4000_0128
+    0       R/W     PAD_P0_O_4                                                  1'b0
+    1       R/W     PAD_P0_E_4                                                  1'b0
+    2       R/W     PAD_P0_PU_EN_4                                              1'b1
+    3       R/W     AON_PAD_P0_PD_4                                             1'b1
+    4       R/W     PAD_P0_PUPDC_4                                              1'b0
+    5       R/W     PAD_P0_WKEN_4                                               1'b0
+    6       R/W     PAD_P0_WKPOL_4                                              1'b0
+    7       R/W     PAD_P0_SHDN_4                                               1'b1
+    8       R/W     PAD_P0_DEB_4                                                1'b0
+    9       R/W     PAD_P0_RAP_WKEN_4                                           1'b0
+    10      R/W     PAD_P0_PPU_WKEN_4                                           1'b0
+    11      R/W     RESERVED_3                                                  1'b0
+    13:12   R       RESERVED_2                                                  2'b00
+    15:14   R/W     PAD_P0_AON_MUX_4                                            2'b00
+    16      R/W     PAD_P0_O_5                                                  1'b0
+    17      R/W     PAD_P0_E_5                                                  1'b0
+    18      R/W     PAD_P0_PU_EN_5                                              1'b1
+    19      R/W     AON_PAD_P0_PD_5                                             1'b1
+    20      R/W     PAD_P0_PUPDC_5                                              1'b0
+    21      R/W     PAD_P0_WKEN_5                                               1'b0
+    22      R/W     PAD_P0_WKPOL_5                                              1'b0
+    23      R/W     PAD_P0_SHDN_5                                               1'b1
+    24      R/W     PAD_P0_DEB_5                                                1'b0
+    25      R/W     PAD_P0_RAP_WKEN_5                                           1'b0
+    26      R/W     PAD_P0_PPU_WKEN_5                                           1'b0
+    27      R/W     RESERVED_1                                                  1'b0
+    28      R/W     PAD_P0_E2_AUX_5                                             1'b0
+    29      R       RESERVED                                                    1'b0
+    31:30   R/W     PAD_P0_AON_MUX_5                                            2'b00
+ */
+typedef union _AON_REG_PAD_REG2X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t PAD_P0_O_4: 1;
+        uint32_t PAD_P0_E_4: 1;
+        uint32_t PAD_P0_PU_EN_4: 1;
+        uint32_t AON_PAD_P0_PD_4: 1;
+        uint32_t PAD_P0_PUPDC_4: 1;
+        uint32_t PAD_P0_WKEN_4: 1;
+        uint32_t PAD_P0_WKPOL_4: 1;
+        uint32_t PAD_P0_SHDN_4: 1;
+        uint32_t PAD_P0_DEB_4: 1;
+        uint32_t PAD_P0_RAP_WKEN_4: 1;
+        uint32_t PAD_P0_PPU_WKEN_4: 1;
+        uint32_t RESERVED_3: 1;
+        uint32_t RESERVED_2: 2;
+        uint32_t PAD_P0_AON_MUX_4: 2;
+        uint32_t PAD_P0_O_5: 1;
+        uint32_t PAD_P0_E_5: 1;
+        uint32_t PAD_P0_PU_EN_5: 1;
+        uint32_t AON_PAD_P0_PD_5: 1;
+        uint32_t PAD_P0_PUPDC_5: 1;
+        uint32_t PAD_P0_WKEN_5: 1;
+        uint32_t PAD_P0_WKPOL_5: 1;
+        uint32_t PAD_P0_SHDN_5: 1;
+        uint32_t PAD_P0_DEB_5: 1;
+        uint32_t PAD_P0_RAP_WKEN_5: 1;
+        uint32_t PAD_P0_PPU_WKEN_5: 1;
+        uint32_t RESERVED_1: 1;
+        uint32_t PAD_P0_E2_AUX_5: 1;
+        uint32_t RESERVED: 1;
+        uint32_t PAD_P0_AON_MUX_5: 2;
+    };
+} AON_REG_PAD_REG2X_TYPE;
+
+/*0x4000_0128 AON_REG_PAD_REG2X*/
+#define AON_REG_PAD_REG2X_PAD_P0_O_4_Pos                                                                                 0U
+#define AON_REG_PAD_REG2X_PAD_P0_O_4_Msk                                                                                 (0x1UL << AON_REG_PAD_REG2X_PAD_P0_O_4_Pos)
+
+#define AON_REG_PAD_REG2X_PAD_P0_E_4_Pos                                                                                 1U
+#define AON_REG_PAD_REG2X_PAD_P0_E_4_Msk                                                                                 (0x1UL << AON_REG_PAD_REG2X_PAD_P0_E_4_Pos)
+
+#define AON_REG_PAD_REG2X_PAD_P0_PU_EN_4_Pos                                                                             2U
+#define AON_REG_PAD_REG2X_PAD_P0_PU_EN_4_Msk                                                                             (0x1UL << AON_REG_PAD_REG2X_PAD_P0_PU_EN_4_Pos)
+
+#define AON_REG_PAD_REG2X_AON_PAD_P0_PD_4_Pos                                                                            3U
+#define AON_REG_PAD_REG2X_AON_PAD_P0_PD_4_Msk                                                                            (0x1UL << AON_REG_PAD_REG2X_AON_PAD_P0_PD_4_Pos)
+
+#define AON_REG_PAD_REG2X_PAD_P0_PUPDC_4_Pos                                                                             4U
+#define AON_REG_PAD_REG2X_PAD_P0_PUPDC_4_Msk                                                                             (0x1UL << AON_REG_PAD_REG2X_PAD_P0_PUPDC_4_Pos)
+
+#define AON_REG_PAD_REG2X_PAD_P0_WKEN_4_Pos                                                                              5U
+#define AON_REG_PAD_REG2X_PAD_P0_WKEN_4_Msk                                                                              (0x1UL << AON_REG_PAD_REG2X_PAD_P0_WKEN_4_Pos)
+
+#define AON_REG_PAD_REG2X_PAD_P0_WKPOL_4_Pos                                                                             6U
+#define AON_REG_PAD_REG2X_PAD_P0_WKPOL_4_Msk                                                                             (0x1UL << AON_REG_PAD_REG2X_PAD_P0_WKPOL_4_Pos)
+
+#define AON_REG_PAD_REG2X_PAD_P0_SHDN_4_Pos                                                                              7U
+#define AON_REG_PAD_REG2X_PAD_P0_SHDN_4_Msk                                                                              (0x1UL << AON_REG_PAD_REG2X_PAD_P0_SHDN_4_Pos)
+
+#define AON_REG_PAD_REG2X_PAD_P0_DEB_4_Pos                                                                               8U
+#define AON_REG_PAD_REG2X_PAD_P0_DEB_4_Msk                                                                               (0x1UL << AON_REG_PAD_REG2X_PAD_P0_DEB_4_Pos)
+
+#define AON_REG_PAD_REG2X_PAD_P0_RAP_WKEN_4_Pos                                                                          9U
+#define AON_REG_PAD_REG2X_PAD_P0_RAP_WKEN_4_Msk                                                                          (0x1UL << AON_REG_PAD_REG2X_PAD_P0_RAP_WKEN_4_Pos)
+
+#define AON_REG_PAD_REG2X_PAD_P0_PPU_WKEN_4_Pos                                                                          10U
+#define AON_REG_PAD_REG2X_PAD_P0_PPU_WKEN_4_Msk                                                                          (0x1UL << AON_REG_PAD_REG2X_PAD_P0_PPU_WKEN_4_Pos)
+
+#define AON_REG_PAD_REG2X_RESERVED_3_Pos                                                                                 11U
+#define AON_REG_PAD_REG2X_RESERVED_3_Msk                                                                                 (0x1UL << AON_REG_PAD_REG2X_RESERVED_3_Pos)
+
+#define AON_REG_PAD_REG2X_RESERVED_2_Pos                                                                                 12U
+#define AON_REG_PAD_REG2X_RESERVED_2_Msk                                                                                 (0x3UL << AON_REG_PAD_REG2X_RESERVED_2_Pos)
+
+#define AON_REG_PAD_REG2X_PAD_P0_AON_MUX_4_Pos                                                                           14U
+#define AON_REG_PAD_REG2X_PAD_P0_AON_MUX_4_Msk                                                                           (0x3UL << AON_REG_PAD_REG2X_PAD_P0_AON_MUX_4_Pos)
+
+#define AON_REG_PAD_REG2X_PAD_P0_O_5_Pos                                                                                 16U
+#define AON_REG_PAD_REG2X_PAD_P0_O_5_Msk                                                                                 (0x1UL << AON_REG_PAD_REG2X_PAD_P0_O_5_Pos)
+
+#define AON_REG_PAD_REG2X_PAD_P0_E_5_Pos                                                                                 17U
+#define AON_REG_PAD_REG2X_PAD_P0_E_5_Msk                                                                                 (0x1UL << AON_REG_PAD_REG2X_PAD_P0_E_5_Pos)
+
+#define AON_REG_PAD_REG2X_PAD_P0_PU_EN_5_Pos                                                                             18U
+#define AON_REG_PAD_REG2X_PAD_P0_PU_EN_5_Msk                                                                             (0x1UL << AON_REG_PAD_REG2X_PAD_P0_PU_EN_5_Pos)
+
+#define AON_REG_PAD_REG2X_AON_PAD_P0_PD_5_Pos                                                                            19U
+#define AON_REG_PAD_REG2X_AON_PAD_P0_PD_5_Msk                                                                            (0x1UL << AON_REG_PAD_REG2X_AON_PAD_P0_PD_5_Pos)
+
+#define AON_REG_PAD_REG2X_PAD_P0_PUPDC_5_Pos                                                                             20U
+#define AON_REG_PAD_REG2X_PAD_P0_PUPDC_5_Msk                                                                             (0x1UL << AON_REG_PAD_REG2X_PAD_P0_PUPDC_5_Pos)
+
+#define AON_REG_PAD_REG2X_PAD_P0_WKEN_5_Pos                                                                              21U
+#define AON_REG_PAD_REG2X_PAD_P0_WKEN_5_Msk                                                                              (0x1UL << AON_REG_PAD_REG2X_PAD_P0_WKEN_5_Pos)
+
+#define AON_REG_PAD_REG2X_PAD_P0_WKPOL_5_Pos                                                                             22U
+#define AON_REG_PAD_REG2X_PAD_P0_WKPOL_5_Msk                                                                             (0x1UL << AON_REG_PAD_REG2X_PAD_P0_WKPOL_5_Pos)
+
+#define AON_REG_PAD_REG2X_PAD_P0_SHDN_5_Pos                                                                              23U
+#define AON_REG_PAD_REG2X_PAD_P0_SHDN_5_Msk                                                                              (0x1UL << AON_REG_PAD_REG2X_PAD_P0_SHDN_5_Pos)
+
+#define AON_REG_PAD_REG2X_PAD_P0_DEB_5_Pos                                                                               24U
+#define AON_REG_PAD_REG2X_PAD_P0_DEB_5_Msk                                                                               (0x1UL << AON_REG_PAD_REG2X_PAD_P0_DEB_5_Pos)
+
+#define AON_REG_PAD_REG2X_PAD_P0_RAP_WKEN_5_Pos                                                                          25U
+#define AON_REG_PAD_REG2X_PAD_P0_RAP_WKEN_5_Msk                                                                          (0x1UL << AON_REG_PAD_REG2X_PAD_P0_RAP_WKEN_5_Pos)
+
+#define AON_REG_PAD_REG2X_PAD_P0_PPU_WKEN_5_Pos                                                                          26U
+#define AON_REG_PAD_REG2X_PAD_P0_PPU_WKEN_5_Msk                                                                          (0x1UL << AON_REG_PAD_REG2X_PAD_P0_PPU_WKEN_5_Pos)
+
+#define AON_REG_PAD_REG2X_RESERVED_1_Pos                                                                                 27U
+#define AON_REG_PAD_REG2X_RESERVED_1_Msk                                                                                 (0x1UL << AON_REG_PAD_REG2X_RESERVED_1_Pos)
+
+#define AON_REG_PAD_REG2X_PAD_P0_E2_AUX_5_Pos                                                                            28U
+#define AON_REG_PAD_REG2X_PAD_P0_E2_AUX_5_Msk                                                                            (0x1UL << AON_REG_PAD_REG2X_PAD_P0_E2_AUX_5_Pos)
+
+#define AON_REG_PAD_REG2X_RESERVED_Pos                                                                                   29U
+#define AON_REG_PAD_REG2X_RESERVED_Msk                                                                                   (0x1UL << AON_REG_PAD_REG2X_RESERVED_Pos)
+
+#define AON_REG_PAD_REG2X_PAD_P0_AON_MUX_5_Pos                                                                           30U
+#define AON_REG_PAD_REG2X_PAD_P0_AON_MUX_5_Msk                                                                           (0x3UL << AON_REG_PAD_REG2X_PAD_P0_AON_MUX_5_Pos)
+
+/* 0x12C    0x4000_012c
+    0       R/W     PAD_P0_O_6                                                  1'b0
+    1       R/W     PAD_P0_E_6                                                  1'b0
+    2       R/W     PAD_P0_PU_EN_6                                              1'b1
+    3       R/W     AON_PAD_P0_PD_6                                             1'b1
+    4       R/W     PAD_P0_PUPDC_6                                              1'b0
+    5       R/W     PAD_P0_WKEN_6                                               1'b0
+    6       R/W     PAD_P0_WKPOL_6                                              1'b0
+    7       R/W     PAD_P0_SHDN_6                                               1'b1
+    8       R/W     PAD_P0_DEB_6                                                1'b0
+    9       R/W     PAD_P0_RAP_WKEN_6                                           1'b0
+    10      R/W     PAD_P0_PPU_WKEN_6                                           1'b0
+    11      R/W     RESERVED_3                                                  1'b0
+    13:12   R       RESERVED_2                                                  2'b00
+    15:14   R/W     PAD_P0_AON_MUX_6                                            2'b00
+    16      R/W     PAD_P0_O_7                                                  1'b0
+    17      R/W     PAD_P0_E_7                                                  1'b0
+    18      R/W     PAD_P0_PU_EN_7                                              1'b1
+    19      R/W     AON_PAD_P0_PD_7                                             1'b1
+    20      R/W     PAD_P0_PUPDC_7                                              1'b0
+    21      R/W     PAD_P0_WKEN_7                                               1'b0
+    22      R/W     PAD_P0_WKPOL_7                                              1'b0
+    23      R/W     PAD_P0_SHDN_7                                               1'b1
+    24      R/W     PAD_P0_DEB_7                                                1'b0
+    25      R/W     PAD_P0_RAP_WKEN_7                                           1'b0
+    26      R/W     PAD_P0_PPU_WKEN_7                                           1'b0
+    27      R/W     RESERVED_1                                                  1'b0
+    29:28   R       RESERVED                                                    2'b00
+    31:30   R/W     PAD_P0_AON_MUX_7                                            2'b00
+ */
+typedef union _AON_REG_PAD_REG3X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t PAD_P0_O_6: 1;
+        uint32_t PAD_P0_E_6: 1;
+        uint32_t PAD_P0_PU_EN_6: 1;
+        uint32_t AON_PAD_P0_PD_6: 1;
+        uint32_t PAD_P0_PUPDC_6: 1;
+        uint32_t PAD_P0_WKEN_6: 1;
+        uint32_t PAD_P0_WKPOL_6: 1;
+        uint32_t PAD_P0_SHDN_6: 1;
+        uint32_t PAD_P0_DEB_6: 1;
+        uint32_t PAD_P0_RAP_WKEN_6: 1;
+        uint32_t PAD_P0_PPU_WKEN_6: 1;
+        uint32_t RESERVED_3: 1;
+        uint32_t RESERVED_2: 2;
+        uint32_t PAD_P0_AON_MUX_6: 2;
+        uint32_t PAD_P0_O_7: 1;
+        uint32_t PAD_P0_E_7: 1;
+        uint32_t PAD_P0_PU_EN_7: 1;
+        uint32_t AON_PAD_P0_PD_7: 1;
+        uint32_t PAD_P0_PUPDC_7: 1;
+        uint32_t PAD_P0_WKEN_7: 1;
+        uint32_t PAD_P0_WKPOL_7: 1;
+        uint32_t PAD_P0_SHDN_7: 1;
+        uint32_t PAD_P0_DEB_7: 1;
+        uint32_t PAD_P0_RAP_WKEN_7: 1;
+        uint32_t PAD_P0_PPU_WKEN_7: 1;
+        uint32_t RESERVED_1: 1;
+        uint32_t RESERVED: 2;
+        uint32_t PAD_P0_AON_MUX_7: 2;
+    };
+} AON_REG_PAD_REG3X_TYPE;
+
+/*0x4000_012c AON_REG_PAD_REG3X*/
+#define AON_REG_PAD_REG3X_PAD_P0_O_6_Pos                                                                                 0U
+#define AON_REG_PAD_REG3X_PAD_P0_O_6_Msk                                                                                 (0x1UL << AON_REG_PAD_REG3X_PAD_P0_O_6_Pos)
+
+#define AON_REG_PAD_REG3X_PAD_P0_E_6_Pos                                                                                 1U
+#define AON_REG_PAD_REG3X_PAD_P0_E_6_Msk                                                                                 (0x1UL << AON_REG_PAD_REG3X_PAD_P0_E_6_Pos)
+
+#define AON_REG_PAD_REG3X_PAD_P0_PU_EN_6_Pos                                                                             2U
+#define AON_REG_PAD_REG3X_PAD_P0_PU_EN_6_Msk                                                                             (0x1UL << AON_REG_PAD_REG3X_PAD_P0_PU_EN_6_Pos)
+
+#define AON_REG_PAD_REG3X_AON_PAD_P0_PD_6_Pos                                                                            3U
+#define AON_REG_PAD_REG3X_AON_PAD_P0_PD_6_Msk                                                                            (0x1UL << AON_REG_PAD_REG3X_AON_PAD_P0_PD_6_Pos)
+
+#define AON_REG_PAD_REG3X_PAD_P0_PUPDC_6_Pos                                                                             4U
+#define AON_REG_PAD_REG3X_PAD_P0_PUPDC_6_Msk                                                                             (0x1UL << AON_REG_PAD_REG3X_PAD_P0_PUPDC_6_Pos)
+
+#define AON_REG_PAD_REG3X_PAD_P0_WKEN_6_Pos                                                                              5U
+#define AON_REG_PAD_REG3X_PAD_P0_WKEN_6_Msk                                                                              (0x1UL << AON_REG_PAD_REG3X_PAD_P0_WKEN_6_Pos)
+
+#define AON_REG_PAD_REG3X_PAD_P0_WKPOL_6_Pos                                                                             6U
+#define AON_REG_PAD_REG3X_PAD_P0_WKPOL_6_Msk                                                                             (0x1UL << AON_REG_PAD_REG3X_PAD_P0_WKPOL_6_Pos)
+
+#define AON_REG_PAD_REG3X_PAD_P0_SHDN_6_Pos                                                                              7U
+#define AON_REG_PAD_REG3X_PAD_P0_SHDN_6_Msk                                                                              (0x1UL << AON_REG_PAD_REG3X_PAD_P0_SHDN_6_Pos)
+
+#define AON_REG_PAD_REG3X_PAD_P0_DEB_6_Pos                                                                               8U
+#define AON_REG_PAD_REG3X_PAD_P0_DEB_6_Msk                                                                               (0x1UL << AON_REG_PAD_REG3X_PAD_P0_DEB_6_Pos)
+
+#define AON_REG_PAD_REG3X_PAD_P0_RAP_WKEN_6_Pos                                                                          9U
+#define AON_REG_PAD_REG3X_PAD_P0_RAP_WKEN_6_Msk                                                                          (0x1UL << AON_REG_PAD_REG3X_PAD_P0_RAP_WKEN_6_Pos)
+
+#define AON_REG_PAD_REG3X_PAD_P0_PPU_WKEN_6_Pos                                                                          10U
+#define AON_REG_PAD_REG3X_PAD_P0_PPU_WKEN_6_Msk                                                                          (0x1UL << AON_REG_PAD_REG3X_PAD_P0_PPU_WKEN_6_Pos)
+
+#define AON_REG_PAD_REG3X_RESERVED_3_Pos                                                                                 11U
+#define AON_REG_PAD_REG3X_RESERVED_3_Msk                                                                                 (0x1UL << AON_REG_PAD_REG3X_RESERVED_3_Pos)
+
+#define AON_REG_PAD_REG3X_RESERVED_2_Pos                                                                                 12U
+#define AON_REG_PAD_REG3X_RESERVED_2_Msk                                                                                 (0x3UL << AON_REG_PAD_REG3X_RESERVED_2_Pos)
+
+#define AON_REG_PAD_REG3X_PAD_P0_AON_MUX_6_Pos                                                                           14U
+#define AON_REG_PAD_REG3X_PAD_P0_AON_MUX_6_Msk                                                                           (0x3UL << AON_REG_PAD_REG3X_PAD_P0_AON_MUX_6_Pos)
+
+#define AON_REG_PAD_REG3X_PAD_P0_O_7_Pos                                                                                 16U
+#define AON_REG_PAD_REG3X_PAD_P0_O_7_Msk                                                                                 (0x1UL << AON_REG_PAD_REG3X_PAD_P0_O_7_Pos)
+
+#define AON_REG_PAD_REG3X_PAD_P0_E_7_Pos                                                                                 17U
+#define AON_REG_PAD_REG3X_PAD_P0_E_7_Msk                                                                                 (0x1UL << AON_REG_PAD_REG3X_PAD_P0_E_7_Pos)
+
+#define AON_REG_PAD_REG3X_PAD_P0_PU_EN_7_Pos                                                                             18U
+#define AON_REG_PAD_REG3X_PAD_P0_PU_EN_7_Msk                                                                             (0x1UL << AON_REG_PAD_REG3X_PAD_P0_PU_EN_7_Pos)
+
+#define AON_REG_PAD_REG3X_AON_PAD_P0_PD_7_Pos                                                                            19U
+#define AON_REG_PAD_REG3X_AON_PAD_P0_PD_7_Msk                                                                            (0x1UL << AON_REG_PAD_REG3X_AON_PAD_P0_PD_7_Pos)
+
+#define AON_REG_PAD_REG3X_PAD_P0_PUPDC_7_Pos                                                                             20U
+#define AON_REG_PAD_REG3X_PAD_P0_PUPDC_7_Msk                                                                             (0x1UL << AON_REG_PAD_REG3X_PAD_P0_PUPDC_7_Pos)
+
+#define AON_REG_PAD_REG3X_PAD_P0_WKEN_7_Pos                                                                              21U
+#define AON_REG_PAD_REG3X_PAD_P0_WKEN_7_Msk                                                                              (0x1UL << AON_REG_PAD_REG3X_PAD_P0_WKEN_7_Pos)
+
+#define AON_REG_PAD_REG3X_PAD_P0_WKPOL_7_Pos                                                                             22U
+#define AON_REG_PAD_REG3X_PAD_P0_WKPOL_7_Msk                                                                             (0x1UL << AON_REG_PAD_REG3X_PAD_P0_WKPOL_7_Pos)
+
+#define AON_REG_PAD_REG3X_PAD_P0_SHDN_7_Pos                                                                              23U
+#define AON_REG_PAD_REG3X_PAD_P0_SHDN_7_Msk                                                                              (0x1UL << AON_REG_PAD_REG3X_PAD_P0_SHDN_7_Pos)
+
+#define AON_REG_PAD_REG3X_PAD_P0_DEB_7_Pos                                                                               24U
+#define AON_REG_PAD_REG3X_PAD_P0_DEB_7_Msk                                                                               (0x1UL << AON_REG_PAD_REG3X_PAD_P0_DEB_7_Pos)
+
+#define AON_REG_PAD_REG3X_PAD_P0_RAP_WKEN_7_Pos                                                                          25U
+#define AON_REG_PAD_REG3X_PAD_P0_RAP_WKEN_7_Msk                                                                          (0x1UL << AON_REG_PAD_REG3X_PAD_P0_RAP_WKEN_7_Pos)
+
+#define AON_REG_PAD_REG3X_PAD_P0_PPU_WKEN_7_Pos                                                                          26U
+#define AON_REG_PAD_REG3X_PAD_P0_PPU_WKEN_7_Msk                                                                          (0x1UL << AON_REG_PAD_REG3X_PAD_P0_PPU_WKEN_7_Pos)
+
+#define AON_REG_PAD_REG3X_RESERVED_1_Pos                                                                                 27U
+#define AON_REG_PAD_REG3X_RESERVED_1_Msk                                                                                 (0x1UL << AON_REG_PAD_REG3X_RESERVED_1_Pos)
+
+#define AON_REG_PAD_REG3X_RESERVED_Pos                                                                                   28U
+#define AON_REG_PAD_REG3X_RESERVED_Msk                                                                                   (0x3UL << AON_REG_PAD_REG3X_RESERVED_Pos)
+
+#define AON_REG_PAD_REG3X_PAD_P0_AON_MUX_7_Pos                                                                           30U
+#define AON_REG_PAD_REG3X_PAD_P0_AON_MUX_7_Msk                                                                           (0x3UL << AON_REG_PAD_REG3X_PAD_P0_AON_MUX_7_Pos)
+
+/* 0x130    0x4000_0130
+    0       R/W     PAD_P1_O_0                                                  1'b0
+    1       R/W     PAD_P1_E_0                                                  1'b0
+    2       R/W     PAD_P1_PU_EN_0                                              1'b1
+    3       R/W     AON_PAD_P1_PD_0                                             1'b0
+    4       R/W     PAD_P1_PUPDC_0                                              1'b0
+    5       R/W     PAD_P1_WKEN_0                                               1'b0
+    6       R/W     PAD_P1_WKPOL_0                                              1'b0
+    7       R/W     PAD_P1_SHDN_0                                               1'b1
+    8       R/W     PAD_P1_DEB_0                                                1'b0
+    9       R/W     PAD_P1_RAP_WKEN_0                                           1'b0
+    10      R/W     PAD_P1_PPU_WKEN_0                                           1'b0
+    11      R/W     RESERVED_3                                                  1'b0
+    13:12   R       RESERVED_2                                                  2'b10
+    15:14   R/W     PAD_P1_AON_MUX_0                                            2'b00
+    16      R/W     PAD_P1_O_1                                                  1'b0
+    17      R/W     PAD_P1_E_1                                                  1'b0
+    18      R/W     PAD_P1_PU_EN_1                                              1'b1
+    19      R/W     AON_PAD_P1_PD_1                                             1'b0
+    20      R/W     PAD_P1_PUPDC_1                                              1'b0
+    21      R/W     PAD_P1_WKEN_1                                               1'b0
+    22      R/W     PAD_P1_WKPOL_1                                              1'b0
+    23      R/W     PAD_P1_SHDN_1                                               1'b1
+    24      R/W     PAD_P1_DEB_1                                                1'b0
+    25      R/W     PAD_P1_RAP_WKEN_1                                           1'b0
+    26      R/W     PAD_P1_PPU_WKEN_1                                           1'b0
+    27      R/W     RESERVED_1                                                  1'b0
+    29:28   R       RESERVED                                                    2'b10
+    31:30   R/W     PAD_P1_AON_MUX_1                                            2'b00
+ */
+typedef union _AON_REG_PAD_REG4X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t PAD_P1_O_0: 1;
+        uint32_t PAD_P1_E_0: 1;
+        uint32_t PAD_P1_PU_EN_0: 1;
+        uint32_t AON_PAD_P1_PD_0: 1;
+        uint32_t PAD_P1_PUPDC_0: 1;
+        uint32_t PAD_P1_WKEN_0: 1;
+        uint32_t PAD_P1_WKPOL_0: 1;
+        uint32_t PAD_P1_SHDN_0: 1;
+        uint32_t PAD_P1_DEB_0: 1;
+        uint32_t PAD_P1_RAP_WKEN_0: 1;
+        uint32_t PAD_P1_PPU_WKEN_0: 1;
+        uint32_t RESERVED_3: 1;
+        uint32_t RESERVED_2: 2;
+        uint32_t PAD_P1_AON_MUX_0: 2;
+        uint32_t PAD_P1_O_1: 1;
+        uint32_t PAD_P1_E_1: 1;
+        uint32_t PAD_P1_PU_EN_1: 1;
+        uint32_t AON_PAD_P1_PD_1: 1;
+        uint32_t PAD_P1_PUPDC_1: 1;
+        uint32_t PAD_P1_WKEN_1: 1;
+        uint32_t PAD_P1_WKPOL_1: 1;
+        uint32_t PAD_P1_SHDN_1: 1;
+        uint32_t PAD_P1_DEB_1: 1;
+        uint32_t PAD_P1_RAP_WKEN_1: 1;
+        uint32_t PAD_P1_PPU_WKEN_1: 1;
+        uint32_t RESERVED_1: 1;
+        uint32_t RESERVED: 2;
+        uint32_t PAD_P1_AON_MUX_1: 2;
+    };
+} AON_REG_PAD_REG4X_TYPE;
+
+/*0x4000_0130 AON_REG_PAD_REG4X*/
+#define AON_REG_PAD_REG4X_PAD_P1_O_0_Pos                                                                                 0U
+#define AON_REG_PAD_REG4X_PAD_P1_O_0_Msk                                                                                 (0x1UL << AON_REG_PAD_REG4X_PAD_P1_O_0_Pos)
+
+#define AON_REG_PAD_REG4X_PAD_P1_E_0_Pos                                                                                 1U
+#define AON_REG_PAD_REG4X_PAD_P1_E_0_Msk                                                                                 (0x1UL << AON_REG_PAD_REG4X_PAD_P1_E_0_Pos)
+
+#define AON_REG_PAD_REG4X_PAD_P1_PU_EN_0_Pos                                                                             2U
+#define AON_REG_PAD_REG4X_PAD_P1_PU_EN_0_Msk                                                                             (0x1UL << AON_REG_PAD_REG4X_PAD_P1_PU_EN_0_Pos)
+
+#define AON_REG_PAD_REG4X_AON_PAD_P1_PD_0_Pos                                                                            3U
+#define AON_REG_PAD_REG4X_AON_PAD_P1_PD_0_Msk                                                                            (0x1UL << AON_REG_PAD_REG4X_AON_PAD_P1_PD_0_Pos)
+
+#define AON_REG_PAD_REG4X_PAD_P1_PUPDC_0_Pos                                                                             4U
+#define AON_REG_PAD_REG4X_PAD_P1_PUPDC_0_Msk                                                                             (0x1UL << AON_REG_PAD_REG4X_PAD_P1_PUPDC_0_Pos)
+
+#define AON_REG_PAD_REG4X_PAD_P1_WKEN_0_Pos                                                                              5U
+#define AON_REG_PAD_REG4X_PAD_P1_WKEN_0_Msk                                                                              (0x1UL << AON_REG_PAD_REG4X_PAD_P1_WKEN_0_Pos)
+
+#define AON_REG_PAD_REG4X_PAD_P1_WKPOL_0_Pos                                                                             6U
+#define AON_REG_PAD_REG4X_PAD_P1_WKPOL_0_Msk                                                                             (0x1UL << AON_REG_PAD_REG4X_PAD_P1_WKPOL_0_Pos)
+
+#define AON_REG_PAD_REG4X_PAD_P1_SHDN_0_Pos                                                                              7U
+#define AON_REG_PAD_REG4X_PAD_P1_SHDN_0_Msk                                                                              (0x1UL << AON_REG_PAD_REG4X_PAD_P1_SHDN_0_Pos)
+
+#define AON_REG_PAD_REG4X_PAD_P1_DEB_0_Pos                                                                               8U
+#define AON_REG_PAD_REG4X_PAD_P1_DEB_0_Msk                                                                               (0x1UL << AON_REG_PAD_REG4X_PAD_P1_DEB_0_Pos)
+
+#define AON_REG_PAD_REG4X_PAD_P1_RAP_WKEN_0_Pos                                                                          9U
+#define AON_REG_PAD_REG4X_PAD_P1_RAP_WKEN_0_Msk                                                                          (0x1UL << AON_REG_PAD_REG4X_PAD_P1_RAP_WKEN_0_Pos)
+
+#define AON_REG_PAD_REG4X_PAD_P1_PPU_WKEN_0_Pos                                                                          10U
+#define AON_REG_PAD_REG4X_PAD_P1_PPU_WKEN_0_Msk                                                                          (0x1UL << AON_REG_PAD_REG4X_PAD_P1_PPU_WKEN_0_Pos)
+
+#define AON_REG_PAD_REG4X_RESERVED_3_Pos                                                                                 11U
+#define AON_REG_PAD_REG4X_RESERVED_3_Msk                                                                                 (0x1UL << AON_REG_PAD_REG4X_RESERVED_3_Pos)
+
+#define AON_REG_PAD_REG4X_RESERVED_2_Pos                                                                                 12U
+#define AON_REG_PAD_REG4X_RESERVED_2_Msk                                                                                 (0x3UL << AON_REG_PAD_REG4X_RESERVED_2_Pos)
+
+#define AON_REG_PAD_REG4X_PAD_P1_AON_MUX_0_Pos                                                                           14U
+#define AON_REG_PAD_REG4X_PAD_P1_AON_MUX_0_Msk                                                                           (0x3UL << AON_REG_PAD_REG4X_PAD_P1_AON_MUX_0_Pos)
+
+#define AON_REG_PAD_REG4X_PAD_P1_O_1_Pos                                                                                 16U
+#define AON_REG_PAD_REG4X_PAD_P1_O_1_Msk                                                                                 (0x1UL << AON_REG_PAD_REG4X_PAD_P1_O_1_Pos)
+
+#define AON_REG_PAD_REG4X_PAD_P1_E_1_Pos                                                                                 17U
+#define AON_REG_PAD_REG4X_PAD_P1_E_1_Msk                                                                                 (0x1UL << AON_REG_PAD_REG4X_PAD_P1_E_1_Pos)
+
+#define AON_REG_PAD_REG4X_PAD_P1_PU_EN_1_Pos                                                                             18U
+#define AON_REG_PAD_REG4X_PAD_P1_PU_EN_1_Msk                                                                             (0x1UL << AON_REG_PAD_REG4X_PAD_P1_PU_EN_1_Pos)
+
+#define AON_REG_PAD_REG4X_AON_PAD_P1_PD_1_Pos                                                                            19U
+#define AON_REG_PAD_REG4X_AON_PAD_P1_PD_1_Msk                                                                            (0x1UL << AON_REG_PAD_REG4X_AON_PAD_P1_PD_1_Pos)
+
+#define AON_REG_PAD_REG4X_PAD_P1_PUPDC_1_Pos                                                                             20U
+#define AON_REG_PAD_REG4X_PAD_P1_PUPDC_1_Msk                                                                             (0x1UL << AON_REG_PAD_REG4X_PAD_P1_PUPDC_1_Pos)
+
+#define AON_REG_PAD_REG4X_PAD_P1_WKEN_1_Pos                                                                              21U
+#define AON_REG_PAD_REG4X_PAD_P1_WKEN_1_Msk                                                                              (0x1UL << AON_REG_PAD_REG4X_PAD_P1_WKEN_1_Pos)
+
+#define AON_REG_PAD_REG4X_PAD_P1_WKPOL_1_Pos                                                                             22U
+#define AON_REG_PAD_REG4X_PAD_P1_WKPOL_1_Msk                                                                             (0x1UL << AON_REG_PAD_REG4X_PAD_P1_WKPOL_1_Pos)
+
+#define AON_REG_PAD_REG4X_PAD_P1_SHDN_1_Pos                                                                              23U
+#define AON_REG_PAD_REG4X_PAD_P1_SHDN_1_Msk                                                                              (0x1UL << AON_REG_PAD_REG4X_PAD_P1_SHDN_1_Pos)
+
+#define AON_REG_PAD_REG4X_PAD_P1_DEB_1_Pos                                                                               24U
+#define AON_REG_PAD_REG4X_PAD_P1_DEB_1_Msk                                                                               (0x1UL << AON_REG_PAD_REG4X_PAD_P1_DEB_1_Pos)
+
+#define AON_REG_PAD_REG4X_PAD_P1_RAP_WKEN_1_Pos                                                                          25U
+#define AON_REG_PAD_REG4X_PAD_P1_RAP_WKEN_1_Msk                                                                          (0x1UL << AON_REG_PAD_REG4X_PAD_P1_RAP_WKEN_1_Pos)
+
+#define AON_REG_PAD_REG4X_PAD_P1_PPU_WKEN_1_Pos                                                                          26U
+#define AON_REG_PAD_REG4X_PAD_P1_PPU_WKEN_1_Msk                                                                          (0x1UL << AON_REG_PAD_REG4X_PAD_P1_PPU_WKEN_1_Pos)
+
+#define AON_REG_PAD_REG4X_RESERVED_1_Pos                                                                                 27U
+#define AON_REG_PAD_REG4X_RESERVED_1_Msk                                                                                 (0x1UL << AON_REG_PAD_REG4X_RESERVED_1_Pos)
+
+#define AON_REG_PAD_REG4X_RESERVED_Pos                                                                                   28U
+#define AON_REG_PAD_REG4X_RESERVED_Msk                                                                                   (0x3UL << AON_REG_PAD_REG4X_RESERVED_Pos)
+
+#define AON_REG_PAD_REG4X_PAD_P1_AON_MUX_1_Pos                                                                           30U
+#define AON_REG_PAD_REG4X_PAD_P1_AON_MUX_1_Msk                                                                           (0x3UL << AON_REG_PAD_REG4X_PAD_P1_AON_MUX_1_Pos)
+
+/* 0x134    0x4000_0134
+    0       R/W     PAD_P1_O_6                                                  1'b0
+    1       R/W     PAD_P1_E_6                                                  1'b0
+    2       R/W     PAD_P1_PU_EN_6                                              1'b1
+    3       R/W     AON_PAD_P1_PD_6                                             1'b1
+    4       R/W     PAD_P1_PUPDC_6                                              1'b0
+    5       R/W     PAD_P1_WKEN_6                                               1'b0
+    6       R/W     PAD_P1_WKPOL_6                                              1'b0
+    7       R/W     PAD_P1_SHDN_6                                               1'b1
+    8       R/W     PAD_P1_DEB_6                                                1'b0
+    9       R/W     PAD_P1_RAP_WKEN_6                                           1'b0
+    10      R/W     PAD_P1_PPU_WKEN_6                                           1'b0
+    11      R/W     RESERVED_3                                                  1'b0
+    13:12   R       RESERVED_2                                                  2'b00
+    15:14   R/W     PAD_P1_AON_MUX_6                                            2'b00
+    16      R/W     PAD_P1_O_7                                                  1'b0
+    17      R/W     PAD_P1_E_7                                                  1'b0
+    18      R/W     PAD_P1_PU_EN_7                                              1'b1
+    19      R/W     AON_PAD_P1_PD_7                                             1'b1
+    20      R/W     PAD_P1_PUPDC_7                                              1'b0
+    21      R/W     PAD_P1_WKEN_7                                               1'b0
+    22      R/W     PAD_P1_WKPOL_7                                              1'b0
+    23      R/W     PAD_P1_SHDN_7                                               1'b1
+    24      R/W     PAD_P1_DEB_7                                                1'b0
+    25      R/W     PAD_P1_RAP_WKEN_7                                           1'b0
+    26      R/W     PAD_P1_PPU_WKEN_7                                           1'b0
+    27      R/W     RESERVED_1                                                  1'b0
+    29:28   R       RESERVED                                                    2'b00
+    31:30   R/W     PAD_P1_AON_MUX_7                                            2'b00
+ */
+typedef union _AON_REG_PAD_REG5X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t PAD_P1_O_6: 1;
+        uint32_t PAD_P1_E_6: 1;
+        uint32_t PAD_P1_PU_EN_6: 1;
+        uint32_t AON_PAD_P1_PD_6: 1;
+        uint32_t PAD_P1_PUPDC_6: 1;
+        uint32_t PAD_P1_WKEN_6: 1;
+        uint32_t PAD_P1_WKPOL_6: 1;
+        uint32_t PAD_P1_SHDN_6: 1;
+        uint32_t PAD_P1_DEB_6: 1;
+        uint32_t PAD_P1_RAP_WKEN_6: 1;
+        uint32_t PAD_P1_PPU_WKEN_6: 1;
+        uint32_t RESERVED_3: 1;
+        uint32_t RESERVED_2: 2;
+        uint32_t PAD_P1_AON_MUX_6: 2;
+        uint32_t PAD_P1_O_7: 1;
+        uint32_t PAD_P1_E_7: 1;
+        uint32_t PAD_P1_PU_EN_7: 1;
+        uint32_t AON_PAD_P1_PD_7: 1;
+        uint32_t PAD_P1_PUPDC_7: 1;
+        uint32_t PAD_P1_WKEN_7: 1;
+        uint32_t PAD_P1_WKPOL_7: 1;
+        uint32_t PAD_P1_SHDN_7: 1;
+        uint32_t PAD_P1_DEB_7: 1;
+        uint32_t PAD_P1_RAP_WKEN_7: 1;
+        uint32_t PAD_P1_PPU_WKEN_7: 1;
+        uint32_t RESERVED_1: 1;
+        uint32_t RESERVED: 2;
+        uint32_t PAD_P1_AON_MUX_7: 2;
+    };
+} AON_REG_PAD_REG5X_TYPE;
+
+/*0x4000_0134 AON_REG_PAD_REG5X*/
+#define AON_REG_PAD_REG5X_PAD_P1_O_6_Pos                                                                                 0U
+#define AON_REG_PAD_REG5X_PAD_P1_O_6_Msk                                                                                 (0x1UL << AON_REG_PAD_REG5X_PAD_P1_O_6_Pos)
+
+#define AON_REG_PAD_REG5X_PAD_P1_E_6_Pos                                                                                 1U
+#define AON_REG_PAD_REG5X_PAD_P1_E_6_Msk                                                                                 (0x1UL << AON_REG_PAD_REG5X_PAD_P1_E_6_Pos)
+
+#define AON_REG_PAD_REG5X_PAD_P1_PU_EN_6_Pos                                                                             2U
+#define AON_REG_PAD_REG5X_PAD_P1_PU_EN_6_Msk                                                                             (0x1UL << AON_REG_PAD_REG5X_PAD_P1_PU_EN_6_Pos)
+
+#define AON_REG_PAD_REG5X_AON_PAD_P1_PD_6_Pos                                                                            3U
+#define AON_REG_PAD_REG5X_AON_PAD_P1_PD_6_Msk                                                                            (0x1UL << AON_REG_PAD_REG5X_AON_PAD_P1_PD_6_Pos)
+
+#define AON_REG_PAD_REG5X_PAD_P1_PUPDC_6_Pos                                                                             4U
+#define AON_REG_PAD_REG5X_PAD_P1_PUPDC_6_Msk                                                                             (0x1UL << AON_REG_PAD_REG5X_PAD_P1_PUPDC_6_Pos)
+
+#define AON_REG_PAD_REG5X_PAD_P1_WKEN_6_Pos                                                                              5U
+#define AON_REG_PAD_REG5X_PAD_P1_WKEN_6_Msk                                                                              (0x1UL << AON_REG_PAD_REG5X_PAD_P1_WKEN_6_Pos)
+
+#define AON_REG_PAD_REG5X_PAD_P1_WKPOL_6_Pos                                                                             6U
+#define AON_REG_PAD_REG5X_PAD_P1_WKPOL_6_Msk                                                                             (0x1UL << AON_REG_PAD_REG5X_PAD_P1_WKPOL_6_Pos)
+
+#define AON_REG_PAD_REG5X_PAD_P1_SHDN_6_Pos                                                                              7U
+#define AON_REG_PAD_REG5X_PAD_P1_SHDN_6_Msk                                                                              (0x1UL << AON_REG_PAD_REG5X_PAD_P1_SHDN_6_Pos)
+
+#define AON_REG_PAD_REG5X_PAD_P1_DEB_6_Pos                                                                               8U
+#define AON_REG_PAD_REG5X_PAD_P1_DEB_6_Msk                                                                               (0x1UL << AON_REG_PAD_REG5X_PAD_P1_DEB_6_Pos)
+
+#define AON_REG_PAD_REG5X_PAD_P1_RAP_WKEN_6_Pos                                                                          9U
+#define AON_REG_PAD_REG5X_PAD_P1_RAP_WKEN_6_Msk                                                                          (0x1UL << AON_REG_PAD_REG5X_PAD_P1_RAP_WKEN_6_Pos)
+
+#define AON_REG_PAD_REG5X_PAD_P1_PPU_WKEN_6_Pos                                                                          10U
+#define AON_REG_PAD_REG5X_PAD_P1_PPU_WKEN_6_Msk                                                                          (0x1UL << AON_REG_PAD_REG5X_PAD_P1_PPU_WKEN_6_Pos)
+
+#define AON_REG_PAD_REG5X_RESERVED_3_Pos                                                                                 11U
+#define AON_REG_PAD_REG5X_RESERVED_3_Msk                                                                                 (0x1UL << AON_REG_PAD_REG5X_RESERVED_3_Pos)
+
+#define AON_REG_PAD_REG5X_RESERVED_2_Pos                                                                                 12U
+#define AON_REG_PAD_REG5X_RESERVED_2_Msk                                                                                 (0x3UL << AON_REG_PAD_REG5X_RESERVED_2_Pos)
+
+#define AON_REG_PAD_REG5X_PAD_P1_AON_MUX_6_Pos                                                                           14U
+#define AON_REG_PAD_REG5X_PAD_P1_AON_MUX_6_Msk                                                                           (0x3UL << AON_REG_PAD_REG5X_PAD_P1_AON_MUX_6_Pos)
+
+#define AON_REG_PAD_REG5X_PAD_P1_O_7_Pos                                                                                 16U
+#define AON_REG_PAD_REG5X_PAD_P1_O_7_Msk                                                                                 (0x1UL << AON_REG_PAD_REG5X_PAD_P1_O_7_Pos)
+
+#define AON_REG_PAD_REG5X_PAD_P1_E_7_Pos                                                                                 17U
+#define AON_REG_PAD_REG5X_PAD_P1_E_7_Msk                                                                                 (0x1UL << AON_REG_PAD_REG5X_PAD_P1_E_7_Pos)
+
+#define AON_REG_PAD_REG5X_PAD_P1_PU_EN_7_Pos                                                                             18U
+#define AON_REG_PAD_REG5X_PAD_P1_PU_EN_7_Msk                                                                             (0x1UL << AON_REG_PAD_REG5X_PAD_P1_PU_EN_7_Pos)
+
+#define AON_REG_PAD_REG5X_AON_PAD_P1_PD_7_Pos                                                                            19U
+#define AON_REG_PAD_REG5X_AON_PAD_P1_PD_7_Msk                                                                            (0x1UL << AON_REG_PAD_REG5X_AON_PAD_P1_PD_7_Pos)
+
+#define AON_REG_PAD_REG5X_PAD_P1_PUPDC_7_Pos                                                                             20U
+#define AON_REG_PAD_REG5X_PAD_P1_PUPDC_7_Msk                                                                             (0x1UL << AON_REG_PAD_REG5X_PAD_P1_PUPDC_7_Pos)
+
+#define AON_REG_PAD_REG5X_PAD_P1_WKEN_7_Pos                                                                              21U
+#define AON_REG_PAD_REG5X_PAD_P1_WKEN_7_Msk                                                                              (0x1UL << AON_REG_PAD_REG5X_PAD_P1_WKEN_7_Pos)
+
+#define AON_REG_PAD_REG5X_PAD_P1_WKPOL_7_Pos                                                                             22U
+#define AON_REG_PAD_REG5X_PAD_P1_WKPOL_7_Msk                                                                             (0x1UL << AON_REG_PAD_REG5X_PAD_P1_WKPOL_7_Pos)
+
+#define AON_REG_PAD_REG5X_PAD_P1_SHDN_7_Pos                                                                              23U
+#define AON_REG_PAD_REG5X_PAD_P1_SHDN_7_Msk                                                                              (0x1UL << AON_REG_PAD_REG5X_PAD_P1_SHDN_7_Pos)
+
+#define AON_REG_PAD_REG5X_PAD_P1_DEB_7_Pos                                                                               24U
+#define AON_REG_PAD_REG5X_PAD_P1_DEB_7_Msk                                                                               (0x1UL << AON_REG_PAD_REG5X_PAD_P1_DEB_7_Pos)
+
+#define AON_REG_PAD_REG5X_PAD_P1_RAP_WKEN_7_Pos                                                                          25U
+#define AON_REG_PAD_REG5X_PAD_P1_RAP_WKEN_7_Msk                                                                          (0x1UL << AON_REG_PAD_REG5X_PAD_P1_RAP_WKEN_7_Pos)
+
+#define AON_REG_PAD_REG5X_PAD_P1_PPU_WKEN_7_Pos                                                                          26U
+#define AON_REG_PAD_REG5X_PAD_P1_PPU_WKEN_7_Msk                                                                          (0x1UL << AON_REG_PAD_REG5X_PAD_P1_PPU_WKEN_7_Pos)
+
+#define AON_REG_PAD_REG5X_RESERVED_1_Pos                                                                                 27U
+#define AON_REG_PAD_REG5X_RESERVED_1_Msk                                                                                 (0x1UL << AON_REG_PAD_REG5X_RESERVED_1_Pos)
+
+#define AON_REG_PAD_REG5X_RESERVED_Pos                                                                                   28U
+#define AON_REG_PAD_REG5X_RESERVED_Msk                                                                                   (0x3UL << AON_REG_PAD_REG5X_RESERVED_Pos)
+
+#define AON_REG_PAD_REG5X_PAD_P1_AON_MUX_7_Pos                                                                           30U
+#define AON_REG_PAD_REG5X_PAD_P1_AON_MUX_7_Msk                                                                           (0x3UL << AON_REG_PAD_REG5X_PAD_P1_AON_MUX_7_Pos)
+
+/* 0x138    0x4000_0138
+    0       R/W     PAD_P2_O_0                                                  1'b0
+    1       R/W     PAD_P2_E_0                                                  1'b0
+    2       R/W     PAD_P2_PU_EN_0                                              1'b1
+    3       R/W     AON_PAD_P2_PD_0                                             1'b1
+    4       R/W     PAD_P2_PUPDC_0                                              1'b0
+    5       R/W     PAD_P2_WKEN_0                                               1'b0
+    6       R/W     PAD_P2_WKPOL_0                                              1'b0
+    7       R/W     PAD_P2_SHDN_0                                               1'b1
+    8       R/W     PAD_P2_DEB_0                                                1'b0
+    9       R/W     PAD_P2_RAP_WKEN_0                                           1'b0
+    10      R/W     PAD_P2_PPU_WKEN_0                                           1'b0
+    11      R/W     RESERVED_3                                                  1'b0
+    12      R/W     DUMMY_PAD0                                                  1'b0
+    13      R       RESERVED_2                                                  1'b0
+    15:14   R/W     PAD_P2_AON_MUX_0                                            2'b00
+    16      R/W     PAD_P2_O_1                                                  1'b0
+    17      R/W     PAD_P2_E_1                                                  1'b0
+    18      R/W     PAD_P2_PU_EN_1                                              1'b1
+    19      R/W     AON_PAD_P2_PD_1                                             1'b1
+    20      R/W     PAD_P2_PUPDC_1                                              1'b0
+    21      R/W     PAD_P2_WKEN_1                                               1'b0
+    22      R/W     PAD_P2_WKPOL_1                                              1'b0
+    23      R/W     PAD_P2_SHDN_1                                               1'b1
+    24      R/W     PAD_P2_DEB_1                                                1'b0
+    25      R/W     PAD_P2_RAP_WKEN_1                                           1'b0
+    26      R/W     PAD_P2_PPU_WKEN_1                                           1'b0
+    27      R/W     RESERVED_1                                                  1'b0
+    28      R/W     DUMMY_PAD1                                                  1'b0
+    29      R       RESERVED                                                    1'b0
+    31:30   R/W     PAD_P2_AON_MUX_1                                            2'b00
+ */
+typedef union _AON_REG_PAD_REG6X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t PAD_P2_O_0: 1;
+        uint32_t PAD_P2_E_0: 1;
+        uint32_t PAD_P2_PU_EN_0: 1;
+        uint32_t AON_PAD_P2_PD_0: 1;
+        uint32_t PAD_P2_PUPDC_0: 1;
+        uint32_t PAD_P2_WKEN_0: 1;
+        uint32_t PAD_P2_WKPOL_0: 1;
+        uint32_t PAD_P2_SHDN_0: 1;
+        uint32_t PAD_P2_DEB_0: 1;
+        uint32_t PAD_P2_RAP_WKEN_0: 1;
+        uint32_t PAD_P2_PPU_WKEN_0: 1;
+        uint32_t RESERVED_3: 1;
+        uint32_t DUMMY_PAD0: 1;
+        uint32_t RESERVED_2: 1;
+        uint32_t PAD_P2_AON_MUX_0: 2;
+        uint32_t PAD_P2_O_1: 1;
+        uint32_t PAD_P2_E_1: 1;
+        uint32_t PAD_P2_PU_EN_1: 1;
+        uint32_t AON_PAD_P2_PD_1: 1;
+        uint32_t PAD_P2_PUPDC_1: 1;
+        uint32_t PAD_P2_WKEN_1: 1;
+        uint32_t PAD_P2_WKPOL_1: 1;
+        uint32_t PAD_P2_SHDN_1: 1;
+        uint32_t PAD_P2_DEB_1: 1;
+        uint32_t PAD_P2_RAP_WKEN_1: 1;
+        uint32_t PAD_P2_PPU_WKEN_1: 1;
+        uint32_t RESERVED_1: 1;
+        uint32_t DUMMY_PAD1: 1;
+        uint32_t RESERVED: 1;
+        uint32_t PAD_P2_AON_MUX_1: 2;
+    };
+} AON_REG_PAD_REG6X_TYPE;
+
+/*0x4000_0138 AON_REG_PAD_REG6X*/
+#define AON_REG_PAD_REG6X_PAD_P2_O_0_Pos                                                                                 0U
+#define AON_REG_PAD_REG6X_PAD_P2_O_0_Msk                                                                                 (0x1UL << AON_REG_PAD_REG6X_PAD_P2_O_0_Pos)
+
+#define AON_REG_PAD_REG6X_PAD_P2_E_0_Pos                                                                                 1U
+#define AON_REG_PAD_REG6X_PAD_P2_E_0_Msk                                                                                 (0x1UL << AON_REG_PAD_REG6X_PAD_P2_E_0_Pos)
+
+#define AON_REG_PAD_REG6X_PAD_P2_PU_EN_0_Pos                                                                             2U
+#define AON_REG_PAD_REG6X_PAD_P2_PU_EN_0_Msk                                                                             (0x1UL << AON_REG_PAD_REG6X_PAD_P2_PU_EN_0_Pos)
+
+#define AON_REG_PAD_REG6X_AON_PAD_P2_PD_0_Pos                                                                            3U
+#define AON_REG_PAD_REG6X_AON_PAD_P2_PD_0_Msk                                                                            (0x1UL << AON_REG_PAD_REG6X_AON_PAD_P2_PD_0_Pos)
+
+#define AON_REG_PAD_REG6X_PAD_P2_PUPDC_0_Pos                                                                             4U
+#define AON_REG_PAD_REG6X_PAD_P2_PUPDC_0_Msk                                                                             (0x1UL << AON_REG_PAD_REG6X_PAD_P2_PUPDC_0_Pos)
+
+#define AON_REG_PAD_REG6X_PAD_P2_WKEN_0_Pos                                                                              5U
+#define AON_REG_PAD_REG6X_PAD_P2_WKEN_0_Msk                                                                              (0x1UL << AON_REG_PAD_REG6X_PAD_P2_WKEN_0_Pos)
+
+#define AON_REG_PAD_REG6X_PAD_P2_WKPOL_0_Pos                                                                             6U
+#define AON_REG_PAD_REG6X_PAD_P2_WKPOL_0_Msk                                                                             (0x1UL << AON_REG_PAD_REG6X_PAD_P2_WKPOL_0_Pos)
+
+#define AON_REG_PAD_REG6X_PAD_P2_SHDN_0_Pos                                                                              7U
+#define AON_REG_PAD_REG6X_PAD_P2_SHDN_0_Msk                                                                              (0x1UL << AON_REG_PAD_REG6X_PAD_P2_SHDN_0_Pos)
+
+#define AON_REG_PAD_REG6X_PAD_P2_DEB_0_Pos                                                                               8U
+#define AON_REG_PAD_REG6X_PAD_P2_DEB_0_Msk                                                                               (0x1UL << AON_REG_PAD_REG6X_PAD_P2_DEB_0_Pos)
+
+#define AON_REG_PAD_REG6X_PAD_P2_RAP_WKEN_0_Pos                                                                          9U
+#define AON_REG_PAD_REG6X_PAD_P2_RAP_WKEN_0_Msk                                                                          (0x1UL << AON_REG_PAD_REG6X_PAD_P2_RAP_WKEN_0_Pos)
+
+#define AON_REG_PAD_REG6X_PAD_P2_PPU_WKEN_0_Pos                                                                          10U
+#define AON_REG_PAD_REG6X_PAD_P2_PPU_WKEN_0_Msk                                                                          (0x1UL << AON_REG_PAD_REG6X_PAD_P2_PPU_WKEN_0_Pos)
+
+#define AON_REG_PAD_REG6X_RESERVED_3_Pos                                                                                 11U
+#define AON_REG_PAD_REG6X_RESERVED_3_Msk                                                                                 (0x1UL << AON_REG_PAD_REG6X_RESERVED_3_Pos)
+
+#define AON_REG_PAD_REG6X_DUMMY_PAD0_Pos                                                                                 12U
+#define AON_REG_PAD_REG6X_DUMMY_PAD0_Msk                                                                                 (0x1UL << AON_REG_PAD_REG6X_DUMMY_PAD0_Pos)
+
+#define AON_REG_PAD_REG6X_RESERVED_2_Pos                                                                                 13U
+#define AON_REG_PAD_REG6X_RESERVED_2_Msk                                                                                 (0x1UL << AON_REG_PAD_REG6X_RESERVED_2_Pos)
+
+#define AON_REG_PAD_REG6X_PAD_P2_AON_MUX_0_Pos                                                                           14U
+#define AON_REG_PAD_REG6X_PAD_P2_AON_MUX_0_Msk                                                                           (0x3UL << AON_REG_PAD_REG6X_PAD_P2_AON_MUX_0_Pos)
+
+#define AON_REG_PAD_REG6X_PAD_P2_O_1_Pos                                                                                 16U
+#define AON_REG_PAD_REG6X_PAD_P2_O_1_Msk                                                                                 (0x1UL << AON_REG_PAD_REG6X_PAD_P2_O_1_Pos)
+
+#define AON_REG_PAD_REG6X_PAD_P2_E_1_Pos                                                                                 17U
+#define AON_REG_PAD_REG6X_PAD_P2_E_1_Msk                                                                                 (0x1UL << AON_REG_PAD_REG6X_PAD_P2_E_1_Pos)
+
+#define AON_REG_PAD_REG6X_PAD_P2_PU_EN_1_Pos                                                                             18U
+#define AON_REG_PAD_REG6X_PAD_P2_PU_EN_1_Msk                                                                             (0x1UL << AON_REG_PAD_REG6X_PAD_P2_PU_EN_1_Pos)
+
+#define AON_REG_PAD_REG6X_AON_PAD_P2_PD_1_Pos                                                                            19U
+#define AON_REG_PAD_REG6X_AON_PAD_P2_PD_1_Msk                                                                            (0x1UL << AON_REG_PAD_REG6X_AON_PAD_P2_PD_1_Pos)
+
+#define AON_REG_PAD_REG6X_PAD_P2_PUPDC_1_Pos                                                                             20U
+#define AON_REG_PAD_REG6X_PAD_P2_PUPDC_1_Msk                                                                             (0x1UL << AON_REG_PAD_REG6X_PAD_P2_PUPDC_1_Pos)
+
+#define AON_REG_PAD_REG6X_PAD_P2_WKEN_1_Pos                                                                              21U
+#define AON_REG_PAD_REG6X_PAD_P2_WKEN_1_Msk                                                                              (0x1UL << AON_REG_PAD_REG6X_PAD_P2_WKEN_1_Pos)
+
+#define AON_REG_PAD_REG6X_PAD_P2_WKPOL_1_Pos                                                                             22U
+#define AON_REG_PAD_REG6X_PAD_P2_WKPOL_1_Msk                                                                             (0x1UL << AON_REG_PAD_REG6X_PAD_P2_WKPOL_1_Pos)
+
+#define AON_REG_PAD_REG6X_PAD_P2_SHDN_1_Pos                                                                              23U
+#define AON_REG_PAD_REG6X_PAD_P2_SHDN_1_Msk                                                                              (0x1UL << AON_REG_PAD_REG6X_PAD_P2_SHDN_1_Pos)
+
+#define AON_REG_PAD_REG6X_PAD_P2_DEB_1_Pos                                                                               24U
+#define AON_REG_PAD_REG6X_PAD_P2_DEB_1_Msk                                                                               (0x1UL << AON_REG_PAD_REG6X_PAD_P2_DEB_1_Pos)
+
+#define AON_REG_PAD_REG6X_PAD_P2_RAP_WKEN_1_Pos                                                                          25U
+#define AON_REG_PAD_REG6X_PAD_P2_RAP_WKEN_1_Msk                                                                          (0x1UL << AON_REG_PAD_REG6X_PAD_P2_RAP_WKEN_1_Pos)
+
+#define AON_REG_PAD_REG6X_PAD_P2_PPU_WKEN_1_Pos                                                                          26U
+#define AON_REG_PAD_REG6X_PAD_P2_PPU_WKEN_1_Msk                                                                          (0x1UL << AON_REG_PAD_REG6X_PAD_P2_PPU_WKEN_1_Pos)
+
+#define AON_REG_PAD_REG6X_RESERVED_1_Pos                                                                                 27U
+#define AON_REG_PAD_REG6X_RESERVED_1_Msk                                                                                 (0x1UL << AON_REG_PAD_REG6X_RESERVED_1_Pos)
+
+#define AON_REG_PAD_REG6X_DUMMY_PAD1_Pos                                                                                 28U
+#define AON_REG_PAD_REG6X_DUMMY_PAD1_Msk                                                                                 (0x1UL << AON_REG_PAD_REG6X_DUMMY_PAD1_Pos)
+
+#define AON_REG_PAD_REG6X_RESERVED_Pos                                                                                   29U
+#define AON_REG_PAD_REG6X_RESERVED_Msk                                                                                   (0x1UL << AON_REG_PAD_REG6X_RESERVED_Pos)
+
+#define AON_REG_PAD_REG6X_PAD_P2_AON_MUX_1_Pos                                                                           30U
+#define AON_REG_PAD_REG6X_PAD_P2_AON_MUX_1_Msk                                                                           (0x3UL << AON_REG_PAD_REG6X_PAD_P2_AON_MUX_1_Pos)
+
+/* 0x13C    0x4000_013c
+    0       R/W     PAD_P2_O_2                                                  1'b0
+    1       R/W     PAD_P2_E_2                                                  1'b0
+    2       R/W     PAD_P2_PU_EN_2                                              1'b1
+    3       R/W     AON_PAD_P2_PD_2                                             1'b1
+    4       R/W     PAD_P2_PUPDC_2                                              1'b0
+    5       R/W     PAD_P2_WKEN_2                                               1'b0
+    6       R/W     PAD_P2_WKPOL_2                                              1'b0
+    7       R/W     PAD_P2_SHDN_2                                               1'b1
+    8       R/W     PAD_P2_DEB_2                                                1'b0
+    9       R/W     PAD_P2_RAP_WKEN_2                                           1'b0
+    10      R/W     PAD_P2_PPU_WKEN_2                                           1'b0
+    11      R/W     RESERVED_3                                                  1'b0
+    12      R/W     DUMMY_PAD2                                                  1'b0
+    13      R       RESERVED_2                                                  1'b0
+    15:14   R/W     PAD_P2_AON_MUX_2                                            2'b00
+    16      R/W     PAD_P2_O_3                                                  1'b0
+    17      R/W     PAD_P2_E_3                                                  1'b0
+    18      R/W     PAD_P2_PU_EN_3                                              1'b1
+    19      R/W     AON_PAD_P2_PD_3                                             1'b1
+    20      R/W     PAD_P2_PUPDC_3                                              1'b0
+    21      R/W     PAD_P2_WKEN_3                                               1'b0
+    22      R/W     PAD_P2_WKPOL_3                                              1'b0
+    23      R/W     PAD_P2_SHDN_3                                               1'b1
+    24      R/W     PAD_P2_DEB_3                                                1'b0
+    25      R/W     PAD_P2_RAP_WKEN_3                                           1'b0
+    26      R/W     PAD_P2_PPU_WKEN_3                                           1'b0
+    27      R/W     RESERVED_1                                                  1'b0
+    28      R/W     DUMMY_PAD3                                                  1'b0
+    29      R       RESERVED                                                    1'b0
+    31:30   R/W     PAD_P2_AON_MUX_3                                            2'b00
+ */
+typedef union _AON_REG_PAD_REG7X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t PAD_P2_O_2: 1;
+        uint32_t PAD_P2_E_2: 1;
+        uint32_t PAD_P2_PU_EN_2: 1;
+        uint32_t AON_PAD_P2_PD_2: 1;
+        uint32_t PAD_P2_PUPDC_2: 1;
+        uint32_t PAD_P2_WKEN_2: 1;
+        uint32_t PAD_P2_WKPOL_2: 1;
+        uint32_t PAD_P2_SHDN_2: 1;
+        uint32_t PAD_P2_DEB_2: 1;
+        uint32_t PAD_P2_RAP_WKEN_2: 1;
+        uint32_t PAD_P2_PPU_WKEN_2: 1;
+        uint32_t RESERVED_3: 1;
+        uint32_t DUMMY_PAD2: 1;
+        uint32_t RESERVED_2: 1;
+        uint32_t PAD_P2_AON_MUX_2: 2;
+        uint32_t PAD_P2_O_3: 1;
+        uint32_t PAD_P2_E_3: 1;
+        uint32_t PAD_P2_PU_EN_3: 1;
+        uint32_t AON_PAD_P2_PD_3: 1;
+        uint32_t PAD_P2_PUPDC_3: 1;
+        uint32_t PAD_P2_WKEN_3: 1;
+        uint32_t PAD_P2_WKPOL_3: 1;
+        uint32_t PAD_P2_SHDN_3: 1;
+        uint32_t PAD_P2_DEB_3: 1;
+        uint32_t PAD_P2_RAP_WKEN_3: 1;
+        uint32_t PAD_P2_PPU_WKEN_3: 1;
+        uint32_t RESERVED_1: 1;
+        uint32_t DUMMY_PAD3: 1;
+        uint32_t RESERVED: 1;
+        uint32_t PAD_P2_AON_MUX_3: 2;
+    };
+} AON_REG_PAD_REG7X_TYPE;
+
+/*0x4000_013c AON_REG_PAD_REG7X*/
+#define AON_REG_PAD_REG7X_PAD_P2_O_2_Pos                                                                                 0U
+#define AON_REG_PAD_REG7X_PAD_P2_O_2_Msk                                                                                 (0x1UL << AON_REG_PAD_REG7X_PAD_P2_O_2_Pos)
+
+#define AON_REG_PAD_REG7X_PAD_P2_E_2_Pos                                                                                 1U
+#define AON_REG_PAD_REG7X_PAD_P2_E_2_Msk                                                                                 (0x1UL << AON_REG_PAD_REG7X_PAD_P2_E_2_Pos)
+
+#define AON_REG_PAD_REG7X_PAD_P2_PU_EN_2_Pos                                                                             2U
+#define AON_REG_PAD_REG7X_PAD_P2_PU_EN_2_Msk                                                                             (0x1UL << AON_REG_PAD_REG7X_PAD_P2_PU_EN_2_Pos)
+
+#define AON_REG_PAD_REG7X_AON_PAD_P2_PD_2_Pos                                                                            3U
+#define AON_REG_PAD_REG7X_AON_PAD_P2_PD_2_Msk                                                                            (0x1UL << AON_REG_PAD_REG7X_AON_PAD_P2_PD_2_Pos)
+
+#define AON_REG_PAD_REG7X_PAD_P2_PUPDC_2_Pos                                                                             4U
+#define AON_REG_PAD_REG7X_PAD_P2_PUPDC_2_Msk                                                                             (0x1UL << AON_REG_PAD_REG7X_PAD_P2_PUPDC_2_Pos)
+
+#define AON_REG_PAD_REG7X_PAD_P2_WKEN_2_Pos                                                                              5U
+#define AON_REG_PAD_REG7X_PAD_P2_WKEN_2_Msk                                                                              (0x1UL << AON_REG_PAD_REG7X_PAD_P2_WKEN_2_Pos)
+
+#define AON_REG_PAD_REG7X_PAD_P2_WKPOL_2_Pos                                                                             6U
+#define AON_REG_PAD_REG7X_PAD_P2_WKPOL_2_Msk                                                                             (0x1UL << AON_REG_PAD_REG7X_PAD_P2_WKPOL_2_Pos)
+
+#define AON_REG_PAD_REG7X_PAD_P2_SHDN_2_Pos                                                                              7U
+#define AON_REG_PAD_REG7X_PAD_P2_SHDN_2_Msk                                                                              (0x1UL << AON_REG_PAD_REG7X_PAD_P2_SHDN_2_Pos)
+
+#define AON_REG_PAD_REG7X_PAD_P2_DEB_2_Pos                                                                               8U
+#define AON_REG_PAD_REG7X_PAD_P2_DEB_2_Msk                                                                               (0x1UL << AON_REG_PAD_REG7X_PAD_P2_DEB_2_Pos)
+
+#define AON_REG_PAD_REG7X_PAD_P2_RAP_WKEN_2_Pos                                                                          9U
+#define AON_REG_PAD_REG7X_PAD_P2_RAP_WKEN_2_Msk                                                                          (0x1UL << AON_REG_PAD_REG7X_PAD_P2_RAP_WKEN_2_Pos)
+
+#define AON_REG_PAD_REG7X_PAD_P2_PPU_WKEN_2_Pos                                                                          10U
+#define AON_REG_PAD_REG7X_PAD_P2_PPU_WKEN_2_Msk                                                                          (0x1UL << AON_REG_PAD_REG7X_PAD_P2_PPU_WKEN_2_Pos)
+
+#define AON_REG_PAD_REG7X_RESERVED_3_Pos                                                                                 11U
+#define AON_REG_PAD_REG7X_RESERVED_3_Msk                                                                                 (0x1UL << AON_REG_PAD_REG7X_RESERVED_3_Pos)
+
+#define AON_REG_PAD_REG7X_DUMMY_PAD2_Pos                                                                                 12U
+#define AON_REG_PAD_REG7X_DUMMY_PAD2_Msk                                                                                 (0x1UL << AON_REG_PAD_REG7X_DUMMY_PAD2_Pos)
+
+#define AON_REG_PAD_REG7X_RESERVED_2_Pos                                                                                 13U
+#define AON_REG_PAD_REG7X_RESERVED_2_Msk                                                                                 (0x1UL << AON_REG_PAD_REG7X_RESERVED_2_Pos)
+
+#define AON_REG_PAD_REG7X_PAD_P2_AON_MUX_2_Pos                                                                           14U
+#define AON_REG_PAD_REG7X_PAD_P2_AON_MUX_2_Msk                                                                           (0x3UL << AON_REG_PAD_REG7X_PAD_P2_AON_MUX_2_Pos)
+
+#define AON_REG_PAD_REG7X_PAD_P2_O_3_Pos                                                                                 16U
+#define AON_REG_PAD_REG7X_PAD_P2_O_3_Msk                                                                                 (0x1UL << AON_REG_PAD_REG7X_PAD_P2_O_3_Pos)
+
+#define AON_REG_PAD_REG7X_PAD_P2_E_3_Pos                                                                                 17U
+#define AON_REG_PAD_REG7X_PAD_P2_E_3_Msk                                                                                 (0x1UL << AON_REG_PAD_REG7X_PAD_P2_E_3_Pos)
+
+#define AON_REG_PAD_REG7X_PAD_P2_PU_EN_3_Pos                                                                             18U
+#define AON_REG_PAD_REG7X_PAD_P2_PU_EN_3_Msk                                                                             (0x1UL << AON_REG_PAD_REG7X_PAD_P2_PU_EN_3_Pos)
+
+#define AON_REG_PAD_REG7X_AON_PAD_P2_PD_3_Pos                                                                            19U
+#define AON_REG_PAD_REG7X_AON_PAD_P2_PD_3_Msk                                                                            (0x1UL << AON_REG_PAD_REG7X_AON_PAD_P2_PD_3_Pos)
+
+#define AON_REG_PAD_REG7X_PAD_P2_PUPDC_3_Pos                                                                             20U
+#define AON_REG_PAD_REG7X_PAD_P2_PUPDC_3_Msk                                                                             (0x1UL << AON_REG_PAD_REG7X_PAD_P2_PUPDC_3_Pos)
+
+#define AON_REG_PAD_REG7X_PAD_P2_WKEN_3_Pos                                                                              21U
+#define AON_REG_PAD_REG7X_PAD_P2_WKEN_3_Msk                                                                              (0x1UL << AON_REG_PAD_REG7X_PAD_P2_WKEN_3_Pos)
+
+#define AON_REG_PAD_REG7X_PAD_P2_WKPOL_3_Pos                                                                             22U
+#define AON_REG_PAD_REG7X_PAD_P2_WKPOL_3_Msk                                                                             (0x1UL << AON_REG_PAD_REG7X_PAD_P2_WKPOL_3_Pos)
+
+#define AON_REG_PAD_REG7X_PAD_P2_SHDN_3_Pos                                                                              23U
+#define AON_REG_PAD_REG7X_PAD_P2_SHDN_3_Msk                                                                              (0x1UL << AON_REG_PAD_REG7X_PAD_P2_SHDN_3_Pos)
+
+#define AON_REG_PAD_REG7X_PAD_P2_DEB_3_Pos                                                                               24U
+#define AON_REG_PAD_REG7X_PAD_P2_DEB_3_Msk                                                                               (0x1UL << AON_REG_PAD_REG7X_PAD_P2_DEB_3_Pos)
+
+#define AON_REG_PAD_REG7X_PAD_P2_RAP_WKEN_3_Pos                                                                          25U
+#define AON_REG_PAD_REG7X_PAD_P2_RAP_WKEN_3_Msk                                                                          (0x1UL << AON_REG_PAD_REG7X_PAD_P2_RAP_WKEN_3_Pos)
+
+#define AON_REG_PAD_REG7X_PAD_P2_PPU_WKEN_3_Pos                                                                          26U
+#define AON_REG_PAD_REG7X_PAD_P2_PPU_WKEN_3_Msk                                                                          (0x1UL << AON_REG_PAD_REG7X_PAD_P2_PPU_WKEN_3_Pos)
+
+#define AON_REG_PAD_REG7X_RESERVED_1_Pos                                                                                 27U
+#define AON_REG_PAD_REG7X_RESERVED_1_Msk                                                                                 (0x1UL << AON_REG_PAD_REG7X_RESERVED_1_Pos)
+
+#define AON_REG_PAD_REG7X_DUMMY_PAD3_Pos                                                                                 28U
+#define AON_REG_PAD_REG7X_DUMMY_PAD3_Msk                                                                                 (0x1UL << AON_REG_PAD_REG7X_DUMMY_PAD3_Pos)
+
+#define AON_REG_PAD_REG7X_RESERVED_Pos                                                                                   29U
+#define AON_REG_PAD_REG7X_RESERVED_Msk                                                                                   (0x1UL << AON_REG_PAD_REG7X_RESERVED_Pos)
+
+#define AON_REG_PAD_REG7X_PAD_P2_AON_MUX_3_Pos                                                                           30U
+#define AON_REG_PAD_REG7X_PAD_P2_AON_MUX_3_Msk                                                                           (0x3UL << AON_REG_PAD_REG7X_PAD_P2_AON_MUX_3_Pos)
+
+/* 0x140    0x4000_0140
+    0       R/W     PAD_P2_O_4                                                  1'b0
+    1       R/W     PAD_P2_E_4                                                  1'b0
+    2       R/W     PAD_P2_PU_EN_4                                              1'b1
+    3       R/W     AON_PAD_P2_PD_4                                             1'b1
+    4       R/W     PAD_P2_PUPDC_4                                              1'b0
+    5       R/W     PAD_P2_WKEN_4                                               1'b0
+    6       R/W     PAD_P2_WKPOL_4                                              1'b0
+    7       R/W     PAD_P2_SHDN_4                                               1'b1
+    8       R/W     PAD_P2_DEB_4                                                1'b0
+    9       R/W     PAD_P2_RAP_WKEN_4                                           1'b0
+    10      R/W     PAD_P2_PPU_WKEN_4                                           1'b0
+    11      R/W     RESERVED_3                                                  1'b0
+    12      R/W     DUMMY_PAD4                                                  1'b0
+    13      R       RESERVED_2                                                  1'b0
+    15:14   R/W     PAD_P2_AON_MUX_4                                            2'b00
+    16      R/W     PAD_P2_O_5                                                  1'b0
+    17      R/W     PAD_P2_E_5                                                  1'b0
+    18      R/W     PAD_P2_PU_EN_5                                              1'b1
+    19      R/W     AON_PAD_P2_PD_5                                             1'b1
+    20      R/W     PAD_P2_PUPDC_5                                              1'b0
+    21      R/W     PAD_P2_WKEN_5                                               1'b0
+    22      R/W     PAD_P2_WKPOL_5                                              1'b0
+    23      R/W     PAD_P2_SHDN_5                                               1'b1
+    24      R/W     PAD_P2_DEB_5                                                1'b0
+    25      R/W     PAD_P2_RAP_WKEN_5                                           1'b0
+    26      R/W     PAD_P2_PPU_WKEN_5                                           1'b0
+    27      R/W     RESERVED_1                                                  1'b0
+    28      R/W     DUMMY_PAD5                                                  1'b0
+    29      R       RESERVED                                                    1'b0
+    31:30   R/W     PAD_P2_AON_MUX_5                                            2'b00
+ */
+typedef union _AON_REG_PAD_REG8X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t PAD_P2_O_4: 1;
+        uint32_t PAD_P2_E_4: 1;
+        uint32_t PAD_P2_PU_EN_4: 1;
+        uint32_t AON_PAD_P2_PD_4: 1;
+        uint32_t PAD_P2_PUPDC_4: 1;
+        uint32_t PAD_P2_WKEN_4: 1;
+        uint32_t PAD_P2_WKPOL_4: 1;
+        uint32_t PAD_P2_SHDN_4: 1;
+        uint32_t PAD_P2_DEB_4: 1;
+        uint32_t PAD_P2_RAP_WKEN_4: 1;
+        uint32_t PAD_P2_PPU_WKEN_4: 1;
+        uint32_t RESERVED_3: 1;
+        uint32_t DUMMY_PAD4: 1;
+        uint32_t RESERVED_2: 1;
+        uint32_t PAD_P2_AON_MUX_4: 2;
+        uint32_t PAD_P2_O_5: 1;
+        uint32_t PAD_P2_E_5: 1;
+        uint32_t PAD_P2_PU_EN_5: 1;
+        uint32_t AON_PAD_P2_PD_5: 1;
+        uint32_t PAD_P2_PUPDC_5: 1;
+        uint32_t PAD_P2_WKEN_5: 1;
+        uint32_t PAD_P2_WKPOL_5: 1;
+        uint32_t PAD_P2_SHDN_5: 1;
+        uint32_t PAD_P2_DEB_5: 1;
+        uint32_t PAD_P2_RAP_WKEN_5: 1;
+        uint32_t PAD_P2_PPU_WKEN_5: 1;
+        uint32_t RESERVED_1: 1;
+        uint32_t DUMMY_PAD5: 1;
+        uint32_t RESERVED: 1;
+        uint32_t PAD_P2_AON_MUX_5: 2;
+    };
+} AON_REG_PAD_REG8X_TYPE;
+
+/*0x4000_0140 AON_REG_PAD_REG8X*/
+#define AON_REG_PAD_REG8X_PAD_P2_O_4_Pos                                                                                 0U
+#define AON_REG_PAD_REG8X_PAD_P2_O_4_Msk                                                                                 (0x1UL << AON_REG_PAD_REG8X_PAD_P2_O_4_Pos)
+
+#define AON_REG_PAD_REG8X_PAD_P2_E_4_Pos                                                                                 1U
+#define AON_REG_PAD_REG8X_PAD_P2_E_4_Msk                                                                                 (0x1UL << AON_REG_PAD_REG8X_PAD_P2_E_4_Pos)
+
+#define AON_REG_PAD_REG8X_PAD_P2_PU_EN_4_Pos                                                                             2U
+#define AON_REG_PAD_REG8X_PAD_P2_PU_EN_4_Msk                                                                             (0x1UL << AON_REG_PAD_REG8X_PAD_P2_PU_EN_4_Pos)
+
+#define AON_REG_PAD_REG8X_AON_PAD_P2_PD_4_Pos                                                                            3U
+#define AON_REG_PAD_REG8X_AON_PAD_P2_PD_4_Msk                                                                            (0x1UL << AON_REG_PAD_REG8X_AON_PAD_P2_PD_4_Pos)
+
+#define AON_REG_PAD_REG8X_PAD_P2_PUPDC_4_Pos                                                                             4U
+#define AON_REG_PAD_REG8X_PAD_P2_PUPDC_4_Msk                                                                             (0x1UL << AON_REG_PAD_REG8X_PAD_P2_PUPDC_4_Pos)
+
+#define AON_REG_PAD_REG8X_PAD_P2_WKEN_4_Pos                                                                              5U
+#define AON_REG_PAD_REG8X_PAD_P2_WKEN_4_Msk                                                                              (0x1UL << AON_REG_PAD_REG8X_PAD_P2_WKEN_4_Pos)
+
+#define AON_REG_PAD_REG8X_PAD_P2_WKPOL_4_Pos                                                                             6U
+#define AON_REG_PAD_REG8X_PAD_P2_WKPOL_4_Msk                                                                             (0x1UL << AON_REG_PAD_REG8X_PAD_P2_WKPOL_4_Pos)
+
+#define AON_REG_PAD_REG8X_PAD_P2_SHDN_4_Pos                                                                              7U
+#define AON_REG_PAD_REG8X_PAD_P2_SHDN_4_Msk                                                                              (0x1UL << AON_REG_PAD_REG8X_PAD_P2_SHDN_4_Pos)
+
+#define AON_REG_PAD_REG8X_PAD_P2_DEB_4_Pos                                                                               8U
+#define AON_REG_PAD_REG8X_PAD_P2_DEB_4_Msk                                                                               (0x1UL << AON_REG_PAD_REG8X_PAD_P2_DEB_4_Pos)
+
+#define AON_REG_PAD_REG8X_PAD_P2_RAP_WKEN_4_Pos                                                                          9U
+#define AON_REG_PAD_REG8X_PAD_P2_RAP_WKEN_4_Msk                                                                          (0x1UL << AON_REG_PAD_REG8X_PAD_P2_RAP_WKEN_4_Pos)
+
+#define AON_REG_PAD_REG8X_PAD_P2_PPU_WKEN_4_Pos                                                                          10U
+#define AON_REG_PAD_REG8X_PAD_P2_PPU_WKEN_4_Msk                                                                          (0x1UL << AON_REG_PAD_REG8X_PAD_P2_PPU_WKEN_4_Pos)
+
+#define AON_REG_PAD_REG8X_RESERVED_3_Pos                                                                                 11U
+#define AON_REG_PAD_REG8X_RESERVED_3_Msk                                                                                 (0x1UL << AON_REG_PAD_REG8X_RESERVED_3_Pos)
+
+#define AON_REG_PAD_REG8X_DUMMY_PAD4_Pos                                                                                 12U
+#define AON_REG_PAD_REG8X_DUMMY_PAD4_Msk                                                                                 (0x1UL << AON_REG_PAD_REG8X_DUMMY_PAD4_Pos)
+
+#define AON_REG_PAD_REG8X_RESERVED_2_Pos                                                                                 13U
+#define AON_REG_PAD_REG8X_RESERVED_2_Msk                                                                                 (0x1UL << AON_REG_PAD_REG8X_RESERVED_2_Pos)
+
+#define AON_REG_PAD_REG8X_PAD_P2_AON_MUX_4_Pos                                                                           14U
+#define AON_REG_PAD_REG8X_PAD_P2_AON_MUX_4_Msk                                                                           (0x3UL << AON_REG_PAD_REG8X_PAD_P2_AON_MUX_4_Pos)
+
+#define AON_REG_PAD_REG8X_PAD_P2_O_5_Pos                                                                                 16U
+#define AON_REG_PAD_REG8X_PAD_P2_O_5_Msk                                                                                 (0x1UL << AON_REG_PAD_REG8X_PAD_P2_O_5_Pos)
+
+#define AON_REG_PAD_REG8X_PAD_P2_E_5_Pos                                                                                 17U
+#define AON_REG_PAD_REG8X_PAD_P2_E_5_Msk                                                                                 (0x1UL << AON_REG_PAD_REG8X_PAD_P2_E_5_Pos)
+
+#define AON_REG_PAD_REG8X_PAD_P2_PU_EN_5_Pos                                                                             18U
+#define AON_REG_PAD_REG8X_PAD_P2_PU_EN_5_Msk                                                                             (0x1UL << AON_REG_PAD_REG8X_PAD_P2_PU_EN_5_Pos)
+
+#define AON_REG_PAD_REG8X_AON_PAD_P2_PD_5_Pos                                                                            19U
+#define AON_REG_PAD_REG8X_AON_PAD_P2_PD_5_Msk                                                                            (0x1UL << AON_REG_PAD_REG8X_AON_PAD_P2_PD_5_Pos)
+
+#define AON_REG_PAD_REG8X_PAD_P2_PUPDC_5_Pos                                                                             20U
+#define AON_REG_PAD_REG8X_PAD_P2_PUPDC_5_Msk                                                                             (0x1UL << AON_REG_PAD_REG8X_PAD_P2_PUPDC_5_Pos)
+
+#define AON_REG_PAD_REG8X_PAD_P2_WKEN_5_Pos                                                                              21U
+#define AON_REG_PAD_REG8X_PAD_P2_WKEN_5_Msk                                                                              (0x1UL << AON_REG_PAD_REG8X_PAD_P2_WKEN_5_Pos)
+
+#define AON_REG_PAD_REG8X_PAD_P2_WKPOL_5_Pos                                                                             22U
+#define AON_REG_PAD_REG8X_PAD_P2_WKPOL_5_Msk                                                                             (0x1UL << AON_REG_PAD_REG8X_PAD_P2_WKPOL_5_Pos)
+
+#define AON_REG_PAD_REG8X_PAD_P2_SHDN_5_Pos                                                                              23U
+#define AON_REG_PAD_REG8X_PAD_P2_SHDN_5_Msk                                                                              (0x1UL << AON_REG_PAD_REG8X_PAD_P2_SHDN_5_Pos)
+
+#define AON_REG_PAD_REG8X_PAD_P2_DEB_5_Pos                                                                               24U
+#define AON_REG_PAD_REG8X_PAD_P2_DEB_5_Msk                                                                               (0x1UL << AON_REG_PAD_REG8X_PAD_P2_DEB_5_Pos)
+
+#define AON_REG_PAD_REG8X_PAD_P2_RAP_WKEN_5_Pos                                                                          25U
+#define AON_REG_PAD_REG8X_PAD_P2_RAP_WKEN_5_Msk                                                                          (0x1UL << AON_REG_PAD_REG8X_PAD_P2_RAP_WKEN_5_Pos)
+
+#define AON_REG_PAD_REG8X_PAD_P2_PPU_WKEN_5_Pos                                                                          26U
+#define AON_REG_PAD_REG8X_PAD_P2_PPU_WKEN_5_Msk                                                                          (0x1UL << AON_REG_PAD_REG8X_PAD_P2_PPU_WKEN_5_Pos)
+
+#define AON_REG_PAD_REG8X_RESERVED_1_Pos                                                                                 27U
+#define AON_REG_PAD_REG8X_RESERVED_1_Msk                                                                                 (0x1UL << AON_REG_PAD_REG8X_RESERVED_1_Pos)
+
+#define AON_REG_PAD_REG8X_DUMMY_PAD5_Pos                                                                                 28U
+#define AON_REG_PAD_REG8X_DUMMY_PAD5_Msk                                                                                 (0x1UL << AON_REG_PAD_REG8X_DUMMY_PAD5_Pos)
+
+#define AON_REG_PAD_REG8X_RESERVED_Pos                                                                                   29U
+#define AON_REG_PAD_REG8X_RESERVED_Msk                                                                                   (0x1UL << AON_REG_PAD_REG8X_RESERVED_Pos)
+
+#define AON_REG_PAD_REG8X_PAD_P2_AON_MUX_5_Pos                                                                           30U
+#define AON_REG_PAD_REG8X_PAD_P2_AON_MUX_5_Msk                                                                           (0x3UL << AON_REG_PAD_REG8X_PAD_P2_AON_MUX_5_Pos)
+
+/* 0x144    0x4000_0144
+    0       R/W     PAD_P2_O_6                                                  1'b0
+    1       R/W     PAD_P2_E_6                                                  1'b0
+    2       R/W     PAD_P2_PU_EN_6                                              1'b1
+    3       R/W     AON_PAD_P2_PD_6                                             1'b1
+    4       R/W     PAD_P2_PUPDC_6                                              1'b0
+    5       R/W     PAD_P2_WKEN_6                                               1'b0
+    6       R/W     PAD_P2_WKPOL_6                                              1'b0
+    7       R/W     PAD_P2_SHDN_6                                               1'b1
+    8       R/W     PAD_P2_DEB_6                                                1'b0
+    9       R/W     PAD_P2_RAP_WKEN_6                                           1'b0
+    10      R/W     PAD_P2_PPU_WKEN_6                                           1'b0
+    11      R/W     RESERVED_3                                                  1'b0
+    12      R/W     DUMMY_PAD6                                                  1'b0
+    13      R       RESERVED_2                                                  1'b0
+    15:14   R/W     PAD_P2_AON_MUX_6                                            2'b00
+    16      R/W     PAD_P2_O_7                                                  1'b0
+    17      R/W     PAD_P2_E_7                                                  1'b0
+    18      R/W     PAD_P2_PU_EN_7                                              1'b1
+    19      R/W     AON_PAD_P2_PD_7                                             1'b1
+    20      R/W     PAD_P2_PUPDC_7                                              1'b0
+    21      R/W     PAD_P2_WKEN_7                                               1'b0
+    22      R/W     PAD_P2_WKPOL_7                                              1'b0
+    23      R/W     PAD_P2_SHDN_7                                               1'b1
+    24      R/W     PAD_P2_DEB_7                                                1'b0
+    25      R/W     PAD_P2_RAP_WKEN_7                                           1'b0
+    26      R/W     PAD_P2_PPU_WKEN_7                                           1'b0
+    27      R/W     RESERVED_1                                                  1'b0
+    28      R/W     DUMMY_PAD7                                                  1'b0
+    29      R       RESERVED                                                    1'b0
+    31:30   R/W     PAD_P2_AON_MUX_7                                            2'b00
+ */
+typedef union _AON_REG_PAD_REG9X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t PAD_P2_O_6: 1;
+        uint32_t PAD_P2_E_6: 1;
+        uint32_t PAD_P2_PU_EN_6: 1;
+        uint32_t AON_PAD_P2_PD_6: 1;
+        uint32_t PAD_P2_PUPDC_6: 1;
+        uint32_t PAD_P2_WKEN_6: 1;
+        uint32_t PAD_P2_WKPOL_6: 1;
+        uint32_t PAD_P2_SHDN_6: 1;
+        uint32_t PAD_P2_DEB_6: 1;
+        uint32_t PAD_P2_RAP_WKEN_6: 1;
+        uint32_t PAD_P2_PPU_WKEN_6: 1;
+        uint32_t RESERVED_3: 1;
+        uint32_t DUMMY_PAD6: 1;
+        uint32_t RESERVED_2: 1;
+        uint32_t PAD_P2_AON_MUX_6: 2;
+        uint32_t PAD_P2_O_7: 1;
+        uint32_t PAD_P2_E_7: 1;
+        uint32_t PAD_P2_PU_EN_7: 1;
+        uint32_t AON_PAD_P2_PD_7: 1;
+        uint32_t PAD_P2_PUPDC_7: 1;
+        uint32_t PAD_P2_WKEN_7: 1;
+        uint32_t PAD_P2_WKPOL_7: 1;
+        uint32_t PAD_P2_SHDN_7: 1;
+        uint32_t PAD_P2_DEB_7: 1;
+        uint32_t PAD_P2_RAP_WKEN_7: 1;
+        uint32_t PAD_P2_PPU_WKEN_7: 1;
+        uint32_t RESERVED_1: 1;
+        uint32_t DUMMY_PAD7: 1;
+        uint32_t RESERVED: 1;
+        uint32_t PAD_P2_AON_MUX_7: 2;
+    };
+} AON_REG_PAD_REG9X_TYPE;
+
+/*0x4000_0144 AON_REG_PAD_REG9X*/
+#define AON_REG_PAD_REG9X_PAD_P2_O_6_Pos                                                                                 0U
+#define AON_REG_PAD_REG9X_PAD_P2_O_6_Msk                                                                                 (0x1UL << AON_REG_PAD_REG9X_PAD_P2_O_6_Pos)
+
+#define AON_REG_PAD_REG9X_PAD_P2_E_6_Pos                                                                                 1U
+#define AON_REG_PAD_REG9X_PAD_P2_E_6_Msk                                                                                 (0x1UL << AON_REG_PAD_REG9X_PAD_P2_E_6_Pos)
+
+#define AON_REG_PAD_REG9X_PAD_P2_PU_EN_6_Pos                                                                             2U
+#define AON_REG_PAD_REG9X_PAD_P2_PU_EN_6_Msk                                                                             (0x1UL << AON_REG_PAD_REG9X_PAD_P2_PU_EN_6_Pos)
+
+#define AON_REG_PAD_REG9X_AON_PAD_P2_PD_6_Pos                                                                            3U
+#define AON_REG_PAD_REG9X_AON_PAD_P2_PD_6_Msk                                                                            (0x1UL << AON_REG_PAD_REG9X_AON_PAD_P2_PD_6_Pos)
+
+#define AON_REG_PAD_REG9X_PAD_P2_PUPDC_6_Pos                                                                             4U
+#define AON_REG_PAD_REG9X_PAD_P2_PUPDC_6_Msk                                                                             (0x1UL << AON_REG_PAD_REG9X_PAD_P2_PUPDC_6_Pos)
+
+#define AON_REG_PAD_REG9X_PAD_P2_WKEN_6_Pos                                                                              5U
+#define AON_REG_PAD_REG9X_PAD_P2_WKEN_6_Msk                                                                              (0x1UL << AON_REG_PAD_REG9X_PAD_P2_WKEN_6_Pos)
+
+#define AON_REG_PAD_REG9X_PAD_P2_WKPOL_6_Pos                                                                             6U
+#define AON_REG_PAD_REG9X_PAD_P2_WKPOL_6_Msk                                                                             (0x1UL << AON_REG_PAD_REG9X_PAD_P2_WKPOL_6_Pos)
+
+#define AON_REG_PAD_REG9X_PAD_P2_SHDN_6_Pos                                                                              7U
+#define AON_REG_PAD_REG9X_PAD_P2_SHDN_6_Msk                                                                              (0x1UL << AON_REG_PAD_REG9X_PAD_P2_SHDN_6_Pos)
+
+#define AON_REG_PAD_REG9X_PAD_P2_DEB_6_Pos                                                                               8U
+#define AON_REG_PAD_REG9X_PAD_P2_DEB_6_Msk                                                                               (0x1UL << AON_REG_PAD_REG9X_PAD_P2_DEB_6_Pos)
+
+#define AON_REG_PAD_REG9X_PAD_P2_RAP_WKEN_6_Pos                                                                          9U
+#define AON_REG_PAD_REG9X_PAD_P2_RAP_WKEN_6_Msk                                                                          (0x1UL << AON_REG_PAD_REG9X_PAD_P2_RAP_WKEN_6_Pos)
+
+#define AON_REG_PAD_REG9X_PAD_P2_PPU_WKEN_6_Pos                                                                          10U
+#define AON_REG_PAD_REG9X_PAD_P2_PPU_WKEN_6_Msk                                                                          (0x1UL << AON_REG_PAD_REG9X_PAD_P2_PPU_WKEN_6_Pos)
+
+#define AON_REG_PAD_REG9X_RESERVED_3_Pos                                                                                 11U
+#define AON_REG_PAD_REG9X_RESERVED_3_Msk                                                                                 (0x1UL << AON_REG_PAD_REG9X_RESERVED_3_Pos)
+
+#define AON_REG_PAD_REG9X_DUMMY_PAD6_Pos                                                                                 12U
+#define AON_REG_PAD_REG9X_DUMMY_PAD6_Msk                                                                                 (0x1UL << AON_REG_PAD_REG9X_DUMMY_PAD6_Pos)
+
+#define AON_REG_PAD_REG9X_RESERVED_2_Pos                                                                                 13U
+#define AON_REG_PAD_REG9X_RESERVED_2_Msk                                                                                 (0x1UL << AON_REG_PAD_REG9X_RESERVED_2_Pos)
+
+#define AON_REG_PAD_REG9X_PAD_P2_AON_MUX_6_Pos                                                                           14U
+#define AON_REG_PAD_REG9X_PAD_P2_AON_MUX_6_Msk                                                                           (0x3UL << AON_REG_PAD_REG9X_PAD_P2_AON_MUX_6_Pos)
+
+#define AON_REG_PAD_REG9X_PAD_P2_O_7_Pos                                                                                 16U
+#define AON_REG_PAD_REG9X_PAD_P2_O_7_Msk                                                                                 (0x1UL << AON_REG_PAD_REG9X_PAD_P2_O_7_Pos)
+
+#define AON_REG_PAD_REG9X_PAD_P2_E_7_Pos                                                                                 17U
+#define AON_REG_PAD_REG9X_PAD_P2_E_7_Msk                                                                                 (0x1UL << AON_REG_PAD_REG9X_PAD_P2_E_7_Pos)
+
+#define AON_REG_PAD_REG9X_PAD_P2_PU_EN_7_Pos                                                                             18U
+#define AON_REG_PAD_REG9X_PAD_P2_PU_EN_7_Msk                                                                             (0x1UL << AON_REG_PAD_REG9X_PAD_P2_PU_EN_7_Pos)
+
+#define AON_REG_PAD_REG9X_AON_PAD_P2_PD_7_Pos                                                                            19U
+#define AON_REG_PAD_REG9X_AON_PAD_P2_PD_7_Msk                                                                            (0x1UL << AON_REG_PAD_REG9X_AON_PAD_P2_PD_7_Pos)
+
+#define AON_REG_PAD_REG9X_PAD_P2_PUPDC_7_Pos                                                                             20U
+#define AON_REG_PAD_REG9X_PAD_P2_PUPDC_7_Msk                                                                             (0x1UL << AON_REG_PAD_REG9X_PAD_P2_PUPDC_7_Pos)
+
+#define AON_REG_PAD_REG9X_PAD_P2_WKEN_7_Pos                                                                              21U
+#define AON_REG_PAD_REG9X_PAD_P2_WKEN_7_Msk                                                                              (0x1UL << AON_REG_PAD_REG9X_PAD_P2_WKEN_7_Pos)
+
+#define AON_REG_PAD_REG9X_PAD_P2_WKPOL_7_Pos                                                                             22U
+#define AON_REG_PAD_REG9X_PAD_P2_WKPOL_7_Msk                                                                             (0x1UL << AON_REG_PAD_REG9X_PAD_P2_WKPOL_7_Pos)
+
+#define AON_REG_PAD_REG9X_PAD_P2_SHDN_7_Pos                                                                              23U
+#define AON_REG_PAD_REG9X_PAD_P2_SHDN_7_Msk                                                                              (0x1UL << AON_REG_PAD_REG9X_PAD_P2_SHDN_7_Pos)
+
+#define AON_REG_PAD_REG9X_PAD_P2_DEB_7_Pos                                                                               24U
+#define AON_REG_PAD_REG9X_PAD_P2_DEB_7_Msk                                                                               (0x1UL << AON_REG_PAD_REG9X_PAD_P2_DEB_7_Pos)
+
+#define AON_REG_PAD_REG9X_PAD_P2_RAP_WKEN_7_Pos                                                                          25U
+#define AON_REG_PAD_REG9X_PAD_P2_RAP_WKEN_7_Msk                                                                          (0x1UL << AON_REG_PAD_REG9X_PAD_P2_RAP_WKEN_7_Pos)
+
+#define AON_REG_PAD_REG9X_PAD_P2_PPU_WKEN_7_Pos                                                                          26U
+#define AON_REG_PAD_REG9X_PAD_P2_PPU_WKEN_7_Msk                                                                          (0x1UL << AON_REG_PAD_REG9X_PAD_P2_PPU_WKEN_7_Pos)
+
+#define AON_REG_PAD_REG9X_RESERVED_1_Pos                                                                                 27U
+#define AON_REG_PAD_REG9X_RESERVED_1_Msk                                                                                 (0x1UL << AON_REG_PAD_REG9X_RESERVED_1_Pos)
+
+#define AON_REG_PAD_REG9X_DUMMY_PAD7_Pos                                                                                 28U
+#define AON_REG_PAD_REG9X_DUMMY_PAD7_Msk                                                                                 (0x1UL << AON_REG_PAD_REG9X_DUMMY_PAD7_Pos)
+
+#define AON_REG_PAD_REG9X_RESERVED_Pos                                                                                   29U
+#define AON_REG_PAD_REG9X_RESERVED_Msk                                                                                   (0x1UL << AON_REG_PAD_REG9X_RESERVED_Pos)
+
+#define AON_REG_PAD_REG9X_PAD_P2_AON_MUX_7_Pos                                                                           30U
+#define AON_REG_PAD_REG9X_PAD_P2_AON_MUX_7_Msk                                                                           (0x3UL << AON_REG_PAD_REG9X_PAD_P2_AON_MUX_7_Pos)
+
+/* 0x148    0x4000_0148
+    0       R/W     PAD_P3_O_0                                                  1'b0
+    1       R/W     PAD_P3_E_0                                                  1'b0
+    2       R/W     PAD_P3_PU_EN_0                                              1'b1
+    3       R/W     AON_PAD_P3_PD_0                                             1'b0
+    4       R/W     PAD_P3_PUPDC_0                                              1'b0
+    5       R/W     PAD_P3_WKEN_0                                               1'b0
+    6       R/W     PAD_P3_WKPOL_0                                              1'b0
+    7       R/W     PAD_P3_SHDN_0                                               1'b1
+    8       R/W     PAD_P3_DEB_0                                                1'b0
+    9       R/W     PAD_P3_RAP_WKEN_0                                           1'b0
+    10      R/W     PAD_P3_PPU_WKEN_0                                           1'b0
+    11      R/W     RESERVED_3                                                  1'b0
+    13:12   R       RESERVED_2                                                  2'b00
+    15:14   R/W     PAD_P3_AON_MUX_0                                            2'b00
+    16      R/W     PAD_P3_O_1                                                  1'b0
+    17      R/W     PAD_P3_E_1                                                  1'b0
+    18      R/W     PAD_P3_PU_EN_1                                              1'b1
+    19      R/W     AON_PAD_P3_PD_1                                             1'b0
+    20      R/W     PAD_P3_PUPDC_1                                              1'b0
+    21      R/W     PAD_P3_WKEN_1                                               1'b0
+    22      R/W     PAD_P3_WKPOL_1                                              1'b0
+    23      R/W     PAD_P3_SHDN_1                                               1'b1
+    24      R/W     PAD_P3_DEB_1                                                1'b0
+    25      R/W     PAD_P3_RAP_WKEN_1                                           1'b0
+    26      R/W     PAD_P3_PPU_WKEN_1                                           1'b0
+    27      R/W     RESERVED_1                                                  1'b0
+    29:28   R       RESERVED                                                    2'b00
+    31:30   R/W     PAD_P3_AON_MUX_1                                            2'b00
+ */
+typedef union _AON_REG_PAD_REG10X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t PAD_P3_O_0: 1;
+        uint32_t PAD_P3_E_0: 1;
+        uint32_t PAD_P3_PU_EN_0: 1;
+        uint32_t AON_PAD_P3_PD_0: 1;
+        uint32_t PAD_P3_PUPDC_0: 1;
+        uint32_t PAD_P3_WKEN_0: 1;
+        uint32_t PAD_P3_WKPOL_0: 1;
+        uint32_t PAD_P3_SHDN_0: 1;
+        uint32_t PAD_P3_DEB_0: 1;
+        uint32_t PAD_P3_RAP_WKEN_0: 1;
+        uint32_t PAD_P3_PPU_WKEN_0: 1;
+        uint32_t RESERVED_3: 1;
+        uint32_t RESERVED_2: 2;
+        uint32_t PAD_P3_AON_MUX_0: 2;
+        uint32_t PAD_P3_O_1: 1;
+        uint32_t PAD_P3_E_1: 1;
+        uint32_t PAD_P3_PU_EN_1: 1;
+        uint32_t AON_PAD_P3_PD_1: 1;
+        uint32_t PAD_P3_PUPDC_1: 1;
+        uint32_t PAD_P3_WKEN_1: 1;
+        uint32_t PAD_P3_WKPOL_1: 1;
+        uint32_t PAD_P3_SHDN_1: 1;
+        uint32_t PAD_P3_DEB_1: 1;
+        uint32_t PAD_P3_RAP_WKEN_1: 1;
+        uint32_t PAD_P3_PPU_WKEN_1: 1;
+        uint32_t RESERVED_1: 1;
+        uint32_t RESERVED: 2;
+        uint32_t PAD_P3_AON_MUX_1: 2;
+    };
+} AON_REG_PAD_REG10X_TYPE;
+
+/*0x4000_0148 AON_REG_PAD_REG10X*/
+#define AON_REG_PAD_REG10X_PAD_P3_O_0_Pos                                                                                0U
+#define AON_REG_PAD_REG10X_PAD_P3_O_0_Msk                                                                                (0x1UL << AON_REG_PAD_REG10X_PAD_P3_O_0_Pos)
+
+#define AON_REG_PAD_REG10X_PAD_P3_E_0_Pos                                                                                1U
+#define AON_REG_PAD_REG10X_PAD_P3_E_0_Msk                                                                                (0x1UL << AON_REG_PAD_REG10X_PAD_P3_E_0_Pos)
+
+#define AON_REG_PAD_REG10X_PAD_P3_PU_EN_0_Pos                                                                            2U
+#define AON_REG_PAD_REG10X_PAD_P3_PU_EN_0_Msk                                                                            (0x1UL << AON_REG_PAD_REG10X_PAD_P3_PU_EN_0_Pos)
+
+#define AON_REG_PAD_REG10X_AON_PAD_P3_PD_0_Pos                                                                           3U
+#define AON_REG_PAD_REG10X_AON_PAD_P3_PD_0_Msk                                                                           (0x1UL << AON_REG_PAD_REG10X_AON_PAD_P3_PD_0_Pos)
+
+#define AON_REG_PAD_REG10X_PAD_P3_PUPDC_0_Pos                                                                            4U
+#define AON_REG_PAD_REG10X_PAD_P3_PUPDC_0_Msk                                                                            (0x1UL << AON_REG_PAD_REG10X_PAD_P3_PUPDC_0_Pos)
+
+#define AON_REG_PAD_REG10X_PAD_P3_WKEN_0_Pos                                                                             5U
+#define AON_REG_PAD_REG10X_PAD_P3_WKEN_0_Msk                                                                             (0x1UL << AON_REG_PAD_REG10X_PAD_P3_WKEN_0_Pos)
+
+#define AON_REG_PAD_REG10X_PAD_P3_WKPOL_0_Pos                                                                            6U
+#define AON_REG_PAD_REG10X_PAD_P3_WKPOL_0_Msk                                                                            (0x1UL << AON_REG_PAD_REG10X_PAD_P3_WKPOL_0_Pos)
+
+#define AON_REG_PAD_REG10X_PAD_P3_SHDN_0_Pos                                                                             7U
+#define AON_REG_PAD_REG10X_PAD_P3_SHDN_0_Msk                                                                             (0x1UL << AON_REG_PAD_REG10X_PAD_P3_SHDN_0_Pos)
+
+#define AON_REG_PAD_REG10X_PAD_P3_DEB_0_Pos                                                                              8U
+#define AON_REG_PAD_REG10X_PAD_P3_DEB_0_Msk                                                                              (0x1UL << AON_REG_PAD_REG10X_PAD_P3_DEB_0_Pos)
+
+#define AON_REG_PAD_REG10X_PAD_P3_RAP_WKEN_0_Pos                                                                         9U
+#define AON_REG_PAD_REG10X_PAD_P3_RAP_WKEN_0_Msk                                                                         (0x1UL << AON_REG_PAD_REG10X_PAD_P3_RAP_WKEN_0_Pos)
+
+#define AON_REG_PAD_REG10X_PAD_P3_PPU_WKEN_0_Pos                                                                         10U
+#define AON_REG_PAD_REG10X_PAD_P3_PPU_WKEN_0_Msk                                                                         (0x1UL << AON_REG_PAD_REG10X_PAD_P3_PPU_WKEN_0_Pos)
+
+#define AON_REG_PAD_REG10X_RESERVED_3_Pos                                                                                11U
+#define AON_REG_PAD_REG10X_RESERVED_3_Msk                                                                                (0x1UL << AON_REG_PAD_REG10X_RESERVED_3_Pos)
+
+#define AON_REG_PAD_REG10X_RESERVED_2_Pos                                                                                12U
+#define AON_REG_PAD_REG10X_RESERVED_2_Msk                                                                                (0x3UL << AON_REG_PAD_REG10X_RESERVED_2_Pos)
+
+#define AON_REG_PAD_REG10X_PAD_P3_AON_MUX_0_Pos                                                                          14U
+#define AON_REG_PAD_REG10X_PAD_P3_AON_MUX_0_Msk                                                                          (0x3UL << AON_REG_PAD_REG10X_PAD_P3_AON_MUX_0_Pos)
+
+#define AON_REG_PAD_REG10X_PAD_P3_O_1_Pos                                                                                16U
+#define AON_REG_PAD_REG10X_PAD_P3_O_1_Msk                                                                                (0x1UL << AON_REG_PAD_REG10X_PAD_P3_O_1_Pos)
+
+#define AON_REG_PAD_REG10X_PAD_P3_E_1_Pos                                                                                17U
+#define AON_REG_PAD_REG10X_PAD_P3_E_1_Msk                                                                                (0x1UL << AON_REG_PAD_REG10X_PAD_P3_E_1_Pos)
+
+#define AON_REG_PAD_REG10X_PAD_P3_PU_EN_1_Pos                                                                            18U
+#define AON_REG_PAD_REG10X_PAD_P3_PU_EN_1_Msk                                                                            (0x1UL << AON_REG_PAD_REG10X_PAD_P3_PU_EN_1_Pos)
+
+#define AON_REG_PAD_REG10X_AON_PAD_P3_PD_1_Pos                                                                           19U
+#define AON_REG_PAD_REG10X_AON_PAD_P3_PD_1_Msk                                                                           (0x1UL << AON_REG_PAD_REG10X_AON_PAD_P3_PD_1_Pos)
+
+#define AON_REG_PAD_REG10X_PAD_P3_PUPDC_1_Pos                                                                            20U
+#define AON_REG_PAD_REG10X_PAD_P3_PUPDC_1_Msk                                                                            (0x1UL << AON_REG_PAD_REG10X_PAD_P3_PUPDC_1_Pos)
+
+#define AON_REG_PAD_REG10X_PAD_P3_WKEN_1_Pos                                                                             21U
+#define AON_REG_PAD_REG10X_PAD_P3_WKEN_1_Msk                                                                             (0x1UL << AON_REG_PAD_REG10X_PAD_P3_WKEN_1_Pos)
+
+#define AON_REG_PAD_REG10X_PAD_P3_WKPOL_1_Pos                                                                            22U
+#define AON_REG_PAD_REG10X_PAD_P3_WKPOL_1_Msk                                                                            (0x1UL << AON_REG_PAD_REG10X_PAD_P3_WKPOL_1_Pos)
+
+#define AON_REG_PAD_REG10X_PAD_P3_SHDN_1_Pos                                                                             23U
+#define AON_REG_PAD_REG10X_PAD_P3_SHDN_1_Msk                                                                             (0x1UL << AON_REG_PAD_REG10X_PAD_P3_SHDN_1_Pos)
+
+#define AON_REG_PAD_REG10X_PAD_P3_DEB_1_Pos                                                                              24U
+#define AON_REG_PAD_REG10X_PAD_P3_DEB_1_Msk                                                                              (0x1UL << AON_REG_PAD_REG10X_PAD_P3_DEB_1_Pos)
+
+#define AON_REG_PAD_REG10X_PAD_P3_RAP_WKEN_1_Pos                                                                         25U
+#define AON_REG_PAD_REG10X_PAD_P3_RAP_WKEN_1_Msk                                                                         (0x1UL << AON_REG_PAD_REG10X_PAD_P3_RAP_WKEN_1_Pos)
+
+#define AON_REG_PAD_REG10X_PAD_P3_PPU_WKEN_1_Pos                                                                         26U
+#define AON_REG_PAD_REG10X_PAD_P3_PPU_WKEN_1_Msk                                                                         (0x1UL << AON_REG_PAD_REG10X_PAD_P3_PPU_WKEN_1_Pos)
+
+#define AON_REG_PAD_REG10X_RESERVED_1_Pos                                                                                27U
+#define AON_REG_PAD_REG10X_RESERVED_1_Msk                                                                                (0x1UL << AON_REG_PAD_REG10X_RESERVED_1_Pos)
+
+#define AON_REG_PAD_REG10X_RESERVED_Pos                                                                                  28U
+#define AON_REG_PAD_REG10X_RESERVED_Msk                                                                                  (0x3UL << AON_REG_PAD_REG10X_RESERVED_Pos)
+
+#define AON_REG_PAD_REG10X_PAD_P3_AON_MUX_1_Pos                                                                          30U
+#define AON_REG_PAD_REG10X_PAD_P3_AON_MUX_1_Msk                                                                          (0x3UL << AON_REG_PAD_REG10X_PAD_P3_AON_MUX_1_Pos)
+
+/* 0x14C    0x4000_014c
+    0       R/W     PAD_P3_O_2                                                  1'b0
+    1       R/W     PAD_P3_E_2                                                  1'b0
+    2       R/W     PAD_P3_PU_EN_2                                              1'b1
+    3       R/W     AON_PAD_P3_PD_2                                             1'b1
+    4       R/W     PAD_P3_PUPDC_2                                              1'b0
+    5       R/W     PAD_P3_WKEN_2                                               1'b0
+    6       R/W     PAD_P3_WKPOL_2                                              1'b0
+    7       R/W     PAD_P3_SHDN_2                                               1'b1
+    8       R/W     PAD_P3_DEB_2                                                1'b0
+    9       R/W     PAD_P3_RAP_WKEN_2                                           1'b0
+    10      R/W     PAD_P3_PPU_WKEN_2                                           1'b0
+    11      R/W     RESERVED_3                                                  1'b0
+    13:12   R       RESERVED_2                                                  2'b00
+    15:14   R/W     PAD_P3_AON_MUX_2                                            2'b00
+    16      R/W     PAD_P3_O_3                                                  1'b0
+    17      R/W     PAD_P3_E_3                                                  1'b0
+    18      R/W     PAD_P3_PU_EN_3                                              1'b1
+    19      R/W     AON_PAD_P3_PD_3                                             1'b1
+    20      R/W     PAD_P3_PUPDC_3                                              1'b0
+    21      R/W     PAD_P3_WKEN_3                                               1'b0
+    22      R/W     PAD_P3_WKPOL_3                                              1'b0
+    23      R/W     PAD_P3_SHDN_3                                               1'b1
+    24      R/W     PAD_P3_DEB_3                                                1'b0
+    25      R/W     PAD_P3_RAP_WKEN_3                                           1'b0
+    26      R/W     PAD_P3_PPU_WKEN_3                                           1'b0
+    27      R/W     RESERVED_1                                                  1'b0
+    29:28   R       RESERVED                                                    2'b00
+    31:30   R/W     PAD_P3_AON_MUX_3                                            2'b00
+ */
+typedef union _AON_REG_PAD_REG11X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t PAD_P3_O_2: 1;
+        uint32_t PAD_P3_E_2: 1;
+        uint32_t PAD_P3_PU_EN_2: 1;
+        uint32_t AON_PAD_P3_PD_2: 1;
+        uint32_t PAD_P3_PUPDC_2: 1;
+        uint32_t PAD_P3_WKEN_2: 1;
+        uint32_t PAD_P3_WKPOL_2: 1;
+        uint32_t PAD_P3_SHDN_2: 1;
+        uint32_t PAD_P3_DEB_2: 1;
+        uint32_t PAD_P3_RAP_WKEN_2: 1;
+        uint32_t PAD_P3_PPU_WKEN_2: 1;
+        uint32_t RESERVED_3: 1;
+        uint32_t RESERVED_2: 2;
+        uint32_t PAD_P3_AON_MUX_2: 2;
+        uint32_t PAD_P3_O_3: 1;
+        uint32_t PAD_P3_E_3: 1;
+        uint32_t PAD_P3_PU_EN_3: 1;
+        uint32_t AON_PAD_P3_PD_3: 1;
+        uint32_t PAD_P3_PUPDC_3: 1;
+        uint32_t PAD_P3_WKEN_3: 1;
+        uint32_t PAD_P3_WKPOL_3: 1;
+        uint32_t PAD_P3_SHDN_3: 1;
+        uint32_t PAD_P3_DEB_3: 1;
+        uint32_t PAD_P3_RAP_WKEN_3: 1;
+        uint32_t PAD_P3_PPU_WKEN_3: 1;
+        uint32_t RESERVED_1: 1;
+        uint32_t RESERVED: 2;
+        uint32_t PAD_P3_AON_MUX_3: 2;
+    };
+} AON_REG_PAD_REG11X_TYPE;
+
+/*0x4000_014c AON_REG_PAD_REG11X*/
+#define AON_REG_PAD_REG11X_PAD_P3_O_2_Pos                                                                                0U
+#define AON_REG_PAD_REG11X_PAD_P3_O_2_Msk                                                                                (0x1UL << AON_REG_PAD_REG11X_PAD_P3_O_2_Pos)
+
+#define AON_REG_PAD_REG11X_PAD_P3_E_2_Pos                                                                                1U
+#define AON_REG_PAD_REG11X_PAD_P3_E_2_Msk                                                                                (0x1UL << AON_REG_PAD_REG11X_PAD_P3_E_2_Pos)
+
+#define AON_REG_PAD_REG11X_PAD_P3_PU_EN_2_Pos                                                                            2U
+#define AON_REG_PAD_REG11X_PAD_P3_PU_EN_2_Msk                                                                            (0x1UL << AON_REG_PAD_REG11X_PAD_P3_PU_EN_2_Pos)
+
+#define AON_REG_PAD_REG11X_AON_PAD_P3_PD_2_Pos                                                                           3U
+#define AON_REG_PAD_REG11X_AON_PAD_P3_PD_2_Msk                                                                           (0x1UL << AON_REG_PAD_REG11X_AON_PAD_P3_PD_2_Pos)
+
+#define AON_REG_PAD_REG11X_PAD_P3_PUPDC_2_Pos                                                                            4U
+#define AON_REG_PAD_REG11X_PAD_P3_PUPDC_2_Msk                                                                            (0x1UL << AON_REG_PAD_REG11X_PAD_P3_PUPDC_2_Pos)
+
+#define AON_REG_PAD_REG11X_PAD_P3_WKEN_2_Pos                                                                             5U
+#define AON_REG_PAD_REG11X_PAD_P3_WKEN_2_Msk                                                                             (0x1UL << AON_REG_PAD_REG11X_PAD_P3_WKEN_2_Pos)
+
+#define AON_REG_PAD_REG11X_PAD_P3_WKPOL_2_Pos                                                                            6U
+#define AON_REG_PAD_REG11X_PAD_P3_WKPOL_2_Msk                                                                            (0x1UL << AON_REG_PAD_REG11X_PAD_P3_WKPOL_2_Pos)
+
+#define AON_REG_PAD_REG11X_PAD_P3_SHDN_2_Pos                                                                             7U
+#define AON_REG_PAD_REG11X_PAD_P3_SHDN_2_Msk                                                                             (0x1UL << AON_REG_PAD_REG11X_PAD_P3_SHDN_2_Pos)
+
+#define AON_REG_PAD_REG11X_PAD_P3_DEB_2_Pos                                                                              8U
+#define AON_REG_PAD_REG11X_PAD_P3_DEB_2_Msk                                                                              (0x1UL << AON_REG_PAD_REG11X_PAD_P3_DEB_2_Pos)
+
+#define AON_REG_PAD_REG11X_PAD_P3_RAP_WKEN_2_Pos                                                                         9U
+#define AON_REG_PAD_REG11X_PAD_P3_RAP_WKEN_2_Msk                                                                         (0x1UL << AON_REG_PAD_REG11X_PAD_P3_RAP_WKEN_2_Pos)
+
+#define AON_REG_PAD_REG11X_PAD_P3_PPU_WKEN_2_Pos                                                                         10U
+#define AON_REG_PAD_REG11X_PAD_P3_PPU_WKEN_2_Msk                                                                         (0x1UL << AON_REG_PAD_REG11X_PAD_P3_PPU_WKEN_2_Pos)
+
+#define AON_REG_PAD_REG11X_RESERVED_3_Pos                                                                                11U
+#define AON_REG_PAD_REG11X_RESERVED_3_Msk                                                                                (0x1UL << AON_REG_PAD_REG11X_RESERVED_3_Pos)
+
+#define AON_REG_PAD_REG11X_RESERVED_2_Pos                                                                                12U
+#define AON_REG_PAD_REG11X_RESERVED_2_Msk                                                                                (0x3UL << AON_REG_PAD_REG11X_RESERVED_2_Pos)
+
+#define AON_REG_PAD_REG11X_PAD_P3_AON_MUX_2_Pos                                                                          14U
+#define AON_REG_PAD_REG11X_PAD_P3_AON_MUX_2_Msk                                                                          (0x3UL << AON_REG_PAD_REG11X_PAD_P3_AON_MUX_2_Pos)
+
+#define AON_REG_PAD_REG11X_PAD_P3_O_3_Pos                                                                                16U
+#define AON_REG_PAD_REG11X_PAD_P3_O_3_Msk                                                                                (0x1UL << AON_REG_PAD_REG11X_PAD_P3_O_3_Pos)
+
+#define AON_REG_PAD_REG11X_PAD_P3_E_3_Pos                                                                                17U
+#define AON_REG_PAD_REG11X_PAD_P3_E_3_Msk                                                                                (0x1UL << AON_REG_PAD_REG11X_PAD_P3_E_3_Pos)
+
+#define AON_REG_PAD_REG11X_PAD_P3_PU_EN_3_Pos                                                                            18U
+#define AON_REG_PAD_REG11X_PAD_P3_PU_EN_3_Msk                                                                            (0x1UL << AON_REG_PAD_REG11X_PAD_P3_PU_EN_3_Pos)
+
+#define AON_REG_PAD_REG11X_AON_PAD_P3_PD_3_Pos                                                                           19U
+#define AON_REG_PAD_REG11X_AON_PAD_P3_PD_3_Msk                                                                           (0x1UL << AON_REG_PAD_REG11X_AON_PAD_P3_PD_3_Pos)
+
+#define AON_REG_PAD_REG11X_PAD_P3_PUPDC_3_Pos                                                                            20U
+#define AON_REG_PAD_REG11X_PAD_P3_PUPDC_3_Msk                                                                            (0x1UL << AON_REG_PAD_REG11X_PAD_P3_PUPDC_3_Pos)
+
+#define AON_REG_PAD_REG11X_PAD_P3_WKEN_3_Pos                                                                             21U
+#define AON_REG_PAD_REG11X_PAD_P3_WKEN_3_Msk                                                                             (0x1UL << AON_REG_PAD_REG11X_PAD_P3_WKEN_3_Pos)
+
+#define AON_REG_PAD_REG11X_PAD_P3_WKPOL_3_Pos                                                                            22U
+#define AON_REG_PAD_REG11X_PAD_P3_WKPOL_3_Msk                                                                            (0x1UL << AON_REG_PAD_REG11X_PAD_P3_WKPOL_3_Pos)
+
+#define AON_REG_PAD_REG11X_PAD_P3_SHDN_3_Pos                                                                             23U
+#define AON_REG_PAD_REG11X_PAD_P3_SHDN_3_Msk                                                                             (0x1UL << AON_REG_PAD_REG11X_PAD_P3_SHDN_3_Pos)
+
+#define AON_REG_PAD_REG11X_PAD_P3_DEB_3_Pos                                                                              24U
+#define AON_REG_PAD_REG11X_PAD_P3_DEB_3_Msk                                                                              (0x1UL << AON_REG_PAD_REG11X_PAD_P3_DEB_3_Pos)
+
+#define AON_REG_PAD_REG11X_PAD_P3_RAP_WKEN_3_Pos                                                                         25U
+#define AON_REG_PAD_REG11X_PAD_P3_RAP_WKEN_3_Msk                                                                         (0x1UL << AON_REG_PAD_REG11X_PAD_P3_RAP_WKEN_3_Pos)
+
+#define AON_REG_PAD_REG11X_PAD_P3_PPU_WKEN_3_Pos                                                                         26U
+#define AON_REG_PAD_REG11X_PAD_P3_PPU_WKEN_3_Msk                                                                         (0x1UL << AON_REG_PAD_REG11X_PAD_P3_PPU_WKEN_3_Pos)
+
+#define AON_REG_PAD_REG11X_RESERVED_1_Pos                                                                                27U
+#define AON_REG_PAD_REG11X_RESERVED_1_Msk                                                                                (0x1UL << AON_REG_PAD_REG11X_RESERVED_1_Pos)
+
+#define AON_REG_PAD_REG11X_RESERVED_Pos                                                                                  28U
+#define AON_REG_PAD_REG11X_RESERVED_Msk                                                                                  (0x3UL << AON_REG_PAD_REG11X_RESERVED_Pos)
+
+#define AON_REG_PAD_REG11X_PAD_P3_AON_MUX_3_Pos                                                                          30U
+#define AON_REG_PAD_REG11X_PAD_P3_AON_MUX_3_Msk                                                                          (0x3UL << AON_REG_PAD_REG11X_PAD_P3_AON_MUX_3_Pos)
+
+/* 0x150    0x4000_0150
+    0       R/W     PAD_P3_O_4                                                  1'b0
+    1       R/W     PAD_P3_E_4                                                  1'b0
+    2       R/W     PAD_P3_PU_EN_4                                              1'b1
+    3       R/W     AON_PAD_P3_PD_4                                             1'b1
+    4       R/W     PAD_P3_PUPDC_4                                              1'b0
+    5       R/W     PAD_P3_WKEN_4                                               1'b0
+    6       R/W     PAD_P3_WKPOL_4                                              1'b0
+    7       R/W     PAD_P3_SHDN_4                                               1'b1
+    8       R/W     PAD_P3_DEB_4                                                1'b0
+    9       R/W     PAD_P3_RAP_WKEN_4                                           1'b0
+    10      R/W     PAD_P3_PPU_WKEN_4                                           1'b0
+    11      R/W     RESERVED_3                                                  1'b0
+    13:12   R       RESERVED_2                                                  2'b00
+    15:14   R/W     PAD_P3_AON_MUX_4                                            2'b00
+    16      R/W     PAD_P3_O_5                                                  1'b0
+    17      R/W     PAD_P3_E_5                                                  1'b0
+    18      R/W     PAD_P3_PU_EN_5                                              1'b1
+    19      R/W     AON_PAD_P3_PD_5                                             1'b1
+    20      R/W     PAD_P3_PUPDC_5                                              1'b0
+    21      R/W     PAD_P3_WKEN_5                                               1'b0
+    22      R/W     PAD_P3_WKPOL_5                                              1'b0
+    23      R/W     PAD_P3_SHDN_5                                               1'b1
+    24      R/W     PAD_P3_DEB_5                                                1'b0
+    25      R/W     PAD_P3_RAP_WKEN_5                                           1'b0
+    26      R/W     PAD_P3_PPU_WKEN_5                                           1'b0
+    27      R/W     RESERVED_1                                                  1'b0
+    29:28   R       RESERVED                                                    2'b00
+    31:30   R/W     PAD_P3_AON_MUX_5                                            2'b00
+ */
+typedef union _AON_REG_PAD_REG12X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t PAD_P3_O_4: 1;
+        uint32_t PAD_P3_E_4: 1;
+        uint32_t PAD_P3_PU_EN_4: 1;
+        uint32_t AON_PAD_P3_PD_4: 1;
+        uint32_t PAD_P3_PUPDC_4: 1;
+        uint32_t PAD_P3_WKEN_4: 1;
+        uint32_t PAD_P3_WKPOL_4: 1;
+        uint32_t PAD_P3_SHDN_4: 1;
+        uint32_t PAD_P3_DEB_4: 1;
+        uint32_t PAD_P3_RAP_WKEN_4: 1;
+        uint32_t PAD_P3_PPU_WKEN_4: 1;
+        uint32_t RESERVED_3: 1;
+        uint32_t RESERVED_2: 2;
+        uint32_t PAD_P3_AON_MUX_4: 2;
+        uint32_t PAD_P3_O_5: 1;
+        uint32_t PAD_P3_E_5: 1;
+        uint32_t PAD_P3_PU_EN_5: 1;
+        uint32_t AON_PAD_P3_PD_5: 1;
+        uint32_t PAD_P3_PUPDC_5: 1;
+        uint32_t PAD_P3_WKEN_5: 1;
+        uint32_t PAD_P3_WKPOL_5: 1;
+        uint32_t PAD_P3_SHDN_5: 1;
+        uint32_t PAD_P3_DEB_5: 1;
+        uint32_t PAD_P3_RAP_WKEN_5: 1;
+        uint32_t PAD_P3_PPU_WKEN_5: 1;
+        uint32_t RESERVED_1: 1;
+        uint32_t RESERVED: 2;
+        uint32_t PAD_P3_AON_MUX_5: 2;
+    };
+} AON_REG_PAD_REG12X_TYPE;
+
+/*0x4000_0150 AON_REG_PAD_REG12X*/
+#define AON_REG_PAD_REG12X_PAD_P3_O_4_Pos                                                                                0U
+#define AON_REG_PAD_REG12X_PAD_P3_O_4_Msk                                                                                (0x1UL << AON_REG_PAD_REG12X_PAD_P3_O_4_Pos)
+
+#define AON_REG_PAD_REG12X_PAD_P3_E_4_Pos                                                                                1U
+#define AON_REG_PAD_REG12X_PAD_P3_E_4_Msk                                                                                (0x1UL << AON_REG_PAD_REG12X_PAD_P3_E_4_Pos)
+
+#define AON_REG_PAD_REG12X_PAD_P3_PU_EN_4_Pos                                                                            2U
+#define AON_REG_PAD_REG12X_PAD_P3_PU_EN_4_Msk                                                                            (0x1UL << AON_REG_PAD_REG12X_PAD_P3_PU_EN_4_Pos)
+
+#define AON_REG_PAD_REG12X_AON_PAD_P3_PD_4_Pos                                                                           3U
+#define AON_REG_PAD_REG12X_AON_PAD_P3_PD_4_Msk                                                                           (0x1UL << AON_REG_PAD_REG12X_AON_PAD_P3_PD_4_Pos)
+
+#define AON_REG_PAD_REG12X_PAD_P3_PUPDC_4_Pos                                                                            4U
+#define AON_REG_PAD_REG12X_PAD_P3_PUPDC_4_Msk                                                                            (0x1UL << AON_REG_PAD_REG12X_PAD_P3_PUPDC_4_Pos)
+
+#define AON_REG_PAD_REG12X_PAD_P3_WKEN_4_Pos                                                                             5U
+#define AON_REG_PAD_REG12X_PAD_P3_WKEN_4_Msk                                                                             (0x1UL << AON_REG_PAD_REG12X_PAD_P3_WKEN_4_Pos)
+
+#define AON_REG_PAD_REG12X_PAD_P3_WKPOL_4_Pos                                                                            6U
+#define AON_REG_PAD_REG12X_PAD_P3_WKPOL_4_Msk                                                                            (0x1UL << AON_REG_PAD_REG12X_PAD_P3_WKPOL_4_Pos)
+
+#define AON_REG_PAD_REG12X_PAD_P3_SHDN_4_Pos                                                                             7U
+#define AON_REG_PAD_REG12X_PAD_P3_SHDN_4_Msk                                                                             (0x1UL << AON_REG_PAD_REG12X_PAD_P3_SHDN_4_Pos)
+
+#define AON_REG_PAD_REG12X_PAD_P3_DEB_4_Pos                                                                              8U
+#define AON_REG_PAD_REG12X_PAD_P3_DEB_4_Msk                                                                              (0x1UL << AON_REG_PAD_REG12X_PAD_P3_DEB_4_Pos)
+
+#define AON_REG_PAD_REG12X_PAD_P3_RAP_WKEN_4_Pos                                                                         9U
+#define AON_REG_PAD_REG12X_PAD_P3_RAP_WKEN_4_Msk                                                                         (0x1UL << AON_REG_PAD_REG12X_PAD_P3_RAP_WKEN_4_Pos)
+
+#define AON_REG_PAD_REG12X_PAD_P3_PPU_WKEN_4_Pos                                                                         10U
+#define AON_REG_PAD_REG12X_PAD_P3_PPU_WKEN_4_Msk                                                                         (0x1UL << AON_REG_PAD_REG12X_PAD_P3_PPU_WKEN_4_Pos)
+
+#define AON_REG_PAD_REG12X_RESERVED_3_Pos                                                                                11U
+#define AON_REG_PAD_REG12X_RESERVED_3_Msk                                                                                (0x1UL << AON_REG_PAD_REG12X_RESERVED_3_Pos)
+
+#define AON_REG_PAD_REG12X_RESERVED_2_Pos                                                                                12U
+#define AON_REG_PAD_REG12X_RESERVED_2_Msk                                                                                (0x3UL << AON_REG_PAD_REG12X_RESERVED_2_Pos)
+
+#define AON_REG_PAD_REG12X_PAD_P3_AON_MUX_4_Pos                                                                          14U
+#define AON_REG_PAD_REG12X_PAD_P3_AON_MUX_4_Msk                                                                          (0x3UL << AON_REG_PAD_REG12X_PAD_P3_AON_MUX_4_Pos)
+
+#define AON_REG_PAD_REG12X_PAD_P3_O_5_Pos                                                                                16U
+#define AON_REG_PAD_REG12X_PAD_P3_O_5_Msk                                                                                (0x1UL << AON_REG_PAD_REG12X_PAD_P3_O_5_Pos)
+
+#define AON_REG_PAD_REG12X_PAD_P3_E_5_Pos                                                                                17U
+#define AON_REG_PAD_REG12X_PAD_P3_E_5_Msk                                                                                (0x1UL << AON_REG_PAD_REG12X_PAD_P3_E_5_Pos)
+
+#define AON_REG_PAD_REG12X_PAD_P3_PU_EN_5_Pos                                                                            18U
+#define AON_REG_PAD_REG12X_PAD_P3_PU_EN_5_Msk                                                                            (0x1UL << AON_REG_PAD_REG12X_PAD_P3_PU_EN_5_Pos)
+
+#define AON_REG_PAD_REG12X_AON_PAD_P3_PD_5_Pos                                                                           19U
+#define AON_REG_PAD_REG12X_AON_PAD_P3_PD_5_Msk                                                                           (0x1UL << AON_REG_PAD_REG12X_AON_PAD_P3_PD_5_Pos)
+
+#define AON_REG_PAD_REG12X_PAD_P3_PUPDC_5_Pos                                                                            20U
+#define AON_REG_PAD_REG12X_PAD_P3_PUPDC_5_Msk                                                                            (0x1UL << AON_REG_PAD_REG12X_PAD_P3_PUPDC_5_Pos)
+
+#define AON_REG_PAD_REG12X_PAD_P3_WKEN_5_Pos                                                                             21U
+#define AON_REG_PAD_REG12X_PAD_P3_WKEN_5_Msk                                                                             (0x1UL << AON_REG_PAD_REG12X_PAD_P3_WKEN_5_Pos)
+
+#define AON_REG_PAD_REG12X_PAD_P3_WKPOL_5_Pos                                                                            22U
+#define AON_REG_PAD_REG12X_PAD_P3_WKPOL_5_Msk                                                                            (0x1UL << AON_REG_PAD_REG12X_PAD_P3_WKPOL_5_Pos)
+
+#define AON_REG_PAD_REG12X_PAD_P3_SHDN_5_Pos                                                                             23U
+#define AON_REG_PAD_REG12X_PAD_P3_SHDN_5_Msk                                                                             (0x1UL << AON_REG_PAD_REG12X_PAD_P3_SHDN_5_Pos)
+
+#define AON_REG_PAD_REG12X_PAD_P3_DEB_5_Pos                                                                              24U
+#define AON_REG_PAD_REG12X_PAD_P3_DEB_5_Msk                                                                              (0x1UL << AON_REG_PAD_REG12X_PAD_P3_DEB_5_Pos)
+
+#define AON_REG_PAD_REG12X_PAD_P3_RAP_WKEN_5_Pos                                                                         25U
+#define AON_REG_PAD_REG12X_PAD_P3_RAP_WKEN_5_Msk                                                                         (0x1UL << AON_REG_PAD_REG12X_PAD_P3_RAP_WKEN_5_Pos)
+
+#define AON_REG_PAD_REG12X_PAD_P3_PPU_WKEN_5_Pos                                                                         26U
+#define AON_REG_PAD_REG12X_PAD_P3_PPU_WKEN_5_Msk                                                                         (0x1UL << AON_REG_PAD_REG12X_PAD_P3_PPU_WKEN_5_Pos)
+
+#define AON_REG_PAD_REG12X_RESERVED_1_Pos                                                                                27U
+#define AON_REG_PAD_REG12X_RESERVED_1_Msk                                                                                (0x1UL << AON_REG_PAD_REG12X_RESERVED_1_Pos)
+
+#define AON_REG_PAD_REG12X_RESERVED_Pos                                                                                  28U
+#define AON_REG_PAD_REG12X_RESERVED_Msk                                                                                  (0x3UL << AON_REG_PAD_REG12X_RESERVED_Pos)
+
+#define AON_REG_PAD_REG12X_PAD_P3_AON_MUX_5_Pos                                                                          30U
+#define AON_REG_PAD_REG12X_PAD_P3_AON_MUX_5_Msk                                                                          (0x3UL << AON_REG_PAD_REG12X_PAD_P3_AON_MUX_5_Pos)
+
+/* 0x154    0x4000_0154
+    0       R/W     PAD_P3_O_6                                                  1'b0
+    1       R/W     PAD_P3_E_6                                                  1'b0
+    2       R/W     PAD_P3_PU_EN_6                                              1'b1
+    3       R/W     AON_PAD_P3_PD_6                                             1'b1
+    4       R/W     PAD_P3_PUPDC_6                                              1'b0
+    5       R/W     PAD_P3_WKEN_6                                               1'b0
+    6       R/W     PAD_P3_WKPOL_6                                              1'b0
+    7       R/W     PAD_P3_SHDN_6                                               1'b1
+    8       R/W     PAD_P3_DEB_6                                                1'b0
+    9       R/W     PAD_P3_RAP_WKEN_6                                           1'b0
+    10      R/W     PAD_P3_PPU_WKEN_6                                           1'b0
+    11      R/W     RESERVED_2                                                  1'b0
+    13:12   R       RESERVED_1                                                  2'b00
+    15:14   R/W     PAD_P3_AON_MUX_6                                            2'b00
+    31:16   R       RESERVED                                                    16'h0
+ */
+typedef union _AON_REG_PAD_REG13X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t PAD_P3_O_6: 1;
+        uint32_t PAD_P3_E_6: 1;
+        uint32_t PAD_P3_PU_EN_6: 1;
+        uint32_t AON_PAD_P3_PD_6: 1;
+        uint32_t PAD_P3_PUPDC_6: 1;
+        uint32_t PAD_P3_WKEN_6: 1;
+        uint32_t PAD_P3_WKPOL_6: 1;
+        uint32_t PAD_P3_SHDN_6: 1;
+        uint32_t PAD_P3_DEB_6: 1;
+        uint32_t PAD_P3_RAP_WKEN_6: 1;
+        uint32_t PAD_P3_PPU_WKEN_6: 1;
+        uint32_t RESERVED_2: 1;
+        uint32_t RESERVED_1: 2;
+        uint32_t PAD_P3_AON_MUX_6: 2;
+        uint32_t RESERVED: 16;
+    };
+} AON_REG_PAD_REG13X_TYPE;
+
+/*0x4000_0154 AON_REG_PAD_REG13X*/
+#define AON_REG_PAD_REG13X_PAD_P3_O_6_Pos                                                                                0U
+#define AON_REG_PAD_REG13X_PAD_P3_O_6_Msk                                                                                (0x1UL << AON_REG_PAD_REG13X_PAD_P3_O_6_Pos)
+
+#define AON_REG_PAD_REG13X_PAD_P3_E_6_Pos                                                                                1U
+#define AON_REG_PAD_REG13X_PAD_P3_E_6_Msk                                                                                (0x1UL << AON_REG_PAD_REG13X_PAD_P3_E_6_Pos)
+
+#define AON_REG_PAD_REG13X_PAD_P3_PU_EN_6_Pos                                                                            2U
+#define AON_REG_PAD_REG13X_PAD_P3_PU_EN_6_Msk                                                                            (0x1UL << AON_REG_PAD_REG13X_PAD_P3_PU_EN_6_Pos)
+
+#define AON_REG_PAD_REG13X_AON_PAD_P3_PD_6_Pos                                                                           3U
+#define AON_REG_PAD_REG13X_AON_PAD_P3_PD_6_Msk                                                                           (0x1UL << AON_REG_PAD_REG13X_AON_PAD_P3_PD_6_Pos)
+
+#define AON_REG_PAD_REG13X_PAD_P3_PUPDC_6_Pos                                                                            4U
+#define AON_REG_PAD_REG13X_PAD_P3_PUPDC_6_Msk                                                                            (0x1UL << AON_REG_PAD_REG13X_PAD_P3_PUPDC_6_Pos)
+
+#define AON_REG_PAD_REG13X_PAD_P3_WKEN_6_Pos                                                                             5U
+#define AON_REG_PAD_REG13X_PAD_P3_WKEN_6_Msk                                                                             (0x1UL << AON_REG_PAD_REG13X_PAD_P3_WKEN_6_Pos)
+
+#define AON_REG_PAD_REG13X_PAD_P3_WKPOL_6_Pos                                                                            6U
+#define AON_REG_PAD_REG13X_PAD_P3_WKPOL_6_Msk                                                                            (0x1UL << AON_REG_PAD_REG13X_PAD_P3_WKPOL_6_Pos)
+
+#define AON_REG_PAD_REG13X_PAD_P3_SHDN_6_Pos                                                                             7U
+#define AON_REG_PAD_REG13X_PAD_P3_SHDN_6_Msk                                                                             (0x1UL << AON_REG_PAD_REG13X_PAD_P3_SHDN_6_Pos)
+
+#define AON_REG_PAD_REG13X_PAD_P3_DEB_6_Pos                                                                              8U
+#define AON_REG_PAD_REG13X_PAD_P3_DEB_6_Msk                                                                              (0x1UL << AON_REG_PAD_REG13X_PAD_P3_DEB_6_Pos)
+
+#define AON_REG_PAD_REG13X_PAD_P3_RAP_WKEN_6_Pos                                                                         9U
+#define AON_REG_PAD_REG13X_PAD_P3_RAP_WKEN_6_Msk                                                                         (0x1UL << AON_REG_PAD_REG13X_PAD_P3_RAP_WKEN_6_Pos)
+
+#define AON_REG_PAD_REG13X_PAD_P3_PPU_WKEN_6_Pos                                                                         10U
+#define AON_REG_PAD_REG13X_PAD_P3_PPU_WKEN_6_Msk                                                                         (0x1UL << AON_REG_PAD_REG13X_PAD_P3_PPU_WKEN_6_Pos)
+
+#define AON_REG_PAD_REG13X_RESERVED_2_Pos                                                                                11U
+#define AON_REG_PAD_REG13X_RESERVED_2_Msk                                                                                (0x1UL << AON_REG_PAD_REG13X_RESERVED_2_Pos)
+
+#define AON_REG_PAD_REG13X_RESERVED_1_Pos                                                                                12U
+#define AON_REG_PAD_REG13X_RESERVED_1_Msk                                                                                (0x3UL << AON_REG_PAD_REG13X_RESERVED_1_Pos)
+
+#define AON_REG_PAD_REG13X_PAD_P3_AON_MUX_6_Pos                                                                          14U
+#define AON_REG_PAD_REG13X_PAD_P3_AON_MUX_6_Msk                                                                          (0x3UL << AON_REG_PAD_REG13X_PAD_P3_AON_MUX_6_Pos)
+
+#define AON_REG_PAD_REG13X_RESERVED_Pos                                                                                  16U
+#define AON_REG_PAD_REG13X_RESERVED_Msk                                                                                  (0xFFFFUL << AON_REG_PAD_REG13X_RESERVED_Pos)
+
+/* 0x158    0x4000_0158
+    0       R/W     PAD_P4_O_0                                                  1'b0
+    1       R/W     PAD_P4_E_0                                                  1'b0
+    2       R/W     PAD_P4_PU_EN_0                                              1'b1
+    3       R/W     AON_PAD_P4_PD_0                                             1'b1
+    4       R/W     PAD_P4_PUPDC_0                                              1'b0
+    5       R/W     PAD_P4_WKEN_0                                               1'b0
+    6       R/W     PAD_P4_WKPOL_0                                              1'b0
+    7       R/W     PAD_P4_SHDN_0                                               1'b1
+    8       R/W     PAD_P4_DEB_0                                                1'b0
+    9       R/W     PAD_P4_RAP_WKEN_0                                           1'b0
+    10      R/W     PAD_P4_PPU_WKEN_0                                           1'b0
+    11      R/W     RESERVED_3                                                  1'b0
+    13:12   R       RESERVED_2                                                  2'b00
+    15:14   R/W     PAD_P4_AON_MUX_0                                            2'b00
+    16      R/W     PAD_P4_O_1                                                  1'b0
+    17      R/W     PAD_P4_E_1                                                  1'b0
+    18      R/W     PAD_P4_PU_EN_1                                              1'b1
+    19      R/W     AON_PAD_P4_PD_1                                             1'b1
+    20      R/W     PAD_P4_PUPDC_1                                              1'b0
+    21      R/W     PAD_P4_WKEN_1                                               1'b0
+    22      R/W     PAD_P4_WKPOL_1                                              1'b0
+    23      R/W     PAD_P4_SHDN_1                                               1'b1
+    24      R/W     PAD_P4_DEB_1                                                1'b0
+    25      R/W     PAD_P4_RAP_WKEN_1                                           1'b0
+    26      R/W     PAD_P4_PPU_WKEN_1                                           1'b0
+    27      R/W     RESERVED_1                                                  1'b0
+    29:28   R       RESERVED                                                    2'b00
+    31:30   R/W     PAD_P4_AON_MUX_1                                            2'b00
+ */
+typedef union _AON_REG_PAD_REG14X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t PAD_P4_O_0: 1;
+        uint32_t PAD_P4_E_0: 1;
+        uint32_t PAD_P4_PU_EN_0: 1;
+        uint32_t AON_PAD_P4_PD_0: 1;
+        uint32_t PAD_P4_PUPDC_0: 1;
+        uint32_t PAD_P4_WKEN_0: 1;
+        uint32_t PAD_P4_WKPOL_0: 1;
+        uint32_t PAD_P4_SHDN_0: 1;
+        uint32_t PAD_P4_DEB_0: 1;
+        uint32_t PAD_P4_RAP_WKEN_0: 1;
+        uint32_t PAD_P4_PPU_WKEN_0: 1;
+        uint32_t RESERVED_3: 1;
+        uint32_t RESERVED_2: 2;
+        uint32_t PAD_P4_AON_MUX_0: 2;
+        uint32_t PAD_P4_O_1: 1;
+        uint32_t PAD_P4_E_1: 1;
+        uint32_t PAD_P4_PU_EN_1: 1;
+        uint32_t AON_PAD_P4_PD_1: 1;
+        uint32_t PAD_P4_PUPDC_1: 1;
+        uint32_t PAD_P4_WKEN_1: 1;
+        uint32_t PAD_P4_WKPOL_1: 1;
+        uint32_t PAD_P4_SHDN_1: 1;
+        uint32_t PAD_P4_DEB_1: 1;
+        uint32_t PAD_P4_RAP_WKEN_1: 1;
+        uint32_t PAD_P4_PPU_WKEN_1: 1;
+        uint32_t RESERVED_1: 1;
+        uint32_t RESERVED: 2;
+        uint32_t PAD_P4_AON_MUX_1: 2;
+    };
+} AON_REG_PAD_REG14X_TYPE;
+
+/*0x4000_0158 AON_REG_PAD_REG14X*/
+#define AON_REG_PAD_REG14X_PAD_P4_O_0_Pos                                                                                0U
+#define AON_REG_PAD_REG14X_PAD_P4_O_0_Msk                                                                                (0x1UL << AON_REG_PAD_REG14X_PAD_P4_O_0_Pos)
+
+#define AON_REG_PAD_REG14X_PAD_P4_E_0_Pos                                                                                1U
+#define AON_REG_PAD_REG14X_PAD_P4_E_0_Msk                                                                                (0x1UL << AON_REG_PAD_REG14X_PAD_P4_E_0_Pos)
+
+#define AON_REG_PAD_REG14X_PAD_P4_PU_EN_0_Pos                                                                            2U
+#define AON_REG_PAD_REG14X_PAD_P4_PU_EN_0_Msk                                                                            (0x1UL << AON_REG_PAD_REG14X_PAD_P4_PU_EN_0_Pos)
+
+#define AON_REG_PAD_REG14X_AON_PAD_P4_PD_0_Pos                                                                           3U
+#define AON_REG_PAD_REG14X_AON_PAD_P4_PD_0_Msk                                                                           (0x1UL << AON_REG_PAD_REG14X_AON_PAD_P4_PD_0_Pos)
+
+#define AON_REG_PAD_REG14X_PAD_P4_PUPDC_0_Pos                                                                            4U
+#define AON_REG_PAD_REG14X_PAD_P4_PUPDC_0_Msk                                                                            (0x1UL << AON_REG_PAD_REG14X_PAD_P4_PUPDC_0_Pos)
+
+#define AON_REG_PAD_REG14X_PAD_P4_WKEN_0_Pos                                                                             5U
+#define AON_REG_PAD_REG14X_PAD_P4_WKEN_0_Msk                                                                             (0x1UL << AON_REG_PAD_REG14X_PAD_P4_WKEN_0_Pos)
+
+#define AON_REG_PAD_REG14X_PAD_P4_WKPOL_0_Pos                                                                            6U
+#define AON_REG_PAD_REG14X_PAD_P4_WKPOL_0_Msk                                                                            (0x1UL << AON_REG_PAD_REG14X_PAD_P4_WKPOL_0_Pos)
+
+#define AON_REG_PAD_REG14X_PAD_P4_SHDN_0_Pos                                                                             7U
+#define AON_REG_PAD_REG14X_PAD_P4_SHDN_0_Msk                                                                             (0x1UL << AON_REG_PAD_REG14X_PAD_P4_SHDN_0_Pos)
+
+#define AON_REG_PAD_REG14X_PAD_P4_DEB_0_Pos                                                                              8U
+#define AON_REG_PAD_REG14X_PAD_P4_DEB_0_Msk                                                                              (0x1UL << AON_REG_PAD_REG14X_PAD_P4_DEB_0_Pos)
+
+#define AON_REG_PAD_REG14X_PAD_P4_RAP_WKEN_0_Pos                                                                         9U
+#define AON_REG_PAD_REG14X_PAD_P4_RAP_WKEN_0_Msk                                                                         (0x1UL << AON_REG_PAD_REG14X_PAD_P4_RAP_WKEN_0_Pos)
+
+#define AON_REG_PAD_REG14X_PAD_P4_PPU_WKEN_0_Pos                                                                         10U
+#define AON_REG_PAD_REG14X_PAD_P4_PPU_WKEN_0_Msk                                                                         (0x1UL << AON_REG_PAD_REG14X_PAD_P4_PPU_WKEN_0_Pos)
+
+#define AON_REG_PAD_REG14X_RESERVED_3_Pos                                                                                11U
+#define AON_REG_PAD_REG14X_RESERVED_3_Msk                                                                                (0x1UL << AON_REG_PAD_REG14X_RESERVED_3_Pos)
+
+#define AON_REG_PAD_REG14X_RESERVED_2_Pos                                                                                12U
+#define AON_REG_PAD_REG14X_RESERVED_2_Msk                                                                                (0x3UL << AON_REG_PAD_REG14X_RESERVED_2_Pos)
+
+#define AON_REG_PAD_REG14X_PAD_P4_AON_MUX_0_Pos                                                                          14U
+#define AON_REG_PAD_REG14X_PAD_P4_AON_MUX_0_Msk                                                                          (0x3UL << AON_REG_PAD_REG14X_PAD_P4_AON_MUX_0_Pos)
+
+#define AON_REG_PAD_REG14X_PAD_P4_O_1_Pos                                                                                16U
+#define AON_REG_PAD_REG14X_PAD_P4_O_1_Msk                                                                                (0x1UL << AON_REG_PAD_REG14X_PAD_P4_O_1_Pos)
+
+#define AON_REG_PAD_REG14X_PAD_P4_E_1_Pos                                                                                17U
+#define AON_REG_PAD_REG14X_PAD_P4_E_1_Msk                                                                                (0x1UL << AON_REG_PAD_REG14X_PAD_P4_E_1_Pos)
+
+#define AON_REG_PAD_REG14X_PAD_P4_PU_EN_1_Pos                                                                            18U
+#define AON_REG_PAD_REG14X_PAD_P4_PU_EN_1_Msk                                                                            (0x1UL << AON_REG_PAD_REG14X_PAD_P4_PU_EN_1_Pos)
+
+#define AON_REG_PAD_REG14X_AON_PAD_P4_PD_1_Pos                                                                           19U
+#define AON_REG_PAD_REG14X_AON_PAD_P4_PD_1_Msk                                                                           (0x1UL << AON_REG_PAD_REG14X_AON_PAD_P4_PD_1_Pos)
+
+#define AON_REG_PAD_REG14X_PAD_P4_PUPDC_1_Pos                                                                            20U
+#define AON_REG_PAD_REG14X_PAD_P4_PUPDC_1_Msk                                                                            (0x1UL << AON_REG_PAD_REG14X_PAD_P4_PUPDC_1_Pos)
+
+#define AON_REG_PAD_REG14X_PAD_P4_WKEN_1_Pos                                                                             21U
+#define AON_REG_PAD_REG14X_PAD_P4_WKEN_1_Msk                                                                             (0x1UL << AON_REG_PAD_REG14X_PAD_P4_WKEN_1_Pos)
+
+#define AON_REG_PAD_REG14X_PAD_P4_WKPOL_1_Pos                                                                            22U
+#define AON_REG_PAD_REG14X_PAD_P4_WKPOL_1_Msk                                                                            (0x1UL << AON_REG_PAD_REG14X_PAD_P4_WKPOL_1_Pos)
+
+#define AON_REG_PAD_REG14X_PAD_P4_SHDN_1_Pos                                                                             23U
+#define AON_REG_PAD_REG14X_PAD_P4_SHDN_1_Msk                                                                             (0x1UL << AON_REG_PAD_REG14X_PAD_P4_SHDN_1_Pos)
+
+#define AON_REG_PAD_REG14X_PAD_P4_DEB_1_Pos                                                                              24U
+#define AON_REG_PAD_REG14X_PAD_P4_DEB_1_Msk                                                                              (0x1UL << AON_REG_PAD_REG14X_PAD_P4_DEB_1_Pos)
+
+#define AON_REG_PAD_REG14X_PAD_P4_RAP_WKEN_1_Pos                                                                         25U
+#define AON_REG_PAD_REG14X_PAD_P4_RAP_WKEN_1_Msk                                                                         (0x1UL << AON_REG_PAD_REG14X_PAD_P4_RAP_WKEN_1_Pos)
+
+#define AON_REG_PAD_REG14X_PAD_P4_PPU_WKEN_1_Pos                                                                         26U
+#define AON_REG_PAD_REG14X_PAD_P4_PPU_WKEN_1_Msk                                                                         (0x1UL << AON_REG_PAD_REG14X_PAD_P4_PPU_WKEN_1_Pos)
+
+#define AON_REG_PAD_REG14X_RESERVED_1_Pos                                                                                27U
+#define AON_REG_PAD_REG14X_RESERVED_1_Msk                                                                                (0x1UL << AON_REG_PAD_REG14X_RESERVED_1_Pos)
+
+#define AON_REG_PAD_REG14X_RESERVED_Pos                                                                                  28U
+#define AON_REG_PAD_REG14X_RESERVED_Msk                                                                                  (0x3UL << AON_REG_PAD_REG14X_RESERVED_Pos)
+
+#define AON_REG_PAD_REG14X_PAD_P4_AON_MUX_1_Pos                                                                          30U
+#define AON_REG_PAD_REG14X_PAD_P4_AON_MUX_1_Msk                                                                          (0x3UL << AON_REG_PAD_REG14X_PAD_P4_AON_MUX_1_Pos)
+
+/* 0x15C    0x4000_015c
+    0       R/W     PAD_P4_O_2                                                  1'b0
+    1       R/W     PAD_P4_E_2                                                  1'b0
+    2       R/W     PAD_P4_PU_EN_2                                              1'b1
+    3       R/W     AON_PAD_P4_PD_2                                             1'b1
+    4       R/W     PAD_P4_PUPDC_2                                              1'b0
+    5       R/W     PAD_P4_WKEN_2                                               1'b0
+    6       R/W     PAD_P4_WKPOL_2                                              1'b0
+    7       R/W     PAD_P4_SHDN_2                                               1'b1
+    8       R/W     PAD_P4_DEB_2                                                1'b0
+    9       R/W     PAD_P4_RAP_WKEN_2                                           1'b0
+    10      R/W     PAD_P4_PPU_WKEN_2                                           1'b0
+    11      R/W     RESERVED_3                                                  1'b0
+    13:12   R       RESERVED_2                                                  2'b00
+    15:14   R/W     PAD_P4_AON_MUX_2                                            2'b00
+    16      R/W     PAD_P4_O_3                                                  1'b0
+    17      R/W     PAD_P4_E_3                                                  1'b0
+    18      R/W     PAD_P4_PU_EN_3                                              1'b1
+    19      R/W     AON_PAD_P4_PD_3                                             1'b0
+    20      R/W     PAD_P4_PUPDC_3                                              1'b0
+    21      R/W     PAD_P4_WKEN_3                                               1'b0
+    22      R/W     PAD_P4_WKPOL_3                                              1'b0
+    23      R/W     PAD_P4_SHDN_3                                               1'b1
+    24      R/W     PAD_P4_DEB_3                                                1'b0
+    25      R/W     PAD_P4_RAP_WKEN_3                                           1'b0
+    26      R/W     PAD_P4_PPU_WKEN_3                                           1'b0
+    27      R/W     RESERVED_1                                                  1'b0
+    29:28   R       RESERVED                                                    2'b00
+    31:30   R/W     PAD_P4_AON_MUX_3                                            2'b00
+ */
+typedef union _AON_REG_PAD_REG15X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t PAD_P4_O_2: 1;
+        uint32_t PAD_P4_E_2: 1;
+        uint32_t PAD_P4_PU_EN_2: 1;
+        uint32_t AON_PAD_P4_PD_2: 1;
+        uint32_t PAD_P4_PUPDC_2: 1;
+        uint32_t PAD_P4_WKEN_2: 1;
+        uint32_t PAD_P4_WKPOL_2: 1;
+        uint32_t PAD_P4_SHDN_2: 1;
+        uint32_t PAD_P4_DEB_2: 1;
+        uint32_t PAD_P4_RAP_WKEN_2: 1;
+        uint32_t PAD_P4_PPU_WKEN_2: 1;
+        uint32_t RESERVED_3: 1;
+        uint32_t RESERVED_2: 2;
+        uint32_t PAD_P4_AON_MUX_2: 2;
+        uint32_t PAD_P4_O_3: 1;
+        uint32_t PAD_P4_E_3: 1;
+        uint32_t PAD_P4_PU_EN_3: 1;
+        uint32_t AON_PAD_P4_PD_3: 1;
+        uint32_t PAD_P4_PUPDC_3: 1;
+        uint32_t PAD_P4_WKEN_3: 1;
+        uint32_t PAD_P4_WKPOL_3: 1;
+        uint32_t PAD_P4_SHDN_3: 1;
+        uint32_t PAD_P4_DEB_3: 1;
+        uint32_t PAD_P4_RAP_WKEN_3: 1;
+        uint32_t PAD_P4_PPU_WKEN_3: 1;
+        uint32_t RESERVED_1: 1;
+        uint32_t RESERVED: 2;
+        uint32_t PAD_P4_AON_MUX_3: 2;
+    };
+} AON_REG_PAD_REG15X_TYPE;
+
+/*0x4000_015c AON_REG_PAD_REG15X*/
+#define AON_REG_PAD_REG15X_PAD_P4_O_2_Pos                                                                                0U
+#define AON_REG_PAD_REG15X_PAD_P4_O_2_Msk                                                                                (0x1UL << AON_REG_PAD_REG15X_PAD_P4_O_2_Pos)
+
+#define AON_REG_PAD_REG15X_PAD_P4_E_2_Pos                                                                                1U
+#define AON_REG_PAD_REG15X_PAD_P4_E_2_Msk                                                                                (0x1UL << AON_REG_PAD_REG15X_PAD_P4_E_2_Pos)
+
+#define AON_REG_PAD_REG15X_PAD_P4_PU_EN_2_Pos                                                                            2U
+#define AON_REG_PAD_REG15X_PAD_P4_PU_EN_2_Msk                                                                            (0x1UL << AON_REG_PAD_REG15X_PAD_P4_PU_EN_2_Pos)
+
+#define AON_REG_PAD_REG15X_AON_PAD_P4_PD_2_Pos                                                                           3U
+#define AON_REG_PAD_REG15X_AON_PAD_P4_PD_2_Msk                                                                           (0x1UL << AON_REG_PAD_REG15X_AON_PAD_P4_PD_2_Pos)
+
+#define AON_REG_PAD_REG15X_PAD_P4_PUPDC_2_Pos                                                                            4U
+#define AON_REG_PAD_REG15X_PAD_P4_PUPDC_2_Msk                                                                            (0x1UL << AON_REG_PAD_REG15X_PAD_P4_PUPDC_2_Pos)
+
+#define AON_REG_PAD_REG15X_PAD_P4_WKEN_2_Pos                                                                             5U
+#define AON_REG_PAD_REG15X_PAD_P4_WKEN_2_Msk                                                                             (0x1UL << AON_REG_PAD_REG15X_PAD_P4_WKEN_2_Pos)
+
+#define AON_REG_PAD_REG15X_PAD_P4_WKPOL_2_Pos                                                                            6U
+#define AON_REG_PAD_REG15X_PAD_P4_WKPOL_2_Msk                                                                            (0x1UL << AON_REG_PAD_REG15X_PAD_P4_WKPOL_2_Pos)
+
+#define AON_REG_PAD_REG15X_PAD_P4_SHDN_2_Pos                                                                             7U
+#define AON_REG_PAD_REG15X_PAD_P4_SHDN_2_Msk                                                                             (0x1UL << AON_REG_PAD_REG15X_PAD_P4_SHDN_2_Pos)
+
+#define AON_REG_PAD_REG15X_PAD_P4_DEB_2_Pos                                                                              8U
+#define AON_REG_PAD_REG15X_PAD_P4_DEB_2_Msk                                                                              (0x1UL << AON_REG_PAD_REG15X_PAD_P4_DEB_2_Pos)
+
+#define AON_REG_PAD_REG15X_PAD_P4_RAP_WKEN_2_Pos                                                                         9U
+#define AON_REG_PAD_REG15X_PAD_P4_RAP_WKEN_2_Msk                                                                         (0x1UL << AON_REG_PAD_REG15X_PAD_P4_RAP_WKEN_2_Pos)
+
+#define AON_REG_PAD_REG15X_PAD_P4_PPU_WKEN_2_Pos                                                                         10U
+#define AON_REG_PAD_REG15X_PAD_P4_PPU_WKEN_2_Msk                                                                         (0x1UL << AON_REG_PAD_REG15X_PAD_P4_PPU_WKEN_2_Pos)
+
+#define AON_REG_PAD_REG15X_RESERVED_3_Pos                                                                                11U
+#define AON_REG_PAD_REG15X_RESERVED_3_Msk                                                                                (0x1UL << AON_REG_PAD_REG15X_RESERVED_3_Pos)
+
+#define AON_REG_PAD_REG15X_RESERVED_2_Pos                                                                                12U
+#define AON_REG_PAD_REG15X_RESERVED_2_Msk                                                                                (0x3UL << AON_REG_PAD_REG15X_RESERVED_2_Pos)
+
+#define AON_REG_PAD_REG15X_PAD_P4_AON_MUX_2_Pos                                                                          14U
+#define AON_REG_PAD_REG15X_PAD_P4_AON_MUX_2_Msk                                                                          (0x3UL << AON_REG_PAD_REG15X_PAD_P4_AON_MUX_2_Pos)
+
+#define AON_REG_PAD_REG15X_PAD_P4_O_3_Pos                                                                                16U
+#define AON_REG_PAD_REG15X_PAD_P4_O_3_Msk                                                                                (0x1UL << AON_REG_PAD_REG15X_PAD_P4_O_3_Pos)
+
+#define AON_REG_PAD_REG15X_PAD_P4_E_3_Pos                                                                                17U
+#define AON_REG_PAD_REG15X_PAD_P4_E_3_Msk                                                                                (0x1UL << AON_REG_PAD_REG15X_PAD_P4_E_3_Pos)
+
+#define AON_REG_PAD_REG15X_PAD_P4_PU_EN_3_Pos                                                                            18U
+#define AON_REG_PAD_REG15X_PAD_P4_PU_EN_3_Msk                                                                            (0x1UL << AON_REG_PAD_REG15X_PAD_P4_PU_EN_3_Pos)
+
+#define AON_REG_PAD_REG15X_AON_PAD_P4_PD_3_Pos                                                                           19U
+#define AON_REG_PAD_REG15X_AON_PAD_P4_PD_3_Msk                                                                           (0x1UL << AON_REG_PAD_REG15X_AON_PAD_P4_PD_3_Pos)
+
+#define AON_REG_PAD_REG15X_PAD_P4_PUPDC_3_Pos                                                                            20U
+#define AON_REG_PAD_REG15X_PAD_P4_PUPDC_3_Msk                                                                            (0x1UL << AON_REG_PAD_REG15X_PAD_P4_PUPDC_3_Pos)
+
+#define AON_REG_PAD_REG15X_PAD_P4_WKEN_3_Pos                                                                             21U
+#define AON_REG_PAD_REG15X_PAD_P4_WKEN_3_Msk                                                                             (0x1UL << AON_REG_PAD_REG15X_PAD_P4_WKEN_3_Pos)
+
+#define AON_REG_PAD_REG15X_PAD_P4_WKPOL_3_Pos                                                                            22U
+#define AON_REG_PAD_REG15X_PAD_P4_WKPOL_3_Msk                                                                            (0x1UL << AON_REG_PAD_REG15X_PAD_P4_WKPOL_3_Pos)
+
+#define AON_REG_PAD_REG15X_PAD_P4_SHDN_3_Pos                                                                             23U
+#define AON_REG_PAD_REG15X_PAD_P4_SHDN_3_Msk                                                                             (0x1UL << AON_REG_PAD_REG15X_PAD_P4_SHDN_3_Pos)
+
+#define AON_REG_PAD_REG15X_PAD_P4_DEB_3_Pos                                                                              24U
+#define AON_REG_PAD_REG15X_PAD_P4_DEB_3_Msk                                                                              (0x1UL << AON_REG_PAD_REG15X_PAD_P4_DEB_3_Pos)
+
+#define AON_REG_PAD_REG15X_PAD_P4_RAP_WKEN_3_Pos                                                                         25U
+#define AON_REG_PAD_REG15X_PAD_P4_RAP_WKEN_3_Msk                                                                         (0x1UL << AON_REG_PAD_REG15X_PAD_P4_RAP_WKEN_3_Pos)
+
+#define AON_REG_PAD_REG15X_PAD_P4_PPU_WKEN_3_Pos                                                                         26U
+#define AON_REG_PAD_REG15X_PAD_P4_PPU_WKEN_3_Msk                                                                         (0x1UL << AON_REG_PAD_REG15X_PAD_P4_PPU_WKEN_3_Pos)
+
+#define AON_REG_PAD_REG15X_RESERVED_1_Pos                                                                                27U
+#define AON_REG_PAD_REG15X_RESERVED_1_Msk                                                                                (0x1UL << AON_REG_PAD_REG15X_RESERVED_1_Pos)
+
+#define AON_REG_PAD_REG15X_RESERVED_Pos                                                                                  28U
+#define AON_REG_PAD_REG15X_RESERVED_Msk                                                                                  (0x3UL << AON_REG_PAD_REG15X_RESERVED_Pos)
+
+#define AON_REG_PAD_REG15X_PAD_P4_AON_MUX_3_Pos                                                                          30U
+#define AON_REG_PAD_REG15X_PAD_P4_AON_MUX_3_Msk                                                                          (0x3UL << AON_REG_PAD_REG15X_PAD_P4_AON_MUX_3_Pos)
+
+/* 0x160    0x4000_0160
+    0       R/W     PAD_P5_O_1                                                  1'b0
+    1       R/W     PAD_P5_E_1                                                  1'b0
+    2       R/W     PAD_P5_PU_EN_1                                              1'b1
+    3       R/W     AON_PAD_P5_PD_1                                             1'b1
+    4       R/W     PAD_P5_PUPDC_1                                              1'b0
+    5       R/W     PAD_P5_WKEN_1                                               1'b0
+    6       R/W     PAD_P5_WKPOL_1                                              1'b0
+    7       R/W     PAD_P5_SHDN_1                                               1'b1
+    8       R/W     PAD_P5_DEB_1                                                1'b0
+    9       R/W     PAD_P5_RAP_WKEN_1                                           1'b0
+    10      R/W     PAD_P5_PPU_WKEN_1                                           1'b0
+    11      R/W     RESERVED_4                                                  1'b0
+    12      R/W     RESERVED_3                                                  1'b0
+    13      R       RESERVED_2                                                  1'b0
+    15:14   R/W     PAD_P5_AON_MUX_1                                            2'b00
+    16      R/W     PAD_P5_O_2                                                  1'b0
+    17      R/W     PAD_P5_E_2                                                  1'b0
+    18      R/W     PAD_P5_PU_EN_2                                              1'b1
+    19      R/W     AON_PAD_P5_PD_2                                             1'b1
+    20      R/W     PAD_P5_PUPDC_2                                              1'b0
+    21      R/W     PAD_P5_WKEN_2                                               1'b0
+    22      R/W     PAD_P5_WKPOL_2                                              1'b0
+    23      R/W     PAD_P5_SHDN_2                                               1'b1
+    24      R/W     PAD_P5_DEB_2                                                1'b0
+    25      R/W     PAD_P5_RAP_WKEN_2                                           1'b0
+    26      R/W     PAD_P5_PPU_WKEN_2                                           1'b0
+    27      R/W     RESERVED_1                                                  1'b0
+    29:28   R       RESERVED                                                    2'b00
+    31:30   R/W     PAD_P5_AON_MUX_2                                            2'b00
+ */
+typedef union _AON_REG_PAD_REG16X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t PAD_P5_O_1: 1;
+        uint32_t PAD_P5_E_1: 1;
+        uint32_t PAD_P5_PU_EN_1: 1;
+        uint32_t AON_PAD_P5_PD_1: 1;
+        uint32_t PAD_P5_PUPDC_1: 1;
+        uint32_t PAD_P5_WKEN_1: 1;
+        uint32_t PAD_P5_WKPOL_1: 1;
+        uint32_t PAD_P5_SHDN_1: 1;
+        uint32_t PAD_P5_DEB_1: 1;
+        uint32_t PAD_P5_RAP_WKEN_1: 1;
+        uint32_t PAD_P5_PPU_WKEN_1: 1;
+        uint32_t RESERVED_4: 1;
+        uint32_t RESERVED_3: 1;
+        uint32_t RESERVED_2: 1;
+        uint32_t PAD_P5_AON_MUX_1: 2;
+        uint32_t PAD_P5_O_2: 1;
+        uint32_t PAD_P5_E_2: 1;
+        uint32_t PAD_P5_PU_EN_2: 1;
+        uint32_t AON_PAD_P5_PD_2: 1;
+        uint32_t PAD_P5_PUPDC_2: 1;
+        uint32_t PAD_P5_WKEN_2: 1;
+        uint32_t PAD_P5_WKPOL_2: 1;
+        uint32_t PAD_P5_SHDN_2: 1;
+        uint32_t PAD_P5_DEB_2: 1;
+        uint32_t PAD_P5_RAP_WKEN_2: 1;
+        uint32_t PAD_P5_PPU_WKEN_2: 1;
+        uint32_t RESERVED_1: 1;
+        uint32_t RESERVED: 2;
+        uint32_t PAD_P5_AON_MUX_2: 2;
+    };
+} AON_REG_PAD_REG16X_TYPE;
+
+/*0x4000_0160 AON_REG_PAD_REG16X*/
+#define AON_REG_PAD_REG16X_PAD_P5_O_1_Pos                                                                                0U
+#define AON_REG_PAD_REG16X_PAD_P5_O_1_Msk                                                                                (0x1UL << AON_REG_PAD_REG16X_PAD_P5_O_1_Pos)
+
+#define AON_REG_PAD_REG16X_PAD_P5_E_1_Pos                                                                                1U
+#define AON_REG_PAD_REG16X_PAD_P5_E_1_Msk                                                                                (0x1UL << AON_REG_PAD_REG16X_PAD_P5_E_1_Pos)
+
+#define AON_REG_PAD_REG16X_PAD_P5_PU_EN_1_Pos                                                                            2U
+#define AON_REG_PAD_REG16X_PAD_P5_PU_EN_1_Msk                                                                            (0x1UL << AON_REG_PAD_REG16X_PAD_P5_PU_EN_1_Pos)
+
+#define AON_REG_PAD_REG16X_AON_PAD_P5_PD_1_Pos                                                                           3U
+#define AON_REG_PAD_REG16X_AON_PAD_P5_PD_1_Msk                                                                           (0x1UL << AON_REG_PAD_REG16X_AON_PAD_P5_PD_1_Pos)
+
+#define AON_REG_PAD_REG16X_PAD_P5_PUPDC_1_Pos                                                                            4U
+#define AON_REG_PAD_REG16X_PAD_P5_PUPDC_1_Msk                                                                            (0x1UL << AON_REG_PAD_REG16X_PAD_P5_PUPDC_1_Pos)
+
+#define AON_REG_PAD_REG16X_PAD_P5_WKEN_1_Pos                                                                             5U
+#define AON_REG_PAD_REG16X_PAD_P5_WKEN_1_Msk                                                                             (0x1UL << AON_REG_PAD_REG16X_PAD_P5_WKEN_1_Pos)
+
+#define AON_REG_PAD_REG16X_PAD_P5_WKPOL_1_Pos                                                                            6U
+#define AON_REG_PAD_REG16X_PAD_P5_WKPOL_1_Msk                                                                            (0x1UL << AON_REG_PAD_REG16X_PAD_P5_WKPOL_1_Pos)
+
+#define AON_REG_PAD_REG16X_PAD_P5_SHDN_1_Pos                                                                             7U
+#define AON_REG_PAD_REG16X_PAD_P5_SHDN_1_Msk                                                                             (0x1UL << AON_REG_PAD_REG16X_PAD_P5_SHDN_1_Pos)
+
+#define AON_REG_PAD_REG16X_PAD_P5_DEB_1_Pos                                                                              8U
+#define AON_REG_PAD_REG16X_PAD_P5_DEB_1_Msk                                                                              (0x1UL << AON_REG_PAD_REG16X_PAD_P5_DEB_1_Pos)
+
+#define AON_REG_PAD_REG16X_PAD_P5_RAP_WKEN_1_Pos                                                                         9U
+#define AON_REG_PAD_REG16X_PAD_P5_RAP_WKEN_1_Msk                                                                         (0x1UL << AON_REG_PAD_REG16X_PAD_P5_RAP_WKEN_1_Pos)
+
+#define AON_REG_PAD_REG16X_PAD_P5_PPU_WKEN_1_Pos                                                                         10U
+#define AON_REG_PAD_REG16X_PAD_P5_PPU_WKEN_1_Msk                                                                         (0x1UL << AON_REG_PAD_REG16X_PAD_P5_PPU_WKEN_1_Pos)
+
+#define AON_REG_PAD_REG16X_RESERVED_4_Pos                                                                                11U
+#define AON_REG_PAD_REG16X_RESERVED_4_Msk                                                                                (0x1UL << AON_REG_PAD_REG16X_RESERVED_4_Pos)
+
+#define AON_REG_PAD_REG16X_RESERVED_3_Pos                                                                                12U
+#define AON_REG_PAD_REG16X_RESERVED_3_Msk                                                                                (0x1UL << AON_REG_PAD_REG16X_RESERVED_3_Pos)
+
+#define AON_REG_PAD_REG16X_RESERVED_2_Pos                                                                                13U
+#define AON_REG_PAD_REG16X_RESERVED_2_Msk                                                                                (0x1UL << AON_REG_PAD_REG16X_RESERVED_2_Pos)
+
+#define AON_REG_PAD_REG16X_PAD_P5_AON_MUX_1_Pos                                                                          14U
+#define AON_REG_PAD_REG16X_PAD_P5_AON_MUX_1_Msk                                                                          (0x3UL << AON_REG_PAD_REG16X_PAD_P5_AON_MUX_1_Pos)
+
+#define AON_REG_PAD_REG16X_PAD_P5_O_2_Pos                                                                                16U
+#define AON_REG_PAD_REG16X_PAD_P5_O_2_Msk                                                                                (0x1UL << AON_REG_PAD_REG16X_PAD_P5_O_2_Pos)
+
+#define AON_REG_PAD_REG16X_PAD_P5_E_2_Pos                                                                                17U
+#define AON_REG_PAD_REG16X_PAD_P5_E_2_Msk                                                                                (0x1UL << AON_REG_PAD_REG16X_PAD_P5_E_2_Pos)
+
+#define AON_REG_PAD_REG16X_PAD_P5_PU_EN_2_Pos                                                                            18U
+#define AON_REG_PAD_REG16X_PAD_P5_PU_EN_2_Msk                                                                            (0x1UL << AON_REG_PAD_REG16X_PAD_P5_PU_EN_2_Pos)
+
+#define AON_REG_PAD_REG16X_AON_PAD_P5_PD_2_Pos                                                                           19U
+#define AON_REG_PAD_REG16X_AON_PAD_P5_PD_2_Msk                                                                           (0x1UL << AON_REG_PAD_REG16X_AON_PAD_P5_PD_2_Pos)
+
+#define AON_REG_PAD_REG16X_PAD_P5_PUPDC_2_Pos                                                                            20U
+#define AON_REG_PAD_REG16X_PAD_P5_PUPDC_2_Msk                                                                            (0x1UL << AON_REG_PAD_REG16X_PAD_P5_PUPDC_2_Pos)
+
+#define AON_REG_PAD_REG16X_PAD_P5_WKEN_2_Pos                                                                             21U
+#define AON_REG_PAD_REG16X_PAD_P5_WKEN_2_Msk                                                                             (0x1UL << AON_REG_PAD_REG16X_PAD_P5_WKEN_2_Pos)
+
+#define AON_REG_PAD_REG16X_PAD_P5_WKPOL_2_Pos                                                                            22U
+#define AON_REG_PAD_REG16X_PAD_P5_WKPOL_2_Msk                                                                            (0x1UL << AON_REG_PAD_REG16X_PAD_P5_WKPOL_2_Pos)
+
+#define AON_REG_PAD_REG16X_PAD_P5_SHDN_2_Pos                                                                             23U
+#define AON_REG_PAD_REG16X_PAD_P5_SHDN_2_Msk                                                                             (0x1UL << AON_REG_PAD_REG16X_PAD_P5_SHDN_2_Pos)
+
+#define AON_REG_PAD_REG16X_PAD_P5_DEB_2_Pos                                                                              24U
+#define AON_REG_PAD_REG16X_PAD_P5_DEB_2_Msk                                                                              (0x1UL << AON_REG_PAD_REG16X_PAD_P5_DEB_2_Pos)
+
+#define AON_REG_PAD_REG16X_PAD_P5_RAP_WKEN_2_Pos                                                                         25U
+#define AON_REG_PAD_REG16X_PAD_P5_RAP_WKEN_2_Msk                                                                         (0x1UL << AON_REG_PAD_REG16X_PAD_P5_RAP_WKEN_2_Pos)
+
+#define AON_REG_PAD_REG16X_PAD_P5_PPU_WKEN_2_Pos                                                                         26U
+#define AON_REG_PAD_REG16X_PAD_P5_PPU_WKEN_2_Msk                                                                         (0x1UL << AON_REG_PAD_REG16X_PAD_P5_PPU_WKEN_2_Pos)
+
+#define AON_REG_PAD_REG16X_RESERVED_1_Pos                                                                                27U
+#define AON_REG_PAD_REG16X_RESERVED_1_Msk                                                                                (0x1UL << AON_REG_PAD_REG16X_RESERVED_1_Pos)
+
+#define AON_REG_PAD_REG16X_RESERVED_Pos                                                                                  28U
+#define AON_REG_PAD_REG16X_RESERVED_Msk                                                                                  (0x3UL << AON_REG_PAD_REG16X_RESERVED_Pos)
+
+#define AON_REG_PAD_REG16X_PAD_P5_AON_MUX_2_Pos                                                                          30U
+#define AON_REG_PAD_REG16X_PAD_P5_AON_MUX_2_Msk                                                                          (0x3UL << AON_REG_PAD_REG16X_PAD_P5_AON_MUX_2_Pos)
+
+/* 0x164    0x4000_0164
+    0       R/W     PAD_P6_O_0                                                  1'b0
+    1       R/W     PAD_P6_E_0                                                  1'b0
+    2       R/W     PAD_P6_PU_EN_0                                              1'b1
+    3       R/W     AON_PAD_P6_PD_0                                             1'b1
+    4       R/W     PAD_P6_PUPDC_0                                              1'b0
+    5       R/W     PAD_P6_WKEN_0                                               1'b0
+    6       R/W     PAD_P6_WKPOL_0                                              1'b0
+    7       R/W     PAD_P6_SHDN_0                                               1'b1
+    8       R/W     PAD_P6_DEB_0                                                1'b0
+    9       R/W     PAD_P6_RAP_WKEN_0                                           1'b0
+    10      R/W     PAD_P6_PPU_WKEN_0                                           1'b0
+    11      R/W     RESERVED_3                                                  1'b0
+    12      R/W     PAD_P6_E2_AUX_0                                             1'b0
+    13      R       RESERVED_2                                                  1'b0
+    15:14   R/W     PAD_P6_AON_MUX_0                                            2'b00
+    16      R/W     PAD_P6_O_1                                                  1'b0
+    17      R/W     PAD_P6_E_1                                                  1'b0
+    18      R/W     PAD_P6_PU_EN_1                                              1'b1
+    19      R/W     AON_PAD_P6_PD_1                                             1'b1
+    20      R/W     PAD_P6_PUPDC_1                                              1'b0
+    21      R/W     PAD_P6_WKEN_1                                               1'b0
+    22      R/W     PAD_P6_WKPOL_1                                              1'b0
+    23      R/W     PAD_P6_SHDN_1                                               1'b1
+    24      R/W     PAD_P6_DEB_1                                                1'b0
+    25      R/W     PAD_P6_RAP_WKEN_1                                           1'b0
+    26      R/W     PAD_P6_PPU_WKEN_1                                           1'b0
+    27      R/W     RESERVED_1                                                  1'b0
+    29:28   R       RESERVED                                                    2'b00
+    31:30   R/W     PAD_P6_AON_MUX_1                                            2'b00
+ */
+typedef union _AON_REG_PAD_REG17X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t PAD_P6_O_0: 1;
+        uint32_t PAD_P6_E_0: 1;
+        uint32_t PAD_P6_PU_EN_0: 1;
+        uint32_t AON_PAD_P6_PD_0: 1;
+        uint32_t PAD_P6_PUPDC_0: 1;
+        uint32_t PAD_P6_WKEN_0: 1;
+        uint32_t PAD_P6_WKPOL_0: 1;
+        uint32_t PAD_P6_SHDN_0: 1;
+        uint32_t PAD_P6_DEB_0: 1;
+        uint32_t PAD_P6_RAP_WKEN_0: 1;
+        uint32_t PAD_P6_PPU_WKEN_0: 1;
+        uint32_t RESERVED_3: 1;
+        uint32_t PAD_P6_E2_AUX_0: 1;
+        uint32_t RESERVED_2: 1;
+        uint32_t PAD_P6_AON_MUX_0: 2;
+        uint32_t PAD_P6_O_1: 1;
+        uint32_t PAD_P6_E_1: 1;
+        uint32_t PAD_P6_PU_EN_1: 1;
+        uint32_t AON_PAD_P6_PD_1: 1;
+        uint32_t PAD_P6_PUPDC_1: 1;
+        uint32_t PAD_P6_WKEN_1: 1;
+        uint32_t PAD_P6_WKPOL_1: 1;
+        uint32_t PAD_P6_SHDN_1: 1;
+        uint32_t PAD_P6_DEB_1: 1;
+        uint32_t PAD_P6_RAP_WKEN_1: 1;
+        uint32_t PAD_P6_PPU_WKEN_1: 1;
+        uint32_t RESERVED_1: 1;
+        uint32_t RESERVED: 2;
+        uint32_t PAD_P6_AON_MUX_1: 2;
+    };
+} AON_REG_PAD_REG17X_TYPE;
+
+/*0x4000_0164 AON_REG_PAD_REG17X*/
+#define AON_REG_PAD_REG17X_PAD_P6_O_0_Pos                                                                                0U
+#define AON_REG_PAD_REG17X_PAD_P6_O_0_Msk                                                                                (0x1UL << AON_REG_PAD_REG17X_PAD_P6_O_0_Pos)
+
+#define AON_REG_PAD_REG17X_PAD_P6_E_0_Pos                                                                                1U
+#define AON_REG_PAD_REG17X_PAD_P6_E_0_Msk                                                                                (0x1UL << AON_REG_PAD_REG17X_PAD_P6_E_0_Pos)
+
+#define AON_REG_PAD_REG17X_PAD_P6_PU_EN_0_Pos                                                                            2U
+#define AON_REG_PAD_REG17X_PAD_P6_PU_EN_0_Msk                                                                            (0x1UL << AON_REG_PAD_REG17X_PAD_P6_PU_EN_0_Pos)
+
+#define AON_REG_PAD_REG17X_AON_PAD_P6_PD_0_Pos                                                                           3U
+#define AON_REG_PAD_REG17X_AON_PAD_P6_PD_0_Msk                                                                           (0x1UL << AON_REG_PAD_REG17X_AON_PAD_P6_PD_0_Pos)
+
+#define AON_REG_PAD_REG17X_PAD_P6_PUPDC_0_Pos                                                                            4U
+#define AON_REG_PAD_REG17X_PAD_P6_PUPDC_0_Msk                                                                            (0x1UL << AON_REG_PAD_REG17X_PAD_P6_PUPDC_0_Pos)
+
+#define AON_REG_PAD_REG17X_PAD_P6_WKEN_0_Pos                                                                             5U
+#define AON_REG_PAD_REG17X_PAD_P6_WKEN_0_Msk                                                                             (0x1UL << AON_REG_PAD_REG17X_PAD_P6_WKEN_0_Pos)
+
+#define AON_REG_PAD_REG17X_PAD_P6_WKPOL_0_Pos                                                                            6U
+#define AON_REG_PAD_REG17X_PAD_P6_WKPOL_0_Msk                                                                            (0x1UL << AON_REG_PAD_REG17X_PAD_P6_WKPOL_0_Pos)
+
+#define AON_REG_PAD_REG17X_PAD_P6_SHDN_0_Pos                                                                             7U
+#define AON_REG_PAD_REG17X_PAD_P6_SHDN_0_Msk                                                                             (0x1UL << AON_REG_PAD_REG17X_PAD_P6_SHDN_0_Pos)
+
+#define AON_REG_PAD_REG17X_PAD_P6_DEB_0_Pos                                                                              8U
+#define AON_REG_PAD_REG17X_PAD_P6_DEB_0_Msk                                                                              (0x1UL << AON_REG_PAD_REG17X_PAD_P6_DEB_0_Pos)
+
+#define AON_REG_PAD_REG17X_PAD_P6_RAP_WKEN_0_Pos                                                                         9U
+#define AON_REG_PAD_REG17X_PAD_P6_RAP_WKEN_0_Msk                                                                         (0x1UL << AON_REG_PAD_REG17X_PAD_P6_RAP_WKEN_0_Pos)
+
+#define AON_REG_PAD_REG17X_PAD_P6_PPU_WKEN_0_Pos                                                                         10U
+#define AON_REG_PAD_REG17X_PAD_P6_PPU_WKEN_0_Msk                                                                         (0x1UL << AON_REG_PAD_REG17X_PAD_P6_PPU_WKEN_0_Pos)
+
+#define AON_REG_PAD_REG17X_RESERVED_3_Pos                                                                                11U
+#define AON_REG_PAD_REG17X_RESERVED_3_Msk                                                                                (0x1UL << AON_REG_PAD_REG17X_RESERVED_3_Pos)
+
+#define AON_REG_PAD_REG17X_PAD_P6_E2_AUX_0_Pos                                                                           12U
+#define AON_REG_PAD_REG17X_PAD_P6_E2_AUX_0_Msk                                                                           (0x1UL << AON_REG_PAD_REG17X_PAD_P6_E2_AUX_0_Pos)
+
+#define AON_REG_PAD_REG17X_RESERVED_2_Pos                                                                                13U
+#define AON_REG_PAD_REG17X_RESERVED_2_Msk                                                                                (0x1UL << AON_REG_PAD_REG17X_RESERVED_2_Pos)
+
+#define AON_REG_PAD_REG17X_PAD_P6_AON_MUX_0_Pos                                                                          14U
+#define AON_REG_PAD_REG17X_PAD_P6_AON_MUX_0_Msk                                                                          (0x3UL << AON_REG_PAD_REG17X_PAD_P6_AON_MUX_0_Pos)
+
+#define AON_REG_PAD_REG17X_PAD_P6_O_1_Pos                                                                                16U
+#define AON_REG_PAD_REG17X_PAD_P6_O_1_Msk                                                                                (0x1UL << AON_REG_PAD_REG17X_PAD_P6_O_1_Pos)
+
+#define AON_REG_PAD_REG17X_PAD_P6_E_1_Pos                                                                                17U
+#define AON_REG_PAD_REG17X_PAD_P6_E_1_Msk                                                                                (0x1UL << AON_REG_PAD_REG17X_PAD_P6_E_1_Pos)
+
+#define AON_REG_PAD_REG17X_PAD_P6_PU_EN_1_Pos                                                                            18U
+#define AON_REG_PAD_REG17X_PAD_P6_PU_EN_1_Msk                                                                            (0x1UL << AON_REG_PAD_REG17X_PAD_P6_PU_EN_1_Pos)
+
+#define AON_REG_PAD_REG17X_AON_PAD_P6_PD_1_Pos                                                                           19U
+#define AON_REG_PAD_REG17X_AON_PAD_P6_PD_1_Msk                                                                           (0x1UL << AON_REG_PAD_REG17X_AON_PAD_P6_PD_1_Pos)
+
+#define AON_REG_PAD_REG17X_PAD_P6_PUPDC_1_Pos                                                                            20U
+#define AON_REG_PAD_REG17X_PAD_P6_PUPDC_1_Msk                                                                            (0x1UL << AON_REG_PAD_REG17X_PAD_P6_PUPDC_1_Pos)
+
+#define AON_REG_PAD_REG17X_PAD_P6_WKEN_1_Pos                                                                             21U
+#define AON_REG_PAD_REG17X_PAD_P6_WKEN_1_Msk                                                                             (0x1UL << AON_REG_PAD_REG17X_PAD_P6_WKEN_1_Pos)
+
+#define AON_REG_PAD_REG17X_PAD_P6_WKPOL_1_Pos                                                                            22U
+#define AON_REG_PAD_REG17X_PAD_P6_WKPOL_1_Msk                                                                            (0x1UL << AON_REG_PAD_REG17X_PAD_P6_WKPOL_1_Pos)
+
+#define AON_REG_PAD_REG17X_PAD_P6_SHDN_1_Pos                                                                             23U
+#define AON_REG_PAD_REG17X_PAD_P6_SHDN_1_Msk                                                                             (0x1UL << AON_REG_PAD_REG17X_PAD_P6_SHDN_1_Pos)
+
+#define AON_REG_PAD_REG17X_PAD_P6_DEB_1_Pos                                                                              24U
+#define AON_REG_PAD_REG17X_PAD_P6_DEB_1_Msk                                                                              (0x1UL << AON_REG_PAD_REG17X_PAD_P6_DEB_1_Pos)
+
+#define AON_REG_PAD_REG17X_PAD_P6_RAP_WKEN_1_Pos                                                                         25U
+#define AON_REG_PAD_REG17X_PAD_P6_RAP_WKEN_1_Msk                                                                         (0x1UL << AON_REG_PAD_REG17X_PAD_P6_RAP_WKEN_1_Pos)
+
+#define AON_REG_PAD_REG17X_PAD_P6_PPU_WKEN_1_Pos                                                                         26U
+#define AON_REG_PAD_REG17X_PAD_P6_PPU_WKEN_1_Msk                                                                         (0x1UL << AON_REG_PAD_REG17X_PAD_P6_PPU_WKEN_1_Pos)
+
+#define AON_REG_PAD_REG17X_RESERVED_1_Pos                                                                                27U
+#define AON_REG_PAD_REG17X_RESERVED_1_Msk                                                                                (0x1UL << AON_REG_PAD_REG17X_RESERVED_1_Pos)
+
+#define AON_REG_PAD_REG17X_RESERVED_Pos                                                                                  28U
+#define AON_REG_PAD_REG17X_RESERVED_Msk                                                                                  (0x3UL << AON_REG_PAD_REG17X_RESERVED_Pos)
+
+#define AON_REG_PAD_REG17X_PAD_P6_AON_MUX_1_Pos                                                                          30U
+#define AON_REG_PAD_REG17X_PAD_P6_AON_MUX_1_Msk                                                                          (0x3UL << AON_REG_PAD_REG17X_PAD_P6_AON_MUX_1_Pos)
+
+/* 0x168    0x4000_0168
+    0       R/W     PAD_P6_O_2                                                  1'b0
+    1       R/W     PAD_P6_E_2                                                  1'b0
+    2       R/W     PAD_P6_PU_EN_2                                              1'b1
+    3       R/W     AON_PAD_P6_PD_2                                             1'b1
+    4       R/W     PAD_P6_PUPDC_2                                              1'b0
+    5       R/W     PAD_P6_WKEN_2                                               1'b0
+    6       R/W     PAD_P6_WKPOL_2                                              1'b0
+    7       R/W     PAD_P6_SHDN_2                                               1'b1
+    8       R/W     PAD_P6_DEB_2                                                1'b0
+    9       R/W     PAD_P6_RAP_WKEN_2                                           1'b0
+    10      R/W     PAD_P6_PPU_WKEN_2                                           1'b0
+    11      R/W     RESERVED_3                                                  1'b0
+    13:12   R       RESERVED_2                                                  2'b00
+    15:14   R/W     PAD_P6_AON_MUX_2                                            2'b00
+    16      R/W     PAD_P6_O_3                                                  1'b0
+    17      R/W     PAD_P6_E_3                                                  1'b0
+    18      R/W     PAD_P6_PU_EN_3                                              1'b1
+    19      R/W     AON_PAD_P6_PD_3                                             1'b1
+    20      R/W     PAD_P6_PUPDC_3                                              1'b0
+    21      R/W     PAD_P6_WKEN_3                                               1'b0
+    22      R/W     PAD_P6_WKPOL_3                                              1'b0
+    23      R/W     PAD_P6_SHDN_3                                               1'b1
+    24      R/W     PAD_P6_DEB_3                                                1'b0
+    25      R/W     PAD_P6_RAP_WKEN_3                                           1'b0
+    26      R/W     PAD_P6_PPU_WKEN_3                                           1'b0
+    27      R/W     RESERVED_1                                                  1'b0
+    29:28   R       RESERVED                                                    2'b00
+    31:30   R/W     PAD_P6_AON_MUX_3                                            2'b00
+ */
+typedef union _AON_REG_PAD_REG18X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t PAD_P6_O_2: 1;
+        uint32_t PAD_P6_E_2: 1;
+        uint32_t PAD_P6_PU_EN_2: 1;
+        uint32_t AON_PAD_P6_PD_2: 1;
+        uint32_t PAD_P6_PUPDC_2: 1;
+        uint32_t PAD_P6_WKEN_2: 1;
+        uint32_t PAD_P6_WKPOL_2: 1;
+        uint32_t PAD_P6_SHDN_2: 1;
+        uint32_t PAD_P6_DEB_2: 1;
+        uint32_t PAD_P6_RAP_WKEN_2: 1;
+        uint32_t PAD_P6_PPU_WKEN_2: 1;
+        uint32_t RESERVED_3: 1;
+        uint32_t RESERVED_2: 2;
+        uint32_t PAD_P6_AON_MUX_2: 2;
+        uint32_t PAD_P6_O_3: 1;
+        uint32_t PAD_P6_E_3: 1;
+        uint32_t PAD_P6_PU_EN_3: 1;
+        uint32_t AON_PAD_P6_PD_3: 1;
+        uint32_t PAD_P6_PUPDC_3: 1;
+        uint32_t PAD_P6_WKEN_3: 1;
+        uint32_t PAD_P6_WKPOL_3: 1;
+        uint32_t PAD_P6_SHDN_3: 1;
+        uint32_t PAD_P6_DEB_3: 1;
+        uint32_t PAD_P6_RAP_WKEN_3: 1;
+        uint32_t PAD_P6_PPU_WKEN_3: 1;
+        uint32_t RESERVED_1: 1;
+        uint32_t RESERVED: 2;
+        uint32_t PAD_P6_AON_MUX_3: 2;
+    };
+} AON_REG_PAD_REG18X_TYPE;
+
+/*0x4000_0168 AON_REG_PAD_REG18X*/
+#define AON_REG_PAD_REG18X_PAD_P6_O_2_Pos                                                                                0U
+#define AON_REG_PAD_REG18X_PAD_P6_O_2_Msk                                                                                (0x1UL << AON_REG_PAD_REG18X_PAD_P6_O_2_Pos)
+
+#define AON_REG_PAD_REG18X_PAD_P6_E_2_Pos                                                                                1U
+#define AON_REG_PAD_REG18X_PAD_P6_E_2_Msk                                                                                (0x1UL << AON_REG_PAD_REG18X_PAD_P6_E_2_Pos)
+
+#define AON_REG_PAD_REG18X_PAD_P6_PU_EN_2_Pos                                                                            2U
+#define AON_REG_PAD_REG18X_PAD_P6_PU_EN_2_Msk                                                                            (0x1UL << AON_REG_PAD_REG18X_PAD_P6_PU_EN_2_Pos)
+
+#define AON_REG_PAD_REG18X_AON_PAD_P6_PD_2_Pos                                                                           3U
+#define AON_REG_PAD_REG18X_AON_PAD_P6_PD_2_Msk                                                                           (0x1UL << AON_REG_PAD_REG18X_AON_PAD_P6_PD_2_Pos)
+
+#define AON_REG_PAD_REG18X_PAD_P6_PUPDC_2_Pos                                                                            4U
+#define AON_REG_PAD_REG18X_PAD_P6_PUPDC_2_Msk                                                                            (0x1UL << AON_REG_PAD_REG18X_PAD_P6_PUPDC_2_Pos)
+
+#define AON_REG_PAD_REG18X_PAD_P6_WKEN_2_Pos                                                                             5U
+#define AON_REG_PAD_REG18X_PAD_P6_WKEN_2_Msk                                                                             (0x1UL << AON_REG_PAD_REG18X_PAD_P6_WKEN_2_Pos)
+
+#define AON_REG_PAD_REG18X_PAD_P6_WKPOL_2_Pos                                                                            6U
+#define AON_REG_PAD_REG18X_PAD_P6_WKPOL_2_Msk                                                                            (0x1UL << AON_REG_PAD_REG18X_PAD_P6_WKPOL_2_Pos)
+
+#define AON_REG_PAD_REG18X_PAD_P6_SHDN_2_Pos                                                                             7U
+#define AON_REG_PAD_REG18X_PAD_P6_SHDN_2_Msk                                                                             (0x1UL << AON_REG_PAD_REG18X_PAD_P6_SHDN_2_Pos)
+
+#define AON_REG_PAD_REG18X_PAD_P6_DEB_2_Pos                                                                              8U
+#define AON_REG_PAD_REG18X_PAD_P6_DEB_2_Msk                                                                              (0x1UL << AON_REG_PAD_REG18X_PAD_P6_DEB_2_Pos)
+
+#define AON_REG_PAD_REG18X_PAD_P6_RAP_WKEN_2_Pos                                                                         9U
+#define AON_REG_PAD_REG18X_PAD_P6_RAP_WKEN_2_Msk                                                                         (0x1UL << AON_REG_PAD_REG18X_PAD_P6_RAP_WKEN_2_Pos)
+
+#define AON_REG_PAD_REG18X_PAD_P6_PPU_WKEN_2_Pos                                                                         10U
+#define AON_REG_PAD_REG18X_PAD_P6_PPU_WKEN_2_Msk                                                                         (0x1UL << AON_REG_PAD_REG18X_PAD_P6_PPU_WKEN_2_Pos)
+
+#define AON_REG_PAD_REG18X_RESERVED_3_Pos                                                                                11U
+#define AON_REG_PAD_REG18X_RESERVED_3_Msk                                                                                (0x1UL << AON_REG_PAD_REG18X_RESERVED_3_Pos)
+
+#define AON_REG_PAD_REG18X_RESERVED_2_Pos                                                                                12U
+#define AON_REG_PAD_REG18X_RESERVED_2_Msk                                                                                (0x3UL << AON_REG_PAD_REG18X_RESERVED_2_Pos)
+
+#define AON_REG_PAD_REG18X_PAD_P6_AON_MUX_2_Pos                                                                          14U
+#define AON_REG_PAD_REG18X_PAD_P6_AON_MUX_2_Msk                                                                          (0x3UL << AON_REG_PAD_REG18X_PAD_P6_AON_MUX_2_Pos)
+
+#define AON_REG_PAD_REG18X_PAD_P6_O_3_Pos                                                                                16U
+#define AON_REG_PAD_REG18X_PAD_P6_O_3_Msk                                                                                (0x1UL << AON_REG_PAD_REG18X_PAD_P6_O_3_Pos)
+
+#define AON_REG_PAD_REG18X_PAD_P6_E_3_Pos                                                                                17U
+#define AON_REG_PAD_REG18X_PAD_P6_E_3_Msk                                                                                (0x1UL << AON_REG_PAD_REG18X_PAD_P6_E_3_Pos)
+
+#define AON_REG_PAD_REG18X_PAD_P6_PU_EN_3_Pos                                                                            18U
+#define AON_REG_PAD_REG18X_PAD_P6_PU_EN_3_Msk                                                                            (0x1UL << AON_REG_PAD_REG18X_PAD_P6_PU_EN_3_Pos)
+
+#define AON_REG_PAD_REG18X_AON_PAD_P6_PD_3_Pos                                                                           19U
+#define AON_REG_PAD_REG18X_AON_PAD_P6_PD_3_Msk                                                                           (0x1UL << AON_REG_PAD_REG18X_AON_PAD_P6_PD_3_Pos)
+
+#define AON_REG_PAD_REG18X_PAD_P6_PUPDC_3_Pos                                                                            20U
+#define AON_REG_PAD_REG18X_PAD_P6_PUPDC_3_Msk                                                                            (0x1UL << AON_REG_PAD_REG18X_PAD_P6_PUPDC_3_Pos)
+
+#define AON_REG_PAD_REG18X_PAD_P6_WKEN_3_Pos                                                                             21U
+#define AON_REG_PAD_REG18X_PAD_P6_WKEN_3_Msk                                                                             (0x1UL << AON_REG_PAD_REG18X_PAD_P6_WKEN_3_Pos)
+
+#define AON_REG_PAD_REG18X_PAD_P6_WKPOL_3_Pos                                                                            22U
+#define AON_REG_PAD_REG18X_PAD_P6_WKPOL_3_Msk                                                                            (0x1UL << AON_REG_PAD_REG18X_PAD_P6_WKPOL_3_Pos)
+
+#define AON_REG_PAD_REG18X_PAD_P6_SHDN_3_Pos                                                                             23U
+#define AON_REG_PAD_REG18X_PAD_P6_SHDN_3_Msk                                                                             (0x1UL << AON_REG_PAD_REG18X_PAD_P6_SHDN_3_Pos)
+
+#define AON_REG_PAD_REG18X_PAD_P6_DEB_3_Pos                                                                              24U
+#define AON_REG_PAD_REG18X_PAD_P6_DEB_3_Msk                                                                              (0x1UL << AON_REG_PAD_REG18X_PAD_P6_DEB_3_Pos)
+
+#define AON_REG_PAD_REG18X_PAD_P6_RAP_WKEN_3_Pos                                                                         25U
+#define AON_REG_PAD_REG18X_PAD_P6_RAP_WKEN_3_Msk                                                                         (0x1UL << AON_REG_PAD_REG18X_PAD_P6_RAP_WKEN_3_Pos)
+
+#define AON_REG_PAD_REG18X_PAD_P6_PPU_WKEN_3_Pos                                                                         26U
+#define AON_REG_PAD_REG18X_PAD_P6_PPU_WKEN_3_Msk                                                                         (0x1UL << AON_REG_PAD_REG18X_PAD_P6_PPU_WKEN_3_Pos)
+
+#define AON_REG_PAD_REG18X_RESERVED_1_Pos                                                                                27U
+#define AON_REG_PAD_REG18X_RESERVED_1_Msk                                                                                (0x1UL << AON_REG_PAD_REG18X_RESERVED_1_Pos)
+
+#define AON_REG_PAD_REG18X_RESERVED_Pos                                                                                  28U
+#define AON_REG_PAD_REG18X_RESERVED_Msk                                                                                  (0x3UL << AON_REG_PAD_REG18X_RESERVED_Pos)
+
+#define AON_REG_PAD_REG18X_PAD_P6_AON_MUX_3_Pos                                                                          30U
+#define AON_REG_PAD_REG18X_PAD_P6_AON_MUX_3_Msk                                                                          (0x3UL << AON_REG_PAD_REG18X_PAD_P6_AON_MUX_3_Pos)
+
+/* 0x16C    0x4000_016c
+    0       R/W     PAD_P6_O_4                                                  1'b0
+    1       R/W     PAD_P6_E_4                                                  1'b0
+    2       R/W     PAD_P6_PU_EN_4                                              1'b1
+    3       R/W     AON_PAD_P6_PD_4                                             1'b1
+    4       R/W     PAD_P6_PUPDC_4                                              1'b0
+    5       R/W     PAD_P6_WKEN_4                                               1'b0
+    6       R/W     PAD_P6_WKPOL_4                                              1'b0
+    7       R/W     PAD_P6_SHDN_4                                               1'b1
+    8       R/W     PAD_P6_DEB_4                                                1'b0
+    9       R/W     PAD_P6_RAP_WKEN_4                                           1'b0
+    10      R/W     PAD_P6_PPU_WKEN_4                                           1'b0
+    11      R/W     RESERVED_3                                                  1'b0
+    13:12   R       RESERVED_2                                                  2'b00
+    15:14   R/W     PAD_P6_AON_MUX_4                                            2'b00
+    16      R/W     PAD_P6_O_5                                                  1'b0
+    17      R/W     PAD_P6_E_5                                                  1'b0
+    18      R/W     PAD_P6_PU_EN_5                                              1'b1
+    19      R/W     AON_PAD_P6_PD_5                                             1'b1
+    20      R/W     PAD_P6_PUPDC_5                                              1'b0
+    21      R/W     PAD_P6_WKEN_5                                               1'b0
+    22      R/W     PAD_P6_WKPOL_5                                              1'b0
+    23      R/W     PAD_P6_SHDN_5                                               1'b1
+    24      R/W     PAD_P6_DEB_5                                                1'b0
+    25      R/W     PAD_P6_RAP_WKEN_5                                           1'b0
+    26      R/W     PAD_P6_PPU_WKEN_5                                           1'b0
+    27      R/W     RESERVED_1                                                  1'b0
+    29:28   R       RESERVED                                                    2'b00
+    31:30   R/W     PAD_P6_AON_MUX_5                                            2'b00
+ */
+typedef union _AON_REG_PAD_REG19X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t PAD_P6_O_4: 1;
+        uint32_t PAD_P6_E_4: 1;
+        uint32_t PAD_P6_PU_EN_4: 1;
+        uint32_t AON_PAD_P6_PD_4: 1;
+        uint32_t PAD_P6_PUPDC_4: 1;
+        uint32_t PAD_P6_WKEN_4: 1;
+        uint32_t PAD_P6_WKPOL_4: 1;
+        uint32_t PAD_P6_SHDN_4: 1;
+        uint32_t PAD_P6_DEB_4: 1;
+        uint32_t PAD_P6_RAP_WKEN_4: 1;
+        uint32_t PAD_P6_PPU_WKEN_4: 1;
+        uint32_t RESERVED_3: 1;
+        uint32_t RESERVED_2: 2;
+        uint32_t PAD_P6_AON_MUX_4: 2;
+        uint32_t PAD_P6_O_5: 1;
+        uint32_t PAD_P6_E_5: 1;
+        uint32_t PAD_P6_PU_EN_5: 1;
+        uint32_t AON_PAD_P6_PD_5: 1;
+        uint32_t PAD_P6_PUPDC_5: 1;
+        uint32_t PAD_P6_WKEN_5: 1;
+        uint32_t PAD_P6_WKPOL_5: 1;
+        uint32_t PAD_P6_SHDN_5: 1;
+        uint32_t PAD_P6_DEB_5: 1;
+        uint32_t PAD_P6_RAP_WKEN_5: 1;
+        uint32_t PAD_P6_PPU_WKEN_5: 1;
+        uint32_t RESERVED_1: 1;
+        uint32_t RESERVED: 2;
+        uint32_t PAD_P6_AON_MUX_5: 2;
+    };
+} AON_REG_PAD_REG19X_TYPE;
+
+/*0x4000_016c AON_REG_PAD_REG19X*/
+#define AON_REG_PAD_REG19X_PAD_P6_O_4_Pos                                                                                0U
+#define AON_REG_PAD_REG19X_PAD_P6_O_4_Msk                                                                                (0x1UL << AON_REG_PAD_REG19X_PAD_P6_O_4_Pos)
+
+#define AON_REG_PAD_REG19X_PAD_P6_E_4_Pos                                                                                1U
+#define AON_REG_PAD_REG19X_PAD_P6_E_4_Msk                                                                                (0x1UL << AON_REG_PAD_REG19X_PAD_P6_E_4_Pos)
+
+#define AON_REG_PAD_REG19X_PAD_P6_PU_EN_4_Pos                                                                            2U
+#define AON_REG_PAD_REG19X_PAD_P6_PU_EN_4_Msk                                                                            (0x1UL << AON_REG_PAD_REG19X_PAD_P6_PU_EN_4_Pos)
+
+#define AON_REG_PAD_REG19X_AON_PAD_P6_PD_4_Pos                                                                           3U
+#define AON_REG_PAD_REG19X_AON_PAD_P6_PD_4_Msk                                                                           (0x1UL << AON_REG_PAD_REG19X_AON_PAD_P6_PD_4_Pos)
+
+#define AON_REG_PAD_REG19X_PAD_P6_PUPDC_4_Pos                                                                            4U
+#define AON_REG_PAD_REG19X_PAD_P6_PUPDC_4_Msk                                                                            (0x1UL << AON_REG_PAD_REG19X_PAD_P6_PUPDC_4_Pos)
+
+#define AON_REG_PAD_REG19X_PAD_P6_WKEN_4_Pos                                                                             5U
+#define AON_REG_PAD_REG19X_PAD_P6_WKEN_4_Msk                                                                             (0x1UL << AON_REG_PAD_REG19X_PAD_P6_WKEN_4_Pos)
+
+#define AON_REG_PAD_REG19X_PAD_P6_WKPOL_4_Pos                                                                            6U
+#define AON_REG_PAD_REG19X_PAD_P6_WKPOL_4_Msk                                                                            (0x1UL << AON_REG_PAD_REG19X_PAD_P6_WKPOL_4_Pos)
+
+#define AON_REG_PAD_REG19X_PAD_P6_SHDN_4_Pos                                                                             7U
+#define AON_REG_PAD_REG19X_PAD_P6_SHDN_4_Msk                                                                             (0x1UL << AON_REG_PAD_REG19X_PAD_P6_SHDN_4_Pos)
+
+#define AON_REG_PAD_REG19X_PAD_P6_DEB_4_Pos                                                                              8U
+#define AON_REG_PAD_REG19X_PAD_P6_DEB_4_Msk                                                                              (0x1UL << AON_REG_PAD_REG19X_PAD_P6_DEB_4_Pos)
+
+#define AON_REG_PAD_REG19X_PAD_P6_RAP_WKEN_4_Pos                                                                         9U
+#define AON_REG_PAD_REG19X_PAD_P6_RAP_WKEN_4_Msk                                                                         (0x1UL << AON_REG_PAD_REG19X_PAD_P6_RAP_WKEN_4_Pos)
+
+#define AON_REG_PAD_REG19X_PAD_P6_PPU_WKEN_4_Pos                                                                         10U
+#define AON_REG_PAD_REG19X_PAD_P6_PPU_WKEN_4_Msk                                                                         (0x1UL << AON_REG_PAD_REG19X_PAD_P6_PPU_WKEN_4_Pos)
+
+#define AON_REG_PAD_REG19X_RESERVED_3_Pos                                                                                11U
+#define AON_REG_PAD_REG19X_RESERVED_3_Msk                                                                                (0x1UL << AON_REG_PAD_REG19X_RESERVED_3_Pos)
+
+#define AON_REG_PAD_REG19X_RESERVED_2_Pos                                                                                12U
+#define AON_REG_PAD_REG19X_RESERVED_2_Msk                                                                                (0x3UL << AON_REG_PAD_REG19X_RESERVED_2_Pos)
+
+#define AON_REG_PAD_REG19X_PAD_P6_AON_MUX_4_Pos                                                                          14U
+#define AON_REG_PAD_REG19X_PAD_P6_AON_MUX_4_Msk                                                                          (0x3UL << AON_REG_PAD_REG19X_PAD_P6_AON_MUX_4_Pos)
+
+#define AON_REG_PAD_REG19X_PAD_P6_O_5_Pos                                                                                16U
+#define AON_REG_PAD_REG19X_PAD_P6_O_5_Msk                                                                                (0x1UL << AON_REG_PAD_REG19X_PAD_P6_O_5_Pos)
+
+#define AON_REG_PAD_REG19X_PAD_P6_E_5_Pos                                                                                17U
+#define AON_REG_PAD_REG19X_PAD_P6_E_5_Msk                                                                                (0x1UL << AON_REG_PAD_REG19X_PAD_P6_E_5_Pos)
+
+#define AON_REG_PAD_REG19X_PAD_P6_PU_EN_5_Pos                                                                            18U
+#define AON_REG_PAD_REG19X_PAD_P6_PU_EN_5_Msk                                                                            (0x1UL << AON_REG_PAD_REG19X_PAD_P6_PU_EN_5_Pos)
+
+#define AON_REG_PAD_REG19X_AON_PAD_P6_PD_5_Pos                                                                           19U
+#define AON_REG_PAD_REG19X_AON_PAD_P6_PD_5_Msk                                                                           (0x1UL << AON_REG_PAD_REG19X_AON_PAD_P6_PD_5_Pos)
+
+#define AON_REG_PAD_REG19X_PAD_P6_PUPDC_5_Pos                                                                            20U
+#define AON_REG_PAD_REG19X_PAD_P6_PUPDC_5_Msk                                                                            (0x1UL << AON_REG_PAD_REG19X_PAD_P6_PUPDC_5_Pos)
+
+#define AON_REG_PAD_REG19X_PAD_P6_WKEN_5_Pos                                                                             21U
+#define AON_REG_PAD_REG19X_PAD_P6_WKEN_5_Msk                                                                             (0x1UL << AON_REG_PAD_REG19X_PAD_P6_WKEN_5_Pos)
+
+#define AON_REG_PAD_REG19X_PAD_P6_WKPOL_5_Pos                                                                            22U
+#define AON_REG_PAD_REG19X_PAD_P6_WKPOL_5_Msk                                                                            (0x1UL << AON_REG_PAD_REG19X_PAD_P6_WKPOL_5_Pos)
+
+#define AON_REG_PAD_REG19X_PAD_P6_SHDN_5_Pos                                                                             23U
+#define AON_REG_PAD_REG19X_PAD_P6_SHDN_5_Msk                                                                             (0x1UL << AON_REG_PAD_REG19X_PAD_P6_SHDN_5_Pos)
+
+#define AON_REG_PAD_REG19X_PAD_P6_DEB_5_Pos                                                                              24U
+#define AON_REG_PAD_REG19X_PAD_P6_DEB_5_Msk                                                                              (0x1UL << AON_REG_PAD_REG19X_PAD_P6_DEB_5_Pos)
+
+#define AON_REG_PAD_REG19X_PAD_P6_RAP_WKEN_5_Pos                                                                         25U
+#define AON_REG_PAD_REG19X_PAD_P6_RAP_WKEN_5_Msk                                                                         (0x1UL << AON_REG_PAD_REG19X_PAD_P6_RAP_WKEN_5_Pos)
+
+#define AON_REG_PAD_REG19X_PAD_P6_PPU_WKEN_5_Pos                                                                         26U
+#define AON_REG_PAD_REG19X_PAD_P6_PPU_WKEN_5_Msk                                                                         (0x1UL << AON_REG_PAD_REG19X_PAD_P6_PPU_WKEN_5_Pos)
+
+#define AON_REG_PAD_REG19X_RESERVED_1_Pos                                                                                27U
+#define AON_REG_PAD_REG19X_RESERVED_1_Msk                                                                                (0x1UL << AON_REG_PAD_REG19X_RESERVED_1_Pos)
+
+#define AON_REG_PAD_REG19X_RESERVED_Pos                                                                                  28U
+#define AON_REG_PAD_REG19X_RESERVED_Msk                                                                                  (0x3UL << AON_REG_PAD_REG19X_RESERVED_Pos)
+
+#define AON_REG_PAD_REG19X_PAD_P6_AON_MUX_5_Pos                                                                          30U
+#define AON_REG_PAD_REG19X_PAD_P6_AON_MUX_5_Msk                                                                          (0x3UL << AON_REG_PAD_REG19X_PAD_P6_AON_MUX_5_Pos)
+
+/* 0x170    0x4000_0170
+    0       R/W     PAD_P6_O_6                                                  1'b0
+    1       R/W     PAD_P6_E_6                                                  1'b0
+    2       R/W     PAD_P6_PU_EN_6                                              1'b1
+    3       R/W     AON_PAD_P6_PD_6                                             1'b1
+    4       R/W     PAD_P6_PUPDC_6                                              1'b0
+    5       R/W     PAD_P6_WKEN_6                                               1'b0
+    6       R/W     PAD_P6_WKPOL_6                                              1'b0
+    7       R/W     PAD_P6_SHDN_6                                               1'b1
+    8       R/W     PAD_P6_DEB_6                                                1'b0
+    9       R/W     PAD_P6_RAP_WKEN_6                                           1'b0
+    10      R/W     PAD_P6_PPU_WKEN_6                                           1'b0
+    11      R/W     RESERVED_3                                                  1'b0
+    13:12   R       RESERVED_2                                                  2'b00
+    15:14   R/W     PAD_P6_AON_MUX_6                                            2'b00
+    16      R/W     PAD_P6_O_7                                                  1'b0
+    17      R/W     PAD_P6_E_7                                                  1'b0
+    18      R/W     PAD_P6_PU_EN_7                                              1'b1
+    19      R/W     AON_PAD_P6_PD_7                                             1'b1
+    20      R/W     PAD_P6_PUPDC_7                                              1'b0
+    21      R/W     PAD_P6_WKEN_7                                               1'b0
+    22      R/W     PAD_P6_WKPOL_7                                              1'b0
+    23      R/W     PAD_P6_SHDN_7                                               1'b1
+    24      R/W     PAD_P6_DEB_7                                                1'b0
+    25      R/W     PAD_P6_RAP_WKEN_7                                           1'b0
+    26      R/W     PAD_P6_PPU_WKEN_7                                           1'b0
+    27      R/W     RESERVED_1                                                  1'b0
+    29:28   R       RESERVED                                                    2'b00
+    31:30   R/W     PAD_P6_AON_MUX_7                                            2'b00
+ */
+typedef union _AON_REG_PAD_REG20X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t PAD_P6_O_6: 1;
+        uint32_t PAD_P6_E_6: 1;
+        uint32_t PAD_P6_PU_EN_6: 1;
+        uint32_t AON_PAD_P6_PD_6: 1;
+        uint32_t PAD_P6_PUPDC_6: 1;
+        uint32_t PAD_P6_WKEN_6: 1;
+        uint32_t PAD_P6_WKPOL_6: 1;
+        uint32_t PAD_P6_SHDN_6: 1;
+        uint32_t PAD_P6_DEB_6: 1;
+        uint32_t PAD_P6_RAP_WKEN_6: 1;
+        uint32_t PAD_P6_PPU_WKEN_6: 1;
+        uint32_t RESERVED_3: 1;
+        uint32_t RESERVED_2: 2;
+        uint32_t PAD_P6_AON_MUX_6: 2;
+        uint32_t PAD_P6_O_7: 1;
+        uint32_t PAD_P6_E_7: 1;
+        uint32_t PAD_P6_PU_EN_7: 1;
+        uint32_t AON_PAD_P6_PD_7: 1;
+        uint32_t PAD_P6_PUPDC_7: 1;
+        uint32_t PAD_P6_WKEN_7: 1;
+        uint32_t PAD_P6_WKPOL_7: 1;
+        uint32_t PAD_P6_SHDN_7: 1;
+        uint32_t PAD_P6_DEB_7: 1;
+        uint32_t PAD_P6_RAP_WKEN_7: 1;
+        uint32_t PAD_P6_PPU_WKEN_7: 1;
+        uint32_t RESERVED_1: 1;
+        uint32_t RESERVED: 2;
+        uint32_t PAD_P6_AON_MUX_7: 2;
+    };
+} AON_REG_PAD_REG20X_TYPE;
+
+/*0x4000_0170 AON_REG_PAD_REG20X*/
+#define AON_REG_PAD_REG20X_PAD_P6_O_6_Pos                                                                                0U
+#define AON_REG_PAD_REG20X_PAD_P6_O_6_Msk                                                                                (0x1UL << AON_REG_PAD_REG20X_PAD_P6_O_6_Pos)
+
+#define AON_REG_PAD_REG20X_PAD_P6_E_6_Pos                                                                                1U
+#define AON_REG_PAD_REG20X_PAD_P6_E_6_Msk                                                                                (0x1UL << AON_REG_PAD_REG20X_PAD_P6_E_6_Pos)
+
+#define AON_REG_PAD_REG20X_PAD_P6_PU_EN_6_Pos                                                                            2U
+#define AON_REG_PAD_REG20X_PAD_P6_PU_EN_6_Msk                                                                            (0x1UL << AON_REG_PAD_REG20X_PAD_P6_PU_EN_6_Pos)
+
+#define AON_REG_PAD_REG20X_AON_PAD_P6_PD_6_Pos                                                                           3U
+#define AON_REG_PAD_REG20X_AON_PAD_P6_PD_6_Msk                                                                           (0x1UL << AON_REG_PAD_REG20X_AON_PAD_P6_PD_6_Pos)
+
+#define AON_REG_PAD_REG20X_PAD_P6_PUPDC_6_Pos                                                                            4U
+#define AON_REG_PAD_REG20X_PAD_P6_PUPDC_6_Msk                                                                            (0x1UL << AON_REG_PAD_REG20X_PAD_P6_PUPDC_6_Pos)
+
+#define AON_REG_PAD_REG20X_PAD_P6_WKEN_6_Pos                                                                             5U
+#define AON_REG_PAD_REG20X_PAD_P6_WKEN_6_Msk                                                                             (0x1UL << AON_REG_PAD_REG20X_PAD_P6_WKEN_6_Pos)
+
+#define AON_REG_PAD_REG20X_PAD_P6_WKPOL_6_Pos                                                                            6U
+#define AON_REG_PAD_REG20X_PAD_P6_WKPOL_6_Msk                                                                            (0x1UL << AON_REG_PAD_REG20X_PAD_P6_WKPOL_6_Pos)
+
+#define AON_REG_PAD_REG20X_PAD_P6_SHDN_6_Pos                                                                             7U
+#define AON_REG_PAD_REG20X_PAD_P6_SHDN_6_Msk                                                                             (0x1UL << AON_REG_PAD_REG20X_PAD_P6_SHDN_6_Pos)
+
+#define AON_REG_PAD_REG20X_PAD_P6_DEB_6_Pos                                                                              8U
+#define AON_REG_PAD_REG20X_PAD_P6_DEB_6_Msk                                                                              (0x1UL << AON_REG_PAD_REG20X_PAD_P6_DEB_6_Pos)
+
+#define AON_REG_PAD_REG20X_PAD_P6_RAP_WKEN_6_Pos                                                                         9U
+#define AON_REG_PAD_REG20X_PAD_P6_RAP_WKEN_6_Msk                                                                         (0x1UL << AON_REG_PAD_REG20X_PAD_P6_RAP_WKEN_6_Pos)
+
+#define AON_REG_PAD_REG20X_PAD_P6_PPU_WKEN_6_Pos                                                                         10U
+#define AON_REG_PAD_REG20X_PAD_P6_PPU_WKEN_6_Msk                                                                         (0x1UL << AON_REG_PAD_REG20X_PAD_P6_PPU_WKEN_6_Pos)
+
+#define AON_REG_PAD_REG20X_RESERVED_3_Pos                                                                                11U
+#define AON_REG_PAD_REG20X_RESERVED_3_Msk                                                                                (0x1UL << AON_REG_PAD_REG20X_RESERVED_3_Pos)
+
+#define AON_REG_PAD_REG20X_RESERVED_2_Pos                                                                                12U
+#define AON_REG_PAD_REG20X_RESERVED_2_Msk                                                                                (0x3UL << AON_REG_PAD_REG20X_RESERVED_2_Pos)
+
+#define AON_REG_PAD_REG20X_PAD_P6_AON_MUX_6_Pos                                                                          14U
+#define AON_REG_PAD_REG20X_PAD_P6_AON_MUX_6_Msk                                                                          (0x3UL << AON_REG_PAD_REG20X_PAD_P6_AON_MUX_6_Pos)
+
+#define AON_REG_PAD_REG20X_PAD_P6_O_7_Pos                                                                                16U
+#define AON_REG_PAD_REG20X_PAD_P6_O_7_Msk                                                                                (0x1UL << AON_REG_PAD_REG20X_PAD_P6_O_7_Pos)
+
+#define AON_REG_PAD_REG20X_PAD_P6_E_7_Pos                                                                                17U
+#define AON_REG_PAD_REG20X_PAD_P6_E_7_Msk                                                                                (0x1UL << AON_REG_PAD_REG20X_PAD_P6_E_7_Pos)
+
+#define AON_REG_PAD_REG20X_PAD_P6_PU_EN_7_Pos                                                                            18U
+#define AON_REG_PAD_REG20X_PAD_P6_PU_EN_7_Msk                                                                            (0x1UL << AON_REG_PAD_REG20X_PAD_P6_PU_EN_7_Pos)
+
+#define AON_REG_PAD_REG20X_AON_PAD_P6_PD_7_Pos                                                                           19U
+#define AON_REG_PAD_REG20X_AON_PAD_P6_PD_7_Msk                                                                           (0x1UL << AON_REG_PAD_REG20X_AON_PAD_P6_PD_7_Pos)
+
+#define AON_REG_PAD_REG20X_PAD_P6_PUPDC_7_Pos                                                                            20U
+#define AON_REG_PAD_REG20X_PAD_P6_PUPDC_7_Msk                                                                            (0x1UL << AON_REG_PAD_REG20X_PAD_P6_PUPDC_7_Pos)
+
+#define AON_REG_PAD_REG20X_PAD_P6_WKEN_7_Pos                                                                             21U
+#define AON_REG_PAD_REG20X_PAD_P6_WKEN_7_Msk                                                                             (0x1UL << AON_REG_PAD_REG20X_PAD_P6_WKEN_7_Pos)
+
+#define AON_REG_PAD_REG20X_PAD_P6_WKPOL_7_Pos                                                                            22U
+#define AON_REG_PAD_REG20X_PAD_P6_WKPOL_7_Msk                                                                            (0x1UL << AON_REG_PAD_REG20X_PAD_P6_WKPOL_7_Pos)
+
+#define AON_REG_PAD_REG20X_PAD_P6_SHDN_7_Pos                                                                             23U
+#define AON_REG_PAD_REG20X_PAD_P6_SHDN_7_Msk                                                                             (0x1UL << AON_REG_PAD_REG20X_PAD_P6_SHDN_7_Pos)
+
+#define AON_REG_PAD_REG20X_PAD_P6_DEB_7_Pos                                                                              24U
+#define AON_REG_PAD_REG20X_PAD_P6_DEB_7_Msk                                                                              (0x1UL << AON_REG_PAD_REG20X_PAD_P6_DEB_7_Pos)
+
+#define AON_REG_PAD_REG20X_PAD_P6_RAP_WKEN_7_Pos                                                                         25U
+#define AON_REG_PAD_REG20X_PAD_P6_RAP_WKEN_7_Msk                                                                         (0x1UL << AON_REG_PAD_REG20X_PAD_P6_RAP_WKEN_7_Pos)
+
+#define AON_REG_PAD_REG20X_PAD_P6_PPU_WKEN_7_Pos                                                                         26U
+#define AON_REG_PAD_REG20X_PAD_P6_PPU_WKEN_7_Msk                                                                         (0x1UL << AON_REG_PAD_REG20X_PAD_P6_PPU_WKEN_7_Pos)
+
+#define AON_REG_PAD_REG20X_RESERVED_1_Pos                                                                                27U
+#define AON_REG_PAD_REG20X_RESERVED_1_Msk                                                                                (0x1UL << AON_REG_PAD_REG20X_RESERVED_1_Pos)
+
+#define AON_REG_PAD_REG20X_RESERVED_Pos                                                                                  28U
+#define AON_REG_PAD_REG20X_RESERVED_Msk                                                                                  (0x3UL << AON_REG_PAD_REG20X_RESERVED_Pos)
+
+#define AON_REG_PAD_REG20X_PAD_P6_AON_MUX_7_Pos                                                                          30U
+#define AON_REG_PAD_REG20X_PAD_P6_AON_MUX_7_Msk                                                                          (0x3UL << AON_REG_PAD_REG20X_PAD_P6_AON_MUX_7_Pos)
+
+/* 0x174    0x4000_0174
+    0       R/W     PAD_P7_O_0                                                  1'b0
+    1       R/W     PAD_P7_E_0                                                  1'b0
+    2       R/W     PAD_P7_PU_EN_0                                              1'b1
+    3       R/W     AON_PAD_P7_PD_0                                             1'b1
+    4       R/W     PAD_P7_PUPDC_0                                              1'b0
+    5       R/W     PAD_P7_WKEN_0                                               1'b0
+    6       R/W     PAD_P7_WKPOL_0                                              1'b0
+    7       R/W     PAD_P7_SHDN_0                                               1'b1
+    8       R/W     PAD_P7_DEB_0                                                1'b0
+    9       R/W     PAD_P7_RAP_WKEN_0                                           1'b0
+    10      R/W     PAD_P7_PPU_WKEN_0                                           1'b0
+    11      R/W     RESERVED_3                                                  1'b0
+    13:12   R       RESERVED_2                                                  2'b00
+    15:14   R/W     PAD_P7_AON_MUX_0                                            2'b00
+    16      R/W     PAD_P7_O_1                                                  1'b0
+    17      R/W     PAD_P7_E_1                                                  1'b0
+    18      R/W     PAD_P7_PU_EN_1                                              1'b1
+    19      R/W     AON_PAD_P7_PD_1                                             1'b1
+    20      R/W     PAD_P7_PUPDC_1                                              1'b0
+    21      R/W     PAD_P7_WKEN_1                                               1'b0
+    22      R/W     PAD_P7_WKPOL_1                                              1'b0
+    23      R/W     PAD_P7_SHDN_1                                               1'b1
+    24      R/W     PAD_P7_DEB_1                                                1'b0
+    25      R/W     PAD_P7_RAP_WKEN_1                                           1'b0
+    26      R/W     PAD_P7_PPU_WKEN_1                                           1'b0
+    27      R/W     RESERVED_1                                                  1'b0
+    29:28   R       RESERVED                                                    2'b00
+    31:30   R/W     PAD_P7_AON_MUX_1                                            2'b00
+ */
+typedef union _AON_REG_PAD_REG21X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t PAD_P7_O_0: 1;
+        uint32_t PAD_P7_E_0: 1;
+        uint32_t PAD_P7_PU_EN_0: 1;
+        uint32_t AON_PAD_P7_PD_0: 1;
+        uint32_t PAD_P7_PUPDC_0: 1;
+        uint32_t PAD_P7_WKEN_0: 1;
+        uint32_t PAD_P7_WKPOL_0: 1;
+        uint32_t PAD_P7_SHDN_0: 1;
+        uint32_t PAD_P7_DEB_0: 1;
+        uint32_t PAD_P7_RAP_WKEN_0: 1;
+        uint32_t PAD_P7_PPU_WKEN_0: 1;
+        uint32_t RESERVED_3: 1;
+        uint32_t RESERVED_2: 2;
+        uint32_t PAD_P7_AON_MUX_0: 2;
+        uint32_t PAD_P7_O_1: 1;
+        uint32_t PAD_P7_E_1: 1;
+        uint32_t PAD_P7_PU_EN_1: 1;
+        uint32_t AON_PAD_P7_PD_1: 1;
+        uint32_t PAD_P7_PUPDC_1: 1;
+        uint32_t PAD_P7_WKEN_1: 1;
+        uint32_t PAD_P7_WKPOL_1: 1;
+        uint32_t PAD_P7_SHDN_1: 1;
+        uint32_t PAD_P7_DEB_1: 1;
+        uint32_t PAD_P7_RAP_WKEN_1: 1;
+        uint32_t PAD_P7_PPU_WKEN_1: 1;
+        uint32_t RESERVED_1: 1;
+        uint32_t RESERVED: 2;
+        uint32_t PAD_P7_AON_MUX_1: 2;
+    };
+} AON_REG_PAD_REG21X_TYPE;
+
+/*0x4000_0174 AON_REG_PAD_REG21X*/
+#define AON_REG_PAD_REG21X_PAD_P7_O_0_Pos                                                                                0U
+#define AON_REG_PAD_REG21X_PAD_P7_O_0_Msk                                                                                (0x1UL << AON_REG_PAD_REG21X_PAD_P7_O_0_Pos)
+
+#define AON_REG_PAD_REG21X_PAD_P7_E_0_Pos                                                                                1U
+#define AON_REG_PAD_REG21X_PAD_P7_E_0_Msk                                                                                (0x1UL << AON_REG_PAD_REG21X_PAD_P7_E_0_Pos)
+
+#define AON_REG_PAD_REG21X_PAD_P7_PU_EN_0_Pos                                                                            2U
+#define AON_REG_PAD_REG21X_PAD_P7_PU_EN_0_Msk                                                                            (0x1UL << AON_REG_PAD_REG21X_PAD_P7_PU_EN_0_Pos)
+
+#define AON_REG_PAD_REG21X_AON_PAD_P7_PD_0_Pos                                                                           3U
+#define AON_REG_PAD_REG21X_AON_PAD_P7_PD_0_Msk                                                                           (0x1UL << AON_REG_PAD_REG21X_AON_PAD_P7_PD_0_Pos)
+
+#define AON_REG_PAD_REG21X_PAD_P7_PUPDC_0_Pos                                                                            4U
+#define AON_REG_PAD_REG21X_PAD_P7_PUPDC_0_Msk                                                                            (0x1UL << AON_REG_PAD_REG21X_PAD_P7_PUPDC_0_Pos)
+
+#define AON_REG_PAD_REG21X_PAD_P7_WKEN_0_Pos                                                                             5U
+#define AON_REG_PAD_REG21X_PAD_P7_WKEN_0_Msk                                                                             (0x1UL << AON_REG_PAD_REG21X_PAD_P7_WKEN_0_Pos)
+
+#define AON_REG_PAD_REG21X_PAD_P7_WKPOL_0_Pos                                                                            6U
+#define AON_REG_PAD_REG21X_PAD_P7_WKPOL_0_Msk                                                                            (0x1UL << AON_REG_PAD_REG21X_PAD_P7_WKPOL_0_Pos)
+
+#define AON_REG_PAD_REG21X_PAD_P7_SHDN_0_Pos                                                                             7U
+#define AON_REG_PAD_REG21X_PAD_P7_SHDN_0_Msk                                                                             (0x1UL << AON_REG_PAD_REG21X_PAD_P7_SHDN_0_Pos)
+
+#define AON_REG_PAD_REG21X_PAD_P7_DEB_0_Pos                                                                              8U
+#define AON_REG_PAD_REG21X_PAD_P7_DEB_0_Msk                                                                              (0x1UL << AON_REG_PAD_REG21X_PAD_P7_DEB_0_Pos)
+
+#define AON_REG_PAD_REG21X_PAD_P7_RAP_WKEN_0_Pos                                                                         9U
+#define AON_REG_PAD_REG21X_PAD_P7_RAP_WKEN_0_Msk                                                                         (0x1UL << AON_REG_PAD_REG21X_PAD_P7_RAP_WKEN_0_Pos)
+
+#define AON_REG_PAD_REG21X_PAD_P7_PPU_WKEN_0_Pos                                                                         10U
+#define AON_REG_PAD_REG21X_PAD_P7_PPU_WKEN_0_Msk                                                                         (0x1UL << AON_REG_PAD_REG21X_PAD_P7_PPU_WKEN_0_Pos)
+
+#define AON_REG_PAD_REG21X_RESERVED_3_Pos                                                                                11U
+#define AON_REG_PAD_REG21X_RESERVED_3_Msk                                                                                (0x1UL << AON_REG_PAD_REG21X_RESERVED_3_Pos)
+
+#define AON_REG_PAD_REG21X_RESERVED_2_Pos                                                                                12U
+#define AON_REG_PAD_REG21X_RESERVED_2_Msk                                                                                (0x3UL << AON_REG_PAD_REG21X_RESERVED_2_Pos)
+
+#define AON_REG_PAD_REG21X_PAD_P7_AON_MUX_0_Pos                                                                          14U
+#define AON_REG_PAD_REG21X_PAD_P7_AON_MUX_0_Msk                                                                          (0x3UL << AON_REG_PAD_REG21X_PAD_P7_AON_MUX_0_Pos)
+
+#define AON_REG_PAD_REG21X_PAD_P7_O_1_Pos                                                                                16U
+#define AON_REG_PAD_REG21X_PAD_P7_O_1_Msk                                                                                (0x1UL << AON_REG_PAD_REG21X_PAD_P7_O_1_Pos)
+
+#define AON_REG_PAD_REG21X_PAD_P7_E_1_Pos                                                                                17U
+#define AON_REG_PAD_REG21X_PAD_P7_E_1_Msk                                                                                (0x1UL << AON_REG_PAD_REG21X_PAD_P7_E_1_Pos)
+
+#define AON_REG_PAD_REG21X_PAD_P7_PU_EN_1_Pos                                                                            18U
+#define AON_REG_PAD_REG21X_PAD_P7_PU_EN_1_Msk                                                                            (0x1UL << AON_REG_PAD_REG21X_PAD_P7_PU_EN_1_Pos)
+
+#define AON_REG_PAD_REG21X_AON_PAD_P7_PD_1_Pos                                                                           19U
+#define AON_REG_PAD_REG21X_AON_PAD_P7_PD_1_Msk                                                                           (0x1UL << AON_REG_PAD_REG21X_AON_PAD_P7_PD_1_Pos)
+
+#define AON_REG_PAD_REG21X_PAD_P7_PUPDC_1_Pos                                                                            20U
+#define AON_REG_PAD_REG21X_PAD_P7_PUPDC_1_Msk                                                                            (0x1UL << AON_REG_PAD_REG21X_PAD_P7_PUPDC_1_Pos)
+
+#define AON_REG_PAD_REG21X_PAD_P7_WKEN_1_Pos                                                                             21U
+#define AON_REG_PAD_REG21X_PAD_P7_WKEN_1_Msk                                                                             (0x1UL << AON_REG_PAD_REG21X_PAD_P7_WKEN_1_Pos)
+
+#define AON_REG_PAD_REG21X_PAD_P7_WKPOL_1_Pos                                                                            22U
+#define AON_REG_PAD_REG21X_PAD_P7_WKPOL_1_Msk                                                                            (0x1UL << AON_REG_PAD_REG21X_PAD_P7_WKPOL_1_Pos)
+
+#define AON_REG_PAD_REG21X_PAD_P7_SHDN_1_Pos                                                                             23U
+#define AON_REG_PAD_REG21X_PAD_P7_SHDN_1_Msk                                                                             (0x1UL << AON_REG_PAD_REG21X_PAD_P7_SHDN_1_Pos)
+
+#define AON_REG_PAD_REG21X_PAD_P7_DEB_1_Pos                                                                              24U
+#define AON_REG_PAD_REG21X_PAD_P7_DEB_1_Msk                                                                              (0x1UL << AON_REG_PAD_REG21X_PAD_P7_DEB_1_Pos)
+
+#define AON_REG_PAD_REG21X_PAD_P7_RAP_WKEN_1_Pos                                                                         25U
+#define AON_REG_PAD_REG21X_PAD_P7_RAP_WKEN_1_Msk                                                                         (0x1UL << AON_REG_PAD_REG21X_PAD_P7_RAP_WKEN_1_Pos)
+
+#define AON_REG_PAD_REG21X_PAD_P7_PPU_WKEN_1_Pos                                                                         26U
+#define AON_REG_PAD_REG21X_PAD_P7_PPU_WKEN_1_Msk                                                                         (0x1UL << AON_REG_PAD_REG21X_PAD_P7_PPU_WKEN_1_Pos)
+
+#define AON_REG_PAD_REG21X_RESERVED_1_Pos                                                                                27U
+#define AON_REG_PAD_REG21X_RESERVED_1_Msk                                                                                (0x1UL << AON_REG_PAD_REG21X_RESERVED_1_Pos)
+
+#define AON_REG_PAD_REG21X_RESERVED_Pos                                                                                  28U
+#define AON_REG_PAD_REG21X_RESERVED_Msk                                                                                  (0x3UL << AON_REG_PAD_REG21X_RESERVED_Pos)
+
+#define AON_REG_PAD_REG21X_PAD_P7_AON_MUX_1_Pos                                                                          30U
+#define AON_REG_PAD_REG21X_PAD_P7_AON_MUX_1_Msk                                                                          (0x3UL << AON_REG_PAD_REG21X_PAD_P7_AON_MUX_1_Pos)
+
+/* 0x178    0x4000_0178
+    0       R/W     PAD_MICBIAS_O                                               1'b0
+    1       R/W     PAD_MICBIAS_E                                               1'b0
+    2       R/W     PAD_MICBIAS_PU_EN                                           1'b1
+    3       R/W     AON_PAD_MICBIAS_PD                                          1'b1
+    4       R/W     PAD_MICBIAS_PUPDC                                           1'b0
+    5       R/W     PAD_MICBIAS_WKEN                                            1'b0
+    6       R/W     PAD_MICBIAS_WKPOL                                           1'b0
+    7       R/W     PAD_MICBIAS_SHDN                                            1'b1
+    8       R/W     PAD_MICBIAS_DEB                                             1'b0
+    9       R/W     PAD_MICBIAS_RAP_WKEN                                        1'b0
+    10      R/W     PAD_MICBIAS_PPU_WKEN                                        1'b0
+    11      R/W     RESERVED_2                                                  1'b0
+    12      R/W     DUMMY_PAD8                                                  1'b0
+    13      R/W     RESERVED_1                                                  1'b0
+    15:14   R/W     PAD_MICBIAS_AON_MUX                                         2'b00
+    31:16   R       RESERVED                                                    16'h0
+ */
+typedef union _AON_REG_PAD_REG22X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t PAD_MICBIAS_O: 1;
+        uint32_t PAD_MICBIAS_E: 1;
+        uint32_t PAD_MICBIAS_PU_EN: 1;
+        uint32_t AON_PAD_MICBIAS_PD: 1;
+        uint32_t PAD_MICBIAS_PUPDC: 1;
+        uint32_t PAD_MICBIAS_WKEN: 1;
+        uint32_t PAD_MICBIAS_WKPOL: 1;
+        uint32_t PAD_MICBIAS_SHDN: 1;
+        uint32_t PAD_MICBIAS_DEB: 1;
+        uint32_t PAD_MICBIAS_RAP_WKEN: 1;
+        uint32_t PAD_MICBIAS_PPU_WKEN: 1;
+        uint32_t RESERVED_2: 1;
+        uint32_t DUMMY_PAD8: 1;
+        uint32_t RESERVED_1: 1;
+        uint32_t PAD_MICBIAS_AON_MUX: 2;
+        uint32_t RESERVED: 16;
+    };
+} AON_REG_PAD_REG22X_TYPE;
+
+/*0x4000_0178 AON_REG_PAD_REG22X*/
+#define AON_REG_PAD_REG22X_PAD_MICBIAS_O_Pos                                                                             0U
+#define AON_REG_PAD_REG22X_PAD_MICBIAS_O_Msk                                                                             (0x1UL << AON_REG_PAD_REG22X_PAD_MICBIAS_O_Pos)
+
+#define AON_REG_PAD_REG22X_PAD_MICBIAS_E_Pos                                                                             1U
+#define AON_REG_PAD_REG22X_PAD_MICBIAS_E_Msk                                                                             (0x1UL << AON_REG_PAD_REG22X_PAD_MICBIAS_E_Pos)
+
+#define AON_REG_PAD_REG22X_PAD_MICBIAS_PU_EN_Pos                                                                         2U
+#define AON_REG_PAD_REG22X_PAD_MICBIAS_PU_EN_Msk                                                                         (0x1UL << AON_REG_PAD_REG22X_PAD_MICBIAS_PU_EN_Pos)
+
+#define AON_REG_PAD_REG22X_AON_PAD_MICBIAS_PD_Pos                                                                        3U
+#define AON_REG_PAD_REG22X_AON_PAD_MICBIAS_PD_Msk                                                                        (0x1UL << AON_REG_PAD_REG22X_AON_PAD_MICBIAS_PD_Pos)
+
+#define AON_REG_PAD_REG22X_PAD_MICBIAS_PUPDC_Pos                                                                         4U
+#define AON_REG_PAD_REG22X_PAD_MICBIAS_PUPDC_Msk                                                                         (0x1UL << AON_REG_PAD_REG22X_PAD_MICBIAS_PUPDC_Pos)
+
+#define AON_REG_PAD_REG22X_PAD_MICBIAS_WKEN_Pos                                                                          5U
+#define AON_REG_PAD_REG22X_PAD_MICBIAS_WKEN_Msk                                                                          (0x1UL << AON_REG_PAD_REG22X_PAD_MICBIAS_WKEN_Pos)
+
+#define AON_REG_PAD_REG22X_PAD_MICBIAS_WKPOL_Pos                                                                         6U
+#define AON_REG_PAD_REG22X_PAD_MICBIAS_WKPOL_Msk                                                                         (0x1UL << AON_REG_PAD_REG22X_PAD_MICBIAS_WKPOL_Pos)
+
+#define AON_REG_PAD_REG22X_PAD_MICBIAS_SHDN_Pos                                                                          7U
+#define AON_REG_PAD_REG22X_PAD_MICBIAS_SHDN_Msk                                                                          (0x1UL << AON_REG_PAD_REG22X_PAD_MICBIAS_SHDN_Pos)
+
+#define AON_REG_PAD_REG22X_PAD_MICBIAS_DEB_Pos                                                                           8U
+#define AON_REG_PAD_REG22X_PAD_MICBIAS_DEB_Msk                                                                           (0x1UL << AON_REG_PAD_REG22X_PAD_MICBIAS_DEB_Pos)
+
+#define AON_REG_PAD_REG22X_PAD_MICBIAS_RAP_WKEN_Pos                                                                      9U
+#define AON_REG_PAD_REG22X_PAD_MICBIAS_RAP_WKEN_Msk                                                                      (0x1UL << AON_REG_PAD_REG22X_PAD_MICBIAS_RAP_WKEN_Pos)
+
+#define AON_REG_PAD_REG22X_PAD_MICBIAS_PPU_WKEN_Pos                                                                      10U
+#define AON_REG_PAD_REG22X_PAD_MICBIAS_PPU_WKEN_Msk                                                                      (0x1UL << AON_REG_PAD_REG22X_PAD_MICBIAS_PPU_WKEN_Pos)
+
+#define AON_REG_PAD_REG22X_RESERVED_2_Pos                                                                                11U
+#define AON_REG_PAD_REG22X_RESERVED_2_Msk                                                                                (0x1UL << AON_REG_PAD_REG22X_RESERVED_2_Pos)
+
+#define AON_REG_PAD_REG22X_DUMMY_PAD8_Pos                                                                                12U
+#define AON_REG_PAD_REG22X_DUMMY_PAD8_Msk                                                                                (0x1UL << AON_REG_PAD_REG22X_DUMMY_PAD8_Pos)
+
+#define AON_REG_PAD_REG22X_RESERVED_1_Pos                                                                                13U
+#define AON_REG_PAD_REG22X_RESERVED_1_Msk                                                                                (0x1UL << AON_REG_PAD_REG22X_RESERVED_1_Pos)
+
+#define AON_REG_PAD_REG22X_PAD_MICBIAS_AON_MUX_Pos                                                                       14U
+#define AON_REG_PAD_REG22X_PAD_MICBIAS_AON_MUX_Msk                                                                       (0x3UL << AON_REG_PAD_REG22X_PAD_MICBIAS_AON_MUX_Pos)
+
+#define AON_REG_PAD_REG22X_RESERVED_Pos                                                                                  16U
+#define AON_REG_PAD_REG22X_RESERVED_Msk                                                                                  (0xFFFFUL << AON_REG_PAD_REG22X_RESERVED_Pos)
+
+/* 0x17C    0x4000_017c
+    0       W1C     PAD_P0_STS_0                                                1'b1
+    1       W1C     PAD_P0_STS_1                                                1'b1
+    2       W1C     PAD_P0_STS_2                                                1'b1
+    3       W1C     PAD_P0_STS_3                                                1'b1
+    4       W1C     PAD_P0_STS_4                                                1'b1
+    5       W1C     PAD_P0_STS_5                                                1'b1
+    6       W1C     PAD_P0_STS_6                                                1'b1
+    7       W1C     PAD_P0_STS_7                                                1'b1
+    8       R/W     PAD_P0_1_RTC_CLK_OUT_EN                                     1'b0
+    9       R/W     PAD_P0_3_RTC_CLK_OUT_EN                                     1'b0
+    10      R/W     PAD_P0_1_O_EN                                               1'b1
+    11      R/W     PAD_P0_4_O_EN                                               1'b1
+    12      W1C     PAD_P1_STS_0                                                1'b1
+    13      W1C     PAD_P1_STS_1                                                1'b1
+    14      W1C     PAD_P1_STS_6                                                1'b1
+    15      W1C     PAD_P1_STS_7                                                1'b1
+    16      W1C     PAD_P2_STS_0                                                1'b1
+    17      W1C     PAD_P2_STS_1                                                1'b1
+    18      W1C     PAD_P2_STS_2                                                1'b1
+    19      W1C     PAD_P2_STS_3                                                1'b1
+    20      W1C     PAD_P2_STS_4                                                1'b1
+    21      W1C     PAD_P2_STS_5                                                1'b1
+    22      W1C     PAD_P2_STS_6                                                1'b1
+    23      W1C     PAD_P2_STS_7                                                1'b1
+    25:24   R/W     PAD_P2_1_CFG                                                2'b00
+    27:26   R/W     PAD_P2_5_CFG                                                2'b00
+    28      R/W     PAD_P2_6_CFG                                                1'b0
+    29      R/W     PAD_P2_7_CFG                                                1'b0
+    30      R/W     PAD_P2_5_O_EN                                               1'b1
+    31      R       RESERVED                                                    1'b0
+ */
+typedef union _AON_REG_PAD_REG23X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t PAD_P0_STS_0: 1;
+        uint32_t PAD_P0_STS_1: 1;
+        uint32_t PAD_P0_STS_2: 1;
+        uint32_t PAD_P0_STS_3: 1;
+        uint32_t PAD_P0_STS_4: 1;
+        uint32_t PAD_P0_STS_5: 1;
+        uint32_t PAD_P0_STS_6: 1;
+        uint32_t PAD_P0_STS_7: 1;
+        uint32_t PAD_P0_1_RTC_CLK_OUT_EN: 1;
+        uint32_t PAD_P0_3_RTC_CLK_OUT_EN: 1;
+        uint32_t PAD_P0_1_O_EN: 1;
+        uint32_t PAD_P0_4_O_EN: 1;
+        uint32_t PAD_P1_STS_0: 1;
+        uint32_t PAD_P1_STS_1: 1;
+        uint32_t PAD_P1_STS_6: 1;
+        uint32_t PAD_P1_STS_7: 1;
+        uint32_t PAD_P2_STS_0: 1;
+        uint32_t PAD_P2_STS_1: 1;
+        uint32_t PAD_P2_STS_2: 1;
+        uint32_t PAD_P2_STS_3: 1;
+        uint32_t PAD_P2_STS_4: 1;
+        uint32_t PAD_P2_STS_5: 1;
+        uint32_t PAD_P2_STS_6: 1;
+        uint32_t PAD_P2_STS_7: 1;
+        uint32_t PAD_P2_1_CFG: 2;
+        uint32_t PAD_P2_5_CFG: 2;
+        uint32_t PAD_P2_6_CFG: 1;
+        uint32_t PAD_P2_7_CFG: 1;
+        uint32_t PAD_P2_5_O_EN: 1;
+        uint32_t RESERVED: 1;
+    };
+} AON_REG_PAD_REG23X_TYPE;
+
+/*0x4000_017c AON_REG_PAD_REG23X*/
+#define AON_REG_PAD_REG23X_PAD_P0_STS_0_Pos                                                                              0U
+#define AON_REG_PAD_REG23X_PAD_P0_STS_0_Msk                                                                              (0x1UL << AON_REG_PAD_REG23X_PAD_P0_STS_0_Pos)
+
+#define AON_REG_PAD_REG23X_PAD_P0_STS_1_Pos                                                                              1U
+#define AON_REG_PAD_REG23X_PAD_P0_STS_1_Msk                                                                              (0x1UL << AON_REG_PAD_REG23X_PAD_P0_STS_1_Pos)
+
+#define AON_REG_PAD_REG23X_PAD_P0_STS_2_Pos                                                                              2U
+#define AON_REG_PAD_REG23X_PAD_P0_STS_2_Msk                                                                              (0x1UL << AON_REG_PAD_REG23X_PAD_P0_STS_2_Pos)
+
+#define AON_REG_PAD_REG23X_PAD_P0_STS_3_Pos                                                                              3U
+#define AON_REG_PAD_REG23X_PAD_P0_STS_3_Msk                                                                              (0x1UL << AON_REG_PAD_REG23X_PAD_P0_STS_3_Pos)
+
+#define AON_REG_PAD_REG23X_PAD_P0_STS_4_Pos                                                                              4U
+#define AON_REG_PAD_REG23X_PAD_P0_STS_4_Msk                                                                              (0x1UL << AON_REG_PAD_REG23X_PAD_P0_STS_4_Pos)
+
+#define AON_REG_PAD_REG23X_PAD_P0_STS_5_Pos                                                                              5U
+#define AON_REG_PAD_REG23X_PAD_P0_STS_5_Msk                                                                              (0x1UL << AON_REG_PAD_REG23X_PAD_P0_STS_5_Pos)
+
+#define AON_REG_PAD_REG23X_PAD_P0_STS_6_Pos                                                                              6U
+#define AON_REG_PAD_REG23X_PAD_P0_STS_6_Msk                                                                              (0x1UL << AON_REG_PAD_REG23X_PAD_P0_STS_6_Pos)
+
+#define AON_REG_PAD_REG23X_PAD_P0_STS_7_Pos                                                                              7U
+#define AON_REG_PAD_REG23X_PAD_P0_STS_7_Msk                                                                              (0x1UL << AON_REG_PAD_REG23X_PAD_P0_STS_7_Pos)
+
+#define AON_REG_PAD_REG23X_PAD_P0_1_RTC_CLK_OUT_EN_Pos                                                                   8U
+#define AON_REG_PAD_REG23X_PAD_P0_1_RTC_CLK_OUT_EN_Msk                                                                   (0x1UL << AON_REG_PAD_REG23X_PAD_P0_1_RTC_CLK_OUT_EN_Pos)
+
+#define AON_REG_PAD_REG23X_PAD_P0_3_RTC_CLK_OUT_EN_Pos                                                                   9U
+#define AON_REG_PAD_REG23X_PAD_P0_3_RTC_CLK_OUT_EN_Msk                                                                   (0x1UL << AON_REG_PAD_REG23X_PAD_P0_3_RTC_CLK_OUT_EN_Pos)
+
+#define AON_REG_PAD_REG23X_PAD_P0_1_O_EN_Pos                                                                             10U
+#define AON_REG_PAD_REG23X_PAD_P0_1_O_EN_Msk                                                                             (0x1UL << AON_REG_PAD_REG23X_PAD_P0_1_O_EN_Pos)
+
+#define AON_REG_PAD_REG23X_PAD_P0_4_O_EN_Pos                                                                             11U
+#define AON_REG_PAD_REG23X_PAD_P0_4_O_EN_Msk                                                                             (0x1UL << AON_REG_PAD_REG23X_PAD_P0_4_O_EN_Pos)
+
+#define AON_REG_PAD_REG23X_PAD_P1_STS_0_Pos                                                                              12U
+#define AON_REG_PAD_REG23X_PAD_P1_STS_0_Msk                                                                              (0x1UL << AON_REG_PAD_REG23X_PAD_P1_STS_0_Pos)
+
+#define AON_REG_PAD_REG23X_PAD_P1_STS_1_Pos                                                                              13U
+#define AON_REG_PAD_REG23X_PAD_P1_STS_1_Msk                                                                              (0x1UL << AON_REG_PAD_REG23X_PAD_P1_STS_1_Pos)
+
+#define AON_REG_PAD_REG23X_PAD_P1_STS_6_Pos                                                                              14U
+#define AON_REG_PAD_REG23X_PAD_P1_STS_6_Msk                                                                              (0x1UL << AON_REG_PAD_REG23X_PAD_P1_STS_6_Pos)
+
+#define AON_REG_PAD_REG23X_PAD_P1_STS_7_Pos                                                                              15U
+#define AON_REG_PAD_REG23X_PAD_P1_STS_7_Msk                                                                              (0x1UL << AON_REG_PAD_REG23X_PAD_P1_STS_7_Pos)
+
+#define AON_REG_PAD_REG23X_PAD_P2_STS_0_Pos                                                                              16U
+#define AON_REG_PAD_REG23X_PAD_P2_STS_0_Msk                                                                              (0x1UL << AON_REG_PAD_REG23X_PAD_P2_STS_0_Pos)
+
+#define AON_REG_PAD_REG23X_PAD_P2_STS_1_Pos                                                                              17U
+#define AON_REG_PAD_REG23X_PAD_P2_STS_1_Msk                                                                              (0x1UL << AON_REG_PAD_REG23X_PAD_P2_STS_1_Pos)
+
+#define AON_REG_PAD_REG23X_PAD_P2_STS_2_Pos                                                                              18U
+#define AON_REG_PAD_REG23X_PAD_P2_STS_2_Msk                                                                              (0x1UL << AON_REG_PAD_REG23X_PAD_P2_STS_2_Pos)
+
+#define AON_REG_PAD_REG23X_PAD_P2_STS_3_Pos                                                                              19U
+#define AON_REG_PAD_REG23X_PAD_P2_STS_3_Msk                                                                              (0x1UL << AON_REG_PAD_REG23X_PAD_P2_STS_3_Pos)
+
+#define AON_REG_PAD_REG23X_PAD_P2_STS_4_Pos                                                                              20U
+#define AON_REG_PAD_REG23X_PAD_P2_STS_4_Msk                                                                              (0x1UL << AON_REG_PAD_REG23X_PAD_P2_STS_4_Pos)
+
+#define AON_REG_PAD_REG23X_PAD_P2_STS_5_Pos                                                                              21U
+#define AON_REG_PAD_REG23X_PAD_P2_STS_5_Msk                                                                              (0x1UL << AON_REG_PAD_REG23X_PAD_P2_STS_5_Pos)
+
+#define AON_REG_PAD_REG23X_PAD_P2_STS_6_Pos                                                                              22U
+#define AON_REG_PAD_REG23X_PAD_P2_STS_6_Msk                                                                              (0x1UL << AON_REG_PAD_REG23X_PAD_P2_STS_6_Pos)
+
+#define AON_REG_PAD_REG23X_PAD_P2_STS_7_Pos                                                                              23U
+#define AON_REG_PAD_REG23X_PAD_P2_STS_7_Msk                                                                              (0x1UL << AON_REG_PAD_REG23X_PAD_P2_STS_7_Pos)
+
+#define AON_REG_PAD_REG23X_PAD_P2_1_CFG_Pos                                                                              24U
+#define AON_REG_PAD_REG23X_PAD_P2_1_CFG_Msk                                                                              (0x3UL << AON_REG_PAD_REG23X_PAD_P2_1_CFG_Pos)
+
+#define AON_REG_PAD_REG23X_PAD_P2_5_CFG_Pos                                                                              26U
+#define AON_REG_PAD_REG23X_PAD_P2_5_CFG_Msk                                                                              (0x3UL << AON_REG_PAD_REG23X_PAD_P2_5_CFG_Pos)
+
+#define AON_REG_PAD_REG23X_PAD_P2_6_CFG_Pos                                                                              28U
+#define AON_REG_PAD_REG23X_PAD_P2_6_CFG_Msk                                                                              (0x1UL << AON_REG_PAD_REG23X_PAD_P2_6_CFG_Pos)
+
+#define AON_REG_PAD_REG23X_PAD_P2_7_CFG_Pos                                                                              29U
+#define AON_REG_PAD_REG23X_PAD_P2_7_CFG_Msk                                                                              (0x1UL << AON_REG_PAD_REG23X_PAD_P2_7_CFG_Pos)
+
+#define AON_REG_PAD_REG23X_PAD_P2_5_O_EN_Pos                                                                             30U
+#define AON_REG_PAD_REG23X_PAD_P2_5_O_EN_Msk                                                                             (0x1UL << AON_REG_PAD_REG23X_PAD_P2_5_O_EN_Pos)
+
+#define AON_REG_PAD_REG23X_RESERVED_Pos                                                                                  31U
+#define AON_REG_PAD_REG23X_RESERVED_Msk                                                                                  (0x1UL << AON_REG_PAD_REG23X_RESERVED_Pos)
+
+/* 0x180    0x4000_0180
+    0       W1C     PAD_P3_STS_0                                                1'b1
+    1       W1C     PAD_P3_STS_1                                                1'b1
+    2       W1C     PAD_P3_STS_2                                                1'b1
+    3       W1C     PAD_P3_STS_3                                                1'b1
+    4       W1C     PAD_P3_STS_4                                                1'b1
+    5       W1C     PAD_P3_STS_5                                                1'b1
+    6       W1C     PAD_P3_STS_6                                                1'b1
+    7       W1C     PAD_P4_STS_0                                                1'b1
+    8       W1C     PAD_P4_STS_1                                                1'b1
+    9       W1C     PAD_P4_STS_2                                                1'b1
+    10      W1C     PAD_P4_STS_3                                                1'b1
+    12:11   R/W     PAD_P4_0_CFG                                                2'b00
+    13      R/W     PAD_P4_1_CFG                                                1'b0
+    14      R/W     PAD_P4_2_CFG                                                1'b0
+    15      R/W     PAD_P4_0_O_EN                                               1'b1
+    16      R/W     PAD_P4_2_O_EN                                               1'b1
+    17      R       RESERVED_2                                                  1'b0
+    18      W1C     PAD_P5_STS_1                                                1'b1
+    19      W1C     PAD_P5_STS_2                                                1'b1
+    20      R       RESERVED_1                                                  1'b0
+    21      W1C     PAD_P6_STS_0                                                1'b1
+    22      W1C     PAD_P6_STS_1                                                1'b1
+    23      W1C     PAD_P6_STS_2                                                1'b1
+    24      W1C     PAD_P6_STS_3                                                1'b1
+    25      W1C     PAD_P6_STS_4                                                1'b1
+    26      W1C     PAD_P6_STS_5                                                1'b1
+    27      W1C     PAD_P6_STS_6                                                1'b1
+    28      W1C     PAD_P6_STS_7                                                1'b1
+    31:29   R       RESERVED                                                    3'b000
+ */
+typedef union _AON_REG_PAD_REG24X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t PAD_P3_STS_0: 1;
+        uint32_t PAD_P3_STS_1: 1;
+        uint32_t PAD_P3_STS_2: 1;
+        uint32_t PAD_P3_STS_3: 1;
+        uint32_t PAD_P3_STS_4: 1;
+        uint32_t PAD_P3_STS_5: 1;
+        uint32_t PAD_P3_STS_6: 1;
+        uint32_t PAD_P4_STS_0: 1;
+        uint32_t PAD_P4_STS_1: 1;
+        uint32_t PAD_P4_STS_2: 1;
+        uint32_t PAD_P4_STS_3: 1;
+        uint32_t PAD_P4_0_CFG: 2;
+        uint32_t PAD_P4_1_CFG: 1;
+        uint32_t PAD_P4_2_CFG: 1;
+        uint32_t PAD_P4_0_O_EN: 1;
+        uint32_t PAD_P4_2_O_EN: 1;
+        uint32_t RESERVED_2: 1;
+        uint32_t PAD_P5_STS_1: 1;
+        uint32_t PAD_P5_STS_2: 1;
+        uint32_t RESERVED_1: 1;
+        uint32_t PAD_P6_STS_0: 1;
+        uint32_t PAD_P6_STS_1: 1;
+        uint32_t PAD_P6_STS_2: 1;
+        uint32_t PAD_P6_STS_3: 1;
+        uint32_t PAD_P6_STS_4: 1;
+        uint32_t PAD_P6_STS_5: 1;
+        uint32_t PAD_P6_STS_6: 1;
+        uint32_t PAD_P6_STS_7: 1;
+        uint32_t RESERVED: 3;
+    };
+} AON_REG_PAD_REG24X_TYPE;
+
+/*0x4000_0180 AON_REG_PAD_REG24X*/
+#define AON_REG_PAD_REG24X_PAD_P3_STS_0_Pos                                                                              0U
+#define AON_REG_PAD_REG24X_PAD_P3_STS_0_Msk                                                                              (0x1UL << AON_REG_PAD_REG24X_PAD_P3_STS_0_Pos)
+
+#define AON_REG_PAD_REG24X_PAD_P3_STS_1_Pos                                                                              1U
+#define AON_REG_PAD_REG24X_PAD_P3_STS_1_Msk                                                                              (0x1UL << AON_REG_PAD_REG24X_PAD_P3_STS_1_Pos)
+
+#define AON_REG_PAD_REG24X_PAD_P3_STS_2_Pos                                                                              2U
+#define AON_REG_PAD_REG24X_PAD_P3_STS_2_Msk                                                                              (0x1UL << AON_REG_PAD_REG24X_PAD_P3_STS_2_Pos)
+
+#define AON_REG_PAD_REG24X_PAD_P3_STS_3_Pos                                                                              3U
+#define AON_REG_PAD_REG24X_PAD_P3_STS_3_Msk                                                                              (0x1UL << AON_REG_PAD_REG24X_PAD_P3_STS_3_Pos)
+
+#define AON_REG_PAD_REG24X_PAD_P3_STS_4_Pos                                                                              4U
+#define AON_REG_PAD_REG24X_PAD_P3_STS_4_Msk                                                                              (0x1UL << AON_REG_PAD_REG24X_PAD_P3_STS_4_Pos)
+
+#define AON_REG_PAD_REG24X_PAD_P3_STS_5_Pos                                                                              5U
+#define AON_REG_PAD_REG24X_PAD_P3_STS_5_Msk                                                                              (0x1UL << AON_REG_PAD_REG24X_PAD_P3_STS_5_Pos)
+
+#define AON_REG_PAD_REG24X_PAD_P3_STS_6_Pos                                                                              6U
+#define AON_REG_PAD_REG24X_PAD_P3_STS_6_Msk                                                                              (0x1UL << AON_REG_PAD_REG24X_PAD_P3_STS_6_Pos)
+
+#define AON_REG_PAD_REG24X_PAD_P4_STS_0_Pos                                                                              7U
+#define AON_REG_PAD_REG24X_PAD_P4_STS_0_Msk                                                                              (0x1UL << AON_REG_PAD_REG24X_PAD_P4_STS_0_Pos)
+
+#define AON_REG_PAD_REG24X_PAD_P4_STS_1_Pos                                                                              8U
+#define AON_REG_PAD_REG24X_PAD_P4_STS_1_Msk                                                                              (0x1UL << AON_REG_PAD_REG24X_PAD_P4_STS_1_Pos)
+
+#define AON_REG_PAD_REG24X_PAD_P4_STS_2_Pos                                                                              9U
+#define AON_REG_PAD_REG24X_PAD_P4_STS_2_Msk                                                                              (0x1UL << AON_REG_PAD_REG24X_PAD_P4_STS_2_Pos)
+
+#define AON_REG_PAD_REG24X_PAD_P4_STS_3_Pos                                                                              10U
+#define AON_REG_PAD_REG24X_PAD_P4_STS_3_Msk                                                                              (0x1UL << AON_REG_PAD_REG24X_PAD_P4_STS_3_Pos)
+
+#define AON_REG_PAD_REG24X_PAD_P4_0_CFG_Pos                                                                              11U
+#define AON_REG_PAD_REG24X_PAD_P4_0_CFG_Msk                                                                              (0x3UL << AON_REG_PAD_REG24X_PAD_P4_0_CFG_Pos)
+
+#define AON_REG_PAD_REG24X_PAD_P4_1_CFG_Pos                                                                              13U
+#define AON_REG_PAD_REG24X_PAD_P4_1_CFG_Msk                                                                              (0x1UL << AON_REG_PAD_REG24X_PAD_P4_1_CFG_Pos)
+
+#define AON_REG_PAD_REG24X_PAD_P4_2_CFG_Pos                                                                              14U
+#define AON_REG_PAD_REG24X_PAD_P4_2_CFG_Msk                                                                              (0x1UL << AON_REG_PAD_REG24X_PAD_P4_2_CFG_Pos)
+
+#define AON_REG_PAD_REG24X_PAD_P4_0_O_EN_Pos                                                                             15U
+#define AON_REG_PAD_REG24X_PAD_P4_0_O_EN_Msk                                                                             (0x1UL << AON_REG_PAD_REG24X_PAD_P4_0_O_EN_Pos)
+
+#define AON_REG_PAD_REG24X_PAD_P4_2_O_EN_Pos                                                                             16U
+#define AON_REG_PAD_REG24X_PAD_P4_2_O_EN_Msk                                                                             (0x1UL << AON_REG_PAD_REG24X_PAD_P4_2_O_EN_Pos)
+
+#define AON_REG_PAD_REG24X_RESERVED_2_Pos                                                                                17U
+#define AON_REG_PAD_REG24X_RESERVED_2_Msk                                                                                (0x1UL << AON_REG_PAD_REG24X_RESERVED_2_Pos)
+
+#define AON_REG_PAD_REG24X_PAD_P5_STS_1_Pos                                                                              18U
+#define AON_REG_PAD_REG24X_PAD_P5_STS_1_Msk                                                                              (0x1UL << AON_REG_PAD_REG24X_PAD_P5_STS_1_Pos)
+
+#define AON_REG_PAD_REG24X_PAD_P5_STS_2_Pos                                                                              19U
+#define AON_REG_PAD_REG24X_PAD_P5_STS_2_Msk                                                                              (0x1UL << AON_REG_PAD_REG24X_PAD_P5_STS_2_Pos)
+
+#define AON_REG_PAD_REG24X_RESERVED_1_Pos                                                                                20U
+#define AON_REG_PAD_REG24X_RESERVED_1_Msk                                                                                (0x1UL << AON_REG_PAD_REG24X_RESERVED_1_Pos)
+
+#define AON_REG_PAD_REG24X_PAD_P6_STS_0_Pos                                                                              21U
+#define AON_REG_PAD_REG24X_PAD_P6_STS_0_Msk                                                                              (0x1UL << AON_REG_PAD_REG24X_PAD_P6_STS_0_Pos)
+
+#define AON_REG_PAD_REG24X_PAD_P6_STS_1_Pos                                                                              22U
+#define AON_REG_PAD_REG24X_PAD_P6_STS_1_Msk                                                                              (0x1UL << AON_REG_PAD_REG24X_PAD_P6_STS_1_Pos)
+
+#define AON_REG_PAD_REG24X_PAD_P6_STS_2_Pos                                                                              23U
+#define AON_REG_PAD_REG24X_PAD_P6_STS_2_Msk                                                                              (0x1UL << AON_REG_PAD_REG24X_PAD_P6_STS_2_Pos)
+
+#define AON_REG_PAD_REG24X_PAD_P6_STS_3_Pos                                                                              24U
+#define AON_REG_PAD_REG24X_PAD_P6_STS_3_Msk                                                                              (0x1UL << AON_REG_PAD_REG24X_PAD_P6_STS_3_Pos)
+
+#define AON_REG_PAD_REG24X_PAD_P6_STS_4_Pos                                                                              25U
+#define AON_REG_PAD_REG24X_PAD_P6_STS_4_Msk                                                                              (0x1UL << AON_REG_PAD_REG24X_PAD_P6_STS_4_Pos)
+
+#define AON_REG_PAD_REG24X_PAD_P6_STS_5_Pos                                                                              26U
+#define AON_REG_PAD_REG24X_PAD_P6_STS_5_Msk                                                                              (0x1UL << AON_REG_PAD_REG24X_PAD_P6_STS_5_Pos)
+
+#define AON_REG_PAD_REG24X_PAD_P6_STS_6_Pos                                                                              27U
+#define AON_REG_PAD_REG24X_PAD_P6_STS_6_Msk                                                                              (0x1UL << AON_REG_PAD_REG24X_PAD_P6_STS_6_Pos)
+
+#define AON_REG_PAD_REG24X_PAD_P6_STS_7_Pos                                                                              28U
+#define AON_REG_PAD_REG24X_PAD_P6_STS_7_Msk                                                                              (0x1UL << AON_REG_PAD_REG24X_PAD_P6_STS_7_Pos)
+
+#define AON_REG_PAD_REG24X_RESERVED_Pos                                                                                  29U
+#define AON_REG_PAD_REG24X_RESERVED_Msk                                                                                  (0x7UL << AON_REG_PAD_REG24X_RESERVED_Pos)
+
+/* 0x184    0x4000_0184
+    21:0    R/W     RESERVED_6                                                  22'b0
+    22      R/W     RESERVED_5                                                  1'b1
+    23      R/W     RESERVED_4                                                  1'b1
+    24      R/W     RESERVED_3                                                  1'b1
+    25      R/W     RESERVED_2                                                  1'b1
+    26      R/W     RESERVED_1                                                  1'b1
+    27      W1C     PAD_P7_STS_0                                                1'b1
+    28      W1C     PAD_P7_STS_1                                                1'b1
+    29      R       RESERVED                                                    1'b0
+    30      W1C     PAD_MICBIAS_STS                                             1'b1
+    31      R/W     PAD_MICBIAS_CFG                                             1'b0
+ */
+typedef union _AON_REG_PAD_REG25X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED_6: 22;
+        uint32_t RESERVED_5: 1;
+        uint32_t RESERVED_4: 1;
+        uint32_t RESERVED_3: 1;
+        uint32_t RESERVED_2: 1;
+        uint32_t RESERVED_1: 1;
+        uint32_t PAD_P7_STS_0: 1;
+        uint32_t PAD_P7_STS_1: 1;
+        uint32_t RESERVED: 1;
+        uint32_t PAD_MICBIAS_STS: 1;
+        uint32_t PAD_MICBIAS_CFG: 1;
+    };
+} AON_REG_PAD_REG25X_TYPE;
+
+/*0x4000_0184 AON_REG_PAD_REG25X*/
+#define AON_REG_PAD_REG25X_RESERVED_6_Pos                                                                                0U
+#define AON_REG_PAD_REG25X_RESERVED_6_Msk                                                                                (0x3FFFFFUL << AON_REG_PAD_REG25X_RESERVED_6_Pos)
+
+#define AON_REG_PAD_REG25X_RESERVED_5_Pos                                                                                22U
+#define AON_REG_PAD_REG25X_RESERVED_5_Msk                                                                                (0x1UL << AON_REG_PAD_REG25X_RESERVED_5_Pos)
+
+#define AON_REG_PAD_REG25X_RESERVED_4_Pos                                                                                23U
+#define AON_REG_PAD_REG25X_RESERVED_4_Msk                                                                                (0x1UL << AON_REG_PAD_REG25X_RESERVED_4_Pos)
+
+#define AON_REG_PAD_REG25X_RESERVED_3_Pos                                                                                24U
+#define AON_REG_PAD_REG25X_RESERVED_3_Msk                                                                                (0x1UL << AON_REG_PAD_REG25X_RESERVED_3_Pos)
+
+#define AON_REG_PAD_REG25X_RESERVED_2_Pos                                                                                25U
+#define AON_REG_PAD_REG25X_RESERVED_2_Msk                                                                                (0x1UL << AON_REG_PAD_REG25X_RESERVED_2_Pos)
+
+#define AON_REG_PAD_REG25X_RESERVED_1_Pos                                                                                26U
+#define AON_REG_PAD_REG25X_RESERVED_1_Msk                                                                                (0x1UL << AON_REG_PAD_REG25X_RESERVED_1_Pos)
+
+#define AON_REG_PAD_REG25X_PAD_P7_STS_0_Pos                                                                              27U
+#define AON_REG_PAD_REG25X_PAD_P7_STS_0_Msk                                                                              (0x1UL << AON_REG_PAD_REG25X_PAD_P7_STS_0_Pos)
+
+#define AON_REG_PAD_REG25X_PAD_P7_STS_1_Pos                                                                              28U
+#define AON_REG_PAD_REG25X_PAD_P7_STS_1_Msk                                                                              (0x1UL << AON_REG_PAD_REG25X_PAD_P7_STS_1_Pos)
+
+#define AON_REG_PAD_REG25X_RESERVED_Pos                                                                                  29U
+#define AON_REG_PAD_REG25X_RESERVED_Msk                                                                                  (0x1UL << AON_REG_PAD_REG25X_RESERVED_Pos)
+
+#define AON_REG_PAD_REG25X_PAD_MICBIAS_STS_Pos                                                                           30U
+#define AON_REG_PAD_REG25X_PAD_MICBIAS_STS_Msk                                                                           (0x1UL << AON_REG_PAD_REG25X_PAD_MICBIAS_STS_Pos)
+
+#define AON_REG_PAD_REG25X_PAD_MICBIAS_CFG_Pos                                                                           31U
+#define AON_REG_PAD_REG25X_PAD_MICBIAS_CFG_Msk                                                                           (0x1UL << AON_REG_PAD_REG25X_PAD_MICBIAS_CFG_Pos)
+
+/* 0x188    0x4000_0188
+    19:0    R/W     RESERVED_3                                                  20'h0
+    20      R/W     RESERVED_2                                                  1'b1
+    21      R/W     RESERVED_1                                                  1'b1
+    22      R/W     RESERVED                                                    1'b1
+    23      R/W     RIGHT_PAD_SMT                                               1'b0
+    24      R/W     RIGHT_PAD_H3L1                                              1'b0
+    25      R/W     RIGHT_PAD_E2                                                1'b1
+    26      R/W     BOTTOM_PAD_SMT                                              1'b0
+    27      R/W     BOTTOM_PAD_H3L1                                             1'b0
+    28      R/W     BOTTOM_PAD_E2                                               1'b1
+    29      R/W     LEFT_PAD_SMT                                                1'b0
+    30      R/W     LEFT_PAD_H3L1                                               1'b0
+    31      R/W     LEFT_PAD_E2                                                 1'b1
+ */
+typedef union _AON_REG_PAD_REG26X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED_3: 20;
+        uint32_t RESERVED_2: 1;
+        uint32_t RESERVED_1: 1;
+        uint32_t RESERVED: 1;
+        uint32_t RIGHT_PAD_SMT: 1;
+        uint32_t RIGHT_PAD_H3L1: 1;
+        uint32_t RIGHT_PAD_E2: 1;
+        uint32_t BOTTOM_PAD_SMT: 1;
+        uint32_t BOTTOM_PAD_H3L1: 1;
+        uint32_t BOTTOM_PAD_E2: 1;
+        uint32_t LEFT_PAD_SMT: 1;
+        uint32_t LEFT_PAD_H3L1: 1;
+        uint32_t LEFT_PAD_E2: 1;
+    };
+} AON_REG_PAD_REG26X_TYPE;
+
+/*0x4000_0188 AON_REG_PAD_REG26X*/
+#define AON_REG_PAD_REG26X_RESERVED_3_Pos                                                                                0U
+#define AON_REG_PAD_REG26X_RESERVED_3_Msk                                                                                (0xFFFFFUL << AON_REG_PAD_REG26X_RESERVED_3_Pos)
+
+#define AON_REG_PAD_REG26X_RESERVED_2_Pos                                                                                20U
+#define AON_REG_PAD_REG26X_RESERVED_2_Msk                                                                                (0x1UL << AON_REG_PAD_REG26X_RESERVED_2_Pos)
+
+#define AON_REG_PAD_REG26X_RESERVED_1_Pos                                                                                21U
+#define AON_REG_PAD_REG26X_RESERVED_1_Msk                                                                                (0x1UL << AON_REG_PAD_REG26X_RESERVED_1_Pos)
+
+#define AON_REG_PAD_REG26X_RESERVED_Pos                                                                                  22U
+#define AON_REG_PAD_REG26X_RESERVED_Msk                                                                                  (0x1UL << AON_REG_PAD_REG26X_RESERVED_Pos)
+
+#define AON_REG_PAD_REG26X_RIGHT_PAD_SMT_Pos                                                                             23U
+#define AON_REG_PAD_REG26X_RIGHT_PAD_SMT_Msk                                                                             (0x1UL << AON_REG_PAD_REG26X_RIGHT_PAD_SMT_Pos)
+
+#define AON_REG_PAD_REG26X_RIGHT_PAD_H3L1_Pos                                                                            24U
+#define AON_REG_PAD_REG26X_RIGHT_PAD_H3L1_Msk                                                                            (0x1UL << AON_REG_PAD_REG26X_RIGHT_PAD_H3L1_Pos)
+
+#define AON_REG_PAD_REG26X_RIGHT_PAD_E2_Pos                                                                              25U
+#define AON_REG_PAD_REG26X_RIGHT_PAD_E2_Msk                                                                              (0x1UL << AON_REG_PAD_REG26X_RIGHT_PAD_E2_Pos)
+
+#define AON_REG_PAD_REG26X_BOTTOM_PAD_SMT_Pos                                                                            26U
+#define AON_REG_PAD_REG26X_BOTTOM_PAD_SMT_Msk                                                                            (0x1UL << AON_REG_PAD_REG26X_BOTTOM_PAD_SMT_Pos)
+
+#define AON_REG_PAD_REG26X_BOTTOM_PAD_H3L1_Pos                                                                           27U
+#define AON_REG_PAD_REG26X_BOTTOM_PAD_H3L1_Msk                                                                           (0x1UL << AON_REG_PAD_REG26X_BOTTOM_PAD_H3L1_Pos)
+
+#define AON_REG_PAD_REG26X_BOTTOM_PAD_E2_Pos                                                                             28U
+#define AON_REG_PAD_REG26X_BOTTOM_PAD_E2_Msk                                                                             (0x1UL << AON_REG_PAD_REG26X_BOTTOM_PAD_E2_Pos)
+
+#define AON_REG_PAD_REG26X_LEFT_PAD_SMT_Pos                                                                              29U
+#define AON_REG_PAD_REG26X_LEFT_PAD_SMT_Msk                                                                              (0x1UL << AON_REG_PAD_REG26X_LEFT_PAD_SMT_Pos)
+
+#define AON_REG_PAD_REG26X_LEFT_PAD_H3L1_Pos                                                                             30U
+#define AON_REG_PAD_REG26X_LEFT_PAD_H3L1_Msk                                                                             (0x1UL << AON_REG_PAD_REG26X_LEFT_PAD_H3L1_Pos)
+
+#define AON_REG_PAD_REG26X_LEFT_PAD_E2_Pos                                                                               31U
+#define AON_REG_PAD_REG26X_LEFT_PAD_E2_Msk                                                                               (0x1UL << AON_REG_PAD_REG26X_LEFT_PAD_E2_Pos)
+
+/* 0x18C    0x4000_018c
+    0       R/W     PAD_SPIC_SCK_O                                              1'b0
+    1       R/W     PAD_SPIC_SCK_E                                              1'b0
+    2       R/W     PAD_SPIC_SCK_PU_EN                                          1'b1
+    3       R/W     AON_PAD_SPIC_SCK_PD                                         1'b0
+    4       R/W     PAD_SPIC_SCK_PUPDC                                          1'b0
+    5       R/W     PAD_SPIC_SCK_WKEN                                           1'b0
+    6       R/W     PAD_SPIC_SCK_WKPOL                                          1'b0
+    7       R/W     PAD_SPIC_SCK_SHDN                                           1'b1
+    8       R/W     PAD_SPIC_SCK_DEB                                            1'b0
+    9       R/W     PAD_SPIC_SCK_RAP_WKEN                                       1'b0
+    10      R/W     PAD_SPIC_SCK_PPU_WKEN                                       1'b0
+    11      R/W     RESERVED_3                                                  1'b0
+    13:12   R       RESERVED_2                                                  2'b00
+    15:14   R/W     PAD_SPIC_SCK_AON_MUX                                        2'b00
+    16      R/W     PAD_SPIC_CSN_O                                              1'b0
+    17      R/W     PAD_SPIC_CSN_E                                              1'b0
+    18      R/W     PAD_SPIC_CSN_PU_EN                                          1'b1
+    19      R/W     AON_PAD_SPIC_CSN_PD                                         1'b0
+    20      R/W     PAD_SPIC_CSN_PUPDC                                          1'b0
+    21      R/W     PAD_SPIC_CSN_WKEN                                           1'b0
+    22      R/W     PAD_SPIC_CSN_WKPOL                                          1'b0
+    23      R/W     PAD_SPIC_CSN_SHDN                                           1'b1
+    24      R/W     PAD_SPIC_CSN_DEB                                            1'b0
+    25      R/W     PAD_SPIC_CSN_RAP_WKEN                                       1'b0
+    26      R/W     PAD_SPIC_CSN_PPU_WKEN                                       1'b0
+    27      R/W     RESERVED_1                                                  1'b0
+    29:28   R       RESERVED                                                    2'b00
+    31:30   R/W     PAD_SPIC_CSN_AON_MUX                                        2'b00
+ */
+typedef union _AON_REG_PAD_REG27X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t PAD_SPIC_SCK_O: 1;
+        uint32_t PAD_SPIC_SCK_E: 1;
+        uint32_t PAD_SPIC_SCK_PU_EN: 1;
+        uint32_t AON_PAD_SPIC_SCK_PD: 1;
+        uint32_t PAD_SPIC_SCK_PUPDC: 1;
+        uint32_t PAD_SPIC_SCK_WKEN: 1;
+        uint32_t PAD_SPIC_SCK_WKPOL: 1;
+        uint32_t PAD_SPIC_SCK_SHDN: 1;
+        uint32_t PAD_SPIC_SCK_DEB: 1;
+        uint32_t PAD_SPIC_SCK_RAP_WKEN: 1;
+        uint32_t PAD_SPIC_SCK_PPU_WKEN: 1;
+        uint32_t RESERVED_3: 1;
+        uint32_t RESERVED_2: 2;
+        uint32_t PAD_SPIC_SCK_AON_MUX: 2;
+        uint32_t PAD_SPIC_CSN_O: 1;
+        uint32_t PAD_SPIC_CSN_E: 1;
+        uint32_t PAD_SPIC_CSN_PU_EN: 1;
+        uint32_t AON_PAD_SPIC_CSN_PD: 1;
+        uint32_t PAD_SPIC_CSN_PUPDC: 1;
+        uint32_t PAD_SPIC_CSN_WKEN: 1;
+        uint32_t PAD_SPIC_CSN_WKPOL: 1;
+        uint32_t PAD_SPIC_CSN_SHDN: 1;
+        uint32_t PAD_SPIC_CSN_DEB: 1;
+        uint32_t PAD_SPIC_CSN_RAP_WKEN: 1;
+        uint32_t PAD_SPIC_CSN_PPU_WKEN: 1;
+        uint32_t RESERVED_1: 1;
+        uint32_t RESERVED: 2;
+        uint32_t PAD_SPIC_CSN_AON_MUX: 2;
+    };
+} AON_REG_PAD_REG27X_TYPE;
+
+/*0x4000_018c AON_REG_PAD_REG27X*/
+#define AON_REG_PAD_REG27X_PAD_SPIC_SCK_O_Pos                                                                            0U
+#define AON_REG_PAD_REG27X_PAD_SPIC_SCK_O_Msk                                                                            (0x1UL << AON_REG_PAD_REG27X_PAD_SPIC_SCK_O_Pos)
+
+#define AON_REG_PAD_REG27X_PAD_SPIC_SCK_E_Pos                                                                            1U
+#define AON_REG_PAD_REG27X_PAD_SPIC_SCK_E_Msk                                                                            (0x1UL << AON_REG_PAD_REG27X_PAD_SPIC_SCK_E_Pos)
+
+#define AON_REG_PAD_REG27X_PAD_SPIC_SCK_PU_EN_Pos                                                                        2U
+#define AON_REG_PAD_REG27X_PAD_SPIC_SCK_PU_EN_Msk                                                                        (0x1UL << AON_REG_PAD_REG27X_PAD_SPIC_SCK_PU_EN_Pos)
+
+#define AON_REG_PAD_REG27X_AON_PAD_SPIC_SCK_PD_Pos                                                                       3U
+#define AON_REG_PAD_REG27X_AON_PAD_SPIC_SCK_PD_Msk                                                                       (0x1UL << AON_REG_PAD_REG27X_AON_PAD_SPIC_SCK_PD_Pos)
+
+#define AON_REG_PAD_REG27X_PAD_SPIC_SCK_PUPDC_Pos                                                                        4U
+#define AON_REG_PAD_REG27X_PAD_SPIC_SCK_PUPDC_Msk                                                                        (0x1UL << AON_REG_PAD_REG27X_PAD_SPIC_SCK_PUPDC_Pos)
+
+#define AON_REG_PAD_REG27X_PAD_SPIC_SCK_WKEN_Pos                                                                         5U
+#define AON_REG_PAD_REG27X_PAD_SPIC_SCK_WKEN_Msk                                                                         (0x1UL << AON_REG_PAD_REG27X_PAD_SPIC_SCK_WKEN_Pos)
+
+#define AON_REG_PAD_REG27X_PAD_SPIC_SCK_WKPOL_Pos                                                                        6U
+#define AON_REG_PAD_REG27X_PAD_SPIC_SCK_WKPOL_Msk                                                                        (0x1UL << AON_REG_PAD_REG27X_PAD_SPIC_SCK_WKPOL_Pos)
+
+#define AON_REG_PAD_REG27X_PAD_SPIC_SCK_SHDN_Pos                                                                         7U
+#define AON_REG_PAD_REG27X_PAD_SPIC_SCK_SHDN_Msk                                                                         (0x1UL << AON_REG_PAD_REG27X_PAD_SPIC_SCK_SHDN_Pos)
+
+#define AON_REG_PAD_REG27X_PAD_SPIC_SCK_DEB_Pos                                                                          8U
+#define AON_REG_PAD_REG27X_PAD_SPIC_SCK_DEB_Msk                                                                          (0x1UL << AON_REG_PAD_REG27X_PAD_SPIC_SCK_DEB_Pos)
+
+#define AON_REG_PAD_REG27X_PAD_SPIC_SCK_RAP_WKEN_Pos                                                                     9U
+#define AON_REG_PAD_REG27X_PAD_SPIC_SCK_RAP_WKEN_Msk                                                                     (0x1UL << AON_REG_PAD_REG27X_PAD_SPIC_SCK_RAP_WKEN_Pos)
+
+#define AON_REG_PAD_REG27X_PAD_SPIC_SCK_PPU_WKEN_Pos                                                                     10U
+#define AON_REG_PAD_REG27X_PAD_SPIC_SCK_PPU_WKEN_Msk                                                                     (0x1UL << AON_REG_PAD_REG27X_PAD_SPIC_SCK_PPU_WKEN_Pos)
+
+#define AON_REG_PAD_REG27X_RESERVED_3_Pos                                                                                11U
+#define AON_REG_PAD_REG27X_RESERVED_3_Msk                                                                                (0x1UL << AON_REG_PAD_REG27X_RESERVED_3_Pos)
+
+#define AON_REG_PAD_REG27X_RESERVED_2_Pos                                                                                12U
+#define AON_REG_PAD_REG27X_RESERVED_2_Msk                                                                                (0x3UL << AON_REG_PAD_REG27X_RESERVED_2_Pos)
+
+#define AON_REG_PAD_REG27X_PAD_SPIC_SCK_AON_MUX_Pos                                                                      14U
+#define AON_REG_PAD_REG27X_PAD_SPIC_SCK_AON_MUX_Msk                                                                      (0x3UL << AON_REG_PAD_REG27X_PAD_SPIC_SCK_AON_MUX_Pos)
+
+#define AON_REG_PAD_REG27X_PAD_SPIC_CSN_O_Pos                                                                            16U
+#define AON_REG_PAD_REG27X_PAD_SPIC_CSN_O_Msk                                                                            (0x1UL << AON_REG_PAD_REG27X_PAD_SPIC_CSN_O_Pos)
+
+#define AON_REG_PAD_REG27X_PAD_SPIC_CSN_E_Pos                                                                            17U
+#define AON_REG_PAD_REG27X_PAD_SPIC_CSN_E_Msk                                                                            (0x1UL << AON_REG_PAD_REG27X_PAD_SPIC_CSN_E_Pos)
+
+#define AON_REG_PAD_REG27X_PAD_SPIC_CSN_PU_EN_Pos                                                                        18U
+#define AON_REG_PAD_REG27X_PAD_SPIC_CSN_PU_EN_Msk                                                                        (0x1UL << AON_REG_PAD_REG27X_PAD_SPIC_CSN_PU_EN_Pos)
+
+#define AON_REG_PAD_REG27X_AON_PAD_SPIC_CSN_PD_Pos                                                                       19U
+#define AON_REG_PAD_REG27X_AON_PAD_SPIC_CSN_PD_Msk                                                                       (0x1UL << AON_REG_PAD_REG27X_AON_PAD_SPIC_CSN_PD_Pos)
+
+#define AON_REG_PAD_REG27X_PAD_SPIC_CSN_PUPDC_Pos                                                                        20U
+#define AON_REG_PAD_REG27X_PAD_SPIC_CSN_PUPDC_Msk                                                                        (0x1UL << AON_REG_PAD_REG27X_PAD_SPIC_CSN_PUPDC_Pos)
+
+#define AON_REG_PAD_REG27X_PAD_SPIC_CSN_WKEN_Pos                                                                         21U
+#define AON_REG_PAD_REG27X_PAD_SPIC_CSN_WKEN_Msk                                                                         (0x1UL << AON_REG_PAD_REG27X_PAD_SPIC_CSN_WKEN_Pos)
+
+#define AON_REG_PAD_REG27X_PAD_SPIC_CSN_WKPOL_Pos                                                                        22U
+#define AON_REG_PAD_REG27X_PAD_SPIC_CSN_WKPOL_Msk                                                                        (0x1UL << AON_REG_PAD_REG27X_PAD_SPIC_CSN_WKPOL_Pos)
+
+#define AON_REG_PAD_REG27X_PAD_SPIC_CSN_SHDN_Pos                                                                         23U
+#define AON_REG_PAD_REG27X_PAD_SPIC_CSN_SHDN_Msk                                                                         (0x1UL << AON_REG_PAD_REG27X_PAD_SPIC_CSN_SHDN_Pos)
+
+#define AON_REG_PAD_REG27X_PAD_SPIC_CSN_DEB_Pos                                                                          24U
+#define AON_REG_PAD_REG27X_PAD_SPIC_CSN_DEB_Msk                                                                          (0x1UL << AON_REG_PAD_REG27X_PAD_SPIC_CSN_DEB_Pos)
+
+#define AON_REG_PAD_REG27X_PAD_SPIC_CSN_RAP_WKEN_Pos                                                                     25U
+#define AON_REG_PAD_REG27X_PAD_SPIC_CSN_RAP_WKEN_Msk                                                                     (0x1UL << AON_REG_PAD_REG27X_PAD_SPIC_CSN_RAP_WKEN_Pos)
+
+#define AON_REG_PAD_REG27X_PAD_SPIC_CSN_PPU_WKEN_Pos                                                                     26U
+#define AON_REG_PAD_REG27X_PAD_SPIC_CSN_PPU_WKEN_Msk                                                                     (0x1UL << AON_REG_PAD_REG27X_PAD_SPIC_CSN_PPU_WKEN_Pos)
+
+#define AON_REG_PAD_REG27X_RESERVED_1_Pos                                                                                27U
+#define AON_REG_PAD_REG27X_RESERVED_1_Msk                                                                                (0x1UL << AON_REG_PAD_REG27X_RESERVED_1_Pos)
+
+#define AON_REG_PAD_REG27X_RESERVED_Pos                                                                                  28U
+#define AON_REG_PAD_REG27X_RESERVED_Msk                                                                                  (0x3UL << AON_REG_PAD_REG27X_RESERVED_Pos)
+
+#define AON_REG_PAD_REG27X_PAD_SPIC_CSN_AON_MUX_Pos                                                                      30U
+#define AON_REG_PAD_REG27X_PAD_SPIC_CSN_AON_MUX_Msk                                                                      (0x3UL << AON_REG_PAD_REG27X_PAD_SPIC_CSN_AON_MUX_Pos)
+
+/* 0x190    0x4000_0190
+    0       R/W     PAD_SPIC_SO_O                                               1'b0
+    1       R/W     PAD_SPIC_SO_E                                               1'b0
+    2       R/W     PAD_SPIC_SO_PU_EN                                           1'b1
+    3       R/W     AON_PAD_SPIC_SO_PD                                          1'b1
+    4       R/W     PAD_SPIC_SO_PUPDC                                           1'b0
+    5       R/W     PAD_SPIC_SO_WKEN                                            1'b0
+    6       R/W     PAD_SPIC_SO_WKPOL                                           1'b0
+    7       R/W     PAD_SPIC_SO_SHDN                                            1'b1
+    8       R/W     PAD_SPIC_SO_DEB                                             1'b0
+    9       R/W     PAD_SPIC_SO_RAP_WKEN                                        1'b0
+    10      R/W     PAD_SPIC_SO_PPU_WKEN                                        1'b0
+    11      R/W     RESERVED_3                                                  1'b0
+    13:12   R       RESERVED_2                                                  2'b00
+    15:14   R/W     PAD_SPIC_SO_AON_MUX                                         2'b00
+    16      R/W     PAD_SPIC_SI_O                                               1'b0
+    17      R/W     PAD_SPIC_SI_E                                               1'b0
+    18      R/W     PAD_SPIC_SI_PU_EN                                           1'b1
+    19      R/W     AON_PAD_SPIC_SI_PD                                          1'b1
+    20      R/W     PAD_SPIC_SI_PUPDC                                           1'b0
+    21      R/W     PAD_SPIC_SI_WKEN                                            1'b0
+    22      R/W     PAD_SPIC_SI_WKPOL                                           1'b0
+    23      R/W     PAD_SPIC_SI_SHDN                                            1'b1
+    24      R/W     PAD_SPIC_SI_DEB                                             1'b0
+    25      R/W     PAD_SPIC_SI_RAP_WKEN                                        1'b0
+    26      R/W     PAD_SPIC_SI_PPU_WKEN                                        1'b0
+    27      R/W     RESERVED_1                                                  1'b0
+    29:28   R       RESERVED                                                    2'b00
+    31:30   R/W     PAD_SPIC_SI_AON_MUX                                         2'b00
+ */
+typedef union _AON_REG_PAD_REG28X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t PAD_SPIC_SO_O: 1;
+        uint32_t PAD_SPIC_SO_E: 1;
+        uint32_t PAD_SPIC_SO_PU_EN: 1;
+        uint32_t AON_PAD_SPIC_SO_PD: 1;
+        uint32_t PAD_SPIC_SO_PUPDC: 1;
+        uint32_t PAD_SPIC_SO_WKEN: 1;
+        uint32_t PAD_SPIC_SO_WKPOL: 1;
+        uint32_t PAD_SPIC_SO_SHDN: 1;
+        uint32_t PAD_SPIC_SO_DEB: 1;
+        uint32_t PAD_SPIC_SO_RAP_WKEN: 1;
+        uint32_t PAD_SPIC_SO_PPU_WKEN: 1;
+        uint32_t RESERVED_3: 1;
+        uint32_t RESERVED_2: 2;
+        uint32_t PAD_SPIC_SO_AON_MUX: 2;
+        uint32_t PAD_SPIC_SI_O: 1;
+        uint32_t PAD_SPIC_SI_E: 1;
+        uint32_t PAD_SPIC_SI_PU_EN: 1;
+        uint32_t AON_PAD_SPIC_SI_PD: 1;
+        uint32_t PAD_SPIC_SI_PUPDC: 1;
+        uint32_t PAD_SPIC_SI_WKEN: 1;
+        uint32_t PAD_SPIC_SI_WKPOL: 1;
+        uint32_t PAD_SPIC_SI_SHDN: 1;
+        uint32_t PAD_SPIC_SI_DEB: 1;
+        uint32_t PAD_SPIC_SI_RAP_WKEN: 1;
+        uint32_t PAD_SPIC_SI_PPU_WKEN: 1;
+        uint32_t RESERVED_1: 1;
+        uint32_t RESERVED: 2;
+        uint32_t PAD_SPIC_SI_AON_MUX: 2;
+    };
+} AON_REG_PAD_REG28X_TYPE;
+
+/*0x4000_0190 AON_REG_PAD_REG28X*/
+#define AON_REG_PAD_REG28X_PAD_SPIC_SO_O_Pos                                                                             0U
+#define AON_REG_PAD_REG28X_PAD_SPIC_SO_O_Msk                                                                             (0x1UL << AON_REG_PAD_REG28X_PAD_SPIC_SO_O_Pos)
+
+#define AON_REG_PAD_REG28X_PAD_SPIC_SO_E_Pos                                                                             1U
+#define AON_REG_PAD_REG28X_PAD_SPIC_SO_E_Msk                                                                             (0x1UL << AON_REG_PAD_REG28X_PAD_SPIC_SO_E_Pos)
+
+#define AON_REG_PAD_REG28X_PAD_SPIC_SO_PU_EN_Pos                                                                         2U
+#define AON_REG_PAD_REG28X_PAD_SPIC_SO_PU_EN_Msk                                                                         (0x1UL << AON_REG_PAD_REG28X_PAD_SPIC_SO_PU_EN_Pos)
+
+#define AON_REG_PAD_REG28X_AON_PAD_SPIC_SO_PD_Pos                                                                        3U
+#define AON_REG_PAD_REG28X_AON_PAD_SPIC_SO_PD_Msk                                                                        (0x1UL << AON_REG_PAD_REG28X_AON_PAD_SPIC_SO_PD_Pos)
+
+#define AON_REG_PAD_REG28X_PAD_SPIC_SO_PUPDC_Pos                                                                         4U
+#define AON_REG_PAD_REG28X_PAD_SPIC_SO_PUPDC_Msk                                                                         (0x1UL << AON_REG_PAD_REG28X_PAD_SPIC_SO_PUPDC_Pos)
+
+#define AON_REG_PAD_REG28X_PAD_SPIC_SO_WKEN_Pos                                                                          5U
+#define AON_REG_PAD_REG28X_PAD_SPIC_SO_WKEN_Msk                                                                          (0x1UL << AON_REG_PAD_REG28X_PAD_SPIC_SO_WKEN_Pos)
+
+#define AON_REG_PAD_REG28X_PAD_SPIC_SO_WKPOL_Pos                                                                         6U
+#define AON_REG_PAD_REG28X_PAD_SPIC_SO_WKPOL_Msk                                                                         (0x1UL << AON_REG_PAD_REG28X_PAD_SPIC_SO_WKPOL_Pos)
+
+#define AON_REG_PAD_REG28X_PAD_SPIC_SO_SHDN_Pos                                                                          7U
+#define AON_REG_PAD_REG28X_PAD_SPIC_SO_SHDN_Msk                                                                          (0x1UL << AON_REG_PAD_REG28X_PAD_SPIC_SO_SHDN_Pos)
+
+#define AON_REG_PAD_REG28X_PAD_SPIC_SO_DEB_Pos                                                                           8U
+#define AON_REG_PAD_REG28X_PAD_SPIC_SO_DEB_Msk                                                                           (0x1UL << AON_REG_PAD_REG28X_PAD_SPIC_SO_DEB_Pos)
+
+#define AON_REG_PAD_REG28X_PAD_SPIC_SO_RAP_WKEN_Pos                                                                      9U
+#define AON_REG_PAD_REG28X_PAD_SPIC_SO_RAP_WKEN_Msk                                                                      (0x1UL << AON_REG_PAD_REG28X_PAD_SPIC_SO_RAP_WKEN_Pos)
+
+#define AON_REG_PAD_REG28X_PAD_SPIC_SO_PPU_WKEN_Pos                                                                      10U
+#define AON_REG_PAD_REG28X_PAD_SPIC_SO_PPU_WKEN_Msk                                                                      (0x1UL << AON_REG_PAD_REG28X_PAD_SPIC_SO_PPU_WKEN_Pos)
+
+#define AON_REG_PAD_REG28X_RESERVED_3_Pos                                                                                11U
+#define AON_REG_PAD_REG28X_RESERVED_3_Msk                                                                                (0x1UL << AON_REG_PAD_REG28X_RESERVED_3_Pos)
+
+#define AON_REG_PAD_REG28X_RESERVED_2_Pos                                                                                12U
+#define AON_REG_PAD_REG28X_RESERVED_2_Msk                                                                                (0x3UL << AON_REG_PAD_REG28X_RESERVED_2_Pos)
+
+#define AON_REG_PAD_REG28X_PAD_SPIC_SO_AON_MUX_Pos                                                                       14U
+#define AON_REG_PAD_REG28X_PAD_SPIC_SO_AON_MUX_Msk                                                                       (0x3UL << AON_REG_PAD_REG28X_PAD_SPIC_SO_AON_MUX_Pos)
+
+#define AON_REG_PAD_REG28X_PAD_SPIC_SI_O_Pos                                                                             16U
+#define AON_REG_PAD_REG28X_PAD_SPIC_SI_O_Msk                                                                             (0x1UL << AON_REG_PAD_REG28X_PAD_SPIC_SI_O_Pos)
+
+#define AON_REG_PAD_REG28X_PAD_SPIC_SI_E_Pos                                                                             17U
+#define AON_REG_PAD_REG28X_PAD_SPIC_SI_E_Msk                                                                             (0x1UL << AON_REG_PAD_REG28X_PAD_SPIC_SI_E_Pos)
+
+#define AON_REG_PAD_REG28X_PAD_SPIC_SI_PU_EN_Pos                                                                         18U
+#define AON_REG_PAD_REG28X_PAD_SPIC_SI_PU_EN_Msk                                                                         (0x1UL << AON_REG_PAD_REG28X_PAD_SPIC_SI_PU_EN_Pos)
+
+#define AON_REG_PAD_REG28X_AON_PAD_SPIC_SI_PD_Pos                                                                        19U
+#define AON_REG_PAD_REG28X_AON_PAD_SPIC_SI_PD_Msk                                                                        (0x1UL << AON_REG_PAD_REG28X_AON_PAD_SPIC_SI_PD_Pos)
+
+#define AON_REG_PAD_REG28X_PAD_SPIC_SI_PUPDC_Pos                                                                         20U
+#define AON_REG_PAD_REG28X_PAD_SPIC_SI_PUPDC_Msk                                                                         (0x1UL << AON_REG_PAD_REG28X_PAD_SPIC_SI_PUPDC_Pos)
+
+#define AON_REG_PAD_REG28X_PAD_SPIC_SI_WKEN_Pos                                                                          21U
+#define AON_REG_PAD_REG28X_PAD_SPIC_SI_WKEN_Msk                                                                          (0x1UL << AON_REG_PAD_REG28X_PAD_SPIC_SI_WKEN_Pos)
+
+#define AON_REG_PAD_REG28X_PAD_SPIC_SI_WKPOL_Pos                                                                         22U
+#define AON_REG_PAD_REG28X_PAD_SPIC_SI_WKPOL_Msk                                                                         (0x1UL << AON_REG_PAD_REG28X_PAD_SPIC_SI_WKPOL_Pos)
+
+#define AON_REG_PAD_REG28X_PAD_SPIC_SI_SHDN_Pos                                                                          23U
+#define AON_REG_PAD_REG28X_PAD_SPIC_SI_SHDN_Msk                                                                          (0x1UL << AON_REG_PAD_REG28X_PAD_SPIC_SI_SHDN_Pos)
+
+#define AON_REG_PAD_REG28X_PAD_SPIC_SI_DEB_Pos                                                                           24U
+#define AON_REG_PAD_REG28X_PAD_SPIC_SI_DEB_Msk                                                                           (0x1UL << AON_REG_PAD_REG28X_PAD_SPIC_SI_DEB_Pos)
+
+#define AON_REG_PAD_REG28X_PAD_SPIC_SI_RAP_WKEN_Pos                                                                      25U
+#define AON_REG_PAD_REG28X_PAD_SPIC_SI_RAP_WKEN_Msk                                                                      (0x1UL << AON_REG_PAD_REG28X_PAD_SPIC_SI_RAP_WKEN_Pos)
+
+#define AON_REG_PAD_REG28X_PAD_SPIC_SI_PPU_WKEN_Pos                                                                      26U
+#define AON_REG_PAD_REG28X_PAD_SPIC_SI_PPU_WKEN_Msk                                                                      (0x1UL << AON_REG_PAD_REG28X_PAD_SPIC_SI_PPU_WKEN_Pos)
+
+#define AON_REG_PAD_REG28X_RESERVED_1_Pos                                                                                27U
+#define AON_REG_PAD_REG28X_RESERVED_1_Msk                                                                                (0x1UL << AON_REG_PAD_REG28X_RESERVED_1_Pos)
+
+#define AON_REG_PAD_REG28X_RESERVED_Pos                                                                                  28U
+#define AON_REG_PAD_REG28X_RESERVED_Msk                                                                                  (0x3UL << AON_REG_PAD_REG28X_RESERVED_Pos)
+
+#define AON_REG_PAD_REG28X_PAD_SPIC_SI_AON_MUX_Pos                                                                       30U
+#define AON_REG_PAD_REG28X_PAD_SPIC_SI_AON_MUX_Msk                                                                       (0x3UL << AON_REG_PAD_REG28X_PAD_SPIC_SI_AON_MUX_Pos)
+
+/* 0x194    0x4000_0194
+    0       R/W     PAD_P1_O_3                                                  1'b0
+    1       R/W     PAD_P1_E_3                                                  1'b0
+    2       R/W     PAD_P1_PU_EN_3                                              1'b1
+    3       R/W     AON_PAD_P1_PD_3                                             1'b1
+    4       R/W     PAD_P1_PUPDC_3                                              1'b0
+    5       R/W     PAD_P1_WKEN_3                                               1'b0
+    6       R/W     PAD_P1_WKPOL_3                                              1'b0
+    7       R/W     PAD_P1_SHDN_3                                               1'b1
+    8       R/W     PAD_P1_DEB_3                                                1'b0
+    9       R/W     PAD_P1_RAP_WKEN_3                                           1'b0
+    10      R/W     PAD_P1_PPU_WKEN_3                                           1'b0
+    11      R/W     RESERVED_3                                                  1'b0
+    13:12   R       RESERVED_2                                                  2'b00
+    15:14   R/W     PAD_P1_AON_MUX_3                                            2'b00
+    16      R/W     PAD_P1_O_4                                                  1'b0
+    17      R/W     PAD_P1_E_4                                                  1'b0
+    18      R/W     PAD_P1_PU_EN_4                                              1'b1
+    19      R/W     AON_PAD_P1_PD_4                                             1'b1
+    20      R/W     PAD_P1_PUPDC_4                                              1'b0
+    21      R/W     PAD_P1_WKEN_4                                               1'b0
+    22      R/W     PAD_P1_WKPOL_4                                              1'b0
+    23      R/W     PAD_P1_SHDN_4                                               1'b1
+    24      R/W     PAD_P1_DEB_4                                                1'b0
+    25      R/W     PAD_P1_RAP_WKEN_4                                           1'b0
+    26      R/W     PAD_P1_PPU_WKEN_4                                           1'b0
+    27      R/W     RESERVED_1                                                  1'b0
+    29:28   R       RESERVED                                                    2'b00
+    31:30   R/W     PAD_P1_AON_MUX_4                                            2'b00
+ */
+typedef union _AON_REG_PAD_REG29X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t PAD_P1_O_3: 1;
+        uint32_t PAD_P1_E_3: 1;
+        uint32_t PAD_P1_PU_EN_3: 1;
+        uint32_t AON_PAD_P1_PD_3: 1;
+        uint32_t PAD_P1_PUPDC_3: 1;
+        uint32_t PAD_P1_WKEN_3: 1;
+        uint32_t PAD_P1_WKPOL_3: 1;
+        uint32_t PAD_P1_SHDN_3: 1;
+        uint32_t PAD_P1_DEB_3: 1;
+        uint32_t PAD_P1_RAP_WKEN_3: 1;
+        uint32_t PAD_P1_PPU_WKEN_3: 1;
+        uint32_t RESERVED_3: 1;
+        uint32_t RESERVED_2: 2;
+        uint32_t PAD_P1_AON_MUX_3: 2;
+        uint32_t PAD_P1_O_4: 1;
+        uint32_t PAD_P1_E_4: 1;
+        uint32_t PAD_P1_PU_EN_4: 1;
+        uint32_t AON_PAD_P1_PD_4: 1;
+        uint32_t PAD_P1_PUPDC_4: 1;
+        uint32_t PAD_P1_WKEN_4: 1;
+        uint32_t PAD_P1_WKPOL_4: 1;
+        uint32_t PAD_P1_SHDN_4: 1;
+        uint32_t PAD_P1_DEB_4: 1;
+        uint32_t PAD_P1_RAP_WKEN_4: 1;
+        uint32_t PAD_P1_PPU_WKEN_4: 1;
+        uint32_t RESERVED_1: 1;
+        uint32_t RESERVED: 2;
+        uint32_t PAD_P1_AON_MUX_4: 2;
+    };
+} AON_REG_PAD_REG29X_TYPE;
+
+/*0x4000_0194 AON_REG_PAD_REG29X*/
+#define AON_REG_PAD_REG29X_PAD_P1_O_3_Pos                                                                                0U
+#define AON_REG_PAD_REG29X_PAD_P1_O_3_Msk                                                                                (0x1UL << AON_REG_PAD_REG29X_PAD_P1_O_3_Pos)
+
+#define AON_REG_PAD_REG29X_PAD_P1_E_3_Pos                                                                                1U
+#define AON_REG_PAD_REG29X_PAD_P1_E_3_Msk                                                                                (0x1UL << AON_REG_PAD_REG29X_PAD_P1_E_3_Pos)
+
+#define AON_REG_PAD_REG29X_PAD_P1_PU_EN_3_Pos                                                                            2U
+#define AON_REG_PAD_REG29X_PAD_P1_PU_EN_3_Msk                                                                            (0x1UL << AON_REG_PAD_REG29X_PAD_P1_PU_EN_3_Pos)
+
+#define AON_REG_PAD_REG29X_AON_PAD_P1_PD_3_Pos                                                                           3U
+#define AON_REG_PAD_REG29X_AON_PAD_P1_PD_3_Msk                                                                           (0x1UL << AON_REG_PAD_REG29X_AON_PAD_P1_PD_3_Pos)
+
+#define AON_REG_PAD_REG29X_PAD_P1_PUPDC_3_Pos                                                                            4U
+#define AON_REG_PAD_REG29X_PAD_P1_PUPDC_3_Msk                                                                            (0x1UL << AON_REG_PAD_REG29X_PAD_P1_PUPDC_3_Pos)
+
+#define AON_REG_PAD_REG29X_PAD_P1_WKEN_3_Pos                                                                             5U
+#define AON_REG_PAD_REG29X_PAD_P1_WKEN_3_Msk                                                                             (0x1UL << AON_REG_PAD_REG29X_PAD_P1_WKEN_3_Pos)
+
+#define AON_REG_PAD_REG29X_PAD_P1_WKPOL_3_Pos                                                                            6U
+#define AON_REG_PAD_REG29X_PAD_P1_WKPOL_3_Msk                                                                            (0x1UL << AON_REG_PAD_REG29X_PAD_P1_WKPOL_3_Pos)
+
+#define AON_REG_PAD_REG29X_PAD_P1_SHDN_3_Pos                                                                             7U
+#define AON_REG_PAD_REG29X_PAD_P1_SHDN_3_Msk                                                                             (0x1UL << AON_REG_PAD_REG29X_PAD_P1_SHDN_3_Pos)
+
+#define AON_REG_PAD_REG29X_PAD_P1_DEB_3_Pos                                                                              8U
+#define AON_REG_PAD_REG29X_PAD_P1_DEB_3_Msk                                                                              (0x1UL << AON_REG_PAD_REG29X_PAD_P1_DEB_3_Pos)
+
+#define AON_REG_PAD_REG29X_PAD_P1_RAP_WKEN_3_Pos                                                                         9U
+#define AON_REG_PAD_REG29X_PAD_P1_RAP_WKEN_3_Msk                                                                         (0x1UL << AON_REG_PAD_REG29X_PAD_P1_RAP_WKEN_3_Pos)
+
+#define AON_REG_PAD_REG29X_PAD_P1_PPU_WKEN_3_Pos                                                                         10U
+#define AON_REG_PAD_REG29X_PAD_P1_PPU_WKEN_3_Msk                                                                         (0x1UL << AON_REG_PAD_REG29X_PAD_P1_PPU_WKEN_3_Pos)
+
+#define AON_REG_PAD_REG29X_RESERVED_3_Pos                                                                                11U
+#define AON_REG_PAD_REG29X_RESERVED_3_Msk                                                                                (0x1UL << AON_REG_PAD_REG29X_RESERVED_3_Pos)
+
+#define AON_REG_PAD_REG29X_RESERVED_2_Pos                                                                                12U
+#define AON_REG_PAD_REG29X_RESERVED_2_Msk                                                                                (0x3UL << AON_REG_PAD_REG29X_RESERVED_2_Pos)
+
+#define AON_REG_PAD_REG29X_PAD_P1_AON_MUX_3_Pos                                                                          14U
+#define AON_REG_PAD_REG29X_PAD_P1_AON_MUX_3_Msk                                                                          (0x3UL << AON_REG_PAD_REG29X_PAD_P1_AON_MUX_3_Pos)
+
+#define AON_REG_PAD_REG29X_PAD_P1_O_4_Pos                                                                                16U
+#define AON_REG_PAD_REG29X_PAD_P1_O_4_Msk                                                                                (0x1UL << AON_REG_PAD_REG29X_PAD_P1_O_4_Pos)
+
+#define AON_REG_PAD_REG29X_PAD_P1_E_4_Pos                                                                                17U
+#define AON_REG_PAD_REG29X_PAD_P1_E_4_Msk                                                                                (0x1UL << AON_REG_PAD_REG29X_PAD_P1_E_4_Pos)
+
+#define AON_REG_PAD_REG29X_PAD_P1_PU_EN_4_Pos                                                                            18U
+#define AON_REG_PAD_REG29X_PAD_P1_PU_EN_4_Msk                                                                            (0x1UL << AON_REG_PAD_REG29X_PAD_P1_PU_EN_4_Pos)
+
+#define AON_REG_PAD_REG29X_AON_PAD_P1_PD_4_Pos                                                                           19U
+#define AON_REG_PAD_REG29X_AON_PAD_P1_PD_4_Msk                                                                           (0x1UL << AON_REG_PAD_REG29X_AON_PAD_P1_PD_4_Pos)
+
+#define AON_REG_PAD_REG29X_PAD_P1_PUPDC_4_Pos                                                                            20U
+#define AON_REG_PAD_REG29X_PAD_P1_PUPDC_4_Msk                                                                            (0x1UL << AON_REG_PAD_REG29X_PAD_P1_PUPDC_4_Pos)
+
+#define AON_REG_PAD_REG29X_PAD_P1_WKEN_4_Pos                                                                             21U
+#define AON_REG_PAD_REG29X_PAD_P1_WKEN_4_Msk                                                                             (0x1UL << AON_REG_PAD_REG29X_PAD_P1_WKEN_4_Pos)
+
+#define AON_REG_PAD_REG29X_PAD_P1_WKPOL_4_Pos                                                                            22U
+#define AON_REG_PAD_REG29X_PAD_P1_WKPOL_4_Msk                                                                            (0x1UL << AON_REG_PAD_REG29X_PAD_P1_WKPOL_4_Pos)
+
+#define AON_REG_PAD_REG29X_PAD_P1_SHDN_4_Pos                                                                             23U
+#define AON_REG_PAD_REG29X_PAD_P1_SHDN_4_Msk                                                                             (0x1UL << AON_REG_PAD_REG29X_PAD_P1_SHDN_4_Pos)
+
+#define AON_REG_PAD_REG29X_PAD_P1_DEB_4_Pos                                                                              24U
+#define AON_REG_PAD_REG29X_PAD_P1_DEB_4_Msk                                                                              (0x1UL << AON_REG_PAD_REG29X_PAD_P1_DEB_4_Pos)
+
+#define AON_REG_PAD_REG29X_PAD_P1_RAP_WKEN_4_Pos                                                                         25U
+#define AON_REG_PAD_REG29X_PAD_P1_RAP_WKEN_4_Msk                                                                         (0x1UL << AON_REG_PAD_REG29X_PAD_P1_RAP_WKEN_4_Pos)
+
+#define AON_REG_PAD_REG29X_PAD_P1_PPU_WKEN_4_Pos                                                                         26U
+#define AON_REG_PAD_REG29X_PAD_P1_PPU_WKEN_4_Msk                                                                         (0x1UL << AON_REG_PAD_REG29X_PAD_P1_PPU_WKEN_4_Pos)
+
+#define AON_REG_PAD_REG29X_RESERVED_1_Pos                                                                                27U
+#define AON_REG_PAD_REG29X_RESERVED_1_Msk                                                                                (0x1UL << AON_REG_PAD_REG29X_RESERVED_1_Pos)
+
+#define AON_REG_PAD_REG29X_RESERVED_Pos                                                                                  28U
+#define AON_REG_PAD_REG29X_RESERVED_Msk                                                                                  (0x3UL << AON_REG_PAD_REG29X_RESERVED_Pos)
+
+#define AON_REG_PAD_REG29X_PAD_P1_AON_MUX_4_Pos                                                                          30U
+#define AON_REG_PAD_REG29X_PAD_P1_AON_MUX_4_Msk                                                                          (0x3UL << AON_REG_PAD_REG29X_PAD_P1_AON_MUX_4_Pos)
+
+/* 0x198    0x4000_0198
+    13:0    R       RESERVED_1                                                  14'h0
+    14      R/W     SPIC_PAD_SMT                                                1'b0
+    15      R/W     SPIC_PAD_H3L1                                               1'b0
+    16      R/W     SPIC_PAD_E2                                                 1'b1
+    20:17   R       RESERVED                                                    4'h0
+    21      R/W     SPI0M_AON_PATH_EN                                           1'b0
+    22      R/W     SPI1M_AON_PATH_EN                                           1'b0
+    23      R/W     SPI2M_AON_PATH_EN                                           1'b0
+    24      R/W     AON_PAD_SPI_FLASH_S                                         1'h1
+    25      W1C     PAD_P1_STS_3                                                1'b1
+    26      W1C     PAD_P1_STS_4                                                1'b1
+    27      W1C     PAD_SPIC_SO_STS                                             1'b1
+    28      W1C     PAD_SPIC_SI_STS                                             1'b1
+    29      W1C     PAD_SPIC_SCK_STS                                            1'b1
+    30      W1C     PAD_SPIC_CSN_STS                                            1'b1
+    31      R/W     PAD_SPIC_SCK_O_EN                                           1'b1
+ */
+typedef union _AON_REG_SPI_PAD_REG30X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED_1: 14;
+        uint32_t SPIC_PAD_SMT: 1;
+        uint32_t SPIC_PAD_H3L1: 1;
+        uint32_t SPIC_PAD_E2: 1;
+        uint32_t RESERVED: 4;
+        uint32_t SPI0M_AON_PATH_EN: 1;
+        uint32_t SPI1M_AON_PATH_EN: 1;
+        uint32_t SPI2M_AON_PATH_EN: 1;
+        uint32_t AON_PAD_SPI_FLASH_S: 1;
+        uint32_t PAD_P1_STS_3: 1;
+        uint32_t PAD_P1_STS_4: 1;
+        uint32_t PAD_SPIC_SO_STS: 1;
+        uint32_t PAD_SPIC_SI_STS: 1;
+        uint32_t PAD_SPIC_SCK_STS: 1;
+        uint32_t PAD_SPIC_CSN_STS: 1;
+        uint32_t PAD_SPIC_SCK_O_EN: 1;
+    };
+} AON_REG_SPI_PAD_REG30X_TYPE;
+
+/*0x4000_0198 AON_REG_SPI_PAD_REG30X*/
+#define AON_REG_SPI_PAD_REG30X_RESERVED_1_Pos                                                                            0U
+#define AON_REG_SPI_PAD_REG30X_RESERVED_1_Msk                                                                            (0x3FFFUL << AON_REG_SPI_PAD_REG30X_RESERVED_1_Pos)
+
+#define AON_REG_SPI_PAD_REG30X_SPIC_PAD_SMT_Pos                                                                          14U
+#define AON_REG_SPI_PAD_REG30X_SPIC_PAD_SMT_Msk                                                                          (0x1UL << AON_REG_SPI_PAD_REG30X_SPIC_PAD_SMT_Pos)
+
+#define AON_REG_SPI_PAD_REG30X_SPIC_PAD_H3L1_Pos                                                                         15U
+#define AON_REG_SPI_PAD_REG30X_SPIC_PAD_H3L1_Msk                                                                         (0x1UL << AON_REG_SPI_PAD_REG30X_SPIC_PAD_H3L1_Pos)
+
+#define AON_REG_SPI_PAD_REG30X_SPIC_PAD_E2_Pos                                                                           16U
+#define AON_REG_SPI_PAD_REG30X_SPIC_PAD_E2_Msk                                                                           (0x1UL << AON_REG_SPI_PAD_REG30X_SPIC_PAD_E2_Pos)
+
+#define AON_REG_SPI_PAD_REG30X_RESERVED_Pos                                                                              17U
+#define AON_REG_SPI_PAD_REG30X_RESERVED_Msk                                                                              (0xFUL << AON_REG_SPI_PAD_REG30X_RESERVED_Pos)
+
+#define AON_REG_SPI_PAD_REG30X_SPI0M_AON_PATH_EN_Pos                                                                     21U
+#define AON_REG_SPI_PAD_REG30X_SPI0M_AON_PATH_EN_Msk                                                                     (0x1UL << AON_REG_SPI_PAD_REG30X_SPI0M_AON_PATH_EN_Pos)
+
+#define AON_REG_SPI_PAD_REG30X_SPI1M_AON_PATH_EN_Pos                                                                     22U
+#define AON_REG_SPI_PAD_REG30X_SPI1M_AON_PATH_EN_Msk                                                                     (0x1UL << AON_REG_SPI_PAD_REG30X_SPI1M_AON_PATH_EN_Pos)
+
+#define AON_REG_SPI_PAD_REG30X_SPI2M_AON_PATH_EN_Pos                                                                     23U
+#define AON_REG_SPI_PAD_REG30X_SPI2M_AON_PATH_EN_Msk                                                                     (0x1UL << AON_REG_SPI_PAD_REG30X_SPI2M_AON_PATH_EN_Pos)
+
+#define AON_REG_SPI_PAD_REG30X_AON_PAD_SPI_FLASH_S_Pos                                                                   24U
+#define AON_REG_SPI_PAD_REG30X_AON_PAD_SPI_FLASH_S_Msk                                                                   (0x1UL << AON_REG_SPI_PAD_REG30X_AON_PAD_SPI_FLASH_S_Pos)
+
+#define AON_REG_SPI_PAD_REG30X_PAD_P1_STS_3_Pos                                                                          25U
+#define AON_REG_SPI_PAD_REG30X_PAD_P1_STS_3_Msk                                                                          (0x1UL << AON_REG_SPI_PAD_REG30X_PAD_P1_STS_3_Pos)
+
+#define AON_REG_SPI_PAD_REG30X_PAD_P1_STS_4_Pos                                                                          26U
+#define AON_REG_SPI_PAD_REG30X_PAD_P1_STS_4_Msk                                                                          (0x1UL << AON_REG_SPI_PAD_REG30X_PAD_P1_STS_4_Pos)
+
+#define AON_REG_SPI_PAD_REG30X_PAD_SPIC_SO_STS_Pos                                                                       27U
+#define AON_REG_SPI_PAD_REG30X_PAD_SPIC_SO_STS_Msk                                                                       (0x1UL << AON_REG_SPI_PAD_REG30X_PAD_SPIC_SO_STS_Pos)
+
+#define AON_REG_SPI_PAD_REG30X_PAD_SPIC_SI_STS_Pos                                                                       28U
+#define AON_REG_SPI_PAD_REG30X_PAD_SPIC_SI_STS_Msk                                                                       (0x1UL << AON_REG_SPI_PAD_REG30X_PAD_SPIC_SI_STS_Pos)
+
+#define AON_REG_SPI_PAD_REG30X_PAD_SPIC_SCK_STS_Pos                                                                      29U
+#define AON_REG_SPI_PAD_REG30X_PAD_SPIC_SCK_STS_Msk                                                                      (0x1UL << AON_REG_SPI_PAD_REG30X_PAD_SPIC_SCK_STS_Pos)
+
+#define AON_REG_SPI_PAD_REG30X_PAD_SPIC_CSN_STS_Pos                                                                      30U
+#define AON_REG_SPI_PAD_REG30X_PAD_SPIC_CSN_STS_Msk                                                                      (0x1UL << AON_REG_SPI_PAD_REG30X_PAD_SPIC_CSN_STS_Pos)
+
+#define AON_REG_SPI_PAD_REG30X_PAD_SPIC_SCK_O_EN_Pos                                                                     31U
+#define AON_REG_SPI_PAD_REG30X_PAD_SPIC_SCK_O_EN_Msk                                                                     (0x1UL << AON_REG_SPI_PAD_REG30X_PAD_SPIC_SCK_O_EN_Pos)
+
+/* 0x19C    0x4000_019c
+    31:0    R/W     RESERVED                                                    32'b0
+ */
+typedef union _AON_REG_PAD_REG31X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED;
+    };
+} AON_REG_PAD_REG31X_TYPE;
+
+/*0x4000_019c AON_REG_PAD_REG31X*/
+#define AON_REG_PAD_REG31X_RESERVED_Pos                                                                                  0U
+#define AON_REG_PAD_REG31X_RESERVED_Msk                                                                                  (0xFFFFFFFFUL << AON_REG_PAD_REG31X_RESERVED_Pos)
+
+/* 0x1A0    0x4000_01a0
+    30:0    R/W     RESERVED                                                    31'b0
+    31      R/W     DEBUG_PCK600_VAON_REG_EN                                    1'b0
+ */
+typedef union _AON_REG_PAD_REG32X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED: 31;
+        uint32_t DEBUG_PCK600_VAON_REG_EN: 1;
+    };
+} AON_REG_PAD_REG32X_TYPE;
+
+/*0x4000_01a0 AON_REG_PAD_REG32X*/
+#define AON_REG_PAD_REG32X_RESERVED_Pos                                                                                  0U
+#define AON_REG_PAD_REG32X_RESERVED_Msk                                                                                  (0x7FFFFFFFUL << AON_REG_PAD_REG32X_RESERVED_Pos)
+
+#define AON_REG_PAD_REG32X_DEBUG_PCK600_VAON_REG_EN_Pos                                                                  31U
+#define AON_REG_PAD_REG32X_DEBUG_PCK600_VAON_REG_EN_Msk                                                                  (0x1UL << AON_REG_PAD_REG32X_DEBUG_PCK600_VAON_REG_EN_Pos)
+
+/* 0x1A4    0x4000_01a4
+    31:0    R       DEBUG_PCK_AON                                               32'b0
+ */
+typedef union _AON_REG_PAD_REG33X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t DEBUG_PCK_AON;
+    };
+} AON_REG_PAD_REG33X_TYPE;
+
+/*0x4000_01a4 AON_REG_PAD_REG33X*/
+#define AON_REG_PAD_REG33X_DEBUG_PCK_AON_Pos                                                                             0U
+#define AON_REG_PAD_REG33X_DEBUG_PCK_AON_Msk                                                                             (0xFFFFFFFFUL << AON_REG_PAD_REG33X_DEBUG_PCK_AON_Pos)
+
+/* 0x1A8    0x4000_01a8
+    1:0     R/W     SPI3W_SDIO_IN_PAD_PULL                                      2'b01
+    2       R/W     SPI3W_SDIO_OUT_PAD_PULL                                     1'b1
+    31:3    R/W     RESERVED                                                    29'b0
+ */
+typedef union _AON_REG_PAD_REG34X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t SPI3W_SDIO_IN_PAD_PULL: 2;
+        uint32_t SPI3W_SDIO_OUT_PAD_PULL: 1;
+        uint32_t RESERVED: 29;
+    };
+} AON_REG_PAD_REG34X_TYPE;
+
+/*0x4000_01a8 AON_REG_PAD_REG34X*/
+#define AON_REG_PAD_REG34X_SPI3W_SDIO_IN_PAD_PULL_Pos                                                                    0U
+#define AON_REG_PAD_REG34X_SPI3W_SDIO_IN_PAD_PULL_Msk                                                                    (0x3UL << AON_REG_PAD_REG34X_SPI3W_SDIO_IN_PAD_PULL_Pos)
+
+#define AON_REG_PAD_REG34X_SPI3W_SDIO_OUT_PAD_PULL_Pos                                                                   2U
+#define AON_REG_PAD_REG34X_SPI3W_SDIO_OUT_PAD_PULL_Msk                                                                   (0x1UL << AON_REG_PAD_REG34X_SPI3W_SDIO_OUT_PAD_PULL_Pos)
+
+#define AON_REG_PAD_REG34X_RESERVED_Pos                                                                                  3U
+#define AON_REG_PAD_REG34X_RESERVED_Msk                                                                                  (0x1FFFFFFFUL << AON_REG_PAD_REG34X_RESERVED_Pos)
+
+/* 0x1C4    0x4000_01c4
+    5:0     R/W     LPPWM_CH0_GPIO_SEL                                          6'h0
+    6       R/W     RESERVED_3                                                  1'h0
+    7       R/W     LPPWM_CH0_GPIO_SEL_EN                                       1'h0
+    13:8    R/W     LPQDEC_LED_GPIO_SEL                                         6'h0
+    14      R/W     RESERVED_2                                                  1'h0
+    15      R/W     LPQDEC_LED_GPIO_SEL_EN                                      1'h0
+    21:16   R/W     LPQDEC_PHB_GPIO_SEL                                         6'h0
+    22      R/W     RESERVED_1                                                  1'h0
+    23      R/W     LPQDEC_PHB_GPIO_SEL_EN                                      1'h0
+    29:24   R/W     LPQDEC_PHA_GPIO_SEL                                         6'h0
+    30      R/W     RESERVED                                                    1'h0
+    31      R/W     LPQDEC_PHA_GPIO_SEL_EN                                      1'h0
+ */
+typedef union _AON_REG_PAD_VPON_REG0X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t LPPWM_CH0_GPIO_SEL: 6;
+        uint32_t RESERVED_3: 1;
+        uint32_t LPPWM_CH0_GPIO_SEL_EN: 1;
+        uint32_t LPQDEC_LED_GPIO_SEL: 6;
+        uint32_t RESERVED_2: 1;
+        uint32_t LPQDEC_LED_GPIO_SEL_EN: 1;
+        uint32_t LPQDEC_PHB_GPIO_SEL: 6;
+        uint32_t RESERVED_1: 1;
+        uint32_t LPQDEC_PHB_GPIO_SEL_EN: 1;
+        uint32_t LPQDEC_PHA_GPIO_SEL: 6;
+        uint32_t RESERVED: 1;
+        uint32_t LPQDEC_PHA_GPIO_SEL_EN: 1;
+    };
+} AON_REG_PAD_VPON_REG0X_TYPE;
+
+/*0x4000_01c4 AON_REG_PAD_VPON_REG0X*/
+#define AON_REG_PAD_VPON_REG0X_LPPWM_CH0_GPIO_SEL_Pos                                                                    0U
+#define AON_REG_PAD_VPON_REG0X_LPPWM_CH0_GPIO_SEL_Msk                                                                    (0x3FUL << AON_REG_PAD_VPON_REG0X_LPPWM_CH0_GPIO_SEL_Pos)
+
+#define AON_REG_PAD_VPON_REG0X_RESERVED_3_Pos                                                                            6U
+#define AON_REG_PAD_VPON_REG0X_RESERVED_3_Msk                                                                            (0x1UL << AON_REG_PAD_VPON_REG0X_RESERVED_3_Pos)
+
+#define AON_REG_PAD_VPON_REG0X_LPPWM_CH0_GPIO_SEL_EN_Pos                                                                 7U
+#define AON_REG_PAD_VPON_REG0X_LPPWM_CH0_GPIO_SEL_EN_Msk                                                                 (0x1UL << AON_REG_PAD_VPON_REG0X_LPPWM_CH0_GPIO_SEL_EN_Pos)
+
+#define AON_REG_PAD_VPON_REG0X_LPQDEC_LED_GPIO_SEL_Pos                                                                   8U
+#define AON_REG_PAD_VPON_REG0X_LPQDEC_LED_GPIO_SEL_Msk                                                                   (0x3FUL << AON_REG_PAD_VPON_REG0X_LPQDEC_LED_GPIO_SEL_Pos)
+
+#define AON_REG_PAD_VPON_REG0X_RESERVED_2_Pos                                                                            14U
+#define AON_REG_PAD_VPON_REG0X_RESERVED_2_Msk                                                                            (0x1UL << AON_REG_PAD_VPON_REG0X_RESERVED_2_Pos)
+
+#define AON_REG_PAD_VPON_REG0X_LPQDEC_LED_GPIO_SEL_EN_Pos                                                                15U
+#define AON_REG_PAD_VPON_REG0X_LPQDEC_LED_GPIO_SEL_EN_Msk                                                                (0x1UL << AON_REG_PAD_VPON_REG0X_LPQDEC_LED_GPIO_SEL_EN_Pos)
+
+#define AON_REG_PAD_VPON_REG0X_LPQDEC_PHB_GPIO_SEL_Pos                                                                   16U
+#define AON_REG_PAD_VPON_REG0X_LPQDEC_PHB_GPIO_SEL_Msk                                                                   (0x3FUL << AON_REG_PAD_VPON_REG0X_LPQDEC_PHB_GPIO_SEL_Pos)
+
+#define AON_REG_PAD_VPON_REG0X_RESERVED_1_Pos                                                                            22U
+#define AON_REG_PAD_VPON_REG0X_RESERVED_1_Msk                                                                            (0x1UL << AON_REG_PAD_VPON_REG0X_RESERVED_1_Pos)
+
+#define AON_REG_PAD_VPON_REG0X_LPQDEC_PHB_GPIO_SEL_EN_Pos                                                                23U
+#define AON_REG_PAD_VPON_REG0X_LPQDEC_PHB_GPIO_SEL_EN_Msk                                                                (0x1UL << AON_REG_PAD_VPON_REG0X_LPQDEC_PHB_GPIO_SEL_EN_Pos)
+
+#define AON_REG_PAD_VPON_REG0X_LPQDEC_PHA_GPIO_SEL_Pos                                                                   24U
+#define AON_REG_PAD_VPON_REG0X_LPQDEC_PHA_GPIO_SEL_Msk                                                                   (0x3FUL << AON_REG_PAD_VPON_REG0X_LPQDEC_PHA_GPIO_SEL_Pos)
+
+#define AON_REG_PAD_VPON_REG0X_RESERVED_Pos                                                                              30U
+#define AON_REG_PAD_VPON_REG0X_RESERVED_Msk                                                                              (0x1UL << AON_REG_PAD_VPON_REG0X_RESERVED_Pos)
+
+#define AON_REG_PAD_VPON_REG0X_LPQDEC_PHA_GPIO_SEL_EN_Pos                                                                31U
+#define AON_REG_PAD_VPON_REG0X_LPQDEC_PHA_GPIO_SEL_EN_Msk                                                                (0x1UL << AON_REG_PAD_VPON_REG0X_LPQDEC_PHA_GPIO_SEL_EN_Pos)
+
+/* 0x1C8    0x4000_01c8
+    1:0     R/W     RTC_IN_SEL                                                  2'b00
+    2       R/W     PIN_CLK_OUT_SEL_0                                           1'b0
+    3       R/W     PIN_CLK_OUT_SEL_1                                           1'b0
+    4       R/W     DEBUG_PCK600_VPON_REG_EN                                    1'b0
+    31:5    R       RESERVED                                                    27'h0
+ */
+typedef union _AON_REG_PAD_VPON_REG1X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RTC_IN_SEL: 2;
+        uint32_t PIN_CLK_OUT_SEL_0: 1;
+        uint32_t PIN_CLK_OUT_SEL_1: 1;
+        uint32_t DEBUG_PCK600_VPON_REG_EN: 1;
+        uint32_t RESERVED: 27;
+    };
+} AON_REG_PAD_VPON_REG1X_TYPE;
+
+/*0x4000_01c8 AON_REG_PAD_VPON_REG1X*/
+#define AON_REG_PAD_VPON_REG1X_RTC_IN_SEL_Pos                                                                            0U
+#define AON_REG_PAD_VPON_REG1X_RTC_IN_SEL_Msk                                                                            (0x3UL << AON_REG_PAD_VPON_REG1X_RTC_IN_SEL_Pos)
+
+#define AON_REG_PAD_VPON_REG1X_PIN_CLK_OUT_SEL_0_Pos                                                                     2U
+#define AON_REG_PAD_VPON_REG1X_PIN_CLK_OUT_SEL_0_Msk                                                                     (0x1UL << AON_REG_PAD_VPON_REG1X_PIN_CLK_OUT_SEL_0_Pos)
+
+#define AON_REG_PAD_VPON_REG1X_PIN_CLK_OUT_SEL_1_Pos                                                                     3U
+#define AON_REG_PAD_VPON_REG1X_PIN_CLK_OUT_SEL_1_Msk                                                                     (0x1UL << AON_REG_PAD_VPON_REG1X_PIN_CLK_OUT_SEL_1_Pos)
+
+#define AON_REG_PAD_VPON_REG1X_DEBUG_PCK600_VPON_REG_EN_Pos                                                              4U
+#define AON_REG_PAD_VPON_REG1X_DEBUG_PCK600_VPON_REG_EN_Msk                                                              (0x1UL << AON_REG_PAD_VPON_REG1X_DEBUG_PCK600_VPON_REG_EN_Pos)
+
+#define AON_REG_PAD_VPON_REG1X_RESERVED_Pos                                                                              5U
+#define AON_REG_PAD_VPON_REG1X_RESERVED_Msk                                                                              (0x7FFFFFFUL << AON_REG_PAD_VPON_REG1X_RESERVED_Pos)
+
+/* 0x1CC    0x4000_01cc
+    31:0    R       DEBUG_PCK_VPON                                              32'h0
+ */
+typedef union _AON_REG_PAD_VPON_REG2X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t DEBUG_PCK_VPON;
+    };
+} AON_REG_PAD_VPON_REG2X_TYPE;
+
+/*0x4000_01cc AON_REG_PAD_VPON_REG2X*/
+#define AON_REG_PAD_VPON_REG2X_DEBUG_PCK_VPON_Pos                                                                        0U
+#define AON_REG_PAD_VPON_REG2X_DEBUG_PCK_VPON_Msk                                                                        (0xFFFFFFFFUL << AON_REG_PAD_VPON_REG2X_DEBUG_PCK_VPON_Pos)
+
+/* 0x400    0x4000_0400
+    27:0    R/W     LPWDT_CNT_LIMIT                                             28'h55F00
+    28      R/W     LPWDT_MODE                                                  1'b0
+    29      R/W     LPWDT_CNT_CTL                                               1'b0
+    30      R/W     LPWDT_CNT_RELOAD                                            1'b0
+    31      R/W     LPWDT_ENABLE                                                1'b0
+ */
+typedef union _AON_REG_WDT_REG0X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t LPWDT_CNT_LIMIT: 28;
+        uint32_t LPWDT_MODE: 1;
+        uint32_t LPWDT_CNT_CTL: 1;
+        uint32_t LPWDT_CNT_RELOAD: 1;
+        uint32_t LPWDT_ENABLE: 1;
+    };
+} AON_REG_WDT_REG0X_TYPE;
+
+/*0x4000_0400 AON_REG_WDT_REG0X*/
+#define AON_REG_WDT_REG0X_LPWDT_CNT_LIMIT_Pos                                                                            0U
+#define AON_REG_WDT_REG0X_LPWDT_CNT_LIMIT_Msk                                                                            (0xFFFFFFFUL << AON_REG_WDT_REG0X_LPWDT_CNT_LIMIT_Pos)
+
+#define AON_REG_WDT_REG0X_LPWDT_MODE_Pos                                                                                 28U
+#define AON_REG_WDT_REG0X_LPWDT_MODE_Msk                                                                                 (0x1UL << AON_REG_WDT_REG0X_LPWDT_MODE_Pos)
+
+#define AON_REG_WDT_REG0X_LPWDT_CNT_CTL_Pos                                                                              29U
+#define AON_REG_WDT_REG0X_LPWDT_CNT_CTL_Msk                                                                              (0x1UL << AON_REG_WDT_REG0X_LPWDT_CNT_CTL_Pos)
+
+#define AON_REG_WDT_REG0X_LPWDT_CNT_RELOAD_Pos                                                                           30U
+#define AON_REG_WDT_REG0X_LPWDT_CNT_RELOAD_Msk                                                                           (0x1UL << AON_REG_WDT_REG0X_LPWDT_CNT_RELOAD_Pos)
+
+#define AON_REG_WDT_REG0X_LPWDT_ENABLE_Pos                                                                               31U
+#define AON_REG_WDT_REG0X_LPWDT_ENABLE_Msk                                                                               (0x1UL << AON_REG_WDT_REG0X_LPWDT_ENABLE_Pos)
+
+/* 0x404    0x4000_0404
+    15:0    R/WAC   LPWDT_CNT_RESET                                             16'h0
+    16      R/W     LPWDT_CLK32K_QACTIVE_MAN_DATA                               1'b0
+    17      R/W     LPWDT_CLK32K_QACTIVE_MAN_EN                                 1'b0
+    31:18   R/W     RESERVED                                                    14'h0
+ */
+typedef union _AON_REG_WDT_REG1X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t LPWDT_CNT_RESET: 16;
+        uint32_t LPWDT_CLK32K_QACTIVE_MAN_DATA: 1;
+        uint32_t LPWDT_CLK32K_QACTIVE_MAN_EN: 1;
+        uint32_t RESERVED: 14;
+    };
+} AON_REG_WDT_REG1X_TYPE;
+
+/*0x4000_0404 AON_REG_WDT_REG1X*/
+#define AON_REG_WDT_REG1X_LPWDT_CNT_RESET_Pos                                                                            0U
+#define AON_REG_WDT_REG1X_LPWDT_CNT_RESET_Msk                                                                            (0xFFFFUL << AON_REG_WDT_REG1X_LPWDT_CNT_RESET_Pos)
+
+#define AON_REG_WDT_REG1X_LPWDT_CLK32K_QACTIVE_MAN_DATA_Pos                                                              16U
+#define AON_REG_WDT_REG1X_LPWDT_CLK32K_QACTIVE_MAN_DATA_Msk                                                              (0x1UL << AON_REG_WDT_REG1X_LPWDT_CLK32K_QACTIVE_MAN_DATA_Pos)
+
+#define AON_REG_WDT_REG1X_LPWDT_CLK32K_QACTIVE_MAN_EN_Pos                                                                17U
+#define AON_REG_WDT_REG1X_LPWDT_CLK32K_QACTIVE_MAN_EN_Msk                                                                (0x1UL << AON_REG_WDT_REG1X_LPWDT_CLK32K_QACTIVE_MAN_EN_Pos)
+
+#define AON_REG_WDT_REG1X_RESERVED_Pos                                                                                   18U
+#define AON_REG_WDT_REG1X_RESERVED_Msk                                                                                   (0x3FFFUL << AON_REG_WDT_REG1X_RESERVED_Pos)
+
+/* 0x408    0x4000_0408
+    15:0    R       COREWDT_CPU_PC_LSB                                          16'b0
+    31:16   R       COREWDT_CPU_PC_MSB                                          16'b0
+ */
+typedef union _AON_REG_WDT_REG2X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t COREWDT_CPU_PC_LSB: 16;
+        uint32_t COREWDT_CPU_PC_MSB: 16;
+    };
+} AON_REG_WDT_REG2X_TYPE;
+
+/*0x4000_0408 AON_REG_WDT_REG2X*/
+#define AON_REG_WDT_REG2X_COREWDT_CPU_PC_LSB_Pos                                                                         0U
+#define AON_REG_WDT_REG2X_COREWDT_CPU_PC_LSB_Msk                                                                         (0xFFFFUL << AON_REG_WDT_REG2X_COREWDT_CPU_PC_LSB_Pos)
+
+#define AON_REG_WDT_REG2X_COREWDT_CPU_PC_MSB_Pos                                                                         16U
+#define AON_REG_WDT_REG2X_COREWDT_CPU_PC_MSB_Msk                                                                         (0xFFFFUL << AON_REG_WDT_REG2X_COREWDT_CPU_PC_MSB_Pos)
+
+/* 0x40C    0x4000_040c
+    15:0    R       COREWDT_CPU_XPSR_LSB                                        16'b0
+    31:16   R       COREWDT_CPU_XPSR_MSB                                        16'b0
+ */
+typedef union _AON_REG_WDT_REG3X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t COREWDT_CPU_XPSR_LSB: 16;
+        uint32_t COREWDT_CPU_XPSR_MSB: 16;
+    };
+} AON_REG_WDT_REG3X_TYPE;
+
+/*0x4000_040c AON_REG_WDT_REG3X*/
+#define AON_REG_WDT_REG3X_COREWDT_CPU_XPSR_LSB_Pos                                                                       0U
+#define AON_REG_WDT_REG3X_COREWDT_CPU_XPSR_LSB_Msk                                                                       (0xFFFFUL << AON_REG_WDT_REG3X_COREWDT_CPU_XPSR_LSB_Pos)
+
+#define AON_REG_WDT_REG3X_COREWDT_CPU_XPSR_MSB_Pos                                                                       16U
+#define AON_REG_WDT_REG3X_COREWDT_CPU_XPSR_MSB_Msk                                                                       (0xFFFFUL << AON_REG_WDT_REG3X_COREWDT_CPU_XPSR_MSB_Pos)
+
+/* 0x410    0x4000_0410
+    15:0    R       COREWDT_CPU_LR_LSB                                          16'b0
+    31:16   R       COREWDT_CPU_LR_MSB                                          16'b0
+ */
+typedef union _AON_REG_WDT_REG4X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t COREWDT_CPU_LR_LSB: 16;
+        uint32_t COREWDT_CPU_LR_MSB: 16;
+    };
+} AON_REG_WDT_REG4X_TYPE;
+
+/*0x4000_0410 AON_REG_WDT_REG4X*/
+#define AON_REG_WDT_REG4X_COREWDT_CPU_LR_LSB_Pos                                                                         0U
+#define AON_REG_WDT_REG4X_COREWDT_CPU_LR_LSB_Msk                                                                         (0xFFFFUL << AON_REG_WDT_REG4X_COREWDT_CPU_LR_LSB_Pos)
+
+#define AON_REG_WDT_REG4X_COREWDT_CPU_LR_MSB_Pos                                                                         16U
+#define AON_REG_WDT_REG4X_COREWDT_CPU_LR_MSB_Msk                                                                         (0xFFFFUL << AON_REG_WDT_REG4X_COREWDT_CPU_LR_MSB_Pos)
+
+/* 0x414    0x4000_0414
+    15:0    R       COREWDT_CPU_R00_Q_LSB                                       16'b0
+    31:16   R       COREWDT_CPU_R00_Q_MSB                                       16'b0
+ */
+typedef union _AON_REG_WDT_REG5X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t COREWDT_CPU_R00_Q_LSB: 16;
+        uint32_t COREWDT_CPU_R00_Q_MSB: 16;
+    };
+} AON_REG_WDT_REG5X_TYPE;
+
+/*0x4000_0414 AON_REG_WDT_REG5X*/
+#define AON_REG_WDT_REG5X_COREWDT_CPU_R00_Q_LSB_Pos                                                                      0U
+#define AON_REG_WDT_REG5X_COREWDT_CPU_R00_Q_LSB_Msk                                                                      (0xFFFFUL << AON_REG_WDT_REG5X_COREWDT_CPU_R00_Q_LSB_Pos)
+
+#define AON_REG_WDT_REG5X_COREWDT_CPU_R00_Q_MSB_Pos                                                                      16U
+#define AON_REG_WDT_REG5X_COREWDT_CPU_R00_Q_MSB_Msk                                                                      (0xFFFFUL << AON_REG_WDT_REG5X_COREWDT_CPU_R00_Q_MSB_Pos)
+
+/* 0x418    0x4000_0418
+    15:0    R       COREWDT_CPU_R01_Q_LSB                                       16'b0
+    31:16   R       COREWDT_CPU_R01_Q_MSB                                       16'b0
+ */
+typedef union _AON_REG_WDT_REG6X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t COREWDT_CPU_R01_Q_LSB: 16;
+        uint32_t COREWDT_CPU_R01_Q_MSB: 16;
+    };
+} AON_REG_WDT_REG6X_TYPE;
+
+/*0x4000_0418 AON_REG_WDT_REG6X*/
+#define AON_REG_WDT_REG6X_COREWDT_CPU_R01_Q_LSB_Pos                                                                      0U
+#define AON_REG_WDT_REG6X_COREWDT_CPU_R01_Q_LSB_Msk                                                                      (0xFFFFUL << AON_REG_WDT_REG6X_COREWDT_CPU_R01_Q_LSB_Pos)
+
+#define AON_REG_WDT_REG6X_COREWDT_CPU_R01_Q_MSB_Pos                                                                      16U
+#define AON_REG_WDT_REG6X_COREWDT_CPU_R01_Q_MSB_Msk                                                                      (0xFFFFUL << AON_REG_WDT_REG6X_COREWDT_CPU_R01_Q_MSB_Pos)
+
+/* 0x41C    0x4000_041c
+    15:0    R       COREWDT_CPU_R02_Q_LSB                                       16'b0
+    31:16   R       COREWDT_CPU_R02_Q_MSB                                       16'b0
+ */
+typedef union _AON_REG_WDT_REG7X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t COREWDT_CPU_R02_Q_LSB: 16;
+        uint32_t COREWDT_CPU_R02_Q_MSB: 16;
+    };
+} AON_REG_WDT_REG7X_TYPE;
+
+/*0x4000_041c AON_REG_WDT_REG7X*/
+#define AON_REG_WDT_REG7X_COREWDT_CPU_R02_Q_LSB_Pos                                                                      0U
+#define AON_REG_WDT_REG7X_COREWDT_CPU_R02_Q_LSB_Msk                                                                      (0xFFFFUL << AON_REG_WDT_REG7X_COREWDT_CPU_R02_Q_LSB_Pos)
+
+#define AON_REG_WDT_REG7X_COREWDT_CPU_R02_Q_MSB_Pos                                                                      16U
+#define AON_REG_WDT_REG7X_COREWDT_CPU_R02_Q_MSB_Msk                                                                      (0xFFFFUL << AON_REG_WDT_REG7X_COREWDT_CPU_R02_Q_MSB_Pos)
+
+/* 0x420    0x4000_0420
+    15:0    R       COREWDT_CPU_R03_Q_LSB                                       16'b0
+    31:16   R       COREWDT_CPU_R03_Q_MSB                                       16'b0
+ */
+typedef union _AON_REG_WDT_REG8X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t COREWDT_CPU_R03_Q_LSB: 16;
+        uint32_t COREWDT_CPU_R03_Q_MSB: 16;
+    };
+} AON_REG_WDT_REG8X_TYPE;
+
+/*0x4000_0420 AON_REG_WDT_REG8X*/
+#define AON_REG_WDT_REG8X_COREWDT_CPU_R03_Q_LSB_Pos                                                                      0U
+#define AON_REG_WDT_REG8X_COREWDT_CPU_R03_Q_LSB_Msk                                                                      (0xFFFFUL << AON_REG_WDT_REG8X_COREWDT_CPU_R03_Q_LSB_Pos)
+
+#define AON_REG_WDT_REG8X_COREWDT_CPU_R03_Q_MSB_Pos                                                                      16U
+#define AON_REG_WDT_REG8X_COREWDT_CPU_R03_Q_MSB_Msk                                                                      (0xFFFFUL << AON_REG_WDT_REG8X_COREWDT_CPU_R03_Q_MSB_Pos)
+
+/* 0x424    0x4000_0424
+    0       R       COREWDT_FLAG                                                1'b0
+    2:1     R       COREWDT_MODE                                                2'b0
+    31:3    R       RESERVED                                                    29'b0
+ */
+typedef union _AON_REG_WDT_REG9X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t COREWDT_FLAG: 1;
+        uint32_t COREWDT_MODE: 2;
+        uint32_t RESERVED: 29;
+    };
+} AON_REG_WDT_REG9X_TYPE;
+
+/*0x4000_0424 AON_REG_WDT_REG9X*/
+#define AON_REG_WDT_REG9X_COREWDT_FLAG_Pos                                                                               0U
+#define AON_REG_WDT_REG9X_COREWDT_FLAG_Msk                                                                               (0x1UL << AON_REG_WDT_REG9X_COREWDT_FLAG_Pos)
+
+#define AON_REG_WDT_REG9X_COREWDT_MODE_Pos                                                                               1U
+#define AON_REG_WDT_REG9X_COREWDT_MODE_Msk                                                                               (0x3UL << AON_REG_WDT_REG9X_COREWDT_MODE_Pos)
+
+#define AON_REG_WDT_REG9X_RESERVED_Pos                                                                                   3U
+#define AON_REG_WDT_REG9X_RESERVED_Msk                                                                                   (0x1FFFFFFFUL << AON_REG_WDT_REG9X_RESERVED_Pos)
+
+/* 0x428    0x4000_0428
+    0       R/WAC   COREWDT_FLAG_CLR                                            1'b0
+    1       R/WAC   COREWDT_MODE_CLR                                            1'b0
+    15:2    R       RESERVED_1                                                  14'b0
+    16      R/WAC   COREWDT_CPU_REG_CLR                                         1'b0
+    31:17   R       RESERVED                                                    15'b0
+ */
+typedef union _AON_REG_WDT_REG10X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t COREWDT_FLAG_CLR: 1;
+        uint32_t COREWDT_MODE_CLR: 1;
+        uint32_t RESERVED_1: 14;
+        uint32_t COREWDT_CPU_REG_CLR: 1;
+        uint32_t RESERVED: 15;
+    };
+} AON_REG_WDT_REG10X_TYPE;
+
+/*0x4000_0428 AON_REG_WDT_REG10X*/
+#define AON_REG_WDT_REG10X_COREWDT_FLAG_CLR_Pos                                                                          0U
+#define AON_REG_WDT_REG10X_COREWDT_FLAG_CLR_Msk                                                                          (0x1UL << AON_REG_WDT_REG10X_COREWDT_FLAG_CLR_Pos)
+
+#define AON_REG_WDT_REG10X_COREWDT_MODE_CLR_Pos                                                                          1U
+#define AON_REG_WDT_REG10X_COREWDT_MODE_CLR_Msk                                                                          (0x1UL << AON_REG_WDT_REG10X_COREWDT_MODE_CLR_Pos)
+
+#define AON_REG_WDT_REG10X_RESERVED_1_Pos                                                                                2U
+#define AON_REG_WDT_REG10X_RESERVED_1_Msk                                                                                (0x3FFFUL << AON_REG_WDT_REG10X_RESERVED_1_Pos)
+
+#define AON_REG_WDT_REG10X_COREWDT_CPU_REG_CLR_Pos                                                                       16U
+#define AON_REG_WDT_REG10X_COREWDT_CPU_REG_CLR_Msk                                                                       (0x1UL << AON_REG_WDT_REG10X_COREWDT_CPU_REG_CLR_Pos)
+
+#define AON_REG_WDT_REG10X_RESERVED_Pos                                                                                  17U
+#define AON_REG_WDT_REG10X_RESERVED_Msk                                                                                  (0x7FFFUL << AON_REG_WDT_REG10X_RESERVED_Pos)
+
+/* 0x42C    0x4000_042c
+    31:0    R       RESERVED                                                    32'b0
+ */
+typedef union _AON_REG_WDT_REG11X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED;
+    };
+} AON_REG_WDT_REG11X_TYPE;
+
+/*0x4000_042c AON_REG_WDT_REG11X*/
+#define AON_REG_WDT_REG11X_RESERVED_Pos                                                                                  0U
+#define AON_REG_WDT_REG11X_RESERVED_Msk                                                                                  (0xFFFFFFFFUL << AON_REG_WDT_REG11X_RESERVED_Pos)
+
+/* 0x430    0x4000_0430
+    15:0    R       LPWDT_CPU_PC_LSB                                            16'b0
+    31:16   R       LPWDT_CPU_PC_MSB                                            16'b0
+ */
+typedef union _AON_REG_WDT_REG12X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t LPWDT_CPU_PC_LSB: 16;
+        uint32_t LPWDT_CPU_PC_MSB: 16;
+    };
+} AON_REG_WDT_REG12X_TYPE;
+
+/*0x4000_0430 AON_REG_WDT_REG12X*/
+#define AON_REG_WDT_REG12X_LPWDT_CPU_PC_LSB_Pos                                                                          0U
+#define AON_REG_WDT_REG12X_LPWDT_CPU_PC_LSB_Msk                                                                          (0xFFFFUL << AON_REG_WDT_REG12X_LPWDT_CPU_PC_LSB_Pos)
+
+#define AON_REG_WDT_REG12X_LPWDT_CPU_PC_MSB_Pos                                                                          16U
+#define AON_REG_WDT_REG12X_LPWDT_CPU_PC_MSB_Msk                                                                          (0xFFFFUL << AON_REG_WDT_REG12X_LPWDT_CPU_PC_MSB_Pos)
+
+/* 0x434    0x4000_0434
+    15:0    R       LPWDT_CPU_XPSR_LSB                                          16'b0
+    31:16   R       LPWDT_CPU_XPSR_MSB                                          16'b0
+ */
+typedef union _AON_REG_WDT_REG13X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t LPWDT_CPU_XPSR_LSB: 16;
+        uint32_t LPWDT_CPU_XPSR_MSB: 16;
+    };
+} AON_REG_WDT_REG13X_TYPE;
+
+/*0x4000_0434 AON_REG_WDT_REG13X*/
+#define AON_REG_WDT_REG13X_LPWDT_CPU_XPSR_LSB_Pos                                                                        0U
+#define AON_REG_WDT_REG13X_LPWDT_CPU_XPSR_LSB_Msk                                                                        (0xFFFFUL << AON_REG_WDT_REG13X_LPWDT_CPU_XPSR_LSB_Pos)
+
+#define AON_REG_WDT_REG13X_LPWDT_CPU_XPSR_MSB_Pos                                                                        16U
+#define AON_REG_WDT_REG13X_LPWDT_CPU_XPSR_MSB_Msk                                                                        (0xFFFFUL << AON_REG_WDT_REG13X_LPWDT_CPU_XPSR_MSB_Pos)
+
+/* 0x438    0x4000_0438
+    15:0    R       LPWDT_CPU_LR_LSB                                            16'b0
+    31:16   R       LPWDT_CPU_LR_MSB                                            16'b0
+ */
+typedef union _AON_REG_WDT_REG14X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t LPWDT_CPU_LR_LSB: 16;
+        uint32_t LPWDT_CPU_LR_MSB: 16;
+    };
+} AON_REG_WDT_REG14X_TYPE;
+
+/*0x4000_0438 AON_REG_WDT_REG14X*/
+#define AON_REG_WDT_REG14X_LPWDT_CPU_LR_LSB_Pos                                                                          0U
+#define AON_REG_WDT_REG14X_LPWDT_CPU_LR_LSB_Msk                                                                          (0xFFFFUL << AON_REG_WDT_REG14X_LPWDT_CPU_LR_LSB_Pos)
+
+#define AON_REG_WDT_REG14X_LPWDT_CPU_LR_MSB_Pos                                                                          16U
+#define AON_REG_WDT_REG14X_LPWDT_CPU_LR_MSB_Msk                                                                          (0xFFFFUL << AON_REG_WDT_REG14X_LPWDT_CPU_LR_MSB_Pos)
+
+/* 0x43C    0x4000_043c
+    15:0    R       LPWDT_CPU_R00_Q_LSB                                         16'b0
+    31:16   R       LPWDT_CPU_R00_Q_MSB                                         16'b0
+ */
+typedef union _AON_REG_WDT_REG15X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t LPWDT_CPU_R00_Q_LSB: 16;
+        uint32_t LPWDT_CPU_R00_Q_MSB: 16;
+    };
+} AON_REG_WDT_REG15X_TYPE;
+
+/*0x4000_043c AON_REG_WDT_REG15X*/
+#define AON_REG_WDT_REG15X_LPWDT_CPU_R00_Q_LSB_Pos                                                                       0U
+#define AON_REG_WDT_REG15X_LPWDT_CPU_R00_Q_LSB_Msk                                                                       (0xFFFFUL << AON_REG_WDT_REG15X_LPWDT_CPU_R00_Q_LSB_Pos)
+
+#define AON_REG_WDT_REG15X_LPWDT_CPU_R00_Q_MSB_Pos                                                                       16U
+#define AON_REG_WDT_REG15X_LPWDT_CPU_R00_Q_MSB_Msk                                                                       (0xFFFFUL << AON_REG_WDT_REG15X_LPWDT_CPU_R00_Q_MSB_Pos)
+
+/* 0x440    0x4000_0440
+    15:0    R       LPWDT_CPU_R01_Q_LSB                                         16'b0
+    31:16   R       LPWDT_CPU_R01_Q_MSB                                         16'b0
+ */
+typedef union _AON_REG_WDT_REG16X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t LPWDT_CPU_R01_Q_LSB: 16;
+        uint32_t LPWDT_CPU_R01_Q_MSB: 16;
+    };
+} AON_REG_WDT_REG16X_TYPE;
+
+/*0x4000_0440 AON_REG_WDT_REG16X*/
+#define AON_REG_WDT_REG16X_LPWDT_CPU_R01_Q_LSB_Pos                                                                       0U
+#define AON_REG_WDT_REG16X_LPWDT_CPU_R01_Q_LSB_Msk                                                                       (0xFFFFUL << AON_REG_WDT_REG16X_LPWDT_CPU_R01_Q_LSB_Pos)
+
+#define AON_REG_WDT_REG16X_LPWDT_CPU_R01_Q_MSB_Pos                                                                       16U
+#define AON_REG_WDT_REG16X_LPWDT_CPU_R01_Q_MSB_Msk                                                                       (0xFFFFUL << AON_REG_WDT_REG16X_LPWDT_CPU_R01_Q_MSB_Pos)
+
+/* 0x444    0x4000_0444
+    15:0    R       LPWDT_CPU_R02_Q_LSB                                         16'b0
+    31:16   R       LPWDT_CPU_R02_Q_MSB                                         16'b0
+ */
+typedef union _AON_REG_WDT_REG17X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t LPWDT_CPU_R02_Q_LSB: 16;
+        uint32_t LPWDT_CPU_R02_Q_MSB: 16;
+    };
+} AON_REG_WDT_REG17X_TYPE;
+
+/*0x4000_0444 AON_REG_WDT_REG17X*/
+#define AON_REG_WDT_REG17X_LPWDT_CPU_R02_Q_LSB_Pos                                                                       0U
+#define AON_REG_WDT_REG17X_LPWDT_CPU_R02_Q_LSB_Msk                                                                       (0xFFFFUL << AON_REG_WDT_REG17X_LPWDT_CPU_R02_Q_LSB_Pos)
+
+#define AON_REG_WDT_REG17X_LPWDT_CPU_R02_Q_MSB_Pos                                                                       16U
+#define AON_REG_WDT_REG17X_LPWDT_CPU_R02_Q_MSB_Msk                                                                       (0xFFFFUL << AON_REG_WDT_REG17X_LPWDT_CPU_R02_Q_MSB_Pos)
+
+/* 0x448    0x4000_0448
+    15:0    R       LPWDT_CPU_R03_Q_LSB                                         16'b0
+    31:16   R       LPWDT_CPU_R03_Q_MSB                                         16'b0
+ */
+typedef union _AON_REG_WDT_REG18X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t LPWDT_CPU_R03_Q_LSB: 16;
+        uint32_t LPWDT_CPU_R03_Q_MSB: 16;
+    };
+} AON_REG_WDT_REG18X_TYPE;
+
+/*0x4000_0448 AON_REG_WDT_REG18X*/
+#define AON_REG_WDT_REG18X_LPWDT_CPU_R03_Q_LSB_Pos                                                                       0U
+#define AON_REG_WDT_REG18X_LPWDT_CPU_R03_Q_LSB_Msk                                                                       (0xFFFFUL << AON_REG_WDT_REG18X_LPWDT_CPU_R03_Q_LSB_Pos)
+
+#define AON_REG_WDT_REG18X_LPWDT_CPU_R03_Q_MSB_Pos                                                                       16U
+#define AON_REG_WDT_REG18X_LPWDT_CPU_R03_Q_MSB_Msk                                                                       (0xFFFFUL << AON_REG_WDT_REG18X_LPWDT_CPU_R03_Q_MSB_Pos)
+
+/* 0x44C    0x4000_044c
+    0       R       LPWDT_FLAG                                                  1'b0
+    2:1     R       LPWDT_MODE_RECORD                                           2'b0
+    30:3    R       LPWDT_CURRENT                                               28'b0
+    31      R       RESERVED                                                    1'b0
+ */
+typedef union _AON_REG_WDT_REG19X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t LPWDT_FLAG: 1;
+        uint32_t LPWDT_MODE_RECORD: 2;
+        uint32_t LPWDT_CURRENT: 28;
+        uint32_t RESERVED: 1;
+    };
+} AON_REG_WDT_REG19X_TYPE;
+
+/*0x4000_044c AON_REG_WDT_REG19X*/
+#define AON_REG_WDT_REG19X_LPWDT_FLAG_Pos                                                                                0U
+#define AON_REG_WDT_REG19X_LPWDT_FLAG_Msk                                                                                (0x1UL << AON_REG_WDT_REG19X_LPWDT_FLAG_Pos)
+
+#define AON_REG_WDT_REG19X_LPWDT_MODE_RECORD_Pos                                                                         1U
+#define AON_REG_WDT_REG19X_LPWDT_MODE_RECORD_Msk                                                                         (0x3UL << AON_REG_WDT_REG19X_LPWDT_MODE_RECORD_Pos)
+
+#define AON_REG_WDT_REG19X_LPWDT_CURRENT_Pos                                                                             3U
+#define AON_REG_WDT_REG19X_LPWDT_CURRENT_Msk                                                                             (0xFFFFFFFUL << AON_REG_WDT_REG19X_LPWDT_CURRENT_Pos)
+
+#define AON_REG_WDT_REG19X_RESERVED_Pos                                                                                  31U
+#define AON_REG_WDT_REG19X_RESERVED_Msk                                                                                  (0x1UL << AON_REG_WDT_REG19X_RESERVED_Pos)
+
+/* 0x450    0x4000_0450
+    0       R/WAC   LPWDT_FLAG_CLR                                              1'b0
+    1       R/WAC   LPWDT_MODE_CLR                                              1'b0
+    15:2    R       RESERVED_1                                                  14'b0
+    16      R/WAC   LPWDT_CPU_REG_CLR                                           1'b0
+    31:17   R       RESERVED                                                    15'b0
+ */
+typedef union _AON_REG_WDT_REG20X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t LPWDT_FLAG_CLR: 1;
+        uint32_t LPWDT_MODE_CLR: 1;
+        uint32_t RESERVED_1: 14;
+        uint32_t LPWDT_CPU_REG_CLR: 1;
+        uint32_t RESERVED: 15;
+    };
+} AON_REG_WDT_REG20X_TYPE;
+
+/*0x4000_0450 AON_REG_WDT_REG20X*/
+#define AON_REG_WDT_REG20X_LPWDT_FLAG_CLR_Pos                                                                            0U
+#define AON_REG_WDT_REG20X_LPWDT_FLAG_CLR_Msk                                                                            (0x1UL << AON_REG_WDT_REG20X_LPWDT_FLAG_CLR_Pos)
+
+#define AON_REG_WDT_REG20X_LPWDT_MODE_CLR_Pos                                                                            1U
+#define AON_REG_WDT_REG20X_LPWDT_MODE_CLR_Msk                                                                            (0x1UL << AON_REG_WDT_REG20X_LPWDT_MODE_CLR_Pos)
+
+#define AON_REG_WDT_REG20X_RESERVED_1_Pos                                                                                2U
+#define AON_REG_WDT_REG20X_RESERVED_1_Msk                                                                                (0x3FFFUL << AON_REG_WDT_REG20X_RESERVED_1_Pos)
+
+#define AON_REG_WDT_REG20X_LPWDT_CPU_REG_CLR_Pos                                                                         16U
+#define AON_REG_WDT_REG20X_LPWDT_CPU_REG_CLR_Msk                                                                         (0x1UL << AON_REG_WDT_REG20X_LPWDT_CPU_REG_CLR_Pos)
+
+#define AON_REG_WDT_REG20X_RESERVED_Pos                                                                                  17U
+#define AON_REG_WDT_REG20X_RESERVED_Msk                                                                                  (0x7FFFUL << AON_REG_WDT_REG20X_RESERVED_Pos)
+
+/* 0x458    0x4000_0458
+    18:0    R/W     REG_AON_WDT_COMP                                            19'h00000
+    19      R/W     REG_AON_WDT_CLK                                             1'b0
+    20      R/W     REG_AON_WDT_RSTN                                            1'b0
+    24:21   R/W     OSCCTUNE                                                    4'b1000
+    28:25   R/W     OSCRTUNE                                                    4'b1000
+    29      R/W     OSC_POW                                                     1'b0
+    30      R/W     WDT_EN                                                      1'b0
+    31      R/W     WDT_CKOUT_EN                                                1'b0
+ */
+typedef union _AON_REG_IO_WDT_REG0X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t REG_AON_WDT_COMP: 19;
+        uint32_t REG_AON_WDT_CLK: 1;
+        uint32_t REG_AON_WDT_RSTN: 1;
+        uint32_t OSCCTUNE: 4;
+        uint32_t OSCRTUNE: 4;
+        uint32_t OSC_POW: 1;
+        uint32_t WDT_EN: 1;
+        uint32_t WDT_CKOUT_EN: 1;
+    };
+} AON_REG_IO_WDT_REG0X_TYPE;
+
+/*0x4000_0458 AON_REG_IO_WDT_REG0X*/
+#define AON_REG_IO_WDT_REG0X_REG_AON_WDT_COMP_Pos                                                                        0U
+#define AON_REG_IO_WDT_REG0X_REG_AON_WDT_COMP_Msk                                                                        (0x7FFFFUL << AON_REG_IO_WDT_REG0X_REG_AON_WDT_COMP_Pos)
+
+#define AON_REG_IO_WDT_REG0X_REG_AON_WDT_CLK_Pos                                                                         19U
+#define AON_REG_IO_WDT_REG0X_REG_AON_WDT_CLK_Msk                                                                         (0x1UL << AON_REG_IO_WDT_REG0X_REG_AON_WDT_CLK_Pos)
+
+#define AON_REG_IO_WDT_REG0X_REG_AON_WDT_RSTN_Pos                                                                        20U
+#define AON_REG_IO_WDT_REG0X_REG_AON_WDT_RSTN_Msk                                                                        (0x1UL << AON_REG_IO_WDT_REG0X_REG_AON_WDT_RSTN_Pos)
+
+#define AON_REG_IO_WDT_REG0X_OSCCTUNE_Pos                                                                                21U
+#define AON_REG_IO_WDT_REG0X_OSCCTUNE_Msk                                                                                (0xFUL << AON_REG_IO_WDT_REG0X_OSCCTUNE_Pos)
+
+#define AON_REG_IO_WDT_REG0X_OSCRTUNE_Pos                                                                                25U
+#define AON_REG_IO_WDT_REG0X_OSCRTUNE_Msk                                                                                (0xFUL << AON_REG_IO_WDT_REG0X_OSCRTUNE_Pos)
+
+#define AON_REG_IO_WDT_REG0X_OSC_POW_Pos                                                                                 29U
+#define AON_REG_IO_WDT_REG0X_OSC_POW_Msk                                                                                 (0x1UL << AON_REG_IO_WDT_REG0X_OSC_POW_Pos)
+
+#define AON_REG_IO_WDT_REG0X_WDT_EN_Pos                                                                                  30U
+#define AON_REG_IO_WDT_REG0X_WDT_EN_Msk                                                                                  (0x1UL << AON_REG_IO_WDT_REG0X_WDT_EN_Pos)
+
+#define AON_REG_IO_WDT_REG0X_WDT_CKOUT_EN_Pos                                                                            31U
+#define AON_REG_IO_WDT_REG0X_WDT_CKOUT_EN_Msk                                                                            (0x1UL << AON_REG_IO_WDT_REG0X_WDT_CKOUT_EN_Pos)
+
+/* 0x45C    0x4000_045c
+    18:0    R       REG_AON_WDT_COMP_FLAG                                       19'h0
+    19      R       WDT2AON_RSTN_FLAG                                           1'b0
+    20      R       RESERVED_2                                                  1'b0
+    24:21   R       RESERVED_1                                                  4'b0
+    28:25   R       RESERVED                                                    4'b0
+    29      R       ENSIMO_FLAG                                                 1'b0
+    30      R       ENLDO_FLAG                                                  1'b0
+    31      R       SIMO_WDT_RST_FLAG                                           1'b0
+ */
+typedef union _AON_REG_IO_WDT_REG1X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t REG_AON_WDT_COMP_FLAG: 19;
+        uint32_t WDT2AON_RSTN_FLAG: 1;
+        uint32_t RESERVED_2: 1;
+        uint32_t RESERVED_1: 4;
+        uint32_t RESERVED: 4;
+        uint32_t ENSIMO_FLAG: 1;
+        uint32_t ENLDO_FLAG: 1;
+        uint32_t SIMO_WDT_RST_FLAG: 1;
+    };
+} AON_REG_IO_WDT_REG1X_TYPE;
+
+/*0x4000_045c AON_REG_IO_WDT_REG1X*/
+#define AON_REG_IO_WDT_REG1X_REG_AON_WDT_COMP_FLAG_Pos                                                                   0U
+#define AON_REG_IO_WDT_REG1X_REG_AON_WDT_COMP_FLAG_Msk                                                                   (0x7FFFFUL << AON_REG_IO_WDT_REG1X_REG_AON_WDT_COMP_FLAG_Pos)
+
+#define AON_REG_IO_WDT_REG1X_WDT2AON_RSTN_FLAG_Pos                                                                       19U
+#define AON_REG_IO_WDT_REG1X_WDT2AON_RSTN_FLAG_Msk                                                                       (0x1UL << AON_REG_IO_WDT_REG1X_WDT2AON_RSTN_FLAG_Pos)
+
+#define AON_REG_IO_WDT_REG1X_RESERVED_2_Pos                                                                              20U
+#define AON_REG_IO_WDT_REG1X_RESERVED_2_Msk                                                                              (0x1UL << AON_REG_IO_WDT_REG1X_RESERVED_2_Pos)
+
+#define AON_REG_IO_WDT_REG1X_RESERVED_1_Pos                                                                              21U
+#define AON_REG_IO_WDT_REG1X_RESERVED_1_Msk                                                                              (0xFUL << AON_REG_IO_WDT_REG1X_RESERVED_1_Pos)
+
+#define AON_REG_IO_WDT_REG1X_RESERVED_Pos                                                                                25U
+#define AON_REG_IO_WDT_REG1X_RESERVED_Msk                                                                                (0xFUL << AON_REG_IO_WDT_REG1X_RESERVED_Pos)
+
+#define AON_REG_IO_WDT_REG1X_ENSIMO_FLAG_Pos                                                                             29U
+#define AON_REG_IO_WDT_REG1X_ENSIMO_FLAG_Msk                                                                             (0x1UL << AON_REG_IO_WDT_REG1X_ENSIMO_FLAG_Pos)
+
+#define AON_REG_IO_WDT_REG1X_ENLDO_FLAG_Pos                                                                              30U
+#define AON_REG_IO_WDT_REG1X_ENLDO_FLAG_Msk                                                                              (0x1UL << AON_REG_IO_WDT_REG1X_ENLDO_FLAG_Pos)
+
+#define AON_REG_IO_WDT_REG1X_SIMO_WDT_RST_FLAG_Pos                                                                       31U
+#define AON_REG_IO_WDT_REG1X_SIMO_WDT_RST_FLAG_Msk                                                                       (0x1UL << AON_REG_IO_WDT_REG1X_SIMO_WDT_RST_FLAG_Pos)
+
+/* 0x464    0x4000_0464
+    0       R/W     DPD_R0                                                      1'b1
+    1       R/W     DPD_R1                                                      1'b0
+    2       R/W     DPD_R2                                                      1'b1
+    3       R/W     DPD_R3                                                      1'b1
+    7:4     R/W     DPD_SEL                                                     4'b0
+    8       R/W     VMAX_SEL_ALWAYS_ON                                          1'b1
+    9       R/W     VMAX_SEL_HIQ                                                1'b0
+    13:10   R/W     RESERVED_1                                                  4'b0
+    14      R/W     DPD_CKOUT_EN                                                1'b1
+    15      R/W     DPD_RCK                                                     1'b0
+    16      R/W     DPD_R4                                                      1'b0
+    17      R/W     DPD_R5                                                      1'b0
+    18      R/W     DPD_R6                                                      1'b0
+    19      R/W     DPD_R7                                                      1'b0
+    20      R/W     DPD_R8                                                      1'b0
+    21      R/W     DPD_R9                                                      1'b0
+    22      R/W     DPD_R10                                                     1'b0
+    23      R/W     DPD_R11                                                     1'b0
+    24      R/W     DPD_R12                                                     1'b0
+    25      R/W     DPD_R13                                                     1'b0
+    26      R/W     DPD_R14                                                     1'b0
+    27      R/W     DPD_R15                                                     1'b0
+    31:28   R/W     RESERVED                                                    4'b0000
+ */
+typedef union _AON_REG_SHIP_DPD_REG0X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t DPD_R0: 1;
+        uint32_t DPD_R1: 1;
+        uint32_t DPD_R2: 1;
+        uint32_t DPD_R3: 1;
+        uint32_t DPD_SEL: 4;
+        uint32_t VMAX_SEL_ALWAYS_ON: 1;
+        uint32_t VMAX_SEL_HIQ: 1;
+        uint32_t RESERVED_1: 4;
+        uint32_t DPD_CKOUT_EN: 1;
+        uint32_t DPD_RCK: 1;
+        uint32_t DPD_R4: 1;
+        uint32_t DPD_R5: 1;
+        uint32_t DPD_R6: 1;
+        uint32_t DPD_R7: 1;
+        uint32_t DPD_R8: 1;
+        uint32_t DPD_R9: 1;
+        uint32_t DPD_R10: 1;
+        uint32_t DPD_R11: 1;
+        uint32_t DPD_R12: 1;
+        uint32_t DPD_R13: 1;
+        uint32_t DPD_R14: 1;
+        uint32_t DPD_R15: 1;
+        uint32_t RESERVED: 4;
+    };
+} AON_REG_SHIP_DPD_REG0X_TYPE;
+
+/*0x4000_0464 AON_REG_SHIP_DPD_REG0X*/
+#define AON_REG_SHIP_DPD_REG0X_DPD_R0_Pos                                                                                0U
+#define AON_REG_SHIP_DPD_REG0X_DPD_R0_Msk                                                                                (0x1UL << AON_REG_SHIP_DPD_REG0X_DPD_R0_Pos)
+
+#define AON_REG_SHIP_DPD_REG0X_DPD_R1_Pos                                                                                1U
+#define AON_REG_SHIP_DPD_REG0X_DPD_R1_Msk                                                                                (0x1UL << AON_REG_SHIP_DPD_REG0X_DPD_R1_Pos)
+
+#define AON_REG_SHIP_DPD_REG0X_DPD_R2_Pos                                                                                2U
+#define AON_REG_SHIP_DPD_REG0X_DPD_R2_Msk                                                                                (0x1UL << AON_REG_SHIP_DPD_REG0X_DPD_R2_Pos)
+
+#define AON_REG_SHIP_DPD_REG0X_DPD_R3_Pos                                                                                3U
+#define AON_REG_SHIP_DPD_REG0X_DPD_R3_Msk                                                                                (0x1UL << AON_REG_SHIP_DPD_REG0X_DPD_R3_Pos)
+
+#define AON_REG_SHIP_DPD_REG0X_DPD_SEL_Pos                                                                               4U
+#define AON_REG_SHIP_DPD_REG0X_DPD_SEL_Msk                                                                               (0xFUL << AON_REG_SHIP_DPD_REG0X_DPD_SEL_Pos)
+
+#define AON_REG_SHIP_DPD_REG0X_VMAX_SEL_ALWAYS_ON_Pos                                                                    8U
+#define AON_REG_SHIP_DPD_REG0X_VMAX_SEL_ALWAYS_ON_Msk                                                                    (0x1UL << AON_REG_SHIP_DPD_REG0X_VMAX_SEL_ALWAYS_ON_Pos)
+
+#define AON_REG_SHIP_DPD_REG0X_VMAX_SEL_HIQ_Pos                                                                          9U
+#define AON_REG_SHIP_DPD_REG0X_VMAX_SEL_HIQ_Msk                                                                          (0x1UL << AON_REG_SHIP_DPD_REG0X_VMAX_SEL_HIQ_Pos)
+
+#define AON_REG_SHIP_DPD_REG0X_RESERVED_1_Pos                                                                            10U
+#define AON_REG_SHIP_DPD_REG0X_RESERVED_1_Msk                                                                            (0xFUL << AON_REG_SHIP_DPD_REG0X_RESERVED_1_Pos)
+
+#define AON_REG_SHIP_DPD_REG0X_DPD_CKOUT_EN_Pos                                                                          14U
+#define AON_REG_SHIP_DPD_REG0X_DPD_CKOUT_EN_Msk                                                                          (0x1UL << AON_REG_SHIP_DPD_REG0X_DPD_CKOUT_EN_Pos)
+
+#define AON_REG_SHIP_DPD_REG0X_DPD_RCK_Pos                                                                               15U
+#define AON_REG_SHIP_DPD_REG0X_DPD_RCK_Msk                                                                               (0x1UL << AON_REG_SHIP_DPD_REG0X_DPD_RCK_Pos)
+
+#define AON_REG_SHIP_DPD_REG0X_DPD_R4_Pos                                                                                16U
+#define AON_REG_SHIP_DPD_REG0X_DPD_R4_Msk                                                                                (0x1UL << AON_REG_SHIP_DPD_REG0X_DPD_R4_Pos)
+
+#define AON_REG_SHIP_DPD_REG0X_DPD_R5_Pos                                                                                17U
+#define AON_REG_SHIP_DPD_REG0X_DPD_R5_Msk                                                                                (0x1UL << AON_REG_SHIP_DPD_REG0X_DPD_R5_Pos)
+
+#define AON_REG_SHIP_DPD_REG0X_DPD_R6_Pos                                                                                18U
+#define AON_REG_SHIP_DPD_REG0X_DPD_R6_Msk                                                                                (0x1UL << AON_REG_SHIP_DPD_REG0X_DPD_R6_Pos)
+
+#define AON_REG_SHIP_DPD_REG0X_DPD_R7_Pos                                                                                19U
+#define AON_REG_SHIP_DPD_REG0X_DPD_R7_Msk                                                                                (0x1UL << AON_REG_SHIP_DPD_REG0X_DPD_R7_Pos)
+
+#define AON_REG_SHIP_DPD_REG0X_DPD_R8_Pos                                                                                20U
+#define AON_REG_SHIP_DPD_REG0X_DPD_R8_Msk                                                                                (0x1UL << AON_REG_SHIP_DPD_REG0X_DPD_R8_Pos)
+
+#define AON_REG_SHIP_DPD_REG0X_DPD_R9_Pos                                                                                21U
+#define AON_REG_SHIP_DPD_REG0X_DPD_R9_Msk                                                                                (0x1UL << AON_REG_SHIP_DPD_REG0X_DPD_R9_Pos)
+
+#define AON_REG_SHIP_DPD_REG0X_DPD_R10_Pos                                                                               22U
+#define AON_REG_SHIP_DPD_REG0X_DPD_R10_Msk                                                                               (0x1UL << AON_REG_SHIP_DPD_REG0X_DPD_R10_Pos)
+
+#define AON_REG_SHIP_DPD_REG0X_DPD_R11_Pos                                                                               23U
+#define AON_REG_SHIP_DPD_REG0X_DPD_R11_Msk                                                                               (0x1UL << AON_REG_SHIP_DPD_REG0X_DPD_R11_Pos)
+
+#define AON_REG_SHIP_DPD_REG0X_DPD_R12_Pos                                                                               24U
+#define AON_REG_SHIP_DPD_REG0X_DPD_R12_Msk                                                                               (0x1UL << AON_REG_SHIP_DPD_REG0X_DPD_R12_Pos)
+
+#define AON_REG_SHIP_DPD_REG0X_DPD_R13_Pos                                                                               25U
+#define AON_REG_SHIP_DPD_REG0X_DPD_R13_Msk                                                                               (0x1UL << AON_REG_SHIP_DPD_REG0X_DPD_R13_Pos)
+
+#define AON_REG_SHIP_DPD_REG0X_DPD_R14_Pos                                                                               26U
+#define AON_REG_SHIP_DPD_REG0X_DPD_R14_Msk                                                                               (0x1UL << AON_REG_SHIP_DPD_REG0X_DPD_R14_Pos)
+
+#define AON_REG_SHIP_DPD_REG0X_DPD_R15_Pos                                                                               27U
+#define AON_REG_SHIP_DPD_REG0X_DPD_R15_Msk                                                                               (0x1UL << AON_REG_SHIP_DPD_REG0X_DPD_R15_Pos)
+
+#define AON_REG_SHIP_DPD_REG0X_RESERVED_Pos                                                                              28U
+#define AON_REG_SHIP_DPD_REG0X_RESERVED_Msk                                                                              (0xFUL << AON_REG_SHIP_DPD_REG0X_RESERVED_Pos)
+
+/* 0x468    0x4000_0468
+    0       R       FLAG_DPD_R0                                                 1'b0
+    1       R       FLAG_DPD_R1                                                 1'b0
+    2       R       FLAG_DPD_R2                                                 1'b0
+    3       R       FLAG_DPD_R3                                                 1'b0
+    7:4     R       FLAG_DPD_SEL                                                4'b0000
+    8       R       FLAG_VMAX_SEL_ALWAYS_ON                                     1'b0
+    9       R       FLAG_VMAX_SEL_HIQ                                           1'b0
+    10      R       FLAG_DPD_R10_RSV                                            1'b0
+    11      R       FLAG_DPD_R11_RSV                                            1'b0
+    12      R       FLAG_DPD_R4                                                 1'b0
+    13      R       FLAG_DPD_R5                                                 1'b0
+    14      R       FLAG_DPD_R6                                                 1'b0
+    15      R       FLAG_DPD_R7                                                 1'b0
+    16      R       FLAG_DPD_R8                                                 1'b0
+    17      R       FLAG_DPD_R9                                                 1'b0
+    18      R       FLAG_DPD_R10                                                1'b0
+    19      R       FLAG_DPD_R11                                                1'b0
+    20      R       FLAG_DPD_R12                                                1'b0
+    21      R       FLAG_DPD_R13                                                1'b0
+    22      R       FLAG_DPD_R14                                                1'b0
+    23      R       FLAG_DPD_R15                                                1'b0
+    31:24   R       RESERVED                                                    8'h0
+ */
+typedef union _AON_C_KOUT0X_DPD_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t FLAG_DPD_R0: 1;
+        uint32_t FLAG_DPD_R1: 1;
+        uint32_t FLAG_DPD_R2: 1;
+        uint32_t FLAG_DPD_R3: 1;
+        uint32_t FLAG_DPD_SEL: 4;
+        uint32_t FLAG_VMAX_SEL_ALWAYS_ON: 1;
+        uint32_t FLAG_VMAX_SEL_HIQ: 1;
+        uint32_t FLAG_DPD_R10_RSV: 1;
+        uint32_t FLAG_DPD_R11_RSV: 1;
+        uint32_t FLAG_DPD_R4: 1;
+        uint32_t FLAG_DPD_R5: 1;
+        uint32_t FLAG_DPD_R6: 1;
+        uint32_t FLAG_DPD_R7: 1;
+        uint32_t FLAG_DPD_R8: 1;
+        uint32_t FLAG_DPD_R9: 1;
+        uint32_t FLAG_DPD_R10: 1;
+        uint32_t FLAG_DPD_R11: 1;
+        uint32_t FLAG_DPD_R12: 1;
+        uint32_t FLAG_DPD_R13: 1;
+        uint32_t FLAG_DPD_R14: 1;
+        uint32_t FLAG_DPD_R15: 1;
+        uint32_t RESERVED: 8;
+    };
+} AON_C_KOUT0X_DPD_TYPE;
+
+/*0x4000_0468 AON_C_KOUT0X_DPD*/
+#define AON_C_KOUT0X_DPD_FLAG_DPD_R0_Pos                                                                                 0U
+#define AON_C_KOUT0X_DPD_FLAG_DPD_R0_Msk                                                                                 (0x1UL << AON_C_KOUT0X_DPD_FLAG_DPD_R0_Pos)
+
+#define AON_C_KOUT0X_DPD_FLAG_DPD_R1_Pos                                                                                 1U
+#define AON_C_KOUT0X_DPD_FLAG_DPD_R1_Msk                                                                                 (0x1UL << AON_C_KOUT0X_DPD_FLAG_DPD_R1_Pos)
+
+#define AON_C_KOUT0X_DPD_FLAG_DPD_R2_Pos                                                                                 2U
+#define AON_C_KOUT0X_DPD_FLAG_DPD_R2_Msk                                                                                 (0x1UL << AON_C_KOUT0X_DPD_FLAG_DPD_R2_Pos)
+
+#define AON_C_KOUT0X_DPD_FLAG_DPD_R3_Pos                                                                                 3U
+#define AON_C_KOUT0X_DPD_FLAG_DPD_R3_Msk                                                                                 (0x1UL << AON_C_KOUT0X_DPD_FLAG_DPD_R3_Pos)
+
+#define AON_C_KOUT0X_DPD_FLAG_DPD_SEL_Pos                                                                                4U
+#define AON_C_KOUT0X_DPD_FLAG_DPD_SEL_Msk                                                                                (0xFUL << AON_C_KOUT0X_DPD_FLAG_DPD_SEL_Pos)
+
+#define AON_C_KOUT0X_DPD_FLAG_VMAX_SEL_ALWAYS_ON_Pos                                                                     8U
+#define AON_C_KOUT0X_DPD_FLAG_VMAX_SEL_ALWAYS_ON_Msk                                                                     (0x1UL << AON_C_KOUT0X_DPD_FLAG_VMAX_SEL_ALWAYS_ON_Pos)
+
+#define AON_C_KOUT0X_DPD_FLAG_VMAX_SEL_HIQ_Pos                                                                           9U
+#define AON_C_KOUT0X_DPD_FLAG_VMAX_SEL_HIQ_Msk                                                                           (0x1UL << AON_C_KOUT0X_DPD_FLAG_VMAX_SEL_HIQ_Pos)
+
+#define AON_C_KOUT0X_DPD_FLAG_DPD_R10_RSV_Pos                                                                            10U
+#define AON_C_KOUT0X_DPD_FLAG_DPD_R10_RSV_Msk                                                                            (0x1UL << AON_C_KOUT0X_DPD_FLAG_DPD_R10_RSV_Pos)
+
+#define AON_C_KOUT0X_DPD_FLAG_DPD_R11_RSV_Pos                                                                            11U
+#define AON_C_KOUT0X_DPD_FLAG_DPD_R11_RSV_Msk                                                                            (0x1UL << AON_C_KOUT0X_DPD_FLAG_DPD_R11_RSV_Pos)
+
+#define AON_C_KOUT0X_DPD_FLAG_DPD_R4_Pos                                                                                 12U
+#define AON_C_KOUT0X_DPD_FLAG_DPD_R4_Msk                                                                                 (0x1UL << AON_C_KOUT0X_DPD_FLAG_DPD_R4_Pos)
+
+#define AON_C_KOUT0X_DPD_FLAG_DPD_R5_Pos                                                                                 13U
+#define AON_C_KOUT0X_DPD_FLAG_DPD_R5_Msk                                                                                 (0x1UL << AON_C_KOUT0X_DPD_FLAG_DPD_R5_Pos)
+
+#define AON_C_KOUT0X_DPD_FLAG_DPD_R6_Pos                                                                                 14U
+#define AON_C_KOUT0X_DPD_FLAG_DPD_R6_Msk                                                                                 (0x1UL << AON_C_KOUT0X_DPD_FLAG_DPD_R6_Pos)
+
+#define AON_C_KOUT0X_DPD_FLAG_DPD_R7_Pos                                                                                 15U
+#define AON_C_KOUT0X_DPD_FLAG_DPD_R7_Msk                                                                                 (0x1UL << AON_C_KOUT0X_DPD_FLAG_DPD_R7_Pos)
+
+#define AON_C_KOUT0X_DPD_FLAG_DPD_R8_Pos                                                                                 16U
+#define AON_C_KOUT0X_DPD_FLAG_DPD_R8_Msk                                                                                 (0x1UL << AON_C_KOUT0X_DPD_FLAG_DPD_R8_Pos)
+
+#define AON_C_KOUT0X_DPD_FLAG_DPD_R9_Pos                                                                                 17U
+#define AON_C_KOUT0X_DPD_FLAG_DPD_R9_Msk                                                                                 (0x1UL << AON_C_KOUT0X_DPD_FLAG_DPD_R9_Pos)
+
+#define AON_C_KOUT0X_DPD_FLAG_DPD_R10_Pos                                                                                18U
+#define AON_C_KOUT0X_DPD_FLAG_DPD_R10_Msk                                                                                (0x1UL << AON_C_KOUT0X_DPD_FLAG_DPD_R10_Pos)
+
+#define AON_C_KOUT0X_DPD_FLAG_DPD_R11_Pos                                                                                19U
+#define AON_C_KOUT0X_DPD_FLAG_DPD_R11_Msk                                                                                (0x1UL << AON_C_KOUT0X_DPD_FLAG_DPD_R11_Pos)
+
+#define AON_C_KOUT0X_DPD_FLAG_DPD_R12_Pos                                                                                20U
+#define AON_C_KOUT0X_DPD_FLAG_DPD_R12_Msk                                                                                (0x1UL << AON_C_KOUT0X_DPD_FLAG_DPD_R12_Pos)
+
+#define AON_C_KOUT0X_DPD_FLAG_DPD_R13_Pos                                                                                21U
+#define AON_C_KOUT0X_DPD_FLAG_DPD_R13_Msk                                                                                (0x1UL << AON_C_KOUT0X_DPD_FLAG_DPD_R13_Pos)
+
+#define AON_C_KOUT0X_DPD_FLAG_DPD_R14_Pos                                                                                22U
+#define AON_C_KOUT0X_DPD_FLAG_DPD_R14_Msk                                                                                (0x1UL << AON_C_KOUT0X_DPD_FLAG_DPD_R14_Pos)
+
+#define AON_C_KOUT0X_DPD_FLAG_DPD_R15_Pos                                                                                23U
+#define AON_C_KOUT0X_DPD_FLAG_DPD_R15_Msk                                                                                (0x1UL << AON_C_KOUT0X_DPD_FLAG_DPD_R15_Pos)
+
+#define AON_C_KOUT0X_DPD_RESERVED_Pos                                                                                    24U
+#define AON_C_KOUT0X_DPD_RESERVED_Msk                                                                                    (0xFFUL << AON_C_KOUT0X_DPD_RESERVED_Pos)
+
+/* 0x488    0x4000_0488
+    0       R/W     EN_PBG_RC                                                   1'b1
+    5:1     R/W     SEL_VREF_LDO_32K                                            5'b01111
+    10:6    R/W     SEL_VREF_VDDCORE_LQ                                         5'b01110
+    15:11   R/W     SEL_VREF_HV25_LQ                                            5'b01111
+    18:16   R/W     TUNE_BG_REF1                                                3'b101
+    19      R/W     REG1X_MBIAS_DUMMY0                                          1'b0
+    25:20   R/W     SEL_VREF_LPC_L                                              6'b011100
+    31:26   R/W     SEL_VREF_LPC_H                                              6'b011101
+ */
+typedef union _AON_REG_MBIAS_REG0X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t EN_PBG_RC: 1;
+        uint32_t SEL_VREF_LDO_32K: 5;
+        uint32_t SEL_VREF_VDDCORE_LQ: 5;
+        uint32_t SEL_VREF_HV25_LQ: 5;
+        uint32_t TUNE_BG_REF1: 3;
+        uint32_t REG1X_MBIAS_DUMMY0: 1;
+        uint32_t SEL_VREF_LPC_L: 6;
+        uint32_t SEL_VREF_LPC_H: 6;
+    };
+} AON_REG_MBIAS_REG0X_TYPE;
+
+/*0x4000_0488 AON_REG_MBIAS_REG0X*/
+#define AON_REG_MBIAS_REG0X_EN_PBG_RC_Pos                                                                                0U
+#define AON_REG_MBIAS_REG0X_EN_PBG_RC_Msk                                                                                (0x1UL << AON_REG_MBIAS_REG0X_EN_PBG_RC_Pos)
+
+#define AON_REG_MBIAS_REG0X_SEL_VREF_LDO_32K_Pos                                                                         1U
+#define AON_REG_MBIAS_REG0X_SEL_VREF_LDO_32K_Msk                                                                         (0x1FUL << AON_REG_MBIAS_REG0X_SEL_VREF_LDO_32K_Pos)
+
+#define AON_REG_MBIAS_REG0X_SEL_VREF_VDDCORE_LQ_Pos                                                                      6U
+#define AON_REG_MBIAS_REG0X_SEL_VREF_VDDCORE_LQ_Msk                                                                      (0x1FUL << AON_REG_MBIAS_REG0X_SEL_VREF_VDDCORE_LQ_Pos)
+
+#define AON_REG_MBIAS_REG0X_SEL_VREF_HV25_LQ_Pos                                                                         11U
+#define AON_REG_MBIAS_REG0X_SEL_VREF_HV25_LQ_Msk                                                                         (0x1FUL << AON_REG_MBIAS_REG0X_SEL_VREF_HV25_LQ_Pos)
+
+#define AON_REG_MBIAS_REG0X_TUNE_BG_REF1_Pos                                                                             16U
+#define AON_REG_MBIAS_REG0X_TUNE_BG_REF1_Msk                                                                             (0x7UL << AON_REG_MBIAS_REG0X_TUNE_BG_REF1_Pos)
+
+#define AON_REG_MBIAS_REG0X_REG1X_MBIAS_DUMMY0_Pos                                                                       19U
+#define AON_REG_MBIAS_REG0X_REG1X_MBIAS_DUMMY0_Msk                                                                       (0x1UL << AON_REG_MBIAS_REG0X_REG1X_MBIAS_DUMMY0_Pos)
+
+#define AON_REG_MBIAS_REG0X_SEL_VREF_LPC_L_Pos                                                                           20U
+#define AON_REG_MBIAS_REG0X_SEL_VREF_LPC_L_Msk                                                                           (0x3FUL << AON_REG_MBIAS_REG0X_SEL_VREF_LPC_L_Pos)
+
+#define AON_REG_MBIAS_REG0X_SEL_VREF_LPC_H_Pos                                                                           26U
+#define AON_REG_MBIAS_REG0X_SEL_VREF_LPC_H_Msk                                                                           (0x3FUL << AON_REG_MBIAS_REG0X_SEL_VREF_LPC_H_Pos)
+
+/* 0x48C    0x4000_048c
+    0       R/W     EN_BIAS_1UA                                                 1'b0
+    5:1     R       TUNE_VREFSS_VDDPA_HQ                                        5'b00000
+    10:6    R       TUNE_VREFSS_HV18_HQ                                         5'b00000
+    15:11   R/W     SEL_VREF_HV25_HQ                                            5'b01111
+    16      R/W     EN_BIAS_10UA                                                1'b0
+    17      R/W     POW_VDDCORE_DET                                             1'b0
+    18      R/W     POW_VANA_DET                                                1'b0
+    19      R/W     POW_VDDANA_DET                                              1'b1
+    20      R/W     POW_VDDPA_DET                                               1'b0
+    21      R/W     POW_HV18_DET                                                1'b0
+    26:22   R/W     TUNE_VREFSS_VDDCORE_HQ                                      5'b11111
+    31:27   R/W     SEL_VREF_VDDPA_HQ2                                          5'b11000
+ */
+typedef union _AON_REG_MBIAS_REG1X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t EN_BIAS_1UA: 1;
+        uint32_t TUNE_VREFSS_VDDPA_HQ: 5;
+        uint32_t TUNE_VREFSS_HV18_HQ: 5;
+        uint32_t SEL_VREF_HV25_HQ: 5;
+        uint32_t EN_BIAS_10UA: 1;
+        uint32_t POW_VDDCORE_DET: 1;
+        uint32_t POW_VANA_DET: 1;
+        uint32_t POW_VDDANA_DET: 1;
+        uint32_t POW_VDDPA_DET: 1;
+        uint32_t POW_HV18_DET: 1;
+        uint32_t TUNE_VREFSS_VDDCORE_HQ: 5;
+        uint32_t SEL_VREF_VDDPA_HQ2: 5;
+    };
+} AON_REG_MBIAS_REG1X_TYPE;
+
+/*0x4000_048c AON_REG_MBIAS_REG1X*/
+#define AON_REG_MBIAS_REG1X_EN_BIAS_1UA_Pos                                                                              0U
+#define AON_REG_MBIAS_REG1X_EN_BIAS_1UA_Msk                                                                              (0x1UL << AON_REG_MBIAS_REG1X_EN_BIAS_1UA_Pos)
+
+#define AON_REG_MBIAS_REG1X_TUNE_VREFSS_VDDPA_HQ_Pos                                                                     1U
+#define AON_REG_MBIAS_REG1X_TUNE_VREFSS_VDDPA_HQ_Msk                                                                     (0x1FUL << AON_REG_MBIAS_REG1X_TUNE_VREFSS_VDDPA_HQ_Pos)
+
+#define AON_REG_MBIAS_REG1X_TUNE_VREFSS_HV18_HQ_Pos                                                                      6U
+#define AON_REG_MBIAS_REG1X_TUNE_VREFSS_HV18_HQ_Msk                                                                      (0x1FUL << AON_REG_MBIAS_REG1X_TUNE_VREFSS_HV18_HQ_Pos)
+
+#define AON_REG_MBIAS_REG1X_SEL_VREF_HV25_HQ_Pos                                                                         11U
+#define AON_REG_MBIAS_REG1X_SEL_VREF_HV25_HQ_Msk                                                                         (0x1FUL << AON_REG_MBIAS_REG1X_SEL_VREF_HV25_HQ_Pos)
+
+#define AON_REG_MBIAS_REG1X_EN_BIAS_10UA_Pos                                                                             16U
+#define AON_REG_MBIAS_REG1X_EN_BIAS_10UA_Msk                                                                             (0x1UL << AON_REG_MBIAS_REG1X_EN_BIAS_10UA_Pos)
+
+#define AON_REG_MBIAS_REG1X_POW_VDDCORE_DET_Pos                                                                          17U
+#define AON_REG_MBIAS_REG1X_POW_VDDCORE_DET_Msk                                                                          (0x1UL << AON_REG_MBIAS_REG1X_POW_VDDCORE_DET_Pos)
+
+#define AON_REG_MBIAS_REG1X_POW_VANA_DET_Pos                                                                             18U
+#define AON_REG_MBIAS_REG1X_POW_VANA_DET_Msk                                                                             (0x1UL << AON_REG_MBIAS_REG1X_POW_VANA_DET_Pos)
+
+#define AON_REG_MBIAS_REG1X_POW_VDDANA_DET_Pos                                                                           19U
+#define AON_REG_MBIAS_REG1X_POW_VDDANA_DET_Msk                                                                           (0x1UL << AON_REG_MBIAS_REG1X_POW_VDDANA_DET_Pos)
+
+#define AON_REG_MBIAS_REG1X_POW_VDDPA_DET_Pos                                                                            20U
+#define AON_REG_MBIAS_REG1X_POW_VDDPA_DET_Msk                                                                            (0x1UL << AON_REG_MBIAS_REG1X_POW_VDDPA_DET_Pos)
+
+#define AON_REG_MBIAS_REG1X_POW_HV18_DET_Pos                                                                             21U
+#define AON_REG_MBIAS_REG1X_POW_HV18_DET_Msk                                                                             (0x1UL << AON_REG_MBIAS_REG1X_POW_HV18_DET_Pos)
+
+#define AON_REG_MBIAS_REG1X_TUNE_VREFSS_VDDCORE_HQ_Pos                                                                   22U
+#define AON_REG_MBIAS_REG1X_TUNE_VREFSS_VDDCORE_HQ_Msk                                                                   (0x1FUL << AON_REG_MBIAS_REG1X_TUNE_VREFSS_VDDCORE_HQ_Pos)
+
+#define AON_REG_MBIAS_REG1X_SEL_VREF_VDDPA_HQ2_Pos                                                                       27U
+#define AON_REG_MBIAS_REG1X_SEL_VREF_VDDPA_HQ2_Msk                                                                       (0x1FUL << AON_REG_MBIAS_REG1X_SEL_VREF_VDDPA_HQ2_Pos)
+
+/* 0x490    0x4000_0490
+    2:0     R/W     SEL_BG_R2                                                   3'b100
+    3       R/W     EN_VDDCORE_DET_V33                                          1'b0
+    6:4     R/W     SEL_VDDPA_VR_L                                              3'b100
+    9:7     R/W     SEL_VDDPA_VR_H                                              3'b100
+    12:10   R/W     SEL_HV18_VR_L                                               3'b100
+    15:13   R/W     SEL_HV18_VR_H                                               3'b100
+    18:16   R/W     TUNE_BG_REF2                                                3'b101
+    19      R/W     REG5X_MBIAS_DUMMY0                                          1'b0
+    22:20   R/W     SEL_VANA_VR_L                                               3'b010
+    25:23   R/W     SEL_VANA_VR_H                                               3'b101
+    28:26   R/W     SEL_VDDANA_VR_L                                             3'b100
+    31:29   R/W     SEL_VDDANA_VR_H                                             3'b101
+ */
+typedef union _AON_REG_MBIAS_REG2X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t SEL_BG_R2: 3;
+        uint32_t EN_VDDCORE_DET_V33: 1;
+        uint32_t SEL_VDDPA_VR_L: 3;
+        uint32_t SEL_VDDPA_VR_H: 3;
+        uint32_t SEL_HV18_VR_L: 3;
+        uint32_t SEL_HV18_VR_H: 3;
+        uint32_t TUNE_BG_REF2: 3;
+        uint32_t REG5X_MBIAS_DUMMY0: 1;
+        uint32_t SEL_VANA_VR_L: 3;
+        uint32_t SEL_VANA_VR_H: 3;
+        uint32_t SEL_VDDANA_VR_L: 3;
+        uint32_t SEL_VDDANA_VR_H: 3;
+    };
+} AON_REG_MBIAS_REG2X_TYPE;
+
+/*0x4000_0490 AON_REG_MBIAS_REG2X*/
+#define AON_REG_MBIAS_REG2X_SEL_BG_R2_Pos                                                                                0U
+#define AON_REG_MBIAS_REG2X_SEL_BG_R2_Msk                                                                                (0x7UL << AON_REG_MBIAS_REG2X_SEL_BG_R2_Pos)
+
+#define AON_REG_MBIAS_REG2X_EN_VDDCORE_DET_V33_Pos                                                                       3U
+#define AON_REG_MBIAS_REG2X_EN_VDDCORE_DET_V33_Msk                                                                       (0x1UL << AON_REG_MBIAS_REG2X_EN_VDDCORE_DET_V33_Pos)
+
+#define AON_REG_MBIAS_REG2X_SEL_VDDPA_VR_L_Pos                                                                           4U
+#define AON_REG_MBIAS_REG2X_SEL_VDDPA_VR_L_Msk                                                                           (0x7UL << AON_REG_MBIAS_REG2X_SEL_VDDPA_VR_L_Pos)
+
+#define AON_REG_MBIAS_REG2X_SEL_VDDPA_VR_H_Pos                                                                           7U
+#define AON_REG_MBIAS_REG2X_SEL_VDDPA_VR_H_Msk                                                                           (0x7UL << AON_REG_MBIAS_REG2X_SEL_VDDPA_VR_H_Pos)
+
+#define AON_REG_MBIAS_REG2X_SEL_HV18_VR_L_Pos                                                                            10U
+#define AON_REG_MBIAS_REG2X_SEL_HV18_VR_L_Msk                                                                            (0x7UL << AON_REG_MBIAS_REG2X_SEL_HV18_VR_L_Pos)
+
+#define AON_REG_MBIAS_REG2X_SEL_HV18_VR_H_Pos                                                                            13U
+#define AON_REG_MBIAS_REG2X_SEL_HV18_VR_H_Msk                                                                            (0x7UL << AON_REG_MBIAS_REG2X_SEL_HV18_VR_H_Pos)
+
+#define AON_REG_MBIAS_REG2X_TUNE_BG_REF2_Pos                                                                             16U
+#define AON_REG_MBIAS_REG2X_TUNE_BG_REF2_Msk                                                                             (0x7UL << AON_REG_MBIAS_REG2X_TUNE_BG_REF2_Pos)
+
+#define AON_REG_MBIAS_REG2X_REG5X_MBIAS_DUMMY0_Pos                                                                       19U
+#define AON_REG_MBIAS_REG2X_REG5X_MBIAS_DUMMY0_Msk                                                                       (0x1UL << AON_REG_MBIAS_REG2X_REG5X_MBIAS_DUMMY0_Pos)
+
+#define AON_REG_MBIAS_REG2X_SEL_VANA_VR_L_Pos                                                                            20U
+#define AON_REG_MBIAS_REG2X_SEL_VANA_VR_L_Msk                                                                            (0x7UL << AON_REG_MBIAS_REG2X_SEL_VANA_VR_L_Pos)
+
+#define AON_REG_MBIAS_REG2X_SEL_VANA_VR_H_Pos                                                                            23U
+#define AON_REG_MBIAS_REG2X_SEL_VANA_VR_H_Msk                                                                            (0x7UL << AON_REG_MBIAS_REG2X_SEL_VANA_VR_H_Pos)
+
+#define AON_REG_MBIAS_REG2X_SEL_VDDANA_VR_L_Pos                                                                          26U
+#define AON_REG_MBIAS_REG2X_SEL_VDDANA_VR_L_Msk                                                                          (0x7UL << AON_REG_MBIAS_REG2X_SEL_VDDANA_VR_L_Pos)
+
+#define AON_REG_MBIAS_REG2X_SEL_VDDANA_VR_H_Pos                                                                          29U
+#define AON_REG_MBIAS_REG2X_SEL_VDDANA_VR_H_Msk                                                                          (0x7UL << AON_REG_MBIAS_REG2X_SEL_VDDANA_VR_H_Pos)
+
+/* 0x494    0x4000_0494
+    2:0     R/W     TUNE_1U_RREF                                                3'b101
+    3       R/W     REG6X_MBIAS_DUMMY0                                          1'b0
+    8:4     R/W     SEL_VREF_VDDANA_LQ                                          5'b10011
+    9       R/W     EN_VREF_EFLASH                                              1'b0
+    12:10   R/W     SEL_VDDCORE_VR_L                                            3'b100
+    15:13   R/W     SEL_VDDCORE_VR_H                                            3'b101
+    31:16   R/W     REG7X_MBIAS_DUMMY0                                          16'b0000000000000000
+ */
+typedef union _AON_REG_MBIAS_REG3X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t TUNE_1U_RREF: 3;
+        uint32_t REG6X_MBIAS_DUMMY0: 1;
+        uint32_t SEL_VREF_VDDANA_LQ: 5;
+        uint32_t EN_VREF_EFLASH: 1;
+        uint32_t SEL_VDDCORE_VR_L: 3;
+        uint32_t SEL_VDDCORE_VR_H: 3;
+        uint32_t REG7X_MBIAS_DUMMY0: 16;
+    };
+} AON_REG_MBIAS_REG3X_TYPE;
+
+/*0x4000_0494 AON_REG_MBIAS_REG3X*/
+#define AON_REG_MBIAS_REG3X_TUNE_1U_RREF_Pos                                                                             0U
+#define AON_REG_MBIAS_REG3X_TUNE_1U_RREF_Msk                                                                             (0x7UL << AON_REG_MBIAS_REG3X_TUNE_1U_RREF_Pos)
+
+#define AON_REG_MBIAS_REG3X_REG6X_MBIAS_DUMMY0_Pos                                                                       3U
+#define AON_REG_MBIAS_REG3X_REG6X_MBIAS_DUMMY0_Msk                                                                       (0x1UL << AON_REG_MBIAS_REG3X_REG6X_MBIAS_DUMMY0_Pos)
+
+#define AON_REG_MBIAS_REG3X_SEL_VREF_VDDANA_LQ_Pos                                                                       4U
+#define AON_REG_MBIAS_REG3X_SEL_VREF_VDDANA_LQ_Msk                                                                       (0x1FUL << AON_REG_MBIAS_REG3X_SEL_VREF_VDDANA_LQ_Pos)
+
+#define AON_REG_MBIAS_REG3X_EN_VREF_EFLASH_Pos                                                                           9U
+#define AON_REG_MBIAS_REG3X_EN_VREF_EFLASH_Msk                                                                           (0x1UL << AON_REG_MBIAS_REG3X_EN_VREF_EFLASH_Pos)
+
+#define AON_REG_MBIAS_REG3X_SEL_VDDCORE_VR_L_Pos                                                                         10U
+#define AON_REG_MBIAS_REG3X_SEL_VDDCORE_VR_L_Msk                                                                         (0x7UL << AON_REG_MBIAS_REG3X_SEL_VDDCORE_VR_L_Pos)
+
+#define AON_REG_MBIAS_REG3X_SEL_VDDCORE_VR_H_Pos                                                                         13U
+#define AON_REG_MBIAS_REG3X_SEL_VDDCORE_VR_H_Msk                                                                         (0x7UL << AON_REG_MBIAS_REG3X_SEL_VDDCORE_VR_H_Pos)
+
+#define AON_REG_MBIAS_REG3X_REG7X_MBIAS_DUMMY0_Pos                                                                       16U
+#define AON_REG_MBIAS_REG3X_REG7X_MBIAS_DUMMY0_Msk                                                                       (0xFFFFUL << AON_REG_MBIAS_REG3X_REG7X_MBIAS_DUMMY0_Pos)
+
+/* 0x498    0x4000_0498
+    2:0     R       CKOUT0X_MBIAS_DUMMY0                                        3'b000
+    3       R       PORB_VOUT2                                                  1'b0
+    4       R       IPTAT_OK_DELAY                                              1'b0
+    5       R       IPTAT_OK                                                    1'b0
+    6       R       ENSIMO                                                      1'b0
+    7       R       PORB_HV                                                     1'b0
+    8       R       VDDCORE_DET                                                 1'b0
+    9       R       VANA_DET                                                    1'b0
+    10      R       VDDANA_DET                                                  1'b0
+    11      R       VDDPA_DET                                                   1'b0
+    12      R       HV18_DET                                                    1'b0
+    13      R       FPORB_VOUT1                                                 1'b0
+    14      R       PORB_VOUT1_DELAY                                            1'b0
+    15      R       PORB_VOUT1                                                  1'b0
+    31:16   R       CKOUT1X_MBIAS_DUMMY0                                        16'b0000000000000000
+ */
+typedef union _AON_C_KOUT0X_MBIAS_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t CKOUT0X_MBIAS_DUMMY0: 3;
+        uint32_t PORB_VOUT2: 1;
+        uint32_t IPTAT_OK_DELAY: 1;
+        uint32_t IPTAT_OK: 1;
+        uint32_t ENSIMO: 1;
+        uint32_t PORB_HV: 1;
+        uint32_t VDDCORE_DET: 1;
+        uint32_t VANA_DET: 1;
+        uint32_t VDDANA_DET: 1;
+        uint32_t VDDPA_DET: 1;
+        uint32_t HV18_DET: 1;
+        uint32_t FPORB_VOUT1: 1;
+        uint32_t PORB_VOUT1_DELAY: 1;
+        uint32_t PORB_VOUT1: 1;
+        uint32_t CKOUT1X_MBIAS_DUMMY0: 16;
+    };
+} AON_C_KOUT0X_MBIAS_TYPE;
+
+/*0x4000_0498 AON_C_KOUT0X_MBIAS*/
+#define AON_C_KOUT0X_MBIAS_CKOUT0X_MBIAS_DUMMY0_Pos                                                                      0U
+#define AON_C_KOUT0X_MBIAS_CKOUT0X_MBIAS_DUMMY0_Msk                                                                      (0x7UL << AON_C_KOUT0X_MBIAS_CKOUT0X_MBIAS_DUMMY0_Pos)
+
+#define AON_C_KOUT0X_MBIAS_PORB_VOUT2_Pos                                                                                3U
+#define AON_C_KOUT0X_MBIAS_PORB_VOUT2_Msk                                                                                (0x1UL << AON_C_KOUT0X_MBIAS_PORB_VOUT2_Pos)
+
+#define AON_C_KOUT0X_MBIAS_IPTAT_OK_DELAY_Pos                                                                            4U
+#define AON_C_KOUT0X_MBIAS_IPTAT_OK_DELAY_Msk                                                                            (0x1UL << AON_C_KOUT0X_MBIAS_IPTAT_OK_DELAY_Pos)
+
+#define AON_C_KOUT0X_MBIAS_IPTAT_OK_Pos                                                                                  5U
+#define AON_C_KOUT0X_MBIAS_IPTAT_OK_Msk                                                                                  (0x1UL << AON_C_KOUT0X_MBIAS_IPTAT_OK_Pos)
+
+#define AON_C_KOUT0X_MBIAS_ENSIMO_Pos                                                                                    6U
+#define AON_C_KOUT0X_MBIAS_ENSIMO_Msk                                                                                    (0x1UL << AON_C_KOUT0X_MBIAS_ENSIMO_Pos)
+
+#define AON_C_KOUT0X_MBIAS_PORB_HV_Pos                                                                                   7U
+#define AON_C_KOUT0X_MBIAS_PORB_HV_Msk                                                                                   (0x1UL << AON_C_KOUT0X_MBIAS_PORB_HV_Pos)
+
+#define AON_C_KOUT0X_MBIAS_VDDCORE_DET_Pos                                                                               8U
+#define AON_C_KOUT0X_MBIAS_VDDCORE_DET_Msk                                                                               (0x1UL << AON_C_KOUT0X_MBIAS_VDDCORE_DET_Pos)
+
+#define AON_C_KOUT0X_MBIAS_VANA_DET_Pos                                                                                  9U
+#define AON_C_KOUT0X_MBIAS_VANA_DET_Msk                                                                                  (0x1UL << AON_C_KOUT0X_MBIAS_VANA_DET_Pos)
+
+#define AON_C_KOUT0X_MBIAS_VDDANA_DET_Pos                                                                                10U
+#define AON_C_KOUT0X_MBIAS_VDDANA_DET_Msk                                                                                (0x1UL << AON_C_KOUT0X_MBIAS_VDDANA_DET_Pos)
+
+#define AON_C_KOUT0X_MBIAS_VDDPA_DET_Pos                                                                                 11U
+#define AON_C_KOUT0X_MBIAS_VDDPA_DET_Msk                                                                                 (0x1UL << AON_C_KOUT0X_MBIAS_VDDPA_DET_Pos)
+
+#define AON_C_KOUT0X_MBIAS_HV18_DET_Pos                                                                                  12U
+#define AON_C_KOUT0X_MBIAS_HV18_DET_Msk                                                                                  (0x1UL << AON_C_KOUT0X_MBIAS_HV18_DET_Pos)
+
+#define AON_C_KOUT0X_MBIAS_FPORB_VOUT1_Pos                                                                               13U
+#define AON_C_KOUT0X_MBIAS_FPORB_VOUT1_Msk                                                                               (0x1UL << AON_C_KOUT0X_MBIAS_FPORB_VOUT1_Pos)
+
+#define AON_C_KOUT0X_MBIAS_PORB_VOUT1_DELAY_Pos                                                                          14U
+#define AON_C_KOUT0X_MBIAS_PORB_VOUT1_DELAY_Msk                                                                          (0x1UL << AON_C_KOUT0X_MBIAS_PORB_VOUT1_DELAY_Pos)
+
+#define AON_C_KOUT0X_MBIAS_PORB_VOUT1_Pos                                                                                15U
+#define AON_C_KOUT0X_MBIAS_PORB_VOUT1_Msk                                                                                (0x1UL << AON_C_KOUT0X_MBIAS_PORB_VOUT1_Pos)
+
+#define AON_C_KOUT0X_MBIAS_CKOUT1X_MBIAS_DUMMY0_Pos                                                                      16U
+#define AON_C_KOUT0X_MBIAS_CKOUT1X_MBIAS_DUMMY0_Msk                                                                      (0xFFFFUL << AON_C_KOUT0X_MBIAS_CKOUT1X_MBIAS_DUMMY0_Pos)
+
+/* 0x49C    0x4000_049c
+    3:0     R/W     RESERVED_10                                                 4'b0
+    7:4     R/W     RESERVED_9                                                  4'b0
+    11:8    R/W     RESERVED_8                                                  4'b0
+    14:12   R/W     RESERVED_7                                                  3'b0
+    17:15   R/W     RESERVED_6                                                  3'b0
+    20:18   R/W     RESERVED_5                                                  3'b0
+    23:21   R/W     RESERVED_4                                                  3'b0
+    26:24   R/W     RESERVED_3                                                  3'b0
+    29:27   R       RESERVED_2                                                  3'b0
+    30      R       RESERVED_1                                                  1'b0
+    31      R/W     RESERVED                                                    1'b0
+ */
+typedef union _AON_C_KOUT1X_MBIAS_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED_10: 4;
+        uint32_t RESERVED_9: 4;
+        uint32_t RESERVED_8: 4;
+        uint32_t RESERVED_7: 3;
+        uint32_t RESERVED_6: 3;
+        uint32_t RESERVED_5: 3;
+        uint32_t RESERVED_4: 3;
+        uint32_t RESERVED_3: 3;
+        uint32_t RESERVED_2: 3;
+        uint32_t RESERVED_1: 1;
+        uint32_t RESERVED: 1;
+    };
+} AON_C_KOUT1X_MBIAS_TYPE;
+
+/*0x4000_049c AON_C_KOUT1X_MBIAS*/
+#define AON_C_KOUT1X_MBIAS_RESERVED_10_Pos                                                                               0U
+#define AON_C_KOUT1X_MBIAS_RESERVED_10_Msk                                                                               (0xFUL << AON_C_KOUT1X_MBIAS_RESERVED_10_Pos)
+
+#define AON_C_KOUT1X_MBIAS_RESERVED_9_Pos                                                                                4U
+#define AON_C_KOUT1X_MBIAS_RESERVED_9_Msk                                                                                (0xFUL << AON_C_KOUT1X_MBIAS_RESERVED_9_Pos)
+
+#define AON_C_KOUT1X_MBIAS_RESERVED_8_Pos                                                                                8U
+#define AON_C_KOUT1X_MBIAS_RESERVED_8_Msk                                                                                (0xFUL << AON_C_KOUT1X_MBIAS_RESERVED_8_Pos)
+
+#define AON_C_KOUT1X_MBIAS_RESERVED_7_Pos                                                                                12U
+#define AON_C_KOUT1X_MBIAS_RESERVED_7_Msk                                                                                (0x7UL << AON_C_KOUT1X_MBIAS_RESERVED_7_Pos)
+
+#define AON_C_KOUT1X_MBIAS_RESERVED_6_Pos                                                                                15U
+#define AON_C_KOUT1X_MBIAS_RESERVED_6_Msk                                                                                (0x7UL << AON_C_KOUT1X_MBIAS_RESERVED_6_Pos)
+
+#define AON_C_KOUT1X_MBIAS_RESERVED_5_Pos                                                                                18U
+#define AON_C_KOUT1X_MBIAS_RESERVED_5_Msk                                                                                (0x7UL << AON_C_KOUT1X_MBIAS_RESERVED_5_Pos)
+
+#define AON_C_KOUT1X_MBIAS_RESERVED_4_Pos                                                                                21U
+#define AON_C_KOUT1X_MBIAS_RESERVED_4_Msk                                                                                (0x7UL << AON_C_KOUT1X_MBIAS_RESERVED_4_Pos)
+
+#define AON_C_KOUT1X_MBIAS_RESERVED_3_Pos                                                                                24U
+#define AON_C_KOUT1X_MBIAS_RESERVED_3_Msk                                                                                (0x7UL << AON_C_KOUT1X_MBIAS_RESERVED_3_Pos)
+
+#define AON_C_KOUT1X_MBIAS_RESERVED_2_Pos                                                                                27U
+#define AON_C_KOUT1X_MBIAS_RESERVED_2_Msk                                                                                (0x7UL << AON_C_KOUT1X_MBIAS_RESERVED_2_Pos)
+
+#define AON_C_KOUT1X_MBIAS_RESERVED_1_Pos                                                                                30U
+#define AON_C_KOUT1X_MBIAS_RESERVED_1_Msk                                                                                (0x1UL << AON_C_KOUT1X_MBIAS_RESERVED_1_Pos)
+
+#define AON_C_KOUT1X_MBIAS_RESERVED_Pos                                                                                  31U
+#define AON_C_KOUT1X_MBIAS_RESERVED_Msk                                                                                  (0x1UL << AON_C_KOUT1X_MBIAS_RESERVED_Pos)
+
+/* 0x4BC    0x4000_04bc
+    7:0     R/W     OSC10M_RCAL                                                 8'd24
+    9:8     R/W     OSC10M_SEL_TOK                                              2'b10
+    15:10   R/W     REG0X_OSC10M_DUMMY0                                         6'b0
+    31:16   R/W     REG1X_OSC10M_DUMMY0                                         16'b0
+ */
+typedef union _AON_REG0X_OSC10M_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t OSC10M_RCAL: 8;
+        uint32_t OSC10M_SEL_TOK: 2;
+        uint32_t REG0X_OSC10M_DUMMY0: 6;
+        uint32_t REG1X_OSC10M_DUMMY0: 16;
+    };
+} AON_REG0X_OSC10M_TYPE;
+
+/*0x4000_04bc AON_REG0X_OSC10M*/
+#define AON_REG0X_OSC10M_OSC10M_RCAL_Pos                                                                                 0U
+#define AON_REG0X_OSC10M_OSC10M_RCAL_Msk                                                                                 (0xFFUL << AON_REG0X_OSC10M_OSC10M_RCAL_Pos)
+
+#define AON_REG0X_OSC10M_OSC10M_SEL_TOK_Pos                                                                              8U
+#define AON_REG0X_OSC10M_OSC10M_SEL_TOK_Msk                                                                              (0x3UL << AON_REG0X_OSC10M_OSC10M_SEL_TOK_Pos)
+
+#define AON_REG0X_OSC10M_REG0X_OSC10M_DUMMY0_Pos                                                                         10U
+#define AON_REG0X_OSC10M_REG0X_OSC10M_DUMMY0_Msk                                                                         (0x3FUL << AON_REG0X_OSC10M_REG0X_OSC10M_DUMMY0_Pos)
+
+#define AON_REG0X_OSC10M_REG1X_OSC10M_DUMMY0_Pos                                                                         16U
+#define AON_REG0X_OSC10M_REG1X_OSC10M_DUMMY0_Msk                                                                         (0xFFFFUL << AON_REG0X_OSC10M_REG1X_OSC10M_DUMMY0_Pos)
+
+/* 0x4C0    0x4000_04c0
+    15:0    R/W     REG2X_OSC10M_DUMMY0                                         16'b0
+    31:16   R       RSVD                                                        16'b0
+ */
+typedef union _AON_REG2X_OSC10M_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t REG2X_OSC10M_DUMMY0: 16;
+        uint32_t RSVD: 16;
+    };
+} AON_REG2X_OSC10M_TYPE;
+
+/*0x4000_04c0 AON_REG2X_OSC10M*/
+#define AON_REG2X_OSC10M_REG2X_OSC10M_DUMMY0_Pos                                                                         0U
+#define AON_REG2X_OSC10M_REG2X_OSC10M_DUMMY0_Msk                                                                         (0xFFFFUL << AON_REG2X_OSC10M_REG2X_OSC10M_DUMMY0_Pos)
+
+#define AON_REG2X_OSC10M_RSVD_Pos                                                                                        16U
+#define AON_REG2X_OSC10M_RSVD_Msk                                                                                        (0xFFFFUL << AON_REG2X_OSC10M_RSVD_Pos)
+
+/* 0x4C4    0x4000_04c4
+    5:0     R/W     OSC128K_RCAL                                                6'h20
+    6       R/W     OSC128K_EN_DIV4_CKOUT                                       1'b0
+    15:7    R/W     REG0X_OSC128K_DUMMY0                                        9'b0
+    31:16   R       RSVD                                                        16'b0
+ */
+typedef union _AON_REG0X_OSC128K_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t OSC128K_RCAL: 6;
+        uint32_t OSC128K_EN_DIV4_CKOUT: 1;
+        uint32_t REG0X_OSC128K_DUMMY0: 9;
+        uint32_t RSVD: 16;
+    };
+} AON_REG0X_OSC128K_TYPE;
+
+/*0x4000_04c4 AON_REG0X_OSC128K*/
+#define AON_REG0X_OSC128K_OSC128K_RCAL_Pos                                                                               0U
+#define AON_REG0X_OSC128K_OSC128K_RCAL_Msk                                                                               (0x3FUL << AON_REG0X_OSC128K_OSC128K_RCAL_Pos)
+
+#define AON_REG0X_OSC128K_OSC128K_EN_DIV4_CKOUT_Pos                                                                      6U
+#define AON_REG0X_OSC128K_OSC128K_EN_DIV4_CKOUT_Msk                                                                      (0x1UL << AON_REG0X_OSC128K_OSC128K_EN_DIV4_CKOUT_Pos)
+
+#define AON_REG0X_OSC128K_REG0X_OSC128K_DUMMY0_Pos                                                                       7U
+#define AON_REG0X_OSC128K_REG0X_OSC128K_DUMMY0_Msk                                                                       (0x1FFUL << AON_REG0X_OSC128K_REG0X_OSC128K_DUMMY0_Pos)
+
+#define AON_REG0X_OSC128K_RSVD_Pos                                                                                       16U
+#define AON_REG0X_OSC128K_RSVD_Msk                                                                                       (0xFFFFUL << AON_REG0X_OSC128K_RSVD_Pos)
+
+/* 0x4C8    0x4000_04c8
+    0       R/W     POW_32KOSC                                                  1'b1
+    1       R/W     POW_10MOSC                                                  1'b0
+    15:2    R/W     REG_POW_OSC_DUMMY0                                          14'b0
+    31:16   R       RSVD                                                        16'h0
+ */
+typedef union _AON_REG_POW_OSC_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t POW_32KOSC: 1;
+        uint32_t POW_10MOSC: 1;
+        uint32_t REG_POW_OSC_DUMMY0: 14;
+        uint32_t RSVD: 16;
+    };
+} AON_REG_POW_OSC_TYPE;
+
+/*0x4000_04c8 AON_REG_POW_OSC*/
+#define AON_REG_POW_OSC_POW_32KOSC_Pos                                                                                   0U
+#define AON_REG_POW_OSC_POW_32KOSC_Msk                                                                                   (0x1UL << AON_REG_POW_OSC_POW_32KOSC_Pos)
+
+#define AON_REG_POW_OSC_POW_10MOSC_Pos                                                                                   1U
+#define AON_REG_POW_OSC_POW_10MOSC_Msk                                                                                   (0x1UL << AON_REG_POW_OSC_POW_10MOSC_Pos)
+
+#define AON_REG_POW_OSC_REG_POW_OSC_DUMMY0_Pos                                                                           2U
+#define AON_REG_POW_OSC_REG_POW_OSC_DUMMY0_Msk                                                                           (0x3FFFUL << AON_REG_POW_OSC_REG_POW_OSC_DUMMY0_Pos)
+
+#define AON_REG_POW_OSC_RSVD_Pos                                                                                         16U
+#define AON_REG_POW_OSC_RSVD_Msk                                                                                         (0xFFFFUL << AON_REG_POW_OSC_RSVD_Pos)
+
+/* 0x4CC    0x4000_04cc
+    0       R       OK_32K                                                      1'b0
+    1       R       OK_10MOSC                                                   1'b0
+    14:2    R       RSVD_1                                                      13'b0
+    15      W1C     PORST_ACTIVE                                                1'b1
+    31:16   R       RSVD                                                        16'h0
+ */
+typedef union _AON_C_KOUT0X_OSC128K10M_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t OK_32K: 1;
+        uint32_t OK_10MOSC: 1;
+        uint32_t RSVD_1: 13;
+        uint32_t PORST_ACTIVE: 1;
+        uint32_t RSVD: 16;
+    };
+} AON_C_KOUT0X_OSC128K10M_TYPE;
+
+/*0x4000_04cc AON_C_KOUT0X_OSC128K10M*/
+#define AON_C_KOUT0X_OSC128K10M_OK_32K_Pos                                                                               0U
+#define AON_C_KOUT0X_OSC128K10M_OK_32K_Msk                                                                               (0x1UL << AON_C_KOUT0X_OSC128K10M_OK_32K_Pos)
+
+#define AON_C_KOUT0X_OSC128K10M_OK_10MOSC_Pos                                                                            1U
+#define AON_C_KOUT0X_OSC128K10M_OK_10MOSC_Msk                                                                            (0x1UL << AON_C_KOUT0X_OSC128K10M_OK_10MOSC_Pos)
+
+#define AON_C_KOUT0X_OSC128K10M_RSVD_1_Pos                                                                               2U
+#define AON_C_KOUT0X_OSC128K10M_RSVD_1_Msk                                                                               (0x1FFFUL << AON_C_KOUT0X_OSC128K10M_RSVD_1_Pos)
+
+#define AON_C_KOUT0X_OSC128K10M_PORST_ACTIVE_Pos                                                                         15U
+#define AON_C_KOUT0X_OSC128K10M_PORST_ACTIVE_Msk                                                                         (0x1UL << AON_C_KOUT0X_OSC128K10M_PORST_ACTIVE_Pos)
+
+#define AON_C_KOUT0X_OSC128K10M_RSVD_Pos                                                                                 16U
+#define AON_C_KOUT0X_OSC128K10M_RSVD_Msk                                                                                 (0xFFFFUL << AON_C_KOUT0X_OSC128K10M_RSVD_Pos)
+
+/* 0x500    0x4000_0500
+    0       R/W     OSC128_CAL_RESET_N                                          1'b1
+    1       R/W     SW_LIN_CAL_EN                                               1'b0
+    2       R/W     SW_SDM_CAL_EN                                               1'b0
+    3       R/W     OSC128K_CAL_TMETER_MODE                                     1'h0
+    4       R/W     OSC128K_CAL_DUMMY2                                          1'b0
+    6:5     R/W     DBG_SEL                                                     2'b00
+    31:7    R       RSVD                                                        25'b0
+ */
+typedef union _AON_REG0X_OSC128K_CAL_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t OSC128_CAL_RESET_N: 1;
+        uint32_t SW_LIN_CAL_EN: 1;
+        uint32_t SW_SDM_CAL_EN: 1;
+        uint32_t OSC128K_CAL_TMETER_MODE: 1;
+        uint32_t OSC128K_CAL_DUMMY2: 1;
+        uint32_t DBG_SEL: 2;
+        uint32_t RSVD: 25;
+    };
+} AON_REG0X_OSC128K_CAL_TYPE;
+
+/*0x4000_0500 AON_REG0X_OSC128K_CAL*/
+#define AON_REG0X_OSC128K_CAL_OSC128_CAL_RESET_N_Pos                                                                     0U
+#define AON_REG0X_OSC128K_CAL_OSC128_CAL_RESET_N_Msk                                                                     (0x1UL << AON_REG0X_OSC128K_CAL_OSC128_CAL_RESET_N_Pos)
+
+#define AON_REG0X_OSC128K_CAL_SW_LIN_CAL_EN_Pos                                                                          1U
+#define AON_REG0X_OSC128K_CAL_SW_LIN_CAL_EN_Msk                                                                          (0x1UL << AON_REG0X_OSC128K_CAL_SW_LIN_CAL_EN_Pos)
+
+#define AON_REG0X_OSC128K_CAL_SW_SDM_CAL_EN_Pos                                                                          2U
+#define AON_REG0X_OSC128K_CAL_SW_SDM_CAL_EN_Msk                                                                          (0x1UL << AON_REG0X_OSC128K_CAL_SW_SDM_CAL_EN_Pos)
+
+#define AON_REG0X_OSC128K_CAL_OSC128K_CAL_TMETER_MODE_Pos                                                                3U
+#define AON_REG0X_OSC128K_CAL_OSC128K_CAL_TMETER_MODE_Msk                                                                (0x1UL << AON_REG0X_OSC128K_CAL_OSC128K_CAL_TMETER_MODE_Pos)
+
+#define AON_REG0X_OSC128K_CAL_OSC128K_CAL_DUMMY2_Pos                                                                     4U
+#define AON_REG0X_OSC128K_CAL_OSC128K_CAL_DUMMY2_Msk                                                                     (0x1UL << AON_REG0X_OSC128K_CAL_OSC128K_CAL_DUMMY2_Pos)
+
+#define AON_REG0X_OSC128K_CAL_DBG_SEL_Pos                                                                                5U
+#define AON_REG0X_OSC128K_CAL_DBG_SEL_Msk                                                                                (0x3UL << AON_REG0X_OSC128K_CAL_DBG_SEL_Pos)
+
+#define AON_REG0X_OSC128K_CAL_RSVD_Pos                                                                                   7U
+#define AON_REG0X_OSC128K_CAL_RSVD_Msk                                                                                   (0x1FFFFFFUL << AON_REG0X_OSC128K_CAL_RSVD_Pos)
+
+/* 0x504    0x4000_0504
+    3:0     R/W     RCAL_H                                                      4'h9
+    10:4    R/W     RCAL_SETTLE_CYC                                             7'h3f
+    11      R       RSVD_1                                                      1'b0
+    15:12   R/W     INC_STEP                                                    4'h0
+    21:16   R/W     KT_LIM                                                      6'h30
+    25:22   R/W     DELTA_RCAL_H                                                4'hA
+    31:26   R       RSVD                                                        6'b0
+ */
+typedef union _AON_REG2X_OSC128K_CAL_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RCAL_H: 4;
+        uint32_t RCAL_SETTLE_CYC: 7;
+        uint32_t RSVD_1: 1;
+        uint32_t INC_STEP: 4;
+        uint32_t KT_LIM: 6;
+        uint32_t DELTA_RCAL_H: 4;
+        uint32_t RSVD: 6;
+    };
+} AON_REG2X_OSC128K_CAL_TYPE;
+
+/*0x4000_0504 AON_REG2X_OSC128K_CAL*/
+#define AON_REG2X_OSC128K_CAL_RCAL_H_Pos                                                                                 0U
+#define AON_REG2X_OSC128K_CAL_RCAL_H_Msk                                                                                 (0xFUL << AON_REG2X_OSC128K_CAL_RCAL_H_Pos)
+
+#define AON_REG2X_OSC128K_CAL_RCAL_SETTLE_CYC_Pos                                                                        4U
+#define AON_REG2X_OSC128K_CAL_RCAL_SETTLE_CYC_Msk                                                                        (0x7FUL << AON_REG2X_OSC128K_CAL_RCAL_SETTLE_CYC_Pos)
+
+#define AON_REG2X_OSC128K_CAL_RSVD_1_Pos                                                                                 11U
+#define AON_REG2X_OSC128K_CAL_RSVD_1_Msk                                                                                 (0x1UL << AON_REG2X_OSC128K_CAL_RSVD_1_Pos)
+
+#define AON_REG2X_OSC128K_CAL_INC_STEP_Pos                                                                               12U
+#define AON_REG2X_OSC128K_CAL_INC_STEP_Msk                                                                               (0xFUL << AON_REG2X_OSC128K_CAL_INC_STEP_Pos)
+
+#define AON_REG2X_OSC128K_CAL_KT_LIM_Pos                                                                                 16U
+#define AON_REG2X_OSC128K_CAL_KT_LIM_Msk                                                                                 (0x3FUL << AON_REG2X_OSC128K_CAL_KT_LIM_Pos)
+
+#define AON_REG2X_OSC128K_CAL_DELTA_RCAL_H_Pos                                                                           22U
+#define AON_REG2X_OSC128K_CAL_DELTA_RCAL_H_Msk                                                                           (0xFUL << AON_REG2X_OSC128K_CAL_DELTA_RCAL_H_Pos)
+
+#define AON_REG2X_OSC128K_CAL_RSVD_Pos                                                                                   26U
+#define AON_REG2X_OSC128K_CAL_RSVD_Msk                                                                                   (0x3FUL << AON_REG2X_OSC128K_CAL_RSVD_Pos)
+
+/* 0x508    0x4000_0508
+    16:0    R/W     CENTER_CNT_FREF                                             17'h1388
+    23:17   R       RSVD_1                                                      7'b0
+    27:24   R/W     LIN_K_CNT_CYC                                               4'h3
+    31:28   R/W     RSVD                                                        4'h0
+ */
+typedef union _AON_REG4X_OSC128K_CAL_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t CENTER_CNT_FREF: 17;
+        uint32_t RSVD_1: 7;
+        uint32_t LIN_K_CNT_CYC: 4;
+        uint32_t RSVD: 4;
+    };
+} AON_REG4X_OSC128K_CAL_TYPE;
+
+/*0x4000_0508 AON_REG4X_OSC128K_CAL*/
+#define AON_REG4X_OSC128K_CAL_CENTER_CNT_FREF_Pos                                                                        0U
+#define AON_REG4X_OSC128K_CAL_CENTER_CNT_FREF_Msk                                                                        (0x1FFFFUL << AON_REG4X_OSC128K_CAL_CENTER_CNT_FREF_Pos)
+
+#define AON_REG4X_OSC128K_CAL_RSVD_1_Pos                                                                                 17U
+#define AON_REG4X_OSC128K_CAL_RSVD_1_Msk                                                                                 (0x7FUL << AON_REG4X_OSC128K_CAL_RSVD_1_Pos)
+
+#define AON_REG4X_OSC128K_CAL_LIN_K_CNT_CYC_Pos                                                                          24U
+#define AON_REG4X_OSC128K_CAL_LIN_K_CNT_CYC_Msk                                                                          (0xFUL << AON_REG4X_OSC128K_CAL_LIN_K_CNT_CYC_Pos)
+
+#define AON_REG4X_OSC128K_CAL_RSVD_Pos                                                                                   28U
+#define AON_REG4X_OSC128K_CAL_RSVD_Msk                                                                                   (0xFUL << AON_REG4X_OSC128K_CAL_RSVD_Pos)
+
+/* 0x50C    0x4000_050c
+    9:0     R/W     CRITER0                                                     10'h96
+    15:10   R       RSVD                                                        6'b0
+    30:16   R/W     RCAL_INIT                                                   15'h20
+    31      R/W     TEST_MODE                                                   1'h0
+ */
+typedef union _AON_REG6X_OSC128K_CAL_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t CRITER0: 10;
+        uint32_t RSVD: 6;
+        uint32_t RCAL_INIT: 15;
+        uint32_t TEST_MODE: 1;
+    };
+} AON_REG6X_OSC128K_CAL_TYPE;
+
+/*0x4000_050c AON_REG6X_OSC128K_CAL*/
+#define AON_REG6X_OSC128K_CAL_CRITER0_Pos                                                                                0U
+#define AON_REG6X_OSC128K_CAL_CRITER0_Msk                                                                                (0x3FFUL << AON_REG6X_OSC128K_CAL_CRITER0_Pos)
+
+#define AON_REG6X_OSC128K_CAL_RSVD_Pos                                                                                   10U
+#define AON_REG6X_OSC128K_CAL_RSVD_Msk                                                                                   (0x3FUL << AON_REG6X_OSC128K_CAL_RSVD_Pos)
+
+#define AON_REG6X_OSC128K_CAL_RCAL_INIT_Pos                                                                              16U
+#define AON_REG6X_OSC128K_CAL_RCAL_INIT_Msk                                                                              (0x7FFFUL << AON_REG6X_OSC128K_CAL_RCAL_INIT_Pos)
+
+#define AON_REG6X_OSC128K_CAL_TEST_MODE_Pos                                                                              31U
+#define AON_REG6X_OSC128K_CAL_TEST_MODE_Msk                                                                              (0x1UL << AON_REG6X_OSC128K_CAL_TEST_MODE_Pos)
+
+/* 0x510    0x4000_0510
+    2:0     R/W     SDM_K_CNT_CYC                                               3'h3
+    3       R       RSVD_3                                                      1'b0
+    6:4     R/W     SDM_K_CNT_CYC_ALPHA                                         3'h0
+    7       R       RSVD_2                                                      1'b0
+    12:8    R/W     ALPHA_PARAM_SET                                             5'd28
+    13      R/W     ALPHA_FB_MANUAL_EN                                          1'b0
+    14      R/W     ALPHA_ONLY_SEL_EN                                           1'b0
+    15      R       RSVD_1                                                      1'b0
+    19:16   R/W     SDM2ALPHA_CNT_TARGET                                        4'h7
+    31:20   R/W     RSVD                                                        12'h0
+ */
+typedef union _AON_REG8X_OSC128K_CAL_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t SDM_K_CNT_CYC: 3;
+        uint32_t RSVD_3: 1;
+        uint32_t SDM_K_CNT_CYC_ALPHA: 3;
+        uint32_t RSVD_2: 1;
+        uint32_t ALPHA_PARAM_SET: 5;
+        uint32_t ALPHA_FB_MANUAL_EN: 1;
+        uint32_t ALPHA_ONLY_SEL_EN: 1;
+        uint32_t RSVD_1: 1;
+        uint32_t SDM2ALPHA_CNT_TARGET: 4;
+        uint32_t RSVD: 12;
+    };
+} AON_REG8X_OSC128K_CAL_TYPE;
+
+/*0x4000_0510 AON_REG8X_OSC128K_CAL*/
+#define AON_REG8X_OSC128K_CAL_SDM_K_CNT_CYC_Pos                                                                          0U
+#define AON_REG8X_OSC128K_CAL_SDM_K_CNT_CYC_Msk                                                                          (0x7UL << AON_REG8X_OSC128K_CAL_SDM_K_CNT_CYC_Pos)
+
+#define AON_REG8X_OSC128K_CAL_RSVD_3_Pos                                                                                 3U
+#define AON_REG8X_OSC128K_CAL_RSVD_3_Msk                                                                                 (0x1UL << AON_REG8X_OSC128K_CAL_RSVD_3_Pos)
+
+#define AON_REG8X_OSC128K_CAL_SDM_K_CNT_CYC_ALPHA_Pos                                                                    4U
+#define AON_REG8X_OSC128K_CAL_SDM_K_CNT_CYC_ALPHA_Msk                                                                    (0x7UL << AON_REG8X_OSC128K_CAL_SDM_K_CNT_CYC_ALPHA_Pos)
+
+#define AON_REG8X_OSC128K_CAL_RSVD_2_Pos                                                                                 7U
+#define AON_REG8X_OSC128K_CAL_RSVD_2_Msk                                                                                 (0x1UL << AON_REG8X_OSC128K_CAL_RSVD_2_Pos)
+
+#define AON_REG8X_OSC128K_CAL_ALPHA_PARAM_SET_Pos                                                                        8U
+#define AON_REG8X_OSC128K_CAL_ALPHA_PARAM_SET_Msk                                                                        (0x1FUL << AON_REG8X_OSC128K_CAL_ALPHA_PARAM_SET_Pos)
+
+#define AON_REG8X_OSC128K_CAL_ALPHA_FB_MANUAL_EN_Pos                                                                     13U
+#define AON_REG8X_OSC128K_CAL_ALPHA_FB_MANUAL_EN_Msk                                                                     (0x1UL << AON_REG8X_OSC128K_CAL_ALPHA_FB_MANUAL_EN_Pos)
+
+#define AON_REG8X_OSC128K_CAL_ALPHA_ONLY_SEL_EN_Pos                                                                      14U
+#define AON_REG8X_OSC128K_CAL_ALPHA_ONLY_SEL_EN_Msk                                                                      (0x1UL << AON_REG8X_OSC128K_CAL_ALPHA_ONLY_SEL_EN_Pos)
+
+#define AON_REG8X_OSC128K_CAL_RSVD_1_Pos                                                                                 15U
+#define AON_REG8X_OSC128K_CAL_RSVD_1_Msk                                                                                 (0x1UL << AON_REG8X_OSC128K_CAL_RSVD_1_Pos)
+
+#define AON_REG8X_OSC128K_CAL_SDM2ALPHA_CNT_TARGET_Pos                                                                   16U
+#define AON_REG8X_OSC128K_CAL_SDM2ALPHA_CNT_TARGET_Msk                                                                   (0xFUL << AON_REG8X_OSC128K_CAL_SDM2ALPHA_CNT_TARGET_Pos)
+
+#define AON_REG8X_OSC128K_CAL_RSVD_Pos                                                                                   20U
+#define AON_REG8X_OSC128K_CAL_RSVD_Msk                                                                                   (0xFFFUL << AON_REG8X_OSC128K_CAL_RSVD_Pos)
+
+/* 0x514    0x4000_0514
+    16:0    R/W     ALPHA_FB_MANUAL                                             17'h0
+    31:17   R       RSVD                                                        15'h0
+ */
+typedef union _AON_REG10X_OSC128K_CAL_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t ALPHA_FB_MANUAL: 17;
+        uint32_t RSVD: 15;
+    };
+} AON_REG10X_OSC128K_CAL_TYPE;
+
+/*0x4000_0514 AON_REG10X_OSC128K_CAL*/
+#define AON_REG10X_OSC128K_CAL_ALPHA_FB_MANUAL_Pos                                                                       0U
+#define AON_REG10X_OSC128K_CAL_ALPHA_FB_MANUAL_Msk                                                                       (0x1FFFFUL << AON_REG10X_OSC128K_CAL_ALPHA_FB_MANUAL_Pos)
+
+#define AON_REG10X_OSC128K_CAL_RSVD_Pos                                                                                  17U
+#define AON_REG10X_OSC128K_CAL_RSVD_Msk                                                                                  (0x7FFFUL << AON_REG10X_OSC128K_CAL_RSVD_Pos)
+
+/* 0x518    0x4000_0518
+    14:0    R/W     MANUAL_SDM_FRAC                                             15'h0
+    15      R       RSVD_1                                                      1'h0
+    19:16   R/W     MANUAL_SDM_INT                                              4'h0
+    30:20   R       RSVD                                                        11'h0
+    31      R/W     MANUAL_SDM_MODE                                             1'h0
+ */
+typedef union _AON_REG12X_OSC128K_CAL_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t MANUAL_SDM_FRAC: 15;
+        uint32_t RSVD_1: 1;
+        uint32_t MANUAL_SDM_INT: 4;
+        uint32_t RSVD: 11;
+        uint32_t MANUAL_SDM_MODE: 1;
+    };
+} AON_REG12X_OSC128K_CAL_TYPE;
+
+/*0x4000_0518 AON_REG12X_OSC128K_CAL*/
+#define AON_REG12X_OSC128K_CAL_MANUAL_SDM_FRAC_Pos                                                                       0U
+#define AON_REG12X_OSC128K_CAL_MANUAL_SDM_FRAC_Msk                                                                       (0x7FFFUL << AON_REG12X_OSC128K_CAL_MANUAL_SDM_FRAC_Pos)
+
+#define AON_REG12X_OSC128K_CAL_RSVD_1_Pos                                                                                15U
+#define AON_REG12X_OSC128K_CAL_RSVD_1_Msk                                                                                (0x1UL << AON_REG12X_OSC128K_CAL_RSVD_1_Pos)
+
+#define AON_REG12X_OSC128K_CAL_MANUAL_SDM_INT_Pos                                                                        16U
+#define AON_REG12X_OSC128K_CAL_MANUAL_SDM_INT_Msk                                                                        (0xFUL << AON_REG12X_OSC128K_CAL_MANUAL_SDM_INT_Pos)
+
+#define AON_REG12X_OSC128K_CAL_RSVD_Pos                                                                                  20U
+#define AON_REG12X_OSC128K_CAL_RSVD_Msk                                                                                  (0x7FFUL << AON_REG12X_OSC128K_CAL_RSVD_Pos)
+
+#define AON_REG12X_OSC128K_CAL_MANUAL_SDM_MODE_Pos                                                                       31U
+#define AON_REG12X_OSC128K_CAL_MANUAL_SDM_MODE_Msk                                                                       (0x1UL << AON_REG12X_OSC128K_CAL_MANUAL_SDM_MODE_Pos)
+
+/* 0x51C    0x4000_051c
+    14:0    R       RCAL_O                                                      15'h0
+    15      R       RSVD_1                                                      1'h0
+    21:16   R       KT_CNT                                                      6'h0
+    23:22   R       LOCK                                                        2'h0
+    28:24   R       SDM_CAL_CNT                                                 5'h0
+    31:29   R       RSVD                                                        3'h0
+ */
+typedef union _AON_REG14X_OSC128K_CAL_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RCAL_O: 15;
+        uint32_t RSVD_1: 1;
+        uint32_t KT_CNT: 6;
+        uint32_t LOCK: 2;
+        uint32_t SDM_CAL_CNT: 5;
+        uint32_t RSVD: 3;
+    };
+} AON_REG14X_OSC128K_CAL_TYPE;
+
+/*0x4000_051c AON_REG14X_OSC128K_CAL*/
+#define AON_REG14X_OSC128K_CAL_RCAL_O_Pos                                                                                0U
+#define AON_REG14X_OSC128K_CAL_RCAL_O_Msk                                                                                (0x7FFFUL << AON_REG14X_OSC128K_CAL_RCAL_O_Pos)
+
+#define AON_REG14X_OSC128K_CAL_RSVD_1_Pos                                                                                15U
+#define AON_REG14X_OSC128K_CAL_RSVD_1_Msk                                                                                (0x1UL << AON_REG14X_OSC128K_CAL_RSVD_1_Pos)
+
+#define AON_REG14X_OSC128K_CAL_KT_CNT_Pos                                                                                16U
+#define AON_REG14X_OSC128K_CAL_KT_CNT_Msk                                                                                (0x3FUL << AON_REG14X_OSC128K_CAL_KT_CNT_Pos)
+
+#define AON_REG14X_OSC128K_CAL_LOCK_Pos                                                                                  22U
+#define AON_REG14X_OSC128K_CAL_LOCK_Msk                                                                                  (0x3UL << AON_REG14X_OSC128K_CAL_LOCK_Pos)
+
+#define AON_REG14X_OSC128K_CAL_SDM_CAL_CNT_Pos                                                                           24U
+#define AON_REG14X_OSC128K_CAL_SDM_CAL_CNT_Msk                                                                           (0x1FUL << AON_REG14X_OSC128K_CAL_SDM_CAL_CNT_Pos)
+
+#define AON_REG14X_OSC128K_CAL_RSVD_Pos                                                                                  29U
+#define AON_REG14X_OSC128K_CAL_RSVD_Msk                                                                                  (0x7UL << AON_REG14X_OSC128K_CAL_RSVD_Pos)
+
+/* 0x520    0x4000_0520
+    14:0    R       SDM_FRAC                                                    15'h0
+    15      R       RSVD_1                                                      1'h0
+    19:16   R       SDM_INT                                                     4'h0
+    31:20   R       RSVD                                                        12'h0
+ */
+typedef union _AON_REG16X_OSC128K_CAL_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t SDM_FRAC: 15;
+        uint32_t RSVD_1: 1;
+        uint32_t SDM_INT: 4;
+        uint32_t RSVD: 12;
+    };
+} AON_REG16X_OSC128K_CAL_TYPE;
+
+/*0x4000_0520 AON_REG16X_OSC128K_CAL*/
+#define AON_REG16X_OSC128K_CAL_SDM_FRAC_Pos                                                                              0U
+#define AON_REG16X_OSC128K_CAL_SDM_FRAC_Msk                                                                              (0x7FFFUL << AON_REG16X_OSC128K_CAL_SDM_FRAC_Pos)
+
+#define AON_REG16X_OSC128K_CAL_RSVD_1_Pos                                                                                15U
+#define AON_REG16X_OSC128K_CAL_RSVD_1_Msk                                                                                (0x1UL << AON_REG16X_OSC128K_CAL_RSVD_1_Pos)
+
+#define AON_REG16X_OSC128K_CAL_SDM_INT_Pos                                                                               16U
+#define AON_REG16X_OSC128K_CAL_SDM_INT_Msk                                                                               (0xFUL << AON_REG16X_OSC128K_CAL_SDM_INT_Pos)
+
+#define AON_REG16X_OSC128K_CAL_RSVD_Pos                                                                                  20U
+#define AON_REG16X_OSC128K_CAL_RSVD_Msk                                                                                  (0xFFFUL << AON_REG16X_OSC128K_CAL_RSVD_Pos)
+
+/* 0x524    0x4000_0524
+    16:0    R       CNT_FREF_REP_0                                              17'h0
+    31:17   R       RSVD                                                        15'h0
+ */
+typedef union _AON_REG18X_OSC128K_CAL_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t CNT_FREF_REP_0: 17;
+        uint32_t RSVD: 15;
+    };
+} AON_REG18X_OSC128K_CAL_TYPE;
+
+/*0x4000_0524 AON_REG18X_OSC128K_CAL*/
+#define AON_REG18X_OSC128K_CAL_CNT_FREF_REP_0_Pos                                                                        0U
+#define AON_REG18X_OSC128K_CAL_CNT_FREF_REP_0_Msk                                                                        (0x1FFFFUL << AON_REG18X_OSC128K_CAL_CNT_FREF_REP_0_Pos)
+
+#define AON_REG18X_OSC128K_CAL_RSVD_Pos                                                                                  17U
+#define AON_REG18X_OSC128K_CAL_RSVD_Msk                                                                                  (0x7FFFUL << AON_REG18X_OSC128K_CAL_RSVD_Pos)
+
+/* 0x528    0x4000_0528
+    16:0    R       CNT_FREF_REP_1                                              17'h0
+    31:17   R       RSVD                                                        15'h0
+ */
+typedef union _AON_REG20X_OSC128K_CAL_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t CNT_FREF_REP_1: 17;
+        uint32_t RSVD: 15;
+    };
+} AON_REG20X_OSC128K_CAL_TYPE;
+
+/*0x4000_0528 AON_REG20X_OSC128K_CAL*/
+#define AON_REG20X_OSC128K_CAL_CNT_FREF_REP_1_Pos                                                                        0U
+#define AON_REG20X_OSC128K_CAL_CNT_FREF_REP_1_Msk                                                                        (0x1FFFFUL << AON_REG20X_OSC128K_CAL_CNT_FREF_REP_1_Pos)
+
+#define AON_REG20X_OSC128K_CAL_RSVD_Pos                                                                                  17U
+#define AON_REG20X_OSC128K_CAL_RSVD_Msk                                                                                  (0x7FFFUL << AON_REG20X_OSC128K_CAL_RSVD_Pos)
+
+/* 0x52C    0x4000_052c
+    16:0    R       CNT_FREF_REP_2                                              17'h0
+    31:17   R       RSVD                                                        15'h0
+ */
+typedef union _AON_REG22X_OSC128K_CAL_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t CNT_FREF_REP_2: 17;
+        uint32_t RSVD: 15;
+    };
+} AON_REG22X_OSC128K_CAL_TYPE;
+
+/*0x4000_052c AON_REG22X_OSC128K_CAL*/
+#define AON_REG22X_OSC128K_CAL_CNT_FREF_REP_2_Pos                                                                        0U
+#define AON_REG22X_OSC128K_CAL_CNT_FREF_REP_2_Msk                                                                        (0x1FFFFUL << AON_REG22X_OSC128K_CAL_CNT_FREF_REP_2_Pos)
+
+#define AON_REG22X_OSC128K_CAL_RSVD_Pos                                                                                  17U
+#define AON_REG22X_OSC128K_CAL_RSVD_Msk                                                                                  (0x7FFFUL << AON_REG22X_OSC128K_CAL_RSVD_Pos)
+
+/* 0x530    0x4000_0530
+    16:0    R       CNT_FREF_REP_3                                              17'h0
+    31:17   R       RSVD                                                        15'h0
+ */
+typedef union _AON_REG24X_OSC128K_CAL_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t CNT_FREF_REP_3: 17;
+        uint32_t RSVD: 15;
+    };
+} AON_REG24X_OSC128K_CAL_TYPE;
+
+/*0x4000_0530 AON_REG24X_OSC128K_CAL*/
+#define AON_REG24X_OSC128K_CAL_CNT_FREF_REP_3_Pos                                                                        0U
+#define AON_REG24X_OSC128K_CAL_CNT_FREF_REP_3_Msk                                                                        (0x1FFFFUL << AON_REG24X_OSC128K_CAL_CNT_FREF_REP_3_Pos)
+
+#define AON_REG24X_OSC128K_CAL_RSVD_Pos                                                                                  17U
+#define AON_REG24X_OSC128K_CAL_RSVD_Msk                                                                                  (0x7FFFUL << AON_REG24X_OSC128K_CAL_RSVD_Pos)
+
+/* 0x534    0x4000_0534
+    16:0    R       CNT_FREF_REP_4                                              17'h0
+    31:17   R       RSVD                                                        15'h0
+ */
+typedef union _AON_REG26X_OSC128K_CAL_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t CNT_FREF_REP_4: 17;
+        uint32_t RSVD: 15;
+    };
+} AON_REG26X_OSC128K_CAL_TYPE;
+
+/*0x4000_0534 AON_REG26X_OSC128K_CAL*/
+#define AON_REG26X_OSC128K_CAL_CNT_FREF_REP_4_Pos                                                                        0U
+#define AON_REG26X_OSC128K_CAL_CNT_FREF_REP_4_Msk                                                                        (0x1FFFFUL << AON_REG26X_OSC128K_CAL_CNT_FREF_REP_4_Pos)
+
+#define AON_REG26X_OSC128K_CAL_RSVD_Pos                                                                                  17U
+#define AON_REG26X_OSC128K_CAL_RSVD_Msk                                                                                  (0x7FFFUL << AON_REG26X_OSC128K_CAL_RSVD_Pos)
+
+/* 0x538    0x4000_0538
+    16:0    R       CNT_FREF_REP_5                                              17'h0
+    31:17   R       RSVD                                                        15'h0
+ */
+typedef union _AON_REG28X_OSC128K_CAL_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t CNT_FREF_REP_5: 17;
+        uint32_t RSVD: 15;
+    };
+} AON_REG28X_OSC128K_CAL_TYPE;
+
+/*0x4000_0538 AON_REG28X_OSC128K_CAL*/
+#define AON_REG28X_OSC128K_CAL_CNT_FREF_REP_5_Pos                                                                        0U
+#define AON_REG28X_OSC128K_CAL_CNT_FREF_REP_5_Msk                                                                        (0x1FFFFUL << AON_REG28X_OSC128K_CAL_CNT_FREF_REP_5_Pos)
+
+#define AON_REG28X_OSC128K_CAL_RSVD_Pos                                                                                  17U
+#define AON_REG28X_OSC128K_CAL_RSVD_Msk                                                                                  (0x7FFFUL << AON_REG28X_OSC128K_CAL_RSVD_Pos)
+
+/* 0x53C    0x4000_053c
+    16:0    R       CNT_FREF_REP_6                                              17'h0
+    31:17   R       RSVD                                                        15'h0
+ */
+typedef union _AON_REG30X_OSC128K_CAL_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t CNT_FREF_REP_6: 17;
+        uint32_t RSVD: 15;
+    };
+} AON_REG30X_OSC128K_CAL_TYPE;
+
+/*0x4000_053c AON_REG30X_OSC128K_CAL*/
+#define AON_REG30X_OSC128K_CAL_CNT_FREF_REP_6_Pos                                                                        0U
+#define AON_REG30X_OSC128K_CAL_CNT_FREF_REP_6_Msk                                                                        (0x1FFFFUL << AON_REG30X_OSC128K_CAL_CNT_FREF_REP_6_Pos)
+
+#define AON_REG30X_OSC128K_CAL_RSVD_Pos                                                                                  17U
+#define AON_REG30X_OSC128K_CAL_RSVD_Msk                                                                                  (0x7FFFUL << AON_REG30X_OSC128K_CAL_RSVD_Pos)
+
+/* 0x540    0x4000_0540
+    16:0    R       CNT_FREF_REP_7                                              17'h0
+    31:17   R       RSVD                                                        15'h0
+ */
+typedef union _AON_REG32X_OSC128K_CAL_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t CNT_FREF_REP_7: 17;
+        uint32_t RSVD: 15;
+    };
+} AON_REG32X_OSC128K_CAL_TYPE;
+
+/*0x4000_0540 AON_REG32X_OSC128K_CAL*/
+#define AON_REG32X_OSC128K_CAL_CNT_FREF_REP_7_Pos                                                                        0U
+#define AON_REG32X_OSC128K_CAL_CNT_FREF_REP_7_Msk                                                                        (0x1FFFFUL << AON_REG32X_OSC128K_CAL_CNT_FREF_REP_7_Pos)
+
+#define AON_REG32X_OSC128K_CAL_RSVD_Pos                                                                                  17U
+#define AON_REG32X_OSC128K_CAL_RSVD_Msk                                                                                  (0x7FFFUL << AON_REG32X_OSC128K_CAL_RSVD_Pos)
+
+/* 0x544    0x4000_0544
+    16:0    R       PAST_ALPHA_OUT                                              17'h0
+    31:17   R       RSVD                                                        15'h0
+ */
+typedef union _AON_REG34X_OSC128K_CAL_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t PAST_ALPHA_OUT: 17;
+        uint32_t RSVD: 15;
+    };
+} AON_REG34X_OSC128K_CAL_TYPE;
+
+/*0x4000_0544 AON_REG34X_OSC128K_CAL*/
+#define AON_REG34X_OSC128K_CAL_PAST_ALPHA_OUT_Pos                                                                        0U
+#define AON_REG34X_OSC128K_CAL_PAST_ALPHA_OUT_Msk                                                                        (0x1FFFFUL << AON_REG34X_OSC128K_CAL_PAST_ALPHA_OUT_Pos)
+
+#define AON_REG34X_OSC128K_CAL_RSVD_Pos                                                                                  17U
+#define AON_REG34X_OSC128K_CAL_RSVD_Msk                                                                                  (0x7FFFUL << AON_REG34X_OSC128K_CAL_RSVD_Pos)
+
+/* 0x548    0x4000_0548
+    16:0    R       LIN_CNT_FREF_REP_0                                          17'h0
+    31:17   R       RSVD                                                        15'h0
+ */
+typedef union _AON_REG36X_OSC128K_CAL_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t LIN_CNT_FREF_REP_0: 17;
+        uint32_t RSVD: 15;
+    };
+} AON_REG36X_OSC128K_CAL_TYPE;
+
+/*0x4000_0548 AON_REG36X_OSC128K_CAL*/
+#define AON_REG36X_OSC128K_CAL_LIN_CNT_FREF_REP_0_Pos                                                                    0U
+#define AON_REG36X_OSC128K_CAL_LIN_CNT_FREF_REP_0_Msk                                                                    (0x1FFFFUL << AON_REG36X_OSC128K_CAL_LIN_CNT_FREF_REP_0_Pos)
+
+#define AON_REG36X_OSC128K_CAL_RSVD_Pos                                                                                  17U
+#define AON_REG36X_OSC128K_CAL_RSVD_Msk                                                                                  (0x7FFFUL << AON_REG36X_OSC128K_CAL_RSVD_Pos)
+
+/* 0x54C    0x4000_054c
+    16:0    R       LIN_CNT_FREF_REP_1                                          17'h0
+    31:17   R       RSVD                                                        15'h0
+ */
+typedef union _AON_REG38X_OSC128K_CAL_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t LIN_CNT_FREF_REP_1: 17;
+        uint32_t RSVD: 15;
+    };
+} AON_REG38X_OSC128K_CAL_TYPE;
+
+/*0x4000_054c AON_REG38X_OSC128K_CAL*/
+#define AON_REG38X_OSC128K_CAL_LIN_CNT_FREF_REP_1_Pos                                                                    0U
+#define AON_REG38X_OSC128K_CAL_LIN_CNT_FREF_REP_1_Msk                                                                    (0x1FFFFUL << AON_REG38X_OSC128K_CAL_LIN_CNT_FREF_REP_1_Pos)
+
+#define AON_REG38X_OSC128K_CAL_RSVD_Pos                                                                                  17U
+#define AON_REG38X_OSC128K_CAL_RSVD_Msk                                                                                  (0x7FFFUL << AON_REG38X_OSC128K_CAL_RSVD_Pos)
+
+/* 0x550    0x4000_0550
+    0       R/W     OSC128K_CAL_RAP_MODE                                        1'h0
+    31:1    R       RSVD                                                        31'b0
+ */
+typedef union _AON_REG_OSC128K_CAL_RAP_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t OSC128K_CAL_RAP_MODE: 1;
+        uint32_t RSVD: 31;
+    };
+} AON_REG_OSC128K_CAL_RAP_TYPE;
+
+/*0x4000_0550 AON_REG_OSC128K_CAL_RAP*/
+#define AON_REG_OSC128K_CAL_RAP_OSC128K_CAL_RAP_MODE_Pos                                                                 0U
+#define AON_REG_OSC128K_CAL_RAP_OSC128K_CAL_RAP_MODE_Msk                                                                 (0x1UL << AON_REG_OSC128K_CAL_RAP_OSC128K_CAL_RAP_MODE_Pos)
+
+#define AON_REG_OSC128K_CAL_RAP_RSVD_Pos                                                                                 1U
+#define AON_REG_OSC128K_CAL_RAP_RSVD_Msk                                                                                 (0x7FFFFFFFUL << AON_REG_OSC128K_CAL_RAP_RSVD_Pos)
+
+/* 0x554    0x4000_0554
+    0       R/W     CAL32K_SCLK_QACTIVE_MAN_DATA                                1'b0
+    1       R/W     CAL32K_SCLK_QACTIVE_MAN_EN                                  1'b0
+    2       R/W     CAL32K_PCLK_QACTIVE_MAN_DATA                                1'b0
+    3       R/W     CAL32K_PCLK_QACTIVE_MAN_EN                                  1'b0
+    4       R/W     CAL32K_OSC128K_QACTIVE_MAN_DATA                             1'b0
+    5       R/W     CAL32K_OSC128K_QACTIVE_MAN_EN                               1'b0
+    6       R/W     CAL32K_AONCLK_QACTIVE_MAN_DATA                              1'b0
+    7       R/W     CAL32K_AONCLK_QACTIVE_MAN_EN                                1'b0
+    31:8    R       RSVD                                                        24'b0
+ */
+typedef union _AON_REG_OSC128K_CAL_QCH_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t CAL32K_SCLK_QACTIVE_MAN_DATA: 1;
+        uint32_t CAL32K_SCLK_QACTIVE_MAN_EN: 1;
+        uint32_t CAL32K_PCLK_QACTIVE_MAN_DATA: 1;
+        uint32_t CAL32K_PCLK_QACTIVE_MAN_EN: 1;
+        uint32_t CAL32K_OSC128K_QACTIVE_MAN_DATA: 1;
+        uint32_t CAL32K_OSC128K_QACTIVE_MAN_EN: 1;
+        uint32_t CAL32K_AONCLK_QACTIVE_MAN_DATA: 1;
+        uint32_t CAL32K_AONCLK_QACTIVE_MAN_EN: 1;
+        uint32_t RSVD: 24;
+    };
+} AON_REG_OSC128K_CAL_QCH_TYPE;
+
+/*0x4000_0554 AON_REG_OSC128K_CAL_QCH*/
+#define AON_REG_OSC128K_CAL_QCH_CAL32K_SCLK_QACTIVE_MAN_DATA_Pos                                                         0U
+#define AON_REG_OSC128K_CAL_QCH_CAL32K_SCLK_QACTIVE_MAN_DATA_Msk                                                         (0x1UL << AON_REG_OSC128K_CAL_QCH_CAL32K_SCLK_QACTIVE_MAN_DATA_Pos)
+
+#define AON_REG_OSC128K_CAL_QCH_CAL32K_SCLK_QACTIVE_MAN_EN_Pos                                                           1U
+#define AON_REG_OSC128K_CAL_QCH_CAL32K_SCLK_QACTIVE_MAN_EN_Msk                                                           (0x1UL << AON_REG_OSC128K_CAL_QCH_CAL32K_SCLK_QACTIVE_MAN_EN_Pos)
+
+#define AON_REG_OSC128K_CAL_QCH_CAL32K_PCLK_QACTIVE_MAN_DATA_Pos                                                         2U
+#define AON_REG_OSC128K_CAL_QCH_CAL32K_PCLK_QACTIVE_MAN_DATA_Msk                                                         (0x1UL << AON_REG_OSC128K_CAL_QCH_CAL32K_PCLK_QACTIVE_MAN_DATA_Pos)
+
+#define AON_REG_OSC128K_CAL_QCH_CAL32K_PCLK_QACTIVE_MAN_EN_Pos                                                           3U
+#define AON_REG_OSC128K_CAL_QCH_CAL32K_PCLK_QACTIVE_MAN_EN_Msk                                                           (0x1UL << AON_REG_OSC128K_CAL_QCH_CAL32K_PCLK_QACTIVE_MAN_EN_Pos)
+
+#define AON_REG_OSC128K_CAL_QCH_CAL32K_OSC128K_QACTIVE_MAN_DATA_Pos                                                      4U
+#define AON_REG_OSC128K_CAL_QCH_CAL32K_OSC128K_QACTIVE_MAN_DATA_Msk                                                      (0x1UL << AON_REG_OSC128K_CAL_QCH_CAL32K_OSC128K_QACTIVE_MAN_DATA_Pos)
+
+#define AON_REG_OSC128K_CAL_QCH_CAL32K_OSC128K_QACTIVE_MAN_EN_Pos                                                        5U
+#define AON_REG_OSC128K_CAL_QCH_CAL32K_OSC128K_QACTIVE_MAN_EN_Msk                                                        (0x1UL << AON_REG_OSC128K_CAL_QCH_CAL32K_OSC128K_QACTIVE_MAN_EN_Pos)
+
+#define AON_REG_OSC128K_CAL_QCH_CAL32K_AONCLK_QACTIVE_MAN_DATA_Pos                                                       6U
+#define AON_REG_OSC128K_CAL_QCH_CAL32K_AONCLK_QACTIVE_MAN_DATA_Msk                                                       (0x1UL << AON_REG_OSC128K_CAL_QCH_CAL32K_AONCLK_QACTIVE_MAN_DATA_Pos)
+
+#define AON_REG_OSC128K_CAL_QCH_CAL32K_AONCLK_QACTIVE_MAN_EN_Pos                                                         7U
+#define AON_REG_OSC128K_CAL_QCH_CAL32K_AONCLK_QACTIVE_MAN_EN_Msk                                                         (0x1UL << AON_REG_OSC128K_CAL_QCH_CAL32K_AONCLK_QACTIVE_MAN_EN_Pos)
+
+#define AON_REG_OSC128K_CAL_QCH_RSVD_Pos                                                                                 8U
+#define AON_REG_OSC128K_CAL_QCH_RSVD_Msk                                                                                 (0xFFFFFFUL << AON_REG_OSC128K_CAL_QCH_RSVD_Pos)
+
+/* 0x600    0x4000_0600
+    10:0    R/W     RESERVED1                                                   11'b0000000000000
+    11      R       CP_DIS_XTAL_OUT                                             1'b0
+    12      R       XTAL_PKDET_OUT                                              1'b0
+    13      R/W     RESERVED                                                    1'b0
+    14      R       XTAL_CLK_OK                                                 1'b0
+    15      R/W     XTAL_EN_DAAC_GM                                             1'b0
+    18:16   R/W     XTAL_FREQ_SEL                                               3'h5
+    19      R/W     AAC_SEL                                                     1'b0
+    25:20   R/W     AAC_GM1                                                     6'h1f
+    31:26   R/W     AAC_GM                                                      6'h1f
+ */
+typedef union _AON_REG_40MXTAL_AON_REG0X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED1: 11;
+        uint32_t CP_DIS_XTAL_OUT: 1;
+        uint32_t XTAL_PKDET_OUT: 1;
+        uint32_t RESERVED: 1;
+        uint32_t XTAL_CLK_OK: 1;
+        uint32_t XTAL_EN_DAAC_GM: 1;
+        uint32_t XTAL_FREQ_SEL: 3;
+        uint32_t AAC_SEL: 1;
+        uint32_t AAC_GM1: 6;
+        uint32_t AAC_GM: 6;
+    };
+} AON_REG_40MXTAL_AON_REG0X_TYPE;
+
+/*0x4000_0600 AON_REG_40MXTAL_AON_REG0X*/
+#define AON_REG_40MXTAL_AON_REG0X_RESERVED1_Pos                                                                          0U
+#define AON_REG_40MXTAL_AON_REG0X_RESERVED1_Msk                                                                          (0x7FFUL << AON_REG_40MXTAL_AON_REG0X_RESERVED1_Pos)
+
+#define AON_REG_40MXTAL_AON_REG0X_CP_DIS_XTAL_OUT_Pos                                                                    11U
+#define AON_REG_40MXTAL_AON_REG0X_CP_DIS_XTAL_OUT_Msk                                                                    (0x1UL << AON_REG_40MXTAL_AON_REG0X_CP_DIS_XTAL_OUT_Pos)
+
+#define AON_REG_40MXTAL_AON_REG0X_XTAL_PKDET_OUT_Pos                                                                     12U
+#define AON_REG_40MXTAL_AON_REG0X_XTAL_PKDET_OUT_Msk                                                                     (0x1UL << AON_REG_40MXTAL_AON_REG0X_XTAL_PKDET_OUT_Pos)
+
+#define AON_REG_40MXTAL_AON_REG0X_RESERVED_Pos                                                                           13U
+#define AON_REG_40MXTAL_AON_REG0X_RESERVED_Msk                                                                           (0x1UL << AON_REG_40MXTAL_AON_REG0X_RESERVED_Pos)
+
+#define AON_REG_40MXTAL_AON_REG0X_XTAL_CLK_OK_Pos                                                                        14U
+#define AON_REG_40MXTAL_AON_REG0X_XTAL_CLK_OK_Msk                                                                        (0x1UL << AON_REG_40MXTAL_AON_REG0X_XTAL_CLK_OK_Pos)
+
+#define AON_REG_40MXTAL_AON_REG0X_XTAL_EN_DAAC_GM_Pos                                                                    15U
+#define AON_REG_40MXTAL_AON_REG0X_XTAL_EN_DAAC_GM_Msk                                                                    (0x1UL << AON_REG_40MXTAL_AON_REG0X_XTAL_EN_DAAC_GM_Pos)
+
+#define AON_REG_40MXTAL_AON_REG0X_XTAL_FREQ_SEL_Pos                                                                      16U
+#define AON_REG_40MXTAL_AON_REG0X_XTAL_FREQ_SEL_Msk                                                                      (0x7UL << AON_REG_40MXTAL_AON_REG0X_XTAL_FREQ_SEL_Pos)
+
+#define AON_REG_40MXTAL_AON_REG0X_AAC_SEL_Pos                                                                            19U
+#define AON_REG_40MXTAL_AON_REG0X_AAC_SEL_Msk                                                                            (0x1UL << AON_REG_40MXTAL_AON_REG0X_AAC_SEL_Pos)
+
+#define AON_REG_40MXTAL_AON_REG0X_AAC_GM1_Pos                                                                            20U
+#define AON_REG_40MXTAL_AON_REG0X_AAC_GM1_Msk                                                                            (0x3FUL << AON_REG_40MXTAL_AON_REG0X_AAC_GM1_Pos)
+
+#define AON_REG_40MXTAL_AON_REG0X_AAC_GM_Pos                                                                             26U
+#define AON_REG_40MXTAL_AON_REG0X_AAC_GM_Msk                                                                             (0x3FUL << AON_REG_40MXTAL_AON_REG0X_AAC_GM_Pos)
+
+/* 0x610    0x4000_0610
+    2:0     R/W     XTAL_SEL_MODE                                               3'b000
+    5:3     R/W     XTAL_MODE_DEBUG                                             3'h0
+    6       R/W     POW_XTAL                                                    1'b0
+    7       R/W     XTAL_EN_DEBUG                                               1'b0
+    8       R/W     ISO_XTALDIG                                                 1'b1
+    9       R/W     XTAL_SUPPLY_MODE                                            1'b0
+    10      R/W     ISO_VDDON_XTAL                                              1'b1
+    11      R/W     XTAL_EN_OK0_PC                                              1'b1
+    15:12   R/W     XTAL_RSVD                                                   4'b0000
+    31:16   R       XTAL_DUMMY0                                                 16'b0
+ */
+typedef union _AON_ANAPAR_XTAL_MODE_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t XTAL_SEL_MODE: 3;
+        uint32_t XTAL_MODE_DEBUG: 3;
+        uint32_t POW_XTAL: 1;
+        uint32_t XTAL_EN_DEBUG: 1;
+        uint32_t ISO_XTALDIG: 1;
+        uint32_t XTAL_SUPPLY_MODE: 1;
+        uint32_t ISO_VDDON_XTAL: 1;
+        uint32_t XTAL_EN_OK0_PC: 1;
+        uint32_t XTAL_RSVD: 4;
+        uint32_t XTAL_DUMMY0: 16;
+    };
+} AON_ANAPAR_XTAL_MODE_TYPE;
+
+/*0x4000_0610 AON_ANAPAR_XTAL_MODE*/
+#define AON_ANAPAR_XTAL_MODE_XTAL_SEL_MODE_Pos                                                                           0U
+#define AON_ANAPAR_XTAL_MODE_XTAL_SEL_MODE_Msk                                                                           (0x7UL << AON_ANAPAR_XTAL_MODE_XTAL_SEL_MODE_Pos)
+
+#define AON_ANAPAR_XTAL_MODE_XTAL_MODE_DEBUG_Pos                                                                         3U
+#define AON_ANAPAR_XTAL_MODE_XTAL_MODE_DEBUG_Msk                                                                         (0x7UL << AON_ANAPAR_XTAL_MODE_XTAL_MODE_DEBUG_Pos)
+
+#define AON_ANAPAR_XTAL_MODE_POW_XTAL_Pos                                                                                6U
+#define AON_ANAPAR_XTAL_MODE_POW_XTAL_Msk                                                                                (0x1UL << AON_ANAPAR_XTAL_MODE_POW_XTAL_Pos)
+
+#define AON_ANAPAR_XTAL_MODE_XTAL_EN_DEBUG_Pos                                                                           7U
+#define AON_ANAPAR_XTAL_MODE_XTAL_EN_DEBUG_Msk                                                                           (0x1UL << AON_ANAPAR_XTAL_MODE_XTAL_EN_DEBUG_Pos)
+
+#define AON_ANAPAR_XTAL_MODE_ISO_XTALDIG_Pos                                                                             8U
+#define AON_ANAPAR_XTAL_MODE_ISO_XTALDIG_Msk                                                                             (0x1UL << AON_ANAPAR_XTAL_MODE_ISO_XTALDIG_Pos)
+
+#define AON_ANAPAR_XTAL_MODE_XTAL_SUPPLY_MODE_Pos                                                                        9U
+#define AON_ANAPAR_XTAL_MODE_XTAL_SUPPLY_MODE_Msk                                                                        (0x1UL << AON_ANAPAR_XTAL_MODE_XTAL_SUPPLY_MODE_Pos)
+
+#define AON_ANAPAR_XTAL_MODE_ISO_VDDON_XTAL_Pos                                                                          10U
+#define AON_ANAPAR_XTAL_MODE_ISO_VDDON_XTAL_Msk                                                                          (0x1UL << AON_ANAPAR_XTAL_MODE_ISO_VDDON_XTAL_Pos)
+
+#define AON_ANAPAR_XTAL_MODE_XTAL_EN_OK0_PC_Pos                                                                          11U
+#define AON_ANAPAR_XTAL_MODE_XTAL_EN_OK0_PC_Msk                                                                          (0x1UL << AON_ANAPAR_XTAL_MODE_XTAL_EN_OK0_PC_Pos)
+
+#define AON_ANAPAR_XTAL_MODE_XTAL_RSVD_Pos                                                                               12U
+#define AON_ANAPAR_XTAL_MODE_XTAL_RSVD_Msk                                                                               (0xFUL << AON_ANAPAR_XTAL_MODE_XTAL_RSVD_Pos)
+
+#define AON_ANAPAR_XTAL_MODE_XTAL_DUMMY0_Pos                                                                             16U
+#define AON_ANAPAR_XTAL_MODE_XTAL_DUMMY0_Msk                                                                             (0xFFFFUL << AON_ANAPAR_XTAL_MODE_XTAL_DUMMY0_Pos)
+
+/* 0x614    0x4000_0614
+    0       R/W     XTAL_AAC_OK                                                 1'b0
+    6:1     R       Reserve1                                                    6'h1f
+    7       R       Reserve                                                     1'b0
+    8       R/W     XTAL_EN_AAC_PKDET                                           1'b0
+    9       R/W     XTAL_EN_LPS_CLK                                             1'b0
+    12:10   R/W     XTAL_SEL_DAAC_PK                                            3'b011
+    13      R/W     XTAL_BK_BG                                                  1'b0
+    14      R/W     XTAL_EN_GM_SEPERATE                                         1'b0
+    15      R/W     XTAL_EN_BDRF                                                1'b0
+    20:16   R/W     XTAL_SEL_BUF_GM_N                                           5'b01000
+    25:21   R/W     XTAL_SEL_BUF_GM_P                                           5'b01000
+    26      R/W     XTAL_SEL_AFE_DELAY                                          1'b0
+    27      R/W     XTAL_SEL_DIGI_DELAY                                         1'b0
+    28      R/W     XTAL_DOUBLE_OP_I                                            1'b0
+    30:29   R/W     XTAL_SEL_AFE_DRV                                            2'b00
+    31      R/W     XTAL_EN_RF_DRV_LATCH                                        1'b0
+ */
+typedef union _AON_ANAPAR_XTAL0_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t XTAL_AAC_OK: 1;
+        uint32_t Reserve1: 6;
+        uint32_t Reserve: 1;
+        uint32_t XTAL_EN_AAC_PKDET: 1;
+        uint32_t XTAL_EN_LPS_CLK: 1;
+        uint32_t XTAL_SEL_DAAC_PK: 3;
+        uint32_t XTAL_BK_BG: 1;
+        uint32_t XTAL_EN_GM_SEPERATE: 1;
+        uint32_t XTAL_EN_BDRF: 1;
+        uint32_t XTAL_SEL_BUF_GM_N: 5;
+        uint32_t XTAL_SEL_BUF_GM_P: 5;
+        uint32_t XTAL_SEL_AFE_DELAY: 1;
+        uint32_t XTAL_SEL_DIGI_DELAY: 1;
+        uint32_t XTAL_DOUBLE_OP_I: 1;
+        uint32_t XTAL_SEL_AFE_DRV: 2;
+        uint32_t XTAL_EN_RF_DRV_LATCH: 1;
+    };
+} AON_ANAPAR_XTAL0_TYPE;
+
+/*0x4000_0614 AON_ANAPAR_XTAL0*/
+#define AON_ANAPAR_XTAL0_XTAL_AAC_OK_Pos                                                                                 0U
+#define AON_ANAPAR_XTAL0_XTAL_AAC_OK_Msk                                                                                 (0x1UL << AON_ANAPAR_XTAL0_XTAL_AAC_OK_Pos)
+
+#define AON_ANAPAR_XTAL0_Reserve1_Pos                                                                                    1U
+#define AON_ANAPAR_XTAL0_Reserve1_Msk                                                                                    (0x3FUL << AON_ANAPAR_XTAL0_Reserve1_Pos)
+
+#define AON_ANAPAR_XTAL0_Reserve_Pos                                                                                     7U
+#define AON_ANAPAR_XTAL0_Reserve_Msk                                                                                     (0x1UL << AON_ANAPAR_XTAL0_Reserve_Pos)
+
+#define AON_ANAPAR_XTAL0_XTAL_EN_AAC_PKDET_Pos                                                                           8U
+#define AON_ANAPAR_XTAL0_XTAL_EN_AAC_PKDET_Msk                                                                           (0x1UL << AON_ANAPAR_XTAL0_XTAL_EN_AAC_PKDET_Pos)
+
+#define AON_ANAPAR_XTAL0_XTAL_EN_LPS_CLK_Pos                                                                             9U
+#define AON_ANAPAR_XTAL0_XTAL_EN_LPS_CLK_Msk                                                                             (0x1UL << AON_ANAPAR_XTAL0_XTAL_EN_LPS_CLK_Pos)
+
+#define AON_ANAPAR_XTAL0_XTAL_SEL_DAAC_PK_Pos                                                                            10U
+#define AON_ANAPAR_XTAL0_XTAL_SEL_DAAC_PK_Msk                                                                            (0x7UL << AON_ANAPAR_XTAL0_XTAL_SEL_DAAC_PK_Pos)
+
+#define AON_ANAPAR_XTAL0_XTAL_BK_BG_Pos                                                                                  13U
+#define AON_ANAPAR_XTAL0_XTAL_BK_BG_Msk                                                                                  (0x1UL << AON_ANAPAR_XTAL0_XTAL_BK_BG_Pos)
+
+#define AON_ANAPAR_XTAL0_XTAL_EN_GM_SEPERATE_Pos                                                                         14U
+#define AON_ANAPAR_XTAL0_XTAL_EN_GM_SEPERATE_Msk                                                                         (0x1UL << AON_ANAPAR_XTAL0_XTAL_EN_GM_SEPERATE_Pos)
+
+#define AON_ANAPAR_XTAL0_XTAL_EN_BDRF_Pos                                                                                15U
+#define AON_ANAPAR_XTAL0_XTAL_EN_BDRF_Msk                                                                                (0x1UL << AON_ANAPAR_XTAL0_XTAL_EN_BDRF_Pos)
+
+#define AON_ANAPAR_XTAL0_XTAL_SEL_BUF_GM_N_Pos                                                                           16U
+#define AON_ANAPAR_XTAL0_XTAL_SEL_BUF_GM_N_Msk                                                                           (0x1FUL << AON_ANAPAR_XTAL0_XTAL_SEL_BUF_GM_N_Pos)
+
+#define AON_ANAPAR_XTAL0_XTAL_SEL_BUF_GM_P_Pos                                                                           21U
+#define AON_ANAPAR_XTAL0_XTAL_SEL_BUF_GM_P_Msk                                                                           (0x1FUL << AON_ANAPAR_XTAL0_XTAL_SEL_BUF_GM_P_Pos)
+
+#define AON_ANAPAR_XTAL0_XTAL_SEL_AFE_DELAY_Pos                                                                          26U
+#define AON_ANAPAR_XTAL0_XTAL_SEL_AFE_DELAY_Msk                                                                          (0x1UL << AON_ANAPAR_XTAL0_XTAL_SEL_AFE_DELAY_Pos)
+
+#define AON_ANAPAR_XTAL0_XTAL_SEL_DIGI_DELAY_Pos                                                                         27U
+#define AON_ANAPAR_XTAL0_XTAL_SEL_DIGI_DELAY_Msk                                                                         (0x1UL << AON_ANAPAR_XTAL0_XTAL_SEL_DIGI_DELAY_Pos)
+
+#define AON_ANAPAR_XTAL0_XTAL_DOUBLE_OP_I_Pos                                                                            28U
+#define AON_ANAPAR_XTAL0_XTAL_DOUBLE_OP_I_Msk                                                                            (0x1UL << AON_ANAPAR_XTAL0_XTAL_DOUBLE_OP_I_Pos)
+
+#define AON_ANAPAR_XTAL0_XTAL_SEL_AFE_DRV_Pos                                                                            29U
+#define AON_ANAPAR_XTAL0_XTAL_SEL_AFE_DRV_Msk                                                                            (0x3UL << AON_ANAPAR_XTAL0_XTAL_SEL_AFE_DRV_Pos)
+
+#define AON_ANAPAR_XTAL0_XTAL_EN_RF_DRV_LATCH_Pos                                                                        31U
+#define AON_ANAPAR_XTAL0_XTAL_EN_RF_DRV_LATCH_Msk                                                                        (0x1UL << AON_ANAPAR_XTAL0_XTAL_EN_RF_DRV_LATCH_Pos)
+
+/* 0x618    0x4000_0618
+    1:0     R/W     XTAL_SEL_DIGI_DRV                                           2'b00
+    3:2     R/W     XTAL_SEL_RF_DRV                                             2'b00
+    4       R/W     XTAL_GATED_AFEP                                             1'b0
+    5       R/W     XTAL_GATED_AFEN                                             1'b0
+    6       R/W     XTAL_GATED_DIGIP                                            1'b0
+    7       R/W     XTAL_GATED_DIGIN                                            1'b0
+    8       R/W     XTAL_GATED_RFP                                              1'b0
+    9       R/W     XTAL_GATED_RFN                                              1'b0
+    11:10   R/W     XTAL_SEL_LPS_DRV                                            2'b00
+    12      R/W     XTAL_GATED_LPS                                              1'b0
+    15:13   R/W     XTAL_SEL_LPS_DIV                                            3'b111
+    18:16   R/W     XTAL_TUNE_LDO_VOUT                                          3'b011
+    21:19   R/W     XTAL_TUNE_LDO_VOUT_OK0                                      3'b011
+    24:22   R/W     XTAL_SEL_TOK                                                3'b011
+    25      R/W     XTAL_EN_LDO2PWRCUT                                          1'b0
+    28:26   R/W     XTAL_SEL_XORES                                              3'b000
+    29      R/W     XTAL_LDOPC_SEL                                              1'b0
+    30      R/W     XTAL_SEL_BUF_LPS                                            1'b0
+    31      R/W     XTAL_LPMODE_CLK_SEL                                         1'b0
+ */
+typedef union _AON_ANAPAR_XTAL2_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t XTAL_SEL_DIGI_DRV: 2;
+        uint32_t XTAL_SEL_RF_DRV: 2;
+        uint32_t XTAL_GATED_AFEP: 1;
+        uint32_t XTAL_GATED_AFEN: 1;
+        uint32_t XTAL_GATED_DIGIP: 1;
+        uint32_t XTAL_GATED_DIGIN: 1;
+        uint32_t XTAL_GATED_RFP: 1;
+        uint32_t XTAL_GATED_RFN: 1;
+        uint32_t XTAL_SEL_LPS_DRV: 2;
+        uint32_t XTAL_GATED_LPS: 1;
+        uint32_t XTAL_SEL_LPS_DIV: 3;
+        uint32_t XTAL_TUNE_LDO_VOUT: 3;
+        uint32_t XTAL_TUNE_LDO_VOUT_OK0: 3;
+        uint32_t XTAL_SEL_TOK: 3;
+        uint32_t XTAL_EN_LDO2PWRCUT: 1;
+        uint32_t XTAL_SEL_XORES: 3;
+        uint32_t XTAL_LDOPC_SEL: 1;
+        uint32_t XTAL_SEL_BUF_LPS: 1;
+        uint32_t XTAL_LPMODE_CLK_SEL: 1;
+    };
+} AON_ANAPAR_XTAL2_TYPE;
+
+/*0x4000_0618 AON_ANAPAR_XTAL2*/
+#define AON_ANAPAR_XTAL2_XTAL_SEL_DIGI_DRV_Pos                                                                           0U
+#define AON_ANAPAR_XTAL2_XTAL_SEL_DIGI_DRV_Msk                                                                           (0x3UL << AON_ANAPAR_XTAL2_XTAL_SEL_DIGI_DRV_Pos)
+
+#define AON_ANAPAR_XTAL2_XTAL_SEL_RF_DRV_Pos                                                                             2U
+#define AON_ANAPAR_XTAL2_XTAL_SEL_RF_DRV_Msk                                                                             (0x3UL << AON_ANAPAR_XTAL2_XTAL_SEL_RF_DRV_Pos)
+
+#define AON_ANAPAR_XTAL2_XTAL_GATED_AFEP_Pos                                                                             4U
+#define AON_ANAPAR_XTAL2_XTAL_GATED_AFEP_Msk                                                                             (0x1UL << AON_ANAPAR_XTAL2_XTAL_GATED_AFEP_Pos)
+
+#define AON_ANAPAR_XTAL2_XTAL_GATED_AFEN_Pos                                                                             5U
+#define AON_ANAPAR_XTAL2_XTAL_GATED_AFEN_Msk                                                                             (0x1UL << AON_ANAPAR_XTAL2_XTAL_GATED_AFEN_Pos)
+
+#define AON_ANAPAR_XTAL2_XTAL_GATED_DIGIP_Pos                                                                            6U
+#define AON_ANAPAR_XTAL2_XTAL_GATED_DIGIP_Msk                                                                            (0x1UL << AON_ANAPAR_XTAL2_XTAL_GATED_DIGIP_Pos)
+
+#define AON_ANAPAR_XTAL2_XTAL_GATED_DIGIN_Pos                                                                            7U
+#define AON_ANAPAR_XTAL2_XTAL_GATED_DIGIN_Msk                                                                            (0x1UL << AON_ANAPAR_XTAL2_XTAL_GATED_DIGIN_Pos)
+
+#define AON_ANAPAR_XTAL2_XTAL_GATED_RFP_Pos                                                                              8U
+#define AON_ANAPAR_XTAL2_XTAL_GATED_RFP_Msk                                                                              (0x1UL << AON_ANAPAR_XTAL2_XTAL_GATED_RFP_Pos)
+
+#define AON_ANAPAR_XTAL2_XTAL_GATED_RFN_Pos                                                                              9U
+#define AON_ANAPAR_XTAL2_XTAL_GATED_RFN_Msk                                                                              (0x1UL << AON_ANAPAR_XTAL2_XTAL_GATED_RFN_Pos)
+
+#define AON_ANAPAR_XTAL2_XTAL_SEL_LPS_DRV_Pos                                                                            10U
+#define AON_ANAPAR_XTAL2_XTAL_SEL_LPS_DRV_Msk                                                                            (0x3UL << AON_ANAPAR_XTAL2_XTAL_SEL_LPS_DRV_Pos)
+
+#define AON_ANAPAR_XTAL2_XTAL_GATED_LPS_Pos                                                                              12U
+#define AON_ANAPAR_XTAL2_XTAL_GATED_LPS_Msk                                                                              (0x1UL << AON_ANAPAR_XTAL2_XTAL_GATED_LPS_Pos)
+
+#define AON_ANAPAR_XTAL2_XTAL_SEL_LPS_DIV_Pos                                                                            13U
+#define AON_ANAPAR_XTAL2_XTAL_SEL_LPS_DIV_Msk                                                                            (0x7UL << AON_ANAPAR_XTAL2_XTAL_SEL_LPS_DIV_Pos)
+
+#define AON_ANAPAR_XTAL2_XTAL_TUNE_LDO_VOUT_Pos                                                                          16U
+#define AON_ANAPAR_XTAL2_XTAL_TUNE_LDO_VOUT_Msk                                                                          (0x7UL << AON_ANAPAR_XTAL2_XTAL_TUNE_LDO_VOUT_Pos)
+
+#define AON_ANAPAR_XTAL2_XTAL_TUNE_LDO_VOUT_OK0_Pos                                                                      19U
+#define AON_ANAPAR_XTAL2_XTAL_TUNE_LDO_VOUT_OK0_Msk                                                                      (0x7UL << AON_ANAPAR_XTAL2_XTAL_TUNE_LDO_VOUT_OK0_Pos)
+
+#define AON_ANAPAR_XTAL2_XTAL_SEL_TOK_Pos                                                                                22U
+#define AON_ANAPAR_XTAL2_XTAL_SEL_TOK_Msk                                                                                (0x7UL << AON_ANAPAR_XTAL2_XTAL_SEL_TOK_Pos)
+
+#define AON_ANAPAR_XTAL2_XTAL_EN_LDO2PWRCUT_Pos                                                                          25U
+#define AON_ANAPAR_XTAL2_XTAL_EN_LDO2PWRCUT_Msk                                                                          (0x1UL << AON_ANAPAR_XTAL2_XTAL_EN_LDO2PWRCUT_Pos)
+
+#define AON_ANAPAR_XTAL2_XTAL_SEL_XORES_Pos                                                                              26U
+#define AON_ANAPAR_XTAL2_XTAL_SEL_XORES_Msk                                                                              (0x7UL << AON_ANAPAR_XTAL2_XTAL_SEL_XORES_Pos)
+
+#define AON_ANAPAR_XTAL2_XTAL_LDOPC_SEL_Pos                                                                              29U
+#define AON_ANAPAR_XTAL2_XTAL_LDOPC_SEL_Msk                                                                              (0x1UL << AON_ANAPAR_XTAL2_XTAL_LDOPC_SEL_Pos)
+
+#define AON_ANAPAR_XTAL2_XTAL_SEL_BUF_LPS_Pos                                                                            30U
+#define AON_ANAPAR_XTAL2_XTAL_SEL_BUF_LPS_Msk                                                                            (0x1UL << AON_ANAPAR_XTAL2_XTAL_SEL_BUF_LPS_Pos)
+
+#define AON_ANAPAR_XTAL2_XTAL_LPMODE_CLK_SEL_Pos                                                                         31U
+#define AON_ANAPAR_XTAL2_XTAL_LPMODE_CLK_SEL_Msk                                                                         (0x1UL << AON_ANAPAR_XTAL2_XTAL_LPMODE_CLK_SEL_Pos)
+
+/* 0x61C    0x4000_061c
+    7:0     R/W     XTAL_TUNE_SC_INI                                            8'b01110000
+    15:8    R/W     XTAL_TUNE_SC_LP                                             8'b01111111
+    23:16   R/W     XTAL_TUNE_SC_XI_FREQ                                        8'b00111111
+    31:24   R/W     XTAL_TUNE_SC_XO_FREQ                                        8'b00111111
+ */
+typedef union _AON_ANAPAR_XTAL4_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t XTAL_TUNE_SC_INI: 8;
+        uint32_t XTAL_TUNE_SC_LP: 8;
+        uint32_t XTAL_TUNE_SC_XI_FREQ: 8;
+        uint32_t XTAL_TUNE_SC_XO_FREQ: 8;
+    };
+} AON_ANAPAR_XTAL4_TYPE;
+
+/*0x4000_061c AON_ANAPAR_XTAL4*/
+#define AON_ANAPAR_XTAL4_XTAL_TUNE_SC_INI_Pos                                                                            0U
+#define AON_ANAPAR_XTAL4_XTAL_TUNE_SC_INI_Msk                                                                            (0xFFUL << AON_ANAPAR_XTAL4_XTAL_TUNE_SC_INI_Pos)
+
+#define AON_ANAPAR_XTAL4_XTAL_TUNE_SC_LP_Pos                                                                             8U
+#define AON_ANAPAR_XTAL4_XTAL_TUNE_SC_LP_Msk                                                                             (0xFFUL << AON_ANAPAR_XTAL4_XTAL_TUNE_SC_LP_Pos)
+
+#define AON_ANAPAR_XTAL4_XTAL_TUNE_SC_XI_FREQ_Pos                                                                        16U
+#define AON_ANAPAR_XTAL4_XTAL_TUNE_SC_XI_FREQ_Msk                                                                        (0xFFUL << AON_ANAPAR_XTAL4_XTAL_TUNE_SC_XI_FREQ_Pos)
+
+#define AON_ANAPAR_XTAL4_XTAL_TUNE_SC_XO_FREQ_Pos                                                                        24U
+#define AON_ANAPAR_XTAL4_XTAL_TUNE_SC_XO_FREQ_Msk                                                                        (0xFFUL << AON_ANAPAR_XTAL4_XTAL_TUNE_SC_XO_FREQ_Pos)
+
+/* 0x620    0x4000_0620
+    0       R/W     XTAL_LPMODE_CLK_AON                                         1'b1
+    1       R/W     XTAL_IOP_SEL                                                1'b0
+    2       R/W     XTAL_PKDET_CMP_SWAP                                         1'b0
+    3       R/W     XTAL_PKDET_LOAD_SWAP                                        1'b0
+    6:4     R/W     XTAL_SEL_TOK01                                              3'b010
+    7       R/W     XTAL_EN_XTAL_SEL_TOK01                                      1'b1
+    8       R/W     XTAL_EN_XO_CLK_SW                                           1'b0
+    9       R/W     XTAL_FASTSET_MANU                                           1'b0
+    11:10   R/W     XTAL_SEL_AAAC_CAP                                           2'b11
+    13:12   R/W     XTAL_SEL_AAAC_IOFFSET                                       2'b00
+    15:14   R/W     XTAL_SEL_AAAC_OP_CUR                                        2'b00
+    16      R/W     XTAL_EN_AAAC_TIE_MID                                        1'b0
+    17      R/W     XTAL_EN_LPCNT_CLK_DIV                                       1'b0
+    18      R/W     XTAL_EN_PDCK_VREF                                           1'b1
+    19      R/W     XTAL_EN_CAP_CTRL_OK0                                        1'b0
+    20      R/W     XTAL_EN_GM_CTRL_OK0                                         1'b0
+    21      R/W     XTAL_EN_GM_CTRL_LP                                          1'b0
+    23:22   R/W     XTAL_GM_OV_RATIO                                            2'b10
+    25:24   R/W     XTAL_OV_RATIO                                               2'b10
+    26      R/W     XTAL_EN_PDCK_MANU                                           1'b0
+    27      R/W     XTAL_PDCK_OK                                                1'b0
+    28      R/W     XTAL_PDCK_OK_MANU                                           1'b0
+    30:29   R/W     XTAL_SEL_AAAC_PKDET_SW                                      2'b01
+    31      R/W     XTAL_EN_CAP_CTRL_LPMODE                                     1'b0
+ */
+typedef union _AON_ANAPAR_XTAL6_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t XTAL_LPMODE_CLK_AON: 1;
+        uint32_t XTAL_IOP_SEL: 1;
+        uint32_t XTAL_PKDET_CMP_SWAP: 1;
+        uint32_t XTAL_PKDET_LOAD_SWAP: 1;
+        uint32_t XTAL_SEL_TOK01: 3;
+        uint32_t XTAL_EN_XTAL_SEL_TOK01: 1;
+        uint32_t XTAL_EN_XO_CLK_SW: 1;
+        uint32_t XTAL_FASTSET_MANU: 1;
+        uint32_t XTAL_SEL_AAAC_CAP: 2;
+        uint32_t XTAL_SEL_AAAC_IOFFSET: 2;
+        uint32_t XTAL_SEL_AAAC_OP_CUR: 2;
+        uint32_t XTAL_EN_AAAC_TIE_MID: 1;
+        uint32_t XTAL_EN_LPCNT_CLK_DIV: 1;
+        uint32_t XTAL_EN_PDCK_VREF: 1;
+        uint32_t XTAL_EN_CAP_CTRL_OK0: 1;
+        uint32_t XTAL_EN_GM_CTRL_OK0: 1;
+        uint32_t XTAL_EN_GM_CTRL_LP: 1;
+        uint32_t XTAL_GM_OV_RATIO: 2;
+        uint32_t XTAL_OV_RATIO: 2;
+        uint32_t XTAL_EN_PDCK_MANU: 1;
+        uint32_t XTAL_PDCK_OK: 1;
+        uint32_t XTAL_PDCK_OK_MANU: 1;
+        uint32_t XTAL_SEL_AAAC_PKDET_SW: 2;
+        uint32_t XTAL_EN_CAP_CTRL_LPMODE: 1;
+    };
+} AON_ANAPAR_XTAL6_TYPE;
+
+/*0x4000_0620 AON_ANAPAR_XTAL6*/
+#define AON_ANAPAR_XTAL6_XTAL_LPMODE_CLK_AON_Pos                                                                         0U
+#define AON_ANAPAR_XTAL6_XTAL_LPMODE_CLK_AON_Msk                                                                         (0x1UL << AON_ANAPAR_XTAL6_XTAL_LPMODE_CLK_AON_Pos)
+
+#define AON_ANAPAR_XTAL6_XTAL_IOP_SEL_Pos                                                                                1U
+#define AON_ANAPAR_XTAL6_XTAL_IOP_SEL_Msk                                                                                (0x1UL << AON_ANAPAR_XTAL6_XTAL_IOP_SEL_Pos)
+
+#define AON_ANAPAR_XTAL6_XTAL_PKDET_CMP_SWAP_Pos                                                                         2U
+#define AON_ANAPAR_XTAL6_XTAL_PKDET_CMP_SWAP_Msk                                                                         (0x1UL << AON_ANAPAR_XTAL6_XTAL_PKDET_CMP_SWAP_Pos)
+
+#define AON_ANAPAR_XTAL6_XTAL_PKDET_LOAD_SWAP_Pos                                                                        3U
+#define AON_ANAPAR_XTAL6_XTAL_PKDET_LOAD_SWAP_Msk                                                                        (0x1UL << AON_ANAPAR_XTAL6_XTAL_PKDET_LOAD_SWAP_Pos)
+
+#define AON_ANAPAR_XTAL6_XTAL_SEL_TOK01_Pos                                                                              4U
+#define AON_ANAPAR_XTAL6_XTAL_SEL_TOK01_Msk                                                                              (0x7UL << AON_ANAPAR_XTAL6_XTAL_SEL_TOK01_Pos)
+
+#define AON_ANAPAR_XTAL6_XTAL_EN_XTAL_SEL_TOK01_Pos                                                                      7U
+#define AON_ANAPAR_XTAL6_XTAL_EN_XTAL_SEL_TOK01_Msk                                                                      (0x1UL << AON_ANAPAR_XTAL6_XTAL_EN_XTAL_SEL_TOK01_Pos)
+
+#define AON_ANAPAR_XTAL6_XTAL_EN_XO_CLK_SW_Pos                                                                           8U
+#define AON_ANAPAR_XTAL6_XTAL_EN_XO_CLK_SW_Msk                                                                           (0x1UL << AON_ANAPAR_XTAL6_XTAL_EN_XO_CLK_SW_Pos)
+
+#define AON_ANAPAR_XTAL6_XTAL_FASTSET_MANU_Pos                                                                           9U
+#define AON_ANAPAR_XTAL6_XTAL_FASTSET_MANU_Msk                                                                           (0x1UL << AON_ANAPAR_XTAL6_XTAL_FASTSET_MANU_Pos)
+
+#define AON_ANAPAR_XTAL6_XTAL_SEL_AAAC_CAP_Pos                                                                           10U
+#define AON_ANAPAR_XTAL6_XTAL_SEL_AAAC_CAP_Msk                                                                           (0x3UL << AON_ANAPAR_XTAL6_XTAL_SEL_AAAC_CAP_Pos)
+
+#define AON_ANAPAR_XTAL6_XTAL_SEL_AAAC_IOFFSET_Pos                                                                       12U
+#define AON_ANAPAR_XTAL6_XTAL_SEL_AAAC_IOFFSET_Msk                                                                       (0x3UL << AON_ANAPAR_XTAL6_XTAL_SEL_AAAC_IOFFSET_Pos)
+
+#define AON_ANAPAR_XTAL6_XTAL_SEL_AAAC_OP_CUR_Pos                                                                        14U
+#define AON_ANAPAR_XTAL6_XTAL_SEL_AAAC_OP_CUR_Msk                                                                        (0x3UL << AON_ANAPAR_XTAL6_XTAL_SEL_AAAC_OP_CUR_Pos)
+
+#define AON_ANAPAR_XTAL6_XTAL_EN_AAAC_TIE_MID_Pos                                                                        16U
+#define AON_ANAPAR_XTAL6_XTAL_EN_AAAC_TIE_MID_Msk                                                                        (0x1UL << AON_ANAPAR_XTAL6_XTAL_EN_AAAC_TIE_MID_Pos)
+
+#define AON_ANAPAR_XTAL6_XTAL_EN_LPCNT_CLK_DIV_Pos                                                                       17U
+#define AON_ANAPAR_XTAL6_XTAL_EN_LPCNT_CLK_DIV_Msk                                                                       (0x1UL << AON_ANAPAR_XTAL6_XTAL_EN_LPCNT_CLK_DIV_Pos)
+
+#define AON_ANAPAR_XTAL6_XTAL_EN_PDCK_VREF_Pos                                                                           18U
+#define AON_ANAPAR_XTAL6_XTAL_EN_PDCK_VREF_Msk                                                                           (0x1UL << AON_ANAPAR_XTAL6_XTAL_EN_PDCK_VREF_Pos)
+
+#define AON_ANAPAR_XTAL6_XTAL_EN_CAP_CTRL_OK0_Pos                                                                        19U
+#define AON_ANAPAR_XTAL6_XTAL_EN_CAP_CTRL_OK0_Msk                                                                        (0x1UL << AON_ANAPAR_XTAL6_XTAL_EN_CAP_CTRL_OK0_Pos)
+
+#define AON_ANAPAR_XTAL6_XTAL_EN_GM_CTRL_OK0_Pos                                                                         20U
+#define AON_ANAPAR_XTAL6_XTAL_EN_GM_CTRL_OK0_Msk                                                                         (0x1UL << AON_ANAPAR_XTAL6_XTAL_EN_GM_CTRL_OK0_Pos)
+
+#define AON_ANAPAR_XTAL6_XTAL_EN_GM_CTRL_LP_Pos                                                                          21U
+#define AON_ANAPAR_XTAL6_XTAL_EN_GM_CTRL_LP_Msk                                                                          (0x1UL << AON_ANAPAR_XTAL6_XTAL_EN_GM_CTRL_LP_Pos)
+
+#define AON_ANAPAR_XTAL6_XTAL_GM_OV_RATIO_Pos                                                                            22U
+#define AON_ANAPAR_XTAL6_XTAL_GM_OV_RATIO_Msk                                                                            (0x3UL << AON_ANAPAR_XTAL6_XTAL_GM_OV_RATIO_Pos)
+
+#define AON_ANAPAR_XTAL6_XTAL_OV_RATIO_Pos                                                                               24U
+#define AON_ANAPAR_XTAL6_XTAL_OV_RATIO_Msk                                                                               (0x3UL << AON_ANAPAR_XTAL6_XTAL_OV_RATIO_Pos)
+
+#define AON_ANAPAR_XTAL6_XTAL_EN_PDCK_MANU_Pos                                                                           26U
+#define AON_ANAPAR_XTAL6_XTAL_EN_PDCK_MANU_Msk                                                                           (0x1UL << AON_ANAPAR_XTAL6_XTAL_EN_PDCK_MANU_Pos)
+
+#define AON_ANAPAR_XTAL6_XTAL_PDCK_OK_Pos                                                                                27U
+#define AON_ANAPAR_XTAL6_XTAL_PDCK_OK_Msk                                                                                (0x1UL << AON_ANAPAR_XTAL6_XTAL_PDCK_OK_Pos)
+
+#define AON_ANAPAR_XTAL6_XTAL_PDCK_OK_MANU_Pos                                                                           28U
+#define AON_ANAPAR_XTAL6_XTAL_PDCK_OK_MANU_Msk                                                                           (0x1UL << AON_ANAPAR_XTAL6_XTAL_PDCK_OK_MANU_Pos)
+
+#define AON_ANAPAR_XTAL6_XTAL_SEL_AAAC_PKDET_SW_Pos                                                                      29U
+#define AON_ANAPAR_XTAL6_XTAL_SEL_AAAC_PKDET_SW_Msk                                                                      (0x3UL << AON_ANAPAR_XTAL6_XTAL_SEL_AAAC_PKDET_SW_Pos)
+
+#define AON_ANAPAR_XTAL6_XTAL_EN_CAP_CTRL_LPMODE_Pos                                                                     31U
+#define AON_ANAPAR_XTAL6_XTAL_EN_CAP_CTRL_LPMODE_Msk                                                                     (0x1UL << AON_ANAPAR_XTAL6_XTAL_EN_CAP_CTRL_LPMODE_Pos)
+
+/* 0x624    0x4000_0624
+    4:0     R/W     XTAL_PDCK_VREF                                              5'b10000
+    9:5     R/W     XTAL_AAAC_VREF_MANU                                         5'b10000
+    11:10   R/W     XTAL_LPS_CAP_CYC                                            2'b01
+    13:12   R/W     XTAL_LPS_CAP_STEP                                           2'b01
+    15:14   R/W     XTAL_SEL_CP_DISABLE_CYCLE                                   2'b11
+    16      R/W     XTAL_EN_PLL_CP_ALWAYS_ON                                    1'b0
+    17      R/W     XTAL_DEBUG_CAP_CTRL                                         1'b0
+    18      R/W     XTAL_DEBUG_GM_CTRL                                          1'b0
+    19      R/W     XTAL_EN_FW_CTRL_GATED_B                                     1'b1
+    25:20   R/W     XTAL_GM                                                     6'b111111
+    27:26   R/W     XTAL_GM_CYC                                                 2'b10
+    29:28   R/W     XTAL_GM_STEP                                                2'b10
+    30      R/W     XTAL_HP_IBGPMU_SEL                                          1'b1
+    31      R/W     XTAL_LPLDO_SEL                                              1'b0
+ */
+typedef union _AON_ANAPAR_XTAL8_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t XTAL_PDCK_VREF: 5;
+        uint32_t XTAL_AAAC_VREF_MANU: 5;
+        uint32_t XTAL_LPS_CAP_CYC: 2;
+        uint32_t XTAL_LPS_CAP_STEP: 2;
+        uint32_t XTAL_SEL_CP_DISABLE_CYCLE: 2;
+        uint32_t XTAL_EN_PLL_CP_ALWAYS_ON: 1;
+        uint32_t XTAL_DEBUG_CAP_CTRL: 1;
+        uint32_t XTAL_DEBUG_GM_CTRL: 1;
+        uint32_t XTAL_EN_FW_CTRL_GATED_B: 1;
+        uint32_t XTAL_GM: 6;
+        uint32_t XTAL_GM_CYC: 2;
+        uint32_t XTAL_GM_STEP: 2;
+        uint32_t XTAL_HP_IBGPMU_SEL: 1;
+        uint32_t XTAL_LPLDO_SEL: 1;
+    };
+} AON_ANAPAR_XTAL8_TYPE;
+
+/*0x4000_0624 AON_ANAPAR_XTAL8*/
+#define AON_ANAPAR_XTAL8_XTAL_PDCK_VREF_Pos                                                                              0U
+#define AON_ANAPAR_XTAL8_XTAL_PDCK_VREF_Msk                                                                              (0x1FUL << AON_ANAPAR_XTAL8_XTAL_PDCK_VREF_Pos)
+
+#define AON_ANAPAR_XTAL8_XTAL_AAAC_VREF_MANU_Pos                                                                         5U
+#define AON_ANAPAR_XTAL8_XTAL_AAAC_VREF_MANU_Msk                                                                         (0x1FUL << AON_ANAPAR_XTAL8_XTAL_AAAC_VREF_MANU_Pos)
+
+#define AON_ANAPAR_XTAL8_XTAL_LPS_CAP_CYC_Pos                                                                            10U
+#define AON_ANAPAR_XTAL8_XTAL_LPS_CAP_CYC_Msk                                                                            (0x3UL << AON_ANAPAR_XTAL8_XTAL_LPS_CAP_CYC_Pos)
+
+#define AON_ANAPAR_XTAL8_XTAL_LPS_CAP_STEP_Pos                                                                           12U
+#define AON_ANAPAR_XTAL8_XTAL_LPS_CAP_STEP_Msk                                                                           (0x3UL << AON_ANAPAR_XTAL8_XTAL_LPS_CAP_STEP_Pos)
+
+#define AON_ANAPAR_XTAL8_XTAL_SEL_CP_DISABLE_CYCLE_Pos                                                                   14U
+#define AON_ANAPAR_XTAL8_XTAL_SEL_CP_DISABLE_CYCLE_Msk                                                                   (0x3UL << AON_ANAPAR_XTAL8_XTAL_SEL_CP_DISABLE_CYCLE_Pos)
+
+#define AON_ANAPAR_XTAL8_XTAL_EN_PLL_CP_ALWAYS_ON_Pos                                                                    16U
+#define AON_ANAPAR_XTAL8_XTAL_EN_PLL_CP_ALWAYS_ON_Msk                                                                    (0x1UL << AON_ANAPAR_XTAL8_XTAL_EN_PLL_CP_ALWAYS_ON_Pos)
+
+#define AON_ANAPAR_XTAL8_XTAL_DEBUG_CAP_CTRL_Pos                                                                         17U
+#define AON_ANAPAR_XTAL8_XTAL_DEBUG_CAP_CTRL_Msk                                                                         (0x1UL << AON_ANAPAR_XTAL8_XTAL_DEBUG_CAP_CTRL_Pos)
+
+#define AON_ANAPAR_XTAL8_XTAL_DEBUG_GM_CTRL_Pos                                                                          18U
+#define AON_ANAPAR_XTAL8_XTAL_DEBUG_GM_CTRL_Msk                                                                          (0x1UL << AON_ANAPAR_XTAL8_XTAL_DEBUG_GM_CTRL_Pos)
+
+#define AON_ANAPAR_XTAL8_XTAL_EN_FW_CTRL_GATED_B_Pos                                                                     19U
+#define AON_ANAPAR_XTAL8_XTAL_EN_FW_CTRL_GATED_B_Msk                                                                     (0x1UL << AON_ANAPAR_XTAL8_XTAL_EN_FW_CTRL_GATED_B_Pos)
+
+#define AON_ANAPAR_XTAL8_XTAL_GM_Pos                                                                                     20U
+#define AON_ANAPAR_XTAL8_XTAL_GM_Msk                                                                                     (0x3FUL << AON_ANAPAR_XTAL8_XTAL_GM_Pos)
+
+#define AON_ANAPAR_XTAL8_XTAL_GM_CYC_Pos                                                                                 26U
+#define AON_ANAPAR_XTAL8_XTAL_GM_CYC_Msk                                                                                 (0x3UL << AON_ANAPAR_XTAL8_XTAL_GM_CYC_Pos)
+
+#define AON_ANAPAR_XTAL8_XTAL_GM_STEP_Pos                                                                                28U
+#define AON_ANAPAR_XTAL8_XTAL_GM_STEP_Msk                                                                                (0x3UL << AON_ANAPAR_XTAL8_XTAL_GM_STEP_Pos)
+
+#define AON_ANAPAR_XTAL8_XTAL_HP_IBGPMU_SEL_Pos                                                                          30U
+#define AON_ANAPAR_XTAL8_XTAL_HP_IBGPMU_SEL_Msk                                                                          (0x1UL << AON_ANAPAR_XTAL8_XTAL_HP_IBGPMU_SEL_Pos)
+
+#define AON_ANAPAR_XTAL8_XTAL_LPLDO_SEL_Pos                                                                              31U
+#define AON_ANAPAR_XTAL8_XTAL_LPLDO_SEL_Msk                                                                              (0x1UL << AON_ANAPAR_XTAL8_XTAL_LPLDO_SEL_Pos)
+
+/* 0x628    0x4000_0628
+    1:0     R/W     XTAL_SEL_LDOFASTSET_CYCLE                                   2'b01
+    2       R/W     XTAL_EN_LPMODE_AUTO_GATED                                   1'b0
+    3       R/W     XTAL_LP_GATE_FW_CTRL_B                                      1'b0
+    6:4     R/W     XTAL_MODE_DEBUG_CAP_CTRL                                    3'b000
+    9:7     R/W     XTAL_MODE_DEBUG_GM_CTRL                                     3'b000
+    10      R/W     XTAL_EN_NMDAAC                                              1'b1
+    11      R/W     XTAL_NMPC_SEL                                               1'b1
+    12      R/W     XTAL_LPS_GM_CTRL                                            1'b0
+    13      R/W     XTAL_EN_SUPPLY_MODE_CTRLBYFASTAON_B                         1'b1
+    14      R/W     XTAL_EN_SUPPLY_MODE_FASTAON                                 1'b1
+    15      R/W     XTAL_PDCK_BUSY                                              1'b0
+    31:16   R/W     XTAL_CTRL                                                   16'b0000000000000000
+ */
+typedef union _AON_ANAPAR_XTAL10_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t XTAL_SEL_LDOFASTSET_CYCLE: 2;
+        uint32_t XTAL_EN_LPMODE_AUTO_GATED: 1;
+        uint32_t XTAL_LP_GATE_FW_CTRL_B: 1;
+        uint32_t XTAL_MODE_DEBUG_CAP_CTRL: 3;
+        uint32_t XTAL_MODE_DEBUG_GM_CTRL: 3;
+        uint32_t XTAL_EN_NMDAAC: 1;
+        uint32_t XTAL_NMPC_SEL: 1;
+        uint32_t XTAL_LPS_GM_CTRL: 1;
+        uint32_t XTAL_EN_SUPPLY_MODE_CTRLBYFASTAON_B: 1;
+        uint32_t XTAL_EN_SUPPLY_MODE_FASTAON: 1;
+        uint32_t XTAL_PDCK_BUSY: 1;
+        uint32_t XTAL_CTRL: 16;
+    };
+} AON_ANAPAR_XTAL10_TYPE;
+
+/*0x4000_0628 AON_ANAPAR_XTAL10*/
+#define AON_ANAPAR_XTAL10_XTAL_SEL_LDOFASTSET_CYCLE_Pos                                                                  0U
+#define AON_ANAPAR_XTAL10_XTAL_SEL_LDOFASTSET_CYCLE_Msk                                                                  (0x3UL << AON_ANAPAR_XTAL10_XTAL_SEL_LDOFASTSET_CYCLE_Pos)
+
+#define AON_ANAPAR_XTAL10_XTAL_EN_LPMODE_AUTO_GATED_Pos                                                                  2U
+#define AON_ANAPAR_XTAL10_XTAL_EN_LPMODE_AUTO_GATED_Msk                                                                  (0x1UL << AON_ANAPAR_XTAL10_XTAL_EN_LPMODE_AUTO_GATED_Pos)
+
+#define AON_ANAPAR_XTAL10_XTAL_LP_GATE_FW_CTRL_B_Pos                                                                     3U
+#define AON_ANAPAR_XTAL10_XTAL_LP_GATE_FW_CTRL_B_Msk                                                                     (0x1UL << AON_ANAPAR_XTAL10_XTAL_LP_GATE_FW_CTRL_B_Pos)
+
+#define AON_ANAPAR_XTAL10_XTAL_MODE_DEBUG_CAP_CTRL_Pos                                                                   4U
+#define AON_ANAPAR_XTAL10_XTAL_MODE_DEBUG_CAP_CTRL_Msk                                                                   (0x7UL << AON_ANAPAR_XTAL10_XTAL_MODE_DEBUG_CAP_CTRL_Pos)
+
+#define AON_ANAPAR_XTAL10_XTAL_MODE_DEBUG_GM_CTRL_Pos                                                                    7U
+#define AON_ANAPAR_XTAL10_XTAL_MODE_DEBUG_GM_CTRL_Msk                                                                    (0x7UL << AON_ANAPAR_XTAL10_XTAL_MODE_DEBUG_GM_CTRL_Pos)
+
+#define AON_ANAPAR_XTAL10_XTAL_EN_NMDAAC_Pos                                                                             10U
+#define AON_ANAPAR_XTAL10_XTAL_EN_NMDAAC_Msk                                                                             (0x1UL << AON_ANAPAR_XTAL10_XTAL_EN_NMDAAC_Pos)
+
+#define AON_ANAPAR_XTAL10_XTAL_NMPC_SEL_Pos                                                                              11U
+#define AON_ANAPAR_XTAL10_XTAL_NMPC_SEL_Msk                                                                              (0x1UL << AON_ANAPAR_XTAL10_XTAL_NMPC_SEL_Pos)
+
+#define AON_ANAPAR_XTAL10_XTAL_LPS_GM_CTRL_Pos                                                                           12U
+#define AON_ANAPAR_XTAL10_XTAL_LPS_GM_CTRL_Msk                                                                           (0x1UL << AON_ANAPAR_XTAL10_XTAL_LPS_GM_CTRL_Pos)
+
+#define AON_ANAPAR_XTAL10_XTAL_EN_SUPPLY_MODE_CTRLBYFASTAON_B_Pos                                                        13U
+#define AON_ANAPAR_XTAL10_XTAL_EN_SUPPLY_MODE_CTRLBYFASTAON_B_Msk                                                        (0x1UL << AON_ANAPAR_XTAL10_XTAL_EN_SUPPLY_MODE_CTRLBYFASTAON_B_Pos)
+
+#define AON_ANAPAR_XTAL10_XTAL_EN_SUPPLY_MODE_FASTAON_Pos                                                                14U
+#define AON_ANAPAR_XTAL10_XTAL_EN_SUPPLY_MODE_FASTAON_Msk                                                                (0x1UL << AON_ANAPAR_XTAL10_XTAL_EN_SUPPLY_MODE_FASTAON_Pos)
+
+#define AON_ANAPAR_XTAL10_XTAL_PDCK_BUSY_Pos                                                                             15U
+#define AON_ANAPAR_XTAL10_XTAL_PDCK_BUSY_Msk                                                                             (0x1UL << AON_ANAPAR_XTAL10_XTAL_PDCK_BUSY_Pos)
+
+#define AON_ANAPAR_XTAL10_XTAL_CTRL_Pos                                                                                  16U
+#define AON_ANAPAR_XTAL10_XTAL_CTRL_Msk                                                                                  (0xFFFFUL << AON_ANAPAR_XTAL10_XTAL_CTRL_Pos)
+
+/* 0x62C    0x4000_062c
+    15:0    R/W     XTAL_REG12X_DUMMY1                                          16'b0000000000000000
+    31:16   R/W     XTAL_REG13X_DUMMY1                                          16'b0000000000000000
+ */
+typedef union _AON_ANAPAR_XTAL12_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t XTAL_REG12X_DUMMY1: 16;
+        uint32_t XTAL_REG13X_DUMMY1: 16;
+    };
+} AON_ANAPAR_XTAL12_TYPE;
+
+/*0x4000_062c AON_ANAPAR_XTAL12*/
+#define AON_ANAPAR_XTAL12_XTAL_REG12X_DUMMY1_Pos                                                                         0U
+#define AON_ANAPAR_XTAL12_XTAL_REG12X_DUMMY1_Msk                                                                         (0xFFFFUL << AON_ANAPAR_XTAL12_XTAL_REG12X_DUMMY1_Pos)
+
+#define AON_ANAPAR_XTAL12_XTAL_REG13X_DUMMY1_Pos                                                                         16U
+#define AON_ANAPAR_XTAL12_XTAL_REG13X_DUMMY1_Msk                                                                         (0xFFFFUL << AON_ANAPAR_XTAL12_XTAL_REG13X_DUMMY1_Pos)
+
+/* 0x630    0x4000_0630
+    15:0    R/W     XTAL_REG14X_DUMMY1                                          16'b0000000000000000
+    31:16   R/W     XTAL_REG15X_DUMMY1                                          16'b0000000000000000
+ */
+typedef union _AON_ANAPAR_XTAL14_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t XTAL_REG14X_DUMMY1: 16;
+        uint32_t XTAL_REG15X_DUMMY1: 16;
+    };
+} AON_ANAPAR_XTAL14_TYPE;
+
+/*0x4000_0630 AON_ANAPAR_XTAL14*/
+#define AON_ANAPAR_XTAL14_XTAL_REG14X_DUMMY1_Pos                                                                         0U
+#define AON_ANAPAR_XTAL14_XTAL_REG14X_DUMMY1_Msk                                                                         (0xFFFFUL << AON_ANAPAR_XTAL14_XTAL_REG14X_DUMMY1_Pos)
+
+#define AON_ANAPAR_XTAL14_XTAL_REG15X_DUMMY1_Pos                                                                         16U
+#define AON_ANAPAR_XTAL14_XTAL_REG15X_DUMMY1_Msk                                                                         (0xFFFFUL << AON_ANAPAR_XTAL14_XTAL_REG15X_DUMMY1_Pos)
+
+/* 0x650    0x4000_0650
+    0       R/W     OSC80M_POW_OSC                                              1'b0
+    1       R/W     OSC80M_EN_OSC                                               1'b1
+    2       R/W     OSC80M_EN_LDO                                               1'b1
+    3       R/W     OSC80M_EN_LDO_VREF                                          1'b1
+    4       R/W     OSC80M_EN_FASTSET                                           1'b0
+    5       R/W     OSC80M_EN_VPULSE                                            1'b0
+    6       R/W     OSC80M_SW_LDO2PWRCUT                                        1'b0
+    7       R/W     OSC80M_EN_D2                                                1'b1
+    15:8    R/W     OSC80M_RCAL                                                 8'd13
+    19:16   R/W     OSC80M_LDO_SW                                               4'h2
+    22:20   R/W     OSC80M_OK_SEL                                               3'b101
+    23      R/W     OSC80M_LDO_VPULSE                                           1'b0
+    26:24   R/W     OSC80M_FASTSET_SEL                                          3'b101
+    27      R/W     EN_CKO_80M                                                  1'b0
+    30:28   R/W     OSC80M_ISEL                                                 3'b101
+    31      R/W     REG1X_OSC80M_DUMMY1                                         1'b0
+ */
+typedef union _AON_REG0X_OSC80M_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t OSC80M_POW_OSC: 1;
+        uint32_t OSC80M_EN_OSC: 1;
+        uint32_t OSC80M_EN_LDO: 1;
+        uint32_t OSC80M_EN_LDO_VREF: 1;
+        uint32_t OSC80M_EN_FASTSET: 1;
+        uint32_t OSC80M_EN_VPULSE: 1;
+        uint32_t OSC80M_SW_LDO2PWRCUT: 1;
+        uint32_t OSC80M_EN_D2: 1;
+        uint32_t OSC80M_RCAL: 8;
+        uint32_t OSC80M_LDO_SW: 4;
+        uint32_t OSC80M_OK_SEL: 3;
+        uint32_t OSC80M_LDO_VPULSE: 1;
+        uint32_t OSC80M_FASTSET_SEL: 3;
+        uint32_t EN_CKO_80M: 1;
+        uint32_t OSC80M_ISEL: 3;
+        uint32_t REG1X_OSC80M_DUMMY1: 1;
+    };
+} AON_REG0X_OSC80M_TYPE;
+
+/*0x4000_0650 AON_REG0X_OSC80M*/
+#define AON_REG0X_OSC80M_OSC80M_POW_OSC_Pos                                                                              0U
+#define AON_REG0X_OSC80M_OSC80M_POW_OSC_Msk                                                                              (0x1UL << AON_REG0X_OSC80M_OSC80M_POW_OSC_Pos)
+
+#define AON_REG0X_OSC80M_OSC80M_EN_OSC_Pos                                                                               1U
+#define AON_REG0X_OSC80M_OSC80M_EN_OSC_Msk                                                                               (0x1UL << AON_REG0X_OSC80M_OSC80M_EN_OSC_Pos)
+
+#define AON_REG0X_OSC80M_OSC80M_EN_LDO_Pos                                                                               2U
+#define AON_REG0X_OSC80M_OSC80M_EN_LDO_Msk                                                                               (0x1UL << AON_REG0X_OSC80M_OSC80M_EN_LDO_Pos)
+
+#define AON_REG0X_OSC80M_OSC80M_EN_LDO_VREF_Pos                                                                          3U
+#define AON_REG0X_OSC80M_OSC80M_EN_LDO_VREF_Msk                                                                          (0x1UL << AON_REG0X_OSC80M_OSC80M_EN_LDO_VREF_Pos)
+
+#define AON_REG0X_OSC80M_OSC80M_EN_FASTSET_Pos                                                                           4U
+#define AON_REG0X_OSC80M_OSC80M_EN_FASTSET_Msk                                                                           (0x1UL << AON_REG0X_OSC80M_OSC80M_EN_FASTSET_Pos)
+
+#define AON_REG0X_OSC80M_OSC80M_EN_VPULSE_Pos                                                                            5U
+#define AON_REG0X_OSC80M_OSC80M_EN_VPULSE_Msk                                                                            (0x1UL << AON_REG0X_OSC80M_OSC80M_EN_VPULSE_Pos)
+
+#define AON_REG0X_OSC80M_OSC80M_SW_LDO2PWRCUT_Pos                                                                        6U
+#define AON_REG0X_OSC80M_OSC80M_SW_LDO2PWRCUT_Msk                                                                        (0x1UL << AON_REG0X_OSC80M_OSC80M_SW_LDO2PWRCUT_Pos)
+
+#define AON_REG0X_OSC80M_OSC80M_EN_D2_Pos                                                                                7U
+#define AON_REG0X_OSC80M_OSC80M_EN_D2_Msk                                                                                (0x1UL << AON_REG0X_OSC80M_OSC80M_EN_D2_Pos)
+
+#define AON_REG0X_OSC80M_OSC80M_RCAL_Pos                                                                                 8U
+#define AON_REG0X_OSC80M_OSC80M_RCAL_Msk                                                                                 (0xFFUL << AON_REG0X_OSC80M_OSC80M_RCAL_Pos)
+
+#define AON_REG0X_OSC80M_OSC80M_LDO_SW_Pos                                                                               16U
+#define AON_REG0X_OSC80M_OSC80M_LDO_SW_Msk                                                                               (0xFUL << AON_REG0X_OSC80M_OSC80M_LDO_SW_Pos)
+
+#define AON_REG0X_OSC80M_OSC80M_OK_SEL_Pos                                                                               20U
+#define AON_REG0X_OSC80M_OSC80M_OK_SEL_Msk                                                                               (0x7UL << AON_REG0X_OSC80M_OSC80M_OK_SEL_Pos)
+
+#define AON_REG0X_OSC80M_OSC80M_LDO_VPULSE_Pos                                                                           23U
+#define AON_REG0X_OSC80M_OSC80M_LDO_VPULSE_Msk                                                                           (0x1UL << AON_REG0X_OSC80M_OSC80M_LDO_VPULSE_Pos)
+
+#define AON_REG0X_OSC80M_OSC80M_FASTSET_SEL_Pos                                                                          24U
+#define AON_REG0X_OSC80M_OSC80M_FASTSET_SEL_Msk                                                                          (0x7UL << AON_REG0X_OSC80M_OSC80M_FASTSET_SEL_Pos)
+
+#define AON_REG0X_OSC80M_EN_CKO_80M_Pos                                                                                  27U
+#define AON_REG0X_OSC80M_EN_CKO_80M_Msk                                                                                  (0x1UL << AON_REG0X_OSC80M_EN_CKO_80M_Pos)
+
+#define AON_REG0X_OSC80M_OSC80M_ISEL_Pos                                                                                 28U
+#define AON_REG0X_OSC80M_OSC80M_ISEL_Msk                                                                                 (0x7UL << AON_REG0X_OSC80M_OSC80M_ISEL_Pos)
+
+#define AON_REG0X_OSC80M_REG1X_OSC80M_DUMMY1_Pos                                                                         31U
+#define AON_REG0X_OSC80M_REG1X_OSC80M_DUMMY1_Msk                                                                         (0x1UL << AON_REG0X_OSC80M_REG1X_OSC80M_DUMMY1_Pos)
+
+/* 0x654    0x4000_0654
+    7:0     R/W     OSC80M_TIE_MID                                              8'h00
+    8       R/W     OSC80M_TIE_L                                                1'b0
+    9       R/W     OSC80M_TIE_H                                                1'b0
+    10      R/W     OSC80M_RING_DN                                              1'b0
+    11      R/W     OSC80M_RING_UP                                              1'b0
+    15:12   R/W     REG2X_OSC80M_DUMMY1                                         4'b1010
+    18:16   R/W     OSC80M_VSEL                                                 3'b011
+    19      R/W     REG3X_OSC80M_DUMMY1                                         1'b0
+    22:20   R/W     OSC80M_STARTUP_SEL                                          3'b011
+    23      R/W     REG3X_OSC80M_DUMMY2                                         1'b0
+    31:24   R/W     REG3X_OSC80M_DUMMY3                                         8'b10101010
+ */
+typedef union _AON_REG2X_OSC80M_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t OSC80M_TIE_MID: 8;
+        uint32_t OSC80M_TIE_L: 1;
+        uint32_t OSC80M_TIE_H: 1;
+        uint32_t OSC80M_RING_DN: 1;
+        uint32_t OSC80M_RING_UP: 1;
+        uint32_t REG2X_OSC80M_DUMMY1: 4;
+        uint32_t OSC80M_VSEL: 3;
+        uint32_t REG3X_OSC80M_DUMMY1: 1;
+        uint32_t OSC80M_STARTUP_SEL: 3;
+        uint32_t REG3X_OSC80M_DUMMY2: 1;
+        uint32_t REG3X_OSC80M_DUMMY3: 8;
+    };
+} AON_REG2X_OSC80M_TYPE;
+
+/*0x4000_0654 AON_REG2X_OSC80M*/
+#define AON_REG2X_OSC80M_OSC80M_TIE_MID_Pos                                                                              0U
+#define AON_REG2X_OSC80M_OSC80M_TIE_MID_Msk                                                                              (0xFFUL << AON_REG2X_OSC80M_OSC80M_TIE_MID_Pos)
+
+#define AON_REG2X_OSC80M_OSC80M_TIE_L_Pos                                                                                8U
+#define AON_REG2X_OSC80M_OSC80M_TIE_L_Msk                                                                                (0x1UL << AON_REG2X_OSC80M_OSC80M_TIE_L_Pos)
+
+#define AON_REG2X_OSC80M_OSC80M_TIE_H_Pos                                                                                9U
+#define AON_REG2X_OSC80M_OSC80M_TIE_H_Msk                                                                                (0x1UL << AON_REG2X_OSC80M_OSC80M_TIE_H_Pos)
+
+#define AON_REG2X_OSC80M_OSC80M_RING_DN_Pos                                                                              10U
+#define AON_REG2X_OSC80M_OSC80M_RING_DN_Msk                                                                              (0x1UL << AON_REG2X_OSC80M_OSC80M_RING_DN_Pos)
+
+#define AON_REG2X_OSC80M_OSC80M_RING_UP_Pos                                                                              11U
+#define AON_REG2X_OSC80M_OSC80M_RING_UP_Msk                                                                              (0x1UL << AON_REG2X_OSC80M_OSC80M_RING_UP_Pos)
+
+#define AON_REG2X_OSC80M_REG2X_OSC80M_DUMMY1_Pos                                                                         12U
+#define AON_REG2X_OSC80M_REG2X_OSC80M_DUMMY1_Msk                                                                         (0xFUL << AON_REG2X_OSC80M_REG2X_OSC80M_DUMMY1_Pos)
+
+#define AON_REG2X_OSC80M_OSC80M_VSEL_Pos                                                                                 16U
+#define AON_REG2X_OSC80M_OSC80M_VSEL_Msk                                                                                 (0x7UL << AON_REG2X_OSC80M_OSC80M_VSEL_Pos)
+
+#define AON_REG2X_OSC80M_REG3X_OSC80M_DUMMY1_Pos                                                                         19U
+#define AON_REG2X_OSC80M_REG3X_OSC80M_DUMMY1_Msk                                                                         (0x1UL << AON_REG2X_OSC80M_REG3X_OSC80M_DUMMY1_Pos)
+
+#define AON_REG2X_OSC80M_OSC80M_STARTUP_SEL_Pos                                                                          20U
+#define AON_REG2X_OSC80M_OSC80M_STARTUP_SEL_Msk                                                                          (0x7UL << AON_REG2X_OSC80M_OSC80M_STARTUP_SEL_Pos)
+
+#define AON_REG2X_OSC80M_REG3X_OSC80M_DUMMY2_Pos                                                                         23U
+#define AON_REG2X_OSC80M_REG3X_OSC80M_DUMMY2_Msk                                                                         (0x1UL << AON_REG2X_OSC80M_REG3X_OSC80M_DUMMY2_Pos)
+
+#define AON_REG2X_OSC80M_REG3X_OSC80M_DUMMY3_Pos                                                                         24U
+#define AON_REG2X_OSC80M_REG3X_OSC80M_DUMMY3_Msk                                                                         (0xFFUL << AON_REG2X_OSC80M_REG3X_OSC80M_DUMMY3_Pos)
+
+/* 0x658    0x4000_0658
+    0       R       OK_80M                                                      1'b0
+    15:1    R       RSVD_1                                                      15'b0
+    31:16   R       RSVD                                                        16'h0
+ */
+typedef union _AON_C_KOUT0X_OSC80M_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t OK_80M: 1;
+        uint32_t RSVD_1: 15;
+        uint32_t RSVD: 16;
+    };
+} AON_C_KOUT0X_OSC80M_TYPE;
+
+/*0x4000_0658 AON_C_KOUT0X_OSC80M*/
+#define AON_C_KOUT0X_OSC80M_OK_80M_Pos                                                                                   0U
+#define AON_C_KOUT0X_OSC80M_OK_80M_Msk                                                                                   (0x1UL << AON_C_KOUT0X_OSC80M_OK_80M_Pos)
+
+#define AON_C_KOUT0X_OSC80M_RSVD_1_Pos                                                                                   1U
+#define AON_C_KOUT0X_OSC80M_RSVD_1_Msk                                                                                   (0x7FFFUL << AON_C_KOUT0X_OSC80M_RSVD_1_Pos)
+
+#define AON_C_KOUT0X_OSC80M_RSVD_Pos                                                                                     16U
+#define AON_C_KOUT0X_OSC80M_RSVD_Msk                                                                                     (0xFFFFUL << AON_C_KOUT0X_OSC80M_RSVD_Pos)
+
+/* 0x674    0x4000_0674
+    1:0     R/W     TUNE_MAXZC_1_0                                              2'b00
+    2       R/W     FWDT_RSTB                                                   1'b0
+    3       R/W     EN_DRVWELL_OPT                                              1'b0
+    12:4    R/W     REG0X_DMY1                                                  9'b000011111
+    13      R/W     EN_MAX_ZC_K                                                 1'b0
+    14      R/W     IO_RSTB33_EN                                                1'b0
+    15      R/W     IO_SHDN33_EN                                                1'b0
+    18:16   R/W     REG1X_DMY1                                                  3'b000
+    19      R/W     L2T                                                         1'b0
+    24:20   R/W     U2_OUT_T_5_1                                                5'b11111
+    25      R/W     L1T                                                         1'b0
+    26      R/W     U1T                                                         1'b1
+    27      R/W     TM_DRV                                                      1'b0
+    30:28   R/W     TM_MOD_FLAGSEL_2_0                                          3'b000
+    31      R/W     TM_ZC_SET                                                   1'b0
+ */
+typedef union _AON_REG_SIMO_REG0X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t TUNE_MAXZC_1_0: 2;
+        uint32_t FWDT_RSTB: 1;
+        uint32_t EN_DRVWELL_OPT: 1;
+        uint32_t REG0X_DMY1: 9;
+        uint32_t EN_MAX_ZC_K: 1;
+        uint32_t IO_RSTB33_EN: 1;
+        uint32_t IO_SHDN33_EN: 1;
+        uint32_t REG1X_DMY1: 3;
+        uint32_t L2T: 1;
+        uint32_t U2_OUT_T_5_1: 5;
+        uint32_t L1T: 1;
+        uint32_t U1T: 1;
+        uint32_t TM_DRV: 1;
+        uint32_t TM_MOD_FLAGSEL_2_0: 3;
+        uint32_t TM_ZC_SET: 1;
+    };
+} AON_REG_SIMO_REG0X_TYPE;
+
+/*0x4000_0674 AON_REG_SIMO_REG0X*/
+#define AON_REG_SIMO_REG0X_TUNE_MAXZC_1_0_Pos                                                                            0U
+#define AON_REG_SIMO_REG0X_TUNE_MAXZC_1_0_Msk                                                                            (0x3UL << AON_REG_SIMO_REG0X_TUNE_MAXZC_1_0_Pos)
+
+#define AON_REG_SIMO_REG0X_FWDT_RSTB_Pos                                                                                 2U
+#define AON_REG_SIMO_REG0X_FWDT_RSTB_Msk                                                                                 (0x1UL << AON_REG_SIMO_REG0X_FWDT_RSTB_Pos)
+
+#define AON_REG_SIMO_REG0X_EN_DRVWELL_OPT_Pos                                                                            3U
+#define AON_REG_SIMO_REG0X_EN_DRVWELL_OPT_Msk                                                                            (0x1UL << AON_REG_SIMO_REG0X_EN_DRVWELL_OPT_Pos)
+
+#define AON_REG_SIMO_REG0X_REG0X_DMY1_Pos                                                                                4U
+#define AON_REG_SIMO_REG0X_REG0X_DMY1_Msk                                                                                (0x1FFUL << AON_REG_SIMO_REG0X_REG0X_DMY1_Pos)
+
+#define AON_REG_SIMO_REG0X_EN_MAX_ZC_K_Pos                                                                               13U
+#define AON_REG_SIMO_REG0X_EN_MAX_ZC_K_Msk                                                                               (0x1UL << AON_REG_SIMO_REG0X_EN_MAX_ZC_K_Pos)
+
+#define AON_REG_SIMO_REG0X_IO_RSTB33_EN_Pos                                                                              14U
+#define AON_REG_SIMO_REG0X_IO_RSTB33_EN_Msk                                                                              (0x1UL << AON_REG_SIMO_REG0X_IO_RSTB33_EN_Pos)
+
+#define AON_REG_SIMO_REG0X_IO_SHDN33_EN_Pos                                                                              15U
+#define AON_REG_SIMO_REG0X_IO_SHDN33_EN_Msk                                                                              (0x1UL << AON_REG_SIMO_REG0X_IO_SHDN33_EN_Pos)
+
+#define AON_REG_SIMO_REG0X_REG1X_DMY1_Pos                                                                                16U
+#define AON_REG_SIMO_REG0X_REG1X_DMY1_Msk                                                                                (0x7UL << AON_REG_SIMO_REG0X_REG1X_DMY1_Pos)
+
+#define AON_REG_SIMO_REG0X_L2T_Pos                                                                                       19U
+#define AON_REG_SIMO_REG0X_L2T_Msk                                                                                       (0x1UL << AON_REG_SIMO_REG0X_L2T_Pos)
+
+#define AON_REG_SIMO_REG0X_U2_OUT_T_5_1_Pos                                                                              20U
+#define AON_REG_SIMO_REG0X_U2_OUT_T_5_1_Msk                                                                              (0x1FUL << AON_REG_SIMO_REG0X_U2_OUT_T_5_1_Pos)
+
+#define AON_REG_SIMO_REG0X_L1T_Pos                                                                                       25U
+#define AON_REG_SIMO_REG0X_L1T_Msk                                                                                       (0x1UL << AON_REG_SIMO_REG0X_L1T_Pos)
+
+#define AON_REG_SIMO_REG0X_U1T_Pos                                                                                       26U
+#define AON_REG_SIMO_REG0X_U1T_Msk                                                                                       (0x1UL << AON_REG_SIMO_REG0X_U1T_Pos)
+
+#define AON_REG_SIMO_REG0X_TM_DRV_Pos                                                                                    27U
+#define AON_REG_SIMO_REG0X_TM_DRV_Msk                                                                                    (0x1UL << AON_REG_SIMO_REG0X_TM_DRV_Pos)
+
+#define AON_REG_SIMO_REG0X_TM_MOD_FLAGSEL_2_0_Pos                                                                        28U
+#define AON_REG_SIMO_REG0X_TM_MOD_FLAGSEL_2_0_Msk                                                                        (0x7UL << AON_REG_SIMO_REG0X_TM_MOD_FLAGSEL_2_0_Pos)
+
+#define AON_REG_SIMO_REG0X_TM_ZC_SET_Pos                                                                                 31U
+#define AON_REG_SIMO_REG0X_TM_ZC_SET_Msk                                                                                 (0x1UL << AON_REG_SIMO_REG0X_TM_ZC_SET_Pos)
+
+/* 0x678    0x4000_0678
+    0       R/W     ENPCCM_TRI                                                  1'b0
+    1       R/W     EN_DISCHG_MCM_FLASH                                         1'b0
+    2       R/W     REG_ENBPOSTF                                                1'b0
+    3       R/W     EN_MCM_FLASH_PC2                                            1'b0
+    4       R/W     EN_MCM_FLASH_PC1                                            1'b0
+    5       R/W     SEL_EFLASH_HV25                                             1'b1
+    6       R/W     SEL_EFLASH_HV18                                             1'b0
+    10:7    R/W     REG2X_DMY2                                                  4'b0000
+    11      R/W     EN_DMYLOAD_HV25                                             1'b0
+    12      R/W     EN_DMYLOAD_HV18                                             1'b1
+    13      R/W     EN_DMYLOAD_VDDPA                                            1'b0
+    14      R/W     EN_DMYLOAD_VDDANA                                           1'b0
+    15      R/W     EN_DMYLOAD_VDDCORE                                          1'b0
+    21:16   R/W     TUNE_HV18                                                   6'b100000
+    26:22   R/W     VOUTFBSEL                                                   5'b00000
+    27      R/W     EN_CMP_LQ_HV25                                              1'b1
+    28      R/W     SEL_VO3CMPHQ2_B                                             1'b1
+    29      R/W     EN_VO3HQ2BETA                                               1'b1
+    30      R/W     EN_VO3CMPHQ2                                                1'b0
+    31      R/W     EN_VIN_BLOCK                                                1'b0
+ */
+typedef union _AON_REG_SIMO_REG1X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t ENPCCM_TRI: 1;
+        uint32_t EN_DISCHG_MCM_FLASH: 1;
+        uint32_t REG_ENBPOSTF: 1;
+        uint32_t EN_MCM_FLASH_PC2: 1;
+        uint32_t EN_MCM_FLASH_PC1: 1;
+        uint32_t SEL_EFLASH_HV25: 1;
+        uint32_t SEL_EFLASH_HV18: 1;
+        uint32_t REG2X_DMY2: 4;
+        uint32_t EN_DMYLOAD_HV25: 1;
+        uint32_t EN_DMYLOAD_HV18: 1;
+        uint32_t EN_DMYLOAD_VDDPA: 1;
+        uint32_t EN_DMYLOAD_VDDANA: 1;
+        uint32_t EN_DMYLOAD_VDDCORE: 1;
+        uint32_t TUNE_HV18: 6;
+        uint32_t VOUTFBSEL: 5;
+        uint32_t EN_CMP_LQ_HV25: 1;
+        uint32_t SEL_VO3CMPHQ2_B: 1;
+        uint32_t EN_VO3HQ2BETA: 1;
+        uint32_t EN_VO3CMPHQ2: 1;
+        uint32_t EN_VIN_BLOCK: 1;
+    };
+} AON_REG_SIMO_REG1X_TYPE;
+
+/*0x4000_0678 AON_REG_SIMO_REG1X*/
+#define AON_REG_SIMO_REG1X_ENPCCM_TRI_Pos                                                                                0U
+#define AON_REG_SIMO_REG1X_ENPCCM_TRI_Msk                                                                                (0x1UL << AON_REG_SIMO_REG1X_ENPCCM_TRI_Pos)
+
+#define AON_REG_SIMO_REG1X_EN_DISCHG_MCM_FLASH_Pos                                                                       1U
+#define AON_REG_SIMO_REG1X_EN_DISCHG_MCM_FLASH_Msk                                                                       (0x1UL << AON_REG_SIMO_REG1X_EN_DISCHG_MCM_FLASH_Pos)
+
+#define AON_REG_SIMO_REG1X_REG_ENBPOSTF_Pos                                                                              2U
+#define AON_REG_SIMO_REG1X_REG_ENBPOSTF_Msk                                                                              (0x1UL << AON_REG_SIMO_REG1X_REG_ENBPOSTF_Pos)
+
+#define AON_REG_SIMO_REG1X_EN_MCM_FLASH_PC2_Pos                                                                          3U
+#define AON_REG_SIMO_REG1X_EN_MCM_FLASH_PC2_Msk                                                                          (0x1UL << AON_REG_SIMO_REG1X_EN_MCM_FLASH_PC2_Pos)
+
+#define AON_REG_SIMO_REG1X_EN_MCM_FLASH_PC1_Pos                                                                          4U
+#define AON_REG_SIMO_REG1X_EN_MCM_FLASH_PC1_Msk                                                                          (0x1UL << AON_REG_SIMO_REG1X_EN_MCM_FLASH_PC1_Pos)
+
+#define AON_REG_SIMO_REG1X_SEL_EFLASH_HV25_Pos                                                                           5U
+#define AON_REG_SIMO_REG1X_SEL_EFLASH_HV25_Msk                                                                           (0x1UL << AON_REG_SIMO_REG1X_SEL_EFLASH_HV25_Pos)
+
+#define AON_REG_SIMO_REG1X_SEL_EFLASH_HV18_Pos                                                                           6U
+#define AON_REG_SIMO_REG1X_SEL_EFLASH_HV18_Msk                                                                           (0x1UL << AON_REG_SIMO_REG1X_SEL_EFLASH_HV18_Pos)
+
+#define AON_REG_SIMO_REG1X_REG2X_DMY2_Pos                                                                                7U
+#define AON_REG_SIMO_REG1X_REG2X_DMY2_Msk                                                                                (0xFUL << AON_REG_SIMO_REG1X_REG2X_DMY2_Pos)
+
+#define AON_REG_SIMO_REG1X_EN_DMYLOAD_HV25_Pos                                                                           11U
+#define AON_REG_SIMO_REG1X_EN_DMYLOAD_HV25_Msk                                                                           (0x1UL << AON_REG_SIMO_REG1X_EN_DMYLOAD_HV25_Pos)
+
+#define AON_REG_SIMO_REG1X_EN_DMYLOAD_HV18_Pos                                                                           12U
+#define AON_REG_SIMO_REG1X_EN_DMYLOAD_HV18_Msk                                                                           (0x1UL << AON_REG_SIMO_REG1X_EN_DMYLOAD_HV18_Pos)
+
+#define AON_REG_SIMO_REG1X_EN_DMYLOAD_VDDPA_Pos                                                                          13U
+#define AON_REG_SIMO_REG1X_EN_DMYLOAD_VDDPA_Msk                                                                          (0x1UL << AON_REG_SIMO_REG1X_EN_DMYLOAD_VDDPA_Pos)
+
+#define AON_REG_SIMO_REG1X_EN_DMYLOAD_VDDANA_Pos                                                                         14U
+#define AON_REG_SIMO_REG1X_EN_DMYLOAD_VDDANA_Msk                                                                         (0x1UL << AON_REG_SIMO_REG1X_EN_DMYLOAD_VDDANA_Pos)
+
+#define AON_REG_SIMO_REG1X_EN_DMYLOAD_VDDCORE_Pos                                                                        15U
+#define AON_REG_SIMO_REG1X_EN_DMYLOAD_VDDCORE_Msk                                                                        (0x1UL << AON_REG_SIMO_REG1X_EN_DMYLOAD_VDDCORE_Pos)
+
+#define AON_REG_SIMO_REG1X_TUNE_HV18_Pos                                                                                 16U
+#define AON_REG_SIMO_REG1X_TUNE_HV18_Msk                                                                                 (0x3FUL << AON_REG_SIMO_REG1X_TUNE_HV18_Pos)
+
+#define AON_REG_SIMO_REG1X_VOUTFBSEL_Pos                                                                                 22U
+#define AON_REG_SIMO_REG1X_VOUTFBSEL_Msk                                                                                 (0x1FUL << AON_REG_SIMO_REG1X_VOUTFBSEL_Pos)
+
+#define AON_REG_SIMO_REG1X_EN_CMP_LQ_HV25_Pos                                                                            27U
+#define AON_REG_SIMO_REG1X_EN_CMP_LQ_HV25_Msk                                                                            (0x1UL << AON_REG_SIMO_REG1X_EN_CMP_LQ_HV25_Pos)
+
+#define AON_REG_SIMO_REG1X_SEL_VO3CMPHQ2_B_Pos                                                                           28U
+#define AON_REG_SIMO_REG1X_SEL_VO3CMPHQ2_B_Msk                                                                           (0x1UL << AON_REG_SIMO_REG1X_SEL_VO3CMPHQ2_B_Pos)
+
+#define AON_REG_SIMO_REG1X_EN_VO3HQ2BETA_Pos                                                                             29U
+#define AON_REG_SIMO_REG1X_EN_VO3HQ2BETA_Msk                                                                             (0x1UL << AON_REG_SIMO_REG1X_EN_VO3HQ2BETA_Pos)
+
+#define AON_REG_SIMO_REG1X_EN_VO3CMPHQ2_Pos                                                                              30U
+#define AON_REG_SIMO_REG1X_EN_VO3CMPHQ2_Msk                                                                              (0x1UL << AON_REG_SIMO_REG1X_EN_VO3CMPHQ2_Pos)
+
+#define AON_REG_SIMO_REG1X_EN_VIN_BLOCK_Pos                                                                              31U
+#define AON_REG_SIMO_REG1X_EN_VIN_BLOCK_Msk                                                                              (0x1UL << AON_REG_SIMO_REG1X_EN_VIN_BLOCK_Pos)
+
+/* 0x684    0x4000_0684
+    7:0     R/W     TUNE_VDDANA                                                 8'b01111010
+    15:8    R/W     TUNE_VDDPA                                                  8'b00100010
+    16      R/W     EN_CMP_LQ_HV18                                              1'b0
+    17      R/W     POW_VDIV_LQ_HV18                                            1'b0
+    23:18   R/W     TUNE_LPM_HV18                                               6'b100000
+    31:24   R/W     TUNE_VDDCORE                                                8'b01100010
+ */
+typedef union _AON_REG_SIMO_REG2X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t TUNE_VDDANA: 8;
+        uint32_t TUNE_VDDPA: 8;
+        uint32_t EN_CMP_LQ_HV18: 1;
+        uint32_t POW_VDIV_LQ_HV18: 1;
+        uint32_t TUNE_LPM_HV18: 6;
+        uint32_t TUNE_VDDCORE: 8;
+    };
+} AON_REG_SIMO_REG2X_TYPE;
+
+/*0x4000_0684 AON_REG_SIMO_REG2X*/
+#define AON_REG_SIMO_REG2X_TUNE_VDDANA_Pos                                                                               0U
+#define AON_REG_SIMO_REG2X_TUNE_VDDANA_Msk                                                                               (0xFFUL << AON_REG_SIMO_REG2X_TUNE_VDDANA_Pos)
+
+#define AON_REG_SIMO_REG2X_TUNE_VDDPA_Pos                                                                                8U
+#define AON_REG_SIMO_REG2X_TUNE_VDDPA_Msk                                                                                (0xFFUL << AON_REG_SIMO_REG2X_TUNE_VDDPA_Pos)
+
+#define AON_REG_SIMO_REG2X_EN_CMP_LQ_HV18_Pos                                                                            16U
+#define AON_REG_SIMO_REG2X_EN_CMP_LQ_HV18_Msk                                                                            (0x1UL << AON_REG_SIMO_REG2X_EN_CMP_LQ_HV18_Pos)
+
+#define AON_REG_SIMO_REG2X_POW_VDIV_LQ_HV18_Pos                                                                          17U
+#define AON_REG_SIMO_REG2X_POW_VDIV_LQ_HV18_Msk                                                                          (0x1UL << AON_REG_SIMO_REG2X_POW_VDIV_LQ_HV18_Pos)
+
+#define AON_REG_SIMO_REG2X_TUNE_LPM_HV18_Pos                                                                             18U
+#define AON_REG_SIMO_REG2X_TUNE_LPM_HV18_Msk                                                                             (0x3FUL << AON_REG_SIMO_REG2X_TUNE_LPM_HV18_Pos)
+
+#define AON_REG_SIMO_REG2X_TUNE_VDDCORE_Pos                                                                              24U
+#define AON_REG_SIMO_REG2X_TUNE_VDDCORE_Msk                                                                              (0xFFUL << AON_REG_SIMO_REG2X_TUNE_VDDCORE_Pos)
+
+/* 0x688    0x4000_0688
+    0       R/W     EN_CMP_LQ_VDDANA                                            1'b0
+    1       R/W     EN_CMP_LQ_VDDCORE                                           1'b0
+    2       R/W     POW_VDIV_LQ_VDDANA                                          1'b0
+    3       R/W     POW_VDIV_LQ_VDDCORE                                         1'b0
+    4       R/W     EN_CMP_HQ_HV25                                              1'b1
+    5       R/W     EN_CMP_HQ_HV18                                              1'b0
+    6       R/W     EN_CMP_HQ_VDDPA                                             1'b0
+    7       R/W     EN_CMP_HQ_VDDANA                                            1'b1
+    8       R/W     EN_CMP_HQ_VDDCORE                                           1'b0
+    9       R/W     POW_VDIV_HQ_HV25                                            1'b1
+    10      R/W     POW_VDIV_HQ_HV18                                            1'b0
+    11      R/W     POW_VDIV_HQ_VDDPA                                           1'b0
+    12      R/W     POW_VDIV_HQ_VDDANA                                          1'b1
+    13      R/W     POW_VDIV_HQ_VDDCORE                                         1'b0
+    14      R/W     TUNE_LPM_HV25_RANGE                                         1'b0
+    15      R/W     TUNE_HV25_RANGE                                             1'b0
+    16      R/W     ENCCM_OUT_HV25                                              1'b1
+    17      R/W     ENCCM_OUT_HV18                                              1'b1
+    18      R/W     ENCCM_OUT_VDDPA                                             1'b0
+    19      R/W     ENCCM_OUT_VDDANA                                            1'b1
+    20      R/W     ENCCM_OUT_VDDCORE                                           1'b1
+    21      R/W     EN_TON_PLUS                                                 1'b0
+    31:22   R/W     REG7X_DMY                                                   10'b0000000000
+ */
+typedef union _AON_REG_SIMO_REG3X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t EN_CMP_LQ_VDDANA: 1;
+        uint32_t EN_CMP_LQ_VDDCORE: 1;
+        uint32_t POW_VDIV_LQ_VDDANA: 1;
+        uint32_t POW_VDIV_LQ_VDDCORE: 1;
+        uint32_t EN_CMP_HQ_HV25: 1;
+        uint32_t EN_CMP_HQ_HV18: 1;
+        uint32_t EN_CMP_HQ_VDDPA: 1;
+        uint32_t EN_CMP_HQ_VDDANA: 1;
+        uint32_t EN_CMP_HQ_VDDCORE: 1;
+        uint32_t POW_VDIV_HQ_HV25: 1;
+        uint32_t POW_VDIV_HQ_HV18: 1;
+        uint32_t POW_VDIV_HQ_VDDPA: 1;
+        uint32_t POW_VDIV_HQ_VDDANA: 1;
+        uint32_t POW_VDIV_HQ_VDDCORE: 1;
+        uint32_t TUNE_LPM_HV25_RANGE: 1;
+        uint32_t TUNE_HV25_RANGE: 1;
+        uint32_t ENCCM_OUT_HV25: 1;
+        uint32_t ENCCM_OUT_HV18: 1;
+        uint32_t ENCCM_OUT_VDDPA: 1;
+        uint32_t ENCCM_OUT_VDDANA: 1;
+        uint32_t ENCCM_OUT_VDDCORE: 1;
+        uint32_t EN_TON_PLUS: 1;
+        uint32_t REG7X_DMY: 10;
+    };
+} AON_REG_SIMO_REG3X_TYPE;
+
+/*0x4000_0688 AON_REG_SIMO_REG3X*/
+#define AON_REG_SIMO_REG3X_EN_CMP_LQ_VDDANA_Pos                                                                          0U
+#define AON_REG_SIMO_REG3X_EN_CMP_LQ_VDDANA_Msk                                                                          (0x1UL << AON_REG_SIMO_REG3X_EN_CMP_LQ_VDDANA_Pos)
+
+#define AON_REG_SIMO_REG3X_EN_CMP_LQ_VDDCORE_Pos                                                                         1U
+#define AON_REG_SIMO_REG3X_EN_CMP_LQ_VDDCORE_Msk                                                                         (0x1UL << AON_REG_SIMO_REG3X_EN_CMP_LQ_VDDCORE_Pos)
+
+#define AON_REG_SIMO_REG3X_POW_VDIV_LQ_VDDANA_Pos                                                                        2U
+#define AON_REG_SIMO_REG3X_POW_VDIV_LQ_VDDANA_Msk                                                                        (0x1UL << AON_REG_SIMO_REG3X_POW_VDIV_LQ_VDDANA_Pos)
+
+#define AON_REG_SIMO_REG3X_POW_VDIV_LQ_VDDCORE_Pos                                                                       3U
+#define AON_REG_SIMO_REG3X_POW_VDIV_LQ_VDDCORE_Msk                                                                       (0x1UL << AON_REG_SIMO_REG3X_POW_VDIV_LQ_VDDCORE_Pos)
+
+#define AON_REG_SIMO_REG3X_EN_CMP_HQ_HV25_Pos                                                                            4U
+#define AON_REG_SIMO_REG3X_EN_CMP_HQ_HV25_Msk                                                                            (0x1UL << AON_REG_SIMO_REG3X_EN_CMP_HQ_HV25_Pos)
+
+#define AON_REG_SIMO_REG3X_EN_CMP_HQ_HV18_Pos                                                                            5U
+#define AON_REG_SIMO_REG3X_EN_CMP_HQ_HV18_Msk                                                                            (0x1UL << AON_REG_SIMO_REG3X_EN_CMP_HQ_HV18_Pos)
+
+#define AON_REG_SIMO_REG3X_EN_CMP_HQ_VDDPA_Pos                                                                           6U
+#define AON_REG_SIMO_REG3X_EN_CMP_HQ_VDDPA_Msk                                                                           (0x1UL << AON_REG_SIMO_REG3X_EN_CMP_HQ_VDDPA_Pos)
+
+#define AON_REG_SIMO_REG3X_EN_CMP_HQ_VDDANA_Pos                                                                          7U
+#define AON_REG_SIMO_REG3X_EN_CMP_HQ_VDDANA_Msk                                                                          (0x1UL << AON_REG_SIMO_REG3X_EN_CMP_HQ_VDDANA_Pos)
+
+#define AON_REG_SIMO_REG3X_EN_CMP_HQ_VDDCORE_Pos                                                                         8U
+#define AON_REG_SIMO_REG3X_EN_CMP_HQ_VDDCORE_Msk                                                                         (0x1UL << AON_REG_SIMO_REG3X_EN_CMP_HQ_VDDCORE_Pos)
+
+#define AON_REG_SIMO_REG3X_POW_VDIV_HQ_HV25_Pos                                                                          9U
+#define AON_REG_SIMO_REG3X_POW_VDIV_HQ_HV25_Msk                                                                          (0x1UL << AON_REG_SIMO_REG3X_POW_VDIV_HQ_HV25_Pos)
+
+#define AON_REG_SIMO_REG3X_POW_VDIV_HQ_HV18_Pos                                                                          10U
+#define AON_REG_SIMO_REG3X_POW_VDIV_HQ_HV18_Msk                                                                          (0x1UL << AON_REG_SIMO_REG3X_POW_VDIV_HQ_HV18_Pos)
+
+#define AON_REG_SIMO_REG3X_POW_VDIV_HQ_VDDPA_Pos                                                                         11U
+#define AON_REG_SIMO_REG3X_POW_VDIV_HQ_VDDPA_Msk                                                                         (0x1UL << AON_REG_SIMO_REG3X_POW_VDIV_HQ_VDDPA_Pos)
+
+#define AON_REG_SIMO_REG3X_POW_VDIV_HQ_VDDANA_Pos                                                                        12U
+#define AON_REG_SIMO_REG3X_POW_VDIV_HQ_VDDANA_Msk                                                                        (0x1UL << AON_REG_SIMO_REG3X_POW_VDIV_HQ_VDDANA_Pos)
+
+#define AON_REG_SIMO_REG3X_POW_VDIV_HQ_VDDCORE_Pos                                                                       13U
+#define AON_REG_SIMO_REG3X_POW_VDIV_HQ_VDDCORE_Msk                                                                       (0x1UL << AON_REG_SIMO_REG3X_POW_VDIV_HQ_VDDCORE_Pos)
+
+#define AON_REG_SIMO_REG3X_TUNE_LPM_HV25_RANGE_Pos                                                                       14U
+#define AON_REG_SIMO_REG3X_TUNE_LPM_HV25_RANGE_Msk                                                                       (0x1UL << AON_REG_SIMO_REG3X_TUNE_LPM_HV25_RANGE_Pos)
+
+#define AON_REG_SIMO_REG3X_TUNE_HV25_RANGE_Pos                                                                           15U
+#define AON_REG_SIMO_REG3X_TUNE_HV25_RANGE_Msk                                                                           (0x1UL << AON_REG_SIMO_REG3X_TUNE_HV25_RANGE_Pos)
+
+#define AON_REG_SIMO_REG3X_ENCCM_OUT_HV25_Pos                                                                            16U
+#define AON_REG_SIMO_REG3X_ENCCM_OUT_HV25_Msk                                                                            (0x1UL << AON_REG_SIMO_REG3X_ENCCM_OUT_HV25_Pos)
+
+#define AON_REG_SIMO_REG3X_ENCCM_OUT_HV18_Pos                                                                            17U
+#define AON_REG_SIMO_REG3X_ENCCM_OUT_HV18_Msk                                                                            (0x1UL << AON_REG_SIMO_REG3X_ENCCM_OUT_HV18_Pos)
+
+#define AON_REG_SIMO_REG3X_ENCCM_OUT_VDDPA_Pos                                                                           18U
+#define AON_REG_SIMO_REG3X_ENCCM_OUT_VDDPA_Msk                                                                           (0x1UL << AON_REG_SIMO_REG3X_ENCCM_OUT_VDDPA_Pos)
+
+#define AON_REG_SIMO_REG3X_ENCCM_OUT_VDDANA_Pos                                                                          19U
+#define AON_REG_SIMO_REG3X_ENCCM_OUT_VDDANA_Msk                                                                          (0x1UL << AON_REG_SIMO_REG3X_ENCCM_OUT_VDDANA_Pos)
+
+#define AON_REG_SIMO_REG3X_ENCCM_OUT_VDDCORE_Pos                                                                         20U
+#define AON_REG_SIMO_REG3X_ENCCM_OUT_VDDCORE_Msk                                                                         (0x1UL << AON_REG_SIMO_REG3X_ENCCM_OUT_VDDCORE_Pos)
+
+#define AON_REG_SIMO_REG3X_EN_TON_PLUS_Pos                                                                               21U
+#define AON_REG_SIMO_REG3X_EN_TON_PLUS_Msk                                                                               (0x1UL << AON_REG_SIMO_REG3X_EN_TON_PLUS_Pos)
+
+#define AON_REG_SIMO_REG3X_REG7X_DMY_Pos                                                                                 22U
+#define AON_REG_SIMO_REG3X_REG7X_DMY_Msk                                                                                 (0x3FFUL << AON_REG_SIMO_REG3X_REG7X_DMY_Pos)
+
+/* 0x68C    0x4000_068c
+    1:0     R/W     ENCCMDLYSET                                                 2'b00
+    3:2     R/W     LPMCMPDLY_SET                                               2'b01
+    5:4     R/W     IBRDY2SET                                                   2'b01
+    7:6     R/W     IBRDY1SET                                                   2'b01
+    8       R/W     BYP_OPOR_LD                                                 1'b1
+    9       R/W     EN_SYNC                                                     1'b0
+    10      R/W     REG_FORCE_ENPOSTD                                           1'b0
+    11      R/W     REG_FORCE_ENPOST                                            1'b0
+    12      R/W     REG_ENNCP                                                   1'b0
+    13      R/W     REG_ENPCCM                                                  1'b0
+    14      R/W     REG_ENHQ_REFCMP                                             1'b1
+    15      R/W     REG_ENLPM                                                   1'b0
+    16      R/W     EN_DBGO                                                     1'b0
+    17      R/W     EN_BBX                                                      1'b0
+    19:18   R/W     SDZ2D                                                       2'b00
+    22:20   R/W     SDZ2                                                        3'b000
+    24:23   R/W     SDZ1                                                        2'b00
+    26:25   R/W     ZCDLY_SET                                                   2'b10
+    28:27   R/W     ENZCDLY2_SET                                                2'b00
+    30:29   R/W     ENZCDLY1_SET                                                2'b01
+    31      R/W     ENDLY_FOR_K                                                 1'b1
+ */
+typedef union _AON_REG_SIMO_REG4X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t ENCCMDLYSET: 2;
+        uint32_t LPMCMPDLY_SET: 2;
+        uint32_t IBRDY2SET: 2;
+        uint32_t IBRDY1SET: 2;
+        uint32_t BYP_OPOR_LD: 1;
+        uint32_t EN_SYNC: 1;
+        uint32_t REG_FORCE_ENPOSTD: 1;
+        uint32_t REG_FORCE_ENPOST: 1;
+        uint32_t REG_ENNCP: 1;
+        uint32_t REG_ENPCCM: 1;
+        uint32_t REG_ENHQ_REFCMP: 1;
+        uint32_t REG_ENLPM: 1;
+        uint32_t EN_DBGO: 1;
+        uint32_t EN_BBX: 1;
+        uint32_t SDZ2D: 2;
+        uint32_t SDZ2: 3;
+        uint32_t SDZ1: 2;
+        uint32_t ZCDLY_SET: 2;
+        uint32_t ENZCDLY2_SET: 2;
+        uint32_t ENZCDLY1_SET: 2;
+        uint32_t ENDLY_FOR_K: 1;
+    };
+} AON_REG_SIMO_REG4X_TYPE;
+
+/*0x4000_068c AON_REG_SIMO_REG4X*/
+#define AON_REG_SIMO_REG4X_ENCCMDLYSET_Pos                                                                               0U
+#define AON_REG_SIMO_REG4X_ENCCMDLYSET_Msk                                                                               (0x3UL << AON_REG_SIMO_REG4X_ENCCMDLYSET_Pos)
+
+#define AON_REG_SIMO_REG4X_LPMCMPDLY_SET_Pos                                                                             2U
+#define AON_REG_SIMO_REG4X_LPMCMPDLY_SET_Msk                                                                             (0x3UL << AON_REG_SIMO_REG4X_LPMCMPDLY_SET_Pos)
+
+#define AON_REG_SIMO_REG4X_IBRDY2SET_Pos                                                                                 4U
+#define AON_REG_SIMO_REG4X_IBRDY2SET_Msk                                                                                 (0x3UL << AON_REG_SIMO_REG4X_IBRDY2SET_Pos)
+
+#define AON_REG_SIMO_REG4X_IBRDY1SET_Pos                                                                                 6U
+#define AON_REG_SIMO_REG4X_IBRDY1SET_Msk                                                                                 (0x3UL << AON_REG_SIMO_REG4X_IBRDY1SET_Pos)
+
+#define AON_REG_SIMO_REG4X_BYP_OPOR_LD_Pos                                                                               8U
+#define AON_REG_SIMO_REG4X_BYP_OPOR_LD_Msk                                                                               (0x1UL << AON_REG_SIMO_REG4X_BYP_OPOR_LD_Pos)
+
+#define AON_REG_SIMO_REG4X_EN_SYNC_Pos                                                                                   9U
+#define AON_REG_SIMO_REG4X_EN_SYNC_Msk                                                                                   (0x1UL << AON_REG_SIMO_REG4X_EN_SYNC_Pos)
+
+#define AON_REG_SIMO_REG4X_REG_FORCE_ENPOSTD_Pos                                                                         10U
+#define AON_REG_SIMO_REG4X_REG_FORCE_ENPOSTD_Msk                                                                         (0x1UL << AON_REG_SIMO_REG4X_REG_FORCE_ENPOSTD_Pos)
+
+#define AON_REG_SIMO_REG4X_REG_FORCE_ENPOST_Pos                                                                          11U
+#define AON_REG_SIMO_REG4X_REG_FORCE_ENPOST_Msk                                                                          (0x1UL << AON_REG_SIMO_REG4X_REG_FORCE_ENPOST_Pos)
+
+#define AON_REG_SIMO_REG4X_REG_ENNCP_Pos                                                                                 12U
+#define AON_REG_SIMO_REG4X_REG_ENNCP_Msk                                                                                 (0x1UL << AON_REG_SIMO_REG4X_REG_ENNCP_Pos)
+
+#define AON_REG_SIMO_REG4X_REG_ENPCCM_Pos                                                                                13U
+#define AON_REG_SIMO_REG4X_REG_ENPCCM_Msk                                                                                (0x1UL << AON_REG_SIMO_REG4X_REG_ENPCCM_Pos)
+
+#define AON_REG_SIMO_REG4X_REG_ENHQ_REFCMP_Pos                                                                           14U
+#define AON_REG_SIMO_REG4X_REG_ENHQ_REFCMP_Msk                                                                           (0x1UL << AON_REG_SIMO_REG4X_REG_ENHQ_REFCMP_Pos)
+
+#define AON_REG_SIMO_REG4X_REG_ENLPM_Pos                                                                                 15U
+#define AON_REG_SIMO_REG4X_REG_ENLPM_Msk                                                                                 (0x1UL << AON_REG_SIMO_REG4X_REG_ENLPM_Pos)
+
+#define AON_REG_SIMO_REG4X_EN_DBGO_Pos                                                                                   16U
+#define AON_REG_SIMO_REG4X_EN_DBGO_Msk                                                                                   (0x1UL << AON_REG_SIMO_REG4X_EN_DBGO_Pos)
+
+#define AON_REG_SIMO_REG4X_EN_BBX_Pos                                                                                    17U
+#define AON_REG_SIMO_REG4X_EN_BBX_Msk                                                                                    (0x1UL << AON_REG_SIMO_REG4X_EN_BBX_Pos)
+
+#define AON_REG_SIMO_REG4X_SDZ2D_Pos                                                                                     18U
+#define AON_REG_SIMO_REG4X_SDZ2D_Msk                                                                                     (0x3UL << AON_REG_SIMO_REG4X_SDZ2D_Pos)
+
+#define AON_REG_SIMO_REG4X_SDZ2_Pos                                                                                      20U
+#define AON_REG_SIMO_REG4X_SDZ2_Msk                                                                                      (0x7UL << AON_REG_SIMO_REG4X_SDZ2_Pos)
+
+#define AON_REG_SIMO_REG4X_SDZ1_Pos                                                                                      23U
+#define AON_REG_SIMO_REG4X_SDZ1_Msk                                                                                      (0x3UL << AON_REG_SIMO_REG4X_SDZ1_Pos)
+
+#define AON_REG_SIMO_REG4X_ZCDLY_SET_Pos                                                                                 25U
+#define AON_REG_SIMO_REG4X_ZCDLY_SET_Msk                                                                                 (0x3UL << AON_REG_SIMO_REG4X_ZCDLY_SET_Pos)
+
+#define AON_REG_SIMO_REG4X_ENZCDLY2_SET_Pos                                                                              27U
+#define AON_REG_SIMO_REG4X_ENZCDLY2_SET_Msk                                                                              (0x3UL << AON_REG_SIMO_REG4X_ENZCDLY2_SET_Pos)
+
+#define AON_REG_SIMO_REG4X_ENZCDLY1_SET_Pos                                                                              29U
+#define AON_REG_SIMO_REG4X_ENZCDLY1_SET_Msk                                                                              (0x3UL << AON_REG_SIMO_REG4X_ENZCDLY1_SET_Pos)
+
+#define AON_REG_SIMO_REG4X_ENDLY_FOR_K_Pos                                                                               31U
+#define AON_REG_SIMO_REG4X_ENDLY_FOR_K_Msk                                                                               (0x1UL << AON_REG_SIMO_REG4X_ENDLY_FOR_K_Pos)
+
+/* 0x690    0x4000_0690
+    1:0     R/W     MINTON2_SET                                                 2'b01
+    3:2     R/W     MINTON1_SET                                                 2'b01
+    5:4     R/W     EXTRA_TON_2_1                                               2'b00
+    10:6    R/W     TON2_TUNE                                                   5'b10000
+    15:11   R/W     TON1_TUNE                                                   5'b10000
+    16      R/W     EN_CMPLQ_RSTPUL                                             1'b1
+    17      R/W     BYP_LPMCMPDLY                                               1'b1
+    18      R/W     CK_CS_LCH                                                   1'b0
+    19      R/W     BYP_CSSS                                                    1'b0
+    22:20   R/W     TUNE_DC_MODDET                                              3'b011
+    24:23   R/W     MAXTON2_SET                                                 2'b01
+    25      R/W     ENB_AC_MODDET                                               1'b0
+    27:26   R/W     REG11X_DMY1                                                 2'b10
+    28      R/W     EN_DC_MODDET                                                1'b1
+    31:29   R/W     TUNE_ITON                                                   3'b100
+ */
+typedef union _AON_REG_SIMO_REG5X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t MINTON2_SET: 2;
+        uint32_t MINTON1_SET: 2;
+        uint32_t EXTRA_TON_2_1: 2;
+        uint32_t TON2_TUNE: 5;
+        uint32_t TON1_TUNE: 5;
+        uint32_t EN_CMPLQ_RSTPUL: 1;
+        uint32_t BYP_LPMCMPDLY: 1;
+        uint32_t CK_CS_LCH: 1;
+        uint32_t BYP_CSSS: 1;
+        uint32_t TUNE_DC_MODDET: 3;
+        uint32_t MAXTON2_SET: 2;
+        uint32_t ENB_AC_MODDET: 1;
+        uint32_t REG11X_DMY1: 2;
+        uint32_t EN_DC_MODDET: 1;
+        uint32_t TUNE_ITON: 3;
+    };
+} AON_REG_SIMO_REG5X_TYPE;
+
+/*0x4000_0690 AON_REG_SIMO_REG5X*/
+#define AON_REG_SIMO_REG5X_MINTON2_SET_Pos                                                                               0U
+#define AON_REG_SIMO_REG5X_MINTON2_SET_Msk                                                                               (0x3UL << AON_REG_SIMO_REG5X_MINTON2_SET_Pos)
+
+#define AON_REG_SIMO_REG5X_MINTON1_SET_Pos                                                                               2U
+#define AON_REG_SIMO_REG5X_MINTON1_SET_Msk                                                                               (0x3UL << AON_REG_SIMO_REG5X_MINTON1_SET_Pos)
+
+#define AON_REG_SIMO_REG5X_EXTRA_TON_2_1_Pos                                                                             4U
+#define AON_REG_SIMO_REG5X_EXTRA_TON_2_1_Msk                                                                             (0x3UL << AON_REG_SIMO_REG5X_EXTRA_TON_2_1_Pos)
+
+#define AON_REG_SIMO_REG5X_TON2_TUNE_Pos                                                                                 6U
+#define AON_REG_SIMO_REG5X_TON2_TUNE_Msk                                                                                 (0x1FUL << AON_REG_SIMO_REG5X_TON2_TUNE_Pos)
+
+#define AON_REG_SIMO_REG5X_TON1_TUNE_Pos                                                                                 11U
+#define AON_REG_SIMO_REG5X_TON1_TUNE_Msk                                                                                 (0x1FUL << AON_REG_SIMO_REG5X_TON1_TUNE_Pos)
+
+#define AON_REG_SIMO_REG5X_EN_CMPLQ_RSTPUL_Pos                                                                           16U
+#define AON_REG_SIMO_REG5X_EN_CMPLQ_RSTPUL_Msk                                                                           (0x1UL << AON_REG_SIMO_REG5X_EN_CMPLQ_RSTPUL_Pos)
+
+#define AON_REG_SIMO_REG5X_BYP_LPMCMPDLY_Pos                                                                             17U
+#define AON_REG_SIMO_REG5X_BYP_LPMCMPDLY_Msk                                                                             (0x1UL << AON_REG_SIMO_REG5X_BYP_LPMCMPDLY_Pos)
+
+#define AON_REG_SIMO_REG5X_CK_CS_LCH_Pos                                                                                 18U
+#define AON_REG_SIMO_REG5X_CK_CS_LCH_Msk                                                                                 (0x1UL << AON_REG_SIMO_REG5X_CK_CS_LCH_Pos)
+
+#define AON_REG_SIMO_REG5X_BYP_CSSS_Pos                                                                                  19U
+#define AON_REG_SIMO_REG5X_BYP_CSSS_Msk                                                                                  (0x1UL << AON_REG_SIMO_REG5X_BYP_CSSS_Pos)
+
+#define AON_REG_SIMO_REG5X_TUNE_DC_MODDET_Pos                                                                            20U
+#define AON_REG_SIMO_REG5X_TUNE_DC_MODDET_Msk                                                                            (0x7UL << AON_REG_SIMO_REG5X_TUNE_DC_MODDET_Pos)
+
+#define AON_REG_SIMO_REG5X_MAXTON2_SET_Pos                                                                               23U
+#define AON_REG_SIMO_REG5X_MAXTON2_SET_Msk                                                                               (0x3UL << AON_REG_SIMO_REG5X_MAXTON2_SET_Pos)
+
+#define AON_REG_SIMO_REG5X_ENB_AC_MODDET_Pos                                                                             25U
+#define AON_REG_SIMO_REG5X_ENB_AC_MODDET_Msk                                                                             (0x1UL << AON_REG_SIMO_REG5X_ENB_AC_MODDET_Pos)
+
+#define AON_REG_SIMO_REG5X_REG11X_DMY1_Pos                                                                               26U
+#define AON_REG_SIMO_REG5X_REG11X_DMY1_Msk                                                                               (0x3UL << AON_REG_SIMO_REG5X_REG11X_DMY1_Pos)
+
+#define AON_REG_SIMO_REG5X_EN_DC_MODDET_Pos                                                                              28U
+#define AON_REG_SIMO_REG5X_EN_DC_MODDET_Msk                                                                              (0x1UL << AON_REG_SIMO_REG5X_EN_DC_MODDET_Pos)
+
+#define AON_REG_SIMO_REG5X_TUNE_ITON_Pos                                                                                 29U
+#define AON_REG_SIMO_REG5X_TUNE_ITON_Msk                                                                                 (0x7UL << AON_REG_SIMO_REG5X_TUNE_ITON_Pos)
+
+/* 0x694    0x4000_0694
+    1:0     R/W     REG12X_DMY                                                  2'b00
+    8:2     R/W     ZCDOFFSET2                                                  7'b0001100
+    15:9    R/W     ZCDOFFSET1                                                  7'b0001100
+    17:16   R/W     REG13X_DMY                                                  2'b00
+    24:18   R/W     ZCDOFFSET4                                                  7'b0001100
+    31:25   R/W     ZCDOFFSET3                                                  7'b0001100
+ */
+typedef union _AON_REG_SIMO_REG6X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t REG12X_DMY: 2;
+        uint32_t ZCDOFFSET2: 7;
+        uint32_t ZCDOFFSET1: 7;
+        uint32_t REG13X_DMY: 2;
+        uint32_t ZCDOFFSET4: 7;
+        uint32_t ZCDOFFSET3: 7;
+    };
+} AON_REG_SIMO_REG6X_TYPE;
+
+/*0x4000_0694 AON_REG_SIMO_REG6X*/
+#define AON_REG_SIMO_REG6X_REG12X_DMY_Pos                                                                                0U
+#define AON_REG_SIMO_REG6X_REG12X_DMY_Msk                                                                                (0x3UL << AON_REG_SIMO_REG6X_REG12X_DMY_Pos)
+
+#define AON_REG_SIMO_REG6X_ZCDOFFSET2_Pos                                                                                2U
+#define AON_REG_SIMO_REG6X_ZCDOFFSET2_Msk                                                                                (0x7FUL << AON_REG_SIMO_REG6X_ZCDOFFSET2_Pos)
+
+#define AON_REG_SIMO_REG6X_ZCDOFFSET1_Pos                                                                                9U
+#define AON_REG_SIMO_REG6X_ZCDOFFSET1_Msk                                                                                (0x7FUL << AON_REG_SIMO_REG6X_ZCDOFFSET1_Pos)
+
+#define AON_REG_SIMO_REG6X_REG13X_DMY_Pos                                                                                16U
+#define AON_REG_SIMO_REG6X_REG13X_DMY_Msk                                                                                (0x3UL << AON_REG_SIMO_REG6X_REG13X_DMY_Pos)
+
+#define AON_REG_SIMO_REG6X_ZCDOFFSET4_Pos                                                                                18U
+#define AON_REG_SIMO_REG6X_ZCDOFFSET4_Msk                                                                                (0x7FUL << AON_REG_SIMO_REG6X_ZCDOFFSET4_Pos)
+
+#define AON_REG_SIMO_REG6X_ZCDOFFSET3_Pos                                                                                25U
+#define AON_REG_SIMO_REG6X_ZCDOFFSET3_Msk                                                                                (0x7FUL << AON_REG_SIMO_REG6X_ZCDOFFSET3_Pos)
+
+/* 0x698    0x4000_0698
+    3:0     R/W     REG14X_DMY                                                  4'b0000
+    8:4     R/W     FORCE_CODE                                                  5'b00000
+    15:9    R/W     ZCDOFFSET5                                                  7'b0001100
+    16      R/W     ENFBC_1245                                                  1'b0
+    17      R/W     ENFBC_3                                                     1'b0
+    18      R/W     SEL_CMPLQ_IQ2X_14                                           1'b0
+    19      R/W     SEL_CMPLQ_IQ2X_25                                           1'b0
+    20      R/W     SEL_CMPHQ_IQ2X_1245                                         1'b0
+    21      R/W     SEL_CMPHQ_IQ2X_3                                            1'b0
+    23:22   R/W     SEL_PS_1_0                                                  2'b01
+    24      R/W     ENB_AUTO_PS                                                 1'b1
+    25      R/W     SEL_SYNC2                                                   1'b1
+    26      R/W     EN_SYNC2                                                    1'b0
+    31:27   R/W     STICKY_CODE                                                 5'b00000
+ */
+typedef union _AON_REG_SIMO_REG7X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t REG14X_DMY: 4;
+        uint32_t FORCE_CODE: 5;
+        uint32_t ZCDOFFSET5: 7;
+        uint32_t ENFBC_1245: 1;
+        uint32_t ENFBC_3: 1;
+        uint32_t SEL_CMPLQ_IQ2X_14: 1;
+        uint32_t SEL_CMPLQ_IQ2X_25: 1;
+        uint32_t SEL_CMPHQ_IQ2X_1245: 1;
+        uint32_t SEL_CMPHQ_IQ2X_3: 1;
+        uint32_t SEL_PS_1_0: 2;
+        uint32_t ENB_AUTO_PS: 1;
+        uint32_t SEL_SYNC2: 1;
+        uint32_t EN_SYNC2: 1;
+        uint32_t STICKY_CODE: 5;
+    };
+} AON_REG_SIMO_REG7X_TYPE;
+
+/*0x4000_0698 AON_REG_SIMO_REG7X*/
+#define AON_REG_SIMO_REG7X_REG14X_DMY_Pos                                                                                0U
+#define AON_REG_SIMO_REG7X_REG14X_DMY_Msk                                                                                (0xFUL << AON_REG_SIMO_REG7X_REG14X_DMY_Pos)
+
+#define AON_REG_SIMO_REG7X_FORCE_CODE_Pos                                                                                4U
+#define AON_REG_SIMO_REG7X_FORCE_CODE_Msk                                                                                (0x1FUL << AON_REG_SIMO_REG7X_FORCE_CODE_Pos)
+
+#define AON_REG_SIMO_REG7X_ZCDOFFSET5_Pos                                                                                9U
+#define AON_REG_SIMO_REG7X_ZCDOFFSET5_Msk                                                                                (0x7FUL << AON_REG_SIMO_REG7X_ZCDOFFSET5_Pos)
+
+#define AON_REG_SIMO_REG7X_ENFBC_1245_Pos                                                                                16U
+#define AON_REG_SIMO_REG7X_ENFBC_1245_Msk                                                                                (0x1UL << AON_REG_SIMO_REG7X_ENFBC_1245_Pos)
+
+#define AON_REG_SIMO_REG7X_ENFBC_3_Pos                                                                                   17U
+#define AON_REG_SIMO_REG7X_ENFBC_3_Msk                                                                                   (0x1UL << AON_REG_SIMO_REG7X_ENFBC_3_Pos)
+
+#define AON_REG_SIMO_REG7X_SEL_CMPLQ_IQ2X_14_Pos                                                                         18U
+#define AON_REG_SIMO_REG7X_SEL_CMPLQ_IQ2X_14_Msk                                                                         (0x1UL << AON_REG_SIMO_REG7X_SEL_CMPLQ_IQ2X_14_Pos)
+
+#define AON_REG_SIMO_REG7X_SEL_CMPLQ_IQ2X_25_Pos                                                                         19U
+#define AON_REG_SIMO_REG7X_SEL_CMPLQ_IQ2X_25_Msk                                                                         (0x1UL << AON_REG_SIMO_REG7X_SEL_CMPLQ_IQ2X_25_Pos)
+
+#define AON_REG_SIMO_REG7X_SEL_CMPHQ_IQ2X_1245_Pos                                                                       20U
+#define AON_REG_SIMO_REG7X_SEL_CMPHQ_IQ2X_1245_Msk                                                                       (0x1UL << AON_REG_SIMO_REG7X_SEL_CMPHQ_IQ2X_1245_Pos)
+
+#define AON_REG_SIMO_REG7X_SEL_CMPHQ_IQ2X_3_Pos                                                                          21U
+#define AON_REG_SIMO_REG7X_SEL_CMPHQ_IQ2X_3_Msk                                                                          (0x1UL << AON_REG_SIMO_REG7X_SEL_CMPHQ_IQ2X_3_Pos)
+
+#define AON_REG_SIMO_REG7X_SEL_PS_1_0_Pos                                                                                22U
+#define AON_REG_SIMO_REG7X_SEL_PS_1_0_Msk                                                                                (0x3UL << AON_REG_SIMO_REG7X_SEL_PS_1_0_Pos)
+
+#define AON_REG_SIMO_REG7X_ENB_AUTO_PS_Pos                                                                               24U
+#define AON_REG_SIMO_REG7X_ENB_AUTO_PS_Msk                                                                               (0x1UL << AON_REG_SIMO_REG7X_ENB_AUTO_PS_Pos)
+
+#define AON_REG_SIMO_REG7X_SEL_SYNC2_Pos                                                                                 25U
+#define AON_REG_SIMO_REG7X_SEL_SYNC2_Msk                                                                                 (0x1UL << AON_REG_SIMO_REG7X_SEL_SYNC2_Pos)
+
+#define AON_REG_SIMO_REG7X_EN_SYNC2_Pos                                                                                  26U
+#define AON_REG_SIMO_REG7X_EN_SYNC2_Msk                                                                                  (0x1UL << AON_REG_SIMO_REG7X_EN_SYNC2_Pos)
+
+#define AON_REG_SIMO_REG7X_STICKY_CODE_Pos                                                                               27U
+#define AON_REG_SIMO_REG7X_STICKY_CODE_Msk                                                                               (0x1FUL << AON_REG_SIMO_REG7X_STICKY_CODE_Pos)
+
+/* 0x69C    0x4000_069c
+    1:0     R/W     C2DT2_SET                                                   2'b00
+    2       R/W     C2DT2_LDLY                                                  1'b0
+    3       R/W     C2DT2_BP                                                    1'b1
+    5:4     R/W     C2DT1_SET                                                   2'b00
+    6       R/W     C2DT1_LDLY                                                  1'b0
+    7       R/W     C2DT1_BP                                                    1'b1
+    9:8     R/W     C1DT2_SET                                                   2'b00
+    10      R/W     C1DT2_LDLY                                                  1'b0
+    11      R/W     C1DT2_BP                                                    1'b1
+    13:12   R/W     C1DT1_SET                                                   2'b00
+    14      R/W     C1DT1_LDLY                                                  1'b0
+    15      R/W     C1DT1_BP                                                    1'b1
+    16      R/W     REG17X_DMY2                                                 1'b0
+    18:17   R/W     DRV41_DT                                                    2'b00
+    20:19   R/W     DRV3_SRC                                                    2'b11
+    22:21   R/W     DRV3_SNK                                                    2'b11
+    24:23   R/W     DRV2_SRC                                                    2'b11
+    26:25   R/W     DRV2_SNK                                                    2'b11
+    28:27   R/W     DRV1_SRC                                                    2'b11
+    30:29   R/W     DRV1_SNK                                                    2'b11
+    31      R/W     REG17X_DMY1                                                 1'b0
+ */
+typedef union _AON_REG_SIMO_REG8X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t C2DT2_SET: 2;
+        uint32_t C2DT2_LDLY: 1;
+        uint32_t C2DT2_BP: 1;
+        uint32_t C2DT1_SET: 2;
+        uint32_t C2DT1_LDLY: 1;
+        uint32_t C2DT1_BP: 1;
+        uint32_t C1DT2_SET: 2;
+        uint32_t C1DT2_LDLY: 1;
+        uint32_t C1DT2_BP: 1;
+        uint32_t C1DT1_SET: 2;
+        uint32_t C1DT1_LDLY: 1;
+        uint32_t C1DT1_BP: 1;
+        uint32_t REG17X_DMY2: 1;
+        uint32_t DRV41_DT: 2;
+        uint32_t DRV3_SRC: 2;
+        uint32_t DRV3_SNK: 2;
+        uint32_t DRV2_SRC: 2;
+        uint32_t DRV2_SNK: 2;
+        uint32_t DRV1_SRC: 2;
+        uint32_t DRV1_SNK: 2;
+        uint32_t REG17X_DMY1: 1;
+    };
+} AON_REG_SIMO_REG8X_TYPE;
+
+/*0x4000_069c AON_REG_SIMO_REG8X*/
+#define AON_REG_SIMO_REG8X_C2DT2_SET_Pos                                                                                 0U
+#define AON_REG_SIMO_REG8X_C2DT2_SET_Msk                                                                                 (0x3UL << AON_REG_SIMO_REG8X_C2DT2_SET_Pos)
+
+#define AON_REG_SIMO_REG8X_C2DT2_LDLY_Pos                                                                                2U
+#define AON_REG_SIMO_REG8X_C2DT2_LDLY_Msk                                                                                (0x1UL << AON_REG_SIMO_REG8X_C2DT2_LDLY_Pos)
+
+#define AON_REG_SIMO_REG8X_C2DT2_BP_Pos                                                                                  3U
+#define AON_REG_SIMO_REG8X_C2DT2_BP_Msk                                                                                  (0x1UL << AON_REG_SIMO_REG8X_C2DT2_BP_Pos)
+
+#define AON_REG_SIMO_REG8X_C2DT1_SET_Pos                                                                                 4U
+#define AON_REG_SIMO_REG8X_C2DT1_SET_Msk                                                                                 (0x3UL << AON_REG_SIMO_REG8X_C2DT1_SET_Pos)
+
+#define AON_REG_SIMO_REG8X_C2DT1_LDLY_Pos                                                                                6U
+#define AON_REG_SIMO_REG8X_C2DT1_LDLY_Msk                                                                                (0x1UL << AON_REG_SIMO_REG8X_C2DT1_LDLY_Pos)
+
+#define AON_REG_SIMO_REG8X_C2DT1_BP_Pos                                                                                  7U
+#define AON_REG_SIMO_REG8X_C2DT1_BP_Msk                                                                                  (0x1UL << AON_REG_SIMO_REG8X_C2DT1_BP_Pos)
+
+#define AON_REG_SIMO_REG8X_C1DT2_SET_Pos                                                                                 8U
+#define AON_REG_SIMO_REG8X_C1DT2_SET_Msk                                                                                 (0x3UL << AON_REG_SIMO_REG8X_C1DT2_SET_Pos)
+
+#define AON_REG_SIMO_REG8X_C1DT2_LDLY_Pos                                                                                10U
+#define AON_REG_SIMO_REG8X_C1DT2_LDLY_Msk                                                                                (0x1UL << AON_REG_SIMO_REG8X_C1DT2_LDLY_Pos)
+
+#define AON_REG_SIMO_REG8X_C1DT2_BP_Pos                                                                                  11U
+#define AON_REG_SIMO_REG8X_C1DT2_BP_Msk                                                                                  (0x1UL << AON_REG_SIMO_REG8X_C1DT2_BP_Pos)
+
+#define AON_REG_SIMO_REG8X_C1DT1_SET_Pos                                                                                 12U
+#define AON_REG_SIMO_REG8X_C1DT1_SET_Msk                                                                                 (0x3UL << AON_REG_SIMO_REG8X_C1DT1_SET_Pos)
+
+#define AON_REG_SIMO_REG8X_C1DT1_LDLY_Pos                                                                                14U
+#define AON_REG_SIMO_REG8X_C1DT1_LDLY_Msk                                                                                (0x1UL << AON_REG_SIMO_REG8X_C1DT1_LDLY_Pos)
+
+#define AON_REG_SIMO_REG8X_C1DT1_BP_Pos                                                                                  15U
+#define AON_REG_SIMO_REG8X_C1DT1_BP_Msk                                                                                  (0x1UL << AON_REG_SIMO_REG8X_C1DT1_BP_Pos)
+
+#define AON_REG_SIMO_REG8X_REG17X_DMY2_Pos                                                                               16U
+#define AON_REG_SIMO_REG8X_REG17X_DMY2_Msk                                                                               (0x1UL << AON_REG_SIMO_REG8X_REG17X_DMY2_Pos)
+
+#define AON_REG_SIMO_REG8X_DRV41_DT_Pos                                                                                  17U
+#define AON_REG_SIMO_REG8X_DRV41_DT_Msk                                                                                  (0x3UL << AON_REG_SIMO_REG8X_DRV41_DT_Pos)
+
+#define AON_REG_SIMO_REG8X_DRV3_SRC_Pos                                                                                  19U
+#define AON_REG_SIMO_REG8X_DRV3_SRC_Msk                                                                                  (0x3UL << AON_REG_SIMO_REG8X_DRV3_SRC_Pos)
+
+#define AON_REG_SIMO_REG8X_DRV3_SNK_Pos                                                                                  21U
+#define AON_REG_SIMO_REG8X_DRV3_SNK_Msk                                                                                  (0x3UL << AON_REG_SIMO_REG8X_DRV3_SNK_Pos)
+
+#define AON_REG_SIMO_REG8X_DRV2_SRC_Pos                                                                                  23U
+#define AON_REG_SIMO_REG8X_DRV2_SRC_Msk                                                                                  (0x3UL << AON_REG_SIMO_REG8X_DRV2_SRC_Pos)
+
+#define AON_REG_SIMO_REG8X_DRV2_SNK_Pos                                                                                  25U
+#define AON_REG_SIMO_REG8X_DRV2_SNK_Msk                                                                                  (0x3UL << AON_REG_SIMO_REG8X_DRV2_SNK_Pos)
+
+#define AON_REG_SIMO_REG8X_DRV1_SRC_Pos                                                                                  27U
+#define AON_REG_SIMO_REG8X_DRV1_SRC_Msk                                                                                  (0x3UL << AON_REG_SIMO_REG8X_DRV1_SRC_Pos)
+
+#define AON_REG_SIMO_REG8X_DRV1_SNK_Pos                                                                                  29U
+#define AON_REG_SIMO_REG8X_DRV1_SNK_Msk                                                                                  (0x3UL << AON_REG_SIMO_REG8X_DRV1_SNK_Pos)
+
+#define AON_REG_SIMO_REG8X_REG17X_DMY1_Pos                                                                               31U
+#define AON_REG_SIMO_REG8X_REG17X_DMY1_Msk                                                                               (0x1UL << AON_REG_SIMO_REG8X_REG17X_DMY1_Pos)
+
+/* 0x6A0    0x4000_06a0
+    3:0     R/W     REG18X_DMY                                                  4'b0000
+    5:4     R/W     DRV43_SRC                                                   2'b11
+    6       R/W     DRV43_EN_WELL_LX2                                           1'b1
+    8:7     R/W     DRV43_DT                                                    2'b00
+    9       R/W     DRV42_EN_WELL_LX2                                           1'b1
+    11:10   R/W     DRV42_DT                                                    2'b00
+    13:12   R/W     DRV41_SRC                                                   2'b11
+    15:14   R/W     DRV41_SNK                                                   2'b11
+    16      R/W     VDDIO_EN_DISCHG                                             1'b0
+    17      R/W     VDDIO_EN_PC2                                                1'b0
+    18      R/W     VDDIO_EN_PC1                                                1'b0
+    21:19   R/W     DRV4DT_BP_2_0                                               3'b000
+    23:22   R/W     DRV45_SRC                                                   2'b11
+    24      R/W     DRV45_EN_WELL_LX2                                           1'b1
+    26:25   R/W     DRV45_DT                                                    2'b00
+    28:27   R/W     DRV44_SRC                                                   2'b11
+    29      R/W     DRV44_EN_WELL_LX2                                           1'b1
+    31:30   R/W     DRV44_DT                                                    2'b00
+ */
+typedef union _AON_REG_SIMO_REG9X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t REG18X_DMY: 4;
+        uint32_t DRV43_SRC: 2;
+        uint32_t DRV43_EN_WELL_LX2: 1;
+        uint32_t DRV43_DT: 2;
+        uint32_t DRV42_EN_WELL_LX2: 1;
+        uint32_t DRV42_DT: 2;
+        uint32_t DRV41_SRC: 2;
+        uint32_t DRV41_SNK: 2;
+        uint32_t VDDIO_EN_DISCHG: 1;
+        uint32_t VDDIO_EN_PC2: 1;
+        uint32_t VDDIO_EN_PC1: 1;
+        uint32_t DRV4DT_BP_2_0: 3;
+        uint32_t DRV45_SRC: 2;
+        uint32_t DRV45_EN_WELL_LX2: 1;
+        uint32_t DRV45_DT: 2;
+        uint32_t DRV44_SRC: 2;
+        uint32_t DRV44_EN_WELL_LX2: 1;
+        uint32_t DRV44_DT: 2;
+    };
+} AON_REG_SIMO_REG9X_TYPE;
+
+/*0x4000_06a0 AON_REG_SIMO_REG9X*/
+#define AON_REG_SIMO_REG9X_REG18X_DMY_Pos                                                                                0U
+#define AON_REG_SIMO_REG9X_REG18X_DMY_Msk                                                                                (0xFUL << AON_REG_SIMO_REG9X_REG18X_DMY_Pos)
+
+#define AON_REG_SIMO_REG9X_DRV43_SRC_Pos                                                                                 4U
+#define AON_REG_SIMO_REG9X_DRV43_SRC_Msk                                                                                 (0x3UL << AON_REG_SIMO_REG9X_DRV43_SRC_Pos)
+
+#define AON_REG_SIMO_REG9X_DRV43_EN_WELL_LX2_Pos                                                                         6U
+#define AON_REG_SIMO_REG9X_DRV43_EN_WELL_LX2_Msk                                                                         (0x1UL << AON_REG_SIMO_REG9X_DRV43_EN_WELL_LX2_Pos)
+
+#define AON_REG_SIMO_REG9X_DRV43_DT_Pos                                                                                  7U
+#define AON_REG_SIMO_REG9X_DRV43_DT_Msk                                                                                  (0x3UL << AON_REG_SIMO_REG9X_DRV43_DT_Pos)
+
+#define AON_REG_SIMO_REG9X_DRV42_EN_WELL_LX2_Pos                                                                         9U
+#define AON_REG_SIMO_REG9X_DRV42_EN_WELL_LX2_Msk                                                                         (0x1UL << AON_REG_SIMO_REG9X_DRV42_EN_WELL_LX2_Pos)
+
+#define AON_REG_SIMO_REG9X_DRV42_DT_Pos                                                                                  10U
+#define AON_REG_SIMO_REG9X_DRV42_DT_Msk                                                                                  (0x3UL << AON_REG_SIMO_REG9X_DRV42_DT_Pos)
+
+#define AON_REG_SIMO_REG9X_DRV41_SRC_Pos                                                                                 12U
+#define AON_REG_SIMO_REG9X_DRV41_SRC_Msk                                                                                 (0x3UL << AON_REG_SIMO_REG9X_DRV41_SRC_Pos)
+
+#define AON_REG_SIMO_REG9X_DRV41_SNK_Pos                                                                                 14U
+#define AON_REG_SIMO_REG9X_DRV41_SNK_Msk                                                                                 (0x3UL << AON_REG_SIMO_REG9X_DRV41_SNK_Pos)
+
+#define AON_REG_SIMO_REG9X_VDDIO_EN_DISCHG_Pos                                                                           16U
+#define AON_REG_SIMO_REG9X_VDDIO_EN_DISCHG_Msk                                                                           (0x1UL << AON_REG_SIMO_REG9X_VDDIO_EN_DISCHG_Pos)
+
+#define AON_REG_SIMO_REG9X_VDDIO_EN_PC2_Pos                                                                              17U
+#define AON_REG_SIMO_REG9X_VDDIO_EN_PC2_Msk                                                                              (0x1UL << AON_REG_SIMO_REG9X_VDDIO_EN_PC2_Pos)
+
+#define AON_REG_SIMO_REG9X_VDDIO_EN_PC1_Pos                                                                              18U
+#define AON_REG_SIMO_REG9X_VDDIO_EN_PC1_Msk                                                                              (0x1UL << AON_REG_SIMO_REG9X_VDDIO_EN_PC1_Pos)
+
+#define AON_REG_SIMO_REG9X_DRV4DT_BP_2_0_Pos                                                                             19U
+#define AON_REG_SIMO_REG9X_DRV4DT_BP_2_0_Msk                                                                             (0x7UL << AON_REG_SIMO_REG9X_DRV4DT_BP_2_0_Pos)
+
+#define AON_REG_SIMO_REG9X_DRV45_SRC_Pos                                                                                 22U
+#define AON_REG_SIMO_REG9X_DRV45_SRC_Msk                                                                                 (0x3UL << AON_REG_SIMO_REG9X_DRV45_SRC_Pos)
+
+#define AON_REG_SIMO_REG9X_DRV45_EN_WELL_LX2_Pos                                                                         24U
+#define AON_REG_SIMO_REG9X_DRV45_EN_WELL_LX2_Msk                                                                         (0x1UL << AON_REG_SIMO_REG9X_DRV45_EN_WELL_LX2_Pos)
+
+#define AON_REG_SIMO_REG9X_DRV45_DT_Pos                                                                                  25U
+#define AON_REG_SIMO_REG9X_DRV45_DT_Msk                                                                                  (0x3UL << AON_REG_SIMO_REG9X_DRV45_DT_Pos)
+
+#define AON_REG_SIMO_REG9X_DRV44_SRC_Pos                                                                                 27U
+#define AON_REG_SIMO_REG9X_DRV44_SRC_Msk                                                                                 (0x3UL << AON_REG_SIMO_REG9X_DRV44_SRC_Pos)
+
+#define AON_REG_SIMO_REG9X_DRV44_EN_WELL_LX2_Pos                                                                         29U
+#define AON_REG_SIMO_REG9X_DRV44_EN_WELL_LX2_Msk                                                                         (0x1UL << AON_REG_SIMO_REG9X_DRV44_EN_WELL_LX2_Pos)
+
+#define AON_REG_SIMO_REG9X_DRV44_DT_Pos                                                                                  30U
+#define AON_REG_SIMO_REG9X_DRV44_DT_Msk                                                                                  (0x3UL << AON_REG_SIMO_REG9X_DRV44_DT_Pos)
+
+/* 0x6A4    0x4000_06a4
+    0       R       ENHQ_RDY_SYNC                                               1'b0
+    1       R       EN_POST_SYNC                                                1'b0
+    2       R       ZC_SET_O                                                    1'b0
+    3       R       ZC_POR_O                                                    1'b0
+    4       R       PRI_SEL_OK                                                  1'b0
+    5       R       PRI_TRIG                                                    1'b0
+    6       R       MINOFFOK                                                    1'b0
+    7       R       ENTON                                                       1'b0
+    8       R       ENTON1                                                      1'b0
+    9       R       OCCUPY_OR                                                   1'b0
+    10      R       PWMTONU1_0                                                  1'b0
+    11      R       PWMTONL2_0                                                  1'b0
+    12      R       HYS_BUCK_AC                                                 1'b0
+    13      R       HYS_BST_AC                                                  1'b0
+    14      R       CMP_BUCK_DC_OUT                                             1'b0
+    15      R       CMP_BST_DC_OUT                                              1'b0
+    16      R       ENPOST_D                                                    1'b0
+    17      R       ENPOST                                                      1'b0
+    18      R       VOUT2_ZCPOR                                                 1'b0
+    19      R       PORB_VOUTT1                                                 1'b0
+    20      R       SEL_A_I                                                     1'b0
+    21      R       CCM_NEED                                                    1'b0
+    22      R       ENLPM_SYNC                                                  1'b0
+    23      R       DRV1_EN_NCP                                                 1'b0
+    24      R       ENTON2_UG2                                                  1'b0
+    25      R       POWTONL2                                                    1'b0
+    26      R       ENLG1                                                       1'b0
+    27      R       POWTONU1                                                    1'b0
+    28      R       IBTHR_RDY                                                   1'b0
+    29      R       UABIAS_RDY2                                                 1'b0
+    30      R       UABIAS_RDY                                                  1'b0
+    31      R       ENUABIAS                                                    1'b0
+ */
+typedef union _AON_C_KOUT0X_SIMO_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t ENHQ_RDY_SYNC: 1;
+        uint32_t EN_POST_SYNC: 1;
+        uint32_t ZC_SET_O: 1;
+        uint32_t ZC_POR_O: 1;
+        uint32_t PRI_SEL_OK: 1;
+        uint32_t PRI_TRIG: 1;
+        uint32_t MINOFFOK: 1;
+        uint32_t ENTON: 1;
+        uint32_t ENTON1: 1;
+        uint32_t OCCUPY_OR: 1;
+        uint32_t PWMTONU1_0: 1;
+        uint32_t PWMTONL2_0: 1;
+        uint32_t HYS_BUCK_AC: 1;
+        uint32_t HYS_BST_AC: 1;
+        uint32_t CMP_BUCK_DC_OUT: 1;
+        uint32_t CMP_BST_DC_OUT: 1;
+        uint32_t ENPOST_D: 1;
+        uint32_t ENPOST: 1;
+        uint32_t VOUT2_ZCPOR: 1;
+        uint32_t PORB_VOUTT1: 1;
+        uint32_t SEL_A_I: 1;
+        uint32_t CCM_NEED: 1;
+        uint32_t ENLPM_SYNC: 1;
+        uint32_t DRV1_EN_NCP: 1;
+        uint32_t ENTON2_UG2: 1;
+        uint32_t POWTONL2: 1;
+        uint32_t ENLG1: 1;
+        uint32_t POWTONU1: 1;
+        uint32_t IBTHR_RDY: 1;
+        uint32_t UABIAS_RDY2: 1;
+        uint32_t UABIAS_RDY: 1;
+        uint32_t ENUABIAS: 1;
+    };
+} AON_C_KOUT0X_SIMO_TYPE;
+
+/*0x4000_06a4 AON_C_KOUT0X_SIMO*/
+#define AON_C_KOUT0X_SIMO_ENHQ_RDY_SYNC_Pos                                                                              0U
+#define AON_C_KOUT0X_SIMO_ENHQ_RDY_SYNC_Msk                                                                              (0x1UL << AON_C_KOUT0X_SIMO_ENHQ_RDY_SYNC_Pos)
+
+#define AON_C_KOUT0X_SIMO_EN_POST_SYNC_Pos                                                                               1U
+#define AON_C_KOUT0X_SIMO_EN_POST_SYNC_Msk                                                                               (0x1UL << AON_C_KOUT0X_SIMO_EN_POST_SYNC_Pos)
+
+#define AON_C_KOUT0X_SIMO_ZC_SET_O_Pos                                                                                   2U
+#define AON_C_KOUT0X_SIMO_ZC_SET_O_Msk                                                                                   (0x1UL << AON_C_KOUT0X_SIMO_ZC_SET_O_Pos)
+
+#define AON_C_KOUT0X_SIMO_ZC_POR_O_Pos                                                                                   3U
+#define AON_C_KOUT0X_SIMO_ZC_POR_O_Msk                                                                                   (0x1UL << AON_C_KOUT0X_SIMO_ZC_POR_O_Pos)
+
+#define AON_C_KOUT0X_SIMO_PRI_SEL_OK_Pos                                                                                 4U
+#define AON_C_KOUT0X_SIMO_PRI_SEL_OK_Msk                                                                                 (0x1UL << AON_C_KOUT0X_SIMO_PRI_SEL_OK_Pos)
+
+#define AON_C_KOUT0X_SIMO_PRI_TRIG_Pos                                                                                   5U
+#define AON_C_KOUT0X_SIMO_PRI_TRIG_Msk                                                                                   (0x1UL << AON_C_KOUT0X_SIMO_PRI_TRIG_Pos)
+
+#define AON_C_KOUT0X_SIMO_MINOFFOK_Pos                                                                                   6U
+#define AON_C_KOUT0X_SIMO_MINOFFOK_Msk                                                                                   (0x1UL << AON_C_KOUT0X_SIMO_MINOFFOK_Pos)
+
+#define AON_C_KOUT0X_SIMO_ENTON_Pos                                                                                      7U
+#define AON_C_KOUT0X_SIMO_ENTON_Msk                                                                                      (0x1UL << AON_C_KOUT0X_SIMO_ENTON_Pos)
+
+#define AON_C_KOUT0X_SIMO_ENTON1_Pos                                                                                     8U
+#define AON_C_KOUT0X_SIMO_ENTON1_Msk                                                                                     (0x1UL << AON_C_KOUT0X_SIMO_ENTON1_Pos)
+
+#define AON_C_KOUT0X_SIMO_OCCUPY_OR_Pos                                                                                  9U
+#define AON_C_KOUT0X_SIMO_OCCUPY_OR_Msk                                                                                  (0x1UL << AON_C_KOUT0X_SIMO_OCCUPY_OR_Pos)
+
+#define AON_C_KOUT0X_SIMO_PWMTONU1_0_Pos                                                                                 10U
+#define AON_C_KOUT0X_SIMO_PWMTONU1_0_Msk                                                                                 (0x1UL << AON_C_KOUT0X_SIMO_PWMTONU1_0_Pos)
+
+#define AON_C_KOUT0X_SIMO_PWMTONL2_0_Pos                                                                                 11U
+#define AON_C_KOUT0X_SIMO_PWMTONL2_0_Msk                                                                                 (0x1UL << AON_C_KOUT0X_SIMO_PWMTONL2_0_Pos)
+
+#define AON_C_KOUT0X_SIMO_HYS_BUCK_AC_Pos                                                                                12U
+#define AON_C_KOUT0X_SIMO_HYS_BUCK_AC_Msk                                                                                (0x1UL << AON_C_KOUT0X_SIMO_HYS_BUCK_AC_Pos)
+
+#define AON_C_KOUT0X_SIMO_HYS_BST_AC_Pos                                                                                 13U
+#define AON_C_KOUT0X_SIMO_HYS_BST_AC_Msk                                                                                 (0x1UL << AON_C_KOUT0X_SIMO_HYS_BST_AC_Pos)
+
+#define AON_C_KOUT0X_SIMO_CMP_BUCK_DC_OUT_Pos                                                                            14U
+#define AON_C_KOUT0X_SIMO_CMP_BUCK_DC_OUT_Msk                                                                            (0x1UL << AON_C_KOUT0X_SIMO_CMP_BUCK_DC_OUT_Pos)
+
+#define AON_C_KOUT0X_SIMO_CMP_BST_DC_OUT_Pos                                                                             15U
+#define AON_C_KOUT0X_SIMO_CMP_BST_DC_OUT_Msk                                                                             (0x1UL << AON_C_KOUT0X_SIMO_CMP_BST_DC_OUT_Pos)
+
+#define AON_C_KOUT0X_SIMO_ENPOST_D_Pos                                                                                   16U
+#define AON_C_KOUT0X_SIMO_ENPOST_D_Msk                                                                                   (0x1UL << AON_C_KOUT0X_SIMO_ENPOST_D_Pos)
+
+#define AON_C_KOUT0X_SIMO_ENPOST_Pos                                                                                     17U
+#define AON_C_KOUT0X_SIMO_ENPOST_Msk                                                                                     (0x1UL << AON_C_KOUT0X_SIMO_ENPOST_Pos)
+
+#define AON_C_KOUT0X_SIMO_VOUT2_ZCPOR_Pos                                                                                18U
+#define AON_C_KOUT0X_SIMO_VOUT2_ZCPOR_Msk                                                                                (0x1UL << AON_C_KOUT0X_SIMO_VOUT2_ZCPOR_Pos)
+
+#define AON_C_KOUT0X_SIMO_PORB_VOUTT1_Pos                                                                                19U
+#define AON_C_KOUT0X_SIMO_PORB_VOUTT1_Msk                                                                                (0x1UL << AON_C_KOUT0X_SIMO_PORB_VOUTT1_Pos)
+
+#define AON_C_KOUT0X_SIMO_SEL_A_I_Pos                                                                                    20U
+#define AON_C_KOUT0X_SIMO_SEL_A_I_Msk                                                                                    (0x1UL << AON_C_KOUT0X_SIMO_SEL_A_I_Pos)
+
+#define AON_C_KOUT0X_SIMO_CCM_NEED_Pos                                                                                   21U
+#define AON_C_KOUT0X_SIMO_CCM_NEED_Msk                                                                                   (0x1UL << AON_C_KOUT0X_SIMO_CCM_NEED_Pos)
+
+#define AON_C_KOUT0X_SIMO_ENLPM_SYNC_Pos                                                                                 22U
+#define AON_C_KOUT0X_SIMO_ENLPM_SYNC_Msk                                                                                 (0x1UL << AON_C_KOUT0X_SIMO_ENLPM_SYNC_Pos)
+
+#define AON_C_KOUT0X_SIMO_DRV1_EN_NCP_Pos                                                                                23U
+#define AON_C_KOUT0X_SIMO_DRV1_EN_NCP_Msk                                                                                (0x1UL << AON_C_KOUT0X_SIMO_DRV1_EN_NCP_Pos)
+
+#define AON_C_KOUT0X_SIMO_ENTON2_UG2_Pos                                                                                 24U
+#define AON_C_KOUT0X_SIMO_ENTON2_UG2_Msk                                                                                 (0x1UL << AON_C_KOUT0X_SIMO_ENTON2_UG2_Pos)
+
+#define AON_C_KOUT0X_SIMO_POWTONL2_Pos                                                                                   25U
+#define AON_C_KOUT0X_SIMO_POWTONL2_Msk                                                                                   (0x1UL << AON_C_KOUT0X_SIMO_POWTONL2_Pos)
+
+#define AON_C_KOUT0X_SIMO_ENLG1_Pos                                                                                      26U
+#define AON_C_KOUT0X_SIMO_ENLG1_Msk                                                                                      (0x1UL << AON_C_KOUT0X_SIMO_ENLG1_Pos)
+
+#define AON_C_KOUT0X_SIMO_POWTONU1_Pos                                                                                   27U
+#define AON_C_KOUT0X_SIMO_POWTONU1_Msk                                                                                   (0x1UL << AON_C_KOUT0X_SIMO_POWTONU1_Pos)
+
+#define AON_C_KOUT0X_SIMO_IBTHR_RDY_Pos                                                                                  28U
+#define AON_C_KOUT0X_SIMO_IBTHR_RDY_Msk                                                                                  (0x1UL << AON_C_KOUT0X_SIMO_IBTHR_RDY_Pos)
+
+#define AON_C_KOUT0X_SIMO_UABIAS_RDY2_Pos                                                                                29U
+#define AON_C_KOUT0X_SIMO_UABIAS_RDY2_Msk                                                                                (0x1UL << AON_C_KOUT0X_SIMO_UABIAS_RDY2_Pos)
+
+#define AON_C_KOUT0X_SIMO_UABIAS_RDY_Pos                                                                                 30U
+#define AON_C_KOUT0X_SIMO_UABIAS_RDY_Msk                                                                                 (0x1UL << AON_C_KOUT0X_SIMO_UABIAS_RDY_Pos)
+
+#define AON_C_KOUT0X_SIMO_ENUABIAS_Pos                                                                                   31U
+#define AON_C_KOUT0X_SIMO_ENUABIAS_Msk                                                                                   (0x1UL << AON_C_KOUT0X_SIMO_ENUABIAS_Pos)
+
+/* 0x6A8    0x4000_06a8
+    0       R       LX_DET1                                                     1'b0
+    7:1     R       ZCDQ1                                                       7'b0000000
+    8       R       ZCD_SET                                                     1'b0
+    9       R       ENZCK                                                       1'b0
+    10      R       ENZC_D                                                      1'b0
+    11      R       ENPCCM                                                      1'b0
+    12      R       ZCK_DLY3                                                    1'b0
+    13      R       ZCK_DLY2                                                    1'b0
+    14      R       ZCK_DLY1                                                    1'b0
+    15      R       ZC_LCH                                                      1'b0
+    16      R       LX_DET345                                                   1'b0
+    23:17   R       ZCDQ345                                                     7'b0000000
+    24      R       LX_DET2                                                     1'b0
+    31:25   R       ZCDQ2                                                       7'b0000000
+ */
+typedef union _AON_C_KOUT1X_SIMO_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t LX_DET1: 1;
+        uint32_t ZCDQ1: 7;
+        uint32_t ZCD_SET: 1;
+        uint32_t ENZCK: 1;
+        uint32_t ENZC_D: 1;
+        uint32_t ENPCCM: 1;
+        uint32_t ZCK_DLY3: 1;
+        uint32_t ZCK_DLY2: 1;
+        uint32_t ZCK_DLY1: 1;
+        uint32_t ZC_LCH: 1;
+        uint32_t LX_DET345: 1;
+        uint32_t ZCDQ345: 7;
+        uint32_t LX_DET2: 1;
+        uint32_t ZCDQ2: 7;
+    };
+} AON_C_KOUT1X_SIMO_TYPE;
+
+/*0x4000_06a8 AON_C_KOUT1X_SIMO*/
+#define AON_C_KOUT1X_SIMO_LX_DET1_Pos                                                                                    0U
+#define AON_C_KOUT1X_SIMO_LX_DET1_Msk                                                                                    (0x1UL << AON_C_KOUT1X_SIMO_LX_DET1_Pos)
+
+#define AON_C_KOUT1X_SIMO_ZCDQ1_Pos                                                                                      1U
+#define AON_C_KOUT1X_SIMO_ZCDQ1_Msk                                                                                      (0x7FUL << AON_C_KOUT1X_SIMO_ZCDQ1_Pos)
+
+#define AON_C_KOUT1X_SIMO_ZCD_SET_Pos                                                                                    8U
+#define AON_C_KOUT1X_SIMO_ZCD_SET_Msk                                                                                    (0x1UL << AON_C_KOUT1X_SIMO_ZCD_SET_Pos)
+
+#define AON_C_KOUT1X_SIMO_ENZCK_Pos                                                                                      9U
+#define AON_C_KOUT1X_SIMO_ENZCK_Msk                                                                                      (0x1UL << AON_C_KOUT1X_SIMO_ENZCK_Pos)
+
+#define AON_C_KOUT1X_SIMO_ENZC_D_Pos                                                                                     10U
+#define AON_C_KOUT1X_SIMO_ENZC_D_Msk                                                                                     (0x1UL << AON_C_KOUT1X_SIMO_ENZC_D_Pos)
+
+#define AON_C_KOUT1X_SIMO_ENPCCM_Pos                                                                                     11U
+#define AON_C_KOUT1X_SIMO_ENPCCM_Msk                                                                                     (0x1UL << AON_C_KOUT1X_SIMO_ENPCCM_Pos)
+
+#define AON_C_KOUT1X_SIMO_ZCK_DLY3_Pos                                                                                   12U
+#define AON_C_KOUT1X_SIMO_ZCK_DLY3_Msk                                                                                   (0x1UL << AON_C_KOUT1X_SIMO_ZCK_DLY3_Pos)
+
+#define AON_C_KOUT1X_SIMO_ZCK_DLY2_Pos                                                                                   13U
+#define AON_C_KOUT1X_SIMO_ZCK_DLY2_Msk                                                                                   (0x1UL << AON_C_KOUT1X_SIMO_ZCK_DLY2_Pos)
+
+#define AON_C_KOUT1X_SIMO_ZCK_DLY1_Pos                                                                                   14U
+#define AON_C_KOUT1X_SIMO_ZCK_DLY1_Msk                                                                                   (0x1UL << AON_C_KOUT1X_SIMO_ZCK_DLY1_Pos)
+
+#define AON_C_KOUT1X_SIMO_ZC_LCH_Pos                                                                                     15U
+#define AON_C_KOUT1X_SIMO_ZC_LCH_Msk                                                                                     (0x1UL << AON_C_KOUT1X_SIMO_ZC_LCH_Pos)
+
+#define AON_C_KOUT1X_SIMO_LX_DET345_Pos                                                                                  16U
+#define AON_C_KOUT1X_SIMO_LX_DET345_Msk                                                                                  (0x1UL << AON_C_KOUT1X_SIMO_LX_DET345_Pos)
+
+#define AON_C_KOUT1X_SIMO_ZCDQ345_Pos                                                                                    17U
+#define AON_C_KOUT1X_SIMO_ZCDQ345_Msk                                                                                    (0x7FUL << AON_C_KOUT1X_SIMO_ZCDQ345_Pos)
+
+#define AON_C_KOUT1X_SIMO_LX_DET2_Pos                                                                                    24U
+#define AON_C_KOUT1X_SIMO_LX_DET2_Msk                                                                                    (0x1UL << AON_C_KOUT1X_SIMO_LX_DET2_Pos)
+
+#define AON_C_KOUT1X_SIMO_ZCDQ2_Pos                                                                                      25U
+#define AON_C_KOUT1X_SIMO_ZCDQ2_Msk                                                                                      (0x7FUL << AON_C_KOUT1X_SIMO_ZCDQ2_Pos)
+
+/* 0x6AC    0x4000_06ac
+    2:0     R       CKOUT4X_DMY                                                 3'b000
+    3       R       LG2_S_OFF                                                   1'b0
+    4       R       U2_S                                                        1'b0
+    5       R       LG1_S_OFF                                                   1'b0
+    6       R       UG1_S_OFF                                                   1'b0
+    7       R       L2                                                          1'b0
+    8       R       U2                                                          1'b0
+    9       R       L1                                                          1'b0
+    10      R       U1                                                          1'b0
+    15:11   R       CMP                                                         5'b00000
+    19:16   R       CKOUT5X_DMY                                                 4'b0000
+    20      R       TM_BUCK_DC                                                  1'b0
+    21      R       TM_BST_DC                                                   1'b0
+    22      R       OPOR_LD_LPM                                                 1'b0
+    23      R       ENPOST_F_SYNC                                               1'b0
+    24      R       ENPCCM_LV2                                                  1'b0
+    25      R       BUCK_DET_H                                                  1'b0
+    26      R       BST_DET_H                                                   1'b0
+    27      R       ENZC                                                        1'b0
+    28      R       IPTAT_OK_D_SIMO                                             1'b0
+    29      R       IPTAT_OK_SIMO                                               1'b0
+    30      R       EN_D                                                        1'b0
+    31      R       EN                                                          1'b0
+ */
+typedef union _AON_C_KOUT2X_SIMO_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t CKOUT4X_DMY: 3;
+        uint32_t LG2_S_OFF: 1;
+        uint32_t U2_S: 1;
+        uint32_t LG1_S_OFF: 1;
+        uint32_t UG1_S_OFF: 1;
+        uint32_t L2: 1;
+        uint32_t U2: 1;
+        uint32_t L1: 1;
+        uint32_t U1: 1;
+        uint32_t CMP: 5;
+        uint32_t CKOUT5X_DMY: 4;
+        uint32_t TM_BUCK_DC: 1;
+        uint32_t TM_BST_DC: 1;
+        uint32_t OPOR_LD_LPM: 1;
+        uint32_t ENPOST_F_SYNC: 1;
+        uint32_t ENPCCM_LV2: 1;
+        uint32_t BUCK_DET_H: 1;
+        uint32_t BST_DET_H: 1;
+        uint32_t ENZC: 1;
+        uint32_t IPTAT_OK_D_SIMO: 1;
+        uint32_t IPTAT_OK_SIMO: 1;
+        uint32_t EN_D: 1;
+        uint32_t EN: 1;
+    };
+} AON_C_KOUT2X_SIMO_TYPE;
+
+/*0x4000_06ac AON_C_KOUT2X_SIMO*/
+#define AON_C_KOUT2X_SIMO_CKOUT4X_DMY_Pos                                                                                0U
+#define AON_C_KOUT2X_SIMO_CKOUT4X_DMY_Msk                                                                                (0x7UL << AON_C_KOUT2X_SIMO_CKOUT4X_DMY_Pos)
+
+#define AON_C_KOUT2X_SIMO_LG2_S_OFF_Pos                                                                                  3U
+#define AON_C_KOUT2X_SIMO_LG2_S_OFF_Msk                                                                                  (0x1UL << AON_C_KOUT2X_SIMO_LG2_S_OFF_Pos)
+
+#define AON_C_KOUT2X_SIMO_U2_S_Pos                                                                                       4U
+#define AON_C_KOUT2X_SIMO_U2_S_Msk                                                                                       (0x1UL << AON_C_KOUT2X_SIMO_U2_S_Pos)
+
+#define AON_C_KOUT2X_SIMO_LG1_S_OFF_Pos                                                                                  5U
+#define AON_C_KOUT2X_SIMO_LG1_S_OFF_Msk                                                                                  (0x1UL << AON_C_KOUT2X_SIMO_LG1_S_OFF_Pos)
+
+#define AON_C_KOUT2X_SIMO_UG1_S_OFF_Pos                                                                                  6U
+#define AON_C_KOUT2X_SIMO_UG1_S_OFF_Msk                                                                                  (0x1UL << AON_C_KOUT2X_SIMO_UG1_S_OFF_Pos)
+
+#define AON_C_KOUT2X_SIMO_L2_Pos                                                                                         7U
+#define AON_C_KOUT2X_SIMO_L2_Msk                                                                                         (0x1UL << AON_C_KOUT2X_SIMO_L2_Pos)
+
+#define AON_C_KOUT2X_SIMO_U2_Pos                                                                                         8U
+#define AON_C_KOUT2X_SIMO_U2_Msk                                                                                         (0x1UL << AON_C_KOUT2X_SIMO_U2_Pos)
+
+#define AON_C_KOUT2X_SIMO_L1_Pos                                                                                         9U
+#define AON_C_KOUT2X_SIMO_L1_Msk                                                                                         (0x1UL << AON_C_KOUT2X_SIMO_L1_Pos)
+
+#define AON_C_KOUT2X_SIMO_U1_Pos                                                                                         10U
+#define AON_C_KOUT2X_SIMO_U1_Msk                                                                                         (0x1UL << AON_C_KOUT2X_SIMO_U1_Pos)
+
+#define AON_C_KOUT2X_SIMO_CMP_Pos                                                                                        11U
+#define AON_C_KOUT2X_SIMO_CMP_Msk                                                                                        (0x1FUL << AON_C_KOUT2X_SIMO_CMP_Pos)
+
+#define AON_C_KOUT2X_SIMO_CKOUT5X_DMY_Pos                                                                                16U
+#define AON_C_KOUT2X_SIMO_CKOUT5X_DMY_Msk                                                                                (0xFUL << AON_C_KOUT2X_SIMO_CKOUT5X_DMY_Pos)
+
+#define AON_C_KOUT2X_SIMO_TM_BUCK_DC_Pos                                                                                 20U
+#define AON_C_KOUT2X_SIMO_TM_BUCK_DC_Msk                                                                                 (0x1UL << AON_C_KOUT2X_SIMO_TM_BUCK_DC_Pos)
+
+#define AON_C_KOUT2X_SIMO_TM_BST_DC_Pos                                                                                  21U
+#define AON_C_KOUT2X_SIMO_TM_BST_DC_Msk                                                                                  (0x1UL << AON_C_KOUT2X_SIMO_TM_BST_DC_Pos)
+
+#define AON_C_KOUT2X_SIMO_OPOR_LD_LPM_Pos                                                                                22U
+#define AON_C_KOUT2X_SIMO_OPOR_LD_LPM_Msk                                                                                (0x1UL << AON_C_KOUT2X_SIMO_OPOR_LD_LPM_Pos)
+
+#define AON_C_KOUT2X_SIMO_ENPOST_F_SYNC_Pos                                                                              23U
+#define AON_C_KOUT2X_SIMO_ENPOST_F_SYNC_Msk                                                                              (0x1UL << AON_C_KOUT2X_SIMO_ENPOST_F_SYNC_Pos)
+
+#define AON_C_KOUT2X_SIMO_ENPCCM_LV2_Pos                                                                                 24U
+#define AON_C_KOUT2X_SIMO_ENPCCM_LV2_Msk                                                                                 (0x1UL << AON_C_KOUT2X_SIMO_ENPCCM_LV2_Pos)
+
+#define AON_C_KOUT2X_SIMO_BUCK_DET_H_Pos                                                                                 25U
+#define AON_C_KOUT2X_SIMO_BUCK_DET_H_Msk                                                                                 (0x1UL << AON_C_KOUT2X_SIMO_BUCK_DET_H_Pos)
+
+#define AON_C_KOUT2X_SIMO_BST_DET_H_Pos                                                                                  26U
+#define AON_C_KOUT2X_SIMO_BST_DET_H_Msk                                                                                  (0x1UL << AON_C_KOUT2X_SIMO_BST_DET_H_Pos)
+
+#define AON_C_KOUT2X_SIMO_ENZC_Pos                                                                                       27U
+#define AON_C_KOUT2X_SIMO_ENZC_Msk                                                                                       (0x1UL << AON_C_KOUT2X_SIMO_ENZC_Pos)
+
+#define AON_C_KOUT2X_SIMO_IPTAT_OK_D_SIMO_Pos                                                                            28U
+#define AON_C_KOUT2X_SIMO_IPTAT_OK_D_SIMO_Msk                                                                            (0x1UL << AON_C_KOUT2X_SIMO_IPTAT_OK_D_SIMO_Pos)
+
+#define AON_C_KOUT2X_SIMO_IPTAT_OK_SIMO_Pos                                                                              29U
+#define AON_C_KOUT2X_SIMO_IPTAT_OK_SIMO_Msk                                                                              (0x1UL << AON_C_KOUT2X_SIMO_IPTAT_OK_SIMO_Pos)
+
+#define AON_C_KOUT2X_SIMO_EN_D_Pos                                                                                       30U
+#define AON_C_KOUT2X_SIMO_EN_D_Msk                                                                                       (0x1UL << AON_C_KOUT2X_SIMO_EN_D_Pos)
+
+#define AON_C_KOUT2X_SIMO_EN_Pos                                                                                         31U
+#define AON_C_KOUT2X_SIMO_EN_Msk                                                                                         (0x1UL << AON_C_KOUT2X_SIMO_EN_Pos)
+
+/* 0x6D4    0x4000_06d4
+    0       R/W     LDO_POW_BIAS_LDOANA                                         1'b0
+    1       R/W     LDO_ENPC_LDOANA                                             1'b0
+    2       R/W     LDO_POW_LDOANA                                              1'b0
+    4:3     R/W     EN_LDO_VREF_SEL                                             2'b00
+    5       R/W     EN_PC_USE_LARGE                                             1'b0
+    6       R/W     LDO_POW_LDOANA_FB                                           1'b1
+    7       R/W     LDO_R_HALF                                                  1'b1
+    8       R/W     LDO_TOFS_LDOANA                                             1'b1
+    13:9    R/W     LDO_TUNE_LDOANA                                             5'b10001
+    14      R/W     LDO_ENB_DMYL_50U_LDOANA                                     1'b1
+    15      R/W     LDO_ENB_DMYL_200U_LDOANA                                    1'b1
+    18:16   R       POS_VDDANA_NO_USE_LSB                                       3'b000
+    21:19   R       POS_VDDANA_VREF                                             3'b000
+    23:22   R       POS_VDDANA_NO_USE_MSB                                       2'b00
+    24      R       EN_LDO_R3S                                                  1'b1
+    25      R/W     EN_LDO_R2S                                                  1'b1
+    28:26   R/W     EN_LDO_ISET                                                 3'b100
+    29      R/W     EN_BIG_R                                                    1'b1
+    30      R/W     EN_FAST_TRNAS                                               1'b1
+    31      R       DUMMY                                                       1'b0
+ */
+typedef union _AON_REG_LDO_ANA_REG0X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t LDO_POW_BIAS_LDOANA: 1;
+        uint32_t LDO_ENPC_LDOANA: 1;
+        uint32_t LDO_POW_LDOANA: 1;
+        uint32_t EN_LDO_VREF_SEL: 2;
+        uint32_t EN_PC_USE_LARGE: 1;
+        uint32_t LDO_POW_LDOANA_FB: 1;
+        uint32_t LDO_R_HALF: 1;
+        uint32_t LDO_TOFS_LDOANA: 1;
+        uint32_t LDO_TUNE_LDOANA: 5;
+        uint32_t LDO_ENB_DMYL_50U_LDOANA: 1;
+        uint32_t LDO_ENB_DMYL_200U_LDOANA: 1;
+        uint32_t POS_VDDANA_NO_USE_LSB: 3;
+        uint32_t POS_VDDANA_VREF: 3;
+        uint32_t POS_VDDANA_NO_USE_MSB: 2;
+        uint32_t EN_LDO_R3S: 1;
+        uint32_t EN_LDO_R2S: 1;
+        uint32_t EN_LDO_ISET: 3;
+        uint32_t EN_BIG_R: 1;
+        uint32_t EN_FAST_TRNAS: 1;
+        uint32_t DUMMY: 1;
+    };
+} AON_REG_LDO_ANA_REG0X_TYPE;
+
+/*0x4000_06d4 AON_REG_LDO_ANA_REG0X*/
+#define AON_REG_LDO_ANA_REG0X_LDO_POW_BIAS_LDOANA_Pos                                                                    0U
+#define AON_REG_LDO_ANA_REG0X_LDO_POW_BIAS_LDOANA_Msk                                                                    (0x1UL << AON_REG_LDO_ANA_REG0X_LDO_POW_BIAS_LDOANA_Pos)
+
+#define AON_REG_LDO_ANA_REG0X_LDO_ENPC_LDOANA_Pos                                                                        1U
+#define AON_REG_LDO_ANA_REG0X_LDO_ENPC_LDOANA_Msk                                                                        (0x1UL << AON_REG_LDO_ANA_REG0X_LDO_ENPC_LDOANA_Pos)
+
+#define AON_REG_LDO_ANA_REG0X_LDO_POW_LDOANA_Pos                                                                         2U
+#define AON_REG_LDO_ANA_REG0X_LDO_POW_LDOANA_Msk                                                                         (0x1UL << AON_REG_LDO_ANA_REG0X_LDO_POW_LDOANA_Pos)
+
+#define AON_REG_LDO_ANA_REG0X_EN_LDO_VREF_SEL_Pos                                                                        3U
+#define AON_REG_LDO_ANA_REG0X_EN_LDO_VREF_SEL_Msk                                                                        (0x3UL << AON_REG_LDO_ANA_REG0X_EN_LDO_VREF_SEL_Pos)
+
+#define AON_REG_LDO_ANA_REG0X_EN_PC_USE_LARGE_Pos                                                                        5U
+#define AON_REG_LDO_ANA_REG0X_EN_PC_USE_LARGE_Msk                                                                        (0x1UL << AON_REG_LDO_ANA_REG0X_EN_PC_USE_LARGE_Pos)
+
+#define AON_REG_LDO_ANA_REG0X_LDO_POW_LDOANA_FB_Pos                                                                      6U
+#define AON_REG_LDO_ANA_REG0X_LDO_POW_LDOANA_FB_Msk                                                                      (0x1UL << AON_REG_LDO_ANA_REG0X_LDO_POW_LDOANA_FB_Pos)
+
+#define AON_REG_LDO_ANA_REG0X_LDO_R_HALF_Pos                                                                             7U
+#define AON_REG_LDO_ANA_REG0X_LDO_R_HALF_Msk                                                                             (0x1UL << AON_REG_LDO_ANA_REG0X_LDO_R_HALF_Pos)
+
+#define AON_REG_LDO_ANA_REG0X_LDO_TOFS_LDOANA_Pos                                                                        8U
+#define AON_REG_LDO_ANA_REG0X_LDO_TOFS_LDOANA_Msk                                                                        (0x1UL << AON_REG_LDO_ANA_REG0X_LDO_TOFS_LDOANA_Pos)
+
+#define AON_REG_LDO_ANA_REG0X_LDO_TUNE_LDOANA_Pos                                                                        9U
+#define AON_REG_LDO_ANA_REG0X_LDO_TUNE_LDOANA_Msk                                                                        (0x1FUL << AON_REG_LDO_ANA_REG0X_LDO_TUNE_LDOANA_Pos)
+
+#define AON_REG_LDO_ANA_REG0X_LDO_ENB_DMYL_50U_LDOANA_Pos                                                                14U
+#define AON_REG_LDO_ANA_REG0X_LDO_ENB_DMYL_50U_LDOANA_Msk                                                                (0x1UL << AON_REG_LDO_ANA_REG0X_LDO_ENB_DMYL_50U_LDOANA_Pos)
+
+#define AON_REG_LDO_ANA_REG0X_LDO_ENB_DMYL_200U_LDOANA_Pos                                                               15U
+#define AON_REG_LDO_ANA_REG0X_LDO_ENB_DMYL_200U_LDOANA_Msk                                                               (0x1UL << AON_REG_LDO_ANA_REG0X_LDO_ENB_DMYL_200U_LDOANA_Pos)
+
+#define AON_REG_LDO_ANA_REG0X_POS_VDDANA_NO_USE_LSB_Pos                                                                  16U
+#define AON_REG_LDO_ANA_REG0X_POS_VDDANA_NO_USE_LSB_Msk                                                                  (0x7UL << AON_REG_LDO_ANA_REG0X_POS_VDDANA_NO_USE_LSB_Pos)
+
+#define AON_REG_LDO_ANA_REG0X_POS_VDDANA_VREF_Pos                                                                        19U
+#define AON_REG_LDO_ANA_REG0X_POS_VDDANA_VREF_Msk                                                                        (0x7UL << AON_REG_LDO_ANA_REG0X_POS_VDDANA_VREF_Pos)
+
+#define AON_REG_LDO_ANA_REG0X_POS_VDDANA_NO_USE_MSB_Pos                                                                  22U
+#define AON_REG_LDO_ANA_REG0X_POS_VDDANA_NO_USE_MSB_Msk                                                                  (0x3UL << AON_REG_LDO_ANA_REG0X_POS_VDDANA_NO_USE_MSB_Pos)
+
+#define AON_REG_LDO_ANA_REG0X_EN_LDO_R3S_Pos                                                                             24U
+#define AON_REG_LDO_ANA_REG0X_EN_LDO_R3S_Msk                                                                             (0x1UL << AON_REG_LDO_ANA_REG0X_EN_LDO_R3S_Pos)
+
+#define AON_REG_LDO_ANA_REG0X_EN_LDO_R2S_Pos                                                                             25U
+#define AON_REG_LDO_ANA_REG0X_EN_LDO_R2S_Msk                                                                             (0x1UL << AON_REG_LDO_ANA_REG0X_EN_LDO_R2S_Pos)
+
+#define AON_REG_LDO_ANA_REG0X_EN_LDO_ISET_Pos                                                                            26U
+#define AON_REG_LDO_ANA_REG0X_EN_LDO_ISET_Msk                                                                            (0x7UL << AON_REG_LDO_ANA_REG0X_EN_LDO_ISET_Pos)
+
+#define AON_REG_LDO_ANA_REG0X_EN_BIG_R_Pos                                                                               29U
+#define AON_REG_LDO_ANA_REG0X_EN_BIG_R_Msk                                                                               (0x1UL << AON_REG_LDO_ANA_REG0X_EN_BIG_R_Pos)
+
+#define AON_REG_LDO_ANA_REG0X_EN_FAST_TRNAS_Pos                                                                          30U
+#define AON_REG_LDO_ANA_REG0X_EN_FAST_TRNAS_Msk                                                                          (0x1UL << AON_REG_LDO_ANA_REG0X_EN_FAST_TRNAS_Pos)
+
+#define AON_REG_LDO_ANA_REG0X_DUMMY_Pos                                                                                  31U
+#define AON_REG_LDO_ANA_REG0X_DUMMY_Msk                                                                                  (0x1UL << AON_REG_LDO_ANA_REG0X_DUMMY_Pos)
+
+/* 0x6E4    0x4000_06e4
+    0       R/W     LDO_POW_BIAS_LDOPA                                          1'b0
+    1       R/W     LDO_ENPC_LDOPA                                              1'b0
+    2       R/W     LDO_POW_LDOPA                                               1'b0
+    4:3     R/W     DUMMY2                                                      2'b00
+    5       R/W     EN_PC_USE_LARGE                                             1'b0
+    6       R/W     LDO_POW_LDOPA_FB                                            1'b1
+    7       R/W     LDO_R_HALF                                                  1'b1
+    13:8    R/W     LDO_TUNE_LDOPA                                              6'b010000
+    14      R/W     LDO_ENB_DMYL_50U_LDOPA                                      1'b1
+    15      R/W     LDO_ENB_DMYL_200U_LDOPA                                     1'b1
+    18:16   R       POS_VDDPA_NO_USE_LSB                                        3'b000
+    21:19   R       POS_VDDPA_VREF                                              3'b000
+    23:22   R       POS_VDDPA_NO_USE_MSB                                        2'b00
+    31:24   R       DUMMY                                                       8'b00000000
+ */
+typedef union _AON_REG_LDO_PA_REG0X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t LDO_POW_BIAS_LDOPA: 1;
+        uint32_t LDO_ENPC_LDOPA: 1;
+        uint32_t LDO_POW_LDOPA: 1;
+        uint32_t DUMMY2: 2;
+        uint32_t EN_PC_USE_LARGE: 1;
+        uint32_t LDO_POW_LDOPA_FB: 1;
+        uint32_t LDO_R_HALF: 1;
+        uint32_t LDO_TUNE_LDOPA: 6;
+        uint32_t LDO_ENB_DMYL_50U_LDOPA: 1;
+        uint32_t LDO_ENB_DMYL_200U_LDOPA: 1;
+        uint32_t POS_VDDPA_NO_USE_LSB: 3;
+        uint32_t POS_VDDPA_VREF: 3;
+        uint32_t POS_VDDPA_NO_USE_MSB: 2;
+        uint32_t DUMMY: 8;
+    };
+} AON_REG_LDO_PA_REG0X_TYPE;
+
+/*0x4000_06e4 AON_REG_LDO_PA_REG0X*/
+#define AON_REG_LDO_PA_REG0X_LDO_POW_BIAS_LDOPA_Pos                                                                      0U
+#define AON_REG_LDO_PA_REG0X_LDO_POW_BIAS_LDOPA_Msk                                                                      (0x1UL << AON_REG_LDO_PA_REG0X_LDO_POW_BIAS_LDOPA_Pos)
+
+#define AON_REG_LDO_PA_REG0X_LDO_ENPC_LDOPA_Pos                                                                          1U
+#define AON_REG_LDO_PA_REG0X_LDO_ENPC_LDOPA_Msk                                                                          (0x1UL << AON_REG_LDO_PA_REG0X_LDO_ENPC_LDOPA_Pos)
+
+#define AON_REG_LDO_PA_REG0X_LDO_POW_LDOPA_Pos                                                                           2U
+#define AON_REG_LDO_PA_REG0X_LDO_POW_LDOPA_Msk                                                                           (0x1UL << AON_REG_LDO_PA_REG0X_LDO_POW_LDOPA_Pos)
+
+#define AON_REG_LDO_PA_REG0X_DUMMY2_Pos                                                                                  3U
+#define AON_REG_LDO_PA_REG0X_DUMMY2_Msk                                                                                  (0x3UL << AON_REG_LDO_PA_REG0X_DUMMY2_Pos)
+
+#define AON_REG_LDO_PA_REG0X_EN_PC_USE_LARGE_Pos                                                                         5U
+#define AON_REG_LDO_PA_REG0X_EN_PC_USE_LARGE_Msk                                                                         (0x1UL << AON_REG_LDO_PA_REG0X_EN_PC_USE_LARGE_Pos)
+
+#define AON_REG_LDO_PA_REG0X_LDO_POW_LDOPA_FB_Pos                                                                        6U
+#define AON_REG_LDO_PA_REG0X_LDO_POW_LDOPA_FB_Msk                                                                        (0x1UL << AON_REG_LDO_PA_REG0X_LDO_POW_LDOPA_FB_Pos)
+
+#define AON_REG_LDO_PA_REG0X_LDO_R_HALF_Pos                                                                              7U
+#define AON_REG_LDO_PA_REG0X_LDO_R_HALF_Msk                                                                              (0x1UL << AON_REG_LDO_PA_REG0X_LDO_R_HALF_Pos)
+
+#define AON_REG_LDO_PA_REG0X_LDO_TUNE_LDOPA_Pos                                                                          8U
+#define AON_REG_LDO_PA_REG0X_LDO_TUNE_LDOPA_Msk                                                                          (0x3FUL << AON_REG_LDO_PA_REG0X_LDO_TUNE_LDOPA_Pos)
+
+#define AON_REG_LDO_PA_REG0X_LDO_ENB_DMYL_50U_LDOPA_Pos                                                                  14U
+#define AON_REG_LDO_PA_REG0X_LDO_ENB_DMYL_50U_LDOPA_Msk                                                                  (0x1UL << AON_REG_LDO_PA_REG0X_LDO_ENB_DMYL_50U_LDOPA_Pos)
+
+#define AON_REG_LDO_PA_REG0X_LDO_ENB_DMYL_200U_LDOPA_Pos                                                                 15U
+#define AON_REG_LDO_PA_REG0X_LDO_ENB_DMYL_200U_LDOPA_Msk                                                                 (0x1UL << AON_REG_LDO_PA_REG0X_LDO_ENB_DMYL_200U_LDOPA_Pos)
+
+#define AON_REG_LDO_PA_REG0X_POS_VDDPA_NO_USE_LSB_Pos                                                                    16U
+#define AON_REG_LDO_PA_REG0X_POS_VDDPA_NO_USE_LSB_Msk                                                                    (0x7UL << AON_REG_LDO_PA_REG0X_POS_VDDPA_NO_USE_LSB_Pos)
+
+#define AON_REG_LDO_PA_REG0X_POS_VDDPA_VREF_Pos                                                                          19U
+#define AON_REG_LDO_PA_REG0X_POS_VDDPA_VREF_Msk                                                                          (0x7UL << AON_REG_LDO_PA_REG0X_POS_VDDPA_VREF_Pos)
+
+#define AON_REG_LDO_PA_REG0X_POS_VDDPA_NO_USE_MSB_Pos                                                                    22U
+#define AON_REG_LDO_PA_REG0X_POS_VDDPA_NO_USE_MSB_Msk                                                                    (0x3UL << AON_REG_LDO_PA_REG0X_POS_VDDPA_NO_USE_MSB_Pos)
+
+#define AON_REG_LDO_PA_REG0X_DUMMY_Pos                                                                                   24U
+#define AON_REG_LDO_PA_REG0X_DUMMY_Msk                                                                                   (0xFFUL << AON_REG_LDO_PA_REG0X_DUMMY_Pos)
+
+/* 0x6F4    0x4000_06f4
+    0       R/W     PLL1_POW_PLL                                                1'b0
+    1       R/W     PLL1_REF_FREF_EDGE                                          1'b1
+    2       R/W     PLL1_POW_CPOP                                               1'b1
+    4:3     R/W     PLL1_LPF_CP_SEL                                             2'b10
+    6:5     R/W     PLL1_LPF_CS_SEL                                             2'b10
+    9:7     R/W     PLL1_LPF_RS_SEL                                             3'b011
+    10      R/W     REG0X_PLL1_DUMMY_LPF_C3_SEL                                 1'b0
+    13:11   R/W     REG0X_PLL1_DUMMY_LPF_R3_SEL                                 3'b100
+    15:14   R/W     PLL1_DAC_DN_SEL                                             2'b0
+    18:16   R/W     PLL1_KVCO_TUNE                                              3'b100
+    19      R/W     PLL1_CKO1_EN                                                1'b0
+    21:20   R/W     PLL1_DN_SEL                                                 2'b00
+    22      R/W     PLL1_WDG_ENB                                                1'b0
+    24:23   R/W     PLL1_LPF_VCTHL                                              2'b00
+    25      R/W     AGPIO_GPE                                                   1'b0
+    26      R/W     AGPIO_GPO                                                   1'b0
+    28:27   R/W     AGPIO_GPDRV                                                 2'b00
+    29      R/W     REG1X_PLL1_DUMMY0                                           1'b0
+    30      R/W     REG1X_PLL1_DUMMY1                                           1'b0
+    31      R/W     REG1X_PLL1_DUMMY2                                           1'b0
+ */
+typedef union _AON_REG0X_PLL1_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t PLL1_POW_PLL: 1;
+        uint32_t PLL1_REF_FREF_EDGE: 1;
+        uint32_t PLL1_POW_CPOP: 1;
+        uint32_t PLL1_LPF_CP_SEL: 2;
+        uint32_t PLL1_LPF_CS_SEL: 2;
+        uint32_t PLL1_LPF_RS_SEL: 3;
+        uint32_t REG0X_PLL1_DUMMY_LPF_C3_SEL: 1;
+        uint32_t REG0X_PLL1_DUMMY_LPF_R3_SEL: 3;
+        uint32_t PLL1_DAC_DN_SEL: 2;
+        uint32_t PLL1_KVCO_TUNE: 3;
+        uint32_t PLL1_CKO1_EN: 1;
+        uint32_t PLL1_DN_SEL: 2;
+        uint32_t PLL1_WDG_ENB: 1;
+        uint32_t PLL1_LPF_VCTHL: 2;
+        uint32_t AGPIO_GPE: 1;
+        uint32_t AGPIO_GPO: 1;
+        uint32_t AGPIO_GPDRV: 2;
+        uint32_t REG1X_PLL1_DUMMY0: 1;
+        uint32_t REG1X_PLL1_DUMMY1: 1;
+        uint32_t REG1X_PLL1_DUMMY2: 1;
+    };
+} AON_REG0X_PLL1_TYPE;
+
+/*0x4000_06f4 AON_REG0X_PLL1*/
+#define AON_REG0X_PLL1_PLL1_POW_PLL_Pos                                                                                  0U
+#define AON_REG0X_PLL1_PLL1_POW_PLL_Msk                                                                                  (0x1UL << AON_REG0X_PLL1_PLL1_POW_PLL_Pos)
+
+#define AON_REG0X_PLL1_PLL1_REF_FREF_EDGE_Pos                                                                            1U
+#define AON_REG0X_PLL1_PLL1_REF_FREF_EDGE_Msk                                                                            (0x1UL << AON_REG0X_PLL1_PLL1_REF_FREF_EDGE_Pos)
+
+#define AON_REG0X_PLL1_PLL1_POW_CPOP_Pos                                                                                 2U
+#define AON_REG0X_PLL1_PLL1_POW_CPOP_Msk                                                                                 (0x1UL << AON_REG0X_PLL1_PLL1_POW_CPOP_Pos)
+
+#define AON_REG0X_PLL1_PLL1_LPF_CP_SEL_Pos                                                                               3U
+#define AON_REG0X_PLL1_PLL1_LPF_CP_SEL_Msk                                                                               (0x3UL << AON_REG0X_PLL1_PLL1_LPF_CP_SEL_Pos)
+
+#define AON_REG0X_PLL1_PLL1_LPF_CS_SEL_Pos                                                                               5U
+#define AON_REG0X_PLL1_PLL1_LPF_CS_SEL_Msk                                                                               (0x3UL << AON_REG0X_PLL1_PLL1_LPF_CS_SEL_Pos)
+
+#define AON_REG0X_PLL1_PLL1_LPF_RS_SEL_Pos                                                                               7U
+#define AON_REG0X_PLL1_PLL1_LPF_RS_SEL_Msk                                                                               (0x7UL << AON_REG0X_PLL1_PLL1_LPF_RS_SEL_Pos)
+
+#define AON_REG0X_PLL1_REG0X_PLL1_DUMMY_LPF_C3_SEL_Pos                                                                   10U
+#define AON_REG0X_PLL1_REG0X_PLL1_DUMMY_LPF_C3_SEL_Msk                                                                   (0x1UL << AON_REG0X_PLL1_REG0X_PLL1_DUMMY_LPF_C3_SEL_Pos)
+
+#define AON_REG0X_PLL1_REG0X_PLL1_DUMMY_LPF_R3_SEL_Pos                                                                   11U
+#define AON_REG0X_PLL1_REG0X_PLL1_DUMMY_LPF_R3_SEL_Msk                                                                   (0x7UL << AON_REG0X_PLL1_REG0X_PLL1_DUMMY_LPF_R3_SEL_Pos)
+
+#define AON_REG0X_PLL1_PLL1_DAC_DN_SEL_Pos                                                                               14U
+#define AON_REG0X_PLL1_PLL1_DAC_DN_SEL_Msk                                                                               (0x3UL << AON_REG0X_PLL1_PLL1_DAC_DN_SEL_Pos)
+
+#define AON_REG0X_PLL1_PLL1_KVCO_TUNE_Pos                                                                                16U
+#define AON_REG0X_PLL1_PLL1_KVCO_TUNE_Msk                                                                                (0x7UL << AON_REG0X_PLL1_PLL1_KVCO_TUNE_Pos)
+
+#define AON_REG0X_PLL1_PLL1_CKO1_EN_Pos                                                                                  19U
+#define AON_REG0X_PLL1_PLL1_CKO1_EN_Msk                                                                                  (0x1UL << AON_REG0X_PLL1_PLL1_CKO1_EN_Pos)
+
+#define AON_REG0X_PLL1_PLL1_DN_SEL_Pos                                                                                   20U
+#define AON_REG0X_PLL1_PLL1_DN_SEL_Msk                                                                                   (0x3UL << AON_REG0X_PLL1_PLL1_DN_SEL_Pos)
+
+#define AON_REG0X_PLL1_PLL1_WDG_ENB_Pos                                                                                  22U
+#define AON_REG0X_PLL1_PLL1_WDG_ENB_Msk                                                                                  (0x1UL << AON_REG0X_PLL1_PLL1_WDG_ENB_Pos)
+
+#define AON_REG0X_PLL1_PLL1_LPF_VCTHL_Pos                                                                                23U
+#define AON_REG0X_PLL1_PLL1_LPF_VCTHL_Msk                                                                                (0x3UL << AON_REG0X_PLL1_PLL1_LPF_VCTHL_Pos)
+
+#define AON_REG0X_PLL1_AGPIO_GPE_Pos                                                                                     25U
+#define AON_REG0X_PLL1_AGPIO_GPE_Msk                                                                                     (0x1UL << AON_REG0X_PLL1_AGPIO_GPE_Pos)
+
+#define AON_REG0X_PLL1_AGPIO_GPO_Pos                                                                                     26U
+#define AON_REG0X_PLL1_AGPIO_GPO_Msk                                                                                     (0x1UL << AON_REG0X_PLL1_AGPIO_GPO_Pos)
+
+#define AON_REG0X_PLL1_AGPIO_GPDRV_Pos                                                                                   27U
+#define AON_REG0X_PLL1_AGPIO_GPDRV_Msk                                                                                   (0x3UL << AON_REG0X_PLL1_AGPIO_GPDRV_Pos)
+
+#define AON_REG0X_PLL1_REG1X_PLL1_DUMMY0_Pos                                                                             29U
+#define AON_REG0X_PLL1_REG1X_PLL1_DUMMY0_Msk                                                                             (0x1UL << AON_REG0X_PLL1_REG1X_PLL1_DUMMY0_Pos)
+
+#define AON_REG0X_PLL1_REG1X_PLL1_DUMMY1_Pos                                                                             30U
+#define AON_REG0X_PLL1_REG1X_PLL1_DUMMY1_Msk                                                                             (0x1UL << AON_REG0X_PLL1_REG1X_PLL1_DUMMY1_Pos)
+
+#define AON_REG0X_PLL1_REG1X_PLL1_DUMMY2_Pos                                                                             31U
+#define AON_REG0X_PLL1_REG1X_PLL1_DUMMY2_Msk                                                                             (0x1UL << AON_REG0X_PLL1_REG1X_PLL1_DUMMY2_Pos)
+
+/* 0x6F8    0x4000_06f8
+    3:0     R/W     REG2X_PLL1_DUMMY0                                           4'b0
+    4       R/W     PLL1_CK_BTADC_EN                                            1'b1
+    5       R/W     REG2X_PLL1_DUMMY1                                           1'b0
+    6       R/W     PLL1_CK_BTDAC_EN                                            1'b0
+    7       R/W     REG2X_PLL1_DUMMY2                                           1'b0
+    8       R/W     PLL1_BT_CKI_PLL_DAC_ANA_EN                                  1'b0
+    9       R/W     PLL1_BT_CKI_PLL_ADC_ANA_EN                                  1'b1
+    11:10   R/W     CKO_DBG_FREQ_SEL                                            2'b0
+    12      R/W     PLL1_TESTMODE_EN                                            1'b0
+    14:13   R/W     PLL1_TESTMODE_CKO_SEL                                       2'b00
+    15      R/W     PLL1_CK_BTADC_AND_CK_BTDAC_EN                               1'b1
+    31:16   R       RSVD                                                        16'b0
+ */
+typedef union _AON_REG2X_PLL1_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t REG2X_PLL1_DUMMY0: 4;
+        uint32_t PLL1_CK_BTADC_EN: 1;
+        uint32_t REG2X_PLL1_DUMMY1: 1;
+        uint32_t PLL1_CK_BTDAC_EN: 1;
+        uint32_t REG2X_PLL1_DUMMY2: 1;
+        uint32_t PLL1_BT_CKI_PLL_DAC_ANA_EN: 1;
+        uint32_t PLL1_BT_CKI_PLL_ADC_ANA_EN: 1;
+        uint32_t CKO_DBG_FREQ_SEL: 2;
+        uint32_t PLL1_TESTMODE_EN: 1;
+        uint32_t PLL1_TESTMODE_CKO_SEL: 2;
+        uint32_t PLL1_CK_BTADC_AND_CK_BTDAC_EN: 1;
+        uint32_t RSVD: 16;
+    };
+} AON_REG2X_PLL1_TYPE;
+
+/*0x4000_06f8 AON_REG2X_PLL1*/
+#define AON_REG2X_PLL1_REG2X_PLL1_DUMMY0_Pos                                                                             0U
+#define AON_REG2X_PLL1_REG2X_PLL1_DUMMY0_Msk                                                                             (0xFUL << AON_REG2X_PLL1_REG2X_PLL1_DUMMY0_Pos)
+
+#define AON_REG2X_PLL1_PLL1_CK_BTADC_EN_Pos                                                                              4U
+#define AON_REG2X_PLL1_PLL1_CK_BTADC_EN_Msk                                                                              (0x1UL << AON_REG2X_PLL1_PLL1_CK_BTADC_EN_Pos)
+
+#define AON_REG2X_PLL1_REG2X_PLL1_DUMMY1_Pos                                                                             5U
+#define AON_REG2X_PLL1_REG2X_PLL1_DUMMY1_Msk                                                                             (0x1UL << AON_REG2X_PLL1_REG2X_PLL1_DUMMY1_Pos)
+
+#define AON_REG2X_PLL1_PLL1_CK_BTDAC_EN_Pos                                                                              6U
+#define AON_REG2X_PLL1_PLL1_CK_BTDAC_EN_Msk                                                                              (0x1UL << AON_REG2X_PLL1_PLL1_CK_BTDAC_EN_Pos)
+
+#define AON_REG2X_PLL1_REG2X_PLL1_DUMMY2_Pos                                                                             7U
+#define AON_REG2X_PLL1_REG2X_PLL1_DUMMY2_Msk                                                                             (0x1UL << AON_REG2X_PLL1_REG2X_PLL1_DUMMY2_Pos)
+
+#define AON_REG2X_PLL1_PLL1_BT_CKI_PLL_DAC_ANA_EN_Pos                                                                    8U
+#define AON_REG2X_PLL1_PLL1_BT_CKI_PLL_DAC_ANA_EN_Msk                                                                    (0x1UL << AON_REG2X_PLL1_PLL1_BT_CKI_PLL_DAC_ANA_EN_Pos)
+
+#define AON_REG2X_PLL1_PLL1_BT_CKI_PLL_ADC_ANA_EN_Pos                                                                    9U
+#define AON_REG2X_PLL1_PLL1_BT_CKI_PLL_ADC_ANA_EN_Msk                                                                    (0x1UL << AON_REG2X_PLL1_PLL1_BT_CKI_PLL_ADC_ANA_EN_Pos)
+
+#define AON_REG2X_PLL1_CKO_DBG_FREQ_SEL_Pos                                                                              10U
+#define AON_REG2X_PLL1_CKO_DBG_FREQ_SEL_Msk                                                                              (0x3UL << AON_REG2X_PLL1_CKO_DBG_FREQ_SEL_Pos)
+
+#define AON_REG2X_PLL1_PLL1_TESTMODE_EN_Pos                                                                              12U
+#define AON_REG2X_PLL1_PLL1_TESTMODE_EN_Msk                                                                              (0x1UL << AON_REG2X_PLL1_PLL1_TESTMODE_EN_Pos)
+
+#define AON_REG2X_PLL1_PLL1_TESTMODE_CKO_SEL_Pos                                                                         13U
+#define AON_REG2X_PLL1_PLL1_TESTMODE_CKO_SEL_Msk                                                                         (0x3UL << AON_REG2X_PLL1_PLL1_TESTMODE_CKO_SEL_Pos)
+
+#define AON_REG2X_PLL1_PLL1_CK_BTADC_AND_CK_BTDAC_EN_Pos                                                                 15U
+#define AON_REG2X_PLL1_PLL1_CK_BTADC_AND_CK_BTDAC_EN_Msk                                                                 (0x1UL << AON_REG2X_PLL1_PLL1_CK_BTADC_AND_CK_BTDAC_EN_Pos)
+
+#define AON_REG2X_PLL1_RSVD_Pos                                                                                          16U
+#define AON_REG2X_PLL1_RSVD_Msk                                                                                          (0xFFFFUL << AON_REG2X_PLL1_RSVD_Pos)
+
+/* 0x6FC    0x4000_06fc
+    0       R       PLL1_READY                                                  1'b0
+    15:1    R       RSVD_1                                                      15'b0
+    31:16   R       RSVD                                                        16'b0
+ */
+typedef union _AON_C_KOUT0X_PLL1_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t PLL1_READY: 1;
+        uint32_t RSVD_1: 15;
+        uint32_t RSVD: 16;
+    };
+} AON_C_KOUT0X_PLL1_TYPE;
+
+/*0x4000_06fc AON_C_KOUT0X_PLL1*/
+#define AON_C_KOUT0X_PLL1_PLL1_READY_Pos                                                                                 0U
+#define AON_C_KOUT0X_PLL1_PLL1_READY_Msk                                                                                 (0x1UL << AON_C_KOUT0X_PLL1_PLL1_READY_Pos)
+
+#define AON_C_KOUT0X_PLL1_RSVD_1_Pos                                                                                     1U
+#define AON_C_KOUT0X_PLL1_RSVD_1_Msk                                                                                     (0x7FFFUL << AON_C_KOUT0X_PLL1_RSVD_1_Pos)
+
+#define AON_C_KOUT0X_PLL1_RSVD_Pos                                                                                       16U
+#define AON_C_KOUT0X_PLL1_RSVD_Msk                                                                                       (0xFFFFUL << AON_C_KOUT0X_PLL1_RSVD_Pos)
+
+/* 0x708    0x4000_0708
+    0       R/W     PLL1_LDO_DIG_SW_LDO2PWRCUT                                  1'b0
+    1       R/W     PLL1_LDO_DIG_POW_LDO                                        1'b0
+    2       R/W     PLL1_LDO_DIG_LDO_VPULSE                                     1'b0
+    6:3     R/W     PLL1_LDO_DIG_LDO_SW                                         4'b0110
+    7       R/W     PLL1_LDO_DIG_DOUBLE_OP_I                                    1'b0
+    8       R/W     PLL1_LDO_DIG_IB_EN                                          1'b0
+    9       R/W     PLL1_LDO_ANA_SW_LDO2PWRCUT                                  1'b0
+    10      R/W     PLL1_LDO_ANA_POW_LDO                                        1'b0
+    11      R/W     PLL1_LDO_ANA_LDO_VPULSE                                     1'b0
+    15:12   R/W     PLL1_LDO_ANA_LDO_SW                                         4'b0110
+    16      R/W     PLL1_LDO_ANA_DOUBLE_OP_I                                    1'b0
+    17      R/W     PLL1_LDO_ANA_IB_EN                                          1'b0
+    31:18   R       RSVD                                                        14'b00000000000000
+ */
+typedef union _AON_REG0X_PLL1_LDO_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t PLL1_LDO_DIG_SW_LDO2PWRCUT: 1;
+        uint32_t PLL1_LDO_DIG_POW_LDO: 1;
+        uint32_t PLL1_LDO_DIG_LDO_VPULSE: 1;
+        uint32_t PLL1_LDO_DIG_LDO_SW: 4;
+        uint32_t PLL1_LDO_DIG_DOUBLE_OP_I: 1;
+        uint32_t PLL1_LDO_DIG_IB_EN: 1;
+        uint32_t PLL1_LDO_ANA_SW_LDO2PWRCUT: 1;
+        uint32_t PLL1_LDO_ANA_POW_LDO: 1;
+        uint32_t PLL1_LDO_ANA_LDO_VPULSE: 1;
+        uint32_t PLL1_LDO_ANA_LDO_SW: 4;
+        uint32_t PLL1_LDO_ANA_DOUBLE_OP_I: 1;
+        uint32_t PLL1_LDO_ANA_IB_EN: 1;
+        uint32_t RSVD: 14;
+    };
+} AON_REG0X_PLL1_LDO_TYPE;
+
+/*0x4000_0708 AON_REG0X_PLL1_LDO*/
+#define AON_REG0X_PLL1_LDO_PLL1_LDO_DIG_SW_LDO2PWRCUT_Pos                                                                0U
+#define AON_REG0X_PLL1_LDO_PLL1_LDO_DIG_SW_LDO2PWRCUT_Msk                                                                (0x1UL << AON_REG0X_PLL1_LDO_PLL1_LDO_DIG_SW_LDO2PWRCUT_Pos)
+
+#define AON_REG0X_PLL1_LDO_PLL1_LDO_DIG_POW_LDO_Pos                                                                      1U
+#define AON_REG0X_PLL1_LDO_PLL1_LDO_DIG_POW_LDO_Msk                                                                      (0x1UL << AON_REG0X_PLL1_LDO_PLL1_LDO_DIG_POW_LDO_Pos)
+
+#define AON_REG0X_PLL1_LDO_PLL1_LDO_DIG_LDO_VPULSE_Pos                                                                   2U
+#define AON_REG0X_PLL1_LDO_PLL1_LDO_DIG_LDO_VPULSE_Msk                                                                   (0x1UL << AON_REG0X_PLL1_LDO_PLL1_LDO_DIG_LDO_VPULSE_Pos)
+
+#define AON_REG0X_PLL1_LDO_PLL1_LDO_DIG_LDO_SW_Pos                                                                       3U
+#define AON_REG0X_PLL1_LDO_PLL1_LDO_DIG_LDO_SW_Msk                                                                       (0xFUL << AON_REG0X_PLL1_LDO_PLL1_LDO_DIG_LDO_SW_Pos)
+
+#define AON_REG0X_PLL1_LDO_PLL1_LDO_DIG_DOUBLE_OP_I_Pos                                                                  7U
+#define AON_REG0X_PLL1_LDO_PLL1_LDO_DIG_DOUBLE_OP_I_Msk                                                                  (0x1UL << AON_REG0X_PLL1_LDO_PLL1_LDO_DIG_DOUBLE_OP_I_Pos)
+
+#define AON_REG0X_PLL1_LDO_PLL1_LDO_DIG_IB_EN_Pos                                                                        8U
+#define AON_REG0X_PLL1_LDO_PLL1_LDO_DIG_IB_EN_Msk                                                                        (0x1UL << AON_REG0X_PLL1_LDO_PLL1_LDO_DIG_IB_EN_Pos)
+
+#define AON_REG0X_PLL1_LDO_PLL1_LDO_ANA_SW_LDO2PWRCUT_Pos                                                                9U
+#define AON_REG0X_PLL1_LDO_PLL1_LDO_ANA_SW_LDO2PWRCUT_Msk                                                                (0x1UL << AON_REG0X_PLL1_LDO_PLL1_LDO_ANA_SW_LDO2PWRCUT_Pos)
+
+#define AON_REG0X_PLL1_LDO_PLL1_LDO_ANA_POW_LDO_Pos                                                                      10U
+#define AON_REG0X_PLL1_LDO_PLL1_LDO_ANA_POW_LDO_Msk                                                                      (0x1UL << AON_REG0X_PLL1_LDO_PLL1_LDO_ANA_POW_LDO_Pos)
+
+#define AON_REG0X_PLL1_LDO_PLL1_LDO_ANA_LDO_VPULSE_Pos                                                                   11U
+#define AON_REG0X_PLL1_LDO_PLL1_LDO_ANA_LDO_VPULSE_Msk                                                                   (0x1UL << AON_REG0X_PLL1_LDO_PLL1_LDO_ANA_LDO_VPULSE_Pos)
+
+#define AON_REG0X_PLL1_LDO_PLL1_LDO_ANA_LDO_SW_Pos                                                                       12U
+#define AON_REG0X_PLL1_LDO_PLL1_LDO_ANA_LDO_SW_Msk                                                                       (0xFUL << AON_REG0X_PLL1_LDO_PLL1_LDO_ANA_LDO_SW_Pos)
+
+#define AON_REG0X_PLL1_LDO_PLL1_LDO_ANA_DOUBLE_OP_I_Pos                                                                  16U
+#define AON_REG0X_PLL1_LDO_PLL1_LDO_ANA_DOUBLE_OP_I_Msk                                                                  (0x1UL << AON_REG0X_PLL1_LDO_PLL1_LDO_ANA_DOUBLE_OP_I_Pos)
+
+#define AON_REG0X_PLL1_LDO_PLL1_LDO_ANA_IB_EN_Pos                                                                        17U
+#define AON_REG0X_PLL1_LDO_PLL1_LDO_ANA_IB_EN_Msk                                                                        (0x1UL << AON_REG0X_PLL1_LDO_PLL1_LDO_ANA_IB_EN_Pos)
+
+#define AON_REG0X_PLL1_LDO_RSVD_Pos                                                                                      18U
+#define AON_REG0X_PLL1_LDO_RSVD_Msk                                                                                      (0x3FFFUL << AON_REG0X_PLL1_LDO_RSVD_Pos)
+
+/* 0x728    0x4000_0728
+    9:0     R/W     TMETER_LATCH_0                                              10'h0
+    19:10   R/W     TMETER_LATCH_1                                              10'h0
+    20      R/W     TMETER_LATCH_VLD                                            1'h0
+    21      R       RESERVED                                                    1'h0
+    31:22   R/W     TMETER_LATCH                                                10'h200
+ */
+typedef union _AON_REG_TMETER_DATA_0_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t TMETER_LATCH_0: 10;
+        uint32_t TMETER_LATCH_1: 10;
+        uint32_t TMETER_LATCH_VLD: 1;
+        uint32_t RESERVED: 1;
+        uint32_t TMETER_LATCH: 10;
+    };
+} AON_REG_TMETER_DATA_0_TYPE;
+
+/*0x4000_0728 AON_REG_TMETER_DATA_0*/
+#define AON_REG_TMETER_DATA_0_TMETER_LATCH_0_Pos                                                                         0U
+#define AON_REG_TMETER_DATA_0_TMETER_LATCH_0_Msk                                                                         (0x3FFUL << AON_REG_TMETER_DATA_0_TMETER_LATCH_0_Pos)
+
+#define AON_REG_TMETER_DATA_0_TMETER_LATCH_1_Pos                                                                         10U
+#define AON_REG_TMETER_DATA_0_TMETER_LATCH_1_Msk                                                                         (0x3FFUL << AON_REG_TMETER_DATA_0_TMETER_LATCH_1_Pos)
+
+#define AON_REG_TMETER_DATA_0_TMETER_LATCH_VLD_Pos                                                                       20U
+#define AON_REG_TMETER_DATA_0_TMETER_LATCH_VLD_Msk                                                                       (0x1UL << AON_REG_TMETER_DATA_0_TMETER_LATCH_VLD_Pos)
+
+#define AON_REG_TMETER_DATA_0_RESERVED_Pos                                                                               21U
+#define AON_REG_TMETER_DATA_0_RESERVED_Msk                                                                               (0x1UL << AON_REG_TMETER_DATA_0_RESERVED_Pos)
+
+#define AON_REG_TMETER_DATA_0_TMETER_LATCH_Pos                                                                           22U
+#define AON_REG_TMETER_DATA_0_TMETER_LATCH_Msk                                                                           (0x3FFUL << AON_REG_TMETER_DATA_0_TMETER_LATCH_Pos)
+
+/* 0x72C    0x4000_072c
+    9:0     R/W     TMETER_LATCH_RAW                                            10'h0
+    19:10   R/W     TMETER_PREV_LATCH_REL0                                      10'h0
+    29:20   R/W     TMETER_PREV_LATCH_REL1                                      10'h0
+    31:30   R       RESERVED                                                    2'h0
+ */
+typedef union _AON_REG_TMETER_DATA_1_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t TMETER_LATCH_RAW: 10;
+        uint32_t TMETER_PREV_LATCH_REL0: 10;
+        uint32_t TMETER_PREV_LATCH_REL1: 10;
+        uint32_t RESERVED: 2;
+    };
+} AON_REG_TMETER_DATA_1_TYPE;
+
+/*0x4000_072c AON_REG_TMETER_DATA_1*/
+#define AON_REG_TMETER_DATA_1_TMETER_LATCH_RAW_Pos                                                                       0U
+#define AON_REG_TMETER_DATA_1_TMETER_LATCH_RAW_Msk                                                                       (0x3FFUL << AON_REG_TMETER_DATA_1_TMETER_LATCH_RAW_Pos)
+
+#define AON_REG_TMETER_DATA_1_TMETER_PREV_LATCH_REL0_Pos                                                                 10U
+#define AON_REG_TMETER_DATA_1_TMETER_PREV_LATCH_REL0_Msk                                                                 (0x3FFUL << AON_REG_TMETER_DATA_1_TMETER_PREV_LATCH_REL0_Pos)
+
+#define AON_REG_TMETER_DATA_1_TMETER_PREV_LATCH_REL1_Pos                                                                 20U
+#define AON_REG_TMETER_DATA_1_TMETER_PREV_LATCH_REL1_Msk                                                                 (0x3FFUL << AON_REG_TMETER_DATA_1_TMETER_PREV_LATCH_REL1_Pos)
+
+#define AON_REG_TMETER_DATA_1_RESERVED_Pos                                                                               30U
+#define AON_REG_TMETER_DATA_1_RESERVED_Msk                                                                               (0x3UL << AON_REG_TMETER_DATA_1_RESERVED_Pos)
+
+/* 0x730    0x4000_0730
+    9:0     R/W     TMETER_PREV_LATCH_REL2                                      10'h0
+    19:10   R/W     TMETER_PREV_LATCH_REL3                                      10'h0
+    29:20   R/W     TMETER_PREV_LATCH_REL_FW                                    10'h0
+    31:30   R       RESERVED                                                    2'h0
+ */
+typedef union _AON_REG_TMETER_DATA_2_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t TMETER_PREV_LATCH_REL2: 10;
+        uint32_t TMETER_PREV_LATCH_REL3: 10;
+        uint32_t TMETER_PREV_LATCH_REL_FW: 10;
+        uint32_t RESERVED: 2;
+    };
+} AON_REG_TMETER_DATA_2_TYPE;
+
+/*0x4000_0730 AON_REG_TMETER_DATA_2*/
+#define AON_REG_TMETER_DATA_2_TMETER_PREV_LATCH_REL2_Pos                                                                 0U
+#define AON_REG_TMETER_DATA_2_TMETER_PREV_LATCH_REL2_Msk                                                                 (0x3FFUL << AON_REG_TMETER_DATA_2_TMETER_PREV_LATCH_REL2_Pos)
+
+#define AON_REG_TMETER_DATA_2_TMETER_PREV_LATCH_REL3_Pos                                                                 10U
+#define AON_REG_TMETER_DATA_2_TMETER_PREV_LATCH_REL3_Msk                                                                 (0x3FFUL << AON_REG_TMETER_DATA_2_TMETER_PREV_LATCH_REL3_Pos)
+
+#define AON_REG_TMETER_DATA_2_TMETER_PREV_LATCH_REL_FW_Pos                                                               20U
+#define AON_REG_TMETER_DATA_2_TMETER_PREV_LATCH_REL_FW_Msk                                                               (0x3FFUL << AON_REG_TMETER_DATA_2_TMETER_PREV_LATCH_REL_FW_Pos)
+
+#define AON_REG_TMETER_DATA_2_RESERVED_Pos                                                                               30U
+#define AON_REG_TMETER_DATA_2_RESERVED_Msk                                                                               (0x3UL << AON_REG_TMETER_DATA_2_RESERVED_Pos)
+
+/* 0x738    0x4000_0738
+    0       R/WAC   FW_TASK_START_ONE_SHOT                                      1'h0
+    4:1     R/W     TMETER_CTRL1_DUMMY_1                                        4'h0
+    9:5     R       TC_STATE                                                    5'h0
+    10      R/W     EN_REL_COMP0                                                1'h0
+    11      R/W     EN_REL_COMP1                                                1'h0
+    12      R/W     EN_REL_COMP2                                                1'h0
+    13      R/W     EN_REL_COMP3                                                1'h0
+    14      R/W     EN_REL_COMP_FW                                              1'h0
+    15      R/W     EN_FW_REL_COMP_INT                                          1'h0
+    19:16   R       RESERVED                                                    4'h0
+    20      R       VLD_TMETER                                                  1'h0
+    21      R       TC_BUSY                                                     1'h0
+    22      R/W     CLK_TMETER_QACTIVE_MAN_DATA                                 1'h0
+    23      R/W     CLK_TMETER_QACTIVE_MAN_ENABLE                               1'h0
+    31:24   R/W     TMETER_CTRL1_DUMMY                                          8'h0
+ */
+typedef union _AON_REG_TMETER_CTRL1_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t FW_TASK_START_ONE_SHOT: 1;
+        uint32_t TMETER_CTRL1_DUMMY_1: 4;
+        uint32_t TC_STATE: 5;
+        uint32_t EN_REL_COMP0: 1;
+        uint32_t EN_REL_COMP1: 1;
+        uint32_t EN_REL_COMP2: 1;
+        uint32_t EN_REL_COMP3: 1;
+        uint32_t EN_REL_COMP_FW: 1;
+        uint32_t EN_FW_REL_COMP_INT: 1;
+        uint32_t RESERVED: 4;
+        uint32_t VLD_TMETER: 1;
+        uint32_t TC_BUSY: 1;
+        uint32_t CLK_TMETER_QACTIVE_MAN_DATA: 1;
+        uint32_t CLK_TMETER_QACTIVE_MAN_ENABLE: 1;
+        uint32_t TMETER_CTRL1_DUMMY: 8;
+    };
+} AON_REG_TMETER_CTRL1_TYPE;
+
+/*0x4000_0738 AON_REG_TMETER_CTRL1*/
+#define AON_REG_TMETER_CTRL1_FW_TASK_START_ONE_SHOT_Pos                                                                  0U
+#define AON_REG_TMETER_CTRL1_FW_TASK_START_ONE_SHOT_Msk                                                                  (0x1UL << AON_REG_TMETER_CTRL1_FW_TASK_START_ONE_SHOT_Pos)
+
+#define AON_REG_TMETER_CTRL1_TMETER_CTRL1_DUMMY_1_Pos                                                                    1U
+#define AON_REG_TMETER_CTRL1_TMETER_CTRL1_DUMMY_1_Msk                                                                    (0xFUL << AON_REG_TMETER_CTRL1_TMETER_CTRL1_DUMMY_1_Pos)
+
+#define AON_REG_TMETER_CTRL1_TC_STATE_Pos                                                                                5U
+#define AON_REG_TMETER_CTRL1_TC_STATE_Msk                                                                                (0x1FUL << AON_REG_TMETER_CTRL1_TC_STATE_Pos)
+
+#define AON_REG_TMETER_CTRL1_EN_REL_COMP0_Pos                                                                            10U
+#define AON_REG_TMETER_CTRL1_EN_REL_COMP0_Msk                                                                            (0x1UL << AON_REG_TMETER_CTRL1_EN_REL_COMP0_Pos)
+
+#define AON_REG_TMETER_CTRL1_EN_REL_COMP1_Pos                                                                            11U
+#define AON_REG_TMETER_CTRL1_EN_REL_COMP1_Msk                                                                            (0x1UL << AON_REG_TMETER_CTRL1_EN_REL_COMP1_Pos)
+
+#define AON_REG_TMETER_CTRL1_EN_REL_COMP2_Pos                                                                            12U
+#define AON_REG_TMETER_CTRL1_EN_REL_COMP2_Msk                                                                            (0x1UL << AON_REG_TMETER_CTRL1_EN_REL_COMP2_Pos)
+
+#define AON_REG_TMETER_CTRL1_EN_REL_COMP3_Pos                                                                            13U
+#define AON_REG_TMETER_CTRL1_EN_REL_COMP3_Msk                                                                            (0x1UL << AON_REG_TMETER_CTRL1_EN_REL_COMP3_Pos)
+
+#define AON_REG_TMETER_CTRL1_EN_REL_COMP_FW_Pos                                                                          14U
+#define AON_REG_TMETER_CTRL1_EN_REL_COMP_FW_Msk                                                                          (0x1UL << AON_REG_TMETER_CTRL1_EN_REL_COMP_FW_Pos)
+
+#define AON_REG_TMETER_CTRL1_EN_FW_REL_COMP_INT_Pos                                                                      15U
+#define AON_REG_TMETER_CTRL1_EN_FW_REL_COMP_INT_Msk                                                                      (0x1UL << AON_REG_TMETER_CTRL1_EN_FW_REL_COMP_INT_Pos)
+
+#define AON_REG_TMETER_CTRL1_RESERVED_Pos                                                                                16U
+#define AON_REG_TMETER_CTRL1_RESERVED_Msk                                                                                (0xFUL << AON_REG_TMETER_CTRL1_RESERVED_Pos)
+
+#define AON_REG_TMETER_CTRL1_VLD_TMETER_Pos                                                                              20U
+#define AON_REG_TMETER_CTRL1_VLD_TMETER_Msk                                                                              (0x1UL << AON_REG_TMETER_CTRL1_VLD_TMETER_Pos)
+
+#define AON_REG_TMETER_CTRL1_TC_BUSY_Pos                                                                                 21U
+#define AON_REG_TMETER_CTRL1_TC_BUSY_Msk                                                                                 (0x1UL << AON_REG_TMETER_CTRL1_TC_BUSY_Pos)
+
+#define AON_REG_TMETER_CTRL1_CLK_TMETER_QACTIVE_MAN_DATA_Pos                                                             22U
+#define AON_REG_TMETER_CTRL1_CLK_TMETER_QACTIVE_MAN_DATA_Msk                                                             (0x1UL << AON_REG_TMETER_CTRL1_CLK_TMETER_QACTIVE_MAN_DATA_Pos)
+
+#define AON_REG_TMETER_CTRL1_CLK_TMETER_QACTIVE_MAN_ENABLE_Pos                                                           23U
+#define AON_REG_TMETER_CTRL1_CLK_TMETER_QACTIVE_MAN_ENABLE_Msk                                                           (0x1UL << AON_REG_TMETER_CTRL1_CLK_TMETER_QACTIVE_MAN_ENABLE_Pos)
+
+#define AON_REG_TMETER_CTRL1_TMETER_CTRL1_DUMMY_Pos                                                                      24U
+#define AON_REG_TMETER_CTRL1_TMETER_CTRL1_DUMMY_Msk                                                                      (0xFFUL << AON_REG_TMETER_CTRL1_TMETER_CTRL1_DUMMY_Pos)
+
+/* 0x73C    0x4000_073c
+    0       R/W1C   ST_REL_COMP0                                                1'h0
+    1       R/W1C   ST_REL_COMP1                                                1'h0
+    2       R/W1C   ST_REL_COMP2                                                1'h0
+    3       R/W1C   ST_REL_COMP3                                                1'h0
+    4       R       ST_ABS_COMP0                                                1'h0
+    5       R       ST_ABS_COMP1                                                1'h0
+    6       R       ST_ABS_COMP2                                                1'h0
+    7       R       ST_ABS_COMP3                                                1'h0
+    8       R/W     TMETER_COMP_CTRL_DUMMY_1                                    1'h0
+    9       R/W1C   ST_FW_REL_COMP_INT                                          1'h0
+    10      R/W1C   ST_FW_REL_COMP                                              1'h0
+    11      R/W     TMETER_PREV_LATCH_REL0_VLD                                  1'h0
+    12      R/W     TMETER_PREV_LATCH_REL1_VLD                                  1'h0
+    13      R/W     TMETER_PREV_LATCH_REL2_VLD                                  1'h0
+    14      R/W     TMETER_PREV_LATCH_REL3_VLD                                  1'h0
+    15      R/W     TMETER_PREV_LATCH_FW_VLD                                    1'h0
+    31:16   R/W     TMETER_COMP_CTRL_DUMMY                                      16'h0
+ */
+typedef union _AON_REG_TMETER_COMP_CTRL_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t ST_REL_COMP0: 1;
+        uint32_t ST_REL_COMP1: 1;
+        uint32_t ST_REL_COMP2: 1;
+        uint32_t ST_REL_COMP3: 1;
+        uint32_t ST_ABS_COMP0: 1;
+        uint32_t ST_ABS_COMP1: 1;
+        uint32_t ST_ABS_COMP2: 1;
+        uint32_t ST_ABS_COMP3: 1;
+        uint32_t TMETER_COMP_CTRL_DUMMY_1: 1;
+        uint32_t ST_FW_REL_COMP_INT: 1;
+        uint32_t ST_FW_REL_COMP: 1;
+        uint32_t TMETER_PREV_LATCH_REL0_VLD: 1;
+        uint32_t TMETER_PREV_LATCH_REL1_VLD: 1;
+        uint32_t TMETER_PREV_LATCH_REL2_VLD: 1;
+        uint32_t TMETER_PREV_LATCH_REL3_VLD: 1;
+        uint32_t TMETER_PREV_LATCH_FW_VLD: 1;
+        uint32_t TMETER_COMP_CTRL_DUMMY: 16;
+    };
+} AON_REG_TMETER_COMP_CTRL_TYPE;
+
+/*0x4000_073c AON_REG_TMETER_COMP_CTRL*/
+#define AON_REG_TMETER_COMP_CTRL_ST_REL_COMP0_Pos                                                                        0U
+#define AON_REG_TMETER_COMP_CTRL_ST_REL_COMP0_Msk                                                                        (0x1UL << AON_REG_TMETER_COMP_CTRL_ST_REL_COMP0_Pos)
+
+#define AON_REG_TMETER_COMP_CTRL_ST_REL_COMP1_Pos                                                                        1U
+#define AON_REG_TMETER_COMP_CTRL_ST_REL_COMP1_Msk                                                                        (0x1UL << AON_REG_TMETER_COMP_CTRL_ST_REL_COMP1_Pos)
+
+#define AON_REG_TMETER_COMP_CTRL_ST_REL_COMP2_Pos                                                                        2U
+#define AON_REG_TMETER_COMP_CTRL_ST_REL_COMP2_Msk                                                                        (0x1UL << AON_REG_TMETER_COMP_CTRL_ST_REL_COMP2_Pos)
+
+#define AON_REG_TMETER_COMP_CTRL_ST_REL_COMP3_Pos                                                                        3U
+#define AON_REG_TMETER_COMP_CTRL_ST_REL_COMP3_Msk                                                                        (0x1UL << AON_REG_TMETER_COMP_CTRL_ST_REL_COMP3_Pos)
+
+#define AON_REG_TMETER_COMP_CTRL_ST_ABS_COMP0_Pos                                                                        4U
+#define AON_REG_TMETER_COMP_CTRL_ST_ABS_COMP0_Msk                                                                        (0x1UL << AON_REG_TMETER_COMP_CTRL_ST_ABS_COMP0_Pos)
+
+#define AON_REG_TMETER_COMP_CTRL_ST_ABS_COMP1_Pos                                                                        5U
+#define AON_REG_TMETER_COMP_CTRL_ST_ABS_COMP1_Msk                                                                        (0x1UL << AON_REG_TMETER_COMP_CTRL_ST_ABS_COMP1_Pos)
+
+#define AON_REG_TMETER_COMP_CTRL_ST_ABS_COMP2_Pos                                                                        6U
+#define AON_REG_TMETER_COMP_CTRL_ST_ABS_COMP2_Msk                                                                        (0x1UL << AON_REG_TMETER_COMP_CTRL_ST_ABS_COMP2_Pos)
+
+#define AON_REG_TMETER_COMP_CTRL_ST_ABS_COMP3_Pos                                                                        7U
+#define AON_REG_TMETER_COMP_CTRL_ST_ABS_COMP3_Msk                                                                        (0x1UL << AON_REG_TMETER_COMP_CTRL_ST_ABS_COMP3_Pos)
+
+#define AON_REG_TMETER_COMP_CTRL_TMETER_COMP_CTRL_DUMMY_1_Pos                                                            8U
+#define AON_REG_TMETER_COMP_CTRL_TMETER_COMP_CTRL_DUMMY_1_Msk                                                            (0x1UL << AON_REG_TMETER_COMP_CTRL_TMETER_COMP_CTRL_DUMMY_1_Pos)
+
+#define AON_REG_TMETER_COMP_CTRL_ST_FW_REL_COMP_INT_Pos                                                                  9U
+#define AON_REG_TMETER_COMP_CTRL_ST_FW_REL_COMP_INT_Msk                                                                  (0x1UL << AON_REG_TMETER_COMP_CTRL_ST_FW_REL_COMP_INT_Pos)
+
+#define AON_REG_TMETER_COMP_CTRL_ST_FW_REL_COMP_Pos                                                                      10U
+#define AON_REG_TMETER_COMP_CTRL_ST_FW_REL_COMP_Msk                                                                      (0x1UL << AON_REG_TMETER_COMP_CTRL_ST_FW_REL_COMP_Pos)
+
+#define AON_REG_TMETER_COMP_CTRL_TMETER_PREV_LATCH_REL0_VLD_Pos                                                          11U
+#define AON_REG_TMETER_COMP_CTRL_TMETER_PREV_LATCH_REL0_VLD_Msk                                                          (0x1UL << AON_REG_TMETER_COMP_CTRL_TMETER_PREV_LATCH_REL0_VLD_Pos)
+
+#define AON_REG_TMETER_COMP_CTRL_TMETER_PREV_LATCH_REL1_VLD_Pos                                                          12U
+#define AON_REG_TMETER_COMP_CTRL_TMETER_PREV_LATCH_REL1_VLD_Msk                                                          (0x1UL << AON_REG_TMETER_COMP_CTRL_TMETER_PREV_LATCH_REL1_VLD_Pos)
+
+#define AON_REG_TMETER_COMP_CTRL_TMETER_PREV_LATCH_REL2_VLD_Pos                                                          13U
+#define AON_REG_TMETER_COMP_CTRL_TMETER_PREV_LATCH_REL2_VLD_Msk                                                          (0x1UL << AON_REG_TMETER_COMP_CTRL_TMETER_PREV_LATCH_REL2_VLD_Pos)
+
+#define AON_REG_TMETER_COMP_CTRL_TMETER_PREV_LATCH_REL3_VLD_Pos                                                          14U
+#define AON_REG_TMETER_COMP_CTRL_TMETER_PREV_LATCH_REL3_VLD_Msk                                                          (0x1UL << AON_REG_TMETER_COMP_CTRL_TMETER_PREV_LATCH_REL3_VLD_Pos)
+
+#define AON_REG_TMETER_COMP_CTRL_TMETER_PREV_LATCH_FW_VLD_Pos                                                            15U
+#define AON_REG_TMETER_COMP_CTRL_TMETER_PREV_LATCH_FW_VLD_Msk                                                            (0x1UL << AON_REG_TMETER_COMP_CTRL_TMETER_PREV_LATCH_FW_VLD_Pos)
+
+#define AON_REG_TMETER_COMP_CTRL_TMETER_COMP_CTRL_DUMMY_Pos                                                              16U
+#define AON_REG_TMETER_COMP_CTRL_TMETER_COMP_CTRL_DUMMY_Msk                                                              (0xFFFFUL << AON_REG_TMETER_COMP_CTRL_TMETER_COMP_CTRL_DUMMY_Pos)
+
+/* 0x740    0x4000_0740
+    9:0     R/W     REL_COMP0_THD                                               10'h0
+    19:10   R/W     REL_COMP1_THD                                               10'h0
+    31:20   R/W     TMETER_REL_COMP_THD0_DUMMY                                  12'h0
+ */
+typedef union _AON_REG_TMETER_REL_COMP_THD0_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t REL_COMP0_THD: 10;
+        uint32_t REL_COMP1_THD: 10;
+        uint32_t TMETER_REL_COMP_THD0_DUMMY: 12;
+    };
+} AON_REG_TMETER_REL_COMP_THD0_TYPE;
+
+/*0x4000_0740 AON_REG_TMETER_REL_COMP_THD0*/
+#define AON_REG_TMETER_REL_COMP_THD0_REL_COMP0_THD_Pos                                                                   0U
+#define AON_REG_TMETER_REL_COMP_THD0_REL_COMP0_THD_Msk                                                                   (0x3FFUL << AON_REG_TMETER_REL_COMP_THD0_REL_COMP0_THD_Pos)
+
+#define AON_REG_TMETER_REL_COMP_THD0_REL_COMP1_THD_Pos                                                                   10U
+#define AON_REG_TMETER_REL_COMP_THD0_REL_COMP1_THD_Msk                                                                   (0x3FFUL << AON_REG_TMETER_REL_COMP_THD0_REL_COMP1_THD_Pos)
+
+#define AON_REG_TMETER_REL_COMP_THD0_TMETER_REL_COMP_THD0_DUMMY_Pos                                                      20U
+#define AON_REG_TMETER_REL_COMP_THD0_TMETER_REL_COMP_THD0_DUMMY_Msk                                                      (0xFFFUL << AON_REG_TMETER_REL_COMP_THD0_TMETER_REL_COMP_THD0_DUMMY_Pos)
+
+/* 0x744    0x4000_0744
+    9:0     R/W     REL_COMP2_THD                                               10'h0
+    19:10   R/W     REL_COMP3_THD                                               10'h0
+    29:20   R/W     FW_REL_COMP_THD                                             10'h0
+    31:30   R/W     TMETER_REL_COMP_THD1_DUMMY                                  2'h0
+ */
+typedef union _AON_REG_TMETER_REL_COMP_THD1_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t REL_COMP2_THD: 10;
+        uint32_t REL_COMP3_THD: 10;
+        uint32_t FW_REL_COMP_THD: 10;
+        uint32_t TMETER_REL_COMP_THD1_DUMMY: 2;
+    };
+} AON_REG_TMETER_REL_COMP_THD1_TYPE;
+
+/*0x4000_0744 AON_REG_TMETER_REL_COMP_THD1*/
+#define AON_REG_TMETER_REL_COMP_THD1_REL_COMP2_THD_Pos                                                                   0U
+#define AON_REG_TMETER_REL_COMP_THD1_REL_COMP2_THD_Msk                                                                   (0x3FFUL << AON_REG_TMETER_REL_COMP_THD1_REL_COMP2_THD_Pos)
+
+#define AON_REG_TMETER_REL_COMP_THD1_REL_COMP3_THD_Pos                                                                   10U
+#define AON_REG_TMETER_REL_COMP_THD1_REL_COMP3_THD_Msk                                                                   (0x3FFUL << AON_REG_TMETER_REL_COMP_THD1_REL_COMP3_THD_Pos)
+
+#define AON_REG_TMETER_REL_COMP_THD1_FW_REL_COMP_THD_Pos                                                                 20U
+#define AON_REG_TMETER_REL_COMP_THD1_FW_REL_COMP_THD_Msk                                                                 (0x3FFUL << AON_REG_TMETER_REL_COMP_THD1_FW_REL_COMP_THD_Pos)
+
+#define AON_REG_TMETER_REL_COMP_THD1_TMETER_REL_COMP_THD1_DUMMY_Pos                                                      30U
+#define AON_REG_TMETER_REL_COMP_THD1_TMETER_REL_COMP_THD1_DUMMY_Msk                                                      (0x3UL << AON_REG_TMETER_REL_COMP_THD1_TMETER_REL_COMP_THD1_DUMMY_Pos)
+
+/* 0x748    0x4000_0748
+    9:0     R/W     ABS_COMP0_VREF_H                                            10'h0
+    19:10   R/W     ABS_COMP0_VREF_L                                            10'h0
+    31:20   R/W     TMETER_ABS_COMP0_VREF_DUMMY                                 12'h0
+ */
+typedef union _AON_REG_TMETER_ABS_COMP0_VREF_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t ABS_COMP0_VREF_H: 10;
+        uint32_t ABS_COMP0_VREF_L: 10;
+        uint32_t TMETER_ABS_COMP0_VREF_DUMMY: 12;
+    };
+} AON_REG_TMETER_ABS_COMP0_VREF_TYPE;
+
+/*0x4000_0748 AON_REG_TMETER_ABS_COMP0_VREF*/
+#define AON_REG_TMETER_ABS_COMP0_VREF_ABS_COMP0_VREF_H_Pos                                                               0U
+#define AON_REG_TMETER_ABS_COMP0_VREF_ABS_COMP0_VREF_H_Msk                                                               (0x3FFUL << AON_REG_TMETER_ABS_COMP0_VREF_ABS_COMP0_VREF_H_Pos)
+
+#define AON_REG_TMETER_ABS_COMP0_VREF_ABS_COMP0_VREF_L_Pos                                                               10U
+#define AON_REG_TMETER_ABS_COMP0_VREF_ABS_COMP0_VREF_L_Msk                                                               (0x3FFUL << AON_REG_TMETER_ABS_COMP0_VREF_ABS_COMP0_VREF_L_Pos)
+
+#define AON_REG_TMETER_ABS_COMP0_VREF_TMETER_ABS_COMP0_VREF_DUMMY_Pos                                                    20U
+#define AON_REG_TMETER_ABS_COMP0_VREF_TMETER_ABS_COMP0_VREF_DUMMY_Msk                                                    (0xFFFUL << AON_REG_TMETER_ABS_COMP0_VREF_TMETER_ABS_COMP0_VREF_DUMMY_Pos)
+
+/* 0x74C    0x4000_074c
+    9:0     R/W     ABS_COMP1_VREF_H                                            10'h0
+    19:10   R/W     ABS_COMP1_VREF_L                                            10'h0
+    31:20   R/W     TMETER_ABS_COMP1_VREF_DUMMY                                 12'h0
+ */
+typedef union _AON_REG_TMETER_ABS_COMP1_VREF_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t ABS_COMP1_VREF_H: 10;
+        uint32_t ABS_COMP1_VREF_L: 10;
+        uint32_t TMETER_ABS_COMP1_VREF_DUMMY: 12;
+    };
+} AON_REG_TMETER_ABS_COMP1_VREF_TYPE;
+
+/*0x4000_074c AON_REG_TMETER_ABS_COMP1_VREF*/
+#define AON_REG_TMETER_ABS_COMP1_VREF_ABS_COMP1_VREF_H_Pos                                                               0U
+#define AON_REG_TMETER_ABS_COMP1_VREF_ABS_COMP1_VREF_H_Msk                                                               (0x3FFUL << AON_REG_TMETER_ABS_COMP1_VREF_ABS_COMP1_VREF_H_Pos)
+
+#define AON_REG_TMETER_ABS_COMP1_VREF_ABS_COMP1_VREF_L_Pos                                                               10U
+#define AON_REG_TMETER_ABS_COMP1_VREF_ABS_COMP1_VREF_L_Msk                                                               (0x3FFUL << AON_REG_TMETER_ABS_COMP1_VREF_ABS_COMP1_VREF_L_Pos)
+
+#define AON_REG_TMETER_ABS_COMP1_VREF_TMETER_ABS_COMP1_VREF_DUMMY_Pos                                                    20U
+#define AON_REG_TMETER_ABS_COMP1_VREF_TMETER_ABS_COMP1_VREF_DUMMY_Msk                                                    (0xFFFUL << AON_REG_TMETER_ABS_COMP1_VREF_TMETER_ABS_COMP1_VREF_DUMMY_Pos)
+
+/* 0x750    0x4000_0750
+    9:0     R/W     ABS_COMP2_VREF_H                                            10'h0
+    19:10   R/W     ABS_COMP2_VREF_L                                            10'h0
+    31:20   R/W     TMETER_ABS_COMP2_VREF_DUMMY                                 12'h0
+ */
+typedef union _AON_REG_TMETER_ABS_COMP2_VREF_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t ABS_COMP2_VREF_H: 10;
+        uint32_t ABS_COMP2_VREF_L: 10;
+        uint32_t TMETER_ABS_COMP2_VREF_DUMMY: 12;
+    };
+} AON_REG_TMETER_ABS_COMP2_VREF_TYPE;
+
+/*0x4000_0750 AON_REG_TMETER_ABS_COMP2_VREF*/
+#define AON_REG_TMETER_ABS_COMP2_VREF_ABS_COMP2_VREF_H_Pos                                                               0U
+#define AON_REG_TMETER_ABS_COMP2_VREF_ABS_COMP2_VREF_H_Msk                                                               (0x3FFUL << AON_REG_TMETER_ABS_COMP2_VREF_ABS_COMP2_VREF_H_Pos)
+
+#define AON_REG_TMETER_ABS_COMP2_VREF_ABS_COMP2_VREF_L_Pos                                                               10U
+#define AON_REG_TMETER_ABS_COMP2_VREF_ABS_COMP2_VREF_L_Msk                                                               (0x3FFUL << AON_REG_TMETER_ABS_COMP2_VREF_ABS_COMP2_VREF_L_Pos)
+
+#define AON_REG_TMETER_ABS_COMP2_VREF_TMETER_ABS_COMP2_VREF_DUMMY_Pos                                                    20U
+#define AON_REG_TMETER_ABS_COMP2_VREF_TMETER_ABS_COMP2_VREF_DUMMY_Msk                                                    (0xFFFUL << AON_REG_TMETER_ABS_COMP2_VREF_TMETER_ABS_COMP2_VREF_DUMMY_Pos)
+
+/* 0x754    0x4000_0754
+    9:0     R/W     ABS_COMP3_VREF_H                                            10'h0
+    19:10   R/W     ABS_COMP3_VREF_L                                            10'h0
+    31:20   R/W     TMETER_ABS_COMP3_VREF_DUMMY                                 12'h0
+ */
+typedef union _AON_REG_TMETER_ABS_COMP3_VREF_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t ABS_COMP3_VREF_H: 10;
+        uint32_t ABS_COMP3_VREF_L: 10;
+        uint32_t TMETER_ABS_COMP3_VREF_DUMMY: 12;
+    };
+} AON_REG_TMETER_ABS_COMP3_VREF_TYPE;
+
+/*0x4000_0754 AON_REG_TMETER_ABS_COMP3_VREF*/
+#define AON_REG_TMETER_ABS_COMP3_VREF_ABS_COMP3_VREF_H_Pos                                                               0U
+#define AON_REG_TMETER_ABS_COMP3_VREF_ABS_COMP3_VREF_H_Msk                                                               (0x3FFUL << AON_REG_TMETER_ABS_COMP3_VREF_ABS_COMP3_VREF_H_Pos)
+
+#define AON_REG_TMETER_ABS_COMP3_VREF_ABS_COMP3_VREF_L_Pos                                                               10U
+#define AON_REG_TMETER_ABS_COMP3_VREF_ABS_COMP3_VREF_L_Msk                                                               (0x3FFUL << AON_REG_TMETER_ABS_COMP3_VREF_ABS_COMP3_VREF_L_Pos)
+
+#define AON_REG_TMETER_ABS_COMP3_VREF_TMETER_ABS_COMP3_VREF_DUMMY_Pos                                                    20U
+#define AON_REG_TMETER_ABS_COMP3_VREF_TMETER_ABS_COMP3_VREF_DUMMY_Msk                                                    (0xFFFUL << AON_REG_TMETER_ABS_COMP3_VREF_TMETER_ABS_COMP3_VREF_DUMMY_Pos)
+
+/* 0x758    0x4000_0758
+    0       R       DOUT                                                        1'h0
+    1       R/W     EN11_DEBUG_TMETER                                           1'h0
+    2       R       BB_TMETER_BBTRIGGER                                         1'h0
+    3       R       TMETER_CLK                                                  1'h1
+    4       R       TMETER_CH_LV                                                1'h0
+    5       R/W     TMETER_CH_EN                                                1'h1
+    6       R       POW11_TMETER                                                1'h0
+    8:7     R/W     TMETER_CLK_FREQ_CTRL                                        2'h0
+    10:9    R/W     TMETER_LDO_STARTUP_TIME                                     2'h0
+    11      R/W     TMETER_BUF_CH                                               1'h0
+    14:12   R/W     SELECT_TMETER                                               3'h0
+    15      R/W     TMETER_ANALOG_CTRL_DUMMY                                    1'h0
+    21:16   R/W     BT_TMETER18_LDO                                             6'h0
+    31:22   R       TC_TMETER                                                   10'h200
+ */
+typedef union _AON_REG_TMETER_ANALOG_CTRL_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t DOUT: 1;
+        uint32_t EN11_DEBUG_TMETER: 1;
+        uint32_t BB_TMETER_BBTRIGGER: 1;
+        uint32_t TMETER_CLK: 1;
+        uint32_t TMETER_CH_LV: 1;
+        uint32_t TMETER_CH_EN: 1;
+        uint32_t POW11_TMETER: 1;
+        uint32_t TMETER_CLK_FREQ_CTRL: 2;
+        uint32_t TMETER_LDO_STARTUP_TIME: 2;
+        uint32_t TMETER_BUF_CH: 1;
+        uint32_t SELECT_TMETER: 3;
+        uint32_t TMETER_ANALOG_CTRL_DUMMY: 1;
+        uint32_t BT_TMETER18_LDO: 6;
+        uint32_t TC_TMETER: 10;
+    };
+} AON_REG_TMETER_ANALOG_CTRL_TYPE;
+
+/*0x4000_0758 AON_REG_TMETER_ANALOG_CTRL*/
+#define AON_REG_TMETER_ANALOG_CTRL_DOUT_Pos                                                                              0U
+#define AON_REG_TMETER_ANALOG_CTRL_DOUT_Msk                                                                              (0x1UL << AON_REG_TMETER_ANALOG_CTRL_DOUT_Pos)
+
+#define AON_REG_TMETER_ANALOG_CTRL_EN11_DEBUG_TMETER_Pos                                                                 1U
+#define AON_REG_TMETER_ANALOG_CTRL_EN11_DEBUG_TMETER_Msk                                                                 (0x1UL << AON_REG_TMETER_ANALOG_CTRL_EN11_DEBUG_TMETER_Pos)
+
+#define AON_REG_TMETER_ANALOG_CTRL_BB_TMETER_BBTRIGGER_Pos                                                               2U
+#define AON_REG_TMETER_ANALOG_CTRL_BB_TMETER_BBTRIGGER_Msk                                                               (0x1UL << AON_REG_TMETER_ANALOG_CTRL_BB_TMETER_BBTRIGGER_Pos)
+
+#define AON_REG_TMETER_ANALOG_CTRL_TMETER_CLK_Pos                                                                        3U
+#define AON_REG_TMETER_ANALOG_CTRL_TMETER_CLK_Msk                                                                        (0x1UL << AON_REG_TMETER_ANALOG_CTRL_TMETER_CLK_Pos)
+
+#define AON_REG_TMETER_ANALOG_CTRL_TMETER_CH_LV_Pos                                                                      4U
+#define AON_REG_TMETER_ANALOG_CTRL_TMETER_CH_LV_Msk                                                                      (0x1UL << AON_REG_TMETER_ANALOG_CTRL_TMETER_CH_LV_Pos)
+
+#define AON_REG_TMETER_ANALOG_CTRL_TMETER_CH_EN_Pos                                                                      5U
+#define AON_REG_TMETER_ANALOG_CTRL_TMETER_CH_EN_Msk                                                                      (0x1UL << AON_REG_TMETER_ANALOG_CTRL_TMETER_CH_EN_Pos)
+
+#define AON_REG_TMETER_ANALOG_CTRL_POW11_TMETER_Pos                                                                      6U
+#define AON_REG_TMETER_ANALOG_CTRL_POW11_TMETER_Msk                                                                      (0x1UL << AON_REG_TMETER_ANALOG_CTRL_POW11_TMETER_Pos)
+
+#define AON_REG_TMETER_ANALOG_CTRL_TMETER_CLK_FREQ_CTRL_Pos                                                              7U
+#define AON_REG_TMETER_ANALOG_CTRL_TMETER_CLK_FREQ_CTRL_Msk                                                              (0x3UL << AON_REG_TMETER_ANALOG_CTRL_TMETER_CLK_FREQ_CTRL_Pos)
+
+#define AON_REG_TMETER_ANALOG_CTRL_TMETER_LDO_STARTUP_TIME_Pos                                                           9U
+#define AON_REG_TMETER_ANALOG_CTRL_TMETER_LDO_STARTUP_TIME_Msk                                                           (0x3UL << AON_REG_TMETER_ANALOG_CTRL_TMETER_LDO_STARTUP_TIME_Pos)
+
+#define AON_REG_TMETER_ANALOG_CTRL_TMETER_BUF_CH_Pos                                                                     11U
+#define AON_REG_TMETER_ANALOG_CTRL_TMETER_BUF_CH_Msk                                                                     (0x1UL << AON_REG_TMETER_ANALOG_CTRL_TMETER_BUF_CH_Pos)
+
+#define AON_REG_TMETER_ANALOG_CTRL_SELECT_TMETER_Pos                                                                     12U
+#define AON_REG_TMETER_ANALOG_CTRL_SELECT_TMETER_Msk                                                                     (0x7UL << AON_REG_TMETER_ANALOG_CTRL_SELECT_TMETER_Pos)
+
+#define AON_REG_TMETER_ANALOG_CTRL_TMETER_ANALOG_CTRL_DUMMY_Pos                                                          15U
+#define AON_REG_TMETER_ANALOG_CTRL_TMETER_ANALOG_CTRL_DUMMY_Msk                                                          (0x1UL << AON_REG_TMETER_ANALOG_CTRL_TMETER_ANALOG_CTRL_DUMMY_Pos)
+
+#define AON_REG_TMETER_ANALOG_CTRL_BT_TMETER18_LDO_Pos                                                                   16U
+#define AON_REG_TMETER_ANALOG_CTRL_BT_TMETER18_LDO_Msk                                                                   (0x3FUL << AON_REG_TMETER_ANALOG_CTRL_BT_TMETER18_LDO_Pos)
+
+#define AON_REG_TMETER_ANALOG_CTRL_TC_TMETER_Pos                                                                         22U
+#define AON_REG_TMETER_ANALOG_CTRL_TC_TMETER_Msk                                                                         (0x3FFUL << AON_REG_TMETER_ANALOG_CTRL_TC_TMETER_Pos)
+
+/* 0x75C    0x4000_075c
+    10:0    R/W     TMETER_MAPPING_B                                            11'h0
+    29:11   R/W     TMETER_MAPPING_A                                            19'h0
+    31:30   R       RESERVED                                                    2'h0
+ */
+typedef union _AON_REG_TMETER_MAPPING_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t TMETER_MAPPING_B: 11;
+        uint32_t TMETER_MAPPING_A: 19;
+        uint32_t RESERVED: 2;
+    };
+} AON_REG_TMETER_MAPPING_TYPE;
+
+/*0x4000_075c AON_REG_TMETER_MAPPING*/
+#define AON_REG_TMETER_MAPPING_TMETER_MAPPING_B_Pos                                                                      0U
+#define AON_REG_TMETER_MAPPING_TMETER_MAPPING_B_Msk                                                                      (0x7FFUL << AON_REG_TMETER_MAPPING_TMETER_MAPPING_B_Pos)
+
+#define AON_REG_TMETER_MAPPING_TMETER_MAPPING_A_Pos                                                                      11U
+#define AON_REG_TMETER_MAPPING_TMETER_MAPPING_A_Msk                                                                      (0x7FFFFUL << AON_REG_TMETER_MAPPING_TMETER_MAPPING_A_Pos)
+
+#define AON_REG_TMETER_MAPPING_RESERVED_Pos                                                                              30U
+#define AON_REG_TMETER_MAPPING_RESERVED_Msk                                                                              (0x3UL << AON_REG_TMETER_MAPPING_RESERVED_Pos)
+
+/* 0x768    0x4000_0768
+    0       R/W     RTC_CNT_START                                               1'b0
+    1       R/W     RTC_CNT_RST                                                 1'b0
+    2       R/W     RTC_PRE_CNT_RST                                             1'b0
+    7:3     R       RTC_CR0_RESERVED7_3                                         5'b0
+    8       R/W     RTC_TICK_IE                                                 1'b0
+    9       R/W     RTC_CNT_OV_IE                                               1'b0
+    10      R/W     RTC_PRECMP_IE                                               1'b0
+    11      R/W     RTC_PRECMP_CMP3_IE                                          1'b0
+    15:12   R       RTC_CR0_RESERVED15_12                                       4'h0
+    16      R/W     RTC_CMP0_NV_IE                                              1'b0
+    17      R/W     RTC_CMP1_NV_IE                                              1'b0
+    18      R/W     RTC_CMP2_NV_IE                                              1'b0
+    19      R/W     RTC_CMP3_NV_IE                                              1'b0
+    20      R/W     RTC_CMP0_WK_IE                                              1'b0
+    21      R/W     RTC_CMP1_WK_IE                                              1'b0
+    22      R/W     RTC_CMP2_WK_IE                                              1'b0
+    23      R/W     RTC_CMP3_WK_IE                                              1'b0
+    28:24   R       RTC_CR0_RESERVED28_24                                       5'b0
+    29      R/W     RTC_WK_IE                                                   1'b0
+    30      R/W     RTC_NV_IE                                                   1'b0
+    31      R/W     RTC_RST                                                     1'b0
+ */
+typedef union _AON_REG_RTC_CR0_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RTC_CNT_START: 1;
+        uint32_t RTC_CNT_RST: 1;
+        uint32_t RTC_PRE_CNT_RST: 1;
+        uint32_t RTC_CR0_RESERVED7_3: 5;
+        uint32_t RTC_TICK_IE: 1;
+        uint32_t RTC_CNT_OV_IE: 1;
+        uint32_t RTC_PRECMP_IE: 1;
+        uint32_t RTC_PRECMP_CMP3_IE: 1;
+        uint32_t RTC_CR0_RESERVED15_12: 4;
+        uint32_t RTC_CMP0_NV_IE: 1;
+        uint32_t RTC_CMP1_NV_IE: 1;
+        uint32_t RTC_CMP2_NV_IE: 1;
+        uint32_t RTC_CMP3_NV_IE: 1;
+        uint32_t RTC_CMP0_WK_IE: 1;
+        uint32_t RTC_CMP1_WK_IE: 1;
+        uint32_t RTC_CMP2_WK_IE: 1;
+        uint32_t RTC_CMP3_WK_IE: 1;
+        uint32_t RTC_CR0_RESERVED28_24: 5;
+        uint32_t RTC_WK_IE: 1;
+        uint32_t RTC_NV_IE: 1;
+        uint32_t RTC_RST: 1;
+    };
+} AON_REG_RTC_CR0_TYPE;
+
+/*0x4000_0768 AON_REG_RTC_CR0*/
+#define AON_REG_RTC_CR0_RTC_CNT_START_Pos                                                                                0U
+#define AON_REG_RTC_CR0_RTC_CNT_START_Msk                                                                                (0x1UL << AON_REG_RTC_CR0_RTC_CNT_START_Pos)
+
+#define AON_REG_RTC_CR0_RTC_CNT_RST_Pos                                                                                  1U
+#define AON_REG_RTC_CR0_RTC_CNT_RST_Msk                                                                                  (0x1UL << AON_REG_RTC_CR0_RTC_CNT_RST_Pos)
+
+#define AON_REG_RTC_CR0_RTC_PRE_CNT_RST_Pos                                                                              2U
+#define AON_REG_RTC_CR0_RTC_PRE_CNT_RST_Msk                                                                              (0x1UL << AON_REG_RTC_CR0_RTC_PRE_CNT_RST_Pos)
+
+#define AON_REG_RTC_CR0_RTC_CR0_RESERVED7_3_Pos                                                                          3U
+#define AON_REG_RTC_CR0_RTC_CR0_RESERVED7_3_Msk                                                                          (0x1FUL << AON_REG_RTC_CR0_RTC_CR0_RESERVED7_3_Pos)
+
+#define AON_REG_RTC_CR0_RTC_TICK_IE_Pos                                                                                  8U
+#define AON_REG_RTC_CR0_RTC_TICK_IE_Msk                                                                                  (0x1UL << AON_REG_RTC_CR0_RTC_TICK_IE_Pos)
+
+#define AON_REG_RTC_CR0_RTC_CNT_OV_IE_Pos                                                                                9U
+#define AON_REG_RTC_CR0_RTC_CNT_OV_IE_Msk                                                                                (0x1UL << AON_REG_RTC_CR0_RTC_CNT_OV_IE_Pos)
+
+#define AON_REG_RTC_CR0_RTC_PRECMP_IE_Pos                                                                                10U
+#define AON_REG_RTC_CR0_RTC_PRECMP_IE_Msk                                                                                (0x1UL << AON_REG_RTC_CR0_RTC_PRECMP_IE_Pos)
+
+#define AON_REG_RTC_CR0_RTC_PRECMP_CMP3_IE_Pos                                                                           11U
+#define AON_REG_RTC_CR0_RTC_PRECMP_CMP3_IE_Msk                                                                           (0x1UL << AON_REG_RTC_CR0_RTC_PRECMP_CMP3_IE_Pos)
+
+#define AON_REG_RTC_CR0_RTC_CR0_RESERVED15_12_Pos                                                                        12U
+#define AON_REG_RTC_CR0_RTC_CR0_RESERVED15_12_Msk                                                                        (0xFUL << AON_REG_RTC_CR0_RTC_CR0_RESERVED15_12_Pos)
+
+#define AON_REG_RTC_CR0_RTC_CMP0_NV_IE_Pos                                                                               16U
+#define AON_REG_RTC_CR0_RTC_CMP0_NV_IE_Msk                                                                               (0x1UL << AON_REG_RTC_CR0_RTC_CMP0_NV_IE_Pos)
+
+#define AON_REG_RTC_CR0_RTC_CMP1_NV_IE_Pos                                                                               17U
+#define AON_REG_RTC_CR0_RTC_CMP1_NV_IE_Msk                                                                               (0x1UL << AON_REG_RTC_CR0_RTC_CMP1_NV_IE_Pos)
+
+#define AON_REG_RTC_CR0_RTC_CMP2_NV_IE_Pos                                                                               18U
+#define AON_REG_RTC_CR0_RTC_CMP2_NV_IE_Msk                                                                               (0x1UL << AON_REG_RTC_CR0_RTC_CMP2_NV_IE_Pos)
+
+#define AON_REG_RTC_CR0_RTC_CMP3_NV_IE_Pos                                                                               19U
+#define AON_REG_RTC_CR0_RTC_CMP3_NV_IE_Msk                                                                               (0x1UL << AON_REG_RTC_CR0_RTC_CMP3_NV_IE_Pos)
+
+#define AON_REG_RTC_CR0_RTC_CMP0_WK_IE_Pos                                                                               20U
+#define AON_REG_RTC_CR0_RTC_CMP0_WK_IE_Msk                                                                               (0x1UL << AON_REG_RTC_CR0_RTC_CMP0_WK_IE_Pos)
+
+#define AON_REG_RTC_CR0_RTC_CMP1_WK_IE_Pos                                                                               21U
+#define AON_REG_RTC_CR0_RTC_CMP1_WK_IE_Msk                                                                               (0x1UL << AON_REG_RTC_CR0_RTC_CMP1_WK_IE_Pos)
+
+#define AON_REG_RTC_CR0_RTC_CMP2_WK_IE_Pos                                                                               22U
+#define AON_REG_RTC_CR0_RTC_CMP2_WK_IE_Msk                                                                               (0x1UL << AON_REG_RTC_CR0_RTC_CMP2_WK_IE_Pos)
+
+#define AON_REG_RTC_CR0_RTC_CMP3_WK_IE_Pos                                                                               23U
+#define AON_REG_RTC_CR0_RTC_CMP3_WK_IE_Msk                                                                               (0x1UL << AON_REG_RTC_CR0_RTC_CMP3_WK_IE_Pos)
+
+#define AON_REG_RTC_CR0_RTC_CR0_RESERVED28_24_Pos                                                                        24U
+#define AON_REG_RTC_CR0_RTC_CR0_RESERVED28_24_Msk                                                                        (0x1FUL << AON_REG_RTC_CR0_RTC_CR0_RESERVED28_24_Pos)
+
+#define AON_REG_RTC_CR0_RTC_WK_IE_Pos                                                                                    29U
+#define AON_REG_RTC_CR0_RTC_WK_IE_Msk                                                                                    (0x1UL << AON_REG_RTC_CR0_RTC_WK_IE_Pos)
+
+#define AON_REG_RTC_CR0_RTC_NV_IE_Pos                                                                                    30U
+#define AON_REG_RTC_CR0_RTC_NV_IE_Msk                                                                                    (0x1UL << AON_REG_RTC_CR0_RTC_NV_IE_Pos)
+
+#define AON_REG_RTC_CR0_RTC_RST_Pos                                                                                      31U
+#define AON_REG_RTC_CR0_RTC_RST_Msk                                                                                      (0x1UL << AON_REG_RTC_CR0_RTC_RST_Pos)
+
+/* 0x76C    0x4000_076c
+    0       R/WAC   RTC_TICK_CLR                                                1'b0
+    1       R/WAC   RTC_CNT_OV_CLR                                              1'b0
+    2       R/WAC   RTC_PRECMP_CLR                                              1'b0
+    3       R/WAC   RTC_PRECMP_CMP3_CLR                                         1'b0
+    7:4     R       RTC_INT_CLEAR_RESERVED7_4                                   4'h0
+    8       R/WAC   RTC_CMP0_NV_CLR                                             1'b0
+    9       R/WAC   RTC_CMP1_NV_CLR                                             1'b0
+    10      R/WAC   RTC_CMP2_NV_CLR                                             1'b0
+    11      R/WAC   RTC_CMP3_NV_CLR                                             1'b0
+    12      R/WAC   RTC_CMP0_WK_CLR                                             1'b0
+    13      R/WAC   RTC_CMP1_WK_CLR                                             1'b0
+    14      R/WAC   RTC_CMP2_WK_CLR                                             1'b0
+    15      R/WAC   RTC_CMP3_WK_CLR                                             1'b0
+    31:16   R       RTC_INT_CLEAR_RESERVED31_16                                 16'b0
+ */
+typedef union _AON_REG_RTC_INT_clear_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RTC_TICK_CLR: 1;
+        uint32_t RTC_CNT_OV_CLR: 1;
+        uint32_t RTC_PRECMP_CLR: 1;
+        uint32_t RTC_PRECMP_CMP3_CLR: 1;
+        uint32_t RTC_INT_CLEAR_RESERVED7_4: 4;
+        uint32_t RTC_CMP0_NV_CLR: 1;
+        uint32_t RTC_CMP1_NV_CLR: 1;
+        uint32_t RTC_CMP2_NV_CLR: 1;
+        uint32_t RTC_CMP3_NV_CLR: 1;
+        uint32_t RTC_CMP0_WK_CLR: 1;
+        uint32_t RTC_CMP1_WK_CLR: 1;
+        uint32_t RTC_CMP2_WK_CLR: 1;
+        uint32_t RTC_CMP3_WK_CLR: 1;
+        uint32_t RTC_INT_CLEAR_RESERVED31_16: 16;
+    };
+} AON_REG_RTC_INT_clear_TYPE;
+
+/*0x4000_076c AON_REG_RTC_INT_clear*/
+#define AON_REG_RTC_INT_clear_RTC_TICK_CLR_Pos                                                                           0U
+#define AON_REG_RTC_INT_clear_RTC_TICK_CLR_Msk                                                                           (0x1UL << AON_REG_RTC_INT_clear_RTC_TICK_CLR_Pos)
+
+#define AON_REG_RTC_INT_clear_RTC_CNT_OV_CLR_Pos                                                                         1U
+#define AON_REG_RTC_INT_clear_RTC_CNT_OV_CLR_Msk                                                                         (0x1UL << AON_REG_RTC_INT_clear_RTC_CNT_OV_CLR_Pos)
+
+#define AON_REG_RTC_INT_clear_RTC_PRECMP_CLR_Pos                                                                         2U
+#define AON_REG_RTC_INT_clear_RTC_PRECMP_CLR_Msk                                                                         (0x1UL << AON_REG_RTC_INT_clear_RTC_PRECMP_CLR_Pos)
+
+#define AON_REG_RTC_INT_clear_RTC_PRECMP_CMP3_CLR_Pos                                                                    3U
+#define AON_REG_RTC_INT_clear_RTC_PRECMP_CMP3_CLR_Msk                                                                    (0x1UL << AON_REG_RTC_INT_clear_RTC_PRECMP_CMP3_CLR_Pos)
+
+#define AON_REG_RTC_INT_clear_RTC_INT_CLEAR_RESERVED7_4_Pos                                                              4U
+#define AON_REG_RTC_INT_clear_RTC_INT_CLEAR_RESERVED7_4_Msk                                                              (0xFUL << AON_REG_RTC_INT_clear_RTC_INT_CLEAR_RESERVED7_4_Pos)
+
+#define AON_REG_RTC_INT_clear_RTC_CMP0_NV_CLR_Pos                                                                        8U
+#define AON_REG_RTC_INT_clear_RTC_CMP0_NV_CLR_Msk                                                                        (0x1UL << AON_REG_RTC_INT_clear_RTC_CMP0_NV_CLR_Pos)
+
+#define AON_REG_RTC_INT_clear_RTC_CMP1_NV_CLR_Pos                                                                        9U
+#define AON_REG_RTC_INT_clear_RTC_CMP1_NV_CLR_Msk                                                                        (0x1UL << AON_REG_RTC_INT_clear_RTC_CMP1_NV_CLR_Pos)
+
+#define AON_REG_RTC_INT_clear_RTC_CMP2_NV_CLR_Pos                                                                        10U
+#define AON_REG_RTC_INT_clear_RTC_CMP2_NV_CLR_Msk                                                                        (0x1UL << AON_REG_RTC_INT_clear_RTC_CMP2_NV_CLR_Pos)
+
+#define AON_REG_RTC_INT_clear_RTC_CMP3_NV_CLR_Pos                                                                        11U
+#define AON_REG_RTC_INT_clear_RTC_CMP3_NV_CLR_Msk                                                                        (0x1UL << AON_REG_RTC_INT_clear_RTC_CMP3_NV_CLR_Pos)
+
+#define AON_REG_RTC_INT_clear_RTC_CMP0_WK_CLR_Pos                                                                        12U
+#define AON_REG_RTC_INT_clear_RTC_CMP0_WK_CLR_Msk                                                                        (0x1UL << AON_REG_RTC_INT_clear_RTC_CMP0_WK_CLR_Pos)
+
+#define AON_REG_RTC_INT_clear_RTC_CMP1_WK_CLR_Pos                                                                        13U
+#define AON_REG_RTC_INT_clear_RTC_CMP1_WK_CLR_Msk                                                                        (0x1UL << AON_REG_RTC_INT_clear_RTC_CMP1_WK_CLR_Pos)
+
+#define AON_REG_RTC_INT_clear_RTC_CMP2_WK_CLR_Pos                                                                        14U
+#define AON_REG_RTC_INT_clear_RTC_CMP2_WK_CLR_Msk                                                                        (0x1UL << AON_REG_RTC_INT_clear_RTC_CMP2_WK_CLR_Pos)
+
+#define AON_REG_RTC_INT_clear_RTC_CMP3_WK_CLR_Pos                                                                        15U
+#define AON_REG_RTC_INT_clear_RTC_CMP3_WK_CLR_Msk                                                                        (0x1UL << AON_REG_RTC_INT_clear_RTC_CMP3_WK_CLR_Pos)
+
+#define AON_REG_RTC_INT_clear_RTC_INT_CLEAR_RESERVED31_16_Pos                                                            16U
+#define AON_REG_RTC_INT_clear_RTC_INT_CLEAR_RESERVED31_16_Msk                                                            (0xFFFFUL << AON_REG_RTC_INT_clear_RTC_INT_CLEAR_RESERVED31_16_Pos)
+
+/* 0x770    0x4000_0770
+    0       R       RTC_TICK_SR                                                 1'b0
+    1       R       RTC_CNT_OV_SR                                               1'b0
+    2       R       RTC_PRECMP_SR                                               1'b0
+    3       R       RTC_PRECMP_CMP3_SR                                          1'b0
+    7:4     R       RTC_INT_SR_RESERVED7_4                                      4'h0
+    8       R       RTC_CMP0_NV_SR                                              1'b0
+    9       R       RTC_CMP1_NV_SR                                              1'b0
+    10      R       RTC_CMP2_NV_SR                                              1'b0
+    11      R       RTC_CMP3_NV_SR                                              1'b0
+    12      R       RTC_CMP0_WK_SR                                              1'b0
+    13      R       RTC_CMP1_WK_SR                                              1'b0
+    14      R       RTC_CMP2_WK_SR                                              1'b0
+    15      R       RTC_CMP3_WK_SR                                              1'b0
+    31:16   R       RTC_INT_SR_RESERVED31_16                                    16'b0
+ */
+typedef union _AON_REG_RTC_INT_SR_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RTC_TICK_SR: 1;
+        uint32_t RTC_CNT_OV_SR: 1;
+        uint32_t RTC_PRECMP_SR: 1;
+        uint32_t RTC_PRECMP_CMP3_SR: 1;
+        uint32_t RTC_INT_SR_RESERVED7_4: 4;
+        uint32_t RTC_CMP0_NV_SR: 1;
+        uint32_t RTC_CMP1_NV_SR: 1;
+        uint32_t RTC_CMP2_NV_SR: 1;
+        uint32_t RTC_CMP3_NV_SR: 1;
+        uint32_t RTC_CMP0_WK_SR: 1;
+        uint32_t RTC_CMP1_WK_SR: 1;
+        uint32_t RTC_CMP2_WK_SR: 1;
+        uint32_t RTC_CMP3_WK_SR: 1;
+        uint32_t RTC_INT_SR_RESERVED31_16: 16;
+    };
+} AON_REG_RTC_INT_SR_TYPE;
+
+/*0x4000_0770 AON_REG_RTC_INT_SR*/
+#define AON_REG_RTC_INT_SR_RTC_TICK_SR_Pos                                                                               0U
+#define AON_REG_RTC_INT_SR_RTC_TICK_SR_Msk                                                                               (0x1UL << AON_REG_RTC_INT_SR_RTC_TICK_SR_Pos)
+
+#define AON_REG_RTC_INT_SR_RTC_CNT_OV_SR_Pos                                                                             1U
+#define AON_REG_RTC_INT_SR_RTC_CNT_OV_SR_Msk                                                                             (0x1UL << AON_REG_RTC_INT_SR_RTC_CNT_OV_SR_Pos)
+
+#define AON_REG_RTC_INT_SR_RTC_PRECMP_SR_Pos                                                                             2U
+#define AON_REG_RTC_INT_SR_RTC_PRECMP_SR_Msk                                                                             (0x1UL << AON_REG_RTC_INT_SR_RTC_PRECMP_SR_Pos)
+
+#define AON_REG_RTC_INT_SR_RTC_PRECMP_CMP3_SR_Pos                                                                        3U
+#define AON_REG_RTC_INT_SR_RTC_PRECMP_CMP3_SR_Msk                                                                        (0x1UL << AON_REG_RTC_INT_SR_RTC_PRECMP_CMP3_SR_Pos)
+
+#define AON_REG_RTC_INT_SR_RTC_INT_SR_RESERVED7_4_Pos                                                                    4U
+#define AON_REG_RTC_INT_SR_RTC_INT_SR_RESERVED7_4_Msk                                                                    (0xFUL << AON_REG_RTC_INT_SR_RTC_INT_SR_RESERVED7_4_Pos)
+
+#define AON_REG_RTC_INT_SR_RTC_CMP0_NV_SR_Pos                                                                            8U
+#define AON_REG_RTC_INT_SR_RTC_CMP0_NV_SR_Msk                                                                            (0x1UL << AON_REG_RTC_INT_SR_RTC_CMP0_NV_SR_Pos)
+
+#define AON_REG_RTC_INT_SR_RTC_CMP1_NV_SR_Pos                                                                            9U
+#define AON_REG_RTC_INT_SR_RTC_CMP1_NV_SR_Msk                                                                            (0x1UL << AON_REG_RTC_INT_SR_RTC_CMP1_NV_SR_Pos)
+
+#define AON_REG_RTC_INT_SR_RTC_CMP2_NV_SR_Pos                                                                            10U
+#define AON_REG_RTC_INT_SR_RTC_CMP2_NV_SR_Msk                                                                            (0x1UL << AON_REG_RTC_INT_SR_RTC_CMP2_NV_SR_Pos)
+
+#define AON_REG_RTC_INT_SR_RTC_CMP3_NV_SR_Pos                                                                            11U
+#define AON_REG_RTC_INT_SR_RTC_CMP3_NV_SR_Msk                                                                            (0x1UL << AON_REG_RTC_INT_SR_RTC_CMP3_NV_SR_Pos)
+
+#define AON_REG_RTC_INT_SR_RTC_CMP0_WK_SR_Pos                                                                            12U
+#define AON_REG_RTC_INT_SR_RTC_CMP0_WK_SR_Msk                                                                            (0x1UL << AON_REG_RTC_INT_SR_RTC_CMP0_WK_SR_Pos)
+
+#define AON_REG_RTC_INT_SR_RTC_CMP1_WK_SR_Pos                                                                            13U
+#define AON_REG_RTC_INT_SR_RTC_CMP1_WK_SR_Msk                                                                            (0x1UL << AON_REG_RTC_INT_SR_RTC_CMP1_WK_SR_Pos)
+
+#define AON_REG_RTC_INT_SR_RTC_CMP2_WK_SR_Pos                                                                            14U
+#define AON_REG_RTC_INT_SR_RTC_CMP2_WK_SR_Msk                                                                            (0x1UL << AON_REG_RTC_INT_SR_RTC_CMP2_WK_SR_Pos)
+
+#define AON_REG_RTC_INT_SR_RTC_CMP3_WK_SR_Pos                                                                            15U
+#define AON_REG_RTC_INT_SR_RTC_CMP3_WK_SR_Msk                                                                            (0x1UL << AON_REG_RTC_INT_SR_RTC_CMP3_WK_SR_Pos)
+
+#define AON_REG_RTC_INT_SR_RTC_INT_SR_RESERVED31_16_Pos                                                                  16U
+#define AON_REG_RTC_INT_SR_RTC_INT_SR_RESERVED31_16_Msk                                                                  (0xFFFFUL << AON_REG_RTC_INT_SR_RTC_INT_SR_RESERVED31_16_Pos)
+
+/* 0x774    0x4000_0774
+    11:0    R/W     RTC_PRESCALER                                               12'b0
+    31:12   R       RTC_PRESCALER_RESERVED31_12                                 20'b0
+ */
+typedef union _AON_REG_RTC_PRESCALER_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RTC_PRESCALER: 12;
+        uint32_t RTC_PRESCALER_RESERVED31_12: 20;
+    };
+} AON_REG_RTC_PRESCALER_TYPE;
+
+/*0x4000_0774 AON_REG_RTC_PRESCALER*/
+#define AON_REG_RTC_PRESCALER_RTC_PRESCALER_Pos                                                                          0U
+#define AON_REG_RTC_PRESCALER_RTC_PRESCALER_Msk                                                                          (0xFFFUL << AON_REG_RTC_PRESCALER_RTC_PRESCALER_Pos)
+
+#define AON_REG_RTC_PRESCALER_RTC_PRESCALER_RESERVED31_12_Pos                                                            12U
+#define AON_REG_RTC_PRESCALER_RTC_PRESCALER_RESERVED31_12_Msk                                                            (0xFFFFFUL << AON_REG_RTC_PRESCALER_RTC_PRESCALER_RESERVED31_12_Pos)
+
+/* 0x778    0x4000_0778
+    31:0    R/W     RTC_CMP0                                                    32'b0
+ */
+typedef union _AON_REG_RTC_COMP_0_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RTC_CMP0;
+    };
+} AON_REG_RTC_COMP_0_TYPE;
+
+/*0x4000_0778 AON_REG_RTC_COMP_0*/
+#define AON_REG_RTC_COMP_0_RTC_CMP0_Pos                                                                                  0U
+#define AON_REG_RTC_COMP_0_RTC_CMP0_Msk                                                                                  (0xFFFFFFFFUL << AON_REG_RTC_COMP_0_RTC_CMP0_Pos)
+
+/* 0x77C    0x4000_077c
+    31:0    R/W     RTC_CMP1                                                    32'b0
+ */
+typedef union _AON_REG_RTC_COMP_1_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RTC_CMP1;
+    };
+} AON_REG_RTC_COMP_1_TYPE;
+
+/*0x4000_077c AON_REG_RTC_COMP_1*/
+#define AON_REG_RTC_COMP_1_RTC_CMP1_Pos                                                                                  0U
+#define AON_REG_RTC_COMP_1_RTC_CMP1_Msk                                                                                  (0xFFFFFFFFUL << AON_REG_RTC_COMP_1_RTC_CMP1_Pos)
+
+/* 0x780    0x4000_0780
+    31:0    R/W     RTC_CMP2                                                    32'b0
+ */
+typedef union _AON_REG_RTC_COMP_2_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RTC_CMP2;
+    };
+} AON_REG_RTC_COMP_2_TYPE;
+
+/*0x4000_0780 AON_REG_RTC_COMP_2*/
+#define AON_REG_RTC_COMP_2_RTC_CMP2_Pos                                                                                  0U
+#define AON_REG_RTC_COMP_2_RTC_CMP2_Msk                                                                                  (0xFFFFFFFFUL << AON_REG_RTC_COMP_2_RTC_CMP2_Pos)
+
+/* 0x784    0x4000_0784
+    31:0    R/W     RTC_CMP3                                                    32'b0
+ */
+typedef union _AON_REG_RTC_COMP_3_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RTC_CMP3;
+    };
+} AON_REG_RTC_COMP_3_TYPE;
+
+/*0x4000_0784 AON_REG_RTC_COMP_3*/
+#define AON_REG_RTC_COMP_3_RTC_CMP3_Pos                                                                                  0U
+#define AON_REG_RTC_COMP_3_RTC_CMP3_Msk                                                                                  (0xFFFFFFFFUL << AON_REG_RTC_COMP_3_RTC_CMP3_Pos)
+
+/* 0x788    0x4000_0788
+    31:0    R       RTC_CNT                                                     32'b0
+ */
+typedef union _AON_REG_RTC_CNT0_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RTC_CNT;
+    };
+} AON_REG_RTC_CNT0_TYPE;
+
+/*0x4000_0788 AON_REG_RTC_CNT0*/
+#define AON_REG_RTC_CNT0_RTC_CNT_Pos                                                                                     0U
+#define AON_REG_RTC_CNT0_RTC_CNT_Msk                                                                                     (0xFFFFFFFFUL << AON_REG_RTC_CNT0_RTC_CNT_Pos)
+
+/* 0x78C    0x4000_078c
+    11:0    R       RTC_PRESCALE_CNT                                            12'b0
+    31:12   R       RTC_PRESCALER_CNT0_RESERVED31_12                            20'b0
+ */
+typedef union _AON_REG_RTC_PRESCALE_CNT0_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RTC_PRESCALE_CNT: 12;
+        uint32_t RTC_PRESCALER_CNT0_RESERVED31_12: 20;
+    };
+} AON_REG_RTC_PRESCALE_CNT0_TYPE;
+
+/*0x4000_078c AON_REG_RTC_PRESCALE_CNT0*/
+#define AON_REG_RTC_PRESCALE_CNT0_RTC_PRESCALE_CNT_Pos                                                                   0U
+#define AON_REG_RTC_PRESCALE_CNT0_RTC_PRESCALE_CNT_Msk                                                                   (0xFFFUL << AON_REG_RTC_PRESCALE_CNT0_RTC_PRESCALE_CNT_Pos)
+
+#define AON_REG_RTC_PRESCALE_CNT0_RTC_PRESCALER_CNT0_RESERVED31_12_Pos                                                   12U
+#define AON_REG_RTC_PRESCALE_CNT0_RTC_PRESCALER_CNT0_RESERVED31_12_Msk                                                   (0xFFFFFUL << AON_REG_RTC_PRESCALE_CNT0_RTC_PRESCALER_CNT0_RESERVED31_12_Pos)
+
+/* 0x790    0x4000_0790
+    11:0    R/W     RTC_PRESCALE_CMP                                            12'b0
+    31:12   R       RTC_PRESCALER_CMP0_RESERVED31_12                            20'b0
+ */
+typedef union _AON_REG_RTC_PRESCALE_CMP0_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RTC_PRESCALE_CMP: 12;
+        uint32_t RTC_PRESCALER_CMP0_RESERVED31_12: 20;
+    };
+} AON_REG_RTC_PRESCALE_CMP0_TYPE;
+
+/*0x4000_0790 AON_REG_RTC_PRESCALE_CMP0*/
+#define AON_REG_RTC_PRESCALE_CMP0_RTC_PRESCALE_CMP_Pos                                                                   0U
+#define AON_REG_RTC_PRESCALE_CMP0_RTC_PRESCALE_CMP_Msk                                                                   (0xFFFUL << AON_REG_RTC_PRESCALE_CMP0_RTC_PRESCALE_CMP_Pos)
+
+#define AON_REG_RTC_PRESCALE_CMP0_RTC_PRESCALER_CMP0_RESERVED31_12_Pos                                                   12U
+#define AON_REG_RTC_PRESCALE_CMP0_RTC_PRESCALER_CMP0_RESERVED31_12_Msk                                                   (0xFFFFFUL << AON_REG_RTC_PRESCALE_CMP0_RTC_PRESCALER_CMP0_RESERVED31_12_Pos)
+
+/* 0x794    0x4000_0794
+    31:0    R/W     RTC_BACKUP                                                  32'b0
+ */
+typedef union _AON_REG_RTC_BACKUP_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RTC_BACKUP;
+    };
+} AON_REG_RTC_BACKUP_TYPE;
+
+/*0x4000_0794 AON_REG_RTC_BACKUP*/
+#define AON_REG_RTC_BACKUP_RTC_BACKUP_Pos                                                                                0U
+#define AON_REG_RTC_BACKUP_RTC_BACKUP_Msk                                                                                (0xFFFFFFFFUL << AON_REG_RTC_BACKUP_RTC_BACKUP_Pos)
+
+/* 0x798    0x4000_0798
+    31:0    R       RTC_RTL_VERSION                                             32'h20240402
+ */
+typedef union _AON_REG_RTC_RTL_VERSION0_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RTC_RTL_VERSION;
+    };
+} AON_REG_RTC_RTL_VERSION0_TYPE;
+
+/*0x4000_0798 AON_REG_RTC_RTL_VERSION0*/
+#define AON_REG_RTC_RTL_VERSION0_RTC_RTL_VERSION_Pos                                                                     0U
+#define AON_REG_RTC_RTL_VERSION0_RTC_RTL_VERSION_Msk                                                                     (0xFFFFFFFFUL << AON_REG_RTC_RTL_VERSION0_RTC_RTL_VERSION_Pos)
+
+/* 0x79C    0x4000_079c
+    0       R/W     RTC_CMP0_RELOAD_EN                                          1'h0
+    1       R/W     RTC_CMP1_RELOAD_EN                                          1'h0
+    2       R/W     RTC_CMP2_RELOAD_EN                                          1'h0
+    3       R/W     RTC_CMP3_RELOAD_EN                                          1'h0
+    31:4    R       RTC_QACTIVE_CTRL_RESERVED31_4                               28'h0
+ */
+typedef union _AON_REG_RTC_RELOAD_CTRL_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RTC_CMP0_RELOAD_EN: 1;
+        uint32_t RTC_CMP1_RELOAD_EN: 1;
+        uint32_t RTC_CMP2_RELOAD_EN: 1;
+        uint32_t RTC_CMP3_RELOAD_EN: 1;
+        uint32_t RTC_QACTIVE_CTRL_RESERVED31_4: 28;
+    };
+} AON_REG_RTC_RELOAD_CTRL_TYPE;
+
+/*0x4000_079c AON_REG_RTC_RELOAD_CTRL*/
+#define AON_REG_RTC_RELOAD_CTRL_RTC_CMP0_RELOAD_EN_Pos                                                                   0U
+#define AON_REG_RTC_RELOAD_CTRL_RTC_CMP0_RELOAD_EN_Msk                                                                   (0x1UL << AON_REG_RTC_RELOAD_CTRL_RTC_CMP0_RELOAD_EN_Pos)
+
+#define AON_REG_RTC_RELOAD_CTRL_RTC_CMP1_RELOAD_EN_Pos                                                                   1U
+#define AON_REG_RTC_RELOAD_CTRL_RTC_CMP1_RELOAD_EN_Msk                                                                   (0x1UL << AON_REG_RTC_RELOAD_CTRL_RTC_CMP1_RELOAD_EN_Pos)
+
+#define AON_REG_RTC_RELOAD_CTRL_RTC_CMP2_RELOAD_EN_Pos                                                                   2U
+#define AON_REG_RTC_RELOAD_CTRL_RTC_CMP2_RELOAD_EN_Msk                                                                   (0x1UL << AON_REG_RTC_RELOAD_CTRL_RTC_CMP2_RELOAD_EN_Pos)
+
+#define AON_REG_RTC_RELOAD_CTRL_RTC_CMP3_RELOAD_EN_Pos                                                                   3U
+#define AON_REG_RTC_RELOAD_CTRL_RTC_CMP3_RELOAD_EN_Msk                                                                   (0x1UL << AON_REG_RTC_RELOAD_CTRL_RTC_CMP3_RELOAD_EN_Pos)
+
+#define AON_REG_RTC_RELOAD_CTRL_RTC_QACTIVE_CTRL_RESERVED31_4_Pos                                                        4U
+#define AON_REG_RTC_RELOAD_CTRL_RTC_QACTIVE_CTRL_RESERVED31_4_Msk                                                        (0xFFFFFFFUL << AON_REG_RTC_RELOAD_CTRL_RTC_QACTIVE_CTRL_RESERVED31_4_Pos)
+
+/* 0x7A0    0x4000_07a0
+    31:0    R/W     RTC_CMP0_RELOAD                                             32'b0
+ */
+typedef union _AON_REG_RTC_COMP_0_RELOAD_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RTC_CMP0_RELOAD;
+    };
+} AON_REG_RTC_COMP_0_RELOAD_TYPE;
+
+/*0x4000_07a0 AON_REG_RTC_COMP_0_RELOAD*/
+#define AON_REG_RTC_COMP_0_RELOAD_RTC_CMP0_RELOAD_Pos                                                                    0U
+#define AON_REG_RTC_COMP_0_RELOAD_RTC_CMP0_RELOAD_Msk                                                                    (0xFFFFFFFFUL << AON_REG_RTC_COMP_0_RELOAD_RTC_CMP0_RELOAD_Pos)
+
+/* 0x7A4    0x4000_07a4
+    31:0    R/W     RTC_CMP1_RELOAD                                             32'b0
+ */
+typedef union _AON_REG_RTC_COMP_1_RELOAD_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RTC_CMP1_RELOAD;
+    };
+} AON_REG_RTC_COMP_1_RELOAD_TYPE;
+
+/*0x4000_07a4 AON_REG_RTC_COMP_1_RELOAD*/
+#define AON_REG_RTC_COMP_1_RELOAD_RTC_CMP1_RELOAD_Pos                                                                    0U
+#define AON_REG_RTC_COMP_1_RELOAD_RTC_CMP1_RELOAD_Msk                                                                    (0xFFFFFFFFUL << AON_REG_RTC_COMP_1_RELOAD_RTC_CMP1_RELOAD_Pos)
+
+/* 0x7A8    0x4000_07a8
+    31:0    R/W     RTC_CMP2_RELOAD                                             32'b0
+ */
+typedef union _AON_REG_RTC_COMP_2_RELOAD_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RTC_CMP2_RELOAD;
+    };
+} AON_REG_RTC_COMP_2_RELOAD_TYPE;
+
+/*0x4000_07a8 AON_REG_RTC_COMP_2_RELOAD*/
+#define AON_REG_RTC_COMP_2_RELOAD_RTC_CMP2_RELOAD_Pos                                                                    0U
+#define AON_REG_RTC_COMP_2_RELOAD_RTC_CMP2_RELOAD_Msk                                                                    (0xFFFFFFFFUL << AON_REG_RTC_COMP_2_RELOAD_RTC_CMP2_RELOAD_Pos)
+
+/* 0x7AC    0x4000_07ac
+    31:0    R/W     RTC_CMP3_RELOAD                                             32'b0
+ */
+typedef union _AON_REG_RTC_COMP_3_RELOAD_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RTC_CMP3_RELOAD;
+    };
+} AON_REG_RTC_COMP_3_RELOAD_TYPE;
+
+/*0x4000_07ac AON_REG_RTC_COMP_3_RELOAD*/
+#define AON_REG_RTC_COMP_3_RELOAD_RTC_CMP3_RELOAD_Pos                                                                    0U
+#define AON_REG_RTC_COMP_3_RELOAD_RTC_CMP3_RELOAD_Msk                                                                    (0xFFFFFFFFUL << AON_REG_RTC_COMP_3_RELOAD_RTC_CMP3_RELOAD_Pos)
+
+/* 0x7B0    0x4000_07b0
+    0       R/W     RTC_RAP_MODE                                                1'h0
+    1       R/WAC   RTC_FW_TASK_START                                           1'h0
+    2       R/WAC   RTC_FW_TASK_STOP                                            1'h0
+    3       R/WAC   RTC_FW_TASK_CLEAR                                           1'h0
+    4       R/WAC   RTC_FW_TASK_RELOAD_CMP0                                     1'h0
+    5       R/WAC   RTC_FW_TASK_RELOAD_CMP1                                     1'h0
+    6       R/WAC   RTC_FW_TASK_RELOAD_CMP2                                     1'h0
+    7       R/WAC   RTC_FW_TASK_RELOAD_CMP3                                     1'h0
+    31:8    R       RTC_TASK_CTRL_RESERVED31_8                                  24'h0
+ */
+typedef union _AON_REG_RTC_TASK_CTRL_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RTC_RAP_MODE: 1;
+        uint32_t RTC_FW_TASK_START: 1;
+        uint32_t RTC_FW_TASK_STOP: 1;
+        uint32_t RTC_FW_TASK_CLEAR: 1;
+        uint32_t RTC_FW_TASK_RELOAD_CMP0: 1;
+        uint32_t RTC_FW_TASK_RELOAD_CMP1: 1;
+        uint32_t RTC_FW_TASK_RELOAD_CMP2: 1;
+        uint32_t RTC_FW_TASK_RELOAD_CMP3: 1;
+        uint32_t RTC_TASK_CTRL_RESERVED31_8: 24;
+    };
+} AON_REG_RTC_TASK_CTRL_TYPE;
+
+/*0x4000_07b0 AON_REG_RTC_TASK_CTRL*/
+#define AON_REG_RTC_TASK_CTRL_RTC_RAP_MODE_Pos                                                                           0U
+#define AON_REG_RTC_TASK_CTRL_RTC_RAP_MODE_Msk                                                                           (0x1UL << AON_REG_RTC_TASK_CTRL_RTC_RAP_MODE_Pos)
+
+#define AON_REG_RTC_TASK_CTRL_RTC_FW_TASK_START_Pos                                                                      1U
+#define AON_REG_RTC_TASK_CTRL_RTC_FW_TASK_START_Msk                                                                      (0x1UL << AON_REG_RTC_TASK_CTRL_RTC_FW_TASK_START_Pos)
+
+#define AON_REG_RTC_TASK_CTRL_RTC_FW_TASK_STOP_Pos                                                                       2U
+#define AON_REG_RTC_TASK_CTRL_RTC_FW_TASK_STOP_Msk                                                                       (0x1UL << AON_REG_RTC_TASK_CTRL_RTC_FW_TASK_STOP_Pos)
+
+#define AON_REG_RTC_TASK_CTRL_RTC_FW_TASK_CLEAR_Pos                                                                      3U
+#define AON_REG_RTC_TASK_CTRL_RTC_FW_TASK_CLEAR_Msk                                                                      (0x1UL << AON_REG_RTC_TASK_CTRL_RTC_FW_TASK_CLEAR_Pos)
+
+#define AON_REG_RTC_TASK_CTRL_RTC_FW_TASK_RELOAD_CMP0_Pos                                                                4U
+#define AON_REG_RTC_TASK_CTRL_RTC_FW_TASK_RELOAD_CMP0_Msk                                                                (0x1UL << AON_REG_RTC_TASK_CTRL_RTC_FW_TASK_RELOAD_CMP0_Pos)
+
+#define AON_REG_RTC_TASK_CTRL_RTC_FW_TASK_RELOAD_CMP1_Pos                                                                5U
+#define AON_REG_RTC_TASK_CTRL_RTC_FW_TASK_RELOAD_CMP1_Msk                                                                (0x1UL << AON_REG_RTC_TASK_CTRL_RTC_FW_TASK_RELOAD_CMP1_Pos)
+
+#define AON_REG_RTC_TASK_CTRL_RTC_FW_TASK_RELOAD_CMP2_Pos                                                                6U
+#define AON_REG_RTC_TASK_CTRL_RTC_FW_TASK_RELOAD_CMP2_Msk                                                                (0x1UL << AON_REG_RTC_TASK_CTRL_RTC_FW_TASK_RELOAD_CMP2_Pos)
+
+#define AON_REG_RTC_TASK_CTRL_RTC_FW_TASK_RELOAD_CMP3_Pos                                                                7U
+#define AON_REG_RTC_TASK_CTRL_RTC_FW_TASK_RELOAD_CMP3_Msk                                                                (0x1UL << AON_REG_RTC_TASK_CTRL_RTC_FW_TASK_RELOAD_CMP3_Pos)
+
+#define AON_REG_RTC_TASK_CTRL_RTC_TASK_CTRL_RESERVED31_8_Pos                                                             8U
+#define AON_REG_RTC_TASK_CTRL_RTC_TASK_CTRL_RESERVED31_8_Msk                                                             (0xFFFFFFUL << AON_REG_RTC_TASK_CTRL_RTC_TASK_CTRL_RESERVED31_8_Pos)
+
+/* 0x7B4    0x4000_07b4
+    0       R/W     RTC_TASK_STOP_SUB_EN                                        1'h0
+    1       R/W     RTC_TASK_CLEAR_SUB_EN                                       1'h0
+    2       R/W     RTC_TASK_RELOAD_CMP0_SUB_EN                                 1'h0
+    3       R/W     RTC_TASK_RELOAD_CMP1_SUB_EN                                 1'h0
+    4       R/W     RTC_TASK_RELOAD_CMP2_SUB_EN                                 1'h0
+    5       R/W     RTC_TASK_RELOAD_CMP3_SUB_EN                                 1'h0
+    15:6    R       RTC_SHOT_CTRL_RESERVED15_6                                  10'h0
+    16      R/W     RTC_EVENT_CMP0_PUB_EN                                       1'h0
+    17      R/W     RTC_EVENT_CMP1_PUB_EN                                       1'h0
+    18      R/W     RTC_EVENT_CMP2_PUB_EN                                       1'h0
+    19      R/W     RTC_EVENT_CMP3_PUB_EN                                       1'h0
+    31:20   R       RTC_SHOT_CTRL_RESERVED31_20                                 12'h0
+ */
+typedef union _AON_REG_RTC_SHOT_CTRL_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RTC_TASK_STOP_SUB_EN: 1;
+        uint32_t RTC_TASK_CLEAR_SUB_EN: 1;
+        uint32_t RTC_TASK_RELOAD_CMP0_SUB_EN: 1;
+        uint32_t RTC_TASK_RELOAD_CMP1_SUB_EN: 1;
+        uint32_t RTC_TASK_RELOAD_CMP2_SUB_EN: 1;
+        uint32_t RTC_TASK_RELOAD_CMP3_SUB_EN: 1;
+        uint32_t RTC_SHOT_CTRL_RESERVED15_6: 10;
+        uint32_t RTC_EVENT_CMP0_PUB_EN: 1;
+        uint32_t RTC_EVENT_CMP1_PUB_EN: 1;
+        uint32_t RTC_EVENT_CMP2_PUB_EN: 1;
+        uint32_t RTC_EVENT_CMP3_PUB_EN: 1;
+        uint32_t RTC_SHOT_CTRL_RESERVED31_20: 12;
+    };
+} AON_REG_RTC_SHOT_CTRL_TYPE;
+
+/*0x4000_07b4 AON_REG_RTC_SHOT_CTRL*/
+#define AON_REG_RTC_SHOT_CTRL_RTC_TASK_STOP_SUB_EN_Pos                                                                   0U
+#define AON_REG_RTC_SHOT_CTRL_RTC_TASK_STOP_SUB_EN_Msk                                                                   (0x1UL << AON_REG_RTC_SHOT_CTRL_RTC_TASK_STOP_SUB_EN_Pos)
+
+#define AON_REG_RTC_SHOT_CTRL_RTC_TASK_CLEAR_SUB_EN_Pos                                                                  1U
+#define AON_REG_RTC_SHOT_CTRL_RTC_TASK_CLEAR_SUB_EN_Msk                                                                  (0x1UL << AON_REG_RTC_SHOT_CTRL_RTC_TASK_CLEAR_SUB_EN_Pos)
+
+#define AON_REG_RTC_SHOT_CTRL_RTC_TASK_RELOAD_CMP0_SUB_EN_Pos                                                            2U
+#define AON_REG_RTC_SHOT_CTRL_RTC_TASK_RELOAD_CMP0_SUB_EN_Msk                                                            (0x1UL << AON_REG_RTC_SHOT_CTRL_RTC_TASK_RELOAD_CMP0_SUB_EN_Pos)
+
+#define AON_REG_RTC_SHOT_CTRL_RTC_TASK_RELOAD_CMP1_SUB_EN_Pos                                                            3U
+#define AON_REG_RTC_SHOT_CTRL_RTC_TASK_RELOAD_CMP1_SUB_EN_Msk                                                            (0x1UL << AON_REG_RTC_SHOT_CTRL_RTC_TASK_RELOAD_CMP1_SUB_EN_Pos)
+
+#define AON_REG_RTC_SHOT_CTRL_RTC_TASK_RELOAD_CMP2_SUB_EN_Pos                                                            4U
+#define AON_REG_RTC_SHOT_CTRL_RTC_TASK_RELOAD_CMP2_SUB_EN_Msk                                                            (0x1UL << AON_REG_RTC_SHOT_CTRL_RTC_TASK_RELOAD_CMP2_SUB_EN_Pos)
+
+#define AON_REG_RTC_SHOT_CTRL_RTC_TASK_RELOAD_CMP3_SUB_EN_Pos                                                            5U
+#define AON_REG_RTC_SHOT_CTRL_RTC_TASK_RELOAD_CMP3_SUB_EN_Msk                                                            (0x1UL << AON_REG_RTC_SHOT_CTRL_RTC_TASK_RELOAD_CMP3_SUB_EN_Pos)
+
+#define AON_REG_RTC_SHOT_CTRL_RTC_SHOT_CTRL_RESERVED15_6_Pos                                                             6U
+#define AON_REG_RTC_SHOT_CTRL_RTC_SHOT_CTRL_RESERVED15_6_Msk                                                             (0x3FFUL << AON_REG_RTC_SHOT_CTRL_RTC_SHOT_CTRL_RESERVED15_6_Pos)
+
+#define AON_REG_RTC_SHOT_CTRL_RTC_EVENT_CMP0_PUB_EN_Pos                                                                  16U
+#define AON_REG_RTC_SHOT_CTRL_RTC_EVENT_CMP0_PUB_EN_Msk                                                                  (0x1UL << AON_REG_RTC_SHOT_CTRL_RTC_EVENT_CMP0_PUB_EN_Pos)
+
+#define AON_REG_RTC_SHOT_CTRL_RTC_EVENT_CMP1_PUB_EN_Pos                                                                  17U
+#define AON_REG_RTC_SHOT_CTRL_RTC_EVENT_CMP1_PUB_EN_Msk                                                                  (0x1UL << AON_REG_RTC_SHOT_CTRL_RTC_EVENT_CMP1_PUB_EN_Pos)
+
+#define AON_REG_RTC_SHOT_CTRL_RTC_EVENT_CMP2_PUB_EN_Pos                                                                  18U
+#define AON_REG_RTC_SHOT_CTRL_RTC_EVENT_CMP2_PUB_EN_Msk                                                                  (0x1UL << AON_REG_RTC_SHOT_CTRL_RTC_EVENT_CMP2_PUB_EN_Pos)
+
+#define AON_REG_RTC_SHOT_CTRL_RTC_EVENT_CMP3_PUB_EN_Pos                                                                  19U
+#define AON_REG_RTC_SHOT_CTRL_RTC_EVENT_CMP3_PUB_EN_Msk                                                                  (0x1UL << AON_REG_RTC_SHOT_CTRL_RTC_EVENT_CMP3_PUB_EN_Pos)
+
+#define AON_REG_RTC_SHOT_CTRL_RTC_SHOT_CTRL_RESERVED31_20_Pos                                                            20U
+#define AON_REG_RTC_SHOT_CTRL_RTC_SHOT_CTRL_RESERVED31_20_Msk                                                            (0xFFFUL << AON_REG_RTC_SHOT_CTRL_RTC_SHOT_CTRL_RESERVED31_20_Pos)
+
+/* 0x7B8    0x4000_07b8
+    0       R/W     RTC_QACT_SCLK_MAN_DATA                                      1'h0
+    1       R/W     RTC_QACT_SCLK_MAN_EN                                        1'h0
+    2       R/W     RTC_QACT_PCLK_MAN_DATA                                      1'h0
+    3       R/W     RTC_QACT_PCLK_MAN_EN                                        1'h0
+    31:4    R       RTC_QACTIVE_CTRL_RESERVED31_4                               28'h0
+ */
+typedef union _AON_REG_RTC_QACTIVE_CTRL_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RTC_QACT_SCLK_MAN_DATA: 1;
+        uint32_t RTC_QACT_SCLK_MAN_EN: 1;
+        uint32_t RTC_QACT_PCLK_MAN_DATA: 1;
+        uint32_t RTC_QACT_PCLK_MAN_EN: 1;
+        uint32_t RTC_QACTIVE_CTRL_RESERVED31_4: 28;
+    };
+} AON_REG_RTC_QACTIVE_CTRL_TYPE;
+
+/*0x4000_07b8 AON_REG_RTC_QACTIVE_CTRL*/
+#define AON_REG_RTC_QACTIVE_CTRL_RTC_QACT_SCLK_MAN_DATA_Pos                                                              0U
+#define AON_REG_RTC_QACTIVE_CTRL_RTC_QACT_SCLK_MAN_DATA_Msk                                                              (0x1UL << AON_REG_RTC_QACTIVE_CTRL_RTC_QACT_SCLK_MAN_DATA_Pos)
+
+#define AON_REG_RTC_QACTIVE_CTRL_RTC_QACT_SCLK_MAN_EN_Pos                                                                1U
+#define AON_REG_RTC_QACTIVE_CTRL_RTC_QACT_SCLK_MAN_EN_Msk                                                                (0x1UL << AON_REG_RTC_QACTIVE_CTRL_RTC_QACT_SCLK_MAN_EN_Pos)
+
+#define AON_REG_RTC_QACTIVE_CTRL_RTC_QACT_PCLK_MAN_DATA_Pos                                                              2U
+#define AON_REG_RTC_QACTIVE_CTRL_RTC_QACT_PCLK_MAN_DATA_Msk                                                              (0x1UL << AON_REG_RTC_QACTIVE_CTRL_RTC_QACT_PCLK_MAN_DATA_Pos)
+
+#define AON_REG_RTC_QACTIVE_CTRL_RTC_QACT_PCLK_MAN_EN_Pos                                                                3U
+#define AON_REG_RTC_QACTIVE_CTRL_RTC_QACT_PCLK_MAN_EN_Msk                                                                (0x1UL << AON_REG_RTC_QACTIVE_CTRL_RTC_QACT_PCLK_MAN_EN_Pos)
+
+#define AON_REG_RTC_QACTIVE_CTRL_RTC_QACTIVE_CTRL_RESERVED31_4_Pos                                                       4U
+#define AON_REG_RTC_QACTIVE_CTRL_RTC_QACTIVE_CTRL_RESERVED31_4_Msk                                                       (0xFFFFFFFUL << AON_REG_RTC_QACTIVE_CTRL_RTC_QACTIVE_CTRL_RESERVED31_4_Pos)
+
+/* 0x7C0    0x4000_07c0
+    31:0    R       LPCOMP_VERSION                                              32'h20240329
+ */
+typedef union _AON_REG_LPC_VERSION_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t LPCOMP_VERSION;
+    };
+} AON_REG_LPC_VERSION_TYPE;
+
+/*0x4000_07c0 AON_REG_LPC_VERSION*/
+#define AON_REG_LPC_VERSION_LPCOMP_VERSION_Pos                                                                           0U
+#define AON_REG_LPC_VERSION_LPCOMP_VERSION_Msk                                                                           (0xFFFFFFFFUL << AON_REG_LPC_VERSION_LPCOMP_VERSION_Pos)
+
+/* 0x7C4    0x4000_07c4
+    0       R/W     REG_LPCOMP_COUNTER_RST                                      1'h0
+    1       R/W     REG_LPCOMP_COUNTER_START                                    1'h0
+    2       R/WAC   REG_LPCOMP_FLAG_CLR                                         1'h0
+    7:3     R       RESERVER080_7_3                                             5'h0
+    8       R/W     REG_LPCOMP_IE                                               1'h0
+    9       R/W     REG_LPCOMP_SRC_INT_EN                                       1'h0
+    18:10   R/W     RESERVER080_18_10                                           9'h0
+    19      R/W     REG_LPCOMP_SRC_AON_INT_EN                                   1'h0
+    20      R/W     REG_LPCOMP_OUTPUT_EN                                        1'h0
+    30:21   R       RESERVER080_30_21                                           10'h0
+    31      R/W     LPC_RST                                                     1'h0
+ */
+typedef union _AON_REG_LPC_CR0_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t REG_LPCOMP_COUNTER_RST: 1;
+        uint32_t REG_LPCOMP_COUNTER_START: 1;
+        uint32_t REG_LPCOMP_FLAG_CLR: 1;
+        uint32_t RESERVER080_7_3: 5;
+        uint32_t REG_LPCOMP_IE: 1;
+        uint32_t REG_LPCOMP_SRC_INT_EN: 1;
+        uint32_t RESERVER080_18_10: 9;
+        uint32_t REG_LPCOMP_SRC_AON_INT_EN: 1;
+        uint32_t REG_LPCOMP_OUTPUT_EN: 1;
+        uint32_t RESERVER080_30_21: 10;
+        uint32_t LPC_RST: 1;
+    };
+} AON_REG_LPC_CR0_TYPE;
+
+/*0x4000_07c4 AON_REG_LPC_CR0*/
+#define AON_REG_LPC_CR0_REG_LPCOMP_COUNTER_RST_Pos                                                                       0U
+#define AON_REG_LPC_CR0_REG_LPCOMP_COUNTER_RST_Msk                                                                       (0x1UL << AON_REG_LPC_CR0_REG_LPCOMP_COUNTER_RST_Pos)
+
+#define AON_REG_LPC_CR0_REG_LPCOMP_COUNTER_START_Pos                                                                     1U
+#define AON_REG_LPC_CR0_REG_LPCOMP_COUNTER_START_Msk                                                                     (0x1UL << AON_REG_LPC_CR0_REG_LPCOMP_COUNTER_START_Pos)
+
+#define AON_REG_LPC_CR0_REG_LPCOMP_FLAG_CLR_Pos                                                                          2U
+#define AON_REG_LPC_CR0_REG_LPCOMP_FLAG_CLR_Msk                                                                          (0x1UL << AON_REG_LPC_CR0_REG_LPCOMP_FLAG_CLR_Pos)
+
+#define AON_REG_LPC_CR0_RESERVER080_7_3_Pos                                                                              3U
+#define AON_REG_LPC_CR0_RESERVER080_7_3_Msk                                                                              (0x1FUL << AON_REG_LPC_CR0_RESERVER080_7_3_Pos)
+
+#define AON_REG_LPC_CR0_REG_LPCOMP_IE_Pos                                                                                8U
+#define AON_REG_LPC_CR0_REG_LPCOMP_IE_Msk                                                                                (0x1UL << AON_REG_LPC_CR0_REG_LPCOMP_IE_Pos)
+
+#define AON_REG_LPC_CR0_REG_LPCOMP_SRC_INT_EN_Pos                                                                        9U
+#define AON_REG_LPC_CR0_REG_LPCOMP_SRC_INT_EN_Msk                                                                        (0x1UL << AON_REG_LPC_CR0_REG_LPCOMP_SRC_INT_EN_Pos)
+
+#define AON_REG_LPC_CR0_RESERVER080_18_10_Pos                                                                            10U
+#define AON_REG_LPC_CR0_RESERVER080_18_10_Msk                                                                            (0x1FFUL << AON_REG_LPC_CR0_RESERVER080_18_10_Pos)
+
+#define AON_REG_LPC_CR0_REG_LPCOMP_SRC_AON_INT_EN_Pos                                                                    19U
+#define AON_REG_LPC_CR0_REG_LPCOMP_SRC_AON_INT_EN_Msk                                                                    (0x1UL << AON_REG_LPC_CR0_REG_LPCOMP_SRC_AON_INT_EN_Pos)
+
+#define AON_REG_LPC_CR0_REG_LPCOMP_OUTPUT_EN_Pos                                                                         20U
+#define AON_REG_LPC_CR0_REG_LPCOMP_OUTPUT_EN_Msk                                                                         (0x1UL << AON_REG_LPC_CR0_REG_LPCOMP_OUTPUT_EN_Pos)
+
+#define AON_REG_LPC_CR0_RESERVER080_30_21_Pos                                                                            21U
+#define AON_REG_LPC_CR0_RESERVER080_30_21_Msk                                                                            (0x3FFUL << AON_REG_LPC_CR0_RESERVER080_30_21_Pos)
+
+#define AON_REG_LPC_CR0_LPC_RST_Pos                                                                                      31U
+#define AON_REG_LPC_CR0_LPC_RST_Msk                                                                                      (0x1UL << AON_REG_LPC_CR0_LPC_RST_Pos)
+
+/* 0x7C8    0x4000_07c8
+    0       R       REG_LPCOMP_FLAG                                             1'h0
+    1       R       REG_LPCOMP_OUT_AON                                          1'h0
+    31:2    R       RESERVER084_31_22                                           30'h0
+ */
+typedef union _AON_REG_LPC_SR_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t REG_LPCOMP_FLAG: 1;
+        uint32_t REG_LPCOMP_OUT_AON: 1;
+        uint32_t RESERVER084_31_22: 30;
+    };
+} AON_REG_LPC_SR_TYPE;
+
+/*0x4000_07c8 AON_REG_LPC_SR*/
+#define AON_REG_LPC_SR_REG_LPCOMP_FLAG_Pos                                                                               0U
+#define AON_REG_LPC_SR_REG_LPCOMP_FLAG_Msk                                                                               (0x1UL << AON_REG_LPC_SR_REG_LPCOMP_FLAG_Pos)
+
+#define AON_REG_LPC_SR_REG_LPCOMP_OUT_AON_Pos                                                                            1U
+#define AON_REG_LPC_SR_REG_LPCOMP_OUT_AON_Msk                                                                            (0x1UL << AON_REG_LPC_SR_REG_LPCOMP_OUT_AON_Pos)
+
+#define AON_REG_LPC_SR_RESERVER084_31_22_Pos                                                                             2U
+#define AON_REG_LPC_SR_RESERVER084_31_22_Msk                                                                             (0x3FFFFFFFUL << AON_REG_LPC_SR_RESERVER084_31_22_Pos)
+
+/* 0x7CC    0x4000_07cc
+    11:0    R/W     REG_LPCOMP_COMP                                             0x0
+    31:12   R       RESERVER088_31_12                                           20'h0
+ */
+typedef union _AON_REG_LPC_CMP_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t REG_LPCOMP_COMP: 12;
+        uint32_t RESERVER088_31_12: 20;
+    };
+} AON_REG_LPC_CMP_TYPE;
+
+/*0x4000_07cc AON_REG_LPC_CMP*/
+#define AON_REG_LPC_CMP_REG_LPCOMP_COMP_Pos                                                                              0U
+#define AON_REG_LPC_CMP_REG_LPCOMP_COMP_Msk                                                                              (0xFFFUL << AON_REG_LPC_CMP_REG_LPCOMP_COMP_Pos)
+
+#define AON_REG_LPC_CMP_RESERVER088_31_12_Pos                                                                            12U
+#define AON_REG_LPC_CMP_RESERVER088_31_12_Msk                                                                            (0xFFFFFUL << AON_REG_LPC_CMP_RESERVER088_31_12_Pos)
+
+/* 0x7D0    0x4000_07d0
+    11:0    R       REG_LPCOMP_COUNTER                                          12'h0
+    31:12   R       RESERVER08C_31_12                                           20'h0
+ */
+typedef union _AON_REG_LPC_CNT_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t REG_LPCOMP_COUNTER: 12;
+        uint32_t RESERVER08C_31_12: 20;
+    };
+} AON_REG_LPC_CNT_TYPE;
+
+/*0x4000_07d0 AON_REG_LPC_CNT*/
+#define AON_REG_LPC_CNT_REG_LPCOMP_COUNTER_Pos                                                                           0U
+#define AON_REG_LPC_CNT_REG_LPCOMP_COUNTER_Msk                                                                           (0xFFFUL << AON_REG_LPC_CNT_REG_LPCOMP_COUNTER_Pos)
+
+#define AON_REG_LPC_CNT_RESERVER08C_31_12_Pos                                                                            12U
+#define AON_REG_LPC_CNT_RESERVER08C_31_12_Msk                                                                            (0xFFFFFUL << AON_REG_LPC_CNT_RESERVER08C_31_12_Pos)
+
+/* 0x7D4    0x4000_07d4
+    0       R/W     LPC_RAP_MODE                                                1'h0
+    1       R/WAC   LPC_FW_TASK_START                                           1'h0
+    2       R/WAC   LPC_FW_TASK_STOP                                            1'h0
+    31:3    R       RESERVER090_31_3                                            29'h0
+ */
+typedef union _AON_REG_LPC_TASK_CTRL_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t LPC_RAP_MODE: 1;
+        uint32_t LPC_FW_TASK_START: 1;
+        uint32_t LPC_FW_TASK_STOP: 1;
+        uint32_t RESERVER090_31_3: 29;
+    };
+} AON_REG_LPC_TASK_CTRL_TYPE;
+
+/*0x4000_07d4 AON_REG_LPC_TASK_CTRL*/
+#define AON_REG_LPC_TASK_CTRL_LPC_RAP_MODE_Pos                                                                           0U
+#define AON_REG_LPC_TASK_CTRL_LPC_RAP_MODE_Msk                                                                           (0x1UL << AON_REG_LPC_TASK_CTRL_LPC_RAP_MODE_Pos)
+
+#define AON_REG_LPC_TASK_CTRL_LPC_FW_TASK_START_Pos                                                                      1U
+#define AON_REG_LPC_TASK_CTRL_LPC_FW_TASK_START_Msk                                                                      (0x1UL << AON_REG_LPC_TASK_CTRL_LPC_FW_TASK_START_Pos)
+
+#define AON_REG_LPC_TASK_CTRL_LPC_FW_TASK_STOP_Pos                                                                       2U
+#define AON_REG_LPC_TASK_CTRL_LPC_FW_TASK_STOP_Msk                                                                       (0x1UL << AON_REG_LPC_TASK_CTRL_LPC_FW_TASK_STOP_Pos)
+
+#define AON_REG_LPC_TASK_CTRL_RESERVER090_31_3_Pos                                                                       3U
+#define AON_REG_LPC_TASK_CTRL_RESERVER090_31_3_Msk                                                                       (0x1FFFFFFFUL << AON_REG_LPC_TASK_CTRL_RESERVER090_31_3_Pos)
+
+/* 0x7D8    0x4000_07d8
+    0       R/W     LPC_TASK_STOP_SUB_EN                                        1'h0
+    15:1    R       RESERVER094_15_1                                            15'h0
+    16      R/W     LPC_EVENT_STATUS_PUB_EN                                     1'h0
+    31:17   R       RESERVER094_31_17                                           15'h0
+ */
+typedef union _AON_REG_LPC_SHOT_CTRL_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t LPC_TASK_STOP_SUB_EN: 1;
+        uint32_t RESERVER094_15_1: 15;
+        uint32_t LPC_EVENT_STATUS_PUB_EN: 1;
+        uint32_t RESERVER094_31_17: 15;
+    };
+} AON_REG_LPC_SHOT_CTRL_TYPE;
+
+/*0x4000_07d8 AON_REG_LPC_SHOT_CTRL*/
+#define AON_REG_LPC_SHOT_CTRL_LPC_TASK_STOP_SUB_EN_Pos                                                                   0U
+#define AON_REG_LPC_SHOT_CTRL_LPC_TASK_STOP_SUB_EN_Msk                                                                   (0x1UL << AON_REG_LPC_SHOT_CTRL_LPC_TASK_STOP_SUB_EN_Pos)
+
+#define AON_REG_LPC_SHOT_CTRL_RESERVER094_15_1_Pos                                                                       1U
+#define AON_REG_LPC_SHOT_CTRL_RESERVER094_15_1_Msk                                                                       (0x7FFFUL << AON_REG_LPC_SHOT_CTRL_RESERVER094_15_1_Pos)
+
+#define AON_REG_LPC_SHOT_CTRL_LPC_EVENT_STATUS_PUB_EN_Pos                                                                16U
+#define AON_REG_LPC_SHOT_CTRL_LPC_EVENT_STATUS_PUB_EN_Msk                                                                (0x1UL << AON_REG_LPC_SHOT_CTRL_LPC_EVENT_STATUS_PUB_EN_Pos)
+
+#define AON_REG_LPC_SHOT_CTRL_RESERVER094_31_17_Pos                                                                      17U
+#define AON_REG_LPC_SHOT_CTRL_RESERVER094_31_17_Msk                                                                      (0x7FFFUL << AON_REG_LPC_SHOT_CTRL_RESERVER094_31_17_Pos)
+
+/* 0x7DC    0x4000_07dc
+    0       R/W     LPC_QACT_SCLK_MAN_DATA                                      1'h0
+    1       R/W     LPC_QACT_SCLK_MAN_EN                                        1'h0
+    2       R/W     LPC_QACT_PCLK_MAN_DATA                                      1'h0
+    3       R/W     LPC_QACT_PCLK_MAN_EN                                        1'h0
+    31:4    R       RESERVER098_31_4                                            28'h0
+ */
+typedef union _AON_REG_LPC_QACTIVE_CTRL_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t LPC_QACT_SCLK_MAN_DATA: 1;
+        uint32_t LPC_QACT_SCLK_MAN_EN: 1;
+        uint32_t LPC_QACT_PCLK_MAN_DATA: 1;
+        uint32_t LPC_QACT_PCLK_MAN_EN: 1;
+        uint32_t RESERVER098_31_4: 28;
+    };
+} AON_REG_LPC_QACTIVE_CTRL_TYPE;
+
+/*0x4000_07dc AON_REG_LPC_QACTIVE_CTRL*/
+#define AON_REG_LPC_QACTIVE_CTRL_LPC_QACT_SCLK_MAN_DATA_Pos                                                              0U
+#define AON_REG_LPC_QACTIVE_CTRL_LPC_QACT_SCLK_MAN_DATA_Msk                                                              (0x1UL << AON_REG_LPC_QACTIVE_CTRL_LPC_QACT_SCLK_MAN_DATA_Pos)
+
+#define AON_REG_LPC_QACTIVE_CTRL_LPC_QACT_SCLK_MAN_EN_Pos                                                                1U
+#define AON_REG_LPC_QACTIVE_CTRL_LPC_QACT_SCLK_MAN_EN_Msk                                                                (0x1UL << AON_REG_LPC_QACTIVE_CTRL_LPC_QACT_SCLK_MAN_EN_Pos)
+
+#define AON_REG_LPC_QACTIVE_CTRL_LPC_QACT_PCLK_MAN_DATA_Pos                                                              2U
+#define AON_REG_LPC_QACTIVE_CTRL_LPC_QACT_PCLK_MAN_DATA_Msk                                                              (0x1UL << AON_REG_LPC_QACTIVE_CTRL_LPC_QACT_PCLK_MAN_DATA_Pos)
+
+#define AON_REG_LPC_QACTIVE_CTRL_LPC_QACT_PCLK_MAN_EN_Pos                                                                3U
+#define AON_REG_LPC_QACTIVE_CTRL_LPC_QACT_PCLK_MAN_EN_Msk                                                                (0x1UL << AON_REG_LPC_QACTIVE_CTRL_LPC_QACT_PCLK_MAN_EN_Pos)
+
+#define AON_REG_LPC_QACTIVE_CTRL_RESERVER098_31_4_Pos                                                                    4U
+#define AON_REG_LPC_QACTIVE_CTRL_RESERVER098_31_4_Msk                                                                    (0xFFFFFFFUL << AON_REG_LPC_QACTIVE_CTRL_RESERVER098_31_4_Pos)
+
+/* 0x7E0    0x4000_07e0
+    0       R/W     POW_SD_H                                                    1'h0
+    4:1     R/W     CH_NUM_H                                                    4'h0
+    5       R/W     SD_POSEDGE_H                                                1'h1
+    6       R/W     EN_HYS                                                      1'h0
+    7       R/W     EN_BYP                                                      1'h0
+    8       R       EN_AD_LPC_COMP_OUT_DBG                                      1'b0
+    31:9    R       RESERVER094_31_9                                            23'h0
+ */
+typedef union _AON_REG0X_SD_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t POW_SD_H: 1;
+        uint32_t CH_NUM_H: 4;
+        uint32_t SD_POSEDGE_H: 1;
+        uint32_t EN_HYS: 1;
+        uint32_t EN_BYP: 1;
+        uint32_t EN_AD_LPC_COMP_OUT_DBG: 1;
+        uint32_t RESERVER094_31_9: 23;
+    };
+} AON_REG0X_SD_TYPE;
+
+/*0x4000_07e0 AON_REG0X_SD*/
+#define AON_REG0X_SD_POW_SD_H_Pos                                                                                        0U
+#define AON_REG0X_SD_POW_SD_H_Msk                                                                                        (0x1UL << AON_REG0X_SD_POW_SD_H_Pos)
+
+#define AON_REG0X_SD_CH_NUM_H_Pos                                                                                        1U
+#define AON_REG0X_SD_CH_NUM_H_Msk                                                                                        (0xFUL << AON_REG0X_SD_CH_NUM_H_Pos)
+
+#define AON_REG0X_SD_SD_POSEDGE_H_Pos                                                                                    5U
+#define AON_REG0X_SD_SD_POSEDGE_H_Msk                                                                                    (0x1UL << AON_REG0X_SD_SD_POSEDGE_H_Pos)
+
+#define AON_REG0X_SD_EN_HYS_Pos                                                                                          6U
+#define AON_REG0X_SD_EN_HYS_Msk                                                                                          (0x1UL << AON_REG0X_SD_EN_HYS_Pos)
+
+#define AON_REG0X_SD_EN_BYP_Pos                                                                                          7U
+#define AON_REG0X_SD_EN_BYP_Msk                                                                                          (0x1UL << AON_REG0X_SD_EN_BYP_Pos)
+
+#define AON_REG0X_SD_EN_AD_LPC_COMP_OUT_DBG_Pos                                                                          8U
+#define AON_REG0X_SD_EN_AD_LPC_COMP_OUT_DBG_Msk                                                                          (0x1UL << AON_REG0X_SD_EN_AD_LPC_COMP_OUT_DBG_Pos)
+
+#define AON_REG0X_SD_RESERVER094_31_9_Pos                                                                                9U
+#define AON_REG0X_SD_RESERVER094_31_9_Msk                                                                                (0x7FFFFFUL << AON_REG0X_SD_RESERVER094_31_9_Pos)
+
+/* 0x7E4    0x4000_07e4
+    3:0     R/W     X_SCAN_DIV                                                  4'h0
+    31:4    R       REG_LPQDEC_X_DIV_RESERVED31_4                               28'h0
+ */
+typedef union _AON_REG_LPQDEC_X_DIV_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t X_SCAN_DIV: 4;
+        uint32_t REG_LPQDEC_X_DIV_RESERVED31_4: 28;
+    };
+} AON_REG_LPQDEC_X_DIV_TYPE;
+
+/*0x4000_07e4 AON_REG_LPQDEC_X_DIV*/
+#define AON_REG_LPQDEC_X_DIV_X_SCAN_DIV_Pos                                                                              0U
+#define AON_REG_LPQDEC_X_DIV_X_SCAN_DIV_Msk                                                                              (0xFUL << AON_REG_LPQDEC_X_DIV_X_SCAN_DIV_Pos)
+
+#define AON_REG_LPQDEC_X_DIV_REG_LPQDEC_X_DIV_RESERVED31_4_Pos                                                           4U
+#define AON_REG_LPQDEC_X_DIV_REG_LPQDEC_X_DIV_RESERVED31_4_Msk                                                           (0xFFFFFFFUL << AON_REG_LPQDEC_X_DIV_REG_LPQDEC_X_DIV_RESERVED31_4_Pos)
+
+/* 0x7E8    0x4000_07e8
+    1:0     R/W     X_INITIAL_PHASE                                             2'h0
+    2       R/W     X_SET_INITAL_PHASE                                          1'h0
+    3       R/W     X_CNT_PAUSE                                                 1'h0
+    4       R/W     X_CNT_SCALE                                                 1'h0
+    5       R/W     X_ILLEGAL_INT_EN                                            1'h0
+    6       R/W     X_CNT_INT_EN                                                1'h0
+    7       R/W     X_ILLEGAL_INT_MASK                                          1'h1
+    8       R/W     X_CNT_INT_MASK                                              1'h1
+    21:9    R/W     X_DEBOUNCE_CNT                                              13'h0
+    22      R/W     X_DEBOUNCE_EN                                               1'h0
+    23      R/W     X_WAKE_AON_MASK                                             1'b1
+    24      R/W     X_INT_MASK                                                  1'b1
+    28:25   R       REG_LPQDEC_X_CONFIG_RESERVED28_25                           4'b0
+    29      R/W     X_RST                                                       1'b0
+    30      R/WAC   X_FSM_EN                                                    1'h0
+    31      R/W     X_AXIS_EN                                                   1'h0
+ */
+typedef union _AON_REG_LPQDEC_X_CONFIG_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t X_INITIAL_PHASE: 2;
+        uint32_t X_SET_INITAL_PHASE: 1;
+        uint32_t X_CNT_PAUSE: 1;
+        uint32_t X_CNT_SCALE: 1;
+        uint32_t X_ILLEGAL_INT_EN: 1;
+        uint32_t X_CNT_INT_EN: 1;
+        uint32_t X_ILLEGAL_INT_MASK: 1;
+        uint32_t X_CNT_INT_MASK: 1;
+        uint32_t X_DEBOUNCE_CNT: 13;
+        uint32_t X_DEBOUNCE_EN: 1;
+        uint32_t X_WAKE_AON_MASK: 1;
+        uint32_t X_INT_MASK: 1;
+        uint32_t REG_LPQDEC_X_CONFIG_RESERVED28_25: 4;
+        uint32_t X_RST: 1;
+        uint32_t X_FSM_EN: 1;
+        uint32_t X_AXIS_EN: 1;
+    };
+} AON_REG_LPQDEC_X_CONFIG_TYPE;
+
+/*0x4000_07e8 AON_REG_LPQDEC_X_CONFIG*/
+#define AON_REG_LPQDEC_X_CONFIG_X_INITIAL_PHASE_Pos                                                                      0U
+#define AON_REG_LPQDEC_X_CONFIG_X_INITIAL_PHASE_Msk                                                                      (0x3UL << AON_REG_LPQDEC_X_CONFIG_X_INITIAL_PHASE_Pos)
+
+#define AON_REG_LPQDEC_X_CONFIG_X_SET_INITAL_PHASE_Pos                                                                   2U
+#define AON_REG_LPQDEC_X_CONFIG_X_SET_INITAL_PHASE_Msk                                                                   (0x1UL << AON_REG_LPQDEC_X_CONFIG_X_SET_INITAL_PHASE_Pos)
+
+#define AON_REG_LPQDEC_X_CONFIG_X_CNT_PAUSE_Pos                                                                          3U
+#define AON_REG_LPQDEC_X_CONFIG_X_CNT_PAUSE_Msk                                                                          (0x1UL << AON_REG_LPQDEC_X_CONFIG_X_CNT_PAUSE_Pos)
+
+#define AON_REG_LPQDEC_X_CONFIG_X_CNT_SCALE_Pos                                                                          4U
+#define AON_REG_LPQDEC_X_CONFIG_X_CNT_SCALE_Msk                                                                          (0x1UL << AON_REG_LPQDEC_X_CONFIG_X_CNT_SCALE_Pos)
+
+#define AON_REG_LPQDEC_X_CONFIG_X_ILLEGAL_INT_EN_Pos                                                                     5U
+#define AON_REG_LPQDEC_X_CONFIG_X_ILLEGAL_INT_EN_Msk                                                                     (0x1UL << AON_REG_LPQDEC_X_CONFIG_X_ILLEGAL_INT_EN_Pos)
+
+#define AON_REG_LPQDEC_X_CONFIG_X_CNT_INT_EN_Pos                                                                         6U
+#define AON_REG_LPQDEC_X_CONFIG_X_CNT_INT_EN_Msk                                                                         (0x1UL << AON_REG_LPQDEC_X_CONFIG_X_CNT_INT_EN_Pos)
+
+#define AON_REG_LPQDEC_X_CONFIG_X_ILLEGAL_INT_MASK_Pos                                                                   7U
+#define AON_REG_LPQDEC_X_CONFIG_X_ILLEGAL_INT_MASK_Msk                                                                   (0x1UL << AON_REG_LPQDEC_X_CONFIG_X_ILLEGAL_INT_MASK_Pos)
+
+#define AON_REG_LPQDEC_X_CONFIG_X_CNT_INT_MASK_Pos                                                                       8U
+#define AON_REG_LPQDEC_X_CONFIG_X_CNT_INT_MASK_Msk                                                                       (0x1UL << AON_REG_LPQDEC_X_CONFIG_X_CNT_INT_MASK_Pos)
+
+#define AON_REG_LPQDEC_X_CONFIG_X_DEBOUNCE_CNT_Pos                                                                       9U
+#define AON_REG_LPQDEC_X_CONFIG_X_DEBOUNCE_CNT_Msk                                                                       (0x1FFFUL << AON_REG_LPQDEC_X_CONFIG_X_DEBOUNCE_CNT_Pos)
+
+#define AON_REG_LPQDEC_X_CONFIG_X_DEBOUNCE_EN_Pos                                                                        22U
+#define AON_REG_LPQDEC_X_CONFIG_X_DEBOUNCE_EN_Msk                                                                        (0x1UL << AON_REG_LPQDEC_X_CONFIG_X_DEBOUNCE_EN_Pos)
+
+#define AON_REG_LPQDEC_X_CONFIG_X_WAKE_AON_MASK_Pos                                                                      23U
+#define AON_REG_LPQDEC_X_CONFIG_X_WAKE_AON_MASK_Msk                                                                      (0x1UL << AON_REG_LPQDEC_X_CONFIG_X_WAKE_AON_MASK_Pos)
+
+#define AON_REG_LPQDEC_X_CONFIG_X_INT_MASK_Pos                                                                           24U
+#define AON_REG_LPQDEC_X_CONFIG_X_INT_MASK_Msk                                                                           (0x1UL << AON_REG_LPQDEC_X_CONFIG_X_INT_MASK_Pos)
+
+#define AON_REG_LPQDEC_X_CONFIG_REG_LPQDEC_X_CONFIG_RESERVED28_25_Pos                                                    25U
+#define AON_REG_LPQDEC_X_CONFIG_REG_LPQDEC_X_CONFIG_RESERVED28_25_Msk                                                    (0xFUL << AON_REG_LPQDEC_X_CONFIG_REG_LPQDEC_X_CONFIG_RESERVED28_25_Pos)
+
+#define AON_REG_LPQDEC_X_CONFIG_X_RST_Pos                                                                                29U
+#define AON_REG_LPQDEC_X_CONFIG_X_RST_Msk                                                                                (0x1UL << AON_REG_LPQDEC_X_CONFIG_X_RST_Pos)
+
+#define AON_REG_LPQDEC_X_CONFIG_X_FSM_EN_Pos                                                                             30U
+#define AON_REG_LPQDEC_X_CONFIG_X_FSM_EN_Msk                                                                             (0x1UL << AON_REG_LPQDEC_X_CONFIG_X_FSM_EN_Pos)
+
+#define AON_REG_LPQDEC_X_CONFIG_X_AXIS_EN_Pos                                                                            31U
+#define AON_REG_LPQDEC_X_CONFIG_X_AXIS_EN_Msk                                                                            (0x1UL << AON_REG_LPQDEC_X_CONFIG_X_AXIS_EN_Pos)
+
+/* 0x7EC    0x4000_07ec
+    15:0    R       REG_LPQDEC_X_SR_1_RESERVED15_0                              16'h0
+    16      R       X_CNT_OF_FLG                                                1'h0
+    17      R       X_CNT_UF_FLG                                                1'h0
+    18      R       X_CNT_INT_STA                                               1'h0
+    19      R       X_ILLEGAL_INT_STA                                           1'h0
+    20      R       X_CNT_DIR                                                   1'h0
+    21      R       X_PHA_STA                                                   1'h0
+    22      R       X_PHB_STA                                                   1'h0
+    31:23   R       REG_LPQDEC_X_SR_1_RESERVED31_23                             9'h0
+ */
+typedef union _AON_REG_LPQDEC_X_SR_1_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t REG_LPQDEC_X_SR_1_RESERVED15_0: 16;
+        uint32_t X_CNT_OF_FLG: 1;
+        uint32_t X_CNT_UF_FLG: 1;
+        uint32_t X_CNT_INT_STA: 1;
+        uint32_t X_ILLEGAL_INT_STA: 1;
+        uint32_t X_CNT_DIR: 1;
+        uint32_t X_PHA_STA: 1;
+        uint32_t X_PHB_STA: 1;
+        uint32_t REG_LPQDEC_X_SR_1_RESERVED31_23: 9;
+    };
+} AON_REG_LPQDEC_X_SR_1_TYPE;
+
+/*0x4000_07ec AON_REG_LPQDEC_X_SR_1*/
+#define AON_REG_LPQDEC_X_SR_1_REG_LPQDEC_X_SR_1_RESERVED15_0_Pos                                                         0U
+#define AON_REG_LPQDEC_X_SR_1_REG_LPQDEC_X_SR_1_RESERVED15_0_Msk                                                         (0xFFFFUL << AON_REG_LPQDEC_X_SR_1_REG_LPQDEC_X_SR_1_RESERVED15_0_Pos)
+
+#define AON_REG_LPQDEC_X_SR_1_X_CNT_OF_FLG_Pos                                                                           16U
+#define AON_REG_LPQDEC_X_SR_1_X_CNT_OF_FLG_Msk                                                                           (0x1UL << AON_REG_LPQDEC_X_SR_1_X_CNT_OF_FLG_Pos)
+
+#define AON_REG_LPQDEC_X_SR_1_X_CNT_UF_FLG_Pos                                                                           17U
+#define AON_REG_LPQDEC_X_SR_1_X_CNT_UF_FLG_Msk                                                                           (0x1UL << AON_REG_LPQDEC_X_SR_1_X_CNT_UF_FLG_Pos)
+
+#define AON_REG_LPQDEC_X_SR_1_X_CNT_INT_STA_Pos                                                                          18U
+#define AON_REG_LPQDEC_X_SR_1_X_CNT_INT_STA_Msk                                                                          (0x1UL << AON_REG_LPQDEC_X_SR_1_X_CNT_INT_STA_Pos)
+
+#define AON_REG_LPQDEC_X_SR_1_X_ILLEGAL_INT_STA_Pos                                                                      19U
+#define AON_REG_LPQDEC_X_SR_1_X_ILLEGAL_INT_STA_Msk                                                                      (0x1UL << AON_REG_LPQDEC_X_SR_1_X_ILLEGAL_INT_STA_Pos)
+
+#define AON_REG_LPQDEC_X_SR_1_X_CNT_DIR_Pos                                                                              20U
+#define AON_REG_LPQDEC_X_SR_1_X_CNT_DIR_Msk                                                                              (0x1UL << AON_REG_LPQDEC_X_SR_1_X_CNT_DIR_Pos)
+
+#define AON_REG_LPQDEC_X_SR_1_X_PHA_STA_Pos                                                                              21U
+#define AON_REG_LPQDEC_X_SR_1_X_PHA_STA_Msk                                                                              (0x1UL << AON_REG_LPQDEC_X_SR_1_X_PHA_STA_Pos)
+
+#define AON_REG_LPQDEC_X_SR_1_X_PHB_STA_Pos                                                                              22U
+#define AON_REG_LPQDEC_X_SR_1_X_PHB_STA_Msk                                                                              (0x1UL << AON_REG_LPQDEC_X_SR_1_X_PHB_STA_Pos)
+
+#define AON_REG_LPQDEC_X_SR_1_REG_LPQDEC_X_SR_1_RESERVED31_23_Pos                                                        23U
+#define AON_REG_LPQDEC_X_SR_1_REG_LPQDEC_X_SR_1_RESERVED31_23_Msk                                                        (0x1FFUL << AON_REG_LPQDEC_X_SR_1_REG_LPQDEC_X_SR_1_RESERVED31_23_Pos)
+
+/* 0x7F0    0x4000_07f0
+    15:0    R       X_ACC_CNT                                                   16'h0
+    21:16   R       REG_LPQDEC_X_SR_2_RESERVED21                                6'h0
+    23:22   R       X_DEBUG_STATE_X                                             2'h0
+    31:24   R       X_DEBUG_ILLEGAL_COUNTER_X                                   8'h0
+ */
+typedef union _AON_REG_LPQDEC_X_SR_2_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t X_ACC_CNT: 16;
+        uint32_t REG_LPQDEC_X_SR_2_RESERVED21: 6;
+        uint32_t X_DEBUG_STATE_X: 2;
+        uint32_t X_DEBUG_ILLEGAL_COUNTER_X: 8;
+    };
+} AON_REG_LPQDEC_X_SR_2_TYPE;
+
+/*0x4000_07f0 AON_REG_LPQDEC_X_SR_2*/
+#define AON_REG_LPQDEC_X_SR_2_X_ACC_CNT_Pos                                                                              0U
+#define AON_REG_LPQDEC_X_SR_2_X_ACC_CNT_Msk                                                                              (0xFFFFUL << AON_REG_LPQDEC_X_SR_2_X_ACC_CNT_Pos)
+
+#define AON_REG_LPQDEC_X_SR_2_REG_LPQDEC_X_SR_2_RESERVED21_Pos                                                           16U
+#define AON_REG_LPQDEC_X_SR_2_REG_LPQDEC_X_SR_2_RESERVED21_Msk                                                           (0x3FUL << AON_REG_LPQDEC_X_SR_2_REG_LPQDEC_X_SR_2_RESERVED21_Pos)
+
+#define AON_REG_LPQDEC_X_SR_2_X_DEBUG_STATE_X_Pos                                                                        22U
+#define AON_REG_LPQDEC_X_SR_2_X_DEBUG_STATE_X_Msk                                                                        (0x3UL << AON_REG_LPQDEC_X_SR_2_X_DEBUG_STATE_X_Pos)
+
+#define AON_REG_LPQDEC_X_SR_2_X_DEBUG_ILLEGAL_COUNTER_X_Pos                                                              24U
+#define AON_REG_LPQDEC_X_SR_2_X_DEBUG_ILLEGAL_COUNTER_X_Msk                                                              (0xFFUL << AON_REG_LPQDEC_X_SR_2_X_DEBUG_ILLEGAL_COUNTER_X_Pos)
+
+/* 0x7F4    0x4000_07f4
+    0       R/WAC   X_ACC_CNT_CLR                                               1'h0
+    1       R/WAC   X_CNT_INT_CLR                                               1'h0
+    2       R/WAC   X_OF_FLG_CLR                                                1'h0
+    3       R/WAC   X_UF_FLG_CLR                                                1'h0
+    4       R/WAC   X_ILLEGAL_INT_CLR                                           1'h0
+    5       R/WAC   X_ILLEGAL_CNT_CLR                                           1'h0
+    31:6    R       REG_INT_CLR_RESERVED31_6                                    26'h0
+ */
+typedef union _AON_REG_LPQDEC_X_INT_CLR_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t X_ACC_CNT_CLR: 1;
+        uint32_t X_CNT_INT_CLR: 1;
+        uint32_t X_OF_FLG_CLR: 1;
+        uint32_t X_UF_FLG_CLR: 1;
+        uint32_t X_ILLEGAL_INT_CLR: 1;
+        uint32_t X_ILLEGAL_CNT_CLR: 1;
+        uint32_t REG_INT_CLR_RESERVED31_6: 26;
+    };
+} AON_REG_LPQDEC_X_INT_CLR_TYPE;
+
+/*0x4000_07f4 AON_REG_LPQDEC_X_INT_CLR*/
+#define AON_REG_LPQDEC_X_INT_CLR_X_ACC_CNT_CLR_Pos                                                                       0U
+#define AON_REG_LPQDEC_X_INT_CLR_X_ACC_CNT_CLR_Msk                                                                       (0x1UL << AON_REG_LPQDEC_X_INT_CLR_X_ACC_CNT_CLR_Pos)
+
+#define AON_REG_LPQDEC_X_INT_CLR_X_CNT_INT_CLR_Pos                                                                       1U
+#define AON_REG_LPQDEC_X_INT_CLR_X_CNT_INT_CLR_Msk                                                                       (0x1UL << AON_REG_LPQDEC_X_INT_CLR_X_CNT_INT_CLR_Pos)
+
+#define AON_REG_LPQDEC_X_INT_CLR_X_OF_FLG_CLR_Pos                                                                        2U
+#define AON_REG_LPQDEC_X_INT_CLR_X_OF_FLG_CLR_Msk                                                                        (0x1UL << AON_REG_LPQDEC_X_INT_CLR_X_OF_FLG_CLR_Pos)
+
+#define AON_REG_LPQDEC_X_INT_CLR_X_UF_FLG_CLR_Pos                                                                        3U
+#define AON_REG_LPQDEC_X_INT_CLR_X_UF_FLG_CLR_Msk                                                                        (0x1UL << AON_REG_LPQDEC_X_INT_CLR_X_UF_FLG_CLR_Pos)
+
+#define AON_REG_LPQDEC_X_INT_CLR_X_ILLEGAL_INT_CLR_Pos                                                                   4U
+#define AON_REG_LPQDEC_X_INT_CLR_X_ILLEGAL_INT_CLR_Msk                                                                   (0x1UL << AON_REG_LPQDEC_X_INT_CLR_X_ILLEGAL_INT_CLR_Pos)
+
+#define AON_REG_LPQDEC_X_INT_CLR_X_ILLEGAL_CNT_CLR_Pos                                                                   5U
+#define AON_REG_LPQDEC_X_INT_CLR_X_ILLEGAL_CNT_CLR_Msk                                                                   (0x1UL << AON_REG_LPQDEC_X_INT_CLR_X_ILLEGAL_CNT_CLR_Pos)
+
+#define AON_REG_LPQDEC_X_INT_CLR_REG_INT_CLR_RESERVED31_6_Pos                                                            6U
+#define AON_REG_LPQDEC_X_INT_CLR_REG_INT_CLR_RESERVED31_6_Msk                                                            (0x3FFFFFFUL << AON_REG_LPQDEC_X_INT_CLR_REG_INT_CLR_RESERVED31_6_Pos)
+
+/* 0x7F8    0x4000_07f8
+    31:0    R       LPQDEC_X_VERSION                                            32'h20240329
+ */
+typedef union _AON_REG_LPQDEC_X_VERSION_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t LPQDEC_X_VERSION;
+    };
+} AON_REG_LPQDEC_X_VERSION_TYPE;
+
+/*0x4000_07f8 AON_REG_LPQDEC_X_VERSION*/
+#define AON_REG_LPQDEC_X_VERSION_LPQDEC_X_VERSION_Pos                                                                    0U
+#define AON_REG_LPQDEC_X_VERSION_LPQDEC_X_VERSION_Msk                                                                    (0xFFFFFFFFUL << AON_REG_LPQDEC_X_VERSION_LPQDEC_X_VERSION_Pos)
+
+/* 0x7FC    0x4000_07fc
+    0       R/W     X_LED_EN                                                    1'h0
+    1       R/W     X_LEDPOL                                                    1'h0
+    4:2     R/W     X_LEDPRE                                                    3'h0
+    31:5    R       REG_LPQDEC_X_LED_CTRL_RESERVED31_5                          27'h0
+ */
+typedef union _AON_REG_LPQDEC_X_LED_CTRL_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t X_LED_EN: 1;
+        uint32_t X_LEDPOL: 1;
+        uint32_t X_LEDPRE: 3;
+        uint32_t REG_LPQDEC_X_LED_CTRL_RESERVED31_5: 27;
+    };
+} AON_REG_LPQDEC_X_LED_CTRL_TYPE;
+
+/*0x4000_07fc AON_REG_LPQDEC_X_LED_CTRL*/
+#define AON_REG_LPQDEC_X_LED_CTRL_X_LED_EN_Pos                                                                           0U
+#define AON_REG_LPQDEC_X_LED_CTRL_X_LED_EN_Msk                                                                           (0x1UL << AON_REG_LPQDEC_X_LED_CTRL_X_LED_EN_Pos)
+
+#define AON_REG_LPQDEC_X_LED_CTRL_X_LEDPOL_Pos                                                                           1U
+#define AON_REG_LPQDEC_X_LED_CTRL_X_LEDPOL_Msk                                                                           (0x1UL << AON_REG_LPQDEC_X_LED_CTRL_X_LEDPOL_Pos)
+
+#define AON_REG_LPQDEC_X_LED_CTRL_X_LEDPRE_Pos                                                                           2U
+#define AON_REG_LPQDEC_X_LED_CTRL_X_LEDPRE_Msk                                                                           (0x7UL << AON_REG_LPQDEC_X_LED_CTRL_X_LEDPRE_Pos)
+
+#define AON_REG_LPQDEC_X_LED_CTRL_REG_LPQDEC_X_LED_CTRL_RESERVED31_5_Pos                                                 5U
+#define AON_REG_LPQDEC_X_LED_CTRL_REG_LPQDEC_X_LED_CTRL_RESERVED31_5_Msk                                                 (0x7FFFFFFUL << AON_REG_LPQDEC_X_LED_CTRL_REG_LPQDEC_X_LED_CTRL_RESERVED31_5_Pos)
+
+/* 0x800    0x4000_0800
+    0       R/W     LPQDEC_X_QACT_SCLK_MAN_DATA                                 1'h0
+    1       R/W     LPQDEC_X_QACT_SCLK_MAN_EN                                   1'h0
+    2       R/W     LPQDEC_X_QACT_PCLK_MAN_DATA                                 1'h0
+    3       R/W     LPQDEC_X_QACT_PCLK_MAN_EN                                   1'h0
+    31:4    R       REG_QACTIVE_CTRL_RESERVED31_4                               28'h0
+ */
+typedef union _AON_REG_LPQDEC_X_QACTIVE_CTRL_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t LPQDEC_X_QACT_SCLK_MAN_DATA: 1;
+        uint32_t LPQDEC_X_QACT_SCLK_MAN_EN: 1;
+        uint32_t LPQDEC_X_QACT_PCLK_MAN_DATA: 1;
+        uint32_t LPQDEC_X_QACT_PCLK_MAN_EN: 1;
+        uint32_t REG_QACTIVE_CTRL_RESERVED31_4: 28;
+    };
+} AON_REG_LPQDEC_X_QACTIVE_CTRL_TYPE;
+
+/*0x4000_0800 AON_REG_LPQDEC_X_QACTIVE_CTRL*/
+#define AON_REG_LPQDEC_X_QACTIVE_CTRL_LPQDEC_X_QACT_SCLK_MAN_DATA_Pos                                                    0U
+#define AON_REG_LPQDEC_X_QACTIVE_CTRL_LPQDEC_X_QACT_SCLK_MAN_DATA_Msk                                                    (0x1UL << AON_REG_LPQDEC_X_QACTIVE_CTRL_LPQDEC_X_QACT_SCLK_MAN_DATA_Pos)
+
+#define AON_REG_LPQDEC_X_QACTIVE_CTRL_LPQDEC_X_QACT_SCLK_MAN_EN_Pos                                                      1U
+#define AON_REG_LPQDEC_X_QACTIVE_CTRL_LPQDEC_X_QACT_SCLK_MAN_EN_Msk                                                      (0x1UL << AON_REG_LPQDEC_X_QACTIVE_CTRL_LPQDEC_X_QACT_SCLK_MAN_EN_Pos)
+
+#define AON_REG_LPQDEC_X_QACTIVE_CTRL_LPQDEC_X_QACT_PCLK_MAN_DATA_Pos                                                    2U
+#define AON_REG_LPQDEC_X_QACTIVE_CTRL_LPQDEC_X_QACT_PCLK_MAN_DATA_Msk                                                    (0x1UL << AON_REG_LPQDEC_X_QACTIVE_CTRL_LPQDEC_X_QACT_PCLK_MAN_DATA_Pos)
+
+#define AON_REG_LPQDEC_X_QACTIVE_CTRL_LPQDEC_X_QACT_PCLK_MAN_EN_Pos                                                      3U
+#define AON_REG_LPQDEC_X_QACTIVE_CTRL_LPQDEC_X_QACT_PCLK_MAN_EN_Msk                                                      (0x1UL << AON_REG_LPQDEC_X_QACTIVE_CTRL_LPQDEC_X_QACT_PCLK_MAN_EN_Pos)
+
+#define AON_REG_LPQDEC_X_QACTIVE_CTRL_REG_QACTIVE_CTRL_RESERVED31_4_Pos                                                  4U
+#define AON_REG_LPQDEC_X_QACTIVE_CTRL_REG_QACTIVE_CTRL_RESERVED31_4_Msk                                                  (0xFFFFFFFUL << AON_REG_LPQDEC_X_QACTIVE_CTRL_REG_QACTIVE_CTRL_RESERVED31_4_Pos)
+
+/* 0x80C    0x4000_080c
+    0       R/W     LPPWM_CH0_REG_RST_N                                         1'h0
+    1       R/W     LPPWM_CH0_EN                                                1'h0
+    2       R/W     LPPWM_CH0_POLARITY                                          1'h0
+    31:3    R       RSVD                                                        29'h0
+ */
+typedef union _AON_REG_LPPWM_CH0_CTL_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t LPPWM_CH0_REG_RST_N: 1;
+        uint32_t LPPWM_CH0_EN: 1;
+        uint32_t LPPWM_CH0_POLARITY: 1;
+        uint32_t RSVD: 29;
+    };
+} AON_REG_LPPWM_CH0_CTL_TYPE;
+
+/*0x4000_080c AON_REG_LPPWM_CH0_CTL*/
+#define AON_REG_LPPWM_CH0_CTL_LPPWM_CH0_REG_RST_N_Pos                                                                    0U
+#define AON_REG_LPPWM_CH0_CTL_LPPWM_CH0_REG_RST_N_Msk                                                                    (0x1UL << AON_REG_LPPWM_CH0_CTL_LPPWM_CH0_REG_RST_N_Pos)
+
+#define AON_REG_LPPWM_CH0_CTL_LPPWM_CH0_EN_Pos                                                                           1U
+#define AON_REG_LPPWM_CH0_CTL_LPPWM_CH0_EN_Msk                                                                           (0x1UL << AON_REG_LPPWM_CH0_CTL_LPPWM_CH0_EN_Pos)
+
+#define AON_REG_LPPWM_CH0_CTL_LPPWM_CH0_POLARITY_Pos                                                                     2U
+#define AON_REG_LPPWM_CH0_CTL_LPPWM_CH0_POLARITY_Msk                                                                     (0x1UL << AON_REG_LPPWM_CH0_CTL_LPPWM_CH0_POLARITY_Pos)
+
+#define AON_REG_LPPWM_CH0_CTL_RSVD_Pos                                                                                   3U
+#define AON_REG_LPPWM_CH0_CTL_RSVD_Msk                                                                                   (0x1FFFFFFFUL << AON_REG_LPPWM_CH0_CTL_RSVD_Pos)
+
+/* 0x810    0x4000_0810
+    15:0    R/W     LPPWM_CH0_P0_H                                              16'h0
+    31:16   R       RSVD                                                        16'h0
+ */
+typedef union _AON_REG_LPPWM_CH0_P0_H_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t LPPWM_CH0_P0_H: 16;
+        uint32_t RSVD: 16;
+    };
+} AON_REG_LPPWM_CH0_P0_H_TYPE;
+
+/*0x4000_0810 AON_REG_LPPWM_CH0_P0_H*/
+#define AON_REG_LPPWM_CH0_P0_H_LPPWM_CH0_P0_H_Pos                                                                        0U
+#define AON_REG_LPPWM_CH0_P0_H_LPPWM_CH0_P0_H_Msk                                                                        (0xFFFFUL << AON_REG_LPPWM_CH0_P0_H_LPPWM_CH0_P0_H_Pos)
+
+#define AON_REG_LPPWM_CH0_P0_H_RSVD_Pos                                                                                  16U
+#define AON_REG_LPPWM_CH0_P0_H_RSVD_Msk                                                                                  (0xFFFFUL << AON_REG_LPPWM_CH0_P0_H_RSVD_Pos)
+
+/* 0x814    0x4000_0814
+    15:0    R/W     LPPWM_CH0_P0_L                                              16'h0
+    31:16   R       RSVD                                                        16'h0
+ */
+typedef union _AON_REG_LPPWM_CH0_P0_L_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t LPPWM_CH0_P0_L: 16;
+        uint32_t RSVD: 16;
+    };
+} AON_REG_LPPWM_CH0_P0_L_TYPE;
+
+/*0x4000_0814 AON_REG_LPPWM_CH0_P0_L*/
+#define AON_REG_LPPWM_CH0_P0_L_LPPWM_CH0_P0_L_Pos                                                                        0U
+#define AON_REG_LPPWM_CH0_P0_L_LPPWM_CH0_P0_L_Msk                                                                        (0xFFFFUL << AON_REG_LPPWM_CH0_P0_L_LPPWM_CH0_P0_L_Pos)
+
+#define AON_REG_LPPWM_CH0_P0_L_RSVD_Pos                                                                                  16U
+#define AON_REG_LPPWM_CH0_P0_L_RSVD_Msk                                                                                  (0xFFFFUL << AON_REG_LPPWM_CH0_P0_L_RSVD_Pos)
+
+/* 0x818    0x4000_0818
+    15:0    R       LPPWM_CH0_CURRENT                                           16'h0
+    31:16   R       RSVD                                                        16'h0
+ */
+typedef union _AON_REG_LPPWM_CH0_CURRENT_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t LPPWM_CH0_CURRENT: 16;
+        uint32_t RSVD: 16;
+    };
+} AON_REG_LPPWM_CH0_CURRENT_TYPE;
+
+/*0x4000_0818 AON_REG_LPPWM_CH0_CURRENT*/
+#define AON_REG_LPPWM_CH0_CURRENT_LPPWM_CH0_CURRENT_Pos                                                                  0U
+#define AON_REG_LPPWM_CH0_CURRENT_LPPWM_CH0_CURRENT_Msk                                                                  (0xFFFFUL << AON_REG_LPPWM_CH0_CURRENT_LPPWM_CH0_CURRENT_Pos)
+
+#define AON_REG_LPPWM_CH0_CURRENT_RSVD_Pos                                                                               16U
+#define AON_REG_LPPWM_CH0_CURRENT_RSVD_Msk                                                                               (0xFFFFUL << AON_REG_LPPWM_CH0_CURRENT_RSVD_Pos)
+
+/* 0x81C    0x4000_081c
+    31:0    R       LPPWM_VERSION                                               32'h2305230A
+ */
+typedef union _AON_REG_LPPWM_VERSION_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t LPPWM_VERSION;
+    };
+} AON_REG_LPPWM_VERSION_TYPE;
+
+/*0x4000_081c AON_REG_LPPWM_VERSION*/
+#define AON_REG_LPPWM_VERSION_LPPWM_VERSION_Pos                                                                          0U
+#define AON_REG_LPPWM_VERSION_LPPWM_VERSION_Msk                                                                          (0xFFFFFFFFUL << AON_REG_LPPWM_VERSION_LPPWM_VERSION_Pos)
+
+/* 0x820    0x4000_0820
+    0       R/W     LPPWM_CLK_QACTIVE_MAN_DATA                                  1'h0
+    1       R/W     LPPWM_CLK_QACTIVE_MAN_ENABLE                                1'h0
+    31:2    R       RSVD                                                        30'h0
+ */
+typedef union _AON_REG_LPPWM_QACTIVE_MANUAL_CTRL_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t LPPWM_CLK_QACTIVE_MAN_DATA: 1;
+        uint32_t LPPWM_CLK_QACTIVE_MAN_ENABLE: 1;
+        uint32_t RSVD: 30;
+    };
+} AON_REG_LPPWM_QACTIVE_MANUAL_CTRL_TYPE;
+
+/*0x4000_0820 AON_REG_LPPWM_QACTIVE_MANUAL_CTRL*/
+#define AON_REG_LPPWM_QACTIVE_MANUAL_CTRL_LPPWM_CLK_QACTIVE_MAN_DATA_Pos                                                 0U
+#define AON_REG_LPPWM_QACTIVE_MANUAL_CTRL_LPPWM_CLK_QACTIVE_MAN_DATA_Msk                                                 (0x1UL << AON_REG_LPPWM_QACTIVE_MANUAL_CTRL_LPPWM_CLK_QACTIVE_MAN_DATA_Pos)
+
+#define AON_REG_LPPWM_QACTIVE_MANUAL_CTRL_LPPWM_CLK_QACTIVE_MAN_ENABLE_Pos                                               1U
+#define AON_REG_LPPWM_QACTIVE_MANUAL_CTRL_LPPWM_CLK_QACTIVE_MAN_ENABLE_Msk                                               (0x1UL << AON_REG_LPPWM_QACTIVE_MANUAL_CTRL_LPPWM_CLK_QACTIVE_MAN_ENABLE_Pos)
+
+#define AON_REG_LPPWM_QACTIVE_MANUAL_CTRL_RSVD_Pos                                                                       2U
+#define AON_REG_LPPWM_QACTIVE_MANUAL_CTRL_RSVD_Msk                                                                       (0x3FFFFFFFUL << AON_REG_LPPWM_QACTIVE_MANUAL_CTRL_RSVD_Pos)
+
+/* 0x828    0x4000_0828
+    0       R/W     TEST1_lemst                                                 1'b0
+    1       R/W     DS_low_pwr_lemst                                            1'b0
+    2       R/W     SD_low_pwr_lemst                                            1'b0
+    3       R/W     LS_low_pwr_lemst                                            1'b0
+    4       R/W     DS_UNK_low_pwr_lemst                                        1'b0
+    6:5     R/W     DS_K_low_pwr_lemst                                          2'b01
+    7       R/W     DS_norm_pwr_lemst                                           1'b0
+    8       R/W     SD_norm_pwr_lemst                                           1'b0
+    9       R/W     LS_norm_pwr_lemst                                           1'b0
+    10      R/W     DS_UNK_norm_pwr_lemst                                       1'b0
+    12:11   R/W     DS_K_norm_pwr_lemst                                         2'b01
+    31:13   R       RSVD                                                        0
+ */
+typedef union _AON_REG_SRAM_CTRL0_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t TEST1_lemst: 1;
+        uint32_t DS_low_pwr_lemst: 1;
+        uint32_t SD_low_pwr_lemst: 1;
+        uint32_t LS_low_pwr_lemst: 1;
+        uint32_t DS_UNK_low_pwr_lemst: 1;
+        uint32_t DS_K_low_pwr_lemst: 2;
+        uint32_t DS_norm_pwr_lemst: 1;
+        uint32_t SD_norm_pwr_lemst: 1;
+        uint32_t LS_norm_pwr_lemst: 1;
+        uint32_t DS_UNK_norm_pwr_lemst: 1;
+        uint32_t DS_K_norm_pwr_lemst: 2;
+        uint32_t RSVD: 19;
+    };
+} AON_REG_SRAM_CTRL0_TYPE;
+
+/*0x4000_0828 AON_REG_SRAM_CTRL0*/
+#define AON_REG_SRAM_CTRL0_TEST1_lemst_Pos                                                                               0U
+#define AON_REG_SRAM_CTRL0_TEST1_lemst_Msk                                                                               (0x1UL << AON_REG_SRAM_CTRL0_TEST1_lemst_Pos)
+
+#define AON_REG_SRAM_CTRL0_DS_low_pwr_lemst_Pos                                                                          1U
+#define AON_REG_SRAM_CTRL0_DS_low_pwr_lemst_Msk                                                                          (0x1UL << AON_REG_SRAM_CTRL0_DS_low_pwr_lemst_Pos)
+
+#define AON_REG_SRAM_CTRL0_SD_low_pwr_lemst_Pos                                                                          2U
+#define AON_REG_SRAM_CTRL0_SD_low_pwr_lemst_Msk                                                                          (0x1UL << AON_REG_SRAM_CTRL0_SD_low_pwr_lemst_Pos)
+
+#define AON_REG_SRAM_CTRL0_LS_low_pwr_lemst_Pos                                                                          3U
+#define AON_REG_SRAM_CTRL0_LS_low_pwr_lemst_Msk                                                                          (0x1UL << AON_REG_SRAM_CTRL0_LS_low_pwr_lemst_Pos)
+
+#define AON_REG_SRAM_CTRL0_DS_UNK_low_pwr_lemst_Pos                                                                      4U
+#define AON_REG_SRAM_CTRL0_DS_UNK_low_pwr_lemst_Msk                                                                      (0x1UL << AON_REG_SRAM_CTRL0_DS_UNK_low_pwr_lemst_Pos)
+
+#define AON_REG_SRAM_CTRL0_DS_K_low_pwr_lemst_Pos                                                                        5U
+#define AON_REG_SRAM_CTRL0_DS_K_low_pwr_lemst_Msk                                                                        (0x3UL << AON_REG_SRAM_CTRL0_DS_K_low_pwr_lemst_Pos)
+
+#define AON_REG_SRAM_CTRL0_DS_norm_pwr_lemst_Pos                                                                         7U
+#define AON_REG_SRAM_CTRL0_DS_norm_pwr_lemst_Msk                                                                         (0x1UL << AON_REG_SRAM_CTRL0_DS_norm_pwr_lemst_Pos)
+
+#define AON_REG_SRAM_CTRL0_SD_norm_pwr_lemst_Pos                                                                         8U
+#define AON_REG_SRAM_CTRL0_SD_norm_pwr_lemst_Msk                                                                         (0x1UL << AON_REG_SRAM_CTRL0_SD_norm_pwr_lemst_Pos)
+
+#define AON_REG_SRAM_CTRL0_LS_norm_pwr_lemst_Pos                                                                         9U
+#define AON_REG_SRAM_CTRL0_LS_norm_pwr_lemst_Msk                                                                         (0x1UL << AON_REG_SRAM_CTRL0_LS_norm_pwr_lemst_Pos)
+
+#define AON_REG_SRAM_CTRL0_DS_UNK_norm_pwr_lemst_Pos                                                                     10U
+#define AON_REG_SRAM_CTRL0_DS_UNK_norm_pwr_lemst_Msk                                                                     (0x1UL << AON_REG_SRAM_CTRL0_DS_UNK_norm_pwr_lemst_Pos)
+
+#define AON_REG_SRAM_CTRL0_DS_K_norm_pwr_lemst_Pos                                                                       11U
+#define AON_REG_SRAM_CTRL0_DS_K_norm_pwr_lemst_Msk                                                                       (0x3UL << AON_REG_SRAM_CTRL0_DS_K_norm_pwr_lemst_Pos)
+
+#define AON_REG_SRAM_CTRL0_RSVD_Pos                                                                                      13U
+#define AON_REG_SRAM_CTRL0_RSVD_Msk                                                                                      (0x7FFFFUL << AON_REG_SRAM_CTRL0_RSVD_Pos)
+
+/* 0x82C    0x4000_082c
+    2:0     R/W     WPULSE_lemst_lv                                             3'b000
+    5:3     R/W     WA_lemst_lv                                                 3'b110
+    9:6     R/W     RM_lemst_lv                                                 4'b0000
+    10      R/W     RME_lemst_lv                                                1'b1
+    12:11   R/W     RA_lemst_lv                                                 2'b01
+    15:13   R       RSVD_1                                                      0
+    18:16   R/W     WPULSE_lemst_hv                                             3'b000
+    21:19   R/W     WA_lemst_hv                                                 3'b100
+    25:22   R/W     RM_lemst_hv                                                 4'b0011
+    26      R/W     RME_lemst_hv                                                1'b1
+    28:27   R/W     RA_lemst_hv                                                 2'b00
+    31:29   R       RSVD                                                        0
+ */
+typedef union _AON_REG_SRAM_CTRL1_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t WPULSE_lemst_lv: 3;
+        uint32_t WA_lemst_lv: 3;
+        uint32_t RM_lemst_lv: 4;
+        uint32_t RME_lemst_lv: 1;
+        uint32_t RA_lemst_lv: 2;
+        uint32_t RSVD_1: 3;
+        uint32_t WPULSE_lemst_hv: 3;
+        uint32_t WA_lemst_hv: 3;
+        uint32_t RM_lemst_hv: 4;
+        uint32_t RME_lemst_hv: 1;
+        uint32_t RA_lemst_hv: 2;
+        uint32_t RSVD: 3;
+    };
+} AON_REG_SRAM_CTRL1_TYPE;
+
+/*0x4000_082c AON_REG_SRAM_CTRL1*/
+#define AON_REG_SRAM_CTRL1_WPULSE_lemst_lv_Pos                                                                           0U
+#define AON_REG_SRAM_CTRL1_WPULSE_lemst_lv_Msk                                                                           (0x7UL << AON_REG_SRAM_CTRL1_WPULSE_lemst_lv_Pos)
+
+#define AON_REG_SRAM_CTRL1_WA_lemst_lv_Pos                                                                               3U
+#define AON_REG_SRAM_CTRL1_WA_lemst_lv_Msk                                                                               (0x7UL << AON_REG_SRAM_CTRL1_WA_lemst_lv_Pos)
+
+#define AON_REG_SRAM_CTRL1_RM_lemst_lv_Pos                                                                               6U
+#define AON_REG_SRAM_CTRL1_RM_lemst_lv_Msk                                                                               (0xFUL << AON_REG_SRAM_CTRL1_RM_lemst_lv_Pos)
+
+#define AON_REG_SRAM_CTRL1_RME_lemst_lv_Pos                                                                              10U
+#define AON_REG_SRAM_CTRL1_RME_lemst_lv_Msk                                                                              (0x1UL << AON_REG_SRAM_CTRL1_RME_lemst_lv_Pos)
+
+#define AON_REG_SRAM_CTRL1_RA_lemst_lv_Pos                                                                               11U
+#define AON_REG_SRAM_CTRL1_RA_lemst_lv_Msk                                                                               (0x3UL << AON_REG_SRAM_CTRL1_RA_lemst_lv_Pos)
+
+#define AON_REG_SRAM_CTRL1_RSVD_1_Pos                                                                                    13U
+#define AON_REG_SRAM_CTRL1_RSVD_1_Msk                                                                                    (0x7UL << AON_REG_SRAM_CTRL1_RSVD_1_Pos)
+
+#define AON_REG_SRAM_CTRL1_WPULSE_lemst_hv_Pos                                                                           16U
+#define AON_REG_SRAM_CTRL1_WPULSE_lemst_hv_Msk                                                                           (0x7UL << AON_REG_SRAM_CTRL1_WPULSE_lemst_hv_Pos)
+
+#define AON_REG_SRAM_CTRL1_WA_lemst_hv_Pos                                                                               19U
+#define AON_REG_SRAM_CTRL1_WA_lemst_hv_Msk                                                                               (0x7UL << AON_REG_SRAM_CTRL1_WA_lemst_hv_Pos)
+
+#define AON_REG_SRAM_CTRL1_RM_lemst_hv_Pos                                                                               22U
+#define AON_REG_SRAM_CTRL1_RM_lemst_hv_Msk                                                                               (0xFUL << AON_REG_SRAM_CTRL1_RM_lemst_hv_Pos)
+
+#define AON_REG_SRAM_CTRL1_RME_lemst_hv_Pos                                                                              26U
+#define AON_REG_SRAM_CTRL1_RME_lemst_hv_Msk                                                                              (0x1UL << AON_REG_SRAM_CTRL1_RME_lemst_hv_Pos)
+
+#define AON_REG_SRAM_CTRL1_RA_lemst_hv_Pos                                                                               27U
+#define AON_REG_SRAM_CTRL1_RA_lemst_hv_Msk                                                                               (0x3UL << AON_REG_SRAM_CTRL1_RA_lemst_hv_Pos)
+
+#define AON_REG_SRAM_CTRL1_RSVD_Pos                                                                                      29U
+#define AON_REG_SRAM_CTRL1_RSVD_Msk                                                                                      (0x7UL << AON_REG_SRAM_CTRL1_RSVD_Pos)
+
+/* 0x830    0x4000_0830
+    0       R/W     TEST1_lepa                                                  1'b0
+    1       R/W     DS_low_pwr_lepa                                             1'b0
+    2       R/W     SD_low_pwr_lepa                                             1'b0
+    3       R/W     LS_low_pwr_lepa                                             1'b0
+    4       R/W     DS_UNK_low_pwr_lepa                                         1'b0
+    6:5     R/W     DS_K_low_pwr_lepa                                           2'b01
+    7       R/W     DS_norm_pwr_lepa                                            1'b0
+    8       R/W     SD_norm_pwr_lepa                                            1'b0
+    9       R/W     LS_norm_pwr_lepa                                            1'b0
+    10      R/W     DS_UNK_norm_pwr_lepa                                        1'b0
+    12:11   R/W     DS_K_norm_pwr_lepa                                          2'b01
+    31:13   R       RSVD                                                        0
+ */
+typedef union _AON_REG_SRAM_CTRL2_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t TEST1_lepa: 1;
+        uint32_t DS_low_pwr_lepa: 1;
+        uint32_t SD_low_pwr_lepa: 1;
+        uint32_t LS_low_pwr_lepa: 1;
+        uint32_t DS_UNK_low_pwr_lepa: 1;
+        uint32_t DS_K_low_pwr_lepa: 2;
+        uint32_t DS_norm_pwr_lepa: 1;
+        uint32_t SD_norm_pwr_lepa: 1;
+        uint32_t LS_norm_pwr_lepa: 1;
+        uint32_t DS_UNK_norm_pwr_lepa: 1;
+        uint32_t DS_K_norm_pwr_lepa: 2;
+        uint32_t RSVD: 19;
+    };
+} AON_REG_SRAM_CTRL2_TYPE;
+
+/*0x4000_0830 AON_REG_SRAM_CTRL2*/
+#define AON_REG_SRAM_CTRL2_TEST1_lepa_Pos                                                                                0U
+#define AON_REG_SRAM_CTRL2_TEST1_lepa_Msk                                                                                (0x1UL << AON_REG_SRAM_CTRL2_TEST1_lepa_Pos)
+
+#define AON_REG_SRAM_CTRL2_DS_low_pwr_lepa_Pos                                                                           1U
+#define AON_REG_SRAM_CTRL2_DS_low_pwr_lepa_Msk                                                                           (0x1UL << AON_REG_SRAM_CTRL2_DS_low_pwr_lepa_Pos)
+
+#define AON_REG_SRAM_CTRL2_SD_low_pwr_lepa_Pos                                                                           2U
+#define AON_REG_SRAM_CTRL2_SD_low_pwr_lepa_Msk                                                                           (0x1UL << AON_REG_SRAM_CTRL2_SD_low_pwr_lepa_Pos)
+
+#define AON_REG_SRAM_CTRL2_LS_low_pwr_lepa_Pos                                                                           3U
+#define AON_REG_SRAM_CTRL2_LS_low_pwr_lepa_Msk                                                                           (0x1UL << AON_REG_SRAM_CTRL2_LS_low_pwr_lepa_Pos)
+
+#define AON_REG_SRAM_CTRL2_DS_UNK_low_pwr_lepa_Pos                                                                       4U
+#define AON_REG_SRAM_CTRL2_DS_UNK_low_pwr_lepa_Msk                                                                       (0x1UL << AON_REG_SRAM_CTRL2_DS_UNK_low_pwr_lepa_Pos)
+
+#define AON_REG_SRAM_CTRL2_DS_K_low_pwr_lepa_Pos                                                                         5U
+#define AON_REG_SRAM_CTRL2_DS_K_low_pwr_lepa_Msk                                                                         (0x3UL << AON_REG_SRAM_CTRL2_DS_K_low_pwr_lepa_Pos)
+
+#define AON_REG_SRAM_CTRL2_DS_norm_pwr_lepa_Pos                                                                          7U
+#define AON_REG_SRAM_CTRL2_DS_norm_pwr_lepa_Msk                                                                          (0x1UL << AON_REG_SRAM_CTRL2_DS_norm_pwr_lepa_Pos)
+
+#define AON_REG_SRAM_CTRL2_SD_norm_pwr_lepa_Pos                                                                          8U
+#define AON_REG_SRAM_CTRL2_SD_norm_pwr_lepa_Msk                                                                          (0x1UL << AON_REG_SRAM_CTRL2_SD_norm_pwr_lepa_Pos)
+
+#define AON_REG_SRAM_CTRL2_LS_norm_pwr_lepa_Pos                                                                          9U
+#define AON_REG_SRAM_CTRL2_LS_norm_pwr_lepa_Msk                                                                          (0x1UL << AON_REG_SRAM_CTRL2_LS_norm_pwr_lepa_Pos)
+
+#define AON_REG_SRAM_CTRL2_DS_UNK_norm_pwr_lepa_Pos                                                                      10U
+#define AON_REG_SRAM_CTRL2_DS_UNK_norm_pwr_lepa_Msk                                                                      (0x1UL << AON_REG_SRAM_CTRL2_DS_UNK_norm_pwr_lepa_Pos)
+
+#define AON_REG_SRAM_CTRL2_DS_K_norm_pwr_lepa_Pos                                                                        11U
+#define AON_REG_SRAM_CTRL2_DS_K_norm_pwr_lepa_Msk                                                                        (0x3UL << AON_REG_SRAM_CTRL2_DS_K_norm_pwr_lepa_Pos)
+
+#define AON_REG_SRAM_CTRL2_RSVD_Pos                                                                                      13U
+#define AON_REG_SRAM_CTRL2_RSVD_Msk                                                                                      (0x7FFFFUL << AON_REG_SRAM_CTRL2_RSVD_Pos)
+
+/* 0x834    0x4000_0834
+    2:0     R/W     WPULSE_lepa_lv                                              3'b000
+    5:3     R/W     WA_lepa_lv                                                  3'b101
+    9:6     R/W     RM_lepa_lv                                                  4'b0010
+    10      R/W     RME_lepa_lv                                                 1'b1
+    12:11   R/W     RA_lepa_lv                                                  2'b00
+    15:13   R       RSVD_1                                                      0
+    18:16   R/W     WPULSE_lepa_hv                                              3'b000
+    21:19   R/W     WA_lepa_hv                                                  3'b100
+    25:22   R/W     RM_lepa_hv                                                  4'b0011
+    26      R/W     RME_lepa_hv                                                 1'b1
+    28:27   R/W     RA_lepa_hv                                                  2'b00
+    31:29   R       RSVD                                                        0
+ */
+typedef union _AON_REG_SRAM_CTRL3_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t WPULSE_lepa_lv: 3;
+        uint32_t WA_lepa_lv: 3;
+        uint32_t RM_lepa_lv: 4;
+        uint32_t RME_lepa_lv: 1;
+        uint32_t RA_lepa_lv: 2;
+        uint32_t RSVD_1: 3;
+        uint32_t WPULSE_lepa_hv: 3;
+        uint32_t WA_lepa_hv: 3;
+        uint32_t RM_lepa_hv: 4;
+        uint32_t RME_lepa_hv: 1;
+        uint32_t RA_lepa_hv: 2;
+        uint32_t RSVD: 3;
+    };
+} AON_REG_SRAM_CTRL3_TYPE;
+
+/*0x4000_0834 AON_REG_SRAM_CTRL3*/
+#define AON_REG_SRAM_CTRL3_WPULSE_lepa_lv_Pos                                                                            0U
+#define AON_REG_SRAM_CTRL3_WPULSE_lepa_lv_Msk                                                                            (0x7UL << AON_REG_SRAM_CTRL3_WPULSE_lepa_lv_Pos)
+
+#define AON_REG_SRAM_CTRL3_WA_lepa_lv_Pos                                                                                3U
+#define AON_REG_SRAM_CTRL3_WA_lepa_lv_Msk                                                                                (0x7UL << AON_REG_SRAM_CTRL3_WA_lepa_lv_Pos)
+
+#define AON_REG_SRAM_CTRL3_RM_lepa_lv_Pos                                                                                6U
+#define AON_REG_SRAM_CTRL3_RM_lepa_lv_Msk                                                                                (0xFUL << AON_REG_SRAM_CTRL3_RM_lepa_lv_Pos)
+
+#define AON_REG_SRAM_CTRL3_RME_lepa_lv_Pos                                                                               10U
+#define AON_REG_SRAM_CTRL3_RME_lepa_lv_Msk                                                                               (0x1UL << AON_REG_SRAM_CTRL3_RME_lepa_lv_Pos)
+
+#define AON_REG_SRAM_CTRL3_RA_lepa_lv_Pos                                                                                11U
+#define AON_REG_SRAM_CTRL3_RA_lepa_lv_Msk                                                                                (0x3UL << AON_REG_SRAM_CTRL3_RA_lepa_lv_Pos)
+
+#define AON_REG_SRAM_CTRL3_RSVD_1_Pos                                                                                    13U
+#define AON_REG_SRAM_CTRL3_RSVD_1_Msk                                                                                    (0x7UL << AON_REG_SRAM_CTRL3_RSVD_1_Pos)
+
+#define AON_REG_SRAM_CTRL3_WPULSE_lepa_hv_Pos                                                                            16U
+#define AON_REG_SRAM_CTRL3_WPULSE_lepa_hv_Msk                                                                            (0x7UL << AON_REG_SRAM_CTRL3_WPULSE_lepa_hv_Pos)
+
+#define AON_REG_SRAM_CTRL3_WA_lepa_hv_Pos                                                                                19U
+#define AON_REG_SRAM_CTRL3_WA_lepa_hv_Msk                                                                                (0x7UL << AON_REG_SRAM_CTRL3_WA_lepa_hv_Pos)
+
+#define AON_REG_SRAM_CTRL3_RM_lepa_hv_Pos                                                                                22U
+#define AON_REG_SRAM_CTRL3_RM_lepa_hv_Msk                                                                                (0xFUL << AON_REG_SRAM_CTRL3_RM_lepa_hv_Pos)
+
+#define AON_REG_SRAM_CTRL3_RME_lepa_hv_Pos                                                                               26U
+#define AON_REG_SRAM_CTRL3_RME_lepa_hv_Msk                                                                               (0x1UL << AON_REG_SRAM_CTRL3_RME_lepa_hv_Pos)
+
+#define AON_REG_SRAM_CTRL3_RA_lepa_hv_Pos                                                                                27U
+#define AON_REG_SRAM_CTRL3_RA_lepa_hv_Msk                                                                                (0x3UL << AON_REG_SRAM_CTRL3_RA_lepa_hv_Pos)
+
+#define AON_REG_SRAM_CTRL3_RSVD_Pos                                                                                      29U
+#define AON_REG_SRAM_CTRL3_RSVD_Msk                                                                                      (0x7UL << AON_REG_SRAM_CTRL3_RSVD_Pos)
+
+/* 0x838    0x4000_0838
+    0       R/W     TEST1_leslv                                                 1'b0
+    1       R/W     DS_low_pwr_leslv                                            1'b0
+    2       R/W     SD_low_pwr_leslv                                            1'b0
+    3       R/W     LS_low_pwr_leslv                                            1'b0
+    4       R/W     DS_UNK_low_pwr_leslv                                        1'b0
+    6:5     R/W     DS_K_low_pwr_leslv                                          2'b01
+    7       R/W     DS_norm_pwr_leslv                                           1'b0
+    8       R/W     SD_norm_pwr_leslv                                           1'b0
+    9       R/W     LS_norm_pwr_leslv                                           1'b0
+    10      R/W     DS_UNK_norm_pwr_leslv                                       1'b0
+    12:11   R/W     DS_K_norm_pwr_leslv                                         2'b01
+    31:13   R       RSVD                                                        0
+ */
+typedef union _AON_REG_SRAM_CTRL4_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t TEST1_leslv: 1;
+        uint32_t DS_low_pwr_leslv: 1;
+        uint32_t SD_low_pwr_leslv: 1;
+        uint32_t LS_low_pwr_leslv: 1;
+        uint32_t DS_UNK_low_pwr_leslv: 1;
+        uint32_t DS_K_low_pwr_leslv: 2;
+        uint32_t DS_norm_pwr_leslv: 1;
+        uint32_t SD_norm_pwr_leslv: 1;
+        uint32_t LS_norm_pwr_leslv: 1;
+        uint32_t DS_UNK_norm_pwr_leslv: 1;
+        uint32_t DS_K_norm_pwr_leslv: 2;
+        uint32_t RSVD: 19;
+    };
+} AON_REG_SRAM_CTRL4_TYPE;
+
+/*0x4000_0838 AON_REG_SRAM_CTRL4*/
+#define AON_REG_SRAM_CTRL4_TEST1_leslv_Pos                                                                               0U
+#define AON_REG_SRAM_CTRL4_TEST1_leslv_Msk                                                                               (0x1UL << AON_REG_SRAM_CTRL4_TEST1_leslv_Pos)
+
+#define AON_REG_SRAM_CTRL4_DS_low_pwr_leslv_Pos                                                                          1U
+#define AON_REG_SRAM_CTRL4_DS_low_pwr_leslv_Msk                                                                          (0x1UL << AON_REG_SRAM_CTRL4_DS_low_pwr_leslv_Pos)
+
+#define AON_REG_SRAM_CTRL4_SD_low_pwr_leslv_Pos                                                                          2U
+#define AON_REG_SRAM_CTRL4_SD_low_pwr_leslv_Msk                                                                          (0x1UL << AON_REG_SRAM_CTRL4_SD_low_pwr_leslv_Pos)
+
+#define AON_REG_SRAM_CTRL4_LS_low_pwr_leslv_Pos                                                                          3U
+#define AON_REG_SRAM_CTRL4_LS_low_pwr_leslv_Msk                                                                          (0x1UL << AON_REG_SRAM_CTRL4_LS_low_pwr_leslv_Pos)
+
+#define AON_REG_SRAM_CTRL4_DS_UNK_low_pwr_leslv_Pos                                                                      4U
+#define AON_REG_SRAM_CTRL4_DS_UNK_low_pwr_leslv_Msk                                                                      (0x1UL << AON_REG_SRAM_CTRL4_DS_UNK_low_pwr_leslv_Pos)
+
+#define AON_REG_SRAM_CTRL4_DS_K_low_pwr_leslv_Pos                                                                        5U
+#define AON_REG_SRAM_CTRL4_DS_K_low_pwr_leslv_Msk                                                                        (0x3UL << AON_REG_SRAM_CTRL4_DS_K_low_pwr_leslv_Pos)
+
+#define AON_REG_SRAM_CTRL4_DS_norm_pwr_leslv_Pos                                                                         7U
+#define AON_REG_SRAM_CTRL4_DS_norm_pwr_leslv_Msk                                                                         (0x1UL << AON_REG_SRAM_CTRL4_DS_norm_pwr_leslv_Pos)
+
+#define AON_REG_SRAM_CTRL4_SD_norm_pwr_leslv_Pos                                                                         8U
+#define AON_REG_SRAM_CTRL4_SD_norm_pwr_leslv_Msk                                                                         (0x1UL << AON_REG_SRAM_CTRL4_SD_norm_pwr_leslv_Pos)
+
+#define AON_REG_SRAM_CTRL4_LS_norm_pwr_leslv_Pos                                                                         9U
+#define AON_REG_SRAM_CTRL4_LS_norm_pwr_leslv_Msk                                                                         (0x1UL << AON_REG_SRAM_CTRL4_LS_norm_pwr_leslv_Pos)
+
+#define AON_REG_SRAM_CTRL4_DS_UNK_norm_pwr_leslv_Pos                                                                     10U
+#define AON_REG_SRAM_CTRL4_DS_UNK_norm_pwr_leslv_Msk                                                                     (0x1UL << AON_REG_SRAM_CTRL4_DS_UNK_norm_pwr_leslv_Pos)
+
+#define AON_REG_SRAM_CTRL4_DS_K_norm_pwr_leslv_Pos                                                                       11U
+#define AON_REG_SRAM_CTRL4_DS_K_norm_pwr_leslv_Msk                                                                       (0x3UL << AON_REG_SRAM_CTRL4_DS_K_norm_pwr_leslv_Pos)
+
+#define AON_REG_SRAM_CTRL4_RSVD_Pos                                                                                      13U
+#define AON_REG_SRAM_CTRL4_RSVD_Msk                                                                                      (0x7FFFFUL << AON_REG_SRAM_CTRL4_RSVD_Pos)
+
+/* 0x83C    0x4000_083c
+    2:0     R/W     WPULSE_leslv_lv                                             3'b000
+    5:3     R/W     WA_leslv_lv                                                 3'b101
+    9:6     R/W     RM_leslv_lv                                                 4'b0010
+    10      R/W     RME_leslv_lv                                                1'b1
+    12:11   R/W     RA_leslv_lv                                                 2'b00
+    15:13   R       RSVD_1                                                      0
+    18:16   R/W     WPULSE_leslv_hv                                             3'b000
+    21:19   R/W     WA_leslv_hv                                                 3'b100
+    25:22   R/W     RM_leslv_hv                                                 4'b0011
+    26      R/W     RME_leslv_hv                                                1'b1
+    28:27   R/W     RA_leslv_hv                                                 2'b00
+    31:29   R       RSVD                                                        0
+ */
+typedef union _AON_REG_SRAM_CTRL5_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t WPULSE_leslv_lv: 3;
+        uint32_t WA_leslv_lv: 3;
+        uint32_t RM_leslv_lv: 4;
+        uint32_t RME_leslv_lv: 1;
+        uint32_t RA_leslv_lv: 2;
+        uint32_t RSVD_1: 3;
+        uint32_t WPULSE_leslv_hv: 3;
+        uint32_t WA_leslv_hv: 3;
+        uint32_t RM_leslv_hv: 4;
+        uint32_t RME_leslv_hv: 1;
+        uint32_t RA_leslv_hv: 2;
+        uint32_t RSVD: 3;
+    };
+} AON_REG_SRAM_CTRL5_TYPE;
+
+/*0x4000_083c AON_REG_SRAM_CTRL5*/
+#define AON_REG_SRAM_CTRL5_WPULSE_leslv_lv_Pos                                                                           0U
+#define AON_REG_SRAM_CTRL5_WPULSE_leslv_lv_Msk                                                                           (0x7UL << AON_REG_SRAM_CTRL5_WPULSE_leslv_lv_Pos)
+
+#define AON_REG_SRAM_CTRL5_WA_leslv_lv_Pos                                                                               3U
+#define AON_REG_SRAM_CTRL5_WA_leslv_lv_Msk                                                                               (0x7UL << AON_REG_SRAM_CTRL5_WA_leslv_lv_Pos)
+
+#define AON_REG_SRAM_CTRL5_RM_leslv_lv_Pos                                                                               6U
+#define AON_REG_SRAM_CTRL5_RM_leslv_lv_Msk                                                                               (0xFUL << AON_REG_SRAM_CTRL5_RM_leslv_lv_Pos)
+
+#define AON_REG_SRAM_CTRL5_RME_leslv_lv_Pos                                                                              10U
+#define AON_REG_SRAM_CTRL5_RME_leslv_lv_Msk                                                                              (0x1UL << AON_REG_SRAM_CTRL5_RME_leslv_lv_Pos)
+
+#define AON_REG_SRAM_CTRL5_RA_leslv_lv_Pos                                                                               11U
+#define AON_REG_SRAM_CTRL5_RA_leslv_lv_Msk                                                                               (0x3UL << AON_REG_SRAM_CTRL5_RA_leslv_lv_Pos)
+
+#define AON_REG_SRAM_CTRL5_RSVD_1_Pos                                                                                    13U
+#define AON_REG_SRAM_CTRL5_RSVD_1_Msk                                                                                    (0x7UL << AON_REG_SRAM_CTRL5_RSVD_1_Pos)
+
+#define AON_REG_SRAM_CTRL5_WPULSE_leslv_hv_Pos                                                                           16U
+#define AON_REG_SRAM_CTRL5_WPULSE_leslv_hv_Msk                                                                           (0x7UL << AON_REG_SRAM_CTRL5_WPULSE_leslv_hv_Pos)
+
+#define AON_REG_SRAM_CTRL5_WA_leslv_hv_Pos                                                                               19U
+#define AON_REG_SRAM_CTRL5_WA_leslv_hv_Msk                                                                               (0x7UL << AON_REG_SRAM_CTRL5_WA_leslv_hv_Pos)
+
+#define AON_REG_SRAM_CTRL5_RM_leslv_hv_Pos                                                                               22U
+#define AON_REG_SRAM_CTRL5_RM_leslv_hv_Msk                                                                               (0xFUL << AON_REG_SRAM_CTRL5_RM_leslv_hv_Pos)
+
+#define AON_REG_SRAM_CTRL5_RME_leslv_hv_Pos                                                                              26U
+#define AON_REG_SRAM_CTRL5_RME_leslv_hv_Msk                                                                              (0x1UL << AON_REG_SRAM_CTRL5_RME_leslv_hv_Pos)
+
+#define AON_REG_SRAM_CTRL5_RA_leslv_hv_Pos                                                                               27U
+#define AON_REG_SRAM_CTRL5_RA_leslv_hv_Msk                                                                               (0x3UL << AON_REG_SRAM_CTRL5_RA_leslv_hv_Pos)
+
+#define AON_REG_SRAM_CTRL5_RSVD_Pos                                                                                      29U
+#define AON_REG_SRAM_CTRL5_RSVD_Msk                                                                                      (0x7UL << AON_REG_SRAM_CTRL5_RSVD_Pos)
+
+/* 0x840    0x4000_0840
+    0       R/W     DS_low_pwr_buffer                                           1'b0
+    1       R/W     SD_low_pwr_buffer                                           1'b0
+    2       R/W     LS_low_pwr_buffer                                           1'b0
+    3       R/W     DS_UNK_low_pwr_buffer                                       1'b0
+    5:4     R/W     DS_K_low_pwr_buffer                                         2'b01
+    6       R/W     DS_norm_pwr_buffer                                          1'b0
+    7       R/W     SD_norm_pwr_buffer                                          1'b0
+    8       R/W     LS_norm_pwr_buffer                                          1'b0
+    9       R/W     DS_UNK_norm_pwr_buffer                                      1'b0
+    11:10   R/W     DS_K_norm_pwr_buffer                                        2'b01
+    12      R/W     TEST1_buffer                                                1'b0
+    13      R/W     DS_BKEN_buffer                                              1'b0
+    15:14   R/W     DS_BK_buffer                                                2'b11
+    16      R/W     DS_low_pwr_buffer_8k                                        1'b0
+    17      R/W     SD_low_pwr_buffer_8k                                        1'b0
+    18      R/W     LS_low_pwr_buffer_8k                                        1'b0
+    19      R/W     DS_UNK_low_pwr_buffer_8k                                    1'b0
+    21:20   R/W     DS_K_low_pwr_buffer_8k                                      2'b01
+    22      R/W     DS_norm_pwr_buffer_8k                                       1'b0
+    23      R/W     SD_norm_pwr_buffer_8k                                       1'b0
+    24      R/W     LS_norm_pwr_buffer_8k                                       1'b0
+    25      R/W     DS_UNK_norm_pwr_buffer_8k                                   1'b0
+    27:26   R/W     DS_K_norm_pwr_buffer_8k                                     2'b01
+    28      R/W     TEST1_buffer_8k                                             1'b0
+    29      R       RSVD_1                                                      0
+    31:30   R       RSVD                                                        0
+ */
+typedef union _AON_REG_SRAM_CTRL6_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t DS_low_pwr_buffer: 1;
+        uint32_t SD_low_pwr_buffer: 1;
+        uint32_t LS_low_pwr_buffer: 1;
+        uint32_t DS_UNK_low_pwr_buffer: 1;
+        uint32_t DS_K_low_pwr_buffer: 2;
+        uint32_t DS_norm_pwr_buffer: 1;
+        uint32_t SD_norm_pwr_buffer: 1;
+        uint32_t LS_norm_pwr_buffer: 1;
+        uint32_t DS_UNK_norm_pwr_buffer: 1;
+        uint32_t DS_K_norm_pwr_buffer: 2;
+        uint32_t TEST1_buffer: 1;
+        uint32_t DS_BKEN_buffer: 1;
+        uint32_t DS_BK_buffer: 2;
+        uint32_t DS_low_pwr_buffer_8k: 1;
+        uint32_t SD_low_pwr_buffer_8k: 1;
+        uint32_t LS_low_pwr_buffer_8k: 1;
+        uint32_t DS_UNK_low_pwr_buffer_8k: 1;
+        uint32_t DS_K_low_pwr_buffer_8k: 2;
+        uint32_t DS_norm_pwr_buffer_8k: 1;
+        uint32_t SD_norm_pwr_buffer_8k: 1;
+        uint32_t LS_norm_pwr_buffer_8k: 1;
+        uint32_t DS_UNK_norm_pwr_buffer_8k: 1;
+        uint32_t DS_K_norm_pwr_buffer_8k: 2;
+        uint32_t TEST1_buffer_8k: 1;
+        uint32_t RSVD_1: 1;
+        uint32_t RSVD: 2;
+    };
+} AON_REG_SRAM_CTRL6_TYPE;
+
+/*0x4000_0840 AON_REG_SRAM_CTRL6*/
+#define AON_REG_SRAM_CTRL6_DS_low_pwr_buffer_Pos                                                                         0U
+#define AON_REG_SRAM_CTRL6_DS_low_pwr_buffer_Msk                                                                         (0x1UL << AON_REG_SRAM_CTRL6_DS_low_pwr_buffer_Pos)
+
+#define AON_REG_SRAM_CTRL6_SD_low_pwr_buffer_Pos                                                                         1U
+#define AON_REG_SRAM_CTRL6_SD_low_pwr_buffer_Msk                                                                         (0x1UL << AON_REG_SRAM_CTRL6_SD_low_pwr_buffer_Pos)
+
+#define AON_REG_SRAM_CTRL6_LS_low_pwr_buffer_Pos                                                                         2U
+#define AON_REG_SRAM_CTRL6_LS_low_pwr_buffer_Msk                                                                         (0x1UL << AON_REG_SRAM_CTRL6_LS_low_pwr_buffer_Pos)
+
+#define AON_REG_SRAM_CTRL6_DS_UNK_low_pwr_buffer_Pos                                                                     3U
+#define AON_REG_SRAM_CTRL6_DS_UNK_low_pwr_buffer_Msk                                                                     (0x1UL << AON_REG_SRAM_CTRL6_DS_UNK_low_pwr_buffer_Pos)
+
+#define AON_REG_SRAM_CTRL6_DS_K_low_pwr_buffer_Pos                                                                       4U
+#define AON_REG_SRAM_CTRL6_DS_K_low_pwr_buffer_Msk                                                                       (0x3UL << AON_REG_SRAM_CTRL6_DS_K_low_pwr_buffer_Pos)
+
+#define AON_REG_SRAM_CTRL6_DS_norm_pwr_buffer_Pos                                                                        6U
+#define AON_REG_SRAM_CTRL6_DS_norm_pwr_buffer_Msk                                                                        (0x1UL << AON_REG_SRAM_CTRL6_DS_norm_pwr_buffer_Pos)
+
+#define AON_REG_SRAM_CTRL6_SD_norm_pwr_buffer_Pos                                                                        7U
+#define AON_REG_SRAM_CTRL6_SD_norm_pwr_buffer_Msk                                                                        (0x1UL << AON_REG_SRAM_CTRL6_SD_norm_pwr_buffer_Pos)
+
+#define AON_REG_SRAM_CTRL6_LS_norm_pwr_buffer_Pos                                                                        8U
+#define AON_REG_SRAM_CTRL6_LS_norm_pwr_buffer_Msk                                                                        (0x1UL << AON_REG_SRAM_CTRL6_LS_norm_pwr_buffer_Pos)
+
+#define AON_REG_SRAM_CTRL6_DS_UNK_norm_pwr_buffer_Pos                                                                    9U
+#define AON_REG_SRAM_CTRL6_DS_UNK_norm_pwr_buffer_Msk                                                                    (0x1UL << AON_REG_SRAM_CTRL6_DS_UNK_norm_pwr_buffer_Pos)
+
+#define AON_REG_SRAM_CTRL6_DS_K_norm_pwr_buffer_Pos                                                                      10U
+#define AON_REG_SRAM_CTRL6_DS_K_norm_pwr_buffer_Msk                                                                      (0x3UL << AON_REG_SRAM_CTRL6_DS_K_norm_pwr_buffer_Pos)
+
+#define AON_REG_SRAM_CTRL6_TEST1_buffer_Pos                                                                              12U
+#define AON_REG_SRAM_CTRL6_TEST1_buffer_Msk                                                                              (0x1UL << AON_REG_SRAM_CTRL6_TEST1_buffer_Pos)
+
+#define AON_REG_SRAM_CTRL6_DS_BKEN_buffer_Pos                                                                            13U
+#define AON_REG_SRAM_CTRL6_DS_BKEN_buffer_Msk                                                                            (0x1UL << AON_REG_SRAM_CTRL6_DS_BKEN_buffer_Pos)
+
+#define AON_REG_SRAM_CTRL6_DS_BK_buffer_Pos                                                                              14U
+#define AON_REG_SRAM_CTRL6_DS_BK_buffer_Msk                                                                              (0x3UL << AON_REG_SRAM_CTRL6_DS_BK_buffer_Pos)
+
+#define AON_REG_SRAM_CTRL6_DS_low_pwr_buffer_8k_Pos                                                                      16U
+#define AON_REG_SRAM_CTRL6_DS_low_pwr_buffer_8k_Msk                                                                      (0x1UL << AON_REG_SRAM_CTRL6_DS_low_pwr_buffer_8k_Pos)
+
+#define AON_REG_SRAM_CTRL6_SD_low_pwr_buffer_8k_Pos                                                                      17U
+#define AON_REG_SRAM_CTRL6_SD_low_pwr_buffer_8k_Msk                                                                      (0x1UL << AON_REG_SRAM_CTRL6_SD_low_pwr_buffer_8k_Pos)
+
+#define AON_REG_SRAM_CTRL6_LS_low_pwr_buffer_8k_Pos                                                                      18U
+#define AON_REG_SRAM_CTRL6_LS_low_pwr_buffer_8k_Msk                                                                      (0x1UL << AON_REG_SRAM_CTRL6_LS_low_pwr_buffer_8k_Pos)
+
+#define AON_REG_SRAM_CTRL6_DS_UNK_low_pwr_buffer_8k_Pos                                                                  19U
+#define AON_REG_SRAM_CTRL6_DS_UNK_low_pwr_buffer_8k_Msk                                                                  (0x1UL << AON_REG_SRAM_CTRL6_DS_UNK_low_pwr_buffer_8k_Pos)
+
+#define AON_REG_SRAM_CTRL6_DS_K_low_pwr_buffer_8k_Pos                                                                    20U
+#define AON_REG_SRAM_CTRL6_DS_K_low_pwr_buffer_8k_Msk                                                                    (0x3UL << AON_REG_SRAM_CTRL6_DS_K_low_pwr_buffer_8k_Pos)
+
+#define AON_REG_SRAM_CTRL6_DS_norm_pwr_buffer_8k_Pos                                                                     22U
+#define AON_REG_SRAM_CTRL6_DS_norm_pwr_buffer_8k_Msk                                                                     (0x1UL << AON_REG_SRAM_CTRL6_DS_norm_pwr_buffer_8k_Pos)
+
+#define AON_REG_SRAM_CTRL6_SD_norm_pwr_buffer_8k_Pos                                                                     23U
+#define AON_REG_SRAM_CTRL6_SD_norm_pwr_buffer_8k_Msk                                                                     (0x1UL << AON_REG_SRAM_CTRL6_SD_norm_pwr_buffer_8k_Pos)
+
+#define AON_REG_SRAM_CTRL6_LS_norm_pwr_buffer_8k_Pos                                                                     24U
+#define AON_REG_SRAM_CTRL6_LS_norm_pwr_buffer_8k_Msk                                                                     (0x1UL << AON_REG_SRAM_CTRL6_LS_norm_pwr_buffer_8k_Pos)
+
+#define AON_REG_SRAM_CTRL6_DS_UNK_norm_pwr_buffer_8k_Pos                                                                 25U
+#define AON_REG_SRAM_CTRL6_DS_UNK_norm_pwr_buffer_8k_Msk                                                                 (0x1UL << AON_REG_SRAM_CTRL6_DS_UNK_norm_pwr_buffer_8k_Pos)
+
+#define AON_REG_SRAM_CTRL6_DS_K_norm_pwr_buffer_8k_Pos                                                                   26U
+#define AON_REG_SRAM_CTRL6_DS_K_norm_pwr_buffer_8k_Msk                                                                   (0x3UL << AON_REG_SRAM_CTRL6_DS_K_norm_pwr_buffer_8k_Pos)
+
+#define AON_REG_SRAM_CTRL6_TEST1_buffer_8k_Pos                                                                           28U
+#define AON_REG_SRAM_CTRL6_TEST1_buffer_8k_Msk                                                                           (0x1UL << AON_REG_SRAM_CTRL6_TEST1_buffer_8k_Pos)
+
+#define AON_REG_SRAM_CTRL6_RSVD_1_Pos                                                                                    29U
+#define AON_REG_SRAM_CTRL6_RSVD_1_Msk                                                                                    (0x1UL << AON_REG_SRAM_CTRL6_RSVD_1_Pos)
+
+#define AON_REG_SRAM_CTRL6_RSVD_Pos                                                                                      30U
+#define AON_REG_SRAM_CTRL6_RSVD_Msk                                                                                      (0x3UL << AON_REG_SRAM_CTRL6_RSVD_Pos)
+
+/* 0x844    0x4000_0844
+    2:0     R/W     WPULSE_buffer_lv                                            3'b000
+    5:3     R/W     WA_buffer_lv                                                3'b101
+    9:6     R/W     RM_buffer_lv                                                4'b0010
+    10      R/W     RME_buffer_lv                                               1'b1
+    12:11   R/W     RA_buffer_lv                                                2'b00
+    15:13   R       RSVD_1                                                      0
+    18:16   R/W     WPULSE_buffer_hv                                            3'b000
+    21:19   R/W     WA_buffer_hv                                                3'b100
+    25:22   R/W     RM_buffer_hv                                                4'b0011
+    26      R/W     RME_buffer_hv                                               1'b1
+    28:27   R/W     RA_buffer_hv                                                2'b00
+    31:29   R       RSVD                                                        0
+ */
+typedef union _AON_REG_SRAM_CTRL7_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t WPULSE_buffer_lv: 3;
+        uint32_t WA_buffer_lv: 3;
+        uint32_t RM_buffer_lv: 4;
+        uint32_t RME_buffer_lv: 1;
+        uint32_t RA_buffer_lv: 2;
+        uint32_t RSVD_1: 3;
+        uint32_t WPULSE_buffer_hv: 3;
+        uint32_t WA_buffer_hv: 3;
+        uint32_t RM_buffer_hv: 4;
+        uint32_t RME_buffer_hv: 1;
+        uint32_t RA_buffer_hv: 2;
+        uint32_t RSVD: 3;
+    };
+} AON_REG_SRAM_CTRL7_TYPE;
+
+/*0x4000_0844 AON_REG_SRAM_CTRL7*/
+#define AON_REG_SRAM_CTRL7_WPULSE_buffer_lv_Pos                                                                          0U
+#define AON_REG_SRAM_CTRL7_WPULSE_buffer_lv_Msk                                                                          (0x7UL << AON_REG_SRAM_CTRL7_WPULSE_buffer_lv_Pos)
+
+#define AON_REG_SRAM_CTRL7_WA_buffer_lv_Pos                                                                              3U
+#define AON_REG_SRAM_CTRL7_WA_buffer_lv_Msk                                                                              (0x7UL << AON_REG_SRAM_CTRL7_WA_buffer_lv_Pos)
+
+#define AON_REG_SRAM_CTRL7_RM_buffer_lv_Pos                                                                              6U
+#define AON_REG_SRAM_CTRL7_RM_buffer_lv_Msk                                                                              (0xFUL << AON_REG_SRAM_CTRL7_RM_buffer_lv_Pos)
+
+#define AON_REG_SRAM_CTRL7_RME_buffer_lv_Pos                                                                             10U
+#define AON_REG_SRAM_CTRL7_RME_buffer_lv_Msk                                                                             (0x1UL << AON_REG_SRAM_CTRL7_RME_buffer_lv_Pos)
+
+#define AON_REG_SRAM_CTRL7_RA_buffer_lv_Pos                                                                              11U
+#define AON_REG_SRAM_CTRL7_RA_buffer_lv_Msk                                                                              (0x3UL << AON_REG_SRAM_CTRL7_RA_buffer_lv_Pos)
+
+#define AON_REG_SRAM_CTRL7_RSVD_1_Pos                                                                                    13U
+#define AON_REG_SRAM_CTRL7_RSVD_1_Msk                                                                                    (0x7UL << AON_REG_SRAM_CTRL7_RSVD_1_Pos)
+
+#define AON_REG_SRAM_CTRL7_WPULSE_buffer_hv_Pos                                                                          16U
+#define AON_REG_SRAM_CTRL7_WPULSE_buffer_hv_Msk                                                                          (0x7UL << AON_REG_SRAM_CTRL7_WPULSE_buffer_hv_Pos)
+
+#define AON_REG_SRAM_CTRL7_WA_buffer_hv_Pos                                                                              19U
+#define AON_REG_SRAM_CTRL7_WA_buffer_hv_Msk                                                                              (0x7UL << AON_REG_SRAM_CTRL7_WA_buffer_hv_Pos)
+
+#define AON_REG_SRAM_CTRL7_RM_buffer_hv_Pos                                                                              22U
+#define AON_REG_SRAM_CTRL7_RM_buffer_hv_Msk                                                                              (0xFUL << AON_REG_SRAM_CTRL7_RM_buffer_hv_Pos)
+
+#define AON_REG_SRAM_CTRL7_RME_buffer_hv_Pos                                                                             26U
+#define AON_REG_SRAM_CTRL7_RME_buffer_hv_Msk                                                                             (0x1UL << AON_REG_SRAM_CTRL7_RME_buffer_hv_Pos)
+
+#define AON_REG_SRAM_CTRL7_RA_buffer_hv_Pos                                                                              27U
+#define AON_REG_SRAM_CTRL7_RA_buffer_hv_Msk                                                                              (0x3UL << AON_REG_SRAM_CTRL7_RA_buffer_hv_Pos)
+
+#define AON_REG_SRAM_CTRL7_RSVD_Pos                                                                                      29U
+#define AON_REG_SRAM_CTRL7_RSVD_Msk                                                                                      (0x7UL << AON_REG_SRAM_CTRL7_RSVD_Pos)
+
+/* 0x848    0x4000_0848
+    4:0     R/W     DS_low_pwr_retsram                                          5'b0
+    9:5     R/W     SD_low_pwr_retsram                                          5'b0
+    14:10   R/W     LS_low_pwr_retsram                                          5'b0
+    19:15   R/W     DS_norm_pwr_retsram                                         5'b0
+    24:20   R/W     SD_norm_pwr_retsram                                         5'b0
+    29:25   R/W     LS_norm_pwr_retsram                                         5'b0
+    30      R/W     TEST1_retsram_0                                             1'b0
+    31      R/W     TEST1_retsram_1                                             1'b0
+ */
+typedef union _AON_REG_SRAM_CTRL8_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t DS_low_pwr_retsram: 5;
+        uint32_t SD_low_pwr_retsram: 5;
+        uint32_t LS_low_pwr_retsram: 5;
+        uint32_t DS_norm_pwr_retsram: 5;
+        uint32_t SD_norm_pwr_retsram: 5;
+        uint32_t LS_norm_pwr_retsram: 5;
+        uint32_t TEST1_retsram_0: 1;
+        uint32_t TEST1_retsram_1: 1;
+    };
+} AON_REG_SRAM_CTRL8_TYPE;
+
+/*0x4000_0848 AON_REG_SRAM_CTRL8*/
+#define AON_REG_SRAM_CTRL8_DS_low_pwr_retsram_Pos                                                                        0U
+#define AON_REG_SRAM_CTRL8_DS_low_pwr_retsram_Msk                                                                        (0x1FUL << AON_REG_SRAM_CTRL8_DS_low_pwr_retsram_Pos)
+
+#define AON_REG_SRAM_CTRL8_SD_low_pwr_retsram_Pos                                                                        5U
+#define AON_REG_SRAM_CTRL8_SD_low_pwr_retsram_Msk                                                                        (0x1FUL << AON_REG_SRAM_CTRL8_SD_low_pwr_retsram_Pos)
+
+#define AON_REG_SRAM_CTRL8_LS_low_pwr_retsram_Pos                                                                        10U
+#define AON_REG_SRAM_CTRL8_LS_low_pwr_retsram_Msk                                                                        (0x1FUL << AON_REG_SRAM_CTRL8_LS_low_pwr_retsram_Pos)
+
+#define AON_REG_SRAM_CTRL8_DS_norm_pwr_retsram_Pos                                                                       15U
+#define AON_REG_SRAM_CTRL8_DS_norm_pwr_retsram_Msk                                                                       (0x1FUL << AON_REG_SRAM_CTRL8_DS_norm_pwr_retsram_Pos)
+
+#define AON_REG_SRAM_CTRL8_SD_norm_pwr_retsram_Pos                                                                       20U
+#define AON_REG_SRAM_CTRL8_SD_norm_pwr_retsram_Msk                                                                       (0x1FUL << AON_REG_SRAM_CTRL8_SD_norm_pwr_retsram_Pos)
+
+#define AON_REG_SRAM_CTRL8_LS_norm_pwr_retsram_Pos                                                                       25U
+#define AON_REG_SRAM_CTRL8_LS_norm_pwr_retsram_Msk                                                                       (0x1FUL << AON_REG_SRAM_CTRL8_LS_norm_pwr_retsram_Pos)
+
+#define AON_REG_SRAM_CTRL8_TEST1_retsram_0_Pos                                                                           30U
+#define AON_REG_SRAM_CTRL8_TEST1_retsram_0_Msk                                                                           (0x1UL << AON_REG_SRAM_CTRL8_TEST1_retsram_0_Pos)
+
+#define AON_REG_SRAM_CTRL8_TEST1_retsram_1_Pos                                                                           31U
+#define AON_REG_SRAM_CTRL8_TEST1_retsram_1_Msk                                                                           (0x1UL << AON_REG_SRAM_CTRL8_TEST1_retsram_1_Pos)
+
+/* 0x84C    0x4000_084c
+    0       R/W     DS_UNK_low_pwr_retsram_0                                    1'b0
+    2:1     R/W     DS_K_low_pwr_retsram_0                                      2'b01
+    3       R/W     DS_UNK_low_pwr_retsram_1                                    1'b0
+    5:4     R/W     DS_K_low_pwr_retsram_1                                      2'b01
+    6       R/W     DS_UNK_low_pwr_retsram_2                                    1'b0
+    8:7     R/W     DS_K_low_pwr_retsram_2                                      2'b01
+    9       R/W     DS_UNK_low_pwr_retsram_3                                    1'b0
+    11:10   R/W     DS_K_low_pwr_retsram_3                                      2'b01
+    12      R/W     DS_UNK_low_pwr_retsram_4                                    1'b0
+    14:13   R/W     DS_K_low_pwr_retsram_4                                      2'b01
+    15      R       RSVD_1                                                      0
+    16      R/W     DS_UNK_norm_pwr_retsram_0                                   1'b0
+    18:17   R/W     DS_K_norm_pwr_retsram_0                                     2'b01
+    19      R/W     DS_UNK_norm_pwr_retsram_1                                   1'b0
+    21:20   R/W     DS_K_norm_pwr_retsram_1                                     2'b01
+    22      R/W     DS_UNK_norm_pwr_retsram_2                                   1'b0
+    24:23   R/W     DS_K_norm_pwr_retsram_2                                     2'b01
+    25      R/W     DS_UNK_norm_pwr_retsram_3                                   1'b0
+    27:26   R/W     DS_K_norm_pwr_retsram_3                                     2'b01
+    28      R/W     DS_UNK_norm_pwr_retsram_4                                   1'b0
+    30:29   R/W     DS_K_norm_pwr_retsram_4                                     2'b01
+    31      R       RSVD                                                        0
+ */
+typedef union _AON_REG_SRAM_CTRL9_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t DS_UNK_low_pwr_retsram_0: 1;
+        uint32_t DS_K_low_pwr_retsram_0: 2;
+        uint32_t DS_UNK_low_pwr_retsram_1: 1;
+        uint32_t DS_K_low_pwr_retsram_1: 2;
+        uint32_t DS_UNK_low_pwr_retsram_2: 1;
+        uint32_t DS_K_low_pwr_retsram_2: 2;
+        uint32_t DS_UNK_low_pwr_retsram_3: 1;
+        uint32_t DS_K_low_pwr_retsram_3: 2;
+        uint32_t DS_UNK_low_pwr_retsram_4: 1;
+        uint32_t DS_K_low_pwr_retsram_4: 2;
+        uint32_t RSVD_1: 1;
+        uint32_t DS_UNK_norm_pwr_retsram_0: 1;
+        uint32_t DS_K_norm_pwr_retsram_0: 2;
+        uint32_t DS_UNK_norm_pwr_retsram_1: 1;
+        uint32_t DS_K_norm_pwr_retsram_1: 2;
+        uint32_t DS_UNK_norm_pwr_retsram_2: 1;
+        uint32_t DS_K_norm_pwr_retsram_2: 2;
+        uint32_t DS_UNK_norm_pwr_retsram_3: 1;
+        uint32_t DS_K_norm_pwr_retsram_3: 2;
+        uint32_t DS_UNK_norm_pwr_retsram_4: 1;
+        uint32_t DS_K_norm_pwr_retsram_4: 2;
+        uint32_t RSVD: 1;
+    };
+} AON_REG_SRAM_CTRL9_TYPE;
+
+/*0x4000_084c AON_REG_SRAM_CTRL9*/
+#define AON_REG_SRAM_CTRL9_DS_UNK_low_pwr_retsram_0_Pos                                                                  0U
+#define AON_REG_SRAM_CTRL9_DS_UNK_low_pwr_retsram_0_Msk                                                                  (0x1UL << AON_REG_SRAM_CTRL9_DS_UNK_low_pwr_retsram_0_Pos)
+
+#define AON_REG_SRAM_CTRL9_DS_K_low_pwr_retsram_0_Pos                                                                    1U
+#define AON_REG_SRAM_CTRL9_DS_K_low_pwr_retsram_0_Msk                                                                    (0x3UL << AON_REG_SRAM_CTRL9_DS_K_low_pwr_retsram_0_Pos)
+
+#define AON_REG_SRAM_CTRL9_DS_UNK_low_pwr_retsram_1_Pos                                                                  3U
+#define AON_REG_SRAM_CTRL9_DS_UNK_low_pwr_retsram_1_Msk                                                                  (0x1UL << AON_REG_SRAM_CTRL9_DS_UNK_low_pwr_retsram_1_Pos)
+
+#define AON_REG_SRAM_CTRL9_DS_K_low_pwr_retsram_1_Pos                                                                    4U
+#define AON_REG_SRAM_CTRL9_DS_K_low_pwr_retsram_1_Msk                                                                    (0x3UL << AON_REG_SRAM_CTRL9_DS_K_low_pwr_retsram_1_Pos)
+
+#define AON_REG_SRAM_CTRL9_DS_UNK_low_pwr_retsram_2_Pos                                                                  6U
+#define AON_REG_SRAM_CTRL9_DS_UNK_low_pwr_retsram_2_Msk                                                                  (0x1UL << AON_REG_SRAM_CTRL9_DS_UNK_low_pwr_retsram_2_Pos)
+
+#define AON_REG_SRAM_CTRL9_DS_K_low_pwr_retsram_2_Pos                                                                    7U
+#define AON_REG_SRAM_CTRL9_DS_K_low_pwr_retsram_2_Msk                                                                    (0x3UL << AON_REG_SRAM_CTRL9_DS_K_low_pwr_retsram_2_Pos)
+
+#define AON_REG_SRAM_CTRL9_DS_UNK_low_pwr_retsram_3_Pos                                                                  9U
+#define AON_REG_SRAM_CTRL9_DS_UNK_low_pwr_retsram_3_Msk                                                                  (0x1UL << AON_REG_SRAM_CTRL9_DS_UNK_low_pwr_retsram_3_Pos)
+
+#define AON_REG_SRAM_CTRL9_DS_K_low_pwr_retsram_3_Pos                                                                    10U
+#define AON_REG_SRAM_CTRL9_DS_K_low_pwr_retsram_3_Msk                                                                    (0x3UL << AON_REG_SRAM_CTRL9_DS_K_low_pwr_retsram_3_Pos)
+
+#define AON_REG_SRAM_CTRL9_DS_UNK_low_pwr_retsram_4_Pos                                                                  12U
+#define AON_REG_SRAM_CTRL9_DS_UNK_low_pwr_retsram_4_Msk                                                                  (0x1UL << AON_REG_SRAM_CTRL9_DS_UNK_low_pwr_retsram_4_Pos)
+
+#define AON_REG_SRAM_CTRL9_DS_K_low_pwr_retsram_4_Pos                                                                    13U
+#define AON_REG_SRAM_CTRL9_DS_K_low_pwr_retsram_4_Msk                                                                    (0x3UL << AON_REG_SRAM_CTRL9_DS_K_low_pwr_retsram_4_Pos)
+
+#define AON_REG_SRAM_CTRL9_RSVD_1_Pos                                                                                    15U
+#define AON_REG_SRAM_CTRL9_RSVD_1_Msk                                                                                    (0x1UL << AON_REG_SRAM_CTRL9_RSVD_1_Pos)
+
+#define AON_REG_SRAM_CTRL9_DS_UNK_norm_pwr_retsram_0_Pos                                                                 16U
+#define AON_REG_SRAM_CTRL9_DS_UNK_norm_pwr_retsram_0_Msk                                                                 (0x1UL << AON_REG_SRAM_CTRL9_DS_UNK_norm_pwr_retsram_0_Pos)
+
+#define AON_REG_SRAM_CTRL9_DS_K_norm_pwr_retsram_0_Pos                                                                   17U
+#define AON_REG_SRAM_CTRL9_DS_K_norm_pwr_retsram_0_Msk                                                                   (0x3UL << AON_REG_SRAM_CTRL9_DS_K_norm_pwr_retsram_0_Pos)
+
+#define AON_REG_SRAM_CTRL9_DS_UNK_norm_pwr_retsram_1_Pos                                                                 19U
+#define AON_REG_SRAM_CTRL9_DS_UNK_norm_pwr_retsram_1_Msk                                                                 (0x1UL << AON_REG_SRAM_CTRL9_DS_UNK_norm_pwr_retsram_1_Pos)
+
+#define AON_REG_SRAM_CTRL9_DS_K_norm_pwr_retsram_1_Pos                                                                   20U
+#define AON_REG_SRAM_CTRL9_DS_K_norm_pwr_retsram_1_Msk                                                                   (0x3UL << AON_REG_SRAM_CTRL9_DS_K_norm_pwr_retsram_1_Pos)
+
+#define AON_REG_SRAM_CTRL9_DS_UNK_norm_pwr_retsram_2_Pos                                                                 22U
+#define AON_REG_SRAM_CTRL9_DS_UNK_norm_pwr_retsram_2_Msk                                                                 (0x1UL << AON_REG_SRAM_CTRL9_DS_UNK_norm_pwr_retsram_2_Pos)
+
+#define AON_REG_SRAM_CTRL9_DS_K_norm_pwr_retsram_2_Pos                                                                   23U
+#define AON_REG_SRAM_CTRL9_DS_K_norm_pwr_retsram_2_Msk                                                                   (0x3UL << AON_REG_SRAM_CTRL9_DS_K_norm_pwr_retsram_2_Pos)
+
+#define AON_REG_SRAM_CTRL9_DS_UNK_norm_pwr_retsram_3_Pos                                                                 25U
+#define AON_REG_SRAM_CTRL9_DS_UNK_norm_pwr_retsram_3_Msk                                                                 (0x1UL << AON_REG_SRAM_CTRL9_DS_UNK_norm_pwr_retsram_3_Pos)
+
+#define AON_REG_SRAM_CTRL9_DS_K_norm_pwr_retsram_3_Pos                                                                   26U
+#define AON_REG_SRAM_CTRL9_DS_K_norm_pwr_retsram_3_Msk                                                                   (0x3UL << AON_REG_SRAM_CTRL9_DS_K_norm_pwr_retsram_3_Pos)
+
+#define AON_REG_SRAM_CTRL9_DS_UNK_norm_pwr_retsram_4_Pos                                                                 28U
+#define AON_REG_SRAM_CTRL9_DS_UNK_norm_pwr_retsram_4_Msk                                                                 (0x1UL << AON_REG_SRAM_CTRL9_DS_UNK_norm_pwr_retsram_4_Pos)
+
+#define AON_REG_SRAM_CTRL9_DS_K_norm_pwr_retsram_4_Pos                                                                   29U
+#define AON_REG_SRAM_CTRL9_DS_K_norm_pwr_retsram_4_Msk                                                                   (0x3UL << AON_REG_SRAM_CTRL9_DS_K_norm_pwr_retsram_4_Pos)
+
+#define AON_REG_SRAM_CTRL9_RSVD_Pos                                                                                      31U
+#define AON_REG_SRAM_CTRL9_RSVD_Msk                                                                                      (0x1UL << AON_REG_SRAM_CTRL9_RSVD_Pos)
+
+/* 0x850    0x4000_0850
+    0       R/W     DS_BKEN_retsram_0                                           1'b0
+    2:1     R/W     DS_BK_retsram_0                                             2'b11
+    3       R/W     DS_BKEN_retsram_1                                           1'b0
+    5:4     R/W     DS_BK_retsram_1                                             2'b11
+    6       R/W     DS_BKEN_retsram_2                                           1'b0
+    8:7     R/W     DS_BK_retsram_2                                             2'b11
+    9       R/W     DS_BKEN_retsram_3                                           1'b0
+    11:10   R/W     DS_BK_retsram_3                                             2'b11
+    12      R/W     DS_BKEN_retsram_4                                           1'b0
+    14:13   R/W     DS_BK_retsram_4                                             2'b11
+    31:15   R       RSVD                                                        0
+ */
+typedef union _AON_REG_SRAM_CTRL10_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t DS_BKEN_retsram_0: 1;
+        uint32_t DS_BK_retsram_0: 2;
+        uint32_t DS_BKEN_retsram_1: 1;
+        uint32_t DS_BK_retsram_1: 2;
+        uint32_t DS_BKEN_retsram_2: 1;
+        uint32_t DS_BK_retsram_2: 2;
+        uint32_t DS_BKEN_retsram_3: 1;
+        uint32_t DS_BK_retsram_3: 2;
+        uint32_t DS_BKEN_retsram_4: 1;
+        uint32_t DS_BK_retsram_4: 2;
+        uint32_t RSVD: 17;
+    };
+} AON_REG_SRAM_CTRL10_TYPE;
+
+/*0x4000_0850 AON_REG_SRAM_CTRL10*/
+#define AON_REG_SRAM_CTRL10_DS_BKEN_retsram_0_Pos                                                                        0U
+#define AON_REG_SRAM_CTRL10_DS_BKEN_retsram_0_Msk                                                                        (0x1UL << AON_REG_SRAM_CTRL10_DS_BKEN_retsram_0_Pos)
+
+#define AON_REG_SRAM_CTRL10_DS_BK_retsram_0_Pos                                                                          1U
+#define AON_REG_SRAM_CTRL10_DS_BK_retsram_0_Msk                                                                          (0x3UL << AON_REG_SRAM_CTRL10_DS_BK_retsram_0_Pos)
+
+#define AON_REG_SRAM_CTRL10_DS_BKEN_retsram_1_Pos                                                                        3U
+#define AON_REG_SRAM_CTRL10_DS_BKEN_retsram_1_Msk                                                                        (0x1UL << AON_REG_SRAM_CTRL10_DS_BKEN_retsram_1_Pos)
+
+#define AON_REG_SRAM_CTRL10_DS_BK_retsram_1_Pos                                                                          4U
+#define AON_REG_SRAM_CTRL10_DS_BK_retsram_1_Msk                                                                          (0x3UL << AON_REG_SRAM_CTRL10_DS_BK_retsram_1_Pos)
+
+#define AON_REG_SRAM_CTRL10_DS_BKEN_retsram_2_Pos                                                                        6U
+#define AON_REG_SRAM_CTRL10_DS_BKEN_retsram_2_Msk                                                                        (0x1UL << AON_REG_SRAM_CTRL10_DS_BKEN_retsram_2_Pos)
+
+#define AON_REG_SRAM_CTRL10_DS_BK_retsram_2_Pos                                                                          7U
+#define AON_REG_SRAM_CTRL10_DS_BK_retsram_2_Msk                                                                          (0x3UL << AON_REG_SRAM_CTRL10_DS_BK_retsram_2_Pos)
+
+#define AON_REG_SRAM_CTRL10_DS_BKEN_retsram_3_Pos                                                                        9U
+#define AON_REG_SRAM_CTRL10_DS_BKEN_retsram_3_Msk                                                                        (0x1UL << AON_REG_SRAM_CTRL10_DS_BKEN_retsram_3_Pos)
+
+#define AON_REG_SRAM_CTRL10_DS_BK_retsram_3_Pos                                                                          10U
+#define AON_REG_SRAM_CTRL10_DS_BK_retsram_3_Msk                                                                          (0x3UL << AON_REG_SRAM_CTRL10_DS_BK_retsram_3_Pos)
+
+#define AON_REG_SRAM_CTRL10_DS_BKEN_retsram_4_Pos                                                                        12U
+#define AON_REG_SRAM_CTRL10_DS_BKEN_retsram_4_Msk                                                                        (0x1UL << AON_REG_SRAM_CTRL10_DS_BKEN_retsram_4_Pos)
+
+#define AON_REG_SRAM_CTRL10_DS_BK_retsram_4_Pos                                                                          13U
+#define AON_REG_SRAM_CTRL10_DS_BK_retsram_4_Msk                                                                          (0x3UL << AON_REG_SRAM_CTRL10_DS_BK_retsram_4_Pos)
+
+#define AON_REG_SRAM_CTRL10_RSVD_Pos                                                                                     15U
+#define AON_REG_SRAM_CTRL10_RSVD_Msk                                                                                     (0x1FFFFUL << AON_REG_SRAM_CTRL10_RSVD_Pos)
+
+/* 0x854    0x4000_0854
+    2:0     R/W     WPULSE_retsram_0_lv                                         3'b000
+    5:3     R/W     WA_retsram_0_lv                                             3'b101
+    9:6     R/W     RM_retsram_0_lv                                             4'b0010
+    10      R/W     RME_retsram_0_lv                                            1'b1
+    12:11   R/W     RA_retsram_0_lv                                             2'b00
+    15:13   R/W     RSVD_1                                                      0
+    18:16   R/W     WPULSE_retsram_0_hv                                         3'b000
+    21:19   R/W     WA_retsram_0_hv                                             3'b100
+    25:22   R/W     RM_retsram_0_hv                                             4'b0011
+    26      R/W     RME_retsram_0_hv                                            1'b1
+    28:27   R/W     RA_retsram_0_hv                                             2'b00
+    31:29   R       RSVD                                                        0
+ */
+typedef union _AON_REG_SRAM_CTRL11_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t WPULSE_retsram_0_lv: 3;
+        uint32_t WA_retsram_0_lv: 3;
+        uint32_t RM_retsram_0_lv: 4;
+        uint32_t RME_retsram_0_lv: 1;
+        uint32_t RA_retsram_0_lv: 2;
+        uint32_t RSVD_1: 3;
+        uint32_t WPULSE_retsram_0_hv: 3;
+        uint32_t WA_retsram_0_hv: 3;
+        uint32_t RM_retsram_0_hv: 4;
+        uint32_t RME_retsram_0_hv: 1;
+        uint32_t RA_retsram_0_hv: 2;
+        uint32_t RSVD: 3;
+    };
+} AON_REG_SRAM_CTRL11_TYPE;
+
+/*0x4000_0854 AON_REG_SRAM_CTRL11*/
+#define AON_REG_SRAM_CTRL11_WPULSE_retsram_0_lv_Pos                                                                      0U
+#define AON_REG_SRAM_CTRL11_WPULSE_retsram_0_lv_Msk                                                                      (0x7UL << AON_REG_SRAM_CTRL11_WPULSE_retsram_0_lv_Pos)
+
+#define AON_REG_SRAM_CTRL11_WA_retsram_0_lv_Pos                                                                          3U
+#define AON_REG_SRAM_CTRL11_WA_retsram_0_lv_Msk                                                                          (0x7UL << AON_REG_SRAM_CTRL11_WA_retsram_0_lv_Pos)
+
+#define AON_REG_SRAM_CTRL11_RM_retsram_0_lv_Pos                                                                          6U
+#define AON_REG_SRAM_CTRL11_RM_retsram_0_lv_Msk                                                                          (0xFUL << AON_REG_SRAM_CTRL11_RM_retsram_0_lv_Pos)
+
+#define AON_REG_SRAM_CTRL11_RME_retsram_0_lv_Pos                                                                         10U
+#define AON_REG_SRAM_CTRL11_RME_retsram_0_lv_Msk                                                                         (0x1UL << AON_REG_SRAM_CTRL11_RME_retsram_0_lv_Pos)
+
+#define AON_REG_SRAM_CTRL11_RA_retsram_0_lv_Pos                                                                          11U
+#define AON_REG_SRAM_CTRL11_RA_retsram_0_lv_Msk                                                                          (0x3UL << AON_REG_SRAM_CTRL11_RA_retsram_0_lv_Pos)
+
+#define AON_REG_SRAM_CTRL11_RSVD_1_Pos                                                                                   13U
+#define AON_REG_SRAM_CTRL11_RSVD_1_Msk                                                                                   (0x7UL << AON_REG_SRAM_CTRL11_RSVD_1_Pos)
+
+#define AON_REG_SRAM_CTRL11_WPULSE_retsram_0_hv_Pos                                                                      16U
+#define AON_REG_SRAM_CTRL11_WPULSE_retsram_0_hv_Msk                                                                      (0x7UL << AON_REG_SRAM_CTRL11_WPULSE_retsram_0_hv_Pos)
+
+#define AON_REG_SRAM_CTRL11_WA_retsram_0_hv_Pos                                                                          19U
+#define AON_REG_SRAM_CTRL11_WA_retsram_0_hv_Msk                                                                          (0x7UL << AON_REG_SRAM_CTRL11_WA_retsram_0_hv_Pos)
+
+#define AON_REG_SRAM_CTRL11_RM_retsram_0_hv_Pos                                                                          22U
+#define AON_REG_SRAM_CTRL11_RM_retsram_0_hv_Msk                                                                          (0xFUL << AON_REG_SRAM_CTRL11_RM_retsram_0_hv_Pos)
+
+#define AON_REG_SRAM_CTRL11_RME_retsram_0_hv_Pos                                                                         26U
+#define AON_REG_SRAM_CTRL11_RME_retsram_0_hv_Msk                                                                         (0x1UL << AON_REG_SRAM_CTRL11_RME_retsram_0_hv_Pos)
+
+#define AON_REG_SRAM_CTRL11_RA_retsram_0_hv_Pos                                                                          27U
+#define AON_REG_SRAM_CTRL11_RA_retsram_0_hv_Msk                                                                          (0x3UL << AON_REG_SRAM_CTRL11_RA_retsram_0_hv_Pos)
+
+#define AON_REG_SRAM_CTRL11_RSVD_Pos                                                                                     29U
+#define AON_REG_SRAM_CTRL11_RSVD_Msk                                                                                     (0x7UL << AON_REG_SRAM_CTRL11_RSVD_Pos)
+
+/* 0x858    0x4000_0858
+    2:0     R/W     WPULSE_retsram_1_lv                                         3'b000
+    5:3     R/W     WA_retsram_1_lv                                             3'b101
+    9:6     R/W     RM_retsram_1_lv                                             4'b0010
+    10      R/W     RME_retsram_1_lv                                            1'b1
+    12:11   R/W     RA_retsram_1_lv                                             2'b00
+    15:13   R       RSVD_1                                                      0
+    18:16   R/W     WPULSE_retsram_1_hv                                         3'b000
+    21:19   R/W     WA_retsram_1_hv                                             3'b100
+    25:22   R/W     RM_retsram_1_hv                                             4'b0011
+    26      R/W     RME_retsram_1_hv                                            1'b1
+    28:27   R/W     RA_retsram_1_hv                                             2'b00
+    31:29   R       RSVD                                                        0
+ */
+typedef union _AON_REG_SRAM_CTRL12_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t WPULSE_retsram_1_lv: 3;
+        uint32_t WA_retsram_1_lv: 3;
+        uint32_t RM_retsram_1_lv: 4;
+        uint32_t RME_retsram_1_lv: 1;
+        uint32_t RA_retsram_1_lv: 2;
+        uint32_t RSVD_1: 3;
+        uint32_t WPULSE_retsram_1_hv: 3;
+        uint32_t WA_retsram_1_hv: 3;
+        uint32_t RM_retsram_1_hv: 4;
+        uint32_t RME_retsram_1_hv: 1;
+        uint32_t RA_retsram_1_hv: 2;
+        uint32_t RSVD: 3;
+    };
+} AON_REG_SRAM_CTRL12_TYPE;
+
+/*0x4000_0858 AON_REG_SRAM_CTRL12*/
+#define AON_REG_SRAM_CTRL12_WPULSE_retsram_1_lv_Pos                                                                      0U
+#define AON_REG_SRAM_CTRL12_WPULSE_retsram_1_lv_Msk                                                                      (0x7UL << AON_REG_SRAM_CTRL12_WPULSE_retsram_1_lv_Pos)
+
+#define AON_REG_SRAM_CTRL12_WA_retsram_1_lv_Pos                                                                          3U
+#define AON_REG_SRAM_CTRL12_WA_retsram_1_lv_Msk                                                                          (0x7UL << AON_REG_SRAM_CTRL12_WA_retsram_1_lv_Pos)
+
+#define AON_REG_SRAM_CTRL12_RM_retsram_1_lv_Pos                                                                          6U
+#define AON_REG_SRAM_CTRL12_RM_retsram_1_lv_Msk                                                                          (0xFUL << AON_REG_SRAM_CTRL12_RM_retsram_1_lv_Pos)
+
+#define AON_REG_SRAM_CTRL12_RME_retsram_1_lv_Pos                                                                         10U
+#define AON_REG_SRAM_CTRL12_RME_retsram_1_lv_Msk                                                                         (0x1UL << AON_REG_SRAM_CTRL12_RME_retsram_1_lv_Pos)
+
+#define AON_REG_SRAM_CTRL12_RA_retsram_1_lv_Pos                                                                          11U
+#define AON_REG_SRAM_CTRL12_RA_retsram_1_lv_Msk                                                                          (0x3UL << AON_REG_SRAM_CTRL12_RA_retsram_1_lv_Pos)
+
+#define AON_REG_SRAM_CTRL12_RSVD_1_Pos                                                                                   13U
+#define AON_REG_SRAM_CTRL12_RSVD_1_Msk                                                                                   (0x7UL << AON_REG_SRAM_CTRL12_RSVD_1_Pos)
+
+#define AON_REG_SRAM_CTRL12_WPULSE_retsram_1_hv_Pos                                                                      16U
+#define AON_REG_SRAM_CTRL12_WPULSE_retsram_1_hv_Msk                                                                      (0x7UL << AON_REG_SRAM_CTRL12_WPULSE_retsram_1_hv_Pos)
+
+#define AON_REG_SRAM_CTRL12_WA_retsram_1_hv_Pos                                                                          19U
+#define AON_REG_SRAM_CTRL12_WA_retsram_1_hv_Msk                                                                          (0x7UL << AON_REG_SRAM_CTRL12_WA_retsram_1_hv_Pos)
+
+#define AON_REG_SRAM_CTRL12_RM_retsram_1_hv_Pos                                                                          22U
+#define AON_REG_SRAM_CTRL12_RM_retsram_1_hv_Msk                                                                          (0xFUL << AON_REG_SRAM_CTRL12_RM_retsram_1_hv_Pos)
+
+#define AON_REG_SRAM_CTRL12_RME_retsram_1_hv_Pos                                                                         26U
+#define AON_REG_SRAM_CTRL12_RME_retsram_1_hv_Msk                                                                         (0x1UL << AON_REG_SRAM_CTRL12_RME_retsram_1_hv_Pos)
+
+#define AON_REG_SRAM_CTRL12_RA_retsram_1_hv_Pos                                                                          27U
+#define AON_REG_SRAM_CTRL12_RA_retsram_1_hv_Msk                                                                          (0x3UL << AON_REG_SRAM_CTRL12_RA_retsram_1_hv_Pos)
+
+#define AON_REG_SRAM_CTRL12_RSVD_Pos                                                                                     29U
+#define AON_REG_SRAM_CTRL12_RSVD_Msk                                                                                     (0x7UL << AON_REG_SRAM_CTRL12_RSVD_Pos)
+
+/* 0x85C    0x4000_085c
+    0       R/W     DS_UNK_low_pwr_cache_0                                      1'b0
+    2:1     R/W     DS_K_low_pwr_cache_0                                        2'b01
+    3       R/W     DS_UNK_low_pwr_cache_1                                      1'b0
+    5:4     R/W     DS_K_low_pwr_cache_1                                        2'b01
+    6       R/W     DS_UNK_low_pwr_cache_2                                      1'b0
+    8:7     R/W     DS_K_low_pwr_cache_2                                        2'b01
+    9       R/W     DS_UNK_low_pwr_cache_3                                      1'b0
+    11:10   R/W     DS_K_low_pwr_cache_3                                        2'b01
+    12      R/W     DS_UNK_low_pwr_cache_4                                      1'b0
+    14:13   R/W     DS_K_low_pwr_cache_4                                        2'b01
+    15      R/W     DS_UNK_low_pwr_cache_5                                      1'b0
+    17:16   R/W     DS_K_low_pwr_cache_5                                        2'b01
+    18      R/W     DS_UNK_low_pwr_cache_6                                      1'b0
+    20:19   R/W     DS_K_low_pwr_cache_6                                        2'b01
+    21      R/W     DS_UNK_low_pwr_cache_7                                      1'b0
+    23:22   R/W     DS_K_low_pwr_cache_7                                        2'b01
+    24      R/W     DS_UNK_low_pwr_cache_8                                      1'b0
+    26:25   R/W     DS_K_low_pwr_cache_8                                        2'b01
+    31:27   R       RSVD                                                        0
+ */
+typedef union _AON_REG_SRAM_CTRL13_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t DS_UNK_low_pwr_cache_0: 1;
+        uint32_t DS_K_low_pwr_cache_0: 2;
+        uint32_t DS_UNK_low_pwr_cache_1: 1;
+        uint32_t DS_K_low_pwr_cache_1: 2;
+        uint32_t DS_UNK_low_pwr_cache_2: 1;
+        uint32_t DS_K_low_pwr_cache_2: 2;
+        uint32_t DS_UNK_low_pwr_cache_3: 1;
+        uint32_t DS_K_low_pwr_cache_3: 2;
+        uint32_t DS_UNK_low_pwr_cache_4: 1;
+        uint32_t DS_K_low_pwr_cache_4: 2;
+        uint32_t DS_UNK_low_pwr_cache_5: 1;
+        uint32_t DS_K_low_pwr_cache_5: 2;
+        uint32_t DS_UNK_low_pwr_cache_6: 1;
+        uint32_t DS_K_low_pwr_cache_6: 2;
+        uint32_t DS_UNK_low_pwr_cache_7: 1;
+        uint32_t DS_K_low_pwr_cache_7: 2;
+        uint32_t DS_UNK_low_pwr_cache_8: 1;
+        uint32_t DS_K_low_pwr_cache_8: 2;
+        uint32_t RSVD: 5;
+    };
+} AON_REG_SRAM_CTRL13_TYPE;
+
+/*0x4000_085c AON_REG_SRAM_CTRL13*/
+#define AON_REG_SRAM_CTRL13_DS_UNK_low_pwr_cache_0_Pos                                                                   0U
+#define AON_REG_SRAM_CTRL13_DS_UNK_low_pwr_cache_0_Msk                                                                   (0x1UL << AON_REG_SRAM_CTRL13_DS_UNK_low_pwr_cache_0_Pos)
+
+#define AON_REG_SRAM_CTRL13_DS_K_low_pwr_cache_0_Pos                                                                     1U
+#define AON_REG_SRAM_CTRL13_DS_K_low_pwr_cache_0_Msk                                                                     (0x3UL << AON_REG_SRAM_CTRL13_DS_K_low_pwr_cache_0_Pos)
+
+#define AON_REG_SRAM_CTRL13_DS_UNK_low_pwr_cache_1_Pos                                                                   3U
+#define AON_REG_SRAM_CTRL13_DS_UNK_low_pwr_cache_1_Msk                                                                   (0x1UL << AON_REG_SRAM_CTRL13_DS_UNK_low_pwr_cache_1_Pos)
+
+#define AON_REG_SRAM_CTRL13_DS_K_low_pwr_cache_1_Pos                                                                     4U
+#define AON_REG_SRAM_CTRL13_DS_K_low_pwr_cache_1_Msk                                                                     (0x3UL << AON_REG_SRAM_CTRL13_DS_K_low_pwr_cache_1_Pos)
+
+#define AON_REG_SRAM_CTRL13_DS_UNK_low_pwr_cache_2_Pos                                                                   6U
+#define AON_REG_SRAM_CTRL13_DS_UNK_low_pwr_cache_2_Msk                                                                   (0x1UL << AON_REG_SRAM_CTRL13_DS_UNK_low_pwr_cache_2_Pos)
+
+#define AON_REG_SRAM_CTRL13_DS_K_low_pwr_cache_2_Pos                                                                     7U
+#define AON_REG_SRAM_CTRL13_DS_K_low_pwr_cache_2_Msk                                                                     (0x3UL << AON_REG_SRAM_CTRL13_DS_K_low_pwr_cache_2_Pos)
+
+#define AON_REG_SRAM_CTRL13_DS_UNK_low_pwr_cache_3_Pos                                                                   9U
+#define AON_REG_SRAM_CTRL13_DS_UNK_low_pwr_cache_3_Msk                                                                   (0x1UL << AON_REG_SRAM_CTRL13_DS_UNK_low_pwr_cache_3_Pos)
+
+#define AON_REG_SRAM_CTRL13_DS_K_low_pwr_cache_3_Pos                                                                     10U
+#define AON_REG_SRAM_CTRL13_DS_K_low_pwr_cache_3_Msk                                                                     (0x3UL << AON_REG_SRAM_CTRL13_DS_K_low_pwr_cache_3_Pos)
+
+#define AON_REG_SRAM_CTRL13_DS_UNK_low_pwr_cache_4_Pos                                                                   12U
+#define AON_REG_SRAM_CTRL13_DS_UNK_low_pwr_cache_4_Msk                                                                   (0x1UL << AON_REG_SRAM_CTRL13_DS_UNK_low_pwr_cache_4_Pos)
+
+#define AON_REG_SRAM_CTRL13_DS_K_low_pwr_cache_4_Pos                                                                     13U
+#define AON_REG_SRAM_CTRL13_DS_K_low_pwr_cache_4_Msk                                                                     (0x3UL << AON_REG_SRAM_CTRL13_DS_K_low_pwr_cache_4_Pos)
+
+#define AON_REG_SRAM_CTRL13_DS_UNK_low_pwr_cache_5_Pos                                                                   15U
+#define AON_REG_SRAM_CTRL13_DS_UNK_low_pwr_cache_5_Msk                                                                   (0x1UL << AON_REG_SRAM_CTRL13_DS_UNK_low_pwr_cache_5_Pos)
+
+#define AON_REG_SRAM_CTRL13_DS_K_low_pwr_cache_5_Pos                                                                     16U
+#define AON_REG_SRAM_CTRL13_DS_K_low_pwr_cache_5_Msk                                                                     (0x3UL << AON_REG_SRAM_CTRL13_DS_K_low_pwr_cache_5_Pos)
+
+#define AON_REG_SRAM_CTRL13_DS_UNK_low_pwr_cache_6_Pos                                                                   18U
+#define AON_REG_SRAM_CTRL13_DS_UNK_low_pwr_cache_6_Msk                                                                   (0x1UL << AON_REG_SRAM_CTRL13_DS_UNK_low_pwr_cache_6_Pos)
+
+#define AON_REG_SRAM_CTRL13_DS_K_low_pwr_cache_6_Pos                                                                     19U
+#define AON_REG_SRAM_CTRL13_DS_K_low_pwr_cache_6_Msk                                                                     (0x3UL << AON_REG_SRAM_CTRL13_DS_K_low_pwr_cache_6_Pos)
+
+#define AON_REG_SRAM_CTRL13_DS_UNK_low_pwr_cache_7_Pos                                                                   21U
+#define AON_REG_SRAM_CTRL13_DS_UNK_low_pwr_cache_7_Msk                                                                   (0x1UL << AON_REG_SRAM_CTRL13_DS_UNK_low_pwr_cache_7_Pos)
+
+#define AON_REG_SRAM_CTRL13_DS_K_low_pwr_cache_7_Pos                                                                     22U
+#define AON_REG_SRAM_CTRL13_DS_K_low_pwr_cache_7_Msk                                                                     (0x3UL << AON_REG_SRAM_CTRL13_DS_K_low_pwr_cache_7_Pos)
+
+#define AON_REG_SRAM_CTRL13_DS_UNK_low_pwr_cache_8_Pos                                                                   24U
+#define AON_REG_SRAM_CTRL13_DS_UNK_low_pwr_cache_8_Msk                                                                   (0x1UL << AON_REG_SRAM_CTRL13_DS_UNK_low_pwr_cache_8_Pos)
+
+#define AON_REG_SRAM_CTRL13_DS_K_low_pwr_cache_8_Pos                                                                     25U
+#define AON_REG_SRAM_CTRL13_DS_K_low_pwr_cache_8_Msk                                                                     (0x3UL << AON_REG_SRAM_CTRL13_DS_K_low_pwr_cache_8_Pos)
+
+#define AON_REG_SRAM_CTRL13_RSVD_Pos                                                                                     27U
+#define AON_REG_SRAM_CTRL13_RSVD_Msk                                                                                     (0x1FUL << AON_REG_SRAM_CTRL13_RSVD_Pos)
+
+/* 0x860    0x4000_0860
+    0       R/W     DS_UNK_norm_pwr_cache_0                                     1'b0
+    2:1     R/W     DS_K_norm_pwr_cache_0                                       2'b01
+    3       R/W     DS_UNK_norm_pwr_cache_1                                     1'b0
+    5:4     R/W     DS_K_norm_pwr_cache_1                                       2'b01
+    6       R/W     DS_UNK_norm_pwr_cache_2                                     1'b0
+    8:7     R/W     DS_K_norm_pwr_cache_2                                       2'b01
+    9       R/W     DS_UNK_norm_pwr_cache_3                                     1'b0
+    11:10   R/W     DS_K_norm_pwr_cache_3                                       2'b01
+    12      R/W     DS_UNK_norm_pwr_cache_4                                     1'b0
+    14:13   R/W     DS_K_norm_pwr_cache_4                                       2'b01
+    15      R/W     DS_UNK_norm_pwr_cache_5                                     1'b0
+    17:16   R/W     DS_K_norm_pwr_cache_5                                       2'b01
+    18      R/W     DS_UNK_norm_pwr_cache_6                                     1'b0
+    20:19   R/W     DS_K_norm_pwr_cache_6                                       2'b01
+    21      R/W     DS_UNK_norm_pwr_cache_7                                     1'b0
+    23:22   R/W     DS_K_norm_pwr_cache_7                                       2'b01
+    24      R/W     DS_UNK_norm_pwr_cache_8                                     1'b0
+    26:25   R/W     DS_K_norm_pwr_cache_8                                       2'b01
+    31:27   R       RSVD                                                        0
+ */
+typedef union _AON_REG_SRAM_CTRL14_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t DS_UNK_norm_pwr_cache_0: 1;
+        uint32_t DS_K_norm_pwr_cache_0: 2;
+        uint32_t DS_UNK_norm_pwr_cache_1: 1;
+        uint32_t DS_K_norm_pwr_cache_1: 2;
+        uint32_t DS_UNK_norm_pwr_cache_2: 1;
+        uint32_t DS_K_norm_pwr_cache_2: 2;
+        uint32_t DS_UNK_norm_pwr_cache_3: 1;
+        uint32_t DS_K_norm_pwr_cache_3: 2;
+        uint32_t DS_UNK_norm_pwr_cache_4: 1;
+        uint32_t DS_K_norm_pwr_cache_4: 2;
+        uint32_t DS_UNK_norm_pwr_cache_5: 1;
+        uint32_t DS_K_norm_pwr_cache_5: 2;
+        uint32_t DS_UNK_norm_pwr_cache_6: 1;
+        uint32_t DS_K_norm_pwr_cache_6: 2;
+        uint32_t DS_UNK_norm_pwr_cache_7: 1;
+        uint32_t DS_K_norm_pwr_cache_7: 2;
+        uint32_t DS_UNK_norm_pwr_cache_8: 1;
+        uint32_t DS_K_norm_pwr_cache_8: 2;
+        uint32_t RSVD: 5;
+    };
+} AON_REG_SRAM_CTRL14_TYPE;
+
+/*0x4000_0860 AON_REG_SRAM_CTRL14*/
+#define AON_REG_SRAM_CTRL14_DS_UNK_norm_pwr_cache_0_Pos                                                                  0U
+#define AON_REG_SRAM_CTRL14_DS_UNK_norm_pwr_cache_0_Msk                                                                  (0x1UL << AON_REG_SRAM_CTRL14_DS_UNK_norm_pwr_cache_0_Pos)
+
+#define AON_REG_SRAM_CTRL14_DS_K_norm_pwr_cache_0_Pos                                                                    1U
+#define AON_REG_SRAM_CTRL14_DS_K_norm_pwr_cache_0_Msk                                                                    (0x3UL << AON_REG_SRAM_CTRL14_DS_K_norm_pwr_cache_0_Pos)
+
+#define AON_REG_SRAM_CTRL14_DS_UNK_norm_pwr_cache_1_Pos                                                                  3U
+#define AON_REG_SRAM_CTRL14_DS_UNK_norm_pwr_cache_1_Msk                                                                  (0x1UL << AON_REG_SRAM_CTRL14_DS_UNK_norm_pwr_cache_1_Pos)
+
+#define AON_REG_SRAM_CTRL14_DS_K_norm_pwr_cache_1_Pos                                                                    4U
+#define AON_REG_SRAM_CTRL14_DS_K_norm_pwr_cache_1_Msk                                                                    (0x3UL << AON_REG_SRAM_CTRL14_DS_K_norm_pwr_cache_1_Pos)
+
+#define AON_REG_SRAM_CTRL14_DS_UNK_norm_pwr_cache_2_Pos                                                                  6U
+#define AON_REG_SRAM_CTRL14_DS_UNK_norm_pwr_cache_2_Msk                                                                  (0x1UL << AON_REG_SRAM_CTRL14_DS_UNK_norm_pwr_cache_2_Pos)
+
+#define AON_REG_SRAM_CTRL14_DS_K_norm_pwr_cache_2_Pos                                                                    7U
+#define AON_REG_SRAM_CTRL14_DS_K_norm_pwr_cache_2_Msk                                                                    (0x3UL << AON_REG_SRAM_CTRL14_DS_K_norm_pwr_cache_2_Pos)
+
+#define AON_REG_SRAM_CTRL14_DS_UNK_norm_pwr_cache_3_Pos                                                                  9U
+#define AON_REG_SRAM_CTRL14_DS_UNK_norm_pwr_cache_3_Msk                                                                  (0x1UL << AON_REG_SRAM_CTRL14_DS_UNK_norm_pwr_cache_3_Pos)
+
+#define AON_REG_SRAM_CTRL14_DS_K_norm_pwr_cache_3_Pos                                                                    10U
+#define AON_REG_SRAM_CTRL14_DS_K_norm_pwr_cache_3_Msk                                                                    (0x3UL << AON_REG_SRAM_CTRL14_DS_K_norm_pwr_cache_3_Pos)
+
+#define AON_REG_SRAM_CTRL14_DS_UNK_norm_pwr_cache_4_Pos                                                                  12U
+#define AON_REG_SRAM_CTRL14_DS_UNK_norm_pwr_cache_4_Msk                                                                  (0x1UL << AON_REG_SRAM_CTRL14_DS_UNK_norm_pwr_cache_4_Pos)
+
+#define AON_REG_SRAM_CTRL14_DS_K_norm_pwr_cache_4_Pos                                                                    13U
+#define AON_REG_SRAM_CTRL14_DS_K_norm_pwr_cache_4_Msk                                                                    (0x3UL << AON_REG_SRAM_CTRL14_DS_K_norm_pwr_cache_4_Pos)
+
+#define AON_REG_SRAM_CTRL14_DS_UNK_norm_pwr_cache_5_Pos                                                                  15U
+#define AON_REG_SRAM_CTRL14_DS_UNK_norm_pwr_cache_5_Msk                                                                  (0x1UL << AON_REG_SRAM_CTRL14_DS_UNK_norm_pwr_cache_5_Pos)
+
+#define AON_REG_SRAM_CTRL14_DS_K_norm_pwr_cache_5_Pos                                                                    16U
+#define AON_REG_SRAM_CTRL14_DS_K_norm_pwr_cache_5_Msk                                                                    (0x3UL << AON_REG_SRAM_CTRL14_DS_K_norm_pwr_cache_5_Pos)
+
+#define AON_REG_SRAM_CTRL14_DS_UNK_norm_pwr_cache_6_Pos                                                                  18U
+#define AON_REG_SRAM_CTRL14_DS_UNK_norm_pwr_cache_6_Msk                                                                  (0x1UL << AON_REG_SRAM_CTRL14_DS_UNK_norm_pwr_cache_6_Pos)
+
+#define AON_REG_SRAM_CTRL14_DS_K_norm_pwr_cache_6_Pos                                                                    19U
+#define AON_REG_SRAM_CTRL14_DS_K_norm_pwr_cache_6_Msk                                                                    (0x3UL << AON_REG_SRAM_CTRL14_DS_K_norm_pwr_cache_6_Pos)
+
+#define AON_REG_SRAM_CTRL14_DS_UNK_norm_pwr_cache_7_Pos                                                                  21U
+#define AON_REG_SRAM_CTRL14_DS_UNK_norm_pwr_cache_7_Msk                                                                  (0x1UL << AON_REG_SRAM_CTRL14_DS_UNK_norm_pwr_cache_7_Pos)
+
+#define AON_REG_SRAM_CTRL14_DS_K_norm_pwr_cache_7_Pos                                                                    22U
+#define AON_REG_SRAM_CTRL14_DS_K_norm_pwr_cache_7_Msk                                                                    (0x3UL << AON_REG_SRAM_CTRL14_DS_K_norm_pwr_cache_7_Pos)
+
+#define AON_REG_SRAM_CTRL14_DS_UNK_norm_pwr_cache_8_Pos                                                                  24U
+#define AON_REG_SRAM_CTRL14_DS_UNK_norm_pwr_cache_8_Msk                                                                  (0x1UL << AON_REG_SRAM_CTRL14_DS_UNK_norm_pwr_cache_8_Pos)
+
+#define AON_REG_SRAM_CTRL14_DS_K_norm_pwr_cache_8_Pos                                                                    25U
+#define AON_REG_SRAM_CTRL14_DS_K_norm_pwr_cache_8_Msk                                                                    (0x3UL << AON_REG_SRAM_CTRL14_DS_K_norm_pwr_cache_8_Pos)
+
+#define AON_REG_SRAM_CTRL14_RSVD_Pos                                                                                     27U
+#define AON_REG_SRAM_CTRL14_RSVD_Msk                                                                                     (0x1FUL << AON_REG_SRAM_CTRL14_RSVD_Pos)
+
+/* 0x864    0x4000_0864
+    0       R/W     DS_low_pwr_cache_0                                          1'b0
+    1       R/W     SD_low_pwr_cache_0                                          1'b0
+    2       R/W     LS_low_pwr_cache_0                                          1'b0
+    3       R/W     DS_low_pwr_cache_1                                          1'b0
+    4       R/W     SD_low_pwr_cache_1                                          1'b0
+    5       R/W     LS_low_pwr_cache_1                                          1'b0
+    6       R/W     DS_low_pwr_cache_2                                          1'b0
+    7       R/W     SD_low_pwr_cache_2                                          1'b0
+    8       R/W     LS_low_pwr_cache_2                                          1'b0
+    9       R/W     DS_low_pwr_cache_3                                          1'b0
+    10      R/W     SD_low_pwr_cache_3                                          1'b0
+    11      R/W     LS_low_pwr_cache_3                                          1'b0
+    15:12   R       RSVD_1                                                      0
+    16      R/W     DS_norm_pwr_cache_0                                         1'b0
+    17      R/W     SD_norm_pwr_cache_0                                         1'b0
+    18      R/W     LS_norm_pwr_cache_0                                         1'b0
+    19      R/W     DS_norm_pwr_cache_1                                         1'b0
+    20      R/W     SD_norm_pwr_cache_1                                         1'b0
+    21      R/W     LS_norm_pwr_cache_1                                         1'b0
+    22      R/W     DS_norm_pwr_cache_2                                         1'b0
+    23      R/W     SD_norm_pwr_cache_2                                         1'b0
+    24      R/W     LS_norm_pwr_cache_2                                         1'b0
+    25      R/W     DS_norm_pwr_cache_3                                         1'b0
+    26      R/W     SD_norm_pwr_cache_3                                         1'b0
+    27      R/W     LS_norm_pwr_cache_3                                         1'b0
+    31:28   R       RSVD                                                        0
+ */
+typedef union _AON_REG_SRAM_CTRL15_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t DS_low_pwr_cache_0: 1;
+        uint32_t SD_low_pwr_cache_0: 1;
+        uint32_t LS_low_pwr_cache_0: 1;
+        uint32_t DS_low_pwr_cache_1: 1;
+        uint32_t SD_low_pwr_cache_1: 1;
+        uint32_t LS_low_pwr_cache_1: 1;
+        uint32_t DS_low_pwr_cache_2: 1;
+        uint32_t SD_low_pwr_cache_2: 1;
+        uint32_t LS_low_pwr_cache_2: 1;
+        uint32_t DS_low_pwr_cache_3: 1;
+        uint32_t SD_low_pwr_cache_3: 1;
+        uint32_t LS_low_pwr_cache_3: 1;
+        uint32_t RSVD_1: 4;
+        uint32_t DS_norm_pwr_cache_0: 1;
+        uint32_t SD_norm_pwr_cache_0: 1;
+        uint32_t LS_norm_pwr_cache_0: 1;
+        uint32_t DS_norm_pwr_cache_1: 1;
+        uint32_t SD_norm_pwr_cache_1: 1;
+        uint32_t LS_norm_pwr_cache_1: 1;
+        uint32_t DS_norm_pwr_cache_2: 1;
+        uint32_t SD_norm_pwr_cache_2: 1;
+        uint32_t LS_norm_pwr_cache_2: 1;
+        uint32_t DS_norm_pwr_cache_3: 1;
+        uint32_t SD_norm_pwr_cache_3: 1;
+        uint32_t LS_norm_pwr_cache_3: 1;
+        uint32_t RSVD: 4;
+    };
+} AON_REG_SRAM_CTRL15_TYPE;
+
+/*0x4000_0864 AON_REG_SRAM_CTRL15*/
+#define AON_REG_SRAM_CTRL15_DS_low_pwr_cache_0_Pos                                                                       0U
+#define AON_REG_SRAM_CTRL15_DS_low_pwr_cache_0_Msk                                                                       (0x1UL << AON_REG_SRAM_CTRL15_DS_low_pwr_cache_0_Pos)
+
+#define AON_REG_SRAM_CTRL15_SD_low_pwr_cache_0_Pos                                                                       1U
+#define AON_REG_SRAM_CTRL15_SD_low_pwr_cache_0_Msk                                                                       (0x1UL << AON_REG_SRAM_CTRL15_SD_low_pwr_cache_0_Pos)
+
+#define AON_REG_SRAM_CTRL15_LS_low_pwr_cache_0_Pos                                                                       2U
+#define AON_REG_SRAM_CTRL15_LS_low_pwr_cache_0_Msk                                                                       (0x1UL << AON_REG_SRAM_CTRL15_LS_low_pwr_cache_0_Pos)
+
+#define AON_REG_SRAM_CTRL15_DS_low_pwr_cache_1_Pos                                                                       3U
+#define AON_REG_SRAM_CTRL15_DS_low_pwr_cache_1_Msk                                                                       (0x1UL << AON_REG_SRAM_CTRL15_DS_low_pwr_cache_1_Pos)
+
+#define AON_REG_SRAM_CTRL15_SD_low_pwr_cache_1_Pos                                                                       4U
+#define AON_REG_SRAM_CTRL15_SD_low_pwr_cache_1_Msk                                                                       (0x1UL << AON_REG_SRAM_CTRL15_SD_low_pwr_cache_1_Pos)
+
+#define AON_REG_SRAM_CTRL15_LS_low_pwr_cache_1_Pos                                                                       5U
+#define AON_REG_SRAM_CTRL15_LS_low_pwr_cache_1_Msk                                                                       (0x1UL << AON_REG_SRAM_CTRL15_LS_low_pwr_cache_1_Pos)
+
+#define AON_REG_SRAM_CTRL15_DS_low_pwr_cache_2_Pos                                                                       6U
+#define AON_REG_SRAM_CTRL15_DS_low_pwr_cache_2_Msk                                                                       (0x1UL << AON_REG_SRAM_CTRL15_DS_low_pwr_cache_2_Pos)
+
+#define AON_REG_SRAM_CTRL15_SD_low_pwr_cache_2_Pos                                                                       7U
+#define AON_REG_SRAM_CTRL15_SD_low_pwr_cache_2_Msk                                                                       (0x1UL << AON_REG_SRAM_CTRL15_SD_low_pwr_cache_2_Pos)
+
+#define AON_REG_SRAM_CTRL15_LS_low_pwr_cache_2_Pos                                                                       8U
+#define AON_REG_SRAM_CTRL15_LS_low_pwr_cache_2_Msk                                                                       (0x1UL << AON_REG_SRAM_CTRL15_LS_low_pwr_cache_2_Pos)
+
+#define AON_REG_SRAM_CTRL15_DS_low_pwr_cache_3_Pos                                                                       9U
+#define AON_REG_SRAM_CTRL15_DS_low_pwr_cache_3_Msk                                                                       (0x1UL << AON_REG_SRAM_CTRL15_DS_low_pwr_cache_3_Pos)
+
+#define AON_REG_SRAM_CTRL15_SD_low_pwr_cache_3_Pos                                                                       10U
+#define AON_REG_SRAM_CTRL15_SD_low_pwr_cache_3_Msk                                                                       (0x1UL << AON_REG_SRAM_CTRL15_SD_low_pwr_cache_3_Pos)
+
+#define AON_REG_SRAM_CTRL15_LS_low_pwr_cache_3_Pos                                                                       11U
+#define AON_REG_SRAM_CTRL15_LS_low_pwr_cache_3_Msk                                                                       (0x1UL << AON_REG_SRAM_CTRL15_LS_low_pwr_cache_3_Pos)
+
+#define AON_REG_SRAM_CTRL15_RSVD_1_Pos                                                                                   12U
+#define AON_REG_SRAM_CTRL15_RSVD_1_Msk                                                                                   (0xFUL << AON_REG_SRAM_CTRL15_RSVD_1_Pos)
+
+#define AON_REG_SRAM_CTRL15_DS_norm_pwr_cache_0_Pos                                                                      16U
+#define AON_REG_SRAM_CTRL15_DS_norm_pwr_cache_0_Msk                                                                      (0x1UL << AON_REG_SRAM_CTRL15_DS_norm_pwr_cache_0_Pos)
+
+#define AON_REG_SRAM_CTRL15_SD_norm_pwr_cache_0_Pos                                                                      17U
+#define AON_REG_SRAM_CTRL15_SD_norm_pwr_cache_0_Msk                                                                      (0x1UL << AON_REG_SRAM_CTRL15_SD_norm_pwr_cache_0_Pos)
+
+#define AON_REG_SRAM_CTRL15_LS_norm_pwr_cache_0_Pos                                                                      18U
+#define AON_REG_SRAM_CTRL15_LS_norm_pwr_cache_0_Msk                                                                      (0x1UL << AON_REG_SRAM_CTRL15_LS_norm_pwr_cache_0_Pos)
+
+#define AON_REG_SRAM_CTRL15_DS_norm_pwr_cache_1_Pos                                                                      19U
+#define AON_REG_SRAM_CTRL15_DS_norm_pwr_cache_1_Msk                                                                      (0x1UL << AON_REG_SRAM_CTRL15_DS_norm_pwr_cache_1_Pos)
+
+#define AON_REG_SRAM_CTRL15_SD_norm_pwr_cache_1_Pos                                                                      20U
+#define AON_REG_SRAM_CTRL15_SD_norm_pwr_cache_1_Msk                                                                      (0x1UL << AON_REG_SRAM_CTRL15_SD_norm_pwr_cache_1_Pos)
+
+#define AON_REG_SRAM_CTRL15_LS_norm_pwr_cache_1_Pos                                                                      21U
+#define AON_REG_SRAM_CTRL15_LS_norm_pwr_cache_1_Msk                                                                      (0x1UL << AON_REG_SRAM_CTRL15_LS_norm_pwr_cache_1_Pos)
+
+#define AON_REG_SRAM_CTRL15_DS_norm_pwr_cache_2_Pos                                                                      22U
+#define AON_REG_SRAM_CTRL15_DS_norm_pwr_cache_2_Msk                                                                      (0x1UL << AON_REG_SRAM_CTRL15_DS_norm_pwr_cache_2_Pos)
+
+#define AON_REG_SRAM_CTRL15_SD_norm_pwr_cache_2_Pos                                                                      23U
+#define AON_REG_SRAM_CTRL15_SD_norm_pwr_cache_2_Msk                                                                      (0x1UL << AON_REG_SRAM_CTRL15_SD_norm_pwr_cache_2_Pos)
+
+#define AON_REG_SRAM_CTRL15_LS_norm_pwr_cache_2_Pos                                                                      24U
+#define AON_REG_SRAM_CTRL15_LS_norm_pwr_cache_2_Msk                                                                      (0x1UL << AON_REG_SRAM_CTRL15_LS_norm_pwr_cache_2_Pos)
+
+#define AON_REG_SRAM_CTRL15_DS_norm_pwr_cache_3_Pos                                                                      25U
+#define AON_REG_SRAM_CTRL15_DS_norm_pwr_cache_3_Msk                                                                      (0x1UL << AON_REG_SRAM_CTRL15_DS_norm_pwr_cache_3_Pos)
+
+#define AON_REG_SRAM_CTRL15_SD_norm_pwr_cache_3_Pos                                                                      26U
+#define AON_REG_SRAM_CTRL15_SD_norm_pwr_cache_3_Msk                                                                      (0x1UL << AON_REG_SRAM_CTRL15_SD_norm_pwr_cache_3_Pos)
+
+#define AON_REG_SRAM_CTRL15_LS_norm_pwr_cache_3_Pos                                                                      27U
+#define AON_REG_SRAM_CTRL15_LS_norm_pwr_cache_3_Msk                                                                      (0x1UL << AON_REG_SRAM_CTRL15_LS_norm_pwr_cache_3_Pos)
+
+#define AON_REG_SRAM_CTRL15_RSVD_Pos                                                                                     28U
+#define AON_REG_SRAM_CTRL15_RSVD_Msk                                                                                     (0xFUL << AON_REG_SRAM_CTRL15_RSVD_Pos)
+
+/* 0x868    0x4000_0868
+    0       R/W     DS_low_pwr_cache_4                                          1'b0
+    1       R/W     SD_low_pwr_cache_4                                          1'b0
+    2       R/W     LS_low_pwr_cache_4                                          1'b0
+    3       R/W     DS_low_pwr_cache_5                                          1'b0
+    4       R/W     SD_low_pwr_cache_5                                          1'b0
+    5       R/W     LS_low_pwr_cache_5                                          1'b0
+    6       R/W     DS_low_pwr_cache_6                                          1'b0
+    7       R/W     SD_low_pwr_cache_6                                          1'b0
+    8       R/W     LS_low_pwr_cache_6                                          1'b0
+    9       R/W     DS_low_pwr_cache_7                                          1'b0
+    10      R/W     SD_low_pwr_cache_7                                          1'b0
+    11      R/W     LS_low_pwr_cache_7                                          1'b0
+    12      R/W     DS_low_pwr_cache_8                                          1'b0
+    13      R/W     SD_low_pwr_cache_8                                          1'b0
+    14      R/W     LS_low_pwr_cache_8                                          1'b0
+    15      R       RSVD_1                                                      0
+    16      R/W     DS_norm_pwr_cache_4                                         1'b0
+    17      R/W     SD_norm_pwr_cache_4                                         1'b0
+    18      R/W     LS_norm_pwr_cache_4                                         1'b0
+    19      R/W     DS_norm_pwr_cache_5                                         1'b0
+    20      R/W     SD_norm_pwr_cache_5                                         1'b0
+    21      R/W     LS_norm_pwr_cache_5                                         1'b0
+    22      R/W     DS_norm_pwr_cache_6                                         1'b0
+    23      R/W     SD_norm_pwr_cache_6                                         1'b0
+    24      R/W     LS_norm_pwr_cache_6                                         1'b0
+    25      R/W     DS_norm_pwr_cache_7                                         1'b0
+    26      R/W     SD_norm_pwr_cache_7                                         1'b0
+    27      R/W     LS_norm_pwr_cache_7                                         1'b0
+    28      R/W     DS_norm_pwr_cache_8                                         1'b0
+    29      R/W     SD_norm_pwr_cache_8                                         1'b0
+    30      R/W     LS_norm_pwr_cache_8                                         1'b0
+    31      R       RSVD                                                        0
+ */
+typedef union _AON_REG_SRAM_CTRL16_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t DS_low_pwr_cache_4: 1;
+        uint32_t SD_low_pwr_cache_4: 1;
+        uint32_t LS_low_pwr_cache_4: 1;
+        uint32_t DS_low_pwr_cache_5: 1;
+        uint32_t SD_low_pwr_cache_5: 1;
+        uint32_t LS_low_pwr_cache_5: 1;
+        uint32_t DS_low_pwr_cache_6: 1;
+        uint32_t SD_low_pwr_cache_6: 1;
+        uint32_t LS_low_pwr_cache_6: 1;
+        uint32_t DS_low_pwr_cache_7: 1;
+        uint32_t SD_low_pwr_cache_7: 1;
+        uint32_t LS_low_pwr_cache_7: 1;
+        uint32_t DS_low_pwr_cache_8: 1;
+        uint32_t SD_low_pwr_cache_8: 1;
+        uint32_t LS_low_pwr_cache_8: 1;
+        uint32_t RSVD_1: 1;
+        uint32_t DS_norm_pwr_cache_4: 1;
+        uint32_t SD_norm_pwr_cache_4: 1;
+        uint32_t LS_norm_pwr_cache_4: 1;
+        uint32_t DS_norm_pwr_cache_5: 1;
+        uint32_t SD_norm_pwr_cache_5: 1;
+        uint32_t LS_norm_pwr_cache_5: 1;
+        uint32_t DS_norm_pwr_cache_6: 1;
+        uint32_t SD_norm_pwr_cache_6: 1;
+        uint32_t LS_norm_pwr_cache_6: 1;
+        uint32_t DS_norm_pwr_cache_7: 1;
+        uint32_t SD_norm_pwr_cache_7: 1;
+        uint32_t LS_norm_pwr_cache_7: 1;
+        uint32_t DS_norm_pwr_cache_8: 1;
+        uint32_t SD_norm_pwr_cache_8: 1;
+        uint32_t LS_norm_pwr_cache_8: 1;
+        uint32_t RSVD: 1;
+    };
+} AON_REG_SRAM_CTRL16_TYPE;
+
+/*0x4000_0868 AON_REG_SRAM_CTRL16*/
+#define AON_REG_SRAM_CTRL16_DS_low_pwr_cache_4_Pos                                                                       0U
+#define AON_REG_SRAM_CTRL16_DS_low_pwr_cache_4_Msk                                                                       (0x1UL << AON_REG_SRAM_CTRL16_DS_low_pwr_cache_4_Pos)
+
+#define AON_REG_SRAM_CTRL16_SD_low_pwr_cache_4_Pos                                                                       1U
+#define AON_REG_SRAM_CTRL16_SD_low_pwr_cache_4_Msk                                                                       (0x1UL << AON_REG_SRAM_CTRL16_SD_low_pwr_cache_4_Pos)
+
+#define AON_REG_SRAM_CTRL16_LS_low_pwr_cache_4_Pos                                                                       2U
+#define AON_REG_SRAM_CTRL16_LS_low_pwr_cache_4_Msk                                                                       (0x1UL << AON_REG_SRAM_CTRL16_LS_low_pwr_cache_4_Pos)
+
+#define AON_REG_SRAM_CTRL16_DS_low_pwr_cache_5_Pos                                                                       3U
+#define AON_REG_SRAM_CTRL16_DS_low_pwr_cache_5_Msk                                                                       (0x1UL << AON_REG_SRAM_CTRL16_DS_low_pwr_cache_5_Pos)
+
+#define AON_REG_SRAM_CTRL16_SD_low_pwr_cache_5_Pos                                                                       4U
+#define AON_REG_SRAM_CTRL16_SD_low_pwr_cache_5_Msk                                                                       (0x1UL << AON_REG_SRAM_CTRL16_SD_low_pwr_cache_5_Pos)
+
+#define AON_REG_SRAM_CTRL16_LS_low_pwr_cache_5_Pos                                                                       5U
+#define AON_REG_SRAM_CTRL16_LS_low_pwr_cache_5_Msk                                                                       (0x1UL << AON_REG_SRAM_CTRL16_LS_low_pwr_cache_5_Pos)
+
+#define AON_REG_SRAM_CTRL16_DS_low_pwr_cache_6_Pos                                                                       6U
+#define AON_REG_SRAM_CTRL16_DS_low_pwr_cache_6_Msk                                                                       (0x1UL << AON_REG_SRAM_CTRL16_DS_low_pwr_cache_6_Pos)
+
+#define AON_REG_SRAM_CTRL16_SD_low_pwr_cache_6_Pos                                                                       7U
+#define AON_REG_SRAM_CTRL16_SD_low_pwr_cache_6_Msk                                                                       (0x1UL << AON_REG_SRAM_CTRL16_SD_low_pwr_cache_6_Pos)
+
+#define AON_REG_SRAM_CTRL16_LS_low_pwr_cache_6_Pos                                                                       8U
+#define AON_REG_SRAM_CTRL16_LS_low_pwr_cache_6_Msk                                                                       (0x1UL << AON_REG_SRAM_CTRL16_LS_low_pwr_cache_6_Pos)
+
+#define AON_REG_SRAM_CTRL16_DS_low_pwr_cache_7_Pos                                                                       9U
+#define AON_REG_SRAM_CTRL16_DS_low_pwr_cache_7_Msk                                                                       (0x1UL << AON_REG_SRAM_CTRL16_DS_low_pwr_cache_7_Pos)
+
+#define AON_REG_SRAM_CTRL16_SD_low_pwr_cache_7_Pos                                                                       10U
+#define AON_REG_SRAM_CTRL16_SD_low_pwr_cache_7_Msk                                                                       (0x1UL << AON_REG_SRAM_CTRL16_SD_low_pwr_cache_7_Pos)
+
+#define AON_REG_SRAM_CTRL16_LS_low_pwr_cache_7_Pos                                                                       11U
+#define AON_REG_SRAM_CTRL16_LS_low_pwr_cache_7_Msk                                                                       (0x1UL << AON_REG_SRAM_CTRL16_LS_low_pwr_cache_7_Pos)
+
+#define AON_REG_SRAM_CTRL16_DS_low_pwr_cache_8_Pos                                                                       12U
+#define AON_REG_SRAM_CTRL16_DS_low_pwr_cache_8_Msk                                                                       (0x1UL << AON_REG_SRAM_CTRL16_DS_low_pwr_cache_8_Pos)
+
+#define AON_REG_SRAM_CTRL16_SD_low_pwr_cache_8_Pos                                                                       13U
+#define AON_REG_SRAM_CTRL16_SD_low_pwr_cache_8_Msk                                                                       (0x1UL << AON_REG_SRAM_CTRL16_SD_low_pwr_cache_8_Pos)
+
+#define AON_REG_SRAM_CTRL16_LS_low_pwr_cache_8_Pos                                                                       14U
+#define AON_REG_SRAM_CTRL16_LS_low_pwr_cache_8_Msk                                                                       (0x1UL << AON_REG_SRAM_CTRL16_LS_low_pwr_cache_8_Pos)
+
+#define AON_REG_SRAM_CTRL16_RSVD_1_Pos                                                                                   15U
+#define AON_REG_SRAM_CTRL16_RSVD_1_Msk                                                                                   (0x1UL << AON_REG_SRAM_CTRL16_RSVD_1_Pos)
+
+#define AON_REG_SRAM_CTRL16_DS_norm_pwr_cache_4_Pos                                                                      16U
+#define AON_REG_SRAM_CTRL16_DS_norm_pwr_cache_4_Msk                                                                      (0x1UL << AON_REG_SRAM_CTRL16_DS_norm_pwr_cache_4_Pos)
+
+#define AON_REG_SRAM_CTRL16_SD_norm_pwr_cache_4_Pos                                                                      17U
+#define AON_REG_SRAM_CTRL16_SD_norm_pwr_cache_4_Msk                                                                      (0x1UL << AON_REG_SRAM_CTRL16_SD_norm_pwr_cache_4_Pos)
+
+#define AON_REG_SRAM_CTRL16_LS_norm_pwr_cache_4_Pos                                                                      18U
+#define AON_REG_SRAM_CTRL16_LS_norm_pwr_cache_4_Msk                                                                      (0x1UL << AON_REG_SRAM_CTRL16_LS_norm_pwr_cache_4_Pos)
+
+#define AON_REG_SRAM_CTRL16_DS_norm_pwr_cache_5_Pos                                                                      19U
+#define AON_REG_SRAM_CTRL16_DS_norm_pwr_cache_5_Msk                                                                      (0x1UL << AON_REG_SRAM_CTRL16_DS_norm_pwr_cache_5_Pos)
+
+#define AON_REG_SRAM_CTRL16_SD_norm_pwr_cache_5_Pos                                                                      20U
+#define AON_REG_SRAM_CTRL16_SD_norm_pwr_cache_5_Msk                                                                      (0x1UL << AON_REG_SRAM_CTRL16_SD_norm_pwr_cache_5_Pos)
+
+#define AON_REG_SRAM_CTRL16_LS_norm_pwr_cache_5_Pos                                                                      21U
+#define AON_REG_SRAM_CTRL16_LS_norm_pwr_cache_5_Msk                                                                      (0x1UL << AON_REG_SRAM_CTRL16_LS_norm_pwr_cache_5_Pos)
+
+#define AON_REG_SRAM_CTRL16_DS_norm_pwr_cache_6_Pos                                                                      22U
+#define AON_REG_SRAM_CTRL16_DS_norm_pwr_cache_6_Msk                                                                      (0x1UL << AON_REG_SRAM_CTRL16_DS_norm_pwr_cache_6_Pos)
+
+#define AON_REG_SRAM_CTRL16_SD_norm_pwr_cache_6_Pos                                                                      23U
+#define AON_REG_SRAM_CTRL16_SD_norm_pwr_cache_6_Msk                                                                      (0x1UL << AON_REG_SRAM_CTRL16_SD_norm_pwr_cache_6_Pos)
+
+#define AON_REG_SRAM_CTRL16_LS_norm_pwr_cache_6_Pos                                                                      24U
+#define AON_REG_SRAM_CTRL16_LS_norm_pwr_cache_6_Msk                                                                      (0x1UL << AON_REG_SRAM_CTRL16_LS_norm_pwr_cache_6_Pos)
+
+#define AON_REG_SRAM_CTRL16_DS_norm_pwr_cache_7_Pos                                                                      25U
+#define AON_REG_SRAM_CTRL16_DS_norm_pwr_cache_7_Msk                                                                      (0x1UL << AON_REG_SRAM_CTRL16_DS_norm_pwr_cache_7_Pos)
+
+#define AON_REG_SRAM_CTRL16_SD_norm_pwr_cache_7_Pos                                                                      26U
+#define AON_REG_SRAM_CTRL16_SD_norm_pwr_cache_7_Msk                                                                      (0x1UL << AON_REG_SRAM_CTRL16_SD_norm_pwr_cache_7_Pos)
+
+#define AON_REG_SRAM_CTRL16_LS_norm_pwr_cache_7_Pos                                                                      27U
+#define AON_REG_SRAM_CTRL16_LS_norm_pwr_cache_7_Msk                                                                      (0x1UL << AON_REG_SRAM_CTRL16_LS_norm_pwr_cache_7_Pos)
+
+#define AON_REG_SRAM_CTRL16_DS_norm_pwr_cache_8_Pos                                                                      28U
+#define AON_REG_SRAM_CTRL16_DS_norm_pwr_cache_8_Msk                                                                      (0x1UL << AON_REG_SRAM_CTRL16_DS_norm_pwr_cache_8_Pos)
+
+#define AON_REG_SRAM_CTRL16_SD_norm_pwr_cache_8_Pos                                                                      29U
+#define AON_REG_SRAM_CTRL16_SD_norm_pwr_cache_8_Msk                                                                      (0x1UL << AON_REG_SRAM_CTRL16_SD_norm_pwr_cache_8_Pos)
+
+#define AON_REG_SRAM_CTRL16_LS_norm_pwr_cache_8_Pos                                                                      30U
+#define AON_REG_SRAM_CTRL16_LS_norm_pwr_cache_8_Msk                                                                      (0x1UL << AON_REG_SRAM_CTRL16_LS_norm_pwr_cache_8_Pos)
+
+#define AON_REG_SRAM_CTRL16_RSVD_Pos                                                                                     31U
+#define AON_REG_SRAM_CTRL16_RSVD_Msk                                                                                     (0x1UL << AON_REG_SRAM_CTRL16_RSVD_Pos)
+
+/* 0x86C    0x4000_086c
+    0       R/W     TEST1_cache_0                                               1'b0
+    3:1     R/W     WPULSE_cache_0_lv                                           3'b000
+    6:4     R/W     WA_cache_0_lv                                               3'b101
+    10:7    R/W     RM_cache_0_lv                                               4'b0010
+    11      R/W     RME_cache_0_lv                                              1'b1
+    13:12   R/W     RA_cache_0_lv                                               2'b00
+    15:14   R       RSVD_1                                                      0
+    18:16   R/W     WPULSE_cache_0_hv                                           3'b000
+    21:19   R/W     WA_cache_0_hv                                               3'b101
+    25:22   R/W     RM_cache_0_hv                                               4'b0010
+    26      R/W     RME_cache_0_hv                                              1'b1
+    28:27   R/W     RA_cache_0_hv                                               2'b00
+    31:29   R       RSVD                                                        0
+ */
+typedef union _AON_REG_SRAM_CTRL17_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t TEST1_cache_0: 1;
+        uint32_t WPULSE_cache_0_lv: 3;
+        uint32_t WA_cache_0_lv: 3;
+        uint32_t RM_cache_0_lv: 4;
+        uint32_t RME_cache_0_lv: 1;
+        uint32_t RA_cache_0_lv: 2;
+        uint32_t RSVD_1: 2;
+        uint32_t WPULSE_cache_0_hv: 3;
+        uint32_t WA_cache_0_hv: 3;
+        uint32_t RM_cache_0_hv: 4;
+        uint32_t RME_cache_0_hv: 1;
+        uint32_t RA_cache_0_hv: 2;
+        uint32_t RSVD: 3;
+    };
+} AON_REG_SRAM_CTRL17_TYPE;
+
+/*0x4000_086c AON_REG_SRAM_CTRL17*/
+#define AON_REG_SRAM_CTRL17_TEST1_cache_0_Pos                                                                            0U
+#define AON_REG_SRAM_CTRL17_TEST1_cache_0_Msk                                                                            (0x1UL << AON_REG_SRAM_CTRL17_TEST1_cache_0_Pos)
+
+#define AON_REG_SRAM_CTRL17_WPULSE_cache_0_lv_Pos                                                                        1U
+#define AON_REG_SRAM_CTRL17_WPULSE_cache_0_lv_Msk                                                                        (0x7UL << AON_REG_SRAM_CTRL17_WPULSE_cache_0_lv_Pos)
+
+#define AON_REG_SRAM_CTRL17_WA_cache_0_lv_Pos                                                                            4U
+#define AON_REG_SRAM_CTRL17_WA_cache_0_lv_Msk                                                                            (0x7UL << AON_REG_SRAM_CTRL17_WA_cache_0_lv_Pos)
+
+#define AON_REG_SRAM_CTRL17_RM_cache_0_lv_Pos                                                                            7U
+#define AON_REG_SRAM_CTRL17_RM_cache_0_lv_Msk                                                                            (0xFUL << AON_REG_SRAM_CTRL17_RM_cache_0_lv_Pos)
+
+#define AON_REG_SRAM_CTRL17_RME_cache_0_lv_Pos                                                                           11U
+#define AON_REG_SRAM_CTRL17_RME_cache_0_lv_Msk                                                                           (0x1UL << AON_REG_SRAM_CTRL17_RME_cache_0_lv_Pos)
+
+#define AON_REG_SRAM_CTRL17_RA_cache_0_lv_Pos                                                                            12U
+#define AON_REG_SRAM_CTRL17_RA_cache_0_lv_Msk                                                                            (0x3UL << AON_REG_SRAM_CTRL17_RA_cache_0_lv_Pos)
+
+#define AON_REG_SRAM_CTRL17_RSVD_1_Pos                                                                                   14U
+#define AON_REG_SRAM_CTRL17_RSVD_1_Msk                                                                                   (0x3UL << AON_REG_SRAM_CTRL17_RSVD_1_Pos)
+
+#define AON_REG_SRAM_CTRL17_WPULSE_cache_0_hv_Pos                                                                        16U
+#define AON_REG_SRAM_CTRL17_WPULSE_cache_0_hv_Msk                                                                        (0x7UL << AON_REG_SRAM_CTRL17_WPULSE_cache_0_hv_Pos)
+
+#define AON_REG_SRAM_CTRL17_WA_cache_0_hv_Pos                                                                            19U
+#define AON_REG_SRAM_CTRL17_WA_cache_0_hv_Msk                                                                            (0x7UL << AON_REG_SRAM_CTRL17_WA_cache_0_hv_Pos)
+
+#define AON_REG_SRAM_CTRL17_RM_cache_0_hv_Pos                                                                            22U
+#define AON_REG_SRAM_CTRL17_RM_cache_0_hv_Msk                                                                            (0xFUL << AON_REG_SRAM_CTRL17_RM_cache_0_hv_Pos)
+
+#define AON_REG_SRAM_CTRL17_RME_cache_0_hv_Pos                                                                           26U
+#define AON_REG_SRAM_CTRL17_RME_cache_0_hv_Msk                                                                           (0x1UL << AON_REG_SRAM_CTRL17_RME_cache_0_hv_Pos)
+
+#define AON_REG_SRAM_CTRL17_RA_cache_0_hv_Pos                                                                            27U
+#define AON_REG_SRAM_CTRL17_RA_cache_0_hv_Msk                                                                            (0x3UL << AON_REG_SRAM_CTRL17_RA_cache_0_hv_Pos)
+
+#define AON_REG_SRAM_CTRL17_RSVD_Pos                                                                                     29U
+#define AON_REG_SRAM_CTRL17_RSVD_Msk                                                                                     (0x7UL << AON_REG_SRAM_CTRL17_RSVD_Pos)
+
+/* 0x870    0x4000_0870
+    0       R/W     TEST1_cache_1                                               1'b0
+    3:1     R/W     WPULSE_cache_1_lv                                           3'b000
+    6:4     R/W     WA_cache_1_lv                                               3'b101
+    10:7    R/W     RM_cache_1_lv                                               4'b0010
+    11      R/W     RME_cache_1_lv                                              1'b1
+    13:12   R/W     RA_cache_1_lv                                               2'b00
+    15:14   R       RSVD_1                                                      0
+    18:16   R/W     WPULSE_cache_1_hv                                           3'b000
+    21:19   R/W     WA_cache_1_hv                                               3'b101
+    25:22   R/W     RM_cache_1_hv                                               4'b0010
+    26      R/W     RME_cache_1_hv                                              1'b1
+    28:27   R/W     RA_cache_1_hv                                               2'b00
+    31:29   R       RSVD                                                        0
+ */
+typedef union _AON_REG_SRAM_CTRL18_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t TEST1_cache_1: 1;
+        uint32_t WPULSE_cache_1_lv: 3;
+        uint32_t WA_cache_1_lv: 3;
+        uint32_t RM_cache_1_lv: 4;
+        uint32_t RME_cache_1_lv: 1;
+        uint32_t RA_cache_1_lv: 2;
+        uint32_t RSVD_1: 2;
+        uint32_t WPULSE_cache_1_hv: 3;
+        uint32_t WA_cache_1_hv: 3;
+        uint32_t RM_cache_1_hv: 4;
+        uint32_t RME_cache_1_hv: 1;
+        uint32_t RA_cache_1_hv: 2;
+        uint32_t RSVD: 3;
+    };
+} AON_REG_SRAM_CTRL18_TYPE;
+
+/*0x4000_0870 AON_REG_SRAM_CTRL18*/
+#define AON_REG_SRAM_CTRL18_TEST1_cache_1_Pos                                                                            0U
+#define AON_REG_SRAM_CTRL18_TEST1_cache_1_Msk                                                                            (0x1UL << AON_REG_SRAM_CTRL18_TEST1_cache_1_Pos)
+
+#define AON_REG_SRAM_CTRL18_WPULSE_cache_1_lv_Pos                                                                        1U
+#define AON_REG_SRAM_CTRL18_WPULSE_cache_1_lv_Msk                                                                        (0x7UL << AON_REG_SRAM_CTRL18_WPULSE_cache_1_lv_Pos)
+
+#define AON_REG_SRAM_CTRL18_WA_cache_1_lv_Pos                                                                            4U
+#define AON_REG_SRAM_CTRL18_WA_cache_1_lv_Msk                                                                            (0x7UL << AON_REG_SRAM_CTRL18_WA_cache_1_lv_Pos)
+
+#define AON_REG_SRAM_CTRL18_RM_cache_1_lv_Pos                                                                            7U
+#define AON_REG_SRAM_CTRL18_RM_cache_1_lv_Msk                                                                            (0xFUL << AON_REG_SRAM_CTRL18_RM_cache_1_lv_Pos)
+
+#define AON_REG_SRAM_CTRL18_RME_cache_1_lv_Pos                                                                           11U
+#define AON_REG_SRAM_CTRL18_RME_cache_1_lv_Msk                                                                           (0x1UL << AON_REG_SRAM_CTRL18_RME_cache_1_lv_Pos)
+
+#define AON_REG_SRAM_CTRL18_RA_cache_1_lv_Pos                                                                            12U
+#define AON_REG_SRAM_CTRL18_RA_cache_1_lv_Msk                                                                            (0x3UL << AON_REG_SRAM_CTRL18_RA_cache_1_lv_Pos)
+
+#define AON_REG_SRAM_CTRL18_RSVD_1_Pos                                                                                   14U
+#define AON_REG_SRAM_CTRL18_RSVD_1_Msk                                                                                   (0x3UL << AON_REG_SRAM_CTRL18_RSVD_1_Pos)
+
+#define AON_REG_SRAM_CTRL18_WPULSE_cache_1_hv_Pos                                                                        16U
+#define AON_REG_SRAM_CTRL18_WPULSE_cache_1_hv_Msk                                                                        (0x7UL << AON_REG_SRAM_CTRL18_WPULSE_cache_1_hv_Pos)
+
+#define AON_REG_SRAM_CTRL18_WA_cache_1_hv_Pos                                                                            19U
+#define AON_REG_SRAM_CTRL18_WA_cache_1_hv_Msk                                                                            (0x7UL << AON_REG_SRAM_CTRL18_WA_cache_1_hv_Pos)
+
+#define AON_REG_SRAM_CTRL18_RM_cache_1_hv_Pos                                                                            22U
+#define AON_REG_SRAM_CTRL18_RM_cache_1_hv_Msk                                                                            (0xFUL << AON_REG_SRAM_CTRL18_RM_cache_1_hv_Pos)
+
+#define AON_REG_SRAM_CTRL18_RME_cache_1_hv_Pos                                                                           26U
+#define AON_REG_SRAM_CTRL18_RME_cache_1_hv_Msk                                                                           (0x1UL << AON_REG_SRAM_CTRL18_RME_cache_1_hv_Pos)
+
+#define AON_REG_SRAM_CTRL18_RA_cache_1_hv_Pos                                                                            27U
+#define AON_REG_SRAM_CTRL18_RA_cache_1_hv_Msk                                                                            (0x3UL << AON_REG_SRAM_CTRL18_RA_cache_1_hv_Pos)
+
+#define AON_REG_SRAM_CTRL18_RSVD_Pos                                                                                     29U
+#define AON_REG_SRAM_CTRL18_RSVD_Msk                                                                                     (0x7UL << AON_REG_SRAM_CTRL18_RSVD_Pos)
+
+/* 0x874    0x4000_0874
+    0       R/W     TEST1_cache_2                                               1'b0
+    3:1     R/W     WPULSE_cache_2_lv                                           3'b000
+    6:4     R/W     WA_cache_2_lv                                               3'b101
+    10:7    R/W     RM_cache_2_lv                                               4'b0010
+    11      R/W     RME_cache_2_lv                                              1'b1
+    13:12   R/W     RA_cache_2_lv                                               2'b00
+    15:14   R       RSVD_1                                                      0
+    18:16   R/W     WPULSE_cache_2_hv                                           3'b000
+    21:19   R/W     WA_cache_2_hv                                               3'b101
+    25:22   R/W     RM_cache_2_hv                                               4'b0010
+    26      R/W     RME_cache_2_hv                                              1'b1
+    28:27   R/W     RA_cache_2_hv                                               2'b00
+    31:29   R       RSVD                                                        0
+ */
+typedef union _AON_REG_SRAM_CTRL19_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t TEST1_cache_2: 1;
+        uint32_t WPULSE_cache_2_lv: 3;
+        uint32_t WA_cache_2_lv: 3;
+        uint32_t RM_cache_2_lv: 4;
+        uint32_t RME_cache_2_lv: 1;
+        uint32_t RA_cache_2_lv: 2;
+        uint32_t RSVD_1: 2;
+        uint32_t WPULSE_cache_2_hv: 3;
+        uint32_t WA_cache_2_hv: 3;
+        uint32_t RM_cache_2_hv: 4;
+        uint32_t RME_cache_2_hv: 1;
+        uint32_t RA_cache_2_hv: 2;
+        uint32_t RSVD: 3;
+    };
+} AON_REG_SRAM_CTRL19_TYPE;
+
+/*0x4000_0874 AON_REG_SRAM_CTRL19*/
+#define AON_REG_SRAM_CTRL19_TEST1_cache_2_Pos                                                                            0U
+#define AON_REG_SRAM_CTRL19_TEST1_cache_2_Msk                                                                            (0x1UL << AON_REG_SRAM_CTRL19_TEST1_cache_2_Pos)
+
+#define AON_REG_SRAM_CTRL19_WPULSE_cache_2_lv_Pos                                                                        1U
+#define AON_REG_SRAM_CTRL19_WPULSE_cache_2_lv_Msk                                                                        (0x7UL << AON_REG_SRAM_CTRL19_WPULSE_cache_2_lv_Pos)
+
+#define AON_REG_SRAM_CTRL19_WA_cache_2_lv_Pos                                                                            4U
+#define AON_REG_SRAM_CTRL19_WA_cache_2_lv_Msk                                                                            (0x7UL << AON_REG_SRAM_CTRL19_WA_cache_2_lv_Pos)
+
+#define AON_REG_SRAM_CTRL19_RM_cache_2_lv_Pos                                                                            7U
+#define AON_REG_SRAM_CTRL19_RM_cache_2_lv_Msk                                                                            (0xFUL << AON_REG_SRAM_CTRL19_RM_cache_2_lv_Pos)
+
+#define AON_REG_SRAM_CTRL19_RME_cache_2_lv_Pos                                                                           11U
+#define AON_REG_SRAM_CTRL19_RME_cache_2_lv_Msk                                                                           (0x1UL << AON_REG_SRAM_CTRL19_RME_cache_2_lv_Pos)
+
+#define AON_REG_SRAM_CTRL19_RA_cache_2_lv_Pos                                                                            12U
+#define AON_REG_SRAM_CTRL19_RA_cache_2_lv_Msk                                                                            (0x3UL << AON_REG_SRAM_CTRL19_RA_cache_2_lv_Pos)
+
+#define AON_REG_SRAM_CTRL19_RSVD_1_Pos                                                                                   14U
+#define AON_REG_SRAM_CTRL19_RSVD_1_Msk                                                                                   (0x3UL << AON_REG_SRAM_CTRL19_RSVD_1_Pos)
+
+#define AON_REG_SRAM_CTRL19_WPULSE_cache_2_hv_Pos                                                                        16U
+#define AON_REG_SRAM_CTRL19_WPULSE_cache_2_hv_Msk                                                                        (0x7UL << AON_REG_SRAM_CTRL19_WPULSE_cache_2_hv_Pos)
+
+#define AON_REG_SRAM_CTRL19_WA_cache_2_hv_Pos                                                                            19U
+#define AON_REG_SRAM_CTRL19_WA_cache_2_hv_Msk                                                                            (0x7UL << AON_REG_SRAM_CTRL19_WA_cache_2_hv_Pos)
+
+#define AON_REG_SRAM_CTRL19_RM_cache_2_hv_Pos                                                                            22U
+#define AON_REG_SRAM_CTRL19_RM_cache_2_hv_Msk                                                                            (0xFUL << AON_REG_SRAM_CTRL19_RM_cache_2_hv_Pos)
+
+#define AON_REG_SRAM_CTRL19_RME_cache_2_hv_Pos                                                                           26U
+#define AON_REG_SRAM_CTRL19_RME_cache_2_hv_Msk                                                                           (0x1UL << AON_REG_SRAM_CTRL19_RME_cache_2_hv_Pos)
+
+#define AON_REG_SRAM_CTRL19_RA_cache_2_hv_Pos                                                                            27U
+#define AON_REG_SRAM_CTRL19_RA_cache_2_hv_Msk                                                                            (0x3UL << AON_REG_SRAM_CTRL19_RA_cache_2_hv_Pos)
+
+#define AON_REG_SRAM_CTRL19_RSVD_Pos                                                                                     29U
+#define AON_REG_SRAM_CTRL19_RSVD_Msk                                                                                     (0x7UL << AON_REG_SRAM_CTRL19_RSVD_Pos)
+
+/* 0x878    0x4000_0878
+    31:0    R/W     DUMMY0                                                      0
+ */
+typedef union _AON_REG_SRAM_CTRL20_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t DUMMY0;
+    };
+} AON_REG_SRAM_CTRL20_TYPE;
+
+/*0x4000_0878 AON_REG_SRAM_CTRL20*/
+#define AON_REG_SRAM_CTRL20_DUMMY0_Pos                                                                                   0U
+#define AON_REG_SRAM_CTRL20_DUMMY0_Msk                                                                                   (0xFFFFFFFFUL << AON_REG_SRAM_CTRL20_DUMMY0_Pos)
+
+/* 0x87C    0x4000_087c
+    31:0    R       DUMMY1                                                      0
+ */
+typedef union _AON_REG_SRAM_CTRL21_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t DUMMY1;
+    };
+} AON_REG_SRAM_CTRL21_TYPE;
+
+/*0x4000_087c AON_REG_SRAM_CTRL21*/
+#define AON_REG_SRAM_CTRL21_DUMMY1_Pos                                                                                   0U
+#define AON_REG_SRAM_CTRL21_DUMMY1_Msk                                                                                   (0xFFFFFFFFUL << AON_REG_SRAM_CTRL21_DUMMY1_Pos)
+
+/* 0x880    0x4000_0880
+    0       R/W     PGEN_rom_0                                                  1'b0
+    1       R/W     KEN_rom_0                                                   1'b1
+    4:2     R/W     EMA_rom_0_lv                                                3'b011
+    7:5     R/W     EMA_rom_0_hv                                                3'b010
+    31:8    R       RSVD                                                        0
+ */
+typedef union _AON_REG_SRAM_CTRL22_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t PGEN_rom_0: 1;
+        uint32_t KEN_rom_0: 1;
+        uint32_t EMA_rom_0_lv: 3;
+        uint32_t EMA_rom_0_hv: 3;
+        uint32_t RSVD: 24;
+    };
+} AON_REG_SRAM_CTRL22_TYPE;
+
+/*0x4000_0880 AON_REG_SRAM_CTRL22*/
+#define AON_REG_SRAM_CTRL22_PGEN_rom_0_Pos                                                                               0U
+#define AON_REG_SRAM_CTRL22_PGEN_rom_0_Msk                                                                               (0x1UL << AON_REG_SRAM_CTRL22_PGEN_rom_0_Pos)
+
+#define AON_REG_SRAM_CTRL22_KEN_rom_0_Pos                                                                                1U
+#define AON_REG_SRAM_CTRL22_KEN_rom_0_Msk                                                                                (0x1UL << AON_REG_SRAM_CTRL22_KEN_rom_0_Pos)
+
+#define AON_REG_SRAM_CTRL22_EMA_rom_0_lv_Pos                                                                             2U
+#define AON_REG_SRAM_CTRL22_EMA_rom_0_lv_Msk                                                                             (0x7UL << AON_REG_SRAM_CTRL22_EMA_rom_0_lv_Pos)
+
+#define AON_REG_SRAM_CTRL22_EMA_rom_0_hv_Pos                                                                             5U
+#define AON_REG_SRAM_CTRL22_EMA_rom_0_hv_Msk                                                                             (0x7UL << AON_REG_SRAM_CTRL22_EMA_rom_0_hv_Pos)
+
+#define AON_REG_SRAM_CTRL22_RSVD_Pos                                                                                     8U
+#define AON_REG_SRAM_CTRL22_RSVD_Msk                                                                                     (0xFFFFFFUL << AON_REG_SRAM_CTRL22_RSVD_Pos)
+
+/* 0x884    0x4000_0884
+    2:0     R/W     EMA_cpu                                                     3'b011
+    5:3     R/W     EMA_usb                                                     3'b010
+    8:6     R/W     EMA_can                                                     3'b011
+    11:9    R/W     EMA_lebis                                                   3'b011
+    14:12   R/W     EMA_audio                                                   3'b011
+    17:15   R/W     EMA_btphy                                                   3'b011
+    20:18   R/W     EMA_ccmp                                                    3'b011
+    23:21   R/W     EMA_snps                                                    3'b011
+    31:24   R       RSVD                                                        0
+ */
+typedef union _AON_REG_SRAM_CTRL23_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t EMA_cpu: 3;
+        uint32_t EMA_usb: 3;
+        uint32_t EMA_can: 3;
+        uint32_t EMA_lebis: 3;
+        uint32_t EMA_audio: 3;
+        uint32_t EMA_btphy: 3;
+        uint32_t EMA_ccmp: 3;
+        uint32_t EMA_snps: 3;
+        uint32_t RSVD: 8;
+    };
+} AON_REG_SRAM_CTRL23_TYPE;
+
+/*0x4000_0884 AON_REG_SRAM_CTRL23*/
+#define AON_REG_SRAM_CTRL23_EMA_cpu_Pos                                                                                  0U
+#define AON_REG_SRAM_CTRL23_EMA_cpu_Msk                                                                                  (0x7UL << AON_REG_SRAM_CTRL23_EMA_cpu_Pos)
+
+#define AON_REG_SRAM_CTRL23_EMA_usb_Pos                                                                                  3U
+#define AON_REG_SRAM_CTRL23_EMA_usb_Msk                                                                                  (0x7UL << AON_REG_SRAM_CTRL23_EMA_usb_Pos)
+
+#define AON_REG_SRAM_CTRL23_EMA_can_Pos                                                                                  6U
+#define AON_REG_SRAM_CTRL23_EMA_can_Msk                                                                                  (0x7UL << AON_REG_SRAM_CTRL23_EMA_can_Pos)
+
+#define AON_REG_SRAM_CTRL23_EMA_lebis_Pos                                                                                9U
+#define AON_REG_SRAM_CTRL23_EMA_lebis_Msk                                                                                (0x7UL << AON_REG_SRAM_CTRL23_EMA_lebis_Pos)
+
+#define AON_REG_SRAM_CTRL23_EMA_audio_Pos                                                                                12U
+#define AON_REG_SRAM_CTRL23_EMA_audio_Msk                                                                                (0x7UL << AON_REG_SRAM_CTRL23_EMA_audio_Pos)
+
+#define AON_REG_SRAM_CTRL23_EMA_btphy_Pos                                                                                15U
+#define AON_REG_SRAM_CTRL23_EMA_btphy_Msk                                                                                (0x7UL << AON_REG_SRAM_CTRL23_EMA_btphy_Pos)
+
+#define AON_REG_SRAM_CTRL23_EMA_ccmp_Pos                                                                                 18U
+#define AON_REG_SRAM_CTRL23_EMA_ccmp_Msk                                                                                 (0x7UL << AON_REG_SRAM_CTRL23_EMA_ccmp_Pos)
+
+#define AON_REG_SRAM_CTRL23_EMA_snps_Pos                                                                                 21U
+#define AON_REG_SRAM_CTRL23_EMA_snps_Msk                                                                                 (0x7UL << AON_REG_SRAM_CTRL23_EMA_snps_Pos)
+
+#define AON_REG_SRAM_CTRL23_RSVD_Pos                                                                                     24U
+#define AON_REG_SRAM_CTRL23_RSVD_Msk                                                                                     (0xFFUL << AON_REG_SRAM_CTRL23_RSVD_Pos)
+
+/* 0x888    0x4000_0888
+    2:0     R/W     EMA_cpu                                                     3'b010
+    5:3     R/W     EMA_usb                                                     3'b010
+    8:6     R/W     EMA_can                                                     3'b010
+    11:9    R/W     EMA_lebis                                                   3'b010
+    14:12   R/W     EMA_audio                                                   3'b010
+    17:15   R/W     EMA_btphy                                                   3'b010
+    20:18   R/W     EMA_ccmp                                                    3'b010
+    23:21   R/W     EMA_snps                                                    3'b010
+    31:24   R       RSVD                                                        0
+ */
+typedef union _AON_REG_SRAM_CTRL24_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t EMA_cpu: 3;
+        uint32_t EMA_usb: 3;
+        uint32_t EMA_can: 3;
+        uint32_t EMA_lebis: 3;
+        uint32_t EMA_audio: 3;
+        uint32_t EMA_btphy: 3;
+        uint32_t EMA_ccmp: 3;
+        uint32_t EMA_snps: 3;
+        uint32_t RSVD: 8;
+    };
+} AON_REG_SRAM_CTRL24_TYPE;
+
+/*0x4000_0888 AON_REG_SRAM_CTRL24*/
+#define AON_REG_SRAM_CTRL24_EMA_cpu_Pos                                                                                  0U
+#define AON_REG_SRAM_CTRL24_EMA_cpu_Msk                                                                                  (0x7UL << AON_REG_SRAM_CTRL24_EMA_cpu_Pos)
+
+#define AON_REG_SRAM_CTRL24_EMA_usb_Pos                                                                                  3U
+#define AON_REG_SRAM_CTRL24_EMA_usb_Msk                                                                                  (0x7UL << AON_REG_SRAM_CTRL24_EMA_usb_Pos)
+
+#define AON_REG_SRAM_CTRL24_EMA_can_Pos                                                                                  6U
+#define AON_REG_SRAM_CTRL24_EMA_can_Msk                                                                                  (0x7UL << AON_REG_SRAM_CTRL24_EMA_can_Pos)
+
+#define AON_REG_SRAM_CTRL24_EMA_lebis_Pos                                                                                9U
+#define AON_REG_SRAM_CTRL24_EMA_lebis_Msk                                                                                (0x7UL << AON_REG_SRAM_CTRL24_EMA_lebis_Pos)
+
+#define AON_REG_SRAM_CTRL24_EMA_audio_Pos                                                                                12U
+#define AON_REG_SRAM_CTRL24_EMA_audio_Msk                                                                                (0x7UL << AON_REG_SRAM_CTRL24_EMA_audio_Pos)
+
+#define AON_REG_SRAM_CTRL24_EMA_btphy_Pos                                                                                15U
+#define AON_REG_SRAM_CTRL24_EMA_btphy_Msk                                                                                (0x7UL << AON_REG_SRAM_CTRL24_EMA_btphy_Pos)
+
+#define AON_REG_SRAM_CTRL24_EMA_ccmp_Pos                                                                                 18U
+#define AON_REG_SRAM_CTRL24_EMA_ccmp_Msk                                                                                 (0x7UL << AON_REG_SRAM_CTRL24_EMA_ccmp_Pos)
+
+#define AON_REG_SRAM_CTRL24_EMA_snps_Pos                                                                                 21U
+#define AON_REG_SRAM_CTRL24_EMA_snps_Msk                                                                                 (0x7UL << AON_REG_SRAM_CTRL24_EMA_snps_Pos)
+
+#define AON_REG_SRAM_CTRL24_RSVD_Pos                                                                                     24U
+#define AON_REG_SRAM_CTRL24_RSVD_Msk                                                                                     (0xFFUL << AON_REG_SRAM_CTRL24_RSVD_Pos)
+
+/* 0x88C    0x4000_088c
+    1:0     R/W     EMAW_cpu_lv                                                 2'b01
+    3:2     R/W     EMAW_usb_lv                                                 2'b01
+    5:4     R/W     EMAW_can_lv                                                 2'b01
+    7:6     R/W     EMAW_lebis_lv                                               2'b01
+    9:8     R/W     EMAW_audio_lv                                               2'b01
+    11:10   R/W     EMAW_btphy_lv                                               2'b01
+    13:12   R/W     EMAW_ccmp_lv                                                2'b01
+    15:14   R/W     EMAW_snps_lv                                                2'b01
+    17:16   R/W     EMAW_cpu_hv                                                 2'b01
+    19:18   R/W     EMAW_usb_hv                                                 2'b01
+    21:20   R/W     EMAW_can_hv                                                 2'b01
+    23:22   R/W     EMAW_lebis_hv                                               2'b01
+    25:24   R/W     EMAW_audio_hv                                               2'b01
+    27:26   R/W     EMAW_btphy_hv                                               2'b01
+    29:28   R/W     EMAW_ccmp_hv                                                2'b01
+    31:30   R/W     EMAW_snps_hv                                                2'b01
+ */
+typedef union _AON_REG_SRAM_CTRL25_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t EMAW_cpu_lv: 2;
+        uint32_t EMAW_usb_lv: 2;
+        uint32_t EMAW_can_lv: 2;
+        uint32_t EMAW_lebis_lv: 2;
+        uint32_t EMAW_audio_lv: 2;
+        uint32_t EMAW_btphy_lv: 2;
+        uint32_t EMAW_ccmp_lv: 2;
+        uint32_t EMAW_snps_lv: 2;
+        uint32_t EMAW_cpu_hv: 2;
+        uint32_t EMAW_usb_hv: 2;
+        uint32_t EMAW_can_hv: 2;
+        uint32_t EMAW_lebis_hv: 2;
+        uint32_t EMAW_audio_hv: 2;
+        uint32_t EMAW_btphy_hv: 2;
+        uint32_t EMAW_ccmp_hv: 2;
+        uint32_t EMAW_snps_hv: 2;
+    };
+} AON_REG_SRAM_CTRL25_TYPE;
+
+/*0x4000_088c AON_REG_SRAM_CTRL25*/
+#define AON_REG_SRAM_CTRL25_EMAW_cpu_lv_Pos                                                                              0U
+#define AON_REG_SRAM_CTRL25_EMAW_cpu_lv_Msk                                                                              (0x3UL << AON_REG_SRAM_CTRL25_EMAW_cpu_lv_Pos)
+
+#define AON_REG_SRAM_CTRL25_EMAW_usb_lv_Pos                                                                              2U
+#define AON_REG_SRAM_CTRL25_EMAW_usb_lv_Msk                                                                              (0x3UL << AON_REG_SRAM_CTRL25_EMAW_usb_lv_Pos)
+
+#define AON_REG_SRAM_CTRL25_EMAW_can_lv_Pos                                                                              4U
+#define AON_REG_SRAM_CTRL25_EMAW_can_lv_Msk                                                                              (0x3UL << AON_REG_SRAM_CTRL25_EMAW_can_lv_Pos)
+
+#define AON_REG_SRAM_CTRL25_EMAW_lebis_lv_Pos                                                                            6U
+#define AON_REG_SRAM_CTRL25_EMAW_lebis_lv_Msk                                                                            (0x3UL << AON_REG_SRAM_CTRL25_EMAW_lebis_lv_Pos)
+
+#define AON_REG_SRAM_CTRL25_EMAW_audio_lv_Pos                                                                            8U
+#define AON_REG_SRAM_CTRL25_EMAW_audio_lv_Msk                                                                            (0x3UL << AON_REG_SRAM_CTRL25_EMAW_audio_lv_Pos)
+
+#define AON_REG_SRAM_CTRL25_EMAW_btphy_lv_Pos                                                                            10U
+#define AON_REG_SRAM_CTRL25_EMAW_btphy_lv_Msk                                                                            (0x3UL << AON_REG_SRAM_CTRL25_EMAW_btphy_lv_Pos)
+
+#define AON_REG_SRAM_CTRL25_EMAW_ccmp_lv_Pos                                                                             12U
+#define AON_REG_SRAM_CTRL25_EMAW_ccmp_lv_Msk                                                                             (0x3UL << AON_REG_SRAM_CTRL25_EMAW_ccmp_lv_Pos)
+
+#define AON_REG_SRAM_CTRL25_EMAW_snps_lv_Pos                                                                             14U
+#define AON_REG_SRAM_CTRL25_EMAW_snps_lv_Msk                                                                             (0x3UL << AON_REG_SRAM_CTRL25_EMAW_snps_lv_Pos)
+
+#define AON_REG_SRAM_CTRL25_EMAW_cpu_hv_Pos                                                                              16U
+#define AON_REG_SRAM_CTRL25_EMAW_cpu_hv_Msk                                                                              (0x3UL << AON_REG_SRAM_CTRL25_EMAW_cpu_hv_Pos)
+
+#define AON_REG_SRAM_CTRL25_EMAW_usb_hv_Pos                                                                              18U
+#define AON_REG_SRAM_CTRL25_EMAW_usb_hv_Msk                                                                              (0x3UL << AON_REG_SRAM_CTRL25_EMAW_usb_hv_Pos)
+
+#define AON_REG_SRAM_CTRL25_EMAW_can_hv_Pos                                                                              20U
+#define AON_REG_SRAM_CTRL25_EMAW_can_hv_Msk                                                                              (0x3UL << AON_REG_SRAM_CTRL25_EMAW_can_hv_Pos)
+
+#define AON_REG_SRAM_CTRL25_EMAW_lebis_hv_Pos                                                                            22U
+#define AON_REG_SRAM_CTRL25_EMAW_lebis_hv_Msk                                                                            (0x3UL << AON_REG_SRAM_CTRL25_EMAW_lebis_hv_Pos)
+
+#define AON_REG_SRAM_CTRL25_EMAW_audio_hv_Pos                                                                            24U
+#define AON_REG_SRAM_CTRL25_EMAW_audio_hv_Msk                                                                            (0x3UL << AON_REG_SRAM_CTRL25_EMAW_audio_hv_Pos)
+
+#define AON_REG_SRAM_CTRL25_EMAW_btphy_hv_Pos                                                                            26U
+#define AON_REG_SRAM_CTRL25_EMAW_btphy_hv_Msk                                                                            (0x3UL << AON_REG_SRAM_CTRL25_EMAW_btphy_hv_Pos)
+
+#define AON_REG_SRAM_CTRL25_EMAW_ccmp_hv_Pos                                                                             28U
+#define AON_REG_SRAM_CTRL25_EMAW_ccmp_hv_Msk                                                                             (0x3UL << AON_REG_SRAM_CTRL25_EMAW_ccmp_hv_Pos)
+
+#define AON_REG_SRAM_CTRL25_EMAW_snps_hv_Pos                                                                             30U
+#define AON_REG_SRAM_CTRL25_EMAW_snps_hv_Msk                                                                             (0x3UL << AON_REG_SRAM_CTRL25_EMAW_snps_hv_Pos)
+
+/* 0x890    0x4000_0890
+    0       R/W     PGEN_cpu                                                    1'b0
+    1       R/W     PGEN_usb                                                    1'b0
+    2       R/W     PGEN_can                                                    1'b0
+    3       R/W     PGEN_lebis                                                  1'b0
+    4       R/W     PGEN_audio                                                  1'b0
+    5       R/W     PGEN_btphy                                                  1'b0
+    6       R/W     PGEN_ccmp                                                   1'b0
+    7       R/W     PGEN_snps                                                   1'b0
+    11:8    R       RSVD_1                                                      0
+    12      R/W     RET1N_cpu                                                   1'b1
+    13      R/W     RET1N_usb                                                   1'b1
+    14      R/W     RET1N_can                                                   1'b1
+    15      R/W     RET1N_lebis                                                 1'b1
+    16      R/W     RET1N_audio                                                 1'b1
+    17      R/W     RET1N_btphy                                                 1'b1
+    18      R/W     RET1N_ccmp                                                  1'b1
+    19      R/W     RET1N_snps                                                  1'b1
+    23:20   R       RSVD                                                        0
+    24      R/W     RET2N_cpu                                                   1'b1
+    25      R/W     RET2N_usb                                                   1'b1
+    26      R/W     RET2N_can                                                   1'b1
+    27      R/W     RET2N_lebis                                                 1'b1
+    28      R/W     RET2N_audio                                                 1'b1
+    29      R/W     RET2N_btphy                                                 1'b1
+    30      R/W     RET2N_ccmp                                                  1'b1
+    31      R/W     RET2N_snps                                                  1'b1
+ */
+typedef union _AON_REG_SRAM_CTRL27_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t PGEN_cpu: 1;
+        uint32_t PGEN_usb: 1;
+        uint32_t PGEN_can: 1;
+        uint32_t PGEN_lebis: 1;
+        uint32_t PGEN_audio: 1;
+        uint32_t PGEN_btphy: 1;
+        uint32_t PGEN_ccmp: 1;
+        uint32_t PGEN_snps: 1;
+        uint32_t RSVD_1: 4;
+        uint32_t RET1N_cpu: 1;
+        uint32_t RET1N_usb: 1;
+        uint32_t RET1N_can: 1;
+        uint32_t RET1N_lebis: 1;
+        uint32_t RET1N_audio: 1;
+        uint32_t RET1N_btphy: 1;
+        uint32_t RET1N_ccmp: 1;
+        uint32_t RET1N_snps: 1;
+        uint32_t RSVD: 4;
+        uint32_t RET2N_cpu: 1;
+        uint32_t RET2N_usb: 1;
+        uint32_t RET2N_can: 1;
+        uint32_t RET2N_lebis: 1;
+        uint32_t RET2N_audio: 1;
+        uint32_t RET2N_btphy: 1;
+        uint32_t RET2N_ccmp: 1;
+        uint32_t RET2N_snps: 1;
+    };
+} AON_REG_SRAM_CTRL27_TYPE;
+
+/*0x4000_0890 AON_REG_SRAM_CTRL27*/
+#define AON_REG_SRAM_CTRL27_PGEN_cpu_Pos                                                                                 0U
+#define AON_REG_SRAM_CTRL27_PGEN_cpu_Msk                                                                                 (0x1UL << AON_REG_SRAM_CTRL27_PGEN_cpu_Pos)
+
+#define AON_REG_SRAM_CTRL27_PGEN_usb_Pos                                                                                 1U
+#define AON_REG_SRAM_CTRL27_PGEN_usb_Msk                                                                                 (0x1UL << AON_REG_SRAM_CTRL27_PGEN_usb_Pos)
+
+#define AON_REG_SRAM_CTRL27_PGEN_can_Pos                                                                                 2U
+#define AON_REG_SRAM_CTRL27_PGEN_can_Msk                                                                                 (0x1UL << AON_REG_SRAM_CTRL27_PGEN_can_Pos)
+
+#define AON_REG_SRAM_CTRL27_PGEN_lebis_Pos                                                                               3U
+#define AON_REG_SRAM_CTRL27_PGEN_lebis_Msk                                                                               (0x1UL << AON_REG_SRAM_CTRL27_PGEN_lebis_Pos)
+
+#define AON_REG_SRAM_CTRL27_PGEN_audio_Pos                                                                               4U
+#define AON_REG_SRAM_CTRL27_PGEN_audio_Msk                                                                               (0x1UL << AON_REG_SRAM_CTRL27_PGEN_audio_Pos)
+
+#define AON_REG_SRAM_CTRL27_PGEN_btphy_Pos                                                                               5U
+#define AON_REG_SRAM_CTRL27_PGEN_btphy_Msk                                                                               (0x1UL << AON_REG_SRAM_CTRL27_PGEN_btphy_Pos)
+
+#define AON_REG_SRAM_CTRL27_PGEN_ccmp_Pos                                                                                6U
+#define AON_REG_SRAM_CTRL27_PGEN_ccmp_Msk                                                                                (0x1UL << AON_REG_SRAM_CTRL27_PGEN_ccmp_Pos)
+
+#define AON_REG_SRAM_CTRL27_PGEN_snps_Pos                                                                                7U
+#define AON_REG_SRAM_CTRL27_PGEN_snps_Msk                                                                                (0x1UL << AON_REG_SRAM_CTRL27_PGEN_snps_Pos)
+
+#define AON_REG_SRAM_CTRL27_RSVD_1_Pos                                                                                   8U
+#define AON_REG_SRAM_CTRL27_RSVD_1_Msk                                                                                   (0xFUL << AON_REG_SRAM_CTRL27_RSVD_1_Pos)
+
+#define AON_REG_SRAM_CTRL27_RET1N_cpu_Pos                                                                                12U
+#define AON_REG_SRAM_CTRL27_RET1N_cpu_Msk                                                                                (0x1UL << AON_REG_SRAM_CTRL27_RET1N_cpu_Pos)
+
+#define AON_REG_SRAM_CTRL27_RET1N_usb_Pos                                                                                13U
+#define AON_REG_SRAM_CTRL27_RET1N_usb_Msk                                                                                (0x1UL << AON_REG_SRAM_CTRL27_RET1N_usb_Pos)
+
+#define AON_REG_SRAM_CTRL27_RET1N_can_Pos                                                                                14U
+#define AON_REG_SRAM_CTRL27_RET1N_can_Msk                                                                                (0x1UL << AON_REG_SRAM_CTRL27_RET1N_can_Pos)
+
+#define AON_REG_SRAM_CTRL27_RET1N_lebis_Pos                                                                              15U
+#define AON_REG_SRAM_CTRL27_RET1N_lebis_Msk                                                                              (0x1UL << AON_REG_SRAM_CTRL27_RET1N_lebis_Pos)
+
+#define AON_REG_SRAM_CTRL27_RET1N_audio_Pos                                                                              16U
+#define AON_REG_SRAM_CTRL27_RET1N_audio_Msk                                                                              (0x1UL << AON_REG_SRAM_CTRL27_RET1N_audio_Pos)
+
+#define AON_REG_SRAM_CTRL27_RET1N_btphy_Pos                                                                              17U
+#define AON_REG_SRAM_CTRL27_RET1N_btphy_Msk                                                                              (0x1UL << AON_REG_SRAM_CTRL27_RET1N_btphy_Pos)
+
+#define AON_REG_SRAM_CTRL27_RET1N_ccmp_Pos                                                                               18U
+#define AON_REG_SRAM_CTRL27_RET1N_ccmp_Msk                                                                               (0x1UL << AON_REG_SRAM_CTRL27_RET1N_ccmp_Pos)
+
+#define AON_REG_SRAM_CTRL27_RET1N_snps_Pos                                                                               19U
+#define AON_REG_SRAM_CTRL27_RET1N_snps_Msk                                                                               (0x1UL << AON_REG_SRAM_CTRL27_RET1N_snps_Pos)
+
+#define AON_REG_SRAM_CTRL27_RSVD_Pos                                                                                     20U
+#define AON_REG_SRAM_CTRL27_RSVD_Msk                                                                                     (0xFUL << AON_REG_SRAM_CTRL27_RSVD_Pos)
+
+#define AON_REG_SRAM_CTRL27_RET2N_cpu_Pos                                                                                24U
+#define AON_REG_SRAM_CTRL27_RET2N_cpu_Msk                                                                                (0x1UL << AON_REG_SRAM_CTRL27_RET2N_cpu_Pos)
+
+#define AON_REG_SRAM_CTRL27_RET2N_usb_Pos                                                                                25U
+#define AON_REG_SRAM_CTRL27_RET2N_usb_Msk                                                                                (0x1UL << AON_REG_SRAM_CTRL27_RET2N_usb_Pos)
+
+#define AON_REG_SRAM_CTRL27_RET2N_can_Pos                                                                                26U
+#define AON_REG_SRAM_CTRL27_RET2N_can_Msk                                                                                (0x1UL << AON_REG_SRAM_CTRL27_RET2N_can_Pos)
+
+#define AON_REG_SRAM_CTRL27_RET2N_lebis_Pos                                                                              27U
+#define AON_REG_SRAM_CTRL27_RET2N_lebis_Msk                                                                              (0x1UL << AON_REG_SRAM_CTRL27_RET2N_lebis_Pos)
+
+#define AON_REG_SRAM_CTRL27_RET2N_audio_Pos                                                                              28U
+#define AON_REG_SRAM_CTRL27_RET2N_audio_Msk                                                                              (0x1UL << AON_REG_SRAM_CTRL27_RET2N_audio_Pos)
+
+#define AON_REG_SRAM_CTRL27_RET2N_btphy_Pos                                                                              29U
+#define AON_REG_SRAM_CTRL27_RET2N_btphy_Msk                                                                              (0x1UL << AON_REG_SRAM_CTRL27_RET2N_btphy_Pos)
+
+#define AON_REG_SRAM_CTRL27_RET2N_ccmp_Pos                                                                               30U
+#define AON_REG_SRAM_CTRL27_RET2N_ccmp_Msk                                                                               (0x1UL << AON_REG_SRAM_CTRL27_RET2N_ccmp_Pos)
+
+#define AON_REG_SRAM_CTRL27_RET2N_snps_Pos                                                                               31U
+#define AON_REG_SRAM_CTRL27_RET2N_snps_Msk                                                                               (0x1UL << AON_REG_SRAM_CTRL27_RET2N_snps_Pos)
+
+/* 0x894    0x4000_0894
+    0       R/W     RAWL_cpu_lv                                                 1'b0
+    1       R/W     RAWL_usb_lv                                                 1'b0
+    2       R/W     RAWL_can_lv                                                 1'b0
+    3       R/W     RAWL_lebis_lv                                               1'b0
+    4       R/W     RAWL_audio_lv                                               1'b0
+    5       R/W     RAWL_btphy_lv                                               1'b0
+    6       R/W     RAWL_ccmp_lv                                                1'b0
+    7       R/W     RAWL_snps_lv                                                1'b0
+    15:8    R       RSVD_1                                                      0
+    16      R/W     RAWL_cpu_hv                                                 1'b0
+    17      R/W     RAWL_usb_hv                                                 1'b0
+    18      R/W     RAWL_can_hv                                                 1'b0
+    19      R/W     RAWL_lebis_hv                                               1'b0
+    20      R/W     RAWL_audio_hv                                               1'b0
+    21      R/W     RAWL_btphy_hv                                               1'b0
+    22      R/W     RAWL_ccmp_hv                                                1'b0
+    23      R/W     RAWL_snps_hv                                                1'b0
+    31:24   R       RSVD                                                        0
+ */
+typedef union _AON_REG_SRAM_CTRL28_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RAWL_cpu_lv: 1;
+        uint32_t RAWL_usb_lv: 1;
+        uint32_t RAWL_can_lv: 1;
+        uint32_t RAWL_lebis_lv: 1;
+        uint32_t RAWL_audio_lv: 1;
+        uint32_t RAWL_btphy_lv: 1;
+        uint32_t RAWL_ccmp_lv: 1;
+        uint32_t RAWL_snps_lv: 1;
+        uint32_t RSVD_1: 8;
+        uint32_t RAWL_cpu_hv: 1;
+        uint32_t RAWL_usb_hv: 1;
+        uint32_t RAWL_can_hv: 1;
+        uint32_t RAWL_lebis_hv: 1;
+        uint32_t RAWL_audio_hv: 1;
+        uint32_t RAWL_btphy_hv: 1;
+        uint32_t RAWL_ccmp_hv: 1;
+        uint32_t RAWL_snps_hv: 1;
+        uint32_t RSVD: 8;
+    };
+} AON_REG_SRAM_CTRL28_TYPE;
+
+/*0x4000_0894 AON_REG_SRAM_CTRL28*/
+#define AON_REG_SRAM_CTRL28_RAWL_cpu_lv_Pos                                                                              0U
+#define AON_REG_SRAM_CTRL28_RAWL_cpu_lv_Msk                                                                              (0x1UL << AON_REG_SRAM_CTRL28_RAWL_cpu_lv_Pos)
+
+#define AON_REG_SRAM_CTRL28_RAWL_usb_lv_Pos                                                                              1U
+#define AON_REG_SRAM_CTRL28_RAWL_usb_lv_Msk                                                                              (0x1UL << AON_REG_SRAM_CTRL28_RAWL_usb_lv_Pos)
+
+#define AON_REG_SRAM_CTRL28_RAWL_can_lv_Pos                                                                              2U
+#define AON_REG_SRAM_CTRL28_RAWL_can_lv_Msk                                                                              (0x1UL << AON_REG_SRAM_CTRL28_RAWL_can_lv_Pos)
+
+#define AON_REG_SRAM_CTRL28_RAWL_lebis_lv_Pos                                                                            3U
+#define AON_REG_SRAM_CTRL28_RAWL_lebis_lv_Msk                                                                            (0x1UL << AON_REG_SRAM_CTRL28_RAWL_lebis_lv_Pos)
+
+#define AON_REG_SRAM_CTRL28_RAWL_audio_lv_Pos                                                                            4U
+#define AON_REG_SRAM_CTRL28_RAWL_audio_lv_Msk                                                                            (0x1UL << AON_REG_SRAM_CTRL28_RAWL_audio_lv_Pos)
+
+#define AON_REG_SRAM_CTRL28_RAWL_btphy_lv_Pos                                                                            5U
+#define AON_REG_SRAM_CTRL28_RAWL_btphy_lv_Msk                                                                            (0x1UL << AON_REG_SRAM_CTRL28_RAWL_btphy_lv_Pos)
+
+#define AON_REG_SRAM_CTRL28_RAWL_ccmp_lv_Pos                                                                             6U
+#define AON_REG_SRAM_CTRL28_RAWL_ccmp_lv_Msk                                                                             (0x1UL << AON_REG_SRAM_CTRL28_RAWL_ccmp_lv_Pos)
+
+#define AON_REG_SRAM_CTRL28_RAWL_snps_lv_Pos                                                                             7U
+#define AON_REG_SRAM_CTRL28_RAWL_snps_lv_Msk                                                                             (0x1UL << AON_REG_SRAM_CTRL28_RAWL_snps_lv_Pos)
+
+#define AON_REG_SRAM_CTRL28_RSVD_1_Pos                                                                                   8U
+#define AON_REG_SRAM_CTRL28_RSVD_1_Msk                                                                                   (0xFFUL << AON_REG_SRAM_CTRL28_RSVD_1_Pos)
+
+#define AON_REG_SRAM_CTRL28_RAWL_cpu_hv_Pos                                                                              16U
+#define AON_REG_SRAM_CTRL28_RAWL_cpu_hv_Msk                                                                              (0x1UL << AON_REG_SRAM_CTRL28_RAWL_cpu_hv_Pos)
+
+#define AON_REG_SRAM_CTRL28_RAWL_usb_hv_Pos                                                                              17U
+#define AON_REG_SRAM_CTRL28_RAWL_usb_hv_Msk                                                                              (0x1UL << AON_REG_SRAM_CTRL28_RAWL_usb_hv_Pos)
+
+#define AON_REG_SRAM_CTRL28_RAWL_can_hv_Pos                                                                              18U
+#define AON_REG_SRAM_CTRL28_RAWL_can_hv_Msk                                                                              (0x1UL << AON_REG_SRAM_CTRL28_RAWL_can_hv_Pos)
+
+#define AON_REG_SRAM_CTRL28_RAWL_lebis_hv_Pos                                                                            19U
+#define AON_REG_SRAM_CTRL28_RAWL_lebis_hv_Msk                                                                            (0x1UL << AON_REG_SRAM_CTRL28_RAWL_lebis_hv_Pos)
+
+#define AON_REG_SRAM_CTRL28_RAWL_audio_hv_Pos                                                                            20U
+#define AON_REG_SRAM_CTRL28_RAWL_audio_hv_Msk                                                                            (0x1UL << AON_REG_SRAM_CTRL28_RAWL_audio_hv_Pos)
+
+#define AON_REG_SRAM_CTRL28_RAWL_btphy_hv_Pos                                                                            21U
+#define AON_REG_SRAM_CTRL28_RAWL_btphy_hv_Msk                                                                            (0x1UL << AON_REG_SRAM_CTRL28_RAWL_btphy_hv_Pos)
+
+#define AON_REG_SRAM_CTRL28_RAWL_ccmp_hv_Pos                                                                             22U
+#define AON_REG_SRAM_CTRL28_RAWL_ccmp_hv_Msk                                                                             (0x1UL << AON_REG_SRAM_CTRL28_RAWL_ccmp_hv_Pos)
+
+#define AON_REG_SRAM_CTRL28_RAWL_snps_hv_Pos                                                                             23U
+#define AON_REG_SRAM_CTRL28_RAWL_snps_hv_Msk                                                                             (0x1UL << AON_REG_SRAM_CTRL28_RAWL_snps_hv_Pos)
+
+#define AON_REG_SRAM_CTRL28_RSVD_Pos                                                                                     24U
+#define AON_REG_SRAM_CTRL28_RSVD_Msk                                                                                     (0xFFUL << AON_REG_SRAM_CTRL28_RSVD_Pos)
+
+/* 0x898    0x4000_0898
+    1:0     R/W     RAWLM_cpu_lv                                                2'b0
+    3:2     R/W     RAWLM_usb_lv                                                2'b0
+    5:4     R/W     RAWLM_can_lv                                                2'b0
+    7:6     R/W     RAWLM_lebis_lv                                              2'b0
+    9:8     R/W     RAWLM_audio_lv                                              2'b0
+    11:10   R/W     RAWLM_btphy_lv                                              2'b0
+    13:12   R/W     RAWLM_ccmp_lv                                               2'b0
+    15:14   R/W     RAWLM_snps_lv                                               2'b0
+    17:16   R/W     RAWLM_cpu_hv                                                2'b0
+    19:18   R/W     RAWLM_usb_hv                                                2'b0
+    21:20   R/W     RAWLM_can_hv                                                2'b0
+    23:22   R/W     RAWLM_lebis_hv                                              2'b0
+    25:24   R/W     RAWLM_audio_hv                                              2'b0
+    27:26   R/W     RAWLM_btphy_hv                                              2'b0
+    29:28   R/W     RAWLM_ccmp_hv                                               2'b0
+    31:30   R/W     RAWLM_snps_hv                                               2'b0
+ */
+typedef union _AON_REG_SRAM_CTRL29_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RAWLM_cpu_lv: 2;
+        uint32_t RAWLM_usb_lv: 2;
+        uint32_t RAWLM_can_lv: 2;
+        uint32_t RAWLM_lebis_lv: 2;
+        uint32_t RAWLM_audio_lv: 2;
+        uint32_t RAWLM_btphy_lv: 2;
+        uint32_t RAWLM_ccmp_lv: 2;
+        uint32_t RAWLM_snps_lv: 2;
+        uint32_t RAWLM_cpu_hv: 2;
+        uint32_t RAWLM_usb_hv: 2;
+        uint32_t RAWLM_can_hv: 2;
+        uint32_t RAWLM_lebis_hv: 2;
+        uint32_t RAWLM_audio_hv: 2;
+        uint32_t RAWLM_btphy_hv: 2;
+        uint32_t RAWLM_ccmp_hv: 2;
+        uint32_t RAWLM_snps_hv: 2;
+    };
+} AON_REG_SRAM_CTRL29_TYPE;
+
+/*0x4000_0898 AON_REG_SRAM_CTRL29*/
+#define AON_REG_SRAM_CTRL29_RAWLM_cpu_lv_Pos                                                                             0U
+#define AON_REG_SRAM_CTRL29_RAWLM_cpu_lv_Msk                                                                             (0x3UL << AON_REG_SRAM_CTRL29_RAWLM_cpu_lv_Pos)
+
+#define AON_REG_SRAM_CTRL29_RAWLM_usb_lv_Pos                                                                             2U
+#define AON_REG_SRAM_CTRL29_RAWLM_usb_lv_Msk                                                                             (0x3UL << AON_REG_SRAM_CTRL29_RAWLM_usb_lv_Pos)
+
+#define AON_REG_SRAM_CTRL29_RAWLM_can_lv_Pos                                                                             4U
+#define AON_REG_SRAM_CTRL29_RAWLM_can_lv_Msk                                                                             (0x3UL << AON_REG_SRAM_CTRL29_RAWLM_can_lv_Pos)
+
+#define AON_REG_SRAM_CTRL29_RAWLM_lebis_lv_Pos                                                                           6U
+#define AON_REG_SRAM_CTRL29_RAWLM_lebis_lv_Msk                                                                           (0x3UL << AON_REG_SRAM_CTRL29_RAWLM_lebis_lv_Pos)
+
+#define AON_REG_SRAM_CTRL29_RAWLM_audio_lv_Pos                                                                           8U
+#define AON_REG_SRAM_CTRL29_RAWLM_audio_lv_Msk                                                                           (0x3UL << AON_REG_SRAM_CTRL29_RAWLM_audio_lv_Pos)
+
+#define AON_REG_SRAM_CTRL29_RAWLM_btphy_lv_Pos                                                                           10U
+#define AON_REG_SRAM_CTRL29_RAWLM_btphy_lv_Msk                                                                           (0x3UL << AON_REG_SRAM_CTRL29_RAWLM_btphy_lv_Pos)
+
+#define AON_REG_SRAM_CTRL29_RAWLM_ccmp_lv_Pos                                                                            12U
+#define AON_REG_SRAM_CTRL29_RAWLM_ccmp_lv_Msk                                                                            (0x3UL << AON_REG_SRAM_CTRL29_RAWLM_ccmp_lv_Pos)
+
+#define AON_REG_SRAM_CTRL29_RAWLM_snps_lv_Pos                                                                            14U
+#define AON_REG_SRAM_CTRL29_RAWLM_snps_lv_Msk                                                                            (0x3UL << AON_REG_SRAM_CTRL29_RAWLM_snps_lv_Pos)
+
+#define AON_REG_SRAM_CTRL29_RAWLM_cpu_hv_Pos                                                                             16U
+#define AON_REG_SRAM_CTRL29_RAWLM_cpu_hv_Msk                                                                             (0x3UL << AON_REG_SRAM_CTRL29_RAWLM_cpu_hv_Pos)
+
+#define AON_REG_SRAM_CTRL29_RAWLM_usb_hv_Pos                                                                             18U
+#define AON_REG_SRAM_CTRL29_RAWLM_usb_hv_Msk                                                                             (0x3UL << AON_REG_SRAM_CTRL29_RAWLM_usb_hv_Pos)
+
+#define AON_REG_SRAM_CTRL29_RAWLM_can_hv_Pos                                                                             20U
+#define AON_REG_SRAM_CTRL29_RAWLM_can_hv_Msk                                                                             (0x3UL << AON_REG_SRAM_CTRL29_RAWLM_can_hv_Pos)
+
+#define AON_REG_SRAM_CTRL29_RAWLM_lebis_hv_Pos                                                                           22U
+#define AON_REG_SRAM_CTRL29_RAWLM_lebis_hv_Msk                                                                           (0x3UL << AON_REG_SRAM_CTRL29_RAWLM_lebis_hv_Pos)
+
+#define AON_REG_SRAM_CTRL29_RAWLM_audio_hv_Pos                                                                           24U
+#define AON_REG_SRAM_CTRL29_RAWLM_audio_hv_Msk                                                                           (0x3UL << AON_REG_SRAM_CTRL29_RAWLM_audio_hv_Pos)
+
+#define AON_REG_SRAM_CTRL29_RAWLM_btphy_hv_Pos                                                                           26U
+#define AON_REG_SRAM_CTRL29_RAWLM_btphy_hv_Msk                                                                           (0x3UL << AON_REG_SRAM_CTRL29_RAWLM_btphy_hv_Pos)
+
+#define AON_REG_SRAM_CTRL29_RAWLM_ccmp_hv_Pos                                                                            28U
+#define AON_REG_SRAM_CTRL29_RAWLM_ccmp_hv_Msk                                                                            (0x3UL << AON_REG_SRAM_CTRL29_RAWLM_ccmp_hv_Pos)
+
+#define AON_REG_SRAM_CTRL29_RAWLM_snps_hv_Pos                                                                            30U
+#define AON_REG_SRAM_CTRL29_RAWLM_snps_hv_Msk                                                                            (0x3UL << AON_REG_SRAM_CTRL29_RAWLM_snps_hv_Pos)
+
+/* 0x89C    0x4000_089c
+    0       R/W     WABL_cpu_lv                                                 1'b1
+    1       R/W     WABL_usb_lv                                                 1'b1
+    2       R/W     WABL_can_lv                                                 1'b1
+    3       R/W     WABL_lebis_lv                                               1'b1
+    4       R/W     WABL_audio_lv                                               1'b1
+    5       R/W     WABL_btphy_lv                                               1'b1
+    6       R/W     WABL_ccmp_lv                                                1'b1
+    7       R/W     WABL_snps_lv                                                1'b1
+    15:8    R       RSVD_1                                                      0
+    16      R/W     WABL_cpu_hv                                                 1'b1
+    17      R/W     WABL_usb_hv                                                 1'b1
+    18      R/W     WABL_can_hv                                                 1'b1
+    19      R/W     WABL_lebis_hv                                               1'b1
+    20      R/W     WABL_audio_hv                                               1'b1
+    21      R/W     WABL_btphy_hv                                               1'b1
+    22      R/W     WABL_ccmp_hv                                                1'b1
+    23      R/W     WABL_snps_hv                                                1'b1
+    31:24   R       RSVD                                                        0
+ */
+typedef union _AON_REG_SRAM_CTRL30_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t WABL_cpu_lv: 1;
+        uint32_t WABL_usb_lv: 1;
+        uint32_t WABL_can_lv: 1;
+        uint32_t WABL_lebis_lv: 1;
+        uint32_t WABL_audio_lv: 1;
+        uint32_t WABL_btphy_lv: 1;
+        uint32_t WABL_ccmp_lv: 1;
+        uint32_t WABL_snps_lv: 1;
+        uint32_t RSVD_1: 8;
+        uint32_t WABL_cpu_hv: 1;
+        uint32_t WABL_usb_hv: 1;
+        uint32_t WABL_can_hv: 1;
+        uint32_t WABL_lebis_hv: 1;
+        uint32_t WABL_audio_hv: 1;
+        uint32_t WABL_btphy_hv: 1;
+        uint32_t WABL_ccmp_hv: 1;
+        uint32_t WABL_snps_hv: 1;
+        uint32_t RSVD: 8;
+    };
+} AON_REG_SRAM_CTRL30_TYPE;
+
+/*0x4000_089c AON_REG_SRAM_CTRL30*/
+#define AON_REG_SRAM_CTRL30_WABL_cpu_lv_Pos                                                                              0U
+#define AON_REG_SRAM_CTRL30_WABL_cpu_lv_Msk                                                                              (0x1UL << AON_REG_SRAM_CTRL30_WABL_cpu_lv_Pos)
+
+#define AON_REG_SRAM_CTRL30_WABL_usb_lv_Pos                                                                              1U
+#define AON_REG_SRAM_CTRL30_WABL_usb_lv_Msk                                                                              (0x1UL << AON_REG_SRAM_CTRL30_WABL_usb_lv_Pos)
+
+#define AON_REG_SRAM_CTRL30_WABL_can_lv_Pos                                                                              2U
+#define AON_REG_SRAM_CTRL30_WABL_can_lv_Msk                                                                              (0x1UL << AON_REG_SRAM_CTRL30_WABL_can_lv_Pos)
+
+#define AON_REG_SRAM_CTRL30_WABL_lebis_lv_Pos                                                                            3U
+#define AON_REG_SRAM_CTRL30_WABL_lebis_lv_Msk                                                                            (0x1UL << AON_REG_SRAM_CTRL30_WABL_lebis_lv_Pos)
+
+#define AON_REG_SRAM_CTRL30_WABL_audio_lv_Pos                                                                            4U
+#define AON_REG_SRAM_CTRL30_WABL_audio_lv_Msk                                                                            (0x1UL << AON_REG_SRAM_CTRL30_WABL_audio_lv_Pos)
+
+#define AON_REG_SRAM_CTRL30_WABL_btphy_lv_Pos                                                                            5U
+#define AON_REG_SRAM_CTRL30_WABL_btphy_lv_Msk                                                                            (0x1UL << AON_REG_SRAM_CTRL30_WABL_btphy_lv_Pos)
+
+#define AON_REG_SRAM_CTRL30_WABL_ccmp_lv_Pos                                                                             6U
+#define AON_REG_SRAM_CTRL30_WABL_ccmp_lv_Msk                                                                             (0x1UL << AON_REG_SRAM_CTRL30_WABL_ccmp_lv_Pos)
+
+#define AON_REG_SRAM_CTRL30_WABL_snps_lv_Pos                                                                             7U
+#define AON_REG_SRAM_CTRL30_WABL_snps_lv_Msk                                                                             (0x1UL << AON_REG_SRAM_CTRL30_WABL_snps_lv_Pos)
+
+#define AON_REG_SRAM_CTRL30_RSVD_1_Pos                                                                                   8U
+#define AON_REG_SRAM_CTRL30_RSVD_1_Msk                                                                                   (0xFFUL << AON_REG_SRAM_CTRL30_RSVD_1_Pos)
+
+#define AON_REG_SRAM_CTRL30_WABL_cpu_hv_Pos                                                                              16U
+#define AON_REG_SRAM_CTRL30_WABL_cpu_hv_Msk                                                                              (0x1UL << AON_REG_SRAM_CTRL30_WABL_cpu_hv_Pos)
+
+#define AON_REG_SRAM_CTRL30_WABL_usb_hv_Pos                                                                              17U
+#define AON_REG_SRAM_CTRL30_WABL_usb_hv_Msk                                                                              (0x1UL << AON_REG_SRAM_CTRL30_WABL_usb_hv_Pos)
+
+#define AON_REG_SRAM_CTRL30_WABL_can_hv_Pos                                                                              18U
+#define AON_REG_SRAM_CTRL30_WABL_can_hv_Msk                                                                              (0x1UL << AON_REG_SRAM_CTRL30_WABL_can_hv_Pos)
+
+#define AON_REG_SRAM_CTRL30_WABL_lebis_hv_Pos                                                                            19U
+#define AON_REG_SRAM_CTRL30_WABL_lebis_hv_Msk                                                                            (0x1UL << AON_REG_SRAM_CTRL30_WABL_lebis_hv_Pos)
+
+#define AON_REG_SRAM_CTRL30_WABL_audio_hv_Pos                                                                            20U
+#define AON_REG_SRAM_CTRL30_WABL_audio_hv_Msk                                                                            (0x1UL << AON_REG_SRAM_CTRL30_WABL_audio_hv_Pos)
+
+#define AON_REG_SRAM_CTRL30_WABL_btphy_hv_Pos                                                                            21U
+#define AON_REG_SRAM_CTRL30_WABL_btphy_hv_Msk                                                                            (0x1UL << AON_REG_SRAM_CTRL30_WABL_btphy_hv_Pos)
+
+#define AON_REG_SRAM_CTRL30_WABL_ccmp_hv_Pos                                                                             22U
+#define AON_REG_SRAM_CTRL30_WABL_ccmp_hv_Msk                                                                             (0x1UL << AON_REG_SRAM_CTRL30_WABL_ccmp_hv_Pos)
+
+#define AON_REG_SRAM_CTRL30_WABL_snps_hv_Pos                                                                             23U
+#define AON_REG_SRAM_CTRL30_WABL_snps_hv_Msk                                                                             (0x1UL << AON_REG_SRAM_CTRL30_WABL_snps_hv_Pos)
+
+#define AON_REG_SRAM_CTRL30_RSVD_Pos                                                                                     24U
+#define AON_REG_SRAM_CTRL30_RSVD_Msk                                                                                     (0xFFUL << AON_REG_SRAM_CTRL30_RSVD_Pos)
+
+/* 0x8A0    0x4000_08a0
+    1:0     R/W     WABLM_cpu_lv                                                2'b0
+    3:2     R/W     WABLM_usb_lv                                                2'b0
+    5:4     R/W     WABLM_can_lv                                                2'b0
+    7:6     R/W     WABLM_lebis_lv                                              2'b0
+    9:8     R/W     WABLM_audio_lv                                              2'b0
+    11:10   R/W     WABLM_btphy_lv                                              2'b0
+    13:12   R/W     WABLM_ccmp_lv                                               2'b0
+    15:14   R/W     WABLM_snps_lv                                               2'b0
+    17:16   R/W     WABLM_cpu_hv                                                2'b0
+    19:18   R/W     WABLM_usb_hv                                                2'b0
+    21:20   R/W     WABLM_can_hv                                                2'b0
+    23:22   R/W     WABLM_lebis_hv                                              2'b0
+    25:24   R/W     WABLM_audio_hv                                              2'b0
+    27:26   R/W     WABLM_btphy_hv                                              2'b0
+    29:28   R/W     WABLM_ccmp_hv                                               2'b0
+    31:30   R/W     WABLM_snps_hv                                               2'b0
+ */
+typedef union _AON_REG_SRAM_CTRL31_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t WABLM_cpu_lv: 2;
+        uint32_t WABLM_usb_lv: 2;
+        uint32_t WABLM_can_lv: 2;
+        uint32_t WABLM_lebis_lv: 2;
+        uint32_t WABLM_audio_lv: 2;
+        uint32_t WABLM_btphy_lv: 2;
+        uint32_t WABLM_ccmp_lv: 2;
+        uint32_t WABLM_snps_lv: 2;
+        uint32_t WABLM_cpu_hv: 2;
+        uint32_t WABLM_usb_hv: 2;
+        uint32_t WABLM_can_hv: 2;
+        uint32_t WABLM_lebis_hv: 2;
+        uint32_t WABLM_audio_hv: 2;
+        uint32_t WABLM_btphy_hv: 2;
+        uint32_t WABLM_ccmp_hv: 2;
+        uint32_t WABLM_snps_hv: 2;
+    };
+} AON_REG_SRAM_CTRL31_TYPE;
+
+/*0x4000_08a0 AON_REG_SRAM_CTRL31*/
+#define AON_REG_SRAM_CTRL31_WABLM_cpu_lv_Pos                                                                             0U
+#define AON_REG_SRAM_CTRL31_WABLM_cpu_lv_Msk                                                                             (0x3UL << AON_REG_SRAM_CTRL31_WABLM_cpu_lv_Pos)
+
+#define AON_REG_SRAM_CTRL31_WABLM_usb_lv_Pos                                                                             2U
+#define AON_REG_SRAM_CTRL31_WABLM_usb_lv_Msk                                                                             (0x3UL << AON_REG_SRAM_CTRL31_WABLM_usb_lv_Pos)
+
+#define AON_REG_SRAM_CTRL31_WABLM_can_lv_Pos                                                                             4U
+#define AON_REG_SRAM_CTRL31_WABLM_can_lv_Msk                                                                             (0x3UL << AON_REG_SRAM_CTRL31_WABLM_can_lv_Pos)
+
+#define AON_REG_SRAM_CTRL31_WABLM_lebis_lv_Pos                                                                           6U
+#define AON_REG_SRAM_CTRL31_WABLM_lebis_lv_Msk                                                                           (0x3UL << AON_REG_SRAM_CTRL31_WABLM_lebis_lv_Pos)
+
+#define AON_REG_SRAM_CTRL31_WABLM_audio_lv_Pos                                                                           8U
+#define AON_REG_SRAM_CTRL31_WABLM_audio_lv_Msk                                                                           (0x3UL << AON_REG_SRAM_CTRL31_WABLM_audio_lv_Pos)
+
+#define AON_REG_SRAM_CTRL31_WABLM_btphy_lv_Pos                                                                           10U
+#define AON_REG_SRAM_CTRL31_WABLM_btphy_lv_Msk                                                                           (0x3UL << AON_REG_SRAM_CTRL31_WABLM_btphy_lv_Pos)
+
+#define AON_REG_SRAM_CTRL31_WABLM_ccmp_lv_Pos                                                                            12U
+#define AON_REG_SRAM_CTRL31_WABLM_ccmp_lv_Msk                                                                            (0x3UL << AON_REG_SRAM_CTRL31_WABLM_ccmp_lv_Pos)
+
+#define AON_REG_SRAM_CTRL31_WABLM_snps_lv_Pos                                                                            14U
+#define AON_REG_SRAM_CTRL31_WABLM_snps_lv_Msk                                                                            (0x3UL << AON_REG_SRAM_CTRL31_WABLM_snps_lv_Pos)
+
+#define AON_REG_SRAM_CTRL31_WABLM_cpu_hv_Pos                                                                             16U
+#define AON_REG_SRAM_CTRL31_WABLM_cpu_hv_Msk                                                                             (0x3UL << AON_REG_SRAM_CTRL31_WABLM_cpu_hv_Pos)
+
+#define AON_REG_SRAM_CTRL31_WABLM_usb_hv_Pos                                                                             18U
+#define AON_REG_SRAM_CTRL31_WABLM_usb_hv_Msk                                                                             (0x3UL << AON_REG_SRAM_CTRL31_WABLM_usb_hv_Pos)
+
+#define AON_REG_SRAM_CTRL31_WABLM_can_hv_Pos                                                                             20U
+#define AON_REG_SRAM_CTRL31_WABLM_can_hv_Msk                                                                             (0x3UL << AON_REG_SRAM_CTRL31_WABLM_can_hv_Pos)
+
+#define AON_REG_SRAM_CTRL31_WABLM_lebis_hv_Pos                                                                           22U
+#define AON_REG_SRAM_CTRL31_WABLM_lebis_hv_Msk                                                                           (0x3UL << AON_REG_SRAM_CTRL31_WABLM_lebis_hv_Pos)
+
+#define AON_REG_SRAM_CTRL31_WABLM_audio_hv_Pos                                                                           24U
+#define AON_REG_SRAM_CTRL31_WABLM_audio_hv_Msk                                                                           (0x3UL << AON_REG_SRAM_CTRL31_WABLM_audio_hv_Pos)
+
+#define AON_REG_SRAM_CTRL31_WABLM_btphy_hv_Pos                                                                           26U
+#define AON_REG_SRAM_CTRL31_WABLM_btphy_hv_Msk                                                                           (0x3UL << AON_REG_SRAM_CTRL31_WABLM_btphy_hv_Pos)
+
+#define AON_REG_SRAM_CTRL31_WABLM_ccmp_hv_Pos                                                                            28U
+#define AON_REG_SRAM_CTRL31_WABLM_ccmp_hv_Msk                                                                            (0x3UL << AON_REG_SRAM_CTRL31_WABLM_ccmp_hv_Pos)
+
+#define AON_REG_SRAM_CTRL31_WABLM_snps_hv_Pos                                                                            30U
+#define AON_REG_SRAM_CTRL31_WABLM_snps_hv_Msk                                                                            (0x3UL << AON_REG_SRAM_CTRL31_WABLM_snps_hv_Pos)
+
+/* 0x8A4    0x4000_08a4
+    0       R/W     RSVD_11                                                     1'b0
+    1       R/W     RSVD_10                                                     1'b0
+    2       R/W     RSVD_9                                                      1'b0
+    3       R/W     RSVD_8                                                      1'b0
+    4       R/W     RSVD_7                                                      1'b0
+    5       R/W     RSVD_6                                                      1'b0
+    6       R/W     RSVD_5                                                      1'b0
+    7       R/W     RSVD_4                                                      1'b0
+    8       R/W     RSVD_3                                                      1'b0
+    9       R/W     RSVD_2                                                      1'b0
+    10      R/W     RSVD_1                                                      1'b0
+    31:11   R       RSVD                                                        21'h0
+ */
+typedef union _AON_REG_SRAM_CTRL32_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RSVD_11: 1;
+        uint32_t RSVD_10: 1;
+        uint32_t RSVD_9: 1;
+        uint32_t RSVD_8: 1;
+        uint32_t RSVD_7: 1;
+        uint32_t RSVD_6: 1;
+        uint32_t RSVD_5: 1;
+        uint32_t RSVD_4: 1;
+        uint32_t RSVD_3: 1;
+        uint32_t RSVD_2: 1;
+        uint32_t RSVD_1: 1;
+        uint32_t RSVD: 21;
+    };
+} AON_REG_SRAM_CTRL32_TYPE;
+
+/*0x4000_08a4 AON_REG_SRAM_CTRL32*/
+#define AON_REG_SRAM_CTRL32_RSVD_11_Pos                                                                                  0U
+#define AON_REG_SRAM_CTRL32_RSVD_11_Msk                                                                                  (0x1UL << AON_REG_SRAM_CTRL32_RSVD_11_Pos)
+
+#define AON_REG_SRAM_CTRL32_RSVD_10_Pos                                                                                  1U
+#define AON_REG_SRAM_CTRL32_RSVD_10_Msk                                                                                  (0x1UL << AON_REG_SRAM_CTRL32_RSVD_10_Pos)
+
+#define AON_REG_SRAM_CTRL32_RSVD_9_Pos                                                                                   2U
+#define AON_REG_SRAM_CTRL32_RSVD_9_Msk                                                                                   (0x1UL << AON_REG_SRAM_CTRL32_RSVD_9_Pos)
+
+#define AON_REG_SRAM_CTRL32_RSVD_8_Pos                                                                                   3U
+#define AON_REG_SRAM_CTRL32_RSVD_8_Msk                                                                                   (0x1UL << AON_REG_SRAM_CTRL32_RSVD_8_Pos)
+
+#define AON_REG_SRAM_CTRL32_RSVD_7_Pos                                                                                   4U
+#define AON_REG_SRAM_CTRL32_RSVD_7_Msk                                                                                   (0x1UL << AON_REG_SRAM_CTRL32_RSVD_7_Pos)
+
+#define AON_REG_SRAM_CTRL32_RSVD_6_Pos                                                                                   5U
+#define AON_REG_SRAM_CTRL32_RSVD_6_Msk                                                                                   (0x1UL << AON_REG_SRAM_CTRL32_RSVD_6_Pos)
+
+#define AON_REG_SRAM_CTRL32_RSVD_5_Pos                                                                                   6U
+#define AON_REG_SRAM_CTRL32_RSVD_5_Msk                                                                                   (0x1UL << AON_REG_SRAM_CTRL32_RSVD_5_Pos)
+
+#define AON_REG_SRAM_CTRL32_RSVD_4_Pos                                                                                   7U
+#define AON_REG_SRAM_CTRL32_RSVD_4_Msk                                                                                   (0x1UL << AON_REG_SRAM_CTRL32_RSVD_4_Pos)
+
+#define AON_REG_SRAM_CTRL32_RSVD_3_Pos                                                                                   8U
+#define AON_REG_SRAM_CTRL32_RSVD_3_Msk                                                                                   (0x1UL << AON_REG_SRAM_CTRL32_RSVD_3_Pos)
+
+#define AON_REG_SRAM_CTRL32_RSVD_2_Pos                                                                                   9U
+#define AON_REG_SRAM_CTRL32_RSVD_2_Msk                                                                                   (0x1UL << AON_REG_SRAM_CTRL32_RSVD_2_Pos)
+
+#define AON_REG_SRAM_CTRL32_RSVD_1_Pos                                                                                   10U
+#define AON_REG_SRAM_CTRL32_RSVD_1_Msk                                                                                   (0x1UL << AON_REG_SRAM_CTRL32_RSVD_1_Pos)
+
+#define AON_REG_SRAM_CTRL32_RSVD_Pos                                                                                     11U
+#define AON_REG_SRAM_CTRL32_RSVD_Msk                                                                                     (0x1FFFFFUL << AON_REG_SRAM_CTRL32_RSVD_Pos)
+
+/* 0x8A8    0x4000_08a8
+    31:0    R       RSVD                                                        0
+ */
+typedef union _AON_REG_SRAM_CTRL33_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RSVD;
+    };
+} AON_REG_SRAM_CTRL33_TYPE;
+
+/*0x4000_08a8 AON_REG_SRAM_CTRL33*/
+#define AON_REG_SRAM_CTRL33_RSVD_Pos                                                                                     0U
+#define AON_REG_SRAM_CTRL33_RSVD_Msk                                                                                     (0xFFFFFFFFUL << AON_REG_SRAM_CTRL33_RSVD_Pos)
+
+/* 0x8AC    0x4000_08ac
+    2:0     R/W     WPULSE_buffer_8k_lv                                         3'b000
+    5:3     R/W     WA_buffer_8k_lv                                             3'b101
+    9:6     R/W     RM_buffer_8k_lv                                             4'b0010
+    10      R/W     RME_buffer_8k_lv                                            1'b1
+    12:11   R/W     RA_buffer_8k_lv                                             2'b00
+    15:13   R       RSVD_1                                                      0
+    18:16   R/W     WPULSE_buffer_8k_hv                                         3'b000
+    21:19   R/W     WA_buffer_8k_hv                                             3'b100
+    25:22   R/W     RM_buffer_8k_hv                                             4'b0011
+    26      R/W     RME_buffer_8k_hv                                            1'b1
+    28:27   R/W     RA_buffer_8k_hv                                             2'b00
+    31:29   R       RSVD                                                        0
+ */
+typedef union _AON_REG_SRAM_CTRL34_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t WPULSE_buffer_8k_lv: 3;
+        uint32_t WA_buffer_8k_lv: 3;
+        uint32_t RM_buffer_8k_lv: 4;
+        uint32_t RME_buffer_8k_lv: 1;
+        uint32_t RA_buffer_8k_lv: 2;
+        uint32_t RSVD_1: 3;
+        uint32_t WPULSE_buffer_8k_hv: 3;
+        uint32_t WA_buffer_8k_hv: 3;
+        uint32_t RM_buffer_8k_hv: 4;
+        uint32_t RME_buffer_8k_hv: 1;
+        uint32_t RA_buffer_8k_hv: 2;
+        uint32_t RSVD: 3;
+    };
+} AON_REG_SRAM_CTRL34_TYPE;
+
+/*0x4000_08ac AON_REG_SRAM_CTRL34*/
+#define AON_REG_SRAM_CTRL34_WPULSE_buffer_8k_lv_Pos                                                                      0U
+#define AON_REG_SRAM_CTRL34_WPULSE_buffer_8k_lv_Msk                                                                      (0x7UL << AON_REG_SRAM_CTRL34_WPULSE_buffer_8k_lv_Pos)
+
+#define AON_REG_SRAM_CTRL34_WA_buffer_8k_lv_Pos                                                                          3U
+#define AON_REG_SRAM_CTRL34_WA_buffer_8k_lv_Msk                                                                          (0x7UL << AON_REG_SRAM_CTRL34_WA_buffer_8k_lv_Pos)
+
+#define AON_REG_SRAM_CTRL34_RM_buffer_8k_lv_Pos                                                                          6U
+#define AON_REG_SRAM_CTRL34_RM_buffer_8k_lv_Msk                                                                          (0xFUL << AON_REG_SRAM_CTRL34_RM_buffer_8k_lv_Pos)
+
+#define AON_REG_SRAM_CTRL34_RME_buffer_8k_lv_Pos                                                                         10U
+#define AON_REG_SRAM_CTRL34_RME_buffer_8k_lv_Msk                                                                         (0x1UL << AON_REG_SRAM_CTRL34_RME_buffer_8k_lv_Pos)
+
+#define AON_REG_SRAM_CTRL34_RA_buffer_8k_lv_Pos                                                                          11U
+#define AON_REG_SRAM_CTRL34_RA_buffer_8k_lv_Msk                                                                          (0x3UL << AON_REG_SRAM_CTRL34_RA_buffer_8k_lv_Pos)
+
+#define AON_REG_SRAM_CTRL34_RSVD_1_Pos                                                                                   13U
+#define AON_REG_SRAM_CTRL34_RSVD_1_Msk                                                                                   (0x7UL << AON_REG_SRAM_CTRL34_RSVD_1_Pos)
+
+#define AON_REG_SRAM_CTRL34_WPULSE_buffer_8k_hv_Pos                                                                      16U
+#define AON_REG_SRAM_CTRL34_WPULSE_buffer_8k_hv_Msk                                                                      (0x7UL << AON_REG_SRAM_CTRL34_WPULSE_buffer_8k_hv_Pos)
+
+#define AON_REG_SRAM_CTRL34_WA_buffer_8k_hv_Pos                                                                          19U
+#define AON_REG_SRAM_CTRL34_WA_buffer_8k_hv_Msk                                                                          (0x7UL << AON_REG_SRAM_CTRL34_WA_buffer_8k_hv_Pos)
+
+#define AON_REG_SRAM_CTRL34_RM_buffer_8k_hv_Pos                                                                          22U
+#define AON_REG_SRAM_CTRL34_RM_buffer_8k_hv_Msk                                                                          (0xFUL << AON_REG_SRAM_CTRL34_RM_buffer_8k_hv_Pos)
+
+#define AON_REG_SRAM_CTRL34_RME_buffer_8k_hv_Pos                                                                         26U
+#define AON_REG_SRAM_CTRL34_RME_buffer_8k_hv_Msk                                                                         (0x1UL << AON_REG_SRAM_CTRL34_RME_buffer_8k_hv_Pos)
+
+#define AON_REG_SRAM_CTRL34_RA_buffer_8k_hv_Pos                                                                          27U
+#define AON_REG_SRAM_CTRL34_RA_buffer_8k_hv_Msk                                                                          (0x3UL << AON_REG_SRAM_CTRL34_RA_buffer_8k_hv_Pos)
+
+#define AON_REG_SRAM_CTRL34_RSVD_Pos                                                                                     29U
+#define AON_REG_SRAM_CTRL34_RSVD_Msk                                                                                     (0x7UL << AON_REG_SRAM_CTRL34_RSVD_Pos)
+
+/* 0x8B0    0x4000_08b0
+    31:0    R/W     DUMMY2                                                      0
+ */
+typedef union _AON_REG_SRAM_CTRL35_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t DUMMY2;
+    };
+} AON_REG_SRAM_CTRL35_TYPE;
+
+/*0x4000_08b0 AON_REG_SRAM_CTRL35*/
+#define AON_REG_SRAM_CTRL35_DUMMY2_Pos                                                                                   0U
+#define AON_REG_SRAM_CTRL35_DUMMY2_Msk                                                                                   (0xFFFFFFFFUL << AON_REG_SRAM_CTRL35_DUMMY2_Pos)
+
+/* 0x8B4    0x4000_08b4
+    0       R/W     CLKCTRL_OSC128K_QACTIVE_ONLY_EN                             1'b1
+    1       R/W     REG_EN_OSC10_FOLLOW_PPU                                     1'b1
+    2       R/W     REG_EN_OSC10_PON_FOLLOW_PPU                                 1'b1
+    7:3     R/W     RESERVED_3                                                  5'b0
+    15:8    R/W     RESERVED_2                                                  8'b0
+    23:16   R/W     RESERVED_1                                                  8'b0
+    31:24   R/W     RESERVED                                                    8'b0
+ */
+typedef union _AON_REG_PCK600_AON_REG0X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t CLKCTRL_OSC128K_QACTIVE_ONLY_EN: 1;
+        uint32_t REG_EN_OSC10_FOLLOW_PPU: 1;
+        uint32_t REG_EN_OSC10_PON_FOLLOW_PPU: 1;
+        uint32_t RESERVED_3: 5;
+        uint32_t RESERVED_2: 8;
+        uint32_t RESERVED_1: 8;
+        uint32_t RESERVED: 8;
+    };
+} AON_REG_PCK600_AON_REG0X_TYPE;
+
+/*0x4000_08b4 AON_REG_PCK600_AON_REG0X*/
+#define AON_REG_PCK600_AON_REG0X_CLKCTRL_OSC128K_QACTIVE_ONLY_EN_Pos                                                     0U
+#define AON_REG_PCK600_AON_REG0X_CLKCTRL_OSC128K_QACTIVE_ONLY_EN_Msk                                                     (0x1UL << AON_REG_PCK600_AON_REG0X_CLKCTRL_OSC128K_QACTIVE_ONLY_EN_Pos)
+
+#define AON_REG_PCK600_AON_REG0X_REG_EN_OSC10_FOLLOW_PPU_Pos                                                             1U
+#define AON_REG_PCK600_AON_REG0X_REG_EN_OSC10_FOLLOW_PPU_Msk                                                             (0x1UL << AON_REG_PCK600_AON_REG0X_REG_EN_OSC10_FOLLOW_PPU_Pos)
+
+#define AON_REG_PCK600_AON_REG0X_REG_EN_OSC10_PON_FOLLOW_PPU_Pos                                                         2U
+#define AON_REG_PCK600_AON_REG0X_REG_EN_OSC10_PON_FOLLOW_PPU_Msk                                                         (0x1UL << AON_REG_PCK600_AON_REG0X_REG_EN_OSC10_PON_FOLLOW_PPU_Pos)
+
+#define AON_REG_PCK600_AON_REG0X_RESERVED_3_Pos                                                                          3U
+#define AON_REG_PCK600_AON_REG0X_RESERVED_3_Msk                                                                          (0x1FUL << AON_REG_PCK600_AON_REG0X_RESERVED_3_Pos)
+
+#define AON_REG_PCK600_AON_REG0X_RESERVED_2_Pos                                                                          8U
+#define AON_REG_PCK600_AON_REG0X_RESERVED_2_Msk                                                                          (0xFFUL << AON_REG_PCK600_AON_REG0X_RESERVED_2_Pos)
+
+#define AON_REG_PCK600_AON_REG0X_RESERVED_1_Pos                                                                          16U
+#define AON_REG_PCK600_AON_REG0X_RESERVED_1_Msk                                                                          (0xFFUL << AON_REG_PCK600_AON_REG0X_RESERVED_1_Pos)
+
+#define AON_REG_PCK600_AON_REG0X_RESERVED_Pos                                                                            24U
+#define AON_REG_PCK600_AON_REG0X_RESERVED_Msk                                                                            (0xFFUL << AON_REG_PCK600_AON_REG0X_RESERVED_Pos)
+
+/* 0x8B8    0x4000_08b8
+    7:0     R/W     RESERVED_2                                                  8'b0
+    15:8    R/W     ENTRY_DELAY_PON_LV_DEV_OSC10                                8'b0
+    23:16   R/W     RESERVED_1                                                  8'b0
+    31:24   R/W     RESERVED                                                    8'b0
+ */
+typedef union _AON_REG_PCK600_AON_REG1X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED_2: 8;
+        uint32_t ENTRY_DELAY_PON_LV_DEV_OSC10: 8;
+        uint32_t RESERVED_1: 8;
+        uint32_t RESERVED: 8;
+    };
+} AON_REG_PCK600_AON_REG1X_TYPE;
+
+/*0x4000_08b8 AON_REG_PCK600_AON_REG1X*/
+#define AON_REG_PCK600_AON_REG1X_RESERVED_2_Pos                                                                          0U
+#define AON_REG_PCK600_AON_REG1X_RESERVED_2_Msk                                                                          (0xFFUL << AON_REG_PCK600_AON_REG1X_RESERVED_2_Pos)
+
+#define AON_REG_PCK600_AON_REG1X_ENTRY_DELAY_PON_LV_DEV_OSC10_Pos                                                        8U
+#define AON_REG_PCK600_AON_REG1X_ENTRY_DELAY_PON_LV_DEV_OSC10_Msk                                                        (0xFFUL << AON_REG_PCK600_AON_REG1X_ENTRY_DELAY_PON_LV_DEV_OSC10_Pos)
+
+#define AON_REG_PCK600_AON_REG1X_RESERVED_1_Pos                                                                          16U
+#define AON_REG_PCK600_AON_REG1X_RESERVED_1_Msk                                                                          (0xFFUL << AON_REG_PCK600_AON_REG1X_RESERVED_1_Pos)
+
+#define AON_REG_PCK600_AON_REG1X_RESERVED_Pos                                                                            24U
+#define AON_REG_PCK600_AON_REG1X_RESERVED_Msk                                                                            (0xFFUL << AON_REG_PCK600_AON_REG1X_RESERVED_Pos)
+
+/* 0x8BC    0x4000_08bc
+    7:0     R/W     ENTRY_DELAY_OSC10_PON                                       8'h0
+    15:8    R/W     ENTRY_DELAY_OSC10                                           8'b0
+    23:16   R/W     ENTRY_DELAY_OSC128K_PON                                     8'b0
+    31:24   R/W     ENTRY_DELAY_OSC128K                                         8'b0
+ */
+typedef union _AON_REG_PCK600_AON_REG2X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t ENTRY_DELAY_OSC10_PON: 8;
+        uint32_t ENTRY_DELAY_OSC10: 8;
+        uint32_t ENTRY_DELAY_OSC128K_PON: 8;
+        uint32_t ENTRY_DELAY_OSC128K: 8;
+    };
+} AON_REG_PCK600_AON_REG2X_TYPE;
+
+/*0x4000_08bc AON_REG_PCK600_AON_REG2X*/
+#define AON_REG_PCK600_AON_REG2X_ENTRY_DELAY_OSC10_PON_Pos                                                               0U
+#define AON_REG_PCK600_AON_REG2X_ENTRY_DELAY_OSC10_PON_Msk                                                               (0xFFUL << AON_REG_PCK600_AON_REG2X_ENTRY_DELAY_OSC10_PON_Pos)
+
+#define AON_REG_PCK600_AON_REG2X_ENTRY_DELAY_OSC10_Pos                                                                   8U
+#define AON_REG_PCK600_AON_REG2X_ENTRY_DELAY_OSC10_Msk                                                                   (0xFFUL << AON_REG_PCK600_AON_REG2X_ENTRY_DELAY_OSC10_Pos)
+
+#define AON_REG_PCK600_AON_REG2X_ENTRY_DELAY_OSC128K_PON_Pos                                                             16U
+#define AON_REG_PCK600_AON_REG2X_ENTRY_DELAY_OSC128K_PON_Msk                                                             (0xFFUL << AON_REG_PCK600_AON_REG2X_ENTRY_DELAY_OSC128K_PON_Pos)
+
+#define AON_REG_PCK600_AON_REG2X_ENTRY_DELAY_OSC128K_Pos                                                                 24U
+#define AON_REG_PCK600_AON_REG2X_ENTRY_DELAY_OSC128K_Msk                                                                 (0xFFUL << AON_REG_PCK600_AON_REG2X_ENTRY_DELAY_OSC128K_Pos)
+
+/* 0x8C0    0x4000_08c0
+    0       R/W     OSC10_CORE_CLK_FORCE                                        1'b0
+    1       R/W     OSC10_PON_CLK_FORCE                                         1'b0
+    2       R/W     OSC10_CLK_FORCE                                             1'b0
+    3       R/W     OSC128_CORE_CLK_FORCE                                       1'b0
+    4       R/W     OSC128_PON_CLK_FORCE                                        1'b0
+    5       R/W     OSC128_CLK_FORCE                                            1'b0
+    15:6    R/W     RESERVED                                                    10'b0
+    23:16   R/W     ENTRY_DELAY_OSC10_CORE                                      8'h0
+    31:24   R/W     ENTRY_DELAY_OSC128K_CORE                                    8'b0
+ */
+typedef union _AON_REG_PCK600_AON_REG3X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t OSC10_CORE_CLK_FORCE: 1;
+        uint32_t OSC10_PON_CLK_FORCE: 1;
+        uint32_t OSC10_CLK_FORCE: 1;
+        uint32_t OSC128_CORE_CLK_FORCE: 1;
+        uint32_t OSC128_PON_CLK_FORCE: 1;
+        uint32_t OSC128_CLK_FORCE: 1;
+        uint32_t RESERVED: 10;
+        uint32_t ENTRY_DELAY_OSC10_CORE: 8;
+        uint32_t ENTRY_DELAY_OSC128K_CORE: 8;
+    };
+} AON_REG_PCK600_AON_REG3X_TYPE;
+
+/*0x4000_08c0 AON_REG_PCK600_AON_REG3X*/
+#define AON_REG_PCK600_AON_REG3X_OSC10_CORE_CLK_FORCE_Pos                                                                0U
+#define AON_REG_PCK600_AON_REG3X_OSC10_CORE_CLK_FORCE_Msk                                                                (0x1UL << AON_REG_PCK600_AON_REG3X_OSC10_CORE_CLK_FORCE_Pos)
+
+#define AON_REG_PCK600_AON_REG3X_OSC10_PON_CLK_FORCE_Pos                                                                 1U
+#define AON_REG_PCK600_AON_REG3X_OSC10_PON_CLK_FORCE_Msk                                                                 (0x1UL << AON_REG_PCK600_AON_REG3X_OSC10_PON_CLK_FORCE_Pos)
+
+#define AON_REG_PCK600_AON_REG3X_OSC10_CLK_FORCE_Pos                                                                     2U
+#define AON_REG_PCK600_AON_REG3X_OSC10_CLK_FORCE_Msk                                                                     (0x1UL << AON_REG_PCK600_AON_REG3X_OSC10_CLK_FORCE_Pos)
+
+#define AON_REG_PCK600_AON_REG3X_OSC128_CORE_CLK_FORCE_Pos                                                               3U
+#define AON_REG_PCK600_AON_REG3X_OSC128_CORE_CLK_FORCE_Msk                                                               (0x1UL << AON_REG_PCK600_AON_REG3X_OSC128_CORE_CLK_FORCE_Pos)
+
+#define AON_REG_PCK600_AON_REG3X_OSC128_PON_CLK_FORCE_Pos                                                                4U
+#define AON_REG_PCK600_AON_REG3X_OSC128_PON_CLK_FORCE_Msk                                                                (0x1UL << AON_REG_PCK600_AON_REG3X_OSC128_PON_CLK_FORCE_Pos)
+
+#define AON_REG_PCK600_AON_REG3X_OSC128_CLK_FORCE_Pos                                                                    5U
+#define AON_REG_PCK600_AON_REG3X_OSC128_CLK_FORCE_Msk                                                                    (0x1UL << AON_REG_PCK600_AON_REG3X_OSC128_CLK_FORCE_Pos)
+
+#define AON_REG_PCK600_AON_REG3X_RESERVED_Pos                                                                            6U
+#define AON_REG_PCK600_AON_REG3X_RESERVED_Msk                                                                            (0x3FFUL << AON_REG_PCK600_AON_REG3X_RESERVED_Pos)
+
+#define AON_REG_PCK600_AON_REG3X_ENTRY_DELAY_OSC10_CORE_Pos                                                              16U
+#define AON_REG_PCK600_AON_REG3X_ENTRY_DELAY_OSC10_CORE_Msk                                                              (0xFFUL << AON_REG_PCK600_AON_REG3X_ENTRY_DELAY_OSC10_CORE_Pos)
+
+#define AON_REG_PCK600_AON_REG3X_ENTRY_DELAY_OSC128K_CORE_Pos                                                            24U
+#define AON_REG_PCK600_AON_REG3X_ENTRY_DELAY_OSC128K_CORE_Msk                                                            (0xFFUL << AON_REG_PCK600_AON_REG3X_ENTRY_DELAY_OSC128K_CORE_Pos)
+
+/* 0x8C4    0x4000_08c4
+    0       R       PCSM_PPU_VPON_QCH_BUSY_FLAG0                                1'b1
+    1       R       PCSM_OSC10_PON_QCH_BUSY_FLAG0                               1'b1
+    2       R       PCSM_OSC10_QCH_BUSY_FLAG0                                   1'b1
+    15:3    R       RESERVED_1                                                  13'd0
+    16      R       PCSM_PPU_VPON_QCH_BUSY_FLAG1                                1'b0
+    17      R       PCSM_OSC10_PON_QCH_BUSY_FLAG1                               1'b0
+    18      R       PCSM_OSC10_QCH_BUSY_FLAG1                                   1'b0
+    30:19   R       RESERVED                                                    12'd0
+    31      R/W1C   AON_DBG_QCH_BUSY_FLAG_W1C                                   1'b0
+ */
+typedef union _AON_REG_PCK600_AON_REG4X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t PCSM_PPU_VPON_QCH_BUSY_FLAG0: 1;
+        uint32_t PCSM_OSC10_PON_QCH_BUSY_FLAG0: 1;
+        uint32_t PCSM_OSC10_QCH_BUSY_FLAG0: 1;
+        uint32_t RESERVED_1: 13;
+        uint32_t PCSM_PPU_VPON_QCH_BUSY_FLAG1: 1;
+        uint32_t PCSM_OSC10_PON_QCH_BUSY_FLAG1: 1;
+        uint32_t PCSM_OSC10_QCH_BUSY_FLAG1: 1;
+        uint32_t RESERVED: 12;
+        uint32_t AON_DBG_QCH_BUSY_FLAG_W1C: 1;
+    };
+} AON_REG_PCK600_AON_REG4X_TYPE;
+
+/*0x4000_08c4 AON_REG_PCK600_AON_REG4X*/
+#define AON_REG_PCK600_AON_REG4X_PCSM_PPU_VPON_QCH_BUSY_FLAG0_Pos                                                        0U
+#define AON_REG_PCK600_AON_REG4X_PCSM_PPU_VPON_QCH_BUSY_FLAG0_Msk                                                        (0x1UL << AON_REG_PCK600_AON_REG4X_PCSM_PPU_VPON_QCH_BUSY_FLAG0_Pos)
+
+#define AON_REG_PCK600_AON_REG4X_PCSM_OSC10_PON_QCH_BUSY_FLAG0_Pos                                                       1U
+#define AON_REG_PCK600_AON_REG4X_PCSM_OSC10_PON_QCH_BUSY_FLAG0_Msk                                                       (0x1UL << AON_REG_PCK600_AON_REG4X_PCSM_OSC10_PON_QCH_BUSY_FLAG0_Pos)
+
+#define AON_REG_PCK600_AON_REG4X_PCSM_OSC10_QCH_BUSY_FLAG0_Pos                                                           2U
+#define AON_REG_PCK600_AON_REG4X_PCSM_OSC10_QCH_BUSY_FLAG0_Msk                                                           (0x1UL << AON_REG_PCK600_AON_REG4X_PCSM_OSC10_QCH_BUSY_FLAG0_Pos)
+
+#define AON_REG_PCK600_AON_REG4X_RESERVED_1_Pos                                                                          3U
+#define AON_REG_PCK600_AON_REG4X_RESERVED_1_Msk                                                                          (0x1FFFUL << AON_REG_PCK600_AON_REG4X_RESERVED_1_Pos)
+
+#define AON_REG_PCK600_AON_REG4X_PCSM_PPU_VPON_QCH_BUSY_FLAG1_Pos                                                        16U
+#define AON_REG_PCK600_AON_REG4X_PCSM_PPU_VPON_QCH_BUSY_FLAG1_Msk                                                        (0x1UL << AON_REG_PCK600_AON_REG4X_PCSM_PPU_VPON_QCH_BUSY_FLAG1_Pos)
+
+#define AON_REG_PCK600_AON_REG4X_PCSM_OSC10_PON_QCH_BUSY_FLAG1_Pos                                                       17U
+#define AON_REG_PCK600_AON_REG4X_PCSM_OSC10_PON_QCH_BUSY_FLAG1_Msk                                                       (0x1UL << AON_REG_PCK600_AON_REG4X_PCSM_OSC10_PON_QCH_BUSY_FLAG1_Pos)
+
+#define AON_REG_PCK600_AON_REG4X_PCSM_OSC10_QCH_BUSY_FLAG1_Pos                                                           18U
+#define AON_REG_PCK600_AON_REG4X_PCSM_OSC10_QCH_BUSY_FLAG1_Msk                                                           (0x1UL << AON_REG_PCK600_AON_REG4X_PCSM_OSC10_QCH_BUSY_FLAG1_Pos)
+
+#define AON_REG_PCK600_AON_REG4X_RESERVED_Pos                                                                            19U
+#define AON_REG_PCK600_AON_REG4X_RESERVED_Msk                                                                            (0xFFFUL << AON_REG_PCK600_AON_REG4X_RESERVED_Pos)
+
+#define AON_REG_PCK600_AON_REG4X_AON_DBG_QCH_BUSY_FLAG_W1C_Pos                                                           31U
+#define AON_REG_PCK600_AON_REG4X_AON_DBG_QCH_BUSY_FLAG_W1C_Msk                                                           (0x1UL << AON_REG_PCK600_AON_REG4X_AON_DBG_QCH_BUSY_FLAG_W1C_Pos)
+
+/* 0x8C8    0x4000_08c8
+    11:0    R       VPON_LEAVE_FUNC_RET_MODE_CNT_VALUE                          12'b0
+    14:12   R       RESERVED_1                                                  3'b0
+    15      R       VPON_LEAVE_FUNC_RET_MODE_CNT_CLAMP_FLAG                     1'b0
+    30:16   R       RESERVED                                                    15'b0
+    31      R/W1C   VPON_LEAVE_FUNC_RET_MODE_CNT_W1C                            1'b0
+ */
+typedef union _AON_REG_PCK600_AON_REG5X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t VPON_LEAVE_FUNC_RET_MODE_CNT_VALUE: 12;
+        uint32_t RESERVED_1: 3;
+        uint32_t VPON_LEAVE_FUNC_RET_MODE_CNT_CLAMP_FLAG: 1;
+        uint32_t RESERVED: 15;
+        uint32_t VPON_LEAVE_FUNC_RET_MODE_CNT_W1C: 1;
+    };
+} AON_REG_PCK600_AON_REG5X_TYPE;
+
+/*0x4000_08c8 AON_REG_PCK600_AON_REG5X*/
+#define AON_REG_PCK600_AON_REG5X_VPON_LEAVE_FUNC_RET_MODE_CNT_VALUE_Pos                                                  0U
+#define AON_REG_PCK600_AON_REG5X_VPON_LEAVE_FUNC_RET_MODE_CNT_VALUE_Msk                                                  (0xFFFUL << AON_REG_PCK600_AON_REG5X_VPON_LEAVE_FUNC_RET_MODE_CNT_VALUE_Pos)
+
+#define AON_REG_PCK600_AON_REG5X_RESERVED_1_Pos                                                                          12U
+#define AON_REG_PCK600_AON_REG5X_RESERVED_1_Msk                                                                          (0x7UL << AON_REG_PCK600_AON_REG5X_RESERVED_1_Pos)
+
+#define AON_REG_PCK600_AON_REG5X_VPON_LEAVE_FUNC_RET_MODE_CNT_CLAMP_FLAG_Pos                                             15U
+#define AON_REG_PCK600_AON_REG5X_VPON_LEAVE_FUNC_RET_MODE_CNT_CLAMP_FLAG_Msk                                             (0x1UL << AON_REG_PCK600_AON_REG5X_VPON_LEAVE_FUNC_RET_MODE_CNT_CLAMP_FLAG_Pos)
+
+#define AON_REG_PCK600_AON_REG5X_RESERVED_Pos                                                                            16U
+#define AON_REG_PCK600_AON_REG5X_RESERVED_Msk                                                                            (0x7FFFUL << AON_REG_PCK600_AON_REG5X_RESERVED_Pos)
+
+#define AON_REG_PCK600_AON_REG5X_VPON_LEAVE_FUNC_RET_MODE_CNT_W1C_Pos                                                    31U
+#define AON_REG_PCK600_AON_REG5X_VPON_LEAVE_FUNC_RET_MODE_CNT_W1C_Msk                                                    (0x1UL << AON_REG_PCK600_AON_REG5X_VPON_LEAVE_FUNC_RET_MODE_CNT_W1C_Pos)
+
+/* 0x8CC    0x4000_08cc
+    7:0     R/W     DEBUG_SEL                                                   8'b0
+    31:8    R/W     RESERVED                                                    24'b0
+ */
+typedef union _AON_REG_PCK600_VPON_REG0X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t DEBUG_SEL: 8;
+        uint32_t RESERVED: 24;
+    };
+} AON_REG_PCK600_VPON_REG0X_TYPE;
+
+/*0x4000_08cc AON_REG_PCK600_VPON_REG0X*/
+#define AON_REG_PCK600_VPON_REG0X_DEBUG_SEL_Pos                                                                          0U
+#define AON_REG_PCK600_VPON_REG0X_DEBUG_SEL_Msk                                                                          (0xFFUL << AON_REG_PCK600_VPON_REG0X_DEBUG_SEL_Pos)
+
+#define AON_REG_PCK600_VPON_REG0X_RESERVED_Pos                                                                           8U
+#define AON_REG_PCK600_VPON_REG0X_RESERVED_Msk                                                                           (0xFFFFFFUL << AON_REG_PCK600_VPON_REG0X_RESERVED_Pos)
+
+/* 0x8D0    0x4000_08d0
+    7:0     R/W     ENTRY_DELAY_OSC80                                           8'b0
+    15:8    R/W     ENTRY_DELAY_OSC80_CG                                        8'b0
+    23:16   R/W     ENTRY_DELAY_XTAL40                                          8'b0
+    31:24   R/W     ENTRY_DELAY_PLL1                                            8'b0
+ */
+typedef union _AON_REG_PCK600_VPON_REG1X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t ENTRY_DELAY_OSC80: 8;
+        uint32_t ENTRY_DELAY_OSC80_CG: 8;
+        uint32_t ENTRY_DELAY_XTAL40: 8;
+        uint32_t ENTRY_DELAY_PLL1: 8;
+    };
+} AON_REG_PCK600_VPON_REG1X_TYPE;
+
+/*0x4000_08d0 AON_REG_PCK600_VPON_REG1X*/
+#define AON_REG_PCK600_VPON_REG1X_ENTRY_DELAY_OSC80_Pos                                                                  0U
+#define AON_REG_PCK600_VPON_REG1X_ENTRY_DELAY_OSC80_Msk                                                                  (0xFFUL << AON_REG_PCK600_VPON_REG1X_ENTRY_DELAY_OSC80_Pos)
+
+#define AON_REG_PCK600_VPON_REG1X_ENTRY_DELAY_OSC80_CG_Pos                                                               8U
+#define AON_REG_PCK600_VPON_REG1X_ENTRY_DELAY_OSC80_CG_Msk                                                               (0xFFUL << AON_REG_PCK600_VPON_REG1X_ENTRY_DELAY_OSC80_CG_Pos)
+
+#define AON_REG_PCK600_VPON_REG1X_ENTRY_DELAY_XTAL40_Pos                                                                 16U
+#define AON_REG_PCK600_VPON_REG1X_ENTRY_DELAY_XTAL40_Msk                                                                 (0xFFUL << AON_REG_PCK600_VPON_REG1X_ENTRY_DELAY_XTAL40_Pos)
+
+#define AON_REG_PCK600_VPON_REG1X_ENTRY_DELAY_PLL1_Pos                                                                   24U
+#define AON_REG_PCK600_VPON_REG1X_ENTRY_DELAY_PLL1_Msk                                                                   (0xFFUL << AON_REG_PCK600_VPON_REG1X_ENTRY_DELAY_PLL1_Pos)
+
+/* 0x8D4    0x4000_08d4
+    0       R/W     OSC80_CLK_FORCE                                             1'b0
+    1       R/W     OSC80_CG_CLK_FORCE                                          1'b0
+    2       R/W     XTAL40_CLK_FORCE                                            1'b0
+    3       R/W     PLL1_CLK_FORCE                                              1'b0
+    28:4    R/W     RESERVED                                                    25'b0
+    29      R/W     EN_BYPASS_EXIT_DSM_XTAL_CHECK                               1'b1
+    30      R/W     LPDQ_REG_EN_CORE1_OSC_PWRQ                                  1'b1
+    31      R/W     LPDQ_REG_EN_CORE1_XTAL40_PWRQ                               1'b1
+ */
+typedef union _AON_REG_PCK600_VPON_REG2X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t OSC80_CLK_FORCE: 1;
+        uint32_t OSC80_CG_CLK_FORCE: 1;
+        uint32_t XTAL40_CLK_FORCE: 1;
+        uint32_t PLL1_CLK_FORCE: 1;
+        uint32_t RESERVED: 25;
+        uint32_t EN_BYPASS_EXIT_DSM_XTAL_CHECK: 1;
+        uint32_t LPDQ_REG_EN_CORE1_OSC_PWRQ: 1;
+        uint32_t LPDQ_REG_EN_CORE1_XTAL40_PWRQ: 1;
+    };
+} AON_REG_PCK600_VPON_REG2X_TYPE;
+
+/*0x4000_08d4 AON_REG_PCK600_VPON_REG2X*/
+#define AON_REG_PCK600_VPON_REG2X_OSC80_CLK_FORCE_Pos                                                                    0U
+#define AON_REG_PCK600_VPON_REG2X_OSC80_CLK_FORCE_Msk                                                                    (0x1UL << AON_REG_PCK600_VPON_REG2X_OSC80_CLK_FORCE_Pos)
+
+#define AON_REG_PCK600_VPON_REG2X_OSC80_CG_CLK_FORCE_Pos                                                                 1U
+#define AON_REG_PCK600_VPON_REG2X_OSC80_CG_CLK_FORCE_Msk                                                                 (0x1UL << AON_REG_PCK600_VPON_REG2X_OSC80_CG_CLK_FORCE_Pos)
+
+#define AON_REG_PCK600_VPON_REG2X_XTAL40_CLK_FORCE_Pos                                                                   2U
+#define AON_REG_PCK600_VPON_REG2X_XTAL40_CLK_FORCE_Msk                                                                   (0x1UL << AON_REG_PCK600_VPON_REG2X_XTAL40_CLK_FORCE_Pos)
+
+#define AON_REG_PCK600_VPON_REG2X_PLL1_CLK_FORCE_Pos                                                                     3U
+#define AON_REG_PCK600_VPON_REG2X_PLL1_CLK_FORCE_Msk                                                                     (0x1UL << AON_REG_PCK600_VPON_REG2X_PLL1_CLK_FORCE_Pos)
+
+#define AON_REG_PCK600_VPON_REG2X_RESERVED_Pos                                                                           4U
+#define AON_REG_PCK600_VPON_REG2X_RESERVED_Msk                                                                           (0x1FFFFFFUL << AON_REG_PCK600_VPON_REG2X_RESERVED_Pos)
+
+#define AON_REG_PCK600_VPON_REG2X_EN_BYPASS_EXIT_DSM_XTAL_CHECK_Pos                                                      29U
+#define AON_REG_PCK600_VPON_REG2X_EN_BYPASS_EXIT_DSM_XTAL_CHECK_Msk                                                      (0x1UL << AON_REG_PCK600_VPON_REG2X_EN_BYPASS_EXIT_DSM_XTAL_CHECK_Pos)
+
+#define AON_REG_PCK600_VPON_REG2X_LPDQ_REG_EN_CORE1_OSC_PWRQ_Pos                                                         30U
+#define AON_REG_PCK600_VPON_REG2X_LPDQ_REG_EN_CORE1_OSC_PWRQ_Msk                                                         (0x1UL << AON_REG_PCK600_VPON_REG2X_LPDQ_REG_EN_CORE1_OSC_PWRQ_Pos)
+
+#define AON_REG_PCK600_VPON_REG2X_LPDQ_REG_EN_CORE1_XTAL40_PWRQ_Pos                                                      31U
+#define AON_REG_PCK600_VPON_REG2X_LPDQ_REG_EN_CORE1_XTAL40_PWRQ_Msk                                                      (0x1UL << AON_REG_PCK600_VPON_REG2X_LPDQ_REG_EN_CORE1_XTAL40_PWRQ_Pos)
+
+/* 0x8D8    0x4000_08d8
+    0       R/W     PPU_VCORE_CLK_FORCE                                         1'b0
+    1       R/W     PLATFORM_EXTEND_CLK_FORCE                                   1'b0
+    9:2     R/W     ENTRY_DELAY_PPU_VCORE                                       8'b0
+    17:10   R/W     ENTRY_DELAY_PLATFORM_EXTEND                                 8'b0
+    31:18   R/W     RESERVED                                                    14'b0
+ */
+typedef union _AON_REG_PCK600_VPON_REG3X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t PPU_VCORE_CLK_FORCE: 1;
+        uint32_t PLATFORM_EXTEND_CLK_FORCE: 1;
+        uint32_t ENTRY_DELAY_PPU_VCORE: 8;
+        uint32_t ENTRY_DELAY_PLATFORM_EXTEND: 8;
+        uint32_t RESERVED: 14;
+    };
+} AON_REG_PCK600_VPON_REG3X_TYPE;
+
+/*0x4000_08d8 AON_REG_PCK600_VPON_REG3X*/
+#define AON_REG_PCK600_VPON_REG3X_PPU_VCORE_CLK_FORCE_Pos                                                                0U
+#define AON_REG_PCK600_VPON_REG3X_PPU_VCORE_CLK_FORCE_Msk                                                                (0x1UL << AON_REG_PCK600_VPON_REG3X_PPU_VCORE_CLK_FORCE_Pos)
+
+#define AON_REG_PCK600_VPON_REG3X_PLATFORM_EXTEND_CLK_FORCE_Pos                                                          1U
+#define AON_REG_PCK600_VPON_REG3X_PLATFORM_EXTEND_CLK_FORCE_Msk                                                          (0x1UL << AON_REG_PCK600_VPON_REG3X_PLATFORM_EXTEND_CLK_FORCE_Pos)
+
+#define AON_REG_PCK600_VPON_REG3X_ENTRY_DELAY_PPU_VCORE_Pos                                                              2U
+#define AON_REG_PCK600_VPON_REG3X_ENTRY_DELAY_PPU_VCORE_Msk                                                              (0xFFUL << AON_REG_PCK600_VPON_REG3X_ENTRY_DELAY_PPU_VCORE_Pos)
+
+#define AON_REG_PCK600_VPON_REG3X_ENTRY_DELAY_PLATFORM_EXTEND_Pos                                                        10U
+#define AON_REG_PCK600_VPON_REG3X_ENTRY_DELAY_PLATFORM_EXTEND_Msk                                                        (0xFFUL << AON_REG_PCK600_VPON_REG3X_ENTRY_DELAY_PLATFORM_EXTEND_Pos)
+
+#define AON_REG_PCK600_VPON_REG3X_RESERVED_Pos                                                                           18U
+#define AON_REG_PCK600_VPON_REG3X_RESERVED_Msk                                                                           (0x3FFFUL << AON_REG_PCK600_VPON_REG3X_RESERVED_Pos)
+
+/* 0x8DC    0x4000_08dc
+    0       R       PSCM_OSC80_QCH_BUSY_FLAG1                                   1'b0
+    1       R       PCSM_XTAL40_QCH_BUSY_FLAG1                                  1'b0
+    2       R       PCSM_PPU_VCORE_QCH_BUSY_FLAG1                               1'b0
+    3       R       PCSM_PLL1_QCH_BUSY_FLAG1                                    1'b0
+    4       R       PCSM_OSC80_CG_QCH_BUSY_FLAG1                                1'b0
+    5       R       WDT_BUS_QCH_BUSY_FLAG1                                      1'b0
+    6       R       WDT_QCH_BUSY_FLAG1                                          1'b0
+    7       R       SCH_PLN_QCH_BUSY_FLAG1                                      1'b0
+    8       R       RTC_BUS_QCH_BUSY_FLAG1                                      1'b0
+    9       R       RTC_QCH_BUSY_FLAG1                                          1'b0
+    10      R       RAP_BUS_QCH_BUSY_FLAG1                                      1'b0
+    11      R       RAP_QCH_BUSY_FLAG1                                          1'b0
+    12      R       LPQDEC_BUS_QCH_BUSY_FLAG1                                   1'b0
+    13      R       LPQDEC_QCH_BUSY_FLAG1                                       1'b0
+    14      R       LPPWM_QCH_BUSY_FLAG1                                        1'b0
+    15      R       LPC_BUS_QCH_BUSY_FLAG1                                      1'b0
+    16      R       LPC_QCH_BUSY_FLAG1                                          1'b0
+    17      R       GRTC_BUS_QCH_BUSY_FLAG1                                     1'b0
+    18      R       GRTC_QCH_BUSY_FLAG1                                         1'b0
+    19      R       BTMAC_32K_QCH_BUSY_FLAG1                                    1'b0
+    31:20   R       RESERVED                                                    12'b0
+ */
+typedef union _AON_REG_PCK600_VPON_REG4X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t PSCM_OSC80_QCH_BUSY_FLAG1: 1;
+        uint32_t PCSM_XTAL40_QCH_BUSY_FLAG1: 1;
+        uint32_t PCSM_PPU_VCORE_QCH_BUSY_FLAG1: 1;
+        uint32_t PCSM_PLL1_QCH_BUSY_FLAG1: 1;
+        uint32_t PCSM_OSC80_CG_QCH_BUSY_FLAG1: 1;
+        uint32_t WDT_BUS_QCH_BUSY_FLAG1: 1;
+        uint32_t WDT_QCH_BUSY_FLAG1: 1;
+        uint32_t SCH_PLN_QCH_BUSY_FLAG1: 1;
+        uint32_t RTC_BUS_QCH_BUSY_FLAG1: 1;
+        uint32_t RTC_QCH_BUSY_FLAG1: 1;
+        uint32_t RAP_BUS_QCH_BUSY_FLAG1: 1;
+        uint32_t RAP_QCH_BUSY_FLAG1: 1;
+        uint32_t LPQDEC_BUS_QCH_BUSY_FLAG1: 1;
+        uint32_t LPQDEC_QCH_BUSY_FLAG1: 1;
+        uint32_t LPPWM_QCH_BUSY_FLAG1: 1;
+        uint32_t LPC_BUS_QCH_BUSY_FLAG1: 1;
+        uint32_t LPC_QCH_BUSY_FLAG1: 1;
+        uint32_t GRTC_BUS_QCH_BUSY_FLAG1: 1;
+        uint32_t GRTC_QCH_BUSY_FLAG1: 1;
+        uint32_t BTMAC_32K_QCH_BUSY_FLAG1: 1;
+        uint32_t RESERVED: 12;
+    };
+} AON_REG_PCK600_VPON_REG4X_TYPE;
+
+/*0x4000_08dc AON_REG_PCK600_VPON_REG4X*/
+#define AON_REG_PCK600_VPON_REG4X_PSCM_OSC80_QCH_BUSY_FLAG1_Pos                                                          0U
+#define AON_REG_PCK600_VPON_REG4X_PSCM_OSC80_QCH_BUSY_FLAG1_Msk                                                          (0x1UL << AON_REG_PCK600_VPON_REG4X_PSCM_OSC80_QCH_BUSY_FLAG1_Pos)
+
+#define AON_REG_PCK600_VPON_REG4X_PCSM_XTAL40_QCH_BUSY_FLAG1_Pos                                                         1U
+#define AON_REG_PCK600_VPON_REG4X_PCSM_XTAL40_QCH_BUSY_FLAG1_Msk                                                         (0x1UL << AON_REG_PCK600_VPON_REG4X_PCSM_XTAL40_QCH_BUSY_FLAG1_Pos)
+
+#define AON_REG_PCK600_VPON_REG4X_PCSM_PPU_VCORE_QCH_BUSY_FLAG1_Pos                                                      2U
+#define AON_REG_PCK600_VPON_REG4X_PCSM_PPU_VCORE_QCH_BUSY_FLAG1_Msk                                                      (0x1UL << AON_REG_PCK600_VPON_REG4X_PCSM_PPU_VCORE_QCH_BUSY_FLAG1_Pos)
+
+#define AON_REG_PCK600_VPON_REG4X_PCSM_PLL1_QCH_BUSY_FLAG1_Pos                                                           3U
+#define AON_REG_PCK600_VPON_REG4X_PCSM_PLL1_QCH_BUSY_FLAG1_Msk                                                           (0x1UL << AON_REG_PCK600_VPON_REG4X_PCSM_PLL1_QCH_BUSY_FLAG1_Pos)
+
+#define AON_REG_PCK600_VPON_REG4X_PCSM_OSC80_CG_QCH_BUSY_FLAG1_Pos                                                       4U
+#define AON_REG_PCK600_VPON_REG4X_PCSM_OSC80_CG_QCH_BUSY_FLAG1_Msk                                                       (0x1UL << AON_REG_PCK600_VPON_REG4X_PCSM_OSC80_CG_QCH_BUSY_FLAG1_Pos)
+
+#define AON_REG_PCK600_VPON_REG4X_WDT_BUS_QCH_BUSY_FLAG1_Pos                                                             5U
+#define AON_REG_PCK600_VPON_REG4X_WDT_BUS_QCH_BUSY_FLAG1_Msk                                                             (0x1UL << AON_REG_PCK600_VPON_REG4X_WDT_BUS_QCH_BUSY_FLAG1_Pos)
+
+#define AON_REG_PCK600_VPON_REG4X_WDT_QCH_BUSY_FLAG1_Pos                                                                 6U
+#define AON_REG_PCK600_VPON_REG4X_WDT_QCH_BUSY_FLAG1_Msk                                                                 (0x1UL << AON_REG_PCK600_VPON_REG4X_WDT_QCH_BUSY_FLAG1_Pos)
+
+#define AON_REG_PCK600_VPON_REG4X_SCH_PLN_QCH_BUSY_FLAG1_Pos                                                             7U
+#define AON_REG_PCK600_VPON_REG4X_SCH_PLN_QCH_BUSY_FLAG1_Msk                                                             (0x1UL << AON_REG_PCK600_VPON_REG4X_SCH_PLN_QCH_BUSY_FLAG1_Pos)
+
+#define AON_REG_PCK600_VPON_REG4X_RTC_BUS_QCH_BUSY_FLAG1_Pos                                                             8U
+#define AON_REG_PCK600_VPON_REG4X_RTC_BUS_QCH_BUSY_FLAG1_Msk                                                             (0x1UL << AON_REG_PCK600_VPON_REG4X_RTC_BUS_QCH_BUSY_FLAG1_Pos)
+
+#define AON_REG_PCK600_VPON_REG4X_RTC_QCH_BUSY_FLAG1_Pos                                                                 9U
+#define AON_REG_PCK600_VPON_REG4X_RTC_QCH_BUSY_FLAG1_Msk                                                                 (0x1UL << AON_REG_PCK600_VPON_REG4X_RTC_QCH_BUSY_FLAG1_Pos)
+
+#define AON_REG_PCK600_VPON_REG4X_RAP_BUS_QCH_BUSY_FLAG1_Pos                                                             10U
+#define AON_REG_PCK600_VPON_REG4X_RAP_BUS_QCH_BUSY_FLAG1_Msk                                                             (0x1UL << AON_REG_PCK600_VPON_REG4X_RAP_BUS_QCH_BUSY_FLAG1_Pos)
+
+#define AON_REG_PCK600_VPON_REG4X_RAP_QCH_BUSY_FLAG1_Pos                                                                 11U
+#define AON_REG_PCK600_VPON_REG4X_RAP_QCH_BUSY_FLAG1_Msk                                                                 (0x1UL << AON_REG_PCK600_VPON_REG4X_RAP_QCH_BUSY_FLAG1_Pos)
+
+#define AON_REG_PCK600_VPON_REG4X_LPQDEC_BUS_QCH_BUSY_FLAG1_Pos                                                          12U
+#define AON_REG_PCK600_VPON_REG4X_LPQDEC_BUS_QCH_BUSY_FLAG1_Msk                                                          (0x1UL << AON_REG_PCK600_VPON_REG4X_LPQDEC_BUS_QCH_BUSY_FLAG1_Pos)
+
+#define AON_REG_PCK600_VPON_REG4X_LPQDEC_QCH_BUSY_FLAG1_Pos                                                              13U
+#define AON_REG_PCK600_VPON_REG4X_LPQDEC_QCH_BUSY_FLAG1_Msk                                                              (0x1UL << AON_REG_PCK600_VPON_REG4X_LPQDEC_QCH_BUSY_FLAG1_Pos)
+
+#define AON_REG_PCK600_VPON_REG4X_LPPWM_QCH_BUSY_FLAG1_Pos                                                               14U
+#define AON_REG_PCK600_VPON_REG4X_LPPWM_QCH_BUSY_FLAG1_Msk                                                               (0x1UL << AON_REG_PCK600_VPON_REG4X_LPPWM_QCH_BUSY_FLAG1_Pos)
+
+#define AON_REG_PCK600_VPON_REG4X_LPC_BUS_QCH_BUSY_FLAG1_Pos                                                             15U
+#define AON_REG_PCK600_VPON_REG4X_LPC_BUS_QCH_BUSY_FLAG1_Msk                                                             (0x1UL << AON_REG_PCK600_VPON_REG4X_LPC_BUS_QCH_BUSY_FLAG1_Pos)
+
+#define AON_REG_PCK600_VPON_REG4X_LPC_QCH_BUSY_FLAG1_Pos                                                                 16U
+#define AON_REG_PCK600_VPON_REG4X_LPC_QCH_BUSY_FLAG1_Msk                                                                 (0x1UL << AON_REG_PCK600_VPON_REG4X_LPC_QCH_BUSY_FLAG1_Pos)
+
+#define AON_REG_PCK600_VPON_REG4X_GRTC_BUS_QCH_BUSY_FLAG1_Pos                                                            17U
+#define AON_REG_PCK600_VPON_REG4X_GRTC_BUS_QCH_BUSY_FLAG1_Msk                                                            (0x1UL << AON_REG_PCK600_VPON_REG4X_GRTC_BUS_QCH_BUSY_FLAG1_Pos)
+
+#define AON_REG_PCK600_VPON_REG4X_GRTC_QCH_BUSY_FLAG1_Pos                                                                18U
+#define AON_REG_PCK600_VPON_REG4X_GRTC_QCH_BUSY_FLAG1_Msk                                                                (0x1UL << AON_REG_PCK600_VPON_REG4X_GRTC_QCH_BUSY_FLAG1_Pos)
+
+#define AON_REG_PCK600_VPON_REG4X_BTMAC_32K_QCH_BUSY_FLAG1_Pos                                                           19U
+#define AON_REG_PCK600_VPON_REG4X_BTMAC_32K_QCH_BUSY_FLAG1_Msk                                                           (0x1UL << AON_REG_PCK600_VPON_REG4X_BTMAC_32K_QCH_BUSY_FLAG1_Pos)
+
+#define AON_REG_PCK600_VPON_REG4X_RESERVED_Pos                                                                           20U
+#define AON_REG_PCK600_VPON_REG4X_RESERVED_Msk                                                                           (0xFFFUL << AON_REG_PCK600_VPON_REG4X_RESERVED_Pos)
+
+/* 0x8E0    0x4000_08e0
+    0       R       PSCM_OSC80_QCH_BUSY_FLAG0                                   1'b1
+    1       R       PCSM_XTAL40_QCH_BUSY_FLAG0                                  1'b1
+    2       R       PCSM_PPU_VCORE_QCH_BUSY_FLAG0                               1'b1
+    3       R       PCSM_PLL1_QCH_BUSY_FLAG0                                    1'b1
+    4       R       PCSM_OSC80_CG_QCH_BUSY_FLAG0                                1'b1
+    5       R       WDT_BUS_QCH_BUSY_FLAG0                                      1'b1
+    6       R       WDT_QCH_BUSY_FLAG0                                          1'b1
+    7       R       SCH_PLN_QCH_BUSY_FLAG0                                      1'b1
+    8       R       RTC_BUS_QCH_BUSY_FLAG0                                      1'b1
+    9       R       RTC_QCH_BUSY_FLAG0                                          1'b1
+    10      R       RAP_BUS_QCH_BUSY_FLAG0                                      1'b1
+    11      R       RAP_QCH_BUSY_FLAG0                                          1'b1
+    12      R       LPQDEC_BUS_QCH_BUSY_FLAG0                                   1'b1
+    13      R       LPQDEC_QCH_BUSY_FLAG0                                       1'b1
+    14      R       LPPWM_QCH_BUSY_FLAG0                                        1'b1
+    15      R       LPC_BUS_QCH_BUSY_FLAG0                                      1'b1
+    16      R       LPC_QCH_BUSY_FLAG0                                          1'b1
+    17      R       GRTC_BUS_QCH_BUSY_FLAG0                                     1'b1
+    18      R       GRTC_QCH_BUSY_FLAG0                                         1'b1
+    19      R       BTMAC_32K_QCH_BUSY_FLAG0                                    1'b1
+    30:20   R       RESERVED                                                    11'b0
+    31      R/W1C   PON_DBG_QCH_BUSY_FLAG_W1C                                   1'b0
+ */
+typedef union _AON_REG_PCK600_VPON_REG5X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t PSCM_OSC80_QCH_BUSY_FLAG0: 1;
+        uint32_t PCSM_XTAL40_QCH_BUSY_FLAG0: 1;
+        uint32_t PCSM_PPU_VCORE_QCH_BUSY_FLAG0: 1;
+        uint32_t PCSM_PLL1_QCH_BUSY_FLAG0: 1;
+        uint32_t PCSM_OSC80_CG_QCH_BUSY_FLAG0: 1;
+        uint32_t WDT_BUS_QCH_BUSY_FLAG0: 1;
+        uint32_t WDT_QCH_BUSY_FLAG0: 1;
+        uint32_t SCH_PLN_QCH_BUSY_FLAG0: 1;
+        uint32_t RTC_BUS_QCH_BUSY_FLAG0: 1;
+        uint32_t RTC_QCH_BUSY_FLAG0: 1;
+        uint32_t RAP_BUS_QCH_BUSY_FLAG0: 1;
+        uint32_t RAP_QCH_BUSY_FLAG0: 1;
+        uint32_t LPQDEC_BUS_QCH_BUSY_FLAG0: 1;
+        uint32_t LPQDEC_QCH_BUSY_FLAG0: 1;
+        uint32_t LPPWM_QCH_BUSY_FLAG0: 1;
+        uint32_t LPC_BUS_QCH_BUSY_FLAG0: 1;
+        uint32_t LPC_QCH_BUSY_FLAG0: 1;
+        uint32_t GRTC_BUS_QCH_BUSY_FLAG0: 1;
+        uint32_t GRTC_QCH_BUSY_FLAG0: 1;
+        uint32_t BTMAC_32K_QCH_BUSY_FLAG0: 1;
+        uint32_t RESERVED: 11;
+        uint32_t PON_DBG_QCH_BUSY_FLAG_W1C: 1;
+    };
+} AON_REG_PCK600_VPON_REG5X_TYPE;
+
+/*0x4000_08e0 AON_REG_PCK600_VPON_REG5X*/
+#define AON_REG_PCK600_VPON_REG5X_PSCM_OSC80_QCH_BUSY_FLAG0_Pos                                                          0U
+#define AON_REG_PCK600_VPON_REG5X_PSCM_OSC80_QCH_BUSY_FLAG0_Msk                                                          (0x1UL << AON_REG_PCK600_VPON_REG5X_PSCM_OSC80_QCH_BUSY_FLAG0_Pos)
+
+#define AON_REG_PCK600_VPON_REG5X_PCSM_XTAL40_QCH_BUSY_FLAG0_Pos                                                         1U
+#define AON_REG_PCK600_VPON_REG5X_PCSM_XTAL40_QCH_BUSY_FLAG0_Msk                                                         (0x1UL << AON_REG_PCK600_VPON_REG5X_PCSM_XTAL40_QCH_BUSY_FLAG0_Pos)
+
+#define AON_REG_PCK600_VPON_REG5X_PCSM_PPU_VCORE_QCH_BUSY_FLAG0_Pos                                                      2U
+#define AON_REG_PCK600_VPON_REG5X_PCSM_PPU_VCORE_QCH_BUSY_FLAG0_Msk                                                      (0x1UL << AON_REG_PCK600_VPON_REG5X_PCSM_PPU_VCORE_QCH_BUSY_FLAG0_Pos)
+
+#define AON_REG_PCK600_VPON_REG5X_PCSM_PLL1_QCH_BUSY_FLAG0_Pos                                                           3U
+#define AON_REG_PCK600_VPON_REG5X_PCSM_PLL1_QCH_BUSY_FLAG0_Msk                                                           (0x1UL << AON_REG_PCK600_VPON_REG5X_PCSM_PLL1_QCH_BUSY_FLAG0_Pos)
+
+#define AON_REG_PCK600_VPON_REG5X_PCSM_OSC80_CG_QCH_BUSY_FLAG0_Pos                                                       4U
+#define AON_REG_PCK600_VPON_REG5X_PCSM_OSC80_CG_QCH_BUSY_FLAG0_Msk                                                       (0x1UL << AON_REG_PCK600_VPON_REG5X_PCSM_OSC80_CG_QCH_BUSY_FLAG0_Pos)
+
+#define AON_REG_PCK600_VPON_REG5X_WDT_BUS_QCH_BUSY_FLAG0_Pos                                                             5U
+#define AON_REG_PCK600_VPON_REG5X_WDT_BUS_QCH_BUSY_FLAG0_Msk                                                             (0x1UL << AON_REG_PCK600_VPON_REG5X_WDT_BUS_QCH_BUSY_FLAG0_Pos)
+
+#define AON_REG_PCK600_VPON_REG5X_WDT_QCH_BUSY_FLAG0_Pos                                                                 6U
+#define AON_REG_PCK600_VPON_REG5X_WDT_QCH_BUSY_FLAG0_Msk                                                                 (0x1UL << AON_REG_PCK600_VPON_REG5X_WDT_QCH_BUSY_FLAG0_Pos)
+
+#define AON_REG_PCK600_VPON_REG5X_SCH_PLN_QCH_BUSY_FLAG0_Pos                                                             7U
+#define AON_REG_PCK600_VPON_REG5X_SCH_PLN_QCH_BUSY_FLAG0_Msk                                                             (0x1UL << AON_REG_PCK600_VPON_REG5X_SCH_PLN_QCH_BUSY_FLAG0_Pos)
+
+#define AON_REG_PCK600_VPON_REG5X_RTC_BUS_QCH_BUSY_FLAG0_Pos                                                             8U
+#define AON_REG_PCK600_VPON_REG5X_RTC_BUS_QCH_BUSY_FLAG0_Msk                                                             (0x1UL << AON_REG_PCK600_VPON_REG5X_RTC_BUS_QCH_BUSY_FLAG0_Pos)
+
+#define AON_REG_PCK600_VPON_REG5X_RTC_QCH_BUSY_FLAG0_Pos                                                                 9U
+#define AON_REG_PCK600_VPON_REG5X_RTC_QCH_BUSY_FLAG0_Msk                                                                 (0x1UL << AON_REG_PCK600_VPON_REG5X_RTC_QCH_BUSY_FLAG0_Pos)
+
+#define AON_REG_PCK600_VPON_REG5X_RAP_BUS_QCH_BUSY_FLAG0_Pos                                                             10U
+#define AON_REG_PCK600_VPON_REG5X_RAP_BUS_QCH_BUSY_FLAG0_Msk                                                             (0x1UL << AON_REG_PCK600_VPON_REG5X_RAP_BUS_QCH_BUSY_FLAG0_Pos)
+
+#define AON_REG_PCK600_VPON_REG5X_RAP_QCH_BUSY_FLAG0_Pos                                                                 11U
+#define AON_REG_PCK600_VPON_REG5X_RAP_QCH_BUSY_FLAG0_Msk                                                                 (0x1UL << AON_REG_PCK600_VPON_REG5X_RAP_QCH_BUSY_FLAG0_Pos)
+
+#define AON_REG_PCK600_VPON_REG5X_LPQDEC_BUS_QCH_BUSY_FLAG0_Pos                                                          12U
+#define AON_REG_PCK600_VPON_REG5X_LPQDEC_BUS_QCH_BUSY_FLAG0_Msk                                                          (0x1UL << AON_REG_PCK600_VPON_REG5X_LPQDEC_BUS_QCH_BUSY_FLAG0_Pos)
+
+#define AON_REG_PCK600_VPON_REG5X_LPQDEC_QCH_BUSY_FLAG0_Pos                                                              13U
+#define AON_REG_PCK600_VPON_REG5X_LPQDEC_QCH_BUSY_FLAG0_Msk                                                              (0x1UL << AON_REG_PCK600_VPON_REG5X_LPQDEC_QCH_BUSY_FLAG0_Pos)
+
+#define AON_REG_PCK600_VPON_REG5X_LPPWM_QCH_BUSY_FLAG0_Pos                                                               14U
+#define AON_REG_PCK600_VPON_REG5X_LPPWM_QCH_BUSY_FLAG0_Msk                                                               (0x1UL << AON_REG_PCK600_VPON_REG5X_LPPWM_QCH_BUSY_FLAG0_Pos)
+
+#define AON_REG_PCK600_VPON_REG5X_LPC_BUS_QCH_BUSY_FLAG0_Pos                                                             15U
+#define AON_REG_PCK600_VPON_REG5X_LPC_BUS_QCH_BUSY_FLAG0_Msk                                                             (0x1UL << AON_REG_PCK600_VPON_REG5X_LPC_BUS_QCH_BUSY_FLAG0_Pos)
+
+#define AON_REG_PCK600_VPON_REG5X_LPC_QCH_BUSY_FLAG0_Pos                                                                 16U
+#define AON_REG_PCK600_VPON_REG5X_LPC_QCH_BUSY_FLAG0_Msk                                                                 (0x1UL << AON_REG_PCK600_VPON_REG5X_LPC_QCH_BUSY_FLAG0_Pos)
+
+#define AON_REG_PCK600_VPON_REG5X_GRTC_BUS_QCH_BUSY_FLAG0_Pos                                                            17U
+#define AON_REG_PCK600_VPON_REG5X_GRTC_BUS_QCH_BUSY_FLAG0_Msk                                                            (0x1UL << AON_REG_PCK600_VPON_REG5X_GRTC_BUS_QCH_BUSY_FLAG0_Pos)
+
+#define AON_REG_PCK600_VPON_REG5X_GRTC_QCH_BUSY_FLAG0_Pos                                                                18U
+#define AON_REG_PCK600_VPON_REG5X_GRTC_QCH_BUSY_FLAG0_Msk                                                                (0x1UL << AON_REG_PCK600_VPON_REG5X_GRTC_QCH_BUSY_FLAG0_Pos)
+
+#define AON_REG_PCK600_VPON_REG5X_BTMAC_32K_QCH_BUSY_FLAG0_Pos                                                           19U
+#define AON_REG_PCK600_VPON_REG5X_BTMAC_32K_QCH_BUSY_FLAG0_Msk                                                           (0x1UL << AON_REG_PCK600_VPON_REG5X_BTMAC_32K_QCH_BUSY_FLAG0_Pos)
+
+#define AON_REG_PCK600_VPON_REG5X_RESERVED_Pos                                                                           20U
+#define AON_REG_PCK600_VPON_REG5X_RESERVED_Msk                                                                           (0x7FFUL << AON_REG_PCK600_VPON_REG5X_RESERVED_Pos)
+
+#define AON_REG_PCK600_VPON_REG5X_PON_DBG_QCH_BUSY_FLAG_W1C_Pos                                                          31U
+#define AON_REG_PCK600_VPON_REG5X_PON_DBG_QCH_BUSY_FLAG_W1C_Msk                                                          (0x1UL << AON_REG_PCK600_VPON_REG5X_PON_DBG_QCH_BUSY_FLAG_W1C_Pos)
+
+/* 0x8E4    0x4000_08e4
+    11:0    R       VCORE_ON_MODE_CNT_VALUE                                     12'b0
+    14:12   R       RESERVED_1                                                  3'b0
+    15      R       VCORE_ON_MODE_CNT_CLAMP_FLAG                                1'b0
+    30:16   R       RESERVED                                                    15'b0
+    31      R/W1C   VCORE_ON_MODE_CNT_W1C                                       1'b0
+ */
+typedef union _AON_REG_PCK600_VPON_REG6X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t VCORE_ON_MODE_CNT_VALUE: 12;
+        uint32_t RESERVED_1: 3;
+        uint32_t VCORE_ON_MODE_CNT_CLAMP_FLAG: 1;
+        uint32_t RESERVED: 15;
+        uint32_t VCORE_ON_MODE_CNT_W1C: 1;
+    };
+} AON_REG_PCK600_VPON_REG6X_TYPE;
+
+/*0x4000_08e4 AON_REG_PCK600_VPON_REG6X*/
+#define AON_REG_PCK600_VPON_REG6X_VCORE_ON_MODE_CNT_VALUE_Pos                                                            0U
+#define AON_REG_PCK600_VPON_REG6X_VCORE_ON_MODE_CNT_VALUE_Msk                                                            (0xFFFUL << AON_REG_PCK600_VPON_REG6X_VCORE_ON_MODE_CNT_VALUE_Pos)
+
+#define AON_REG_PCK600_VPON_REG6X_RESERVED_1_Pos                                                                         12U
+#define AON_REG_PCK600_VPON_REG6X_RESERVED_1_Msk                                                                         (0x7UL << AON_REG_PCK600_VPON_REG6X_RESERVED_1_Pos)
+
+#define AON_REG_PCK600_VPON_REG6X_VCORE_ON_MODE_CNT_CLAMP_FLAG_Pos                                                       15U
+#define AON_REG_PCK600_VPON_REG6X_VCORE_ON_MODE_CNT_CLAMP_FLAG_Msk                                                       (0x1UL << AON_REG_PCK600_VPON_REG6X_VCORE_ON_MODE_CNT_CLAMP_FLAG_Pos)
+
+#define AON_REG_PCK600_VPON_REG6X_RESERVED_Pos                                                                           16U
+#define AON_REG_PCK600_VPON_REG6X_RESERVED_Msk                                                                           (0x7FFFUL << AON_REG_PCK600_VPON_REG6X_RESERVED_Pos)
+
+#define AON_REG_PCK600_VPON_REG6X_VCORE_ON_MODE_CNT_W1C_Pos                                                              31U
+#define AON_REG_PCK600_VPON_REG6X_VCORE_ON_MODE_CNT_W1C_Msk                                                              (0x1UL << AON_REG_PCK600_VPON_REG6X_VCORE_ON_MODE_CNT_W1C_Pos)
+
+/* 0x718    0x4000_0718
+    0       R/W     ADDA_SW_LDO2PWRCUT                                          1'b1
+    1       R/W     ADDA_POW_LDO                                                1'b1
+    2       R/W     ADDA_LDO_VPULSE                                             1'b0
+    6:3     R/W     ADDA_LDO_SW                                                 4'b0110
+    7       R/W     ADDA_DOUBLE_OP_I                                            1'b0
+    8       R/W     RESERVED_6                                                  1'b1
+    9       R/W     ADDA_LDO_CPT_SW                                             1'b0
+    10      R/W     RESERVED_5                                                  1'b0
+    11      R/W     RESERVED_4                                                  1'b0
+    12      R/W     RESERVED_3                                                  1'b0
+    15:13   R/W     RESERVED_2                                                  3'b100
+    16      R       RESERVED_1                                                  1'b0
+    31:17   R       RESERVED                                                    16'b0
+ */
+typedef union _AON_BT_ANAPAR_LDO_ADDA_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t ADDA_SW_LDO2PWRCUT: 1;
+        uint32_t ADDA_POW_LDO: 1;
+        uint32_t ADDA_LDO_VPULSE: 1;
+        uint32_t ADDA_LDO_SW: 4;
+        uint32_t ADDA_DOUBLE_OP_I: 1;
+        uint32_t RESERVED_6: 1;
+        uint32_t ADDA_LDO_CPT_SW: 1;
+        uint32_t RESERVED_5: 1;
+        uint32_t RESERVED_4: 1;
+        uint32_t RESERVED_3: 1;
+        uint32_t RESERVED_2: 3;
+        uint32_t RESERVED_1: 1;
+        uint32_t RESERVED: 15;
+    };
+} AON_BT_ANAPAR_LDO_ADDA_TYPE;
+
+/*0x4000_0718 AON_BT_ANAPAR_LDO_ADDA*/
+#define AON_BT_ANAPAR_LDO_ADDA_ADDA_SW_LDO2PWRCUT_Pos                                                                    0U
+#define AON_BT_ANAPAR_LDO_ADDA_ADDA_SW_LDO2PWRCUT_Msk                                                                    (0x1UL << AON_BT_ANAPAR_LDO_ADDA_ADDA_SW_LDO2PWRCUT_Pos)
+
+#define AON_BT_ANAPAR_LDO_ADDA_ADDA_POW_LDO_Pos                                                                          1U
+#define AON_BT_ANAPAR_LDO_ADDA_ADDA_POW_LDO_Msk                                                                          (0x1UL << AON_BT_ANAPAR_LDO_ADDA_ADDA_POW_LDO_Pos)
+
+#define AON_BT_ANAPAR_LDO_ADDA_ADDA_LDO_VPULSE_Pos                                                                       2U
+#define AON_BT_ANAPAR_LDO_ADDA_ADDA_LDO_VPULSE_Msk                                                                       (0x1UL << AON_BT_ANAPAR_LDO_ADDA_ADDA_LDO_VPULSE_Pos)
+
+#define AON_BT_ANAPAR_LDO_ADDA_ADDA_LDO_SW_Pos                                                                           3U
+#define AON_BT_ANAPAR_LDO_ADDA_ADDA_LDO_SW_Msk                                                                           (0xFUL << AON_BT_ANAPAR_LDO_ADDA_ADDA_LDO_SW_Pos)
+
+#define AON_BT_ANAPAR_LDO_ADDA_ADDA_DOUBLE_OP_I_Pos                                                                      7U
+#define AON_BT_ANAPAR_LDO_ADDA_ADDA_DOUBLE_OP_I_Msk                                                                      (0x1UL << AON_BT_ANAPAR_LDO_ADDA_ADDA_DOUBLE_OP_I_Pos)
+
+#define AON_BT_ANAPAR_LDO_ADDA_RESERVED_6_Pos                                                                            8U
+#define AON_BT_ANAPAR_LDO_ADDA_RESERVED_6_Msk                                                                            (0x1UL << AON_BT_ANAPAR_LDO_ADDA_RESERVED_6_Pos)
+
+#define AON_BT_ANAPAR_LDO_ADDA_ADDA_LDO_CPT_SW_Pos                                                                       9U
+#define AON_BT_ANAPAR_LDO_ADDA_ADDA_LDO_CPT_SW_Msk                                                                       (0x1UL << AON_BT_ANAPAR_LDO_ADDA_ADDA_LDO_CPT_SW_Pos)
+
+#define AON_BT_ANAPAR_LDO_ADDA_RESERVED_5_Pos                                                                            10U
+#define AON_BT_ANAPAR_LDO_ADDA_RESERVED_5_Msk                                                                            (0x1UL << AON_BT_ANAPAR_LDO_ADDA_RESERVED_5_Pos)
+
+#define AON_BT_ANAPAR_LDO_ADDA_RESERVED_4_Pos                                                                            11U
+#define AON_BT_ANAPAR_LDO_ADDA_RESERVED_4_Msk                                                                            (0x1UL << AON_BT_ANAPAR_LDO_ADDA_RESERVED_4_Pos)
+
+#define AON_BT_ANAPAR_LDO_ADDA_RESERVED_3_Pos                                                                            12U
+#define AON_BT_ANAPAR_LDO_ADDA_RESERVED_3_Msk                                                                            (0x1UL << AON_BT_ANAPAR_LDO_ADDA_RESERVED_3_Pos)
+
+#define AON_BT_ANAPAR_LDO_ADDA_RESERVED_2_Pos                                                                            13U
+#define AON_BT_ANAPAR_LDO_ADDA_RESERVED_2_Msk                                                                            (0x7UL << AON_BT_ANAPAR_LDO_ADDA_RESERVED_2_Pos)
+
+#define AON_BT_ANAPAR_LDO_ADDA_RESERVED_1_Pos                                                                            16U
+#define AON_BT_ANAPAR_LDO_ADDA_RESERVED_1_Msk                                                                            (0x1UL << AON_BT_ANAPAR_LDO_ADDA_RESERVED_1_Pos)
+
+#define AON_BT_ANAPAR_LDO_ADDA_RESERVED_Pos                                                                              17U
+#define AON_BT_ANAPAR_LDO_ADDA_RESERVED_Msk                                                                              (0x7FFFUL << AON_BT_ANAPAR_LDO_ADDA_RESERVED_Pos)
+
+/* 0x71C    0x4000_071c
+    0       R/W     RESERVED_6                                                  1'b0
+    1       R/W     RESERVED_5                                                  1'b0
+    2       R/W     RESERVED_4                                                  1'b0
+    6:3     R/W     RESERVED_3                                                  4'b0000
+    7       R/W     RESERVED_2                                                  1'b0
+    8       R/W     RESERVED_1                                                  1'b0
+    31:9    R/W     RESERVED                                                    23'h0
+ */
+typedef union _AON_REG_BT_ANAPAR_LDO_IQMDA_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED_6: 1;
+        uint32_t RESERVED_5: 1;
+        uint32_t RESERVED_4: 1;
+        uint32_t RESERVED_3: 4;
+        uint32_t RESERVED_2: 1;
+        uint32_t RESERVED_1: 1;
+        uint32_t RESERVED: 23;
+    };
+} AON_REG_BT_ANAPAR_LDO_IQMDA_TYPE;
+
+/*0x4000_071c AON_REG_BT_ANAPAR_LDO_IQMDA*/
+#define AON_REG_BT_ANAPAR_LDO_IQMDA_RESERVED_6_Pos                                                                       0U
+#define AON_REG_BT_ANAPAR_LDO_IQMDA_RESERVED_6_Msk                                                                       (0x1UL << AON_REG_BT_ANAPAR_LDO_IQMDA_RESERVED_6_Pos)
+
+#define AON_REG_BT_ANAPAR_LDO_IQMDA_RESERVED_5_Pos                                                                       1U
+#define AON_REG_BT_ANAPAR_LDO_IQMDA_RESERVED_5_Msk                                                                       (0x1UL << AON_REG_BT_ANAPAR_LDO_IQMDA_RESERVED_5_Pos)
+
+#define AON_REG_BT_ANAPAR_LDO_IQMDA_RESERVED_4_Pos                                                                       2U
+#define AON_REG_BT_ANAPAR_LDO_IQMDA_RESERVED_4_Msk                                                                       (0x1UL << AON_REG_BT_ANAPAR_LDO_IQMDA_RESERVED_4_Pos)
+
+#define AON_REG_BT_ANAPAR_LDO_IQMDA_RESERVED_3_Pos                                                                       3U
+#define AON_REG_BT_ANAPAR_LDO_IQMDA_RESERVED_3_Msk                                                                       (0xFUL << AON_REG_BT_ANAPAR_LDO_IQMDA_RESERVED_3_Pos)
+
+#define AON_REG_BT_ANAPAR_LDO_IQMDA_RESERVED_2_Pos                                                                       7U
+#define AON_REG_BT_ANAPAR_LDO_IQMDA_RESERVED_2_Msk                                                                       (0x1UL << AON_REG_BT_ANAPAR_LDO_IQMDA_RESERVED_2_Pos)
+
+#define AON_REG_BT_ANAPAR_LDO_IQMDA_RESERVED_1_Pos                                                                       8U
+#define AON_REG_BT_ANAPAR_LDO_IQMDA_RESERVED_1_Msk                                                                       (0x1UL << AON_REG_BT_ANAPAR_LDO_IQMDA_RESERVED_1_Pos)
+
+#define AON_REG_BT_ANAPAR_LDO_IQMDA_RESERVED_Pos                                                                         9U
+#define AON_REG_BT_ANAPAR_LDO_IQMDA_RESERVED_Msk                                                                         (0x7FFFFFUL << AON_REG_BT_ANAPAR_LDO_IQMDA_RESERVED_Pos)
+
+/* 0x720    0x4000_0720
+    0       R/W     SW_LDO2PWRCUT_TPMK_ADC                                      1'b1
+    1       R/W     DOUBLE_OP_I                                                 1'b0
+    2       R/W     LDO_VPULSE                                                  1'b0
+    6:3     R/W     LDO_SW                                                      4'b0110
+    7       R/W     POW_LDO_TPMK_ADC                                            1'b1
+    8       R/W     RESERVED_1                                                  1'b0
+    9       R/W     EN33_LDO_CPT_SW                                             1'b0
+    31:10   R/W     RESERVED                                                    23'h0
+ */
+typedef union _AON_BT_TPMK_ADC_LDO_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t SW_LDO2PWRCUT_TPMK_ADC: 1;
+        uint32_t DOUBLE_OP_I: 1;
+        uint32_t LDO_VPULSE: 1;
+        uint32_t LDO_SW: 4;
+        uint32_t POW_LDO_TPMK_ADC: 1;
+        uint32_t RESERVED_1: 1;
+        uint32_t EN33_LDO_CPT_SW: 1;
+        uint32_t RESERVED: 22;
+    };
+} AON_BT_TPMK_ADC_LDO_TYPE;
+
+/*0x4000_0720 AON_BT_TPMK_ADC_LDO*/
+#define AON_BT_TPMK_ADC_LDO_SW_LDO2PWRCUT_TPMK_ADC_Pos                                                                   0U
+#define AON_BT_TPMK_ADC_LDO_SW_LDO2PWRCUT_TPMK_ADC_Msk                                                                   (0x1UL << AON_BT_TPMK_ADC_LDO_SW_LDO2PWRCUT_TPMK_ADC_Pos)
+
+#define AON_BT_TPMK_ADC_LDO_DOUBLE_OP_I_Pos                                                                              1U
+#define AON_BT_TPMK_ADC_LDO_DOUBLE_OP_I_Msk                                                                              (0x1UL << AON_BT_TPMK_ADC_LDO_DOUBLE_OP_I_Pos)
+
+#define AON_BT_TPMK_ADC_LDO_LDO_VPULSE_Pos                                                                               2U
+#define AON_BT_TPMK_ADC_LDO_LDO_VPULSE_Msk                                                                               (0x1UL << AON_BT_TPMK_ADC_LDO_LDO_VPULSE_Pos)
+
+#define AON_BT_TPMK_ADC_LDO_LDO_SW_Pos                                                                                   3U
+#define AON_BT_TPMK_ADC_LDO_LDO_SW_Msk                                                                                   (0xFUL << AON_BT_TPMK_ADC_LDO_LDO_SW_Pos)
+
+#define AON_BT_TPMK_ADC_LDO_POW_LDO_TPMK_ADC_Pos                                                                         7U
+#define AON_BT_TPMK_ADC_LDO_POW_LDO_TPMK_ADC_Msk                                                                         (0x1UL << AON_BT_TPMK_ADC_LDO_POW_LDO_TPMK_ADC_Pos)
+
+#define AON_BT_TPMK_ADC_LDO_RESERVED_1_Pos                                                                               8U
+#define AON_BT_TPMK_ADC_LDO_RESERVED_1_Msk                                                                               (0x1UL << AON_BT_TPMK_ADC_LDO_RESERVED_1_Pos)
+
+#define AON_BT_TPMK_ADC_LDO_EN33_LDO_CPT_SW_Pos                                                                          9U
+#define AON_BT_TPMK_ADC_LDO_EN33_LDO_CPT_SW_Msk                                                                          (0x1UL << AON_BT_TPMK_ADC_LDO_EN33_LDO_CPT_SW_Pos)
+
+#define AON_BT_TPMK_ADC_LDO_RESERVED_Pos                                                                                 10U
+#define AON_BT_TPMK_ADC_LDO_RESERVED_Msk                                                                                 (0x3FFFFFUL << AON_BT_TPMK_ADC_LDO_RESERVED_Pos)
+
+/* 0x9A4    0x4000_09a4
+    7:0     R/W     RESERVED_3                                                  8'h0
+    8       R/W     RESERVED_2                                                  1'b0
+    9       R/W     RESERVED_1                                                  1'b0
+    10      R/W     LOP_PON_PPU_VPON_PCSM_EN_CMP_LQ_VDDANA                      1'b1
+    11      R/W     LOP_PON_PPU_VPON_PCSM_EN_CMP_HQ_VDDANA                      1'b1
+    16:12   R/W     LOP_PON_PPU_VPON_PCSM_SEL_VREF_VDDANA_LQ                    5'b10011
+    24:17   R/W     LOP_PON_PPU_VPON_PCSM_TUNE_VDDANA                           8'b01111010
+    25      R/W     LOP_PON_PPU_VPON_PCSM_POW_VDIV_LQ_VDDANA                    1'b1
+    26      R/W     LOP_PON_PPU_VPON_PCSM_POW_VDIV_HQ_VDDANA                    1'b1
+    27      R/W     LOP_PON_PPU_VPON_PCSM_EN_DMYLOAD_VDDANA                     1'b0
+    28      R/W     LOP_PON_PPU_VPON_PCSM_POW_VDDANA_DET                        1'b1
+    29      R/W     LOP_PON_PPU_VPON_PCSM_ENCCM_OUT_VDDANA                      1'b1
+    30      R/W     RESERVED                                                    1'b1
+    31      R/W     LOP_PON_OSC128K_PCSM_POW_32KOSC                             1'b1
+ */
+typedef union _AON_LOP_PON_CLK_CTRL_OSC128K_OSC10_PCSM_1_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED_3: 8;
+        uint32_t RESERVED_2: 1;
+        uint32_t RESERVED_1: 1;
+        uint32_t LOP_PON_PPU_VPON_PCSM_EN_CMP_LQ_VDDANA: 1;
+        uint32_t LOP_PON_PPU_VPON_PCSM_EN_CMP_HQ_VDDANA: 1;
+        uint32_t LOP_PON_PPU_VPON_PCSM_SEL_VREF_VDDANA_LQ: 5;
+        uint32_t LOP_PON_PPU_VPON_PCSM_TUNE_VDDANA: 8;
+        uint32_t LOP_PON_PPU_VPON_PCSM_POW_VDIV_LQ_VDDANA: 1;
+        uint32_t LOP_PON_PPU_VPON_PCSM_POW_VDIV_HQ_VDDANA: 1;
+        uint32_t LOP_PON_PPU_VPON_PCSM_EN_DMYLOAD_VDDANA: 1;
+        uint32_t LOP_PON_PPU_VPON_PCSM_POW_VDDANA_DET: 1;
+        uint32_t LOP_PON_PPU_VPON_PCSM_ENCCM_OUT_VDDANA: 1;
+        uint32_t RESERVED: 1;
+        uint32_t LOP_PON_OSC128K_PCSM_POW_32KOSC: 1;
+    };
+} AON_LOP_PON_CLK_CTRL_OSC128K_OSC10_PCSM_1_TYPE;
+
+/*0x4000_09a4 AON_LOP_PON_CLK_CTRL_OSC128K_OSC10_PCSM_1*/
+#define AON_LOP_PON_CLK_CTRL_OSC128K_OSC10_PCSM_1_RESERVED_3_Pos                                                         0U
+#define AON_LOP_PON_CLK_CTRL_OSC128K_OSC10_PCSM_1_RESERVED_3_Msk                                                         (0xFFUL << AON_LOP_PON_CLK_CTRL_OSC128K_OSC10_PCSM_1_RESERVED_3_Pos)
+
+#define AON_LOP_PON_CLK_CTRL_OSC128K_OSC10_PCSM_1_RESERVED_2_Pos                                                         8U
+#define AON_LOP_PON_CLK_CTRL_OSC128K_OSC10_PCSM_1_RESERVED_2_Msk                                                         (0x1UL << AON_LOP_PON_CLK_CTRL_OSC128K_OSC10_PCSM_1_RESERVED_2_Pos)
+
+#define AON_LOP_PON_CLK_CTRL_OSC128K_OSC10_PCSM_1_RESERVED_1_Pos                                                         9U
+#define AON_LOP_PON_CLK_CTRL_OSC128K_OSC10_PCSM_1_RESERVED_1_Msk                                                         (0x1UL << AON_LOP_PON_CLK_CTRL_OSC128K_OSC10_PCSM_1_RESERVED_1_Pos)
+
+#define AON_LOP_PON_CLK_CTRL_OSC128K_OSC10_PCSM_1_LOP_PON_PPU_VPON_PCSM_EN_CMP_LQ_VDDANA_Pos                             10U
+#define AON_LOP_PON_CLK_CTRL_OSC128K_OSC10_PCSM_1_LOP_PON_PPU_VPON_PCSM_EN_CMP_LQ_VDDANA_Msk                             (0x1UL << AON_LOP_PON_CLK_CTRL_OSC128K_OSC10_PCSM_1_LOP_PON_PPU_VPON_PCSM_EN_CMP_LQ_VDDANA_Pos)
+
+#define AON_LOP_PON_CLK_CTRL_OSC128K_OSC10_PCSM_1_LOP_PON_PPU_VPON_PCSM_EN_CMP_HQ_VDDANA_Pos                             11U
+#define AON_LOP_PON_CLK_CTRL_OSC128K_OSC10_PCSM_1_LOP_PON_PPU_VPON_PCSM_EN_CMP_HQ_VDDANA_Msk                             (0x1UL << AON_LOP_PON_CLK_CTRL_OSC128K_OSC10_PCSM_1_LOP_PON_PPU_VPON_PCSM_EN_CMP_HQ_VDDANA_Pos)
+
+#define AON_LOP_PON_CLK_CTRL_OSC128K_OSC10_PCSM_1_LOP_PON_PPU_VPON_PCSM_SEL_VREF_VDDANA_LQ_Pos                           12U
+#define AON_LOP_PON_CLK_CTRL_OSC128K_OSC10_PCSM_1_LOP_PON_PPU_VPON_PCSM_SEL_VREF_VDDANA_LQ_Msk                           (0x1FUL << AON_LOP_PON_CLK_CTRL_OSC128K_OSC10_PCSM_1_LOP_PON_PPU_VPON_PCSM_SEL_VREF_VDDANA_LQ_Pos)
+
+#define AON_LOP_PON_CLK_CTRL_OSC128K_OSC10_PCSM_1_LOP_PON_PPU_VPON_PCSM_TUNE_VDDANA_Pos                                  17U
+#define AON_LOP_PON_CLK_CTRL_OSC128K_OSC10_PCSM_1_LOP_PON_PPU_VPON_PCSM_TUNE_VDDANA_Msk                                  (0xFFUL << AON_LOP_PON_CLK_CTRL_OSC128K_OSC10_PCSM_1_LOP_PON_PPU_VPON_PCSM_TUNE_VDDANA_Pos)
+
+#define AON_LOP_PON_CLK_CTRL_OSC128K_OSC10_PCSM_1_LOP_PON_PPU_VPON_PCSM_POW_VDIV_LQ_VDDANA_Pos                           25U
+#define AON_LOP_PON_CLK_CTRL_OSC128K_OSC10_PCSM_1_LOP_PON_PPU_VPON_PCSM_POW_VDIV_LQ_VDDANA_Msk                           (0x1UL << AON_LOP_PON_CLK_CTRL_OSC128K_OSC10_PCSM_1_LOP_PON_PPU_VPON_PCSM_POW_VDIV_LQ_VDDANA_Pos)
+
+#define AON_LOP_PON_CLK_CTRL_OSC128K_OSC10_PCSM_1_LOP_PON_PPU_VPON_PCSM_POW_VDIV_HQ_VDDANA_Pos                           26U
+#define AON_LOP_PON_CLK_CTRL_OSC128K_OSC10_PCSM_1_LOP_PON_PPU_VPON_PCSM_POW_VDIV_HQ_VDDANA_Msk                           (0x1UL << AON_LOP_PON_CLK_CTRL_OSC128K_OSC10_PCSM_1_LOP_PON_PPU_VPON_PCSM_POW_VDIV_HQ_VDDANA_Pos)
+
+#define AON_LOP_PON_CLK_CTRL_OSC128K_OSC10_PCSM_1_LOP_PON_PPU_VPON_PCSM_EN_DMYLOAD_VDDANA_Pos                            27U
+#define AON_LOP_PON_CLK_CTRL_OSC128K_OSC10_PCSM_1_LOP_PON_PPU_VPON_PCSM_EN_DMYLOAD_VDDANA_Msk                            (0x1UL << AON_LOP_PON_CLK_CTRL_OSC128K_OSC10_PCSM_1_LOP_PON_PPU_VPON_PCSM_EN_DMYLOAD_VDDANA_Pos)
+
+#define AON_LOP_PON_CLK_CTRL_OSC128K_OSC10_PCSM_1_LOP_PON_PPU_VPON_PCSM_POW_VDDANA_DET_Pos                               28U
+#define AON_LOP_PON_CLK_CTRL_OSC128K_OSC10_PCSM_1_LOP_PON_PPU_VPON_PCSM_POW_VDDANA_DET_Msk                               (0x1UL << AON_LOP_PON_CLK_CTRL_OSC128K_OSC10_PCSM_1_LOP_PON_PPU_VPON_PCSM_POW_VDDANA_DET_Pos)
+
+#define AON_LOP_PON_CLK_CTRL_OSC128K_OSC10_PCSM_1_LOP_PON_PPU_VPON_PCSM_ENCCM_OUT_VDDANA_Pos                             29U
+#define AON_LOP_PON_CLK_CTRL_OSC128K_OSC10_PCSM_1_LOP_PON_PPU_VPON_PCSM_ENCCM_OUT_VDDANA_Msk                             (0x1UL << AON_LOP_PON_CLK_CTRL_OSC128K_OSC10_PCSM_1_LOP_PON_PPU_VPON_PCSM_ENCCM_OUT_VDDANA_Pos)
+
+#define AON_LOP_PON_CLK_CTRL_OSC128K_OSC10_PCSM_1_RESERVED_Pos                                                           30U
+#define AON_LOP_PON_CLK_CTRL_OSC128K_OSC10_PCSM_1_RESERVED_Msk                                                           (0x1UL << AON_LOP_PON_CLK_CTRL_OSC128K_OSC10_PCSM_1_RESERVED_Pos)
+
+#define AON_LOP_PON_CLK_CTRL_OSC128K_OSC10_PCSM_1_LOP_PON_OSC128K_PCSM_POW_32KOSC_Pos                                    31U
+#define AON_LOP_PON_CLK_CTRL_OSC128K_OSC10_PCSM_1_LOP_PON_OSC128K_PCSM_POW_32KOSC_Msk                                    (0x1UL << AON_LOP_PON_CLK_CTRL_OSC128K_OSC10_PCSM_1_LOP_PON_OSC128K_PCSM_POW_32KOSC_Pos)
+
+/* 0x9A8    0x4000_09a8
+    7:0     R/W     RESERVED                                                    8'h0
+    11:8    R/W     LOP_PON_OSC10_PON_PCSM_1_DELAY                              4'b0000
+    15:12   R/W     LOP_PON_OSC10_PCSM_PWR_DELAY                                4'b0000
+    19:16   R/W     LOP_PON_OSC10_PCSM_VDDANA_4_DELAY                           4'b0000
+    23:20   R/W     LOP_PON_OSC10_PCSM_VDDANA_3_DELAY                           4'b0000
+    27:24   R/W     LOP_PON_OSC10_PCSM_VDDANA_2_DELAY                           4'b0000
+    31:28   R/W     LOP_PON_OSC10_PCSM_VDDANA_DELAY                             4'b0000
+ */
+typedef union _AON_LOP_PON_CLK_CTRL_OSC128K_OSC10_PCSM_2_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED: 8;
+        uint32_t LOP_PON_OSC10_PON_PCSM_1_DELAY: 4;
+        uint32_t LOP_PON_OSC10_PCSM_PWR_DELAY: 4;
+        uint32_t LOP_PON_OSC10_PCSM_VDDANA_4_DELAY: 4;
+        uint32_t LOP_PON_OSC10_PCSM_VDDANA_3_DELAY: 4;
+        uint32_t LOP_PON_OSC10_PCSM_VDDANA_2_DELAY: 4;
+        uint32_t LOP_PON_OSC10_PCSM_VDDANA_DELAY: 4;
+    };
+} AON_LOP_PON_CLK_CTRL_OSC128K_OSC10_PCSM_2_TYPE;
+
+/*0x4000_09a8 AON_LOP_PON_CLK_CTRL_OSC128K_OSC10_PCSM_2*/
+#define AON_LOP_PON_CLK_CTRL_OSC128K_OSC10_PCSM_2_RESERVED_Pos                                                           0U
+#define AON_LOP_PON_CLK_CTRL_OSC128K_OSC10_PCSM_2_RESERVED_Msk                                                           (0xFFUL << AON_LOP_PON_CLK_CTRL_OSC128K_OSC10_PCSM_2_RESERVED_Pos)
+
+#define AON_LOP_PON_CLK_CTRL_OSC128K_OSC10_PCSM_2_LOP_PON_OSC10_PON_PCSM_1_DELAY_Pos                                     8U
+#define AON_LOP_PON_CLK_CTRL_OSC128K_OSC10_PCSM_2_LOP_PON_OSC10_PON_PCSM_1_DELAY_Msk                                     (0xFUL << AON_LOP_PON_CLK_CTRL_OSC128K_OSC10_PCSM_2_LOP_PON_OSC10_PON_PCSM_1_DELAY_Pos)
+
+#define AON_LOP_PON_CLK_CTRL_OSC128K_OSC10_PCSM_2_LOP_PON_OSC10_PCSM_PWR_DELAY_Pos                                       12U
+#define AON_LOP_PON_CLK_CTRL_OSC128K_OSC10_PCSM_2_LOP_PON_OSC10_PCSM_PWR_DELAY_Msk                                       (0xFUL << AON_LOP_PON_CLK_CTRL_OSC128K_OSC10_PCSM_2_LOP_PON_OSC10_PCSM_PWR_DELAY_Pos)
+
+#define AON_LOP_PON_CLK_CTRL_OSC128K_OSC10_PCSM_2_LOP_PON_OSC10_PCSM_VDDANA_4_DELAY_Pos                                  16U
+#define AON_LOP_PON_CLK_CTRL_OSC128K_OSC10_PCSM_2_LOP_PON_OSC10_PCSM_VDDANA_4_DELAY_Msk                                  (0xFUL << AON_LOP_PON_CLK_CTRL_OSC128K_OSC10_PCSM_2_LOP_PON_OSC10_PCSM_VDDANA_4_DELAY_Pos)
+
+#define AON_LOP_PON_CLK_CTRL_OSC128K_OSC10_PCSM_2_LOP_PON_OSC10_PCSM_VDDANA_3_DELAY_Pos                                  20U
+#define AON_LOP_PON_CLK_CTRL_OSC128K_OSC10_PCSM_2_LOP_PON_OSC10_PCSM_VDDANA_3_DELAY_Msk                                  (0xFUL << AON_LOP_PON_CLK_CTRL_OSC128K_OSC10_PCSM_2_LOP_PON_OSC10_PCSM_VDDANA_3_DELAY_Pos)
+
+#define AON_LOP_PON_CLK_CTRL_OSC128K_OSC10_PCSM_2_LOP_PON_OSC10_PCSM_VDDANA_2_DELAY_Pos                                  24U
+#define AON_LOP_PON_CLK_CTRL_OSC128K_OSC10_PCSM_2_LOP_PON_OSC10_PCSM_VDDANA_2_DELAY_Msk                                  (0xFUL << AON_LOP_PON_CLK_CTRL_OSC128K_OSC10_PCSM_2_LOP_PON_OSC10_PCSM_VDDANA_2_DELAY_Pos)
+
+#define AON_LOP_PON_CLK_CTRL_OSC128K_OSC10_PCSM_2_LOP_PON_OSC10_PCSM_VDDANA_DELAY_Pos                                    28U
+#define AON_LOP_PON_CLK_CTRL_OSC128K_OSC10_PCSM_2_LOP_PON_OSC10_PCSM_VDDANA_DELAY_Msk                                    (0xFUL << AON_LOP_PON_CLK_CTRL_OSC128K_OSC10_PCSM_2_LOP_PON_OSC10_PCSM_VDDANA_DELAY_Pos)
+
+/* 0x9AC    0x4000_09ac
+    0       R/W     LOP_PON_PPU_VPON_PCSM_VDDIO_EN_DISCHG                       1'b0
+    1       R/W     LOP_PON_PPU_VPON_PCSM_VDDIO_EN_PC2                          1'b1
+    2       R/W     LOP_PON_PPU_VPON_PCSM_VDDIO_EN_PC1                          1'b1
+    3       R/W     LOP_PON_PPU_VPON_PCSM_EN_SYNC                               1'b0
+    4       R/W     LOP_PON_PPU_VPON_PCSM_POW_VDIV_LQ_VDDCORE                   1'b1
+    5       R/W     LOP_PON_PPU_VPON_PCSM_POW_VDIV_LQ_HV18                      1'b1
+    6       R/W     LOP_PON_PPU_VPON_PCSM_POW_VDIV_HQ_VDDCORE                   1'b1
+    7       R/W     LOP_PON_PPU_VPON_PCSM_POW_VDIV_HQ_VDDPA                     1'b1
+    8       R/W     LOP_PON_PPU_VPON_PCSM_POW_VDIV_HQ_HV18                      1'b1
+    9       R/W     LOP_PON_PPU_VPON_PCSM_POW_VDIV_HQ_HV25                      1'b1
+    10      R/W     LOP_PON_PPU_VPON_PCSM_REG_ENHQ_REFCMP                       1'b1
+    11      R/W     LOP_PON_PPU_VPON_PCSM_BYP_OPOR_LD                           1'b1
+    12      R/W     LOP_PON_PPU_VPON_PCSM_REG_ENLPM                             1'b0
+    13      R/W     LOP_PON_PPU_VPON_PCSM_REG_ENPCCM                            1'b0
+    14      R/W     LOP_PON_PPU_VPON_PCSM_ENCCM_OUT_VDDCORE                     1'b1
+    15      R/W     LOP_PON_PPU_VPON_PCSM_ENCCM_OUT_VDDPA                       1'b1
+    16      R/W     LOP_PON_PPU_VPON_PCSM_ENCCM_OUT_HV18                        1'b1
+    17      R/W     LOP_PON_PPU_VPON_PCSM_ENCCM_OUT_HV25                        1'b1
+    19:18   R/W     LOP_PON_PPU_VPON_PCSM_ZCDLY_SET                             2'b10
+    20      R/W     LOP_PON_PPU_VPON_PCSM_ENDLY_FOR_K                           1'b1
+    21      R/W     LOP_PON_PPU_VPON_PCSM_BUCK_BOOST_VDDPA_POS_RSTB             1'b1
+    22      R/W     LOP_PON_PPU_VPON_PCSM_BUCK_BOOST_HV18_POS_RSTB              1'b1
+    23      R/W     LOP_PON_PPU_VPON_PCSM_EN_DMYLOAD_VDDCORE                    1'b0
+    24      R/W     LOP_PON_PPU_VPON_PCSM_EN_DMYLOAD_VDDPA                      1'b0
+    25      R/W     LOP_PON_PPU_VPON_PCSM_EN_DMYLOAD_HV18                       1'b0
+    26      R/W     LOP_PON_PPU_VPON_PCSM_EN_DMYLOAD_HV25                       1'b0
+    27      R/W     LOP_PON_PPU_VPON_PCSM_POW_VDDPA_DET                         1'b1
+    28      R/W     LOP_PON_PPU_VPON_PCSM_POW_HV18_DET                          1'b1
+    29      R/W     LOP_PON_PPU_VPON_PCSM_POW_VDDCORE_DET                       1'b1
+    30      R/W     LOP_PON_PPU_VPON_PCSM_POW_VANA_DET                          1'b1
+    31      R/W     LOP_PON_PPU_VPON_PCSM_EN_BIAS_10UA                          1'b1
+ */
+typedef union _AON_LOP_PON_PPU_VPON_PCSM_1_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t LOP_PON_PPU_VPON_PCSM_VDDIO_EN_DISCHG: 1;
+        uint32_t LOP_PON_PPU_VPON_PCSM_VDDIO_EN_PC2: 1;
+        uint32_t LOP_PON_PPU_VPON_PCSM_VDDIO_EN_PC1: 1;
+        uint32_t LOP_PON_PPU_VPON_PCSM_EN_SYNC: 1;
+        uint32_t LOP_PON_PPU_VPON_PCSM_POW_VDIV_LQ_VDDCORE: 1;
+        uint32_t LOP_PON_PPU_VPON_PCSM_POW_VDIV_LQ_HV18: 1;
+        uint32_t LOP_PON_PPU_VPON_PCSM_POW_VDIV_HQ_VDDCORE: 1;
+        uint32_t LOP_PON_PPU_VPON_PCSM_POW_VDIV_HQ_VDDPA: 1;
+        uint32_t LOP_PON_PPU_VPON_PCSM_POW_VDIV_HQ_HV18: 1;
+        uint32_t LOP_PON_PPU_VPON_PCSM_POW_VDIV_HQ_HV25: 1;
+        uint32_t LOP_PON_PPU_VPON_PCSM_REG_ENHQ_REFCMP: 1;
+        uint32_t LOP_PON_PPU_VPON_PCSM_BYP_OPOR_LD: 1;
+        uint32_t LOP_PON_PPU_VPON_PCSM_REG_ENLPM: 1;
+        uint32_t LOP_PON_PPU_VPON_PCSM_REG_ENPCCM: 1;
+        uint32_t LOP_PON_PPU_VPON_PCSM_ENCCM_OUT_VDDCORE: 1;
+        uint32_t LOP_PON_PPU_VPON_PCSM_ENCCM_OUT_VDDPA: 1;
+        uint32_t LOP_PON_PPU_VPON_PCSM_ENCCM_OUT_HV18: 1;
+        uint32_t LOP_PON_PPU_VPON_PCSM_ENCCM_OUT_HV25: 1;
+        uint32_t LOP_PON_PPU_VPON_PCSM_ZCDLY_SET: 2;
+        uint32_t LOP_PON_PPU_VPON_PCSM_ENDLY_FOR_K: 1;
+        uint32_t LOP_PON_PPU_VPON_PCSM_BUCK_BOOST_VDDPA_POS_RSTB: 1;
+        uint32_t LOP_PON_PPU_VPON_PCSM_BUCK_BOOST_HV18_POS_RSTB: 1;
+        uint32_t LOP_PON_PPU_VPON_PCSM_EN_DMYLOAD_VDDCORE: 1;
+        uint32_t LOP_PON_PPU_VPON_PCSM_EN_DMYLOAD_VDDPA: 1;
+        uint32_t LOP_PON_PPU_VPON_PCSM_EN_DMYLOAD_HV18: 1;
+        uint32_t LOP_PON_PPU_VPON_PCSM_EN_DMYLOAD_HV25: 1;
+        uint32_t LOP_PON_PPU_VPON_PCSM_POW_VDDPA_DET: 1;
+        uint32_t LOP_PON_PPU_VPON_PCSM_POW_HV18_DET: 1;
+        uint32_t LOP_PON_PPU_VPON_PCSM_POW_VDDCORE_DET: 1;
+        uint32_t LOP_PON_PPU_VPON_PCSM_POW_VANA_DET: 1;
+        uint32_t LOP_PON_PPU_VPON_PCSM_EN_BIAS_10UA: 1;
+    };
+} AON_LOP_PON_PPU_VPON_PCSM_1_TYPE;
+
+/*0x4000_09ac AON_LOP_PON_PPU_VPON_PCSM_1*/
+#define AON_LOP_PON_PPU_VPON_PCSM_1_LOP_PON_PPU_VPON_PCSM_VDDIO_EN_DISCHG_Pos                                            0U
+#define AON_LOP_PON_PPU_VPON_PCSM_1_LOP_PON_PPU_VPON_PCSM_VDDIO_EN_DISCHG_Msk                                            (0x1UL << AON_LOP_PON_PPU_VPON_PCSM_1_LOP_PON_PPU_VPON_PCSM_VDDIO_EN_DISCHG_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_1_LOP_PON_PPU_VPON_PCSM_VDDIO_EN_PC2_Pos                                               1U
+#define AON_LOP_PON_PPU_VPON_PCSM_1_LOP_PON_PPU_VPON_PCSM_VDDIO_EN_PC2_Msk                                               (0x1UL << AON_LOP_PON_PPU_VPON_PCSM_1_LOP_PON_PPU_VPON_PCSM_VDDIO_EN_PC2_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_1_LOP_PON_PPU_VPON_PCSM_VDDIO_EN_PC1_Pos                                               2U
+#define AON_LOP_PON_PPU_VPON_PCSM_1_LOP_PON_PPU_VPON_PCSM_VDDIO_EN_PC1_Msk                                               (0x1UL << AON_LOP_PON_PPU_VPON_PCSM_1_LOP_PON_PPU_VPON_PCSM_VDDIO_EN_PC1_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_1_LOP_PON_PPU_VPON_PCSM_EN_SYNC_Pos                                                    3U
+#define AON_LOP_PON_PPU_VPON_PCSM_1_LOP_PON_PPU_VPON_PCSM_EN_SYNC_Msk                                                    (0x1UL << AON_LOP_PON_PPU_VPON_PCSM_1_LOP_PON_PPU_VPON_PCSM_EN_SYNC_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_1_LOP_PON_PPU_VPON_PCSM_POW_VDIV_LQ_VDDCORE_Pos                                        4U
+#define AON_LOP_PON_PPU_VPON_PCSM_1_LOP_PON_PPU_VPON_PCSM_POW_VDIV_LQ_VDDCORE_Msk                                        (0x1UL << AON_LOP_PON_PPU_VPON_PCSM_1_LOP_PON_PPU_VPON_PCSM_POW_VDIV_LQ_VDDCORE_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_1_LOP_PON_PPU_VPON_PCSM_POW_VDIV_LQ_HV18_Pos                                           5U
+#define AON_LOP_PON_PPU_VPON_PCSM_1_LOP_PON_PPU_VPON_PCSM_POW_VDIV_LQ_HV18_Msk                                           (0x1UL << AON_LOP_PON_PPU_VPON_PCSM_1_LOP_PON_PPU_VPON_PCSM_POW_VDIV_LQ_HV18_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_1_LOP_PON_PPU_VPON_PCSM_POW_VDIV_HQ_VDDCORE_Pos                                        6U
+#define AON_LOP_PON_PPU_VPON_PCSM_1_LOP_PON_PPU_VPON_PCSM_POW_VDIV_HQ_VDDCORE_Msk                                        (0x1UL << AON_LOP_PON_PPU_VPON_PCSM_1_LOP_PON_PPU_VPON_PCSM_POW_VDIV_HQ_VDDCORE_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_1_LOP_PON_PPU_VPON_PCSM_POW_VDIV_HQ_VDDPA_Pos                                          7U
+#define AON_LOP_PON_PPU_VPON_PCSM_1_LOP_PON_PPU_VPON_PCSM_POW_VDIV_HQ_VDDPA_Msk                                          (0x1UL << AON_LOP_PON_PPU_VPON_PCSM_1_LOP_PON_PPU_VPON_PCSM_POW_VDIV_HQ_VDDPA_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_1_LOP_PON_PPU_VPON_PCSM_POW_VDIV_HQ_HV18_Pos                                           8U
+#define AON_LOP_PON_PPU_VPON_PCSM_1_LOP_PON_PPU_VPON_PCSM_POW_VDIV_HQ_HV18_Msk                                           (0x1UL << AON_LOP_PON_PPU_VPON_PCSM_1_LOP_PON_PPU_VPON_PCSM_POW_VDIV_HQ_HV18_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_1_LOP_PON_PPU_VPON_PCSM_POW_VDIV_HQ_HV25_Pos                                           9U
+#define AON_LOP_PON_PPU_VPON_PCSM_1_LOP_PON_PPU_VPON_PCSM_POW_VDIV_HQ_HV25_Msk                                           (0x1UL << AON_LOP_PON_PPU_VPON_PCSM_1_LOP_PON_PPU_VPON_PCSM_POW_VDIV_HQ_HV25_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_1_LOP_PON_PPU_VPON_PCSM_REG_ENHQ_REFCMP_Pos                                            10U
+#define AON_LOP_PON_PPU_VPON_PCSM_1_LOP_PON_PPU_VPON_PCSM_REG_ENHQ_REFCMP_Msk                                            (0x1UL << AON_LOP_PON_PPU_VPON_PCSM_1_LOP_PON_PPU_VPON_PCSM_REG_ENHQ_REFCMP_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_1_LOP_PON_PPU_VPON_PCSM_BYP_OPOR_LD_Pos                                                11U
+#define AON_LOP_PON_PPU_VPON_PCSM_1_LOP_PON_PPU_VPON_PCSM_BYP_OPOR_LD_Msk                                                (0x1UL << AON_LOP_PON_PPU_VPON_PCSM_1_LOP_PON_PPU_VPON_PCSM_BYP_OPOR_LD_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_1_LOP_PON_PPU_VPON_PCSM_REG_ENLPM_Pos                                                  12U
+#define AON_LOP_PON_PPU_VPON_PCSM_1_LOP_PON_PPU_VPON_PCSM_REG_ENLPM_Msk                                                  (0x1UL << AON_LOP_PON_PPU_VPON_PCSM_1_LOP_PON_PPU_VPON_PCSM_REG_ENLPM_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_1_LOP_PON_PPU_VPON_PCSM_REG_ENPCCM_Pos                                                 13U
+#define AON_LOP_PON_PPU_VPON_PCSM_1_LOP_PON_PPU_VPON_PCSM_REG_ENPCCM_Msk                                                 (0x1UL << AON_LOP_PON_PPU_VPON_PCSM_1_LOP_PON_PPU_VPON_PCSM_REG_ENPCCM_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_1_LOP_PON_PPU_VPON_PCSM_ENCCM_OUT_VDDCORE_Pos                                          14U
+#define AON_LOP_PON_PPU_VPON_PCSM_1_LOP_PON_PPU_VPON_PCSM_ENCCM_OUT_VDDCORE_Msk                                          (0x1UL << AON_LOP_PON_PPU_VPON_PCSM_1_LOP_PON_PPU_VPON_PCSM_ENCCM_OUT_VDDCORE_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_1_LOP_PON_PPU_VPON_PCSM_ENCCM_OUT_VDDPA_Pos                                            15U
+#define AON_LOP_PON_PPU_VPON_PCSM_1_LOP_PON_PPU_VPON_PCSM_ENCCM_OUT_VDDPA_Msk                                            (0x1UL << AON_LOP_PON_PPU_VPON_PCSM_1_LOP_PON_PPU_VPON_PCSM_ENCCM_OUT_VDDPA_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_1_LOP_PON_PPU_VPON_PCSM_ENCCM_OUT_HV18_Pos                                             16U
+#define AON_LOP_PON_PPU_VPON_PCSM_1_LOP_PON_PPU_VPON_PCSM_ENCCM_OUT_HV18_Msk                                             (0x1UL << AON_LOP_PON_PPU_VPON_PCSM_1_LOP_PON_PPU_VPON_PCSM_ENCCM_OUT_HV18_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_1_LOP_PON_PPU_VPON_PCSM_ENCCM_OUT_HV25_Pos                                             17U
+#define AON_LOP_PON_PPU_VPON_PCSM_1_LOP_PON_PPU_VPON_PCSM_ENCCM_OUT_HV25_Msk                                             (0x1UL << AON_LOP_PON_PPU_VPON_PCSM_1_LOP_PON_PPU_VPON_PCSM_ENCCM_OUT_HV25_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_1_LOP_PON_PPU_VPON_PCSM_ZCDLY_SET_Pos                                                  18U
+#define AON_LOP_PON_PPU_VPON_PCSM_1_LOP_PON_PPU_VPON_PCSM_ZCDLY_SET_Msk                                                  (0x3UL << AON_LOP_PON_PPU_VPON_PCSM_1_LOP_PON_PPU_VPON_PCSM_ZCDLY_SET_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_1_LOP_PON_PPU_VPON_PCSM_ENDLY_FOR_K_Pos                                                20U
+#define AON_LOP_PON_PPU_VPON_PCSM_1_LOP_PON_PPU_VPON_PCSM_ENDLY_FOR_K_Msk                                                (0x1UL << AON_LOP_PON_PPU_VPON_PCSM_1_LOP_PON_PPU_VPON_PCSM_ENDLY_FOR_K_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_1_LOP_PON_PPU_VPON_PCSM_BUCK_BOOST_VDDPA_POS_RSTB_Pos                                  21U
+#define AON_LOP_PON_PPU_VPON_PCSM_1_LOP_PON_PPU_VPON_PCSM_BUCK_BOOST_VDDPA_POS_RSTB_Msk                                  (0x1UL << AON_LOP_PON_PPU_VPON_PCSM_1_LOP_PON_PPU_VPON_PCSM_BUCK_BOOST_VDDPA_POS_RSTB_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_1_LOP_PON_PPU_VPON_PCSM_BUCK_BOOST_HV18_POS_RSTB_Pos                                   22U
+#define AON_LOP_PON_PPU_VPON_PCSM_1_LOP_PON_PPU_VPON_PCSM_BUCK_BOOST_HV18_POS_RSTB_Msk                                   (0x1UL << AON_LOP_PON_PPU_VPON_PCSM_1_LOP_PON_PPU_VPON_PCSM_BUCK_BOOST_HV18_POS_RSTB_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_1_LOP_PON_PPU_VPON_PCSM_EN_DMYLOAD_VDDCORE_Pos                                         23U
+#define AON_LOP_PON_PPU_VPON_PCSM_1_LOP_PON_PPU_VPON_PCSM_EN_DMYLOAD_VDDCORE_Msk                                         (0x1UL << AON_LOP_PON_PPU_VPON_PCSM_1_LOP_PON_PPU_VPON_PCSM_EN_DMYLOAD_VDDCORE_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_1_LOP_PON_PPU_VPON_PCSM_EN_DMYLOAD_VDDPA_Pos                                           24U
+#define AON_LOP_PON_PPU_VPON_PCSM_1_LOP_PON_PPU_VPON_PCSM_EN_DMYLOAD_VDDPA_Msk                                           (0x1UL << AON_LOP_PON_PPU_VPON_PCSM_1_LOP_PON_PPU_VPON_PCSM_EN_DMYLOAD_VDDPA_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_1_LOP_PON_PPU_VPON_PCSM_EN_DMYLOAD_HV18_Pos                                            25U
+#define AON_LOP_PON_PPU_VPON_PCSM_1_LOP_PON_PPU_VPON_PCSM_EN_DMYLOAD_HV18_Msk                                            (0x1UL << AON_LOP_PON_PPU_VPON_PCSM_1_LOP_PON_PPU_VPON_PCSM_EN_DMYLOAD_HV18_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_1_LOP_PON_PPU_VPON_PCSM_EN_DMYLOAD_HV25_Pos                                            26U
+#define AON_LOP_PON_PPU_VPON_PCSM_1_LOP_PON_PPU_VPON_PCSM_EN_DMYLOAD_HV25_Msk                                            (0x1UL << AON_LOP_PON_PPU_VPON_PCSM_1_LOP_PON_PPU_VPON_PCSM_EN_DMYLOAD_HV25_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_1_LOP_PON_PPU_VPON_PCSM_POW_VDDPA_DET_Pos                                              27U
+#define AON_LOP_PON_PPU_VPON_PCSM_1_LOP_PON_PPU_VPON_PCSM_POW_VDDPA_DET_Msk                                              (0x1UL << AON_LOP_PON_PPU_VPON_PCSM_1_LOP_PON_PPU_VPON_PCSM_POW_VDDPA_DET_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_1_LOP_PON_PPU_VPON_PCSM_POW_HV18_DET_Pos                                               28U
+#define AON_LOP_PON_PPU_VPON_PCSM_1_LOP_PON_PPU_VPON_PCSM_POW_HV18_DET_Msk                                               (0x1UL << AON_LOP_PON_PPU_VPON_PCSM_1_LOP_PON_PPU_VPON_PCSM_POW_HV18_DET_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_1_LOP_PON_PPU_VPON_PCSM_POW_VDDCORE_DET_Pos                                            29U
+#define AON_LOP_PON_PPU_VPON_PCSM_1_LOP_PON_PPU_VPON_PCSM_POW_VDDCORE_DET_Msk                                            (0x1UL << AON_LOP_PON_PPU_VPON_PCSM_1_LOP_PON_PPU_VPON_PCSM_POW_VDDCORE_DET_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_1_LOP_PON_PPU_VPON_PCSM_POW_VANA_DET_Pos                                               30U
+#define AON_LOP_PON_PPU_VPON_PCSM_1_LOP_PON_PPU_VPON_PCSM_POW_VANA_DET_Msk                                               (0x1UL << AON_LOP_PON_PPU_VPON_PCSM_1_LOP_PON_PPU_VPON_PCSM_POW_VANA_DET_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_1_LOP_PON_PPU_VPON_PCSM_EN_BIAS_10UA_Pos                                               31U
+#define AON_LOP_PON_PPU_VPON_PCSM_1_LOP_PON_PPU_VPON_PCSM_EN_BIAS_10UA_Msk                                               (0x1UL << AON_LOP_PON_PPU_VPON_PCSM_1_LOP_PON_PPU_VPON_PCSM_EN_BIAS_10UA_Pos)
+
+/* 0x9B0    0x4000_09b0
+    0       R/W     LOP_PON_PPU_VPON_PCSM_EN_MCM_FLASH_PC2                      1'b1
+    1       R/W     LOP_PON_PPU_VPON_PCSM_EN_MCM_FLASH_PC1                      1'b1
+    2       R/W     LOP_PON_PPU_VPON_PCSM_EN_DISCHG_MCM_FLASH                   1'b0
+    3       R/W     LOP_PON_PPU_VPON_PCSM_EN_BIAS_1UA                           1'b1
+    4       R/W     LOP_PON_PPU_VPON_PCSM_IO_RSTB33_EN                          1'b1
+    5       R/W     LOP_PON_PPU_VPON_PCSM_IO_SHDN33_EN                          1'b1
+    13:6    R/W     LOP_PON_PPU_VPON_PCSM_TUNE_VDDPA                            8'b00100010
+    19:14   R/W     LOP_PON_PPU_VPON_PCSM_TUNE_HV18                             6'b100000
+    24:20   R/W     LOP_PON_PPU_VPON_PCSM_SEL_VREF_HV25_HQ                      5'b01111
+    25      R/W     LOP_PON_PPU_VPON_PCSM_EN_CMP_LQ_VDDCORE                     1'b1
+    26      R/W     LOP_PON_PPU_VPON_PCSM_EN_CMP_LQ_HV18                        1'b1
+    27      R/W     LOP_PON_PPU_VPON_PCSM_EN_CMP_LQ_HV25                        1'b1
+    28      R/W     LOP_PON_PPU_VPON_PCSM_EN_CMP_HQ_VDDCORE                     1'b1
+    29      R/W     LOP_PON_PPU_VPON_PCSM_EN_CMP_HQ_VDDPA                       1'b1
+    30      R/W     LOP_PON_PPU_VPON_PCSM_EN_CMP_HQ_HV18                        1'b1
+    31      R/W     LOP_PON_PPU_VPON_PCSM_EN_CMP_HQ_HV25                        1'b1
+ */
+typedef union _AON_LOP_PON_PPU_VPON_PCSM_2_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t LOP_PON_PPU_VPON_PCSM_EN_MCM_FLASH_PC2: 1;
+        uint32_t LOP_PON_PPU_VPON_PCSM_EN_MCM_FLASH_PC1: 1;
+        uint32_t LOP_PON_PPU_VPON_PCSM_EN_DISCHG_MCM_FLASH: 1;
+        uint32_t LOP_PON_PPU_VPON_PCSM_EN_BIAS_1UA: 1;
+        uint32_t LOP_PON_PPU_VPON_PCSM_IO_RSTB33_EN: 1;
+        uint32_t LOP_PON_PPU_VPON_PCSM_IO_SHDN33_EN: 1;
+        uint32_t LOP_PON_PPU_VPON_PCSM_TUNE_VDDPA: 8;
+        uint32_t LOP_PON_PPU_VPON_PCSM_TUNE_HV18: 6;
+        uint32_t LOP_PON_PPU_VPON_PCSM_SEL_VREF_HV25_HQ: 5;
+        uint32_t LOP_PON_PPU_VPON_PCSM_EN_CMP_LQ_VDDCORE: 1;
+        uint32_t LOP_PON_PPU_VPON_PCSM_EN_CMP_LQ_HV18: 1;
+        uint32_t LOP_PON_PPU_VPON_PCSM_EN_CMP_LQ_HV25: 1;
+        uint32_t LOP_PON_PPU_VPON_PCSM_EN_CMP_HQ_VDDCORE: 1;
+        uint32_t LOP_PON_PPU_VPON_PCSM_EN_CMP_HQ_VDDPA: 1;
+        uint32_t LOP_PON_PPU_VPON_PCSM_EN_CMP_HQ_HV18: 1;
+        uint32_t LOP_PON_PPU_VPON_PCSM_EN_CMP_HQ_HV25: 1;
+    };
+} AON_LOP_PON_PPU_VPON_PCSM_2_TYPE;
+
+/*0x4000_09b0 AON_LOP_PON_PPU_VPON_PCSM_2*/
+#define AON_LOP_PON_PPU_VPON_PCSM_2_LOP_PON_PPU_VPON_PCSM_EN_MCM_FLASH_PC2_Pos                                           0U
+#define AON_LOP_PON_PPU_VPON_PCSM_2_LOP_PON_PPU_VPON_PCSM_EN_MCM_FLASH_PC2_Msk                                           (0x1UL << AON_LOP_PON_PPU_VPON_PCSM_2_LOP_PON_PPU_VPON_PCSM_EN_MCM_FLASH_PC2_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_2_LOP_PON_PPU_VPON_PCSM_EN_MCM_FLASH_PC1_Pos                                           1U
+#define AON_LOP_PON_PPU_VPON_PCSM_2_LOP_PON_PPU_VPON_PCSM_EN_MCM_FLASH_PC1_Msk                                           (0x1UL << AON_LOP_PON_PPU_VPON_PCSM_2_LOP_PON_PPU_VPON_PCSM_EN_MCM_FLASH_PC1_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_2_LOP_PON_PPU_VPON_PCSM_EN_DISCHG_MCM_FLASH_Pos                                        2U
+#define AON_LOP_PON_PPU_VPON_PCSM_2_LOP_PON_PPU_VPON_PCSM_EN_DISCHG_MCM_FLASH_Msk                                        (0x1UL << AON_LOP_PON_PPU_VPON_PCSM_2_LOP_PON_PPU_VPON_PCSM_EN_DISCHG_MCM_FLASH_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_2_LOP_PON_PPU_VPON_PCSM_EN_BIAS_1UA_Pos                                                3U
+#define AON_LOP_PON_PPU_VPON_PCSM_2_LOP_PON_PPU_VPON_PCSM_EN_BIAS_1UA_Msk                                                (0x1UL << AON_LOP_PON_PPU_VPON_PCSM_2_LOP_PON_PPU_VPON_PCSM_EN_BIAS_1UA_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_2_LOP_PON_PPU_VPON_PCSM_IO_RSTB33_EN_Pos                                               4U
+#define AON_LOP_PON_PPU_VPON_PCSM_2_LOP_PON_PPU_VPON_PCSM_IO_RSTB33_EN_Msk                                               (0x1UL << AON_LOP_PON_PPU_VPON_PCSM_2_LOP_PON_PPU_VPON_PCSM_IO_RSTB33_EN_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_2_LOP_PON_PPU_VPON_PCSM_IO_SHDN33_EN_Pos                                               5U
+#define AON_LOP_PON_PPU_VPON_PCSM_2_LOP_PON_PPU_VPON_PCSM_IO_SHDN33_EN_Msk                                               (0x1UL << AON_LOP_PON_PPU_VPON_PCSM_2_LOP_PON_PPU_VPON_PCSM_IO_SHDN33_EN_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_2_LOP_PON_PPU_VPON_PCSM_TUNE_VDDPA_Pos                                                 6U
+#define AON_LOP_PON_PPU_VPON_PCSM_2_LOP_PON_PPU_VPON_PCSM_TUNE_VDDPA_Msk                                                 (0xFFUL << AON_LOP_PON_PPU_VPON_PCSM_2_LOP_PON_PPU_VPON_PCSM_TUNE_VDDPA_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_2_LOP_PON_PPU_VPON_PCSM_TUNE_HV18_Pos                                                  14U
+#define AON_LOP_PON_PPU_VPON_PCSM_2_LOP_PON_PPU_VPON_PCSM_TUNE_HV18_Msk                                                  (0x3FUL << AON_LOP_PON_PPU_VPON_PCSM_2_LOP_PON_PPU_VPON_PCSM_TUNE_HV18_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_2_LOP_PON_PPU_VPON_PCSM_SEL_VREF_HV25_HQ_Pos                                           20U
+#define AON_LOP_PON_PPU_VPON_PCSM_2_LOP_PON_PPU_VPON_PCSM_SEL_VREF_HV25_HQ_Msk                                           (0x1FUL << AON_LOP_PON_PPU_VPON_PCSM_2_LOP_PON_PPU_VPON_PCSM_SEL_VREF_HV25_HQ_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_2_LOP_PON_PPU_VPON_PCSM_EN_CMP_LQ_VDDCORE_Pos                                          25U
+#define AON_LOP_PON_PPU_VPON_PCSM_2_LOP_PON_PPU_VPON_PCSM_EN_CMP_LQ_VDDCORE_Msk                                          (0x1UL << AON_LOP_PON_PPU_VPON_PCSM_2_LOP_PON_PPU_VPON_PCSM_EN_CMP_LQ_VDDCORE_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_2_LOP_PON_PPU_VPON_PCSM_EN_CMP_LQ_HV18_Pos                                             26U
+#define AON_LOP_PON_PPU_VPON_PCSM_2_LOP_PON_PPU_VPON_PCSM_EN_CMP_LQ_HV18_Msk                                             (0x1UL << AON_LOP_PON_PPU_VPON_PCSM_2_LOP_PON_PPU_VPON_PCSM_EN_CMP_LQ_HV18_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_2_LOP_PON_PPU_VPON_PCSM_EN_CMP_LQ_HV25_Pos                                             27U
+#define AON_LOP_PON_PPU_VPON_PCSM_2_LOP_PON_PPU_VPON_PCSM_EN_CMP_LQ_HV25_Msk                                             (0x1UL << AON_LOP_PON_PPU_VPON_PCSM_2_LOP_PON_PPU_VPON_PCSM_EN_CMP_LQ_HV25_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_2_LOP_PON_PPU_VPON_PCSM_EN_CMP_HQ_VDDCORE_Pos                                          28U
+#define AON_LOP_PON_PPU_VPON_PCSM_2_LOP_PON_PPU_VPON_PCSM_EN_CMP_HQ_VDDCORE_Msk                                          (0x1UL << AON_LOP_PON_PPU_VPON_PCSM_2_LOP_PON_PPU_VPON_PCSM_EN_CMP_HQ_VDDCORE_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_2_LOP_PON_PPU_VPON_PCSM_EN_CMP_HQ_VDDPA_Pos                                            29U
+#define AON_LOP_PON_PPU_VPON_PCSM_2_LOP_PON_PPU_VPON_PCSM_EN_CMP_HQ_VDDPA_Msk                                            (0x1UL << AON_LOP_PON_PPU_VPON_PCSM_2_LOP_PON_PPU_VPON_PCSM_EN_CMP_HQ_VDDPA_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_2_LOP_PON_PPU_VPON_PCSM_EN_CMP_HQ_HV18_Pos                                             30U
+#define AON_LOP_PON_PPU_VPON_PCSM_2_LOP_PON_PPU_VPON_PCSM_EN_CMP_HQ_HV18_Msk                                             (0x1UL << AON_LOP_PON_PPU_VPON_PCSM_2_LOP_PON_PPU_VPON_PCSM_EN_CMP_HQ_HV18_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_2_LOP_PON_PPU_VPON_PCSM_EN_CMP_HQ_HV25_Pos                                             31U
+#define AON_LOP_PON_PPU_VPON_PCSM_2_LOP_PON_PPU_VPON_PCSM_EN_CMP_HQ_HV25_Msk                                             (0x1UL << AON_LOP_PON_PPU_VPON_PCSM_2_LOP_PON_PPU_VPON_PCSM_EN_CMP_HQ_HV25_Pos)
+
+/* 0x9B4    0x4000_09b4
+    0       R/W     LOP_PON_PPU_VPON_PCSM_LDO_ENB_DMYL_200U_LDOPA               1'b1
+    1       R/W     LOP_PON_PPU_VPON_PCSM_LDO_ENB_DMYL_200U_LDOANA              1'b1
+    2       R/W     LOP_PON_PPU_VPON_PCSM_LDO_PA_POS_RSTB                       1'b1
+    3       R/W     LOP_PON_PPU_VPON_PCSM_LDO_ANA_POS_RSTB                      1'b1
+    4       R/W     LOP_PON_PPU_VPON_PCSM_LDO_POW_BIAS_LDOPA                    1'b1
+    5       R/W     LOP_PON_PPU_VPON_PCSM_LDO_POW_BIAS_LDOANA                   1'b1
+    6       R/W     LOP_PON_PPU_VPON_PCSM_BUCK_BOOST_VDDPA_POS_EN_POS           1'b1
+    7       R/W     LOP_PON_PPU_VPON_PCSM_BUCK_BOOST_HV18_POS_EN_POS            1'b1
+    12:8    R/W     LOP_PON_PPU_VPON_PCSM_SEL_VREF_VDDCORE_LQ                   5'b01110
+    18:13   R/W     LOP_PON_PPU_VPON_PCSM_TUNE_LPM_HV18                         6'b100000
+    23:19   R/W     LOP_PON_PPU_VPON_PCSM_SEL_VREF_HV25_LQ                      5'b01111
+    31:24   R/W     LOP_PON_PPU_VPON_PCSM_TUNE_VDDCORE                          8'b01110110
+ */
+typedef union _AON_LOP_PON_PPU_VPON_PCSM_3_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t LOP_PON_PPU_VPON_PCSM_LDO_ENB_DMYL_200U_LDOPA: 1;
+        uint32_t LOP_PON_PPU_VPON_PCSM_LDO_ENB_DMYL_200U_LDOANA: 1;
+        uint32_t LOP_PON_PPU_VPON_PCSM_LDO_PA_POS_RSTB: 1;
+        uint32_t LOP_PON_PPU_VPON_PCSM_LDO_ANA_POS_RSTB: 1;
+        uint32_t LOP_PON_PPU_VPON_PCSM_LDO_POW_BIAS_LDOPA: 1;
+        uint32_t LOP_PON_PPU_VPON_PCSM_LDO_POW_BIAS_LDOANA: 1;
+        uint32_t LOP_PON_PPU_VPON_PCSM_BUCK_BOOST_VDDPA_POS_EN_POS: 1;
+        uint32_t LOP_PON_PPU_VPON_PCSM_BUCK_BOOST_HV18_POS_EN_POS: 1;
+        uint32_t LOP_PON_PPU_VPON_PCSM_SEL_VREF_VDDCORE_LQ: 5;
+        uint32_t LOP_PON_PPU_VPON_PCSM_TUNE_LPM_HV18: 6;
+        uint32_t LOP_PON_PPU_VPON_PCSM_SEL_VREF_HV25_LQ: 5;
+        uint32_t LOP_PON_PPU_VPON_PCSM_TUNE_VDDCORE: 8;
+    };
+} AON_LOP_PON_PPU_VPON_PCSM_3_TYPE;
+
+/*0x4000_09b4 AON_LOP_PON_PPU_VPON_PCSM_3*/
+#define AON_LOP_PON_PPU_VPON_PCSM_3_LOP_PON_PPU_VPON_PCSM_LDO_ENB_DMYL_200U_LDOPA_Pos                                    0U
+#define AON_LOP_PON_PPU_VPON_PCSM_3_LOP_PON_PPU_VPON_PCSM_LDO_ENB_DMYL_200U_LDOPA_Msk                                    (0x1UL << AON_LOP_PON_PPU_VPON_PCSM_3_LOP_PON_PPU_VPON_PCSM_LDO_ENB_DMYL_200U_LDOPA_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_3_LOP_PON_PPU_VPON_PCSM_LDO_ENB_DMYL_200U_LDOANA_Pos                                   1U
+#define AON_LOP_PON_PPU_VPON_PCSM_3_LOP_PON_PPU_VPON_PCSM_LDO_ENB_DMYL_200U_LDOANA_Msk                                   (0x1UL << AON_LOP_PON_PPU_VPON_PCSM_3_LOP_PON_PPU_VPON_PCSM_LDO_ENB_DMYL_200U_LDOANA_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_3_LOP_PON_PPU_VPON_PCSM_LDO_PA_POS_RSTB_Pos                                            2U
+#define AON_LOP_PON_PPU_VPON_PCSM_3_LOP_PON_PPU_VPON_PCSM_LDO_PA_POS_RSTB_Msk                                            (0x1UL << AON_LOP_PON_PPU_VPON_PCSM_3_LOP_PON_PPU_VPON_PCSM_LDO_PA_POS_RSTB_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_3_LOP_PON_PPU_VPON_PCSM_LDO_ANA_POS_RSTB_Pos                                           3U
+#define AON_LOP_PON_PPU_VPON_PCSM_3_LOP_PON_PPU_VPON_PCSM_LDO_ANA_POS_RSTB_Msk                                           (0x1UL << AON_LOP_PON_PPU_VPON_PCSM_3_LOP_PON_PPU_VPON_PCSM_LDO_ANA_POS_RSTB_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_3_LOP_PON_PPU_VPON_PCSM_LDO_POW_BIAS_LDOPA_Pos                                         4U
+#define AON_LOP_PON_PPU_VPON_PCSM_3_LOP_PON_PPU_VPON_PCSM_LDO_POW_BIAS_LDOPA_Msk                                         (0x1UL << AON_LOP_PON_PPU_VPON_PCSM_3_LOP_PON_PPU_VPON_PCSM_LDO_POW_BIAS_LDOPA_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_3_LOP_PON_PPU_VPON_PCSM_LDO_POW_BIAS_LDOANA_Pos                                        5U
+#define AON_LOP_PON_PPU_VPON_PCSM_3_LOP_PON_PPU_VPON_PCSM_LDO_POW_BIAS_LDOANA_Msk                                        (0x1UL << AON_LOP_PON_PPU_VPON_PCSM_3_LOP_PON_PPU_VPON_PCSM_LDO_POW_BIAS_LDOANA_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_3_LOP_PON_PPU_VPON_PCSM_BUCK_BOOST_VDDPA_POS_EN_POS_Pos                                6U
+#define AON_LOP_PON_PPU_VPON_PCSM_3_LOP_PON_PPU_VPON_PCSM_BUCK_BOOST_VDDPA_POS_EN_POS_Msk                                (0x1UL << AON_LOP_PON_PPU_VPON_PCSM_3_LOP_PON_PPU_VPON_PCSM_BUCK_BOOST_VDDPA_POS_EN_POS_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_3_LOP_PON_PPU_VPON_PCSM_BUCK_BOOST_HV18_POS_EN_POS_Pos                                 7U
+#define AON_LOP_PON_PPU_VPON_PCSM_3_LOP_PON_PPU_VPON_PCSM_BUCK_BOOST_HV18_POS_EN_POS_Msk                                 (0x1UL << AON_LOP_PON_PPU_VPON_PCSM_3_LOP_PON_PPU_VPON_PCSM_BUCK_BOOST_HV18_POS_EN_POS_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_3_LOP_PON_PPU_VPON_PCSM_SEL_VREF_VDDCORE_LQ_Pos                                        8U
+#define AON_LOP_PON_PPU_VPON_PCSM_3_LOP_PON_PPU_VPON_PCSM_SEL_VREF_VDDCORE_LQ_Msk                                        (0x1FUL << AON_LOP_PON_PPU_VPON_PCSM_3_LOP_PON_PPU_VPON_PCSM_SEL_VREF_VDDCORE_LQ_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_3_LOP_PON_PPU_VPON_PCSM_TUNE_LPM_HV18_Pos                                              13U
+#define AON_LOP_PON_PPU_VPON_PCSM_3_LOP_PON_PPU_VPON_PCSM_TUNE_LPM_HV18_Msk                                              (0x3FUL << AON_LOP_PON_PPU_VPON_PCSM_3_LOP_PON_PPU_VPON_PCSM_TUNE_LPM_HV18_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_3_LOP_PON_PPU_VPON_PCSM_SEL_VREF_HV25_LQ_Pos                                           19U
+#define AON_LOP_PON_PPU_VPON_PCSM_3_LOP_PON_PPU_VPON_PCSM_SEL_VREF_HV25_LQ_Msk                                           (0x1FUL << AON_LOP_PON_PPU_VPON_PCSM_3_LOP_PON_PPU_VPON_PCSM_SEL_VREF_HV25_LQ_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_3_LOP_PON_PPU_VPON_PCSM_TUNE_VDDCORE_Pos                                               24U
+#define AON_LOP_PON_PPU_VPON_PCSM_3_LOP_PON_PPU_VPON_PCSM_TUNE_VDDCORE_Msk                                               (0xFFUL << AON_LOP_PON_PPU_VPON_PCSM_3_LOP_PON_PPU_VPON_PCSM_TUNE_VDDCORE_Pos)
+
+/* 0x9B8    0x4000_09b8
+    0       R/W     RESERVED_1                                                  1'h0
+    1       R/W     LOP_PON_PPU_VPON_PCSM_DVFS_HV_BT_MAC_VSEL                   1'b1
+    2       R/W     LOP_PON_PPU_VPON_PCSM_DVFS_HV_BT_MAC_CCMP_VSEL              1'b1
+    3       R/W     LOP_PON_PPU_VPON_PCSM_DVFS_HV_BUFFER_RAM_VSEL               1'b1
+    4       R/W     LOP_PON_PPU_VPON_PCSM_DVFS_HV_USB_RAM_VSEL                  1'b1
+    5       R/W     LOP_PON_PPU_VPON_PCSM_DVFS_HV_CAN_RAM_VSEL                  1'b1
+    6       R/W     LOP_PON_PPU_VPON_PCSM_DVFS_HV_CPU_RAM_VSEL                  1'b1
+    7       R/W     LOP_PON_PPU_VPON_PCSM_DVFS_HV_AUDIO_RAM_VSEL                1'b1
+    8       R/W     LOP_PON_PPU_VPON_PCSM_DVFS_HV_BTPHY_RAM_VSEL                1'b1
+    9       R/W     LOP_PON_PPU_VPON_PCSM_DVFS_HV_PLATFORM_ROM_VSEL             1'b1
+    10      R/W     LOP_PON_PPU_VPON_PCSM_DVFS_HV_RETSRAM_VSEL                  1'b1
+    11      R/W     LOP_PON_PPU_VPON_PCSM_DVFS_HV_CACHE_VSEL                    1'b1
+    12      R/W     LOP_PON_PPU_VPON_PCSM_DVFS_HV_AMU_RAM_VSEL                  1'b1
+    13      R/W     RESERVED                                                    1'h0
+    14      R/W     LOP_PON_PPU_VPON_PCSM_EN_FAST_TRNAS                         1'b0
+    15      R/W     LOP_PON_PPU_VPON_PCSM_LDO_PA_POS_EN_POS                     1'b1
+    16      R/W     LOP_PON_PPU_VPON_PCSM_LDO_ANA_POS_EN_POS                    1'b1
+    22:17   R/W     LOP_PON_PPU_VPON_PCSM_LDO_TUNE_LDOPA                        6'b010000
+    27:23   R/W     LOP_PON_PPU_VPON_PCSM_LDO_TUNE_LDOANA                       5'b10001
+    28      R/W     LOP_PON_PPU_VPON_PCSM_LDO_ENPC_LDOPA                        1'b0
+    29      R/W     LOP_PON_PPU_VPON_PCSM_LDO_ENPC_LDOANA                       1'b0
+    30      R/W     LOP_PON_PPU_VPON_PCSM_LDO_POW_LDOPA                         1'b1
+    31      R/W     LOP_PON_PPU_VPON_PCSM_LDO_POW_LDOANA                        1'b1
+ */
+typedef union _AON_LOP_PON_PPU_VPON_PCSM_4_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED_1: 1;
+        uint32_t LOP_PON_PPU_VPON_PCSM_DVFS_HV_BT_MAC_VSEL: 1;
+        uint32_t LOP_PON_PPU_VPON_PCSM_DVFS_HV_BT_MAC_CCMP_VSEL: 1;
+        uint32_t LOP_PON_PPU_VPON_PCSM_DVFS_HV_BUFFER_RAM_VSEL: 1;
+        uint32_t LOP_PON_PPU_VPON_PCSM_DVFS_HV_USB_RAM_VSEL: 1;
+        uint32_t LOP_PON_PPU_VPON_PCSM_DVFS_HV_CAN_RAM_VSEL: 1;
+        uint32_t LOP_PON_PPU_VPON_PCSM_DVFS_HV_CPU_RAM_VSEL: 1;
+        uint32_t LOP_PON_PPU_VPON_PCSM_DVFS_HV_AUDIO_RAM_VSEL: 1;
+        uint32_t LOP_PON_PPU_VPON_PCSM_DVFS_HV_BTPHY_RAM_VSEL: 1;
+        uint32_t LOP_PON_PPU_VPON_PCSM_DVFS_HV_PLATFORM_ROM_VSEL: 1;
+        uint32_t LOP_PON_PPU_VPON_PCSM_DVFS_HV_RETSRAM_VSEL: 1;
+        uint32_t LOP_PON_PPU_VPON_PCSM_DVFS_HV_CACHE_VSEL: 1;
+        uint32_t LOP_PON_PPU_VPON_PCSM_DVFS_HV_AMU_RAM_VSEL: 1;
+        uint32_t RESERVED: 1;
+        uint32_t LOP_PON_PPU_VPON_PCSM_EN_FAST_TRNAS: 1;
+        uint32_t LOP_PON_PPU_VPON_PCSM_LDO_PA_POS_EN_POS: 1;
+        uint32_t LOP_PON_PPU_VPON_PCSM_LDO_ANA_POS_EN_POS: 1;
+        uint32_t LOP_PON_PPU_VPON_PCSM_LDO_TUNE_LDOPA: 6;
+        uint32_t LOP_PON_PPU_VPON_PCSM_LDO_TUNE_LDOANA: 5;
+        uint32_t LOP_PON_PPU_VPON_PCSM_LDO_ENPC_LDOPA: 1;
+        uint32_t LOP_PON_PPU_VPON_PCSM_LDO_ENPC_LDOANA: 1;
+        uint32_t LOP_PON_PPU_VPON_PCSM_LDO_POW_LDOPA: 1;
+        uint32_t LOP_PON_PPU_VPON_PCSM_LDO_POW_LDOANA: 1;
+    };
+} AON_LOP_PON_PPU_VPON_PCSM_4_TYPE;
+
+/*0x4000_09b8 AON_LOP_PON_PPU_VPON_PCSM_4*/
+#define AON_LOP_PON_PPU_VPON_PCSM_4_RESERVED_1_Pos                                                                       0U
+#define AON_LOP_PON_PPU_VPON_PCSM_4_RESERVED_1_Msk                                                                       (0x1UL << AON_LOP_PON_PPU_VPON_PCSM_4_RESERVED_1_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_4_LOP_PON_PPU_VPON_PCSM_DVFS_HV_BT_MAC_VSEL_Pos                                        1U
+#define AON_LOP_PON_PPU_VPON_PCSM_4_LOP_PON_PPU_VPON_PCSM_DVFS_HV_BT_MAC_VSEL_Msk                                        (0x1UL << AON_LOP_PON_PPU_VPON_PCSM_4_LOP_PON_PPU_VPON_PCSM_DVFS_HV_BT_MAC_VSEL_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_4_LOP_PON_PPU_VPON_PCSM_DVFS_HV_BT_MAC_CCMP_VSEL_Pos                                   2U
+#define AON_LOP_PON_PPU_VPON_PCSM_4_LOP_PON_PPU_VPON_PCSM_DVFS_HV_BT_MAC_CCMP_VSEL_Msk                                   (0x1UL << AON_LOP_PON_PPU_VPON_PCSM_4_LOP_PON_PPU_VPON_PCSM_DVFS_HV_BT_MAC_CCMP_VSEL_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_4_LOP_PON_PPU_VPON_PCSM_DVFS_HV_BUFFER_RAM_VSEL_Pos                                    3U
+#define AON_LOP_PON_PPU_VPON_PCSM_4_LOP_PON_PPU_VPON_PCSM_DVFS_HV_BUFFER_RAM_VSEL_Msk                                    (0x1UL << AON_LOP_PON_PPU_VPON_PCSM_4_LOP_PON_PPU_VPON_PCSM_DVFS_HV_BUFFER_RAM_VSEL_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_4_LOP_PON_PPU_VPON_PCSM_DVFS_HV_USB_RAM_VSEL_Pos                                       4U
+#define AON_LOP_PON_PPU_VPON_PCSM_4_LOP_PON_PPU_VPON_PCSM_DVFS_HV_USB_RAM_VSEL_Msk                                       (0x1UL << AON_LOP_PON_PPU_VPON_PCSM_4_LOP_PON_PPU_VPON_PCSM_DVFS_HV_USB_RAM_VSEL_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_4_LOP_PON_PPU_VPON_PCSM_DVFS_HV_CAN_RAM_VSEL_Pos                                       5U
+#define AON_LOP_PON_PPU_VPON_PCSM_4_LOP_PON_PPU_VPON_PCSM_DVFS_HV_CAN_RAM_VSEL_Msk                                       (0x1UL << AON_LOP_PON_PPU_VPON_PCSM_4_LOP_PON_PPU_VPON_PCSM_DVFS_HV_CAN_RAM_VSEL_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_4_LOP_PON_PPU_VPON_PCSM_DVFS_HV_CPU_RAM_VSEL_Pos                                       6U
+#define AON_LOP_PON_PPU_VPON_PCSM_4_LOP_PON_PPU_VPON_PCSM_DVFS_HV_CPU_RAM_VSEL_Msk                                       (0x1UL << AON_LOP_PON_PPU_VPON_PCSM_4_LOP_PON_PPU_VPON_PCSM_DVFS_HV_CPU_RAM_VSEL_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_4_LOP_PON_PPU_VPON_PCSM_DVFS_HV_AUDIO_RAM_VSEL_Pos                                     7U
+#define AON_LOP_PON_PPU_VPON_PCSM_4_LOP_PON_PPU_VPON_PCSM_DVFS_HV_AUDIO_RAM_VSEL_Msk                                     (0x1UL << AON_LOP_PON_PPU_VPON_PCSM_4_LOP_PON_PPU_VPON_PCSM_DVFS_HV_AUDIO_RAM_VSEL_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_4_LOP_PON_PPU_VPON_PCSM_DVFS_HV_BTPHY_RAM_VSEL_Pos                                     8U
+#define AON_LOP_PON_PPU_VPON_PCSM_4_LOP_PON_PPU_VPON_PCSM_DVFS_HV_BTPHY_RAM_VSEL_Msk                                     (0x1UL << AON_LOP_PON_PPU_VPON_PCSM_4_LOP_PON_PPU_VPON_PCSM_DVFS_HV_BTPHY_RAM_VSEL_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_4_LOP_PON_PPU_VPON_PCSM_DVFS_HV_PLATFORM_ROM_VSEL_Pos                                  9U
+#define AON_LOP_PON_PPU_VPON_PCSM_4_LOP_PON_PPU_VPON_PCSM_DVFS_HV_PLATFORM_ROM_VSEL_Msk                                  (0x1UL << AON_LOP_PON_PPU_VPON_PCSM_4_LOP_PON_PPU_VPON_PCSM_DVFS_HV_PLATFORM_ROM_VSEL_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_4_LOP_PON_PPU_VPON_PCSM_DVFS_HV_RETSRAM_VSEL_Pos                                       10U
+#define AON_LOP_PON_PPU_VPON_PCSM_4_LOP_PON_PPU_VPON_PCSM_DVFS_HV_RETSRAM_VSEL_Msk                                       (0x1UL << AON_LOP_PON_PPU_VPON_PCSM_4_LOP_PON_PPU_VPON_PCSM_DVFS_HV_RETSRAM_VSEL_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_4_LOP_PON_PPU_VPON_PCSM_DVFS_HV_CACHE_VSEL_Pos                                         11U
+#define AON_LOP_PON_PPU_VPON_PCSM_4_LOP_PON_PPU_VPON_PCSM_DVFS_HV_CACHE_VSEL_Msk                                         (0x1UL << AON_LOP_PON_PPU_VPON_PCSM_4_LOP_PON_PPU_VPON_PCSM_DVFS_HV_CACHE_VSEL_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_4_LOP_PON_PPU_VPON_PCSM_DVFS_HV_AMU_RAM_VSEL_Pos                                       12U
+#define AON_LOP_PON_PPU_VPON_PCSM_4_LOP_PON_PPU_VPON_PCSM_DVFS_HV_AMU_RAM_VSEL_Msk                                       (0x1UL << AON_LOP_PON_PPU_VPON_PCSM_4_LOP_PON_PPU_VPON_PCSM_DVFS_HV_AMU_RAM_VSEL_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_4_RESERVED_Pos                                                                         13U
+#define AON_LOP_PON_PPU_VPON_PCSM_4_RESERVED_Msk                                                                         (0x1UL << AON_LOP_PON_PPU_VPON_PCSM_4_RESERVED_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_4_LOP_PON_PPU_VPON_PCSM_EN_FAST_TRNAS_Pos                                              14U
+#define AON_LOP_PON_PPU_VPON_PCSM_4_LOP_PON_PPU_VPON_PCSM_EN_FAST_TRNAS_Msk                                              (0x1UL << AON_LOP_PON_PPU_VPON_PCSM_4_LOP_PON_PPU_VPON_PCSM_EN_FAST_TRNAS_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_4_LOP_PON_PPU_VPON_PCSM_LDO_PA_POS_EN_POS_Pos                                          15U
+#define AON_LOP_PON_PPU_VPON_PCSM_4_LOP_PON_PPU_VPON_PCSM_LDO_PA_POS_EN_POS_Msk                                          (0x1UL << AON_LOP_PON_PPU_VPON_PCSM_4_LOP_PON_PPU_VPON_PCSM_LDO_PA_POS_EN_POS_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_4_LOP_PON_PPU_VPON_PCSM_LDO_ANA_POS_EN_POS_Pos                                         16U
+#define AON_LOP_PON_PPU_VPON_PCSM_4_LOP_PON_PPU_VPON_PCSM_LDO_ANA_POS_EN_POS_Msk                                         (0x1UL << AON_LOP_PON_PPU_VPON_PCSM_4_LOP_PON_PPU_VPON_PCSM_LDO_ANA_POS_EN_POS_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_4_LOP_PON_PPU_VPON_PCSM_LDO_TUNE_LDOPA_Pos                                             17U
+#define AON_LOP_PON_PPU_VPON_PCSM_4_LOP_PON_PPU_VPON_PCSM_LDO_TUNE_LDOPA_Msk                                             (0x3FUL << AON_LOP_PON_PPU_VPON_PCSM_4_LOP_PON_PPU_VPON_PCSM_LDO_TUNE_LDOPA_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_4_LOP_PON_PPU_VPON_PCSM_LDO_TUNE_LDOANA_Pos                                            23U
+#define AON_LOP_PON_PPU_VPON_PCSM_4_LOP_PON_PPU_VPON_PCSM_LDO_TUNE_LDOANA_Msk                                            (0x1FUL << AON_LOP_PON_PPU_VPON_PCSM_4_LOP_PON_PPU_VPON_PCSM_LDO_TUNE_LDOANA_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_4_LOP_PON_PPU_VPON_PCSM_LDO_ENPC_LDOPA_Pos                                             28U
+#define AON_LOP_PON_PPU_VPON_PCSM_4_LOP_PON_PPU_VPON_PCSM_LDO_ENPC_LDOPA_Msk                                             (0x1UL << AON_LOP_PON_PPU_VPON_PCSM_4_LOP_PON_PPU_VPON_PCSM_LDO_ENPC_LDOPA_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_4_LOP_PON_PPU_VPON_PCSM_LDO_ENPC_LDOANA_Pos                                            29U
+#define AON_LOP_PON_PPU_VPON_PCSM_4_LOP_PON_PPU_VPON_PCSM_LDO_ENPC_LDOANA_Msk                                            (0x1UL << AON_LOP_PON_PPU_VPON_PCSM_4_LOP_PON_PPU_VPON_PCSM_LDO_ENPC_LDOANA_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_4_LOP_PON_PPU_VPON_PCSM_LDO_POW_LDOPA_Pos                                              30U
+#define AON_LOP_PON_PPU_VPON_PCSM_4_LOP_PON_PPU_VPON_PCSM_LDO_POW_LDOPA_Msk                                              (0x1UL << AON_LOP_PON_PPU_VPON_PCSM_4_LOP_PON_PPU_VPON_PCSM_LDO_POW_LDOPA_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_4_LOP_PON_PPU_VPON_PCSM_LDO_POW_LDOANA_Pos                                             31U
+#define AON_LOP_PON_PPU_VPON_PCSM_4_LOP_PON_PPU_VPON_PCSM_LDO_POW_LDOANA_Msk                                             (0x1UL << AON_LOP_PON_PPU_VPON_PCSM_4_LOP_PON_PPU_VPON_PCSM_LDO_POW_LDOANA_Pos)
+
+/* 0x9BC    0x4000_09bc
+    2:0     R/W     RESERVED_1                                                  3'h0
+    10:3    R/W     LOP_PON_PPU_VPON_PCSM_DVFS_LV_TUNE_VDDCORE                  8'b01110110
+    18:11   R/W     LOP_PON_PPU_VPON_PCSM_DVFS_HV_TUNE_VDDCORE                  8'b01110110
+    19      R/W     LOP_PON_PPU_VPON_PCSM_DVFS_LV_BT_MAC_VSEL                   1'b0
+    20      R/W     LOP_PON_PPU_VPON_PCSM_DVFS_LV_BT_MAC_CCMP_VSEL              1'b0
+    21      R/W     LOP_PON_PPU_VPON_PCSM_DVFS_LV_BUFFER_RAM_VSEL               1'b0
+    22      R/W     LOP_PON_PPU_VPON_PCSM_DVFS_LV_USB_RAM_VSEL                  1'b0
+    23      R/W     LOP_PON_PPU_VPON_PCSM_DVFS_LV_CAN_RAM_VSEL                  1'b0
+    24      R/W     LOP_PON_PPU_VPON_PCSM_DVFS_LV_CPU_RAM_VSEL                  1'b0
+    25      R/W     LOP_PON_PPU_VPON_PCSM_DVFS_LV_AUDIO_RAM_VSEL                1'b0
+    26      R/W     LOP_PON_PPU_VPON_PCSM_DVFS_LV_BTPHY_RAM_VSEL                1'b0
+    27      R/W     LOP_PON_PPU_VPON_PCSM_DVFS_LV_PLATFORM_ROM_VSEL             1'b0
+    28      R/W     LOP_PON_PPU_VPON_PCSM_DVFS_LV_RETSRAM_VSEL                  1'b0
+    29      R/W     LOP_PON_PPU_VPON_PCSM_DVFS_LV_CACHE_VSEL                    1'b0
+    30      R/W     LOP_PON_PPU_VPON_PCSM_DVFS_LV_AMU_RAM_VSEL                  1'b0
+    31      R/W     RESERVED                                                    1'h0
+ */
+typedef union _AON_LOP_PON_PPU_VPON_PCSM_5_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED_1: 3;
+        uint32_t LOP_PON_PPU_VPON_PCSM_DVFS_LV_TUNE_VDDCORE: 8;
+        uint32_t LOP_PON_PPU_VPON_PCSM_DVFS_HV_TUNE_VDDCORE: 8;
+        uint32_t LOP_PON_PPU_VPON_PCSM_DVFS_LV_BT_MAC_VSEL: 1;
+        uint32_t LOP_PON_PPU_VPON_PCSM_DVFS_LV_BT_MAC_CCMP_VSEL: 1;
+        uint32_t LOP_PON_PPU_VPON_PCSM_DVFS_LV_BUFFER_RAM_VSEL: 1;
+        uint32_t LOP_PON_PPU_VPON_PCSM_DVFS_LV_USB_RAM_VSEL: 1;
+        uint32_t LOP_PON_PPU_VPON_PCSM_DVFS_LV_CAN_RAM_VSEL: 1;
+        uint32_t LOP_PON_PPU_VPON_PCSM_DVFS_LV_CPU_RAM_VSEL: 1;
+        uint32_t LOP_PON_PPU_VPON_PCSM_DVFS_LV_AUDIO_RAM_VSEL: 1;
+        uint32_t LOP_PON_PPU_VPON_PCSM_DVFS_LV_BTPHY_RAM_VSEL: 1;
+        uint32_t LOP_PON_PPU_VPON_PCSM_DVFS_LV_PLATFORM_ROM_VSEL: 1;
+        uint32_t LOP_PON_PPU_VPON_PCSM_DVFS_LV_RETSRAM_VSEL: 1;
+        uint32_t LOP_PON_PPU_VPON_PCSM_DVFS_LV_CACHE_VSEL: 1;
+        uint32_t LOP_PON_PPU_VPON_PCSM_DVFS_LV_AMU_RAM_VSEL: 1;
+        uint32_t RESERVED: 1;
+    };
+} AON_LOP_PON_PPU_VPON_PCSM_5_TYPE;
+
+/*0x4000_09bc AON_LOP_PON_PPU_VPON_PCSM_5*/
+#define AON_LOP_PON_PPU_VPON_PCSM_5_RESERVED_1_Pos                                                                       0U
+#define AON_LOP_PON_PPU_VPON_PCSM_5_RESERVED_1_Msk                                                                       (0x7UL << AON_LOP_PON_PPU_VPON_PCSM_5_RESERVED_1_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_5_LOP_PON_PPU_VPON_PCSM_DVFS_LV_TUNE_VDDCORE_Pos                                       3U
+#define AON_LOP_PON_PPU_VPON_PCSM_5_LOP_PON_PPU_VPON_PCSM_DVFS_LV_TUNE_VDDCORE_Msk                                       (0xFFUL << AON_LOP_PON_PPU_VPON_PCSM_5_LOP_PON_PPU_VPON_PCSM_DVFS_LV_TUNE_VDDCORE_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_5_LOP_PON_PPU_VPON_PCSM_DVFS_HV_TUNE_VDDCORE_Pos                                       11U
+#define AON_LOP_PON_PPU_VPON_PCSM_5_LOP_PON_PPU_VPON_PCSM_DVFS_HV_TUNE_VDDCORE_Msk                                       (0xFFUL << AON_LOP_PON_PPU_VPON_PCSM_5_LOP_PON_PPU_VPON_PCSM_DVFS_HV_TUNE_VDDCORE_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_5_LOP_PON_PPU_VPON_PCSM_DVFS_LV_BT_MAC_VSEL_Pos                                        19U
+#define AON_LOP_PON_PPU_VPON_PCSM_5_LOP_PON_PPU_VPON_PCSM_DVFS_LV_BT_MAC_VSEL_Msk                                        (0x1UL << AON_LOP_PON_PPU_VPON_PCSM_5_LOP_PON_PPU_VPON_PCSM_DVFS_LV_BT_MAC_VSEL_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_5_LOP_PON_PPU_VPON_PCSM_DVFS_LV_BT_MAC_CCMP_VSEL_Pos                                   20U
+#define AON_LOP_PON_PPU_VPON_PCSM_5_LOP_PON_PPU_VPON_PCSM_DVFS_LV_BT_MAC_CCMP_VSEL_Msk                                   (0x1UL << AON_LOP_PON_PPU_VPON_PCSM_5_LOP_PON_PPU_VPON_PCSM_DVFS_LV_BT_MAC_CCMP_VSEL_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_5_LOP_PON_PPU_VPON_PCSM_DVFS_LV_BUFFER_RAM_VSEL_Pos                                    21U
+#define AON_LOP_PON_PPU_VPON_PCSM_5_LOP_PON_PPU_VPON_PCSM_DVFS_LV_BUFFER_RAM_VSEL_Msk                                    (0x1UL << AON_LOP_PON_PPU_VPON_PCSM_5_LOP_PON_PPU_VPON_PCSM_DVFS_LV_BUFFER_RAM_VSEL_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_5_LOP_PON_PPU_VPON_PCSM_DVFS_LV_USB_RAM_VSEL_Pos                                       22U
+#define AON_LOP_PON_PPU_VPON_PCSM_5_LOP_PON_PPU_VPON_PCSM_DVFS_LV_USB_RAM_VSEL_Msk                                       (0x1UL << AON_LOP_PON_PPU_VPON_PCSM_5_LOP_PON_PPU_VPON_PCSM_DVFS_LV_USB_RAM_VSEL_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_5_LOP_PON_PPU_VPON_PCSM_DVFS_LV_CAN_RAM_VSEL_Pos                                       23U
+#define AON_LOP_PON_PPU_VPON_PCSM_5_LOP_PON_PPU_VPON_PCSM_DVFS_LV_CAN_RAM_VSEL_Msk                                       (0x1UL << AON_LOP_PON_PPU_VPON_PCSM_5_LOP_PON_PPU_VPON_PCSM_DVFS_LV_CAN_RAM_VSEL_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_5_LOP_PON_PPU_VPON_PCSM_DVFS_LV_CPU_RAM_VSEL_Pos                                       24U
+#define AON_LOP_PON_PPU_VPON_PCSM_5_LOP_PON_PPU_VPON_PCSM_DVFS_LV_CPU_RAM_VSEL_Msk                                       (0x1UL << AON_LOP_PON_PPU_VPON_PCSM_5_LOP_PON_PPU_VPON_PCSM_DVFS_LV_CPU_RAM_VSEL_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_5_LOP_PON_PPU_VPON_PCSM_DVFS_LV_AUDIO_RAM_VSEL_Pos                                     25U
+#define AON_LOP_PON_PPU_VPON_PCSM_5_LOP_PON_PPU_VPON_PCSM_DVFS_LV_AUDIO_RAM_VSEL_Msk                                     (0x1UL << AON_LOP_PON_PPU_VPON_PCSM_5_LOP_PON_PPU_VPON_PCSM_DVFS_LV_AUDIO_RAM_VSEL_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_5_LOP_PON_PPU_VPON_PCSM_DVFS_LV_BTPHY_RAM_VSEL_Pos                                     26U
+#define AON_LOP_PON_PPU_VPON_PCSM_5_LOP_PON_PPU_VPON_PCSM_DVFS_LV_BTPHY_RAM_VSEL_Msk                                     (0x1UL << AON_LOP_PON_PPU_VPON_PCSM_5_LOP_PON_PPU_VPON_PCSM_DVFS_LV_BTPHY_RAM_VSEL_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_5_LOP_PON_PPU_VPON_PCSM_DVFS_LV_PLATFORM_ROM_VSEL_Pos                                  27U
+#define AON_LOP_PON_PPU_VPON_PCSM_5_LOP_PON_PPU_VPON_PCSM_DVFS_LV_PLATFORM_ROM_VSEL_Msk                                  (0x1UL << AON_LOP_PON_PPU_VPON_PCSM_5_LOP_PON_PPU_VPON_PCSM_DVFS_LV_PLATFORM_ROM_VSEL_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_5_LOP_PON_PPU_VPON_PCSM_DVFS_LV_RETSRAM_VSEL_Pos                                       28U
+#define AON_LOP_PON_PPU_VPON_PCSM_5_LOP_PON_PPU_VPON_PCSM_DVFS_LV_RETSRAM_VSEL_Msk                                       (0x1UL << AON_LOP_PON_PPU_VPON_PCSM_5_LOP_PON_PPU_VPON_PCSM_DVFS_LV_RETSRAM_VSEL_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_5_LOP_PON_PPU_VPON_PCSM_DVFS_LV_CACHE_VSEL_Pos                                         29U
+#define AON_LOP_PON_PPU_VPON_PCSM_5_LOP_PON_PPU_VPON_PCSM_DVFS_LV_CACHE_VSEL_Msk                                         (0x1UL << AON_LOP_PON_PPU_VPON_PCSM_5_LOP_PON_PPU_VPON_PCSM_DVFS_LV_CACHE_VSEL_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_5_LOP_PON_PPU_VPON_PCSM_DVFS_LV_AMU_RAM_VSEL_Pos                                       30U
+#define AON_LOP_PON_PPU_VPON_PCSM_5_LOP_PON_PPU_VPON_PCSM_DVFS_LV_AMU_RAM_VSEL_Msk                                       (0x1UL << AON_LOP_PON_PPU_VPON_PCSM_5_LOP_PON_PPU_VPON_PCSM_DVFS_LV_AMU_RAM_VSEL_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_5_RESERVED_Pos                                                                         31U
+#define AON_LOP_PON_PPU_VPON_PCSM_5_RESERVED_Msk                                                                         (0x1UL << AON_LOP_PON_PPU_VPON_PCSM_5_RESERVED_Pos)
+
+/* 0x9C0    0x4000_09c0
+    3:0     R/W     LOP_PON_PPU_VPON_PCSM_SWR4_DELAY                            4'b1010
+    7:4     R/W     LOP_PON_PPU_VPON_PCSM_SWR3_DELAY                            4'b0000
+    11:8    R/W     LOP_PON_PPU_VPON_PCSM_SWR2_DELAY                            4'b0010
+    15:12   R/W     LOP_PON_PPU_VPON_PCSM_SWR1_DELAY                            4'b0011
+    23:16   R/W     LOP_PON_PPU_VPON_PCSM_DVFS_LV_TUNE_VDDANA                   8'b01111010
+    31:24   R/W     LOP_PON_PPU_VPON_PCSM_DVFS_HV_TUNE_VDDANA                   8'b01111010
+ */
+typedef union _AON_LOP_PON_PPU_VPON_PCSM_6_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t LOP_PON_PPU_VPON_PCSM_SWR4_DELAY: 4;
+        uint32_t LOP_PON_PPU_VPON_PCSM_SWR3_DELAY: 4;
+        uint32_t LOP_PON_PPU_VPON_PCSM_SWR2_DELAY: 4;
+        uint32_t LOP_PON_PPU_VPON_PCSM_SWR1_DELAY: 4;
+        uint32_t LOP_PON_PPU_VPON_PCSM_DVFS_LV_TUNE_VDDANA: 8;
+        uint32_t LOP_PON_PPU_VPON_PCSM_DVFS_HV_TUNE_VDDANA: 8;
+    };
+} AON_LOP_PON_PPU_VPON_PCSM_6_TYPE;
+
+/*0x4000_09c0 AON_LOP_PON_PPU_VPON_PCSM_6*/
+#define AON_LOP_PON_PPU_VPON_PCSM_6_LOP_PON_PPU_VPON_PCSM_SWR4_DELAY_Pos                                                 0U
+#define AON_LOP_PON_PPU_VPON_PCSM_6_LOP_PON_PPU_VPON_PCSM_SWR4_DELAY_Msk                                                 (0xFUL << AON_LOP_PON_PPU_VPON_PCSM_6_LOP_PON_PPU_VPON_PCSM_SWR4_DELAY_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_6_LOP_PON_PPU_VPON_PCSM_SWR3_DELAY_Pos                                                 4U
+#define AON_LOP_PON_PPU_VPON_PCSM_6_LOP_PON_PPU_VPON_PCSM_SWR3_DELAY_Msk                                                 (0xFUL << AON_LOP_PON_PPU_VPON_PCSM_6_LOP_PON_PPU_VPON_PCSM_SWR3_DELAY_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_6_LOP_PON_PPU_VPON_PCSM_SWR2_DELAY_Pos                                                 8U
+#define AON_LOP_PON_PPU_VPON_PCSM_6_LOP_PON_PPU_VPON_PCSM_SWR2_DELAY_Msk                                                 (0xFUL << AON_LOP_PON_PPU_VPON_PCSM_6_LOP_PON_PPU_VPON_PCSM_SWR2_DELAY_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_6_LOP_PON_PPU_VPON_PCSM_SWR1_DELAY_Pos                                                 12U
+#define AON_LOP_PON_PPU_VPON_PCSM_6_LOP_PON_PPU_VPON_PCSM_SWR1_DELAY_Msk                                                 (0xFUL << AON_LOP_PON_PPU_VPON_PCSM_6_LOP_PON_PPU_VPON_PCSM_SWR1_DELAY_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_6_LOP_PON_PPU_VPON_PCSM_DVFS_LV_TUNE_VDDANA_Pos                                        16U
+#define AON_LOP_PON_PPU_VPON_PCSM_6_LOP_PON_PPU_VPON_PCSM_DVFS_LV_TUNE_VDDANA_Msk                                        (0xFFUL << AON_LOP_PON_PPU_VPON_PCSM_6_LOP_PON_PPU_VPON_PCSM_DVFS_LV_TUNE_VDDANA_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_6_LOP_PON_PPU_VPON_PCSM_DVFS_HV_TUNE_VDDANA_Pos                                        24U
+#define AON_LOP_PON_PPU_VPON_PCSM_6_LOP_PON_PPU_VPON_PCSM_DVFS_HV_TUNE_VDDANA_Msk                                        (0xFFUL << AON_LOP_PON_PPU_VPON_PCSM_6_LOP_PON_PPU_VPON_PCSM_DVFS_HV_TUNE_VDDANA_Pos)
+
+/* 0x9C4    0x4000_09c4
+    1:0     R/W     LOP_PON_PPU_VPON_PCSM_LDO2_DELAY_MSB                        2'b01
+    5:2     R/W     LOP_PON_PPU_VPON_PCSM_DVFS_LV_DELAY                         4'b0001
+    9:6     R/W     LOP_PON_PPU_VPON_PCSM_DVFS_HV_DELAY                         4'b0000
+    13:10   R/W     LOP_PON_PPU_VPON_PCSM_2_DELAY                               4'b0000
+    17:14   R/W     LOP_PON_PPU_VPON_PCSM_1_DELAY                               4'b0000
+    21:18   R/W     LOP_PON_PPU_VPON_PCSM_LDO2_DELAY                            4'b0001
+    25:22   R/W     LOP_PON_PPU_VPON_PCSM_LDO1_DELAY                            4'b0000
+    31:26   R/W     LOP_PON_PPU_VPON_PCSM_SWR5_DELAY                            6'b010001
+ */
+typedef union _AON_LOP_PON_PPU_VPON_PCSM_7_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t LOP_PON_PPU_VPON_PCSM_LDO2_DELAY_MSB: 2;
+        uint32_t LOP_PON_PPU_VPON_PCSM_DVFS_LV_DELAY: 4;
+        uint32_t LOP_PON_PPU_VPON_PCSM_DVFS_HV_DELAY: 4;
+        uint32_t LOP_PON_PPU_VPON_PCSM_2_DELAY: 4;
+        uint32_t LOP_PON_PPU_VPON_PCSM_1_DELAY: 4;
+        uint32_t LOP_PON_PPU_VPON_PCSM_LDO2_DELAY: 4;
+        uint32_t LOP_PON_PPU_VPON_PCSM_LDO1_DELAY: 4;
+        uint32_t LOP_PON_PPU_VPON_PCSM_SWR5_DELAY: 6;
+    };
+} AON_LOP_PON_PPU_VPON_PCSM_7_TYPE;
+
+/*0x4000_09c4 AON_LOP_PON_PPU_VPON_PCSM_7*/
+#define AON_LOP_PON_PPU_VPON_PCSM_7_LOP_PON_PPU_VPON_PCSM_LDO2_DELAY_MSB_Pos                                             0U
+#define AON_LOP_PON_PPU_VPON_PCSM_7_LOP_PON_PPU_VPON_PCSM_LDO2_DELAY_MSB_Msk                                             (0x3UL << AON_LOP_PON_PPU_VPON_PCSM_7_LOP_PON_PPU_VPON_PCSM_LDO2_DELAY_MSB_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_7_LOP_PON_PPU_VPON_PCSM_DVFS_LV_DELAY_Pos                                              2U
+#define AON_LOP_PON_PPU_VPON_PCSM_7_LOP_PON_PPU_VPON_PCSM_DVFS_LV_DELAY_Msk                                              (0xFUL << AON_LOP_PON_PPU_VPON_PCSM_7_LOP_PON_PPU_VPON_PCSM_DVFS_LV_DELAY_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_7_LOP_PON_PPU_VPON_PCSM_DVFS_HV_DELAY_Pos                                              6U
+#define AON_LOP_PON_PPU_VPON_PCSM_7_LOP_PON_PPU_VPON_PCSM_DVFS_HV_DELAY_Msk                                              (0xFUL << AON_LOP_PON_PPU_VPON_PCSM_7_LOP_PON_PPU_VPON_PCSM_DVFS_HV_DELAY_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_7_LOP_PON_PPU_VPON_PCSM_2_DELAY_Pos                                                    10U
+#define AON_LOP_PON_PPU_VPON_PCSM_7_LOP_PON_PPU_VPON_PCSM_2_DELAY_Msk                                                    (0xFUL << AON_LOP_PON_PPU_VPON_PCSM_7_LOP_PON_PPU_VPON_PCSM_2_DELAY_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_7_LOP_PON_PPU_VPON_PCSM_1_DELAY_Pos                                                    14U
+#define AON_LOP_PON_PPU_VPON_PCSM_7_LOP_PON_PPU_VPON_PCSM_1_DELAY_Msk                                                    (0xFUL << AON_LOP_PON_PPU_VPON_PCSM_7_LOP_PON_PPU_VPON_PCSM_1_DELAY_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_7_LOP_PON_PPU_VPON_PCSM_LDO2_DELAY_Pos                                                 18U
+#define AON_LOP_PON_PPU_VPON_PCSM_7_LOP_PON_PPU_VPON_PCSM_LDO2_DELAY_Msk                                                 (0xFUL << AON_LOP_PON_PPU_VPON_PCSM_7_LOP_PON_PPU_VPON_PCSM_LDO2_DELAY_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_7_LOP_PON_PPU_VPON_PCSM_LDO1_DELAY_Pos                                                 22U
+#define AON_LOP_PON_PPU_VPON_PCSM_7_LOP_PON_PPU_VPON_PCSM_LDO1_DELAY_Msk                                                 (0xFUL << AON_LOP_PON_PPU_VPON_PCSM_7_LOP_PON_PPU_VPON_PCSM_LDO1_DELAY_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_7_LOP_PON_PPU_VPON_PCSM_SWR5_DELAY_Pos                                                 26U
+#define AON_LOP_PON_PPU_VPON_PCSM_7_LOP_PON_PPU_VPON_PCSM_SWR5_DELAY_Msk                                                 (0x3FUL << AON_LOP_PON_PPU_VPON_PCSM_7_LOP_PON_PPU_VPON_PCSM_SWR5_DELAY_Pos)
+
+/* 0x9C8    0x4000_09c8
+    13:0    R/W     RESERVED_2                                                  14'h0
+    14      R/W     RESERVED_1                                                  1'b0
+    15      R/W     LOP_PON_PPU_VPON_PCSM_LDO_POW_LDOANA_PARKING_START          1'b0
+    16      R/W     RESERVED                                                    1'b0
+    20:17   R/W     LOP_PON_PPU_VPON_PCSM_DVFS_HV_ACCEPT_DELAY                  4'b0001
+    21      R/W     LOP_PON_PPU_VPON_PCSM_ENB_AUTO_PS                           1'b1
+    22      R/W     LOP_PON_PPU_VPON_PCSM_SEL_SYNC2                             1'b1
+    23      R/W     LOP_PON_PPU_VPON_PCSM_EN_SYNC2                              1'b0
+    24      R/W     LOP_PON_PPU_VPON_PCSM_SEL_VO3CMPHQ2_B                       1'b1
+    29:25   R/W     LOP_PON_PPU_VPON_PCSM_SEL_VREF_VDDPA_HQ2                    5'b11000
+    30      R/W     LOP_PON_PPU_VPON_PCSM_EN_VO3CMPHQ2                          1'b0
+    31      R/W     LOP_PON_PPU_VPON_PCSM_EN_VO3HQ2BETA                         1'b1
+ */
+typedef union _AON_LOP_PON_PPU_VPON_PCSM_8_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED_2: 14;
+        uint32_t RESERVED_1: 1;
+        uint32_t LOP_PON_PPU_VPON_PCSM_LDO_POW_LDOANA_PARKING_START: 1;
+        uint32_t RESERVED: 1;
+        uint32_t LOP_PON_PPU_VPON_PCSM_DVFS_HV_ACCEPT_DELAY: 4;
+        uint32_t LOP_PON_PPU_VPON_PCSM_ENB_AUTO_PS: 1;
+        uint32_t LOP_PON_PPU_VPON_PCSM_SEL_SYNC2: 1;
+        uint32_t LOP_PON_PPU_VPON_PCSM_EN_SYNC2: 1;
+        uint32_t LOP_PON_PPU_VPON_PCSM_SEL_VO3CMPHQ2_B: 1;
+        uint32_t LOP_PON_PPU_VPON_PCSM_SEL_VREF_VDDPA_HQ2: 5;
+        uint32_t LOP_PON_PPU_VPON_PCSM_EN_VO3CMPHQ2: 1;
+        uint32_t LOP_PON_PPU_VPON_PCSM_EN_VO3HQ2BETA: 1;
+    };
+} AON_LOP_PON_PPU_VPON_PCSM_8_TYPE;
+
+/*0x4000_09c8 AON_LOP_PON_PPU_VPON_PCSM_8*/
+#define AON_LOP_PON_PPU_VPON_PCSM_8_RESERVED_2_Pos                                                                       0U
+#define AON_LOP_PON_PPU_VPON_PCSM_8_RESERVED_2_Msk                                                                       (0x3FFFUL << AON_LOP_PON_PPU_VPON_PCSM_8_RESERVED_2_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_8_RESERVED_1_Pos                                                                       14U
+#define AON_LOP_PON_PPU_VPON_PCSM_8_RESERVED_1_Msk                                                                       (0x1UL << AON_LOP_PON_PPU_VPON_PCSM_8_RESERVED_1_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_8_LOP_PON_PPU_VPON_PCSM_LDO_POW_LDOANA_PARKING_START_Pos                               15U
+#define AON_LOP_PON_PPU_VPON_PCSM_8_LOP_PON_PPU_VPON_PCSM_LDO_POW_LDOANA_PARKING_START_Msk                               (0x1UL << AON_LOP_PON_PPU_VPON_PCSM_8_LOP_PON_PPU_VPON_PCSM_LDO_POW_LDOANA_PARKING_START_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_8_RESERVED_Pos                                                                         16U
+#define AON_LOP_PON_PPU_VPON_PCSM_8_RESERVED_Msk                                                                         (0x1UL << AON_LOP_PON_PPU_VPON_PCSM_8_RESERVED_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_8_LOP_PON_PPU_VPON_PCSM_DVFS_HV_ACCEPT_DELAY_Pos                                       17U
+#define AON_LOP_PON_PPU_VPON_PCSM_8_LOP_PON_PPU_VPON_PCSM_DVFS_HV_ACCEPT_DELAY_Msk                                       (0xFUL << AON_LOP_PON_PPU_VPON_PCSM_8_LOP_PON_PPU_VPON_PCSM_DVFS_HV_ACCEPT_DELAY_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_8_LOP_PON_PPU_VPON_PCSM_ENB_AUTO_PS_Pos                                                21U
+#define AON_LOP_PON_PPU_VPON_PCSM_8_LOP_PON_PPU_VPON_PCSM_ENB_AUTO_PS_Msk                                                (0x1UL << AON_LOP_PON_PPU_VPON_PCSM_8_LOP_PON_PPU_VPON_PCSM_ENB_AUTO_PS_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_8_LOP_PON_PPU_VPON_PCSM_SEL_SYNC2_Pos                                                  22U
+#define AON_LOP_PON_PPU_VPON_PCSM_8_LOP_PON_PPU_VPON_PCSM_SEL_SYNC2_Msk                                                  (0x1UL << AON_LOP_PON_PPU_VPON_PCSM_8_LOP_PON_PPU_VPON_PCSM_SEL_SYNC2_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_8_LOP_PON_PPU_VPON_PCSM_EN_SYNC2_Pos                                                   23U
+#define AON_LOP_PON_PPU_VPON_PCSM_8_LOP_PON_PPU_VPON_PCSM_EN_SYNC2_Msk                                                   (0x1UL << AON_LOP_PON_PPU_VPON_PCSM_8_LOP_PON_PPU_VPON_PCSM_EN_SYNC2_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_8_LOP_PON_PPU_VPON_PCSM_SEL_VO3CMPHQ2_B_Pos                                            24U
+#define AON_LOP_PON_PPU_VPON_PCSM_8_LOP_PON_PPU_VPON_PCSM_SEL_VO3CMPHQ2_B_Msk                                            (0x1UL << AON_LOP_PON_PPU_VPON_PCSM_8_LOP_PON_PPU_VPON_PCSM_SEL_VO3CMPHQ2_B_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_8_LOP_PON_PPU_VPON_PCSM_SEL_VREF_VDDPA_HQ2_Pos                                         25U
+#define AON_LOP_PON_PPU_VPON_PCSM_8_LOP_PON_PPU_VPON_PCSM_SEL_VREF_VDDPA_HQ2_Msk                                         (0x1FUL << AON_LOP_PON_PPU_VPON_PCSM_8_LOP_PON_PPU_VPON_PCSM_SEL_VREF_VDDPA_HQ2_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_8_LOP_PON_PPU_VPON_PCSM_EN_VO3CMPHQ2_Pos                                               30U
+#define AON_LOP_PON_PPU_VPON_PCSM_8_LOP_PON_PPU_VPON_PCSM_EN_VO3CMPHQ2_Msk                                               (0x1UL << AON_LOP_PON_PPU_VPON_PCSM_8_LOP_PON_PPU_VPON_PCSM_EN_VO3CMPHQ2_Pos)
+
+#define AON_LOP_PON_PPU_VPON_PCSM_8_LOP_PON_PPU_VPON_PCSM_EN_VO3HQ2BETA_Pos                                              31U
+#define AON_LOP_PON_PPU_VPON_PCSM_8_LOP_PON_PPU_VPON_PCSM_EN_VO3HQ2BETA_Msk                                              (0x1UL << AON_LOP_PON_PPU_VPON_PCSM_8_LOP_PON_PPU_VPON_PCSM_EN_VO3HQ2BETA_Pos)
+
+/* 0x9CC    0x4000_09cc
+    1:0     R/W     RESERVED                                                    2'b00
+    5:2     R/W     LOP_PON_PPU_VCORE1_PCSM_2_DELAY                             4'b0001
+    9:6     R/W     LOP_PON_PLL1_PCSM_3_DELAY                                   4'b0110
+    13:10   R/W     LOP_PON_PLL1_PCSM_2_DELAY                                   4'b0001
+    17:14   R/W     LOP_PON_PLL1_PCSM_1_DELAY                                   4'b0011
+    18      R/W     LOP_PON_PLL1_PCSM_PLL1_LDO_DIG_SW_LDO2PWRCUT                1'b0
+    19      R/W     LOP_PON_PLL1_PCSM_PLL1_LDO_ANA_SW_LDO2PWRCUT                1'b0
+    23:20   R/W     LOP_PON_OSC80_PCSM_1_DELAY                                  4'b0111
+    31:24   R/W     LOP_PON_XTAL40_PCSM_2_DELAY                                 8'b00011100
+ */
+typedef union _AON_LOP_PON_OTHER_PCSM_SWAP_PCSM_1_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED: 2;
+        uint32_t LOP_PON_PPU_VCORE1_PCSM_2_DELAY: 4;
+        uint32_t LOP_PON_PLL1_PCSM_3_DELAY: 4;
+        uint32_t LOP_PON_PLL1_PCSM_2_DELAY: 4;
+        uint32_t LOP_PON_PLL1_PCSM_1_DELAY: 4;
+        uint32_t LOP_PON_PLL1_PCSM_PLL1_LDO_DIG_SW_LDO2PWRCUT: 1;
+        uint32_t LOP_PON_PLL1_PCSM_PLL1_LDO_ANA_SW_LDO2PWRCUT: 1;
+        uint32_t LOP_PON_OSC80_PCSM_1_DELAY: 4;
+        uint32_t LOP_PON_XTAL40_PCSM_2_DELAY: 8;
+    };
+} AON_LOP_PON_OTHER_PCSM_SWAP_PCSM_1_TYPE;
+
+/*0x4000_09cc AON_LOP_PON_OTHER_PCSM_SWAP_PCSM_1*/
+#define AON_LOP_PON_OTHER_PCSM_SWAP_PCSM_1_RESERVED_Pos                                                                  0U
+#define AON_LOP_PON_OTHER_PCSM_SWAP_PCSM_1_RESERVED_Msk                                                                  (0x3UL << AON_LOP_PON_OTHER_PCSM_SWAP_PCSM_1_RESERVED_Pos)
+
+#define AON_LOP_PON_OTHER_PCSM_SWAP_PCSM_1_LOP_PON_PPU_VCORE1_PCSM_2_DELAY_Pos                                           2U
+#define AON_LOP_PON_OTHER_PCSM_SWAP_PCSM_1_LOP_PON_PPU_VCORE1_PCSM_2_DELAY_Msk                                           (0xFUL << AON_LOP_PON_OTHER_PCSM_SWAP_PCSM_1_LOP_PON_PPU_VCORE1_PCSM_2_DELAY_Pos)
+
+#define AON_LOP_PON_OTHER_PCSM_SWAP_PCSM_1_LOP_PON_PLL1_PCSM_3_DELAY_Pos                                                 6U
+#define AON_LOP_PON_OTHER_PCSM_SWAP_PCSM_1_LOP_PON_PLL1_PCSM_3_DELAY_Msk                                                 (0xFUL << AON_LOP_PON_OTHER_PCSM_SWAP_PCSM_1_LOP_PON_PLL1_PCSM_3_DELAY_Pos)
+
+#define AON_LOP_PON_OTHER_PCSM_SWAP_PCSM_1_LOP_PON_PLL1_PCSM_2_DELAY_Pos                                                 10U
+#define AON_LOP_PON_OTHER_PCSM_SWAP_PCSM_1_LOP_PON_PLL1_PCSM_2_DELAY_Msk                                                 (0xFUL << AON_LOP_PON_OTHER_PCSM_SWAP_PCSM_1_LOP_PON_PLL1_PCSM_2_DELAY_Pos)
+
+#define AON_LOP_PON_OTHER_PCSM_SWAP_PCSM_1_LOP_PON_PLL1_PCSM_1_DELAY_Pos                                                 14U
+#define AON_LOP_PON_OTHER_PCSM_SWAP_PCSM_1_LOP_PON_PLL1_PCSM_1_DELAY_Msk                                                 (0xFUL << AON_LOP_PON_OTHER_PCSM_SWAP_PCSM_1_LOP_PON_PLL1_PCSM_1_DELAY_Pos)
+
+#define AON_LOP_PON_OTHER_PCSM_SWAP_PCSM_1_LOP_PON_PLL1_PCSM_PLL1_LDO_DIG_SW_LDO2PWRCUT_Pos                              18U
+#define AON_LOP_PON_OTHER_PCSM_SWAP_PCSM_1_LOP_PON_PLL1_PCSM_PLL1_LDO_DIG_SW_LDO2PWRCUT_Msk                              (0x1UL << AON_LOP_PON_OTHER_PCSM_SWAP_PCSM_1_LOP_PON_PLL1_PCSM_PLL1_LDO_DIG_SW_LDO2PWRCUT_Pos)
+
+#define AON_LOP_PON_OTHER_PCSM_SWAP_PCSM_1_LOP_PON_PLL1_PCSM_PLL1_LDO_ANA_SW_LDO2PWRCUT_Pos                              19U
+#define AON_LOP_PON_OTHER_PCSM_SWAP_PCSM_1_LOP_PON_PLL1_PCSM_PLL1_LDO_ANA_SW_LDO2PWRCUT_Msk                              (0x1UL << AON_LOP_PON_OTHER_PCSM_SWAP_PCSM_1_LOP_PON_PLL1_PCSM_PLL1_LDO_ANA_SW_LDO2PWRCUT_Pos)
+
+#define AON_LOP_PON_OTHER_PCSM_SWAP_PCSM_1_LOP_PON_OSC80_PCSM_1_DELAY_Pos                                                20U
+#define AON_LOP_PON_OTHER_PCSM_SWAP_PCSM_1_LOP_PON_OSC80_PCSM_1_DELAY_Msk                                                (0xFUL << AON_LOP_PON_OTHER_PCSM_SWAP_PCSM_1_LOP_PON_OSC80_PCSM_1_DELAY_Pos)
+
+#define AON_LOP_PON_OTHER_PCSM_SWAP_PCSM_1_LOP_PON_XTAL40_PCSM_2_DELAY_Pos                                               24U
+#define AON_LOP_PON_OTHER_PCSM_SWAP_PCSM_1_LOP_PON_XTAL40_PCSM_2_DELAY_Msk                                               (0xFFUL << AON_LOP_PON_OTHER_PCSM_SWAP_PCSM_1_LOP_PON_XTAL40_PCSM_2_DELAY_Pos)
+
+/* 0x9D0    0x4000_09d0
+    2:0     R/W     RESERVED_1                                                  3'b0
+    5:3     R/W     RESERVED                                                    3'b0
+    6       R/W     LOP_PON_VCORE_OP1_PADRV_PCUT_CTRL_SEL                       1'b1
+    10:7    R/W     LOP_PON_VCORE_OP1_5_PCSM_DELAY                              4'b0000
+    14:11   R/W     LOP_PON_VCORE_OP1_4_PCSM_DELAY                              4'b1111
+    18:15   R/W     LOP_PON_VCORE_OP1_3_PCSM_DELAY                              4'b0001
+    22:19   R/W     LOP_PON_VCORE_OP1_2_PCSM_DELAY                              4'b0001
+    26:23   R/W     LOP_PON_VCORE_OP1_1_PCSM_DELAY                              4'b0001
+    27      R/W     LOP_PON_VCORE_OP1_PCSM_SPIC_PDEX_CMD                        1'b0
+    28      R/W     LOP_PON_VCORE_OP1_PCSM_SPIC_PDEX_REQ                        1'b1
+    29      R/W     LOP_PON_VCORE_OP1_PCSM_SEL_EFLASH_HV18                      1'b0
+    30      R/W     LOP_PON_VCORE_OP1_PCSM_SEL_EFLASH_HV25                      1'b1
+    31      R/W     LOP_PON_PPU_VCORE1_PCSM_REG_ENLPM                           1'b0
+ */
+typedef union _AON_LOP_PON_OTHER_PCSM_SWAP_PCSM_2_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED_1: 3;
+        uint32_t RESERVED: 3;
+        uint32_t LOP_PON_VCORE_OP1_PADRV_PCUT_CTRL_SEL: 1;
+        uint32_t LOP_PON_VCORE_OP1_5_PCSM_DELAY: 4;
+        uint32_t LOP_PON_VCORE_OP1_4_PCSM_DELAY: 4;
+        uint32_t LOP_PON_VCORE_OP1_3_PCSM_DELAY: 4;
+        uint32_t LOP_PON_VCORE_OP1_2_PCSM_DELAY: 4;
+        uint32_t LOP_PON_VCORE_OP1_1_PCSM_DELAY: 4;
+        uint32_t LOP_PON_VCORE_OP1_PCSM_SPIC_PDEX_CMD: 1;
+        uint32_t LOP_PON_VCORE_OP1_PCSM_SPIC_PDEX_REQ: 1;
+        uint32_t LOP_PON_VCORE_OP1_PCSM_SEL_EFLASH_HV18: 1;
+        uint32_t LOP_PON_VCORE_OP1_PCSM_SEL_EFLASH_HV25: 1;
+        uint32_t LOP_PON_PPU_VCORE1_PCSM_REG_ENLPM: 1;
+    };
+} AON_LOP_PON_OTHER_PCSM_SWAP_PCSM_2_TYPE;
+
+/*0x4000_09d0 AON_LOP_PON_OTHER_PCSM_SWAP_PCSM_2*/
+#define AON_LOP_PON_OTHER_PCSM_SWAP_PCSM_2_RESERVED_1_Pos                                                                0U
+#define AON_LOP_PON_OTHER_PCSM_SWAP_PCSM_2_RESERVED_1_Msk                                                                (0x7UL << AON_LOP_PON_OTHER_PCSM_SWAP_PCSM_2_RESERVED_1_Pos)
+
+#define AON_LOP_PON_OTHER_PCSM_SWAP_PCSM_2_RESERVED_Pos                                                                  3U
+#define AON_LOP_PON_OTHER_PCSM_SWAP_PCSM_2_RESERVED_Msk                                                                  (0x7UL << AON_LOP_PON_OTHER_PCSM_SWAP_PCSM_2_RESERVED_Pos)
+
+#define AON_LOP_PON_OTHER_PCSM_SWAP_PCSM_2_LOP_PON_VCORE_OP1_PADRV_PCUT_CTRL_SEL_Pos                                     6U
+#define AON_LOP_PON_OTHER_PCSM_SWAP_PCSM_2_LOP_PON_VCORE_OP1_PADRV_PCUT_CTRL_SEL_Msk                                     (0x1UL << AON_LOP_PON_OTHER_PCSM_SWAP_PCSM_2_LOP_PON_VCORE_OP1_PADRV_PCUT_CTRL_SEL_Pos)
+
+#define AON_LOP_PON_OTHER_PCSM_SWAP_PCSM_2_LOP_PON_VCORE_OP1_5_PCSM_DELAY_Pos                                            7U
+#define AON_LOP_PON_OTHER_PCSM_SWAP_PCSM_2_LOP_PON_VCORE_OP1_5_PCSM_DELAY_Msk                                            (0xFUL << AON_LOP_PON_OTHER_PCSM_SWAP_PCSM_2_LOP_PON_VCORE_OP1_5_PCSM_DELAY_Pos)
+
+#define AON_LOP_PON_OTHER_PCSM_SWAP_PCSM_2_LOP_PON_VCORE_OP1_4_PCSM_DELAY_Pos                                            11U
+#define AON_LOP_PON_OTHER_PCSM_SWAP_PCSM_2_LOP_PON_VCORE_OP1_4_PCSM_DELAY_Msk                                            (0xFUL << AON_LOP_PON_OTHER_PCSM_SWAP_PCSM_2_LOP_PON_VCORE_OP1_4_PCSM_DELAY_Pos)
+
+#define AON_LOP_PON_OTHER_PCSM_SWAP_PCSM_2_LOP_PON_VCORE_OP1_3_PCSM_DELAY_Pos                                            15U
+#define AON_LOP_PON_OTHER_PCSM_SWAP_PCSM_2_LOP_PON_VCORE_OP1_3_PCSM_DELAY_Msk                                            (0xFUL << AON_LOP_PON_OTHER_PCSM_SWAP_PCSM_2_LOP_PON_VCORE_OP1_3_PCSM_DELAY_Pos)
+
+#define AON_LOP_PON_OTHER_PCSM_SWAP_PCSM_2_LOP_PON_VCORE_OP1_2_PCSM_DELAY_Pos                                            19U
+#define AON_LOP_PON_OTHER_PCSM_SWAP_PCSM_2_LOP_PON_VCORE_OP1_2_PCSM_DELAY_Msk                                            (0xFUL << AON_LOP_PON_OTHER_PCSM_SWAP_PCSM_2_LOP_PON_VCORE_OP1_2_PCSM_DELAY_Pos)
+
+#define AON_LOP_PON_OTHER_PCSM_SWAP_PCSM_2_LOP_PON_VCORE_OP1_1_PCSM_DELAY_Pos                                            23U
+#define AON_LOP_PON_OTHER_PCSM_SWAP_PCSM_2_LOP_PON_VCORE_OP1_1_PCSM_DELAY_Msk                                            (0xFUL << AON_LOP_PON_OTHER_PCSM_SWAP_PCSM_2_LOP_PON_VCORE_OP1_1_PCSM_DELAY_Pos)
+
+#define AON_LOP_PON_OTHER_PCSM_SWAP_PCSM_2_LOP_PON_VCORE_OP1_PCSM_SPIC_PDEX_CMD_Pos                                      27U
+#define AON_LOP_PON_OTHER_PCSM_SWAP_PCSM_2_LOP_PON_VCORE_OP1_PCSM_SPIC_PDEX_CMD_Msk                                      (0x1UL << AON_LOP_PON_OTHER_PCSM_SWAP_PCSM_2_LOP_PON_VCORE_OP1_PCSM_SPIC_PDEX_CMD_Pos)
+
+#define AON_LOP_PON_OTHER_PCSM_SWAP_PCSM_2_LOP_PON_VCORE_OP1_PCSM_SPIC_PDEX_REQ_Pos                                      28U
+#define AON_LOP_PON_OTHER_PCSM_SWAP_PCSM_2_LOP_PON_VCORE_OP1_PCSM_SPIC_PDEX_REQ_Msk                                      (0x1UL << AON_LOP_PON_OTHER_PCSM_SWAP_PCSM_2_LOP_PON_VCORE_OP1_PCSM_SPIC_PDEX_REQ_Pos)
+
+#define AON_LOP_PON_OTHER_PCSM_SWAP_PCSM_2_LOP_PON_VCORE_OP1_PCSM_SEL_EFLASH_HV18_Pos                                    29U
+#define AON_LOP_PON_OTHER_PCSM_SWAP_PCSM_2_LOP_PON_VCORE_OP1_PCSM_SEL_EFLASH_HV18_Msk                                    (0x1UL << AON_LOP_PON_OTHER_PCSM_SWAP_PCSM_2_LOP_PON_VCORE_OP1_PCSM_SEL_EFLASH_HV18_Pos)
+
+#define AON_LOP_PON_OTHER_PCSM_SWAP_PCSM_2_LOP_PON_VCORE_OP1_PCSM_SEL_EFLASH_HV25_Pos                                    30U
+#define AON_LOP_PON_OTHER_PCSM_SWAP_PCSM_2_LOP_PON_VCORE_OP1_PCSM_SEL_EFLASH_HV25_Msk                                    (0x1UL << AON_LOP_PON_OTHER_PCSM_SWAP_PCSM_2_LOP_PON_VCORE_OP1_PCSM_SEL_EFLASH_HV25_Pos)
+
+#define AON_LOP_PON_OTHER_PCSM_SWAP_PCSM_2_LOP_PON_PPU_VCORE1_PCSM_REG_ENLPM_Pos                                         31U
+#define AON_LOP_PON_OTHER_PCSM_SWAP_PCSM_2_LOP_PON_PPU_VCORE1_PCSM_REG_ENLPM_Msk                                         (0x1UL << AON_LOP_PON_OTHER_PCSM_SWAP_PCSM_2_LOP_PON_PPU_VCORE1_PCSM_REG_ENLPM_Pos)
+
+/* 0xA30    0x4000_0a30
+    7:0     R/W     RESERVED_3                                                  8'h0
+    8       R/W     RESERVED_2                                                  1'b0
+    9       R/W     RESERVED_1                                                  1'b0
+    10      R/W     LOP_POF_OFF_PPU_VPON_PCSM_EN_CMP_LQ_VDDANA                  1'b1
+    11      R/W     LOP_POF_OFF_PPU_VPON_PCSM_EN_CMP_HQ_VDDANA                  1'b0
+    16:12   R/W     LOP_POF_OFF_PPU_VPON_PCSM_SEL_VREF_VDDANA_LQ                5'b01001
+    24:17   R/W     LOP_POF_OFF_PPU_VPON_PCSM_TUNE_VDDANA                       8'b01111010
+    25      R/W     LOP_POF_OFF_PPU_VPON_PCSM_POW_VDIV_LQ_VDDANA                1'b1
+    26      R/W     LOP_POF_OFF_PPU_VPON_PCSM_POW_VDIV_HQ_VDDANA                1'b0
+    27      R/W     LOP_POF_OFF_PPU_VPON_PCSM_EN_DMYLOAD_VDDANA                 1'b0
+    28      R/W     LOP_POF_OFF_PPU_VPON_PCSM_POW_VDDANA_DET                    1'b1
+    29      R/W     LOP_POF_OFF_PPU_VPON_PCSM_ENCCM_OUT_VDDANA                  1'b1
+    30      R/W     RESERVED                                                    1'b0
+    31      R/W     LOP_POF_OSC128K_PCSM_POW_32KOSC                             1'b1
+ */
+typedef union _AON_LOP_POF_CLK_CTRL_OSC128K_OSC10_PCSM_1_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED_3: 8;
+        uint32_t RESERVED_2: 1;
+        uint32_t RESERVED_1: 1;
+        uint32_t LOP_POF_OFF_PPU_VPON_PCSM_EN_CMP_LQ_VDDANA: 1;
+        uint32_t LOP_POF_OFF_PPU_VPON_PCSM_EN_CMP_HQ_VDDANA: 1;
+        uint32_t LOP_POF_OFF_PPU_VPON_PCSM_SEL_VREF_VDDANA_LQ: 5;
+        uint32_t LOP_POF_OFF_PPU_VPON_PCSM_TUNE_VDDANA: 8;
+        uint32_t LOP_POF_OFF_PPU_VPON_PCSM_POW_VDIV_LQ_VDDANA: 1;
+        uint32_t LOP_POF_OFF_PPU_VPON_PCSM_POW_VDIV_HQ_VDDANA: 1;
+        uint32_t LOP_POF_OFF_PPU_VPON_PCSM_EN_DMYLOAD_VDDANA: 1;
+        uint32_t LOP_POF_OFF_PPU_VPON_PCSM_POW_VDDANA_DET: 1;
+        uint32_t LOP_POF_OFF_PPU_VPON_PCSM_ENCCM_OUT_VDDANA: 1;
+        uint32_t RESERVED: 1;
+        uint32_t LOP_POF_OSC128K_PCSM_POW_32KOSC: 1;
+    };
+} AON_LOP_POF_CLK_CTRL_OSC128K_OSC10_PCSM_1_TYPE;
+
+/*0x4000_0a30 AON_LOP_POF_CLK_CTRL_OSC128K_OSC10_PCSM_1*/
+#define AON_LOP_POF_CLK_CTRL_OSC128K_OSC10_PCSM_1_RESERVED_3_Pos                                                         0U
+#define AON_LOP_POF_CLK_CTRL_OSC128K_OSC10_PCSM_1_RESERVED_3_Msk                                                         (0xFFUL << AON_LOP_POF_CLK_CTRL_OSC128K_OSC10_PCSM_1_RESERVED_3_Pos)
+
+#define AON_LOP_POF_CLK_CTRL_OSC128K_OSC10_PCSM_1_RESERVED_2_Pos                                                         8U
+#define AON_LOP_POF_CLK_CTRL_OSC128K_OSC10_PCSM_1_RESERVED_2_Msk                                                         (0x1UL << AON_LOP_POF_CLK_CTRL_OSC128K_OSC10_PCSM_1_RESERVED_2_Pos)
+
+#define AON_LOP_POF_CLK_CTRL_OSC128K_OSC10_PCSM_1_RESERVED_1_Pos                                                         9U
+#define AON_LOP_POF_CLK_CTRL_OSC128K_OSC10_PCSM_1_RESERVED_1_Msk                                                         (0x1UL << AON_LOP_POF_CLK_CTRL_OSC128K_OSC10_PCSM_1_RESERVED_1_Pos)
+
+#define AON_LOP_POF_CLK_CTRL_OSC128K_OSC10_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_EN_CMP_LQ_VDDANA_Pos                         10U
+#define AON_LOP_POF_CLK_CTRL_OSC128K_OSC10_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_EN_CMP_LQ_VDDANA_Msk                         (0x1UL << AON_LOP_POF_CLK_CTRL_OSC128K_OSC10_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_EN_CMP_LQ_VDDANA_Pos)
+
+#define AON_LOP_POF_CLK_CTRL_OSC128K_OSC10_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_EN_CMP_HQ_VDDANA_Pos                         11U
+#define AON_LOP_POF_CLK_CTRL_OSC128K_OSC10_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_EN_CMP_HQ_VDDANA_Msk                         (0x1UL << AON_LOP_POF_CLK_CTRL_OSC128K_OSC10_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_EN_CMP_HQ_VDDANA_Pos)
+
+#define AON_LOP_POF_CLK_CTRL_OSC128K_OSC10_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_SEL_VREF_VDDANA_LQ_Pos                       12U
+#define AON_LOP_POF_CLK_CTRL_OSC128K_OSC10_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_SEL_VREF_VDDANA_LQ_Msk                       (0x1FUL << AON_LOP_POF_CLK_CTRL_OSC128K_OSC10_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_SEL_VREF_VDDANA_LQ_Pos)
+
+#define AON_LOP_POF_CLK_CTRL_OSC128K_OSC10_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_TUNE_VDDANA_Pos                              17U
+#define AON_LOP_POF_CLK_CTRL_OSC128K_OSC10_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_TUNE_VDDANA_Msk                              (0xFFUL << AON_LOP_POF_CLK_CTRL_OSC128K_OSC10_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_TUNE_VDDANA_Pos)
+
+#define AON_LOP_POF_CLK_CTRL_OSC128K_OSC10_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_POW_VDIV_LQ_VDDANA_Pos                       25U
+#define AON_LOP_POF_CLK_CTRL_OSC128K_OSC10_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_POW_VDIV_LQ_VDDANA_Msk                       (0x1UL << AON_LOP_POF_CLK_CTRL_OSC128K_OSC10_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_POW_VDIV_LQ_VDDANA_Pos)
+
+#define AON_LOP_POF_CLK_CTRL_OSC128K_OSC10_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_POW_VDIV_HQ_VDDANA_Pos                       26U
+#define AON_LOP_POF_CLK_CTRL_OSC128K_OSC10_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_POW_VDIV_HQ_VDDANA_Msk                       (0x1UL << AON_LOP_POF_CLK_CTRL_OSC128K_OSC10_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_POW_VDIV_HQ_VDDANA_Pos)
+
+#define AON_LOP_POF_CLK_CTRL_OSC128K_OSC10_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_EN_DMYLOAD_VDDANA_Pos                        27U
+#define AON_LOP_POF_CLK_CTRL_OSC128K_OSC10_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_EN_DMYLOAD_VDDANA_Msk                        (0x1UL << AON_LOP_POF_CLK_CTRL_OSC128K_OSC10_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_EN_DMYLOAD_VDDANA_Pos)
+
+#define AON_LOP_POF_CLK_CTRL_OSC128K_OSC10_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_POW_VDDANA_DET_Pos                           28U
+#define AON_LOP_POF_CLK_CTRL_OSC128K_OSC10_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_POW_VDDANA_DET_Msk                           (0x1UL << AON_LOP_POF_CLK_CTRL_OSC128K_OSC10_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_POW_VDDANA_DET_Pos)
+
+#define AON_LOP_POF_CLK_CTRL_OSC128K_OSC10_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_ENCCM_OUT_VDDANA_Pos                         29U
+#define AON_LOP_POF_CLK_CTRL_OSC128K_OSC10_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_ENCCM_OUT_VDDANA_Msk                         (0x1UL << AON_LOP_POF_CLK_CTRL_OSC128K_OSC10_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_ENCCM_OUT_VDDANA_Pos)
+
+#define AON_LOP_POF_CLK_CTRL_OSC128K_OSC10_PCSM_1_RESERVED_Pos                                                           30U
+#define AON_LOP_POF_CLK_CTRL_OSC128K_OSC10_PCSM_1_RESERVED_Msk                                                           (0x1UL << AON_LOP_POF_CLK_CTRL_OSC128K_OSC10_PCSM_1_RESERVED_Pos)
+
+#define AON_LOP_POF_CLK_CTRL_OSC128K_OSC10_PCSM_1_LOP_POF_OSC128K_PCSM_POW_32KOSC_Pos                                    31U
+#define AON_LOP_POF_CLK_CTRL_OSC128K_OSC10_PCSM_1_LOP_POF_OSC128K_PCSM_POW_32KOSC_Msk                                    (0x1UL << AON_LOP_POF_CLK_CTRL_OSC128K_OSC10_PCSM_1_LOP_POF_OSC128K_PCSM_POW_32KOSC_Pos)
+
+/* 0xA34    0x4000_0a34
+    7:0     R/W     RESERVED                                                    8'h0
+    11:8    R/W     LOP_POF_OSC10_PON_PCSM_INACTIVE_DELAY                       4'b0000
+    15:12   R/W     LOP_POF_OSC10_PCSM_VDDANA_2_DELAY                           4'b0000
+    19:16   R/W     LOP_POF_OSC10_PCSM_VDDANA_3_DELAY                           4'b0000
+    23:20   R/W     LOP_POF_OSC10_PCSM_VDDANA_4_DELAY                           4'b0000
+    27:24   R/W     LOP_POF_OSC10_PCSM_PWR_DELAY                                4'b0000
+    31:28   R/W     LOP_POF_OSC10_PCSM_INACTIVE_DELAY                           4'b0000
+ */
+typedef union _AON_LOP_POF_CLK_CTRL_OSC128K_OSC10_PCSM_2_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED: 8;
+        uint32_t LOP_POF_OSC10_PON_PCSM_INACTIVE_DELAY: 4;
+        uint32_t LOP_POF_OSC10_PCSM_VDDANA_2_DELAY: 4;
+        uint32_t LOP_POF_OSC10_PCSM_VDDANA_3_DELAY: 4;
+        uint32_t LOP_POF_OSC10_PCSM_VDDANA_4_DELAY: 4;
+        uint32_t LOP_POF_OSC10_PCSM_PWR_DELAY: 4;
+        uint32_t LOP_POF_OSC10_PCSM_INACTIVE_DELAY: 4;
+    };
+} AON_LOP_POF_CLK_CTRL_OSC128K_OSC10_PCSM_2_TYPE;
+
+/*0x4000_0a34 AON_LOP_POF_CLK_CTRL_OSC128K_OSC10_PCSM_2*/
+#define AON_LOP_POF_CLK_CTRL_OSC128K_OSC10_PCSM_2_RESERVED_Pos                                                           0U
+#define AON_LOP_POF_CLK_CTRL_OSC128K_OSC10_PCSM_2_RESERVED_Msk                                                           (0xFFUL << AON_LOP_POF_CLK_CTRL_OSC128K_OSC10_PCSM_2_RESERVED_Pos)
+
+#define AON_LOP_POF_CLK_CTRL_OSC128K_OSC10_PCSM_2_LOP_POF_OSC10_PON_PCSM_INACTIVE_DELAY_Pos                              8U
+#define AON_LOP_POF_CLK_CTRL_OSC128K_OSC10_PCSM_2_LOP_POF_OSC10_PON_PCSM_INACTIVE_DELAY_Msk                              (0xFUL << AON_LOP_POF_CLK_CTRL_OSC128K_OSC10_PCSM_2_LOP_POF_OSC10_PON_PCSM_INACTIVE_DELAY_Pos)
+
+#define AON_LOP_POF_CLK_CTRL_OSC128K_OSC10_PCSM_2_LOP_POF_OSC10_PCSM_VDDANA_2_DELAY_Pos                                  12U
+#define AON_LOP_POF_CLK_CTRL_OSC128K_OSC10_PCSM_2_LOP_POF_OSC10_PCSM_VDDANA_2_DELAY_Msk                                  (0xFUL << AON_LOP_POF_CLK_CTRL_OSC128K_OSC10_PCSM_2_LOP_POF_OSC10_PCSM_VDDANA_2_DELAY_Pos)
+
+#define AON_LOP_POF_CLK_CTRL_OSC128K_OSC10_PCSM_2_LOP_POF_OSC10_PCSM_VDDANA_3_DELAY_Pos                                  16U
+#define AON_LOP_POF_CLK_CTRL_OSC128K_OSC10_PCSM_2_LOP_POF_OSC10_PCSM_VDDANA_3_DELAY_Msk                                  (0xFUL << AON_LOP_POF_CLK_CTRL_OSC128K_OSC10_PCSM_2_LOP_POF_OSC10_PCSM_VDDANA_3_DELAY_Pos)
+
+#define AON_LOP_POF_CLK_CTRL_OSC128K_OSC10_PCSM_2_LOP_POF_OSC10_PCSM_VDDANA_4_DELAY_Pos                                  20U
+#define AON_LOP_POF_CLK_CTRL_OSC128K_OSC10_PCSM_2_LOP_POF_OSC10_PCSM_VDDANA_4_DELAY_Msk                                  (0xFUL << AON_LOP_POF_CLK_CTRL_OSC128K_OSC10_PCSM_2_LOP_POF_OSC10_PCSM_VDDANA_4_DELAY_Pos)
+
+#define AON_LOP_POF_CLK_CTRL_OSC128K_OSC10_PCSM_2_LOP_POF_OSC10_PCSM_PWR_DELAY_Pos                                       24U
+#define AON_LOP_POF_CLK_CTRL_OSC128K_OSC10_PCSM_2_LOP_POF_OSC10_PCSM_PWR_DELAY_Msk                                       (0xFUL << AON_LOP_POF_CLK_CTRL_OSC128K_OSC10_PCSM_2_LOP_POF_OSC10_PCSM_PWR_DELAY_Pos)
+
+#define AON_LOP_POF_CLK_CTRL_OSC128K_OSC10_PCSM_2_LOP_POF_OSC10_PCSM_INACTIVE_DELAY_Pos                                  28U
+#define AON_LOP_POF_CLK_CTRL_OSC128K_OSC10_PCSM_2_LOP_POF_OSC10_PCSM_INACTIVE_DELAY_Msk                                  (0xFUL << AON_LOP_POF_CLK_CTRL_OSC128K_OSC10_PCSM_2_LOP_POF_OSC10_PCSM_INACTIVE_DELAY_Pos)
+
+/* 0xA38    0x4000_0a38
+    0       R/W     LOP_POF_OFF_PPU_VPON_PCSM_VDDIO_EN_DISCHG                   1'b0
+    1       R/W     LOP_POF_OFF_PPU_VPON_PCSM_VDDIO_EN_PC2                      1'b1
+    2       R/W     LOP_POF_OFF_PPU_VPON_PCSM_VDDIO_EN_PC1                      1'b1
+    3       R/W     LOP_POF_OFF_PPU_VPON_PCSM_EN_SYNC                           1'b0
+    4       R/W     LOP_POF_OFF_PPU_VPON_PCSM_POW_VDIV_LQ_VDDCORE               1'b0
+    5       R/W     LOP_POF_OFF_PPU_VPON_PCSM_POW_VDIV_LQ_HV18                  1'b0
+    6       R/W     LOP_POF_OFF_PPU_VPON_PCSM_POW_VDIV_HQ_VDDCORE               1'b0
+    7       R/W     LOP_POF_OFF_PPU_VPON_PCSM_POW_VDIV_HQ_VDDPA                 1'b0
+    8       R/W     LOP_POF_OFF_PPU_VPON_PCSM_POW_VDIV_HQ_HV18                  1'b0
+    9       R/W     LOP_POF_OFF_PPU_VPON_PCSM_POW_VDIV_HQ_HV25                  1'b0
+    10      R/W     LOP_POF_OFF_PPU_VPON_PCSM_REG_ENHQ_REFCMP                   1'b0
+    11      R/W     LOP_POF_OFF_PPU_VPON_PCSM_BYP_OPOR_LD                       1'b0
+    12      R/W     LOP_POF_OFF_PPU_VPON_PCSM_REG_ENLPM                         1'b1
+    13      R/W     LOP_POF_OFF_PPU_VPON_PCSM_REG_ENPCCM                        1'b0
+    14      R/W     LOP_POF_OFF_PPU_VPON_PCSM_ENCCM_OUT_VDDCORE                 1'b0
+    15      R/W     LOP_POF_OFF_PPU_VPON_PCSM_ENCCM_OUT_VDDPA                   1'b0
+    16      R/W     LOP_POF_OFF_PPU_VPON_PCSM_ENCCM_OUT_HV18                    1'b0
+    17      R/W     LOP_POF_OFF_PPU_VPON_PCSM_ENCCM_OUT_HV25                    1'b0
+    19:18   R/W     LOP_POF_OFF_PPU_VPON_PCSM_ZCDLY_SET                         2'b10
+    20      R/W     LOP_POF_OFF_PPU_VPON_PCSM_ENDLY_FOR_K                       1'b1
+    21      R/W     LOP_POF_OFF_PPU_VPON_PCSM_BUCK_BOOST_VDDPA_POS_RSTB         1'b0
+    22      R/W     LOP_POF_OFF_PPU_VPON_PCSM_BUCK_BOOST_HV18_POS_RSTB          1'b0
+    23      R/W     LOP_POF_OFF_PPU_VPON_PCSM_EN_DMYLOAD_VDDCORE                1'b0
+    24      R/W     LOP_POF_OFF_PPU_VPON_PCSM_EN_DMYLOAD_VDDPA                  1'b0
+    25      R/W     LOP_POF_OFF_PPU_VPON_PCSM_EN_DMYLOAD_HV18                   1'b0
+    26      R/W     LOP_POF_OFF_PPU_VPON_PCSM_EN_DMYLOAD_HV25                   1'b0
+    27      R/W     LOP_POF_OFF_PPU_VPON_PCSM_POW_VDDPA_DET                     1'b0
+    28      R/W     LOP_POF_OFF_PPU_VPON_PCSM_POW_HV18_DET                      1'b0
+    29      R/W     LOP_POF_OFF_PPU_VPON_PCSM_POW_VDDCORE_DET                   1'b0
+    30      R/W     LOP_POF_OFF_PPU_VPON_PCSM_POW_VANA_DET                      1'b0
+    31      R/W     LOP_POF_OFF_PPU_VPON_PCSM_EN_BIAS_10UA                      1'b0
+ */
+typedef union _AON_LOP_POF_OFF_PPU_VPON_PCSM_1_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t LOP_POF_OFF_PPU_VPON_PCSM_VDDIO_EN_DISCHG: 1;
+        uint32_t LOP_POF_OFF_PPU_VPON_PCSM_VDDIO_EN_PC2: 1;
+        uint32_t LOP_POF_OFF_PPU_VPON_PCSM_VDDIO_EN_PC1: 1;
+        uint32_t LOP_POF_OFF_PPU_VPON_PCSM_EN_SYNC: 1;
+        uint32_t LOP_POF_OFF_PPU_VPON_PCSM_POW_VDIV_LQ_VDDCORE: 1;
+        uint32_t LOP_POF_OFF_PPU_VPON_PCSM_POW_VDIV_LQ_HV18: 1;
+        uint32_t LOP_POF_OFF_PPU_VPON_PCSM_POW_VDIV_HQ_VDDCORE: 1;
+        uint32_t LOP_POF_OFF_PPU_VPON_PCSM_POW_VDIV_HQ_VDDPA: 1;
+        uint32_t LOP_POF_OFF_PPU_VPON_PCSM_POW_VDIV_HQ_HV18: 1;
+        uint32_t LOP_POF_OFF_PPU_VPON_PCSM_POW_VDIV_HQ_HV25: 1;
+        uint32_t LOP_POF_OFF_PPU_VPON_PCSM_REG_ENHQ_REFCMP: 1;
+        uint32_t LOP_POF_OFF_PPU_VPON_PCSM_BYP_OPOR_LD: 1;
+        uint32_t LOP_POF_OFF_PPU_VPON_PCSM_REG_ENLPM: 1;
+        uint32_t LOP_POF_OFF_PPU_VPON_PCSM_REG_ENPCCM: 1;
+        uint32_t LOP_POF_OFF_PPU_VPON_PCSM_ENCCM_OUT_VDDCORE: 1;
+        uint32_t LOP_POF_OFF_PPU_VPON_PCSM_ENCCM_OUT_VDDPA: 1;
+        uint32_t LOP_POF_OFF_PPU_VPON_PCSM_ENCCM_OUT_HV18: 1;
+        uint32_t LOP_POF_OFF_PPU_VPON_PCSM_ENCCM_OUT_HV25: 1;
+        uint32_t LOP_POF_OFF_PPU_VPON_PCSM_ZCDLY_SET: 2;
+        uint32_t LOP_POF_OFF_PPU_VPON_PCSM_ENDLY_FOR_K: 1;
+        uint32_t LOP_POF_OFF_PPU_VPON_PCSM_BUCK_BOOST_VDDPA_POS_RSTB: 1;
+        uint32_t LOP_POF_OFF_PPU_VPON_PCSM_BUCK_BOOST_HV18_POS_RSTB: 1;
+        uint32_t LOP_POF_OFF_PPU_VPON_PCSM_EN_DMYLOAD_VDDCORE: 1;
+        uint32_t LOP_POF_OFF_PPU_VPON_PCSM_EN_DMYLOAD_VDDPA: 1;
+        uint32_t LOP_POF_OFF_PPU_VPON_PCSM_EN_DMYLOAD_HV18: 1;
+        uint32_t LOP_POF_OFF_PPU_VPON_PCSM_EN_DMYLOAD_HV25: 1;
+        uint32_t LOP_POF_OFF_PPU_VPON_PCSM_POW_VDDPA_DET: 1;
+        uint32_t LOP_POF_OFF_PPU_VPON_PCSM_POW_HV18_DET: 1;
+        uint32_t LOP_POF_OFF_PPU_VPON_PCSM_POW_VDDCORE_DET: 1;
+        uint32_t LOP_POF_OFF_PPU_VPON_PCSM_POW_VANA_DET: 1;
+        uint32_t LOP_POF_OFF_PPU_VPON_PCSM_EN_BIAS_10UA: 1;
+    };
+} AON_LOP_POF_OFF_PPU_VPON_PCSM_1_TYPE;
+
+/*0x4000_0a38 AON_LOP_POF_OFF_PPU_VPON_PCSM_1*/
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_VDDIO_EN_DISCHG_Pos                                    0U
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_VDDIO_EN_DISCHG_Msk                                    (0x1UL << AON_LOP_POF_OFF_PPU_VPON_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_VDDIO_EN_DISCHG_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_VDDIO_EN_PC2_Pos                                       1U
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_VDDIO_EN_PC2_Msk                                       (0x1UL << AON_LOP_POF_OFF_PPU_VPON_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_VDDIO_EN_PC2_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_VDDIO_EN_PC1_Pos                                       2U
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_VDDIO_EN_PC1_Msk                                       (0x1UL << AON_LOP_POF_OFF_PPU_VPON_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_VDDIO_EN_PC1_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_EN_SYNC_Pos                                            3U
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_EN_SYNC_Msk                                            (0x1UL << AON_LOP_POF_OFF_PPU_VPON_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_EN_SYNC_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_POW_VDIV_LQ_VDDCORE_Pos                                4U
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_POW_VDIV_LQ_VDDCORE_Msk                                (0x1UL << AON_LOP_POF_OFF_PPU_VPON_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_POW_VDIV_LQ_VDDCORE_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_POW_VDIV_LQ_HV18_Pos                                   5U
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_POW_VDIV_LQ_HV18_Msk                                   (0x1UL << AON_LOP_POF_OFF_PPU_VPON_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_POW_VDIV_LQ_HV18_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_POW_VDIV_HQ_VDDCORE_Pos                                6U
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_POW_VDIV_HQ_VDDCORE_Msk                                (0x1UL << AON_LOP_POF_OFF_PPU_VPON_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_POW_VDIV_HQ_VDDCORE_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_POW_VDIV_HQ_VDDPA_Pos                                  7U
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_POW_VDIV_HQ_VDDPA_Msk                                  (0x1UL << AON_LOP_POF_OFF_PPU_VPON_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_POW_VDIV_HQ_VDDPA_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_POW_VDIV_HQ_HV18_Pos                                   8U
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_POW_VDIV_HQ_HV18_Msk                                   (0x1UL << AON_LOP_POF_OFF_PPU_VPON_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_POW_VDIV_HQ_HV18_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_POW_VDIV_HQ_HV25_Pos                                   9U
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_POW_VDIV_HQ_HV25_Msk                                   (0x1UL << AON_LOP_POF_OFF_PPU_VPON_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_POW_VDIV_HQ_HV25_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_REG_ENHQ_REFCMP_Pos                                    10U
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_REG_ENHQ_REFCMP_Msk                                    (0x1UL << AON_LOP_POF_OFF_PPU_VPON_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_REG_ENHQ_REFCMP_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_BYP_OPOR_LD_Pos                                        11U
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_BYP_OPOR_LD_Msk                                        (0x1UL << AON_LOP_POF_OFF_PPU_VPON_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_BYP_OPOR_LD_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_REG_ENLPM_Pos                                          12U
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_REG_ENLPM_Msk                                          (0x1UL << AON_LOP_POF_OFF_PPU_VPON_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_REG_ENLPM_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_REG_ENPCCM_Pos                                         13U
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_REG_ENPCCM_Msk                                         (0x1UL << AON_LOP_POF_OFF_PPU_VPON_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_REG_ENPCCM_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_ENCCM_OUT_VDDCORE_Pos                                  14U
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_ENCCM_OUT_VDDCORE_Msk                                  (0x1UL << AON_LOP_POF_OFF_PPU_VPON_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_ENCCM_OUT_VDDCORE_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_ENCCM_OUT_VDDPA_Pos                                    15U
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_ENCCM_OUT_VDDPA_Msk                                    (0x1UL << AON_LOP_POF_OFF_PPU_VPON_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_ENCCM_OUT_VDDPA_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_ENCCM_OUT_HV18_Pos                                     16U
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_ENCCM_OUT_HV18_Msk                                     (0x1UL << AON_LOP_POF_OFF_PPU_VPON_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_ENCCM_OUT_HV18_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_ENCCM_OUT_HV25_Pos                                     17U
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_ENCCM_OUT_HV25_Msk                                     (0x1UL << AON_LOP_POF_OFF_PPU_VPON_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_ENCCM_OUT_HV25_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_ZCDLY_SET_Pos                                          18U
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_ZCDLY_SET_Msk                                          (0x3UL << AON_LOP_POF_OFF_PPU_VPON_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_ZCDLY_SET_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_ENDLY_FOR_K_Pos                                        20U
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_ENDLY_FOR_K_Msk                                        (0x1UL << AON_LOP_POF_OFF_PPU_VPON_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_ENDLY_FOR_K_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_BUCK_BOOST_VDDPA_POS_RSTB_Pos                          21U
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_BUCK_BOOST_VDDPA_POS_RSTB_Msk                          (0x1UL << AON_LOP_POF_OFF_PPU_VPON_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_BUCK_BOOST_VDDPA_POS_RSTB_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_BUCK_BOOST_HV18_POS_RSTB_Pos                           22U
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_BUCK_BOOST_HV18_POS_RSTB_Msk                           (0x1UL << AON_LOP_POF_OFF_PPU_VPON_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_BUCK_BOOST_HV18_POS_RSTB_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_EN_DMYLOAD_VDDCORE_Pos                                 23U
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_EN_DMYLOAD_VDDCORE_Msk                                 (0x1UL << AON_LOP_POF_OFF_PPU_VPON_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_EN_DMYLOAD_VDDCORE_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_EN_DMYLOAD_VDDPA_Pos                                   24U
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_EN_DMYLOAD_VDDPA_Msk                                   (0x1UL << AON_LOP_POF_OFF_PPU_VPON_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_EN_DMYLOAD_VDDPA_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_EN_DMYLOAD_HV18_Pos                                    25U
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_EN_DMYLOAD_HV18_Msk                                    (0x1UL << AON_LOP_POF_OFF_PPU_VPON_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_EN_DMYLOAD_HV18_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_EN_DMYLOAD_HV25_Pos                                    26U
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_EN_DMYLOAD_HV25_Msk                                    (0x1UL << AON_LOP_POF_OFF_PPU_VPON_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_EN_DMYLOAD_HV25_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_POW_VDDPA_DET_Pos                                      27U
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_POW_VDDPA_DET_Msk                                      (0x1UL << AON_LOP_POF_OFF_PPU_VPON_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_POW_VDDPA_DET_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_POW_HV18_DET_Pos                                       28U
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_POW_HV18_DET_Msk                                       (0x1UL << AON_LOP_POF_OFF_PPU_VPON_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_POW_HV18_DET_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_POW_VDDCORE_DET_Pos                                    29U
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_POW_VDDCORE_DET_Msk                                    (0x1UL << AON_LOP_POF_OFF_PPU_VPON_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_POW_VDDCORE_DET_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_POW_VANA_DET_Pos                                       30U
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_POW_VANA_DET_Msk                                       (0x1UL << AON_LOP_POF_OFF_PPU_VPON_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_POW_VANA_DET_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_EN_BIAS_10UA_Pos                                       31U
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_EN_BIAS_10UA_Msk                                       (0x1UL << AON_LOP_POF_OFF_PPU_VPON_PCSM_1_LOP_POF_OFF_PPU_VPON_PCSM_EN_BIAS_10UA_Pos)
+
+/* 0xA3C    0x4000_0a3c
+    0       R/W     LOP_POF_OFF_PPU_VPON_PCSM_EN_MCM_FLASH_PC2                  1'b0
+    1       R/W     LOP_POF_OFF_PPU_VPON_PCSM_EN_MCM_FLASH_PC1                  1'b0
+    2       R/W     LOP_POF_OFF_PPU_VPON_PCSM_EN_DISCHG_MCM_FLASH               1'b1
+    3       R/W     LOP_POF_OFF_PPU_VPON_PCSM_EN_BIAS_1UA                       1'b0
+    4       R/W     LOP_POF_OFF_PPU_VPON_PCSM_IO_RSTB33_EN                      1'b1
+    5       R/W     LOP_POF_OFF_PPU_VPON_PCSM_IO_SHDN33_EN                      1'b1
+    13:6    R/W     LOP_POF_OFF_PPU_VPON_PCSM_TUNE_VDDPA                        8'b00100010
+    19:14   R/W     LOP_POF_OFF_PPU_VPON_PCSM_TUNE_HV18                         6'b100000
+    24:20   R/W     LOP_POF_OFF_PPU_VPON_PCSM_SEL_VREF_HV25_HQ                  5'b01111
+    25      R/W     LOP_POF_OFF_PPU_VPON_PCSM_EN_CMP_LQ_VDDCORE                 1'b0
+    26      R/W     LOP_POF_OFF_PPU_VPON_PCSM_EN_CMP_LQ_HV18                    1'b0
+    27      R/W     LOP_POF_OFF_PPU_VPON_PCSM_EN_CMP_LQ_HV25                    1'b1
+    28      R/W     LOP_POF_OFF_PPU_VPON_PCSM_EN_CMP_HQ_VDDCORE                 1'b0
+    29      R/W     LOP_POF_OFF_PPU_VPON_PCSM_EN_CMP_HQ_VDDPA                   1'b0
+    30      R/W     LOP_POF_OFF_PPU_VPON_PCSM_EN_CMP_HQ_HV18                    1'b0
+    31      R/W     LOP_POF_OFF_PPU_VPON_PCSM_EN_CMP_HQ_HV25                    1'b0
+ */
+typedef union _AON_LOP_POF_OFF_PPU_VPON_PCSM_2_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t LOP_POF_OFF_PPU_VPON_PCSM_EN_MCM_FLASH_PC2: 1;
+        uint32_t LOP_POF_OFF_PPU_VPON_PCSM_EN_MCM_FLASH_PC1: 1;
+        uint32_t LOP_POF_OFF_PPU_VPON_PCSM_EN_DISCHG_MCM_FLASH: 1;
+        uint32_t LOP_POF_OFF_PPU_VPON_PCSM_EN_BIAS_1UA: 1;
+        uint32_t LOP_POF_OFF_PPU_VPON_PCSM_IO_RSTB33_EN: 1;
+        uint32_t LOP_POF_OFF_PPU_VPON_PCSM_IO_SHDN33_EN: 1;
+        uint32_t LOP_POF_OFF_PPU_VPON_PCSM_TUNE_VDDPA: 8;
+        uint32_t LOP_POF_OFF_PPU_VPON_PCSM_TUNE_HV18: 6;
+        uint32_t LOP_POF_OFF_PPU_VPON_PCSM_SEL_VREF_HV25_HQ: 5;
+        uint32_t LOP_POF_OFF_PPU_VPON_PCSM_EN_CMP_LQ_VDDCORE: 1;
+        uint32_t LOP_POF_OFF_PPU_VPON_PCSM_EN_CMP_LQ_HV18: 1;
+        uint32_t LOP_POF_OFF_PPU_VPON_PCSM_EN_CMP_LQ_HV25: 1;
+        uint32_t LOP_POF_OFF_PPU_VPON_PCSM_EN_CMP_HQ_VDDCORE: 1;
+        uint32_t LOP_POF_OFF_PPU_VPON_PCSM_EN_CMP_HQ_VDDPA: 1;
+        uint32_t LOP_POF_OFF_PPU_VPON_PCSM_EN_CMP_HQ_HV18: 1;
+        uint32_t LOP_POF_OFF_PPU_VPON_PCSM_EN_CMP_HQ_HV25: 1;
+    };
+} AON_LOP_POF_OFF_PPU_VPON_PCSM_2_TYPE;
+
+/*0x4000_0a3c AON_LOP_POF_OFF_PPU_VPON_PCSM_2*/
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_2_LOP_POF_OFF_PPU_VPON_PCSM_EN_MCM_FLASH_PC2_Pos                                   0U
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_2_LOP_POF_OFF_PPU_VPON_PCSM_EN_MCM_FLASH_PC2_Msk                                   (0x1UL << AON_LOP_POF_OFF_PPU_VPON_PCSM_2_LOP_POF_OFF_PPU_VPON_PCSM_EN_MCM_FLASH_PC2_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_2_LOP_POF_OFF_PPU_VPON_PCSM_EN_MCM_FLASH_PC1_Pos                                   1U
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_2_LOP_POF_OFF_PPU_VPON_PCSM_EN_MCM_FLASH_PC1_Msk                                   (0x1UL << AON_LOP_POF_OFF_PPU_VPON_PCSM_2_LOP_POF_OFF_PPU_VPON_PCSM_EN_MCM_FLASH_PC1_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_2_LOP_POF_OFF_PPU_VPON_PCSM_EN_DISCHG_MCM_FLASH_Pos                                2U
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_2_LOP_POF_OFF_PPU_VPON_PCSM_EN_DISCHG_MCM_FLASH_Msk                                (0x1UL << AON_LOP_POF_OFF_PPU_VPON_PCSM_2_LOP_POF_OFF_PPU_VPON_PCSM_EN_DISCHG_MCM_FLASH_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_2_LOP_POF_OFF_PPU_VPON_PCSM_EN_BIAS_1UA_Pos                                        3U
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_2_LOP_POF_OFF_PPU_VPON_PCSM_EN_BIAS_1UA_Msk                                        (0x1UL << AON_LOP_POF_OFF_PPU_VPON_PCSM_2_LOP_POF_OFF_PPU_VPON_PCSM_EN_BIAS_1UA_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_2_LOP_POF_OFF_PPU_VPON_PCSM_IO_RSTB33_EN_Pos                                       4U
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_2_LOP_POF_OFF_PPU_VPON_PCSM_IO_RSTB33_EN_Msk                                       (0x1UL << AON_LOP_POF_OFF_PPU_VPON_PCSM_2_LOP_POF_OFF_PPU_VPON_PCSM_IO_RSTB33_EN_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_2_LOP_POF_OFF_PPU_VPON_PCSM_IO_SHDN33_EN_Pos                                       5U
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_2_LOP_POF_OFF_PPU_VPON_PCSM_IO_SHDN33_EN_Msk                                       (0x1UL << AON_LOP_POF_OFF_PPU_VPON_PCSM_2_LOP_POF_OFF_PPU_VPON_PCSM_IO_SHDN33_EN_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_2_LOP_POF_OFF_PPU_VPON_PCSM_TUNE_VDDPA_Pos                                         6U
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_2_LOP_POF_OFF_PPU_VPON_PCSM_TUNE_VDDPA_Msk                                         (0xFFUL << AON_LOP_POF_OFF_PPU_VPON_PCSM_2_LOP_POF_OFF_PPU_VPON_PCSM_TUNE_VDDPA_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_2_LOP_POF_OFF_PPU_VPON_PCSM_TUNE_HV18_Pos                                          14U
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_2_LOP_POF_OFF_PPU_VPON_PCSM_TUNE_HV18_Msk                                          (0x3FUL << AON_LOP_POF_OFF_PPU_VPON_PCSM_2_LOP_POF_OFF_PPU_VPON_PCSM_TUNE_HV18_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_2_LOP_POF_OFF_PPU_VPON_PCSM_SEL_VREF_HV25_HQ_Pos                                   20U
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_2_LOP_POF_OFF_PPU_VPON_PCSM_SEL_VREF_HV25_HQ_Msk                                   (0x1FUL << AON_LOP_POF_OFF_PPU_VPON_PCSM_2_LOP_POF_OFF_PPU_VPON_PCSM_SEL_VREF_HV25_HQ_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_2_LOP_POF_OFF_PPU_VPON_PCSM_EN_CMP_LQ_VDDCORE_Pos                                  25U
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_2_LOP_POF_OFF_PPU_VPON_PCSM_EN_CMP_LQ_VDDCORE_Msk                                  (0x1UL << AON_LOP_POF_OFF_PPU_VPON_PCSM_2_LOP_POF_OFF_PPU_VPON_PCSM_EN_CMP_LQ_VDDCORE_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_2_LOP_POF_OFF_PPU_VPON_PCSM_EN_CMP_LQ_HV18_Pos                                     26U
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_2_LOP_POF_OFF_PPU_VPON_PCSM_EN_CMP_LQ_HV18_Msk                                     (0x1UL << AON_LOP_POF_OFF_PPU_VPON_PCSM_2_LOP_POF_OFF_PPU_VPON_PCSM_EN_CMP_LQ_HV18_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_2_LOP_POF_OFF_PPU_VPON_PCSM_EN_CMP_LQ_HV25_Pos                                     27U
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_2_LOP_POF_OFF_PPU_VPON_PCSM_EN_CMP_LQ_HV25_Msk                                     (0x1UL << AON_LOP_POF_OFF_PPU_VPON_PCSM_2_LOP_POF_OFF_PPU_VPON_PCSM_EN_CMP_LQ_HV25_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_2_LOP_POF_OFF_PPU_VPON_PCSM_EN_CMP_HQ_VDDCORE_Pos                                  28U
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_2_LOP_POF_OFF_PPU_VPON_PCSM_EN_CMP_HQ_VDDCORE_Msk                                  (0x1UL << AON_LOP_POF_OFF_PPU_VPON_PCSM_2_LOP_POF_OFF_PPU_VPON_PCSM_EN_CMP_HQ_VDDCORE_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_2_LOP_POF_OFF_PPU_VPON_PCSM_EN_CMP_HQ_VDDPA_Pos                                    29U
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_2_LOP_POF_OFF_PPU_VPON_PCSM_EN_CMP_HQ_VDDPA_Msk                                    (0x1UL << AON_LOP_POF_OFF_PPU_VPON_PCSM_2_LOP_POF_OFF_PPU_VPON_PCSM_EN_CMP_HQ_VDDPA_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_2_LOP_POF_OFF_PPU_VPON_PCSM_EN_CMP_HQ_HV18_Pos                                     30U
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_2_LOP_POF_OFF_PPU_VPON_PCSM_EN_CMP_HQ_HV18_Msk                                     (0x1UL << AON_LOP_POF_OFF_PPU_VPON_PCSM_2_LOP_POF_OFF_PPU_VPON_PCSM_EN_CMP_HQ_HV18_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_2_LOP_POF_OFF_PPU_VPON_PCSM_EN_CMP_HQ_HV25_Pos                                     31U
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_2_LOP_POF_OFF_PPU_VPON_PCSM_EN_CMP_HQ_HV25_Msk                                     (0x1UL << AON_LOP_POF_OFF_PPU_VPON_PCSM_2_LOP_POF_OFF_PPU_VPON_PCSM_EN_CMP_HQ_HV25_Pos)
+
+/* 0xA40    0x4000_0a40
+    1:0     R/W     RESERVED                                                    2'h0
+    2       R/W     LOP_POF_OFF_PPU_VPON_PCSM_LDO_PA_POS_RSTB                   1'b0
+    3       R/W     LOP_POF_OFF_PPU_VPON_PCSM_LDO_ANA_POS_RSTB                  1'b0
+    4       R/W     LOP_POF_OFF_PPU_VPON_PCSM_LDO_POW_BIAS_LDOPA                1'b0
+    5       R/W     LOP_POF_OFF_PPU_VPON_PCSM_LDO_POW_BIAS_LDOANA               1'b0
+    6       R/W     LOP_POF_OFF_PPU_VPON_PCSM_BUCK_BOOST_VDDPA_POS_EN_POS       1'b0
+    7       R/W     LOP_POF_OFF_PPU_VPON_PCSM_BUCK_BOOST_HV18_POS_EN_POS        1'b0
+    12:8    R/W     LOP_POF_OFF_PPU_VPON_PCSM_SEL_VREF_VDDCORE_LQ               5'b01110
+    18:13   R/W     LOP_POF_OFF_PPU_VPON_PCSM_TUNE_LPM_HV18                     6'b100000
+    23:19   R/W     LOP_POF_OFF_PPU_VPON_PCSM_SEL_VREF_HV25_LQ                  5'b01111
+    31:24   R/W     LOP_POF_OFF_PPU_VPON_PCSM_TUNE_VDDCORE                      8'b01100010
+ */
+typedef union _AON_LOP_POF_OFF_PPU_VPON_PCSM_3_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED: 2;
+        uint32_t LOP_POF_OFF_PPU_VPON_PCSM_LDO_PA_POS_RSTB: 1;
+        uint32_t LOP_POF_OFF_PPU_VPON_PCSM_LDO_ANA_POS_RSTB: 1;
+        uint32_t LOP_POF_OFF_PPU_VPON_PCSM_LDO_POW_BIAS_LDOPA: 1;
+        uint32_t LOP_POF_OFF_PPU_VPON_PCSM_LDO_POW_BIAS_LDOANA: 1;
+        uint32_t LOP_POF_OFF_PPU_VPON_PCSM_BUCK_BOOST_VDDPA_POS_EN_POS: 1;
+        uint32_t LOP_POF_OFF_PPU_VPON_PCSM_BUCK_BOOST_HV18_POS_EN_POS: 1;
+        uint32_t LOP_POF_OFF_PPU_VPON_PCSM_SEL_VREF_VDDCORE_LQ: 5;
+        uint32_t LOP_POF_OFF_PPU_VPON_PCSM_TUNE_LPM_HV18: 6;
+        uint32_t LOP_POF_OFF_PPU_VPON_PCSM_SEL_VREF_HV25_LQ: 5;
+        uint32_t LOP_POF_OFF_PPU_VPON_PCSM_TUNE_VDDCORE: 8;
+    };
+} AON_LOP_POF_OFF_PPU_VPON_PCSM_3_TYPE;
+
+/*0x4000_0a40 AON_LOP_POF_OFF_PPU_VPON_PCSM_3*/
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_3_RESERVED_Pos                                                                     0U
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_3_RESERVED_Msk                                                                     (0x3UL << AON_LOP_POF_OFF_PPU_VPON_PCSM_3_RESERVED_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_3_LOP_POF_OFF_PPU_VPON_PCSM_LDO_PA_POS_RSTB_Pos                                    2U
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_3_LOP_POF_OFF_PPU_VPON_PCSM_LDO_PA_POS_RSTB_Msk                                    (0x1UL << AON_LOP_POF_OFF_PPU_VPON_PCSM_3_LOP_POF_OFF_PPU_VPON_PCSM_LDO_PA_POS_RSTB_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_3_LOP_POF_OFF_PPU_VPON_PCSM_LDO_ANA_POS_RSTB_Pos                                   3U
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_3_LOP_POF_OFF_PPU_VPON_PCSM_LDO_ANA_POS_RSTB_Msk                                   (0x1UL << AON_LOP_POF_OFF_PPU_VPON_PCSM_3_LOP_POF_OFF_PPU_VPON_PCSM_LDO_ANA_POS_RSTB_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_3_LOP_POF_OFF_PPU_VPON_PCSM_LDO_POW_BIAS_LDOPA_Pos                                 4U
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_3_LOP_POF_OFF_PPU_VPON_PCSM_LDO_POW_BIAS_LDOPA_Msk                                 (0x1UL << AON_LOP_POF_OFF_PPU_VPON_PCSM_3_LOP_POF_OFF_PPU_VPON_PCSM_LDO_POW_BIAS_LDOPA_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_3_LOP_POF_OFF_PPU_VPON_PCSM_LDO_POW_BIAS_LDOANA_Pos                                5U
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_3_LOP_POF_OFF_PPU_VPON_PCSM_LDO_POW_BIAS_LDOANA_Msk                                (0x1UL << AON_LOP_POF_OFF_PPU_VPON_PCSM_3_LOP_POF_OFF_PPU_VPON_PCSM_LDO_POW_BIAS_LDOANA_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_3_LOP_POF_OFF_PPU_VPON_PCSM_BUCK_BOOST_VDDPA_POS_EN_POS_Pos                        6U
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_3_LOP_POF_OFF_PPU_VPON_PCSM_BUCK_BOOST_VDDPA_POS_EN_POS_Msk                        (0x1UL << AON_LOP_POF_OFF_PPU_VPON_PCSM_3_LOP_POF_OFF_PPU_VPON_PCSM_BUCK_BOOST_VDDPA_POS_EN_POS_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_3_LOP_POF_OFF_PPU_VPON_PCSM_BUCK_BOOST_HV18_POS_EN_POS_Pos                         7U
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_3_LOP_POF_OFF_PPU_VPON_PCSM_BUCK_BOOST_HV18_POS_EN_POS_Msk                         (0x1UL << AON_LOP_POF_OFF_PPU_VPON_PCSM_3_LOP_POF_OFF_PPU_VPON_PCSM_BUCK_BOOST_HV18_POS_EN_POS_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_3_LOP_POF_OFF_PPU_VPON_PCSM_SEL_VREF_VDDCORE_LQ_Pos                                8U
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_3_LOP_POF_OFF_PPU_VPON_PCSM_SEL_VREF_VDDCORE_LQ_Msk                                (0x1FUL << AON_LOP_POF_OFF_PPU_VPON_PCSM_3_LOP_POF_OFF_PPU_VPON_PCSM_SEL_VREF_VDDCORE_LQ_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_3_LOP_POF_OFF_PPU_VPON_PCSM_TUNE_LPM_HV18_Pos                                      13U
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_3_LOP_POF_OFF_PPU_VPON_PCSM_TUNE_LPM_HV18_Msk                                      (0x3FUL << AON_LOP_POF_OFF_PPU_VPON_PCSM_3_LOP_POF_OFF_PPU_VPON_PCSM_TUNE_LPM_HV18_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_3_LOP_POF_OFF_PPU_VPON_PCSM_SEL_VREF_HV25_LQ_Pos                                   19U
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_3_LOP_POF_OFF_PPU_VPON_PCSM_SEL_VREF_HV25_LQ_Msk                                   (0x1FUL << AON_LOP_POF_OFF_PPU_VPON_PCSM_3_LOP_POF_OFF_PPU_VPON_PCSM_SEL_VREF_HV25_LQ_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_3_LOP_POF_OFF_PPU_VPON_PCSM_TUNE_VDDCORE_Pos                                       24U
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_3_LOP_POF_OFF_PPU_VPON_PCSM_TUNE_VDDCORE_Msk                                       (0xFFUL << AON_LOP_POF_OFF_PPU_VPON_PCSM_3_LOP_POF_OFF_PPU_VPON_PCSM_TUNE_VDDCORE_Pos)
+
+/* 0xA44    0x4000_0a44
+    0       R/W     LOP_POF_OFF_PPU_VPON_PCSM_ENB_AUTO_PS                       1'b1
+    1       R/W     LOP_POF_OFF_PPU_VPON_PCSM_SEL_SYNC2                         1'b1
+    2       R/W     LOP_POF_OFF_PPU_VPON_PCSM_EN_SYNC2                          1'b0
+    3       R/W     LOP_POF_OFF_PPU_VPON_PCSM_SEL_VO3CMPHQ2_B                   1'b1
+    8:4     R/W     LOP_POF_OFF_PPU_VPON_PCSM_SEL_VREF_VDDPA_HQ2                5'b11000
+    9       R/W     LOP_POF_OFF_PPU_VPON_PCSM_EN_VO3CMPHQ2                      1'b0
+    10      R/W     LOP_POF_OFF_PPU_VPON_PCSM_EN_VO3HQ2BETA                     1'b1
+    11      R/W     LOP_POF_OFF_PPU_VPON_PCSM_PAD_AUTO_SW_PD_EN_RET             1'b1
+    12      R/W     LOP_POF_OFF_PPU_VPON_PCSM_EN_FAST_TRNAS                     1'b1
+    13      R/W     LOP_POF_OFF_PPU_VPON_PCSM_LDO_PA_POS_EN_POS                 1'b0
+    14      R/W     LOP_POF_OFF_PPU_VPON_PCSM_LDO_ANA_POS_EN_POS                1'b0
+    20:15   R/W     LOP_POF_OFF_PPU_VPON_PCSM_LDO_TUNE_LDOPA                    6'b010000
+    25:21   R/W     LOP_POF_OFF_PPU_VPON_PCSM_LDO_TUNE_LDOANA                   5'b01111
+    26      R/W     LOP_POF_OFF_PPU_VPON_PCSM_LDO_ENPC_LDOPA                    1'b0
+    27      R/W     LOP_POF_OFF_PPU_VPON_PCSM_LDO_ENPC_LDOANA                   1'b0
+    28      R/W     LOP_POF_OFF_PPU_VPON_PCSM_LDO_POW_LDOPA                     1'b0
+    29      R/W     LOP_POF_OFF_PPU_VPON_PCSM_LDO_POW_LDOANA                    1'b0
+    30      R/W     LOP_POF_OFF_PPU_VPON_PCSM_LDO_ENB_DMYL_200U_LDOPA           1'b1
+    31      R/W     LOP_POF_OFF_PPU_VPON_PCSM_LDO_ENB_DMYL_200U_LDOANA          1'b1
+ */
+typedef union _AON_LOP_POF_OFF_PPU_VPON_PCSM_4_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t LOP_POF_OFF_PPU_VPON_PCSM_ENB_AUTO_PS: 1;
+        uint32_t LOP_POF_OFF_PPU_VPON_PCSM_SEL_SYNC2: 1;
+        uint32_t LOP_POF_OFF_PPU_VPON_PCSM_EN_SYNC2: 1;
+        uint32_t LOP_POF_OFF_PPU_VPON_PCSM_SEL_VO3CMPHQ2_B: 1;
+        uint32_t LOP_POF_OFF_PPU_VPON_PCSM_SEL_VREF_VDDPA_HQ2: 5;
+        uint32_t LOP_POF_OFF_PPU_VPON_PCSM_EN_VO3CMPHQ2: 1;
+        uint32_t LOP_POF_OFF_PPU_VPON_PCSM_EN_VO3HQ2BETA: 1;
+        uint32_t LOP_POF_OFF_PPU_VPON_PCSM_PAD_AUTO_SW_PD_EN_RET: 1;
+        uint32_t LOP_POF_OFF_PPU_VPON_PCSM_EN_FAST_TRNAS: 1;
+        uint32_t LOP_POF_OFF_PPU_VPON_PCSM_LDO_PA_POS_EN_POS: 1;
+        uint32_t LOP_POF_OFF_PPU_VPON_PCSM_LDO_ANA_POS_EN_POS: 1;
+        uint32_t LOP_POF_OFF_PPU_VPON_PCSM_LDO_TUNE_LDOPA: 6;
+        uint32_t LOP_POF_OFF_PPU_VPON_PCSM_LDO_TUNE_LDOANA: 5;
+        uint32_t LOP_POF_OFF_PPU_VPON_PCSM_LDO_ENPC_LDOPA: 1;
+        uint32_t LOP_POF_OFF_PPU_VPON_PCSM_LDO_ENPC_LDOANA: 1;
+        uint32_t LOP_POF_OFF_PPU_VPON_PCSM_LDO_POW_LDOPA: 1;
+        uint32_t LOP_POF_OFF_PPU_VPON_PCSM_LDO_POW_LDOANA: 1;
+        uint32_t LOP_POF_OFF_PPU_VPON_PCSM_LDO_ENB_DMYL_200U_LDOPA: 1;
+        uint32_t LOP_POF_OFF_PPU_VPON_PCSM_LDO_ENB_DMYL_200U_LDOANA: 1;
+    };
+} AON_LOP_POF_OFF_PPU_VPON_PCSM_4_TYPE;
+
+/*0x4000_0a44 AON_LOP_POF_OFF_PPU_VPON_PCSM_4*/
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_4_LOP_POF_OFF_PPU_VPON_PCSM_ENB_AUTO_PS_Pos                                        0U
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_4_LOP_POF_OFF_PPU_VPON_PCSM_ENB_AUTO_PS_Msk                                        (0x1UL << AON_LOP_POF_OFF_PPU_VPON_PCSM_4_LOP_POF_OFF_PPU_VPON_PCSM_ENB_AUTO_PS_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_4_LOP_POF_OFF_PPU_VPON_PCSM_SEL_SYNC2_Pos                                          1U
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_4_LOP_POF_OFF_PPU_VPON_PCSM_SEL_SYNC2_Msk                                          (0x1UL << AON_LOP_POF_OFF_PPU_VPON_PCSM_4_LOP_POF_OFF_PPU_VPON_PCSM_SEL_SYNC2_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_4_LOP_POF_OFF_PPU_VPON_PCSM_EN_SYNC2_Pos                                           2U
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_4_LOP_POF_OFF_PPU_VPON_PCSM_EN_SYNC2_Msk                                           (0x1UL << AON_LOP_POF_OFF_PPU_VPON_PCSM_4_LOP_POF_OFF_PPU_VPON_PCSM_EN_SYNC2_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_4_LOP_POF_OFF_PPU_VPON_PCSM_SEL_VO3CMPHQ2_B_Pos                                    3U
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_4_LOP_POF_OFF_PPU_VPON_PCSM_SEL_VO3CMPHQ2_B_Msk                                    (0x1UL << AON_LOP_POF_OFF_PPU_VPON_PCSM_4_LOP_POF_OFF_PPU_VPON_PCSM_SEL_VO3CMPHQ2_B_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_4_LOP_POF_OFF_PPU_VPON_PCSM_SEL_VREF_VDDPA_HQ2_Pos                                 4U
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_4_LOP_POF_OFF_PPU_VPON_PCSM_SEL_VREF_VDDPA_HQ2_Msk                                 (0x1FUL << AON_LOP_POF_OFF_PPU_VPON_PCSM_4_LOP_POF_OFF_PPU_VPON_PCSM_SEL_VREF_VDDPA_HQ2_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_4_LOP_POF_OFF_PPU_VPON_PCSM_EN_VO3CMPHQ2_Pos                                       9U
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_4_LOP_POF_OFF_PPU_VPON_PCSM_EN_VO3CMPHQ2_Msk                                       (0x1UL << AON_LOP_POF_OFF_PPU_VPON_PCSM_4_LOP_POF_OFF_PPU_VPON_PCSM_EN_VO3CMPHQ2_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_4_LOP_POF_OFF_PPU_VPON_PCSM_EN_VO3HQ2BETA_Pos                                      10U
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_4_LOP_POF_OFF_PPU_VPON_PCSM_EN_VO3HQ2BETA_Msk                                      (0x1UL << AON_LOP_POF_OFF_PPU_VPON_PCSM_4_LOP_POF_OFF_PPU_VPON_PCSM_EN_VO3HQ2BETA_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_4_LOP_POF_OFF_PPU_VPON_PCSM_PAD_AUTO_SW_PD_EN_RET_Pos                              11U
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_4_LOP_POF_OFF_PPU_VPON_PCSM_PAD_AUTO_SW_PD_EN_RET_Msk                              (0x1UL << AON_LOP_POF_OFF_PPU_VPON_PCSM_4_LOP_POF_OFF_PPU_VPON_PCSM_PAD_AUTO_SW_PD_EN_RET_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_4_LOP_POF_OFF_PPU_VPON_PCSM_EN_FAST_TRNAS_Pos                                      12U
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_4_LOP_POF_OFF_PPU_VPON_PCSM_EN_FAST_TRNAS_Msk                                      (0x1UL << AON_LOP_POF_OFF_PPU_VPON_PCSM_4_LOP_POF_OFF_PPU_VPON_PCSM_EN_FAST_TRNAS_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_4_LOP_POF_OFF_PPU_VPON_PCSM_LDO_PA_POS_EN_POS_Pos                                  13U
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_4_LOP_POF_OFF_PPU_VPON_PCSM_LDO_PA_POS_EN_POS_Msk                                  (0x1UL << AON_LOP_POF_OFF_PPU_VPON_PCSM_4_LOP_POF_OFF_PPU_VPON_PCSM_LDO_PA_POS_EN_POS_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_4_LOP_POF_OFF_PPU_VPON_PCSM_LDO_ANA_POS_EN_POS_Pos                                 14U
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_4_LOP_POF_OFF_PPU_VPON_PCSM_LDO_ANA_POS_EN_POS_Msk                                 (0x1UL << AON_LOP_POF_OFF_PPU_VPON_PCSM_4_LOP_POF_OFF_PPU_VPON_PCSM_LDO_ANA_POS_EN_POS_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_4_LOP_POF_OFF_PPU_VPON_PCSM_LDO_TUNE_LDOPA_Pos                                     15U
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_4_LOP_POF_OFF_PPU_VPON_PCSM_LDO_TUNE_LDOPA_Msk                                     (0x3FUL << AON_LOP_POF_OFF_PPU_VPON_PCSM_4_LOP_POF_OFF_PPU_VPON_PCSM_LDO_TUNE_LDOPA_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_4_LOP_POF_OFF_PPU_VPON_PCSM_LDO_TUNE_LDOANA_Pos                                    21U
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_4_LOP_POF_OFF_PPU_VPON_PCSM_LDO_TUNE_LDOANA_Msk                                    (0x1FUL << AON_LOP_POF_OFF_PPU_VPON_PCSM_4_LOP_POF_OFF_PPU_VPON_PCSM_LDO_TUNE_LDOANA_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_4_LOP_POF_OFF_PPU_VPON_PCSM_LDO_ENPC_LDOPA_Pos                                     26U
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_4_LOP_POF_OFF_PPU_VPON_PCSM_LDO_ENPC_LDOPA_Msk                                     (0x1UL << AON_LOP_POF_OFF_PPU_VPON_PCSM_4_LOP_POF_OFF_PPU_VPON_PCSM_LDO_ENPC_LDOPA_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_4_LOP_POF_OFF_PPU_VPON_PCSM_LDO_ENPC_LDOANA_Pos                                    27U
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_4_LOP_POF_OFF_PPU_VPON_PCSM_LDO_ENPC_LDOANA_Msk                                    (0x1UL << AON_LOP_POF_OFF_PPU_VPON_PCSM_4_LOP_POF_OFF_PPU_VPON_PCSM_LDO_ENPC_LDOANA_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_4_LOP_POF_OFF_PPU_VPON_PCSM_LDO_POW_LDOPA_Pos                                      28U
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_4_LOP_POF_OFF_PPU_VPON_PCSM_LDO_POW_LDOPA_Msk                                      (0x1UL << AON_LOP_POF_OFF_PPU_VPON_PCSM_4_LOP_POF_OFF_PPU_VPON_PCSM_LDO_POW_LDOPA_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_4_LOP_POF_OFF_PPU_VPON_PCSM_LDO_POW_LDOANA_Pos                                     29U
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_4_LOP_POF_OFF_PPU_VPON_PCSM_LDO_POW_LDOANA_Msk                                     (0x1UL << AON_LOP_POF_OFF_PPU_VPON_PCSM_4_LOP_POF_OFF_PPU_VPON_PCSM_LDO_POW_LDOANA_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_4_LOP_POF_OFF_PPU_VPON_PCSM_LDO_ENB_DMYL_200U_LDOPA_Pos                            30U
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_4_LOP_POF_OFF_PPU_VPON_PCSM_LDO_ENB_DMYL_200U_LDOPA_Msk                            (0x1UL << AON_LOP_POF_OFF_PPU_VPON_PCSM_4_LOP_POF_OFF_PPU_VPON_PCSM_LDO_ENB_DMYL_200U_LDOPA_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_4_LOP_POF_OFF_PPU_VPON_PCSM_LDO_ENB_DMYL_200U_LDOANA_Pos                           31U
+#define AON_LOP_POF_OFF_PPU_VPON_PCSM_4_LOP_POF_OFF_PPU_VPON_PCSM_LDO_ENB_DMYL_200U_LDOANA_Msk                           (0x1UL << AON_LOP_POF_OFF_PPU_VPON_PCSM_4_LOP_POF_OFF_PPU_VPON_PCSM_LDO_ENB_DMYL_200U_LDOANA_Pos)
+
+/* 0xA48    0x4000_0a48
+    0       R/W     LOP_POF_MEM_OFF_PPU_VPON_PCSM_VDDIO_EN_DISCHG               1'b0
+    1       R/W     LOP_POF_MEM_OFF_PPU_VPON_PCSM_VDDIO_EN_PC2                  1'b1
+    2       R/W     LOP_POF_MEM_OFF_PPU_VPON_PCSM_VDDIO_EN_PC1                  1'b1
+    3       R/W     LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_SYNC                       1'b0
+    4       R/W     LOP_POF_MEM_OFF_PPU_VPON_PCSM_POW_VDIV_LQ_VDDCORE           1'b1
+    5       R/W     LOP_POF_MEM_OFF_PPU_VPON_PCSM_POW_VDIV_LQ_HV18              1'b0
+    6       R/W     LOP_POF_MEM_OFF_PPU_VPON_PCSM_POW_VDIV_HQ_VDDCORE           1'b0
+    7       R/W     LOP_POF_MEM_OFF_PPU_VPON_PCSM_POW_VDIV_HQ_VDDPA             1'b0
+    8       R/W     LOP_POF_MEM_OFF_PPU_VPON_PCSM_POW_VDIV_HQ_HV18              1'b0
+    9       R/W     LOP_POF_MEM_OFF_PPU_VPON_PCSM_POW_VDIV_HQ_HV25              1'b0
+    10      R/W     LOP_POF_MEM_OFF_PPU_VPON_PCSM_REG_ENHQ_REFCMP               1'b0
+    11      R/W     LOP_POF_MEM_OFF_PPU_VPON_PCSM_BYP_OPOR_LD                   1'b0
+    12      R/W     LOP_POF_MEM_OFF_PPU_VPON_PCSM_REG_ENLPM                     1'b1
+    13      R/W     LOP_POF_MEM_OFF_PPU_VPON_PCSM_REG_ENPCCM                    1'b0
+    14      R/W     LOP_POF_MEM_OFF_PPU_VPON_PCSM_ENCCM_OUT_VDDCORE             1'b0
+    15      R/W     LOP_POF_MEM_OFF_PPU_VPON_PCSM_ENCCM_OUT_VDDPA               1'b0
+    16      R/W     LOP_POF_MEM_OFF_PPU_VPON_PCSM_ENCCM_OUT_HV18                1'b0
+    17      R/W     LOP_POF_MEM_OFF_PPU_VPON_PCSM_ENCCM_OUT_HV25                1'b0
+    19:18   R/W     LOP_POF_MEM_OFF_PPU_VPON_PCSM_ZCDLY_SET                     2'b10
+    20      R/W     LOP_POF_MEM_OFF_PPU_VPON_PCSM_ENDLY_FOR_K                   1'b1
+    21      R/W     LOP_POF_MEM_OFF_PPU_VPON_PCSM_BUCK_BOOST_VDDPA_POS_RSTB     1'b0
+    22      R/W     LOP_POF_MEM_OFF_PPU_VPON_PCSM_BUCK_BOOST_HV18_POS_RSTB      1'b0
+    23      R/W     LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_DMYLOAD_VDDCORE            1'b0
+    24      R/W     LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_DMYLOAD_VDDPA              1'b0
+    25      R/W     LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_DMYLOAD_HV18               1'b0
+    26      R/W     LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_DMYLOAD_HV25               1'b0
+    27      R/W     LOP_POF_MEM_OFF_PPU_VPON_PCSM_POW_VDDPA_DET                 1'b0
+    28      R/W     LOP_POF_MEM_OFF_PPU_VPON_PCSM_POW_HV18_DET                  1'b0
+    29      R/W     LOP_POF_MEM_OFF_PPU_VPON_PCSM_POW_VDDCORE_DET               1'b0
+    30      R/W     LOP_POF_MEM_OFF_PPU_VPON_PCSM_POW_VANA_DET                  1'b0
+    31      R/W     LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_BIAS_10UA                  1'b0
+ */
+typedef union _AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_1_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t LOP_POF_MEM_OFF_PPU_VPON_PCSM_VDDIO_EN_DISCHG: 1;
+        uint32_t LOP_POF_MEM_OFF_PPU_VPON_PCSM_VDDIO_EN_PC2: 1;
+        uint32_t LOP_POF_MEM_OFF_PPU_VPON_PCSM_VDDIO_EN_PC1: 1;
+        uint32_t LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_SYNC: 1;
+        uint32_t LOP_POF_MEM_OFF_PPU_VPON_PCSM_POW_VDIV_LQ_VDDCORE: 1;
+        uint32_t LOP_POF_MEM_OFF_PPU_VPON_PCSM_POW_VDIV_LQ_HV18: 1;
+        uint32_t LOP_POF_MEM_OFF_PPU_VPON_PCSM_POW_VDIV_HQ_VDDCORE: 1;
+        uint32_t LOP_POF_MEM_OFF_PPU_VPON_PCSM_POW_VDIV_HQ_VDDPA: 1;
+        uint32_t LOP_POF_MEM_OFF_PPU_VPON_PCSM_POW_VDIV_HQ_HV18: 1;
+        uint32_t LOP_POF_MEM_OFF_PPU_VPON_PCSM_POW_VDIV_HQ_HV25: 1;
+        uint32_t LOP_POF_MEM_OFF_PPU_VPON_PCSM_REG_ENHQ_REFCMP: 1;
+        uint32_t LOP_POF_MEM_OFF_PPU_VPON_PCSM_BYP_OPOR_LD: 1;
+        uint32_t LOP_POF_MEM_OFF_PPU_VPON_PCSM_REG_ENLPM: 1;
+        uint32_t LOP_POF_MEM_OFF_PPU_VPON_PCSM_REG_ENPCCM: 1;
+        uint32_t LOP_POF_MEM_OFF_PPU_VPON_PCSM_ENCCM_OUT_VDDCORE: 1;
+        uint32_t LOP_POF_MEM_OFF_PPU_VPON_PCSM_ENCCM_OUT_VDDPA: 1;
+        uint32_t LOP_POF_MEM_OFF_PPU_VPON_PCSM_ENCCM_OUT_HV18: 1;
+        uint32_t LOP_POF_MEM_OFF_PPU_VPON_PCSM_ENCCM_OUT_HV25: 1;
+        uint32_t LOP_POF_MEM_OFF_PPU_VPON_PCSM_ZCDLY_SET: 2;
+        uint32_t LOP_POF_MEM_OFF_PPU_VPON_PCSM_ENDLY_FOR_K: 1;
+        uint32_t LOP_POF_MEM_OFF_PPU_VPON_PCSM_BUCK_BOOST_VDDPA_POS_RSTB: 1;
+        uint32_t LOP_POF_MEM_OFF_PPU_VPON_PCSM_BUCK_BOOST_HV18_POS_RSTB: 1;
+        uint32_t LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_DMYLOAD_VDDCORE: 1;
+        uint32_t LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_DMYLOAD_VDDPA: 1;
+        uint32_t LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_DMYLOAD_HV18: 1;
+        uint32_t LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_DMYLOAD_HV25: 1;
+        uint32_t LOP_POF_MEM_OFF_PPU_VPON_PCSM_POW_VDDPA_DET: 1;
+        uint32_t LOP_POF_MEM_OFF_PPU_VPON_PCSM_POW_HV18_DET: 1;
+        uint32_t LOP_POF_MEM_OFF_PPU_VPON_PCSM_POW_VDDCORE_DET: 1;
+        uint32_t LOP_POF_MEM_OFF_PPU_VPON_PCSM_POW_VANA_DET: 1;
+        uint32_t LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_BIAS_10UA: 1;
+    };
+} AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_1_TYPE;
+
+/*0x4000_0a48 AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_1*/
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_1_LOP_POF_MEM_OFF_PPU_VPON_PCSM_VDDIO_EN_DISCHG_Pos                            0U
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_1_LOP_POF_MEM_OFF_PPU_VPON_PCSM_VDDIO_EN_DISCHG_Msk                            (0x1UL << AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_1_LOP_POF_MEM_OFF_PPU_VPON_PCSM_VDDIO_EN_DISCHG_Pos)
+
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_1_LOP_POF_MEM_OFF_PPU_VPON_PCSM_VDDIO_EN_PC2_Pos                               1U
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_1_LOP_POF_MEM_OFF_PPU_VPON_PCSM_VDDIO_EN_PC2_Msk                               (0x1UL << AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_1_LOP_POF_MEM_OFF_PPU_VPON_PCSM_VDDIO_EN_PC2_Pos)
+
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_1_LOP_POF_MEM_OFF_PPU_VPON_PCSM_VDDIO_EN_PC1_Pos                               2U
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_1_LOP_POF_MEM_OFF_PPU_VPON_PCSM_VDDIO_EN_PC1_Msk                               (0x1UL << AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_1_LOP_POF_MEM_OFF_PPU_VPON_PCSM_VDDIO_EN_PC1_Pos)
+
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_1_LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_SYNC_Pos                                    3U
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_1_LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_SYNC_Msk                                    (0x1UL << AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_1_LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_SYNC_Pos)
+
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_1_LOP_POF_MEM_OFF_PPU_VPON_PCSM_POW_VDIV_LQ_VDDCORE_Pos                        4U
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_1_LOP_POF_MEM_OFF_PPU_VPON_PCSM_POW_VDIV_LQ_VDDCORE_Msk                        (0x1UL << AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_1_LOP_POF_MEM_OFF_PPU_VPON_PCSM_POW_VDIV_LQ_VDDCORE_Pos)
+
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_1_LOP_POF_MEM_OFF_PPU_VPON_PCSM_POW_VDIV_LQ_HV18_Pos                           5U
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_1_LOP_POF_MEM_OFF_PPU_VPON_PCSM_POW_VDIV_LQ_HV18_Msk                           (0x1UL << AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_1_LOP_POF_MEM_OFF_PPU_VPON_PCSM_POW_VDIV_LQ_HV18_Pos)
+
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_1_LOP_POF_MEM_OFF_PPU_VPON_PCSM_POW_VDIV_HQ_VDDCORE_Pos                        6U
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_1_LOP_POF_MEM_OFF_PPU_VPON_PCSM_POW_VDIV_HQ_VDDCORE_Msk                        (0x1UL << AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_1_LOP_POF_MEM_OFF_PPU_VPON_PCSM_POW_VDIV_HQ_VDDCORE_Pos)
+
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_1_LOP_POF_MEM_OFF_PPU_VPON_PCSM_POW_VDIV_HQ_VDDPA_Pos                          7U
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_1_LOP_POF_MEM_OFF_PPU_VPON_PCSM_POW_VDIV_HQ_VDDPA_Msk                          (0x1UL << AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_1_LOP_POF_MEM_OFF_PPU_VPON_PCSM_POW_VDIV_HQ_VDDPA_Pos)
+
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_1_LOP_POF_MEM_OFF_PPU_VPON_PCSM_POW_VDIV_HQ_HV18_Pos                           8U
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_1_LOP_POF_MEM_OFF_PPU_VPON_PCSM_POW_VDIV_HQ_HV18_Msk                           (0x1UL << AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_1_LOP_POF_MEM_OFF_PPU_VPON_PCSM_POW_VDIV_HQ_HV18_Pos)
+
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_1_LOP_POF_MEM_OFF_PPU_VPON_PCSM_POW_VDIV_HQ_HV25_Pos                           9U
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_1_LOP_POF_MEM_OFF_PPU_VPON_PCSM_POW_VDIV_HQ_HV25_Msk                           (0x1UL << AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_1_LOP_POF_MEM_OFF_PPU_VPON_PCSM_POW_VDIV_HQ_HV25_Pos)
+
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_1_LOP_POF_MEM_OFF_PPU_VPON_PCSM_REG_ENHQ_REFCMP_Pos                            10U
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_1_LOP_POF_MEM_OFF_PPU_VPON_PCSM_REG_ENHQ_REFCMP_Msk                            (0x1UL << AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_1_LOP_POF_MEM_OFF_PPU_VPON_PCSM_REG_ENHQ_REFCMP_Pos)
+
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_1_LOP_POF_MEM_OFF_PPU_VPON_PCSM_BYP_OPOR_LD_Pos                                11U
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_1_LOP_POF_MEM_OFF_PPU_VPON_PCSM_BYP_OPOR_LD_Msk                                (0x1UL << AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_1_LOP_POF_MEM_OFF_PPU_VPON_PCSM_BYP_OPOR_LD_Pos)
+
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_1_LOP_POF_MEM_OFF_PPU_VPON_PCSM_REG_ENLPM_Pos                                  12U
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_1_LOP_POF_MEM_OFF_PPU_VPON_PCSM_REG_ENLPM_Msk                                  (0x1UL << AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_1_LOP_POF_MEM_OFF_PPU_VPON_PCSM_REG_ENLPM_Pos)
+
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_1_LOP_POF_MEM_OFF_PPU_VPON_PCSM_REG_ENPCCM_Pos                                 13U
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_1_LOP_POF_MEM_OFF_PPU_VPON_PCSM_REG_ENPCCM_Msk                                 (0x1UL << AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_1_LOP_POF_MEM_OFF_PPU_VPON_PCSM_REG_ENPCCM_Pos)
+
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_1_LOP_POF_MEM_OFF_PPU_VPON_PCSM_ENCCM_OUT_VDDCORE_Pos                          14U
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_1_LOP_POF_MEM_OFF_PPU_VPON_PCSM_ENCCM_OUT_VDDCORE_Msk                          (0x1UL << AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_1_LOP_POF_MEM_OFF_PPU_VPON_PCSM_ENCCM_OUT_VDDCORE_Pos)
+
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_1_LOP_POF_MEM_OFF_PPU_VPON_PCSM_ENCCM_OUT_VDDPA_Pos                            15U
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_1_LOP_POF_MEM_OFF_PPU_VPON_PCSM_ENCCM_OUT_VDDPA_Msk                            (0x1UL << AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_1_LOP_POF_MEM_OFF_PPU_VPON_PCSM_ENCCM_OUT_VDDPA_Pos)
+
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_1_LOP_POF_MEM_OFF_PPU_VPON_PCSM_ENCCM_OUT_HV18_Pos                             16U
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_1_LOP_POF_MEM_OFF_PPU_VPON_PCSM_ENCCM_OUT_HV18_Msk                             (0x1UL << AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_1_LOP_POF_MEM_OFF_PPU_VPON_PCSM_ENCCM_OUT_HV18_Pos)
+
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_1_LOP_POF_MEM_OFF_PPU_VPON_PCSM_ENCCM_OUT_HV25_Pos                             17U
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_1_LOP_POF_MEM_OFF_PPU_VPON_PCSM_ENCCM_OUT_HV25_Msk                             (0x1UL << AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_1_LOP_POF_MEM_OFF_PPU_VPON_PCSM_ENCCM_OUT_HV25_Pos)
+
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_1_LOP_POF_MEM_OFF_PPU_VPON_PCSM_ZCDLY_SET_Pos                                  18U
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_1_LOP_POF_MEM_OFF_PPU_VPON_PCSM_ZCDLY_SET_Msk                                  (0x3UL << AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_1_LOP_POF_MEM_OFF_PPU_VPON_PCSM_ZCDLY_SET_Pos)
+
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_1_LOP_POF_MEM_OFF_PPU_VPON_PCSM_ENDLY_FOR_K_Pos                                20U
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_1_LOP_POF_MEM_OFF_PPU_VPON_PCSM_ENDLY_FOR_K_Msk                                (0x1UL << AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_1_LOP_POF_MEM_OFF_PPU_VPON_PCSM_ENDLY_FOR_K_Pos)
+
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_1_LOP_POF_MEM_OFF_PPU_VPON_PCSM_BUCK_BOOST_VDDPA_POS_RSTB_Pos                  21U
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_1_LOP_POF_MEM_OFF_PPU_VPON_PCSM_BUCK_BOOST_VDDPA_POS_RSTB_Msk                  (0x1UL << AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_1_LOP_POF_MEM_OFF_PPU_VPON_PCSM_BUCK_BOOST_VDDPA_POS_RSTB_Pos)
+
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_1_LOP_POF_MEM_OFF_PPU_VPON_PCSM_BUCK_BOOST_HV18_POS_RSTB_Pos                   22U
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_1_LOP_POF_MEM_OFF_PPU_VPON_PCSM_BUCK_BOOST_HV18_POS_RSTB_Msk                   (0x1UL << AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_1_LOP_POF_MEM_OFF_PPU_VPON_PCSM_BUCK_BOOST_HV18_POS_RSTB_Pos)
+
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_1_LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_DMYLOAD_VDDCORE_Pos                         23U
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_1_LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_DMYLOAD_VDDCORE_Msk                         (0x1UL << AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_1_LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_DMYLOAD_VDDCORE_Pos)
+
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_1_LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_DMYLOAD_VDDPA_Pos                           24U
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_1_LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_DMYLOAD_VDDPA_Msk                           (0x1UL << AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_1_LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_DMYLOAD_VDDPA_Pos)
+
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_1_LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_DMYLOAD_HV18_Pos                            25U
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_1_LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_DMYLOAD_HV18_Msk                            (0x1UL << AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_1_LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_DMYLOAD_HV18_Pos)
+
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_1_LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_DMYLOAD_HV25_Pos                            26U
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_1_LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_DMYLOAD_HV25_Msk                            (0x1UL << AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_1_LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_DMYLOAD_HV25_Pos)
+
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_1_LOP_POF_MEM_OFF_PPU_VPON_PCSM_POW_VDDPA_DET_Pos                              27U
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_1_LOP_POF_MEM_OFF_PPU_VPON_PCSM_POW_VDDPA_DET_Msk                              (0x1UL << AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_1_LOP_POF_MEM_OFF_PPU_VPON_PCSM_POW_VDDPA_DET_Pos)
+
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_1_LOP_POF_MEM_OFF_PPU_VPON_PCSM_POW_HV18_DET_Pos                               28U
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_1_LOP_POF_MEM_OFF_PPU_VPON_PCSM_POW_HV18_DET_Msk                               (0x1UL << AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_1_LOP_POF_MEM_OFF_PPU_VPON_PCSM_POW_HV18_DET_Pos)
+
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_1_LOP_POF_MEM_OFF_PPU_VPON_PCSM_POW_VDDCORE_DET_Pos                            29U
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_1_LOP_POF_MEM_OFF_PPU_VPON_PCSM_POW_VDDCORE_DET_Msk                            (0x1UL << AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_1_LOP_POF_MEM_OFF_PPU_VPON_PCSM_POW_VDDCORE_DET_Pos)
+
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_1_LOP_POF_MEM_OFF_PPU_VPON_PCSM_POW_VANA_DET_Pos                               30U
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_1_LOP_POF_MEM_OFF_PPU_VPON_PCSM_POW_VANA_DET_Msk                               (0x1UL << AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_1_LOP_POF_MEM_OFF_PPU_VPON_PCSM_POW_VANA_DET_Pos)
+
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_1_LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_BIAS_10UA_Pos                               31U
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_1_LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_BIAS_10UA_Msk                               (0x1UL << AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_1_LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_BIAS_10UA_Pos)
+
+/* 0xA4C    0x4000_0a4c
+    0       R/W     LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_MCM_FLASH_PC2              1'b0
+    1       R/W     LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_MCM_FLASH_PC1              1'b0
+    2       R/W     LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_DISCHG_MCM_FLASH           1'b1
+    3       R/W     LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_BIAS_1UA                   1'b0
+    4       R/W     LOP_POF_MEM_OFF_PPU_VPON_PCSM_IO_RSTB33_EN                  1'b1
+    5       R/W     LOP_POF_MEM_OFF_PPU_VPON_PCSM_IO_SHDN33_EN                  1'b1
+    13:6    R/W     LOP_POF_MEM_OFF_PPU_VPON_PCSM_TUNE_VDDPA                    8'b00100010
+    19:14   R/W     LOP_POF_MEM_OFF_PPU_VPON_PCSM_TUNE_HV18                     6'b100000
+    24:20   R/W     LOP_POF_MEM_OFF_PPU_VPON_PCSM_SEL_VREF_HV25_HQ              5'b01111
+    25      R/W     LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_CMP_LQ_VDDCORE             1'b1
+    26      R/W     LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_CMP_LQ_HV18                1'b0
+    27      R/W     LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_CMP_LQ_HV25                1'b1
+    28      R/W     LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_CMP_HQ_VDDCORE             1'b0
+    29      R/W     LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_CMP_HQ_VDDPA               1'b0
+    30      R/W     LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_CMP_HQ_HV18                1'b0
+    31      R/W     LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_CMP_HQ_HV25                1'b0
+ */
+typedef union _AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_2_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_MCM_FLASH_PC2: 1;
+        uint32_t LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_MCM_FLASH_PC1: 1;
+        uint32_t LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_DISCHG_MCM_FLASH: 1;
+        uint32_t LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_BIAS_1UA: 1;
+        uint32_t LOP_POF_MEM_OFF_PPU_VPON_PCSM_IO_RSTB33_EN: 1;
+        uint32_t LOP_POF_MEM_OFF_PPU_VPON_PCSM_IO_SHDN33_EN: 1;
+        uint32_t LOP_POF_MEM_OFF_PPU_VPON_PCSM_TUNE_VDDPA: 8;
+        uint32_t LOP_POF_MEM_OFF_PPU_VPON_PCSM_TUNE_HV18: 6;
+        uint32_t LOP_POF_MEM_OFF_PPU_VPON_PCSM_SEL_VREF_HV25_HQ: 5;
+        uint32_t LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_CMP_LQ_VDDCORE: 1;
+        uint32_t LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_CMP_LQ_HV18: 1;
+        uint32_t LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_CMP_LQ_HV25: 1;
+        uint32_t LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_CMP_HQ_VDDCORE: 1;
+        uint32_t LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_CMP_HQ_VDDPA: 1;
+        uint32_t LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_CMP_HQ_HV18: 1;
+        uint32_t LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_CMP_HQ_HV25: 1;
+    };
+} AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_2_TYPE;
+
+/*0x4000_0a4c AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_2*/
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_2_LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_MCM_FLASH_PC2_Pos                           0U
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_2_LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_MCM_FLASH_PC2_Msk                           (0x1UL << AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_2_LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_MCM_FLASH_PC2_Pos)
+
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_2_LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_MCM_FLASH_PC1_Pos                           1U
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_2_LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_MCM_FLASH_PC1_Msk                           (0x1UL << AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_2_LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_MCM_FLASH_PC1_Pos)
+
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_2_LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_DISCHG_MCM_FLASH_Pos                        2U
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_2_LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_DISCHG_MCM_FLASH_Msk                        (0x1UL << AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_2_LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_DISCHG_MCM_FLASH_Pos)
+
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_2_LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_BIAS_1UA_Pos                                3U
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_2_LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_BIAS_1UA_Msk                                (0x1UL << AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_2_LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_BIAS_1UA_Pos)
+
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_2_LOP_POF_MEM_OFF_PPU_VPON_PCSM_IO_RSTB33_EN_Pos                               4U
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_2_LOP_POF_MEM_OFF_PPU_VPON_PCSM_IO_RSTB33_EN_Msk                               (0x1UL << AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_2_LOP_POF_MEM_OFF_PPU_VPON_PCSM_IO_RSTB33_EN_Pos)
+
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_2_LOP_POF_MEM_OFF_PPU_VPON_PCSM_IO_SHDN33_EN_Pos                               5U
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_2_LOP_POF_MEM_OFF_PPU_VPON_PCSM_IO_SHDN33_EN_Msk                               (0x1UL << AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_2_LOP_POF_MEM_OFF_PPU_VPON_PCSM_IO_SHDN33_EN_Pos)
+
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_2_LOP_POF_MEM_OFF_PPU_VPON_PCSM_TUNE_VDDPA_Pos                                 6U
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_2_LOP_POF_MEM_OFF_PPU_VPON_PCSM_TUNE_VDDPA_Msk                                 (0xFFUL << AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_2_LOP_POF_MEM_OFF_PPU_VPON_PCSM_TUNE_VDDPA_Pos)
+
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_2_LOP_POF_MEM_OFF_PPU_VPON_PCSM_TUNE_HV18_Pos                                  14U
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_2_LOP_POF_MEM_OFF_PPU_VPON_PCSM_TUNE_HV18_Msk                                  (0x3FUL << AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_2_LOP_POF_MEM_OFF_PPU_VPON_PCSM_TUNE_HV18_Pos)
+
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_2_LOP_POF_MEM_OFF_PPU_VPON_PCSM_SEL_VREF_HV25_HQ_Pos                           20U
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_2_LOP_POF_MEM_OFF_PPU_VPON_PCSM_SEL_VREF_HV25_HQ_Msk                           (0x1FUL << AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_2_LOP_POF_MEM_OFF_PPU_VPON_PCSM_SEL_VREF_HV25_HQ_Pos)
+
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_2_LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_CMP_LQ_VDDCORE_Pos                          25U
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_2_LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_CMP_LQ_VDDCORE_Msk                          (0x1UL << AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_2_LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_CMP_LQ_VDDCORE_Pos)
+
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_2_LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_CMP_LQ_HV18_Pos                             26U
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_2_LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_CMP_LQ_HV18_Msk                             (0x1UL << AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_2_LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_CMP_LQ_HV18_Pos)
+
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_2_LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_CMP_LQ_HV25_Pos                             27U
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_2_LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_CMP_LQ_HV25_Msk                             (0x1UL << AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_2_LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_CMP_LQ_HV25_Pos)
+
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_2_LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_CMP_HQ_VDDCORE_Pos                          28U
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_2_LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_CMP_HQ_VDDCORE_Msk                          (0x1UL << AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_2_LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_CMP_HQ_VDDCORE_Pos)
+
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_2_LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_CMP_HQ_VDDPA_Pos                            29U
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_2_LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_CMP_HQ_VDDPA_Msk                            (0x1UL << AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_2_LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_CMP_HQ_VDDPA_Pos)
+
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_2_LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_CMP_HQ_HV18_Pos                             30U
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_2_LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_CMP_HQ_HV18_Msk                             (0x1UL << AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_2_LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_CMP_HQ_HV18_Pos)
+
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_2_LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_CMP_HQ_HV25_Pos                             31U
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_2_LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_CMP_HQ_HV25_Msk                             (0x1UL << AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_2_LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_CMP_HQ_HV25_Pos)
+
+/* 0xA50    0x4000_0a50
+    1:0     R/W     RESERVED                                                    2'h0
+    2       R/W     LOP_POF_MEM_OFF_PPU_VPON_PCSM_LDO_PA_POS_RSTB               1'b0
+    3       R/W     LOP_POF_MEM_OFF_PPU_VPON_PCSM_LDO_ANA_POS_RSTB              1'b0
+    4       R/W     LOP_POF_MEM_OFF_PPU_VPON_PCSM_LDO_POW_BIAS_LDOPA            1'b0
+    5       R/W     LOP_POF_MEM_OFF_PPU_VPON_PCSM_LDO_POW_BIAS_LDOANA           1'b0
+    6       R/W     LOP_POF_MEM_OFF_PPU_VPON_PCSM_BUCK_BOOST_VDDPA_POS_EN_POS   1'b0
+    7       R/W     LOP_POF_MEM_OFF_PPU_VPON_PCSM_BUCK_BOOST_HV18_POS_EN_POS    1'b0
+    12:8    R/W     LOP_POF_MEM_OFF_PPU_VPON_PCSM_SEL_VREF_VDDCORE_LQ           5'b01110
+    18:13   R/W     LOP_POF_MEM_OFF_PPU_VPON_PCSM_TUNE_LPM_HV18                 6'b100000
+    23:19   R/W     LOP_POF_MEM_OFF_PPU_VPON_PCSM_SEL_VREF_HV25_LQ              5'b01111
+    31:24   R/W     LOP_POF_MEM_OFF_PPU_VPON_PCSM_TUNE_VDDCORE                  8'b01100010
+ */
+typedef union _AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_3_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED: 2;
+        uint32_t LOP_POF_MEM_OFF_PPU_VPON_PCSM_LDO_PA_POS_RSTB: 1;
+        uint32_t LOP_POF_MEM_OFF_PPU_VPON_PCSM_LDO_ANA_POS_RSTB: 1;
+        uint32_t LOP_POF_MEM_OFF_PPU_VPON_PCSM_LDO_POW_BIAS_LDOPA: 1;
+        uint32_t LOP_POF_MEM_OFF_PPU_VPON_PCSM_LDO_POW_BIAS_LDOANA: 1;
+        uint32_t LOP_POF_MEM_OFF_PPU_VPON_PCSM_BUCK_BOOST_VDDPA_POS_EN_POS: 1;
+        uint32_t LOP_POF_MEM_OFF_PPU_VPON_PCSM_BUCK_BOOST_HV18_POS_EN_POS: 1;
+        uint32_t LOP_POF_MEM_OFF_PPU_VPON_PCSM_SEL_VREF_VDDCORE_LQ: 5;
+        uint32_t LOP_POF_MEM_OFF_PPU_VPON_PCSM_TUNE_LPM_HV18: 6;
+        uint32_t LOP_POF_MEM_OFF_PPU_VPON_PCSM_SEL_VREF_HV25_LQ: 5;
+        uint32_t LOP_POF_MEM_OFF_PPU_VPON_PCSM_TUNE_VDDCORE: 8;
+    };
+} AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_3_TYPE;
+
+/*0x4000_0a50 AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_3*/
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_3_RESERVED_Pos                                                                 0U
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_3_RESERVED_Msk                                                                 (0x3UL << AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_3_RESERVED_Pos)
+
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_3_LOP_POF_MEM_OFF_PPU_VPON_PCSM_LDO_PA_POS_RSTB_Pos                            2U
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_3_LOP_POF_MEM_OFF_PPU_VPON_PCSM_LDO_PA_POS_RSTB_Msk                            (0x1UL << AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_3_LOP_POF_MEM_OFF_PPU_VPON_PCSM_LDO_PA_POS_RSTB_Pos)
+
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_3_LOP_POF_MEM_OFF_PPU_VPON_PCSM_LDO_ANA_POS_RSTB_Pos                           3U
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_3_LOP_POF_MEM_OFF_PPU_VPON_PCSM_LDO_ANA_POS_RSTB_Msk                           (0x1UL << AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_3_LOP_POF_MEM_OFF_PPU_VPON_PCSM_LDO_ANA_POS_RSTB_Pos)
+
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_3_LOP_POF_MEM_OFF_PPU_VPON_PCSM_LDO_POW_BIAS_LDOPA_Pos                         4U
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_3_LOP_POF_MEM_OFF_PPU_VPON_PCSM_LDO_POW_BIAS_LDOPA_Msk                         (0x1UL << AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_3_LOP_POF_MEM_OFF_PPU_VPON_PCSM_LDO_POW_BIAS_LDOPA_Pos)
+
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_3_LOP_POF_MEM_OFF_PPU_VPON_PCSM_LDO_POW_BIAS_LDOANA_Pos                        5U
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_3_LOP_POF_MEM_OFF_PPU_VPON_PCSM_LDO_POW_BIAS_LDOANA_Msk                        (0x1UL << AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_3_LOP_POF_MEM_OFF_PPU_VPON_PCSM_LDO_POW_BIAS_LDOANA_Pos)
+
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_3_LOP_POF_MEM_OFF_PPU_VPON_PCSM_BUCK_BOOST_VDDPA_POS_EN_POS_Pos                6U
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_3_LOP_POF_MEM_OFF_PPU_VPON_PCSM_BUCK_BOOST_VDDPA_POS_EN_POS_Msk                (0x1UL << AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_3_LOP_POF_MEM_OFF_PPU_VPON_PCSM_BUCK_BOOST_VDDPA_POS_EN_POS_Pos)
+
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_3_LOP_POF_MEM_OFF_PPU_VPON_PCSM_BUCK_BOOST_HV18_POS_EN_POS_Pos                 7U
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_3_LOP_POF_MEM_OFF_PPU_VPON_PCSM_BUCK_BOOST_HV18_POS_EN_POS_Msk                 (0x1UL << AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_3_LOP_POF_MEM_OFF_PPU_VPON_PCSM_BUCK_BOOST_HV18_POS_EN_POS_Pos)
+
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_3_LOP_POF_MEM_OFF_PPU_VPON_PCSM_SEL_VREF_VDDCORE_LQ_Pos                        8U
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_3_LOP_POF_MEM_OFF_PPU_VPON_PCSM_SEL_VREF_VDDCORE_LQ_Msk                        (0x1FUL << AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_3_LOP_POF_MEM_OFF_PPU_VPON_PCSM_SEL_VREF_VDDCORE_LQ_Pos)
+
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_3_LOP_POF_MEM_OFF_PPU_VPON_PCSM_TUNE_LPM_HV18_Pos                              13U
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_3_LOP_POF_MEM_OFF_PPU_VPON_PCSM_TUNE_LPM_HV18_Msk                              (0x3FUL << AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_3_LOP_POF_MEM_OFF_PPU_VPON_PCSM_TUNE_LPM_HV18_Pos)
+
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_3_LOP_POF_MEM_OFF_PPU_VPON_PCSM_SEL_VREF_HV25_LQ_Pos                           19U
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_3_LOP_POF_MEM_OFF_PPU_VPON_PCSM_SEL_VREF_HV25_LQ_Msk                           (0x1FUL << AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_3_LOP_POF_MEM_OFF_PPU_VPON_PCSM_SEL_VREF_HV25_LQ_Pos)
+
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_3_LOP_POF_MEM_OFF_PPU_VPON_PCSM_TUNE_VDDCORE_Pos                               24U
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_3_LOP_POF_MEM_OFF_PPU_VPON_PCSM_TUNE_VDDCORE_Msk                               (0xFFUL << AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_3_LOP_POF_MEM_OFF_PPU_VPON_PCSM_TUNE_VDDCORE_Pos)
+
+/* 0xA54    0x4000_0a54
+    0       R/W     LOP_POF_MEM_OFF_PPU_VPON_PCSM_ENB_AUTO_PS                   1'b1
+    1       R/W     LOP_POF_MEM_OFF_PPU_VPON_PCSM_SEL_SYNC2                     1'b1
+    2       R/W     LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_SYNC2                      1'b0
+    3       R/W     LOP_POF_MEM_OFF_PPU_VPON_PCSM_SEL_VO3CMPHQ2_B               1'b1
+    8:4     R/W     LOP_POF_MEM_OFF_PPU_VPON_PCSM_SEL_VREF_VDDPA_HQ2            5'b11000
+    9       R/W     LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_VO3CMPHQ2                  1'b0
+    10      R/W     LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_VO3HQ2BETA                 1'b1
+    11      R/W     LOP_POF_MEM_OFF_PPU_VPON_PCSM_PAD_AUTO_SW_PD_EN_RET         1'b1
+    12      R/W     LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_FAST_TRNAS                 1'b1
+    13      R/W     LOP_POF_MEM_OFF_PPU_VPON_PCSM_LDO_PA_POS_EN_POS             1'b0
+    14      R/W     LOP_POF_MEM_OFF_PPU_VPON_PCSM_LDO_ANA_POS_EN_POS            1'b0
+    20:15   R/W     LOP_POF_MEM_OFF_PPU_VPON_PCSM_LDO_TUNE_LDOPA                6'b010000
+    25:21   R/W     LOP_POF_MEM_OFF_PPU_VPON_PCSM_LDO_TUNE_LDOANA               5'b01111
+    26      R/W     LOP_POF_MEM_OFF_PPU_VPON_PCSM_LDO_ENPC_LDOPA                1'b0
+    27      R/W     LOP_POF_MEM_OFF_PPU_VPON_PCSM_LDO_ENPC_LDOANA               1'b0
+    28      R/W     LOP_POF_MEM_OFF_PPU_VPON_PCSM_LDO_POW_LDOPA                 1'b0
+    29      R/W     LOP_POF_MEM_OFF_PPU_VPON_PCSM_LDO_POW_LDOANA                1'b0
+    30      R/W     LOP_POF_MEM_OFF_PPU_VPON_PCSM_LDO_ENB_DMYL_200U_LDOPA       1'b1
+    31      R/W     LOP_POF_MEM_OFF_PPU_VPON_PCSM_LDO_ENB_DMYL_200U_LDOANA      1'b1
+ */
+typedef union _AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_4_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t LOP_POF_MEM_OFF_PPU_VPON_PCSM_ENB_AUTO_PS: 1;
+        uint32_t LOP_POF_MEM_OFF_PPU_VPON_PCSM_SEL_SYNC2: 1;
+        uint32_t LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_SYNC2: 1;
+        uint32_t LOP_POF_MEM_OFF_PPU_VPON_PCSM_SEL_VO3CMPHQ2_B: 1;
+        uint32_t LOP_POF_MEM_OFF_PPU_VPON_PCSM_SEL_VREF_VDDPA_HQ2: 5;
+        uint32_t LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_VO3CMPHQ2: 1;
+        uint32_t LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_VO3HQ2BETA: 1;
+        uint32_t LOP_POF_MEM_OFF_PPU_VPON_PCSM_PAD_AUTO_SW_PD_EN_RET: 1;
+        uint32_t LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_FAST_TRNAS: 1;
+        uint32_t LOP_POF_MEM_OFF_PPU_VPON_PCSM_LDO_PA_POS_EN_POS: 1;
+        uint32_t LOP_POF_MEM_OFF_PPU_VPON_PCSM_LDO_ANA_POS_EN_POS: 1;
+        uint32_t LOP_POF_MEM_OFF_PPU_VPON_PCSM_LDO_TUNE_LDOPA: 6;
+        uint32_t LOP_POF_MEM_OFF_PPU_VPON_PCSM_LDO_TUNE_LDOANA: 5;
+        uint32_t LOP_POF_MEM_OFF_PPU_VPON_PCSM_LDO_ENPC_LDOPA: 1;
+        uint32_t LOP_POF_MEM_OFF_PPU_VPON_PCSM_LDO_ENPC_LDOANA: 1;
+        uint32_t LOP_POF_MEM_OFF_PPU_VPON_PCSM_LDO_POW_LDOPA: 1;
+        uint32_t LOP_POF_MEM_OFF_PPU_VPON_PCSM_LDO_POW_LDOANA: 1;
+        uint32_t LOP_POF_MEM_OFF_PPU_VPON_PCSM_LDO_ENB_DMYL_200U_LDOPA: 1;
+        uint32_t LOP_POF_MEM_OFF_PPU_VPON_PCSM_LDO_ENB_DMYL_200U_LDOANA: 1;
+    };
+} AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_4_TYPE;
+
+/*0x4000_0a54 AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_4*/
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_4_LOP_POF_MEM_OFF_PPU_VPON_PCSM_ENB_AUTO_PS_Pos                                0U
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_4_LOP_POF_MEM_OFF_PPU_VPON_PCSM_ENB_AUTO_PS_Msk                                (0x1UL << AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_4_LOP_POF_MEM_OFF_PPU_VPON_PCSM_ENB_AUTO_PS_Pos)
+
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_4_LOP_POF_MEM_OFF_PPU_VPON_PCSM_SEL_SYNC2_Pos                                  1U
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_4_LOP_POF_MEM_OFF_PPU_VPON_PCSM_SEL_SYNC2_Msk                                  (0x1UL << AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_4_LOP_POF_MEM_OFF_PPU_VPON_PCSM_SEL_SYNC2_Pos)
+
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_4_LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_SYNC2_Pos                                   2U
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_4_LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_SYNC2_Msk                                   (0x1UL << AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_4_LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_SYNC2_Pos)
+
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_4_LOP_POF_MEM_OFF_PPU_VPON_PCSM_SEL_VO3CMPHQ2_B_Pos                            3U
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_4_LOP_POF_MEM_OFF_PPU_VPON_PCSM_SEL_VO3CMPHQ2_B_Msk                            (0x1UL << AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_4_LOP_POF_MEM_OFF_PPU_VPON_PCSM_SEL_VO3CMPHQ2_B_Pos)
+
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_4_LOP_POF_MEM_OFF_PPU_VPON_PCSM_SEL_VREF_VDDPA_HQ2_Pos                         4U
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_4_LOP_POF_MEM_OFF_PPU_VPON_PCSM_SEL_VREF_VDDPA_HQ2_Msk                         (0x1FUL << AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_4_LOP_POF_MEM_OFF_PPU_VPON_PCSM_SEL_VREF_VDDPA_HQ2_Pos)
+
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_4_LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_VO3CMPHQ2_Pos                               9U
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_4_LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_VO3CMPHQ2_Msk                               (0x1UL << AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_4_LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_VO3CMPHQ2_Pos)
+
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_4_LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_VO3HQ2BETA_Pos                              10U
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_4_LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_VO3HQ2BETA_Msk                              (0x1UL << AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_4_LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_VO3HQ2BETA_Pos)
+
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_4_LOP_POF_MEM_OFF_PPU_VPON_PCSM_PAD_AUTO_SW_PD_EN_RET_Pos                      11U
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_4_LOP_POF_MEM_OFF_PPU_VPON_PCSM_PAD_AUTO_SW_PD_EN_RET_Msk                      (0x1UL << AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_4_LOP_POF_MEM_OFF_PPU_VPON_PCSM_PAD_AUTO_SW_PD_EN_RET_Pos)
+
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_4_LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_FAST_TRNAS_Pos                              12U
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_4_LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_FAST_TRNAS_Msk                              (0x1UL << AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_4_LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_FAST_TRNAS_Pos)
+
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_4_LOP_POF_MEM_OFF_PPU_VPON_PCSM_LDO_PA_POS_EN_POS_Pos                          13U
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_4_LOP_POF_MEM_OFF_PPU_VPON_PCSM_LDO_PA_POS_EN_POS_Msk                          (0x1UL << AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_4_LOP_POF_MEM_OFF_PPU_VPON_PCSM_LDO_PA_POS_EN_POS_Pos)
+
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_4_LOP_POF_MEM_OFF_PPU_VPON_PCSM_LDO_ANA_POS_EN_POS_Pos                         14U
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_4_LOP_POF_MEM_OFF_PPU_VPON_PCSM_LDO_ANA_POS_EN_POS_Msk                         (0x1UL << AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_4_LOP_POF_MEM_OFF_PPU_VPON_PCSM_LDO_ANA_POS_EN_POS_Pos)
+
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_4_LOP_POF_MEM_OFF_PPU_VPON_PCSM_LDO_TUNE_LDOPA_Pos                             15U
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_4_LOP_POF_MEM_OFF_PPU_VPON_PCSM_LDO_TUNE_LDOPA_Msk                             (0x3FUL << AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_4_LOP_POF_MEM_OFF_PPU_VPON_PCSM_LDO_TUNE_LDOPA_Pos)
+
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_4_LOP_POF_MEM_OFF_PPU_VPON_PCSM_LDO_TUNE_LDOANA_Pos                            21U
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_4_LOP_POF_MEM_OFF_PPU_VPON_PCSM_LDO_TUNE_LDOANA_Msk                            (0x1FUL << AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_4_LOP_POF_MEM_OFF_PPU_VPON_PCSM_LDO_TUNE_LDOANA_Pos)
+
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_4_LOP_POF_MEM_OFF_PPU_VPON_PCSM_LDO_ENPC_LDOPA_Pos                             26U
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_4_LOP_POF_MEM_OFF_PPU_VPON_PCSM_LDO_ENPC_LDOPA_Msk                             (0x1UL << AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_4_LOP_POF_MEM_OFF_PPU_VPON_PCSM_LDO_ENPC_LDOPA_Pos)
+
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_4_LOP_POF_MEM_OFF_PPU_VPON_PCSM_LDO_ENPC_LDOANA_Pos                            27U
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_4_LOP_POF_MEM_OFF_PPU_VPON_PCSM_LDO_ENPC_LDOANA_Msk                            (0x1UL << AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_4_LOP_POF_MEM_OFF_PPU_VPON_PCSM_LDO_ENPC_LDOANA_Pos)
+
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_4_LOP_POF_MEM_OFF_PPU_VPON_PCSM_LDO_POW_LDOPA_Pos                              28U
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_4_LOP_POF_MEM_OFF_PPU_VPON_PCSM_LDO_POW_LDOPA_Msk                              (0x1UL << AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_4_LOP_POF_MEM_OFF_PPU_VPON_PCSM_LDO_POW_LDOPA_Pos)
+
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_4_LOP_POF_MEM_OFF_PPU_VPON_PCSM_LDO_POW_LDOANA_Pos                             29U
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_4_LOP_POF_MEM_OFF_PPU_VPON_PCSM_LDO_POW_LDOANA_Msk                             (0x1UL << AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_4_LOP_POF_MEM_OFF_PPU_VPON_PCSM_LDO_POW_LDOANA_Pos)
+
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_4_LOP_POF_MEM_OFF_PPU_VPON_PCSM_LDO_ENB_DMYL_200U_LDOPA_Pos                    30U
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_4_LOP_POF_MEM_OFF_PPU_VPON_PCSM_LDO_ENB_DMYL_200U_LDOPA_Msk                    (0x1UL << AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_4_LOP_POF_MEM_OFF_PPU_VPON_PCSM_LDO_ENB_DMYL_200U_LDOPA_Pos)
+
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_4_LOP_POF_MEM_OFF_PPU_VPON_PCSM_LDO_ENB_DMYL_200U_LDOANA_Pos                   31U
+#define AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_4_LOP_POF_MEM_OFF_PPU_VPON_PCSM_LDO_ENB_DMYL_200U_LDOANA_Msk                   (0x1UL << AON_LOP_POF_MEM_OFF_PPU_VPON_PCSM_4_LOP_POF_MEM_OFF_PPU_VPON_PCSM_LDO_ENB_DMYL_200U_LDOANA_Pos)
+
+/* 0xA58    0x4000_0a58
+    0       R/W     LOP_POF_FUNC_RET_PPU_VPON_PCSM_VDDIO_EN_DISCHG              1'b0
+    1       R/W     LOP_POF_FUNC_RET_PPU_VPON_PCSM_VDDIO_EN_PC2                 1'b1
+    2       R/W     LOP_POF_FUNC_RET_PPU_VPON_PCSM_VDDIO_EN_PC1                 1'b1
+    3       R/W     LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_SYNC                      1'b0
+    4       R/W     LOP_POF_FUNC_RET_PPU_VPON_PCSM_POW_VDIV_LQ_VDDCORE          1'b1
+    5       R/W     LOP_POF_FUNC_RET_PPU_VPON_PCSM_POW_VDIV_LQ_HV18             1'b0
+    6       R/W     LOP_POF_FUNC_RET_PPU_VPON_PCSM_POW_VDIV_HQ_VDDCORE          1'b0
+    7       R/W     LOP_POF_FUNC_RET_PPU_VPON_PCSM_POW_VDIV_HQ_VDDPA            1'b0
+    8       R/W     LOP_POF_FUNC_RET_PPU_VPON_PCSM_POW_VDIV_HQ_HV18             1'b0
+    9       R/W     LOP_POF_FUNC_RET_PPU_VPON_PCSM_POW_VDIV_HQ_HV25             1'b0
+    10      R/W     LOP_POF_FUNC_RET_PPU_VPON_PCSM_REG_ENHQ_REFCMP              1'b0
+    11      R/W     LOP_POF_FUNC_RET_PPU_VPON_PCSM_BYP_OPOR_LD                  1'b0
+    12      R/W     LOP_POF_FUNC_RET_PPU_VPON_PCSM_REG_ENLPM                    1'b1
+    13      R/W     LOP_POF_FUNC_RET_PPU_VPON_PCSM_REG_ENPCCM                   1'b0
+    14      R/W     LOP_POF_FUNC_RET_PPU_VPON_PCSM_ENCCM_OUT_VDDCORE            1'b0
+    15      R/W     LOP_POF_FUNC_RET_PPU_VPON_PCSM_ENCCM_OUT_VDDPA              1'b0
+    16      R/W     LOP_POF_FUNC_RET_PPU_VPON_PCSM_ENCCM_OUT_HV18               1'b0
+    17      R/W     LOP_POF_FUNC_RET_PPU_VPON_PCSM_ENCCM_OUT_HV25               1'b0
+    19:18   R/W     LOP_POF_FUNC_RET_PPU_VPON_PCSM_ZCDLY_SET                    2'b10
+    20      R/W     LOP_POF_FUNC_RET_PPU_VPON_PCSM_ENDLY_FOR_K                  1'b1
+    21      R/W     LOP_POF_FUNC_RET_PPU_VPON_PCSM_BUCK_BOOST_VDDPA_POS_RSTB    1'b0
+    22      R/W     LOP_POF_FUNC_RET_PPU_VPON_PCSM_BUCK_BOOST_HV18_POS_RSTB     1'b0
+    23      R/W     LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_DMYLOAD_VDDCORE           1'b0
+    24      R/W     LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_DMYLOAD_VDDPA             1'b0
+    25      R/W     LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_DMYLOAD_HV18              1'b0
+    26      R/W     LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_DMYLOAD_HV25              1'b0
+    27      R/W     LOP_POF_FUNC_RET_PPU_VPON_PCSM_POW_VDDPA_DET                1'b0
+    28      R/W     LOP_POF_FUNC_RET_PPU_VPON_PCSM_POW_HV18_DET                 1'b0
+    29      R/W     LOP_POF_FUNC_RET_PPU_VPON_PCSM_POW_VDDCORE_DET              1'b0
+    30      R/W     LOP_POF_FUNC_RET_PPU_VPON_PCSM_POW_VANA_DET                 1'b1
+    31      R/W     LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_BIAS_10UA                 1'b0
+ */
+typedef union _AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_1_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t LOP_POF_FUNC_RET_PPU_VPON_PCSM_VDDIO_EN_DISCHG: 1;
+        uint32_t LOP_POF_FUNC_RET_PPU_VPON_PCSM_VDDIO_EN_PC2: 1;
+        uint32_t LOP_POF_FUNC_RET_PPU_VPON_PCSM_VDDIO_EN_PC1: 1;
+        uint32_t LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_SYNC: 1;
+        uint32_t LOP_POF_FUNC_RET_PPU_VPON_PCSM_POW_VDIV_LQ_VDDCORE: 1;
+        uint32_t LOP_POF_FUNC_RET_PPU_VPON_PCSM_POW_VDIV_LQ_HV18: 1;
+        uint32_t LOP_POF_FUNC_RET_PPU_VPON_PCSM_POW_VDIV_HQ_VDDCORE: 1;
+        uint32_t LOP_POF_FUNC_RET_PPU_VPON_PCSM_POW_VDIV_HQ_VDDPA: 1;
+        uint32_t LOP_POF_FUNC_RET_PPU_VPON_PCSM_POW_VDIV_HQ_HV18: 1;
+        uint32_t LOP_POF_FUNC_RET_PPU_VPON_PCSM_POW_VDIV_HQ_HV25: 1;
+        uint32_t LOP_POF_FUNC_RET_PPU_VPON_PCSM_REG_ENHQ_REFCMP: 1;
+        uint32_t LOP_POF_FUNC_RET_PPU_VPON_PCSM_BYP_OPOR_LD: 1;
+        uint32_t LOP_POF_FUNC_RET_PPU_VPON_PCSM_REG_ENLPM: 1;
+        uint32_t LOP_POF_FUNC_RET_PPU_VPON_PCSM_REG_ENPCCM: 1;
+        uint32_t LOP_POF_FUNC_RET_PPU_VPON_PCSM_ENCCM_OUT_VDDCORE: 1;
+        uint32_t LOP_POF_FUNC_RET_PPU_VPON_PCSM_ENCCM_OUT_VDDPA: 1;
+        uint32_t LOP_POF_FUNC_RET_PPU_VPON_PCSM_ENCCM_OUT_HV18: 1;
+        uint32_t LOP_POF_FUNC_RET_PPU_VPON_PCSM_ENCCM_OUT_HV25: 1;
+        uint32_t LOP_POF_FUNC_RET_PPU_VPON_PCSM_ZCDLY_SET: 2;
+        uint32_t LOP_POF_FUNC_RET_PPU_VPON_PCSM_ENDLY_FOR_K: 1;
+        uint32_t LOP_POF_FUNC_RET_PPU_VPON_PCSM_BUCK_BOOST_VDDPA_POS_RSTB: 1;
+        uint32_t LOP_POF_FUNC_RET_PPU_VPON_PCSM_BUCK_BOOST_HV18_POS_RSTB: 1;
+        uint32_t LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_DMYLOAD_VDDCORE: 1;
+        uint32_t LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_DMYLOAD_VDDPA: 1;
+        uint32_t LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_DMYLOAD_HV18: 1;
+        uint32_t LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_DMYLOAD_HV25: 1;
+        uint32_t LOP_POF_FUNC_RET_PPU_VPON_PCSM_POW_VDDPA_DET: 1;
+        uint32_t LOP_POF_FUNC_RET_PPU_VPON_PCSM_POW_HV18_DET: 1;
+        uint32_t LOP_POF_FUNC_RET_PPU_VPON_PCSM_POW_VDDCORE_DET: 1;
+        uint32_t LOP_POF_FUNC_RET_PPU_VPON_PCSM_POW_VANA_DET: 1;
+        uint32_t LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_BIAS_10UA: 1;
+    };
+} AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_1_TYPE;
+
+/*0x4000_0a58 AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_1*/
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_1_LOP_POF_FUNC_RET_PPU_VPON_PCSM_VDDIO_EN_DISCHG_Pos                          0U
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_1_LOP_POF_FUNC_RET_PPU_VPON_PCSM_VDDIO_EN_DISCHG_Msk                          (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_1_LOP_POF_FUNC_RET_PPU_VPON_PCSM_VDDIO_EN_DISCHG_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_1_LOP_POF_FUNC_RET_PPU_VPON_PCSM_VDDIO_EN_PC2_Pos                             1U
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_1_LOP_POF_FUNC_RET_PPU_VPON_PCSM_VDDIO_EN_PC2_Msk                             (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_1_LOP_POF_FUNC_RET_PPU_VPON_PCSM_VDDIO_EN_PC2_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_1_LOP_POF_FUNC_RET_PPU_VPON_PCSM_VDDIO_EN_PC1_Pos                             2U
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_1_LOP_POF_FUNC_RET_PPU_VPON_PCSM_VDDIO_EN_PC1_Msk                             (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_1_LOP_POF_FUNC_RET_PPU_VPON_PCSM_VDDIO_EN_PC1_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_1_LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_SYNC_Pos                                  3U
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_1_LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_SYNC_Msk                                  (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_1_LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_SYNC_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_1_LOP_POF_FUNC_RET_PPU_VPON_PCSM_POW_VDIV_LQ_VDDCORE_Pos                      4U
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_1_LOP_POF_FUNC_RET_PPU_VPON_PCSM_POW_VDIV_LQ_VDDCORE_Msk                      (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_1_LOP_POF_FUNC_RET_PPU_VPON_PCSM_POW_VDIV_LQ_VDDCORE_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_1_LOP_POF_FUNC_RET_PPU_VPON_PCSM_POW_VDIV_LQ_HV18_Pos                         5U
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_1_LOP_POF_FUNC_RET_PPU_VPON_PCSM_POW_VDIV_LQ_HV18_Msk                         (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_1_LOP_POF_FUNC_RET_PPU_VPON_PCSM_POW_VDIV_LQ_HV18_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_1_LOP_POF_FUNC_RET_PPU_VPON_PCSM_POW_VDIV_HQ_VDDCORE_Pos                      6U
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_1_LOP_POF_FUNC_RET_PPU_VPON_PCSM_POW_VDIV_HQ_VDDCORE_Msk                      (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_1_LOP_POF_FUNC_RET_PPU_VPON_PCSM_POW_VDIV_HQ_VDDCORE_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_1_LOP_POF_FUNC_RET_PPU_VPON_PCSM_POW_VDIV_HQ_VDDPA_Pos                        7U
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_1_LOP_POF_FUNC_RET_PPU_VPON_PCSM_POW_VDIV_HQ_VDDPA_Msk                        (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_1_LOP_POF_FUNC_RET_PPU_VPON_PCSM_POW_VDIV_HQ_VDDPA_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_1_LOP_POF_FUNC_RET_PPU_VPON_PCSM_POW_VDIV_HQ_HV18_Pos                         8U
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_1_LOP_POF_FUNC_RET_PPU_VPON_PCSM_POW_VDIV_HQ_HV18_Msk                         (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_1_LOP_POF_FUNC_RET_PPU_VPON_PCSM_POW_VDIV_HQ_HV18_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_1_LOP_POF_FUNC_RET_PPU_VPON_PCSM_POW_VDIV_HQ_HV25_Pos                         9U
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_1_LOP_POF_FUNC_RET_PPU_VPON_PCSM_POW_VDIV_HQ_HV25_Msk                         (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_1_LOP_POF_FUNC_RET_PPU_VPON_PCSM_POW_VDIV_HQ_HV25_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_1_LOP_POF_FUNC_RET_PPU_VPON_PCSM_REG_ENHQ_REFCMP_Pos                          10U
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_1_LOP_POF_FUNC_RET_PPU_VPON_PCSM_REG_ENHQ_REFCMP_Msk                          (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_1_LOP_POF_FUNC_RET_PPU_VPON_PCSM_REG_ENHQ_REFCMP_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_1_LOP_POF_FUNC_RET_PPU_VPON_PCSM_BYP_OPOR_LD_Pos                              11U
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_1_LOP_POF_FUNC_RET_PPU_VPON_PCSM_BYP_OPOR_LD_Msk                              (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_1_LOP_POF_FUNC_RET_PPU_VPON_PCSM_BYP_OPOR_LD_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_1_LOP_POF_FUNC_RET_PPU_VPON_PCSM_REG_ENLPM_Pos                                12U
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_1_LOP_POF_FUNC_RET_PPU_VPON_PCSM_REG_ENLPM_Msk                                (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_1_LOP_POF_FUNC_RET_PPU_VPON_PCSM_REG_ENLPM_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_1_LOP_POF_FUNC_RET_PPU_VPON_PCSM_REG_ENPCCM_Pos                               13U
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_1_LOP_POF_FUNC_RET_PPU_VPON_PCSM_REG_ENPCCM_Msk                               (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_1_LOP_POF_FUNC_RET_PPU_VPON_PCSM_REG_ENPCCM_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_1_LOP_POF_FUNC_RET_PPU_VPON_PCSM_ENCCM_OUT_VDDCORE_Pos                        14U
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_1_LOP_POF_FUNC_RET_PPU_VPON_PCSM_ENCCM_OUT_VDDCORE_Msk                        (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_1_LOP_POF_FUNC_RET_PPU_VPON_PCSM_ENCCM_OUT_VDDCORE_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_1_LOP_POF_FUNC_RET_PPU_VPON_PCSM_ENCCM_OUT_VDDPA_Pos                          15U
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_1_LOP_POF_FUNC_RET_PPU_VPON_PCSM_ENCCM_OUT_VDDPA_Msk                          (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_1_LOP_POF_FUNC_RET_PPU_VPON_PCSM_ENCCM_OUT_VDDPA_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_1_LOP_POF_FUNC_RET_PPU_VPON_PCSM_ENCCM_OUT_HV18_Pos                           16U
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_1_LOP_POF_FUNC_RET_PPU_VPON_PCSM_ENCCM_OUT_HV18_Msk                           (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_1_LOP_POF_FUNC_RET_PPU_VPON_PCSM_ENCCM_OUT_HV18_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_1_LOP_POF_FUNC_RET_PPU_VPON_PCSM_ENCCM_OUT_HV25_Pos                           17U
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_1_LOP_POF_FUNC_RET_PPU_VPON_PCSM_ENCCM_OUT_HV25_Msk                           (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_1_LOP_POF_FUNC_RET_PPU_VPON_PCSM_ENCCM_OUT_HV25_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_1_LOP_POF_FUNC_RET_PPU_VPON_PCSM_ZCDLY_SET_Pos                                18U
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_1_LOP_POF_FUNC_RET_PPU_VPON_PCSM_ZCDLY_SET_Msk                                (0x3UL << AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_1_LOP_POF_FUNC_RET_PPU_VPON_PCSM_ZCDLY_SET_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_1_LOP_POF_FUNC_RET_PPU_VPON_PCSM_ENDLY_FOR_K_Pos                              20U
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_1_LOP_POF_FUNC_RET_PPU_VPON_PCSM_ENDLY_FOR_K_Msk                              (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_1_LOP_POF_FUNC_RET_PPU_VPON_PCSM_ENDLY_FOR_K_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_1_LOP_POF_FUNC_RET_PPU_VPON_PCSM_BUCK_BOOST_VDDPA_POS_RSTB_Pos                21U
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_1_LOP_POF_FUNC_RET_PPU_VPON_PCSM_BUCK_BOOST_VDDPA_POS_RSTB_Msk                (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_1_LOP_POF_FUNC_RET_PPU_VPON_PCSM_BUCK_BOOST_VDDPA_POS_RSTB_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_1_LOP_POF_FUNC_RET_PPU_VPON_PCSM_BUCK_BOOST_HV18_POS_RSTB_Pos                 22U
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_1_LOP_POF_FUNC_RET_PPU_VPON_PCSM_BUCK_BOOST_HV18_POS_RSTB_Msk                 (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_1_LOP_POF_FUNC_RET_PPU_VPON_PCSM_BUCK_BOOST_HV18_POS_RSTB_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_1_LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_DMYLOAD_VDDCORE_Pos                       23U
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_1_LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_DMYLOAD_VDDCORE_Msk                       (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_1_LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_DMYLOAD_VDDCORE_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_1_LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_DMYLOAD_VDDPA_Pos                         24U
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_1_LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_DMYLOAD_VDDPA_Msk                         (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_1_LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_DMYLOAD_VDDPA_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_1_LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_DMYLOAD_HV18_Pos                          25U
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_1_LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_DMYLOAD_HV18_Msk                          (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_1_LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_DMYLOAD_HV18_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_1_LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_DMYLOAD_HV25_Pos                          26U
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_1_LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_DMYLOAD_HV25_Msk                          (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_1_LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_DMYLOAD_HV25_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_1_LOP_POF_FUNC_RET_PPU_VPON_PCSM_POW_VDDPA_DET_Pos                            27U
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_1_LOP_POF_FUNC_RET_PPU_VPON_PCSM_POW_VDDPA_DET_Msk                            (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_1_LOP_POF_FUNC_RET_PPU_VPON_PCSM_POW_VDDPA_DET_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_1_LOP_POF_FUNC_RET_PPU_VPON_PCSM_POW_HV18_DET_Pos                             28U
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_1_LOP_POF_FUNC_RET_PPU_VPON_PCSM_POW_HV18_DET_Msk                             (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_1_LOP_POF_FUNC_RET_PPU_VPON_PCSM_POW_HV18_DET_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_1_LOP_POF_FUNC_RET_PPU_VPON_PCSM_POW_VDDCORE_DET_Pos                          29U
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_1_LOP_POF_FUNC_RET_PPU_VPON_PCSM_POW_VDDCORE_DET_Msk                          (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_1_LOP_POF_FUNC_RET_PPU_VPON_PCSM_POW_VDDCORE_DET_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_1_LOP_POF_FUNC_RET_PPU_VPON_PCSM_POW_VANA_DET_Pos                             30U
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_1_LOP_POF_FUNC_RET_PPU_VPON_PCSM_POW_VANA_DET_Msk                             (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_1_LOP_POF_FUNC_RET_PPU_VPON_PCSM_POW_VANA_DET_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_1_LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_BIAS_10UA_Pos                             31U
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_1_LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_BIAS_10UA_Msk                             (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_1_LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_BIAS_10UA_Pos)
+
+/* 0xA5C    0x4000_0a5c
+    0       R/W     LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_MCM_FLASH_PC2             1'b1
+    1       R/W     LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_MCM_FLASH_PC1             1'b1
+    2       R/W     LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_DISCHG_MCM_FLASH          1'b0
+    3       R/W     LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_BIAS_1UA                  1'b0
+    4       R/W     LOP_POF_FUNC_RET_PPU_VPON_PCSM_IO_RSTB33_EN                 1'b1
+    5       R/W     LOP_POF_FUNC_RET_PPU_VPON_PCSM_IO_SHDN33_EN                 1'b1
+    13:6    R/W     LOP_POF_FUNC_RET_PPU_VPON_PCSM_TUNE_VDDPA                   8'b00100010
+    19:14   R/W     LOP_POF_FUNC_RET_PPU_VPON_PCSM_TUNE_HV18                    6'b100000
+    24:20   R/W     LOP_POF_FUNC_RET_PPU_VPON_PCSM_SEL_VREF_HV25_HQ             5'b01111
+    25      R/W     LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_CMP_LQ_VDDCORE            1'b1
+    26      R/W     LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_CMP_LQ_HV18               1'b0
+    27      R/W     LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_CMP_LQ_HV25               1'b1
+    28      R/W     LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_CMP_HQ_VDDCORE            1'b0
+    29      R/W     LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_CMP_HQ_VDDPA              1'b0
+    30      R/W     LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_CMP_HQ_HV18               1'b0
+    31      R/W     LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_CMP_HQ_HV25               1'b0
+ */
+typedef union _AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_2_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_MCM_FLASH_PC2: 1;
+        uint32_t LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_MCM_FLASH_PC1: 1;
+        uint32_t LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_DISCHG_MCM_FLASH: 1;
+        uint32_t LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_BIAS_1UA: 1;
+        uint32_t LOP_POF_FUNC_RET_PPU_VPON_PCSM_IO_RSTB33_EN: 1;
+        uint32_t LOP_POF_FUNC_RET_PPU_VPON_PCSM_IO_SHDN33_EN: 1;
+        uint32_t LOP_POF_FUNC_RET_PPU_VPON_PCSM_TUNE_VDDPA: 8;
+        uint32_t LOP_POF_FUNC_RET_PPU_VPON_PCSM_TUNE_HV18: 6;
+        uint32_t LOP_POF_FUNC_RET_PPU_VPON_PCSM_SEL_VREF_HV25_HQ: 5;
+        uint32_t LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_CMP_LQ_VDDCORE: 1;
+        uint32_t LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_CMP_LQ_HV18: 1;
+        uint32_t LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_CMP_LQ_HV25: 1;
+        uint32_t LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_CMP_HQ_VDDCORE: 1;
+        uint32_t LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_CMP_HQ_VDDPA: 1;
+        uint32_t LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_CMP_HQ_HV18: 1;
+        uint32_t LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_CMP_HQ_HV25: 1;
+    };
+} AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_2_TYPE;
+
+/*0x4000_0a5c AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_2*/
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_2_LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_MCM_FLASH_PC2_Pos                         0U
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_2_LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_MCM_FLASH_PC2_Msk                         (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_2_LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_MCM_FLASH_PC2_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_2_LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_MCM_FLASH_PC1_Pos                         1U
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_2_LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_MCM_FLASH_PC1_Msk                         (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_2_LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_MCM_FLASH_PC1_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_2_LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_DISCHG_MCM_FLASH_Pos                      2U
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_2_LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_DISCHG_MCM_FLASH_Msk                      (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_2_LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_DISCHG_MCM_FLASH_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_2_LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_BIAS_1UA_Pos                              3U
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_2_LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_BIAS_1UA_Msk                              (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_2_LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_BIAS_1UA_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_2_LOP_POF_FUNC_RET_PPU_VPON_PCSM_IO_RSTB33_EN_Pos                             4U
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_2_LOP_POF_FUNC_RET_PPU_VPON_PCSM_IO_RSTB33_EN_Msk                             (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_2_LOP_POF_FUNC_RET_PPU_VPON_PCSM_IO_RSTB33_EN_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_2_LOP_POF_FUNC_RET_PPU_VPON_PCSM_IO_SHDN33_EN_Pos                             5U
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_2_LOP_POF_FUNC_RET_PPU_VPON_PCSM_IO_SHDN33_EN_Msk                             (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_2_LOP_POF_FUNC_RET_PPU_VPON_PCSM_IO_SHDN33_EN_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_2_LOP_POF_FUNC_RET_PPU_VPON_PCSM_TUNE_VDDPA_Pos                               6U
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_2_LOP_POF_FUNC_RET_PPU_VPON_PCSM_TUNE_VDDPA_Msk                               (0xFFUL << AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_2_LOP_POF_FUNC_RET_PPU_VPON_PCSM_TUNE_VDDPA_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_2_LOP_POF_FUNC_RET_PPU_VPON_PCSM_TUNE_HV18_Pos                                14U
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_2_LOP_POF_FUNC_RET_PPU_VPON_PCSM_TUNE_HV18_Msk                                (0x3FUL << AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_2_LOP_POF_FUNC_RET_PPU_VPON_PCSM_TUNE_HV18_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_2_LOP_POF_FUNC_RET_PPU_VPON_PCSM_SEL_VREF_HV25_HQ_Pos                         20U
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_2_LOP_POF_FUNC_RET_PPU_VPON_PCSM_SEL_VREF_HV25_HQ_Msk                         (0x1FUL << AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_2_LOP_POF_FUNC_RET_PPU_VPON_PCSM_SEL_VREF_HV25_HQ_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_2_LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_CMP_LQ_VDDCORE_Pos                        25U
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_2_LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_CMP_LQ_VDDCORE_Msk                        (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_2_LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_CMP_LQ_VDDCORE_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_2_LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_CMP_LQ_HV18_Pos                           26U
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_2_LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_CMP_LQ_HV18_Msk                           (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_2_LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_CMP_LQ_HV18_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_2_LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_CMP_LQ_HV25_Pos                           27U
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_2_LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_CMP_LQ_HV25_Msk                           (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_2_LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_CMP_LQ_HV25_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_2_LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_CMP_HQ_VDDCORE_Pos                        28U
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_2_LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_CMP_HQ_VDDCORE_Msk                        (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_2_LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_CMP_HQ_VDDCORE_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_2_LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_CMP_HQ_VDDPA_Pos                          29U
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_2_LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_CMP_HQ_VDDPA_Msk                          (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_2_LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_CMP_HQ_VDDPA_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_2_LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_CMP_HQ_HV18_Pos                           30U
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_2_LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_CMP_HQ_HV18_Msk                           (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_2_LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_CMP_HQ_HV18_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_2_LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_CMP_HQ_HV25_Pos                           31U
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_2_LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_CMP_HQ_HV25_Msk                           (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_2_LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_CMP_HQ_HV25_Pos)
+
+/* 0xA60    0x4000_0a60
+    1:0     R/W     RESERVED                                                    2'h0
+    2       R/W     LOP_POF_FUNC_RET_PPU_VPON_PCSM_LDO_PA_POS_RSTB              1'b0
+    3       R/W     LOP_POF_FUNC_RET_PPU_VPON_PCSM_LDO_ANA_POS_RSTB             1'b1
+    4       R/W     LOP_POF_FUNC_RET_PPU_VPON_PCSM_LDO_POW_BIAS_LDOPA           1'b0
+    5       R/W     LOP_POF_FUNC_RET_PPU_VPON_PCSM_LDO_POW_BIAS_LDOANA          1'b1
+    6       R/W     LOP_POF_FUNC_RET_PPU_VPON_PCSM_BUCK_BOOST_VDDPA_POS_EN_POS  1'b0
+    7       R/W     LOP_POF_FUNC_RET_PPU_VPON_PCSM_BUCK_BOOST_HV18_POS_EN_POS   1'b0
+    12:8    R/W     LOP_POF_FUNC_RET_PPU_VPON_PCSM_SEL_VREF_VDDCORE_LQ          5'b01110
+    18:13   R/W     LOP_POF_FUNC_RET_PPU_VPON_PCSM_TUNE_LPM_HV18                6'b100000
+    23:19   R/W     LOP_POF_FUNC_RET_PPU_VPON_PCSM_SEL_VREF_HV25_LQ             5'b01111
+    31:24   R/W     LOP_POF_FUNC_RET_PPU_VPON_PCSM_TUNE_VDDCORE                 8'b01100010
+ */
+typedef union _AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_3_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED: 2;
+        uint32_t LOP_POF_FUNC_RET_PPU_VPON_PCSM_LDO_PA_POS_RSTB: 1;
+        uint32_t LOP_POF_FUNC_RET_PPU_VPON_PCSM_LDO_ANA_POS_RSTB: 1;
+        uint32_t LOP_POF_FUNC_RET_PPU_VPON_PCSM_LDO_POW_BIAS_LDOPA: 1;
+        uint32_t LOP_POF_FUNC_RET_PPU_VPON_PCSM_LDO_POW_BIAS_LDOANA: 1;
+        uint32_t LOP_POF_FUNC_RET_PPU_VPON_PCSM_BUCK_BOOST_VDDPA_POS_EN_POS: 1;
+        uint32_t LOP_POF_FUNC_RET_PPU_VPON_PCSM_BUCK_BOOST_HV18_POS_EN_POS: 1;
+        uint32_t LOP_POF_FUNC_RET_PPU_VPON_PCSM_SEL_VREF_VDDCORE_LQ: 5;
+        uint32_t LOP_POF_FUNC_RET_PPU_VPON_PCSM_TUNE_LPM_HV18: 6;
+        uint32_t LOP_POF_FUNC_RET_PPU_VPON_PCSM_SEL_VREF_HV25_LQ: 5;
+        uint32_t LOP_POF_FUNC_RET_PPU_VPON_PCSM_TUNE_VDDCORE: 8;
+    };
+} AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_3_TYPE;
+
+/*0x4000_0a60 AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_3*/
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_3_RESERVED_Pos                                                                0U
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_3_RESERVED_Msk                                                                (0x3UL << AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_3_RESERVED_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_3_LOP_POF_FUNC_RET_PPU_VPON_PCSM_LDO_PA_POS_RSTB_Pos                          2U
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_3_LOP_POF_FUNC_RET_PPU_VPON_PCSM_LDO_PA_POS_RSTB_Msk                          (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_3_LOP_POF_FUNC_RET_PPU_VPON_PCSM_LDO_PA_POS_RSTB_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_3_LOP_POF_FUNC_RET_PPU_VPON_PCSM_LDO_ANA_POS_RSTB_Pos                         3U
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_3_LOP_POF_FUNC_RET_PPU_VPON_PCSM_LDO_ANA_POS_RSTB_Msk                         (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_3_LOP_POF_FUNC_RET_PPU_VPON_PCSM_LDO_ANA_POS_RSTB_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_3_LOP_POF_FUNC_RET_PPU_VPON_PCSM_LDO_POW_BIAS_LDOPA_Pos                       4U
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_3_LOP_POF_FUNC_RET_PPU_VPON_PCSM_LDO_POW_BIAS_LDOPA_Msk                       (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_3_LOP_POF_FUNC_RET_PPU_VPON_PCSM_LDO_POW_BIAS_LDOPA_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_3_LOP_POF_FUNC_RET_PPU_VPON_PCSM_LDO_POW_BIAS_LDOANA_Pos                      5U
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_3_LOP_POF_FUNC_RET_PPU_VPON_PCSM_LDO_POW_BIAS_LDOANA_Msk                      (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_3_LOP_POF_FUNC_RET_PPU_VPON_PCSM_LDO_POW_BIAS_LDOANA_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_3_LOP_POF_FUNC_RET_PPU_VPON_PCSM_BUCK_BOOST_VDDPA_POS_EN_POS_Pos              6U
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_3_LOP_POF_FUNC_RET_PPU_VPON_PCSM_BUCK_BOOST_VDDPA_POS_EN_POS_Msk              (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_3_LOP_POF_FUNC_RET_PPU_VPON_PCSM_BUCK_BOOST_VDDPA_POS_EN_POS_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_3_LOP_POF_FUNC_RET_PPU_VPON_PCSM_BUCK_BOOST_HV18_POS_EN_POS_Pos               7U
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_3_LOP_POF_FUNC_RET_PPU_VPON_PCSM_BUCK_BOOST_HV18_POS_EN_POS_Msk               (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_3_LOP_POF_FUNC_RET_PPU_VPON_PCSM_BUCK_BOOST_HV18_POS_EN_POS_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_3_LOP_POF_FUNC_RET_PPU_VPON_PCSM_SEL_VREF_VDDCORE_LQ_Pos                      8U
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_3_LOP_POF_FUNC_RET_PPU_VPON_PCSM_SEL_VREF_VDDCORE_LQ_Msk                      (0x1FUL << AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_3_LOP_POF_FUNC_RET_PPU_VPON_PCSM_SEL_VREF_VDDCORE_LQ_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_3_LOP_POF_FUNC_RET_PPU_VPON_PCSM_TUNE_LPM_HV18_Pos                            13U
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_3_LOP_POF_FUNC_RET_PPU_VPON_PCSM_TUNE_LPM_HV18_Msk                            (0x3FUL << AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_3_LOP_POF_FUNC_RET_PPU_VPON_PCSM_TUNE_LPM_HV18_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_3_LOP_POF_FUNC_RET_PPU_VPON_PCSM_SEL_VREF_HV25_LQ_Pos                         19U
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_3_LOP_POF_FUNC_RET_PPU_VPON_PCSM_SEL_VREF_HV25_LQ_Msk                         (0x1FUL << AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_3_LOP_POF_FUNC_RET_PPU_VPON_PCSM_SEL_VREF_HV25_LQ_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_3_LOP_POF_FUNC_RET_PPU_VPON_PCSM_TUNE_VDDCORE_Pos                             24U
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_3_LOP_POF_FUNC_RET_PPU_VPON_PCSM_TUNE_VDDCORE_Msk                             (0xFFUL << AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_3_LOP_POF_FUNC_RET_PPU_VPON_PCSM_TUNE_VDDCORE_Pos)
+
+/* 0xA64    0x4000_0a64
+    0       R/W     LOP_POF_FUNC_RET_PPU_VPON_PCSM_ENB_AUTO_PS                  1'b1
+    1       R/W     LOP_POF_FUNC_RET_PPU_VPON_PCSM_SEL_SYNC2                    1'b1
+    2       R/W     LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_SYNC2                     1'b0
+    3       R/W     LOP_POF_FUNC_RET_PPU_VPON_PCSM_SEL_VO3CMPHQ2_B              1'b1
+    8:4     R/W     LOP_POF_FUNC_RET_PPU_VPON_PCSM_SEL_VREF_VDDPA_HQ2           5'b11000
+    9       R/W     LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_VO3CMPHQ2                 1'b0
+    10      R/W     LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_VO3HQ2BETA                1'b1
+    11      R/W     LOP_POF_FUNC_RET_PPU_VPON_PCSM_PAD_AUTO_SW_PD_EN_RET        1'b0
+    12      R/W     LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_FAST_TRNAS                1'b1
+    13      R/W     LOP_POF_FUNC_RET_PPU_VPON_PCSM_LDO_PA_POS_EN_POS            1'b0
+    14      R/W     LOP_POF_FUNC_RET_PPU_VPON_PCSM_LDO_ANA_POS_EN_POS           1'b1
+    20:15   R/W     LOP_POF_FUNC_RET_PPU_VPON_PCSM_LDO_TUNE_LDOPA               6'b010000
+    25:21   R/W     LOP_POF_FUNC_RET_PPU_VPON_PCSM_LDO_TUNE_LDOANA              5'b01111
+    26      R/W     LOP_POF_FUNC_RET_PPU_VPON_PCSM_LDO_ENPC_LDOPA               1'b0
+    27      R/W     LOP_POF_FUNC_RET_PPU_VPON_PCSM_LDO_ENPC_LDOANA              1'b1
+    28      R/W     LOP_POF_FUNC_RET_PPU_VPON_PCSM_LDO_POW_LDOPA                1'b0
+    29      R/W     LOP_POF_FUNC_RET_PPU_VPON_PCSM_LDO_POW_LDOANA               1'b1
+    30      R/W     LOP_POF_FUNC_RET_PPU_VPON_PCSM_LDO_ENB_DMYL_200U_LDOPA      1'b1
+    31      R/W     LOP_POF_FUNC_RET_PPU_VPON_PCSM_LDO_ENB_DMYL_200U_LDOANA     1'b1
+ */
+typedef union _AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_4_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t LOP_POF_FUNC_RET_PPU_VPON_PCSM_ENB_AUTO_PS: 1;
+        uint32_t LOP_POF_FUNC_RET_PPU_VPON_PCSM_SEL_SYNC2: 1;
+        uint32_t LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_SYNC2: 1;
+        uint32_t LOP_POF_FUNC_RET_PPU_VPON_PCSM_SEL_VO3CMPHQ2_B: 1;
+        uint32_t LOP_POF_FUNC_RET_PPU_VPON_PCSM_SEL_VREF_VDDPA_HQ2: 5;
+        uint32_t LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_VO3CMPHQ2: 1;
+        uint32_t LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_VO3HQ2BETA: 1;
+        uint32_t LOP_POF_FUNC_RET_PPU_VPON_PCSM_PAD_AUTO_SW_PD_EN_RET: 1;
+        uint32_t LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_FAST_TRNAS: 1;
+        uint32_t LOP_POF_FUNC_RET_PPU_VPON_PCSM_LDO_PA_POS_EN_POS: 1;
+        uint32_t LOP_POF_FUNC_RET_PPU_VPON_PCSM_LDO_ANA_POS_EN_POS: 1;
+        uint32_t LOP_POF_FUNC_RET_PPU_VPON_PCSM_LDO_TUNE_LDOPA: 6;
+        uint32_t LOP_POF_FUNC_RET_PPU_VPON_PCSM_LDO_TUNE_LDOANA: 5;
+        uint32_t LOP_POF_FUNC_RET_PPU_VPON_PCSM_LDO_ENPC_LDOPA: 1;
+        uint32_t LOP_POF_FUNC_RET_PPU_VPON_PCSM_LDO_ENPC_LDOANA: 1;
+        uint32_t LOP_POF_FUNC_RET_PPU_VPON_PCSM_LDO_POW_LDOPA: 1;
+        uint32_t LOP_POF_FUNC_RET_PPU_VPON_PCSM_LDO_POW_LDOANA: 1;
+        uint32_t LOP_POF_FUNC_RET_PPU_VPON_PCSM_LDO_ENB_DMYL_200U_LDOPA: 1;
+        uint32_t LOP_POF_FUNC_RET_PPU_VPON_PCSM_LDO_ENB_DMYL_200U_LDOANA: 1;
+    };
+} AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_4_TYPE;
+
+/*0x4000_0a64 AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_4*/
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_4_LOP_POF_FUNC_RET_PPU_VPON_PCSM_ENB_AUTO_PS_Pos                              0U
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_4_LOP_POF_FUNC_RET_PPU_VPON_PCSM_ENB_AUTO_PS_Msk                              (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_4_LOP_POF_FUNC_RET_PPU_VPON_PCSM_ENB_AUTO_PS_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_4_LOP_POF_FUNC_RET_PPU_VPON_PCSM_SEL_SYNC2_Pos                                1U
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_4_LOP_POF_FUNC_RET_PPU_VPON_PCSM_SEL_SYNC2_Msk                                (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_4_LOP_POF_FUNC_RET_PPU_VPON_PCSM_SEL_SYNC2_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_4_LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_SYNC2_Pos                                 2U
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_4_LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_SYNC2_Msk                                 (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_4_LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_SYNC2_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_4_LOP_POF_FUNC_RET_PPU_VPON_PCSM_SEL_VO3CMPHQ2_B_Pos                          3U
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_4_LOP_POF_FUNC_RET_PPU_VPON_PCSM_SEL_VO3CMPHQ2_B_Msk                          (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_4_LOP_POF_FUNC_RET_PPU_VPON_PCSM_SEL_VO3CMPHQ2_B_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_4_LOP_POF_FUNC_RET_PPU_VPON_PCSM_SEL_VREF_VDDPA_HQ2_Pos                       4U
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_4_LOP_POF_FUNC_RET_PPU_VPON_PCSM_SEL_VREF_VDDPA_HQ2_Msk                       (0x1FUL << AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_4_LOP_POF_FUNC_RET_PPU_VPON_PCSM_SEL_VREF_VDDPA_HQ2_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_4_LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_VO3CMPHQ2_Pos                             9U
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_4_LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_VO3CMPHQ2_Msk                             (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_4_LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_VO3CMPHQ2_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_4_LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_VO3HQ2BETA_Pos                            10U
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_4_LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_VO3HQ2BETA_Msk                            (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_4_LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_VO3HQ2BETA_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_4_LOP_POF_FUNC_RET_PPU_VPON_PCSM_PAD_AUTO_SW_PD_EN_RET_Pos                    11U
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_4_LOP_POF_FUNC_RET_PPU_VPON_PCSM_PAD_AUTO_SW_PD_EN_RET_Msk                    (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_4_LOP_POF_FUNC_RET_PPU_VPON_PCSM_PAD_AUTO_SW_PD_EN_RET_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_4_LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_FAST_TRNAS_Pos                            12U
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_4_LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_FAST_TRNAS_Msk                            (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_4_LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_FAST_TRNAS_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_4_LOP_POF_FUNC_RET_PPU_VPON_PCSM_LDO_PA_POS_EN_POS_Pos                        13U
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_4_LOP_POF_FUNC_RET_PPU_VPON_PCSM_LDO_PA_POS_EN_POS_Msk                        (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_4_LOP_POF_FUNC_RET_PPU_VPON_PCSM_LDO_PA_POS_EN_POS_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_4_LOP_POF_FUNC_RET_PPU_VPON_PCSM_LDO_ANA_POS_EN_POS_Pos                       14U
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_4_LOP_POF_FUNC_RET_PPU_VPON_PCSM_LDO_ANA_POS_EN_POS_Msk                       (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_4_LOP_POF_FUNC_RET_PPU_VPON_PCSM_LDO_ANA_POS_EN_POS_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_4_LOP_POF_FUNC_RET_PPU_VPON_PCSM_LDO_TUNE_LDOPA_Pos                           15U
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_4_LOP_POF_FUNC_RET_PPU_VPON_PCSM_LDO_TUNE_LDOPA_Msk                           (0x3FUL << AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_4_LOP_POF_FUNC_RET_PPU_VPON_PCSM_LDO_TUNE_LDOPA_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_4_LOP_POF_FUNC_RET_PPU_VPON_PCSM_LDO_TUNE_LDOANA_Pos                          21U
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_4_LOP_POF_FUNC_RET_PPU_VPON_PCSM_LDO_TUNE_LDOANA_Msk                          (0x1FUL << AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_4_LOP_POF_FUNC_RET_PPU_VPON_PCSM_LDO_TUNE_LDOANA_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_4_LOP_POF_FUNC_RET_PPU_VPON_PCSM_LDO_ENPC_LDOPA_Pos                           26U
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_4_LOP_POF_FUNC_RET_PPU_VPON_PCSM_LDO_ENPC_LDOPA_Msk                           (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_4_LOP_POF_FUNC_RET_PPU_VPON_PCSM_LDO_ENPC_LDOPA_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_4_LOP_POF_FUNC_RET_PPU_VPON_PCSM_LDO_ENPC_LDOANA_Pos                          27U
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_4_LOP_POF_FUNC_RET_PPU_VPON_PCSM_LDO_ENPC_LDOANA_Msk                          (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_4_LOP_POF_FUNC_RET_PPU_VPON_PCSM_LDO_ENPC_LDOANA_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_4_LOP_POF_FUNC_RET_PPU_VPON_PCSM_LDO_POW_LDOPA_Pos                            28U
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_4_LOP_POF_FUNC_RET_PPU_VPON_PCSM_LDO_POW_LDOPA_Msk                            (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_4_LOP_POF_FUNC_RET_PPU_VPON_PCSM_LDO_POW_LDOPA_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_4_LOP_POF_FUNC_RET_PPU_VPON_PCSM_LDO_POW_LDOANA_Pos                           29U
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_4_LOP_POF_FUNC_RET_PPU_VPON_PCSM_LDO_POW_LDOANA_Msk                           (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_4_LOP_POF_FUNC_RET_PPU_VPON_PCSM_LDO_POW_LDOANA_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_4_LOP_POF_FUNC_RET_PPU_VPON_PCSM_LDO_ENB_DMYL_200U_LDOPA_Pos                  30U
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_4_LOP_POF_FUNC_RET_PPU_VPON_PCSM_LDO_ENB_DMYL_200U_LDOPA_Msk                  (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_4_LOP_POF_FUNC_RET_PPU_VPON_PCSM_LDO_ENB_DMYL_200U_LDOPA_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_4_LOP_POF_FUNC_RET_PPU_VPON_PCSM_LDO_ENB_DMYL_200U_LDOANA_Pos                 31U
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_4_LOP_POF_FUNC_RET_PPU_VPON_PCSM_LDO_ENB_DMYL_200U_LDOANA_Msk                 (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_4_LOP_POF_FUNC_RET_PPU_VPON_PCSM_LDO_ENB_DMYL_200U_LDOANA_Pos)
+
+/* 0xA68    0x4000_0a68
+    2:0     R/W     RESERVED_1                                                  3'b000
+    3       R/W     LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_CMP_LQ_VDDANA             1'b1
+    4       R/W     LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_CMP_HQ_VDDANA             1'b0
+    9:5     R/W     LOP_POF_FUNC_RET_PPU_VPON_PCSM_SEL_VREF_VDDANA_LQ           5'b10011
+    17:10   R/W     LOP_POF_FUNC_RET_PPU_VPON_PCSM_TUNE_VDDANA                  8'b01111010
+    18      R/W     LOP_POF_FUNC_RET_PPU_VPON_PCSM_POW_VDIV_LQ_VDDANA           1'b1
+    19      R/W     LOP_POF_FUNC_RET_PPU_VPON_PCSM_POW_VDIV_HQ_VDDANA           1'b0
+    20      R/W     LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_DMYLOAD_VDDANA            1'b0
+    21      R/W     LOP_POF_FUNC_RET_PPU_VPON_PCSM_POW_VDDANA_DET               1'b1
+    22      R/W     LOP_POF_FUNC_RET_PPU_VPON_PCSM_ENCCM_OUT_VDDANA             1'b1
+    23      R/W     RESERVED                                                    1'b0
+    27:24   R/W     LOP_POF_OFF_PPU_VPON_PCSM_2_DELAY                           4'b0000
+    31:28   R/W     LOP_POF_OFF_PPU_VPON_PCSM_INACTIVE_DELAY                    4'b0000
+ */
+typedef union _AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_5_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED_1: 3;
+        uint32_t LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_CMP_LQ_VDDANA: 1;
+        uint32_t LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_CMP_HQ_VDDANA: 1;
+        uint32_t LOP_POF_FUNC_RET_PPU_VPON_PCSM_SEL_VREF_VDDANA_LQ: 5;
+        uint32_t LOP_POF_FUNC_RET_PPU_VPON_PCSM_TUNE_VDDANA: 8;
+        uint32_t LOP_POF_FUNC_RET_PPU_VPON_PCSM_POW_VDIV_LQ_VDDANA: 1;
+        uint32_t LOP_POF_FUNC_RET_PPU_VPON_PCSM_POW_VDIV_HQ_VDDANA: 1;
+        uint32_t LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_DMYLOAD_VDDANA: 1;
+        uint32_t LOP_POF_FUNC_RET_PPU_VPON_PCSM_POW_VDDANA_DET: 1;
+        uint32_t LOP_POF_FUNC_RET_PPU_VPON_PCSM_ENCCM_OUT_VDDANA: 1;
+        uint32_t RESERVED: 1;
+        uint32_t LOP_POF_OFF_PPU_VPON_PCSM_2_DELAY: 4;
+        uint32_t LOP_POF_OFF_PPU_VPON_PCSM_INACTIVE_DELAY: 4;
+    };
+} AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_5_TYPE;
+
+/*0x4000_0a68 AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_5*/
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_5_RESERVED_1_Pos                                                              0U
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_5_RESERVED_1_Msk                                                              (0x7UL << AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_5_RESERVED_1_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_5_LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_CMP_LQ_VDDANA_Pos                         3U
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_5_LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_CMP_LQ_VDDANA_Msk                         (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_5_LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_CMP_LQ_VDDANA_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_5_LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_CMP_HQ_VDDANA_Pos                         4U
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_5_LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_CMP_HQ_VDDANA_Msk                         (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_5_LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_CMP_HQ_VDDANA_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_5_LOP_POF_FUNC_RET_PPU_VPON_PCSM_SEL_VREF_VDDANA_LQ_Pos                       5U
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_5_LOP_POF_FUNC_RET_PPU_VPON_PCSM_SEL_VREF_VDDANA_LQ_Msk                       (0x1FUL << AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_5_LOP_POF_FUNC_RET_PPU_VPON_PCSM_SEL_VREF_VDDANA_LQ_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_5_LOP_POF_FUNC_RET_PPU_VPON_PCSM_TUNE_VDDANA_Pos                              10U
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_5_LOP_POF_FUNC_RET_PPU_VPON_PCSM_TUNE_VDDANA_Msk                              (0xFFUL << AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_5_LOP_POF_FUNC_RET_PPU_VPON_PCSM_TUNE_VDDANA_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_5_LOP_POF_FUNC_RET_PPU_VPON_PCSM_POW_VDIV_LQ_VDDANA_Pos                       18U
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_5_LOP_POF_FUNC_RET_PPU_VPON_PCSM_POW_VDIV_LQ_VDDANA_Msk                       (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_5_LOP_POF_FUNC_RET_PPU_VPON_PCSM_POW_VDIV_LQ_VDDANA_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_5_LOP_POF_FUNC_RET_PPU_VPON_PCSM_POW_VDIV_HQ_VDDANA_Pos                       19U
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_5_LOP_POF_FUNC_RET_PPU_VPON_PCSM_POW_VDIV_HQ_VDDANA_Msk                       (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_5_LOP_POF_FUNC_RET_PPU_VPON_PCSM_POW_VDIV_HQ_VDDANA_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_5_LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_DMYLOAD_VDDANA_Pos                        20U
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_5_LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_DMYLOAD_VDDANA_Msk                        (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_5_LOP_POF_FUNC_RET_PPU_VPON_PCSM_EN_DMYLOAD_VDDANA_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_5_LOP_POF_FUNC_RET_PPU_VPON_PCSM_POW_VDDANA_DET_Pos                           21U
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_5_LOP_POF_FUNC_RET_PPU_VPON_PCSM_POW_VDDANA_DET_Msk                           (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_5_LOP_POF_FUNC_RET_PPU_VPON_PCSM_POW_VDDANA_DET_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_5_LOP_POF_FUNC_RET_PPU_VPON_PCSM_ENCCM_OUT_VDDANA_Pos                         22U
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_5_LOP_POF_FUNC_RET_PPU_VPON_PCSM_ENCCM_OUT_VDDANA_Msk                         (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_5_LOP_POF_FUNC_RET_PPU_VPON_PCSM_ENCCM_OUT_VDDANA_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_5_RESERVED_Pos                                                                23U
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_5_RESERVED_Msk                                                                (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_5_RESERVED_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_5_LOP_POF_OFF_PPU_VPON_PCSM_2_DELAY_Pos                                       24U
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_5_LOP_POF_OFF_PPU_VPON_PCSM_2_DELAY_Msk                                       (0xFUL << AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_5_LOP_POF_OFF_PPU_VPON_PCSM_2_DELAY_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_5_LOP_POF_OFF_PPU_VPON_PCSM_INACTIVE_DELAY_Pos                                28U
+#define AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_5_LOP_POF_OFF_PPU_VPON_PCSM_INACTIVE_DELAY_Msk                                (0xFUL << AON_LOP_POF_FUNC_RET_PPU_VPON_PCSM_5_LOP_POF_OFF_PPU_VPON_PCSM_INACTIVE_DELAY_Pos)
+
+/* 0xA6C    0x4000_0a6c
+    3:0     R/W     RESERVED                                                    4'h0
+    7:4     R/W     LOP_POF_OFF_PPU_VPON_PCSM_SWR2_DELAY                        4'b0000
+    11:8    R/W     LOP_POF_OFF_PPU_VPON_PCSM_SWR3_DELAY                        4'b0000
+    15:12   R/W     LOP_POF_OFF_PPU_VPON_PCSM_SWR4_DELAY                        4'b0000
+    19:16   R/W     LOP_POF_OFF_PPU_VPON_PCSM_SWR5_DELAY                        4'b0000
+    23:20   R/W     LOP_POF_OFF_PPU_VPON_PCSM_LDO1_DELAY                        4'b0000
+    27:24   R/W     LOP_POF_OFF_PPU_VPON_PCSM_LDO2_DELAY                        4'b0001
+    31:28   R/W     LOP_POF_OFF_PPU_VPON_PCSM_1_DELAY                           4'b0001
+ */
+typedef union _AON_LOP_POF_PPU_VPON_PCSM_DELAY_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED: 4;
+        uint32_t LOP_POF_OFF_PPU_VPON_PCSM_SWR2_DELAY: 4;
+        uint32_t LOP_POF_OFF_PPU_VPON_PCSM_SWR3_DELAY: 4;
+        uint32_t LOP_POF_OFF_PPU_VPON_PCSM_SWR4_DELAY: 4;
+        uint32_t LOP_POF_OFF_PPU_VPON_PCSM_SWR5_DELAY: 4;
+        uint32_t LOP_POF_OFF_PPU_VPON_PCSM_LDO1_DELAY: 4;
+        uint32_t LOP_POF_OFF_PPU_VPON_PCSM_LDO2_DELAY: 4;
+        uint32_t LOP_POF_OFF_PPU_VPON_PCSM_1_DELAY: 4;
+    };
+} AON_LOP_POF_PPU_VPON_PCSM_DELAY_TYPE;
+
+/*0x4000_0a6c AON_LOP_POF_PPU_VPON_PCSM_DELAY*/
+#define AON_LOP_POF_PPU_VPON_PCSM_DELAY_RESERVED_Pos                                                                     0U
+#define AON_LOP_POF_PPU_VPON_PCSM_DELAY_RESERVED_Msk                                                                     (0xFUL << AON_LOP_POF_PPU_VPON_PCSM_DELAY_RESERVED_Pos)
+
+#define AON_LOP_POF_PPU_VPON_PCSM_DELAY_LOP_POF_OFF_PPU_VPON_PCSM_SWR2_DELAY_Pos                                         4U
+#define AON_LOP_POF_PPU_VPON_PCSM_DELAY_LOP_POF_OFF_PPU_VPON_PCSM_SWR2_DELAY_Msk                                         (0xFUL << AON_LOP_POF_PPU_VPON_PCSM_DELAY_LOP_POF_OFF_PPU_VPON_PCSM_SWR2_DELAY_Pos)
+
+#define AON_LOP_POF_PPU_VPON_PCSM_DELAY_LOP_POF_OFF_PPU_VPON_PCSM_SWR3_DELAY_Pos                                         8U
+#define AON_LOP_POF_PPU_VPON_PCSM_DELAY_LOP_POF_OFF_PPU_VPON_PCSM_SWR3_DELAY_Msk                                         (0xFUL << AON_LOP_POF_PPU_VPON_PCSM_DELAY_LOP_POF_OFF_PPU_VPON_PCSM_SWR3_DELAY_Pos)
+
+#define AON_LOP_POF_PPU_VPON_PCSM_DELAY_LOP_POF_OFF_PPU_VPON_PCSM_SWR4_DELAY_Pos                                         12U
+#define AON_LOP_POF_PPU_VPON_PCSM_DELAY_LOP_POF_OFF_PPU_VPON_PCSM_SWR4_DELAY_Msk                                         (0xFUL << AON_LOP_POF_PPU_VPON_PCSM_DELAY_LOP_POF_OFF_PPU_VPON_PCSM_SWR4_DELAY_Pos)
+
+#define AON_LOP_POF_PPU_VPON_PCSM_DELAY_LOP_POF_OFF_PPU_VPON_PCSM_SWR5_DELAY_Pos                                         16U
+#define AON_LOP_POF_PPU_VPON_PCSM_DELAY_LOP_POF_OFF_PPU_VPON_PCSM_SWR5_DELAY_Msk                                         (0xFUL << AON_LOP_POF_PPU_VPON_PCSM_DELAY_LOP_POF_OFF_PPU_VPON_PCSM_SWR5_DELAY_Pos)
+
+#define AON_LOP_POF_PPU_VPON_PCSM_DELAY_LOP_POF_OFF_PPU_VPON_PCSM_LDO1_DELAY_Pos                                         20U
+#define AON_LOP_POF_PPU_VPON_PCSM_DELAY_LOP_POF_OFF_PPU_VPON_PCSM_LDO1_DELAY_Msk                                         (0xFUL << AON_LOP_POF_PPU_VPON_PCSM_DELAY_LOP_POF_OFF_PPU_VPON_PCSM_LDO1_DELAY_Pos)
+
+#define AON_LOP_POF_PPU_VPON_PCSM_DELAY_LOP_POF_OFF_PPU_VPON_PCSM_LDO2_DELAY_Pos                                         24U
+#define AON_LOP_POF_PPU_VPON_PCSM_DELAY_LOP_POF_OFF_PPU_VPON_PCSM_LDO2_DELAY_Msk                                         (0xFUL << AON_LOP_POF_PPU_VPON_PCSM_DELAY_LOP_POF_OFF_PPU_VPON_PCSM_LDO2_DELAY_Pos)
+
+#define AON_LOP_POF_PPU_VPON_PCSM_DELAY_LOP_POF_OFF_PPU_VPON_PCSM_1_DELAY_Pos                                            28U
+#define AON_LOP_POF_PPU_VPON_PCSM_DELAY_LOP_POF_OFF_PPU_VPON_PCSM_1_DELAY_Msk                                            (0xFUL << AON_LOP_POF_PPU_VPON_PCSM_DELAY_LOP_POF_OFF_PPU_VPON_PCSM_1_DELAY_Pos)
+
+/* 0xA70    0x4000_0a70
+    17:0    R/W     RESERVED                                                    18'h0
+    19:18   R/W     LOP_POF_PPU_VPON_PCSM_SHIP_7_DELAY                          2'b00
+    21:20   R/W     LOP_POF_PPU_VPON_PCSM_SHIP_6_DELAY                          2'b00
+    23:22   R/W     LOP_POF_PPU_VPON_PCSM_SHIP_5_DELAY                          2'b00
+    25:24   R/W     LOP_POF_PPU_VPON_PCSM_SHIP_4_DELAY                          2'b00
+    27:26   R/W     LOP_POF_PPU_VPON_PCSM_SHIP_3_DELAY                          2'b00
+    29:28   R/W     LOP_POF_PPU_VPON_PCSM_SHIP_2_DELAY                          2'b00
+    31:30   R/W     LOP_POF_PPU_VPON_PCSM_SHIP_1_DELAY                          2'b00
+ */
+typedef union _AON_LOP_POF_PPU_VPON_PCSM_SHIP_DELAY_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED: 18;
+        uint32_t LOP_POF_PPU_VPON_PCSM_SHIP_7_DELAY: 2;
+        uint32_t LOP_POF_PPU_VPON_PCSM_SHIP_6_DELAY: 2;
+        uint32_t LOP_POF_PPU_VPON_PCSM_SHIP_5_DELAY: 2;
+        uint32_t LOP_POF_PPU_VPON_PCSM_SHIP_4_DELAY: 2;
+        uint32_t LOP_POF_PPU_VPON_PCSM_SHIP_3_DELAY: 2;
+        uint32_t LOP_POF_PPU_VPON_PCSM_SHIP_2_DELAY: 2;
+        uint32_t LOP_POF_PPU_VPON_PCSM_SHIP_1_DELAY: 2;
+    };
+} AON_LOP_POF_PPU_VPON_PCSM_SHIP_DELAY_TYPE;
+
+/*0x4000_0a70 AON_LOP_POF_PPU_VPON_PCSM_SHIP_DELAY*/
+#define AON_LOP_POF_PPU_VPON_PCSM_SHIP_DELAY_RESERVED_Pos                                                                0U
+#define AON_LOP_POF_PPU_VPON_PCSM_SHIP_DELAY_RESERVED_Msk                                                                (0x3FFFFUL << AON_LOP_POF_PPU_VPON_PCSM_SHIP_DELAY_RESERVED_Pos)
+
+#define AON_LOP_POF_PPU_VPON_PCSM_SHIP_DELAY_LOP_POF_PPU_VPON_PCSM_SHIP_7_DELAY_Pos                                      18U
+#define AON_LOP_POF_PPU_VPON_PCSM_SHIP_DELAY_LOP_POF_PPU_VPON_PCSM_SHIP_7_DELAY_Msk                                      (0x3UL << AON_LOP_POF_PPU_VPON_PCSM_SHIP_DELAY_LOP_POF_PPU_VPON_PCSM_SHIP_7_DELAY_Pos)
+
+#define AON_LOP_POF_PPU_VPON_PCSM_SHIP_DELAY_LOP_POF_PPU_VPON_PCSM_SHIP_6_DELAY_Pos                                      20U
+#define AON_LOP_POF_PPU_VPON_PCSM_SHIP_DELAY_LOP_POF_PPU_VPON_PCSM_SHIP_6_DELAY_Msk                                      (0x3UL << AON_LOP_POF_PPU_VPON_PCSM_SHIP_DELAY_LOP_POF_PPU_VPON_PCSM_SHIP_6_DELAY_Pos)
+
+#define AON_LOP_POF_PPU_VPON_PCSM_SHIP_DELAY_LOP_POF_PPU_VPON_PCSM_SHIP_5_DELAY_Pos                                      22U
+#define AON_LOP_POF_PPU_VPON_PCSM_SHIP_DELAY_LOP_POF_PPU_VPON_PCSM_SHIP_5_DELAY_Msk                                      (0x3UL << AON_LOP_POF_PPU_VPON_PCSM_SHIP_DELAY_LOP_POF_PPU_VPON_PCSM_SHIP_5_DELAY_Pos)
+
+#define AON_LOP_POF_PPU_VPON_PCSM_SHIP_DELAY_LOP_POF_PPU_VPON_PCSM_SHIP_4_DELAY_Pos                                      24U
+#define AON_LOP_POF_PPU_VPON_PCSM_SHIP_DELAY_LOP_POF_PPU_VPON_PCSM_SHIP_4_DELAY_Msk                                      (0x3UL << AON_LOP_POF_PPU_VPON_PCSM_SHIP_DELAY_LOP_POF_PPU_VPON_PCSM_SHIP_4_DELAY_Pos)
+
+#define AON_LOP_POF_PPU_VPON_PCSM_SHIP_DELAY_LOP_POF_PPU_VPON_PCSM_SHIP_3_DELAY_Pos                                      26U
+#define AON_LOP_POF_PPU_VPON_PCSM_SHIP_DELAY_LOP_POF_PPU_VPON_PCSM_SHIP_3_DELAY_Msk                                      (0x3UL << AON_LOP_POF_PPU_VPON_PCSM_SHIP_DELAY_LOP_POF_PPU_VPON_PCSM_SHIP_3_DELAY_Pos)
+
+#define AON_LOP_POF_PPU_VPON_PCSM_SHIP_DELAY_LOP_POF_PPU_VPON_PCSM_SHIP_2_DELAY_Pos                                      28U
+#define AON_LOP_POF_PPU_VPON_PCSM_SHIP_DELAY_LOP_POF_PPU_VPON_PCSM_SHIP_2_DELAY_Msk                                      (0x3UL << AON_LOP_POF_PPU_VPON_PCSM_SHIP_DELAY_LOP_POF_PPU_VPON_PCSM_SHIP_2_DELAY_Pos)
+
+#define AON_LOP_POF_PPU_VPON_PCSM_SHIP_DELAY_LOP_POF_PPU_VPON_PCSM_SHIP_1_DELAY_Pos                                      30U
+#define AON_LOP_POF_PPU_VPON_PCSM_SHIP_DELAY_LOP_POF_PPU_VPON_PCSM_SHIP_1_DELAY_Msk                                      (0x3UL << AON_LOP_POF_PPU_VPON_PCSM_SHIP_DELAY_LOP_POF_PPU_VPON_PCSM_SHIP_1_DELAY_Pos)
+
+/* 0xA74    0x4000_0a74
+    0       R/W     LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_CMP_LQ_VDDANA              1'b1
+    1       R/W     LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_CMP_HQ_VDDANA              1'b0
+    6:2     R/W     LOP_POF_MEM_OFF_PPU_VPON_PCSM_SEL_VREF_VDDANA_LQ            5'b10011
+    14:7    R/W     LOP_POF_MEM_OFF_PPU_VPON_PCSM_TUNE_VDDANA                   8'b01111010
+    15      R/W     LOP_POF_MEM_OFF_PPU_VPON_PCSM_POW_VDIV_LQ_VDDANA            1'b1
+    16      R/W     LOP_POF_MEM_OFF_PPU_VPON_PCSM_POW_VDIV_HQ_VDDANA            1'b0
+    17      R/W     LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_DMYLOAD_VDDANA             1'b0
+    18      R/W     LOP_POF_MEM_OFF_PPU_VPON_PCSM_POW_VDDANA_DET                1'b1
+    19      R/W     LOP_POF_MEM_OFF_PPU_VPON_PCSM_ENCCM_OUT_VDDANA              1'b1
+    23:20   R/W     LOP_POF_OFF_PPU_VPON_PCSM_SWR2_OFF2MEMOFF_DELAY             4'b0110
+    27:24   R/W     LOP_POF_OFF_PPU_VPON_PCSM_SWR4_OFF2MEMOFF_DELAY             4'b0010
+    31:28   R/W     LOP_POF_OFF_PPU_VPON_PCSM_1_OFF2MEMOFF_DELAY                4'b0000
+ */
+typedef union _AON_LOP_POF_PPU_VPON_PCSM_DELAY_2_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_CMP_LQ_VDDANA: 1;
+        uint32_t LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_CMP_HQ_VDDANA: 1;
+        uint32_t LOP_POF_MEM_OFF_PPU_VPON_PCSM_SEL_VREF_VDDANA_LQ: 5;
+        uint32_t LOP_POF_MEM_OFF_PPU_VPON_PCSM_TUNE_VDDANA: 8;
+        uint32_t LOP_POF_MEM_OFF_PPU_VPON_PCSM_POW_VDIV_LQ_VDDANA: 1;
+        uint32_t LOP_POF_MEM_OFF_PPU_VPON_PCSM_POW_VDIV_HQ_VDDANA: 1;
+        uint32_t LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_DMYLOAD_VDDANA: 1;
+        uint32_t LOP_POF_MEM_OFF_PPU_VPON_PCSM_POW_VDDANA_DET: 1;
+        uint32_t LOP_POF_MEM_OFF_PPU_VPON_PCSM_ENCCM_OUT_VDDANA: 1;
+        uint32_t LOP_POF_OFF_PPU_VPON_PCSM_SWR2_OFF2MEMOFF_DELAY: 4;
+        uint32_t LOP_POF_OFF_PPU_VPON_PCSM_SWR4_OFF2MEMOFF_DELAY: 4;
+        uint32_t LOP_POF_OFF_PPU_VPON_PCSM_1_OFF2MEMOFF_DELAY: 4;
+    };
+} AON_LOP_POF_PPU_VPON_PCSM_DELAY_2_TYPE;
+
+/*0x4000_0a74 AON_LOP_POF_PPU_VPON_PCSM_DELAY_2*/
+#define AON_LOP_POF_PPU_VPON_PCSM_DELAY_2_LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_CMP_LQ_VDDANA_Pos                             0U
+#define AON_LOP_POF_PPU_VPON_PCSM_DELAY_2_LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_CMP_LQ_VDDANA_Msk                             (0x1UL << AON_LOP_POF_PPU_VPON_PCSM_DELAY_2_LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_CMP_LQ_VDDANA_Pos)
+
+#define AON_LOP_POF_PPU_VPON_PCSM_DELAY_2_LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_CMP_HQ_VDDANA_Pos                             1U
+#define AON_LOP_POF_PPU_VPON_PCSM_DELAY_2_LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_CMP_HQ_VDDANA_Msk                             (0x1UL << AON_LOP_POF_PPU_VPON_PCSM_DELAY_2_LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_CMP_HQ_VDDANA_Pos)
+
+#define AON_LOP_POF_PPU_VPON_PCSM_DELAY_2_LOP_POF_MEM_OFF_PPU_VPON_PCSM_SEL_VREF_VDDANA_LQ_Pos                           2U
+#define AON_LOP_POF_PPU_VPON_PCSM_DELAY_2_LOP_POF_MEM_OFF_PPU_VPON_PCSM_SEL_VREF_VDDANA_LQ_Msk                           (0x1FUL << AON_LOP_POF_PPU_VPON_PCSM_DELAY_2_LOP_POF_MEM_OFF_PPU_VPON_PCSM_SEL_VREF_VDDANA_LQ_Pos)
+
+#define AON_LOP_POF_PPU_VPON_PCSM_DELAY_2_LOP_POF_MEM_OFF_PPU_VPON_PCSM_TUNE_VDDANA_Pos                                  7U
+#define AON_LOP_POF_PPU_VPON_PCSM_DELAY_2_LOP_POF_MEM_OFF_PPU_VPON_PCSM_TUNE_VDDANA_Msk                                  (0xFFUL << AON_LOP_POF_PPU_VPON_PCSM_DELAY_2_LOP_POF_MEM_OFF_PPU_VPON_PCSM_TUNE_VDDANA_Pos)
+
+#define AON_LOP_POF_PPU_VPON_PCSM_DELAY_2_LOP_POF_MEM_OFF_PPU_VPON_PCSM_POW_VDIV_LQ_VDDANA_Pos                           15U
+#define AON_LOP_POF_PPU_VPON_PCSM_DELAY_2_LOP_POF_MEM_OFF_PPU_VPON_PCSM_POW_VDIV_LQ_VDDANA_Msk                           (0x1UL << AON_LOP_POF_PPU_VPON_PCSM_DELAY_2_LOP_POF_MEM_OFF_PPU_VPON_PCSM_POW_VDIV_LQ_VDDANA_Pos)
+
+#define AON_LOP_POF_PPU_VPON_PCSM_DELAY_2_LOP_POF_MEM_OFF_PPU_VPON_PCSM_POW_VDIV_HQ_VDDANA_Pos                           16U
+#define AON_LOP_POF_PPU_VPON_PCSM_DELAY_2_LOP_POF_MEM_OFF_PPU_VPON_PCSM_POW_VDIV_HQ_VDDANA_Msk                           (0x1UL << AON_LOP_POF_PPU_VPON_PCSM_DELAY_2_LOP_POF_MEM_OFF_PPU_VPON_PCSM_POW_VDIV_HQ_VDDANA_Pos)
+
+#define AON_LOP_POF_PPU_VPON_PCSM_DELAY_2_LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_DMYLOAD_VDDANA_Pos                            17U
+#define AON_LOP_POF_PPU_VPON_PCSM_DELAY_2_LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_DMYLOAD_VDDANA_Msk                            (0x1UL << AON_LOP_POF_PPU_VPON_PCSM_DELAY_2_LOP_POF_MEM_OFF_PPU_VPON_PCSM_EN_DMYLOAD_VDDANA_Pos)
+
+#define AON_LOP_POF_PPU_VPON_PCSM_DELAY_2_LOP_POF_MEM_OFF_PPU_VPON_PCSM_POW_VDDANA_DET_Pos                               18U
+#define AON_LOP_POF_PPU_VPON_PCSM_DELAY_2_LOP_POF_MEM_OFF_PPU_VPON_PCSM_POW_VDDANA_DET_Msk                               (0x1UL << AON_LOP_POF_PPU_VPON_PCSM_DELAY_2_LOP_POF_MEM_OFF_PPU_VPON_PCSM_POW_VDDANA_DET_Pos)
+
+#define AON_LOP_POF_PPU_VPON_PCSM_DELAY_2_LOP_POF_MEM_OFF_PPU_VPON_PCSM_ENCCM_OUT_VDDANA_Pos                             19U
+#define AON_LOP_POF_PPU_VPON_PCSM_DELAY_2_LOP_POF_MEM_OFF_PPU_VPON_PCSM_ENCCM_OUT_VDDANA_Msk                             (0x1UL << AON_LOP_POF_PPU_VPON_PCSM_DELAY_2_LOP_POF_MEM_OFF_PPU_VPON_PCSM_ENCCM_OUT_VDDANA_Pos)
+
+#define AON_LOP_POF_PPU_VPON_PCSM_DELAY_2_LOP_POF_OFF_PPU_VPON_PCSM_SWR2_OFF2MEMOFF_DELAY_Pos                            20U
+#define AON_LOP_POF_PPU_VPON_PCSM_DELAY_2_LOP_POF_OFF_PPU_VPON_PCSM_SWR2_OFF2MEMOFF_DELAY_Msk                            (0xFUL << AON_LOP_POF_PPU_VPON_PCSM_DELAY_2_LOP_POF_OFF_PPU_VPON_PCSM_SWR2_OFF2MEMOFF_DELAY_Pos)
+
+#define AON_LOP_POF_PPU_VPON_PCSM_DELAY_2_LOP_POF_OFF_PPU_VPON_PCSM_SWR4_OFF2MEMOFF_DELAY_Pos                            24U
+#define AON_LOP_POF_PPU_VPON_PCSM_DELAY_2_LOP_POF_OFF_PPU_VPON_PCSM_SWR4_OFF2MEMOFF_DELAY_Msk                            (0xFUL << AON_LOP_POF_PPU_VPON_PCSM_DELAY_2_LOP_POF_OFF_PPU_VPON_PCSM_SWR4_OFF2MEMOFF_DELAY_Pos)
+
+#define AON_LOP_POF_PPU_VPON_PCSM_DELAY_2_LOP_POF_OFF_PPU_VPON_PCSM_1_OFF2MEMOFF_DELAY_Pos                               28U
+#define AON_LOP_POF_PPU_VPON_PCSM_DELAY_2_LOP_POF_OFF_PPU_VPON_PCSM_1_OFF2MEMOFF_DELAY_Msk                               (0xFUL << AON_LOP_POF_PPU_VPON_PCSM_DELAY_2_LOP_POF_OFF_PPU_VPON_PCSM_1_OFF2MEMOFF_DELAY_Pos)
+
+/* 0xA78    0x4000_0a78
+    0       R/W     LOP_POF_FULL_RET_PPU_VCORE1_PCSM_R_PADMUX_ALL_PUPDSD_AS_EN  1'b1
+    1       R/W     RESERVED_5                                                  1'b0
+    5:2     R/W     RESERVED_4                                                  4'b0000
+    9:6     R/W     RESERVED_3                                                  4'b0000
+    13:10   R/W     RESERVED_2                                                  4'b0000
+    17:14   R/W     RESERVED_1                                                  4'b0000
+    21:18   R/W     RESERVED                                                    4'b0000
+    25:22   R/W     LOP_POF_OFF_PPU_VCORE1_PCSM_3_DELAY                         4'b0001
+    26      R/W     LOP_POF_PLL1_PCSM_PLL1_LDO_DIG_SW_LDO2PWRCUT                1'b0
+    27      R/W     LOP_POF_PLL1_PCSM_PLL1_LDO_DIG_LDO_VPULSE                   1'b0
+    28      R/W     LOP_POF_PLL1_PCSM_PLL1_LDO_DIG_IB_EN                        1'b0
+    29      R/W     LOP_POF_PLL1_PCSM_PLL1_LDO_ANA_SW_LDO2PWRCUT                1'b0
+    30      R/W     LOP_POF_PLL1_PCSM_PLL1_LDO_ANA_LDO_VPULSE                   1'b0
+    31      R/W     LOP_POF_PLL1_PCSM_PLL1_LDO_ANA_IB_EN                        1'b0
+ */
+typedef union _AON_LOP_POF_OTHER_PCSM_SWAP_PCSM_1_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t LOP_POF_FULL_RET_PPU_VCORE1_PCSM_R_PADMUX_ALL_PUPDSD_AS_EN: 1;
+        uint32_t RESERVED_5: 1;
+        uint32_t RESERVED_4: 4;
+        uint32_t RESERVED_3: 4;
+        uint32_t RESERVED_2: 4;
+        uint32_t RESERVED_1: 4;
+        uint32_t RESERVED: 4;
+        uint32_t LOP_POF_OFF_PPU_VCORE1_PCSM_3_DELAY: 4;
+        uint32_t LOP_POF_PLL1_PCSM_PLL1_LDO_DIG_SW_LDO2PWRCUT: 1;
+        uint32_t LOP_POF_PLL1_PCSM_PLL1_LDO_DIG_LDO_VPULSE: 1;
+        uint32_t LOP_POF_PLL1_PCSM_PLL1_LDO_DIG_IB_EN: 1;
+        uint32_t LOP_POF_PLL1_PCSM_PLL1_LDO_ANA_SW_LDO2PWRCUT: 1;
+        uint32_t LOP_POF_PLL1_PCSM_PLL1_LDO_ANA_LDO_VPULSE: 1;
+        uint32_t LOP_POF_PLL1_PCSM_PLL1_LDO_ANA_IB_EN: 1;
+    };
+} AON_LOP_POF_OTHER_PCSM_SWAP_PCSM_1_TYPE;
+
+/*0x4000_0a78 AON_LOP_POF_OTHER_PCSM_SWAP_PCSM_1*/
+#define AON_LOP_POF_OTHER_PCSM_SWAP_PCSM_1_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_R_PADMUX_ALL_PUPDSD_AS_EN_Pos                0U
+#define AON_LOP_POF_OTHER_PCSM_SWAP_PCSM_1_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_R_PADMUX_ALL_PUPDSD_AS_EN_Msk                (0x1UL << AON_LOP_POF_OTHER_PCSM_SWAP_PCSM_1_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_R_PADMUX_ALL_PUPDSD_AS_EN_Pos)
+
+#define AON_LOP_POF_OTHER_PCSM_SWAP_PCSM_1_RESERVED_5_Pos                                                                1U
+#define AON_LOP_POF_OTHER_PCSM_SWAP_PCSM_1_RESERVED_5_Msk                                                                (0x1UL << AON_LOP_POF_OTHER_PCSM_SWAP_PCSM_1_RESERVED_5_Pos)
+
+#define AON_LOP_POF_OTHER_PCSM_SWAP_PCSM_1_RESERVED_4_Pos                                                                2U
+#define AON_LOP_POF_OTHER_PCSM_SWAP_PCSM_1_RESERVED_4_Msk                                                                (0xFUL << AON_LOP_POF_OTHER_PCSM_SWAP_PCSM_1_RESERVED_4_Pos)
+
+#define AON_LOP_POF_OTHER_PCSM_SWAP_PCSM_1_RESERVED_3_Pos                                                                6U
+#define AON_LOP_POF_OTHER_PCSM_SWAP_PCSM_1_RESERVED_3_Msk                                                                (0xFUL << AON_LOP_POF_OTHER_PCSM_SWAP_PCSM_1_RESERVED_3_Pos)
+
+#define AON_LOP_POF_OTHER_PCSM_SWAP_PCSM_1_RESERVED_2_Pos                                                                10U
+#define AON_LOP_POF_OTHER_PCSM_SWAP_PCSM_1_RESERVED_2_Msk                                                                (0xFUL << AON_LOP_POF_OTHER_PCSM_SWAP_PCSM_1_RESERVED_2_Pos)
+
+#define AON_LOP_POF_OTHER_PCSM_SWAP_PCSM_1_RESERVED_1_Pos                                                                14U
+#define AON_LOP_POF_OTHER_PCSM_SWAP_PCSM_1_RESERVED_1_Msk                                                                (0xFUL << AON_LOP_POF_OTHER_PCSM_SWAP_PCSM_1_RESERVED_1_Pos)
+
+#define AON_LOP_POF_OTHER_PCSM_SWAP_PCSM_1_RESERVED_Pos                                                                  18U
+#define AON_LOP_POF_OTHER_PCSM_SWAP_PCSM_1_RESERVED_Msk                                                                  (0xFUL << AON_LOP_POF_OTHER_PCSM_SWAP_PCSM_1_RESERVED_Pos)
+
+#define AON_LOP_POF_OTHER_PCSM_SWAP_PCSM_1_LOP_POF_OFF_PPU_VCORE1_PCSM_3_DELAY_Pos                                       22U
+#define AON_LOP_POF_OTHER_PCSM_SWAP_PCSM_1_LOP_POF_OFF_PPU_VCORE1_PCSM_3_DELAY_Msk                                       (0xFUL << AON_LOP_POF_OTHER_PCSM_SWAP_PCSM_1_LOP_POF_OFF_PPU_VCORE1_PCSM_3_DELAY_Pos)
+
+#define AON_LOP_POF_OTHER_PCSM_SWAP_PCSM_1_LOP_POF_PLL1_PCSM_PLL1_LDO_DIG_SW_LDO2PWRCUT_Pos                              26U
+#define AON_LOP_POF_OTHER_PCSM_SWAP_PCSM_1_LOP_POF_PLL1_PCSM_PLL1_LDO_DIG_SW_LDO2PWRCUT_Msk                              (0x1UL << AON_LOP_POF_OTHER_PCSM_SWAP_PCSM_1_LOP_POF_PLL1_PCSM_PLL1_LDO_DIG_SW_LDO2PWRCUT_Pos)
+
+#define AON_LOP_POF_OTHER_PCSM_SWAP_PCSM_1_LOP_POF_PLL1_PCSM_PLL1_LDO_DIG_LDO_VPULSE_Pos                                 27U
+#define AON_LOP_POF_OTHER_PCSM_SWAP_PCSM_1_LOP_POF_PLL1_PCSM_PLL1_LDO_DIG_LDO_VPULSE_Msk                                 (0x1UL << AON_LOP_POF_OTHER_PCSM_SWAP_PCSM_1_LOP_POF_PLL1_PCSM_PLL1_LDO_DIG_LDO_VPULSE_Pos)
+
+#define AON_LOP_POF_OTHER_PCSM_SWAP_PCSM_1_LOP_POF_PLL1_PCSM_PLL1_LDO_DIG_IB_EN_Pos                                      28U
+#define AON_LOP_POF_OTHER_PCSM_SWAP_PCSM_1_LOP_POF_PLL1_PCSM_PLL1_LDO_DIG_IB_EN_Msk                                      (0x1UL << AON_LOP_POF_OTHER_PCSM_SWAP_PCSM_1_LOP_POF_PLL1_PCSM_PLL1_LDO_DIG_IB_EN_Pos)
+
+#define AON_LOP_POF_OTHER_PCSM_SWAP_PCSM_1_LOP_POF_PLL1_PCSM_PLL1_LDO_ANA_SW_LDO2PWRCUT_Pos                              29U
+#define AON_LOP_POF_OTHER_PCSM_SWAP_PCSM_1_LOP_POF_PLL1_PCSM_PLL1_LDO_ANA_SW_LDO2PWRCUT_Msk                              (0x1UL << AON_LOP_POF_OTHER_PCSM_SWAP_PCSM_1_LOP_POF_PLL1_PCSM_PLL1_LDO_ANA_SW_LDO2PWRCUT_Pos)
+
+#define AON_LOP_POF_OTHER_PCSM_SWAP_PCSM_1_LOP_POF_PLL1_PCSM_PLL1_LDO_ANA_LDO_VPULSE_Pos                                 30U
+#define AON_LOP_POF_OTHER_PCSM_SWAP_PCSM_1_LOP_POF_PLL1_PCSM_PLL1_LDO_ANA_LDO_VPULSE_Msk                                 (0x1UL << AON_LOP_POF_OTHER_PCSM_SWAP_PCSM_1_LOP_POF_PLL1_PCSM_PLL1_LDO_ANA_LDO_VPULSE_Pos)
+
+#define AON_LOP_POF_OTHER_PCSM_SWAP_PCSM_1_LOP_POF_PLL1_PCSM_PLL1_LDO_ANA_IB_EN_Pos                                      31U
+#define AON_LOP_POF_OTHER_PCSM_SWAP_PCSM_1_LOP_POF_PLL1_PCSM_PLL1_LDO_ANA_IB_EN_Msk                                      (0x1UL << AON_LOP_POF_OTHER_PCSM_SWAP_PCSM_1_LOP_POF_PLL1_PCSM_PLL1_LDO_ANA_IB_EN_Pos)
+
+/* 0xA7C    0x4000_0a7c
+    2:0     R/W     RESERVED_2                                                  3'b000
+    6:3     R/W     RESERVED_1                                                  4'b0000
+    9:7     R/W     RESERVED                                                    3'b000
+    10      R/W     LOP_POF_VCORE_OP1_PADRV_PCUT_CTRL_SEL                       1'b1
+    14:11   R/W     LOP_POF_VCORE_OP1_4_PCSM_DELAY                              4'b0101
+    18:15   R/W     LOP_POF_VCORE_OP1_3_PCSM_DELAY                              4'b0001
+    22:19   R/W     LOP_POF_VCORE_OP1_2_PCSM_DELAY                              4'b0001
+    26:23   R/W     LOP_POF_VCORE_OP1_INACTIVE_PCSM_DELAY                       4'b0001
+    27      R/W     LOP_POF_VCORE_OP1_PCSM_SPIC_PDEX_CMD                        1'b1
+    28      R/W     LOP_POF_VCORE_OP1_PCSM_SPIC_PDEX_REQ                        1'b0
+    29      R/W     LOP_POF_VCORE_OP1_PCSM_SEL_EFLASH_HV18                      1'b0
+    30      R/W     LOP_POF_VCORE_OP1_PCSM_SEL_EFLASH_HV25                      1'b0
+    31      R/W     LOP_POF_FULL_RET_PPU_VCORE1_PCSM_REG_ENLPM                  1'b1
+ */
+typedef union _AON_LOP_POF_OTHER_PCSM_SWAP_PCSM_2_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED_2: 3;
+        uint32_t RESERVED_1: 4;
+        uint32_t RESERVED: 3;
+        uint32_t LOP_POF_VCORE_OP1_PADRV_PCUT_CTRL_SEL: 1;
+        uint32_t LOP_POF_VCORE_OP1_4_PCSM_DELAY: 4;
+        uint32_t LOP_POF_VCORE_OP1_3_PCSM_DELAY: 4;
+        uint32_t LOP_POF_VCORE_OP1_2_PCSM_DELAY: 4;
+        uint32_t LOP_POF_VCORE_OP1_INACTIVE_PCSM_DELAY: 4;
+        uint32_t LOP_POF_VCORE_OP1_PCSM_SPIC_PDEX_CMD: 1;
+        uint32_t LOP_POF_VCORE_OP1_PCSM_SPIC_PDEX_REQ: 1;
+        uint32_t LOP_POF_VCORE_OP1_PCSM_SEL_EFLASH_HV18: 1;
+        uint32_t LOP_POF_VCORE_OP1_PCSM_SEL_EFLASH_HV25: 1;
+        uint32_t LOP_POF_FULL_RET_PPU_VCORE1_PCSM_REG_ENLPM: 1;
+    };
+} AON_LOP_POF_OTHER_PCSM_SWAP_PCSM_2_TYPE;
+
+/*0x4000_0a7c AON_LOP_POF_OTHER_PCSM_SWAP_PCSM_2*/
+#define AON_LOP_POF_OTHER_PCSM_SWAP_PCSM_2_RESERVED_2_Pos                                                                0U
+#define AON_LOP_POF_OTHER_PCSM_SWAP_PCSM_2_RESERVED_2_Msk                                                                (0x7UL << AON_LOP_POF_OTHER_PCSM_SWAP_PCSM_2_RESERVED_2_Pos)
+
+#define AON_LOP_POF_OTHER_PCSM_SWAP_PCSM_2_RESERVED_1_Pos                                                                3U
+#define AON_LOP_POF_OTHER_PCSM_SWAP_PCSM_2_RESERVED_1_Msk                                                                (0xFUL << AON_LOP_POF_OTHER_PCSM_SWAP_PCSM_2_RESERVED_1_Pos)
+
+#define AON_LOP_POF_OTHER_PCSM_SWAP_PCSM_2_RESERVED_Pos                                                                  7U
+#define AON_LOP_POF_OTHER_PCSM_SWAP_PCSM_2_RESERVED_Msk                                                                  (0x7UL << AON_LOP_POF_OTHER_PCSM_SWAP_PCSM_2_RESERVED_Pos)
+
+#define AON_LOP_POF_OTHER_PCSM_SWAP_PCSM_2_LOP_POF_VCORE_OP1_PADRV_PCUT_CTRL_SEL_Pos                                     10U
+#define AON_LOP_POF_OTHER_PCSM_SWAP_PCSM_2_LOP_POF_VCORE_OP1_PADRV_PCUT_CTRL_SEL_Msk                                     (0x1UL << AON_LOP_POF_OTHER_PCSM_SWAP_PCSM_2_LOP_POF_VCORE_OP1_PADRV_PCUT_CTRL_SEL_Pos)
+
+#define AON_LOP_POF_OTHER_PCSM_SWAP_PCSM_2_LOP_POF_VCORE_OP1_4_PCSM_DELAY_Pos                                            11U
+#define AON_LOP_POF_OTHER_PCSM_SWAP_PCSM_2_LOP_POF_VCORE_OP1_4_PCSM_DELAY_Msk                                            (0xFUL << AON_LOP_POF_OTHER_PCSM_SWAP_PCSM_2_LOP_POF_VCORE_OP1_4_PCSM_DELAY_Pos)
+
+#define AON_LOP_POF_OTHER_PCSM_SWAP_PCSM_2_LOP_POF_VCORE_OP1_3_PCSM_DELAY_Pos                                            15U
+#define AON_LOP_POF_OTHER_PCSM_SWAP_PCSM_2_LOP_POF_VCORE_OP1_3_PCSM_DELAY_Msk                                            (0xFUL << AON_LOP_POF_OTHER_PCSM_SWAP_PCSM_2_LOP_POF_VCORE_OP1_3_PCSM_DELAY_Pos)
+
+#define AON_LOP_POF_OTHER_PCSM_SWAP_PCSM_2_LOP_POF_VCORE_OP1_2_PCSM_DELAY_Pos                                            19U
+#define AON_LOP_POF_OTHER_PCSM_SWAP_PCSM_2_LOP_POF_VCORE_OP1_2_PCSM_DELAY_Msk                                            (0xFUL << AON_LOP_POF_OTHER_PCSM_SWAP_PCSM_2_LOP_POF_VCORE_OP1_2_PCSM_DELAY_Pos)
+
+#define AON_LOP_POF_OTHER_PCSM_SWAP_PCSM_2_LOP_POF_VCORE_OP1_INACTIVE_PCSM_DELAY_Pos                                     23U
+#define AON_LOP_POF_OTHER_PCSM_SWAP_PCSM_2_LOP_POF_VCORE_OP1_INACTIVE_PCSM_DELAY_Msk                                     (0xFUL << AON_LOP_POF_OTHER_PCSM_SWAP_PCSM_2_LOP_POF_VCORE_OP1_INACTIVE_PCSM_DELAY_Pos)
+
+#define AON_LOP_POF_OTHER_PCSM_SWAP_PCSM_2_LOP_POF_VCORE_OP1_PCSM_SPIC_PDEX_CMD_Pos                                      27U
+#define AON_LOP_POF_OTHER_PCSM_SWAP_PCSM_2_LOP_POF_VCORE_OP1_PCSM_SPIC_PDEX_CMD_Msk                                      (0x1UL << AON_LOP_POF_OTHER_PCSM_SWAP_PCSM_2_LOP_POF_VCORE_OP1_PCSM_SPIC_PDEX_CMD_Pos)
+
+#define AON_LOP_POF_OTHER_PCSM_SWAP_PCSM_2_LOP_POF_VCORE_OP1_PCSM_SPIC_PDEX_REQ_Pos                                      28U
+#define AON_LOP_POF_OTHER_PCSM_SWAP_PCSM_2_LOP_POF_VCORE_OP1_PCSM_SPIC_PDEX_REQ_Msk                                      (0x1UL << AON_LOP_POF_OTHER_PCSM_SWAP_PCSM_2_LOP_POF_VCORE_OP1_PCSM_SPIC_PDEX_REQ_Pos)
+
+#define AON_LOP_POF_OTHER_PCSM_SWAP_PCSM_2_LOP_POF_VCORE_OP1_PCSM_SEL_EFLASH_HV18_Pos                                    29U
+#define AON_LOP_POF_OTHER_PCSM_SWAP_PCSM_2_LOP_POF_VCORE_OP1_PCSM_SEL_EFLASH_HV18_Msk                                    (0x1UL << AON_LOP_POF_OTHER_PCSM_SWAP_PCSM_2_LOP_POF_VCORE_OP1_PCSM_SEL_EFLASH_HV18_Pos)
+
+#define AON_LOP_POF_OTHER_PCSM_SWAP_PCSM_2_LOP_POF_VCORE_OP1_PCSM_SEL_EFLASH_HV25_Pos                                    30U
+#define AON_LOP_POF_OTHER_PCSM_SWAP_PCSM_2_LOP_POF_VCORE_OP1_PCSM_SEL_EFLASH_HV25_Msk                                    (0x1UL << AON_LOP_POF_OTHER_PCSM_SWAP_PCSM_2_LOP_POF_VCORE_OP1_PCSM_SEL_EFLASH_HV25_Pos)
+
+#define AON_LOP_POF_OTHER_PCSM_SWAP_PCSM_2_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_REG_ENLPM_Pos                                31U
+#define AON_LOP_POF_OTHER_PCSM_SWAP_PCSM_2_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_REG_ENLPM_Msk                                (0x1UL << AON_LOP_POF_OTHER_PCSM_SWAP_PCSM_2_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_REG_ENLPM_Pos)
+
+/* 0xB18    0x4000_0b18
+    0       R/W     RESERVED_16                                                 1'b0
+    4:1     R/W     RESERVED_15                                                 4'b0000
+    12:5    R/W     RESERVED_14                                                 8'b00000000
+    16:13   R/W     RESERVED_13                                                 4'b0000
+    17      R/W     RESERVED_12                                                 1'b0
+    18      R/W     RESERVED_11                                                 1'b0
+    19      R/W     RESERVED_10                                                 1'b0
+    20      R/W     RESERVED_9                                                  1'b0
+    21      R/W     RESERVED_8                                                  1'b0
+    22      R/W     RESERVED_7                                                  1'b0
+    23      R/W     RESERVED_6                                                  1'b0
+    24      R/W     RESERVED_5                                                  1'b0
+    25      R/W     RESERVED_4                                                  1'b0
+    26      R/W     RESERVED_3                                                  1'b0
+    27      R/W     RESERVED_2                                                  1'b0
+    30:28   R/W     RESERVED_1                                                  3'b000
+    31      R/W     RESERVED                                                    1'b0
+ */
+typedef union _AON_LOP_PON_VPON_40MXTAL_PCSM_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED_16: 1;
+        uint32_t RESERVED_15: 4;
+        uint32_t RESERVED_14: 8;
+        uint32_t RESERVED_13: 4;
+        uint32_t RESERVED_12: 1;
+        uint32_t RESERVED_11: 1;
+        uint32_t RESERVED_10: 1;
+        uint32_t RESERVED_9: 1;
+        uint32_t RESERVED_8: 1;
+        uint32_t RESERVED_7: 1;
+        uint32_t RESERVED_6: 1;
+        uint32_t RESERVED_5: 1;
+        uint32_t RESERVED_4: 1;
+        uint32_t RESERVED_3: 1;
+        uint32_t RESERVED_2: 1;
+        uint32_t RESERVED_1: 3;
+        uint32_t RESERVED: 1;
+    };
+} AON_LOP_PON_VPON_40MXTAL_PCSM_TYPE;
+
+/*0x4000_0b18 AON_LOP_PON_VPON_40MXTAL_PCSM*/
+#define AON_LOP_PON_VPON_40MXTAL_PCSM_RESERVED_16_Pos                                                                    0U
+#define AON_LOP_PON_VPON_40MXTAL_PCSM_RESERVED_16_Msk                                                                    (0x1UL << AON_LOP_PON_VPON_40MXTAL_PCSM_RESERVED_16_Pos)
+
+#define AON_LOP_PON_VPON_40MXTAL_PCSM_RESERVED_15_Pos                                                                    1U
+#define AON_LOP_PON_VPON_40MXTAL_PCSM_RESERVED_15_Msk                                                                    (0xFUL << AON_LOP_PON_VPON_40MXTAL_PCSM_RESERVED_15_Pos)
+
+#define AON_LOP_PON_VPON_40MXTAL_PCSM_RESERVED_14_Pos                                                                    5U
+#define AON_LOP_PON_VPON_40MXTAL_PCSM_RESERVED_14_Msk                                                                    (0xFFUL << AON_LOP_PON_VPON_40MXTAL_PCSM_RESERVED_14_Pos)
+
+#define AON_LOP_PON_VPON_40MXTAL_PCSM_RESERVED_13_Pos                                                                    13U
+#define AON_LOP_PON_VPON_40MXTAL_PCSM_RESERVED_13_Msk                                                                    (0xFUL << AON_LOP_PON_VPON_40MXTAL_PCSM_RESERVED_13_Pos)
+
+#define AON_LOP_PON_VPON_40MXTAL_PCSM_RESERVED_12_Pos                                                                    17U
+#define AON_LOP_PON_VPON_40MXTAL_PCSM_RESERVED_12_Msk                                                                    (0x1UL << AON_LOP_PON_VPON_40MXTAL_PCSM_RESERVED_12_Pos)
+
+#define AON_LOP_PON_VPON_40MXTAL_PCSM_RESERVED_11_Pos                                                                    18U
+#define AON_LOP_PON_VPON_40MXTAL_PCSM_RESERVED_11_Msk                                                                    (0x1UL << AON_LOP_PON_VPON_40MXTAL_PCSM_RESERVED_11_Pos)
+
+#define AON_LOP_PON_VPON_40MXTAL_PCSM_RESERVED_10_Pos                                                                    19U
+#define AON_LOP_PON_VPON_40MXTAL_PCSM_RESERVED_10_Msk                                                                    (0x1UL << AON_LOP_PON_VPON_40MXTAL_PCSM_RESERVED_10_Pos)
+
+#define AON_LOP_PON_VPON_40MXTAL_PCSM_RESERVED_9_Pos                                                                     20U
+#define AON_LOP_PON_VPON_40MXTAL_PCSM_RESERVED_9_Msk                                                                     (0x1UL << AON_LOP_PON_VPON_40MXTAL_PCSM_RESERVED_9_Pos)
+
+#define AON_LOP_PON_VPON_40MXTAL_PCSM_RESERVED_8_Pos                                                                     21U
+#define AON_LOP_PON_VPON_40MXTAL_PCSM_RESERVED_8_Msk                                                                     (0x1UL << AON_LOP_PON_VPON_40MXTAL_PCSM_RESERVED_8_Pos)
+
+#define AON_LOP_PON_VPON_40MXTAL_PCSM_RESERVED_7_Pos                                                                     22U
+#define AON_LOP_PON_VPON_40MXTAL_PCSM_RESERVED_7_Msk                                                                     (0x1UL << AON_LOP_PON_VPON_40MXTAL_PCSM_RESERVED_7_Pos)
+
+#define AON_LOP_PON_VPON_40MXTAL_PCSM_RESERVED_6_Pos                                                                     23U
+#define AON_LOP_PON_VPON_40MXTAL_PCSM_RESERVED_6_Msk                                                                     (0x1UL << AON_LOP_PON_VPON_40MXTAL_PCSM_RESERVED_6_Pos)
+
+#define AON_LOP_PON_VPON_40MXTAL_PCSM_RESERVED_5_Pos                                                                     24U
+#define AON_LOP_PON_VPON_40MXTAL_PCSM_RESERVED_5_Msk                                                                     (0x1UL << AON_LOP_PON_VPON_40MXTAL_PCSM_RESERVED_5_Pos)
+
+#define AON_LOP_PON_VPON_40MXTAL_PCSM_RESERVED_4_Pos                                                                     25U
+#define AON_LOP_PON_VPON_40MXTAL_PCSM_RESERVED_4_Msk                                                                     (0x1UL << AON_LOP_PON_VPON_40MXTAL_PCSM_RESERVED_4_Pos)
+
+#define AON_LOP_PON_VPON_40MXTAL_PCSM_RESERVED_3_Pos                                                                     26U
+#define AON_LOP_PON_VPON_40MXTAL_PCSM_RESERVED_3_Msk                                                                     (0x1UL << AON_LOP_PON_VPON_40MXTAL_PCSM_RESERVED_3_Pos)
+
+#define AON_LOP_PON_VPON_40MXTAL_PCSM_RESERVED_2_Pos                                                                     27U
+#define AON_LOP_PON_VPON_40MXTAL_PCSM_RESERVED_2_Msk                                                                     (0x1UL << AON_LOP_PON_VPON_40MXTAL_PCSM_RESERVED_2_Pos)
+
+#define AON_LOP_PON_VPON_40MXTAL_PCSM_RESERVED_1_Pos                                                                     28U
+#define AON_LOP_PON_VPON_40MXTAL_PCSM_RESERVED_1_Msk                                                                     (0x7UL << AON_LOP_PON_VPON_40MXTAL_PCSM_RESERVED_1_Pos)
+
+#define AON_LOP_PON_VPON_40MXTAL_PCSM_RESERVED_Pos                                                                       31U
+#define AON_LOP_PON_VPON_40MXTAL_PCSM_RESERVED_Msk                                                                       (0x1UL << AON_LOP_PON_VPON_40MXTAL_PCSM_RESERVED_Pos)
+
+/* 0xB14    0x4000_0b14
+    9:0     R/W     RESERVED_19                                                 10'h0
+    10      R/W     RESERVED_18                                                 1'b0
+    11      R/W     RESERVED_17                                                 1'b1
+    12      R/W     RESERVED_16                                                 1'b1
+    13      R/W     RESERVED_15                                                 1'b1
+    14      R/W     RESERVED_14                                                 1'b1
+    15      R/W     RESERVED_13                                                 1'b1
+    16      R/W     RESERVED_12                                                 1'b1
+    17      R/W     RESERVED_11                                                 1'b1
+    18      R/W     RESERVED_10                                                 1'b0
+    19      R/W     RESERVED_9                                                  1'b1
+    20      R/W     RESERVED_8                                                  1'b1
+    21      R/W     RESERVED_7                                                  1'b1
+    22      R/W     RESERVED_6                                                  1'b0
+    23      R/W     RESERVED_5                                                  1'b1
+    24      R/W     RESERVED_4                                                  1'b1
+    25      R/W     RESERVED_3                                                  1'b1
+    26      R/W     RESERVED_2                                                  1'b1
+    30:27   R/W     RESERVED_1                                                  4'b0000
+    31      R/W     RESERVED                                                    1'b1
+ */
+typedef union _AON_LOP_PON_VPON_OSC80_OSC80CG_PLL1_PCSM_1_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED_19: 10;
+        uint32_t RESERVED_18: 1;
+        uint32_t RESERVED_17: 1;
+        uint32_t RESERVED_16: 1;
+        uint32_t RESERVED_15: 1;
+        uint32_t RESERVED_14: 1;
+        uint32_t RESERVED_13: 1;
+        uint32_t RESERVED_12: 1;
+        uint32_t RESERVED_11: 1;
+        uint32_t RESERVED_10: 1;
+        uint32_t RESERVED_9: 1;
+        uint32_t RESERVED_8: 1;
+        uint32_t RESERVED_7: 1;
+        uint32_t RESERVED_6: 1;
+        uint32_t RESERVED_5: 1;
+        uint32_t RESERVED_4: 1;
+        uint32_t RESERVED_3: 1;
+        uint32_t RESERVED_2: 1;
+        uint32_t RESERVED_1: 4;
+        uint32_t RESERVED: 1;
+    };
+} AON_LOP_PON_VPON_OSC80_OSC80CG_PLL1_PCSM_1_TYPE;
+
+/*0x4000_0b14 AON_LOP_PON_VPON_OSC80_OSC80CG_PLL1_PCSM_1*/
+#define AON_LOP_PON_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_19_Pos                                                       0U
+#define AON_LOP_PON_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_19_Msk                                                       (0x3FFUL << AON_LOP_PON_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_19_Pos)
+
+#define AON_LOP_PON_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_18_Pos                                                       10U
+#define AON_LOP_PON_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_18_Msk                                                       (0x1UL << AON_LOP_PON_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_18_Pos)
+
+#define AON_LOP_PON_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_17_Pos                                                       11U
+#define AON_LOP_PON_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_17_Msk                                                       (0x1UL << AON_LOP_PON_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_17_Pos)
+
+#define AON_LOP_PON_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_16_Pos                                                       12U
+#define AON_LOP_PON_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_16_Msk                                                       (0x1UL << AON_LOP_PON_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_16_Pos)
+
+#define AON_LOP_PON_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_15_Pos                                                       13U
+#define AON_LOP_PON_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_15_Msk                                                       (0x1UL << AON_LOP_PON_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_15_Pos)
+
+#define AON_LOP_PON_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_14_Pos                                                       14U
+#define AON_LOP_PON_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_14_Msk                                                       (0x1UL << AON_LOP_PON_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_14_Pos)
+
+#define AON_LOP_PON_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_13_Pos                                                       15U
+#define AON_LOP_PON_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_13_Msk                                                       (0x1UL << AON_LOP_PON_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_13_Pos)
+
+#define AON_LOP_PON_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_12_Pos                                                       16U
+#define AON_LOP_PON_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_12_Msk                                                       (0x1UL << AON_LOP_PON_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_12_Pos)
+
+#define AON_LOP_PON_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_11_Pos                                                       17U
+#define AON_LOP_PON_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_11_Msk                                                       (0x1UL << AON_LOP_PON_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_11_Pos)
+
+#define AON_LOP_PON_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_10_Pos                                                       18U
+#define AON_LOP_PON_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_10_Msk                                                       (0x1UL << AON_LOP_PON_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_10_Pos)
+
+#define AON_LOP_PON_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_9_Pos                                                        19U
+#define AON_LOP_PON_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_9_Msk                                                        (0x1UL << AON_LOP_PON_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_9_Pos)
+
+#define AON_LOP_PON_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_8_Pos                                                        20U
+#define AON_LOP_PON_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_8_Msk                                                        (0x1UL << AON_LOP_PON_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_8_Pos)
+
+#define AON_LOP_PON_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_7_Pos                                                        21U
+#define AON_LOP_PON_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_7_Msk                                                        (0x1UL << AON_LOP_PON_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_7_Pos)
+
+#define AON_LOP_PON_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_6_Pos                                                        22U
+#define AON_LOP_PON_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_6_Msk                                                        (0x1UL << AON_LOP_PON_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_6_Pos)
+
+#define AON_LOP_PON_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_5_Pos                                                        23U
+#define AON_LOP_PON_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_5_Msk                                                        (0x1UL << AON_LOP_PON_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_5_Pos)
+
+#define AON_LOP_PON_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_4_Pos                                                        24U
+#define AON_LOP_PON_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_4_Msk                                                        (0x1UL << AON_LOP_PON_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_4_Pos)
+
+#define AON_LOP_PON_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_3_Pos                                                        25U
+#define AON_LOP_PON_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_3_Msk                                                        (0x1UL << AON_LOP_PON_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_3_Pos)
+
+#define AON_LOP_PON_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_2_Pos                                                        26U
+#define AON_LOP_PON_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_2_Msk                                                        (0x1UL << AON_LOP_PON_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_2_Pos)
+
+#define AON_LOP_PON_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_1_Pos                                                        27U
+#define AON_LOP_PON_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_1_Msk                                                        (0xFUL << AON_LOP_PON_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_1_Pos)
+
+#define AON_LOP_PON_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_Pos                                                          31U
+#define AON_LOP_PON_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_Msk                                                          (0x1UL << AON_LOP_PON_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_Pos)
+
+/* 0xB10    0x4000_0b10
+    15:0    R/W     RESERVED_4                                                  16'h0
+    19:16   R/W     RESERVED_3                                                  4'b0001
+    23:20   R/W     RESERVED_2                                                  4'b0110
+    27:24   R/W     RESERVED_1                                                  4'b0000
+    31:28   R/W     RESERVED                                                    4'b0000
+ */
+typedef union _AON_LOP_PON_VPON_OSC80_OSC80CG_PLL1_PCSM_2_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED_4: 16;
+        uint32_t RESERVED_3: 4;
+        uint32_t RESERVED_2: 4;
+        uint32_t RESERVED_1: 4;
+        uint32_t RESERVED: 4;
+    };
+} AON_LOP_PON_VPON_OSC80_OSC80CG_PLL1_PCSM_2_TYPE;
+
+/*0x4000_0b10 AON_LOP_PON_VPON_OSC80_OSC80CG_PLL1_PCSM_2*/
+#define AON_LOP_PON_VPON_OSC80_OSC80CG_PLL1_PCSM_2_RESERVED_4_Pos                                                        0U
+#define AON_LOP_PON_VPON_OSC80_OSC80CG_PLL1_PCSM_2_RESERVED_4_Msk                                                        (0xFFFFUL << AON_LOP_PON_VPON_OSC80_OSC80CG_PLL1_PCSM_2_RESERVED_4_Pos)
+
+#define AON_LOP_PON_VPON_OSC80_OSC80CG_PLL1_PCSM_2_RESERVED_3_Pos                                                        16U
+#define AON_LOP_PON_VPON_OSC80_OSC80CG_PLL1_PCSM_2_RESERVED_3_Msk                                                        (0xFUL << AON_LOP_PON_VPON_OSC80_OSC80CG_PLL1_PCSM_2_RESERVED_3_Pos)
+
+#define AON_LOP_PON_VPON_OSC80_OSC80CG_PLL1_PCSM_2_RESERVED_2_Pos                                                        20U
+#define AON_LOP_PON_VPON_OSC80_OSC80CG_PLL1_PCSM_2_RESERVED_2_Msk                                                        (0xFUL << AON_LOP_PON_VPON_OSC80_OSC80CG_PLL1_PCSM_2_RESERVED_2_Pos)
+
+#define AON_LOP_PON_VPON_OSC80_OSC80CG_PLL1_PCSM_2_RESERVED_1_Pos                                                        24U
+#define AON_LOP_PON_VPON_OSC80_OSC80CG_PLL1_PCSM_2_RESERVED_1_Msk                                                        (0xFUL << AON_LOP_PON_VPON_OSC80_OSC80CG_PLL1_PCSM_2_RESERVED_1_Pos)
+
+#define AON_LOP_PON_VPON_OSC80_OSC80CG_PLL1_PCSM_2_RESERVED_Pos                                                          28U
+#define AON_LOP_PON_VPON_OSC80_OSC80CG_PLL1_PCSM_2_RESERVED_Msk                                                          (0xFUL << AON_LOP_PON_VPON_OSC80_OSC80CG_PLL1_PCSM_2_RESERVED_Pos)
+
+/* 0xB0C    0x4000_0b0c
+    0       R/W     RESERVED_4                                                  1'b0
+    1       R/W     RESERVED_3                                                  1'b1
+    2       R/W     LOP_PON_PPU_VCORE1_PCSM_RET2N_CPU                           1'b1
+    3       R/W     LOP_PON_PPU_VCORE1_PCSM_RET2N_USB                           1'b1
+    4       R/W     LOP_PON_PPU_VCORE1_PCSM_RET2N_CAN                           1'b1
+    5       R/W     LOP_PON_PPU_VCORE1_PCSM_RET2N_LEBIS                         1'b1
+    6       R/W     LOP_PON_PPU_VCORE1_PCSM_RET2N_AUDIO                         1'b1
+    7       R/W     LOP_PON_PPU_VCORE1_PCSM_RET2N_BTPHY                         1'b1
+    8       R/W     LOP_PON_PPU_VCORE1_PCSM_RET2N_CCMP                          1'b1
+    9       R/W     LOP_PON_PPU_VCORE1_PCSM_RET2N_SNPS                          1'b1
+    10      R/W     LOP_PON_PPU_VCORE1_PCSM_RET1N_CPU                           1'b1
+    11      R/W     LOP_PON_PPU_VCORE1_PCSM_RET1N_USB                           1'b1
+    12      R/W     LOP_PON_PPU_VCORE1_PCSM_RET1N_CAN                           1'b1
+    13      R/W     LOP_PON_PPU_VCORE1_PCSM_RET1N_LEBIS                         1'b1
+    14      R/W     LOP_PON_PPU_VCORE1_PCSM_RET1N_AUDIO                         1'b1
+    15      R/W     LOP_PON_PPU_VCORE1_PCSM_RET1N_BTPHY                         1'b1
+    16      R/W     LOP_PON_PPU_VCORE1_PCSM_RET1N_CCMP                          1'b1
+    17      R/W     LOP_PON_PPU_VCORE1_PCSM_RET1N_SNPS                          1'b1
+    18      R/W     LOP_PON_PPU_VCORE1_PCSM_PGEN_CPU                            1'b0
+    19      R/W     LOP_PON_PPU_VCORE1_PCSM_PGEN_USB                            1'b0
+    20      R/W     LOP_PON_PPU_VCORE1_PCSM_PGEN_CAN                            1'b0
+    21      R/W     LOP_PON_PPU_VCORE1_PCSM_PGEN_LEBIS                          1'b0
+    22      R/W     LOP_PON_PPU_VCORE1_PCSM_PGEN_AUDIO                          1'b0
+    23      R/W     LOP_PON_PPU_VCORE1_PCSM_PGEN_BTPHY                          1'b0
+    24      R/W     LOP_PON_PPU_VCORE1_PCSM_PGEN_CCMP                           1'b0
+    25      R/W     LOP_PON_PPU_VCORE1_PCSM_PGEN_SNPS                           1'b0
+    26      R/W     LOP_PON_PPU_VCORE1_PCSM_PGEN_ROM_0                          1'b0
+    27      R/W     RESERVED_2                                                  1'b1
+    28      R/W     RESERVED_1                                                  1'b1
+    29      R/W     RESERVED                                                    1'b0
+    30      R/W     LOP_PON_PPU_VCORE1_PCSM_VCORE_PC_VG2                        1'b0
+    31      R/W     LOP_PON_PPU_VCORE1_PCSM_VCORE_PC_VG1                        1'b0
+ */
+typedef union _AON_LOP_PON_PPUVCORE1_PCSM_1_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED_4: 1;
+        uint32_t RESERVED_3: 1;
+        uint32_t LOP_PON_PPU_VCORE1_PCSM_RET2N_CPU: 1;
+        uint32_t LOP_PON_PPU_VCORE1_PCSM_RET2N_USB: 1;
+        uint32_t LOP_PON_PPU_VCORE1_PCSM_RET2N_CAN: 1;
+        uint32_t LOP_PON_PPU_VCORE1_PCSM_RET2N_LEBIS: 1;
+        uint32_t LOP_PON_PPU_VCORE1_PCSM_RET2N_AUDIO: 1;
+        uint32_t LOP_PON_PPU_VCORE1_PCSM_RET2N_BTPHY: 1;
+        uint32_t LOP_PON_PPU_VCORE1_PCSM_RET2N_CCMP: 1;
+        uint32_t LOP_PON_PPU_VCORE1_PCSM_RET2N_SNPS: 1;
+        uint32_t LOP_PON_PPU_VCORE1_PCSM_RET1N_CPU: 1;
+        uint32_t LOP_PON_PPU_VCORE1_PCSM_RET1N_USB: 1;
+        uint32_t LOP_PON_PPU_VCORE1_PCSM_RET1N_CAN: 1;
+        uint32_t LOP_PON_PPU_VCORE1_PCSM_RET1N_LEBIS: 1;
+        uint32_t LOP_PON_PPU_VCORE1_PCSM_RET1N_AUDIO: 1;
+        uint32_t LOP_PON_PPU_VCORE1_PCSM_RET1N_BTPHY: 1;
+        uint32_t LOP_PON_PPU_VCORE1_PCSM_RET1N_CCMP: 1;
+        uint32_t LOP_PON_PPU_VCORE1_PCSM_RET1N_SNPS: 1;
+        uint32_t LOP_PON_PPU_VCORE1_PCSM_PGEN_CPU: 1;
+        uint32_t LOP_PON_PPU_VCORE1_PCSM_PGEN_USB: 1;
+        uint32_t LOP_PON_PPU_VCORE1_PCSM_PGEN_CAN: 1;
+        uint32_t LOP_PON_PPU_VCORE1_PCSM_PGEN_LEBIS: 1;
+        uint32_t LOP_PON_PPU_VCORE1_PCSM_PGEN_AUDIO: 1;
+        uint32_t LOP_PON_PPU_VCORE1_PCSM_PGEN_BTPHY: 1;
+        uint32_t LOP_PON_PPU_VCORE1_PCSM_PGEN_CCMP: 1;
+        uint32_t LOP_PON_PPU_VCORE1_PCSM_PGEN_SNPS: 1;
+        uint32_t LOP_PON_PPU_VCORE1_PCSM_PGEN_ROM_0: 1;
+        uint32_t RESERVED_2: 1;
+        uint32_t RESERVED_1: 1;
+        uint32_t RESERVED: 1;
+        uint32_t LOP_PON_PPU_VCORE1_PCSM_VCORE_PC_VG2: 1;
+        uint32_t LOP_PON_PPU_VCORE1_PCSM_VCORE_PC_VG1: 1;
+    };
+} AON_LOP_PON_PPUVCORE1_PCSM_1_TYPE;
+
+/*0x4000_0b0c AON_LOP_PON_PPUVCORE1_PCSM_1*/
+#define AON_LOP_PON_PPUVCORE1_PCSM_1_RESERVED_4_Pos                                                                      0U
+#define AON_LOP_PON_PPUVCORE1_PCSM_1_RESERVED_4_Msk                                                                      (0x1UL << AON_LOP_PON_PPUVCORE1_PCSM_1_RESERVED_4_Pos)
+
+#define AON_LOP_PON_PPUVCORE1_PCSM_1_RESERVED_3_Pos                                                                      1U
+#define AON_LOP_PON_PPUVCORE1_PCSM_1_RESERVED_3_Msk                                                                      (0x1UL << AON_LOP_PON_PPUVCORE1_PCSM_1_RESERVED_3_Pos)
+
+#define AON_LOP_PON_PPUVCORE1_PCSM_1_LOP_PON_PPU_VCORE1_PCSM_RET2N_CPU_Pos                                               2U
+#define AON_LOP_PON_PPUVCORE1_PCSM_1_LOP_PON_PPU_VCORE1_PCSM_RET2N_CPU_Msk                                               (0x1UL << AON_LOP_PON_PPUVCORE1_PCSM_1_LOP_PON_PPU_VCORE1_PCSM_RET2N_CPU_Pos)
+
+#define AON_LOP_PON_PPUVCORE1_PCSM_1_LOP_PON_PPU_VCORE1_PCSM_RET2N_USB_Pos                                               3U
+#define AON_LOP_PON_PPUVCORE1_PCSM_1_LOP_PON_PPU_VCORE1_PCSM_RET2N_USB_Msk                                               (0x1UL << AON_LOP_PON_PPUVCORE1_PCSM_1_LOP_PON_PPU_VCORE1_PCSM_RET2N_USB_Pos)
+
+#define AON_LOP_PON_PPUVCORE1_PCSM_1_LOP_PON_PPU_VCORE1_PCSM_RET2N_CAN_Pos                                               4U
+#define AON_LOP_PON_PPUVCORE1_PCSM_1_LOP_PON_PPU_VCORE1_PCSM_RET2N_CAN_Msk                                               (0x1UL << AON_LOP_PON_PPUVCORE1_PCSM_1_LOP_PON_PPU_VCORE1_PCSM_RET2N_CAN_Pos)
+
+#define AON_LOP_PON_PPUVCORE1_PCSM_1_LOP_PON_PPU_VCORE1_PCSM_RET2N_LEBIS_Pos                                             5U
+#define AON_LOP_PON_PPUVCORE1_PCSM_1_LOP_PON_PPU_VCORE1_PCSM_RET2N_LEBIS_Msk                                             (0x1UL << AON_LOP_PON_PPUVCORE1_PCSM_1_LOP_PON_PPU_VCORE1_PCSM_RET2N_LEBIS_Pos)
+
+#define AON_LOP_PON_PPUVCORE1_PCSM_1_LOP_PON_PPU_VCORE1_PCSM_RET2N_AUDIO_Pos                                             6U
+#define AON_LOP_PON_PPUVCORE1_PCSM_1_LOP_PON_PPU_VCORE1_PCSM_RET2N_AUDIO_Msk                                             (0x1UL << AON_LOP_PON_PPUVCORE1_PCSM_1_LOP_PON_PPU_VCORE1_PCSM_RET2N_AUDIO_Pos)
+
+#define AON_LOP_PON_PPUVCORE1_PCSM_1_LOP_PON_PPU_VCORE1_PCSM_RET2N_BTPHY_Pos                                             7U
+#define AON_LOP_PON_PPUVCORE1_PCSM_1_LOP_PON_PPU_VCORE1_PCSM_RET2N_BTPHY_Msk                                             (0x1UL << AON_LOP_PON_PPUVCORE1_PCSM_1_LOP_PON_PPU_VCORE1_PCSM_RET2N_BTPHY_Pos)
+
+#define AON_LOP_PON_PPUVCORE1_PCSM_1_LOP_PON_PPU_VCORE1_PCSM_RET2N_CCMP_Pos                                              8U
+#define AON_LOP_PON_PPUVCORE1_PCSM_1_LOP_PON_PPU_VCORE1_PCSM_RET2N_CCMP_Msk                                              (0x1UL << AON_LOP_PON_PPUVCORE1_PCSM_1_LOP_PON_PPU_VCORE1_PCSM_RET2N_CCMP_Pos)
+
+#define AON_LOP_PON_PPUVCORE1_PCSM_1_LOP_PON_PPU_VCORE1_PCSM_RET2N_SNPS_Pos                                              9U
+#define AON_LOP_PON_PPUVCORE1_PCSM_1_LOP_PON_PPU_VCORE1_PCSM_RET2N_SNPS_Msk                                              (0x1UL << AON_LOP_PON_PPUVCORE1_PCSM_1_LOP_PON_PPU_VCORE1_PCSM_RET2N_SNPS_Pos)
+
+#define AON_LOP_PON_PPUVCORE1_PCSM_1_LOP_PON_PPU_VCORE1_PCSM_RET1N_CPU_Pos                                               10U
+#define AON_LOP_PON_PPUVCORE1_PCSM_1_LOP_PON_PPU_VCORE1_PCSM_RET1N_CPU_Msk                                               (0x1UL << AON_LOP_PON_PPUVCORE1_PCSM_1_LOP_PON_PPU_VCORE1_PCSM_RET1N_CPU_Pos)
+
+#define AON_LOP_PON_PPUVCORE1_PCSM_1_LOP_PON_PPU_VCORE1_PCSM_RET1N_USB_Pos                                               11U
+#define AON_LOP_PON_PPUVCORE1_PCSM_1_LOP_PON_PPU_VCORE1_PCSM_RET1N_USB_Msk                                               (0x1UL << AON_LOP_PON_PPUVCORE1_PCSM_1_LOP_PON_PPU_VCORE1_PCSM_RET1N_USB_Pos)
+
+#define AON_LOP_PON_PPUVCORE1_PCSM_1_LOP_PON_PPU_VCORE1_PCSM_RET1N_CAN_Pos                                               12U
+#define AON_LOP_PON_PPUVCORE1_PCSM_1_LOP_PON_PPU_VCORE1_PCSM_RET1N_CAN_Msk                                               (0x1UL << AON_LOP_PON_PPUVCORE1_PCSM_1_LOP_PON_PPU_VCORE1_PCSM_RET1N_CAN_Pos)
+
+#define AON_LOP_PON_PPUVCORE1_PCSM_1_LOP_PON_PPU_VCORE1_PCSM_RET1N_LEBIS_Pos                                             13U
+#define AON_LOP_PON_PPUVCORE1_PCSM_1_LOP_PON_PPU_VCORE1_PCSM_RET1N_LEBIS_Msk                                             (0x1UL << AON_LOP_PON_PPUVCORE1_PCSM_1_LOP_PON_PPU_VCORE1_PCSM_RET1N_LEBIS_Pos)
+
+#define AON_LOP_PON_PPUVCORE1_PCSM_1_LOP_PON_PPU_VCORE1_PCSM_RET1N_AUDIO_Pos                                             14U
+#define AON_LOP_PON_PPUVCORE1_PCSM_1_LOP_PON_PPU_VCORE1_PCSM_RET1N_AUDIO_Msk                                             (0x1UL << AON_LOP_PON_PPUVCORE1_PCSM_1_LOP_PON_PPU_VCORE1_PCSM_RET1N_AUDIO_Pos)
+
+#define AON_LOP_PON_PPUVCORE1_PCSM_1_LOP_PON_PPU_VCORE1_PCSM_RET1N_BTPHY_Pos                                             15U
+#define AON_LOP_PON_PPUVCORE1_PCSM_1_LOP_PON_PPU_VCORE1_PCSM_RET1N_BTPHY_Msk                                             (0x1UL << AON_LOP_PON_PPUVCORE1_PCSM_1_LOP_PON_PPU_VCORE1_PCSM_RET1N_BTPHY_Pos)
+
+#define AON_LOP_PON_PPUVCORE1_PCSM_1_LOP_PON_PPU_VCORE1_PCSM_RET1N_CCMP_Pos                                              16U
+#define AON_LOP_PON_PPUVCORE1_PCSM_1_LOP_PON_PPU_VCORE1_PCSM_RET1N_CCMP_Msk                                              (0x1UL << AON_LOP_PON_PPUVCORE1_PCSM_1_LOP_PON_PPU_VCORE1_PCSM_RET1N_CCMP_Pos)
+
+#define AON_LOP_PON_PPUVCORE1_PCSM_1_LOP_PON_PPU_VCORE1_PCSM_RET1N_SNPS_Pos                                              17U
+#define AON_LOP_PON_PPUVCORE1_PCSM_1_LOP_PON_PPU_VCORE1_PCSM_RET1N_SNPS_Msk                                              (0x1UL << AON_LOP_PON_PPUVCORE1_PCSM_1_LOP_PON_PPU_VCORE1_PCSM_RET1N_SNPS_Pos)
+
+#define AON_LOP_PON_PPUVCORE1_PCSM_1_LOP_PON_PPU_VCORE1_PCSM_PGEN_CPU_Pos                                                18U
+#define AON_LOP_PON_PPUVCORE1_PCSM_1_LOP_PON_PPU_VCORE1_PCSM_PGEN_CPU_Msk                                                (0x1UL << AON_LOP_PON_PPUVCORE1_PCSM_1_LOP_PON_PPU_VCORE1_PCSM_PGEN_CPU_Pos)
+
+#define AON_LOP_PON_PPUVCORE1_PCSM_1_LOP_PON_PPU_VCORE1_PCSM_PGEN_USB_Pos                                                19U
+#define AON_LOP_PON_PPUVCORE1_PCSM_1_LOP_PON_PPU_VCORE1_PCSM_PGEN_USB_Msk                                                (0x1UL << AON_LOP_PON_PPUVCORE1_PCSM_1_LOP_PON_PPU_VCORE1_PCSM_PGEN_USB_Pos)
+
+#define AON_LOP_PON_PPUVCORE1_PCSM_1_LOP_PON_PPU_VCORE1_PCSM_PGEN_CAN_Pos                                                20U
+#define AON_LOP_PON_PPUVCORE1_PCSM_1_LOP_PON_PPU_VCORE1_PCSM_PGEN_CAN_Msk                                                (0x1UL << AON_LOP_PON_PPUVCORE1_PCSM_1_LOP_PON_PPU_VCORE1_PCSM_PGEN_CAN_Pos)
+
+#define AON_LOP_PON_PPUVCORE1_PCSM_1_LOP_PON_PPU_VCORE1_PCSM_PGEN_LEBIS_Pos                                              21U
+#define AON_LOP_PON_PPUVCORE1_PCSM_1_LOP_PON_PPU_VCORE1_PCSM_PGEN_LEBIS_Msk                                              (0x1UL << AON_LOP_PON_PPUVCORE1_PCSM_1_LOP_PON_PPU_VCORE1_PCSM_PGEN_LEBIS_Pos)
+
+#define AON_LOP_PON_PPUVCORE1_PCSM_1_LOP_PON_PPU_VCORE1_PCSM_PGEN_AUDIO_Pos                                              22U
+#define AON_LOP_PON_PPUVCORE1_PCSM_1_LOP_PON_PPU_VCORE1_PCSM_PGEN_AUDIO_Msk                                              (0x1UL << AON_LOP_PON_PPUVCORE1_PCSM_1_LOP_PON_PPU_VCORE1_PCSM_PGEN_AUDIO_Pos)
+
+#define AON_LOP_PON_PPUVCORE1_PCSM_1_LOP_PON_PPU_VCORE1_PCSM_PGEN_BTPHY_Pos                                              23U
+#define AON_LOP_PON_PPUVCORE1_PCSM_1_LOP_PON_PPU_VCORE1_PCSM_PGEN_BTPHY_Msk                                              (0x1UL << AON_LOP_PON_PPUVCORE1_PCSM_1_LOP_PON_PPU_VCORE1_PCSM_PGEN_BTPHY_Pos)
+
+#define AON_LOP_PON_PPUVCORE1_PCSM_1_LOP_PON_PPU_VCORE1_PCSM_PGEN_CCMP_Pos                                               24U
+#define AON_LOP_PON_PPUVCORE1_PCSM_1_LOP_PON_PPU_VCORE1_PCSM_PGEN_CCMP_Msk                                               (0x1UL << AON_LOP_PON_PPUVCORE1_PCSM_1_LOP_PON_PPU_VCORE1_PCSM_PGEN_CCMP_Pos)
+
+#define AON_LOP_PON_PPUVCORE1_PCSM_1_LOP_PON_PPU_VCORE1_PCSM_PGEN_SNPS_Pos                                               25U
+#define AON_LOP_PON_PPUVCORE1_PCSM_1_LOP_PON_PPU_VCORE1_PCSM_PGEN_SNPS_Msk                                               (0x1UL << AON_LOP_PON_PPUVCORE1_PCSM_1_LOP_PON_PPU_VCORE1_PCSM_PGEN_SNPS_Pos)
+
+#define AON_LOP_PON_PPUVCORE1_PCSM_1_LOP_PON_PPU_VCORE1_PCSM_PGEN_ROM_0_Pos                                              26U
+#define AON_LOP_PON_PPUVCORE1_PCSM_1_LOP_PON_PPU_VCORE1_PCSM_PGEN_ROM_0_Msk                                              (0x1UL << AON_LOP_PON_PPUVCORE1_PCSM_1_LOP_PON_PPU_VCORE1_PCSM_PGEN_ROM_0_Pos)
+
+#define AON_LOP_PON_PPUVCORE1_PCSM_1_RESERVED_2_Pos                                                                      27U
+#define AON_LOP_PON_PPUVCORE1_PCSM_1_RESERVED_2_Msk                                                                      (0x1UL << AON_LOP_PON_PPUVCORE1_PCSM_1_RESERVED_2_Pos)
+
+#define AON_LOP_PON_PPUVCORE1_PCSM_1_RESERVED_1_Pos                                                                      28U
+#define AON_LOP_PON_PPUVCORE1_PCSM_1_RESERVED_1_Msk                                                                      (0x1UL << AON_LOP_PON_PPUVCORE1_PCSM_1_RESERVED_1_Pos)
+
+#define AON_LOP_PON_PPUVCORE1_PCSM_1_RESERVED_Pos                                                                        29U
+#define AON_LOP_PON_PPUVCORE1_PCSM_1_RESERVED_Msk                                                                        (0x1UL << AON_LOP_PON_PPUVCORE1_PCSM_1_RESERVED_Pos)
+
+#define AON_LOP_PON_PPUVCORE1_PCSM_1_LOP_PON_PPU_VCORE1_PCSM_VCORE_PC_VG2_Pos                                            30U
+#define AON_LOP_PON_PPUVCORE1_PCSM_1_LOP_PON_PPU_VCORE1_PCSM_VCORE_PC_VG2_Msk                                            (0x1UL << AON_LOP_PON_PPUVCORE1_PCSM_1_LOP_PON_PPU_VCORE1_PCSM_VCORE_PC_VG2_Pos)
+
+#define AON_LOP_PON_PPUVCORE1_PCSM_1_LOP_PON_PPU_VCORE1_PCSM_VCORE_PC_VG1_Pos                                            31U
+#define AON_LOP_PON_PPUVCORE1_PCSM_1_LOP_PON_PPU_VCORE1_PCSM_VCORE_PC_VG1_Msk                                            (0x1UL << AON_LOP_PON_PPUVCORE1_PCSM_1_LOP_PON_PPU_VCORE1_PCSM_VCORE_PC_VG1_Pos)
+
+/* 0xB08    0x4000_0b08
+    2:0     R/W     RESERVED_29                                                 3'h0
+    3       R/W     RESERVED_28                                                 1'b0
+    4       R/W     RESERVED_27                                                 1'b0
+    5       R/W     RESERVED_26                                                 1'b0
+    6       R/W     RESERVED_25                                                 1'b0
+    7       R/W     RESERVED_24                                                 1'b0
+    8       R/W     RESERVED_23                                                 1'b0
+    9       R/W     RESERVED_22                                                 1'b0
+    10      R/W     RESERVED_21                                                 1'b0
+    11      R/W     RESERVED_20                                                 1'b0
+    12      R/W     RESERVED_19                                                 1'b0
+    13      R/W     RESERVED_18                                                 1'b0
+    14      R/W     RESERVED_17                                                 1'b0
+    15      R/W     RESERVED_16                                                 1'b0
+    16      R/W     RESERVED_15                                                 1'b0
+    17      R/W     RESERVED_14                                                 1'b0
+    18      R/W     RESERVED_13                                                 1'b0
+    19      R/W     RESERVED_12                                                 1'b0
+    20      R/W     RESERVED_11                                                 1'b0
+    21      R/W     RESERVED_10                                                 1'b0
+    22      R/W     RESERVED_9                                                  1'b0
+    23      R/W     RESERVED_8                                                  1'b0
+    24      R/W     RESERVED_7                                                  1'b0
+    25      R/W     RESERVED_6                                                  1'b0
+    26      R/W     RESERVED_5                                                  1'b0
+    27      R/W     RESERVED_4                                                  1'b0
+    28      R/W     RESERVED_3                                                  1'b0
+    29      R/W     RESERVED_2                                                  1'b0
+    30      R/W     RESERVED_1                                                  1'b0
+    31      R/W     RESERVED                                                    1'b1
+ */
+typedef union _AON_LOP_PON_PPUVCORE1_PCSM_2_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED_29: 3;
+        uint32_t RESERVED_28: 1;
+        uint32_t RESERVED_27: 1;
+        uint32_t RESERVED_26: 1;
+        uint32_t RESERVED_25: 1;
+        uint32_t RESERVED_24: 1;
+        uint32_t RESERVED_23: 1;
+        uint32_t RESERVED_22: 1;
+        uint32_t RESERVED_21: 1;
+        uint32_t RESERVED_20: 1;
+        uint32_t RESERVED_19: 1;
+        uint32_t RESERVED_18: 1;
+        uint32_t RESERVED_17: 1;
+        uint32_t RESERVED_16: 1;
+        uint32_t RESERVED_15: 1;
+        uint32_t RESERVED_14: 1;
+        uint32_t RESERVED_13: 1;
+        uint32_t RESERVED_12: 1;
+        uint32_t RESERVED_11: 1;
+        uint32_t RESERVED_10: 1;
+        uint32_t RESERVED_9: 1;
+        uint32_t RESERVED_8: 1;
+        uint32_t RESERVED_7: 1;
+        uint32_t RESERVED_6: 1;
+        uint32_t RESERVED_5: 1;
+        uint32_t RESERVED_4: 1;
+        uint32_t RESERVED_3: 1;
+        uint32_t RESERVED_2: 1;
+        uint32_t RESERVED_1: 1;
+        uint32_t RESERVED: 1;
+    };
+} AON_LOP_PON_PPUVCORE1_PCSM_2_TYPE;
+
+/*0x4000_0b08 AON_LOP_PON_PPUVCORE1_PCSM_2*/
+#define AON_LOP_PON_PPUVCORE1_PCSM_2_RESERVED_29_Pos                                                                     0U
+#define AON_LOP_PON_PPUVCORE1_PCSM_2_RESERVED_29_Msk                                                                     (0x7UL << AON_LOP_PON_PPUVCORE1_PCSM_2_RESERVED_29_Pos)
+
+#define AON_LOP_PON_PPUVCORE1_PCSM_2_RESERVED_28_Pos                                                                     3U
+#define AON_LOP_PON_PPUVCORE1_PCSM_2_RESERVED_28_Msk                                                                     (0x1UL << AON_LOP_PON_PPUVCORE1_PCSM_2_RESERVED_28_Pos)
+
+#define AON_LOP_PON_PPUVCORE1_PCSM_2_RESERVED_27_Pos                                                                     4U
+#define AON_LOP_PON_PPUVCORE1_PCSM_2_RESERVED_27_Msk                                                                     (0x1UL << AON_LOP_PON_PPUVCORE1_PCSM_2_RESERVED_27_Pos)
+
+#define AON_LOP_PON_PPUVCORE1_PCSM_2_RESERVED_26_Pos                                                                     5U
+#define AON_LOP_PON_PPUVCORE1_PCSM_2_RESERVED_26_Msk                                                                     (0x1UL << AON_LOP_PON_PPUVCORE1_PCSM_2_RESERVED_26_Pos)
+
+#define AON_LOP_PON_PPUVCORE1_PCSM_2_RESERVED_25_Pos                                                                     6U
+#define AON_LOP_PON_PPUVCORE1_PCSM_2_RESERVED_25_Msk                                                                     (0x1UL << AON_LOP_PON_PPUVCORE1_PCSM_2_RESERVED_25_Pos)
+
+#define AON_LOP_PON_PPUVCORE1_PCSM_2_RESERVED_24_Pos                                                                     7U
+#define AON_LOP_PON_PPUVCORE1_PCSM_2_RESERVED_24_Msk                                                                     (0x1UL << AON_LOP_PON_PPUVCORE1_PCSM_2_RESERVED_24_Pos)
+
+#define AON_LOP_PON_PPUVCORE1_PCSM_2_RESERVED_23_Pos                                                                     8U
+#define AON_LOP_PON_PPUVCORE1_PCSM_2_RESERVED_23_Msk                                                                     (0x1UL << AON_LOP_PON_PPUVCORE1_PCSM_2_RESERVED_23_Pos)
+
+#define AON_LOP_PON_PPUVCORE1_PCSM_2_RESERVED_22_Pos                                                                     9U
+#define AON_LOP_PON_PPUVCORE1_PCSM_2_RESERVED_22_Msk                                                                     (0x1UL << AON_LOP_PON_PPUVCORE1_PCSM_2_RESERVED_22_Pos)
+
+#define AON_LOP_PON_PPUVCORE1_PCSM_2_RESERVED_21_Pos                                                                     10U
+#define AON_LOP_PON_PPUVCORE1_PCSM_2_RESERVED_21_Msk                                                                     (0x1UL << AON_LOP_PON_PPUVCORE1_PCSM_2_RESERVED_21_Pos)
+
+#define AON_LOP_PON_PPUVCORE1_PCSM_2_RESERVED_20_Pos                                                                     11U
+#define AON_LOP_PON_PPUVCORE1_PCSM_2_RESERVED_20_Msk                                                                     (0x1UL << AON_LOP_PON_PPUVCORE1_PCSM_2_RESERVED_20_Pos)
+
+#define AON_LOP_PON_PPUVCORE1_PCSM_2_RESERVED_19_Pos                                                                     12U
+#define AON_LOP_PON_PPUVCORE1_PCSM_2_RESERVED_19_Msk                                                                     (0x1UL << AON_LOP_PON_PPUVCORE1_PCSM_2_RESERVED_19_Pos)
+
+#define AON_LOP_PON_PPUVCORE1_PCSM_2_RESERVED_18_Pos                                                                     13U
+#define AON_LOP_PON_PPUVCORE1_PCSM_2_RESERVED_18_Msk                                                                     (0x1UL << AON_LOP_PON_PPUVCORE1_PCSM_2_RESERVED_18_Pos)
+
+#define AON_LOP_PON_PPUVCORE1_PCSM_2_RESERVED_17_Pos                                                                     14U
+#define AON_LOP_PON_PPUVCORE1_PCSM_2_RESERVED_17_Msk                                                                     (0x1UL << AON_LOP_PON_PPUVCORE1_PCSM_2_RESERVED_17_Pos)
+
+#define AON_LOP_PON_PPUVCORE1_PCSM_2_RESERVED_16_Pos                                                                     15U
+#define AON_LOP_PON_PPUVCORE1_PCSM_2_RESERVED_16_Msk                                                                     (0x1UL << AON_LOP_PON_PPUVCORE1_PCSM_2_RESERVED_16_Pos)
+
+#define AON_LOP_PON_PPUVCORE1_PCSM_2_RESERVED_15_Pos                                                                     16U
+#define AON_LOP_PON_PPUVCORE1_PCSM_2_RESERVED_15_Msk                                                                     (0x1UL << AON_LOP_PON_PPUVCORE1_PCSM_2_RESERVED_15_Pos)
+
+#define AON_LOP_PON_PPUVCORE1_PCSM_2_RESERVED_14_Pos                                                                     17U
+#define AON_LOP_PON_PPUVCORE1_PCSM_2_RESERVED_14_Msk                                                                     (0x1UL << AON_LOP_PON_PPUVCORE1_PCSM_2_RESERVED_14_Pos)
+
+#define AON_LOP_PON_PPUVCORE1_PCSM_2_RESERVED_13_Pos                                                                     18U
+#define AON_LOP_PON_PPUVCORE1_PCSM_2_RESERVED_13_Msk                                                                     (0x1UL << AON_LOP_PON_PPUVCORE1_PCSM_2_RESERVED_13_Pos)
+
+#define AON_LOP_PON_PPUVCORE1_PCSM_2_RESERVED_12_Pos                                                                     19U
+#define AON_LOP_PON_PPUVCORE1_PCSM_2_RESERVED_12_Msk                                                                     (0x1UL << AON_LOP_PON_PPUVCORE1_PCSM_2_RESERVED_12_Pos)
+
+#define AON_LOP_PON_PPUVCORE1_PCSM_2_RESERVED_11_Pos                                                                     20U
+#define AON_LOP_PON_PPUVCORE1_PCSM_2_RESERVED_11_Msk                                                                     (0x1UL << AON_LOP_PON_PPUVCORE1_PCSM_2_RESERVED_11_Pos)
+
+#define AON_LOP_PON_PPUVCORE1_PCSM_2_RESERVED_10_Pos                                                                     21U
+#define AON_LOP_PON_PPUVCORE1_PCSM_2_RESERVED_10_Msk                                                                     (0x1UL << AON_LOP_PON_PPUVCORE1_PCSM_2_RESERVED_10_Pos)
+
+#define AON_LOP_PON_PPUVCORE1_PCSM_2_RESERVED_9_Pos                                                                      22U
+#define AON_LOP_PON_PPUVCORE1_PCSM_2_RESERVED_9_Msk                                                                      (0x1UL << AON_LOP_PON_PPUVCORE1_PCSM_2_RESERVED_9_Pos)
+
+#define AON_LOP_PON_PPUVCORE1_PCSM_2_RESERVED_8_Pos                                                                      23U
+#define AON_LOP_PON_PPUVCORE1_PCSM_2_RESERVED_8_Msk                                                                      (0x1UL << AON_LOP_PON_PPUVCORE1_PCSM_2_RESERVED_8_Pos)
+
+#define AON_LOP_PON_PPUVCORE1_PCSM_2_RESERVED_7_Pos                                                                      24U
+#define AON_LOP_PON_PPUVCORE1_PCSM_2_RESERVED_7_Msk                                                                      (0x1UL << AON_LOP_PON_PPUVCORE1_PCSM_2_RESERVED_7_Pos)
+
+#define AON_LOP_PON_PPUVCORE1_PCSM_2_RESERVED_6_Pos                                                                      25U
+#define AON_LOP_PON_PPUVCORE1_PCSM_2_RESERVED_6_Msk                                                                      (0x1UL << AON_LOP_PON_PPUVCORE1_PCSM_2_RESERVED_6_Pos)
+
+#define AON_LOP_PON_PPUVCORE1_PCSM_2_RESERVED_5_Pos                                                                      26U
+#define AON_LOP_PON_PPUVCORE1_PCSM_2_RESERVED_5_Msk                                                                      (0x1UL << AON_LOP_PON_PPUVCORE1_PCSM_2_RESERVED_5_Pos)
+
+#define AON_LOP_PON_PPUVCORE1_PCSM_2_RESERVED_4_Pos                                                                      27U
+#define AON_LOP_PON_PPUVCORE1_PCSM_2_RESERVED_4_Msk                                                                      (0x1UL << AON_LOP_PON_PPUVCORE1_PCSM_2_RESERVED_4_Pos)
+
+#define AON_LOP_PON_PPUVCORE1_PCSM_2_RESERVED_3_Pos                                                                      28U
+#define AON_LOP_PON_PPUVCORE1_PCSM_2_RESERVED_3_Msk                                                                      (0x1UL << AON_LOP_PON_PPUVCORE1_PCSM_2_RESERVED_3_Pos)
+
+#define AON_LOP_PON_PPUVCORE1_PCSM_2_RESERVED_2_Pos                                                                      29U
+#define AON_LOP_PON_PPUVCORE1_PCSM_2_RESERVED_2_Msk                                                                      (0x1UL << AON_LOP_PON_PPUVCORE1_PCSM_2_RESERVED_2_Pos)
+
+#define AON_LOP_PON_PPUVCORE1_PCSM_2_RESERVED_1_Pos                                                                      30U
+#define AON_LOP_PON_PPUVCORE1_PCSM_2_RESERVED_1_Msk                                                                      (0x1UL << AON_LOP_PON_PPUVCORE1_PCSM_2_RESERVED_1_Pos)
+
+#define AON_LOP_PON_PPUVCORE1_PCSM_2_RESERVED_Pos                                                                        31U
+#define AON_LOP_PON_PPUVCORE1_PCSM_2_RESERVED_Msk                                                                        (0x1UL << AON_LOP_PON_PPUVCORE1_PCSM_2_RESERVED_Pos)
+
+/* 0xB04    0x4000_0b04
+    0       R/W     RESERVED_31                                                 1'b0
+    1       R/W     RESERVED_30                                                 1'b0
+    2       R/W     RESERVED_29                                                 1'b0
+    3       R/W     RESERVED_28                                                 1'b0
+    4       R/W     RESERVED_27                                                 1'b0
+    5       R/W     RESERVED_26                                                 1'b0
+    6       R/W     RESERVED_25                                                 1'b0
+    7       R/W     RESERVED_24                                                 1'b0
+    8       R/W     RESERVED_23                                                 1'b0
+    9       R/W     RESERVED_22                                                 1'b0
+    10      R/W     RESERVED_21                                                 1'b0
+    11      R/W     RESERVED_20                                                 1'b0
+    12      R/W     RESERVED_19                                                 1'b0
+    13      R/W     RESERVED_18                                                 1'b0
+    14      R/W     RESERVED_17                                                 1'b0
+    15      R/W     RESERVED_16                                                 1'b0
+    16      R/W     RESERVED_15                                                 1'b0
+    17      R/W     RESERVED_14                                                 1'b0
+    18      R/W     RESERVED_13                                                 1'b0
+    19      R/W     RESERVED_12                                                 1'b0
+    20      R/W     RESERVED_11                                                 1'b0
+    21      R/W     RESERVED_10                                                 1'b0
+    22      R/W     RESERVED_9                                                  1'b0
+    23      R/W     RESERVED_8                                                  1'b0
+    24      R/W     RESERVED_7                                                  1'b0
+    25      R/W     RESERVED_6                                                  1'b0
+    26      R/W     RESERVED_5                                                  1'b0
+    27      R/W     RESERVED_4                                                  1'b0
+    28      R/W     RESERVED_3                                                  1'b0
+    29      R/W     RESERVED_2                                                  1'b0
+    30      R/W     RESERVED_1                                                  1'b0
+    31      R/W     RESERVED                                                    1'b0
+ */
+typedef union _AON_LOP_PON_PPUVCORE1_PCSM_3_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED_31: 1;
+        uint32_t RESERVED_30: 1;
+        uint32_t RESERVED_29: 1;
+        uint32_t RESERVED_28: 1;
+        uint32_t RESERVED_27: 1;
+        uint32_t RESERVED_26: 1;
+        uint32_t RESERVED_25: 1;
+        uint32_t RESERVED_24: 1;
+        uint32_t RESERVED_23: 1;
+        uint32_t RESERVED_22: 1;
+        uint32_t RESERVED_21: 1;
+        uint32_t RESERVED_20: 1;
+        uint32_t RESERVED_19: 1;
+        uint32_t RESERVED_18: 1;
+        uint32_t RESERVED_17: 1;
+        uint32_t RESERVED_16: 1;
+        uint32_t RESERVED_15: 1;
+        uint32_t RESERVED_14: 1;
+        uint32_t RESERVED_13: 1;
+        uint32_t RESERVED_12: 1;
+        uint32_t RESERVED_11: 1;
+        uint32_t RESERVED_10: 1;
+        uint32_t RESERVED_9: 1;
+        uint32_t RESERVED_8: 1;
+        uint32_t RESERVED_7: 1;
+        uint32_t RESERVED_6: 1;
+        uint32_t RESERVED_5: 1;
+        uint32_t RESERVED_4: 1;
+        uint32_t RESERVED_3: 1;
+        uint32_t RESERVED_2: 1;
+        uint32_t RESERVED_1: 1;
+        uint32_t RESERVED: 1;
+    };
+} AON_LOP_PON_PPUVCORE1_PCSM_3_TYPE;
+
+/*0x4000_0b04 AON_LOP_PON_PPUVCORE1_PCSM_3*/
+#define AON_LOP_PON_PPUVCORE1_PCSM_3_RESERVED_31_Pos                                                                     0U
+#define AON_LOP_PON_PPUVCORE1_PCSM_3_RESERVED_31_Msk                                                                     (0x1UL << AON_LOP_PON_PPUVCORE1_PCSM_3_RESERVED_31_Pos)
+
+#define AON_LOP_PON_PPUVCORE1_PCSM_3_RESERVED_30_Pos                                                                     1U
+#define AON_LOP_PON_PPUVCORE1_PCSM_3_RESERVED_30_Msk                                                                     (0x1UL << AON_LOP_PON_PPUVCORE1_PCSM_3_RESERVED_30_Pos)
+
+#define AON_LOP_PON_PPUVCORE1_PCSM_3_RESERVED_29_Pos                                                                     2U
+#define AON_LOP_PON_PPUVCORE1_PCSM_3_RESERVED_29_Msk                                                                     (0x1UL << AON_LOP_PON_PPUVCORE1_PCSM_3_RESERVED_29_Pos)
+
+#define AON_LOP_PON_PPUVCORE1_PCSM_3_RESERVED_28_Pos                                                                     3U
+#define AON_LOP_PON_PPUVCORE1_PCSM_3_RESERVED_28_Msk                                                                     (0x1UL << AON_LOP_PON_PPUVCORE1_PCSM_3_RESERVED_28_Pos)
+
+#define AON_LOP_PON_PPUVCORE1_PCSM_3_RESERVED_27_Pos                                                                     4U
+#define AON_LOP_PON_PPUVCORE1_PCSM_3_RESERVED_27_Msk                                                                     (0x1UL << AON_LOP_PON_PPUVCORE1_PCSM_3_RESERVED_27_Pos)
+
+#define AON_LOP_PON_PPUVCORE1_PCSM_3_RESERVED_26_Pos                                                                     5U
+#define AON_LOP_PON_PPUVCORE1_PCSM_3_RESERVED_26_Msk                                                                     (0x1UL << AON_LOP_PON_PPUVCORE1_PCSM_3_RESERVED_26_Pos)
+
+#define AON_LOP_PON_PPUVCORE1_PCSM_3_RESERVED_25_Pos                                                                     6U
+#define AON_LOP_PON_PPUVCORE1_PCSM_3_RESERVED_25_Msk                                                                     (0x1UL << AON_LOP_PON_PPUVCORE1_PCSM_3_RESERVED_25_Pos)
+
+#define AON_LOP_PON_PPUVCORE1_PCSM_3_RESERVED_24_Pos                                                                     7U
+#define AON_LOP_PON_PPUVCORE1_PCSM_3_RESERVED_24_Msk                                                                     (0x1UL << AON_LOP_PON_PPUVCORE1_PCSM_3_RESERVED_24_Pos)
+
+#define AON_LOP_PON_PPUVCORE1_PCSM_3_RESERVED_23_Pos                                                                     8U
+#define AON_LOP_PON_PPUVCORE1_PCSM_3_RESERVED_23_Msk                                                                     (0x1UL << AON_LOP_PON_PPUVCORE1_PCSM_3_RESERVED_23_Pos)
+
+#define AON_LOP_PON_PPUVCORE1_PCSM_3_RESERVED_22_Pos                                                                     9U
+#define AON_LOP_PON_PPUVCORE1_PCSM_3_RESERVED_22_Msk                                                                     (0x1UL << AON_LOP_PON_PPUVCORE1_PCSM_3_RESERVED_22_Pos)
+
+#define AON_LOP_PON_PPUVCORE1_PCSM_3_RESERVED_21_Pos                                                                     10U
+#define AON_LOP_PON_PPUVCORE1_PCSM_3_RESERVED_21_Msk                                                                     (0x1UL << AON_LOP_PON_PPUVCORE1_PCSM_3_RESERVED_21_Pos)
+
+#define AON_LOP_PON_PPUVCORE1_PCSM_3_RESERVED_20_Pos                                                                     11U
+#define AON_LOP_PON_PPUVCORE1_PCSM_3_RESERVED_20_Msk                                                                     (0x1UL << AON_LOP_PON_PPUVCORE1_PCSM_3_RESERVED_20_Pos)
+
+#define AON_LOP_PON_PPUVCORE1_PCSM_3_RESERVED_19_Pos                                                                     12U
+#define AON_LOP_PON_PPUVCORE1_PCSM_3_RESERVED_19_Msk                                                                     (0x1UL << AON_LOP_PON_PPUVCORE1_PCSM_3_RESERVED_19_Pos)
+
+#define AON_LOP_PON_PPUVCORE1_PCSM_3_RESERVED_18_Pos                                                                     13U
+#define AON_LOP_PON_PPUVCORE1_PCSM_3_RESERVED_18_Msk                                                                     (0x1UL << AON_LOP_PON_PPUVCORE1_PCSM_3_RESERVED_18_Pos)
+
+#define AON_LOP_PON_PPUVCORE1_PCSM_3_RESERVED_17_Pos                                                                     14U
+#define AON_LOP_PON_PPUVCORE1_PCSM_3_RESERVED_17_Msk                                                                     (0x1UL << AON_LOP_PON_PPUVCORE1_PCSM_3_RESERVED_17_Pos)
+
+#define AON_LOP_PON_PPUVCORE1_PCSM_3_RESERVED_16_Pos                                                                     15U
+#define AON_LOP_PON_PPUVCORE1_PCSM_3_RESERVED_16_Msk                                                                     (0x1UL << AON_LOP_PON_PPUVCORE1_PCSM_3_RESERVED_16_Pos)
+
+#define AON_LOP_PON_PPUVCORE1_PCSM_3_RESERVED_15_Pos                                                                     16U
+#define AON_LOP_PON_PPUVCORE1_PCSM_3_RESERVED_15_Msk                                                                     (0x1UL << AON_LOP_PON_PPUVCORE1_PCSM_3_RESERVED_15_Pos)
+
+#define AON_LOP_PON_PPUVCORE1_PCSM_3_RESERVED_14_Pos                                                                     17U
+#define AON_LOP_PON_PPUVCORE1_PCSM_3_RESERVED_14_Msk                                                                     (0x1UL << AON_LOP_PON_PPUVCORE1_PCSM_3_RESERVED_14_Pos)
+
+#define AON_LOP_PON_PPUVCORE1_PCSM_3_RESERVED_13_Pos                                                                     18U
+#define AON_LOP_PON_PPUVCORE1_PCSM_3_RESERVED_13_Msk                                                                     (0x1UL << AON_LOP_PON_PPUVCORE1_PCSM_3_RESERVED_13_Pos)
+
+#define AON_LOP_PON_PPUVCORE1_PCSM_3_RESERVED_12_Pos                                                                     19U
+#define AON_LOP_PON_PPUVCORE1_PCSM_3_RESERVED_12_Msk                                                                     (0x1UL << AON_LOP_PON_PPUVCORE1_PCSM_3_RESERVED_12_Pos)
+
+#define AON_LOP_PON_PPUVCORE1_PCSM_3_RESERVED_11_Pos                                                                     20U
+#define AON_LOP_PON_PPUVCORE1_PCSM_3_RESERVED_11_Msk                                                                     (0x1UL << AON_LOP_PON_PPUVCORE1_PCSM_3_RESERVED_11_Pos)
+
+#define AON_LOP_PON_PPUVCORE1_PCSM_3_RESERVED_10_Pos                                                                     21U
+#define AON_LOP_PON_PPUVCORE1_PCSM_3_RESERVED_10_Msk                                                                     (0x1UL << AON_LOP_PON_PPUVCORE1_PCSM_3_RESERVED_10_Pos)
+
+#define AON_LOP_PON_PPUVCORE1_PCSM_3_RESERVED_9_Pos                                                                      22U
+#define AON_LOP_PON_PPUVCORE1_PCSM_3_RESERVED_9_Msk                                                                      (0x1UL << AON_LOP_PON_PPUVCORE1_PCSM_3_RESERVED_9_Pos)
+
+#define AON_LOP_PON_PPUVCORE1_PCSM_3_RESERVED_8_Pos                                                                      23U
+#define AON_LOP_PON_PPUVCORE1_PCSM_3_RESERVED_8_Msk                                                                      (0x1UL << AON_LOP_PON_PPUVCORE1_PCSM_3_RESERVED_8_Pos)
+
+#define AON_LOP_PON_PPUVCORE1_PCSM_3_RESERVED_7_Pos                                                                      24U
+#define AON_LOP_PON_PPUVCORE1_PCSM_3_RESERVED_7_Msk                                                                      (0x1UL << AON_LOP_PON_PPUVCORE1_PCSM_3_RESERVED_7_Pos)
+
+#define AON_LOP_PON_PPUVCORE1_PCSM_3_RESERVED_6_Pos                                                                      25U
+#define AON_LOP_PON_PPUVCORE1_PCSM_3_RESERVED_6_Msk                                                                      (0x1UL << AON_LOP_PON_PPUVCORE1_PCSM_3_RESERVED_6_Pos)
+
+#define AON_LOP_PON_PPUVCORE1_PCSM_3_RESERVED_5_Pos                                                                      26U
+#define AON_LOP_PON_PPUVCORE1_PCSM_3_RESERVED_5_Msk                                                                      (0x1UL << AON_LOP_PON_PPUVCORE1_PCSM_3_RESERVED_5_Pos)
+
+#define AON_LOP_PON_PPUVCORE1_PCSM_3_RESERVED_4_Pos                                                                      27U
+#define AON_LOP_PON_PPUVCORE1_PCSM_3_RESERVED_4_Msk                                                                      (0x1UL << AON_LOP_PON_PPUVCORE1_PCSM_3_RESERVED_4_Pos)
+
+#define AON_LOP_PON_PPUVCORE1_PCSM_3_RESERVED_3_Pos                                                                      28U
+#define AON_LOP_PON_PPUVCORE1_PCSM_3_RESERVED_3_Msk                                                                      (0x1UL << AON_LOP_PON_PPUVCORE1_PCSM_3_RESERVED_3_Pos)
+
+#define AON_LOP_PON_PPUVCORE1_PCSM_3_RESERVED_2_Pos                                                                      29U
+#define AON_LOP_PON_PPUVCORE1_PCSM_3_RESERVED_2_Msk                                                                      (0x1UL << AON_LOP_PON_PPUVCORE1_PCSM_3_RESERVED_2_Pos)
+
+#define AON_LOP_PON_PPUVCORE1_PCSM_3_RESERVED_1_Pos                                                                      30U
+#define AON_LOP_PON_PPUVCORE1_PCSM_3_RESERVED_1_Msk                                                                      (0x1UL << AON_LOP_PON_PPUVCORE1_PCSM_3_RESERVED_1_Pos)
+
+#define AON_LOP_PON_PPUVCORE1_PCSM_3_RESERVED_Pos                                                                        31U
+#define AON_LOP_PON_PPUVCORE1_PCSM_3_RESERVED_Msk                                                                        (0x1UL << AON_LOP_PON_PPUVCORE1_PCSM_3_RESERVED_Pos)
+
+/* 0xB00    0x4000_0b00
+    26:0    R/W     RESERVED_4                                                  27'h0
+    27      R/W     LOP_PON_PPU_VCORE1_PCSM_SRAM_SETTING_SEL                    1'b0
+    28      R/W     RESERVED_3                                                  1'b0
+    29      R/W     RESERVED_2                                                  1'b0
+    30      R/W     RESERVED_1                                                  1'b0
+    31      R/W     RESERVED                                                    1'b0
+ */
+typedef union _AON_LOP_PON_PPUVCORE1_PCSM_4_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED_4: 27;
+        uint32_t LOP_PON_PPU_VCORE1_PCSM_SRAM_SETTING_SEL: 1;
+        uint32_t RESERVED_3: 1;
+        uint32_t RESERVED_2: 1;
+        uint32_t RESERVED_1: 1;
+        uint32_t RESERVED: 1;
+    };
+} AON_LOP_PON_PPUVCORE1_PCSM_4_TYPE;
+
+/*0x4000_0b00 AON_LOP_PON_PPUVCORE1_PCSM_4*/
+#define AON_LOP_PON_PPUVCORE1_PCSM_4_RESERVED_4_Pos                                                                      0U
+#define AON_LOP_PON_PPUVCORE1_PCSM_4_RESERVED_4_Msk                                                                      (0x7FFFFFFUL << AON_LOP_PON_PPUVCORE1_PCSM_4_RESERVED_4_Pos)
+
+#define AON_LOP_PON_PPUVCORE1_PCSM_4_LOP_PON_PPU_VCORE1_PCSM_SRAM_SETTING_SEL_Pos                                        27U
+#define AON_LOP_PON_PPUVCORE1_PCSM_4_LOP_PON_PPU_VCORE1_PCSM_SRAM_SETTING_SEL_Msk                                        (0x1UL << AON_LOP_PON_PPUVCORE1_PCSM_4_LOP_PON_PPU_VCORE1_PCSM_SRAM_SETTING_SEL_Pos)
+
+#define AON_LOP_PON_PPUVCORE1_PCSM_4_RESERVED_3_Pos                                                                      28U
+#define AON_LOP_PON_PPUVCORE1_PCSM_4_RESERVED_3_Msk                                                                      (0x1UL << AON_LOP_PON_PPUVCORE1_PCSM_4_RESERVED_3_Pos)
+
+#define AON_LOP_PON_PPUVCORE1_PCSM_4_RESERVED_2_Pos                                                                      29U
+#define AON_LOP_PON_PPUVCORE1_PCSM_4_RESERVED_2_Msk                                                                      (0x1UL << AON_LOP_PON_PPUVCORE1_PCSM_4_RESERVED_2_Pos)
+
+#define AON_LOP_PON_PPUVCORE1_PCSM_4_RESERVED_1_Pos                                                                      30U
+#define AON_LOP_PON_PPUVCORE1_PCSM_4_RESERVED_1_Msk                                                                      (0x1UL << AON_LOP_PON_PPUVCORE1_PCSM_4_RESERVED_1_Pos)
+
+#define AON_LOP_PON_PPUVCORE1_PCSM_4_RESERVED_Pos                                                                        31U
+#define AON_LOP_PON_PPUVCORE1_PCSM_4_RESERVED_Msk                                                                        (0x1UL << AON_LOP_PON_PPUVCORE1_PCSM_4_RESERVED_Pos)
+
+/* 0xAFC    0x4000_0afc
+    3:0     R/W     RESERVED_7                                                  4'b0000
+    7:4     R/W     RESERVED_6                                                  4'b0001
+    11:8    R/W     RESERVED_5                                                  4'b0001
+    15:12   R/W     RESERVED_4                                                  4'b0000
+    19:16   R/W     RESERVED_3                                                  4'b0001
+    23:20   R/W     RESERVED_2                                                  4'b0000
+    27:24   R/W     RESERVED_1                                                  4'b0000
+    31:28   R/W     RESERVED                                                    4'b0000
+ */
+typedef union _AON_LOP_PON_PPUVCORE1_PCSM_DELAY_1_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED_7: 4;
+        uint32_t RESERVED_6: 4;
+        uint32_t RESERVED_5: 4;
+        uint32_t RESERVED_4: 4;
+        uint32_t RESERVED_3: 4;
+        uint32_t RESERVED_2: 4;
+        uint32_t RESERVED_1: 4;
+        uint32_t RESERVED: 4;
+    };
+} AON_LOP_PON_PPUVCORE1_PCSM_DELAY_1_TYPE;
+
+/*0x4000_0afc AON_LOP_PON_PPUVCORE1_PCSM_DELAY_1*/
+#define AON_LOP_PON_PPUVCORE1_PCSM_DELAY_1_RESERVED_7_Pos                                                                0U
+#define AON_LOP_PON_PPUVCORE1_PCSM_DELAY_1_RESERVED_7_Msk                                                                (0xFUL << AON_LOP_PON_PPUVCORE1_PCSM_DELAY_1_RESERVED_7_Pos)
+
+#define AON_LOP_PON_PPUVCORE1_PCSM_DELAY_1_RESERVED_6_Pos                                                                4U
+#define AON_LOP_PON_PPUVCORE1_PCSM_DELAY_1_RESERVED_6_Msk                                                                (0xFUL << AON_LOP_PON_PPUVCORE1_PCSM_DELAY_1_RESERVED_6_Pos)
+
+#define AON_LOP_PON_PPUVCORE1_PCSM_DELAY_1_RESERVED_5_Pos                                                                8U
+#define AON_LOP_PON_PPUVCORE1_PCSM_DELAY_1_RESERVED_5_Msk                                                                (0xFUL << AON_LOP_PON_PPUVCORE1_PCSM_DELAY_1_RESERVED_5_Pos)
+
+#define AON_LOP_PON_PPUVCORE1_PCSM_DELAY_1_RESERVED_4_Pos                                                                12U
+#define AON_LOP_PON_PPUVCORE1_PCSM_DELAY_1_RESERVED_4_Msk                                                                (0xFUL << AON_LOP_PON_PPUVCORE1_PCSM_DELAY_1_RESERVED_4_Pos)
+
+#define AON_LOP_PON_PPUVCORE1_PCSM_DELAY_1_RESERVED_3_Pos                                                                16U
+#define AON_LOP_PON_PPUVCORE1_PCSM_DELAY_1_RESERVED_3_Msk                                                                (0xFUL << AON_LOP_PON_PPUVCORE1_PCSM_DELAY_1_RESERVED_3_Pos)
+
+#define AON_LOP_PON_PPUVCORE1_PCSM_DELAY_1_RESERVED_2_Pos                                                                20U
+#define AON_LOP_PON_PPUVCORE1_PCSM_DELAY_1_RESERVED_2_Msk                                                                (0xFUL << AON_LOP_PON_PPUVCORE1_PCSM_DELAY_1_RESERVED_2_Pos)
+
+#define AON_LOP_PON_PPUVCORE1_PCSM_DELAY_1_RESERVED_1_Pos                                                                24U
+#define AON_LOP_PON_PPUVCORE1_PCSM_DELAY_1_RESERVED_1_Msk                                                                (0xFUL << AON_LOP_PON_PPUVCORE1_PCSM_DELAY_1_RESERVED_1_Pos)
+
+#define AON_LOP_PON_PPUVCORE1_PCSM_DELAY_1_RESERVED_Pos                                                                  28U
+#define AON_LOP_PON_PPUVCORE1_PCSM_DELAY_1_RESERVED_Msk                                                                  (0xFUL << AON_LOP_PON_PPUVCORE1_PCSM_DELAY_1_RESERVED_Pos)
+
+/* 0xC08    0x4000_0c08
+    4:0     R/W     RESERVED_16                                                 5'h0
+    8:5     R/W     RESERVED_15                                                 4'b0000
+    12:9    R/W     RESERVED_14                                                 4'b0000
+    16:13   R/W     RESERVED_13                                                 4'b0000
+    17      R/W     RESERVED_12                                                 1'b0
+    18      R/W     RESERVED_11                                                 1'b0
+    19      R/W     RESERVED_10                                                 1'b0
+    20      R/W     RESERVED_9                                                  1'b0
+    21      R/W     RESERVED_8                                                  1'b0
+    22      R/W     RESERVED_7                                                  1'b0
+    23      R/W     RESERVED_6                                                  1'b0
+    24      R/W     RESERVED_5                                                  1'b0
+    25      R/W     RESERVED_4                                                  1'b0
+    26      R/W     RESERVED_3                                                  1'b0
+    27      R/W     RESERVED_2                                                  1'b0
+    30:28   R/W     RESERVED_1                                                  3'b000
+    31      R/W     RESERVED                                                    1'b1
+ */
+typedef union _AON_LOP_POF_VPON_40MXTAL_PCSM_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED_16: 5;
+        uint32_t RESERVED_15: 4;
+        uint32_t RESERVED_14: 4;
+        uint32_t RESERVED_13: 4;
+        uint32_t RESERVED_12: 1;
+        uint32_t RESERVED_11: 1;
+        uint32_t RESERVED_10: 1;
+        uint32_t RESERVED_9: 1;
+        uint32_t RESERVED_8: 1;
+        uint32_t RESERVED_7: 1;
+        uint32_t RESERVED_6: 1;
+        uint32_t RESERVED_5: 1;
+        uint32_t RESERVED_4: 1;
+        uint32_t RESERVED_3: 1;
+        uint32_t RESERVED_2: 1;
+        uint32_t RESERVED_1: 3;
+        uint32_t RESERVED: 1;
+    };
+} AON_LOP_POF_VPON_40MXTAL_PCSM_TYPE;
+
+/*0x4000_0c08 AON_LOP_POF_VPON_40MXTAL_PCSM*/
+#define AON_LOP_POF_VPON_40MXTAL_PCSM_RESERVED_16_Pos                                                                    0U
+#define AON_LOP_POF_VPON_40MXTAL_PCSM_RESERVED_16_Msk                                                                    (0x1FUL << AON_LOP_POF_VPON_40MXTAL_PCSM_RESERVED_16_Pos)
+
+#define AON_LOP_POF_VPON_40MXTAL_PCSM_RESERVED_15_Pos                                                                    5U
+#define AON_LOP_POF_VPON_40MXTAL_PCSM_RESERVED_15_Msk                                                                    (0xFUL << AON_LOP_POF_VPON_40MXTAL_PCSM_RESERVED_15_Pos)
+
+#define AON_LOP_POF_VPON_40MXTAL_PCSM_RESERVED_14_Pos                                                                    9U
+#define AON_LOP_POF_VPON_40MXTAL_PCSM_RESERVED_14_Msk                                                                    (0xFUL << AON_LOP_POF_VPON_40MXTAL_PCSM_RESERVED_14_Pos)
+
+#define AON_LOP_POF_VPON_40MXTAL_PCSM_RESERVED_13_Pos                                                                    13U
+#define AON_LOP_POF_VPON_40MXTAL_PCSM_RESERVED_13_Msk                                                                    (0xFUL << AON_LOP_POF_VPON_40MXTAL_PCSM_RESERVED_13_Pos)
+
+#define AON_LOP_POF_VPON_40MXTAL_PCSM_RESERVED_12_Pos                                                                    17U
+#define AON_LOP_POF_VPON_40MXTAL_PCSM_RESERVED_12_Msk                                                                    (0x1UL << AON_LOP_POF_VPON_40MXTAL_PCSM_RESERVED_12_Pos)
+
+#define AON_LOP_POF_VPON_40MXTAL_PCSM_RESERVED_11_Pos                                                                    18U
+#define AON_LOP_POF_VPON_40MXTAL_PCSM_RESERVED_11_Msk                                                                    (0x1UL << AON_LOP_POF_VPON_40MXTAL_PCSM_RESERVED_11_Pos)
+
+#define AON_LOP_POF_VPON_40MXTAL_PCSM_RESERVED_10_Pos                                                                    19U
+#define AON_LOP_POF_VPON_40MXTAL_PCSM_RESERVED_10_Msk                                                                    (0x1UL << AON_LOP_POF_VPON_40MXTAL_PCSM_RESERVED_10_Pos)
+
+#define AON_LOP_POF_VPON_40MXTAL_PCSM_RESERVED_9_Pos                                                                     20U
+#define AON_LOP_POF_VPON_40MXTAL_PCSM_RESERVED_9_Msk                                                                     (0x1UL << AON_LOP_POF_VPON_40MXTAL_PCSM_RESERVED_9_Pos)
+
+#define AON_LOP_POF_VPON_40MXTAL_PCSM_RESERVED_8_Pos                                                                     21U
+#define AON_LOP_POF_VPON_40MXTAL_PCSM_RESERVED_8_Msk                                                                     (0x1UL << AON_LOP_POF_VPON_40MXTAL_PCSM_RESERVED_8_Pos)
+
+#define AON_LOP_POF_VPON_40MXTAL_PCSM_RESERVED_7_Pos                                                                     22U
+#define AON_LOP_POF_VPON_40MXTAL_PCSM_RESERVED_7_Msk                                                                     (0x1UL << AON_LOP_POF_VPON_40MXTAL_PCSM_RESERVED_7_Pos)
+
+#define AON_LOP_POF_VPON_40MXTAL_PCSM_RESERVED_6_Pos                                                                     23U
+#define AON_LOP_POF_VPON_40MXTAL_PCSM_RESERVED_6_Msk                                                                     (0x1UL << AON_LOP_POF_VPON_40MXTAL_PCSM_RESERVED_6_Pos)
+
+#define AON_LOP_POF_VPON_40MXTAL_PCSM_RESERVED_5_Pos                                                                     24U
+#define AON_LOP_POF_VPON_40MXTAL_PCSM_RESERVED_5_Msk                                                                     (0x1UL << AON_LOP_POF_VPON_40MXTAL_PCSM_RESERVED_5_Pos)
+
+#define AON_LOP_POF_VPON_40MXTAL_PCSM_RESERVED_4_Pos                                                                     25U
+#define AON_LOP_POF_VPON_40MXTAL_PCSM_RESERVED_4_Msk                                                                     (0x1UL << AON_LOP_POF_VPON_40MXTAL_PCSM_RESERVED_4_Pos)
+
+#define AON_LOP_POF_VPON_40MXTAL_PCSM_RESERVED_3_Pos                                                                     26U
+#define AON_LOP_POF_VPON_40MXTAL_PCSM_RESERVED_3_Msk                                                                     (0x1UL << AON_LOP_POF_VPON_40MXTAL_PCSM_RESERVED_3_Pos)
+
+#define AON_LOP_POF_VPON_40MXTAL_PCSM_RESERVED_2_Pos                                                                     27U
+#define AON_LOP_POF_VPON_40MXTAL_PCSM_RESERVED_2_Msk                                                                     (0x1UL << AON_LOP_POF_VPON_40MXTAL_PCSM_RESERVED_2_Pos)
+
+#define AON_LOP_POF_VPON_40MXTAL_PCSM_RESERVED_1_Pos                                                                     28U
+#define AON_LOP_POF_VPON_40MXTAL_PCSM_RESERVED_1_Msk                                                                     (0x7UL << AON_LOP_POF_VPON_40MXTAL_PCSM_RESERVED_1_Pos)
+
+#define AON_LOP_POF_VPON_40MXTAL_PCSM_RESERVED_Pos                                                                       31U
+#define AON_LOP_POF_VPON_40MXTAL_PCSM_RESERVED_Msk                                                                       (0x1UL << AON_LOP_POF_VPON_40MXTAL_PCSM_RESERVED_Pos)
+
+/* 0xC04    0x4000_0c04
+    9:0     R/W     RESERVED_19                                                 10'h0
+    10      R/W     RESERVED_18                                                 1'b1
+    11      R/W     RESERVED_17                                                 1'b1
+    12      R/W     RESERVED_16                                                 1'b1
+    13      R/W     RESERVED_15                                                 1'b1
+    14      R/W     RESERVED_14                                                 1'b1
+    15      R/W     RESERVED_13                                                 1'b0
+    16      R/W     RESERVED_12                                                 1'b0
+    17      R/W     RESERVED_11                                                 1'b0
+    18      R/W     RESERVED_10                                                 1'b0
+    19      R/W     RESERVED_9                                                  1'b0
+    20      R/W     RESERVED_8                                                  1'b0
+    21      R/W     RESERVED_7                                                  1'b0
+    22      R/W     RESERVED_6                                                  1'b0
+    23      R/W     RESERVED_5                                                  1'b0
+    24      R/W     RESERVED_4                                                  1'b0
+    25      R/W     RESERVED_3                                                  1'b0
+    26      R/W     RESERVED_2                                                  1'b0
+    30:27   R/W     RESERVED_1                                                  4'b0000
+    31      R/W     RESERVED                                                    1'b0
+ */
+typedef union _AON_LOP_POF_VPON_OSC80_OSC80CG_PLL1_PCSM_1_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED_19: 10;
+        uint32_t RESERVED_18: 1;
+        uint32_t RESERVED_17: 1;
+        uint32_t RESERVED_16: 1;
+        uint32_t RESERVED_15: 1;
+        uint32_t RESERVED_14: 1;
+        uint32_t RESERVED_13: 1;
+        uint32_t RESERVED_12: 1;
+        uint32_t RESERVED_11: 1;
+        uint32_t RESERVED_10: 1;
+        uint32_t RESERVED_9: 1;
+        uint32_t RESERVED_8: 1;
+        uint32_t RESERVED_7: 1;
+        uint32_t RESERVED_6: 1;
+        uint32_t RESERVED_5: 1;
+        uint32_t RESERVED_4: 1;
+        uint32_t RESERVED_3: 1;
+        uint32_t RESERVED_2: 1;
+        uint32_t RESERVED_1: 4;
+        uint32_t RESERVED: 1;
+    };
+} AON_LOP_POF_VPON_OSC80_OSC80CG_PLL1_PCSM_1_TYPE;
+
+/*0x4000_0c04 AON_LOP_POF_VPON_OSC80_OSC80CG_PLL1_PCSM_1*/
+#define AON_LOP_POF_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_19_Pos                                                       0U
+#define AON_LOP_POF_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_19_Msk                                                       (0x3FFUL << AON_LOP_POF_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_19_Pos)
+
+#define AON_LOP_POF_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_18_Pos                                                       10U
+#define AON_LOP_POF_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_18_Msk                                                       (0x1UL << AON_LOP_POF_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_18_Pos)
+
+#define AON_LOP_POF_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_17_Pos                                                       11U
+#define AON_LOP_POF_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_17_Msk                                                       (0x1UL << AON_LOP_POF_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_17_Pos)
+
+#define AON_LOP_POF_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_16_Pos                                                       12U
+#define AON_LOP_POF_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_16_Msk                                                       (0x1UL << AON_LOP_POF_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_16_Pos)
+
+#define AON_LOP_POF_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_15_Pos                                                       13U
+#define AON_LOP_POF_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_15_Msk                                                       (0x1UL << AON_LOP_POF_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_15_Pos)
+
+#define AON_LOP_POF_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_14_Pos                                                       14U
+#define AON_LOP_POF_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_14_Msk                                                       (0x1UL << AON_LOP_POF_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_14_Pos)
+
+#define AON_LOP_POF_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_13_Pos                                                       15U
+#define AON_LOP_POF_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_13_Msk                                                       (0x1UL << AON_LOP_POF_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_13_Pos)
+
+#define AON_LOP_POF_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_12_Pos                                                       16U
+#define AON_LOP_POF_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_12_Msk                                                       (0x1UL << AON_LOP_POF_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_12_Pos)
+
+#define AON_LOP_POF_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_11_Pos                                                       17U
+#define AON_LOP_POF_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_11_Msk                                                       (0x1UL << AON_LOP_POF_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_11_Pos)
+
+#define AON_LOP_POF_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_10_Pos                                                       18U
+#define AON_LOP_POF_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_10_Msk                                                       (0x1UL << AON_LOP_POF_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_10_Pos)
+
+#define AON_LOP_POF_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_9_Pos                                                        19U
+#define AON_LOP_POF_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_9_Msk                                                        (0x1UL << AON_LOP_POF_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_9_Pos)
+
+#define AON_LOP_POF_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_8_Pos                                                        20U
+#define AON_LOP_POF_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_8_Msk                                                        (0x1UL << AON_LOP_POF_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_8_Pos)
+
+#define AON_LOP_POF_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_7_Pos                                                        21U
+#define AON_LOP_POF_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_7_Msk                                                        (0x1UL << AON_LOP_POF_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_7_Pos)
+
+#define AON_LOP_POF_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_6_Pos                                                        22U
+#define AON_LOP_POF_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_6_Msk                                                        (0x1UL << AON_LOP_POF_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_6_Pos)
+
+#define AON_LOP_POF_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_5_Pos                                                        23U
+#define AON_LOP_POF_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_5_Msk                                                        (0x1UL << AON_LOP_POF_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_5_Pos)
+
+#define AON_LOP_POF_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_4_Pos                                                        24U
+#define AON_LOP_POF_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_4_Msk                                                        (0x1UL << AON_LOP_POF_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_4_Pos)
+
+#define AON_LOP_POF_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_3_Pos                                                        25U
+#define AON_LOP_POF_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_3_Msk                                                        (0x1UL << AON_LOP_POF_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_3_Pos)
+
+#define AON_LOP_POF_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_2_Pos                                                        26U
+#define AON_LOP_POF_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_2_Msk                                                        (0x1UL << AON_LOP_POF_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_2_Pos)
+
+#define AON_LOP_POF_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_1_Pos                                                        27U
+#define AON_LOP_POF_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_1_Msk                                                        (0xFUL << AON_LOP_POF_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_1_Pos)
+
+#define AON_LOP_POF_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_Pos                                                          31U
+#define AON_LOP_POF_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_Msk                                                          (0x1UL << AON_LOP_POF_VPON_OSC80_OSC80CG_PLL1_PCSM_1_RESERVED_Pos)
+
+/* 0xC00    0x4000_0c00
+    15:0    R/W     RESERVED_4                                                  16'h0
+    19:16   R/W     RESERVED_3                                                  4'b0000
+    23:20   R/W     RESERVED_2                                                  4'b0000
+    27:24   R/W     RESERVED_1                                                  4'b0000
+    31:28   R/W     RESERVED                                                    4'b0000
+ */
+typedef union _AON_LOP_POF_VPON_OSC80_OSC80CG_PLL1_PCSM_2_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED_4: 16;
+        uint32_t RESERVED_3: 4;
+        uint32_t RESERVED_2: 4;
+        uint32_t RESERVED_1: 4;
+        uint32_t RESERVED: 4;
+    };
+} AON_LOP_POF_VPON_OSC80_OSC80CG_PLL1_PCSM_2_TYPE;
+
+/*0x4000_0c00 AON_LOP_POF_VPON_OSC80_OSC80CG_PLL1_PCSM_2*/
+#define AON_LOP_POF_VPON_OSC80_OSC80CG_PLL1_PCSM_2_RESERVED_4_Pos                                                        0U
+#define AON_LOP_POF_VPON_OSC80_OSC80CG_PLL1_PCSM_2_RESERVED_4_Msk                                                        (0xFFFFUL << AON_LOP_POF_VPON_OSC80_OSC80CG_PLL1_PCSM_2_RESERVED_4_Pos)
+
+#define AON_LOP_POF_VPON_OSC80_OSC80CG_PLL1_PCSM_2_RESERVED_3_Pos                                                        16U
+#define AON_LOP_POF_VPON_OSC80_OSC80CG_PLL1_PCSM_2_RESERVED_3_Msk                                                        (0xFUL << AON_LOP_POF_VPON_OSC80_OSC80CG_PLL1_PCSM_2_RESERVED_3_Pos)
+
+#define AON_LOP_POF_VPON_OSC80_OSC80CG_PLL1_PCSM_2_RESERVED_2_Pos                                                        20U
+#define AON_LOP_POF_VPON_OSC80_OSC80CG_PLL1_PCSM_2_RESERVED_2_Msk                                                        (0xFUL << AON_LOP_POF_VPON_OSC80_OSC80CG_PLL1_PCSM_2_RESERVED_2_Pos)
+
+#define AON_LOP_POF_VPON_OSC80_OSC80CG_PLL1_PCSM_2_RESERVED_1_Pos                                                        24U
+#define AON_LOP_POF_VPON_OSC80_OSC80CG_PLL1_PCSM_2_RESERVED_1_Msk                                                        (0xFUL << AON_LOP_POF_VPON_OSC80_OSC80CG_PLL1_PCSM_2_RESERVED_1_Pos)
+
+#define AON_LOP_POF_VPON_OSC80_OSC80CG_PLL1_PCSM_2_RESERVED_Pos                                                          28U
+#define AON_LOP_POF_VPON_OSC80_OSC80CG_PLL1_PCSM_2_RESERVED_Msk                                                          (0xFUL << AON_LOP_POF_VPON_OSC80_OSC80CG_PLL1_PCSM_2_RESERVED_Pos)
+
+/* 0xBFC    0x4000_0bfc
+    0       R/W     RESERVED_4                                                  1'b0
+    1       R/W     RESERVED_3                                                  1'b0
+    2       R/W     LOP_POF_OFF_PPU_VCORE1_PCSM_RET2N_CPU                       1'b1
+    3       R/W     LOP_POF_OFF_PPU_VCORE1_PCSM_RET2N_USB                       1'b1
+    4       R/W     LOP_POF_OFF_PPU_VCORE1_PCSM_RET2N_CAN                       1'b1
+    5       R/W     LOP_POF_OFF_PPU_VCORE1_PCSM_RET2N_LEBIS                     1'b1
+    6       R/W     LOP_POF_OFF_PPU_VCORE1_PCSM_RET2N_AUDIO                     1'b1
+    7       R/W     LOP_POF_OFF_PPU_VCORE1_PCSM_RET2N_BTPHY                     1'b1
+    8       R/W     LOP_POF_OFF_PPU_VCORE1_PCSM_RET2N_CCMP                      1'b1
+    9       R/W     LOP_POF_OFF_PPU_VCORE1_PCSM_RET2N_SNPS                      1'b1
+    10      R/W     LOP_POF_OFF_PPU_VCORE1_PCSM_RET1N_CPU                       1'b1
+    11      R/W     LOP_POF_OFF_PPU_VCORE1_PCSM_RET1N_USB                       1'b1
+    12      R/W     LOP_POF_OFF_PPU_VCORE1_PCSM_RET1N_CAN                       1'b1
+    13      R/W     LOP_POF_OFF_PPU_VCORE1_PCSM_RET1N_LEBIS                     1'b1
+    14      R/W     LOP_POF_OFF_PPU_VCORE1_PCSM_RET1N_AUDIO                     1'b1
+    15      R/W     LOP_POF_OFF_PPU_VCORE1_PCSM_RET1N_BTPHY                     1'b1
+    16      R/W     LOP_POF_OFF_PPU_VCORE1_PCSM_RET1N_CCMP                      1'b1
+    17      R/W     LOP_POF_OFF_PPU_VCORE1_PCSM_RET1N_SNPS                      1'b1
+    18      R/W     LOP_POF_OFF_PPU_VCORE1_PCSM_PGEN_CPU                        1'b1
+    19      R/W     LOP_POF_OFF_PPU_VCORE1_PCSM_PGEN_USB                        1'b1
+    20      R/W     LOP_POF_OFF_PPU_VCORE1_PCSM_PGEN_CAN                        1'b1
+    21      R/W     LOP_POF_OFF_PPU_VCORE1_PCSM_PGEN_LEBIS                      1'b1
+    22      R/W     LOP_POF_OFF_PPU_VCORE1_PCSM_PGEN_AUDIO                      1'b1
+    23      R/W     LOP_POF_OFF_PPU_VCORE1_PCSM_PGEN_BTPHY                      1'b1
+    24      R/W     LOP_POF_OFF_PPU_VCORE1_PCSM_PGEN_CCMP                       1'b1
+    25      R/W     LOP_POF_OFF_PPU_VCORE1_PCSM_PGEN_SNPS                       1'b1
+    26      R/W     LOP_POF_OFF_PPU_VCORE1_PCSM_PGEN_ROM_0                      1'b1
+    27      R/W     RESERVED_2                                                  1'b0
+    28      R/W     RESERVED_1                                                  1'b0
+    29      R/W     RESERVED                                                    1'b1
+    30      R/W     LOP_POF_OFF_PPU_VCORE1_PCSM_VCORE_PC_VG2                    1'b1
+    31      R/W     LOP_POF_OFF_PPU_VCORE1_PCSM_VCORE_PC_VG1                    1'b1
+ */
+typedef union _AON_LOP_POF_OFF_PPU_VCORE1_PCSM_1_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED_4: 1;
+        uint32_t RESERVED_3: 1;
+        uint32_t LOP_POF_OFF_PPU_VCORE1_PCSM_RET2N_CPU: 1;
+        uint32_t LOP_POF_OFF_PPU_VCORE1_PCSM_RET2N_USB: 1;
+        uint32_t LOP_POF_OFF_PPU_VCORE1_PCSM_RET2N_CAN: 1;
+        uint32_t LOP_POF_OFF_PPU_VCORE1_PCSM_RET2N_LEBIS: 1;
+        uint32_t LOP_POF_OFF_PPU_VCORE1_PCSM_RET2N_AUDIO: 1;
+        uint32_t LOP_POF_OFF_PPU_VCORE1_PCSM_RET2N_BTPHY: 1;
+        uint32_t LOP_POF_OFF_PPU_VCORE1_PCSM_RET2N_CCMP: 1;
+        uint32_t LOP_POF_OFF_PPU_VCORE1_PCSM_RET2N_SNPS: 1;
+        uint32_t LOP_POF_OFF_PPU_VCORE1_PCSM_RET1N_CPU: 1;
+        uint32_t LOP_POF_OFF_PPU_VCORE1_PCSM_RET1N_USB: 1;
+        uint32_t LOP_POF_OFF_PPU_VCORE1_PCSM_RET1N_CAN: 1;
+        uint32_t LOP_POF_OFF_PPU_VCORE1_PCSM_RET1N_LEBIS: 1;
+        uint32_t LOP_POF_OFF_PPU_VCORE1_PCSM_RET1N_AUDIO: 1;
+        uint32_t LOP_POF_OFF_PPU_VCORE1_PCSM_RET1N_BTPHY: 1;
+        uint32_t LOP_POF_OFF_PPU_VCORE1_PCSM_RET1N_CCMP: 1;
+        uint32_t LOP_POF_OFF_PPU_VCORE1_PCSM_RET1N_SNPS: 1;
+        uint32_t LOP_POF_OFF_PPU_VCORE1_PCSM_PGEN_CPU: 1;
+        uint32_t LOP_POF_OFF_PPU_VCORE1_PCSM_PGEN_USB: 1;
+        uint32_t LOP_POF_OFF_PPU_VCORE1_PCSM_PGEN_CAN: 1;
+        uint32_t LOP_POF_OFF_PPU_VCORE1_PCSM_PGEN_LEBIS: 1;
+        uint32_t LOP_POF_OFF_PPU_VCORE1_PCSM_PGEN_AUDIO: 1;
+        uint32_t LOP_POF_OFF_PPU_VCORE1_PCSM_PGEN_BTPHY: 1;
+        uint32_t LOP_POF_OFF_PPU_VCORE1_PCSM_PGEN_CCMP: 1;
+        uint32_t LOP_POF_OFF_PPU_VCORE1_PCSM_PGEN_SNPS: 1;
+        uint32_t LOP_POF_OFF_PPU_VCORE1_PCSM_PGEN_ROM_0: 1;
+        uint32_t RESERVED_2: 1;
+        uint32_t RESERVED_1: 1;
+        uint32_t RESERVED: 1;
+        uint32_t LOP_POF_OFF_PPU_VCORE1_PCSM_VCORE_PC_VG2: 1;
+        uint32_t LOP_POF_OFF_PPU_VCORE1_PCSM_VCORE_PC_VG1: 1;
+    };
+} AON_LOP_POF_OFF_PPU_VCORE1_PCSM_1_TYPE;
+
+/*0x4000_0bfc AON_LOP_POF_OFF_PPU_VCORE1_PCSM_1*/
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_1_RESERVED_4_Pos                                                                 0U
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_1_RESERVED_4_Msk                                                                 (0x1UL << AON_LOP_POF_OFF_PPU_VCORE1_PCSM_1_RESERVED_4_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_1_RESERVED_3_Pos                                                                 1U
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_1_RESERVED_3_Msk                                                                 (0x1UL << AON_LOP_POF_OFF_PPU_VCORE1_PCSM_1_RESERVED_3_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_1_LOP_POF_OFF_PPU_VCORE1_PCSM_RET2N_CPU_Pos                                      2U
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_1_LOP_POF_OFF_PPU_VCORE1_PCSM_RET2N_CPU_Msk                                      (0x1UL << AON_LOP_POF_OFF_PPU_VCORE1_PCSM_1_LOP_POF_OFF_PPU_VCORE1_PCSM_RET2N_CPU_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_1_LOP_POF_OFF_PPU_VCORE1_PCSM_RET2N_USB_Pos                                      3U
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_1_LOP_POF_OFF_PPU_VCORE1_PCSM_RET2N_USB_Msk                                      (0x1UL << AON_LOP_POF_OFF_PPU_VCORE1_PCSM_1_LOP_POF_OFF_PPU_VCORE1_PCSM_RET2N_USB_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_1_LOP_POF_OFF_PPU_VCORE1_PCSM_RET2N_CAN_Pos                                      4U
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_1_LOP_POF_OFF_PPU_VCORE1_PCSM_RET2N_CAN_Msk                                      (0x1UL << AON_LOP_POF_OFF_PPU_VCORE1_PCSM_1_LOP_POF_OFF_PPU_VCORE1_PCSM_RET2N_CAN_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_1_LOP_POF_OFF_PPU_VCORE1_PCSM_RET2N_LEBIS_Pos                                    5U
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_1_LOP_POF_OFF_PPU_VCORE1_PCSM_RET2N_LEBIS_Msk                                    (0x1UL << AON_LOP_POF_OFF_PPU_VCORE1_PCSM_1_LOP_POF_OFF_PPU_VCORE1_PCSM_RET2N_LEBIS_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_1_LOP_POF_OFF_PPU_VCORE1_PCSM_RET2N_AUDIO_Pos                                    6U
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_1_LOP_POF_OFF_PPU_VCORE1_PCSM_RET2N_AUDIO_Msk                                    (0x1UL << AON_LOP_POF_OFF_PPU_VCORE1_PCSM_1_LOP_POF_OFF_PPU_VCORE1_PCSM_RET2N_AUDIO_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_1_LOP_POF_OFF_PPU_VCORE1_PCSM_RET2N_BTPHY_Pos                                    7U
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_1_LOP_POF_OFF_PPU_VCORE1_PCSM_RET2N_BTPHY_Msk                                    (0x1UL << AON_LOP_POF_OFF_PPU_VCORE1_PCSM_1_LOP_POF_OFF_PPU_VCORE1_PCSM_RET2N_BTPHY_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_1_LOP_POF_OFF_PPU_VCORE1_PCSM_RET2N_CCMP_Pos                                     8U
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_1_LOP_POF_OFF_PPU_VCORE1_PCSM_RET2N_CCMP_Msk                                     (0x1UL << AON_LOP_POF_OFF_PPU_VCORE1_PCSM_1_LOP_POF_OFF_PPU_VCORE1_PCSM_RET2N_CCMP_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_1_LOP_POF_OFF_PPU_VCORE1_PCSM_RET2N_SNPS_Pos                                     9U
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_1_LOP_POF_OFF_PPU_VCORE1_PCSM_RET2N_SNPS_Msk                                     (0x1UL << AON_LOP_POF_OFF_PPU_VCORE1_PCSM_1_LOP_POF_OFF_PPU_VCORE1_PCSM_RET2N_SNPS_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_1_LOP_POF_OFF_PPU_VCORE1_PCSM_RET1N_CPU_Pos                                      10U
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_1_LOP_POF_OFF_PPU_VCORE1_PCSM_RET1N_CPU_Msk                                      (0x1UL << AON_LOP_POF_OFF_PPU_VCORE1_PCSM_1_LOP_POF_OFF_PPU_VCORE1_PCSM_RET1N_CPU_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_1_LOP_POF_OFF_PPU_VCORE1_PCSM_RET1N_USB_Pos                                      11U
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_1_LOP_POF_OFF_PPU_VCORE1_PCSM_RET1N_USB_Msk                                      (0x1UL << AON_LOP_POF_OFF_PPU_VCORE1_PCSM_1_LOP_POF_OFF_PPU_VCORE1_PCSM_RET1N_USB_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_1_LOP_POF_OFF_PPU_VCORE1_PCSM_RET1N_CAN_Pos                                      12U
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_1_LOP_POF_OFF_PPU_VCORE1_PCSM_RET1N_CAN_Msk                                      (0x1UL << AON_LOP_POF_OFF_PPU_VCORE1_PCSM_1_LOP_POF_OFF_PPU_VCORE1_PCSM_RET1N_CAN_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_1_LOP_POF_OFF_PPU_VCORE1_PCSM_RET1N_LEBIS_Pos                                    13U
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_1_LOP_POF_OFF_PPU_VCORE1_PCSM_RET1N_LEBIS_Msk                                    (0x1UL << AON_LOP_POF_OFF_PPU_VCORE1_PCSM_1_LOP_POF_OFF_PPU_VCORE1_PCSM_RET1N_LEBIS_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_1_LOP_POF_OFF_PPU_VCORE1_PCSM_RET1N_AUDIO_Pos                                    14U
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_1_LOP_POF_OFF_PPU_VCORE1_PCSM_RET1N_AUDIO_Msk                                    (0x1UL << AON_LOP_POF_OFF_PPU_VCORE1_PCSM_1_LOP_POF_OFF_PPU_VCORE1_PCSM_RET1N_AUDIO_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_1_LOP_POF_OFF_PPU_VCORE1_PCSM_RET1N_BTPHY_Pos                                    15U
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_1_LOP_POF_OFF_PPU_VCORE1_PCSM_RET1N_BTPHY_Msk                                    (0x1UL << AON_LOP_POF_OFF_PPU_VCORE1_PCSM_1_LOP_POF_OFF_PPU_VCORE1_PCSM_RET1N_BTPHY_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_1_LOP_POF_OFF_PPU_VCORE1_PCSM_RET1N_CCMP_Pos                                     16U
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_1_LOP_POF_OFF_PPU_VCORE1_PCSM_RET1N_CCMP_Msk                                     (0x1UL << AON_LOP_POF_OFF_PPU_VCORE1_PCSM_1_LOP_POF_OFF_PPU_VCORE1_PCSM_RET1N_CCMP_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_1_LOP_POF_OFF_PPU_VCORE1_PCSM_RET1N_SNPS_Pos                                     17U
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_1_LOP_POF_OFF_PPU_VCORE1_PCSM_RET1N_SNPS_Msk                                     (0x1UL << AON_LOP_POF_OFF_PPU_VCORE1_PCSM_1_LOP_POF_OFF_PPU_VCORE1_PCSM_RET1N_SNPS_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_1_LOP_POF_OFF_PPU_VCORE1_PCSM_PGEN_CPU_Pos                                       18U
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_1_LOP_POF_OFF_PPU_VCORE1_PCSM_PGEN_CPU_Msk                                       (0x1UL << AON_LOP_POF_OFF_PPU_VCORE1_PCSM_1_LOP_POF_OFF_PPU_VCORE1_PCSM_PGEN_CPU_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_1_LOP_POF_OFF_PPU_VCORE1_PCSM_PGEN_USB_Pos                                       19U
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_1_LOP_POF_OFF_PPU_VCORE1_PCSM_PGEN_USB_Msk                                       (0x1UL << AON_LOP_POF_OFF_PPU_VCORE1_PCSM_1_LOP_POF_OFF_PPU_VCORE1_PCSM_PGEN_USB_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_1_LOP_POF_OFF_PPU_VCORE1_PCSM_PGEN_CAN_Pos                                       20U
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_1_LOP_POF_OFF_PPU_VCORE1_PCSM_PGEN_CAN_Msk                                       (0x1UL << AON_LOP_POF_OFF_PPU_VCORE1_PCSM_1_LOP_POF_OFF_PPU_VCORE1_PCSM_PGEN_CAN_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_1_LOP_POF_OFF_PPU_VCORE1_PCSM_PGEN_LEBIS_Pos                                     21U
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_1_LOP_POF_OFF_PPU_VCORE1_PCSM_PGEN_LEBIS_Msk                                     (0x1UL << AON_LOP_POF_OFF_PPU_VCORE1_PCSM_1_LOP_POF_OFF_PPU_VCORE1_PCSM_PGEN_LEBIS_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_1_LOP_POF_OFF_PPU_VCORE1_PCSM_PGEN_AUDIO_Pos                                     22U
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_1_LOP_POF_OFF_PPU_VCORE1_PCSM_PGEN_AUDIO_Msk                                     (0x1UL << AON_LOP_POF_OFF_PPU_VCORE1_PCSM_1_LOP_POF_OFF_PPU_VCORE1_PCSM_PGEN_AUDIO_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_1_LOP_POF_OFF_PPU_VCORE1_PCSM_PGEN_BTPHY_Pos                                     23U
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_1_LOP_POF_OFF_PPU_VCORE1_PCSM_PGEN_BTPHY_Msk                                     (0x1UL << AON_LOP_POF_OFF_PPU_VCORE1_PCSM_1_LOP_POF_OFF_PPU_VCORE1_PCSM_PGEN_BTPHY_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_1_LOP_POF_OFF_PPU_VCORE1_PCSM_PGEN_CCMP_Pos                                      24U
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_1_LOP_POF_OFF_PPU_VCORE1_PCSM_PGEN_CCMP_Msk                                      (0x1UL << AON_LOP_POF_OFF_PPU_VCORE1_PCSM_1_LOP_POF_OFF_PPU_VCORE1_PCSM_PGEN_CCMP_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_1_LOP_POF_OFF_PPU_VCORE1_PCSM_PGEN_SNPS_Pos                                      25U
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_1_LOP_POF_OFF_PPU_VCORE1_PCSM_PGEN_SNPS_Msk                                      (0x1UL << AON_LOP_POF_OFF_PPU_VCORE1_PCSM_1_LOP_POF_OFF_PPU_VCORE1_PCSM_PGEN_SNPS_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_1_LOP_POF_OFF_PPU_VCORE1_PCSM_PGEN_ROM_0_Pos                                     26U
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_1_LOP_POF_OFF_PPU_VCORE1_PCSM_PGEN_ROM_0_Msk                                     (0x1UL << AON_LOP_POF_OFF_PPU_VCORE1_PCSM_1_LOP_POF_OFF_PPU_VCORE1_PCSM_PGEN_ROM_0_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_1_RESERVED_2_Pos                                                                 27U
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_1_RESERVED_2_Msk                                                                 (0x1UL << AON_LOP_POF_OFF_PPU_VCORE1_PCSM_1_RESERVED_2_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_1_RESERVED_1_Pos                                                                 28U
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_1_RESERVED_1_Msk                                                                 (0x1UL << AON_LOP_POF_OFF_PPU_VCORE1_PCSM_1_RESERVED_1_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_1_RESERVED_Pos                                                                   29U
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_1_RESERVED_Msk                                                                   (0x1UL << AON_LOP_POF_OFF_PPU_VCORE1_PCSM_1_RESERVED_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_1_LOP_POF_OFF_PPU_VCORE1_PCSM_VCORE_PC_VG2_Pos                                   30U
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_1_LOP_POF_OFF_PPU_VCORE1_PCSM_VCORE_PC_VG2_Msk                                   (0x1UL << AON_LOP_POF_OFF_PPU_VCORE1_PCSM_1_LOP_POF_OFF_PPU_VCORE1_PCSM_VCORE_PC_VG2_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_1_LOP_POF_OFF_PPU_VCORE1_PCSM_VCORE_PC_VG1_Pos                                   31U
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_1_LOP_POF_OFF_PPU_VCORE1_PCSM_VCORE_PC_VG1_Msk                                   (0x1UL << AON_LOP_POF_OFF_PPU_VCORE1_PCSM_1_LOP_POF_OFF_PPU_VCORE1_PCSM_VCORE_PC_VG1_Pos)
+
+/* 0xBF8    0x4000_0bf8
+    2:0     R/W     RESERVED_29                                                 3'h0
+    3       R/W     RESERVED_28                                                 1'b0
+    4       R/W     RESERVED_27                                                 1'b1
+    5       R/W     RESERVED_26                                                 1'b0
+    6       R/W     RESERVED_25                                                 1'b1
+    7       R/W     RESERVED_24                                                 1'b0
+    8       R/W     RESERVED_23                                                 1'b1
+    9       R/W     RESERVED_22                                                 1'b0
+    10      R/W     RESERVED_21                                                 1'b1
+    11      R/W     RESERVED_20                                                 1'b0
+    12      R/W     RESERVED_19                                                 1'b1
+    13      R/W     RESERVED_18                                                 1'b0
+    14      R/W     RESERVED_17                                                 1'b1
+    15      R/W     RESERVED_16                                                 1'b0
+    16      R/W     RESERVED_15                                                 1'b1
+    17      R/W     RESERVED_14                                                 1'b0
+    18      R/W     RESERVED_13                                                 1'b1
+    19      R/W     RESERVED_12                                                 1'b0
+    20      R/W     RESERVED_11                                                 1'b1
+    21      R/W     RESERVED_10                                                 1'b0
+    22      R/W     RESERVED_9                                                  1'b1
+    23      R/W     RESERVED_8                                                  1'b0
+    24      R/W     RESERVED_7                                                  1'b1
+    25      R/W     RESERVED_6                                                  1'b0
+    26      R/W     RESERVED_5                                                  1'b1
+    27      R/W     RESERVED_4                                                  1'b0
+    28      R/W     RESERVED_3                                                  1'b1
+    29      R/W     RESERVED_2                                                  1'b0
+    30      R/W     RESERVED_1                                                  1'b1
+    31      R/W     RESERVED                                                    1'b0
+ */
+typedef union _AON_LOP_POF_OFF_PPU_VCORE1_PCSM_2_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED_29: 3;
+        uint32_t RESERVED_28: 1;
+        uint32_t RESERVED_27: 1;
+        uint32_t RESERVED_26: 1;
+        uint32_t RESERVED_25: 1;
+        uint32_t RESERVED_24: 1;
+        uint32_t RESERVED_23: 1;
+        uint32_t RESERVED_22: 1;
+        uint32_t RESERVED_21: 1;
+        uint32_t RESERVED_20: 1;
+        uint32_t RESERVED_19: 1;
+        uint32_t RESERVED_18: 1;
+        uint32_t RESERVED_17: 1;
+        uint32_t RESERVED_16: 1;
+        uint32_t RESERVED_15: 1;
+        uint32_t RESERVED_14: 1;
+        uint32_t RESERVED_13: 1;
+        uint32_t RESERVED_12: 1;
+        uint32_t RESERVED_11: 1;
+        uint32_t RESERVED_10: 1;
+        uint32_t RESERVED_9: 1;
+        uint32_t RESERVED_8: 1;
+        uint32_t RESERVED_7: 1;
+        uint32_t RESERVED_6: 1;
+        uint32_t RESERVED_5: 1;
+        uint32_t RESERVED_4: 1;
+        uint32_t RESERVED_3: 1;
+        uint32_t RESERVED_2: 1;
+        uint32_t RESERVED_1: 1;
+        uint32_t RESERVED: 1;
+    };
+} AON_LOP_POF_OFF_PPU_VCORE1_PCSM_2_TYPE;
+
+/*0x4000_0bf8 AON_LOP_POF_OFF_PPU_VCORE1_PCSM_2*/
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_2_RESERVED_29_Pos                                                                0U
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_2_RESERVED_29_Msk                                                                (0x7UL << AON_LOP_POF_OFF_PPU_VCORE1_PCSM_2_RESERVED_29_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_2_RESERVED_28_Pos                                                                3U
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_2_RESERVED_28_Msk                                                                (0x1UL << AON_LOP_POF_OFF_PPU_VCORE1_PCSM_2_RESERVED_28_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_2_RESERVED_27_Pos                                                                4U
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_2_RESERVED_27_Msk                                                                (0x1UL << AON_LOP_POF_OFF_PPU_VCORE1_PCSM_2_RESERVED_27_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_2_RESERVED_26_Pos                                                                5U
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_2_RESERVED_26_Msk                                                                (0x1UL << AON_LOP_POF_OFF_PPU_VCORE1_PCSM_2_RESERVED_26_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_2_RESERVED_25_Pos                                                                6U
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_2_RESERVED_25_Msk                                                                (0x1UL << AON_LOP_POF_OFF_PPU_VCORE1_PCSM_2_RESERVED_25_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_2_RESERVED_24_Pos                                                                7U
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_2_RESERVED_24_Msk                                                                (0x1UL << AON_LOP_POF_OFF_PPU_VCORE1_PCSM_2_RESERVED_24_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_2_RESERVED_23_Pos                                                                8U
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_2_RESERVED_23_Msk                                                                (0x1UL << AON_LOP_POF_OFF_PPU_VCORE1_PCSM_2_RESERVED_23_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_2_RESERVED_22_Pos                                                                9U
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_2_RESERVED_22_Msk                                                                (0x1UL << AON_LOP_POF_OFF_PPU_VCORE1_PCSM_2_RESERVED_22_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_2_RESERVED_21_Pos                                                                10U
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_2_RESERVED_21_Msk                                                                (0x1UL << AON_LOP_POF_OFF_PPU_VCORE1_PCSM_2_RESERVED_21_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_2_RESERVED_20_Pos                                                                11U
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_2_RESERVED_20_Msk                                                                (0x1UL << AON_LOP_POF_OFF_PPU_VCORE1_PCSM_2_RESERVED_20_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_2_RESERVED_19_Pos                                                                12U
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_2_RESERVED_19_Msk                                                                (0x1UL << AON_LOP_POF_OFF_PPU_VCORE1_PCSM_2_RESERVED_19_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_2_RESERVED_18_Pos                                                                13U
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_2_RESERVED_18_Msk                                                                (0x1UL << AON_LOP_POF_OFF_PPU_VCORE1_PCSM_2_RESERVED_18_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_2_RESERVED_17_Pos                                                                14U
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_2_RESERVED_17_Msk                                                                (0x1UL << AON_LOP_POF_OFF_PPU_VCORE1_PCSM_2_RESERVED_17_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_2_RESERVED_16_Pos                                                                15U
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_2_RESERVED_16_Msk                                                                (0x1UL << AON_LOP_POF_OFF_PPU_VCORE1_PCSM_2_RESERVED_16_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_2_RESERVED_15_Pos                                                                16U
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_2_RESERVED_15_Msk                                                                (0x1UL << AON_LOP_POF_OFF_PPU_VCORE1_PCSM_2_RESERVED_15_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_2_RESERVED_14_Pos                                                                17U
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_2_RESERVED_14_Msk                                                                (0x1UL << AON_LOP_POF_OFF_PPU_VCORE1_PCSM_2_RESERVED_14_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_2_RESERVED_13_Pos                                                                18U
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_2_RESERVED_13_Msk                                                                (0x1UL << AON_LOP_POF_OFF_PPU_VCORE1_PCSM_2_RESERVED_13_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_2_RESERVED_12_Pos                                                                19U
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_2_RESERVED_12_Msk                                                                (0x1UL << AON_LOP_POF_OFF_PPU_VCORE1_PCSM_2_RESERVED_12_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_2_RESERVED_11_Pos                                                                20U
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_2_RESERVED_11_Msk                                                                (0x1UL << AON_LOP_POF_OFF_PPU_VCORE1_PCSM_2_RESERVED_11_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_2_RESERVED_10_Pos                                                                21U
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_2_RESERVED_10_Msk                                                                (0x1UL << AON_LOP_POF_OFF_PPU_VCORE1_PCSM_2_RESERVED_10_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_2_RESERVED_9_Pos                                                                 22U
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_2_RESERVED_9_Msk                                                                 (0x1UL << AON_LOP_POF_OFF_PPU_VCORE1_PCSM_2_RESERVED_9_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_2_RESERVED_8_Pos                                                                 23U
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_2_RESERVED_8_Msk                                                                 (0x1UL << AON_LOP_POF_OFF_PPU_VCORE1_PCSM_2_RESERVED_8_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_2_RESERVED_7_Pos                                                                 24U
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_2_RESERVED_7_Msk                                                                 (0x1UL << AON_LOP_POF_OFF_PPU_VCORE1_PCSM_2_RESERVED_7_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_2_RESERVED_6_Pos                                                                 25U
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_2_RESERVED_6_Msk                                                                 (0x1UL << AON_LOP_POF_OFF_PPU_VCORE1_PCSM_2_RESERVED_6_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_2_RESERVED_5_Pos                                                                 26U
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_2_RESERVED_5_Msk                                                                 (0x1UL << AON_LOP_POF_OFF_PPU_VCORE1_PCSM_2_RESERVED_5_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_2_RESERVED_4_Pos                                                                 27U
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_2_RESERVED_4_Msk                                                                 (0x1UL << AON_LOP_POF_OFF_PPU_VCORE1_PCSM_2_RESERVED_4_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_2_RESERVED_3_Pos                                                                 28U
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_2_RESERVED_3_Msk                                                                 (0x1UL << AON_LOP_POF_OFF_PPU_VCORE1_PCSM_2_RESERVED_3_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_2_RESERVED_2_Pos                                                                 29U
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_2_RESERVED_2_Msk                                                                 (0x1UL << AON_LOP_POF_OFF_PPU_VCORE1_PCSM_2_RESERVED_2_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_2_RESERVED_1_Pos                                                                 30U
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_2_RESERVED_1_Msk                                                                 (0x1UL << AON_LOP_POF_OFF_PPU_VCORE1_PCSM_2_RESERVED_1_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_2_RESERVED_Pos                                                                   31U
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_2_RESERVED_Msk                                                                   (0x1UL << AON_LOP_POF_OFF_PPU_VCORE1_PCSM_2_RESERVED_Pos)
+
+/* 0xBF4    0x4000_0bf4
+    0       R/W     RESERVED_31                                                 1'b0
+    1       R/W     RESERVED_30                                                 1'b1
+    2       R/W     RESERVED_29                                                 1'b0
+    3       R/W     RESERVED_28                                                 1'b1
+    4       R/W     RESERVED_27                                                 1'b0
+    5       R/W     RESERVED_26                                                 1'b1
+    6       R/W     RESERVED_25                                                 1'b0
+    7       R/W     RESERVED_24                                                 1'b1
+    8       R/W     RESERVED_23                                                 1'b0
+    9       R/W     RESERVED_22                                                 1'b1
+    10      R/W     RESERVED_21                                                 1'b0
+    11      R/W     RESERVED_20                                                 1'b1
+    12      R/W     RESERVED_19                                                 1'b0
+    13      R/W     RESERVED_18                                                 1'b1
+    14      R/W     RESERVED_17                                                 1'b0
+    15      R/W     RESERVED_16                                                 1'b1
+    16      R/W     RESERVED_15                                                 1'b0
+    17      R/W     RESERVED_14                                                 1'b1
+    18      R/W     RESERVED_13                                                 1'b0
+    19      R/W     RESERVED_12                                                 1'b1
+    20      R/W     RESERVED_11                                                 1'b0
+    21      R/W     RESERVED_10                                                 1'b1
+    22      R/W     RESERVED_9                                                  1'b0
+    23      R/W     RESERVED_8                                                  1'b1
+    24      R/W     RESERVED_7                                                  1'b0
+    25      R/W     RESERVED_6                                                  1'b1
+    26      R/W     RESERVED_5                                                  1'b0
+    27      R/W     RESERVED_4                                                  1'b1
+    28      R/W     RESERVED_3                                                  1'b0
+    29      R/W     RESERVED_2                                                  1'b1
+    30      R/W     RESERVED_1                                                  1'b0
+    31      R/W     RESERVED                                                    1'b1
+ */
+typedef union _AON_LOP_POF_OFF_PPU_VCORE1_PCSM_3_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED_31: 1;
+        uint32_t RESERVED_30: 1;
+        uint32_t RESERVED_29: 1;
+        uint32_t RESERVED_28: 1;
+        uint32_t RESERVED_27: 1;
+        uint32_t RESERVED_26: 1;
+        uint32_t RESERVED_25: 1;
+        uint32_t RESERVED_24: 1;
+        uint32_t RESERVED_23: 1;
+        uint32_t RESERVED_22: 1;
+        uint32_t RESERVED_21: 1;
+        uint32_t RESERVED_20: 1;
+        uint32_t RESERVED_19: 1;
+        uint32_t RESERVED_18: 1;
+        uint32_t RESERVED_17: 1;
+        uint32_t RESERVED_16: 1;
+        uint32_t RESERVED_15: 1;
+        uint32_t RESERVED_14: 1;
+        uint32_t RESERVED_13: 1;
+        uint32_t RESERVED_12: 1;
+        uint32_t RESERVED_11: 1;
+        uint32_t RESERVED_10: 1;
+        uint32_t RESERVED_9: 1;
+        uint32_t RESERVED_8: 1;
+        uint32_t RESERVED_7: 1;
+        uint32_t RESERVED_6: 1;
+        uint32_t RESERVED_5: 1;
+        uint32_t RESERVED_4: 1;
+        uint32_t RESERVED_3: 1;
+        uint32_t RESERVED_2: 1;
+        uint32_t RESERVED_1: 1;
+        uint32_t RESERVED: 1;
+    };
+} AON_LOP_POF_OFF_PPU_VCORE1_PCSM_3_TYPE;
+
+/*0x4000_0bf4 AON_LOP_POF_OFF_PPU_VCORE1_PCSM_3*/
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_3_RESERVED_31_Pos                                                                0U
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_3_RESERVED_31_Msk                                                                (0x1UL << AON_LOP_POF_OFF_PPU_VCORE1_PCSM_3_RESERVED_31_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_3_RESERVED_30_Pos                                                                1U
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_3_RESERVED_30_Msk                                                                (0x1UL << AON_LOP_POF_OFF_PPU_VCORE1_PCSM_3_RESERVED_30_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_3_RESERVED_29_Pos                                                                2U
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_3_RESERVED_29_Msk                                                                (0x1UL << AON_LOP_POF_OFF_PPU_VCORE1_PCSM_3_RESERVED_29_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_3_RESERVED_28_Pos                                                                3U
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_3_RESERVED_28_Msk                                                                (0x1UL << AON_LOP_POF_OFF_PPU_VCORE1_PCSM_3_RESERVED_28_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_3_RESERVED_27_Pos                                                                4U
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_3_RESERVED_27_Msk                                                                (0x1UL << AON_LOP_POF_OFF_PPU_VCORE1_PCSM_3_RESERVED_27_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_3_RESERVED_26_Pos                                                                5U
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_3_RESERVED_26_Msk                                                                (0x1UL << AON_LOP_POF_OFF_PPU_VCORE1_PCSM_3_RESERVED_26_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_3_RESERVED_25_Pos                                                                6U
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_3_RESERVED_25_Msk                                                                (0x1UL << AON_LOP_POF_OFF_PPU_VCORE1_PCSM_3_RESERVED_25_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_3_RESERVED_24_Pos                                                                7U
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_3_RESERVED_24_Msk                                                                (0x1UL << AON_LOP_POF_OFF_PPU_VCORE1_PCSM_3_RESERVED_24_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_3_RESERVED_23_Pos                                                                8U
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_3_RESERVED_23_Msk                                                                (0x1UL << AON_LOP_POF_OFF_PPU_VCORE1_PCSM_3_RESERVED_23_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_3_RESERVED_22_Pos                                                                9U
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_3_RESERVED_22_Msk                                                                (0x1UL << AON_LOP_POF_OFF_PPU_VCORE1_PCSM_3_RESERVED_22_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_3_RESERVED_21_Pos                                                                10U
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_3_RESERVED_21_Msk                                                                (0x1UL << AON_LOP_POF_OFF_PPU_VCORE1_PCSM_3_RESERVED_21_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_3_RESERVED_20_Pos                                                                11U
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_3_RESERVED_20_Msk                                                                (0x1UL << AON_LOP_POF_OFF_PPU_VCORE1_PCSM_3_RESERVED_20_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_3_RESERVED_19_Pos                                                                12U
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_3_RESERVED_19_Msk                                                                (0x1UL << AON_LOP_POF_OFF_PPU_VCORE1_PCSM_3_RESERVED_19_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_3_RESERVED_18_Pos                                                                13U
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_3_RESERVED_18_Msk                                                                (0x1UL << AON_LOP_POF_OFF_PPU_VCORE1_PCSM_3_RESERVED_18_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_3_RESERVED_17_Pos                                                                14U
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_3_RESERVED_17_Msk                                                                (0x1UL << AON_LOP_POF_OFF_PPU_VCORE1_PCSM_3_RESERVED_17_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_3_RESERVED_16_Pos                                                                15U
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_3_RESERVED_16_Msk                                                                (0x1UL << AON_LOP_POF_OFF_PPU_VCORE1_PCSM_3_RESERVED_16_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_3_RESERVED_15_Pos                                                                16U
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_3_RESERVED_15_Msk                                                                (0x1UL << AON_LOP_POF_OFF_PPU_VCORE1_PCSM_3_RESERVED_15_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_3_RESERVED_14_Pos                                                                17U
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_3_RESERVED_14_Msk                                                                (0x1UL << AON_LOP_POF_OFF_PPU_VCORE1_PCSM_3_RESERVED_14_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_3_RESERVED_13_Pos                                                                18U
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_3_RESERVED_13_Msk                                                                (0x1UL << AON_LOP_POF_OFF_PPU_VCORE1_PCSM_3_RESERVED_13_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_3_RESERVED_12_Pos                                                                19U
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_3_RESERVED_12_Msk                                                                (0x1UL << AON_LOP_POF_OFF_PPU_VCORE1_PCSM_3_RESERVED_12_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_3_RESERVED_11_Pos                                                                20U
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_3_RESERVED_11_Msk                                                                (0x1UL << AON_LOP_POF_OFF_PPU_VCORE1_PCSM_3_RESERVED_11_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_3_RESERVED_10_Pos                                                                21U
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_3_RESERVED_10_Msk                                                                (0x1UL << AON_LOP_POF_OFF_PPU_VCORE1_PCSM_3_RESERVED_10_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_3_RESERVED_9_Pos                                                                 22U
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_3_RESERVED_9_Msk                                                                 (0x1UL << AON_LOP_POF_OFF_PPU_VCORE1_PCSM_3_RESERVED_9_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_3_RESERVED_8_Pos                                                                 23U
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_3_RESERVED_8_Msk                                                                 (0x1UL << AON_LOP_POF_OFF_PPU_VCORE1_PCSM_3_RESERVED_8_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_3_RESERVED_7_Pos                                                                 24U
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_3_RESERVED_7_Msk                                                                 (0x1UL << AON_LOP_POF_OFF_PPU_VCORE1_PCSM_3_RESERVED_7_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_3_RESERVED_6_Pos                                                                 25U
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_3_RESERVED_6_Msk                                                                 (0x1UL << AON_LOP_POF_OFF_PPU_VCORE1_PCSM_3_RESERVED_6_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_3_RESERVED_5_Pos                                                                 26U
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_3_RESERVED_5_Msk                                                                 (0x1UL << AON_LOP_POF_OFF_PPU_VCORE1_PCSM_3_RESERVED_5_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_3_RESERVED_4_Pos                                                                 27U
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_3_RESERVED_4_Msk                                                                 (0x1UL << AON_LOP_POF_OFF_PPU_VCORE1_PCSM_3_RESERVED_4_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_3_RESERVED_3_Pos                                                                 28U
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_3_RESERVED_3_Msk                                                                 (0x1UL << AON_LOP_POF_OFF_PPU_VCORE1_PCSM_3_RESERVED_3_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_3_RESERVED_2_Pos                                                                 29U
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_3_RESERVED_2_Msk                                                                 (0x1UL << AON_LOP_POF_OFF_PPU_VCORE1_PCSM_3_RESERVED_2_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_3_RESERVED_1_Pos                                                                 30U
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_3_RESERVED_1_Msk                                                                 (0x1UL << AON_LOP_POF_OFF_PPU_VCORE1_PCSM_3_RESERVED_1_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_3_RESERVED_Pos                                                                   31U
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_3_RESERVED_Msk                                                                   (0x1UL << AON_LOP_POF_OFF_PPU_VCORE1_PCSM_3_RESERVED_Pos)
+
+/* 0xBF0    0x4000_0bf0
+    28:0    R/W     RESERVED_1                                                  29'h0
+    29      R/W     RESERVED                                                    1'b0
+    30      R/W     LOP_POF_OFF_PPU_VCORE1_PCSM_SRAM_SETTING_SEL                1'b1
+    31      R/W     LOP_POF_OFF_PPU_VCORE1_PCSM_PAD_AUTO_SW_EN_RET              1'b1
+ */
+typedef union _AON_LOP_POF_OFF_PPU_VCORE1_PCSM_4_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED_1: 29;
+        uint32_t RESERVED: 1;
+        uint32_t LOP_POF_OFF_PPU_VCORE1_PCSM_SRAM_SETTING_SEL: 1;
+        uint32_t LOP_POF_OFF_PPU_VCORE1_PCSM_PAD_AUTO_SW_EN_RET: 1;
+    };
+} AON_LOP_POF_OFF_PPU_VCORE1_PCSM_4_TYPE;
+
+/*0x4000_0bf0 AON_LOP_POF_OFF_PPU_VCORE1_PCSM_4*/
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_4_RESERVED_1_Pos                                                                 0U
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_4_RESERVED_1_Msk                                                                 (0x1FFFFFFFUL << AON_LOP_POF_OFF_PPU_VCORE1_PCSM_4_RESERVED_1_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_4_RESERVED_Pos                                                                   29U
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_4_RESERVED_Msk                                                                   (0x1UL << AON_LOP_POF_OFF_PPU_VCORE1_PCSM_4_RESERVED_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_4_LOP_POF_OFF_PPU_VCORE1_PCSM_SRAM_SETTING_SEL_Pos                               30U
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_4_LOP_POF_OFF_PPU_VCORE1_PCSM_SRAM_SETTING_SEL_Msk                               (0x1UL << AON_LOP_POF_OFF_PPU_VCORE1_PCSM_4_LOP_POF_OFF_PPU_VCORE1_PCSM_SRAM_SETTING_SEL_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_4_LOP_POF_OFF_PPU_VCORE1_PCSM_PAD_AUTO_SW_EN_RET_Pos                             31U
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_4_LOP_POF_OFF_PPU_VCORE1_PCSM_PAD_AUTO_SW_EN_RET_Msk                             (0x1UL << AON_LOP_POF_OFF_PPU_VCORE1_PCSM_4_LOP_POF_OFF_PPU_VCORE1_PCSM_PAD_AUTO_SW_EN_RET_Pos)
+
+/* 0xBEC    0x4000_0bec
+    0       R/W     RESERVED_4                                                  1'b1
+    1       R/W     RESERVED_3                                                  1'b1
+    2       R/W     LOP_POF_FULL_RET_PPU_VCORE1_PCSM_RET2N_CPU                  1'b1
+    3       R/W     LOP_POF_FULL_RET_PPU_VCORE1_PCSM_RET2N_USB                  1'b1
+    4       R/W     LOP_POF_FULL_RET_PPU_VCORE1_PCSM_RET2N_CAN                  1'b1
+    5       R/W     LOP_POF_FULL_RET_PPU_VCORE1_PCSM_RET2N_LEBIS                1'b1
+    6       R/W     LOP_POF_FULL_RET_PPU_VCORE1_PCSM_RET2N_AUDIO                1'b1
+    7       R/W     LOP_POF_FULL_RET_PPU_VCORE1_PCSM_RET2N_BTPHY                1'b1
+    8       R/W     LOP_POF_FULL_RET_PPU_VCORE1_PCSM_RET2N_CCMP                 1'b1
+    9       R/W     LOP_POF_FULL_RET_PPU_VCORE1_PCSM_RET2N_SNPS                 1'b1
+    10      R/W     LOP_POF_FULL_RET_PPU_VCORE1_PCSM_RET1N_CPU                  1'b1
+    11      R/W     LOP_POF_FULL_RET_PPU_VCORE1_PCSM_RET1N_USB                  1'b1
+    12      R/W     LOP_POF_FULL_RET_PPU_VCORE1_PCSM_RET1N_CAN                  1'b1
+    13      R/W     LOP_POF_FULL_RET_PPU_VCORE1_PCSM_RET1N_LEBIS                1'b1
+    14      R/W     LOP_POF_FULL_RET_PPU_VCORE1_PCSM_RET1N_AUDIO                1'b1
+    15      R/W     LOP_POF_FULL_RET_PPU_VCORE1_PCSM_RET1N_BTPHY                1'b1
+    16      R/W     LOP_POF_FULL_RET_PPU_VCORE1_PCSM_RET1N_CCMP                 1'b1
+    17      R/W     LOP_POF_FULL_RET_PPU_VCORE1_PCSM_RET1N_SNPS                 1'b1
+    18      R/W     LOP_POF_FULL_RET_PPU_VCORE1_PCSM_PGEN_CPU                   1'b1
+    19      R/W     LOP_POF_FULL_RET_PPU_VCORE1_PCSM_PGEN_USB                   1'b1
+    20      R/W     LOP_POF_FULL_RET_PPU_VCORE1_PCSM_PGEN_CAN                   1'b1
+    21      R/W     LOP_POF_FULL_RET_PPU_VCORE1_PCSM_PGEN_LEBIS                 1'b1
+    22      R/W     LOP_POF_FULL_RET_PPU_VCORE1_PCSM_PGEN_AUDIO                 1'b1
+    23      R/W     LOP_POF_FULL_RET_PPU_VCORE1_PCSM_PGEN_BTPHY                 1'b1
+    24      R/W     LOP_POF_FULL_RET_PPU_VCORE1_PCSM_PGEN_CCMP                  1'b1
+    25      R/W     LOP_POF_FULL_RET_PPU_VCORE1_PCSM_PGEN_SNPS                  1'b1
+    26      R/W     LOP_POF_FULL_RET_PPU_VCORE1_PCSM_PGEN_ROM_0                 1'b1
+    27      R/W     RESERVED_2                                                  1'b0
+    28      R/W     RESERVED_1                                                  1'b0
+    29      R/W     RESERVED                                                    1'b1
+    30      R/W     LOP_POF_FULL_RET_PPU_VCORE1_PCSM_VCORE_PC_VG2               1'b1
+    31      R/W     LOP_POF_FULL_RET_PPU_VCORE1_PCSM_VCORE_PC_VG1               1'b1
+ */
+typedef union _AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_1_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED_4: 1;
+        uint32_t RESERVED_3: 1;
+        uint32_t LOP_POF_FULL_RET_PPU_VCORE1_PCSM_RET2N_CPU: 1;
+        uint32_t LOP_POF_FULL_RET_PPU_VCORE1_PCSM_RET2N_USB: 1;
+        uint32_t LOP_POF_FULL_RET_PPU_VCORE1_PCSM_RET2N_CAN: 1;
+        uint32_t LOP_POF_FULL_RET_PPU_VCORE1_PCSM_RET2N_LEBIS: 1;
+        uint32_t LOP_POF_FULL_RET_PPU_VCORE1_PCSM_RET2N_AUDIO: 1;
+        uint32_t LOP_POF_FULL_RET_PPU_VCORE1_PCSM_RET2N_BTPHY: 1;
+        uint32_t LOP_POF_FULL_RET_PPU_VCORE1_PCSM_RET2N_CCMP: 1;
+        uint32_t LOP_POF_FULL_RET_PPU_VCORE1_PCSM_RET2N_SNPS: 1;
+        uint32_t LOP_POF_FULL_RET_PPU_VCORE1_PCSM_RET1N_CPU: 1;
+        uint32_t LOP_POF_FULL_RET_PPU_VCORE1_PCSM_RET1N_USB: 1;
+        uint32_t LOP_POF_FULL_RET_PPU_VCORE1_PCSM_RET1N_CAN: 1;
+        uint32_t LOP_POF_FULL_RET_PPU_VCORE1_PCSM_RET1N_LEBIS: 1;
+        uint32_t LOP_POF_FULL_RET_PPU_VCORE1_PCSM_RET1N_AUDIO: 1;
+        uint32_t LOP_POF_FULL_RET_PPU_VCORE1_PCSM_RET1N_BTPHY: 1;
+        uint32_t LOP_POF_FULL_RET_PPU_VCORE1_PCSM_RET1N_CCMP: 1;
+        uint32_t LOP_POF_FULL_RET_PPU_VCORE1_PCSM_RET1N_SNPS: 1;
+        uint32_t LOP_POF_FULL_RET_PPU_VCORE1_PCSM_PGEN_CPU: 1;
+        uint32_t LOP_POF_FULL_RET_PPU_VCORE1_PCSM_PGEN_USB: 1;
+        uint32_t LOP_POF_FULL_RET_PPU_VCORE1_PCSM_PGEN_CAN: 1;
+        uint32_t LOP_POF_FULL_RET_PPU_VCORE1_PCSM_PGEN_LEBIS: 1;
+        uint32_t LOP_POF_FULL_RET_PPU_VCORE1_PCSM_PGEN_AUDIO: 1;
+        uint32_t LOP_POF_FULL_RET_PPU_VCORE1_PCSM_PGEN_BTPHY: 1;
+        uint32_t LOP_POF_FULL_RET_PPU_VCORE1_PCSM_PGEN_CCMP: 1;
+        uint32_t LOP_POF_FULL_RET_PPU_VCORE1_PCSM_PGEN_SNPS: 1;
+        uint32_t LOP_POF_FULL_RET_PPU_VCORE1_PCSM_PGEN_ROM_0: 1;
+        uint32_t RESERVED_2: 1;
+        uint32_t RESERVED_1: 1;
+        uint32_t RESERVED: 1;
+        uint32_t LOP_POF_FULL_RET_PPU_VCORE1_PCSM_VCORE_PC_VG2: 1;
+        uint32_t LOP_POF_FULL_RET_PPU_VCORE1_PCSM_VCORE_PC_VG1: 1;
+    };
+} AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_1_TYPE;
+
+/*0x4000_0bec AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_1*/
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_1_RESERVED_4_Pos                                                            0U
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_1_RESERVED_4_Msk                                                            (0x1UL << AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_1_RESERVED_4_Pos)
+
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_1_RESERVED_3_Pos                                                            1U
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_1_RESERVED_3_Msk                                                            (0x1UL << AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_1_RESERVED_3_Pos)
+
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_1_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_RET2N_CPU_Pos                            2U
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_1_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_RET2N_CPU_Msk                            (0x1UL << AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_1_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_RET2N_CPU_Pos)
+
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_1_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_RET2N_USB_Pos                            3U
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_1_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_RET2N_USB_Msk                            (0x1UL << AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_1_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_RET2N_USB_Pos)
+
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_1_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_RET2N_CAN_Pos                            4U
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_1_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_RET2N_CAN_Msk                            (0x1UL << AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_1_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_RET2N_CAN_Pos)
+
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_1_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_RET2N_LEBIS_Pos                          5U
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_1_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_RET2N_LEBIS_Msk                          (0x1UL << AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_1_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_RET2N_LEBIS_Pos)
+
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_1_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_RET2N_AUDIO_Pos                          6U
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_1_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_RET2N_AUDIO_Msk                          (0x1UL << AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_1_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_RET2N_AUDIO_Pos)
+
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_1_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_RET2N_BTPHY_Pos                          7U
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_1_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_RET2N_BTPHY_Msk                          (0x1UL << AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_1_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_RET2N_BTPHY_Pos)
+
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_1_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_RET2N_CCMP_Pos                           8U
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_1_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_RET2N_CCMP_Msk                           (0x1UL << AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_1_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_RET2N_CCMP_Pos)
+
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_1_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_RET2N_SNPS_Pos                           9U
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_1_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_RET2N_SNPS_Msk                           (0x1UL << AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_1_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_RET2N_SNPS_Pos)
+
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_1_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_RET1N_CPU_Pos                            10U
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_1_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_RET1N_CPU_Msk                            (0x1UL << AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_1_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_RET1N_CPU_Pos)
+
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_1_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_RET1N_USB_Pos                            11U
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_1_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_RET1N_USB_Msk                            (0x1UL << AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_1_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_RET1N_USB_Pos)
+
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_1_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_RET1N_CAN_Pos                            12U
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_1_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_RET1N_CAN_Msk                            (0x1UL << AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_1_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_RET1N_CAN_Pos)
+
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_1_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_RET1N_LEBIS_Pos                          13U
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_1_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_RET1N_LEBIS_Msk                          (0x1UL << AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_1_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_RET1N_LEBIS_Pos)
+
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_1_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_RET1N_AUDIO_Pos                          14U
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_1_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_RET1N_AUDIO_Msk                          (0x1UL << AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_1_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_RET1N_AUDIO_Pos)
+
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_1_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_RET1N_BTPHY_Pos                          15U
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_1_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_RET1N_BTPHY_Msk                          (0x1UL << AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_1_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_RET1N_BTPHY_Pos)
+
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_1_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_RET1N_CCMP_Pos                           16U
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_1_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_RET1N_CCMP_Msk                           (0x1UL << AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_1_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_RET1N_CCMP_Pos)
+
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_1_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_RET1N_SNPS_Pos                           17U
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_1_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_RET1N_SNPS_Msk                           (0x1UL << AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_1_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_RET1N_SNPS_Pos)
+
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_1_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_PGEN_CPU_Pos                             18U
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_1_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_PGEN_CPU_Msk                             (0x1UL << AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_1_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_PGEN_CPU_Pos)
+
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_1_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_PGEN_USB_Pos                             19U
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_1_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_PGEN_USB_Msk                             (0x1UL << AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_1_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_PGEN_USB_Pos)
+
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_1_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_PGEN_CAN_Pos                             20U
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_1_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_PGEN_CAN_Msk                             (0x1UL << AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_1_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_PGEN_CAN_Pos)
+
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_1_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_PGEN_LEBIS_Pos                           21U
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_1_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_PGEN_LEBIS_Msk                           (0x1UL << AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_1_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_PGEN_LEBIS_Pos)
+
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_1_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_PGEN_AUDIO_Pos                           22U
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_1_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_PGEN_AUDIO_Msk                           (0x1UL << AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_1_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_PGEN_AUDIO_Pos)
+
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_1_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_PGEN_BTPHY_Pos                           23U
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_1_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_PGEN_BTPHY_Msk                           (0x1UL << AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_1_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_PGEN_BTPHY_Pos)
+
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_1_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_PGEN_CCMP_Pos                            24U
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_1_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_PGEN_CCMP_Msk                            (0x1UL << AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_1_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_PGEN_CCMP_Pos)
+
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_1_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_PGEN_SNPS_Pos                            25U
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_1_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_PGEN_SNPS_Msk                            (0x1UL << AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_1_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_PGEN_SNPS_Pos)
+
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_1_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_PGEN_ROM_0_Pos                           26U
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_1_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_PGEN_ROM_0_Msk                           (0x1UL << AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_1_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_PGEN_ROM_0_Pos)
+
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_1_RESERVED_2_Pos                                                            27U
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_1_RESERVED_2_Msk                                                            (0x1UL << AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_1_RESERVED_2_Pos)
+
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_1_RESERVED_1_Pos                                                            28U
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_1_RESERVED_1_Msk                                                            (0x1UL << AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_1_RESERVED_1_Pos)
+
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_1_RESERVED_Pos                                                              29U
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_1_RESERVED_Msk                                                              (0x1UL << AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_1_RESERVED_Pos)
+
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_1_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_VCORE_PC_VG2_Pos                         30U
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_1_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_VCORE_PC_VG2_Msk                         (0x1UL << AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_1_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_VCORE_PC_VG2_Pos)
+
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_1_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_VCORE_PC_VG1_Pos                         31U
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_1_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_VCORE_PC_VG1_Msk                         (0x1UL << AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_1_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_VCORE_PC_VG1_Pos)
+
+/* 0xBE8    0x4000_0be8
+    2:0     R/W     RESERVED_28                                                 3'h0
+    3       R/W     RESERVED_27                                                 1'b0
+    4       R/W     RESERVED_26                                                 1'b1
+    5       R/W     RESERVED_25                                                 1'b0
+    6       R/W     RESERVED_24                                                 1'b1
+    7       R/W     RESERVED_23                                                 1'b0
+    8       R/W     RESERVED_22                                                 1'b1
+    9       R/W     RESERVED_21                                                 1'b0
+    10      R/W     RESERVED_20                                                 1'b1
+    11      R/W     RESERVED_19                                                 1'b0
+    12      R/W     RESERVED_18                                                 1'b1
+    13      R/W     RESERVED_17                                                 1'b0
+    14      R/W     RESERVED_16                                                 1'b1
+    15      R/W     RESERVED_15                                                 1'b0
+    16      R/W     RESERVED_14                                                 1'b1
+    17      R/W     RESERVED_13                                                 1'b0
+    18      R/W     LOP_POF_FULL_RET_PPU_VCORE1_PCSM_PERIPHERAL_ALL_RET         1'b1
+    19      R/W     RESERVED_12                                                 1'b0
+    20      R/W     RESERVED_11                                                 1'b1
+    21      R/W     RESERVED_10                                                 1'b0
+    22      R/W     RESERVED_9                                                  1'b1
+    23      R/W     RESERVED_8                                                  1'b0
+    24      R/W     RESERVED_7                                                  1'b1
+    25      R/W     RESERVED_6                                                  1'b0
+    26      R/W     RESERVED_5                                                  1'b1
+    27      R/W     RESERVED_4                                                  1'b0
+    28      R/W     RESERVED_3                                                  1'b1
+    29      R/W     RESERVED_2                                                  1'b0
+    30      R/W     RESERVED_1                                                  1'b1
+    31      R/W     RESERVED                                                    1'b1
+ */
+typedef union _AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_2_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED_28: 3;
+        uint32_t RESERVED_27: 1;
+        uint32_t RESERVED_26: 1;
+        uint32_t RESERVED_25: 1;
+        uint32_t RESERVED_24: 1;
+        uint32_t RESERVED_23: 1;
+        uint32_t RESERVED_22: 1;
+        uint32_t RESERVED_21: 1;
+        uint32_t RESERVED_20: 1;
+        uint32_t RESERVED_19: 1;
+        uint32_t RESERVED_18: 1;
+        uint32_t RESERVED_17: 1;
+        uint32_t RESERVED_16: 1;
+        uint32_t RESERVED_15: 1;
+        uint32_t RESERVED_14: 1;
+        uint32_t RESERVED_13: 1;
+        uint32_t LOP_POF_FULL_RET_PPU_VCORE1_PCSM_PERIPHERAL_ALL_RET: 1;
+        uint32_t RESERVED_12: 1;
+        uint32_t RESERVED_11: 1;
+        uint32_t RESERVED_10: 1;
+        uint32_t RESERVED_9: 1;
+        uint32_t RESERVED_8: 1;
+        uint32_t RESERVED_7: 1;
+        uint32_t RESERVED_6: 1;
+        uint32_t RESERVED_5: 1;
+        uint32_t RESERVED_4: 1;
+        uint32_t RESERVED_3: 1;
+        uint32_t RESERVED_2: 1;
+        uint32_t RESERVED_1: 1;
+        uint32_t RESERVED: 1;
+    };
+} AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_2_TYPE;
+
+/*0x4000_0be8 AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_2*/
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_2_RESERVED_28_Pos                                                           0U
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_2_RESERVED_28_Msk                                                           (0x7UL << AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_2_RESERVED_28_Pos)
+
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_2_RESERVED_27_Pos                                                           3U
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_2_RESERVED_27_Msk                                                           (0x1UL << AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_2_RESERVED_27_Pos)
+
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_2_RESERVED_26_Pos                                                           4U
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_2_RESERVED_26_Msk                                                           (0x1UL << AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_2_RESERVED_26_Pos)
+
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_2_RESERVED_25_Pos                                                           5U
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_2_RESERVED_25_Msk                                                           (0x1UL << AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_2_RESERVED_25_Pos)
+
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_2_RESERVED_24_Pos                                                           6U
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_2_RESERVED_24_Msk                                                           (0x1UL << AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_2_RESERVED_24_Pos)
+
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_2_RESERVED_23_Pos                                                           7U
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_2_RESERVED_23_Msk                                                           (0x1UL << AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_2_RESERVED_23_Pos)
+
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_2_RESERVED_22_Pos                                                           8U
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_2_RESERVED_22_Msk                                                           (0x1UL << AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_2_RESERVED_22_Pos)
+
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_2_RESERVED_21_Pos                                                           9U
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_2_RESERVED_21_Msk                                                           (0x1UL << AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_2_RESERVED_21_Pos)
+
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_2_RESERVED_20_Pos                                                           10U
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_2_RESERVED_20_Msk                                                           (0x1UL << AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_2_RESERVED_20_Pos)
+
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_2_RESERVED_19_Pos                                                           11U
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_2_RESERVED_19_Msk                                                           (0x1UL << AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_2_RESERVED_19_Pos)
+
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_2_RESERVED_18_Pos                                                           12U
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_2_RESERVED_18_Msk                                                           (0x1UL << AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_2_RESERVED_18_Pos)
+
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_2_RESERVED_17_Pos                                                           13U
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_2_RESERVED_17_Msk                                                           (0x1UL << AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_2_RESERVED_17_Pos)
+
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_2_RESERVED_16_Pos                                                           14U
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_2_RESERVED_16_Msk                                                           (0x1UL << AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_2_RESERVED_16_Pos)
+
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_2_RESERVED_15_Pos                                                           15U
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_2_RESERVED_15_Msk                                                           (0x1UL << AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_2_RESERVED_15_Pos)
+
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_2_RESERVED_14_Pos                                                           16U
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_2_RESERVED_14_Msk                                                           (0x1UL << AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_2_RESERVED_14_Pos)
+
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_2_RESERVED_13_Pos                                                           17U
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_2_RESERVED_13_Msk                                                           (0x1UL << AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_2_RESERVED_13_Pos)
+
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_2_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_PERIPHERAL_ALL_RET_Pos                   18U
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_2_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_PERIPHERAL_ALL_RET_Msk                   (0x1UL << AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_2_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_PERIPHERAL_ALL_RET_Pos)
+
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_2_RESERVED_12_Pos                                                           19U
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_2_RESERVED_12_Msk                                                           (0x1UL << AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_2_RESERVED_12_Pos)
+
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_2_RESERVED_11_Pos                                                           20U
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_2_RESERVED_11_Msk                                                           (0x1UL << AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_2_RESERVED_11_Pos)
+
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_2_RESERVED_10_Pos                                                           21U
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_2_RESERVED_10_Msk                                                           (0x1UL << AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_2_RESERVED_10_Pos)
+
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_2_RESERVED_9_Pos                                                            22U
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_2_RESERVED_9_Msk                                                            (0x1UL << AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_2_RESERVED_9_Pos)
+
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_2_RESERVED_8_Pos                                                            23U
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_2_RESERVED_8_Msk                                                            (0x1UL << AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_2_RESERVED_8_Pos)
+
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_2_RESERVED_7_Pos                                                            24U
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_2_RESERVED_7_Msk                                                            (0x1UL << AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_2_RESERVED_7_Pos)
+
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_2_RESERVED_6_Pos                                                            25U
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_2_RESERVED_6_Msk                                                            (0x1UL << AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_2_RESERVED_6_Pos)
+
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_2_RESERVED_5_Pos                                                            26U
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_2_RESERVED_5_Msk                                                            (0x1UL << AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_2_RESERVED_5_Pos)
+
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_2_RESERVED_4_Pos                                                            27U
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_2_RESERVED_4_Msk                                                            (0x1UL << AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_2_RESERVED_4_Pos)
+
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_2_RESERVED_3_Pos                                                            28U
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_2_RESERVED_3_Msk                                                            (0x1UL << AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_2_RESERVED_3_Pos)
+
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_2_RESERVED_2_Pos                                                            29U
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_2_RESERVED_2_Msk                                                            (0x1UL << AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_2_RESERVED_2_Pos)
+
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_2_RESERVED_1_Pos                                                            30U
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_2_RESERVED_1_Msk                                                            (0x1UL << AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_2_RESERVED_1_Pos)
+
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_2_RESERVED_Pos                                                              31U
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_2_RESERVED_Msk                                                              (0x1UL << AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_2_RESERVED_Pos)
+
+/* 0xBE4    0x4000_0be4
+    0       R/W     RESERVED_31                                                 1'b1
+    1       R/W     RESERVED_30                                                 1'b1
+    2       R/W     RESERVED_29                                                 1'b0
+    3       R/W     RESERVED_28                                                 1'b1
+    4       R/W     RESERVED_27                                                 1'b0
+    5       R/W     RESERVED_26                                                 1'b1
+    6       R/W     RESERVED_25                                                 1'b0
+    7       R/W     RESERVED_24                                                 1'b1
+    8       R/W     RESERVED_23                                                 1'b0
+    9       R/W     RESERVED_22                                                 1'b1
+    10      R/W     RESERVED_21                                                 1'b0
+    11      R/W     RESERVED_20                                                 1'b1
+    12      R/W     RESERVED_19                                                 1'b0
+    13      R/W     RESERVED_18                                                 1'b1
+    14      R/W     RESERVED_17                                                 1'b0
+    15      R/W     RESERVED_16                                                 1'b1
+    16      R/W     RESERVED_15                                                 1'b0
+    17      R/W     RESERVED_14                                                 1'b1
+    18      R/W     RESERVED_13                                                 1'b0
+    19      R/W     RESERVED_12                                                 1'b1
+    20      R/W     RESERVED_11                                                 1'b0
+    21      R/W     RESERVED_10                                                 1'b1
+    22      R/W     RESERVED_9                                                  1'b0
+    23      R/W     RESERVED_8                                                  1'b1
+    24      R/W     RESERVED_7                                                  1'b0
+    25      R/W     RESERVED_6                                                  1'b1
+    26      R/W     RESERVED_5                                                  1'b0
+    27      R/W     RESERVED_4                                                  1'b1
+    28      R/W     RESERVED_3                                                  1'b0
+    29      R/W     RESERVED_2                                                  1'b1
+    30      R/W     RESERVED_1                                                  1'b0
+    31      R/W     RESERVED                                                    1'b1
+ */
+typedef union _AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_3_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED_31: 1;
+        uint32_t RESERVED_30: 1;
+        uint32_t RESERVED_29: 1;
+        uint32_t RESERVED_28: 1;
+        uint32_t RESERVED_27: 1;
+        uint32_t RESERVED_26: 1;
+        uint32_t RESERVED_25: 1;
+        uint32_t RESERVED_24: 1;
+        uint32_t RESERVED_23: 1;
+        uint32_t RESERVED_22: 1;
+        uint32_t RESERVED_21: 1;
+        uint32_t RESERVED_20: 1;
+        uint32_t RESERVED_19: 1;
+        uint32_t RESERVED_18: 1;
+        uint32_t RESERVED_17: 1;
+        uint32_t RESERVED_16: 1;
+        uint32_t RESERVED_15: 1;
+        uint32_t RESERVED_14: 1;
+        uint32_t RESERVED_13: 1;
+        uint32_t RESERVED_12: 1;
+        uint32_t RESERVED_11: 1;
+        uint32_t RESERVED_10: 1;
+        uint32_t RESERVED_9: 1;
+        uint32_t RESERVED_8: 1;
+        uint32_t RESERVED_7: 1;
+        uint32_t RESERVED_6: 1;
+        uint32_t RESERVED_5: 1;
+        uint32_t RESERVED_4: 1;
+        uint32_t RESERVED_3: 1;
+        uint32_t RESERVED_2: 1;
+        uint32_t RESERVED_1: 1;
+        uint32_t RESERVED: 1;
+    };
+} AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_3_TYPE;
+
+/*0x4000_0be4 AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_3*/
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_3_RESERVED_31_Pos                                                           0U
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_3_RESERVED_31_Msk                                                           (0x1UL << AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_3_RESERVED_31_Pos)
+
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_3_RESERVED_30_Pos                                                           1U
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_3_RESERVED_30_Msk                                                           (0x1UL << AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_3_RESERVED_30_Pos)
+
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_3_RESERVED_29_Pos                                                           2U
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_3_RESERVED_29_Msk                                                           (0x1UL << AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_3_RESERVED_29_Pos)
+
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_3_RESERVED_28_Pos                                                           3U
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_3_RESERVED_28_Msk                                                           (0x1UL << AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_3_RESERVED_28_Pos)
+
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_3_RESERVED_27_Pos                                                           4U
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_3_RESERVED_27_Msk                                                           (0x1UL << AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_3_RESERVED_27_Pos)
+
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_3_RESERVED_26_Pos                                                           5U
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_3_RESERVED_26_Msk                                                           (0x1UL << AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_3_RESERVED_26_Pos)
+
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_3_RESERVED_25_Pos                                                           6U
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_3_RESERVED_25_Msk                                                           (0x1UL << AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_3_RESERVED_25_Pos)
+
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_3_RESERVED_24_Pos                                                           7U
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_3_RESERVED_24_Msk                                                           (0x1UL << AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_3_RESERVED_24_Pos)
+
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_3_RESERVED_23_Pos                                                           8U
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_3_RESERVED_23_Msk                                                           (0x1UL << AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_3_RESERVED_23_Pos)
+
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_3_RESERVED_22_Pos                                                           9U
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_3_RESERVED_22_Msk                                                           (0x1UL << AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_3_RESERVED_22_Pos)
+
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_3_RESERVED_21_Pos                                                           10U
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_3_RESERVED_21_Msk                                                           (0x1UL << AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_3_RESERVED_21_Pos)
+
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_3_RESERVED_20_Pos                                                           11U
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_3_RESERVED_20_Msk                                                           (0x1UL << AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_3_RESERVED_20_Pos)
+
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_3_RESERVED_19_Pos                                                           12U
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_3_RESERVED_19_Msk                                                           (0x1UL << AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_3_RESERVED_19_Pos)
+
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_3_RESERVED_18_Pos                                                           13U
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_3_RESERVED_18_Msk                                                           (0x1UL << AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_3_RESERVED_18_Pos)
+
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_3_RESERVED_17_Pos                                                           14U
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_3_RESERVED_17_Msk                                                           (0x1UL << AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_3_RESERVED_17_Pos)
+
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_3_RESERVED_16_Pos                                                           15U
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_3_RESERVED_16_Msk                                                           (0x1UL << AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_3_RESERVED_16_Pos)
+
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_3_RESERVED_15_Pos                                                           16U
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_3_RESERVED_15_Msk                                                           (0x1UL << AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_3_RESERVED_15_Pos)
+
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_3_RESERVED_14_Pos                                                           17U
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_3_RESERVED_14_Msk                                                           (0x1UL << AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_3_RESERVED_14_Pos)
+
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_3_RESERVED_13_Pos                                                           18U
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_3_RESERVED_13_Msk                                                           (0x1UL << AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_3_RESERVED_13_Pos)
+
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_3_RESERVED_12_Pos                                                           19U
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_3_RESERVED_12_Msk                                                           (0x1UL << AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_3_RESERVED_12_Pos)
+
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_3_RESERVED_11_Pos                                                           20U
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_3_RESERVED_11_Msk                                                           (0x1UL << AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_3_RESERVED_11_Pos)
+
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_3_RESERVED_10_Pos                                                           21U
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_3_RESERVED_10_Msk                                                           (0x1UL << AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_3_RESERVED_10_Pos)
+
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_3_RESERVED_9_Pos                                                            22U
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_3_RESERVED_9_Msk                                                            (0x1UL << AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_3_RESERVED_9_Pos)
+
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_3_RESERVED_8_Pos                                                            23U
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_3_RESERVED_8_Msk                                                            (0x1UL << AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_3_RESERVED_8_Pos)
+
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_3_RESERVED_7_Pos                                                            24U
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_3_RESERVED_7_Msk                                                            (0x1UL << AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_3_RESERVED_7_Pos)
+
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_3_RESERVED_6_Pos                                                            25U
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_3_RESERVED_6_Msk                                                            (0x1UL << AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_3_RESERVED_6_Pos)
+
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_3_RESERVED_5_Pos                                                            26U
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_3_RESERVED_5_Msk                                                            (0x1UL << AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_3_RESERVED_5_Pos)
+
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_3_RESERVED_4_Pos                                                            27U
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_3_RESERVED_4_Msk                                                            (0x1UL << AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_3_RESERVED_4_Pos)
+
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_3_RESERVED_3_Pos                                                            28U
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_3_RESERVED_3_Msk                                                            (0x1UL << AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_3_RESERVED_3_Pos)
+
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_3_RESERVED_2_Pos                                                            29U
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_3_RESERVED_2_Msk                                                            (0x1UL << AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_3_RESERVED_2_Pos)
+
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_3_RESERVED_1_Pos                                                            30U
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_3_RESERVED_1_Msk                                                            (0x1UL << AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_3_RESERVED_1_Pos)
+
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_3_RESERVED_Pos                                                              31U
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_3_RESERVED_Msk                                                              (0x1UL << AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_3_RESERVED_Pos)
+
+/* 0xBE0    0x4000_0be0
+    25:0    R/W     RESERVED_4                                                  26'h0
+    26      R/W     RESERVED_3                                                  1'b1
+    27      R/W     RESERVED_2                                                  1'b1
+    28      R/W     RESERVED_1                                                  1'b1
+    29      R/W     RESERVED                                                    1'b1
+    30      R/W     LOP_POF_FULL_RET_PPU_VCORE1_PCSM_SRAM_SETTING_SEL           1'b1
+    31      R/W     LOP_POF_FULL_RET_PPU_VCORE1_PCSM_PAD_AUTO_SW_EN_RET         1'b1
+ */
+typedef union _AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_4_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED_4: 26;
+        uint32_t RESERVED_3: 1;
+        uint32_t RESERVED_2: 1;
+        uint32_t RESERVED_1: 1;
+        uint32_t RESERVED: 1;
+        uint32_t LOP_POF_FULL_RET_PPU_VCORE1_PCSM_SRAM_SETTING_SEL: 1;
+        uint32_t LOP_POF_FULL_RET_PPU_VCORE1_PCSM_PAD_AUTO_SW_EN_RET: 1;
+    };
+} AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_4_TYPE;
+
+/*0x4000_0be0 AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_4*/
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_4_RESERVED_4_Pos                                                            0U
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_4_RESERVED_4_Msk                                                            (0x3FFFFFFUL << AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_4_RESERVED_4_Pos)
+
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_4_RESERVED_3_Pos                                                            26U
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_4_RESERVED_3_Msk                                                            (0x1UL << AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_4_RESERVED_3_Pos)
+
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_4_RESERVED_2_Pos                                                            27U
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_4_RESERVED_2_Msk                                                            (0x1UL << AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_4_RESERVED_2_Pos)
+
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_4_RESERVED_1_Pos                                                            28U
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_4_RESERVED_1_Msk                                                            (0x1UL << AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_4_RESERVED_1_Pos)
+
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_4_RESERVED_Pos                                                              29U
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_4_RESERVED_Msk                                                              (0x1UL << AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_4_RESERVED_Pos)
+
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_4_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_SRAM_SETTING_SEL_Pos                     30U
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_4_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_SRAM_SETTING_SEL_Msk                     (0x1UL << AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_4_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_SRAM_SETTING_SEL_Pos)
+
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_4_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_PAD_AUTO_SW_EN_RET_Pos                   31U
+#define AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_4_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_PAD_AUTO_SW_EN_RET_Msk                   (0x1UL << AON_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_4_LOP_POF_FULL_RET_PPU_VCORE1_PCSM_PAD_AUTO_SW_EN_RET_Pos)
+
+/* 0xBDC    0x4000_0bdc
+    0       R/W     RESERVED_4                                                  1'b0
+    1       R/W     RESERVED_3                                                  1'b1
+    2       R/W     LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_RET2N_CPU                  1'b0
+    3       R/W     LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_RET2N_USB                  1'b0
+    4       R/W     LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_RET2N_CAN                  1'b0
+    5       R/W     LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_RET2N_LEBIS                1'b0
+    6       R/W     LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_RET2N_AUDIO                1'b0
+    7       R/W     LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_RET2N_BTPHY                1'b0
+    8       R/W     LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_RET2N_CCMP                 1'b0
+    9       R/W     LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_RET2N_SNPS                 1'b0
+    10      R/W     LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_RET1N_CPU                  1'b1
+    11      R/W     LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_RET1N_USB                  1'b1
+    12      R/W     LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_RET1N_CAN                  1'b1
+    13      R/W     LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_RET1N_LEBIS                1'b1
+    14      R/W     LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_RET1N_AUDIO                1'b1
+    15      R/W     LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_RET1N_BTPHY                1'b1
+    16      R/W     LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_RET1N_CCMP                 1'b1
+    17      R/W     LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_RET1N_SNPS                 1'b1
+    18      R/W     LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_PGEN_CPU                   1'b1
+    19      R/W     LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_PGEN_USB                   1'b1
+    20      R/W     LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_PGEN_CAN                   1'b1
+    21      R/W     LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_PGEN_LEBIS                 1'b1
+    22      R/W     LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_PGEN_AUDIO                 1'b1
+    23      R/W     LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_PGEN_BTPHY                 1'b1
+    24      R/W     LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_PGEN_CCMP                  1'b1
+    25      R/W     LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_PGEN_SNPS                  1'b1
+    26      R/W     LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_PGEN_ROM_0                 1'b1
+    27      R/W     RESERVED_2                                                  1'b1
+    28      R/W     RESERVED_1                                                  1'b1
+    29      R/W     RESERVED                                                    1'b0
+    30      R/W     LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_VCORE_PC_VG2               1'b0
+    31      R/W     LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_VCORE_PC_VG1               1'b0
+ */
+typedef union _AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_1_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED_4: 1;
+        uint32_t RESERVED_3: 1;
+        uint32_t LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_RET2N_CPU: 1;
+        uint32_t LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_RET2N_USB: 1;
+        uint32_t LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_RET2N_CAN: 1;
+        uint32_t LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_RET2N_LEBIS: 1;
+        uint32_t LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_RET2N_AUDIO: 1;
+        uint32_t LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_RET2N_BTPHY: 1;
+        uint32_t LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_RET2N_CCMP: 1;
+        uint32_t LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_RET2N_SNPS: 1;
+        uint32_t LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_RET1N_CPU: 1;
+        uint32_t LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_RET1N_USB: 1;
+        uint32_t LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_RET1N_CAN: 1;
+        uint32_t LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_RET1N_LEBIS: 1;
+        uint32_t LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_RET1N_AUDIO: 1;
+        uint32_t LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_RET1N_BTPHY: 1;
+        uint32_t LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_RET1N_CCMP: 1;
+        uint32_t LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_RET1N_SNPS: 1;
+        uint32_t LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_PGEN_CPU: 1;
+        uint32_t LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_PGEN_USB: 1;
+        uint32_t LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_PGEN_CAN: 1;
+        uint32_t LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_PGEN_LEBIS: 1;
+        uint32_t LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_PGEN_AUDIO: 1;
+        uint32_t LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_PGEN_BTPHY: 1;
+        uint32_t LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_PGEN_CCMP: 1;
+        uint32_t LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_PGEN_SNPS: 1;
+        uint32_t LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_PGEN_ROM_0: 1;
+        uint32_t RESERVED_2: 1;
+        uint32_t RESERVED_1: 1;
+        uint32_t RESERVED: 1;
+        uint32_t LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_VCORE_PC_VG2: 1;
+        uint32_t LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_VCORE_PC_VG1: 1;
+    };
+} AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_1_TYPE;
+
+/*0x4000_0bdc AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_1*/
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_1_RESERVED_4_Pos                                                            0U
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_1_RESERVED_4_Msk                                                            (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_1_RESERVED_4_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_1_RESERVED_3_Pos                                                            1U
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_1_RESERVED_3_Msk                                                            (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_1_RESERVED_3_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_1_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_RET2N_CPU_Pos                            2U
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_1_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_RET2N_CPU_Msk                            (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_1_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_RET2N_CPU_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_1_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_RET2N_USB_Pos                            3U
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_1_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_RET2N_USB_Msk                            (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_1_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_RET2N_USB_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_1_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_RET2N_CAN_Pos                            4U
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_1_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_RET2N_CAN_Msk                            (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_1_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_RET2N_CAN_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_1_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_RET2N_LEBIS_Pos                          5U
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_1_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_RET2N_LEBIS_Msk                          (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_1_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_RET2N_LEBIS_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_1_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_RET2N_AUDIO_Pos                          6U
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_1_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_RET2N_AUDIO_Msk                          (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_1_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_RET2N_AUDIO_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_1_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_RET2N_BTPHY_Pos                          7U
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_1_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_RET2N_BTPHY_Msk                          (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_1_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_RET2N_BTPHY_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_1_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_RET2N_CCMP_Pos                           8U
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_1_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_RET2N_CCMP_Msk                           (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_1_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_RET2N_CCMP_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_1_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_RET2N_SNPS_Pos                           9U
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_1_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_RET2N_SNPS_Msk                           (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_1_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_RET2N_SNPS_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_1_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_RET1N_CPU_Pos                            10U
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_1_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_RET1N_CPU_Msk                            (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_1_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_RET1N_CPU_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_1_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_RET1N_USB_Pos                            11U
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_1_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_RET1N_USB_Msk                            (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_1_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_RET1N_USB_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_1_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_RET1N_CAN_Pos                            12U
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_1_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_RET1N_CAN_Msk                            (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_1_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_RET1N_CAN_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_1_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_RET1N_LEBIS_Pos                          13U
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_1_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_RET1N_LEBIS_Msk                          (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_1_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_RET1N_LEBIS_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_1_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_RET1N_AUDIO_Pos                          14U
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_1_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_RET1N_AUDIO_Msk                          (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_1_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_RET1N_AUDIO_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_1_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_RET1N_BTPHY_Pos                          15U
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_1_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_RET1N_BTPHY_Msk                          (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_1_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_RET1N_BTPHY_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_1_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_RET1N_CCMP_Pos                           16U
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_1_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_RET1N_CCMP_Msk                           (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_1_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_RET1N_CCMP_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_1_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_RET1N_SNPS_Pos                           17U
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_1_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_RET1N_SNPS_Msk                           (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_1_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_RET1N_SNPS_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_1_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_PGEN_CPU_Pos                             18U
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_1_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_PGEN_CPU_Msk                             (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_1_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_PGEN_CPU_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_1_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_PGEN_USB_Pos                             19U
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_1_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_PGEN_USB_Msk                             (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_1_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_PGEN_USB_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_1_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_PGEN_CAN_Pos                             20U
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_1_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_PGEN_CAN_Msk                             (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_1_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_PGEN_CAN_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_1_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_PGEN_LEBIS_Pos                           21U
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_1_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_PGEN_LEBIS_Msk                           (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_1_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_PGEN_LEBIS_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_1_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_PGEN_AUDIO_Pos                           22U
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_1_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_PGEN_AUDIO_Msk                           (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_1_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_PGEN_AUDIO_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_1_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_PGEN_BTPHY_Pos                           23U
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_1_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_PGEN_BTPHY_Msk                           (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_1_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_PGEN_BTPHY_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_1_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_PGEN_CCMP_Pos                            24U
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_1_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_PGEN_CCMP_Msk                            (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_1_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_PGEN_CCMP_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_1_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_PGEN_SNPS_Pos                            25U
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_1_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_PGEN_SNPS_Msk                            (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_1_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_PGEN_SNPS_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_1_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_PGEN_ROM_0_Pos                           26U
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_1_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_PGEN_ROM_0_Msk                           (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_1_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_PGEN_ROM_0_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_1_RESERVED_2_Pos                                                            27U
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_1_RESERVED_2_Msk                                                            (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_1_RESERVED_2_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_1_RESERVED_1_Pos                                                            28U
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_1_RESERVED_1_Msk                                                            (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_1_RESERVED_1_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_1_RESERVED_Pos                                                              29U
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_1_RESERVED_Msk                                                              (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_1_RESERVED_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_1_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_VCORE_PC_VG2_Pos                         30U
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_1_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_VCORE_PC_VG2_Msk                         (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_1_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_VCORE_PC_VG2_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_1_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_VCORE_PC_VG1_Pos                         31U
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_1_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_VCORE_PC_VG1_Msk                         (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_1_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_VCORE_PC_VG1_Pos)
+
+/* 0xBD8    0x4000_0bd8
+    2:0     R/W     RESERVED_29                                                 3'h0
+    3       R/W     RESERVED_28                                                 1'b0
+    4       R/W     RESERVED_27                                                 1'b1
+    5       R/W     RESERVED_26                                                 1'b0
+    6       R/W     RESERVED_25                                                 1'b1
+    7       R/W     RESERVED_24                                                 1'b0
+    8       R/W     RESERVED_23                                                 1'b1
+    9       R/W     RESERVED_22                                                 1'b0
+    10      R/W     RESERVED_21                                                 1'b1
+    11      R/W     RESERVED_20                                                 1'b0
+    12      R/W     RESERVED_19                                                 1'b1
+    13      R/W     RESERVED_18                                                 1'b0
+    14      R/W     RESERVED_17                                                 1'b1
+    15      R/W     RESERVED_16                                                 1'b0
+    16      R/W     RESERVED_15                                                 1'b1
+    17      R/W     RESERVED_14                                                 1'b0
+    18      R/W     RESERVED_13                                                 1'b1
+    19      R/W     RESERVED_12                                                 1'b0
+    20      R/W     RESERVED_11                                                 1'b1
+    21      R/W     RESERVED_10                                                 1'b0
+    22      R/W     RESERVED_9                                                  1'b1
+    23      R/W     RESERVED_8                                                  1'b0
+    24      R/W     RESERVED_7                                                  1'b1
+    25      R/W     RESERVED_6                                                  1'b0
+    26      R/W     RESERVED_5                                                  1'b1
+    27      R/W     RESERVED_4                                                  1'b0
+    28      R/W     RESERVED_3                                                  1'b1
+    29      R/W     RESERVED_2                                                  1'b0
+    30      R/W     RESERVED_1                                                  1'b1
+    31      R/W     RESERVED                                                    1'b0
+ */
+typedef union _AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_2_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED_29: 3;
+        uint32_t RESERVED_28: 1;
+        uint32_t RESERVED_27: 1;
+        uint32_t RESERVED_26: 1;
+        uint32_t RESERVED_25: 1;
+        uint32_t RESERVED_24: 1;
+        uint32_t RESERVED_23: 1;
+        uint32_t RESERVED_22: 1;
+        uint32_t RESERVED_21: 1;
+        uint32_t RESERVED_20: 1;
+        uint32_t RESERVED_19: 1;
+        uint32_t RESERVED_18: 1;
+        uint32_t RESERVED_17: 1;
+        uint32_t RESERVED_16: 1;
+        uint32_t RESERVED_15: 1;
+        uint32_t RESERVED_14: 1;
+        uint32_t RESERVED_13: 1;
+        uint32_t RESERVED_12: 1;
+        uint32_t RESERVED_11: 1;
+        uint32_t RESERVED_10: 1;
+        uint32_t RESERVED_9: 1;
+        uint32_t RESERVED_8: 1;
+        uint32_t RESERVED_7: 1;
+        uint32_t RESERVED_6: 1;
+        uint32_t RESERVED_5: 1;
+        uint32_t RESERVED_4: 1;
+        uint32_t RESERVED_3: 1;
+        uint32_t RESERVED_2: 1;
+        uint32_t RESERVED_1: 1;
+        uint32_t RESERVED: 1;
+    };
+} AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_2_TYPE;
+
+/*0x4000_0bd8 AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_2*/
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_2_RESERVED_29_Pos                                                           0U
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_2_RESERVED_29_Msk                                                           (0x7UL << AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_2_RESERVED_29_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_2_RESERVED_28_Pos                                                           3U
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_2_RESERVED_28_Msk                                                           (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_2_RESERVED_28_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_2_RESERVED_27_Pos                                                           4U
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_2_RESERVED_27_Msk                                                           (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_2_RESERVED_27_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_2_RESERVED_26_Pos                                                           5U
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_2_RESERVED_26_Msk                                                           (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_2_RESERVED_26_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_2_RESERVED_25_Pos                                                           6U
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_2_RESERVED_25_Msk                                                           (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_2_RESERVED_25_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_2_RESERVED_24_Pos                                                           7U
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_2_RESERVED_24_Msk                                                           (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_2_RESERVED_24_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_2_RESERVED_23_Pos                                                           8U
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_2_RESERVED_23_Msk                                                           (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_2_RESERVED_23_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_2_RESERVED_22_Pos                                                           9U
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_2_RESERVED_22_Msk                                                           (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_2_RESERVED_22_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_2_RESERVED_21_Pos                                                           10U
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_2_RESERVED_21_Msk                                                           (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_2_RESERVED_21_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_2_RESERVED_20_Pos                                                           11U
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_2_RESERVED_20_Msk                                                           (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_2_RESERVED_20_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_2_RESERVED_19_Pos                                                           12U
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_2_RESERVED_19_Msk                                                           (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_2_RESERVED_19_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_2_RESERVED_18_Pos                                                           13U
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_2_RESERVED_18_Msk                                                           (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_2_RESERVED_18_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_2_RESERVED_17_Pos                                                           14U
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_2_RESERVED_17_Msk                                                           (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_2_RESERVED_17_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_2_RESERVED_16_Pos                                                           15U
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_2_RESERVED_16_Msk                                                           (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_2_RESERVED_16_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_2_RESERVED_15_Pos                                                           16U
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_2_RESERVED_15_Msk                                                           (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_2_RESERVED_15_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_2_RESERVED_14_Pos                                                           17U
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_2_RESERVED_14_Msk                                                           (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_2_RESERVED_14_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_2_RESERVED_13_Pos                                                           18U
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_2_RESERVED_13_Msk                                                           (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_2_RESERVED_13_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_2_RESERVED_12_Pos                                                           19U
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_2_RESERVED_12_Msk                                                           (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_2_RESERVED_12_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_2_RESERVED_11_Pos                                                           20U
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_2_RESERVED_11_Msk                                                           (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_2_RESERVED_11_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_2_RESERVED_10_Pos                                                           21U
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_2_RESERVED_10_Msk                                                           (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_2_RESERVED_10_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_2_RESERVED_9_Pos                                                            22U
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_2_RESERVED_9_Msk                                                            (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_2_RESERVED_9_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_2_RESERVED_8_Pos                                                            23U
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_2_RESERVED_8_Msk                                                            (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_2_RESERVED_8_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_2_RESERVED_7_Pos                                                            24U
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_2_RESERVED_7_Msk                                                            (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_2_RESERVED_7_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_2_RESERVED_6_Pos                                                            25U
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_2_RESERVED_6_Msk                                                            (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_2_RESERVED_6_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_2_RESERVED_5_Pos                                                            26U
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_2_RESERVED_5_Msk                                                            (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_2_RESERVED_5_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_2_RESERVED_4_Pos                                                            27U
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_2_RESERVED_4_Msk                                                            (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_2_RESERVED_4_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_2_RESERVED_3_Pos                                                            28U
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_2_RESERVED_3_Msk                                                            (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_2_RESERVED_3_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_2_RESERVED_2_Pos                                                            29U
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_2_RESERVED_2_Msk                                                            (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_2_RESERVED_2_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_2_RESERVED_1_Pos                                                            30U
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_2_RESERVED_1_Msk                                                            (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_2_RESERVED_1_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_2_RESERVED_Pos                                                              31U
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_2_RESERVED_Msk                                                              (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_2_RESERVED_Pos)
+
+/* 0xBD4    0x4000_0bd4
+    0       R/W     RESERVED_31                                                 1'b0
+    1       R/W     RESERVED_30                                                 1'b1
+    2       R/W     RESERVED_29                                                 1'b0
+    3       R/W     RESERVED_28                                                 1'b1
+    4       R/W     RESERVED_27                                                 1'b0
+    5       R/W     RESERVED_26                                                 1'b1
+    6       R/W     RESERVED_25                                                 1'b0
+    7       R/W     RESERVED_24                                                 1'b1
+    8       R/W     RESERVED_23                                                 1'b0
+    9       R/W     RESERVED_22                                                 1'b1
+    10      R/W     RESERVED_21                                                 1'b0
+    11      R/W     RESERVED_20                                                 1'b1
+    12      R/W     RESERVED_19                                                 1'b0
+    13      R/W     RESERVED_18                                                 1'b1
+    14      R/W     RESERVED_17                                                 1'b0
+    15      R/W     RESERVED_16                                                 1'b1
+    16      R/W     RESERVED_15                                                 1'b0
+    17      R/W     RESERVED_14                                                 1'b1
+    18      R/W     RESERVED_13                                                 1'b0
+    19      R/W     RESERVED_12                                                 1'b1
+    20      R/W     RESERVED_11                                                 1'b0
+    21      R/W     RESERVED_10                                                 1'b1
+    22      R/W     RESERVED_9                                                  1'b0
+    23      R/W     RESERVED_8                                                  1'b1
+    24      R/W     RESERVED_7                                                  1'b0
+    25      R/W     RESERVED_6                                                  1'b1
+    26      R/W     RESERVED_5                                                  1'b0
+    27      R/W     RESERVED_4                                                  1'b1
+    28      R/W     RESERVED_3                                                  1'b0
+    29      R/W     RESERVED_2                                                  1'b1
+    30      R/W     RESERVED_1                                                  1'b0
+    31      R/W     RESERVED                                                    1'b1
+ */
+typedef union _AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_3_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED_31: 1;
+        uint32_t RESERVED_30: 1;
+        uint32_t RESERVED_29: 1;
+        uint32_t RESERVED_28: 1;
+        uint32_t RESERVED_27: 1;
+        uint32_t RESERVED_26: 1;
+        uint32_t RESERVED_25: 1;
+        uint32_t RESERVED_24: 1;
+        uint32_t RESERVED_23: 1;
+        uint32_t RESERVED_22: 1;
+        uint32_t RESERVED_21: 1;
+        uint32_t RESERVED_20: 1;
+        uint32_t RESERVED_19: 1;
+        uint32_t RESERVED_18: 1;
+        uint32_t RESERVED_17: 1;
+        uint32_t RESERVED_16: 1;
+        uint32_t RESERVED_15: 1;
+        uint32_t RESERVED_14: 1;
+        uint32_t RESERVED_13: 1;
+        uint32_t RESERVED_12: 1;
+        uint32_t RESERVED_11: 1;
+        uint32_t RESERVED_10: 1;
+        uint32_t RESERVED_9: 1;
+        uint32_t RESERVED_8: 1;
+        uint32_t RESERVED_7: 1;
+        uint32_t RESERVED_6: 1;
+        uint32_t RESERVED_5: 1;
+        uint32_t RESERVED_4: 1;
+        uint32_t RESERVED_3: 1;
+        uint32_t RESERVED_2: 1;
+        uint32_t RESERVED_1: 1;
+        uint32_t RESERVED: 1;
+    };
+} AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_3_TYPE;
+
+/*0x4000_0bd4 AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_3*/
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_3_RESERVED_31_Pos                                                           0U
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_3_RESERVED_31_Msk                                                           (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_3_RESERVED_31_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_3_RESERVED_30_Pos                                                           1U
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_3_RESERVED_30_Msk                                                           (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_3_RESERVED_30_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_3_RESERVED_29_Pos                                                           2U
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_3_RESERVED_29_Msk                                                           (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_3_RESERVED_29_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_3_RESERVED_28_Pos                                                           3U
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_3_RESERVED_28_Msk                                                           (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_3_RESERVED_28_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_3_RESERVED_27_Pos                                                           4U
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_3_RESERVED_27_Msk                                                           (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_3_RESERVED_27_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_3_RESERVED_26_Pos                                                           5U
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_3_RESERVED_26_Msk                                                           (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_3_RESERVED_26_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_3_RESERVED_25_Pos                                                           6U
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_3_RESERVED_25_Msk                                                           (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_3_RESERVED_25_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_3_RESERVED_24_Pos                                                           7U
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_3_RESERVED_24_Msk                                                           (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_3_RESERVED_24_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_3_RESERVED_23_Pos                                                           8U
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_3_RESERVED_23_Msk                                                           (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_3_RESERVED_23_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_3_RESERVED_22_Pos                                                           9U
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_3_RESERVED_22_Msk                                                           (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_3_RESERVED_22_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_3_RESERVED_21_Pos                                                           10U
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_3_RESERVED_21_Msk                                                           (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_3_RESERVED_21_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_3_RESERVED_20_Pos                                                           11U
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_3_RESERVED_20_Msk                                                           (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_3_RESERVED_20_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_3_RESERVED_19_Pos                                                           12U
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_3_RESERVED_19_Msk                                                           (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_3_RESERVED_19_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_3_RESERVED_18_Pos                                                           13U
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_3_RESERVED_18_Msk                                                           (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_3_RESERVED_18_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_3_RESERVED_17_Pos                                                           14U
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_3_RESERVED_17_Msk                                                           (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_3_RESERVED_17_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_3_RESERVED_16_Pos                                                           15U
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_3_RESERVED_16_Msk                                                           (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_3_RESERVED_16_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_3_RESERVED_15_Pos                                                           16U
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_3_RESERVED_15_Msk                                                           (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_3_RESERVED_15_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_3_RESERVED_14_Pos                                                           17U
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_3_RESERVED_14_Msk                                                           (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_3_RESERVED_14_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_3_RESERVED_13_Pos                                                           18U
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_3_RESERVED_13_Msk                                                           (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_3_RESERVED_13_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_3_RESERVED_12_Pos                                                           19U
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_3_RESERVED_12_Msk                                                           (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_3_RESERVED_12_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_3_RESERVED_11_Pos                                                           20U
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_3_RESERVED_11_Msk                                                           (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_3_RESERVED_11_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_3_RESERVED_10_Pos                                                           21U
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_3_RESERVED_10_Msk                                                           (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_3_RESERVED_10_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_3_RESERVED_9_Pos                                                            22U
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_3_RESERVED_9_Msk                                                            (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_3_RESERVED_9_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_3_RESERVED_8_Pos                                                            23U
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_3_RESERVED_8_Msk                                                            (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_3_RESERVED_8_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_3_RESERVED_7_Pos                                                            24U
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_3_RESERVED_7_Msk                                                            (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_3_RESERVED_7_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_3_RESERVED_6_Pos                                                            25U
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_3_RESERVED_6_Msk                                                            (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_3_RESERVED_6_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_3_RESERVED_5_Pos                                                            26U
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_3_RESERVED_5_Msk                                                            (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_3_RESERVED_5_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_3_RESERVED_4_Pos                                                            27U
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_3_RESERVED_4_Msk                                                            (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_3_RESERVED_4_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_3_RESERVED_3_Pos                                                            28U
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_3_RESERVED_3_Msk                                                            (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_3_RESERVED_3_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_3_RESERVED_2_Pos                                                            29U
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_3_RESERVED_2_Msk                                                            (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_3_RESERVED_2_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_3_RESERVED_1_Pos                                                            30U
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_3_RESERVED_1_Msk                                                            (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_3_RESERVED_1_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_3_RESERVED_Pos                                                              31U
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_3_RESERVED_Msk                                                              (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_3_RESERVED_Pos)
+
+/* 0xBD0    0x4000_0bd0
+    28:0    R/W     RESERVED_1                                                  29'h0
+    29      R/W     RESERVED                                                    1'b0
+    30      R/W     LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_SRAM_SETTING_SEL           1'b0
+    31      R/W     LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_PAD_AUTO_SW_EN_RET         1'b0
+ */
+typedef union _AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_4_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED_1: 29;
+        uint32_t RESERVED: 1;
+        uint32_t LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_SRAM_SETTING_SEL: 1;
+        uint32_t LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_PAD_AUTO_SW_EN_RET: 1;
+    };
+} AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_4_TYPE;
+
+/*0x4000_0bd0 AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_4*/
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_4_RESERVED_1_Pos                                                            0U
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_4_RESERVED_1_Msk                                                            (0x1FFFFFFFUL << AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_4_RESERVED_1_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_4_RESERVED_Pos                                                              29U
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_4_RESERVED_Msk                                                              (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_4_RESERVED_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_4_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_SRAM_SETTING_SEL_Pos                     30U
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_4_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_SRAM_SETTING_SEL_Msk                     (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_4_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_SRAM_SETTING_SEL_Pos)
+
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_4_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_PAD_AUTO_SW_EN_RET_Pos                   31U
+#define AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_4_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_PAD_AUTO_SW_EN_RET_Msk                   (0x1UL << AON_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_4_LOP_POF_FUNC_RET_PPU_VCORE1_PCSM_PAD_AUTO_SW_EN_RET_Pos)
+
+/* 0xBCC    0x4000_0bcc
+    7:0     R/W     RESERVED_6                                                  8'h0
+    11:8    R/W     RESERVED_5                                                  4'b0000
+    15:12   R/W     RESERVED_4                                                  4'b0000
+    19:16   R/W     RESERVED_3                                                  4'b0000
+    23:20   R/W     RESERVED_2                                                  4'b0001
+    27:24   R/W     RESERVED_1                                                  4'b0001
+    31:28   R/W     RESERVED                                                    4'b0001
+ */
+typedef union _AON_LOP_POF_OFF_PPU_VCORE1_PCSM_DELAY_1_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED_6: 8;
+        uint32_t RESERVED_5: 4;
+        uint32_t RESERVED_4: 4;
+        uint32_t RESERVED_3: 4;
+        uint32_t RESERVED_2: 4;
+        uint32_t RESERVED_1: 4;
+        uint32_t RESERVED: 4;
+    };
+} AON_LOP_POF_OFF_PPU_VCORE1_PCSM_DELAY_1_TYPE;
+
+/*0x4000_0bcc AON_LOP_POF_OFF_PPU_VCORE1_PCSM_DELAY_1*/
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_DELAY_1_RESERVED_6_Pos                                                           0U
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_DELAY_1_RESERVED_6_Msk                                                           (0xFFUL << AON_LOP_POF_OFF_PPU_VCORE1_PCSM_DELAY_1_RESERVED_6_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_DELAY_1_RESERVED_5_Pos                                                           8U
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_DELAY_1_RESERVED_5_Msk                                                           (0xFUL << AON_LOP_POF_OFF_PPU_VCORE1_PCSM_DELAY_1_RESERVED_5_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_DELAY_1_RESERVED_4_Pos                                                           12U
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_DELAY_1_RESERVED_4_Msk                                                           (0xFUL << AON_LOP_POF_OFF_PPU_VCORE1_PCSM_DELAY_1_RESERVED_4_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_DELAY_1_RESERVED_3_Pos                                                           16U
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_DELAY_1_RESERVED_3_Msk                                                           (0xFUL << AON_LOP_POF_OFF_PPU_VCORE1_PCSM_DELAY_1_RESERVED_3_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_DELAY_1_RESERVED_2_Pos                                                           20U
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_DELAY_1_RESERVED_2_Msk                                                           (0xFUL << AON_LOP_POF_OFF_PPU_VCORE1_PCSM_DELAY_1_RESERVED_2_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_DELAY_1_RESERVED_1_Pos                                                           24U
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_DELAY_1_RESERVED_1_Msk                                                           (0xFUL << AON_LOP_POF_OFF_PPU_VCORE1_PCSM_DELAY_1_RESERVED_1_Pos)
+
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_DELAY_1_RESERVED_Pos                                                             28U
+#define AON_LOP_POF_OFF_PPU_VCORE1_PCSM_DELAY_1_RESERVED_Msk                                                             (0xFUL << AON_LOP_POF_OFF_PPU_VCORE1_PCSM_DELAY_1_RESERVED_Pos)
+
+/* 0xC2C    0x4000_0c2c
+    3:0     R/W     RESERVED_16                                                 4'b0000
+    7:4     R/W     RESERVED_15                                                 4'b0000
+    11:8    R/W     RESERVED_14                                                 4'b0000
+    15:12   R/W     RESERVED_13                                                 4'b0000
+    19:16   R/W     RESERVED_12                                                 4'b0000
+    20      R/W     RESERVED_11                                                 1'b1
+    21      R/W     RESERVED_10                                                 1'b1
+    22      R/W     RESERVED_9                                                  1'b0
+    23      R/W     RESERVED_8                                                  1'b1
+    24      R/W     RESERVED_7                                                  1'b1
+    25      R/W     RESERVED_6                                                  1'b0
+    26      R/W     RESERVED_5                                                  1'b0
+    27      R/W     RESERVED_4                                                  1'b1
+    28      R/W     RESERVED_3                                                  1'b0
+    29      R/W     RESERVED_2                                                  1'b0
+    30      R/W     RESERVED_1                                                  1'b0
+    31      R/W     RESERVED                                                    1'b0
+ */
+typedef union _AON_LOP_PON_VPON_VCORE1_OP1_PCSM_1_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED_16: 4;
+        uint32_t RESERVED_15: 4;
+        uint32_t RESERVED_14: 4;
+        uint32_t RESERVED_13: 4;
+        uint32_t RESERVED_12: 4;
+        uint32_t RESERVED_11: 1;
+        uint32_t RESERVED_10: 1;
+        uint32_t RESERVED_9: 1;
+        uint32_t RESERVED_8: 1;
+        uint32_t RESERVED_7: 1;
+        uint32_t RESERVED_6: 1;
+        uint32_t RESERVED_5: 1;
+        uint32_t RESERVED_4: 1;
+        uint32_t RESERVED_3: 1;
+        uint32_t RESERVED_2: 1;
+        uint32_t RESERVED_1: 1;
+        uint32_t RESERVED: 1;
+    };
+} AON_LOP_PON_VPON_VCORE1_OP1_PCSM_1_TYPE;
+
+/*0x4000_0c2c AON_LOP_PON_VPON_VCORE1_OP1_PCSM_1*/
+#define AON_LOP_PON_VPON_VCORE1_OP1_PCSM_1_RESERVED_16_Pos                                                               0U
+#define AON_LOP_PON_VPON_VCORE1_OP1_PCSM_1_RESERVED_16_Msk                                                               (0xFUL << AON_LOP_PON_VPON_VCORE1_OP1_PCSM_1_RESERVED_16_Pos)
+
+#define AON_LOP_PON_VPON_VCORE1_OP1_PCSM_1_RESERVED_15_Pos                                                               4U
+#define AON_LOP_PON_VPON_VCORE1_OP1_PCSM_1_RESERVED_15_Msk                                                               (0xFUL << AON_LOP_PON_VPON_VCORE1_OP1_PCSM_1_RESERVED_15_Pos)
+
+#define AON_LOP_PON_VPON_VCORE1_OP1_PCSM_1_RESERVED_14_Pos                                                               8U
+#define AON_LOP_PON_VPON_VCORE1_OP1_PCSM_1_RESERVED_14_Msk                                                               (0xFUL << AON_LOP_PON_VPON_VCORE1_OP1_PCSM_1_RESERVED_14_Pos)
+
+#define AON_LOP_PON_VPON_VCORE1_OP1_PCSM_1_RESERVED_13_Pos                                                               12U
+#define AON_LOP_PON_VPON_VCORE1_OP1_PCSM_1_RESERVED_13_Msk                                                               (0xFUL << AON_LOP_PON_VPON_VCORE1_OP1_PCSM_1_RESERVED_13_Pos)
+
+#define AON_LOP_PON_VPON_VCORE1_OP1_PCSM_1_RESERVED_12_Pos                                                               16U
+#define AON_LOP_PON_VPON_VCORE1_OP1_PCSM_1_RESERVED_12_Msk                                                               (0xFUL << AON_LOP_PON_VPON_VCORE1_OP1_PCSM_1_RESERVED_12_Pos)
+
+#define AON_LOP_PON_VPON_VCORE1_OP1_PCSM_1_RESERVED_11_Pos                                                               20U
+#define AON_LOP_PON_VPON_VCORE1_OP1_PCSM_1_RESERVED_11_Msk                                                               (0x1UL << AON_LOP_PON_VPON_VCORE1_OP1_PCSM_1_RESERVED_11_Pos)
+
+#define AON_LOP_PON_VPON_VCORE1_OP1_PCSM_1_RESERVED_10_Pos                                                               21U
+#define AON_LOP_PON_VPON_VCORE1_OP1_PCSM_1_RESERVED_10_Msk                                                               (0x1UL << AON_LOP_PON_VPON_VCORE1_OP1_PCSM_1_RESERVED_10_Pos)
+
+#define AON_LOP_PON_VPON_VCORE1_OP1_PCSM_1_RESERVED_9_Pos                                                                22U
+#define AON_LOP_PON_VPON_VCORE1_OP1_PCSM_1_RESERVED_9_Msk                                                                (0x1UL << AON_LOP_PON_VPON_VCORE1_OP1_PCSM_1_RESERVED_9_Pos)
+
+#define AON_LOP_PON_VPON_VCORE1_OP1_PCSM_1_RESERVED_8_Pos                                                                23U
+#define AON_LOP_PON_VPON_VCORE1_OP1_PCSM_1_RESERVED_8_Msk                                                                (0x1UL << AON_LOP_PON_VPON_VCORE1_OP1_PCSM_1_RESERVED_8_Pos)
+
+#define AON_LOP_PON_VPON_VCORE1_OP1_PCSM_1_RESERVED_7_Pos                                                                24U
+#define AON_LOP_PON_VPON_VCORE1_OP1_PCSM_1_RESERVED_7_Msk                                                                (0x1UL << AON_LOP_PON_VPON_VCORE1_OP1_PCSM_1_RESERVED_7_Pos)
+
+#define AON_LOP_PON_VPON_VCORE1_OP1_PCSM_1_RESERVED_6_Pos                                                                25U
+#define AON_LOP_PON_VPON_VCORE1_OP1_PCSM_1_RESERVED_6_Msk                                                                (0x1UL << AON_LOP_PON_VPON_VCORE1_OP1_PCSM_1_RESERVED_6_Pos)
+
+#define AON_LOP_PON_VPON_VCORE1_OP1_PCSM_1_RESERVED_5_Pos                                                                26U
+#define AON_LOP_PON_VPON_VCORE1_OP1_PCSM_1_RESERVED_5_Msk                                                                (0x1UL << AON_LOP_PON_VPON_VCORE1_OP1_PCSM_1_RESERVED_5_Pos)
+
+#define AON_LOP_PON_VPON_VCORE1_OP1_PCSM_1_RESERVED_4_Pos                                                                27U
+#define AON_LOP_PON_VPON_VCORE1_OP1_PCSM_1_RESERVED_4_Msk                                                                (0x1UL << AON_LOP_PON_VPON_VCORE1_OP1_PCSM_1_RESERVED_4_Pos)
+
+#define AON_LOP_PON_VPON_VCORE1_OP1_PCSM_1_RESERVED_3_Pos                                                                28U
+#define AON_LOP_PON_VPON_VCORE1_OP1_PCSM_1_RESERVED_3_Msk                                                                (0x1UL << AON_LOP_PON_VPON_VCORE1_OP1_PCSM_1_RESERVED_3_Pos)
+
+#define AON_LOP_PON_VPON_VCORE1_OP1_PCSM_1_RESERVED_2_Pos                                                                29U
+#define AON_LOP_PON_VPON_VCORE1_OP1_PCSM_1_RESERVED_2_Msk                                                                (0x1UL << AON_LOP_PON_VPON_VCORE1_OP1_PCSM_1_RESERVED_2_Pos)
+
+#define AON_LOP_PON_VPON_VCORE1_OP1_PCSM_1_RESERVED_1_Pos                                                                30U
+#define AON_LOP_PON_VPON_VCORE1_OP1_PCSM_1_RESERVED_1_Msk                                                                (0x1UL << AON_LOP_PON_VPON_VCORE1_OP1_PCSM_1_RESERVED_1_Pos)
+
+#define AON_LOP_PON_VPON_VCORE1_OP1_PCSM_1_RESERVED_Pos                                                                  31U
+#define AON_LOP_PON_VPON_VCORE1_OP1_PCSM_1_RESERVED_Msk                                                                  (0x1UL << AON_LOP_PON_VPON_VCORE1_OP1_PCSM_1_RESERVED_Pos)
+
+/* 0xC28    0x4000_0c28
+    10:0    R/W     RESERVED_18                                                 11'h0
+    11      R/W     RESERVED_17                                                 1'b1
+    12      R/W     RESERVED_16                                                 1'b1
+    13      R/W     RESERVED_15                                                 1'b1
+    14      R/W     RESERVED_14                                                 1'b1
+    15      R/W     RESERVED_13                                                 1'b1
+    16      R/W     RESERVED_12                                                 1'b1
+    17      R/W     RESERVED_11                                                 1'b1
+    18      R/W     RESERVED_10                                                 1'b0
+    19      R/W     RESERVED_9                                                  1'b1
+    20      R/W     RESERVED_8                                                  1'b1
+    21      R/W     RESERVED_7                                                  1'b1
+    22      R/W     RESERVED_6                                                  1'b0
+    23      R/W     RESERVED_5                                                  1'b1
+    24      R/W     RESERVED_4                                                  1'b1
+    25      R/W     RESERVED_3                                                  1'b1
+    26      R/W     RESERVED_2                                                  1'b1
+    30:27   R/W     RESERVED_1                                                  4'b0001
+    31      R/W     RESERVED                                                    1'b1
+ */
+typedef union _AON_LOP_PON_VPON_VCORE1_OP1_PCSM_2_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED_18: 11;
+        uint32_t RESERVED_17: 1;
+        uint32_t RESERVED_16: 1;
+        uint32_t RESERVED_15: 1;
+        uint32_t RESERVED_14: 1;
+        uint32_t RESERVED_13: 1;
+        uint32_t RESERVED_12: 1;
+        uint32_t RESERVED_11: 1;
+        uint32_t RESERVED_10: 1;
+        uint32_t RESERVED_9: 1;
+        uint32_t RESERVED_8: 1;
+        uint32_t RESERVED_7: 1;
+        uint32_t RESERVED_6: 1;
+        uint32_t RESERVED_5: 1;
+        uint32_t RESERVED_4: 1;
+        uint32_t RESERVED_3: 1;
+        uint32_t RESERVED_2: 1;
+        uint32_t RESERVED_1: 4;
+        uint32_t RESERVED: 1;
+    };
+} AON_LOP_PON_VPON_VCORE1_OP1_PCSM_2_TYPE;
+
+/*0x4000_0c28 AON_LOP_PON_VPON_VCORE1_OP1_PCSM_2*/
+#define AON_LOP_PON_VPON_VCORE1_OP1_PCSM_2_RESERVED_18_Pos                                                               0U
+#define AON_LOP_PON_VPON_VCORE1_OP1_PCSM_2_RESERVED_18_Msk                                                               (0x7FFUL << AON_LOP_PON_VPON_VCORE1_OP1_PCSM_2_RESERVED_18_Pos)
+
+#define AON_LOP_PON_VPON_VCORE1_OP1_PCSM_2_RESERVED_17_Pos                                                               11U
+#define AON_LOP_PON_VPON_VCORE1_OP1_PCSM_2_RESERVED_17_Msk                                                               (0x1UL << AON_LOP_PON_VPON_VCORE1_OP1_PCSM_2_RESERVED_17_Pos)
+
+#define AON_LOP_PON_VPON_VCORE1_OP1_PCSM_2_RESERVED_16_Pos                                                               12U
+#define AON_LOP_PON_VPON_VCORE1_OP1_PCSM_2_RESERVED_16_Msk                                                               (0x1UL << AON_LOP_PON_VPON_VCORE1_OP1_PCSM_2_RESERVED_16_Pos)
+
+#define AON_LOP_PON_VPON_VCORE1_OP1_PCSM_2_RESERVED_15_Pos                                                               13U
+#define AON_LOP_PON_VPON_VCORE1_OP1_PCSM_2_RESERVED_15_Msk                                                               (0x1UL << AON_LOP_PON_VPON_VCORE1_OP1_PCSM_2_RESERVED_15_Pos)
+
+#define AON_LOP_PON_VPON_VCORE1_OP1_PCSM_2_RESERVED_14_Pos                                                               14U
+#define AON_LOP_PON_VPON_VCORE1_OP1_PCSM_2_RESERVED_14_Msk                                                               (0x1UL << AON_LOP_PON_VPON_VCORE1_OP1_PCSM_2_RESERVED_14_Pos)
+
+#define AON_LOP_PON_VPON_VCORE1_OP1_PCSM_2_RESERVED_13_Pos                                                               15U
+#define AON_LOP_PON_VPON_VCORE1_OP1_PCSM_2_RESERVED_13_Msk                                                               (0x1UL << AON_LOP_PON_VPON_VCORE1_OP1_PCSM_2_RESERVED_13_Pos)
+
+#define AON_LOP_PON_VPON_VCORE1_OP1_PCSM_2_RESERVED_12_Pos                                                               16U
+#define AON_LOP_PON_VPON_VCORE1_OP1_PCSM_2_RESERVED_12_Msk                                                               (0x1UL << AON_LOP_PON_VPON_VCORE1_OP1_PCSM_2_RESERVED_12_Pos)
+
+#define AON_LOP_PON_VPON_VCORE1_OP1_PCSM_2_RESERVED_11_Pos                                                               17U
+#define AON_LOP_PON_VPON_VCORE1_OP1_PCSM_2_RESERVED_11_Msk                                                               (0x1UL << AON_LOP_PON_VPON_VCORE1_OP1_PCSM_2_RESERVED_11_Pos)
+
+#define AON_LOP_PON_VPON_VCORE1_OP1_PCSM_2_RESERVED_10_Pos                                                               18U
+#define AON_LOP_PON_VPON_VCORE1_OP1_PCSM_2_RESERVED_10_Msk                                                               (0x1UL << AON_LOP_PON_VPON_VCORE1_OP1_PCSM_2_RESERVED_10_Pos)
+
+#define AON_LOP_PON_VPON_VCORE1_OP1_PCSM_2_RESERVED_9_Pos                                                                19U
+#define AON_LOP_PON_VPON_VCORE1_OP1_PCSM_2_RESERVED_9_Msk                                                                (0x1UL << AON_LOP_PON_VPON_VCORE1_OP1_PCSM_2_RESERVED_9_Pos)
+
+#define AON_LOP_PON_VPON_VCORE1_OP1_PCSM_2_RESERVED_8_Pos                                                                20U
+#define AON_LOP_PON_VPON_VCORE1_OP1_PCSM_2_RESERVED_8_Msk                                                                (0x1UL << AON_LOP_PON_VPON_VCORE1_OP1_PCSM_2_RESERVED_8_Pos)
+
+#define AON_LOP_PON_VPON_VCORE1_OP1_PCSM_2_RESERVED_7_Pos                                                                21U
+#define AON_LOP_PON_VPON_VCORE1_OP1_PCSM_2_RESERVED_7_Msk                                                                (0x1UL << AON_LOP_PON_VPON_VCORE1_OP1_PCSM_2_RESERVED_7_Pos)
+
+#define AON_LOP_PON_VPON_VCORE1_OP1_PCSM_2_RESERVED_6_Pos                                                                22U
+#define AON_LOP_PON_VPON_VCORE1_OP1_PCSM_2_RESERVED_6_Msk                                                                (0x1UL << AON_LOP_PON_VPON_VCORE1_OP1_PCSM_2_RESERVED_6_Pos)
+
+#define AON_LOP_PON_VPON_VCORE1_OP1_PCSM_2_RESERVED_5_Pos                                                                23U
+#define AON_LOP_PON_VPON_VCORE1_OP1_PCSM_2_RESERVED_5_Msk                                                                (0x1UL << AON_LOP_PON_VPON_VCORE1_OP1_PCSM_2_RESERVED_5_Pos)
+
+#define AON_LOP_PON_VPON_VCORE1_OP1_PCSM_2_RESERVED_4_Pos                                                                24U
+#define AON_LOP_PON_VPON_VCORE1_OP1_PCSM_2_RESERVED_4_Msk                                                                (0x1UL << AON_LOP_PON_VPON_VCORE1_OP1_PCSM_2_RESERVED_4_Pos)
+
+#define AON_LOP_PON_VPON_VCORE1_OP1_PCSM_2_RESERVED_3_Pos                                                                25U
+#define AON_LOP_PON_VPON_VCORE1_OP1_PCSM_2_RESERVED_3_Msk                                                                (0x1UL << AON_LOP_PON_VPON_VCORE1_OP1_PCSM_2_RESERVED_3_Pos)
+
+#define AON_LOP_PON_VPON_VCORE1_OP1_PCSM_2_RESERVED_2_Pos                                                                26U
+#define AON_LOP_PON_VPON_VCORE1_OP1_PCSM_2_RESERVED_2_Msk                                                                (0x1UL << AON_LOP_PON_VPON_VCORE1_OP1_PCSM_2_RESERVED_2_Pos)
+
+#define AON_LOP_PON_VPON_VCORE1_OP1_PCSM_2_RESERVED_1_Pos                                                                27U
+#define AON_LOP_PON_VPON_VCORE1_OP1_PCSM_2_RESERVED_1_Msk                                                                (0xFUL << AON_LOP_PON_VPON_VCORE1_OP1_PCSM_2_RESERVED_1_Pos)
+
+#define AON_LOP_PON_VPON_VCORE1_OP1_PCSM_2_RESERVED_Pos                                                                  31U
+#define AON_LOP_PON_VPON_VCORE1_OP1_PCSM_2_RESERVED_Msk                                                                  (0x1UL << AON_LOP_PON_VPON_VCORE1_OP1_PCSM_2_RESERVED_Pos)
+
+/* 0xC44    0x4000_0c44
+    3:0     R/W     RESERVED_16                                                 4'b0000
+    7:4     R/W     RESERVED_15                                                 4'b0001
+    11:8    R/W     RESERVED_14                                                 4'b0000
+    15:12   R/W     RESERVED_13                                                 4'b0000
+    19:16   R/W     RESERVED_12                                                 4'b0101
+    20      R/W     RESERVED_11                                                 1'b0
+    21      R/W     RESERVED_10                                                 1'b0
+    22      R/W     RESERVED_9                                                  1'b1
+    23      R/W     RESERVED_8                                                  1'b1
+    24      R/W     RESERVED_7                                                  1'b0
+    25      R/W     RESERVED_6                                                  1'b0
+    26      R/W     RESERVED_5                                                  1'b1
+    27      R/W     RESERVED_4                                                  1'b0
+    28      R/W     RESERVED_3                                                  1'b0
+    29      R/W     RESERVED_2                                                  1'b0
+    30      R/W     RESERVED_1                                                  1'b1
+    31      R/W     RESERVED                                                    1'b1
+ */
+typedef union _AON_LOP_POF_VPON_VCORE1_OP1_PCSM_1_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED_16: 4;
+        uint32_t RESERVED_15: 4;
+        uint32_t RESERVED_14: 4;
+        uint32_t RESERVED_13: 4;
+        uint32_t RESERVED_12: 4;
+        uint32_t RESERVED_11: 1;
+        uint32_t RESERVED_10: 1;
+        uint32_t RESERVED_9: 1;
+        uint32_t RESERVED_8: 1;
+        uint32_t RESERVED_7: 1;
+        uint32_t RESERVED_6: 1;
+        uint32_t RESERVED_5: 1;
+        uint32_t RESERVED_4: 1;
+        uint32_t RESERVED_3: 1;
+        uint32_t RESERVED_2: 1;
+        uint32_t RESERVED_1: 1;
+        uint32_t RESERVED: 1;
+    };
+} AON_LOP_POF_VPON_VCORE1_OP1_PCSM_1_TYPE;
+
+/*0x4000_0c44 AON_LOP_POF_VPON_VCORE1_OP1_PCSM_1*/
+#define AON_LOP_POF_VPON_VCORE1_OP1_PCSM_1_RESERVED_16_Pos                                                               0U
+#define AON_LOP_POF_VPON_VCORE1_OP1_PCSM_1_RESERVED_16_Msk                                                               (0xFUL << AON_LOP_POF_VPON_VCORE1_OP1_PCSM_1_RESERVED_16_Pos)
+
+#define AON_LOP_POF_VPON_VCORE1_OP1_PCSM_1_RESERVED_15_Pos                                                               4U
+#define AON_LOP_POF_VPON_VCORE1_OP1_PCSM_1_RESERVED_15_Msk                                                               (0xFUL << AON_LOP_POF_VPON_VCORE1_OP1_PCSM_1_RESERVED_15_Pos)
+
+#define AON_LOP_POF_VPON_VCORE1_OP1_PCSM_1_RESERVED_14_Pos                                                               8U
+#define AON_LOP_POF_VPON_VCORE1_OP1_PCSM_1_RESERVED_14_Msk                                                               (0xFUL << AON_LOP_POF_VPON_VCORE1_OP1_PCSM_1_RESERVED_14_Pos)
+
+#define AON_LOP_POF_VPON_VCORE1_OP1_PCSM_1_RESERVED_13_Pos                                                               12U
+#define AON_LOP_POF_VPON_VCORE1_OP1_PCSM_1_RESERVED_13_Msk                                                               (0xFUL << AON_LOP_POF_VPON_VCORE1_OP1_PCSM_1_RESERVED_13_Pos)
+
+#define AON_LOP_POF_VPON_VCORE1_OP1_PCSM_1_RESERVED_12_Pos                                                               16U
+#define AON_LOP_POF_VPON_VCORE1_OP1_PCSM_1_RESERVED_12_Msk                                                               (0xFUL << AON_LOP_POF_VPON_VCORE1_OP1_PCSM_1_RESERVED_12_Pos)
+
+#define AON_LOP_POF_VPON_VCORE1_OP1_PCSM_1_RESERVED_11_Pos                                                               20U
+#define AON_LOP_POF_VPON_VCORE1_OP1_PCSM_1_RESERVED_11_Msk                                                               (0x1UL << AON_LOP_POF_VPON_VCORE1_OP1_PCSM_1_RESERVED_11_Pos)
+
+#define AON_LOP_POF_VPON_VCORE1_OP1_PCSM_1_RESERVED_10_Pos                                                               21U
+#define AON_LOP_POF_VPON_VCORE1_OP1_PCSM_1_RESERVED_10_Msk                                                               (0x1UL << AON_LOP_POF_VPON_VCORE1_OP1_PCSM_1_RESERVED_10_Pos)
+
+#define AON_LOP_POF_VPON_VCORE1_OP1_PCSM_1_RESERVED_9_Pos                                                                22U
+#define AON_LOP_POF_VPON_VCORE1_OP1_PCSM_1_RESERVED_9_Msk                                                                (0x1UL << AON_LOP_POF_VPON_VCORE1_OP1_PCSM_1_RESERVED_9_Pos)
+
+#define AON_LOP_POF_VPON_VCORE1_OP1_PCSM_1_RESERVED_8_Pos                                                                23U
+#define AON_LOP_POF_VPON_VCORE1_OP1_PCSM_1_RESERVED_8_Msk                                                                (0x1UL << AON_LOP_POF_VPON_VCORE1_OP1_PCSM_1_RESERVED_8_Pos)
+
+#define AON_LOP_POF_VPON_VCORE1_OP1_PCSM_1_RESERVED_7_Pos                                                                24U
+#define AON_LOP_POF_VPON_VCORE1_OP1_PCSM_1_RESERVED_7_Msk                                                                (0x1UL << AON_LOP_POF_VPON_VCORE1_OP1_PCSM_1_RESERVED_7_Pos)
+
+#define AON_LOP_POF_VPON_VCORE1_OP1_PCSM_1_RESERVED_6_Pos                                                                25U
+#define AON_LOP_POF_VPON_VCORE1_OP1_PCSM_1_RESERVED_6_Msk                                                                (0x1UL << AON_LOP_POF_VPON_VCORE1_OP1_PCSM_1_RESERVED_6_Pos)
+
+#define AON_LOP_POF_VPON_VCORE1_OP1_PCSM_1_RESERVED_5_Pos                                                                26U
+#define AON_LOP_POF_VPON_VCORE1_OP1_PCSM_1_RESERVED_5_Msk                                                                (0x1UL << AON_LOP_POF_VPON_VCORE1_OP1_PCSM_1_RESERVED_5_Pos)
+
+#define AON_LOP_POF_VPON_VCORE1_OP1_PCSM_1_RESERVED_4_Pos                                                                27U
+#define AON_LOP_POF_VPON_VCORE1_OP1_PCSM_1_RESERVED_4_Msk                                                                (0x1UL << AON_LOP_POF_VPON_VCORE1_OP1_PCSM_1_RESERVED_4_Pos)
+
+#define AON_LOP_POF_VPON_VCORE1_OP1_PCSM_1_RESERVED_3_Pos                                                                28U
+#define AON_LOP_POF_VPON_VCORE1_OP1_PCSM_1_RESERVED_3_Msk                                                                (0x1UL << AON_LOP_POF_VPON_VCORE1_OP1_PCSM_1_RESERVED_3_Pos)
+
+#define AON_LOP_POF_VPON_VCORE1_OP1_PCSM_1_RESERVED_2_Pos                                                                29U
+#define AON_LOP_POF_VPON_VCORE1_OP1_PCSM_1_RESERVED_2_Msk                                                                (0x1UL << AON_LOP_POF_VPON_VCORE1_OP1_PCSM_1_RESERVED_2_Pos)
+
+#define AON_LOP_POF_VPON_VCORE1_OP1_PCSM_1_RESERVED_1_Pos                                                                30U
+#define AON_LOP_POF_VPON_VCORE1_OP1_PCSM_1_RESERVED_1_Msk                                                                (0x1UL << AON_LOP_POF_VPON_VCORE1_OP1_PCSM_1_RESERVED_1_Pos)
+
+#define AON_LOP_POF_VPON_VCORE1_OP1_PCSM_1_RESERVED_Pos                                                                  31U
+#define AON_LOP_POF_VPON_VCORE1_OP1_PCSM_1_RESERVED_Msk                                                                  (0x1UL << AON_LOP_POF_VPON_VCORE1_OP1_PCSM_1_RESERVED_Pos)
+
+/* 0xC40    0x4000_0c40
+    10:0    R/W     RESERVED_18                                                 11'h0
+    11      R/W     RESERVED_17                                                 1'b1
+    12      R/W     RESERVED_16                                                 1'b1
+    13      R/W     RESERVED_15                                                 1'b1
+    14      R/W     RESERVED_14                                                 1'b1
+    15      R/W     RESERVED_13                                                 1'b0
+    16      R/W     RESERVED_12                                                 1'b0
+    17      R/W     RESERVED_11                                                 1'b0
+    18      R/W     RESERVED_10                                                 1'b0
+    19      R/W     RESERVED_9                                                  1'b0
+    20      R/W     RESERVED_8                                                  1'b0
+    21      R/W     RESERVED_7                                                  1'b0
+    22      R/W     RESERVED_6                                                  1'b0
+    23      R/W     RESERVED_5                                                  1'b0
+    24      R/W     RESERVED_4                                                  1'b0
+    25      R/W     RESERVED_3                                                  1'b0
+    26      R/W     RESERVED_2                                                  1'b0
+    30:27   R/W     RESERVED_1                                                  4'b0000
+    31      R/W     RESERVED                                                    1'b0
+ */
+typedef union _AON_LOP_POF_VPON_VCORE1_OP1_PCSM_2_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED_18: 11;
+        uint32_t RESERVED_17: 1;
+        uint32_t RESERVED_16: 1;
+        uint32_t RESERVED_15: 1;
+        uint32_t RESERVED_14: 1;
+        uint32_t RESERVED_13: 1;
+        uint32_t RESERVED_12: 1;
+        uint32_t RESERVED_11: 1;
+        uint32_t RESERVED_10: 1;
+        uint32_t RESERVED_9: 1;
+        uint32_t RESERVED_8: 1;
+        uint32_t RESERVED_7: 1;
+        uint32_t RESERVED_6: 1;
+        uint32_t RESERVED_5: 1;
+        uint32_t RESERVED_4: 1;
+        uint32_t RESERVED_3: 1;
+        uint32_t RESERVED_2: 1;
+        uint32_t RESERVED_1: 4;
+        uint32_t RESERVED: 1;
+    };
+} AON_LOP_POF_VPON_VCORE1_OP1_PCSM_2_TYPE;
+
+/*0x4000_0c40 AON_LOP_POF_VPON_VCORE1_OP1_PCSM_2*/
+#define AON_LOP_POF_VPON_VCORE1_OP1_PCSM_2_RESERVED_18_Pos                                                               0U
+#define AON_LOP_POF_VPON_VCORE1_OP1_PCSM_2_RESERVED_18_Msk                                                               (0x7FFUL << AON_LOP_POF_VPON_VCORE1_OP1_PCSM_2_RESERVED_18_Pos)
+
+#define AON_LOP_POF_VPON_VCORE1_OP1_PCSM_2_RESERVED_17_Pos                                                               11U
+#define AON_LOP_POF_VPON_VCORE1_OP1_PCSM_2_RESERVED_17_Msk                                                               (0x1UL << AON_LOP_POF_VPON_VCORE1_OP1_PCSM_2_RESERVED_17_Pos)
+
+#define AON_LOP_POF_VPON_VCORE1_OP1_PCSM_2_RESERVED_16_Pos                                                               12U
+#define AON_LOP_POF_VPON_VCORE1_OP1_PCSM_2_RESERVED_16_Msk                                                               (0x1UL << AON_LOP_POF_VPON_VCORE1_OP1_PCSM_2_RESERVED_16_Pos)
+
+#define AON_LOP_POF_VPON_VCORE1_OP1_PCSM_2_RESERVED_15_Pos                                                               13U
+#define AON_LOP_POF_VPON_VCORE1_OP1_PCSM_2_RESERVED_15_Msk                                                               (0x1UL << AON_LOP_POF_VPON_VCORE1_OP1_PCSM_2_RESERVED_15_Pos)
+
+#define AON_LOP_POF_VPON_VCORE1_OP1_PCSM_2_RESERVED_14_Pos                                                               14U
+#define AON_LOP_POF_VPON_VCORE1_OP1_PCSM_2_RESERVED_14_Msk                                                               (0x1UL << AON_LOP_POF_VPON_VCORE1_OP1_PCSM_2_RESERVED_14_Pos)
+
+#define AON_LOP_POF_VPON_VCORE1_OP1_PCSM_2_RESERVED_13_Pos                                                               15U
+#define AON_LOP_POF_VPON_VCORE1_OP1_PCSM_2_RESERVED_13_Msk                                                               (0x1UL << AON_LOP_POF_VPON_VCORE1_OP1_PCSM_2_RESERVED_13_Pos)
+
+#define AON_LOP_POF_VPON_VCORE1_OP1_PCSM_2_RESERVED_12_Pos                                                               16U
+#define AON_LOP_POF_VPON_VCORE1_OP1_PCSM_2_RESERVED_12_Msk                                                               (0x1UL << AON_LOP_POF_VPON_VCORE1_OP1_PCSM_2_RESERVED_12_Pos)
+
+#define AON_LOP_POF_VPON_VCORE1_OP1_PCSM_2_RESERVED_11_Pos                                                               17U
+#define AON_LOP_POF_VPON_VCORE1_OP1_PCSM_2_RESERVED_11_Msk                                                               (0x1UL << AON_LOP_POF_VPON_VCORE1_OP1_PCSM_2_RESERVED_11_Pos)
+
+#define AON_LOP_POF_VPON_VCORE1_OP1_PCSM_2_RESERVED_10_Pos                                                               18U
+#define AON_LOP_POF_VPON_VCORE1_OP1_PCSM_2_RESERVED_10_Msk                                                               (0x1UL << AON_LOP_POF_VPON_VCORE1_OP1_PCSM_2_RESERVED_10_Pos)
+
+#define AON_LOP_POF_VPON_VCORE1_OP1_PCSM_2_RESERVED_9_Pos                                                                19U
+#define AON_LOP_POF_VPON_VCORE1_OP1_PCSM_2_RESERVED_9_Msk                                                                (0x1UL << AON_LOP_POF_VPON_VCORE1_OP1_PCSM_2_RESERVED_9_Pos)
+
+#define AON_LOP_POF_VPON_VCORE1_OP1_PCSM_2_RESERVED_8_Pos                                                                20U
+#define AON_LOP_POF_VPON_VCORE1_OP1_PCSM_2_RESERVED_8_Msk                                                                (0x1UL << AON_LOP_POF_VPON_VCORE1_OP1_PCSM_2_RESERVED_8_Pos)
+
+#define AON_LOP_POF_VPON_VCORE1_OP1_PCSM_2_RESERVED_7_Pos                                                                21U
+#define AON_LOP_POF_VPON_VCORE1_OP1_PCSM_2_RESERVED_7_Msk                                                                (0x1UL << AON_LOP_POF_VPON_VCORE1_OP1_PCSM_2_RESERVED_7_Pos)
+
+#define AON_LOP_POF_VPON_VCORE1_OP1_PCSM_2_RESERVED_6_Pos                                                                22U
+#define AON_LOP_POF_VPON_VCORE1_OP1_PCSM_2_RESERVED_6_Msk                                                                (0x1UL << AON_LOP_POF_VPON_VCORE1_OP1_PCSM_2_RESERVED_6_Pos)
+
+#define AON_LOP_POF_VPON_VCORE1_OP1_PCSM_2_RESERVED_5_Pos                                                                23U
+#define AON_LOP_POF_VPON_VCORE1_OP1_PCSM_2_RESERVED_5_Msk                                                                (0x1UL << AON_LOP_POF_VPON_VCORE1_OP1_PCSM_2_RESERVED_5_Pos)
+
+#define AON_LOP_POF_VPON_VCORE1_OP1_PCSM_2_RESERVED_4_Pos                                                                24U
+#define AON_LOP_POF_VPON_VCORE1_OP1_PCSM_2_RESERVED_4_Msk                                                                (0x1UL << AON_LOP_POF_VPON_VCORE1_OP1_PCSM_2_RESERVED_4_Pos)
+
+#define AON_LOP_POF_VPON_VCORE1_OP1_PCSM_2_RESERVED_3_Pos                                                                25U
+#define AON_LOP_POF_VPON_VCORE1_OP1_PCSM_2_RESERVED_3_Msk                                                                (0x1UL << AON_LOP_POF_VPON_VCORE1_OP1_PCSM_2_RESERVED_3_Pos)
+
+#define AON_LOP_POF_VPON_VCORE1_OP1_PCSM_2_RESERVED_2_Pos                                                                26U
+#define AON_LOP_POF_VPON_VCORE1_OP1_PCSM_2_RESERVED_2_Msk                                                                (0x1UL << AON_LOP_POF_VPON_VCORE1_OP1_PCSM_2_RESERVED_2_Pos)
+
+#define AON_LOP_POF_VPON_VCORE1_OP1_PCSM_2_RESERVED_1_Pos                                                                27U
+#define AON_LOP_POF_VPON_VCORE1_OP1_PCSM_2_RESERVED_1_Msk                                                                (0xFUL << AON_LOP_POF_VPON_VCORE1_OP1_PCSM_2_RESERVED_1_Pos)
+
+#define AON_LOP_POF_VPON_VCORE1_OP1_PCSM_2_RESERVED_Pos                                                                  31U
+#define AON_LOP_POF_VPON_VCORE1_OP1_PCSM_2_RESERVED_Msk                                                                  (0x1UL << AON_LOP_POF_VPON_VCORE1_OP1_PCSM_2_RESERVED_Pos)
+
+/* 0xC60    0x4000_0c60
+    0       R/W     SCH_PLN_RST                                                 1'b0
+    31:1    R       SCH_PLN_RSTB_RESERVED31_1                                   1'b0
+ */
+typedef union _AON_REG_SCH_PLN_RSTB_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t SCH_PLN_RST: 1;
+        uint32_t SCH_PLN_RSTB_RESERVED31_1: 31;
+    };
+} AON_REG_SCH_PLN_RSTB_TYPE;
+
+/*0x4000_0c60 AON_REG_SCH_PLN_RSTB*/
+#define AON_REG_SCH_PLN_RSTB_SCH_PLN_RST_Pos                                                                             0U
+#define AON_REG_SCH_PLN_RSTB_SCH_PLN_RST_Msk                                                                             (0x1UL << AON_REG_SCH_PLN_RSTB_SCH_PLN_RST_Pos)
+
+#define AON_REG_SCH_PLN_RSTB_SCH_PLN_RSTB_RESERVED31_1_Pos                                                               1U
+#define AON_REG_SCH_PLN_RSTB_SCH_PLN_RSTB_RESERVED31_1_Msk                                                               (0x7FFFFFFFUL << AON_REG_SCH_PLN_RSTB_SCH_PLN_RSTB_RESERVED31_1_Pos)
+
+/* 0xC64    0x4000_0c64
+    31:0    R/W     TREE0_ROOT_ACT_TIME                                         32'b0
+ */
+typedef union _AON_REG_SCH_PLN_TREE0_ROOT_ACT_TIME_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t TREE0_ROOT_ACT_TIME;
+    };
+} AON_REG_SCH_PLN_TREE0_ROOT_ACT_TIME_TYPE;
+
+/*0x4000_0c64 AON_REG_SCH_PLN_TREE0_ROOT_ACT_TIME*/
+#define AON_REG_SCH_PLN_TREE0_ROOT_ACT_TIME_TREE0_ROOT_ACT_TIME_Pos                                                      0U
+#define AON_REG_SCH_PLN_TREE0_ROOT_ACT_TIME_TREE0_ROOT_ACT_TIME_Msk                                                      (0xFFFFFFFFUL << AON_REG_SCH_PLN_TREE0_ROOT_ACT_TIME_TREE0_ROOT_ACT_TIME_Pos)
+
+/* 0xC68    0x4000_0c68
+    31:0    R/W     TREE1_ROOT_ACT_TIME                                         32'b0
+ */
+typedef union _AON_REG_SCH_PLN_TREE1_ROOT_ACT_TIME_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t TREE1_ROOT_ACT_TIME;
+    };
+} AON_REG_SCH_PLN_TREE1_ROOT_ACT_TIME_TYPE;
+
+/*0x4000_0c68 AON_REG_SCH_PLN_TREE1_ROOT_ACT_TIME*/
+#define AON_REG_SCH_PLN_TREE1_ROOT_ACT_TIME_TREE1_ROOT_ACT_TIME_Pos                                                      0U
+#define AON_REG_SCH_PLN_TREE1_ROOT_ACT_TIME_TREE1_ROOT_ACT_TIME_Msk                                                      (0xFFFFFFFFUL << AON_REG_SCH_PLN_TREE1_ROOT_ACT_TIME_TREE1_ROOT_ACT_TIME_Pos)
+
+/* 0xC6C    0x4000_0c6c
+    0       R/WAC   TREE0_ACT_CLR                                               1'b0
+    1       R/WAC   TREE1_ACT_CLR                                               1'b0
+    31:2    R       SCH_PLN_TREE_ACTIVE_CLEAR_RESERVED31_2                      30'b0
+ */
+typedef union _AON_REG_SCH_PLN_TREE_ACT_CLEAR_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t TREE0_ACT_CLR: 1;
+        uint32_t TREE1_ACT_CLR: 1;
+        uint32_t SCH_PLN_TREE_ACTIVE_CLEAR_RESERVED31_2: 30;
+    };
+} AON_REG_SCH_PLN_TREE_ACT_CLEAR_TYPE;
+
+/*0x4000_0c6c AON_REG_SCH_PLN_TREE_ACT_CLEAR*/
+#define AON_REG_SCH_PLN_TREE_ACT_CLEAR_TREE0_ACT_CLR_Pos                                                                 0U
+#define AON_REG_SCH_PLN_TREE_ACT_CLEAR_TREE0_ACT_CLR_Msk                                                                 (0x1UL << AON_REG_SCH_PLN_TREE_ACT_CLEAR_TREE0_ACT_CLR_Pos)
+
+#define AON_REG_SCH_PLN_TREE_ACT_CLEAR_TREE1_ACT_CLR_Pos                                                                 1U
+#define AON_REG_SCH_PLN_TREE_ACT_CLEAR_TREE1_ACT_CLR_Msk                                                                 (0x1UL << AON_REG_SCH_PLN_TREE_ACT_CLEAR_TREE1_ACT_CLR_Pos)
+
+#define AON_REG_SCH_PLN_TREE_ACT_CLEAR_SCH_PLN_TREE_ACTIVE_CLEAR_RESERVED31_2_Pos                                        2U
+#define AON_REG_SCH_PLN_TREE_ACT_CLEAR_SCH_PLN_TREE_ACTIVE_CLEAR_RESERVED31_2_Msk                                        (0x3FFFFFFFUL << AON_REG_SCH_PLN_TREE_ACT_CLEAR_SCH_PLN_TREE_ACTIVE_CLEAR_RESERVED31_2_Pos)
+
+/* 0xC70    0x4000_0c70
+    0       R/W     TREE0_MANUAL_TRIGGER                                        1'b0
+    1       R/W     TREE1_MANUAL_TRIGGER                                        1'b0
+    31:2    R       SCH_PLN_MANUAL_INTR_RESERVED31_2                            30'b0
+ */
+typedef union _AON_REG_SCH_PLN_MANUAL_TRIGGER_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t TREE0_MANUAL_TRIGGER: 1;
+        uint32_t TREE1_MANUAL_TRIGGER: 1;
+        uint32_t SCH_PLN_MANUAL_INTR_RESERVED31_2: 30;
+    };
+} AON_REG_SCH_PLN_MANUAL_TRIGGER_TYPE;
+
+/*0x4000_0c70 AON_REG_SCH_PLN_MANUAL_TRIGGER*/
+#define AON_REG_SCH_PLN_MANUAL_TRIGGER_TREE0_MANUAL_TRIGGER_Pos                                                          0U
+#define AON_REG_SCH_PLN_MANUAL_TRIGGER_TREE0_MANUAL_TRIGGER_Msk                                                          (0x1UL << AON_REG_SCH_PLN_MANUAL_TRIGGER_TREE0_MANUAL_TRIGGER_Pos)
+
+#define AON_REG_SCH_PLN_MANUAL_TRIGGER_TREE1_MANUAL_TRIGGER_Pos                                                          1U
+#define AON_REG_SCH_PLN_MANUAL_TRIGGER_TREE1_MANUAL_TRIGGER_Msk                                                          (0x1UL << AON_REG_SCH_PLN_MANUAL_TRIGGER_TREE1_MANUAL_TRIGGER_Pos)
+
+#define AON_REG_SCH_PLN_MANUAL_TRIGGER_SCH_PLN_MANUAL_INTR_RESERVED31_2_Pos                                              2U
+#define AON_REG_SCH_PLN_MANUAL_TRIGGER_SCH_PLN_MANUAL_INTR_RESERVED31_2_Msk                                              (0x3FFFFFFFUL << AON_REG_SCH_PLN_MANUAL_TRIGGER_SCH_PLN_MANUAL_INTR_RESERVED31_2_Pos)
+
+/* 0xC74    0x4000_0c74
+    0       R/W     TREE0_INTR_EN                                               1'b0
+    1       R/W     TREE1_INTR_EN                                               1'b0
+    2       R/W     TREE0_INTR_TYPE                                             1'b0
+    3       R/W     TREE1_INTR_TYPE                                             1'b0
+    31:4    R       SCH_PLN_INTR_CTRL_RESERVED31_4                              28'b0
+ */
+typedef union _AON_REG_SCH_PLN_INTR_CTRL_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t TREE0_INTR_EN: 1;
+        uint32_t TREE1_INTR_EN: 1;
+        uint32_t TREE0_INTR_TYPE: 1;
+        uint32_t TREE1_INTR_TYPE: 1;
+        uint32_t SCH_PLN_INTR_CTRL_RESERVED31_4: 28;
+    };
+} AON_REG_SCH_PLN_INTR_CTRL_TYPE;
+
+/*0x4000_0c74 AON_REG_SCH_PLN_INTR_CTRL*/
+#define AON_REG_SCH_PLN_INTR_CTRL_TREE0_INTR_EN_Pos                                                                      0U
+#define AON_REG_SCH_PLN_INTR_CTRL_TREE0_INTR_EN_Msk                                                                      (0x1UL << AON_REG_SCH_PLN_INTR_CTRL_TREE0_INTR_EN_Pos)
+
+#define AON_REG_SCH_PLN_INTR_CTRL_TREE1_INTR_EN_Pos                                                                      1U
+#define AON_REG_SCH_PLN_INTR_CTRL_TREE1_INTR_EN_Msk                                                                      (0x1UL << AON_REG_SCH_PLN_INTR_CTRL_TREE1_INTR_EN_Pos)
+
+#define AON_REG_SCH_PLN_INTR_CTRL_TREE0_INTR_TYPE_Pos                                                                    2U
+#define AON_REG_SCH_PLN_INTR_CTRL_TREE0_INTR_TYPE_Msk                                                                    (0x1UL << AON_REG_SCH_PLN_INTR_CTRL_TREE0_INTR_TYPE_Pos)
+
+#define AON_REG_SCH_PLN_INTR_CTRL_TREE1_INTR_TYPE_Pos                                                                    3U
+#define AON_REG_SCH_PLN_INTR_CTRL_TREE1_INTR_TYPE_Msk                                                                    (0x1UL << AON_REG_SCH_PLN_INTR_CTRL_TREE1_INTR_TYPE_Pos)
+
+#define AON_REG_SCH_PLN_INTR_CTRL_SCH_PLN_INTR_CTRL_RESERVED31_4_Pos                                                     4U
+#define AON_REG_SCH_PLN_INTR_CTRL_SCH_PLN_INTR_CTRL_RESERVED31_4_Msk                                                     (0xFFFFFFFUL << AON_REG_SCH_PLN_INTR_CTRL_SCH_PLN_INTR_CTRL_RESERVED31_4_Pos)
+
+/* 0xC78    0x4000_0c78
+    0       R       TREE0_SCH_INTR_STS                                          1'b0
+    1       R       TREE1_SCH_INTR_STS                                          1'b0
+    31:2    R       SCH_PLN_INTR_STS_RESERVED31_2                               30'b0
+ */
+typedef union _AON_REG_SCH_PLN_INTR_STATUS_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t TREE0_SCH_INTR_STS: 1;
+        uint32_t TREE1_SCH_INTR_STS: 1;
+        uint32_t SCH_PLN_INTR_STS_RESERVED31_2: 30;
+    };
+} AON_REG_SCH_PLN_INTR_STATUS_TYPE;
+
+/*0x4000_0c78 AON_REG_SCH_PLN_INTR_STATUS*/
+#define AON_REG_SCH_PLN_INTR_STATUS_TREE0_SCH_INTR_STS_Pos                                                               0U
+#define AON_REG_SCH_PLN_INTR_STATUS_TREE0_SCH_INTR_STS_Msk                                                               (0x1UL << AON_REG_SCH_PLN_INTR_STATUS_TREE0_SCH_INTR_STS_Pos)
+
+#define AON_REG_SCH_PLN_INTR_STATUS_TREE1_SCH_INTR_STS_Pos                                                               1U
+#define AON_REG_SCH_PLN_INTR_STATUS_TREE1_SCH_INTR_STS_Msk                                                               (0x1UL << AON_REG_SCH_PLN_INTR_STATUS_TREE1_SCH_INTR_STS_Pos)
+
+#define AON_REG_SCH_PLN_INTR_STATUS_SCH_PLN_INTR_STS_RESERVED31_2_Pos                                                    2U
+#define AON_REG_SCH_PLN_INTR_STATUS_SCH_PLN_INTR_STS_RESERVED31_2_Msk                                                    (0x3FFFFFFFUL << AON_REG_SCH_PLN_INTR_STATUS_SCH_PLN_INTR_STS_RESERVED31_2_Pos)
+
+/* 0xC7C    0x4000_0c7c
+    0       R/WAC   TREE0_SCH_INTR_CLR                                          1'b0
+    1       R/WAC   TREE1_SCH_INTR_CLR                                          1'b0
+    31:2    R       SCH_PLN_INTR_CLR_RESERVED31_2                               30'b0
+ */
+typedef union _AON_REG_SCH_PLN_INTR_CLEAR_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t TREE0_SCH_INTR_CLR: 1;
+        uint32_t TREE1_SCH_INTR_CLR: 1;
+        uint32_t SCH_PLN_INTR_CLR_RESERVED31_2: 30;
+    };
+} AON_REG_SCH_PLN_INTR_CLEAR_TYPE;
+
+/*0x4000_0c7c AON_REG_SCH_PLN_INTR_CLEAR*/
+#define AON_REG_SCH_PLN_INTR_CLEAR_TREE0_SCH_INTR_CLR_Pos                                                                0U
+#define AON_REG_SCH_PLN_INTR_CLEAR_TREE0_SCH_INTR_CLR_Msk                                                                (0x1UL << AON_REG_SCH_PLN_INTR_CLEAR_TREE0_SCH_INTR_CLR_Pos)
+
+#define AON_REG_SCH_PLN_INTR_CLEAR_TREE1_SCH_INTR_CLR_Pos                                                                1U
+#define AON_REG_SCH_PLN_INTR_CLEAR_TREE1_SCH_INTR_CLR_Msk                                                                (0x1UL << AON_REG_SCH_PLN_INTR_CLEAR_TREE1_SCH_INTR_CLR_Pos)
+
+#define AON_REG_SCH_PLN_INTR_CLEAR_SCH_PLN_INTR_CLR_RESERVED31_2_Pos                                                     2U
+#define AON_REG_SCH_PLN_INTR_CLEAR_SCH_PLN_INTR_CLR_RESERVED31_2_Msk                                                     (0x3FFFFFFFUL << AON_REG_SCH_PLN_INTR_CLEAR_SCH_PLN_INTR_CLR_RESERVED31_2_Pos)
+
+/* 0xC80    0x4000_0c80
+    0       R/W     NODE_0_1_DISABLE                                            1'b0
+    1       R/W     NODE_0_2_DISABLE                                            1'b0
+    2       R/W     NODE_0_3_DISABLE                                            1'b0
+    3       R/W     NODE_0_4_DISABLE                                            1'b0
+    4       R/W     NODE_0_5_DISABLE                                            1'b0
+    5       R/W     NODE_0_6_DISABLE                                            1'b0
+    6       R/W     NODE_0_7_DISABLE                                            1'b0
+    7       R/W     NODE_0_8_DISABLE                                            1'b0
+    8       R/W     NODE_0_9_DISABLE                                            1'b0
+    9       R/W     NODE_0_10_DISABLE                                           1'b0
+    15:10   R       SCH_PLN_NODE_DISABLE_RESERVED15_10                          6'b0
+    16      R/W     NODE_1_1_DISABLE                                            1'b0
+    17      R/W     NODE_1_2_DISABLE                                            1'b0
+    18      R/W     NODE_1_3_DISABLE                                            1'b0
+    19      R/W     NODE_1_4_DISABLE                                            1'b0
+    20      R/W     NODE_1_5_DISABLE                                            1'b0
+    21      R/W     NODE_1_6_DISABLE                                            1'b0
+    22      R/W     NODE_1_7_DISABLE                                            1'b0
+    23      R/W     NODE_1_8_DISABLE                                            1'b0
+    24      R/W     NODE_1_9_DISABLE                                            1'b0
+    25      R/W     NODE_1_10_DISABLE                                           1'b0
+    26      R/W     NODE_1_11_DISABLE                                           1'b0
+    27      R/W     NODE_1_12_DISABLE                                           1'b0
+    28      R/W     NODE_1_13_DISABLE                                           1'b0
+    29      R/W     NODE_1_14_DISABLE                                           1'b0
+    31:30   R       SCH_PLN_NODE_DISABLE_RESERVED31_30                          2'b0
+ */
+typedef union _AON_REG_SCH_PLN_NODE_DISABLE_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t NODE_0_1_DISABLE: 1;
+        uint32_t NODE_0_2_DISABLE: 1;
+        uint32_t NODE_0_3_DISABLE: 1;
+        uint32_t NODE_0_4_DISABLE: 1;
+        uint32_t NODE_0_5_DISABLE: 1;
+        uint32_t NODE_0_6_DISABLE: 1;
+        uint32_t NODE_0_7_DISABLE: 1;
+        uint32_t NODE_0_8_DISABLE: 1;
+        uint32_t NODE_0_9_DISABLE: 1;
+        uint32_t NODE_0_10_DISABLE: 1;
+        uint32_t SCH_PLN_NODE_DISABLE_RESERVED15_10: 6;
+        uint32_t NODE_1_1_DISABLE: 1;
+        uint32_t NODE_1_2_DISABLE: 1;
+        uint32_t NODE_1_3_DISABLE: 1;
+        uint32_t NODE_1_4_DISABLE: 1;
+        uint32_t NODE_1_5_DISABLE: 1;
+        uint32_t NODE_1_6_DISABLE: 1;
+        uint32_t NODE_1_7_DISABLE: 1;
+        uint32_t NODE_1_8_DISABLE: 1;
+        uint32_t NODE_1_9_DISABLE: 1;
+        uint32_t NODE_1_10_DISABLE: 1;
+        uint32_t NODE_1_11_DISABLE: 1;
+        uint32_t NODE_1_12_DISABLE: 1;
+        uint32_t NODE_1_13_DISABLE: 1;
+        uint32_t NODE_1_14_DISABLE: 1;
+        uint32_t SCH_PLN_NODE_DISABLE_RESERVED31_30: 2;
+    };
+} AON_REG_SCH_PLN_NODE_DISABLE_TYPE;
+
+/*0x4000_0c80 AON_REG_SCH_PLN_NODE_DISABLE*/
+#define AON_REG_SCH_PLN_NODE_DISABLE_NODE_0_1_DISABLE_Pos                                                                0U
+#define AON_REG_SCH_PLN_NODE_DISABLE_NODE_0_1_DISABLE_Msk                                                                (0x1UL << AON_REG_SCH_PLN_NODE_DISABLE_NODE_0_1_DISABLE_Pos)
+
+#define AON_REG_SCH_PLN_NODE_DISABLE_NODE_0_2_DISABLE_Pos                                                                1U
+#define AON_REG_SCH_PLN_NODE_DISABLE_NODE_0_2_DISABLE_Msk                                                                (0x1UL << AON_REG_SCH_PLN_NODE_DISABLE_NODE_0_2_DISABLE_Pos)
+
+#define AON_REG_SCH_PLN_NODE_DISABLE_NODE_0_3_DISABLE_Pos                                                                2U
+#define AON_REG_SCH_PLN_NODE_DISABLE_NODE_0_3_DISABLE_Msk                                                                (0x1UL << AON_REG_SCH_PLN_NODE_DISABLE_NODE_0_3_DISABLE_Pos)
+
+#define AON_REG_SCH_PLN_NODE_DISABLE_NODE_0_4_DISABLE_Pos                                                                3U
+#define AON_REG_SCH_PLN_NODE_DISABLE_NODE_0_4_DISABLE_Msk                                                                (0x1UL << AON_REG_SCH_PLN_NODE_DISABLE_NODE_0_4_DISABLE_Pos)
+
+#define AON_REG_SCH_PLN_NODE_DISABLE_NODE_0_5_DISABLE_Pos                                                                4U
+#define AON_REG_SCH_PLN_NODE_DISABLE_NODE_0_5_DISABLE_Msk                                                                (0x1UL << AON_REG_SCH_PLN_NODE_DISABLE_NODE_0_5_DISABLE_Pos)
+
+#define AON_REG_SCH_PLN_NODE_DISABLE_NODE_0_6_DISABLE_Pos                                                                5U
+#define AON_REG_SCH_PLN_NODE_DISABLE_NODE_0_6_DISABLE_Msk                                                                (0x1UL << AON_REG_SCH_PLN_NODE_DISABLE_NODE_0_6_DISABLE_Pos)
+
+#define AON_REG_SCH_PLN_NODE_DISABLE_NODE_0_7_DISABLE_Pos                                                                6U
+#define AON_REG_SCH_PLN_NODE_DISABLE_NODE_0_7_DISABLE_Msk                                                                (0x1UL << AON_REG_SCH_PLN_NODE_DISABLE_NODE_0_7_DISABLE_Pos)
+
+#define AON_REG_SCH_PLN_NODE_DISABLE_NODE_0_8_DISABLE_Pos                                                                7U
+#define AON_REG_SCH_PLN_NODE_DISABLE_NODE_0_8_DISABLE_Msk                                                                (0x1UL << AON_REG_SCH_PLN_NODE_DISABLE_NODE_0_8_DISABLE_Pos)
+
+#define AON_REG_SCH_PLN_NODE_DISABLE_NODE_0_9_DISABLE_Pos                                                                8U
+#define AON_REG_SCH_PLN_NODE_DISABLE_NODE_0_9_DISABLE_Msk                                                                (0x1UL << AON_REG_SCH_PLN_NODE_DISABLE_NODE_0_9_DISABLE_Pos)
+
+#define AON_REG_SCH_PLN_NODE_DISABLE_NODE_0_10_DISABLE_Pos                                                               9U
+#define AON_REG_SCH_PLN_NODE_DISABLE_NODE_0_10_DISABLE_Msk                                                               (0x1UL << AON_REG_SCH_PLN_NODE_DISABLE_NODE_0_10_DISABLE_Pos)
+
+#define AON_REG_SCH_PLN_NODE_DISABLE_SCH_PLN_NODE_DISABLE_RESERVED15_10_Pos                                              10U
+#define AON_REG_SCH_PLN_NODE_DISABLE_SCH_PLN_NODE_DISABLE_RESERVED15_10_Msk                                              (0x3FUL << AON_REG_SCH_PLN_NODE_DISABLE_SCH_PLN_NODE_DISABLE_RESERVED15_10_Pos)
+
+#define AON_REG_SCH_PLN_NODE_DISABLE_NODE_1_1_DISABLE_Pos                                                                16U
+#define AON_REG_SCH_PLN_NODE_DISABLE_NODE_1_1_DISABLE_Msk                                                                (0x1UL << AON_REG_SCH_PLN_NODE_DISABLE_NODE_1_1_DISABLE_Pos)
+
+#define AON_REG_SCH_PLN_NODE_DISABLE_NODE_1_2_DISABLE_Pos                                                                17U
+#define AON_REG_SCH_PLN_NODE_DISABLE_NODE_1_2_DISABLE_Msk                                                                (0x1UL << AON_REG_SCH_PLN_NODE_DISABLE_NODE_1_2_DISABLE_Pos)
+
+#define AON_REG_SCH_PLN_NODE_DISABLE_NODE_1_3_DISABLE_Pos                                                                18U
+#define AON_REG_SCH_PLN_NODE_DISABLE_NODE_1_3_DISABLE_Msk                                                                (0x1UL << AON_REG_SCH_PLN_NODE_DISABLE_NODE_1_3_DISABLE_Pos)
+
+#define AON_REG_SCH_PLN_NODE_DISABLE_NODE_1_4_DISABLE_Pos                                                                19U
+#define AON_REG_SCH_PLN_NODE_DISABLE_NODE_1_4_DISABLE_Msk                                                                (0x1UL << AON_REG_SCH_PLN_NODE_DISABLE_NODE_1_4_DISABLE_Pos)
+
+#define AON_REG_SCH_PLN_NODE_DISABLE_NODE_1_5_DISABLE_Pos                                                                20U
+#define AON_REG_SCH_PLN_NODE_DISABLE_NODE_1_5_DISABLE_Msk                                                                (0x1UL << AON_REG_SCH_PLN_NODE_DISABLE_NODE_1_5_DISABLE_Pos)
+
+#define AON_REG_SCH_PLN_NODE_DISABLE_NODE_1_6_DISABLE_Pos                                                                21U
+#define AON_REG_SCH_PLN_NODE_DISABLE_NODE_1_6_DISABLE_Msk                                                                (0x1UL << AON_REG_SCH_PLN_NODE_DISABLE_NODE_1_6_DISABLE_Pos)
+
+#define AON_REG_SCH_PLN_NODE_DISABLE_NODE_1_7_DISABLE_Pos                                                                22U
+#define AON_REG_SCH_PLN_NODE_DISABLE_NODE_1_7_DISABLE_Msk                                                                (0x1UL << AON_REG_SCH_PLN_NODE_DISABLE_NODE_1_7_DISABLE_Pos)
+
+#define AON_REG_SCH_PLN_NODE_DISABLE_NODE_1_8_DISABLE_Pos                                                                23U
+#define AON_REG_SCH_PLN_NODE_DISABLE_NODE_1_8_DISABLE_Msk                                                                (0x1UL << AON_REG_SCH_PLN_NODE_DISABLE_NODE_1_8_DISABLE_Pos)
+
+#define AON_REG_SCH_PLN_NODE_DISABLE_NODE_1_9_DISABLE_Pos                                                                24U
+#define AON_REG_SCH_PLN_NODE_DISABLE_NODE_1_9_DISABLE_Msk                                                                (0x1UL << AON_REG_SCH_PLN_NODE_DISABLE_NODE_1_9_DISABLE_Pos)
+
+#define AON_REG_SCH_PLN_NODE_DISABLE_NODE_1_10_DISABLE_Pos                                                               25U
+#define AON_REG_SCH_PLN_NODE_DISABLE_NODE_1_10_DISABLE_Msk                                                               (0x1UL << AON_REG_SCH_PLN_NODE_DISABLE_NODE_1_10_DISABLE_Pos)
+
+#define AON_REG_SCH_PLN_NODE_DISABLE_NODE_1_11_DISABLE_Pos                                                               26U
+#define AON_REG_SCH_PLN_NODE_DISABLE_NODE_1_11_DISABLE_Msk                                                               (0x1UL << AON_REG_SCH_PLN_NODE_DISABLE_NODE_1_11_DISABLE_Pos)
+
+#define AON_REG_SCH_PLN_NODE_DISABLE_NODE_1_12_DISABLE_Pos                                                               27U
+#define AON_REG_SCH_PLN_NODE_DISABLE_NODE_1_12_DISABLE_Msk                                                               (0x1UL << AON_REG_SCH_PLN_NODE_DISABLE_NODE_1_12_DISABLE_Pos)
+
+#define AON_REG_SCH_PLN_NODE_DISABLE_NODE_1_13_DISABLE_Pos                                                               28U
+#define AON_REG_SCH_PLN_NODE_DISABLE_NODE_1_13_DISABLE_Msk                                                               (0x1UL << AON_REG_SCH_PLN_NODE_DISABLE_NODE_1_13_DISABLE_Pos)
+
+#define AON_REG_SCH_PLN_NODE_DISABLE_NODE_1_14_DISABLE_Pos                                                               29U
+#define AON_REG_SCH_PLN_NODE_DISABLE_NODE_1_14_DISABLE_Msk                                                               (0x1UL << AON_REG_SCH_PLN_NODE_DISABLE_NODE_1_14_DISABLE_Pos)
+
+#define AON_REG_SCH_PLN_NODE_DISABLE_SCH_PLN_NODE_DISABLE_RESERVED31_30_Pos                                              30U
+#define AON_REG_SCH_PLN_NODE_DISABLE_SCH_PLN_NODE_DISABLE_RESERVED31_30_Msk                                              (0x3UL << AON_REG_SCH_PLN_NODE_DISABLE_SCH_PLN_NODE_DISABLE_RESERVED31_30_Pos)
+
+/* 0xC84    0x4000_0c84
+    0       R/W     NODE_0_1_DISABLE_AUTO_BYPASS                                1'b0
+    1       R/W     NODE_0_2_DISABLE_AUTO_BYPASS                                1'b0
+    2       R/W     NODE_0_3_DISABLE_AUTO_BYPASS                                1'b0
+    3       R/W     NODE_0_4_DISABLE_AUTO_BYPASS                                1'b0
+    4       R/W     NODE_0_5_DISABLE_AUTO_BYPASS                                1'b0
+    5       R/W     NODE_0_6_DISABLE_AUTO_BYPASS                                1'b0
+    6       R/W     NODE_0_7_DISABLE_AUTO_BYPASS                                1'b0
+    7       R/W     NODE_0_8_DISABLE_AUTO_BYPASS                                1'b0
+    8       R/W     NODE_0_9_DISABLE_AUTO_BYPASS                                1'b0
+    9       R/W     NODE_0_10_DISABLE_AUTO_BYPASS                               1'b0
+    15:10   R       SCH_PLN_NODE_DISABLE_AUTO_BYPASS_RESERVED15_10              6'b0
+    16      R/W     NODE_1_1_DISABLE_AUTO_BYPASS                                1'b0
+    17      R/W     NODE_1_2_DISABLE_AUTO_BYPASS                                1'b0
+    18      R/W     NODE_1_3_DISABLE_AUTO_BYPASS                                1'b0
+    19      R/W     NODE_1_4_DISABLE_AUTO_BYPASS                                1'b0
+    20      R/W     NODE_1_5_DISABLE_AUTO_BYPASS                                1'b0
+    21      R/W     NODE_1_6_DISABLE_AUTO_BYPASS                                1'b0
+    22      R/W     NODE_1_7_DISABLE_AUTO_BYPASS                                1'b0
+    23      R/W     NODE_1_8_DISABLE_AUTO_BYPASS                                1'b0
+    24      R/W     NODE_1_9_DISABLE_AUTO_BYPASS                                1'b0
+    25      R/W     NODE_1_10_DISABLE_AUTO_BYPASS                               1'b0
+    26      R/W     NODE_1_11_DISABLE_AUTO_BYPASS                               1'b0
+    27      R/W     NODE_1_12_DISABLE_AUTO_BYPASS                               1'b0
+    28      R/W     NODE_1_13_DISABLE_AUTO_BYPASS                               1'b0
+    29      R/W     NODE_1_14_DISABLE_AUTO_BYPASS                               1'b0
+    31:30   R       SCH_PLN_NODE_DISABLE_AUTO_BYPASS_RESERVED31_30              2'b0
+ */
+typedef union _AON_REG_SCH_PLN_NODE_DISABLE_AUTO_BYPASS_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t NODE_0_1_DISABLE_AUTO_BYPASS: 1;
+        uint32_t NODE_0_2_DISABLE_AUTO_BYPASS: 1;
+        uint32_t NODE_0_3_DISABLE_AUTO_BYPASS: 1;
+        uint32_t NODE_0_4_DISABLE_AUTO_BYPASS: 1;
+        uint32_t NODE_0_5_DISABLE_AUTO_BYPASS: 1;
+        uint32_t NODE_0_6_DISABLE_AUTO_BYPASS: 1;
+        uint32_t NODE_0_7_DISABLE_AUTO_BYPASS: 1;
+        uint32_t NODE_0_8_DISABLE_AUTO_BYPASS: 1;
+        uint32_t NODE_0_9_DISABLE_AUTO_BYPASS: 1;
+        uint32_t NODE_0_10_DISABLE_AUTO_BYPASS: 1;
+        uint32_t SCH_PLN_NODE_DISABLE_AUTO_BYPASS_RESERVED15_10: 6;
+        uint32_t NODE_1_1_DISABLE_AUTO_BYPASS: 1;
+        uint32_t NODE_1_2_DISABLE_AUTO_BYPASS: 1;
+        uint32_t NODE_1_3_DISABLE_AUTO_BYPASS: 1;
+        uint32_t NODE_1_4_DISABLE_AUTO_BYPASS: 1;
+        uint32_t NODE_1_5_DISABLE_AUTO_BYPASS: 1;
+        uint32_t NODE_1_6_DISABLE_AUTO_BYPASS: 1;
+        uint32_t NODE_1_7_DISABLE_AUTO_BYPASS: 1;
+        uint32_t NODE_1_8_DISABLE_AUTO_BYPASS: 1;
+        uint32_t NODE_1_9_DISABLE_AUTO_BYPASS: 1;
+        uint32_t NODE_1_10_DISABLE_AUTO_BYPASS: 1;
+        uint32_t NODE_1_11_DISABLE_AUTO_BYPASS: 1;
+        uint32_t NODE_1_12_DISABLE_AUTO_BYPASS: 1;
+        uint32_t NODE_1_13_DISABLE_AUTO_BYPASS: 1;
+        uint32_t NODE_1_14_DISABLE_AUTO_BYPASS: 1;
+        uint32_t SCH_PLN_NODE_DISABLE_AUTO_BYPASS_RESERVED31_30: 2;
+    };
+} AON_REG_SCH_PLN_NODE_DISABLE_AUTO_BYPASS_TYPE;
+
+/*0x4000_0c84 AON_REG_SCH_PLN_NODE_DISABLE_AUTO_BYPASS*/
+#define AON_REG_SCH_PLN_NODE_DISABLE_AUTO_BYPASS_NODE_0_1_DISABLE_AUTO_BYPASS_Pos                                        0U
+#define AON_REG_SCH_PLN_NODE_DISABLE_AUTO_BYPASS_NODE_0_1_DISABLE_AUTO_BYPASS_Msk                                        (0x1UL << AON_REG_SCH_PLN_NODE_DISABLE_AUTO_BYPASS_NODE_0_1_DISABLE_AUTO_BYPASS_Pos)
+
+#define AON_REG_SCH_PLN_NODE_DISABLE_AUTO_BYPASS_NODE_0_2_DISABLE_AUTO_BYPASS_Pos                                        1U
+#define AON_REG_SCH_PLN_NODE_DISABLE_AUTO_BYPASS_NODE_0_2_DISABLE_AUTO_BYPASS_Msk                                        (0x1UL << AON_REG_SCH_PLN_NODE_DISABLE_AUTO_BYPASS_NODE_0_2_DISABLE_AUTO_BYPASS_Pos)
+
+#define AON_REG_SCH_PLN_NODE_DISABLE_AUTO_BYPASS_NODE_0_3_DISABLE_AUTO_BYPASS_Pos                                        2U
+#define AON_REG_SCH_PLN_NODE_DISABLE_AUTO_BYPASS_NODE_0_3_DISABLE_AUTO_BYPASS_Msk                                        (0x1UL << AON_REG_SCH_PLN_NODE_DISABLE_AUTO_BYPASS_NODE_0_3_DISABLE_AUTO_BYPASS_Pos)
+
+#define AON_REG_SCH_PLN_NODE_DISABLE_AUTO_BYPASS_NODE_0_4_DISABLE_AUTO_BYPASS_Pos                                        3U
+#define AON_REG_SCH_PLN_NODE_DISABLE_AUTO_BYPASS_NODE_0_4_DISABLE_AUTO_BYPASS_Msk                                        (0x1UL << AON_REG_SCH_PLN_NODE_DISABLE_AUTO_BYPASS_NODE_0_4_DISABLE_AUTO_BYPASS_Pos)
+
+#define AON_REG_SCH_PLN_NODE_DISABLE_AUTO_BYPASS_NODE_0_5_DISABLE_AUTO_BYPASS_Pos                                        4U
+#define AON_REG_SCH_PLN_NODE_DISABLE_AUTO_BYPASS_NODE_0_5_DISABLE_AUTO_BYPASS_Msk                                        (0x1UL << AON_REG_SCH_PLN_NODE_DISABLE_AUTO_BYPASS_NODE_0_5_DISABLE_AUTO_BYPASS_Pos)
+
+#define AON_REG_SCH_PLN_NODE_DISABLE_AUTO_BYPASS_NODE_0_6_DISABLE_AUTO_BYPASS_Pos                                        5U
+#define AON_REG_SCH_PLN_NODE_DISABLE_AUTO_BYPASS_NODE_0_6_DISABLE_AUTO_BYPASS_Msk                                        (0x1UL << AON_REG_SCH_PLN_NODE_DISABLE_AUTO_BYPASS_NODE_0_6_DISABLE_AUTO_BYPASS_Pos)
+
+#define AON_REG_SCH_PLN_NODE_DISABLE_AUTO_BYPASS_NODE_0_7_DISABLE_AUTO_BYPASS_Pos                                        6U
+#define AON_REG_SCH_PLN_NODE_DISABLE_AUTO_BYPASS_NODE_0_7_DISABLE_AUTO_BYPASS_Msk                                        (0x1UL << AON_REG_SCH_PLN_NODE_DISABLE_AUTO_BYPASS_NODE_0_7_DISABLE_AUTO_BYPASS_Pos)
+
+#define AON_REG_SCH_PLN_NODE_DISABLE_AUTO_BYPASS_NODE_0_8_DISABLE_AUTO_BYPASS_Pos                                        7U
+#define AON_REG_SCH_PLN_NODE_DISABLE_AUTO_BYPASS_NODE_0_8_DISABLE_AUTO_BYPASS_Msk                                        (0x1UL << AON_REG_SCH_PLN_NODE_DISABLE_AUTO_BYPASS_NODE_0_8_DISABLE_AUTO_BYPASS_Pos)
+
+#define AON_REG_SCH_PLN_NODE_DISABLE_AUTO_BYPASS_NODE_0_9_DISABLE_AUTO_BYPASS_Pos                                        8U
+#define AON_REG_SCH_PLN_NODE_DISABLE_AUTO_BYPASS_NODE_0_9_DISABLE_AUTO_BYPASS_Msk                                        (0x1UL << AON_REG_SCH_PLN_NODE_DISABLE_AUTO_BYPASS_NODE_0_9_DISABLE_AUTO_BYPASS_Pos)
+
+#define AON_REG_SCH_PLN_NODE_DISABLE_AUTO_BYPASS_NODE_0_10_DISABLE_AUTO_BYPASS_Pos                                       9U
+#define AON_REG_SCH_PLN_NODE_DISABLE_AUTO_BYPASS_NODE_0_10_DISABLE_AUTO_BYPASS_Msk                                       (0x1UL << AON_REG_SCH_PLN_NODE_DISABLE_AUTO_BYPASS_NODE_0_10_DISABLE_AUTO_BYPASS_Pos)
+
+#define AON_REG_SCH_PLN_NODE_DISABLE_AUTO_BYPASS_SCH_PLN_NODE_DISABLE_AUTO_BYPASS_RESERVED15_10_Pos                      10U
+#define AON_REG_SCH_PLN_NODE_DISABLE_AUTO_BYPASS_SCH_PLN_NODE_DISABLE_AUTO_BYPASS_RESERVED15_10_Msk                      (0x3FUL << AON_REG_SCH_PLN_NODE_DISABLE_AUTO_BYPASS_SCH_PLN_NODE_DISABLE_AUTO_BYPASS_RESERVED15_10_Pos)
+
+#define AON_REG_SCH_PLN_NODE_DISABLE_AUTO_BYPASS_NODE_1_1_DISABLE_AUTO_BYPASS_Pos                                        16U
+#define AON_REG_SCH_PLN_NODE_DISABLE_AUTO_BYPASS_NODE_1_1_DISABLE_AUTO_BYPASS_Msk                                        (0x1UL << AON_REG_SCH_PLN_NODE_DISABLE_AUTO_BYPASS_NODE_1_1_DISABLE_AUTO_BYPASS_Pos)
+
+#define AON_REG_SCH_PLN_NODE_DISABLE_AUTO_BYPASS_NODE_1_2_DISABLE_AUTO_BYPASS_Pos                                        17U
+#define AON_REG_SCH_PLN_NODE_DISABLE_AUTO_BYPASS_NODE_1_2_DISABLE_AUTO_BYPASS_Msk                                        (0x1UL << AON_REG_SCH_PLN_NODE_DISABLE_AUTO_BYPASS_NODE_1_2_DISABLE_AUTO_BYPASS_Pos)
+
+#define AON_REG_SCH_PLN_NODE_DISABLE_AUTO_BYPASS_NODE_1_3_DISABLE_AUTO_BYPASS_Pos                                        18U
+#define AON_REG_SCH_PLN_NODE_DISABLE_AUTO_BYPASS_NODE_1_3_DISABLE_AUTO_BYPASS_Msk                                        (0x1UL << AON_REG_SCH_PLN_NODE_DISABLE_AUTO_BYPASS_NODE_1_3_DISABLE_AUTO_BYPASS_Pos)
+
+#define AON_REG_SCH_PLN_NODE_DISABLE_AUTO_BYPASS_NODE_1_4_DISABLE_AUTO_BYPASS_Pos                                        19U
+#define AON_REG_SCH_PLN_NODE_DISABLE_AUTO_BYPASS_NODE_1_4_DISABLE_AUTO_BYPASS_Msk                                        (0x1UL << AON_REG_SCH_PLN_NODE_DISABLE_AUTO_BYPASS_NODE_1_4_DISABLE_AUTO_BYPASS_Pos)
+
+#define AON_REG_SCH_PLN_NODE_DISABLE_AUTO_BYPASS_NODE_1_5_DISABLE_AUTO_BYPASS_Pos                                        20U
+#define AON_REG_SCH_PLN_NODE_DISABLE_AUTO_BYPASS_NODE_1_5_DISABLE_AUTO_BYPASS_Msk                                        (0x1UL << AON_REG_SCH_PLN_NODE_DISABLE_AUTO_BYPASS_NODE_1_5_DISABLE_AUTO_BYPASS_Pos)
+
+#define AON_REG_SCH_PLN_NODE_DISABLE_AUTO_BYPASS_NODE_1_6_DISABLE_AUTO_BYPASS_Pos                                        21U
+#define AON_REG_SCH_PLN_NODE_DISABLE_AUTO_BYPASS_NODE_1_6_DISABLE_AUTO_BYPASS_Msk                                        (0x1UL << AON_REG_SCH_PLN_NODE_DISABLE_AUTO_BYPASS_NODE_1_6_DISABLE_AUTO_BYPASS_Pos)
+
+#define AON_REG_SCH_PLN_NODE_DISABLE_AUTO_BYPASS_NODE_1_7_DISABLE_AUTO_BYPASS_Pos                                        22U
+#define AON_REG_SCH_PLN_NODE_DISABLE_AUTO_BYPASS_NODE_1_7_DISABLE_AUTO_BYPASS_Msk                                        (0x1UL << AON_REG_SCH_PLN_NODE_DISABLE_AUTO_BYPASS_NODE_1_7_DISABLE_AUTO_BYPASS_Pos)
+
+#define AON_REG_SCH_PLN_NODE_DISABLE_AUTO_BYPASS_NODE_1_8_DISABLE_AUTO_BYPASS_Pos                                        23U
+#define AON_REG_SCH_PLN_NODE_DISABLE_AUTO_BYPASS_NODE_1_8_DISABLE_AUTO_BYPASS_Msk                                        (0x1UL << AON_REG_SCH_PLN_NODE_DISABLE_AUTO_BYPASS_NODE_1_8_DISABLE_AUTO_BYPASS_Pos)
+
+#define AON_REG_SCH_PLN_NODE_DISABLE_AUTO_BYPASS_NODE_1_9_DISABLE_AUTO_BYPASS_Pos                                        24U
+#define AON_REG_SCH_PLN_NODE_DISABLE_AUTO_BYPASS_NODE_1_9_DISABLE_AUTO_BYPASS_Msk                                        (0x1UL << AON_REG_SCH_PLN_NODE_DISABLE_AUTO_BYPASS_NODE_1_9_DISABLE_AUTO_BYPASS_Pos)
+
+#define AON_REG_SCH_PLN_NODE_DISABLE_AUTO_BYPASS_NODE_1_10_DISABLE_AUTO_BYPASS_Pos                                       25U
+#define AON_REG_SCH_PLN_NODE_DISABLE_AUTO_BYPASS_NODE_1_10_DISABLE_AUTO_BYPASS_Msk                                       (0x1UL << AON_REG_SCH_PLN_NODE_DISABLE_AUTO_BYPASS_NODE_1_10_DISABLE_AUTO_BYPASS_Pos)
+
+#define AON_REG_SCH_PLN_NODE_DISABLE_AUTO_BYPASS_NODE_1_11_DISABLE_AUTO_BYPASS_Pos                                       26U
+#define AON_REG_SCH_PLN_NODE_DISABLE_AUTO_BYPASS_NODE_1_11_DISABLE_AUTO_BYPASS_Msk                                       (0x1UL << AON_REG_SCH_PLN_NODE_DISABLE_AUTO_BYPASS_NODE_1_11_DISABLE_AUTO_BYPASS_Pos)
+
+#define AON_REG_SCH_PLN_NODE_DISABLE_AUTO_BYPASS_NODE_1_12_DISABLE_AUTO_BYPASS_Pos                                       27U
+#define AON_REG_SCH_PLN_NODE_DISABLE_AUTO_BYPASS_NODE_1_12_DISABLE_AUTO_BYPASS_Msk                                       (0x1UL << AON_REG_SCH_PLN_NODE_DISABLE_AUTO_BYPASS_NODE_1_12_DISABLE_AUTO_BYPASS_Pos)
+
+#define AON_REG_SCH_PLN_NODE_DISABLE_AUTO_BYPASS_NODE_1_13_DISABLE_AUTO_BYPASS_Pos                                       28U
+#define AON_REG_SCH_PLN_NODE_DISABLE_AUTO_BYPASS_NODE_1_13_DISABLE_AUTO_BYPASS_Msk                                       (0x1UL << AON_REG_SCH_PLN_NODE_DISABLE_AUTO_BYPASS_NODE_1_13_DISABLE_AUTO_BYPASS_Pos)
+
+#define AON_REG_SCH_PLN_NODE_DISABLE_AUTO_BYPASS_NODE_1_14_DISABLE_AUTO_BYPASS_Pos                                       29U
+#define AON_REG_SCH_PLN_NODE_DISABLE_AUTO_BYPASS_NODE_1_14_DISABLE_AUTO_BYPASS_Msk                                       (0x1UL << AON_REG_SCH_PLN_NODE_DISABLE_AUTO_BYPASS_NODE_1_14_DISABLE_AUTO_BYPASS_Pos)
+
+#define AON_REG_SCH_PLN_NODE_DISABLE_AUTO_BYPASS_SCH_PLN_NODE_DISABLE_AUTO_BYPASS_RESERVED31_30_Pos                      30U
+#define AON_REG_SCH_PLN_NODE_DISABLE_AUTO_BYPASS_SCH_PLN_NODE_DISABLE_AUTO_BYPASS_RESERVED31_30_Msk                      (0x3UL << AON_REG_SCH_PLN_NODE_DISABLE_AUTO_BYPASS_SCH_PLN_NODE_DISABLE_AUTO_BYPASS_RESERVED31_30_Pos)
+
+/* 0xC88    0x4000_0c88
+    31:0    R/W     CMPNT0_DELAY_PON                                            32'b0
+ */
+typedef union _AON_REG_SCH_PLN_CMPNT0_DELAY_PON_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t CMPNT0_DELAY_PON;
+    };
+} AON_REG_SCH_PLN_CMPNT0_DELAY_PON_TYPE;
+
+/*0x4000_0c88 AON_REG_SCH_PLN_CMPNT0_DELAY_PON*/
+#define AON_REG_SCH_PLN_CMPNT0_DELAY_PON_CMPNT0_DELAY_PON_Pos                                                            0U
+#define AON_REG_SCH_PLN_CMPNT0_DELAY_PON_CMPNT0_DELAY_PON_Msk                                                            (0xFFFFFFFFUL << AON_REG_SCH_PLN_CMPNT0_DELAY_PON_CMPNT0_DELAY_PON_Pos)
+
+/* 0xC8C    0x4000_0c8c
+    31:0    R/W     CMPNT0_DELAY_POF                                            32'b0
+ */
+typedef union _AON_REG_SCH_PLN_CMPNT0_DELAY_POF_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t CMPNT0_DELAY_POF;
+    };
+} AON_REG_SCH_PLN_CMPNT0_DELAY_POF_TYPE;
+
+/*0x4000_0c8c AON_REG_SCH_PLN_CMPNT0_DELAY_POF*/
+#define AON_REG_SCH_PLN_CMPNT0_DELAY_POF_CMPNT0_DELAY_POF_Pos                                                            0U
+#define AON_REG_SCH_PLN_CMPNT0_DELAY_POF_CMPNT0_DELAY_POF_Msk                                                            (0xFFFFFFFFUL << AON_REG_SCH_PLN_CMPNT0_DELAY_POF_CMPNT0_DELAY_POF_Pos)
+
+/* 0xC90    0x4000_0c90
+    31:0    R/W     CMPNT1_DELAY_PON                                            32'b0
+ */
+typedef union _AON_REG_SCH_PLN_CMPNT1_DELAY_PON_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t CMPNT1_DELAY_PON;
+    };
+} AON_REG_SCH_PLN_CMPNT1_DELAY_PON_TYPE;
+
+/*0x4000_0c90 AON_REG_SCH_PLN_CMPNT1_DELAY_PON*/
+#define AON_REG_SCH_PLN_CMPNT1_DELAY_PON_CMPNT1_DELAY_PON_Pos                                                            0U
+#define AON_REG_SCH_PLN_CMPNT1_DELAY_PON_CMPNT1_DELAY_PON_Msk                                                            (0xFFFFFFFFUL << AON_REG_SCH_PLN_CMPNT1_DELAY_PON_CMPNT1_DELAY_PON_Pos)
+
+/* 0xC94    0x4000_0c94
+    31:0    R/W     CMPNT1_DELAY_POF                                            32'b0
+ */
+typedef union _AON_REG_SCH_PLN_CMPNT1_DELAY_POF_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t CMPNT1_DELAY_POF;
+    };
+} AON_REG_SCH_PLN_CMPNT1_DELAY_POF_TYPE;
+
+/*0x4000_0c94 AON_REG_SCH_PLN_CMPNT1_DELAY_POF*/
+#define AON_REG_SCH_PLN_CMPNT1_DELAY_POF_CMPNT1_DELAY_POF_Pos                                                            0U
+#define AON_REG_SCH_PLN_CMPNT1_DELAY_POF_CMPNT1_DELAY_POF_Msk                                                            (0xFFFFFFFFUL << AON_REG_SCH_PLN_CMPNT1_DELAY_POF_CMPNT1_DELAY_POF_Pos)
+
+/* 0xC98    0x4000_0c98
+    31:0    R/W     CMPNT2_DELAY_PON                                            32'b0
+ */
+typedef union _AON_REG_SCH_PLN_CMPNT2_DELAY_PON_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t CMPNT2_DELAY_PON;
+    };
+} AON_REG_SCH_PLN_CMPNT2_DELAY_PON_TYPE;
+
+/*0x4000_0c98 AON_REG_SCH_PLN_CMPNT2_DELAY_PON*/
+#define AON_REG_SCH_PLN_CMPNT2_DELAY_PON_CMPNT2_DELAY_PON_Pos                                                            0U
+#define AON_REG_SCH_PLN_CMPNT2_DELAY_PON_CMPNT2_DELAY_PON_Msk                                                            (0xFFFFFFFFUL << AON_REG_SCH_PLN_CMPNT2_DELAY_PON_CMPNT2_DELAY_PON_Pos)
+
+/* 0xC9C    0x4000_0c9c
+    31:0    R/W     CMPNT2_DELAY_POF                                            32'b0
+ */
+typedef union _AON_REG_SCH_PLN_CMPNT2_DELAY_POF_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t CMPNT2_DELAY_POF;
+    };
+} AON_REG_SCH_PLN_CMPNT2_DELAY_POF_TYPE;
+
+/*0x4000_0c9c AON_REG_SCH_PLN_CMPNT2_DELAY_POF*/
+#define AON_REG_SCH_PLN_CMPNT2_DELAY_POF_CMPNT2_DELAY_POF_Pos                                                            0U
+#define AON_REG_SCH_PLN_CMPNT2_DELAY_POF_CMPNT2_DELAY_POF_Msk                                                            (0xFFFFFFFFUL << AON_REG_SCH_PLN_CMPNT2_DELAY_POF_CMPNT2_DELAY_POF_Pos)
+
+/* 0xCA0    0x4000_0ca0
+    31:0    R/W     CMPNT3_DELAY_PON                                            32'b0
+ */
+typedef union _AON_REG_SCH_PLN_CMPNT3_DELAY_PON_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t CMPNT3_DELAY_PON;
+    };
+} AON_REG_SCH_PLN_CMPNT3_DELAY_PON_TYPE;
+
+/*0x4000_0ca0 AON_REG_SCH_PLN_CMPNT3_DELAY_PON*/
+#define AON_REG_SCH_PLN_CMPNT3_DELAY_PON_CMPNT3_DELAY_PON_Pos                                                            0U
+#define AON_REG_SCH_PLN_CMPNT3_DELAY_PON_CMPNT3_DELAY_PON_Msk                                                            (0xFFFFFFFFUL << AON_REG_SCH_PLN_CMPNT3_DELAY_PON_CMPNT3_DELAY_PON_Pos)
+
+/* 0xCA4    0x4000_0ca4
+    31:0    R/W     CMPNT3_DELAY_POF                                            32'b0
+ */
+typedef union _AON_REG_SCH_PLN_CMPNT3_DELAY_POF_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t CMPNT3_DELAY_POF;
+    };
+} AON_REG_SCH_PLN_CMPNT3_DELAY_POF_TYPE;
+
+/*0x4000_0ca4 AON_REG_SCH_PLN_CMPNT3_DELAY_POF*/
+#define AON_REG_SCH_PLN_CMPNT3_DELAY_POF_CMPNT3_DELAY_POF_Pos                                                            0U
+#define AON_REG_SCH_PLN_CMPNT3_DELAY_POF_CMPNT3_DELAY_POF_Msk                                                            (0xFFFFFFFFUL << AON_REG_SCH_PLN_CMPNT3_DELAY_POF_CMPNT3_DELAY_POF_Pos)
+
+/* 0xCA8    0x4000_0ca8
+    31:0    R/W     CMPNT4_DELAY_PON                                            32'b0
+ */
+typedef union _AON_REG_SCH_PLN_CMPNT4_DELAY_PON_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t CMPNT4_DELAY_PON;
+    };
+} AON_REG_SCH_PLN_CMPNT4_DELAY_PON_TYPE;
+
+/*0x4000_0ca8 AON_REG_SCH_PLN_CMPNT4_DELAY_PON*/
+#define AON_REG_SCH_PLN_CMPNT4_DELAY_PON_CMPNT4_DELAY_PON_Pos                                                            0U
+#define AON_REG_SCH_PLN_CMPNT4_DELAY_PON_CMPNT4_DELAY_PON_Msk                                                            (0xFFFFFFFFUL << AON_REG_SCH_PLN_CMPNT4_DELAY_PON_CMPNT4_DELAY_PON_Pos)
+
+/* 0xCAC    0x4000_0cac
+    31:0    R/W     CMPNT4_DELAY_POF                                            32'b0
+ */
+typedef union _AON_REG_SCH_PLN_CMPNT4_DELAY_POF_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t CMPNT4_DELAY_POF;
+    };
+} AON_REG_SCH_PLN_CMPNT4_DELAY_POF_TYPE;
+
+/*0x4000_0cac AON_REG_SCH_PLN_CMPNT4_DELAY_POF*/
+#define AON_REG_SCH_PLN_CMPNT4_DELAY_POF_CMPNT4_DELAY_POF_Pos                                                            0U
+#define AON_REG_SCH_PLN_CMPNT4_DELAY_POF_CMPNT4_DELAY_POF_Msk                                                            (0xFFFFFFFFUL << AON_REG_SCH_PLN_CMPNT4_DELAY_POF_CMPNT4_DELAY_POF_Pos)
+
+/* 0xCB0    0x4000_0cb0
+    31:0    R/W     CMPNT5_DELAY_PON                                            32'b0
+ */
+typedef union _AON_REG_SCH_PLN_CMPNT5_DELAY_PON_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t CMPNT5_DELAY_PON;
+    };
+} AON_REG_SCH_PLN_CMPNT5_DELAY_PON_TYPE;
+
+/*0x4000_0cb0 AON_REG_SCH_PLN_CMPNT5_DELAY_PON*/
+#define AON_REG_SCH_PLN_CMPNT5_DELAY_PON_CMPNT5_DELAY_PON_Pos                                                            0U
+#define AON_REG_SCH_PLN_CMPNT5_DELAY_PON_CMPNT5_DELAY_PON_Msk                                                            (0xFFFFFFFFUL << AON_REG_SCH_PLN_CMPNT5_DELAY_PON_CMPNT5_DELAY_PON_Pos)
+
+/* 0xCB4    0x4000_0cb4
+    31:0    R/W     CMPNT5_DELAY_POF                                            32'b0
+ */
+typedef union _AON_REG_SCH_PLN_CMPNT5_DELAY_POF_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t CMPNT5_DELAY_POF;
+    };
+} AON_REG_SCH_PLN_CMPNT5_DELAY_POF_TYPE;
+
+/*0x4000_0cb4 AON_REG_SCH_PLN_CMPNT5_DELAY_POF*/
+#define AON_REG_SCH_PLN_CMPNT5_DELAY_POF_CMPNT5_DELAY_POF_Pos                                                            0U
+#define AON_REG_SCH_PLN_CMPNT5_DELAY_POF_CMPNT5_DELAY_POF_Msk                                                            (0xFFFFFFFFUL << AON_REG_SCH_PLN_CMPNT5_DELAY_POF_CMPNT5_DELAY_POF_Pos)
+
+/* 0xCB8    0x4000_0cb8
+    31:0    R/W     CMPNT6_DELAY_PON                                            32'b0
+ */
+typedef union _AON_REG_SCH_PLN_CMPNT6_DELAY_PON_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t CMPNT6_DELAY_PON;
+    };
+} AON_REG_SCH_PLN_CMPNT6_DELAY_PON_TYPE;
+
+/*0x4000_0cb8 AON_REG_SCH_PLN_CMPNT6_DELAY_PON*/
+#define AON_REG_SCH_PLN_CMPNT6_DELAY_PON_CMPNT6_DELAY_PON_Pos                                                            0U
+#define AON_REG_SCH_PLN_CMPNT6_DELAY_PON_CMPNT6_DELAY_PON_Msk                                                            (0xFFFFFFFFUL << AON_REG_SCH_PLN_CMPNT6_DELAY_PON_CMPNT6_DELAY_PON_Pos)
+
+/* 0xCBC    0x4000_0cbc
+    31:0    R/W     CMPNT6_DELAY_POF                                            32'b0
+ */
+typedef union _AON_REG_SCH_PLN_CMPNT6_DELAY_POF_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t CMPNT6_DELAY_POF;
+    };
+} AON_REG_SCH_PLN_CMPNT6_DELAY_POF_TYPE;
+
+/*0x4000_0cbc AON_REG_SCH_PLN_CMPNT6_DELAY_POF*/
+#define AON_REG_SCH_PLN_CMPNT6_DELAY_POF_CMPNT6_DELAY_POF_Pos                                                            0U
+#define AON_REG_SCH_PLN_CMPNT6_DELAY_POF_CMPNT6_DELAY_POF_Msk                                                            (0xFFFFFFFFUL << AON_REG_SCH_PLN_CMPNT6_DELAY_POF_CMPNT6_DELAY_POF_Pos)
+
+/* 0xCC0    0x4000_0cc0
+    31:0    R/W     CMPNT7_DELAY_PON                                            32'b0
+ */
+typedef union _AON_REG_SCH_PLN_CMPNT7_DELAY_PON_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t CMPNT7_DELAY_PON;
+    };
+} AON_REG_SCH_PLN_CMPNT7_DELAY_PON_TYPE;
+
+/*0x4000_0cc0 AON_REG_SCH_PLN_CMPNT7_DELAY_PON*/
+#define AON_REG_SCH_PLN_CMPNT7_DELAY_PON_CMPNT7_DELAY_PON_Pos                                                            0U
+#define AON_REG_SCH_PLN_CMPNT7_DELAY_PON_CMPNT7_DELAY_PON_Msk                                                            (0xFFFFFFFFUL << AON_REG_SCH_PLN_CMPNT7_DELAY_PON_CMPNT7_DELAY_PON_Pos)
+
+/* 0xCC4    0x4000_0cc4
+    31:0    R/W     CMPNT7_DELAY_POF                                            32'b0
+ */
+typedef union _AON_REG_SCH_PLN_CMPNT7_DELAY_POF_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t CMPNT7_DELAY_POF;
+    };
+} AON_REG_SCH_PLN_CMPNT7_DELAY_POF_TYPE;
+
+/*0x4000_0cc4 AON_REG_SCH_PLN_CMPNT7_DELAY_POF*/
+#define AON_REG_SCH_PLN_CMPNT7_DELAY_POF_CMPNT7_DELAY_POF_Pos                                                            0U
+#define AON_REG_SCH_PLN_CMPNT7_DELAY_POF_CMPNT7_DELAY_POF_Msk                                                            (0xFFFFFFFFUL << AON_REG_SCH_PLN_CMPNT7_DELAY_POF_CMPNT7_DELAY_POF_Pos)
+
+/* 0xCC8    0x4000_0cc8
+    31:0    R/W     CMPNT8_DELAY_PON                                            32'b0
+ */
+typedef union _AON_REG_SCH_PLN_CMPNT8_DELAY_PON_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t CMPNT8_DELAY_PON;
+    };
+} AON_REG_SCH_PLN_CMPNT8_DELAY_PON_TYPE;
+
+/*0x4000_0cc8 AON_REG_SCH_PLN_CMPNT8_DELAY_PON*/
+#define AON_REG_SCH_PLN_CMPNT8_DELAY_PON_CMPNT8_DELAY_PON_Pos                                                            0U
+#define AON_REG_SCH_PLN_CMPNT8_DELAY_PON_CMPNT8_DELAY_PON_Msk                                                            (0xFFFFFFFFUL << AON_REG_SCH_PLN_CMPNT8_DELAY_PON_CMPNT8_DELAY_PON_Pos)
+
+/* 0xCCC    0x4000_0ccc
+    31:0    R/W     CMPNT8_DELAY_POF                                            32'b0
+ */
+typedef union _AON_REG_SCH_PLN_CMPNT8_DELAY_POF_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t CMPNT8_DELAY_POF;
+    };
+} AON_REG_SCH_PLN_CMPNT8_DELAY_POF_TYPE;
+
+/*0x4000_0ccc AON_REG_SCH_PLN_CMPNT8_DELAY_POF*/
+#define AON_REG_SCH_PLN_CMPNT8_DELAY_POF_CMPNT8_DELAY_POF_Pos                                                            0U
+#define AON_REG_SCH_PLN_CMPNT8_DELAY_POF_CMPNT8_DELAY_POF_Msk                                                            (0xFFFFFFFFUL << AON_REG_SCH_PLN_CMPNT8_DELAY_POF_CMPNT8_DELAY_POF_Pos)
+
+/* 0xCD0    0x4000_0cd0
+    31:0    R/W     CMPNT9_DELAY_PON                                            32'b0
+ */
+typedef union _AON_REG_SCH_PLN_CMPNT9_DELAY_PON_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t CMPNT9_DELAY_PON;
+    };
+} AON_REG_SCH_PLN_CMPNT9_DELAY_PON_TYPE;
+
+/*0x4000_0cd0 AON_REG_SCH_PLN_CMPNT9_DELAY_PON*/
+#define AON_REG_SCH_PLN_CMPNT9_DELAY_PON_CMPNT9_DELAY_PON_Pos                                                            0U
+#define AON_REG_SCH_PLN_CMPNT9_DELAY_PON_CMPNT9_DELAY_PON_Msk                                                            (0xFFFFFFFFUL << AON_REG_SCH_PLN_CMPNT9_DELAY_PON_CMPNT9_DELAY_PON_Pos)
+
+/* 0xCD4    0x4000_0cd4
+    31:0    R/W     CMPNT9_DELAY_POF                                            32'b0
+ */
+typedef union _AON_REG_SCH_PLN_CMPNT9_DELAY_POF_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t CMPNT9_DELAY_POF;
+    };
+} AON_REG_SCH_PLN_CMPNT9_DELAY_POF_TYPE;
+
+/*0x4000_0cd4 AON_REG_SCH_PLN_CMPNT9_DELAY_POF*/
+#define AON_REG_SCH_PLN_CMPNT9_DELAY_POF_CMPNT9_DELAY_POF_Pos                                                            0U
+#define AON_REG_SCH_PLN_CMPNT9_DELAY_POF_CMPNT9_DELAY_POF_Msk                                                            (0xFFFFFFFFUL << AON_REG_SCH_PLN_CMPNT9_DELAY_POF_CMPNT9_DELAY_POF_Pos)
+
+/* 0xCD8    0x4000_0cd8
+    0       R/W     SCH_PLN_QACT_CLK_MAN_DATA                                   1'h0
+    1       R/W     SCH_PLN_QACT_CLK_MAN_EN                                     1'h0
+    31:2    R       SCH_PLN_INTR_CLR_RESERVED31_2                               30'b0
+ */
+typedef union _AON_REG_SCH_PLN_QACTIVE_CTRL_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t SCH_PLN_QACT_CLK_MAN_DATA: 1;
+        uint32_t SCH_PLN_QACT_CLK_MAN_EN: 1;
+        uint32_t SCH_PLN_INTR_CLR_RESERVED31_2: 30;
+    };
+} AON_REG_SCH_PLN_QACTIVE_CTRL_TYPE;
+
+/*0x4000_0cd8 AON_REG_SCH_PLN_QACTIVE_CTRL*/
+#define AON_REG_SCH_PLN_QACTIVE_CTRL_SCH_PLN_QACT_CLK_MAN_DATA_Pos                                                       0U
+#define AON_REG_SCH_PLN_QACTIVE_CTRL_SCH_PLN_QACT_CLK_MAN_DATA_Msk                                                       (0x1UL << AON_REG_SCH_PLN_QACTIVE_CTRL_SCH_PLN_QACT_CLK_MAN_DATA_Pos)
+
+#define AON_REG_SCH_PLN_QACTIVE_CTRL_SCH_PLN_QACT_CLK_MAN_EN_Pos                                                         1U
+#define AON_REG_SCH_PLN_QACTIVE_CTRL_SCH_PLN_QACT_CLK_MAN_EN_Msk                                                         (0x1UL << AON_REG_SCH_PLN_QACTIVE_CTRL_SCH_PLN_QACT_CLK_MAN_EN_Pos)
+
+#define AON_REG_SCH_PLN_QACTIVE_CTRL_SCH_PLN_INTR_CLR_RESERVED31_2_Pos                                                   2U
+#define AON_REG_SCH_PLN_QACTIVE_CTRL_SCH_PLN_INTR_CLR_RESERVED31_2_Msk                                                   (0x3FFFFFFFUL << AON_REG_SCH_PLN_QACTIVE_CTRL_SCH_PLN_INTR_CLR_RESERVED31_2_Pos)
+
+/* 0xCDC    0x4000_0cdc
+    31:0    R       SCH_PLN_VERSION                                             32'h20240827
+ */
+typedef union _AON_REG_SCH_PLN_VERSION_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t SCH_PLN_VERSION;
+    };
+} AON_REG_SCH_PLN_VERSION_TYPE;
+
+/*0x4000_0cdc AON_REG_SCH_PLN_VERSION*/
+#define AON_REG_SCH_PLN_VERSION_SCH_PLN_VERSION_Pos                                                                      0U
+#define AON_REG_SCH_PLN_VERSION_SCH_PLN_VERSION_Msk                                                                      (0xFFFFFFFFUL << AON_REG_SCH_PLN_VERSION_SCH_PLN_VERSION_Pos)
+
+/* 0xCE0    0x4000_0ce0
+    31:0    R/W     TREE0_ROOT_CHECK_TIME                                       32'b0
+ */
+typedef union _AON_REG_SCH_PLN_TREE0_ROOT_CHECK_TIME_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t TREE0_ROOT_CHECK_TIME;
+    };
+} AON_REG_SCH_PLN_TREE0_ROOT_CHECK_TIME_TYPE;
+
+/*0x4000_0ce0 AON_REG_SCH_PLN_TREE0_ROOT_CHECK_TIME*/
+#define AON_REG_SCH_PLN_TREE0_ROOT_CHECK_TIME_TREE0_ROOT_CHECK_TIME_Pos                                                  0U
+#define AON_REG_SCH_PLN_TREE0_ROOT_CHECK_TIME_TREE0_ROOT_CHECK_TIME_Msk                                                  (0xFFFFFFFFUL << AON_REG_SCH_PLN_TREE0_ROOT_CHECK_TIME_TREE0_ROOT_CHECK_TIME_Pos)
+
+/* 0xCE4    0x4000_0ce4
+    31:0    R/W     TREE1_ROOT_CHECK_TIME                                       32'b0
+ */
+typedef union _AON_REG_SCH_PLN_TREE1_ROOT_CHECK_TIME_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t TREE1_ROOT_CHECK_TIME;
+    };
+} AON_REG_SCH_PLN_TREE1_ROOT_CHECK_TIME_TYPE;
+
+/*0x4000_0ce4 AON_REG_SCH_PLN_TREE1_ROOT_CHECK_TIME*/
+#define AON_REG_SCH_PLN_TREE1_ROOT_CHECK_TIME_TREE1_ROOT_CHECK_TIME_Pos                                                  0U
+#define AON_REG_SCH_PLN_TREE1_ROOT_CHECK_TIME_TREE1_ROOT_CHECK_TIME_Msk                                                  (0xFFFFFFFFUL << AON_REG_SCH_PLN_TREE1_ROOT_CHECK_TIME_TREE1_ROOT_CHECK_TIME_Pos)
+
+/* 0xCF0    0x4000_0cf0
+    0       R/W     GTC_CNT_START                                               1'b1
+    1       R/WAC   GTC_CNT_RST                                                 1'b0
+    30:2    R       GTC_CTRL_RESERVED29_2                                       29'h0
+    31      R/W     GTC_RST                                                     1'b0
+ */
+typedef union _AON_REG_GTC_CTRL_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t GTC_CNT_START: 1;
+        uint32_t GTC_CNT_RST: 1;
+        uint32_t GTC_CTRL_RESERVED29_2: 29;
+        uint32_t GTC_RST: 1;
+    };
+} AON_REG_GTC_CTRL_TYPE;
+
+/*0x4000_0cf0 AON_REG_GTC_CTRL*/
+#define AON_REG_GTC_CTRL_GTC_CNT_START_Pos                                                                               0U
+#define AON_REG_GTC_CTRL_GTC_CNT_START_Msk                                                                               (0x1UL << AON_REG_GTC_CTRL_GTC_CNT_START_Pos)
+
+#define AON_REG_GTC_CTRL_GTC_CNT_RST_Pos                                                                                 1U
+#define AON_REG_GTC_CTRL_GTC_CNT_RST_Msk                                                                                 (0x1UL << AON_REG_GTC_CTRL_GTC_CNT_RST_Pos)
+
+#define AON_REG_GTC_CTRL_GTC_CTRL_RESERVED29_2_Pos                                                                       2U
+#define AON_REG_GTC_CTRL_GTC_CTRL_RESERVED29_2_Msk                                                                       (0x1FFFFFFFUL << AON_REG_GTC_CTRL_GTC_CTRL_RESERVED29_2_Pos)
+
+#define AON_REG_GTC_CTRL_GTC_RST_Pos                                                                                     31U
+#define AON_REG_GTC_CTRL_GTC_RST_Msk                                                                                     (0x1UL << AON_REG_GTC_CTRL_GTC_RST_Pos)
+
+/* 0xCF4    0x4000_0cf4
+    31:0    R       GLOBAL_TIME_COUNTER_VALUE                                   32'b0
+ */
+typedef union _AON_REG_GTC_CNT_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t GLOBAL_TIME_COUNTER_VALUE;
+    };
+} AON_REG_GTC_CNT_TYPE;
+
+/*0x4000_0cf4 AON_REG_GTC_CNT*/
+#define AON_REG_GTC_CNT_GLOBAL_TIME_COUNTER_VALUE_Pos                                                                    0U
+#define AON_REG_GTC_CNT_GLOBAL_TIME_COUNTER_VALUE_Msk                                                                    (0xFFFFFFFFUL << AON_REG_GTC_CNT_GLOBAL_TIME_COUNTER_VALUE_Pos)
+
+/* 0xCF8    0x4000_0cf8
+    31:0    R       GTC_VERSION                                                 32'h20240930
+ */
+typedef union _AON_REG_GTC_VERSION_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t GTC_VERSION;
+    };
+} AON_REG_GTC_VERSION_TYPE;
+
+/*0x4000_0cf8 AON_REG_GTC_VERSION*/
+#define AON_REG_GTC_VERSION_GTC_VERSION_Pos                                                                              0U
+#define AON_REG_GTC_VERSION_GTC_VERSION_Msk                                                                              (0xFFFFFFFFUL << AON_REG_GTC_VERSION_GTC_VERSION_Pos)
+
+/* 0xD04    0x4000_0d04
+    30:0    R       GRTC_CTRL_RESERVED30_0                                      31'b0
+    31      R/W     GRTC_RST                                                    1'b0
+ */
+typedef union _AON_REG_GRTC_CTRL_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t GRTC_CTRL_RESERVED30_0: 31;
+        uint32_t GRTC_RST: 1;
+    };
+} AON_REG_GRTC_CTRL_TYPE;
+
+/*0x4000_0d04 AON_REG_GRTC_CTRL*/
+#define AON_REG_GRTC_CTRL_GRTC_CTRL_RESERVED30_0_Pos                                                                     0U
+#define AON_REG_GRTC_CTRL_GRTC_CTRL_RESERVED30_0_Msk                                                                     (0x7FFFFFFFUL << AON_REG_GRTC_CTRL_GRTC_CTRL_RESERVED30_0_Pos)
+
+#define AON_REG_GRTC_CTRL_GRTC_RST_Pos                                                                                   31U
+#define AON_REG_GRTC_CTRL_GRTC_RST_Msk                                                                                   (0x1UL << AON_REG_GRTC_CTRL_GRTC_RST_Pos)
+
+/* 0xD08    0x4000_0d08
+    0       R/W     GRTC_CMP0_NV_IE                                             1'b0
+    1       R/W     GRTC_CMP1_NV_IE                                             1'b0
+    2       R/W     GRTC_CMP2_NV_IE                                             1'b0
+    3       R/W     GRTC_CMP3_NV_IE                                             1'b0
+    4       R/W     GRTC_CMP4_NV_IE                                             1'b0
+    5       R/W     GRTC_CMP5_NV_IE                                             1'b0
+    6       R/W     GRTC_CMP6_NV_IE                                             1'b0
+    7       R/W     GRTC_CMP7_NV_IE                                             1'b0
+    31:8    R       GRTC_INTR_CTRL_RESERVED31_8                                 24'b0
+ */
+typedef union _AON_REG_GRTC_INTR_CTRL_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t GRTC_CMP0_NV_IE: 1;
+        uint32_t GRTC_CMP1_NV_IE: 1;
+        uint32_t GRTC_CMP2_NV_IE: 1;
+        uint32_t GRTC_CMP3_NV_IE: 1;
+        uint32_t GRTC_CMP4_NV_IE: 1;
+        uint32_t GRTC_CMP5_NV_IE: 1;
+        uint32_t GRTC_CMP6_NV_IE: 1;
+        uint32_t GRTC_CMP7_NV_IE: 1;
+        uint32_t GRTC_INTR_CTRL_RESERVED31_8: 24;
+    };
+} AON_REG_GRTC_INTR_CTRL_TYPE;
+
+/*0x4000_0d08 AON_REG_GRTC_INTR_CTRL*/
+#define AON_REG_GRTC_INTR_CTRL_GRTC_CMP0_NV_IE_Pos                                                                       0U
+#define AON_REG_GRTC_INTR_CTRL_GRTC_CMP0_NV_IE_Msk                                                                       (0x1UL << AON_REG_GRTC_INTR_CTRL_GRTC_CMP0_NV_IE_Pos)
+
+#define AON_REG_GRTC_INTR_CTRL_GRTC_CMP1_NV_IE_Pos                                                                       1U
+#define AON_REG_GRTC_INTR_CTRL_GRTC_CMP1_NV_IE_Msk                                                                       (0x1UL << AON_REG_GRTC_INTR_CTRL_GRTC_CMP1_NV_IE_Pos)
+
+#define AON_REG_GRTC_INTR_CTRL_GRTC_CMP2_NV_IE_Pos                                                                       2U
+#define AON_REG_GRTC_INTR_CTRL_GRTC_CMP2_NV_IE_Msk                                                                       (0x1UL << AON_REG_GRTC_INTR_CTRL_GRTC_CMP2_NV_IE_Pos)
+
+#define AON_REG_GRTC_INTR_CTRL_GRTC_CMP3_NV_IE_Pos                                                                       3U
+#define AON_REG_GRTC_INTR_CTRL_GRTC_CMP3_NV_IE_Msk                                                                       (0x1UL << AON_REG_GRTC_INTR_CTRL_GRTC_CMP3_NV_IE_Pos)
+
+#define AON_REG_GRTC_INTR_CTRL_GRTC_CMP4_NV_IE_Pos                                                                       4U
+#define AON_REG_GRTC_INTR_CTRL_GRTC_CMP4_NV_IE_Msk                                                                       (0x1UL << AON_REG_GRTC_INTR_CTRL_GRTC_CMP4_NV_IE_Pos)
+
+#define AON_REG_GRTC_INTR_CTRL_GRTC_CMP5_NV_IE_Pos                                                                       5U
+#define AON_REG_GRTC_INTR_CTRL_GRTC_CMP5_NV_IE_Msk                                                                       (0x1UL << AON_REG_GRTC_INTR_CTRL_GRTC_CMP5_NV_IE_Pos)
+
+#define AON_REG_GRTC_INTR_CTRL_GRTC_CMP6_NV_IE_Pos                                                                       6U
+#define AON_REG_GRTC_INTR_CTRL_GRTC_CMP6_NV_IE_Msk                                                                       (0x1UL << AON_REG_GRTC_INTR_CTRL_GRTC_CMP6_NV_IE_Pos)
+
+#define AON_REG_GRTC_INTR_CTRL_GRTC_CMP7_NV_IE_Pos                                                                       7U
+#define AON_REG_GRTC_INTR_CTRL_GRTC_CMP7_NV_IE_Msk                                                                       (0x1UL << AON_REG_GRTC_INTR_CTRL_GRTC_CMP7_NV_IE_Pos)
+
+#define AON_REG_GRTC_INTR_CTRL_GRTC_INTR_CTRL_RESERVED31_8_Pos                                                           8U
+#define AON_REG_GRTC_INTR_CTRL_GRTC_INTR_CTRL_RESERVED31_8_Msk                                                           (0xFFFFFFUL << AON_REG_GRTC_INTR_CTRL_GRTC_INTR_CTRL_RESERVED31_8_Pos)
+
+/* 0xD0C    0x4000_0d0c
+    0       R       GRTC_CMP0_NV_SR                                             1'b0
+    1       R       GRTC_CMP1_NV_SR                                             1'b0
+    2       R       GRTC_CMP2_NV_SR                                             1'b0
+    3       R       GRTC_CMP3_NV_SR                                             1'b0
+    4       R       GRTC_CMP4_NV_SR                                             1'b0
+    5       R       GRTC_CMP5_NV_SR                                             1'b0
+    6       R       GRTC_CMP6_NV_SR                                             1'b0
+    7       R       GRTC_CMP7_NV_SR                                             1'b0
+    31:8    R       GRTC_COMP_INTR_SR_RESERVED31_8                              24'b0
+ */
+typedef union _AON_REG_GRTC_COMP_INTR_SR_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t GRTC_CMP0_NV_SR: 1;
+        uint32_t GRTC_CMP1_NV_SR: 1;
+        uint32_t GRTC_CMP2_NV_SR: 1;
+        uint32_t GRTC_CMP3_NV_SR: 1;
+        uint32_t GRTC_CMP4_NV_SR: 1;
+        uint32_t GRTC_CMP5_NV_SR: 1;
+        uint32_t GRTC_CMP6_NV_SR: 1;
+        uint32_t GRTC_CMP7_NV_SR: 1;
+        uint32_t GRTC_COMP_INTR_SR_RESERVED31_8: 24;
+    };
+} AON_REG_GRTC_COMP_INTR_SR_TYPE;
+
+/*0x4000_0d0c AON_REG_GRTC_COMP_INTR_SR*/
+#define AON_REG_GRTC_COMP_INTR_SR_GRTC_CMP0_NV_SR_Pos                                                                    0U
+#define AON_REG_GRTC_COMP_INTR_SR_GRTC_CMP0_NV_SR_Msk                                                                    (0x1UL << AON_REG_GRTC_COMP_INTR_SR_GRTC_CMP0_NV_SR_Pos)
+
+#define AON_REG_GRTC_COMP_INTR_SR_GRTC_CMP1_NV_SR_Pos                                                                    1U
+#define AON_REG_GRTC_COMP_INTR_SR_GRTC_CMP1_NV_SR_Msk                                                                    (0x1UL << AON_REG_GRTC_COMP_INTR_SR_GRTC_CMP1_NV_SR_Pos)
+
+#define AON_REG_GRTC_COMP_INTR_SR_GRTC_CMP2_NV_SR_Pos                                                                    2U
+#define AON_REG_GRTC_COMP_INTR_SR_GRTC_CMP2_NV_SR_Msk                                                                    (0x1UL << AON_REG_GRTC_COMP_INTR_SR_GRTC_CMP2_NV_SR_Pos)
+
+#define AON_REG_GRTC_COMP_INTR_SR_GRTC_CMP3_NV_SR_Pos                                                                    3U
+#define AON_REG_GRTC_COMP_INTR_SR_GRTC_CMP3_NV_SR_Msk                                                                    (0x1UL << AON_REG_GRTC_COMP_INTR_SR_GRTC_CMP3_NV_SR_Pos)
+
+#define AON_REG_GRTC_COMP_INTR_SR_GRTC_CMP4_NV_SR_Pos                                                                    4U
+#define AON_REG_GRTC_COMP_INTR_SR_GRTC_CMP4_NV_SR_Msk                                                                    (0x1UL << AON_REG_GRTC_COMP_INTR_SR_GRTC_CMP4_NV_SR_Pos)
+
+#define AON_REG_GRTC_COMP_INTR_SR_GRTC_CMP5_NV_SR_Pos                                                                    5U
+#define AON_REG_GRTC_COMP_INTR_SR_GRTC_CMP5_NV_SR_Msk                                                                    (0x1UL << AON_REG_GRTC_COMP_INTR_SR_GRTC_CMP5_NV_SR_Pos)
+
+#define AON_REG_GRTC_COMP_INTR_SR_GRTC_CMP6_NV_SR_Pos                                                                    6U
+#define AON_REG_GRTC_COMP_INTR_SR_GRTC_CMP6_NV_SR_Msk                                                                    (0x1UL << AON_REG_GRTC_COMP_INTR_SR_GRTC_CMP6_NV_SR_Pos)
+
+#define AON_REG_GRTC_COMP_INTR_SR_GRTC_CMP7_NV_SR_Pos                                                                    7U
+#define AON_REG_GRTC_COMP_INTR_SR_GRTC_CMP7_NV_SR_Msk                                                                    (0x1UL << AON_REG_GRTC_COMP_INTR_SR_GRTC_CMP7_NV_SR_Pos)
+
+#define AON_REG_GRTC_COMP_INTR_SR_GRTC_COMP_INTR_SR_RESERVED31_8_Pos                                                     8U
+#define AON_REG_GRTC_COMP_INTR_SR_GRTC_COMP_INTR_SR_RESERVED31_8_Msk                                                     (0xFFFFFFUL << AON_REG_GRTC_COMP_INTR_SR_GRTC_COMP_INTR_SR_RESERVED31_8_Pos)
+
+/* 0xD10    0x4000_0d10
+    0       R/WAC   GRTC_CMP0_NV_CLR                                            1'b0
+    1       R/WAC   GRTC_CMP1_NV_CLR                                            1'b0
+    2       R/WAC   GRTC_CMP2_NV_CLR                                            1'b0
+    3       R/WAC   GRTC_CMP3_NV_CLR                                            1'b0
+    4       R/WAC   GRTC_CMP4_NV_CLR                                            1'b0
+    5       R/WAC   GRTC_CMP5_NV_CLR                                            1'b0
+    6       R/WAC   GRTC_CMP6_NV_CLR                                            1'b0
+    7       R/WAC   GRTC_CMP7_NV_CLR                                            1'b0
+    31:8    R       GRTC_COMP_INTR_CLR_RESERVED31_8                             24'b0
+ */
+typedef union _AON_REG_GRTC_COMP_INT_CLR_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t GRTC_CMP0_NV_CLR: 1;
+        uint32_t GRTC_CMP1_NV_CLR: 1;
+        uint32_t GRTC_CMP2_NV_CLR: 1;
+        uint32_t GRTC_CMP3_NV_CLR: 1;
+        uint32_t GRTC_CMP4_NV_CLR: 1;
+        uint32_t GRTC_CMP5_NV_CLR: 1;
+        uint32_t GRTC_CMP6_NV_CLR: 1;
+        uint32_t GRTC_CMP7_NV_CLR: 1;
+        uint32_t GRTC_COMP_INTR_CLR_RESERVED31_8: 24;
+    };
+} AON_REG_GRTC_COMP_INT_CLR_TYPE;
+
+/*0x4000_0d10 AON_REG_GRTC_COMP_INT_CLR*/
+#define AON_REG_GRTC_COMP_INT_CLR_GRTC_CMP0_NV_CLR_Pos                                                                   0U
+#define AON_REG_GRTC_COMP_INT_CLR_GRTC_CMP0_NV_CLR_Msk                                                                   (0x1UL << AON_REG_GRTC_COMP_INT_CLR_GRTC_CMP0_NV_CLR_Pos)
+
+#define AON_REG_GRTC_COMP_INT_CLR_GRTC_CMP1_NV_CLR_Pos                                                                   1U
+#define AON_REG_GRTC_COMP_INT_CLR_GRTC_CMP1_NV_CLR_Msk                                                                   (0x1UL << AON_REG_GRTC_COMP_INT_CLR_GRTC_CMP1_NV_CLR_Pos)
+
+#define AON_REG_GRTC_COMP_INT_CLR_GRTC_CMP2_NV_CLR_Pos                                                                   2U
+#define AON_REG_GRTC_COMP_INT_CLR_GRTC_CMP2_NV_CLR_Msk                                                                   (0x1UL << AON_REG_GRTC_COMP_INT_CLR_GRTC_CMP2_NV_CLR_Pos)
+
+#define AON_REG_GRTC_COMP_INT_CLR_GRTC_CMP3_NV_CLR_Pos                                                                   3U
+#define AON_REG_GRTC_COMP_INT_CLR_GRTC_CMP3_NV_CLR_Msk                                                                   (0x1UL << AON_REG_GRTC_COMP_INT_CLR_GRTC_CMP3_NV_CLR_Pos)
+
+#define AON_REG_GRTC_COMP_INT_CLR_GRTC_CMP4_NV_CLR_Pos                                                                   4U
+#define AON_REG_GRTC_COMP_INT_CLR_GRTC_CMP4_NV_CLR_Msk                                                                   (0x1UL << AON_REG_GRTC_COMP_INT_CLR_GRTC_CMP4_NV_CLR_Pos)
+
+#define AON_REG_GRTC_COMP_INT_CLR_GRTC_CMP5_NV_CLR_Pos                                                                   5U
+#define AON_REG_GRTC_COMP_INT_CLR_GRTC_CMP5_NV_CLR_Msk                                                                   (0x1UL << AON_REG_GRTC_COMP_INT_CLR_GRTC_CMP5_NV_CLR_Pos)
+
+#define AON_REG_GRTC_COMP_INT_CLR_GRTC_CMP6_NV_CLR_Pos                                                                   6U
+#define AON_REG_GRTC_COMP_INT_CLR_GRTC_CMP6_NV_CLR_Msk                                                                   (0x1UL << AON_REG_GRTC_COMP_INT_CLR_GRTC_CMP6_NV_CLR_Pos)
+
+#define AON_REG_GRTC_COMP_INT_CLR_GRTC_CMP7_NV_CLR_Pos                                                                   7U
+#define AON_REG_GRTC_COMP_INT_CLR_GRTC_CMP7_NV_CLR_Msk                                                                   (0x1UL << AON_REG_GRTC_COMP_INT_CLR_GRTC_CMP7_NV_CLR_Pos)
+
+#define AON_REG_GRTC_COMP_INT_CLR_GRTC_COMP_INTR_CLR_RESERVED31_8_Pos                                                    8U
+#define AON_REG_GRTC_COMP_INT_CLR_GRTC_COMP_INTR_CLR_RESERVED31_8_Msk                                                    (0xFFFFFFUL << AON_REG_GRTC_COMP_INT_CLR_GRTC_COMP_INTR_CLR_RESERVED31_8_Pos)
+
+/* 0xD14    0x4000_0d14
+    31:0    R/W     GRTC_CMP0                                                   32'b0
+ */
+typedef union _AON_REG_GRTC_COMP_0_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t GRTC_CMP0;
+    };
+} AON_REG_GRTC_COMP_0_TYPE;
+
+/*0x4000_0d14 AON_REG_GRTC_COMP_0*/
+#define AON_REG_GRTC_COMP_0_GRTC_CMP0_Pos                                                                                0U
+#define AON_REG_GRTC_COMP_0_GRTC_CMP0_Msk                                                                                (0xFFFFFFFFUL << AON_REG_GRTC_COMP_0_GRTC_CMP0_Pos)
+
+/* 0xD18    0x4000_0d18
+    31:0    R/W     GRTC_CMP1                                                   32'b0
+ */
+typedef union _AON_REG_GRTC_COMP_1_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t GRTC_CMP1;
+    };
+} AON_REG_GRTC_COMP_1_TYPE;
+
+/*0x4000_0d18 AON_REG_GRTC_COMP_1*/
+#define AON_REG_GRTC_COMP_1_GRTC_CMP1_Pos                                                                                0U
+#define AON_REG_GRTC_COMP_1_GRTC_CMP1_Msk                                                                                (0xFFFFFFFFUL << AON_REG_GRTC_COMP_1_GRTC_CMP1_Pos)
+
+/* 0xD1C    0x4000_0d1c
+    31:0    R/W     GRTC_CMP2                                                   32'b0
+ */
+typedef union _AON_REG_GRTC_COMP_2_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t GRTC_CMP2;
+    };
+} AON_REG_GRTC_COMP_2_TYPE;
+
+/*0x4000_0d1c AON_REG_GRTC_COMP_2*/
+#define AON_REG_GRTC_COMP_2_GRTC_CMP2_Pos                                                                                0U
+#define AON_REG_GRTC_COMP_2_GRTC_CMP2_Msk                                                                                (0xFFFFFFFFUL << AON_REG_GRTC_COMP_2_GRTC_CMP2_Pos)
+
+/* 0xD20    0x4000_0d20
+    31:0    R/W     GRTC_CMP3                                                   32'b0
+ */
+typedef union _AON_REG_GRTC_COMP_3_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t GRTC_CMP3;
+    };
+} AON_REG_GRTC_COMP_3_TYPE;
+
+/*0x4000_0d20 AON_REG_GRTC_COMP_3*/
+#define AON_REG_GRTC_COMP_3_GRTC_CMP3_Pos                                                                                0U
+#define AON_REG_GRTC_COMP_3_GRTC_CMP3_Msk                                                                                (0xFFFFFFFFUL << AON_REG_GRTC_COMP_3_GRTC_CMP3_Pos)
+
+/* 0xD24    0x4000_0d24
+    31:0    R/W     GRTC_CMP4                                                   32'b0
+ */
+typedef union _AON_REG_GRTC_COMP_4_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t GRTC_CMP4;
+    };
+} AON_REG_GRTC_COMP_4_TYPE;
+
+/*0x4000_0d24 AON_REG_GRTC_COMP_4*/
+#define AON_REG_GRTC_COMP_4_GRTC_CMP4_Pos                                                                                0U
+#define AON_REG_GRTC_COMP_4_GRTC_CMP4_Msk                                                                                (0xFFFFFFFFUL << AON_REG_GRTC_COMP_4_GRTC_CMP4_Pos)
+
+/* 0xD28    0x4000_0d28
+    31:0    R/W     GRTC_CMP5                                                   32'b0
+ */
+typedef union _AON_REG_GRTC_COMP_5_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t GRTC_CMP5;
+    };
+} AON_REG_GRTC_COMP_5_TYPE;
+
+/*0x4000_0d28 AON_REG_GRTC_COMP_5*/
+#define AON_REG_GRTC_COMP_5_GRTC_CMP5_Pos                                                                                0U
+#define AON_REG_GRTC_COMP_5_GRTC_CMP5_Msk                                                                                (0xFFFFFFFFUL << AON_REG_GRTC_COMP_5_GRTC_CMP5_Pos)
+
+/* 0xD2C    0x4000_0d2c
+    31:0    R/W     GRTC_CMP6                                                   32'b0
+ */
+typedef union _AON_REG_GRTC_COMP_6_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t GRTC_CMP6;
+    };
+} AON_REG_GRTC_COMP_6_TYPE;
+
+/*0x4000_0d2c AON_REG_GRTC_COMP_6*/
+#define AON_REG_GRTC_COMP_6_GRTC_CMP6_Pos                                                                                0U
+#define AON_REG_GRTC_COMP_6_GRTC_CMP6_Msk                                                                                (0xFFFFFFFFUL << AON_REG_GRTC_COMP_6_GRTC_CMP6_Pos)
+
+/* 0xD30    0x4000_0d30
+    31:0    R/W     GRTC_CMP7                                                   32'b0
+ */
+typedef union _AON_REG_GRTC_COMP_7_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t GRTC_CMP7;
+    };
+} AON_REG_GRTC_COMP_7_TYPE;
+
+/*0x4000_0d30 AON_REG_GRTC_COMP_7*/
+#define AON_REG_GRTC_COMP_7_GRTC_CMP7_Pos                                                                                0U
+#define AON_REG_GRTC_COMP_7_GRTC_CMP7_Msk                                                                                (0xFFFFFFFFUL << AON_REG_GRTC_COMP_7_GRTC_CMP7_Pos)
+
+/* 0xD34    0x4000_0d34
+    0       R/W     GRTC_CMP0_RELOAD_EN                                         1'h0
+    1       R/W     GRTC_CMP1_RELOAD_EN                                         1'b0
+    2       R/W     GRTC_CMP2_RELOAD_EN                                         1'b0
+    3       R/W     GRTC_CMP3_RELOAD_EN                                         1'b0
+    4       R/W     GRTC_CMP4_RELOAD_EN                                         1'b0
+    5       R/W     GRTC_CMP5_RELOAD_EN                                         1'b0
+    6       R/W     GRTC_CMP6_RELOAD_EN                                         1'b0
+    7       R/W     GRTC_CMP7_RELOAD_EN                                         1'b0
+    31:8    R       GRTC_COMP_RELOAD_CTRL_RESERVED31_8                          24'b0
+ */
+typedef union _AON_REG_GRTC_RELOAD_CTRL_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t GRTC_CMP0_RELOAD_EN: 1;
+        uint32_t GRTC_CMP1_RELOAD_EN: 1;
+        uint32_t GRTC_CMP2_RELOAD_EN: 1;
+        uint32_t GRTC_CMP3_RELOAD_EN: 1;
+        uint32_t GRTC_CMP4_RELOAD_EN: 1;
+        uint32_t GRTC_CMP5_RELOAD_EN: 1;
+        uint32_t GRTC_CMP6_RELOAD_EN: 1;
+        uint32_t GRTC_CMP7_RELOAD_EN: 1;
+        uint32_t GRTC_COMP_RELOAD_CTRL_RESERVED31_8: 24;
+    };
+} AON_REG_GRTC_RELOAD_CTRL_TYPE;
+
+/*0x4000_0d34 AON_REG_GRTC_RELOAD_CTRL*/
+#define AON_REG_GRTC_RELOAD_CTRL_GRTC_CMP0_RELOAD_EN_Pos                                                                 0U
+#define AON_REG_GRTC_RELOAD_CTRL_GRTC_CMP0_RELOAD_EN_Msk                                                                 (0x1UL << AON_REG_GRTC_RELOAD_CTRL_GRTC_CMP0_RELOAD_EN_Pos)
+
+#define AON_REG_GRTC_RELOAD_CTRL_GRTC_CMP1_RELOAD_EN_Pos                                                                 1U
+#define AON_REG_GRTC_RELOAD_CTRL_GRTC_CMP1_RELOAD_EN_Msk                                                                 (0x1UL << AON_REG_GRTC_RELOAD_CTRL_GRTC_CMP1_RELOAD_EN_Pos)
+
+#define AON_REG_GRTC_RELOAD_CTRL_GRTC_CMP2_RELOAD_EN_Pos                                                                 2U
+#define AON_REG_GRTC_RELOAD_CTRL_GRTC_CMP2_RELOAD_EN_Msk                                                                 (0x1UL << AON_REG_GRTC_RELOAD_CTRL_GRTC_CMP2_RELOAD_EN_Pos)
+
+#define AON_REG_GRTC_RELOAD_CTRL_GRTC_CMP3_RELOAD_EN_Pos                                                                 3U
+#define AON_REG_GRTC_RELOAD_CTRL_GRTC_CMP3_RELOAD_EN_Msk                                                                 (0x1UL << AON_REG_GRTC_RELOAD_CTRL_GRTC_CMP3_RELOAD_EN_Pos)
+
+#define AON_REG_GRTC_RELOAD_CTRL_GRTC_CMP4_RELOAD_EN_Pos                                                                 4U
+#define AON_REG_GRTC_RELOAD_CTRL_GRTC_CMP4_RELOAD_EN_Msk                                                                 (0x1UL << AON_REG_GRTC_RELOAD_CTRL_GRTC_CMP4_RELOAD_EN_Pos)
+
+#define AON_REG_GRTC_RELOAD_CTRL_GRTC_CMP5_RELOAD_EN_Pos                                                                 5U
+#define AON_REG_GRTC_RELOAD_CTRL_GRTC_CMP5_RELOAD_EN_Msk                                                                 (0x1UL << AON_REG_GRTC_RELOAD_CTRL_GRTC_CMP5_RELOAD_EN_Pos)
+
+#define AON_REG_GRTC_RELOAD_CTRL_GRTC_CMP6_RELOAD_EN_Pos                                                                 6U
+#define AON_REG_GRTC_RELOAD_CTRL_GRTC_CMP6_RELOAD_EN_Msk                                                                 (0x1UL << AON_REG_GRTC_RELOAD_CTRL_GRTC_CMP6_RELOAD_EN_Pos)
+
+#define AON_REG_GRTC_RELOAD_CTRL_GRTC_CMP7_RELOAD_EN_Pos                                                                 7U
+#define AON_REG_GRTC_RELOAD_CTRL_GRTC_CMP7_RELOAD_EN_Msk                                                                 (0x1UL << AON_REG_GRTC_RELOAD_CTRL_GRTC_CMP7_RELOAD_EN_Pos)
+
+#define AON_REG_GRTC_RELOAD_CTRL_GRTC_COMP_RELOAD_CTRL_RESERVED31_8_Pos                                                  8U
+#define AON_REG_GRTC_RELOAD_CTRL_GRTC_COMP_RELOAD_CTRL_RESERVED31_8_Msk                                                  (0xFFFFFFUL << AON_REG_GRTC_RELOAD_CTRL_GRTC_COMP_RELOAD_CTRL_RESERVED31_8_Pos)
+
+/* 0xD38    0x4000_0d38
+    31:0    R/W     GRTC_CMP0_RELOAD                                            32'b0
+ */
+typedef union _AON_REG_GRTC_COMP_0_RELOAD_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t GRTC_CMP0_RELOAD;
+    };
+} AON_REG_GRTC_COMP_0_RELOAD_TYPE;
+
+/*0x4000_0d38 AON_REG_GRTC_COMP_0_RELOAD*/
+#define AON_REG_GRTC_COMP_0_RELOAD_GRTC_CMP0_RELOAD_Pos                                                                  0U
+#define AON_REG_GRTC_COMP_0_RELOAD_GRTC_CMP0_RELOAD_Msk                                                                  (0xFFFFFFFFUL << AON_REG_GRTC_COMP_0_RELOAD_GRTC_CMP0_RELOAD_Pos)
+
+/* 0xD3C    0x4000_0d3c
+    31:0    R/W     GRTC_CMP1_RELOAD                                            32'b0
+ */
+typedef union _AON_REG_GRTC_COMP_1_RELOAD_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t GRTC_CMP1_RELOAD;
+    };
+} AON_REG_GRTC_COMP_1_RELOAD_TYPE;
+
+/*0x4000_0d3c AON_REG_GRTC_COMP_1_RELOAD*/
+#define AON_REG_GRTC_COMP_1_RELOAD_GRTC_CMP1_RELOAD_Pos                                                                  0U
+#define AON_REG_GRTC_COMP_1_RELOAD_GRTC_CMP1_RELOAD_Msk                                                                  (0xFFFFFFFFUL << AON_REG_GRTC_COMP_1_RELOAD_GRTC_CMP1_RELOAD_Pos)
+
+/* 0xD40    0x4000_0d40
+    31:0    R/W     GRTC_CMP2_RELOAD                                            32'b0
+ */
+typedef union _AON_REG_GRTC_COMP_2_RELOAD_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t GRTC_CMP2_RELOAD;
+    };
+} AON_REG_GRTC_COMP_2_RELOAD_TYPE;
+
+/*0x4000_0d40 AON_REG_GRTC_COMP_2_RELOAD*/
+#define AON_REG_GRTC_COMP_2_RELOAD_GRTC_CMP2_RELOAD_Pos                                                                  0U
+#define AON_REG_GRTC_COMP_2_RELOAD_GRTC_CMP2_RELOAD_Msk                                                                  (0xFFFFFFFFUL << AON_REG_GRTC_COMP_2_RELOAD_GRTC_CMP2_RELOAD_Pos)
+
+/* 0xD44    0x4000_0d44
+    31:0    R/W     GRTC_CMP3_RELOAD                                            32'b0
+ */
+typedef union _AON_REG_GRTC_COMP_3_RELOAD_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t GRTC_CMP3_RELOAD;
+    };
+} AON_REG_GRTC_COMP_3_RELOAD_TYPE;
+
+/*0x4000_0d44 AON_REG_GRTC_COMP_3_RELOAD*/
+#define AON_REG_GRTC_COMP_3_RELOAD_GRTC_CMP3_RELOAD_Pos                                                                  0U
+#define AON_REG_GRTC_COMP_3_RELOAD_GRTC_CMP3_RELOAD_Msk                                                                  (0xFFFFFFFFUL << AON_REG_GRTC_COMP_3_RELOAD_GRTC_CMP3_RELOAD_Pos)
+
+/* 0xD48    0x4000_0d48
+    31:0    R/W     GRTC_CMP4_RELOAD                                            32'b0
+ */
+typedef union _AON_REG_GRTC_COMP_4_RELOAD_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t GRTC_CMP4_RELOAD;
+    };
+} AON_REG_GRTC_COMP_4_RELOAD_TYPE;
+
+/*0x4000_0d48 AON_REG_GRTC_COMP_4_RELOAD*/
+#define AON_REG_GRTC_COMP_4_RELOAD_GRTC_CMP4_RELOAD_Pos                                                                  0U
+#define AON_REG_GRTC_COMP_4_RELOAD_GRTC_CMP4_RELOAD_Msk                                                                  (0xFFFFFFFFUL << AON_REG_GRTC_COMP_4_RELOAD_GRTC_CMP4_RELOAD_Pos)
+
+/* 0xD4C    0x4000_0d4c
+    31:0    R/W     GRTC_CMP5_RELOAD                                            32'b0
+ */
+typedef union _AON_REG_GRTC_COMP_5_RELOAD_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t GRTC_CMP5_RELOAD;
+    };
+} AON_REG_GRTC_COMP_5_RELOAD_TYPE;
+
+/*0x4000_0d4c AON_REG_GRTC_COMP_5_RELOAD*/
+#define AON_REG_GRTC_COMP_5_RELOAD_GRTC_CMP5_RELOAD_Pos                                                                  0U
+#define AON_REG_GRTC_COMP_5_RELOAD_GRTC_CMP5_RELOAD_Msk                                                                  (0xFFFFFFFFUL << AON_REG_GRTC_COMP_5_RELOAD_GRTC_CMP5_RELOAD_Pos)
+
+/* 0xD50    0x4000_0d50
+    31:0    R/W     GRTC_CMP6_RELOAD                                            32'b0
+ */
+typedef union _AON_REG_GRTC_COMP_6_RELOAD_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t GRTC_CMP6_RELOAD;
+    };
+} AON_REG_GRTC_COMP_6_RELOAD_TYPE;
+
+/*0x4000_0d50 AON_REG_GRTC_COMP_6_RELOAD*/
+#define AON_REG_GRTC_COMP_6_RELOAD_GRTC_CMP6_RELOAD_Pos                                                                  0U
+#define AON_REG_GRTC_COMP_6_RELOAD_GRTC_CMP6_RELOAD_Msk                                                                  (0xFFFFFFFFUL << AON_REG_GRTC_COMP_6_RELOAD_GRTC_CMP6_RELOAD_Pos)
+
+/* 0xD54    0x4000_0d54
+    31:0    R/W     GRTC_CMP7_RELOAD                                            32'b0
+ */
+typedef union _AON_REG_GRTC_COMP_7_RELOAD_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t GRTC_CMP7_RELOAD;
+    };
+} AON_REG_GRTC_COMP_7_RELOAD_TYPE;
+
+/*0x4000_0d54 AON_REG_GRTC_COMP_7_RELOAD*/
+#define AON_REG_GRTC_COMP_7_RELOAD_GRTC_CMP7_RELOAD_Pos                                                                  0U
+#define AON_REG_GRTC_COMP_7_RELOAD_GRTC_CMP7_RELOAD_Msk                                                                  (0xFFFFFFFFUL << AON_REG_GRTC_COMP_7_RELOAD_GRTC_CMP7_RELOAD_Pos)
+
+/* 0xD58    0x4000_0d58
+    0       R/W     GRTC_CMP0_SLEEP_CTRL                                        1'h0
+    1       R/W     GRTC_CMP1_SLEEP_CTRL                                        1'b0
+    2       R/W     GRTC_CMP2_SLEEP_CTRL                                        1'b0
+    3       R/W     GRTC_CMP3_SLEEP_CTRL                                        1'b0
+    4       R/W     GRTC_CMP4_SLEEP_CTRL                                        1'b0
+    5       R/W     GRTC_CMP5_SLEEP_CTRL                                        1'b0
+    6       R/W     GRTC_CMP6_SLEEP_CTRL                                        1'b0
+    7       R/W     GRTC_CMP7_SLEEP_CTRL                                        1'b0
+    31:8    R       GRTC_SLEEP_CTRL_RESERVED31_8                                24'b0
+ */
+typedef union _AON_REG_GRTC_SLEEP_CTRL_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t GRTC_CMP0_SLEEP_CTRL: 1;
+        uint32_t GRTC_CMP1_SLEEP_CTRL: 1;
+        uint32_t GRTC_CMP2_SLEEP_CTRL: 1;
+        uint32_t GRTC_CMP3_SLEEP_CTRL: 1;
+        uint32_t GRTC_CMP4_SLEEP_CTRL: 1;
+        uint32_t GRTC_CMP5_SLEEP_CTRL: 1;
+        uint32_t GRTC_CMP6_SLEEP_CTRL: 1;
+        uint32_t GRTC_CMP7_SLEEP_CTRL: 1;
+        uint32_t GRTC_SLEEP_CTRL_RESERVED31_8: 24;
+    };
+} AON_REG_GRTC_SLEEP_CTRL_TYPE;
+
+/*0x4000_0d58 AON_REG_GRTC_SLEEP_CTRL*/
+#define AON_REG_GRTC_SLEEP_CTRL_GRTC_CMP0_SLEEP_CTRL_Pos                                                                 0U
+#define AON_REG_GRTC_SLEEP_CTRL_GRTC_CMP0_SLEEP_CTRL_Msk                                                                 (0x1UL << AON_REG_GRTC_SLEEP_CTRL_GRTC_CMP0_SLEEP_CTRL_Pos)
+
+#define AON_REG_GRTC_SLEEP_CTRL_GRTC_CMP1_SLEEP_CTRL_Pos                                                                 1U
+#define AON_REG_GRTC_SLEEP_CTRL_GRTC_CMP1_SLEEP_CTRL_Msk                                                                 (0x1UL << AON_REG_GRTC_SLEEP_CTRL_GRTC_CMP1_SLEEP_CTRL_Pos)
+
+#define AON_REG_GRTC_SLEEP_CTRL_GRTC_CMP2_SLEEP_CTRL_Pos                                                                 2U
+#define AON_REG_GRTC_SLEEP_CTRL_GRTC_CMP2_SLEEP_CTRL_Msk                                                                 (0x1UL << AON_REG_GRTC_SLEEP_CTRL_GRTC_CMP2_SLEEP_CTRL_Pos)
+
+#define AON_REG_GRTC_SLEEP_CTRL_GRTC_CMP3_SLEEP_CTRL_Pos                                                                 3U
+#define AON_REG_GRTC_SLEEP_CTRL_GRTC_CMP3_SLEEP_CTRL_Msk                                                                 (0x1UL << AON_REG_GRTC_SLEEP_CTRL_GRTC_CMP3_SLEEP_CTRL_Pos)
+
+#define AON_REG_GRTC_SLEEP_CTRL_GRTC_CMP4_SLEEP_CTRL_Pos                                                                 4U
+#define AON_REG_GRTC_SLEEP_CTRL_GRTC_CMP4_SLEEP_CTRL_Msk                                                                 (0x1UL << AON_REG_GRTC_SLEEP_CTRL_GRTC_CMP4_SLEEP_CTRL_Pos)
+
+#define AON_REG_GRTC_SLEEP_CTRL_GRTC_CMP5_SLEEP_CTRL_Pos                                                                 5U
+#define AON_REG_GRTC_SLEEP_CTRL_GRTC_CMP5_SLEEP_CTRL_Msk                                                                 (0x1UL << AON_REG_GRTC_SLEEP_CTRL_GRTC_CMP5_SLEEP_CTRL_Pos)
+
+#define AON_REG_GRTC_SLEEP_CTRL_GRTC_CMP6_SLEEP_CTRL_Pos                                                                 6U
+#define AON_REG_GRTC_SLEEP_CTRL_GRTC_CMP6_SLEEP_CTRL_Msk                                                                 (0x1UL << AON_REG_GRTC_SLEEP_CTRL_GRTC_CMP6_SLEEP_CTRL_Pos)
+
+#define AON_REG_GRTC_SLEEP_CTRL_GRTC_CMP7_SLEEP_CTRL_Pos                                                                 7U
+#define AON_REG_GRTC_SLEEP_CTRL_GRTC_CMP7_SLEEP_CTRL_Msk                                                                 (0x1UL << AON_REG_GRTC_SLEEP_CTRL_GRTC_CMP7_SLEEP_CTRL_Pos)
+
+#define AON_REG_GRTC_SLEEP_CTRL_GRTC_SLEEP_CTRL_RESERVED31_8_Pos                                                         8U
+#define AON_REG_GRTC_SLEEP_CTRL_GRTC_SLEEP_CTRL_RESERVED31_8_Msk                                                         (0xFFFFFFUL << AON_REG_GRTC_SLEEP_CTRL_GRTC_SLEEP_CTRL_RESERVED31_8_Pos)
+
+/* 0xD5C    0x4000_0d5c
+    31:0    R       GRTC_CMP0_SLEEP_PENDING_CNT                                 32'b0
+ */
+typedef union _AON_REG_GRTC_COMP_0_SLEEP_PENDING_CNT_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t GRTC_CMP0_SLEEP_PENDING_CNT;
+    };
+} AON_REG_GRTC_COMP_0_SLEEP_PENDING_CNT_TYPE;
+
+/*0x4000_0d5c AON_REG_GRTC_COMP_0_SLEEP_PENDING_CNT*/
+#define AON_REG_GRTC_COMP_0_SLEEP_PENDING_CNT_GRTC_CMP0_SLEEP_PENDING_CNT_Pos                                            0U
+#define AON_REG_GRTC_COMP_0_SLEEP_PENDING_CNT_GRTC_CMP0_SLEEP_PENDING_CNT_Msk                                            (0xFFFFFFFFUL << AON_REG_GRTC_COMP_0_SLEEP_PENDING_CNT_GRTC_CMP0_SLEEP_PENDING_CNT_Pos)
+
+/* 0xD60    0x4000_0d60
+    31:0    R       GRTC_CMP1_SLEEP_PENDING_CNT                                 32'b0
+ */
+typedef union _AON_REG_GRTC_COMP_1_SLEEP_PENDING_CNT_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t GRTC_CMP1_SLEEP_PENDING_CNT;
+    };
+} AON_REG_GRTC_COMP_1_SLEEP_PENDING_CNT_TYPE;
+
+/*0x4000_0d60 AON_REG_GRTC_COMP_1_SLEEP_PENDING_CNT*/
+#define AON_REG_GRTC_COMP_1_SLEEP_PENDING_CNT_GRTC_CMP1_SLEEP_PENDING_CNT_Pos                                            0U
+#define AON_REG_GRTC_COMP_1_SLEEP_PENDING_CNT_GRTC_CMP1_SLEEP_PENDING_CNT_Msk                                            (0xFFFFFFFFUL << AON_REG_GRTC_COMP_1_SLEEP_PENDING_CNT_GRTC_CMP1_SLEEP_PENDING_CNT_Pos)
+
+/* 0xD64    0x4000_0d64
+    31:0    R       GRTC_CMP2_SLEEP_PENDING_CNT                                 32'b0
+ */
+typedef union _AON_REG_GRTC_COMP_2_SLEEP_PENDING_CNT_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t GRTC_CMP2_SLEEP_PENDING_CNT;
+    };
+} AON_REG_GRTC_COMP_2_SLEEP_PENDING_CNT_TYPE;
+
+/*0x4000_0d64 AON_REG_GRTC_COMP_2_SLEEP_PENDING_CNT*/
+#define AON_REG_GRTC_COMP_2_SLEEP_PENDING_CNT_GRTC_CMP2_SLEEP_PENDING_CNT_Pos                                            0U
+#define AON_REG_GRTC_COMP_2_SLEEP_PENDING_CNT_GRTC_CMP2_SLEEP_PENDING_CNT_Msk                                            (0xFFFFFFFFUL << AON_REG_GRTC_COMP_2_SLEEP_PENDING_CNT_GRTC_CMP2_SLEEP_PENDING_CNT_Pos)
+
+/* 0xD68    0x4000_0d68
+    31:0    R       GRTC_CMP3_SLEEP_PENDING_CNT                                 32'b0
+ */
+typedef union _AON_REG_GRTC_COMP_3_SLEEP_PENDING_CNT_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t GRTC_CMP3_SLEEP_PENDING_CNT;
+    };
+} AON_REG_GRTC_COMP_3_SLEEP_PENDING_CNT_TYPE;
+
+/*0x4000_0d68 AON_REG_GRTC_COMP_3_SLEEP_PENDING_CNT*/
+#define AON_REG_GRTC_COMP_3_SLEEP_PENDING_CNT_GRTC_CMP3_SLEEP_PENDING_CNT_Pos                                            0U
+#define AON_REG_GRTC_COMP_3_SLEEP_PENDING_CNT_GRTC_CMP3_SLEEP_PENDING_CNT_Msk                                            (0xFFFFFFFFUL << AON_REG_GRTC_COMP_3_SLEEP_PENDING_CNT_GRTC_CMP3_SLEEP_PENDING_CNT_Pos)
+
+/* 0xD6C    0x4000_0d6c
+    31:0    R       GRTC_CMP4_SLEEP_PENDING_CNT                                 32'b0
+ */
+typedef union _AON_REG_GRTC_COMP_4_SLEEP_PENDING_CNT_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t GRTC_CMP4_SLEEP_PENDING_CNT;
+    };
+} AON_REG_GRTC_COMP_4_SLEEP_PENDING_CNT_TYPE;
+
+/*0x4000_0d6c AON_REG_GRTC_COMP_4_SLEEP_PENDING_CNT*/
+#define AON_REG_GRTC_COMP_4_SLEEP_PENDING_CNT_GRTC_CMP4_SLEEP_PENDING_CNT_Pos                                            0U
+#define AON_REG_GRTC_COMP_4_SLEEP_PENDING_CNT_GRTC_CMP4_SLEEP_PENDING_CNT_Msk                                            (0xFFFFFFFFUL << AON_REG_GRTC_COMP_4_SLEEP_PENDING_CNT_GRTC_CMP4_SLEEP_PENDING_CNT_Pos)
+
+/* 0xD70    0x4000_0d70
+    31:0    R       GRTC_CMP5_SLEEP_PENDING_CNT                                 32'b0
+ */
+typedef union _AON_REG_GRTC_COMP_5_SLEEP_PENDING_CNT_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t GRTC_CMP5_SLEEP_PENDING_CNT;
+    };
+} AON_REG_GRTC_COMP_5_SLEEP_PENDING_CNT_TYPE;
+
+/*0x4000_0d70 AON_REG_GRTC_COMP_5_SLEEP_PENDING_CNT*/
+#define AON_REG_GRTC_COMP_5_SLEEP_PENDING_CNT_GRTC_CMP5_SLEEP_PENDING_CNT_Pos                                            0U
+#define AON_REG_GRTC_COMP_5_SLEEP_PENDING_CNT_GRTC_CMP5_SLEEP_PENDING_CNT_Msk                                            (0xFFFFFFFFUL << AON_REG_GRTC_COMP_5_SLEEP_PENDING_CNT_GRTC_CMP5_SLEEP_PENDING_CNT_Pos)
+
+/* 0xD74    0x4000_0d74
+    31:0    R       GRTC_CMP6_SLEEP_PENDING_CNT                                 32'b0
+ */
+typedef union _AON_REG_GRTC_COMP_6_SLEEP_PENDING_CNT_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t GRTC_CMP6_SLEEP_PENDING_CNT;
+    };
+} AON_REG_GRTC_COMP_6_SLEEP_PENDING_CNT_TYPE;
+
+/*0x4000_0d74 AON_REG_GRTC_COMP_6_SLEEP_PENDING_CNT*/
+#define AON_REG_GRTC_COMP_6_SLEEP_PENDING_CNT_GRTC_CMP6_SLEEP_PENDING_CNT_Pos                                            0U
+#define AON_REG_GRTC_COMP_6_SLEEP_PENDING_CNT_GRTC_CMP6_SLEEP_PENDING_CNT_Msk                                            (0xFFFFFFFFUL << AON_REG_GRTC_COMP_6_SLEEP_PENDING_CNT_GRTC_CMP6_SLEEP_PENDING_CNT_Pos)
+
+/* 0xD78    0x4000_0d78
+    31:0    R       GRTC_CMP7_SLEEP_PENDING_CNT                                 32'b0
+ */
+typedef union _AON_REG_GRTC_COMP_7_SLEEP_PENDING_CNT_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t GRTC_CMP7_SLEEP_PENDING_CNT;
+    };
+} AON_REG_GRTC_COMP_7_SLEEP_PENDING_CNT_TYPE;
+
+/*0x4000_0d78 AON_REG_GRTC_COMP_7_SLEEP_PENDING_CNT*/
+#define AON_REG_GRTC_COMP_7_SLEEP_PENDING_CNT_GRTC_CMP7_SLEEP_PENDING_CNT_Pos                                            0U
+#define AON_REG_GRTC_COMP_7_SLEEP_PENDING_CNT_GRTC_CMP7_SLEEP_PENDING_CNT_Msk                                            (0xFFFFFFFFUL << AON_REG_GRTC_COMP_7_SLEEP_PENDING_CNT_GRTC_CMP7_SLEEP_PENDING_CNT_Pos)
+
+/* 0xD7C    0x4000_0d7c
+    0       R/W     GRTC_CMP0_RAP_MODE                                          1'h0
+    1       R/W     GRTC_CMP1_RAP_MODE                                          1'h0
+    2       R/W     GRTC_CMP2_RAP_MODE                                          1'h0
+    3       R/W     GRTC_CMP3_RAP_MODE                                          1'h0
+    4       R/W     GRTC_CMP4_RAP_MODE                                          1'h0
+    5       R/W     GRTC_CMP5_RAP_MODE                                          1'h0
+    6       R/W     GRTC_CMP6_RAP_MODE                                          1'h0
+    7       R/W     GRTC_CMP7_RAP_MODE                                          1'h0
+    8       R/WAC   GRTC_FW_TASK_RELOAD_CMP0                                    1'h0
+    9       R/WAC   GRTC_FW_TASK_RELOAD_CMP1                                    1'b0
+    10      R/WAC   GRTC_FW_TASK_RELOAD_CMP2                                    1'b0
+    11      R/WAC   GRTC_FW_TASK_RELOAD_CMP3                                    1'b0
+    12      R/WAC   GRTC_FW_TASK_RELOAD_CMP4                                    1'b0
+    13      R/WAC   GRTC_FW_TASK_RELOAD_CMP5                                    1'b0
+    14      R/WAC   GRTC_FW_TASK_RELOAD_CMP6                                    1'b0
+    15      R/WAC   GRTC_FW_TASK_RELOAD_CMP7                                    1'b0
+    31:16   R       GRTC_TASK_CTRL_RESERVED31_16                                16'b0
+ */
+typedef union _AON_REG_GRTC_TASK_CTRL_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t GRTC_CMP0_RAP_MODE: 1;
+        uint32_t GRTC_CMP1_RAP_MODE: 1;
+        uint32_t GRTC_CMP2_RAP_MODE: 1;
+        uint32_t GRTC_CMP3_RAP_MODE: 1;
+        uint32_t GRTC_CMP4_RAP_MODE: 1;
+        uint32_t GRTC_CMP5_RAP_MODE: 1;
+        uint32_t GRTC_CMP6_RAP_MODE: 1;
+        uint32_t GRTC_CMP7_RAP_MODE: 1;
+        uint32_t GRTC_FW_TASK_RELOAD_CMP0: 1;
+        uint32_t GRTC_FW_TASK_RELOAD_CMP1: 1;
+        uint32_t GRTC_FW_TASK_RELOAD_CMP2: 1;
+        uint32_t GRTC_FW_TASK_RELOAD_CMP3: 1;
+        uint32_t GRTC_FW_TASK_RELOAD_CMP4: 1;
+        uint32_t GRTC_FW_TASK_RELOAD_CMP5: 1;
+        uint32_t GRTC_FW_TASK_RELOAD_CMP6: 1;
+        uint32_t GRTC_FW_TASK_RELOAD_CMP7: 1;
+        uint32_t GRTC_TASK_CTRL_RESERVED31_16: 16;
+    };
+} AON_REG_GRTC_TASK_CTRL_TYPE;
+
+/*0x4000_0d7c AON_REG_GRTC_TASK_CTRL*/
+#define AON_REG_GRTC_TASK_CTRL_GRTC_CMP0_RAP_MODE_Pos                                                                    0U
+#define AON_REG_GRTC_TASK_CTRL_GRTC_CMP0_RAP_MODE_Msk                                                                    (0x1UL << AON_REG_GRTC_TASK_CTRL_GRTC_CMP0_RAP_MODE_Pos)
+
+#define AON_REG_GRTC_TASK_CTRL_GRTC_CMP1_RAP_MODE_Pos                                                                    1U
+#define AON_REG_GRTC_TASK_CTRL_GRTC_CMP1_RAP_MODE_Msk                                                                    (0x1UL << AON_REG_GRTC_TASK_CTRL_GRTC_CMP1_RAP_MODE_Pos)
+
+#define AON_REG_GRTC_TASK_CTRL_GRTC_CMP2_RAP_MODE_Pos                                                                    2U
+#define AON_REG_GRTC_TASK_CTRL_GRTC_CMP2_RAP_MODE_Msk                                                                    (0x1UL << AON_REG_GRTC_TASK_CTRL_GRTC_CMP2_RAP_MODE_Pos)
+
+#define AON_REG_GRTC_TASK_CTRL_GRTC_CMP3_RAP_MODE_Pos                                                                    3U
+#define AON_REG_GRTC_TASK_CTRL_GRTC_CMP3_RAP_MODE_Msk                                                                    (0x1UL << AON_REG_GRTC_TASK_CTRL_GRTC_CMP3_RAP_MODE_Pos)
+
+#define AON_REG_GRTC_TASK_CTRL_GRTC_CMP4_RAP_MODE_Pos                                                                    4U
+#define AON_REG_GRTC_TASK_CTRL_GRTC_CMP4_RAP_MODE_Msk                                                                    (0x1UL << AON_REG_GRTC_TASK_CTRL_GRTC_CMP4_RAP_MODE_Pos)
+
+#define AON_REG_GRTC_TASK_CTRL_GRTC_CMP5_RAP_MODE_Pos                                                                    5U
+#define AON_REG_GRTC_TASK_CTRL_GRTC_CMP5_RAP_MODE_Msk                                                                    (0x1UL << AON_REG_GRTC_TASK_CTRL_GRTC_CMP5_RAP_MODE_Pos)
+
+#define AON_REG_GRTC_TASK_CTRL_GRTC_CMP6_RAP_MODE_Pos                                                                    6U
+#define AON_REG_GRTC_TASK_CTRL_GRTC_CMP6_RAP_MODE_Msk                                                                    (0x1UL << AON_REG_GRTC_TASK_CTRL_GRTC_CMP6_RAP_MODE_Pos)
+
+#define AON_REG_GRTC_TASK_CTRL_GRTC_CMP7_RAP_MODE_Pos                                                                    7U
+#define AON_REG_GRTC_TASK_CTRL_GRTC_CMP7_RAP_MODE_Msk                                                                    (0x1UL << AON_REG_GRTC_TASK_CTRL_GRTC_CMP7_RAP_MODE_Pos)
+
+#define AON_REG_GRTC_TASK_CTRL_GRTC_FW_TASK_RELOAD_CMP0_Pos                                                              8U
+#define AON_REG_GRTC_TASK_CTRL_GRTC_FW_TASK_RELOAD_CMP0_Msk                                                              (0x1UL << AON_REG_GRTC_TASK_CTRL_GRTC_FW_TASK_RELOAD_CMP0_Pos)
+
+#define AON_REG_GRTC_TASK_CTRL_GRTC_FW_TASK_RELOAD_CMP1_Pos                                                              9U
+#define AON_REG_GRTC_TASK_CTRL_GRTC_FW_TASK_RELOAD_CMP1_Msk                                                              (0x1UL << AON_REG_GRTC_TASK_CTRL_GRTC_FW_TASK_RELOAD_CMP1_Pos)
+
+#define AON_REG_GRTC_TASK_CTRL_GRTC_FW_TASK_RELOAD_CMP2_Pos                                                              10U
+#define AON_REG_GRTC_TASK_CTRL_GRTC_FW_TASK_RELOAD_CMP2_Msk                                                              (0x1UL << AON_REG_GRTC_TASK_CTRL_GRTC_FW_TASK_RELOAD_CMP2_Pos)
+
+#define AON_REG_GRTC_TASK_CTRL_GRTC_FW_TASK_RELOAD_CMP3_Pos                                                              11U
+#define AON_REG_GRTC_TASK_CTRL_GRTC_FW_TASK_RELOAD_CMP3_Msk                                                              (0x1UL << AON_REG_GRTC_TASK_CTRL_GRTC_FW_TASK_RELOAD_CMP3_Pos)
+
+#define AON_REG_GRTC_TASK_CTRL_GRTC_FW_TASK_RELOAD_CMP4_Pos                                                              12U
+#define AON_REG_GRTC_TASK_CTRL_GRTC_FW_TASK_RELOAD_CMP4_Msk                                                              (0x1UL << AON_REG_GRTC_TASK_CTRL_GRTC_FW_TASK_RELOAD_CMP4_Pos)
+
+#define AON_REG_GRTC_TASK_CTRL_GRTC_FW_TASK_RELOAD_CMP5_Pos                                                              13U
+#define AON_REG_GRTC_TASK_CTRL_GRTC_FW_TASK_RELOAD_CMP5_Msk                                                              (0x1UL << AON_REG_GRTC_TASK_CTRL_GRTC_FW_TASK_RELOAD_CMP5_Pos)
+
+#define AON_REG_GRTC_TASK_CTRL_GRTC_FW_TASK_RELOAD_CMP6_Pos                                                              14U
+#define AON_REG_GRTC_TASK_CTRL_GRTC_FW_TASK_RELOAD_CMP6_Msk                                                              (0x1UL << AON_REG_GRTC_TASK_CTRL_GRTC_FW_TASK_RELOAD_CMP6_Pos)
+
+#define AON_REG_GRTC_TASK_CTRL_GRTC_FW_TASK_RELOAD_CMP7_Pos                                                              15U
+#define AON_REG_GRTC_TASK_CTRL_GRTC_FW_TASK_RELOAD_CMP7_Msk                                                              (0x1UL << AON_REG_GRTC_TASK_CTRL_GRTC_FW_TASK_RELOAD_CMP7_Pos)
+
+#define AON_REG_GRTC_TASK_CTRL_GRTC_TASK_CTRL_RESERVED31_16_Pos                                                          16U
+#define AON_REG_GRTC_TASK_CTRL_GRTC_TASK_CTRL_RESERVED31_16_Msk                                                          (0xFFFFUL << AON_REG_GRTC_TASK_CTRL_GRTC_TASK_CTRL_RESERVED31_16_Pos)
+
+/* 0xD80    0x4000_0d80
+    0       R/W     GRTC_QACT_SCLK_MAN_DATA                                     1'h0
+    1       R/W     GRTC_QACT_SCLK_MAN_EN                                       1'h0
+    2       R/W     GRTC_QACT_PCLK_MAN_DATA                                     1'h0
+    3       R/W     GRTC_QACT_PCLK_MAN_EN                                       1'h0
+    7:4     R       GRTC_INTR_CLR_RESERVED7_4                                   4'b0
+    8       R/W     GRTC_CMP0_FORCE_QACT_EN                                     1'h0
+    9       R/W     GRTC_CMP1_FORCE_QACT_EN                                     1'h0
+    10      R/W     GRTC_CMP2_FORCE_QACT_EN                                     1'h0
+    11      R/W     GRTC_CMP3_FORCE_QACT_EN                                     1'h0
+    12      R/W     GRTC_CMP4_FORCE_QACT_EN                                     1'h0
+    13      R/W     GRTC_CMP5_FORCE_QACT_EN                                     1'h0
+    14      R/W     GRTC_CMP6_FORCE_QACT_EN                                     1'h0
+    15      R/W     GRTC_CMP7_FORCE_QACT_EN                                     1'h0
+    31:16   R       GRTC_INTR_CLR_RESERVED31_16                                 16'b0
+ */
+typedef union _AON_REG_GRTC_QACTIVE_CTRL_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t GRTC_QACT_SCLK_MAN_DATA: 1;
+        uint32_t GRTC_QACT_SCLK_MAN_EN: 1;
+        uint32_t GRTC_QACT_PCLK_MAN_DATA: 1;
+        uint32_t GRTC_QACT_PCLK_MAN_EN: 1;
+        uint32_t GRTC_INTR_CLR_RESERVED7_4: 4;
+        uint32_t GRTC_CMP0_FORCE_QACT_EN: 1;
+        uint32_t GRTC_CMP1_FORCE_QACT_EN: 1;
+        uint32_t GRTC_CMP2_FORCE_QACT_EN: 1;
+        uint32_t GRTC_CMP3_FORCE_QACT_EN: 1;
+        uint32_t GRTC_CMP4_FORCE_QACT_EN: 1;
+        uint32_t GRTC_CMP5_FORCE_QACT_EN: 1;
+        uint32_t GRTC_CMP6_FORCE_QACT_EN: 1;
+        uint32_t GRTC_CMP7_FORCE_QACT_EN: 1;
+        uint32_t GRTC_INTR_CLR_RESERVED31_16: 16;
+    };
+} AON_REG_GRTC_QACTIVE_CTRL_TYPE;
+
+/*0x4000_0d80 AON_REG_GRTC_QACTIVE_CTRL*/
+#define AON_REG_GRTC_QACTIVE_CTRL_GRTC_QACT_SCLK_MAN_DATA_Pos                                                            0U
+#define AON_REG_GRTC_QACTIVE_CTRL_GRTC_QACT_SCLK_MAN_DATA_Msk                                                            (0x1UL << AON_REG_GRTC_QACTIVE_CTRL_GRTC_QACT_SCLK_MAN_DATA_Pos)
+
+#define AON_REG_GRTC_QACTIVE_CTRL_GRTC_QACT_SCLK_MAN_EN_Pos                                                              1U
+#define AON_REG_GRTC_QACTIVE_CTRL_GRTC_QACT_SCLK_MAN_EN_Msk                                                              (0x1UL << AON_REG_GRTC_QACTIVE_CTRL_GRTC_QACT_SCLK_MAN_EN_Pos)
+
+#define AON_REG_GRTC_QACTIVE_CTRL_GRTC_QACT_PCLK_MAN_DATA_Pos                                                            2U
+#define AON_REG_GRTC_QACTIVE_CTRL_GRTC_QACT_PCLK_MAN_DATA_Msk                                                            (0x1UL << AON_REG_GRTC_QACTIVE_CTRL_GRTC_QACT_PCLK_MAN_DATA_Pos)
+
+#define AON_REG_GRTC_QACTIVE_CTRL_GRTC_QACT_PCLK_MAN_EN_Pos                                                              3U
+#define AON_REG_GRTC_QACTIVE_CTRL_GRTC_QACT_PCLK_MAN_EN_Msk                                                              (0x1UL << AON_REG_GRTC_QACTIVE_CTRL_GRTC_QACT_PCLK_MAN_EN_Pos)
+
+#define AON_REG_GRTC_QACTIVE_CTRL_GRTC_INTR_CLR_RESERVED7_4_Pos                                                          4U
+#define AON_REG_GRTC_QACTIVE_CTRL_GRTC_INTR_CLR_RESERVED7_4_Msk                                                          (0xFUL << AON_REG_GRTC_QACTIVE_CTRL_GRTC_INTR_CLR_RESERVED7_4_Pos)
+
+#define AON_REG_GRTC_QACTIVE_CTRL_GRTC_CMP0_FORCE_QACT_EN_Pos                                                            8U
+#define AON_REG_GRTC_QACTIVE_CTRL_GRTC_CMP0_FORCE_QACT_EN_Msk                                                            (0x1UL << AON_REG_GRTC_QACTIVE_CTRL_GRTC_CMP0_FORCE_QACT_EN_Pos)
+
+#define AON_REG_GRTC_QACTIVE_CTRL_GRTC_CMP1_FORCE_QACT_EN_Pos                                                            9U
+#define AON_REG_GRTC_QACTIVE_CTRL_GRTC_CMP1_FORCE_QACT_EN_Msk                                                            (0x1UL << AON_REG_GRTC_QACTIVE_CTRL_GRTC_CMP1_FORCE_QACT_EN_Pos)
+
+#define AON_REG_GRTC_QACTIVE_CTRL_GRTC_CMP2_FORCE_QACT_EN_Pos                                                            10U
+#define AON_REG_GRTC_QACTIVE_CTRL_GRTC_CMP2_FORCE_QACT_EN_Msk                                                            (0x1UL << AON_REG_GRTC_QACTIVE_CTRL_GRTC_CMP2_FORCE_QACT_EN_Pos)
+
+#define AON_REG_GRTC_QACTIVE_CTRL_GRTC_CMP3_FORCE_QACT_EN_Pos                                                            11U
+#define AON_REG_GRTC_QACTIVE_CTRL_GRTC_CMP3_FORCE_QACT_EN_Msk                                                            (0x1UL << AON_REG_GRTC_QACTIVE_CTRL_GRTC_CMP3_FORCE_QACT_EN_Pos)
+
+#define AON_REG_GRTC_QACTIVE_CTRL_GRTC_CMP4_FORCE_QACT_EN_Pos                                                            12U
+#define AON_REG_GRTC_QACTIVE_CTRL_GRTC_CMP4_FORCE_QACT_EN_Msk                                                            (0x1UL << AON_REG_GRTC_QACTIVE_CTRL_GRTC_CMP4_FORCE_QACT_EN_Pos)
+
+#define AON_REG_GRTC_QACTIVE_CTRL_GRTC_CMP5_FORCE_QACT_EN_Pos                                                            13U
+#define AON_REG_GRTC_QACTIVE_CTRL_GRTC_CMP5_FORCE_QACT_EN_Msk                                                            (0x1UL << AON_REG_GRTC_QACTIVE_CTRL_GRTC_CMP5_FORCE_QACT_EN_Pos)
+
+#define AON_REG_GRTC_QACTIVE_CTRL_GRTC_CMP6_FORCE_QACT_EN_Pos                                                            14U
+#define AON_REG_GRTC_QACTIVE_CTRL_GRTC_CMP6_FORCE_QACT_EN_Msk                                                            (0x1UL << AON_REG_GRTC_QACTIVE_CTRL_GRTC_CMP6_FORCE_QACT_EN_Pos)
+
+#define AON_REG_GRTC_QACTIVE_CTRL_GRTC_CMP7_FORCE_QACT_EN_Pos                                                            15U
+#define AON_REG_GRTC_QACTIVE_CTRL_GRTC_CMP7_FORCE_QACT_EN_Msk                                                            (0x1UL << AON_REG_GRTC_QACTIVE_CTRL_GRTC_CMP7_FORCE_QACT_EN_Pos)
+
+#define AON_REG_GRTC_QACTIVE_CTRL_GRTC_INTR_CLR_RESERVED31_16_Pos                                                        16U
+#define AON_REG_GRTC_QACTIVE_CTRL_GRTC_INTR_CLR_RESERVED31_16_Msk                                                        (0xFFFFUL << AON_REG_GRTC_QACTIVE_CTRL_GRTC_INTR_CLR_RESERVED31_16_Pos)
+
+/* 0xD84    0x4000_0d84
+    31:0    R       GRTC_RTL_VERSION                                            32'h20240930
+ */
+typedef union _AON_REG_GRTC_RTL_VERSION_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t GRTC_RTL_VERSION;
+    };
+} AON_REG_GRTC_RTL_VERSION_TYPE;
+
+/*0x4000_0d84 AON_REG_GRTC_RTL_VERSION*/
+#define AON_REG_GRTC_RTL_VERSION_GRTC_RTL_VERSION_Pos                                                                    0U
+#define AON_REG_GRTC_RTL_VERSION_GRTC_RTL_VERSION_Msk                                                                    (0xFFFFFFFFUL << AON_REG_GRTC_RTL_VERSION_GRTC_RTL_VERSION_Pos)
+
+/* 0xD88    0x4000_0d88
+    0       R       GRTC_CMP0_TIMEOUT_OV_ERR_SR                                 1'b0
+    1       R       GRTC_CMP1_TIMEOUT_OV_ERR_SR                                 1'b0
+    2       R       GRTC_CMP2_TIMEOUT_OV_ERR_SR                                 1'b0
+    3       R       GRTC_CMP3_TIMEOUT_OV_ERR_SR                                 1'b0
+    4       R       GRTC_CMP4_TIMEOUT_OV_ERR_SR                                 1'b0
+    5       R       GRTC_CMP5_TIMEOUT_OV_ERR_SR                                 1'b0
+    6       R       GRTC_CMP6_TIMEOUT_OV_ERR_SR                                 1'b0
+    7       R       GRTC_CMP7_TIMEOUT_OV_ERR_SR                                 1'b0
+    31:8    R       GRTC_COMP_TIMEOUT_OV_ERR_SR_RESERVED31_8                    24'b0
+ */
+typedef union _AON_REG_GRTC_COMP_TIMEOUT_OV_ERR_SR_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t GRTC_CMP0_TIMEOUT_OV_ERR_SR: 1;
+        uint32_t GRTC_CMP1_TIMEOUT_OV_ERR_SR: 1;
+        uint32_t GRTC_CMP2_TIMEOUT_OV_ERR_SR: 1;
+        uint32_t GRTC_CMP3_TIMEOUT_OV_ERR_SR: 1;
+        uint32_t GRTC_CMP4_TIMEOUT_OV_ERR_SR: 1;
+        uint32_t GRTC_CMP5_TIMEOUT_OV_ERR_SR: 1;
+        uint32_t GRTC_CMP6_TIMEOUT_OV_ERR_SR: 1;
+        uint32_t GRTC_CMP7_TIMEOUT_OV_ERR_SR: 1;
+        uint32_t GRTC_COMP_TIMEOUT_OV_ERR_SR_RESERVED31_8: 24;
+    };
+} AON_REG_GRTC_COMP_TIMEOUT_OV_ERR_SR_TYPE;
+
+/*0x4000_0d88 AON_REG_GRTC_COMP_TIMEOUT_OV_ERR_SR*/
+#define AON_REG_GRTC_COMP_TIMEOUT_OV_ERR_SR_GRTC_CMP0_TIMEOUT_OV_ERR_SR_Pos                                              0U
+#define AON_REG_GRTC_COMP_TIMEOUT_OV_ERR_SR_GRTC_CMP0_TIMEOUT_OV_ERR_SR_Msk                                              (0x1UL << AON_REG_GRTC_COMP_TIMEOUT_OV_ERR_SR_GRTC_CMP0_TIMEOUT_OV_ERR_SR_Pos)
+
+#define AON_REG_GRTC_COMP_TIMEOUT_OV_ERR_SR_GRTC_CMP1_TIMEOUT_OV_ERR_SR_Pos                                              1U
+#define AON_REG_GRTC_COMP_TIMEOUT_OV_ERR_SR_GRTC_CMP1_TIMEOUT_OV_ERR_SR_Msk                                              (0x1UL << AON_REG_GRTC_COMP_TIMEOUT_OV_ERR_SR_GRTC_CMP1_TIMEOUT_OV_ERR_SR_Pos)
+
+#define AON_REG_GRTC_COMP_TIMEOUT_OV_ERR_SR_GRTC_CMP2_TIMEOUT_OV_ERR_SR_Pos                                              2U
+#define AON_REG_GRTC_COMP_TIMEOUT_OV_ERR_SR_GRTC_CMP2_TIMEOUT_OV_ERR_SR_Msk                                              (0x1UL << AON_REG_GRTC_COMP_TIMEOUT_OV_ERR_SR_GRTC_CMP2_TIMEOUT_OV_ERR_SR_Pos)
+
+#define AON_REG_GRTC_COMP_TIMEOUT_OV_ERR_SR_GRTC_CMP3_TIMEOUT_OV_ERR_SR_Pos                                              3U
+#define AON_REG_GRTC_COMP_TIMEOUT_OV_ERR_SR_GRTC_CMP3_TIMEOUT_OV_ERR_SR_Msk                                              (0x1UL << AON_REG_GRTC_COMP_TIMEOUT_OV_ERR_SR_GRTC_CMP3_TIMEOUT_OV_ERR_SR_Pos)
+
+#define AON_REG_GRTC_COMP_TIMEOUT_OV_ERR_SR_GRTC_CMP4_TIMEOUT_OV_ERR_SR_Pos                                              4U
+#define AON_REG_GRTC_COMP_TIMEOUT_OV_ERR_SR_GRTC_CMP4_TIMEOUT_OV_ERR_SR_Msk                                              (0x1UL << AON_REG_GRTC_COMP_TIMEOUT_OV_ERR_SR_GRTC_CMP4_TIMEOUT_OV_ERR_SR_Pos)
+
+#define AON_REG_GRTC_COMP_TIMEOUT_OV_ERR_SR_GRTC_CMP5_TIMEOUT_OV_ERR_SR_Pos                                              5U
+#define AON_REG_GRTC_COMP_TIMEOUT_OV_ERR_SR_GRTC_CMP5_TIMEOUT_OV_ERR_SR_Msk                                              (0x1UL << AON_REG_GRTC_COMP_TIMEOUT_OV_ERR_SR_GRTC_CMP5_TIMEOUT_OV_ERR_SR_Pos)
+
+#define AON_REG_GRTC_COMP_TIMEOUT_OV_ERR_SR_GRTC_CMP6_TIMEOUT_OV_ERR_SR_Pos                                              6U
+#define AON_REG_GRTC_COMP_TIMEOUT_OV_ERR_SR_GRTC_CMP6_TIMEOUT_OV_ERR_SR_Msk                                              (0x1UL << AON_REG_GRTC_COMP_TIMEOUT_OV_ERR_SR_GRTC_CMP6_TIMEOUT_OV_ERR_SR_Pos)
+
+#define AON_REG_GRTC_COMP_TIMEOUT_OV_ERR_SR_GRTC_CMP7_TIMEOUT_OV_ERR_SR_Pos                                              7U
+#define AON_REG_GRTC_COMP_TIMEOUT_OV_ERR_SR_GRTC_CMP7_TIMEOUT_OV_ERR_SR_Msk                                              (0x1UL << AON_REG_GRTC_COMP_TIMEOUT_OV_ERR_SR_GRTC_CMP7_TIMEOUT_OV_ERR_SR_Pos)
+
+#define AON_REG_GRTC_COMP_TIMEOUT_OV_ERR_SR_GRTC_COMP_TIMEOUT_OV_ERR_SR_RESERVED31_8_Pos                                 8U
+#define AON_REG_GRTC_COMP_TIMEOUT_OV_ERR_SR_GRTC_COMP_TIMEOUT_OV_ERR_SR_RESERVED31_8_Msk                                 (0xFFFFFFUL << AON_REG_GRTC_COMP_TIMEOUT_OV_ERR_SR_GRTC_COMP_TIMEOUT_OV_ERR_SR_RESERVED31_8_Pos)
+
+/* 0xD8C    0x4000_0d8c
+    0       R/WAC   GRTC_CMP0_TIMEOUT_OV_ERR_CLR                                1'b0
+    1       R/WAC   GRTC_CMP1_TIMEOUT_OV_ERR_CLR                                1'b0
+    2       R/WAC   GRTC_CMP2_TIMEOUT_OV_ERR_CLR                                1'b0
+    3       R/WAC   GRTC_CMP3_TIMEOUT_OV_ERR_CLR                                1'b0
+    4       R/WAC   GRTC_CMP4_TIMEOUT_OV_ERR_CLR                                1'b0
+    5       R/WAC   GRTC_CMP5_TIMEOUT_OV_ERR_CLR                                1'b0
+    6       R/WAC   GRTC_CMP6_TIMEOUT_OV_ERR_CLR                                1'b0
+    7       R/WAC   GRTC_CMP7_TIMEOUT_OV_ERR_CLR                                1'b0
+    31:8    R       GRTC_COMP_TIMEOUT_OV_ERR_CLR_RESERVED31_8                   24'b0
+ */
+typedef union _AON_REG_GRTC_COMP_TIMEOUT_OV_ERR_CLR_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t GRTC_CMP0_TIMEOUT_OV_ERR_CLR: 1;
+        uint32_t GRTC_CMP1_TIMEOUT_OV_ERR_CLR: 1;
+        uint32_t GRTC_CMP2_TIMEOUT_OV_ERR_CLR: 1;
+        uint32_t GRTC_CMP3_TIMEOUT_OV_ERR_CLR: 1;
+        uint32_t GRTC_CMP4_TIMEOUT_OV_ERR_CLR: 1;
+        uint32_t GRTC_CMP5_TIMEOUT_OV_ERR_CLR: 1;
+        uint32_t GRTC_CMP6_TIMEOUT_OV_ERR_CLR: 1;
+        uint32_t GRTC_CMP7_TIMEOUT_OV_ERR_CLR: 1;
+        uint32_t GRTC_COMP_TIMEOUT_OV_ERR_CLR_RESERVED31_8: 24;
+    };
+} AON_REG_GRTC_COMP_TIMEOUT_OV_ERR_CLR_TYPE;
+
+/*0x4000_0d8c AON_REG_GRTC_COMP_TIMEOUT_OV_ERR_CLR*/
+#define AON_REG_GRTC_COMP_TIMEOUT_OV_ERR_CLR_GRTC_CMP0_TIMEOUT_OV_ERR_CLR_Pos                                            0U
+#define AON_REG_GRTC_COMP_TIMEOUT_OV_ERR_CLR_GRTC_CMP0_TIMEOUT_OV_ERR_CLR_Msk                                            (0x1UL << AON_REG_GRTC_COMP_TIMEOUT_OV_ERR_CLR_GRTC_CMP0_TIMEOUT_OV_ERR_CLR_Pos)
+
+#define AON_REG_GRTC_COMP_TIMEOUT_OV_ERR_CLR_GRTC_CMP1_TIMEOUT_OV_ERR_CLR_Pos                                            1U
+#define AON_REG_GRTC_COMP_TIMEOUT_OV_ERR_CLR_GRTC_CMP1_TIMEOUT_OV_ERR_CLR_Msk                                            (0x1UL << AON_REG_GRTC_COMP_TIMEOUT_OV_ERR_CLR_GRTC_CMP1_TIMEOUT_OV_ERR_CLR_Pos)
+
+#define AON_REG_GRTC_COMP_TIMEOUT_OV_ERR_CLR_GRTC_CMP2_TIMEOUT_OV_ERR_CLR_Pos                                            2U
+#define AON_REG_GRTC_COMP_TIMEOUT_OV_ERR_CLR_GRTC_CMP2_TIMEOUT_OV_ERR_CLR_Msk                                            (0x1UL << AON_REG_GRTC_COMP_TIMEOUT_OV_ERR_CLR_GRTC_CMP2_TIMEOUT_OV_ERR_CLR_Pos)
+
+#define AON_REG_GRTC_COMP_TIMEOUT_OV_ERR_CLR_GRTC_CMP3_TIMEOUT_OV_ERR_CLR_Pos                                            3U
+#define AON_REG_GRTC_COMP_TIMEOUT_OV_ERR_CLR_GRTC_CMP3_TIMEOUT_OV_ERR_CLR_Msk                                            (0x1UL << AON_REG_GRTC_COMP_TIMEOUT_OV_ERR_CLR_GRTC_CMP3_TIMEOUT_OV_ERR_CLR_Pos)
+
+#define AON_REG_GRTC_COMP_TIMEOUT_OV_ERR_CLR_GRTC_CMP4_TIMEOUT_OV_ERR_CLR_Pos                                            4U
+#define AON_REG_GRTC_COMP_TIMEOUT_OV_ERR_CLR_GRTC_CMP4_TIMEOUT_OV_ERR_CLR_Msk                                            (0x1UL << AON_REG_GRTC_COMP_TIMEOUT_OV_ERR_CLR_GRTC_CMP4_TIMEOUT_OV_ERR_CLR_Pos)
+
+#define AON_REG_GRTC_COMP_TIMEOUT_OV_ERR_CLR_GRTC_CMP5_TIMEOUT_OV_ERR_CLR_Pos                                            5U
+#define AON_REG_GRTC_COMP_TIMEOUT_OV_ERR_CLR_GRTC_CMP5_TIMEOUT_OV_ERR_CLR_Msk                                            (0x1UL << AON_REG_GRTC_COMP_TIMEOUT_OV_ERR_CLR_GRTC_CMP5_TIMEOUT_OV_ERR_CLR_Pos)
+
+#define AON_REG_GRTC_COMP_TIMEOUT_OV_ERR_CLR_GRTC_CMP6_TIMEOUT_OV_ERR_CLR_Pos                                            6U
+#define AON_REG_GRTC_COMP_TIMEOUT_OV_ERR_CLR_GRTC_CMP6_TIMEOUT_OV_ERR_CLR_Msk                                            (0x1UL << AON_REG_GRTC_COMP_TIMEOUT_OV_ERR_CLR_GRTC_CMP6_TIMEOUT_OV_ERR_CLR_Pos)
+
+#define AON_REG_GRTC_COMP_TIMEOUT_OV_ERR_CLR_GRTC_CMP7_TIMEOUT_OV_ERR_CLR_Pos                                            7U
+#define AON_REG_GRTC_COMP_TIMEOUT_OV_ERR_CLR_GRTC_CMP7_TIMEOUT_OV_ERR_CLR_Msk                                            (0x1UL << AON_REG_GRTC_COMP_TIMEOUT_OV_ERR_CLR_GRTC_CMP7_TIMEOUT_OV_ERR_CLR_Pos)
+
+#define AON_REG_GRTC_COMP_TIMEOUT_OV_ERR_CLR_GRTC_COMP_TIMEOUT_OV_ERR_CLR_RESERVED31_8_Pos                               8U
+#define AON_REG_GRTC_COMP_TIMEOUT_OV_ERR_CLR_GRTC_COMP_TIMEOUT_OV_ERR_CLR_RESERVED31_8_Msk                               (0xFFFFFFUL << AON_REG_GRTC_COMP_TIMEOUT_OV_ERR_CLR_GRTC_COMP_TIMEOUT_OV_ERR_CLR_RESERVED31_8_Pos)
+
+/* 0xDB4    0x4000_0db4
+    0       R/W     OSC80M_CAL_RESET_N                                          1'b1
+    1       R/W     OSC80M_CAL_SW_LIN_CAL_EN                                    1'b0
+    2       R/W     OSC80M_CAL_REG0X_DUMMY1                                     1'b0
+    3       R/W     OSC80M_CAL_TMETER_MODE                                      1'b0
+    4       R/W     OSC80M_CAL_REG0X_DUMMY0                                     1'b0
+    6:5     R/W     OSC80M_CAL_DBG_SEL                                          2'b00
+    31:7    R       RSVD                                                        25'b0
+ */
+typedef union _AON_REG0X_OSC80M_CAL_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t OSC80M_CAL_RESET_N: 1;
+        uint32_t OSC80M_CAL_SW_LIN_CAL_EN: 1;
+        uint32_t OSC80M_CAL_REG0X_DUMMY1: 1;
+        uint32_t OSC80M_CAL_TMETER_MODE: 1;
+        uint32_t OSC80M_CAL_REG0X_DUMMY0: 1;
+        uint32_t OSC80M_CAL_DBG_SEL: 2;
+        uint32_t RSVD: 25;
+    };
+} AON_REG0X_OSC80M_CAL_TYPE;
+
+/*0x4000_0db4 AON_REG0X_OSC80M_CAL*/
+#define AON_REG0X_OSC80M_CAL_OSC80M_CAL_RESET_N_Pos                                                                      0U
+#define AON_REG0X_OSC80M_CAL_OSC80M_CAL_RESET_N_Msk                                                                      (0x1UL << AON_REG0X_OSC80M_CAL_OSC80M_CAL_RESET_N_Pos)
+
+#define AON_REG0X_OSC80M_CAL_OSC80M_CAL_SW_LIN_CAL_EN_Pos                                                                1U
+#define AON_REG0X_OSC80M_CAL_OSC80M_CAL_SW_LIN_CAL_EN_Msk                                                                (0x1UL << AON_REG0X_OSC80M_CAL_OSC80M_CAL_SW_LIN_CAL_EN_Pos)
+
+#define AON_REG0X_OSC80M_CAL_OSC80M_CAL_REG0X_DUMMY1_Pos                                                                 2U
+#define AON_REG0X_OSC80M_CAL_OSC80M_CAL_REG0X_DUMMY1_Msk                                                                 (0x1UL << AON_REG0X_OSC80M_CAL_OSC80M_CAL_REG0X_DUMMY1_Pos)
+
+#define AON_REG0X_OSC80M_CAL_OSC80M_CAL_TMETER_MODE_Pos                                                                  3U
+#define AON_REG0X_OSC80M_CAL_OSC80M_CAL_TMETER_MODE_Msk                                                                  (0x1UL << AON_REG0X_OSC80M_CAL_OSC80M_CAL_TMETER_MODE_Pos)
+
+#define AON_REG0X_OSC80M_CAL_OSC80M_CAL_REG0X_DUMMY0_Pos                                                                 4U
+#define AON_REG0X_OSC80M_CAL_OSC80M_CAL_REG0X_DUMMY0_Msk                                                                 (0x1UL << AON_REG0X_OSC80M_CAL_OSC80M_CAL_REG0X_DUMMY0_Pos)
+
+#define AON_REG0X_OSC80M_CAL_OSC80M_CAL_DBG_SEL_Pos                                                                      5U
+#define AON_REG0X_OSC80M_CAL_OSC80M_CAL_DBG_SEL_Msk                                                                      (0x3UL << AON_REG0X_OSC80M_CAL_OSC80M_CAL_DBG_SEL_Pos)
+
+#define AON_REG0X_OSC80M_CAL_RSVD_Pos                                                                                    7U
+#define AON_REG0X_OSC80M_CAL_RSVD_Msk                                                                                    (0x1FFFFFFUL << AON_REG0X_OSC80M_CAL_RSVD_Pos)
+
+/* 0xDB8    0x4000_0db8
+    3:0     R/W     OSC80M_CAL_RCAL_H                                           4'h7
+    7:4     R/W     OSC80M_CAL_RCAL_SETTLE_CYC                                  4'h2
+    8       R       RSVD_1                                                      1'b0
+    12:9    R/W     OSC80M_CAL_INC_STEP                                         4'h4
+    18:13   R/W     OSC80M_CAL_KT_LIM                                           6'h30
+    22:19   R/W     OSC80M_CAL_DELTA_RCAL_H                                     4'd8
+    31:23   R       RSVD                                                        9'b0
+ */
+typedef union _AON_REG2X_OSC80M_CAL_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t OSC80M_CAL_RCAL_H: 4;
+        uint32_t OSC80M_CAL_RCAL_SETTLE_CYC: 4;
+        uint32_t RSVD_1: 1;
+        uint32_t OSC80M_CAL_INC_STEP: 4;
+        uint32_t OSC80M_CAL_KT_LIM: 6;
+        uint32_t OSC80M_CAL_DELTA_RCAL_H: 4;
+        uint32_t RSVD: 9;
+    };
+} AON_REG2X_OSC80M_CAL_TYPE;
+
+/*0x4000_0db8 AON_REG2X_OSC80M_CAL*/
+#define AON_REG2X_OSC80M_CAL_OSC80M_CAL_RCAL_H_Pos                                                                       0U
+#define AON_REG2X_OSC80M_CAL_OSC80M_CAL_RCAL_H_Msk                                                                       (0xFUL << AON_REG2X_OSC80M_CAL_OSC80M_CAL_RCAL_H_Pos)
+
+#define AON_REG2X_OSC80M_CAL_OSC80M_CAL_RCAL_SETTLE_CYC_Pos                                                              4U
+#define AON_REG2X_OSC80M_CAL_OSC80M_CAL_RCAL_SETTLE_CYC_Msk                                                              (0xFUL << AON_REG2X_OSC80M_CAL_OSC80M_CAL_RCAL_SETTLE_CYC_Pos)
+
+#define AON_REG2X_OSC80M_CAL_RSVD_1_Pos                                                                                  8U
+#define AON_REG2X_OSC80M_CAL_RSVD_1_Msk                                                                                  (0x1UL << AON_REG2X_OSC80M_CAL_RSVD_1_Pos)
+
+#define AON_REG2X_OSC80M_CAL_OSC80M_CAL_INC_STEP_Pos                                                                     9U
+#define AON_REG2X_OSC80M_CAL_OSC80M_CAL_INC_STEP_Msk                                                                     (0xFUL << AON_REG2X_OSC80M_CAL_OSC80M_CAL_INC_STEP_Pos)
+
+#define AON_REG2X_OSC80M_CAL_OSC80M_CAL_KT_LIM_Pos                                                                       13U
+#define AON_REG2X_OSC80M_CAL_OSC80M_CAL_KT_LIM_Msk                                                                       (0x3FUL << AON_REG2X_OSC80M_CAL_OSC80M_CAL_KT_LIM_Pos)
+
+#define AON_REG2X_OSC80M_CAL_OSC80M_CAL_DELTA_RCAL_H_Pos                                                                 19U
+#define AON_REG2X_OSC80M_CAL_OSC80M_CAL_DELTA_RCAL_H_Msk                                                                 (0xFUL << AON_REG2X_OSC80M_CAL_OSC80M_CAL_DELTA_RCAL_H_Pos)
+
+#define AON_REG2X_OSC80M_CAL_RSVD_Pos                                                                                    23U
+#define AON_REG2X_OSC80M_CAL_RSVD_Msk                                                                                    (0x1FFUL << AON_REG2X_OSC80M_CAL_RSVD_Pos)
+
+/* 0xDBC    0x4000_0dbc
+    10:0    R/W     OSC80M_CAL_CENTER_CNT_FREF                                  11'd256
+    17:11   R       RSVD_1                                                      7'b0
+    22:18   R/W     OSC80M_CAL_LIN_K_CNT_CYC                                    5'h7
+    31:23   R/W     RSVD                                                        9'h0
+ */
+typedef union _AON_REG4X_OSC80M_CAL_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t OSC80M_CAL_CENTER_CNT_FREF: 11;
+        uint32_t RSVD_1: 7;
+        uint32_t OSC80M_CAL_LIN_K_CNT_CYC: 5;
+        uint32_t RSVD: 9;
+    };
+} AON_REG4X_OSC80M_CAL_TYPE;
+
+/*0x4000_0dbc AON_REG4X_OSC80M_CAL*/
+#define AON_REG4X_OSC80M_CAL_OSC80M_CAL_CENTER_CNT_FREF_Pos                                                              0U
+#define AON_REG4X_OSC80M_CAL_OSC80M_CAL_CENTER_CNT_FREF_Msk                                                              (0x7FFUL << AON_REG4X_OSC80M_CAL_OSC80M_CAL_CENTER_CNT_FREF_Pos)
+
+#define AON_REG4X_OSC80M_CAL_RSVD_1_Pos                                                                                  11U
+#define AON_REG4X_OSC80M_CAL_RSVD_1_Msk                                                                                  (0x7FUL << AON_REG4X_OSC80M_CAL_RSVD_1_Pos)
+
+#define AON_REG4X_OSC80M_CAL_OSC80M_CAL_LIN_K_CNT_CYC_Pos                                                                18U
+#define AON_REG4X_OSC80M_CAL_OSC80M_CAL_LIN_K_CNT_CYC_Msk                                                                (0x1FUL << AON_REG4X_OSC80M_CAL_OSC80M_CAL_LIN_K_CNT_CYC_Pos)
+
+#define AON_REG4X_OSC80M_CAL_RSVD_Pos                                                                                    23U
+#define AON_REG4X_OSC80M_CAL_RSVD_Msk                                                                                    (0x1FFUL << AON_REG4X_OSC80M_CAL_RSVD_Pos)
+
+/* 0xDC0    0x4000_0dc0
+    6:0     R/W     OSC80M_CAL_CRITER0                                          7'd4
+    22:7    R       RSVD                                                        16'b0
+    30:23   R/W     OSC80M_CAL_RCAL_INIT                                        8'd13
+    31      R/W     OSC80M_CAL_TEST_MODE                                        1'h0
+ */
+typedef union _AON_REG6X_OSC80M_CAL_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t OSC80M_CAL_CRITER0: 7;
+        uint32_t RSVD: 16;
+        uint32_t OSC80M_CAL_RCAL_INIT: 8;
+        uint32_t OSC80M_CAL_TEST_MODE: 1;
+    };
+} AON_REG6X_OSC80M_CAL_TYPE;
+
+/*0x4000_0dc0 AON_REG6X_OSC80M_CAL*/
+#define AON_REG6X_OSC80M_CAL_OSC80M_CAL_CRITER0_Pos                                                                      0U
+#define AON_REG6X_OSC80M_CAL_OSC80M_CAL_CRITER0_Msk                                                                      (0x7FUL << AON_REG6X_OSC80M_CAL_OSC80M_CAL_CRITER0_Pos)
+
+#define AON_REG6X_OSC80M_CAL_RSVD_Pos                                                                                    7U
+#define AON_REG6X_OSC80M_CAL_RSVD_Msk                                                                                    (0xFFFFUL << AON_REG6X_OSC80M_CAL_RSVD_Pos)
+
+#define AON_REG6X_OSC80M_CAL_OSC80M_CAL_RCAL_INIT_Pos                                                                    23U
+#define AON_REG6X_OSC80M_CAL_OSC80M_CAL_RCAL_INIT_Msk                                                                    (0xFFUL << AON_REG6X_OSC80M_CAL_OSC80M_CAL_RCAL_INIT_Pos)
+
+#define AON_REG6X_OSC80M_CAL_OSC80M_CAL_TEST_MODE_Pos                                                                    31U
+#define AON_REG6X_OSC80M_CAL_OSC80M_CAL_TEST_MODE_Msk                                                                    (0x1UL << AON_REG6X_OSC80M_CAL_OSC80M_CAL_TEST_MODE_Pos)
+
+/* 0xDC4    0x4000_0dc4
+    14:0    R       OSC80M_CAL_RCAL_O                                           15'h80
+    15      R       RSVD_1                                                      1'h0
+    21:16   R       OSC80M_CAL_KT_CNT                                           6'h0
+    23:22   R       OSC80M_CAL_LOCK                                             2'h0
+    31:24   R       RSVD                                                        8'h0
+ */
+typedef union _AON_REG8X_OSC80M_CAL_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t OSC80M_CAL_RCAL_O: 15;
+        uint32_t RSVD_1: 1;
+        uint32_t OSC80M_CAL_KT_CNT: 6;
+        uint32_t OSC80M_CAL_LOCK: 2;
+        uint32_t RSVD: 8;
+    };
+} AON_REG8X_OSC80M_CAL_TYPE;
+
+/*0x4000_0dc4 AON_REG8X_OSC80M_CAL*/
+#define AON_REG8X_OSC80M_CAL_OSC80M_CAL_RCAL_O_Pos                                                                       0U
+#define AON_REG8X_OSC80M_CAL_OSC80M_CAL_RCAL_O_Msk                                                                       (0x7FFFUL << AON_REG8X_OSC80M_CAL_OSC80M_CAL_RCAL_O_Pos)
+
+#define AON_REG8X_OSC80M_CAL_RSVD_1_Pos                                                                                  15U
+#define AON_REG8X_OSC80M_CAL_RSVD_1_Msk                                                                                  (0x1UL << AON_REG8X_OSC80M_CAL_RSVD_1_Pos)
+
+#define AON_REG8X_OSC80M_CAL_OSC80M_CAL_KT_CNT_Pos                                                                       16U
+#define AON_REG8X_OSC80M_CAL_OSC80M_CAL_KT_CNT_Msk                                                                       (0x3FUL << AON_REG8X_OSC80M_CAL_OSC80M_CAL_KT_CNT_Pos)
+
+#define AON_REG8X_OSC80M_CAL_OSC80M_CAL_LOCK_Pos                                                                         22U
+#define AON_REG8X_OSC80M_CAL_OSC80M_CAL_LOCK_Msk                                                                         (0x3UL << AON_REG8X_OSC80M_CAL_OSC80M_CAL_LOCK_Pos)
+
+#define AON_REG8X_OSC80M_CAL_RSVD_Pos                                                                                    24U
+#define AON_REG8X_OSC80M_CAL_RSVD_Msk                                                                                    (0xFFUL << AON_REG8X_OSC80M_CAL_RSVD_Pos)
+
+/* 0xDC8    0x4000_0dc8
+    12:0    R       OSC80M_CAL_LIN_CNT_FREF_REP_1                               13'h0
+    25:13   R       OSC80M_CAL_LIN_CNT_FREF_REP_0                               13'h0
+    31:26   R       RSVD                                                        6'h0
+ */
+typedef union _AON_REG10X_OSC80M_CAL_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t OSC80M_CAL_LIN_CNT_FREF_REP_1: 13;
+        uint32_t OSC80M_CAL_LIN_CNT_FREF_REP_0: 13;
+        uint32_t RSVD: 6;
+    };
+} AON_REG10X_OSC80M_CAL_TYPE;
+
+/*0x4000_0dc8 AON_REG10X_OSC80M_CAL*/
+#define AON_REG10X_OSC80M_CAL_OSC80M_CAL_LIN_CNT_FREF_REP_1_Pos                                                          0U
+#define AON_REG10X_OSC80M_CAL_OSC80M_CAL_LIN_CNT_FREF_REP_1_Msk                                                          (0x1FFFUL << AON_REG10X_OSC80M_CAL_OSC80M_CAL_LIN_CNT_FREF_REP_1_Pos)
+
+#define AON_REG10X_OSC80M_CAL_OSC80M_CAL_LIN_CNT_FREF_REP_0_Pos                                                          13U
+#define AON_REG10X_OSC80M_CAL_OSC80M_CAL_LIN_CNT_FREF_REP_0_Msk                                                          (0x1FFFUL << AON_REG10X_OSC80M_CAL_OSC80M_CAL_LIN_CNT_FREF_REP_0_Pos)
+
+#define AON_REG10X_OSC80M_CAL_RSVD_Pos                                                                                   26U
+#define AON_REG10X_OSC80M_CAL_RSVD_Msk                                                                                   (0x3FUL << AON_REG10X_OSC80M_CAL_RSVD_Pos)
+
+/* 0xDCC    0x4000_0dcc
+    0       R/W     OSC80M_CAL_RAP_MODE                                         1'h0
+    31:1    R       RSVD                                                        31'b0
+ */
+typedef union _AON_REG_OSC80M_CAL_RAP_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t OSC80M_CAL_RAP_MODE: 1;
+        uint32_t RSVD: 31;
+    };
+} AON_REG_OSC80M_CAL_RAP_TYPE;
+
+/*0x4000_0dcc AON_REG_OSC80M_CAL_RAP*/
+#define AON_REG_OSC80M_CAL_RAP_OSC80M_CAL_RAP_MODE_Pos                                                                   0U
+#define AON_REG_OSC80M_CAL_RAP_OSC80M_CAL_RAP_MODE_Msk                                                                   (0x1UL << AON_REG_OSC80M_CAL_RAP_OSC80M_CAL_RAP_MODE_Pos)
+
+#define AON_REG_OSC80M_CAL_RAP_RSVD_Pos                                                                                  1U
+#define AON_REG_OSC80M_CAL_RAP_RSVD_Msk                                                                                  (0x7FFFFFFFUL << AON_REG_OSC80M_CAL_RAP_RSVD_Pos)
+
+/* 0xDD0    0x4000_0dd0
+    0       R/W     OSC80M_CAL_CLK_QACTIVE_MAN_DATA                             1'h0
+    1       R/W     OSC80M_CAL_CLK_QACTIVE_MAN_EN                               1'h0
+    31:2    R       RSVD                                                        30'b0
+ */
+typedef union _AON_REG_OSC80M_CAL_QCH_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t OSC80M_CAL_CLK_QACTIVE_MAN_DATA: 1;
+        uint32_t OSC80M_CAL_CLK_QACTIVE_MAN_EN: 1;
+        uint32_t RSVD: 30;
+    };
+} AON_REG_OSC80M_CAL_QCH_TYPE;
+
+/*0x4000_0dd0 AON_REG_OSC80M_CAL_QCH*/
+#define AON_REG_OSC80M_CAL_QCH_OSC80M_CAL_CLK_QACTIVE_MAN_DATA_Pos                                                       0U
+#define AON_REG_OSC80M_CAL_QCH_OSC80M_CAL_CLK_QACTIVE_MAN_DATA_Msk                                                       (0x1UL << AON_REG_OSC80M_CAL_QCH_OSC80M_CAL_CLK_QACTIVE_MAN_DATA_Pos)
+
+#define AON_REG_OSC80M_CAL_QCH_OSC80M_CAL_CLK_QACTIVE_MAN_EN_Pos                                                         1U
+#define AON_REG_OSC80M_CAL_QCH_OSC80M_CAL_CLK_QACTIVE_MAN_EN_Msk                                                         (0x1UL << AON_REG_OSC80M_CAL_QCH_OSC80M_CAL_CLK_QACTIVE_MAN_EN_Pos)
+
+#define AON_REG_OSC80M_CAL_QCH_RSVD_Pos                                                                                  2U
+#define AON_REG_OSC80M_CAL_QCH_RSVD_Msk                                                                                  (0x3FFFFFFFUL << AON_REG_OSC80M_CAL_QCH_RSVD_Pos)
+
+/* 0xDF0    0x4000_0df0
+    0       R/W     OSC10M_CAL_RESET_N                                          1'b1
+    1       R/W     OSC10M_CAL_SW_LIN_CAL_EN                                    1'b0
+    2       R/W     OSC10M_CAL_REG0X_DUMMY1                                     1'b0
+    3       R/W     OSC10M_CAL_TMETER_MODE                                      1'b0
+    4       R/W     OSC10M_CAL_REG0X_DUMMY0                                     1'b0
+    6:5     R/W     OSC10M_CAL_DBG_SEL                                          2'b00
+    31:7    R       RSVD                                                        25'b0
+ */
+typedef union _AON_REG0X_OSC10M_CAL_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t OSC10M_CAL_RESET_N: 1;
+        uint32_t OSC10M_CAL_SW_LIN_CAL_EN: 1;
+        uint32_t OSC10M_CAL_REG0X_DUMMY1: 1;
+        uint32_t OSC10M_CAL_TMETER_MODE: 1;
+        uint32_t OSC10M_CAL_REG0X_DUMMY0: 1;
+        uint32_t OSC10M_CAL_DBG_SEL: 2;
+        uint32_t RSVD: 25;
+    };
+} AON_REG0X_OSC10M_CAL_TYPE;
+
+/*0x4000_0df0 AON_REG0X_OSC10M_CAL*/
+#define AON_REG0X_OSC10M_CAL_OSC10M_CAL_RESET_N_Pos                                                                      0U
+#define AON_REG0X_OSC10M_CAL_OSC10M_CAL_RESET_N_Msk                                                                      (0x1UL << AON_REG0X_OSC10M_CAL_OSC10M_CAL_RESET_N_Pos)
+
+#define AON_REG0X_OSC10M_CAL_OSC10M_CAL_SW_LIN_CAL_EN_Pos                                                                1U
+#define AON_REG0X_OSC10M_CAL_OSC10M_CAL_SW_LIN_CAL_EN_Msk                                                                (0x1UL << AON_REG0X_OSC10M_CAL_OSC10M_CAL_SW_LIN_CAL_EN_Pos)
+
+#define AON_REG0X_OSC10M_CAL_OSC10M_CAL_REG0X_DUMMY1_Pos                                                                 2U
+#define AON_REG0X_OSC10M_CAL_OSC10M_CAL_REG0X_DUMMY1_Msk                                                                 (0x1UL << AON_REG0X_OSC10M_CAL_OSC10M_CAL_REG0X_DUMMY1_Pos)
+
+#define AON_REG0X_OSC10M_CAL_OSC10M_CAL_TMETER_MODE_Pos                                                                  3U
+#define AON_REG0X_OSC10M_CAL_OSC10M_CAL_TMETER_MODE_Msk                                                                  (0x1UL << AON_REG0X_OSC10M_CAL_OSC10M_CAL_TMETER_MODE_Pos)
+
+#define AON_REG0X_OSC10M_CAL_OSC10M_CAL_REG0X_DUMMY0_Pos                                                                 4U
+#define AON_REG0X_OSC10M_CAL_OSC10M_CAL_REG0X_DUMMY0_Msk                                                                 (0x1UL << AON_REG0X_OSC10M_CAL_OSC10M_CAL_REG0X_DUMMY0_Pos)
+
+#define AON_REG0X_OSC10M_CAL_OSC10M_CAL_DBG_SEL_Pos                                                                      5U
+#define AON_REG0X_OSC10M_CAL_OSC10M_CAL_DBG_SEL_Msk                                                                      (0x3UL << AON_REG0X_OSC10M_CAL_OSC10M_CAL_DBG_SEL_Pos)
+
+#define AON_REG0X_OSC10M_CAL_RSVD_Pos                                                                                    7U
+#define AON_REG0X_OSC10M_CAL_RSVD_Msk                                                                                    (0x1FFFFFFUL << AON_REG0X_OSC10M_CAL_RSVD_Pos)
+
+/* 0xDF4    0x4000_0df4
+    3:0     R/W     OSC10M_CAL_RCAL_H                                           4'h7
+    7:4     R/W     OSC10M_CAL_RCAL_SETTLE_CYC                                  4'h2
+    8       R       RSVD_1                                                      1'b0
+    12:9    R/W     OSC10M_CAL_INC_STEP                                         4'h4
+    18:13   R/W     OSC10M_CAL_KT_LIM                                           6'h30
+    22:19   R/W     OSC10M_CAL_DELTA_RCAL_H                                     4'd8
+    31:23   R       RSVD                                                        9'b0
+ */
+typedef union _AON_REG2X_OSC10M_CAL_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t OSC10M_CAL_RCAL_H: 4;
+        uint32_t OSC10M_CAL_RCAL_SETTLE_CYC: 4;
+        uint32_t RSVD_1: 1;
+        uint32_t OSC10M_CAL_INC_STEP: 4;
+        uint32_t OSC10M_CAL_KT_LIM: 6;
+        uint32_t OSC10M_CAL_DELTA_RCAL_H: 4;
+        uint32_t RSVD: 9;
+    };
+} AON_REG2X_OSC10M_CAL_TYPE;
+
+/*0x4000_0df4 AON_REG2X_OSC10M_CAL*/
+#define AON_REG2X_OSC10M_CAL_OSC10M_CAL_RCAL_H_Pos                                                                       0U
+#define AON_REG2X_OSC10M_CAL_OSC10M_CAL_RCAL_H_Msk                                                                       (0xFUL << AON_REG2X_OSC10M_CAL_OSC10M_CAL_RCAL_H_Pos)
+
+#define AON_REG2X_OSC10M_CAL_OSC10M_CAL_RCAL_SETTLE_CYC_Pos                                                              4U
+#define AON_REG2X_OSC10M_CAL_OSC10M_CAL_RCAL_SETTLE_CYC_Msk                                                              (0xFUL << AON_REG2X_OSC10M_CAL_OSC10M_CAL_RCAL_SETTLE_CYC_Pos)
+
+#define AON_REG2X_OSC10M_CAL_RSVD_1_Pos                                                                                  8U
+#define AON_REG2X_OSC10M_CAL_RSVD_1_Msk                                                                                  (0x1UL << AON_REG2X_OSC10M_CAL_RSVD_1_Pos)
+
+#define AON_REG2X_OSC10M_CAL_OSC10M_CAL_INC_STEP_Pos                                                                     9U
+#define AON_REG2X_OSC10M_CAL_OSC10M_CAL_INC_STEP_Msk                                                                     (0xFUL << AON_REG2X_OSC10M_CAL_OSC10M_CAL_INC_STEP_Pos)
+
+#define AON_REG2X_OSC10M_CAL_OSC10M_CAL_KT_LIM_Pos                                                                       13U
+#define AON_REG2X_OSC10M_CAL_OSC10M_CAL_KT_LIM_Msk                                                                       (0x3FUL << AON_REG2X_OSC10M_CAL_OSC10M_CAL_KT_LIM_Pos)
+
+#define AON_REG2X_OSC10M_CAL_OSC10M_CAL_DELTA_RCAL_H_Pos                                                                 19U
+#define AON_REG2X_OSC10M_CAL_OSC10M_CAL_DELTA_RCAL_H_Msk                                                                 (0xFUL << AON_REG2X_OSC10M_CAL_OSC10M_CAL_DELTA_RCAL_H_Pos)
+
+#define AON_REG2X_OSC10M_CAL_RSVD_Pos                                                                                    23U
+#define AON_REG2X_OSC10M_CAL_RSVD_Msk                                                                                    (0x1FFUL << AON_REG2X_OSC10M_CAL_RSVD_Pos)
+
+/* 0xDF8    0x4000_0df8
+    10:0    R/W     OSC10M_CAL_CENTER_CNT_FREF                                  11'd128
+    17:11   R       RSVD_1                                                      7'b0
+    22:18   R/W     OSC10M_CAL_LIN_K_CNT_CYC                                    5'h3
+    31:23   R/W     RSVD                                                        9'h0
+ */
+typedef union _AON_REG4X_OSC10M_CAL_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t OSC10M_CAL_CENTER_CNT_FREF: 11;
+        uint32_t RSVD_1: 7;
+        uint32_t OSC10M_CAL_LIN_K_CNT_CYC: 5;
+        uint32_t RSVD: 9;
+    };
+} AON_REG4X_OSC10M_CAL_TYPE;
+
+/*0x4000_0df8 AON_REG4X_OSC10M_CAL*/
+#define AON_REG4X_OSC10M_CAL_OSC10M_CAL_CENTER_CNT_FREF_Pos                                                              0U
+#define AON_REG4X_OSC10M_CAL_OSC10M_CAL_CENTER_CNT_FREF_Msk                                                              (0x7FFUL << AON_REG4X_OSC10M_CAL_OSC10M_CAL_CENTER_CNT_FREF_Pos)
+
+#define AON_REG4X_OSC10M_CAL_RSVD_1_Pos                                                                                  11U
+#define AON_REG4X_OSC10M_CAL_RSVD_1_Msk                                                                                  (0x7FUL << AON_REG4X_OSC10M_CAL_RSVD_1_Pos)
+
+#define AON_REG4X_OSC10M_CAL_OSC10M_CAL_LIN_K_CNT_CYC_Pos                                                                18U
+#define AON_REG4X_OSC10M_CAL_OSC10M_CAL_LIN_K_CNT_CYC_Msk                                                                (0x1FUL << AON_REG4X_OSC10M_CAL_OSC10M_CAL_LIN_K_CNT_CYC_Pos)
+
+#define AON_REG4X_OSC10M_CAL_RSVD_Pos                                                                                    23U
+#define AON_REG4X_OSC10M_CAL_RSVD_Msk                                                                                    (0x1FFUL << AON_REG4X_OSC10M_CAL_RSVD_Pos)
+
+/* 0xDFC    0x4000_0dfc
+    6:0     R/W     OSC10M_CAL_CRITER0                                          7'd6
+    22:7    R       RSVD                                                        16'b0
+    30:23   R/W     OSC10M_CAL_RCAL_INIT                                        8'd24
+    31      R/W     OSC10M_CAL_TEST_MODE                                        1'h0
+ */
+typedef union _AON_REG6X_OSC10M_CAL_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t OSC10M_CAL_CRITER0: 7;
+        uint32_t RSVD: 16;
+        uint32_t OSC10M_CAL_RCAL_INIT: 8;
+        uint32_t OSC10M_CAL_TEST_MODE: 1;
+    };
+} AON_REG6X_OSC10M_CAL_TYPE;
+
+/*0x4000_0dfc AON_REG6X_OSC10M_CAL*/
+#define AON_REG6X_OSC10M_CAL_OSC10M_CAL_CRITER0_Pos                                                                      0U
+#define AON_REG6X_OSC10M_CAL_OSC10M_CAL_CRITER0_Msk                                                                      (0x7FUL << AON_REG6X_OSC10M_CAL_OSC10M_CAL_CRITER0_Pos)
+
+#define AON_REG6X_OSC10M_CAL_RSVD_Pos                                                                                    7U
+#define AON_REG6X_OSC10M_CAL_RSVD_Msk                                                                                    (0xFFFFUL << AON_REG6X_OSC10M_CAL_RSVD_Pos)
+
+#define AON_REG6X_OSC10M_CAL_OSC10M_CAL_RCAL_INIT_Pos                                                                    23U
+#define AON_REG6X_OSC10M_CAL_OSC10M_CAL_RCAL_INIT_Msk                                                                    (0xFFUL << AON_REG6X_OSC10M_CAL_OSC10M_CAL_RCAL_INIT_Pos)
+
+#define AON_REG6X_OSC10M_CAL_OSC10M_CAL_TEST_MODE_Pos                                                                    31U
+#define AON_REG6X_OSC10M_CAL_OSC10M_CAL_TEST_MODE_Msk                                                                    (0x1UL << AON_REG6X_OSC10M_CAL_OSC10M_CAL_TEST_MODE_Pos)
+
+/* 0xE00    0x4000_0e00
+    14:0    R       OSC10M_CAL_RCAL_O                                           15'h80
+    15      R       RSVD_1                                                      1'h0
+    21:16   R       OSC10M_CAL_KT_CNT                                           6'h0
+    23:22   R       OSC10M_CAL_LOCK                                             2'h0
+    31:24   R       RSVD                                                        8'h0
+ */
+typedef union _AON_REG8X_OSC10M_CAL_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t OSC10M_CAL_RCAL_O: 15;
+        uint32_t RSVD_1: 1;
+        uint32_t OSC10M_CAL_KT_CNT: 6;
+        uint32_t OSC10M_CAL_LOCK: 2;
+        uint32_t RSVD: 8;
+    };
+} AON_REG8X_OSC10M_CAL_TYPE;
+
+/*0x4000_0e00 AON_REG8X_OSC10M_CAL*/
+#define AON_REG8X_OSC10M_CAL_OSC10M_CAL_RCAL_O_Pos                                                                       0U
+#define AON_REG8X_OSC10M_CAL_OSC10M_CAL_RCAL_O_Msk                                                                       (0x7FFFUL << AON_REG8X_OSC10M_CAL_OSC10M_CAL_RCAL_O_Pos)
+
+#define AON_REG8X_OSC10M_CAL_RSVD_1_Pos                                                                                  15U
+#define AON_REG8X_OSC10M_CAL_RSVD_1_Msk                                                                                  (0x1UL << AON_REG8X_OSC10M_CAL_RSVD_1_Pos)
+
+#define AON_REG8X_OSC10M_CAL_OSC10M_CAL_KT_CNT_Pos                                                                       16U
+#define AON_REG8X_OSC10M_CAL_OSC10M_CAL_KT_CNT_Msk                                                                       (0x3FUL << AON_REG8X_OSC10M_CAL_OSC10M_CAL_KT_CNT_Pos)
+
+#define AON_REG8X_OSC10M_CAL_OSC10M_CAL_LOCK_Pos                                                                         22U
+#define AON_REG8X_OSC10M_CAL_OSC10M_CAL_LOCK_Msk                                                                         (0x3UL << AON_REG8X_OSC10M_CAL_OSC10M_CAL_LOCK_Pos)
+
+#define AON_REG8X_OSC10M_CAL_RSVD_Pos                                                                                    24U
+#define AON_REG8X_OSC10M_CAL_RSVD_Msk                                                                                    (0xFFUL << AON_REG8X_OSC10M_CAL_RSVD_Pos)
+
+/* 0xE04    0x4000_0e04
+    12:0    R       OSC10M_CAL_LIN_CNT_FREF_REP_1                               13'h0
+    25:13   R       OSC10M_CAL_LIN_CNT_FREF_REP_0                               13'h0
+    31:26   R       RSVD                                                        6'h0
+ */
+typedef union _AON_REG10X_OSC10M_CAL_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t OSC10M_CAL_LIN_CNT_FREF_REP_1: 13;
+        uint32_t OSC10M_CAL_LIN_CNT_FREF_REP_0: 13;
+        uint32_t RSVD: 6;
+    };
+} AON_REG10X_OSC10M_CAL_TYPE;
+
+/*0x4000_0e04 AON_REG10X_OSC10M_CAL*/
+#define AON_REG10X_OSC10M_CAL_OSC10M_CAL_LIN_CNT_FREF_REP_1_Pos                                                          0U
+#define AON_REG10X_OSC10M_CAL_OSC10M_CAL_LIN_CNT_FREF_REP_1_Msk                                                          (0x1FFFUL << AON_REG10X_OSC10M_CAL_OSC10M_CAL_LIN_CNT_FREF_REP_1_Pos)
+
+#define AON_REG10X_OSC10M_CAL_OSC10M_CAL_LIN_CNT_FREF_REP_0_Pos                                                          13U
+#define AON_REG10X_OSC10M_CAL_OSC10M_CAL_LIN_CNT_FREF_REP_0_Msk                                                          (0x1FFFUL << AON_REG10X_OSC10M_CAL_OSC10M_CAL_LIN_CNT_FREF_REP_0_Pos)
+
+#define AON_REG10X_OSC10M_CAL_RSVD_Pos                                                                                   26U
+#define AON_REG10X_OSC10M_CAL_RSVD_Msk                                                                                   (0x3FUL << AON_REG10X_OSC10M_CAL_RSVD_Pos)
+
+/* 0xE08    0x4000_0e08
+    0       R/W     OSC10M_CAL_RAP_MODE                                         1'h0
+    31:1    R       RSVD                                                        31'b0
+ */
+typedef union _AON_REG_OSC10M_CAL_RAP_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t OSC10M_CAL_RAP_MODE: 1;
+        uint32_t RSVD: 31;
+    };
+} AON_REG_OSC10M_CAL_RAP_TYPE;
+
+/*0x4000_0e08 AON_REG_OSC10M_CAL_RAP*/
+#define AON_REG_OSC10M_CAL_RAP_OSC10M_CAL_RAP_MODE_Pos                                                                   0U
+#define AON_REG_OSC10M_CAL_RAP_OSC10M_CAL_RAP_MODE_Msk                                                                   (0x1UL << AON_REG_OSC10M_CAL_RAP_OSC10M_CAL_RAP_MODE_Pos)
+
+#define AON_REG_OSC10M_CAL_RAP_RSVD_Pos                                                                                  1U
+#define AON_REG_OSC10M_CAL_RAP_RSVD_Msk                                                                                  (0x7FFFFFFFUL << AON_REG_OSC10M_CAL_RAP_RSVD_Pos)
+
+/* 0xE0C    0x4000_0e0c
+    0       R/W     OSC10M_CAL_CLK_QACTIVE_MAN_DATA                             1'h0
+    1       R/W     OSC10M_CAL_CLK_QACTIVE_MAN_EN                               1'h0
+    31:2    R       RSVD                                                        30'b0
+ */
+typedef union _AON_REG_OSC10M_CAL_QCH_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t OSC10M_CAL_CLK_QACTIVE_MAN_DATA: 1;
+        uint32_t OSC10M_CAL_CLK_QACTIVE_MAN_EN: 1;
+        uint32_t RSVD: 30;
+    };
+} AON_REG_OSC10M_CAL_QCH_TYPE;
+
+/*0x4000_0e0c AON_REG_OSC10M_CAL_QCH*/
+#define AON_REG_OSC10M_CAL_QCH_OSC10M_CAL_CLK_QACTIVE_MAN_DATA_Pos                                                       0U
+#define AON_REG_OSC10M_CAL_QCH_OSC10M_CAL_CLK_QACTIVE_MAN_DATA_Msk                                                       (0x1UL << AON_REG_OSC10M_CAL_QCH_OSC10M_CAL_CLK_QACTIVE_MAN_DATA_Pos)
+
+#define AON_REG_OSC10M_CAL_QCH_OSC10M_CAL_CLK_QACTIVE_MAN_EN_Pos                                                         1U
+#define AON_REG_OSC10M_CAL_QCH_OSC10M_CAL_CLK_QACTIVE_MAN_EN_Msk                                                         (0x1UL << AON_REG_OSC10M_CAL_QCH_OSC10M_CAL_CLK_QACTIVE_MAN_EN_Pos)
+
+#define AON_REG_OSC10M_CAL_QCH_RSVD_Pos                                                                                  2U
+#define AON_REG_OSC10M_CAL_QCH_RSVD_Msk                                                                                  (0x3FFFFFFFUL << AON_REG_OSC10M_CAL_QCH_RSVD_Pos)
+
+/* 0xE2C    0x4000_0e2c
+    5:0     R/W     DEB_MUX_SEL0                                                6'h3f
+    7:6     R       RESERVED10                                                  2'b0
+    13:8    R/W     DEB_MUX_SEL1                                                6'h3f
+    15:14   R       RESERVED8                                                   2'b0
+    21:16   R/W     DEB_MUX_SEL2                                                6'h3f
+    23:22   R       RESERVED6                                                   2'b0
+    29:24   R/W     DEB_MUX_SEL3                                                6'h3f
+    31:30   R       RESERVED4                                                   2'b0
+ */
+typedef union _AON_REG_DEB_MUX_SEL_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t DEB_MUX_SEL0: 6;
+        uint32_t RESERVED10: 2;
+        uint32_t DEB_MUX_SEL1: 6;
+        uint32_t RESERVED8: 2;
+        uint32_t DEB_MUX_SEL2: 6;
+        uint32_t RESERVED6: 2;
+        uint32_t DEB_MUX_SEL3: 6;
+        uint32_t RESERVED4: 2;
+    };
+} AON_REG_DEB_MUX_SEL_TYPE;
+
+/*0x4000_0e2c AON_REG_DEB_MUX_SEL*/
+#define AON_REG_DEB_MUX_SEL_DEB_MUX_SEL0_Pos                                                                             0U
+#define AON_REG_DEB_MUX_SEL_DEB_MUX_SEL0_Msk                                                                             (0x3FUL << AON_REG_DEB_MUX_SEL_DEB_MUX_SEL0_Pos)
+
+#define AON_REG_DEB_MUX_SEL_RESERVED10_Pos                                                                               6U
+#define AON_REG_DEB_MUX_SEL_RESERVED10_Msk                                                                               (0x3UL << AON_REG_DEB_MUX_SEL_RESERVED10_Pos)
+
+#define AON_REG_DEB_MUX_SEL_DEB_MUX_SEL1_Pos                                                                             8U
+#define AON_REG_DEB_MUX_SEL_DEB_MUX_SEL1_Msk                                                                             (0x3FUL << AON_REG_DEB_MUX_SEL_DEB_MUX_SEL1_Pos)
+
+#define AON_REG_DEB_MUX_SEL_RESERVED8_Pos                                                                                14U
+#define AON_REG_DEB_MUX_SEL_RESERVED8_Msk                                                                                (0x3UL << AON_REG_DEB_MUX_SEL_RESERVED8_Pos)
+
+#define AON_REG_DEB_MUX_SEL_DEB_MUX_SEL2_Pos                                                                             16U
+#define AON_REG_DEB_MUX_SEL_DEB_MUX_SEL2_Msk                                                                             (0x3FUL << AON_REG_DEB_MUX_SEL_DEB_MUX_SEL2_Pos)
+
+#define AON_REG_DEB_MUX_SEL_RESERVED6_Pos                                                                                22U
+#define AON_REG_DEB_MUX_SEL_RESERVED6_Msk                                                                                (0x3UL << AON_REG_DEB_MUX_SEL_RESERVED6_Pos)
+
+#define AON_REG_DEB_MUX_SEL_DEB_MUX_SEL3_Pos                                                                             24U
+#define AON_REG_DEB_MUX_SEL_DEB_MUX_SEL3_Msk                                                                             (0x3FUL << AON_REG_DEB_MUX_SEL_DEB_MUX_SEL3_Pos)
+
+#define AON_REG_DEB_MUX_SEL_RESERVED4_Pos                                                                                30U
+#define AON_REG_DEB_MUX_SEL_RESERVED4_Msk                                                                                (0x3UL << AON_REG_DEB_MUX_SEL_RESERVED4_Pos)
+
+/* 0xE30    0x4000_0e30
+    3:0     R       RESERVED20                                                  4'h0
+    11:4    R/W     DEB_CNT_0_CNT_LIMIT                                         8'h0
+    14:12   R/W     DEB_CNT_0_CLK_DIV                                           3'h0
+    15      R/W     DEB_CNT_0_EN                                                1'b0
+    19:16   R       RESERVED16                                                  4'h0
+    27:20   R/W     DEB_CNT_1_CNT_LIMIT                                         8'h0
+    30:28   R/W     DEB_CNT_1_CLK_DIV                                           3'h0
+    31      R/W     DEB_CNT_1_EN                                                1'b0
+ */
+typedef union _AON_REG_DEB_CNT_1_0_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED20: 4;
+        uint32_t DEB_CNT_0_CNT_LIMIT: 8;
+        uint32_t DEB_CNT_0_CLK_DIV: 3;
+        uint32_t DEB_CNT_0_EN: 1;
+        uint32_t RESERVED16: 4;
+        uint32_t DEB_CNT_1_CNT_LIMIT: 8;
+        uint32_t DEB_CNT_1_CLK_DIV: 3;
+        uint32_t DEB_CNT_1_EN: 1;
+    };
+} AON_REG_DEB_CNT_1_0_TYPE;
+
+/*0x4000_0e30 AON_REG_DEB_CNT_1_0*/
+#define AON_REG_DEB_CNT_1_0_RESERVED20_Pos                                                                               0U
+#define AON_REG_DEB_CNT_1_0_RESERVED20_Msk                                                                               (0xFUL << AON_REG_DEB_CNT_1_0_RESERVED20_Pos)
+
+#define AON_REG_DEB_CNT_1_0_DEB_CNT_0_CNT_LIMIT_Pos                                                                      4U
+#define AON_REG_DEB_CNT_1_0_DEB_CNT_0_CNT_LIMIT_Msk                                                                      (0xFFUL << AON_REG_DEB_CNT_1_0_DEB_CNT_0_CNT_LIMIT_Pos)
+
+#define AON_REG_DEB_CNT_1_0_DEB_CNT_0_CLK_DIV_Pos                                                                        12U
+#define AON_REG_DEB_CNT_1_0_DEB_CNT_0_CLK_DIV_Msk                                                                        (0x7UL << AON_REG_DEB_CNT_1_0_DEB_CNT_0_CLK_DIV_Pos)
+
+#define AON_REG_DEB_CNT_1_0_DEB_CNT_0_EN_Pos                                                                             15U
+#define AON_REG_DEB_CNT_1_0_DEB_CNT_0_EN_Msk                                                                             (0x1UL << AON_REG_DEB_CNT_1_0_DEB_CNT_0_EN_Pos)
+
+#define AON_REG_DEB_CNT_1_0_RESERVED16_Pos                                                                               16U
+#define AON_REG_DEB_CNT_1_0_RESERVED16_Msk                                                                               (0xFUL << AON_REG_DEB_CNT_1_0_RESERVED16_Pos)
+
+#define AON_REG_DEB_CNT_1_0_DEB_CNT_1_CNT_LIMIT_Pos                                                                      20U
+#define AON_REG_DEB_CNT_1_0_DEB_CNT_1_CNT_LIMIT_Msk                                                                      (0xFFUL << AON_REG_DEB_CNT_1_0_DEB_CNT_1_CNT_LIMIT_Pos)
+
+#define AON_REG_DEB_CNT_1_0_DEB_CNT_1_CLK_DIV_Pos                                                                        28U
+#define AON_REG_DEB_CNT_1_0_DEB_CNT_1_CLK_DIV_Msk                                                                        (0x7UL << AON_REG_DEB_CNT_1_0_DEB_CNT_1_CLK_DIV_Pos)
+
+#define AON_REG_DEB_CNT_1_0_DEB_CNT_1_EN_Pos                                                                             31U
+#define AON_REG_DEB_CNT_1_0_DEB_CNT_1_EN_Msk                                                                             (0x1UL << AON_REG_DEB_CNT_1_0_DEB_CNT_1_EN_Pos)
+
+/* 0xE34    0x4000_0e34
+    3:0     R       RESERVED29                                                  4'h0
+    11:4    R/W     DEB_CNT_2_CNT_LIMIT                                         8'h0
+    14:12   R/W     DEB_CNT_2_CLK_DIV                                           3'h0
+    15      R/W     DEB_CNT_2_EN                                                1'b0
+    19:16   R       RESERVED25                                                  4'h0
+    27:20   R/W     DEB_CNT_3_CNT_LIMIT                                         8'h0
+    30:28   R/W     DEB_CNT_3_CLK_DIV                                           3'h0
+    31      R/W     DEB_CNT_3_EN                                                1'b0
+ */
+typedef union _AON_REG_DEB_CNT_3_2_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED29: 4;
+        uint32_t DEB_CNT_2_CNT_LIMIT: 8;
+        uint32_t DEB_CNT_2_CLK_DIV: 3;
+        uint32_t DEB_CNT_2_EN: 1;
+        uint32_t RESERVED25: 4;
+        uint32_t DEB_CNT_3_CNT_LIMIT: 8;
+        uint32_t DEB_CNT_3_CLK_DIV: 3;
+        uint32_t DEB_CNT_3_EN: 1;
+    };
+} AON_REG_DEB_CNT_3_2_TYPE;
+
+/*0x4000_0e34 AON_REG_DEB_CNT_3_2*/
+#define AON_REG_DEB_CNT_3_2_RESERVED29_Pos                                                                               0U
+#define AON_REG_DEB_CNT_3_2_RESERVED29_Msk                                                                               (0xFUL << AON_REG_DEB_CNT_3_2_RESERVED29_Pos)
+
+#define AON_REG_DEB_CNT_3_2_DEB_CNT_2_CNT_LIMIT_Pos                                                                      4U
+#define AON_REG_DEB_CNT_3_2_DEB_CNT_2_CNT_LIMIT_Msk                                                                      (0xFFUL << AON_REG_DEB_CNT_3_2_DEB_CNT_2_CNT_LIMIT_Pos)
+
+#define AON_REG_DEB_CNT_3_2_DEB_CNT_2_CLK_DIV_Pos                                                                        12U
+#define AON_REG_DEB_CNT_3_2_DEB_CNT_2_CLK_DIV_Msk                                                                        (0x7UL << AON_REG_DEB_CNT_3_2_DEB_CNT_2_CLK_DIV_Pos)
+
+#define AON_REG_DEB_CNT_3_2_DEB_CNT_2_EN_Pos                                                                             15U
+#define AON_REG_DEB_CNT_3_2_DEB_CNT_2_EN_Msk                                                                             (0x1UL << AON_REG_DEB_CNT_3_2_DEB_CNT_2_EN_Pos)
+
+#define AON_REG_DEB_CNT_3_2_RESERVED25_Pos                                                                               16U
+#define AON_REG_DEB_CNT_3_2_RESERVED25_Msk                                                                               (0xFUL << AON_REG_DEB_CNT_3_2_RESERVED25_Pos)
+
+#define AON_REG_DEB_CNT_3_2_DEB_CNT_3_CNT_LIMIT_Pos                                                                      20U
+#define AON_REG_DEB_CNT_3_2_DEB_CNT_3_CNT_LIMIT_Msk                                                                      (0xFFUL << AON_REG_DEB_CNT_3_2_DEB_CNT_3_CNT_LIMIT_Pos)
+
+#define AON_REG_DEB_CNT_3_2_DEB_CNT_3_CLK_DIV_Pos                                                                        28U
+#define AON_REG_DEB_CNT_3_2_DEB_CNT_3_CLK_DIV_Msk                                                                        (0x7UL << AON_REG_DEB_CNT_3_2_DEB_CNT_3_CLK_DIV_Pos)
+
+#define AON_REG_DEB_CNT_3_2_DEB_CNT_3_EN_Pos                                                                             31U
+#define AON_REG_DEB_CNT_3_2_DEB_CNT_3_EN_Msk                                                                             (0x1UL << AON_REG_DEB_CNT_3_2_DEB_CNT_3_EN_Pos)
+
+/* 0xE38    0x4000_0e38
+    3:0     R       RESERVED35                                                  4'h0
+    11:4    R/W     DEB_CNT_4_CNT_LIMIT                                         8'h0
+    14:12   R/W     DEB_CNT_4_CLK_DIV                                           3'h0
+    15      R/W     DEB_CNT_4_EN                                                1'b0
+    31:16   R       RESERVED31                                                  16'b0
+ */
+typedef union _AON_REG_DEB_CNT_4_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED35: 4;
+        uint32_t DEB_CNT_4_CNT_LIMIT: 8;
+        uint32_t DEB_CNT_4_CLK_DIV: 3;
+        uint32_t DEB_CNT_4_EN: 1;
+        uint32_t RESERVED31: 16;
+    };
+} AON_REG_DEB_CNT_4_TYPE;
+
+/*0x4000_0e38 AON_REG_DEB_CNT_4*/
+#define AON_REG_DEB_CNT_4_RESERVED35_Pos                                                                                 0U
+#define AON_REG_DEB_CNT_4_RESERVED35_Msk                                                                                 (0xFUL << AON_REG_DEB_CNT_4_RESERVED35_Pos)
+
+#define AON_REG_DEB_CNT_4_DEB_CNT_4_CNT_LIMIT_Pos                                                                        4U
+#define AON_REG_DEB_CNT_4_DEB_CNT_4_CNT_LIMIT_Msk                                                                        (0xFFUL << AON_REG_DEB_CNT_4_DEB_CNT_4_CNT_LIMIT_Pos)
+
+#define AON_REG_DEB_CNT_4_DEB_CNT_4_CLK_DIV_Pos                                                                          12U
+#define AON_REG_DEB_CNT_4_DEB_CNT_4_CLK_DIV_Msk                                                                          (0x7UL << AON_REG_DEB_CNT_4_DEB_CNT_4_CLK_DIV_Pos)
+
+#define AON_REG_DEB_CNT_4_DEB_CNT_4_EN_Pos                                                                               15U
+#define AON_REG_DEB_CNT_4_DEB_CNT_4_EN_Msk                                                                               (0x1UL << AON_REG_DEB_CNT_4_DEB_CNT_4_EN_Pos)
+
+#define AON_REG_DEB_CNT_4_RESERVED31_Pos                                                                                 16U
+#define AON_REG_DEB_CNT_4_RESERVED31_Msk                                                                                 (0xFFFFUL << AON_REG_DEB_CNT_4_RESERVED31_Pos)
+
+/* 0xE3C    0x4000_0e3c
+    0       R/W1C   DEB_CNT_0_STS                                               1'b1
+    1       R/W1C   DEB_CNT_1_STS                                               1'b1
+    2       R/W1C   DEB_CNT_2_STS                                               1'b1
+    3       R/W1C   DEB_CNT_3_STS                                               1'b1
+    4       R/W1C   DEB_CNT_4_STS                                               1'b1
+    31:5    R       RESERVED37                                                  27'h0
+ */
+typedef union _AON_REG_DEB_STS_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t DEB_CNT_0_STS: 1;
+        uint32_t DEB_CNT_1_STS: 1;
+        uint32_t DEB_CNT_2_STS: 1;
+        uint32_t DEB_CNT_3_STS: 1;
+        uint32_t DEB_CNT_4_STS: 1;
+        uint32_t RESERVED37: 27;
+    };
+} AON_REG_DEB_STS_TYPE;
+
+/*0x4000_0e3c AON_REG_DEB_STS*/
+#define AON_REG_DEB_STS_DEB_CNT_0_STS_Pos                                                                                0U
+#define AON_REG_DEB_STS_DEB_CNT_0_STS_Msk                                                                                (0x1UL << AON_REG_DEB_STS_DEB_CNT_0_STS_Pos)
+
+#define AON_REG_DEB_STS_DEB_CNT_1_STS_Pos                                                                                1U
+#define AON_REG_DEB_STS_DEB_CNT_1_STS_Msk                                                                                (0x1UL << AON_REG_DEB_STS_DEB_CNT_1_STS_Pos)
+
+#define AON_REG_DEB_STS_DEB_CNT_2_STS_Pos                                                                                2U
+#define AON_REG_DEB_STS_DEB_CNT_2_STS_Msk                                                                                (0x1UL << AON_REG_DEB_STS_DEB_CNT_2_STS_Pos)
+
+#define AON_REG_DEB_STS_DEB_CNT_3_STS_Pos                                                                                3U
+#define AON_REG_DEB_STS_DEB_CNT_3_STS_Msk                                                                                (0x1UL << AON_REG_DEB_STS_DEB_CNT_3_STS_Pos)
+
+#define AON_REG_DEB_STS_DEB_CNT_4_STS_Pos                                                                                4U
+#define AON_REG_DEB_STS_DEB_CNT_4_STS_Msk                                                                                (0x1UL << AON_REG_DEB_STS_DEB_CNT_4_STS_Pos)
+
+#define AON_REG_DEB_STS_RESERVED37_Pos                                                                                   5U
+#define AON_REG_DEB_STS_RESERVED37_Msk                                                                                   (0x7FFFFFFUL << AON_REG_DEB_STS_RESERVED37_Pos)
+
+/* 0xE90    0x4000_0e90
+    0       R/W     RESERVED_11                                                 1'b0
+    1       R/W     R_PADMUX_P0_PD_VAON_2                                       1'b0
+    2       R/W     R_PADMUX_P0_PU_EN_VAON_2                                    1'b0
+    3       R/W     RESERVED_10                                                 1'b0
+    6:4     R/W     RESERVED_9                                                  3'd0
+    7       R/W     R_PADMUX_P0_PUPDSD_AS_EN_2                                  1'b0
+    8       R/W     RESERVED_8                                                  1'b0
+    9       R/W     R_PADMUX_P0_PD_VAON_4                                       1'b0
+    10      R/W     R_PADMUX_P0_PU_EN_VAON_4                                    1'b0
+    11      R/W     RESERVED_7                                                  1'b0
+    14:12   R/W     RESERVED_6                                                  3'd0
+    15      R/W     R_PADMUX_P0_PUPDSD_AS_EN_4                                  1'b0
+    16      R/W     RESERVED_5                                                  1'b0
+    17      R/W     R_PADMUX_P0_PD_VAON_0                                       1'b0
+    18      R/W     R_PADMUX_P0_PU_EN_VAON_0                                    1'b0
+    19      R/W     RESERVED_4                                                  1'b0
+    22:20   R/W     RESERVED_3                                                  3'd0
+    23      R/W     R_PADMUX_P0_PUPDSD_AS_EN_0                                  1'b0
+    24      R/W     RESERVED_2                                                  1'b0
+    25      R/W     R_PADMUX_P0_PD_VAON_1                                       1'b0
+    26      R/W     R_PADMUX_P0_PU_EN_VAON_1                                    1'b0
+    27      R/W     RESERVED_1                                                  1'b0
+    30:28   R/W     RESERVED                                                    3'd0
+    31      R/W     R_PADMUX_P0_PUPDSD_AS_EN_1                                  1'b0
+ */
+typedef union _AON_REG_PAD_AUTO_SW_AON_REG0X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED_11: 1;
+        uint32_t R_PADMUX_P0_PD_VAON_2: 1;
+        uint32_t R_PADMUX_P0_PU_EN_VAON_2: 1;
+        uint32_t RESERVED_10: 1;
+        uint32_t RESERVED_9: 3;
+        uint32_t R_PADMUX_P0_PUPDSD_AS_EN_2: 1;
+        uint32_t RESERVED_8: 1;
+        uint32_t R_PADMUX_P0_PD_VAON_4: 1;
+        uint32_t R_PADMUX_P0_PU_EN_VAON_4: 1;
+        uint32_t RESERVED_7: 1;
+        uint32_t RESERVED_6: 3;
+        uint32_t R_PADMUX_P0_PUPDSD_AS_EN_4: 1;
+        uint32_t RESERVED_5: 1;
+        uint32_t R_PADMUX_P0_PD_VAON_0: 1;
+        uint32_t R_PADMUX_P0_PU_EN_VAON_0: 1;
+        uint32_t RESERVED_4: 1;
+        uint32_t RESERVED_3: 3;
+        uint32_t R_PADMUX_P0_PUPDSD_AS_EN_0: 1;
+        uint32_t RESERVED_2: 1;
+        uint32_t R_PADMUX_P0_PD_VAON_1: 1;
+        uint32_t R_PADMUX_P0_PU_EN_VAON_1: 1;
+        uint32_t RESERVED_1: 1;
+        uint32_t RESERVED: 3;
+        uint32_t R_PADMUX_P0_PUPDSD_AS_EN_1: 1;
+    };
+} AON_REG_PAD_AUTO_SW_AON_REG0X_TYPE;
+
+/*0x4000_0e90 AON_REG_PAD_AUTO_SW_AON_REG0X*/
+#define AON_REG_PAD_AUTO_SW_AON_REG0X_RESERVED_11_Pos                                                                    0U
+#define AON_REG_PAD_AUTO_SW_AON_REG0X_RESERVED_11_Msk                                                                    (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG0X_RESERVED_11_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG0X_R_PADMUX_P0_PD_VAON_2_Pos                                                          1U
+#define AON_REG_PAD_AUTO_SW_AON_REG0X_R_PADMUX_P0_PD_VAON_2_Msk                                                          (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG0X_R_PADMUX_P0_PD_VAON_2_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG0X_R_PADMUX_P0_PU_EN_VAON_2_Pos                                                       2U
+#define AON_REG_PAD_AUTO_SW_AON_REG0X_R_PADMUX_P0_PU_EN_VAON_2_Msk                                                       (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG0X_R_PADMUX_P0_PU_EN_VAON_2_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG0X_RESERVED_10_Pos                                                                    3U
+#define AON_REG_PAD_AUTO_SW_AON_REG0X_RESERVED_10_Msk                                                                    (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG0X_RESERVED_10_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG0X_RESERVED_9_Pos                                                                     4U
+#define AON_REG_PAD_AUTO_SW_AON_REG0X_RESERVED_9_Msk                                                                     (0x7UL << AON_REG_PAD_AUTO_SW_AON_REG0X_RESERVED_9_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG0X_R_PADMUX_P0_PUPDSD_AS_EN_2_Pos                                                     7U
+#define AON_REG_PAD_AUTO_SW_AON_REG0X_R_PADMUX_P0_PUPDSD_AS_EN_2_Msk                                                     (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG0X_R_PADMUX_P0_PUPDSD_AS_EN_2_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG0X_RESERVED_8_Pos                                                                     8U
+#define AON_REG_PAD_AUTO_SW_AON_REG0X_RESERVED_8_Msk                                                                     (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG0X_RESERVED_8_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG0X_R_PADMUX_P0_PD_VAON_4_Pos                                                          9U
+#define AON_REG_PAD_AUTO_SW_AON_REG0X_R_PADMUX_P0_PD_VAON_4_Msk                                                          (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG0X_R_PADMUX_P0_PD_VAON_4_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG0X_R_PADMUX_P0_PU_EN_VAON_4_Pos                                                       10U
+#define AON_REG_PAD_AUTO_SW_AON_REG0X_R_PADMUX_P0_PU_EN_VAON_4_Msk                                                       (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG0X_R_PADMUX_P0_PU_EN_VAON_4_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG0X_RESERVED_7_Pos                                                                     11U
+#define AON_REG_PAD_AUTO_SW_AON_REG0X_RESERVED_7_Msk                                                                     (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG0X_RESERVED_7_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG0X_RESERVED_6_Pos                                                                     12U
+#define AON_REG_PAD_AUTO_SW_AON_REG0X_RESERVED_6_Msk                                                                     (0x7UL << AON_REG_PAD_AUTO_SW_AON_REG0X_RESERVED_6_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG0X_R_PADMUX_P0_PUPDSD_AS_EN_4_Pos                                                     15U
+#define AON_REG_PAD_AUTO_SW_AON_REG0X_R_PADMUX_P0_PUPDSD_AS_EN_4_Msk                                                     (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG0X_R_PADMUX_P0_PUPDSD_AS_EN_4_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG0X_RESERVED_5_Pos                                                                     16U
+#define AON_REG_PAD_AUTO_SW_AON_REG0X_RESERVED_5_Msk                                                                     (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG0X_RESERVED_5_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG0X_R_PADMUX_P0_PD_VAON_0_Pos                                                          17U
+#define AON_REG_PAD_AUTO_SW_AON_REG0X_R_PADMUX_P0_PD_VAON_0_Msk                                                          (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG0X_R_PADMUX_P0_PD_VAON_0_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG0X_R_PADMUX_P0_PU_EN_VAON_0_Pos                                                       18U
+#define AON_REG_PAD_AUTO_SW_AON_REG0X_R_PADMUX_P0_PU_EN_VAON_0_Msk                                                       (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG0X_R_PADMUX_P0_PU_EN_VAON_0_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG0X_RESERVED_4_Pos                                                                     19U
+#define AON_REG_PAD_AUTO_SW_AON_REG0X_RESERVED_4_Msk                                                                     (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG0X_RESERVED_4_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG0X_RESERVED_3_Pos                                                                     20U
+#define AON_REG_PAD_AUTO_SW_AON_REG0X_RESERVED_3_Msk                                                                     (0x7UL << AON_REG_PAD_AUTO_SW_AON_REG0X_RESERVED_3_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG0X_R_PADMUX_P0_PUPDSD_AS_EN_0_Pos                                                     23U
+#define AON_REG_PAD_AUTO_SW_AON_REG0X_R_PADMUX_P0_PUPDSD_AS_EN_0_Msk                                                     (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG0X_R_PADMUX_P0_PUPDSD_AS_EN_0_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG0X_RESERVED_2_Pos                                                                     24U
+#define AON_REG_PAD_AUTO_SW_AON_REG0X_RESERVED_2_Msk                                                                     (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG0X_RESERVED_2_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG0X_R_PADMUX_P0_PD_VAON_1_Pos                                                          25U
+#define AON_REG_PAD_AUTO_SW_AON_REG0X_R_PADMUX_P0_PD_VAON_1_Msk                                                          (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG0X_R_PADMUX_P0_PD_VAON_1_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG0X_R_PADMUX_P0_PU_EN_VAON_1_Pos                                                       26U
+#define AON_REG_PAD_AUTO_SW_AON_REG0X_R_PADMUX_P0_PU_EN_VAON_1_Msk                                                       (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG0X_R_PADMUX_P0_PU_EN_VAON_1_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG0X_RESERVED_1_Pos                                                                     27U
+#define AON_REG_PAD_AUTO_SW_AON_REG0X_RESERVED_1_Msk                                                                     (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG0X_RESERVED_1_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG0X_RESERVED_Pos                                                                       28U
+#define AON_REG_PAD_AUTO_SW_AON_REG0X_RESERVED_Msk                                                                       (0x7UL << AON_REG_PAD_AUTO_SW_AON_REG0X_RESERVED_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG0X_R_PADMUX_P0_PUPDSD_AS_EN_1_Pos                                                     31U
+#define AON_REG_PAD_AUTO_SW_AON_REG0X_R_PADMUX_P0_PUPDSD_AS_EN_1_Msk                                                     (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG0X_R_PADMUX_P0_PUPDSD_AS_EN_1_Pos)
+
+/* 0xE94    0x4000_0e94
+    0       R/W     RESERVED_11                                                 1'b0
+    1       R/W     R_PADMUX_P1_PD_VAON_0                                       1'b0
+    2       R/W     R_PADMUX_P1_PU_EN_VAON_0                                    1'b0
+    3       R/W     RESERVED_10                                                 1'b0
+    6:4     R/W     RESERVED_9                                                  3'd0
+    7       R/W     R_PADMUX_P1_PUPDSD_AS_EN_0                                  1'b0
+    8       R/W     RESERVED_8                                                  1'b0
+    9       R/W     R_PADMUX_P1_PD_VAON_1                                       1'b0
+    10      R/W     R_PADMUX_P1_PU_EN_VAON_1                                    1'b0
+    11      R/W     RESERVED_7                                                  1'b0
+    14:12   R/W     RESERVED_6                                                  3'd0
+    15      R/W     R_PADMUX_P1_PUPDSD_AS_EN_1                                  1'b0
+    16      R/W     RESERVED_5                                                  1'b0
+    17      R/W     R_PADMUX_P0_PD_VAON_5                                       1'b0
+    18      R/W     R_PADMUX_P0_PU_EN_VAON_5                                    1'b0
+    19      R/W     RESERVED_4                                                  1'b0
+    22:20   R/W     RESERVED_3                                                  3'd0
+    23      R/W     R_PADMUX_P0_PUPDSD_AS_EN_5                                  1'b0
+    24      R/W     RESERVED_2                                                  1'b0
+    25      R/W     R_PADMUX_P0_PD_VAON_6                                       1'b0
+    26      R/W     R_PADMUX_P0_PU_EN_VAON_6                                    1'b0
+    27      R/W     RESERVED_1                                                  1'b0
+    30:28   R/W     RESERVED                                                    3'd0
+    31      R/W     R_PADMUX_P0_PUPDSD_AS_EN_6                                  1'b0
+ */
+typedef union _AON_REG_PAD_AUTO_SW_AON_REG1X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED_11: 1;
+        uint32_t R_PADMUX_P1_PD_VAON_0: 1;
+        uint32_t R_PADMUX_P1_PU_EN_VAON_0: 1;
+        uint32_t RESERVED_10: 1;
+        uint32_t RESERVED_9: 3;
+        uint32_t R_PADMUX_P1_PUPDSD_AS_EN_0: 1;
+        uint32_t RESERVED_8: 1;
+        uint32_t R_PADMUX_P1_PD_VAON_1: 1;
+        uint32_t R_PADMUX_P1_PU_EN_VAON_1: 1;
+        uint32_t RESERVED_7: 1;
+        uint32_t RESERVED_6: 3;
+        uint32_t R_PADMUX_P1_PUPDSD_AS_EN_1: 1;
+        uint32_t RESERVED_5: 1;
+        uint32_t R_PADMUX_P0_PD_VAON_5: 1;
+        uint32_t R_PADMUX_P0_PU_EN_VAON_5: 1;
+        uint32_t RESERVED_4: 1;
+        uint32_t RESERVED_3: 3;
+        uint32_t R_PADMUX_P0_PUPDSD_AS_EN_5: 1;
+        uint32_t RESERVED_2: 1;
+        uint32_t R_PADMUX_P0_PD_VAON_6: 1;
+        uint32_t R_PADMUX_P0_PU_EN_VAON_6: 1;
+        uint32_t RESERVED_1: 1;
+        uint32_t RESERVED: 3;
+        uint32_t R_PADMUX_P0_PUPDSD_AS_EN_6: 1;
+    };
+} AON_REG_PAD_AUTO_SW_AON_REG1X_TYPE;
+
+/*0x4000_0e94 AON_REG_PAD_AUTO_SW_AON_REG1X*/
+#define AON_REG_PAD_AUTO_SW_AON_REG1X_RESERVED_11_Pos                                                                    0U
+#define AON_REG_PAD_AUTO_SW_AON_REG1X_RESERVED_11_Msk                                                                    (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG1X_RESERVED_11_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG1X_R_PADMUX_P1_PD_VAON_0_Pos                                                          1U
+#define AON_REG_PAD_AUTO_SW_AON_REG1X_R_PADMUX_P1_PD_VAON_0_Msk                                                          (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG1X_R_PADMUX_P1_PD_VAON_0_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG1X_R_PADMUX_P1_PU_EN_VAON_0_Pos                                                       2U
+#define AON_REG_PAD_AUTO_SW_AON_REG1X_R_PADMUX_P1_PU_EN_VAON_0_Msk                                                       (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG1X_R_PADMUX_P1_PU_EN_VAON_0_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG1X_RESERVED_10_Pos                                                                    3U
+#define AON_REG_PAD_AUTO_SW_AON_REG1X_RESERVED_10_Msk                                                                    (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG1X_RESERVED_10_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG1X_RESERVED_9_Pos                                                                     4U
+#define AON_REG_PAD_AUTO_SW_AON_REG1X_RESERVED_9_Msk                                                                     (0x7UL << AON_REG_PAD_AUTO_SW_AON_REG1X_RESERVED_9_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG1X_R_PADMUX_P1_PUPDSD_AS_EN_0_Pos                                                     7U
+#define AON_REG_PAD_AUTO_SW_AON_REG1X_R_PADMUX_P1_PUPDSD_AS_EN_0_Msk                                                     (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG1X_R_PADMUX_P1_PUPDSD_AS_EN_0_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG1X_RESERVED_8_Pos                                                                     8U
+#define AON_REG_PAD_AUTO_SW_AON_REG1X_RESERVED_8_Msk                                                                     (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG1X_RESERVED_8_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG1X_R_PADMUX_P1_PD_VAON_1_Pos                                                          9U
+#define AON_REG_PAD_AUTO_SW_AON_REG1X_R_PADMUX_P1_PD_VAON_1_Msk                                                          (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG1X_R_PADMUX_P1_PD_VAON_1_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG1X_R_PADMUX_P1_PU_EN_VAON_1_Pos                                                       10U
+#define AON_REG_PAD_AUTO_SW_AON_REG1X_R_PADMUX_P1_PU_EN_VAON_1_Msk                                                       (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG1X_R_PADMUX_P1_PU_EN_VAON_1_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG1X_RESERVED_7_Pos                                                                     11U
+#define AON_REG_PAD_AUTO_SW_AON_REG1X_RESERVED_7_Msk                                                                     (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG1X_RESERVED_7_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG1X_RESERVED_6_Pos                                                                     12U
+#define AON_REG_PAD_AUTO_SW_AON_REG1X_RESERVED_6_Msk                                                                     (0x7UL << AON_REG_PAD_AUTO_SW_AON_REG1X_RESERVED_6_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG1X_R_PADMUX_P1_PUPDSD_AS_EN_1_Pos                                                     15U
+#define AON_REG_PAD_AUTO_SW_AON_REG1X_R_PADMUX_P1_PUPDSD_AS_EN_1_Msk                                                     (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG1X_R_PADMUX_P1_PUPDSD_AS_EN_1_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG1X_RESERVED_5_Pos                                                                     16U
+#define AON_REG_PAD_AUTO_SW_AON_REG1X_RESERVED_5_Msk                                                                     (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG1X_RESERVED_5_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG1X_R_PADMUX_P0_PD_VAON_5_Pos                                                          17U
+#define AON_REG_PAD_AUTO_SW_AON_REG1X_R_PADMUX_P0_PD_VAON_5_Msk                                                          (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG1X_R_PADMUX_P0_PD_VAON_5_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG1X_R_PADMUX_P0_PU_EN_VAON_5_Pos                                                       18U
+#define AON_REG_PAD_AUTO_SW_AON_REG1X_R_PADMUX_P0_PU_EN_VAON_5_Msk                                                       (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG1X_R_PADMUX_P0_PU_EN_VAON_5_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG1X_RESERVED_4_Pos                                                                     19U
+#define AON_REG_PAD_AUTO_SW_AON_REG1X_RESERVED_4_Msk                                                                     (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG1X_RESERVED_4_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG1X_RESERVED_3_Pos                                                                     20U
+#define AON_REG_PAD_AUTO_SW_AON_REG1X_RESERVED_3_Msk                                                                     (0x7UL << AON_REG_PAD_AUTO_SW_AON_REG1X_RESERVED_3_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG1X_R_PADMUX_P0_PUPDSD_AS_EN_5_Pos                                                     23U
+#define AON_REG_PAD_AUTO_SW_AON_REG1X_R_PADMUX_P0_PUPDSD_AS_EN_5_Msk                                                     (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG1X_R_PADMUX_P0_PUPDSD_AS_EN_5_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG1X_RESERVED_2_Pos                                                                     24U
+#define AON_REG_PAD_AUTO_SW_AON_REG1X_RESERVED_2_Msk                                                                     (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG1X_RESERVED_2_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG1X_R_PADMUX_P0_PD_VAON_6_Pos                                                          25U
+#define AON_REG_PAD_AUTO_SW_AON_REG1X_R_PADMUX_P0_PD_VAON_6_Msk                                                          (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG1X_R_PADMUX_P0_PD_VAON_6_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG1X_R_PADMUX_P0_PU_EN_VAON_6_Pos                                                       26U
+#define AON_REG_PAD_AUTO_SW_AON_REG1X_R_PADMUX_P0_PU_EN_VAON_6_Msk                                                       (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG1X_R_PADMUX_P0_PU_EN_VAON_6_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG1X_RESERVED_1_Pos                                                                     27U
+#define AON_REG_PAD_AUTO_SW_AON_REG1X_RESERVED_1_Msk                                                                     (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG1X_RESERVED_1_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG1X_RESERVED_Pos                                                                       28U
+#define AON_REG_PAD_AUTO_SW_AON_REG1X_RESERVED_Msk                                                                       (0x7UL << AON_REG_PAD_AUTO_SW_AON_REG1X_RESERVED_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG1X_R_PADMUX_P0_PUPDSD_AS_EN_6_Pos                                                     31U
+#define AON_REG_PAD_AUTO_SW_AON_REG1X_R_PADMUX_P0_PUPDSD_AS_EN_6_Msk                                                     (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG1X_R_PADMUX_P0_PUPDSD_AS_EN_6_Pos)
+
+/* 0xE98    0x4000_0e98
+    0       R/W     RESERVED_11                                                 1'b0
+    1       R/W     R_PADMUX_P2_PD_VAON_2                                       1'b0
+    2       R/W     R_PADMUX_P2_PU_EN_VAON_2                                    1'b0
+    3       R/W     RESERVED_10                                                 1'b0
+    6:4     R/W     RESERVED_9                                                  3'd0
+    7       R/W     R_PADMUX_P2_PUPDSD_AS_EN_2                                  1'b0
+    8       R/W     RESERVED_8                                                  1'b0
+    9       R/W     R_PADMUX_P2_PD_VAON_3                                       1'b0
+    10      R/W     R_PADMUX_P2_PU_EN_VAON_3                                    1'b0
+    11      R/W     RESERVED_7                                                  1'b0
+    14:12   R/W     RESERVED_6                                                  3'd0
+    15      R/W     R_PADMUX_P2_PUPDSD_AS_EN_3                                  1'b0
+    16      R/W     RESERVED_5                                                  1'b0
+    17      R/W     R_PADMUX_P2_PD_VAON_0                                       1'b0
+    18      R/W     R_PADMUX_P2_PU_EN_VAON_0                                    1'b0
+    19      R/W     RESERVED_4                                                  1'b0
+    22:20   R/W     RESERVED_3                                                  3'd0
+    23      R/W     R_PADMUX_P2_PUPDSD_AS_EN_0                                  1'b0
+    24      R/W     RESERVED_2                                                  1'b0
+    25      R/W     R_PADMUX_P2_PD_VAON_1                                       1'b0
+    26      R/W     R_PADMUX_P2_PU_EN_VAON_1                                    1'b0
+    27      R/W     RESERVED_1                                                  1'b0
+    30:28   R/W     RESERVED                                                    3'd0
+    31      R/W     R_PADMUX_P2_PUPDSD_AS_EN_1                                  1'b0
+ */
+typedef union _AON_REG_PAD_AUTO_SW_AON_REG2X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED_11: 1;
+        uint32_t R_PADMUX_P2_PD_VAON_2: 1;
+        uint32_t R_PADMUX_P2_PU_EN_VAON_2: 1;
+        uint32_t RESERVED_10: 1;
+        uint32_t RESERVED_9: 3;
+        uint32_t R_PADMUX_P2_PUPDSD_AS_EN_2: 1;
+        uint32_t RESERVED_8: 1;
+        uint32_t R_PADMUX_P2_PD_VAON_3: 1;
+        uint32_t R_PADMUX_P2_PU_EN_VAON_3: 1;
+        uint32_t RESERVED_7: 1;
+        uint32_t RESERVED_6: 3;
+        uint32_t R_PADMUX_P2_PUPDSD_AS_EN_3: 1;
+        uint32_t RESERVED_5: 1;
+        uint32_t R_PADMUX_P2_PD_VAON_0: 1;
+        uint32_t R_PADMUX_P2_PU_EN_VAON_0: 1;
+        uint32_t RESERVED_4: 1;
+        uint32_t RESERVED_3: 3;
+        uint32_t R_PADMUX_P2_PUPDSD_AS_EN_0: 1;
+        uint32_t RESERVED_2: 1;
+        uint32_t R_PADMUX_P2_PD_VAON_1: 1;
+        uint32_t R_PADMUX_P2_PU_EN_VAON_1: 1;
+        uint32_t RESERVED_1: 1;
+        uint32_t RESERVED: 3;
+        uint32_t R_PADMUX_P2_PUPDSD_AS_EN_1: 1;
+    };
+} AON_REG_PAD_AUTO_SW_AON_REG2X_TYPE;
+
+/*0x4000_0e98 AON_REG_PAD_AUTO_SW_AON_REG2X*/
+#define AON_REG_PAD_AUTO_SW_AON_REG2X_RESERVED_11_Pos                                                                    0U
+#define AON_REG_PAD_AUTO_SW_AON_REG2X_RESERVED_11_Msk                                                                    (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG2X_RESERVED_11_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG2X_R_PADMUX_P2_PD_VAON_2_Pos                                                          1U
+#define AON_REG_PAD_AUTO_SW_AON_REG2X_R_PADMUX_P2_PD_VAON_2_Msk                                                          (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG2X_R_PADMUX_P2_PD_VAON_2_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG2X_R_PADMUX_P2_PU_EN_VAON_2_Pos                                                       2U
+#define AON_REG_PAD_AUTO_SW_AON_REG2X_R_PADMUX_P2_PU_EN_VAON_2_Msk                                                       (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG2X_R_PADMUX_P2_PU_EN_VAON_2_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG2X_RESERVED_10_Pos                                                                    3U
+#define AON_REG_PAD_AUTO_SW_AON_REG2X_RESERVED_10_Msk                                                                    (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG2X_RESERVED_10_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG2X_RESERVED_9_Pos                                                                     4U
+#define AON_REG_PAD_AUTO_SW_AON_REG2X_RESERVED_9_Msk                                                                     (0x7UL << AON_REG_PAD_AUTO_SW_AON_REG2X_RESERVED_9_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG2X_R_PADMUX_P2_PUPDSD_AS_EN_2_Pos                                                     7U
+#define AON_REG_PAD_AUTO_SW_AON_REG2X_R_PADMUX_P2_PUPDSD_AS_EN_2_Msk                                                     (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG2X_R_PADMUX_P2_PUPDSD_AS_EN_2_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG2X_RESERVED_8_Pos                                                                     8U
+#define AON_REG_PAD_AUTO_SW_AON_REG2X_RESERVED_8_Msk                                                                     (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG2X_RESERVED_8_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG2X_R_PADMUX_P2_PD_VAON_3_Pos                                                          9U
+#define AON_REG_PAD_AUTO_SW_AON_REG2X_R_PADMUX_P2_PD_VAON_3_Msk                                                          (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG2X_R_PADMUX_P2_PD_VAON_3_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG2X_R_PADMUX_P2_PU_EN_VAON_3_Pos                                                       10U
+#define AON_REG_PAD_AUTO_SW_AON_REG2X_R_PADMUX_P2_PU_EN_VAON_3_Msk                                                       (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG2X_R_PADMUX_P2_PU_EN_VAON_3_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG2X_RESERVED_7_Pos                                                                     11U
+#define AON_REG_PAD_AUTO_SW_AON_REG2X_RESERVED_7_Msk                                                                     (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG2X_RESERVED_7_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG2X_RESERVED_6_Pos                                                                     12U
+#define AON_REG_PAD_AUTO_SW_AON_REG2X_RESERVED_6_Msk                                                                     (0x7UL << AON_REG_PAD_AUTO_SW_AON_REG2X_RESERVED_6_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG2X_R_PADMUX_P2_PUPDSD_AS_EN_3_Pos                                                     15U
+#define AON_REG_PAD_AUTO_SW_AON_REG2X_R_PADMUX_P2_PUPDSD_AS_EN_3_Msk                                                     (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG2X_R_PADMUX_P2_PUPDSD_AS_EN_3_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG2X_RESERVED_5_Pos                                                                     16U
+#define AON_REG_PAD_AUTO_SW_AON_REG2X_RESERVED_5_Msk                                                                     (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG2X_RESERVED_5_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG2X_R_PADMUX_P2_PD_VAON_0_Pos                                                          17U
+#define AON_REG_PAD_AUTO_SW_AON_REG2X_R_PADMUX_P2_PD_VAON_0_Msk                                                          (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG2X_R_PADMUX_P2_PD_VAON_0_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG2X_R_PADMUX_P2_PU_EN_VAON_0_Pos                                                       18U
+#define AON_REG_PAD_AUTO_SW_AON_REG2X_R_PADMUX_P2_PU_EN_VAON_0_Msk                                                       (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG2X_R_PADMUX_P2_PU_EN_VAON_0_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG2X_RESERVED_4_Pos                                                                     19U
+#define AON_REG_PAD_AUTO_SW_AON_REG2X_RESERVED_4_Msk                                                                     (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG2X_RESERVED_4_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG2X_RESERVED_3_Pos                                                                     20U
+#define AON_REG_PAD_AUTO_SW_AON_REG2X_RESERVED_3_Msk                                                                     (0x7UL << AON_REG_PAD_AUTO_SW_AON_REG2X_RESERVED_3_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG2X_R_PADMUX_P2_PUPDSD_AS_EN_0_Pos                                                     23U
+#define AON_REG_PAD_AUTO_SW_AON_REG2X_R_PADMUX_P2_PUPDSD_AS_EN_0_Msk                                                     (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG2X_R_PADMUX_P2_PUPDSD_AS_EN_0_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG2X_RESERVED_2_Pos                                                                     24U
+#define AON_REG_PAD_AUTO_SW_AON_REG2X_RESERVED_2_Msk                                                                     (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG2X_RESERVED_2_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG2X_R_PADMUX_P2_PD_VAON_1_Pos                                                          25U
+#define AON_REG_PAD_AUTO_SW_AON_REG2X_R_PADMUX_P2_PD_VAON_1_Msk                                                          (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG2X_R_PADMUX_P2_PD_VAON_1_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG2X_R_PADMUX_P2_PU_EN_VAON_1_Pos                                                       26U
+#define AON_REG_PAD_AUTO_SW_AON_REG2X_R_PADMUX_P2_PU_EN_VAON_1_Msk                                                       (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG2X_R_PADMUX_P2_PU_EN_VAON_1_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG2X_RESERVED_1_Pos                                                                     27U
+#define AON_REG_PAD_AUTO_SW_AON_REG2X_RESERVED_1_Msk                                                                     (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG2X_RESERVED_1_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG2X_RESERVED_Pos                                                                       28U
+#define AON_REG_PAD_AUTO_SW_AON_REG2X_RESERVED_Msk                                                                       (0x7UL << AON_REG_PAD_AUTO_SW_AON_REG2X_RESERVED_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG2X_R_PADMUX_P2_PUPDSD_AS_EN_1_Pos                                                     31U
+#define AON_REG_PAD_AUTO_SW_AON_REG2X_R_PADMUX_P2_PUPDSD_AS_EN_1_Msk                                                     (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG2X_R_PADMUX_P2_PUPDSD_AS_EN_1_Pos)
+
+/* 0xE9C    0x4000_0e9c
+    0       R/W     RESERVED_11                                                 1'b0
+    1       R/W     R_PADMUX_P2_PD_VAON_6                                       1'b0
+    2       R/W     R_PADMUX_P2_PU_EN_VAON_6                                    1'b0
+    3       R/W     RESERVED_10                                                 1'b0
+    6:4     R/W     RESERVED_9                                                  3'd0
+    7       R/W     R_PADMUX_P2_PUPDSD_AS_EN_6                                  1'b0
+    8       R/W     RESERVED_8                                                  1'b0
+    9       R/W     R_PADMUX_P2_PD_VAON_7                                       1'b0
+    10      R/W     R_PADMUX_P2_PU_EN_VAON_7                                    1'b0
+    11      R/W     RESERVED_7                                                  1'b0
+    14:12   R/W     RESERVED_6                                                  3'd0
+    15      R/W     R_PADMUX_P2_PUPDSD_AS_EN_7                                  1'b0
+    16      R/W     RESERVED_5                                                  1'b0
+    17      R/W     R_PADMUX_P2_PD_VAON_4                                       1'b0
+    18      R/W     R_PADMUX_P2_PU_EN_VAON_4                                    1'b0
+    19      R/W     RESERVED_4                                                  1'b0
+    22:20   R/W     RESERVED_3                                                  3'd0
+    23      R/W     R_PADMUX_P2_PUPDSD_AS_EN_4                                  1'b0
+    24      R/W     RESERVED_2                                                  1'b0
+    25      R/W     R_PADMUX_P2_PD_VAON_5                                       1'b0
+    26      R/W     R_PADMUX_P2_PU_EN_VAON_5                                    1'b0
+    27      R/W     RESERVED_1                                                  1'b0
+    30:28   R/W     RESERVED                                                    3'd0
+    31      R/W     R_PADMUX_P2_PUPDSD_AS_EN_5                                  1'b0
+ */
+typedef union _AON_REG_PAD_AUTO_SW_AON_REG3X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED_11: 1;
+        uint32_t R_PADMUX_P2_PD_VAON_6: 1;
+        uint32_t R_PADMUX_P2_PU_EN_VAON_6: 1;
+        uint32_t RESERVED_10: 1;
+        uint32_t RESERVED_9: 3;
+        uint32_t R_PADMUX_P2_PUPDSD_AS_EN_6: 1;
+        uint32_t RESERVED_8: 1;
+        uint32_t R_PADMUX_P2_PD_VAON_7: 1;
+        uint32_t R_PADMUX_P2_PU_EN_VAON_7: 1;
+        uint32_t RESERVED_7: 1;
+        uint32_t RESERVED_6: 3;
+        uint32_t R_PADMUX_P2_PUPDSD_AS_EN_7: 1;
+        uint32_t RESERVED_5: 1;
+        uint32_t R_PADMUX_P2_PD_VAON_4: 1;
+        uint32_t R_PADMUX_P2_PU_EN_VAON_4: 1;
+        uint32_t RESERVED_4: 1;
+        uint32_t RESERVED_3: 3;
+        uint32_t R_PADMUX_P2_PUPDSD_AS_EN_4: 1;
+        uint32_t RESERVED_2: 1;
+        uint32_t R_PADMUX_P2_PD_VAON_5: 1;
+        uint32_t R_PADMUX_P2_PU_EN_VAON_5: 1;
+        uint32_t RESERVED_1: 1;
+        uint32_t RESERVED: 3;
+        uint32_t R_PADMUX_P2_PUPDSD_AS_EN_5: 1;
+    };
+} AON_REG_PAD_AUTO_SW_AON_REG3X_TYPE;
+
+/*0x4000_0e9c AON_REG_PAD_AUTO_SW_AON_REG3X*/
+#define AON_REG_PAD_AUTO_SW_AON_REG3X_RESERVED_11_Pos                                                                    0U
+#define AON_REG_PAD_AUTO_SW_AON_REG3X_RESERVED_11_Msk                                                                    (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG3X_RESERVED_11_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG3X_R_PADMUX_P2_PD_VAON_6_Pos                                                          1U
+#define AON_REG_PAD_AUTO_SW_AON_REG3X_R_PADMUX_P2_PD_VAON_6_Msk                                                          (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG3X_R_PADMUX_P2_PD_VAON_6_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG3X_R_PADMUX_P2_PU_EN_VAON_6_Pos                                                       2U
+#define AON_REG_PAD_AUTO_SW_AON_REG3X_R_PADMUX_P2_PU_EN_VAON_6_Msk                                                       (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG3X_R_PADMUX_P2_PU_EN_VAON_6_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG3X_RESERVED_10_Pos                                                                    3U
+#define AON_REG_PAD_AUTO_SW_AON_REG3X_RESERVED_10_Msk                                                                    (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG3X_RESERVED_10_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG3X_RESERVED_9_Pos                                                                     4U
+#define AON_REG_PAD_AUTO_SW_AON_REG3X_RESERVED_9_Msk                                                                     (0x7UL << AON_REG_PAD_AUTO_SW_AON_REG3X_RESERVED_9_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG3X_R_PADMUX_P2_PUPDSD_AS_EN_6_Pos                                                     7U
+#define AON_REG_PAD_AUTO_SW_AON_REG3X_R_PADMUX_P2_PUPDSD_AS_EN_6_Msk                                                     (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG3X_R_PADMUX_P2_PUPDSD_AS_EN_6_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG3X_RESERVED_8_Pos                                                                     8U
+#define AON_REG_PAD_AUTO_SW_AON_REG3X_RESERVED_8_Msk                                                                     (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG3X_RESERVED_8_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG3X_R_PADMUX_P2_PD_VAON_7_Pos                                                          9U
+#define AON_REG_PAD_AUTO_SW_AON_REG3X_R_PADMUX_P2_PD_VAON_7_Msk                                                          (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG3X_R_PADMUX_P2_PD_VAON_7_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG3X_R_PADMUX_P2_PU_EN_VAON_7_Pos                                                       10U
+#define AON_REG_PAD_AUTO_SW_AON_REG3X_R_PADMUX_P2_PU_EN_VAON_7_Msk                                                       (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG3X_R_PADMUX_P2_PU_EN_VAON_7_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG3X_RESERVED_7_Pos                                                                     11U
+#define AON_REG_PAD_AUTO_SW_AON_REG3X_RESERVED_7_Msk                                                                     (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG3X_RESERVED_7_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG3X_RESERVED_6_Pos                                                                     12U
+#define AON_REG_PAD_AUTO_SW_AON_REG3X_RESERVED_6_Msk                                                                     (0x7UL << AON_REG_PAD_AUTO_SW_AON_REG3X_RESERVED_6_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG3X_R_PADMUX_P2_PUPDSD_AS_EN_7_Pos                                                     15U
+#define AON_REG_PAD_AUTO_SW_AON_REG3X_R_PADMUX_P2_PUPDSD_AS_EN_7_Msk                                                     (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG3X_R_PADMUX_P2_PUPDSD_AS_EN_7_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG3X_RESERVED_5_Pos                                                                     16U
+#define AON_REG_PAD_AUTO_SW_AON_REG3X_RESERVED_5_Msk                                                                     (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG3X_RESERVED_5_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG3X_R_PADMUX_P2_PD_VAON_4_Pos                                                          17U
+#define AON_REG_PAD_AUTO_SW_AON_REG3X_R_PADMUX_P2_PD_VAON_4_Msk                                                          (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG3X_R_PADMUX_P2_PD_VAON_4_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG3X_R_PADMUX_P2_PU_EN_VAON_4_Pos                                                       18U
+#define AON_REG_PAD_AUTO_SW_AON_REG3X_R_PADMUX_P2_PU_EN_VAON_4_Msk                                                       (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG3X_R_PADMUX_P2_PU_EN_VAON_4_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG3X_RESERVED_4_Pos                                                                     19U
+#define AON_REG_PAD_AUTO_SW_AON_REG3X_RESERVED_4_Msk                                                                     (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG3X_RESERVED_4_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG3X_RESERVED_3_Pos                                                                     20U
+#define AON_REG_PAD_AUTO_SW_AON_REG3X_RESERVED_3_Msk                                                                     (0x7UL << AON_REG_PAD_AUTO_SW_AON_REG3X_RESERVED_3_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG3X_R_PADMUX_P2_PUPDSD_AS_EN_4_Pos                                                     23U
+#define AON_REG_PAD_AUTO_SW_AON_REG3X_R_PADMUX_P2_PUPDSD_AS_EN_4_Msk                                                     (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG3X_R_PADMUX_P2_PUPDSD_AS_EN_4_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG3X_RESERVED_2_Pos                                                                     24U
+#define AON_REG_PAD_AUTO_SW_AON_REG3X_RESERVED_2_Msk                                                                     (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG3X_RESERVED_2_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG3X_R_PADMUX_P2_PD_VAON_5_Pos                                                          25U
+#define AON_REG_PAD_AUTO_SW_AON_REG3X_R_PADMUX_P2_PD_VAON_5_Msk                                                          (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG3X_R_PADMUX_P2_PD_VAON_5_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG3X_R_PADMUX_P2_PU_EN_VAON_5_Pos                                                       26U
+#define AON_REG_PAD_AUTO_SW_AON_REG3X_R_PADMUX_P2_PU_EN_VAON_5_Msk                                                       (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG3X_R_PADMUX_P2_PU_EN_VAON_5_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG3X_RESERVED_1_Pos                                                                     27U
+#define AON_REG_PAD_AUTO_SW_AON_REG3X_RESERVED_1_Msk                                                                     (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG3X_RESERVED_1_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG3X_RESERVED_Pos                                                                       28U
+#define AON_REG_PAD_AUTO_SW_AON_REG3X_RESERVED_Msk                                                                       (0x7UL << AON_REG_PAD_AUTO_SW_AON_REG3X_RESERVED_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG3X_R_PADMUX_P2_PUPDSD_AS_EN_5_Pos                                                     31U
+#define AON_REG_PAD_AUTO_SW_AON_REG3X_R_PADMUX_P2_PUPDSD_AS_EN_5_Msk                                                     (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG3X_R_PADMUX_P2_PUPDSD_AS_EN_5_Pos)
+
+/* 0xEA0    0x4000_0ea0
+    0       R/W     RESERVED_11                                                 1'b0
+    1       R/W     R_PADMUX_P3_PD_VAON_2                                       1'b0
+    2       R/W     R_PADMUX_P3_PU_EN_VAON_2                                    1'b0
+    3       R/W     RESERVED_10                                                 1'b0
+    6:4     R/W     RESERVED_9                                                  3'd0
+    7       R/W     R_PADMUX_P3_PUPDSD_AS_EN_2                                  1'b0
+    8       R/W     RESERVED_8                                                  1'b0
+    9       R/W     R_PADMUX_P3_PD_VAON_3                                       1'b0
+    10      R/W     R_PADMUX_P3_PU_EN_VAON_3                                    1'b0
+    11      R/W     RESERVED_7                                                  1'b0
+    14:12   R/W     RESERVED_6                                                  3'd0
+    15      R/W     R_PADMUX_P3_PUPDSD_AS_EN_3                                  1'b0
+    16      R/W     RESERVED_5                                                  1'b0
+    17      R/W     R_PADMUX_P3_PD_VAON_0                                       1'b0
+    18      R/W     R_PADMUX_P3_PU_EN_VAON_0                                    1'b0
+    19      R/W     RESERVED_4                                                  1'b0
+    22:20   R/W     RESERVED_3                                                  3'd0
+    23      R/W     R_PADMUX_P3_PUPDSD_AS_EN_0                                  1'b0
+    24      R/W     RESERVED_2                                                  1'b0
+    25      R/W     R_PADMUX_P3_PD_VAON_1                                       1'b0
+    26      R/W     R_PADMUX_P3_PU_EN_VAON_1                                    1'b0
+    27      R/W     RESERVED_1                                                  1'b0
+    30:28   R/W     RESERVED                                                    3'd0
+    31      R/W     R_PADMUX_P3_PUPDSD_AS_EN_1                                  1'b0
+ */
+typedef union _AON_REG_PAD_AUTO_SW_AON_REG4X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED_11: 1;
+        uint32_t R_PADMUX_P3_PD_VAON_2: 1;
+        uint32_t R_PADMUX_P3_PU_EN_VAON_2: 1;
+        uint32_t RESERVED_10: 1;
+        uint32_t RESERVED_9: 3;
+        uint32_t R_PADMUX_P3_PUPDSD_AS_EN_2: 1;
+        uint32_t RESERVED_8: 1;
+        uint32_t R_PADMUX_P3_PD_VAON_3: 1;
+        uint32_t R_PADMUX_P3_PU_EN_VAON_3: 1;
+        uint32_t RESERVED_7: 1;
+        uint32_t RESERVED_6: 3;
+        uint32_t R_PADMUX_P3_PUPDSD_AS_EN_3: 1;
+        uint32_t RESERVED_5: 1;
+        uint32_t R_PADMUX_P3_PD_VAON_0: 1;
+        uint32_t R_PADMUX_P3_PU_EN_VAON_0: 1;
+        uint32_t RESERVED_4: 1;
+        uint32_t RESERVED_3: 3;
+        uint32_t R_PADMUX_P3_PUPDSD_AS_EN_0: 1;
+        uint32_t RESERVED_2: 1;
+        uint32_t R_PADMUX_P3_PD_VAON_1: 1;
+        uint32_t R_PADMUX_P3_PU_EN_VAON_1: 1;
+        uint32_t RESERVED_1: 1;
+        uint32_t RESERVED: 3;
+        uint32_t R_PADMUX_P3_PUPDSD_AS_EN_1: 1;
+    };
+} AON_REG_PAD_AUTO_SW_AON_REG4X_TYPE;
+
+/*0x4000_0ea0 AON_REG_PAD_AUTO_SW_AON_REG4X*/
+#define AON_REG_PAD_AUTO_SW_AON_REG4X_RESERVED_11_Pos                                                                    0U
+#define AON_REG_PAD_AUTO_SW_AON_REG4X_RESERVED_11_Msk                                                                    (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG4X_RESERVED_11_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG4X_R_PADMUX_P3_PD_VAON_2_Pos                                                          1U
+#define AON_REG_PAD_AUTO_SW_AON_REG4X_R_PADMUX_P3_PD_VAON_2_Msk                                                          (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG4X_R_PADMUX_P3_PD_VAON_2_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG4X_R_PADMUX_P3_PU_EN_VAON_2_Pos                                                       2U
+#define AON_REG_PAD_AUTO_SW_AON_REG4X_R_PADMUX_P3_PU_EN_VAON_2_Msk                                                       (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG4X_R_PADMUX_P3_PU_EN_VAON_2_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG4X_RESERVED_10_Pos                                                                    3U
+#define AON_REG_PAD_AUTO_SW_AON_REG4X_RESERVED_10_Msk                                                                    (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG4X_RESERVED_10_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG4X_RESERVED_9_Pos                                                                     4U
+#define AON_REG_PAD_AUTO_SW_AON_REG4X_RESERVED_9_Msk                                                                     (0x7UL << AON_REG_PAD_AUTO_SW_AON_REG4X_RESERVED_9_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG4X_R_PADMUX_P3_PUPDSD_AS_EN_2_Pos                                                     7U
+#define AON_REG_PAD_AUTO_SW_AON_REG4X_R_PADMUX_P3_PUPDSD_AS_EN_2_Msk                                                     (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG4X_R_PADMUX_P3_PUPDSD_AS_EN_2_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG4X_RESERVED_8_Pos                                                                     8U
+#define AON_REG_PAD_AUTO_SW_AON_REG4X_RESERVED_8_Msk                                                                     (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG4X_RESERVED_8_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG4X_R_PADMUX_P3_PD_VAON_3_Pos                                                          9U
+#define AON_REG_PAD_AUTO_SW_AON_REG4X_R_PADMUX_P3_PD_VAON_3_Msk                                                          (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG4X_R_PADMUX_P3_PD_VAON_3_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG4X_R_PADMUX_P3_PU_EN_VAON_3_Pos                                                       10U
+#define AON_REG_PAD_AUTO_SW_AON_REG4X_R_PADMUX_P3_PU_EN_VAON_3_Msk                                                       (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG4X_R_PADMUX_P3_PU_EN_VAON_3_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG4X_RESERVED_7_Pos                                                                     11U
+#define AON_REG_PAD_AUTO_SW_AON_REG4X_RESERVED_7_Msk                                                                     (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG4X_RESERVED_7_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG4X_RESERVED_6_Pos                                                                     12U
+#define AON_REG_PAD_AUTO_SW_AON_REG4X_RESERVED_6_Msk                                                                     (0x7UL << AON_REG_PAD_AUTO_SW_AON_REG4X_RESERVED_6_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG4X_R_PADMUX_P3_PUPDSD_AS_EN_3_Pos                                                     15U
+#define AON_REG_PAD_AUTO_SW_AON_REG4X_R_PADMUX_P3_PUPDSD_AS_EN_3_Msk                                                     (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG4X_R_PADMUX_P3_PUPDSD_AS_EN_3_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG4X_RESERVED_5_Pos                                                                     16U
+#define AON_REG_PAD_AUTO_SW_AON_REG4X_RESERVED_5_Msk                                                                     (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG4X_RESERVED_5_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG4X_R_PADMUX_P3_PD_VAON_0_Pos                                                          17U
+#define AON_REG_PAD_AUTO_SW_AON_REG4X_R_PADMUX_P3_PD_VAON_0_Msk                                                          (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG4X_R_PADMUX_P3_PD_VAON_0_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG4X_R_PADMUX_P3_PU_EN_VAON_0_Pos                                                       18U
+#define AON_REG_PAD_AUTO_SW_AON_REG4X_R_PADMUX_P3_PU_EN_VAON_0_Msk                                                       (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG4X_R_PADMUX_P3_PU_EN_VAON_0_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG4X_RESERVED_4_Pos                                                                     19U
+#define AON_REG_PAD_AUTO_SW_AON_REG4X_RESERVED_4_Msk                                                                     (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG4X_RESERVED_4_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG4X_RESERVED_3_Pos                                                                     20U
+#define AON_REG_PAD_AUTO_SW_AON_REG4X_RESERVED_3_Msk                                                                     (0x7UL << AON_REG_PAD_AUTO_SW_AON_REG4X_RESERVED_3_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG4X_R_PADMUX_P3_PUPDSD_AS_EN_0_Pos                                                     23U
+#define AON_REG_PAD_AUTO_SW_AON_REG4X_R_PADMUX_P3_PUPDSD_AS_EN_0_Msk                                                     (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG4X_R_PADMUX_P3_PUPDSD_AS_EN_0_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG4X_RESERVED_2_Pos                                                                     24U
+#define AON_REG_PAD_AUTO_SW_AON_REG4X_RESERVED_2_Msk                                                                     (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG4X_RESERVED_2_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG4X_R_PADMUX_P3_PD_VAON_1_Pos                                                          25U
+#define AON_REG_PAD_AUTO_SW_AON_REG4X_R_PADMUX_P3_PD_VAON_1_Msk                                                          (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG4X_R_PADMUX_P3_PD_VAON_1_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG4X_R_PADMUX_P3_PU_EN_VAON_1_Pos                                                       26U
+#define AON_REG_PAD_AUTO_SW_AON_REG4X_R_PADMUX_P3_PU_EN_VAON_1_Msk                                                       (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG4X_R_PADMUX_P3_PU_EN_VAON_1_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG4X_RESERVED_1_Pos                                                                     27U
+#define AON_REG_PAD_AUTO_SW_AON_REG4X_RESERVED_1_Msk                                                                     (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG4X_RESERVED_1_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG4X_RESERVED_Pos                                                                       28U
+#define AON_REG_PAD_AUTO_SW_AON_REG4X_RESERVED_Msk                                                                       (0x7UL << AON_REG_PAD_AUTO_SW_AON_REG4X_RESERVED_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG4X_R_PADMUX_P3_PUPDSD_AS_EN_1_Pos                                                     31U
+#define AON_REG_PAD_AUTO_SW_AON_REG4X_R_PADMUX_P3_PUPDSD_AS_EN_1_Msk                                                     (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG4X_R_PADMUX_P3_PUPDSD_AS_EN_1_Pos)
+
+/* 0xEA4    0x4000_0ea4
+    0       R/W     RESERVED_11                                                 1'b0
+    1       R/W     R_PADMUX_P4_PD_VAON_2                                       1'b0
+    2       R/W     R_PADMUX_P4_PU_EN_VAON_2                                    1'b0
+    3       R/W     RESERVED_10                                                 1'b0
+    6:4     R/W     RESERVED_9                                                  3'd0
+    7       R/W     R_PADMUX_P4_PUPDSD_AS_EN_2                                  1'b0
+    8       R/W     RESERVED_8                                                  1'b0
+    9       R/W     R_PADMUX_P4_PD_VAON_3                                       1'b0
+    10      R/W     R_PADMUX_P4_PU_EN_VAON_3                                    1'b0
+    11      R/W     RESERVED_7                                                  1'b0
+    14:12   R/W     RESERVED_6                                                  3'd0
+    15      R/W     R_PADMUX_P4_PUPDSD_AS_EN_3                                  1'b0
+    16      R/W     RESERVED_5                                                  1'b0
+    17      R/W     R_PADMUX_P4_PD_VAON_0                                       1'b0
+    18      R/W     R_PADMUX_P4_PU_EN_VAON_0                                    1'b0
+    19      R/W     RESERVED_4                                                  1'b0
+    22:20   R/W     RESERVED_3                                                  3'd0
+    23      R/W     R_PADMUX_P4_PUPDSD_AS_EN_0                                  1'b0
+    24      R/W     RESERVED_2                                                  1'b0
+    25      R/W     R_PADMUX_P4_PD_VAON_1                                       1'b0
+    26      R/W     R_PADMUX_P4_PU_EN_VAON_1                                    1'b0
+    27      R/W     RESERVED_1                                                  1'b0
+    30:28   R/W     RESERVED                                                    3'd0
+    31      R/W     R_PADMUX_P4_PUPDSD_AS_EN_1                                  1'b0
+ */
+typedef union _AON_REG_PAD_AUTO_SW_AON_REG5X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED_11: 1;
+        uint32_t R_PADMUX_P4_PD_VAON_2: 1;
+        uint32_t R_PADMUX_P4_PU_EN_VAON_2: 1;
+        uint32_t RESERVED_10: 1;
+        uint32_t RESERVED_9: 3;
+        uint32_t R_PADMUX_P4_PUPDSD_AS_EN_2: 1;
+        uint32_t RESERVED_8: 1;
+        uint32_t R_PADMUX_P4_PD_VAON_3: 1;
+        uint32_t R_PADMUX_P4_PU_EN_VAON_3: 1;
+        uint32_t RESERVED_7: 1;
+        uint32_t RESERVED_6: 3;
+        uint32_t R_PADMUX_P4_PUPDSD_AS_EN_3: 1;
+        uint32_t RESERVED_5: 1;
+        uint32_t R_PADMUX_P4_PD_VAON_0: 1;
+        uint32_t R_PADMUX_P4_PU_EN_VAON_0: 1;
+        uint32_t RESERVED_4: 1;
+        uint32_t RESERVED_3: 3;
+        uint32_t R_PADMUX_P4_PUPDSD_AS_EN_0: 1;
+        uint32_t RESERVED_2: 1;
+        uint32_t R_PADMUX_P4_PD_VAON_1: 1;
+        uint32_t R_PADMUX_P4_PU_EN_VAON_1: 1;
+        uint32_t RESERVED_1: 1;
+        uint32_t RESERVED: 3;
+        uint32_t R_PADMUX_P4_PUPDSD_AS_EN_1: 1;
+    };
+} AON_REG_PAD_AUTO_SW_AON_REG5X_TYPE;
+
+/*0x4000_0ea4 AON_REG_PAD_AUTO_SW_AON_REG5X*/
+#define AON_REG_PAD_AUTO_SW_AON_REG5X_RESERVED_11_Pos                                                                    0U
+#define AON_REG_PAD_AUTO_SW_AON_REG5X_RESERVED_11_Msk                                                                    (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG5X_RESERVED_11_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG5X_R_PADMUX_P4_PD_VAON_2_Pos                                                          1U
+#define AON_REG_PAD_AUTO_SW_AON_REG5X_R_PADMUX_P4_PD_VAON_2_Msk                                                          (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG5X_R_PADMUX_P4_PD_VAON_2_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG5X_R_PADMUX_P4_PU_EN_VAON_2_Pos                                                       2U
+#define AON_REG_PAD_AUTO_SW_AON_REG5X_R_PADMUX_P4_PU_EN_VAON_2_Msk                                                       (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG5X_R_PADMUX_P4_PU_EN_VAON_2_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG5X_RESERVED_10_Pos                                                                    3U
+#define AON_REG_PAD_AUTO_SW_AON_REG5X_RESERVED_10_Msk                                                                    (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG5X_RESERVED_10_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG5X_RESERVED_9_Pos                                                                     4U
+#define AON_REG_PAD_AUTO_SW_AON_REG5X_RESERVED_9_Msk                                                                     (0x7UL << AON_REG_PAD_AUTO_SW_AON_REG5X_RESERVED_9_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG5X_R_PADMUX_P4_PUPDSD_AS_EN_2_Pos                                                     7U
+#define AON_REG_PAD_AUTO_SW_AON_REG5X_R_PADMUX_P4_PUPDSD_AS_EN_2_Msk                                                     (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG5X_R_PADMUX_P4_PUPDSD_AS_EN_2_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG5X_RESERVED_8_Pos                                                                     8U
+#define AON_REG_PAD_AUTO_SW_AON_REG5X_RESERVED_8_Msk                                                                     (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG5X_RESERVED_8_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG5X_R_PADMUX_P4_PD_VAON_3_Pos                                                          9U
+#define AON_REG_PAD_AUTO_SW_AON_REG5X_R_PADMUX_P4_PD_VAON_3_Msk                                                          (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG5X_R_PADMUX_P4_PD_VAON_3_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG5X_R_PADMUX_P4_PU_EN_VAON_3_Pos                                                       10U
+#define AON_REG_PAD_AUTO_SW_AON_REG5X_R_PADMUX_P4_PU_EN_VAON_3_Msk                                                       (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG5X_R_PADMUX_P4_PU_EN_VAON_3_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG5X_RESERVED_7_Pos                                                                     11U
+#define AON_REG_PAD_AUTO_SW_AON_REG5X_RESERVED_7_Msk                                                                     (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG5X_RESERVED_7_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG5X_RESERVED_6_Pos                                                                     12U
+#define AON_REG_PAD_AUTO_SW_AON_REG5X_RESERVED_6_Msk                                                                     (0x7UL << AON_REG_PAD_AUTO_SW_AON_REG5X_RESERVED_6_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG5X_R_PADMUX_P4_PUPDSD_AS_EN_3_Pos                                                     15U
+#define AON_REG_PAD_AUTO_SW_AON_REG5X_R_PADMUX_P4_PUPDSD_AS_EN_3_Msk                                                     (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG5X_R_PADMUX_P4_PUPDSD_AS_EN_3_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG5X_RESERVED_5_Pos                                                                     16U
+#define AON_REG_PAD_AUTO_SW_AON_REG5X_RESERVED_5_Msk                                                                     (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG5X_RESERVED_5_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG5X_R_PADMUX_P4_PD_VAON_0_Pos                                                          17U
+#define AON_REG_PAD_AUTO_SW_AON_REG5X_R_PADMUX_P4_PD_VAON_0_Msk                                                          (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG5X_R_PADMUX_P4_PD_VAON_0_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG5X_R_PADMUX_P4_PU_EN_VAON_0_Pos                                                       18U
+#define AON_REG_PAD_AUTO_SW_AON_REG5X_R_PADMUX_P4_PU_EN_VAON_0_Msk                                                       (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG5X_R_PADMUX_P4_PU_EN_VAON_0_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG5X_RESERVED_4_Pos                                                                     19U
+#define AON_REG_PAD_AUTO_SW_AON_REG5X_RESERVED_4_Msk                                                                     (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG5X_RESERVED_4_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG5X_RESERVED_3_Pos                                                                     20U
+#define AON_REG_PAD_AUTO_SW_AON_REG5X_RESERVED_3_Msk                                                                     (0x7UL << AON_REG_PAD_AUTO_SW_AON_REG5X_RESERVED_3_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG5X_R_PADMUX_P4_PUPDSD_AS_EN_0_Pos                                                     23U
+#define AON_REG_PAD_AUTO_SW_AON_REG5X_R_PADMUX_P4_PUPDSD_AS_EN_0_Msk                                                     (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG5X_R_PADMUX_P4_PUPDSD_AS_EN_0_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG5X_RESERVED_2_Pos                                                                     24U
+#define AON_REG_PAD_AUTO_SW_AON_REG5X_RESERVED_2_Msk                                                                     (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG5X_RESERVED_2_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG5X_R_PADMUX_P4_PD_VAON_1_Pos                                                          25U
+#define AON_REG_PAD_AUTO_SW_AON_REG5X_R_PADMUX_P4_PD_VAON_1_Msk                                                          (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG5X_R_PADMUX_P4_PD_VAON_1_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG5X_R_PADMUX_P4_PU_EN_VAON_1_Pos                                                       26U
+#define AON_REG_PAD_AUTO_SW_AON_REG5X_R_PADMUX_P4_PU_EN_VAON_1_Msk                                                       (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG5X_R_PADMUX_P4_PU_EN_VAON_1_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG5X_RESERVED_1_Pos                                                                     27U
+#define AON_REG_PAD_AUTO_SW_AON_REG5X_RESERVED_1_Msk                                                                     (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG5X_RESERVED_1_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG5X_RESERVED_Pos                                                                       28U
+#define AON_REG_PAD_AUTO_SW_AON_REG5X_RESERVED_Msk                                                                       (0x7UL << AON_REG_PAD_AUTO_SW_AON_REG5X_RESERVED_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG5X_R_PADMUX_P4_PUPDSD_AS_EN_1_Pos                                                     31U
+#define AON_REG_PAD_AUTO_SW_AON_REG5X_R_PADMUX_P4_PUPDSD_AS_EN_1_Msk                                                     (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG5X_R_PADMUX_P4_PUPDSD_AS_EN_1_Pos)
+
+/* 0xEA8    0x4000_0ea8
+    0       R/W     RESERVED_11                                                 1'b0
+    1       R/W     R_PADMUX_SPIC_SIO1_PD_VAON                                  1'b0
+    2       R/W     R_PADMUX_SPIC_SIO1_PU_EN_VAON                               1'b0
+    3       R/W     RESERVED_10                                                 1'b0
+    6:4     R/W     RESERVED_9                                                  3'd0
+    7       R/W     R_PADMUX_SPIC_SIO1_PUPDSD_AS_EN                             1'b0
+    8       R/W     RESERVED_8                                                  1'b0
+    9       R/W     R_PADMUX_SPIC_SIO0_PD_VAON                                  1'b0
+    10      R/W     R_PADMUX_SPIC_SIO0_PU_EN_VAON                               1'b0
+    11      R/W     RESERVED_7                                                  1'b0
+    14:12   R/W     RESERVED_6                                                  3'd0
+    15      R/W     R_PADMUX_SPIC_SIO0_PUPDSD_AS_EN                             1'b0
+    16      R/W     RESERVED_5                                                  1'b0
+    17      R/W     R_PADMUX_SPIC_SCK_PD_VAON                                   1'b0
+    18      R/W     R_PADMUX_SPIC_SCK_PU_EN_VAON                                1'b0
+    19      R/W     RESERVED_4                                                  1'b0
+    22:20   R/W     RESERVED_3                                                  3'd0
+    23      R/W     R_PADMUX_SPIC_SCK_PUPDSD_AS_EN                              1'b0
+    24      R/W     RESERVED_2                                                  1'b0
+    25      R/W     R_PADMUX_SPIC_CSN_PD_VAON                                   1'b0
+    26      R/W     R_PADMUX_SPIC_CSN_PU_EN_VAON                                1'b0
+    27      R/W     RESERVED_1                                                  1'b0
+    30:28   R/W     RESERVED                                                    3'd0
+    31      R/W     R_PADMUX_SPIC_CSN_PUPDSD_AS_EN                              1'b0
+ */
+typedef union _AON_REG_PAD_AUTO_SW_AON_REG6X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED_11: 1;
+        uint32_t R_PADMUX_SPIC_SIO1_PD_VAON: 1;
+        uint32_t R_PADMUX_SPIC_SIO1_PU_EN_VAON: 1;
+        uint32_t RESERVED_10: 1;
+        uint32_t RESERVED_9: 3;
+        uint32_t R_PADMUX_SPIC_SIO1_PUPDSD_AS_EN: 1;
+        uint32_t RESERVED_8: 1;
+        uint32_t R_PADMUX_SPIC_SIO0_PD_VAON: 1;
+        uint32_t R_PADMUX_SPIC_SIO0_PU_EN_VAON: 1;
+        uint32_t RESERVED_7: 1;
+        uint32_t RESERVED_6: 3;
+        uint32_t R_PADMUX_SPIC_SIO0_PUPDSD_AS_EN: 1;
+        uint32_t RESERVED_5: 1;
+        uint32_t R_PADMUX_SPIC_SCK_PD_VAON: 1;
+        uint32_t R_PADMUX_SPIC_SCK_PU_EN_VAON: 1;
+        uint32_t RESERVED_4: 1;
+        uint32_t RESERVED_3: 3;
+        uint32_t R_PADMUX_SPIC_SCK_PUPDSD_AS_EN: 1;
+        uint32_t RESERVED_2: 1;
+        uint32_t R_PADMUX_SPIC_CSN_PD_VAON: 1;
+        uint32_t R_PADMUX_SPIC_CSN_PU_EN_VAON: 1;
+        uint32_t RESERVED_1: 1;
+        uint32_t RESERVED: 3;
+        uint32_t R_PADMUX_SPIC_CSN_PUPDSD_AS_EN: 1;
+    };
+} AON_REG_PAD_AUTO_SW_AON_REG6X_TYPE;
+
+/*0x4000_0ea8 AON_REG_PAD_AUTO_SW_AON_REG6X*/
+#define AON_REG_PAD_AUTO_SW_AON_REG6X_RESERVED_11_Pos                                                                    0U
+#define AON_REG_PAD_AUTO_SW_AON_REG6X_RESERVED_11_Msk                                                                    (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG6X_RESERVED_11_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG6X_R_PADMUX_SPIC_SIO1_PD_VAON_Pos                                                     1U
+#define AON_REG_PAD_AUTO_SW_AON_REG6X_R_PADMUX_SPIC_SIO1_PD_VAON_Msk                                                     (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG6X_R_PADMUX_SPIC_SIO1_PD_VAON_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG6X_R_PADMUX_SPIC_SIO1_PU_EN_VAON_Pos                                                  2U
+#define AON_REG_PAD_AUTO_SW_AON_REG6X_R_PADMUX_SPIC_SIO1_PU_EN_VAON_Msk                                                  (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG6X_R_PADMUX_SPIC_SIO1_PU_EN_VAON_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG6X_RESERVED_10_Pos                                                                    3U
+#define AON_REG_PAD_AUTO_SW_AON_REG6X_RESERVED_10_Msk                                                                    (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG6X_RESERVED_10_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG6X_RESERVED_9_Pos                                                                     4U
+#define AON_REG_PAD_AUTO_SW_AON_REG6X_RESERVED_9_Msk                                                                     (0x7UL << AON_REG_PAD_AUTO_SW_AON_REG6X_RESERVED_9_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG6X_R_PADMUX_SPIC_SIO1_PUPDSD_AS_EN_Pos                                                7U
+#define AON_REG_PAD_AUTO_SW_AON_REG6X_R_PADMUX_SPIC_SIO1_PUPDSD_AS_EN_Msk                                                (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG6X_R_PADMUX_SPIC_SIO1_PUPDSD_AS_EN_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG6X_RESERVED_8_Pos                                                                     8U
+#define AON_REG_PAD_AUTO_SW_AON_REG6X_RESERVED_8_Msk                                                                     (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG6X_RESERVED_8_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG6X_R_PADMUX_SPIC_SIO0_PD_VAON_Pos                                                     9U
+#define AON_REG_PAD_AUTO_SW_AON_REG6X_R_PADMUX_SPIC_SIO0_PD_VAON_Msk                                                     (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG6X_R_PADMUX_SPIC_SIO0_PD_VAON_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG6X_R_PADMUX_SPIC_SIO0_PU_EN_VAON_Pos                                                  10U
+#define AON_REG_PAD_AUTO_SW_AON_REG6X_R_PADMUX_SPIC_SIO0_PU_EN_VAON_Msk                                                  (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG6X_R_PADMUX_SPIC_SIO0_PU_EN_VAON_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG6X_RESERVED_7_Pos                                                                     11U
+#define AON_REG_PAD_AUTO_SW_AON_REG6X_RESERVED_7_Msk                                                                     (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG6X_RESERVED_7_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG6X_RESERVED_6_Pos                                                                     12U
+#define AON_REG_PAD_AUTO_SW_AON_REG6X_RESERVED_6_Msk                                                                     (0x7UL << AON_REG_PAD_AUTO_SW_AON_REG6X_RESERVED_6_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG6X_R_PADMUX_SPIC_SIO0_PUPDSD_AS_EN_Pos                                                15U
+#define AON_REG_PAD_AUTO_SW_AON_REG6X_R_PADMUX_SPIC_SIO0_PUPDSD_AS_EN_Msk                                                (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG6X_R_PADMUX_SPIC_SIO0_PUPDSD_AS_EN_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG6X_RESERVED_5_Pos                                                                     16U
+#define AON_REG_PAD_AUTO_SW_AON_REG6X_RESERVED_5_Msk                                                                     (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG6X_RESERVED_5_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG6X_R_PADMUX_SPIC_SCK_PD_VAON_Pos                                                      17U
+#define AON_REG_PAD_AUTO_SW_AON_REG6X_R_PADMUX_SPIC_SCK_PD_VAON_Msk                                                      (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG6X_R_PADMUX_SPIC_SCK_PD_VAON_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG6X_R_PADMUX_SPIC_SCK_PU_EN_VAON_Pos                                                   18U
+#define AON_REG_PAD_AUTO_SW_AON_REG6X_R_PADMUX_SPIC_SCK_PU_EN_VAON_Msk                                                   (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG6X_R_PADMUX_SPIC_SCK_PU_EN_VAON_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG6X_RESERVED_4_Pos                                                                     19U
+#define AON_REG_PAD_AUTO_SW_AON_REG6X_RESERVED_4_Msk                                                                     (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG6X_RESERVED_4_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG6X_RESERVED_3_Pos                                                                     20U
+#define AON_REG_PAD_AUTO_SW_AON_REG6X_RESERVED_3_Msk                                                                     (0x7UL << AON_REG_PAD_AUTO_SW_AON_REG6X_RESERVED_3_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG6X_R_PADMUX_SPIC_SCK_PUPDSD_AS_EN_Pos                                                 23U
+#define AON_REG_PAD_AUTO_SW_AON_REG6X_R_PADMUX_SPIC_SCK_PUPDSD_AS_EN_Msk                                                 (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG6X_R_PADMUX_SPIC_SCK_PUPDSD_AS_EN_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG6X_RESERVED_2_Pos                                                                     24U
+#define AON_REG_PAD_AUTO_SW_AON_REG6X_RESERVED_2_Msk                                                                     (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG6X_RESERVED_2_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG6X_R_PADMUX_SPIC_CSN_PD_VAON_Pos                                                      25U
+#define AON_REG_PAD_AUTO_SW_AON_REG6X_R_PADMUX_SPIC_CSN_PD_VAON_Msk                                                      (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG6X_R_PADMUX_SPIC_CSN_PD_VAON_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG6X_R_PADMUX_SPIC_CSN_PU_EN_VAON_Pos                                                   26U
+#define AON_REG_PAD_AUTO_SW_AON_REG6X_R_PADMUX_SPIC_CSN_PU_EN_VAON_Msk                                                   (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG6X_R_PADMUX_SPIC_CSN_PU_EN_VAON_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG6X_RESERVED_1_Pos                                                                     27U
+#define AON_REG_PAD_AUTO_SW_AON_REG6X_RESERVED_1_Msk                                                                     (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG6X_RESERVED_1_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG6X_RESERVED_Pos                                                                       28U
+#define AON_REG_PAD_AUTO_SW_AON_REG6X_RESERVED_Msk                                                                       (0x7UL << AON_REG_PAD_AUTO_SW_AON_REG6X_RESERVED_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG6X_R_PADMUX_SPIC_CSN_PUPDSD_AS_EN_Pos                                                 31U
+#define AON_REG_PAD_AUTO_SW_AON_REG6X_R_PADMUX_SPIC_CSN_PUPDSD_AS_EN_Msk                                                 (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG6X_R_PADMUX_SPIC_CSN_PUPDSD_AS_EN_Pos)
+
+/* 0xEAC    0x4000_0eac
+    0       R/W     R_PADMUX_ALL_PUPDSD_AS_EN                                   1'b0
+    1       R/W     RESERVED_16                                                 1'b0
+    2       R/W     RESERVED_15                                                 1'b0
+    3       R/W     RESERVED_14                                                 1'b0
+    6:4     R/W     RESERVED_13                                                 3'd0
+    7       R/W     RESERVED_12                                                 1'b0
+    8       R/W     RESERVED_11                                                 1'b0
+    9       R/W     RESERVED_10                                                 1'b0
+    10      R/W     RESERVED_9                                                  1'b0
+    11      R/W     RESERVED_8                                                  1'b0
+    14:12   R/W     RESERVED_7                                                  3'd0
+    15      R/W     RESERVED_6                                                  1'b0
+    16      R/W     RESERVED_5                                                  1'b0
+    17      R/W     R_PADMUX_SPIC_SIO3_PD_VAON                                  1'b0
+    18      R/W     R_PADMUX_SPIC_SIO3_PU_EN_VAON                               1'b0
+    19      R/W     RESERVED_4                                                  1'b0
+    22:20   R/W     RESERVED_3                                                  3'd0
+    23      R/W     R_PADMUX_SPIC_SIO3_PUPDSD_AS_EN                             1'b0
+    24      R/W     RESERVED_2                                                  1'b0
+    25      R/W     R_PADMUX_SPIC_SIO2_PD_VAON                                  1'b0
+    26      R/W     R_PADMUX_SPIC_SIO2_PU_EN_VAON                               1'b0
+    27      R/W     RESERVED_1                                                  1'b0
+    30:28   R/W     RESERVED                                                    3'd0
+    31      R/W     R_PADMUX_SPIC_SIO2_PUPDSD_AS_EN                             1'b0
+ */
+typedef union _AON_REG_PAD_AUTO_SW_AON_REG7X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t R_PADMUX_ALL_PUPDSD_AS_EN: 1;
+        uint32_t RESERVED_16: 1;
+        uint32_t RESERVED_15: 1;
+        uint32_t RESERVED_14: 1;
+        uint32_t RESERVED_13: 3;
+        uint32_t RESERVED_12: 1;
+        uint32_t RESERVED_11: 1;
+        uint32_t RESERVED_10: 1;
+        uint32_t RESERVED_9: 1;
+        uint32_t RESERVED_8: 1;
+        uint32_t RESERVED_7: 3;
+        uint32_t RESERVED_6: 1;
+        uint32_t RESERVED_5: 1;
+        uint32_t R_PADMUX_SPIC_SIO3_PD_VAON: 1;
+        uint32_t R_PADMUX_SPIC_SIO3_PU_EN_VAON: 1;
+        uint32_t RESERVED_4: 1;
+        uint32_t RESERVED_3: 3;
+        uint32_t R_PADMUX_SPIC_SIO3_PUPDSD_AS_EN: 1;
+        uint32_t RESERVED_2: 1;
+        uint32_t R_PADMUX_SPIC_SIO2_PD_VAON: 1;
+        uint32_t R_PADMUX_SPIC_SIO2_PU_EN_VAON: 1;
+        uint32_t RESERVED_1: 1;
+        uint32_t RESERVED: 3;
+        uint32_t R_PADMUX_SPIC_SIO2_PUPDSD_AS_EN: 1;
+    };
+} AON_REG_PAD_AUTO_SW_AON_REG7X_TYPE;
+
+/*0x4000_0eac AON_REG_PAD_AUTO_SW_AON_REG7X*/
+#define AON_REG_PAD_AUTO_SW_AON_REG7X_R_PADMUX_ALL_PUPDSD_AS_EN_Pos                                                      0U
+#define AON_REG_PAD_AUTO_SW_AON_REG7X_R_PADMUX_ALL_PUPDSD_AS_EN_Msk                                                      (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG7X_R_PADMUX_ALL_PUPDSD_AS_EN_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG7X_RESERVED_16_Pos                                                                    1U
+#define AON_REG_PAD_AUTO_SW_AON_REG7X_RESERVED_16_Msk                                                                    (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG7X_RESERVED_16_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG7X_RESERVED_15_Pos                                                                    2U
+#define AON_REG_PAD_AUTO_SW_AON_REG7X_RESERVED_15_Msk                                                                    (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG7X_RESERVED_15_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG7X_RESERVED_14_Pos                                                                    3U
+#define AON_REG_PAD_AUTO_SW_AON_REG7X_RESERVED_14_Msk                                                                    (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG7X_RESERVED_14_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG7X_RESERVED_13_Pos                                                                    4U
+#define AON_REG_PAD_AUTO_SW_AON_REG7X_RESERVED_13_Msk                                                                    (0x7UL << AON_REG_PAD_AUTO_SW_AON_REG7X_RESERVED_13_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG7X_RESERVED_12_Pos                                                                    7U
+#define AON_REG_PAD_AUTO_SW_AON_REG7X_RESERVED_12_Msk                                                                    (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG7X_RESERVED_12_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG7X_RESERVED_11_Pos                                                                    8U
+#define AON_REG_PAD_AUTO_SW_AON_REG7X_RESERVED_11_Msk                                                                    (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG7X_RESERVED_11_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG7X_RESERVED_10_Pos                                                                    9U
+#define AON_REG_PAD_AUTO_SW_AON_REG7X_RESERVED_10_Msk                                                                    (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG7X_RESERVED_10_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG7X_RESERVED_9_Pos                                                                     10U
+#define AON_REG_PAD_AUTO_SW_AON_REG7X_RESERVED_9_Msk                                                                     (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG7X_RESERVED_9_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG7X_RESERVED_8_Pos                                                                     11U
+#define AON_REG_PAD_AUTO_SW_AON_REG7X_RESERVED_8_Msk                                                                     (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG7X_RESERVED_8_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG7X_RESERVED_7_Pos                                                                     12U
+#define AON_REG_PAD_AUTO_SW_AON_REG7X_RESERVED_7_Msk                                                                     (0x7UL << AON_REG_PAD_AUTO_SW_AON_REG7X_RESERVED_7_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG7X_RESERVED_6_Pos                                                                     15U
+#define AON_REG_PAD_AUTO_SW_AON_REG7X_RESERVED_6_Msk                                                                     (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG7X_RESERVED_6_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG7X_RESERVED_5_Pos                                                                     16U
+#define AON_REG_PAD_AUTO_SW_AON_REG7X_RESERVED_5_Msk                                                                     (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG7X_RESERVED_5_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG7X_R_PADMUX_SPIC_SIO3_PD_VAON_Pos                                                     17U
+#define AON_REG_PAD_AUTO_SW_AON_REG7X_R_PADMUX_SPIC_SIO3_PD_VAON_Msk                                                     (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG7X_R_PADMUX_SPIC_SIO3_PD_VAON_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG7X_R_PADMUX_SPIC_SIO3_PU_EN_VAON_Pos                                                  18U
+#define AON_REG_PAD_AUTO_SW_AON_REG7X_R_PADMUX_SPIC_SIO3_PU_EN_VAON_Msk                                                  (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG7X_R_PADMUX_SPIC_SIO3_PU_EN_VAON_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG7X_RESERVED_4_Pos                                                                     19U
+#define AON_REG_PAD_AUTO_SW_AON_REG7X_RESERVED_4_Msk                                                                     (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG7X_RESERVED_4_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG7X_RESERVED_3_Pos                                                                     20U
+#define AON_REG_PAD_AUTO_SW_AON_REG7X_RESERVED_3_Msk                                                                     (0x7UL << AON_REG_PAD_AUTO_SW_AON_REG7X_RESERVED_3_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG7X_R_PADMUX_SPIC_SIO3_PUPDSD_AS_EN_Pos                                                23U
+#define AON_REG_PAD_AUTO_SW_AON_REG7X_R_PADMUX_SPIC_SIO3_PUPDSD_AS_EN_Msk                                                (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG7X_R_PADMUX_SPIC_SIO3_PUPDSD_AS_EN_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG7X_RESERVED_2_Pos                                                                     24U
+#define AON_REG_PAD_AUTO_SW_AON_REG7X_RESERVED_2_Msk                                                                     (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG7X_RESERVED_2_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG7X_R_PADMUX_SPIC_SIO2_PD_VAON_Pos                                                     25U
+#define AON_REG_PAD_AUTO_SW_AON_REG7X_R_PADMUX_SPIC_SIO2_PD_VAON_Msk                                                     (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG7X_R_PADMUX_SPIC_SIO2_PD_VAON_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG7X_R_PADMUX_SPIC_SIO2_PU_EN_VAON_Pos                                                  26U
+#define AON_REG_PAD_AUTO_SW_AON_REG7X_R_PADMUX_SPIC_SIO2_PU_EN_VAON_Msk                                                  (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG7X_R_PADMUX_SPIC_SIO2_PU_EN_VAON_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG7X_RESERVED_1_Pos                                                                     27U
+#define AON_REG_PAD_AUTO_SW_AON_REG7X_RESERVED_1_Msk                                                                     (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG7X_RESERVED_1_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG7X_RESERVED_Pos                                                                       28U
+#define AON_REG_PAD_AUTO_SW_AON_REG7X_RESERVED_Msk                                                                       (0x7UL << AON_REG_PAD_AUTO_SW_AON_REG7X_RESERVED_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG7X_R_PADMUX_SPIC_SIO2_PUPDSD_AS_EN_Pos                                                31U
+#define AON_REG_PAD_AUTO_SW_AON_REG7X_R_PADMUX_SPIC_SIO2_PUPDSD_AS_EN_Msk                                                (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG7X_R_PADMUX_SPIC_SIO2_PUPDSD_AS_EN_Pos)
+
+/* 0xEB0    0x4000_0eb0
+    0       R/W     R_PADMUX_P0_AON_AS_EN_0                                     1'b0
+    1       R/W     R_PADMUX_P0_AON_AS_EN_1                                     1'b0
+    2       R/W     R_PADMUX_P0_AON_AS_EN_2                                     1'b0
+    3       R/W     R_PADMUX_P0_AON_AS_EN_3                                     1'b0
+    4       R/W     R_PADMUX_P0_AON_AS_EN_4                                     1'b0
+    5       R/W     R_PADMUX_P0_AON_AS_EN_5                                     1'b0
+    6       R/W     R_PADMUX_P0_AON_AS_EN_6                                     1'b0
+    7       R/W     R_PADMUX_P0_AON_AS_EN_7                                     1'b0
+    8       R/W     R_PADMUX_P1_AON_AS_EN_0                                     1'b0
+    9       R/W     R_PADMUX_P1_AON_AS_EN_1                                     1'b0
+    10      R/W     R_PADMUX_P1_AON_AS_EN_6                                     1'b0
+    11      R/W     R_PADMUX_P1_AON_AS_EN_7                                     1'b0
+    12      R/W     R_PADMUX_P2_AON_AS_EN_0                                     1'b0
+    13      R/W     R_PADMUX_P2_AON_AS_EN_1                                     1'b0
+    14      R/W     R_PADMUX_P2_AON_AS_EN_2                                     1'b0
+    15      R/W     R_PADMUX_P2_AON_AS_EN_3                                     1'b0
+    16      R/W     R_PADMUX_P2_AON_AS_EN_4                                     1'b0
+    17      R/W     R_PADMUX_P2_AON_AS_EN_5                                     1'b0
+    18      R/W     R_PADMUX_P2_AON_AS_EN_6                                     1'b0
+    19      R/W     R_PADMUX_P2_AON_AS_EN_7                                     1'b0
+    20      R/W     R_PADMUX_P3_AON_AS_EN_0                                     1'b0
+    21      R/W     R_PADMUX_P3_AON_AS_EN_1                                     1'b0
+    22      R/W     R_PADMUX_P3_AON_AS_EN_2                                     1'b0
+    23      R/W     R_PADMUX_P3_AON_AS_EN_3                                     1'b0
+    24      R/W     R_PADMUX_P3_AON_AS_EN_4                                     1'b0
+    25      R/W     R_PADMUX_P3_AON_AS_EN_5                                     1'b0
+    26      R/W     R_PADMUX_P3_AON_AS_EN_6                                     1'b0
+    27      R/W     R_PADMUX_P4_AON_AS_EN_0                                     1'b0
+    28      R/W     R_PADMUX_P4_AON_AS_EN_1                                     1'b0
+    29      R/W     R_PADMUX_P4_AON_AS_EN_2                                     1'b0
+    30      R/W     R_PADMUX_P4_AON_AS_EN_3                                     1'b0
+    31      R/W     R_PADMUX_MICBIAS_AON_AS_EN                                  1'b0
+ */
+typedef union _AON_REG_PAD_AUTO_SW_AON_REG8X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t R_PADMUX_P0_AON_AS_EN_0: 1;
+        uint32_t R_PADMUX_P0_AON_AS_EN_1: 1;
+        uint32_t R_PADMUX_P0_AON_AS_EN_2: 1;
+        uint32_t R_PADMUX_P0_AON_AS_EN_3: 1;
+        uint32_t R_PADMUX_P0_AON_AS_EN_4: 1;
+        uint32_t R_PADMUX_P0_AON_AS_EN_5: 1;
+        uint32_t R_PADMUX_P0_AON_AS_EN_6: 1;
+        uint32_t R_PADMUX_P0_AON_AS_EN_7: 1;
+        uint32_t R_PADMUX_P1_AON_AS_EN_0: 1;
+        uint32_t R_PADMUX_P1_AON_AS_EN_1: 1;
+        uint32_t R_PADMUX_P1_AON_AS_EN_6: 1;
+        uint32_t R_PADMUX_P1_AON_AS_EN_7: 1;
+        uint32_t R_PADMUX_P2_AON_AS_EN_0: 1;
+        uint32_t R_PADMUX_P2_AON_AS_EN_1: 1;
+        uint32_t R_PADMUX_P2_AON_AS_EN_2: 1;
+        uint32_t R_PADMUX_P2_AON_AS_EN_3: 1;
+        uint32_t R_PADMUX_P2_AON_AS_EN_4: 1;
+        uint32_t R_PADMUX_P2_AON_AS_EN_5: 1;
+        uint32_t R_PADMUX_P2_AON_AS_EN_6: 1;
+        uint32_t R_PADMUX_P2_AON_AS_EN_7: 1;
+        uint32_t R_PADMUX_P3_AON_AS_EN_0: 1;
+        uint32_t R_PADMUX_P3_AON_AS_EN_1: 1;
+        uint32_t R_PADMUX_P3_AON_AS_EN_2: 1;
+        uint32_t R_PADMUX_P3_AON_AS_EN_3: 1;
+        uint32_t R_PADMUX_P3_AON_AS_EN_4: 1;
+        uint32_t R_PADMUX_P3_AON_AS_EN_5: 1;
+        uint32_t R_PADMUX_P3_AON_AS_EN_6: 1;
+        uint32_t R_PADMUX_P4_AON_AS_EN_0: 1;
+        uint32_t R_PADMUX_P4_AON_AS_EN_1: 1;
+        uint32_t R_PADMUX_P4_AON_AS_EN_2: 1;
+        uint32_t R_PADMUX_P4_AON_AS_EN_3: 1;
+        uint32_t R_PADMUX_MICBIAS_AON_AS_EN: 1;
+    };
+} AON_REG_PAD_AUTO_SW_AON_REG8X_TYPE;
+
+/*0x4000_0eb0 AON_REG_PAD_AUTO_SW_AON_REG8X*/
+#define AON_REG_PAD_AUTO_SW_AON_REG8X_R_PADMUX_P0_AON_AS_EN_0_Pos                                                        0U
+#define AON_REG_PAD_AUTO_SW_AON_REG8X_R_PADMUX_P0_AON_AS_EN_0_Msk                                                        (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG8X_R_PADMUX_P0_AON_AS_EN_0_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG8X_R_PADMUX_P0_AON_AS_EN_1_Pos                                                        1U
+#define AON_REG_PAD_AUTO_SW_AON_REG8X_R_PADMUX_P0_AON_AS_EN_1_Msk                                                        (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG8X_R_PADMUX_P0_AON_AS_EN_1_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG8X_R_PADMUX_P0_AON_AS_EN_2_Pos                                                        2U
+#define AON_REG_PAD_AUTO_SW_AON_REG8X_R_PADMUX_P0_AON_AS_EN_2_Msk                                                        (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG8X_R_PADMUX_P0_AON_AS_EN_2_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG8X_R_PADMUX_P0_AON_AS_EN_3_Pos                                                        3U
+#define AON_REG_PAD_AUTO_SW_AON_REG8X_R_PADMUX_P0_AON_AS_EN_3_Msk                                                        (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG8X_R_PADMUX_P0_AON_AS_EN_3_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG8X_R_PADMUX_P0_AON_AS_EN_4_Pos                                                        4U
+#define AON_REG_PAD_AUTO_SW_AON_REG8X_R_PADMUX_P0_AON_AS_EN_4_Msk                                                        (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG8X_R_PADMUX_P0_AON_AS_EN_4_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG8X_R_PADMUX_P0_AON_AS_EN_5_Pos                                                        5U
+#define AON_REG_PAD_AUTO_SW_AON_REG8X_R_PADMUX_P0_AON_AS_EN_5_Msk                                                        (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG8X_R_PADMUX_P0_AON_AS_EN_5_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG8X_R_PADMUX_P0_AON_AS_EN_6_Pos                                                        6U
+#define AON_REG_PAD_AUTO_SW_AON_REG8X_R_PADMUX_P0_AON_AS_EN_6_Msk                                                        (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG8X_R_PADMUX_P0_AON_AS_EN_6_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG8X_R_PADMUX_P0_AON_AS_EN_7_Pos                                                        7U
+#define AON_REG_PAD_AUTO_SW_AON_REG8X_R_PADMUX_P0_AON_AS_EN_7_Msk                                                        (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG8X_R_PADMUX_P0_AON_AS_EN_7_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG8X_R_PADMUX_P1_AON_AS_EN_0_Pos                                                        8U
+#define AON_REG_PAD_AUTO_SW_AON_REG8X_R_PADMUX_P1_AON_AS_EN_0_Msk                                                        (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG8X_R_PADMUX_P1_AON_AS_EN_0_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG8X_R_PADMUX_P1_AON_AS_EN_1_Pos                                                        9U
+#define AON_REG_PAD_AUTO_SW_AON_REG8X_R_PADMUX_P1_AON_AS_EN_1_Msk                                                        (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG8X_R_PADMUX_P1_AON_AS_EN_1_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG8X_R_PADMUX_P1_AON_AS_EN_6_Pos                                                        10U
+#define AON_REG_PAD_AUTO_SW_AON_REG8X_R_PADMUX_P1_AON_AS_EN_6_Msk                                                        (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG8X_R_PADMUX_P1_AON_AS_EN_6_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG8X_R_PADMUX_P1_AON_AS_EN_7_Pos                                                        11U
+#define AON_REG_PAD_AUTO_SW_AON_REG8X_R_PADMUX_P1_AON_AS_EN_7_Msk                                                        (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG8X_R_PADMUX_P1_AON_AS_EN_7_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG8X_R_PADMUX_P2_AON_AS_EN_0_Pos                                                        12U
+#define AON_REG_PAD_AUTO_SW_AON_REG8X_R_PADMUX_P2_AON_AS_EN_0_Msk                                                        (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG8X_R_PADMUX_P2_AON_AS_EN_0_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG8X_R_PADMUX_P2_AON_AS_EN_1_Pos                                                        13U
+#define AON_REG_PAD_AUTO_SW_AON_REG8X_R_PADMUX_P2_AON_AS_EN_1_Msk                                                        (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG8X_R_PADMUX_P2_AON_AS_EN_1_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG8X_R_PADMUX_P2_AON_AS_EN_2_Pos                                                        14U
+#define AON_REG_PAD_AUTO_SW_AON_REG8X_R_PADMUX_P2_AON_AS_EN_2_Msk                                                        (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG8X_R_PADMUX_P2_AON_AS_EN_2_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG8X_R_PADMUX_P2_AON_AS_EN_3_Pos                                                        15U
+#define AON_REG_PAD_AUTO_SW_AON_REG8X_R_PADMUX_P2_AON_AS_EN_3_Msk                                                        (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG8X_R_PADMUX_P2_AON_AS_EN_3_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG8X_R_PADMUX_P2_AON_AS_EN_4_Pos                                                        16U
+#define AON_REG_PAD_AUTO_SW_AON_REG8X_R_PADMUX_P2_AON_AS_EN_4_Msk                                                        (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG8X_R_PADMUX_P2_AON_AS_EN_4_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG8X_R_PADMUX_P2_AON_AS_EN_5_Pos                                                        17U
+#define AON_REG_PAD_AUTO_SW_AON_REG8X_R_PADMUX_P2_AON_AS_EN_5_Msk                                                        (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG8X_R_PADMUX_P2_AON_AS_EN_5_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG8X_R_PADMUX_P2_AON_AS_EN_6_Pos                                                        18U
+#define AON_REG_PAD_AUTO_SW_AON_REG8X_R_PADMUX_P2_AON_AS_EN_6_Msk                                                        (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG8X_R_PADMUX_P2_AON_AS_EN_6_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG8X_R_PADMUX_P2_AON_AS_EN_7_Pos                                                        19U
+#define AON_REG_PAD_AUTO_SW_AON_REG8X_R_PADMUX_P2_AON_AS_EN_7_Msk                                                        (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG8X_R_PADMUX_P2_AON_AS_EN_7_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG8X_R_PADMUX_P3_AON_AS_EN_0_Pos                                                        20U
+#define AON_REG_PAD_AUTO_SW_AON_REG8X_R_PADMUX_P3_AON_AS_EN_0_Msk                                                        (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG8X_R_PADMUX_P3_AON_AS_EN_0_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG8X_R_PADMUX_P3_AON_AS_EN_1_Pos                                                        21U
+#define AON_REG_PAD_AUTO_SW_AON_REG8X_R_PADMUX_P3_AON_AS_EN_1_Msk                                                        (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG8X_R_PADMUX_P3_AON_AS_EN_1_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG8X_R_PADMUX_P3_AON_AS_EN_2_Pos                                                        22U
+#define AON_REG_PAD_AUTO_SW_AON_REG8X_R_PADMUX_P3_AON_AS_EN_2_Msk                                                        (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG8X_R_PADMUX_P3_AON_AS_EN_2_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG8X_R_PADMUX_P3_AON_AS_EN_3_Pos                                                        23U
+#define AON_REG_PAD_AUTO_SW_AON_REG8X_R_PADMUX_P3_AON_AS_EN_3_Msk                                                        (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG8X_R_PADMUX_P3_AON_AS_EN_3_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG8X_R_PADMUX_P3_AON_AS_EN_4_Pos                                                        24U
+#define AON_REG_PAD_AUTO_SW_AON_REG8X_R_PADMUX_P3_AON_AS_EN_4_Msk                                                        (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG8X_R_PADMUX_P3_AON_AS_EN_4_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG8X_R_PADMUX_P3_AON_AS_EN_5_Pos                                                        25U
+#define AON_REG_PAD_AUTO_SW_AON_REG8X_R_PADMUX_P3_AON_AS_EN_5_Msk                                                        (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG8X_R_PADMUX_P3_AON_AS_EN_5_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG8X_R_PADMUX_P3_AON_AS_EN_6_Pos                                                        26U
+#define AON_REG_PAD_AUTO_SW_AON_REG8X_R_PADMUX_P3_AON_AS_EN_6_Msk                                                        (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG8X_R_PADMUX_P3_AON_AS_EN_6_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG8X_R_PADMUX_P4_AON_AS_EN_0_Pos                                                        27U
+#define AON_REG_PAD_AUTO_SW_AON_REG8X_R_PADMUX_P4_AON_AS_EN_0_Msk                                                        (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG8X_R_PADMUX_P4_AON_AS_EN_0_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG8X_R_PADMUX_P4_AON_AS_EN_1_Pos                                                        28U
+#define AON_REG_PAD_AUTO_SW_AON_REG8X_R_PADMUX_P4_AON_AS_EN_1_Msk                                                        (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG8X_R_PADMUX_P4_AON_AS_EN_1_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG8X_R_PADMUX_P4_AON_AS_EN_2_Pos                                                        29U
+#define AON_REG_PAD_AUTO_SW_AON_REG8X_R_PADMUX_P4_AON_AS_EN_2_Msk                                                        (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG8X_R_PADMUX_P4_AON_AS_EN_2_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG8X_R_PADMUX_P4_AON_AS_EN_3_Pos                                                        30U
+#define AON_REG_PAD_AUTO_SW_AON_REG8X_R_PADMUX_P4_AON_AS_EN_3_Msk                                                        (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG8X_R_PADMUX_P4_AON_AS_EN_3_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG8X_R_PADMUX_MICBIAS_AON_AS_EN_Pos                                                     31U
+#define AON_REG_PAD_AUTO_SW_AON_REG8X_R_PADMUX_MICBIAS_AON_AS_EN_Msk                                                     (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG8X_R_PADMUX_MICBIAS_AON_AS_EN_Pos)
+
+/* 0xEB4    0x4000_0eb4
+    0       R/W     R_PADMUX_P5_AON_AS_EN_1                                     1'b0
+    1       R/W     R_PADMUX_P5_AON_AS_EN_2                                     1'b0
+    2       R/W     R_PADMUX_P6_AON_AS_EN_0                                     1'b0
+    3       R/W     R_PADMUX_P6_AON_AS_EN_1                                     1'b0
+    4       R/W     R_PADMUX_P6_AON_AS_EN_2                                     1'b0
+    5       R/W     R_PADMUX_P6_AON_AS_EN_3                                     1'b0
+    6       R/W     R_PADMUX_P6_AON_AS_EN_4                                     1'b0
+    7       R/W     R_PADMUX_P6_AON_AS_EN_5                                     1'b0
+    8       R/W     R_PADMUX_P6_AON_AS_EN_6                                     1'b0
+    9       R/W     R_PADMUX_P6_AON_AS_EN_7                                     1'b0
+    10      R/W     R_PADMUX_P7_AON_AS_EN_0                                     1'b0
+    11      R/W     R_PADMUX_P7_AON_AS_EN_1                                     1'b0
+    12      R/W     R_PADMUX_SPIC_CSN_AON_AS_EN                                 1'b0
+    13      R/W     R_PADMUX_SPIC_SCK_AON_AS_EN                                 1'b0
+    14      R/W     R_PADMUX_SPIC_SIO0_AON_AS_EN                                1'b0
+    15      R/W     R_PADMUX_SPIC_SIO1_AON_AS_EN                                1'b0
+    16      R/W     R_PADMUX_SPIC_SIO2_AON_AS_EN                                1'b0
+    17      R/W     R_PADMUX_SPIC_SIO3_AON_AS_EN                                1'b0
+    31:18   R/W     RESERVED                                                    14'h0
+ */
+typedef union _AON_REG_PAD_AUTO_SW_AON_REG9X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t R_PADMUX_P5_AON_AS_EN_1: 1;
+        uint32_t R_PADMUX_P5_AON_AS_EN_2: 1;
+        uint32_t R_PADMUX_P6_AON_AS_EN_0: 1;
+        uint32_t R_PADMUX_P6_AON_AS_EN_1: 1;
+        uint32_t R_PADMUX_P6_AON_AS_EN_2: 1;
+        uint32_t R_PADMUX_P6_AON_AS_EN_3: 1;
+        uint32_t R_PADMUX_P6_AON_AS_EN_4: 1;
+        uint32_t R_PADMUX_P6_AON_AS_EN_5: 1;
+        uint32_t R_PADMUX_P6_AON_AS_EN_6: 1;
+        uint32_t R_PADMUX_P6_AON_AS_EN_7: 1;
+        uint32_t R_PADMUX_P7_AON_AS_EN_0: 1;
+        uint32_t R_PADMUX_P7_AON_AS_EN_1: 1;
+        uint32_t R_PADMUX_SPIC_CSN_AON_AS_EN: 1;
+        uint32_t R_PADMUX_SPIC_SCK_AON_AS_EN: 1;
+        uint32_t R_PADMUX_SPIC_SIO0_AON_AS_EN: 1;
+        uint32_t R_PADMUX_SPIC_SIO1_AON_AS_EN: 1;
+        uint32_t R_PADMUX_SPIC_SIO2_AON_AS_EN: 1;
+        uint32_t R_PADMUX_SPIC_SIO3_AON_AS_EN: 1;
+        uint32_t RESERVED: 14;
+    };
+} AON_REG_PAD_AUTO_SW_AON_REG9X_TYPE;
+
+/*0x4000_0eb4 AON_REG_PAD_AUTO_SW_AON_REG9X*/
+#define AON_REG_PAD_AUTO_SW_AON_REG9X_R_PADMUX_P5_AON_AS_EN_1_Pos                                                        0U
+#define AON_REG_PAD_AUTO_SW_AON_REG9X_R_PADMUX_P5_AON_AS_EN_1_Msk                                                        (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG9X_R_PADMUX_P5_AON_AS_EN_1_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG9X_R_PADMUX_P5_AON_AS_EN_2_Pos                                                        1U
+#define AON_REG_PAD_AUTO_SW_AON_REG9X_R_PADMUX_P5_AON_AS_EN_2_Msk                                                        (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG9X_R_PADMUX_P5_AON_AS_EN_2_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG9X_R_PADMUX_P6_AON_AS_EN_0_Pos                                                        2U
+#define AON_REG_PAD_AUTO_SW_AON_REG9X_R_PADMUX_P6_AON_AS_EN_0_Msk                                                        (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG9X_R_PADMUX_P6_AON_AS_EN_0_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG9X_R_PADMUX_P6_AON_AS_EN_1_Pos                                                        3U
+#define AON_REG_PAD_AUTO_SW_AON_REG9X_R_PADMUX_P6_AON_AS_EN_1_Msk                                                        (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG9X_R_PADMUX_P6_AON_AS_EN_1_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG9X_R_PADMUX_P6_AON_AS_EN_2_Pos                                                        4U
+#define AON_REG_PAD_AUTO_SW_AON_REG9X_R_PADMUX_P6_AON_AS_EN_2_Msk                                                        (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG9X_R_PADMUX_P6_AON_AS_EN_2_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG9X_R_PADMUX_P6_AON_AS_EN_3_Pos                                                        5U
+#define AON_REG_PAD_AUTO_SW_AON_REG9X_R_PADMUX_P6_AON_AS_EN_3_Msk                                                        (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG9X_R_PADMUX_P6_AON_AS_EN_3_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG9X_R_PADMUX_P6_AON_AS_EN_4_Pos                                                        6U
+#define AON_REG_PAD_AUTO_SW_AON_REG9X_R_PADMUX_P6_AON_AS_EN_4_Msk                                                        (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG9X_R_PADMUX_P6_AON_AS_EN_4_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG9X_R_PADMUX_P6_AON_AS_EN_5_Pos                                                        7U
+#define AON_REG_PAD_AUTO_SW_AON_REG9X_R_PADMUX_P6_AON_AS_EN_5_Msk                                                        (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG9X_R_PADMUX_P6_AON_AS_EN_5_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG9X_R_PADMUX_P6_AON_AS_EN_6_Pos                                                        8U
+#define AON_REG_PAD_AUTO_SW_AON_REG9X_R_PADMUX_P6_AON_AS_EN_6_Msk                                                        (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG9X_R_PADMUX_P6_AON_AS_EN_6_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG9X_R_PADMUX_P6_AON_AS_EN_7_Pos                                                        9U
+#define AON_REG_PAD_AUTO_SW_AON_REG9X_R_PADMUX_P6_AON_AS_EN_7_Msk                                                        (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG9X_R_PADMUX_P6_AON_AS_EN_7_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG9X_R_PADMUX_P7_AON_AS_EN_0_Pos                                                        10U
+#define AON_REG_PAD_AUTO_SW_AON_REG9X_R_PADMUX_P7_AON_AS_EN_0_Msk                                                        (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG9X_R_PADMUX_P7_AON_AS_EN_0_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG9X_R_PADMUX_P7_AON_AS_EN_1_Pos                                                        11U
+#define AON_REG_PAD_AUTO_SW_AON_REG9X_R_PADMUX_P7_AON_AS_EN_1_Msk                                                        (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG9X_R_PADMUX_P7_AON_AS_EN_1_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG9X_R_PADMUX_SPIC_CSN_AON_AS_EN_Pos                                                    12U
+#define AON_REG_PAD_AUTO_SW_AON_REG9X_R_PADMUX_SPIC_CSN_AON_AS_EN_Msk                                                    (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG9X_R_PADMUX_SPIC_CSN_AON_AS_EN_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG9X_R_PADMUX_SPIC_SCK_AON_AS_EN_Pos                                                    13U
+#define AON_REG_PAD_AUTO_SW_AON_REG9X_R_PADMUX_SPIC_SCK_AON_AS_EN_Msk                                                    (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG9X_R_PADMUX_SPIC_SCK_AON_AS_EN_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG9X_R_PADMUX_SPIC_SIO0_AON_AS_EN_Pos                                                   14U
+#define AON_REG_PAD_AUTO_SW_AON_REG9X_R_PADMUX_SPIC_SIO0_AON_AS_EN_Msk                                                   (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG9X_R_PADMUX_SPIC_SIO0_AON_AS_EN_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG9X_R_PADMUX_SPIC_SIO1_AON_AS_EN_Pos                                                   15U
+#define AON_REG_PAD_AUTO_SW_AON_REG9X_R_PADMUX_SPIC_SIO1_AON_AS_EN_Msk                                                   (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG9X_R_PADMUX_SPIC_SIO1_AON_AS_EN_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG9X_R_PADMUX_SPIC_SIO2_AON_AS_EN_Pos                                                   16U
+#define AON_REG_PAD_AUTO_SW_AON_REG9X_R_PADMUX_SPIC_SIO2_AON_AS_EN_Msk                                                   (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG9X_R_PADMUX_SPIC_SIO2_AON_AS_EN_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG9X_R_PADMUX_SPIC_SIO3_AON_AS_EN_Pos                                                   17U
+#define AON_REG_PAD_AUTO_SW_AON_REG9X_R_PADMUX_SPIC_SIO3_AON_AS_EN_Msk                                                   (0x1UL << AON_REG_PAD_AUTO_SW_AON_REG9X_R_PADMUX_SPIC_SIO3_AON_AS_EN_Pos)
+
+#define AON_REG_PAD_AUTO_SW_AON_REG9X_RESERVED_Pos                                                                       18U
+#define AON_REG_PAD_AUTO_SW_AON_REG9X_RESERVED_Msk                                                                       (0x3FFFUL << AON_REG_PAD_AUTO_SW_AON_REG9X_RESERVED_Pos)
+
+/* 0xEC4    0x4000_0ec4
+    0       R/W     RESERVED_11                                                 1'b0
+    1       R/W     R_PADMUX_P0_PD_CORE_2                                       1'b0
+    2       R/W     R_PADMUX_P0_PU_EN_CORE_2                                    1'b0
+    3       R/W     RESERVED_10                                                 1'b0
+    7:4     R/W     RESERVED_9                                                  4'd0
+    8       R/W     RESERVED_8                                                  1'b0
+    9       R/W     R_PADMUX_P0_PD_CORE_4                                       1'b0
+    10      R/W     R_PADMUX_P0_PU_EN_CORE_4                                    1'b0
+    11      R/W     RESERVED_7                                                  1'b0
+    15:12   R/W     RESERVED_6                                                  4'd0
+    16      R/W     RESERVED_5                                                  1'b0
+    17      R/W     R_PADMUX_P0_PD_CORE_0                                       1'b0
+    18      R/W     R_PADMUX_P0_PU_EN_CORE_0                                    1'b0
+    19      R/W     RESERVED_4                                                  1'b0
+    23:20   R/W     RESERVED_3                                                  4'd0
+    24      R/W     RESERVED_2                                                  1'b0
+    25      R/W     R_PADMUX_P0_PD_CORE_1                                       1'b0
+    26      R/W     R_PADMUX_P0_PU_EN_CORE_1                                    1'b0
+    27      R/W     RESERVED_1                                                  1'b0
+    31:28   R/W     RESERVED                                                    4'd0
+ */
+typedef union _AON_REG_PAD_AUTO_SW_PON_REG0X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED_11: 1;
+        uint32_t R_PADMUX_P0_PD_CORE_2: 1;
+        uint32_t R_PADMUX_P0_PU_EN_CORE_2: 1;
+        uint32_t RESERVED_10: 1;
+        uint32_t RESERVED_9: 4;
+        uint32_t RESERVED_8: 1;
+        uint32_t R_PADMUX_P0_PD_CORE_4: 1;
+        uint32_t R_PADMUX_P0_PU_EN_CORE_4: 1;
+        uint32_t RESERVED_7: 1;
+        uint32_t RESERVED_6: 4;
+        uint32_t RESERVED_5: 1;
+        uint32_t R_PADMUX_P0_PD_CORE_0: 1;
+        uint32_t R_PADMUX_P0_PU_EN_CORE_0: 1;
+        uint32_t RESERVED_4: 1;
+        uint32_t RESERVED_3: 4;
+        uint32_t RESERVED_2: 1;
+        uint32_t R_PADMUX_P0_PD_CORE_1: 1;
+        uint32_t R_PADMUX_P0_PU_EN_CORE_1: 1;
+        uint32_t RESERVED_1: 1;
+        uint32_t RESERVED: 4;
+    };
+} AON_REG_PAD_AUTO_SW_PON_REG0X_TYPE;
+
+/*0x4000_0ec4 AON_REG_PAD_AUTO_SW_PON_REG0X*/
+#define AON_REG_PAD_AUTO_SW_PON_REG0X_RESERVED_11_Pos                                                                    0U
+#define AON_REG_PAD_AUTO_SW_PON_REG0X_RESERVED_11_Msk                                                                    (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG0X_RESERVED_11_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG0X_R_PADMUX_P0_PD_CORE_2_Pos                                                          1U
+#define AON_REG_PAD_AUTO_SW_PON_REG0X_R_PADMUX_P0_PD_CORE_2_Msk                                                          (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG0X_R_PADMUX_P0_PD_CORE_2_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG0X_R_PADMUX_P0_PU_EN_CORE_2_Pos                                                       2U
+#define AON_REG_PAD_AUTO_SW_PON_REG0X_R_PADMUX_P0_PU_EN_CORE_2_Msk                                                       (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG0X_R_PADMUX_P0_PU_EN_CORE_2_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG0X_RESERVED_10_Pos                                                                    3U
+#define AON_REG_PAD_AUTO_SW_PON_REG0X_RESERVED_10_Msk                                                                    (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG0X_RESERVED_10_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG0X_RESERVED_9_Pos                                                                     4U
+#define AON_REG_PAD_AUTO_SW_PON_REG0X_RESERVED_9_Msk                                                                     (0xFUL << AON_REG_PAD_AUTO_SW_PON_REG0X_RESERVED_9_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG0X_RESERVED_8_Pos                                                                     8U
+#define AON_REG_PAD_AUTO_SW_PON_REG0X_RESERVED_8_Msk                                                                     (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG0X_RESERVED_8_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG0X_R_PADMUX_P0_PD_CORE_4_Pos                                                          9U
+#define AON_REG_PAD_AUTO_SW_PON_REG0X_R_PADMUX_P0_PD_CORE_4_Msk                                                          (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG0X_R_PADMUX_P0_PD_CORE_4_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG0X_R_PADMUX_P0_PU_EN_CORE_4_Pos                                                       10U
+#define AON_REG_PAD_AUTO_SW_PON_REG0X_R_PADMUX_P0_PU_EN_CORE_4_Msk                                                       (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG0X_R_PADMUX_P0_PU_EN_CORE_4_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG0X_RESERVED_7_Pos                                                                     11U
+#define AON_REG_PAD_AUTO_SW_PON_REG0X_RESERVED_7_Msk                                                                     (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG0X_RESERVED_7_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG0X_RESERVED_6_Pos                                                                     12U
+#define AON_REG_PAD_AUTO_SW_PON_REG0X_RESERVED_6_Msk                                                                     (0xFUL << AON_REG_PAD_AUTO_SW_PON_REG0X_RESERVED_6_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG0X_RESERVED_5_Pos                                                                     16U
+#define AON_REG_PAD_AUTO_SW_PON_REG0X_RESERVED_5_Msk                                                                     (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG0X_RESERVED_5_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG0X_R_PADMUX_P0_PD_CORE_0_Pos                                                          17U
+#define AON_REG_PAD_AUTO_SW_PON_REG0X_R_PADMUX_P0_PD_CORE_0_Msk                                                          (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG0X_R_PADMUX_P0_PD_CORE_0_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG0X_R_PADMUX_P0_PU_EN_CORE_0_Pos                                                       18U
+#define AON_REG_PAD_AUTO_SW_PON_REG0X_R_PADMUX_P0_PU_EN_CORE_0_Msk                                                       (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG0X_R_PADMUX_P0_PU_EN_CORE_0_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG0X_RESERVED_4_Pos                                                                     19U
+#define AON_REG_PAD_AUTO_SW_PON_REG0X_RESERVED_4_Msk                                                                     (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG0X_RESERVED_4_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG0X_RESERVED_3_Pos                                                                     20U
+#define AON_REG_PAD_AUTO_SW_PON_REG0X_RESERVED_3_Msk                                                                     (0xFUL << AON_REG_PAD_AUTO_SW_PON_REG0X_RESERVED_3_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG0X_RESERVED_2_Pos                                                                     24U
+#define AON_REG_PAD_AUTO_SW_PON_REG0X_RESERVED_2_Msk                                                                     (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG0X_RESERVED_2_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG0X_R_PADMUX_P0_PD_CORE_1_Pos                                                          25U
+#define AON_REG_PAD_AUTO_SW_PON_REG0X_R_PADMUX_P0_PD_CORE_1_Msk                                                          (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG0X_R_PADMUX_P0_PD_CORE_1_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG0X_R_PADMUX_P0_PU_EN_CORE_1_Pos                                                       26U
+#define AON_REG_PAD_AUTO_SW_PON_REG0X_R_PADMUX_P0_PU_EN_CORE_1_Msk                                                       (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG0X_R_PADMUX_P0_PU_EN_CORE_1_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG0X_RESERVED_1_Pos                                                                     27U
+#define AON_REG_PAD_AUTO_SW_PON_REG0X_RESERVED_1_Msk                                                                     (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG0X_RESERVED_1_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG0X_RESERVED_Pos                                                                       28U
+#define AON_REG_PAD_AUTO_SW_PON_REG0X_RESERVED_Msk                                                                       (0xFUL << AON_REG_PAD_AUTO_SW_PON_REG0X_RESERVED_Pos)
+
+/* 0xEC8    0x4000_0ec8
+    0       R/W     RESERVED_11                                                 1'b0
+    1       R/W     R_PADMUX_P1_PD_CORE_0                                       1'b0
+    2       R/W     R_PADMUX_P1_PU_EN_CORE_0                                    1'b0
+    3       R/W     RESERVED_10                                                 1'b0
+    7:4     R/W     RESERVED_9                                                  4'd0
+    8       R/W     RESERVED_8                                                  1'b0
+    9       R/W     R_PADMUX_P1_PD_CORE_1                                       1'b0
+    10      R/W     R_PADMUX_P1_PU_EN_CORE_1                                    1'b0
+    11      R/W     RESERVED_7                                                  1'b0
+    15:12   R/W     RESERVED_6                                                  4'd0
+    16      R/W     RESERVED_5                                                  1'b0
+    17      R/W     R_PADMUX_P0_PD_CORE_5                                       1'b0
+    18      R/W     R_PADMUX_P0_PU_EN_CORE_5                                    1'b0
+    19      R/W     RESERVED_4                                                  1'b0
+    23:20   R/W     RESERVED_3                                                  4'd0
+    24      R/W     RESERVED_2                                                  1'b0
+    25      R/W     R_PADMUX_P0_PD_CORE_6                                       1'b0
+    26      R/W     R_PADMUX_P0_PU_EN_CORE_6                                    1'b0
+    27      R/W     RESERVED_1                                                  1'b0
+    31:28   R/W     RESERVED                                                    4'd0
+ */
+typedef union _AON_REG_PAD_AUTO_SW_PON_REG1X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED_11: 1;
+        uint32_t R_PADMUX_P1_PD_CORE_0: 1;
+        uint32_t R_PADMUX_P1_PU_EN_CORE_0: 1;
+        uint32_t RESERVED_10: 1;
+        uint32_t RESERVED_9: 4;
+        uint32_t RESERVED_8: 1;
+        uint32_t R_PADMUX_P1_PD_CORE_1: 1;
+        uint32_t R_PADMUX_P1_PU_EN_CORE_1: 1;
+        uint32_t RESERVED_7: 1;
+        uint32_t RESERVED_6: 4;
+        uint32_t RESERVED_5: 1;
+        uint32_t R_PADMUX_P0_PD_CORE_5: 1;
+        uint32_t R_PADMUX_P0_PU_EN_CORE_5: 1;
+        uint32_t RESERVED_4: 1;
+        uint32_t RESERVED_3: 4;
+        uint32_t RESERVED_2: 1;
+        uint32_t R_PADMUX_P0_PD_CORE_6: 1;
+        uint32_t R_PADMUX_P0_PU_EN_CORE_6: 1;
+        uint32_t RESERVED_1: 1;
+        uint32_t RESERVED: 4;
+    };
+} AON_REG_PAD_AUTO_SW_PON_REG1X_TYPE;
+
+/*0x4000_0ec8 AON_REG_PAD_AUTO_SW_PON_REG1X*/
+#define AON_REG_PAD_AUTO_SW_PON_REG1X_RESERVED_11_Pos                                                                    0U
+#define AON_REG_PAD_AUTO_SW_PON_REG1X_RESERVED_11_Msk                                                                    (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG1X_RESERVED_11_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG1X_R_PADMUX_P1_PD_CORE_0_Pos                                                          1U
+#define AON_REG_PAD_AUTO_SW_PON_REG1X_R_PADMUX_P1_PD_CORE_0_Msk                                                          (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG1X_R_PADMUX_P1_PD_CORE_0_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG1X_R_PADMUX_P1_PU_EN_CORE_0_Pos                                                       2U
+#define AON_REG_PAD_AUTO_SW_PON_REG1X_R_PADMUX_P1_PU_EN_CORE_0_Msk                                                       (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG1X_R_PADMUX_P1_PU_EN_CORE_0_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG1X_RESERVED_10_Pos                                                                    3U
+#define AON_REG_PAD_AUTO_SW_PON_REG1X_RESERVED_10_Msk                                                                    (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG1X_RESERVED_10_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG1X_RESERVED_9_Pos                                                                     4U
+#define AON_REG_PAD_AUTO_SW_PON_REG1X_RESERVED_9_Msk                                                                     (0xFUL << AON_REG_PAD_AUTO_SW_PON_REG1X_RESERVED_9_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG1X_RESERVED_8_Pos                                                                     8U
+#define AON_REG_PAD_AUTO_SW_PON_REG1X_RESERVED_8_Msk                                                                     (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG1X_RESERVED_8_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG1X_R_PADMUX_P1_PD_CORE_1_Pos                                                          9U
+#define AON_REG_PAD_AUTO_SW_PON_REG1X_R_PADMUX_P1_PD_CORE_1_Msk                                                          (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG1X_R_PADMUX_P1_PD_CORE_1_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG1X_R_PADMUX_P1_PU_EN_CORE_1_Pos                                                       10U
+#define AON_REG_PAD_AUTO_SW_PON_REG1X_R_PADMUX_P1_PU_EN_CORE_1_Msk                                                       (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG1X_R_PADMUX_P1_PU_EN_CORE_1_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG1X_RESERVED_7_Pos                                                                     11U
+#define AON_REG_PAD_AUTO_SW_PON_REG1X_RESERVED_7_Msk                                                                     (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG1X_RESERVED_7_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG1X_RESERVED_6_Pos                                                                     12U
+#define AON_REG_PAD_AUTO_SW_PON_REG1X_RESERVED_6_Msk                                                                     (0xFUL << AON_REG_PAD_AUTO_SW_PON_REG1X_RESERVED_6_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG1X_RESERVED_5_Pos                                                                     16U
+#define AON_REG_PAD_AUTO_SW_PON_REG1X_RESERVED_5_Msk                                                                     (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG1X_RESERVED_5_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG1X_R_PADMUX_P0_PD_CORE_5_Pos                                                          17U
+#define AON_REG_PAD_AUTO_SW_PON_REG1X_R_PADMUX_P0_PD_CORE_5_Msk                                                          (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG1X_R_PADMUX_P0_PD_CORE_5_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG1X_R_PADMUX_P0_PU_EN_CORE_5_Pos                                                       18U
+#define AON_REG_PAD_AUTO_SW_PON_REG1X_R_PADMUX_P0_PU_EN_CORE_5_Msk                                                       (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG1X_R_PADMUX_P0_PU_EN_CORE_5_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG1X_RESERVED_4_Pos                                                                     19U
+#define AON_REG_PAD_AUTO_SW_PON_REG1X_RESERVED_4_Msk                                                                     (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG1X_RESERVED_4_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG1X_RESERVED_3_Pos                                                                     20U
+#define AON_REG_PAD_AUTO_SW_PON_REG1X_RESERVED_3_Msk                                                                     (0xFUL << AON_REG_PAD_AUTO_SW_PON_REG1X_RESERVED_3_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG1X_RESERVED_2_Pos                                                                     24U
+#define AON_REG_PAD_AUTO_SW_PON_REG1X_RESERVED_2_Msk                                                                     (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG1X_RESERVED_2_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG1X_R_PADMUX_P0_PD_CORE_6_Pos                                                          25U
+#define AON_REG_PAD_AUTO_SW_PON_REG1X_R_PADMUX_P0_PD_CORE_6_Msk                                                          (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG1X_R_PADMUX_P0_PD_CORE_6_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG1X_R_PADMUX_P0_PU_EN_CORE_6_Pos                                                       26U
+#define AON_REG_PAD_AUTO_SW_PON_REG1X_R_PADMUX_P0_PU_EN_CORE_6_Msk                                                       (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG1X_R_PADMUX_P0_PU_EN_CORE_6_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG1X_RESERVED_1_Pos                                                                     27U
+#define AON_REG_PAD_AUTO_SW_PON_REG1X_RESERVED_1_Msk                                                                     (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG1X_RESERVED_1_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG1X_RESERVED_Pos                                                                       28U
+#define AON_REG_PAD_AUTO_SW_PON_REG1X_RESERVED_Msk                                                                       (0xFUL << AON_REG_PAD_AUTO_SW_PON_REG1X_RESERVED_Pos)
+
+/* 0xECC    0x4000_0ecc
+    0       R/W     RESERVED_11                                                 1'b0
+    1       R/W     R_PADMUX_P2_PD_CORE_2                                       1'b0
+    2       R/W     R_PADMUX_P2_PU_EN_CORE_2                                    1'b0
+    3       R/W     RESERVED_10                                                 1'b0
+    7:4     R/W     RESERVED_9                                                  4'd0
+    8       R/W     RESERVED_8                                                  1'b0
+    9       R/W     R_PADMUX_P2_PD_CORE_3                                       1'b0
+    10      R/W     R_PADMUX_P2_PU_EN_CORE_3                                    1'b0
+    11      R/W     RESERVED_7                                                  1'b0
+    15:12   R/W     RESERVED_6                                                  4'd0
+    16      R/W     RESERVED_5                                                  1'b0
+    17      R/W     R_PADMUX_P2_PD_CORE_0                                       1'b0
+    18      R/W     R_PADMUX_P2_PU_EN_CORE_0                                    1'b0
+    19      R/W     RESERVED_4                                                  1'b0
+    23:20   R/W     RESERVED_3                                                  4'd0
+    24      R/W     RESERVED_2                                                  1'b0
+    25      R/W     R_PADMUX_P2_PD_CORE_1                                       1'b0
+    26      R/W     R_PADMUX_P2_PU_EN_CORE_1                                    1'b0
+    27      R/W     RESERVED_1                                                  1'b0
+    31:28   R/W     RESERVED                                                    4'd0
+ */
+typedef union _AON_REG_PAD_AUTO_SW_PON_REG2X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED_11: 1;
+        uint32_t R_PADMUX_P2_PD_CORE_2: 1;
+        uint32_t R_PADMUX_P2_PU_EN_CORE_2: 1;
+        uint32_t RESERVED_10: 1;
+        uint32_t RESERVED_9: 4;
+        uint32_t RESERVED_8: 1;
+        uint32_t R_PADMUX_P2_PD_CORE_3: 1;
+        uint32_t R_PADMUX_P2_PU_EN_CORE_3: 1;
+        uint32_t RESERVED_7: 1;
+        uint32_t RESERVED_6: 4;
+        uint32_t RESERVED_5: 1;
+        uint32_t R_PADMUX_P2_PD_CORE_0: 1;
+        uint32_t R_PADMUX_P2_PU_EN_CORE_0: 1;
+        uint32_t RESERVED_4: 1;
+        uint32_t RESERVED_3: 4;
+        uint32_t RESERVED_2: 1;
+        uint32_t R_PADMUX_P2_PD_CORE_1: 1;
+        uint32_t R_PADMUX_P2_PU_EN_CORE_1: 1;
+        uint32_t RESERVED_1: 1;
+        uint32_t RESERVED: 4;
+    };
+} AON_REG_PAD_AUTO_SW_PON_REG2X_TYPE;
+
+/*0x4000_0ecc AON_REG_PAD_AUTO_SW_PON_REG2X*/
+#define AON_REG_PAD_AUTO_SW_PON_REG2X_RESERVED_11_Pos                                                                    0U
+#define AON_REG_PAD_AUTO_SW_PON_REG2X_RESERVED_11_Msk                                                                    (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG2X_RESERVED_11_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG2X_R_PADMUX_P2_PD_CORE_2_Pos                                                          1U
+#define AON_REG_PAD_AUTO_SW_PON_REG2X_R_PADMUX_P2_PD_CORE_2_Msk                                                          (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG2X_R_PADMUX_P2_PD_CORE_2_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG2X_R_PADMUX_P2_PU_EN_CORE_2_Pos                                                       2U
+#define AON_REG_PAD_AUTO_SW_PON_REG2X_R_PADMUX_P2_PU_EN_CORE_2_Msk                                                       (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG2X_R_PADMUX_P2_PU_EN_CORE_2_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG2X_RESERVED_10_Pos                                                                    3U
+#define AON_REG_PAD_AUTO_SW_PON_REG2X_RESERVED_10_Msk                                                                    (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG2X_RESERVED_10_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG2X_RESERVED_9_Pos                                                                     4U
+#define AON_REG_PAD_AUTO_SW_PON_REG2X_RESERVED_9_Msk                                                                     (0xFUL << AON_REG_PAD_AUTO_SW_PON_REG2X_RESERVED_9_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG2X_RESERVED_8_Pos                                                                     8U
+#define AON_REG_PAD_AUTO_SW_PON_REG2X_RESERVED_8_Msk                                                                     (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG2X_RESERVED_8_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG2X_R_PADMUX_P2_PD_CORE_3_Pos                                                          9U
+#define AON_REG_PAD_AUTO_SW_PON_REG2X_R_PADMUX_P2_PD_CORE_3_Msk                                                          (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG2X_R_PADMUX_P2_PD_CORE_3_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG2X_R_PADMUX_P2_PU_EN_CORE_3_Pos                                                       10U
+#define AON_REG_PAD_AUTO_SW_PON_REG2X_R_PADMUX_P2_PU_EN_CORE_3_Msk                                                       (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG2X_R_PADMUX_P2_PU_EN_CORE_3_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG2X_RESERVED_7_Pos                                                                     11U
+#define AON_REG_PAD_AUTO_SW_PON_REG2X_RESERVED_7_Msk                                                                     (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG2X_RESERVED_7_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG2X_RESERVED_6_Pos                                                                     12U
+#define AON_REG_PAD_AUTO_SW_PON_REG2X_RESERVED_6_Msk                                                                     (0xFUL << AON_REG_PAD_AUTO_SW_PON_REG2X_RESERVED_6_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG2X_RESERVED_5_Pos                                                                     16U
+#define AON_REG_PAD_AUTO_SW_PON_REG2X_RESERVED_5_Msk                                                                     (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG2X_RESERVED_5_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG2X_R_PADMUX_P2_PD_CORE_0_Pos                                                          17U
+#define AON_REG_PAD_AUTO_SW_PON_REG2X_R_PADMUX_P2_PD_CORE_0_Msk                                                          (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG2X_R_PADMUX_P2_PD_CORE_0_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG2X_R_PADMUX_P2_PU_EN_CORE_0_Pos                                                       18U
+#define AON_REG_PAD_AUTO_SW_PON_REG2X_R_PADMUX_P2_PU_EN_CORE_0_Msk                                                       (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG2X_R_PADMUX_P2_PU_EN_CORE_0_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG2X_RESERVED_4_Pos                                                                     19U
+#define AON_REG_PAD_AUTO_SW_PON_REG2X_RESERVED_4_Msk                                                                     (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG2X_RESERVED_4_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG2X_RESERVED_3_Pos                                                                     20U
+#define AON_REG_PAD_AUTO_SW_PON_REG2X_RESERVED_3_Msk                                                                     (0xFUL << AON_REG_PAD_AUTO_SW_PON_REG2X_RESERVED_3_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG2X_RESERVED_2_Pos                                                                     24U
+#define AON_REG_PAD_AUTO_SW_PON_REG2X_RESERVED_2_Msk                                                                     (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG2X_RESERVED_2_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG2X_R_PADMUX_P2_PD_CORE_1_Pos                                                          25U
+#define AON_REG_PAD_AUTO_SW_PON_REG2X_R_PADMUX_P2_PD_CORE_1_Msk                                                          (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG2X_R_PADMUX_P2_PD_CORE_1_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG2X_R_PADMUX_P2_PU_EN_CORE_1_Pos                                                       26U
+#define AON_REG_PAD_AUTO_SW_PON_REG2X_R_PADMUX_P2_PU_EN_CORE_1_Msk                                                       (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG2X_R_PADMUX_P2_PU_EN_CORE_1_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG2X_RESERVED_1_Pos                                                                     27U
+#define AON_REG_PAD_AUTO_SW_PON_REG2X_RESERVED_1_Msk                                                                     (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG2X_RESERVED_1_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG2X_RESERVED_Pos                                                                       28U
+#define AON_REG_PAD_AUTO_SW_PON_REG2X_RESERVED_Msk                                                                       (0xFUL << AON_REG_PAD_AUTO_SW_PON_REG2X_RESERVED_Pos)
+
+/* 0xED0    0x4000_0ed0
+    0       R/W     RESERVED_11                                                 1'b0
+    1       R/W     R_PADMUX_P2_PD_CORE_6                                       1'b0
+    2       R/W     R_PADMUX_P2_PU_EN_CORE_6                                    1'b0
+    3       R/W     RESERVED_10                                                 1'b0
+    7:4     R/W     RESERVED_9                                                  4'd0
+    8       R/W     RESERVED_8                                                  1'b0
+    9       R/W     R_PADMUX_P2_PD_CORE_7                                       1'b0
+    10      R/W     R_PADMUX_P2_PU_EN_CORE_7                                    1'b0
+    11      R/W     RESERVED_7                                                  1'b0
+    15:12   R/W     RESERVED_6                                                  4'd0
+    16      R/W     RESERVED_5                                                  1'b0
+    17      R/W     R_PADMUX_P2_PD_CORE_4                                       1'b0
+    18      R/W     R_PADMUX_P2_PU_EN_CORE_4                                    1'b0
+    19      R/W     RESERVED_4                                                  1'b0
+    23:20   R/W     RESERVED_3                                                  4'd0
+    24      R/W     RESERVED_2                                                  1'b0
+    25      R/W     R_PADMUX_P2_PD_CORE_5                                       1'b0
+    26      R/W     R_PADMUX_P2_PU_EN_CORE_5                                    1'b0
+    27      R/W     RESERVED_1                                                  1'b0
+    31:28   R/W     RESERVED                                                    4'd0
+ */
+typedef union _AON_REG_PAD_AUTO_SW_PON_REG3X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED_11: 1;
+        uint32_t R_PADMUX_P2_PD_CORE_6: 1;
+        uint32_t R_PADMUX_P2_PU_EN_CORE_6: 1;
+        uint32_t RESERVED_10: 1;
+        uint32_t RESERVED_9: 4;
+        uint32_t RESERVED_8: 1;
+        uint32_t R_PADMUX_P2_PD_CORE_7: 1;
+        uint32_t R_PADMUX_P2_PU_EN_CORE_7: 1;
+        uint32_t RESERVED_7: 1;
+        uint32_t RESERVED_6: 4;
+        uint32_t RESERVED_5: 1;
+        uint32_t R_PADMUX_P2_PD_CORE_4: 1;
+        uint32_t R_PADMUX_P2_PU_EN_CORE_4: 1;
+        uint32_t RESERVED_4: 1;
+        uint32_t RESERVED_3: 4;
+        uint32_t RESERVED_2: 1;
+        uint32_t R_PADMUX_P2_PD_CORE_5: 1;
+        uint32_t R_PADMUX_P2_PU_EN_CORE_5: 1;
+        uint32_t RESERVED_1: 1;
+        uint32_t RESERVED: 4;
+    };
+} AON_REG_PAD_AUTO_SW_PON_REG3X_TYPE;
+
+/*0x4000_0ed0 AON_REG_PAD_AUTO_SW_PON_REG3X*/
+#define AON_REG_PAD_AUTO_SW_PON_REG3X_RESERVED_11_Pos                                                                    0U
+#define AON_REG_PAD_AUTO_SW_PON_REG3X_RESERVED_11_Msk                                                                    (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG3X_RESERVED_11_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG3X_R_PADMUX_P2_PD_CORE_6_Pos                                                          1U
+#define AON_REG_PAD_AUTO_SW_PON_REG3X_R_PADMUX_P2_PD_CORE_6_Msk                                                          (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG3X_R_PADMUX_P2_PD_CORE_6_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG3X_R_PADMUX_P2_PU_EN_CORE_6_Pos                                                       2U
+#define AON_REG_PAD_AUTO_SW_PON_REG3X_R_PADMUX_P2_PU_EN_CORE_6_Msk                                                       (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG3X_R_PADMUX_P2_PU_EN_CORE_6_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG3X_RESERVED_10_Pos                                                                    3U
+#define AON_REG_PAD_AUTO_SW_PON_REG3X_RESERVED_10_Msk                                                                    (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG3X_RESERVED_10_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG3X_RESERVED_9_Pos                                                                     4U
+#define AON_REG_PAD_AUTO_SW_PON_REG3X_RESERVED_9_Msk                                                                     (0xFUL << AON_REG_PAD_AUTO_SW_PON_REG3X_RESERVED_9_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG3X_RESERVED_8_Pos                                                                     8U
+#define AON_REG_PAD_AUTO_SW_PON_REG3X_RESERVED_8_Msk                                                                     (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG3X_RESERVED_8_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG3X_R_PADMUX_P2_PD_CORE_7_Pos                                                          9U
+#define AON_REG_PAD_AUTO_SW_PON_REG3X_R_PADMUX_P2_PD_CORE_7_Msk                                                          (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG3X_R_PADMUX_P2_PD_CORE_7_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG3X_R_PADMUX_P2_PU_EN_CORE_7_Pos                                                       10U
+#define AON_REG_PAD_AUTO_SW_PON_REG3X_R_PADMUX_P2_PU_EN_CORE_7_Msk                                                       (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG3X_R_PADMUX_P2_PU_EN_CORE_7_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG3X_RESERVED_7_Pos                                                                     11U
+#define AON_REG_PAD_AUTO_SW_PON_REG3X_RESERVED_7_Msk                                                                     (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG3X_RESERVED_7_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG3X_RESERVED_6_Pos                                                                     12U
+#define AON_REG_PAD_AUTO_SW_PON_REG3X_RESERVED_6_Msk                                                                     (0xFUL << AON_REG_PAD_AUTO_SW_PON_REG3X_RESERVED_6_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG3X_RESERVED_5_Pos                                                                     16U
+#define AON_REG_PAD_AUTO_SW_PON_REG3X_RESERVED_5_Msk                                                                     (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG3X_RESERVED_5_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG3X_R_PADMUX_P2_PD_CORE_4_Pos                                                          17U
+#define AON_REG_PAD_AUTO_SW_PON_REG3X_R_PADMUX_P2_PD_CORE_4_Msk                                                          (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG3X_R_PADMUX_P2_PD_CORE_4_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG3X_R_PADMUX_P2_PU_EN_CORE_4_Pos                                                       18U
+#define AON_REG_PAD_AUTO_SW_PON_REG3X_R_PADMUX_P2_PU_EN_CORE_4_Msk                                                       (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG3X_R_PADMUX_P2_PU_EN_CORE_4_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG3X_RESERVED_4_Pos                                                                     19U
+#define AON_REG_PAD_AUTO_SW_PON_REG3X_RESERVED_4_Msk                                                                     (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG3X_RESERVED_4_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG3X_RESERVED_3_Pos                                                                     20U
+#define AON_REG_PAD_AUTO_SW_PON_REG3X_RESERVED_3_Msk                                                                     (0xFUL << AON_REG_PAD_AUTO_SW_PON_REG3X_RESERVED_3_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG3X_RESERVED_2_Pos                                                                     24U
+#define AON_REG_PAD_AUTO_SW_PON_REG3X_RESERVED_2_Msk                                                                     (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG3X_RESERVED_2_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG3X_R_PADMUX_P2_PD_CORE_5_Pos                                                          25U
+#define AON_REG_PAD_AUTO_SW_PON_REG3X_R_PADMUX_P2_PD_CORE_5_Msk                                                          (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG3X_R_PADMUX_P2_PD_CORE_5_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG3X_R_PADMUX_P2_PU_EN_CORE_5_Pos                                                       26U
+#define AON_REG_PAD_AUTO_SW_PON_REG3X_R_PADMUX_P2_PU_EN_CORE_5_Msk                                                       (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG3X_R_PADMUX_P2_PU_EN_CORE_5_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG3X_RESERVED_1_Pos                                                                     27U
+#define AON_REG_PAD_AUTO_SW_PON_REG3X_RESERVED_1_Msk                                                                     (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG3X_RESERVED_1_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG3X_RESERVED_Pos                                                                       28U
+#define AON_REG_PAD_AUTO_SW_PON_REG3X_RESERVED_Msk                                                                       (0xFUL << AON_REG_PAD_AUTO_SW_PON_REG3X_RESERVED_Pos)
+
+/* 0xED4    0x4000_0ed4
+    0       R/W     RESERVED_11                                                 1'b0
+    1       R/W     R_PADMUX_P3_PD_CORE_2                                       1'b0
+    2       R/W     R_PADMUX_P3_PU_EN_CORE_2                                    1'b0
+    3       R/W     RESERVED_10                                                 1'b0
+    7:4     R/W     RESERVED_9                                                  4'd0
+    8       R/W     RESERVED_8                                                  1'b0
+    9       R/W     R_PADMUX_P3_PD_CORE_3                                       1'b0
+    10      R/W     R_PADMUX_P3_PU_EN_CORE_3                                    1'b0
+    11      R/W     RESERVED_7                                                  1'b0
+    15:12   R/W     RESERVED_6                                                  4'd0
+    16      R/W     RESERVED_5                                                  1'b0
+    17      R/W     R_PADMUX_P3_PD_CORE_0                                       1'b0
+    18      R/W     R_PADMUX_P3_PU_EN_CORE_0                                    1'b0
+    19      R/W     RESERVED_4                                                  1'b0
+    23:20   R/W     RESERVED_3                                                  4'd0
+    24      R/W     RESERVED_2                                                  1'b0
+    25      R/W     R_PADMUX_P3_PD_CORE_1                                       1'b0
+    26      R/W     R_PADMUX_P3_PU_EN_CORE_1                                    1'b0
+    27      R/W     RESERVED_1                                                  1'b0
+    31:28   R/W     RESERVED                                                    4'd0
+ */
+typedef union _AON_REG_PAD_AUTO_SW_PON_REG4X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED_11: 1;
+        uint32_t R_PADMUX_P3_PD_CORE_2: 1;
+        uint32_t R_PADMUX_P3_PU_EN_CORE_2: 1;
+        uint32_t RESERVED_10: 1;
+        uint32_t RESERVED_9: 4;
+        uint32_t RESERVED_8: 1;
+        uint32_t R_PADMUX_P3_PD_CORE_3: 1;
+        uint32_t R_PADMUX_P3_PU_EN_CORE_3: 1;
+        uint32_t RESERVED_7: 1;
+        uint32_t RESERVED_6: 4;
+        uint32_t RESERVED_5: 1;
+        uint32_t R_PADMUX_P3_PD_CORE_0: 1;
+        uint32_t R_PADMUX_P3_PU_EN_CORE_0: 1;
+        uint32_t RESERVED_4: 1;
+        uint32_t RESERVED_3: 4;
+        uint32_t RESERVED_2: 1;
+        uint32_t R_PADMUX_P3_PD_CORE_1: 1;
+        uint32_t R_PADMUX_P3_PU_EN_CORE_1: 1;
+        uint32_t RESERVED_1: 1;
+        uint32_t RESERVED: 4;
+    };
+} AON_REG_PAD_AUTO_SW_PON_REG4X_TYPE;
+
+/*0x4000_0ed4 AON_REG_PAD_AUTO_SW_PON_REG4X*/
+#define AON_REG_PAD_AUTO_SW_PON_REG4X_RESERVED_11_Pos                                                                    0U
+#define AON_REG_PAD_AUTO_SW_PON_REG4X_RESERVED_11_Msk                                                                    (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG4X_RESERVED_11_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG4X_R_PADMUX_P3_PD_CORE_2_Pos                                                          1U
+#define AON_REG_PAD_AUTO_SW_PON_REG4X_R_PADMUX_P3_PD_CORE_2_Msk                                                          (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG4X_R_PADMUX_P3_PD_CORE_2_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG4X_R_PADMUX_P3_PU_EN_CORE_2_Pos                                                       2U
+#define AON_REG_PAD_AUTO_SW_PON_REG4X_R_PADMUX_P3_PU_EN_CORE_2_Msk                                                       (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG4X_R_PADMUX_P3_PU_EN_CORE_2_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG4X_RESERVED_10_Pos                                                                    3U
+#define AON_REG_PAD_AUTO_SW_PON_REG4X_RESERVED_10_Msk                                                                    (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG4X_RESERVED_10_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG4X_RESERVED_9_Pos                                                                     4U
+#define AON_REG_PAD_AUTO_SW_PON_REG4X_RESERVED_9_Msk                                                                     (0xFUL << AON_REG_PAD_AUTO_SW_PON_REG4X_RESERVED_9_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG4X_RESERVED_8_Pos                                                                     8U
+#define AON_REG_PAD_AUTO_SW_PON_REG4X_RESERVED_8_Msk                                                                     (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG4X_RESERVED_8_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG4X_R_PADMUX_P3_PD_CORE_3_Pos                                                          9U
+#define AON_REG_PAD_AUTO_SW_PON_REG4X_R_PADMUX_P3_PD_CORE_3_Msk                                                          (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG4X_R_PADMUX_P3_PD_CORE_3_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG4X_R_PADMUX_P3_PU_EN_CORE_3_Pos                                                       10U
+#define AON_REG_PAD_AUTO_SW_PON_REG4X_R_PADMUX_P3_PU_EN_CORE_3_Msk                                                       (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG4X_R_PADMUX_P3_PU_EN_CORE_3_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG4X_RESERVED_7_Pos                                                                     11U
+#define AON_REG_PAD_AUTO_SW_PON_REG4X_RESERVED_7_Msk                                                                     (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG4X_RESERVED_7_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG4X_RESERVED_6_Pos                                                                     12U
+#define AON_REG_PAD_AUTO_SW_PON_REG4X_RESERVED_6_Msk                                                                     (0xFUL << AON_REG_PAD_AUTO_SW_PON_REG4X_RESERVED_6_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG4X_RESERVED_5_Pos                                                                     16U
+#define AON_REG_PAD_AUTO_SW_PON_REG4X_RESERVED_5_Msk                                                                     (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG4X_RESERVED_5_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG4X_R_PADMUX_P3_PD_CORE_0_Pos                                                          17U
+#define AON_REG_PAD_AUTO_SW_PON_REG4X_R_PADMUX_P3_PD_CORE_0_Msk                                                          (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG4X_R_PADMUX_P3_PD_CORE_0_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG4X_R_PADMUX_P3_PU_EN_CORE_0_Pos                                                       18U
+#define AON_REG_PAD_AUTO_SW_PON_REG4X_R_PADMUX_P3_PU_EN_CORE_0_Msk                                                       (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG4X_R_PADMUX_P3_PU_EN_CORE_0_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG4X_RESERVED_4_Pos                                                                     19U
+#define AON_REG_PAD_AUTO_SW_PON_REG4X_RESERVED_4_Msk                                                                     (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG4X_RESERVED_4_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG4X_RESERVED_3_Pos                                                                     20U
+#define AON_REG_PAD_AUTO_SW_PON_REG4X_RESERVED_3_Msk                                                                     (0xFUL << AON_REG_PAD_AUTO_SW_PON_REG4X_RESERVED_3_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG4X_RESERVED_2_Pos                                                                     24U
+#define AON_REG_PAD_AUTO_SW_PON_REG4X_RESERVED_2_Msk                                                                     (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG4X_RESERVED_2_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG4X_R_PADMUX_P3_PD_CORE_1_Pos                                                          25U
+#define AON_REG_PAD_AUTO_SW_PON_REG4X_R_PADMUX_P3_PD_CORE_1_Msk                                                          (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG4X_R_PADMUX_P3_PD_CORE_1_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG4X_R_PADMUX_P3_PU_EN_CORE_1_Pos                                                       26U
+#define AON_REG_PAD_AUTO_SW_PON_REG4X_R_PADMUX_P3_PU_EN_CORE_1_Msk                                                       (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG4X_R_PADMUX_P3_PU_EN_CORE_1_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG4X_RESERVED_1_Pos                                                                     27U
+#define AON_REG_PAD_AUTO_SW_PON_REG4X_RESERVED_1_Msk                                                                     (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG4X_RESERVED_1_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG4X_RESERVED_Pos                                                                       28U
+#define AON_REG_PAD_AUTO_SW_PON_REG4X_RESERVED_Msk                                                                       (0xFUL << AON_REG_PAD_AUTO_SW_PON_REG4X_RESERVED_Pos)
+
+/* 0xED8    0x4000_0ed8
+    0       R/W     RESERVED_11                                                 1'b0
+    1       R/W     R_PADMUX_P4_PD_CORE_2                                       1'b0
+    2       R/W     R_PADMUX_P4_PU_EN_CORE_2                                    1'b0
+    3       R/W     RESERVED_10                                                 1'b0
+    7:4     R/W     RESERVED_9                                                  4'd0
+    8       R/W     RESERVED_8                                                  1'b0
+    9       R/W     R_PADMUX_P4_PD_CORE_3                                       1'b0
+    10      R/W     R_PADMUX_P4_PU_EN_CORE_3                                    1'b0
+    11      R/W     RESERVED_7                                                  1'b0
+    15:12   R/W     RESERVED_6                                                  4'd0
+    16      R/W     RESERVED_5                                                  1'b0
+    17      R/W     R_PADMUX_P4_PD_CORE_0                                       1'b0
+    18      R/W     R_PADMUX_P4_PU_EN_CORE_0                                    1'b0
+    19      R/W     RESERVED_4                                                  1'b0
+    23:20   R/W     RESERVED_3                                                  4'd0
+    24      R/W     RESERVED_2                                                  1'b0
+    25      R/W     R_PADMUX_P4_PD_CORE_1                                       1'b0
+    26      R/W     R_PADMUX_P4_PU_EN_CORE_1                                    1'b0
+    27      R/W     RESERVED_1                                                  1'b0
+    31:28   R/W     RESERVED                                                    4'd0
+ */
+typedef union _AON_REG_PAD_AUTO_SW_PON_REG5X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED_11: 1;
+        uint32_t R_PADMUX_P4_PD_CORE_2: 1;
+        uint32_t R_PADMUX_P4_PU_EN_CORE_2: 1;
+        uint32_t RESERVED_10: 1;
+        uint32_t RESERVED_9: 4;
+        uint32_t RESERVED_8: 1;
+        uint32_t R_PADMUX_P4_PD_CORE_3: 1;
+        uint32_t R_PADMUX_P4_PU_EN_CORE_3: 1;
+        uint32_t RESERVED_7: 1;
+        uint32_t RESERVED_6: 4;
+        uint32_t RESERVED_5: 1;
+        uint32_t R_PADMUX_P4_PD_CORE_0: 1;
+        uint32_t R_PADMUX_P4_PU_EN_CORE_0: 1;
+        uint32_t RESERVED_4: 1;
+        uint32_t RESERVED_3: 4;
+        uint32_t RESERVED_2: 1;
+        uint32_t R_PADMUX_P4_PD_CORE_1: 1;
+        uint32_t R_PADMUX_P4_PU_EN_CORE_1: 1;
+        uint32_t RESERVED_1: 1;
+        uint32_t RESERVED: 4;
+    };
+} AON_REG_PAD_AUTO_SW_PON_REG5X_TYPE;
+
+/*0x4000_0ed8 AON_REG_PAD_AUTO_SW_PON_REG5X*/
+#define AON_REG_PAD_AUTO_SW_PON_REG5X_RESERVED_11_Pos                                                                    0U
+#define AON_REG_PAD_AUTO_SW_PON_REG5X_RESERVED_11_Msk                                                                    (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG5X_RESERVED_11_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG5X_R_PADMUX_P4_PD_CORE_2_Pos                                                          1U
+#define AON_REG_PAD_AUTO_SW_PON_REG5X_R_PADMUX_P4_PD_CORE_2_Msk                                                          (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG5X_R_PADMUX_P4_PD_CORE_2_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG5X_R_PADMUX_P4_PU_EN_CORE_2_Pos                                                       2U
+#define AON_REG_PAD_AUTO_SW_PON_REG5X_R_PADMUX_P4_PU_EN_CORE_2_Msk                                                       (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG5X_R_PADMUX_P4_PU_EN_CORE_2_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG5X_RESERVED_10_Pos                                                                    3U
+#define AON_REG_PAD_AUTO_SW_PON_REG5X_RESERVED_10_Msk                                                                    (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG5X_RESERVED_10_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG5X_RESERVED_9_Pos                                                                     4U
+#define AON_REG_PAD_AUTO_SW_PON_REG5X_RESERVED_9_Msk                                                                     (0xFUL << AON_REG_PAD_AUTO_SW_PON_REG5X_RESERVED_9_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG5X_RESERVED_8_Pos                                                                     8U
+#define AON_REG_PAD_AUTO_SW_PON_REG5X_RESERVED_8_Msk                                                                     (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG5X_RESERVED_8_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG5X_R_PADMUX_P4_PD_CORE_3_Pos                                                          9U
+#define AON_REG_PAD_AUTO_SW_PON_REG5X_R_PADMUX_P4_PD_CORE_3_Msk                                                          (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG5X_R_PADMUX_P4_PD_CORE_3_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG5X_R_PADMUX_P4_PU_EN_CORE_3_Pos                                                       10U
+#define AON_REG_PAD_AUTO_SW_PON_REG5X_R_PADMUX_P4_PU_EN_CORE_3_Msk                                                       (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG5X_R_PADMUX_P4_PU_EN_CORE_3_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG5X_RESERVED_7_Pos                                                                     11U
+#define AON_REG_PAD_AUTO_SW_PON_REG5X_RESERVED_7_Msk                                                                     (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG5X_RESERVED_7_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG5X_RESERVED_6_Pos                                                                     12U
+#define AON_REG_PAD_AUTO_SW_PON_REG5X_RESERVED_6_Msk                                                                     (0xFUL << AON_REG_PAD_AUTO_SW_PON_REG5X_RESERVED_6_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG5X_RESERVED_5_Pos                                                                     16U
+#define AON_REG_PAD_AUTO_SW_PON_REG5X_RESERVED_5_Msk                                                                     (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG5X_RESERVED_5_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG5X_R_PADMUX_P4_PD_CORE_0_Pos                                                          17U
+#define AON_REG_PAD_AUTO_SW_PON_REG5X_R_PADMUX_P4_PD_CORE_0_Msk                                                          (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG5X_R_PADMUX_P4_PD_CORE_0_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG5X_R_PADMUX_P4_PU_EN_CORE_0_Pos                                                       18U
+#define AON_REG_PAD_AUTO_SW_PON_REG5X_R_PADMUX_P4_PU_EN_CORE_0_Msk                                                       (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG5X_R_PADMUX_P4_PU_EN_CORE_0_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG5X_RESERVED_4_Pos                                                                     19U
+#define AON_REG_PAD_AUTO_SW_PON_REG5X_RESERVED_4_Msk                                                                     (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG5X_RESERVED_4_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG5X_RESERVED_3_Pos                                                                     20U
+#define AON_REG_PAD_AUTO_SW_PON_REG5X_RESERVED_3_Msk                                                                     (0xFUL << AON_REG_PAD_AUTO_SW_PON_REG5X_RESERVED_3_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG5X_RESERVED_2_Pos                                                                     24U
+#define AON_REG_PAD_AUTO_SW_PON_REG5X_RESERVED_2_Msk                                                                     (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG5X_RESERVED_2_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG5X_R_PADMUX_P4_PD_CORE_1_Pos                                                          25U
+#define AON_REG_PAD_AUTO_SW_PON_REG5X_R_PADMUX_P4_PD_CORE_1_Msk                                                          (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG5X_R_PADMUX_P4_PD_CORE_1_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG5X_R_PADMUX_P4_PU_EN_CORE_1_Pos                                                       26U
+#define AON_REG_PAD_AUTO_SW_PON_REG5X_R_PADMUX_P4_PU_EN_CORE_1_Msk                                                       (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG5X_R_PADMUX_P4_PU_EN_CORE_1_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG5X_RESERVED_1_Pos                                                                     27U
+#define AON_REG_PAD_AUTO_SW_PON_REG5X_RESERVED_1_Msk                                                                     (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG5X_RESERVED_1_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG5X_RESERVED_Pos                                                                       28U
+#define AON_REG_PAD_AUTO_SW_PON_REG5X_RESERVED_Msk                                                                       (0xFUL << AON_REG_PAD_AUTO_SW_PON_REG5X_RESERVED_Pos)
+
+/* 0xEDC    0x4000_0edc
+    0       R/W     RESERVED_11                                                 1'b0
+    1       R/W     R_PADMUX_SPIC_SIO1_PD_CORE                                  1'b0
+    2       R/W     R_PADMUX_SPIC_SIO1_PU_EN_CORE                               1'b0
+    3       R/W     RESERVED_10                                                 1'b0
+    7:4     R/W     RESERVED_9                                                  4'd0
+    8       R/W     RESERVED_8                                                  1'b0
+    9       R/W     R_PADMUX_SPIC_SIO0_PD_CORE                                  1'b0
+    10      R/W     R_PADMUX_SPIC_SIO0_PU_EN_CORE                               1'b0
+    11      R/W     RESERVED_7                                                  1'b0
+    15:12   R/W     RESERVED_6                                                  4'd0
+    16      R/W     RESERVED_5                                                  1'b0
+    17      R/W     R_PADMUX_SPIC_SCK_PD_CORE                                   1'b0
+    18      R/W     R_PADMUX_SPIC_SCK_PU_EN_CORE                                1'b0
+    19      R/W     RESERVED_4                                                  1'b0
+    23:20   R/W     RESERVED_3                                                  4'd0
+    24      R/W     RESERVED_2                                                  1'b0
+    25      R/W     R_PADMUX_SPIC_CSN_PD_CORE                                   1'b0
+    26      R/W     R_PADMUX_SPIC_CSN_PU_EN_CORE                                1'b0
+    27      R/W     RESERVED_1                                                  1'b0
+    31:28   R/W     RESERVED                                                    4'd0
+ */
+typedef union _AON_REG_PAD_AUTO_SW_PON_REG6X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED_11: 1;
+        uint32_t R_PADMUX_SPIC_SIO1_PD_CORE: 1;
+        uint32_t R_PADMUX_SPIC_SIO1_PU_EN_CORE: 1;
+        uint32_t RESERVED_10: 1;
+        uint32_t RESERVED_9: 4;
+        uint32_t RESERVED_8: 1;
+        uint32_t R_PADMUX_SPIC_SIO0_PD_CORE: 1;
+        uint32_t R_PADMUX_SPIC_SIO0_PU_EN_CORE: 1;
+        uint32_t RESERVED_7: 1;
+        uint32_t RESERVED_6: 4;
+        uint32_t RESERVED_5: 1;
+        uint32_t R_PADMUX_SPIC_SCK_PD_CORE: 1;
+        uint32_t R_PADMUX_SPIC_SCK_PU_EN_CORE: 1;
+        uint32_t RESERVED_4: 1;
+        uint32_t RESERVED_3: 4;
+        uint32_t RESERVED_2: 1;
+        uint32_t R_PADMUX_SPIC_CSN_PD_CORE: 1;
+        uint32_t R_PADMUX_SPIC_CSN_PU_EN_CORE: 1;
+        uint32_t RESERVED_1: 1;
+        uint32_t RESERVED: 4;
+    };
+} AON_REG_PAD_AUTO_SW_PON_REG6X_TYPE;
+
+/*0x4000_0edc AON_REG_PAD_AUTO_SW_PON_REG6X*/
+#define AON_REG_PAD_AUTO_SW_PON_REG6X_RESERVED_11_Pos                                                                    0U
+#define AON_REG_PAD_AUTO_SW_PON_REG6X_RESERVED_11_Msk                                                                    (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG6X_RESERVED_11_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG6X_R_PADMUX_SPIC_SIO1_PD_CORE_Pos                                                     1U
+#define AON_REG_PAD_AUTO_SW_PON_REG6X_R_PADMUX_SPIC_SIO1_PD_CORE_Msk                                                     (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG6X_R_PADMUX_SPIC_SIO1_PD_CORE_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG6X_R_PADMUX_SPIC_SIO1_PU_EN_CORE_Pos                                                  2U
+#define AON_REG_PAD_AUTO_SW_PON_REG6X_R_PADMUX_SPIC_SIO1_PU_EN_CORE_Msk                                                  (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG6X_R_PADMUX_SPIC_SIO1_PU_EN_CORE_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG6X_RESERVED_10_Pos                                                                    3U
+#define AON_REG_PAD_AUTO_SW_PON_REG6X_RESERVED_10_Msk                                                                    (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG6X_RESERVED_10_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG6X_RESERVED_9_Pos                                                                     4U
+#define AON_REG_PAD_AUTO_SW_PON_REG6X_RESERVED_9_Msk                                                                     (0xFUL << AON_REG_PAD_AUTO_SW_PON_REG6X_RESERVED_9_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG6X_RESERVED_8_Pos                                                                     8U
+#define AON_REG_PAD_AUTO_SW_PON_REG6X_RESERVED_8_Msk                                                                     (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG6X_RESERVED_8_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG6X_R_PADMUX_SPIC_SIO0_PD_CORE_Pos                                                     9U
+#define AON_REG_PAD_AUTO_SW_PON_REG6X_R_PADMUX_SPIC_SIO0_PD_CORE_Msk                                                     (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG6X_R_PADMUX_SPIC_SIO0_PD_CORE_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG6X_R_PADMUX_SPIC_SIO0_PU_EN_CORE_Pos                                                  10U
+#define AON_REG_PAD_AUTO_SW_PON_REG6X_R_PADMUX_SPIC_SIO0_PU_EN_CORE_Msk                                                  (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG6X_R_PADMUX_SPIC_SIO0_PU_EN_CORE_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG6X_RESERVED_7_Pos                                                                     11U
+#define AON_REG_PAD_AUTO_SW_PON_REG6X_RESERVED_7_Msk                                                                     (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG6X_RESERVED_7_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG6X_RESERVED_6_Pos                                                                     12U
+#define AON_REG_PAD_AUTO_SW_PON_REG6X_RESERVED_6_Msk                                                                     (0xFUL << AON_REG_PAD_AUTO_SW_PON_REG6X_RESERVED_6_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG6X_RESERVED_5_Pos                                                                     16U
+#define AON_REG_PAD_AUTO_SW_PON_REG6X_RESERVED_5_Msk                                                                     (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG6X_RESERVED_5_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG6X_R_PADMUX_SPIC_SCK_PD_CORE_Pos                                                      17U
+#define AON_REG_PAD_AUTO_SW_PON_REG6X_R_PADMUX_SPIC_SCK_PD_CORE_Msk                                                      (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG6X_R_PADMUX_SPIC_SCK_PD_CORE_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG6X_R_PADMUX_SPIC_SCK_PU_EN_CORE_Pos                                                   18U
+#define AON_REG_PAD_AUTO_SW_PON_REG6X_R_PADMUX_SPIC_SCK_PU_EN_CORE_Msk                                                   (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG6X_R_PADMUX_SPIC_SCK_PU_EN_CORE_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG6X_RESERVED_4_Pos                                                                     19U
+#define AON_REG_PAD_AUTO_SW_PON_REG6X_RESERVED_4_Msk                                                                     (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG6X_RESERVED_4_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG6X_RESERVED_3_Pos                                                                     20U
+#define AON_REG_PAD_AUTO_SW_PON_REG6X_RESERVED_3_Msk                                                                     (0xFUL << AON_REG_PAD_AUTO_SW_PON_REG6X_RESERVED_3_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG6X_RESERVED_2_Pos                                                                     24U
+#define AON_REG_PAD_AUTO_SW_PON_REG6X_RESERVED_2_Msk                                                                     (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG6X_RESERVED_2_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG6X_R_PADMUX_SPIC_CSN_PD_CORE_Pos                                                      25U
+#define AON_REG_PAD_AUTO_SW_PON_REG6X_R_PADMUX_SPIC_CSN_PD_CORE_Msk                                                      (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG6X_R_PADMUX_SPIC_CSN_PD_CORE_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG6X_R_PADMUX_SPIC_CSN_PU_EN_CORE_Pos                                                   26U
+#define AON_REG_PAD_AUTO_SW_PON_REG6X_R_PADMUX_SPIC_CSN_PU_EN_CORE_Msk                                                   (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG6X_R_PADMUX_SPIC_CSN_PU_EN_CORE_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG6X_RESERVED_1_Pos                                                                     27U
+#define AON_REG_PAD_AUTO_SW_PON_REG6X_RESERVED_1_Msk                                                                     (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG6X_RESERVED_1_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG6X_RESERVED_Pos                                                                       28U
+#define AON_REG_PAD_AUTO_SW_PON_REG6X_RESERVED_Msk                                                                       (0xFUL << AON_REG_PAD_AUTO_SW_PON_REG6X_RESERVED_Pos)
+
+/* 0xEE0    0x4000_0ee0
+    0       R/W     RESERVED_15                                                 1'b0
+    1       R/W     RESERVED_14                                                 1'b0
+    2       R/W     RESERVED_13                                                 1'b0
+    3       R/W     RESERVED_12                                                 1'b0
+    7:4     R/W     RESERVED_11                                                 4'd0
+    8       R/W     RESERVED_10                                                 1'b0
+    9       R/W     RESERVED_9                                                  1'b0
+    10      R/W     RESERVED_8                                                  1'b0
+    11      R/W     RESERVED_7                                                  1'b0
+    15:12   R/W     RESERVED_6                                                  4'd0
+    16      R/W     RESERVED_5                                                  1'b0
+    17      R/W     R_PADMUX_SPIC_SIO3_PD_CORE                                  1'b0
+    18      R/W     R_PADMUX_SPIC_SIO3_PU_EN_CORE                               1'b0
+    19      R/W     RESERVED_4                                                  1'b0
+    23:20   R/W     RESERVED_3                                                  4'd0
+    24      R/W     RESERVED_2                                                  1'b0
+    25      R/W     R_PADMUX_SPIC_SIO2_PD_CORE                                  1'b0
+    26      R/W     R_PADMUX_SPIC_SIO2_PU_EN_CORE                               1'b0
+    27      R/W     RESERVED_1                                                  1'b0
+    31:28   R/W     RESERVED                                                    4'd0
+ */
+typedef union _AON_REG_PAD_AUTO_SW_PON_REG7X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED_15: 1;
+        uint32_t RESERVED_14: 1;
+        uint32_t RESERVED_13: 1;
+        uint32_t RESERVED_12: 1;
+        uint32_t RESERVED_11: 4;
+        uint32_t RESERVED_10: 1;
+        uint32_t RESERVED_9: 1;
+        uint32_t RESERVED_8: 1;
+        uint32_t RESERVED_7: 1;
+        uint32_t RESERVED_6: 4;
+        uint32_t RESERVED_5: 1;
+        uint32_t R_PADMUX_SPIC_SIO3_PD_CORE: 1;
+        uint32_t R_PADMUX_SPIC_SIO3_PU_EN_CORE: 1;
+        uint32_t RESERVED_4: 1;
+        uint32_t RESERVED_3: 4;
+        uint32_t RESERVED_2: 1;
+        uint32_t R_PADMUX_SPIC_SIO2_PD_CORE: 1;
+        uint32_t R_PADMUX_SPIC_SIO2_PU_EN_CORE: 1;
+        uint32_t RESERVED_1: 1;
+        uint32_t RESERVED: 4;
+    };
+} AON_REG_PAD_AUTO_SW_PON_REG7X_TYPE;
+
+/*0x4000_0ee0 AON_REG_PAD_AUTO_SW_PON_REG7X*/
+#define AON_REG_PAD_AUTO_SW_PON_REG7X_RESERVED_15_Pos                                                                    0U
+#define AON_REG_PAD_AUTO_SW_PON_REG7X_RESERVED_15_Msk                                                                    (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG7X_RESERVED_15_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG7X_RESERVED_14_Pos                                                                    1U
+#define AON_REG_PAD_AUTO_SW_PON_REG7X_RESERVED_14_Msk                                                                    (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG7X_RESERVED_14_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG7X_RESERVED_13_Pos                                                                    2U
+#define AON_REG_PAD_AUTO_SW_PON_REG7X_RESERVED_13_Msk                                                                    (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG7X_RESERVED_13_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG7X_RESERVED_12_Pos                                                                    3U
+#define AON_REG_PAD_AUTO_SW_PON_REG7X_RESERVED_12_Msk                                                                    (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG7X_RESERVED_12_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG7X_RESERVED_11_Pos                                                                    4U
+#define AON_REG_PAD_AUTO_SW_PON_REG7X_RESERVED_11_Msk                                                                    (0xFUL << AON_REG_PAD_AUTO_SW_PON_REG7X_RESERVED_11_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG7X_RESERVED_10_Pos                                                                    8U
+#define AON_REG_PAD_AUTO_SW_PON_REG7X_RESERVED_10_Msk                                                                    (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG7X_RESERVED_10_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG7X_RESERVED_9_Pos                                                                     9U
+#define AON_REG_PAD_AUTO_SW_PON_REG7X_RESERVED_9_Msk                                                                     (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG7X_RESERVED_9_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG7X_RESERVED_8_Pos                                                                     10U
+#define AON_REG_PAD_AUTO_SW_PON_REG7X_RESERVED_8_Msk                                                                     (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG7X_RESERVED_8_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG7X_RESERVED_7_Pos                                                                     11U
+#define AON_REG_PAD_AUTO_SW_PON_REG7X_RESERVED_7_Msk                                                                     (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG7X_RESERVED_7_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG7X_RESERVED_6_Pos                                                                     12U
+#define AON_REG_PAD_AUTO_SW_PON_REG7X_RESERVED_6_Msk                                                                     (0xFUL << AON_REG_PAD_AUTO_SW_PON_REG7X_RESERVED_6_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG7X_RESERVED_5_Pos                                                                     16U
+#define AON_REG_PAD_AUTO_SW_PON_REG7X_RESERVED_5_Msk                                                                     (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG7X_RESERVED_5_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG7X_R_PADMUX_SPIC_SIO3_PD_CORE_Pos                                                     17U
+#define AON_REG_PAD_AUTO_SW_PON_REG7X_R_PADMUX_SPIC_SIO3_PD_CORE_Msk                                                     (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG7X_R_PADMUX_SPIC_SIO3_PD_CORE_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG7X_R_PADMUX_SPIC_SIO3_PU_EN_CORE_Pos                                                  18U
+#define AON_REG_PAD_AUTO_SW_PON_REG7X_R_PADMUX_SPIC_SIO3_PU_EN_CORE_Msk                                                  (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG7X_R_PADMUX_SPIC_SIO3_PU_EN_CORE_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG7X_RESERVED_4_Pos                                                                     19U
+#define AON_REG_PAD_AUTO_SW_PON_REG7X_RESERVED_4_Msk                                                                     (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG7X_RESERVED_4_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG7X_RESERVED_3_Pos                                                                     20U
+#define AON_REG_PAD_AUTO_SW_PON_REG7X_RESERVED_3_Msk                                                                     (0xFUL << AON_REG_PAD_AUTO_SW_PON_REG7X_RESERVED_3_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG7X_RESERVED_2_Pos                                                                     24U
+#define AON_REG_PAD_AUTO_SW_PON_REG7X_RESERVED_2_Msk                                                                     (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG7X_RESERVED_2_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG7X_R_PADMUX_SPIC_SIO2_PD_CORE_Pos                                                     25U
+#define AON_REG_PAD_AUTO_SW_PON_REG7X_R_PADMUX_SPIC_SIO2_PD_CORE_Msk                                                     (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG7X_R_PADMUX_SPIC_SIO2_PD_CORE_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG7X_R_PADMUX_SPIC_SIO2_PU_EN_CORE_Pos                                                  26U
+#define AON_REG_PAD_AUTO_SW_PON_REG7X_R_PADMUX_SPIC_SIO2_PU_EN_CORE_Msk                                                  (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG7X_R_PADMUX_SPIC_SIO2_PU_EN_CORE_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG7X_RESERVED_1_Pos                                                                     27U
+#define AON_REG_PAD_AUTO_SW_PON_REG7X_RESERVED_1_Msk                                                                     (0x1UL << AON_REG_PAD_AUTO_SW_PON_REG7X_RESERVED_1_Pos)
+
+#define AON_REG_PAD_AUTO_SW_PON_REG7X_RESERVED_Pos                                                                       28U
+#define AON_REG_PAD_AUTO_SW_PON_REG7X_RESERVED_Msk                                                                       (0xFUL << AON_REG_PAD_AUTO_SW_PON_REG7X_RESERVED_Pos)
+
+
+#define AON_REG_BASE 0x40000000
+
+#define AON_REG_READ(Offset)\
+    ((uint32_t)*((volatile uint32_t*)(AON_REG_BASE+(Offset))))
+
+#define AON_REG_WRITE(Offset, Value)\
+    ((*((volatile uint32_t*)(AON_REG_BASE + (Offset)))) = (Value))
+
+#define AON_REG_UPDATE(Offset, Mask, Value) \
+    do {\
+        uint32_t temp;\
+        temp = AON_REG_READ(Offset) & ~(Mask);\
+        AON_REG_WRITE(Offset, (temp | ((Value) & (Mask))));\
+    } while(0)
+
+#define AON_REG_READ_BITFIELD(Offset, Bitfield)                   \
+    (((Offset##_TYPE)AON_REG_READ(Offset)).Bitfield)
+
+#define AON_REG_WRITE_BITFIELD(Offset, Bitfield, Value)           \
+    do {                                                        \
+        Offset##_TYPE temp = {.d32 = AON_REG_READ(Offset)};       \
+        temp.Bitfield = Value;                                         \
+        AON_REG_WRITE(Offset, temp.d32);                          \
+    } while(0)
+
+#endif //#define AON_REG_H
diff --git a/bee/soc/inc/rtl87x2j/chip_define.h b/bee/soc/inc/rtl87x2j/chip_define.h
new file mode 100755
index 00000000..3e3af585
--- /dev/null
+++ b/bee/soc/inc/rtl87x2j/chip_define.h
@@ -0,0 +1,17 @@
+#ifndef _CHIP_DEFINE_H_
+#define _CHIP_DEFINE_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* https://wiki.realtek.com/display/BTFWKNOW/BT+Chip+Version+In+FW */
+#define CHIP_ID_IN_ROM                                  59 // RTK_BT_CHIP_ID_RTL8762J
+
+#define _ROM_VER_                                       0
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _CHIP_DEFINE_H_ */
diff --git a/bee/soc/inc/rtl87x2j/cm33f_setting.h b/bee/soc/inc/rtl87x2j/cm33f_setting.h
new file mode 100755
index 00000000..2b6fcee5
--- /dev/null
+++ b/bee/soc/inc/rtl87x2j/cm33f_setting.h
@@ -0,0 +1,23 @@
+#ifndef CM33F_SETTING_H
+#define CM33F_SETTING_H
+
+/* ================================================================================ */
+/* ================      Processor and Core Peripheral Section     ================ */
+/* ================================================================================ */
+#define __CHECK_DEVICE_DEFINES
+#define __CM33_REV                     0x0000U    //!< Core revision
+#define __MPU_PRESENT                  1          //!< MPU present or not
+#define __SAUREGION_PRESENT            0          //!< SAU present or not
+#define __VTOR_PRESENT                 1          //!< VTOR present or not
+#define __FPU_PRESENT                  1          //!< FPU present or not
+#define __DSP_PRESENT                  1          //!< DSP extension present or not
+#define __NVIC_PRIO_BITS               3          //!< Number of Bits used for Priority Levels
+#define __Vendor_SysTickConfig         0          //!< Set to 1 if different SysTick Config is used
+
+/*============================================================================*
+ *                               Header Files
+*============================================================================*/
+#include "vector_table.h"
+#include "core_cm33.h"                       /* Processor and core peripherals */
+
+#endif //#define CM33F_SETTING_H
diff --git a/bee/soc/inc/rtl87x2j/cpu_setting.h b/bee/soc/inc/rtl87x2j/cpu_setting.h
new file mode 100755
index 00000000..e0ea3178
--- /dev/null
+++ b/bee/soc/inc/rtl87x2j/cpu_setting.h
@@ -0,0 +1,9 @@
+#ifndef CPU_SETTING_H
+#define CPU_SETTING_H
+
+/*============================================================================*
+ *                               Header Files
+*============================================================================*/
+#include "cm33f_setting.h"                       /* Processor and core peripherals */
+
+#endif //#define CPU_SETTING_H
diff --git a/bee/soc/inc/rtl87x2j/pcc_reg.h b/bee/soc/inc/rtl87x2j/pcc_reg.h
new file mode 100755
index 00000000..17ab72d7
--- /dev/null
+++ b/bee/soc/inc/rtl87x2j/pcc_reg.h
@@ -0,0 +1,10830 @@
+#ifndef PCC_REG_H
+#define PCC_REG_H
+#include <stdint.h>
+
+/* ================================================================================ */
+/* ================                PCC Register               ================ */
+/* ===========     Reference: RL7019_SYSON_auto_gen_table_20251107A.xlsx     =========== */
+/* ================================================================================ */
+#define PCC_REG_PERION_CLK_REG0X        0x200
+#define PCC_REG_PERION_CLK_REG1X        0x204
+#define PCC_REG_PERION_CLK_REG2X        0x208
+#define PCC_REG_PERION_CLK_REG3X        0x20C
+#define PCC_REG_PERION_CLK_REG4X        0x210
+#define PCC_REG_PERION_CLK_REG5X        0x214
+#define PCC_REG_TRNG                    0x218
+#define PCC_REG_CORE_WDT                0x21C
+#define PCC_REG_AES                     0x220
+#define PCC_REG_SHA256                  0x224
+#define PCC_REG_MODEMRFCPI              0x228
+#define PCC_REG_DMA                     0x22C
+#define PCC_REG_SPIC                    0x230
+#define PCC_REG_SPI0                    0x234
+#define PCC_REG_SPI1                    0x238
+#define PCC_REG_SPI2                    0x23C
+#define PCC_REG_I2S0                    0x240
+#define PCC_REG_TIMER0                  0x244
+#define PCC_REG_TIMER1_A                0x248
+#define PCC_REG_TIMER1_B                0x24C
+#define PCC_REG_TIMER1_C                0x250
+#define PCC_REG_TIMER2                  0x254
+#define PCC_REG_TIMER2_PWM              0x258
+#define PCC_REG_USB                     0x25C
+#define PCC_REG_ADC_CONTROLLER          0x260
+#define PCC_REG_I2C0                    0x264
+#define PCC_REG_I2C1                    0x268
+#define PCC_REG_Keyscan                 0x26C
+#define PCC_REG_SPI3W                   0x270
+#define PCC_REG_EFLASH                  0x274
+#define PCC_REG_CAN                     0x278
+#define PCC_REG_GPIO_DEBOUNCE_2P4G      0x27C
+#define PCC_REG_UART0                   0x280
+#define PCC_REG_UART1                   0x284
+#define PCC_REG_UART2                   0x288
+#define PCC_REG_UART3                   0x28C
+#define PCC_REG_GPIOA                   0x290
+#define PCC_REG_MODEM                   0x294
+#define PCC_REG_PROPRIETARY             0x298
+#define PCC_REG_IR                      0x29C
+#define PCC_REG_BT_VDREG                0x2A0
+#define PCC_REG_AUDIO                   0x2A4
+#define PCC_REG_LXBUS                   0x2A8
+#define PCC_REG_CAL32K                  0x2AC
+#define PCC_REG_PLATFORM                0x2B0
+#define PCC_REG_PCC                     0x2B4
+#define PCC_REG_TMETER                  0x2B8
+#define PCC_REG_TIMER1_D                0x2BC
+#define PCC_REG_CAL80M                  0x8F0
+#define PCC_REG_CAL10M                  0x8F4
+#define PCC_REG_VDREG                   0x8F8
+#define PCC_REG_CPU                     0x8FC
+#define PCC_REG_SYSON                   0x900
+#define PCC_REG_HCI                     0x904
+#define PCC_REG_BT_OTHER0               0x908
+#define PCC_REG_TIMER0_PCLK             0x90C
+#define PCC_REG_TIMER1_PCLK             0x910
+#define PCC_REG_ETIMER_PCLK             0x914
+#define PCC_REG_OSC128K_CAL             0x918
+#define PCC_REG_RXI300                  0x91C
+#define PCC_REG_AON_DEB_TOP             0x920
+#define PCC_REG_OTHERS                  0x924
+#define PCC_REG_PERION_CLK_VPON_REG0X   0x3C4
+#define PCC_REG_PERION_CLK_VPON_REG1X   0x3C8
+#define PCC_REG_PERION_CLK_VPON_REG2X   0x3CC
+#define PCC_REG_LPPWM                   0x3D0
+#define PCC_REG_LPQDEC                  0x3D4
+#define PCC_REG_GRTC                    0x3D8
+#define PCC_REG_BLUEWIZ                 0x3DC
+#define PCC_REG_USER_RTC                0x3E0
+#define PCC_REG_RAP                     0x3E4
+#define PCC_REG_GTC                     0x3E8
+#define PCC_REG_SDM_VPON                0x3EC
+#define PCC_REG_LPWDT_VPON              0x3F0
+#define PCC_REG_PERION_CLK_AON_REG0X    0x3F4
+#define PCC_REG_PCK600                  0x3F8
+#define PCC_REG_LPC                     0x3FC
+#define PCC_r_PMUX_GPIO_P0_0to3         0x2C0
+#define PCC_r_PMUX_GPIO_P0_4to7         0x2C4
+#define PCC_r_PMUX_GPIO_P1_0to7         0x2C8
+#define PCC_r_PMUX_GPIO_P2_0to3         0x2CC
+#define PCC_r_PMUX_GPIO_P2_4to7         0x2D0
+#define PCC_r_PMUX_GPIO_P3_0to3         0x2D4
+#define PCC_r_PMUX_GPIO_P3_4to6         0x2D8
+#define PCC_r_PMUX_GPIO_P4_0to3         0x2DC
+#define PCC_r_PMUX_GPIO_H_0to2          0x2E0
+#define PCC_REG_PMUX_GPIO_6_0to3        0x2E4
+#define PCC_REG_PMUX_GPIO_6_4to7        0x2E8
+#define PCC_REG_PMUX_GPIO_7_0to1_SPIC_1 0x2EC
+#define PCC_REG_PMUX_GPIO_SPIC_2        0x2F0
+#define PCC_r_PMUX_TEST_MODE            0x2F4
+#define PCC_REG_BC12_CTRL1              0x2F8
+#define PCC_REG_BC12_CTRL2              0x2FC
+#define PCC_REG_BC12_CTRL3              0x300
+#define PCC_REG_BC12_CTRL4              0x304
+#define PCC_REG_BC12_CTRL5              0x308
+#define PCC_REG_BC12_CTRL6              0x30C
+#define PCC_REG_DBG_MUX_CTRL            0x310
+#define PCC_REG_RSVD_2D8                0x314
+#define PCC_REG_SWITCH_PAR              0x318
+#define PCC_REG_PINMUX_DBG_REG          0x31C
+#define PCC_LDO_PA_SWR_AUTO_SW          0x320
+#define PCC_CORE_SWR_PAR_TAB_0_0        0x324
+#define PCC_CORE_SWR_PAR_TAB_4_0        0x328
+#define PCC_CORE_SWR_PAR_TAB_5_0        0x32C
+#define PCC_CORE_SWR_PAR_TAB_6_0        0x330
+#define PCC_CORE_SWR_PAR_TAB_7_0        0x334
+#define PCC_REG_CORE_PAR                0x338
+#define PCC_PON_PERI_DLYSEL_CTRL        0x33C
+#define PCC_REG_DSS_CTRL0               0x340
+#define PCC_REG_DSS_CTRL1               0x344
+#define PCC_REG_DSS_CTRL2               0x348
+#define PCC_REG_OSC40_CTRL              0x34C
+#define PCC_REG_AAC_0                   0x350
+#define PCC_REG_AAC_1                   0x354
+#define PCC_REG_XTAL_PLL                0x358
+#define PCC_REG_XTALPDCK                0x35C
+#define PCC_REG_PADMUX_AS_CFG0          0x360
+#define PCC_REG_PADMUX_AS_CFG1          0x364
+#define PCC_REG_PADMUX_AS_CFG2          0x368
+#define PCC_REG_PADMUX_AS_CFG3          0x36C
+#define PCC_REG_PADMUX_AS_CFG4          0x370
+#define PCC_REG_PADMUX_AS_CFG5          0x374
+#define PCC_REG_PADMUX_AS_CFG6          0x378
+#define PCC_REG_PADMUX_AS_CFG7          0x37C
+#define PCC_REG_PADMUX_AS_CFG8          0x380
+#define PCC_REG_PADMUX_AS_CFG9          0x384
+#define PCC_REG_PADMUX_AS_CFG10         0x388
+#define PCC_REG_QCH_BUSY_FLAG1_PROC1    0x38C
+#define PCC_REG_QCH_BUSY_FLAG1_PROC2    0x390
+#define PCC_REG_QCH_BUSY_FLAG0_PROC0    0x394
+#define PCC_REG_QCH_BUSY_FLAG0_PROC1    0x398
+#define PCC_REG_QCH_BUSY_FLAG0_PROC2    0x39C
+#define PCC_REG_QCH_BUSY_FLAG1          0x3A0
+#define PCC_REG_QCH_BUSY_FLAG0          0x3A4
+#define PCC_REG_USB_POW                 0x3A8
+#define PCC_REG_DUMMY_3AC               0x3AC
+#define PCC_REG_DUMMY_3B0               0x3B0
+#define PCC_REG_DUMMY_3B4               0x3B4
+#define PCC_REG_DBG_MUX_PCK             0x3B8
+#define PCC_REG_DBG_MUX_GRP_CFG0        0x3BC
+#define PCC_REG_DBG_MUX_GRP_CFG1        0x3C0
+
+/* 0x200    0x4000_0200
+    0       R/W     RESERVED                                        1'b0
+    1       W1O     REG_ZONE1_WRP_EN                                1'b0
+    2       W1O     REG_ZONE2_WRP_EN                                1'b0
+    3       W1O     REG_WRP_LOCK                                    1'b0
+    9:4     R/W     R_BT_AHB_WAIT_CNT                               6'h0C
+    10      R/W     R_AON_RD_OPT                                    1'b1
+    11      R/W     R_BTAON_ACC_NO_BLOCK                            1'b0
+    12      R       CLKEN_O_UART0                                   1'h0
+    13      R       CLKEN_O_UART1                                   1'h0
+    14      R       CLKEN_O_UART2                                   1'h0
+    15      R       CLKEN_O_UART3                                   1'h0
+    16      R       CLKEN_O_IRRC                                    1'h0
+    17      R       CLKEN_O_AUDIO                                   1'h0
+    18      R       CLKEN_O_TIMER1                                  1'h0
+    19      R       CLKEN_O_TIMER2                                  1'h0
+    20      R       CLKEN_O_TIMER3                                  1'h0
+    21      R       CLKEN_O_TIMER4                                  1'h0
+    22      R       CLKEN_O_TIMER5                                  1'h0
+    23      R       CLKEN_O_TIMER6                                  1'h0
+    24      R       CLKEN_O_TIMER7                                  1'h0
+    25      R       CLKEN_O_TIMER8                                  1'h0
+    26      R       CLKEN_O_TIMER9                                  1'h0
+    27      R       CLKEN_O_TIMER10                                 1'h0
+    28      R       CLKEN_O_TIMER11                                 1'h0
+    29      R       CLKEN_O_ETIMER                                  1'h0
+    30      R       CLKEN_O_RFC                                     1'h0
+    31      R       CLKEN_O_MODEM                                   1'h0
+ */
+typedef union _PCC_REG_PERION_CLK_REG0X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED: 1;
+        uint32_t REG_ZONE1_WRP_EN: 1;
+        uint32_t REG_ZONE2_WRP_EN: 1;
+        uint32_t REG_WRP_LOCK: 1;
+        uint32_t R_BT_AHB_WAIT_CNT: 6;
+        uint32_t R_AON_RD_OPT: 1;
+        uint32_t R_BTAON_ACC_NO_BLOCK: 1;
+        uint32_t CLKEN_O_UART0: 1;
+        uint32_t CLKEN_O_UART1: 1;
+        uint32_t CLKEN_O_UART2: 1;
+        uint32_t CLKEN_O_UART3: 1;
+        uint32_t CLKEN_O_IRRC: 1;
+        uint32_t CLKEN_O_AUDIO: 1;
+        uint32_t CLKEN_O_TIMER1: 1;
+        uint32_t CLKEN_O_TIMER2: 1;
+        uint32_t CLKEN_O_TIMER3: 1;
+        uint32_t CLKEN_O_TIMER4: 1;
+        uint32_t CLKEN_O_TIMER5: 1;
+        uint32_t CLKEN_O_TIMER6: 1;
+        uint32_t CLKEN_O_TIMER7: 1;
+        uint32_t CLKEN_O_TIMER8: 1;
+        uint32_t CLKEN_O_TIMER9: 1;
+        uint32_t CLKEN_O_TIMER10: 1;
+        uint32_t CLKEN_O_TIMER11: 1;
+        uint32_t CLKEN_O_ETIMER: 1;
+        uint32_t CLKEN_O_RFC: 1;
+        uint32_t CLKEN_O_MODEM: 1;
+    };
+} PCC_REG_PERION_CLK_REG0X_TYPE;
+
+/*0x4000_0200 PCC_REG_PERION_CLK_REG0X*/
+#define PCC_REG_PERION_CLK_REG0X_RESERVED_Pos                                                    0U
+#define PCC_REG_PERION_CLK_REG0X_RESERVED_Msk                                                    (0x1UL << PCC_REG_PERION_CLK_REG0X_RESERVED_Pos)
+
+#define PCC_REG_PERION_CLK_REG0X_REG_ZONE1_WRP_EN_Pos                                            1U
+#define PCC_REG_PERION_CLK_REG0X_REG_ZONE1_WRP_EN_Msk                                            (0x1UL << PCC_REG_PERION_CLK_REG0X_REG_ZONE1_WRP_EN_Pos)
+
+#define PCC_REG_PERION_CLK_REG0X_REG_ZONE2_WRP_EN_Pos                                            2U
+#define PCC_REG_PERION_CLK_REG0X_REG_ZONE2_WRP_EN_Msk                                            (0x1UL << PCC_REG_PERION_CLK_REG0X_REG_ZONE2_WRP_EN_Pos)
+
+#define PCC_REG_PERION_CLK_REG0X_REG_WRP_LOCK_Pos                                                3U
+#define PCC_REG_PERION_CLK_REG0X_REG_WRP_LOCK_Msk                                                (0x1UL << PCC_REG_PERION_CLK_REG0X_REG_WRP_LOCK_Pos)
+
+#define PCC_REG_PERION_CLK_REG0X_R_BT_AHB_WAIT_CNT_Pos                                           4U
+#define PCC_REG_PERION_CLK_REG0X_R_BT_AHB_WAIT_CNT_Msk                                           (0x3FUL << PCC_REG_PERION_CLK_REG0X_R_BT_AHB_WAIT_CNT_Pos)
+
+#define PCC_REG_PERION_CLK_REG0X_R_AON_RD_OPT_Pos                                                10U
+#define PCC_REG_PERION_CLK_REG0X_R_AON_RD_OPT_Msk                                                (0x1UL << PCC_REG_PERION_CLK_REG0X_R_AON_RD_OPT_Pos)
+
+#define PCC_REG_PERION_CLK_REG0X_R_BTAON_ACC_NO_BLOCK_Pos                                        11U
+#define PCC_REG_PERION_CLK_REG0X_R_BTAON_ACC_NO_BLOCK_Msk                                        (0x1UL << PCC_REG_PERION_CLK_REG0X_R_BTAON_ACC_NO_BLOCK_Pos)
+
+#define PCC_REG_PERION_CLK_REG0X_CLKEN_O_UART0_Pos                                               12U
+#define PCC_REG_PERION_CLK_REG0X_CLKEN_O_UART0_Msk                                               (0x1UL << PCC_REG_PERION_CLK_REG0X_CLKEN_O_UART0_Pos)
+
+#define PCC_REG_PERION_CLK_REG0X_CLKEN_O_UART1_Pos                                               13U
+#define PCC_REG_PERION_CLK_REG0X_CLKEN_O_UART1_Msk                                               (0x1UL << PCC_REG_PERION_CLK_REG0X_CLKEN_O_UART1_Pos)
+
+#define PCC_REG_PERION_CLK_REG0X_CLKEN_O_UART2_Pos                                               14U
+#define PCC_REG_PERION_CLK_REG0X_CLKEN_O_UART2_Msk                                               (0x1UL << PCC_REG_PERION_CLK_REG0X_CLKEN_O_UART2_Pos)
+
+#define PCC_REG_PERION_CLK_REG0X_CLKEN_O_UART3_Pos                                               15U
+#define PCC_REG_PERION_CLK_REG0X_CLKEN_O_UART3_Msk                                               (0x1UL << PCC_REG_PERION_CLK_REG0X_CLKEN_O_UART3_Pos)
+
+#define PCC_REG_PERION_CLK_REG0X_CLKEN_O_IRRC_Pos                                                16U
+#define PCC_REG_PERION_CLK_REG0X_CLKEN_O_IRRC_Msk                                                (0x1UL << PCC_REG_PERION_CLK_REG0X_CLKEN_O_IRRC_Pos)
+
+#define PCC_REG_PERION_CLK_REG0X_CLKEN_O_AUDIO_Pos                                               17U
+#define PCC_REG_PERION_CLK_REG0X_CLKEN_O_AUDIO_Msk                                               (0x1UL << PCC_REG_PERION_CLK_REG0X_CLKEN_O_AUDIO_Pos)
+
+#define PCC_REG_PERION_CLK_REG0X_CLKEN_O_TIMER1_Pos                                              18U
+#define PCC_REG_PERION_CLK_REG0X_CLKEN_O_TIMER1_Msk                                              (0x1UL << PCC_REG_PERION_CLK_REG0X_CLKEN_O_TIMER1_Pos)
+
+#define PCC_REG_PERION_CLK_REG0X_CLKEN_O_TIMER2_Pos                                              19U
+#define PCC_REG_PERION_CLK_REG0X_CLKEN_O_TIMER2_Msk                                              (0x1UL << PCC_REG_PERION_CLK_REG0X_CLKEN_O_TIMER2_Pos)
+
+#define PCC_REG_PERION_CLK_REG0X_CLKEN_O_TIMER3_Pos                                              20U
+#define PCC_REG_PERION_CLK_REG0X_CLKEN_O_TIMER3_Msk                                              (0x1UL << PCC_REG_PERION_CLK_REG0X_CLKEN_O_TIMER3_Pos)
+
+#define PCC_REG_PERION_CLK_REG0X_CLKEN_O_TIMER4_Pos                                              21U
+#define PCC_REG_PERION_CLK_REG0X_CLKEN_O_TIMER4_Msk                                              (0x1UL << PCC_REG_PERION_CLK_REG0X_CLKEN_O_TIMER4_Pos)
+
+#define PCC_REG_PERION_CLK_REG0X_CLKEN_O_TIMER5_Pos                                              22U
+#define PCC_REG_PERION_CLK_REG0X_CLKEN_O_TIMER5_Msk                                              (0x1UL << PCC_REG_PERION_CLK_REG0X_CLKEN_O_TIMER5_Pos)
+
+#define PCC_REG_PERION_CLK_REG0X_CLKEN_O_TIMER6_Pos                                              23U
+#define PCC_REG_PERION_CLK_REG0X_CLKEN_O_TIMER6_Msk                                              (0x1UL << PCC_REG_PERION_CLK_REG0X_CLKEN_O_TIMER6_Pos)
+
+#define PCC_REG_PERION_CLK_REG0X_CLKEN_O_TIMER7_Pos                                              24U
+#define PCC_REG_PERION_CLK_REG0X_CLKEN_O_TIMER7_Msk                                              (0x1UL << PCC_REG_PERION_CLK_REG0X_CLKEN_O_TIMER7_Pos)
+
+#define PCC_REG_PERION_CLK_REG0X_CLKEN_O_TIMER8_Pos                                              25U
+#define PCC_REG_PERION_CLK_REG0X_CLKEN_O_TIMER8_Msk                                              (0x1UL << PCC_REG_PERION_CLK_REG0X_CLKEN_O_TIMER8_Pos)
+
+#define PCC_REG_PERION_CLK_REG0X_CLKEN_O_TIMER9_Pos                                              26U
+#define PCC_REG_PERION_CLK_REG0X_CLKEN_O_TIMER9_Msk                                              (0x1UL << PCC_REG_PERION_CLK_REG0X_CLKEN_O_TIMER9_Pos)
+
+#define PCC_REG_PERION_CLK_REG0X_CLKEN_O_TIMER10_Pos                                             27U
+#define PCC_REG_PERION_CLK_REG0X_CLKEN_O_TIMER10_Msk                                             (0x1UL << PCC_REG_PERION_CLK_REG0X_CLKEN_O_TIMER10_Pos)
+
+#define PCC_REG_PERION_CLK_REG0X_CLKEN_O_TIMER11_Pos                                             28U
+#define PCC_REG_PERION_CLK_REG0X_CLKEN_O_TIMER11_Msk                                             (0x1UL << PCC_REG_PERION_CLK_REG0X_CLKEN_O_TIMER11_Pos)
+
+#define PCC_REG_PERION_CLK_REG0X_CLKEN_O_ETIMER_Pos                                              29U
+#define PCC_REG_PERION_CLK_REG0X_CLKEN_O_ETIMER_Msk                                              (0x1UL << PCC_REG_PERION_CLK_REG0X_CLKEN_O_ETIMER_Pos)
+
+#define PCC_REG_PERION_CLK_REG0X_CLKEN_O_RFC_Pos                                                 30U
+#define PCC_REG_PERION_CLK_REG0X_CLKEN_O_RFC_Msk                                                 (0x1UL << PCC_REG_PERION_CLK_REG0X_CLKEN_O_RFC_Pos)
+
+#define PCC_REG_PERION_CLK_REG0X_CLKEN_O_MODEM_Pos                                               31U
+#define PCC_REG_PERION_CLK_REG0X_CLKEN_O_MODEM_Msk                                               (0x1UL << PCC_REG_PERION_CLK_REG0X_CLKEN_O_MODEM_Pos)
+
+/* 0x204    0x4000_0204
+    3:0     R       RF_RL_ID                                        4'd0
+    7:4     R       RF_RTL_ID                                       4'd0
+    27:8    R       RESERVED                                        20'h0
+    30:28   R/W     DUMMY2                                          3'b0
+    31      R/W     VCORE_STATUS_CHECK                              1'b0
+ */
+typedef union _PCC_REG_PERION_CLK_REG1X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RF_RL_ID: 4;
+        uint32_t RF_RTL_ID: 4;
+        uint32_t RESERVED: 20;
+        uint32_t DUMMY2: 3;
+        uint32_t VCORE_STATUS_CHECK: 1;
+    };
+} PCC_REG_PERION_CLK_REG1X_TYPE;
+
+/*0x4000_0204 PCC_REG_PERION_CLK_REG1X*/
+#define PCC_REG_PERION_CLK_REG1X_RF_RL_ID_Pos                                                    0U
+#define PCC_REG_PERION_CLK_REG1X_RF_RL_ID_Msk                                                    (0xFUL << PCC_REG_PERION_CLK_REG1X_RF_RL_ID_Pos)
+
+#define PCC_REG_PERION_CLK_REG1X_RF_RTL_ID_Pos                                                   4U
+#define PCC_REG_PERION_CLK_REG1X_RF_RTL_ID_Msk                                                   (0xFUL << PCC_REG_PERION_CLK_REG1X_RF_RTL_ID_Pos)
+
+#define PCC_REG_PERION_CLK_REG1X_RESERVED_Pos                                                    8U
+#define PCC_REG_PERION_CLK_REG1X_RESERVED_Msk                                                    (0xFFFFFUL << PCC_REG_PERION_CLK_REG1X_RESERVED_Pos)
+
+#define PCC_REG_PERION_CLK_REG1X_DUMMY2_Pos                                                      28U
+#define PCC_REG_PERION_CLK_REG1X_DUMMY2_Msk                                                      (0x7UL << PCC_REG_PERION_CLK_REG1X_DUMMY2_Pos)
+
+#define PCC_REG_PERION_CLK_REG1X_VCORE_STATUS_CHECK_Pos                                          31U
+#define PCC_REG_PERION_CLK_REG1X_VCORE_STATUS_CHECK_Msk                                          (0x1UL << PCC_REG_PERION_CLK_REG1X_VCORE_STATUS_CHECK_Pos)
+
+/* 0x208    0x4000_0208
+    0       R/W     HCLK_AUTO_SLOW_EN                               1'b0
+    8:1     R/W     HCLK_AUTO_SLOW_OP1_EVNT                         8'b0
+    11:9    R/W     HCLK_DIV_SEL                                    3'h0
+    12      R       MODEM_CLK_SWITCH_DONE                           1'h1
+    13      R/W     MODEM_CK_40M_GATE_EN                            1'h0
+    14      R/W     MODEM_CK_FORCE_LOW                              1'h0
+    16:15   R/W     R_PLATFORM_DIV_SEL                              2'b00
+    19:17   R/W     RESERVED_2                                      3'b000
+    20      R/W     RESERVED_1                                      1'b0
+    21      R/W     RESERVED                                        1'b0
+    22      R/W     R_CLK_SYSTICK_EN                                1'b1
+    23      R/W     R_10M_SYSTICK_CLK_SRC_SEL                       1'b1
+    24      R/W     R_40M_AUDIO_CLK_SRC_SEL                         1'b1
+    25      R/W     R_TIMER_CLK_F40M_SRC_SEL                        1'b1
+    26      R/W     R_UART_CLK_SRC_SEL                              1'b1
+    31:27   R/W     DUMMY3                                          5'b0
+ */
+typedef union _PCC_REG_PERION_CLK_REG2X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t HCLK_AUTO_SLOW_EN: 1;
+        uint32_t HCLK_AUTO_SLOW_OP1_EVNT: 8;
+        uint32_t HCLK_DIV_SEL: 3;
+        uint32_t MODEM_CLK_SWITCH_DONE: 1;
+        uint32_t MODEM_CK_40M_GATE_EN: 1;
+        uint32_t MODEM_CK_FORCE_LOW: 1;
+        uint32_t R_PLATFORM_DIV_SEL: 2;
+        uint32_t RESERVED_2: 3;
+        uint32_t RESERVED_1: 1;
+        uint32_t RESERVED: 1;
+        uint32_t R_CLK_SYSTICK_EN: 1;
+        uint32_t R_10M_SYSTICK_CLK_SRC_SEL: 1;
+        uint32_t R_40M_AUDIO_CLK_SRC_SEL: 1;
+        uint32_t R_TIMER_CLK_F40M_SRC_SEL: 1;
+        uint32_t R_UART_CLK_SRC_SEL: 1;
+        uint32_t DUMMY3: 5;
+    };
+} PCC_REG_PERION_CLK_REG2X_TYPE;
+
+/*0x4000_0208 PCC_REG_PERION_CLK_REG2X*/
+#define PCC_REG_PERION_CLK_REG2X_HCLK_AUTO_SLOW_EN_Pos                                           0U
+#define PCC_REG_PERION_CLK_REG2X_HCLK_AUTO_SLOW_EN_Msk                                           (0x1UL << PCC_REG_PERION_CLK_REG2X_HCLK_AUTO_SLOW_EN_Pos)
+
+#define PCC_REG_PERION_CLK_REG2X_HCLK_AUTO_SLOW_OP1_EVNT_Pos                                     1U
+#define PCC_REG_PERION_CLK_REG2X_HCLK_AUTO_SLOW_OP1_EVNT_Msk                                     (0xFFUL << PCC_REG_PERION_CLK_REG2X_HCLK_AUTO_SLOW_OP1_EVNT_Pos)
+
+#define PCC_REG_PERION_CLK_REG2X_HCLK_DIV_SEL_Pos                                                9U
+#define PCC_REG_PERION_CLK_REG2X_HCLK_DIV_SEL_Msk                                                (0x7UL << PCC_REG_PERION_CLK_REG2X_HCLK_DIV_SEL_Pos)
+
+#define PCC_REG_PERION_CLK_REG2X_MODEM_CLK_SWITCH_DONE_Pos                                       12U
+#define PCC_REG_PERION_CLK_REG2X_MODEM_CLK_SWITCH_DONE_Msk                                       (0x1UL << PCC_REG_PERION_CLK_REG2X_MODEM_CLK_SWITCH_DONE_Pos)
+
+#define PCC_REG_PERION_CLK_REG2X_MODEM_CK_40M_GATE_EN_Pos                                        13U
+#define PCC_REG_PERION_CLK_REG2X_MODEM_CK_40M_GATE_EN_Msk                                        (0x1UL << PCC_REG_PERION_CLK_REG2X_MODEM_CK_40M_GATE_EN_Pos)
+
+#define PCC_REG_PERION_CLK_REG2X_MODEM_CK_FORCE_LOW_Pos                                          14U
+#define PCC_REG_PERION_CLK_REG2X_MODEM_CK_FORCE_LOW_Msk                                          (0x1UL << PCC_REG_PERION_CLK_REG2X_MODEM_CK_FORCE_LOW_Pos)
+
+#define PCC_REG_PERION_CLK_REG2X_R_PLATFORM_DIV_SEL_Pos                                          15U
+#define PCC_REG_PERION_CLK_REG2X_R_PLATFORM_DIV_SEL_Msk                                          (0x3UL << PCC_REG_PERION_CLK_REG2X_R_PLATFORM_DIV_SEL_Pos)
+
+#define PCC_REG_PERION_CLK_REG2X_RESERVED_2_Pos                                                  17U
+#define PCC_REG_PERION_CLK_REG2X_RESERVED_2_Msk                                                  (0x7UL << PCC_REG_PERION_CLK_REG2X_RESERVED_2_Pos)
+
+#define PCC_REG_PERION_CLK_REG2X_RESERVED_1_Pos                                                  20U
+#define PCC_REG_PERION_CLK_REG2X_RESERVED_1_Msk                                                  (0x1UL << PCC_REG_PERION_CLK_REG2X_RESERVED_1_Pos)
+
+#define PCC_REG_PERION_CLK_REG2X_RESERVED_Pos                                                    21U
+#define PCC_REG_PERION_CLK_REG2X_RESERVED_Msk                                                    (0x1UL << PCC_REG_PERION_CLK_REG2X_RESERVED_Pos)
+
+#define PCC_REG_PERION_CLK_REG2X_R_CLK_SYSTICK_EN_Pos                                            22U
+#define PCC_REG_PERION_CLK_REG2X_R_CLK_SYSTICK_EN_Msk                                            (0x1UL << PCC_REG_PERION_CLK_REG2X_R_CLK_SYSTICK_EN_Pos)
+
+#define PCC_REG_PERION_CLK_REG2X_R_10M_SYSTICK_CLK_SRC_SEL_Pos                                   23U
+#define PCC_REG_PERION_CLK_REG2X_R_10M_SYSTICK_CLK_SRC_SEL_Msk                                   (0x1UL << PCC_REG_PERION_CLK_REG2X_R_10M_SYSTICK_CLK_SRC_SEL_Pos)
+
+#define PCC_REG_PERION_CLK_REG2X_R_40M_AUDIO_CLK_SRC_SEL_Pos                                     24U
+#define PCC_REG_PERION_CLK_REG2X_R_40M_AUDIO_CLK_SRC_SEL_Msk                                     (0x1UL << PCC_REG_PERION_CLK_REG2X_R_40M_AUDIO_CLK_SRC_SEL_Pos)
+
+#define PCC_REG_PERION_CLK_REG2X_R_TIMER_CLK_F40M_SRC_SEL_Pos                                    25U
+#define PCC_REG_PERION_CLK_REG2X_R_TIMER_CLK_F40M_SRC_SEL_Msk                                    (0x1UL << PCC_REG_PERION_CLK_REG2X_R_TIMER_CLK_F40M_SRC_SEL_Pos)
+
+#define PCC_REG_PERION_CLK_REG2X_R_UART_CLK_SRC_SEL_Pos                                          26U
+#define PCC_REG_PERION_CLK_REG2X_R_UART_CLK_SRC_SEL_Msk                                          (0x1UL << PCC_REG_PERION_CLK_REG2X_R_UART_CLK_SRC_SEL_Pos)
+
+#define PCC_REG_PERION_CLK_REG2X_DUMMY3_Pos                                                      27U
+#define PCC_REG_PERION_CLK_REG2X_DUMMY3_Msk                                                      (0x1FUL << PCC_REG_PERION_CLK_REG2X_DUMMY3_Pos)
+
+/* 0x20C    0x4000_020c
+    23:0    R/W     RESERVED                                        24'h0
+    31:24   R/W     DUMMY4                                          8'h0
+ */
+typedef union _PCC_REG_PERION_CLK_REG3X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED: 24;
+        uint32_t DUMMY4: 8;
+    };
+} PCC_REG_PERION_CLK_REG3X_TYPE;
+
+/*0x4000_020c PCC_REG_PERION_CLK_REG3X*/
+#define PCC_REG_PERION_CLK_REG3X_RESERVED_Pos                                                    0U
+#define PCC_REG_PERION_CLK_REG3X_RESERVED_Msk                                                    (0xFFFFFFUL << PCC_REG_PERION_CLK_REG3X_RESERVED_Pos)
+
+#define PCC_REG_PERION_CLK_REG3X_DUMMY4_Pos                                                      24U
+#define PCC_REG_PERION_CLK_REG3X_DUMMY4_Msk                                                      (0xFFUL << PCC_REG_PERION_CLK_REG3X_DUMMY4_Pos)
+
+/* 0x210    0x4000_0210
+    0       R/W     R_LS_MCU_ROM                                    1'b0
+    1       R/W     R_CODEC_STANDALONE                              1'b0
+    11:2    R/W     RESERVED                                        10'h0
+    12      R/W     FORCE_QACTIVE_UART0                             1'h0
+    13      R/W     FORCE_QACTIVE_UART1                             1'h0
+    14      R/W     FORCE_QACTIVE_UART2                             1'h0
+    15      R/W     FORCE_QACTIVE_UART3                             1'h0
+    16      R/W     FORCE_QACTIVE_IRRC                              1'h0
+    17      R/W     FORCE_QACTIVE_AUDIO                             1'h0
+    18      R/W     FORCE_QACTIVE_TIMER1                            1'h0
+    19      R/W     FORCE_QACTIVE_TIMER2                            1'h0
+    20      R/W     FORCE_QACTIVE_TIMER3                            1'h0
+    21      R/W     FORCE_QACTIVE_TIMER4                            1'h0
+    22      R/W     FORCE_QACTIVE_TIMER5                            1'h0
+    23      R/W     FORCE_QACTIVE_TIMER6                            1'h0
+    24      R/W     FORCE_QACTIVE_TIMER7                            1'h0
+    25      R/W     FORCE_QACTIVE_TIMER8                            1'h0
+    26      R/W     FORCE_QACTIVE_TIMER9                            1'h0
+    27      R/W     FORCE_QACTIVE_TIMER10                           1'h0
+    28      R/W     FORCE_QACTIVE_TIMER11                           1'h0
+    29      R/W     FORCE_QACTIVE_ETIMER                            1'h0
+    30      R/W     FORCE_QACTIVE_RFC                               1'h0
+    31      R/W     FORCE_QACTIVE_MODEM                             1'h0
+ */
+typedef union _PCC_REG_PERION_CLK_REG4X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t R_LS_MCU_ROM: 1;
+        uint32_t R_CODEC_STANDALONE: 1;
+        uint32_t RESERVED: 10;
+        uint32_t FORCE_QACTIVE_UART0: 1;
+        uint32_t FORCE_QACTIVE_UART1: 1;
+        uint32_t FORCE_QACTIVE_UART2: 1;
+        uint32_t FORCE_QACTIVE_UART3: 1;
+        uint32_t FORCE_QACTIVE_IRRC: 1;
+        uint32_t FORCE_QACTIVE_AUDIO: 1;
+        uint32_t FORCE_QACTIVE_TIMER1: 1;
+        uint32_t FORCE_QACTIVE_TIMER2: 1;
+        uint32_t FORCE_QACTIVE_TIMER3: 1;
+        uint32_t FORCE_QACTIVE_TIMER4: 1;
+        uint32_t FORCE_QACTIVE_TIMER5: 1;
+        uint32_t FORCE_QACTIVE_TIMER6: 1;
+        uint32_t FORCE_QACTIVE_TIMER7: 1;
+        uint32_t FORCE_QACTIVE_TIMER8: 1;
+        uint32_t FORCE_QACTIVE_TIMER9: 1;
+        uint32_t FORCE_QACTIVE_TIMER10: 1;
+        uint32_t FORCE_QACTIVE_TIMER11: 1;
+        uint32_t FORCE_QACTIVE_ETIMER: 1;
+        uint32_t FORCE_QACTIVE_RFC: 1;
+        uint32_t FORCE_QACTIVE_MODEM: 1;
+    };
+} PCC_REG_PERION_CLK_REG4X_TYPE;
+
+/*0x4000_0210 PCC_REG_PERION_CLK_REG4X*/
+#define PCC_REG_PERION_CLK_REG4X_R_LS_MCU_ROM_Pos                                                0U
+#define PCC_REG_PERION_CLK_REG4X_R_LS_MCU_ROM_Msk                                                (0x1UL << PCC_REG_PERION_CLK_REG4X_R_LS_MCU_ROM_Pos)
+
+#define PCC_REG_PERION_CLK_REG4X_R_CODEC_STANDALONE_Pos                                          1U
+#define PCC_REG_PERION_CLK_REG4X_R_CODEC_STANDALONE_Msk                                          (0x1UL << PCC_REG_PERION_CLK_REG4X_R_CODEC_STANDALONE_Pos)
+
+#define PCC_REG_PERION_CLK_REG4X_RESERVED_Pos                                                    2U
+#define PCC_REG_PERION_CLK_REG4X_RESERVED_Msk                                                    (0x3FFUL << PCC_REG_PERION_CLK_REG4X_RESERVED_Pos)
+
+#define PCC_REG_PERION_CLK_REG4X_FORCE_QACTIVE_UART0_Pos                                         12U
+#define PCC_REG_PERION_CLK_REG4X_FORCE_QACTIVE_UART0_Msk                                         (0x1UL << PCC_REG_PERION_CLK_REG4X_FORCE_QACTIVE_UART0_Pos)
+
+#define PCC_REG_PERION_CLK_REG4X_FORCE_QACTIVE_UART1_Pos                                         13U
+#define PCC_REG_PERION_CLK_REG4X_FORCE_QACTIVE_UART1_Msk                                         (0x1UL << PCC_REG_PERION_CLK_REG4X_FORCE_QACTIVE_UART1_Pos)
+
+#define PCC_REG_PERION_CLK_REG4X_FORCE_QACTIVE_UART2_Pos                                         14U
+#define PCC_REG_PERION_CLK_REG4X_FORCE_QACTIVE_UART2_Msk                                         (0x1UL << PCC_REG_PERION_CLK_REG4X_FORCE_QACTIVE_UART2_Pos)
+
+#define PCC_REG_PERION_CLK_REG4X_FORCE_QACTIVE_UART3_Pos                                         15U
+#define PCC_REG_PERION_CLK_REG4X_FORCE_QACTIVE_UART3_Msk                                         (0x1UL << PCC_REG_PERION_CLK_REG4X_FORCE_QACTIVE_UART3_Pos)
+
+#define PCC_REG_PERION_CLK_REG4X_FORCE_QACTIVE_IRRC_Pos                                          16U
+#define PCC_REG_PERION_CLK_REG4X_FORCE_QACTIVE_IRRC_Msk                                          (0x1UL << PCC_REG_PERION_CLK_REG4X_FORCE_QACTIVE_IRRC_Pos)
+
+#define PCC_REG_PERION_CLK_REG4X_FORCE_QACTIVE_AUDIO_Pos                                         17U
+#define PCC_REG_PERION_CLK_REG4X_FORCE_QACTIVE_AUDIO_Msk                                         (0x1UL << PCC_REG_PERION_CLK_REG4X_FORCE_QACTIVE_AUDIO_Pos)
+
+#define PCC_REG_PERION_CLK_REG4X_FORCE_QACTIVE_TIMER1_Pos                                        18U
+#define PCC_REG_PERION_CLK_REG4X_FORCE_QACTIVE_TIMER1_Msk                                        (0x1UL << PCC_REG_PERION_CLK_REG4X_FORCE_QACTIVE_TIMER1_Pos)
+
+#define PCC_REG_PERION_CLK_REG4X_FORCE_QACTIVE_TIMER2_Pos                                        19U
+#define PCC_REG_PERION_CLK_REG4X_FORCE_QACTIVE_TIMER2_Msk                                        (0x1UL << PCC_REG_PERION_CLK_REG4X_FORCE_QACTIVE_TIMER2_Pos)
+
+#define PCC_REG_PERION_CLK_REG4X_FORCE_QACTIVE_TIMER3_Pos                                        20U
+#define PCC_REG_PERION_CLK_REG4X_FORCE_QACTIVE_TIMER3_Msk                                        (0x1UL << PCC_REG_PERION_CLK_REG4X_FORCE_QACTIVE_TIMER3_Pos)
+
+#define PCC_REG_PERION_CLK_REG4X_FORCE_QACTIVE_TIMER4_Pos                                        21U
+#define PCC_REG_PERION_CLK_REG4X_FORCE_QACTIVE_TIMER4_Msk                                        (0x1UL << PCC_REG_PERION_CLK_REG4X_FORCE_QACTIVE_TIMER4_Pos)
+
+#define PCC_REG_PERION_CLK_REG4X_FORCE_QACTIVE_TIMER5_Pos                                        22U
+#define PCC_REG_PERION_CLK_REG4X_FORCE_QACTIVE_TIMER5_Msk                                        (0x1UL << PCC_REG_PERION_CLK_REG4X_FORCE_QACTIVE_TIMER5_Pos)
+
+#define PCC_REG_PERION_CLK_REG4X_FORCE_QACTIVE_TIMER6_Pos                                        23U
+#define PCC_REG_PERION_CLK_REG4X_FORCE_QACTIVE_TIMER6_Msk                                        (0x1UL << PCC_REG_PERION_CLK_REG4X_FORCE_QACTIVE_TIMER6_Pos)
+
+#define PCC_REG_PERION_CLK_REG4X_FORCE_QACTIVE_TIMER7_Pos                                        24U
+#define PCC_REG_PERION_CLK_REG4X_FORCE_QACTIVE_TIMER7_Msk                                        (0x1UL << PCC_REG_PERION_CLK_REG4X_FORCE_QACTIVE_TIMER7_Pos)
+
+#define PCC_REG_PERION_CLK_REG4X_FORCE_QACTIVE_TIMER8_Pos                                        25U
+#define PCC_REG_PERION_CLK_REG4X_FORCE_QACTIVE_TIMER8_Msk                                        (0x1UL << PCC_REG_PERION_CLK_REG4X_FORCE_QACTIVE_TIMER8_Pos)
+
+#define PCC_REG_PERION_CLK_REG4X_FORCE_QACTIVE_TIMER9_Pos                                        26U
+#define PCC_REG_PERION_CLK_REG4X_FORCE_QACTIVE_TIMER9_Msk                                        (0x1UL << PCC_REG_PERION_CLK_REG4X_FORCE_QACTIVE_TIMER9_Pos)
+
+#define PCC_REG_PERION_CLK_REG4X_FORCE_QACTIVE_TIMER10_Pos                                       27U
+#define PCC_REG_PERION_CLK_REG4X_FORCE_QACTIVE_TIMER10_Msk                                       (0x1UL << PCC_REG_PERION_CLK_REG4X_FORCE_QACTIVE_TIMER10_Pos)
+
+#define PCC_REG_PERION_CLK_REG4X_FORCE_QACTIVE_TIMER11_Pos                                       28U
+#define PCC_REG_PERION_CLK_REG4X_FORCE_QACTIVE_TIMER11_Msk                                       (0x1UL << PCC_REG_PERION_CLK_REG4X_FORCE_QACTIVE_TIMER11_Pos)
+
+#define PCC_REG_PERION_CLK_REG4X_FORCE_QACTIVE_ETIMER_Pos                                        29U
+#define PCC_REG_PERION_CLK_REG4X_FORCE_QACTIVE_ETIMER_Msk                                        (0x1UL << PCC_REG_PERION_CLK_REG4X_FORCE_QACTIVE_ETIMER_Pos)
+
+#define PCC_REG_PERION_CLK_REG4X_FORCE_QACTIVE_RFC_Pos                                           30U
+#define PCC_REG_PERION_CLK_REG4X_FORCE_QACTIVE_RFC_Msk                                           (0x1UL << PCC_REG_PERION_CLK_REG4X_FORCE_QACTIVE_RFC_Pos)
+
+#define PCC_REG_PERION_CLK_REG4X_FORCE_QACTIVE_MODEM_Pos                                         31U
+#define PCC_REG_PERION_CLK_REG4X_FORCE_QACTIVE_MODEM_Msk                                         (0x1UL << PCC_REG_PERION_CLK_REG4X_FORCE_QACTIVE_MODEM_Pos)
+
+/* 0x214    0x4000_0214
+    6:0     R/W     R_PRO_AHB_WAIT_CNT                              7'h3
+    26:7    R/W     RESERVED                                        20'b0
+    31:27   R/W     DUMMY6                                          5'b0
+ */
+typedef union _PCC_REG_PERION_CLK_REG5X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t R_PRO_AHB_WAIT_CNT: 7;
+        uint32_t RESERVED: 20;
+        uint32_t DUMMY6: 5;
+    };
+} PCC_REG_PERION_CLK_REG5X_TYPE;
+
+/*0x4000_0214 PCC_REG_PERION_CLK_REG5X*/
+#define PCC_REG_PERION_CLK_REG5X_R_PRO_AHB_WAIT_CNT_Pos                                          0U
+#define PCC_REG_PERION_CLK_REG5X_R_PRO_AHB_WAIT_CNT_Msk                                          (0x7FUL << PCC_REG_PERION_CLK_REG5X_R_PRO_AHB_WAIT_CNT_Pos)
+
+#define PCC_REG_PERION_CLK_REG5X_RESERVED_Pos                                                    7U
+#define PCC_REG_PERION_CLK_REG5X_RESERVED_Msk                                                    (0xFFFFFUL << PCC_REG_PERION_CLK_REG5X_RESERVED_Pos)
+
+#define PCC_REG_PERION_CLK_REG5X_DUMMY6_Pos                                                      27U
+#define PCC_REG_PERION_CLK_REG5X_DUMMY6_Msk                                                      (0x1FUL << PCC_REG_PERION_CLK_REG5X_DUMMY6_Pos)
+
+/* 0x218    0x4000_0218
+    7:0     R/W     ENTRY_DELAY_CORE1_DEV_RNG                       8'b0
+    8       R/W     RESERVED_12                                     1'b0
+    9       R/W     RESERVED_11                                     1'b1
+    10      R/W     RESERVED_10                                     1'b0
+    11      R/W     RESERVED_9                                      1'b1
+    12      R/W     RESERVED_8                                      1'b1
+    13      R/W     RESERVED_7                                      1'b0
+    14      R/W     RESERVED_6                                      1'b1
+    15      R/W     RESERVED_5                                      1'b0
+    16      R/W     R_CKE_RNG                                       1'b0
+    17      R/W     RNG_CLK_FORCE                                   1'b0
+    20:18   R/W     RSVD_1                                          3'b000
+    21      R/W     RESERVED_4                                      1'b0
+    22      R/W     RESERVED_3                                      1'b0
+    23      R/W     RESERVED_2                                      1'b0
+    24      R/W     RESERVED_1                                      1'b0
+    27:25   R/W     R_RNG_SFOSC_DIV_SEL                             3'h0
+    30:28   R/W     RSVD                                            3'b000
+    31      R/W     RESERVED                                        1'b0
+ */
+typedef union _PCC_REG_TRNG_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t ENTRY_DELAY_CORE1_DEV_RNG: 8;
+        uint32_t RESERVED_12: 1;
+        uint32_t RESERVED_11: 1;
+        uint32_t RESERVED_10: 1;
+        uint32_t RESERVED_9: 1;
+        uint32_t RESERVED_8: 1;
+        uint32_t RESERVED_7: 1;
+        uint32_t RESERVED_6: 1;
+        uint32_t RESERVED_5: 1;
+        uint32_t R_CKE_RNG: 1;
+        uint32_t RNG_CLK_FORCE: 1;
+        uint32_t RSVD_1: 3;
+        uint32_t RESERVED_4: 1;
+        uint32_t RESERVED_3: 1;
+        uint32_t RESERVED_2: 1;
+        uint32_t RESERVED_1: 1;
+        uint32_t R_RNG_SFOSC_DIV_SEL: 3;
+        uint32_t RSVD: 3;
+        uint32_t RESERVED: 1;
+    };
+} PCC_REG_TRNG_TYPE;
+
+/*0x4000_0218 PCC_REG_TRNG*/
+#define PCC_REG_TRNG_ENTRY_DELAY_CORE1_DEV_RNG_Pos                                               0U
+#define PCC_REG_TRNG_ENTRY_DELAY_CORE1_DEV_RNG_Msk                                               (0xFFUL << PCC_REG_TRNG_ENTRY_DELAY_CORE1_DEV_RNG_Pos)
+
+#define PCC_REG_TRNG_RESERVED_12_Pos                                                             8U
+#define PCC_REG_TRNG_RESERVED_12_Msk                                                             (0x1UL << PCC_REG_TRNG_RESERVED_12_Pos)
+
+#define PCC_REG_TRNG_RESERVED_11_Pos                                                             9U
+#define PCC_REG_TRNG_RESERVED_11_Msk                                                             (0x1UL << PCC_REG_TRNG_RESERVED_11_Pos)
+
+#define PCC_REG_TRNG_RESERVED_10_Pos                                                             10U
+#define PCC_REG_TRNG_RESERVED_10_Msk                                                             (0x1UL << PCC_REG_TRNG_RESERVED_10_Pos)
+
+#define PCC_REG_TRNG_RESERVED_9_Pos                                                              11U
+#define PCC_REG_TRNG_RESERVED_9_Msk                                                              (0x1UL << PCC_REG_TRNG_RESERVED_9_Pos)
+
+#define PCC_REG_TRNG_RESERVED_8_Pos                                                              12U
+#define PCC_REG_TRNG_RESERVED_8_Msk                                                              (0x1UL << PCC_REG_TRNG_RESERVED_8_Pos)
+
+#define PCC_REG_TRNG_RESERVED_7_Pos                                                              13U
+#define PCC_REG_TRNG_RESERVED_7_Msk                                                              (0x1UL << PCC_REG_TRNG_RESERVED_7_Pos)
+
+#define PCC_REG_TRNG_RESERVED_6_Pos                                                              14U
+#define PCC_REG_TRNG_RESERVED_6_Msk                                                              (0x1UL << PCC_REG_TRNG_RESERVED_6_Pos)
+
+#define PCC_REG_TRNG_RESERVED_5_Pos                                                              15U
+#define PCC_REG_TRNG_RESERVED_5_Msk                                                              (0x1UL << PCC_REG_TRNG_RESERVED_5_Pos)
+
+#define PCC_REG_TRNG_R_CKE_RNG_Pos                                                               16U
+#define PCC_REG_TRNG_R_CKE_RNG_Msk                                                               (0x1UL << PCC_REG_TRNG_R_CKE_RNG_Pos)
+
+#define PCC_REG_TRNG_RNG_CLK_FORCE_Pos                                                           17U
+#define PCC_REG_TRNG_RNG_CLK_FORCE_Msk                                                           (0x1UL << PCC_REG_TRNG_RNG_CLK_FORCE_Pos)
+
+#define PCC_REG_TRNG_RSVD_1_Pos                                                                  18U
+#define PCC_REG_TRNG_RSVD_1_Msk                                                                  (0x7UL << PCC_REG_TRNG_RSVD_1_Pos)
+
+#define PCC_REG_TRNG_RESERVED_4_Pos                                                              21U
+#define PCC_REG_TRNG_RESERVED_4_Msk                                                              (0x1UL << PCC_REG_TRNG_RESERVED_4_Pos)
+
+#define PCC_REG_TRNG_RESERVED_3_Pos                                                              22U
+#define PCC_REG_TRNG_RESERVED_3_Msk                                                              (0x1UL << PCC_REG_TRNG_RESERVED_3_Pos)
+
+#define PCC_REG_TRNG_RESERVED_2_Pos                                                              23U
+#define PCC_REG_TRNG_RESERVED_2_Msk                                                              (0x1UL << PCC_REG_TRNG_RESERVED_2_Pos)
+
+#define PCC_REG_TRNG_RESERVED_1_Pos                                                              24U
+#define PCC_REG_TRNG_RESERVED_1_Msk                                                              (0x1UL << PCC_REG_TRNG_RESERVED_1_Pos)
+
+#define PCC_REG_TRNG_R_RNG_SFOSC_DIV_SEL_Pos                                                     25U
+#define PCC_REG_TRNG_R_RNG_SFOSC_DIV_SEL_Msk                                                     (0x7UL << PCC_REG_TRNG_R_RNG_SFOSC_DIV_SEL_Pos)
+
+#define PCC_REG_TRNG_RSVD_Pos                                                                    28U
+#define PCC_REG_TRNG_RSVD_Msk                                                                    (0x7UL << PCC_REG_TRNG_RSVD_Pos)
+
+#define PCC_REG_TRNG_RESERVED_Pos                                                                31U
+#define PCC_REG_TRNG_RESERVED_Msk                                                                (0x1UL << PCC_REG_TRNG_RESERVED_Pos)
+
+/* 0x21C    0x4000_021c
+    7:0     R/W     ENTRY_DELAY_CORE1_DEV_WDT                       8'b0
+    8       R/W     RESERVED_16                                     1'b0
+    9       R/W     RESERVED_15                                     1'b0
+    10      R/W     RESERVED_14                                     1'b0
+    11      R/W     RESERVED_13                                     1'b0
+    12      R/W     RESERVED_12                                     1'b1
+    13      R/W     RESERVED_11                                     1'b0
+    14      R/W     RESERVED_10                                     1'b1
+    15      R/W     RESERVED_9                                      1'h0
+    16      R/W     RESERVED_8                                      1'b0
+    17      R/W     RESERVED_7                                      1'b0
+    18      R/W     WDT_CLK_FORCE                                   1'b0
+    21:19   R/W     RSVD_1                                          3'b000
+    22      R/W     RESERVED_6                                      1'b0
+    23      R/W     RESERVED_5                                      1'b0
+    24      R/W     RESERVED_4                                      1'b0
+    25      R/W     RESERVED_3                                      1'b0
+    26      R/W     RESERVED_2                                      1'b0
+    27      R/W     RESERVED_1                                      1'b0
+    30:28   R/W     RSVD                                            3'b000
+    31      R/W     RESERVED                                        1'b0
+ */
+typedef union _PCC_REG_CORE_WDT_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t ENTRY_DELAY_CORE1_DEV_WDT: 8;
+        uint32_t RESERVED_16: 1;
+        uint32_t RESERVED_15: 1;
+        uint32_t RESERVED_14: 1;
+        uint32_t RESERVED_13: 1;
+        uint32_t RESERVED_12: 1;
+        uint32_t RESERVED_11: 1;
+        uint32_t RESERVED_10: 1;
+        uint32_t RESERVED_9: 1;
+        uint32_t RESERVED_8: 1;
+        uint32_t RESERVED_7: 1;
+        uint32_t WDT_CLK_FORCE: 1;
+        uint32_t RSVD_1: 3;
+        uint32_t RESERVED_6: 1;
+        uint32_t RESERVED_5: 1;
+        uint32_t RESERVED_4: 1;
+        uint32_t RESERVED_3: 1;
+        uint32_t RESERVED_2: 1;
+        uint32_t RESERVED_1: 1;
+        uint32_t RSVD: 3;
+        uint32_t RESERVED: 1;
+    };
+} PCC_REG_CORE_WDT_TYPE;
+
+/*0x4000_021c PCC_REG_CORE_WDT*/
+#define PCC_REG_CORE_WDT_ENTRY_DELAY_CORE1_DEV_WDT_Pos                                           0U
+#define PCC_REG_CORE_WDT_ENTRY_DELAY_CORE1_DEV_WDT_Msk                                           (0xFFUL << PCC_REG_CORE_WDT_ENTRY_DELAY_CORE1_DEV_WDT_Pos)
+
+#define PCC_REG_CORE_WDT_RESERVED_16_Pos                                                         8U
+#define PCC_REG_CORE_WDT_RESERVED_16_Msk                                                         (0x1UL << PCC_REG_CORE_WDT_RESERVED_16_Pos)
+
+#define PCC_REG_CORE_WDT_RESERVED_15_Pos                                                         9U
+#define PCC_REG_CORE_WDT_RESERVED_15_Msk                                                         (0x1UL << PCC_REG_CORE_WDT_RESERVED_15_Pos)
+
+#define PCC_REG_CORE_WDT_RESERVED_14_Pos                                                         10U
+#define PCC_REG_CORE_WDT_RESERVED_14_Msk                                                         (0x1UL << PCC_REG_CORE_WDT_RESERVED_14_Pos)
+
+#define PCC_REG_CORE_WDT_RESERVED_13_Pos                                                         11U
+#define PCC_REG_CORE_WDT_RESERVED_13_Msk                                                         (0x1UL << PCC_REG_CORE_WDT_RESERVED_13_Pos)
+
+#define PCC_REG_CORE_WDT_RESERVED_12_Pos                                                         12U
+#define PCC_REG_CORE_WDT_RESERVED_12_Msk                                                         (0x1UL << PCC_REG_CORE_WDT_RESERVED_12_Pos)
+
+#define PCC_REG_CORE_WDT_RESERVED_11_Pos                                                         13U
+#define PCC_REG_CORE_WDT_RESERVED_11_Msk                                                         (0x1UL << PCC_REG_CORE_WDT_RESERVED_11_Pos)
+
+#define PCC_REG_CORE_WDT_RESERVED_10_Pos                                                         14U
+#define PCC_REG_CORE_WDT_RESERVED_10_Msk                                                         (0x1UL << PCC_REG_CORE_WDT_RESERVED_10_Pos)
+
+#define PCC_REG_CORE_WDT_RESERVED_9_Pos                                                          15U
+#define PCC_REG_CORE_WDT_RESERVED_9_Msk                                                          (0x1UL << PCC_REG_CORE_WDT_RESERVED_9_Pos)
+
+#define PCC_REG_CORE_WDT_RESERVED_8_Pos                                                          16U
+#define PCC_REG_CORE_WDT_RESERVED_8_Msk                                                          (0x1UL << PCC_REG_CORE_WDT_RESERVED_8_Pos)
+
+#define PCC_REG_CORE_WDT_RESERVED_7_Pos                                                          17U
+#define PCC_REG_CORE_WDT_RESERVED_7_Msk                                                          (0x1UL << PCC_REG_CORE_WDT_RESERVED_7_Pos)
+
+#define PCC_REG_CORE_WDT_WDT_CLK_FORCE_Pos                                                       18U
+#define PCC_REG_CORE_WDT_WDT_CLK_FORCE_Msk                                                       (0x1UL << PCC_REG_CORE_WDT_WDT_CLK_FORCE_Pos)
+
+#define PCC_REG_CORE_WDT_RSVD_1_Pos                                                              19U
+#define PCC_REG_CORE_WDT_RSVD_1_Msk                                                              (0x7UL << PCC_REG_CORE_WDT_RSVD_1_Pos)
+
+#define PCC_REG_CORE_WDT_RESERVED_6_Pos                                                          22U
+#define PCC_REG_CORE_WDT_RESERVED_6_Msk                                                          (0x1UL << PCC_REG_CORE_WDT_RESERVED_6_Pos)
+
+#define PCC_REG_CORE_WDT_RESERVED_5_Pos                                                          23U
+#define PCC_REG_CORE_WDT_RESERVED_5_Msk                                                          (0x1UL << PCC_REG_CORE_WDT_RESERVED_5_Pos)
+
+#define PCC_REG_CORE_WDT_RESERVED_4_Pos                                                          24U
+#define PCC_REG_CORE_WDT_RESERVED_4_Msk                                                          (0x1UL << PCC_REG_CORE_WDT_RESERVED_4_Pos)
+
+#define PCC_REG_CORE_WDT_RESERVED_3_Pos                                                          25U
+#define PCC_REG_CORE_WDT_RESERVED_3_Msk                                                          (0x1UL << PCC_REG_CORE_WDT_RESERVED_3_Pos)
+
+#define PCC_REG_CORE_WDT_RESERVED_2_Pos                                                          26U
+#define PCC_REG_CORE_WDT_RESERVED_2_Msk                                                          (0x1UL << PCC_REG_CORE_WDT_RESERVED_2_Pos)
+
+#define PCC_REG_CORE_WDT_RESERVED_1_Pos                                                          27U
+#define PCC_REG_CORE_WDT_RESERVED_1_Msk                                                          (0x1UL << PCC_REG_CORE_WDT_RESERVED_1_Pos)
+
+#define PCC_REG_CORE_WDT_RSVD_Pos                                                                28U
+#define PCC_REG_CORE_WDT_RSVD_Msk                                                                (0x7UL << PCC_REG_CORE_WDT_RSVD_Pos)
+
+#define PCC_REG_CORE_WDT_RESERVED_Pos                                                            31U
+#define PCC_REG_CORE_WDT_RESERVED_Msk                                                            (0x1UL << PCC_REG_CORE_WDT_RESERVED_Pos)
+
+/* 0x220    0x4000_0220
+    7:0     R/W     ENTRY_DELAY_CORE1_DEV_AES                       8'b0
+    8       R/W     RESERVED_13                                     1'b0
+    9       R/W     RESERVED_12                                     1'b0
+    10      R/W     RESERVED_11                                     1'b0
+    11      R/W     RESERVED_10                                     1'b1
+    12      R/W     RESERVED_9                                      1'b1
+    15:13   R/W     RSVD_2                                          3'h0
+    16      R/W     RESERVED_8                                      1'b0
+    17      R/W     RESERVED_7                                      1'b0
+    18      R/W     AES_CLK_FORCE                                   1'b0
+    21:19   R/W     RSVD_1                                          3'b000
+    22      R/W     RESERVED_6                                      1'b0
+    23      R/W     RESERVED_5                                      1'b0
+    24      R/W     RESERVED_4                                      1'b0
+    25      R/W     RESERVED_3                                      1'b0
+    26      R/W     RESERVED_2                                      1'b0
+    27      R/W     RESERVED_1                                      1'b0
+    30:28   R/W     RSVD                                            3'b000
+    31      R/W     RESERVED                                        1'b0
+ */
+typedef union _PCC_REG_AES_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t ENTRY_DELAY_CORE1_DEV_AES: 8;
+        uint32_t RESERVED_13: 1;
+        uint32_t RESERVED_12: 1;
+        uint32_t RESERVED_11: 1;
+        uint32_t RESERVED_10: 1;
+        uint32_t RESERVED_9: 1;
+        uint32_t RSVD_2: 3;
+        uint32_t RESERVED_8: 1;
+        uint32_t RESERVED_7: 1;
+        uint32_t AES_CLK_FORCE: 1;
+        uint32_t RSVD_1: 3;
+        uint32_t RESERVED_6: 1;
+        uint32_t RESERVED_5: 1;
+        uint32_t RESERVED_4: 1;
+        uint32_t RESERVED_3: 1;
+        uint32_t RESERVED_2: 1;
+        uint32_t RESERVED_1: 1;
+        uint32_t RSVD: 3;
+        uint32_t RESERVED: 1;
+    };
+} PCC_REG_AES_TYPE;
+
+/*0x4000_0220 PCC_REG_AES*/
+#define PCC_REG_AES_ENTRY_DELAY_CORE1_DEV_AES_Pos                                                0U
+#define PCC_REG_AES_ENTRY_DELAY_CORE1_DEV_AES_Msk                                                (0xFFUL << PCC_REG_AES_ENTRY_DELAY_CORE1_DEV_AES_Pos)
+
+#define PCC_REG_AES_RESERVED_13_Pos                                                              8U
+#define PCC_REG_AES_RESERVED_13_Msk                                                              (0x1UL << PCC_REG_AES_RESERVED_13_Pos)
+
+#define PCC_REG_AES_RESERVED_12_Pos                                                              9U
+#define PCC_REG_AES_RESERVED_12_Msk                                                              (0x1UL << PCC_REG_AES_RESERVED_12_Pos)
+
+#define PCC_REG_AES_RESERVED_11_Pos                                                              10U
+#define PCC_REG_AES_RESERVED_11_Msk                                                              (0x1UL << PCC_REG_AES_RESERVED_11_Pos)
+
+#define PCC_REG_AES_RESERVED_10_Pos                                                              11U
+#define PCC_REG_AES_RESERVED_10_Msk                                                              (0x1UL << PCC_REG_AES_RESERVED_10_Pos)
+
+#define PCC_REG_AES_RESERVED_9_Pos                                                               12U
+#define PCC_REG_AES_RESERVED_9_Msk                                                               (0x1UL << PCC_REG_AES_RESERVED_9_Pos)
+
+#define PCC_REG_AES_RSVD_2_Pos                                                                   13U
+#define PCC_REG_AES_RSVD_2_Msk                                                                   (0x7UL << PCC_REG_AES_RSVD_2_Pos)
+
+#define PCC_REG_AES_RESERVED_8_Pos                                                               16U
+#define PCC_REG_AES_RESERVED_8_Msk                                                               (0x1UL << PCC_REG_AES_RESERVED_8_Pos)
+
+#define PCC_REG_AES_RESERVED_7_Pos                                                               17U
+#define PCC_REG_AES_RESERVED_7_Msk                                                               (0x1UL << PCC_REG_AES_RESERVED_7_Pos)
+
+#define PCC_REG_AES_AES_CLK_FORCE_Pos                                                            18U
+#define PCC_REG_AES_AES_CLK_FORCE_Msk                                                            (0x1UL << PCC_REG_AES_AES_CLK_FORCE_Pos)
+
+#define PCC_REG_AES_RSVD_1_Pos                                                                   19U
+#define PCC_REG_AES_RSVD_1_Msk                                                                   (0x7UL << PCC_REG_AES_RSVD_1_Pos)
+
+#define PCC_REG_AES_RESERVED_6_Pos                                                               22U
+#define PCC_REG_AES_RESERVED_6_Msk                                                               (0x1UL << PCC_REG_AES_RESERVED_6_Pos)
+
+#define PCC_REG_AES_RESERVED_5_Pos                                                               23U
+#define PCC_REG_AES_RESERVED_5_Msk                                                               (0x1UL << PCC_REG_AES_RESERVED_5_Pos)
+
+#define PCC_REG_AES_RESERVED_4_Pos                                                               24U
+#define PCC_REG_AES_RESERVED_4_Msk                                                               (0x1UL << PCC_REG_AES_RESERVED_4_Pos)
+
+#define PCC_REG_AES_RESERVED_3_Pos                                                               25U
+#define PCC_REG_AES_RESERVED_3_Msk                                                               (0x1UL << PCC_REG_AES_RESERVED_3_Pos)
+
+#define PCC_REG_AES_RESERVED_2_Pos                                                               26U
+#define PCC_REG_AES_RESERVED_2_Msk                                                               (0x1UL << PCC_REG_AES_RESERVED_2_Pos)
+
+#define PCC_REG_AES_RESERVED_1_Pos                                                               27U
+#define PCC_REG_AES_RESERVED_1_Msk                                                               (0x1UL << PCC_REG_AES_RESERVED_1_Pos)
+
+#define PCC_REG_AES_RSVD_Pos                                                                     28U
+#define PCC_REG_AES_RSVD_Msk                                                                     (0x7UL << PCC_REG_AES_RSVD_Pos)
+
+#define PCC_REG_AES_RESERVED_Pos                                                                 31U
+#define PCC_REG_AES_RESERVED_Msk                                                                 (0x1UL << PCC_REG_AES_RESERVED_Pos)
+
+/* 0x224    0x4000_0224
+    7:0     R/W     ENTRY_DELAY_CORE1_DEV_SHA256                    8'b0
+    8       R/W     RESERVED_13                                     1'b0
+    9       R/W     RESERVED_12                                     1'b0
+    10      R/W     RESERVED_11                                     1'b0
+    11      R/W     RESERVED_10                                     1'b1
+    12      R/W     RESERVED_9                                      1'b1
+    15:13   R/W     RSVD_2                                          3'h0
+    16      R/W     RESERVED_8                                      1'b0
+    17      R/W     RESERVED_7                                      1'b0
+    18      R/W     SHA256_CLK_FORCE                                1'b0
+    21:19   R/W     RSVD_1                                          3'b000
+    22      R/W     RESERVED_6                                      1'b0
+    23      R/W     RESERVED_5                                      1'b0
+    24      R/W     RESERVED_4                                      1'b0
+    25      R/W     RESERVED_3                                      1'b0
+    26      R/W     RESERVED_2                                      1'b0
+    27      R/W     RESERVED_1                                      1'b0
+    30:28   R/W     RSVD                                            3'b000
+    31      R/W     RESERVED                                        1'b0
+ */
+typedef union _PCC_REG_SHA256_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t ENTRY_DELAY_CORE1_DEV_SHA256: 8;
+        uint32_t RESERVED_13: 1;
+        uint32_t RESERVED_12: 1;
+        uint32_t RESERVED_11: 1;
+        uint32_t RESERVED_10: 1;
+        uint32_t RESERVED_9: 1;
+        uint32_t RSVD_2: 3;
+        uint32_t RESERVED_8: 1;
+        uint32_t RESERVED_7: 1;
+        uint32_t SHA256_CLK_FORCE: 1;
+        uint32_t RSVD_1: 3;
+        uint32_t RESERVED_6: 1;
+        uint32_t RESERVED_5: 1;
+        uint32_t RESERVED_4: 1;
+        uint32_t RESERVED_3: 1;
+        uint32_t RESERVED_2: 1;
+        uint32_t RESERVED_1: 1;
+        uint32_t RSVD: 3;
+        uint32_t RESERVED: 1;
+    };
+} PCC_REG_SHA256_TYPE;
+
+/*0x4000_0224 PCC_REG_SHA256*/
+#define PCC_REG_SHA256_ENTRY_DELAY_CORE1_DEV_SHA256_Pos                                          0U
+#define PCC_REG_SHA256_ENTRY_DELAY_CORE1_DEV_SHA256_Msk                                          (0xFFUL << PCC_REG_SHA256_ENTRY_DELAY_CORE1_DEV_SHA256_Pos)
+
+#define PCC_REG_SHA256_RESERVED_13_Pos                                                           8U
+#define PCC_REG_SHA256_RESERVED_13_Msk                                                           (0x1UL << PCC_REG_SHA256_RESERVED_13_Pos)
+
+#define PCC_REG_SHA256_RESERVED_12_Pos                                                           9U
+#define PCC_REG_SHA256_RESERVED_12_Msk                                                           (0x1UL << PCC_REG_SHA256_RESERVED_12_Pos)
+
+#define PCC_REG_SHA256_RESERVED_11_Pos                                                           10U
+#define PCC_REG_SHA256_RESERVED_11_Msk                                                           (0x1UL << PCC_REG_SHA256_RESERVED_11_Pos)
+
+#define PCC_REG_SHA256_RESERVED_10_Pos                                                           11U
+#define PCC_REG_SHA256_RESERVED_10_Msk                                                           (0x1UL << PCC_REG_SHA256_RESERVED_10_Pos)
+
+#define PCC_REG_SHA256_RESERVED_9_Pos                                                            12U
+#define PCC_REG_SHA256_RESERVED_9_Msk                                                            (0x1UL << PCC_REG_SHA256_RESERVED_9_Pos)
+
+#define PCC_REG_SHA256_RSVD_2_Pos                                                                13U
+#define PCC_REG_SHA256_RSVD_2_Msk                                                                (0x7UL << PCC_REG_SHA256_RSVD_2_Pos)
+
+#define PCC_REG_SHA256_RESERVED_8_Pos                                                            16U
+#define PCC_REG_SHA256_RESERVED_8_Msk                                                            (0x1UL << PCC_REG_SHA256_RESERVED_8_Pos)
+
+#define PCC_REG_SHA256_RESERVED_7_Pos                                                            17U
+#define PCC_REG_SHA256_RESERVED_7_Msk                                                            (0x1UL << PCC_REG_SHA256_RESERVED_7_Pos)
+
+#define PCC_REG_SHA256_SHA256_CLK_FORCE_Pos                                                      18U
+#define PCC_REG_SHA256_SHA256_CLK_FORCE_Msk                                                      (0x1UL << PCC_REG_SHA256_SHA256_CLK_FORCE_Pos)
+
+#define PCC_REG_SHA256_RSVD_1_Pos                                                                19U
+#define PCC_REG_SHA256_RSVD_1_Msk                                                                (0x7UL << PCC_REG_SHA256_RSVD_1_Pos)
+
+#define PCC_REG_SHA256_RESERVED_6_Pos                                                            22U
+#define PCC_REG_SHA256_RESERVED_6_Msk                                                            (0x1UL << PCC_REG_SHA256_RESERVED_6_Pos)
+
+#define PCC_REG_SHA256_RESERVED_5_Pos                                                            23U
+#define PCC_REG_SHA256_RESERVED_5_Msk                                                            (0x1UL << PCC_REG_SHA256_RESERVED_5_Pos)
+
+#define PCC_REG_SHA256_RESERVED_4_Pos                                                            24U
+#define PCC_REG_SHA256_RESERVED_4_Msk                                                            (0x1UL << PCC_REG_SHA256_RESERVED_4_Pos)
+
+#define PCC_REG_SHA256_RESERVED_3_Pos                                                            25U
+#define PCC_REG_SHA256_RESERVED_3_Msk                                                            (0x1UL << PCC_REG_SHA256_RESERVED_3_Pos)
+
+#define PCC_REG_SHA256_RESERVED_2_Pos                                                            26U
+#define PCC_REG_SHA256_RESERVED_2_Msk                                                            (0x1UL << PCC_REG_SHA256_RESERVED_2_Pos)
+
+#define PCC_REG_SHA256_RESERVED_1_Pos                                                            27U
+#define PCC_REG_SHA256_RESERVED_1_Msk                                                            (0x1UL << PCC_REG_SHA256_RESERVED_1_Pos)
+
+#define PCC_REG_SHA256_RSVD_Pos                                                                  28U
+#define PCC_REG_SHA256_RSVD_Msk                                                                  (0x7UL << PCC_REG_SHA256_RSVD_Pos)
+
+#define PCC_REG_SHA256_RESERVED_Pos                                                              31U
+#define PCC_REG_SHA256_RESERVED_Msk                                                              (0x1UL << PCC_REG_SHA256_RESERVED_Pos)
+
+/* 0x228    0x4000_0228
+    7:0     R/W     ENTRY_DELAY_CORE1_DEV_MODEMRFCPI_APB_WRAPPER    8'b0
+    8       R/W     RESERVED_13                                     1'b0
+    9       R/W     RESERVED_12                                     1'b0
+    10      R/W     RESERVED_11                                     1'b0
+    11      R/W     RESERVED_10                                     1'b0
+    12      R/W     RESERVED_9                                      1'b0
+    15:13   R/W     RSVD_2                                          3'h0
+    16      R/W     RESERVED_8                                      1'b0
+    17      R/W     RESERVED_7                                      1'b0
+    18      R/W     MODEMRFCPI_CLK_FORCE                            1'b0
+    21:19   R/W     RSVD_1                                          3'b000
+    22      R/W     RESERVED_6                                      1'b0
+    23      R/W     RESERVED_5                                      1'b0
+    24      R/W     RESERVED_4                                      1'b0
+    25      R/W     RESERVED_3                                      1'b0
+    26      R/W     RESERVED_2                                      1'b0
+    27      R/W     RESERVED_1                                      1'b0
+    30:28   R/W     RSVD                                            3'b000
+    31      R/W     RESERVED                                        1'b0
+ */
+typedef union _PCC_REG_MODEMRFCPI_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t ENTRY_DELAY_CORE1_DEV_MODEMRFCPI_APB_WRAPPER: 8;
+        uint32_t RESERVED_13: 1;
+        uint32_t RESERVED_12: 1;
+        uint32_t RESERVED_11: 1;
+        uint32_t RESERVED_10: 1;
+        uint32_t RESERVED_9: 1;
+        uint32_t RSVD_2: 3;
+        uint32_t RESERVED_8: 1;
+        uint32_t RESERVED_7: 1;
+        uint32_t MODEMRFCPI_CLK_FORCE: 1;
+        uint32_t RSVD_1: 3;
+        uint32_t RESERVED_6: 1;
+        uint32_t RESERVED_5: 1;
+        uint32_t RESERVED_4: 1;
+        uint32_t RESERVED_3: 1;
+        uint32_t RESERVED_2: 1;
+        uint32_t RESERVED_1: 1;
+        uint32_t RSVD: 3;
+        uint32_t RESERVED: 1;
+    };
+} PCC_REG_MODEMRFCPI_TYPE;
+
+/*0x4000_0228 PCC_REG_MODEMRFCPI*/
+#define PCC_REG_MODEMRFCPI_ENTRY_DELAY_CORE1_DEV_MODEMRFCPI_APB_WRAPPER_Pos                      0U
+#define PCC_REG_MODEMRFCPI_ENTRY_DELAY_CORE1_DEV_MODEMRFCPI_APB_WRAPPER_Msk                      (0xFFUL << PCC_REG_MODEMRFCPI_ENTRY_DELAY_CORE1_DEV_MODEMRFCPI_APB_WRAPPER_Pos)
+
+#define PCC_REG_MODEMRFCPI_RESERVED_13_Pos                                                       8U
+#define PCC_REG_MODEMRFCPI_RESERVED_13_Msk                                                       (0x1UL << PCC_REG_MODEMRFCPI_RESERVED_13_Pos)
+
+#define PCC_REG_MODEMRFCPI_RESERVED_12_Pos                                                       9U
+#define PCC_REG_MODEMRFCPI_RESERVED_12_Msk                                                       (0x1UL << PCC_REG_MODEMRFCPI_RESERVED_12_Pos)
+
+#define PCC_REG_MODEMRFCPI_RESERVED_11_Pos                                                       10U
+#define PCC_REG_MODEMRFCPI_RESERVED_11_Msk                                                       (0x1UL << PCC_REG_MODEMRFCPI_RESERVED_11_Pos)
+
+#define PCC_REG_MODEMRFCPI_RESERVED_10_Pos                                                       11U
+#define PCC_REG_MODEMRFCPI_RESERVED_10_Msk                                                       (0x1UL << PCC_REG_MODEMRFCPI_RESERVED_10_Pos)
+
+#define PCC_REG_MODEMRFCPI_RESERVED_9_Pos                                                        12U
+#define PCC_REG_MODEMRFCPI_RESERVED_9_Msk                                                        (0x1UL << PCC_REG_MODEMRFCPI_RESERVED_9_Pos)
+
+#define PCC_REG_MODEMRFCPI_RSVD_2_Pos                                                            13U
+#define PCC_REG_MODEMRFCPI_RSVD_2_Msk                                                            (0x7UL << PCC_REG_MODEMRFCPI_RSVD_2_Pos)
+
+#define PCC_REG_MODEMRFCPI_RESERVED_8_Pos                                                        16U
+#define PCC_REG_MODEMRFCPI_RESERVED_8_Msk                                                        (0x1UL << PCC_REG_MODEMRFCPI_RESERVED_8_Pos)
+
+#define PCC_REG_MODEMRFCPI_RESERVED_7_Pos                                                        17U
+#define PCC_REG_MODEMRFCPI_RESERVED_7_Msk                                                        (0x1UL << PCC_REG_MODEMRFCPI_RESERVED_7_Pos)
+
+#define PCC_REG_MODEMRFCPI_MODEMRFCPI_CLK_FORCE_Pos                                              18U
+#define PCC_REG_MODEMRFCPI_MODEMRFCPI_CLK_FORCE_Msk                                              (0x1UL << PCC_REG_MODEMRFCPI_MODEMRFCPI_CLK_FORCE_Pos)
+
+#define PCC_REG_MODEMRFCPI_RSVD_1_Pos                                                            19U
+#define PCC_REG_MODEMRFCPI_RSVD_1_Msk                                                            (0x7UL << PCC_REG_MODEMRFCPI_RSVD_1_Pos)
+
+#define PCC_REG_MODEMRFCPI_RESERVED_6_Pos                                                        22U
+#define PCC_REG_MODEMRFCPI_RESERVED_6_Msk                                                        (0x1UL << PCC_REG_MODEMRFCPI_RESERVED_6_Pos)
+
+#define PCC_REG_MODEMRFCPI_RESERVED_5_Pos                                                        23U
+#define PCC_REG_MODEMRFCPI_RESERVED_5_Msk                                                        (0x1UL << PCC_REG_MODEMRFCPI_RESERVED_5_Pos)
+
+#define PCC_REG_MODEMRFCPI_RESERVED_4_Pos                                                        24U
+#define PCC_REG_MODEMRFCPI_RESERVED_4_Msk                                                        (0x1UL << PCC_REG_MODEMRFCPI_RESERVED_4_Pos)
+
+#define PCC_REG_MODEMRFCPI_RESERVED_3_Pos                                                        25U
+#define PCC_REG_MODEMRFCPI_RESERVED_3_Msk                                                        (0x1UL << PCC_REG_MODEMRFCPI_RESERVED_3_Pos)
+
+#define PCC_REG_MODEMRFCPI_RESERVED_2_Pos                                                        26U
+#define PCC_REG_MODEMRFCPI_RESERVED_2_Msk                                                        (0x1UL << PCC_REG_MODEMRFCPI_RESERVED_2_Pos)
+
+#define PCC_REG_MODEMRFCPI_RESERVED_1_Pos                                                        27U
+#define PCC_REG_MODEMRFCPI_RESERVED_1_Msk                                                        (0x1UL << PCC_REG_MODEMRFCPI_RESERVED_1_Pos)
+
+#define PCC_REG_MODEMRFCPI_RSVD_Pos                                                              28U
+#define PCC_REG_MODEMRFCPI_RSVD_Msk                                                              (0x7UL << PCC_REG_MODEMRFCPI_RSVD_Pos)
+
+#define PCC_REG_MODEMRFCPI_RESERVED_Pos                                                          31U
+#define PCC_REG_MODEMRFCPI_RESERVED_Msk                                                          (0x1UL << PCC_REG_MODEMRFCPI_RESERVED_Pos)
+
+/* 0x22C    0x4000_022c
+    7:0     R/W     ENTRY_DELAY_CORE1_DEV_DMA0                      8'b0
+    8       R/W     RESERVED_8                                      1'b0
+    9       R/W     RESERVED_7                                      1'b0
+    10      R/W     RESERVED_6                                      1'b0
+    11      R/W     RESERVED_5                                      1'b1
+    14:12   R/W     RSVD_2                                          3'h0
+    15      R/W     RESERVED_4                                      1'b0
+    16      R/W     RESERVED_3                                      1'b0
+    17      R/W     GDMA0_CLK_FORCE                                 1'b0
+    20:18   R/W     RSVD_1                                          3'b000
+    21      R/W     RESERVED_2                                      1'b0
+    22      R/W     RESERVED_1                                      1'b0
+    23      R/W     GDMA0_MANU_SEL                                  1'b0
+    24      R/W     GDMA0_MANU_DAT                                  1'b0
+    26:25   R/W     DMA_CG_CTRL                                     2'b10
+    27      R/W     BZDMA_AUTOSLOW_ECO_DISABLE                      1'b0
+    30:28   R/W     RSVD                                            3'b000
+    31      R/W     RESERVED                                        1'b0
+ */
+typedef union _PCC_REG_DMA_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t ENTRY_DELAY_CORE1_DEV_DMA0: 8;
+        uint32_t RESERVED_8: 1;
+        uint32_t RESERVED_7: 1;
+        uint32_t RESERVED_6: 1;
+        uint32_t RESERVED_5: 1;
+        uint32_t RSVD_2: 3;
+        uint32_t RESERVED_4: 1;
+        uint32_t RESERVED_3: 1;
+        uint32_t GDMA0_CLK_FORCE: 1;
+        uint32_t RSVD_1: 3;
+        uint32_t RESERVED_2: 1;
+        uint32_t RESERVED_1: 1;
+        uint32_t GDMA0_MANU_SEL: 1;
+        uint32_t GDMA0_MANU_DAT: 1;
+        uint32_t DMA_CG_CTRL: 2;
+        uint32_t BZDMA_AUTOSLOW_ECO_DISABLE: 1;
+        uint32_t RSVD: 3;
+        uint32_t RESERVED: 1;
+    };
+} PCC_REG_DMA_TYPE;
+
+/*0x4000_022c PCC_REG_DMA*/
+#define PCC_REG_DMA_ENTRY_DELAY_CORE1_DEV_DMA0_Pos                                               0U
+#define PCC_REG_DMA_ENTRY_DELAY_CORE1_DEV_DMA0_Msk                                               (0xFFUL << PCC_REG_DMA_ENTRY_DELAY_CORE1_DEV_DMA0_Pos)
+
+#define PCC_REG_DMA_RESERVED_8_Pos                                                               8U
+#define PCC_REG_DMA_RESERVED_8_Msk                                                               (0x1UL << PCC_REG_DMA_RESERVED_8_Pos)
+
+#define PCC_REG_DMA_RESERVED_7_Pos                                                               9U
+#define PCC_REG_DMA_RESERVED_7_Msk                                                               (0x1UL << PCC_REG_DMA_RESERVED_7_Pos)
+
+#define PCC_REG_DMA_RESERVED_6_Pos                                                               10U
+#define PCC_REG_DMA_RESERVED_6_Msk                                                               (0x1UL << PCC_REG_DMA_RESERVED_6_Pos)
+
+#define PCC_REG_DMA_RESERVED_5_Pos                                                               11U
+#define PCC_REG_DMA_RESERVED_5_Msk                                                               (0x1UL << PCC_REG_DMA_RESERVED_5_Pos)
+
+#define PCC_REG_DMA_RSVD_2_Pos                                                                   12U
+#define PCC_REG_DMA_RSVD_2_Msk                                                                   (0x7UL << PCC_REG_DMA_RSVD_2_Pos)
+
+#define PCC_REG_DMA_RESERVED_4_Pos                                                               15U
+#define PCC_REG_DMA_RESERVED_4_Msk                                                               (0x1UL << PCC_REG_DMA_RESERVED_4_Pos)
+
+#define PCC_REG_DMA_RESERVED_3_Pos                                                               16U
+#define PCC_REG_DMA_RESERVED_3_Msk                                                               (0x1UL << PCC_REG_DMA_RESERVED_3_Pos)
+
+#define PCC_REG_DMA_GDMA0_CLK_FORCE_Pos                                                          17U
+#define PCC_REG_DMA_GDMA0_CLK_FORCE_Msk                                                          (0x1UL << PCC_REG_DMA_GDMA0_CLK_FORCE_Pos)
+
+#define PCC_REG_DMA_RSVD_1_Pos                                                                   18U
+#define PCC_REG_DMA_RSVD_1_Msk                                                                   (0x7UL << PCC_REG_DMA_RSVD_1_Pos)
+
+#define PCC_REG_DMA_RESERVED_2_Pos                                                               21U
+#define PCC_REG_DMA_RESERVED_2_Msk                                                               (0x1UL << PCC_REG_DMA_RESERVED_2_Pos)
+
+#define PCC_REG_DMA_RESERVED_1_Pos                                                               22U
+#define PCC_REG_DMA_RESERVED_1_Msk                                                               (0x1UL << PCC_REG_DMA_RESERVED_1_Pos)
+
+#define PCC_REG_DMA_GDMA0_MANU_SEL_Pos                                                           23U
+#define PCC_REG_DMA_GDMA0_MANU_SEL_Msk                                                           (0x1UL << PCC_REG_DMA_GDMA0_MANU_SEL_Pos)
+
+#define PCC_REG_DMA_GDMA0_MANU_DAT_Pos                                                           24U
+#define PCC_REG_DMA_GDMA0_MANU_DAT_Msk                                                           (0x1UL << PCC_REG_DMA_GDMA0_MANU_DAT_Pos)
+
+#define PCC_REG_DMA_DMA_CG_CTRL_Pos                                                              25U
+#define PCC_REG_DMA_DMA_CG_CTRL_Msk                                                              (0x3UL << PCC_REG_DMA_DMA_CG_CTRL_Pos)
+
+#define PCC_REG_DMA_BZDMA_AUTOSLOW_ECO_DISABLE_Pos                                               27U
+#define PCC_REG_DMA_BZDMA_AUTOSLOW_ECO_DISABLE_Msk                                               (0x1UL << PCC_REG_DMA_BZDMA_AUTOSLOW_ECO_DISABLE_Pos)
+
+#define PCC_REG_DMA_RSVD_Pos                                                                     28U
+#define PCC_REG_DMA_RSVD_Msk                                                                     (0x7UL << PCC_REG_DMA_RSVD_Pos)
+
+#define PCC_REG_DMA_RESERVED_Pos                                                                 31U
+#define PCC_REG_DMA_RESERVED_Msk                                                                 (0x1UL << PCC_REG_DMA_RESERVED_Pos)
+
+/* 0x230    0x4000_0230
+    7:0     R/W     ENTRY_DELAY_CORE1_DEV_SPIC0                     8'b0
+    8       R/W     RESERVED_9                                      1'b1
+    9       R/W     RESERVED_8                                      1'b1
+    10      R/W     RESERVED_7                                      1'b1
+    11      R/W     RESERVED_6                                      1'b1
+    12      R/W     RESERVED_5                                      1'b1
+    13      R/W     RESERVED_4                                      1'b1
+    15:14   R/W     RESERVED_3                                      2'b0
+    18:16   R/W     SPIC0_DIV_SEL                                   3'h0
+    19      R/W     SPIC0_CLK_SRC_SEL                               1'b0
+    20      R/W     FMC0_CLK_FORCE                                  1'b0
+    21      R/W     RESERVED_2                                      1'b0
+    22      R/W     RESERVED_1                                      1'b0
+    28:23   R/W     R_PON_DLYSEL_FMC0                               6'h0
+    29      R/W     SPIC0_MANU_SEL                                  1'b0
+    30      R/W     SPIC0_MANU_DAT                                  1'b0
+    31      R/W     RESERVED                                        1'b0
+ */
+typedef union _PCC_REG_SPIC_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t ENTRY_DELAY_CORE1_DEV_SPIC0: 8;
+        uint32_t RESERVED_9: 1;
+        uint32_t RESERVED_8: 1;
+        uint32_t RESERVED_7: 1;
+        uint32_t RESERVED_6: 1;
+        uint32_t RESERVED_5: 1;
+        uint32_t RESERVED_4: 1;
+        uint32_t RESERVED_3: 2;
+        uint32_t SPIC0_DIV_SEL: 3;
+        uint32_t SPIC0_CLK_SRC_SEL: 1;
+        uint32_t FMC0_CLK_FORCE: 1;
+        uint32_t RESERVED_2: 1;
+        uint32_t RESERVED_1: 1;
+        uint32_t R_PON_DLYSEL_FMC0: 6;
+        uint32_t SPIC0_MANU_SEL: 1;
+        uint32_t SPIC0_MANU_DAT: 1;
+        uint32_t RESERVED: 1;
+    };
+} PCC_REG_SPIC_TYPE;
+
+/*0x4000_0230 PCC_REG_SPIC*/
+#define PCC_REG_SPIC_ENTRY_DELAY_CORE1_DEV_SPIC0_Pos                                             0U
+#define PCC_REG_SPIC_ENTRY_DELAY_CORE1_DEV_SPIC0_Msk                                             (0xFFUL << PCC_REG_SPIC_ENTRY_DELAY_CORE1_DEV_SPIC0_Pos)
+
+#define PCC_REG_SPIC_RESERVED_9_Pos                                                              8U
+#define PCC_REG_SPIC_RESERVED_9_Msk                                                              (0x1UL << PCC_REG_SPIC_RESERVED_9_Pos)
+
+#define PCC_REG_SPIC_RESERVED_8_Pos                                                              9U
+#define PCC_REG_SPIC_RESERVED_8_Msk                                                              (0x1UL << PCC_REG_SPIC_RESERVED_8_Pos)
+
+#define PCC_REG_SPIC_RESERVED_7_Pos                                                              10U
+#define PCC_REG_SPIC_RESERVED_7_Msk                                                              (0x1UL << PCC_REG_SPIC_RESERVED_7_Pos)
+
+#define PCC_REG_SPIC_RESERVED_6_Pos                                                              11U
+#define PCC_REG_SPIC_RESERVED_6_Msk                                                              (0x1UL << PCC_REG_SPIC_RESERVED_6_Pos)
+
+#define PCC_REG_SPIC_RESERVED_5_Pos                                                              12U
+#define PCC_REG_SPIC_RESERVED_5_Msk                                                              (0x1UL << PCC_REG_SPIC_RESERVED_5_Pos)
+
+#define PCC_REG_SPIC_RESERVED_4_Pos                                                              13U
+#define PCC_REG_SPIC_RESERVED_4_Msk                                                              (0x1UL << PCC_REG_SPIC_RESERVED_4_Pos)
+
+#define PCC_REG_SPIC_RESERVED_3_Pos                                                              14U
+#define PCC_REG_SPIC_RESERVED_3_Msk                                                              (0x3UL << PCC_REG_SPIC_RESERVED_3_Pos)
+
+#define PCC_REG_SPIC_SPIC0_DIV_SEL_Pos                                                           16U
+#define PCC_REG_SPIC_SPIC0_DIV_SEL_Msk                                                           (0x7UL << PCC_REG_SPIC_SPIC0_DIV_SEL_Pos)
+
+#define PCC_REG_SPIC_SPIC0_CLK_SRC_SEL_Pos                                                       19U
+#define PCC_REG_SPIC_SPIC0_CLK_SRC_SEL_Msk                                                       (0x1UL << PCC_REG_SPIC_SPIC0_CLK_SRC_SEL_Pos)
+
+#define PCC_REG_SPIC_FMC0_CLK_FORCE_Pos                                                          20U
+#define PCC_REG_SPIC_FMC0_CLK_FORCE_Msk                                                          (0x1UL << PCC_REG_SPIC_FMC0_CLK_FORCE_Pos)
+
+#define PCC_REG_SPIC_RESERVED_2_Pos                                                              21U
+#define PCC_REG_SPIC_RESERVED_2_Msk                                                              (0x1UL << PCC_REG_SPIC_RESERVED_2_Pos)
+
+#define PCC_REG_SPIC_RESERVED_1_Pos                                                              22U
+#define PCC_REG_SPIC_RESERVED_1_Msk                                                              (0x1UL << PCC_REG_SPIC_RESERVED_1_Pos)
+
+#define PCC_REG_SPIC_R_PON_DLYSEL_FMC0_Pos                                                       23U
+#define PCC_REG_SPIC_R_PON_DLYSEL_FMC0_Msk                                                       (0x3FUL << PCC_REG_SPIC_R_PON_DLYSEL_FMC0_Pos)
+
+#define PCC_REG_SPIC_SPIC0_MANU_SEL_Pos                                                          29U
+#define PCC_REG_SPIC_SPIC0_MANU_SEL_Msk                                                          (0x1UL << PCC_REG_SPIC_SPIC0_MANU_SEL_Pos)
+
+#define PCC_REG_SPIC_SPIC0_MANU_DAT_Pos                                                          30U
+#define PCC_REG_SPIC_SPIC0_MANU_DAT_Msk                                                          (0x1UL << PCC_REG_SPIC_SPIC0_MANU_DAT_Pos)
+
+#define PCC_REG_SPIC_RESERVED_Pos                                                                31U
+#define PCC_REG_SPIC_RESERVED_Msk                                                                (0x1UL << PCC_REG_SPIC_RESERVED_Pos)
+
+/* 0x234    0x4000_0234
+    7:0     R/W     ENTRY_DELAY_CORE1_DEV_SPI0                      8'b0
+    8       R/W     RESERVED_9                                      1'b1
+    9       R/W     RESERVED_8                                      1'b1
+    10      R/W     RESERVED_7                                      1'b1
+    11      R/W     RESERVED_6                                      1'b1
+    12      R/W     RESERVED_5                                      1'b1
+    13      R/W     RESERVED_4                                      1'b1
+    14      R/W     RESERVED_3                                      1'b1
+    15      R/W     RESERVED_2                                      1'b0
+    18:16   R/W     R_SPI0_CLK_DIV_SEL                              3'h0
+    19      R/W     R_SPI0_CLK_SRC_SEL                              1'b0
+    20      R/W     RESERVED_1                                      1'b0
+    21      R/W     SPI0_CLK_FORCE                                  1'b0
+    22      R/W     PON_SPI0_MST                                    1'b0
+    23      R/W     PON_SPI0_H2S_BRG_EN                             1'b0
+    24      R/W     PON_SPI0_BRG_EN                                 1'b0
+    25      R/W     R_CPU_SLOW_OPT_SPI0                             1'b0
+    26      W1O     R_SPI0_DIV_SEL_OPT                              1'b0
+    27      W1O     R_SPI0_DIV_SEL_OPT1                             1'b0
+    30:28   R/W     RSVD                                            3'b00
+    31      R/W     RESERVED                                        1'b0
+ */
+typedef union _PCC_REG_SPI0_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t ENTRY_DELAY_CORE1_DEV_SPI0: 8;
+        uint32_t RESERVED_9: 1;
+        uint32_t RESERVED_8: 1;
+        uint32_t RESERVED_7: 1;
+        uint32_t RESERVED_6: 1;
+        uint32_t RESERVED_5: 1;
+        uint32_t RESERVED_4: 1;
+        uint32_t RESERVED_3: 1;
+        uint32_t RESERVED_2: 1;
+        uint32_t R_SPI0_CLK_DIV_SEL: 3;
+        uint32_t R_SPI0_CLK_SRC_SEL: 1;
+        uint32_t RESERVED_1: 1;
+        uint32_t SPI0_CLK_FORCE: 1;
+        uint32_t PON_SPI0_MST: 1;
+        uint32_t PON_SPI0_H2S_BRG_EN: 1;
+        uint32_t PON_SPI0_BRG_EN: 1;
+        uint32_t R_CPU_SLOW_OPT_SPI0: 1;
+        uint32_t R_SPI0_DIV_SEL_OPT: 1;
+        uint32_t R_SPI0_DIV_SEL_OPT1: 1;
+        uint32_t RSVD: 3;
+        uint32_t RESERVED: 1;
+    };
+} PCC_REG_SPI0_TYPE;
+
+/*0x4000_0234 PCC_REG_SPI0*/
+#define PCC_REG_SPI0_ENTRY_DELAY_CORE1_DEV_SPI0_Pos                                              0U
+#define PCC_REG_SPI0_ENTRY_DELAY_CORE1_DEV_SPI0_Msk                                              (0xFFUL << PCC_REG_SPI0_ENTRY_DELAY_CORE1_DEV_SPI0_Pos)
+
+#define PCC_REG_SPI0_RESERVED_9_Pos                                                              8U
+#define PCC_REG_SPI0_RESERVED_9_Msk                                                              (0x1UL << PCC_REG_SPI0_RESERVED_9_Pos)
+
+#define PCC_REG_SPI0_RESERVED_8_Pos                                                              9U
+#define PCC_REG_SPI0_RESERVED_8_Msk                                                              (0x1UL << PCC_REG_SPI0_RESERVED_8_Pos)
+
+#define PCC_REG_SPI0_RESERVED_7_Pos                                                              10U
+#define PCC_REG_SPI0_RESERVED_7_Msk                                                              (0x1UL << PCC_REG_SPI0_RESERVED_7_Pos)
+
+#define PCC_REG_SPI0_RESERVED_6_Pos                                                              11U
+#define PCC_REG_SPI0_RESERVED_6_Msk                                                              (0x1UL << PCC_REG_SPI0_RESERVED_6_Pos)
+
+#define PCC_REG_SPI0_RESERVED_5_Pos                                                              12U
+#define PCC_REG_SPI0_RESERVED_5_Msk                                                              (0x1UL << PCC_REG_SPI0_RESERVED_5_Pos)
+
+#define PCC_REG_SPI0_RESERVED_4_Pos                                                              13U
+#define PCC_REG_SPI0_RESERVED_4_Msk                                                              (0x1UL << PCC_REG_SPI0_RESERVED_4_Pos)
+
+#define PCC_REG_SPI0_RESERVED_3_Pos                                                              14U
+#define PCC_REG_SPI0_RESERVED_3_Msk                                                              (0x1UL << PCC_REG_SPI0_RESERVED_3_Pos)
+
+#define PCC_REG_SPI0_RESERVED_2_Pos                                                              15U
+#define PCC_REG_SPI0_RESERVED_2_Msk                                                              (0x1UL << PCC_REG_SPI0_RESERVED_2_Pos)
+
+#define PCC_REG_SPI0_R_SPI0_CLK_DIV_SEL_Pos                                                      16U
+#define PCC_REG_SPI0_R_SPI0_CLK_DIV_SEL_Msk                                                      (0x7UL << PCC_REG_SPI0_R_SPI0_CLK_DIV_SEL_Pos)
+
+#define PCC_REG_SPI0_R_SPI0_CLK_SRC_SEL_Pos                                                      19U
+#define PCC_REG_SPI0_R_SPI0_CLK_SRC_SEL_Msk                                                      (0x1UL << PCC_REG_SPI0_R_SPI0_CLK_SRC_SEL_Pos)
+
+#define PCC_REG_SPI0_RESERVED_1_Pos                                                              20U
+#define PCC_REG_SPI0_RESERVED_1_Msk                                                              (0x1UL << PCC_REG_SPI0_RESERVED_1_Pos)
+
+#define PCC_REG_SPI0_SPI0_CLK_FORCE_Pos                                                          21U
+#define PCC_REG_SPI0_SPI0_CLK_FORCE_Msk                                                          (0x1UL << PCC_REG_SPI0_SPI0_CLK_FORCE_Pos)
+
+#define PCC_REG_SPI0_PON_SPI0_MST_Pos                                                            22U
+#define PCC_REG_SPI0_PON_SPI0_MST_Msk                                                            (0x1UL << PCC_REG_SPI0_PON_SPI0_MST_Pos)
+
+#define PCC_REG_SPI0_PON_SPI0_H2S_BRG_EN_Pos                                                     23U
+#define PCC_REG_SPI0_PON_SPI0_H2S_BRG_EN_Msk                                                     (0x1UL << PCC_REG_SPI0_PON_SPI0_H2S_BRG_EN_Pos)
+
+#define PCC_REG_SPI0_PON_SPI0_BRG_EN_Pos                                                         24U
+#define PCC_REG_SPI0_PON_SPI0_BRG_EN_Msk                                                         (0x1UL << PCC_REG_SPI0_PON_SPI0_BRG_EN_Pos)
+
+#define PCC_REG_SPI0_R_CPU_SLOW_OPT_SPI0_Pos                                                     25U
+#define PCC_REG_SPI0_R_CPU_SLOW_OPT_SPI0_Msk                                                     (0x1UL << PCC_REG_SPI0_R_CPU_SLOW_OPT_SPI0_Pos)
+
+#define PCC_REG_SPI0_R_SPI0_DIV_SEL_OPT_Pos                                                      26U
+#define PCC_REG_SPI0_R_SPI0_DIV_SEL_OPT_Msk                                                      (0x1UL << PCC_REG_SPI0_R_SPI0_DIV_SEL_OPT_Pos)
+
+#define PCC_REG_SPI0_R_SPI0_DIV_SEL_OPT1_Pos                                                     27U
+#define PCC_REG_SPI0_R_SPI0_DIV_SEL_OPT1_Msk                                                     (0x1UL << PCC_REG_SPI0_R_SPI0_DIV_SEL_OPT1_Pos)
+
+#define PCC_REG_SPI0_RSVD_Pos                                                                    28U
+#define PCC_REG_SPI0_RSVD_Msk                                                                    (0x7UL << PCC_REG_SPI0_RSVD_Pos)
+
+#define PCC_REG_SPI0_RESERVED_Pos                                                                31U
+#define PCC_REG_SPI0_RESERVED_Msk                                                                (0x1UL << PCC_REG_SPI0_RESERVED_Pos)
+
+/* 0x238    0x4000_0238
+    7:0     R/W     ENTRY_DELAY_CORE1_DEV_SPI1                      8'b0
+    8       R/W     RESERVED_8                                      1'b1
+    9       R/W     RESERVED_7                                      1'b1
+    10      R/W     RESERVED_6                                      1'b1
+    11      R/W     RESERVED_5                                      1'b1
+    12      R/W     RESERVED_4                                      1'b1
+    13      R/W     RESERVED_3                                      1'b1
+    14      R/W     RESERVED_2                                      1'b1
+    17:15   R/W     R_SPI1_CLK_DIV_SEL                              3'h0
+    18      R/W     R_SPI1_CLK_SRC_SEL                              1'b0
+    19      R/W     SPI1_CLK_FORCE                                  1'b0
+    23:20   R/W     RESERVED_1                                      4'b0
+    24      R/W     PON_SPI1_H2S_BRG_EN                             1'b0
+    25      R/W     PON_SPI1_BRG_EN                                 1'b0
+    26      W1O     R_SPI1_DIV_SEL_OPT                              1'b0
+    27      W1O     R_SPI1_DIV_SEL_OPT1                             1'b0
+    30:28   R/W     RSVD                                            3'b0
+    31      R/W     RESERVED                                        1'b0
+ */
+typedef union _PCC_REG_SPI1_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t ENTRY_DELAY_CORE1_DEV_SPI1: 8;
+        uint32_t RESERVED_8: 1;
+        uint32_t RESERVED_7: 1;
+        uint32_t RESERVED_6: 1;
+        uint32_t RESERVED_5: 1;
+        uint32_t RESERVED_4: 1;
+        uint32_t RESERVED_3: 1;
+        uint32_t RESERVED_2: 1;
+        uint32_t R_SPI1_CLK_DIV_SEL: 3;
+        uint32_t R_SPI1_CLK_SRC_SEL: 1;
+        uint32_t SPI1_CLK_FORCE: 1;
+        uint32_t RESERVED_1: 4;
+        uint32_t PON_SPI1_H2S_BRG_EN: 1;
+        uint32_t PON_SPI1_BRG_EN: 1;
+        uint32_t R_SPI1_DIV_SEL_OPT: 1;
+        uint32_t R_SPI1_DIV_SEL_OPT1: 1;
+        uint32_t RSVD: 3;
+        uint32_t RESERVED: 1;
+    };
+} PCC_REG_SPI1_TYPE;
+
+/*0x4000_0238 PCC_REG_SPI1*/
+#define PCC_REG_SPI1_ENTRY_DELAY_CORE1_DEV_SPI1_Pos                                              0U
+#define PCC_REG_SPI1_ENTRY_DELAY_CORE1_DEV_SPI1_Msk                                              (0xFFUL << PCC_REG_SPI1_ENTRY_DELAY_CORE1_DEV_SPI1_Pos)
+
+#define PCC_REG_SPI1_RESERVED_8_Pos                                                              8U
+#define PCC_REG_SPI1_RESERVED_8_Msk                                                              (0x1UL << PCC_REG_SPI1_RESERVED_8_Pos)
+
+#define PCC_REG_SPI1_RESERVED_7_Pos                                                              9U
+#define PCC_REG_SPI1_RESERVED_7_Msk                                                              (0x1UL << PCC_REG_SPI1_RESERVED_7_Pos)
+
+#define PCC_REG_SPI1_RESERVED_6_Pos                                                              10U
+#define PCC_REG_SPI1_RESERVED_6_Msk                                                              (0x1UL << PCC_REG_SPI1_RESERVED_6_Pos)
+
+#define PCC_REG_SPI1_RESERVED_5_Pos                                                              11U
+#define PCC_REG_SPI1_RESERVED_5_Msk                                                              (0x1UL << PCC_REG_SPI1_RESERVED_5_Pos)
+
+#define PCC_REG_SPI1_RESERVED_4_Pos                                                              12U
+#define PCC_REG_SPI1_RESERVED_4_Msk                                                              (0x1UL << PCC_REG_SPI1_RESERVED_4_Pos)
+
+#define PCC_REG_SPI1_RESERVED_3_Pos                                                              13U
+#define PCC_REG_SPI1_RESERVED_3_Msk                                                              (0x1UL << PCC_REG_SPI1_RESERVED_3_Pos)
+
+#define PCC_REG_SPI1_RESERVED_2_Pos                                                              14U
+#define PCC_REG_SPI1_RESERVED_2_Msk                                                              (0x1UL << PCC_REG_SPI1_RESERVED_2_Pos)
+
+#define PCC_REG_SPI1_R_SPI1_CLK_DIV_SEL_Pos                                                      15U
+#define PCC_REG_SPI1_R_SPI1_CLK_DIV_SEL_Msk                                                      (0x7UL << PCC_REG_SPI1_R_SPI1_CLK_DIV_SEL_Pos)
+
+#define PCC_REG_SPI1_R_SPI1_CLK_SRC_SEL_Pos                                                      18U
+#define PCC_REG_SPI1_R_SPI1_CLK_SRC_SEL_Msk                                                      (0x1UL << PCC_REG_SPI1_R_SPI1_CLK_SRC_SEL_Pos)
+
+#define PCC_REG_SPI1_SPI1_CLK_FORCE_Pos                                                          19U
+#define PCC_REG_SPI1_SPI1_CLK_FORCE_Msk                                                          (0x1UL << PCC_REG_SPI1_SPI1_CLK_FORCE_Pos)
+
+#define PCC_REG_SPI1_RESERVED_1_Pos                                                              20U
+#define PCC_REG_SPI1_RESERVED_1_Msk                                                              (0xFUL << PCC_REG_SPI1_RESERVED_1_Pos)
+
+#define PCC_REG_SPI1_PON_SPI1_H2S_BRG_EN_Pos                                                     24U
+#define PCC_REG_SPI1_PON_SPI1_H2S_BRG_EN_Msk                                                     (0x1UL << PCC_REG_SPI1_PON_SPI1_H2S_BRG_EN_Pos)
+
+#define PCC_REG_SPI1_PON_SPI1_BRG_EN_Pos                                                         25U
+#define PCC_REG_SPI1_PON_SPI1_BRG_EN_Msk                                                         (0x1UL << PCC_REG_SPI1_PON_SPI1_BRG_EN_Pos)
+
+#define PCC_REG_SPI1_R_SPI1_DIV_SEL_OPT_Pos                                                      26U
+#define PCC_REG_SPI1_R_SPI1_DIV_SEL_OPT_Msk                                                      (0x1UL << PCC_REG_SPI1_R_SPI1_DIV_SEL_OPT_Pos)
+
+#define PCC_REG_SPI1_R_SPI1_DIV_SEL_OPT1_Pos                                                     27U
+#define PCC_REG_SPI1_R_SPI1_DIV_SEL_OPT1_Msk                                                     (0x1UL << PCC_REG_SPI1_R_SPI1_DIV_SEL_OPT1_Pos)
+
+#define PCC_REG_SPI1_RSVD_Pos                                                                    28U
+#define PCC_REG_SPI1_RSVD_Msk                                                                    (0x7UL << PCC_REG_SPI1_RSVD_Pos)
+
+#define PCC_REG_SPI1_RESERVED_Pos                                                                31U
+#define PCC_REG_SPI1_RESERVED_Msk                                                                (0x1UL << PCC_REG_SPI1_RESERVED_Pos)
+
+/* 0x23C    0x4000_023c
+    7:0     R/W     ENTRY_DELAY_CORE1_DEV_SPI2                      8'b0
+    8       R/W     RESERVED_8                                      1'b0
+    9       R/W     RESERVED_7                                      1'b1
+    10      R/W     RESERVED_6                                      1'b1
+    11      R/W     RESERVED_5                                      1'b1
+    12      R/W     RESERVED_4                                      1'b1
+    13      R/W     RESERVED_3                                      1'b1
+    15:14   R/W     RESERVED_2                                      2'b0
+    18:16   R/W     R_SPI2_CLK_DIV_SEL                              3'h0
+    19      R/W     R_SPI2_CLK_SRC_SEL                              1'b0
+    20      R/W     SPI2_CLK_FORCE                                  1'b0
+    23:21   R/W     RESERVED_1                                      3'b0
+    24      R/W     PON_SPI2_H2S_BRG_EN                             1'b0
+    25      R/W     PON_SPI2_BRG_EN                                 1'b0
+    26      W1O     R_SPI2_DIV_SEL_OPT                              1'b0
+    27      W1O     R_SPI2_DIV_SEL_OPT1                             1'b0
+    30:28   R/W     RSVD                                            3'b0
+    31      R/W     RESERVED                                        1'b0
+ */
+typedef union _PCC_REG_SPI2_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t ENTRY_DELAY_CORE1_DEV_SPI2: 8;
+        uint32_t RESERVED_8: 1;
+        uint32_t RESERVED_7: 1;
+        uint32_t RESERVED_6: 1;
+        uint32_t RESERVED_5: 1;
+        uint32_t RESERVED_4: 1;
+        uint32_t RESERVED_3: 1;
+        uint32_t RESERVED_2: 2;
+        uint32_t R_SPI2_CLK_DIV_SEL: 3;
+        uint32_t R_SPI2_CLK_SRC_SEL: 1;
+        uint32_t SPI2_CLK_FORCE: 1;
+        uint32_t RESERVED_1: 3;
+        uint32_t PON_SPI2_H2S_BRG_EN: 1;
+        uint32_t PON_SPI2_BRG_EN: 1;
+        uint32_t R_SPI2_DIV_SEL_OPT: 1;
+        uint32_t R_SPI2_DIV_SEL_OPT1: 1;
+        uint32_t RSVD: 3;
+        uint32_t RESERVED: 1;
+    };
+} PCC_REG_SPI2_TYPE;
+
+/*0x4000_023c PCC_REG_SPI2*/
+#define PCC_REG_SPI2_ENTRY_DELAY_CORE1_DEV_SPI2_Pos                                              0U
+#define PCC_REG_SPI2_ENTRY_DELAY_CORE1_DEV_SPI2_Msk                                              (0xFFUL << PCC_REG_SPI2_ENTRY_DELAY_CORE1_DEV_SPI2_Pos)
+
+#define PCC_REG_SPI2_RESERVED_8_Pos                                                              8U
+#define PCC_REG_SPI2_RESERVED_8_Msk                                                              (0x1UL << PCC_REG_SPI2_RESERVED_8_Pos)
+
+#define PCC_REG_SPI2_RESERVED_7_Pos                                                              9U
+#define PCC_REG_SPI2_RESERVED_7_Msk                                                              (0x1UL << PCC_REG_SPI2_RESERVED_7_Pos)
+
+#define PCC_REG_SPI2_RESERVED_6_Pos                                                              10U
+#define PCC_REG_SPI2_RESERVED_6_Msk                                                              (0x1UL << PCC_REG_SPI2_RESERVED_6_Pos)
+
+#define PCC_REG_SPI2_RESERVED_5_Pos                                                              11U
+#define PCC_REG_SPI2_RESERVED_5_Msk                                                              (0x1UL << PCC_REG_SPI2_RESERVED_5_Pos)
+
+#define PCC_REG_SPI2_RESERVED_4_Pos                                                              12U
+#define PCC_REG_SPI2_RESERVED_4_Msk                                                              (0x1UL << PCC_REG_SPI2_RESERVED_4_Pos)
+
+#define PCC_REG_SPI2_RESERVED_3_Pos                                                              13U
+#define PCC_REG_SPI2_RESERVED_3_Msk                                                              (0x1UL << PCC_REG_SPI2_RESERVED_3_Pos)
+
+#define PCC_REG_SPI2_RESERVED_2_Pos                                                              14U
+#define PCC_REG_SPI2_RESERVED_2_Msk                                                              (0x3UL << PCC_REG_SPI2_RESERVED_2_Pos)
+
+#define PCC_REG_SPI2_R_SPI2_CLK_DIV_SEL_Pos                                                      16U
+#define PCC_REG_SPI2_R_SPI2_CLK_DIV_SEL_Msk                                                      (0x7UL << PCC_REG_SPI2_R_SPI2_CLK_DIV_SEL_Pos)
+
+#define PCC_REG_SPI2_R_SPI2_CLK_SRC_SEL_Pos                                                      19U
+#define PCC_REG_SPI2_R_SPI2_CLK_SRC_SEL_Msk                                                      (0x1UL << PCC_REG_SPI2_R_SPI2_CLK_SRC_SEL_Pos)
+
+#define PCC_REG_SPI2_SPI2_CLK_FORCE_Pos                                                          20U
+#define PCC_REG_SPI2_SPI2_CLK_FORCE_Msk                                                          (0x1UL << PCC_REG_SPI2_SPI2_CLK_FORCE_Pos)
+
+#define PCC_REG_SPI2_RESERVED_1_Pos                                                              21U
+#define PCC_REG_SPI2_RESERVED_1_Msk                                                              (0x7UL << PCC_REG_SPI2_RESERVED_1_Pos)
+
+#define PCC_REG_SPI2_PON_SPI2_H2S_BRG_EN_Pos                                                     24U
+#define PCC_REG_SPI2_PON_SPI2_H2S_BRG_EN_Msk                                                     (0x1UL << PCC_REG_SPI2_PON_SPI2_H2S_BRG_EN_Pos)
+
+#define PCC_REG_SPI2_PON_SPI2_BRG_EN_Pos                                                         25U
+#define PCC_REG_SPI2_PON_SPI2_BRG_EN_Msk                                                         (0x1UL << PCC_REG_SPI2_PON_SPI2_BRG_EN_Pos)
+
+#define PCC_REG_SPI2_R_SPI2_DIV_SEL_OPT_Pos                                                      26U
+#define PCC_REG_SPI2_R_SPI2_DIV_SEL_OPT_Msk                                                      (0x1UL << PCC_REG_SPI2_R_SPI2_DIV_SEL_OPT_Pos)
+
+#define PCC_REG_SPI2_R_SPI2_DIV_SEL_OPT1_Pos                                                     27U
+#define PCC_REG_SPI2_R_SPI2_DIV_SEL_OPT1_Msk                                                     (0x1UL << PCC_REG_SPI2_R_SPI2_DIV_SEL_OPT1_Pos)
+
+#define PCC_REG_SPI2_RSVD_Pos                                                                    28U
+#define PCC_REG_SPI2_RSVD_Msk                                                                    (0x7UL << PCC_REG_SPI2_RSVD_Pos)
+
+#define PCC_REG_SPI2_RESERVED_Pos                                                                31U
+#define PCC_REG_SPI2_RESERVED_Msk                                                                (0x1UL << PCC_REG_SPI2_RESERVED_Pos)
+
+/* 0x240    0x4000_0240
+    7:0     R/W     ENTRY_DELAY_CORE1_DEV_I2S0                      8'b0
+    8       R/W     RESERVED_7                                      1'b0
+    9       R/W     RESERVED_6                                      1'b1
+    10      R/W     RESERVED_5                                      1'b1
+    11      R/W     RESERVED_4                                      1'b1
+    12      R/W     RESERVED_3                                      1'b1
+    15:13   R/W     RESERVED_2                                      3'b0
+    17:16   R/W     MCLK_SEL                                        2'b00
+    20:18   R/W     R_I2S_PLL_CLK_SEL                               3'h4
+    21      R/W     RESERVED_1                                      1'b0
+    22      R/W     I2S_CLK_FORCE                                   1'b0
+    26:23   R/W     RSVD                                            4'b00
+    27      R/W     R_SPORT0_EXT_CODEC                              1'b0
+    31:28   R/W     RESERVED                                        4'b0
+ */
+typedef union _PCC_REG_I2S0_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t ENTRY_DELAY_CORE1_DEV_I2S0: 8;
+        uint32_t RESERVED_7: 1;
+        uint32_t RESERVED_6: 1;
+        uint32_t RESERVED_5: 1;
+        uint32_t RESERVED_4: 1;
+        uint32_t RESERVED_3: 1;
+        uint32_t RESERVED_2: 3;
+        uint32_t MCLK_SEL: 2;
+        uint32_t R_I2S_PLL_CLK_SEL: 3;
+        uint32_t RESERVED_1: 1;
+        uint32_t I2S_CLK_FORCE: 1;
+        uint32_t RSVD: 4;
+        uint32_t R_SPORT0_EXT_CODEC: 1;
+        uint32_t RESERVED: 4;
+    };
+} PCC_REG_I2S0_TYPE;
+
+/*0x4000_0240 PCC_REG_I2S0*/
+#define PCC_REG_I2S0_ENTRY_DELAY_CORE1_DEV_I2S0_Pos                                              0U
+#define PCC_REG_I2S0_ENTRY_DELAY_CORE1_DEV_I2S0_Msk                                              (0xFFUL << PCC_REG_I2S0_ENTRY_DELAY_CORE1_DEV_I2S0_Pos)
+
+#define PCC_REG_I2S0_RESERVED_7_Pos                                                              8U
+#define PCC_REG_I2S0_RESERVED_7_Msk                                                              (0x1UL << PCC_REG_I2S0_RESERVED_7_Pos)
+
+#define PCC_REG_I2S0_RESERVED_6_Pos                                                              9U
+#define PCC_REG_I2S0_RESERVED_6_Msk                                                              (0x1UL << PCC_REG_I2S0_RESERVED_6_Pos)
+
+#define PCC_REG_I2S0_RESERVED_5_Pos                                                              10U
+#define PCC_REG_I2S0_RESERVED_5_Msk                                                              (0x1UL << PCC_REG_I2S0_RESERVED_5_Pos)
+
+#define PCC_REG_I2S0_RESERVED_4_Pos                                                              11U
+#define PCC_REG_I2S0_RESERVED_4_Msk                                                              (0x1UL << PCC_REG_I2S0_RESERVED_4_Pos)
+
+#define PCC_REG_I2S0_RESERVED_3_Pos                                                              12U
+#define PCC_REG_I2S0_RESERVED_3_Msk                                                              (0x1UL << PCC_REG_I2S0_RESERVED_3_Pos)
+
+#define PCC_REG_I2S0_RESERVED_2_Pos                                                              13U
+#define PCC_REG_I2S0_RESERVED_2_Msk                                                              (0x7UL << PCC_REG_I2S0_RESERVED_2_Pos)
+
+#define PCC_REG_I2S0_MCLK_SEL_Pos                                                                16U
+#define PCC_REG_I2S0_MCLK_SEL_Msk                                                                (0x3UL << PCC_REG_I2S0_MCLK_SEL_Pos)
+
+#define PCC_REG_I2S0_R_I2S_PLL_CLK_SEL_Pos                                                       18U
+#define PCC_REG_I2S0_R_I2S_PLL_CLK_SEL_Msk                                                       (0x7UL << PCC_REG_I2S0_R_I2S_PLL_CLK_SEL_Pos)
+
+#define PCC_REG_I2S0_RESERVED_1_Pos                                                              21U
+#define PCC_REG_I2S0_RESERVED_1_Msk                                                              (0x1UL << PCC_REG_I2S0_RESERVED_1_Pos)
+
+#define PCC_REG_I2S0_I2S_CLK_FORCE_Pos                                                           22U
+#define PCC_REG_I2S0_I2S_CLK_FORCE_Msk                                                           (0x1UL << PCC_REG_I2S0_I2S_CLK_FORCE_Pos)
+
+#define PCC_REG_I2S0_RSVD_Pos                                                                    23U
+#define PCC_REG_I2S0_RSVD_Msk                                                                    (0xFUL << PCC_REG_I2S0_RSVD_Pos)
+
+#define PCC_REG_I2S0_R_SPORT0_EXT_CODEC_Pos                                                      27U
+#define PCC_REG_I2S0_R_SPORT0_EXT_CODEC_Msk                                                      (0x1UL << PCC_REG_I2S0_R_SPORT0_EXT_CODEC_Pos)
+
+#define PCC_REG_I2S0_RESERVED_Pos                                                                28U
+#define PCC_REG_I2S0_RESERVED_Msk                                                                (0xFUL << PCC_REG_I2S0_RESERVED_Pos)
+
+/* 0x244    0x4000_0244
+    7:0     R/W     ENTRY_DELAY_CORE1_DEV_TIMER0                    8'b0
+    8       R/W     RESERVED_8                                      1'b1
+    9       R/W     RESERVED_7                                      1'b1
+    10      R/W     RESERVED_6                                      1'b1
+    11      R/W     RESERVED_5                                      1'b1
+    12      R/W     RESERVED_4                                      1'b1
+    13      R/W     RESERVED_3                                      1'b1
+    14      R/W     RESERVED_2                                      1'b1
+    15      R/W     RESERVED_1                                      1'b1
+    21:16   R/W     RESERVED                                        6'b0
+    22      R/W     RSVD_1                                          1'b0
+    23      R/W     RSVD                                            1'b0
+    26:24   R/W     R_TIMER_1_CLK_DIV                               3'h0
+    29:27   R/W     R_TIMER_2_CLK_DIV                               3'h0
+    30      R/W     TIMER0_CH1_CLK_FORCE                            1'b0
+    31      R/W     TIMER0_CH2_CLK_FORCE                            1'b0
+ */
+typedef union _PCC_REG_TIMER0_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t ENTRY_DELAY_CORE1_DEV_TIMER0: 8;
+        uint32_t RESERVED_8: 1;
+        uint32_t RESERVED_7: 1;
+        uint32_t RESERVED_6: 1;
+        uint32_t RESERVED_5: 1;
+        uint32_t RESERVED_4: 1;
+        uint32_t RESERVED_3: 1;
+        uint32_t RESERVED_2: 1;
+        uint32_t RESERVED_1: 1;
+        uint32_t RESERVED: 6;
+        uint32_t RSVD_1: 1;
+        uint32_t RSVD: 1;
+        uint32_t R_TIMER_1_CLK_DIV: 3;
+        uint32_t R_TIMER_2_CLK_DIV: 3;
+        uint32_t TIMER0_CH1_CLK_FORCE: 1;
+        uint32_t TIMER0_CH2_CLK_FORCE: 1;
+    };
+} PCC_REG_TIMER0_TYPE;
+
+/*0x4000_0244 PCC_REG_TIMER0*/
+#define PCC_REG_TIMER0_ENTRY_DELAY_CORE1_DEV_TIMER0_Pos                                          0U
+#define PCC_REG_TIMER0_ENTRY_DELAY_CORE1_DEV_TIMER0_Msk                                          (0xFFUL << PCC_REG_TIMER0_ENTRY_DELAY_CORE1_DEV_TIMER0_Pos)
+
+#define PCC_REG_TIMER0_RESERVED_8_Pos                                                            8U
+#define PCC_REG_TIMER0_RESERVED_8_Msk                                                            (0x1UL << PCC_REG_TIMER0_RESERVED_8_Pos)
+
+#define PCC_REG_TIMER0_RESERVED_7_Pos                                                            9U
+#define PCC_REG_TIMER0_RESERVED_7_Msk                                                            (0x1UL << PCC_REG_TIMER0_RESERVED_7_Pos)
+
+#define PCC_REG_TIMER0_RESERVED_6_Pos                                                            10U
+#define PCC_REG_TIMER0_RESERVED_6_Msk                                                            (0x1UL << PCC_REG_TIMER0_RESERVED_6_Pos)
+
+#define PCC_REG_TIMER0_RESERVED_5_Pos                                                            11U
+#define PCC_REG_TIMER0_RESERVED_5_Msk                                                            (0x1UL << PCC_REG_TIMER0_RESERVED_5_Pos)
+
+#define PCC_REG_TIMER0_RESERVED_4_Pos                                                            12U
+#define PCC_REG_TIMER0_RESERVED_4_Msk                                                            (0x1UL << PCC_REG_TIMER0_RESERVED_4_Pos)
+
+#define PCC_REG_TIMER0_RESERVED_3_Pos                                                            13U
+#define PCC_REG_TIMER0_RESERVED_3_Msk                                                            (0x1UL << PCC_REG_TIMER0_RESERVED_3_Pos)
+
+#define PCC_REG_TIMER0_RESERVED_2_Pos                                                            14U
+#define PCC_REG_TIMER0_RESERVED_2_Msk                                                            (0x1UL << PCC_REG_TIMER0_RESERVED_2_Pos)
+
+#define PCC_REG_TIMER0_RESERVED_1_Pos                                                            15U
+#define PCC_REG_TIMER0_RESERVED_1_Msk                                                            (0x1UL << PCC_REG_TIMER0_RESERVED_1_Pos)
+
+#define PCC_REG_TIMER0_RESERVED_Pos                                                              16U
+#define PCC_REG_TIMER0_RESERVED_Msk                                                              (0x3FUL << PCC_REG_TIMER0_RESERVED_Pos)
+
+#define PCC_REG_TIMER0_RSVD_1_Pos                                                                22U
+#define PCC_REG_TIMER0_RSVD_1_Msk                                                                (0x1UL << PCC_REG_TIMER0_RSVD_1_Pos)
+
+#define PCC_REG_TIMER0_RSVD_Pos                                                                  23U
+#define PCC_REG_TIMER0_RSVD_Msk                                                                  (0x1UL << PCC_REG_TIMER0_RSVD_Pos)
+
+#define PCC_REG_TIMER0_R_TIMER_1_CLK_DIV_Pos                                                     24U
+#define PCC_REG_TIMER0_R_TIMER_1_CLK_DIV_Msk                                                     (0x7UL << PCC_REG_TIMER0_R_TIMER_1_CLK_DIV_Pos)
+
+#define PCC_REG_TIMER0_R_TIMER_2_CLK_DIV_Pos                                                     27U
+#define PCC_REG_TIMER0_R_TIMER_2_CLK_DIV_Msk                                                     (0x7UL << PCC_REG_TIMER0_R_TIMER_2_CLK_DIV_Pos)
+
+#define PCC_REG_TIMER0_TIMER0_CH1_CLK_FORCE_Pos                                                  30U
+#define PCC_REG_TIMER0_TIMER0_CH1_CLK_FORCE_Msk                                                  (0x1UL << PCC_REG_TIMER0_TIMER0_CH1_CLK_FORCE_Pos)
+
+#define PCC_REG_TIMER0_TIMER0_CH2_CLK_FORCE_Pos                                                  31U
+#define PCC_REG_TIMER0_TIMER0_CH2_CLK_FORCE_Msk                                                  (0x1UL << PCC_REG_TIMER0_TIMER0_CH2_CLK_FORCE_Pos)
+
+/* 0x248    0x4000_0248
+    7:0     R/W     ENTRY_DELAY_CORE1_DEV_TIMER1                    8'b0
+    8       R/W     RESERVED_9                                      1'b1
+    9       R/W     RESERVED_8                                      1'b1
+    10      R/W     RESERVED_7                                      1'b1
+    11      R/W     RESERVED_6                                      1'b1
+    12      R/W     RESERVED_5                                      1'b1
+    13      R/W     RESERVED_4                                      1'b1
+    14      R/W     RESERVED_3                                      1'b1
+    15      R/W     RESERVED_2                                      1'b1
+    16      R/W     RESERVED_1                                      1'b1
+    17      R/W     RESERVED                                        1'b1
+    19:18   R/W     RSVD                                            2'b0
+    22:20   R/W     R_TIMER_3_CLK_DIV                               3'h0
+    25:23   R/W     R_TIMER_4_CLK_DIV                               3'h0
+    28:26   R/W     R_TIMER_5_CLK_DIV                               3'h0
+    29      R/W     TIMER1_CH3_CLK_FORCE                            1'b0
+    30      R/W     TIMER1_CH4_CLK_FORCE                            1'b0
+    31      R/W     TIMER1_CH5_CLK_FORCE                            1'b0
+ */
+typedef union _PCC_REG_TIMER1_A_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t ENTRY_DELAY_CORE1_DEV_TIMER1: 8;
+        uint32_t RESERVED_9: 1;
+        uint32_t RESERVED_8: 1;
+        uint32_t RESERVED_7: 1;
+        uint32_t RESERVED_6: 1;
+        uint32_t RESERVED_5: 1;
+        uint32_t RESERVED_4: 1;
+        uint32_t RESERVED_3: 1;
+        uint32_t RESERVED_2: 1;
+        uint32_t RESERVED_1: 1;
+        uint32_t RESERVED: 1;
+        uint32_t RSVD: 2;
+        uint32_t R_TIMER_3_CLK_DIV: 3;
+        uint32_t R_TIMER_4_CLK_DIV: 3;
+        uint32_t R_TIMER_5_CLK_DIV: 3;
+        uint32_t TIMER1_CH3_CLK_FORCE: 1;
+        uint32_t TIMER1_CH4_CLK_FORCE: 1;
+        uint32_t TIMER1_CH5_CLK_FORCE: 1;
+    };
+} PCC_REG_TIMER1_A_TYPE;
+
+/*0x4000_0248 PCC_REG_TIMER1_A*/
+#define PCC_REG_TIMER1_A_ENTRY_DELAY_CORE1_DEV_TIMER1_Pos                                        0U
+#define PCC_REG_TIMER1_A_ENTRY_DELAY_CORE1_DEV_TIMER1_Msk                                        (0xFFUL << PCC_REG_TIMER1_A_ENTRY_DELAY_CORE1_DEV_TIMER1_Pos)
+
+#define PCC_REG_TIMER1_A_RESERVED_9_Pos                                                          8U
+#define PCC_REG_TIMER1_A_RESERVED_9_Msk                                                          (0x1UL << PCC_REG_TIMER1_A_RESERVED_9_Pos)
+
+#define PCC_REG_TIMER1_A_RESERVED_8_Pos                                                          9U
+#define PCC_REG_TIMER1_A_RESERVED_8_Msk                                                          (0x1UL << PCC_REG_TIMER1_A_RESERVED_8_Pos)
+
+#define PCC_REG_TIMER1_A_RESERVED_7_Pos                                                          10U
+#define PCC_REG_TIMER1_A_RESERVED_7_Msk                                                          (0x1UL << PCC_REG_TIMER1_A_RESERVED_7_Pos)
+
+#define PCC_REG_TIMER1_A_RESERVED_6_Pos                                                          11U
+#define PCC_REG_TIMER1_A_RESERVED_6_Msk                                                          (0x1UL << PCC_REG_TIMER1_A_RESERVED_6_Pos)
+
+#define PCC_REG_TIMER1_A_RESERVED_5_Pos                                                          12U
+#define PCC_REG_TIMER1_A_RESERVED_5_Msk                                                          (0x1UL << PCC_REG_TIMER1_A_RESERVED_5_Pos)
+
+#define PCC_REG_TIMER1_A_RESERVED_4_Pos                                                          13U
+#define PCC_REG_TIMER1_A_RESERVED_4_Msk                                                          (0x1UL << PCC_REG_TIMER1_A_RESERVED_4_Pos)
+
+#define PCC_REG_TIMER1_A_RESERVED_3_Pos                                                          14U
+#define PCC_REG_TIMER1_A_RESERVED_3_Msk                                                          (0x1UL << PCC_REG_TIMER1_A_RESERVED_3_Pos)
+
+#define PCC_REG_TIMER1_A_RESERVED_2_Pos                                                          15U
+#define PCC_REG_TIMER1_A_RESERVED_2_Msk                                                          (0x1UL << PCC_REG_TIMER1_A_RESERVED_2_Pos)
+
+#define PCC_REG_TIMER1_A_RESERVED_1_Pos                                                          16U
+#define PCC_REG_TIMER1_A_RESERVED_1_Msk                                                          (0x1UL << PCC_REG_TIMER1_A_RESERVED_1_Pos)
+
+#define PCC_REG_TIMER1_A_RESERVED_Pos                                                            17U
+#define PCC_REG_TIMER1_A_RESERVED_Msk                                                            (0x1UL << PCC_REG_TIMER1_A_RESERVED_Pos)
+
+#define PCC_REG_TIMER1_A_RSVD_Pos                                                                18U
+#define PCC_REG_TIMER1_A_RSVD_Msk                                                                (0x3UL << PCC_REG_TIMER1_A_RSVD_Pos)
+
+#define PCC_REG_TIMER1_A_R_TIMER_3_CLK_DIV_Pos                                                   20U
+#define PCC_REG_TIMER1_A_R_TIMER_3_CLK_DIV_Msk                                                   (0x7UL << PCC_REG_TIMER1_A_R_TIMER_3_CLK_DIV_Pos)
+
+#define PCC_REG_TIMER1_A_R_TIMER_4_CLK_DIV_Pos                                                   23U
+#define PCC_REG_TIMER1_A_R_TIMER_4_CLK_DIV_Msk                                                   (0x7UL << PCC_REG_TIMER1_A_R_TIMER_4_CLK_DIV_Pos)
+
+#define PCC_REG_TIMER1_A_R_TIMER_5_CLK_DIV_Pos                                                   26U
+#define PCC_REG_TIMER1_A_R_TIMER_5_CLK_DIV_Msk                                                   (0x7UL << PCC_REG_TIMER1_A_R_TIMER_5_CLK_DIV_Pos)
+
+#define PCC_REG_TIMER1_A_TIMER1_CH3_CLK_FORCE_Pos                                                29U
+#define PCC_REG_TIMER1_A_TIMER1_CH3_CLK_FORCE_Msk                                                (0x1UL << PCC_REG_TIMER1_A_TIMER1_CH3_CLK_FORCE_Pos)
+
+#define PCC_REG_TIMER1_A_TIMER1_CH4_CLK_FORCE_Pos                                                30U
+#define PCC_REG_TIMER1_A_TIMER1_CH4_CLK_FORCE_Msk                                                (0x1UL << PCC_REG_TIMER1_A_TIMER1_CH4_CLK_FORCE_Pos)
+
+#define PCC_REG_TIMER1_A_TIMER1_CH5_CLK_FORCE_Pos                                                31U
+#define PCC_REG_TIMER1_A_TIMER1_CH5_CLK_FORCE_Msk                                                (0x1UL << PCC_REG_TIMER1_A_TIMER1_CH5_CLK_FORCE_Pos)
+
+/* 0x24C    0x4000_024c
+    7:0     R/W     RESERVED_11                                     8'b0
+    8       R/W     RESERVED_10                                     1'b0
+    9       R/W     RESERVED_9                                      1'b1
+    10      R/W     RESERVED_8                                      1'b1
+    11      R/W     RESERVED_7                                      1'b1
+    12      R/W     RESERVED_6                                      1'b1
+    13      R/W     RESERVED_5                                      1'b1
+    14      R/W     RESERVED_4                                      1'b1
+    15      R/W     RESERVED_3                                      1'b1
+    16      R/W     RESERVED_2                                      1'b1
+    17      R/W     RESERVED_1                                      1'b1
+    19:18   R/W     RESERVED                                        2'b0
+    22:20   R/W     R_TIMER_6_CLK_DIV                               3'h0
+    25:23   R/W     R_TIMER_7_CLK_DIV                               3'h0
+    28:26   R/W     R_TIMER_8_CLK_DIV                               3'h0
+    29      R/W     TIMER1_CH6_CLK_FORCE                            1'b0
+    30      R/W     TIMER1_CH7_CLK_FORCE                            1'b0
+    31      R/W     TIMER1_CH8_CLK_FORCE                            1'b0
+ */
+typedef union _PCC_REG_TIMER1_B_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED_11: 8;
+        uint32_t RESERVED_10: 1;
+        uint32_t RESERVED_9: 1;
+        uint32_t RESERVED_8: 1;
+        uint32_t RESERVED_7: 1;
+        uint32_t RESERVED_6: 1;
+        uint32_t RESERVED_5: 1;
+        uint32_t RESERVED_4: 1;
+        uint32_t RESERVED_3: 1;
+        uint32_t RESERVED_2: 1;
+        uint32_t RESERVED_1: 1;
+        uint32_t RESERVED: 2;
+        uint32_t R_TIMER_6_CLK_DIV: 3;
+        uint32_t R_TIMER_7_CLK_DIV: 3;
+        uint32_t R_TIMER_8_CLK_DIV: 3;
+        uint32_t TIMER1_CH6_CLK_FORCE: 1;
+        uint32_t TIMER1_CH7_CLK_FORCE: 1;
+        uint32_t TIMER1_CH8_CLK_FORCE: 1;
+    };
+} PCC_REG_TIMER1_B_TYPE;
+
+/*0x4000_024c PCC_REG_TIMER1_B*/
+#define PCC_REG_TIMER1_B_RESERVED_11_Pos                                                         0U
+#define PCC_REG_TIMER1_B_RESERVED_11_Msk                                                         (0xFFUL << PCC_REG_TIMER1_B_RESERVED_11_Pos)
+
+#define PCC_REG_TIMER1_B_RESERVED_10_Pos                                                         8U
+#define PCC_REG_TIMER1_B_RESERVED_10_Msk                                                         (0x1UL << PCC_REG_TIMER1_B_RESERVED_10_Pos)
+
+#define PCC_REG_TIMER1_B_RESERVED_9_Pos                                                          9U
+#define PCC_REG_TIMER1_B_RESERVED_9_Msk                                                          (0x1UL << PCC_REG_TIMER1_B_RESERVED_9_Pos)
+
+#define PCC_REG_TIMER1_B_RESERVED_8_Pos                                                          10U
+#define PCC_REG_TIMER1_B_RESERVED_8_Msk                                                          (0x1UL << PCC_REG_TIMER1_B_RESERVED_8_Pos)
+
+#define PCC_REG_TIMER1_B_RESERVED_7_Pos                                                          11U
+#define PCC_REG_TIMER1_B_RESERVED_7_Msk                                                          (0x1UL << PCC_REG_TIMER1_B_RESERVED_7_Pos)
+
+#define PCC_REG_TIMER1_B_RESERVED_6_Pos                                                          12U
+#define PCC_REG_TIMER1_B_RESERVED_6_Msk                                                          (0x1UL << PCC_REG_TIMER1_B_RESERVED_6_Pos)
+
+#define PCC_REG_TIMER1_B_RESERVED_5_Pos                                                          13U
+#define PCC_REG_TIMER1_B_RESERVED_5_Msk                                                          (0x1UL << PCC_REG_TIMER1_B_RESERVED_5_Pos)
+
+#define PCC_REG_TIMER1_B_RESERVED_4_Pos                                                          14U
+#define PCC_REG_TIMER1_B_RESERVED_4_Msk                                                          (0x1UL << PCC_REG_TIMER1_B_RESERVED_4_Pos)
+
+#define PCC_REG_TIMER1_B_RESERVED_3_Pos                                                          15U
+#define PCC_REG_TIMER1_B_RESERVED_3_Msk                                                          (0x1UL << PCC_REG_TIMER1_B_RESERVED_3_Pos)
+
+#define PCC_REG_TIMER1_B_RESERVED_2_Pos                                                          16U
+#define PCC_REG_TIMER1_B_RESERVED_2_Msk                                                          (0x1UL << PCC_REG_TIMER1_B_RESERVED_2_Pos)
+
+#define PCC_REG_TIMER1_B_RESERVED_1_Pos                                                          17U
+#define PCC_REG_TIMER1_B_RESERVED_1_Msk                                                          (0x1UL << PCC_REG_TIMER1_B_RESERVED_1_Pos)
+
+#define PCC_REG_TIMER1_B_RESERVED_Pos                                                            18U
+#define PCC_REG_TIMER1_B_RESERVED_Msk                                                            (0x3UL << PCC_REG_TIMER1_B_RESERVED_Pos)
+
+#define PCC_REG_TIMER1_B_R_TIMER_6_CLK_DIV_Pos                                                   20U
+#define PCC_REG_TIMER1_B_R_TIMER_6_CLK_DIV_Msk                                                   (0x7UL << PCC_REG_TIMER1_B_R_TIMER_6_CLK_DIV_Pos)
+
+#define PCC_REG_TIMER1_B_R_TIMER_7_CLK_DIV_Pos                                                   23U
+#define PCC_REG_TIMER1_B_R_TIMER_7_CLK_DIV_Msk                                                   (0x7UL << PCC_REG_TIMER1_B_R_TIMER_7_CLK_DIV_Pos)
+
+#define PCC_REG_TIMER1_B_R_TIMER_8_CLK_DIV_Pos                                                   26U
+#define PCC_REG_TIMER1_B_R_TIMER_8_CLK_DIV_Msk                                                   (0x7UL << PCC_REG_TIMER1_B_R_TIMER_8_CLK_DIV_Pos)
+
+#define PCC_REG_TIMER1_B_TIMER1_CH6_CLK_FORCE_Pos                                                29U
+#define PCC_REG_TIMER1_B_TIMER1_CH6_CLK_FORCE_Msk                                                (0x1UL << PCC_REG_TIMER1_B_TIMER1_CH6_CLK_FORCE_Pos)
+
+#define PCC_REG_TIMER1_B_TIMER1_CH7_CLK_FORCE_Pos                                                30U
+#define PCC_REG_TIMER1_B_TIMER1_CH7_CLK_FORCE_Msk                                                (0x1UL << PCC_REG_TIMER1_B_TIMER1_CH7_CLK_FORCE_Pos)
+
+#define PCC_REG_TIMER1_B_TIMER1_CH8_CLK_FORCE_Pos                                                31U
+#define PCC_REG_TIMER1_B_TIMER1_CH8_CLK_FORCE_Msk                                                (0x1UL << PCC_REG_TIMER1_B_TIMER1_CH8_CLK_FORCE_Pos)
+
+/* 0x250    0x4000_0250
+    7:0     R/W     RESERVED_11                                     8'b0
+    8       R/W     RESERVED_10                                     1'b0
+    9       R/W     RESERVED_9                                      1'b1
+    10      R/W     RESERVED_8                                      1'b1
+    11      R/W     RESERVED_7                                      1'b1
+    12      R/W     RESERVED_6                                      1'b1
+    13      R/W     RESERVED_5                                      1'b1
+    14      R/W     RESERVED_4                                      1'b1
+    15      R/W     RESERVED_3                                      1'b1
+    16      R/W     RESERVED_2                                      1'b1
+    17      R/W     RESERVED_1                                      1'b1
+    19:18   R/W     RESERVED                                        2'b0
+    22:20   R/W     R_TIMER_9_CLK_DIV                               3'h0
+    25:23   R/W     R_TIMER_10_CLK_DIV                              3'h0
+    28:26   R/W     R_TIMER_11_CLK_DIV                              3'h0
+    29      R/W     TIMER1_CH9_CLK_FORCE                            1'b0
+    30      R/W     TIMER1_CH10_CLK_FORCE                           1'b0
+    31      R/W     TIMER1_CH11_CLK_FORCE                           1'b0
+ */
+typedef union _PCC_REG_TIMER1_C_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED_11: 8;
+        uint32_t RESERVED_10: 1;
+        uint32_t RESERVED_9: 1;
+        uint32_t RESERVED_8: 1;
+        uint32_t RESERVED_7: 1;
+        uint32_t RESERVED_6: 1;
+        uint32_t RESERVED_5: 1;
+        uint32_t RESERVED_4: 1;
+        uint32_t RESERVED_3: 1;
+        uint32_t RESERVED_2: 1;
+        uint32_t RESERVED_1: 1;
+        uint32_t RESERVED: 2;
+        uint32_t R_TIMER_9_CLK_DIV: 3;
+        uint32_t R_TIMER_10_CLK_DIV: 3;
+        uint32_t R_TIMER_11_CLK_DIV: 3;
+        uint32_t TIMER1_CH9_CLK_FORCE: 1;
+        uint32_t TIMER1_CH10_CLK_FORCE: 1;
+        uint32_t TIMER1_CH11_CLK_FORCE: 1;
+    };
+} PCC_REG_TIMER1_C_TYPE;
+
+/*0x4000_0250 PCC_REG_TIMER1_C*/
+#define PCC_REG_TIMER1_C_RESERVED_11_Pos                                                         0U
+#define PCC_REG_TIMER1_C_RESERVED_11_Msk                                                         (0xFFUL << PCC_REG_TIMER1_C_RESERVED_11_Pos)
+
+#define PCC_REG_TIMER1_C_RESERVED_10_Pos                                                         8U
+#define PCC_REG_TIMER1_C_RESERVED_10_Msk                                                         (0x1UL << PCC_REG_TIMER1_C_RESERVED_10_Pos)
+
+#define PCC_REG_TIMER1_C_RESERVED_9_Pos                                                          9U
+#define PCC_REG_TIMER1_C_RESERVED_9_Msk                                                          (0x1UL << PCC_REG_TIMER1_C_RESERVED_9_Pos)
+
+#define PCC_REG_TIMER1_C_RESERVED_8_Pos                                                          10U
+#define PCC_REG_TIMER1_C_RESERVED_8_Msk                                                          (0x1UL << PCC_REG_TIMER1_C_RESERVED_8_Pos)
+
+#define PCC_REG_TIMER1_C_RESERVED_7_Pos                                                          11U
+#define PCC_REG_TIMER1_C_RESERVED_7_Msk                                                          (0x1UL << PCC_REG_TIMER1_C_RESERVED_7_Pos)
+
+#define PCC_REG_TIMER1_C_RESERVED_6_Pos                                                          12U
+#define PCC_REG_TIMER1_C_RESERVED_6_Msk                                                          (0x1UL << PCC_REG_TIMER1_C_RESERVED_6_Pos)
+
+#define PCC_REG_TIMER1_C_RESERVED_5_Pos                                                          13U
+#define PCC_REG_TIMER1_C_RESERVED_5_Msk                                                          (0x1UL << PCC_REG_TIMER1_C_RESERVED_5_Pos)
+
+#define PCC_REG_TIMER1_C_RESERVED_4_Pos                                                          14U
+#define PCC_REG_TIMER1_C_RESERVED_4_Msk                                                          (0x1UL << PCC_REG_TIMER1_C_RESERVED_4_Pos)
+
+#define PCC_REG_TIMER1_C_RESERVED_3_Pos                                                          15U
+#define PCC_REG_TIMER1_C_RESERVED_3_Msk                                                          (0x1UL << PCC_REG_TIMER1_C_RESERVED_3_Pos)
+
+#define PCC_REG_TIMER1_C_RESERVED_2_Pos                                                          16U
+#define PCC_REG_TIMER1_C_RESERVED_2_Msk                                                          (0x1UL << PCC_REG_TIMER1_C_RESERVED_2_Pos)
+
+#define PCC_REG_TIMER1_C_RESERVED_1_Pos                                                          17U
+#define PCC_REG_TIMER1_C_RESERVED_1_Msk                                                          (0x1UL << PCC_REG_TIMER1_C_RESERVED_1_Pos)
+
+#define PCC_REG_TIMER1_C_RESERVED_Pos                                                            18U
+#define PCC_REG_TIMER1_C_RESERVED_Msk                                                            (0x3UL << PCC_REG_TIMER1_C_RESERVED_Pos)
+
+#define PCC_REG_TIMER1_C_R_TIMER_9_CLK_DIV_Pos                                                   20U
+#define PCC_REG_TIMER1_C_R_TIMER_9_CLK_DIV_Msk                                                   (0x7UL << PCC_REG_TIMER1_C_R_TIMER_9_CLK_DIV_Pos)
+
+#define PCC_REG_TIMER1_C_R_TIMER_10_CLK_DIV_Pos                                                  23U
+#define PCC_REG_TIMER1_C_R_TIMER_10_CLK_DIV_Msk                                                  (0x7UL << PCC_REG_TIMER1_C_R_TIMER_10_CLK_DIV_Pos)
+
+#define PCC_REG_TIMER1_C_R_TIMER_11_CLK_DIV_Pos                                                  26U
+#define PCC_REG_TIMER1_C_R_TIMER_11_CLK_DIV_Msk                                                  (0x7UL << PCC_REG_TIMER1_C_R_TIMER_11_CLK_DIV_Pos)
+
+#define PCC_REG_TIMER1_C_TIMER1_CH9_CLK_FORCE_Pos                                                29U
+#define PCC_REG_TIMER1_C_TIMER1_CH9_CLK_FORCE_Msk                                                (0x1UL << PCC_REG_TIMER1_C_TIMER1_CH9_CLK_FORCE_Pos)
+
+#define PCC_REG_TIMER1_C_TIMER1_CH10_CLK_FORCE_Pos                                               30U
+#define PCC_REG_TIMER1_C_TIMER1_CH10_CLK_FORCE_Msk                                               (0x1UL << PCC_REG_TIMER1_C_TIMER1_CH10_CLK_FORCE_Pos)
+
+#define PCC_REG_TIMER1_C_TIMER1_CH11_CLK_FORCE_Pos                                               31U
+#define PCC_REG_TIMER1_C_TIMER1_CH11_CLK_FORCE_Msk                                               (0x1UL << PCC_REG_TIMER1_C_TIMER1_CH11_CLK_FORCE_Pos)
+
+/* 0x254    0x4000_0254
+    7:0     R/W     ENTRY_DELAY_CORE1_DEV_ENHANCED_TIMER            8'b0
+    8       R/W     RESERVED_12                                     1'b0
+    9       R/W     RESERVED_11                                     1'b1
+    10      R/W     RESERVED_10                                     1'b1
+    11      R/W     RESERVED_9                                      1'b1
+    12      R/W     RESERVED_8                                      1'b1
+    13      R/W     RESERVED_7                                      1'b0
+    14      R/W     RESERVED_6                                      1'b1
+    15      R/W     RESERVED_5                                      1'b0
+    16      R/W     RESERVED_4                                      1'b0
+    19:17   R/W     R_ETIMER_CLK_DIV_SEL                            3'h0
+    20      R/W     RSVD_2                                          1'h0
+    21      R/W     RESERVED_3                                      1'b0
+    22      R/W     RESERVED_2                                      1'b0
+    23      R/W     ENHANCED_TIMER_CLK_FORCE                        1'b0
+    26:24   R/W     RSVD_1                                          3'b000
+    27      R/W     RESERVED_1                                      1'b0
+    30:28   R/W     RSVD                                            3'b000
+    31      R/W     RESERVED                                        1'b0
+ */
+typedef union _PCC_REG_TIMER2_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t ENTRY_DELAY_CORE1_DEV_ENHANCED_TIMER: 8;
+        uint32_t RESERVED_12: 1;
+        uint32_t RESERVED_11: 1;
+        uint32_t RESERVED_10: 1;
+        uint32_t RESERVED_9: 1;
+        uint32_t RESERVED_8: 1;
+        uint32_t RESERVED_7: 1;
+        uint32_t RESERVED_6: 1;
+        uint32_t RESERVED_5: 1;
+        uint32_t RESERVED_4: 1;
+        uint32_t R_ETIMER_CLK_DIV_SEL: 3;
+        uint32_t RSVD_2: 1;
+        uint32_t RESERVED_3: 1;
+        uint32_t RESERVED_2: 1;
+        uint32_t ENHANCED_TIMER_CLK_FORCE: 1;
+        uint32_t RSVD_1: 3;
+        uint32_t RESERVED_1: 1;
+        uint32_t RSVD: 3;
+        uint32_t RESERVED: 1;
+    };
+} PCC_REG_TIMER2_TYPE;
+
+/*0x4000_0254 PCC_REG_TIMER2*/
+#define PCC_REG_TIMER2_ENTRY_DELAY_CORE1_DEV_ENHANCED_TIMER_Pos                                  0U
+#define PCC_REG_TIMER2_ENTRY_DELAY_CORE1_DEV_ENHANCED_TIMER_Msk                                  (0xFFUL << PCC_REG_TIMER2_ENTRY_DELAY_CORE1_DEV_ENHANCED_TIMER_Pos)
+
+#define PCC_REG_TIMER2_RESERVED_12_Pos                                                           8U
+#define PCC_REG_TIMER2_RESERVED_12_Msk                                                           (0x1UL << PCC_REG_TIMER2_RESERVED_12_Pos)
+
+#define PCC_REG_TIMER2_RESERVED_11_Pos                                                           9U
+#define PCC_REG_TIMER2_RESERVED_11_Msk                                                           (0x1UL << PCC_REG_TIMER2_RESERVED_11_Pos)
+
+#define PCC_REG_TIMER2_RESERVED_10_Pos                                                           10U
+#define PCC_REG_TIMER2_RESERVED_10_Msk                                                           (0x1UL << PCC_REG_TIMER2_RESERVED_10_Pos)
+
+#define PCC_REG_TIMER2_RESERVED_9_Pos                                                            11U
+#define PCC_REG_TIMER2_RESERVED_9_Msk                                                            (0x1UL << PCC_REG_TIMER2_RESERVED_9_Pos)
+
+#define PCC_REG_TIMER2_RESERVED_8_Pos                                                            12U
+#define PCC_REG_TIMER2_RESERVED_8_Msk                                                            (0x1UL << PCC_REG_TIMER2_RESERVED_8_Pos)
+
+#define PCC_REG_TIMER2_RESERVED_7_Pos                                                            13U
+#define PCC_REG_TIMER2_RESERVED_7_Msk                                                            (0x1UL << PCC_REG_TIMER2_RESERVED_7_Pos)
+
+#define PCC_REG_TIMER2_RESERVED_6_Pos                                                            14U
+#define PCC_REG_TIMER2_RESERVED_6_Msk                                                            (0x1UL << PCC_REG_TIMER2_RESERVED_6_Pos)
+
+#define PCC_REG_TIMER2_RESERVED_5_Pos                                                            15U
+#define PCC_REG_TIMER2_RESERVED_5_Msk                                                            (0x1UL << PCC_REG_TIMER2_RESERVED_5_Pos)
+
+#define PCC_REG_TIMER2_RESERVED_4_Pos                                                            16U
+#define PCC_REG_TIMER2_RESERVED_4_Msk                                                            (0x1UL << PCC_REG_TIMER2_RESERVED_4_Pos)
+
+#define PCC_REG_TIMER2_R_ETIMER_CLK_DIV_SEL_Pos                                                  17U
+#define PCC_REG_TIMER2_R_ETIMER_CLK_DIV_SEL_Msk                                                  (0x7UL << PCC_REG_TIMER2_R_ETIMER_CLK_DIV_SEL_Pos)
+
+#define PCC_REG_TIMER2_RSVD_2_Pos                                                                20U
+#define PCC_REG_TIMER2_RSVD_2_Msk                                                                (0x1UL << PCC_REG_TIMER2_RSVD_2_Pos)
+
+#define PCC_REG_TIMER2_RESERVED_3_Pos                                                            21U
+#define PCC_REG_TIMER2_RESERVED_3_Msk                                                            (0x1UL << PCC_REG_TIMER2_RESERVED_3_Pos)
+
+#define PCC_REG_TIMER2_RESERVED_2_Pos                                                            22U
+#define PCC_REG_TIMER2_RESERVED_2_Msk                                                            (0x1UL << PCC_REG_TIMER2_RESERVED_2_Pos)
+
+#define PCC_REG_TIMER2_ENHANCED_TIMER_CLK_FORCE_Pos                                              23U
+#define PCC_REG_TIMER2_ENHANCED_TIMER_CLK_FORCE_Msk                                              (0x1UL << PCC_REG_TIMER2_ENHANCED_TIMER_CLK_FORCE_Pos)
+
+#define PCC_REG_TIMER2_RSVD_1_Pos                                                                24U
+#define PCC_REG_TIMER2_RSVD_1_Msk                                                                (0x7UL << PCC_REG_TIMER2_RSVD_1_Pos)
+
+#define PCC_REG_TIMER2_RESERVED_1_Pos                                                            27U
+#define PCC_REG_TIMER2_RESERVED_1_Msk                                                            (0x1UL << PCC_REG_TIMER2_RESERVED_1_Pos)
+
+#define PCC_REG_TIMER2_RSVD_Pos                                                                  28U
+#define PCC_REG_TIMER2_RSVD_Msk                                                                  (0x7UL << PCC_REG_TIMER2_RSVD_Pos)
+
+#define PCC_REG_TIMER2_RESERVED_Pos                                                              31U
+#define PCC_REG_TIMER2_RESERVED_Msk                                                              (0x1UL << PCC_REG_TIMER2_RESERVED_Pos)
+
+/* 0x258    0x4000_0258
+    7:0     R/W     ENTRY_DELAY_CORE1_DEV_ENHANCED_TIMER_PWM        8'b0
+    8       R/W     RESERVED_11                                     1'b0
+    9       R/W     RESERVED_10                                     1'b1
+    10      R/W     RESERVED_9                                      1'b1
+    11      R/W     RESERVED_8                                      1'b0
+    12      R/W     RESERVED_7                                      1'b1
+    13      R/W     RESERVED_6                                      1'b0
+    14      R/W     RESERVED_5                                      1'b1
+    15      R/W     RESERVED_4                                      1'b0
+    16      R/W     R_ETIMER_PWM_CLK_SRC_SEL                        1'b0
+    19:17   R/W     R_ETIMER_PWM_CLK_DIV_SEL                        3'h0
+    20      R/W     RSVD_2                                          1'h0
+    21      R/W     RESERVED_3                                      1'b0
+    22      R/W     RESERVED_2                                      1'b0
+    23      R/W     ENHANCED_TIMER_PWM_CLK_FORCE                    1'b0
+    26:24   R/W     RSVD_1                                          3'b000
+    27      R/W     RESERVED_1                                      1'b0
+    30:28   R/W     RSVD                                            3'b000
+    31      R/W     RESERVED                                        1'b0
+ */
+typedef union _PCC_REG_TIMER2_PWM_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t ENTRY_DELAY_CORE1_DEV_ENHANCED_TIMER_PWM: 8;
+        uint32_t RESERVED_11: 1;
+        uint32_t RESERVED_10: 1;
+        uint32_t RESERVED_9: 1;
+        uint32_t RESERVED_8: 1;
+        uint32_t RESERVED_7: 1;
+        uint32_t RESERVED_6: 1;
+        uint32_t RESERVED_5: 1;
+        uint32_t RESERVED_4: 1;
+        uint32_t R_ETIMER_PWM_CLK_SRC_SEL: 1;
+        uint32_t R_ETIMER_PWM_CLK_DIV_SEL: 3;
+        uint32_t RSVD_2: 1;
+        uint32_t RESERVED_3: 1;
+        uint32_t RESERVED_2: 1;
+        uint32_t ENHANCED_TIMER_PWM_CLK_FORCE: 1;
+        uint32_t RSVD_1: 3;
+        uint32_t RESERVED_1: 1;
+        uint32_t RSVD: 3;
+        uint32_t RESERVED: 1;
+    };
+} PCC_REG_TIMER2_PWM_TYPE;
+
+/*0x4000_0258 PCC_REG_TIMER2_PWM*/
+#define PCC_REG_TIMER2_PWM_ENTRY_DELAY_CORE1_DEV_ENHANCED_TIMER_PWM_Pos                          0U
+#define PCC_REG_TIMER2_PWM_ENTRY_DELAY_CORE1_DEV_ENHANCED_TIMER_PWM_Msk                          (0xFFUL << PCC_REG_TIMER2_PWM_ENTRY_DELAY_CORE1_DEV_ENHANCED_TIMER_PWM_Pos)
+
+#define PCC_REG_TIMER2_PWM_RESERVED_11_Pos                                                       8U
+#define PCC_REG_TIMER2_PWM_RESERVED_11_Msk                                                       (0x1UL << PCC_REG_TIMER2_PWM_RESERVED_11_Pos)
+
+#define PCC_REG_TIMER2_PWM_RESERVED_10_Pos                                                       9U
+#define PCC_REG_TIMER2_PWM_RESERVED_10_Msk                                                       (0x1UL << PCC_REG_TIMER2_PWM_RESERVED_10_Pos)
+
+#define PCC_REG_TIMER2_PWM_RESERVED_9_Pos                                                        10U
+#define PCC_REG_TIMER2_PWM_RESERVED_9_Msk                                                        (0x1UL << PCC_REG_TIMER2_PWM_RESERVED_9_Pos)
+
+#define PCC_REG_TIMER2_PWM_RESERVED_8_Pos                                                        11U
+#define PCC_REG_TIMER2_PWM_RESERVED_8_Msk                                                        (0x1UL << PCC_REG_TIMER2_PWM_RESERVED_8_Pos)
+
+#define PCC_REG_TIMER2_PWM_RESERVED_7_Pos                                                        12U
+#define PCC_REG_TIMER2_PWM_RESERVED_7_Msk                                                        (0x1UL << PCC_REG_TIMER2_PWM_RESERVED_7_Pos)
+
+#define PCC_REG_TIMER2_PWM_RESERVED_6_Pos                                                        13U
+#define PCC_REG_TIMER2_PWM_RESERVED_6_Msk                                                        (0x1UL << PCC_REG_TIMER2_PWM_RESERVED_6_Pos)
+
+#define PCC_REG_TIMER2_PWM_RESERVED_5_Pos                                                        14U
+#define PCC_REG_TIMER2_PWM_RESERVED_5_Msk                                                        (0x1UL << PCC_REG_TIMER2_PWM_RESERVED_5_Pos)
+
+#define PCC_REG_TIMER2_PWM_RESERVED_4_Pos                                                        15U
+#define PCC_REG_TIMER2_PWM_RESERVED_4_Msk                                                        (0x1UL << PCC_REG_TIMER2_PWM_RESERVED_4_Pos)
+
+#define PCC_REG_TIMER2_PWM_R_ETIMER_PWM_CLK_SRC_SEL_Pos                                          16U
+#define PCC_REG_TIMER2_PWM_R_ETIMER_PWM_CLK_SRC_SEL_Msk                                          (0x1UL << PCC_REG_TIMER2_PWM_R_ETIMER_PWM_CLK_SRC_SEL_Pos)
+
+#define PCC_REG_TIMER2_PWM_R_ETIMER_PWM_CLK_DIV_SEL_Pos                                          17U
+#define PCC_REG_TIMER2_PWM_R_ETIMER_PWM_CLK_DIV_SEL_Msk                                          (0x7UL << PCC_REG_TIMER2_PWM_R_ETIMER_PWM_CLK_DIV_SEL_Pos)
+
+#define PCC_REG_TIMER2_PWM_RSVD_2_Pos                                                            20U
+#define PCC_REG_TIMER2_PWM_RSVD_2_Msk                                                            (0x1UL << PCC_REG_TIMER2_PWM_RSVD_2_Pos)
+
+#define PCC_REG_TIMER2_PWM_RESERVED_3_Pos                                                        21U
+#define PCC_REG_TIMER2_PWM_RESERVED_3_Msk                                                        (0x1UL << PCC_REG_TIMER2_PWM_RESERVED_3_Pos)
+
+#define PCC_REG_TIMER2_PWM_RESERVED_2_Pos                                                        22U
+#define PCC_REG_TIMER2_PWM_RESERVED_2_Msk                                                        (0x1UL << PCC_REG_TIMER2_PWM_RESERVED_2_Pos)
+
+#define PCC_REG_TIMER2_PWM_ENHANCED_TIMER_PWM_CLK_FORCE_Pos                                      23U
+#define PCC_REG_TIMER2_PWM_ENHANCED_TIMER_PWM_CLK_FORCE_Msk                                      (0x1UL << PCC_REG_TIMER2_PWM_ENHANCED_TIMER_PWM_CLK_FORCE_Pos)
+
+#define PCC_REG_TIMER2_PWM_RSVD_1_Pos                                                            24U
+#define PCC_REG_TIMER2_PWM_RSVD_1_Msk                                                            (0x7UL << PCC_REG_TIMER2_PWM_RSVD_1_Pos)
+
+#define PCC_REG_TIMER2_PWM_RESERVED_1_Pos                                                        27U
+#define PCC_REG_TIMER2_PWM_RESERVED_1_Msk                                                        (0x1UL << PCC_REG_TIMER2_PWM_RESERVED_1_Pos)
+
+#define PCC_REG_TIMER2_PWM_RSVD_Pos                                                              28U
+#define PCC_REG_TIMER2_PWM_RSVD_Msk                                                              (0x7UL << PCC_REG_TIMER2_PWM_RSVD_Pos)
+
+#define PCC_REG_TIMER2_PWM_RESERVED_Pos                                                          31U
+#define PCC_REG_TIMER2_PWM_RESERVED_Msk                                                          (0x1UL << PCC_REG_TIMER2_PWM_RESERVED_Pos)
+
+/* 0x25C    0x4000_025c
+    7:0     R/W     ENTRY_DELAY_USB                                 8'b0
+    8       R/W     RESERVED_9                                      1'b1
+    9       R/W     RESERVED_8                                      1'b1
+    10      R/W     RESERVED_7                                      1'b1
+    11      R/W     RESERVED_6                                      1'b0
+    12      R/W     RESERVED_5                                      1'b1
+    13      R/W     RESERVED_4                                      1'b1
+    15:14   R/W     RESERVED_3                                      2'b0
+    16      R/W     R_USB_CLK_SRC_SEL                               1'b0
+    20:17   R/W     R_USB_CLK_DIV_SEL                               4'h0
+    21      R/W     RSVD_2                                          1'h0
+    22      R/W     RESERVED_2                                      1'b0
+    23      R/W     USB_CLK_FORCE                                   1'b0
+    26:24   R/W     RSVD_1                                          3'b000
+    27      R/W     RESERVED_1                                      1'b0
+    30:28   R/W     RSVD                                            3'b000
+    31      R/W     RESERVED                                        1'b0
+ */
+typedef union _PCC_REG_USB_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t ENTRY_DELAY_USB: 8;
+        uint32_t RESERVED_9: 1;
+        uint32_t RESERVED_8: 1;
+        uint32_t RESERVED_7: 1;
+        uint32_t RESERVED_6: 1;
+        uint32_t RESERVED_5: 1;
+        uint32_t RESERVED_4: 1;
+        uint32_t RESERVED_3: 2;
+        uint32_t R_USB_CLK_SRC_SEL: 1;
+        uint32_t R_USB_CLK_DIV_SEL: 4;
+        uint32_t RSVD_2: 1;
+        uint32_t RESERVED_2: 1;
+        uint32_t USB_CLK_FORCE: 1;
+        uint32_t RSVD_1: 3;
+        uint32_t RESERVED_1: 1;
+        uint32_t RSVD: 3;
+        uint32_t RESERVED: 1;
+    };
+} PCC_REG_USB_TYPE;
+
+/*0x4000_025c PCC_REG_USB*/
+#define PCC_REG_USB_ENTRY_DELAY_USB_Pos                                                          0U
+#define PCC_REG_USB_ENTRY_DELAY_USB_Msk                                                          (0xFFUL << PCC_REG_USB_ENTRY_DELAY_USB_Pos)
+
+#define PCC_REG_USB_RESERVED_9_Pos                                                               8U
+#define PCC_REG_USB_RESERVED_9_Msk                                                               (0x1UL << PCC_REG_USB_RESERVED_9_Pos)
+
+#define PCC_REG_USB_RESERVED_8_Pos                                                               9U
+#define PCC_REG_USB_RESERVED_8_Msk                                                               (0x1UL << PCC_REG_USB_RESERVED_8_Pos)
+
+#define PCC_REG_USB_RESERVED_7_Pos                                                               10U
+#define PCC_REG_USB_RESERVED_7_Msk                                                               (0x1UL << PCC_REG_USB_RESERVED_7_Pos)
+
+#define PCC_REG_USB_RESERVED_6_Pos                                                               11U
+#define PCC_REG_USB_RESERVED_6_Msk                                                               (0x1UL << PCC_REG_USB_RESERVED_6_Pos)
+
+#define PCC_REG_USB_RESERVED_5_Pos                                                               12U
+#define PCC_REG_USB_RESERVED_5_Msk                                                               (0x1UL << PCC_REG_USB_RESERVED_5_Pos)
+
+#define PCC_REG_USB_RESERVED_4_Pos                                                               13U
+#define PCC_REG_USB_RESERVED_4_Msk                                                               (0x1UL << PCC_REG_USB_RESERVED_4_Pos)
+
+#define PCC_REG_USB_RESERVED_3_Pos                                                               14U
+#define PCC_REG_USB_RESERVED_3_Msk                                                               (0x3UL << PCC_REG_USB_RESERVED_3_Pos)
+
+#define PCC_REG_USB_R_USB_CLK_SRC_SEL_Pos                                                        16U
+#define PCC_REG_USB_R_USB_CLK_SRC_SEL_Msk                                                        (0x1UL << PCC_REG_USB_R_USB_CLK_SRC_SEL_Pos)
+
+#define PCC_REG_USB_R_USB_CLK_DIV_SEL_Pos                                                        17U
+#define PCC_REG_USB_R_USB_CLK_DIV_SEL_Msk                                                        (0xFUL << PCC_REG_USB_R_USB_CLK_DIV_SEL_Pos)
+
+#define PCC_REG_USB_RSVD_2_Pos                                                                   21U
+#define PCC_REG_USB_RSVD_2_Msk                                                                   (0x1UL << PCC_REG_USB_RSVD_2_Pos)
+
+#define PCC_REG_USB_RESERVED_2_Pos                                                               22U
+#define PCC_REG_USB_RESERVED_2_Msk                                                               (0x1UL << PCC_REG_USB_RESERVED_2_Pos)
+
+#define PCC_REG_USB_USB_CLK_FORCE_Pos                                                            23U
+#define PCC_REG_USB_USB_CLK_FORCE_Msk                                                            (0x1UL << PCC_REG_USB_USB_CLK_FORCE_Pos)
+
+#define PCC_REG_USB_RSVD_1_Pos                                                                   24U
+#define PCC_REG_USB_RSVD_1_Msk                                                                   (0x7UL << PCC_REG_USB_RSVD_1_Pos)
+
+#define PCC_REG_USB_RESERVED_1_Pos                                                               27U
+#define PCC_REG_USB_RESERVED_1_Msk                                                               (0x1UL << PCC_REG_USB_RESERVED_1_Pos)
+
+#define PCC_REG_USB_RSVD_Pos                                                                     28U
+#define PCC_REG_USB_RSVD_Msk                                                                     (0x7UL << PCC_REG_USB_RSVD_Pos)
+
+#define PCC_REG_USB_RESERVED_Pos                                                                 31U
+#define PCC_REG_USB_RESERVED_Msk                                                                 (0x1UL << PCC_REG_USB_RESERVED_Pos)
+
+/* 0x260    0x4000_0260
+    7:0     R/W     ENTRY_DELAY_CORE1_DEV_AUXADC                    8'b0
+    8       R/W     RESERVED_8                                      1'b0
+    9       R/W     RESERVED_7                                      1'b1
+    10      R/W     RESERVED_6                                      1'b1
+    11      R/W     RESERVED_5                                      1'b1
+    12      R/W     RESERVED_4                                      1'b1
+    16:13   R/W     RESERVED_3                                      4'b0
+    17      R/W     RESERVED_2                                      1'b0
+    18      R/W     ADC_CLK_FORCE                                   1'b0
+    26:19   R/W     RSVD_1                                          8'b000
+    27      R/W     RESERVED_1                                      1'b0
+    30:28   R/W     RSVD                                            3'b000
+    31      R/W     RESERVED                                        1'b0
+ */
+typedef union _PCC_REG_ADC_CONTROLLER_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t ENTRY_DELAY_CORE1_DEV_AUXADC: 8;
+        uint32_t RESERVED_8: 1;
+        uint32_t RESERVED_7: 1;
+        uint32_t RESERVED_6: 1;
+        uint32_t RESERVED_5: 1;
+        uint32_t RESERVED_4: 1;
+        uint32_t RESERVED_3: 4;
+        uint32_t RESERVED_2: 1;
+        uint32_t ADC_CLK_FORCE: 1;
+        uint32_t RSVD_1: 8;
+        uint32_t RESERVED_1: 1;
+        uint32_t RSVD: 3;
+        uint32_t RESERVED: 1;
+    };
+} PCC_REG_ADC_CONTROLLER_TYPE;
+
+/*0x4000_0260 PCC_REG_ADC_CONTROLLER*/
+#define PCC_REG_ADC_CONTROLLER_ENTRY_DELAY_CORE1_DEV_AUXADC_Pos                                  0U
+#define PCC_REG_ADC_CONTROLLER_ENTRY_DELAY_CORE1_DEV_AUXADC_Msk                                  (0xFFUL << PCC_REG_ADC_CONTROLLER_ENTRY_DELAY_CORE1_DEV_AUXADC_Pos)
+
+#define PCC_REG_ADC_CONTROLLER_RESERVED_8_Pos                                                    8U
+#define PCC_REG_ADC_CONTROLLER_RESERVED_8_Msk                                                    (0x1UL << PCC_REG_ADC_CONTROLLER_RESERVED_8_Pos)
+
+#define PCC_REG_ADC_CONTROLLER_RESERVED_7_Pos                                                    9U
+#define PCC_REG_ADC_CONTROLLER_RESERVED_7_Msk                                                    (0x1UL << PCC_REG_ADC_CONTROLLER_RESERVED_7_Pos)
+
+#define PCC_REG_ADC_CONTROLLER_RESERVED_6_Pos                                                    10U
+#define PCC_REG_ADC_CONTROLLER_RESERVED_6_Msk                                                    (0x1UL << PCC_REG_ADC_CONTROLLER_RESERVED_6_Pos)
+
+#define PCC_REG_ADC_CONTROLLER_RESERVED_5_Pos                                                    11U
+#define PCC_REG_ADC_CONTROLLER_RESERVED_5_Msk                                                    (0x1UL << PCC_REG_ADC_CONTROLLER_RESERVED_5_Pos)
+
+#define PCC_REG_ADC_CONTROLLER_RESERVED_4_Pos                                                    12U
+#define PCC_REG_ADC_CONTROLLER_RESERVED_4_Msk                                                    (0x1UL << PCC_REG_ADC_CONTROLLER_RESERVED_4_Pos)
+
+#define PCC_REG_ADC_CONTROLLER_RESERVED_3_Pos                                                    13U
+#define PCC_REG_ADC_CONTROLLER_RESERVED_3_Msk                                                    (0xFUL << PCC_REG_ADC_CONTROLLER_RESERVED_3_Pos)
+
+#define PCC_REG_ADC_CONTROLLER_RESERVED_2_Pos                                                    17U
+#define PCC_REG_ADC_CONTROLLER_RESERVED_2_Msk                                                    (0x1UL << PCC_REG_ADC_CONTROLLER_RESERVED_2_Pos)
+
+#define PCC_REG_ADC_CONTROLLER_ADC_CLK_FORCE_Pos                                                 18U
+#define PCC_REG_ADC_CONTROLLER_ADC_CLK_FORCE_Msk                                                 (0x1UL << PCC_REG_ADC_CONTROLLER_ADC_CLK_FORCE_Pos)
+
+#define PCC_REG_ADC_CONTROLLER_RSVD_1_Pos                                                        19U
+#define PCC_REG_ADC_CONTROLLER_RSVD_1_Msk                                                        (0xFFUL << PCC_REG_ADC_CONTROLLER_RSVD_1_Pos)
+
+#define PCC_REG_ADC_CONTROLLER_RESERVED_1_Pos                                                    27U
+#define PCC_REG_ADC_CONTROLLER_RESERVED_1_Msk                                                    (0x1UL << PCC_REG_ADC_CONTROLLER_RESERVED_1_Pos)
+
+#define PCC_REG_ADC_CONTROLLER_RSVD_Pos                                                          28U
+#define PCC_REG_ADC_CONTROLLER_RSVD_Msk                                                          (0x7UL << PCC_REG_ADC_CONTROLLER_RSVD_Pos)
+
+#define PCC_REG_ADC_CONTROLLER_RESERVED_Pos                                                      31U
+#define PCC_REG_ADC_CONTROLLER_RESERVED_Msk                                                      (0x1UL << PCC_REG_ADC_CONTROLLER_RESERVED_Pos)
+
+/* 0x264    0x4000_0264
+    7:0     R/W     ENTRY_DELAY_CORE1_DEV_I2C0                      8'b0
+    8       R/W     RESERVED_9                                      1'b0
+    9       R/W     RESERVED_8                                      1'b1
+    10      R/W     RESERVED_7                                      1'b1
+    11      R/W     RESERVED_6                                      1'b1
+    12      R/W     RESERVED_5                                      1'b1
+    15:13   R/W     RESERVED_4                                      3'b0
+    18:16   R/W     R_I2C0_CLK_DIV_SEL                              3'b000
+    20:19   R/W     RSVD_2                                          2'h0
+    21      R/W     RESERVED_3                                      1'b0
+    22      R/W     RESERVED_2                                      1'b0
+    23      R/W     I2C0_CLK_FORCE                                  1'b0
+    26:24   R/W     RSVD_1                                          3'b000
+    27      R/W     RESERVED_1                                      1'b0
+    30:28   R/W     RSVD                                            3'b000
+    31      R/W     RESERVED                                        1'b0
+ */
+typedef union _PCC_REG_I2C0_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t ENTRY_DELAY_CORE1_DEV_I2C0: 8;
+        uint32_t RESERVED_9: 1;
+        uint32_t RESERVED_8: 1;
+        uint32_t RESERVED_7: 1;
+        uint32_t RESERVED_6: 1;
+        uint32_t RESERVED_5: 1;
+        uint32_t RESERVED_4: 3;
+        uint32_t R_I2C0_CLK_DIV_SEL: 3;
+        uint32_t RSVD_2: 2;
+        uint32_t RESERVED_3: 1;
+        uint32_t RESERVED_2: 1;
+        uint32_t I2C0_CLK_FORCE: 1;
+        uint32_t RSVD_1: 3;
+        uint32_t RESERVED_1: 1;
+        uint32_t RSVD: 3;
+        uint32_t RESERVED: 1;
+    };
+} PCC_REG_I2C0_TYPE;
+
+/*0x4000_0264 PCC_REG_I2C0*/
+#define PCC_REG_I2C0_ENTRY_DELAY_CORE1_DEV_I2C0_Pos                                              0U
+#define PCC_REG_I2C0_ENTRY_DELAY_CORE1_DEV_I2C0_Msk                                              (0xFFUL << PCC_REG_I2C0_ENTRY_DELAY_CORE1_DEV_I2C0_Pos)
+
+#define PCC_REG_I2C0_RESERVED_9_Pos                                                              8U
+#define PCC_REG_I2C0_RESERVED_9_Msk                                                              (0x1UL << PCC_REG_I2C0_RESERVED_9_Pos)
+
+#define PCC_REG_I2C0_RESERVED_8_Pos                                                              9U
+#define PCC_REG_I2C0_RESERVED_8_Msk                                                              (0x1UL << PCC_REG_I2C0_RESERVED_8_Pos)
+
+#define PCC_REG_I2C0_RESERVED_7_Pos                                                              10U
+#define PCC_REG_I2C0_RESERVED_7_Msk                                                              (0x1UL << PCC_REG_I2C0_RESERVED_7_Pos)
+
+#define PCC_REG_I2C0_RESERVED_6_Pos                                                              11U
+#define PCC_REG_I2C0_RESERVED_6_Msk                                                              (0x1UL << PCC_REG_I2C0_RESERVED_6_Pos)
+
+#define PCC_REG_I2C0_RESERVED_5_Pos                                                              12U
+#define PCC_REG_I2C0_RESERVED_5_Msk                                                              (0x1UL << PCC_REG_I2C0_RESERVED_5_Pos)
+
+#define PCC_REG_I2C0_RESERVED_4_Pos                                                              13U
+#define PCC_REG_I2C0_RESERVED_4_Msk                                                              (0x7UL << PCC_REG_I2C0_RESERVED_4_Pos)
+
+#define PCC_REG_I2C0_R_I2C0_CLK_DIV_SEL_Pos                                                      16U
+#define PCC_REG_I2C0_R_I2C0_CLK_DIV_SEL_Msk                                                      (0x7UL << PCC_REG_I2C0_R_I2C0_CLK_DIV_SEL_Pos)
+
+#define PCC_REG_I2C0_RSVD_2_Pos                                                                  19U
+#define PCC_REG_I2C0_RSVD_2_Msk                                                                  (0x3UL << PCC_REG_I2C0_RSVD_2_Pos)
+
+#define PCC_REG_I2C0_RESERVED_3_Pos                                                              21U
+#define PCC_REG_I2C0_RESERVED_3_Msk                                                              (0x1UL << PCC_REG_I2C0_RESERVED_3_Pos)
+
+#define PCC_REG_I2C0_RESERVED_2_Pos                                                              22U
+#define PCC_REG_I2C0_RESERVED_2_Msk                                                              (0x1UL << PCC_REG_I2C0_RESERVED_2_Pos)
+
+#define PCC_REG_I2C0_I2C0_CLK_FORCE_Pos                                                          23U
+#define PCC_REG_I2C0_I2C0_CLK_FORCE_Msk                                                          (0x1UL << PCC_REG_I2C0_I2C0_CLK_FORCE_Pos)
+
+#define PCC_REG_I2C0_RSVD_1_Pos                                                                  24U
+#define PCC_REG_I2C0_RSVD_1_Msk                                                                  (0x7UL << PCC_REG_I2C0_RSVD_1_Pos)
+
+#define PCC_REG_I2C0_RESERVED_1_Pos                                                              27U
+#define PCC_REG_I2C0_RESERVED_1_Msk                                                              (0x1UL << PCC_REG_I2C0_RESERVED_1_Pos)
+
+#define PCC_REG_I2C0_RSVD_Pos                                                                    28U
+#define PCC_REG_I2C0_RSVD_Msk                                                                    (0x7UL << PCC_REG_I2C0_RSVD_Pos)
+
+#define PCC_REG_I2C0_RESERVED_Pos                                                                31U
+#define PCC_REG_I2C0_RESERVED_Msk                                                                (0x1UL << PCC_REG_I2C0_RESERVED_Pos)
+
+/* 0x268    0x4000_0268
+    7:0     R/W     ENTRY_DELAY_CORE1_DEV_I2C1                      8'b0
+    8       R/W     RESERVED_10                                     1'b0
+    9       R/W     RESERVED_9                                      1'b1
+    10      R/W     RESERVED_8                                      1'b1
+    11      R/W     RESERVED_7                                      1'b1
+    12      R/W     RESERVED_6                                      1'b1
+    15:13   R/W     RESERVED_5                                      3'b0
+    18:16   R/W     R_I2C1_CLK_DIV_SEL                              3'b000
+    19      R/W     RSVD_2                                          1'h0
+    20      R/W     RESERVED_4                                      1'b0
+    21      R/W     RESERVED_3                                      1'b0
+    22      R/W     I2C1_CLK_FORCE                                  1'b0
+    25:23   R/W     RSVD_1                                          3'b000
+    26      R/W     RESERVED_2                                      1'b0
+    27      R/W     RESERVED_1                                      1'b0
+    30:28   R/W     RSVD                                            3'b000
+    31      R/W     RESERVED                                        1'b0
+ */
+typedef union _PCC_REG_I2C1_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t ENTRY_DELAY_CORE1_DEV_I2C1: 8;
+        uint32_t RESERVED_10: 1;
+        uint32_t RESERVED_9: 1;
+        uint32_t RESERVED_8: 1;
+        uint32_t RESERVED_7: 1;
+        uint32_t RESERVED_6: 1;
+        uint32_t RESERVED_5: 3;
+        uint32_t R_I2C1_CLK_DIV_SEL: 3;
+        uint32_t RSVD_2: 1;
+        uint32_t RESERVED_4: 1;
+        uint32_t RESERVED_3: 1;
+        uint32_t I2C1_CLK_FORCE: 1;
+        uint32_t RSVD_1: 3;
+        uint32_t RESERVED_2: 1;
+        uint32_t RESERVED_1: 1;
+        uint32_t RSVD: 3;
+        uint32_t RESERVED: 1;
+    };
+} PCC_REG_I2C1_TYPE;
+
+/*0x4000_0268 PCC_REG_I2C1*/
+#define PCC_REG_I2C1_ENTRY_DELAY_CORE1_DEV_I2C1_Pos                                              0U
+#define PCC_REG_I2C1_ENTRY_DELAY_CORE1_DEV_I2C1_Msk                                              (0xFFUL << PCC_REG_I2C1_ENTRY_DELAY_CORE1_DEV_I2C1_Pos)
+
+#define PCC_REG_I2C1_RESERVED_10_Pos                                                             8U
+#define PCC_REG_I2C1_RESERVED_10_Msk                                                             (0x1UL << PCC_REG_I2C1_RESERVED_10_Pos)
+
+#define PCC_REG_I2C1_RESERVED_9_Pos                                                              9U
+#define PCC_REG_I2C1_RESERVED_9_Msk                                                              (0x1UL << PCC_REG_I2C1_RESERVED_9_Pos)
+
+#define PCC_REG_I2C1_RESERVED_8_Pos                                                              10U
+#define PCC_REG_I2C1_RESERVED_8_Msk                                                              (0x1UL << PCC_REG_I2C1_RESERVED_8_Pos)
+
+#define PCC_REG_I2C1_RESERVED_7_Pos                                                              11U
+#define PCC_REG_I2C1_RESERVED_7_Msk                                                              (0x1UL << PCC_REG_I2C1_RESERVED_7_Pos)
+
+#define PCC_REG_I2C1_RESERVED_6_Pos                                                              12U
+#define PCC_REG_I2C1_RESERVED_6_Msk                                                              (0x1UL << PCC_REG_I2C1_RESERVED_6_Pos)
+
+#define PCC_REG_I2C1_RESERVED_5_Pos                                                              13U
+#define PCC_REG_I2C1_RESERVED_5_Msk                                                              (0x7UL << PCC_REG_I2C1_RESERVED_5_Pos)
+
+#define PCC_REG_I2C1_R_I2C1_CLK_DIV_SEL_Pos                                                      16U
+#define PCC_REG_I2C1_R_I2C1_CLK_DIV_SEL_Msk                                                      (0x7UL << PCC_REG_I2C1_R_I2C1_CLK_DIV_SEL_Pos)
+
+#define PCC_REG_I2C1_RSVD_2_Pos                                                                  19U
+#define PCC_REG_I2C1_RSVD_2_Msk                                                                  (0x1UL << PCC_REG_I2C1_RSVD_2_Pos)
+
+#define PCC_REG_I2C1_RESERVED_4_Pos                                                              20U
+#define PCC_REG_I2C1_RESERVED_4_Msk                                                              (0x1UL << PCC_REG_I2C1_RESERVED_4_Pos)
+
+#define PCC_REG_I2C1_RESERVED_3_Pos                                                              21U
+#define PCC_REG_I2C1_RESERVED_3_Msk                                                              (0x1UL << PCC_REG_I2C1_RESERVED_3_Pos)
+
+#define PCC_REG_I2C1_I2C1_CLK_FORCE_Pos                                                          22U
+#define PCC_REG_I2C1_I2C1_CLK_FORCE_Msk                                                          (0x1UL << PCC_REG_I2C1_I2C1_CLK_FORCE_Pos)
+
+#define PCC_REG_I2C1_RSVD_1_Pos                                                                  23U
+#define PCC_REG_I2C1_RSVD_1_Msk                                                                  (0x7UL << PCC_REG_I2C1_RSVD_1_Pos)
+
+#define PCC_REG_I2C1_RESERVED_2_Pos                                                              26U
+#define PCC_REG_I2C1_RESERVED_2_Msk                                                              (0x1UL << PCC_REG_I2C1_RESERVED_2_Pos)
+
+#define PCC_REG_I2C1_RESERVED_1_Pos                                                              27U
+#define PCC_REG_I2C1_RESERVED_1_Msk                                                              (0x1UL << PCC_REG_I2C1_RESERVED_1_Pos)
+
+#define PCC_REG_I2C1_RSVD_Pos                                                                    28U
+#define PCC_REG_I2C1_RSVD_Msk                                                                    (0x7UL << PCC_REG_I2C1_RSVD_Pos)
+
+#define PCC_REG_I2C1_RESERVED_Pos                                                                31U
+#define PCC_REG_I2C1_RESERVED_Msk                                                                (0x1UL << PCC_REG_I2C1_RESERVED_Pos)
+
+/* 0x26C    0x4000_026c
+    7:0     R/W     ENTRY_DELAY_CORE1_DEV_KEYSCAN                   8'b0
+    8       R/W     RESERVED_13                                     1'b0
+    9       R/W     RESERVED_12                                     1'b1
+    10      R/W     RESERVED_11                                     1'b1
+    11      R/W     RESERVED_10                                     1'b1
+    12      R/W     RESERVED_9                                      1'b1
+    15:13   R/W     RSVD_2                                          3'h0
+    16      R/W     RESERVED_8                                      1'b0
+    17      R/W     RESERVED_7                                      1'b0
+    18      R/W     KEYSCAN_CLK_FORCE                               1'b0
+    21:19   R/W     RSVD_1                                          3'b000
+    22      R/W     RESERVED_6                                      1'b0
+    23      R/W     RESERVED_5                                      1'b0
+    24      R/W     RESERVED_4                                      1'b0
+    25      R/W     RESERVED_3                                      1'b0
+    26      R/W     RESERVED_2                                      1'b0
+    27      R/W     RESERVED_1                                      1'b0
+    30:28   R/W     RSVD                                            3'b000
+    31      R/W     RESERVED                                        1'b0
+ */
+typedef union _PCC_REG_Keyscan_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t ENTRY_DELAY_CORE1_DEV_KEYSCAN: 8;
+        uint32_t RESERVED_13: 1;
+        uint32_t RESERVED_12: 1;
+        uint32_t RESERVED_11: 1;
+        uint32_t RESERVED_10: 1;
+        uint32_t RESERVED_9: 1;
+        uint32_t RSVD_2: 3;
+        uint32_t RESERVED_8: 1;
+        uint32_t RESERVED_7: 1;
+        uint32_t KEYSCAN_CLK_FORCE: 1;
+        uint32_t RSVD_1: 3;
+        uint32_t RESERVED_6: 1;
+        uint32_t RESERVED_5: 1;
+        uint32_t RESERVED_4: 1;
+        uint32_t RESERVED_3: 1;
+        uint32_t RESERVED_2: 1;
+        uint32_t RESERVED_1: 1;
+        uint32_t RSVD: 3;
+        uint32_t RESERVED: 1;
+    };
+} PCC_REG_Keyscan_TYPE;
+
+/*0x4000_026c PCC_REG_Keyscan*/
+#define PCC_REG_Keyscan_ENTRY_DELAY_CORE1_DEV_KEYSCAN_Pos                                        0U
+#define PCC_REG_Keyscan_ENTRY_DELAY_CORE1_DEV_KEYSCAN_Msk                                        (0xFFUL << PCC_REG_Keyscan_ENTRY_DELAY_CORE1_DEV_KEYSCAN_Pos)
+
+#define PCC_REG_Keyscan_RESERVED_13_Pos                                                          8U
+#define PCC_REG_Keyscan_RESERVED_13_Msk                                                          (0x1UL << PCC_REG_Keyscan_RESERVED_13_Pos)
+
+#define PCC_REG_Keyscan_RESERVED_12_Pos                                                          9U
+#define PCC_REG_Keyscan_RESERVED_12_Msk                                                          (0x1UL << PCC_REG_Keyscan_RESERVED_12_Pos)
+
+#define PCC_REG_Keyscan_RESERVED_11_Pos                                                          10U
+#define PCC_REG_Keyscan_RESERVED_11_Msk                                                          (0x1UL << PCC_REG_Keyscan_RESERVED_11_Pos)
+
+#define PCC_REG_Keyscan_RESERVED_10_Pos                                                          11U
+#define PCC_REG_Keyscan_RESERVED_10_Msk                                                          (0x1UL << PCC_REG_Keyscan_RESERVED_10_Pos)
+
+#define PCC_REG_Keyscan_RESERVED_9_Pos                                                           12U
+#define PCC_REG_Keyscan_RESERVED_9_Msk                                                           (0x1UL << PCC_REG_Keyscan_RESERVED_9_Pos)
+
+#define PCC_REG_Keyscan_RSVD_2_Pos                                                               13U
+#define PCC_REG_Keyscan_RSVD_2_Msk                                                               (0x7UL << PCC_REG_Keyscan_RSVD_2_Pos)
+
+#define PCC_REG_Keyscan_RESERVED_8_Pos                                                           16U
+#define PCC_REG_Keyscan_RESERVED_8_Msk                                                           (0x1UL << PCC_REG_Keyscan_RESERVED_8_Pos)
+
+#define PCC_REG_Keyscan_RESERVED_7_Pos                                                           17U
+#define PCC_REG_Keyscan_RESERVED_7_Msk                                                           (0x1UL << PCC_REG_Keyscan_RESERVED_7_Pos)
+
+#define PCC_REG_Keyscan_KEYSCAN_CLK_FORCE_Pos                                                    18U
+#define PCC_REG_Keyscan_KEYSCAN_CLK_FORCE_Msk                                                    (0x1UL << PCC_REG_Keyscan_KEYSCAN_CLK_FORCE_Pos)
+
+#define PCC_REG_Keyscan_RSVD_1_Pos                                                               19U
+#define PCC_REG_Keyscan_RSVD_1_Msk                                                               (0x7UL << PCC_REG_Keyscan_RSVD_1_Pos)
+
+#define PCC_REG_Keyscan_RESERVED_6_Pos                                                           22U
+#define PCC_REG_Keyscan_RESERVED_6_Msk                                                           (0x1UL << PCC_REG_Keyscan_RESERVED_6_Pos)
+
+#define PCC_REG_Keyscan_RESERVED_5_Pos                                                           23U
+#define PCC_REG_Keyscan_RESERVED_5_Msk                                                           (0x1UL << PCC_REG_Keyscan_RESERVED_5_Pos)
+
+#define PCC_REG_Keyscan_RESERVED_4_Pos                                                           24U
+#define PCC_REG_Keyscan_RESERVED_4_Msk                                                           (0x1UL << PCC_REG_Keyscan_RESERVED_4_Pos)
+
+#define PCC_REG_Keyscan_RESERVED_3_Pos                                                           25U
+#define PCC_REG_Keyscan_RESERVED_3_Msk                                                           (0x1UL << PCC_REG_Keyscan_RESERVED_3_Pos)
+
+#define PCC_REG_Keyscan_RESERVED_2_Pos                                                           26U
+#define PCC_REG_Keyscan_RESERVED_2_Msk                                                           (0x1UL << PCC_REG_Keyscan_RESERVED_2_Pos)
+
+#define PCC_REG_Keyscan_RESERVED_1_Pos                                                           27U
+#define PCC_REG_Keyscan_RESERVED_1_Msk                                                           (0x1UL << PCC_REG_Keyscan_RESERVED_1_Pos)
+
+#define PCC_REG_Keyscan_RSVD_Pos                                                                 28U
+#define PCC_REG_Keyscan_RSVD_Msk                                                                 (0x7UL << PCC_REG_Keyscan_RSVD_Pos)
+
+#define PCC_REG_Keyscan_RESERVED_Pos                                                             31U
+#define PCC_REG_Keyscan_RESERVED_Msk                                                             (0x1UL << PCC_REG_Keyscan_RESERVED_Pos)
+
+/* 0x270    0x4000_0270
+    7:0     R/W     ENTRY_DELAY_CORE1_DEV_SPI3W                     8'b0
+    8       R/W     RESERVED_13                                     1'b0
+    9       R/W     RESERVED_12                                     1'b1
+    10      R/W     RESERVED_11                                     1'b1
+    11      R/W     RESERVED_10                                     1'b1
+    12      R/W     RESERVED_9                                      1'b1
+    15:13   R/W     RSVD_2                                          3'h0
+    16      R/W     RESERVED_8                                      1'b0
+    17      R/W     RESERVED_7                                      1'b0
+    18      R/W     SPI3W_CLK_FORCE                                 1'b0
+    21:19   R/W     RSVD_1                                          3'b000
+    22      R/W     RESERVED_6                                      1'b0
+    23      R/W     RESERVED_5                                      1'b0
+    24      R/W     RESERVED_4                                      1'b0
+    25      R/W     RESERVED_3                                      1'b0
+    26      R/W     RESERVED_2                                      1'b0
+    27      R/W     RESERVED_1                                      1'b0
+    30:28   R/W     RSVD                                            3'b000
+    31      R/W     RESERVED                                        1'b0
+ */
+typedef union _PCC_REG_SPI3W_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t ENTRY_DELAY_CORE1_DEV_SPI3W: 8;
+        uint32_t RESERVED_13: 1;
+        uint32_t RESERVED_12: 1;
+        uint32_t RESERVED_11: 1;
+        uint32_t RESERVED_10: 1;
+        uint32_t RESERVED_9: 1;
+        uint32_t RSVD_2: 3;
+        uint32_t RESERVED_8: 1;
+        uint32_t RESERVED_7: 1;
+        uint32_t SPI3W_CLK_FORCE: 1;
+        uint32_t RSVD_1: 3;
+        uint32_t RESERVED_6: 1;
+        uint32_t RESERVED_5: 1;
+        uint32_t RESERVED_4: 1;
+        uint32_t RESERVED_3: 1;
+        uint32_t RESERVED_2: 1;
+        uint32_t RESERVED_1: 1;
+        uint32_t RSVD: 3;
+        uint32_t RESERVED: 1;
+    };
+} PCC_REG_SPI3W_TYPE;
+
+/*0x4000_0270 PCC_REG_SPI3W*/
+#define PCC_REG_SPI3W_ENTRY_DELAY_CORE1_DEV_SPI3W_Pos                                            0U
+#define PCC_REG_SPI3W_ENTRY_DELAY_CORE1_DEV_SPI3W_Msk                                            (0xFFUL << PCC_REG_SPI3W_ENTRY_DELAY_CORE1_DEV_SPI3W_Pos)
+
+#define PCC_REG_SPI3W_RESERVED_13_Pos                                                            8U
+#define PCC_REG_SPI3W_RESERVED_13_Msk                                                            (0x1UL << PCC_REG_SPI3W_RESERVED_13_Pos)
+
+#define PCC_REG_SPI3W_RESERVED_12_Pos                                                            9U
+#define PCC_REG_SPI3W_RESERVED_12_Msk                                                            (0x1UL << PCC_REG_SPI3W_RESERVED_12_Pos)
+
+#define PCC_REG_SPI3W_RESERVED_11_Pos                                                            10U
+#define PCC_REG_SPI3W_RESERVED_11_Msk                                                            (0x1UL << PCC_REG_SPI3W_RESERVED_11_Pos)
+
+#define PCC_REG_SPI3W_RESERVED_10_Pos                                                            11U
+#define PCC_REG_SPI3W_RESERVED_10_Msk                                                            (0x1UL << PCC_REG_SPI3W_RESERVED_10_Pos)
+
+#define PCC_REG_SPI3W_RESERVED_9_Pos                                                             12U
+#define PCC_REG_SPI3W_RESERVED_9_Msk                                                             (0x1UL << PCC_REG_SPI3W_RESERVED_9_Pos)
+
+#define PCC_REG_SPI3W_RSVD_2_Pos                                                                 13U
+#define PCC_REG_SPI3W_RSVD_2_Msk                                                                 (0x7UL << PCC_REG_SPI3W_RSVD_2_Pos)
+
+#define PCC_REG_SPI3W_RESERVED_8_Pos                                                             16U
+#define PCC_REG_SPI3W_RESERVED_8_Msk                                                             (0x1UL << PCC_REG_SPI3W_RESERVED_8_Pos)
+
+#define PCC_REG_SPI3W_RESERVED_7_Pos                                                             17U
+#define PCC_REG_SPI3W_RESERVED_7_Msk                                                             (0x1UL << PCC_REG_SPI3W_RESERVED_7_Pos)
+
+#define PCC_REG_SPI3W_SPI3W_CLK_FORCE_Pos                                                        18U
+#define PCC_REG_SPI3W_SPI3W_CLK_FORCE_Msk                                                        (0x1UL << PCC_REG_SPI3W_SPI3W_CLK_FORCE_Pos)
+
+#define PCC_REG_SPI3W_RSVD_1_Pos                                                                 19U
+#define PCC_REG_SPI3W_RSVD_1_Msk                                                                 (0x7UL << PCC_REG_SPI3W_RSVD_1_Pos)
+
+#define PCC_REG_SPI3W_RESERVED_6_Pos                                                             22U
+#define PCC_REG_SPI3W_RESERVED_6_Msk                                                             (0x1UL << PCC_REG_SPI3W_RESERVED_6_Pos)
+
+#define PCC_REG_SPI3W_RESERVED_5_Pos                                                             23U
+#define PCC_REG_SPI3W_RESERVED_5_Msk                                                             (0x1UL << PCC_REG_SPI3W_RESERVED_5_Pos)
+
+#define PCC_REG_SPI3W_RESERVED_4_Pos                                                             24U
+#define PCC_REG_SPI3W_RESERVED_4_Msk                                                             (0x1UL << PCC_REG_SPI3W_RESERVED_4_Pos)
+
+#define PCC_REG_SPI3W_RESERVED_3_Pos                                                             25U
+#define PCC_REG_SPI3W_RESERVED_3_Msk                                                             (0x1UL << PCC_REG_SPI3W_RESERVED_3_Pos)
+
+#define PCC_REG_SPI3W_RESERVED_2_Pos                                                             26U
+#define PCC_REG_SPI3W_RESERVED_2_Msk                                                             (0x1UL << PCC_REG_SPI3W_RESERVED_2_Pos)
+
+#define PCC_REG_SPI3W_RESERVED_1_Pos                                                             27U
+#define PCC_REG_SPI3W_RESERVED_1_Msk                                                             (0x1UL << PCC_REG_SPI3W_RESERVED_1_Pos)
+
+#define PCC_REG_SPI3W_RSVD_Pos                                                                   28U
+#define PCC_REG_SPI3W_RSVD_Msk                                                                   (0x7UL << PCC_REG_SPI3W_RSVD_Pos)
+
+#define PCC_REG_SPI3W_RESERVED_Pos                                                               31U
+#define PCC_REG_SPI3W_RESERVED_Msk                                                               (0x1UL << PCC_REG_SPI3W_RESERVED_Pos)
+
+/* 0x274    0x4000_0274
+    7:0     R/W     ENTRY_DELAY_CORE1_DEV_EFLASH_CTRL               8'b0
+    8       R/W     RESERVED_10                                     1'b0
+    9       R/W     RESERVED_9                                      1'b1
+    10      R/W     RESERVED_8                                      1'b1
+    11      R/W     RESERVED_7                                      1'b0
+    12      R/W     RESERVED_6                                      1'b1
+    15:13   R/W     RSVD_2                                          3'h0
+    16      R/W     RESERVED_5                                      1'b0
+    17      R/W     RESERVED_4                                      1'b0
+    18      R/W     EFLASH_CLK_FORCE                                1'b0
+    21:19   R/W     RSVD_1                                          3'b000
+    22      R/W     RESERVED_3                                      1'b0
+    23      R/W     EFLASH_MANU_SEL                                 1'b0
+    24      R/W     EFLASH_MANU_DAT                                 1'b0
+    25      R/W     RESERVED_2                                      1'b0
+    26      R/W     RESERVED_1                                      1'b0
+    27      R/W     LVCTL                                           1'b0
+    30:28   R/W     RSVD                                            3'b000
+    31      R/W     RESERVED                                        1'b0
+ */
+typedef union _PCC_REG_EFLASH_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t ENTRY_DELAY_CORE1_DEV_EFLASH_CTRL: 8;
+        uint32_t RESERVED_10: 1;
+        uint32_t RESERVED_9: 1;
+        uint32_t RESERVED_8: 1;
+        uint32_t RESERVED_7: 1;
+        uint32_t RESERVED_6: 1;
+        uint32_t RSVD_2: 3;
+        uint32_t RESERVED_5: 1;
+        uint32_t RESERVED_4: 1;
+        uint32_t EFLASH_CLK_FORCE: 1;
+        uint32_t RSVD_1: 3;
+        uint32_t RESERVED_3: 1;
+        uint32_t EFLASH_MANU_SEL: 1;
+        uint32_t EFLASH_MANU_DAT: 1;
+        uint32_t RESERVED_2: 1;
+        uint32_t RESERVED_1: 1;
+        uint32_t LVCTL: 1;
+        uint32_t RSVD: 3;
+        uint32_t RESERVED: 1;
+    };
+} PCC_REG_EFLASH_TYPE;
+
+/*0x4000_0274 PCC_REG_EFLASH*/
+#define PCC_REG_EFLASH_ENTRY_DELAY_CORE1_DEV_EFLASH_CTRL_Pos                                     0U
+#define PCC_REG_EFLASH_ENTRY_DELAY_CORE1_DEV_EFLASH_CTRL_Msk                                     (0xFFUL << PCC_REG_EFLASH_ENTRY_DELAY_CORE1_DEV_EFLASH_CTRL_Pos)
+
+#define PCC_REG_EFLASH_RESERVED_10_Pos                                                           8U
+#define PCC_REG_EFLASH_RESERVED_10_Msk                                                           (0x1UL << PCC_REG_EFLASH_RESERVED_10_Pos)
+
+#define PCC_REG_EFLASH_RESERVED_9_Pos                                                            9U
+#define PCC_REG_EFLASH_RESERVED_9_Msk                                                            (0x1UL << PCC_REG_EFLASH_RESERVED_9_Pos)
+
+#define PCC_REG_EFLASH_RESERVED_8_Pos                                                            10U
+#define PCC_REG_EFLASH_RESERVED_8_Msk                                                            (0x1UL << PCC_REG_EFLASH_RESERVED_8_Pos)
+
+#define PCC_REG_EFLASH_RESERVED_7_Pos                                                            11U
+#define PCC_REG_EFLASH_RESERVED_7_Msk                                                            (0x1UL << PCC_REG_EFLASH_RESERVED_7_Pos)
+
+#define PCC_REG_EFLASH_RESERVED_6_Pos                                                            12U
+#define PCC_REG_EFLASH_RESERVED_6_Msk                                                            (0x1UL << PCC_REG_EFLASH_RESERVED_6_Pos)
+
+#define PCC_REG_EFLASH_RSVD_2_Pos                                                                13U
+#define PCC_REG_EFLASH_RSVD_2_Msk                                                                (0x7UL << PCC_REG_EFLASH_RSVD_2_Pos)
+
+#define PCC_REG_EFLASH_RESERVED_5_Pos                                                            16U
+#define PCC_REG_EFLASH_RESERVED_5_Msk                                                            (0x1UL << PCC_REG_EFLASH_RESERVED_5_Pos)
+
+#define PCC_REG_EFLASH_RESERVED_4_Pos                                                            17U
+#define PCC_REG_EFLASH_RESERVED_4_Msk                                                            (0x1UL << PCC_REG_EFLASH_RESERVED_4_Pos)
+
+#define PCC_REG_EFLASH_EFLASH_CLK_FORCE_Pos                                                      18U
+#define PCC_REG_EFLASH_EFLASH_CLK_FORCE_Msk                                                      (0x1UL << PCC_REG_EFLASH_EFLASH_CLK_FORCE_Pos)
+
+#define PCC_REG_EFLASH_RSVD_1_Pos                                                                19U
+#define PCC_REG_EFLASH_RSVD_1_Msk                                                                (0x7UL << PCC_REG_EFLASH_RSVD_1_Pos)
+
+#define PCC_REG_EFLASH_RESERVED_3_Pos                                                            22U
+#define PCC_REG_EFLASH_RESERVED_3_Msk                                                            (0x1UL << PCC_REG_EFLASH_RESERVED_3_Pos)
+
+#define PCC_REG_EFLASH_EFLASH_MANU_SEL_Pos                                                       23U
+#define PCC_REG_EFLASH_EFLASH_MANU_SEL_Msk                                                       (0x1UL << PCC_REG_EFLASH_EFLASH_MANU_SEL_Pos)
+
+#define PCC_REG_EFLASH_EFLASH_MANU_DAT_Pos                                                       24U
+#define PCC_REG_EFLASH_EFLASH_MANU_DAT_Msk                                                       (0x1UL << PCC_REG_EFLASH_EFLASH_MANU_DAT_Pos)
+
+#define PCC_REG_EFLASH_RESERVED_2_Pos                                                            25U
+#define PCC_REG_EFLASH_RESERVED_2_Msk                                                            (0x1UL << PCC_REG_EFLASH_RESERVED_2_Pos)
+
+#define PCC_REG_EFLASH_RESERVED_1_Pos                                                            26U
+#define PCC_REG_EFLASH_RESERVED_1_Msk                                                            (0x1UL << PCC_REG_EFLASH_RESERVED_1_Pos)
+
+#define PCC_REG_EFLASH_LVCTL_Pos                                                                 27U
+#define PCC_REG_EFLASH_LVCTL_Msk                                                                 (0x1UL << PCC_REG_EFLASH_LVCTL_Pos)
+
+#define PCC_REG_EFLASH_RSVD_Pos                                                                  28U
+#define PCC_REG_EFLASH_RSVD_Msk                                                                  (0x7UL << PCC_REG_EFLASH_RSVD_Pos)
+
+#define PCC_REG_EFLASH_RESERVED_Pos                                                              31U
+#define PCC_REG_EFLASH_RESERVED_Msk                                                              (0x1UL << PCC_REG_EFLASH_RESERVED_Pos)
+
+/* 0x278    0x4000_0278
+    7:0     R/W     ENTRY_DELAY_CORE1_DEV_CAN                       8'b0
+    8       R/W     RESERVED_5                                      1'b0
+    9       R/W     RESERVED_4                                      1'b1
+    10      R/W     RESERVED_3                                      1'b1
+    11      R/W     RESERVED_2                                      1'b1
+    12      R/W     RESERVED_1                                      1'b1
+    14:13   R/W     R_CAN_CLK_DIV                                   2'h0
+    15      R/W     CAN_CLK_FORCE                                   1'b0
+    23:16   R/W     ENTRY_DELAY_CORE1_DEV_CAN_LP                    8'b0
+    24      R/W     CAN_LP_CLK_FORCE                                1'b0
+    26:25   R/W     R_CAN_LP_CLK_DIV                                2'h0
+    31:27   R/W     RESERVED                                        5'b0
+ */
+typedef union _PCC_REG_CAN_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t ENTRY_DELAY_CORE1_DEV_CAN: 8;
+        uint32_t RESERVED_5: 1;
+        uint32_t RESERVED_4: 1;
+        uint32_t RESERVED_3: 1;
+        uint32_t RESERVED_2: 1;
+        uint32_t RESERVED_1: 1;
+        uint32_t R_CAN_CLK_DIV: 2;
+        uint32_t CAN_CLK_FORCE: 1;
+        uint32_t ENTRY_DELAY_CORE1_DEV_CAN_LP: 8;
+        uint32_t CAN_LP_CLK_FORCE: 1;
+        uint32_t R_CAN_LP_CLK_DIV: 2;
+        uint32_t RESERVED: 5;
+    };
+} PCC_REG_CAN_TYPE;
+
+/*0x4000_0278 PCC_REG_CAN*/
+#define PCC_REG_CAN_ENTRY_DELAY_CORE1_DEV_CAN_Pos                                                0U
+#define PCC_REG_CAN_ENTRY_DELAY_CORE1_DEV_CAN_Msk                                                (0xFFUL << PCC_REG_CAN_ENTRY_DELAY_CORE1_DEV_CAN_Pos)
+
+#define PCC_REG_CAN_RESERVED_5_Pos                                                               8U
+#define PCC_REG_CAN_RESERVED_5_Msk                                                               (0x1UL << PCC_REG_CAN_RESERVED_5_Pos)
+
+#define PCC_REG_CAN_RESERVED_4_Pos                                                               9U
+#define PCC_REG_CAN_RESERVED_4_Msk                                                               (0x1UL << PCC_REG_CAN_RESERVED_4_Pos)
+
+#define PCC_REG_CAN_RESERVED_3_Pos                                                               10U
+#define PCC_REG_CAN_RESERVED_3_Msk                                                               (0x1UL << PCC_REG_CAN_RESERVED_3_Pos)
+
+#define PCC_REG_CAN_RESERVED_2_Pos                                                               11U
+#define PCC_REG_CAN_RESERVED_2_Msk                                                               (0x1UL << PCC_REG_CAN_RESERVED_2_Pos)
+
+#define PCC_REG_CAN_RESERVED_1_Pos                                                               12U
+#define PCC_REG_CAN_RESERVED_1_Msk                                                               (0x1UL << PCC_REG_CAN_RESERVED_1_Pos)
+
+#define PCC_REG_CAN_R_CAN_CLK_DIV_Pos                                                            13U
+#define PCC_REG_CAN_R_CAN_CLK_DIV_Msk                                                            (0x3UL << PCC_REG_CAN_R_CAN_CLK_DIV_Pos)
+
+#define PCC_REG_CAN_CAN_CLK_FORCE_Pos                                                            15U
+#define PCC_REG_CAN_CAN_CLK_FORCE_Msk                                                            (0x1UL << PCC_REG_CAN_CAN_CLK_FORCE_Pos)
+
+#define PCC_REG_CAN_ENTRY_DELAY_CORE1_DEV_CAN_LP_Pos                                             16U
+#define PCC_REG_CAN_ENTRY_DELAY_CORE1_DEV_CAN_LP_Msk                                             (0xFFUL << PCC_REG_CAN_ENTRY_DELAY_CORE1_DEV_CAN_LP_Pos)
+
+#define PCC_REG_CAN_CAN_LP_CLK_FORCE_Pos                                                         24U
+#define PCC_REG_CAN_CAN_LP_CLK_FORCE_Msk                                                         (0x1UL << PCC_REG_CAN_CAN_LP_CLK_FORCE_Pos)
+
+#define PCC_REG_CAN_R_CAN_LP_CLK_DIV_Pos                                                         25U
+#define PCC_REG_CAN_R_CAN_LP_CLK_DIV_Msk                                                         (0x3UL << PCC_REG_CAN_R_CAN_LP_CLK_DIV_Pos)
+
+#define PCC_REG_CAN_RESERVED_Pos                                                                 27U
+#define PCC_REG_CAN_RESERVED_Msk                                                                 (0x1FUL << PCC_REG_CAN_RESERVED_Pos)
+
+/* 0x27C    0x4000_027c
+    7:0     R/W     ENTRY_DELAY_CORE1_DEV_GPIO_DBNC                 8'b0
+    8       R/W     RESERVED_7                                      1'b0
+    9       R/W     RESERVED_6                                      1'b1
+    10      R/W     RESERVED_5                                      1'b1
+    11      R/W     RESERVED_4                                      1'b0
+    12      R/W     RESERVED_3                                      1'b1
+    15:13   R/W     RESERVED_2                                      3'b0
+    18:16   R/W     DBNC_DIV_SEL                                    3'h001
+    19      R/W     RSVD_1                                          1'h0
+    20      R/W     GPIO_DBNC_2P4G_CLK_FORCE                        1'b0
+    29:21   R/W     RSVD                                            9'b0
+    30      R/W     RESERVED_1                                      1'b0
+    31      R/W     RESERVED                                        1'b0
+ */
+typedef union _PCC_REG_GPIO_DEBOUNCE_2P4G_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t ENTRY_DELAY_CORE1_DEV_GPIO_DBNC: 8;
+        uint32_t RESERVED_7: 1;
+        uint32_t RESERVED_6: 1;
+        uint32_t RESERVED_5: 1;
+        uint32_t RESERVED_4: 1;
+        uint32_t RESERVED_3: 1;
+        uint32_t RESERVED_2: 3;
+        uint32_t DBNC_DIV_SEL: 3;
+        uint32_t RSVD_1: 1;
+        uint32_t GPIO_DBNC_2P4G_CLK_FORCE: 1;
+        uint32_t RSVD: 9;
+        uint32_t RESERVED_1: 1;
+        uint32_t RESERVED: 1;
+    };
+} PCC_REG_GPIO_DEBOUNCE_2P4G_TYPE;
+
+/*0x4000_027c PCC_REG_GPIO_DEBOUNCE_2P4G*/
+#define PCC_REG_GPIO_DEBOUNCE_2P4G_ENTRY_DELAY_CORE1_DEV_GPIO_DBNC_Pos                           0U
+#define PCC_REG_GPIO_DEBOUNCE_2P4G_ENTRY_DELAY_CORE1_DEV_GPIO_DBNC_Msk                           (0xFFUL << PCC_REG_GPIO_DEBOUNCE_2P4G_ENTRY_DELAY_CORE1_DEV_GPIO_DBNC_Pos)
+
+#define PCC_REG_GPIO_DEBOUNCE_2P4G_RESERVED_7_Pos                                                8U
+#define PCC_REG_GPIO_DEBOUNCE_2P4G_RESERVED_7_Msk                                                (0x1UL << PCC_REG_GPIO_DEBOUNCE_2P4G_RESERVED_7_Pos)
+
+#define PCC_REG_GPIO_DEBOUNCE_2P4G_RESERVED_6_Pos                                                9U
+#define PCC_REG_GPIO_DEBOUNCE_2P4G_RESERVED_6_Msk                                                (0x1UL << PCC_REG_GPIO_DEBOUNCE_2P4G_RESERVED_6_Pos)
+
+#define PCC_REG_GPIO_DEBOUNCE_2P4G_RESERVED_5_Pos                                                10U
+#define PCC_REG_GPIO_DEBOUNCE_2P4G_RESERVED_5_Msk                                                (0x1UL << PCC_REG_GPIO_DEBOUNCE_2P4G_RESERVED_5_Pos)
+
+#define PCC_REG_GPIO_DEBOUNCE_2P4G_RESERVED_4_Pos                                                11U
+#define PCC_REG_GPIO_DEBOUNCE_2P4G_RESERVED_4_Msk                                                (0x1UL << PCC_REG_GPIO_DEBOUNCE_2P4G_RESERVED_4_Pos)
+
+#define PCC_REG_GPIO_DEBOUNCE_2P4G_RESERVED_3_Pos                                                12U
+#define PCC_REG_GPIO_DEBOUNCE_2P4G_RESERVED_3_Msk                                                (0x1UL << PCC_REG_GPIO_DEBOUNCE_2P4G_RESERVED_3_Pos)
+
+#define PCC_REG_GPIO_DEBOUNCE_2P4G_RESERVED_2_Pos                                                13U
+#define PCC_REG_GPIO_DEBOUNCE_2P4G_RESERVED_2_Msk                                                (0x7UL << PCC_REG_GPIO_DEBOUNCE_2P4G_RESERVED_2_Pos)
+
+#define PCC_REG_GPIO_DEBOUNCE_2P4G_DBNC_DIV_SEL_Pos                                              16U
+#define PCC_REG_GPIO_DEBOUNCE_2P4G_DBNC_DIV_SEL_Msk                                              (0x7UL << PCC_REG_GPIO_DEBOUNCE_2P4G_DBNC_DIV_SEL_Pos)
+
+#define PCC_REG_GPIO_DEBOUNCE_2P4G_RSVD_1_Pos                                                    19U
+#define PCC_REG_GPIO_DEBOUNCE_2P4G_RSVD_1_Msk                                                    (0x1UL << PCC_REG_GPIO_DEBOUNCE_2P4G_RSVD_1_Pos)
+
+#define PCC_REG_GPIO_DEBOUNCE_2P4G_GPIO_DBNC_2P4G_CLK_FORCE_Pos                                  20U
+#define PCC_REG_GPIO_DEBOUNCE_2P4G_GPIO_DBNC_2P4G_CLK_FORCE_Msk                                  (0x1UL << PCC_REG_GPIO_DEBOUNCE_2P4G_GPIO_DBNC_2P4G_CLK_FORCE_Pos)
+
+#define PCC_REG_GPIO_DEBOUNCE_2P4G_RSVD_Pos                                                      21U
+#define PCC_REG_GPIO_DEBOUNCE_2P4G_RSVD_Msk                                                      (0x1FFUL << PCC_REG_GPIO_DEBOUNCE_2P4G_RSVD_Pos)
+
+#define PCC_REG_GPIO_DEBOUNCE_2P4G_RESERVED_1_Pos                                                30U
+#define PCC_REG_GPIO_DEBOUNCE_2P4G_RESERVED_1_Msk                                                (0x1UL << PCC_REG_GPIO_DEBOUNCE_2P4G_RESERVED_1_Pos)
+
+#define PCC_REG_GPIO_DEBOUNCE_2P4G_RESERVED_Pos                                                  31U
+#define PCC_REG_GPIO_DEBOUNCE_2P4G_RESERVED_Msk                                                  (0x1UL << PCC_REG_GPIO_DEBOUNCE_2P4G_RESERVED_Pos)
+
+/* 0x280    0x4000_0280
+    7:0     R/W     ENTRY_DELAY_CORE1_DEV_UART0                     8'b0
+    8       R/W     RESERVED_7                                      1'b0
+    9       R/W     RESERVED_6                                      1'b1
+    10      R/W     RESERVED_5                                      1'b1
+    11      R/W     RESERVED_4                                      1'b1
+    12      R/W     RESERVED_3                                      1'b1
+    15:13   R/W     RESERVED_2                                      3'b0
+    18:16   R/W     R_UART0_CLK_DIV_SEL                             3'h0
+    19      R/W     RSVD_2                                          1'h0
+    20      R/W     UART0_CLK_FORCE                                 1'b0
+    25:21   R/W     RSVD_1                                          5'b000
+    26      R/W     RESERVED_1                                      1'b0
+    27      R/W     UART0_PCLK_NO_LATENCY_EN                        1'b0
+    30:28   R/W     RSVD                                            3'b000
+    31      R/W     RESERVED                                        1'b0
+ */
+typedef union _PCC_REG_UART0_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t ENTRY_DELAY_CORE1_DEV_UART0: 8;
+        uint32_t RESERVED_7: 1;
+        uint32_t RESERVED_6: 1;
+        uint32_t RESERVED_5: 1;
+        uint32_t RESERVED_4: 1;
+        uint32_t RESERVED_3: 1;
+        uint32_t RESERVED_2: 3;
+        uint32_t R_UART0_CLK_DIV_SEL: 3;
+        uint32_t RSVD_2: 1;
+        uint32_t UART0_CLK_FORCE: 1;
+        uint32_t RSVD_1: 5;
+        uint32_t RESERVED_1: 1;
+        uint32_t UART0_PCLK_NO_LATENCY_EN: 1;
+        uint32_t RSVD: 3;
+        uint32_t RESERVED: 1;
+    };
+} PCC_REG_UART0_TYPE;
+
+/*0x4000_0280 PCC_REG_UART0*/
+#define PCC_REG_UART0_ENTRY_DELAY_CORE1_DEV_UART0_Pos                                            0U
+#define PCC_REG_UART0_ENTRY_DELAY_CORE1_DEV_UART0_Msk                                            (0xFFUL << PCC_REG_UART0_ENTRY_DELAY_CORE1_DEV_UART0_Pos)
+
+#define PCC_REG_UART0_RESERVED_7_Pos                                                             8U
+#define PCC_REG_UART0_RESERVED_7_Msk                                                             (0x1UL << PCC_REG_UART0_RESERVED_7_Pos)
+
+#define PCC_REG_UART0_RESERVED_6_Pos                                                             9U
+#define PCC_REG_UART0_RESERVED_6_Msk                                                             (0x1UL << PCC_REG_UART0_RESERVED_6_Pos)
+
+#define PCC_REG_UART0_RESERVED_5_Pos                                                             10U
+#define PCC_REG_UART0_RESERVED_5_Msk                                                             (0x1UL << PCC_REG_UART0_RESERVED_5_Pos)
+
+#define PCC_REG_UART0_RESERVED_4_Pos                                                             11U
+#define PCC_REG_UART0_RESERVED_4_Msk                                                             (0x1UL << PCC_REG_UART0_RESERVED_4_Pos)
+
+#define PCC_REG_UART0_RESERVED_3_Pos                                                             12U
+#define PCC_REG_UART0_RESERVED_3_Msk                                                             (0x1UL << PCC_REG_UART0_RESERVED_3_Pos)
+
+#define PCC_REG_UART0_RESERVED_2_Pos                                                             13U
+#define PCC_REG_UART0_RESERVED_2_Msk                                                             (0x7UL << PCC_REG_UART0_RESERVED_2_Pos)
+
+#define PCC_REG_UART0_R_UART0_CLK_DIV_SEL_Pos                                                    16U
+#define PCC_REG_UART0_R_UART0_CLK_DIV_SEL_Msk                                                    (0x7UL << PCC_REG_UART0_R_UART0_CLK_DIV_SEL_Pos)
+
+#define PCC_REG_UART0_RSVD_2_Pos                                                                 19U
+#define PCC_REG_UART0_RSVD_2_Msk                                                                 (0x1UL << PCC_REG_UART0_RSVD_2_Pos)
+
+#define PCC_REG_UART0_UART0_CLK_FORCE_Pos                                                        20U
+#define PCC_REG_UART0_UART0_CLK_FORCE_Msk                                                        (0x1UL << PCC_REG_UART0_UART0_CLK_FORCE_Pos)
+
+#define PCC_REG_UART0_RSVD_1_Pos                                                                 21U
+#define PCC_REG_UART0_RSVD_1_Msk                                                                 (0x1FUL << PCC_REG_UART0_RSVD_1_Pos)
+
+#define PCC_REG_UART0_RESERVED_1_Pos                                                             26U
+#define PCC_REG_UART0_RESERVED_1_Msk                                                             (0x1UL << PCC_REG_UART0_RESERVED_1_Pos)
+
+#define PCC_REG_UART0_UART0_PCLK_NO_LATENCY_EN_Pos                                               27U
+#define PCC_REG_UART0_UART0_PCLK_NO_LATENCY_EN_Msk                                               (0x1UL << PCC_REG_UART0_UART0_PCLK_NO_LATENCY_EN_Pos)
+
+#define PCC_REG_UART0_RSVD_Pos                                                                   28U
+#define PCC_REG_UART0_RSVD_Msk                                                                   (0x7UL << PCC_REG_UART0_RSVD_Pos)
+
+#define PCC_REG_UART0_RESERVED_Pos                                                               31U
+#define PCC_REG_UART0_RESERVED_Msk                                                               (0x1UL << PCC_REG_UART0_RESERVED_Pos)
+
+/* 0x284    0x4000_0284
+    7:0     R/W     ENTRY_DELAY_CORE1_DEV_UART1                     8'b0
+    8       R/W     RESERVED_7                                      1'b0
+    9       R/W     RESERVED_6                                      1'b1
+    10      R/W     RESERVED_5                                      1'b1
+    11      R/W     RESERVED_4                                      1'b1
+    12      R/W     RESERVED_3                                      1'b1
+    15:13   R/W     RESERVED_2                                      3'b0
+    18:16   R/W     R_UART1_CLK_DIV_SEL                             3'h0
+    19      R/W     RSVD_2                                          1'h0
+    20      R/W     UART1_CLK_FORCE                                 1'b0
+    25:21   R/W     RSVD_1                                          5'b000
+    26      R/W     RESERVED_1                                      1'b0
+    27      R/W     UART1_PCLK_NO_LATENCY_EN                        1'b0
+    30:28   R/W     RSVD                                            3'b000
+    31      R/W     RESERVED                                        1'b0
+ */
+typedef union _PCC_REG_UART1_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t ENTRY_DELAY_CORE1_DEV_UART1: 8;
+        uint32_t RESERVED_7: 1;
+        uint32_t RESERVED_6: 1;
+        uint32_t RESERVED_5: 1;
+        uint32_t RESERVED_4: 1;
+        uint32_t RESERVED_3: 1;
+        uint32_t RESERVED_2: 3;
+        uint32_t R_UART1_CLK_DIV_SEL: 3;
+        uint32_t RSVD_2: 1;
+        uint32_t UART1_CLK_FORCE: 1;
+        uint32_t RSVD_1: 5;
+        uint32_t RESERVED_1: 1;
+        uint32_t UART1_PCLK_NO_LATENCY_EN: 1;
+        uint32_t RSVD: 3;
+        uint32_t RESERVED: 1;
+    };
+} PCC_REG_UART1_TYPE;
+
+/*0x4000_0284 PCC_REG_UART1*/
+#define PCC_REG_UART1_ENTRY_DELAY_CORE1_DEV_UART1_Pos                                            0U
+#define PCC_REG_UART1_ENTRY_DELAY_CORE1_DEV_UART1_Msk                                            (0xFFUL << PCC_REG_UART1_ENTRY_DELAY_CORE1_DEV_UART1_Pos)
+
+#define PCC_REG_UART1_RESERVED_7_Pos                                                             8U
+#define PCC_REG_UART1_RESERVED_7_Msk                                                             (0x1UL << PCC_REG_UART1_RESERVED_7_Pos)
+
+#define PCC_REG_UART1_RESERVED_6_Pos                                                             9U
+#define PCC_REG_UART1_RESERVED_6_Msk                                                             (0x1UL << PCC_REG_UART1_RESERVED_6_Pos)
+
+#define PCC_REG_UART1_RESERVED_5_Pos                                                             10U
+#define PCC_REG_UART1_RESERVED_5_Msk                                                             (0x1UL << PCC_REG_UART1_RESERVED_5_Pos)
+
+#define PCC_REG_UART1_RESERVED_4_Pos                                                             11U
+#define PCC_REG_UART1_RESERVED_4_Msk                                                             (0x1UL << PCC_REG_UART1_RESERVED_4_Pos)
+
+#define PCC_REG_UART1_RESERVED_3_Pos                                                             12U
+#define PCC_REG_UART1_RESERVED_3_Msk                                                             (0x1UL << PCC_REG_UART1_RESERVED_3_Pos)
+
+#define PCC_REG_UART1_RESERVED_2_Pos                                                             13U
+#define PCC_REG_UART1_RESERVED_2_Msk                                                             (0x7UL << PCC_REG_UART1_RESERVED_2_Pos)
+
+#define PCC_REG_UART1_R_UART1_CLK_DIV_SEL_Pos                                                    16U
+#define PCC_REG_UART1_R_UART1_CLK_DIV_SEL_Msk                                                    (0x7UL << PCC_REG_UART1_R_UART1_CLK_DIV_SEL_Pos)
+
+#define PCC_REG_UART1_RSVD_2_Pos                                                                 19U
+#define PCC_REG_UART1_RSVD_2_Msk                                                                 (0x1UL << PCC_REG_UART1_RSVD_2_Pos)
+
+#define PCC_REG_UART1_UART1_CLK_FORCE_Pos                                                        20U
+#define PCC_REG_UART1_UART1_CLK_FORCE_Msk                                                        (0x1UL << PCC_REG_UART1_UART1_CLK_FORCE_Pos)
+
+#define PCC_REG_UART1_RSVD_1_Pos                                                                 21U
+#define PCC_REG_UART1_RSVD_1_Msk                                                                 (0x1FUL << PCC_REG_UART1_RSVD_1_Pos)
+
+#define PCC_REG_UART1_RESERVED_1_Pos                                                             26U
+#define PCC_REG_UART1_RESERVED_1_Msk                                                             (0x1UL << PCC_REG_UART1_RESERVED_1_Pos)
+
+#define PCC_REG_UART1_UART1_PCLK_NO_LATENCY_EN_Pos                                               27U
+#define PCC_REG_UART1_UART1_PCLK_NO_LATENCY_EN_Msk                                               (0x1UL << PCC_REG_UART1_UART1_PCLK_NO_LATENCY_EN_Pos)
+
+#define PCC_REG_UART1_RSVD_Pos                                                                   28U
+#define PCC_REG_UART1_RSVD_Msk                                                                   (0x7UL << PCC_REG_UART1_RSVD_Pos)
+
+#define PCC_REG_UART1_RESERVED_Pos                                                               31U
+#define PCC_REG_UART1_RESERVED_Msk                                                               (0x1UL << PCC_REG_UART1_RESERVED_Pos)
+
+/* 0x288    0x4000_0288
+    7:0     R/W     ENTRY_DELAY_CORE1_DEV_UART2                     8'b0
+    8       R/W     RESERVED_7                                      1'b0
+    9       R/W     RESERVED_6                                      1'b1
+    10      R/W     RESERVED_5                                      1'b1
+    11      R/W     RESERVED_4                                      1'b1
+    12      R/W     RESERVED_3                                      1'b1
+    15:13   R/W     RESERVED_2                                      3'b0
+    18:16   R/W     R_UART2_CLK_DIV_SEL                             3'h0
+    19      R/W     RSVD_2                                          1'h0
+    20      R/W     UART2_CLK_FORCE                                 1'b0
+    25:21   R/W     RSVD_1                                          5'b000
+    26      R/W     RESERVED_1                                      1'b0
+    27      R/W     UART2_PCLK_NO_LATENCY_EN                        1'b0
+    30:28   R/W     RSVD                                            3'b000
+    31      R/W     RESERVED                                        1'b0
+ */
+typedef union _PCC_REG_UART2_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t ENTRY_DELAY_CORE1_DEV_UART2: 8;
+        uint32_t RESERVED_7: 1;
+        uint32_t RESERVED_6: 1;
+        uint32_t RESERVED_5: 1;
+        uint32_t RESERVED_4: 1;
+        uint32_t RESERVED_3: 1;
+        uint32_t RESERVED_2: 3;
+        uint32_t R_UART2_CLK_DIV_SEL: 3;
+        uint32_t RSVD_2: 1;
+        uint32_t UART2_CLK_FORCE: 1;
+        uint32_t RSVD_1: 5;
+        uint32_t RESERVED_1: 1;
+        uint32_t UART2_PCLK_NO_LATENCY_EN: 1;
+        uint32_t RSVD: 3;
+        uint32_t RESERVED: 1;
+    };
+} PCC_REG_UART2_TYPE;
+
+/*0x4000_0288 PCC_REG_UART2*/
+#define PCC_REG_UART2_ENTRY_DELAY_CORE1_DEV_UART2_Pos                                            0U
+#define PCC_REG_UART2_ENTRY_DELAY_CORE1_DEV_UART2_Msk                                            (0xFFUL << PCC_REG_UART2_ENTRY_DELAY_CORE1_DEV_UART2_Pos)
+
+#define PCC_REG_UART2_RESERVED_7_Pos                                                             8U
+#define PCC_REG_UART2_RESERVED_7_Msk                                                             (0x1UL << PCC_REG_UART2_RESERVED_7_Pos)
+
+#define PCC_REG_UART2_RESERVED_6_Pos                                                             9U
+#define PCC_REG_UART2_RESERVED_6_Msk                                                             (0x1UL << PCC_REG_UART2_RESERVED_6_Pos)
+
+#define PCC_REG_UART2_RESERVED_5_Pos                                                             10U
+#define PCC_REG_UART2_RESERVED_5_Msk                                                             (0x1UL << PCC_REG_UART2_RESERVED_5_Pos)
+
+#define PCC_REG_UART2_RESERVED_4_Pos                                                             11U
+#define PCC_REG_UART2_RESERVED_4_Msk                                                             (0x1UL << PCC_REG_UART2_RESERVED_4_Pos)
+
+#define PCC_REG_UART2_RESERVED_3_Pos                                                             12U
+#define PCC_REG_UART2_RESERVED_3_Msk                                                             (0x1UL << PCC_REG_UART2_RESERVED_3_Pos)
+
+#define PCC_REG_UART2_RESERVED_2_Pos                                                             13U
+#define PCC_REG_UART2_RESERVED_2_Msk                                                             (0x7UL << PCC_REG_UART2_RESERVED_2_Pos)
+
+#define PCC_REG_UART2_R_UART2_CLK_DIV_SEL_Pos                                                    16U
+#define PCC_REG_UART2_R_UART2_CLK_DIV_SEL_Msk                                                    (0x7UL << PCC_REG_UART2_R_UART2_CLK_DIV_SEL_Pos)
+
+#define PCC_REG_UART2_RSVD_2_Pos                                                                 19U
+#define PCC_REG_UART2_RSVD_2_Msk                                                                 (0x1UL << PCC_REG_UART2_RSVD_2_Pos)
+
+#define PCC_REG_UART2_UART2_CLK_FORCE_Pos                                                        20U
+#define PCC_REG_UART2_UART2_CLK_FORCE_Msk                                                        (0x1UL << PCC_REG_UART2_UART2_CLK_FORCE_Pos)
+
+#define PCC_REG_UART2_RSVD_1_Pos                                                                 21U
+#define PCC_REG_UART2_RSVD_1_Msk                                                                 (0x1FUL << PCC_REG_UART2_RSVD_1_Pos)
+
+#define PCC_REG_UART2_RESERVED_1_Pos                                                             26U
+#define PCC_REG_UART2_RESERVED_1_Msk                                                             (0x1UL << PCC_REG_UART2_RESERVED_1_Pos)
+
+#define PCC_REG_UART2_UART2_PCLK_NO_LATENCY_EN_Pos                                               27U
+#define PCC_REG_UART2_UART2_PCLK_NO_LATENCY_EN_Msk                                               (0x1UL << PCC_REG_UART2_UART2_PCLK_NO_LATENCY_EN_Pos)
+
+#define PCC_REG_UART2_RSVD_Pos                                                                   28U
+#define PCC_REG_UART2_RSVD_Msk                                                                   (0x7UL << PCC_REG_UART2_RSVD_Pos)
+
+#define PCC_REG_UART2_RESERVED_Pos                                                               31U
+#define PCC_REG_UART2_RESERVED_Msk                                                               (0x1UL << PCC_REG_UART2_RESERVED_Pos)
+
+/* 0x28C    0x4000_028c
+    7:0     R/W     ENTRY_DELAY_CORE1_DEV_UART3                     8'b0
+    8       R/W     RESERVED_7                                      1'b0
+    9       R/W     RESERVED_6                                      1'b1
+    10      R/W     RESERVED_5                                      1'b1
+    11      R/W     RESERVED_4                                      1'b1
+    12      R/W     RESERVED_3                                      1'b1
+    15:13   R/W     RESERVED_2                                      3'b0
+    18:16   R/W     R_UART3_CLK_DIV_SEL                             3'h0
+    19      R/W     RSVD_2                                          1'h0
+    20      R/W     UART3_CLK_FORCE                                 1'b0
+    25:21   R/W     RSVD_1                                          5'b000
+    26      R/W     RESERVED_1                                      1'b0
+    27      R/W     UART3_PCLK_NO_LATENCY_EN                        1'b0
+    30:28   R/W     RSVD                                            3'b000
+    31      R/W     RESERVED                                        1'b0
+ */
+typedef union _PCC_REG_UART3_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t ENTRY_DELAY_CORE1_DEV_UART3: 8;
+        uint32_t RESERVED_7: 1;
+        uint32_t RESERVED_6: 1;
+        uint32_t RESERVED_5: 1;
+        uint32_t RESERVED_4: 1;
+        uint32_t RESERVED_3: 1;
+        uint32_t RESERVED_2: 3;
+        uint32_t R_UART3_CLK_DIV_SEL: 3;
+        uint32_t RSVD_2: 1;
+        uint32_t UART3_CLK_FORCE: 1;
+        uint32_t RSVD_1: 5;
+        uint32_t RESERVED_1: 1;
+        uint32_t UART3_PCLK_NO_LATENCY_EN: 1;
+        uint32_t RSVD: 3;
+        uint32_t RESERVED: 1;
+    };
+} PCC_REG_UART3_TYPE;
+
+/*0x4000_028c PCC_REG_UART3*/
+#define PCC_REG_UART3_ENTRY_DELAY_CORE1_DEV_UART3_Pos                                            0U
+#define PCC_REG_UART3_ENTRY_DELAY_CORE1_DEV_UART3_Msk                                            (0xFFUL << PCC_REG_UART3_ENTRY_DELAY_CORE1_DEV_UART3_Pos)
+
+#define PCC_REG_UART3_RESERVED_7_Pos                                                             8U
+#define PCC_REG_UART3_RESERVED_7_Msk                                                             (0x1UL << PCC_REG_UART3_RESERVED_7_Pos)
+
+#define PCC_REG_UART3_RESERVED_6_Pos                                                             9U
+#define PCC_REG_UART3_RESERVED_6_Msk                                                             (0x1UL << PCC_REG_UART3_RESERVED_6_Pos)
+
+#define PCC_REG_UART3_RESERVED_5_Pos                                                             10U
+#define PCC_REG_UART3_RESERVED_5_Msk                                                             (0x1UL << PCC_REG_UART3_RESERVED_5_Pos)
+
+#define PCC_REG_UART3_RESERVED_4_Pos                                                             11U
+#define PCC_REG_UART3_RESERVED_4_Msk                                                             (0x1UL << PCC_REG_UART3_RESERVED_4_Pos)
+
+#define PCC_REG_UART3_RESERVED_3_Pos                                                             12U
+#define PCC_REG_UART3_RESERVED_3_Msk                                                             (0x1UL << PCC_REG_UART3_RESERVED_3_Pos)
+
+#define PCC_REG_UART3_RESERVED_2_Pos                                                             13U
+#define PCC_REG_UART3_RESERVED_2_Msk                                                             (0x7UL << PCC_REG_UART3_RESERVED_2_Pos)
+
+#define PCC_REG_UART3_R_UART3_CLK_DIV_SEL_Pos                                                    16U
+#define PCC_REG_UART3_R_UART3_CLK_DIV_SEL_Msk                                                    (0x7UL << PCC_REG_UART3_R_UART3_CLK_DIV_SEL_Pos)
+
+#define PCC_REG_UART3_RSVD_2_Pos                                                                 19U
+#define PCC_REG_UART3_RSVD_2_Msk                                                                 (0x1UL << PCC_REG_UART3_RSVD_2_Pos)
+
+#define PCC_REG_UART3_UART3_CLK_FORCE_Pos                                                        20U
+#define PCC_REG_UART3_UART3_CLK_FORCE_Msk                                                        (0x1UL << PCC_REG_UART3_UART3_CLK_FORCE_Pos)
+
+#define PCC_REG_UART3_RSVD_1_Pos                                                                 21U
+#define PCC_REG_UART3_RSVD_1_Msk                                                                 (0x1FUL << PCC_REG_UART3_RSVD_1_Pos)
+
+#define PCC_REG_UART3_RESERVED_1_Pos                                                             26U
+#define PCC_REG_UART3_RESERVED_1_Msk                                                             (0x1UL << PCC_REG_UART3_RESERVED_1_Pos)
+
+#define PCC_REG_UART3_UART3_PCLK_NO_LATENCY_EN_Pos                                               27U
+#define PCC_REG_UART3_UART3_PCLK_NO_LATENCY_EN_Msk                                               (0x1UL << PCC_REG_UART3_UART3_PCLK_NO_LATENCY_EN_Pos)
+
+#define PCC_REG_UART3_RSVD_Pos                                                                   28U
+#define PCC_REG_UART3_RSVD_Msk                                                                   (0x7UL << PCC_REG_UART3_RSVD_Pos)
+
+#define PCC_REG_UART3_RESERVED_Pos                                                               31U
+#define PCC_REG_UART3_RESERVED_Msk                                                               (0x1UL << PCC_REG_UART3_RESERVED_Pos)
+
+/* 0x290    0x4000_0290
+    7:0     R/W     ENTRY_DELAY_CORE1_DEV_RTKGPIO                   8'b0
+    8       R/W     RESERVED_11                                     1'b0
+    9       R/W     RESERVED_10                                     1'b1
+    10      R/W     RESERVED_9                                      1'b0
+    11      R/W     RESERVED_8                                      1'b1
+    12      R/W     RESERVED_7                                      1'b1
+    13      R/W     RESERVED_6                                      1'b1
+    14      R/W     RESERVED_5                                      1'b1
+    15      R/W     RESERVED_4                                      1'b0
+    16      R/W     RESERVED_3                                      1'b0
+    17      R/W     RESERVED_2                                      1'b0
+    18      R/W     GPIOA_CLK_FORCE                                 1'b0
+    29:19   R/W     RSVD                                            11'b0
+    30      R/W     RESERVED_1                                      1'b0
+    31      R/W     RESERVED                                        1'b0
+ */
+typedef union _PCC_REG_GPIOA_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t ENTRY_DELAY_CORE1_DEV_RTKGPIO: 8;
+        uint32_t RESERVED_11: 1;
+        uint32_t RESERVED_10: 1;
+        uint32_t RESERVED_9: 1;
+        uint32_t RESERVED_8: 1;
+        uint32_t RESERVED_7: 1;
+        uint32_t RESERVED_6: 1;
+        uint32_t RESERVED_5: 1;
+        uint32_t RESERVED_4: 1;
+        uint32_t RESERVED_3: 1;
+        uint32_t RESERVED_2: 1;
+        uint32_t GPIOA_CLK_FORCE: 1;
+        uint32_t RSVD: 11;
+        uint32_t RESERVED_1: 1;
+        uint32_t RESERVED: 1;
+    };
+} PCC_REG_GPIOA_TYPE;
+
+/*0x4000_0290 PCC_REG_GPIOA*/
+#define PCC_REG_GPIOA_ENTRY_DELAY_CORE1_DEV_RTKGPIO_Pos                                          0U
+#define PCC_REG_GPIOA_ENTRY_DELAY_CORE1_DEV_RTKGPIO_Msk                                          (0xFFUL << PCC_REG_GPIOA_ENTRY_DELAY_CORE1_DEV_RTKGPIO_Pos)
+
+#define PCC_REG_GPIOA_RESERVED_11_Pos                                                            8U
+#define PCC_REG_GPIOA_RESERVED_11_Msk                                                            (0x1UL << PCC_REG_GPIOA_RESERVED_11_Pos)
+
+#define PCC_REG_GPIOA_RESERVED_10_Pos                                                            9U
+#define PCC_REG_GPIOA_RESERVED_10_Msk                                                            (0x1UL << PCC_REG_GPIOA_RESERVED_10_Pos)
+
+#define PCC_REG_GPIOA_RESERVED_9_Pos                                                             10U
+#define PCC_REG_GPIOA_RESERVED_9_Msk                                                             (0x1UL << PCC_REG_GPIOA_RESERVED_9_Pos)
+
+#define PCC_REG_GPIOA_RESERVED_8_Pos                                                             11U
+#define PCC_REG_GPIOA_RESERVED_8_Msk                                                             (0x1UL << PCC_REG_GPIOA_RESERVED_8_Pos)
+
+#define PCC_REG_GPIOA_RESERVED_7_Pos                                                             12U
+#define PCC_REG_GPIOA_RESERVED_7_Msk                                                             (0x1UL << PCC_REG_GPIOA_RESERVED_7_Pos)
+
+#define PCC_REG_GPIOA_RESERVED_6_Pos                                                             13U
+#define PCC_REG_GPIOA_RESERVED_6_Msk                                                             (0x1UL << PCC_REG_GPIOA_RESERVED_6_Pos)
+
+#define PCC_REG_GPIOA_RESERVED_5_Pos                                                             14U
+#define PCC_REG_GPIOA_RESERVED_5_Msk                                                             (0x1UL << PCC_REG_GPIOA_RESERVED_5_Pos)
+
+#define PCC_REG_GPIOA_RESERVED_4_Pos                                                             15U
+#define PCC_REG_GPIOA_RESERVED_4_Msk                                                             (0x1UL << PCC_REG_GPIOA_RESERVED_4_Pos)
+
+#define PCC_REG_GPIOA_RESERVED_3_Pos                                                             16U
+#define PCC_REG_GPIOA_RESERVED_3_Msk                                                             (0x1UL << PCC_REG_GPIOA_RESERVED_3_Pos)
+
+#define PCC_REG_GPIOA_RESERVED_2_Pos                                                             17U
+#define PCC_REG_GPIOA_RESERVED_2_Msk                                                             (0x1UL << PCC_REG_GPIOA_RESERVED_2_Pos)
+
+#define PCC_REG_GPIOA_GPIOA_CLK_FORCE_Pos                                                        18U
+#define PCC_REG_GPIOA_GPIOA_CLK_FORCE_Msk                                                        (0x1UL << PCC_REG_GPIOA_GPIOA_CLK_FORCE_Pos)
+
+#define PCC_REG_GPIOA_RSVD_Pos                                                                   19U
+#define PCC_REG_GPIOA_RSVD_Msk                                                                   (0x7FFUL << PCC_REG_GPIOA_RSVD_Pos)
+
+#define PCC_REG_GPIOA_RESERVED_1_Pos                                                             30U
+#define PCC_REG_GPIOA_RESERVED_1_Msk                                                             (0x1UL << PCC_REG_GPIOA_RESERVED_1_Pos)
+
+#define PCC_REG_GPIOA_RESERVED_Pos                                                               31U
+#define PCC_REG_GPIOA_RESERVED_Msk                                                               (0x1UL << PCC_REG_GPIOA_RESERVED_Pos)
+
+/* 0x294    0x4000_0294
+    7:0     R/W     ENTRY_DELAY_CORE1_DEV_MODEM                     8'b0
+    8       R/W     RESERVED_7                                      1'b1
+    9       R/W     RESERVED_6                                      1'b1
+    10      R/W     RESERVED_5                                      1'b1
+    11      R/W     RESERVED_4                                      1'b1
+    12      R/W     RESERVED_3                                      1'b1
+    14:13   R/W     RESERVED_2                                      2'b0
+    15      R/W     R_MODEM_CLK_SEL_CK1_FORCE                       1'b0
+    16      R/W     R_MODEM_CLK_SRC_SEL                             1'b1
+    17      R/W     RSVD_4                                          1'h0
+    18      R/W     MODEM_CLK_FORCE                                 1'b0
+    21:19   R/W     RSVD_3                                          3'b000
+    22      R/W     RESERVED_1                                      1'b0
+    23      R/W     RSVD_2                                          1'b0
+    24      R/W     RSVD_1                                          1'b0
+    30:25   R/W     RSVD                                            6'b0
+    31      R/W     RESERVED                                        1'b0
+ */
+typedef union _PCC_REG_MODEM_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t ENTRY_DELAY_CORE1_DEV_MODEM: 8;
+        uint32_t RESERVED_7: 1;
+        uint32_t RESERVED_6: 1;
+        uint32_t RESERVED_5: 1;
+        uint32_t RESERVED_4: 1;
+        uint32_t RESERVED_3: 1;
+        uint32_t RESERVED_2: 2;
+        uint32_t R_MODEM_CLK_SEL_CK1_FORCE: 1;
+        uint32_t R_MODEM_CLK_SRC_SEL: 1;
+        uint32_t RSVD_4: 1;
+        uint32_t MODEM_CLK_FORCE: 1;
+        uint32_t RSVD_3: 3;
+        uint32_t RESERVED_1: 1;
+        uint32_t RSVD_2: 1;
+        uint32_t RSVD_1: 1;
+        uint32_t RSVD: 6;
+        uint32_t RESERVED: 1;
+    };
+} PCC_REG_MODEM_TYPE;
+
+/*0x4000_0294 PCC_REG_MODEM*/
+#define PCC_REG_MODEM_ENTRY_DELAY_CORE1_DEV_MODEM_Pos                                            0U
+#define PCC_REG_MODEM_ENTRY_DELAY_CORE1_DEV_MODEM_Msk                                            (0xFFUL << PCC_REG_MODEM_ENTRY_DELAY_CORE1_DEV_MODEM_Pos)
+
+#define PCC_REG_MODEM_RESERVED_7_Pos                                                             8U
+#define PCC_REG_MODEM_RESERVED_7_Msk                                                             (0x1UL << PCC_REG_MODEM_RESERVED_7_Pos)
+
+#define PCC_REG_MODEM_RESERVED_6_Pos                                                             9U
+#define PCC_REG_MODEM_RESERVED_6_Msk                                                             (0x1UL << PCC_REG_MODEM_RESERVED_6_Pos)
+
+#define PCC_REG_MODEM_RESERVED_5_Pos                                                             10U
+#define PCC_REG_MODEM_RESERVED_5_Msk                                                             (0x1UL << PCC_REG_MODEM_RESERVED_5_Pos)
+
+#define PCC_REG_MODEM_RESERVED_4_Pos                                                             11U
+#define PCC_REG_MODEM_RESERVED_4_Msk                                                             (0x1UL << PCC_REG_MODEM_RESERVED_4_Pos)
+
+#define PCC_REG_MODEM_RESERVED_3_Pos                                                             12U
+#define PCC_REG_MODEM_RESERVED_3_Msk                                                             (0x1UL << PCC_REG_MODEM_RESERVED_3_Pos)
+
+#define PCC_REG_MODEM_RESERVED_2_Pos                                                             13U
+#define PCC_REG_MODEM_RESERVED_2_Msk                                                             (0x3UL << PCC_REG_MODEM_RESERVED_2_Pos)
+
+#define PCC_REG_MODEM_R_MODEM_CLK_SEL_CK1_FORCE_Pos                                              15U
+#define PCC_REG_MODEM_R_MODEM_CLK_SEL_CK1_FORCE_Msk                                              (0x1UL << PCC_REG_MODEM_R_MODEM_CLK_SEL_CK1_FORCE_Pos)
+
+#define PCC_REG_MODEM_R_MODEM_CLK_SRC_SEL_Pos                                                    16U
+#define PCC_REG_MODEM_R_MODEM_CLK_SRC_SEL_Msk                                                    (0x1UL << PCC_REG_MODEM_R_MODEM_CLK_SRC_SEL_Pos)
+
+#define PCC_REG_MODEM_RSVD_4_Pos                                                                 17U
+#define PCC_REG_MODEM_RSVD_4_Msk                                                                 (0x1UL << PCC_REG_MODEM_RSVD_4_Pos)
+
+#define PCC_REG_MODEM_MODEM_CLK_FORCE_Pos                                                        18U
+#define PCC_REG_MODEM_MODEM_CLK_FORCE_Msk                                                        (0x1UL << PCC_REG_MODEM_MODEM_CLK_FORCE_Pos)
+
+#define PCC_REG_MODEM_RSVD_3_Pos                                                                 19U
+#define PCC_REG_MODEM_RSVD_3_Msk                                                                 (0x7UL << PCC_REG_MODEM_RSVD_3_Pos)
+
+#define PCC_REG_MODEM_RESERVED_1_Pos                                                             22U
+#define PCC_REG_MODEM_RESERVED_1_Msk                                                             (0x1UL << PCC_REG_MODEM_RESERVED_1_Pos)
+
+#define PCC_REG_MODEM_RSVD_2_Pos                                                                 23U
+#define PCC_REG_MODEM_RSVD_2_Msk                                                                 (0x1UL << PCC_REG_MODEM_RSVD_2_Pos)
+
+#define PCC_REG_MODEM_RSVD_1_Pos                                                                 24U
+#define PCC_REG_MODEM_RSVD_1_Msk                                                                 (0x1UL << PCC_REG_MODEM_RSVD_1_Pos)
+
+#define PCC_REG_MODEM_RSVD_Pos                                                                   25U
+#define PCC_REG_MODEM_RSVD_Msk                                                                   (0x3FUL << PCC_REG_MODEM_RSVD_Pos)
+
+#define PCC_REG_MODEM_RESERVED_Pos                                                               31U
+#define PCC_REG_MODEM_RESERVED_Msk                                                               (0x1UL << PCC_REG_MODEM_RESERVED_Pos)
+
+/* 0x298    0x4000_0298
+    7:0     R/W     RESERVED_16                                     8'b0
+    8       R/W     RESERVED_15                                     1'b0
+    9       R/W     RESERVED_14                                     1'b1
+    10      R/W     RESERVED_13                                     1'b1
+    11      R/W     RESERVED_12                                     1'b1
+    12      R/W     RESERVED_11                                     1'b1
+    13      R/W     RESERVED_10                                     1'b0
+    14      R/W     RESERVED_9                                      1'b0
+    15      R/W     RSVD_2                                          1'h0
+    16      R/W     RESERVED_8                                      1'b0
+    17      R/W     RESERVED_7                                      1'b0
+    18      R/W     PRO24G_CLK_FORCE                                1'b0
+    21:19   R/W     RSVD_1                                          3'b000
+    22      R/W     RESERVED_6                                      1'b0
+    23      R/W     RESERVED_5                                      1'b0
+    24      R/W     RESERVED_4                                      1'b0
+    25      R/W     RESERVED_3                                      1'b0
+    26      R/W     RESERVED_2                                      1'b0
+    27      R/W     RESERVED_1                                      1'b0
+    30:28   R/W     RSVD                                            3'b000
+    31      R/W     RESERVED                                        1'b0
+ */
+typedef union _PCC_REG_PROPRIETARY_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED_16: 8;
+        uint32_t RESERVED_15: 1;
+        uint32_t RESERVED_14: 1;
+        uint32_t RESERVED_13: 1;
+        uint32_t RESERVED_12: 1;
+        uint32_t RESERVED_11: 1;
+        uint32_t RESERVED_10: 1;
+        uint32_t RESERVED_9: 1;
+        uint32_t RSVD_2: 1;
+        uint32_t RESERVED_8: 1;
+        uint32_t RESERVED_7: 1;
+        uint32_t PRO24G_CLK_FORCE: 1;
+        uint32_t RSVD_1: 3;
+        uint32_t RESERVED_6: 1;
+        uint32_t RESERVED_5: 1;
+        uint32_t RESERVED_4: 1;
+        uint32_t RESERVED_3: 1;
+        uint32_t RESERVED_2: 1;
+        uint32_t RESERVED_1: 1;
+        uint32_t RSVD: 3;
+        uint32_t RESERVED: 1;
+    };
+} PCC_REG_PROPRIETARY_TYPE;
+
+/*0x4000_0298 PCC_REG_PROPRIETARY*/
+#define PCC_REG_PROPRIETARY_RESERVED_16_Pos                                                      0U
+#define PCC_REG_PROPRIETARY_RESERVED_16_Msk                                                      (0xFFUL << PCC_REG_PROPRIETARY_RESERVED_16_Pos)
+
+#define PCC_REG_PROPRIETARY_RESERVED_15_Pos                                                      8U
+#define PCC_REG_PROPRIETARY_RESERVED_15_Msk                                                      (0x1UL << PCC_REG_PROPRIETARY_RESERVED_15_Pos)
+
+#define PCC_REG_PROPRIETARY_RESERVED_14_Pos                                                      9U
+#define PCC_REG_PROPRIETARY_RESERVED_14_Msk                                                      (0x1UL << PCC_REG_PROPRIETARY_RESERVED_14_Pos)
+
+#define PCC_REG_PROPRIETARY_RESERVED_13_Pos                                                      10U
+#define PCC_REG_PROPRIETARY_RESERVED_13_Msk                                                      (0x1UL << PCC_REG_PROPRIETARY_RESERVED_13_Pos)
+
+#define PCC_REG_PROPRIETARY_RESERVED_12_Pos                                                      11U
+#define PCC_REG_PROPRIETARY_RESERVED_12_Msk                                                      (0x1UL << PCC_REG_PROPRIETARY_RESERVED_12_Pos)
+
+#define PCC_REG_PROPRIETARY_RESERVED_11_Pos                                                      12U
+#define PCC_REG_PROPRIETARY_RESERVED_11_Msk                                                      (0x1UL << PCC_REG_PROPRIETARY_RESERVED_11_Pos)
+
+#define PCC_REG_PROPRIETARY_RESERVED_10_Pos                                                      13U
+#define PCC_REG_PROPRIETARY_RESERVED_10_Msk                                                      (0x1UL << PCC_REG_PROPRIETARY_RESERVED_10_Pos)
+
+#define PCC_REG_PROPRIETARY_RESERVED_9_Pos                                                       14U
+#define PCC_REG_PROPRIETARY_RESERVED_9_Msk                                                       (0x1UL << PCC_REG_PROPRIETARY_RESERVED_9_Pos)
+
+#define PCC_REG_PROPRIETARY_RSVD_2_Pos                                                           15U
+#define PCC_REG_PROPRIETARY_RSVD_2_Msk                                                           (0x1UL << PCC_REG_PROPRIETARY_RSVD_2_Pos)
+
+#define PCC_REG_PROPRIETARY_RESERVED_8_Pos                                                       16U
+#define PCC_REG_PROPRIETARY_RESERVED_8_Msk                                                       (0x1UL << PCC_REG_PROPRIETARY_RESERVED_8_Pos)
+
+#define PCC_REG_PROPRIETARY_RESERVED_7_Pos                                                       17U
+#define PCC_REG_PROPRIETARY_RESERVED_7_Msk                                                       (0x1UL << PCC_REG_PROPRIETARY_RESERVED_7_Pos)
+
+#define PCC_REG_PROPRIETARY_PRO24G_CLK_FORCE_Pos                                                 18U
+#define PCC_REG_PROPRIETARY_PRO24G_CLK_FORCE_Msk                                                 (0x1UL << PCC_REG_PROPRIETARY_PRO24G_CLK_FORCE_Pos)
+
+#define PCC_REG_PROPRIETARY_RSVD_1_Pos                                                           19U
+#define PCC_REG_PROPRIETARY_RSVD_1_Msk                                                           (0x7UL << PCC_REG_PROPRIETARY_RSVD_1_Pos)
+
+#define PCC_REG_PROPRIETARY_RESERVED_6_Pos                                                       22U
+#define PCC_REG_PROPRIETARY_RESERVED_6_Msk                                                       (0x1UL << PCC_REG_PROPRIETARY_RESERVED_6_Pos)
+
+#define PCC_REG_PROPRIETARY_RESERVED_5_Pos                                                       23U
+#define PCC_REG_PROPRIETARY_RESERVED_5_Msk                                                       (0x1UL << PCC_REG_PROPRIETARY_RESERVED_5_Pos)
+
+#define PCC_REG_PROPRIETARY_RESERVED_4_Pos                                                       24U
+#define PCC_REG_PROPRIETARY_RESERVED_4_Msk                                                       (0x1UL << PCC_REG_PROPRIETARY_RESERVED_4_Pos)
+
+#define PCC_REG_PROPRIETARY_RESERVED_3_Pos                                                       25U
+#define PCC_REG_PROPRIETARY_RESERVED_3_Msk                                                       (0x1UL << PCC_REG_PROPRIETARY_RESERVED_3_Pos)
+
+#define PCC_REG_PROPRIETARY_RESERVED_2_Pos                                                       26U
+#define PCC_REG_PROPRIETARY_RESERVED_2_Msk                                                       (0x1UL << PCC_REG_PROPRIETARY_RESERVED_2_Pos)
+
+#define PCC_REG_PROPRIETARY_RESERVED_1_Pos                                                       27U
+#define PCC_REG_PROPRIETARY_RESERVED_1_Msk                                                       (0x1UL << PCC_REG_PROPRIETARY_RESERVED_1_Pos)
+
+#define PCC_REG_PROPRIETARY_RSVD_Pos                                                             28U
+#define PCC_REG_PROPRIETARY_RSVD_Msk                                                             (0x7UL << PCC_REG_PROPRIETARY_RSVD_Pos)
+
+#define PCC_REG_PROPRIETARY_RESERVED_Pos                                                         31U
+#define PCC_REG_PROPRIETARY_RESERVED_Msk                                                         (0x1UL << PCC_REG_PROPRIETARY_RESERVED_Pos)
+
+/* 0x29C    0x4000_029c
+    7:0     R/W     ENTRY_DELAY_CORE1_DEV_IR_RC                     8'b0
+    8       R/W     RESERVED_7                                      1'b1
+    9       R/W     RESERVED_6                                      1'b1
+    10      R/W     RESERVED_5                                      1'b1
+    11      R/W     RESERVED_4                                      1'b1
+    12      R/W     RESERVED_3                                      1'b1
+    15:13   R/W     RESERVED_2                                      3'b0
+    16      R/W     R_SCLK_IRRC_SRC_SEL_0                           1'b1
+    17      R/W     R_SCLK_IRRC_SRC_SEL_1                           1'b0
+    18      R/W     IRRC_CLK_FORCE                                  1'b0
+    26:19   R/W     RSVD_1                                          8'b000
+    27      R/W     RESERVED_1                                      1'b0
+    30:28   R/W     RSVD                                            3'b000
+    31      R/W     RESERVED                                        1'b0
+ */
+typedef union _PCC_REG_IR_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t ENTRY_DELAY_CORE1_DEV_IR_RC: 8;
+        uint32_t RESERVED_7: 1;
+        uint32_t RESERVED_6: 1;
+        uint32_t RESERVED_5: 1;
+        uint32_t RESERVED_4: 1;
+        uint32_t RESERVED_3: 1;
+        uint32_t RESERVED_2: 3;
+        uint32_t R_SCLK_IRRC_SRC_SEL_0: 1;
+        uint32_t R_SCLK_IRRC_SRC_SEL_1: 1;
+        uint32_t IRRC_CLK_FORCE: 1;
+        uint32_t RSVD_1: 8;
+        uint32_t RESERVED_1: 1;
+        uint32_t RSVD: 3;
+        uint32_t RESERVED: 1;
+    };
+} PCC_REG_IR_TYPE;
+
+/*0x4000_029c PCC_REG_IR*/
+#define PCC_REG_IR_ENTRY_DELAY_CORE1_DEV_IR_RC_Pos                                               0U
+#define PCC_REG_IR_ENTRY_DELAY_CORE1_DEV_IR_RC_Msk                                               (0xFFUL << PCC_REG_IR_ENTRY_DELAY_CORE1_DEV_IR_RC_Pos)
+
+#define PCC_REG_IR_RESERVED_7_Pos                                                                8U
+#define PCC_REG_IR_RESERVED_7_Msk                                                                (0x1UL << PCC_REG_IR_RESERVED_7_Pos)
+
+#define PCC_REG_IR_RESERVED_6_Pos                                                                9U
+#define PCC_REG_IR_RESERVED_6_Msk                                                                (0x1UL << PCC_REG_IR_RESERVED_6_Pos)
+
+#define PCC_REG_IR_RESERVED_5_Pos                                                                10U
+#define PCC_REG_IR_RESERVED_5_Msk                                                                (0x1UL << PCC_REG_IR_RESERVED_5_Pos)
+
+#define PCC_REG_IR_RESERVED_4_Pos                                                                11U
+#define PCC_REG_IR_RESERVED_4_Msk                                                                (0x1UL << PCC_REG_IR_RESERVED_4_Pos)
+
+#define PCC_REG_IR_RESERVED_3_Pos                                                                12U
+#define PCC_REG_IR_RESERVED_3_Msk                                                                (0x1UL << PCC_REG_IR_RESERVED_3_Pos)
+
+#define PCC_REG_IR_RESERVED_2_Pos                                                                13U
+#define PCC_REG_IR_RESERVED_2_Msk                                                                (0x7UL << PCC_REG_IR_RESERVED_2_Pos)
+
+#define PCC_REG_IR_R_SCLK_IRRC_SRC_SEL_0_Pos                                                     16U
+#define PCC_REG_IR_R_SCLK_IRRC_SRC_SEL_0_Msk                                                     (0x1UL << PCC_REG_IR_R_SCLK_IRRC_SRC_SEL_0_Pos)
+
+#define PCC_REG_IR_R_SCLK_IRRC_SRC_SEL_1_Pos                                                     17U
+#define PCC_REG_IR_R_SCLK_IRRC_SRC_SEL_1_Msk                                                     (0x1UL << PCC_REG_IR_R_SCLK_IRRC_SRC_SEL_1_Pos)
+
+#define PCC_REG_IR_IRRC_CLK_FORCE_Pos                                                            18U
+#define PCC_REG_IR_IRRC_CLK_FORCE_Msk                                                            (0x1UL << PCC_REG_IR_IRRC_CLK_FORCE_Pos)
+
+#define PCC_REG_IR_RSVD_1_Pos                                                                    19U
+#define PCC_REG_IR_RSVD_1_Msk                                                                    (0xFFUL << PCC_REG_IR_RSVD_1_Pos)
+
+#define PCC_REG_IR_RESERVED_1_Pos                                                                27U
+#define PCC_REG_IR_RESERVED_1_Msk                                                                (0x1UL << PCC_REG_IR_RESERVED_1_Pos)
+
+#define PCC_REG_IR_RSVD_Pos                                                                      28U
+#define PCC_REG_IR_RSVD_Msk                                                                      (0x7UL << PCC_REG_IR_RSVD_Pos)
+
+#define PCC_REG_IR_RESERVED_Pos                                                                  31U
+#define PCC_REG_IR_RESERVED_Msk                                                                  (0x1UL << PCC_REG_IR_RESERVED_Pos)
+
+/* 0x2A0    0x4000_02a0
+    7:0     R/W     ENTRY_DELAY_CORE1_DEV_BT_VENDOR_REG             8'b0
+    8       R/W     RESERVED_13                                     1'b0
+    9       R/W     RESERVED_12                                     1'b0
+    10      R/W     RESERVED_11                                     1'b0
+    11      R/W     RESERVED_10                                     1'b1
+    12      R/W     RESERVED_9                                      1'b0
+    15:13   R/W     RSVD_2                                          3'h0
+    16      R/W     RESERVED_8                                      1'b0
+    17      R/W     BT_VDREG_CLK_FORCE                              1'b0
+    18      R/W     RESERVED_7                                      1'b1
+    21:19   R/W     RSVD_1                                          3'b000
+    22      R/W     RESERVED_6                                      1'b0
+    23      R/W     RESERVED_5                                      1'b0
+    24      R/W     RESERVED_4                                      1'b0
+    25      R/W     RESERVED_3                                      1'b0
+    26      R/W     RESERVED_2                                      1'b0
+    27      R/W     RESERVED_1                                      1'b0
+    30:28   R/W     RSVD                                            3'b000
+    31      R/W     RESERVED                                        1'b0
+ */
+typedef union _PCC_REG_BT_VDREG_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t ENTRY_DELAY_CORE1_DEV_BT_VENDOR_REG: 8;
+        uint32_t RESERVED_13: 1;
+        uint32_t RESERVED_12: 1;
+        uint32_t RESERVED_11: 1;
+        uint32_t RESERVED_10: 1;
+        uint32_t RESERVED_9: 1;
+        uint32_t RSVD_2: 3;
+        uint32_t RESERVED_8: 1;
+        uint32_t BT_VDREG_CLK_FORCE: 1;
+        uint32_t RESERVED_7: 1;
+        uint32_t RSVD_1: 3;
+        uint32_t RESERVED_6: 1;
+        uint32_t RESERVED_5: 1;
+        uint32_t RESERVED_4: 1;
+        uint32_t RESERVED_3: 1;
+        uint32_t RESERVED_2: 1;
+        uint32_t RESERVED_1: 1;
+        uint32_t RSVD: 3;
+        uint32_t RESERVED: 1;
+    };
+} PCC_REG_BT_VDREG_TYPE;
+
+/*0x4000_02a0 PCC_REG_BT_VDREG*/
+#define PCC_REG_BT_VDREG_ENTRY_DELAY_CORE1_DEV_BT_VENDOR_REG_Pos                                 0U
+#define PCC_REG_BT_VDREG_ENTRY_DELAY_CORE1_DEV_BT_VENDOR_REG_Msk                                 (0xFFUL << PCC_REG_BT_VDREG_ENTRY_DELAY_CORE1_DEV_BT_VENDOR_REG_Pos)
+
+#define PCC_REG_BT_VDREG_RESERVED_13_Pos                                                         8U
+#define PCC_REG_BT_VDREG_RESERVED_13_Msk                                                         (0x1UL << PCC_REG_BT_VDREG_RESERVED_13_Pos)
+
+#define PCC_REG_BT_VDREG_RESERVED_12_Pos                                                         9U
+#define PCC_REG_BT_VDREG_RESERVED_12_Msk                                                         (0x1UL << PCC_REG_BT_VDREG_RESERVED_12_Pos)
+
+#define PCC_REG_BT_VDREG_RESERVED_11_Pos                                                         10U
+#define PCC_REG_BT_VDREG_RESERVED_11_Msk                                                         (0x1UL << PCC_REG_BT_VDREG_RESERVED_11_Pos)
+
+#define PCC_REG_BT_VDREG_RESERVED_10_Pos                                                         11U
+#define PCC_REG_BT_VDREG_RESERVED_10_Msk                                                         (0x1UL << PCC_REG_BT_VDREG_RESERVED_10_Pos)
+
+#define PCC_REG_BT_VDREG_RESERVED_9_Pos                                                          12U
+#define PCC_REG_BT_VDREG_RESERVED_9_Msk                                                          (0x1UL << PCC_REG_BT_VDREG_RESERVED_9_Pos)
+
+#define PCC_REG_BT_VDREG_RSVD_2_Pos                                                              13U
+#define PCC_REG_BT_VDREG_RSVD_2_Msk                                                              (0x7UL << PCC_REG_BT_VDREG_RSVD_2_Pos)
+
+#define PCC_REG_BT_VDREG_RESERVED_8_Pos                                                          16U
+#define PCC_REG_BT_VDREG_RESERVED_8_Msk                                                          (0x1UL << PCC_REG_BT_VDREG_RESERVED_8_Pos)
+
+#define PCC_REG_BT_VDREG_BT_VDREG_CLK_FORCE_Pos                                                  17U
+#define PCC_REG_BT_VDREG_BT_VDREG_CLK_FORCE_Msk                                                  (0x1UL << PCC_REG_BT_VDREG_BT_VDREG_CLK_FORCE_Pos)
+
+#define PCC_REG_BT_VDREG_RESERVED_7_Pos                                                          18U
+#define PCC_REG_BT_VDREG_RESERVED_7_Msk                                                          (0x1UL << PCC_REG_BT_VDREG_RESERVED_7_Pos)
+
+#define PCC_REG_BT_VDREG_RSVD_1_Pos                                                              19U
+#define PCC_REG_BT_VDREG_RSVD_1_Msk                                                              (0x7UL << PCC_REG_BT_VDREG_RSVD_1_Pos)
+
+#define PCC_REG_BT_VDREG_RESERVED_6_Pos                                                          22U
+#define PCC_REG_BT_VDREG_RESERVED_6_Msk                                                          (0x1UL << PCC_REG_BT_VDREG_RESERVED_6_Pos)
+
+#define PCC_REG_BT_VDREG_RESERVED_5_Pos                                                          23U
+#define PCC_REG_BT_VDREG_RESERVED_5_Msk                                                          (0x1UL << PCC_REG_BT_VDREG_RESERVED_5_Pos)
+
+#define PCC_REG_BT_VDREG_RESERVED_4_Pos                                                          24U
+#define PCC_REG_BT_VDREG_RESERVED_4_Msk                                                          (0x1UL << PCC_REG_BT_VDREG_RESERVED_4_Pos)
+
+#define PCC_REG_BT_VDREG_RESERVED_3_Pos                                                          25U
+#define PCC_REG_BT_VDREG_RESERVED_3_Msk                                                          (0x1UL << PCC_REG_BT_VDREG_RESERVED_3_Pos)
+
+#define PCC_REG_BT_VDREG_RESERVED_2_Pos                                                          26U
+#define PCC_REG_BT_VDREG_RESERVED_2_Msk                                                          (0x1UL << PCC_REG_BT_VDREG_RESERVED_2_Pos)
+
+#define PCC_REG_BT_VDREG_RESERVED_1_Pos                                                          27U
+#define PCC_REG_BT_VDREG_RESERVED_1_Msk                                                          (0x1UL << PCC_REG_BT_VDREG_RESERVED_1_Pos)
+
+#define PCC_REG_BT_VDREG_RSVD_Pos                                                                28U
+#define PCC_REG_BT_VDREG_RSVD_Msk                                                                (0x7UL << PCC_REG_BT_VDREG_RSVD_Pos)
+
+#define PCC_REG_BT_VDREG_RESERVED_Pos                                                            31U
+#define PCC_REG_BT_VDREG_RESERVED_Msk                                                            (0x1UL << PCC_REG_BT_VDREG_RESERVED_Pos)
+
+/* 0x2A4    0x4000_02a4
+    7:0     R/W     ENTRY_DELAY_CORE1_DEV_CODEC                     8'b0
+    8       R/W     RESERVED_14                                     1'b0
+    9       R/W     RESERVED_13                                     1'b1
+    10      R/W     RESERVED_12                                     1'b1
+    11      R/W     RESERVED_11                                     1'b1
+    12      R/W     RESERVED_10                                     1'b1
+    13      R/W     RESERVED_9                                      1'b0
+    15:14   R/W     RSVD_2                                          2'h0
+    16      R/W     RESERVED_8                                      1'b0
+    17      R/W     RESERVED_7                                      1'b0
+    18      R/W     CODEC_CLK_FORCE                                 1'b0
+    21:19   R/W     RSVD_1                                          3'b000
+    22      R/W     RESERVED_6                                      1'b0
+    23      R/W     RESERVED_5                                      1'b0
+    24      R/W     RESERVED_4                                      1'b0
+    25      R/W     RESERVED_3                                      1'b0
+    26      R/W     RESERVED_2                                      1'b0
+    27      R/W     RESERVED_1                                      1'b0
+    30:28   R/W     RSVD                                            3'b000
+    31      R/W     RESERVED                                        1'b0
+ */
+typedef union _PCC_REG_AUDIO_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t ENTRY_DELAY_CORE1_DEV_CODEC: 8;
+        uint32_t RESERVED_14: 1;
+        uint32_t RESERVED_13: 1;
+        uint32_t RESERVED_12: 1;
+        uint32_t RESERVED_11: 1;
+        uint32_t RESERVED_10: 1;
+        uint32_t RESERVED_9: 1;
+        uint32_t RSVD_2: 2;
+        uint32_t RESERVED_8: 1;
+        uint32_t RESERVED_7: 1;
+        uint32_t CODEC_CLK_FORCE: 1;
+        uint32_t RSVD_1: 3;
+        uint32_t RESERVED_6: 1;
+        uint32_t RESERVED_5: 1;
+        uint32_t RESERVED_4: 1;
+        uint32_t RESERVED_3: 1;
+        uint32_t RESERVED_2: 1;
+        uint32_t RESERVED_1: 1;
+        uint32_t RSVD: 3;
+        uint32_t RESERVED: 1;
+    };
+} PCC_REG_AUDIO_TYPE;
+
+/*0x4000_02a4 PCC_REG_AUDIO*/
+#define PCC_REG_AUDIO_ENTRY_DELAY_CORE1_DEV_CODEC_Pos                                            0U
+#define PCC_REG_AUDIO_ENTRY_DELAY_CORE1_DEV_CODEC_Msk                                            (0xFFUL << PCC_REG_AUDIO_ENTRY_DELAY_CORE1_DEV_CODEC_Pos)
+
+#define PCC_REG_AUDIO_RESERVED_14_Pos                                                            8U
+#define PCC_REG_AUDIO_RESERVED_14_Msk                                                            (0x1UL << PCC_REG_AUDIO_RESERVED_14_Pos)
+
+#define PCC_REG_AUDIO_RESERVED_13_Pos                                                            9U
+#define PCC_REG_AUDIO_RESERVED_13_Msk                                                            (0x1UL << PCC_REG_AUDIO_RESERVED_13_Pos)
+
+#define PCC_REG_AUDIO_RESERVED_12_Pos                                                            10U
+#define PCC_REG_AUDIO_RESERVED_12_Msk                                                            (0x1UL << PCC_REG_AUDIO_RESERVED_12_Pos)
+
+#define PCC_REG_AUDIO_RESERVED_11_Pos                                                            11U
+#define PCC_REG_AUDIO_RESERVED_11_Msk                                                            (0x1UL << PCC_REG_AUDIO_RESERVED_11_Pos)
+
+#define PCC_REG_AUDIO_RESERVED_10_Pos                                                            12U
+#define PCC_REG_AUDIO_RESERVED_10_Msk                                                            (0x1UL << PCC_REG_AUDIO_RESERVED_10_Pos)
+
+#define PCC_REG_AUDIO_RESERVED_9_Pos                                                             13U
+#define PCC_REG_AUDIO_RESERVED_9_Msk                                                             (0x1UL << PCC_REG_AUDIO_RESERVED_9_Pos)
+
+#define PCC_REG_AUDIO_RSVD_2_Pos                                                                 14U
+#define PCC_REG_AUDIO_RSVD_2_Msk                                                                 (0x3UL << PCC_REG_AUDIO_RSVD_2_Pos)
+
+#define PCC_REG_AUDIO_RESERVED_8_Pos                                                             16U
+#define PCC_REG_AUDIO_RESERVED_8_Msk                                                             (0x1UL << PCC_REG_AUDIO_RESERVED_8_Pos)
+
+#define PCC_REG_AUDIO_RESERVED_7_Pos                                                             17U
+#define PCC_REG_AUDIO_RESERVED_7_Msk                                                             (0x1UL << PCC_REG_AUDIO_RESERVED_7_Pos)
+
+#define PCC_REG_AUDIO_CODEC_CLK_FORCE_Pos                                                        18U
+#define PCC_REG_AUDIO_CODEC_CLK_FORCE_Msk                                                        (0x1UL << PCC_REG_AUDIO_CODEC_CLK_FORCE_Pos)
+
+#define PCC_REG_AUDIO_RSVD_1_Pos                                                                 19U
+#define PCC_REG_AUDIO_RSVD_1_Msk                                                                 (0x7UL << PCC_REG_AUDIO_RSVD_1_Pos)
+
+#define PCC_REG_AUDIO_RESERVED_6_Pos                                                             22U
+#define PCC_REG_AUDIO_RESERVED_6_Msk                                                             (0x1UL << PCC_REG_AUDIO_RESERVED_6_Pos)
+
+#define PCC_REG_AUDIO_RESERVED_5_Pos                                                             23U
+#define PCC_REG_AUDIO_RESERVED_5_Msk                                                             (0x1UL << PCC_REG_AUDIO_RESERVED_5_Pos)
+
+#define PCC_REG_AUDIO_RESERVED_4_Pos                                                             24U
+#define PCC_REG_AUDIO_RESERVED_4_Msk                                                             (0x1UL << PCC_REG_AUDIO_RESERVED_4_Pos)
+
+#define PCC_REG_AUDIO_RESERVED_3_Pos                                                             25U
+#define PCC_REG_AUDIO_RESERVED_3_Msk                                                             (0x1UL << PCC_REG_AUDIO_RESERVED_3_Pos)
+
+#define PCC_REG_AUDIO_RESERVED_2_Pos                                                             26U
+#define PCC_REG_AUDIO_RESERVED_2_Msk                                                             (0x1UL << PCC_REG_AUDIO_RESERVED_2_Pos)
+
+#define PCC_REG_AUDIO_RESERVED_1_Pos                                                             27U
+#define PCC_REG_AUDIO_RESERVED_1_Msk                                                             (0x1UL << PCC_REG_AUDIO_RESERVED_1_Pos)
+
+#define PCC_REG_AUDIO_RSVD_Pos                                                                   28U
+#define PCC_REG_AUDIO_RSVD_Msk                                                                   (0x7UL << PCC_REG_AUDIO_RSVD_Pos)
+
+#define PCC_REG_AUDIO_RESERVED_Pos                                                               31U
+#define PCC_REG_AUDIO_RESERVED_Msk                                                               (0x1UL << PCC_REG_AUDIO_RESERVED_Pos)
+
+/* 0x2A8    0x4000_02a8
+    7:0     R/W     ENTRY_DELAY_CORE1_DEV_LXBUS                     8'b0
+    8       R/W     RESERVED_13                                     1'b0
+    9       R/W     RESERVED_12                                     1'b0
+    10      R/W     RESERVED_11                                     1'b0
+    11      R/W     RESERVED_10                                     1'b1
+    12      R/W     RESERVED_9                                      1'b1
+    15:13   R/W     RSVD_2                                          3'h0
+    16      R/W     RESERVED_8                                      1'b0
+    17      R/W     RESERVED_7                                      1'b0
+    18      R/W     LXBUS_CLK_FORCE                                 1'b0
+    21:19   R/W     RSVD_1                                          3'b000
+    22      R/W     RESERVED_6                                      1'b0
+    23      R/W     RESERVED_5                                      1'b0
+    24      R/W     RESERVED_4                                      1'b0
+    25      R/W     RESERVED_3                                      1'b0
+    26      R/W     RESERVED_2                                      1'b0
+    27      R/W     RESERVED_1                                      1'b0
+    30:28   R/W     RSVD                                            3'b000
+    31      R/W     RESERVED                                        1'b0
+ */
+typedef union _PCC_REG_LXBUS_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t ENTRY_DELAY_CORE1_DEV_LXBUS: 8;
+        uint32_t RESERVED_13: 1;
+        uint32_t RESERVED_12: 1;
+        uint32_t RESERVED_11: 1;
+        uint32_t RESERVED_10: 1;
+        uint32_t RESERVED_9: 1;
+        uint32_t RSVD_2: 3;
+        uint32_t RESERVED_8: 1;
+        uint32_t RESERVED_7: 1;
+        uint32_t LXBUS_CLK_FORCE: 1;
+        uint32_t RSVD_1: 3;
+        uint32_t RESERVED_6: 1;
+        uint32_t RESERVED_5: 1;
+        uint32_t RESERVED_4: 1;
+        uint32_t RESERVED_3: 1;
+        uint32_t RESERVED_2: 1;
+        uint32_t RESERVED_1: 1;
+        uint32_t RSVD: 3;
+        uint32_t RESERVED: 1;
+    };
+} PCC_REG_LXBUS_TYPE;
+
+/*0x4000_02a8 PCC_REG_LXBUS*/
+#define PCC_REG_LXBUS_ENTRY_DELAY_CORE1_DEV_LXBUS_Pos                                            0U
+#define PCC_REG_LXBUS_ENTRY_DELAY_CORE1_DEV_LXBUS_Msk                                            (0xFFUL << PCC_REG_LXBUS_ENTRY_DELAY_CORE1_DEV_LXBUS_Pos)
+
+#define PCC_REG_LXBUS_RESERVED_13_Pos                                                            8U
+#define PCC_REG_LXBUS_RESERVED_13_Msk                                                            (0x1UL << PCC_REG_LXBUS_RESERVED_13_Pos)
+
+#define PCC_REG_LXBUS_RESERVED_12_Pos                                                            9U
+#define PCC_REG_LXBUS_RESERVED_12_Msk                                                            (0x1UL << PCC_REG_LXBUS_RESERVED_12_Pos)
+
+#define PCC_REG_LXBUS_RESERVED_11_Pos                                                            10U
+#define PCC_REG_LXBUS_RESERVED_11_Msk                                                            (0x1UL << PCC_REG_LXBUS_RESERVED_11_Pos)
+
+#define PCC_REG_LXBUS_RESERVED_10_Pos                                                            11U
+#define PCC_REG_LXBUS_RESERVED_10_Msk                                                            (0x1UL << PCC_REG_LXBUS_RESERVED_10_Pos)
+
+#define PCC_REG_LXBUS_RESERVED_9_Pos                                                             12U
+#define PCC_REG_LXBUS_RESERVED_9_Msk                                                             (0x1UL << PCC_REG_LXBUS_RESERVED_9_Pos)
+
+#define PCC_REG_LXBUS_RSVD_2_Pos                                                                 13U
+#define PCC_REG_LXBUS_RSVD_2_Msk                                                                 (0x7UL << PCC_REG_LXBUS_RSVD_2_Pos)
+
+#define PCC_REG_LXBUS_RESERVED_8_Pos                                                             16U
+#define PCC_REG_LXBUS_RESERVED_8_Msk                                                             (0x1UL << PCC_REG_LXBUS_RESERVED_8_Pos)
+
+#define PCC_REG_LXBUS_RESERVED_7_Pos                                                             17U
+#define PCC_REG_LXBUS_RESERVED_7_Msk                                                             (0x1UL << PCC_REG_LXBUS_RESERVED_7_Pos)
+
+#define PCC_REG_LXBUS_LXBUS_CLK_FORCE_Pos                                                        18U
+#define PCC_REG_LXBUS_LXBUS_CLK_FORCE_Msk                                                        (0x1UL << PCC_REG_LXBUS_LXBUS_CLK_FORCE_Pos)
+
+#define PCC_REG_LXBUS_RSVD_1_Pos                                                                 19U
+#define PCC_REG_LXBUS_RSVD_1_Msk                                                                 (0x7UL << PCC_REG_LXBUS_RSVD_1_Pos)
+
+#define PCC_REG_LXBUS_RESERVED_6_Pos                                                             22U
+#define PCC_REG_LXBUS_RESERVED_6_Msk                                                             (0x1UL << PCC_REG_LXBUS_RESERVED_6_Pos)
+
+#define PCC_REG_LXBUS_RESERVED_5_Pos                                                             23U
+#define PCC_REG_LXBUS_RESERVED_5_Msk                                                             (0x1UL << PCC_REG_LXBUS_RESERVED_5_Pos)
+
+#define PCC_REG_LXBUS_RESERVED_4_Pos                                                             24U
+#define PCC_REG_LXBUS_RESERVED_4_Msk                                                             (0x1UL << PCC_REG_LXBUS_RESERVED_4_Pos)
+
+#define PCC_REG_LXBUS_RESERVED_3_Pos                                                             25U
+#define PCC_REG_LXBUS_RESERVED_3_Msk                                                             (0x1UL << PCC_REG_LXBUS_RESERVED_3_Pos)
+
+#define PCC_REG_LXBUS_RESERVED_2_Pos                                                             26U
+#define PCC_REG_LXBUS_RESERVED_2_Msk                                                             (0x1UL << PCC_REG_LXBUS_RESERVED_2_Pos)
+
+#define PCC_REG_LXBUS_RESERVED_1_Pos                                                             27U
+#define PCC_REG_LXBUS_RESERVED_1_Msk                                                             (0x1UL << PCC_REG_LXBUS_RESERVED_1_Pos)
+
+#define PCC_REG_LXBUS_RSVD_Pos                                                                   28U
+#define PCC_REG_LXBUS_RSVD_Msk                                                                   (0x7UL << PCC_REG_LXBUS_RSVD_Pos)
+
+#define PCC_REG_LXBUS_RESERVED_Pos                                                               31U
+#define PCC_REG_LXBUS_RESERVED_Msk                                                               (0x1UL << PCC_REG_LXBUS_RESERVED_Pos)
+
+/* 0x2AC    0x4000_02ac
+    7:0     R/W     RESERVED_11                                     8'b0
+    8       R/W     RESERVED_10                                     1'b0
+    9       R/W     RESERVED_9                                      1'b0
+    10      R/W     RESERVED_8                                      1'b1
+    11      R/W     RESERVED_7                                      1'b1
+    12      R/W     RESERVED_6                                      1'b1
+    15:13   R/W     RSVD_2                                          3'b0
+    16      R/W     ACC_CLK_FORCE                                   1'b0
+    18:17   R/W     RSVD_1                                          2'b0
+    19      R/W     CAL32K_CLK_FORCE                                1'b0
+    24:20   R/W     RSVD                                            5'b0
+    25      R/W     RESERVED_5                                      1'b0
+    27:26   R/W     RESERVED_4                                      2'b0
+    28      R/W     RESERVED_3                                      1'b0
+    29      R/W     RESERVED_2                                      1'b0
+    30      R/W     RESERVED_1                                      1'b0
+    31      R/W     RESERVED                                        1'b0
+ */
+typedef union _PCC_REG_CAL32K_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED_11: 8;
+        uint32_t RESERVED_10: 1;
+        uint32_t RESERVED_9: 1;
+        uint32_t RESERVED_8: 1;
+        uint32_t RESERVED_7: 1;
+        uint32_t RESERVED_6: 1;
+        uint32_t RSVD_2: 3;
+        uint32_t ACC_CLK_FORCE: 1;
+        uint32_t RSVD_1: 2;
+        uint32_t CAL32K_CLK_FORCE: 1;
+        uint32_t RSVD: 5;
+        uint32_t RESERVED_5: 1;
+        uint32_t RESERVED_4: 2;
+        uint32_t RESERVED_3: 1;
+        uint32_t RESERVED_2: 1;
+        uint32_t RESERVED_1: 1;
+        uint32_t RESERVED: 1;
+    };
+} PCC_REG_CAL32K_TYPE;
+
+/*0x4000_02ac PCC_REG_CAL32K*/
+#define PCC_REG_CAL32K_RESERVED_11_Pos                                                           0U
+#define PCC_REG_CAL32K_RESERVED_11_Msk                                                           (0xFFUL << PCC_REG_CAL32K_RESERVED_11_Pos)
+
+#define PCC_REG_CAL32K_RESERVED_10_Pos                                                           8U
+#define PCC_REG_CAL32K_RESERVED_10_Msk                                                           (0x1UL << PCC_REG_CAL32K_RESERVED_10_Pos)
+
+#define PCC_REG_CAL32K_RESERVED_9_Pos                                                            9U
+#define PCC_REG_CAL32K_RESERVED_9_Msk                                                            (0x1UL << PCC_REG_CAL32K_RESERVED_9_Pos)
+
+#define PCC_REG_CAL32K_RESERVED_8_Pos                                                            10U
+#define PCC_REG_CAL32K_RESERVED_8_Msk                                                            (0x1UL << PCC_REG_CAL32K_RESERVED_8_Pos)
+
+#define PCC_REG_CAL32K_RESERVED_7_Pos                                                            11U
+#define PCC_REG_CAL32K_RESERVED_7_Msk                                                            (0x1UL << PCC_REG_CAL32K_RESERVED_7_Pos)
+
+#define PCC_REG_CAL32K_RESERVED_6_Pos                                                            12U
+#define PCC_REG_CAL32K_RESERVED_6_Msk                                                            (0x1UL << PCC_REG_CAL32K_RESERVED_6_Pos)
+
+#define PCC_REG_CAL32K_RSVD_2_Pos                                                                13U
+#define PCC_REG_CAL32K_RSVD_2_Msk                                                                (0x7UL << PCC_REG_CAL32K_RSVD_2_Pos)
+
+#define PCC_REG_CAL32K_ACC_CLK_FORCE_Pos                                                         16U
+#define PCC_REG_CAL32K_ACC_CLK_FORCE_Msk                                                         (0x1UL << PCC_REG_CAL32K_ACC_CLK_FORCE_Pos)
+
+#define PCC_REG_CAL32K_RSVD_1_Pos                                                                17U
+#define PCC_REG_CAL32K_RSVD_1_Msk                                                                (0x3UL << PCC_REG_CAL32K_RSVD_1_Pos)
+
+#define PCC_REG_CAL32K_CAL32K_CLK_FORCE_Pos                                                      19U
+#define PCC_REG_CAL32K_CAL32K_CLK_FORCE_Msk                                                      (0x1UL << PCC_REG_CAL32K_CAL32K_CLK_FORCE_Pos)
+
+#define PCC_REG_CAL32K_RSVD_Pos                                                                  20U
+#define PCC_REG_CAL32K_RSVD_Msk                                                                  (0x1FUL << PCC_REG_CAL32K_RSVD_Pos)
+
+#define PCC_REG_CAL32K_RESERVED_5_Pos                                                            25U
+#define PCC_REG_CAL32K_RESERVED_5_Msk                                                            (0x1UL << PCC_REG_CAL32K_RESERVED_5_Pos)
+
+#define PCC_REG_CAL32K_RESERVED_4_Pos                                                            26U
+#define PCC_REG_CAL32K_RESERVED_4_Msk                                                            (0x3UL << PCC_REG_CAL32K_RESERVED_4_Pos)
+
+#define PCC_REG_CAL32K_RESERVED_3_Pos                                                            28U
+#define PCC_REG_CAL32K_RESERVED_3_Msk                                                            (0x1UL << PCC_REG_CAL32K_RESERVED_3_Pos)
+
+#define PCC_REG_CAL32K_RESERVED_2_Pos                                                            29U
+#define PCC_REG_CAL32K_RESERVED_2_Msk                                                            (0x1UL << PCC_REG_CAL32K_RESERVED_2_Pos)
+
+#define PCC_REG_CAL32K_RESERVED_1_Pos                                                            30U
+#define PCC_REG_CAL32K_RESERVED_1_Msk                                                            (0x1UL << PCC_REG_CAL32K_RESERVED_1_Pos)
+
+#define PCC_REG_CAL32K_RESERVED_Pos                                                              31U
+#define PCC_REG_CAL32K_RESERVED_Msk                                                              (0x1UL << PCC_REG_CAL32K_RESERVED_Pos)
+
+/* 0x2B0    0x4000_02b0
+    7:0     R/W     RESERVED_9                                      8'b0
+    8       R/W     RESERVED_8                                      1'b1
+    9       R/W     RESERVED_7                                      1'b1
+    10      R/W     RESERVED_6                                      1'b1
+    11      R/W     RESERVED_5                                      1'b0
+    12      R/W     RESERVED_4                                      1'b1
+    13      R/W     RESERVED_3                                      1'b1
+    14      R/W     RESERVED_2                                      1'b1
+    15      R/W     RESERVED_1                                      1'b0
+    16      R/W     PLATFORM_CLK_FORCE                              1'b0
+    17      R/W     PLATFORM_MANU_SEL                               1'b0
+    18      R/W     PLATFORM_MANU_DAT                               1'b0
+    31:19   R/W     RESERVED                                        13'b0
+ */
+typedef union _PCC_REG_PLATFORM_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED_9: 8;
+        uint32_t RESERVED_8: 1;
+        uint32_t RESERVED_7: 1;
+        uint32_t RESERVED_6: 1;
+        uint32_t RESERVED_5: 1;
+        uint32_t RESERVED_4: 1;
+        uint32_t RESERVED_3: 1;
+        uint32_t RESERVED_2: 1;
+        uint32_t RESERVED_1: 1;
+        uint32_t PLATFORM_CLK_FORCE: 1;
+        uint32_t PLATFORM_MANU_SEL: 1;
+        uint32_t PLATFORM_MANU_DAT: 1;
+        uint32_t RESERVED: 13;
+    };
+} PCC_REG_PLATFORM_TYPE;
+
+/*0x4000_02b0 PCC_REG_PLATFORM*/
+#define PCC_REG_PLATFORM_RESERVED_9_Pos                                                          0U
+#define PCC_REG_PLATFORM_RESERVED_9_Msk                                                          (0xFFUL << PCC_REG_PLATFORM_RESERVED_9_Pos)
+
+#define PCC_REG_PLATFORM_RESERVED_8_Pos                                                          8U
+#define PCC_REG_PLATFORM_RESERVED_8_Msk                                                          (0x1UL << PCC_REG_PLATFORM_RESERVED_8_Pos)
+
+#define PCC_REG_PLATFORM_RESERVED_7_Pos                                                          9U
+#define PCC_REG_PLATFORM_RESERVED_7_Msk                                                          (0x1UL << PCC_REG_PLATFORM_RESERVED_7_Pos)
+
+#define PCC_REG_PLATFORM_RESERVED_6_Pos                                                          10U
+#define PCC_REG_PLATFORM_RESERVED_6_Msk                                                          (0x1UL << PCC_REG_PLATFORM_RESERVED_6_Pos)
+
+#define PCC_REG_PLATFORM_RESERVED_5_Pos                                                          11U
+#define PCC_REG_PLATFORM_RESERVED_5_Msk                                                          (0x1UL << PCC_REG_PLATFORM_RESERVED_5_Pos)
+
+#define PCC_REG_PLATFORM_RESERVED_4_Pos                                                          12U
+#define PCC_REG_PLATFORM_RESERVED_4_Msk                                                          (0x1UL << PCC_REG_PLATFORM_RESERVED_4_Pos)
+
+#define PCC_REG_PLATFORM_RESERVED_3_Pos                                                          13U
+#define PCC_REG_PLATFORM_RESERVED_3_Msk                                                          (0x1UL << PCC_REG_PLATFORM_RESERVED_3_Pos)
+
+#define PCC_REG_PLATFORM_RESERVED_2_Pos                                                          14U
+#define PCC_REG_PLATFORM_RESERVED_2_Msk                                                          (0x1UL << PCC_REG_PLATFORM_RESERVED_2_Pos)
+
+#define PCC_REG_PLATFORM_RESERVED_1_Pos                                                          15U
+#define PCC_REG_PLATFORM_RESERVED_1_Msk                                                          (0x1UL << PCC_REG_PLATFORM_RESERVED_1_Pos)
+
+#define PCC_REG_PLATFORM_PLATFORM_CLK_FORCE_Pos                                                  16U
+#define PCC_REG_PLATFORM_PLATFORM_CLK_FORCE_Msk                                                  (0x1UL << PCC_REG_PLATFORM_PLATFORM_CLK_FORCE_Pos)
+
+#define PCC_REG_PLATFORM_PLATFORM_MANU_SEL_Pos                                                   17U
+#define PCC_REG_PLATFORM_PLATFORM_MANU_SEL_Msk                                                   (0x1UL << PCC_REG_PLATFORM_PLATFORM_MANU_SEL_Pos)
+
+#define PCC_REG_PLATFORM_PLATFORM_MANU_DAT_Pos                                                   18U
+#define PCC_REG_PLATFORM_PLATFORM_MANU_DAT_Msk                                                   (0x1UL << PCC_REG_PLATFORM_PLATFORM_MANU_DAT_Pos)
+
+#define PCC_REG_PLATFORM_RESERVED_Pos                                                            19U
+#define PCC_REG_PLATFORM_RESERVED_Msk                                                            (0x1FFFUL << PCC_REG_PLATFORM_RESERVED_Pos)
+
+/* 0x2B4    0x4000_02b4
+    7:0     R/W     ENTRY_DELAY_CORE1_DEV_PCC                       8'b0
+    8       R/W     RESERVED_10                                     1'b0
+    9       R/W     RESERVED_9                                      1'b0
+    10      R/W     RESERVED_8                                      1'b0
+    11      R/W     RESERVED_7                                      1'b1
+    12      R/W     RESERVED_6                                      1'b1
+    15:13   R/W     RESERVED_5                                      3'b0
+    16      R/W     RESERVED_4                                      1'b1
+    17      R/W     RESERVED_3                                      1'b0
+    18      R/W     RESERVED_2                                      1'b0
+    19      R/W     RESERVED_1                                      1'b0
+    31:20   R/W     RESERVED                                        12'b0
+ */
+typedef union _PCC_REG_PCC_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t ENTRY_DELAY_CORE1_DEV_PCC: 8;
+        uint32_t RESERVED_10: 1;
+        uint32_t RESERVED_9: 1;
+        uint32_t RESERVED_8: 1;
+        uint32_t RESERVED_7: 1;
+        uint32_t RESERVED_6: 1;
+        uint32_t RESERVED_5: 3;
+        uint32_t RESERVED_4: 1;
+        uint32_t RESERVED_3: 1;
+        uint32_t RESERVED_2: 1;
+        uint32_t RESERVED_1: 1;
+        uint32_t RESERVED: 12;
+    };
+} PCC_REG_PCC_TYPE;
+
+/*0x4000_02b4 PCC_REG_PCC*/
+#define PCC_REG_PCC_ENTRY_DELAY_CORE1_DEV_PCC_Pos                                                0U
+#define PCC_REG_PCC_ENTRY_DELAY_CORE1_DEV_PCC_Msk                                                (0xFFUL << PCC_REG_PCC_ENTRY_DELAY_CORE1_DEV_PCC_Pos)
+
+#define PCC_REG_PCC_RESERVED_10_Pos                                                              8U
+#define PCC_REG_PCC_RESERVED_10_Msk                                                              (0x1UL << PCC_REG_PCC_RESERVED_10_Pos)
+
+#define PCC_REG_PCC_RESERVED_9_Pos                                                               9U
+#define PCC_REG_PCC_RESERVED_9_Msk                                                               (0x1UL << PCC_REG_PCC_RESERVED_9_Pos)
+
+#define PCC_REG_PCC_RESERVED_8_Pos                                                               10U
+#define PCC_REG_PCC_RESERVED_8_Msk                                                               (0x1UL << PCC_REG_PCC_RESERVED_8_Pos)
+
+#define PCC_REG_PCC_RESERVED_7_Pos                                                               11U
+#define PCC_REG_PCC_RESERVED_7_Msk                                                               (0x1UL << PCC_REG_PCC_RESERVED_7_Pos)
+
+#define PCC_REG_PCC_RESERVED_6_Pos                                                               12U
+#define PCC_REG_PCC_RESERVED_6_Msk                                                               (0x1UL << PCC_REG_PCC_RESERVED_6_Pos)
+
+#define PCC_REG_PCC_RESERVED_5_Pos                                                               13U
+#define PCC_REG_PCC_RESERVED_5_Msk                                                               (0x7UL << PCC_REG_PCC_RESERVED_5_Pos)
+
+#define PCC_REG_PCC_RESERVED_4_Pos                                                               16U
+#define PCC_REG_PCC_RESERVED_4_Msk                                                               (0x1UL << PCC_REG_PCC_RESERVED_4_Pos)
+
+#define PCC_REG_PCC_RESERVED_3_Pos                                                               17U
+#define PCC_REG_PCC_RESERVED_3_Msk                                                               (0x1UL << PCC_REG_PCC_RESERVED_3_Pos)
+
+#define PCC_REG_PCC_RESERVED_2_Pos                                                               18U
+#define PCC_REG_PCC_RESERVED_2_Msk                                                               (0x1UL << PCC_REG_PCC_RESERVED_2_Pos)
+
+#define PCC_REG_PCC_RESERVED_1_Pos                                                               19U
+#define PCC_REG_PCC_RESERVED_1_Msk                                                               (0x1UL << PCC_REG_PCC_RESERVED_1_Pos)
+
+#define PCC_REG_PCC_RESERVED_Pos                                                                 20U
+#define PCC_REG_PCC_RESERVED_Msk                                                                 (0xFFFUL << PCC_REG_PCC_RESERVED_Pos)
+
+/* 0x2B8    0x4000_02b8
+    7:0     R/W     ENTRY_DELAY_CORE1_DEV_TMETER                    8'b0
+    8       R/W     RESERVED_13                                     1'b0
+    9       R/W     RESERVED_12                                     1'b1
+    10      R/W     RESERVED_11                                     1'b1
+    11      R/W     RESERVED_10                                     1'b1
+    12      R/W     RESERVED_9                                      1'b1
+    15:13   R/W     RSVD_2                                          3'h0
+    16      R/W     RESERVED_8                                      1'b0
+    17      R/W     RESERVED_7                                      1'b0
+    18      R/W     TMETER_CLK_FORCE                                1'b0
+    21:19   R/W     RSVD_1                                          3'b000
+    22      R/W     RESERVED_6                                      1'b0
+    23      R/W     RESERVED_5                                      1'b0
+    24      R/W     RESERVED_4                                      1'b0
+    25      R/W     RESERVED_3                                      1'b0
+    26      R/W     RESERVED_2                                      1'b0
+    27      R/W     RESERVED_1                                      1'b0
+    30:28   R/W     RSVD                                            3'b000
+    31      R/W     RESERVED                                        1'b0
+ */
+typedef union _PCC_REG_TMETER_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t ENTRY_DELAY_CORE1_DEV_TMETER: 8;
+        uint32_t RESERVED_13: 1;
+        uint32_t RESERVED_12: 1;
+        uint32_t RESERVED_11: 1;
+        uint32_t RESERVED_10: 1;
+        uint32_t RESERVED_9: 1;
+        uint32_t RSVD_2: 3;
+        uint32_t RESERVED_8: 1;
+        uint32_t RESERVED_7: 1;
+        uint32_t TMETER_CLK_FORCE: 1;
+        uint32_t RSVD_1: 3;
+        uint32_t RESERVED_6: 1;
+        uint32_t RESERVED_5: 1;
+        uint32_t RESERVED_4: 1;
+        uint32_t RESERVED_3: 1;
+        uint32_t RESERVED_2: 1;
+        uint32_t RESERVED_1: 1;
+        uint32_t RSVD: 3;
+        uint32_t RESERVED: 1;
+    };
+} PCC_REG_TMETER_TYPE;
+
+/*0x4000_02b8 PCC_REG_TMETER*/
+#define PCC_REG_TMETER_ENTRY_DELAY_CORE1_DEV_TMETER_Pos                                          0U
+#define PCC_REG_TMETER_ENTRY_DELAY_CORE1_DEV_TMETER_Msk                                          (0xFFUL << PCC_REG_TMETER_ENTRY_DELAY_CORE1_DEV_TMETER_Pos)
+
+#define PCC_REG_TMETER_RESERVED_13_Pos                                                           8U
+#define PCC_REG_TMETER_RESERVED_13_Msk                                                           (0x1UL << PCC_REG_TMETER_RESERVED_13_Pos)
+
+#define PCC_REG_TMETER_RESERVED_12_Pos                                                           9U
+#define PCC_REG_TMETER_RESERVED_12_Msk                                                           (0x1UL << PCC_REG_TMETER_RESERVED_12_Pos)
+
+#define PCC_REG_TMETER_RESERVED_11_Pos                                                           10U
+#define PCC_REG_TMETER_RESERVED_11_Msk                                                           (0x1UL << PCC_REG_TMETER_RESERVED_11_Pos)
+
+#define PCC_REG_TMETER_RESERVED_10_Pos                                                           11U
+#define PCC_REG_TMETER_RESERVED_10_Msk                                                           (0x1UL << PCC_REG_TMETER_RESERVED_10_Pos)
+
+#define PCC_REG_TMETER_RESERVED_9_Pos                                                            12U
+#define PCC_REG_TMETER_RESERVED_9_Msk                                                            (0x1UL << PCC_REG_TMETER_RESERVED_9_Pos)
+
+#define PCC_REG_TMETER_RSVD_2_Pos                                                                13U
+#define PCC_REG_TMETER_RSVD_2_Msk                                                                (0x7UL << PCC_REG_TMETER_RSVD_2_Pos)
+
+#define PCC_REG_TMETER_RESERVED_8_Pos                                                            16U
+#define PCC_REG_TMETER_RESERVED_8_Msk                                                            (0x1UL << PCC_REG_TMETER_RESERVED_8_Pos)
+
+#define PCC_REG_TMETER_RESERVED_7_Pos                                                            17U
+#define PCC_REG_TMETER_RESERVED_7_Msk                                                            (0x1UL << PCC_REG_TMETER_RESERVED_7_Pos)
+
+#define PCC_REG_TMETER_TMETER_CLK_FORCE_Pos                                                      18U
+#define PCC_REG_TMETER_TMETER_CLK_FORCE_Msk                                                      (0x1UL << PCC_REG_TMETER_TMETER_CLK_FORCE_Pos)
+
+#define PCC_REG_TMETER_RSVD_1_Pos                                                                19U
+#define PCC_REG_TMETER_RSVD_1_Msk                                                                (0x7UL << PCC_REG_TMETER_RSVD_1_Pos)
+
+#define PCC_REG_TMETER_RESERVED_6_Pos                                                            22U
+#define PCC_REG_TMETER_RESERVED_6_Msk                                                            (0x1UL << PCC_REG_TMETER_RESERVED_6_Pos)
+
+#define PCC_REG_TMETER_RESERVED_5_Pos                                                            23U
+#define PCC_REG_TMETER_RESERVED_5_Msk                                                            (0x1UL << PCC_REG_TMETER_RESERVED_5_Pos)
+
+#define PCC_REG_TMETER_RESERVED_4_Pos                                                            24U
+#define PCC_REG_TMETER_RESERVED_4_Msk                                                            (0x1UL << PCC_REG_TMETER_RESERVED_4_Pos)
+
+#define PCC_REG_TMETER_RESERVED_3_Pos                                                            25U
+#define PCC_REG_TMETER_RESERVED_3_Msk                                                            (0x1UL << PCC_REG_TMETER_RESERVED_3_Pos)
+
+#define PCC_REG_TMETER_RESERVED_2_Pos                                                            26U
+#define PCC_REG_TMETER_RESERVED_2_Msk                                                            (0x1UL << PCC_REG_TMETER_RESERVED_2_Pos)
+
+#define PCC_REG_TMETER_RESERVED_1_Pos                                                            27U
+#define PCC_REG_TMETER_RESERVED_1_Msk                                                            (0x1UL << PCC_REG_TMETER_RESERVED_1_Pos)
+
+#define PCC_REG_TMETER_RSVD_Pos                                                                  28U
+#define PCC_REG_TMETER_RSVD_Msk                                                                  (0x7UL << PCC_REG_TMETER_RSVD_Pos)
+
+#define PCC_REG_TMETER_RESERVED_Pos                                                              31U
+#define PCC_REG_TMETER_RESERVED_Msk                                                              (0x1UL << PCC_REG_TMETER_RESERVED_Pos)
+
+/* 0x2BC    0x4000_02bc
+    7:0     R/W     ENTRY_DELAY_CORE1_DEV_TIMER1_PWM                8'b0
+    8       R/W     RESERVED_5                                      1'b1
+    9       R/W     RESERVED_4                                      1'b1
+    10      R/W     RESERVED_3                                      1'b1
+    11      R/W     RESERVED_2                                      1'b1
+    12      R/W     RESERVED_1                                      1'b1
+    13      R/W     RESERVED                                        1'b1
+    15:14   R/W     RSVD_1                                          2'b0
+    16      R/W     R_TIMER_PWM_9_CLK_SRC_SEL                       1'b0
+    17      R/W     R_TIMER_PWM_10_CLK_SRC_SEL                      1'b0
+    18      R/W     R_TIMER_PWM_11_CLK_SRC_SEL                      1'b0
+    21:19   R/W     R_TIMER_PWM_9_CLK_DIV                           3'h0
+    24:22   R/W     R_TIMER_PWM_10_CLK_DIV                          3'h0
+    27:25   R/W     R_TIMER_PWM_11_CLK_DIV                          3'h0
+    28      R/W     TIMER1_PWM_CH9_CLK_FORCE                        1'b0
+    29      R/W     TIMER1_PWM_CH10_CLK_FORCE                       1'b0
+    30      R/W     TIMER1_PWM_CH11_CLK_FORCE                       1'b0
+    31      R/W     RSVD                                            1'b0
+ */
+typedef union _PCC_REG_TIMER1_D_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t ENTRY_DELAY_CORE1_DEV_TIMER1_PWM: 8;
+        uint32_t RESERVED_5: 1;
+        uint32_t RESERVED_4: 1;
+        uint32_t RESERVED_3: 1;
+        uint32_t RESERVED_2: 1;
+        uint32_t RESERVED_1: 1;
+        uint32_t RESERVED: 1;
+        uint32_t RSVD_1: 2;
+        uint32_t R_TIMER_PWM_9_CLK_SRC_SEL: 1;
+        uint32_t R_TIMER_PWM_10_CLK_SRC_SEL: 1;
+        uint32_t R_TIMER_PWM_11_CLK_SRC_SEL: 1;
+        uint32_t R_TIMER_PWM_9_CLK_DIV: 3;
+        uint32_t R_TIMER_PWM_10_CLK_DIV: 3;
+        uint32_t R_TIMER_PWM_11_CLK_DIV: 3;
+        uint32_t TIMER1_PWM_CH9_CLK_FORCE: 1;
+        uint32_t TIMER1_PWM_CH10_CLK_FORCE: 1;
+        uint32_t TIMER1_PWM_CH11_CLK_FORCE: 1;
+        uint32_t RSVD: 1;
+    };
+} PCC_REG_TIMER1_D_TYPE;
+
+/*0x4000_02bc PCC_REG_TIMER1_D*/
+#define PCC_REG_TIMER1_D_ENTRY_DELAY_CORE1_DEV_TIMER1_PWM_Pos                                    0U
+#define PCC_REG_TIMER1_D_ENTRY_DELAY_CORE1_DEV_TIMER1_PWM_Msk                                    (0xFFUL << PCC_REG_TIMER1_D_ENTRY_DELAY_CORE1_DEV_TIMER1_PWM_Pos)
+
+#define PCC_REG_TIMER1_D_RESERVED_5_Pos                                                          8U
+#define PCC_REG_TIMER1_D_RESERVED_5_Msk                                                          (0x1UL << PCC_REG_TIMER1_D_RESERVED_5_Pos)
+
+#define PCC_REG_TIMER1_D_RESERVED_4_Pos                                                          9U
+#define PCC_REG_TIMER1_D_RESERVED_4_Msk                                                          (0x1UL << PCC_REG_TIMER1_D_RESERVED_4_Pos)
+
+#define PCC_REG_TIMER1_D_RESERVED_3_Pos                                                          10U
+#define PCC_REG_TIMER1_D_RESERVED_3_Msk                                                          (0x1UL << PCC_REG_TIMER1_D_RESERVED_3_Pos)
+
+#define PCC_REG_TIMER1_D_RESERVED_2_Pos                                                          11U
+#define PCC_REG_TIMER1_D_RESERVED_2_Msk                                                          (0x1UL << PCC_REG_TIMER1_D_RESERVED_2_Pos)
+
+#define PCC_REG_TIMER1_D_RESERVED_1_Pos                                                          12U
+#define PCC_REG_TIMER1_D_RESERVED_1_Msk                                                          (0x1UL << PCC_REG_TIMER1_D_RESERVED_1_Pos)
+
+#define PCC_REG_TIMER1_D_RESERVED_Pos                                                            13U
+#define PCC_REG_TIMER1_D_RESERVED_Msk                                                            (0x1UL << PCC_REG_TIMER1_D_RESERVED_Pos)
+
+#define PCC_REG_TIMER1_D_RSVD_1_Pos                                                              14U
+#define PCC_REG_TIMER1_D_RSVD_1_Msk                                                              (0x3UL << PCC_REG_TIMER1_D_RSVD_1_Pos)
+
+#define PCC_REG_TIMER1_D_R_TIMER_PWM_9_CLK_SRC_SEL_Pos                                           16U
+#define PCC_REG_TIMER1_D_R_TIMER_PWM_9_CLK_SRC_SEL_Msk                                           (0x1UL << PCC_REG_TIMER1_D_R_TIMER_PWM_9_CLK_SRC_SEL_Pos)
+
+#define PCC_REG_TIMER1_D_R_TIMER_PWM_10_CLK_SRC_SEL_Pos                                          17U
+#define PCC_REG_TIMER1_D_R_TIMER_PWM_10_CLK_SRC_SEL_Msk                                          (0x1UL << PCC_REG_TIMER1_D_R_TIMER_PWM_10_CLK_SRC_SEL_Pos)
+
+#define PCC_REG_TIMER1_D_R_TIMER_PWM_11_CLK_SRC_SEL_Pos                                          18U
+#define PCC_REG_TIMER1_D_R_TIMER_PWM_11_CLK_SRC_SEL_Msk                                          (0x1UL << PCC_REG_TIMER1_D_R_TIMER_PWM_11_CLK_SRC_SEL_Pos)
+
+#define PCC_REG_TIMER1_D_R_TIMER_PWM_9_CLK_DIV_Pos                                               19U
+#define PCC_REG_TIMER1_D_R_TIMER_PWM_9_CLK_DIV_Msk                                               (0x7UL << PCC_REG_TIMER1_D_R_TIMER_PWM_9_CLK_DIV_Pos)
+
+#define PCC_REG_TIMER1_D_R_TIMER_PWM_10_CLK_DIV_Pos                                              22U
+#define PCC_REG_TIMER1_D_R_TIMER_PWM_10_CLK_DIV_Msk                                              (0x7UL << PCC_REG_TIMER1_D_R_TIMER_PWM_10_CLK_DIV_Pos)
+
+#define PCC_REG_TIMER1_D_R_TIMER_PWM_11_CLK_DIV_Pos                                              25U
+#define PCC_REG_TIMER1_D_R_TIMER_PWM_11_CLK_DIV_Msk                                              (0x7UL << PCC_REG_TIMER1_D_R_TIMER_PWM_11_CLK_DIV_Pos)
+
+#define PCC_REG_TIMER1_D_TIMER1_PWM_CH9_CLK_FORCE_Pos                                            28U
+#define PCC_REG_TIMER1_D_TIMER1_PWM_CH9_CLK_FORCE_Msk                                            (0x1UL << PCC_REG_TIMER1_D_TIMER1_PWM_CH9_CLK_FORCE_Pos)
+
+#define PCC_REG_TIMER1_D_TIMER1_PWM_CH10_CLK_FORCE_Pos                                           29U
+#define PCC_REG_TIMER1_D_TIMER1_PWM_CH10_CLK_FORCE_Msk                                           (0x1UL << PCC_REG_TIMER1_D_TIMER1_PWM_CH10_CLK_FORCE_Pos)
+
+#define PCC_REG_TIMER1_D_TIMER1_PWM_CH11_CLK_FORCE_Pos                                           30U
+#define PCC_REG_TIMER1_D_TIMER1_PWM_CH11_CLK_FORCE_Msk                                           (0x1UL << PCC_REG_TIMER1_D_TIMER1_PWM_CH11_CLK_FORCE_Pos)
+
+#define PCC_REG_TIMER1_D_RSVD_Pos                                                                31U
+#define PCC_REG_TIMER1_D_RSVD_Msk                                                                (0x1UL << PCC_REG_TIMER1_D_RSVD_Pos)
+
+/* 0x8F0    0x4000_08f0
+    7:0     R/W     ENTRY_DELAY_CORE1_DEV_OSC80M_CAL                8'b0
+    8       R/W     RESERVED_10                                     1'b0
+    9       R/W     RESERVED_9                                      1'b1
+    10      R/W     RESERVED_8                                      1'b1
+    11      R/W     RESERVED_7                                      1'b1
+    12      R/W     RESERVED_6                                      1'b1
+    15:13   R/W     RESERVED_5                                      3'b0
+    16      R/W     CAL80M_CLK_FORCE                                1'b0
+    19:17   R/W     RSVD                                            3'b0
+    20      R/W     RESERVED_4                                      1'b0
+    21      R/W     RESERVED_3                                      1'b0
+    23:22   R/W     RESERVED_2                                      2'b0
+    24      R/W     RESERVED_1                                      1'b0
+    31:25   R/W     RESERVED                                        7'b0
+ */
+typedef union _PCC_REG_CAL80M_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t ENTRY_DELAY_CORE1_DEV_OSC80M_CAL: 8;
+        uint32_t RESERVED_10: 1;
+        uint32_t RESERVED_9: 1;
+        uint32_t RESERVED_8: 1;
+        uint32_t RESERVED_7: 1;
+        uint32_t RESERVED_6: 1;
+        uint32_t RESERVED_5: 3;
+        uint32_t CAL80M_CLK_FORCE: 1;
+        uint32_t RSVD: 3;
+        uint32_t RESERVED_4: 1;
+        uint32_t RESERVED_3: 1;
+        uint32_t RESERVED_2: 2;
+        uint32_t RESERVED_1: 1;
+        uint32_t RESERVED: 7;
+    };
+} PCC_REG_CAL80M_TYPE;
+
+/*0x4000_08f0 PCC_REG_CAL80M*/
+#define PCC_REG_CAL80M_ENTRY_DELAY_CORE1_DEV_OSC80M_CAL_Pos                                      0U
+#define PCC_REG_CAL80M_ENTRY_DELAY_CORE1_DEV_OSC80M_CAL_Msk                                      (0xFFUL << PCC_REG_CAL80M_ENTRY_DELAY_CORE1_DEV_OSC80M_CAL_Pos)
+
+#define PCC_REG_CAL80M_RESERVED_10_Pos                                                           8U
+#define PCC_REG_CAL80M_RESERVED_10_Msk                                                           (0x1UL << PCC_REG_CAL80M_RESERVED_10_Pos)
+
+#define PCC_REG_CAL80M_RESERVED_9_Pos                                                            9U
+#define PCC_REG_CAL80M_RESERVED_9_Msk                                                            (0x1UL << PCC_REG_CAL80M_RESERVED_9_Pos)
+
+#define PCC_REG_CAL80M_RESERVED_8_Pos                                                            10U
+#define PCC_REG_CAL80M_RESERVED_8_Msk                                                            (0x1UL << PCC_REG_CAL80M_RESERVED_8_Pos)
+
+#define PCC_REG_CAL80M_RESERVED_7_Pos                                                            11U
+#define PCC_REG_CAL80M_RESERVED_7_Msk                                                            (0x1UL << PCC_REG_CAL80M_RESERVED_7_Pos)
+
+#define PCC_REG_CAL80M_RESERVED_6_Pos                                                            12U
+#define PCC_REG_CAL80M_RESERVED_6_Msk                                                            (0x1UL << PCC_REG_CAL80M_RESERVED_6_Pos)
+
+#define PCC_REG_CAL80M_RESERVED_5_Pos                                                            13U
+#define PCC_REG_CAL80M_RESERVED_5_Msk                                                            (0x7UL << PCC_REG_CAL80M_RESERVED_5_Pos)
+
+#define PCC_REG_CAL80M_CAL80M_CLK_FORCE_Pos                                                      16U
+#define PCC_REG_CAL80M_CAL80M_CLK_FORCE_Msk                                                      (0x1UL << PCC_REG_CAL80M_CAL80M_CLK_FORCE_Pos)
+
+#define PCC_REG_CAL80M_RSVD_Pos                                                                  17U
+#define PCC_REG_CAL80M_RSVD_Msk                                                                  (0x7UL << PCC_REG_CAL80M_RSVD_Pos)
+
+#define PCC_REG_CAL80M_RESERVED_4_Pos                                                            20U
+#define PCC_REG_CAL80M_RESERVED_4_Msk                                                            (0x1UL << PCC_REG_CAL80M_RESERVED_4_Pos)
+
+#define PCC_REG_CAL80M_RESERVED_3_Pos                                                            21U
+#define PCC_REG_CAL80M_RESERVED_3_Msk                                                            (0x1UL << PCC_REG_CAL80M_RESERVED_3_Pos)
+
+#define PCC_REG_CAL80M_RESERVED_2_Pos                                                            22U
+#define PCC_REG_CAL80M_RESERVED_2_Msk                                                            (0x3UL << PCC_REG_CAL80M_RESERVED_2_Pos)
+
+#define PCC_REG_CAL80M_RESERVED_1_Pos                                                            24U
+#define PCC_REG_CAL80M_RESERVED_1_Msk                                                            (0x1UL << PCC_REG_CAL80M_RESERVED_1_Pos)
+
+#define PCC_REG_CAL80M_RESERVED_Pos                                                              25U
+#define PCC_REG_CAL80M_RESERVED_Msk                                                              (0x7FUL << PCC_REG_CAL80M_RESERVED_Pos)
+
+/* 0x8F4    0x4000_08f4
+    7:0     R/W     ENTRY_DELAY_CORE1_DEV_OSC10M_CAL                8'b0
+    8       R/W     RESERVED_10                                     1'b0
+    9       R/W     RESERVED_9                                      1'b0
+    10      R/W     RESERVED_8                                      1'b1
+    11      R/W     RESERVED_7                                      1'b1
+    12      R/W     RESERVED_6                                      1'b1
+    15:13   R/W     RESERVED_5                                      3'b0
+    16      R/W     CAL10M_CLK_FORCE                                1'b0
+    19:17   R/W     RSVD                                            3'h0
+    20      R/W     RESERVED_4                                      1'b0
+    21      R/W     RESERVED_3                                      1'b0
+    23:22   R/W     RESERVED_2                                      2'b0
+    24      R/W     RESERVED_1                                      1'b0
+    31:25   R/W     RESERVED                                        7'b0
+ */
+typedef union _PCC_REG_CAL10M_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t ENTRY_DELAY_CORE1_DEV_OSC10M_CAL: 8;
+        uint32_t RESERVED_10: 1;
+        uint32_t RESERVED_9: 1;
+        uint32_t RESERVED_8: 1;
+        uint32_t RESERVED_7: 1;
+        uint32_t RESERVED_6: 1;
+        uint32_t RESERVED_5: 3;
+        uint32_t CAL10M_CLK_FORCE: 1;
+        uint32_t RSVD: 3;
+        uint32_t RESERVED_4: 1;
+        uint32_t RESERVED_3: 1;
+        uint32_t RESERVED_2: 2;
+        uint32_t RESERVED_1: 1;
+        uint32_t RESERVED: 7;
+    };
+} PCC_REG_CAL10M_TYPE;
+
+/*0x4000_08f4 PCC_REG_CAL10M*/
+#define PCC_REG_CAL10M_ENTRY_DELAY_CORE1_DEV_OSC10M_CAL_Pos                                      0U
+#define PCC_REG_CAL10M_ENTRY_DELAY_CORE1_DEV_OSC10M_CAL_Msk                                      (0xFFUL << PCC_REG_CAL10M_ENTRY_DELAY_CORE1_DEV_OSC10M_CAL_Pos)
+
+#define PCC_REG_CAL10M_RESERVED_10_Pos                                                           8U
+#define PCC_REG_CAL10M_RESERVED_10_Msk                                                           (0x1UL << PCC_REG_CAL10M_RESERVED_10_Pos)
+
+#define PCC_REG_CAL10M_RESERVED_9_Pos                                                            9U
+#define PCC_REG_CAL10M_RESERVED_9_Msk                                                            (0x1UL << PCC_REG_CAL10M_RESERVED_9_Pos)
+
+#define PCC_REG_CAL10M_RESERVED_8_Pos                                                            10U
+#define PCC_REG_CAL10M_RESERVED_8_Msk                                                            (0x1UL << PCC_REG_CAL10M_RESERVED_8_Pos)
+
+#define PCC_REG_CAL10M_RESERVED_7_Pos                                                            11U
+#define PCC_REG_CAL10M_RESERVED_7_Msk                                                            (0x1UL << PCC_REG_CAL10M_RESERVED_7_Pos)
+
+#define PCC_REG_CAL10M_RESERVED_6_Pos                                                            12U
+#define PCC_REG_CAL10M_RESERVED_6_Msk                                                            (0x1UL << PCC_REG_CAL10M_RESERVED_6_Pos)
+
+#define PCC_REG_CAL10M_RESERVED_5_Pos                                                            13U
+#define PCC_REG_CAL10M_RESERVED_5_Msk                                                            (0x7UL << PCC_REG_CAL10M_RESERVED_5_Pos)
+
+#define PCC_REG_CAL10M_CAL10M_CLK_FORCE_Pos                                                      16U
+#define PCC_REG_CAL10M_CAL10M_CLK_FORCE_Msk                                                      (0x1UL << PCC_REG_CAL10M_CAL10M_CLK_FORCE_Pos)
+
+#define PCC_REG_CAL10M_RSVD_Pos                                                                  17U
+#define PCC_REG_CAL10M_RSVD_Msk                                                                  (0x7UL << PCC_REG_CAL10M_RSVD_Pos)
+
+#define PCC_REG_CAL10M_RESERVED_4_Pos                                                            20U
+#define PCC_REG_CAL10M_RESERVED_4_Msk                                                            (0x1UL << PCC_REG_CAL10M_RESERVED_4_Pos)
+
+#define PCC_REG_CAL10M_RESERVED_3_Pos                                                            21U
+#define PCC_REG_CAL10M_RESERVED_3_Msk                                                            (0x1UL << PCC_REG_CAL10M_RESERVED_3_Pos)
+
+#define PCC_REG_CAL10M_RESERVED_2_Pos                                                            22U
+#define PCC_REG_CAL10M_RESERVED_2_Msk                                                            (0x3UL << PCC_REG_CAL10M_RESERVED_2_Pos)
+
+#define PCC_REG_CAL10M_RESERVED_1_Pos                                                            24U
+#define PCC_REG_CAL10M_RESERVED_1_Msk                                                            (0x1UL << PCC_REG_CAL10M_RESERVED_1_Pos)
+
+#define PCC_REG_CAL10M_RESERVED_Pos                                                              25U
+#define PCC_REG_CAL10M_RESERVED_Msk                                                              (0x7FUL << PCC_REG_CAL10M_RESERVED_Pos)
+
+/* 0x8F8    0x4000_08f8
+    7:0     R/W     ENTRY_DELAY_CORE1_DEV_VDREG                     8'b0
+    8       R/W     RESERVED_8                                      1'b0
+    9       R/W     RESERVED_7                                      1'b0
+    10      R/W     RESERVED_6                                      1'b0
+    11      R/W     RESERVED_5                                      1'b1
+    12      R/W     RESERVED_4                                      1'b1
+    15:13   R/W     RESERVED_3                                      3'b0
+    16      R/W     VDREG_CLK_FORCE                                 1'b0
+    17      R/W     RESERVED_2                                      1'b0
+    18      R/W     RESERVED_1                                      1'b0
+    31:19   R/W     RESERVED                                        13'b0
+ */
+typedef union _PCC_REG_VDREG_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t ENTRY_DELAY_CORE1_DEV_VDREG: 8;
+        uint32_t RESERVED_8: 1;
+        uint32_t RESERVED_7: 1;
+        uint32_t RESERVED_6: 1;
+        uint32_t RESERVED_5: 1;
+        uint32_t RESERVED_4: 1;
+        uint32_t RESERVED_3: 3;
+        uint32_t VDREG_CLK_FORCE: 1;
+        uint32_t RESERVED_2: 1;
+        uint32_t RESERVED_1: 1;
+        uint32_t RESERVED: 13;
+    };
+} PCC_REG_VDREG_TYPE;
+
+/*0x4000_08f8 PCC_REG_VDREG*/
+#define PCC_REG_VDREG_ENTRY_DELAY_CORE1_DEV_VDREG_Pos                                            0U
+#define PCC_REG_VDREG_ENTRY_DELAY_CORE1_DEV_VDREG_Msk                                            (0xFFUL << PCC_REG_VDREG_ENTRY_DELAY_CORE1_DEV_VDREG_Pos)
+
+#define PCC_REG_VDREG_RESERVED_8_Pos                                                             8U
+#define PCC_REG_VDREG_RESERVED_8_Msk                                                             (0x1UL << PCC_REG_VDREG_RESERVED_8_Pos)
+
+#define PCC_REG_VDREG_RESERVED_7_Pos                                                             9U
+#define PCC_REG_VDREG_RESERVED_7_Msk                                                             (0x1UL << PCC_REG_VDREG_RESERVED_7_Pos)
+
+#define PCC_REG_VDREG_RESERVED_6_Pos                                                             10U
+#define PCC_REG_VDREG_RESERVED_6_Msk                                                             (0x1UL << PCC_REG_VDREG_RESERVED_6_Pos)
+
+#define PCC_REG_VDREG_RESERVED_5_Pos                                                             11U
+#define PCC_REG_VDREG_RESERVED_5_Msk                                                             (0x1UL << PCC_REG_VDREG_RESERVED_5_Pos)
+
+#define PCC_REG_VDREG_RESERVED_4_Pos                                                             12U
+#define PCC_REG_VDREG_RESERVED_4_Msk                                                             (0x1UL << PCC_REG_VDREG_RESERVED_4_Pos)
+
+#define PCC_REG_VDREG_RESERVED_3_Pos                                                             13U
+#define PCC_REG_VDREG_RESERVED_3_Msk                                                             (0x7UL << PCC_REG_VDREG_RESERVED_3_Pos)
+
+#define PCC_REG_VDREG_VDREG_CLK_FORCE_Pos                                                        16U
+#define PCC_REG_VDREG_VDREG_CLK_FORCE_Msk                                                        (0x1UL << PCC_REG_VDREG_VDREG_CLK_FORCE_Pos)
+
+#define PCC_REG_VDREG_RESERVED_2_Pos                                                             17U
+#define PCC_REG_VDREG_RESERVED_2_Msk                                                             (0x1UL << PCC_REG_VDREG_RESERVED_2_Pos)
+
+#define PCC_REG_VDREG_RESERVED_1_Pos                                                             18U
+#define PCC_REG_VDREG_RESERVED_1_Msk                                                             (0x1UL << PCC_REG_VDREG_RESERVED_1_Pos)
+
+#define PCC_REG_VDREG_RESERVED_Pos                                                               19U
+#define PCC_REG_VDREG_RESERVED_Msk                                                               (0x1FFFUL << PCC_REG_VDREG_RESERVED_Pos)
+
+/* 0x8FC    0x4000_08fc
+    7:0     R/W     ENTRY_DELAY_CM33                                8'b0
+    8       R/W     RESERVED_6                                      1'b0
+    9       R/W     RESERVED_5                                      1'b0
+    10      R/W     RESERVED_4                                      1'b0
+    11      R/W     RESERVED_3                                      1'b1
+    12      R/W     RESERVED_2                                      1'b1
+    15:13   R/W     RESERVED_1                                      3'b0
+    16      R/W     CM33_CLK_FORCE                                  1'b0
+    31:17   R/W     RESERVED                                        15'b0
+ */
+typedef union _PCC_REG_CPU_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t ENTRY_DELAY_CM33: 8;
+        uint32_t RESERVED_6: 1;
+        uint32_t RESERVED_5: 1;
+        uint32_t RESERVED_4: 1;
+        uint32_t RESERVED_3: 1;
+        uint32_t RESERVED_2: 1;
+        uint32_t RESERVED_1: 3;
+        uint32_t CM33_CLK_FORCE: 1;
+        uint32_t RESERVED: 15;
+    };
+} PCC_REG_CPU_TYPE;
+
+/*0x4000_08fc PCC_REG_CPU*/
+#define PCC_REG_CPU_ENTRY_DELAY_CM33_Pos                                                         0U
+#define PCC_REG_CPU_ENTRY_DELAY_CM33_Msk                                                         (0xFFUL << PCC_REG_CPU_ENTRY_DELAY_CM33_Pos)
+
+#define PCC_REG_CPU_RESERVED_6_Pos                                                               8U
+#define PCC_REG_CPU_RESERVED_6_Msk                                                               (0x1UL << PCC_REG_CPU_RESERVED_6_Pos)
+
+#define PCC_REG_CPU_RESERVED_5_Pos                                                               9U
+#define PCC_REG_CPU_RESERVED_5_Msk                                                               (0x1UL << PCC_REG_CPU_RESERVED_5_Pos)
+
+#define PCC_REG_CPU_RESERVED_4_Pos                                                               10U
+#define PCC_REG_CPU_RESERVED_4_Msk                                                               (0x1UL << PCC_REG_CPU_RESERVED_4_Pos)
+
+#define PCC_REG_CPU_RESERVED_3_Pos                                                               11U
+#define PCC_REG_CPU_RESERVED_3_Msk                                                               (0x1UL << PCC_REG_CPU_RESERVED_3_Pos)
+
+#define PCC_REG_CPU_RESERVED_2_Pos                                                               12U
+#define PCC_REG_CPU_RESERVED_2_Msk                                                               (0x1UL << PCC_REG_CPU_RESERVED_2_Pos)
+
+#define PCC_REG_CPU_RESERVED_1_Pos                                                               13U
+#define PCC_REG_CPU_RESERVED_1_Msk                                                               (0x7UL << PCC_REG_CPU_RESERVED_1_Pos)
+
+#define PCC_REG_CPU_CM33_CLK_FORCE_Pos                                                           16U
+#define PCC_REG_CPU_CM33_CLK_FORCE_Msk                                                           (0x1UL << PCC_REG_CPU_CM33_CLK_FORCE_Pos)
+
+#define PCC_REG_CPU_RESERVED_Pos                                                                 17U
+#define PCC_REG_CPU_RESERVED_Msk                                                                 (0x7FFFUL << PCC_REG_CPU_RESERVED_Pos)
+
+/* 0x900    0x4000_0900
+    7:0     R/W     ENTRY_DELAY_CORE1_DEV_SYSON                     8'b0
+    15:8    R/W     RESERVED_1                                      8'b0
+    16      R/W     SYSON_CLK_FORCE                                 1'b0
+    17      R/W     RFC_MANU_SEL                                    1'b0
+    18      R/W     RFC_MANU_DAT                                    1'b0
+    31:19   R/W     RESERVED                                        13'b0
+ */
+typedef union _PCC_REG_SYSON_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t ENTRY_DELAY_CORE1_DEV_SYSON: 8;
+        uint32_t RESERVED_1: 8;
+        uint32_t SYSON_CLK_FORCE: 1;
+        uint32_t RFC_MANU_SEL: 1;
+        uint32_t RFC_MANU_DAT: 1;
+        uint32_t RESERVED: 13;
+    };
+} PCC_REG_SYSON_TYPE;
+
+/*0x4000_0900 PCC_REG_SYSON*/
+#define PCC_REG_SYSON_ENTRY_DELAY_CORE1_DEV_SYSON_Pos                                            0U
+#define PCC_REG_SYSON_ENTRY_DELAY_CORE1_DEV_SYSON_Msk                                            (0xFFUL << PCC_REG_SYSON_ENTRY_DELAY_CORE1_DEV_SYSON_Pos)
+
+#define PCC_REG_SYSON_RESERVED_1_Pos                                                             8U
+#define PCC_REG_SYSON_RESERVED_1_Msk                                                             (0xFFUL << PCC_REG_SYSON_RESERVED_1_Pos)
+
+#define PCC_REG_SYSON_SYSON_CLK_FORCE_Pos                                                        16U
+#define PCC_REG_SYSON_SYSON_CLK_FORCE_Msk                                                        (0x1UL << PCC_REG_SYSON_SYSON_CLK_FORCE_Pos)
+
+#define PCC_REG_SYSON_RFC_MANU_SEL_Pos                                                           17U
+#define PCC_REG_SYSON_RFC_MANU_SEL_Msk                                                           (0x1UL << PCC_REG_SYSON_RFC_MANU_SEL_Pos)
+
+#define PCC_REG_SYSON_RFC_MANU_DAT_Pos                                                           18U
+#define PCC_REG_SYSON_RFC_MANU_DAT_Msk                                                           (0x1UL << PCC_REG_SYSON_RFC_MANU_DAT_Pos)
+
+#define PCC_REG_SYSON_RESERVED_Pos                                                               19U
+#define PCC_REG_SYSON_RESERVED_Msk                                                               (0x1FFFUL << PCC_REG_SYSON_RESERVED_Pos)
+
+/* 0x904    0x4000_0904
+    7:0     R/W     ENTRY_DELAY_CORE1_DEV_HCI                       8'b0
+    8       R/W     RESERVED_5                                      1'b0
+    9       R/W     RESERVED_4                                      1'b1
+    10      R/W     RESERVED_3                                      1'b1
+    11      R/W     RESERVED_2                                      1'b1
+    12      R/W     RESERVED_1                                      1'b1
+    15:13   R/W     RSVD                                            3'h0
+    16      R/W     HCI_CLK_FORCE                                   1'b0
+    31:17   R/W     RESERVED                                        15'b0
+ */
+typedef union _PCC_REG_HCI_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t ENTRY_DELAY_CORE1_DEV_HCI: 8;
+        uint32_t RESERVED_5: 1;
+        uint32_t RESERVED_4: 1;
+        uint32_t RESERVED_3: 1;
+        uint32_t RESERVED_2: 1;
+        uint32_t RESERVED_1: 1;
+        uint32_t RSVD: 3;
+        uint32_t HCI_CLK_FORCE: 1;
+        uint32_t RESERVED: 15;
+    };
+} PCC_REG_HCI_TYPE;
+
+/*0x4000_0904 PCC_REG_HCI*/
+#define PCC_REG_HCI_ENTRY_DELAY_CORE1_DEV_HCI_Pos                                                0U
+#define PCC_REG_HCI_ENTRY_DELAY_CORE1_DEV_HCI_Msk                                                (0xFFUL << PCC_REG_HCI_ENTRY_DELAY_CORE1_DEV_HCI_Pos)
+
+#define PCC_REG_HCI_RESERVED_5_Pos                                                               8U
+#define PCC_REG_HCI_RESERVED_5_Msk                                                               (0x1UL << PCC_REG_HCI_RESERVED_5_Pos)
+
+#define PCC_REG_HCI_RESERVED_4_Pos                                                               9U
+#define PCC_REG_HCI_RESERVED_4_Msk                                                               (0x1UL << PCC_REG_HCI_RESERVED_4_Pos)
+
+#define PCC_REG_HCI_RESERVED_3_Pos                                                               10U
+#define PCC_REG_HCI_RESERVED_3_Msk                                                               (0x1UL << PCC_REG_HCI_RESERVED_3_Pos)
+
+#define PCC_REG_HCI_RESERVED_2_Pos                                                               11U
+#define PCC_REG_HCI_RESERVED_2_Msk                                                               (0x1UL << PCC_REG_HCI_RESERVED_2_Pos)
+
+#define PCC_REG_HCI_RESERVED_1_Pos                                                               12U
+#define PCC_REG_HCI_RESERVED_1_Msk                                                               (0x1UL << PCC_REG_HCI_RESERVED_1_Pos)
+
+#define PCC_REG_HCI_RSVD_Pos                                                                     13U
+#define PCC_REG_HCI_RSVD_Msk                                                                     (0x7UL << PCC_REG_HCI_RSVD_Pos)
+
+#define PCC_REG_HCI_HCI_CLK_FORCE_Pos                                                            16U
+#define PCC_REG_HCI_HCI_CLK_FORCE_Msk                                                            (0x1UL << PCC_REG_HCI_HCI_CLK_FORCE_Pos)
+
+#define PCC_REG_HCI_RESERVED_Pos                                                                 17U
+#define PCC_REG_HCI_RESERVED_Msk                                                                 (0x7FFFUL << PCC_REG_HCI_RESERVED_Pos)
+
+/* 0x908    0x4000_0908
+    7:0     R/W     ENTRY_DELAY_CORE1_DEV_RFC                       8'b0
+    15:8    R/W     ENTRY_DELAY_CORE1_DEV_BLUEWIZ_BRIDGE            8'b0
+    23:16   R/W     ENTRY_DELAY_CORE1_DEV_2P4G_MAC                  8'b0
+    31:24   R/W     ENTRY_DELAY_CORE1_DEV_BTMAC                     8'b0
+ */
+typedef union _PCC_REG_BT_OTHER0_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t ENTRY_DELAY_CORE1_DEV_RFC: 8;
+        uint32_t ENTRY_DELAY_CORE1_DEV_BLUEWIZ_BRIDGE: 8;
+        uint32_t ENTRY_DELAY_CORE1_DEV_2P4G_MAC: 8;
+        uint32_t ENTRY_DELAY_CORE1_DEV_BTMAC: 8;
+    };
+} PCC_REG_BT_OTHER0_TYPE;
+
+/*0x4000_0908 PCC_REG_BT_OTHER0*/
+#define PCC_REG_BT_OTHER0_ENTRY_DELAY_CORE1_DEV_RFC_Pos                                          0U
+#define PCC_REG_BT_OTHER0_ENTRY_DELAY_CORE1_DEV_RFC_Msk                                          (0xFFUL << PCC_REG_BT_OTHER0_ENTRY_DELAY_CORE1_DEV_RFC_Pos)
+
+#define PCC_REG_BT_OTHER0_ENTRY_DELAY_CORE1_DEV_BLUEWIZ_BRIDGE_Pos                               8U
+#define PCC_REG_BT_OTHER0_ENTRY_DELAY_CORE1_DEV_BLUEWIZ_BRIDGE_Msk                               (0xFFUL << PCC_REG_BT_OTHER0_ENTRY_DELAY_CORE1_DEV_BLUEWIZ_BRIDGE_Pos)
+
+#define PCC_REG_BT_OTHER0_ENTRY_DELAY_CORE1_DEV_2P4G_MAC_Pos                                     16U
+#define PCC_REG_BT_OTHER0_ENTRY_DELAY_CORE1_DEV_2P4G_MAC_Msk                                     (0xFFUL << PCC_REG_BT_OTHER0_ENTRY_DELAY_CORE1_DEV_2P4G_MAC_Pos)
+
+#define PCC_REG_BT_OTHER0_ENTRY_DELAY_CORE1_DEV_BTMAC_Pos                                        24U
+#define PCC_REG_BT_OTHER0_ENTRY_DELAY_CORE1_DEV_BTMAC_Msk                                        (0xFFUL << PCC_REG_BT_OTHER0_ENTRY_DELAY_CORE1_DEV_BTMAC_Pos)
+
+/* 0x90C    0x4000_090c
+    7:0     R/W     ENTRY_DELAY_CORE1_DEV_TIMER0_PCLK               8'b0
+    8       R/W     RESERVED_4                                      1'b0
+    9       R/W     RESERVED_3                                      1'b1
+    10      R/W     RESERVED_2                                      1'b1
+    21:11   R/W     RESERVED_1                                      11'b0
+    22      R/W     TIMER0_PCLK_CLK_FORCE                           1'b0
+    31:23   R/W     RESERVED                                        9'b0
+ */
+typedef union _PCC_REG_TIMER0_PCLK_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t ENTRY_DELAY_CORE1_DEV_TIMER0_PCLK: 8;
+        uint32_t RESERVED_4: 1;
+        uint32_t RESERVED_3: 1;
+        uint32_t RESERVED_2: 1;
+        uint32_t RESERVED_1: 11;
+        uint32_t TIMER0_PCLK_CLK_FORCE: 1;
+        uint32_t RESERVED: 9;
+    };
+} PCC_REG_TIMER0_PCLK_TYPE;
+
+/*0x4000_090c PCC_REG_TIMER0_PCLK*/
+#define PCC_REG_TIMER0_PCLK_ENTRY_DELAY_CORE1_DEV_TIMER0_PCLK_Pos                                0U
+#define PCC_REG_TIMER0_PCLK_ENTRY_DELAY_CORE1_DEV_TIMER0_PCLK_Msk                                (0xFFUL << PCC_REG_TIMER0_PCLK_ENTRY_DELAY_CORE1_DEV_TIMER0_PCLK_Pos)
+
+#define PCC_REG_TIMER0_PCLK_RESERVED_4_Pos                                                       8U
+#define PCC_REG_TIMER0_PCLK_RESERVED_4_Msk                                                       (0x1UL << PCC_REG_TIMER0_PCLK_RESERVED_4_Pos)
+
+#define PCC_REG_TIMER0_PCLK_RESERVED_3_Pos                                                       9U
+#define PCC_REG_TIMER0_PCLK_RESERVED_3_Msk                                                       (0x1UL << PCC_REG_TIMER0_PCLK_RESERVED_3_Pos)
+
+#define PCC_REG_TIMER0_PCLK_RESERVED_2_Pos                                                       10U
+#define PCC_REG_TIMER0_PCLK_RESERVED_2_Msk                                                       (0x1UL << PCC_REG_TIMER0_PCLK_RESERVED_2_Pos)
+
+#define PCC_REG_TIMER0_PCLK_RESERVED_1_Pos                                                       11U
+#define PCC_REG_TIMER0_PCLK_RESERVED_1_Msk                                                       (0x7FFUL << PCC_REG_TIMER0_PCLK_RESERVED_1_Pos)
+
+#define PCC_REG_TIMER0_PCLK_TIMER0_PCLK_CLK_FORCE_Pos                                            22U
+#define PCC_REG_TIMER0_PCLK_TIMER0_PCLK_CLK_FORCE_Msk                                            (0x1UL << PCC_REG_TIMER0_PCLK_TIMER0_PCLK_CLK_FORCE_Pos)
+
+#define PCC_REG_TIMER0_PCLK_RESERVED_Pos                                                         23U
+#define PCC_REG_TIMER0_PCLK_RESERVED_Msk                                                         (0x1FFUL << PCC_REG_TIMER0_PCLK_RESERVED_Pos)
+
+/* 0x910    0x4000_0910
+    7:0     R/W     ENTRY_DELAY_CORE1_DEV_TIMER1_PCLK               8'b0
+    8       R/W     RESERVED_4                                      1'b0
+    9       R/W     RESERVED_3                                      1'b1
+    10      R/W     RESERVED_2                                      1'b1
+    21:11   R/W     RESERVED_1                                      11'b0
+    22      R/W     TIMER1_PCLK_CLK_FORCE                           1'b0
+    31:23   R/W     RESERVED                                        9'b0
+ */
+typedef union _PCC_REG_TIMER1_PCLK_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t ENTRY_DELAY_CORE1_DEV_TIMER1_PCLK: 8;
+        uint32_t RESERVED_4: 1;
+        uint32_t RESERVED_3: 1;
+        uint32_t RESERVED_2: 1;
+        uint32_t RESERVED_1: 11;
+        uint32_t TIMER1_PCLK_CLK_FORCE: 1;
+        uint32_t RESERVED: 9;
+    };
+} PCC_REG_TIMER1_PCLK_TYPE;
+
+/*0x4000_0910 PCC_REG_TIMER1_PCLK*/
+#define PCC_REG_TIMER1_PCLK_ENTRY_DELAY_CORE1_DEV_TIMER1_PCLK_Pos                                0U
+#define PCC_REG_TIMER1_PCLK_ENTRY_DELAY_CORE1_DEV_TIMER1_PCLK_Msk                                (0xFFUL << PCC_REG_TIMER1_PCLK_ENTRY_DELAY_CORE1_DEV_TIMER1_PCLK_Pos)
+
+#define PCC_REG_TIMER1_PCLK_RESERVED_4_Pos                                                       8U
+#define PCC_REG_TIMER1_PCLK_RESERVED_4_Msk                                                       (0x1UL << PCC_REG_TIMER1_PCLK_RESERVED_4_Pos)
+
+#define PCC_REG_TIMER1_PCLK_RESERVED_3_Pos                                                       9U
+#define PCC_REG_TIMER1_PCLK_RESERVED_3_Msk                                                       (0x1UL << PCC_REG_TIMER1_PCLK_RESERVED_3_Pos)
+
+#define PCC_REG_TIMER1_PCLK_RESERVED_2_Pos                                                       10U
+#define PCC_REG_TIMER1_PCLK_RESERVED_2_Msk                                                       (0x1UL << PCC_REG_TIMER1_PCLK_RESERVED_2_Pos)
+
+#define PCC_REG_TIMER1_PCLK_RESERVED_1_Pos                                                       11U
+#define PCC_REG_TIMER1_PCLK_RESERVED_1_Msk                                                       (0x7FFUL << PCC_REG_TIMER1_PCLK_RESERVED_1_Pos)
+
+#define PCC_REG_TIMER1_PCLK_TIMER1_PCLK_CLK_FORCE_Pos                                            22U
+#define PCC_REG_TIMER1_PCLK_TIMER1_PCLK_CLK_FORCE_Msk                                            (0x1UL << PCC_REG_TIMER1_PCLK_TIMER1_PCLK_CLK_FORCE_Pos)
+
+#define PCC_REG_TIMER1_PCLK_RESERVED_Pos                                                         23U
+#define PCC_REG_TIMER1_PCLK_RESERVED_Msk                                                         (0x1FFUL << PCC_REG_TIMER1_PCLK_RESERVED_Pos)
+
+/* 0x914    0x4000_0914
+    7:0     R/W     ENTRY_DELAY_CORE1_DEV_ETIMER_PCLK               8'b0
+    8       R/W     RESERVED_4                                      1'b0
+    9       R/W     RESERVED_3                                      1'b1
+    10      R/W     RESERVED_2                                      1'b1
+    21:11   R/W     RESERVED_1                                      11'b0
+    22      R/W     ETIMER_PCLK_CLK_FORCE                           1'b0
+    31:23   R/W     RESERVED                                        9'b0
+ */
+typedef union _PCC_REG_ETIMER_PCLK_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t ENTRY_DELAY_CORE1_DEV_ETIMER_PCLK: 8;
+        uint32_t RESERVED_4: 1;
+        uint32_t RESERVED_3: 1;
+        uint32_t RESERVED_2: 1;
+        uint32_t RESERVED_1: 11;
+        uint32_t ETIMER_PCLK_CLK_FORCE: 1;
+        uint32_t RESERVED: 9;
+    };
+} PCC_REG_ETIMER_PCLK_TYPE;
+
+/*0x4000_0914 PCC_REG_ETIMER_PCLK*/
+#define PCC_REG_ETIMER_PCLK_ENTRY_DELAY_CORE1_DEV_ETIMER_PCLK_Pos                                0U
+#define PCC_REG_ETIMER_PCLK_ENTRY_DELAY_CORE1_DEV_ETIMER_PCLK_Msk                                (0xFFUL << PCC_REG_ETIMER_PCLK_ENTRY_DELAY_CORE1_DEV_ETIMER_PCLK_Pos)
+
+#define PCC_REG_ETIMER_PCLK_RESERVED_4_Pos                                                       8U
+#define PCC_REG_ETIMER_PCLK_RESERVED_4_Msk                                                       (0x1UL << PCC_REG_ETIMER_PCLK_RESERVED_4_Pos)
+
+#define PCC_REG_ETIMER_PCLK_RESERVED_3_Pos                                                       9U
+#define PCC_REG_ETIMER_PCLK_RESERVED_3_Msk                                                       (0x1UL << PCC_REG_ETIMER_PCLK_RESERVED_3_Pos)
+
+#define PCC_REG_ETIMER_PCLK_RESERVED_2_Pos                                                       10U
+#define PCC_REG_ETIMER_PCLK_RESERVED_2_Msk                                                       (0x1UL << PCC_REG_ETIMER_PCLK_RESERVED_2_Pos)
+
+#define PCC_REG_ETIMER_PCLK_RESERVED_1_Pos                                                       11U
+#define PCC_REG_ETIMER_PCLK_RESERVED_1_Msk                                                       (0x7FFUL << PCC_REG_ETIMER_PCLK_RESERVED_1_Pos)
+
+#define PCC_REG_ETIMER_PCLK_ETIMER_PCLK_CLK_FORCE_Pos                                            22U
+#define PCC_REG_ETIMER_PCLK_ETIMER_PCLK_CLK_FORCE_Msk                                            (0x1UL << PCC_REG_ETIMER_PCLK_ETIMER_PCLK_CLK_FORCE_Pos)
+
+#define PCC_REG_ETIMER_PCLK_RESERVED_Pos                                                         23U
+#define PCC_REG_ETIMER_PCLK_RESERVED_Msk                                                         (0x1FFUL << PCC_REG_ETIMER_PCLK_RESERVED_Pos)
+
+/* 0x918    0x4000_0918
+    7:0     R/W     ENTRY_DELAY_CORE1_DEV_OSC128K_CAL               8'b0
+    31:8    R/W     RESERVED                                        24'b0
+ */
+typedef union _PCC_REG_OSC128K_CAL_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t ENTRY_DELAY_CORE1_DEV_OSC128K_CAL: 8;
+        uint32_t RESERVED: 24;
+    };
+} PCC_REG_OSC128K_CAL_TYPE;
+
+/*0x4000_0918 PCC_REG_OSC128K_CAL*/
+#define PCC_REG_OSC128K_CAL_ENTRY_DELAY_CORE1_DEV_OSC128K_CAL_Pos                                0U
+#define PCC_REG_OSC128K_CAL_ENTRY_DELAY_CORE1_DEV_OSC128K_CAL_Msk                                (0xFFUL << PCC_REG_OSC128K_CAL_ENTRY_DELAY_CORE1_DEV_OSC128K_CAL_Pos)
+
+#define PCC_REG_OSC128K_CAL_RESERVED_Pos                                                         8U
+#define PCC_REG_OSC128K_CAL_RESERVED_Msk                                                         (0xFFFFFFUL << PCC_REG_OSC128K_CAL_RESERVED_Pos)
+
+/* 0x91C    0x4000_091c
+    7:0     R/W     ENTRY_DELAY_RXI300                              8'b0
+    31:8    R/W     RESERVED                                        24'b0
+ */
+typedef union _PCC_REG_RXI300_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t ENTRY_DELAY_RXI300: 8;
+        uint32_t RESERVED: 24;
+    };
+} PCC_REG_RXI300_TYPE;
+
+/*0x4000_091c PCC_REG_RXI300*/
+#define PCC_REG_RXI300_ENTRY_DELAY_RXI300_Pos                                                    0U
+#define PCC_REG_RXI300_ENTRY_DELAY_RXI300_Msk                                                    (0xFFUL << PCC_REG_RXI300_ENTRY_DELAY_RXI300_Pos)
+
+#define PCC_REG_RXI300_RESERVED_Pos                                                              8U
+#define PCC_REG_RXI300_RESERVED_Msk                                                              (0xFFFFFFUL << PCC_REG_RXI300_RESERVED_Pos)
+
+/* 0x920    0x4000_0920
+    7:0     R/W     ENTRY_DELAY_AON_DEB_TOP                         8'b0
+    31:8    R/W     RESERVED                                        24'b0
+ */
+typedef union _PCC_REG_AON_DEB_TOP_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t ENTRY_DELAY_AON_DEB_TOP: 8;
+        uint32_t RESERVED: 24;
+    };
+} PCC_REG_AON_DEB_TOP_TYPE;
+
+/*0x4000_0920 PCC_REG_AON_DEB_TOP*/
+#define PCC_REG_AON_DEB_TOP_ENTRY_DELAY_AON_DEB_TOP_Pos                                          0U
+#define PCC_REG_AON_DEB_TOP_ENTRY_DELAY_AON_DEB_TOP_Msk                                          (0xFFUL << PCC_REG_AON_DEB_TOP_ENTRY_DELAY_AON_DEB_TOP_Pos)
+
+#define PCC_REG_AON_DEB_TOP_RESERVED_Pos                                                         8U
+#define PCC_REG_AON_DEB_TOP_RESERVED_Msk                                                         (0xFFFFFFUL << PCC_REG_AON_DEB_TOP_RESERVED_Pos)
+
+/* 0x924    0x4000_0924
+    7:0     R/W     ENTRY_DELAY_CORE1_DEV_OSC128K                   8'b0
+    15:8    R/W     ENTRY_DELAY_CORE1_DEV_OSC10M                    8'b0
+    31:16   R/W     RESERVED                                        16'b0
+ */
+typedef union _PCC_REG_OTHERS_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t ENTRY_DELAY_CORE1_DEV_OSC128K: 8;
+        uint32_t ENTRY_DELAY_CORE1_DEV_OSC10M: 8;
+        uint32_t RESERVED: 16;
+    };
+} PCC_REG_OTHERS_TYPE;
+
+/*0x4000_0924 PCC_REG_OTHERS*/
+#define PCC_REG_OTHERS_ENTRY_DELAY_CORE1_DEV_OSC128K_Pos                                         0U
+#define PCC_REG_OTHERS_ENTRY_DELAY_CORE1_DEV_OSC128K_Msk                                         (0xFFUL << PCC_REG_OTHERS_ENTRY_DELAY_CORE1_DEV_OSC128K_Pos)
+
+#define PCC_REG_OTHERS_ENTRY_DELAY_CORE1_DEV_OSC10M_Pos                                          8U
+#define PCC_REG_OTHERS_ENTRY_DELAY_CORE1_DEV_OSC10M_Msk                                          (0xFFUL << PCC_REG_OTHERS_ENTRY_DELAY_CORE1_DEV_OSC10M_Pos)
+
+#define PCC_REG_OTHERS_RESERVED_Pos                                                              16U
+#define PCC_REG_OTHERS_RESERVED_Msk                                                              (0xFFFFUL << PCC_REG_OTHERS_RESERVED_Pos)
+
+/* 0x3C4    0x4000_03c4
+    0       R/W     R_PON_FEN_VDREG                                 1'b0
+    1       R/W     R_PON_FEN_SYSON                                 1'b1
+    2       R/W     R_PON_FEN_TMETER                                1'b1
+    3       R/W     R_PON_FEN_DSS                                   1'b0
+    4       R/W     R_PON_FEN_CODEC                                 1'b0
+    5       R/W     R_PON_FEN_UART2                                 1'b0
+    6       R/W     R_PON_FEN_UART1                                 1'b0
+    7       R/W     R_PON_FEN_UART0                                 1'b0
+    8       R/W     R_PON_FEN_GPIO_DBNC_2P4G                        1'b0
+    9       R/W     R_PON_FEN_CAN                                   1'b0
+    10      R/W     R_PON_FEN_EFLASH                                1'b1
+    11      R/W     R_PON_FEN_SPI3W                                 1'b0
+    12      R/W     R_PON_FEN_KEYSCAN                               1'b0
+    13      R/W     R_PON_FEN_I2C1                                  1'b0
+    14      R/W     R_PON_FEN_I2C0                                  1'b0
+    15      R/W     R_PON_FEN_ADC                                   1'b0
+    16      R/W     R_PON_FEN_USB                                   1'b0
+    17      R/W     R_PON_FEN_TIMER_2_PWM                           1'b0
+    18      R/W     R_PON_FEN_TIMER_2                               1'b0
+    19      R/W     R_PON_FEN_TIMER_1                               1'b0
+    20      R/W     R_PON_FEN_TIMER_0                               1'b0
+    21      R/W     R_PON_FEN_I2S                                   1'b0
+    22      R/W     R_PON_FEN_SPI2                                  1'b0
+    23      R/W     R_PON_FEN_SPI1                                  1'b0
+    24      R/W     R_PON_FEN_SPI0                                  1'b0
+    25      R/W     R_PON_FEN_FMC0                                  1'b0
+    26      R/W     R_PON_FEN_DMA0                                  1'b0
+    27      R/W     R_PON_FEN_MODEMRFCPI                            1'b0
+    28      R/W     R_PON_FEN_SHA256                                1'b0
+    29      R/W     R_PON_FEN_AES                                   1'b0
+    30      R/W     R_PON_FEN_CORE_WDT                              1'b0
+    31      R/W     R_PON_FEN_RNG                                   1'b0
+ */
+typedef union _PCC_REG_PERION_CLK_VPON_REG0X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t R_PON_FEN_VDREG: 1;
+        uint32_t R_PON_FEN_SYSON: 1;
+        uint32_t R_PON_FEN_TMETER: 1;
+        uint32_t R_PON_FEN_DSS: 1;
+        uint32_t R_PON_FEN_CODEC: 1;
+        uint32_t R_PON_FEN_UART2: 1;
+        uint32_t R_PON_FEN_UART1: 1;
+        uint32_t R_PON_FEN_UART0: 1;
+        uint32_t R_PON_FEN_GPIO_DBNC_2P4G: 1;
+        uint32_t R_PON_FEN_CAN: 1;
+        uint32_t R_PON_FEN_EFLASH: 1;
+        uint32_t R_PON_FEN_SPI3W: 1;
+        uint32_t R_PON_FEN_KEYSCAN: 1;
+        uint32_t R_PON_FEN_I2C1: 1;
+        uint32_t R_PON_FEN_I2C0: 1;
+        uint32_t R_PON_FEN_ADC: 1;
+        uint32_t R_PON_FEN_USB: 1;
+        uint32_t R_PON_FEN_TIMER_2_PWM: 1;
+        uint32_t R_PON_FEN_TIMER_2: 1;
+        uint32_t R_PON_FEN_TIMER_1: 1;
+        uint32_t R_PON_FEN_TIMER_0: 1;
+        uint32_t R_PON_FEN_I2S: 1;
+        uint32_t R_PON_FEN_SPI2: 1;
+        uint32_t R_PON_FEN_SPI1: 1;
+        uint32_t R_PON_FEN_SPI0: 1;
+        uint32_t R_PON_FEN_FMC0: 1;
+        uint32_t R_PON_FEN_DMA0: 1;
+        uint32_t R_PON_FEN_MODEMRFCPI: 1;
+        uint32_t R_PON_FEN_SHA256: 1;
+        uint32_t R_PON_FEN_AES: 1;
+        uint32_t R_PON_FEN_CORE_WDT: 1;
+        uint32_t R_PON_FEN_RNG: 1;
+    };
+} PCC_REG_PERION_CLK_VPON_REG0X_TYPE;
+
+/*0x4000_03c4 PCC_REG_PERION_CLK_VPON_REG0X*/
+#define PCC_REG_PERION_CLK_VPON_REG0X_R_PON_FEN_VDREG_Pos                                        0U
+#define PCC_REG_PERION_CLK_VPON_REG0X_R_PON_FEN_VDREG_Msk                                        (0x1UL << PCC_REG_PERION_CLK_VPON_REG0X_R_PON_FEN_VDREG_Pos)
+
+#define PCC_REG_PERION_CLK_VPON_REG0X_R_PON_FEN_SYSON_Pos                                        1U
+#define PCC_REG_PERION_CLK_VPON_REG0X_R_PON_FEN_SYSON_Msk                                        (0x1UL << PCC_REG_PERION_CLK_VPON_REG0X_R_PON_FEN_SYSON_Pos)
+
+#define PCC_REG_PERION_CLK_VPON_REG0X_R_PON_FEN_TMETER_Pos                                       2U
+#define PCC_REG_PERION_CLK_VPON_REG0X_R_PON_FEN_TMETER_Msk                                       (0x1UL << PCC_REG_PERION_CLK_VPON_REG0X_R_PON_FEN_TMETER_Pos)
+
+#define PCC_REG_PERION_CLK_VPON_REG0X_R_PON_FEN_DSS_Pos                                          3U
+#define PCC_REG_PERION_CLK_VPON_REG0X_R_PON_FEN_DSS_Msk                                          (0x1UL << PCC_REG_PERION_CLK_VPON_REG0X_R_PON_FEN_DSS_Pos)
+
+#define PCC_REG_PERION_CLK_VPON_REG0X_R_PON_FEN_CODEC_Pos                                        4U
+#define PCC_REG_PERION_CLK_VPON_REG0X_R_PON_FEN_CODEC_Msk                                        (0x1UL << PCC_REG_PERION_CLK_VPON_REG0X_R_PON_FEN_CODEC_Pos)
+
+#define PCC_REG_PERION_CLK_VPON_REG0X_R_PON_FEN_UART2_Pos                                        5U
+#define PCC_REG_PERION_CLK_VPON_REG0X_R_PON_FEN_UART2_Msk                                        (0x1UL << PCC_REG_PERION_CLK_VPON_REG0X_R_PON_FEN_UART2_Pos)
+
+#define PCC_REG_PERION_CLK_VPON_REG0X_R_PON_FEN_UART1_Pos                                        6U
+#define PCC_REG_PERION_CLK_VPON_REG0X_R_PON_FEN_UART1_Msk                                        (0x1UL << PCC_REG_PERION_CLK_VPON_REG0X_R_PON_FEN_UART1_Pos)
+
+#define PCC_REG_PERION_CLK_VPON_REG0X_R_PON_FEN_UART0_Pos                                        7U
+#define PCC_REG_PERION_CLK_VPON_REG0X_R_PON_FEN_UART0_Msk                                        (0x1UL << PCC_REG_PERION_CLK_VPON_REG0X_R_PON_FEN_UART0_Pos)
+
+#define PCC_REG_PERION_CLK_VPON_REG0X_R_PON_FEN_GPIO_DBNC_2P4G_Pos                               8U
+#define PCC_REG_PERION_CLK_VPON_REG0X_R_PON_FEN_GPIO_DBNC_2P4G_Msk                               (0x1UL << PCC_REG_PERION_CLK_VPON_REG0X_R_PON_FEN_GPIO_DBNC_2P4G_Pos)
+
+#define PCC_REG_PERION_CLK_VPON_REG0X_R_PON_FEN_CAN_Pos                                          9U
+#define PCC_REG_PERION_CLK_VPON_REG0X_R_PON_FEN_CAN_Msk                                          (0x1UL << PCC_REG_PERION_CLK_VPON_REG0X_R_PON_FEN_CAN_Pos)
+
+#define PCC_REG_PERION_CLK_VPON_REG0X_R_PON_FEN_EFLASH_Pos                                       10U
+#define PCC_REG_PERION_CLK_VPON_REG0X_R_PON_FEN_EFLASH_Msk                                       (0x1UL << PCC_REG_PERION_CLK_VPON_REG0X_R_PON_FEN_EFLASH_Pos)
+
+#define PCC_REG_PERION_CLK_VPON_REG0X_R_PON_FEN_SPI3W_Pos                                        11U
+#define PCC_REG_PERION_CLK_VPON_REG0X_R_PON_FEN_SPI3W_Msk                                        (0x1UL << PCC_REG_PERION_CLK_VPON_REG0X_R_PON_FEN_SPI3W_Pos)
+
+#define PCC_REG_PERION_CLK_VPON_REG0X_R_PON_FEN_KEYSCAN_Pos                                      12U
+#define PCC_REG_PERION_CLK_VPON_REG0X_R_PON_FEN_KEYSCAN_Msk                                      (0x1UL << PCC_REG_PERION_CLK_VPON_REG0X_R_PON_FEN_KEYSCAN_Pos)
+
+#define PCC_REG_PERION_CLK_VPON_REG0X_R_PON_FEN_I2C1_Pos                                         13U
+#define PCC_REG_PERION_CLK_VPON_REG0X_R_PON_FEN_I2C1_Msk                                         (0x1UL << PCC_REG_PERION_CLK_VPON_REG0X_R_PON_FEN_I2C1_Pos)
+
+#define PCC_REG_PERION_CLK_VPON_REG0X_R_PON_FEN_I2C0_Pos                                         14U
+#define PCC_REG_PERION_CLK_VPON_REG0X_R_PON_FEN_I2C0_Msk                                         (0x1UL << PCC_REG_PERION_CLK_VPON_REG0X_R_PON_FEN_I2C0_Pos)
+
+#define PCC_REG_PERION_CLK_VPON_REG0X_R_PON_FEN_ADC_Pos                                          15U
+#define PCC_REG_PERION_CLK_VPON_REG0X_R_PON_FEN_ADC_Msk                                          (0x1UL << PCC_REG_PERION_CLK_VPON_REG0X_R_PON_FEN_ADC_Pos)
+
+#define PCC_REG_PERION_CLK_VPON_REG0X_R_PON_FEN_USB_Pos                                          16U
+#define PCC_REG_PERION_CLK_VPON_REG0X_R_PON_FEN_USB_Msk                                          (0x1UL << PCC_REG_PERION_CLK_VPON_REG0X_R_PON_FEN_USB_Pos)
+
+#define PCC_REG_PERION_CLK_VPON_REG0X_R_PON_FEN_TIMER_2_PWM_Pos                                  17U
+#define PCC_REG_PERION_CLK_VPON_REG0X_R_PON_FEN_TIMER_2_PWM_Msk                                  (0x1UL << PCC_REG_PERION_CLK_VPON_REG0X_R_PON_FEN_TIMER_2_PWM_Pos)
+
+#define PCC_REG_PERION_CLK_VPON_REG0X_R_PON_FEN_TIMER_2_Pos                                      18U
+#define PCC_REG_PERION_CLK_VPON_REG0X_R_PON_FEN_TIMER_2_Msk                                      (0x1UL << PCC_REG_PERION_CLK_VPON_REG0X_R_PON_FEN_TIMER_2_Pos)
+
+#define PCC_REG_PERION_CLK_VPON_REG0X_R_PON_FEN_TIMER_1_Pos                                      19U
+#define PCC_REG_PERION_CLK_VPON_REG0X_R_PON_FEN_TIMER_1_Msk                                      (0x1UL << PCC_REG_PERION_CLK_VPON_REG0X_R_PON_FEN_TIMER_1_Pos)
+
+#define PCC_REG_PERION_CLK_VPON_REG0X_R_PON_FEN_TIMER_0_Pos                                      20U
+#define PCC_REG_PERION_CLK_VPON_REG0X_R_PON_FEN_TIMER_0_Msk                                      (0x1UL << PCC_REG_PERION_CLK_VPON_REG0X_R_PON_FEN_TIMER_0_Pos)
+
+#define PCC_REG_PERION_CLK_VPON_REG0X_R_PON_FEN_I2S_Pos                                          21U
+#define PCC_REG_PERION_CLK_VPON_REG0X_R_PON_FEN_I2S_Msk                                          (0x1UL << PCC_REG_PERION_CLK_VPON_REG0X_R_PON_FEN_I2S_Pos)
+
+#define PCC_REG_PERION_CLK_VPON_REG0X_R_PON_FEN_SPI2_Pos                                         22U
+#define PCC_REG_PERION_CLK_VPON_REG0X_R_PON_FEN_SPI2_Msk                                         (0x1UL << PCC_REG_PERION_CLK_VPON_REG0X_R_PON_FEN_SPI2_Pos)
+
+#define PCC_REG_PERION_CLK_VPON_REG0X_R_PON_FEN_SPI1_Pos                                         23U
+#define PCC_REG_PERION_CLK_VPON_REG0X_R_PON_FEN_SPI1_Msk                                         (0x1UL << PCC_REG_PERION_CLK_VPON_REG0X_R_PON_FEN_SPI1_Pos)
+
+#define PCC_REG_PERION_CLK_VPON_REG0X_R_PON_FEN_SPI0_Pos                                         24U
+#define PCC_REG_PERION_CLK_VPON_REG0X_R_PON_FEN_SPI0_Msk                                         (0x1UL << PCC_REG_PERION_CLK_VPON_REG0X_R_PON_FEN_SPI0_Pos)
+
+#define PCC_REG_PERION_CLK_VPON_REG0X_R_PON_FEN_FMC0_Pos                                         25U
+#define PCC_REG_PERION_CLK_VPON_REG0X_R_PON_FEN_FMC0_Msk                                         (0x1UL << PCC_REG_PERION_CLK_VPON_REG0X_R_PON_FEN_FMC0_Pos)
+
+#define PCC_REG_PERION_CLK_VPON_REG0X_R_PON_FEN_DMA0_Pos                                         26U
+#define PCC_REG_PERION_CLK_VPON_REG0X_R_PON_FEN_DMA0_Msk                                         (0x1UL << PCC_REG_PERION_CLK_VPON_REG0X_R_PON_FEN_DMA0_Pos)
+
+#define PCC_REG_PERION_CLK_VPON_REG0X_R_PON_FEN_MODEMRFCPI_Pos                                   27U
+#define PCC_REG_PERION_CLK_VPON_REG0X_R_PON_FEN_MODEMRFCPI_Msk                                   (0x1UL << PCC_REG_PERION_CLK_VPON_REG0X_R_PON_FEN_MODEMRFCPI_Pos)
+
+#define PCC_REG_PERION_CLK_VPON_REG0X_R_PON_FEN_SHA256_Pos                                       28U
+#define PCC_REG_PERION_CLK_VPON_REG0X_R_PON_FEN_SHA256_Msk                                       (0x1UL << PCC_REG_PERION_CLK_VPON_REG0X_R_PON_FEN_SHA256_Pos)
+
+#define PCC_REG_PERION_CLK_VPON_REG0X_R_PON_FEN_AES_Pos                                          29U
+#define PCC_REG_PERION_CLK_VPON_REG0X_R_PON_FEN_AES_Msk                                          (0x1UL << PCC_REG_PERION_CLK_VPON_REG0X_R_PON_FEN_AES_Pos)
+
+#define PCC_REG_PERION_CLK_VPON_REG0X_R_PON_FEN_CORE_WDT_Pos                                     30U
+#define PCC_REG_PERION_CLK_VPON_REG0X_R_PON_FEN_CORE_WDT_Msk                                     (0x1UL << PCC_REG_PERION_CLK_VPON_REG0X_R_PON_FEN_CORE_WDT_Pos)
+
+#define PCC_REG_PERION_CLK_VPON_REG0X_R_PON_FEN_RNG_Pos                                          31U
+#define PCC_REG_PERION_CLK_VPON_REG0X_R_PON_FEN_RNG_Msk                                          (0x1UL << PCC_REG_PERION_CLK_VPON_REG0X_R_PON_FEN_RNG_Pos)
+
+/* 0x3C8    0x4000_03c8
+    11:0    R/W     RESERVED                                        12'h0
+    12      W1O     SWD_ENABLE_WR_ENABLE                            1'b0
+    13      R/W     SWD_ENABLE                                      1'b1
+    14      R/W     R_PON_FEN_RFC                                   1'b0
+    15      R/W     R_PON_FEN_PLATFORM                              1'b1
+    16      R/W     R_PON_FEN_CPU                                   1'b1
+    17      R/W     R_PON_FEN_SDM32K                                1'b1
+    18      R/W     R_PON_FEN_AAC                                   1'b0
+    19      R/W     R_PON_FEN_CAL80M                                1'b0
+    20      R/W     R_PON_FEN_CAL10M                                1'b0
+    21      R/W     R_PON_FEN_CAL32K                                1'b1
+    22      R/W     R_PON_FEN_TIMER1_PWM_CH8                        1'b0
+    23      R/W     R_PON_FEN_TIMER1_PWM_CH7                        1'b0
+    24      R/W     R_PON_FEN_TIMER1_PWM_CH6                        1'b0
+    25      R/W     R_PON_FEN_HCI                                   1'b0
+    26      R/W     R_PON_FEN_LXBUS                                 1'b1
+    27      R/W     R_PON_FEN_BT_VEN                                1'b1
+    28      R/W     R_PON_FEN_IRRC                                  1'b0
+    29      R/W     R_PON_FEN_PRO24G                                1'b0
+    30      R/W     R_PON_FEN_GPIO0                                 1'b0
+    31      R/W     R_PON_FEN_UART3                                 1'b0
+ */
+typedef union _PCC_REG_PERION_CLK_VPON_REG1X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED: 12;
+        uint32_t SWD_ENABLE_WR_ENABLE: 1;
+        uint32_t SWD_ENABLE: 1;
+        uint32_t R_PON_FEN_RFC: 1;
+        uint32_t R_PON_FEN_PLATFORM: 1;
+        uint32_t R_PON_FEN_CPU: 1;
+        uint32_t R_PON_FEN_SDM32K: 1;
+        uint32_t R_PON_FEN_AAC: 1;
+        uint32_t R_PON_FEN_CAL80M: 1;
+        uint32_t R_PON_FEN_CAL10M: 1;
+        uint32_t R_PON_FEN_CAL32K: 1;
+        uint32_t R_PON_FEN_TIMER1_PWM_CH8: 1;
+        uint32_t R_PON_FEN_TIMER1_PWM_CH7: 1;
+        uint32_t R_PON_FEN_TIMER1_PWM_CH6: 1;
+        uint32_t R_PON_FEN_HCI: 1;
+        uint32_t R_PON_FEN_LXBUS: 1;
+        uint32_t R_PON_FEN_BT_VEN: 1;
+        uint32_t R_PON_FEN_IRRC: 1;
+        uint32_t R_PON_FEN_PRO24G: 1;
+        uint32_t R_PON_FEN_GPIO0: 1;
+        uint32_t R_PON_FEN_UART3: 1;
+    };
+} PCC_REG_PERION_CLK_VPON_REG1X_TYPE;
+
+/*0x4000_03c8 PCC_REG_PERION_CLK_VPON_REG1X*/
+#define PCC_REG_PERION_CLK_VPON_REG1X_RESERVED_Pos                                               0U
+#define PCC_REG_PERION_CLK_VPON_REG1X_RESERVED_Msk                                               (0xFFFUL << PCC_REG_PERION_CLK_VPON_REG1X_RESERVED_Pos)
+
+#define PCC_REG_PERION_CLK_VPON_REG1X_SWD_ENABLE_WR_ENABLE_Pos                                   12U
+#define PCC_REG_PERION_CLK_VPON_REG1X_SWD_ENABLE_WR_ENABLE_Msk                                   (0x1UL << PCC_REG_PERION_CLK_VPON_REG1X_SWD_ENABLE_WR_ENABLE_Pos)
+
+#define PCC_REG_PERION_CLK_VPON_REG1X_SWD_ENABLE_Pos                                             13U
+#define PCC_REG_PERION_CLK_VPON_REG1X_SWD_ENABLE_Msk                                             (0x1UL << PCC_REG_PERION_CLK_VPON_REG1X_SWD_ENABLE_Pos)
+
+#define PCC_REG_PERION_CLK_VPON_REG1X_R_PON_FEN_RFC_Pos                                          14U
+#define PCC_REG_PERION_CLK_VPON_REG1X_R_PON_FEN_RFC_Msk                                          (0x1UL << PCC_REG_PERION_CLK_VPON_REG1X_R_PON_FEN_RFC_Pos)
+
+#define PCC_REG_PERION_CLK_VPON_REG1X_R_PON_FEN_PLATFORM_Pos                                     15U
+#define PCC_REG_PERION_CLK_VPON_REG1X_R_PON_FEN_PLATFORM_Msk                                     (0x1UL << PCC_REG_PERION_CLK_VPON_REG1X_R_PON_FEN_PLATFORM_Pos)
+
+#define PCC_REG_PERION_CLK_VPON_REG1X_R_PON_FEN_CPU_Pos                                          16U
+#define PCC_REG_PERION_CLK_VPON_REG1X_R_PON_FEN_CPU_Msk                                          (0x1UL << PCC_REG_PERION_CLK_VPON_REG1X_R_PON_FEN_CPU_Pos)
+
+#define PCC_REG_PERION_CLK_VPON_REG1X_R_PON_FEN_SDM32K_Pos                                       17U
+#define PCC_REG_PERION_CLK_VPON_REG1X_R_PON_FEN_SDM32K_Msk                                       (0x1UL << PCC_REG_PERION_CLK_VPON_REG1X_R_PON_FEN_SDM32K_Pos)
+
+#define PCC_REG_PERION_CLK_VPON_REG1X_R_PON_FEN_AAC_Pos                                          18U
+#define PCC_REG_PERION_CLK_VPON_REG1X_R_PON_FEN_AAC_Msk                                          (0x1UL << PCC_REG_PERION_CLK_VPON_REG1X_R_PON_FEN_AAC_Pos)
+
+#define PCC_REG_PERION_CLK_VPON_REG1X_R_PON_FEN_CAL80M_Pos                                       19U
+#define PCC_REG_PERION_CLK_VPON_REG1X_R_PON_FEN_CAL80M_Msk                                       (0x1UL << PCC_REG_PERION_CLK_VPON_REG1X_R_PON_FEN_CAL80M_Pos)
+
+#define PCC_REG_PERION_CLK_VPON_REG1X_R_PON_FEN_CAL10M_Pos                                       20U
+#define PCC_REG_PERION_CLK_VPON_REG1X_R_PON_FEN_CAL10M_Msk                                       (0x1UL << PCC_REG_PERION_CLK_VPON_REG1X_R_PON_FEN_CAL10M_Pos)
+
+#define PCC_REG_PERION_CLK_VPON_REG1X_R_PON_FEN_CAL32K_Pos                                       21U
+#define PCC_REG_PERION_CLK_VPON_REG1X_R_PON_FEN_CAL32K_Msk                                       (0x1UL << PCC_REG_PERION_CLK_VPON_REG1X_R_PON_FEN_CAL32K_Pos)
+
+#define PCC_REG_PERION_CLK_VPON_REG1X_R_PON_FEN_TIMER1_PWM_CH8_Pos                               22U
+#define PCC_REG_PERION_CLK_VPON_REG1X_R_PON_FEN_TIMER1_PWM_CH8_Msk                               (0x1UL << PCC_REG_PERION_CLK_VPON_REG1X_R_PON_FEN_TIMER1_PWM_CH8_Pos)
+
+#define PCC_REG_PERION_CLK_VPON_REG1X_R_PON_FEN_TIMER1_PWM_CH7_Pos                               23U
+#define PCC_REG_PERION_CLK_VPON_REG1X_R_PON_FEN_TIMER1_PWM_CH7_Msk                               (0x1UL << PCC_REG_PERION_CLK_VPON_REG1X_R_PON_FEN_TIMER1_PWM_CH7_Pos)
+
+#define PCC_REG_PERION_CLK_VPON_REG1X_R_PON_FEN_TIMER1_PWM_CH6_Pos                               24U
+#define PCC_REG_PERION_CLK_VPON_REG1X_R_PON_FEN_TIMER1_PWM_CH6_Msk                               (0x1UL << PCC_REG_PERION_CLK_VPON_REG1X_R_PON_FEN_TIMER1_PWM_CH6_Pos)
+
+#define PCC_REG_PERION_CLK_VPON_REG1X_R_PON_FEN_HCI_Pos                                          25U
+#define PCC_REG_PERION_CLK_VPON_REG1X_R_PON_FEN_HCI_Msk                                          (0x1UL << PCC_REG_PERION_CLK_VPON_REG1X_R_PON_FEN_HCI_Pos)
+
+#define PCC_REG_PERION_CLK_VPON_REG1X_R_PON_FEN_LXBUS_Pos                                        26U
+#define PCC_REG_PERION_CLK_VPON_REG1X_R_PON_FEN_LXBUS_Msk                                        (0x1UL << PCC_REG_PERION_CLK_VPON_REG1X_R_PON_FEN_LXBUS_Pos)
+
+#define PCC_REG_PERION_CLK_VPON_REG1X_R_PON_FEN_BT_VEN_Pos                                       27U
+#define PCC_REG_PERION_CLK_VPON_REG1X_R_PON_FEN_BT_VEN_Msk                                       (0x1UL << PCC_REG_PERION_CLK_VPON_REG1X_R_PON_FEN_BT_VEN_Pos)
+
+#define PCC_REG_PERION_CLK_VPON_REG1X_R_PON_FEN_IRRC_Pos                                         28U
+#define PCC_REG_PERION_CLK_VPON_REG1X_R_PON_FEN_IRRC_Msk                                         (0x1UL << PCC_REG_PERION_CLK_VPON_REG1X_R_PON_FEN_IRRC_Pos)
+
+#define PCC_REG_PERION_CLK_VPON_REG1X_R_PON_FEN_PRO24G_Pos                                       29U
+#define PCC_REG_PERION_CLK_VPON_REG1X_R_PON_FEN_PRO24G_Msk                                       (0x1UL << PCC_REG_PERION_CLK_VPON_REG1X_R_PON_FEN_PRO24G_Pos)
+
+#define PCC_REG_PERION_CLK_VPON_REG1X_R_PON_FEN_GPIO0_Pos                                        30U
+#define PCC_REG_PERION_CLK_VPON_REG1X_R_PON_FEN_GPIO0_Msk                                        (0x1UL << PCC_REG_PERION_CLK_VPON_REG1X_R_PON_FEN_GPIO0_Pos)
+
+#define PCC_REG_PERION_CLK_VPON_REG1X_R_PON_FEN_UART3_Pos                                        31U
+#define PCC_REG_PERION_CLK_VPON_REG1X_R_PON_FEN_UART3_Msk                                        (0x1UL << PCC_REG_PERION_CLK_VPON_REG1X_R_PON_FEN_UART3_Pos)
+
+/* 0x3CC    0x4000_03cc
+    0       R/W     S9_INTF_MASK_EN                                 1'b0
+    1       R/W     M4_INTF_MASK_EN                                 1'b0
+    6:2     R/W     RESERVED_3                                      5'h0
+    7       R       CLKEN_O_BTMAC                                   1'b0
+    20:8    R/W     RESERVED_2                                      13'h0
+    21      R/W     R_CPU_CLK_SRC_SEL_1                             1'b0
+    22      R/W     R_CPU_CLK_SRC_SEL_2                             1'b1
+    23      R/W     R_40M_MAC_CLK_SRC_SEL                           1'b1
+    26:24   R/W     RESERVED_1                                      3'h0
+    27      R/W     R_40M_CLK_SRC_SEL_0                             1'b1
+    30:28   R/W     RESERVED                                        3'h0
+    31      R/W     R_32K_CLK_SRC_SEL                               1'b1
+ */
+typedef union _PCC_REG_PERION_CLK_VPON_REG2X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t S9_INTF_MASK_EN: 1;
+        uint32_t M4_INTF_MASK_EN: 1;
+        uint32_t RESERVED_3: 5;
+        uint32_t CLKEN_O_BTMAC: 1;
+        uint32_t RESERVED_2: 13;
+        uint32_t R_CPU_CLK_SRC_SEL_1: 1;
+        uint32_t R_CPU_CLK_SRC_SEL_2: 1;
+        uint32_t R_40M_MAC_CLK_SRC_SEL: 1;
+        uint32_t RESERVED_1: 3;
+        uint32_t R_40M_CLK_SRC_SEL_0: 1;
+        uint32_t RESERVED: 3;
+        uint32_t R_32K_CLK_SRC_SEL: 1;
+    };
+} PCC_REG_PERION_CLK_VPON_REG2X_TYPE;
+
+/*0x4000_03cc PCC_REG_PERION_CLK_VPON_REG2X*/
+#define PCC_REG_PERION_CLK_VPON_REG2X_S9_INTF_MASK_EN_Pos                                        0U
+#define PCC_REG_PERION_CLK_VPON_REG2X_S9_INTF_MASK_EN_Msk                                        (0x1UL << PCC_REG_PERION_CLK_VPON_REG2X_S9_INTF_MASK_EN_Pos)
+
+#define PCC_REG_PERION_CLK_VPON_REG2X_M4_INTF_MASK_EN_Pos                                        1U
+#define PCC_REG_PERION_CLK_VPON_REG2X_M4_INTF_MASK_EN_Msk                                        (0x1UL << PCC_REG_PERION_CLK_VPON_REG2X_M4_INTF_MASK_EN_Pos)
+
+#define PCC_REG_PERION_CLK_VPON_REG2X_RESERVED_3_Pos                                             2U
+#define PCC_REG_PERION_CLK_VPON_REG2X_RESERVED_3_Msk                                             (0x1FUL << PCC_REG_PERION_CLK_VPON_REG2X_RESERVED_3_Pos)
+
+#define PCC_REG_PERION_CLK_VPON_REG2X_CLKEN_O_BTMAC_Pos                                          7U
+#define PCC_REG_PERION_CLK_VPON_REG2X_CLKEN_O_BTMAC_Msk                                          (0x1UL << PCC_REG_PERION_CLK_VPON_REG2X_CLKEN_O_BTMAC_Pos)
+
+#define PCC_REG_PERION_CLK_VPON_REG2X_RESERVED_2_Pos                                             8U
+#define PCC_REG_PERION_CLK_VPON_REG2X_RESERVED_2_Msk                                             (0x1FFFUL << PCC_REG_PERION_CLK_VPON_REG2X_RESERVED_2_Pos)
+
+#define PCC_REG_PERION_CLK_VPON_REG2X_R_CPU_CLK_SRC_SEL_1_Pos                                    21U
+#define PCC_REG_PERION_CLK_VPON_REG2X_R_CPU_CLK_SRC_SEL_1_Msk                                    (0x1UL << PCC_REG_PERION_CLK_VPON_REG2X_R_CPU_CLK_SRC_SEL_1_Pos)
+
+#define PCC_REG_PERION_CLK_VPON_REG2X_R_CPU_CLK_SRC_SEL_2_Pos                                    22U
+#define PCC_REG_PERION_CLK_VPON_REG2X_R_CPU_CLK_SRC_SEL_2_Msk                                    (0x1UL << PCC_REG_PERION_CLK_VPON_REG2X_R_CPU_CLK_SRC_SEL_2_Pos)
+
+#define PCC_REG_PERION_CLK_VPON_REG2X_R_40M_MAC_CLK_SRC_SEL_Pos                                  23U
+#define PCC_REG_PERION_CLK_VPON_REG2X_R_40M_MAC_CLK_SRC_SEL_Msk                                  (0x1UL << PCC_REG_PERION_CLK_VPON_REG2X_R_40M_MAC_CLK_SRC_SEL_Pos)
+
+#define PCC_REG_PERION_CLK_VPON_REG2X_RESERVED_1_Pos                                             24U
+#define PCC_REG_PERION_CLK_VPON_REG2X_RESERVED_1_Msk                                             (0x7UL << PCC_REG_PERION_CLK_VPON_REG2X_RESERVED_1_Pos)
+
+#define PCC_REG_PERION_CLK_VPON_REG2X_R_40M_CLK_SRC_SEL_0_Pos                                    27U
+#define PCC_REG_PERION_CLK_VPON_REG2X_R_40M_CLK_SRC_SEL_0_Msk                                    (0x1UL << PCC_REG_PERION_CLK_VPON_REG2X_R_40M_CLK_SRC_SEL_0_Pos)
+
+#define PCC_REG_PERION_CLK_VPON_REG2X_RESERVED_Pos                                               28U
+#define PCC_REG_PERION_CLK_VPON_REG2X_RESERVED_Msk                                               (0x7UL << PCC_REG_PERION_CLK_VPON_REG2X_RESERVED_Pos)
+
+#define PCC_REG_PERION_CLK_VPON_REG2X_R_32K_CLK_SRC_SEL_Pos                                      31U
+#define PCC_REG_PERION_CLK_VPON_REG2X_R_32K_CLK_SRC_SEL_Msk                                      (0x1UL << PCC_REG_PERION_CLK_VPON_REG2X_R_32K_CLK_SRC_SEL_Pos)
+
+/* 0x3D0    0x4000_03d0
+    7:0     R/W     ENTRY_DELAY_LPPWM                               8'b0
+    15:8    R/W     RSVD_2                                          8'h0
+    16      R/W     RESERVED_7                                      1'b0
+    17      R/W     RESERVED_6                                      1'b0
+    18      R/W     LPPWM_CLK_FORCE                                 1'b0
+    21:19   R/W     RSVD_1                                          3'b000
+    22      R/W     RESERVED_5                                      1'b0
+    23      R/W     RESERVED_4                                      1'b0
+    24      R/W     RESERVED_3                                      1'b0
+    25      R/W     RESERVED_2                                      1'b0
+    26      R/W     RESERVED_1                                      1'b0
+    27      R/W     RESERVED                                        1'b0
+    30:28   R/W     RSVD                                            3'b000
+    31      R/W     R_PON_FEN_LPPWM                                 1'b0
+ */
+typedef union _PCC_REG_LPPWM_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t ENTRY_DELAY_LPPWM: 8;
+        uint32_t RSVD_2: 8;
+        uint32_t RESERVED_7: 1;
+        uint32_t RESERVED_6: 1;
+        uint32_t LPPWM_CLK_FORCE: 1;
+        uint32_t RSVD_1: 3;
+        uint32_t RESERVED_5: 1;
+        uint32_t RESERVED_4: 1;
+        uint32_t RESERVED_3: 1;
+        uint32_t RESERVED_2: 1;
+        uint32_t RESERVED_1: 1;
+        uint32_t RESERVED: 1;
+        uint32_t RSVD: 3;
+        uint32_t R_PON_FEN_LPPWM: 1;
+    };
+} PCC_REG_LPPWM_TYPE;
+
+/*0x4000_03d0 PCC_REG_LPPWM*/
+#define PCC_REG_LPPWM_ENTRY_DELAY_LPPWM_Pos                                                      0U
+#define PCC_REG_LPPWM_ENTRY_DELAY_LPPWM_Msk                                                      (0xFFUL << PCC_REG_LPPWM_ENTRY_DELAY_LPPWM_Pos)
+
+#define PCC_REG_LPPWM_RSVD_2_Pos                                                                 8U
+#define PCC_REG_LPPWM_RSVD_2_Msk                                                                 (0xFFUL << PCC_REG_LPPWM_RSVD_2_Pos)
+
+#define PCC_REG_LPPWM_RESERVED_7_Pos                                                             16U
+#define PCC_REG_LPPWM_RESERVED_7_Msk                                                             (0x1UL << PCC_REG_LPPWM_RESERVED_7_Pos)
+
+#define PCC_REG_LPPWM_RESERVED_6_Pos                                                             17U
+#define PCC_REG_LPPWM_RESERVED_6_Msk                                                             (0x1UL << PCC_REG_LPPWM_RESERVED_6_Pos)
+
+#define PCC_REG_LPPWM_LPPWM_CLK_FORCE_Pos                                                        18U
+#define PCC_REG_LPPWM_LPPWM_CLK_FORCE_Msk                                                        (0x1UL << PCC_REG_LPPWM_LPPWM_CLK_FORCE_Pos)
+
+#define PCC_REG_LPPWM_RSVD_1_Pos                                                                 19U
+#define PCC_REG_LPPWM_RSVD_1_Msk                                                                 (0x7UL << PCC_REG_LPPWM_RSVD_1_Pos)
+
+#define PCC_REG_LPPWM_RESERVED_5_Pos                                                             22U
+#define PCC_REG_LPPWM_RESERVED_5_Msk                                                             (0x1UL << PCC_REG_LPPWM_RESERVED_5_Pos)
+
+#define PCC_REG_LPPWM_RESERVED_4_Pos                                                             23U
+#define PCC_REG_LPPWM_RESERVED_4_Msk                                                             (0x1UL << PCC_REG_LPPWM_RESERVED_4_Pos)
+
+#define PCC_REG_LPPWM_RESERVED_3_Pos                                                             24U
+#define PCC_REG_LPPWM_RESERVED_3_Msk                                                             (0x1UL << PCC_REG_LPPWM_RESERVED_3_Pos)
+
+#define PCC_REG_LPPWM_RESERVED_2_Pos                                                             25U
+#define PCC_REG_LPPWM_RESERVED_2_Msk                                                             (0x1UL << PCC_REG_LPPWM_RESERVED_2_Pos)
+
+#define PCC_REG_LPPWM_RESERVED_1_Pos                                                             26U
+#define PCC_REG_LPPWM_RESERVED_1_Msk                                                             (0x1UL << PCC_REG_LPPWM_RESERVED_1_Pos)
+
+#define PCC_REG_LPPWM_RESERVED_Pos                                                               27U
+#define PCC_REG_LPPWM_RESERVED_Msk                                                               (0x1UL << PCC_REG_LPPWM_RESERVED_Pos)
+
+#define PCC_REG_LPPWM_RSVD_Pos                                                                   28U
+#define PCC_REG_LPPWM_RSVD_Msk                                                                   (0x7UL << PCC_REG_LPPWM_RSVD_Pos)
+
+#define PCC_REG_LPPWM_R_PON_FEN_LPPWM_Pos                                                        31U
+#define PCC_REG_LPPWM_R_PON_FEN_LPPWM_Msk                                                        (0x1UL << PCC_REG_LPPWM_R_PON_FEN_LPPWM_Pos)
+
+/* 0x3D4    0x4000_03d4
+    7:0     R/W     ENTRY_DELAY_LPQDEC                              8'b0
+    15:8    R/W     RSVD_2                                          8'h0
+    16      R/W     RESERVED_7                                      1'b0
+    17      R/W     RESERVED_6                                      1'b0
+    18      R/W     LPQDEC_CLK_FORCE                                1'b0
+    21:19   R/W     RSVD_1                                          3'b000
+    22      R/W     RESERVED_5                                      1'b0
+    23      R/W     RESERVED_4                                      1'b0
+    24      R/W     RESERVED_3                                      1'b0
+    25      R/W     RESERVED_2                                      1'b0
+    26      R/W     RESERVED_1                                      1'b0
+    27      R/W     RESERVED                                        1'b0
+    30:28   R/W     RSVD                                            3'b000
+    31      R/W     R_PON_FEN_LPQDEC                                1'b0
+ */
+typedef union _PCC_REG_LPQDEC_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t ENTRY_DELAY_LPQDEC: 8;
+        uint32_t RSVD_2: 8;
+        uint32_t RESERVED_7: 1;
+        uint32_t RESERVED_6: 1;
+        uint32_t LPQDEC_CLK_FORCE: 1;
+        uint32_t RSVD_1: 3;
+        uint32_t RESERVED_5: 1;
+        uint32_t RESERVED_4: 1;
+        uint32_t RESERVED_3: 1;
+        uint32_t RESERVED_2: 1;
+        uint32_t RESERVED_1: 1;
+        uint32_t RESERVED: 1;
+        uint32_t RSVD: 3;
+        uint32_t R_PON_FEN_LPQDEC: 1;
+    };
+} PCC_REG_LPQDEC_TYPE;
+
+/*0x4000_03d4 PCC_REG_LPQDEC*/
+#define PCC_REG_LPQDEC_ENTRY_DELAY_LPQDEC_Pos                                                    0U
+#define PCC_REG_LPQDEC_ENTRY_DELAY_LPQDEC_Msk                                                    (0xFFUL << PCC_REG_LPQDEC_ENTRY_DELAY_LPQDEC_Pos)
+
+#define PCC_REG_LPQDEC_RSVD_2_Pos                                                                8U
+#define PCC_REG_LPQDEC_RSVD_2_Msk                                                                (0xFFUL << PCC_REG_LPQDEC_RSVD_2_Pos)
+
+#define PCC_REG_LPQDEC_RESERVED_7_Pos                                                            16U
+#define PCC_REG_LPQDEC_RESERVED_7_Msk                                                            (0x1UL << PCC_REG_LPQDEC_RESERVED_7_Pos)
+
+#define PCC_REG_LPQDEC_RESERVED_6_Pos                                                            17U
+#define PCC_REG_LPQDEC_RESERVED_6_Msk                                                            (0x1UL << PCC_REG_LPQDEC_RESERVED_6_Pos)
+
+#define PCC_REG_LPQDEC_LPQDEC_CLK_FORCE_Pos                                                      18U
+#define PCC_REG_LPQDEC_LPQDEC_CLK_FORCE_Msk                                                      (0x1UL << PCC_REG_LPQDEC_LPQDEC_CLK_FORCE_Pos)
+
+#define PCC_REG_LPQDEC_RSVD_1_Pos                                                                19U
+#define PCC_REG_LPQDEC_RSVD_1_Msk                                                                (0x7UL << PCC_REG_LPQDEC_RSVD_1_Pos)
+
+#define PCC_REG_LPQDEC_RESERVED_5_Pos                                                            22U
+#define PCC_REG_LPQDEC_RESERVED_5_Msk                                                            (0x1UL << PCC_REG_LPQDEC_RESERVED_5_Pos)
+
+#define PCC_REG_LPQDEC_RESERVED_4_Pos                                                            23U
+#define PCC_REG_LPQDEC_RESERVED_4_Msk                                                            (0x1UL << PCC_REG_LPQDEC_RESERVED_4_Pos)
+
+#define PCC_REG_LPQDEC_RESERVED_3_Pos                                                            24U
+#define PCC_REG_LPQDEC_RESERVED_3_Msk                                                            (0x1UL << PCC_REG_LPQDEC_RESERVED_3_Pos)
+
+#define PCC_REG_LPQDEC_RESERVED_2_Pos                                                            25U
+#define PCC_REG_LPQDEC_RESERVED_2_Msk                                                            (0x1UL << PCC_REG_LPQDEC_RESERVED_2_Pos)
+
+#define PCC_REG_LPQDEC_RESERVED_1_Pos                                                            26U
+#define PCC_REG_LPQDEC_RESERVED_1_Msk                                                            (0x1UL << PCC_REG_LPQDEC_RESERVED_1_Pos)
+
+#define PCC_REG_LPQDEC_RESERVED_Pos                                                              27U
+#define PCC_REG_LPQDEC_RESERVED_Msk                                                              (0x1UL << PCC_REG_LPQDEC_RESERVED_Pos)
+
+#define PCC_REG_LPQDEC_RSVD_Pos                                                                  28U
+#define PCC_REG_LPQDEC_RSVD_Msk                                                                  (0x7UL << PCC_REG_LPQDEC_RSVD_Pos)
+
+#define PCC_REG_LPQDEC_R_PON_FEN_LPQDEC_Pos                                                      31U
+#define PCC_REG_LPQDEC_R_PON_FEN_LPQDEC_Msk                                                      (0x1UL << PCC_REG_LPQDEC_R_PON_FEN_LPQDEC_Pos)
+
+/* 0x3D8    0x4000_03d8
+    7:0     R/W     ENTRY_DELAY_GRTC                                8'b0
+    15:8    R/W     RSVD_2                                          8'h0
+    16      R/W     RESERVED_7                                      1'b0
+    17      R/W     RESERVED_6                                      1'b0
+    18      R/W     GRTC_CLK_FORCE                                  1'b0
+    21:19   R/W     RSVD_1                                          3'b000
+    22      R/W     RESERVED_5                                      1'b0
+    23      R/W     RESERVED_4                                      1'b0
+    24      R/W     RESERVED_3                                      1'b0
+    25      R/W     RESERVED_2                                      1'b0
+    26      R/W     RESERVED_1                                      1'b0
+    27      R/W     RESERVED                                        1'b0
+    30:28   R/W     RSVD                                            3'b000
+    31      R/W     R_PON_FEN_GRTC                                  1'b0
+ */
+typedef union _PCC_REG_GRTC_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t ENTRY_DELAY_GRTC: 8;
+        uint32_t RSVD_2: 8;
+        uint32_t RESERVED_7: 1;
+        uint32_t RESERVED_6: 1;
+        uint32_t GRTC_CLK_FORCE: 1;
+        uint32_t RSVD_1: 3;
+        uint32_t RESERVED_5: 1;
+        uint32_t RESERVED_4: 1;
+        uint32_t RESERVED_3: 1;
+        uint32_t RESERVED_2: 1;
+        uint32_t RESERVED_1: 1;
+        uint32_t RESERVED: 1;
+        uint32_t RSVD: 3;
+        uint32_t R_PON_FEN_GRTC: 1;
+    };
+} PCC_REG_GRTC_TYPE;
+
+/*0x4000_03d8 PCC_REG_GRTC*/
+#define PCC_REG_GRTC_ENTRY_DELAY_GRTC_Pos                                                        0U
+#define PCC_REG_GRTC_ENTRY_DELAY_GRTC_Msk                                                        (0xFFUL << PCC_REG_GRTC_ENTRY_DELAY_GRTC_Pos)
+
+#define PCC_REG_GRTC_RSVD_2_Pos                                                                  8U
+#define PCC_REG_GRTC_RSVD_2_Msk                                                                  (0xFFUL << PCC_REG_GRTC_RSVD_2_Pos)
+
+#define PCC_REG_GRTC_RESERVED_7_Pos                                                              16U
+#define PCC_REG_GRTC_RESERVED_7_Msk                                                              (0x1UL << PCC_REG_GRTC_RESERVED_7_Pos)
+
+#define PCC_REG_GRTC_RESERVED_6_Pos                                                              17U
+#define PCC_REG_GRTC_RESERVED_6_Msk                                                              (0x1UL << PCC_REG_GRTC_RESERVED_6_Pos)
+
+#define PCC_REG_GRTC_GRTC_CLK_FORCE_Pos                                                          18U
+#define PCC_REG_GRTC_GRTC_CLK_FORCE_Msk                                                          (0x1UL << PCC_REG_GRTC_GRTC_CLK_FORCE_Pos)
+
+#define PCC_REG_GRTC_RSVD_1_Pos                                                                  19U
+#define PCC_REG_GRTC_RSVD_1_Msk                                                                  (0x7UL << PCC_REG_GRTC_RSVD_1_Pos)
+
+#define PCC_REG_GRTC_RESERVED_5_Pos                                                              22U
+#define PCC_REG_GRTC_RESERVED_5_Msk                                                              (0x1UL << PCC_REG_GRTC_RESERVED_5_Pos)
+
+#define PCC_REG_GRTC_RESERVED_4_Pos                                                              23U
+#define PCC_REG_GRTC_RESERVED_4_Msk                                                              (0x1UL << PCC_REG_GRTC_RESERVED_4_Pos)
+
+#define PCC_REG_GRTC_RESERVED_3_Pos                                                              24U
+#define PCC_REG_GRTC_RESERVED_3_Msk                                                              (0x1UL << PCC_REG_GRTC_RESERVED_3_Pos)
+
+#define PCC_REG_GRTC_RESERVED_2_Pos                                                              25U
+#define PCC_REG_GRTC_RESERVED_2_Msk                                                              (0x1UL << PCC_REG_GRTC_RESERVED_2_Pos)
+
+#define PCC_REG_GRTC_RESERVED_1_Pos                                                              26U
+#define PCC_REG_GRTC_RESERVED_1_Msk                                                              (0x1UL << PCC_REG_GRTC_RESERVED_1_Pos)
+
+#define PCC_REG_GRTC_RESERVED_Pos                                                                27U
+#define PCC_REG_GRTC_RESERVED_Msk                                                                (0x1UL << PCC_REG_GRTC_RESERVED_Pos)
+
+#define PCC_REG_GRTC_RSVD_Pos                                                                    28U
+#define PCC_REG_GRTC_RSVD_Msk                                                                    (0x7UL << PCC_REG_GRTC_RSVD_Pos)
+
+#define PCC_REG_GRTC_R_PON_FEN_GRTC_Pos                                                          31U
+#define PCC_REG_GRTC_R_PON_FEN_GRTC_Msk                                                          (0x1UL << PCC_REG_GRTC_R_PON_FEN_GRTC_Pos)
+
+/* 0x3DC    0x4000_03dc
+    0       R/W     RESERVED_13                                     1'b0
+    1       R/W     RESERVED_12                                     1'b0
+    2       R/W     RESERVED_11                                     1'b0
+    3       R/W     RESERVED_10                                     1'b0
+    4       R/W     RESERVED_9                                      1'b0
+    5       R/W     RESERVED_8                                      1'b0
+    15:6    R/W     RSVD_2                                          10'h0
+    16      R/W     RESERVED_7                                      1'b0
+    17      R/W     RESERVED_6                                      1'b0
+    18      R/W     BLUEWIZ_CLK_FORCE                               1'b0
+    21:19   R/W     RSVD_1                                          3'b000
+    22      R/W     RESERVED_5                                      1'b0
+    23      R/W     RESERVED_4                                      1'b0
+    24      R/W     RESERVED_3                                      1'b0
+    25      R/W     RESERVED_2                                      1'b0
+    26      R/W     RESERVED_1                                      1'b0
+    27      R/W     RESERVED                                        1'b0
+    30:28   R/W     RSVD                                            3'b000
+    31      R/W     R_PON_FEN_BLUEWIZ                               1'b0
+ */
+typedef union _PCC_REG_BLUEWIZ_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED_13: 1;
+        uint32_t RESERVED_12: 1;
+        uint32_t RESERVED_11: 1;
+        uint32_t RESERVED_10: 1;
+        uint32_t RESERVED_9: 1;
+        uint32_t RESERVED_8: 1;
+        uint32_t RSVD_2: 10;
+        uint32_t RESERVED_7: 1;
+        uint32_t RESERVED_6: 1;
+        uint32_t BLUEWIZ_CLK_FORCE: 1;
+        uint32_t RSVD_1: 3;
+        uint32_t RESERVED_5: 1;
+        uint32_t RESERVED_4: 1;
+        uint32_t RESERVED_3: 1;
+        uint32_t RESERVED_2: 1;
+        uint32_t RESERVED_1: 1;
+        uint32_t RESERVED: 1;
+        uint32_t RSVD: 3;
+        uint32_t R_PON_FEN_BLUEWIZ: 1;
+    };
+} PCC_REG_BLUEWIZ_TYPE;
+
+/*0x4000_03dc PCC_REG_BLUEWIZ*/
+#define PCC_REG_BLUEWIZ_RESERVED_13_Pos                                                          0U
+#define PCC_REG_BLUEWIZ_RESERVED_13_Msk                                                          (0x1UL << PCC_REG_BLUEWIZ_RESERVED_13_Pos)
+
+#define PCC_REG_BLUEWIZ_RESERVED_12_Pos                                                          1U
+#define PCC_REG_BLUEWIZ_RESERVED_12_Msk                                                          (0x1UL << PCC_REG_BLUEWIZ_RESERVED_12_Pos)
+
+#define PCC_REG_BLUEWIZ_RESERVED_11_Pos                                                          2U
+#define PCC_REG_BLUEWIZ_RESERVED_11_Msk                                                          (0x1UL << PCC_REG_BLUEWIZ_RESERVED_11_Pos)
+
+#define PCC_REG_BLUEWIZ_RESERVED_10_Pos                                                          3U
+#define PCC_REG_BLUEWIZ_RESERVED_10_Msk                                                          (0x1UL << PCC_REG_BLUEWIZ_RESERVED_10_Pos)
+
+#define PCC_REG_BLUEWIZ_RESERVED_9_Pos                                                           4U
+#define PCC_REG_BLUEWIZ_RESERVED_9_Msk                                                           (0x1UL << PCC_REG_BLUEWIZ_RESERVED_9_Pos)
+
+#define PCC_REG_BLUEWIZ_RESERVED_8_Pos                                                           5U
+#define PCC_REG_BLUEWIZ_RESERVED_8_Msk                                                           (0x1UL << PCC_REG_BLUEWIZ_RESERVED_8_Pos)
+
+#define PCC_REG_BLUEWIZ_RSVD_2_Pos                                                               6U
+#define PCC_REG_BLUEWIZ_RSVD_2_Msk                                                               (0x3FFUL << PCC_REG_BLUEWIZ_RSVD_2_Pos)
+
+#define PCC_REG_BLUEWIZ_RESERVED_7_Pos                                                           16U
+#define PCC_REG_BLUEWIZ_RESERVED_7_Msk                                                           (0x1UL << PCC_REG_BLUEWIZ_RESERVED_7_Pos)
+
+#define PCC_REG_BLUEWIZ_RESERVED_6_Pos                                                           17U
+#define PCC_REG_BLUEWIZ_RESERVED_6_Msk                                                           (0x1UL << PCC_REG_BLUEWIZ_RESERVED_6_Pos)
+
+#define PCC_REG_BLUEWIZ_BLUEWIZ_CLK_FORCE_Pos                                                    18U
+#define PCC_REG_BLUEWIZ_BLUEWIZ_CLK_FORCE_Msk                                                    (0x1UL << PCC_REG_BLUEWIZ_BLUEWIZ_CLK_FORCE_Pos)
+
+#define PCC_REG_BLUEWIZ_RSVD_1_Pos                                                               19U
+#define PCC_REG_BLUEWIZ_RSVD_1_Msk                                                               (0x7UL << PCC_REG_BLUEWIZ_RSVD_1_Pos)
+
+#define PCC_REG_BLUEWIZ_RESERVED_5_Pos                                                           22U
+#define PCC_REG_BLUEWIZ_RESERVED_5_Msk                                                           (0x1UL << PCC_REG_BLUEWIZ_RESERVED_5_Pos)
+
+#define PCC_REG_BLUEWIZ_RESERVED_4_Pos                                                           23U
+#define PCC_REG_BLUEWIZ_RESERVED_4_Msk                                                           (0x1UL << PCC_REG_BLUEWIZ_RESERVED_4_Pos)
+
+#define PCC_REG_BLUEWIZ_RESERVED_3_Pos                                                           24U
+#define PCC_REG_BLUEWIZ_RESERVED_3_Msk                                                           (0x1UL << PCC_REG_BLUEWIZ_RESERVED_3_Pos)
+
+#define PCC_REG_BLUEWIZ_RESERVED_2_Pos                                                           25U
+#define PCC_REG_BLUEWIZ_RESERVED_2_Msk                                                           (0x1UL << PCC_REG_BLUEWIZ_RESERVED_2_Pos)
+
+#define PCC_REG_BLUEWIZ_RESERVED_1_Pos                                                           26U
+#define PCC_REG_BLUEWIZ_RESERVED_1_Msk                                                           (0x1UL << PCC_REG_BLUEWIZ_RESERVED_1_Pos)
+
+#define PCC_REG_BLUEWIZ_RESERVED_Pos                                                             27U
+#define PCC_REG_BLUEWIZ_RESERVED_Msk                                                             (0x1UL << PCC_REG_BLUEWIZ_RESERVED_Pos)
+
+#define PCC_REG_BLUEWIZ_RSVD_Pos                                                                 28U
+#define PCC_REG_BLUEWIZ_RSVD_Msk                                                                 (0x7UL << PCC_REG_BLUEWIZ_RSVD_Pos)
+
+#define PCC_REG_BLUEWIZ_R_PON_FEN_BLUEWIZ_Pos                                                    31U
+#define PCC_REG_BLUEWIZ_R_PON_FEN_BLUEWIZ_Msk                                                    (0x1UL << PCC_REG_BLUEWIZ_R_PON_FEN_BLUEWIZ_Pos)
+
+/* 0x3E0    0x4000_03e0
+    7:0     R/W     ENTRY_DELAY_USER_RTC                            8'b0
+    15:8    R/W     RSVD_3                                          8'h0
+    16      R/W     RESERVED_3                                      1'b0
+    17      R/W     RESERVED_2                                      1'b0
+    18      R/W     USER_RTC_CLK_FORCE                              1'b0
+    21:19   R/W     RSVD_2                                          3'b000
+    22      R/W     MULTI_DATA_CMP_OUT                              1'b0
+    24:23   R/W     RSVD_1                                          2'b00
+    25      R/W     R_RTC_GPIO_CLK_SRC_SEL                          1'b0
+    26      R/W     RESERVED_1                                      1'b0
+    27      R/W     RESERVED                                        1'b0
+    30:28   R/W     RSVD                                            3'b000
+    31      R/W     R_PON_FEN_USER_RTC                              1'b0
+ */
+typedef union _PCC_REG_USER_RTC_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t ENTRY_DELAY_USER_RTC: 8;
+        uint32_t RSVD_3: 8;
+        uint32_t RESERVED_3: 1;
+        uint32_t RESERVED_2: 1;
+        uint32_t USER_RTC_CLK_FORCE: 1;
+        uint32_t RSVD_2: 3;
+        uint32_t MULTI_DATA_CMP_OUT: 1;
+        uint32_t RSVD_1: 2;
+        uint32_t R_RTC_GPIO_CLK_SRC_SEL: 1;
+        uint32_t RESERVED_1: 1;
+        uint32_t RESERVED: 1;
+        uint32_t RSVD: 3;
+        uint32_t R_PON_FEN_USER_RTC: 1;
+    };
+} PCC_REG_USER_RTC_TYPE;
+
+/*0x4000_03e0 PCC_REG_USER_RTC*/
+#define PCC_REG_USER_RTC_ENTRY_DELAY_USER_RTC_Pos                                                0U
+#define PCC_REG_USER_RTC_ENTRY_DELAY_USER_RTC_Msk                                                (0xFFUL << PCC_REG_USER_RTC_ENTRY_DELAY_USER_RTC_Pos)
+
+#define PCC_REG_USER_RTC_RSVD_3_Pos                                                              8U
+#define PCC_REG_USER_RTC_RSVD_3_Msk                                                              (0xFFUL << PCC_REG_USER_RTC_RSVD_3_Pos)
+
+#define PCC_REG_USER_RTC_RESERVED_3_Pos                                                          16U
+#define PCC_REG_USER_RTC_RESERVED_3_Msk                                                          (0x1UL << PCC_REG_USER_RTC_RESERVED_3_Pos)
+
+#define PCC_REG_USER_RTC_RESERVED_2_Pos                                                          17U
+#define PCC_REG_USER_RTC_RESERVED_2_Msk                                                          (0x1UL << PCC_REG_USER_RTC_RESERVED_2_Pos)
+
+#define PCC_REG_USER_RTC_USER_RTC_CLK_FORCE_Pos                                                  18U
+#define PCC_REG_USER_RTC_USER_RTC_CLK_FORCE_Msk                                                  (0x1UL << PCC_REG_USER_RTC_USER_RTC_CLK_FORCE_Pos)
+
+#define PCC_REG_USER_RTC_RSVD_2_Pos                                                              19U
+#define PCC_REG_USER_RTC_RSVD_2_Msk                                                              (0x7UL << PCC_REG_USER_RTC_RSVD_2_Pos)
+
+#define PCC_REG_USER_RTC_MULTI_DATA_CMP_OUT_Pos                                                  22U
+#define PCC_REG_USER_RTC_MULTI_DATA_CMP_OUT_Msk                                                  (0x1UL << PCC_REG_USER_RTC_MULTI_DATA_CMP_OUT_Pos)
+
+#define PCC_REG_USER_RTC_RSVD_1_Pos                                                              23U
+#define PCC_REG_USER_RTC_RSVD_1_Msk                                                              (0x3UL << PCC_REG_USER_RTC_RSVD_1_Pos)
+
+#define PCC_REG_USER_RTC_R_RTC_GPIO_CLK_SRC_SEL_Pos                                              25U
+#define PCC_REG_USER_RTC_R_RTC_GPIO_CLK_SRC_SEL_Msk                                              (0x1UL << PCC_REG_USER_RTC_R_RTC_GPIO_CLK_SRC_SEL_Pos)
+
+#define PCC_REG_USER_RTC_RESERVED_1_Pos                                                          26U
+#define PCC_REG_USER_RTC_RESERVED_1_Msk                                                          (0x1UL << PCC_REG_USER_RTC_RESERVED_1_Pos)
+
+#define PCC_REG_USER_RTC_RESERVED_Pos                                                            27U
+#define PCC_REG_USER_RTC_RESERVED_Msk                                                            (0x1UL << PCC_REG_USER_RTC_RESERVED_Pos)
+
+#define PCC_REG_USER_RTC_RSVD_Pos                                                                28U
+#define PCC_REG_USER_RTC_RSVD_Msk                                                                (0x7UL << PCC_REG_USER_RTC_RSVD_Pos)
+
+#define PCC_REG_USER_RTC_R_PON_FEN_USER_RTC_Pos                                                  31U
+#define PCC_REG_USER_RTC_R_PON_FEN_USER_RTC_Msk                                                  (0x1UL << PCC_REG_USER_RTC_R_PON_FEN_USER_RTC_Pos)
+
+/* 0x3E4    0x4000_03e4
+    7:0     R/W     ENTRY_DELAY_RAP                                 8'b0
+    15:8    R/W     RSVD_2                                          8'h0
+    16      R/W     RESERVED_7                                      1'b0
+    17      R/W     RESERVED_6                                      1'b0
+    18      R/W     RAP_CLK_FORCE                                   1'b0
+    21:19   R/W     RSVD_1                                          3'b000
+    22      R/W     RESERVED_5                                      1'b0
+    23      R/W     RESERVED_4                                      1'b0
+    24      R/W     RESERVED_3                                      1'b0
+    25      R/W     RESERVED_2                                      1'b0
+    26      R/W     RESERVED_1                                      1'b0
+    27      R/W     RESERVED                                        1'b0
+    30:28   R/W     RSVD                                            3'b000
+    31      R/W     R_PON_FEN_RAP                                   1'b0
+ */
+typedef union _PCC_REG_RAP_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t ENTRY_DELAY_RAP: 8;
+        uint32_t RSVD_2: 8;
+        uint32_t RESERVED_7: 1;
+        uint32_t RESERVED_6: 1;
+        uint32_t RAP_CLK_FORCE: 1;
+        uint32_t RSVD_1: 3;
+        uint32_t RESERVED_5: 1;
+        uint32_t RESERVED_4: 1;
+        uint32_t RESERVED_3: 1;
+        uint32_t RESERVED_2: 1;
+        uint32_t RESERVED_1: 1;
+        uint32_t RESERVED: 1;
+        uint32_t RSVD: 3;
+        uint32_t R_PON_FEN_RAP: 1;
+    };
+} PCC_REG_RAP_TYPE;
+
+/*0x4000_03e4 PCC_REG_RAP*/
+#define PCC_REG_RAP_ENTRY_DELAY_RAP_Pos                                                          0U
+#define PCC_REG_RAP_ENTRY_DELAY_RAP_Msk                                                          (0xFFUL << PCC_REG_RAP_ENTRY_DELAY_RAP_Pos)
+
+#define PCC_REG_RAP_RSVD_2_Pos                                                                   8U
+#define PCC_REG_RAP_RSVD_2_Msk                                                                   (0xFFUL << PCC_REG_RAP_RSVD_2_Pos)
+
+#define PCC_REG_RAP_RESERVED_7_Pos                                                               16U
+#define PCC_REG_RAP_RESERVED_7_Msk                                                               (0x1UL << PCC_REG_RAP_RESERVED_7_Pos)
+
+#define PCC_REG_RAP_RESERVED_6_Pos                                                               17U
+#define PCC_REG_RAP_RESERVED_6_Msk                                                               (0x1UL << PCC_REG_RAP_RESERVED_6_Pos)
+
+#define PCC_REG_RAP_RAP_CLK_FORCE_Pos                                                            18U
+#define PCC_REG_RAP_RAP_CLK_FORCE_Msk                                                            (0x1UL << PCC_REG_RAP_RAP_CLK_FORCE_Pos)
+
+#define PCC_REG_RAP_RSVD_1_Pos                                                                   19U
+#define PCC_REG_RAP_RSVD_1_Msk                                                                   (0x7UL << PCC_REG_RAP_RSVD_1_Pos)
+
+#define PCC_REG_RAP_RESERVED_5_Pos                                                               22U
+#define PCC_REG_RAP_RESERVED_5_Msk                                                               (0x1UL << PCC_REG_RAP_RESERVED_5_Pos)
+
+#define PCC_REG_RAP_RESERVED_4_Pos                                                               23U
+#define PCC_REG_RAP_RESERVED_4_Msk                                                               (0x1UL << PCC_REG_RAP_RESERVED_4_Pos)
+
+#define PCC_REG_RAP_RESERVED_3_Pos                                                               24U
+#define PCC_REG_RAP_RESERVED_3_Msk                                                               (0x1UL << PCC_REG_RAP_RESERVED_3_Pos)
+
+#define PCC_REG_RAP_RESERVED_2_Pos                                                               25U
+#define PCC_REG_RAP_RESERVED_2_Msk                                                               (0x1UL << PCC_REG_RAP_RESERVED_2_Pos)
+
+#define PCC_REG_RAP_RESERVED_1_Pos                                                               26U
+#define PCC_REG_RAP_RESERVED_1_Msk                                                               (0x1UL << PCC_REG_RAP_RESERVED_1_Pos)
+
+#define PCC_REG_RAP_RESERVED_Pos                                                                 27U
+#define PCC_REG_RAP_RESERVED_Msk                                                                 (0x1UL << PCC_REG_RAP_RESERVED_Pos)
+
+#define PCC_REG_RAP_RSVD_Pos                                                                     28U
+#define PCC_REG_RAP_RSVD_Msk                                                                     (0x7UL << PCC_REG_RAP_RSVD_Pos)
+
+#define PCC_REG_RAP_R_PON_FEN_RAP_Pos                                                            31U
+#define PCC_REG_RAP_R_PON_FEN_RAP_Msk                                                            (0x1UL << PCC_REG_RAP_R_PON_FEN_RAP_Pos)
+
+/* 0x3E8    0x4000_03e8
+    7:0     R/W     ENTRY_DELAY_SCHPLN                              8'b0
+    15:8    R/W     RSVD_2                                          8'h0
+    16      R/W     RESERVED_6                                      1'b1
+    17      R/W     RESERVED_5                                      1'b1
+    18      R/W     SCHPLN_CLK_FORCE                                1'b0
+    21:19   R/W     RSVD_1                                          3'b000
+    22      R/W     RESERVED_4                                      1'b0
+    23      R/W     RESERVED_3                                      1'b0
+    24      R/W     RESERVED_2                                      1'b0
+    25      R/W     RESERVED_1                                      1'b0
+    26      R/W     RESERVED                                        1'b0
+    27      R/W     R_PON_FEN_SCHPLN                                1'b0
+    30:28   R/W     RSVD                                            3'b000
+    31      R/W     R_PON_FEN_GTC                                   1'b1
+ */
+typedef union _PCC_REG_GTC_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t ENTRY_DELAY_SCHPLN: 8;
+        uint32_t RSVD_2: 8;
+        uint32_t RESERVED_6: 1;
+        uint32_t RESERVED_5: 1;
+        uint32_t SCHPLN_CLK_FORCE: 1;
+        uint32_t RSVD_1: 3;
+        uint32_t RESERVED_4: 1;
+        uint32_t RESERVED_3: 1;
+        uint32_t RESERVED_2: 1;
+        uint32_t RESERVED_1: 1;
+        uint32_t RESERVED: 1;
+        uint32_t R_PON_FEN_SCHPLN: 1;
+        uint32_t RSVD: 3;
+        uint32_t R_PON_FEN_GTC: 1;
+    };
+} PCC_REG_GTC_TYPE;
+
+/*0x4000_03e8 PCC_REG_GTC*/
+#define PCC_REG_GTC_ENTRY_DELAY_SCHPLN_Pos                                                       0U
+#define PCC_REG_GTC_ENTRY_DELAY_SCHPLN_Msk                                                       (0xFFUL << PCC_REG_GTC_ENTRY_DELAY_SCHPLN_Pos)
+
+#define PCC_REG_GTC_RSVD_2_Pos                                                                   8U
+#define PCC_REG_GTC_RSVD_2_Msk                                                                   (0xFFUL << PCC_REG_GTC_RSVD_2_Pos)
+
+#define PCC_REG_GTC_RESERVED_6_Pos                                                               16U
+#define PCC_REG_GTC_RESERVED_6_Msk                                                               (0x1UL << PCC_REG_GTC_RESERVED_6_Pos)
+
+#define PCC_REG_GTC_RESERVED_5_Pos                                                               17U
+#define PCC_REG_GTC_RESERVED_5_Msk                                                               (0x1UL << PCC_REG_GTC_RESERVED_5_Pos)
+
+#define PCC_REG_GTC_SCHPLN_CLK_FORCE_Pos                                                         18U
+#define PCC_REG_GTC_SCHPLN_CLK_FORCE_Msk                                                         (0x1UL << PCC_REG_GTC_SCHPLN_CLK_FORCE_Pos)
+
+#define PCC_REG_GTC_RSVD_1_Pos                                                                   19U
+#define PCC_REG_GTC_RSVD_1_Msk                                                                   (0x7UL << PCC_REG_GTC_RSVD_1_Pos)
+
+#define PCC_REG_GTC_RESERVED_4_Pos                                                               22U
+#define PCC_REG_GTC_RESERVED_4_Msk                                                               (0x1UL << PCC_REG_GTC_RESERVED_4_Pos)
+
+#define PCC_REG_GTC_RESERVED_3_Pos                                                               23U
+#define PCC_REG_GTC_RESERVED_3_Msk                                                               (0x1UL << PCC_REG_GTC_RESERVED_3_Pos)
+
+#define PCC_REG_GTC_RESERVED_2_Pos                                                               24U
+#define PCC_REG_GTC_RESERVED_2_Msk                                                               (0x1UL << PCC_REG_GTC_RESERVED_2_Pos)
+
+#define PCC_REG_GTC_RESERVED_1_Pos                                                               25U
+#define PCC_REG_GTC_RESERVED_1_Msk                                                               (0x1UL << PCC_REG_GTC_RESERVED_1_Pos)
+
+#define PCC_REG_GTC_RESERVED_Pos                                                                 26U
+#define PCC_REG_GTC_RESERVED_Msk                                                                 (0x1UL << PCC_REG_GTC_RESERVED_Pos)
+
+#define PCC_REG_GTC_R_PON_FEN_SCHPLN_Pos                                                         27U
+#define PCC_REG_GTC_R_PON_FEN_SCHPLN_Msk                                                         (0x1UL << PCC_REG_GTC_R_PON_FEN_SCHPLN_Pos)
+
+#define PCC_REG_GTC_RSVD_Pos                                                                     28U
+#define PCC_REG_GTC_RSVD_Msk                                                                     (0x7UL << PCC_REG_GTC_RSVD_Pos)
+
+#define PCC_REG_GTC_R_PON_FEN_GTC_Pos                                                            31U
+#define PCC_REG_GTC_R_PON_FEN_GTC_Msk                                                            (0x1UL << PCC_REG_GTC_R_PON_FEN_GTC_Pos)
+
+/* 0x3EC    0x4000_03ec
+    7:0     R/W     ENTRY_DELAY_CAL32K                              8'b0
+    15:8    R/W     RSVD_2                                          8'h0
+    16      R/W     RESERVED_7                                      1'b0
+    17      R/W     RESERVED_6                                      1'b0
+    18      R/W     SDM_CLK_FORCE                                   1'b0
+    21:19   R/W     RSVD_1                                          3'b000
+    22      R/W     RESERVED_5                                      1'b0
+    23      R/W     RESERVED_4                                      1'b0
+    24      R/W     RESERVED_3                                      1'b0
+    25      R/W     RESERVED_2                                      1'b0
+    26      R/W     RESERVED_1                                      1'b0
+    27      R/W     RESERVED                                        1'b0
+    30:28   R/W     RSVD                                            3'b000
+    31      R/W     R_PON_FEN_CAL32K_VPON                           1'b0
+ */
+typedef union _PCC_REG_SDM_VPON_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t ENTRY_DELAY_CAL32K: 8;
+        uint32_t RSVD_2: 8;
+        uint32_t RESERVED_7: 1;
+        uint32_t RESERVED_6: 1;
+        uint32_t SDM_CLK_FORCE: 1;
+        uint32_t RSVD_1: 3;
+        uint32_t RESERVED_5: 1;
+        uint32_t RESERVED_4: 1;
+        uint32_t RESERVED_3: 1;
+        uint32_t RESERVED_2: 1;
+        uint32_t RESERVED_1: 1;
+        uint32_t RESERVED: 1;
+        uint32_t RSVD: 3;
+        uint32_t R_PON_FEN_CAL32K_VPON: 1;
+    };
+} PCC_REG_SDM_VPON_TYPE;
+
+/*0x4000_03ec PCC_REG_SDM_VPON*/
+#define PCC_REG_SDM_VPON_ENTRY_DELAY_CAL32K_Pos                                                  0U
+#define PCC_REG_SDM_VPON_ENTRY_DELAY_CAL32K_Msk                                                  (0xFFUL << PCC_REG_SDM_VPON_ENTRY_DELAY_CAL32K_Pos)
+
+#define PCC_REG_SDM_VPON_RSVD_2_Pos                                                              8U
+#define PCC_REG_SDM_VPON_RSVD_2_Msk                                                              (0xFFUL << PCC_REG_SDM_VPON_RSVD_2_Pos)
+
+#define PCC_REG_SDM_VPON_RESERVED_7_Pos                                                          16U
+#define PCC_REG_SDM_VPON_RESERVED_7_Msk                                                          (0x1UL << PCC_REG_SDM_VPON_RESERVED_7_Pos)
+
+#define PCC_REG_SDM_VPON_RESERVED_6_Pos                                                          17U
+#define PCC_REG_SDM_VPON_RESERVED_6_Msk                                                          (0x1UL << PCC_REG_SDM_VPON_RESERVED_6_Pos)
+
+#define PCC_REG_SDM_VPON_SDM_CLK_FORCE_Pos                                                       18U
+#define PCC_REG_SDM_VPON_SDM_CLK_FORCE_Msk                                                       (0x1UL << PCC_REG_SDM_VPON_SDM_CLK_FORCE_Pos)
+
+#define PCC_REG_SDM_VPON_RSVD_1_Pos                                                              19U
+#define PCC_REG_SDM_VPON_RSVD_1_Msk                                                              (0x7UL << PCC_REG_SDM_VPON_RSVD_1_Pos)
+
+#define PCC_REG_SDM_VPON_RESERVED_5_Pos                                                          22U
+#define PCC_REG_SDM_VPON_RESERVED_5_Msk                                                          (0x1UL << PCC_REG_SDM_VPON_RESERVED_5_Pos)
+
+#define PCC_REG_SDM_VPON_RESERVED_4_Pos                                                          23U
+#define PCC_REG_SDM_VPON_RESERVED_4_Msk                                                          (0x1UL << PCC_REG_SDM_VPON_RESERVED_4_Pos)
+
+#define PCC_REG_SDM_VPON_RESERVED_3_Pos                                                          24U
+#define PCC_REG_SDM_VPON_RESERVED_3_Msk                                                          (0x1UL << PCC_REG_SDM_VPON_RESERVED_3_Pos)
+
+#define PCC_REG_SDM_VPON_RESERVED_2_Pos                                                          25U
+#define PCC_REG_SDM_VPON_RESERVED_2_Msk                                                          (0x1UL << PCC_REG_SDM_VPON_RESERVED_2_Pos)
+
+#define PCC_REG_SDM_VPON_RESERVED_1_Pos                                                          26U
+#define PCC_REG_SDM_VPON_RESERVED_1_Msk                                                          (0x1UL << PCC_REG_SDM_VPON_RESERVED_1_Pos)
+
+#define PCC_REG_SDM_VPON_RESERVED_Pos                                                            27U
+#define PCC_REG_SDM_VPON_RESERVED_Msk                                                            (0x1UL << PCC_REG_SDM_VPON_RESERVED_Pos)
+
+#define PCC_REG_SDM_VPON_RSVD_Pos                                                                28U
+#define PCC_REG_SDM_VPON_RSVD_Msk                                                                (0x7UL << PCC_REG_SDM_VPON_RSVD_Pos)
+
+#define PCC_REG_SDM_VPON_R_PON_FEN_CAL32K_VPON_Pos                                               31U
+#define PCC_REG_SDM_VPON_R_PON_FEN_CAL32K_VPON_Msk                                               (0x1UL << PCC_REG_SDM_VPON_R_PON_FEN_CAL32K_VPON_Pos)
+
+/* 0x3F0    0x4000_03f0
+    7:0     R/W     ENTRY_DELAY_WDT                                 8'b0
+    15:8    R/W     RSVD_2                                          8'h0
+    16      R/W     RESERVED_7                                      1'b0
+    17      R/W     RESERVED_6                                      1'b1
+    18      R/W     WDT_CLK_FORCE                                   1'b0
+    21:19   R/W     RSVD_1                                          3'b000
+    22      R/W     RESERVED_5                                      1'b0
+    23      R/W     RESERVED_4                                      1'b0
+    24      R/W     RESERVED_3                                      1'b0
+    25      R/W     RESERVED_2                                      1'b0
+    26      R/W     RESERVED_1                                      1'b0
+    27      R/W     RESERVED                                        1'b0
+    30:28   R/W     RSVD                                            3'b000
+    31      R/W     R_PON_FEN_WDT                                   1'b0
+ */
+typedef union _PCC_REG_LPWDT_VPON_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t ENTRY_DELAY_WDT: 8;
+        uint32_t RSVD_2: 8;
+        uint32_t RESERVED_7: 1;
+        uint32_t RESERVED_6: 1;
+        uint32_t WDT_CLK_FORCE: 1;
+        uint32_t RSVD_1: 3;
+        uint32_t RESERVED_5: 1;
+        uint32_t RESERVED_4: 1;
+        uint32_t RESERVED_3: 1;
+        uint32_t RESERVED_2: 1;
+        uint32_t RESERVED_1: 1;
+        uint32_t RESERVED: 1;
+        uint32_t RSVD: 3;
+        uint32_t R_PON_FEN_WDT: 1;
+    };
+} PCC_REG_LPWDT_VPON_TYPE;
+
+/*0x4000_03f0 PCC_REG_LPWDT_VPON*/
+#define PCC_REG_LPWDT_VPON_ENTRY_DELAY_WDT_Pos                                                   0U
+#define PCC_REG_LPWDT_VPON_ENTRY_DELAY_WDT_Msk                                                   (0xFFUL << PCC_REG_LPWDT_VPON_ENTRY_DELAY_WDT_Pos)
+
+#define PCC_REG_LPWDT_VPON_RSVD_2_Pos                                                            8U
+#define PCC_REG_LPWDT_VPON_RSVD_2_Msk                                                            (0xFFUL << PCC_REG_LPWDT_VPON_RSVD_2_Pos)
+
+#define PCC_REG_LPWDT_VPON_RESERVED_7_Pos                                                        16U
+#define PCC_REG_LPWDT_VPON_RESERVED_7_Msk                                                        (0x1UL << PCC_REG_LPWDT_VPON_RESERVED_7_Pos)
+
+#define PCC_REG_LPWDT_VPON_RESERVED_6_Pos                                                        17U
+#define PCC_REG_LPWDT_VPON_RESERVED_6_Msk                                                        (0x1UL << PCC_REG_LPWDT_VPON_RESERVED_6_Pos)
+
+#define PCC_REG_LPWDT_VPON_WDT_CLK_FORCE_Pos                                                     18U
+#define PCC_REG_LPWDT_VPON_WDT_CLK_FORCE_Msk                                                     (0x1UL << PCC_REG_LPWDT_VPON_WDT_CLK_FORCE_Pos)
+
+#define PCC_REG_LPWDT_VPON_RSVD_1_Pos                                                            19U
+#define PCC_REG_LPWDT_VPON_RSVD_1_Msk                                                            (0x7UL << PCC_REG_LPWDT_VPON_RSVD_1_Pos)
+
+#define PCC_REG_LPWDT_VPON_RESERVED_5_Pos                                                        22U
+#define PCC_REG_LPWDT_VPON_RESERVED_5_Msk                                                        (0x1UL << PCC_REG_LPWDT_VPON_RESERVED_5_Pos)
+
+#define PCC_REG_LPWDT_VPON_RESERVED_4_Pos                                                        23U
+#define PCC_REG_LPWDT_VPON_RESERVED_4_Msk                                                        (0x1UL << PCC_REG_LPWDT_VPON_RESERVED_4_Pos)
+
+#define PCC_REG_LPWDT_VPON_RESERVED_3_Pos                                                        24U
+#define PCC_REG_LPWDT_VPON_RESERVED_3_Msk                                                        (0x1UL << PCC_REG_LPWDT_VPON_RESERVED_3_Pos)
+
+#define PCC_REG_LPWDT_VPON_RESERVED_2_Pos                                                        25U
+#define PCC_REG_LPWDT_VPON_RESERVED_2_Msk                                                        (0x1UL << PCC_REG_LPWDT_VPON_RESERVED_2_Pos)
+
+#define PCC_REG_LPWDT_VPON_RESERVED_1_Pos                                                        26U
+#define PCC_REG_LPWDT_VPON_RESERVED_1_Msk                                                        (0x1UL << PCC_REG_LPWDT_VPON_RESERVED_1_Pos)
+
+#define PCC_REG_LPWDT_VPON_RESERVED_Pos                                                          27U
+#define PCC_REG_LPWDT_VPON_RESERVED_Msk                                                          (0x1UL << PCC_REG_LPWDT_VPON_RESERVED_Pos)
+
+#define PCC_REG_LPWDT_VPON_RSVD_Pos                                                              28U
+#define PCC_REG_LPWDT_VPON_RSVD_Msk                                                              (0x7UL << PCC_REG_LPWDT_VPON_RSVD_Pos)
+
+#define PCC_REG_LPWDT_VPON_R_PON_FEN_WDT_Pos                                                     31U
+#define PCC_REG_LPWDT_VPON_R_PON_FEN_WDT_Msk                                                     (0x1UL << PCC_REG_LPWDT_VPON_R_PON_FEN_WDT_Pos)
+
+/* 0x3F4    0x4000_03f4
+    28:0    R/W     RESERVED                                        29'h0
+    31:29   R/W     AON_HF_DIV_SEL                                  3'b000
+ */
+typedef union _PCC_REG_PERION_CLK_AON_REG0X_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED: 29;
+        uint32_t AON_HF_DIV_SEL: 3;
+    };
+} PCC_REG_PERION_CLK_AON_REG0X_TYPE;
+
+/*0x4000_03f4 PCC_REG_PERION_CLK_AON_REG0X*/
+#define PCC_REG_PERION_CLK_AON_REG0X_RESERVED_Pos                                                0U
+#define PCC_REG_PERION_CLK_AON_REG0X_RESERVED_Msk                                                (0x1FFFFFFFUL << PCC_REG_PERION_CLK_AON_REG0X_RESERVED_Pos)
+
+#define PCC_REG_PERION_CLK_AON_REG0X_AON_HF_DIV_SEL_Pos                                          29U
+#define PCC_REG_PERION_CLK_AON_REG0X_AON_HF_DIV_SEL_Msk                                          (0x7UL << PCC_REG_PERION_CLK_AON_REG0X_AON_HF_DIV_SEL_Pos)
+
+/* 0x3F8    0x4000_03f8
+    0       R/W     RESERVED_15                                     1'b0
+    1       R/W     RESERVED_14                                     1'b0
+    2       R/W     RESERVED_13                                     1'b0
+    3       R/W     RESERVED_12                                     1'b0
+    4       R/W     RESERVED_11                                     1'b0
+    5       R/W     RESERVED_10                                     1'b0
+    15:6    R/W     RSVD_2                                          10'h0
+    16      R/W     RESERVED_9                                      1'b0
+    17      R/W     RESERVED_8                                      1'b0
+    18      R/W     RESERVED_7                                      1'b1
+    21:19   R/W     RSVD_1                                          3'b000
+    22      R/W     RESERVED_6                                      1'b0
+    23      R/W     RESERVED_5                                      1'b0
+    24      R/W     RESERVED_4                                      1'b0
+    25      R/W     RESERVED_3                                      1'b0
+    26      R/W     RESERVED_2                                      1'b0
+    27      R/W     RESERVED_1                                      1'b0
+    30:28   R/W     RSVD                                            3'b000
+    31      R/W     RESERVED                                        1'b0
+ */
+typedef union _PCC_REG_PCK600_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED_15: 1;
+        uint32_t RESERVED_14: 1;
+        uint32_t RESERVED_13: 1;
+        uint32_t RESERVED_12: 1;
+        uint32_t RESERVED_11: 1;
+        uint32_t RESERVED_10: 1;
+        uint32_t RSVD_2: 10;
+        uint32_t RESERVED_9: 1;
+        uint32_t RESERVED_8: 1;
+        uint32_t RESERVED_7: 1;
+        uint32_t RSVD_1: 3;
+        uint32_t RESERVED_6: 1;
+        uint32_t RESERVED_5: 1;
+        uint32_t RESERVED_4: 1;
+        uint32_t RESERVED_3: 1;
+        uint32_t RESERVED_2: 1;
+        uint32_t RESERVED_1: 1;
+        uint32_t RSVD: 3;
+        uint32_t RESERVED: 1;
+    };
+} PCC_REG_PCK600_TYPE;
+
+/*0x4000_03f8 PCC_REG_PCK600*/
+#define PCC_REG_PCK600_RESERVED_15_Pos                                                           0U
+#define PCC_REG_PCK600_RESERVED_15_Msk                                                           (0x1UL << PCC_REG_PCK600_RESERVED_15_Pos)
+
+#define PCC_REG_PCK600_RESERVED_14_Pos                                                           1U
+#define PCC_REG_PCK600_RESERVED_14_Msk                                                           (0x1UL << PCC_REG_PCK600_RESERVED_14_Pos)
+
+#define PCC_REG_PCK600_RESERVED_13_Pos                                                           2U
+#define PCC_REG_PCK600_RESERVED_13_Msk                                                           (0x1UL << PCC_REG_PCK600_RESERVED_13_Pos)
+
+#define PCC_REG_PCK600_RESERVED_12_Pos                                                           3U
+#define PCC_REG_PCK600_RESERVED_12_Msk                                                           (0x1UL << PCC_REG_PCK600_RESERVED_12_Pos)
+
+#define PCC_REG_PCK600_RESERVED_11_Pos                                                           4U
+#define PCC_REG_PCK600_RESERVED_11_Msk                                                           (0x1UL << PCC_REG_PCK600_RESERVED_11_Pos)
+
+#define PCC_REG_PCK600_RESERVED_10_Pos                                                           5U
+#define PCC_REG_PCK600_RESERVED_10_Msk                                                           (0x1UL << PCC_REG_PCK600_RESERVED_10_Pos)
+
+#define PCC_REG_PCK600_RSVD_2_Pos                                                                6U
+#define PCC_REG_PCK600_RSVD_2_Msk                                                                (0x3FFUL << PCC_REG_PCK600_RSVD_2_Pos)
+
+#define PCC_REG_PCK600_RESERVED_9_Pos                                                            16U
+#define PCC_REG_PCK600_RESERVED_9_Msk                                                            (0x1UL << PCC_REG_PCK600_RESERVED_9_Pos)
+
+#define PCC_REG_PCK600_RESERVED_8_Pos                                                            17U
+#define PCC_REG_PCK600_RESERVED_8_Msk                                                            (0x1UL << PCC_REG_PCK600_RESERVED_8_Pos)
+
+#define PCC_REG_PCK600_RESERVED_7_Pos                                                            18U
+#define PCC_REG_PCK600_RESERVED_7_Msk                                                            (0x1UL << PCC_REG_PCK600_RESERVED_7_Pos)
+
+#define PCC_REG_PCK600_RSVD_1_Pos                                                                19U
+#define PCC_REG_PCK600_RSVD_1_Msk                                                                (0x7UL << PCC_REG_PCK600_RSVD_1_Pos)
+
+#define PCC_REG_PCK600_RESERVED_6_Pos                                                            22U
+#define PCC_REG_PCK600_RESERVED_6_Msk                                                            (0x1UL << PCC_REG_PCK600_RESERVED_6_Pos)
+
+#define PCC_REG_PCK600_RESERVED_5_Pos                                                            23U
+#define PCC_REG_PCK600_RESERVED_5_Msk                                                            (0x1UL << PCC_REG_PCK600_RESERVED_5_Pos)
+
+#define PCC_REG_PCK600_RESERVED_4_Pos                                                            24U
+#define PCC_REG_PCK600_RESERVED_4_Msk                                                            (0x1UL << PCC_REG_PCK600_RESERVED_4_Pos)
+
+#define PCC_REG_PCK600_RESERVED_3_Pos                                                            25U
+#define PCC_REG_PCK600_RESERVED_3_Msk                                                            (0x1UL << PCC_REG_PCK600_RESERVED_3_Pos)
+
+#define PCC_REG_PCK600_RESERVED_2_Pos                                                            26U
+#define PCC_REG_PCK600_RESERVED_2_Msk                                                            (0x1UL << PCC_REG_PCK600_RESERVED_2_Pos)
+
+#define PCC_REG_PCK600_RESERVED_1_Pos                                                            27U
+#define PCC_REG_PCK600_RESERVED_1_Msk                                                            (0x1UL << PCC_REG_PCK600_RESERVED_1_Pos)
+
+#define PCC_REG_PCK600_RSVD_Pos                                                                  28U
+#define PCC_REG_PCK600_RSVD_Msk                                                                  (0x7UL << PCC_REG_PCK600_RSVD_Pos)
+
+#define PCC_REG_PCK600_RESERVED_Pos                                                              31U
+#define PCC_REG_PCK600_RESERVED_Msk                                                              (0x1UL << PCC_REG_PCK600_RESERVED_Pos)
+
+/* 0x3FC    0x4000_03fc
+    7:0     R/W     ENTRY_DELAY_DEV_LPC                             8'b0
+    15:8    R/W     RSVD_2                                          8'h0
+    16      R/W     RESERVED_7                                      1'b0
+    17      R/W     RESERVED_6                                      1'b0
+    18      R/W     LPC_CLK_FORCE                                   1'b0
+    21:19   R/W     RSVD_1                                          3'b000
+    22      R/W     RESERVED_5                                      1'b0
+    23      R/W     RESERVED_4                                      1'b0
+    24      R/W     RESERVED_3                                      1'b0
+    25      R/W     RESERVED_2                                      1'b0
+    26      R/W     RESERVED_1                                      1'b0
+    27      R/W     RESERVED                                        1'b0
+    30:28   R/W     RSVD                                            3'b000
+    31      R/W     R_PON_FEN_LPC                                   1'b0
+ */
+typedef union _PCC_REG_LPC_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t ENTRY_DELAY_DEV_LPC: 8;
+        uint32_t RSVD_2: 8;
+        uint32_t RESERVED_7: 1;
+        uint32_t RESERVED_6: 1;
+        uint32_t LPC_CLK_FORCE: 1;
+        uint32_t RSVD_1: 3;
+        uint32_t RESERVED_5: 1;
+        uint32_t RESERVED_4: 1;
+        uint32_t RESERVED_3: 1;
+        uint32_t RESERVED_2: 1;
+        uint32_t RESERVED_1: 1;
+        uint32_t RESERVED: 1;
+        uint32_t RSVD: 3;
+        uint32_t R_PON_FEN_LPC: 1;
+    };
+} PCC_REG_LPC_TYPE;
+
+/*0x4000_03fc PCC_REG_LPC*/
+#define PCC_REG_LPC_ENTRY_DELAY_DEV_LPC_Pos                                                      0U
+#define PCC_REG_LPC_ENTRY_DELAY_DEV_LPC_Msk                                                      (0xFFUL << PCC_REG_LPC_ENTRY_DELAY_DEV_LPC_Pos)
+
+#define PCC_REG_LPC_RSVD_2_Pos                                                                   8U
+#define PCC_REG_LPC_RSVD_2_Msk                                                                   (0xFFUL << PCC_REG_LPC_RSVD_2_Pos)
+
+#define PCC_REG_LPC_RESERVED_7_Pos                                                               16U
+#define PCC_REG_LPC_RESERVED_7_Msk                                                               (0x1UL << PCC_REG_LPC_RESERVED_7_Pos)
+
+#define PCC_REG_LPC_RESERVED_6_Pos                                                               17U
+#define PCC_REG_LPC_RESERVED_6_Msk                                                               (0x1UL << PCC_REG_LPC_RESERVED_6_Pos)
+
+#define PCC_REG_LPC_LPC_CLK_FORCE_Pos                                                            18U
+#define PCC_REG_LPC_LPC_CLK_FORCE_Msk                                                            (0x1UL << PCC_REG_LPC_LPC_CLK_FORCE_Pos)
+
+#define PCC_REG_LPC_RSVD_1_Pos                                                                   19U
+#define PCC_REG_LPC_RSVD_1_Msk                                                                   (0x7UL << PCC_REG_LPC_RSVD_1_Pos)
+
+#define PCC_REG_LPC_RESERVED_5_Pos                                                               22U
+#define PCC_REG_LPC_RESERVED_5_Msk                                                               (0x1UL << PCC_REG_LPC_RESERVED_5_Pos)
+
+#define PCC_REG_LPC_RESERVED_4_Pos                                                               23U
+#define PCC_REG_LPC_RESERVED_4_Msk                                                               (0x1UL << PCC_REG_LPC_RESERVED_4_Pos)
+
+#define PCC_REG_LPC_RESERVED_3_Pos                                                               24U
+#define PCC_REG_LPC_RESERVED_3_Msk                                                               (0x1UL << PCC_REG_LPC_RESERVED_3_Pos)
+
+#define PCC_REG_LPC_RESERVED_2_Pos                                                               25U
+#define PCC_REG_LPC_RESERVED_2_Msk                                                               (0x1UL << PCC_REG_LPC_RESERVED_2_Pos)
+
+#define PCC_REG_LPC_RESERVED_1_Pos                                                               26U
+#define PCC_REG_LPC_RESERVED_1_Msk                                                               (0x1UL << PCC_REG_LPC_RESERVED_1_Pos)
+
+#define PCC_REG_LPC_RESERVED_Pos                                                                 27U
+#define PCC_REG_LPC_RESERVED_Msk                                                                 (0x1UL << PCC_REG_LPC_RESERVED_Pos)
+
+#define PCC_REG_LPC_RSVD_Pos                                                                     28U
+#define PCC_REG_LPC_RSVD_Msk                                                                     (0x7UL << PCC_REG_LPC_RSVD_Pos)
+
+#define PCC_REG_LPC_R_PON_FEN_LPC_Pos                                                            31U
+#define PCC_REG_LPC_R_PON_FEN_LPC_Msk                                                            (0x1UL << PCC_REG_LPC_R_PON_FEN_LPC_Pos)
+
+/* 0x2C0    0x4000_02c0
+    7:0     R/W     R_PMUX_GPIO_P0_0                                8'h00
+    15:8    R/W     R_PMUX_GPIO_P0_1                                8'h00
+    23:16   R/W     R_PMUX_GPIO_P0_2                                8'h00
+    31:24   R/W     R_PMUX_GPIO_P0_3                                8'h1D
+ */
+typedef union _PCC_r_PMUX_GPIO_P0_0to3_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t R_PMUX_GPIO_P0_0: 8;
+        uint32_t R_PMUX_GPIO_P0_1: 8;
+        uint32_t R_PMUX_GPIO_P0_2: 8;
+        uint32_t R_PMUX_GPIO_P0_3: 8;
+    };
+} PCC_r_PMUX_GPIO_P0_0to3_TYPE;
+
+/*0x4000_02c0 PCC_r_PMUX_GPIO_P0_0to3*/
+#define PCC_r_PMUX_GPIO_P0_0to3_R_PMUX_GPIO_P0_0_Pos                                             0U
+#define PCC_r_PMUX_GPIO_P0_0to3_R_PMUX_GPIO_P0_0_Msk                                             (0xFFUL << PCC_r_PMUX_GPIO_P0_0to3_R_PMUX_GPIO_P0_0_Pos)
+
+#define PCC_r_PMUX_GPIO_P0_0to3_R_PMUX_GPIO_P0_1_Pos                                             8U
+#define PCC_r_PMUX_GPIO_P0_0to3_R_PMUX_GPIO_P0_1_Msk                                             (0xFFUL << PCC_r_PMUX_GPIO_P0_0to3_R_PMUX_GPIO_P0_1_Pos)
+
+#define PCC_r_PMUX_GPIO_P0_0to3_R_PMUX_GPIO_P0_2_Pos                                             16U
+#define PCC_r_PMUX_GPIO_P0_0to3_R_PMUX_GPIO_P0_2_Msk                                             (0xFFUL << PCC_r_PMUX_GPIO_P0_0to3_R_PMUX_GPIO_P0_2_Pos)
+
+#define PCC_r_PMUX_GPIO_P0_0to3_R_PMUX_GPIO_P0_3_Pos                                             24U
+#define PCC_r_PMUX_GPIO_P0_0to3_R_PMUX_GPIO_P0_3_Msk                                             (0xFFUL << PCC_r_PMUX_GPIO_P0_0to3_R_PMUX_GPIO_P0_3_Pos)
+
+/* 0x2C4    0x4000_02c4
+    7:0     R/W     R_PMUX_GPIO_P0_4                                8'h00
+    15:8    R/W     R_PMUX_GPIO_P0_5                                8'h00
+    23:16   R/W     R_PMUX_GPIO_P0_6                                8'h00
+    31:24   R/W     R_PMUX_GPIO_P0_7                                8'h00
+ */
+typedef union _PCC_r_PMUX_GPIO_P0_4to7_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t R_PMUX_GPIO_P0_4: 8;
+        uint32_t R_PMUX_GPIO_P0_5: 8;
+        uint32_t R_PMUX_GPIO_P0_6: 8;
+        uint32_t R_PMUX_GPIO_P0_7: 8;
+    };
+} PCC_r_PMUX_GPIO_P0_4to7_TYPE;
+
+/*0x4000_02c4 PCC_r_PMUX_GPIO_P0_4to7*/
+#define PCC_r_PMUX_GPIO_P0_4to7_R_PMUX_GPIO_P0_4_Pos                                             0U
+#define PCC_r_PMUX_GPIO_P0_4to7_R_PMUX_GPIO_P0_4_Msk                                             (0xFFUL << PCC_r_PMUX_GPIO_P0_4to7_R_PMUX_GPIO_P0_4_Pos)
+
+#define PCC_r_PMUX_GPIO_P0_4to7_R_PMUX_GPIO_P0_5_Pos                                             8U
+#define PCC_r_PMUX_GPIO_P0_4to7_R_PMUX_GPIO_P0_5_Msk                                             (0xFFUL << PCC_r_PMUX_GPIO_P0_4to7_R_PMUX_GPIO_P0_5_Pos)
+
+#define PCC_r_PMUX_GPIO_P0_4to7_R_PMUX_GPIO_P0_6_Pos                                             16U
+#define PCC_r_PMUX_GPIO_P0_4to7_R_PMUX_GPIO_P0_6_Msk                                             (0xFFUL << PCC_r_PMUX_GPIO_P0_4to7_R_PMUX_GPIO_P0_6_Pos)
+
+#define PCC_r_PMUX_GPIO_P0_4to7_R_PMUX_GPIO_P0_7_Pos                                             24U
+#define PCC_r_PMUX_GPIO_P0_4to7_R_PMUX_GPIO_P0_7_Msk                                             (0xFFUL << PCC_r_PMUX_GPIO_P0_4to7_R_PMUX_GPIO_P0_7_Pos)
+
+/* 0x2C8    0x4000_02c8
+    7:0     R/W     R_PMUX_GPIO_P1_0                                8'h3C
+    15:8    R/W     R_PMUX_GPIO_P1_1                                8'h3B
+    23:16   R/W     R_PMUX_GPIO_P1_6                                8'h00
+    31:24   R/W     R_PMUX_GPIO_P1_7                                8'h00
+ */
+typedef union _PCC_r_PMUX_GPIO_P1_0to7_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t R_PMUX_GPIO_P1_0: 8;
+        uint32_t R_PMUX_GPIO_P1_1: 8;
+        uint32_t R_PMUX_GPIO_P1_6: 8;
+        uint32_t R_PMUX_GPIO_P1_7: 8;
+    };
+} PCC_r_PMUX_GPIO_P1_0to7_TYPE;
+
+/*0x4000_02c8 PCC_r_PMUX_GPIO_P1_0to7*/
+#define PCC_r_PMUX_GPIO_P1_0to7_R_PMUX_GPIO_P1_0_Pos                                             0U
+#define PCC_r_PMUX_GPIO_P1_0to7_R_PMUX_GPIO_P1_0_Msk                                             (0xFFUL << PCC_r_PMUX_GPIO_P1_0to7_R_PMUX_GPIO_P1_0_Pos)
+
+#define PCC_r_PMUX_GPIO_P1_0to7_R_PMUX_GPIO_P1_1_Pos                                             8U
+#define PCC_r_PMUX_GPIO_P1_0to7_R_PMUX_GPIO_P1_1_Msk                                             (0xFFUL << PCC_r_PMUX_GPIO_P1_0to7_R_PMUX_GPIO_P1_1_Pos)
+
+#define PCC_r_PMUX_GPIO_P1_0to7_R_PMUX_GPIO_P1_6_Pos                                             16U
+#define PCC_r_PMUX_GPIO_P1_0to7_R_PMUX_GPIO_P1_6_Msk                                             (0xFFUL << PCC_r_PMUX_GPIO_P1_0to7_R_PMUX_GPIO_P1_6_Pos)
+
+#define PCC_r_PMUX_GPIO_P1_0to7_R_PMUX_GPIO_P1_7_Pos                                             24U
+#define PCC_r_PMUX_GPIO_P1_0to7_R_PMUX_GPIO_P1_7_Msk                                             (0xFFUL << PCC_r_PMUX_GPIO_P1_0to7_R_PMUX_GPIO_P1_7_Pos)
+
+/* 0x2CC    0x4000_02cc
+    7:0     R/W     R_PMUX_GPIO_P2_0                                8'h00
+    15:8    R/W     R_PMUX_GPIO_P2_1                                8'h00
+    23:16   R/W     R_PMUX_GPIO_P2_2                                8'h00
+    31:24   R/W     R_PMUX_GPIO_P2_3                                8'h00
+ */
+typedef union _PCC_r_PMUX_GPIO_P2_0to3_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t R_PMUX_GPIO_P2_0: 8;
+        uint32_t R_PMUX_GPIO_P2_1: 8;
+        uint32_t R_PMUX_GPIO_P2_2: 8;
+        uint32_t R_PMUX_GPIO_P2_3: 8;
+    };
+} PCC_r_PMUX_GPIO_P2_0to3_TYPE;
+
+/*0x4000_02cc PCC_r_PMUX_GPIO_P2_0to3*/
+#define PCC_r_PMUX_GPIO_P2_0to3_R_PMUX_GPIO_P2_0_Pos                                             0U
+#define PCC_r_PMUX_GPIO_P2_0to3_R_PMUX_GPIO_P2_0_Msk                                             (0xFFUL << PCC_r_PMUX_GPIO_P2_0to3_R_PMUX_GPIO_P2_0_Pos)
+
+#define PCC_r_PMUX_GPIO_P2_0to3_R_PMUX_GPIO_P2_1_Pos                                             8U
+#define PCC_r_PMUX_GPIO_P2_0to3_R_PMUX_GPIO_P2_1_Msk                                             (0xFFUL << PCC_r_PMUX_GPIO_P2_0to3_R_PMUX_GPIO_P2_1_Pos)
+
+#define PCC_r_PMUX_GPIO_P2_0to3_R_PMUX_GPIO_P2_2_Pos                                             16U
+#define PCC_r_PMUX_GPIO_P2_0to3_R_PMUX_GPIO_P2_2_Msk                                             (0xFFUL << PCC_r_PMUX_GPIO_P2_0to3_R_PMUX_GPIO_P2_2_Pos)
+
+#define PCC_r_PMUX_GPIO_P2_0to3_R_PMUX_GPIO_P2_3_Pos                                             24U
+#define PCC_r_PMUX_GPIO_P2_0to3_R_PMUX_GPIO_P2_3_Msk                                             (0xFFUL << PCC_r_PMUX_GPIO_P2_0to3_R_PMUX_GPIO_P2_3_Pos)
+
+/* 0x2D0    0x4000_02d0
+    7:0     R/W     R_PMUX_GPIO_P2_4                                8'h00
+    15:8    R/W     R_PMUX_GPIO_P2_5                                8'h00
+    23:16   R/W     R_PMUX_GPIO_P2_6                                8'h00
+    31:24   R/W     R_PMUX_GPIO_P2_7                                8'h00
+ */
+typedef union _PCC_r_PMUX_GPIO_P2_4to7_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t R_PMUX_GPIO_P2_4: 8;
+        uint32_t R_PMUX_GPIO_P2_5: 8;
+        uint32_t R_PMUX_GPIO_P2_6: 8;
+        uint32_t R_PMUX_GPIO_P2_7: 8;
+    };
+} PCC_r_PMUX_GPIO_P2_4to7_TYPE;
+
+/*0x4000_02d0 PCC_r_PMUX_GPIO_P2_4to7*/
+#define PCC_r_PMUX_GPIO_P2_4to7_R_PMUX_GPIO_P2_4_Pos                                             0U
+#define PCC_r_PMUX_GPIO_P2_4to7_R_PMUX_GPIO_P2_4_Msk                                             (0xFFUL << PCC_r_PMUX_GPIO_P2_4to7_R_PMUX_GPIO_P2_4_Pos)
+
+#define PCC_r_PMUX_GPIO_P2_4to7_R_PMUX_GPIO_P2_5_Pos                                             8U
+#define PCC_r_PMUX_GPIO_P2_4to7_R_PMUX_GPIO_P2_5_Msk                                             (0xFFUL << PCC_r_PMUX_GPIO_P2_4to7_R_PMUX_GPIO_P2_5_Pos)
+
+#define PCC_r_PMUX_GPIO_P2_4to7_R_PMUX_GPIO_P2_6_Pos                                             16U
+#define PCC_r_PMUX_GPIO_P2_4to7_R_PMUX_GPIO_P2_6_Msk                                             (0xFFUL << PCC_r_PMUX_GPIO_P2_4to7_R_PMUX_GPIO_P2_6_Pos)
+
+#define PCC_r_PMUX_GPIO_P2_4to7_R_PMUX_GPIO_P2_7_Pos                                             24U
+#define PCC_r_PMUX_GPIO_P2_4to7_R_PMUX_GPIO_P2_7_Msk                                             (0xFFUL << PCC_r_PMUX_GPIO_P2_4to7_R_PMUX_GPIO_P2_7_Pos)
+
+/* 0x2D4    0x4000_02d4
+    7:0     R/W     R_PMUX_GPIO_P3_0                                8'h00
+    15:8    R/W     R_PMUX_GPIO_P3_1                                8'h00
+    23:16   R/W     R_PMUX_GPIO_P3_2                                8'h00
+    31:24   R/W     R_PMUX_GPIO_P3_3                                8'h00
+ */
+typedef union _PCC_r_PMUX_GPIO_P3_0to3_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t R_PMUX_GPIO_P3_0: 8;
+        uint32_t R_PMUX_GPIO_P3_1: 8;
+        uint32_t R_PMUX_GPIO_P3_2: 8;
+        uint32_t R_PMUX_GPIO_P3_3: 8;
+    };
+} PCC_r_PMUX_GPIO_P3_0to3_TYPE;
+
+/*0x4000_02d4 PCC_r_PMUX_GPIO_P3_0to3*/
+#define PCC_r_PMUX_GPIO_P3_0to3_R_PMUX_GPIO_P3_0_Pos                                             0U
+#define PCC_r_PMUX_GPIO_P3_0to3_R_PMUX_GPIO_P3_0_Msk                                             (0xFFUL << PCC_r_PMUX_GPIO_P3_0to3_R_PMUX_GPIO_P3_0_Pos)
+
+#define PCC_r_PMUX_GPIO_P3_0to3_R_PMUX_GPIO_P3_1_Pos                                             8U
+#define PCC_r_PMUX_GPIO_P3_0to3_R_PMUX_GPIO_P3_1_Msk                                             (0xFFUL << PCC_r_PMUX_GPIO_P3_0to3_R_PMUX_GPIO_P3_1_Pos)
+
+#define PCC_r_PMUX_GPIO_P3_0to3_R_PMUX_GPIO_P3_2_Pos                                             16U
+#define PCC_r_PMUX_GPIO_P3_0to3_R_PMUX_GPIO_P3_2_Msk                                             (0xFFUL << PCC_r_PMUX_GPIO_P3_0to3_R_PMUX_GPIO_P3_2_Pos)
+
+#define PCC_r_PMUX_GPIO_P3_0to3_R_PMUX_GPIO_P3_3_Pos                                             24U
+#define PCC_r_PMUX_GPIO_P3_0to3_R_PMUX_GPIO_P3_3_Msk                                             (0xFFUL << PCC_r_PMUX_GPIO_P3_0to3_R_PMUX_GPIO_P3_3_Pos)
+
+/* 0x2D8    0x4000_02d8
+    7:0     R/W     R_PMUX_GPIO_P3_4                                8'h23
+    15:8    R/W     R_PMUX_GPIO_P3_5                                8'h24
+    23:16   R/W     R_PMUX_GPIO_P3_6                                8'h00
+    31:24   R/W     DUMMY                                           8'h00
+ */
+typedef union _PCC_r_PMUX_GPIO_P3_4to6_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t R_PMUX_GPIO_P3_4: 8;
+        uint32_t R_PMUX_GPIO_P3_5: 8;
+        uint32_t R_PMUX_GPIO_P3_6: 8;
+        uint32_t DUMMY: 8;
+    };
+} PCC_r_PMUX_GPIO_P3_4to6_TYPE;
+
+/*0x4000_02d8 PCC_r_PMUX_GPIO_P3_4to6*/
+#define PCC_r_PMUX_GPIO_P3_4to6_R_PMUX_GPIO_P3_4_Pos                                             0U
+#define PCC_r_PMUX_GPIO_P3_4to6_R_PMUX_GPIO_P3_4_Msk                                             (0xFFUL << PCC_r_PMUX_GPIO_P3_4to6_R_PMUX_GPIO_P3_4_Pos)
+
+#define PCC_r_PMUX_GPIO_P3_4to6_R_PMUX_GPIO_P3_5_Pos                                             8U
+#define PCC_r_PMUX_GPIO_P3_4to6_R_PMUX_GPIO_P3_5_Msk                                             (0xFFUL << PCC_r_PMUX_GPIO_P3_4to6_R_PMUX_GPIO_P3_5_Pos)
+
+#define PCC_r_PMUX_GPIO_P3_4to6_R_PMUX_GPIO_P3_6_Pos                                             16U
+#define PCC_r_PMUX_GPIO_P3_4to6_R_PMUX_GPIO_P3_6_Msk                                             (0xFFUL << PCC_r_PMUX_GPIO_P3_4to6_R_PMUX_GPIO_P3_6_Pos)
+
+#define PCC_r_PMUX_GPIO_P3_4to6_DUMMY_Pos                                                        24U
+#define PCC_r_PMUX_GPIO_P3_4to6_DUMMY_Msk                                                        (0xFFUL << PCC_r_PMUX_GPIO_P3_4to6_DUMMY_Pos)
+
+/* 0x2DC    0x4000_02dc
+    7:0     R/W     R_PMUX_GPIO_P4_0                                8'h00
+    15:8    R/W     R_PMUX_GPIO_P4_1                                8'h00
+    23:16   R/W     R_PMUX_GPIO_P4_2                                8'h00
+    31:24   R/W     R_PMUX_GPIO_P4_3                                8'h00
+ */
+typedef union _PCC_r_PMUX_GPIO_P4_0to3_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t R_PMUX_GPIO_P4_0: 8;
+        uint32_t R_PMUX_GPIO_P4_1: 8;
+        uint32_t R_PMUX_GPIO_P4_2: 8;
+        uint32_t R_PMUX_GPIO_P4_3: 8;
+    };
+} PCC_r_PMUX_GPIO_P4_0to3_TYPE;
+
+/*0x4000_02dc PCC_r_PMUX_GPIO_P4_0to3*/
+#define PCC_r_PMUX_GPIO_P4_0to3_R_PMUX_GPIO_P4_0_Pos                                             0U
+#define PCC_r_PMUX_GPIO_P4_0to3_R_PMUX_GPIO_P4_0_Msk                                             (0xFFUL << PCC_r_PMUX_GPIO_P4_0to3_R_PMUX_GPIO_P4_0_Pos)
+
+#define PCC_r_PMUX_GPIO_P4_0to3_R_PMUX_GPIO_P4_1_Pos                                             8U
+#define PCC_r_PMUX_GPIO_P4_0to3_R_PMUX_GPIO_P4_1_Msk                                             (0xFFUL << PCC_r_PMUX_GPIO_P4_0to3_R_PMUX_GPIO_P4_1_Pos)
+
+#define PCC_r_PMUX_GPIO_P4_0to3_R_PMUX_GPIO_P4_2_Pos                                             16U
+#define PCC_r_PMUX_GPIO_P4_0to3_R_PMUX_GPIO_P4_2_Msk                                             (0xFFUL << PCC_r_PMUX_GPIO_P4_0to3_R_PMUX_GPIO_P4_2_Pos)
+
+#define PCC_r_PMUX_GPIO_P4_0to3_R_PMUX_GPIO_P4_3_Pos                                             24U
+#define PCC_r_PMUX_GPIO_P4_0to3_R_PMUX_GPIO_P4_3_Msk                                             (0xFFUL << PCC_r_PMUX_GPIO_P4_0to3_R_PMUX_GPIO_P4_3_Pos)
+
+/* 0x2E0    0x4000_02e0
+    7:0     R/W     R_PMUX_GPIO_MICBIAS_0                           8'h00
+    15:8    R/W     R_PMUX_GPIO_P5_1                                8'h00
+    23:16   R/W     R_PMUX_GPIO_P5_2                                8'h00
+    31:24   R/W     DUMMY37                                         8'h00
+ */
+typedef union _PCC_r_PMUX_GPIO_H_0to2_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t R_PMUX_GPIO_MICBIAS_0: 8;
+        uint32_t R_PMUX_GPIO_P5_1: 8;
+        uint32_t R_PMUX_GPIO_P5_2: 8;
+        uint32_t DUMMY37: 8;
+    };
+} PCC_r_PMUX_GPIO_H_0to2_TYPE;
+
+/*0x4000_02e0 PCC_r_PMUX_GPIO_H_0to2*/
+#define PCC_r_PMUX_GPIO_H_0to2_R_PMUX_GPIO_MICBIAS_0_Pos                                         0U
+#define PCC_r_PMUX_GPIO_H_0to2_R_PMUX_GPIO_MICBIAS_0_Msk                                         (0xFFUL << PCC_r_PMUX_GPIO_H_0to2_R_PMUX_GPIO_MICBIAS_0_Pos)
+
+#define PCC_r_PMUX_GPIO_H_0to2_R_PMUX_GPIO_P5_1_Pos                                              8U
+#define PCC_r_PMUX_GPIO_H_0to2_R_PMUX_GPIO_P5_1_Msk                                              (0xFFUL << PCC_r_PMUX_GPIO_H_0to2_R_PMUX_GPIO_P5_1_Pos)
+
+#define PCC_r_PMUX_GPIO_H_0to2_R_PMUX_GPIO_P5_2_Pos                                              16U
+#define PCC_r_PMUX_GPIO_H_0to2_R_PMUX_GPIO_P5_2_Msk                                              (0xFFUL << PCC_r_PMUX_GPIO_H_0to2_R_PMUX_GPIO_P5_2_Pos)
+
+#define PCC_r_PMUX_GPIO_H_0to2_DUMMY37_Pos                                                       24U
+#define PCC_r_PMUX_GPIO_H_0to2_DUMMY37_Msk                                                       (0xFFUL << PCC_r_PMUX_GPIO_H_0to2_DUMMY37_Pos)
+
+/* 0x2E4    0x4000_02e4
+    7:0     R/W     R_PMUX_GPIO_P6_0                                8'h00
+    15:8    R/W     R_PMUX_GPIO_P6_1                                8'h00
+    23:16   R/W     R_PMUX_GPIO_P6_2                                8'h00
+    31:24   R/W     R_PMUX_GPIO_P6_3                                8'h00
+ */
+typedef union _PCC_REG_PMUX_GPIO_6_0to3_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t R_PMUX_GPIO_P6_0: 8;
+        uint32_t R_PMUX_GPIO_P6_1: 8;
+        uint32_t R_PMUX_GPIO_P6_2: 8;
+        uint32_t R_PMUX_GPIO_P6_3: 8;
+    };
+} PCC_REG_PMUX_GPIO_6_0to3_TYPE;
+
+/*0x4000_02e4 PCC_REG_PMUX_GPIO_6_0to3*/
+#define PCC_REG_PMUX_GPIO_6_0to3_R_PMUX_GPIO_P6_0_Pos                                            0U
+#define PCC_REG_PMUX_GPIO_6_0to3_R_PMUX_GPIO_P6_0_Msk                                            (0xFFUL << PCC_REG_PMUX_GPIO_6_0to3_R_PMUX_GPIO_P6_0_Pos)
+
+#define PCC_REG_PMUX_GPIO_6_0to3_R_PMUX_GPIO_P6_1_Pos                                            8U
+#define PCC_REG_PMUX_GPIO_6_0to3_R_PMUX_GPIO_P6_1_Msk                                            (0xFFUL << PCC_REG_PMUX_GPIO_6_0to3_R_PMUX_GPIO_P6_1_Pos)
+
+#define PCC_REG_PMUX_GPIO_6_0to3_R_PMUX_GPIO_P6_2_Pos                                            16U
+#define PCC_REG_PMUX_GPIO_6_0to3_R_PMUX_GPIO_P6_2_Msk                                            (0xFFUL << PCC_REG_PMUX_GPIO_6_0to3_R_PMUX_GPIO_P6_2_Pos)
+
+#define PCC_REG_PMUX_GPIO_6_0to3_R_PMUX_GPIO_P6_3_Pos                                            24U
+#define PCC_REG_PMUX_GPIO_6_0to3_R_PMUX_GPIO_P6_3_Msk                                            (0xFFUL << PCC_REG_PMUX_GPIO_6_0to3_R_PMUX_GPIO_P6_3_Pos)
+
+/* 0x2E8    0x4000_02e8
+    7:0     R/W     R_PMUX_GPIO_P6_4                                8'h00
+    15:8    R/W     R_PMUX_GPIO_P6_5                                8'h00
+    23:16   R/W     R_PMUX_GPIO_P6_6                                8'h00
+    31:24   R/W     R_PMUX_GPIO_P6_7                                8'h00
+ */
+typedef union _PCC_REG_PMUX_GPIO_6_4to7_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t R_PMUX_GPIO_P6_4: 8;
+        uint32_t R_PMUX_GPIO_P6_5: 8;
+        uint32_t R_PMUX_GPIO_P6_6: 8;
+        uint32_t R_PMUX_GPIO_P6_7: 8;
+    };
+} PCC_REG_PMUX_GPIO_6_4to7_TYPE;
+
+/*0x4000_02e8 PCC_REG_PMUX_GPIO_6_4to7*/
+#define PCC_REG_PMUX_GPIO_6_4to7_R_PMUX_GPIO_P6_4_Pos                                            0U
+#define PCC_REG_PMUX_GPIO_6_4to7_R_PMUX_GPIO_P6_4_Msk                                            (0xFFUL << PCC_REG_PMUX_GPIO_6_4to7_R_PMUX_GPIO_P6_4_Pos)
+
+#define PCC_REG_PMUX_GPIO_6_4to7_R_PMUX_GPIO_P6_5_Pos                                            8U
+#define PCC_REG_PMUX_GPIO_6_4to7_R_PMUX_GPIO_P6_5_Msk                                            (0xFFUL << PCC_REG_PMUX_GPIO_6_4to7_R_PMUX_GPIO_P6_5_Pos)
+
+#define PCC_REG_PMUX_GPIO_6_4to7_R_PMUX_GPIO_P6_6_Pos                                            16U
+#define PCC_REG_PMUX_GPIO_6_4to7_R_PMUX_GPIO_P6_6_Msk                                            (0xFFUL << PCC_REG_PMUX_GPIO_6_4to7_R_PMUX_GPIO_P6_6_Pos)
+
+#define PCC_REG_PMUX_GPIO_6_4to7_R_PMUX_GPIO_P6_7_Pos                                            24U
+#define PCC_REG_PMUX_GPIO_6_4to7_R_PMUX_GPIO_P6_7_Msk                                            (0xFFUL << PCC_REG_PMUX_GPIO_6_4to7_R_PMUX_GPIO_P6_7_Pos)
+
+/* 0x2EC    0x4000_02ec
+    7:0     R/W     R_PMUX_GPIO_P7_0                                8'h00
+    15:8    R/W     R_PMUX_GPIO_P7_1                                8'h00
+    23:16   R/W     R_PMUX_GPIO_SPIC_CSN                            8'h00
+    31:24   R/W     R_PMUX_GPIO_SPIC_SCK                            8'h00
+ */
+typedef union _PCC_REG_PMUX_GPIO_7_0to1_SPIC_1_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t R_PMUX_GPIO_P7_0: 8;
+        uint32_t R_PMUX_GPIO_P7_1: 8;
+        uint32_t R_PMUX_GPIO_SPIC_CSN: 8;
+        uint32_t R_PMUX_GPIO_SPIC_SCK: 8;
+    };
+} PCC_REG_PMUX_GPIO_7_0to1_SPIC_1_TYPE;
+
+/*0x4000_02ec PCC_REG_PMUX_GPIO_7_0to1_SPIC_1*/
+#define PCC_REG_PMUX_GPIO_7_0to1_SPIC_1_R_PMUX_GPIO_P7_0_Pos                                     0U
+#define PCC_REG_PMUX_GPIO_7_0to1_SPIC_1_R_PMUX_GPIO_P7_0_Msk                                     (0xFFUL << PCC_REG_PMUX_GPIO_7_0to1_SPIC_1_R_PMUX_GPIO_P7_0_Pos)
+
+#define PCC_REG_PMUX_GPIO_7_0to1_SPIC_1_R_PMUX_GPIO_P7_1_Pos                                     8U
+#define PCC_REG_PMUX_GPIO_7_0to1_SPIC_1_R_PMUX_GPIO_P7_1_Msk                                     (0xFFUL << PCC_REG_PMUX_GPIO_7_0to1_SPIC_1_R_PMUX_GPIO_P7_1_Pos)
+
+#define PCC_REG_PMUX_GPIO_7_0to1_SPIC_1_R_PMUX_GPIO_SPIC_CSN_Pos                                 16U
+#define PCC_REG_PMUX_GPIO_7_0to1_SPIC_1_R_PMUX_GPIO_SPIC_CSN_Msk                                 (0xFFUL << PCC_REG_PMUX_GPIO_7_0to1_SPIC_1_R_PMUX_GPIO_SPIC_CSN_Pos)
+
+#define PCC_REG_PMUX_GPIO_7_0to1_SPIC_1_R_PMUX_GPIO_SPIC_SCK_Pos                                 24U
+#define PCC_REG_PMUX_GPIO_7_0to1_SPIC_1_R_PMUX_GPIO_SPIC_SCK_Msk                                 (0xFFUL << PCC_REG_PMUX_GPIO_7_0to1_SPIC_1_R_PMUX_GPIO_SPIC_SCK_Pos)
+
+/* 0x2F0    0x4000_02f0
+    7:0     R/W     R_PMUX_GPIO_SPIC_SI                             8'h00
+    15:8    R/W     R_PMUX_GPIO_SPIC_SO                             8'h00
+    23:16   R/W     R_PMUX_GPIO_P1_4                                8'h00
+    31:24   R/W     R_PMUX_GPIO_P1_3                                8'h00
+ */
+typedef union _PCC_REG_PMUX_GPIO_SPIC_2_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t R_PMUX_GPIO_SPIC_SI: 8;
+        uint32_t R_PMUX_GPIO_SPIC_SO: 8;
+        uint32_t R_PMUX_GPIO_P1_4: 8;
+        uint32_t R_PMUX_GPIO_P1_3: 8;
+    };
+} PCC_REG_PMUX_GPIO_SPIC_2_TYPE;
+
+/*0x4000_02f0 PCC_REG_PMUX_GPIO_SPIC_2*/
+#define PCC_REG_PMUX_GPIO_SPIC_2_R_PMUX_GPIO_SPIC_SI_Pos                                         0U
+#define PCC_REG_PMUX_GPIO_SPIC_2_R_PMUX_GPIO_SPIC_SI_Msk                                         (0xFFUL << PCC_REG_PMUX_GPIO_SPIC_2_R_PMUX_GPIO_SPIC_SI_Pos)
+
+#define PCC_REG_PMUX_GPIO_SPIC_2_R_PMUX_GPIO_SPIC_SO_Pos                                         8U
+#define PCC_REG_PMUX_GPIO_SPIC_2_R_PMUX_GPIO_SPIC_SO_Msk                                         (0xFFUL << PCC_REG_PMUX_GPIO_SPIC_2_R_PMUX_GPIO_SPIC_SO_Pos)
+
+#define PCC_REG_PMUX_GPIO_SPIC_2_R_PMUX_GPIO_P1_4_Pos                                            16U
+#define PCC_REG_PMUX_GPIO_SPIC_2_R_PMUX_GPIO_P1_4_Msk                                            (0xFFUL << PCC_REG_PMUX_GPIO_SPIC_2_R_PMUX_GPIO_P1_4_Pos)
+
+#define PCC_REG_PMUX_GPIO_SPIC_2_R_PMUX_GPIO_P1_3_Pos                                            24U
+#define PCC_REG_PMUX_GPIO_SPIC_2_R_PMUX_GPIO_P1_3_Msk                                            (0xFFUL << PCC_REG_PMUX_GPIO_SPIC_2_R_PMUX_GPIO_P1_3_Pos)
+
+/* 0x2F4    0x4000_02f4
+    3:0     R/W     R_PMUX_TEST_MODE                                4'h1
+    6:4     R/W     R_DW_SPIM_EN                                    3'h0
+    7       R/W     R_PMUX_TEST_MODE_EN                             0
+    8       R/W     R_SAR_TM_DAT_SEL                                0
+    9       R/W     DUMMY62                                         0
+    13:10   R/W     R_PMUX_1_WIRE_UART_EN                           4'h0
+    14      R/W     R_SAR_TM_CLK_SEL                                1'b0
+    15      R/W     R_SAR_TM_CH_SEL                                 1'b0
+    17:16   R/W     R_OSC80M_TEST_MODE_CLK_DIV                      2'h0
+    19:18   R/W     R_PLL_TEST_MODE_CLK_DIV                         2'h0
+    20      R/W     R_PMUX_DBG_SPIC0                                0
+    21      R/W     DUMMY60                                         0
+    22      R/W     DUMMY59                                         0
+    23      R/W     R_PMUX_DIG_SMUX_EN                              0
+    24      R/W     R_PON_PMUX_SPIM0_EN                             0
+    25      R/W     R_PMUX_SPIM_EN_OPT                              0
+    26      R/W     R_PMUX_FLASH_EXTC_EN                            0
+    27      R/W     R_PMUX_FLASH_EN                                 0
+    29:28   R/W     DUMMY58                                         2'h0
+    30      R/W     DUMMY57                                         0
+    31      R/W     DUMMY56                                         0
+ */
+typedef union _PCC_r_PMUX_TEST_MODE_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t R_PMUX_TEST_MODE: 4;
+        uint32_t R_DW_SPIM_EN: 3;
+        uint32_t R_PMUX_TEST_MODE_EN: 1;
+        uint32_t R_SAR_TM_DAT_SEL: 1;
+        uint32_t DUMMY62: 1;
+        uint32_t R_PMUX_1_WIRE_UART_EN: 4;
+        uint32_t R_SAR_TM_CLK_SEL: 1;
+        uint32_t R_SAR_TM_CH_SEL: 1;
+        uint32_t R_OSC80M_TEST_MODE_CLK_DIV: 2;
+        uint32_t R_PLL_TEST_MODE_CLK_DIV: 2;
+        uint32_t R_PMUX_DBG_SPIC0: 1;
+        uint32_t DUMMY60: 1;
+        uint32_t DUMMY59: 1;
+        uint32_t R_PMUX_DIG_SMUX_EN: 1;
+        uint32_t R_PON_PMUX_SPIM0_EN: 1;
+        uint32_t R_PMUX_SPIM_EN_OPT: 1;
+        uint32_t R_PMUX_FLASH_EXTC_EN: 1;
+        uint32_t R_PMUX_FLASH_EN: 1;
+        uint32_t DUMMY58: 2;
+        uint32_t DUMMY57: 1;
+        uint32_t DUMMY56: 1;
+    };
+} PCC_r_PMUX_TEST_MODE_TYPE;
+
+/*0x4000_02f4 PCC_r_PMUX_TEST_MODE*/
+#define PCC_r_PMUX_TEST_MODE_R_PMUX_TEST_MODE_Pos                                                0U
+#define PCC_r_PMUX_TEST_MODE_R_PMUX_TEST_MODE_Msk                                                (0xFUL << PCC_r_PMUX_TEST_MODE_R_PMUX_TEST_MODE_Pos)
+
+#define PCC_r_PMUX_TEST_MODE_R_DW_SPIM_EN_Pos                                                    4U
+#define PCC_r_PMUX_TEST_MODE_R_DW_SPIM_EN_Msk                                                    (0x7UL << PCC_r_PMUX_TEST_MODE_R_DW_SPIM_EN_Pos)
+
+#define PCC_r_PMUX_TEST_MODE_R_PMUX_TEST_MODE_EN_Pos                                             7U
+#define PCC_r_PMUX_TEST_MODE_R_PMUX_TEST_MODE_EN_Msk                                             (0x1UL << PCC_r_PMUX_TEST_MODE_R_PMUX_TEST_MODE_EN_Pos)
+
+#define PCC_r_PMUX_TEST_MODE_R_SAR_TM_DAT_SEL_Pos                                                8U
+#define PCC_r_PMUX_TEST_MODE_R_SAR_TM_DAT_SEL_Msk                                                (0x1UL << PCC_r_PMUX_TEST_MODE_R_SAR_TM_DAT_SEL_Pos)
+
+#define PCC_r_PMUX_TEST_MODE_DUMMY62_Pos                                                         9U
+#define PCC_r_PMUX_TEST_MODE_DUMMY62_Msk                                                         (0x1UL << PCC_r_PMUX_TEST_MODE_DUMMY62_Pos)
+
+#define PCC_r_PMUX_TEST_MODE_R_PMUX_1_WIRE_UART_EN_Pos                                           10U
+#define PCC_r_PMUX_TEST_MODE_R_PMUX_1_WIRE_UART_EN_Msk                                           (0xFUL << PCC_r_PMUX_TEST_MODE_R_PMUX_1_WIRE_UART_EN_Pos)
+
+#define PCC_r_PMUX_TEST_MODE_R_SAR_TM_CLK_SEL_Pos                                                14U
+#define PCC_r_PMUX_TEST_MODE_R_SAR_TM_CLK_SEL_Msk                                                (0x1UL << PCC_r_PMUX_TEST_MODE_R_SAR_TM_CLK_SEL_Pos)
+
+#define PCC_r_PMUX_TEST_MODE_R_SAR_TM_CH_SEL_Pos                                                 15U
+#define PCC_r_PMUX_TEST_MODE_R_SAR_TM_CH_SEL_Msk                                                 (0x1UL << PCC_r_PMUX_TEST_MODE_R_SAR_TM_CH_SEL_Pos)
+
+#define PCC_r_PMUX_TEST_MODE_R_OSC80M_TEST_MODE_CLK_DIV_Pos                                      16U
+#define PCC_r_PMUX_TEST_MODE_R_OSC80M_TEST_MODE_CLK_DIV_Msk                                      (0x3UL << PCC_r_PMUX_TEST_MODE_R_OSC80M_TEST_MODE_CLK_DIV_Pos)
+
+#define PCC_r_PMUX_TEST_MODE_R_PLL_TEST_MODE_CLK_DIV_Pos                                         18U
+#define PCC_r_PMUX_TEST_MODE_R_PLL_TEST_MODE_CLK_DIV_Msk                                         (0x3UL << PCC_r_PMUX_TEST_MODE_R_PLL_TEST_MODE_CLK_DIV_Pos)
+
+#define PCC_r_PMUX_TEST_MODE_R_PMUX_DBG_SPIC0_Pos                                                20U
+#define PCC_r_PMUX_TEST_MODE_R_PMUX_DBG_SPIC0_Msk                                                (0x1UL << PCC_r_PMUX_TEST_MODE_R_PMUX_DBG_SPIC0_Pos)
+
+#define PCC_r_PMUX_TEST_MODE_DUMMY60_Pos                                                         21U
+#define PCC_r_PMUX_TEST_MODE_DUMMY60_Msk                                                         (0x1UL << PCC_r_PMUX_TEST_MODE_DUMMY60_Pos)
+
+#define PCC_r_PMUX_TEST_MODE_DUMMY59_Pos                                                         22U
+#define PCC_r_PMUX_TEST_MODE_DUMMY59_Msk                                                         (0x1UL << PCC_r_PMUX_TEST_MODE_DUMMY59_Pos)
+
+#define PCC_r_PMUX_TEST_MODE_R_PMUX_DIG_SMUX_EN_Pos                                              23U
+#define PCC_r_PMUX_TEST_MODE_R_PMUX_DIG_SMUX_EN_Msk                                              (0x1UL << PCC_r_PMUX_TEST_MODE_R_PMUX_DIG_SMUX_EN_Pos)
+
+#define PCC_r_PMUX_TEST_MODE_R_PON_PMUX_SPIM0_EN_Pos                                             24U
+#define PCC_r_PMUX_TEST_MODE_R_PON_PMUX_SPIM0_EN_Msk                                             (0x1UL << PCC_r_PMUX_TEST_MODE_R_PON_PMUX_SPIM0_EN_Pos)
+
+#define PCC_r_PMUX_TEST_MODE_R_PMUX_SPIM_EN_OPT_Pos                                              25U
+#define PCC_r_PMUX_TEST_MODE_R_PMUX_SPIM_EN_OPT_Msk                                              (0x1UL << PCC_r_PMUX_TEST_MODE_R_PMUX_SPIM_EN_OPT_Pos)
+
+#define PCC_r_PMUX_TEST_MODE_R_PMUX_FLASH_EXTC_EN_Pos                                            26U
+#define PCC_r_PMUX_TEST_MODE_R_PMUX_FLASH_EXTC_EN_Msk                                            (0x1UL << PCC_r_PMUX_TEST_MODE_R_PMUX_FLASH_EXTC_EN_Pos)
+
+#define PCC_r_PMUX_TEST_MODE_R_PMUX_FLASH_EN_Pos                                                 27U
+#define PCC_r_PMUX_TEST_MODE_R_PMUX_FLASH_EN_Msk                                                 (0x1UL << PCC_r_PMUX_TEST_MODE_R_PMUX_FLASH_EN_Pos)
+
+#define PCC_r_PMUX_TEST_MODE_DUMMY58_Pos                                                         28U
+#define PCC_r_PMUX_TEST_MODE_DUMMY58_Msk                                                         (0x3UL << PCC_r_PMUX_TEST_MODE_DUMMY58_Pos)
+
+#define PCC_r_PMUX_TEST_MODE_DUMMY57_Pos                                                         30U
+#define PCC_r_PMUX_TEST_MODE_DUMMY57_Msk                                                         (0x1UL << PCC_r_PMUX_TEST_MODE_DUMMY57_Pos)
+
+#define PCC_r_PMUX_TEST_MODE_DUMMY56_Pos                                                         31U
+#define PCC_r_PMUX_TEST_MODE_DUMMY56_Msk                                                         (0x1UL << PCC_r_PMUX_TEST_MODE_DUMMY56_Pos)
+
+/* 0x2F8    0x4000_02f8
+    0       R/W     DET_ENABLE                                      1'b0
+    1       R/W     VBUS_DET                                        1'b0
+    2       R/W     SKIP_SEC_DET                                    1'b0
+    3       R/W     DUMMY68                                         1'b0
+    7:4     R/W     DUMMY67                                         4'h0
+    8       R       SDP_0P5A                                        1'h0
+    9       R       DCP_CDP_1P5A                                    1'h0
+    10      R       CDP_DET                                         1'h0
+    11      R       DCP_DET                                         1'h0
+    12      R       OTHERS_0P5A                                     1'h0
+    13      R       RSVD_4                                          1'h0
+    14      R       RSVD_3                                          1'h0
+    15      R       RSVD_2                                          1'h0
+    16      R       DET_IS_DONE                                     1'h0
+    17      R       RSVD_1                                          1'h0
+    18      R       RSVD                                            1'h0
+    28:19   R/W     DUMMY66                                         10'h0
+    29      R/W     DCP_OPTION                                      1'h1
+    30      R/W     DUMMY65                                         1'h1
+    31      R/W     BYPASS_DCD_DBNC                                 1'h0
+ */
+typedef union _PCC_REG_BC12_CTRL1_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t DET_ENABLE: 1;
+        uint32_t VBUS_DET: 1;
+        uint32_t SKIP_SEC_DET: 1;
+        uint32_t DUMMY68: 1;
+        uint32_t DUMMY67: 4;
+        uint32_t SDP_0P5A: 1;
+        uint32_t DCP_CDP_1P5A: 1;
+        uint32_t CDP_DET: 1;
+        uint32_t DCP_DET: 1;
+        uint32_t OTHERS_0P5A: 1;
+        uint32_t RSVD_4: 1;
+        uint32_t RSVD_3: 1;
+        uint32_t RSVD_2: 1;
+        uint32_t DET_IS_DONE: 1;
+        uint32_t RSVD_1: 1;
+        uint32_t RSVD: 1;
+        uint32_t DUMMY66: 10;
+        uint32_t DCP_OPTION: 1;
+        uint32_t DUMMY65: 1;
+        uint32_t BYPASS_DCD_DBNC: 1;
+    };
+} PCC_REG_BC12_CTRL1_TYPE;
+
+/*0x4000_02f8 PCC_REG_BC12_CTRL1*/
+#define PCC_REG_BC12_CTRL1_DET_ENABLE_Pos                                                        0U
+#define PCC_REG_BC12_CTRL1_DET_ENABLE_Msk                                                        (0x1UL << PCC_REG_BC12_CTRL1_DET_ENABLE_Pos)
+
+#define PCC_REG_BC12_CTRL1_VBUS_DET_Pos                                                          1U
+#define PCC_REG_BC12_CTRL1_VBUS_DET_Msk                                                          (0x1UL << PCC_REG_BC12_CTRL1_VBUS_DET_Pos)
+
+#define PCC_REG_BC12_CTRL1_SKIP_SEC_DET_Pos                                                      2U
+#define PCC_REG_BC12_CTRL1_SKIP_SEC_DET_Msk                                                      (0x1UL << PCC_REG_BC12_CTRL1_SKIP_SEC_DET_Pos)
+
+#define PCC_REG_BC12_CTRL1_DUMMY68_Pos                                                           3U
+#define PCC_REG_BC12_CTRL1_DUMMY68_Msk                                                           (0x1UL << PCC_REG_BC12_CTRL1_DUMMY68_Pos)
+
+#define PCC_REG_BC12_CTRL1_DUMMY67_Pos                                                           4U
+#define PCC_REG_BC12_CTRL1_DUMMY67_Msk                                                           (0xFUL << PCC_REG_BC12_CTRL1_DUMMY67_Pos)
+
+#define PCC_REG_BC12_CTRL1_SDP_0P5A_Pos                                                          8U
+#define PCC_REG_BC12_CTRL1_SDP_0P5A_Msk                                                          (0x1UL << PCC_REG_BC12_CTRL1_SDP_0P5A_Pos)
+
+#define PCC_REG_BC12_CTRL1_DCP_CDP_1P5A_Pos                                                      9U
+#define PCC_REG_BC12_CTRL1_DCP_CDP_1P5A_Msk                                                      (0x1UL << PCC_REG_BC12_CTRL1_DCP_CDP_1P5A_Pos)
+
+#define PCC_REG_BC12_CTRL1_CDP_DET_Pos                                                           10U
+#define PCC_REG_BC12_CTRL1_CDP_DET_Msk                                                           (0x1UL << PCC_REG_BC12_CTRL1_CDP_DET_Pos)
+
+#define PCC_REG_BC12_CTRL1_DCP_DET_Pos                                                           11U
+#define PCC_REG_BC12_CTRL1_DCP_DET_Msk                                                           (0x1UL << PCC_REG_BC12_CTRL1_DCP_DET_Pos)
+
+#define PCC_REG_BC12_CTRL1_OTHERS_0P5A_Pos                                                       12U
+#define PCC_REG_BC12_CTRL1_OTHERS_0P5A_Msk                                                       (0x1UL << PCC_REG_BC12_CTRL1_OTHERS_0P5A_Pos)
+
+#define PCC_REG_BC12_CTRL1_RSVD_4_Pos                                                            13U
+#define PCC_REG_BC12_CTRL1_RSVD_4_Msk                                                            (0x1UL << PCC_REG_BC12_CTRL1_RSVD_4_Pos)
+
+#define PCC_REG_BC12_CTRL1_RSVD_3_Pos                                                            14U
+#define PCC_REG_BC12_CTRL1_RSVD_3_Msk                                                            (0x1UL << PCC_REG_BC12_CTRL1_RSVD_3_Pos)
+
+#define PCC_REG_BC12_CTRL1_RSVD_2_Pos                                                            15U
+#define PCC_REG_BC12_CTRL1_RSVD_2_Msk                                                            (0x1UL << PCC_REG_BC12_CTRL1_RSVD_2_Pos)
+
+#define PCC_REG_BC12_CTRL1_DET_IS_DONE_Pos                                                       16U
+#define PCC_REG_BC12_CTRL1_DET_IS_DONE_Msk                                                       (0x1UL << PCC_REG_BC12_CTRL1_DET_IS_DONE_Pos)
+
+#define PCC_REG_BC12_CTRL1_RSVD_1_Pos                                                            17U
+#define PCC_REG_BC12_CTRL1_RSVD_1_Msk                                                            (0x1UL << PCC_REG_BC12_CTRL1_RSVD_1_Pos)
+
+#define PCC_REG_BC12_CTRL1_RSVD_Pos                                                              18U
+#define PCC_REG_BC12_CTRL1_RSVD_Msk                                                              (0x1UL << PCC_REG_BC12_CTRL1_RSVD_Pos)
+
+#define PCC_REG_BC12_CTRL1_DUMMY66_Pos                                                           19U
+#define PCC_REG_BC12_CTRL1_DUMMY66_Msk                                                           (0x3FFUL << PCC_REG_BC12_CTRL1_DUMMY66_Pos)
+
+#define PCC_REG_BC12_CTRL1_DCP_OPTION_Pos                                                        29U
+#define PCC_REG_BC12_CTRL1_DCP_OPTION_Msk                                                        (0x1UL << PCC_REG_BC12_CTRL1_DCP_OPTION_Pos)
+
+#define PCC_REG_BC12_CTRL1_DUMMY65_Pos                                                           30U
+#define PCC_REG_BC12_CTRL1_DUMMY65_Msk                                                           (0x1UL << PCC_REG_BC12_CTRL1_DUMMY65_Pos)
+
+#define PCC_REG_BC12_CTRL1_BYPASS_DCD_DBNC_Pos                                                   31U
+#define PCC_REG_BC12_CTRL1_BYPASS_DCD_DBNC_Msk                                                   (0x1UL << PCC_REG_BC12_CTRL1_BYPASS_DCD_DBNC_Pos)
+
+/* 0x2FC    0x4000_02fc
+    7:0     R/W     FW_WRITE_BUS                                    8'h0
+    8       R/W     FW_CTRL_MODE                                    1'h0
+    15:9    R/W     DUMMY70                                         7'h0
+    19:16   R       VDP_COMP_L                                      4'h0
+    20      R       VDP_LT_VLOW_L                                   1'h0
+    24:21   R       VDM_COMP_L                                      4'h0
+    25      R       VDM_LT_VLOW_L                                   1'h0
+    31:26   R/W     DUMMY69                                         6'h0
+ */
+typedef union _PCC_REG_BC12_CTRL2_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t FW_WRITE_BUS: 8;
+        uint32_t FW_CTRL_MODE: 1;
+        uint32_t DUMMY70: 7;
+        uint32_t VDP_COMP_L: 4;
+        uint32_t VDP_LT_VLOW_L: 1;
+        uint32_t VDM_COMP_L: 4;
+        uint32_t VDM_LT_VLOW_L: 1;
+        uint32_t DUMMY69: 6;
+    };
+} PCC_REG_BC12_CTRL2_TYPE;
+
+/*0x4000_02fc PCC_REG_BC12_CTRL2*/
+#define PCC_REG_BC12_CTRL2_FW_WRITE_BUS_Pos                                                      0U
+#define PCC_REG_BC12_CTRL2_FW_WRITE_BUS_Msk                                                      (0xFFUL << PCC_REG_BC12_CTRL2_FW_WRITE_BUS_Pos)
+
+#define PCC_REG_BC12_CTRL2_FW_CTRL_MODE_Pos                                                      8U
+#define PCC_REG_BC12_CTRL2_FW_CTRL_MODE_Msk                                                      (0x1UL << PCC_REG_BC12_CTRL2_FW_CTRL_MODE_Pos)
+
+#define PCC_REG_BC12_CTRL2_DUMMY70_Pos                                                           9U
+#define PCC_REG_BC12_CTRL2_DUMMY70_Msk                                                           (0x7FUL << PCC_REG_BC12_CTRL2_DUMMY70_Pos)
+
+#define PCC_REG_BC12_CTRL2_VDP_COMP_L_Pos                                                        16U
+#define PCC_REG_BC12_CTRL2_VDP_COMP_L_Msk                                                        (0xFUL << PCC_REG_BC12_CTRL2_VDP_COMP_L_Pos)
+
+#define PCC_REG_BC12_CTRL2_VDP_LT_VLOW_L_Pos                                                     20U
+#define PCC_REG_BC12_CTRL2_VDP_LT_VLOW_L_Msk                                                     (0x1UL << PCC_REG_BC12_CTRL2_VDP_LT_VLOW_L_Pos)
+
+#define PCC_REG_BC12_CTRL2_VDM_COMP_L_Pos                                                        21U
+#define PCC_REG_BC12_CTRL2_VDM_COMP_L_Msk                                                        (0xFUL << PCC_REG_BC12_CTRL2_VDM_COMP_L_Pos)
+
+#define PCC_REG_BC12_CTRL2_VDM_LT_VLOW_L_Pos                                                     25U
+#define PCC_REG_BC12_CTRL2_VDM_LT_VLOW_L_Msk                                                     (0x1UL << PCC_REG_BC12_CTRL2_VDM_LT_VLOW_L_Pos)
+
+#define PCC_REG_BC12_CTRL2_DUMMY69_Pos                                                           26U
+#define PCC_REG_BC12_CTRL2_DUMMY69_Msk                                                           (0x3FUL << PCC_REG_BC12_CTRL2_DUMMY69_Pos)
+
+/* 0x300    0x4000_0300
+    15:0    R/W     DCD_A_MIN_TIME                                  16'h200
+    31:16   R/W     DCD_B_MIN_TIME                                  16'h3E80
+ */
+typedef union _PCC_REG_BC12_CTRL3_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t DCD_A_MIN_TIME: 16;
+        uint32_t DCD_B_MIN_TIME: 16;
+    };
+} PCC_REG_BC12_CTRL3_TYPE;
+
+/*0x4000_0300 PCC_REG_BC12_CTRL3*/
+#define PCC_REG_BC12_CTRL3_DCD_A_MIN_TIME_Pos                                                    0U
+#define PCC_REG_BC12_CTRL3_DCD_A_MIN_TIME_Msk                                                    (0xFFFFUL << PCC_REG_BC12_CTRL3_DCD_A_MIN_TIME_Pos)
+
+#define PCC_REG_BC12_CTRL3_DCD_B_MIN_TIME_Pos                                                    16U
+#define PCC_REG_BC12_CTRL3_DCD_B_MIN_TIME_Msk                                                    (0xFFFFUL << PCC_REG_BC12_CTRL3_DCD_B_MIN_TIME_Pos)
+
+/* 0x304    0x4000_0304
+    15:0    R/W     PRI_DET_MIN_TIME                                16'h500
+    31:16   R/W     NOTE_DET_MIN_TIME                               16'h140
+ */
+typedef union _PCC_REG_BC12_CTRL4_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t PRI_DET_MIN_TIME: 16;
+        uint32_t NOTE_DET_MIN_TIME: 16;
+    };
+} PCC_REG_BC12_CTRL4_TYPE;
+
+/*0x4000_0304 PCC_REG_BC12_CTRL4*/
+#define PCC_REG_BC12_CTRL4_PRI_DET_MIN_TIME_Pos                                                  0U
+#define PCC_REG_BC12_CTRL4_PRI_DET_MIN_TIME_Msk                                                  (0xFFFFUL << PCC_REG_BC12_CTRL4_PRI_DET_MIN_TIME_Pos)
+
+#define PCC_REG_BC12_CTRL4_NOTE_DET_MIN_TIME_Pos                                                 16U
+#define PCC_REG_BC12_CTRL4_NOTE_DET_MIN_TIME_Msk                                                 (0xFFFFUL << PCC_REG_BC12_CTRL4_NOTE_DET_MIN_TIME_Pos)
+
+/* 0x308    0x4000_0308
+    15:0    R/W     WAIT_A_MIN_TIME                                 16'h280
+    31:16   R/W     SECOND_DET_MIN_TIME                             16'h540
+ */
+typedef union _PCC_REG_BC12_CTRL5_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t WAIT_A_MIN_TIME: 16;
+        uint32_t SECOND_DET_MIN_TIME: 16;
+    };
+} PCC_REG_BC12_CTRL5_TYPE;
+
+/*0x4000_0308 PCC_REG_BC12_CTRL5*/
+#define PCC_REG_BC12_CTRL5_WAIT_A_MIN_TIME_Pos                                                   0U
+#define PCC_REG_BC12_CTRL5_WAIT_A_MIN_TIME_Msk                                                   (0xFFFFUL << PCC_REG_BC12_CTRL5_WAIT_A_MIN_TIME_Pos)
+
+#define PCC_REG_BC12_CTRL5_SECOND_DET_MIN_TIME_Pos                                               16U
+#define PCC_REG_BC12_CTRL5_SECOND_DET_MIN_TIME_Msk                                               (0xFFFFUL << PCC_REG_BC12_CTRL5_SECOND_DET_MIN_TIME_Pos)
+
+/* 0x30C    0x4000_030c
+    15:0    R/W     SA_DET_MIN_TIME                                 16'h140
+    31:16   R/W     DUMMY71                                         16'h0
+ */
+typedef union _PCC_REG_BC12_CTRL6_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t SA_DET_MIN_TIME: 16;
+        uint32_t DUMMY71: 16;
+    };
+} PCC_REG_BC12_CTRL6_TYPE;
+
+/*0x4000_030c PCC_REG_BC12_CTRL6*/
+#define PCC_REG_BC12_CTRL6_SA_DET_MIN_TIME_Pos                                                   0U
+#define PCC_REG_BC12_CTRL6_SA_DET_MIN_TIME_Msk                                                   (0xFFFFUL << PCC_REG_BC12_CTRL6_SA_DET_MIN_TIME_Pos)
+
+#define PCC_REG_BC12_CTRL6_DUMMY71_Pos                                                           16U
+#define PCC_REG_BC12_CTRL6_DUMMY71_Msk                                                           (0xFFFFUL << PCC_REG_BC12_CTRL6_DUMMY71_Pos)
+
+/* 0x310    0x4000_0310
+    3:0     R/W     R_PMUX_DBG_MODE_SEL_G0                          4'h0
+    7:4     R/W     R_PMUX_DBG_MODE_SEL_G1                          4'h0
+    11:8    R/W     R_PMUX_DBG_MODE_SEL_G2                          4'h0
+    15:12   R/W     R_PMUX_DBG_MODE_SEL_G3                          4'h0
+    17:16   R/W     R_DBG_MUX_SEC_SEL_G0                            2'h0
+    19:18   R/W     R_DBG_MUX_SEC_SEL_G1                            2'h0
+    21:20   R/W     R_DBG_MUX_SEC_SEL_G2                            2'h0
+    23:22   R/W     R_DBG_MUX_SEC_SEL_G3                            2'h0
+    31:24   R       RSVD                                            8'h00
+ */
+typedef union _PCC_REG_DBG_MUX_CTRL_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t R_PMUX_DBG_MODE_SEL_G0: 4;
+        uint32_t R_PMUX_DBG_MODE_SEL_G1: 4;
+        uint32_t R_PMUX_DBG_MODE_SEL_G2: 4;
+        uint32_t R_PMUX_DBG_MODE_SEL_G3: 4;
+        uint32_t R_DBG_MUX_SEC_SEL_G0: 2;
+        uint32_t R_DBG_MUX_SEC_SEL_G1: 2;
+        uint32_t R_DBG_MUX_SEC_SEL_G2: 2;
+        uint32_t R_DBG_MUX_SEC_SEL_G3: 2;
+        uint32_t RSVD: 8;
+    };
+} PCC_REG_DBG_MUX_CTRL_TYPE;
+
+/*0x4000_0310 PCC_REG_DBG_MUX_CTRL*/
+#define PCC_REG_DBG_MUX_CTRL_R_PMUX_DBG_MODE_SEL_G0_Pos                                          0U
+#define PCC_REG_DBG_MUX_CTRL_R_PMUX_DBG_MODE_SEL_G0_Msk                                          (0xFUL << PCC_REG_DBG_MUX_CTRL_R_PMUX_DBG_MODE_SEL_G0_Pos)
+
+#define PCC_REG_DBG_MUX_CTRL_R_PMUX_DBG_MODE_SEL_G1_Pos                                          4U
+#define PCC_REG_DBG_MUX_CTRL_R_PMUX_DBG_MODE_SEL_G1_Msk                                          (0xFUL << PCC_REG_DBG_MUX_CTRL_R_PMUX_DBG_MODE_SEL_G1_Pos)
+
+#define PCC_REG_DBG_MUX_CTRL_R_PMUX_DBG_MODE_SEL_G2_Pos                                          8U
+#define PCC_REG_DBG_MUX_CTRL_R_PMUX_DBG_MODE_SEL_G2_Msk                                          (0xFUL << PCC_REG_DBG_MUX_CTRL_R_PMUX_DBG_MODE_SEL_G2_Pos)
+
+#define PCC_REG_DBG_MUX_CTRL_R_PMUX_DBG_MODE_SEL_G3_Pos                                          12U
+#define PCC_REG_DBG_MUX_CTRL_R_PMUX_DBG_MODE_SEL_G3_Msk                                          (0xFUL << PCC_REG_DBG_MUX_CTRL_R_PMUX_DBG_MODE_SEL_G3_Pos)
+
+#define PCC_REG_DBG_MUX_CTRL_R_DBG_MUX_SEC_SEL_G0_Pos                                            16U
+#define PCC_REG_DBG_MUX_CTRL_R_DBG_MUX_SEC_SEL_G0_Msk                                            (0x3UL << PCC_REG_DBG_MUX_CTRL_R_DBG_MUX_SEC_SEL_G0_Pos)
+
+#define PCC_REG_DBG_MUX_CTRL_R_DBG_MUX_SEC_SEL_G1_Pos                                            18U
+#define PCC_REG_DBG_MUX_CTRL_R_DBG_MUX_SEC_SEL_G1_Msk                                            (0x3UL << PCC_REG_DBG_MUX_CTRL_R_DBG_MUX_SEC_SEL_G1_Pos)
+
+#define PCC_REG_DBG_MUX_CTRL_R_DBG_MUX_SEC_SEL_G2_Pos                                            20U
+#define PCC_REG_DBG_MUX_CTRL_R_DBG_MUX_SEC_SEL_G2_Msk                                            (0x3UL << PCC_REG_DBG_MUX_CTRL_R_DBG_MUX_SEC_SEL_G2_Pos)
+
+#define PCC_REG_DBG_MUX_CTRL_R_DBG_MUX_SEC_SEL_G3_Pos                                            22U
+#define PCC_REG_DBG_MUX_CTRL_R_DBG_MUX_SEC_SEL_G3_Msk                                            (0x3UL << PCC_REG_DBG_MUX_CTRL_R_DBG_MUX_SEC_SEL_G3_Pos)
+
+#define PCC_REG_DBG_MUX_CTRL_RSVD_Pos                                                            24U
+#define PCC_REG_DBG_MUX_CTRL_RSVD_Msk                                                            (0xFFUL << PCC_REG_DBG_MUX_CTRL_RSVD_Pos)
+
+/* 0x314    0x4000_0314
+    31:0    R       RSVD                                            32'hEAEAEAEA
+ */
+typedef union _PCC_REG_RSVD_2D8_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RSVD;
+    };
+} PCC_REG_RSVD_2D8_TYPE;
+
+/*0x4000_0314 PCC_REG_RSVD_2D8*/
+#define PCC_REG_RSVD_2D8_RSVD_Pos                                                                0U
+#define PCC_REG_RSVD_2D8_RSVD_Msk                                                                (0xFFFFFFFFUL << PCC_REG_RSVD_2D8_RSVD_Pos)
+
+/* 0x318    0x4000_0318
+    2:0     R/W     RF_0_REMAP_TABLE                                3'b000
+    3       R       RSVD_4                                          1'b0
+    6:4     R/W     RF_4_REMAP_TABLE                                3'b000
+    7       R       RSVD_3                                          1'b0
+    10:8    R/W     RF_5_REMAP_TABLE                                3'b001
+    11      R       RSVD_2                                          1'b0
+    14:12   R/W     RF_6_REMAP_TABLE                                3'b000
+    15      R       RSVD_1                                          1'b0
+    18:16   R/W     RF_7_REMAP_TABLE                                3'b010
+    30:19   R       RSVD                                            12'b000001100000
+    31      R/W     AUTO_SWITCH_UPDATE                              1'b0
+ */
+typedef union _PCC_REG_SWITCH_PAR_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RF_0_REMAP_TABLE: 3;
+        uint32_t RSVD_4: 1;
+        uint32_t RF_4_REMAP_TABLE: 3;
+        uint32_t RSVD_3: 1;
+        uint32_t RF_5_REMAP_TABLE: 3;
+        uint32_t RSVD_2: 1;
+        uint32_t RF_6_REMAP_TABLE: 3;
+        uint32_t RSVD_1: 1;
+        uint32_t RF_7_REMAP_TABLE: 3;
+        uint32_t RSVD: 12;
+        uint32_t AUTO_SWITCH_UPDATE: 1;
+    };
+} PCC_REG_SWITCH_PAR_TYPE;
+
+/*0x4000_0318 PCC_REG_SWITCH_PAR*/
+#define PCC_REG_SWITCH_PAR_RF_0_REMAP_TABLE_Pos                                                  0U
+#define PCC_REG_SWITCH_PAR_RF_0_REMAP_TABLE_Msk                                                  (0x7UL << PCC_REG_SWITCH_PAR_RF_0_REMAP_TABLE_Pos)
+
+#define PCC_REG_SWITCH_PAR_RSVD_4_Pos                                                            3U
+#define PCC_REG_SWITCH_PAR_RSVD_4_Msk                                                            (0x1UL << PCC_REG_SWITCH_PAR_RSVD_4_Pos)
+
+#define PCC_REG_SWITCH_PAR_RF_4_REMAP_TABLE_Pos                                                  4U
+#define PCC_REG_SWITCH_PAR_RF_4_REMAP_TABLE_Msk                                                  (0x7UL << PCC_REG_SWITCH_PAR_RF_4_REMAP_TABLE_Pos)
+
+#define PCC_REG_SWITCH_PAR_RSVD_3_Pos                                                            7U
+#define PCC_REG_SWITCH_PAR_RSVD_3_Msk                                                            (0x1UL << PCC_REG_SWITCH_PAR_RSVD_3_Pos)
+
+#define PCC_REG_SWITCH_PAR_RF_5_REMAP_TABLE_Pos                                                  8U
+#define PCC_REG_SWITCH_PAR_RF_5_REMAP_TABLE_Msk                                                  (0x7UL << PCC_REG_SWITCH_PAR_RF_5_REMAP_TABLE_Pos)
+
+#define PCC_REG_SWITCH_PAR_RSVD_2_Pos                                                            11U
+#define PCC_REG_SWITCH_PAR_RSVD_2_Msk                                                            (0x1UL << PCC_REG_SWITCH_PAR_RSVD_2_Pos)
+
+#define PCC_REG_SWITCH_PAR_RF_6_REMAP_TABLE_Pos                                                  12U
+#define PCC_REG_SWITCH_PAR_RF_6_REMAP_TABLE_Msk                                                  (0x7UL << PCC_REG_SWITCH_PAR_RF_6_REMAP_TABLE_Pos)
+
+#define PCC_REG_SWITCH_PAR_RSVD_1_Pos                                                            15U
+#define PCC_REG_SWITCH_PAR_RSVD_1_Msk                                                            (0x1UL << PCC_REG_SWITCH_PAR_RSVD_1_Pos)
+
+#define PCC_REG_SWITCH_PAR_RF_7_REMAP_TABLE_Pos                                                  16U
+#define PCC_REG_SWITCH_PAR_RF_7_REMAP_TABLE_Msk                                                  (0x7UL << PCC_REG_SWITCH_PAR_RF_7_REMAP_TABLE_Pos)
+
+#define PCC_REG_SWITCH_PAR_RSVD_Pos                                                              19U
+#define PCC_REG_SWITCH_PAR_RSVD_Msk                                                              (0xFFFUL << PCC_REG_SWITCH_PAR_RSVD_Pos)
+
+#define PCC_REG_SWITCH_PAR_AUTO_SWITCH_UPDATE_Pos                                                31U
+#define PCC_REG_SWITCH_PAR_AUTO_SWITCH_UPDATE_Msk                                                (0x1UL << PCC_REG_SWITCH_PAR_AUTO_SWITCH_UPDATE_Pos)
+
+/* 0x31C    0x4000_031c
+    31:0    R/W     R_PMUX_DIGI_DBG_REG                             32'h0
+ */
+typedef union _PCC_REG_PINMUX_DBG_REG_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t R_PMUX_DIGI_DBG_REG;
+    };
+} PCC_REG_PINMUX_DBG_REG_TYPE;
+
+/*0x4000_031c PCC_REG_PINMUX_DBG_REG*/
+#define PCC_REG_PINMUX_DBG_REG_R_PMUX_DIGI_DBG_REG_Pos                                           0U
+#define PCC_REG_PINMUX_DBG_REG_R_PMUX_DIGI_DBG_REG_Msk                                           (0xFFFFFFFFUL << PCC_REG_PINMUX_DBG_REG_R_PMUX_DIGI_DBG_REG_Pos)
+
+/* 0x320    0x4000_0320
+    15:0    R/W     DUMMY73                                         15'h0
+    24:16   R       RSVD_1                                          10'h0
+    25      R/W     RSVD                                            1'b0
+    31:26   R/W     LDOPA_VOUT_SW_VOUT_TUNE                         6'b000101
+ */
+typedef union _PCC_LDO_PA_SWR_AUTO_SW_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t DUMMY73: 16;
+        uint32_t RSVD_1: 9;
+        uint32_t RSVD: 1;
+        uint32_t LDOPA_VOUT_SW_VOUT_TUNE: 6;
+    };
+} PCC_LDO_PA_SWR_AUTO_SW_TYPE;
+
+/*0x4000_0320 PCC_LDO_PA_SWR_AUTO_SW*/
+#define PCC_LDO_PA_SWR_AUTO_SW_DUMMY73_Pos                                                       0U
+#define PCC_LDO_PA_SWR_AUTO_SW_DUMMY73_Msk                                                       (0xFFFFUL << PCC_LDO_PA_SWR_AUTO_SW_DUMMY73_Pos)
+
+#define PCC_LDO_PA_SWR_AUTO_SW_RSVD_1_Pos                                                        16U
+#define PCC_LDO_PA_SWR_AUTO_SW_RSVD_1_Msk                                                        (0x1FFUL << PCC_LDO_PA_SWR_AUTO_SW_RSVD_1_Pos)
+
+#define PCC_LDO_PA_SWR_AUTO_SW_RSVD_Pos                                                          25U
+#define PCC_LDO_PA_SWR_AUTO_SW_RSVD_Msk                                                          (0x1UL << PCC_LDO_PA_SWR_AUTO_SW_RSVD_Pos)
+
+#define PCC_LDO_PA_SWR_AUTO_SW_LDOPA_VOUT_SW_VOUT_TUNE_Pos                                       26U
+#define PCC_LDO_PA_SWR_AUTO_SW_LDOPA_VOUT_SW_VOUT_TUNE_Msk                                       (0x3FUL << PCC_LDO_PA_SWR_AUTO_SW_LDOPA_VOUT_SW_VOUT_TUNE_Pos)
+
+/* 0x324    0x4000_0324
+    7:0     R/W     TUNE_VDDCORE_0                                  8'b01100010
+    12:8    R/W     TON2_TUNE_0                                     5'b01000
+    17:13   R/W     TON1_TUNE_0                                     5'b01000
+    18      R/W     RESERVED                                        1'b1
+    23:19   R/W     LDO_TUNE_LDOANA_0                               5'b00101
+    31:24   R/W     TUNE_VDDPA_0                                    8'b00100010
+ */
+typedef union _PCC_CORE_SWR_PAR_TAB_0_0_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t TUNE_VDDCORE_0: 8;
+        uint32_t TON2_TUNE_0: 5;
+        uint32_t TON1_TUNE_0: 5;
+        uint32_t RESERVED: 1;
+        uint32_t LDO_TUNE_LDOANA_0: 5;
+        uint32_t TUNE_VDDPA_0: 8;
+    };
+} PCC_CORE_SWR_PAR_TAB_0_0_TYPE;
+
+/*0x4000_0324 PCC_CORE_SWR_PAR_TAB_0_0*/
+#define PCC_CORE_SWR_PAR_TAB_0_0_TUNE_VDDCORE_0_Pos                                              0U
+#define PCC_CORE_SWR_PAR_TAB_0_0_TUNE_VDDCORE_0_Msk                                              (0xFFUL << PCC_CORE_SWR_PAR_TAB_0_0_TUNE_VDDCORE_0_Pos)
+
+#define PCC_CORE_SWR_PAR_TAB_0_0_TON2_TUNE_0_Pos                                                 8U
+#define PCC_CORE_SWR_PAR_TAB_0_0_TON2_TUNE_0_Msk                                                 (0x1FUL << PCC_CORE_SWR_PAR_TAB_0_0_TON2_TUNE_0_Pos)
+
+#define PCC_CORE_SWR_PAR_TAB_0_0_TON1_TUNE_0_Pos                                                 13U
+#define PCC_CORE_SWR_PAR_TAB_0_0_TON1_TUNE_0_Msk                                                 (0x1FUL << PCC_CORE_SWR_PAR_TAB_0_0_TON1_TUNE_0_Pos)
+
+#define PCC_CORE_SWR_PAR_TAB_0_0_RESERVED_Pos                                                    18U
+#define PCC_CORE_SWR_PAR_TAB_0_0_RESERVED_Msk                                                    (0x1UL << PCC_CORE_SWR_PAR_TAB_0_0_RESERVED_Pos)
+
+#define PCC_CORE_SWR_PAR_TAB_0_0_LDO_TUNE_LDOANA_0_Pos                                           19U
+#define PCC_CORE_SWR_PAR_TAB_0_0_LDO_TUNE_LDOANA_0_Msk                                           (0x1FUL << PCC_CORE_SWR_PAR_TAB_0_0_LDO_TUNE_LDOANA_0_Pos)
+
+#define PCC_CORE_SWR_PAR_TAB_0_0_TUNE_VDDPA_0_Pos                                                24U
+#define PCC_CORE_SWR_PAR_TAB_0_0_TUNE_VDDPA_0_Msk                                                (0xFFUL << PCC_CORE_SWR_PAR_TAB_0_0_TUNE_VDDPA_0_Pos)
+
+/* 0x328    0x4000_0328
+    7:0     R/W     TUNE_VDDCORE_4                                  8'b01100010
+    12:8    R/W     TON2_TUNE_4                                     5'b01000
+    17:13   R/W     TON1_TUNE_4                                     5'b01000
+    18      R/W     RESERVED                                        1'b1
+    23:19   R/W     LDO_TUNE_LDOANA_4                               5'b00101
+    31:24   R/W     TUNE_VDDPA_4                                    8'b01111010
+ */
+typedef union _PCC_CORE_SWR_PAR_TAB_4_0_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t TUNE_VDDCORE_4: 8;
+        uint32_t TON2_TUNE_4: 5;
+        uint32_t TON1_TUNE_4: 5;
+        uint32_t RESERVED: 1;
+        uint32_t LDO_TUNE_LDOANA_4: 5;
+        uint32_t TUNE_VDDPA_4: 8;
+    };
+} PCC_CORE_SWR_PAR_TAB_4_0_TYPE;
+
+/*0x4000_0328 PCC_CORE_SWR_PAR_TAB_4_0*/
+#define PCC_CORE_SWR_PAR_TAB_4_0_TUNE_VDDCORE_4_Pos                                              0U
+#define PCC_CORE_SWR_PAR_TAB_4_0_TUNE_VDDCORE_4_Msk                                              (0xFFUL << PCC_CORE_SWR_PAR_TAB_4_0_TUNE_VDDCORE_4_Pos)
+
+#define PCC_CORE_SWR_PAR_TAB_4_0_TON2_TUNE_4_Pos                                                 8U
+#define PCC_CORE_SWR_PAR_TAB_4_0_TON2_TUNE_4_Msk                                                 (0x1FUL << PCC_CORE_SWR_PAR_TAB_4_0_TON2_TUNE_4_Pos)
+
+#define PCC_CORE_SWR_PAR_TAB_4_0_TON1_TUNE_4_Pos                                                 13U
+#define PCC_CORE_SWR_PAR_TAB_4_0_TON1_TUNE_4_Msk                                                 (0x1FUL << PCC_CORE_SWR_PAR_TAB_4_0_TON1_TUNE_4_Pos)
+
+#define PCC_CORE_SWR_PAR_TAB_4_0_RESERVED_Pos                                                    18U
+#define PCC_CORE_SWR_PAR_TAB_4_0_RESERVED_Msk                                                    (0x1UL << PCC_CORE_SWR_PAR_TAB_4_0_RESERVED_Pos)
+
+#define PCC_CORE_SWR_PAR_TAB_4_0_LDO_TUNE_LDOANA_4_Pos                                           19U
+#define PCC_CORE_SWR_PAR_TAB_4_0_LDO_TUNE_LDOANA_4_Msk                                           (0x1FUL << PCC_CORE_SWR_PAR_TAB_4_0_LDO_TUNE_LDOANA_4_Pos)
+
+#define PCC_CORE_SWR_PAR_TAB_4_0_TUNE_VDDPA_4_Pos                                                24U
+#define PCC_CORE_SWR_PAR_TAB_4_0_TUNE_VDDPA_4_Msk                                                (0xFFUL << PCC_CORE_SWR_PAR_TAB_4_0_TUNE_VDDPA_4_Pos)
+
+/* 0x32C    0x4000_032c
+    7:0     R/W     TUNE_VDDCORE_5                                  8'b01100010
+    12:8    R/W     TON2_TUNE_5                                     5'b01000
+    17:13   R/W     TON1_TUNE_5                                     5'b01000
+    18      R/W     RESERVED                                        1'b1
+    23:19   R/W     LDO_TUNE_LDOANA_5                               5'b00101
+    31:24   R/W     TUNE_VDDPA_5                                    8'b01111010
+ */
+typedef union _PCC_CORE_SWR_PAR_TAB_5_0_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t TUNE_VDDCORE_5: 8;
+        uint32_t TON2_TUNE_5: 5;
+        uint32_t TON1_TUNE_5: 5;
+        uint32_t RESERVED: 1;
+        uint32_t LDO_TUNE_LDOANA_5: 5;
+        uint32_t TUNE_VDDPA_5: 8;
+    };
+} PCC_CORE_SWR_PAR_TAB_5_0_TYPE;
+
+/*0x4000_032c PCC_CORE_SWR_PAR_TAB_5_0*/
+#define PCC_CORE_SWR_PAR_TAB_5_0_TUNE_VDDCORE_5_Pos                                              0U
+#define PCC_CORE_SWR_PAR_TAB_5_0_TUNE_VDDCORE_5_Msk                                              (0xFFUL << PCC_CORE_SWR_PAR_TAB_5_0_TUNE_VDDCORE_5_Pos)
+
+#define PCC_CORE_SWR_PAR_TAB_5_0_TON2_TUNE_5_Pos                                                 8U
+#define PCC_CORE_SWR_PAR_TAB_5_0_TON2_TUNE_5_Msk                                                 (0x1FUL << PCC_CORE_SWR_PAR_TAB_5_0_TON2_TUNE_5_Pos)
+
+#define PCC_CORE_SWR_PAR_TAB_5_0_TON1_TUNE_5_Pos                                                 13U
+#define PCC_CORE_SWR_PAR_TAB_5_0_TON1_TUNE_5_Msk                                                 (0x1FUL << PCC_CORE_SWR_PAR_TAB_5_0_TON1_TUNE_5_Pos)
+
+#define PCC_CORE_SWR_PAR_TAB_5_0_RESERVED_Pos                                                    18U
+#define PCC_CORE_SWR_PAR_TAB_5_0_RESERVED_Msk                                                    (0x1UL << PCC_CORE_SWR_PAR_TAB_5_0_RESERVED_Pos)
+
+#define PCC_CORE_SWR_PAR_TAB_5_0_LDO_TUNE_LDOANA_5_Pos                                           19U
+#define PCC_CORE_SWR_PAR_TAB_5_0_LDO_TUNE_LDOANA_5_Msk                                           (0x1FUL << PCC_CORE_SWR_PAR_TAB_5_0_LDO_TUNE_LDOANA_5_Pos)
+
+#define PCC_CORE_SWR_PAR_TAB_5_0_TUNE_VDDPA_5_Pos                                                24U
+#define PCC_CORE_SWR_PAR_TAB_5_0_TUNE_VDDPA_5_Msk                                                (0xFFUL << PCC_CORE_SWR_PAR_TAB_5_0_TUNE_VDDPA_5_Pos)
+
+/* 0x330    0x4000_0330
+    7:0     R/W     TUNE_VDDCORE_6                                  8'b01100010
+    12:8    R/W     TON2_TUNE_6                                     5'b01000
+    17:13   R/W     TON1_TUNE_6                                     5'b01000
+    18      R/W     RESERVED                                        1'b1
+    23:19   R/W     LDO_TUNE_LDOANA_6                               5'b00101
+    31:24   R/W     TUNE_VDDPA_6                                    8'b01111010
+ */
+typedef union _PCC_CORE_SWR_PAR_TAB_6_0_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t TUNE_VDDCORE_6: 8;
+        uint32_t TON2_TUNE_6: 5;
+        uint32_t TON1_TUNE_6: 5;
+        uint32_t RESERVED: 1;
+        uint32_t LDO_TUNE_LDOANA_6: 5;
+        uint32_t TUNE_VDDPA_6: 8;
+    };
+} PCC_CORE_SWR_PAR_TAB_6_0_TYPE;
+
+/*0x4000_0330 PCC_CORE_SWR_PAR_TAB_6_0*/
+#define PCC_CORE_SWR_PAR_TAB_6_0_TUNE_VDDCORE_6_Pos                                              0U
+#define PCC_CORE_SWR_PAR_TAB_6_0_TUNE_VDDCORE_6_Msk                                              (0xFFUL << PCC_CORE_SWR_PAR_TAB_6_0_TUNE_VDDCORE_6_Pos)
+
+#define PCC_CORE_SWR_PAR_TAB_6_0_TON2_TUNE_6_Pos                                                 8U
+#define PCC_CORE_SWR_PAR_TAB_6_0_TON2_TUNE_6_Msk                                                 (0x1FUL << PCC_CORE_SWR_PAR_TAB_6_0_TON2_TUNE_6_Pos)
+
+#define PCC_CORE_SWR_PAR_TAB_6_0_TON1_TUNE_6_Pos                                                 13U
+#define PCC_CORE_SWR_PAR_TAB_6_0_TON1_TUNE_6_Msk                                                 (0x1FUL << PCC_CORE_SWR_PAR_TAB_6_0_TON1_TUNE_6_Pos)
+
+#define PCC_CORE_SWR_PAR_TAB_6_0_RESERVED_Pos                                                    18U
+#define PCC_CORE_SWR_PAR_TAB_6_0_RESERVED_Msk                                                    (0x1UL << PCC_CORE_SWR_PAR_TAB_6_0_RESERVED_Pos)
+
+#define PCC_CORE_SWR_PAR_TAB_6_0_LDO_TUNE_LDOANA_6_Pos                                           19U
+#define PCC_CORE_SWR_PAR_TAB_6_0_LDO_TUNE_LDOANA_6_Msk                                           (0x1FUL << PCC_CORE_SWR_PAR_TAB_6_0_LDO_TUNE_LDOANA_6_Pos)
+
+#define PCC_CORE_SWR_PAR_TAB_6_0_TUNE_VDDPA_6_Pos                                                24U
+#define PCC_CORE_SWR_PAR_TAB_6_0_TUNE_VDDPA_6_Msk                                                (0xFFUL << PCC_CORE_SWR_PAR_TAB_6_0_TUNE_VDDPA_6_Pos)
+
+/* 0x334    0x4000_0334
+    7:0     R/W     TUNE_VDDCORE_7                                  8'b01100010
+    12:8    R/W     TON2_TUNE_7                                     5'b01000
+    17:13   R/W     TON1_TUNE_7                                     5'b01000
+    18      R/W     RESERVED                                        1'b1
+    23:19   R/W     LDO_TUNE_LDOANA_7                               5'b00101
+    31:24   R/W     TUNE_VDDPA_7                                    8'b01111010
+ */
+typedef union _PCC_CORE_SWR_PAR_TAB_7_0_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t TUNE_VDDCORE_7: 8;
+        uint32_t TON2_TUNE_7: 5;
+        uint32_t TON1_TUNE_7: 5;
+        uint32_t RESERVED: 1;
+        uint32_t LDO_TUNE_LDOANA_7: 5;
+        uint32_t TUNE_VDDPA_7: 8;
+    };
+} PCC_CORE_SWR_PAR_TAB_7_0_TYPE;
+
+/*0x4000_0334 PCC_CORE_SWR_PAR_TAB_7_0*/
+#define PCC_CORE_SWR_PAR_TAB_7_0_TUNE_VDDCORE_7_Pos                                              0U
+#define PCC_CORE_SWR_PAR_TAB_7_0_TUNE_VDDCORE_7_Msk                                              (0xFFUL << PCC_CORE_SWR_PAR_TAB_7_0_TUNE_VDDCORE_7_Pos)
+
+#define PCC_CORE_SWR_PAR_TAB_7_0_TON2_TUNE_7_Pos                                                 8U
+#define PCC_CORE_SWR_PAR_TAB_7_0_TON2_TUNE_7_Msk                                                 (0x1FUL << PCC_CORE_SWR_PAR_TAB_7_0_TON2_TUNE_7_Pos)
+
+#define PCC_CORE_SWR_PAR_TAB_7_0_TON1_TUNE_7_Pos                                                 13U
+#define PCC_CORE_SWR_PAR_TAB_7_0_TON1_TUNE_7_Msk                                                 (0x1FUL << PCC_CORE_SWR_PAR_TAB_7_0_TON1_TUNE_7_Pos)
+
+#define PCC_CORE_SWR_PAR_TAB_7_0_RESERVED_Pos                                                    18U
+#define PCC_CORE_SWR_PAR_TAB_7_0_RESERVED_Msk                                                    (0x1UL << PCC_CORE_SWR_PAR_TAB_7_0_RESERVED_Pos)
+
+#define PCC_CORE_SWR_PAR_TAB_7_0_LDO_TUNE_LDOANA_7_Pos                                           19U
+#define PCC_CORE_SWR_PAR_TAB_7_0_LDO_TUNE_LDOANA_7_Msk                                           (0x1FUL << PCC_CORE_SWR_PAR_TAB_7_0_LDO_TUNE_LDOANA_7_Pos)
+
+#define PCC_CORE_SWR_PAR_TAB_7_0_TUNE_VDDPA_7_Pos                                                24U
+#define PCC_CORE_SWR_PAR_TAB_7_0_TUNE_VDDPA_7_Msk                                                (0xFFUL << PCC_CORE_SWR_PAR_TAB_7_0_TUNE_VDDPA_7_Pos)
+
+/* 0x338    0x4000_0338
+    5:0     R/W     CORE_SWR_PAR_TAB_7                              6'h0
+    11:6    R/W     CORE_SWR_PAR_TAB_6                              6'h0
+    17:12   R/W     CORE_SWR_PAR_TAB_5                              6'h0
+    23:18   R/W     CORE_SWR_PAR_TAB_4                              6'h0
+    29:24   R/W     CORE_SWR_PAR_TAB_0                              6'h0
+    31:30   R/W     DUMMY74                                         2'b00
+ */
+typedef union _PCC_REG_CORE_PAR_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t CORE_SWR_PAR_TAB_7: 6;
+        uint32_t CORE_SWR_PAR_TAB_6: 6;
+        uint32_t CORE_SWR_PAR_TAB_5: 6;
+        uint32_t CORE_SWR_PAR_TAB_4: 6;
+        uint32_t CORE_SWR_PAR_TAB_0: 6;
+        uint32_t DUMMY74: 2;
+    };
+} PCC_REG_CORE_PAR_TYPE;
+
+/*0x4000_0338 PCC_REG_CORE_PAR*/
+#define PCC_REG_CORE_PAR_CORE_SWR_PAR_TAB_7_Pos                                                  0U
+#define PCC_REG_CORE_PAR_CORE_SWR_PAR_TAB_7_Msk                                                  (0x3FUL << PCC_REG_CORE_PAR_CORE_SWR_PAR_TAB_7_Pos)
+
+#define PCC_REG_CORE_PAR_CORE_SWR_PAR_TAB_6_Pos                                                  6U
+#define PCC_REG_CORE_PAR_CORE_SWR_PAR_TAB_6_Msk                                                  (0x3FUL << PCC_REG_CORE_PAR_CORE_SWR_PAR_TAB_6_Pos)
+
+#define PCC_REG_CORE_PAR_CORE_SWR_PAR_TAB_5_Pos                                                  12U
+#define PCC_REG_CORE_PAR_CORE_SWR_PAR_TAB_5_Msk                                                  (0x3FUL << PCC_REG_CORE_PAR_CORE_SWR_PAR_TAB_5_Pos)
+
+#define PCC_REG_CORE_PAR_CORE_SWR_PAR_TAB_4_Pos                                                  18U
+#define PCC_REG_CORE_PAR_CORE_SWR_PAR_TAB_4_Msk                                                  (0x3FUL << PCC_REG_CORE_PAR_CORE_SWR_PAR_TAB_4_Pos)
+
+#define PCC_REG_CORE_PAR_CORE_SWR_PAR_TAB_0_Pos                                                  24U
+#define PCC_REG_CORE_PAR_CORE_SWR_PAR_TAB_0_Msk                                                  (0x3FUL << PCC_REG_CORE_PAR_CORE_SWR_PAR_TAB_0_Pos)
+
+#define PCC_REG_CORE_PAR_DUMMY74_Pos                                                             30U
+#define PCC_REG_CORE_PAR_DUMMY74_Msk                                                             (0x3UL << PCC_REG_CORE_PAR_DUMMY74_Pos)
+
+/* 0x33C    0x4000_033c
+    7:0     R/W     PON_PERI_DLYSEL_CTRL                            8'h0
+    15:8    R/W     DUMMY79                                         8'h0
+    23:16   R/W     DUMMY78                                         8'h0
+    24      R/W     R_FLASH0_CLK_INV_EN                             0
+    25      R/W     DUMMY77                                         0
+    26      R/W     DUMMY76                                         0
+    30:27   R/W     DUMMY75                                         4'h0
+    31      R/W     R_SPIC2_DMA_TX_REQ_AS_SINGLE                    0
+ */
+typedef union _PCC_PON_PERI_DLYSEL_CTRL_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t PON_PERI_DLYSEL_CTRL: 8;
+        uint32_t DUMMY79: 8;
+        uint32_t DUMMY78: 8;
+        uint32_t R_FLASH0_CLK_INV_EN: 1;
+        uint32_t DUMMY77: 1;
+        uint32_t DUMMY76: 1;
+        uint32_t DUMMY75: 4;
+        uint32_t R_SPIC2_DMA_TX_REQ_AS_SINGLE: 1;
+    };
+} PCC_PON_PERI_DLYSEL_CTRL_TYPE;
+
+/*0x4000_033c PCC_PON_PERI_DLYSEL_CTRL*/
+#define PCC_PON_PERI_DLYSEL_CTRL_PON_PERI_DLYSEL_CTRL_Pos                                        0U
+#define PCC_PON_PERI_DLYSEL_CTRL_PON_PERI_DLYSEL_CTRL_Msk                                        (0xFFUL << PCC_PON_PERI_DLYSEL_CTRL_PON_PERI_DLYSEL_CTRL_Pos)
+
+#define PCC_PON_PERI_DLYSEL_CTRL_DUMMY79_Pos                                                     8U
+#define PCC_PON_PERI_DLYSEL_CTRL_DUMMY79_Msk                                                     (0xFFUL << PCC_PON_PERI_DLYSEL_CTRL_DUMMY79_Pos)
+
+#define PCC_PON_PERI_DLYSEL_CTRL_DUMMY78_Pos                                                     16U
+#define PCC_PON_PERI_DLYSEL_CTRL_DUMMY78_Msk                                                     (0xFFUL << PCC_PON_PERI_DLYSEL_CTRL_DUMMY78_Pos)
+
+#define PCC_PON_PERI_DLYSEL_CTRL_R_FLASH0_CLK_INV_EN_Pos                                         24U
+#define PCC_PON_PERI_DLYSEL_CTRL_R_FLASH0_CLK_INV_EN_Msk                                         (0x1UL << PCC_PON_PERI_DLYSEL_CTRL_R_FLASH0_CLK_INV_EN_Pos)
+
+#define PCC_PON_PERI_DLYSEL_CTRL_DUMMY77_Pos                                                     25U
+#define PCC_PON_PERI_DLYSEL_CTRL_DUMMY77_Msk                                                     (0x1UL << PCC_PON_PERI_DLYSEL_CTRL_DUMMY77_Pos)
+
+#define PCC_PON_PERI_DLYSEL_CTRL_DUMMY76_Pos                                                     26U
+#define PCC_PON_PERI_DLYSEL_CTRL_DUMMY76_Msk                                                     (0x1UL << PCC_PON_PERI_DLYSEL_CTRL_DUMMY76_Pos)
+
+#define PCC_PON_PERI_DLYSEL_CTRL_DUMMY75_Pos                                                     27U
+#define PCC_PON_PERI_DLYSEL_CTRL_DUMMY75_Msk                                                     (0xFUL << PCC_PON_PERI_DLYSEL_CTRL_DUMMY75_Pos)
+
+#define PCC_PON_PERI_DLYSEL_CTRL_R_SPIC2_DMA_TX_REQ_AS_SINGLE_Pos                                31U
+#define PCC_PON_PERI_DLYSEL_CTRL_R_SPIC2_DMA_TX_REQ_AS_SINGLE_Msk                                (0x1UL << PCC_PON_PERI_DLYSEL_CTRL_R_SPIC2_DMA_TX_REQ_AS_SINGLE_Pos)
+
+/* 0x340    0x4000_0340
+    19:0    R/W     R_DSS_DATA_IN                                   20'h1543d
+    22:20   R/W     R_DSS_RO_SEL                                    3'd0
+    23      R/W     R_DSS_WIRE_SEL                                  1'd0
+    24      R/W     R_DSS_CLK_EN                                    1'd0
+    25      R/W     R_DSS_SPEED_EN                                  1'd0
+    31:26   R/W     DUMMY80                                         6'h0
+ */
+typedef union _PCC_REG_DSS_CTRL0_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t R_DSS_DATA_IN: 20;
+        uint32_t R_DSS_RO_SEL: 3;
+        uint32_t R_DSS_WIRE_SEL: 1;
+        uint32_t R_DSS_CLK_EN: 1;
+        uint32_t R_DSS_SPEED_EN: 1;
+        uint32_t DUMMY80: 6;
+    };
+} PCC_REG_DSS_CTRL0_TYPE;
+
+/*0x4000_0340 PCC_REG_DSS_CTRL0*/
+#define PCC_REG_DSS_CTRL0_R_DSS_DATA_IN_Pos                                                      0U
+#define PCC_REG_DSS_CTRL0_R_DSS_DATA_IN_Msk                                                      (0xFFFFFUL << PCC_REG_DSS_CTRL0_R_DSS_DATA_IN_Pos)
+
+#define PCC_REG_DSS_CTRL0_R_DSS_RO_SEL_Pos                                                       20U
+#define PCC_REG_DSS_CTRL0_R_DSS_RO_SEL_Msk                                                       (0x7UL << PCC_REG_DSS_CTRL0_R_DSS_RO_SEL_Pos)
+
+#define PCC_REG_DSS_CTRL0_R_DSS_WIRE_SEL_Pos                                                     23U
+#define PCC_REG_DSS_CTRL0_R_DSS_WIRE_SEL_Msk                                                     (0x1UL << PCC_REG_DSS_CTRL0_R_DSS_WIRE_SEL_Pos)
+
+#define PCC_REG_DSS_CTRL0_R_DSS_CLK_EN_Pos                                                       24U
+#define PCC_REG_DSS_CTRL0_R_DSS_CLK_EN_Msk                                                       (0x1UL << PCC_REG_DSS_CTRL0_R_DSS_CLK_EN_Pos)
+
+#define PCC_REG_DSS_CTRL0_R_DSS_SPEED_EN_Pos                                                     25U
+#define PCC_REG_DSS_CTRL0_R_DSS_SPEED_EN_Msk                                                     (0x1UL << PCC_REG_DSS_CTRL0_R_DSS_SPEED_EN_Pos)
+
+#define PCC_REG_DSS_CTRL0_DUMMY80_Pos                                                            26U
+#define PCC_REG_DSS_CTRL0_DUMMY80_Msk                                                            (0x3FUL << PCC_REG_DSS_CTRL0_DUMMY80_Pos)
+
+/* 0x344    0x4000_0344
+    19:0    R       DSS_POW_COUNT                                   20'd0
+    20      R       DSS_POW_WSORT_GO                                0
+    21      R       DSS_POW_READY                                   0
+    31:22   R       RSVD                                            10'h0
+ */
+typedef union _PCC_REG_DSS_CTRL1_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t DSS_POW_COUNT: 20;
+        uint32_t DSS_POW_WSORT_GO: 1;
+        uint32_t DSS_POW_READY: 1;
+        uint32_t RSVD: 10;
+    };
+} PCC_REG_DSS_CTRL1_TYPE;
+
+/*0x4000_0344 PCC_REG_DSS_CTRL1*/
+#define PCC_REG_DSS_CTRL1_DSS_POW_COUNT_Pos                                                      0U
+#define PCC_REG_DSS_CTRL1_DSS_POW_COUNT_Msk                                                      (0xFFFFFUL << PCC_REG_DSS_CTRL1_DSS_POW_COUNT_Pos)
+
+#define PCC_REG_DSS_CTRL1_DSS_POW_WSORT_GO_Pos                                                   20U
+#define PCC_REG_DSS_CTRL1_DSS_POW_WSORT_GO_Msk                                                   (0x1UL << PCC_REG_DSS_CTRL1_DSS_POW_WSORT_GO_Pos)
+
+#define PCC_REG_DSS_CTRL1_DSS_POW_READY_Pos                                                      21U
+#define PCC_REG_DSS_CTRL1_DSS_POW_READY_Msk                                                      (0x1UL << PCC_REG_DSS_CTRL1_DSS_POW_READY_Pos)
+
+#define PCC_REG_DSS_CTRL1_RSVD_Pos                                                               22U
+#define PCC_REG_DSS_CTRL1_RSVD_Msk                                                               (0x3FFUL << PCC_REG_DSS_CTRL1_RSVD_Pos)
+
+/* 0x348    0x4000_0348
+    19:0    R       DSS_IR_COUNT                                    20'd0
+    20      R       DSS_IR_WSORT_GO                                 0
+    21      R       DSS_IR_READY                                    0
+    31:22   R       RSVD                                            10'h0
+ */
+typedef union _PCC_REG_DSS_CTRL2_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t DSS_IR_COUNT: 20;
+        uint32_t DSS_IR_WSORT_GO: 1;
+        uint32_t DSS_IR_READY: 1;
+        uint32_t RSVD: 10;
+    };
+} PCC_REG_DSS_CTRL2_TYPE;
+
+/*0x4000_0348 PCC_REG_DSS_CTRL2*/
+#define PCC_REG_DSS_CTRL2_DSS_IR_COUNT_Pos                                                       0U
+#define PCC_REG_DSS_CTRL2_DSS_IR_COUNT_Msk                                                       (0xFFFFFUL << PCC_REG_DSS_CTRL2_DSS_IR_COUNT_Pos)
+
+#define PCC_REG_DSS_CTRL2_DSS_IR_WSORT_GO_Pos                                                    20U
+#define PCC_REG_DSS_CTRL2_DSS_IR_WSORT_GO_Msk                                                    (0x1UL << PCC_REG_DSS_CTRL2_DSS_IR_WSORT_GO_Pos)
+
+#define PCC_REG_DSS_CTRL2_DSS_IR_READY_Pos                                                       21U
+#define PCC_REG_DSS_CTRL2_DSS_IR_READY_Msk                                                       (0x1UL << PCC_REG_DSS_CTRL2_DSS_IR_READY_Pos)
+
+#define PCC_REG_DSS_CTRL2_RSVD_Pos                                                               22U
+#define PCC_REG_DSS_CTRL2_RSVD_Msk                                                               (0x3FFUL << PCC_REG_DSS_CTRL2_RSVD_Pos)
+
+/* 0x34C    0x4000_034c
+    3:0     R       OSC40_FSET                                      4'h0
+    7:4     R       RSVD                                            4'h0
+    31:8    R/W     DUMMY84                                         24'h000109
+ */
+typedef union _PCC_REG_OSC40_CTRL_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t OSC40_FSET: 4;
+        uint32_t RSVD: 4;
+        uint32_t DUMMY84: 24;
+    };
+} PCC_REG_OSC40_CTRL_TYPE;
+
+/*0x4000_034c PCC_REG_OSC40_CTRL*/
+#define PCC_REG_OSC40_CTRL_OSC40_FSET_Pos                                                        0U
+#define PCC_REG_OSC40_CTRL_OSC40_FSET_Msk                                                        (0xFUL << PCC_REG_OSC40_CTRL_OSC40_FSET_Pos)
+
+#define PCC_REG_OSC40_CTRL_RSVD_Pos                                                              4U
+#define PCC_REG_OSC40_CTRL_RSVD_Msk                                                              (0xFUL << PCC_REG_OSC40_CTRL_RSVD_Pos)
+
+#define PCC_REG_OSC40_CTRL_DUMMY84_Pos                                                           8U
+#define PCC_REG_OSC40_CTRL_DUMMY84_Msk                                                           (0xFFFFFFUL << PCC_REG_OSC40_CTRL_DUMMY84_Pos)
+
+/* 0x350    0x4000_0350
+    0       R/W     RST_N_AAC                                       0
+    1       R/W     OFFSET_PLUS                                     0
+    7:2     R/W     XAAC_GM_OFFSET                                  6'b000000
+    8       R/W     GM_STEP                                         0
+    14:9    R/W     GM_INIT                                         6'b111110
+    17:15   R/W     XTAL_CLK_SET                                    3'b101
+    23:18   R/W     GM_STUP                                         6'b111111
+    29:24   R/W     GM_MANUAL                                       6'b111111
+    30      R/W     R_EN_XTAL_AAC_DIGI                              0
+    31      R/W     R_EN_XTAL_AAC_TRIG                              0
+ */
+typedef union _PCC_REG_AAC_0_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RST_N_AAC: 1;
+        uint32_t OFFSET_PLUS: 1;
+        uint32_t XAAC_GM_OFFSET: 6;
+        uint32_t GM_STEP: 1;
+        uint32_t GM_INIT: 6;
+        uint32_t XTAL_CLK_SET: 3;
+        uint32_t GM_STUP: 6;
+        uint32_t GM_MANUAL: 6;
+        uint32_t R_EN_XTAL_AAC_DIGI: 1;
+        uint32_t R_EN_XTAL_AAC_TRIG: 1;
+    };
+} PCC_REG_AAC_0_TYPE;
+
+/*0x4000_0350 PCC_REG_AAC_0*/
+#define PCC_REG_AAC_0_RST_N_AAC_Pos                                                              0U
+#define PCC_REG_AAC_0_RST_N_AAC_Msk                                                              (0x1UL << PCC_REG_AAC_0_RST_N_AAC_Pos)
+
+#define PCC_REG_AAC_0_OFFSET_PLUS_Pos                                                            1U
+#define PCC_REG_AAC_0_OFFSET_PLUS_Msk                                                            (0x1UL << PCC_REG_AAC_0_OFFSET_PLUS_Pos)
+
+#define PCC_REG_AAC_0_XAAC_GM_OFFSET_Pos                                                         2U
+#define PCC_REG_AAC_0_XAAC_GM_OFFSET_Msk                                                         (0x3FUL << PCC_REG_AAC_0_XAAC_GM_OFFSET_Pos)
+
+#define PCC_REG_AAC_0_GM_STEP_Pos                                                                8U
+#define PCC_REG_AAC_0_GM_STEP_Msk                                                                (0x1UL << PCC_REG_AAC_0_GM_STEP_Pos)
+
+#define PCC_REG_AAC_0_GM_INIT_Pos                                                                9U
+#define PCC_REG_AAC_0_GM_INIT_Msk                                                                (0x3FUL << PCC_REG_AAC_0_GM_INIT_Pos)
+
+#define PCC_REG_AAC_0_XTAL_CLK_SET_Pos                                                           15U
+#define PCC_REG_AAC_0_XTAL_CLK_SET_Msk                                                           (0x7UL << PCC_REG_AAC_0_XTAL_CLK_SET_Pos)
+
+#define PCC_REG_AAC_0_GM_STUP_Pos                                                                18U
+#define PCC_REG_AAC_0_GM_STUP_Msk                                                                (0x3FUL << PCC_REG_AAC_0_GM_STUP_Pos)
+
+#define PCC_REG_AAC_0_GM_MANUAL_Pos                                                              24U
+#define PCC_REG_AAC_0_GM_MANUAL_Msk                                                              (0x3FUL << PCC_REG_AAC_0_GM_MANUAL_Pos)
+
+#define PCC_REG_AAC_0_R_EN_XTAL_AAC_DIGI_Pos                                                     30U
+#define PCC_REG_AAC_0_R_EN_XTAL_AAC_DIGI_Msk                                                     (0x1UL << PCC_REG_AAC_0_R_EN_XTAL_AAC_DIGI_Pos)
+
+#define PCC_REG_AAC_0_R_EN_XTAL_AAC_TRIG_Pos                                                     31U
+#define PCC_REG_AAC_0_R_EN_XTAL_AAC_TRIG_Msk                                                     (0x1UL << PCC_REG_AAC_0_R_EN_XTAL_AAC_TRIG_Pos)
+
+/* 0x354    0x4000_0354
+    0       R       XAAC_BUSY                                       0
+    1       R       XTAL_AAC_OK                                     0
+    7:2     R       XTAL_GM_OUT                                     6'h3F
+    11:8    R       XAAC_CURR_STATE                                 4'h0
+    12      R/W     XTAL_EN_DAAC_GM                                 0
+    13      R/W     XTAL_EN_AAC_PKDET                               0
+    14      R       XTAL_PKDET_OUT                                  0
+    15      R/W     DUMMY86                                         0
+    31:16   R/W     DUMMY85                                         16'h0129
+ */
+typedef union _PCC_REG_AAC_1_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t XAAC_BUSY: 1;
+        uint32_t XTAL_AAC_OK: 1;
+        uint32_t XTAL_GM_OUT: 6;
+        uint32_t XAAC_CURR_STATE: 4;
+        uint32_t XTAL_EN_DAAC_GM: 1;
+        uint32_t XTAL_EN_AAC_PKDET: 1;
+        uint32_t XTAL_PKDET_OUT: 1;
+        uint32_t DUMMY86: 1;
+        uint32_t DUMMY85: 16;
+    };
+} PCC_REG_AAC_1_TYPE;
+
+/*0x4000_0354 PCC_REG_AAC_1*/
+#define PCC_REG_AAC_1_XAAC_BUSY_Pos                                                              0U
+#define PCC_REG_AAC_1_XAAC_BUSY_Msk                                                              (0x1UL << PCC_REG_AAC_1_XAAC_BUSY_Pos)
+
+#define PCC_REG_AAC_1_XTAL_AAC_OK_Pos                                                            1U
+#define PCC_REG_AAC_1_XTAL_AAC_OK_Msk                                                            (0x1UL << PCC_REG_AAC_1_XTAL_AAC_OK_Pos)
+
+#define PCC_REG_AAC_1_XTAL_GM_OUT_Pos                                                            2U
+#define PCC_REG_AAC_1_XTAL_GM_OUT_Msk                                                            (0x3FUL << PCC_REG_AAC_1_XTAL_GM_OUT_Pos)
+
+#define PCC_REG_AAC_1_XAAC_CURR_STATE_Pos                                                        8U
+#define PCC_REG_AAC_1_XAAC_CURR_STATE_Msk                                                        (0xFUL << PCC_REG_AAC_1_XAAC_CURR_STATE_Pos)
+
+#define PCC_REG_AAC_1_XTAL_EN_DAAC_GM_Pos                                                        12U
+#define PCC_REG_AAC_1_XTAL_EN_DAAC_GM_Msk                                                        (0x1UL << PCC_REG_AAC_1_XTAL_EN_DAAC_GM_Pos)
+
+#define PCC_REG_AAC_1_XTAL_EN_AAC_PKDET_Pos                                                      13U
+#define PCC_REG_AAC_1_XTAL_EN_AAC_PKDET_Msk                                                      (0x1UL << PCC_REG_AAC_1_XTAL_EN_AAC_PKDET_Pos)
+
+#define PCC_REG_AAC_1_XTAL_PKDET_OUT_Pos                                                         14U
+#define PCC_REG_AAC_1_XTAL_PKDET_OUT_Msk                                                         (0x1UL << PCC_REG_AAC_1_XTAL_PKDET_OUT_Pos)
+
+#define PCC_REG_AAC_1_DUMMY86_Pos                                                                15U
+#define PCC_REG_AAC_1_DUMMY86_Msk                                                                (0x1UL << PCC_REG_AAC_1_DUMMY86_Pos)
+
+#define PCC_REG_AAC_1_DUMMY85_Pos                                                                16U
+#define PCC_REG_AAC_1_DUMMY85_Msk                                                                (0xFFFFUL << PCC_REG_AAC_1_DUMMY85_Pos)
+
+/* 0x358    0x4000_0358
+    0       R/W     DISABLE_PLL_PRE_GATING                          0
+    15:1    R/W     DUMMY88                                         15'h0
+    17:16   R/W     DUMMY87                                         2'h3
+    23:18   R       RSVD_1                                          6'h0
+    24      R       BT_PLL_READY                                    0
+    25      R       XTAL_OK                                         0
+    31:26   R       RSVD                                            6'h0
+ */
+typedef union _PCC_REG_XTAL_PLL_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t DISABLE_PLL_PRE_GATING: 1;
+        uint32_t DUMMY88: 15;
+        uint32_t DUMMY87: 2;
+        uint32_t RSVD_1: 6;
+        uint32_t BT_PLL_READY: 1;
+        uint32_t XTAL_OK: 1;
+        uint32_t RSVD: 6;
+    };
+} PCC_REG_XTAL_PLL_TYPE;
+
+/*0x4000_0358 PCC_REG_XTAL_PLL*/
+#define PCC_REG_XTAL_PLL_DISABLE_PLL_PRE_GATING_Pos                                              0U
+#define PCC_REG_XTAL_PLL_DISABLE_PLL_PRE_GATING_Msk                                              (0x1UL << PCC_REG_XTAL_PLL_DISABLE_PLL_PRE_GATING_Pos)
+
+#define PCC_REG_XTAL_PLL_DUMMY88_Pos                                                             1U
+#define PCC_REG_XTAL_PLL_DUMMY88_Msk                                                             (0x7FFFUL << PCC_REG_XTAL_PLL_DUMMY88_Pos)
+
+#define PCC_REG_XTAL_PLL_DUMMY87_Pos                                                             16U
+#define PCC_REG_XTAL_PLL_DUMMY87_Msk                                                             (0x3UL << PCC_REG_XTAL_PLL_DUMMY87_Pos)
+
+#define PCC_REG_XTAL_PLL_RSVD_1_Pos                                                              18U
+#define PCC_REG_XTAL_PLL_RSVD_1_Msk                                                              (0x3FUL << PCC_REG_XTAL_PLL_RSVD_1_Pos)
+
+#define PCC_REG_XTAL_PLL_BT_PLL_READY_Pos                                                        24U
+#define PCC_REG_XTAL_PLL_BT_PLL_READY_Msk                                                        (0x1UL << PCC_REG_XTAL_PLL_BT_PLL_READY_Pos)
+
+#define PCC_REG_XTAL_PLL_XTAL_OK_Pos                                                             25U
+#define PCC_REG_XTAL_PLL_XTAL_OK_Msk                                                             (0x1UL << PCC_REG_XTAL_PLL_XTAL_OK_Pos)
+
+#define PCC_REG_XTAL_PLL_RSVD_Pos                                                                26U
+#define PCC_REG_XTAL_PLL_RSVD_Msk                                                                (0x3FUL << PCC_REG_XTAL_PLL_RSVD_Pos)
+
+/* 0x35C    0x4000_035c
+    0       R/W     RESERVED_10                                     0
+    1       R/W     RESERVED_9                                      1
+    2       R/W     RESERVED_8                                      0
+    4:3     R/W     RESERVED_7                                      2'b01
+    9:5     R/W     RESERVED_6                                      5'b10000
+    14:10   R/W     RESERVED_5                                      5'b11111
+    16:15   R/W     RESERVED_4                                      2'b10
+    21:17   R/W     RESERVED_3                                      5'b00000
+    22      R/W     RESERVED_2                                      0
+    27:23   R/W     RESERVED_1                                      5'h0
+    31:28   R       RESERVED                                        4'h0
+ */
+typedef union _PCC_REG_XTALPDCK_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED_10: 1;
+        uint32_t RESERVED_9: 1;
+        uint32_t RESERVED_8: 1;
+        uint32_t RESERVED_7: 2;
+        uint32_t RESERVED_6: 5;
+        uint32_t RESERVED_5: 5;
+        uint32_t RESERVED_4: 2;
+        uint32_t RESERVED_3: 5;
+        uint32_t RESERVED_2: 1;
+        uint32_t RESERVED_1: 5;
+        uint32_t RESERVED: 4;
+    };
+} PCC_REG_XTALPDCK_TYPE;
+
+/*0x4000_035c PCC_REG_XTALPDCK*/
+#define PCC_REG_XTALPDCK_RESERVED_10_Pos                                                         0U
+#define PCC_REG_XTALPDCK_RESERVED_10_Msk                                                         (0x1UL << PCC_REG_XTALPDCK_RESERVED_10_Pos)
+
+#define PCC_REG_XTALPDCK_RESERVED_9_Pos                                                          1U
+#define PCC_REG_XTALPDCK_RESERVED_9_Msk                                                          (0x1UL << PCC_REG_XTALPDCK_RESERVED_9_Pos)
+
+#define PCC_REG_XTALPDCK_RESERVED_8_Pos                                                          2U
+#define PCC_REG_XTALPDCK_RESERVED_8_Msk                                                          (0x1UL << PCC_REG_XTALPDCK_RESERVED_8_Pos)
+
+#define PCC_REG_XTALPDCK_RESERVED_7_Pos                                                          3U
+#define PCC_REG_XTALPDCK_RESERVED_7_Msk                                                          (0x3UL << PCC_REG_XTALPDCK_RESERVED_7_Pos)
+
+#define PCC_REG_XTALPDCK_RESERVED_6_Pos                                                          5U
+#define PCC_REG_XTALPDCK_RESERVED_6_Msk                                                          (0x1FUL << PCC_REG_XTALPDCK_RESERVED_6_Pos)
+
+#define PCC_REG_XTALPDCK_RESERVED_5_Pos                                                          10U
+#define PCC_REG_XTALPDCK_RESERVED_5_Msk                                                          (0x1FUL << PCC_REG_XTALPDCK_RESERVED_5_Pos)
+
+#define PCC_REG_XTALPDCK_RESERVED_4_Pos                                                          15U
+#define PCC_REG_XTALPDCK_RESERVED_4_Msk                                                          (0x3UL << PCC_REG_XTALPDCK_RESERVED_4_Pos)
+
+#define PCC_REG_XTALPDCK_RESERVED_3_Pos                                                          17U
+#define PCC_REG_XTALPDCK_RESERVED_3_Msk                                                          (0x1FUL << PCC_REG_XTALPDCK_RESERVED_3_Pos)
+
+#define PCC_REG_XTALPDCK_RESERVED_2_Pos                                                          22U
+#define PCC_REG_XTALPDCK_RESERVED_2_Msk                                                          (0x1UL << PCC_REG_XTALPDCK_RESERVED_2_Pos)
+
+#define PCC_REG_XTALPDCK_RESERVED_1_Pos                                                          23U
+#define PCC_REG_XTALPDCK_RESERVED_1_Msk                                                          (0x1FUL << PCC_REG_XTALPDCK_RESERVED_1_Pos)
+
+#define PCC_REG_XTALPDCK_RESERVED_Pos                                                            28U
+#define PCC_REG_XTALPDCK_RESERVED_Msk                                                            (0xFUL << PCC_REG_XTALPDCK_RESERVED_Pos)
+
+/* 0x360    0x4000_0360
+    0       R/W     RESERVED_21                                     1'b0
+    1       R/W     RESERVED_20                                     1'b0
+    2       R/W     RESERVED_19                                     1'b0
+    3       R/W     RESERVED_18                                     1'b0
+    7:4     R/W     RESERVED_17                                     4'd0
+    8       R/W     RESERVED_16                                     1'b0
+    9       R/W     RESERVED_15                                     1'b0
+    10      R/W     RESERVED_14                                     1'b0
+    11      R/W     RESERVED_13                                     1'b0
+    14:12   R/W     RESERVED_12                                     3'd0
+    15      R/W     RESERVED_11                                     1'b0
+    16      R/W     RESERVED_10                                     1'b0
+    17      R/W     RESERVED_9                                      1'b0
+    18      R/W     RESERVED_8                                      1'b0
+    19      R/W     RESERVED_7                                      1'b0
+    23:20   R/W     RESERVED_6                                      4'd0
+    24      R/W     RESERVED_5                                      1'b0
+    25      R/W     RESERVED_4                                      1'b0
+    26      R/W     RESERVED_3                                      1'b0
+    27      R/W     RESERVED_2                                      1'b0
+    30:28   R/W     RESERVED_1                                      3'd0
+    31      R/W     RESERVED                                        1'b0
+ */
+typedef union _PCC_REG_PADMUX_AS_CFG0_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED_21: 1;
+        uint32_t RESERVED_20: 1;
+        uint32_t RESERVED_19: 1;
+        uint32_t RESERVED_18: 1;
+        uint32_t RESERVED_17: 4;
+        uint32_t RESERVED_16: 1;
+        uint32_t RESERVED_15: 1;
+        uint32_t RESERVED_14: 1;
+        uint32_t RESERVED_13: 1;
+        uint32_t RESERVED_12: 3;
+        uint32_t RESERVED_11: 1;
+        uint32_t RESERVED_10: 1;
+        uint32_t RESERVED_9: 1;
+        uint32_t RESERVED_8: 1;
+        uint32_t RESERVED_7: 1;
+        uint32_t RESERVED_6: 4;
+        uint32_t RESERVED_5: 1;
+        uint32_t RESERVED_4: 1;
+        uint32_t RESERVED_3: 1;
+        uint32_t RESERVED_2: 1;
+        uint32_t RESERVED_1: 3;
+        uint32_t RESERVED: 1;
+    };
+} PCC_REG_PADMUX_AS_CFG0_TYPE;
+
+/*0x4000_0360 PCC_REG_PADMUX_AS_CFG0*/
+#define PCC_REG_PADMUX_AS_CFG0_RESERVED_21_Pos                                                   0U
+#define PCC_REG_PADMUX_AS_CFG0_RESERVED_21_Msk                                                   (0x1UL << PCC_REG_PADMUX_AS_CFG0_RESERVED_21_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG0_RESERVED_20_Pos                                                   1U
+#define PCC_REG_PADMUX_AS_CFG0_RESERVED_20_Msk                                                   (0x1UL << PCC_REG_PADMUX_AS_CFG0_RESERVED_20_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG0_RESERVED_19_Pos                                                   2U
+#define PCC_REG_PADMUX_AS_CFG0_RESERVED_19_Msk                                                   (0x1UL << PCC_REG_PADMUX_AS_CFG0_RESERVED_19_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG0_RESERVED_18_Pos                                                   3U
+#define PCC_REG_PADMUX_AS_CFG0_RESERVED_18_Msk                                                   (0x1UL << PCC_REG_PADMUX_AS_CFG0_RESERVED_18_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG0_RESERVED_17_Pos                                                   4U
+#define PCC_REG_PADMUX_AS_CFG0_RESERVED_17_Msk                                                   (0xFUL << PCC_REG_PADMUX_AS_CFG0_RESERVED_17_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG0_RESERVED_16_Pos                                                   8U
+#define PCC_REG_PADMUX_AS_CFG0_RESERVED_16_Msk                                                   (0x1UL << PCC_REG_PADMUX_AS_CFG0_RESERVED_16_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG0_RESERVED_15_Pos                                                   9U
+#define PCC_REG_PADMUX_AS_CFG0_RESERVED_15_Msk                                                   (0x1UL << PCC_REG_PADMUX_AS_CFG0_RESERVED_15_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG0_RESERVED_14_Pos                                                   10U
+#define PCC_REG_PADMUX_AS_CFG0_RESERVED_14_Msk                                                   (0x1UL << PCC_REG_PADMUX_AS_CFG0_RESERVED_14_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG0_RESERVED_13_Pos                                                   11U
+#define PCC_REG_PADMUX_AS_CFG0_RESERVED_13_Msk                                                   (0x1UL << PCC_REG_PADMUX_AS_CFG0_RESERVED_13_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG0_RESERVED_12_Pos                                                   12U
+#define PCC_REG_PADMUX_AS_CFG0_RESERVED_12_Msk                                                   (0x7UL << PCC_REG_PADMUX_AS_CFG0_RESERVED_12_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG0_RESERVED_11_Pos                                                   15U
+#define PCC_REG_PADMUX_AS_CFG0_RESERVED_11_Msk                                                   (0x1UL << PCC_REG_PADMUX_AS_CFG0_RESERVED_11_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG0_RESERVED_10_Pos                                                   16U
+#define PCC_REG_PADMUX_AS_CFG0_RESERVED_10_Msk                                                   (0x1UL << PCC_REG_PADMUX_AS_CFG0_RESERVED_10_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG0_RESERVED_9_Pos                                                    17U
+#define PCC_REG_PADMUX_AS_CFG0_RESERVED_9_Msk                                                    (0x1UL << PCC_REG_PADMUX_AS_CFG0_RESERVED_9_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG0_RESERVED_8_Pos                                                    18U
+#define PCC_REG_PADMUX_AS_CFG0_RESERVED_8_Msk                                                    (0x1UL << PCC_REG_PADMUX_AS_CFG0_RESERVED_8_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG0_RESERVED_7_Pos                                                    19U
+#define PCC_REG_PADMUX_AS_CFG0_RESERVED_7_Msk                                                    (0x1UL << PCC_REG_PADMUX_AS_CFG0_RESERVED_7_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG0_RESERVED_6_Pos                                                    20U
+#define PCC_REG_PADMUX_AS_CFG0_RESERVED_6_Msk                                                    (0xFUL << PCC_REG_PADMUX_AS_CFG0_RESERVED_6_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG0_RESERVED_5_Pos                                                    24U
+#define PCC_REG_PADMUX_AS_CFG0_RESERVED_5_Msk                                                    (0x1UL << PCC_REG_PADMUX_AS_CFG0_RESERVED_5_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG0_RESERVED_4_Pos                                                    25U
+#define PCC_REG_PADMUX_AS_CFG0_RESERVED_4_Msk                                                    (0x1UL << PCC_REG_PADMUX_AS_CFG0_RESERVED_4_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG0_RESERVED_3_Pos                                                    26U
+#define PCC_REG_PADMUX_AS_CFG0_RESERVED_3_Msk                                                    (0x1UL << PCC_REG_PADMUX_AS_CFG0_RESERVED_3_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG0_RESERVED_2_Pos                                                    27U
+#define PCC_REG_PADMUX_AS_CFG0_RESERVED_2_Msk                                                    (0x1UL << PCC_REG_PADMUX_AS_CFG0_RESERVED_2_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG0_RESERVED_1_Pos                                                    28U
+#define PCC_REG_PADMUX_AS_CFG0_RESERVED_1_Msk                                                    (0x7UL << PCC_REG_PADMUX_AS_CFG0_RESERVED_1_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG0_RESERVED_Pos                                                      31U
+#define PCC_REG_PADMUX_AS_CFG0_RESERVED_Msk                                                      (0x1UL << PCC_REG_PADMUX_AS_CFG0_RESERVED_Pos)
+
+/* 0x364    0x4000_0364
+    0       R/W     RESERVED_11                                     1'b0
+    1       R/W     RESERVED_10                                     1'b0
+    2       R/W     RESERVED_9                                      1'b0
+    3       R/W     RESERVED_8                                      1'b0
+    7:4     R/W     RESERVED_7                                      4'd0
+    8       R/W     RESERVED_6                                      1'b0
+    9       R/W     RESERVED_5                                      1'b0
+    10      R/W     RESERVED_4                                      1'b0
+    11      R/W     RESERVED_3                                      1'b0
+    14:12   R/W     RESERVED_2                                      3'd0
+    15      R/W     RESERVED_1                                      1'b0
+    31:16   R/W     RESERVED                                        16'd0
+ */
+typedef union _PCC_REG_PADMUX_AS_CFG1_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED_11: 1;
+        uint32_t RESERVED_10: 1;
+        uint32_t RESERVED_9: 1;
+        uint32_t RESERVED_8: 1;
+        uint32_t RESERVED_7: 4;
+        uint32_t RESERVED_6: 1;
+        uint32_t RESERVED_5: 1;
+        uint32_t RESERVED_4: 1;
+        uint32_t RESERVED_3: 1;
+        uint32_t RESERVED_2: 3;
+        uint32_t RESERVED_1: 1;
+        uint32_t RESERVED: 16;
+    };
+} PCC_REG_PADMUX_AS_CFG1_TYPE;
+
+/*0x4000_0364 PCC_REG_PADMUX_AS_CFG1*/
+#define PCC_REG_PADMUX_AS_CFG1_RESERVED_11_Pos                                                   0U
+#define PCC_REG_PADMUX_AS_CFG1_RESERVED_11_Msk                                                   (0x1UL << PCC_REG_PADMUX_AS_CFG1_RESERVED_11_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG1_RESERVED_10_Pos                                                   1U
+#define PCC_REG_PADMUX_AS_CFG1_RESERVED_10_Msk                                                   (0x1UL << PCC_REG_PADMUX_AS_CFG1_RESERVED_10_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG1_RESERVED_9_Pos                                                    2U
+#define PCC_REG_PADMUX_AS_CFG1_RESERVED_9_Msk                                                    (0x1UL << PCC_REG_PADMUX_AS_CFG1_RESERVED_9_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG1_RESERVED_8_Pos                                                    3U
+#define PCC_REG_PADMUX_AS_CFG1_RESERVED_8_Msk                                                    (0x1UL << PCC_REG_PADMUX_AS_CFG1_RESERVED_8_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG1_RESERVED_7_Pos                                                    4U
+#define PCC_REG_PADMUX_AS_CFG1_RESERVED_7_Msk                                                    (0xFUL << PCC_REG_PADMUX_AS_CFG1_RESERVED_7_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG1_RESERVED_6_Pos                                                    8U
+#define PCC_REG_PADMUX_AS_CFG1_RESERVED_6_Msk                                                    (0x1UL << PCC_REG_PADMUX_AS_CFG1_RESERVED_6_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG1_RESERVED_5_Pos                                                    9U
+#define PCC_REG_PADMUX_AS_CFG1_RESERVED_5_Msk                                                    (0x1UL << PCC_REG_PADMUX_AS_CFG1_RESERVED_5_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG1_RESERVED_4_Pos                                                    10U
+#define PCC_REG_PADMUX_AS_CFG1_RESERVED_4_Msk                                                    (0x1UL << PCC_REG_PADMUX_AS_CFG1_RESERVED_4_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG1_RESERVED_3_Pos                                                    11U
+#define PCC_REG_PADMUX_AS_CFG1_RESERVED_3_Msk                                                    (0x1UL << PCC_REG_PADMUX_AS_CFG1_RESERVED_3_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG1_RESERVED_2_Pos                                                    12U
+#define PCC_REG_PADMUX_AS_CFG1_RESERVED_2_Msk                                                    (0x7UL << PCC_REG_PADMUX_AS_CFG1_RESERVED_2_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG1_RESERVED_1_Pos                                                    15U
+#define PCC_REG_PADMUX_AS_CFG1_RESERVED_1_Msk                                                    (0x1UL << PCC_REG_PADMUX_AS_CFG1_RESERVED_1_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG1_RESERVED_Pos                                                      16U
+#define PCC_REG_PADMUX_AS_CFG1_RESERVED_Msk                                                      (0xFFFFUL << PCC_REG_PADMUX_AS_CFG1_RESERVED_Pos)
+
+/* 0x368    0x4000_0368
+    0       R/W     RESERVED_21                                     1'b0
+    1       R/W     RESERVED_20                                     1'b0
+    2       R/W     RESERVED_19                                     1'b0
+    3       R/W     RESERVED_18                                     1'b0
+    7:4     R/W     RESERVED_17                                     4'd0
+    8       R/W     RESERVED_16                                     1'b0
+    9       R/W     RESERVED_15                                     1'b0
+    10      R/W     RESERVED_14                                     1'b0
+    11      R/W     RESERVED_13                                     1'b0
+    14:12   R/W     RESERVED_12                                     3'd0
+    15      R/W     RESERVED_11                                     1'b0
+    16      R/W     RESERVED_10                                     1'b0
+    17      R/W     RESERVED_9                                      1'b0
+    18      R/W     RESERVED_8                                      1'b0
+    19      R/W     RESERVED_7                                      1'b0
+    23:20   R/W     RESERVED_6                                      4'd0
+    24      R/W     RESERVED_5                                      1'b0
+    25      R/W     RESERVED_4                                      1'b0
+    26      R/W     RESERVED_3                                      1'b0
+    27      R/W     RESERVED_2                                      1'b0
+    30:28   R/W     RESERVED_1                                      3'd0
+    31      R/W     RESERVED                                        1'b0
+ */
+typedef union _PCC_REG_PADMUX_AS_CFG2_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED_21: 1;
+        uint32_t RESERVED_20: 1;
+        uint32_t RESERVED_19: 1;
+        uint32_t RESERVED_18: 1;
+        uint32_t RESERVED_17: 4;
+        uint32_t RESERVED_16: 1;
+        uint32_t RESERVED_15: 1;
+        uint32_t RESERVED_14: 1;
+        uint32_t RESERVED_13: 1;
+        uint32_t RESERVED_12: 3;
+        uint32_t RESERVED_11: 1;
+        uint32_t RESERVED_10: 1;
+        uint32_t RESERVED_9: 1;
+        uint32_t RESERVED_8: 1;
+        uint32_t RESERVED_7: 1;
+        uint32_t RESERVED_6: 4;
+        uint32_t RESERVED_5: 1;
+        uint32_t RESERVED_4: 1;
+        uint32_t RESERVED_3: 1;
+        uint32_t RESERVED_2: 1;
+        uint32_t RESERVED_1: 3;
+        uint32_t RESERVED: 1;
+    };
+} PCC_REG_PADMUX_AS_CFG2_TYPE;
+
+/*0x4000_0368 PCC_REG_PADMUX_AS_CFG2*/
+#define PCC_REG_PADMUX_AS_CFG2_RESERVED_21_Pos                                                   0U
+#define PCC_REG_PADMUX_AS_CFG2_RESERVED_21_Msk                                                   (0x1UL << PCC_REG_PADMUX_AS_CFG2_RESERVED_21_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG2_RESERVED_20_Pos                                                   1U
+#define PCC_REG_PADMUX_AS_CFG2_RESERVED_20_Msk                                                   (0x1UL << PCC_REG_PADMUX_AS_CFG2_RESERVED_20_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG2_RESERVED_19_Pos                                                   2U
+#define PCC_REG_PADMUX_AS_CFG2_RESERVED_19_Msk                                                   (0x1UL << PCC_REG_PADMUX_AS_CFG2_RESERVED_19_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG2_RESERVED_18_Pos                                                   3U
+#define PCC_REG_PADMUX_AS_CFG2_RESERVED_18_Msk                                                   (0x1UL << PCC_REG_PADMUX_AS_CFG2_RESERVED_18_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG2_RESERVED_17_Pos                                                   4U
+#define PCC_REG_PADMUX_AS_CFG2_RESERVED_17_Msk                                                   (0xFUL << PCC_REG_PADMUX_AS_CFG2_RESERVED_17_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG2_RESERVED_16_Pos                                                   8U
+#define PCC_REG_PADMUX_AS_CFG2_RESERVED_16_Msk                                                   (0x1UL << PCC_REG_PADMUX_AS_CFG2_RESERVED_16_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG2_RESERVED_15_Pos                                                   9U
+#define PCC_REG_PADMUX_AS_CFG2_RESERVED_15_Msk                                                   (0x1UL << PCC_REG_PADMUX_AS_CFG2_RESERVED_15_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG2_RESERVED_14_Pos                                                   10U
+#define PCC_REG_PADMUX_AS_CFG2_RESERVED_14_Msk                                                   (0x1UL << PCC_REG_PADMUX_AS_CFG2_RESERVED_14_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG2_RESERVED_13_Pos                                                   11U
+#define PCC_REG_PADMUX_AS_CFG2_RESERVED_13_Msk                                                   (0x1UL << PCC_REG_PADMUX_AS_CFG2_RESERVED_13_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG2_RESERVED_12_Pos                                                   12U
+#define PCC_REG_PADMUX_AS_CFG2_RESERVED_12_Msk                                                   (0x7UL << PCC_REG_PADMUX_AS_CFG2_RESERVED_12_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG2_RESERVED_11_Pos                                                   15U
+#define PCC_REG_PADMUX_AS_CFG2_RESERVED_11_Msk                                                   (0x1UL << PCC_REG_PADMUX_AS_CFG2_RESERVED_11_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG2_RESERVED_10_Pos                                                   16U
+#define PCC_REG_PADMUX_AS_CFG2_RESERVED_10_Msk                                                   (0x1UL << PCC_REG_PADMUX_AS_CFG2_RESERVED_10_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG2_RESERVED_9_Pos                                                    17U
+#define PCC_REG_PADMUX_AS_CFG2_RESERVED_9_Msk                                                    (0x1UL << PCC_REG_PADMUX_AS_CFG2_RESERVED_9_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG2_RESERVED_8_Pos                                                    18U
+#define PCC_REG_PADMUX_AS_CFG2_RESERVED_8_Msk                                                    (0x1UL << PCC_REG_PADMUX_AS_CFG2_RESERVED_8_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG2_RESERVED_7_Pos                                                    19U
+#define PCC_REG_PADMUX_AS_CFG2_RESERVED_7_Msk                                                    (0x1UL << PCC_REG_PADMUX_AS_CFG2_RESERVED_7_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG2_RESERVED_6_Pos                                                    20U
+#define PCC_REG_PADMUX_AS_CFG2_RESERVED_6_Msk                                                    (0xFUL << PCC_REG_PADMUX_AS_CFG2_RESERVED_6_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG2_RESERVED_5_Pos                                                    24U
+#define PCC_REG_PADMUX_AS_CFG2_RESERVED_5_Msk                                                    (0x1UL << PCC_REG_PADMUX_AS_CFG2_RESERVED_5_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG2_RESERVED_4_Pos                                                    25U
+#define PCC_REG_PADMUX_AS_CFG2_RESERVED_4_Msk                                                    (0x1UL << PCC_REG_PADMUX_AS_CFG2_RESERVED_4_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG2_RESERVED_3_Pos                                                    26U
+#define PCC_REG_PADMUX_AS_CFG2_RESERVED_3_Msk                                                    (0x1UL << PCC_REG_PADMUX_AS_CFG2_RESERVED_3_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG2_RESERVED_2_Pos                                                    27U
+#define PCC_REG_PADMUX_AS_CFG2_RESERVED_2_Msk                                                    (0x1UL << PCC_REG_PADMUX_AS_CFG2_RESERVED_2_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG2_RESERVED_1_Pos                                                    28U
+#define PCC_REG_PADMUX_AS_CFG2_RESERVED_1_Msk                                                    (0x7UL << PCC_REG_PADMUX_AS_CFG2_RESERVED_1_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG2_RESERVED_Pos                                                      31U
+#define PCC_REG_PADMUX_AS_CFG2_RESERVED_Msk                                                      (0x1UL << PCC_REG_PADMUX_AS_CFG2_RESERVED_Pos)
+
+/* 0x36C    0x4000_036c
+    0       R/W     RESERVED_11                                     1'b0
+    1       R/W     RESERVED_10                                     1'b0
+    2       R/W     RESERVED_9                                      1'b0
+    3       R/W     RESERVED_8                                      1'b0
+    7:4     R/W     RESERVED_7                                      4'd0
+    8       R/W     RESERVED_6                                      1'b0
+    9       R/W     RESERVED_5                                      1'b0
+    10      R/W     RESERVED_4                                      1'b0
+    11      R/W     RESERVED_3                                      1'b0
+    14:12   R/W     RESERVED_2                                      3'd0
+    15      R/W     RESERVED_1                                      1'b0
+    31:16   R/W     RESERVED                                        16'd0
+ */
+typedef union _PCC_REG_PADMUX_AS_CFG3_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED_11: 1;
+        uint32_t RESERVED_10: 1;
+        uint32_t RESERVED_9: 1;
+        uint32_t RESERVED_8: 1;
+        uint32_t RESERVED_7: 4;
+        uint32_t RESERVED_6: 1;
+        uint32_t RESERVED_5: 1;
+        uint32_t RESERVED_4: 1;
+        uint32_t RESERVED_3: 1;
+        uint32_t RESERVED_2: 3;
+        uint32_t RESERVED_1: 1;
+        uint32_t RESERVED: 16;
+    };
+} PCC_REG_PADMUX_AS_CFG3_TYPE;
+
+/*0x4000_036c PCC_REG_PADMUX_AS_CFG3*/
+#define PCC_REG_PADMUX_AS_CFG3_RESERVED_11_Pos                                                   0U
+#define PCC_REG_PADMUX_AS_CFG3_RESERVED_11_Msk                                                   (0x1UL << PCC_REG_PADMUX_AS_CFG3_RESERVED_11_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG3_RESERVED_10_Pos                                                   1U
+#define PCC_REG_PADMUX_AS_CFG3_RESERVED_10_Msk                                                   (0x1UL << PCC_REG_PADMUX_AS_CFG3_RESERVED_10_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG3_RESERVED_9_Pos                                                    2U
+#define PCC_REG_PADMUX_AS_CFG3_RESERVED_9_Msk                                                    (0x1UL << PCC_REG_PADMUX_AS_CFG3_RESERVED_9_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG3_RESERVED_8_Pos                                                    3U
+#define PCC_REG_PADMUX_AS_CFG3_RESERVED_8_Msk                                                    (0x1UL << PCC_REG_PADMUX_AS_CFG3_RESERVED_8_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG3_RESERVED_7_Pos                                                    4U
+#define PCC_REG_PADMUX_AS_CFG3_RESERVED_7_Msk                                                    (0xFUL << PCC_REG_PADMUX_AS_CFG3_RESERVED_7_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG3_RESERVED_6_Pos                                                    8U
+#define PCC_REG_PADMUX_AS_CFG3_RESERVED_6_Msk                                                    (0x1UL << PCC_REG_PADMUX_AS_CFG3_RESERVED_6_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG3_RESERVED_5_Pos                                                    9U
+#define PCC_REG_PADMUX_AS_CFG3_RESERVED_5_Msk                                                    (0x1UL << PCC_REG_PADMUX_AS_CFG3_RESERVED_5_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG3_RESERVED_4_Pos                                                    10U
+#define PCC_REG_PADMUX_AS_CFG3_RESERVED_4_Msk                                                    (0x1UL << PCC_REG_PADMUX_AS_CFG3_RESERVED_4_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG3_RESERVED_3_Pos                                                    11U
+#define PCC_REG_PADMUX_AS_CFG3_RESERVED_3_Msk                                                    (0x1UL << PCC_REG_PADMUX_AS_CFG3_RESERVED_3_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG3_RESERVED_2_Pos                                                    12U
+#define PCC_REG_PADMUX_AS_CFG3_RESERVED_2_Msk                                                    (0x7UL << PCC_REG_PADMUX_AS_CFG3_RESERVED_2_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG3_RESERVED_1_Pos                                                    15U
+#define PCC_REG_PADMUX_AS_CFG3_RESERVED_1_Msk                                                    (0x1UL << PCC_REG_PADMUX_AS_CFG3_RESERVED_1_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG3_RESERVED_Pos                                                      16U
+#define PCC_REG_PADMUX_AS_CFG3_RESERVED_Msk                                                      (0xFFFFUL << PCC_REG_PADMUX_AS_CFG3_RESERVED_Pos)
+
+/* 0x370    0x4000_0370
+    0       R/W     RESERVED_21                                     1'b0
+    1       R/W     RESERVED_20                                     1'b0
+    2       R/W     RESERVED_19                                     1'b0
+    3       R/W     RESERVED_18                                     1'b0
+    7:4     R/W     RESERVED_17                                     4'd0
+    8       R/W     RESERVED_16                                     1'b0
+    9       R/W     RESERVED_15                                     1'b0
+    10      R/W     RESERVED_14                                     1'b0
+    11      R/W     RESERVED_13                                     1'b0
+    14:12   R/W     RESERVED_12                                     3'd0
+    15      R/W     RESERVED_11                                     1'b0
+    16      R/W     RESERVED_10                                     1'b0
+    17      R/W     RESERVED_9                                      1'b0
+    18      R/W     RESERVED_8                                      1'b0
+    19      R/W     RESERVED_7                                      1'b0
+    23:20   R/W     RESERVED_6                                      4'd0
+    24      R/W     RESERVED_5                                      1'b0
+    25      R/W     RESERVED_4                                      1'b0
+    26      R/W     RESERVED_3                                      1'b0
+    27      R/W     RESERVED_2                                      1'b0
+    30:28   R/W     RESERVED_1                                      3'd0
+    31      R/W     RESERVED                                        1'b0
+ */
+typedef union _PCC_REG_PADMUX_AS_CFG4_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED_21: 1;
+        uint32_t RESERVED_20: 1;
+        uint32_t RESERVED_19: 1;
+        uint32_t RESERVED_18: 1;
+        uint32_t RESERVED_17: 4;
+        uint32_t RESERVED_16: 1;
+        uint32_t RESERVED_15: 1;
+        uint32_t RESERVED_14: 1;
+        uint32_t RESERVED_13: 1;
+        uint32_t RESERVED_12: 3;
+        uint32_t RESERVED_11: 1;
+        uint32_t RESERVED_10: 1;
+        uint32_t RESERVED_9: 1;
+        uint32_t RESERVED_8: 1;
+        uint32_t RESERVED_7: 1;
+        uint32_t RESERVED_6: 4;
+        uint32_t RESERVED_5: 1;
+        uint32_t RESERVED_4: 1;
+        uint32_t RESERVED_3: 1;
+        uint32_t RESERVED_2: 1;
+        uint32_t RESERVED_1: 3;
+        uint32_t RESERVED: 1;
+    };
+} PCC_REG_PADMUX_AS_CFG4_TYPE;
+
+/*0x4000_0370 PCC_REG_PADMUX_AS_CFG4*/
+#define PCC_REG_PADMUX_AS_CFG4_RESERVED_21_Pos                                                   0U
+#define PCC_REG_PADMUX_AS_CFG4_RESERVED_21_Msk                                                   (0x1UL << PCC_REG_PADMUX_AS_CFG4_RESERVED_21_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG4_RESERVED_20_Pos                                                   1U
+#define PCC_REG_PADMUX_AS_CFG4_RESERVED_20_Msk                                                   (0x1UL << PCC_REG_PADMUX_AS_CFG4_RESERVED_20_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG4_RESERVED_19_Pos                                                   2U
+#define PCC_REG_PADMUX_AS_CFG4_RESERVED_19_Msk                                                   (0x1UL << PCC_REG_PADMUX_AS_CFG4_RESERVED_19_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG4_RESERVED_18_Pos                                                   3U
+#define PCC_REG_PADMUX_AS_CFG4_RESERVED_18_Msk                                                   (0x1UL << PCC_REG_PADMUX_AS_CFG4_RESERVED_18_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG4_RESERVED_17_Pos                                                   4U
+#define PCC_REG_PADMUX_AS_CFG4_RESERVED_17_Msk                                                   (0xFUL << PCC_REG_PADMUX_AS_CFG4_RESERVED_17_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG4_RESERVED_16_Pos                                                   8U
+#define PCC_REG_PADMUX_AS_CFG4_RESERVED_16_Msk                                                   (0x1UL << PCC_REG_PADMUX_AS_CFG4_RESERVED_16_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG4_RESERVED_15_Pos                                                   9U
+#define PCC_REG_PADMUX_AS_CFG4_RESERVED_15_Msk                                                   (0x1UL << PCC_REG_PADMUX_AS_CFG4_RESERVED_15_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG4_RESERVED_14_Pos                                                   10U
+#define PCC_REG_PADMUX_AS_CFG4_RESERVED_14_Msk                                                   (0x1UL << PCC_REG_PADMUX_AS_CFG4_RESERVED_14_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG4_RESERVED_13_Pos                                                   11U
+#define PCC_REG_PADMUX_AS_CFG4_RESERVED_13_Msk                                                   (0x1UL << PCC_REG_PADMUX_AS_CFG4_RESERVED_13_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG4_RESERVED_12_Pos                                                   12U
+#define PCC_REG_PADMUX_AS_CFG4_RESERVED_12_Msk                                                   (0x7UL << PCC_REG_PADMUX_AS_CFG4_RESERVED_12_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG4_RESERVED_11_Pos                                                   15U
+#define PCC_REG_PADMUX_AS_CFG4_RESERVED_11_Msk                                                   (0x1UL << PCC_REG_PADMUX_AS_CFG4_RESERVED_11_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG4_RESERVED_10_Pos                                                   16U
+#define PCC_REG_PADMUX_AS_CFG4_RESERVED_10_Msk                                                   (0x1UL << PCC_REG_PADMUX_AS_CFG4_RESERVED_10_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG4_RESERVED_9_Pos                                                    17U
+#define PCC_REG_PADMUX_AS_CFG4_RESERVED_9_Msk                                                    (0x1UL << PCC_REG_PADMUX_AS_CFG4_RESERVED_9_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG4_RESERVED_8_Pos                                                    18U
+#define PCC_REG_PADMUX_AS_CFG4_RESERVED_8_Msk                                                    (0x1UL << PCC_REG_PADMUX_AS_CFG4_RESERVED_8_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG4_RESERVED_7_Pos                                                    19U
+#define PCC_REG_PADMUX_AS_CFG4_RESERVED_7_Msk                                                    (0x1UL << PCC_REG_PADMUX_AS_CFG4_RESERVED_7_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG4_RESERVED_6_Pos                                                    20U
+#define PCC_REG_PADMUX_AS_CFG4_RESERVED_6_Msk                                                    (0xFUL << PCC_REG_PADMUX_AS_CFG4_RESERVED_6_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG4_RESERVED_5_Pos                                                    24U
+#define PCC_REG_PADMUX_AS_CFG4_RESERVED_5_Msk                                                    (0x1UL << PCC_REG_PADMUX_AS_CFG4_RESERVED_5_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG4_RESERVED_4_Pos                                                    25U
+#define PCC_REG_PADMUX_AS_CFG4_RESERVED_4_Msk                                                    (0x1UL << PCC_REG_PADMUX_AS_CFG4_RESERVED_4_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG4_RESERVED_3_Pos                                                    26U
+#define PCC_REG_PADMUX_AS_CFG4_RESERVED_3_Msk                                                    (0x1UL << PCC_REG_PADMUX_AS_CFG4_RESERVED_3_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG4_RESERVED_2_Pos                                                    27U
+#define PCC_REG_PADMUX_AS_CFG4_RESERVED_2_Msk                                                    (0x1UL << PCC_REG_PADMUX_AS_CFG4_RESERVED_2_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG4_RESERVED_1_Pos                                                    28U
+#define PCC_REG_PADMUX_AS_CFG4_RESERVED_1_Msk                                                    (0x7UL << PCC_REG_PADMUX_AS_CFG4_RESERVED_1_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG4_RESERVED_Pos                                                      31U
+#define PCC_REG_PADMUX_AS_CFG4_RESERVED_Msk                                                      (0x1UL << PCC_REG_PADMUX_AS_CFG4_RESERVED_Pos)
+
+/* 0x374    0x4000_0374
+    0       R/W     RESERVED_21                                     1'b0
+    1       R/W     RESERVED_20                                     1'b0
+    2       R/W     RESERVED_19                                     1'b0
+    3       R/W     RESERVED_18                                     1'b0
+    7:4     R/W     RESERVED_17                                     4'd0
+    8       R/W     RESERVED_16                                     1'b0
+    9       R/W     RESERVED_15                                     1'b0
+    10      R/W     RESERVED_14                                     1'b0
+    11      R/W     RESERVED_13                                     1'b0
+    14:12   R/W     RESERVED_12                                     3'd0
+    15      R/W     RESERVED_11                                     1'b0
+    16      R/W     RESERVED_10                                     1'b0
+    17      R/W     RESERVED_9                                      1'b0
+    18      R/W     RESERVED_8                                      1'b0
+    19      R/W     RESERVED_7                                      1'b0
+    23:20   R/W     RESERVED_6                                      4'd0
+    24      R/W     RESERVED_5                                      1'b0
+    25      R/W     RESERVED_4                                      1'b0
+    26      R/W     RESERVED_3                                      1'b0
+    27      R/W     RESERVED_2                                      1'b0
+    30:28   R/W     RESERVED_1                                      3'd0
+    31      R/W     RESERVED                                        1'b0
+ */
+typedef union _PCC_REG_PADMUX_AS_CFG5_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED_21: 1;
+        uint32_t RESERVED_20: 1;
+        uint32_t RESERVED_19: 1;
+        uint32_t RESERVED_18: 1;
+        uint32_t RESERVED_17: 4;
+        uint32_t RESERVED_16: 1;
+        uint32_t RESERVED_15: 1;
+        uint32_t RESERVED_14: 1;
+        uint32_t RESERVED_13: 1;
+        uint32_t RESERVED_12: 3;
+        uint32_t RESERVED_11: 1;
+        uint32_t RESERVED_10: 1;
+        uint32_t RESERVED_9: 1;
+        uint32_t RESERVED_8: 1;
+        uint32_t RESERVED_7: 1;
+        uint32_t RESERVED_6: 4;
+        uint32_t RESERVED_5: 1;
+        uint32_t RESERVED_4: 1;
+        uint32_t RESERVED_3: 1;
+        uint32_t RESERVED_2: 1;
+        uint32_t RESERVED_1: 3;
+        uint32_t RESERVED: 1;
+    };
+} PCC_REG_PADMUX_AS_CFG5_TYPE;
+
+/*0x4000_0374 PCC_REG_PADMUX_AS_CFG5*/
+#define PCC_REG_PADMUX_AS_CFG5_RESERVED_21_Pos                                                   0U
+#define PCC_REG_PADMUX_AS_CFG5_RESERVED_21_Msk                                                   (0x1UL << PCC_REG_PADMUX_AS_CFG5_RESERVED_21_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG5_RESERVED_20_Pos                                                   1U
+#define PCC_REG_PADMUX_AS_CFG5_RESERVED_20_Msk                                                   (0x1UL << PCC_REG_PADMUX_AS_CFG5_RESERVED_20_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG5_RESERVED_19_Pos                                                   2U
+#define PCC_REG_PADMUX_AS_CFG5_RESERVED_19_Msk                                                   (0x1UL << PCC_REG_PADMUX_AS_CFG5_RESERVED_19_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG5_RESERVED_18_Pos                                                   3U
+#define PCC_REG_PADMUX_AS_CFG5_RESERVED_18_Msk                                                   (0x1UL << PCC_REG_PADMUX_AS_CFG5_RESERVED_18_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG5_RESERVED_17_Pos                                                   4U
+#define PCC_REG_PADMUX_AS_CFG5_RESERVED_17_Msk                                                   (0xFUL << PCC_REG_PADMUX_AS_CFG5_RESERVED_17_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG5_RESERVED_16_Pos                                                   8U
+#define PCC_REG_PADMUX_AS_CFG5_RESERVED_16_Msk                                                   (0x1UL << PCC_REG_PADMUX_AS_CFG5_RESERVED_16_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG5_RESERVED_15_Pos                                                   9U
+#define PCC_REG_PADMUX_AS_CFG5_RESERVED_15_Msk                                                   (0x1UL << PCC_REG_PADMUX_AS_CFG5_RESERVED_15_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG5_RESERVED_14_Pos                                                   10U
+#define PCC_REG_PADMUX_AS_CFG5_RESERVED_14_Msk                                                   (0x1UL << PCC_REG_PADMUX_AS_CFG5_RESERVED_14_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG5_RESERVED_13_Pos                                                   11U
+#define PCC_REG_PADMUX_AS_CFG5_RESERVED_13_Msk                                                   (0x1UL << PCC_REG_PADMUX_AS_CFG5_RESERVED_13_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG5_RESERVED_12_Pos                                                   12U
+#define PCC_REG_PADMUX_AS_CFG5_RESERVED_12_Msk                                                   (0x7UL << PCC_REG_PADMUX_AS_CFG5_RESERVED_12_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG5_RESERVED_11_Pos                                                   15U
+#define PCC_REG_PADMUX_AS_CFG5_RESERVED_11_Msk                                                   (0x1UL << PCC_REG_PADMUX_AS_CFG5_RESERVED_11_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG5_RESERVED_10_Pos                                                   16U
+#define PCC_REG_PADMUX_AS_CFG5_RESERVED_10_Msk                                                   (0x1UL << PCC_REG_PADMUX_AS_CFG5_RESERVED_10_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG5_RESERVED_9_Pos                                                    17U
+#define PCC_REG_PADMUX_AS_CFG5_RESERVED_9_Msk                                                    (0x1UL << PCC_REG_PADMUX_AS_CFG5_RESERVED_9_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG5_RESERVED_8_Pos                                                    18U
+#define PCC_REG_PADMUX_AS_CFG5_RESERVED_8_Msk                                                    (0x1UL << PCC_REG_PADMUX_AS_CFG5_RESERVED_8_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG5_RESERVED_7_Pos                                                    19U
+#define PCC_REG_PADMUX_AS_CFG5_RESERVED_7_Msk                                                    (0x1UL << PCC_REG_PADMUX_AS_CFG5_RESERVED_7_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG5_RESERVED_6_Pos                                                    20U
+#define PCC_REG_PADMUX_AS_CFG5_RESERVED_6_Msk                                                    (0xFUL << PCC_REG_PADMUX_AS_CFG5_RESERVED_6_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG5_RESERVED_5_Pos                                                    24U
+#define PCC_REG_PADMUX_AS_CFG5_RESERVED_5_Msk                                                    (0x1UL << PCC_REG_PADMUX_AS_CFG5_RESERVED_5_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG5_RESERVED_4_Pos                                                    25U
+#define PCC_REG_PADMUX_AS_CFG5_RESERVED_4_Msk                                                    (0x1UL << PCC_REG_PADMUX_AS_CFG5_RESERVED_4_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG5_RESERVED_3_Pos                                                    26U
+#define PCC_REG_PADMUX_AS_CFG5_RESERVED_3_Msk                                                    (0x1UL << PCC_REG_PADMUX_AS_CFG5_RESERVED_3_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG5_RESERVED_2_Pos                                                    27U
+#define PCC_REG_PADMUX_AS_CFG5_RESERVED_2_Msk                                                    (0x1UL << PCC_REG_PADMUX_AS_CFG5_RESERVED_2_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG5_RESERVED_1_Pos                                                    28U
+#define PCC_REG_PADMUX_AS_CFG5_RESERVED_1_Msk                                                    (0x7UL << PCC_REG_PADMUX_AS_CFG5_RESERVED_1_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG5_RESERVED_Pos                                                      31U
+#define PCC_REG_PADMUX_AS_CFG5_RESERVED_Msk                                                      (0x1UL << PCC_REG_PADMUX_AS_CFG5_RESERVED_Pos)
+
+/* 0x378    0x4000_0378
+    0       R/W     RESERVED_21                                     1'b0
+    1       R/W     RESERVED_20                                     1'b0
+    2       R/W     RESERVED_19                                     1'b0
+    3       R/W     RESERVED_18                                     1'b0
+    7:4     R/W     RESERVED_17                                     4'd0
+    8       R/W     RESERVED_16                                     1'b0
+    9       R/W     RESERVED_15                                     1'b0
+    10      R/W     RESERVED_14                                     1'b0
+    11      R/W     RESERVED_13                                     1'b0
+    14:12   R/W     RESERVED_12                                     3'd0
+    15      R/W     RESERVED_11                                     1'b0
+    16      R/W     RESERVED_10                                     1'b0
+    17      R/W     RESERVED_9                                      1'b0
+    18      R/W     RESERVED_8                                      1'b0
+    19      R/W     RESERVED_7                                      1'b0
+    23:20   R/W     RESERVED_6                                      4'd0
+    24      R/W     RESERVED_5                                      1'b0
+    25      R/W     RESERVED_4                                      1'b0
+    26      R/W     RESERVED_3                                      1'b0
+    27      R/W     RESERVED_2                                      1'b0
+    30:28   R/W     RESERVED_1                                      3'd0
+    31      R/W     RESERVED                                        1'b0
+ */
+typedef union _PCC_REG_PADMUX_AS_CFG6_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED_21: 1;
+        uint32_t RESERVED_20: 1;
+        uint32_t RESERVED_19: 1;
+        uint32_t RESERVED_18: 1;
+        uint32_t RESERVED_17: 4;
+        uint32_t RESERVED_16: 1;
+        uint32_t RESERVED_15: 1;
+        uint32_t RESERVED_14: 1;
+        uint32_t RESERVED_13: 1;
+        uint32_t RESERVED_12: 3;
+        uint32_t RESERVED_11: 1;
+        uint32_t RESERVED_10: 1;
+        uint32_t RESERVED_9: 1;
+        uint32_t RESERVED_8: 1;
+        uint32_t RESERVED_7: 1;
+        uint32_t RESERVED_6: 4;
+        uint32_t RESERVED_5: 1;
+        uint32_t RESERVED_4: 1;
+        uint32_t RESERVED_3: 1;
+        uint32_t RESERVED_2: 1;
+        uint32_t RESERVED_1: 3;
+        uint32_t RESERVED: 1;
+    };
+} PCC_REG_PADMUX_AS_CFG6_TYPE;
+
+/*0x4000_0378 PCC_REG_PADMUX_AS_CFG6*/
+#define PCC_REG_PADMUX_AS_CFG6_RESERVED_21_Pos                                                   0U
+#define PCC_REG_PADMUX_AS_CFG6_RESERVED_21_Msk                                                   (0x1UL << PCC_REG_PADMUX_AS_CFG6_RESERVED_21_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG6_RESERVED_20_Pos                                                   1U
+#define PCC_REG_PADMUX_AS_CFG6_RESERVED_20_Msk                                                   (0x1UL << PCC_REG_PADMUX_AS_CFG6_RESERVED_20_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG6_RESERVED_19_Pos                                                   2U
+#define PCC_REG_PADMUX_AS_CFG6_RESERVED_19_Msk                                                   (0x1UL << PCC_REG_PADMUX_AS_CFG6_RESERVED_19_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG6_RESERVED_18_Pos                                                   3U
+#define PCC_REG_PADMUX_AS_CFG6_RESERVED_18_Msk                                                   (0x1UL << PCC_REG_PADMUX_AS_CFG6_RESERVED_18_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG6_RESERVED_17_Pos                                                   4U
+#define PCC_REG_PADMUX_AS_CFG6_RESERVED_17_Msk                                                   (0xFUL << PCC_REG_PADMUX_AS_CFG6_RESERVED_17_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG6_RESERVED_16_Pos                                                   8U
+#define PCC_REG_PADMUX_AS_CFG6_RESERVED_16_Msk                                                   (0x1UL << PCC_REG_PADMUX_AS_CFG6_RESERVED_16_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG6_RESERVED_15_Pos                                                   9U
+#define PCC_REG_PADMUX_AS_CFG6_RESERVED_15_Msk                                                   (0x1UL << PCC_REG_PADMUX_AS_CFG6_RESERVED_15_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG6_RESERVED_14_Pos                                                   10U
+#define PCC_REG_PADMUX_AS_CFG6_RESERVED_14_Msk                                                   (0x1UL << PCC_REG_PADMUX_AS_CFG6_RESERVED_14_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG6_RESERVED_13_Pos                                                   11U
+#define PCC_REG_PADMUX_AS_CFG6_RESERVED_13_Msk                                                   (0x1UL << PCC_REG_PADMUX_AS_CFG6_RESERVED_13_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG6_RESERVED_12_Pos                                                   12U
+#define PCC_REG_PADMUX_AS_CFG6_RESERVED_12_Msk                                                   (0x7UL << PCC_REG_PADMUX_AS_CFG6_RESERVED_12_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG6_RESERVED_11_Pos                                                   15U
+#define PCC_REG_PADMUX_AS_CFG6_RESERVED_11_Msk                                                   (0x1UL << PCC_REG_PADMUX_AS_CFG6_RESERVED_11_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG6_RESERVED_10_Pos                                                   16U
+#define PCC_REG_PADMUX_AS_CFG6_RESERVED_10_Msk                                                   (0x1UL << PCC_REG_PADMUX_AS_CFG6_RESERVED_10_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG6_RESERVED_9_Pos                                                    17U
+#define PCC_REG_PADMUX_AS_CFG6_RESERVED_9_Msk                                                    (0x1UL << PCC_REG_PADMUX_AS_CFG6_RESERVED_9_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG6_RESERVED_8_Pos                                                    18U
+#define PCC_REG_PADMUX_AS_CFG6_RESERVED_8_Msk                                                    (0x1UL << PCC_REG_PADMUX_AS_CFG6_RESERVED_8_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG6_RESERVED_7_Pos                                                    19U
+#define PCC_REG_PADMUX_AS_CFG6_RESERVED_7_Msk                                                    (0x1UL << PCC_REG_PADMUX_AS_CFG6_RESERVED_7_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG6_RESERVED_6_Pos                                                    20U
+#define PCC_REG_PADMUX_AS_CFG6_RESERVED_6_Msk                                                    (0xFUL << PCC_REG_PADMUX_AS_CFG6_RESERVED_6_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG6_RESERVED_5_Pos                                                    24U
+#define PCC_REG_PADMUX_AS_CFG6_RESERVED_5_Msk                                                    (0x1UL << PCC_REG_PADMUX_AS_CFG6_RESERVED_5_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG6_RESERVED_4_Pos                                                    25U
+#define PCC_REG_PADMUX_AS_CFG6_RESERVED_4_Msk                                                    (0x1UL << PCC_REG_PADMUX_AS_CFG6_RESERVED_4_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG6_RESERVED_3_Pos                                                    26U
+#define PCC_REG_PADMUX_AS_CFG6_RESERVED_3_Msk                                                    (0x1UL << PCC_REG_PADMUX_AS_CFG6_RESERVED_3_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG6_RESERVED_2_Pos                                                    27U
+#define PCC_REG_PADMUX_AS_CFG6_RESERVED_2_Msk                                                    (0x1UL << PCC_REG_PADMUX_AS_CFG6_RESERVED_2_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG6_RESERVED_1_Pos                                                    28U
+#define PCC_REG_PADMUX_AS_CFG6_RESERVED_1_Msk                                                    (0x7UL << PCC_REG_PADMUX_AS_CFG6_RESERVED_1_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG6_RESERVED_Pos                                                      31U
+#define PCC_REG_PADMUX_AS_CFG6_RESERVED_Msk                                                      (0x1UL << PCC_REG_PADMUX_AS_CFG6_RESERVED_Pos)
+
+/* 0x37C    0x4000_037c
+    0       R/W     RESERVED_21                                     1'b0
+    1       R/W     RESERVED_20                                     1'b0
+    2       R/W     RESERVED_19                                     1'b0
+    3       R/W     RESERVED_18                                     1'b0
+    7:4     R/W     RESERVED_17                                     4'd0
+    8       R/W     RESERVED_16                                     1'b0
+    9       R/W     RESERVED_15                                     1'b0
+    10      R/W     RESERVED_14                                     1'b0
+    11      R/W     RESERVED_13                                     1'b0
+    14:12   R/W     RESERVED_12                                     3'd0
+    15      R/W     RESERVED_11                                     1'b0
+    16      R/W     RESERVED_10                                     1'b0
+    17      R/W     RESERVED_9                                      1'b0
+    18      R/W     RESERVED_8                                      1'b0
+    19      R/W     RESERVED_7                                      1'b0
+    23:20   R/W     RESERVED_6                                      4'd0
+    24      R/W     RESERVED_5                                      1'b0
+    25      R/W     RESERVED_4                                      1'b0
+    26      R/W     RESERVED_3                                      1'b0
+    27      R/W     RESERVED_2                                      1'b0
+    30:28   R/W     RESERVED_1                                      3'd0
+    31      R/W     RESERVED                                        1'b0
+ */
+typedef union _PCC_REG_PADMUX_AS_CFG7_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED_21: 1;
+        uint32_t RESERVED_20: 1;
+        uint32_t RESERVED_19: 1;
+        uint32_t RESERVED_18: 1;
+        uint32_t RESERVED_17: 4;
+        uint32_t RESERVED_16: 1;
+        uint32_t RESERVED_15: 1;
+        uint32_t RESERVED_14: 1;
+        uint32_t RESERVED_13: 1;
+        uint32_t RESERVED_12: 3;
+        uint32_t RESERVED_11: 1;
+        uint32_t RESERVED_10: 1;
+        uint32_t RESERVED_9: 1;
+        uint32_t RESERVED_8: 1;
+        uint32_t RESERVED_7: 1;
+        uint32_t RESERVED_6: 4;
+        uint32_t RESERVED_5: 1;
+        uint32_t RESERVED_4: 1;
+        uint32_t RESERVED_3: 1;
+        uint32_t RESERVED_2: 1;
+        uint32_t RESERVED_1: 3;
+        uint32_t RESERVED: 1;
+    };
+} PCC_REG_PADMUX_AS_CFG7_TYPE;
+
+/*0x4000_037c PCC_REG_PADMUX_AS_CFG7*/
+#define PCC_REG_PADMUX_AS_CFG7_RESERVED_21_Pos                                                   0U
+#define PCC_REG_PADMUX_AS_CFG7_RESERVED_21_Msk                                                   (0x1UL << PCC_REG_PADMUX_AS_CFG7_RESERVED_21_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG7_RESERVED_20_Pos                                                   1U
+#define PCC_REG_PADMUX_AS_CFG7_RESERVED_20_Msk                                                   (0x1UL << PCC_REG_PADMUX_AS_CFG7_RESERVED_20_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG7_RESERVED_19_Pos                                                   2U
+#define PCC_REG_PADMUX_AS_CFG7_RESERVED_19_Msk                                                   (0x1UL << PCC_REG_PADMUX_AS_CFG7_RESERVED_19_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG7_RESERVED_18_Pos                                                   3U
+#define PCC_REG_PADMUX_AS_CFG7_RESERVED_18_Msk                                                   (0x1UL << PCC_REG_PADMUX_AS_CFG7_RESERVED_18_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG7_RESERVED_17_Pos                                                   4U
+#define PCC_REG_PADMUX_AS_CFG7_RESERVED_17_Msk                                                   (0xFUL << PCC_REG_PADMUX_AS_CFG7_RESERVED_17_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG7_RESERVED_16_Pos                                                   8U
+#define PCC_REG_PADMUX_AS_CFG7_RESERVED_16_Msk                                                   (0x1UL << PCC_REG_PADMUX_AS_CFG7_RESERVED_16_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG7_RESERVED_15_Pos                                                   9U
+#define PCC_REG_PADMUX_AS_CFG7_RESERVED_15_Msk                                                   (0x1UL << PCC_REG_PADMUX_AS_CFG7_RESERVED_15_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG7_RESERVED_14_Pos                                                   10U
+#define PCC_REG_PADMUX_AS_CFG7_RESERVED_14_Msk                                                   (0x1UL << PCC_REG_PADMUX_AS_CFG7_RESERVED_14_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG7_RESERVED_13_Pos                                                   11U
+#define PCC_REG_PADMUX_AS_CFG7_RESERVED_13_Msk                                                   (0x1UL << PCC_REG_PADMUX_AS_CFG7_RESERVED_13_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG7_RESERVED_12_Pos                                                   12U
+#define PCC_REG_PADMUX_AS_CFG7_RESERVED_12_Msk                                                   (0x7UL << PCC_REG_PADMUX_AS_CFG7_RESERVED_12_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG7_RESERVED_11_Pos                                                   15U
+#define PCC_REG_PADMUX_AS_CFG7_RESERVED_11_Msk                                                   (0x1UL << PCC_REG_PADMUX_AS_CFG7_RESERVED_11_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG7_RESERVED_10_Pos                                                   16U
+#define PCC_REG_PADMUX_AS_CFG7_RESERVED_10_Msk                                                   (0x1UL << PCC_REG_PADMUX_AS_CFG7_RESERVED_10_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG7_RESERVED_9_Pos                                                    17U
+#define PCC_REG_PADMUX_AS_CFG7_RESERVED_9_Msk                                                    (0x1UL << PCC_REG_PADMUX_AS_CFG7_RESERVED_9_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG7_RESERVED_8_Pos                                                    18U
+#define PCC_REG_PADMUX_AS_CFG7_RESERVED_8_Msk                                                    (0x1UL << PCC_REG_PADMUX_AS_CFG7_RESERVED_8_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG7_RESERVED_7_Pos                                                    19U
+#define PCC_REG_PADMUX_AS_CFG7_RESERVED_7_Msk                                                    (0x1UL << PCC_REG_PADMUX_AS_CFG7_RESERVED_7_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG7_RESERVED_6_Pos                                                    20U
+#define PCC_REG_PADMUX_AS_CFG7_RESERVED_6_Msk                                                    (0xFUL << PCC_REG_PADMUX_AS_CFG7_RESERVED_6_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG7_RESERVED_5_Pos                                                    24U
+#define PCC_REG_PADMUX_AS_CFG7_RESERVED_5_Msk                                                    (0x1UL << PCC_REG_PADMUX_AS_CFG7_RESERVED_5_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG7_RESERVED_4_Pos                                                    25U
+#define PCC_REG_PADMUX_AS_CFG7_RESERVED_4_Msk                                                    (0x1UL << PCC_REG_PADMUX_AS_CFG7_RESERVED_4_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG7_RESERVED_3_Pos                                                    26U
+#define PCC_REG_PADMUX_AS_CFG7_RESERVED_3_Msk                                                    (0x1UL << PCC_REG_PADMUX_AS_CFG7_RESERVED_3_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG7_RESERVED_2_Pos                                                    27U
+#define PCC_REG_PADMUX_AS_CFG7_RESERVED_2_Msk                                                    (0x1UL << PCC_REG_PADMUX_AS_CFG7_RESERVED_2_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG7_RESERVED_1_Pos                                                    28U
+#define PCC_REG_PADMUX_AS_CFG7_RESERVED_1_Msk                                                    (0x7UL << PCC_REG_PADMUX_AS_CFG7_RESERVED_1_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG7_RESERVED_Pos                                                      31U
+#define PCC_REG_PADMUX_AS_CFG7_RESERVED_Msk                                                      (0x1UL << PCC_REG_PADMUX_AS_CFG7_RESERVED_Pos)
+
+/* 0x380    0x4000_0380
+    0       R/W     RESERVED_21                                     1'b0
+    1       R/W     RESERVED_20                                     1'b0
+    2       R/W     RESERVED_19                                     1'b0
+    3       R/W     RESERVED_18                                     1'b0
+    7:4     R/W     RESERVED_17                                     4'd0
+    8       R/W     RESERVED_16                                     1'b0
+    9       R/W     RESERVED_15                                     1'b0
+    10      R/W     RESERVED_14                                     1'b0
+    11      R/W     RESERVED_13                                     1'b0
+    14:12   R/W     RESERVED_12                                     3'd0
+    15      R/W     RESERVED_11                                     1'b0
+    16      R/W     RESERVED_10                                     1'b0
+    17      R/W     RESERVED_9                                      1'b0
+    18      R/W     RESERVED_8                                      1'b0
+    19      R/W     RESERVED_7                                      1'b0
+    23:20   R/W     RESERVED_6                                      4'd0
+    24      R/W     RESERVED_5                                      1'b0
+    25      R/W     RESERVED_4                                      1'b0
+    26      R/W     RESERVED_3                                      1'b0
+    27      R/W     RESERVED_2                                      1'b0
+    30:28   R/W     RESERVED_1                                      3'd0
+    31      R/W     RESERVED                                        1'b0
+ */
+typedef union _PCC_REG_PADMUX_AS_CFG8_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED_21: 1;
+        uint32_t RESERVED_20: 1;
+        uint32_t RESERVED_19: 1;
+        uint32_t RESERVED_18: 1;
+        uint32_t RESERVED_17: 4;
+        uint32_t RESERVED_16: 1;
+        uint32_t RESERVED_15: 1;
+        uint32_t RESERVED_14: 1;
+        uint32_t RESERVED_13: 1;
+        uint32_t RESERVED_12: 3;
+        uint32_t RESERVED_11: 1;
+        uint32_t RESERVED_10: 1;
+        uint32_t RESERVED_9: 1;
+        uint32_t RESERVED_8: 1;
+        uint32_t RESERVED_7: 1;
+        uint32_t RESERVED_6: 4;
+        uint32_t RESERVED_5: 1;
+        uint32_t RESERVED_4: 1;
+        uint32_t RESERVED_3: 1;
+        uint32_t RESERVED_2: 1;
+        uint32_t RESERVED_1: 3;
+        uint32_t RESERVED: 1;
+    };
+} PCC_REG_PADMUX_AS_CFG8_TYPE;
+
+/*0x4000_0380 PCC_REG_PADMUX_AS_CFG8*/
+#define PCC_REG_PADMUX_AS_CFG8_RESERVED_21_Pos                                                   0U
+#define PCC_REG_PADMUX_AS_CFG8_RESERVED_21_Msk                                                   (0x1UL << PCC_REG_PADMUX_AS_CFG8_RESERVED_21_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG8_RESERVED_20_Pos                                                   1U
+#define PCC_REG_PADMUX_AS_CFG8_RESERVED_20_Msk                                                   (0x1UL << PCC_REG_PADMUX_AS_CFG8_RESERVED_20_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG8_RESERVED_19_Pos                                                   2U
+#define PCC_REG_PADMUX_AS_CFG8_RESERVED_19_Msk                                                   (0x1UL << PCC_REG_PADMUX_AS_CFG8_RESERVED_19_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG8_RESERVED_18_Pos                                                   3U
+#define PCC_REG_PADMUX_AS_CFG8_RESERVED_18_Msk                                                   (0x1UL << PCC_REG_PADMUX_AS_CFG8_RESERVED_18_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG8_RESERVED_17_Pos                                                   4U
+#define PCC_REG_PADMUX_AS_CFG8_RESERVED_17_Msk                                                   (0xFUL << PCC_REG_PADMUX_AS_CFG8_RESERVED_17_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG8_RESERVED_16_Pos                                                   8U
+#define PCC_REG_PADMUX_AS_CFG8_RESERVED_16_Msk                                                   (0x1UL << PCC_REG_PADMUX_AS_CFG8_RESERVED_16_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG8_RESERVED_15_Pos                                                   9U
+#define PCC_REG_PADMUX_AS_CFG8_RESERVED_15_Msk                                                   (0x1UL << PCC_REG_PADMUX_AS_CFG8_RESERVED_15_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG8_RESERVED_14_Pos                                                   10U
+#define PCC_REG_PADMUX_AS_CFG8_RESERVED_14_Msk                                                   (0x1UL << PCC_REG_PADMUX_AS_CFG8_RESERVED_14_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG8_RESERVED_13_Pos                                                   11U
+#define PCC_REG_PADMUX_AS_CFG8_RESERVED_13_Msk                                                   (0x1UL << PCC_REG_PADMUX_AS_CFG8_RESERVED_13_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG8_RESERVED_12_Pos                                                   12U
+#define PCC_REG_PADMUX_AS_CFG8_RESERVED_12_Msk                                                   (0x7UL << PCC_REG_PADMUX_AS_CFG8_RESERVED_12_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG8_RESERVED_11_Pos                                                   15U
+#define PCC_REG_PADMUX_AS_CFG8_RESERVED_11_Msk                                                   (0x1UL << PCC_REG_PADMUX_AS_CFG8_RESERVED_11_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG8_RESERVED_10_Pos                                                   16U
+#define PCC_REG_PADMUX_AS_CFG8_RESERVED_10_Msk                                                   (0x1UL << PCC_REG_PADMUX_AS_CFG8_RESERVED_10_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG8_RESERVED_9_Pos                                                    17U
+#define PCC_REG_PADMUX_AS_CFG8_RESERVED_9_Msk                                                    (0x1UL << PCC_REG_PADMUX_AS_CFG8_RESERVED_9_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG8_RESERVED_8_Pos                                                    18U
+#define PCC_REG_PADMUX_AS_CFG8_RESERVED_8_Msk                                                    (0x1UL << PCC_REG_PADMUX_AS_CFG8_RESERVED_8_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG8_RESERVED_7_Pos                                                    19U
+#define PCC_REG_PADMUX_AS_CFG8_RESERVED_7_Msk                                                    (0x1UL << PCC_REG_PADMUX_AS_CFG8_RESERVED_7_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG8_RESERVED_6_Pos                                                    20U
+#define PCC_REG_PADMUX_AS_CFG8_RESERVED_6_Msk                                                    (0xFUL << PCC_REG_PADMUX_AS_CFG8_RESERVED_6_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG8_RESERVED_5_Pos                                                    24U
+#define PCC_REG_PADMUX_AS_CFG8_RESERVED_5_Msk                                                    (0x1UL << PCC_REG_PADMUX_AS_CFG8_RESERVED_5_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG8_RESERVED_4_Pos                                                    25U
+#define PCC_REG_PADMUX_AS_CFG8_RESERVED_4_Msk                                                    (0x1UL << PCC_REG_PADMUX_AS_CFG8_RESERVED_4_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG8_RESERVED_3_Pos                                                    26U
+#define PCC_REG_PADMUX_AS_CFG8_RESERVED_3_Msk                                                    (0x1UL << PCC_REG_PADMUX_AS_CFG8_RESERVED_3_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG8_RESERVED_2_Pos                                                    27U
+#define PCC_REG_PADMUX_AS_CFG8_RESERVED_2_Msk                                                    (0x1UL << PCC_REG_PADMUX_AS_CFG8_RESERVED_2_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG8_RESERVED_1_Pos                                                    28U
+#define PCC_REG_PADMUX_AS_CFG8_RESERVED_1_Msk                                                    (0x7UL << PCC_REG_PADMUX_AS_CFG8_RESERVED_1_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG8_RESERVED_Pos                                                      31U
+#define PCC_REG_PADMUX_AS_CFG8_RESERVED_Msk                                                      (0x1UL << PCC_REG_PADMUX_AS_CFG8_RESERVED_Pos)
+
+/* 0x384    0x4000_0384
+    0       R/W     RESERVED_21                                     1'b0
+    1       R/W     RESERVED_20                                     1'b0
+    2       R/W     RESERVED_19                                     1'b0
+    3       R/W     RESERVED_18                                     1'b0
+    7:4     R/W     RESERVED_17                                     4'd0
+    8       R/W     RESERVED_16                                     1'b0
+    9       R/W     RESERVED_15                                     1'b0
+    10      R/W     RESERVED_14                                     1'b0
+    11      R/W     RESERVED_13                                     1'b0
+    14:12   R/W     RESERVED_12                                     3'd0
+    15      R/W     RESERVED_11                                     1'b0
+    16      R/W     RESERVED_10                                     1'b0
+    17      R/W     RESERVED_9                                      1'b0
+    18      R/W     RESERVED_8                                      1'b0
+    19      R/W     RESERVED_7                                      1'b0
+    23:20   R/W     RESERVED_6                                      4'd0
+    24      R/W     RESERVED_5                                      1'b0
+    25      R/W     RESERVED_4                                      1'b0
+    26      R/W     RESERVED_3                                      1'b0
+    27      R/W     RESERVED_2                                      1'b0
+    30:28   R/W     RESERVED_1                                      3'd0
+    31      R/W     RESERVED                                        1'b0
+ */
+typedef union _PCC_REG_PADMUX_AS_CFG9_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED_21: 1;
+        uint32_t RESERVED_20: 1;
+        uint32_t RESERVED_19: 1;
+        uint32_t RESERVED_18: 1;
+        uint32_t RESERVED_17: 4;
+        uint32_t RESERVED_16: 1;
+        uint32_t RESERVED_15: 1;
+        uint32_t RESERVED_14: 1;
+        uint32_t RESERVED_13: 1;
+        uint32_t RESERVED_12: 3;
+        uint32_t RESERVED_11: 1;
+        uint32_t RESERVED_10: 1;
+        uint32_t RESERVED_9: 1;
+        uint32_t RESERVED_8: 1;
+        uint32_t RESERVED_7: 1;
+        uint32_t RESERVED_6: 4;
+        uint32_t RESERVED_5: 1;
+        uint32_t RESERVED_4: 1;
+        uint32_t RESERVED_3: 1;
+        uint32_t RESERVED_2: 1;
+        uint32_t RESERVED_1: 3;
+        uint32_t RESERVED: 1;
+    };
+} PCC_REG_PADMUX_AS_CFG9_TYPE;
+
+/*0x4000_0384 PCC_REG_PADMUX_AS_CFG9*/
+#define PCC_REG_PADMUX_AS_CFG9_RESERVED_21_Pos                                                   0U
+#define PCC_REG_PADMUX_AS_CFG9_RESERVED_21_Msk                                                   (0x1UL << PCC_REG_PADMUX_AS_CFG9_RESERVED_21_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG9_RESERVED_20_Pos                                                   1U
+#define PCC_REG_PADMUX_AS_CFG9_RESERVED_20_Msk                                                   (0x1UL << PCC_REG_PADMUX_AS_CFG9_RESERVED_20_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG9_RESERVED_19_Pos                                                   2U
+#define PCC_REG_PADMUX_AS_CFG9_RESERVED_19_Msk                                                   (0x1UL << PCC_REG_PADMUX_AS_CFG9_RESERVED_19_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG9_RESERVED_18_Pos                                                   3U
+#define PCC_REG_PADMUX_AS_CFG9_RESERVED_18_Msk                                                   (0x1UL << PCC_REG_PADMUX_AS_CFG9_RESERVED_18_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG9_RESERVED_17_Pos                                                   4U
+#define PCC_REG_PADMUX_AS_CFG9_RESERVED_17_Msk                                                   (0xFUL << PCC_REG_PADMUX_AS_CFG9_RESERVED_17_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG9_RESERVED_16_Pos                                                   8U
+#define PCC_REG_PADMUX_AS_CFG9_RESERVED_16_Msk                                                   (0x1UL << PCC_REG_PADMUX_AS_CFG9_RESERVED_16_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG9_RESERVED_15_Pos                                                   9U
+#define PCC_REG_PADMUX_AS_CFG9_RESERVED_15_Msk                                                   (0x1UL << PCC_REG_PADMUX_AS_CFG9_RESERVED_15_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG9_RESERVED_14_Pos                                                   10U
+#define PCC_REG_PADMUX_AS_CFG9_RESERVED_14_Msk                                                   (0x1UL << PCC_REG_PADMUX_AS_CFG9_RESERVED_14_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG9_RESERVED_13_Pos                                                   11U
+#define PCC_REG_PADMUX_AS_CFG9_RESERVED_13_Msk                                                   (0x1UL << PCC_REG_PADMUX_AS_CFG9_RESERVED_13_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG9_RESERVED_12_Pos                                                   12U
+#define PCC_REG_PADMUX_AS_CFG9_RESERVED_12_Msk                                                   (0x7UL << PCC_REG_PADMUX_AS_CFG9_RESERVED_12_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG9_RESERVED_11_Pos                                                   15U
+#define PCC_REG_PADMUX_AS_CFG9_RESERVED_11_Msk                                                   (0x1UL << PCC_REG_PADMUX_AS_CFG9_RESERVED_11_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG9_RESERVED_10_Pos                                                   16U
+#define PCC_REG_PADMUX_AS_CFG9_RESERVED_10_Msk                                                   (0x1UL << PCC_REG_PADMUX_AS_CFG9_RESERVED_10_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG9_RESERVED_9_Pos                                                    17U
+#define PCC_REG_PADMUX_AS_CFG9_RESERVED_9_Msk                                                    (0x1UL << PCC_REG_PADMUX_AS_CFG9_RESERVED_9_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG9_RESERVED_8_Pos                                                    18U
+#define PCC_REG_PADMUX_AS_CFG9_RESERVED_8_Msk                                                    (0x1UL << PCC_REG_PADMUX_AS_CFG9_RESERVED_8_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG9_RESERVED_7_Pos                                                    19U
+#define PCC_REG_PADMUX_AS_CFG9_RESERVED_7_Msk                                                    (0x1UL << PCC_REG_PADMUX_AS_CFG9_RESERVED_7_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG9_RESERVED_6_Pos                                                    20U
+#define PCC_REG_PADMUX_AS_CFG9_RESERVED_6_Msk                                                    (0xFUL << PCC_REG_PADMUX_AS_CFG9_RESERVED_6_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG9_RESERVED_5_Pos                                                    24U
+#define PCC_REG_PADMUX_AS_CFG9_RESERVED_5_Msk                                                    (0x1UL << PCC_REG_PADMUX_AS_CFG9_RESERVED_5_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG9_RESERVED_4_Pos                                                    25U
+#define PCC_REG_PADMUX_AS_CFG9_RESERVED_4_Msk                                                    (0x1UL << PCC_REG_PADMUX_AS_CFG9_RESERVED_4_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG9_RESERVED_3_Pos                                                    26U
+#define PCC_REG_PADMUX_AS_CFG9_RESERVED_3_Msk                                                    (0x1UL << PCC_REG_PADMUX_AS_CFG9_RESERVED_3_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG9_RESERVED_2_Pos                                                    27U
+#define PCC_REG_PADMUX_AS_CFG9_RESERVED_2_Msk                                                    (0x1UL << PCC_REG_PADMUX_AS_CFG9_RESERVED_2_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG9_RESERVED_1_Pos                                                    28U
+#define PCC_REG_PADMUX_AS_CFG9_RESERVED_1_Msk                                                    (0x7UL << PCC_REG_PADMUX_AS_CFG9_RESERVED_1_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG9_RESERVED_Pos                                                      31U
+#define PCC_REG_PADMUX_AS_CFG9_RESERVED_Msk                                                      (0x1UL << PCC_REG_PADMUX_AS_CFG9_RESERVED_Pos)
+
+/* 0x388    0x4000_0388
+    0       R       I2C0_BUS_QCH_BUSY_FLAG1                         1'b0
+    1       R       I2C0_QCH_BUSY_FLAG1                             1'b0
+    2       R       GPIO_DBNC_QCH_BUSY_FLAG1                        1'b0
+    3       R       GPIO_BUS_QCH_BUSY_FLAG1                         1'b0
+    4       R       GPIO_QCH_BUSY_FLAG1                             1'b0
+    5       R       GDMA_BUS_QCH_BUSY_FLAG1                         1'b0
+    6       R       ETIMER_PCLK_QCH_BUSY_FLAG1                      1'b0
+    7       R       ETIMER_PWM_QCH_BUSY_FLAG1                       1'b0
+    8       R       ETIMER_BUS_QCH_BUSY_FLAG1                       1'b0
+    9       R       ETIMER_QCH_BUSY_FLAG1                           1'b0
+    10      R       EFLASH_BUS_QCH_BUSY_FLAG1                       1'b0
+    11      R       EFLASH_QCH_BUSY_FLAG1                           1'b0
+    12      R       CPU_BUS_QCH_BUSY_FLAG1                          1'b0
+    13      R       CAN_LP_QCH_BUSY_FLAG1                           1'b0
+    14      R       CAN_BUS_QCH_BUSY_FLAG1                          1'b0
+    15      R       CAN_PWR_QCH_BUSY_FLAG1                          1'b0
+    16      R       CAN_QCH_BUSY_FLAG1                              1'b0
+    17      R       AES_QCH_BUSY_FLAG1                              1'b0
+    31:18   R       RESERVED                                        14'd0
+ */
+typedef union _PCC_REG_PADMUX_AS_CFG10_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t I2C0_BUS_QCH_BUSY_FLAG1: 1;
+        uint32_t I2C0_QCH_BUSY_FLAG1: 1;
+        uint32_t GPIO_DBNC_QCH_BUSY_FLAG1: 1;
+        uint32_t GPIO_BUS_QCH_BUSY_FLAG1: 1;
+        uint32_t GPIO_QCH_BUSY_FLAG1: 1;
+        uint32_t GDMA_BUS_QCH_BUSY_FLAG1: 1;
+        uint32_t ETIMER_PCLK_QCH_BUSY_FLAG1: 1;
+        uint32_t ETIMER_PWM_QCH_BUSY_FLAG1: 1;
+        uint32_t ETIMER_BUS_QCH_BUSY_FLAG1: 1;
+        uint32_t ETIMER_QCH_BUSY_FLAG1: 1;
+        uint32_t EFLASH_BUS_QCH_BUSY_FLAG1: 1;
+        uint32_t EFLASH_QCH_BUSY_FLAG1: 1;
+        uint32_t CPU_BUS_QCH_BUSY_FLAG1: 1;
+        uint32_t CAN_LP_QCH_BUSY_FLAG1: 1;
+        uint32_t CAN_BUS_QCH_BUSY_FLAG1: 1;
+        uint32_t CAN_PWR_QCH_BUSY_FLAG1: 1;
+        uint32_t CAN_QCH_BUSY_FLAG1: 1;
+        uint32_t AES_QCH_BUSY_FLAG1: 1;
+        uint32_t RESERVED: 14;
+    };
+} PCC_REG_PADMUX_AS_CFG10_TYPE;
+
+/*0x4000_0388 PCC_REG_PADMUX_AS_CFG10*/
+#define PCC_REG_PADMUX_AS_CFG10_I2C0_BUS_QCH_BUSY_FLAG1_Pos                                      0U
+#define PCC_REG_PADMUX_AS_CFG10_I2C0_BUS_QCH_BUSY_FLAG1_Msk                                      (0x1UL << PCC_REG_PADMUX_AS_CFG10_I2C0_BUS_QCH_BUSY_FLAG1_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG10_I2C0_QCH_BUSY_FLAG1_Pos                                          1U
+#define PCC_REG_PADMUX_AS_CFG10_I2C0_QCH_BUSY_FLAG1_Msk                                          (0x1UL << PCC_REG_PADMUX_AS_CFG10_I2C0_QCH_BUSY_FLAG1_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG10_GPIO_DBNC_QCH_BUSY_FLAG1_Pos                                     2U
+#define PCC_REG_PADMUX_AS_CFG10_GPIO_DBNC_QCH_BUSY_FLAG1_Msk                                     (0x1UL << PCC_REG_PADMUX_AS_CFG10_GPIO_DBNC_QCH_BUSY_FLAG1_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG10_GPIO_BUS_QCH_BUSY_FLAG1_Pos                                      3U
+#define PCC_REG_PADMUX_AS_CFG10_GPIO_BUS_QCH_BUSY_FLAG1_Msk                                      (0x1UL << PCC_REG_PADMUX_AS_CFG10_GPIO_BUS_QCH_BUSY_FLAG1_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG10_GPIO_QCH_BUSY_FLAG1_Pos                                          4U
+#define PCC_REG_PADMUX_AS_CFG10_GPIO_QCH_BUSY_FLAG1_Msk                                          (0x1UL << PCC_REG_PADMUX_AS_CFG10_GPIO_QCH_BUSY_FLAG1_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG10_GDMA_BUS_QCH_BUSY_FLAG1_Pos                                      5U
+#define PCC_REG_PADMUX_AS_CFG10_GDMA_BUS_QCH_BUSY_FLAG1_Msk                                      (0x1UL << PCC_REG_PADMUX_AS_CFG10_GDMA_BUS_QCH_BUSY_FLAG1_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG10_ETIMER_PCLK_QCH_BUSY_FLAG1_Pos                                   6U
+#define PCC_REG_PADMUX_AS_CFG10_ETIMER_PCLK_QCH_BUSY_FLAG1_Msk                                   (0x1UL << PCC_REG_PADMUX_AS_CFG10_ETIMER_PCLK_QCH_BUSY_FLAG1_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG10_ETIMER_PWM_QCH_BUSY_FLAG1_Pos                                    7U
+#define PCC_REG_PADMUX_AS_CFG10_ETIMER_PWM_QCH_BUSY_FLAG1_Msk                                    (0x1UL << PCC_REG_PADMUX_AS_CFG10_ETIMER_PWM_QCH_BUSY_FLAG1_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG10_ETIMER_BUS_QCH_BUSY_FLAG1_Pos                                    8U
+#define PCC_REG_PADMUX_AS_CFG10_ETIMER_BUS_QCH_BUSY_FLAG1_Msk                                    (0x1UL << PCC_REG_PADMUX_AS_CFG10_ETIMER_BUS_QCH_BUSY_FLAG1_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG10_ETIMER_QCH_BUSY_FLAG1_Pos                                        9U
+#define PCC_REG_PADMUX_AS_CFG10_ETIMER_QCH_BUSY_FLAG1_Msk                                        (0x1UL << PCC_REG_PADMUX_AS_CFG10_ETIMER_QCH_BUSY_FLAG1_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG10_EFLASH_BUS_QCH_BUSY_FLAG1_Pos                                    10U
+#define PCC_REG_PADMUX_AS_CFG10_EFLASH_BUS_QCH_BUSY_FLAG1_Msk                                    (0x1UL << PCC_REG_PADMUX_AS_CFG10_EFLASH_BUS_QCH_BUSY_FLAG1_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG10_EFLASH_QCH_BUSY_FLAG1_Pos                                        11U
+#define PCC_REG_PADMUX_AS_CFG10_EFLASH_QCH_BUSY_FLAG1_Msk                                        (0x1UL << PCC_REG_PADMUX_AS_CFG10_EFLASH_QCH_BUSY_FLAG1_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG10_CPU_BUS_QCH_BUSY_FLAG1_Pos                                       12U
+#define PCC_REG_PADMUX_AS_CFG10_CPU_BUS_QCH_BUSY_FLAG1_Msk                                       (0x1UL << PCC_REG_PADMUX_AS_CFG10_CPU_BUS_QCH_BUSY_FLAG1_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG10_CAN_LP_QCH_BUSY_FLAG1_Pos                                        13U
+#define PCC_REG_PADMUX_AS_CFG10_CAN_LP_QCH_BUSY_FLAG1_Msk                                        (0x1UL << PCC_REG_PADMUX_AS_CFG10_CAN_LP_QCH_BUSY_FLAG1_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG10_CAN_BUS_QCH_BUSY_FLAG1_Pos                                       14U
+#define PCC_REG_PADMUX_AS_CFG10_CAN_BUS_QCH_BUSY_FLAG1_Msk                                       (0x1UL << PCC_REG_PADMUX_AS_CFG10_CAN_BUS_QCH_BUSY_FLAG1_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG10_CAN_PWR_QCH_BUSY_FLAG1_Pos                                       15U
+#define PCC_REG_PADMUX_AS_CFG10_CAN_PWR_QCH_BUSY_FLAG1_Msk                                       (0x1UL << PCC_REG_PADMUX_AS_CFG10_CAN_PWR_QCH_BUSY_FLAG1_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG10_CAN_QCH_BUSY_FLAG1_Pos                                           16U
+#define PCC_REG_PADMUX_AS_CFG10_CAN_QCH_BUSY_FLAG1_Msk                                           (0x1UL << PCC_REG_PADMUX_AS_CFG10_CAN_QCH_BUSY_FLAG1_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG10_AES_QCH_BUSY_FLAG1_Pos                                           17U
+#define PCC_REG_PADMUX_AS_CFG10_AES_QCH_BUSY_FLAG1_Msk                                           (0x1UL << PCC_REG_PADMUX_AS_CFG10_AES_QCH_BUSY_FLAG1_Pos)
+
+#define PCC_REG_PADMUX_AS_CFG10_RESERVED_Pos                                                     18U
+#define PCC_REG_PADMUX_AS_CFG10_RESERVED_Msk                                                     (0x3FFFUL << PCC_REG_PADMUX_AS_CFG10_RESERVED_Pos)
+
+/* 0x38C    0x4000_038c
+    0       R       TIMER3_QCH_BUSY_FLAG1                           1'b0
+    1       R       TIMER2_QCH_BUSY_FLAG1                           1'b0
+    2       R       TIMER1_PCLK_QCH_BUSY_FLAG1                      1'b0
+    3       R       TIMER1_BUS_QCH_BUSY_FLAG1                       1'b0
+    4       R       TIMER1_QCH_BUSY_FLAG1                           1'b0
+    5       R       SPIC0_QCH_BUSY_FLAG1                            1'b0
+    6       R       SPI3W_BUS_QCH_BUSY_FLAG1                        1'b0
+    7       R       SPI3W_QCH_BUSY_FLAG1                            1'b0
+    8       R       SPI2_PWR_QCH_BUSY_FLAG1                         1'b0
+    9       R       SPI2_BUS_QCH_BUSY_FLAG1                         1'b0
+    10      R       SPI2_QCH_BUSY_FLAG1                             1'b0
+    11      R       SPI1_HS_BUS_QCH_BUSY_FLAG1                      1'b0
+    12      R       SPI1_PWR_QCH_BUSY_FLAG1                         1'b0
+    13      R       SPI1_BUS_QCH_BUSY_FLAG1                         1'b0
+    14      R       SPI1_QCH_BUSY_FLAG1                             1'b0
+    15      R       SPI0_HS_BUS_QCH_BUSY_FLAG1                      1'b0
+    16      R       SPI0_PWR_QCH_BUSY_FLAG1                         1'b0
+    17      R       SPI0_BUS_QCH_BUSY_FLAG1                         1'b0
+    18      R       SPI0_QCH_BUSY_FLAG1                             1'b0
+    19      R       SHA256_BUS_QCH_BUSY_FLAG1                       1'b0
+    20      R       RNG_BUS_QCH_BUSY_FLAG1                          1'b0
+    21      R       RNG_QCH_BUSY_FLAG1                              1'b0
+    22      R       RXI300_QCH_BUSY_FLAG1                           1'b0
+    23      R       KEYSCAN_BUS_QCH_BUSY_FLAG1                      1'b0
+    24      R       KEYSCAN_QCH_BUSY_FLAG1                          1'b0
+    25      R       IRRC_PWR_QCH_BUSY_FLAG1                         1'b0
+    26      R       IRRC_BUS_QCH_BUSY_FLAG1                         1'b0
+    27      R       IRRC_QCH_BUSY_FLAG1                             1'b0
+    28      R       I2C1_PWR_QCH_BUSY_FLAG1                         1'b0
+    29      R       I2C1_BUS_QCH_BUSY_FLAG1                         1'b0
+    30      R       I2C1_QCH_BUSY_FLAG1                             1'b0
+    31      R       I2C0_PWR_QCH_BUSY_FLAG1                         1'b0
+ */
+typedef union _PCC_REG_QCH_BUSY_FLAG1_PROC1_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t TIMER3_QCH_BUSY_FLAG1: 1;
+        uint32_t TIMER2_QCH_BUSY_FLAG1: 1;
+        uint32_t TIMER1_PCLK_QCH_BUSY_FLAG1: 1;
+        uint32_t TIMER1_BUS_QCH_BUSY_FLAG1: 1;
+        uint32_t TIMER1_QCH_BUSY_FLAG1: 1;
+        uint32_t SPIC0_QCH_BUSY_FLAG1: 1;
+        uint32_t SPI3W_BUS_QCH_BUSY_FLAG1: 1;
+        uint32_t SPI3W_QCH_BUSY_FLAG1: 1;
+        uint32_t SPI2_PWR_QCH_BUSY_FLAG1: 1;
+        uint32_t SPI2_BUS_QCH_BUSY_FLAG1: 1;
+        uint32_t SPI2_QCH_BUSY_FLAG1: 1;
+        uint32_t SPI1_HS_BUS_QCH_BUSY_FLAG1: 1;
+        uint32_t SPI1_PWR_QCH_BUSY_FLAG1: 1;
+        uint32_t SPI1_BUS_QCH_BUSY_FLAG1: 1;
+        uint32_t SPI1_QCH_BUSY_FLAG1: 1;
+        uint32_t SPI0_HS_BUS_QCH_BUSY_FLAG1: 1;
+        uint32_t SPI0_PWR_QCH_BUSY_FLAG1: 1;
+        uint32_t SPI0_BUS_QCH_BUSY_FLAG1: 1;
+        uint32_t SPI0_QCH_BUSY_FLAG1: 1;
+        uint32_t SHA256_BUS_QCH_BUSY_FLAG1: 1;
+        uint32_t RNG_BUS_QCH_BUSY_FLAG1: 1;
+        uint32_t RNG_QCH_BUSY_FLAG1: 1;
+        uint32_t RXI300_QCH_BUSY_FLAG1: 1;
+        uint32_t KEYSCAN_BUS_QCH_BUSY_FLAG1: 1;
+        uint32_t KEYSCAN_QCH_BUSY_FLAG1: 1;
+        uint32_t IRRC_PWR_QCH_BUSY_FLAG1: 1;
+        uint32_t IRRC_BUS_QCH_BUSY_FLAG1: 1;
+        uint32_t IRRC_QCH_BUSY_FLAG1: 1;
+        uint32_t I2C1_PWR_QCH_BUSY_FLAG1: 1;
+        uint32_t I2C1_BUS_QCH_BUSY_FLAG1: 1;
+        uint32_t I2C1_QCH_BUSY_FLAG1: 1;
+        uint32_t I2C0_PWR_QCH_BUSY_FLAG1: 1;
+    };
+} PCC_REG_QCH_BUSY_FLAG1_PROC1_TYPE;
+
+/*0x4000_038c PCC_REG_QCH_BUSY_FLAG1_PROC1*/
+#define PCC_REG_QCH_BUSY_FLAG1_PROC1_TIMER3_QCH_BUSY_FLAG1_Pos                                   0U
+#define PCC_REG_QCH_BUSY_FLAG1_PROC1_TIMER3_QCH_BUSY_FLAG1_Msk                                   (0x1UL << PCC_REG_QCH_BUSY_FLAG1_PROC1_TIMER3_QCH_BUSY_FLAG1_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG1_PROC1_TIMER2_QCH_BUSY_FLAG1_Pos                                   1U
+#define PCC_REG_QCH_BUSY_FLAG1_PROC1_TIMER2_QCH_BUSY_FLAG1_Msk                                   (0x1UL << PCC_REG_QCH_BUSY_FLAG1_PROC1_TIMER2_QCH_BUSY_FLAG1_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG1_PROC1_TIMER1_PCLK_QCH_BUSY_FLAG1_Pos                              2U
+#define PCC_REG_QCH_BUSY_FLAG1_PROC1_TIMER1_PCLK_QCH_BUSY_FLAG1_Msk                              (0x1UL << PCC_REG_QCH_BUSY_FLAG1_PROC1_TIMER1_PCLK_QCH_BUSY_FLAG1_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG1_PROC1_TIMER1_BUS_QCH_BUSY_FLAG1_Pos                               3U
+#define PCC_REG_QCH_BUSY_FLAG1_PROC1_TIMER1_BUS_QCH_BUSY_FLAG1_Msk                               (0x1UL << PCC_REG_QCH_BUSY_FLAG1_PROC1_TIMER1_BUS_QCH_BUSY_FLAG1_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG1_PROC1_TIMER1_QCH_BUSY_FLAG1_Pos                                   4U
+#define PCC_REG_QCH_BUSY_FLAG1_PROC1_TIMER1_QCH_BUSY_FLAG1_Msk                                   (0x1UL << PCC_REG_QCH_BUSY_FLAG1_PROC1_TIMER1_QCH_BUSY_FLAG1_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG1_PROC1_SPIC0_QCH_BUSY_FLAG1_Pos                                    5U
+#define PCC_REG_QCH_BUSY_FLAG1_PROC1_SPIC0_QCH_BUSY_FLAG1_Msk                                    (0x1UL << PCC_REG_QCH_BUSY_FLAG1_PROC1_SPIC0_QCH_BUSY_FLAG1_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG1_PROC1_SPI3W_BUS_QCH_BUSY_FLAG1_Pos                                6U
+#define PCC_REG_QCH_BUSY_FLAG1_PROC1_SPI3W_BUS_QCH_BUSY_FLAG1_Msk                                (0x1UL << PCC_REG_QCH_BUSY_FLAG1_PROC1_SPI3W_BUS_QCH_BUSY_FLAG1_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG1_PROC1_SPI3W_QCH_BUSY_FLAG1_Pos                                    7U
+#define PCC_REG_QCH_BUSY_FLAG1_PROC1_SPI3W_QCH_BUSY_FLAG1_Msk                                    (0x1UL << PCC_REG_QCH_BUSY_FLAG1_PROC1_SPI3W_QCH_BUSY_FLAG1_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG1_PROC1_SPI2_PWR_QCH_BUSY_FLAG1_Pos                                 8U
+#define PCC_REG_QCH_BUSY_FLAG1_PROC1_SPI2_PWR_QCH_BUSY_FLAG1_Msk                                 (0x1UL << PCC_REG_QCH_BUSY_FLAG1_PROC1_SPI2_PWR_QCH_BUSY_FLAG1_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG1_PROC1_SPI2_BUS_QCH_BUSY_FLAG1_Pos                                 9U
+#define PCC_REG_QCH_BUSY_FLAG1_PROC1_SPI2_BUS_QCH_BUSY_FLAG1_Msk                                 (0x1UL << PCC_REG_QCH_BUSY_FLAG1_PROC1_SPI2_BUS_QCH_BUSY_FLAG1_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG1_PROC1_SPI2_QCH_BUSY_FLAG1_Pos                                     10U
+#define PCC_REG_QCH_BUSY_FLAG1_PROC1_SPI2_QCH_BUSY_FLAG1_Msk                                     (0x1UL << PCC_REG_QCH_BUSY_FLAG1_PROC1_SPI2_QCH_BUSY_FLAG1_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG1_PROC1_SPI1_HS_BUS_QCH_BUSY_FLAG1_Pos                              11U
+#define PCC_REG_QCH_BUSY_FLAG1_PROC1_SPI1_HS_BUS_QCH_BUSY_FLAG1_Msk                              (0x1UL << PCC_REG_QCH_BUSY_FLAG1_PROC1_SPI1_HS_BUS_QCH_BUSY_FLAG1_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG1_PROC1_SPI1_PWR_QCH_BUSY_FLAG1_Pos                                 12U
+#define PCC_REG_QCH_BUSY_FLAG1_PROC1_SPI1_PWR_QCH_BUSY_FLAG1_Msk                                 (0x1UL << PCC_REG_QCH_BUSY_FLAG1_PROC1_SPI1_PWR_QCH_BUSY_FLAG1_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG1_PROC1_SPI1_BUS_QCH_BUSY_FLAG1_Pos                                 13U
+#define PCC_REG_QCH_BUSY_FLAG1_PROC1_SPI1_BUS_QCH_BUSY_FLAG1_Msk                                 (0x1UL << PCC_REG_QCH_BUSY_FLAG1_PROC1_SPI1_BUS_QCH_BUSY_FLAG1_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG1_PROC1_SPI1_QCH_BUSY_FLAG1_Pos                                     14U
+#define PCC_REG_QCH_BUSY_FLAG1_PROC1_SPI1_QCH_BUSY_FLAG1_Msk                                     (0x1UL << PCC_REG_QCH_BUSY_FLAG1_PROC1_SPI1_QCH_BUSY_FLAG1_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG1_PROC1_SPI0_HS_BUS_QCH_BUSY_FLAG1_Pos                              15U
+#define PCC_REG_QCH_BUSY_FLAG1_PROC1_SPI0_HS_BUS_QCH_BUSY_FLAG1_Msk                              (0x1UL << PCC_REG_QCH_BUSY_FLAG1_PROC1_SPI0_HS_BUS_QCH_BUSY_FLAG1_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG1_PROC1_SPI0_PWR_QCH_BUSY_FLAG1_Pos                                 16U
+#define PCC_REG_QCH_BUSY_FLAG1_PROC1_SPI0_PWR_QCH_BUSY_FLAG1_Msk                                 (0x1UL << PCC_REG_QCH_BUSY_FLAG1_PROC1_SPI0_PWR_QCH_BUSY_FLAG1_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG1_PROC1_SPI0_BUS_QCH_BUSY_FLAG1_Pos                                 17U
+#define PCC_REG_QCH_BUSY_FLAG1_PROC1_SPI0_BUS_QCH_BUSY_FLAG1_Msk                                 (0x1UL << PCC_REG_QCH_BUSY_FLAG1_PROC1_SPI0_BUS_QCH_BUSY_FLAG1_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG1_PROC1_SPI0_QCH_BUSY_FLAG1_Pos                                     18U
+#define PCC_REG_QCH_BUSY_FLAG1_PROC1_SPI0_QCH_BUSY_FLAG1_Msk                                     (0x1UL << PCC_REG_QCH_BUSY_FLAG1_PROC1_SPI0_QCH_BUSY_FLAG1_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG1_PROC1_SHA256_BUS_QCH_BUSY_FLAG1_Pos                               19U
+#define PCC_REG_QCH_BUSY_FLAG1_PROC1_SHA256_BUS_QCH_BUSY_FLAG1_Msk                               (0x1UL << PCC_REG_QCH_BUSY_FLAG1_PROC1_SHA256_BUS_QCH_BUSY_FLAG1_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG1_PROC1_RNG_BUS_QCH_BUSY_FLAG1_Pos                                  20U
+#define PCC_REG_QCH_BUSY_FLAG1_PROC1_RNG_BUS_QCH_BUSY_FLAG1_Msk                                  (0x1UL << PCC_REG_QCH_BUSY_FLAG1_PROC1_RNG_BUS_QCH_BUSY_FLAG1_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG1_PROC1_RNG_QCH_BUSY_FLAG1_Pos                                      21U
+#define PCC_REG_QCH_BUSY_FLAG1_PROC1_RNG_QCH_BUSY_FLAG1_Msk                                      (0x1UL << PCC_REG_QCH_BUSY_FLAG1_PROC1_RNG_QCH_BUSY_FLAG1_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG1_PROC1_RXI300_QCH_BUSY_FLAG1_Pos                                   22U
+#define PCC_REG_QCH_BUSY_FLAG1_PROC1_RXI300_QCH_BUSY_FLAG1_Msk                                   (0x1UL << PCC_REG_QCH_BUSY_FLAG1_PROC1_RXI300_QCH_BUSY_FLAG1_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG1_PROC1_KEYSCAN_BUS_QCH_BUSY_FLAG1_Pos                              23U
+#define PCC_REG_QCH_BUSY_FLAG1_PROC1_KEYSCAN_BUS_QCH_BUSY_FLAG1_Msk                              (0x1UL << PCC_REG_QCH_BUSY_FLAG1_PROC1_KEYSCAN_BUS_QCH_BUSY_FLAG1_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG1_PROC1_KEYSCAN_QCH_BUSY_FLAG1_Pos                                  24U
+#define PCC_REG_QCH_BUSY_FLAG1_PROC1_KEYSCAN_QCH_BUSY_FLAG1_Msk                                  (0x1UL << PCC_REG_QCH_BUSY_FLAG1_PROC1_KEYSCAN_QCH_BUSY_FLAG1_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG1_PROC1_IRRC_PWR_QCH_BUSY_FLAG1_Pos                                 25U
+#define PCC_REG_QCH_BUSY_FLAG1_PROC1_IRRC_PWR_QCH_BUSY_FLAG1_Msk                                 (0x1UL << PCC_REG_QCH_BUSY_FLAG1_PROC1_IRRC_PWR_QCH_BUSY_FLAG1_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG1_PROC1_IRRC_BUS_QCH_BUSY_FLAG1_Pos                                 26U
+#define PCC_REG_QCH_BUSY_FLAG1_PROC1_IRRC_BUS_QCH_BUSY_FLAG1_Msk                                 (0x1UL << PCC_REG_QCH_BUSY_FLAG1_PROC1_IRRC_BUS_QCH_BUSY_FLAG1_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG1_PROC1_IRRC_QCH_BUSY_FLAG1_Pos                                     27U
+#define PCC_REG_QCH_BUSY_FLAG1_PROC1_IRRC_QCH_BUSY_FLAG1_Msk                                     (0x1UL << PCC_REG_QCH_BUSY_FLAG1_PROC1_IRRC_QCH_BUSY_FLAG1_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG1_PROC1_I2C1_PWR_QCH_BUSY_FLAG1_Pos                                 28U
+#define PCC_REG_QCH_BUSY_FLAG1_PROC1_I2C1_PWR_QCH_BUSY_FLAG1_Msk                                 (0x1UL << PCC_REG_QCH_BUSY_FLAG1_PROC1_I2C1_PWR_QCH_BUSY_FLAG1_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG1_PROC1_I2C1_BUS_QCH_BUSY_FLAG1_Pos                                 29U
+#define PCC_REG_QCH_BUSY_FLAG1_PROC1_I2C1_BUS_QCH_BUSY_FLAG1_Msk                                 (0x1UL << PCC_REG_QCH_BUSY_FLAG1_PROC1_I2C1_BUS_QCH_BUSY_FLAG1_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG1_PROC1_I2C1_QCH_BUSY_FLAG1_Pos                                     30U
+#define PCC_REG_QCH_BUSY_FLAG1_PROC1_I2C1_QCH_BUSY_FLAG1_Msk                                     (0x1UL << PCC_REG_QCH_BUSY_FLAG1_PROC1_I2C1_QCH_BUSY_FLAG1_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG1_PROC1_I2C0_PWR_QCH_BUSY_FLAG1_Pos                                 31U
+#define PCC_REG_QCH_BUSY_FLAG1_PROC1_I2C0_PWR_QCH_BUSY_FLAG1_Msk                                 (0x1UL << PCC_REG_QCH_BUSY_FLAG1_PROC1_I2C0_PWR_QCH_BUSY_FLAG1_Pos)
+
+/* 0x390    0x4000_0390
+    0       R       USB_PWR_QCH_BUSY_FLAG1                          1'b0
+    1       R       USB_BUS_QCH_BUSY_FLAG1                          1'b0
+    2       R       USB_QCH_BUSY_FLAG1                              1'b0
+    3       R       PCSM_VCORE_OP1_QCH_BUSY_FLAG1                   1'b0
+    4       R       VDREG_QCH_BUSY_FLAG1                            1'b0
+    5       R       UART3_PWR_QCH_BUSY_FLAG1                        1'b0
+    6       R       UART3_BUS_QCH_BUSY_FLAG1                        1'b0
+    7       R       UART3_QCH_BUSY_FLAG1                            1'b0
+    8       R       UART2_PWR_QCH_BUSY_FLAG1                        1'b0
+    9       R       UART2_BUS_QCH_BUSY_FLAG1                        1'b0
+    10      R       UART2_QCH_BUSY_FLAG1                            1'b0
+    11      R       UART1_PWR_QCH_BUSY_FLAG1                        1'b0
+    12      R       UART1_BUS_QCH_BUSY_FLAG1                        1'b0
+    13      R       UART1_QCH_BUSY_FLAG1                            1'b0
+    14      R       UART0_PWR_QCH_BUSY_FLAG1                        1'b0
+    15      R       UART0_BUS_QCH_BUSY_FLAG1                        1'b0
+    16      R       UART0_QCH_BUSY_FLAG1                            1'b0
+    17      R       TMETER_BUS_QCH_BUSY_FLAG1                       1'b0
+    18      R       TMETER_QCH_BUSY_FLAG1                           1'b0
+    19      R       TIMER11_PWM_QCH_BUSY_FLAG1                      1'b0
+    20      R       TIMER11_QCH_BUSY_FLAG1                          1'b0
+    21      R       TIMER10_PWM_QCH_BUSY_FLAG1                      1'b0
+    22      R       TIMER10_QCH_BUSY_FLAG1                          1'b0
+    23      R       TIMER9_PCLK_QCH_BUSY_FLAG1                      1'b0
+    24      R       TIMER9_PWM_QCH_BUSY_FLAG1                       1'b0
+    25      R       TIMER9_BUS_QCH_BUSY_FLAG1                       1'b0
+    26      R       TIMER9_QCH_BUSY_FLAG1                           1'b0
+    27      R       TIMER8_QCH_BUSY_FLAG1                           1'b0
+    28      R       TIMER7_QCH_BUSY_FLAG1                           1'b0
+    29      R       TIMER6_QCH_BUSY_FLAG1                           1'b0
+    30      R       TIMER5_QCH_BUSY_FLAG1                           1'b0
+    31      R       TIMER4_QCH_BUSY_FLAG1                           1'b0
+ */
+typedef union _PCC_REG_QCH_BUSY_FLAG1_PROC2_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t USB_PWR_QCH_BUSY_FLAG1: 1;
+        uint32_t USB_BUS_QCH_BUSY_FLAG1: 1;
+        uint32_t USB_QCH_BUSY_FLAG1: 1;
+        uint32_t PCSM_VCORE_OP1_QCH_BUSY_FLAG1: 1;
+        uint32_t VDREG_QCH_BUSY_FLAG1: 1;
+        uint32_t UART3_PWR_QCH_BUSY_FLAG1: 1;
+        uint32_t UART3_BUS_QCH_BUSY_FLAG1: 1;
+        uint32_t UART3_QCH_BUSY_FLAG1: 1;
+        uint32_t UART2_PWR_QCH_BUSY_FLAG1: 1;
+        uint32_t UART2_BUS_QCH_BUSY_FLAG1: 1;
+        uint32_t UART2_QCH_BUSY_FLAG1: 1;
+        uint32_t UART1_PWR_QCH_BUSY_FLAG1: 1;
+        uint32_t UART1_BUS_QCH_BUSY_FLAG1: 1;
+        uint32_t UART1_QCH_BUSY_FLAG1: 1;
+        uint32_t UART0_PWR_QCH_BUSY_FLAG1: 1;
+        uint32_t UART0_BUS_QCH_BUSY_FLAG1: 1;
+        uint32_t UART0_QCH_BUSY_FLAG1: 1;
+        uint32_t TMETER_BUS_QCH_BUSY_FLAG1: 1;
+        uint32_t TMETER_QCH_BUSY_FLAG1: 1;
+        uint32_t TIMER11_PWM_QCH_BUSY_FLAG1: 1;
+        uint32_t TIMER11_QCH_BUSY_FLAG1: 1;
+        uint32_t TIMER10_PWM_QCH_BUSY_FLAG1: 1;
+        uint32_t TIMER10_QCH_BUSY_FLAG1: 1;
+        uint32_t TIMER9_PCLK_QCH_BUSY_FLAG1: 1;
+        uint32_t TIMER9_PWM_QCH_BUSY_FLAG1: 1;
+        uint32_t TIMER9_BUS_QCH_BUSY_FLAG1: 1;
+        uint32_t TIMER9_QCH_BUSY_FLAG1: 1;
+        uint32_t TIMER8_QCH_BUSY_FLAG1: 1;
+        uint32_t TIMER7_QCH_BUSY_FLAG1: 1;
+        uint32_t TIMER6_QCH_BUSY_FLAG1: 1;
+        uint32_t TIMER5_QCH_BUSY_FLAG1: 1;
+        uint32_t TIMER4_QCH_BUSY_FLAG1: 1;
+    };
+} PCC_REG_QCH_BUSY_FLAG1_PROC2_TYPE;
+
+/*0x4000_0390 PCC_REG_QCH_BUSY_FLAG1_PROC2*/
+#define PCC_REG_QCH_BUSY_FLAG1_PROC2_USB_PWR_QCH_BUSY_FLAG1_Pos                                  0U
+#define PCC_REG_QCH_BUSY_FLAG1_PROC2_USB_PWR_QCH_BUSY_FLAG1_Msk                                  (0x1UL << PCC_REG_QCH_BUSY_FLAG1_PROC2_USB_PWR_QCH_BUSY_FLAG1_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG1_PROC2_USB_BUS_QCH_BUSY_FLAG1_Pos                                  1U
+#define PCC_REG_QCH_BUSY_FLAG1_PROC2_USB_BUS_QCH_BUSY_FLAG1_Msk                                  (0x1UL << PCC_REG_QCH_BUSY_FLAG1_PROC2_USB_BUS_QCH_BUSY_FLAG1_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG1_PROC2_USB_QCH_BUSY_FLAG1_Pos                                      2U
+#define PCC_REG_QCH_BUSY_FLAG1_PROC2_USB_QCH_BUSY_FLAG1_Msk                                      (0x1UL << PCC_REG_QCH_BUSY_FLAG1_PROC2_USB_QCH_BUSY_FLAG1_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG1_PROC2_PCSM_VCORE_OP1_QCH_BUSY_FLAG1_Pos                           3U
+#define PCC_REG_QCH_BUSY_FLAG1_PROC2_PCSM_VCORE_OP1_QCH_BUSY_FLAG1_Msk                           (0x1UL << PCC_REG_QCH_BUSY_FLAG1_PROC2_PCSM_VCORE_OP1_QCH_BUSY_FLAG1_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG1_PROC2_VDREG_QCH_BUSY_FLAG1_Pos                                    4U
+#define PCC_REG_QCH_BUSY_FLAG1_PROC2_VDREG_QCH_BUSY_FLAG1_Msk                                    (0x1UL << PCC_REG_QCH_BUSY_FLAG1_PROC2_VDREG_QCH_BUSY_FLAG1_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG1_PROC2_UART3_PWR_QCH_BUSY_FLAG1_Pos                                5U
+#define PCC_REG_QCH_BUSY_FLAG1_PROC2_UART3_PWR_QCH_BUSY_FLAG1_Msk                                (0x1UL << PCC_REG_QCH_BUSY_FLAG1_PROC2_UART3_PWR_QCH_BUSY_FLAG1_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG1_PROC2_UART3_BUS_QCH_BUSY_FLAG1_Pos                                6U
+#define PCC_REG_QCH_BUSY_FLAG1_PROC2_UART3_BUS_QCH_BUSY_FLAG1_Msk                                (0x1UL << PCC_REG_QCH_BUSY_FLAG1_PROC2_UART3_BUS_QCH_BUSY_FLAG1_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG1_PROC2_UART3_QCH_BUSY_FLAG1_Pos                                    7U
+#define PCC_REG_QCH_BUSY_FLAG1_PROC2_UART3_QCH_BUSY_FLAG1_Msk                                    (0x1UL << PCC_REG_QCH_BUSY_FLAG1_PROC2_UART3_QCH_BUSY_FLAG1_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG1_PROC2_UART2_PWR_QCH_BUSY_FLAG1_Pos                                8U
+#define PCC_REG_QCH_BUSY_FLAG1_PROC2_UART2_PWR_QCH_BUSY_FLAG1_Msk                                (0x1UL << PCC_REG_QCH_BUSY_FLAG1_PROC2_UART2_PWR_QCH_BUSY_FLAG1_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG1_PROC2_UART2_BUS_QCH_BUSY_FLAG1_Pos                                9U
+#define PCC_REG_QCH_BUSY_FLAG1_PROC2_UART2_BUS_QCH_BUSY_FLAG1_Msk                                (0x1UL << PCC_REG_QCH_BUSY_FLAG1_PROC2_UART2_BUS_QCH_BUSY_FLAG1_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG1_PROC2_UART2_QCH_BUSY_FLAG1_Pos                                    10U
+#define PCC_REG_QCH_BUSY_FLAG1_PROC2_UART2_QCH_BUSY_FLAG1_Msk                                    (0x1UL << PCC_REG_QCH_BUSY_FLAG1_PROC2_UART2_QCH_BUSY_FLAG1_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG1_PROC2_UART1_PWR_QCH_BUSY_FLAG1_Pos                                11U
+#define PCC_REG_QCH_BUSY_FLAG1_PROC2_UART1_PWR_QCH_BUSY_FLAG1_Msk                                (0x1UL << PCC_REG_QCH_BUSY_FLAG1_PROC2_UART1_PWR_QCH_BUSY_FLAG1_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG1_PROC2_UART1_BUS_QCH_BUSY_FLAG1_Pos                                12U
+#define PCC_REG_QCH_BUSY_FLAG1_PROC2_UART1_BUS_QCH_BUSY_FLAG1_Msk                                (0x1UL << PCC_REG_QCH_BUSY_FLAG1_PROC2_UART1_BUS_QCH_BUSY_FLAG1_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG1_PROC2_UART1_QCH_BUSY_FLAG1_Pos                                    13U
+#define PCC_REG_QCH_BUSY_FLAG1_PROC2_UART1_QCH_BUSY_FLAG1_Msk                                    (0x1UL << PCC_REG_QCH_BUSY_FLAG1_PROC2_UART1_QCH_BUSY_FLAG1_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG1_PROC2_UART0_PWR_QCH_BUSY_FLAG1_Pos                                14U
+#define PCC_REG_QCH_BUSY_FLAG1_PROC2_UART0_PWR_QCH_BUSY_FLAG1_Msk                                (0x1UL << PCC_REG_QCH_BUSY_FLAG1_PROC2_UART0_PWR_QCH_BUSY_FLAG1_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG1_PROC2_UART0_BUS_QCH_BUSY_FLAG1_Pos                                15U
+#define PCC_REG_QCH_BUSY_FLAG1_PROC2_UART0_BUS_QCH_BUSY_FLAG1_Msk                                (0x1UL << PCC_REG_QCH_BUSY_FLAG1_PROC2_UART0_BUS_QCH_BUSY_FLAG1_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG1_PROC2_UART0_QCH_BUSY_FLAG1_Pos                                    16U
+#define PCC_REG_QCH_BUSY_FLAG1_PROC2_UART0_QCH_BUSY_FLAG1_Msk                                    (0x1UL << PCC_REG_QCH_BUSY_FLAG1_PROC2_UART0_QCH_BUSY_FLAG1_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG1_PROC2_TMETER_BUS_QCH_BUSY_FLAG1_Pos                               17U
+#define PCC_REG_QCH_BUSY_FLAG1_PROC2_TMETER_BUS_QCH_BUSY_FLAG1_Msk                               (0x1UL << PCC_REG_QCH_BUSY_FLAG1_PROC2_TMETER_BUS_QCH_BUSY_FLAG1_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG1_PROC2_TMETER_QCH_BUSY_FLAG1_Pos                                   18U
+#define PCC_REG_QCH_BUSY_FLAG1_PROC2_TMETER_QCH_BUSY_FLAG1_Msk                                   (0x1UL << PCC_REG_QCH_BUSY_FLAG1_PROC2_TMETER_QCH_BUSY_FLAG1_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG1_PROC2_TIMER11_PWM_QCH_BUSY_FLAG1_Pos                              19U
+#define PCC_REG_QCH_BUSY_FLAG1_PROC2_TIMER11_PWM_QCH_BUSY_FLAG1_Msk                              (0x1UL << PCC_REG_QCH_BUSY_FLAG1_PROC2_TIMER11_PWM_QCH_BUSY_FLAG1_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG1_PROC2_TIMER11_QCH_BUSY_FLAG1_Pos                                  20U
+#define PCC_REG_QCH_BUSY_FLAG1_PROC2_TIMER11_QCH_BUSY_FLAG1_Msk                                  (0x1UL << PCC_REG_QCH_BUSY_FLAG1_PROC2_TIMER11_QCH_BUSY_FLAG1_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG1_PROC2_TIMER10_PWM_QCH_BUSY_FLAG1_Pos                              21U
+#define PCC_REG_QCH_BUSY_FLAG1_PROC2_TIMER10_PWM_QCH_BUSY_FLAG1_Msk                              (0x1UL << PCC_REG_QCH_BUSY_FLAG1_PROC2_TIMER10_PWM_QCH_BUSY_FLAG1_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG1_PROC2_TIMER10_QCH_BUSY_FLAG1_Pos                                  22U
+#define PCC_REG_QCH_BUSY_FLAG1_PROC2_TIMER10_QCH_BUSY_FLAG1_Msk                                  (0x1UL << PCC_REG_QCH_BUSY_FLAG1_PROC2_TIMER10_QCH_BUSY_FLAG1_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG1_PROC2_TIMER9_PCLK_QCH_BUSY_FLAG1_Pos                              23U
+#define PCC_REG_QCH_BUSY_FLAG1_PROC2_TIMER9_PCLK_QCH_BUSY_FLAG1_Msk                              (0x1UL << PCC_REG_QCH_BUSY_FLAG1_PROC2_TIMER9_PCLK_QCH_BUSY_FLAG1_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG1_PROC2_TIMER9_PWM_QCH_BUSY_FLAG1_Pos                               24U
+#define PCC_REG_QCH_BUSY_FLAG1_PROC2_TIMER9_PWM_QCH_BUSY_FLAG1_Msk                               (0x1UL << PCC_REG_QCH_BUSY_FLAG1_PROC2_TIMER9_PWM_QCH_BUSY_FLAG1_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG1_PROC2_TIMER9_BUS_QCH_BUSY_FLAG1_Pos                               25U
+#define PCC_REG_QCH_BUSY_FLAG1_PROC2_TIMER9_BUS_QCH_BUSY_FLAG1_Msk                               (0x1UL << PCC_REG_QCH_BUSY_FLAG1_PROC2_TIMER9_BUS_QCH_BUSY_FLAG1_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG1_PROC2_TIMER9_QCH_BUSY_FLAG1_Pos                                   26U
+#define PCC_REG_QCH_BUSY_FLAG1_PROC2_TIMER9_QCH_BUSY_FLAG1_Msk                                   (0x1UL << PCC_REG_QCH_BUSY_FLAG1_PROC2_TIMER9_QCH_BUSY_FLAG1_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG1_PROC2_TIMER8_QCH_BUSY_FLAG1_Pos                                   27U
+#define PCC_REG_QCH_BUSY_FLAG1_PROC2_TIMER8_QCH_BUSY_FLAG1_Msk                                   (0x1UL << PCC_REG_QCH_BUSY_FLAG1_PROC2_TIMER8_QCH_BUSY_FLAG1_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG1_PROC2_TIMER7_QCH_BUSY_FLAG1_Pos                                   28U
+#define PCC_REG_QCH_BUSY_FLAG1_PROC2_TIMER7_QCH_BUSY_FLAG1_Msk                                   (0x1UL << PCC_REG_QCH_BUSY_FLAG1_PROC2_TIMER7_QCH_BUSY_FLAG1_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG1_PROC2_TIMER6_QCH_BUSY_FLAG1_Pos                                   29U
+#define PCC_REG_QCH_BUSY_FLAG1_PROC2_TIMER6_QCH_BUSY_FLAG1_Msk                                   (0x1UL << PCC_REG_QCH_BUSY_FLAG1_PROC2_TIMER6_QCH_BUSY_FLAG1_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG1_PROC2_TIMER5_QCH_BUSY_FLAG1_Pos                                   30U
+#define PCC_REG_QCH_BUSY_FLAG1_PROC2_TIMER5_QCH_BUSY_FLAG1_Msk                                   (0x1UL << PCC_REG_QCH_BUSY_FLAG1_PROC2_TIMER5_QCH_BUSY_FLAG1_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG1_PROC2_TIMER4_QCH_BUSY_FLAG1_Pos                                   31U
+#define PCC_REG_QCH_BUSY_FLAG1_PROC2_TIMER4_QCH_BUSY_FLAG1_Msk                                   (0x1UL << PCC_REG_QCH_BUSY_FLAG1_PROC2_TIMER4_QCH_BUSY_FLAG1_Pos)
+
+/* 0x394    0x4000_0394
+    0       R       I2C0_BUS_QCH_BUSY_FLAG0                         1'b1
+    1       R       I2C0_QCH_BUSY_FLAG0                             1'b1
+    2       R       GPIO_DBNC_QCH_BUSY_FLAG0                        1'b1
+    3       R       GPIO_BUS_QCH_BUSY_FLAG0                         1'b1
+    4       R       GPIO_QCH_BUSY_FLAG0                             1'b1
+    5       R       GDMA_BUS_QCH_BUSY_FLAG0                         1'b1
+    6       R       ETIMER_PCLK_QCH_BUSY_FLAG0                      1'b1
+    7       R       ETIMER_PWM_QCH_BUSY_FLAG0                       1'b1
+    8       R       ETIMER_BUS_QCH_BUSY_FLAG0                       1'b1
+    9       R       ETIMER_QCH_BUSY_FLAG0                           1'b1
+    10      R       EFLASH_BUS_QCH_BUSY_FLAG0                       1'b1
+    11      R       EFLASH_QCH_BUSY_FLAG0                           1'b1
+    12      R       CPU_BUS_QCH_BUSY_FLAG0                          1'b1
+    13      R       CAN_LP_QCH_BUSY_FLAG0                           1'b1
+    14      R       CAN_BUS_QCH_BUSY_FLAG0                          1'b1
+    15      R       CAN_PWR_QCH_BUSY_FLAG0                          1'b1
+    16      R       CAN_QCH_BUSY_FLAG0                              1'b1
+    17      R       AES_QCH_BUSY_FLAG0                              1'b1
+    31:18   R       RESERVED                                        14'd0
+ */
+typedef union _PCC_REG_QCH_BUSY_FLAG0_PROC0_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t I2C0_BUS_QCH_BUSY_FLAG0: 1;
+        uint32_t I2C0_QCH_BUSY_FLAG0: 1;
+        uint32_t GPIO_DBNC_QCH_BUSY_FLAG0: 1;
+        uint32_t GPIO_BUS_QCH_BUSY_FLAG0: 1;
+        uint32_t GPIO_QCH_BUSY_FLAG0: 1;
+        uint32_t GDMA_BUS_QCH_BUSY_FLAG0: 1;
+        uint32_t ETIMER_PCLK_QCH_BUSY_FLAG0: 1;
+        uint32_t ETIMER_PWM_QCH_BUSY_FLAG0: 1;
+        uint32_t ETIMER_BUS_QCH_BUSY_FLAG0: 1;
+        uint32_t ETIMER_QCH_BUSY_FLAG0: 1;
+        uint32_t EFLASH_BUS_QCH_BUSY_FLAG0: 1;
+        uint32_t EFLASH_QCH_BUSY_FLAG0: 1;
+        uint32_t CPU_BUS_QCH_BUSY_FLAG0: 1;
+        uint32_t CAN_LP_QCH_BUSY_FLAG0: 1;
+        uint32_t CAN_BUS_QCH_BUSY_FLAG0: 1;
+        uint32_t CAN_PWR_QCH_BUSY_FLAG0: 1;
+        uint32_t CAN_QCH_BUSY_FLAG0: 1;
+        uint32_t AES_QCH_BUSY_FLAG0: 1;
+        uint32_t RESERVED: 14;
+    };
+} PCC_REG_QCH_BUSY_FLAG0_PROC0_TYPE;
+
+/*0x4000_0394 PCC_REG_QCH_BUSY_FLAG0_PROC0*/
+#define PCC_REG_QCH_BUSY_FLAG0_PROC0_I2C0_BUS_QCH_BUSY_FLAG0_Pos                                 0U
+#define PCC_REG_QCH_BUSY_FLAG0_PROC0_I2C0_BUS_QCH_BUSY_FLAG0_Msk                                 (0x1UL << PCC_REG_QCH_BUSY_FLAG0_PROC0_I2C0_BUS_QCH_BUSY_FLAG0_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG0_PROC0_I2C0_QCH_BUSY_FLAG0_Pos                                     1U
+#define PCC_REG_QCH_BUSY_FLAG0_PROC0_I2C0_QCH_BUSY_FLAG0_Msk                                     (0x1UL << PCC_REG_QCH_BUSY_FLAG0_PROC0_I2C0_QCH_BUSY_FLAG0_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG0_PROC0_GPIO_DBNC_QCH_BUSY_FLAG0_Pos                                2U
+#define PCC_REG_QCH_BUSY_FLAG0_PROC0_GPIO_DBNC_QCH_BUSY_FLAG0_Msk                                (0x1UL << PCC_REG_QCH_BUSY_FLAG0_PROC0_GPIO_DBNC_QCH_BUSY_FLAG0_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG0_PROC0_GPIO_BUS_QCH_BUSY_FLAG0_Pos                                 3U
+#define PCC_REG_QCH_BUSY_FLAG0_PROC0_GPIO_BUS_QCH_BUSY_FLAG0_Msk                                 (0x1UL << PCC_REG_QCH_BUSY_FLAG0_PROC0_GPIO_BUS_QCH_BUSY_FLAG0_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG0_PROC0_GPIO_QCH_BUSY_FLAG0_Pos                                     4U
+#define PCC_REG_QCH_BUSY_FLAG0_PROC0_GPIO_QCH_BUSY_FLAG0_Msk                                     (0x1UL << PCC_REG_QCH_BUSY_FLAG0_PROC0_GPIO_QCH_BUSY_FLAG0_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG0_PROC0_GDMA_BUS_QCH_BUSY_FLAG0_Pos                                 5U
+#define PCC_REG_QCH_BUSY_FLAG0_PROC0_GDMA_BUS_QCH_BUSY_FLAG0_Msk                                 (0x1UL << PCC_REG_QCH_BUSY_FLAG0_PROC0_GDMA_BUS_QCH_BUSY_FLAG0_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG0_PROC0_ETIMER_PCLK_QCH_BUSY_FLAG0_Pos                              6U
+#define PCC_REG_QCH_BUSY_FLAG0_PROC0_ETIMER_PCLK_QCH_BUSY_FLAG0_Msk                              (0x1UL << PCC_REG_QCH_BUSY_FLAG0_PROC0_ETIMER_PCLK_QCH_BUSY_FLAG0_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG0_PROC0_ETIMER_PWM_QCH_BUSY_FLAG0_Pos                               7U
+#define PCC_REG_QCH_BUSY_FLAG0_PROC0_ETIMER_PWM_QCH_BUSY_FLAG0_Msk                               (0x1UL << PCC_REG_QCH_BUSY_FLAG0_PROC0_ETIMER_PWM_QCH_BUSY_FLAG0_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG0_PROC0_ETIMER_BUS_QCH_BUSY_FLAG0_Pos                               8U
+#define PCC_REG_QCH_BUSY_FLAG0_PROC0_ETIMER_BUS_QCH_BUSY_FLAG0_Msk                               (0x1UL << PCC_REG_QCH_BUSY_FLAG0_PROC0_ETIMER_BUS_QCH_BUSY_FLAG0_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG0_PROC0_ETIMER_QCH_BUSY_FLAG0_Pos                                   9U
+#define PCC_REG_QCH_BUSY_FLAG0_PROC0_ETIMER_QCH_BUSY_FLAG0_Msk                                   (0x1UL << PCC_REG_QCH_BUSY_FLAG0_PROC0_ETIMER_QCH_BUSY_FLAG0_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG0_PROC0_EFLASH_BUS_QCH_BUSY_FLAG0_Pos                               10U
+#define PCC_REG_QCH_BUSY_FLAG0_PROC0_EFLASH_BUS_QCH_BUSY_FLAG0_Msk                               (0x1UL << PCC_REG_QCH_BUSY_FLAG0_PROC0_EFLASH_BUS_QCH_BUSY_FLAG0_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG0_PROC0_EFLASH_QCH_BUSY_FLAG0_Pos                                   11U
+#define PCC_REG_QCH_BUSY_FLAG0_PROC0_EFLASH_QCH_BUSY_FLAG0_Msk                                   (0x1UL << PCC_REG_QCH_BUSY_FLAG0_PROC0_EFLASH_QCH_BUSY_FLAG0_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG0_PROC0_CPU_BUS_QCH_BUSY_FLAG0_Pos                                  12U
+#define PCC_REG_QCH_BUSY_FLAG0_PROC0_CPU_BUS_QCH_BUSY_FLAG0_Msk                                  (0x1UL << PCC_REG_QCH_BUSY_FLAG0_PROC0_CPU_BUS_QCH_BUSY_FLAG0_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG0_PROC0_CAN_LP_QCH_BUSY_FLAG0_Pos                                   13U
+#define PCC_REG_QCH_BUSY_FLAG0_PROC0_CAN_LP_QCH_BUSY_FLAG0_Msk                                   (0x1UL << PCC_REG_QCH_BUSY_FLAG0_PROC0_CAN_LP_QCH_BUSY_FLAG0_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG0_PROC0_CAN_BUS_QCH_BUSY_FLAG0_Pos                                  14U
+#define PCC_REG_QCH_BUSY_FLAG0_PROC0_CAN_BUS_QCH_BUSY_FLAG0_Msk                                  (0x1UL << PCC_REG_QCH_BUSY_FLAG0_PROC0_CAN_BUS_QCH_BUSY_FLAG0_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG0_PROC0_CAN_PWR_QCH_BUSY_FLAG0_Pos                                  15U
+#define PCC_REG_QCH_BUSY_FLAG0_PROC0_CAN_PWR_QCH_BUSY_FLAG0_Msk                                  (0x1UL << PCC_REG_QCH_BUSY_FLAG0_PROC0_CAN_PWR_QCH_BUSY_FLAG0_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG0_PROC0_CAN_QCH_BUSY_FLAG0_Pos                                      16U
+#define PCC_REG_QCH_BUSY_FLAG0_PROC0_CAN_QCH_BUSY_FLAG0_Msk                                      (0x1UL << PCC_REG_QCH_BUSY_FLAG0_PROC0_CAN_QCH_BUSY_FLAG0_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG0_PROC0_AES_QCH_BUSY_FLAG0_Pos                                      17U
+#define PCC_REG_QCH_BUSY_FLAG0_PROC0_AES_QCH_BUSY_FLAG0_Msk                                      (0x1UL << PCC_REG_QCH_BUSY_FLAG0_PROC0_AES_QCH_BUSY_FLAG0_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG0_PROC0_RESERVED_Pos                                                18U
+#define PCC_REG_QCH_BUSY_FLAG0_PROC0_RESERVED_Msk                                                (0x3FFFUL << PCC_REG_QCH_BUSY_FLAG0_PROC0_RESERVED_Pos)
+
+/* 0x398    0x4000_0398
+    0       R       TIMER3_QCH_BUSY_FLAG0                           1'b1
+    1       R       TIMER2_QCH_BUSY_FLAG0                           1'b1
+    2       R       TIMER1_PCLK_QCH_BUSY_FLAG0                      1'b1
+    3       R       TIMER1_BUS_QCH_BUSY_FLAG0                       1'b1
+    4       R       TIMER1_QCH_BUSY_FLAG0                           1'b1
+    5       R       SPIC0_QCH_BUSY_FLAG0                            1'b1
+    6       R       SPI3W_BUS_QCH_BUSY_FLAG0                        1'b1
+    7       R       SPI3W_QCH_BUSY_FLAG0                            1'b1
+    8       R       SPI2_PWR_QCH_BUSY_FLAG0                         1'b1
+    9       R       SPI2_BUS_QCH_BUSY_FLAG0                         1'b1
+    10      R       SPI2_QCH_BUSY_FLAG0                             1'b1
+    11      R       SPI1_HS_BUS_QCH_BUSY_FLAG0                      1'b1
+    12      R       SPI1_PWR_QCH_BUSY_FLAG0                         1'b1
+    13      R       SPI1_BUS_QCH_BUSY_FLAG0                         1'b1
+    14      R       SPI1_QCH_BUSY_FLAG0                             1'b1
+    15      R       SPI0_HS_BUS_QCH_BUSY_FLAG0                      1'b1
+    16      R       SPI0_PWR_QCH_BUSY_FLAG0                         1'b1
+    17      R       SPI0_BUS_QCH_BUSY_FLAG0                         1'b1
+    18      R       SPI0_QCH_BUSY_FLAG0                             1'b1
+    19      R       SHA256_BUS_QCH_BUSY_FLAG0                       1'b1
+    20      R       RNG_BUS_QCH_BUSY_FLAG0                          1'b1
+    21      R       RNG_QCH_BUSY_FLAG0                              1'b1
+    22      R       RXI300_QCH_BUSY_FLAG0                           1'b1
+    23      R       KEYSCAN_BUS_QCH_BUSY_FLAG0                      1'b1
+    24      R       KEYSCAN_QCH_BUSY_FLAG0                          1'b1
+    25      R       IRRC_PWR_QCH_BUSY_FLAG0                         1'b1
+    26      R       IRRC_BUS_QCH_BUSY_FLAG0                         1'b1
+    27      R       IRRC_QCH_BUSY_FLAG0                             1'b1
+    28      R       I2C1_PWR_QCH_BUSY_FLAG0                         1'b1
+    29      R       I2C1_BUS_QCH_BUSY_FLAG0                         1'b1
+    30      R       I2C1_QCH_BUSY_FLAG0                             1'b1
+    31      R       I2C0_PWR_QCH_BUSY_FLAG0                         1'b1
+ */
+typedef union _PCC_REG_QCH_BUSY_FLAG0_PROC1_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t TIMER3_QCH_BUSY_FLAG0: 1;
+        uint32_t TIMER2_QCH_BUSY_FLAG0: 1;
+        uint32_t TIMER1_PCLK_QCH_BUSY_FLAG0: 1;
+        uint32_t TIMER1_BUS_QCH_BUSY_FLAG0: 1;
+        uint32_t TIMER1_QCH_BUSY_FLAG0: 1;
+        uint32_t SPIC0_QCH_BUSY_FLAG0: 1;
+        uint32_t SPI3W_BUS_QCH_BUSY_FLAG0: 1;
+        uint32_t SPI3W_QCH_BUSY_FLAG0: 1;
+        uint32_t SPI2_PWR_QCH_BUSY_FLAG0: 1;
+        uint32_t SPI2_BUS_QCH_BUSY_FLAG0: 1;
+        uint32_t SPI2_QCH_BUSY_FLAG0: 1;
+        uint32_t SPI1_HS_BUS_QCH_BUSY_FLAG0: 1;
+        uint32_t SPI1_PWR_QCH_BUSY_FLAG0: 1;
+        uint32_t SPI1_BUS_QCH_BUSY_FLAG0: 1;
+        uint32_t SPI1_QCH_BUSY_FLAG0: 1;
+        uint32_t SPI0_HS_BUS_QCH_BUSY_FLAG0: 1;
+        uint32_t SPI0_PWR_QCH_BUSY_FLAG0: 1;
+        uint32_t SPI0_BUS_QCH_BUSY_FLAG0: 1;
+        uint32_t SPI0_QCH_BUSY_FLAG0: 1;
+        uint32_t SHA256_BUS_QCH_BUSY_FLAG0: 1;
+        uint32_t RNG_BUS_QCH_BUSY_FLAG0: 1;
+        uint32_t RNG_QCH_BUSY_FLAG0: 1;
+        uint32_t RXI300_QCH_BUSY_FLAG0: 1;
+        uint32_t KEYSCAN_BUS_QCH_BUSY_FLAG0: 1;
+        uint32_t KEYSCAN_QCH_BUSY_FLAG0: 1;
+        uint32_t IRRC_PWR_QCH_BUSY_FLAG0: 1;
+        uint32_t IRRC_BUS_QCH_BUSY_FLAG0: 1;
+        uint32_t IRRC_QCH_BUSY_FLAG0: 1;
+        uint32_t I2C1_PWR_QCH_BUSY_FLAG0: 1;
+        uint32_t I2C1_BUS_QCH_BUSY_FLAG0: 1;
+        uint32_t I2C1_QCH_BUSY_FLAG0: 1;
+        uint32_t I2C0_PWR_QCH_BUSY_FLAG0: 1;
+    };
+} PCC_REG_QCH_BUSY_FLAG0_PROC1_TYPE;
+
+/*0x4000_0398 PCC_REG_QCH_BUSY_FLAG0_PROC1*/
+#define PCC_REG_QCH_BUSY_FLAG0_PROC1_TIMER3_QCH_BUSY_FLAG0_Pos                                   0U
+#define PCC_REG_QCH_BUSY_FLAG0_PROC1_TIMER3_QCH_BUSY_FLAG0_Msk                                   (0x1UL << PCC_REG_QCH_BUSY_FLAG0_PROC1_TIMER3_QCH_BUSY_FLAG0_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG0_PROC1_TIMER2_QCH_BUSY_FLAG0_Pos                                   1U
+#define PCC_REG_QCH_BUSY_FLAG0_PROC1_TIMER2_QCH_BUSY_FLAG0_Msk                                   (0x1UL << PCC_REG_QCH_BUSY_FLAG0_PROC1_TIMER2_QCH_BUSY_FLAG0_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG0_PROC1_TIMER1_PCLK_QCH_BUSY_FLAG0_Pos                              2U
+#define PCC_REG_QCH_BUSY_FLAG0_PROC1_TIMER1_PCLK_QCH_BUSY_FLAG0_Msk                              (0x1UL << PCC_REG_QCH_BUSY_FLAG0_PROC1_TIMER1_PCLK_QCH_BUSY_FLAG0_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG0_PROC1_TIMER1_BUS_QCH_BUSY_FLAG0_Pos                               3U
+#define PCC_REG_QCH_BUSY_FLAG0_PROC1_TIMER1_BUS_QCH_BUSY_FLAG0_Msk                               (0x1UL << PCC_REG_QCH_BUSY_FLAG0_PROC1_TIMER1_BUS_QCH_BUSY_FLAG0_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG0_PROC1_TIMER1_QCH_BUSY_FLAG0_Pos                                   4U
+#define PCC_REG_QCH_BUSY_FLAG0_PROC1_TIMER1_QCH_BUSY_FLAG0_Msk                                   (0x1UL << PCC_REG_QCH_BUSY_FLAG0_PROC1_TIMER1_QCH_BUSY_FLAG0_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG0_PROC1_SPIC0_QCH_BUSY_FLAG0_Pos                                    5U
+#define PCC_REG_QCH_BUSY_FLAG0_PROC1_SPIC0_QCH_BUSY_FLAG0_Msk                                    (0x1UL << PCC_REG_QCH_BUSY_FLAG0_PROC1_SPIC0_QCH_BUSY_FLAG0_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG0_PROC1_SPI3W_BUS_QCH_BUSY_FLAG0_Pos                                6U
+#define PCC_REG_QCH_BUSY_FLAG0_PROC1_SPI3W_BUS_QCH_BUSY_FLAG0_Msk                                (0x1UL << PCC_REG_QCH_BUSY_FLAG0_PROC1_SPI3W_BUS_QCH_BUSY_FLAG0_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG0_PROC1_SPI3W_QCH_BUSY_FLAG0_Pos                                    7U
+#define PCC_REG_QCH_BUSY_FLAG0_PROC1_SPI3W_QCH_BUSY_FLAG0_Msk                                    (0x1UL << PCC_REG_QCH_BUSY_FLAG0_PROC1_SPI3W_QCH_BUSY_FLAG0_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG0_PROC1_SPI2_PWR_QCH_BUSY_FLAG0_Pos                                 8U
+#define PCC_REG_QCH_BUSY_FLAG0_PROC1_SPI2_PWR_QCH_BUSY_FLAG0_Msk                                 (0x1UL << PCC_REG_QCH_BUSY_FLAG0_PROC1_SPI2_PWR_QCH_BUSY_FLAG0_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG0_PROC1_SPI2_BUS_QCH_BUSY_FLAG0_Pos                                 9U
+#define PCC_REG_QCH_BUSY_FLAG0_PROC1_SPI2_BUS_QCH_BUSY_FLAG0_Msk                                 (0x1UL << PCC_REG_QCH_BUSY_FLAG0_PROC1_SPI2_BUS_QCH_BUSY_FLAG0_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG0_PROC1_SPI2_QCH_BUSY_FLAG0_Pos                                     10U
+#define PCC_REG_QCH_BUSY_FLAG0_PROC1_SPI2_QCH_BUSY_FLAG0_Msk                                     (0x1UL << PCC_REG_QCH_BUSY_FLAG0_PROC1_SPI2_QCH_BUSY_FLAG0_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG0_PROC1_SPI1_HS_BUS_QCH_BUSY_FLAG0_Pos                              11U
+#define PCC_REG_QCH_BUSY_FLAG0_PROC1_SPI1_HS_BUS_QCH_BUSY_FLAG0_Msk                              (0x1UL << PCC_REG_QCH_BUSY_FLAG0_PROC1_SPI1_HS_BUS_QCH_BUSY_FLAG0_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG0_PROC1_SPI1_PWR_QCH_BUSY_FLAG0_Pos                                 12U
+#define PCC_REG_QCH_BUSY_FLAG0_PROC1_SPI1_PWR_QCH_BUSY_FLAG0_Msk                                 (0x1UL << PCC_REG_QCH_BUSY_FLAG0_PROC1_SPI1_PWR_QCH_BUSY_FLAG0_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG0_PROC1_SPI1_BUS_QCH_BUSY_FLAG0_Pos                                 13U
+#define PCC_REG_QCH_BUSY_FLAG0_PROC1_SPI1_BUS_QCH_BUSY_FLAG0_Msk                                 (0x1UL << PCC_REG_QCH_BUSY_FLAG0_PROC1_SPI1_BUS_QCH_BUSY_FLAG0_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG0_PROC1_SPI1_QCH_BUSY_FLAG0_Pos                                     14U
+#define PCC_REG_QCH_BUSY_FLAG0_PROC1_SPI1_QCH_BUSY_FLAG0_Msk                                     (0x1UL << PCC_REG_QCH_BUSY_FLAG0_PROC1_SPI1_QCH_BUSY_FLAG0_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG0_PROC1_SPI0_HS_BUS_QCH_BUSY_FLAG0_Pos                              15U
+#define PCC_REG_QCH_BUSY_FLAG0_PROC1_SPI0_HS_BUS_QCH_BUSY_FLAG0_Msk                              (0x1UL << PCC_REG_QCH_BUSY_FLAG0_PROC1_SPI0_HS_BUS_QCH_BUSY_FLAG0_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG0_PROC1_SPI0_PWR_QCH_BUSY_FLAG0_Pos                                 16U
+#define PCC_REG_QCH_BUSY_FLAG0_PROC1_SPI0_PWR_QCH_BUSY_FLAG0_Msk                                 (0x1UL << PCC_REG_QCH_BUSY_FLAG0_PROC1_SPI0_PWR_QCH_BUSY_FLAG0_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG0_PROC1_SPI0_BUS_QCH_BUSY_FLAG0_Pos                                 17U
+#define PCC_REG_QCH_BUSY_FLAG0_PROC1_SPI0_BUS_QCH_BUSY_FLAG0_Msk                                 (0x1UL << PCC_REG_QCH_BUSY_FLAG0_PROC1_SPI0_BUS_QCH_BUSY_FLAG0_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG0_PROC1_SPI0_QCH_BUSY_FLAG0_Pos                                     18U
+#define PCC_REG_QCH_BUSY_FLAG0_PROC1_SPI0_QCH_BUSY_FLAG0_Msk                                     (0x1UL << PCC_REG_QCH_BUSY_FLAG0_PROC1_SPI0_QCH_BUSY_FLAG0_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG0_PROC1_SHA256_BUS_QCH_BUSY_FLAG0_Pos                               19U
+#define PCC_REG_QCH_BUSY_FLAG0_PROC1_SHA256_BUS_QCH_BUSY_FLAG0_Msk                               (0x1UL << PCC_REG_QCH_BUSY_FLAG0_PROC1_SHA256_BUS_QCH_BUSY_FLAG0_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG0_PROC1_RNG_BUS_QCH_BUSY_FLAG0_Pos                                  20U
+#define PCC_REG_QCH_BUSY_FLAG0_PROC1_RNG_BUS_QCH_BUSY_FLAG0_Msk                                  (0x1UL << PCC_REG_QCH_BUSY_FLAG0_PROC1_RNG_BUS_QCH_BUSY_FLAG0_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG0_PROC1_RNG_QCH_BUSY_FLAG0_Pos                                      21U
+#define PCC_REG_QCH_BUSY_FLAG0_PROC1_RNG_QCH_BUSY_FLAG0_Msk                                      (0x1UL << PCC_REG_QCH_BUSY_FLAG0_PROC1_RNG_QCH_BUSY_FLAG0_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG0_PROC1_RXI300_QCH_BUSY_FLAG0_Pos                                   22U
+#define PCC_REG_QCH_BUSY_FLAG0_PROC1_RXI300_QCH_BUSY_FLAG0_Msk                                   (0x1UL << PCC_REG_QCH_BUSY_FLAG0_PROC1_RXI300_QCH_BUSY_FLAG0_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG0_PROC1_KEYSCAN_BUS_QCH_BUSY_FLAG0_Pos                              23U
+#define PCC_REG_QCH_BUSY_FLAG0_PROC1_KEYSCAN_BUS_QCH_BUSY_FLAG0_Msk                              (0x1UL << PCC_REG_QCH_BUSY_FLAG0_PROC1_KEYSCAN_BUS_QCH_BUSY_FLAG0_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG0_PROC1_KEYSCAN_QCH_BUSY_FLAG0_Pos                                  24U
+#define PCC_REG_QCH_BUSY_FLAG0_PROC1_KEYSCAN_QCH_BUSY_FLAG0_Msk                                  (0x1UL << PCC_REG_QCH_BUSY_FLAG0_PROC1_KEYSCAN_QCH_BUSY_FLAG0_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG0_PROC1_IRRC_PWR_QCH_BUSY_FLAG0_Pos                                 25U
+#define PCC_REG_QCH_BUSY_FLAG0_PROC1_IRRC_PWR_QCH_BUSY_FLAG0_Msk                                 (0x1UL << PCC_REG_QCH_BUSY_FLAG0_PROC1_IRRC_PWR_QCH_BUSY_FLAG0_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG0_PROC1_IRRC_BUS_QCH_BUSY_FLAG0_Pos                                 26U
+#define PCC_REG_QCH_BUSY_FLAG0_PROC1_IRRC_BUS_QCH_BUSY_FLAG0_Msk                                 (0x1UL << PCC_REG_QCH_BUSY_FLAG0_PROC1_IRRC_BUS_QCH_BUSY_FLAG0_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG0_PROC1_IRRC_QCH_BUSY_FLAG0_Pos                                     27U
+#define PCC_REG_QCH_BUSY_FLAG0_PROC1_IRRC_QCH_BUSY_FLAG0_Msk                                     (0x1UL << PCC_REG_QCH_BUSY_FLAG0_PROC1_IRRC_QCH_BUSY_FLAG0_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG0_PROC1_I2C1_PWR_QCH_BUSY_FLAG0_Pos                                 28U
+#define PCC_REG_QCH_BUSY_FLAG0_PROC1_I2C1_PWR_QCH_BUSY_FLAG0_Msk                                 (0x1UL << PCC_REG_QCH_BUSY_FLAG0_PROC1_I2C1_PWR_QCH_BUSY_FLAG0_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG0_PROC1_I2C1_BUS_QCH_BUSY_FLAG0_Pos                                 29U
+#define PCC_REG_QCH_BUSY_FLAG0_PROC1_I2C1_BUS_QCH_BUSY_FLAG0_Msk                                 (0x1UL << PCC_REG_QCH_BUSY_FLAG0_PROC1_I2C1_BUS_QCH_BUSY_FLAG0_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG0_PROC1_I2C1_QCH_BUSY_FLAG0_Pos                                     30U
+#define PCC_REG_QCH_BUSY_FLAG0_PROC1_I2C1_QCH_BUSY_FLAG0_Msk                                     (0x1UL << PCC_REG_QCH_BUSY_FLAG0_PROC1_I2C1_QCH_BUSY_FLAG0_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG0_PROC1_I2C0_PWR_QCH_BUSY_FLAG0_Pos                                 31U
+#define PCC_REG_QCH_BUSY_FLAG0_PROC1_I2C0_PWR_QCH_BUSY_FLAG0_Msk                                 (0x1UL << PCC_REG_QCH_BUSY_FLAG0_PROC1_I2C0_PWR_QCH_BUSY_FLAG0_Pos)
+
+/* 0x39C    0x4000_039c
+    0       R       USB_PWR_QCH_BUSY_FLAG0                          1'b1
+    1       R       USB_BUS_QCH_BUSY_FLAG0                          1'b1
+    2       R       USB_QCH_BUSY_FLAG0                              1'b1
+    3       R       PCSM_VCORE_OP1_QCH_BUSY_FLAG0                   1'b1
+    4       R       VDREG_QCH_BUSY_FLAG0                            1'b1
+    5       R       UART3_PWR_QCH_BUSY_FLAG0                        1'b1
+    6       R       UART3_BUS_QCH_BUSY_FLAG0                        1'b1
+    7       R       UART3_QCH_BUSY_FLAG0                            1'b1
+    8       R       UART2_PWR_QCH_BUSY_FLAG0                        1'b1
+    9       R       UART2_BUS_QCH_BUSY_FLAG0                        1'b1
+    10      R       UART2_QCH_BUSY_FLAG0                            1'b1
+    11      R       UART1_PWR_QCH_BUSY_FLAG0                        1'b1
+    12      R       UART1_BUS_QCH_BUSY_FLAG0                        1'b1
+    13      R       UART1_QCH_BUSY_FLAG0                            1'b1
+    14      R       UART0_PWR_QCH_BUSY_FLAG0                        1'b1
+    15      R       UART0_BUS_QCH_BUSY_FLAG0                        1'b1
+    16      R       UART0_QCH_BUSY_FLAG0                            1'b1
+    17      R       TMETER_BUS_QCH_BUSY_FLAG0                       1'b1
+    18      R       TMETER_QCH_BUSY_FLAG0                           1'b1
+    19      R       TIMER11_PWM_QCH_BUSY_FLAG0                      1'b1
+    20      R       TIMER11_QCH_BUSY_FLAG0                          1'b1
+    21      R       TIMER10_PWM_QCH_BUSY_FLAG0                      1'b1
+    22      R       TIMER10_QCH_BUSY_FLAG0                          1'b1
+    23      R       TIMER9_PCLK_QCH_BUSY_FLAG0                      1'b1
+    24      R       TIMER9_PWM_QCH_BUSY_FLAG0                       1'b1
+    25      R       TIMER9_BUS_QCH_BUSY_FLAG0                       1'b1
+    26      R       TIMER9_QCH_BUSY_FLAG0                           1'b1
+    27      R       TIMER8_QCH_BUSY_FLAG0                           1'b1
+    28      R       TIMER7_QCH_BUSY_FLAG0                           1'b1
+    29      R       TIMER6_QCH_BUSY_FLAG0                           1'b1
+    30      R       TIMER5_QCH_BUSY_FLAG0                           1'b1
+    31      R       TIMER4_QCH_BUSY_FLAG0                           1'b1
+ */
+typedef union _PCC_REG_QCH_BUSY_FLAG0_PROC2_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t USB_PWR_QCH_BUSY_FLAG0: 1;
+        uint32_t USB_BUS_QCH_BUSY_FLAG0: 1;
+        uint32_t USB_QCH_BUSY_FLAG0: 1;
+        uint32_t PCSM_VCORE_OP1_QCH_BUSY_FLAG0: 1;
+        uint32_t VDREG_QCH_BUSY_FLAG0: 1;
+        uint32_t UART3_PWR_QCH_BUSY_FLAG0: 1;
+        uint32_t UART3_BUS_QCH_BUSY_FLAG0: 1;
+        uint32_t UART3_QCH_BUSY_FLAG0: 1;
+        uint32_t UART2_PWR_QCH_BUSY_FLAG0: 1;
+        uint32_t UART2_BUS_QCH_BUSY_FLAG0: 1;
+        uint32_t UART2_QCH_BUSY_FLAG0: 1;
+        uint32_t UART1_PWR_QCH_BUSY_FLAG0: 1;
+        uint32_t UART1_BUS_QCH_BUSY_FLAG0: 1;
+        uint32_t UART1_QCH_BUSY_FLAG0: 1;
+        uint32_t UART0_PWR_QCH_BUSY_FLAG0: 1;
+        uint32_t UART0_BUS_QCH_BUSY_FLAG0: 1;
+        uint32_t UART0_QCH_BUSY_FLAG0: 1;
+        uint32_t TMETER_BUS_QCH_BUSY_FLAG0: 1;
+        uint32_t TMETER_QCH_BUSY_FLAG0: 1;
+        uint32_t TIMER11_PWM_QCH_BUSY_FLAG0: 1;
+        uint32_t TIMER11_QCH_BUSY_FLAG0: 1;
+        uint32_t TIMER10_PWM_QCH_BUSY_FLAG0: 1;
+        uint32_t TIMER10_QCH_BUSY_FLAG0: 1;
+        uint32_t TIMER9_PCLK_QCH_BUSY_FLAG0: 1;
+        uint32_t TIMER9_PWM_QCH_BUSY_FLAG0: 1;
+        uint32_t TIMER9_BUS_QCH_BUSY_FLAG0: 1;
+        uint32_t TIMER9_QCH_BUSY_FLAG0: 1;
+        uint32_t TIMER8_QCH_BUSY_FLAG0: 1;
+        uint32_t TIMER7_QCH_BUSY_FLAG0: 1;
+        uint32_t TIMER6_QCH_BUSY_FLAG0: 1;
+        uint32_t TIMER5_QCH_BUSY_FLAG0: 1;
+        uint32_t TIMER4_QCH_BUSY_FLAG0: 1;
+    };
+} PCC_REG_QCH_BUSY_FLAG0_PROC2_TYPE;
+
+/*0x4000_039c PCC_REG_QCH_BUSY_FLAG0_PROC2*/
+#define PCC_REG_QCH_BUSY_FLAG0_PROC2_USB_PWR_QCH_BUSY_FLAG0_Pos                                  0U
+#define PCC_REG_QCH_BUSY_FLAG0_PROC2_USB_PWR_QCH_BUSY_FLAG0_Msk                                  (0x1UL << PCC_REG_QCH_BUSY_FLAG0_PROC2_USB_PWR_QCH_BUSY_FLAG0_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG0_PROC2_USB_BUS_QCH_BUSY_FLAG0_Pos                                  1U
+#define PCC_REG_QCH_BUSY_FLAG0_PROC2_USB_BUS_QCH_BUSY_FLAG0_Msk                                  (0x1UL << PCC_REG_QCH_BUSY_FLAG0_PROC2_USB_BUS_QCH_BUSY_FLAG0_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG0_PROC2_USB_QCH_BUSY_FLAG0_Pos                                      2U
+#define PCC_REG_QCH_BUSY_FLAG0_PROC2_USB_QCH_BUSY_FLAG0_Msk                                      (0x1UL << PCC_REG_QCH_BUSY_FLAG0_PROC2_USB_QCH_BUSY_FLAG0_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG0_PROC2_PCSM_VCORE_OP1_QCH_BUSY_FLAG0_Pos                           3U
+#define PCC_REG_QCH_BUSY_FLAG0_PROC2_PCSM_VCORE_OP1_QCH_BUSY_FLAG0_Msk                           (0x1UL << PCC_REG_QCH_BUSY_FLAG0_PROC2_PCSM_VCORE_OP1_QCH_BUSY_FLAG0_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG0_PROC2_VDREG_QCH_BUSY_FLAG0_Pos                                    4U
+#define PCC_REG_QCH_BUSY_FLAG0_PROC2_VDREG_QCH_BUSY_FLAG0_Msk                                    (0x1UL << PCC_REG_QCH_BUSY_FLAG0_PROC2_VDREG_QCH_BUSY_FLAG0_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG0_PROC2_UART3_PWR_QCH_BUSY_FLAG0_Pos                                5U
+#define PCC_REG_QCH_BUSY_FLAG0_PROC2_UART3_PWR_QCH_BUSY_FLAG0_Msk                                (0x1UL << PCC_REG_QCH_BUSY_FLAG0_PROC2_UART3_PWR_QCH_BUSY_FLAG0_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG0_PROC2_UART3_BUS_QCH_BUSY_FLAG0_Pos                                6U
+#define PCC_REG_QCH_BUSY_FLAG0_PROC2_UART3_BUS_QCH_BUSY_FLAG0_Msk                                (0x1UL << PCC_REG_QCH_BUSY_FLAG0_PROC2_UART3_BUS_QCH_BUSY_FLAG0_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG0_PROC2_UART3_QCH_BUSY_FLAG0_Pos                                    7U
+#define PCC_REG_QCH_BUSY_FLAG0_PROC2_UART3_QCH_BUSY_FLAG0_Msk                                    (0x1UL << PCC_REG_QCH_BUSY_FLAG0_PROC2_UART3_QCH_BUSY_FLAG0_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG0_PROC2_UART2_PWR_QCH_BUSY_FLAG0_Pos                                8U
+#define PCC_REG_QCH_BUSY_FLAG0_PROC2_UART2_PWR_QCH_BUSY_FLAG0_Msk                                (0x1UL << PCC_REG_QCH_BUSY_FLAG0_PROC2_UART2_PWR_QCH_BUSY_FLAG0_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG0_PROC2_UART2_BUS_QCH_BUSY_FLAG0_Pos                                9U
+#define PCC_REG_QCH_BUSY_FLAG0_PROC2_UART2_BUS_QCH_BUSY_FLAG0_Msk                                (0x1UL << PCC_REG_QCH_BUSY_FLAG0_PROC2_UART2_BUS_QCH_BUSY_FLAG0_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG0_PROC2_UART2_QCH_BUSY_FLAG0_Pos                                    10U
+#define PCC_REG_QCH_BUSY_FLAG0_PROC2_UART2_QCH_BUSY_FLAG0_Msk                                    (0x1UL << PCC_REG_QCH_BUSY_FLAG0_PROC2_UART2_QCH_BUSY_FLAG0_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG0_PROC2_UART1_PWR_QCH_BUSY_FLAG0_Pos                                11U
+#define PCC_REG_QCH_BUSY_FLAG0_PROC2_UART1_PWR_QCH_BUSY_FLAG0_Msk                                (0x1UL << PCC_REG_QCH_BUSY_FLAG0_PROC2_UART1_PWR_QCH_BUSY_FLAG0_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG0_PROC2_UART1_BUS_QCH_BUSY_FLAG0_Pos                                12U
+#define PCC_REG_QCH_BUSY_FLAG0_PROC2_UART1_BUS_QCH_BUSY_FLAG0_Msk                                (0x1UL << PCC_REG_QCH_BUSY_FLAG0_PROC2_UART1_BUS_QCH_BUSY_FLAG0_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG0_PROC2_UART1_QCH_BUSY_FLAG0_Pos                                    13U
+#define PCC_REG_QCH_BUSY_FLAG0_PROC2_UART1_QCH_BUSY_FLAG0_Msk                                    (0x1UL << PCC_REG_QCH_BUSY_FLAG0_PROC2_UART1_QCH_BUSY_FLAG0_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG0_PROC2_UART0_PWR_QCH_BUSY_FLAG0_Pos                                14U
+#define PCC_REG_QCH_BUSY_FLAG0_PROC2_UART0_PWR_QCH_BUSY_FLAG0_Msk                                (0x1UL << PCC_REG_QCH_BUSY_FLAG0_PROC2_UART0_PWR_QCH_BUSY_FLAG0_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG0_PROC2_UART0_BUS_QCH_BUSY_FLAG0_Pos                                15U
+#define PCC_REG_QCH_BUSY_FLAG0_PROC2_UART0_BUS_QCH_BUSY_FLAG0_Msk                                (0x1UL << PCC_REG_QCH_BUSY_FLAG0_PROC2_UART0_BUS_QCH_BUSY_FLAG0_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG0_PROC2_UART0_QCH_BUSY_FLAG0_Pos                                    16U
+#define PCC_REG_QCH_BUSY_FLAG0_PROC2_UART0_QCH_BUSY_FLAG0_Msk                                    (0x1UL << PCC_REG_QCH_BUSY_FLAG0_PROC2_UART0_QCH_BUSY_FLAG0_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG0_PROC2_TMETER_BUS_QCH_BUSY_FLAG0_Pos                               17U
+#define PCC_REG_QCH_BUSY_FLAG0_PROC2_TMETER_BUS_QCH_BUSY_FLAG0_Msk                               (0x1UL << PCC_REG_QCH_BUSY_FLAG0_PROC2_TMETER_BUS_QCH_BUSY_FLAG0_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG0_PROC2_TMETER_QCH_BUSY_FLAG0_Pos                                   18U
+#define PCC_REG_QCH_BUSY_FLAG0_PROC2_TMETER_QCH_BUSY_FLAG0_Msk                                   (0x1UL << PCC_REG_QCH_BUSY_FLAG0_PROC2_TMETER_QCH_BUSY_FLAG0_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG0_PROC2_TIMER11_PWM_QCH_BUSY_FLAG0_Pos                              19U
+#define PCC_REG_QCH_BUSY_FLAG0_PROC2_TIMER11_PWM_QCH_BUSY_FLAG0_Msk                              (0x1UL << PCC_REG_QCH_BUSY_FLAG0_PROC2_TIMER11_PWM_QCH_BUSY_FLAG0_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG0_PROC2_TIMER11_QCH_BUSY_FLAG0_Pos                                  20U
+#define PCC_REG_QCH_BUSY_FLAG0_PROC2_TIMER11_QCH_BUSY_FLAG0_Msk                                  (0x1UL << PCC_REG_QCH_BUSY_FLAG0_PROC2_TIMER11_QCH_BUSY_FLAG0_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG0_PROC2_TIMER10_PWM_QCH_BUSY_FLAG0_Pos                              21U
+#define PCC_REG_QCH_BUSY_FLAG0_PROC2_TIMER10_PWM_QCH_BUSY_FLAG0_Msk                              (0x1UL << PCC_REG_QCH_BUSY_FLAG0_PROC2_TIMER10_PWM_QCH_BUSY_FLAG0_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG0_PROC2_TIMER10_QCH_BUSY_FLAG0_Pos                                  22U
+#define PCC_REG_QCH_BUSY_FLAG0_PROC2_TIMER10_QCH_BUSY_FLAG0_Msk                                  (0x1UL << PCC_REG_QCH_BUSY_FLAG0_PROC2_TIMER10_QCH_BUSY_FLAG0_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG0_PROC2_TIMER9_PCLK_QCH_BUSY_FLAG0_Pos                              23U
+#define PCC_REG_QCH_BUSY_FLAG0_PROC2_TIMER9_PCLK_QCH_BUSY_FLAG0_Msk                              (0x1UL << PCC_REG_QCH_BUSY_FLAG0_PROC2_TIMER9_PCLK_QCH_BUSY_FLAG0_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG0_PROC2_TIMER9_PWM_QCH_BUSY_FLAG0_Pos                               24U
+#define PCC_REG_QCH_BUSY_FLAG0_PROC2_TIMER9_PWM_QCH_BUSY_FLAG0_Msk                               (0x1UL << PCC_REG_QCH_BUSY_FLAG0_PROC2_TIMER9_PWM_QCH_BUSY_FLAG0_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG0_PROC2_TIMER9_BUS_QCH_BUSY_FLAG0_Pos                               25U
+#define PCC_REG_QCH_BUSY_FLAG0_PROC2_TIMER9_BUS_QCH_BUSY_FLAG0_Msk                               (0x1UL << PCC_REG_QCH_BUSY_FLAG0_PROC2_TIMER9_BUS_QCH_BUSY_FLAG0_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG0_PROC2_TIMER9_QCH_BUSY_FLAG0_Pos                                   26U
+#define PCC_REG_QCH_BUSY_FLAG0_PROC2_TIMER9_QCH_BUSY_FLAG0_Msk                                   (0x1UL << PCC_REG_QCH_BUSY_FLAG0_PROC2_TIMER9_QCH_BUSY_FLAG0_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG0_PROC2_TIMER8_QCH_BUSY_FLAG0_Pos                                   27U
+#define PCC_REG_QCH_BUSY_FLAG0_PROC2_TIMER8_QCH_BUSY_FLAG0_Msk                                   (0x1UL << PCC_REG_QCH_BUSY_FLAG0_PROC2_TIMER8_QCH_BUSY_FLAG0_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG0_PROC2_TIMER7_QCH_BUSY_FLAG0_Pos                                   28U
+#define PCC_REG_QCH_BUSY_FLAG0_PROC2_TIMER7_QCH_BUSY_FLAG0_Msk                                   (0x1UL << PCC_REG_QCH_BUSY_FLAG0_PROC2_TIMER7_QCH_BUSY_FLAG0_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG0_PROC2_TIMER6_QCH_BUSY_FLAG0_Pos                                   29U
+#define PCC_REG_QCH_BUSY_FLAG0_PROC2_TIMER6_QCH_BUSY_FLAG0_Msk                                   (0x1UL << PCC_REG_QCH_BUSY_FLAG0_PROC2_TIMER6_QCH_BUSY_FLAG0_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG0_PROC2_TIMER5_QCH_BUSY_FLAG0_Pos                                   30U
+#define PCC_REG_QCH_BUSY_FLAG0_PROC2_TIMER5_QCH_BUSY_FLAG0_Msk                                   (0x1UL << PCC_REG_QCH_BUSY_FLAG0_PROC2_TIMER5_QCH_BUSY_FLAG0_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG0_PROC2_TIMER4_QCH_BUSY_FLAG0_Pos                                   31U
+#define PCC_REG_QCH_BUSY_FLAG0_PROC2_TIMER4_QCH_BUSY_FLAG0_Msk                                   (0x1UL << PCC_REG_QCH_BUSY_FLAG0_PROC2_TIMER4_QCH_BUSY_FLAG0_Pos)
+
+/* 0x3A0    0x4000_03a0
+    0       R       SPORT_BUS_QCH_BUSY_FLAG1                        1'b0
+    1       R       SPORT_QCH_BUSY_FLAG1                            1'b0
+    2       R       RFC_QCH_BUSY_FLAG1                              1'b0
+    3       R       PRO24G_QCH_BUSY_FLAG1                           1'b0
+    4       R       PCC_BUS_QCH_BUSY_FLAG1                          1'b0
+    5       R       MODEM_BUS_QCH_BUSY_FLAG1                        1'b0
+    6       R       MODEM_QCH_BUSY_FLAG1                            1'b0
+    7       R       CAL80M_OSC_QCH_BUSY_FLAG1                       1'b0
+    8       R       CAL80M_BUS_QCH_BUSY_FLAG1                       1'b0
+    9       R       CAL80M_QCH_BUSY_FLAG1                           1'b0
+    10      R       CAL32K_AON_BUS_QCH_BUSY_FLAG1                   1'b0
+    11      R       CAL32K_AON_QCH_BUSY_FLAG1                       1'b0
+    12      R       CAL32K_QCH_BUSY_FLAG1                           1'b0
+    13      R       CAL10M_OSC_BUS_QCH_BUSY_FLAG1                   1'b0
+    14      R       CAL10M_BUS_QCH_BUSY_FLAG1                       1'b0
+    15      R       CAL10M_QCH_BUSY_FLAG1                           1'b0
+    16      R       BTMAC_BUS_QCH_BUSY_FLAG1                        1'b0
+    17      R       BTMAC_QCH_BUSY_FLAG1                            1'b0
+    18      R       BT_VEN_BUS_QCH_BUSY_FLAG1                       1'b0
+    19      R       AUDIO_BUS_BUS_QCH_BUSY_FLAG1                    1'b0
+    20      R       AUDIO_QCH_BUSY_FLAG1                            1'b0
+    21      R       ADC_PWR_QCH_BUSY_FLAG1                          1'b0
+    22      R       ADC_BUS_QCH_BUSY_FLAG1                          1'b0
+    23      R       ADC_QCH_BUSY_FLAG1                              1'b0
+    24      R       AACK_QCH_BUSY_FLAG1                             1'b0
+    31:25   R       RESERVED                                        7'd0
+ */
+typedef union _PCC_REG_QCH_BUSY_FLAG1_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t SPORT_BUS_QCH_BUSY_FLAG1: 1;
+        uint32_t SPORT_QCH_BUSY_FLAG1: 1;
+        uint32_t RFC_QCH_BUSY_FLAG1: 1;
+        uint32_t PRO24G_QCH_BUSY_FLAG1: 1;
+        uint32_t PCC_BUS_QCH_BUSY_FLAG1: 1;
+        uint32_t MODEM_BUS_QCH_BUSY_FLAG1: 1;
+        uint32_t MODEM_QCH_BUSY_FLAG1: 1;
+        uint32_t CAL80M_OSC_QCH_BUSY_FLAG1: 1;
+        uint32_t CAL80M_BUS_QCH_BUSY_FLAG1: 1;
+        uint32_t CAL80M_QCH_BUSY_FLAG1: 1;
+        uint32_t CAL32K_AON_BUS_QCH_BUSY_FLAG1: 1;
+        uint32_t CAL32K_AON_QCH_BUSY_FLAG1: 1;
+        uint32_t CAL32K_QCH_BUSY_FLAG1: 1;
+        uint32_t CAL10M_OSC_BUS_QCH_BUSY_FLAG1: 1;
+        uint32_t CAL10M_BUS_QCH_BUSY_FLAG1: 1;
+        uint32_t CAL10M_QCH_BUSY_FLAG1: 1;
+        uint32_t BTMAC_BUS_QCH_BUSY_FLAG1: 1;
+        uint32_t BTMAC_QCH_BUSY_FLAG1: 1;
+        uint32_t BT_VEN_BUS_QCH_BUSY_FLAG1: 1;
+        uint32_t AUDIO_BUS_BUS_QCH_BUSY_FLAG1: 1;
+        uint32_t AUDIO_QCH_BUSY_FLAG1: 1;
+        uint32_t ADC_PWR_QCH_BUSY_FLAG1: 1;
+        uint32_t ADC_BUS_QCH_BUSY_FLAG1: 1;
+        uint32_t ADC_QCH_BUSY_FLAG1: 1;
+        uint32_t AACK_QCH_BUSY_FLAG1: 1;
+        uint32_t RESERVED: 7;
+    };
+} PCC_REG_QCH_BUSY_FLAG1_TYPE;
+
+/*0x4000_03a0 PCC_REG_QCH_BUSY_FLAG1*/
+#define PCC_REG_QCH_BUSY_FLAG1_SPORT_BUS_QCH_BUSY_FLAG1_Pos                                      0U
+#define PCC_REG_QCH_BUSY_FLAG1_SPORT_BUS_QCH_BUSY_FLAG1_Msk                                      (0x1UL << PCC_REG_QCH_BUSY_FLAG1_SPORT_BUS_QCH_BUSY_FLAG1_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG1_SPORT_QCH_BUSY_FLAG1_Pos                                          1U
+#define PCC_REG_QCH_BUSY_FLAG1_SPORT_QCH_BUSY_FLAG1_Msk                                          (0x1UL << PCC_REG_QCH_BUSY_FLAG1_SPORT_QCH_BUSY_FLAG1_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG1_RFC_QCH_BUSY_FLAG1_Pos                                            2U
+#define PCC_REG_QCH_BUSY_FLAG1_RFC_QCH_BUSY_FLAG1_Msk                                            (0x1UL << PCC_REG_QCH_BUSY_FLAG1_RFC_QCH_BUSY_FLAG1_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG1_PRO24G_QCH_BUSY_FLAG1_Pos                                         3U
+#define PCC_REG_QCH_BUSY_FLAG1_PRO24G_QCH_BUSY_FLAG1_Msk                                         (0x1UL << PCC_REG_QCH_BUSY_FLAG1_PRO24G_QCH_BUSY_FLAG1_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG1_PCC_BUS_QCH_BUSY_FLAG1_Pos                                        4U
+#define PCC_REG_QCH_BUSY_FLAG1_PCC_BUS_QCH_BUSY_FLAG1_Msk                                        (0x1UL << PCC_REG_QCH_BUSY_FLAG1_PCC_BUS_QCH_BUSY_FLAG1_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG1_MODEM_BUS_QCH_BUSY_FLAG1_Pos                                      5U
+#define PCC_REG_QCH_BUSY_FLAG1_MODEM_BUS_QCH_BUSY_FLAG1_Msk                                      (0x1UL << PCC_REG_QCH_BUSY_FLAG1_MODEM_BUS_QCH_BUSY_FLAG1_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG1_MODEM_QCH_BUSY_FLAG1_Pos                                          6U
+#define PCC_REG_QCH_BUSY_FLAG1_MODEM_QCH_BUSY_FLAG1_Msk                                          (0x1UL << PCC_REG_QCH_BUSY_FLAG1_MODEM_QCH_BUSY_FLAG1_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG1_CAL80M_OSC_QCH_BUSY_FLAG1_Pos                                     7U
+#define PCC_REG_QCH_BUSY_FLAG1_CAL80M_OSC_QCH_BUSY_FLAG1_Msk                                     (0x1UL << PCC_REG_QCH_BUSY_FLAG1_CAL80M_OSC_QCH_BUSY_FLAG1_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG1_CAL80M_BUS_QCH_BUSY_FLAG1_Pos                                     8U
+#define PCC_REG_QCH_BUSY_FLAG1_CAL80M_BUS_QCH_BUSY_FLAG1_Msk                                     (0x1UL << PCC_REG_QCH_BUSY_FLAG1_CAL80M_BUS_QCH_BUSY_FLAG1_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG1_CAL80M_QCH_BUSY_FLAG1_Pos                                         9U
+#define PCC_REG_QCH_BUSY_FLAG1_CAL80M_QCH_BUSY_FLAG1_Msk                                         (0x1UL << PCC_REG_QCH_BUSY_FLAG1_CAL80M_QCH_BUSY_FLAG1_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG1_CAL32K_AON_BUS_QCH_BUSY_FLAG1_Pos                                 10U
+#define PCC_REG_QCH_BUSY_FLAG1_CAL32K_AON_BUS_QCH_BUSY_FLAG1_Msk                                 (0x1UL << PCC_REG_QCH_BUSY_FLAG1_CAL32K_AON_BUS_QCH_BUSY_FLAG1_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG1_CAL32K_AON_QCH_BUSY_FLAG1_Pos                                     11U
+#define PCC_REG_QCH_BUSY_FLAG1_CAL32K_AON_QCH_BUSY_FLAG1_Msk                                     (0x1UL << PCC_REG_QCH_BUSY_FLAG1_CAL32K_AON_QCH_BUSY_FLAG1_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG1_CAL32K_QCH_BUSY_FLAG1_Pos                                         12U
+#define PCC_REG_QCH_BUSY_FLAG1_CAL32K_QCH_BUSY_FLAG1_Msk                                         (0x1UL << PCC_REG_QCH_BUSY_FLAG1_CAL32K_QCH_BUSY_FLAG1_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG1_CAL10M_OSC_BUS_QCH_BUSY_FLAG1_Pos                                 13U
+#define PCC_REG_QCH_BUSY_FLAG1_CAL10M_OSC_BUS_QCH_BUSY_FLAG1_Msk                                 (0x1UL << PCC_REG_QCH_BUSY_FLAG1_CAL10M_OSC_BUS_QCH_BUSY_FLAG1_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG1_CAL10M_BUS_QCH_BUSY_FLAG1_Pos                                     14U
+#define PCC_REG_QCH_BUSY_FLAG1_CAL10M_BUS_QCH_BUSY_FLAG1_Msk                                     (0x1UL << PCC_REG_QCH_BUSY_FLAG1_CAL10M_BUS_QCH_BUSY_FLAG1_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG1_CAL10M_QCH_BUSY_FLAG1_Pos                                         15U
+#define PCC_REG_QCH_BUSY_FLAG1_CAL10M_QCH_BUSY_FLAG1_Msk                                         (0x1UL << PCC_REG_QCH_BUSY_FLAG1_CAL10M_QCH_BUSY_FLAG1_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG1_BTMAC_BUS_QCH_BUSY_FLAG1_Pos                                      16U
+#define PCC_REG_QCH_BUSY_FLAG1_BTMAC_BUS_QCH_BUSY_FLAG1_Msk                                      (0x1UL << PCC_REG_QCH_BUSY_FLAG1_BTMAC_BUS_QCH_BUSY_FLAG1_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG1_BTMAC_QCH_BUSY_FLAG1_Pos                                          17U
+#define PCC_REG_QCH_BUSY_FLAG1_BTMAC_QCH_BUSY_FLAG1_Msk                                          (0x1UL << PCC_REG_QCH_BUSY_FLAG1_BTMAC_QCH_BUSY_FLAG1_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG1_BT_VEN_BUS_QCH_BUSY_FLAG1_Pos                                     18U
+#define PCC_REG_QCH_BUSY_FLAG1_BT_VEN_BUS_QCH_BUSY_FLAG1_Msk                                     (0x1UL << PCC_REG_QCH_BUSY_FLAG1_BT_VEN_BUS_QCH_BUSY_FLAG1_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG1_AUDIO_BUS_BUS_QCH_BUSY_FLAG1_Pos                                  19U
+#define PCC_REG_QCH_BUSY_FLAG1_AUDIO_BUS_BUS_QCH_BUSY_FLAG1_Msk                                  (0x1UL << PCC_REG_QCH_BUSY_FLAG1_AUDIO_BUS_BUS_QCH_BUSY_FLAG1_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG1_AUDIO_QCH_BUSY_FLAG1_Pos                                          20U
+#define PCC_REG_QCH_BUSY_FLAG1_AUDIO_QCH_BUSY_FLAG1_Msk                                          (0x1UL << PCC_REG_QCH_BUSY_FLAG1_AUDIO_QCH_BUSY_FLAG1_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG1_ADC_PWR_QCH_BUSY_FLAG1_Pos                                        21U
+#define PCC_REG_QCH_BUSY_FLAG1_ADC_PWR_QCH_BUSY_FLAG1_Msk                                        (0x1UL << PCC_REG_QCH_BUSY_FLAG1_ADC_PWR_QCH_BUSY_FLAG1_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG1_ADC_BUS_QCH_BUSY_FLAG1_Pos                                        22U
+#define PCC_REG_QCH_BUSY_FLAG1_ADC_BUS_QCH_BUSY_FLAG1_Msk                                        (0x1UL << PCC_REG_QCH_BUSY_FLAG1_ADC_BUS_QCH_BUSY_FLAG1_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG1_ADC_QCH_BUSY_FLAG1_Pos                                            23U
+#define PCC_REG_QCH_BUSY_FLAG1_ADC_QCH_BUSY_FLAG1_Msk                                            (0x1UL << PCC_REG_QCH_BUSY_FLAG1_ADC_QCH_BUSY_FLAG1_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG1_AACK_QCH_BUSY_FLAG1_Pos                                           24U
+#define PCC_REG_QCH_BUSY_FLAG1_AACK_QCH_BUSY_FLAG1_Msk                                           (0x1UL << PCC_REG_QCH_BUSY_FLAG1_AACK_QCH_BUSY_FLAG1_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG1_RESERVED_Pos                                                      25U
+#define PCC_REG_QCH_BUSY_FLAG1_RESERVED_Msk                                                      (0x7FUL << PCC_REG_QCH_BUSY_FLAG1_RESERVED_Pos)
+
+/* 0x3A4    0x4000_03a4
+    0       R       SPORT_BUS_QCH_BUSY_FLAG0                        1'b1
+    1       R       SPORT_QCH_BUSY_FLAG0                            1'b1
+    2       R       RFC_QCH_BUSY_FLAG0                              1'b1
+    3       R       PRO24G_QCH_BUSY_FLAG0                           1'b1
+    4       R       PCC_BUS_QCH_BUSY_FLAG0                          1'b1
+    5       R       MODEM_BUS_QCH_BUSY_FLAG0                        1'b1
+    6       R       MODEM_QCH_BUSY_FLAG0                            1'b1
+    7       R       CAL80M_OSC_QCH_BUSY_FLAG0                       1'b1
+    8       R       CAL80M_BUS_QCH_BUSY_FLAG0                       1'b1
+    9       R       CAL80M_QCH_BUSY_FLAG0                           1'b1
+    10      R       CAL32K_AON_BUS_QCH_BUSY_FLAG0                   1'b1
+    11      R       CAL32K_AON_QCH_BUSY_FLAG0                       1'b1
+    12      R       CAL32K_QCH_BUSY_FLAG0                           1'b1
+    13      R       CAL10M_OSC_BUS_QCH_BUSY_FLAG0                   1'b1
+    14      R       CAL10M_BUS_QCH_BUSY_FLAG0                       1'b1
+    15      R       CAL10M_QCH_BUSY_FLAG0                           1'b1
+    16      R       BTMAC_BUS_QCH_BUSY_FLAG0                        1'b1
+    17      R       BTMAC_QCH_BUSY_FLAG0                            1'b1
+    18      R       BT_VEN_BUS_QCH_BUSY_FLAG0                       1'b1
+    19      R       AUDIO_BUS_BUS_QCH_BUSY_FLAG0                    1'b1
+    20      R       AUDIO_QCH_BUSY_FLAG0                            1'b1
+    21      R       ADC_PWR_QCH_BUSY_FLAG0                          1'b1
+    22      R       ADC_BUS_QCH_BUSY_FLAG0                          1'b1
+    23      R       ADC_QCH_BUSY_FLAG0                              1'b1
+    24      R       AACK_QCH_BUSY_FLAG0                             1'b1
+    30:25   R       RESERVED                                        6'd0
+    31      R/W1C   DBG_QCH_BUSY_FLAG_W1C                           1'b0
+ */
+typedef union _PCC_REG_QCH_BUSY_FLAG0_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t SPORT_BUS_QCH_BUSY_FLAG0: 1;
+        uint32_t SPORT_QCH_BUSY_FLAG0: 1;
+        uint32_t RFC_QCH_BUSY_FLAG0: 1;
+        uint32_t PRO24G_QCH_BUSY_FLAG0: 1;
+        uint32_t PCC_BUS_QCH_BUSY_FLAG0: 1;
+        uint32_t MODEM_BUS_QCH_BUSY_FLAG0: 1;
+        uint32_t MODEM_QCH_BUSY_FLAG0: 1;
+        uint32_t CAL80M_OSC_QCH_BUSY_FLAG0: 1;
+        uint32_t CAL80M_BUS_QCH_BUSY_FLAG0: 1;
+        uint32_t CAL80M_QCH_BUSY_FLAG0: 1;
+        uint32_t CAL32K_AON_BUS_QCH_BUSY_FLAG0: 1;
+        uint32_t CAL32K_AON_QCH_BUSY_FLAG0: 1;
+        uint32_t CAL32K_QCH_BUSY_FLAG0: 1;
+        uint32_t CAL10M_OSC_BUS_QCH_BUSY_FLAG0: 1;
+        uint32_t CAL10M_BUS_QCH_BUSY_FLAG0: 1;
+        uint32_t CAL10M_QCH_BUSY_FLAG0: 1;
+        uint32_t BTMAC_BUS_QCH_BUSY_FLAG0: 1;
+        uint32_t BTMAC_QCH_BUSY_FLAG0: 1;
+        uint32_t BT_VEN_BUS_QCH_BUSY_FLAG0: 1;
+        uint32_t AUDIO_BUS_BUS_QCH_BUSY_FLAG0: 1;
+        uint32_t AUDIO_QCH_BUSY_FLAG0: 1;
+        uint32_t ADC_PWR_QCH_BUSY_FLAG0: 1;
+        uint32_t ADC_BUS_QCH_BUSY_FLAG0: 1;
+        uint32_t ADC_QCH_BUSY_FLAG0: 1;
+        uint32_t AACK_QCH_BUSY_FLAG0: 1;
+        uint32_t RESERVED: 6;
+        uint32_t DBG_QCH_BUSY_FLAG_W1C: 1;
+    };
+} PCC_REG_QCH_BUSY_FLAG0_TYPE;
+
+/*0x4000_03a4 PCC_REG_QCH_BUSY_FLAG0*/
+#define PCC_REG_QCH_BUSY_FLAG0_SPORT_BUS_QCH_BUSY_FLAG0_Pos                                      0U
+#define PCC_REG_QCH_BUSY_FLAG0_SPORT_BUS_QCH_BUSY_FLAG0_Msk                                      (0x1UL << PCC_REG_QCH_BUSY_FLAG0_SPORT_BUS_QCH_BUSY_FLAG0_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG0_SPORT_QCH_BUSY_FLAG0_Pos                                          1U
+#define PCC_REG_QCH_BUSY_FLAG0_SPORT_QCH_BUSY_FLAG0_Msk                                          (0x1UL << PCC_REG_QCH_BUSY_FLAG0_SPORT_QCH_BUSY_FLAG0_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG0_RFC_QCH_BUSY_FLAG0_Pos                                            2U
+#define PCC_REG_QCH_BUSY_FLAG0_RFC_QCH_BUSY_FLAG0_Msk                                            (0x1UL << PCC_REG_QCH_BUSY_FLAG0_RFC_QCH_BUSY_FLAG0_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG0_PRO24G_QCH_BUSY_FLAG0_Pos                                         3U
+#define PCC_REG_QCH_BUSY_FLAG0_PRO24G_QCH_BUSY_FLAG0_Msk                                         (0x1UL << PCC_REG_QCH_BUSY_FLAG0_PRO24G_QCH_BUSY_FLAG0_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG0_PCC_BUS_QCH_BUSY_FLAG0_Pos                                        4U
+#define PCC_REG_QCH_BUSY_FLAG0_PCC_BUS_QCH_BUSY_FLAG0_Msk                                        (0x1UL << PCC_REG_QCH_BUSY_FLAG0_PCC_BUS_QCH_BUSY_FLAG0_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG0_MODEM_BUS_QCH_BUSY_FLAG0_Pos                                      5U
+#define PCC_REG_QCH_BUSY_FLAG0_MODEM_BUS_QCH_BUSY_FLAG0_Msk                                      (0x1UL << PCC_REG_QCH_BUSY_FLAG0_MODEM_BUS_QCH_BUSY_FLAG0_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG0_MODEM_QCH_BUSY_FLAG0_Pos                                          6U
+#define PCC_REG_QCH_BUSY_FLAG0_MODEM_QCH_BUSY_FLAG0_Msk                                          (0x1UL << PCC_REG_QCH_BUSY_FLAG0_MODEM_QCH_BUSY_FLAG0_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG0_CAL80M_OSC_QCH_BUSY_FLAG0_Pos                                     7U
+#define PCC_REG_QCH_BUSY_FLAG0_CAL80M_OSC_QCH_BUSY_FLAG0_Msk                                     (0x1UL << PCC_REG_QCH_BUSY_FLAG0_CAL80M_OSC_QCH_BUSY_FLAG0_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG0_CAL80M_BUS_QCH_BUSY_FLAG0_Pos                                     8U
+#define PCC_REG_QCH_BUSY_FLAG0_CAL80M_BUS_QCH_BUSY_FLAG0_Msk                                     (0x1UL << PCC_REG_QCH_BUSY_FLAG0_CAL80M_BUS_QCH_BUSY_FLAG0_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG0_CAL80M_QCH_BUSY_FLAG0_Pos                                         9U
+#define PCC_REG_QCH_BUSY_FLAG0_CAL80M_QCH_BUSY_FLAG0_Msk                                         (0x1UL << PCC_REG_QCH_BUSY_FLAG0_CAL80M_QCH_BUSY_FLAG0_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG0_CAL32K_AON_BUS_QCH_BUSY_FLAG0_Pos                                 10U
+#define PCC_REG_QCH_BUSY_FLAG0_CAL32K_AON_BUS_QCH_BUSY_FLAG0_Msk                                 (0x1UL << PCC_REG_QCH_BUSY_FLAG0_CAL32K_AON_BUS_QCH_BUSY_FLAG0_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG0_CAL32K_AON_QCH_BUSY_FLAG0_Pos                                     11U
+#define PCC_REG_QCH_BUSY_FLAG0_CAL32K_AON_QCH_BUSY_FLAG0_Msk                                     (0x1UL << PCC_REG_QCH_BUSY_FLAG0_CAL32K_AON_QCH_BUSY_FLAG0_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG0_CAL32K_QCH_BUSY_FLAG0_Pos                                         12U
+#define PCC_REG_QCH_BUSY_FLAG0_CAL32K_QCH_BUSY_FLAG0_Msk                                         (0x1UL << PCC_REG_QCH_BUSY_FLAG0_CAL32K_QCH_BUSY_FLAG0_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG0_CAL10M_OSC_BUS_QCH_BUSY_FLAG0_Pos                                 13U
+#define PCC_REG_QCH_BUSY_FLAG0_CAL10M_OSC_BUS_QCH_BUSY_FLAG0_Msk                                 (0x1UL << PCC_REG_QCH_BUSY_FLAG0_CAL10M_OSC_BUS_QCH_BUSY_FLAG0_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG0_CAL10M_BUS_QCH_BUSY_FLAG0_Pos                                     14U
+#define PCC_REG_QCH_BUSY_FLAG0_CAL10M_BUS_QCH_BUSY_FLAG0_Msk                                     (0x1UL << PCC_REG_QCH_BUSY_FLAG0_CAL10M_BUS_QCH_BUSY_FLAG0_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG0_CAL10M_QCH_BUSY_FLAG0_Pos                                         15U
+#define PCC_REG_QCH_BUSY_FLAG0_CAL10M_QCH_BUSY_FLAG0_Msk                                         (0x1UL << PCC_REG_QCH_BUSY_FLAG0_CAL10M_QCH_BUSY_FLAG0_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG0_BTMAC_BUS_QCH_BUSY_FLAG0_Pos                                      16U
+#define PCC_REG_QCH_BUSY_FLAG0_BTMAC_BUS_QCH_BUSY_FLAG0_Msk                                      (0x1UL << PCC_REG_QCH_BUSY_FLAG0_BTMAC_BUS_QCH_BUSY_FLAG0_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG0_BTMAC_QCH_BUSY_FLAG0_Pos                                          17U
+#define PCC_REG_QCH_BUSY_FLAG0_BTMAC_QCH_BUSY_FLAG0_Msk                                          (0x1UL << PCC_REG_QCH_BUSY_FLAG0_BTMAC_QCH_BUSY_FLAG0_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG0_BT_VEN_BUS_QCH_BUSY_FLAG0_Pos                                     18U
+#define PCC_REG_QCH_BUSY_FLAG0_BT_VEN_BUS_QCH_BUSY_FLAG0_Msk                                     (0x1UL << PCC_REG_QCH_BUSY_FLAG0_BT_VEN_BUS_QCH_BUSY_FLAG0_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG0_AUDIO_BUS_BUS_QCH_BUSY_FLAG0_Pos                                  19U
+#define PCC_REG_QCH_BUSY_FLAG0_AUDIO_BUS_BUS_QCH_BUSY_FLAG0_Msk                                  (0x1UL << PCC_REG_QCH_BUSY_FLAG0_AUDIO_BUS_BUS_QCH_BUSY_FLAG0_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG0_AUDIO_QCH_BUSY_FLAG0_Pos                                          20U
+#define PCC_REG_QCH_BUSY_FLAG0_AUDIO_QCH_BUSY_FLAG0_Msk                                          (0x1UL << PCC_REG_QCH_BUSY_FLAG0_AUDIO_QCH_BUSY_FLAG0_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG0_ADC_PWR_QCH_BUSY_FLAG0_Pos                                        21U
+#define PCC_REG_QCH_BUSY_FLAG0_ADC_PWR_QCH_BUSY_FLAG0_Msk                                        (0x1UL << PCC_REG_QCH_BUSY_FLAG0_ADC_PWR_QCH_BUSY_FLAG0_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG0_ADC_BUS_QCH_BUSY_FLAG0_Pos                                        22U
+#define PCC_REG_QCH_BUSY_FLAG0_ADC_BUS_QCH_BUSY_FLAG0_Msk                                        (0x1UL << PCC_REG_QCH_BUSY_FLAG0_ADC_BUS_QCH_BUSY_FLAG0_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG0_ADC_QCH_BUSY_FLAG0_Pos                                            23U
+#define PCC_REG_QCH_BUSY_FLAG0_ADC_QCH_BUSY_FLAG0_Msk                                            (0x1UL << PCC_REG_QCH_BUSY_FLAG0_ADC_QCH_BUSY_FLAG0_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG0_AACK_QCH_BUSY_FLAG0_Pos                                           24U
+#define PCC_REG_QCH_BUSY_FLAG0_AACK_QCH_BUSY_FLAG0_Msk                                           (0x1UL << PCC_REG_QCH_BUSY_FLAG0_AACK_QCH_BUSY_FLAG0_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG0_RESERVED_Pos                                                      25U
+#define PCC_REG_QCH_BUSY_FLAG0_RESERVED_Msk                                                      (0x3FUL << PCC_REG_QCH_BUSY_FLAG0_RESERVED_Pos)
+
+#define PCC_REG_QCH_BUSY_FLAG0_DBG_QCH_BUSY_FLAG_W1C_Pos                                         31U
+#define PCC_REG_QCH_BUSY_FLAG0_DBG_QCH_BUSY_FLAG_W1C_Msk                                         (0x1UL << PCC_REG_QCH_BUSY_FLAG0_DBG_QCH_BUSY_FLAG_W1C_Pos)
+
+/* 0x3A8    0x4000_03a8
+    0       R/W     R_PDN09                                         1'b0
+    1       R/W     UA33PC_EN                                       1'b0
+    2       R/W     RSVD_2                                          1'b0
+    3       R/W     POW_MBIAS                                       1'b0
+    4       R/W     RSVD_1                                          1'b0
+    5       R/W     ISO_LV_0                                        1'b1
+    6       R/W     POW_BC_L                                        1'b0
+    7       R/W     UA33PC_BC_EN                                    1'b0
+    8       R/W     ISO_UA2USB                                      1'b0
+    9       R/W     USB_BUS_CLK_EN                                  1'b0
+    10      R/W     REG_FORCE_DP                                    1'b0
+    11      R/W     REG_DP_MODE                                     1'b0
+    12      R/W     REG_LDOPW                                       1'b0
+    13      R/W     RES1M_EN_L                                      1'b0
+    31:14   R/W     RSVD                                            18'b0
+ */
+typedef union _PCC_REG_USB_POW_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t R_PDN09: 1;
+        uint32_t UA33PC_EN: 1;
+        uint32_t RSVD_2: 1;
+        uint32_t POW_MBIAS: 1;
+        uint32_t RSVD_1: 1;
+        uint32_t ISO_LV_0: 1;
+        uint32_t POW_BC_L: 1;
+        uint32_t UA33PC_BC_EN: 1;
+        uint32_t ISO_UA2USB: 1;
+        uint32_t USB_BUS_CLK_EN: 1;
+        uint32_t REG_FORCE_DP: 1;
+        uint32_t REG_DP_MODE: 1;
+        uint32_t REG_LDOPW: 1;
+        uint32_t RES1M_EN_L: 1;
+        uint32_t RSVD: 18;
+    };
+} PCC_REG_USB_POW_TYPE;
+
+/*0x4000_03a8 PCC_REG_USB_POW*/
+#define PCC_REG_USB_POW_R_PDN09_Pos                                                              0U
+#define PCC_REG_USB_POW_R_PDN09_Msk                                                              (0x1UL << PCC_REG_USB_POW_R_PDN09_Pos)
+
+#define PCC_REG_USB_POW_UA33PC_EN_Pos                                                            1U
+#define PCC_REG_USB_POW_UA33PC_EN_Msk                                                            (0x1UL << PCC_REG_USB_POW_UA33PC_EN_Pos)
+
+#define PCC_REG_USB_POW_RSVD_2_Pos                                                               2U
+#define PCC_REG_USB_POW_RSVD_2_Msk                                                               (0x1UL << PCC_REG_USB_POW_RSVD_2_Pos)
+
+#define PCC_REG_USB_POW_POW_MBIAS_Pos                                                            3U
+#define PCC_REG_USB_POW_POW_MBIAS_Msk                                                            (0x1UL << PCC_REG_USB_POW_POW_MBIAS_Pos)
+
+#define PCC_REG_USB_POW_RSVD_1_Pos                                                               4U
+#define PCC_REG_USB_POW_RSVD_1_Msk                                                               (0x1UL << PCC_REG_USB_POW_RSVD_1_Pos)
+
+#define PCC_REG_USB_POW_ISO_LV_0_Pos                                                             5U
+#define PCC_REG_USB_POW_ISO_LV_0_Msk                                                             (0x1UL << PCC_REG_USB_POW_ISO_LV_0_Pos)
+
+#define PCC_REG_USB_POW_POW_BC_L_Pos                                                             6U
+#define PCC_REG_USB_POW_POW_BC_L_Msk                                                             (0x1UL << PCC_REG_USB_POW_POW_BC_L_Pos)
+
+#define PCC_REG_USB_POW_UA33PC_BC_EN_Pos                                                         7U
+#define PCC_REG_USB_POW_UA33PC_BC_EN_Msk                                                         (0x1UL << PCC_REG_USB_POW_UA33PC_BC_EN_Pos)
+
+#define PCC_REG_USB_POW_ISO_UA2USB_Pos                                                           8U
+#define PCC_REG_USB_POW_ISO_UA2USB_Msk                                                           (0x1UL << PCC_REG_USB_POW_ISO_UA2USB_Pos)
+
+#define PCC_REG_USB_POW_USB_BUS_CLK_EN_Pos                                                       9U
+#define PCC_REG_USB_POW_USB_BUS_CLK_EN_Msk                                                       (0x1UL << PCC_REG_USB_POW_USB_BUS_CLK_EN_Pos)
+
+#define PCC_REG_USB_POW_REG_FORCE_DP_Pos                                                         10U
+#define PCC_REG_USB_POW_REG_FORCE_DP_Msk                                                         (0x1UL << PCC_REG_USB_POW_REG_FORCE_DP_Pos)
+
+#define PCC_REG_USB_POW_REG_DP_MODE_Pos                                                          11U
+#define PCC_REG_USB_POW_REG_DP_MODE_Msk                                                          (0x1UL << PCC_REG_USB_POW_REG_DP_MODE_Pos)
+
+#define PCC_REG_USB_POW_REG_LDOPW_Pos                                                            12U
+#define PCC_REG_USB_POW_REG_LDOPW_Msk                                                            (0x1UL << PCC_REG_USB_POW_REG_LDOPW_Pos)
+
+#define PCC_REG_USB_POW_RES1M_EN_L_Pos                                                           13U
+#define PCC_REG_USB_POW_RES1M_EN_L_Msk                                                           (0x1UL << PCC_REG_USB_POW_RES1M_EN_L_Pos)
+
+#define PCC_REG_USB_POW_RSVD_Pos                                                                 14U
+#define PCC_REG_USB_POW_RSVD_Msk                                                                 (0x3FFFFUL << PCC_REG_USB_POW_RSVD_Pos)
+
+/* 0x3AC    0x4000_03ac
+    31:0    R       RSVD                                            32'd0
+ */
+typedef union _PCC_REG_DUMMY_3AC_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RSVD;
+    };
+} PCC_REG_DUMMY_3AC_TYPE;
+
+/*0x4000_03ac PCC_REG_DUMMY_3AC*/
+#define PCC_REG_DUMMY_3AC_RSVD_Pos                                                               0U
+#define PCC_REG_DUMMY_3AC_RSVD_Msk                                                               (0xFFFFFFFFUL << PCC_REG_DUMMY_3AC_RSVD_Pos)
+
+/* 0x3B0    0x4000_03b0
+    31:0    R       RSVD                                            32'd0
+ */
+typedef union _PCC_REG_DUMMY_3B0_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RSVD;
+    };
+} PCC_REG_DUMMY_3B0_TYPE;
+
+/*0x4000_03b0 PCC_REG_DUMMY_3B0*/
+#define PCC_REG_DUMMY_3B0_RSVD_Pos                                                               0U
+#define PCC_REG_DUMMY_3B0_RSVD_Msk                                                               (0xFFFFFFFFUL << PCC_REG_DUMMY_3B0_RSVD_Pos)
+
+/* 0x3B4    0x4000_03b4
+    31:0    R       RSVD                                            32'd0
+ */
+typedef union _PCC_REG_DUMMY_3B4_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RSVD;
+    };
+} PCC_REG_DUMMY_3B4_TYPE;
+
+/*0x4000_03b4 PCC_REG_DUMMY_3B4*/
+#define PCC_REG_DUMMY_3B4_RSVD_Pos                                                               0U
+#define PCC_REG_DUMMY_3B4_RSVD_Msk                                                               (0xFFFFFFFFUL << PCC_REG_DUMMY_3B4_RSVD_Pos)
+
+/* 0x3B8    0x4000_03b8
+    31:0    R       DEBUG_PCK_VCORE                                 32'd0
+ */
+typedef union _PCC_REG_DBG_MUX_PCK_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t DEBUG_PCK_VCORE;
+    };
+} PCC_REG_DBG_MUX_PCK_TYPE;
+
+/*0x4000_03b8 PCC_REG_DBG_MUX_PCK*/
+#define PCC_REG_DBG_MUX_PCK_DEBUG_PCK_VCORE_Pos                                                  0U
+#define PCC_REG_DBG_MUX_PCK_DEBUG_PCK_VCORE_Msk                                                  (0xFFFFFFFFUL << PCC_REG_DBG_MUX_PCK_DEBUG_PCK_VCORE_Pos)
+
+/* 0x3BC    0x4000_03bc
+    2:0     R/W     R_DBG_MUX_GRP_SEL0                              3'd0
+    3       R       RSVD_7                                          1'd0
+    6:4     R/W     R_DBG_MUX_GRP_SEL1                              3'd0
+    7       R       RSVD_6                                          1'd0
+    10:8    R/W     R_DBG_MUX_GRP_SEL2                              3'd0
+    11      R       RSVD_5                                          1'd0
+    14:12   R/W     R_DBG_MUX_GRP_SEL3                              3'd0
+    15      R       RSVD_4                                          1'd0
+    18:16   R/W     R_DBG_MUX_GRP_SEL4                              3'd0
+    19      R       RSVD_3                                          1'd0
+    22:20   R/W     R_DBG_MUX_GRP_SEL5                              3'd0
+    23      R       RSVD_2                                          1'd0
+    26:24   R/W     R_DBG_MUX_GRP_SEL6                              3'd0
+    27      R       RSVD_1                                          1'd0
+    30:28   R/W     R_DBG_MUX_GRP_SEL7                              3'd0
+    31      R       RSVD                                            1'd0
+ */
+typedef union _PCC_REG_DBG_MUX_GRP_CFG0_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t R_DBG_MUX_GRP_SEL0: 3;
+        uint32_t RSVD_7: 1;
+        uint32_t R_DBG_MUX_GRP_SEL1: 3;
+        uint32_t RSVD_6: 1;
+        uint32_t R_DBG_MUX_GRP_SEL2: 3;
+        uint32_t RSVD_5: 1;
+        uint32_t R_DBG_MUX_GRP_SEL3: 3;
+        uint32_t RSVD_4: 1;
+        uint32_t R_DBG_MUX_GRP_SEL4: 3;
+        uint32_t RSVD_3: 1;
+        uint32_t R_DBG_MUX_GRP_SEL5: 3;
+        uint32_t RSVD_2: 1;
+        uint32_t R_DBG_MUX_GRP_SEL6: 3;
+        uint32_t RSVD_1: 1;
+        uint32_t R_DBG_MUX_GRP_SEL7: 3;
+        uint32_t RSVD: 1;
+    };
+} PCC_REG_DBG_MUX_GRP_CFG0_TYPE;
+
+/*0x4000_03bc PCC_REG_DBG_MUX_GRP_CFG0*/
+#define PCC_REG_DBG_MUX_GRP_CFG0_R_DBG_MUX_GRP_SEL0_Pos                                          0U
+#define PCC_REG_DBG_MUX_GRP_CFG0_R_DBG_MUX_GRP_SEL0_Msk                                          (0x7UL << PCC_REG_DBG_MUX_GRP_CFG0_R_DBG_MUX_GRP_SEL0_Pos)
+
+#define PCC_REG_DBG_MUX_GRP_CFG0_RSVD_7_Pos                                                      3U
+#define PCC_REG_DBG_MUX_GRP_CFG0_RSVD_7_Msk                                                      (0x1UL << PCC_REG_DBG_MUX_GRP_CFG0_RSVD_7_Pos)
+
+#define PCC_REG_DBG_MUX_GRP_CFG0_R_DBG_MUX_GRP_SEL1_Pos                                          4U
+#define PCC_REG_DBG_MUX_GRP_CFG0_R_DBG_MUX_GRP_SEL1_Msk                                          (0x7UL << PCC_REG_DBG_MUX_GRP_CFG0_R_DBG_MUX_GRP_SEL1_Pos)
+
+#define PCC_REG_DBG_MUX_GRP_CFG0_RSVD_6_Pos                                                      7U
+#define PCC_REG_DBG_MUX_GRP_CFG0_RSVD_6_Msk                                                      (0x1UL << PCC_REG_DBG_MUX_GRP_CFG0_RSVD_6_Pos)
+
+#define PCC_REG_DBG_MUX_GRP_CFG0_R_DBG_MUX_GRP_SEL2_Pos                                          8U
+#define PCC_REG_DBG_MUX_GRP_CFG0_R_DBG_MUX_GRP_SEL2_Msk                                          (0x7UL << PCC_REG_DBG_MUX_GRP_CFG0_R_DBG_MUX_GRP_SEL2_Pos)
+
+#define PCC_REG_DBG_MUX_GRP_CFG0_RSVD_5_Pos                                                      11U
+#define PCC_REG_DBG_MUX_GRP_CFG0_RSVD_5_Msk                                                      (0x1UL << PCC_REG_DBG_MUX_GRP_CFG0_RSVD_5_Pos)
+
+#define PCC_REG_DBG_MUX_GRP_CFG0_R_DBG_MUX_GRP_SEL3_Pos                                          12U
+#define PCC_REG_DBG_MUX_GRP_CFG0_R_DBG_MUX_GRP_SEL3_Msk                                          (0x7UL << PCC_REG_DBG_MUX_GRP_CFG0_R_DBG_MUX_GRP_SEL3_Pos)
+
+#define PCC_REG_DBG_MUX_GRP_CFG0_RSVD_4_Pos                                                      15U
+#define PCC_REG_DBG_MUX_GRP_CFG0_RSVD_4_Msk                                                      (0x1UL << PCC_REG_DBG_MUX_GRP_CFG0_RSVD_4_Pos)
+
+#define PCC_REG_DBG_MUX_GRP_CFG0_R_DBG_MUX_GRP_SEL4_Pos                                          16U
+#define PCC_REG_DBG_MUX_GRP_CFG0_R_DBG_MUX_GRP_SEL4_Msk                                          (0x7UL << PCC_REG_DBG_MUX_GRP_CFG0_R_DBG_MUX_GRP_SEL4_Pos)
+
+#define PCC_REG_DBG_MUX_GRP_CFG0_RSVD_3_Pos                                                      19U
+#define PCC_REG_DBG_MUX_GRP_CFG0_RSVD_3_Msk                                                      (0x1UL << PCC_REG_DBG_MUX_GRP_CFG0_RSVD_3_Pos)
+
+#define PCC_REG_DBG_MUX_GRP_CFG0_R_DBG_MUX_GRP_SEL5_Pos                                          20U
+#define PCC_REG_DBG_MUX_GRP_CFG0_R_DBG_MUX_GRP_SEL5_Msk                                          (0x7UL << PCC_REG_DBG_MUX_GRP_CFG0_R_DBG_MUX_GRP_SEL5_Pos)
+
+#define PCC_REG_DBG_MUX_GRP_CFG0_RSVD_2_Pos                                                      23U
+#define PCC_REG_DBG_MUX_GRP_CFG0_RSVD_2_Msk                                                      (0x1UL << PCC_REG_DBG_MUX_GRP_CFG0_RSVD_2_Pos)
+
+#define PCC_REG_DBG_MUX_GRP_CFG0_R_DBG_MUX_GRP_SEL6_Pos                                          24U
+#define PCC_REG_DBG_MUX_GRP_CFG0_R_DBG_MUX_GRP_SEL6_Msk                                          (0x7UL << PCC_REG_DBG_MUX_GRP_CFG0_R_DBG_MUX_GRP_SEL6_Pos)
+
+#define PCC_REG_DBG_MUX_GRP_CFG0_RSVD_1_Pos                                                      27U
+#define PCC_REG_DBG_MUX_GRP_CFG0_RSVD_1_Msk                                                      (0x1UL << PCC_REG_DBG_MUX_GRP_CFG0_RSVD_1_Pos)
+
+#define PCC_REG_DBG_MUX_GRP_CFG0_R_DBG_MUX_GRP_SEL7_Pos                                          28U
+#define PCC_REG_DBG_MUX_GRP_CFG0_R_DBG_MUX_GRP_SEL7_Msk                                          (0x7UL << PCC_REG_DBG_MUX_GRP_CFG0_R_DBG_MUX_GRP_SEL7_Pos)
+
+#define PCC_REG_DBG_MUX_GRP_CFG0_RSVD_Pos                                                        31U
+#define PCC_REG_DBG_MUX_GRP_CFG0_RSVD_Msk                                                        (0x1UL << PCC_REG_DBG_MUX_GRP_CFG0_RSVD_Pos)
+
+/* 0x3C0    0x4000_03c0
+    2:0     R/W     R_DBG_MUX_GRP_SEL8                              3'd0
+    3       R       RSVD_3                                          1'd0
+    6:4     R/W     R_DBG_MUX_GRP_SEL9                              3'd0
+    7       R       RSVD_2                                          1'd0
+    10:8    R/W     R_DBG_MUX_GRP_SEL10                             3'd0
+    11      R       RSVD_1                                          1'd0
+    14:12   R/W     R_DBG_MUX_GRP_SEL11                             3'd0
+    31:15   R       RSVD                                            1'd0
+ */
+typedef union _PCC_REG_DBG_MUX_GRP_CFG1_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t R_DBG_MUX_GRP_SEL8: 3;
+        uint32_t RSVD_3: 1;
+        uint32_t R_DBG_MUX_GRP_SEL9: 3;
+        uint32_t RSVD_2: 1;
+        uint32_t R_DBG_MUX_GRP_SEL10: 3;
+        uint32_t RSVD_1: 1;
+        uint32_t R_DBG_MUX_GRP_SEL11: 3;
+        uint32_t RSVD: 17;
+    };
+} PCC_REG_DBG_MUX_GRP_CFG1_TYPE;
+
+/*0x4000_03c0 PCC_REG_DBG_MUX_GRP_CFG1*/
+#define PCC_REG_DBG_MUX_GRP_CFG1_R_DBG_MUX_GRP_SEL8_Pos                                          0U
+#define PCC_REG_DBG_MUX_GRP_CFG1_R_DBG_MUX_GRP_SEL8_Msk                                          (0x7UL << PCC_REG_DBG_MUX_GRP_CFG1_R_DBG_MUX_GRP_SEL8_Pos)
+
+#define PCC_REG_DBG_MUX_GRP_CFG1_RSVD_3_Pos                                                      3U
+#define PCC_REG_DBG_MUX_GRP_CFG1_RSVD_3_Msk                                                      (0x1UL << PCC_REG_DBG_MUX_GRP_CFG1_RSVD_3_Pos)
+
+#define PCC_REG_DBG_MUX_GRP_CFG1_R_DBG_MUX_GRP_SEL9_Pos                                          4U
+#define PCC_REG_DBG_MUX_GRP_CFG1_R_DBG_MUX_GRP_SEL9_Msk                                          (0x7UL << PCC_REG_DBG_MUX_GRP_CFG1_R_DBG_MUX_GRP_SEL9_Pos)
+
+#define PCC_REG_DBG_MUX_GRP_CFG1_RSVD_2_Pos                                                      7U
+#define PCC_REG_DBG_MUX_GRP_CFG1_RSVD_2_Msk                                                      (0x1UL << PCC_REG_DBG_MUX_GRP_CFG1_RSVD_2_Pos)
+
+#define PCC_REG_DBG_MUX_GRP_CFG1_R_DBG_MUX_GRP_SEL10_Pos                                         8U
+#define PCC_REG_DBG_MUX_GRP_CFG1_R_DBG_MUX_GRP_SEL10_Msk                                         (0x7UL << PCC_REG_DBG_MUX_GRP_CFG1_R_DBG_MUX_GRP_SEL10_Pos)
+
+#define PCC_REG_DBG_MUX_GRP_CFG1_RSVD_1_Pos                                                      11U
+#define PCC_REG_DBG_MUX_GRP_CFG1_RSVD_1_Msk                                                      (0x1UL << PCC_REG_DBG_MUX_GRP_CFG1_RSVD_1_Pos)
+
+#define PCC_REG_DBG_MUX_GRP_CFG1_R_DBG_MUX_GRP_SEL11_Pos                                         12U
+#define PCC_REG_DBG_MUX_GRP_CFG1_R_DBG_MUX_GRP_SEL11_Msk                                         (0x7UL << PCC_REG_DBG_MUX_GRP_CFG1_R_DBG_MUX_GRP_SEL11_Pos)
+
+#define PCC_REG_DBG_MUX_GRP_CFG1_RSVD_Pos                                                        15U
+#define PCC_REG_DBG_MUX_GRP_CFG1_RSVD_Msk                                                        (0x1FFFFUL << PCC_REG_DBG_MUX_GRP_CFG1_RSVD_Pos)
+
+
+#define PCC_REG_BASE 0x40000000
+
+#define PCC_REG_READ(Offset)\
+    ((uint32_t)*((volatile uint32_t*)(PCC_REG_BASE+(Offset))))
+
+#define PCC_REG_WRITE(Offset, Value)\
+    ((*((volatile uint32_t*)(PCC_REG_BASE + (Offset)))) = (Value))
+
+#define PCC_REG_UPDATE(Offset, Mask, Value) \
+    do {\
+        uint32_t temp;\
+        temp = PCC_REG_READ(Offset) & ~(Mask);\
+        PCC_REG_WRITE(Offset, (temp | ((Value) & (Mask))));\
+    } while(0)
+
+#define PCC_REG_READ_BITFIELD(Offset, Bitfield)                   \
+    (((Offset##_TYPE)PCC_REG_READ(Offset)).Bitfield)
+
+#define PCC_REG_WRITE_BITFIELD(Offset, Bitfield, Value)           \
+    do {                                                        \
+        Offset##_TYPE temp = {.d32 = PCC_REG_READ(Offset)};       \
+        temp.Bitfield = Value;                                         \
+        PCC_REG_WRITE(Offset, temp.d32);                          \
+    } while(0)
+
+#endif //#define PCC_REG_H
diff --git a/bee/soc/inc/rtl87x2j/platform_reg.h b/bee/soc/inc/rtl87x2j/platform_reg.h
new file mode 100755
index 00000000..548205a0
--- /dev/null
+++ b/bee/soc/inc/rtl87x2j/platform_reg.h
@@ -0,0 +1,5849 @@
+#ifndef PLATFORM_REG_H
+#define PLATFORM_REG_H
+#include <stdint.h>
+
+/* ================================================================================ */
+/* ================                PLATFORM Register               ================ */
+/* ===========     Reference: RL7019_SoC_Vendor_register_table_250812A.xlsx     =========== */
+/* ================================================================================ */
+#define PLATFORM_REG_RSVD_0000                  0x0000
+#define PLATFORM_REG_LOW_PRI_INT_STATUS         0x0004
+#define PLATFORM_REG_LOW_PRI_INT_MODE           0x0008
+#define PLATFORM_REG_LOW_PRI_INT_EN             0x000c
+#define PLATFORM_BTMACinterrupt                 0x0010
+#define PLATFORM_RXIinterrupt                   0x0014
+#define PLATFORM_Interruptedgeoption            0x0018
+#define PLATFORM_REG_DEBUG_SEL                  0x001C
+#define PLATFORM_REG_DATA_FIFO_SWAP_CTRL        0x0020
+#define PLATFORM_DUMMY                          0x0024
+#define PLATFORM_REG_ENHTIMER_TRIG_CTRL         0x0028
+#define PLATFORM_REG_SYSTICK_TIMER_CTRL         0x002C
+#define PLATFORM_REG_SYSTICK_TIMER_CNT          0x0030
+#define PLATFORM_REG_TMETER_CTRL                0x0034
+#define PLATFORM_REG_TMETER_INT_STS             0x0038
+#define PLATFORM_REG_CM33_NMI_INT_EN            0x003C
+#define PLATFORM_REG_BIST_RSTN                  0x0040
+#define PLATFORM_REG_BIST_MODE                  0x0044
+#define PLATFORM_REG_DRF_BIST_MODE              0x0048
+#define PLATFORM_REG_BIST_TEST_RESUME           0x004C
+#define PLATFORM_REG_BIST_START_PAUSE           0x0050
+#define PLATFORM_REG_BIST_DONE                  0x0054
+#define PLATFORM_REG_BIST_FAIL                  0x0058
+#define PLATFORM_REG_DRF_BIST_DONE              0x005C
+#define PLATFORM_REG_DRF_BIST_FAIL              0x0060
+#define PLATFORM_REG_MCU_ROM0_MISR0             0x0064
+#define PLATFORM_REG_MCU_ROM0_MISR1             0x0068
+#define PLATFORM_REG_MCU_ROM1_MISR0             0x006C
+#define PLATFORM_REG_MCU_ROM1_MISR1             0x0070
+#define PLATFORM_REG_MCU_ROM2_MISR0             0x0074
+#define PLATFORM_REG_MCU_ROM2_MISR1             0x0078
+#define PLATFORM_REG_MCU_ROM3_MISR0             0x007C
+#define PLATFORM_REG_MCU_ROM3_MISR1             0x0080
+#define PLATFORM_REG_MCU_ROM4_MISR0             0x0084
+#define PLATFORM_REG_MCU_ROM4_MISR1             0x0088
+#define PLATFORM_REG_I2C_MAILBOX_OUT_DATA0      0x0090
+#define PLATFORM_REG_I2C_MAILBOX_OUT_DATA1      0x0094
+#define PLATFORM_REG_I2C_MAILBOX_IN_DATA0       0x0098
+#define PLATFORM_REG_I2C_MAILBOX_IN_DATA1       0x009C
+#define PLATFORM_REG_I2C_MAILBOX_CTRL           0x00A0
+#define PLATFORM_WIC_HANDSHAKE                  0x00A4
+#define PLATFORM_WKUP_REASON_CORE               0x00A8
+#define PLATFORM_Reserved                       0x00AC
+#define PLATFORM_Reserved_1                     0x00B0
+#define PLATFORM_Reserved_2                     0x00B4
+#define PLATFORM_REG_SNPS_SRAM_CTRL             0x00B8
+#define PLATFORM_Reserved_3                     0x00BC
+#define PLATFORM_Reserved_4                     0x00C0
+#define PLATFORM_Reserved_5                     0x00C4
+#define PLATFORM_REG_MBISR_DATA_SRAM_CTRL       0x00C8
+#define PLATFORM_REG_MBISR_BUF_SRAM_CTRL        0x00CC
+#define PLATFORM_REG_MBISR_SRAM_RESULT          0x00D0
+#define PLATFORM_REG_DYN_READ_EN                0x00D4
+#define PLATFORM_REG_BIST_LOOP_MODE             0x00D8
+#define PLATFORM_REG_BT_BIST_LOOP_MODE          0x00DC
+#define PLATFORM_REG_BT_BIST_RSTN               0x00E0
+#define PLATFORM_REG_BT_BIST_MODE               0x00E4
+#define PLATFORM_REG_BT_DRF_BIST_MODE           0x00E8
+#define PLATFORM_REG_BT_BIST_TEST_RESUME        0x00EC
+#define PLATFORM_REG_BT_BIST_START_PAUSE        0x00F0
+#define PLATFORM_REG_BT_BIST_DONE               0x00F4
+#define PLATFORM_REG_BT_BIST_FAIL               0x00F8
+#define PLATFORM_REG_BT_DRF_BIST_DONE           0x00FC
+#define PLATFORM_REG_BT_DRF_BIST_FAIL           0x0100
+#define PLATFORM_Reserved_6                     0x0130
+#define PLATFORM_Reserved_7                     0x0134
+#define PLATFORM_REG_WDT_CTL                    0x01E0
+#define PLATFORM_REG_WDT_KICK                   0x01E4
+#define PLATFORM_REG_WDT_CURRENT                0x01E8
+#define PLATFORM_REG_WDT_VER                    0x01EC
+#define PLATFORM_REG_WDT_CLK_QACTIVE_CTL        0x01F0
+#define PLATFORM_RNGControlRegister             0x0200
+#define PLATFORM_Reserved_8                     0x0204
+#define PLATFORM_Reserved_9                     0x0208
+#define PLATFORM_Reserved_10                    0x020C
+#define PLATFORM_Reserved_11                    0x0210
+#define PLATFORM_Reserved_12                    0x0214
+#define PLATFORM_Reserved_13                    0x0218
+#define PLATFORM_RNG_return0                    0x021C
+#define PLATFORM_RNG_return1                    0x0220
+#define PLATFORM_RNG_return2                    0x0224
+#define PLATFORM_RNG_result                     0x0228
+#define PLATFORM_RNG_lfsr_poly_lsb              0x022C
+#define PLATFORM_RNG_lfsr_poly_msb              0x0230
+#define PLATFORM_Reserved_14                    0x0234
+#define PLATFORM_RNG_POWER                      0x0238
+#define PLATFORM_RNG_st                         0x023C
+#define PLATFORM_RNG_st_return                  0x0240
+#define PLATFORM_Reserved_15                    0x0244
+#define PLATFORM_Reserved_16                    0x0248
+#define PLATFORM_Reserved_17                    0x024C
+#define PLATFORM_Reserved_18                    0x0250
+#define PLATFORM_RNGinterrupt                   0x0254
+#define PLATFORM_Reserved_19                    0x0258
+#define PLATFORM_Reserved_20                    0x025C
+#define PLATFORM_RNG_st_thr_err                 0x0260
+#define PLATFORM_RNGinterruptenable             0x0264
+#define PLATFORM_SPIC0PGMfifointerrtup0         0x02cc
+#define PLATFORM_SPIC0PGMfifointerrtup1         0x02d0
+#define PLATFORM_SPIC0PGMfifointerrtup2         0x02d4
+#define PLATFORM_SPIC0PGMfifointerrtup3         0x02d8
+#define PLATFORM_SPIC0PGMfifointerrtup4         0x02dc
+#define PLATFORM_SPIC0PGMfifointerrtup5         0x02e0
+#define PLATFORM_SPIC0PGMfifointerrtup6         0x02e4
+#define PLATFORM_SPIC0PGMfifointerrtup7         0x02e8
+#define PLATFORM_REG_ENHTIMER_TASK_EVNT_STS     0x02ec
+#define PLATFORM_REG_KEYSCAN_TASK_EVNT_STS      0x02f0
+#define PLATFORM_REG_TIMER1_EVNT_STS            0x02f4
+#define PLATFORM_REG_TIMER1_TASK_STS            0x02f8
+#define PLATFORM_REG_GPIO_0_EVNT_STS            0x02fc
+#define PLATFORM_REG_GPIO_1_EVENT_STS           0x0300
+#define PLATFORM_REG_GPIO_0_TASK_DRCLR_STS      0x0314
+#define PLATFORM_REG_GPIO_1_TASK_DRCLR_STS      0x0318
+#define PLATFORM_REG_GPIO_0_TASK_DRSET_STS      0x031c
+#define PLATFORM_REG_GPIO_1_TASK_DRSET_STS      0x0320
+#define PLATFORM_REG_GPIO_0_TASK_DRTOGGLE_STS   0x0324
+#define PLATFORM_REG_GPIO_1_TASK_DRTOGGLE_STS   0x0328
+#define PLATFORM_REG_GIRDA_TASK_EVNT_STS        0x0344
+#define PLATFORM_REG_I2C0_TASK_EVNT_STS         0x0348
+#define PLATFORM_REG_I2C1_TASK_EVNT_STS         0x034c
+#define PLATFORM_REG_AUXADC_TASK_EVNT_STS       0x0350
+#define PLATFORM_REG_SPI3WIRE_TASK_EVNT_STS     0x0354
+#define PLATFORM_REG_SPI0DUAL_TASK_EVNT_STS     0x0358
+#define PLATFORM_REG_SPI1MST_TASK_EVNT_STS      0x035c
+#define PLATFORM_REG_TMETER_TASK_EVNT_STS       0x0364
+#define PLATFORM_REG_DMA_TASK_EVNT_STS          0x0368
+#define PLATFORM_REG_SDMK_TASK_EVNT_STS         0x036C
+#define PLATFORM_REG_OSC10M_CAL_TASK_EVNT_STS   0x0370
+#define PLATFORM_REG_OSC80M_CAL_TASK_EVNT_STS   0x0374
+
+/* 0x0000   0x4000_6000
+    31:0    R       RESERVED                                            32'h0
+ */
+typedef union _PLATFORM_REG_RSVD_0000_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED;
+    };
+} PLATFORM_REG_RSVD_0000_TYPE;
+
+/*0x4000_6000 PLATFORM_REG_RSVD_0000*/
+#define PLATFORM_REG_RSVD_0000_RESERVED_Pos                                                                  0U
+#define PLATFORM_REG_RSVD_0000_RESERVED_Msk                                                                  (0xFFFFFFFFUL << PLATFORM_REG_RSVD_0000_RESERVED_Pos)
+
+/* 0x0004   0x4000_6004
+    0       R       RESERVED_15                                         0
+    1       R       RESERVED_14                                         0
+    2       R       RESERVED_13                                         0
+    3       R       RESERVED_12                                         0
+    4       R       RESERVED_11                                         0
+    5       R       RESERVED_10                                         0
+    6       R       RESERVED_9                                          0
+    7       R       RESERVED_8                                          0
+    8       R       RESERVED_7                                          0
+    9       R       RESERVED_6                                          0
+    10      R       RESERVED_5                                          0
+    11      R       RESERVED_4                                          0
+    12      R       RESERVED_3                                          0
+    13      R       RESERVED_2                                          0
+    14      R       RESERVED_1                                          0
+    15      R/W1C   utmi_resume_intr                                    0
+    31:16   R       RESERVED                                            15'h0
+ */
+typedef union _PLATFORM_REG_LOW_PRI_INT_STATUS_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED_15: 1;
+        uint32_t RESERVED_14: 1;
+        uint32_t RESERVED_13: 1;
+        uint32_t RESERVED_12: 1;
+        uint32_t RESERVED_11: 1;
+        uint32_t RESERVED_10: 1;
+        uint32_t RESERVED_9: 1;
+        uint32_t RESERVED_8: 1;
+        uint32_t RESERVED_7: 1;
+        uint32_t RESERVED_6: 1;
+        uint32_t RESERVED_5: 1;
+        uint32_t RESERVED_4: 1;
+        uint32_t RESERVED_3: 1;
+        uint32_t RESERVED_2: 1;
+        uint32_t RESERVED_1: 1;
+        uint32_t utmi_resume_intr: 1;
+        uint32_t RESERVED: 16;
+    };
+} PLATFORM_REG_LOW_PRI_INT_STATUS_TYPE;
+
+/*0x4000_6004 PLATFORM_REG_LOW_PRI_INT_STATUS*/
+#define PLATFORM_REG_LOW_PRI_INT_STATUS_RESERVED_15_Pos                                                      0U
+#define PLATFORM_REG_LOW_PRI_INT_STATUS_RESERVED_15_Msk                                                      (0x1UL << PLATFORM_REG_LOW_PRI_INT_STATUS_RESERVED_15_Pos)
+
+#define PLATFORM_REG_LOW_PRI_INT_STATUS_RESERVED_14_Pos                                                      1U
+#define PLATFORM_REG_LOW_PRI_INT_STATUS_RESERVED_14_Msk                                                      (0x1UL << PLATFORM_REG_LOW_PRI_INT_STATUS_RESERVED_14_Pos)
+
+#define PLATFORM_REG_LOW_PRI_INT_STATUS_RESERVED_13_Pos                                                      2U
+#define PLATFORM_REG_LOW_PRI_INT_STATUS_RESERVED_13_Msk                                                      (0x1UL << PLATFORM_REG_LOW_PRI_INT_STATUS_RESERVED_13_Pos)
+
+#define PLATFORM_REG_LOW_PRI_INT_STATUS_RESERVED_12_Pos                                                      3U
+#define PLATFORM_REG_LOW_PRI_INT_STATUS_RESERVED_12_Msk                                                      (0x1UL << PLATFORM_REG_LOW_PRI_INT_STATUS_RESERVED_12_Pos)
+
+#define PLATFORM_REG_LOW_PRI_INT_STATUS_RESERVED_11_Pos                                                      4U
+#define PLATFORM_REG_LOW_PRI_INT_STATUS_RESERVED_11_Msk                                                      (0x1UL << PLATFORM_REG_LOW_PRI_INT_STATUS_RESERVED_11_Pos)
+
+#define PLATFORM_REG_LOW_PRI_INT_STATUS_RESERVED_10_Pos                                                      5U
+#define PLATFORM_REG_LOW_PRI_INT_STATUS_RESERVED_10_Msk                                                      (0x1UL << PLATFORM_REG_LOW_PRI_INT_STATUS_RESERVED_10_Pos)
+
+#define PLATFORM_REG_LOW_PRI_INT_STATUS_RESERVED_9_Pos                                                       6U
+#define PLATFORM_REG_LOW_PRI_INT_STATUS_RESERVED_9_Msk                                                       (0x1UL << PLATFORM_REG_LOW_PRI_INT_STATUS_RESERVED_9_Pos)
+
+#define PLATFORM_REG_LOW_PRI_INT_STATUS_RESERVED_8_Pos                                                       7U
+#define PLATFORM_REG_LOW_PRI_INT_STATUS_RESERVED_8_Msk                                                       (0x1UL << PLATFORM_REG_LOW_PRI_INT_STATUS_RESERVED_8_Pos)
+
+#define PLATFORM_REG_LOW_PRI_INT_STATUS_RESERVED_7_Pos                                                       8U
+#define PLATFORM_REG_LOW_PRI_INT_STATUS_RESERVED_7_Msk                                                       (0x1UL << PLATFORM_REG_LOW_PRI_INT_STATUS_RESERVED_7_Pos)
+
+#define PLATFORM_REG_LOW_PRI_INT_STATUS_RESERVED_6_Pos                                                       9U
+#define PLATFORM_REG_LOW_PRI_INT_STATUS_RESERVED_6_Msk                                                       (0x1UL << PLATFORM_REG_LOW_PRI_INT_STATUS_RESERVED_6_Pos)
+
+#define PLATFORM_REG_LOW_PRI_INT_STATUS_RESERVED_5_Pos                                                       10U
+#define PLATFORM_REG_LOW_PRI_INT_STATUS_RESERVED_5_Msk                                                       (0x1UL << PLATFORM_REG_LOW_PRI_INT_STATUS_RESERVED_5_Pos)
+
+#define PLATFORM_REG_LOW_PRI_INT_STATUS_RESERVED_4_Pos                                                       11U
+#define PLATFORM_REG_LOW_PRI_INT_STATUS_RESERVED_4_Msk                                                       (0x1UL << PLATFORM_REG_LOW_PRI_INT_STATUS_RESERVED_4_Pos)
+
+#define PLATFORM_REG_LOW_PRI_INT_STATUS_RESERVED_3_Pos                                                       12U
+#define PLATFORM_REG_LOW_PRI_INT_STATUS_RESERVED_3_Msk                                                       (0x1UL << PLATFORM_REG_LOW_PRI_INT_STATUS_RESERVED_3_Pos)
+
+#define PLATFORM_REG_LOW_PRI_INT_STATUS_RESERVED_2_Pos                                                       13U
+#define PLATFORM_REG_LOW_PRI_INT_STATUS_RESERVED_2_Msk                                                       (0x1UL << PLATFORM_REG_LOW_PRI_INT_STATUS_RESERVED_2_Pos)
+
+#define PLATFORM_REG_LOW_PRI_INT_STATUS_RESERVED_1_Pos                                                       14U
+#define PLATFORM_REG_LOW_PRI_INT_STATUS_RESERVED_1_Msk                                                       (0x1UL << PLATFORM_REG_LOW_PRI_INT_STATUS_RESERVED_1_Pos)
+
+#define PLATFORM_REG_LOW_PRI_INT_STATUS_utmi_resume_intr_Pos                                                 15U
+#define PLATFORM_REG_LOW_PRI_INT_STATUS_utmi_resume_intr_Msk                                                 (0x1UL << PLATFORM_REG_LOW_PRI_INT_STATUS_utmi_resume_intr_Pos)
+
+#define PLATFORM_REG_LOW_PRI_INT_STATUS_RESERVED_Pos                                                         16U
+#define PLATFORM_REG_LOW_PRI_INT_STATUS_RESERVED_Msk                                                         (0xFFFFUL << PLATFORM_REG_LOW_PRI_INT_STATUS_RESERVED_Pos)
+
+/* 0x0008   0x4000_6008
+    15:0    R/W     BIT_LOW_PRI_INT_MODE                                16'hFFFF
+    31:16   R       RSVD                                                16'h0
+ */
+typedef union _PLATFORM_REG_LOW_PRI_INT_MODE_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t BIT_LOW_PRI_INT_MODE: 16;
+        uint32_t RSVD: 16;
+    };
+} PLATFORM_REG_LOW_PRI_INT_MODE_TYPE;
+
+/*0x4000_6008 PLATFORM_REG_LOW_PRI_INT_MODE*/
+#define PLATFORM_REG_LOW_PRI_INT_MODE_BIT_LOW_PRI_INT_MODE_Pos                                               0U
+#define PLATFORM_REG_LOW_PRI_INT_MODE_BIT_LOW_PRI_INT_MODE_Msk                                               (0xFFFFUL << PLATFORM_REG_LOW_PRI_INT_MODE_BIT_LOW_PRI_INT_MODE_Pos)
+
+#define PLATFORM_REG_LOW_PRI_INT_MODE_RSVD_Pos                                                               16U
+#define PLATFORM_REG_LOW_PRI_INT_MODE_RSVD_Msk                                                               (0xFFFFUL << PLATFORM_REG_LOW_PRI_INT_MODE_RSVD_Pos)
+
+/* 0x000c   0x4000_600c
+    15:0    R/W     BIT_LOW_PRI_INT_EN                                  16'h0
+    31:16   R       RSVD                                                16'h0
+ */
+typedef union _PLATFORM_REG_LOW_PRI_INT_EN_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t BIT_LOW_PRI_INT_EN: 16;
+        uint32_t RSVD: 16;
+    };
+} PLATFORM_REG_LOW_PRI_INT_EN_TYPE;
+
+/*0x4000_600c PLATFORM_REG_LOW_PRI_INT_EN*/
+#define PLATFORM_REG_LOW_PRI_INT_EN_BIT_LOW_PRI_INT_EN_Pos                                                   0U
+#define PLATFORM_REG_LOW_PRI_INT_EN_BIT_LOW_PRI_INT_EN_Msk                                                   (0xFFFFUL << PLATFORM_REG_LOW_PRI_INT_EN_BIT_LOW_PRI_INT_EN_Pos)
+
+#define PLATFORM_REG_LOW_PRI_INT_EN_RSVD_Pos                                                                 16U
+#define PLATFORM_REG_LOW_PRI_INT_EN_RSVD_Msk                                                                 (0xFFFFUL << PLATFORM_REG_LOW_PRI_INT_EN_RSVD_Pos)
+
+/* 0x0010   0x4000_6010
+    0       R       timer_intr1andtimer_intr0                           0
+    1       R       bluewiz_intr_r                                      0
+    2       R       hci_dma_intr                                        0
+    3       R       btverdor_reg_intr                                   0
+    4       R       pro_intr_r                                          0
+    31:5    R       RSVD                                                27'h0
+ */
+typedef union _PLATFORM_BTMACinterrupt_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t timer_intr1andtimer_intr0: 1;
+        uint32_t bluewiz_intr_r: 1;
+        uint32_t hci_dma_intr: 1;
+        uint32_t btverdor_reg_intr: 1;
+        uint32_t pro_intr_r: 1;
+        uint32_t RSVD: 27;
+    };
+} PLATFORM_BTMACinterrupt_TYPE;
+
+/*0x4000_6010 PLATFORM_BTMACinterrupt*/
+#define PLATFORM_BTMACinterrupt_timer_intr1andtimer_intr0_Pos                                                0U
+#define PLATFORM_BTMACinterrupt_timer_intr1andtimer_intr0_Msk                                                (0x1UL << PLATFORM_BTMACinterrupt_timer_intr1andtimer_intr0_Pos)
+
+#define PLATFORM_BTMACinterrupt_bluewiz_intr_r_Pos                                                           1U
+#define PLATFORM_BTMACinterrupt_bluewiz_intr_r_Msk                                                           (0x1UL << PLATFORM_BTMACinterrupt_bluewiz_intr_r_Pos)
+
+#define PLATFORM_BTMACinterrupt_hci_dma_intr_Pos                                                             2U
+#define PLATFORM_BTMACinterrupt_hci_dma_intr_Msk                                                             (0x1UL << PLATFORM_BTMACinterrupt_hci_dma_intr_Pos)
+
+#define PLATFORM_BTMACinterrupt_btverdor_reg_intr_Pos                                                        3U
+#define PLATFORM_BTMACinterrupt_btverdor_reg_intr_Msk                                                        (0x1UL << PLATFORM_BTMACinterrupt_btverdor_reg_intr_Pos)
+
+#define PLATFORM_BTMACinterrupt_pro_intr_r_Pos                                                               4U
+#define PLATFORM_BTMACinterrupt_pro_intr_r_Msk                                                               (0x1UL << PLATFORM_BTMACinterrupt_pro_intr_r_Pos)
+
+#define PLATFORM_BTMACinterrupt_RSVD_Pos                                                                     5U
+#define PLATFORM_BTMACinterrupt_RSVD_Msk                                                                     (0x7FFFFFFUL << PLATFORM_BTMACinterrupt_RSVD_Pos)
+
+/* 0x0014   0x4000_6014
+    15:0    R       RSVD_2                                              16'h0
+    16      R       rxi300_intr                                         0
+    17      R       rdp_intr                                            0
+    18      R       rxi300_ah_intr                                      0
+    23:19   R       RSVD_1                                              5'h0
+    24      R/W     rxi300_intr_en                                      1
+    25      R/W     rdp_intr_en                                         0
+    26      R/W     rxi300_ah_intr_en                                   0
+    31:27   R       RSVD                                                5'h0
+ */
+typedef union _PLATFORM_RXIinterrupt_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RSVD_2: 16;
+        uint32_t rxi300_intr: 1;
+        uint32_t rdp_intr: 1;
+        uint32_t rxi300_ah_intr: 1;
+        uint32_t RSVD_1: 5;
+        uint32_t rxi300_intr_en: 1;
+        uint32_t rdp_intr_en: 1;
+        uint32_t rxi300_ah_intr_en: 1;
+        uint32_t RSVD: 5;
+    };
+} PLATFORM_RXIinterrupt_TYPE;
+
+/*0x4000_6014 PLATFORM_RXIinterrupt*/
+#define PLATFORM_RXIinterrupt_RSVD_2_Pos                                                                     0U
+#define PLATFORM_RXIinterrupt_RSVD_2_Msk                                                                     (0xFFFFUL << PLATFORM_RXIinterrupt_RSVD_2_Pos)
+
+#define PLATFORM_RXIinterrupt_rxi300_intr_Pos                                                                16U
+#define PLATFORM_RXIinterrupt_rxi300_intr_Msk                                                                (0x1UL << PLATFORM_RXIinterrupt_rxi300_intr_Pos)
+
+#define PLATFORM_RXIinterrupt_rdp_intr_Pos                                                                   17U
+#define PLATFORM_RXIinterrupt_rdp_intr_Msk                                                                   (0x1UL << PLATFORM_RXIinterrupt_rdp_intr_Pos)
+
+#define PLATFORM_RXIinterrupt_rxi300_ah_intr_Pos                                                             18U
+#define PLATFORM_RXIinterrupt_rxi300_ah_intr_Msk                                                             (0x1UL << PLATFORM_RXIinterrupt_rxi300_ah_intr_Pos)
+
+#define PLATFORM_RXIinterrupt_RSVD_1_Pos                                                                     19U
+#define PLATFORM_RXIinterrupt_RSVD_1_Msk                                                                     (0x1FUL << PLATFORM_RXIinterrupt_RSVD_1_Pos)
+
+#define PLATFORM_RXIinterrupt_rxi300_intr_en_Pos                                                             24U
+#define PLATFORM_RXIinterrupt_rxi300_intr_en_Msk                                                             (0x1UL << PLATFORM_RXIinterrupt_rxi300_intr_en_Pos)
+
+#define PLATFORM_RXIinterrupt_rdp_intr_en_Pos                                                                25U
+#define PLATFORM_RXIinterrupt_rdp_intr_en_Msk                                                                (0x1UL << PLATFORM_RXIinterrupt_rdp_intr_en_Pos)
+
+#define PLATFORM_RXIinterrupt_rxi300_ah_intr_en_Pos                                                          26U
+#define PLATFORM_RXIinterrupt_rxi300_ah_intr_en_Msk                                                          (0x1UL << PLATFORM_RXIinterrupt_rxi300_ah_intr_en_Pos)
+
+#define PLATFORM_RXIinterrupt_RSVD_Pos                                                                       27U
+#define PLATFORM_RXIinterrupt_RSVD_Msk                                                                       (0x1FUL << PLATFORM_RXIinterrupt_RSVD_Pos)
+
+/* 0x0018   0x4000_6018
+    15:0    R/W     int_pol                                             16'h0
+    31:16   R       RSVD                                                16'h0
+ */
+typedef union _PLATFORM_Interruptedgeoption_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t int_pol: 16;
+        uint32_t RSVD: 16;
+    };
+} PLATFORM_Interruptedgeoption_TYPE;
+
+/*0x4000_6018 PLATFORM_Interruptedgeoption*/
+#define PLATFORM_Interruptedgeoption_int_pol_Pos                                                             0U
+#define PLATFORM_Interruptedgeoption_int_pol_Msk                                                             (0xFFFFUL << PLATFORM_Interruptedgeoption_int_pol_Pos)
+
+#define PLATFORM_Interruptedgeoption_RSVD_Pos                                                                16U
+#define PLATFORM_Interruptedgeoption_RSVD_Msk                                                                (0xFFFFUL << PLATFORM_Interruptedgeoption_RSVD_Pos)
+
+/* 0x001C   0x4000_601c
+    13:0    R/W     debug_sel                                           14'h0
+    15:14   R/W     uart_force_cg_en                                    2'h0
+    23:16   R/W     IRQLATENCY                                          8'h0
+    24      R/W     uart0_pclk_no_latency_en                            1'h0
+    25      R/W     uart1_pclk_no_latency_en                            1'h0
+    26      R/W     uart2_pclk_no_latency_en                            1'h0
+    27      R/W     uart3_pclk_no_latency_en                            1'h0
+    28      R       RSVD_1                                              1'h0
+    29      R/W     spi_speed_up_sim                                    0
+    30      R       RSVD                                                0
+    31      R/W     uartlog_sir_inv                                     0
+ */
+typedef union _PLATFORM_REG_DEBUG_SEL_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t debug_sel: 14;
+        uint32_t uart_force_cg_en: 2;
+        uint32_t IRQLATENCY: 8;
+        uint32_t uart0_pclk_no_latency_en: 1;
+        uint32_t uart1_pclk_no_latency_en: 1;
+        uint32_t uart2_pclk_no_latency_en: 1;
+        uint32_t uart3_pclk_no_latency_en: 1;
+        uint32_t RSVD_1: 1;
+        uint32_t spi_speed_up_sim: 1;
+        uint32_t RSVD: 1;
+        uint32_t uartlog_sir_inv: 1;
+    };
+} PLATFORM_REG_DEBUG_SEL_TYPE;
+
+/*0x4000_601c PLATFORM_REG_DEBUG_SEL*/
+#define PLATFORM_REG_DEBUG_SEL_debug_sel_Pos                                                                 0U
+#define PLATFORM_REG_DEBUG_SEL_debug_sel_Msk                                                                 (0x3FFFUL << PLATFORM_REG_DEBUG_SEL_debug_sel_Pos)
+
+#define PLATFORM_REG_DEBUG_SEL_uart_force_cg_en_Pos                                                          14U
+#define PLATFORM_REG_DEBUG_SEL_uart_force_cg_en_Msk                                                          (0x3UL << PLATFORM_REG_DEBUG_SEL_uart_force_cg_en_Pos)
+
+#define PLATFORM_REG_DEBUG_SEL_IRQLATENCY_Pos                                                                16U
+#define PLATFORM_REG_DEBUG_SEL_IRQLATENCY_Msk                                                                (0xFFUL << PLATFORM_REG_DEBUG_SEL_IRQLATENCY_Pos)
+
+#define PLATFORM_REG_DEBUG_SEL_uart0_pclk_no_latency_en_Pos                                                  24U
+#define PLATFORM_REG_DEBUG_SEL_uart0_pclk_no_latency_en_Msk                                                  (0x1UL << PLATFORM_REG_DEBUG_SEL_uart0_pclk_no_latency_en_Pos)
+
+#define PLATFORM_REG_DEBUG_SEL_uart1_pclk_no_latency_en_Pos                                                  25U
+#define PLATFORM_REG_DEBUG_SEL_uart1_pclk_no_latency_en_Msk                                                  (0x1UL << PLATFORM_REG_DEBUG_SEL_uart1_pclk_no_latency_en_Pos)
+
+#define PLATFORM_REG_DEBUG_SEL_uart2_pclk_no_latency_en_Pos                                                  26U
+#define PLATFORM_REG_DEBUG_SEL_uart2_pclk_no_latency_en_Msk                                                  (0x1UL << PLATFORM_REG_DEBUG_SEL_uart2_pclk_no_latency_en_Pos)
+
+#define PLATFORM_REG_DEBUG_SEL_uart3_pclk_no_latency_en_Pos                                                  27U
+#define PLATFORM_REG_DEBUG_SEL_uart3_pclk_no_latency_en_Msk                                                  (0x1UL << PLATFORM_REG_DEBUG_SEL_uart3_pclk_no_latency_en_Pos)
+
+#define PLATFORM_REG_DEBUG_SEL_RSVD_1_Pos                                                                    28U
+#define PLATFORM_REG_DEBUG_SEL_RSVD_1_Msk                                                                    (0x1UL << PLATFORM_REG_DEBUG_SEL_RSVD_1_Pos)
+
+#define PLATFORM_REG_DEBUG_SEL_spi_speed_up_sim_Pos                                                          29U
+#define PLATFORM_REG_DEBUG_SEL_spi_speed_up_sim_Msk                                                          (0x1UL << PLATFORM_REG_DEBUG_SEL_spi_speed_up_sim_Pos)
+
+#define PLATFORM_REG_DEBUG_SEL_RSVD_Pos                                                                      30U
+#define PLATFORM_REG_DEBUG_SEL_RSVD_Msk                                                                      (0x1UL << PLATFORM_REG_DEBUG_SEL_RSVD_Pos)
+
+#define PLATFORM_REG_DEBUG_SEL_uartlog_sir_inv_Pos                                                           31U
+#define PLATFORM_REG_DEBUG_SEL_uartlog_sir_inv_Msk                                                           (0x1UL << PLATFORM_REG_DEBUG_SEL_uartlog_sir_inv_Pos)
+
+/* 0x0020   0x4000_6020
+    0       R/W     BIT_I2C0_TX_BIT_SWAP_EN                             0
+    1       R/W     BIT_I2C0_RX_BIT_SWAP_EN                             0
+    2       R/W     BIT_I2C1_TX_BIT_SWAP_EN                             0
+    3       R/W     BIT_I2C1_RX_BIT_SWAP_EN                             0
+    4       R/W     BIT_I2C2_TX_BIT_SWAP_EN                             0
+    5       R/W     BIT_I2C2_RX_BIT_SWAP_EN                             0
+    6       R/W     BIT_I2C3_TX_BIT_SWAP_EN                             0
+    7       R/W     BIT_I2C3_RX_BIT_SWAP_EN                             0
+    8       R/W     BIT_SPI0_TX_BIT_SWAP_EN                             0
+    9       R/W     BIT_SPI0_RX_BIT_SWAP_EN                             0
+    10      R/W     BIT_SPI1_TX_BIT_SWAP_EN                             0
+    11      R/W     BIT_SPI1_RX_BIT_SWAP_EN                             0
+    12      R/W     BIT_SPI2_TX_BIT_SWAP_EN                             0
+    13      R/W     BIT_SPI2_RX_BIT_SWAP_EN                             0
+    15:14   R       RSVD_1                                              2'h0
+    16      R/W     SPI0_TX_BYTE_SWAP_EN                                0
+    17      R/W     SPI0_RX_BYTE_SWAP_EN                                0
+    18      R/W     SPI1_TX_BYTE_SWAP_EN                                0
+    19      R/W     SPI1_RX_BYTE_SWAP_EN                                0
+    20      R/W     SPI2_TX_BYTE_SWAP_EN                                0
+    21      R/W     SPI2_RX_BYTE_SWAP_EN                                0
+    28:22   R       RSVD                                                7'h0
+    29      W1O     EFUSE_RP_bk1                                        0
+    30      W1O     EFUSE_WP                                            0
+    31      W1O     EFUSE_RP                                            0
+ */
+typedef union _PLATFORM_REG_DATA_FIFO_SWAP_CTRL_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t BIT_I2C0_TX_BIT_SWAP_EN: 1;
+        uint32_t BIT_I2C0_RX_BIT_SWAP_EN: 1;
+        uint32_t BIT_I2C1_TX_BIT_SWAP_EN: 1;
+        uint32_t BIT_I2C1_RX_BIT_SWAP_EN: 1;
+        uint32_t BIT_I2C2_TX_BIT_SWAP_EN: 1;
+        uint32_t BIT_I2C2_RX_BIT_SWAP_EN: 1;
+        uint32_t BIT_I2C3_TX_BIT_SWAP_EN: 1;
+        uint32_t BIT_I2C3_RX_BIT_SWAP_EN: 1;
+        uint32_t BIT_SPI0_TX_BIT_SWAP_EN: 1;
+        uint32_t BIT_SPI0_RX_BIT_SWAP_EN: 1;
+        uint32_t BIT_SPI1_TX_BIT_SWAP_EN: 1;
+        uint32_t BIT_SPI1_RX_BIT_SWAP_EN: 1;
+        uint32_t BIT_SPI2_TX_BIT_SWAP_EN: 1;
+        uint32_t BIT_SPI2_RX_BIT_SWAP_EN: 1;
+        uint32_t RSVD_1: 2;
+        uint32_t SPI0_TX_BYTE_SWAP_EN: 1;
+        uint32_t SPI0_RX_BYTE_SWAP_EN: 1;
+        uint32_t SPI1_TX_BYTE_SWAP_EN: 1;
+        uint32_t SPI1_RX_BYTE_SWAP_EN: 1;
+        uint32_t SPI2_TX_BYTE_SWAP_EN: 1;
+        uint32_t SPI2_RX_BYTE_SWAP_EN: 1;
+        uint32_t RSVD: 7;
+        uint32_t EFUSE_RP_bk1: 1;
+        uint32_t EFUSE_WP: 1;
+        uint32_t EFUSE_RP: 1;
+    };
+} PLATFORM_REG_DATA_FIFO_SWAP_CTRL_TYPE;
+
+/*0x4000_6020 PLATFORM_REG_DATA_FIFO_SWAP_CTRL*/
+#define PLATFORM_REG_DATA_FIFO_SWAP_CTRL_BIT_I2C0_TX_BIT_SWAP_EN_Pos                                         0U
+#define PLATFORM_REG_DATA_FIFO_SWAP_CTRL_BIT_I2C0_TX_BIT_SWAP_EN_Msk                                         (0x1UL << PLATFORM_REG_DATA_FIFO_SWAP_CTRL_BIT_I2C0_TX_BIT_SWAP_EN_Pos)
+
+#define PLATFORM_REG_DATA_FIFO_SWAP_CTRL_BIT_I2C0_RX_BIT_SWAP_EN_Pos                                         1U
+#define PLATFORM_REG_DATA_FIFO_SWAP_CTRL_BIT_I2C0_RX_BIT_SWAP_EN_Msk                                         (0x1UL << PLATFORM_REG_DATA_FIFO_SWAP_CTRL_BIT_I2C0_RX_BIT_SWAP_EN_Pos)
+
+#define PLATFORM_REG_DATA_FIFO_SWAP_CTRL_BIT_I2C1_TX_BIT_SWAP_EN_Pos                                         2U
+#define PLATFORM_REG_DATA_FIFO_SWAP_CTRL_BIT_I2C1_TX_BIT_SWAP_EN_Msk                                         (0x1UL << PLATFORM_REG_DATA_FIFO_SWAP_CTRL_BIT_I2C1_TX_BIT_SWAP_EN_Pos)
+
+#define PLATFORM_REG_DATA_FIFO_SWAP_CTRL_BIT_I2C1_RX_BIT_SWAP_EN_Pos                                         3U
+#define PLATFORM_REG_DATA_FIFO_SWAP_CTRL_BIT_I2C1_RX_BIT_SWAP_EN_Msk                                         (0x1UL << PLATFORM_REG_DATA_FIFO_SWAP_CTRL_BIT_I2C1_RX_BIT_SWAP_EN_Pos)
+
+#define PLATFORM_REG_DATA_FIFO_SWAP_CTRL_BIT_I2C2_TX_BIT_SWAP_EN_Pos                                         4U
+#define PLATFORM_REG_DATA_FIFO_SWAP_CTRL_BIT_I2C2_TX_BIT_SWAP_EN_Msk                                         (0x1UL << PLATFORM_REG_DATA_FIFO_SWAP_CTRL_BIT_I2C2_TX_BIT_SWAP_EN_Pos)
+
+#define PLATFORM_REG_DATA_FIFO_SWAP_CTRL_BIT_I2C2_RX_BIT_SWAP_EN_Pos                                         5U
+#define PLATFORM_REG_DATA_FIFO_SWAP_CTRL_BIT_I2C2_RX_BIT_SWAP_EN_Msk                                         (0x1UL << PLATFORM_REG_DATA_FIFO_SWAP_CTRL_BIT_I2C2_RX_BIT_SWAP_EN_Pos)
+
+#define PLATFORM_REG_DATA_FIFO_SWAP_CTRL_BIT_I2C3_TX_BIT_SWAP_EN_Pos                                         6U
+#define PLATFORM_REG_DATA_FIFO_SWAP_CTRL_BIT_I2C3_TX_BIT_SWAP_EN_Msk                                         (0x1UL << PLATFORM_REG_DATA_FIFO_SWAP_CTRL_BIT_I2C3_TX_BIT_SWAP_EN_Pos)
+
+#define PLATFORM_REG_DATA_FIFO_SWAP_CTRL_BIT_I2C3_RX_BIT_SWAP_EN_Pos                                         7U
+#define PLATFORM_REG_DATA_FIFO_SWAP_CTRL_BIT_I2C3_RX_BIT_SWAP_EN_Msk                                         (0x1UL << PLATFORM_REG_DATA_FIFO_SWAP_CTRL_BIT_I2C3_RX_BIT_SWAP_EN_Pos)
+
+#define PLATFORM_REG_DATA_FIFO_SWAP_CTRL_BIT_SPI0_TX_BIT_SWAP_EN_Pos                                         8U
+#define PLATFORM_REG_DATA_FIFO_SWAP_CTRL_BIT_SPI0_TX_BIT_SWAP_EN_Msk                                         (0x1UL << PLATFORM_REG_DATA_FIFO_SWAP_CTRL_BIT_SPI0_TX_BIT_SWAP_EN_Pos)
+
+#define PLATFORM_REG_DATA_FIFO_SWAP_CTRL_BIT_SPI0_RX_BIT_SWAP_EN_Pos                                         9U
+#define PLATFORM_REG_DATA_FIFO_SWAP_CTRL_BIT_SPI0_RX_BIT_SWAP_EN_Msk                                         (0x1UL << PLATFORM_REG_DATA_FIFO_SWAP_CTRL_BIT_SPI0_RX_BIT_SWAP_EN_Pos)
+
+#define PLATFORM_REG_DATA_FIFO_SWAP_CTRL_BIT_SPI1_TX_BIT_SWAP_EN_Pos                                         10U
+#define PLATFORM_REG_DATA_FIFO_SWAP_CTRL_BIT_SPI1_TX_BIT_SWAP_EN_Msk                                         (0x1UL << PLATFORM_REG_DATA_FIFO_SWAP_CTRL_BIT_SPI1_TX_BIT_SWAP_EN_Pos)
+
+#define PLATFORM_REG_DATA_FIFO_SWAP_CTRL_BIT_SPI1_RX_BIT_SWAP_EN_Pos                                         11U
+#define PLATFORM_REG_DATA_FIFO_SWAP_CTRL_BIT_SPI1_RX_BIT_SWAP_EN_Msk                                         (0x1UL << PLATFORM_REG_DATA_FIFO_SWAP_CTRL_BIT_SPI1_RX_BIT_SWAP_EN_Pos)
+
+#define PLATFORM_REG_DATA_FIFO_SWAP_CTRL_BIT_SPI2_TX_BIT_SWAP_EN_Pos                                         12U
+#define PLATFORM_REG_DATA_FIFO_SWAP_CTRL_BIT_SPI2_TX_BIT_SWAP_EN_Msk                                         (0x1UL << PLATFORM_REG_DATA_FIFO_SWAP_CTRL_BIT_SPI2_TX_BIT_SWAP_EN_Pos)
+
+#define PLATFORM_REG_DATA_FIFO_SWAP_CTRL_BIT_SPI2_RX_BIT_SWAP_EN_Pos                                         13U
+#define PLATFORM_REG_DATA_FIFO_SWAP_CTRL_BIT_SPI2_RX_BIT_SWAP_EN_Msk                                         (0x1UL << PLATFORM_REG_DATA_FIFO_SWAP_CTRL_BIT_SPI2_RX_BIT_SWAP_EN_Pos)
+
+#define PLATFORM_REG_DATA_FIFO_SWAP_CTRL_RSVD_1_Pos                                                          14U
+#define PLATFORM_REG_DATA_FIFO_SWAP_CTRL_RSVD_1_Msk                                                          (0x3UL << PLATFORM_REG_DATA_FIFO_SWAP_CTRL_RSVD_1_Pos)
+
+#define PLATFORM_REG_DATA_FIFO_SWAP_CTRL_SPI0_TX_BYTE_SWAP_EN_Pos                                            16U
+#define PLATFORM_REG_DATA_FIFO_SWAP_CTRL_SPI0_TX_BYTE_SWAP_EN_Msk                                            (0x1UL << PLATFORM_REG_DATA_FIFO_SWAP_CTRL_SPI0_TX_BYTE_SWAP_EN_Pos)
+
+#define PLATFORM_REG_DATA_FIFO_SWAP_CTRL_SPI0_RX_BYTE_SWAP_EN_Pos                                            17U
+#define PLATFORM_REG_DATA_FIFO_SWAP_CTRL_SPI0_RX_BYTE_SWAP_EN_Msk                                            (0x1UL << PLATFORM_REG_DATA_FIFO_SWAP_CTRL_SPI0_RX_BYTE_SWAP_EN_Pos)
+
+#define PLATFORM_REG_DATA_FIFO_SWAP_CTRL_SPI1_TX_BYTE_SWAP_EN_Pos                                            18U
+#define PLATFORM_REG_DATA_FIFO_SWAP_CTRL_SPI1_TX_BYTE_SWAP_EN_Msk                                            (0x1UL << PLATFORM_REG_DATA_FIFO_SWAP_CTRL_SPI1_TX_BYTE_SWAP_EN_Pos)
+
+#define PLATFORM_REG_DATA_FIFO_SWAP_CTRL_SPI1_RX_BYTE_SWAP_EN_Pos                                            19U
+#define PLATFORM_REG_DATA_FIFO_SWAP_CTRL_SPI1_RX_BYTE_SWAP_EN_Msk                                            (0x1UL << PLATFORM_REG_DATA_FIFO_SWAP_CTRL_SPI1_RX_BYTE_SWAP_EN_Pos)
+
+#define PLATFORM_REG_DATA_FIFO_SWAP_CTRL_SPI2_TX_BYTE_SWAP_EN_Pos                                            20U
+#define PLATFORM_REG_DATA_FIFO_SWAP_CTRL_SPI2_TX_BYTE_SWAP_EN_Msk                                            (0x1UL << PLATFORM_REG_DATA_FIFO_SWAP_CTRL_SPI2_TX_BYTE_SWAP_EN_Pos)
+
+#define PLATFORM_REG_DATA_FIFO_SWAP_CTRL_SPI2_RX_BYTE_SWAP_EN_Pos                                            21U
+#define PLATFORM_REG_DATA_FIFO_SWAP_CTRL_SPI2_RX_BYTE_SWAP_EN_Msk                                            (0x1UL << PLATFORM_REG_DATA_FIFO_SWAP_CTRL_SPI2_RX_BYTE_SWAP_EN_Pos)
+
+#define PLATFORM_REG_DATA_FIFO_SWAP_CTRL_RSVD_Pos                                                            22U
+#define PLATFORM_REG_DATA_FIFO_SWAP_CTRL_RSVD_Msk                                                            (0x7FUL << PLATFORM_REG_DATA_FIFO_SWAP_CTRL_RSVD_Pos)
+
+#define PLATFORM_REG_DATA_FIFO_SWAP_CTRL_EFUSE_RP_bk1_Pos                                                    29U
+#define PLATFORM_REG_DATA_FIFO_SWAP_CTRL_EFUSE_RP_bk1_Msk                                                    (0x1UL << PLATFORM_REG_DATA_FIFO_SWAP_CTRL_EFUSE_RP_bk1_Pos)
+
+#define PLATFORM_REG_DATA_FIFO_SWAP_CTRL_EFUSE_WP_Pos                                                        30U
+#define PLATFORM_REG_DATA_FIFO_SWAP_CTRL_EFUSE_WP_Msk                                                        (0x1UL << PLATFORM_REG_DATA_FIFO_SWAP_CTRL_EFUSE_WP_Pos)
+
+#define PLATFORM_REG_DATA_FIFO_SWAP_CTRL_EFUSE_RP_Pos                                                        31U
+#define PLATFORM_REG_DATA_FIFO_SWAP_CTRL_EFUSE_RP_Msk                                                        (0x1UL << PLATFORM_REG_DATA_FIFO_SWAP_CTRL_EFUSE_RP_Pos)
+
+/* 0x0024   0x4000_6024
+    0       R       RSVD_11                                             0
+    1       R       RSVD_10                                             0
+    2       R       RSVD_9                                              0
+    3       R       RSVD_8                                              0
+    4       R       RSVD_7                                              0
+    5       R       RSVD_6                                              0
+    6       R       RSVD_5                                              0
+    7       R       RSVD_4                                              0
+    8       R/W     spic0_mem_wr_en                                     0
+    9       R/W     spic1_mem_wr_en                                     0
+    10      W1O     dram_c2s_remap_dis                                  1
+    11      R/W     spic_icg_disable                                    0
+    12      R/W     ic_icg_disable                                      0
+    13      R/W     dmac_clk_always_disable                             0
+    14      R/W     dmac_clk_always_enable                              0
+    15      R/W     rxi300_auto_icg_en                                  1
+    23:16   R/W     RSVD_3                                              8'h0
+    24      W1O     dram_c2s_remap_dis_wlock                            0
+    25      R/W     RSVD_2                                              0
+    26      R/W     RSVD_1                                              0
+    30:27   R       RSVD                                                4'd0
+    31      R/W     fwpi_enable                                         1
+ */
+typedef union _PLATFORM_DUMMY_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RSVD_11: 1;
+        uint32_t RSVD_10: 1;
+        uint32_t RSVD_9: 1;
+        uint32_t RSVD_8: 1;
+        uint32_t RSVD_7: 1;
+        uint32_t RSVD_6: 1;
+        uint32_t RSVD_5: 1;
+        uint32_t RSVD_4: 1;
+        uint32_t spic0_mem_wr_en: 1;
+        uint32_t spic1_mem_wr_en: 1;
+        uint32_t dram_c2s_remap_dis: 1;
+        uint32_t spic_icg_disable: 1;
+        uint32_t ic_icg_disable: 1;
+        uint32_t dmac_clk_always_disable: 1;
+        uint32_t dmac_clk_always_enable: 1;
+        uint32_t rxi300_auto_icg_en: 1;
+        uint32_t RSVD_3: 8;
+        uint32_t dram_c2s_remap_dis_wlock: 1;
+        uint32_t RSVD_2: 1;
+        uint32_t RSVD_1: 1;
+        uint32_t RSVD: 4;
+        uint32_t fwpi_enable: 1;
+    };
+} PLATFORM_DUMMY_TYPE;
+
+/*0x4000_6024 PLATFORM_DUMMY*/
+#define PLATFORM_DUMMY_RSVD_11_Pos                                                                           0U
+#define PLATFORM_DUMMY_RSVD_11_Msk                                                                           (0x1UL << PLATFORM_DUMMY_RSVD_11_Pos)
+
+#define PLATFORM_DUMMY_RSVD_10_Pos                                                                           1U
+#define PLATFORM_DUMMY_RSVD_10_Msk                                                                           (0x1UL << PLATFORM_DUMMY_RSVD_10_Pos)
+
+#define PLATFORM_DUMMY_RSVD_9_Pos                                                                            2U
+#define PLATFORM_DUMMY_RSVD_9_Msk                                                                            (0x1UL << PLATFORM_DUMMY_RSVD_9_Pos)
+
+#define PLATFORM_DUMMY_RSVD_8_Pos                                                                            3U
+#define PLATFORM_DUMMY_RSVD_8_Msk                                                                            (0x1UL << PLATFORM_DUMMY_RSVD_8_Pos)
+
+#define PLATFORM_DUMMY_RSVD_7_Pos                                                                            4U
+#define PLATFORM_DUMMY_RSVD_7_Msk                                                                            (0x1UL << PLATFORM_DUMMY_RSVD_7_Pos)
+
+#define PLATFORM_DUMMY_RSVD_6_Pos                                                                            5U
+#define PLATFORM_DUMMY_RSVD_6_Msk                                                                            (0x1UL << PLATFORM_DUMMY_RSVD_6_Pos)
+
+#define PLATFORM_DUMMY_RSVD_5_Pos                                                                            6U
+#define PLATFORM_DUMMY_RSVD_5_Msk                                                                            (0x1UL << PLATFORM_DUMMY_RSVD_5_Pos)
+
+#define PLATFORM_DUMMY_RSVD_4_Pos                                                                            7U
+#define PLATFORM_DUMMY_RSVD_4_Msk                                                                            (0x1UL << PLATFORM_DUMMY_RSVD_4_Pos)
+
+#define PLATFORM_DUMMY_spic0_mem_wr_en_Pos                                                                   8U
+#define PLATFORM_DUMMY_spic0_mem_wr_en_Msk                                                                   (0x1UL << PLATFORM_DUMMY_spic0_mem_wr_en_Pos)
+
+#define PLATFORM_DUMMY_spic1_mem_wr_en_Pos                                                                   9U
+#define PLATFORM_DUMMY_spic1_mem_wr_en_Msk                                                                   (0x1UL << PLATFORM_DUMMY_spic1_mem_wr_en_Pos)
+
+#define PLATFORM_DUMMY_dram_c2s_remap_dis_Pos                                                                10U
+#define PLATFORM_DUMMY_dram_c2s_remap_dis_Msk                                                                (0x1UL << PLATFORM_DUMMY_dram_c2s_remap_dis_Pos)
+
+#define PLATFORM_DUMMY_spic_icg_disable_Pos                                                                  11U
+#define PLATFORM_DUMMY_spic_icg_disable_Msk                                                                  (0x1UL << PLATFORM_DUMMY_spic_icg_disable_Pos)
+
+#define PLATFORM_DUMMY_ic_icg_disable_Pos                                                                    12U
+#define PLATFORM_DUMMY_ic_icg_disable_Msk                                                                    (0x1UL << PLATFORM_DUMMY_ic_icg_disable_Pos)
+
+#define PLATFORM_DUMMY_dmac_clk_always_disable_Pos                                                           13U
+#define PLATFORM_DUMMY_dmac_clk_always_disable_Msk                                                           (0x1UL << PLATFORM_DUMMY_dmac_clk_always_disable_Pos)
+
+#define PLATFORM_DUMMY_dmac_clk_always_enable_Pos                                                            14U
+#define PLATFORM_DUMMY_dmac_clk_always_enable_Msk                                                            (0x1UL << PLATFORM_DUMMY_dmac_clk_always_enable_Pos)
+
+#define PLATFORM_DUMMY_rxi300_auto_icg_en_Pos                                                                15U
+#define PLATFORM_DUMMY_rxi300_auto_icg_en_Msk                                                                (0x1UL << PLATFORM_DUMMY_rxi300_auto_icg_en_Pos)
+
+#define PLATFORM_DUMMY_RSVD_3_Pos                                                                            16U
+#define PLATFORM_DUMMY_RSVD_3_Msk                                                                            (0xFFUL << PLATFORM_DUMMY_RSVD_3_Pos)
+
+#define PLATFORM_DUMMY_dram_c2s_remap_dis_wlock_Pos                                                          24U
+#define PLATFORM_DUMMY_dram_c2s_remap_dis_wlock_Msk                                                          (0x1UL << PLATFORM_DUMMY_dram_c2s_remap_dis_wlock_Pos)
+
+#define PLATFORM_DUMMY_RSVD_2_Pos                                                                            25U
+#define PLATFORM_DUMMY_RSVD_2_Msk                                                                            (0x1UL << PLATFORM_DUMMY_RSVD_2_Pos)
+
+#define PLATFORM_DUMMY_RSVD_1_Pos                                                                            26U
+#define PLATFORM_DUMMY_RSVD_1_Msk                                                                            (0x1UL << PLATFORM_DUMMY_RSVD_1_Pos)
+
+#define PLATFORM_DUMMY_RSVD_Pos                                                                              27U
+#define PLATFORM_DUMMY_RSVD_Msk                                                                              (0xFUL << PLATFORM_DUMMY_RSVD_Pos)
+
+#define PLATFORM_DUMMY_fwpi_enable_Pos                                                                       31U
+#define PLATFORM_DUMMY_fwpi_enable_Msk                                                                       (0x1UL << PLATFORM_DUMMY_fwpi_enable_Pos)
+
+/* 0x0028   0x4000_6028
+    5:0     R/W     enhtimer_gpio_trig_sel                              6'h3f
+    6       R/W     RSVD_2                                              0
+    7       R/W     RSVD_1                                              0
+    23:8    R/W     enhtimer_gpio_trig_deb_cnt_limit                    16'h1
+    24      R/W     enhtimer_gpio_trig_deb_en                           1'h0
+    25      R       enhtimer_gpio_trig_deb_sts                          1'h0
+    29:26   R       RSVD                                                4'h0
+    30      R/W     enhtimer_gpio_deb_clk_q_ch_qactive_fw_manual_data   1'h0
+    31      R/W     enhtimer_gpio_deb_clk_q_ch_qactive_fw_manual_en     1'h0
+ */
+typedef union _PLATFORM_REG_ENHTIMER_TRIG_CTRL_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t enhtimer_gpio_trig_sel: 6;
+        uint32_t RSVD_2: 1;
+        uint32_t RSVD_1: 1;
+        uint32_t enhtimer_gpio_trig_deb_cnt_limit: 16;
+        uint32_t enhtimer_gpio_trig_deb_en: 1;
+        uint32_t enhtimer_gpio_trig_deb_sts: 1;
+        uint32_t RSVD: 4;
+        uint32_t enhtimer_gpio_deb_clk_q_ch_qactive_fw_manual_data: 1;
+        uint32_t enhtimer_gpio_deb_clk_q_ch_qactive_fw_manual_en: 1;
+    };
+} PLATFORM_REG_ENHTIMER_TRIG_CTRL_TYPE;
+
+/*0x4000_6028 PLATFORM_REG_ENHTIMER_TRIG_CTRL*/
+#define PLATFORM_REG_ENHTIMER_TRIG_CTRL_enhtimer_gpio_trig_sel_Pos                                           0U
+#define PLATFORM_REG_ENHTIMER_TRIG_CTRL_enhtimer_gpio_trig_sel_Msk                                           (0x3FUL << PLATFORM_REG_ENHTIMER_TRIG_CTRL_enhtimer_gpio_trig_sel_Pos)
+
+#define PLATFORM_REG_ENHTIMER_TRIG_CTRL_RSVD_2_Pos                                                           6U
+#define PLATFORM_REG_ENHTIMER_TRIG_CTRL_RSVD_2_Msk                                                           (0x1UL << PLATFORM_REG_ENHTIMER_TRIG_CTRL_RSVD_2_Pos)
+
+#define PLATFORM_REG_ENHTIMER_TRIG_CTRL_RSVD_1_Pos                                                           7U
+#define PLATFORM_REG_ENHTIMER_TRIG_CTRL_RSVD_1_Msk                                                           (0x1UL << PLATFORM_REG_ENHTIMER_TRIG_CTRL_RSVD_1_Pos)
+
+#define PLATFORM_REG_ENHTIMER_TRIG_CTRL_enhtimer_gpio_trig_deb_cnt_limit_Pos                                 8U
+#define PLATFORM_REG_ENHTIMER_TRIG_CTRL_enhtimer_gpio_trig_deb_cnt_limit_Msk                                 (0xFFFFUL << PLATFORM_REG_ENHTIMER_TRIG_CTRL_enhtimer_gpio_trig_deb_cnt_limit_Pos)
+
+#define PLATFORM_REG_ENHTIMER_TRIG_CTRL_enhtimer_gpio_trig_deb_en_Pos                                        24U
+#define PLATFORM_REG_ENHTIMER_TRIG_CTRL_enhtimer_gpio_trig_deb_en_Msk                                        (0x1UL << PLATFORM_REG_ENHTIMER_TRIG_CTRL_enhtimer_gpio_trig_deb_en_Pos)
+
+#define PLATFORM_REG_ENHTIMER_TRIG_CTRL_enhtimer_gpio_trig_deb_sts_Pos                                       25U
+#define PLATFORM_REG_ENHTIMER_TRIG_CTRL_enhtimer_gpio_trig_deb_sts_Msk                                       (0x1UL << PLATFORM_REG_ENHTIMER_TRIG_CTRL_enhtimer_gpio_trig_deb_sts_Pos)
+
+#define PLATFORM_REG_ENHTIMER_TRIG_CTRL_RSVD_Pos                                                             26U
+#define PLATFORM_REG_ENHTIMER_TRIG_CTRL_RSVD_Msk                                                             (0xFUL << PLATFORM_REG_ENHTIMER_TRIG_CTRL_RSVD_Pos)
+
+#define PLATFORM_REG_ENHTIMER_TRIG_CTRL_enhtimer_gpio_deb_clk_q_ch_qactive_fw_manual_data_Pos                30U
+#define PLATFORM_REG_ENHTIMER_TRIG_CTRL_enhtimer_gpio_deb_clk_q_ch_qactive_fw_manual_data_Msk                (0x1UL << PLATFORM_REG_ENHTIMER_TRIG_CTRL_enhtimer_gpio_deb_clk_q_ch_qactive_fw_manual_data_Pos)
+
+#define PLATFORM_REG_ENHTIMER_TRIG_CTRL_enhtimer_gpio_deb_clk_q_ch_qactive_fw_manual_en_Pos                  31U
+#define PLATFORM_REG_ENHTIMER_TRIG_CTRL_enhtimer_gpio_deb_clk_q_ch_qactive_fw_manual_en_Msk                  (0x1UL << PLATFORM_REG_ENHTIMER_TRIG_CTRL_enhtimer_gpio_deb_clk_q_ch_qactive_fw_manual_en_Pos)
+
+/* 0x002C   0x4000_602c
+    0       R/W     r_systick_timer_manual_rstb                         0
+    1       R/W     r_systick_timer_rst_sel                             1
+    31:2    R       RSVD                                                30'h0
+ */
+typedef union _PLATFORM_REG_SYSTICK_TIMER_CTRL_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t r_systick_timer_manual_rstb: 1;
+        uint32_t r_systick_timer_rst_sel: 1;
+        uint32_t RSVD: 30;
+    };
+} PLATFORM_REG_SYSTICK_TIMER_CTRL_TYPE;
+
+/*0x4000_602c PLATFORM_REG_SYSTICK_TIMER_CTRL*/
+#define PLATFORM_REG_SYSTICK_TIMER_CTRL_r_systick_timer_manual_rstb_Pos                                      0U
+#define PLATFORM_REG_SYSTICK_TIMER_CTRL_r_systick_timer_manual_rstb_Msk                                      (0x1UL << PLATFORM_REG_SYSTICK_TIMER_CTRL_r_systick_timer_manual_rstb_Pos)
+
+#define PLATFORM_REG_SYSTICK_TIMER_CTRL_r_systick_timer_rst_sel_Pos                                          1U
+#define PLATFORM_REG_SYSTICK_TIMER_CTRL_r_systick_timer_rst_sel_Msk                                          (0x1UL << PLATFORM_REG_SYSTICK_TIMER_CTRL_r_systick_timer_rst_sel_Pos)
+
+#define PLATFORM_REG_SYSTICK_TIMER_CTRL_RSVD_Pos                                                             2U
+#define PLATFORM_REG_SYSTICK_TIMER_CTRL_RSVD_Msk                                                             (0x3FFFFFFFUL << PLATFORM_REG_SYSTICK_TIMER_CTRL_RSVD_Pos)
+
+/* 0x0030   0x4000_6030
+    31:0    R       cpu_systick_timer_cnt                               32'h0
+ */
+typedef union _PLATFORM_REG_SYSTICK_TIMER_CNT_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t cpu_systick_timer_cnt;
+    };
+} PLATFORM_REG_SYSTICK_TIMER_CNT_TYPE;
+
+/*0x4000_6030 PLATFORM_REG_SYSTICK_TIMER_CNT*/
+#define PLATFORM_REG_SYSTICK_TIMER_CNT_cpu_systick_timer_cnt_Pos                                             0U
+#define PLATFORM_REG_SYSTICK_TIMER_CNT_cpu_systick_timer_cnt_Msk                                             (0xFFFFFFFFUL << PLATFORM_REG_SYSTICK_TIMER_CNT_cpu_systick_timer_cnt_Pos)
+
+/* 0x0034   0x4000_6034
+    0       R/W     TIMER_INT_EN                                        1'b0
+    1       R/W     VLD_TIMER                                           1'b0
+    30:2    R       RSVD                                                29'h0
+    31      R/W     VLD_TIMER_FAKE_INFPGA                               1'b0
+ */
+typedef union _PLATFORM_REG_TMETER_CTRL_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t TIMER_INT_EN: 1;
+        uint32_t VLD_TIMER: 1;
+        uint32_t RSVD: 29;
+        uint32_t VLD_TIMER_FAKE_INFPGA: 1;
+    };
+} PLATFORM_REG_TMETER_CTRL_TYPE;
+
+/*0x4000_6034 PLATFORM_REG_TMETER_CTRL*/
+#define PLATFORM_REG_TMETER_CTRL_TIMER_INT_EN_Pos                                                            0U
+#define PLATFORM_REG_TMETER_CTRL_TIMER_INT_EN_Msk                                                            (0x1UL << PLATFORM_REG_TMETER_CTRL_TIMER_INT_EN_Pos)
+
+#define PLATFORM_REG_TMETER_CTRL_VLD_TIMER_Pos                                                               1U
+#define PLATFORM_REG_TMETER_CTRL_VLD_TIMER_Msk                                                               (0x1UL << PLATFORM_REG_TMETER_CTRL_VLD_TIMER_Pos)
+
+#define PLATFORM_REG_TMETER_CTRL_RSVD_Pos                                                                    2U
+#define PLATFORM_REG_TMETER_CTRL_RSVD_Msk                                                                    (0x1FFFFFFFUL << PLATFORM_REG_TMETER_CTRL_RSVD_Pos)
+
+#define PLATFORM_REG_TMETER_CTRL_VLD_TIMER_FAKE_INFPGA_Pos                                                   31U
+#define PLATFORM_REG_TMETER_CTRL_VLD_TIMER_FAKE_INFPGA_Msk                                                   (0x1UL << PLATFORM_REG_TMETER_CTRL_VLD_TIMER_FAKE_INFPGA_Pos)
+
+/* 0x0038   0x4000_6038
+    0       R/W1C   VLD_TIMER_INT                                       1'b0
+    31:1    R       RSVD                                                31'h0
+ */
+typedef union _PLATFORM_REG_TMETER_INT_STS_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t VLD_TIMER_INT: 1;
+        uint32_t RSVD: 31;
+    };
+} PLATFORM_REG_TMETER_INT_STS_TYPE;
+
+/*0x4000_6038 PLATFORM_REG_TMETER_INT_STS*/
+#define PLATFORM_REG_TMETER_INT_STS_VLD_TIMER_INT_Pos                                                        0U
+#define PLATFORM_REG_TMETER_INT_STS_VLD_TIMER_INT_Msk                                                        (0x1UL << PLATFORM_REG_TMETER_INT_STS_VLD_TIMER_INT_Pos)
+
+#define PLATFORM_REG_TMETER_INT_STS_RSVD_Pos                                                                 1U
+#define PLATFORM_REG_TMETER_INT_STS_RSVD_Msk                                                                 (0x7FFFFFFFUL << PLATFORM_REG_TMETER_INT_STS_RSVD_Pos)
+
+/* 0x003C   0x4000_603c
+    0       R/W     cm33_nmi_int_enable                                 1'b0
+    31:1    R       RSVD                                                31'h0
+ */
+typedef union _PLATFORM_REG_CM33_NMI_INT_EN_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t cm33_nmi_int_enable: 1;
+        uint32_t RSVD: 31;
+    };
+} PLATFORM_REG_CM33_NMI_INT_EN_TYPE;
+
+/*0x4000_603c PLATFORM_REG_CM33_NMI_INT_EN*/
+#define PLATFORM_REG_CM33_NMI_INT_EN_cm33_nmi_int_enable_Pos                                                 0U
+#define PLATFORM_REG_CM33_NMI_INT_EN_cm33_nmi_int_enable_Msk                                                 (0x1UL << PLATFORM_REG_CM33_NMI_INT_EN_cm33_nmi_int_enable_Pos)
+
+#define PLATFORM_REG_CM33_NMI_INT_EN_RSVD_Pos                                                                1U
+#define PLATFORM_REG_CM33_NMI_INT_EN_RSVD_Msk                                                                (0x7FFFFFFFUL << PLATFORM_REG_CM33_NMI_INT_EN_RSVD_Pos)
+
+/* 0x0040   0x4000_6040
+    0       R/W     bist_rstn_mcu_rom                                   0
+    1       R/W     bist_rstn_data_ram                                  0
+    2       R/W     bist_rstn_cpu_ram                                   0
+    3       R/W     bist_rstn_usb_ram                                   0
+    4       R/W     bist_rstn_can_ram                                   0
+    5       R/W     bist_rstn_cache_ram                                 0
+    6       R/W     bist_rstn_amu_ram                                   0
+    31:7    R       RSVD                                                25'h0
+ */
+typedef union _PLATFORM_REG_BIST_RSTN_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t bist_rstn_mcu_rom: 1;
+        uint32_t bist_rstn_data_ram: 1;
+        uint32_t bist_rstn_cpu_ram: 1;
+        uint32_t bist_rstn_usb_ram: 1;
+        uint32_t bist_rstn_can_ram: 1;
+        uint32_t bist_rstn_cache_ram: 1;
+        uint32_t bist_rstn_amu_ram: 1;
+        uint32_t RSVD: 25;
+    };
+} PLATFORM_REG_BIST_RSTN_TYPE;
+
+/*0x4000_6040 PLATFORM_REG_BIST_RSTN*/
+#define PLATFORM_REG_BIST_RSTN_bist_rstn_mcu_rom_Pos                                                         0U
+#define PLATFORM_REG_BIST_RSTN_bist_rstn_mcu_rom_Msk                                                         (0x1UL << PLATFORM_REG_BIST_RSTN_bist_rstn_mcu_rom_Pos)
+
+#define PLATFORM_REG_BIST_RSTN_bist_rstn_data_ram_Pos                                                        1U
+#define PLATFORM_REG_BIST_RSTN_bist_rstn_data_ram_Msk                                                        (0x1UL << PLATFORM_REG_BIST_RSTN_bist_rstn_data_ram_Pos)
+
+#define PLATFORM_REG_BIST_RSTN_bist_rstn_cpu_ram_Pos                                                         2U
+#define PLATFORM_REG_BIST_RSTN_bist_rstn_cpu_ram_Msk                                                         (0x1UL << PLATFORM_REG_BIST_RSTN_bist_rstn_cpu_ram_Pos)
+
+#define PLATFORM_REG_BIST_RSTN_bist_rstn_usb_ram_Pos                                                         3U
+#define PLATFORM_REG_BIST_RSTN_bist_rstn_usb_ram_Msk                                                         (0x1UL << PLATFORM_REG_BIST_RSTN_bist_rstn_usb_ram_Pos)
+
+#define PLATFORM_REG_BIST_RSTN_bist_rstn_can_ram_Pos                                                         4U
+#define PLATFORM_REG_BIST_RSTN_bist_rstn_can_ram_Msk                                                         (0x1UL << PLATFORM_REG_BIST_RSTN_bist_rstn_can_ram_Pos)
+
+#define PLATFORM_REG_BIST_RSTN_bist_rstn_cache_ram_Pos                                                       5U
+#define PLATFORM_REG_BIST_RSTN_bist_rstn_cache_ram_Msk                                                       (0x1UL << PLATFORM_REG_BIST_RSTN_bist_rstn_cache_ram_Pos)
+
+#define PLATFORM_REG_BIST_RSTN_bist_rstn_amu_ram_Pos                                                         6U
+#define PLATFORM_REG_BIST_RSTN_bist_rstn_amu_ram_Msk                                                         (0x1UL << PLATFORM_REG_BIST_RSTN_bist_rstn_amu_ram_Pos)
+
+#define PLATFORM_REG_BIST_RSTN_RSVD_Pos                                                                      7U
+#define PLATFORM_REG_BIST_RSTN_RSVD_Msk                                                                      (0x1FFFFFFUL << PLATFORM_REG_BIST_RSTN_RSVD_Pos)
+
+/* 0x0044   0x4000_6044
+    0       R/W     bist_mode_mcu_rom                                   0
+    1       R/W     bist_mode_data_ram                                  0
+    2       R/W     bist_mode_cpu_ram                                   0
+    3       R/W     bist_mode_usb_ram                                   0
+    4       R/W     bist_mode_can_ram                                   0
+    5       R/W     bist_mode_cache_ram                                 0
+    6       R/W     bist_mode_amu_ram                                   0
+    31:7    R       RSVD                                                25'h0
+ */
+typedef union _PLATFORM_REG_BIST_MODE_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t bist_mode_mcu_rom: 1;
+        uint32_t bist_mode_data_ram: 1;
+        uint32_t bist_mode_cpu_ram: 1;
+        uint32_t bist_mode_usb_ram: 1;
+        uint32_t bist_mode_can_ram: 1;
+        uint32_t bist_mode_cache_ram: 1;
+        uint32_t bist_mode_amu_ram: 1;
+        uint32_t RSVD: 25;
+    };
+} PLATFORM_REG_BIST_MODE_TYPE;
+
+/*0x4000_6044 PLATFORM_REG_BIST_MODE*/
+#define PLATFORM_REG_BIST_MODE_bist_mode_mcu_rom_Pos                                                         0U
+#define PLATFORM_REG_BIST_MODE_bist_mode_mcu_rom_Msk                                                         (0x1UL << PLATFORM_REG_BIST_MODE_bist_mode_mcu_rom_Pos)
+
+#define PLATFORM_REG_BIST_MODE_bist_mode_data_ram_Pos                                                        1U
+#define PLATFORM_REG_BIST_MODE_bist_mode_data_ram_Msk                                                        (0x1UL << PLATFORM_REG_BIST_MODE_bist_mode_data_ram_Pos)
+
+#define PLATFORM_REG_BIST_MODE_bist_mode_cpu_ram_Pos                                                         2U
+#define PLATFORM_REG_BIST_MODE_bist_mode_cpu_ram_Msk                                                         (0x1UL << PLATFORM_REG_BIST_MODE_bist_mode_cpu_ram_Pos)
+
+#define PLATFORM_REG_BIST_MODE_bist_mode_usb_ram_Pos                                                         3U
+#define PLATFORM_REG_BIST_MODE_bist_mode_usb_ram_Msk                                                         (0x1UL << PLATFORM_REG_BIST_MODE_bist_mode_usb_ram_Pos)
+
+#define PLATFORM_REG_BIST_MODE_bist_mode_can_ram_Pos                                                         4U
+#define PLATFORM_REG_BIST_MODE_bist_mode_can_ram_Msk                                                         (0x1UL << PLATFORM_REG_BIST_MODE_bist_mode_can_ram_Pos)
+
+#define PLATFORM_REG_BIST_MODE_bist_mode_cache_ram_Pos                                                       5U
+#define PLATFORM_REG_BIST_MODE_bist_mode_cache_ram_Msk                                                       (0x1UL << PLATFORM_REG_BIST_MODE_bist_mode_cache_ram_Pos)
+
+#define PLATFORM_REG_BIST_MODE_bist_mode_amu_ram_Pos                                                         6U
+#define PLATFORM_REG_BIST_MODE_bist_mode_amu_ram_Msk                                                         (0x1UL << PLATFORM_REG_BIST_MODE_bist_mode_amu_ram_Pos)
+
+#define PLATFORM_REG_BIST_MODE_RSVD_Pos                                                                      7U
+#define PLATFORM_REG_BIST_MODE_RSVD_Msk                                                                      (0x1FFFFFFUL << PLATFORM_REG_BIST_MODE_RSVD_Pos)
+
+/* 0x0048   0x4000_6048
+    0       R/W     bist_mode_drf_data_ram                              0
+    1       R/W     bist_mode_drf_cpu_ram                               0
+    2       R/W     bist_mode_drf_usb_ram                               0
+    3       R/W     bist_mode_drf_can_ram                               0
+    4       R/W     bist_mode_drf_cache_ram                             0
+    5       R/W     bist_mode_drf_amu_ram                               0
+    31:6    R       RSVD                                                26'h0
+ */
+typedef union _PLATFORM_REG_DRF_BIST_MODE_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t bist_mode_drf_data_ram: 1;
+        uint32_t bist_mode_drf_cpu_ram: 1;
+        uint32_t bist_mode_drf_usb_ram: 1;
+        uint32_t bist_mode_drf_can_ram: 1;
+        uint32_t bist_mode_drf_cache_ram: 1;
+        uint32_t bist_mode_drf_amu_ram: 1;
+        uint32_t RSVD: 26;
+    };
+} PLATFORM_REG_DRF_BIST_MODE_TYPE;
+
+/*0x4000_6048 PLATFORM_REG_DRF_BIST_MODE*/
+#define PLATFORM_REG_DRF_BIST_MODE_bist_mode_drf_data_ram_Pos                                                0U
+#define PLATFORM_REG_DRF_BIST_MODE_bist_mode_drf_data_ram_Msk                                                (0x1UL << PLATFORM_REG_DRF_BIST_MODE_bist_mode_drf_data_ram_Pos)
+
+#define PLATFORM_REG_DRF_BIST_MODE_bist_mode_drf_cpu_ram_Pos                                                 1U
+#define PLATFORM_REG_DRF_BIST_MODE_bist_mode_drf_cpu_ram_Msk                                                 (0x1UL << PLATFORM_REG_DRF_BIST_MODE_bist_mode_drf_cpu_ram_Pos)
+
+#define PLATFORM_REG_DRF_BIST_MODE_bist_mode_drf_usb_ram_Pos                                                 2U
+#define PLATFORM_REG_DRF_BIST_MODE_bist_mode_drf_usb_ram_Msk                                                 (0x1UL << PLATFORM_REG_DRF_BIST_MODE_bist_mode_drf_usb_ram_Pos)
+
+#define PLATFORM_REG_DRF_BIST_MODE_bist_mode_drf_can_ram_Pos                                                 3U
+#define PLATFORM_REG_DRF_BIST_MODE_bist_mode_drf_can_ram_Msk                                                 (0x1UL << PLATFORM_REG_DRF_BIST_MODE_bist_mode_drf_can_ram_Pos)
+
+#define PLATFORM_REG_DRF_BIST_MODE_bist_mode_drf_cache_ram_Pos                                               4U
+#define PLATFORM_REG_DRF_BIST_MODE_bist_mode_drf_cache_ram_Msk                                               (0x1UL << PLATFORM_REG_DRF_BIST_MODE_bist_mode_drf_cache_ram_Pos)
+
+#define PLATFORM_REG_DRF_BIST_MODE_bist_mode_drf_amu_ram_Pos                                                 5U
+#define PLATFORM_REG_DRF_BIST_MODE_bist_mode_drf_amu_ram_Msk                                                 (0x1UL << PLATFORM_REG_DRF_BIST_MODE_bist_mode_drf_amu_ram_Pos)
+
+#define PLATFORM_REG_DRF_BIST_MODE_RSVD_Pos                                                                  6U
+#define PLATFORM_REG_DRF_BIST_MODE_RSVD_Msk                                                                  (0x3FFFFFFUL << PLATFORM_REG_DRF_BIST_MODE_RSVD_Pos)
+
+/* 0x004C   0x4000_604c
+    0       R/W     bist_test_resume_data_ram                           0
+    1       R/W     bist_test_resume_cpu_ram                            0
+    2       R/W     bist_test_resume_usb_ram                            0
+    3       R/W     bist_test_resume_can_ram                            0
+    4       R/W     bist_test_resume_cache_ram                          0
+    5       R/W     bist_test_resume_amu_ram                            0
+    31:6    R       RSVD                                                26'h0
+ */
+typedef union _PLATFORM_REG_BIST_TEST_RESUME_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t bist_test_resume_data_ram: 1;
+        uint32_t bist_test_resume_cpu_ram: 1;
+        uint32_t bist_test_resume_usb_ram: 1;
+        uint32_t bist_test_resume_can_ram: 1;
+        uint32_t bist_test_resume_cache_ram: 1;
+        uint32_t bist_test_resume_amu_ram: 1;
+        uint32_t RSVD: 26;
+    };
+} PLATFORM_REG_BIST_TEST_RESUME_TYPE;
+
+/*0x4000_604c PLATFORM_REG_BIST_TEST_RESUME*/
+#define PLATFORM_REG_BIST_TEST_RESUME_bist_test_resume_data_ram_Pos                                          0U
+#define PLATFORM_REG_BIST_TEST_RESUME_bist_test_resume_data_ram_Msk                                          (0x1UL << PLATFORM_REG_BIST_TEST_RESUME_bist_test_resume_data_ram_Pos)
+
+#define PLATFORM_REG_BIST_TEST_RESUME_bist_test_resume_cpu_ram_Pos                                           1U
+#define PLATFORM_REG_BIST_TEST_RESUME_bist_test_resume_cpu_ram_Msk                                           (0x1UL << PLATFORM_REG_BIST_TEST_RESUME_bist_test_resume_cpu_ram_Pos)
+
+#define PLATFORM_REG_BIST_TEST_RESUME_bist_test_resume_usb_ram_Pos                                           2U
+#define PLATFORM_REG_BIST_TEST_RESUME_bist_test_resume_usb_ram_Msk                                           (0x1UL << PLATFORM_REG_BIST_TEST_RESUME_bist_test_resume_usb_ram_Pos)
+
+#define PLATFORM_REG_BIST_TEST_RESUME_bist_test_resume_can_ram_Pos                                           3U
+#define PLATFORM_REG_BIST_TEST_RESUME_bist_test_resume_can_ram_Msk                                           (0x1UL << PLATFORM_REG_BIST_TEST_RESUME_bist_test_resume_can_ram_Pos)
+
+#define PLATFORM_REG_BIST_TEST_RESUME_bist_test_resume_cache_ram_Pos                                         4U
+#define PLATFORM_REG_BIST_TEST_RESUME_bist_test_resume_cache_ram_Msk                                         (0x1UL << PLATFORM_REG_BIST_TEST_RESUME_bist_test_resume_cache_ram_Pos)
+
+#define PLATFORM_REG_BIST_TEST_RESUME_bist_test_resume_amu_ram_Pos                                           5U
+#define PLATFORM_REG_BIST_TEST_RESUME_bist_test_resume_amu_ram_Msk                                           (0x1UL << PLATFORM_REG_BIST_TEST_RESUME_bist_test_resume_amu_ram_Pos)
+
+#define PLATFORM_REG_BIST_TEST_RESUME_RSVD_Pos                                                               6U
+#define PLATFORM_REG_BIST_TEST_RESUME_RSVD_Msk                                                               (0x3FFFFFFUL << PLATFORM_REG_BIST_TEST_RESUME_RSVD_Pos)
+
+/* 0x0050   0x4000_6050
+    0       R       bist_start_pause_data_ram                           0
+    1       R       bist_start_pause_cpu_ram                            0
+    2       R       bist_start_pause_usb_ram                            0
+    3       R       bist_start_pause_can_ram                            0
+    4       R       bist_start_pause_cache_ram                          0
+    5       R       bist_start_pause_amu_ram                            0
+    31:6    R       RSVD                                                26'h0
+ */
+typedef union _PLATFORM_REG_BIST_START_PAUSE_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t bist_start_pause_data_ram: 1;
+        uint32_t bist_start_pause_cpu_ram: 1;
+        uint32_t bist_start_pause_usb_ram: 1;
+        uint32_t bist_start_pause_can_ram: 1;
+        uint32_t bist_start_pause_cache_ram: 1;
+        uint32_t bist_start_pause_amu_ram: 1;
+        uint32_t RSVD: 26;
+    };
+} PLATFORM_REG_BIST_START_PAUSE_TYPE;
+
+/*0x4000_6050 PLATFORM_REG_BIST_START_PAUSE*/
+#define PLATFORM_REG_BIST_START_PAUSE_bist_start_pause_data_ram_Pos                                          0U
+#define PLATFORM_REG_BIST_START_PAUSE_bist_start_pause_data_ram_Msk                                          (0x1UL << PLATFORM_REG_BIST_START_PAUSE_bist_start_pause_data_ram_Pos)
+
+#define PLATFORM_REG_BIST_START_PAUSE_bist_start_pause_cpu_ram_Pos                                           1U
+#define PLATFORM_REG_BIST_START_PAUSE_bist_start_pause_cpu_ram_Msk                                           (0x1UL << PLATFORM_REG_BIST_START_PAUSE_bist_start_pause_cpu_ram_Pos)
+
+#define PLATFORM_REG_BIST_START_PAUSE_bist_start_pause_usb_ram_Pos                                           2U
+#define PLATFORM_REG_BIST_START_PAUSE_bist_start_pause_usb_ram_Msk                                           (0x1UL << PLATFORM_REG_BIST_START_PAUSE_bist_start_pause_usb_ram_Pos)
+
+#define PLATFORM_REG_BIST_START_PAUSE_bist_start_pause_can_ram_Pos                                           3U
+#define PLATFORM_REG_BIST_START_PAUSE_bist_start_pause_can_ram_Msk                                           (0x1UL << PLATFORM_REG_BIST_START_PAUSE_bist_start_pause_can_ram_Pos)
+
+#define PLATFORM_REG_BIST_START_PAUSE_bist_start_pause_cache_ram_Pos                                         4U
+#define PLATFORM_REG_BIST_START_PAUSE_bist_start_pause_cache_ram_Msk                                         (0x1UL << PLATFORM_REG_BIST_START_PAUSE_bist_start_pause_cache_ram_Pos)
+
+#define PLATFORM_REG_BIST_START_PAUSE_bist_start_pause_amu_ram_Pos                                           5U
+#define PLATFORM_REG_BIST_START_PAUSE_bist_start_pause_amu_ram_Msk                                           (0x1UL << PLATFORM_REG_BIST_START_PAUSE_bist_start_pause_amu_ram_Pos)
+
+#define PLATFORM_REG_BIST_START_PAUSE_RSVD_Pos                                                               6U
+#define PLATFORM_REG_BIST_START_PAUSE_RSVD_Msk                                                               (0x3FFFFFFUL << PLATFORM_REG_BIST_START_PAUSE_RSVD_Pos)
+
+/* 0x0054   0x4000_6054
+    0       R       bist_done_mcu_rom                                   0
+    1       R       bist_done_data_ram                                  0
+    2       R       bisr_done_data_ram                                  0
+    3       R       bist_done_cpu_ram                                   0
+    4       R       bist_done_usb_ram                                   0
+    5       R       bist_done_can_ram                                   0
+    6       R       bist_done_cache_ram                                 0
+    7       R       bist_done_amu_ram                                   0
+    31:8    R       RSVD                                                25'h0
+ */
+typedef union _PLATFORM_REG_BIST_DONE_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t bist_done_mcu_rom: 1;
+        uint32_t bist_done_data_ram: 1;
+        uint32_t bisr_done_data_ram: 1;
+        uint32_t bist_done_cpu_ram: 1;
+        uint32_t bist_done_usb_ram: 1;
+        uint32_t bist_done_can_ram: 1;
+        uint32_t bist_done_cache_ram: 1;
+        uint32_t bist_done_amu_ram: 1;
+        uint32_t RSVD: 24;
+    };
+} PLATFORM_REG_BIST_DONE_TYPE;
+
+/*0x4000_6054 PLATFORM_REG_BIST_DONE*/
+#define PLATFORM_REG_BIST_DONE_bist_done_mcu_rom_Pos                                                         0U
+#define PLATFORM_REG_BIST_DONE_bist_done_mcu_rom_Msk                                                         (0x1UL << PLATFORM_REG_BIST_DONE_bist_done_mcu_rom_Pos)
+
+#define PLATFORM_REG_BIST_DONE_bist_done_data_ram_Pos                                                        1U
+#define PLATFORM_REG_BIST_DONE_bist_done_data_ram_Msk                                                        (0x1UL << PLATFORM_REG_BIST_DONE_bist_done_data_ram_Pos)
+
+#define PLATFORM_REG_BIST_DONE_bisr_done_data_ram_Pos                                                        2U
+#define PLATFORM_REG_BIST_DONE_bisr_done_data_ram_Msk                                                        (0x1UL << PLATFORM_REG_BIST_DONE_bisr_done_data_ram_Pos)
+
+#define PLATFORM_REG_BIST_DONE_bist_done_cpu_ram_Pos                                                         3U
+#define PLATFORM_REG_BIST_DONE_bist_done_cpu_ram_Msk                                                         (0x1UL << PLATFORM_REG_BIST_DONE_bist_done_cpu_ram_Pos)
+
+#define PLATFORM_REG_BIST_DONE_bist_done_usb_ram_Pos                                                         4U
+#define PLATFORM_REG_BIST_DONE_bist_done_usb_ram_Msk                                                         (0x1UL << PLATFORM_REG_BIST_DONE_bist_done_usb_ram_Pos)
+
+#define PLATFORM_REG_BIST_DONE_bist_done_can_ram_Pos                                                         5U
+#define PLATFORM_REG_BIST_DONE_bist_done_can_ram_Msk                                                         (0x1UL << PLATFORM_REG_BIST_DONE_bist_done_can_ram_Pos)
+
+#define PLATFORM_REG_BIST_DONE_bist_done_cache_ram_Pos                                                       6U
+#define PLATFORM_REG_BIST_DONE_bist_done_cache_ram_Msk                                                       (0x1UL << PLATFORM_REG_BIST_DONE_bist_done_cache_ram_Pos)
+
+#define PLATFORM_REG_BIST_DONE_bist_done_amu_ram_Pos                                                         7U
+#define PLATFORM_REG_BIST_DONE_bist_done_amu_ram_Msk                                                         (0x1UL << PLATFORM_REG_BIST_DONE_bist_done_amu_ram_Pos)
+
+#define PLATFORM_REG_BIST_DONE_RSVD_Pos                                                                      8U
+#define PLATFORM_REG_BIST_DONE_RSVD_Msk                                                                      (0xFFFFFFUL << PLATFORM_REG_BIST_DONE_RSVD_Pos)
+
+/* 0x0058   0x4000_6058
+    4:0     R       bist_fail_data_ram                                  5'h0
+    5       R       bist_fail_cpu_ram                                   0
+    6       R       bist_fail_usb_ram                                   0
+    7       R       bist_fail_can_ram                                   0
+    16:8    R       bist_fail_cache_ram                                 9'h0
+    17      R       bist_fail_amu_ram                                   0
+    31:18   R       RSVD                                                14'h0
+ */
+typedef union _PLATFORM_REG_BIST_FAIL_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t bist_fail_data_ram: 5;
+        uint32_t bist_fail_cpu_ram: 1;
+        uint32_t bist_fail_usb_ram: 1;
+        uint32_t bist_fail_can_ram: 1;
+        uint32_t bist_fail_cache_ram: 9;
+        uint32_t bist_fail_amu_ram: 1;
+        uint32_t RSVD: 14;
+    };
+} PLATFORM_REG_BIST_FAIL_TYPE;
+
+/*0x4000_6058 PLATFORM_REG_BIST_FAIL*/
+#define PLATFORM_REG_BIST_FAIL_bist_fail_data_ram_Pos                                                        0U
+#define PLATFORM_REG_BIST_FAIL_bist_fail_data_ram_Msk                                                        (0x1FUL << PLATFORM_REG_BIST_FAIL_bist_fail_data_ram_Pos)
+
+#define PLATFORM_REG_BIST_FAIL_bist_fail_cpu_ram_Pos                                                         5U
+#define PLATFORM_REG_BIST_FAIL_bist_fail_cpu_ram_Msk                                                         (0x1UL << PLATFORM_REG_BIST_FAIL_bist_fail_cpu_ram_Pos)
+
+#define PLATFORM_REG_BIST_FAIL_bist_fail_usb_ram_Pos                                                         6U
+#define PLATFORM_REG_BIST_FAIL_bist_fail_usb_ram_Msk                                                         (0x1UL << PLATFORM_REG_BIST_FAIL_bist_fail_usb_ram_Pos)
+
+#define PLATFORM_REG_BIST_FAIL_bist_fail_can_ram_Pos                                                         7U
+#define PLATFORM_REG_BIST_FAIL_bist_fail_can_ram_Msk                                                         (0x1UL << PLATFORM_REG_BIST_FAIL_bist_fail_can_ram_Pos)
+
+#define PLATFORM_REG_BIST_FAIL_bist_fail_cache_ram_Pos                                                       8U
+#define PLATFORM_REG_BIST_FAIL_bist_fail_cache_ram_Msk                                                       (0x1FFUL << PLATFORM_REG_BIST_FAIL_bist_fail_cache_ram_Pos)
+
+#define PLATFORM_REG_BIST_FAIL_bist_fail_amu_ram_Pos                                                         17U
+#define PLATFORM_REG_BIST_FAIL_bist_fail_amu_ram_Msk                                                         (0x1UL << PLATFORM_REG_BIST_FAIL_bist_fail_amu_ram_Pos)
+
+#define PLATFORM_REG_BIST_FAIL_RSVD_Pos                                                                      18U
+#define PLATFORM_REG_BIST_FAIL_RSVD_Msk                                                                      (0x3FFFUL << PLATFORM_REG_BIST_FAIL_RSVD_Pos)
+
+/* 0x005C   0x4000_605c
+    0       R       bist_done_drf_data_ram                              0
+    1       R       bist_done_drf_cpu_ram                               0
+    2       R       bist_done_drf_usb_ram                               0
+    3       R       bist_done_drf_can_ram                               0
+    4       R       bist_done_drf_cache_ram                             0
+    5       R       bist_done_drf_amu_ram                               0
+    6       R       bisr_done_drf_data_ram                              0
+    31:7    R       RSVD                                                26'h0
+ */
+typedef union _PLATFORM_REG_DRF_BIST_DONE_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t bist_done_drf_data_ram: 1;
+        uint32_t bist_done_drf_cpu_ram: 1;
+        uint32_t bist_done_drf_usb_ram: 1;
+        uint32_t bist_done_drf_can_ram: 1;
+        uint32_t bist_done_drf_cache_ram: 1;
+        uint32_t bist_done_drf_amu_ram: 1;
+        uint32_t bisr_done_drf_data_ram: 1;
+        uint32_t RSVD: 25;
+    };
+} PLATFORM_REG_DRF_BIST_DONE_TYPE;
+
+/*0x4000_605c PLATFORM_REG_DRF_BIST_DONE*/
+#define PLATFORM_REG_DRF_BIST_DONE_bist_done_drf_data_ram_Pos                                                0U
+#define PLATFORM_REG_DRF_BIST_DONE_bist_done_drf_data_ram_Msk                                                (0x1UL << PLATFORM_REG_DRF_BIST_DONE_bist_done_drf_data_ram_Pos)
+
+#define PLATFORM_REG_DRF_BIST_DONE_bist_done_drf_cpu_ram_Pos                                                 1U
+#define PLATFORM_REG_DRF_BIST_DONE_bist_done_drf_cpu_ram_Msk                                                 (0x1UL << PLATFORM_REG_DRF_BIST_DONE_bist_done_drf_cpu_ram_Pos)
+
+#define PLATFORM_REG_DRF_BIST_DONE_bist_done_drf_usb_ram_Pos                                                 2U
+#define PLATFORM_REG_DRF_BIST_DONE_bist_done_drf_usb_ram_Msk                                                 (0x1UL << PLATFORM_REG_DRF_BIST_DONE_bist_done_drf_usb_ram_Pos)
+
+#define PLATFORM_REG_DRF_BIST_DONE_bist_done_drf_can_ram_Pos                                                 3U
+#define PLATFORM_REG_DRF_BIST_DONE_bist_done_drf_can_ram_Msk                                                 (0x1UL << PLATFORM_REG_DRF_BIST_DONE_bist_done_drf_can_ram_Pos)
+
+#define PLATFORM_REG_DRF_BIST_DONE_bist_done_drf_cache_ram_Pos                                               4U
+#define PLATFORM_REG_DRF_BIST_DONE_bist_done_drf_cache_ram_Msk                                               (0x1UL << PLATFORM_REG_DRF_BIST_DONE_bist_done_drf_cache_ram_Pos)
+
+#define PLATFORM_REG_DRF_BIST_DONE_bist_done_drf_amu_ram_Pos                                                 5U
+#define PLATFORM_REG_DRF_BIST_DONE_bist_done_drf_amu_ram_Msk                                                 (0x1UL << PLATFORM_REG_DRF_BIST_DONE_bist_done_drf_amu_ram_Pos)
+
+#define PLATFORM_REG_DRF_BIST_DONE_bisr_done_drf_data_ram_Pos                                                6U
+#define PLATFORM_REG_DRF_BIST_DONE_bisr_done_drf_data_ram_Msk                                                (0x1UL << PLATFORM_REG_DRF_BIST_DONE_bisr_done_drf_data_ram_Pos)
+
+#define PLATFORM_REG_DRF_BIST_DONE_RSVD_Pos                                                                  7U
+#define PLATFORM_REG_DRF_BIST_DONE_RSVD_Msk                                                                  (0x1FFFFFFUL << PLATFORM_REG_DRF_BIST_DONE_RSVD_Pos)
+
+/* 0x0060   0x4000_6060
+    4:0     R       bist_fail_drf_data_ram                              5'h0
+    5       R       bist_fail_drf_cpu_ram                               0
+    6       R       bist_fail_drf_usb_ram                               0
+    7       R       bist_fail_drf_can_ram                               0
+    16:8    R       bist_fail_drf_cache_ram                             9'h0
+    17      R       bist_fail_drf_amu_ram                               0
+    31:18   R       RSVD                                                14'h0
+ */
+typedef union _PLATFORM_REG_DRF_BIST_FAIL_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t bist_fail_drf_data_ram: 5;
+        uint32_t bist_fail_drf_cpu_ram: 1;
+        uint32_t bist_fail_drf_usb_ram: 1;
+        uint32_t bist_fail_drf_can_ram: 1;
+        uint32_t bist_fail_drf_cache_ram: 9;
+        uint32_t bist_fail_drf_amu_ram: 1;
+        uint32_t RSVD: 14;
+    };
+} PLATFORM_REG_DRF_BIST_FAIL_TYPE;
+
+/*0x4000_6060 PLATFORM_REG_DRF_BIST_FAIL*/
+#define PLATFORM_REG_DRF_BIST_FAIL_bist_fail_drf_data_ram_Pos                                                0U
+#define PLATFORM_REG_DRF_BIST_FAIL_bist_fail_drf_data_ram_Msk                                                (0x1FUL << PLATFORM_REG_DRF_BIST_FAIL_bist_fail_drf_data_ram_Pos)
+
+#define PLATFORM_REG_DRF_BIST_FAIL_bist_fail_drf_cpu_ram_Pos                                                 5U
+#define PLATFORM_REG_DRF_BIST_FAIL_bist_fail_drf_cpu_ram_Msk                                                 (0x1UL << PLATFORM_REG_DRF_BIST_FAIL_bist_fail_drf_cpu_ram_Pos)
+
+#define PLATFORM_REG_DRF_BIST_FAIL_bist_fail_drf_usb_ram_Pos                                                 6U
+#define PLATFORM_REG_DRF_BIST_FAIL_bist_fail_drf_usb_ram_Msk                                                 (0x1UL << PLATFORM_REG_DRF_BIST_FAIL_bist_fail_drf_usb_ram_Pos)
+
+#define PLATFORM_REG_DRF_BIST_FAIL_bist_fail_drf_can_ram_Pos                                                 7U
+#define PLATFORM_REG_DRF_BIST_FAIL_bist_fail_drf_can_ram_Msk                                                 (0x1UL << PLATFORM_REG_DRF_BIST_FAIL_bist_fail_drf_can_ram_Pos)
+
+#define PLATFORM_REG_DRF_BIST_FAIL_bist_fail_drf_cache_ram_Pos                                               8U
+#define PLATFORM_REG_DRF_BIST_FAIL_bist_fail_drf_cache_ram_Msk                                               (0x1FFUL << PLATFORM_REG_DRF_BIST_FAIL_bist_fail_drf_cache_ram_Pos)
+
+#define PLATFORM_REG_DRF_BIST_FAIL_bist_fail_drf_amu_ram_Pos                                                 17U
+#define PLATFORM_REG_DRF_BIST_FAIL_bist_fail_drf_amu_ram_Msk                                                 (0x1UL << PLATFORM_REG_DRF_BIST_FAIL_bist_fail_drf_amu_ram_Pos)
+
+#define PLATFORM_REG_DRF_BIST_FAIL_RSVD_Pos                                                                  18U
+#define PLATFORM_REG_DRF_BIST_FAIL_RSVD_Msk                                                                  (0x3FFFUL << PLATFORM_REG_DRF_BIST_FAIL_RSVD_Pos)
+
+/* 0x0064   0x4000_6064
+    31:0    R       mcu_rom0_misr31_0                                   32'h0
+ */
+typedef union _PLATFORM_REG_MCU_ROM0_MISR0_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t mcu_rom0_misr31_0;
+    };
+} PLATFORM_REG_MCU_ROM0_MISR0_TYPE;
+
+/*0x4000_6064 PLATFORM_REG_MCU_ROM0_MISR0*/
+#define PLATFORM_REG_MCU_ROM0_MISR0_mcu_rom0_misr31_0_Pos                                                    0U
+#define PLATFORM_REG_MCU_ROM0_MISR0_mcu_rom0_misr31_0_Msk                                                    (0xFFFFFFFFUL << PLATFORM_REG_MCU_ROM0_MISR0_mcu_rom0_misr31_0_Pos)
+
+/* 0x0068   0x4000_6068
+    31:0    R       mcu_rom0_misr63_32                                  32'h0
+ */
+typedef union _PLATFORM_REG_MCU_ROM0_MISR1_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t mcu_rom0_misr63_32;
+    };
+} PLATFORM_REG_MCU_ROM0_MISR1_TYPE;
+
+/*0x4000_6068 PLATFORM_REG_MCU_ROM0_MISR1*/
+#define PLATFORM_REG_MCU_ROM0_MISR1_mcu_rom0_misr63_32_Pos                                                   0U
+#define PLATFORM_REG_MCU_ROM0_MISR1_mcu_rom0_misr63_32_Msk                                                   (0xFFFFFFFFUL << PLATFORM_REG_MCU_ROM0_MISR1_mcu_rom0_misr63_32_Pos)
+
+/* 0x006C   0x4000_606c
+    31:0    R       RSVD                                                32'h0
+ */
+typedef union _PLATFORM_REG_MCU_ROM1_MISR0_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RSVD;
+    };
+} PLATFORM_REG_MCU_ROM1_MISR0_TYPE;
+
+/*0x4000_606c PLATFORM_REG_MCU_ROM1_MISR0*/
+#define PLATFORM_REG_MCU_ROM1_MISR0_RSVD_Pos                                                                 0U
+#define PLATFORM_REG_MCU_ROM1_MISR0_RSVD_Msk                                                                 (0xFFFFFFFFUL << PLATFORM_REG_MCU_ROM1_MISR0_RSVD_Pos)
+
+/* 0x0070   0x4000_6070
+    31:0    R       RSVD                                                32'h0
+ */
+typedef union _PLATFORM_REG_MCU_ROM1_MISR1_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RSVD;
+    };
+} PLATFORM_REG_MCU_ROM1_MISR1_TYPE;
+
+/*0x4000_6070 PLATFORM_REG_MCU_ROM1_MISR1*/
+#define PLATFORM_REG_MCU_ROM1_MISR1_RSVD_Pos                                                                 0U
+#define PLATFORM_REG_MCU_ROM1_MISR1_RSVD_Msk                                                                 (0xFFFFFFFFUL << PLATFORM_REG_MCU_ROM1_MISR1_RSVD_Pos)
+
+/* 0x0074   0x4000_6074
+    31:0    R       RSVD                                                32'h0
+ */
+typedef union _PLATFORM_REG_MCU_ROM2_MISR0_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RSVD;
+    };
+} PLATFORM_REG_MCU_ROM2_MISR0_TYPE;
+
+/*0x4000_6074 PLATFORM_REG_MCU_ROM2_MISR0*/
+#define PLATFORM_REG_MCU_ROM2_MISR0_RSVD_Pos                                                                 0U
+#define PLATFORM_REG_MCU_ROM2_MISR0_RSVD_Msk                                                                 (0xFFFFFFFFUL << PLATFORM_REG_MCU_ROM2_MISR0_RSVD_Pos)
+
+/* 0x0078   0x4000_6078
+    31:0    R       RSVD                                                32'h0
+ */
+typedef union _PLATFORM_REG_MCU_ROM2_MISR1_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RSVD;
+    };
+} PLATFORM_REG_MCU_ROM2_MISR1_TYPE;
+
+/*0x4000_6078 PLATFORM_REG_MCU_ROM2_MISR1*/
+#define PLATFORM_REG_MCU_ROM2_MISR1_RSVD_Pos                                                                 0U
+#define PLATFORM_REG_MCU_ROM2_MISR1_RSVD_Msk                                                                 (0xFFFFFFFFUL << PLATFORM_REG_MCU_ROM2_MISR1_RSVD_Pos)
+
+/* 0x007C   0x4000_607c
+    31:0    R       RSVD                                                32'h0
+ */
+typedef union _PLATFORM_REG_MCU_ROM3_MISR0_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RSVD;
+    };
+} PLATFORM_REG_MCU_ROM3_MISR0_TYPE;
+
+/*0x4000_607c PLATFORM_REG_MCU_ROM3_MISR0*/
+#define PLATFORM_REG_MCU_ROM3_MISR0_RSVD_Pos                                                                 0U
+#define PLATFORM_REG_MCU_ROM3_MISR0_RSVD_Msk                                                                 (0xFFFFFFFFUL << PLATFORM_REG_MCU_ROM3_MISR0_RSVD_Pos)
+
+/* 0x0080   0x4000_6080
+    31:0    R       RSVD                                                32'h0
+ */
+typedef union _PLATFORM_REG_MCU_ROM3_MISR1_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RSVD;
+    };
+} PLATFORM_REG_MCU_ROM3_MISR1_TYPE;
+
+/*0x4000_6080 PLATFORM_REG_MCU_ROM3_MISR1*/
+#define PLATFORM_REG_MCU_ROM3_MISR1_RSVD_Pos                                                                 0U
+#define PLATFORM_REG_MCU_ROM3_MISR1_RSVD_Msk                                                                 (0xFFFFFFFFUL << PLATFORM_REG_MCU_ROM3_MISR1_RSVD_Pos)
+
+/* 0x0084   0x4000_6084
+    31:0    R       RSVD                                                32'h0
+ */
+typedef union _PLATFORM_REG_MCU_ROM4_MISR0_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RSVD;
+    };
+} PLATFORM_REG_MCU_ROM4_MISR0_TYPE;
+
+/*0x4000_6084 PLATFORM_REG_MCU_ROM4_MISR0*/
+#define PLATFORM_REG_MCU_ROM4_MISR0_RSVD_Pos                                                                 0U
+#define PLATFORM_REG_MCU_ROM4_MISR0_RSVD_Msk                                                                 (0xFFFFFFFFUL << PLATFORM_REG_MCU_ROM4_MISR0_RSVD_Pos)
+
+/* 0x0088   0x4000_6088
+    31:0    R       RSVD                                                32'h0
+ */
+typedef union _PLATFORM_REG_MCU_ROM4_MISR1_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RSVD;
+    };
+} PLATFORM_REG_MCU_ROM4_MISR1_TYPE;
+
+/*0x4000_6088 PLATFORM_REG_MCU_ROM4_MISR1*/
+#define PLATFORM_REG_MCU_ROM4_MISR1_RSVD_Pos                                                                 0U
+#define PLATFORM_REG_MCU_ROM4_MISR1_RSVD_Msk                                                                 (0xFFFFFFFFUL << PLATFORM_REG_MCU_ROM4_MISR1_RSVD_Pos)
+
+/* 0x0090   0x4000_6090
+    31:0    R/W     OUT_DATA0                                           32'h0
+ */
+typedef union _PLATFORM_REG_I2C_MAILBOX_OUT_DATA0_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t OUT_DATA0;
+    };
+} PLATFORM_REG_I2C_MAILBOX_OUT_DATA0_TYPE;
+
+/*0x4000_6090 PLATFORM_REG_I2C_MAILBOX_OUT_DATA0*/
+#define PLATFORM_REG_I2C_MAILBOX_OUT_DATA0_OUT_DATA0_Pos                                                     0U
+#define PLATFORM_REG_I2C_MAILBOX_OUT_DATA0_OUT_DATA0_Msk                                                     (0xFFFFFFFFUL << PLATFORM_REG_I2C_MAILBOX_OUT_DATA0_OUT_DATA0_Pos)
+
+/* 0x0094   0x4000_6094
+    31:0    R/W     OUT_DATA1                                           32'h0
+ */
+typedef union _PLATFORM_REG_I2C_MAILBOX_OUT_DATA1_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t OUT_DATA1;
+    };
+} PLATFORM_REG_I2C_MAILBOX_OUT_DATA1_TYPE;
+
+/*0x4000_6094 PLATFORM_REG_I2C_MAILBOX_OUT_DATA1*/
+#define PLATFORM_REG_I2C_MAILBOX_OUT_DATA1_OUT_DATA1_Pos                                                     0U
+#define PLATFORM_REG_I2C_MAILBOX_OUT_DATA1_OUT_DATA1_Msk                                                     (0xFFFFFFFFUL << PLATFORM_REG_I2C_MAILBOX_OUT_DATA1_OUT_DATA1_Pos)
+
+/* 0x0098   0x4000_6098
+    31:0    R       IN_DATA0                                            32'h0
+ */
+typedef union _PLATFORM_REG_I2C_MAILBOX_IN_DATA0_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t IN_DATA0;
+    };
+} PLATFORM_REG_I2C_MAILBOX_IN_DATA0_TYPE;
+
+/*0x4000_6098 PLATFORM_REG_I2C_MAILBOX_IN_DATA0*/
+#define PLATFORM_REG_I2C_MAILBOX_IN_DATA0_IN_DATA0_Pos                                                       0U
+#define PLATFORM_REG_I2C_MAILBOX_IN_DATA0_IN_DATA0_Msk                                                       (0xFFFFFFFFUL << PLATFORM_REG_I2C_MAILBOX_IN_DATA0_IN_DATA0_Pos)
+
+/* 0x009C   0x4000_609c
+    31:0    R       IN_DATA1                                            32'h0
+ */
+typedef union _PLATFORM_REG_I2C_MAILBOX_IN_DATA1_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t IN_DATA1;
+    };
+} PLATFORM_REG_I2C_MAILBOX_IN_DATA1_TYPE;
+
+/*0x4000_609c PLATFORM_REG_I2C_MAILBOX_IN_DATA1*/
+#define PLATFORM_REG_I2C_MAILBOX_IN_DATA1_IN_DATA1_Pos                                                       0U
+#define PLATFORM_REG_I2C_MAILBOX_IN_DATA1_IN_DATA1_Msk                                                       (0xFFFFFFFFUL << PLATFORM_REG_I2C_MAILBOX_IN_DATA1_IN_DATA1_Pos)
+
+/* 0x00A0   0x4000_60a0
+    0       R/W1C   outbox_rdy_r                                        0
+    1       R/W     out_empty_inten                                     0
+    2       R/W     out_int_mode                                        0
+    3       R/W1C   out_edge_sts                                        0
+    4       R       rx_data_crc_ok                                      0
+    15:5    R       RSVD_1                                              11'h0
+    16      R/W1C   inbox_rdy_r                                         0
+    17      R/W     in_rdy_inten                                        0
+    30:18   R       RSVD                                                13'h0
+    31      R/W     pta_i2c_en                                          0
+ */
+typedef union _PLATFORM_REG_I2C_MAILBOX_CTRL_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t outbox_rdy_r: 1;
+        uint32_t out_empty_inten: 1;
+        uint32_t out_int_mode: 1;
+        uint32_t out_edge_sts: 1;
+        uint32_t rx_data_crc_ok: 1;
+        uint32_t RSVD_1: 11;
+        uint32_t inbox_rdy_r: 1;
+        uint32_t in_rdy_inten: 1;
+        uint32_t RSVD: 13;
+        uint32_t pta_i2c_en: 1;
+    };
+} PLATFORM_REG_I2C_MAILBOX_CTRL_TYPE;
+
+/*0x4000_60a0 PLATFORM_REG_I2C_MAILBOX_CTRL*/
+#define PLATFORM_REG_I2C_MAILBOX_CTRL_outbox_rdy_r_Pos                                                       0U
+#define PLATFORM_REG_I2C_MAILBOX_CTRL_outbox_rdy_r_Msk                                                       (0x1UL << PLATFORM_REG_I2C_MAILBOX_CTRL_outbox_rdy_r_Pos)
+
+#define PLATFORM_REG_I2C_MAILBOX_CTRL_out_empty_inten_Pos                                                    1U
+#define PLATFORM_REG_I2C_MAILBOX_CTRL_out_empty_inten_Msk                                                    (0x1UL << PLATFORM_REG_I2C_MAILBOX_CTRL_out_empty_inten_Pos)
+
+#define PLATFORM_REG_I2C_MAILBOX_CTRL_out_int_mode_Pos                                                       2U
+#define PLATFORM_REG_I2C_MAILBOX_CTRL_out_int_mode_Msk                                                       (0x1UL << PLATFORM_REG_I2C_MAILBOX_CTRL_out_int_mode_Pos)
+
+#define PLATFORM_REG_I2C_MAILBOX_CTRL_out_edge_sts_Pos                                                       3U
+#define PLATFORM_REG_I2C_MAILBOX_CTRL_out_edge_sts_Msk                                                       (0x1UL << PLATFORM_REG_I2C_MAILBOX_CTRL_out_edge_sts_Pos)
+
+#define PLATFORM_REG_I2C_MAILBOX_CTRL_rx_data_crc_ok_Pos                                                     4U
+#define PLATFORM_REG_I2C_MAILBOX_CTRL_rx_data_crc_ok_Msk                                                     (0x1UL << PLATFORM_REG_I2C_MAILBOX_CTRL_rx_data_crc_ok_Pos)
+
+#define PLATFORM_REG_I2C_MAILBOX_CTRL_RSVD_1_Pos                                                             5U
+#define PLATFORM_REG_I2C_MAILBOX_CTRL_RSVD_1_Msk                                                             (0x7FFUL << PLATFORM_REG_I2C_MAILBOX_CTRL_RSVD_1_Pos)
+
+#define PLATFORM_REG_I2C_MAILBOX_CTRL_inbox_rdy_r_Pos                                                        16U
+#define PLATFORM_REG_I2C_MAILBOX_CTRL_inbox_rdy_r_Msk                                                        (0x1UL << PLATFORM_REG_I2C_MAILBOX_CTRL_inbox_rdy_r_Pos)
+
+#define PLATFORM_REG_I2C_MAILBOX_CTRL_in_rdy_inten_Pos                                                       17U
+#define PLATFORM_REG_I2C_MAILBOX_CTRL_in_rdy_inten_Msk                                                       (0x1UL << PLATFORM_REG_I2C_MAILBOX_CTRL_in_rdy_inten_Pos)
+
+#define PLATFORM_REG_I2C_MAILBOX_CTRL_RSVD_Pos                                                               18U
+#define PLATFORM_REG_I2C_MAILBOX_CTRL_RSVD_Msk                                                               (0x1FFFUL << PLATFORM_REG_I2C_MAILBOX_CTRL_RSVD_Pos)
+
+#define PLATFORM_REG_I2C_MAILBOX_CTRL_pta_i2c_en_Pos                                                         31U
+#define PLATFORM_REG_I2C_MAILBOX_CTRL_pta_i2c_en_Msk                                                         (0x1UL << PLATFORM_REG_I2C_MAILBOX_CTRL_pta_i2c_en_Pos)
+
+/* 0x00A4   0x4000_60a4
+    0       R/W     CM33_WICEN_REQ                                      1'b0
+    1       R       CM33_WICEN_ACK                                      1'b0
+    31:2    R       RSVD                                                30'h0
+ */
+typedef union _PLATFORM_WIC_HANDSHAKE_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t CM33_WICEN_REQ: 1;
+        uint32_t CM33_WICEN_ACK: 1;
+        uint32_t RSVD: 30;
+    };
+} PLATFORM_WIC_HANDSHAKE_TYPE;
+
+/*0x4000_60a4 PLATFORM_WIC_HANDSHAKE*/
+#define PLATFORM_WIC_HANDSHAKE_CM33_WICEN_REQ_Pos                                                            0U
+#define PLATFORM_WIC_HANDSHAKE_CM33_WICEN_REQ_Msk                                                            (0x1UL << PLATFORM_WIC_HANDSHAKE_CM33_WICEN_REQ_Pos)
+
+#define PLATFORM_WIC_HANDSHAKE_CM33_WICEN_ACK_Pos                                                            1U
+#define PLATFORM_WIC_HANDSHAKE_CM33_WICEN_ACK_Msk                                                            (0x1UL << PLATFORM_WIC_HANDSHAKE_CM33_WICEN_ACK_Pos)
+
+#define PLATFORM_WIC_HANDSHAKE_RSVD_Pos                                                                      2U
+#define PLATFORM_WIC_HANDSHAKE_RSVD_Msk                                                                      (0x3FFFFFFFUL << PLATFORM_WIC_HANDSHAKE_RSVD_Pos)
+
+/* 0x00A8   0x4000_60a8
+    3:0     R/W1C   WKUP_REASON_W1C                                     4'd0
+    15:4    R       RSVD_1                                              12'd0
+    19:16   R       RO_WKUP_REASON                                      4'd0
+    31:20   R       RSVD                                                12'd0
+ */
+typedef union _PLATFORM_WKUP_REASON_CORE_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t WKUP_REASON_W1C: 4;
+        uint32_t RSVD_1: 12;
+        uint32_t RO_WKUP_REASON: 4;
+        uint32_t RSVD: 12;
+    };
+} PLATFORM_WKUP_REASON_CORE_TYPE;
+
+/*0x4000_60a8 PLATFORM_WKUP_REASON_CORE*/
+#define PLATFORM_WKUP_REASON_CORE_WKUP_REASON_W1C_Pos                                                        0U
+#define PLATFORM_WKUP_REASON_CORE_WKUP_REASON_W1C_Msk                                                        (0xFUL << PLATFORM_WKUP_REASON_CORE_WKUP_REASON_W1C_Pos)
+
+#define PLATFORM_WKUP_REASON_CORE_RSVD_1_Pos                                                                 4U
+#define PLATFORM_WKUP_REASON_CORE_RSVD_1_Msk                                                                 (0xFFFUL << PLATFORM_WKUP_REASON_CORE_RSVD_1_Pos)
+
+#define PLATFORM_WKUP_REASON_CORE_RO_WKUP_REASON_Pos                                                         16U
+#define PLATFORM_WKUP_REASON_CORE_RO_WKUP_REASON_Msk                                                         (0xFUL << PLATFORM_WKUP_REASON_CORE_RO_WKUP_REASON_Pos)
+
+#define PLATFORM_WKUP_REASON_CORE_RSVD_Pos                                                                   20U
+#define PLATFORM_WKUP_REASON_CORE_RSVD_Msk                                                                   (0xFFFUL << PLATFORM_WKUP_REASON_CORE_RSVD_Pos)
+
+/* 0x00AC   0x4000_60ac
+    31:0    R       RSVD                                                32'h0
+ */
+typedef union _PLATFORM_Reserved_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RSVD;
+    };
+} PLATFORM_Reserved_TYPE;
+
+/*0x4000_60ac PLATFORM_Reserved*/
+#define PLATFORM_Reserved_RSVD_Pos                                                                           0U
+#define PLATFORM_Reserved_RSVD_Msk                                                                           (0xFFFFFFFFUL << PLATFORM_Reserved_RSVD_Pos)
+
+/* 0x00B0   0x4000_60b0
+    31:0    R       RSVD                                                32'h0
+ */
+typedef union _PLATFORM_Reserved_1_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RSVD;
+    };
+} PLATFORM_Reserved_1_TYPE;
+
+/*0x4000_60b0 PLATFORM_Reserved_1*/
+#define PLATFORM_Reserved_1_RSVD_Pos                                                                         0U
+#define PLATFORM_Reserved_1_RSVD_Msk                                                                         (0xFFFFFFFFUL << PLATFORM_Reserved_1_RSVD_Pos)
+
+/* 0x00B4   0x4000_60b4
+    31:0    R       RSVD                                                32'h0
+ */
+typedef union _PLATFORM_Reserved_2_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RSVD;
+    };
+} PLATFORM_Reserved_2_TYPE;
+
+/*0x4000_60b4 PLATFORM_Reserved_2*/
+#define PLATFORM_Reserved_2_RSVD_Pos                                                                         0U
+#define PLATFORM_Reserved_2_RSVD_Msk                                                                         (0xFFFFFFFFUL << PLATFORM_Reserved_2_RSVD_Pos)
+
+/* 0x00B8   0x4000_60b8
+    1:0     R/W     RSVD_3                                              2'h0
+    4:2     R       RSVD_2                                              3'h0
+    7:5     R/W     RSVD_1                                              3'h0
+    31:8    R       RSVD                                                24'h0
+ */
+typedef union _PLATFORM_REG_SNPS_SRAM_CTRL_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RSVD_3: 2;
+        uint32_t RSVD_2: 3;
+        uint32_t RSVD_1: 3;
+        uint32_t RSVD: 24;
+    };
+} PLATFORM_REG_SNPS_SRAM_CTRL_TYPE;
+
+/*0x4000_60b8 PLATFORM_REG_SNPS_SRAM_CTRL*/
+#define PLATFORM_REG_SNPS_SRAM_CTRL_RSVD_3_Pos                                                               0U
+#define PLATFORM_REG_SNPS_SRAM_CTRL_RSVD_3_Msk                                                               (0x3UL << PLATFORM_REG_SNPS_SRAM_CTRL_RSVD_3_Pos)
+
+#define PLATFORM_REG_SNPS_SRAM_CTRL_RSVD_2_Pos                                                               2U
+#define PLATFORM_REG_SNPS_SRAM_CTRL_RSVD_2_Msk                                                               (0x7UL << PLATFORM_REG_SNPS_SRAM_CTRL_RSVD_2_Pos)
+
+#define PLATFORM_REG_SNPS_SRAM_CTRL_RSVD_1_Pos                                                               5U
+#define PLATFORM_REG_SNPS_SRAM_CTRL_RSVD_1_Msk                                                               (0x7UL << PLATFORM_REG_SNPS_SRAM_CTRL_RSVD_1_Pos)
+
+#define PLATFORM_REG_SNPS_SRAM_CTRL_RSVD_Pos                                                                 8U
+#define PLATFORM_REG_SNPS_SRAM_CTRL_RSVD_Msk                                                                 (0xFFFFFFUL << PLATFORM_REG_SNPS_SRAM_CTRL_RSVD_Pos)
+
+/* 0x00BC   0x4000_60bc
+    31:0    R       RSVD                                                32'h0
+ */
+typedef union _PLATFORM_Reserved_3_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RSVD;
+    };
+} PLATFORM_Reserved_3_TYPE;
+
+/*0x4000_60bc PLATFORM_Reserved_3*/
+#define PLATFORM_Reserved_3_RSVD_Pos                                                                         0U
+#define PLATFORM_Reserved_3_RSVD_Msk                                                                         (0xFFFFFFFFUL << PLATFORM_Reserved_3_RSVD_Pos)
+
+/* 0x00C0   0x4000_60c0
+    31:0    R       RSVD                                                32'h0
+ */
+typedef union _PLATFORM_Reserved_4_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RSVD;
+    };
+} PLATFORM_Reserved_4_TYPE;
+
+/*0x4000_60c0 PLATFORM_Reserved_4*/
+#define PLATFORM_Reserved_4_RSVD_Pos                                                                         0U
+#define PLATFORM_Reserved_4_RSVD_Msk                                                                         (0xFFFFFFFFUL << PLATFORM_Reserved_4_RSVD_Pos)
+
+/* 0x00C4   0x4000_60c4
+    31:0    R       RSVD                                                32'h0
+ */
+typedef union _PLATFORM_Reserved_5_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RSVD;
+    };
+} PLATFORM_Reserved_5_TYPE;
+
+/*0x4000_60c4 PLATFORM_Reserved_5*/
+#define PLATFORM_Reserved_5_RSVD_Pos                                                                         0U
+#define PLATFORM_Reserved_5_RSVD_Msk                                                                         (0xFFFFFFFFUL << PLATFORM_Reserved_5_RSVD_Pos)
+
+/* 0x00C8   0x4000_60c8
+    0       R/W     bisr_remap_rstn_data_ram                            1'b0
+    1       R/W     bisr_load_fuse_data_ram                             1'b0
+    19:2    R/W     bisr_remap_sig_data_ram                             18'h0
+    20      R/W     bisr_second_run_data_ram                            1'b0
+    21      R/W     bisr_hold_remap_data_ram                            1'b0
+    22      R/W     bisr_pwr_rstn_data_ram                              1'b1
+    31:23   R       RSVD                                                9'h0
+ */
+typedef union _PLATFORM_REG_MBISR_DATA_SRAM_CTRL_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t bisr_remap_rstn_data_ram: 1;
+        uint32_t bisr_load_fuse_data_ram: 1;
+        uint32_t bisr_remap_sig_data_ram: 18;
+        uint32_t bisr_second_run_data_ram: 1;
+        uint32_t bisr_hold_remap_data_ram: 1;
+        uint32_t bisr_pwr_rstn_data_ram: 1;
+        uint32_t RSVD: 9;
+    };
+} PLATFORM_REG_MBISR_DATA_SRAM_CTRL_TYPE;
+
+/*0x4000_60c8 PLATFORM_REG_MBISR_DATA_SRAM_CTRL*/
+#define PLATFORM_REG_MBISR_DATA_SRAM_CTRL_bisr_remap_rstn_data_ram_Pos                                       0U
+#define PLATFORM_REG_MBISR_DATA_SRAM_CTRL_bisr_remap_rstn_data_ram_Msk                                       (0x1UL << PLATFORM_REG_MBISR_DATA_SRAM_CTRL_bisr_remap_rstn_data_ram_Pos)
+
+#define PLATFORM_REG_MBISR_DATA_SRAM_CTRL_bisr_load_fuse_data_ram_Pos                                        1U
+#define PLATFORM_REG_MBISR_DATA_SRAM_CTRL_bisr_load_fuse_data_ram_Msk                                        (0x1UL << PLATFORM_REG_MBISR_DATA_SRAM_CTRL_bisr_load_fuse_data_ram_Pos)
+
+#define PLATFORM_REG_MBISR_DATA_SRAM_CTRL_bisr_remap_sig_data_ram_Pos                                        2U
+#define PLATFORM_REG_MBISR_DATA_SRAM_CTRL_bisr_remap_sig_data_ram_Msk                                        (0x3FFFFUL << PLATFORM_REG_MBISR_DATA_SRAM_CTRL_bisr_remap_sig_data_ram_Pos)
+
+#define PLATFORM_REG_MBISR_DATA_SRAM_CTRL_bisr_second_run_data_ram_Pos                                       20U
+#define PLATFORM_REG_MBISR_DATA_SRAM_CTRL_bisr_second_run_data_ram_Msk                                       (0x1UL << PLATFORM_REG_MBISR_DATA_SRAM_CTRL_bisr_second_run_data_ram_Pos)
+
+#define PLATFORM_REG_MBISR_DATA_SRAM_CTRL_bisr_hold_remap_data_ram_Pos                                       21U
+#define PLATFORM_REG_MBISR_DATA_SRAM_CTRL_bisr_hold_remap_data_ram_Msk                                       (0x1UL << PLATFORM_REG_MBISR_DATA_SRAM_CTRL_bisr_hold_remap_data_ram_Pos)
+
+#define PLATFORM_REG_MBISR_DATA_SRAM_CTRL_bisr_pwr_rstn_data_ram_Pos                                         22U
+#define PLATFORM_REG_MBISR_DATA_SRAM_CTRL_bisr_pwr_rstn_data_ram_Msk                                         (0x1UL << PLATFORM_REG_MBISR_DATA_SRAM_CTRL_bisr_pwr_rstn_data_ram_Pos)
+
+#define PLATFORM_REG_MBISR_DATA_SRAM_CTRL_RSVD_Pos                                                           23U
+#define PLATFORM_REG_MBISR_DATA_SRAM_CTRL_RSVD_Msk                                                           (0x1FFUL << PLATFORM_REG_MBISR_DATA_SRAM_CTRL_RSVD_Pos)
+
+/* 0x00CC   0x4000_60cc
+    0       R/W     bisr_remap_rstn_buffer_ram                          1'b0
+    1       R/W     bisr_load_fuse_buffer_ram                           1'b0
+    8:2     R/W     bisr_remap_sig_buffer_ram                           7'h0
+    9       R/W     bisr_second_run_buffer_ram                          1'b0
+    10      R/W     bisr_hold_remap_buffer_ram                          1'b0
+    11      R/W     bisr_pwr_rstn_buffer_ram                            1'b1
+    31:12   R       RSVD                                                20'h0
+ */
+typedef union _PLATFORM_REG_MBISR_BUF_SRAM_CTRL_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t bisr_remap_rstn_buffer_ram: 1;
+        uint32_t bisr_load_fuse_buffer_ram: 1;
+        uint32_t bisr_remap_sig_buffer_ram: 7;
+        uint32_t bisr_second_run_buffer_ram: 1;
+        uint32_t bisr_hold_remap_buffer_ram: 1;
+        uint32_t bisr_pwr_rstn_buffer_ram: 1;
+        uint32_t RSVD: 20;
+    };
+} PLATFORM_REG_MBISR_BUF_SRAM_CTRL_TYPE;
+
+/*0x4000_60cc PLATFORM_REG_MBISR_BUF_SRAM_CTRL*/
+#define PLATFORM_REG_MBISR_BUF_SRAM_CTRL_bisr_remap_rstn_buffer_ram_Pos                                      0U
+#define PLATFORM_REG_MBISR_BUF_SRAM_CTRL_bisr_remap_rstn_buffer_ram_Msk                                      (0x1UL << PLATFORM_REG_MBISR_BUF_SRAM_CTRL_bisr_remap_rstn_buffer_ram_Pos)
+
+#define PLATFORM_REG_MBISR_BUF_SRAM_CTRL_bisr_load_fuse_buffer_ram_Pos                                       1U
+#define PLATFORM_REG_MBISR_BUF_SRAM_CTRL_bisr_load_fuse_buffer_ram_Msk                                       (0x1UL << PLATFORM_REG_MBISR_BUF_SRAM_CTRL_bisr_load_fuse_buffer_ram_Pos)
+
+#define PLATFORM_REG_MBISR_BUF_SRAM_CTRL_bisr_remap_sig_buffer_ram_Pos                                       2U
+#define PLATFORM_REG_MBISR_BUF_SRAM_CTRL_bisr_remap_sig_buffer_ram_Msk                                       (0x7FUL << PLATFORM_REG_MBISR_BUF_SRAM_CTRL_bisr_remap_sig_buffer_ram_Pos)
+
+#define PLATFORM_REG_MBISR_BUF_SRAM_CTRL_bisr_second_run_buffer_ram_Pos                                      9U
+#define PLATFORM_REG_MBISR_BUF_SRAM_CTRL_bisr_second_run_buffer_ram_Msk                                      (0x1UL << PLATFORM_REG_MBISR_BUF_SRAM_CTRL_bisr_second_run_buffer_ram_Pos)
+
+#define PLATFORM_REG_MBISR_BUF_SRAM_CTRL_bisr_hold_remap_buffer_ram_Pos                                      10U
+#define PLATFORM_REG_MBISR_BUF_SRAM_CTRL_bisr_hold_remap_buffer_ram_Msk                                      (0x1UL << PLATFORM_REG_MBISR_BUF_SRAM_CTRL_bisr_hold_remap_buffer_ram_Pos)
+
+#define PLATFORM_REG_MBISR_BUF_SRAM_CTRL_bisr_pwr_rstn_buffer_ram_Pos                                        11U
+#define PLATFORM_REG_MBISR_BUF_SRAM_CTRL_bisr_pwr_rstn_buffer_ram_Msk                                        (0x1UL << PLATFORM_REG_MBISR_BUF_SRAM_CTRL_bisr_pwr_rstn_buffer_ram_Pos)
+
+#define PLATFORM_REG_MBISR_BUF_SRAM_CTRL_RSVD_Pos                                                            12U
+#define PLATFORM_REG_MBISR_BUF_SRAM_CTRL_RSVD_Msk                                                            (0xFFFFFUL << PLATFORM_REG_MBISR_BUF_SRAM_CTRL_RSVD_Pos)
+
+/* 0x00D0   0x4000_60d0
+    6:0     R       bisr_out_buffer_ram                                 7'h0
+    7       R       bisr_repaired_buffer_ram                            0
+    9:8     R       RSVD_1                                              2'h0
+    27:10   R       bisr_out_data_ram                                   18'h0
+    28      R       bisr_repaired_data_ram                              0
+    31:29   R       RSVD                                                3'h0
+ */
+typedef union _PLATFORM_REG_MBISR_SRAM_RESULT_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t bisr_out_buffer_ram: 7;
+        uint32_t bisr_repaired_buffer_ram: 1;
+        uint32_t RSVD_1: 2;
+        uint32_t bisr_out_data_ram: 18;
+        uint32_t bisr_repaired_data_ram: 1;
+        uint32_t RSVD: 3;
+    };
+} PLATFORM_REG_MBISR_SRAM_RESULT_TYPE;
+
+/*0x4000_60d0 PLATFORM_REG_MBISR_SRAM_RESULT*/
+#define PLATFORM_REG_MBISR_SRAM_RESULT_bisr_out_buffer_ram_Pos                                               0U
+#define PLATFORM_REG_MBISR_SRAM_RESULT_bisr_out_buffer_ram_Msk                                               (0x7FUL << PLATFORM_REG_MBISR_SRAM_RESULT_bisr_out_buffer_ram_Pos)
+
+#define PLATFORM_REG_MBISR_SRAM_RESULT_bisr_repaired_buffer_ram_Pos                                          7U
+#define PLATFORM_REG_MBISR_SRAM_RESULT_bisr_repaired_buffer_ram_Msk                                          (0x1UL << PLATFORM_REG_MBISR_SRAM_RESULT_bisr_repaired_buffer_ram_Pos)
+
+#define PLATFORM_REG_MBISR_SRAM_RESULT_RSVD_1_Pos                                                            8U
+#define PLATFORM_REG_MBISR_SRAM_RESULT_RSVD_1_Msk                                                            (0x3UL << PLATFORM_REG_MBISR_SRAM_RESULT_RSVD_1_Pos)
+
+#define PLATFORM_REG_MBISR_SRAM_RESULT_bisr_out_data_ram_Pos                                                 10U
+#define PLATFORM_REG_MBISR_SRAM_RESULT_bisr_out_data_ram_Msk                                                 (0x3FFFFUL << PLATFORM_REG_MBISR_SRAM_RESULT_bisr_out_data_ram_Pos)
+
+#define PLATFORM_REG_MBISR_SRAM_RESULT_bisr_repaired_data_ram_Pos                                            28U
+#define PLATFORM_REG_MBISR_SRAM_RESULT_bisr_repaired_data_ram_Msk                                            (0x1UL << PLATFORM_REG_MBISR_SRAM_RESULT_bisr_repaired_data_ram_Pos)
+
+#define PLATFORM_REG_MBISR_SRAM_RESULT_RSVD_Pos                                                              29U
+#define PLATFORM_REG_MBISR_SRAM_RESULT_RSVD_Msk                                                              (0x7UL << PLATFORM_REG_MBISR_SRAM_RESULT_RSVD_Pos)
+
+/* 0x00D4   0x4000_60d4
+    0       R/W     bist_dyn_read_en_data_ram                           0
+    1       R/W     bist_dyn_read_en_cpu_ram                            0
+    2       R/W     bist_dyn_read_en_usb_ram                            0
+    3       R/W     bist_dyn_read_en_can_ram                            0
+    4       R/W     bist_dyn_read_en_leslv_ram                          0
+    5       R/W     bist_dyn_read_en_lecis_ram                          0
+    6       R/W     bist_dyn_read_en_lebis_ram                          0
+    7       R/W     bist_dyn_read_en_buffer_ram                         0
+    8       R/W     bist_dyn_read_en_audio_ram                          0
+    9       R/W     bist_dyn_read_en_btphy_ram                          0
+    10      R/W     bist_dyn_read_en_ccmp_ram                           0
+    11      R/W     bist_dyn_read_en_btrx_ram                           0
+    12      R/W     bist_dyn_read_en_bttx_ram                           0
+    13      R/W     bist_dyn_read_en_lepa_ram                           0
+    14      R/W     bist_dyn_read_en_lemst_ram                          0
+    15      R/W     bist_dyn_read_en_cache_ram                          0
+    16      R/W     bist_dyn_read_en_amu_ram                            0
+    31:17   R       RSVD                                                15'h0
+ */
+typedef union _PLATFORM_REG_DYN_READ_EN_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t bist_dyn_read_en_data_ram: 1;
+        uint32_t bist_dyn_read_en_cpu_ram: 1;
+        uint32_t bist_dyn_read_en_usb_ram: 1;
+        uint32_t bist_dyn_read_en_can_ram: 1;
+        uint32_t bist_dyn_read_en_leslv_ram: 1;
+        uint32_t bist_dyn_read_en_lecis_ram: 1;
+        uint32_t bist_dyn_read_en_lebis_ram: 1;
+        uint32_t bist_dyn_read_en_buffer_ram: 1;
+        uint32_t bist_dyn_read_en_audio_ram: 1;
+        uint32_t bist_dyn_read_en_btphy_ram: 1;
+        uint32_t bist_dyn_read_en_ccmp_ram: 1;
+        uint32_t bist_dyn_read_en_btrx_ram: 1;
+        uint32_t bist_dyn_read_en_bttx_ram: 1;
+        uint32_t bist_dyn_read_en_lepa_ram: 1;
+        uint32_t bist_dyn_read_en_lemst_ram: 1;
+        uint32_t bist_dyn_read_en_cache_ram: 1;
+        uint32_t bist_dyn_read_en_amu_ram: 1;
+        uint32_t RSVD: 15;
+    };
+} PLATFORM_REG_DYN_READ_EN_TYPE;
+
+/*0x4000_60d4 PLATFORM_REG_DYN_READ_EN*/
+#define PLATFORM_REG_DYN_READ_EN_bist_dyn_read_en_data_ram_Pos                                               0U
+#define PLATFORM_REG_DYN_READ_EN_bist_dyn_read_en_data_ram_Msk                                               (0x1UL << PLATFORM_REG_DYN_READ_EN_bist_dyn_read_en_data_ram_Pos)
+
+#define PLATFORM_REG_DYN_READ_EN_bist_dyn_read_en_cpu_ram_Pos                                                1U
+#define PLATFORM_REG_DYN_READ_EN_bist_dyn_read_en_cpu_ram_Msk                                                (0x1UL << PLATFORM_REG_DYN_READ_EN_bist_dyn_read_en_cpu_ram_Pos)
+
+#define PLATFORM_REG_DYN_READ_EN_bist_dyn_read_en_usb_ram_Pos                                                2U
+#define PLATFORM_REG_DYN_READ_EN_bist_dyn_read_en_usb_ram_Msk                                                (0x1UL << PLATFORM_REG_DYN_READ_EN_bist_dyn_read_en_usb_ram_Pos)
+
+#define PLATFORM_REG_DYN_READ_EN_bist_dyn_read_en_can_ram_Pos                                                3U
+#define PLATFORM_REG_DYN_READ_EN_bist_dyn_read_en_can_ram_Msk                                                (0x1UL << PLATFORM_REG_DYN_READ_EN_bist_dyn_read_en_can_ram_Pos)
+
+#define PLATFORM_REG_DYN_READ_EN_bist_dyn_read_en_leslv_ram_Pos                                              4U
+#define PLATFORM_REG_DYN_READ_EN_bist_dyn_read_en_leslv_ram_Msk                                              (0x1UL << PLATFORM_REG_DYN_READ_EN_bist_dyn_read_en_leslv_ram_Pos)
+
+#define PLATFORM_REG_DYN_READ_EN_bist_dyn_read_en_lecis_ram_Pos                                              5U
+#define PLATFORM_REG_DYN_READ_EN_bist_dyn_read_en_lecis_ram_Msk                                              (0x1UL << PLATFORM_REG_DYN_READ_EN_bist_dyn_read_en_lecis_ram_Pos)
+
+#define PLATFORM_REG_DYN_READ_EN_bist_dyn_read_en_lebis_ram_Pos                                              6U
+#define PLATFORM_REG_DYN_READ_EN_bist_dyn_read_en_lebis_ram_Msk                                              (0x1UL << PLATFORM_REG_DYN_READ_EN_bist_dyn_read_en_lebis_ram_Pos)
+
+#define PLATFORM_REG_DYN_READ_EN_bist_dyn_read_en_buffer_ram_Pos                                             7U
+#define PLATFORM_REG_DYN_READ_EN_bist_dyn_read_en_buffer_ram_Msk                                             (0x1UL << PLATFORM_REG_DYN_READ_EN_bist_dyn_read_en_buffer_ram_Pos)
+
+#define PLATFORM_REG_DYN_READ_EN_bist_dyn_read_en_audio_ram_Pos                                              8U
+#define PLATFORM_REG_DYN_READ_EN_bist_dyn_read_en_audio_ram_Msk                                              (0x1UL << PLATFORM_REG_DYN_READ_EN_bist_dyn_read_en_audio_ram_Pos)
+
+#define PLATFORM_REG_DYN_READ_EN_bist_dyn_read_en_btphy_ram_Pos                                              9U
+#define PLATFORM_REG_DYN_READ_EN_bist_dyn_read_en_btphy_ram_Msk                                              (0x1UL << PLATFORM_REG_DYN_READ_EN_bist_dyn_read_en_btphy_ram_Pos)
+
+#define PLATFORM_REG_DYN_READ_EN_bist_dyn_read_en_ccmp_ram_Pos                                               10U
+#define PLATFORM_REG_DYN_READ_EN_bist_dyn_read_en_ccmp_ram_Msk                                               (0x1UL << PLATFORM_REG_DYN_READ_EN_bist_dyn_read_en_ccmp_ram_Pos)
+
+#define PLATFORM_REG_DYN_READ_EN_bist_dyn_read_en_btrx_ram_Pos                                               11U
+#define PLATFORM_REG_DYN_READ_EN_bist_dyn_read_en_btrx_ram_Msk                                               (0x1UL << PLATFORM_REG_DYN_READ_EN_bist_dyn_read_en_btrx_ram_Pos)
+
+#define PLATFORM_REG_DYN_READ_EN_bist_dyn_read_en_bttx_ram_Pos                                               12U
+#define PLATFORM_REG_DYN_READ_EN_bist_dyn_read_en_bttx_ram_Msk                                               (0x1UL << PLATFORM_REG_DYN_READ_EN_bist_dyn_read_en_bttx_ram_Pos)
+
+#define PLATFORM_REG_DYN_READ_EN_bist_dyn_read_en_lepa_ram_Pos                                               13U
+#define PLATFORM_REG_DYN_READ_EN_bist_dyn_read_en_lepa_ram_Msk                                               (0x1UL << PLATFORM_REG_DYN_READ_EN_bist_dyn_read_en_lepa_ram_Pos)
+
+#define PLATFORM_REG_DYN_READ_EN_bist_dyn_read_en_lemst_ram_Pos                                              14U
+#define PLATFORM_REG_DYN_READ_EN_bist_dyn_read_en_lemst_ram_Msk                                              (0x1UL << PLATFORM_REG_DYN_READ_EN_bist_dyn_read_en_lemst_ram_Pos)
+
+#define PLATFORM_REG_DYN_READ_EN_bist_dyn_read_en_cache_ram_Pos                                              15U
+#define PLATFORM_REG_DYN_READ_EN_bist_dyn_read_en_cache_ram_Msk                                              (0x1UL << PLATFORM_REG_DYN_READ_EN_bist_dyn_read_en_cache_ram_Pos)
+
+#define PLATFORM_REG_DYN_READ_EN_bist_dyn_read_en_amu_ram_Pos                                                16U
+#define PLATFORM_REG_DYN_READ_EN_bist_dyn_read_en_amu_ram_Msk                                                (0x1UL << PLATFORM_REG_DYN_READ_EN_bist_dyn_read_en_amu_ram_Pos)
+
+#define PLATFORM_REG_DYN_READ_EN_RSVD_Pos                                                                    17U
+#define PLATFORM_REG_DYN_READ_EN_RSVD_Msk                                                                    (0x7FFFUL << PLATFORM_REG_DYN_READ_EN_RSVD_Pos)
+
+/* 0x00D8   0x4000_60d8
+    0       R/W     bist_loop_mode_data_ram                             0
+    1       R/W     bist_loop_mode_cpu_ram                              0
+    2       R/W     bist_loop_mode_usb_ram                              0
+    3       R/W     bist_loop_mode_can_ram                              0
+    4       R/W     bist_loop_mode_cache_ram                            0
+    5       R/W     bist_loop_mode_amu_ram                              0
+    31:6    R       RSVD                                                26'h0
+ */
+typedef union _PLATFORM_REG_BIST_LOOP_MODE_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t bist_loop_mode_data_ram: 1;
+        uint32_t bist_loop_mode_cpu_ram: 1;
+        uint32_t bist_loop_mode_usb_ram: 1;
+        uint32_t bist_loop_mode_can_ram: 1;
+        uint32_t bist_loop_mode_cache_ram: 1;
+        uint32_t bist_loop_mode_amu_ram: 1;
+        uint32_t RSVD: 26;
+    };
+} PLATFORM_REG_BIST_LOOP_MODE_TYPE;
+
+/*0x4000_60d8 PLATFORM_REG_BIST_LOOP_MODE*/
+#define PLATFORM_REG_BIST_LOOP_MODE_bist_loop_mode_data_ram_Pos                                              0U
+#define PLATFORM_REG_BIST_LOOP_MODE_bist_loop_mode_data_ram_Msk                                              (0x1UL << PLATFORM_REG_BIST_LOOP_MODE_bist_loop_mode_data_ram_Pos)
+
+#define PLATFORM_REG_BIST_LOOP_MODE_bist_loop_mode_cpu_ram_Pos                                               1U
+#define PLATFORM_REG_BIST_LOOP_MODE_bist_loop_mode_cpu_ram_Msk                                               (0x1UL << PLATFORM_REG_BIST_LOOP_MODE_bist_loop_mode_cpu_ram_Pos)
+
+#define PLATFORM_REG_BIST_LOOP_MODE_bist_loop_mode_usb_ram_Pos                                               2U
+#define PLATFORM_REG_BIST_LOOP_MODE_bist_loop_mode_usb_ram_Msk                                               (0x1UL << PLATFORM_REG_BIST_LOOP_MODE_bist_loop_mode_usb_ram_Pos)
+
+#define PLATFORM_REG_BIST_LOOP_MODE_bist_loop_mode_can_ram_Pos                                               3U
+#define PLATFORM_REG_BIST_LOOP_MODE_bist_loop_mode_can_ram_Msk                                               (0x1UL << PLATFORM_REG_BIST_LOOP_MODE_bist_loop_mode_can_ram_Pos)
+
+#define PLATFORM_REG_BIST_LOOP_MODE_bist_loop_mode_cache_ram_Pos                                             4U
+#define PLATFORM_REG_BIST_LOOP_MODE_bist_loop_mode_cache_ram_Msk                                             (0x1UL << PLATFORM_REG_BIST_LOOP_MODE_bist_loop_mode_cache_ram_Pos)
+
+#define PLATFORM_REG_BIST_LOOP_MODE_bist_loop_mode_amu_ram_Pos                                               5U
+#define PLATFORM_REG_BIST_LOOP_MODE_bist_loop_mode_amu_ram_Msk                                               (0x1UL << PLATFORM_REG_BIST_LOOP_MODE_bist_loop_mode_amu_ram_Pos)
+
+#define PLATFORM_REG_BIST_LOOP_MODE_RSVD_Pos                                                                 6U
+#define PLATFORM_REG_BIST_LOOP_MODE_RSVD_Msk                                                                 (0x3FFFFFFUL << PLATFORM_REG_BIST_LOOP_MODE_RSVD_Pos)
+
+/* 0x00DC   0x4000_60dc
+    0       R/W     bist_loop_mode_leslv_ram                            0
+    1       R/W     bist_loop_mode_lecis_ram                            0
+    2       R/W     bist_loop_mode_lebis_ram                            0
+    3       R/W     bist_loop_mode_buffer_ram                           0
+    4       R/W     bist_loop_mode_audio_ram                            0
+    5       R/W     bist_loop_mode_btphy_ram                            0
+    6       R/W     bist_loop_mode_ccmp_ram                             0
+    7       R/W     bist_loop_mode_btrx_ram                             0
+    8       R/W     bist_loop_mode_bttx_ram                             0
+    9       R/W     bist_loop_mode_lepa_ram                             0
+    10      R/W     bist_loop_mode_lemst_ram                            0
+    11      R       RSVD_2                                              0
+    12      R/W     RSVD_1                                              0
+    31:13   R       RSVD                                                19'h0
+ */
+typedef union _PLATFORM_REG_BT_BIST_LOOP_MODE_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t bist_loop_mode_leslv_ram: 1;
+        uint32_t bist_loop_mode_lecis_ram: 1;
+        uint32_t bist_loop_mode_lebis_ram: 1;
+        uint32_t bist_loop_mode_buffer_ram: 1;
+        uint32_t bist_loop_mode_audio_ram: 1;
+        uint32_t bist_loop_mode_btphy_ram: 1;
+        uint32_t bist_loop_mode_ccmp_ram: 1;
+        uint32_t bist_loop_mode_btrx_ram: 1;
+        uint32_t bist_loop_mode_bttx_ram: 1;
+        uint32_t bist_loop_mode_lepa_ram: 1;
+        uint32_t bist_loop_mode_lemst_ram: 1;
+        uint32_t RSVD_2: 1;
+        uint32_t RSVD_1: 1;
+        uint32_t RSVD: 19;
+    };
+} PLATFORM_REG_BT_BIST_LOOP_MODE_TYPE;
+
+/*0x4000_60dc PLATFORM_REG_BT_BIST_LOOP_MODE*/
+#define PLATFORM_REG_BT_BIST_LOOP_MODE_bist_loop_mode_leslv_ram_Pos                                          0U
+#define PLATFORM_REG_BT_BIST_LOOP_MODE_bist_loop_mode_leslv_ram_Msk                                          (0x1UL << PLATFORM_REG_BT_BIST_LOOP_MODE_bist_loop_mode_leslv_ram_Pos)
+
+#define PLATFORM_REG_BT_BIST_LOOP_MODE_bist_loop_mode_lecis_ram_Pos                                          1U
+#define PLATFORM_REG_BT_BIST_LOOP_MODE_bist_loop_mode_lecis_ram_Msk                                          (0x1UL << PLATFORM_REG_BT_BIST_LOOP_MODE_bist_loop_mode_lecis_ram_Pos)
+
+#define PLATFORM_REG_BT_BIST_LOOP_MODE_bist_loop_mode_lebis_ram_Pos                                          2U
+#define PLATFORM_REG_BT_BIST_LOOP_MODE_bist_loop_mode_lebis_ram_Msk                                          (0x1UL << PLATFORM_REG_BT_BIST_LOOP_MODE_bist_loop_mode_lebis_ram_Pos)
+
+#define PLATFORM_REG_BT_BIST_LOOP_MODE_bist_loop_mode_buffer_ram_Pos                                         3U
+#define PLATFORM_REG_BT_BIST_LOOP_MODE_bist_loop_mode_buffer_ram_Msk                                         (0x1UL << PLATFORM_REG_BT_BIST_LOOP_MODE_bist_loop_mode_buffer_ram_Pos)
+
+#define PLATFORM_REG_BT_BIST_LOOP_MODE_bist_loop_mode_audio_ram_Pos                                          4U
+#define PLATFORM_REG_BT_BIST_LOOP_MODE_bist_loop_mode_audio_ram_Msk                                          (0x1UL << PLATFORM_REG_BT_BIST_LOOP_MODE_bist_loop_mode_audio_ram_Pos)
+
+#define PLATFORM_REG_BT_BIST_LOOP_MODE_bist_loop_mode_btphy_ram_Pos                                          5U
+#define PLATFORM_REG_BT_BIST_LOOP_MODE_bist_loop_mode_btphy_ram_Msk                                          (0x1UL << PLATFORM_REG_BT_BIST_LOOP_MODE_bist_loop_mode_btphy_ram_Pos)
+
+#define PLATFORM_REG_BT_BIST_LOOP_MODE_bist_loop_mode_ccmp_ram_Pos                                           6U
+#define PLATFORM_REG_BT_BIST_LOOP_MODE_bist_loop_mode_ccmp_ram_Msk                                           (0x1UL << PLATFORM_REG_BT_BIST_LOOP_MODE_bist_loop_mode_ccmp_ram_Pos)
+
+#define PLATFORM_REG_BT_BIST_LOOP_MODE_bist_loop_mode_btrx_ram_Pos                                           7U
+#define PLATFORM_REG_BT_BIST_LOOP_MODE_bist_loop_mode_btrx_ram_Msk                                           (0x1UL << PLATFORM_REG_BT_BIST_LOOP_MODE_bist_loop_mode_btrx_ram_Pos)
+
+#define PLATFORM_REG_BT_BIST_LOOP_MODE_bist_loop_mode_bttx_ram_Pos                                           8U
+#define PLATFORM_REG_BT_BIST_LOOP_MODE_bist_loop_mode_bttx_ram_Msk                                           (0x1UL << PLATFORM_REG_BT_BIST_LOOP_MODE_bist_loop_mode_bttx_ram_Pos)
+
+#define PLATFORM_REG_BT_BIST_LOOP_MODE_bist_loop_mode_lepa_ram_Pos                                           9U
+#define PLATFORM_REG_BT_BIST_LOOP_MODE_bist_loop_mode_lepa_ram_Msk                                           (0x1UL << PLATFORM_REG_BT_BIST_LOOP_MODE_bist_loop_mode_lepa_ram_Pos)
+
+#define PLATFORM_REG_BT_BIST_LOOP_MODE_bist_loop_mode_lemst_ram_Pos                                          10U
+#define PLATFORM_REG_BT_BIST_LOOP_MODE_bist_loop_mode_lemst_ram_Msk                                          (0x1UL << PLATFORM_REG_BT_BIST_LOOP_MODE_bist_loop_mode_lemst_ram_Pos)
+
+#define PLATFORM_REG_BT_BIST_LOOP_MODE_RSVD_2_Pos                                                            11U
+#define PLATFORM_REG_BT_BIST_LOOP_MODE_RSVD_2_Msk                                                            (0x1UL << PLATFORM_REG_BT_BIST_LOOP_MODE_RSVD_2_Pos)
+
+#define PLATFORM_REG_BT_BIST_LOOP_MODE_RSVD_1_Pos                                                            12U
+#define PLATFORM_REG_BT_BIST_LOOP_MODE_RSVD_1_Msk                                                            (0x1UL << PLATFORM_REG_BT_BIST_LOOP_MODE_RSVD_1_Pos)
+
+#define PLATFORM_REG_BT_BIST_LOOP_MODE_RSVD_Pos                                                              13U
+#define PLATFORM_REG_BT_BIST_LOOP_MODE_RSVD_Msk                                                              (0x7FFFFUL << PLATFORM_REG_BT_BIST_LOOP_MODE_RSVD_Pos)
+
+/* 0x00E0   0x4000_60e0
+    0       R/W     bist_rstn_leslv_ram                                 0
+    1       R/W     bist_rstn_lecis_ram                                 0
+    2       R/W     bist_rstn_lebis_ram                                 0
+    3       R/W     bist_rstn_buffer_ram                                0
+    4       R/W     bist_rstn_audio_ram                                 0
+    5       R/W     bist_rstn_btphy_ram                                 0
+    6       R/W     bist_rstn_ccmp_ram                                  0
+    7       R/W     bist_rstn_btrx_ram                                  0
+    8       R/W     bist_rstn_bttx_ram                                  0
+    9       R/W     bist_rstn_lepa_ram                                  0
+    10      R/W     bist_rstn_lemst_ram                                 0
+    11      R       RSVD_2                                              0
+    12      R/W     RSVD_1                                              0
+    31:13   R       RSVD                                                19'h0
+ */
+typedef union _PLATFORM_REG_BT_BIST_RSTN_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t bist_rstn_leslv_ram: 1;
+        uint32_t bist_rstn_lecis_ram: 1;
+        uint32_t bist_rstn_lebis_ram: 1;
+        uint32_t bist_rstn_buffer_ram: 1;
+        uint32_t bist_rstn_audio_ram: 1;
+        uint32_t bist_rstn_btphy_ram: 1;
+        uint32_t bist_rstn_ccmp_ram: 1;
+        uint32_t bist_rstn_btrx_ram: 1;
+        uint32_t bist_rstn_bttx_ram: 1;
+        uint32_t bist_rstn_lepa_ram: 1;
+        uint32_t bist_rstn_lemst_ram: 1;
+        uint32_t RSVD_2: 1;
+        uint32_t RSVD_1: 1;
+        uint32_t RSVD: 19;
+    };
+} PLATFORM_REG_BT_BIST_RSTN_TYPE;
+
+/*0x4000_60e0 PLATFORM_REG_BT_BIST_RSTN*/
+#define PLATFORM_REG_BT_BIST_RSTN_bist_rstn_leslv_ram_Pos                                                    0U
+#define PLATFORM_REG_BT_BIST_RSTN_bist_rstn_leslv_ram_Msk                                                    (0x1UL << PLATFORM_REG_BT_BIST_RSTN_bist_rstn_leslv_ram_Pos)
+
+#define PLATFORM_REG_BT_BIST_RSTN_bist_rstn_lecis_ram_Pos                                                    1U
+#define PLATFORM_REG_BT_BIST_RSTN_bist_rstn_lecis_ram_Msk                                                    (0x1UL << PLATFORM_REG_BT_BIST_RSTN_bist_rstn_lecis_ram_Pos)
+
+#define PLATFORM_REG_BT_BIST_RSTN_bist_rstn_lebis_ram_Pos                                                    2U
+#define PLATFORM_REG_BT_BIST_RSTN_bist_rstn_lebis_ram_Msk                                                    (0x1UL << PLATFORM_REG_BT_BIST_RSTN_bist_rstn_lebis_ram_Pos)
+
+#define PLATFORM_REG_BT_BIST_RSTN_bist_rstn_buffer_ram_Pos                                                   3U
+#define PLATFORM_REG_BT_BIST_RSTN_bist_rstn_buffer_ram_Msk                                                   (0x1UL << PLATFORM_REG_BT_BIST_RSTN_bist_rstn_buffer_ram_Pos)
+
+#define PLATFORM_REG_BT_BIST_RSTN_bist_rstn_audio_ram_Pos                                                    4U
+#define PLATFORM_REG_BT_BIST_RSTN_bist_rstn_audio_ram_Msk                                                    (0x1UL << PLATFORM_REG_BT_BIST_RSTN_bist_rstn_audio_ram_Pos)
+
+#define PLATFORM_REG_BT_BIST_RSTN_bist_rstn_btphy_ram_Pos                                                    5U
+#define PLATFORM_REG_BT_BIST_RSTN_bist_rstn_btphy_ram_Msk                                                    (0x1UL << PLATFORM_REG_BT_BIST_RSTN_bist_rstn_btphy_ram_Pos)
+
+#define PLATFORM_REG_BT_BIST_RSTN_bist_rstn_ccmp_ram_Pos                                                     6U
+#define PLATFORM_REG_BT_BIST_RSTN_bist_rstn_ccmp_ram_Msk                                                     (0x1UL << PLATFORM_REG_BT_BIST_RSTN_bist_rstn_ccmp_ram_Pos)
+
+#define PLATFORM_REG_BT_BIST_RSTN_bist_rstn_btrx_ram_Pos                                                     7U
+#define PLATFORM_REG_BT_BIST_RSTN_bist_rstn_btrx_ram_Msk                                                     (0x1UL << PLATFORM_REG_BT_BIST_RSTN_bist_rstn_btrx_ram_Pos)
+
+#define PLATFORM_REG_BT_BIST_RSTN_bist_rstn_bttx_ram_Pos                                                     8U
+#define PLATFORM_REG_BT_BIST_RSTN_bist_rstn_bttx_ram_Msk                                                     (0x1UL << PLATFORM_REG_BT_BIST_RSTN_bist_rstn_bttx_ram_Pos)
+
+#define PLATFORM_REG_BT_BIST_RSTN_bist_rstn_lepa_ram_Pos                                                     9U
+#define PLATFORM_REG_BT_BIST_RSTN_bist_rstn_lepa_ram_Msk                                                     (0x1UL << PLATFORM_REG_BT_BIST_RSTN_bist_rstn_lepa_ram_Pos)
+
+#define PLATFORM_REG_BT_BIST_RSTN_bist_rstn_lemst_ram_Pos                                                    10U
+#define PLATFORM_REG_BT_BIST_RSTN_bist_rstn_lemst_ram_Msk                                                    (0x1UL << PLATFORM_REG_BT_BIST_RSTN_bist_rstn_lemst_ram_Pos)
+
+#define PLATFORM_REG_BT_BIST_RSTN_RSVD_2_Pos                                                                 11U
+#define PLATFORM_REG_BT_BIST_RSTN_RSVD_2_Msk                                                                 (0x1UL << PLATFORM_REG_BT_BIST_RSTN_RSVD_2_Pos)
+
+#define PLATFORM_REG_BT_BIST_RSTN_RSVD_1_Pos                                                                 12U
+#define PLATFORM_REG_BT_BIST_RSTN_RSVD_1_Msk                                                                 (0x1UL << PLATFORM_REG_BT_BIST_RSTN_RSVD_1_Pos)
+
+#define PLATFORM_REG_BT_BIST_RSTN_RSVD_Pos                                                                   13U
+#define PLATFORM_REG_BT_BIST_RSTN_RSVD_Msk                                                                   (0x7FFFFUL << PLATFORM_REG_BT_BIST_RSTN_RSVD_Pos)
+
+/* 0x00E4   0x4000_60e4
+    0       R/W     bist_mode_leslv_ram                                 0
+    1       R/W     bist_mode_lecis_ram                                 0
+    2       R/W     bist_mode_lebis_ram                                 0
+    3       R/W     bist_mode_buffer_ram                                0
+    4       R/W     bist_mode_audio_ram                                 0
+    5       R/W     bist_mode_btphy_ram                                 0
+    6       R/W     bist_mode_ccmp_ram                                  0
+    7       R/W     bist_mode_btrx_ram                                  0
+    8       R/W     bist_mode_bttx_ram                                  0
+    9       R/W     bist_mode_lepa_ram                                  0
+    10      R/W     bist_mode_lemst_ram                                 0
+    11      R       RSVD_2                                              0
+    12      R/W     RSVD_1                                              0
+    31:13   R       RSVD                                                19'h0
+ */
+typedef union _PLATFORM_REG_BT_BIST_MODE_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t bist_mode_leslv_ram: 1;
+        uint32_t bist_mode_lecis_ram: 1;
+        uint32_t bist_mode_lebis_ram: 1;
+        uint32_t bist_mode_buffer_ram: 1;
+        uint32_t bist_mode_audio_ram: 1;
+        uint32_t bist_mode_btphy_ram: 1;
+        uint32_t bist_mode_ccmp_ram: 1;
+        uint32_t bist_mode_btrx_ram: 1;
+        uint32_t bist_mode_bttx_ram: 1;
+        uint32_t bist_mode_lepa_ram: 1;
+        uint32_t bist_mode_lemst_ram: 1;
+        uint32_t RSVD_2: 1;
+        uint32_t RSVD_1: 1;
+        uint32_t RSVD: 19;
+    };
+} PLATFORM_REG_BT_BIST_MODE_TYPE;
+
+/*0x4000_60e4 PLATFORM_REG_BT_BIST_MODE*/
+#define PLATFORM_REG_BT_BIST_MODE_bist_mode_leslv_ram_Pos                                                    0U
+#define PLATFORM_REG_BT_BIST_MODE_bist_mode_leslv_ram_Msk                                                    (0x1UL << PLATFORM_REG_BT_BIST_MODE_bist_mode_leslv_ram_Pos)
+
+#define PLATFORM_REG_BT_BIST_MODE_bist_mode_lecis_ram_Pos                                                    1U
+#define PLATFORM_REG_BT_BIST_MODE_bist_mode_lecis_ram_Msk                                                    (0x1UL << PLATFORM_REG_BT_BIST_MODE_bist_mode_lecis_ram_Pos)
+
+#define PLATFORM_REG_BT_BIST_MODE_bist_mode_lebis_ram_Pos                                                    2U
+#define PLATFORM_REG_BT_BIST_MODE_bist_mode_lebis_ram_Msk                                                    (0x1UL << PLATFORM_REG_BT_BIST_MODE_bist_mode_lebis_ram_Pos)
+
+#define PLATFORM_REG_BT_BIST_MODE_bist_mode_buffer_ram_Pos                                                   3U
+#define PLATFORM_REG_BT_BIST_MODE_bist_mode_buffer_ram_Msk                                                   (0x1UL << PLATFORM_REG_BT_BIST_MODE_bist_mode_buffer_ram_Pos)
+
+#define PLATFORM_REG_BT_BIST_MODE_bist_mode_audio_ram_Pos                                                    4U
+#define PLATFORM_REG_BT_BIST_MODE_bist_mode_audio_ram_Msk                                                    (0x1UL << PLATFORM_REG_BT_BIST_MODE_bist_mode_audio_ram_Pos)
+
+#define PLATFORM_REG_BT_BIST_MODE_bist_mode_btphy_ram_Pos                                                    5U
+#define PLATFORM_REG_BT_BIST_MODE_bist_mode_btphy_ram_Msk                                                    (0x1UL << PLATFORM_REG_BT_BIST_MODE_bist_mode_btphy_ram_Pos)
+
+#define PLATFORM_REG_BT_BIST_MODE_bist_mode_ccmp_ram_Pos                                                     6U
+#define PLATFORM_REG_BT_BIST_MODE_bist_mode_ccmp_ram_Msk                                                     (0x1UL << PLATFORM_REG_BT_BIST_MODE_bist_mode_ccmp_ram_Pos)
+
+#define PLATFORM_REG_BT_BIST_MODE_bist_mode_btrx_ram_Pos                                                     7U
+#define PLATFORM_REG_BT_BIST_MODE_bist_mode_btrx_ram_Msk                                                     (0x1UL << PLATFORM_REG_BT_BIST_MODE_bist_mode_btrx_ram_Pos)
+
+#define PLATFORM_REG_BT_BIST_MODE_bist_mode_bttx_ram_Pos                                                     8U
+#define PLATFORM_REG_BT_BIST_MODE_bist_mode_bttx_ram_Msk                                                     (0x1UL << PLATFORM_REG_BT_BIST_MODE_bist_mode_bttx_ram_Pos)
+
+#define PLATFORM_REG_BT_BIST_MODE_bist_mode_lepa_ram_Pos                                                     9U
+#define PLATFORM_REG_BT_BIST_MODE_bist_mode_lepa_ram_Msk                                                     (0x1UL << PLATFORM_REG_BT_BIST_MODE_bist_mode_lepa_ram_Pos)
+
+#define PLATFORM_REG_BT_BIST_MODE_bist_mode_lemst_ram_Pos                                                    10U
+#define PLATFORM_REG_BT_BIST_MODE_bist_mode_lemst_ram_Msk                                                    (0x1UL << PLATFORM_REG_BT_BIST_MODE_bist_mode_lemst_ram_Pos)
+
+#define PLATFORM_REG_BT_BIST_MODE_RSVD_2_Pos                                                                 11U
+#define PLATFORM_REG_BT_BIST_MODE_RSVD_2_Msk                                                                 (0x1UL << PLATFORM_REG_BT_BIST_MODE_RSVD_2_Pos)
+
+#define PLATFORM_REG_BT_BIST_MODE_RSVD_1_Pos                                                                 12U
+#define PLATFORM_REG_BT_BIST_MODE_RSVD_1_Msk                                                                 (0x1UL << PLATFORM_REG_BT_BIST_MODE_RSVD_1_Pos)
+
+#define PLATFORM_REG_BT_BIST_MODE_RSVD_Pos                                                                   13U
+#define PLATFORM_REG_BT_BIST_MODE_RSVD_Msk                                                                   (0x7FFFFUL << PLATFORM_REG_BT_BIST_MODE_RSVD_Pos)
+
+/* 0x00E8   0x4000_60e8
+    0       R/W     bist_mode_drf_leslv_ram                             0
+    1       R/W     bist_mode_drf_lecis_ram                             0
+    2       R/W     bist_mode_drf_lebis_ram                             0
+    3       R/W     bist_mode_drf_buffer_ram                            0
+    4       R/W     bist_mode_drf_audio_ram                             0
+    5       R/W     bist_mode_drf_btphy_ram                             0
+    6       R/W     bist_mode_drf_ccmp_ram                              0
+    7       R/W     bist_mode_drf_btrx_ram                              0
+    8       R/W     bist_mode_drf_bttx_ram                              0
+    9       R/W     bist_mode_drf_lepa_ram                              0
+    10      R/W     bist_mode_drf_lemst_ram                             0
+    11      R       RSVD_2                                              0
+    12      R/W     RSVD_1                                              0
+    31:13   R       RSVD                                                19'h0
+ */
+typedef union _PLATFORM_REG_BT_DRF_BIST_MODE_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t bist_mode_drf_leslv_ram: 1;
+        uint32_t bist_mode_drf_lecis_ram: 1;
+        uint32_t bist_mode_drf_lebis_ram: 1;
+        uint32_t bist_mode_drf_buffer_ram: 1;
+        uint32_t bist_mode_drf_audio_ram: 1;
+        uint32_t bist_mode_drf_btphy_ram: 1;
+        uint32_t bist_mode_drf_ccmp_ram: 1;
+        uint32_t bist_mode_drf_btrx_ram: 1;
+        uint32_t bist_mode_drf_bttx_ram: 1;
+        uint32_t bist_mode_drf_lepa_ram: 1;
+        uint32_t bist_mode_drf_lemst_ram: 1;
+        uint32_t RSVD_2: 1;
+        uint32_t RSVD_1: 1;
+        uint32_t RSVD: 19;
+    };
+} PLATFORM_REG_BT_DRF_BIST_MODE_TYPE;
+
+/*0x4000_60e8 PLATFORM_REG_BT_DRF_BIST_MODE*/
+#define PLATFORM_REG_BT_DRF_BIST_MODE_bist_mode_drf_leslv_ram_Pos                                            0U
+#define PLATFORM_REG_BT_DRF_BIST_MODE_bist_mode_drf_leslv_ram_Msk                                            (0x1UL << PLATFORM_REG_BT_DRF_BIST_MODE_bist_mode_drf_leslv_ram_Pos)
+
+#define PLATFORM_REG_BT_DRF_BIST_MODE_bist_mode_drf_lecis_ram_Pos                                            1U
+#define PLATFORM_REG_BT_DRF_BIST_MODE_bist_mode_drf_lecis_ram_Msk                                            (0x1UL << PLATFORM_REG_BT_DRF_BIST_MODE_bist_mode_drf_lecis_ram_Pos)
+
+#define PLATFORM_REG_BT_DRF_BIST_MODE_bist_mode_drf_lebis_ram_Pos                                            2U
+#define PLATFORM_REG_BT_DRF_BIST_MODE_bist_mode_drf_lebis_ram_Msk                                            (0x1UL << PLATFORM_REG_BT_DRF_BIST_MODE_bist_mode_drf_lebis_ram_Pos)
+
+#define PLATFORM_REG_BT_DRF_BIST_MODE_bist_mode_drf_buffer_ram_Pos                                           3U
+#define PLATFORM_REG_BT_DRF_BIST_MODE_bist_mode_drf_buffer_ram_Msk                                           (0x1UL << PLATFORM_REG_BT_DRF_BIST_MODE_bist_mode_drf_buffer_ram_Pos)
+
+#define PLATFORM_REG_BT_DRF_BIST_MODE_bist_mode_drf_audio_ram_Pos                                            4U
+#define PLATFORM_REG_BT_DRF_BIST_MODE_bist_mode_drf_audio_ram_Msk                                            (0x1UL << PLATFORM_REG_BT_DRF_BIST_MODE_bist_mode_drf_audio_ram_Pos)
+
+#define PLATFORM_REG_BT_DRF_BIST_MODE_bist_mode_drf_btphy_ram_Pos                                            5U
+#define PLATFORM_REG_BT_DRF_BIST_MODE_bist_mode_drf_btphy_ram_Msk                                            (0x1UL << PLATFORM_REG_BT_DRF_BIST_MODE_bist_mode_drf_btphy_ram_Pos)
+
+#define PLATFORM_REG_BT_DRF_BIST_MODE_bist_mode_drf_ccmp_ram_Pos                                             6U
+#define PLATFORM_REG_BT_DRF_BIST_MODE_bist_mode_drf_ccmp_ram_Msk                                             (0x1UL << PLATFORM_REG_BT_DRF_BIST_MODE_bist_mode_drf_ccmp_ram_Pos)
+
+#define PLATFORM_REG_BT_DRF_BIST_MODE_bist_mode_drf_btrx_ram_Pos                                             7U
+#define PLATFORM_REG_BT_DRF_BIST_MODE_bist_mode_drf_btrx_ram_Msk                                             (0x1UL << PLATFORM_REG_BT_DRF_BIST_MODE_bist_mode_drf_btrx_ram_Pos)
+
+#define PLATFORM_REG_BT_DRF_BIST_MODE_bist_mode_drf_bttx_ram_Pos                                             8U
+#define PLATFORM_REG_BT_DRF_BIST_MODE_bist_mode_drf_bttx_ram_Msk                                             (0x1UL << PLATFORM_REG_BT_DRF_BIST_MODE_bist_mode_drf_bttx_ram_Pos)
+
+#define PLATFORM_REG_BT_DRF_BIST_MODE_bist_mode_drf_lepa_ram_Pos                                             9U
+#define PLATFORM_REG_BT_DRF_BIST_MODE_bist_mode_drf_lepa_ram_Msk                                             (0x1UL << PLATFORM_REG_BT_DRF_BIST_MODE_bist_mode_drf_lepa_ram_Pos)
+
+#define PLATFORM_REG_BT_DRF_BIST_MODE_bist_mode_drf_lemst_ram_Pos                                            10U
+#define PLATFORM_REG_BT_DRF_BIST_MODE_bist_mode_drf_lemst_ram_Msk                                            (0x1UL << PLATFORM_REG_BT_DRF_BIST_MODE_bist_mode_drf_lemst_ram_Pos)
+
+#define PLATFORM_REG_BT_DRF_BIST_MODE_RSVD_2_Pos                                                             11U
+#define PLATFORM_REG_BT_DRF_BIST_MODE_RSVD_2_Msk                                                             (0x1UL << PLATFORM_REG_BT_DRF_BIST_MODE_RSVD_2_Pos)
+
+#define PLATFORM_REG_BT_DRF_BIST_MODE_RSVD_1_Pos                                                             12U
+#define PLATFORM_REG_BT_DRF_BIST_MODE_RSVD_1_Msk                                                             (0x1UL << PLATFORM_REG_BT_DRF_BIST_MODE_RSVD_1_Pos)
+
+#define PLATFORM_REG_BT_DRF_BIST_MODE_RSVD_Pos                                                               13U
+#define PLATFORM_REG_BT_DRF_BIST_MODE_RSVD_Msk                                                               (0x7FFFFUL << PLATFORM_REG_BT_DRF_BIST_MODE_RSVD_Pos)
+
+/* 0x00EC   0x4000_60ec
+    0       R/W     bist_test_resume_leslv_ram                          0
+    1       R/W     bist_test_resume_lecis_ram                          0
+    2       R/W     bist_test_resume_lebis_ram                          0
+    3       R/W     bist_test_resume_buffer_ram                         0
+    4       R/W     bist_test_resume_audio_ram                          0
+    5       R/W     bist_test_resume_btphy_ram                          0
+    6       R/W     bist_test_resume_ccmp_ram                           0
+    7       R/W     bist_test_resume_btrx_ram                           0
+    8       R/W     bist_test_resume_bttx_ram                           0
+    9       R/W     bist_test_resume_lepa_ram                           0
+    10      R/W     bist_test_resume_lemst_ram                          0
+    11      R       RSVD_2                                              0
+    12      R/W     RSVD_1                                              0
+    31:13   R       RSVD                                                19'h0
+ */
+typedef union _PLATFORM_REG_BT_BIST_TEST_RESUME_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t bist_test_resume_leslv_ram: 1;
+        uint32_t bist_test_resume_lecis_ram: 1;
+        uint32_t bist_test_resume_lebis_ram: 1;
+        uint32_t bist_test_resume_buffer_ram: 1;
+        uint32_t bist_test_resume_audio_ram: 1;
+        uint32_t bist_test_resume_btphy_ram: 1;
+        uint32_t bist_test_resume_ccmp_ram: 1;
+        uint32_t bist_test_resume_btrx_ram: 1;
+        uint32_t bist_test_resume_bttx_ram: 1;
+        uint32_t bist_test_resume_lepa_ram: 1;
+        uint32_t bist_test_resume_lemst_ram: 1;
+        uint32_t RSVD_2: 1;
+        uint32_t RSVD_1: 1;
+        uint32_t RSVD: 19;
+    };
+} PLATFORM_REG_BT_BIST_TEST_RESUME_TYPE;
+
+/*0x4000_60ec PLATFORM_REG_BT_BIST_TEST_RESUME*/
+#define PLATFORM_REG_BT_BIST_TEST_RESUME_bist_test_resume_leslv_ram_Pos                                      0U
+#define PLATFORM_REG_BT_BIST_TEST_RESUME_bist_test_resume_leslv_ram_Msk                                      (0x1UL << PLATFORM_REG_BT_BIST_TEST_RESUME_bist_test_resume_leslv_ram_Pos)
+
+#define PLATFORM_REG_BT_BIST_TEST_RESUME_bist_test_resume_lecis_ram_Pos                                      1U
+#define PLATFORM_REG_BT_BIST_TEST_RESUME_bist_test_resume_lecis_ram_Msk                                      (0x1UL << PLATFORM_REG_BT_BIST_TEST_RESUME_bist_test_resume_lecis_ram_Pos)
+
+#define PLATFORM_REG_BT_BIST_TEST_RESUME_bist_test_resume_lebis_ram_Pos                                      2U
+#define PLATFORM_REG_BT_BIST_TEST_RESUME_bist_test_resume_lebis_ram_Msk                                      (0x1UL << PLATFORM_REG_BT_BIST_TEST_RESUME_bist_test_resume_lebis_ram_Pos)
+
+#define PLATFORM_REG_BT_BIST_TEST_RESUME_bist_test_resume_buffer_ram_Pos                                     3U
+#define PLATFORM_REG_BT_BIST_TEST_RESUME_bist_test_resume_buffer_ram_Msk                                     (0x1UL << PLATFORM_REG_BT_BIST_TEST_RESUME_bist_test_resume_buffer_ram_Pos)
+
+#define PLATFORM_REG_BT_BIST_TEST_RESUME_bist_test_resume_audio_ram_Pos                                      4U
+#define PLATFORM_REG_BT_BIST_TEST_RESUME_bist_test_resume_audio_ram_Msk                                      (0x1UL << PLATFORM_REG_BT_BIST_TEST_RESUME_bist_test_resume_audio_ram_Pos)
+
+#define PLATFORM_REG_BT_BIST_TEST_RESUME_bist_test_resume_btphy_ram_Pos                                      5U
+#define PLATFORM_REG_BT_BIST_TEST_RESUME_bist_test_resume_btphy_ram_Msk                                      (0x1UL << PLATFORM_REG_BT_BIST_TEST_RESUME_bist_test_resume_btphy_ram_Pos)
+
+#define PLATFORM_REG_BT_BIST_TEST_RESUME_bist_test_resume_ccmp_ram_Pos                                       6U
+#define PLATFORM_REG_BT_BIST_TEST_RESUME_bist_test_resume_ccmp_ram_Msk                                       (0x1UL << PLATFORM_REG_BT_BIST_TEST_RESUME_bist_test_resume_ccmp_ram_Pos)
+
+#define PLATFORM_REG_BT_BIST_TEST_RESUME_bist_test_resume_btrx_ram_Pos                                       7U
+#define PLATFORM_REG_BT_BIST_TEST_RESUME_bist_test_resume_btrx_ram_Msk                                       (0x1UL << PLATFORM_REG_BT_BIST_TEST_RESUME_bist_test_resume_btrx_ram_Pos)
+
+#define PLATFORM_REG_BT_BIST_TEST_RESUME_bist_test_resume_bttx_ram_Pos                                       8U
+#define PLATFORM_REG_BT_BIST_TEST_RESUME_bist_test_resume_bttx_ram_Msk                                       (0x1UL << PLATFORM_REG_BT_BIST_TEST_RESUME_bist_test_resume_bttx_ram_Pos)
+
+#define PLATFORM_REG_BT_BIST_TEST_RESUME_bist_test_resume_lepa_ram_Pos                                       9U
+#define PLATFORM_REG_BT_BIST_TEST_RESUME_bist_test_resume_lepa_ram_Msk                                       (0x1UL << PLATFORM_REG_BT_BIST_TEST_RESUME_bist_test_resume_lepa_ram_Pos)
+
+#define PLATFORM_REG_BT_BIST_TEST_RESUME_bist_test_resume_lemst_ram_Pos                                      10U
+#define PLATFORM_REG_BT_BIST_TEST_RESUME_bist_test_resume_lemst_ram_Msk                                      (0x1UL << PLATFORM_REG_BT_BIST_TEST_RESUME_bist_test_resume_lemst_ram_Pos)
+
+#define PLATFORM_REG_BT_BIST_TEST_RESUME_RSVD_2_Pos                                                          11U
+#define PLATFORM_REG_BT_BIST_TEST_RESUME_RSVD_2_Msk                                                          (0x1UL << PLATFORM_REG_BT_BIST_TEST_RESUME_RSVD_2_Pos)
+
+#define PLATFORM_REG_BT_BIST_TEST_RESUME_RSVD_1_Pos                                                          12U
+#define PLATFORM_REG_BT_BIST_TEST_RESUME_RSVD_1_Msk                                                          (0x1UL << PLATFORM_REG_BT_BIST_TEST_RESUME_RSVD_1_Pos)
+
+#define PLATFORM_REG_BT_BIST_TEST_RESUME_RSVD_Pos                                                            13U
+#define PLATFORM_REG_BT_BIST_TEST_RESUME_RSVD_Msk                                                            (0x7FFFFUL << PLATFORM_REG_BT_BIST_TEST_RESUME_RSVD_Pos)
+
+/* 0x00F0   0x4000_60f0
+    0       R       bist_start_pause_leslv_ram                          0
+    1       R       bist_start_pause_lecis_ram                          0
+    2       R       bist_start_pause_lebis_ram                          0
+    3       R       bist_start_pause_buffer_ram                         0
+    4       R       bist_start_pause_audio_ram                          0
+    5       R       bist_start_pause_btphy_ram                          0
+    6       R       bist_start_pause_ccmp_ram                           0
+    7       R       bist_start_pause_btrx_ram                           0
+    8       R       bist_start_pause_bttx_ram                           0
+    9       R       bist_start_pause_lepa_ram                           0
+    10      R       bist_start_pause_lemst_ram                          0
+    11      R       RSVD_1                                              0
+    12      R       bist_start_pause_buffer_8k_ram                      0
+    31:13   R       RSVD                                                19'h0
+ */
+typedef union _PLATFORM_REG_BT_BIST_START_PAUSE_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t bist_start_pause_leslv_ram: 1;
+        uint32_t bist_start_pause_lecis_ram: 1;
+        uint32_t bist_start_pause_lebis_ram: 1;
+        uint32_t bist_start_pause_buffer_ram: 1;
+        uint32_t bist_start_pause_audio_ram: 1;
+        uint32_t bist_start_pause_btphy_ram: 1;
+        uint32_t bist_start_pause_ccmp_ram: 1;
+        uint32_t bist_start_pause_btrx_ram: 1;
+        uint32_t bist_start_pause_bttx_ram: 1;
+        uint32_t bist_start_pause_lepa_ram: 1;
+        uint32_t bist_start_pause_lemst_ram: 1;
+        uint32_t RSVD_1: 1;
+        uint32_t bist_start_pause_buffer_8k_ram: 1;
+        uint32_t RSVD: 19;
+    };
+} PLATFORM_REG_BT_BIST_START_PAUSE_TYPE;
+
+/*0x4000_60f0 PLATFORM_REG_BT_BIST_START_PAUSE*/
+#define PLATFORM_REG_BT_BIST_START_PAUSE_bist_start_pause_leslv_ram_Pos                                      0U
+#define PLATFORM_REG_BT_BIST_START_PAUSE_bist_start_pause_leslv_ram_Msk                                      (0x1UL << PLATFORM_REG_BT_BIST_START_PAUSE_bist_start_pause_leslv_ram_Pos)
+
+#define PLATFORM_REG_BT_BIST_START_PAUSE_bist_start_pause_lecis_ram_Pos                                      1U
+#define PLATFORM_REG_BT_BIST_START_PAUSE_bist_start_pause_lecis_ram_Msk                                      (0x1UL << PLATFORM_REG_BT_BIST_START_PAUSE_bist_start_pause_lecis_ram_Pos)
+
+#define PLATFORM_REG_BT_BIST_START_PAUSE_bist_start_pause_lebis_ram_Pos                                      2U
+#define PLATFORM_REG_BT_BIST_START_PAUSE_bist_start_pause_lebis_ram_Msk                                      (0x1UL << PLATFORM_REG_BT_BIST_START_PAUSE_bist_start_pause_lebis_ram_Pos)
+
+#define PLATFORM_REG_BT_BIST_START_PAUSE_bist_start_pause_buffer_ram_Pos                                     3U
+#define PLATFORM_REG_BT_BIST_START_PAUSE_bist_start_pause_buffer_ram_Msk                                     (0x1UL << PLATFORM_REG_BT_BIST_START_PAUSE_bist_start_pause_buffer_ram_Pos)
+
+#define PLATFORM_REG_BT_BIST_START_PAUSE_bist_start_pause_audio_ram_Pos                                      4U
+#define PLATFORM_REG_BT_BIST_START_PAUSE_bist_start_pause_audio_ram_Msk                                      (0x1UL << PLATFORM_REG_BT_BIST_START_PAUSE_bist_start_pause_audio_ram_Pos)
+
+#define PLATFORM_REG_BT_BIST_START_PAUSE_bist_start_pause_btphy_ram_Pos                                      5U
+#define PLATFORM_REG_BT_BIST_START_PAUSE_bist_start_pause_btphy_ram_Msk                                      (0x1UL << PLATFORM_REG_BT_BIST_START_PAUSE_bist_start_pause_btphy_ram_Pos)
+
+#define PLATFORM_REG_BT_BIST_START_PAUSE_bist_start_pause_ccmp_ram_Pos                                       6U
+#define PLATFORM_REG_BT_BIST_START_PAUSE_bist_start_pause_ccmp_ram_Msk                                       (0x1UL << PLATFORM_REG_BT_BIST_START_PAUSE_bist_start_pause_ccmp_ram_Pos)
+
+#define PLATFORM_REG_BT_BIST_START_PAUSE_bist_start_pause_btrx_ram_Pos                                       7U
+#define PLATFORM_REG_BT_BIST_START_PAUSE_bist_start_pause_btrx_ram_Msk                                       (0x1UL << PLATFORM_REG_BT_BIST_START_PAUSE_bist_start_pause_btrx_ram_Pos)
+
+#define PLATFORM_REG_BT_BIST_START_PAUSE_bist_start_pause_bttx_ram_Pos                                       8U
+#define PLATFORM_REG_BT_BIST_START_PAUSE_bist_start_pause_bttx_ram_Msk                                       (0x1UL << PLATFORM_REG_BT_BIST_START_PAUSE_bist_start_pause_bttx_ram_Pos)
+
+#define PLATFORM_REG_BT_BIST_START_PAUSE_bist_start_pause_lepa_ram_Pos                                       9U
+#define PLATFORM_REG_BT_BIST_START_PAUSE_bist_start_pause_lepa_ram_Msk                                       (0x1UL << PLATFORM_REG_BT_BIST_START_PAUSE_bist_start_pause_lepa_ram_Pos)
+
+#define PLATFORM_REG_BT_BIST_START_PAUSE_bist_start_pause_lemst_ram_Pos                                      10U
+#define PLATFORM_REG_BT_BIST_START_PAUSE_bist_start_pause_lemst_ram_Msk                                      (0x1UL << PLATFORM_REG_BT_BIST_START_PAUSE_bist_start_pause_lemst_ram_Pos)
+
+#define PLATFORM_REG_BT_BIST_START_PAUSE_RSVD_1_Pos                                                          11U
+#define PLATFORM_REG_BT_BIST_START_PAUSE_RSVD_1_Msk                                                          (0x1UL << PLATFORM_REG_BT_BIST_START_PAUSE_RSVD_1_Pos)
+
+#define PLATFORM_REG_BT_BIST_START_PAUSE_bist_start_pause_buffer_8k_ram_Pos                                  12U
+#define PLATFORM_REG_BT_BIST_START_PAUSE_bist_start_pause_buffer_8k_ram_Msk                                  (0x1UL << PLATFORM_REG_BT_BIST_START_PAUSE_bist_start_pause_buffer_8k_ram_Pos)
+
+#define PLATFORM_REG_BT_BIST_START_PAUSE_RSVD_Pos                                                            13U
+#define PLATFORM_REG_BT_BIST_START_PAUSE_RSVD_Msk                                                            (0x7FFFFUL << PLATFORM_REG_BT_BIST_START_PAUSE_RSVD_Pos)
+
+/* 0x00F4   0x4000_60f4
+    0       R       bist_done_leslv_ram                                 0
+    1       R       bist_done_lecis_ram                                 0
+    2       R       bist_done_lebis_ram                                 0
+    3       R       bist_done_buffer_ram                                0
+    4       R       bist_done_audio_ram                                 0
+    5       R       bist_done_btphy_ram                                 0
+    6       R       bist_done_ccmp_ram                                  0
+    7       R       bist_done_btrx_ram                                  0
+    8       R       bist_done_bttx_ram                                  0
+    9       R       bist_done_lepa_ram                                  0
+    10      R       bist_done_lemst_ram                                 0
+    11      R       RSVD_1                                              0
+    12      R       bist_done_buffer_8k_ram                             0
+    31:13   R       RSVD                                                19'h0
+ */
+typedef union _PLATFORM_REG_BT_BIST_DONE_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t bist_done_leslv_ram: 1;
+        uint32_t bist_done_lecis_ram: 1;
+        uint32_t bist_done_lebis_ram: 1;
+        uint32_t bist_done_buffer_ram: 1;
+        uint32_t bist_done_audio_ram: 1;
+        uint32_t bist_done_btphy_ram: 1;
+        uint32_t bist_done_ccmp_ram: 1;
+        uint32_t bist_done_btrx_ram: 1;
+        uint32_t bist_done_bttx_ram: 1;
+        uint32_t bist_done_lepa_ram: 1;
+        uint32_t bist_done_lemst_ram: 1;
+        uint32_t RSVD_1: 1;
+        uint32_t bist_done_buffer_8k_ram: 1;
+        uint32_t RSVD: 19;
+    };
+} PLATFORM_REG_BT_BIST_DONE_TYPE;
+
+/*0x4000_60f4 PLATFORM_REG_BT_BIST_DONE*/
+#define PLATFORM_REG_BT_BIST_DONE_bist_done_leslv_ram_Pos                                                    0U
+#define PLATFORM_REG_BT_BIST_DONE_bist_done_leslv_ram_Msk                                                    (0x1UL << PLATFORM_REG_BT_BIST_DONE_bist_done_leslv_ram_Pos)
+
+#define PLATFORM_REG_BT_BIST_DONE_bist_done_lecis_ram_Pos                                                    1U
+#define PLATFORM_REG_BT_BIST_DONE_bist_done_lecis_ram_Msk                                                    (0x1UL << PLATFORM_REG_BT_BIST_DONE_bist_done_lecis_ram_Pos)
+
+#define PLATFORM_REG_BT_BIST_DONE_bist_done_lebis_ram_Pos                                                    2U
+#define PLATFORM_REG_BT_BIST_DONE_bist_done_lebis_ram_Msk                                                    (0x1UL << PLATFORM_REG_BT_BIST_DONE_bist_done_lebis_ram_Pos)
+
+#define PLATFORM_REG_BT_BIST_DONE_bist_done_buffer_ram_Pos                                                   3U
+#define PLATFORM_REG_BT_BIST_DONE_bist_done_buffer_ram_Msk                                                   (0x1UL << PLATFORM_REG_BT_BIST_DONE_bist_done_buffer_ram_Pos)
+
+#define PLATFORM_REG_BT_BIST_DONE_bist_done_audio_ram_Pos                                                    4U
+#define PLATFORM_REG_BT_BIST_DONE_bist_done_audio_ram_Msk                                                    (0x1UL << PLATFORM_REG_BT_BIST_DONE_bist_done_audio_ram_Pos)
+
+#define PLATFORM_REG_BT_BIST_DONE_bist_done_btphy_ram_Pos                                                    5U
+#define PLATFORM_REG_BT_BIST_DONE_bist_done_btphy_ram_Msk                                                    (0x1UL << PLATFORM_REG_BT_BIST_DONE_bist_done_btphy_ram_Pos)
+
+#define PLATFORM_REG_BT_BIST_DONE_bist_done_ccmp_ram_Pos                                                     6U
+#define PLATFORM_REG_BT_BIST_DONE_bist_done_ccmp_ram_Msk                                                     (0x1UL << PLATFORM_REG_BT_BIST_DONE_bist_done_ccmp_ram_Pos)
+
+#define PLATFORM_REG_BT_BIST_DONE_bist_done_btrx_ram_Pos                                                     7U
+#define PLATFORM_REG_BT_BIST_DONE_bist_done_btrx_ram_Msk                                                     (0x1UL << PLATFORM_REG_BT_BIST_DONE_bist_done_btrx_ram_Pos)
+
+#define PLATFORM_REG_BT_BIST_DONE_bist_done_bttx_ram_Pos                                                     8U
+#define PLATFORM_REG_BT_BIST_DONE_bist_done_bttx_ram_Msk                                                     (0x1UL << PLATFORM_REG_BT_BIST_DONE_bist_done_bttx_ram_Pos)
+
+#define PLATFORM_REG_BT_BIST_DONE_bist_done_lepa_ram_Pos                                                     9U
+#define PLATFORM_REG_BT_BIST_DONE_bist_done_lepa_ram_Msk                                                     (0x1UL << PLATFORM_REG_BT_BIST_DONE_bist_done_lepa_ram_Pos)
+
+#define PLATFORM_REG_BT_BIST_DONE_bist_done_lemst_ram_Pos                                                    10U
+#define PLATFORM_REG_BT_BIST_DONE_bist_done_lemst_ram_Msk                                                    (0x1UL << PLATFORM_REG_BT_BIST_DONE_bist_done_lemst_ram_Pos)
+
+#define PLATFORM_REG_BT_BIST_DONE_RSVD_1_Pos                                                                 11U
+#define PLATFORM_REG_BT_BIST_DONE_RSVD_1_Msk                                                                 (0x1UL << PLATFORM_REG_BT_BIST_DONE_RSVD_1_Pos)
+
+#define PLATFORM_REG_BT_BIST_DONE_bist_done_buffer_8k_ram_Pos                                                12U
+#define PLATFORM_REG_BT_BIST_DONE_bist_done_buffer_8k_ram_Msk                                                (0x1UL << PLATFORM_REG_BT_BIST_DONE_bist_done_buffer_8k_ram_Pos)
+
+#define PLATFORM_REG_BT_BIST_DONE_RSVD_Pos                                                                   13U
+#define PLATFORM_REG_BT_BIST_DONE_RSVD_Msk                                                                   (0x7FFFFUL << PLATFORM_REG_BT_BIST_DONE_RSVD_Pos)
+
+/* 0x00F8   0x4000_60f8
+    0       R       bist_fail_leslv_ram                                 0
+    1       R       bist_fail_lecis_ram                                 0
+    2       R       bist_fail_lebis_ram                                 0
+    3       R       bist_fail_buffer_ram                                0
+    4       R       bist_fail_audio_ram                                 0
+    8:5     R       bist_fail_btphy_ram                                 4'b0000
+    11:9    R       bist_fail_ccmp_ram                                  3'b000
+    12      R       bist_fail_btrx_ram                                  0
+    13      R       bist_fail_bttx_ram                                  0
+    14      R       bist_fail_lepa_ram                                  0
+    15      R       bist_fail_lemst_ram                                 0
+    16      R       RSVD_1                                              0
+    17      R       bist_fail_buffer_8k_ram                             0
+    31:18   R       RSVD                                                14'h0
+ */
+typedef union _PLATFORM_REG_BT_BIST_FAIL_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t bist_fail_leslv_ram: 1;
+        uint32_t bist_fail_lecis_ram: 1;
+        uint32_t bist_fail_lebis_ram: 1;
+        uint32_t bist_fail_buffer_ram: 1;
+        uint32_t bist_fail_audio_ram: 1;
+        uint32_t bist_fail_btphy_ram: 4;
+        uint32_t bist_fail_ccmp_ram: 3;
+        uint32_t bist_fail_btrx_ram: 1;
+        uint32_t bist_fail_bttx_ram: 1;
+        uint32_t bist_fail_lepa_ram: 1;
+        uint32_t bist_fail_lemst_ram: 1;
+        uint32_t RSVD_1: 1;
+        uint32_t bist_fail_buffer_8k_ram: 1;
+        uint32_t RSVD: 14;
+    };
+} PLATFORM_REG_BT_BIST_FAIL_TYPE;
+
+/*0x4000_60f8 PLATFORM_REG_BT_BIST_FAIL*/
+#define PLATFORM_REG_BT_BIST_FAIL_bist_fail_leslv_ram_Pos                                                    0U
+#define PLATFORM_REG_BT_BIST_FAIL_bist_fail_leslv_ram_Msk                                                    (0x1UL << PLATFORM_REG_BT_BIST_FAIL_bist_fail_leslv_ram_Pos)
+
+#define PLATFORM_REG_BT_BIST_FAIL_bist_fail_lecis_ram_Pos                                                    1U
+#define PLATFORM_REG_BT_BIST_FAIL_bist_fail_lecis_ram_Msk                                                    (0x1UL << PLATFORM_REG_BT_BIST_FAIL_bist_fail_lecis_ram_Pos)
+
+#define PLATFORM_REG_BT_BIST_FAIL_bist_fail_lebis_ram_Pos                                                    2U
+#define PLATFORM_REG_BT_BIST_FAIL_bist_fail_lebis_ram_Msk                                                    (0x1UL << PLATFORM_REG_BT_BIST_FAIL_bist_fail_lebis_ram_Pos)
+
+#define PLATFORM_REG_BT_BIST_FAIL_bist_fail_buffer_ram_Pos                                                   3U
+#define PLATFORM_REG_BT_BIST_FAIL_bist_fail_buffer_ram_Msk                                                   (0x1UL << PLATFORM_REG_BT_BIST_FAIL_bist_fail_buffer_ram_Pos)
+
+#define PLATFORM_REG_BT_BIST_FAIL_bist_fail_audio_ram_Pos                                                    4U
+#define PLATFORM_REG_BT_BIST_FAIL_bist_fail_audio_ram_Msk                                                    (0x1UL << PLATFORM_REG_BT_BIST_FAIL_bist_fail_audio_ram_Pos)
+
+#define PLATFORM_REG_BT_BIST_FAIL_bist_fail_btphy_ram_Pos                                                    5U
+#define PLATFORM_REG_BT_BIST_FAIL_bist_fail_btphy_ram_Msk                                                    (0xFUL << PLATFORM_REG_BT_BIST_FAIL_bist_fail_btphy_ram_Pos)
+
+#define PLATFORM_REG_BT_BIST_FAIL_bist_fail_ccmp_ram_Pos                                                     9U
+#define PLATFORM_REG_BT_BIST_FAIL_bist_fail_ccmp_ram_Msk                                                     (0x7UL << PLATFORM_REG_BT_BIST_FAIL_bist_fail_ccmp_ram_Pos)
+
+#define PLATFORM_REG_BT_BIST_FAIL_bist_fail_btrx_ram_Pos                                                     12U
+#define PLATFORM_REG_BT_BIST_FAIL_bist_fail_btrx_ram_Msk                                                     (0x1UL << PLATFORM_REG_BT_BIST_FAIL_bist_fail_btrx_ram_Pos)
+
+#define PLATFORM_REG_BT_BIST_FAIL_bist_fail_bttx_ram_Pos                                                     13U
+#define PLATFORM_REG_BT_BIST_FAIL_bist_fail_bttx_ram_Msk                                                     (0x1UL << PLATFORM_REG_BT_BIST_FAIL_bist_fail_bttx_ram_Pos)
+
+#define PLATFORM_REG_BT_BIST_FAIL_bist_fail_lepa_ram_Pos                                                     14U
+#define PLATFORM_REG_BT_BIST_FAIL_bist_fail_lepa_ram_Msk                                                     (0x1UL << PLATFORM_REG_BT_BIST_FAIL_bist_fail_lepa_ram_Pos)
+
+#define PLATFORM_REG_BT_BIST_FAIL_bist_fail_lemst_ram_Pos                                                    15U
+#define PLATFORM_REG_BT_BIST_FAIL_bist_fail_lemst_ram_Msk                                                    (0x1UL << PLATFORM_REG_BT_BIST_FAIL_bist_fail_lemst_ram_Pos)
+
+#define PLATFORM_REG_BT_BIST_FAIL_RSVD_1_Pos                                                                 16U
+#define PLATFORM_REG_BT_BIST_FAIL_RSVD_1_Msk                                                                 (0x1UL << PLATFORM_REG_BT_BIST_FAIL_RSVD_1_Pos)
+
+#define PLATFORM_REG_BT_BIST_FAIL_bist_fail_buffer_8k_ram_Pos                                                17U
+#define PLATFORM_REG_BT_BIST_FAIL_bist_fail_buffer_8k_ram_Msk                                                (0x1UL << PLATFORM_REG_BT_BIST_FAIL_bist_fail_buffer_8k_ram_Pos)
+
+#define PLATFORM_REG_BT_BIST_FAIL_RSVD_Pos                                                                   18U
+#define PLATFORM_REG_BT_BIST_FAIL_RSVD_Msk                                                                   (0x3FFFUL << PLATFORM_REG_BT_BIST_FAIL_RSVD_Pos)
+
+/* 0x00FC   0x4000_60fc
+    0       R       bist_done_drf_leslv_ram                             0
+    1       R       bist_done_drf_lecis_ram                             0
+    2       R       bist_done_drf_lebis_ram                             0
+    3       R       bist_done_drf_buffer_ram                            0
+    4       R       bist_done_drf_audio_ram                             0
+    5       R       bist_done_drf_btphy_ram                             0
+    6       R       bist_done_drf_ccmp_ram                              0
+    7       R       bist_done_drf_btrx_ram                              0
+    8       R       bist_done_drf_bttx_ram                              0
+    9       R       bist_done_drf_lepa_ram                              0
+    10      R       bist_done_drf_lemst_ram                             0
+    11      R       RSVD_1                                              0
+    12      R       bist_done_drf_buffer_8k_ram                         0
+    31:13   R       RSVD                                                19'h0
+ */
+typedef union _PLATFORM_REG_BT_DRF_BIST_DONE_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t bist_done_drf_leslv_ram: 1;
+        uint32_t bist_done_drf_lecis_ram: 1;
+        uint32_t bist_done_drf_lebis_ram: 1;
+        uint32_t bist_done_drf_buffer_ram: 1;
+        uint32_t bist_done_drf_audio_ram: 1;
+        uint32_t bist_done_drf_btphy_ram: 1;
+        uint32_t bist_done_drf_ccmp_ram: 1;
+        uint32_t bist_done_drf_btrx_ram: 1;
+        uint32_t bist_done_drf_bttx_ram: 1;
+        uint32_t bist_done_drf_lepa_ram: 1;
+        uint32_t bist_done_drf_lemst_ram: 1;
+        uint32_t RSVD_1: 1;
+        uint32_t bist_done_drf_buffer_8k_ram: 1;
+        uint32_t RSVD: 19;
+    };
+} PLATFORM_REG_BT_DRF_BIST_DONE_TYPE;
+
+/*0x4000_60fc PLATFORM_REG_BT_DRF_BIST_DONE*/
+#define PLATFORM_REG_BT_DRF_BIST_DONE_bist_done_drf_leslv_ram_Pos                                            0U
+#define PLATFORM_REG_BT_DRF_BIST_DONE_bist_done_drf_leslv_ram_Msk                                            (0x1UL << PLATFORM_REG_BT_DRF_BIST_DONE_bist_done_drf_leslv_ram_Pos)
+
+#define PLATFORM_REG_BT_DRF_BIST_DONE_bist_done_drf_lecis_ram_Pos                                            1U
+#define PLATFORM_REG_BT_DRF_BIST_DONE_bist_done_drf_lecis_ram_Msk                                            (0x1UL << PLATFORM_REG_BT_DRF_BIST_DONE_bist_done_drf_lecis_ram_Pos)
+
+#define PLATFORM_REG_BT_DRF_BIST_DONE_bist_done_drf_lebis_ram_Pos                                            2U
+#define PLATFORM_REG_BT_DRF_BIST_DONE_bist_done_drf_lebis_ram_Msk                                            (0x1UL << PLATFORM_REG_BT_DRF_BIST_DONE_bist_done_drf_lebis_ram_Pos)
+
+#define PLATFORM_REG_BT_DRF_BIST_DONE_bist_done_drf_buffer_ram_Pos                                           3U
+#define PLATFORM_REG_BT_DRF_BIST_DONE_bist_done_drf_buffer_ram_Msk                                           (0x1UL << PLATFORM_REG_BT_DRF_BIST_DONE_bist_done_drf_buffer_ram_Pos)
+
+#define PLATFORM_REG_BT_DRF_BIST_DONE_bist_done_drf_audio_ram_Pos                                            4U
+#define PLATFORM_REG_BT_DRF_BIST_DONE_bist_done_drf_audio_ram_Msk                                            (0x1UL << PLATFORM_REG_BT_DRF_BIST_DONE_bist_done_drf_audio_ram_Pos)
+
+#define PLATFORM_REG_BT_DRF_BIST_DONE_bist_done_drf_btphy_ram_Pos                                            5U
+#define PLATFORM_REG_BT_DRF_BIST_DONE_bist_done_drf_btphy_ram_Msk                                            (0x1UL << PLATFORM_REG_BT_DRF_BIST_DONE_bist_done_drf_btphy_ram_Pos)
+
+#define PLATFORM_REG_BT_DRF_BIST_DONE_bist_done_drf_ccmp_ram_Pos                                             6U
+#define PLATFORM_REG_BT_DRF_BIST_DONE_bist_done_drf_ccmp_ram_Msk                                             (0x1UL << PLATFORM_REG_BT_DRF_BIST_DONE_bist_done_drf_ccmp_ram_Pos)
+
+#define PLATFORM_REG_BT_DRF_BIST_DONE_bist_done_drf_btrx_ram_Pos                                             7U
+#define PLATFORM_REG_BT_DRF_BIST_DONE_bist_done_drf_btrx_ram_Msk                                             (0x1UL << PLATFORM_REG_BT_DRF_BIST_DONE_bist_done_drf_btrx_ram_Pos)
+
+#define PLATFORM_REG_BT_DRF_BIST_DONE_bist_done_drf_bttx_ram_Pos                                             8U
+#define PLATFORM_REG_BT_DRF_BIST_DONE_bist_done_drf_bttx_ram_Msk                                             (0x1UL << PLATFORM_REG_BT_DRF_BIST_DONE_bist_done_drf_bttx_ram_Pos)
+
+#define PLATFORM_REG_BT_DRF_BIST_DONE_bist_done_drf_lepa_ram_Pos                                             9U
+#define PLATFORM_REG_BT_DRF_BIST_DONE_bist_done_drf_lepa_ram_Msk                                             (0x1UL << PLATFORM_REG_BT_DRF_BIST_DONE_bist_done_drf_lepa_ram_Pos)
+
+#define PLATFORM_REG_BT_DRF_BIST_DONE_bist_done_drf_lemst_ram_Pos                                            10U
+#define PLATFORM_REG_BT_DRF_BIST_DONE_bist_done_drf_lemst_ram_Msk                                            (0x1UL << PLATFORM_REG_BT_DRF_BIST_DONE_bist_done_drf_lemst_ram_Pos)
+
+#define PLATFORM_REG_BT_DRF_BIST_DONE_RSVD_1_Pos                                                             11U
+#define PLATFORM_REG_BT_DRF_BIST_DONE_RSVD_1_Msk                                                             (0x1UL << PLATFORM_REG_BT_DRF_BIST_DONE_RSVD_1_Pos)
+
+#define PLATFORM_REG_BT_DRF_BIST_DONE_bist_done_drf_buffer_8k_ram_Pos                                        12U
+#define PLATFORM_REG_BT_DRF_BIST_DONE_bist_done_drf_buffer_8k_ram_Msk                                        (0x1UL << PLATFORM_REG_BT_DRF_BIST_DONE_bist_done_drf_buffer_8k_ram_Pos)
+
+#define PLATFORM_REG_BT_DRF_BIST_DONE_RSVD_Pos                                                               13U
+#define PLATFORM_REG_BT_DRF_BIST_DONE_RSVD_Msk                                                               (0x7FFFFUL << PLATFORM_REG_BT_DRF_BIST_DONE_RSVD_Pos)
+
+/* 0x0100   0x4000_6100
+    0       R       bist_fail_drf_leslv_ram                             0
+    1       R       bist_fail_drf_lecis_ram                             0
+    2       R       bist_fail_drf_lebis_ram                             0
+    3       R       bist_fail_drf_buffer_ram                            0
+    4       R       bist_fail_drf_audio_ram                             0
+    8:5     R       bist_fail_drf_btphy_ram                             4'b0000
+    11:9    R       bist_fail_drf_ccmp_ram                              3'b000
+    12      R       bist_fail_drf_btrx_ram                              0
+    13      R       bist_fail_drf_bttx_ram                              0
+    14      R       bist_fail_drf_lepa_ram                              0
+    15      R       bist_fail_drf_lemst_ram                             0
+    16      R       RSVD_1                                              0
+    17      R       bist_fail_drf_buffer_8k_ram                         0
+    31:18   R       RSVD                                                14'h0
+ */
+typedef union _PLATFORM_REG_BT_DRF_BIST_FAIL_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t bist_fail_drf_leslv_ram: 1;
+        uint32_t bist_fail_drf_lecis_ram: 1;
+        uint32_t bist_fail_drf_lebis_ram: 1;
+        uint32_t bist_fail_drf_buffer_ram: 1;
+        uint32_t bist_fail_drf_audio_ram: 1;
+        uint32_t bist_fail_drf_btphy_ram: 4;
+        uint32_t bist_fail_drf_ccmp_ram: 3;
+        uint32_t bist_fail_drf_btrx_ram: 1;
+        uint32_t bist_fail_drf_bttx_ram: 1;
+        uint32_t bist_fail_drf_lepa_ram: 1;
+        uint32_t bist_fail_drf_lemst_ram: 1;
+        uint32_t RSVD_1: 1;
+        uint32_t bist_fail_drf_buffer_8k_ram: 1;
+        uint32_t RSVD: 14;
+    };
+} PLATFORM_REG_BT_DRF_BIST_FAIL_TYPE;
+
+/*0x4000_6100 PLATFORM_REG_BT_DRF_BIST_FAIL*/
+#define PLATFORM_REG_BT_DRF_BIST_FAIL_bist_fail_drf_leslv_ram_Pos                                            0U
+#define PLATFORM_REG_BT_DRF_BIST_FAIL_bist_fail_drf_leslv_ram_Msk                                            (0x1UL << PLATFORM_REG_BT_DRF_BIST_FAIL_bist_fail_drf_leslv_ram_Pos)
+
+#define PLATFORM_REG_BT_DRF_BIST_FAIL_bist_fail_drf_lecis_ram_Pos                                            1U
+#define PLATFORM_REG_BT_DRF_BIST_FAIL_bist_fail_drf_lecis_ram_Msk                                            (0x1UL << PLATFORM_REG_BT_DRF_BIST_FAIL_bist_fail_drf_lecis_ram_Pos)
+
+#define PLATFORM_REG_BT_DRF_BIST_FAIL_bist_fail_drf_lebis_ram_Pos                                            2U
+#define PLATFORM_REG_BT_DRF_BIST_FAIL_bist_fail_drf_lebis_ram_Msk                                            (0x1UL << PLATFORM_REG_BT_DRF_BIST_FAIL_bist_fail_drf_lebis_ram_Pos)
+
+#define PLATFORM_REG_BT_DRF_BIST_FAIL_bist_fail_drf_buffer_ram_Pos                                           3U
+#define PLATFORM_REG_BT_DRF_BIST_FAIL_bist_fail_drf_buffer_ram_Msk                                           (0x1UL << PLATFORM_REG_BT_DRF_BIST_FAIL_bist_fail_drf_buffer_ram_Pos)
+
+#define PLATFORM_REG_BT_DRF_BIST_FAIL_bist_fail_drf_audio_ram_Pos                                            4U
+#define PLATFORM_REG_BT_DRF_BIST_FAIL_bist_fail_drf_audio_ram_Msk                                            (0x1UL << PLATFORM_REG_BT_DRF_BIST_FAIL_bist_fail_drf_audio_ram_Pos)
+
+#define PLATFORM_REG_BT_DRF_BIST_FAIL_bist_fail_drf_btphy_ram_Pos                                            5U
+#define PLATFORM_REG_BT_DRF_BIST_FAIL_bist_fail_drf_btphy_ram_Msk                                            (0xFUL << PLATFORM_REG_BT_DRF_BIST_FAIL_bist_fail_drf_btphy_ram_Pos)
+
+#define PLATFORM_REG_BT_DRF_BIST_FAIL_bist_fail_drf_ccmp_ram_Pos                                             9U
+#define PLATFORM_REG_BT_DRF_BIST_FAIL_bist_fail_drf_ccmp_ram_Msk                                             (0x7UL << PLATFORM_REG_BT_DRF_BIST_FAIL_bist_fail_drf_ccmp_ram_Pos)
+
+#define PLATFORM_REG_BT_DRF_BIST_FAIL_bist_fail_drf_btrx_ram_Pos                                             12U
+#define PLATFORM_REG_BT_DRF_BIST_FAIL_bist_fail_drf_btrx_ram_Msk                                             (0x1UL << PLATFORM_REG_BT_DRF_BIST_FAIL_bist_fail_drf_btrx_ram_Pos)
+
+#define PLATFORM_REG_BT_DRF_BIST_FAIL_bist_fail_drf_bttx_ram_Pos                                             13U
+#define PLATFORM_REG_BT_DRF_BIST_FAIL_bist_fail_drf_bttx_ram_Msk                                             (0x1UL << PLATFORM_REG_BT_DRF_BIST_FAIL_bist_fail_drf_bttx_ram_Pos)
+
+#define PLATFORM_REG_BT_DRF_BIST_FAIL_bist_fail_drf_lepa_ram_Pos                                             14U
+#define PLATFORM_REG_BT_DRF_BIST_FAIL_bist_fail_drf_lepa_ram_Msk                                             (0x1UL << PLATFORM_REG_BT_DRF_BIST_FAIL_bist_fail_drf_lepa_ram_Pos)
+
+#define PLATFORM_REG_BT_DRF_BIST_FAIL_bist_fail_drf_lemst_ram_Pos                                            15U
+#define PLATFORM_REG_BT_DRF_BIST_FAIL_bist_fail_drf_lemst_ram_Msk                                            (0x1UL << PLATFORM_REG_BT_DRF_BIST_FAIL_bist_fail_drf_lemst_ram_Pos)
+
+#define PLATFORM_REG_BT_DRF_BIST_FAIL_RSVD_1_Pos                                                             16U
+#define PLATFORM_REG_BT_DRF_BIST_FAIL_RSVD_1_Msk                                                             (0x1UL << PLATFORM_REG_BT_DRF_BIST_FAIL_RSVD_1_Pos)
+
+#define PLATFORM_REG_BT_DRF_BIST_FAIL_bist_fail_drf_buffer_8k_ram_Pos                                        17U
+#define PLATFORM_REG_BT_DRF_BIST_FAIL_bist_fail_drf_buffer_8k_ram_Msk                                        (0x1UL << PLATFORM_REG_BT_DRF_BIST_FAIL_bist_fail_drf_buffer_8k_ram_Pos)
+
+#define PLATFORM_REG_BT_DRF_BIST_FAIL_RSVD_Pos                                                               18U
+#define PLATFORM_REG_BT_DRF_BIST_FAIL_RSVD_Msk                                                               (0x3FFFUL << PLATFORM_REG_BT_DRF_BIST_FAIL_RSVD_Pos)
+
+/* 0x0130   0x4000_6130
+    31:0    R       RSVD                                                32'h0
+ */
+typedef union _PLATFORM_Reserved_6_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RSVD;
+    };
+} PLATFORM_Reserved_6_TYPE;
+
+/*0x4000_6130 PLATFORM_Reserved_6*/
+#define PLATFORM_Reserved_6_RSVD_Pos                                                                         0U
+#define PLATFORM_Reserved_6_RSVD_Msk                                                                         (0xFFFFFFFFUL << PLATFORM_Reserved_6_RSVD_Pos)
+
+/* 0x0134   0x4000_6134
+    31:0    R       RSVD                                                32'h0
+ */
+typedef union _PLATFORM_Reserved_7_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RSVD;
+    };
+} PLATFORM_Reserved_7_TYPE;
+
+/*0x4000_6134 PLATFORM_Reserved_7*/
+#define PLATFORM_Reserved_7_RSVD_Pos                                                                         0U
+#define PLATFORM_Reserved_7_RSVD_Msk                                                                         (0xFFFFFFFFUL << PLATFORM_Reserved_7_RSVD_Pos)
+
+/* 0x01E0   0x4000_61e0
+    27:0    R/W     WDT_CNT_LIMIT                                       28'h4E200
+    29:28   R/W     WDT_MODE                                            2'h0
+    30      R/W1C   WDT_TO                                              1'h0
+    31      R/W     WDT_EN                                              1'h0
+ */
+typedef union _PLATFORM_REG_WDT_CTL_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t WDT_CNT_LIMIT: 28;
+        uint32_t WDT_MODE: 2;
+        uint32_t WDT_TO: 1;
+        uint32_t WDT_EN: 1;
+    };
+} PLATFORM_REG_WDT_CTL_TYPE;
+
+/*0x4000_61e0 PLATFORM_REG_WDT_CTL*/
+#define PLATFORM_REG_WDT_CTL_WDT_CNT_LIMIT_Pos                                                               0U
+#define PLATFORM_REG_WDT_CTL_WDT_CNT_LIMIT_Msk                                                               (0xFFFFFFFUL << PLATFORM_REG_WDT_CTL_WDT_CNT_LIMIT_Pos)
+
+#define PLATFORM_REG_WDT_CTL_WDT_MODE_Pos                                                                    28U
+#define PLATFORM_REG_WDT_CTL_WDT_MODE_Msk                                                                    (0x3UL << PLATFORM_REG_WDT_CTL_WDT_MODE_Pos)
+
+#define PLATFORM_REG_WDT_CTL_WDT_TO_Pos                                                                      30U
+#define PLATFORM_REG_WDT_CTL_WDT_TO_Msk                                                                      (0x1UL << PLATFORM_REG_WDT_CTL_WDT_TO_Pos)
+
+#define PLATFORM_REG_WDT_CTL_WDT_EN_Pos                                                                      31U
+#define PLATFORM_REG_WDT_CTL_WDT_EN_Msk                                                                      (0x1UL << PLATFORM_REG_WDT_CTL_WDT_EN_Pos)
+
+/* 0x01E4   0x4000_61e4
+    15:0    R/WAC   WDT_KICK                                            16'h0
+    31:16   R       RESERVED                                            16'h0
+ */
+typedef union _PLATFORM_REG_WDT_KICK_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t WDT_KICK: 16;
+        uint32_t RESERVED: 16;
+    };
+} PLATFORM_REG_WDT_KICK_TYPE;
+
+/*0x4000_61e4 PLATFORM_REG_WDT_KICK*/
+#define PLATFORM_REG_WDT_KICK_WDT_KICK_Pos                                                                   0U
+#define PLATFORM_REG_WDT_KICK_WDT_KICK_Msk                                                                   (0xFFFFUL << PLATFORM_REG_WDT_KICK_WDT_KICK_Pos)
+
+#define PLATFORM_REG_WDT_KICK_RESERVED_Pos                                                                   16U
+#define PLATFORM_REG_WDT_KICK_RESERVED_Msk                                                                   (0xFFFFUL << PLATFORM_REG_WDT_KICK_RESERVED_Pos)
+
+/* 0x01E8   0x4000_61e8
+    27:0    R       WDT_CURRENT                                         28'h0
+    31:28   R       RESERVED                                            4'h0
+ */
+typedef union _PLATFORM_REG_WDT_CURRENT_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t WDT_CURRENT: 28;
+        uint32_t RESERVED: 4;
+    };
+} PLATFORM_REG_WDT_CURRENT_TYPE;
+
+/*0x4000_61e8 PLATFORM_REG_WDT_CURRENT*/
+#define PLATFORM_REG_WDT_CURRENT_WDT_CURRENT_Pos                                                             0U
+#define PLATFORM_REG_WDT_CURRENT_WDT_CURRENT_Msk                                                             (0xFFFFFFFUL << PLATFORM_REG_WDT_CURRENT_WDT_CURRENT_Pos)
+
+#define PLATFORM_REG_WDT_CURRENT_RESERVED_Pos                                                                28U
+#define PLATFORM_REG_WDT_CURRENT_RESERVED_Msk                                                                (0xFUL << PLATFORM_REG_WDT_CURRENT_RESERVED_Pos)
+
+/* 0x01EC   0x4000_61ec
+    31:0    R       WDT_VER                                             32'h2409030A
+ */
+typedef union _PLATFORM_REG_WDT_VER_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t WDT_VER;
+    };
+} PLATFORM_REG_WDT_VER_TYPE;
+
+/*0x4000_61ec PLATFORM_REG_WDT_VER*/
+#define PLATFORM_REG_WDT_VER_WDT_VER_Pos                                                                     0U
+#define PLATFORM_REG_WDT_VER_WDT_VER_Msk                                                                     (0xFFFFFFFFUL << PLATFORM_REG_WDT_VER_WDT_VER_Pos)
+
+/* 0x01F0   0x4000_61f0
+    0       R/W     WDT_CLK_QACTIVE_MAN_DATA                            1'h0
+    1       R/W     WDT_CLK_QACTIVE_MAN_ENABLE                          1'h0
+    31:2    R       RESERVED                                            30'h0
+ */
+typedef union _PLATFORM_REG_WDT_CLK_QACTIVE_CTL_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t WDT_CLK_QACTIVE_MAN_DATA: 1;
+        uint32_t WDT_CLK_QACTIVE_MAN_ENABLE: 1;
+        uint32_t RESERVED: 30;
+    };
+} PLATFORM_REG_WDT_CLK_QACTIVE_CTL_TYPE;
+
+/*0x4000_61f0 PLATFORM_REG_WDT_CLK_QACTIVE_CTL*/
+#define PLATFORM_REG_WDT_CLK_QACTIVE_CTL_WDT_CLK_QACTIVE_MAN_DATA_Pos                                        0U
+#define PLATFORM_REG_WDT_CLK_QACTIVE_CTL_WDT_CLK_QACTIVE_MAN_DATA_Msk                                        (0x1UL << PLATFORM_REG_WDT_CLK_QACTIVE_CTL_WDT_CLK_QACTIVE_MAN_DATA_Pos)
+
+#define PLATFORM_REG_WDT_CLK_QACTIVE_CTL_WDT_CLK_QACTIVE_MAN_ENABLE_Pos                                      1U
+#define PLATFORM_REG_WDT_CLK_QACTIVE_CTL_WDT_CLK_QACTIVE_MAN_ENABLE_Msk                                      (0x1UL << PLATFORM_REG_WDT_CLK_QACTIVE_CTL_WDT_CLK_QACTIVE_MAN_ENABLE_Pos)
+
+#define PLATFORM_REG_WDT_CLK_QACTIVE_CTL_RESERVED_Pos                                                        2U
+#define PLATFORM_REG_WDT_CLK_QACTIVE_CTL_RESERVED_Msk                                                        (0x3FFFFFFFUL << PLATFORM_REG_WDT_CLK_QACTIVE_CTL_RESERVED_Pos)
+
+/* 0x0200   0x4000_6200
+    0       R/W     rng_srst                                            0
+    1       R/W     clk_hf_sel                                          0
+    2       R/W     corrector_bypass                                    0
+    3       R/W     cali_srst                                           0
+    4       R       RSVD_1                                              0
+    5       R/W     corrector_imode                                     0
+    10:6    R/W     dbg0_sel                                            5'h0
+    15:11   R/W     dbg1_sel                                            5'h1
+    16      R/W     lfsr_bypass_1                                       1
+    17      R/W     lfsr_mode                                           0
+    18      R/W     st_en                                               0
+    19      R/W     mode                                                0
+    31:20   R       RSVD                                                12'h0
+ */
+typedef union _PLATFORM_RNGControlRegister_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t rng_srst: 1;
+        uint32_t clk_hf_sel: 1;
+        uint32_t corrector_bypass: 1;
+        uint32_t cali_srst: 1;
+        uint32_t RSVD_1: 1;
+        uint32_t corrector_imode: 1;
+        uint32_t dbg0_sel: 5;
+        uint32_t dbg1_sel: 5;
+        uint32_t lfsr_bypass_1: 1;
+        uint32_t lfsr_mode: 1;
+        uint32_t st_en: 1;
+        uint32_t mode: 1;
+        uint32_t RSVD: 12;
+    };
+} PLATFORM_RNGControlRegister_TYPE;
+
+/*0x4000_6200 PLATFORM_RNGControlRegister*/
+#define PLATFORM_RNGControlRegister_rng_srst_Pos                                                             0U
+#define PLATFORM_RNGControlRegister_rng_srst_Msk                                                             (0x1UL << PLATFORM_RNGControlRegister_rng_srst_Pos)
+
+#define PLATFORM_RNGControlRegister_clk_hf_sel_Pos                                                           1U
+#define PLATFORM_RNGControlRegister_clk_hf_sel_Msk                                                           (0x1UL << PLATFORM_RNGControlRegister_clk_hf_sel_Pos)
+
+#define PLATFORM_RNGControlRegister_corrector_bypass_Pos                                                     2U
+#define PLATFORM_RNGControlRegister_corrector_bypass_Msk                                                     (0x1UL << PLATFORM_RNGControlRegister_corrector_bypass_Pos)
+
+#define PLATFORM_RNGControlRegister_cali_srst_Pos                                                            3U
+#define PLATFORM_RNGControlRegister_cali_srst_Msk                                                            (0x1UL << PLATFORM_RNGControlRegister_cali_srst_Pos)
+
+#define PLATFORM_RNGControlRegister_RSVD_1_Pos                                                               4U
+#define PLATFORM_RNGControlRegister_RSVD_1_Msk                                                               (0x1UL << PLATFORM_RNGControlRegister_RSVD_1_Pos)
+
+#define PLATFORM_RNGControlRegister_corrector_imode_Pos                                                      5U
+#define PLATFORM_RNGControlRegister_corrector_imode_Msk                                                      (0x1UL << PLATFORM_RNGControlRegister_corrector_imode_Pos)
+
+#define PLATFORM_RNGControlRegister_dbg0_sel_Pos                                                             6U
+#define PLATFORM_RNGControlRegister_dbg0_sel_Msk                                                             (0x1FUL << PLATFORM_RNGControlRegister_dbg0_sel_Pos)
+
+#define PLATFORM_RNGControlRegister_dbg1_sel_Pos                                                             11U
+#define PLATFORM_RNGControlRegister_dbg1_sel_Msk                                                             (0x1FUL << PLATFORM_RNGControlRegister_dbg1_sel_Pos)
+
+#define PLATFORM_RNGControlRegister_lfsr_bypass_1_Pos                                                        16U
+#define PLATFORM_RNGControlRegister_lfsr_bypass_1_Msk                                                        (0x1UL << PLATFORM_RNGControlRegister_lfsr_bypass_1_Pos)
+
+#define PLATFORM_RNGControlRegister_lfsr_mode_Pos                                                            17U
+#define PLATFORM_RNGControlRegister_lfsr_mode_Msk                                                            (0x1UL << PLATFORM_RNGControlRegister_lfsr_mode_Pos)
+
+#define PLATFORM_RNGControlRegister_st_en_Pos                                                                18U
+#define PLATFORM_RNGControlRegister_st_en_Msk                                                                (0x1UL << PLATFORM_RNGControlRegister_st_en_Pos)
+
+#define PLATFORM_RNGControlRegister_mode_Pos                                                                 19U
+#define PLATFORM_RNGControlRegister_mode_Msk                                                                 (0x1UL << PLATFORM_RNGControlRegister_mode_Pos)
+
+#define PLATFORM_RNGControlRegister_RSVD_Pos                                                                 20U
+#define PLATFORM_RNGControlRegister_RSVD_Msk                                                                 (0xFFFUL << PLATFORM_RNGControlRegister_RSVD_Pos)
+
+/* 0x0204   0x4000_6204
+    1:0     R/W     DUMMY_1                                             2'b0
+    3:2     R       RSVD_1                                              2'b0
+    15:4    R/W     DUMMY                                               12'h889
+    31:16   R       RSVD                                                16'h0
+ */
+typedef union _PLATFORM_Reserved_8_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t DUMMY_1: 2;
+        uint32_t RSVD_1: 2;
+        uint32_t DUMMY: 12;
+        uint32_t RSVD: 16;
+    };
+} PLATFORM_Reserved_8_TYPE;
+
+/*0x4000_6204 PLATFORM_Reserved_8*/
+#define PLATFORM_Reserved_8_DUMMY_1_Pos                                                                      0U
+#define PLATFORM_Reserved_8_DUMMY_1_Msk                                                                      (0x3UL << PLATFORM_Reserved_8_DUMMY_1_Pos)
+
+#define PLATFORM_Reserved_8_RSVD_1_Pos                                                                       2U
+#define PLATFORM_Reserved_8_RSVD_1_Msk                                                                       (0x3UL << PLATFORM_Reserved_8_RSVD_1_Pos)
+
+#define PLATFORM_Reserved_8_DUMMY_Pos                                                                        4U
+#define PLATFORM_Reserved_8_DUMMY_Msk                                                                        (0xFFFUL << PLATFORM_Reserved_8_DUMMY_Pos)
+
+#define PLATFORM_Reserved_8_RSVD_Pos                                                                         16U
+#define PLATFORM_Reserved_8_RSVD_Msk                                                                         (0xFFFFUL << PLATFORM_Reserved_8_RSVD_Pos)
+
+/* 0x0208   0x4000_6208
+    31:0    R/W     DUMMY                                               32'h28001a00
+ */
+typedef union _PLATFORM_Reserved_9_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t DUMMY;
+    };
+} PLATFORM_Reserved_9_TYPE;
+
+/*0x4000_6208 PLATFORM_Reserved_9*/
+#define PLATFORM_Reserved_9_DUMMY_Pos                                                                        0U
+#define PLATFORM_Reserved_9_DUMMY_Msk                                                                        (0xFFFFFFFFUL << PLATFORM_Reserved_9_DUMMY_Pos)
+
+/* 0x020C   0x4000_620c
+    8:0     R/W     DUMMY_1                                             9'h101
+    11:9    R       RSVD                                                3'h0
+    31:12   R/W     DUMMY                                               20'h10d0
+ */
+typedef union _PLATFORM_Reserved_10_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t DUMMY_1: 9;
+        uint32_t RSVD: 3;
+        uint32_t DUMMY: 20;
+    };
+} PLATFORM_Reserved_10_TYPE;
+
+/*0x4000_620c PLATFORM_Reserved_10*/
+#define PLATFORM_Reserved_10_DUMMY_1_Pos                                                                     0U
+#define PLATFORM_Reserved_10_DUMMY_1_Msk                                                                     (0x1FFUL << PLATFORM_Reserved_10_DUMMY_1_Pos)
+
+#define PLATFORM_Reserved_10_RSVD_Pos                                                                        9U
+#define PLATFORM_Reserved_10_RSVD_Msk                                                                        (0x7UL << PLATFORM_Reserved_10_RSVD_Pos)
+
+#define PLATFORM_Reserved_10_DUMMY_Pos                                                                       12U
+#define PLATFORM_Reserved_10_DUMMY_Msk                                                                       (0xFFFFFUL << PLATFORM_Reserved_10_DUMMY_Pos)
+
+/* 0x0210   0x4000_6210
+    31:0    R       RSVD                                                32'h00020000
+ */
+typedef union _PLATFORM_Reserved_11_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RSVD;
+    };
+} PLATFORM_Reserved_11_TYPE;
+
+/*0x4000_6210 PLATFORM_Reserved_11*/
+#define PLATFORM_Reserved_11_RSVD_Pos                                                                        0U
+#define PLATFORM_Reserved_11_RSVD_Msk                                                                        (0xFFFFFFFFUL << PLATFORM_Reserved_11_RSVD_Pos)
+
+/* 0x0214   0x4000_6214
+    31:0    R/W     DUMMY                                               32'h2b001800
+ */
+typedef union _PLATFORM_Reserved_12_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t DUMMY;
+    };
+} PLATFORM_Reserved_12_TYPE;
+
+/*0x4000_6214 PLATFORM_Reserved_12*/
+#define PLATFORM_Reserved_12_DUMMY_Pos                                                                       0U
+#define PLATFORM_Reserved_12_DUMMY_Msk                                                                       (0xFFFFFFFFUL << PLATFORM_Reserved_12_DUMMY_Pos)
+
+/* 0x0218   0x4000_6218
+    3:0     R/W     DUMMY_1                                             4'h8
+    15:4    R/W     RSVD_1                                              12'h0
+    19:16   R/W     DUMMY                                               4'h4
+    31:20   R/W     RSVD                                                12'h0
+ */
+typedef union _PLATFORM_Reserved_13_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t DUMMY_1: 4;
+        uint32_t RSVD_1: 12;
+        uint32_t DUMMY: 4;
+        uint32_t RSVD: 12;
+    };
+} PLATFORM_Reserved_13_TYPE;
+
+/*0x4000_6218 PLATFORM_Reserved_13*/
+#define PLATFORM_Reserved_13_DUMMY_1_Pos                                                                     0U
+#define PLATFORM_Reserved_13_DUMMY_1_Msk                                                                     (0xFUL << PLATFORM_Reserved_13_DUMMY_1_Pos)
+
+#define PLATFORM_Reserved_13_RSVD_1_Pos                                                                      4U
+#define PLATFORM_Reserved_13_RSVD_1_Msk                                                                      (0xFFFUL << PLATFORM_Reserved_13_RSVD_1_Pos)
+
+#define PLATFORM_Reserved_13_DUMMY_Pos                                                                       16U
+#define PLATFORM_Reserved_13_DUMMY_Msk                                                                       (0xFUL << PLATFORM_Reserved_13_DUMMY_Pos)
+
+#define PLATFORM_Reserved_13_RSVD_Pos                                                                        20U
+#define PLATFORM_Reserved_13_RSVD_Msk                                                                        (0xFFFUL << PLATFORM_Reserved_13_RSVD_Pos)
+
+/* 0x021C   0x4000_621c
+    0       R       out_ready                                           0
+    1       R       init_ready                                          0
+    31:2    R       RSVD                                                30'h0
+ */
+typedef union _PLATFORM_RNG_return0_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t out_ready: 1;
+        uint32_t init_ready: 1;
+        uint32_t RSVD: 30;
+    };
+} PLATFORM_RNG_return0_TYPE;
+
+/*0x4000_621c PLATFORM_RNG_return0*/
+#define PLATFORM_RNG_return0_out_ready_Pos                                                                   0U
+#define PLATFORM_RNG_return0_out_ready_Msk                                                                   (0x1UL << PLATFORM_RNG_return0_out_ready_Pos)
+
+#define PLATFORM_RNG_return0_init_ready_Pos                                                                  1U
+#define PLATFORM_RNG_return0_init_ready_Msk                                                                  (0x1UL << PLATFORM_RNG_return0_init_ready_Pos)
+
+#define PLATFORM_RNG_return0_RSVD_Pos                                                                        2U
+#define PLATFORM_RNG_return0_RSVD_Msk                                                                        (0x3FFFFFFFUL << PLATFORM_RNG_return0_RSVD_Pos)
+
+/* 0x0220   0x4000_6220
+    31:0    R       valid_bit_num                                       32'h0
+ */
+typedef union _PLATFORM_RNG_return1_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t valid_bit_num;
+    };
+} PLATFORM_RNG_return1_TYPE;
+
+/*0x4000_6220 PLATFORM_RNG_return1*/
+#define PLATFORM_RNG_return1_valid_bit_num_Pos                                                               0U
+#define PLATFORM_RNG_return1_valid_bit_num_Msk                                                               (0xFFFFFFFFUL << PLATFORM_RNG_return1_valid_bit_num_Pos)
+
+/* 0x0224   0x4000_6224
+    31:0    R       drop_num                                            32'h0
+ */
+typedef union _PLATFORM_RNG_return2_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t drop_num;
+    };
+} PLATFORM_RNG_return2_TYPE;
+
+/*0x4000_6224 PLATFORM_RNG_return2*/
+#define PLATFORM_RNG_return2_drop_num_Pos                                                                    0U
+#define PLATFORM_RNG_return2_drop_num_Msk                                                                    (0xFFFFFFFFUL << PLATFORM_RNG_return2_drop_num_Pos)
+
+/* 0x0228   0x4000_6228
+    31:0    R       random_out                                          32'h0
+ */
+typedef union _PLATFORM_RNG_result_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t random_out;
+    };
+} PLATFORM_RNG_result_TYPE;
+
+/*0x4000_6228 PLATFORM_RNG_result*/
+#define PLATFORM_RNG_result_random_out_Pos                                                                   0U
+#define PLATFORM_RNG_result_random_out_Msk                                                                   (0xFFFFFFFFUL << PLATFORM_RNG_result_random_out_Pos)
+
+/* 0x022C   0x4000_622c
+    31:0    R/W     lfsr_poly_lsb                                       32'h0
+ */
+typedef union _PLATFORM_RNG_lfsr_poly_lsb_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t lfsr_poly_lsb;
+    };
+} PLATFORM_RNG_lfsr_poly_lsb_TYPE;
+
+/*0x4000_622c PLATFORM_RNG_lfsr_poly_lsb*/
+#define PLATFORM_RNG_lfsr_poly_lsb_lfsr_poly_lsb_Pos                                                         0U
+#define PLATFORM_RNG_lfsr_poly_lsb_lfsr_poly_lsb_Msk                                                         (0xFFFFFFFFUL << PLATFORM_RNG_lfsr_poly_lsb_lfsr_poly_lsb_Pos)
+
+/* 0x0230   0x4000_6230
+    31:0    R/W     lfsr_poly_msb                                       32'h0
+ */
+typedef union _PLATFORM_RNG_lfsr_poly_msb_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t lfsr_poly_msb;
+    };
+} PLATFORM_RNG_lfsr_poly_msb_TYPE;
+
+/*0x4000_6230 PLATFORM_RNG_lfsr_poly_msb*/
+#define PLATFORM_RNG_lfsr_poly_msb_lfsr_poly_msb_Pos                                                         0U
+#define PLATFORM_RNG_lfsr_poly_msb_lfsr_poly_msb_Msk                                                         (0xFFFFFFFFUL << PLATFORM_RNG_lfsr_poly_msb_lfsr_poly_msb_Pos)
+
+/* 0x0234   0x4000_6234
+    31:0    R/W     DUMMY                                               32'hffff0000
+ */
+typedef union _PLATFORM_Reserved_14_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t DUMMY;
+    };
+} PLATFORM_Reserved_14_TYPE;
+
+/*0x4000_6234 PLATFORM_Reserved_14*/
+#define PLATFORM_Reserved_14_DUMMY_Pos                                                                       0U
+#define PLATFORM_Reserved_14_DUMMY_Msk                                                                       (0xFFFFFFFFUL << PLATFORM_Reserved_14_DUMMY_Pos)
+
+/* 0x0238   0x4000_6238
+    0       R/W     gating_en                                           1
+    31:1    R       RSVD                                                31'h0
+ */
+typedef union _PLATFORM_RNG_POWER_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t gating_en: 1;
+        uint32_t RSVD: 31;
+    };
+} PLATFORM_RNG_POWER_TYPE;
+
+/*0x4000_6238 PLATFORM_RNG_POWER*/
+#define PLATFORM_RNG_POWER_gating_en_Pos                                                                     0U
+#define PLATFORM_RNG_POWER_gating_en_Msk                                                                     (0x1UL << PLATFORM_RNG_POWER_gating_en_Pos)
+
+#define PLATFORM_RNG_POWER_RSVD_Pos                                                                          1U
+#define PLATFORM_RNG_POWER_RSVD_Msk                                                                          (0x7FFFFFFFUL << PLATFORM_RNG_POWER_RSVD_Pos)
+
+/* 0x023C   0x4000_623c
+    7:0     R/W     thr_done_rep                                        8'h0
+    15:8    R/W     thr_err_rep                                         8'h5
+    17:16   R/W     window_size_adap2                                   2'b1
+    19:18   R/W     window_size_adap1                                   2'b1
+    20      R/W     compare_unit_adap2                                  0
+    21      R/W     compare_unit_adap1                                  0
+    22      R/W     compare_unit_rep                                    1
+    23      R       RSVD                                                0
+    27:24   R/W     thr_done_adap2                                      4'h4
+    31:28   R/W     thr_done_adap1                                      4'h4
+ */
+typedef union _PLATFORM_RNG_st_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t thr_done_rep: 8;
+        uint32_t thr_err_rep: 8;
+        uint32_t window_size_adap2: 2;
+        uint32_t window_size_adap1: 2;
+        uint32_t compare_unit_adap2: 1;
+        uint32_t compare_unit_adap1: 1;
+        uint32_t compare_unit_rep: 1;
+        uint32_t RSVD: 1;
+        uint32_t thr_done_adap2: 4;
+        uint32_t thr_done_adap1: 4;
+    };
+} PLATFORM_RNG_st_TYPE;
+
+/*0x4000_623c PLATFORM_RNG_st*/
+#define PLATFORM_RNG_st_thr_done_rep_Pos                                                                     0U
+#define PLATFORM_RNG_st_thr_done_rep_Msk                                                                     (0xFFUL << PLATFORM_RNG_st_thr_done_rep_Pos)
+
+#define PLATFORM_RNG_st_thr_err_rep_Pos                                                                      8U
+#define PLATFORM_RNG_st_thr_err_rep_Msk                                                                      (0xFFUL << PLATFORM_RNG_st_thr_err_rep_Pos)
+
+#define PLATFORM_RNG_st_window_size_adap2_Pos                                                                16U
+#define PLATFORM_RNG_st_window_size_adap2_Msk                                                                (0x3UL << PLATFORM_RNG_st_window_size_adap2_Pos)
+
+#define PLATFORM_RNG_st_window_size_adap1_Pos                                                                18U
+#define PLATFORM_RNG_st_window_size_adap1_Msk                                                                (0x3UL << PLATFORM_RNG_st_window_size_adap1_Pos)
+
+#define PLATFORM_RNG_st_compare_unit_adap2_Pos                                                               20U
+#define PLATFORM_RNG_st_compare_unit_adap2_Msk                                                               (0x1UL << PLATFORM_RNG_st_compare_unit_adap2_Pos)
+
+#define PLATFORM_RNG_st_compare_unit_adap1_Pos                                                               21U
+#define PLATFORM_RNG_st_compare_unit_adap1_Msk                                                               (0x1UL << PLATFORM_RNG_st_compare_unit_adap1_Pos)
+
+#define PLATFORM_RNG_st_compare_unit_rep_Pos                                                                 22U
+#define PLATFORM_RNG_st_compare_unit_rep_Msk                                                                 (0x1UL << PLATFORM_RNG_st_compare_unit_rep_Pos)
+
+#define PLATFORM_RNG_st_RSVD_Pos                                                                             23U
+#define PLATFORM_RNG_st_RSVD_Msk                                                                             (0x1UL << PLATFORM_RNG_st_RSVD_Pos)
+
+#define PLATFORM_RNG_st_thr_done_adap2_Pos                                                                   24U
+#define PLATFORM_RNG_st_thr_done_adap2_Msk                                                                   (0xFUL << PLATFORM_RNG_st_thr_done_adap2_Pos)
+
+#define PLATFORM_RNG_st_thr_done_adap1_Pos                                                                   28U
+#define PLATFORM_RNG_st_thr_done_adap1_Msk                                                                   (0xFUL << PLATFORM_RNG_st_thr_done_adap1_Pos)
+
+/* 0x0240   0x4000_6240
+    0       R/W     err_adap2                                           0
+    1       R/W     err_adap1                                           0
+    2       R/W     err_rep                                             0
+    3       R/W     err                                                 0
+    4       R       done_adap2                                          0
+    5       R       done_adap1                                          0
+    6       R       done_rep                                            0
+    7       R       done                                                0
+    31:8    R       RSVD                                                24'h0
+ */
+typedef union _PLATFORM_RNG_st_return_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t err_adap2: 1;
+        uint32_t err_adap1: 1;
+        uint32_t err_rep: 1;
+        uint32_t err: 1;
+        uint32_t done_adap2: 1;
+        uint32_t done_adap1: 1;
+        uint32_t done_rep: 1;
+        uint32_t done: 1;
+        uint32_t RSVD: 24;
+    };
+} PLATFORM_RNG_st_return_TYPE;
+
+/*0x4000_6240 PLATFORM_RNG_st_return*/
+#define PLATFORM_RNG_st_return_err_adap2_Pos                                                                 0U
+#define PLATFORM_RNG_st_return_err_adap2_Msk                                                                 (0x1UL << PLATFORM_RNG_st_return_err_adap2_Pos)
+
+#define PLATFORM_RNG_st_return_err_adap1_Pos                                                                 1U
+#define PLATFORM_RNG_st_return_err_adap1_Msk                                                                 (0x1UL << PLATFORM_RNG_st_return_err_adap1_Pos)
+
+#define PLATFORM_RNG_st_return_err_rep_Pos                                                                   2U
+#define PLATFORM_RNG_st_return_err_rep_Msk                                                                   (0x1UL << PLATFORM_RNG_st_return_err_rep_Pos)
+
+#define PLATFORM_RNG_st_return_err_Pos                                                                       3U
+#define PLATFORM_RNG_st_return_err_Msk                                                                       (0x1UL << PLATFORM_RNG_st_return_err_Pos)
+
+#define PLATFORM_RNG_st_return_done_adap2_Pos                                                                4U
+#define PLATFORM_RNG_st_return_done_adap2_Msk                                                                (0x1UL << PLATFORM_RNG_st_return_done_adap2_Pos)
+
+#define PLATFORM_RNG_st_return_done_adap1_Pos                                                                5U
+#define PLATFORM_RNG_st_return_done_adap1_Msk                                                                (0x1UL << PLATFORM_RNG_st_return_done_adap1_Pos)
+
+#define PLATFORM_RNG_st_return_done_rep_Pos                                                                  6U
+#define PLATFORM_RNG_st_return_done_rep_Msk                                                                  (0x1UL << PLATFORM_RNG_st_return_done_rep_Pos)
+
+#define PLATFORM_RNG_st_return_done_Pos                                                                      7U
+#define PLATFORM_RNG_st_return_done_Msk                                                                      (0x1UL << PLATFORM_RNG_st_return_done_Pos)
+
+#define PLATFORM_RNG_st_return_RSVD_Pos                                                                      8U
+#define PLATFORM_RNG_st_return_RSVD_Msk                                                                      (0xFFFFFFUL << PLATFORM_RNG_st_return_RSVD_Pos)
+
+/* 0x0244   0x4000_6244
+    31:0    R       RSVD                                                32'h0
+ */
+typedef union _PLATFORM_Reserved_15_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RSVD;
+    };
+} PLATFORM_Reserved_15_TYPE;
+
+/*0x4000_6244 PLATFORM_Reserved_15*/
+#define PLATFORM_Reserved_15_RSVD_Pos                                                                        0U
+#define PLATFORM_Reserved_15_RSVD_Msk                                                                        (0xFFFFFFFFUL << PLATFORM_Reserved_15_RSVD_Pos)
+
+/* 0x0248   0x4000_6248
+    31:0    R       RSVD                                                32'h0
+ */
+typedef union _PLATFORM_Reserved_16_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RSVD;
+    };
+} PLATFORM_Reserved_16_TYPE;
+
+/*0x4000_6248 PLATFORM_Reserved_16*/
+#define PLATFORM_Reserved_16_RSVD_Pos                                                                        0U
+#define PLATFORM_Reserved_16_RSVD_Msk                                                                        (0xFFFFFFFFUL << PLATFORM_Reserved_16_RSVD_Pos)
+
+/* 0x024C   0x4000_624c
+    31:0    R       RSVD                                                32'h0
+ */
+typedef union _PLATFORM_Reserved_17_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RSVD;
+    };
+} PLATFORM_Reserved_17_TYPE;
+
+/*0x4000_624c PLATFORM_Reserved_17*/
+#define PLATFORM_Reserved_17_RSVD_Pos                                                                        0U
+#define PLATFORM_Reserved_17_RSVD_Msk                                                                        (0xFFFFFFFFUL << PLATFORM_Reserved_17_RSVD_Pos)
+
+/* 0x0250   0x4000_6250
+    31:0    R       RSVD                                                32'h0
+ */
+typedef union _PLATFORM_Reserved_18_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RSVD;
+    };
+} PLATFORM_Reserved_18_TYPE;
+
+/*0x4000_6250 PLATFORM_Reserved_18*/
+#define PLATFORM_Reserved_18_RSVD_Pos                                                                        0U
+#define PLATFORM_Reserved_18_RSVD_Msk                                                                        (0xFFFFFFFFUL << PLATFORM_Reserved_18_RSVD_Pos)
+
+/* 0x0254   0x4000_6254
+    0       W       write_data                                          0
+    1       R/W1S   otp                                                 0
+    2       R/W1S   parity                                              0
+    3       R/W1S   st_err                                              0
+    31:4    R       RSVD                                                28'h0
+ */
+typedef union _PLATFORM_RNGinterrupt_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t write_data: 1;
+        uint32_t otp: 1;
+        uint32_t parity: 1;
+        uint32_t st_err: 1;
+        uint32_t RSVD: 28;
+    };
+} PLATFORM_RNGinterrupt_TYPE;
+
+/*0x4000_6254 PLATFORM_RNGinterrupt*/
+#define PLATFORM_RNGinterrupt_write_data_Pos                                                                 0U
+#define PLATFORM_RNGinterrupt_write_data_Msk                                                                 (0x1UL << PLATFORM_RNGinterrupt_write_data_Pos)
+
+#define PLATFORM_RNGinterrupt_otp_Pos                                                                        1U
+#define PLATFORM_RNGinterrupt_otp_Msk                                                                        (0x1UL << PLATFORM_RNGinterrupt_otp_Pos)
+
+#define PLATFORM_RNGinterrupt_parity_Pos                                                                     2U
+#define PLATFORM_RNGinterrupt_parity_Msk                                                                     (0x1UL << PLATFORM_RNGinterrupt_parity_Pos)
+
+#define PLATFORM_RNGinterrupt_st_err_Pos                                                                     3U
+#define PLATFORM_RNGinterrupt_st_err_Msk                                                                     (0x1UL << PLATFORM_RNGinterrupt_st_err_Pos)
+
+#define PLATFORM_RNGinterrupt_RSVD_Pos                                                                       4U
+#define PLATFORM_RNGinterrupt_RSVD_Msk                                                                       (0xFFFFFFFUL << PLATFORM_RNGinterrupt_RSVD_Pos)
+
+/* 0x0258   0x4000_6258
+    31:0    R       RSVD                                                32'h0
+ */
+typedef union _PLATFORM_Reserved_19_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RSVD;
+    };
+} PLATFORM_Reserved_19_TYPE;
+
+/*0x4000_6258 PLATFORM_Reserved_19*/
+#define PLATFORM_Reserved_19_RSVD_Pos                                                                        0U
+#define PLATFORM_Reserved_19_RSVD_Msk                                                                        (0xFFFFFFFFUL << PLATFORM_Reserved_19_RSVD_Pos)
+
+/* 0x025C   0x4000_625c
+    31:0    R       RSVD                                                32'h0
+ */
+typedef union _PLATFORM_Reserved_20_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RSVD;
+    };
+} PLATFORM_Reserved_20_TYPE;
+
+/*0x4000_625c PLATFORM_Reserved_20*/
+#define PLATFORM_Reserved_20_RSVD_Pos                                                                        0U
+#define PLATFORM_Reserved_20_RSVD_Msk                                                                        (0xFFFFFFFFUL << PLATFORM_Reserved_20_RSVD_Pos)
+
+/* 0x0260   0x4000_6260
+    15:0    R/W     adap2                                               16'h270
+    31:16   R/W     adap1                                               16'h270
+ */
+typedef union _PLATFORM_RNG_st_thr_err_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t adap2: 16;
+        uint32_t adap1: 16;
+    };
+} PLATFORM_RNG_st_thr_err_TYPE;
+
+/*0x4000_6260 PLATFORM_RNG_st_thr_err*/
+#define PLATFORM_RNG_st_thr_err_adap2_Pos                                                                    0U
+#define PLATFORM_RNG_st_thr_err_adap2_Msk                                                                    (0xFFFFUL << PLATFORM_RNG_st_thr_err_adap2_Pos)
+
+#define PLATFORM_RNG_st_thr_err_adap1_Pos                                                                    16U
+#define PLATFORM_RNG_st_thr_err_adap1_Msk                                                                    (0xFFFFUL << PLATFORM_RNG_st_thr_err_adap1_Pos)
+
+/* 0x0264   0x4000_6264
+    0       W       write_data                                          0
+    1       R/W     otp                                                 0
+    2       R/W     parity                                              0
+    3       R/W     st_err                                              0
+    31:4    R       RSVD                                                28'h0
+ */
+typedef union _PLATFORM_RNGinterruptenable_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t write_data: 1;
+        uint32_t otp: 1;
+        uint32_t parity: 1;
+        uint32_t st_err: 1;
+        uint32_t RSVD: 28;
+    };
+} PLATFORM_RNGinterruptenable_TYPE;
+
+/*0x4000_6264 PLATFORM_RNGinterruptenable*/
+#define PLATFORM_RNGinterruptenable_write_data_Pos                                                           0U
+#define PLATFORM_RNGinterruptenable_write_data_Msk                                                           (0x1UL << PLATFORM_RNGinterruptenable_write_data_Pos)
+
+#define PLATFORM_RNGinterruptenable_otp_Pos                                                                  1U
+#define PLATFORM_RNGinterruptenable_otp_Msk                                                                  (0x1UL << PLATFORM_RNGinterruptenable_otp_Pos)
+
+#define PLATFORM_RNGinterruptenable_parity_Pos                                                               2U
+#define PLATFORM_RNGinterruptenable_parity_Msk                                                               (0x1UL << PLATFORM_RNGinterruptenable_parity_Pos)
+
+#define PLATFORM_RNGinterruptenable_st_err_Pos                                                               3U
+#define PLATFORM_RNGinterruptenable_st_err_Msk                                                               (0x1UL << PLATFORM_RNGinterruptenable_st_err_Pos)
+
+#define PLATFORM_RNGinterruptenable_RSVD_Pos                                                                 4U
+#define PLATFORM_RNGinterruptenable_RSVD_Msk                                                                 (0xFFFFFFFUL << PLATFORM_RNGinterruptenable_RSVD_Pos)
+
+/* 0x02cc   0x4000_62cc
+    31:0    R/W     spic0_pgm_fifo_init_0                               32'h0
+ */
+typedef union _PLATFORM_SPIC0PGMfifointerrtup0_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t spic0_pgm_fifo_init_0;
+    };
+} PLATFORM_SPIC0PGMfifointerrtup0_TYPE;
+
+/*0x4000_62cc PLATFORM_SPIC0PGMfifointerrtup0*/
+#define PLATFORM_SPIC0PGMfifointerrtup0_spic0_pgm_fifo_init_0_Pos                                            0U
+#define PLATFORM_SPIC0PGMfifointerrtup0_spic0_pgm_fifo_init_0_Msk                                            (0xFFFFFFFFUL << PLATFORM_SPIC0PGMfifointerrtup0_spic0_pgm_fifo_init_0_Pos)
+
+/* 0x02d0   0x4000_62d0
+    31:0    R/W     spic0_pgm_fifo_init_1                               32'h0
+ */
+typedef union _PLATFORM_SPIC0PGMfifointerrtup1_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t spic0_pgm_fifo_init_1;
+    };
+} PLATFORM_SPIC0PGMfifointerrtup1_TYPE;
+
+/*0x4000_62d0 PLATFORM_SPIC0PGMfifointerrtup1*/
+#define PLATFORM_SPIC0PGMfifointerrtup1_spic0_pgm_fifo_init_1_Pos                                            0U
+#define PLATFORM_SPIC0PGMfifointerrtup1_spic0_pgm_fifo_init_1_Msk                                            (0xFFFFFFFFUL << PLATFORM_SPIC0PGMfifointerrtup1_spic0_pgm_fifo_init_1_Pos)
+
+/* 0x02d4   0x4000_62d4
+    31:0    R/W     spic0_pgm_fifo_init_2                               32'h0
+ */
+typedef union _PLATFORM_SPIC0PGMfifointerrtup2_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t spic0_pgm_fifo_init_2;
+    };
+} PLATFORM_SPIC0PGMfifointerrtup2_TYPE;
+
+/*0x4000_62d4 PLATFORM_SPIC0PGMfifointerrtup2*/
+#define PLATFORM_SPIC0PGMfifointerrtup2_spic0_pgm_fifo_init_2_Pos                                            0U
+#define PLATFORM_SPIC0PGMfifointerrtup2_spic0_pgm_fifo_init_2_Msk                                            (0xFFFFFFFFUL << PLATFORM_SPIC0PGMfifointerrtup2_spic0_pgm_fifo_init_2_Pos)
+
+/* 0x02d8   0x4000_62d8
+    31:0    R/W     spic0_pgm_fifo_init_3                               32'h0
+ */
+typedef union _PLATFORM_SPIC0PGMfifointerrtup3_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t spic0_pgm_fifo_init_3;
+    };
+} PLATFORM_SPIC0PGMfifointerrtup3_TYPE;
+
+/*0x4000_62d8 PLATFORM_SPIC0PGMfifointerrtup3*/
+#define PLATFORM_SPIC0PGMfifointerrtup3_spic0_pgm_fifo_init_3_Pos                                            0U
+#define PLATFORM_SPIC0PGMfifointerrtup3_spic0_pgm_fifo_init_3_Msk                                            (0xFFFFFFFFUL << PLATFORM_SPIC0PGMfifointerrtup3_spic0_pgm_fifo_init_3_Pos)
+
+/* 0x02dc   0x4000_62dc
+    31:0    R/W     spic0_pgm_fifo_init_4                               32'h0
+ */
+typedef union _PLATFORM_SPIC0PGMfifointerrtup4_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t spic0_pgm_fifo_init_4;
+    };
+} PLATFORM_SPIC0PGMfifointerrtup4_TYPE;
+
+/*0x4000_62dc PLATFORM_SPIC0PGMfifointerrtup4*/
+#define PLATFORM_SPIC0PGMfifointerrtup4_spic0_pgm_fifo_init_4_Pos                                            0U
+#define PLATFORM_SPIC0PGMfifointerrtup4_spic0_pgm_fifo_init_4_Msk                                            (0xFFFFFFFFUL << PLATFORM_SPIC0PGMfifointerrtup4_spic0_pgm_fifo_init_4_Pos)
+
+/* 0x02e0   0x4000_62e0
+    31:0    R/W     spic0_pgm_fifo_init_5                               32'h0
+ */
+typedef union _PLATFORM_SPIC0PGMfifointerrtup5_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t spic0_pgm_fifo_init_5;
+    };
+} PLATFORM_SPIC0PGMfifointerrtup5_TYPE;
+
+/*0x4000_62e0 PLATFORM_SPIC0PGMfifointerrtup5*/
+#define PLATFORM_SPIC0PGMfifointerrtup5_spic0_pgm_fifo_init_5_Pos                                            0U
+#define PLATFORM_SPIC0PGMfifointerrtup5_spic0_pgm_fifo_init_5_Msk                                            (0xFFFFFFFFUL << PLATFORM_SPIC0PGMfifointerrtup5_spic0_pgm_fifo_init_5_Pos)
+
+/* 0x02e4   0x4000_62e4
+    31:0    R/W     spic0_pgm_fifo_init_6                               32'h0
+ */
+typedef union _PLATFORM_SPIC0PGMfifointerrtup6_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t spic0_pgm_fifo_init_6;
+    };
+} PLATFORM_SPIC0PGMfifointerrtup6_TYPE;
+
+/*0x4000_62e4 PLATFORM_SPIC0PGMfifointerrtup6*/
+#define PLATFORM_SPIC0PGMfifointerrtup6_spic0_pgm_fifo_init_6_Pos                                            0U
+#define PLATFORM_SPIC0PGMfifointerrtup6_spic0_pgm_fifo_init_6_Msk                                            (0xFFFFFFFFUL << PLATFORM_SPIC0PGMfifointerrtup6_spic0_pgm_fifo_init_6_Pos)
+
+/* 0x02e8   0x4000_62e8
+    31:0    R/W     spic0_pgm_fifo_init_7                               32'h0
+ */
+typedef union _PLATFORM_SPIC0PGMfifointerrtup7_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t spic0_pgm_fifo_init_7;
+    };
+} PLATFORM_SPIC0PGMfifointerrtup7_TYPE;
+
+/*0x4000_62e8 PLATFORM_SPIC0PGMfifointerrtup7*/
+#define PLATFORM_SPIC0PGMfifointerrtup7_spic0_pgm_fifo_init_7_Pos                                            0U
+#define PLATFORM_SPIC0PGMfifointerrtup7_spic0_pgm_fifo_init_7_Msk                                            (0xFFFFFFFFUL << PLATFORM_SPIC0PGMfifointerrtup7_spic0_pgm_fifo_init_7_Pos)
+
+/* 0x02ec   0x4000_62ec
+    0       R/W1C   r_ENHTIMER_EVNT_ACTIVE_sts                          1'b0
+    1       R/W1C   r_ENHTIMER_EVNT_LCH_CNT0_FIFO_FULL_sts              1'b0
+    2       R/W1C   r_ENHTIMER_EVNT_LCH_CNT0_FIFO_MET_TH_sts            1'b0
+    3       R/W1C   r_ENHTIMER_EVNT_STOP_sts                            1'b0
+    4       R/W1C   r_ENHTIMER_EVNT_TIMEOUT_sts                         1'b0
+    15:5    R       reserved_1                                          11'h0000
+    16      R/W1C   r_ENHTIMER_TASK_DISABLE_sts                         1'b0
+    17      R/W1C   r_ENHTIMER_TASK_PAUSE_sts                           1'b0
+    18      R/W1C   r_ENHTIMER_TASK_START_sts                           1'b0
+    31:19   R       reserved                                            13'h0000
+ */
+typedef union _PLATFORM_REG_ENHTIMER_TASK_EVNT_STS_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t r_ENHTIMER_EVNT_ACTIVE_sts: 1;
+        uint32_t r_ENHTIMER_EVNT_LCH_CNT0_FIFO_FULL_sts: 1;
+        uint32_t r_ENHTIMER_EVNT_LCH_CNT0_FIFO_MET_TH_sts: 1;
+        uint32_t r_ENHTIMER_EVNT_STOP_sts: 1;
+        uint32_t r_ENHTIMER_EVNT_TIMEOUT_sts: 1;
+        uint32_t reserved_1: 11;
+        uint32_t r_ENHTIMER_TASK_DISABLE_sts: 1;
+        uint32_t r_ENHTIMER_TASK_PAUSE_sts: 1;
+        uint32_t r_ENHTIMER_TASK_START_sts: 1;
+        uint32_t reserved: 13;
+    };
+} PLATFORM_REG_ENHTIMER_TASK_EVNT_STS_TYPE;
+
+/*0x4000_62ec PLATFORM_REG_ENHTIMER_TASK_EVNT_STS*/
+#define PLATFORM_REG_ENHTIMER_TASK_EVNT_STS_r_ENHTIMER_EVNT_ACTIVE_sts_Pos                                   0U
+#define PLATFORM_REG_ENHTIMER_TASK_EVNT_STS_r_ENHTIMER_EVNT_ACTIVE_sts_Msk                                   (0x1UL << PLATFORM_REG_ENHTIMER_TASK_EVNT_STS_r_ENHTIMER_EVNT_ACTIVE_sts_Pos)
+
+#define PLATFORM_REG_ENHTIMER_TASK_EVNT_STS_r_ENHTIMER_EVNT_LCH_CNT0_FIFO_FULL_sts_Pos                       1U
+#define PLATFORM_REG_ENHTIMER_TASK_EVNT_STS_r_ENHTIMER_EVNT_LCH_CNT0_FIFO_FULL_sts_Msk                       (0x1UL << PLATFORM_REG_ENHTIMER_TASK_EVNT_STS_r_ENHTIMER_EVNT_LCH_CNT0_FIFO_FULL_sts_Pos)
+
+#define PLATFORM_REG_ENHTIMER_TASK_EVNT_STS_r_ENHTIMER_EVNT_LCH_CNT0_FIFO_MET_TH_sts_Pos                     2U
+#define PLATFORM_REG_ENHTIMER_TASK_EVNT_STS_r_ENHTIMER_EVNT_LCH_CNT0_FIFO_MET_TH_sts_Msk                     (0x1UL << PLATFORM_REG_ENHTIMER_TASK_EVNT_STS_r_ENHTIMER_EVNT_LCH_CNT0_FIFO_MET_TH_sts_Pos)
+
+#define PLATFORM_REG_ENHTIMER_TASK_EVNT_STS_r_ENHTIMER_EVNT_STOP_sts_Pos                                     3U
+#define PLATFORM_REG_ENHTIMER_TASK_EVNT_STS_r_ENHTIMER_EVNT_STOP_sts_Msk                                     (0x1UL << PLATFORM_REG_ENHTIMER_TASK_EVNT_STS_r_ENHTIMER_EVNT_STOP_sts_Pos)
+
+#define PLATFORM_REG_ENHTIMER_TASK_EVNT_STS_r_ENHTIMER_EVNT_TIMEOUT_sts_Pos                                  4U
+#define PLATFORM_REG_ENHTIMER_TASK_EVNT_STS_r_ENHTIMER_EVNT_TIMEOUT_sts_Msk                                  (0x1UL << PLATFORM_REG_ENHTIMER_TASK_EVNT_STS_r_ENHTIMER_EVNT_TIMEOUT_sts_Pos)
+
+#define PLATFORM_REG_ENHTIMER_TASK_EVNT_STS_reserved_1_Pos                                                   5U
+#define PLATFORM_REG_ENHTIMER_TASK_EVNT_STS_reserved_1_Msk                                                   (0x7FFUL << PLATFORM_REG_ENHTIMER_TASK_EVNT_STS_reserved_1_Pos)
+
+#define PLATFORM_REG_ENHTIMER_TASK_EVNT_STS_r_ENHTIMER_TASK_DISABLE_sts_Pos                                  16U
+#define PLATFORM_REG_ENHTIMER_TASK_EVNT_STS_r_ENHTIMER_TASK_DISABLE_sts_Msk                                  (0x1UL << PLATFORM_REG_ENHTIMER_TASK_EVNT_STS_r_ENHTIMER_TASK_DISABLE_sts_Pos)
+
+#define PLATFORM_REG_ENHTIMER_TASK_EVNT_STS_r_ENHTIMER_TASK_PAUSE_sts_Pos                                    17U
+#define PLATFORM_REG_ENHTIMER_TASK_EVNT_STS_r_ENHTIMER_TASK_PAUSE_sts_Msk                                    (0x1UL << PLATFORM_REG_ENHTIMER_TASK_EVNT_STS_r_ENHTIMER_TASK_PAUSE_sts_Pos)
+
+#define PLATFORM_REG_ENHTIMER_TASK_EVNT_STS_r_ENHTIMER_TASK_START_sts_Pos                                    18U
+#define PLATFORM_REG_ENHTIMER_TASK_EVNT_STS_r_ENHTIMER_TASK_START_sts_Msk                                    (0x1UL << PLATFORM_REG_ENHTIMER_TASK_EVNT_STS_r_ENHTIMER_TASK_START_sts_Pos)
+
+#define PLATFORM_REG_ENHTIMER_TASK_EVNT_STS_reserved_Pos                                                     19U
+#define PLATFORM_REG_ENHTIMER_TASK_EVNT_STS_reserved_Msk                                                     (0x1FFFUL << PLATFORM_REG_ENHTIMER_TASK_EVNT_STS_reserved_Pos)
+
+/* 0x02f0   0x4000_62f0
+    0       R/W1C   r_KEYSCAN_EVNT_MANUAL_DONE_sts                      1'b0
+    15:1    R       reserved_1                                          15'h0000
+    16      R/W1C   r_KEYSCAN_TASK_MANUAL_sts                           1'b0
+    31:17   R       reserved                                            15'h0000
+ */
+typedef union _PLATFORM_REG_KEYSCAN_TASK_EVNT_STS_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t r_KEYSCAN_EVNT_MANUAL_DONE_sts: 1;
+        uint32_t reserved_1: 15;
+        uint32_t r_KEYSCAN_TASK_MANUAL_sts: 1;
+        uint32_t reserved: 15;
+    };
+} PLATFORM_REG_KEYSCAN_TASK_EVNT_STS_TYPE;
+
+/*0x4000_62f0 PLATFORM_REG_KEYSCAN_TASK_EVNT_STS*/
+#define PLATFORM_REG_KEYSCAN_TASK_EVNT_STS_r_KEYSCAN_EVNT_MANUAL_DONE_sts_Pos                                0U
+#define PLATFORM_REG_KEYSCAN_TASK_EVNT_STS_r_KEYSCAN_EVNT_MANUAL_DONE_sts_Msk                                (0x1UL << PLATFORM_REG_KEYSCAN_TASK_EVNT_STS_r_KEYSCAN_EVNT_MANUAL_DONE_sts_Pos)
+
+#define PLATFORM_REG_KEYSCAN_TASK_EVNT_STS_reserved_1_Pos                                                    1U
+#define PLATFORM_REG_KEYSCAN_TASK_EVNT_STS_reserved_1_Msk                                                    (0x7FFFUL << PLATFORM_REG_KEYSCAN_TASK_EVNT_STS_reserved_1_Pos)
+
+#define PLATFORM_REG_KEYSCAN_TASK_EVNT_STS_r_KEYSCAN_TASK_MANUAL_sts_Pos                                     16U
+#define PLATFORM_REG_KEYSCAN_TASK_EVNT_STS_r_KEYSCAN_TASK_MANUAL_sts_Msk                                     (0x1UL << PLATFORM_REG_KEYSCAN_TASK_EVNT_STS_r_KEYSCAN_TASK_MANUAL_sts_Pos)
+
+#define PLATFORM_REG_KEYSCAN_TASK_EVNT_STS_reserved_Pos                                                      17U
+#define PLATFORM_REG_KEYSCAN_TASK_EVNT_STS_reserved_Msk                                                      (0x7FFFUL << PLATFORM_REG_KEYSCAN_TASK_EVNT_STS_reserved_Pos)
+
+/* 0x02f4   0x4000_62f4
+    0       R/W1C   r_TIMER1_CH0_EVNT_ACTIVE_sts                        1'b0
+    1       R/W1C   r_TIMER1_CH0_EVNT_STOP_sts                          1'b0
+    2       R/W1C   r_TIMER1_CH0_EVNT_TIMEOUT_sts                       1'b0
+    3       R/W1C   r_TIMER1_CH1_EVNT_ACTIVE_sts                        1'b0
+    4       R/W1C   r_TIMER1_CH1_EVNT_STOP_sts                          1'b0
+    5       R/W1C   r_TIMER1_CH1_EVNT_TIMEOUT_sts                       1'b0
+    6       R/W1C   r_TIMER1_CH2_EVNT_ACTIVE_sts                        1'b0
+    7       R/W1C   r_TIMER1_CH2_EVNT_STOP_sts                          1'b0
+    8       R/W1C   r_TIMER1_CH2_EVNT_TIMEOUT_sts                       1'b0
+    9       R/W1C   r_TIMER1_CH3_EVNT_ACTIVE_sts                        1'b0
+    10      R/W1C   r_TIMER1_CH3_EVNT_STOP_sts                          1'b0
+    11      R/W1C   r_TIMER1_CH3_EVNT_TIMEOUT_sts                       1'b0
+    12      R/W1C   r_TIMER1_CH4_EVNT_ACTIVE_sts                        1'b0
+    13      R/W1C   r_TIMER1_CH4_EVNT_STOP_sts                          1'b0
+    14      R/W1C   r_TIMER1_CH4_EVNT_TIMEOUT_sts                       1'b0
+    15      R/W1C   r_TIMER1_CH5_EVNT_ACTIVE_sts                        1'b0
+    16      R/W1C   r_TIMER1_CH5_EVNT_STOP_sts                          1'b0
+    17      R/W1C   r_TIMER1_CH5_EVNT_TIMEOUT_sts                       1'b0
+    18      R/W1C   r_TIMER1_CH6_EVNT_ACTIVE_sts                        1'b0
+    19      R/W1C   r_TIMER1_CH6_EVNT_STOP_sts                          1'b0
+    20      R/W1C   r_TIMER1_CH6_EVNT_TIMEOUT_sts                       1'b0
+    21      R/W1C   r_TIMER1_CH7_EVNT_ACTIVE_sts                        1'b0
+    22      R/W1C   r_TIMER1_CH7_EVNT_STOP_sts                          1'b0
+    23      R/W1C   r_TIMER1_CH7_EVNT_TIMEOUT_sts                       1'b0
+    24      R/W1C   r_TIMER1_CH8_EVNT_ACTIVE_sts                        1'b0
+    25      R/W1C   r_TIMER1_CH8_EVNT_STOP_sts                          1'b0
+    26      R/W1C   r_TIMER1_CH8_EVNT_TIMEOUT_sts                       1'b0
+    31:27   R       reserved                                            5'h00
+ */
+typedef union _PLATFORM_REG_TIMER1_EVNT_STS_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t r_TIMER1_CH0_EVNT_ACTIVE_sts: 1;
+        uint32_t r_TIMER1_CH0_EVNT_STOP_sts: 1;
+        uint32_t r_TIMER1_CH0_EVNT_TIMEOUT_sts: 1;
+        uint32_t r_TIMER1_CH1_EVNT_ACTIVE_sts: 1;
+        uint32_t r_TIMER1_CH1_EVNT_STOP_sts: 1;
+        uint32_t r_TIMER1_CH1_EVNT_TIMEOUT_sts: 1;
+        uint32_t r_TIMER1_CH2_EVNT_ACTIVE_sts: 1;
+        uint32_t r_TIMER1_CH2_EVNT_STOP_sts: 1;
+        uint32_t r_TIMER1_CH2_EVNT_TIMEOUT_sts: 1;
+        uint32_t r_TIMER1_CH3_EVNT_ACTIVE_sts: 1;
+        uint32_t r_TIMER1_CH3_EVNT_STOP_sts: 1;
+        uint32_t r_TIMER1_CH3_EVNT_TIMEOUT_sts: 1;
+        uint32_t r_TIMER1_CH4_EVNT_ACTIVE_sts: 1;
+        uint32_t r_TIMER1_CH4_EVNT_STOP_sts: 1;
+        uint32_t r_TIMER1_CH4_EVNT_TIMEOUT_sts: 1;
+        uint32_t r_TIMER1_CH5_EVNT_ACTIVE_sts: 1;
+        uint32_t r_TIMER1_CH5_EVNT_STOP_sts: 1;
+        uint32_t r_TIMER1_CH5_EVNT_TIMEOUT_sts: 1;
+        uint32_t r_TIMER1_CH6_EVNT_ACTIVE_sts: 1;
+        uint32_t r_TIMER1_CH6_EVNT_STOP_sts: 1;
+        uint32_t r_TIMER1_CH6_EVNT_TIMEOUT_sts: 1;
+        uint32_t r_TIMER1_CH7_EVNT_ACTIVE_sts: 1;
+        uint32_t r_TIMER1_CH7_EVNT_STOP_sts: 1;
+        uint32_t r_TIMER1_CH7_EVNT_TIMEOUT_sts: 1;
+        uint32_t r_TIMER1_CH8_EVNT_ACTIVE_sts: 1;
+        uint32_t r_TIMER1_CH8_EVNT_STOP_sts: 1;
+        uint32_t r_TIMER1_CH8_EVNT_TIMEOUT_sts: 1;
+        uint32_t reserved: 5;
+    };
+} PLATFORM_REG_TIMER1_EVNT_STS_TYPE;
+
+/*0x4000_62f4 PLATFORM_REG_TIMER1_EVNT_STS*/
+#define PLATFORM_REG_TIMER1_EVNT_STS_r_TIMER1_CH0_EVNT_ACTIVE_sts_Pos                                        0U
+#define PLATFORM_REG_TIMER1_EVNT_STS_r_TIMER1_CH0_EVNT_ACTIVE_sts_Msk                                        (0x1UL << PLATFORM_REG_TIMER1_EVNT_STS_r_TIMER1_CH0_EVNT_ACTIVE_sts_Pos)
+
+#define PLATFORM_REG_TIMER1_EVNT_STS_r_TIMER1_CH0_EVNT_STOP_sts_Pos                                          1U
+#define PLATFORM_REG_TIMER1_EVNT_STS_r_TIMER1_CH0_EVNT_STOP_sts_Msk                                          (0x1UL << PLATFORM_REG_TIMER1_EVNT_STS_r_TIMER1_CH0_EVNT_STOP_sts_Pos)
+
+#define PLATFORM_REG_TIMER1_EVNT_STS_r_TIMER1_CH0_EVNT_TIMEOUT_sts_Pos                                       2U
+#define PLATFORM_REG_TIMER1_EVNT_STS_r_TIMER1_CH0_EVNT_TIMEOUT_sts_Msk                                       (0x1UL << PLATFORM_REG_TIMER1_EVNT_STS_r_TIMER1_CH0_EVNT_TIMEOUT_sts_Pos)
+
+#define PLATFORM_REG_TIMER1_EVNT_STS_r_TIMER1_CH1_EVNT_ACTIVE_sts_Pos                                        3U
+#define PLATFORM_REG_TIMER1_EVNT_STS_r_TIMER1_CH1_EVNT_ACTIVE_sts_Msk                                        (0x1UL << PLATFORM_REG_TIMER1_EVNT_STS_r_TIMER1_CH1_EVNT_ACTIVE_sts_Pos)
+
+#define PLATFORM_REG_TIMER1_EVNT_STS_r_TIMER1_CH1_EVNT_STOP_sts_Pos                                          4U
+#define PLATFORM_REG_TIMER1_EVNT_STS_r_TIMER1_CH1_EVNT_STOP_sts_Msk                                          (0x1UL << PLATFORM_REG_TIMER1_EVNT_STS_r_TIMER1_CH1_EVNT_STOP_sts_Pos)
+
+#define PLATFORM_REG_TIMER1_EVNT_STS_r_TIMER1_CH1_EVNT_TIMEOUT_sts_Pos                                       5U
+#define PLATFORM_REG_TIMER1_EVNT_STS_r_TIMER1_CH1_EVNT_TIMEOUT_sts_Msk                                       (0x1UL << PLATFORM_REG_TIMER1_EVNT_STS_r_TIMER1_CH1_EVNT_TIMEOUT_sts_Pos)
+
+#define PLATFORM_REG_TIMER1_EVNT_STS_r_TIMER1_CH2_EVNT_ACTIVE_sts_Pos                                        6U
+#define PLATFORM_REG_TIMER1_EVNT_STS_r_TIMER1_CH2_EVNT_ACTIVE_sts_Msk                                        (0x1UL << PLATFORM_REG_TIMER1_EVNT_STS_r_TIMER1_CH2_EVNT_ACTIVE_sts_Pos)
+
+#define PLATFORM_REG_TIMER1_EVNT_STS_r_TIMER1_CH2_EVNT_STOP_sts_Pos                                          7U
+#define PLATFORM_REG_TIMER1_EVNT_STS_r_TIMER1_CH2_EVNT_STOP_sts_Msk                                          (0x1UL << PLATFORM_REG_TIMER1_EVNT_STS_r_TIMER1_CH2_EVNT_STOP_sts_Pos)
+
+#define PLATFORM_REG_TIMER1_EVNT_STS_r_TIMER1_CH2_EVNT_TIMEOUT_sts_Pos                                       8U
+#define PLATFORM_REG_TIMER1_EVNT_STS_r_TIMER1_CH2_EVNT_TIMEOUT_sts_Msk                                       (0x1UL << PLATFORM_REG_TIMER1_EVNT_STS_r_TIMER1_CH2_EVNT_TIMEOUT_sts_Pos)
+
+#define PLATFORM_REG_TIMER1_EVNT_STS_r_TIMER1_CH3_EVNT_ACTIVE_sts_Pos                                        9U
+#define PLATFORM_REG_TIMER1_EVNT_STS_r_TIMER1_CH3_EVNT_ACTIVE_sts_Msk                                        (0x1UL << PLATFORM_REG_TIMER1_EVNT_STS_r_TIMER1_CH3_EVNT_ACTIVE_sts_Pos)
+
+#define PLATFORM_REG_TIMER1_EVNT_STS_r_TIMER1_CH3_EVNT_STOP_sts_Pos                                          10U
+#define PLATFORM_REG_TIMER1_EVNT_STS_r_TIMER1_CH3_EVNT_STOP_sts_Msk                                          (0x1UL << PLATFORM_REG_TIMER1_EVNT_STS_r_TIMER1_CH3_EVNT_STOP_sts_Pos)
+
+#define PLATFORM_REG_TIMER1_EVNT_STS_r_TIMER1_CH3_EVNT_TIMEOUT_sts_Pos                                       11U
+#define PLATFORM_REG_TIMER1_EVNT_STS_r_TIMER1_CH3_EVNT_TIMEOUT_sts_Msk                                       (0x1UL << PLATFORM_REG_TIMER1_EVNT_STS_r_TIMER1_CH3_EVNT_TIMEOUT_sts_Pos)
+
+#define PLATFORM_REG_TIMER1_EVNT_STS_r_TIMER1_CH4_EVNT_ACTIVE_sts_Pos                                        12U
+#define PLATFORM_REG_TIMER1_EVNT_STS_r_TIMER1_CH4_EVNT_ACTIVE_sts_Msk                                        (0x1UL << PLATFORM_REG_TIMER1_EVNT_STS_r_TIMER1_CH4_EVNT_ACTIVE_sts_Pos)
+
+#define PLATFORM_REG_TIMER1_EVNT_STS_r_TIMER1_CH4_EVNT_STOP_sts_Pos                                          13U
+#define PLATFORM_REG_TIMER1_EVNT_STS_r_TIMER1_CH4_EVNT_STOP_sts_Msk                                          (0x1UL << PLATFORM_REG_TIMER1_EVNT_STS_r_TIMER1_CH4_EVNT_STOP_sts_Pos)
+
+#define PLATFORM_REG_TIMER1_EVNT_STS_r_TIMER1_CH4_EVNT_TIMEOUT_sts_Pos                                       14U
+#define PLATFORM_REG_TIMER1_EVNT_STS_r_TIMER1_CH4_EVNT_TIMEOUT_sts_Msk                                       (0x1UL << PLATFORM_REG_TIMER1_EVNT_STS_r_TIMER1_CH4_EVNT_TIMEOUT_sts_Pos)
+
+#define PLATFORM_REG_TIMER1_EVNT_STS_r_TIMER1_CH5_EVNT_ACTIVE_sts_Pos                                        15U
+#define PLATFORM_REG_TIMER1_EVNT_STS_r_TIMER1_CH5_EVNT_ACTIVE_sts_Msk                                        (0x1UL << PLATFORM_REG_TIMER1_EVNT_STS_r_TIMER1_CH5_EVNT_ACTIVE_sts_Pos)
+
+#define PLATFORM_REG_TIMER1_EVNT_STS_r_TIMER1_CH5_EVNT_STOP_sts_Pos                                          16U
+#define PLATFORM_REG_TIMER1_EVNT_STS_r_TIMER1_CH5_EVNT_STOP_sts_Msk                                          (0x1UL << PLATFORM_REG_TIMER1_EVNT_STS_r_TIMER1_CH5_EVNT_STOP_sts_Pos)
+
+#define PLATFORM_REG_TIMER1_EVNT_STS_r_TIMER1_CH5_EVNT_TIMEOUT_sts_Pos                                       17U
+#define PLATFORM_REG_TIMER1_EVNT_STS_r_TIMER1_CH5_EVNT_TIMEOUT_sts_Msk                                       (0x1UL << PLATFORM_REG_TIMER1_EVNT_STS_r_TIMER1_CH5_EVNT_TIMEOUT_sts_Pos)
+
+#define PLATFORM_REG_TIMER1_EVNT_STS_r_TIMER1_CH6_EVNT_ACTIVE_sts_Pos                                        18U
+#define PLATFORM_REG_TIMER1_EVNT_STS_r_TIMER1_CH6_EVNT_ACTIVE_sts_Msk                                        (0x1UL << PLATFORM_REG_TIMER1_EVNT_STS_r_TIMER1_CH6_EVNT_ACTIVE_sts_Pos)
+
+#define PLATFORM_REG_TIMER1_EVNT_STS_r_TIMER1_CH6_EVNT_STOP_sts_Pos                                          19U
+#define PLATFORM_REG_TIMER1_EVNT_STS_r_TIMER1_CH6_EVNT_STOP_sts_Msk                                          (0x1UL << PLATFORM_REG_TIMER1_EVNT_STS_r_TIMER1_CH6_EVNT_STOP_sts_Pos)
+
+#define PLATFORM_REG_TIMER1_EVNT_STS_r_TIMER1_CH6_EVNT_TIMEOUT_sts_Pos                                       20U
+#define PLATFORM_REG_TIMER1_EVNT_STS_r_TIMER1_CH6_EVNT_TIMEOUT_sts_Msk                                       (0x1UL << PLATFORM_REG_TIMER1_EVNT_STS_r_TIMER1_CH6_EVNT_TIMEOUT_sts_Pos)
+
+#define PLATFORM_REG_TIMER1_EVNT_STS_r_TIMER1_CH7_EVNT_ACTIVE_sts_Pos                                        21U
+#define PLATFORM_REG_TIMER1_EVNT_STS_r_TIMER1_CH7_EVNT_ACTIVE_sts_Msk                                        (0x1UL << PLATFORM_REG_TIMER1_EVNT_STS_r_TIMER1_CH7_EVNT_ACTIVE_sts_Pos)
+
+#define PLATFORM_REG_TIMER1_EVNT_STS_r_TIMER1_CH7_EVNT_STOP_sts_Pos                                          22U
+#define PLATFORM_REG_TIMER1_EVNT_STS_r_TIMER1_CH7_EVNT_STOP_sts_Msk                                          (0x1UL << PLATFORM_REG_TIMER1_EVNT_STS_r_TIMER1_CH7_EVNT_STOP_sts_Pos)
+
+#define PLATFORM_REG_TIMER1_EVNT_STS_r_TIMER1_CH7_EVNT_TIMEOUT_sts_Pos                                       23U
+#define PLATFORM_REG_TIMER1_EVNT_STS_r_TIMER1_CH7_EVNT_TIMEOUT_sts_Msk                                       (0x1UL << PLATFORM_REG_TIMER1_EVNT_STS_r_TIMER1_CH7_EVNT_TIMEOUT_sts_Pos)
+
+#define PLATFORM_REG_TIMER1_EVNT_STS_r_TIMER1_CH8_EVNT_ACTIVE_sts_Pos                                        24U
+#define PLATFORM_REG_TIMER1_EVNT_STS_r_TIMER1_CH8_EVNT_ACTIVE_sts_Msk                                        (0x1UL << PLATFORM_REG_TIMER1_EVNT_STS_r_TIMER1_CH8_EVNT_ACTIVE_sts_Pos)
+
+#define PLATFORM_REG_TIMER1_EVNT_STS_r_TIMER1_CH8_EVNT_STOP_sts_Pos                                          25U
+#define PLATFORM_REG_TIMER1_EVNT_STS_r_TIMER1_CH8_EVNT_STOP_sts_Msk                                          (0x1UL << PLATFORM_REG_TIMER1_EVNT_STS_r_TIMER1_CH8_EVNT_STOP_sts_Pos)
+
+#define PLATFORM_REG_TIMER1_EVNT_STS_r_TIMER1_CH8_EVNT_TIMEOUT_sts_Pos                                       26U
+#define PLATFORM_REG_TIMER1_EVNT_STS_r_TIMER1_CH8_EVNT_TIMEOUT_sts_Msk                                       (0x1UL << PLATFORM_REG_TIMER1_EVNT_STS_r_TIMER1_CH8_EVNT_TIMEOUT_sts_Pos)
+
+#define PLATFORM_REG_TIMER1_EVNT_STS_reserved_Pos                                                            27U
+#define PLATFORM_REG_TIMER1_EVNT_STS_reserved_Msk                                                            (0x1FUL << PLATFORM_REG_TIMER1_EVNT_STS_reserved_Pos)
+
+/* 0x02f8   0x4000_62f8
+    0       R/W1C   r_TIMER1_CH0_TASK_DISABLE_sts                       1'b0
+    1       R/W1C   r_TIMER1_CH0_TASK_PAUSE_sts                         1'b0
+    2       R/W1C   r_TIMER1_CH0_TASK_START_sts                         1'b0
+    3       R/W1C   r_TIMER1_CH1_TASK_DISABLE_sts                       1'b0
+    4       R/W1C   r_TIMER1_CH1_TASK_PAUSE_sts                         1'b0
+    5       R/W1C   r_TIMER1_CH1_TASK_START_sts                         1'b0
+    6       R/W1C   r_TIMER1_CH2_TASK_DISABLE_sts                       1'b0
+    7       R/W1C   r_TIMER1_CH2_TASK_PAUSE_sts                         1'b0
+    8       R/W1C   r_TIMER1_CH2_TASK_START_sts                         1'b0
+    9       R/W1C   r_TIMER1_CH3_TASK_DISABLE_sts                       1'b0
+    10      R/W1C   r_TIMER1_CH3_TASK_PAUSE_sts                         1'b0
+    11      R/W1C   r_TIMER1_CH3_TASK_START_sts                         1'b0
+    12      R/W1C   r_TIMER1_CH4_TASK_DISABLE_sts                       1'b0
+    13      R/W1C   r_TIMER1_CH4_TASK_PAUSE_sts                         1'b0
+    14      R/W1C   r_TIMER1_CH4_TASK_START_sts                         1'b0
+    15      R/W1C   r_TIMER1_CH5_TASK_DISABLE_sts                       1'b0
+    16      R/W1C   r_TIMER1_CH5_TASK_PAUSE_sts                         1'b0
+    17      R/W1C   r_TIMER1_CH5_TASK_START_sts                         1'b0
+    18      R/W1C   r_TIMER1_CH6_TASK_DISABLE_sts                       1'b0
+    19      R/W1C   r_TIMER1_CH6_TASK_PAUSE_sts                         1'b0
+    20      R/W1C   r_TIMER1_CH6_TASK_START_sts                         1'b0
+    21      R/W1C   r_TIMER1_CH7_TASK_DISABLE_sts                       1'b0
+    22      R/W1C   r_TIMER1_CH7_TASK_PAUSE_sts                         1'b0
+    23      R/W1C   r_TIMER1_CH7_TASK_START_sts                         1'b0
+    24      R/W1C   r_TIMER1_CH8_TASK_DISABLE_sts                       1'b0
+    25      R/W1C   r_TIMER1_CH8_TASK_PAUSE_sts                         1'b0
+    26      R/W1C   r_TIMER1_CH8_TASK_START_sts                         1'b0
+    31:27   R       reserved                                            5'h00
+ */
+typedef union _PLATFORM_REG_TIMER1_TASK_STS_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t r_TIMER1_CH0_TASK_DISABLE_sts: 1;
+        uint32_t r_TIMER1_CH0_TASK_PAUSE_sts: 1;
+        uint32_t r_TIMER1_CH0_TASK_START_sts: 1;
+        uint32_t r_TIMER1_CH1_TASK_DISABLE_sts: 1;
+        uint32_t r_TIMER1_CH1_TASK_PAUSE_sts: 1;
+        uint32_t r_TIMER1_CH1_TASK_START_sts: 1;
+        uint32_t r_TIMER1_CH2_TASK_DISABLE_sts: 1;
+        uint32_t r_TIMER1_CH2_TASK_PAUSE_sts: 1;
+        uint32_t r_TIMER1_CH2_TASK_START_sts: 1;
+        uint32_t r_TIMER1_CH3_TASK_DISABLE_sts: 1;
+        uint32_t r_TIMER1_CH3_TASK_PAUSE_sts: 1;
+        uint32_t r_TIMER1_CH3_TASK_START_sts: 1;
+        uint32_t r_TIMER1_CH4_TASK_DISABLE_sts: 1;
+        uint32_t r_TIMER1_CH4_TASK_PAUSE_sts: 1;
+        uint32_t r_TIMER1_CH4_TASK_START_sts: 1;
+        uint32_t r_TIMER1_CH5_TASK_DISABLE_sts: 1;
+        uint32_t r_TIMER1_CH5_TASK_PAUSE_sts: 1;
+        uint32_t r_TIMER1_CH5_TASK_START_sts: 1;
+        uint32_t r_TIMER1_CH6_TASK_DISABLE_sts: 1;
+        uint32_t r_TIMER1_CH6_TASK_PAUSE_sts: 1;
+        uint32_t r_TIMER1_CH6_TASK_START_sts: 1;
+        uint32_t r_TIMER1_CH7_TASK_DISABLE_sts: 1;
+        uint32_t r_TIMER1_CH7_TASK_PAUSE_sts: 1;
+        uint32_t r_TIMER1_CH7_TASK_START_sts: 1;
+        uint32_t r_TIMER1_CH8_TASK_DISABLE_sts: 1;
+        uint32_t r_TIMER1_CH8_TASK_PAUSE_sts: 1;
+        uint32_t r_TIMER1_CH8_TASK_START_sts: 1;
+        uint32_t reserved: 5;
+    };
+} PLATFORM_REG_TIMER1_TASK_STS_TYPE;
+
+/*0x4000_62f8 PLATFORM_REG_TIMER1_TASK_STS*/
+#define PLATFORM_REG_TIMER1_TASK_STS_r_TIMER1_CH0_TASK_DISABLE_sts_Pos                                       0U
+#define PLATFORM_REG_TIMER1_TASK_STS_r_TIMER1_CH0_TASK_DISABLE_sts_Msk                                       (0x1UL << PLATFORM_REG_TIMER1_TASK_STS_r_TIMER1_CH0_TASK_DISABLE_sts_Pos)
+
+#define PLATFORM_REG_TIMER1_TASK_STS_r_TIMER1_CH0_TASK_PAUSE_sts_Pos                                         1U
+#define PLATFORM_REG_TIMER1_TASK_STS_r_TIMER1_CH0_TASK_PAUSE_sts_Msk                                         (0x1UL << PLATFORM_REG_TIMER1_TASK_STS_r_TIMER1_CH0_TASK_PAUSE_sts_Pos)
+
+#define PLATFORM_REG_TIMER1_TASK_STS_r_TIMER1_CH0_TASK_START_sts_Pos                                         2U
+#define PLATFORM_REG_TIMER1_TASK_STS_r_TIMER1_CH0_TASK_START_sts_Msk                                         (0x1UL << PLATFORM_REG_TIMER1_TASK_STS_r_TIMER1_CH0_TASK_START_sts_Pos)
+
+#define PLATFORM_REG_TIMER1_TASK_STS_r_TIMER1_CH1_TASK_DISABLE_sts_Pos                                       3U
+#define PLATFORM_REG_TIMER1_TASK_STS_r_TIMER1_CH1_TASK_DISABLE_sts_Msk                                       (0x1UL << PLATFORM_REG_TIMER1_TASK_STS_r_TIMER1_CH1_TASK_DISABLE_sts_Pos)
+
+#define PLATFORM_REG_TIMER1_TASK_STS_r_TIMER1_CH1_TASK_PAUSE_sts_Pos                                         4U
+#define PLATFORM_REG_TIMER1_TASK_STS_r_TIMER1_CH1_TASK_PAUSE_sts_Msk                                         (0x1UL << PLATFORM_REG_TIMER1_TASK_STS_r_TIMER1_CH1_TASK_PAUSE_sts_Pos)
+
+#define PLATFORM_REG_TIMER1_TASK_STS_r_TIMER1_CH1_TASK_START_sts_Pos                                         5U
+#define PLATFORM_REG_TIMER1_TASK_STS_r_TIMER1_CH1_TASK_START_sts_Msk                                         (0x1UL << PLATFORM_REG_TIMER1_TASK_STS_r_TIMER1_CH1_TASK_START_sts_Pos)
+
+#define PLATFORM_REG_TIMER1_TASK_STS_r_TIMER1_CH2_TASK_DISABLE_sts_Pos                                       6U
+#define PLATFORM_REG_TIMER1_TASK_STS_r_TIMER1_CH2_TASK_DISABLE_sts_Msk                                       (0x1UL << PLATFORM_REG_TIMER1_TASK_STS_r_TIMER1_CH2_TASK_DISABLE_sts_Pos)
+
+#define PLATFORM_REG_TIMER1_TASK_STS_r_TIMER1_CH2_TASK_PAUSE_sts_Pos                                         7U
+#define PLATFORM_REG_TIMER1_TASK_STS_r_TIMER1_CH2_TASK_PAUSE_sts_Msk                                         (0x1UL << PLATFORM_REG_TIMER1_TASK_STS_r_TIMER1_CH2_TASK_PAUSE_sts_Pos)
+
+#define PLATFORM_REG_TIMER1_TASK_STS_r_TIMER1_CH2_TASK_START_sts_Pos                                         8U
+#define PLATFORM_REG_TIMER1_TASK_STS_r_TIMER1_CH2_TASK_START_sts_Msk                                         (0x1UL << PLATFORM_REG_TIMER1_TASK_STS_r_TIMER1_CH2_TASK_START_sts_Pos)
+
+#define PLATFORM_REG_TIMER1_TASK_STS_r_TIMER1_CH3_TASK_DISABLE_sts_Pos                                       9U
+#define PLATFORM_REG_TIMER1_TASK_STS_r_TIMER1_CH3_TASK_DISABLE_sts_Msk                                       (0x1UL << PLATFORM_REG_TIMER1_TASK_STS_r_TIMER1_CH3_TASK_DISABLE_sts_Pos)
+
+#define PLATFORM_REG_TIMER1_TASK_STS_r_TIMER1_CH3_TASK_PAUSE_sts_Pos                                         10U
+#define PLATFORM_REG_TIMER1_TASK_STS_r_TIMER1_CH3_TASK_PAUSE_sts_Msk                                         (0x1UL << PLATFORM_REG_TIMER1_TASK_STS_r_TIMER1_CH3_TASK_PAUSE_sts_Pos)
+
+#define PLATFORM_REG_TIMER1_TASK_STS_r_TIMER1_CH3_TASK_START_sts_Pos                                         11U
+#define PLATFORM_REG_TIMER1_TASK_STS_r_TIMER1_CH3_TASK_START_sts_Msk                                         (0x1UL << PLATFORM_REG_TIMER1_TASK_STS_r_TIMER1_CH3_TASK_START_sts_Pos)
+
+#define PLATFORM_REG_TIMER1_TASK_STS_r_TIMER1_CH4_TASK_DISABLE_sts_Pos                                       12U
+#define PLATFORM_REG_TIMER1_TASK_STS_r_TIMER1_CH4_TASK_DISABLE_sts_Msk                                       (0x1UL << PLATFORM_REG_TIMER1_TASK_STS_r_TIMER1_CH4_TASK_DISABLE_sts_Pos)
+
+#define PLATFORM_REG_TIMER1_TASK_STS_r_TIMER1_CH4_TASK_PAUSE_sts_Pos                                         13U
+#define PLATFORM_REG_TIMER1_TASK_STS_r_TIMER1_CH4_TASK_PAUSE_sts_Msk                                         (0x1UL << PLATFORM_REG_TIMER1_TASK_STS_r_TIMER1_CH4_TASK_PAUSE_sts_Pos)
+
+#define PLATFORM_REG_TIMER1_TASK_STS_r_TIMER1_CH4_TASK_START_sts_Pos                                         14U
+#define PLATFORM_REG_TIMER1_TASK_STS_r_TIMER1_CH4_TASK_START_sts_Msk                                         (0x1UL << PLATFORM_REG_TIMER1_TASK_STS_r_TIMER1_CH4_TASK_START_sts_Pos)
+
+#define PLATFORM_REG_TIMER1_TASK_STS_r_TIMER1_CH5_TASK_DISABLE_sts_Pos                                       15U
+#define PLATFORM_REG_TIMER1_TASK_STS_r_TIMER1_CH5_TASK_DISABLE_sts_Msk                                       (0x1UL << PLATFORM_REG_TIMER1_TASK_STS_r_TIMER1_CH5_TASK_DISABLE_sts_Pos)
+
+#define PLATFORM_REG_TIMER1_TASK_STS_r_TIMER1_CH5_TASK_PAUSE_sts_Pos                                         16U
+#define PLATFORM_REG_TIMER1_TASK_STS_r_TIMER1_CH5_TASK_PAUSE_sts_Msk                                         (0x1UL << PLATFORM_REG_TIMER1_TASK_STS_r_TIMER1_CH5_TASK_PAUSE_sts_Pos)
+
+#define PLATFORM_REG_TIMER1_TASK_STS_r_TIMER1_CH5_TASK_START_sts_Pos                                         17U
+#define PLATFORM_REG_TIMER1_TASK_STS_r_TIMER1_CH5_TASK_START_sts_Msk                                         (0x1UL << PLATFORM_REG_TIMER1_TASK_STS_r_TIMER1_CH5_TASK_START_sts_Pos)
+
+#define PLATFORM_REG_TIMER1_TASK_STS_r_TIMER1_CH6_TASK_DISABLE_sts_Pos                                       18U
+#define PLATFORM_REG_TIMER1_TASK_STS_r_TIMER1_CH6_TASK_DISABLE_sts_Msk                                       (0x1UL << PLATFORM_REG_TIMER1_TASK_STS_r_TIMER1_CH6_TASK_DISABLE_sts_Pos)
+
+#define PLATFORM_REG_TIMER1_TASK_STS_r_TIMER1_CH6_TASK_PAUSE_sts_Pos                                         19U
+#define PLATFORM_REG_TIMER1_TASK_STS_r_TIMER1_CH6_TASK_PAUSE_sts_Msk                                         (0x1UL << PLATFORM_REG_TIMER1_TASK_STS_r_TIMER1_CH6_TASK_PAUSE_sts_Pos)
+
+#define PLATFORM_REG_TIMER1_TASK_STS_r_TIMER1_CH6_TASK_START_sts_Pos                                         20U
+#define PLATFORM_REG_TIMER1_TASK_STS_r_TIMER1_CH6_TASK_START_sts_Msk                                         (0x1UL << PLATFORM_REG_TIMER1_TASK_STS_r_TIMER1_CH6_TASK_START_sts_Pos)
+
+#define PLATFORM_REG_TIMER1_TASK_STS_r_TIMER1_CH7_TASK_DISABLE_sts_Pos                                       21U
+#define PLATFORM_REG_TIMER1_TASK_STS_r_TIMER1_CH7_TASK_DISABLE_sts_Msk                                       (0x1UL << PLATFORM_REG_TIMER1_TASK_STS_r_TIMER1_CH7_TASK_DISABLE_sts_Pos)
+
+#define PLATFORM_REG_TIMER1_TASK_STS_r_TIMER1_CH7_TASK_PAUSE_sts_Pos                                         22U
+#define PLATFORM_REG_TIMER1_TASK_STS_r_TIMER1_CH7_TASK_PAUSE_sts_Msk                                         (0x1UL << PLATFORM_REG_TIMER1_TASK_STS_r_TIMER1_CH7_TASK_PAUSE_sts_Pos)
+
+#define PLATFORM_REG_TIMER1_TASK_STS_r_TIMER1_CH7_TASK_START_sts_Pos                                         23U
+#define PLATFORM_REG_TIMER1_TASK_STS_r_TIMER1_CH7_TASK_START_sts_Msk                                         (0x1UL << PLATFORM_REG_TIMER1_TASK_STS_r_TIMER1_CH7_TASK_START_sts_Pos)
+
+#define PLATFORM_REG_TIMER1_TASK_STS_r_TIMER1_CH8_TASK_DISABLE_sts_Pos                                       24U
+#define PLATFORM_REG_TIMER1_TASK_STS_r_TIMER1_CH8_TASK_DISABLE_sts_Msk                                       (0x1UL << PLATFORM_REG_TIMER1_TASK_STS_r_TIMER1_CH8_TASK_DISABLE_sts_Pos)
+
+#define PLATFORM_REG_TIMER1_TASK_STS_r_TIMER1_CH8_TASK_PAUSE_sts_Pos                                         25U
+#define PLATFORM_REG_TIMER1_TASK_STS_r_TIMER1_CH8_TASK_PAUSE_sts_Msk                                         (0x1UL << PLATFORM_REG_TIMER1_TASK_STS_r_TIMER1_CH8_TASK_PAUSE_sts_Pos)
+
+#define PLATFORM_REG_TIMER1_TASK_STS_r_TIMER1_CH8_TASK_START_sts_Pos                                         26U
+#define PLATFORM_REG_TIMER1_TASK_STS_r_TIMER1_CH8_TASK_START_sts_Msk                                         (0x1UL << PLATFORM_REG_TIMER1_TASK_STS_r_TIMER1_CH8_TASK_START_sts_Pos)
+
+#define PLATFORM_REG_TIMER1_TASK_STS_reserved_Pos                                                            27U
+#define PLATFORM_REG_TIMER1_TASK_STS_reserved_Msk                                                            (0x1FUL << PLATFORM_REG_TIMER1_TASK_STS_reserved_Pos)
+
+/* 0x02fc   0x4000_62fc
+    0       R/W1C   r_GPIO0_0_EVNT_IN_sts                               1'b0
+    1       R/W1C   r_GPIO0_1_EVNT_IN_sts                               1'b0
+    2       R/W1C   r_GPIO0_2_EVNT_IN_sts                               1'b0
+    3       R/W1C   r_GPIO0_3_EVNT_IN_sts                               1'b0
+    4       R/W1C   r_GPIO0_4_EVNT_IN_sts                               1'b0
+    5       R/W1C   r_GPIO0_5_EVNT_IN_sts                               1'b0
+    6       R/W1C   r_GPIO0_6_EVNT_IN_sts                               1'b0
+    7       R/W1C   r_GPIO0_7_EVNT_IN_sts                               1'b0
+    8       R/W1C   r_GPIO0_8_EVNT_IN_sts                               1'b0
+    9       R/W1C   r_GPIO0_9_EVNT_IN_sts                               1'b0
+    10      R/W1C   r_GPIO0_10_EVNT_IN_sts                              1'b0
+    11      R/W1C   r_GPIO0_11_EVNT_IN_sts                              1'b0
+    12      R/W1C   r_GPIO0_12_EVNT_IN_sts                              1'b0
+    13      R/W1C   r_GPIO0_13_EVNT_IN_sts                              1'b0
+    14      R/W1C   r_GPIO0_14_EVNT_IN_sts                              1'b0
+    15      R/W1C   r_GPIO0_15_EVNT_IN_sts                              1'b0
+    16      R/W1C   r_GPIO0_16_EVNT_IN_sts                              1'b0
+    17      R/W1C   r_GPIO0_17_EVNT_IN_sts                              1'b0
+    18      R/W1C   r_GPIO0_18_EVNT_IN_sts                              1'b0
+    19      R/W1C   r_GPIO0_19_EVNT_IN_sts                              1'b0
+    20      R/W1C   r_GPIO0_20_EVNT_IN_sts                              1'b0
+    21      R/W1C   r_GPIO0_21_EVNT_IN_sts                              1'b0
+    22      R/W1C   r_GPIO0_22_EVNT_IN_sts                              1'b0
+    23      R/W1C   r_GPIO0_23_EVNT_IN_sts                              1'b0
+    24      R/W1C   r_GPIO0_24_EVNT_IN_sts                              1'b0
+    25      R/W1C   r_GPIO0_25_EVNT_IN_sts                              1'b0
+    26      R/W1C   r_GPIO0_26_EVNT_IN_sts                              1'b0
+    27      R/W1C   r_GPIO0_27_EVNT_IN_sts                              1'b0
+    28      R/W1C   r_GPIO0_28_EVNT_IN_sts                              1'b0
+    29      R/W1C   r_GPIO0_29_EVNT_IN_sts                              1'b0
+    30      R/W1C   r_GPIO0_30_EVNT_IN_sts                              1'b0
+    31      R/W1C   r_GPIO0_31_EVNT_IN_sts                              1'b0
+ */
+typedef union _PLATFORM_REG_GPIO_0_EVNT_STS_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t r_GPIO0_0_EVNT_IN_sts: 1;
+        uint32_t r_GPIO0_1_EVNT_IN_sts: 1;
+        uint32_t r_GPIO0_2_EVNT_IN_sts: 1;
+        uint32_t r_GPIO0_3_EVNT_IN_sts: 1;
+        uint32_t r_GPIO0_4_EVNT_IN_sts: 1;
+        uint32_t r_GPIO0_5_EVNT_IN_sts: 1;
+        uint32_t r_GPIO0_6_EVNT_IN_sts: 1;
+        uint32_t r_GPIO0_7_EVNT_IN_sts: 1;
+        uint32_t r_GPIO0_8_EVNT_IN_sts: 1;
+        uint32_t r_GPIO0_9_EVNT_IN_sts: 1;
+        uint32_t r_GPIO0_10_EVNT_IN_sts: 1;
+        uint32_t r_GPIO0_11_EVNT_IN_sts: 1;
+        uint32_t r_GPIO0_12_EVNT_IN_sts: 1;
+        uint32_t r_GPIO0_13_EVNT_IN_sts: 1;
+        uint32_t r_GPIO0_14_EVNT_IN_sts: 1;
+        uint32_t r_GPIO0_15_EVNT_IN_sts: 1;
+        uint32_t r_GPIO0_16_EVNT_IN_sts: 1;
+        uint32_t r_GPIO0_17_EVNT_IN_sts: 1;
+        uint32_t r_GPIO0_18_EVNT_IN_sts: 1;
+        uint32_t r_GPIO0_19_EVNT_IN_sts: 1;
+        uint32_t r_GPIO0_20_EVNT_IN_sts: 1;
+        uint32_t r_GPIO0_21_EVNT_IN_sts: 1;
+        uint32_t r_GPIO0_22_EVNT_IN_sts: 1;
+        uint32_t r_GPIO0_23_EVNT_IN_sts: 1;
+        uint32_t r_GPIO0_24_EVNT_IN_sts: 1;
+        uint32_t r_GPIO0_25_EVNT_IN_sts: 1;
+        uint32_t r_GPIO0_26_EVNT_IN_sts: 1;
+        uint32_t r_GPIO0_27_EVNT_IN_sts: 1;
+        uint32_t r_GPIO0_28_EVNT_IN_sts: 1;
+        uint32_t r_GPIO0_29_EVNT_IN_sts: 1;
+        uint32_t r_GPIO0_30_EVNT_IN_sts: 1;
+        uint32_t r_GPIO0_31_EVNT_IN_sts: 1;
+    };
+} PLATFORM_REG_GPIO_0_EVNT_STS_TYPE;
+
+/*0x4000_62fc PLATFORM_REG_GPIO_0_EVNT_STS*/
+#define PLATFORM_REG_GPIO_0_EVNT_STS_r_GPIO0_0_EVNT_IN_sts_Pos                                               0U
+#define PLATFORM_REG_GPIO_0_EVNT_STS_r_GPIO0_0_EVNT_IN_sts_Msk                                               (0x1UL << PLATFORM_REG_GPIO_0_EVNT_STS_r_GPIO0_0_EVNT_IN_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_EVNT_STS_r_GPIO0_1_EVNT_IN_sts_Pos                                               1U
+#define PLATFORM_REG_GPIO_0_EVNT_STS_r_GPIO0_1_EVNT_IN_sts_Msk                                               (0x1UL << PLATFORM_REG_GPIO_0_EVNT_STS_r_GPIO0_1_EVNT_IN_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_EVNT_STS_r_GPIO0_2_EVNT_IN_sts_Pos                                               2U
+#define PLATFORM_REG_GPIO_0_EVNT_STS_r_GPIO0_2_EVNT_IN_sts_Msk                                               (0x1UL << PLATFORM_REG_GPIO_0_EVNT_STS_r_GPIO0_2_EVNT_IN_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_EVNT_STS_r_GPIO0_3_EVNT_IN_sts_Pos                                               3U
+#define PLATFORM_REG_GPIO_0_EVNT_STS_r_GPIO0_3_EVNT_IN_sts_Msk                                               (0x1UL << PLATFORM_REG_GPIO_0_EVNT_STS_r_GPIO0_3_EVNT_IN_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_EVNT_STS_r_GPIO0_4_EVNT_IN_sts_Pos                                               4U
+#define PLATFORM_REG_GPIO_0_EVNT_STS_r_GPIO0_4_EVNT_IN_sts_Msk                                               (0x1UL << PLATFORM_REG_GPIO_0_EVNT_STS_r_GPIO0_4_EVNT_IN_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_EVNT_STS_r_GPIO0_5_EVNT_IN_sts_Pos                                               5U
+#define PLATFORM_REG_GPIO_0_EVNT_STS_r_GPIO0_5_EVNT_IN_sts_Msk                                               (0x1UL << PLATFORM_REG_GPIO_0_EVNT_STS_r_GPIO0_5_EVNT_IN_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_EVNT_STS_r_GPIO0_6_EVNT_IN_sts_Pos                                               6U
+#define PLATFORM_REG_GPIO_0_EVNT_STS_r_GPIO0_6_EVNT_IN_sts_Msk                                               (0x1UL << PLATFORM_REG_GPIO_0_EVNT_STS_r_GPIO0_6_EVNT_IN_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_EVNT_STS_r_GPIO0_7_EVNT_IN_sts_Pos                                               7U
+#define PLATFORM_REG_GPIO_0_EVNT_STS_r_GPIO0_7_EVNT_IN_sts_Msk                                               (0x1UL << PLATFORM_REG_GPIO_0_EVNT_STS_r_GPIO0_7_EVNT_IN_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_EVNT_STS_r_GPIO0_8_EVNT_IN_sts_Pos                                               8U
+#define PLATFORM_REG_GPIO_0_EVNT_STS_r_GPIO0_8_EVNT_IN_sts_Msk                                               (0x1UL << PLATFORM_REG_GPIO_0_EVNT_STS_r_GPIO0_8_EVNT_IN_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_EVNT_STS_r_GPIO0_9_EVNT_IN_sts_Pos                                               9U
+#define PLATFORM_REG_GPIO_0_EVNT_STS_r_GPIO0_9_EVNT_IN_sts_Msk                                               (0x1UL << PLATFORM_REG_GPIO_0_EVNT_STS_r_GPIO0_9_EVNT_IN_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_EVNT_STS_r_GPIO0_10_EVNT_IN_sts_Pos                                              10U
+#define PLATFORM_REG_GPIO_0_EVNT_STS_r_GPIO0_10_EVNT_IN_sts_Msk                                              (0x1UL << PLATFORM_REG_GPIO_0_EVNT_STS_r_GPIO0_10_EVNT_IN_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_EVNT_STS_r_GPIO0_11_EVNT_IN_sts_Pos                                              11U
+#define PLATFORM_REG_GPIO_0_EVNT_STS_r_GPIO0_11_EVNT_IN_sts_Msk                                              (0x1UL << PLATFORM_REG_GPIO_0_EVNT_STS_r_GPIO0_11_EVNT_IN_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_EVNT_STS_r_GPIO0_12_EVNT_IN_sts_Pos                                              12U
+#define PLATFORM_REG_GPIO_0_EVNT_STS_r_GPIO0_12_EVNT_IN_sts_Msk                                              (0x1UL << PLATFORM_REG_GPIO_0_EVNT_STS_r_GPIO0_12_EVNT_IN_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_EVNT_STS_r_GPIO0_13_EVNT_IN_sts_Pos                                              13U
+#define PLATFORM_REG_GPIO_0_EVNT_STS_r_GPIO0_13_EVNT_IN_sts_Msk                                              (0x1UL << PLATFORM_REG_GPIO_0_EVNT_STS_r_GPIO0_13_EVNT_IN_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_EVNT_STS_r_GPIO0_14_EVNT_IN_sts_Pos                                              14U
+#define PLATFORM_REG_GPIO_0_EVNT_STS_r_GPIO0_14_EVNT_IN_sts_Msk                                              (0x1UL << PLATFORM_REG_GPIO_0_EVNT_STS_r_GPIO0_14_EVNT_IN_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_EVNT_STS_r_GPIO0_15_EVNT_IN_sts_Pos                                              15U
+#define PLATFORM_REG_GPIO_0_EVNT_STS_r_GPIO0_15_EVNT_IN_sts_Msk                                              (0x1UL << PLATFORM_REG_GPIO_0_EVNT_STS_r_GPIO0_15_EVNT_IN_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_EVNT_STS_r_GPIO0_16_EVNT_IN_sts_Pos                                              16U
+#define PLATFORM_REG_GPIO_0_EVNT_STS_r_GPIO0_16_EVNT_IN_sts_Msk                                              (0x1UL << PLATFORM_REG_GPIO_0_EVNT_STS_r_GPIO0_16_EVNT_IN_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_EVNT_STS_r_GPIO0_17_EVNT_IN_sts_Pos                                              17U
+#define PLATFORM_REG_GPIO_0_EVNT_STS_r_GPIO0_17_EVNT_IN_sts_Msk                                              (0x1UL << PLATFORM_REG_GPIO_0_EVNT_STS_r_GPIO0_17_EVNT_IN_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_EVNT_STS_r_GPIO0_18_EVNT_IN_sts_Pos                                              18U
+#define PLATFORM_REG_GPIO_0_EVNT_STS_r_GPIO0_18_EVNT_IN_sts_Msk                                              (0x1UL << PLATFORM_REG_GPIO_0_EVNT_STS_r_GPIO0_18_EVNT_IN_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_EVNT_STS_r_GPIO0_19_EVNT_IN_sts_Pos                                              19U
+#define PLATFORM_REG_GPIO_0_EVNT_STS_r_GPIO0_19_EVNT_IN_sts_Msk                                              (0x1UL << PLATFORM_REG_GPIO_0_EVNT_STS_r_GPIO0_19_EVNT_IN_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_EVNT_STS_r_GPIO0_20_EVNT_IN_sts_Pos                                              20U
+#define PLATFORM_REG_GPIO_0_EVNT_STS_r_GPIO0_20_EVNT_IN_sts_Msk                                              (0x1UL << PLATFORM_REG_GPIO_0_EVNT_STS_r_GPIO0_20_EVNT_IN_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_EVNT_STS_r_GPIO0_21_EVNT_IN_sts_Pos                                              21U
+#define PLATFORM_REG_GPIO_0_EVNT_STS_r_GPIO0_21_EVNT_IN_sts_Msk                                              (0x1UL << PLATFORM_REG_GPIO_0_EVNT_STS_r_GPIO0_21_EVNT_IN_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_EVNT_STS_r_GPIO0_22_EVNT_IN_sts_Pos                                              22U
+#define PLATFORM_REG_GPIO_0_EVNT_STS_r_GPIO0_22_EVNT_IN_sts_Msk                                              (0x1UL << PLATFORM_REG_GPIO_0_EVNT_STS_r_GPIO0_22_EVNT_IN_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_EVNT_STS_r_GPIO0_23_EVNT_IN_sts_Pos                                              23U
+#define PLATFORM_REG_GPIO_0_EVNT_STS_r_GPIO0_23_EVNT_IN_sts_Msk                                              (0x1UL << PLATFORM_REG_GPIO_0_EVNT_STS_r_GPIO0_23_EVNT_IN_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_EVNT_STS_r_GPIO0_24_EVNT_IN_sts_Pos                                              24U
+#define PLATFORM_REG_GPIO_0_EVNT_STS_r_GPIO0_24_EVNT_IN_sts_Msk                                              (0x1UL << PLATFORM_REG_GPIO_0_EVNT_STS_r_GPIO0_24_EVNT_IN_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_EVNT_STS_r_GPIO0_25_EVNT_IN_sts_Pos                                              25U
+#define PLATFORM_REG_GPIO_0_EVNT_STS_r_GPIO0_25_EVNT_IN_sts_Msk                                              (0x1UL << PLATFORM_REG_GPIO_0_EVNT_STS_r_GPIO0_25_EVNT_IN_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_EVNT_STS_r_GPIO0_26_EVNT_IN_sts_Pos                                              26U
+#define PLATFORM_REG_GPIO_0_EVNT_STS_r_GPIO0_26_EVNT_IN_sts_Msk                                              (0x1UL << PLATFORM_REG_GPIO_0_EVNT_STS_r_GPIO0_26_EVNT_IN_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_EVNT_STS_r_GPIO0_27_EVNT_IN_sts_Pos                                              27U
+#define PLATFORM_REG_GPIO_0_EVNT_STS_r_GPIO0_27_EVNT_IN_sts_Msk                                              (0x1UL << PLATFORM_REG_GPIO_0_EVNT_STS_r_GPIO0_27_EVNT_IN_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_EVNT_STS_r_GPIO0_28_EVNT_IN_sts_Pos                                              28U
+#define PLATFORM_REG_GPIO_0_EVNT_STS_r_GPIO0_28_EVNT_IN_sts_Msk                                              (0x1UL << PLATFORM_REG_GPIO_0_EVNT_STS_r_GPIO0_28_EVNT_IN_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_EVNT_STS_r_GPIO0_29_EVNT_IN_sts_Pos                                              29U
+#define PLATFORM_REG_GPIO_0_EVNT_STS_r_GPIO0_29_EVNT_IN_sts_Msk                                              (0x1UL << PLATFORM_REG_GPIO_0_EVNT_STS_r_GPIO0_29_EVNT_IN_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_EVNT_STS_r_GPIO0_30_EVNT_IN_sts_Pos                                              30U
+#define PLATFORM_REG_GPIO_0_EVNT_STS_r_GPIO0_30_EVNT_IN_sts_Msk                                              (0x1UL << PLATFORM_REG_GPIO_0_EVNT_STS_r_GPIO0_30_EVNT_IN_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_EVNT_STS_r_GPIO0_31_EVNT_IN_sts_Pos                                              31U
+#define PLATFORM_REG_GPIO_0_EVNT_STS_r_GPIO0_31_EVNT_IN_sts_Msk                                              (0x1UL << PLATFORM_REG_GPIO_0_EVNT_STS_r_GPIO0_31_EVNT_IN_sts_Pos)
+
+/* 0x0300   0x4000_6300
+    0       R/W1C   r_GPIO0_32_EVNT_IN_sts                              1'b0
+    1       R/W1C   r_GPIO0_33_EVNT_IN_sts                              1'b0
+    2       R/W1C   r_GPIO0_34_EVNT_IN_sts                              1'b0
+    3       R/W1C   r_GPIO0_35_EVNT_IN_sts                              1'b0
+    4       R/W1C   r_GPIO0_36_EVNT_IN_sts                              1'b0
+    5       R/W1C   r_GPIO0_37_EVNT_IN_sts                              1'b0
+    6       R/W1C   r_GPIO0_38_EVNT_IN_sts                              1'b0
+    7       R/W1C   r_GPIO0_39_EVNT_IN_sts                              1'b0
+    8       R/W1C   r_GPIO0_40_EVNT_IN_sts                              1'b0
+    9       R/W1C   r_GPIO0_41_EVNT_IN_sts                              1'b0
+    10      R/W1C   r_GPIO0_42_EVNT_IN_sts                              1'b0
+    11      R/W1C   r_GPIO0_43_EVNT_IN_sts                              1'b0
+    12      R/W1C   r_GPIO0_44_EVNT_IN_sts                              1'b0
+    13      R/W1C   r_GPIO0_45_EVNT_IN_sts                              1'b0
+    14      R/W1C   r_GPIO0_46_EVNT_IN_sts                              1'b0
+    15      R/W1C   r_GPIO0_47_EVNT_IN_sts                              1'b0
+    16      R/W1C   r_GPIO0_48_EVNT_IN_sts                              1'b0
+    17      R/W1C   r_GPIO0_49_EVNT_IN_sts                              1'b0
+    31:18   R       reserved                                            14'h0000
+ */
+typedef union _PLATFORM_REG_GPIO_1_EVENT_STS_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t r_GPIO0_32_EVNT_IN_sts: 1;
+        uint32_t r_GPIO0_33_EVNT_IN_sts: 1;
+        uint32_t r_GPIO0_34_EVNT_IN_sts: 1;
+        uint32_t r_GPIO0_35_EVNT_IN_sts: 1;
+        uint32_t r_GPIO0_36_EVNT_IN_sts: 1;
+        uint32_t r_GPIO0_37_EVNT_IN_sts: 1;
+        uint32_t r_GPIO0_38_EVNT_IN_sts: 1;
+        uint32_t r_GPIO0_39_EVNT_IN_sts: 1;
+        uint32_t r_GPIO0_40_EVNT_IN_sts: 1;
+        uint32_t r_GPIO0_41_EVNT_IN_sts: 1;
+        uint32_t r_GPIO0_42_EVNT_IN_sts: 1;
+        uint32_t r_GPIO0_43_EVNT_IN_sts: 1;
+        uint32_t r_GPIO0_44_EVNT_IN_sts: 1;
+        uint32_t r_GPIO0_45_EVNT_IN_sts: 1;
+        uint32_t r_GPIO0_46_EVNT_IN_sts: 1;
+        uint32_t r_GPIO0_47_EVNT_IN_sts: 1;
+        uint32_t r_GPIO0_48_EVNT_IN_sts: 1;
+        uint32_t r_GPIO0_49_EVNT_IN_sts: 1;
+        uint32_t reserved: 14;
+    };
+} PLATFORM_REG_GPIO_1_EVENT_STS_TYPE;
+
+/*0x4000_6300 PLATFORM_REG_GPIO_1_EVENT_STS*/
+#define PLATFORM_REG_GPIO_1_EVENT_STS_r_GPIO0_32_EVNT_IN_sts_Pos                                             0U
+#define PLATFORM_REG_GPIO_1_EVENT_STS_r_GPIO0_32_EVNT_IN_sts_Msk                                             (0x1UL << PLATFORM_REG_GPIO_1_EVENT_STS_r_GPIO0_32_EVNT_IN_sts_Pos)
+
+#define PLATFORM_REG_GPIO_1_EVENT_STS_r_GPIO0_33_EVNT_IN_sts_Pos                                             1U
+#define PLATFORM_REG_GPIO_1_EVENT_STS_r_GPIO0_33_EVNT_IN_sts_Msk                                             (0x1UL << PLATFORM_REG_GPIO_1_EVENT_STS_r_GPIO0_33_EVNT_IN_sts_Pos)
+
+#define PLATFORM_REG_GPIO_1_EVENT_STS_r_GPIO0_34_EVNT_IN_sts_Pos                                             2U
+#define PLATFORM_REG_GPIO_1_EVENT_STS_r_GPIO0_34_EVNT_IN_sts_Msk                                             (0x1UL << PLATFORM_REG_GPIO_1_EVENT_STS_r_GPIO0_34_EVNT_IN_sts_Pos)
+
+#define PLATFORM_REG_GPIO_1_EVENT_STS_r_GPIO0_35_EVNT_IN_sts_Pos                                             3U
+#define PLATFORM_REG_GPIO_1_EVENT_STS_r_GPIO0_35_EVNT_IN_sts_Msk                                             (0x1UL << PLATFORM_REG_GPIO_1_EVENT_STS_r_GPIO0_35_EVNT_IN_sts_Pos)
+
+#define PLATFORM_REG_GPIO_1_EVENT_STS_r_GPIO0_36_EVNT_IN_sts_Pos                                             4U
+#define PLATFORM_REG_GPIO_1_EVENT_STS_r_GPIO0_36_EVNT_IN_sts_Msk                                             (0x1UL << PLATFORM_REG_GPIO_1_EVENT_STS_r_GPIO0_36_EVNT_IN_sts_Pos)
+
+#define PLATFORM_REG_GPIO_1_EVENT_STS_r_GPIO0_37_EVNT_IN_sts_Pos                                             5U
+#define PLATFORM_REG_GPIO_1_EVENT_STS_r_GPIO0_37_EVNT_IN_sts_Msk                                             (0x1UL << PLATFORM_REG_GPIO_1_EVENT_STS_r_GPIO0_37_EVNT_IN_sts_Pos)
+
+#define PLATFORM_REG_GPIO_1_EVENT_STS_r_GPIO0_38_EVNT_IN_sts_Pos                                             6U
+#define PLATFORM_REG_GPIO_1_EVENT_STS_r_GPIO0_38_EVNT_IN_sts_Msk                                             (0x1UL << PLATFORM_REG_GPIO_1_EVENT_STS_r_GPIO0_38_EVNT_IN_sts_Pos)
+
+#define PLATFORM_REG_GPIO_1_EVENT_STS_r_GPIO0_39_EVNT_IN_sts_Pos                                             7U
+#define PLATFORM_REG_GPIO_1_EVENT_STS_r_GPIO0_39_EVNT_IN_sts_Msk                                             (0x1UL << PLATFORM_REG_GPIO_1_EVENT_STS_r_GPIO0_39_EVNT_IN_sts_Pos)
+
+#define PLATFORM_REG_GPIO_1_EVENT_STS_r_GPIO0_40_EVNT_IN_sts_Pos                                             8U
+#define PLATFORM_REG_GPIO_1_EVENT_STS_r_GPIO0_40_EVNT_IN_sts_Msk                                             (0x1UL << PLATFORM_REG_GPIO_1_EVENT_STS_r_GPIO0_40_EVNT_IN_sts_Pos)
+
+#define PLATFORM_REG_GPIO_1_EVENT_STS_r_GPIO0_41_EVNT_IN_sts_Pos                                             9U
+#define PLATFORM_REG_GPIO_1_EVENT_STS_r_GPIO0_41_EVNT_IN_sts_Msk                                             (0x1UL << PLATFORM_REG_GPIO_1_EVENT_STS_r_GPIO0_41_EVNT_IN_sts_Pos)
+
+#define PLATFORM_REG_GPIO_1_EVENT_STS_r_GPIO0_42_EVNT_IN_sts_Pos                                             10U
+#define PLATFORM_REG_GPIO_1_EVENT_STS_r_GPIO0_42_EVNT_IN_sts_Msk                                             (0x1UL << PLATFORM_REG_GPIO_1_EVENT_STS_r_GPIO0_42_EVNT_IN_sts_Pos)
+
+#define PLATFORM_REG_GPIO_1_EVENT_STS_r_GPIO0_43_EVNT_IN_sts_Pos                                             11U
+#define PLATFORM_REG_GPIO_1_EVENT_STS_r_GPIO0_43_EVNT_IN_sts_Msk                                             (0x1UL << PLATFORM_REG_GPIO_1_EVENT_STS_r_GPIO0_43_EVNT_IN_sts_Pos)
+
+#define PLATFORM_REG_GPIO_1_EVENT_STS_r_GPIO0_44_EVNT_IN_sts_Pos                                             12U
+#define PLATFORM_REG_GPIO_1_EVENT_STS_r_GPIO0_44_EVNT_IN_sts_Msk                                             (0x1UL << PLATFORM_REG_GPIO_1_EVENT_STS_r_GPIO0_44_EVNT_IN_sts_Pos)
+
+#define PLATFORM_REG_GPIO_1_EVENT_STS_r_GPIO0_45_EVNT_IN_sts_Pos                                             13U
+#define PLATFORM_REG_GPIO_1_EVENT_STS_r_GPIO0_45_EVNT_IN_sts_Msk                                             (0x1UL << PLATFORM_REG_GPIO_1_EVENT_STS_r_GPIO0_45_EVNT_IN_sts_Pos)
+
+#define PLATFORM_REG_GPIO_1_EVENT_STS_r_GPIO0_46_EVNT_IN_sts_Pos                                             14U
+#define PLATFORM_REG_GPIO_1_EVENT_STS_r_GPIO0_46_EVNT_IN_sts_Msk                                             (0x1UL << PLATFORM_REG_GPIO_1_EVENT_STS_r_GPIO0_46_EVNT_IN_sts_Pos)
+
+#define PLATFORM_REG_GPIO_1_EVENT_STS_r_GPIO0_47_EVNT_IN_sts_Pos                                             15U
+#define PLATFORM_REG_GPIO_1_EVENT_STS_r_GPIO0_47_EVNT_IN_sts_Msk                                             (0x1UL << PLATFORM_REG_GPIO_1_EVENT_STS_r_GPIO0_47_EVNT_IN_sts_Pos)
+
+#define PLATFORM_REG_GPIO_1_EVENT_STS_r_GPIO0_48_EVNT_IN_sts_Pos                                             16U
+#define PLATFORM_REG_GPIO_1_EVENT_STS_r_GPIO0_48_EVNT_IN_sts_Msk                                             (0x1UL << PLATFORM_REG_GPIO_1_EVENT_STS_r_GPIO0_48_EVNT_IN_sts_Pos)
+
+#define PLATFORM_REG_GPIO_1_EVENT_STS_r_GPIO0_49_EVNT_IN_sts_Pos                                             17U
+#define PLATFORM_REG_GPIO_1_EVENT_STS_r_GPIO0_49_EVNT_IN_sts_Msk                                             (0x1UL << PLATFORM_REG_GPIO_1_EVENT_STS_r_GPIO0_49_EVNT_IN_sts_Pos)
+
+#define PLATFORM_REG_GPIO_1_EVENT_STS_reserved_Pos                                                           18U
+#define PLATFORM_REG_GPIO_1_EVENT_STS_reserved_Msk                                                           (0x3FFFUL << PLATFORM_REG_GPIO_1_EVENT_STS_reserved_Pos)
+
+/* 0x0314   0x4000_6314
+    0       R/W1C   r_GPIO0_0_TASK_DRCLR_sts                            1'b0
+    1       R/W1C   r_GPIO0_1_TASK_DRCLR_sts                            1'b0
+    2       R/W1C   r_GPIO0_2_TASK_DRCLR_sts                            1'b0
+    3       R/W1C   r_GPIO0_3_TASK_DRCLR_sts                            1'b0
+    4       R/W1C   r_GPIO0_4_TASK_DRCLR_sts                            1'b0
+    5       R/W1C   r_GPIO0_5_TASK_DRCLR_sts                            1'b0
+    6       R/W1C   r_GPIO0_6_TASK_DRCLR_sts                            1'b0
+    7       R/W1C   r_GPIO0_7_TASK_DRCLR_sts                            1'b0
+    8       R/W1C   r_GPIO0_8_TASK_DRCLR_sts                            1'b0
+    9       R/W1C   r_GPIO0_9_TASK_DRCLR_sts                            1'b0
+    10      R/W1C   r_GPIO0_10_TASK_DRCLR_sts                           1'b0
+    11      R/W1C   r_GPIO0_11_TASK_DRCLR_sts                           1'b0
+    12      R/W1C   r_GPIO0_12_TASK_DRCLR_sts                           1'b0
+    13      R/W1C   r_GPIO0_13_TASK_DRCLR_sts                           1'b0
+    14      R/W1C   r_GPIO0_14_TASK_DRCLR_sts                           1'b0
+    15      R/W1C   r_GPIO0_15_TASK_DRCLR_sts                           1'b0
+    16      R/W1C   r_GPIO0_16_TASK_DRCLR_sts                           1'b0
+    17      R/W1C   r_GPIO0_17_TASK_DRCLR_sts                           1'b0
+    18      R/W1C   r_GPIO0_18_TASK_DRCLR_sts                           1'b0
+    19      R/W1C   r_GPIO0_19_TASK_DRCLR_sts                           1'b0
+    20      R/W1C   r_GPIO0_20_TASK_DRCLR_sts                           1'b0
+    21      R/W1C   r_GPIO0_21_TASK_DRCLR_sts                           1'b0
+    22      R/W1C   r_GPIO0_22_TASK_DRCLR_sts                           1'b0
+    23      R/W1C   r_GPIO0_23_TASK_DRCLR_sts                           1'b0
+    24      R/W1C   r_GPIO0_24_TASK_DRCLR_sts                           1'b0
+    25      R/W1C   r_GPIO0_25_TASK_DRCLR_sts                           1'b0
+    26      R/W1C   r_GPIO0_26_TASK_DRCLR_sts                           1'b0
+    27      R/W1C   r_GPIO0_27_TASK_DRCLR_sts                           1'b0
+    28      R/W1C   r_GPIO0_28_TASK_DRCLR_sts                           1'b0
+    29      R/W1C   r_GPIO0_29_TASK_DRCLR_sts                           1'b0
+    30      R/W1C   r_GPIO0_30_TASK_DRCLR_sts                           1'b0
+    31      R/W1C   r_GPIO0_31_TASK_DRCLR_sts                           1'b0
+ */
+typedef union _PLATFORM_REG_GPIO_0_TASK_DRCLR_STS_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t r_GPIO0_0_TASK_DRCLR_sts: 1;
+        uint32_t r_GPIO0_1_TASK_DRCLR_sts: 1;
+        uint32_t r_GPIO0_2_TASK_DRCLR_sts: 1;
+        uint32_t r_GPIO0_3_TASK_DRCLR_sts: 1;
+        uint32_t r_GPIO0_4_TASK_DRCLR_sts: 1;
+        uint32_t r_GPIO0_5_TASK_DRCLR_sts: 1;
+        uint32_t r_GPIO0_6_TASK_DRCLR_sts: 1;
+        uint32_t r_GPIO0_7_TASK_DRCLR_sts: 1;
+        uint32_t r_GPIO0_8_TASK_DRCLR_sts: 1;
+        uint32_t r_GPIO0_9_TASK_DRCLR_sts: 1;
+        uint32_t r_GPIO0_10_TASK_DRCLR_sts: 1;
+        uint32_t r_GPIO0_11_TASK_DRCLR_sts: 1;
+        uint32_t r_GPIO0_12_TASK_DRCLR_sts: 1;
+        uint32_t r_GPIO0_13_TASK_DRCLR_sts: 1;
+        uint32_t r_GPIO0_14_TASK_DRCLR_sts: 1;
+        uint32_t r_GPIO0_15_TASK_DRCLR_sts: 1;
+        uint32_t r_GPIO0_16_TASK_DRCLR_sts: 1;
+        uint32_t r_GPIO0_17_TASK_DRCLR_sts: 1;
+        uint32_t r_GPIO0_18_TASK_DRCLR_sts: 1;
+        uint32_t r_GPIO0_19_TASK_DRCLR_sts: 1;
+        uint32_t r_GPIO0_20_TASK_DRCLR_sts: 1;
+        uint32_t r_GPIO0_21_TASK_DRCLR_sts: 1;
+        uint32_t r_GPIO0_22_TASK_DRCLR_sts: 1;
+        uint32_t r_GPIO0_23_TASK_DRCLR_sts: 1;
+        uint32_t r_GPIO0_24_TASK_DRCLR_sts: 1;
+        uint32_t r_GPIO0_25_TASK_DRCLR_sts: 1;
+        uint32_t r_GPIO0_26_TASK_DRCLR_sts: 1;
+        uint32_t r_GPIO0_27_TASK_DRCLR_sts: 1;
+        uint32_t r_GPIO0_28_TASK_DRCLR_sts: 1;
+        uint32_t r_GPIO0_29_TASK_DRCLR_sts: 1;
+        uint32_t r_GPIO0_30_TASK_DRCLR_sts: 1;
+        uint32_t r_GPIO0_31_TASK_DRCLR_sts: 1;
+    };
+} PLATFORM_REG_GPIO_0_TASK_DRCLR_STS_TYPE;
+
+/*0x4000_6314 PLATFORM_REG_GPIO_0_TASK_DRCLR_STS*/
+#define PLATFORM_REG_GPIO_0_TASK_DRCLR_STS_r_GPIO0_0_TASK_DRCLR_sts_Pos                                      0U
+#define PLATFORM_REG_GPIO_0_TASK_DRCLR_STS_r_GPIO0_0_TASK_DRCLR_sts_Msk                                      (0x1UL << PLATFORM_REG_GPIO_0_TASK_DRCLR_STS_r_GPIO0_0_TASK_DRCLR_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_TASK_DRCLR_STS_r_GPIO0_1_TASK_DRCLR_sts_Pos                                      1U
+#define PLATFORM_REG_GPIO_0_TASK_DRCLR_STS_r_GPIO0_1_TASK_DRCLR_sts_Msk                                      (0x1UL << PLATFORM_REG_GPIO_0_TASK_DRCLR_STS_r_GPIO0_1_TASK_DRCLR_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_TASK_DRCLR_STS_r_GPIO0_2_TASK_DRCLR_sts_Pos                                      2U
+#define PLATFORM_REG_GPIO_0_TASK_DRCLR_STS_r_GPIO0_2_TASK_DRCLR_sts_Msk                                      (0x1UL << PLATFORM_REG_GPIO_0_TASK_DRCLR_STS_r_GPIO0_2_TASK_DRCLR_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_TASK_DRCLR_STS_r_GPIO0_3_TASK_DRCLR_sts_Pos                                      3U
+#define PLATFORM_REG_GPIO_0_TASK_DRCLR_STS_r_GPIO0_3_TASK_DRCLR_sts_Msk                                      (0x1UL << PLATFORM_REG_GPIO_0_TASK_DRCLR_STS_r_GPIO0_3_TASK_DRCLR_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_TASK_DRCLR_STS_r_GPIO0_4_TASK_DRCLR_sts_Pos                                      4U
+#define PLATFORM_REG_GPIO_0_TASK_DRCLR_STS_r_GPIO0_4_TASK_DRCLR_sts_Msk                                      (0x1UL << PLATFORM_REG_GPIO_0_TASK_DRCLR_STS_r_GPIO0_4_TASK_DRCLR_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_TASK_DRCLR_STS_r_GPIO0_5_TASK_DRCLR_sts_Pos                                      5U
+#define PLATFORM_REG_GPIO_0_TASK_DRCLR_STS_r_GPIO0_5_TASK_DRCLR_sts_Msk                                      (0x1UL << PLATFORM_REG_GPIO_0_TASK_DRCLR_STS_r_GPIO0_5_TASK_DRCLR_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_TASK_DRCLR_STS_r_GPIO0_6_TASK_DRCLR_sts_Pos                                      6U
+#define PLATFORM_REG_GPIO_0_TASK_DRCLR_STS_r_GPIO0_6_TASK_DRCLR_sts_Msk                                      (0x1UL << PLATFORM_REG_GPIO_0_TASK_DRCLR_STS_r_GPIO0_6_TASK_DRCLR_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_TASK_DRCLR_STS_r_GPIO0_7_TASK_DRCLR_sts_Pos                                      7U
+#define PLATFORM_REG_GPIO_0_TASK_DRCLR_STS_r_GPIO0_7_TASK_DRCLR_sts_Msk                                      (0x1UL << PLATFORM_REG_GPIO_0_TASK_DRCLR_STS_r_GPIO0_7_TASK_DRCLR_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_TASK_DRCLR_STS_r_GPIO0_8_TASK_DRCLR_sts_Pos                                      8U
+#define PLATFORM_REG_GPIO_0_TASK_DRCLR_STS_r_GPIO0_8_TASK_DRCLR_sts_Msk                                      (0x1UL << PLATFORM_REG_GPIO_0_TASK_DRCLR_STS_r_GPIO0_8_TASK_DRCLR_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_TASK_DRCLR_STS_r_GPIO0_9_TASK_DRCLR_sts_Pos                                      9U
+#define PLATFORM_REG_GPIO_0_TASK_DRCLR_STS_r_GPIO0_9_TASK_DRCLR_sts_Msk                                      (0x1UL << PLATFORM_REG_GPIO_0_TASK_DRCLR_STS_r_GPIO0_9_TASK_DRCLR_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_TASK_DRCLR_STS_r_GPIO0_10_TASK_DRCLR_sts_Pos                                     10U
+#define PLATFORM_REG_GPIO_0_TASK_DRCLR_STS_r_GPIO0_10_TASK_DRCLR_sts_Msk                                     (0x1UL << PLATFORM_REG_GPIO_0_TASK_DRCLR_STS_r_GPIO0_10_TASK_DRCLR_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_TASK_DRCLR_STS_r_GPIO0_11_TASK_DRCLR_sts_Pos                                     11U
+#define PLATFORM_REG_GPIO_0_TASK_DRCLR_STS_r_GPIO0_11_TASK_DRCLR_sts_Msk                                     (0x1UL << PLATFORM_REG_GPIO_0_TASK_DRCLR_STS_r_GPIO0_11_TASK_DRCLR_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_TASK_DRCLR_STS_r_GPIO0_12_TASK_DRCLR_sts_Pos                                     12U
+#define PLATFORM_REG_GPIO_0_TASK_DRCLR_STS_r_GPIO0_12_TASK_DRCLR_sts_Msk                                     (0x1UL << PLATFORM_REG_GPIO_0_TASK_DRCLR_STS_r_GPIO0_12_TASK_DRCLR_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_TASK_DRCLR_STS_r_GPIO0_13_TASK_DRCLR_sts_Pos                                     13U
+#define PLATFORM_REG_GPIO_0_TASK_DRCLR_STS_r_GPIO0_13_TASK_DRCLR_sts_Msk                                     (0x1UL << PLATFORM_REG_GPIO_0_TASK_DRCLR_STS_r_GPIO0_13_TASK_DRCLR_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_TASK_DRCLR_STS_r_GPIO0_14_TASK_DRCLR_sts_Pos                                     14U
+#define PLATFORM_REG_GPIO_0_TASK_DRCLR_STS_r_GPIO0_14_TASK_DRCLR_sts_Msk                                     (0x1UL << PLATFORM_REG_GPIO_0_TASK_DRCLR_STS_r_GPIO0_14_TASK_DRCLR_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_TASK_DRCLR_STS_r_GPIO0_15_TASK_DRCLR_sts_Pos                                     15U
+#define PLATFORM_REG_GPIO_0_TASK_DRCLR_STS_r_GPIO0_15_TASK_DRCLR_sts_Msk                                     (0x1UL << PLATFORM_REG_GPIO_0_TASK_DRCLR_STS_r_GPIO0_15_TASK_DRCLR_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_TASK_DRCLR_STS_r_GPIO0_16_TASK_DRCLR_sts_Pos                                     16U
+#define PLATFORM_REG_GPIO_0_TASK_DRCLR_STS_r_GPIO0_16_TASK_DRCLR_sts_Msk                                     (0x1UL << PLATFORM_REG_GPIO_0_TASK_DRCLR_STS_r_GPIO0_16_TASK_DRCLR_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_TASK_DRCLR_STS_r_GPIO0_17_TASK_DRCLR_sts_Pos                                     17U
+#define PLATFORM_REG_GPIO_0_TASK_DRCLR_STS_r_GPIO0_17_TASK_DRCLR_sts_Msk                                     (0x1UL << PLATFORM_REG_GPIO_0_TASK_DRCLR_STS_r_GPIO0_17_TASK_DRCLR_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_TASK_DRCLR_STS_r_GPIO0_18_TASK_DRCLR_sts_Pos                                     18U
+#define PLATFORM_REG_GPIO_0_TASK_DRCLR_STS_r_GPIO0_18_TASK_DRCLR_sts_Msk                                     (0x1UL << PLATFORM_REG_GPIO_0_TASK_DRCLR_STS_r_GPIO0_18_TASK_DRCLR_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_TASK_DRCLR_STS_r_GPIO0_19_TASK_DRCLR_sts_Pos                                     19U
+#define PLATFORM_REG_GPIO_0_TASK_DRCLR_STS_r_GPIO0_19_TASK_DRCLR_sts_Msk                                     (0x1UL << PLATFORM_REG_GPIO_0_TASK_DRCLR_STS_r_GPIO0_19_TASK_DRCLR_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_TASK_DRCLR_STS_r_GPIO0_20_TASK_DRCLR_sts_Pos                                     20U
+#define PLATFORM_REG_GPIO_0_TASK_DRCLR_STS_r_GPIO0_20_TASK_DRCLR_sts_Msk                                     (0x1UL << PLATFORM_REG_GPIO_0_TASK_DRCLR_STS_r_GPIO0_20_TASK_DRCLR_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_TASK_DRCLR_STS_r_GPIO0_21_TASK_DRCLR_sts_Pos                                     21U
+#define PLATFORM_REG_GPIO_0_TASK_DRCLR_STS_r_GPIO0_21_TASK_DRCLR_sts_Msk                                     (0x1UL << PLATFORM_REG_GPIO_0_TASK_DRCLR_STS_r_GPIO0_21_TASK_DRCLR_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_TASK_DRCLR_STS_r_GPIO0_22_TASK_DRCLR_sts_Pos                                     22U
+#define PLATFORM_REG_GPIO_0_TASK_DRCLR_STS_r_GPIO0_22_TASK_DRCLR_sts_Msk                                     (0x1UL << PLATFORM_REG_GPIO_0_TASK_DRCLR_STS_r_GPIO0_22_TASK_DRCLR_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_TASK_DRCLR_STS_r_GPIO0_23_TASK_DRCLR_sts_Pos                                     23U
+#define PLATFORM_REG_GPIO_0_TASK_DRCLR_STS_r_GPIO0_23_TASK_DRCLR_sts_Msk                                     (0x1UL << PLATFORM_REG_GPIO_0_TASK_DRCLR_STS_r_GPIO0_23_TASK_DRCLR_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_TASK_DRCLR_STS_r_GPIO0_24_TASK_DRCLR_sts_Pos                                     24U
+#define PLATFORM_REG_GPIO_0_TASK_DRCLR_STS_r_GPIO0_24_TASK_DRCLR_sts_Msk                                     (0x1UL << PLATFORM_REG_GPIO_0_TASK_DRCLR_STS_r_GPIO0_24_TASK_DRCLR_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_TASK_DRCLR_STS_r_GPIO0_25_TASK_DRCLR_sts_Pos                                     25U
+#define PLATFORM_REG_GPIO_0_TASK_DRCLR_STS_r_GPIO0_25_TASK_DRCLR_sts_Msk                                     (0x1UL << PLATFORM_REG_GPIO_0_TASK_DRCLR_STS_r_GPIO0_25_TASK_DRCLR_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_TASK_DRCLR_STS_r_GPIO0_26_TASK_DRCLR_sts_Pos                                     26U
+#define PLATFORM_REG_GPIO_0_TASK_DRCLR_STS_r_GPIO0_26_TASK_DRCLR_sts_Msk                                     (0x1UL << PLATFORM_REG_GPIO_0_TASK_DRCLR_STS_r_GPIO0_26_TASK_DRCLR_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_TASK_DRCLR_STS_r_GPIO0_27_TASK_DRCLR_sts_Pos                                     27U
+#define PLATFORM_REG_GPIO_0_TASK_DRCLR_STS_r_GPIO0_27_TASK_DRCLR_sts_Msk                                     (0x1UL << PLATFORM_REG_GPIO_0_TASK_DRCLR_STS_r_GPIO0_27_TASK_DRCLR_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_TASK_DRCLR_STS_r_GPIO0_28_TASK_DRCLR_sts_Pos                                     28U
+#define PLATFORM_REG_GPIO_0_TASK_DRCLR_STS_r_GPIO0_28_TASK_DRCLR_sts_Msk                                     (0x1UL << PLATFORM_REG_GPIO_0_TASK_DRCLR_STS_r_GPIO0_28_TASK_DRCLR_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_TASK_DRCLR_STS_r_GPIO0_29_TASK_DRCLR_sts_Pos                                     29U
+#define PLATFORM_REG_GPIO_0_TASK_DRCLR_STS_r_GPIO0_29_TASK_DRCLR_sts_Msk                                     (0x1UL << PLATFORM_REG_GPIO_0_TASK_DRCLR_STS_r_GPIO0_29_TASK_DRCLR_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_TASK_DRCLR_STS_r_GPIO0_30_TASK_DRCLR_sts_Pos                                     30U
+#define PLATFORM_REG_GPIO_0_TASK_DRCLR_STS_r_GPIO0_30_TASK_DRCLR_sts_Msk                                     (0x1UL << PLATFORM_REG_GPIO_0_TASK_DRCLR_STS_r_GPIO0_30_TASK_DRCLR_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_TASK_DRCLR_STS_r_GPIO0_31_TASK_DRCLR_sts_Pos                                     31U
+#define PLATFORM_REG_GPIO_0_TASK_DRCLR_STS_r_GPIO0_31_TASK_DRCLR_sts_Msk                                     (0x1UL << PLATFORM_REG_GPIO_0_TASK_DRCLR_STS_r_GPIO0_31_TASK_DRCLR_sts_Pos)
+
+/* 0x0318   0x4000_6318
+    0       R/W1C   r_GPIO0_32_TASK_DRCLR_sts                           1'b0
+    1       R/W1C   r_GPIO0_33_TASK_DRCLR_sts                           1'b0
+    2       R/W1C   r_GPIO0_34_TASK_DRCLR_sts                           1'b0
+    3       R/W1C   r_GPIO0_35_TASK_DRCLR_sts                           1'b0
+    4       R/W1C   r_GPIO0_36_TASK_DRCLR_sts                           1'b0
+    5       R/W1C   r_GPIO0_37_TASK_DRCLR_sts                           1'b0
+    6       R/W1C   r_GPIO0_38_TASK_DRCLR_sts                           1'b0
+    7       R/W1C   r_GPIO0_39_TASK_DRCLR_sts                           1'b0
+    8       R/W1C   r_GPIO0_40_TASK_DRCLR_sts                           1'b0
+    9       R/W1C   r_GPIO0_41_TASK_DRCLR_sts                           1'b0
+    10      R/W1C   r_GPIO0_42_TASK_DRCLR_sts                           1'b0
+    11      R/W1C   r_GPIO0_43_TASK_DRCLR_sts                           1'b0
+    12      R/W1C   r_GPIO0_44_TASK_DRCLR_sts                           1'b0
+    13      R/W1C   r_GPIO0_45_TASK_DRCLR_sts                           1'b0
+    14      R/W1C   r_GPIO0_46_TASK_DRCLR_sts                           1'b0
+    15      R/W1C   r_GPIO0_47_TASK_DRCLR_sts                           1'b0
+    16      R/W1C   r_GPIO0_48_TASK_DRCLR_sts                           1'b0
+    17      R/W1C   r_GPIO0_49_TASK_DRCLR_sts                           1'b0
+    31:18   R       reserved                                            14'h0000
+ */
+typedef union _PLATFORM_REG_GPIO_1_TASK_DRCLR_STS_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t r_GPIO0_32_TASK_DRCLR_sts: 1;
+        uint32_t r_GPIO0_33_TASK_DRCLR_sts: 1;
+        uint32_t r_GPIO0_34_TASK_DRCLR_sts: 1;
+        uint32_t r_GPIO0_35_TASK_DRCLR_sts: 1;
+        uint32_t r_GPIO0_36_TASK_DRCLR_sts: 1;
+        uint32_t r_GPIO0_37_TASK_DRCLR_sts: 1;
+        uint32_t r_GPIO0_38_TASK_DRCLR_sts: 1;
+        uint32_t r_GPIO0_39_TASK_DRCLR_sts: 1;
+        uint32_t r_GPIO0_40_TASK_DRCLR_sts: 1;
+        uint32_t r_GPIO0_41_TASK_DRCLR_sts: 1;
+        uint32_t r_GPIO0_42_TASK_DRCLR_sts: 1;
+        uint32_t r_GPIO0_43_TASK_DRCLR_sts: 1;
+        uint32_t r_GPIO0_44_TASK_DRCLR_sts: 1;
+        uint32_t r_GPIO0_45_TASK_DRCLR_sts: 1;
+        uint32_t r_GPIO0_46_TASK_DRCLR_sts: 1;
+        uint32_t r_GPIO0_47_TASK_DRCLR_sts: 1;
+        uint32_t r_GPIO0_48_TASK_DRCLR_sts: 1;
+        uint32_t r_GPIO0_49_TASK_DRCLR_sts: 1;
+        uint32_t reserved: 14;
+    };
+} PLATFORM_REG_GPIO_1_TASK_DRCLR_STS_TYPE;
+
+/*0x4000_6318 PLATFORM_REG_GPIO_1_TASK_DRCLR_STS*/
+#define PLATFORM_REG_GPIO_1_TASK_DRCLR_STS_r_GPIO0_32_TASK_DRCLR_sts_Pos                                     0U
+#define PLATFORM_REG_GPIO_1_TASK_DRCLR_STS_r_GPIO0_32_TASK_DRCLR_sts_Msk                                     (0x1UL << PLATFORM_REG_GPIO_1_TASK_DRCLR_STS_r_GPIO0_32_TASK_DRCLR_sts_Pos)
+
+#define PLATFORM_REG_GPIO_1_TASK_DRCLR_STS_r_GPIO0_33_TASK_DRCLR_sts_Pos                                     1U
+#define PLATFORM_REG_GPIO_1_TASK_DRCLR_STS_r_GPIO0_33_TASK_DRCLR_sts_Msk                                     (0x1UL << PLATFORM_REG_GPIO_1_TASK_DRCLR_STS_r_GPIO0_33_TASK_DRCLR_sts_Pos)
+
+#define PLATFORM_REG_GPIO_1_TASK_DRCLR_STS_r_GPIO0_34_TASK_DRCLR_sts_Pos                                     2U
+#define PLATFORM_REG_GPIO_1_TASK_DRCLR_STS_r_GPIO0_34_TASK_DRCLR_sts_Msk                                     (0x1UL << PLATFORM_REG_GPIO_1_TASK_DRCLR_STS_r_GPIO0_34_TASK_DRCLR_sts_Pos)
+
+#define PLATFORM_REG_GPIO_1_TASK_DRCLR_STS_r_GPIO0_35_TASK_DRCLR_sts_Pos                                     3U
+#define PLATFORM_REG_GPIO_1_TASK_DRCLR_STS_r_GPIO0_35_TASK_DRCLR_sts_Msk                                     (0x1UL << PLATFORM_REG_GPIO_1_TASK_DRCLR_STS_r_GPIO0_35_TASK_DRCLR_sts_Pos)
+
+#define PLATFORM_REG_GPIO_1_TASK_DRCLR_STS_r_GPIO0_36_TASK_DRCLR_sts_Pos                                     4U
+#define PLATFORM_REG_GPIO_1_TASK_DRCLR_STS_r_GPIO0_36_TASK_DRCLR_sts_Msk                                     (0x1UL << PLATFORM_REG_GPIO_1_TASK_DRCLR_STS_r_GPIO0_36_TASK_DRCLR_sts_Pos)
+
+#define PLATFORM_REG_GPIO_1_TASK_DRCLR_STS_r_GPIO0_37_TASK_DRCLR_sts_Pos                                     5U
+#define PLATFORM_REG_GPIO_1_TASK_DRCLR_STS_r_GPIO0_37_TASK_DRCLR_sts_Msk                                     (0x1UL << PLATFORM_REG_GPIO_1_TASK_DRCLR_STS_r_GPIO0_37_TASK_DRCLR_sts_Pos)
+
+#define PLATFORM_REG_GPIO_1_TASK_DRCLR_STS_r_GPIO0_38_TASK_DRCLR_sts_Pos                                     6U
+#define PLATFORM_REG_GPIO_1_TASK_DRCLR_STS_r_GPIO0_38_TASK_DRCLR_sts_Msk                                     (0x1UL << PLATFORM_REG_GPIO_1_TASK_DRCLR_STS_r_GPIO0_38_TASK_DRCLR_sts_Pos)
+
+#define PLATFORM_REG_GPIO_1_TASK_DRCLR_STS_r_GPIO0_39_TASK_DRCLR_sts_Pos                                     7U
+#define PLATFORM_REG_GPIO_1_TASK_DRCLR_STS_r_GPIO0_39_TASK_DRCLR_sts_Msk                                     (0x1UL << PLATFORM_REG_GPIO_1_TASK_DRCLR_STS_r_GPIO0_39_TASK_DRCLR_sts_Pos)
+
+#define PLATFORM_REG_GPIO_1_TASK_DRCLR_STS_r_GPIO0_40_TASK_DRCLR_sts_Pos                                     8U
+#define PLATFORM_REG_GPIO_1_TASK_DRCLR_STS_r_GPIO0_40_TASK_DRCLR_sts_Msk                                     (0x1UL << PLATFORM_REG_GPIO_1_TASK_DRCLR_STS_r_GPIO0_40_TASK_DRCLR_sts_Pos)
+
+#define PLATFORM_REG_GPIO_1_TASK_DRCLR_STS_r_GPIO0_41_TASK_DRCLR_sts_Pos                                     9U
+#define PLATFORM_REG_GPIO_1_TASK_DRCLR_STS_r_GPIO0_41_TASK_DRCLR_sts_Msk                                     (0x1UL << PLATFORM_REG_GPIO_1_TASK_DRCLR_STS_r_GPIO0_41_TASK_DRCLR_sts_Pos)
+
+#define PLATFORM_REG_GPIO_1_TASK_DRCLR_STS_r_GPIO0_42_TASK_DRCLR_sts_Pos                                     10U
+#define PLATFORM_REG_GPIO_1_TASK_DRCLR_STS_r_GPIO0_42_TASK_DRCLR_sts_Msk                                     (0x1UL << PLATFORM_REG_GPIO_1_TASK_DRCLR_STS_r_GPIO0_42_TASK_DRCLR_sts_Pos)
+
+#define PLATFORM_REG_GPIO_1_TASK_DRCLR_STS_r_GPIO0_43_TASK_DRCLR_sts_Pos                                     11U
+#define PLATFORM_REG_GPIO_1_TASK_DRCLR_STS_r_GPIO0_43_TASK_DRCLR_sts_Msk                                     (0x1UL << PLATFORM_REG_GPIO_1_TASK_DRCLR_STS_r_GPIO0_43_TASK_DRCLR_sts_Pos)
+
+#define PLATFORM_REG_GPIO_1_TASK_DRCLR_STS_r_GPIO0_44_TASK_DRCLR_sts_Pos                                     12U
+#define PLATFORM_REG_GPIO_1_TASK_DRCLR_STS_r_GPIO0_44_TASK_DRCLR_sts_Msk                                     (0x1UL << PLATFORM_REG_GPIO_1_TASK_DRCLR_STS_r_GPIO0_44_TASK_DRCLR_sts_Pos)
+
+#define PLATFORM_REG_GPIO_1_TASK_DRCLR_STS_r_GPIO0_45_TASK_DRCLR_sts_Pos                                     13U
+#define PLATFORM_REG_GPIO_1_TASK_DRCLR_STS_r_GPIO0_45_TASK_DRCLR_sts_Msk                                     (0x1UL << PLATFORM_REG_GPIO_1_TASK_DRCLR_STS_r_GPIO0_45_TASK_DRCLR_sts_Pos)
+
+#define PLATFORM_REG_GPIO_1_TASK_DRCLR_STS_r_GPIO0_46_TASK_DRCLR_sts_Pos                                     14U
+#define PLATFORM_REG_GPIO_1_TASK_DRCLR_STS_r_GPIO0_46_TASK_DRCLR_sts_Msk                                     (0x1UL << PLATFORM_REG_GPIO_1_TASK_DRCLR_STS_r_GPIO0_46_TASK_DRCLR_sts_Pos)
+
+#define PLATFORM_REG_GPIO_1_TASK_DRCLR_STS_r_GPIO0_47_TASK_DRCLR_sts_Pos                                     15U
+#define PLATFORM_REG_GPIO_1_TASK_DRCLR_STS_r_GPIO0_47_TASK_DRCLR_sts_Msk                                     (0x1UL << PLATFORM_REG_GPIO_1_TASK_DRCLR_STS_r_GPIO0_47_TASK_DRCLR_sts_Pos)
+
+#define PLATFORM_REG_GPIO_1_TASK_DRCLR_STS_r_GPIO0_48_TASK_DRCLR_sts_Pos                                     16U
+#define PLATFORM_REG_GPIO_1_TASK_DRCLR_STS_r_GPIO0_48_TASK_DRCLR_sts_Msk                                     (0x1UL << PLATFORM_REG_GPIO_1_TASK_DRCLR_STS_r_GPIO0_48_TASK_DRCLR_sts_Pos)
+
+#define PLATFORM_REG_GPIO_1_TASK_DRCLR_STS_r_GPIO0_49_TASK_DRCLR_sts_Pos                                     17U
+#define PLATFORM_REG_GPIO_1_TASK_DRCLR_STS_r_GPIO0_49_TASK_DRCLR_sts_Msk                                     (0x1UL << PLATFORM_REG_GPIO_1_TASK_DRCLR_STS_r_GPIO0_49_TASK_DRCLR_sts_Pos)
+
+#define PLATFORM_REG_GPIO_1_TASK_DRCLR_STS_reserved_Pos                                                      18U
+#define PLATFORM_REG_GPIO_1_TASK_DRCLR_STS_reserved_Msk                                                      (0x3FFFUL << PLATFORM_REG_GPIO_1_TASK_DRCLR_STS_reserved_Pos)
+
+/* 0x031c   0x4000_631c
+    0       R/W1C   r_GPIO0_0_TASK_DRSET_sts                            1'b0
+    1       R/W1C   r_GPIO0_1_TASK_DRSET_sts                            1'b0
+    2       R/W1C   r_GPIO0_2_TASK_DRSET_sts                            1'b0
+    3       R/W1C   r_GPIO0_3_TASK_DRSET_sts                            1'b0
+    4       R/W1C   r_GPIO0_4_TASK_DRSET_sts                            1'b0
+    5       R/W1C   r_GPIO0_5_TASK_DRSET_sts                            1'b0
+    6       R/W1C   r_GPIO0_6_TASK_DRSET_sts                            1'b0
+    7       R/W1C   r_GPIO0_7_TASK_DRSET_sts                            1'b0
+    8       R/W1C   r_GPIO0_8_TASK_DRSET_sts                            1'b0
+    9       R/W1C   r_GPIO0_9_TASK_DRSET_sts                            1'b0
+    10      R/W1C   r_GPIO0_10_TASK_DRSET_sts                           1'b0
+    11      R/W1C   r_GPIO0_11_TASK_DRSET_sts                           1'b0
+    12      R/W1C   r_GPIO0_12_TASK_DRSET_sts                           1'b0
+    13      R/W1C   r_GPIO0_13_TASK_DRSET_sts                           1'b0
+    14      R/W1C   r_GPIO0_14_TASK_DRSET_sts                           1'b0
+    15      R/W1C   r_GPIO0_15_TASK_DRSET_sts                           1'b0
+    16      R/W1C   r_GPIO0_16_TASK_DRSET_sts                           1'b0
+    17      R/W1C   r_GPIO0_17_TASK_DRSET_sts                           1'b0
+    18      R/W1C   r_GPIO0_18_TASK_DRSET_sts                           1'b0
+    19      R/W1C   r_GPIO0_19_TASK_DRSET_sts                           1'b0
+    20      R/W1C   r_GPIO0_20_TASK_DRSET_sts                           1'b0
+    21      R/W1C   r_GPIO0_21_TASK_DRSET_sts                           1'b0
+    22      R/W1C   r_GPIO0_22_TASK_DRSET_sts                           1'b0
+    23      R/W1C   r_GPIO0_23_TASK_DRSET_sts                           1'b0
+    24      R/W1C   r_GPIO0_24_TASK_DRSET_sts                           1'b0
+    25      R/W1C   r_GPIO0_25_TASK_DRSET_sts                           1'b0
+    26      R/W1C   r_GPIO0_26_TASK_DRSET_sts                           1'b0
+    27      R/W1C   r_GPIO0_27_TASK_DRSET_sts                           1'b0
+    28      R/W1C   r_GPIO0_28_TASK_DRSET_sts                           1'b0
+    29      R/W1C   r_GPIO0_29_TASK_DRSET_sts                           1'b0
+    30      R/W1C   r_GPIO0_30_TASK_DRSET_sts                           1'b0
+    31      R/W1C   r_GPIO0_31_TASK_DRSET_sts                           1'b0
+ */
+typedef union _PLATFORM_REG_GPIO_0_TASK_DRSET_STS_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t r_GPIO0_0_TASK_DRSET_sts: 1;
+        uint32_t r_GPIO0_1_TASK_DRSET_sts: 1;
+        uint32_t r_GPIO0_2_TASK_DRSET_sts: 1;
+        uint32_t r_GPIO0_3_TASK_DRSET_sts: 1;
+        uint32_t r_GPIO0_4_TASK_DRSET_sts: 1;
+        uint32_t r_GPIO0_5_TASK_DRSET_sts: 1;
+        uint32_t r_GPIO0_6_TASK_DRSET_sts: 1;
+        uint32_t r_GPIO0_7_TASK_DRSET_sts: 1;
+        uint32_t r_GPIO0_8_TASK_DRSET_sts: 1;
+        uint32_t r_GPIO0_9_TASK_DRSET_sts: 1;
+        uint32_t r_GPIO0_10_TASK_DRSET_sts: 1;
+        uint32_t r_GPIO0_11_TASK_DRSET_sts: 1;
+        uint32_t r_GPIO0_12_TASK_DRSET_sts: 1;
+        uint32_t r_GPIO0_13_TASK_DRSET_sts: 1;
+        uint32_t r_GPIO0_14_TASK_DRSET_sts: 1;
+        uint32_t r_GPIO0_15_TASK_DRSET_sts: 1;
+        uint32_t r_GPIO0_16_TASK_DRSET_sts: 1;
+        uint32_t r_GPIO0_17_TASK_DRSET_sts: 1;
+        uint32_t r_GPIO0_18_TASK_DRSET_sts: 1;
+        uint32_t r_GPIO0_19_TASK_DRSET_sts: 1;
+        uint32_t r_GPIO0_20_TASK_DRSET_sts: 1;
+        uint32_t r_GPIO0_21_TASK_DRSET_sts: 1;
+        uint32_t r_GPIO0_22_TASK_DRSET_sts: 1;
+        uint32_t r_GPIO0_23_TASK_DRSET_sts: 1;
+        uint32_t r_GPIO0_24_TASK_DRSET_sts: 1;
+        uint32_t r_GPIO0_25_TASK_DRSET_sts: 1;
+        uint32_t r_GPIO0_26_TASK_DRSET_sts: 1;
+        uint32_t r_GPIO0_27_TASK_DRSET_sts: 1;
+        uint32_t r_GPIO0_28_TASK_DRSET_sts: 1;
+        uint32_t r_GPIO0_29_TASK_DRSET_sts: 1;
+        uint32_t r_GPIO0_30_TASK_DRSET_sts: 1;
+        uint32_t r_GPIO0_31_TASK_DRSET_sts: 1;
+    };
+} PLATFORM_REG_GPIO_0_TASK_DRSET_STS_TYPE;
+
+/*0x4000_631c PLATFORM_REG_GPIO_0_TASK_DRSET_STS*/
+#define PLATFORM_REG_GPIO_0_TASK_DRSET_STS_r_GPIO0_0_TASK_DRSET_sts_Pos                                      0U
+#define PLATFORM_REG_GPIO_0_TASK_DRSET_STS_r_GPIO0_0_TASK_DRSET_sts_Msk                                      (0x1UL << PLATFORM_REG_GPIO_0_TASK_DRSET_STS_r_GPIO0_0_TASK_DRSET_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_TASK_DRSET_STS_r_GPIO0_1_TASK_DRSET_sts_Pos                                      1U
+#define PLATFORM_REG_GPIO_0_TASK_DRSET_STS_r_GPIO0_1_TASK_DRSET_sts_Msk                                      (0x1UL << PLATFORM_REG_GPIO_0_TASK_DRSET_STS_r_GPIO0_1_TASK_DRSET_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_TASK_DRSET_STS_r_GPIO0_2_TASK_DRSET_sts_Pos                                      2U
+#define PLATFORM_REG_GPIO_0_TASK_DRSET_STS_r_GPIO0_2_TASK_DRSET_sts_Msk                                      (0x1UL << PLATFORM_REG_GPIO_0_TASK_DRSET_STS_r_GPIO0_2_TASK_DRSET_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_TASK_DRSET_STS_r_GPIO0_3_TASK_DRSET_sts_Pos                                      3U
+#define PLATFORM_REG_GPIO_0_TASK_DRSET_STS_r_GPIO0_3_TASK_DRSET_sts_Msk                                      (0x1UL << PLATFORM_REG_GPIO_0_TASK_DRSET_STS_r_GPIO0_3_TASK_DRSET_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_TASK_DRSET_STS_r_GPIO0_4_TASK_DRSET_sts_Pos                                      4U
+#define PLATFORM_REG_GPIO_0_TASK_DRSET_STS_r_GPIO0_4_TASK_DRSET_sts_Msk                                      (0x1UL << PLATFORM_REG_GPIO_0_TASK_DRSET_STS_r_GPIO0_4_TASK_DRSET_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_TASK_DRSET_STS_r_GPIO0_5_TASK_DRSET_sts_Pos                                      5U
+#define PLATFORM_REG_GPIO_0_TASK_DRSET_STS_r_GPIO0_5_TASK_DRSET_sts_Msk                                      (0x1UL << PLATFORM_REG_GPIO_0_TASK_DRSET_STS_r_GPIO0_5_TASK_DRSET_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_TASK_DRSET_STS_r_GPIO0_6_TASK_DRSET_sts_Pos                                      6U
+#define PLATFORM_REG_GPIO_0_TASK_DRSET_STS_r_GPIO0_6_TASK_DRSET_sts_Msk                                      (0x1UL << PLATFORM_REG_GPIO_0_TASK_DRSET_STS_r_GPIO0_6_TASK_DRSET_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_TASK_DRSET_STS_r_GPIO0_7_TASK_DRSET_sts_Pos                                      7U
+#define PLATFORM_REG_GPIO_0_TASK_DRSET_STS_r_GPIO0_7_TASK_DRSET_sts_Msk                                      (0x1UL << PLATFORM_REG_GPIO_0_TASK_DRSET_STS_r_GPIO0_7_TASK_DRSET_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_TASK_DRSET_STS_r_GPIO0_8_TASK_DRSET_sts_Pos                                      8U
+#define PLATFORM_REG_GPIO_0_TASK_DRSET_STS_r_GPIO0_8_TASK_DRSET_sts_Msk                                      (0x1UL << PLATFORM_REG_GPIO_0_TASK_DRSET_STS_r_GPIO0_8_TASK_DRSET_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_TASK_DRSET_STS_r_GPIO0_9_TASK_DRSET_sts_Pos                                      9U
+#define PLATFORM_REG_GPIO_0_TASK_DRSET_STS_r_GPIO0_9_TASK_DRSET_sts_Msk                                      (0x1UL << PLATFORM_REG_GPIO_0_TASK_DRSET_STS_r_GPIO0_9_TASK_DRSET_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_TASK_DRSET_STS_r_GPIO0_10_TASK_DRSET_sts_Pos                                     10U
+#define PLATFORM_REG_GPIO_0_TASK_DRSET_STS_r_GPIO0_10_TASK_DRSET_sts_Msk                                     (0x1UL << PLATFORM_REG_GPIO_0_TASK_DRSET_STS_r_GPIO0_10_TASK_DRSET_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_TASK_DRSET_STS_r_GPIO0_11_TASK_DRSET_sts_Pos                                     11U
+#define PLATFORM_REG_GPIO_0_TASK_DRSET_STS_r_GPIO0_11_TASK_DRSET_sts_Msk                                     (0x1UL << PLATFORM_REG_GPIO_0_TASK_DRSET_STS_r_GPIO0_11_TASK_DRSET_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_TASK_DRSET_STS_r_GPIO0_12_TASK_DRSET_sts_Pos                                     12U
+#define PLATFORM_REG_GPIO_0_TASK_DRSET_STS_r_GPIO0_12_TASK_DRSET_sts_Msk                                     (0x1UL << PLATFORM_REG_GPIO_0_TASK_DRSET_STS_r_GPIO0_12_TASK_DRSET_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_TASK_DRSET_STS_r_GPIO0_13_TASK_DRSET_sts_Pos                                     13U
+#define PLATFORM_REG_GPIO_0_TASK_DRSET_STS_r_GPIO0_13_TASK_DRSET_sts_Msk                                     (0x1UL << PLATFORM_REG_GPIO_0_TASK_DRSET_STS_r_GPIO0_13_TASK_DRSET_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_TASK_DRSET_STS_r_GPIO0_14_TASK_DRSET_sts_Pos                                     14U
+#define PLATFORM_REG_GPIO_0_TASK_DRSET_STS_r_GPIO0_14_TASK_DRSET_sts_Msk                                     (0x1UL << PLATFORM_REG_GPIO_0_TASK_DRSET_STS_r_GPIO0_14_TASK_DRSET_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_TASK_DRSET_STS_r_GPIO0_15_TASK_DRSET_sts_Pos                                     15U
+#define PLATFORM_REG_GPIO_0_TASK_DRSET_STS_r_GPIO0_15_TASK_DRSET_sts_Msk                                     (0x1UL << PLATFORM_REG_GPIO_0_TASK_DRSET_STS_r_GPIO0_15_TASK_DRSET_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_TASK_DRSET_STS_r_GPIO0_16_TASK_DRSET_sts_Pos                                     16U
+#define PLATFORM_REG_GPIO_0_TASK_DRSET_STS_r_GPIO0_16_TASK_DRSET_sts_Msk                                     (0x1UL << PLATFORM_REG_GPIO_0_TASK_DRSET_STS_r_GPIO0_16_TASK_DRSET_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_TASK_DRSET_STS_r_GPIO0_17_TASK_DRSET_sts_Pos                                     17U
+#define PLATFORM_REG_GPIO_0_TASK_DRSET_STS_r_GPIO0_17_TASK_DRSET_sts_Msk                                     (0x1UL << PLATFORM_REG_GPIO_0_TASK_DRSET_STS_r_GPIO0_17_TASK_DRSET_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_TASK_DRSET_STS_r_GPIO0_18_TASK_DRSET_sts_Pos                                     18U
+#define PLATFORM_REG_GPIO_0_TASK_DRSET_STS_r_GPIO0_18_TASK_DRSET_sts_Msk                                     (0x1UL << PLATFORM_REG_GPIO_0_TASK_DRSET_STS_r_GPIO0_18_TASK_DRSET_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_TASK_DRSET_STS_r_GPIO0_19_TASK_DRSET_sts_Pos                                     19U
+#define PLATFORM_REG_GPIO_0_TASK_DRSET_STS_r_GPIO0_19_TASK_DRSET_sts_Msk                                     (0x1UL << PLATFORM_REG_GPIO_0_TASK_DRSET_STS_r_GPIO0_19_TASK_DRSET_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_TASK_DRSET_STS_r_GPIO0_20_TASK_DRSET_sts_Pos                                     20U
+#define PLATFORM_REG_GPIO_0_TASK_DRSET_STS_r_GPIO0_20_TASK_DRSET_sts_Msk                                     (0x1UL << PLATFORM_REG_GPIO_0_TASK_DRSET_STS_r_GPIO0_20_TASK_DRSET_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_TASK_DRSET_STS_r_GPIO0_21_TASK_DRSET_sts_Pos                                     21U
+#define PLATFORM_REG_GPIO_0_TASK_DRSET_STS_r_GPIO0_21_TASK_DRSET_sts_Msk                                     (0x1UL << PLATFORM_REG_GPIO_0_TASK_DRSET_STS_r_GPIO0_21_TASK_DRSET_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_TASK_DRSET_STS_r_GPIO0_22_TASK_DRSET_sts_Pos                                     22U
+#define PLATFORM_REG_GPIO_0_TASK_DRSET_STS_r_GPIO0_22_TASK_DRSET_sts_Msk                                     (0x1UL << PLATFORM_REG_GPIO_0_TASK_DRSET_STS_r_GPIO0_22_TASK_DRSET_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_TASK_DRSET_STS_r_GPIO0_23_TASK_DRSET_sts_Pos                                     23U
+#define PLATFORM_REG_GPIO_0_TASK_DRSET_STS_r_GPIO0_23_TASK_DRSET_sts_Msk                                     (0x1UL << PLATFORM_REG_GPIO_0_TASK_DRSET_STS_r_GPIO0_23_TASK_DRSET_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_TASK_DRSET_STS_r_GPIO0_24_TASK_DRSET_sts_Pos                                     24U
+#define PLATFORM_REG_GPIO_0_TASK_DRSET_STS_r_GPIO0_24_TASK_DRSET_sts_Msk                                     (0x1UL << PLATFORM_REG_GPIO_0_TASK_DRSET_STS_r_GPIO0_24_TASK_DRSET_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_TASK_DRSET_STS_r_GPIO0_25_TASK_DRSET_sts_Pos                                     25U
+#define PLATFORM_REG_GPIO_0_TASK_DRSET_STS_r_GPIO0_25_TASK_DRSET_sts_Msk                                     (0x1UL << PLATFORM_REG_GPIO_0_TASK_DRSET_STS_r_GPIO0_25_TASK_DRSET_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_TASK_DRSET_STS_r_GPIO0_26_TASK_DRSET_sts_Pos                                     26U
+#define PLATFORM_REG_GPIO_0_TASK_DRSET_STS_r_GPIO0_26_TASK_DRSET_sts_Msk                                     (0x1UL << PLATFORM_REG_GPIO_0_TASK_DRSET_STS_r_GPIO0_26_TASK_DRSET_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_TASK_DRSET_STS_r_GPIO0_27_TASK_DRSET_sts_Pos                                     27U
+#define PLATFORM_REG_GPIO_0_TASK_DRSET_STS_r_GPIO0_27_TASK_DRSET_sts_Msk                                     (0x1UL << PLATFORM_REG_GPIO_0_TASK_DRSET_STS_r_GPIO0_27_TASK_DRSET_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_TASK_DRSET_STS_r_GPIO0_28_TASK_DRSET_sts_Pos                                     28U
+#define PLATFORM_REG_GPIO_0_TASK_DRSET_STS_r_GPIO0_28_TASK_DRSET_sts_Msk                                     (0x1UL << PLATFORM_REG_GPIO_0_TASK_DRSET_STS_r_GPIO0_28_TASK_DRSET_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_TASK_DRSET_STS_r_GPIO0_29_TASK_DRSET_sts_Pos                                     29U
+#define PLATFORM_REG_GPIO_0_TASK_DRSET_STS_r_GPIO0_29_TASK_DRSET_sts_Msk                                     (0x1UL << PLATFORM_REG_GPIO_0_TASK_DRSET_STS_r_GPIO0_29_TASK_DRSET_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_TASK_DRSET_STS_r_GPIO0_30_TASK_DRSET_sts_Pos                                     30U
+#define PLATFORM_REG_GPIO_0_TASK_DRSET_STS_r_GPIO0_30_TASK_DRSET_sts_Msk                                     (0x1UL << PLATFORM_REG_GPIO_0_TASK_DRSET_STS_r_GPIO0_30_TASK_DRSET_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_TASK_DRSET_STS_r_GPIO0_31_TASK_DRSET_sts_Pos                                     31U
+#define PLATFORM_REG_GPIO_0_TASK_DRSET_STS_r_GPIO0_31_TASK_DRSET_sts_Msk                                     (0x1UL << PLATFORM_REG_GPIO_0_TASK_DRSET_STS_r_GPIO0_31_TASK_DRSET_sts_Pos)
+
+/* 0x0320   0x4000_6320
+    0       R/W1C   r_GPIO0_32_TASK_DRSET_sts                           1'b0
+    1       R/W1C   r_GPIO0_33_TASK_DRSET_sts                           1'b0
+    2       R/W1C   r_GPIO0_34_TASK_DRSET_sts                           1'b0
+    3       R/W1C   r_GPIO0_35_TASK_DRSET_sts                           1'b0
+    4       R/W1C   r_GPIO0_36_TASK_DRSET_sts                           1'b0
+    5       R/W1C   r_GPIO0_37_TASK_DRSET_sts                           1'b0
+    6       R/W1C   r_GPIO0_38_TASK_DRSET_sts                           1'b0
+    7       R/W1C   r_GPIO0_39_TASK_DRSET_sts                           1'b0
+    8       R/W1C   r_GPIO0_40_TASK_DRSET_sts                           1'b0
+    9       R/W1C   r_GPIO0_41_TASK_DRSET_sts                           1'b0
+    10      R/W1C   r_GPIO0_42_TASK_DRSET_sts                           1'b0
+    11      R/W1C   r_GPIO0_43_TASK_DRSET_sts                           1'b0
+    12      R/W1C   r_GPIO0_44_TASK_DRSET_sts                           1'b0
+    13      R/W1C   r_GPIO0_45_TASK_DRSET_sts                           1'b0
+    14      R/W1C   r_GPIO0_46_TASK_DRSET_sts                           1'b0
+    15      R/W1C   r_GPIO0_47_TASK_DRSET_sts                           1'b0
+    16      R/W1C   r_GPIO0_48_TASK_DRSET_sts                           1'b0
+    17      R/W1C   r_GPIO0_49_TASK_DRSET_sts                           1'b0
+    31:18   R       reserved                                            14'h0000
+ */
+typedef union _PLATFORM_REG_GPIO_1_TASK_DRSET_STS_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t r_GPIO0_32_TASK_DRSET_sts: 1;
+        uint32_t r_GPIO0_33_TASK_DRSET_sts: 1;
+        uint32_t r_GPIO0_34_TASK_DRSET_sts: 1;
+        uint32_t r_GPIO0_35_TASK_DRSET_sts: 1;
+        uint32_t r_GPIO0_36_TASK_DRSET_sts: 1;
+        uint32_t r_GPIO0_37_TASK_DRSET_sts: 1;
+        uint32_t r_GPIO0_38_TASK_DRSET_sts: 1;
+        uint32_t r_GPIO0_39_TASK_DRSET_sts: 1;
+        uint32_t r_GPIO0_40_TASK_DRSET_sts: 1;
+        uint32_t r_GPIO0_41_TASK_DRSET_sts: 1;
+        uint32_t r_GPIO0_42_TASK_DRSET_sts: 1;
+        uint32_t r_GPIO0_43_TASK_DRSET_sts: 1;
+        uint32_t r_GPIO0_44_TASK_DRSET_sts: 1;
+        uint32_t r_GPIO0_45_TASK_DRSET_sts: 1;
+        uint32_t r_GPIO0_46_TASK_DRSET_sts: 1;
+        uint32_t r_GPIO0_47_TASK_DRSET_sts: 1;
+        uint32_t r_GPIO0_48_TASK_DRSET_sts: 1;
+        uint32_t r_GPIO0_49_TASK_DRSET_sts: 1;
+        uint32_t reserved: 14;
+    };
+} PLATFORM_REG_GPIO_1_TASK_DRSET_STS_TYPE;
+
+/*0x4000_6320 PLATFORM_REG_GPIO_1_TASK_DRSET_STS*/
+#define PLATFORM_REG_GPIO_1_TASK_DRSET_STS_r_GPIO0_32_TASK_DRSET_sts_Pos                                     0U
+#define PLATFORM_REG_GPIO_1_TASK_DRSET_STS_r_GPIO0_32_TASK_DRSET_sts_Msk                                     (0x1UL << PLATFORM_REG_GPIO_1_TASK_DRSET_STS_r_GPIO0_32_TASK_DRSET_sts_Pos)
+
+#define PLATFORM_REG_GPIO_1_TASK_DRSET_STS_r_GPIO0_33_TASK_DRSET_sts_Pos                                     1U
+#define PLATFORM_REG_GPIO_1_TASK_DRSET_STS_r_GPIO0_33_TASK_DRSET_sts_Msk                                     (0x1UL << PLATFORM_REG_GPIO_1_TASK_DRSET_STS_r_GPIO0_33_TASK_DRSET_sts_Pos)
+
+#define PLATFORM_REG_GPIO_1_TASK_DRSET_STS_r_GPIO0_34_TASK_DRSET_sts_Pos                                     2U
+#define PLATFORM_REG_GPIO_1_TASK_DRSET_STS_r_GPIO0_34_TASK_DRSET_sts_Msk                                     (0x1UL << PLATFORM_REG_GPIO_1_TASK_DRSET_STS_r_GPIO0_34_TASK_DRSET_sts_Pos)
+
+#define PLATFORM_REG_GPIO_1_TASK_DRSET_STS_r_GPIO0_35_TASK_DRSET_sts_Pos                                     3U
+#define PLATFORM_REG_GPIO_1_TASK_DRSET_STS_r_GPIO0_35_TASK_DRSET_sts_Msk                                     (0x1UL << PLATFORM_REG_GPIO_1_TASK_DRSET_STS_r_GPIO0_35_TASK_DRSET_sts_Pos)
+
+#define PLATFORM_REG_GPIO_1_TASK_DRSET_STS_r_GPIO0_36_TASK_DRSET_sts_Pos                                     4U
+#define PLATFORM_REG_GPIO_1_TASK_DRSET_STS_r_GPIO0_36_TASK_DRSET_sts_Msk                                     (0x1UL << PLATFORM_REG_GPIO_1_TASK_DRSET_STS_r_GPIO0_36_TASK_DRSET_sts_Pos)
+
+#define PLATFORM_REG_GPIO_1_TASK_DRSET_STS_r_GPIO0_37_TASK_DRSET_sts_Pos                                     5U
+#define PLATFORM_REG_GPIO_1_TASK_DRSET_STS_r_GPIO0_37_TASK_DRSET_sts_Msk                                     (0x1UL << PLATFORM_REG_GPIO_1_TASK_DRSET_STS_r_GPIO0_37_TASK_DRSET_sts_Pos)
+
+#define PLATFORM_REG_GPIO_1_TASK_DRSET_STS_r_GPIO0_38_TASK_DRSET_sts_Pos                                     6U
+#define PLATFORM_REG_GPIO_1_TASK_DRSET_STS_r_GPIO0_38_TASK_DRSET_sts_Msk                                     (0x1UL << PLATFORM_REG_GPIO_1_TASK_DRSET_STS_r_GPIO0_38_TASK_DRSET_sts_Pos)
+
+#define PLATFORM_REG_GPIO_1_TASK_DRSET_STS_r_GPIO0_39_TASK_DRSET_sts_Pos                                     7U
+#define PLATFORM_REG_GPIO_1_TASK_DRSET_STS_r_GPIO0_39_TASK_DRSET_sts_Msk                                     (0x1UL << PLATFORM_REG_GPIO_1_TASK_DRSET_STS_r_GPIO0_39_TASK_DRSET_sts_Pos)
+
+#define PLATFORM_REG_GPIO_1_TASK_DRSET_STS_r_GPIO0_40_TASK_DRSET_sts_Pos                                     8U
+#define PLATFORM_REG_GPIO_1_TASK_DRSET_STS_r_GPIO0_40_TASK_DRSET_sts_Msk                                     (0x1UL << PLATFORM_REG_GPIO_1_TASK_DRSET_STS_r_GPIO0_40_TASK_DRSET_sts_Pos)
+
+#define PLATFORM_REG_GPIO_1_TASK_DRSET_STS_r_GPIO0_41_TASK_DRSET_sts_Pos                                     9U
+#define PLATFORM_REG_GPIO_1_TASK_DRSET_STS_r_GPIO0_41_TASK_DRSET_sts_Msk                                     (0x1UL << PLATFORM_REG_GPIO_1_TASK_DRSET_STS_r_GPIO0_41_TASK_DRSET_sts_Pos)
+
+#define PLATFORM_REG_GPIO_1_TASK_DRSET_STS_r_GPIO0_42_TASK_DRSET_sts_Pos                                     10U
+#define PLATFORM_REG_GPIO_1_TASK_DRSET_STS_r_GPIO0_42_TASK_DRSET_sts_Msk                                     (0x1UL << PLATFORM_REG_GPIO_1_TASK_DRSET_STS_r_GPIO0_42_TASK_DRSET_sts_Pos)
+
+#define PLATFORM_REG_GPIO_1_TASK_DRSET_STS_r_GPIO0_43_TASK_DRSET_sts_Pos                                     11U
+#define PLATFORM_REG_GPIO_1_TASK_DRSET_STS_r_GPIO0_43_TASK_DRSET_sts_Msk                                     (0x1UL << PLATFORM_REG_GPIO_1_TASK_DRSET_STS_r_GPIO0_43_TASK_DRSET_sts_Pos)
+
+#define PLATFORM_REG_GPIO_1_TASK_DRSET_STS_r_GPIO0_44_TASK_DRSET_sts_Pos                                     12U
+#define PLATFORM_REG_GPIO_1_TASK_DRSET_STS_r_GPIO0_44_TASK_DRSET_sts_Msk                                     (0x1UL << PLATFORM_REG_GPIO_1_TASK_DRSET_STS_r_GPIO0_44_TASK_DRSET_sts_Pos)
+
+#define PLATFORM_REG_GPIO_1_TASK_DRSET_STS_r_GPIO0_45_TASK_DRSET_sts_Pos                                     13U
+#define PLATFORM_REG_GPIO_1_TASK_DRSET_STS_r_GPIO0_45_TASK_DRSET_sts_Msk                                     (0x1UL << PLATFORM_REG_GPIO_1_TASK_DRSET_STS_r_GPIO0_45_TASK_DRSET_sts_Pos)
+
+#define PLATFORM_REG_GPIO_1_TASK_DRSET_STS_r_GPIO0_46_TASK_DRSET_sts_Pos                                     14U
+#define PLATFORM_REG_GPIO_1_TASK_DRSET_STS_r_GPIO0_46_TASK_DRSET_sts_Msk                                     (0x1UL << PLATFORM_REG_GPIO_1_TASK_DRSET_STS_r_GPIO0_46_TASK_DRSET_sts_Pos)
+
+#define PLATFORM_REG_GPIO_1_TASK_DRSET_STS_r_GPIO0_47_TASK_DRSET_sts_Pos                                     15U
+#define PLATFORM_REG_GPIO_1_TASK_DRSET_STS_r_GPIO0_47_TASK_DRSET_sts_Msk                                     (0x1UL << PLATFORM_REG_GPIO_1_TASK_DRSET_STS_r_GPIO0_47_TASK_DRSET_sts_Pos)
+
+#define PLATFORM_REG_GPIO_1_TASK_DRSET_STS_r_GPIO0_48_TASK_DRSET_sts_Pos                                     16U
+#define PLATFORM_REG_GPIO_1_TASK_DRSET_STS_r_GPIO0_48_TASK_DRSET_sts_Msk                                     (0x1UL << PLATFORM_REG_GPIO_1_TASK_DRSET_STS_r_GPIO0_48_TASK_DRSET_sts_Pos)
+
+#define PLATFORM_REG_GPIO_1_TASK_DRSET_STS_r_GPIO0_49_TASK_DRSET_sts_Pos                                     17U
+#define PLATFORM_REG_GPIO_1_TASK_DRSET_STS_r_GPIO0_49_TASK_DRSET_sts_Msk                                     (0x1UL << PLATFORM_REG_GPIO_1_TASK_DRSET_STS_r_GPIO0_49_TASK_DRSET_sts_Pos)
+
+#define PLATFORM_REG_GPIO_1_TASK_DRSET_STS_reserved_Pos                                                      18U
+#define PLATFORM_REG_GPIO_1_TASK_DRSET_STS_reserved_Msk                                                      (0x3FFFUL << PLATFORM_REG_GPIO_1_TASK_DRSET_STS_reserved_Pos)
+
+/* 0x0324   0x4000_6324
+    0       R/W1C   r_GPIO0_0_TASK_DRTOGGLE_sts                         1'b0
+    1       R/W1C   r_GPIO0_1_TASK_DRTOGGLE_sts                         1'b0
+    2       R/W1C   r_GPIO0_2_TASK_DRTOGGLE_sts                         1'b0
+    3       R/W1C   r_GPIO0_3_TASK_DRTOGGLE_sts                         1'b0
+    4       R/W1C   r_GPIO0_4_TASK_DRTOGGLE_sts                         1'b0
+    5       R/W1C   r_GPIO0_5_TASK_DRTOGGLE_sts                         1'b0
+    6       R/W1C   r_GPIO0_6_TASK_DRTOGGLE_sts                         1'b0
+    7       R/W1C   r_GPIO0_7_TASK_DRTOGGLE_sts                         1'b0
+    8       R/W1C   r_GPIO0_8_TASK_DRTOGGLE_sts                         1'b0
+    9       R/W1C   r_GPIO0_9_TASK_DRTOGGLE_sts                         1'b0
+    10      R/W1C   r_GPIO0_10_TASK_DRTOGGLE_sts                        1'b0
+    11      R/W1C   r_GPIO0_11_TASK_DRTOGGLE_sts                        1'b0
+    12      R/W1C   r_GPIO0_12_TASK_DRTOGGLE_sts                        1'b0
+    13      R/W1C   r_GPIO0_13_TASK_DRTOGGLE_sts                        1'b0
+    14      R/W1C   r_GPIO0_14_TASK_DRTOGGLE_sts                        1'b0
+    15      R/W1C   r_GPIO0_15_TASK_DRTOGGLE_sts                        1'b0
+    16      R/W1C   r_GPIO0_16_TASK_DRTOGGLE_sts                        1'b0
+    17      R/W1C   r_GPIO0_17_TASK_DRTOGGLE_sts                        1'b0
+    18      R/W1C   r_GPIO0_18_TASK_DRTOGGLE_sts                        1'b0
+    19      R/W1C   r_GPIO0_19_TASK_DRTOGGLE_sts                        1'b0
+    20      R/W1C   r_GPIO0_20_TASK_DRTOGGLE_sts                        1'b0
+    21      R/W1C   r_GPIO0_21_TASK_DRTOGGLE_sts                        1'b0
+    22      R/W1C   r_GPIO0_22_TASK_DRTOGGLE_sts                        1'b0
+    23      R/W1C   r_GPIO0_23_TASK_DRTOGGLE_sts                        1'b0
+    24      R/W1C   r_GPIO0_24_TASK_DRTOGGLE_sts                        1'b0
+    25      R/W1C   r_GPIO0_25_TASK_DRTOGGLE_sts                        1'b0
+    26      R/W1C   r_GPIO0_26_TASK_DRTOGGLE_sts                        1'b0
+    27      R/W1C   r_GPIO0_27_TASK_DRTOGGLE_sts                        1'b0
+    28      R/W1C   r_GPIO0_28_TASK_DRTOGGLE_sts                        1'b0
+    29      R/W1C   r_GPIO0_29_TASK_DRTOGGLE_sts                        1'b0
+    30      R/W1C   r_GPIO0_30_TASK_DRTOGGLE_sts                        1'b0
+    31      R/W1C   r_GPIO0_31_TASK_DRTOGGLE_sts                        1'b0
+ */
+typedef union _PLATFORM_REG_GPIO_0_TASK_DRTOGGLE_STS_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t r_GPIO0_0_TASK_DRTOGGLE_sts: 1;
+        uint32_t r_GPIO0_1_TASK_DRTOGGLE_sts: 1;
+        uint32_t r_GPIO0_2_TASK_DRTOGGLE_sts: 1;
+        uint32_t r_GPIO0_3_TASK_DRTOGGLE_sts: 1;
+        uint32_t r_GPIO0_4_TASK_DRTOGGLE_sts: 1;
+        uint32_t r_GPIO0_5_TASK_DRTOGGLE_sts: 1;
+        uint32_t r_GPIO0_6_TASK_DRTOGGLE_sts: 1;
+        uint32_t r_GPIO0_7_TASK_DRTOGGLE_sts: 1;
+        uint32_t r_GPIO0_8_TASK_DRTOGGLE_sts: 1;
+        uint32_t r_GPIO0_9_TASK_DRTOGGLE_sts: 1;
+        uint32_t r_GPIO0_10_TASK_DRTOGGLE_sts: 1;
+        uint32_t r_GPIO0_11_TASK_DRTOGGLE_sts: 1;
+        uint32_t r_GPIO0_12_TASK_DRTOGGLE_sts: 1;
+        uint32_t r_GPIO0_13_TASK_DRTOGGLE_sts: 1;
+        uint32_t r_GPIO0_14_TASK_DRTOGGLE_sts: 1;
+        uint32_t r_GPIO0_15_TASK_DRTOGGLE_sts: 1;
+        uint32_t r_GPIO0_16_TASK_DRTOGGLE_sts: 1;
+        uint32_t r_GPIO0_17_TASK_DRTOGGLE_sts: 1;
+        uint32_t r_GPIO0_18_TASK_DRTOGGLE_sts: 1;
+        uint32_t r_GPIO0_19_TASK_DRTOGGLE_sts: 1;
+        uint32_t r_GPIO0_20_TASK_DRTOGGLE_sts: 1;
+        uint32_t r_GPIO0_21_TASK_DRTOGGLE_sts: 1;
+        uint32_t r_GPIO0_22_TASK_DRTOGGLE_sts: 1;
+        uint32_t r_GPIO0_23_TASK_DRTOGGLE_sts: 1;
+        uint32_t r_GPIO0_24_TASK_DRTOGGLE_sts: 1;
+        uint32_t r_GPIO0_25_TASK_DRTOGGLE_sts: 1;
+        uint32_t r_GPIO0_26_TASK_DRTOGGLE_sts: 1;
+        uint32_t r_GPIO0_27_TASK_DRTOGGLE_sts: 1;
+        uint32_t r_GPIO0_28_TASK_DRTOGGLE_sts: 1;
+        uint32_t r_GPIO0_29_TASK_DRTOGGLE_sts: 1;
+        uint32_t r_GPIO0_30_TASK_DRTOGGLE_sts: 1;
+        uint32_t r_GPIO0_31_TASK_DRTOGGLE_sts: 1;
+    };
+} PLATFORM_REG_GPIO_0_TASK_DRTOGGLE_STS_TYPE;
+
+/*0x4000_6324 PLATFORM_REG_GPIO_0_TASK_DRTOGGLE_STS*/
+#define PLATFORM_REG_GPIO_0_TASK_DRTOGGLE_STS_r_GPIO0_0_TASK_DRTOGGLE_sts_Pos                                0U
+#define PLATFORM_REG_GPIO_0_TASK_DRTOGGLE_STS_r_GPIO0_0_TASK_DRTOGGLE_sts_Msk                                (0x1UL << PLATFORM_REG_GPIO_0_TASK_DRTOGGLE_STS_r_GPIO0_0_TASK_DRTOGGLE_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_TASK_DRTOGGLE_STS_r_GPIO0_1_TASK_DRTOGGLE_sts_Pos                                1U
+#define PLATFORM_REG_GPIO_0_TASK_DRTOGGLE_STS_r_GPIO0_1_TASK_DRTOGGLE_sts_Msk                                (0x1UL << PLATFORM_REG_GPIO_0_TASK_DRTOGGLE_STS_r_GPIO0_1_TASK_DRTOGGLE_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_TASK_DRTOGGLE_STS_r_GPIO0_2_TASK_DRTOGGLE_sts_Pos                                2U
+#define PLATFORM_REG_GPIO_0_TASK_DRTOGGLE_STS_r_GPIO0_2_TASK_DRTOGGLE_sts_Msk                                (0x1UL << PLATFORM_REG_GPIO_0_TASK_DRTOGGLE_STS_r_GPIO0_2_TASK_DRTOGGLE_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_TASK_DRTOGGLE_STS_r_GPIO0_3_TASK_DRTOGGLE_sts_Pos                                3U
+#define PLATFORM_REG_GPIO_0_TASK_DRTOGGLE_STS_r_GPIO0_3_TASK_DRTOGGLE_sts_Msk                                (0x1UL << PLATFORM_REG_GPIO_0_TASK_DRTOGGLE_STS_r_GPIO0_3_TASK_DRTOGGLE_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_TASK_DRTOGGLE_STS_r_GPIO0_4_TASK_DRTOGGLE_sts_Pos                                4U
+#define PLATFORM_REG_GPIO_0_TASK_DRTOGGLE_STS_r_GPIO0_4_TASK_DRTOGGLE_sts_Msk                                (0x1UL << PLATFORM_REG_GPIO_0_TASK_DRTOGGLE_STS_r_GPIO0_4_TASK_DRTOGGLE_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_TASK_DRTOGGLE_STS_r_GPIO0_5_TASK_DRTOGGLE_sts_Pos                                5U
+#define PLATFORM_REG_GPIO_0_TASK_DRTOGGLE_STS_r_GPIO0_5_TASK_DRTOGGLE_sts_Msk                                (0x1UL << PLATFORM_REG_GPIO_0_TASK_DRTOGGLE_STS_r_GPIO0_5_TASK_DRTOGGLE_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_TASK_DRTOGGLE_STS_r_GPIO0_6_TASK_DRTOGGLE_sts_Pos                                6U
+#define PLATFORM_REG_GPIO_0_TASK_DRTOGGLE_STS_r_GPIO0_6_TASK_DRTOGGLE_sts_Msk                                (0x1UL << PLATFORM_REG_GPIO_0_TASK_DRTOGGLE_STS_r_GPIO0_6_TASK_DRTOGGLE_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_TASK_DRTOGGLE_STS_r_GPIO0_7_TASK_DRTOGGLE_sts_Pos                                7U
+#define PLATFORM_REG_GPIO_0_TASK_DRTOGGLE_STS_r_GPIO0_7_TASK_DRTOGGLE_sts_Msk                                (0x1UL << PLATFORM_REG_GPIO_0_TASK_DRTOGGLE_STS_r_GPIO0_7_TASK_DRTOGGLE_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_TASK_DRTOGGLE_STS_r_GPIO0_8_TASK_DRTOGGLE_sts_Pos                                8U
+#define PLATFORM_REG_GPIO_0_TASK_DRTOGGLE_STS_r_GPIO0_8_TASK_DRTOGGLE_sts_Msk                                (0x1UL << PLATFORM_REG_GPIO_0_TASK_DRTOGGLE_STS_r_GPIO0_8_TASK_DRTOGGLE_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_TASK_DRTOGGLE_STS_r_GPIO0_9_TASK_DRTOGGLE_sts_Pos                                9U
+#define PLATFORM_REG_GPIO_0_TASK_DRTOGGLE_STS_r_GPIO0_9_TASK_DRTOGGLE_sts_Msk                                (0x1UL << PLATFORM_REG_GPIO_0_TASK_DRTOGGLE_STS_r_GPIO0_9_TASK_DRTOGGLE_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_TASK_DRTOGGLE_STS_r_GPIO0_10_TASK_DRTOGGLE_sts_Pos                               10U
+#define PLATFORM_REG_GPIO_0_TASK_DRTOGGLE_STS_r_GPIO0_10_TASK_DRTOGGLE_sts_Msk                               (0x1UL << PLATFORM_REG_GPIO_0_TASK_DRTOGGLE_STS_r_GPIO0_10_TASK_DRTOGGLE_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_TASK_DRTOGGLE_STS_r_GPIO0_11_TASK_DRTOGGLE_sts_Pos                               11U
+#define PLATFORM_REG_GPIO_0_TASK_DRTOGGLE_STS_r_GPIO0_11_TASK_DRTOGGLE_sts_Msk                               (0x1UL << PLATFORM_REG_GPIO_0_TASK_DRTOGGLE_STS_r_GPIO0_11_TASK_DRTOGGLE_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_TASK_DRTOGGLE_STS_r_GPIO0_12_TASK_DRTOGGLE_sts_Pos                               12U
+#define PLATFORM_REG_GPIO_0_TASK_DRTOGGLE_STS_r_GPIO0_12_TASK_DRTOGGLE_sts_Msk                               (0x1UL << PLATFORM_REG_GPIO_0_TASK_DRTOGGLE_STS_r_GPIO0_12_TASK_DRTOGGLE_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_TASK_DRTOGGLE_STS_r_GPIO0_13_TASK_DRTOGGLE_sts_Pos                               13U
+#define PLATFORM_REG_GPIO_0_TASK_DRTOGGLE_STS_r_GPIO0_13_TASK_DRTOGGLE_sts_Msk                               (0x1UL << PLATFORM_REG_GPIO_0_TASK_DRTOGGLE_STS_r_GPIO0_13_TASK_DRTOGGLE_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_TASK_DRTOGGLE_STS_r_GPIO0_14_TASK_DRTOGGLE_sts_Pos                               14U
+#define PLATFORM_REG_GPIO_0_TASK_DRTOGGLE_STS_r_GPIO0_14_TASK_DRTOGGLE_sts_Msk                               (0x1UL << PLATFORM_REG_GPIO_0_TASK_DRTOGGLE_STS_r_GPIO0_14_TASK_DRTOGGLE_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_TASK_DRTOGGLE_STS_r_GPIO0_15_TASK_DRTOGGLE_sts_Pos                               15U
+#define PLATFORM_REG_GPIO_0_TASK_DRTOGGLE_STS_r_GPIO0_15_TASK_DRTOGGLE_sts_Msk                               (0x1UL << PLATFORM_REG_GPIO_0_TASK_DRTOGGLE_STS_r_GPIO0_15_TASK_DRTOGGLE_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_TASK_DRTOGGLE_STS_r_GPIO0_16_TASK_DRTOGGLE_sts_Pos                               16U
+#define PLATFORM_REG_GPIO_0_TASK_DRTOGGLE_STS_r_GPIO0_16_TASK_DRTOGGLE_sts_Msk                               (0x1UL << PLATFORM_REG_GPIO_0_TASK_DRTOGGLE_STS_r_GPIO0_16_TASK_DRTOGGLE_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_TASK_DRTOGGLE_STS_r_GPIO0_17_TASK_DRTOGGLE_sts_Pos                               17U
+#define PLATFORM_REG_GPIO_0_TASK_DRTOGGLE_STS_r_GPIO0_17_TASK_DRTOGGLE_sts_Msk                               (0x1UL << PLATFORM_REG_GPIO_0_TASK_DRTOGGLE_STS_r_GPIO0_17_TASK_DRTOGGLE_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_TASK_DRTOGGLE_STS_r_GPIO0_18_TASK_DRTOGGLE_sts_Pos                               18U
+#define PLATFORM_REG_GPIO_0_TASK_DRTOGGLE_STS_r_GPIO0_18_TASK_DRTOGGLE_sts_Msk                               (0x1UL << PLATFORM_REG_GPIO_0_TASK_DRTOGGLE_STS_r_GPIO0_18_TASK_DRTOGGLE_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_TASK_DRTOGGLE_STS_r_GPIO0_19_TASK_DRTOGGLE_sts_Pos                               19U
+#define PLATFORM_REG_GPIO_0_TASK_DRTOGGLE_STS_r_GPIO0_19_TASK_DRTOGGLE_sts_Msk                               (0x1UL << PLATFORM_REG_GPIO_0_TASK_DRTOGGLE_STS_r_GPIO0_19_TASK_DRTOGGLE_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_TASK_DRTOGGLE_STS_r_GPIO0_20_TASK_DRTOGGLE_sts_Pos                               20U
+#define PLATFORM_REG_GPIO_0_TASK_DRTOGGLE_STS_r_GPIO0_20_TASK_DRTOGGLE_sts_Msk                               (0x1UL << PLATFORM_REG_GPIO_0_TASK_DRTOGGLE_STS_r_GPIO0_20_TASK_DRTOGGLE_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_TASK_DRTOGGLE_STS_r_GPIO0_21_TASK_DRTOGGLE_sts_Pos                               21U
+#define PLATFORM_REG_GPIO_0_TASK_DRTOGGLE_STS_r_GPIO0_21_TASK_DRTOGGLE_sts_Msk                               (0x1UL << PLATFORM_REG_GPIO_0_TASK_DRTOGGLE_STS_r_GPIO0_21_TASK_DRTOGGLE_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_TASK_DRTOGGLE_STS_r_GPIO0_22_TASK_DRTOGGLE_sts_Pos                               22U
+#define PLATFORM_REG_GPIO_0_TASK_DRTOGGLE_STS_r_GPIO0_22_TASK_DRTOGGLE_sts_Msk                               (0x1UL << PLATFORM_REG_GPIO_0_TASK_DRTOGGLE_STS_r_GPIO0_22_TASK_DRTOGGLE_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_TASK_DRTOGGLE_STS_r_GPIO0_23_TASK_DRTOGGLE_sts_Pos                               23U
+#define PLATFORM_REG_GPIO_0_TASK_DRTOGGLE_STS_r_GPIO0_23_TASK_DRTOGGLE_sts_Msk                               (0x1UL << PLATFORM_REG_GPIO_0_TASK_DRTOGGLE_STS_r_GPIO0_23_TASK_DRTOGGLE_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_TASK_DRTOGGLE_STS_r_GPIO0_24_TASK_DRTOGGLE_sts_Pos                               24U
+#define PLATFORM_REG_GPIO_0_TASK_DRTOGGLE_STS_r_GPIO0_24_TASK_DRTOGGLE_sts_Msk                               (0x1UL << PLATFORM_REG_GPIO_0_TASK_DRTOGGLE_STS_r_GPIO0_24_TASK_DRTOGGLE_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_TASK_DRTOGGLE_STS_r_GPIO0_25_TASK_DRTOGGLE_sts_Pos                               25U
+#define PLATFORM_REG_GPIO_0_TASK_DRTOGGLE_STS_r_GPIO0_25_TASK_DRTOGGLE_sts_Msk                               (0x1UL << PLATFORM_REG_GPIO_0_TASK_DRTOGGLE_STS_r_GPIO0_25_TASK_DRTOGGLE_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_TASK_DRTOGGLE_STS_r_GPIO0_26_TASK_DRTOGGLE_sts_Pos                               26U
+#define PLATFORM_REG_GPIO_0_TASK_DRTOGGLE_STS_r_GPIO0_26_TASK_DRTOGGLE_sts_Msk                               (0x1UL << PLATFORM_REG_GPIO_0_TASK_DRTOGGLE_STS_r_GPIO0_26_TASK_DRTOGGLE_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_TASK_DRTOGGLE_STS_r_GPIO0_27_TASK_DRTOGGLE_sts_Pos                               27U
+#define PLATFORM_REG_GPIO_0_TASK_DRTOGGLE_STS_r_GPIO0_27_TASK_DRTOGGLE_sts_Msk                               (0x1UL << PLATFORM_REG_GPIO_0_TASK_DRTOGGLE_STS_r_GPIO0_27_TASK_DRTOGGLE_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_TASK_DRTOGGLE_STS_r_GPIO0_28_TASK_DRTOGGLE_sts_Pos                               28U
+#define PLATFORM_REG_GPIO_0_TASK_DRTOGGLE_STS_r_GPIO0_28_TASK_DRTOGGLE_sts_Msk                               (0x1UL << PLATFORM_REG_GPIO_0_TASK_DRTOGGLE_STS_r_GPIO0_28_TASK_DRTOGGLE_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_TASK_DRTOGGLE_STS_r_GPIO0_29_TASK_DRTOGGLE_sts_Pos                               29U
+#define PLATFORM_REG_GPIO_0_TASK_DRTOGGLE_STS_r_GPIO0_29_TASK_DRTOGGLE_sts_Msk                               (0x1UL << PLATFORM_REG_GPIO_0_TASK_DRTOGGLE_STS_r_GPIO0_29_TASK_DRTOGGLE_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_TASK_DRTOGGLE_STS_r_GPIO0_30_TASK_DRTOGGLE_sts_Pos                               30U
+#define PLATFORM_REG_GPIO_0_TASK_DRTOGGLE_STS_r_GPIO0_30_TASK_DRTOGGLE_sts_Msk                               (0x1UL << PLATFORM_REG_GPIO_0_TASK_DRTOGGLE_STS_r_GPIO0_30_TASK_DRTOGGLE_sts_Pos)
+
+#define PLATFORM_REG_GPIO_0_TASK_DRTOGGLE_STS_r_GPIO0_31_TASK_DRTOGGLE_sts_Pos                               31U
+#define PLATFORM_REG_GPIO_0_TASK_DRTOGGLE_STS_r_GPIO0_31_TASK_DRTOGGLE_sts_Msk                               (0x1UL << PLATFORM_REG_GPIO_0_TASK_DRTOGGLE_STS_r_GPIO0_31_TASK_DRTOGGLE_sts_Pos)
+
+/* 0x0328   0x4000_6328
+    0       R/W1C   r_GPIO0_32_TASK_DRTOGGLE_sts                        1'b0
+    1       R/W1C   r_GPIO0_33_TASK_DRTOGGLE_sts                        1'b0
+    2       R/W1C   r_GPIO0_34_TASK_DRTOGGLE_sts                        1'b0
+    3       R/W1C   r_GPIO0_35_TASK_DRTOGGLE_sts                        1'b0
+    4       R/W1C   r_GPIO0_36_TASK_DRTOGGLE_sts                        1'b0
+    5       R/W1C   r_GPIO0_37_TASK_DRTOGGLE_sts                        1'b0
+    6       R/W1C   r_GPIO0_38_TASK_DRTOGGLE_sts                        1'b0
+    7       R/W1C   r_GPIO0_39_TASK_DRTOGGLE_sts                        1'b0
+    8       R/W1C   r_GPIO0_40_TASK_DRTOGGLE_sts                        1'b0
+    9       R/W1C   r_GPIO0_41_TASK_DRTOGGLE_sts                        1'b0
+    10      R/W1C   r_GPIO0_42_TASK_DRTOGGLE_sts                        1'b0
+    11      R/W1C   r_GPIO0_43_TASK_DRTOGGLE_sts                        1'b0
+    12      R/W1C   r_GPIO0_44_TASK_DRTOGGLE_sts                        1'b0
+    13      R/W1C   r_GPIO0_45_TASK_DRTOGGLE_sts                        1'b0
+    14      R/W1C   r_GPIO0_46_TASK_DRTOGGLE_sts                        1'b0
+    15      R/W1C   r_GPIO0_47_TASK_DRTOGGLE_sts                        1'b0
+    16      R/W1C   r_GPIO0_48_TASK_DRTOGGLE_sts                        1'b0
+    17      R/W1C   r_GPIO0_49_TASK_DRTOGGLE_sts                        1'b0
+    30:18   R       reserved                                            13'h0000
+    31      R       r_GPIO0_TASK_NOP_sts                                1'b0
+ */
+typedef union _PLATFORM_REG_GPIO_1_TASK_DRTOGGLE_STS_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t r_GPIO0_32_TASK_DRTOGGLE_sts: 1;
+        uint32_t r_GPIO0_33_TASK_DRTOGGLE_sts: 1;
+        uint32_t r_GPIO0_34_TASK_DRTOGGLE_sts: 1;
+        uint32_t r_GPIO0_35_TASK_DRTOGGLE_sts: 1;
+        uint32_t r_GPIO0_36_TASK_DRTOGGLE_sts: 1;
+        uint32_t r_GPIO0_37_TASK_DRTOGGLE_sts: 1;
+        uint32_t r_GPIO0_38_TASK_DRTOGGLE_sts: 1;
+        uint32_t r_GPIO0_39_TASK_DRTOGGLE_sts: 1;
+        uint32_t r_GPIO0_40_TASK_DRTOGGLE_sts: 1;
+        uint32_t r_GPIO0_41_TASK_DRTOGGLE_sts: 1;
+        uint32_t r_GPIO0_42_TASK_DRTOGGLE_sts: 1;
+        uint32_t r_GPIO0_43_TASK_DRTOGGLE_sts: 1;
+        uint32_t r_GPIO0_44_TASK_DRTOGGLE_sts: 1;
+        uint32_t r_GPIO0_45_TASK_DRTOGGLE_sts: 1;
+        uint32_t r_GPIO0_46_TASK_DRTOGGLE_sts: 1;
+        uint32_t r_GPIO0_47_TASK_DRTOGGLE_sts: 1;
+        uint32_t r_GPIO0_48_TASK_DRTOGGLE_sts: 1;
+        uint32_t r_GPIO0_49_TASK_DRTOGGLE_sts: 1;
+        uint32_t reserved: 13;
+        uint32_t r_GPIO0_TASK_NOP_sts: 1;
+    };
+} PLATFORM_REG_GPIO_1_TASK_DRTOGGLE_STS_TYPE;
+
+/*0x4000_6328 PLATFORM_REG_GPIO_1_TASK_DRTOGGLE_STS*/
+#define PLATFORM_REG_GPIO_1_TASK_DRTOGGLE_STS_r_GPIO0_32_TASK_DRTOGGLE_sts_Pos                               0U
+#define PLATFORM_REG_GPIO_1_TASK_DRTOGGLE_STS_r_GPIO0_32_TASK_DRTOGGLE_sts_Msk                               (0x1UL << PLATFORM_REG_GPIO_1_TASK_DRTOGGLE_STS_r_GPIO0_32_TASK_DRTOGGLE_sts_Pos)
+
+#define PLATFORM_REG_GPIO_1_TASK_DRTOGGLE_STS_r_GPIO0_33_TASK_DRTOGGLE_sts_Pos                               1U
+#define PLATFORM_REG_GPIO_1_TASK_DRTOGGLE_STS_r_GPIO0_33_TASK_DRTOGGLE_sts_Msk                               (0x1UL << PLATFORM_REG_GPIO_1_TASK_DRTOGGLE_STS_r_GPIO0_33_TASK_DRTOGGLE_sts_Pos)
+
+#define PLATFORM_REG_GPIO_1_TASK_DRTOGGLE_STS_r_GPIO0_34_TASK_DRTOGGLE_sts_Pos                               2U
+#define PLATFORM_REG_GPIO_1_TASK_DRTOGGLE_STS_r_GPIO0_34_TASK_DRTOGGLE_sts_Msk                               (0x1UL << PLATFORM_REG_GPIO_1_TASK_DRTOGGLE_STS_r_GPIO0_34_TASK_DRTOGGLE_sts_Pos)
+
+#define PLATFORM_REG_GPIO_1_TASK_DRTOGGLE_STS_r_GPIO0_35_TASK_DRTOGGLE_sts_Pos                               3U
+#define PLATFORM_REG_GPIO_1_TASK_DRTOGGLE_STS_r_GPIO0_35_TASK_DRTOGGLE_sts_Msk                               (0x1UL << PLATFORM_REG_GPIO_1_TASK_DRTOGGLE_STS_r_GPIO0_35_TASK_DRTOGGLE_sts_Pos)
+
+#define PLATFORM_REG_GPIO_1_TASK_DRTOGGLE_STS_r_GPIO0_36_TASK_DRTOGGLE_sts_Pos                               4U
+#define PLATFORM_REG_GPIO_1_TASK_DRTOGGLE_STS_r_GPIO0_36_TASK_DRTOGGLE_sts_Msk                               (0x1UL << PLATFORM_REG_GPIO_1_TASK_DRTOGGLE_STS_r_GPIO0_36_TASK_DRTOGGLE_sts_Pos)
+
+#define PLATFORM_REG_GPIO_1_TASK_DRTOGGLE_STS_r_GPIO0_37_TASK_DRTOGGLE_sts_Pos                               5U
+#define PLATFORM_REG_GPIO_1_TASK_DRTOGGLE_STS_r_GPIO0_37_TASK_DRTOGGLE_sts_Msk                               (0x1UL << PLATFORM_REG_GPIO_1_TASK_DRTOGGLE_STS_r_GPIO0_37_TASK_DRTOGGLE_sts_Pos)
+
+#define PLATFORM_REG_GPIO_1_TASK_DRTOGGLE_STS_r_GPIO0_38_TASK_DRTOGGLE_sts_Pos                               6U
+#define PLATFORM_REG_GPIO_1_TASK_DRTOGGLE_STS_r_GPIO0_38_TASK_DRTOGGLE_sts_Msk                               (0x1UL << PLATFORM_REG_GPIO_1_TASK_DRTOGGLE_STS_r_GPIO0_38_TASK_DRTOGGLE_sts_Pos)
+
+#define PLATFORM_REG_GPIO_1_TASK_DRTOGGLE_STS_r_GPIO0_39_TASK_DRTOGGLE_sts_Pos                               7U
+#define PLATFORM_REG_GPIO_1_TASK_DRTOGGLE_STS_r_GPIO0_39_TASK_DRTOGGLE_sts_Msk                               (0x1UL << PLATFORM_REG_GPIO_1_TASK_DRTOGGLE_STS_r_GPIO0_39_TASK_DRTOGGLE_sts_Pos)
+
+#define PLATFORM_REG_GPIO_1_TASK_DRTOGGLE_STS_r_GPIO0_40_TASK_DRTOGGLE_sts_Pos                               8U
+#define PLATFORM_REG_GPIO_1_TASK_DRTOGGLE_STS_r_GPIO0_40_TASK_DRTOGGLE_sts_Msk                               (0x1UL << PLATFORM_REG_GPIO_1_TASK_DRTOGGLE_STS_r_GPIO0_40_TASK_DRTOGGLE_sts_Pos)
+
+#define PLATFORM_REG_GPIO_1_TASK_DRTOGGLE_STS_r_GPIO0_41_TASK_DRTOGGLE_sts_Pos                               9U
+#define PLATFORM_REG_GPIO_1_TASK_DRTOGGLE_STS_r_GPIO0_41_TASK_DRTOGGLE_sts_Msk                               (0x1UL << PLATFORM_REG_GPIO_1_TASK_DRTOGGLE_STS_r_GPIO0_41_TASK_DRTOGGLE_sts_Pos)
+
+#define PLATFORM_REG_GPIO_1_TASK_DRTOGGLE_STS_r_GPIO0_42_TASK_DRTOGGLE_sts_Pos                               10U
+#define PLATFORM_REG_GPIO_1_TASK_DRTOGGLE_STS_r_GPIO0_42_TASK_DRTOGGLE_sts_Msk                               (0x1UL << PLATFORM_REG_GPIO_1_TASK_DRTOGGLE_STS_r_GPIO0_42_TASK_DRTOGGLE_sts_Pos)
+
+#define PLATFORM_REG_GPIO_1_TASK_DRTOGGLE_STS_r_GPIO0_43_TASK_DRTOGGLE_sts_Pos                               11U
+#define PLATFORM_REG_GPIO_1_TASK_DRTOGGLE_STS_r_GPIO0_43_TASK_DRTOGGLE_sts_Msk                               (0x1UL << PLATFORM_REG_GPIO_1_TASK_DRTOGGLE_STS_r_GPIO0_43_TASK_DRTOGGLE_sts_Pos)
+
+#define PLATFORM_REG_GPIO_1_TASK_DRTOGGLE_STS_r_GPIO0_44_TASK_DRTOGGLE_sts_Pos                               12U
+#define PLATFORM_REG_GPIO_1_TASK_DRTOGGLE_STS_r_GPIO0_44_TASK_DRTOGGLE_sts_Msk                               (0x1UL << PLATFORM_REG_GPIO_1_TASK_DRTOGGLE_STS_r_GPIO0_44_TASK_DRTOGGLE_sts_Pos)
+
+#define PLATFORM_REG_GPIO_1_TASK_DRTOGGLE_STS_r_GPIO0_45_TASK_DRTOGGLE_sts_Pos                               13U
+#define PLATFORM_REG_GPIO_1_TASK_DRTOGGLE_STS_r_GPIO0_45_TASK_DRTOGGLE_sts_Msk                               (0x1UL << PLATFORM_REG_GPIO_1_TASK_DRTOGGLE_STS_r_GPIO0_45_TASK_DRTOGGLE_sts_Pos)
+
+#define PLATFORM_REG_GPIO_1_TASK_DRTOGGLE_STS_r_GPIO0_46_TASK_DRTOGGLE_sts_Pos                               14U
+#define PLATFORM_REG_GPIO_1_TASK_DRTOGGLE_STS_r_GPIO0_46_TASK_DRTOGGLE_sts_Msk                               (0x1UL << PLATFORM_REG_GPIO_1_TASK_DRTOGGLE_STS_r_GPIO0_46_TASK_DRTOGGLE_sts_Pos)
+
+#define PLATFORM_REG_GPIO_1_TASK_DRTOGGLE_STS_r_GPIO0_47_TASK_DRTOGGLE_sts_Pos                               15U
+#define PLATFORM_REG_GPIO_1_TASK_DRTOGGLE_STS_r_GPIO0_47_TASK_DRTOGGLE_sts_Msk                               (0x1UL << PLATFORM_REG_GPIO_1_TASK_DRTOGGLE_STS_r_GPIO0_47_TASK_DRTOGGLE_sts_Pos)
+
+#define PLATFORM_REG_GPIO_1_TASK_DRTOGGLE_STS_r_GPIO0_48_TASK_DRTOGGLE_sts_Pos                               16U
+#define PLATFORM_REG_GPIO_1_TASK_DRTOGGLE_STS_r_GPIO0_48_TASK_DRTOGGLE_sts_Msk                               (0x1UL << PLATFORM_REG_GPIO_1_TASK_DRTOGGLE_STS_r_GPIO0_48_TASK_DRTOGGLE_sts_Pos)
+
+#define PLATFORM_REG_GPIO_1_TASK_DRTOGGLE_STS_r_GPIO0_49_TASK_DRTOGGLE_sts_Pos                               17U
+#define PLATFORM_REG_GPIO_1_TASK_DRTOGGLE_STS_r_GPIO0_49_TASK_DRTOGGLE_sts_Msk                               (0x1UL << PLATFORM_REG_GPIO_1_TASK_DRTOGGLE_STS_r_GPIO0_49_TASK_DRTOGGLE_sts_Pos)
+
+#define PLATFORM_REG_GPIO_1_TASK_DRTOGGLE_STS_reserved_Pos                                                   18U
+#define PLATFORM_REG_GPIO_1_TASK_DRTOGGLE_STS_reserved_Msk                                                   (0x1FFFUL << PLATFORM_REG_GPIO_1_TASK_DRTOGGLE_STS_reserved_Pos)
+
+#define PLATFORM_REG_GPIO_1_TASK_DRTOGGLE_STS_r_GPIO0_TASK_NOP_sts_Pos                                       31U
+#define PLATFORM_REG_GPIO_1_TASK_DRTOGGLE_STS_r_GPIO0_TASK_NOP_sts_Msk                                       (0x1UL << PLATFORM_REG_GPIO_1_TASK_DRTOGGLE_STS_r_GPIO0_TASK_NOP_sts_Pos)
+
+/* 0x0344   0x4000_6344
+    0       R/W1C   r_GIRDA_EVNT_TXDONE_sts                             1'b0
+    1       R/W1C   r_GIRDA_EVNT_RXDONE_sts                             1'b0
+    15:2    R       reserved_1                                          14'h0000
+    16      R/W1C   r_GIRDA_TASK_START_TX_sts                           1'b0
+    17      R/W1C   r_GIRDA_TASK_START_RX_sts                           1'b0
+    31:18   R       reserved                                            14'h0000
+ */
+typedef union _PLATFORM_REG_GIRDA_TASK_EVNT_STS_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t r_GIRDA_EVNT_TXDONE_sts: 1;
+        uint32_t r_GIRDA_EVNT_RXDONE_sts: 1;
+        uint32_t reserved_1: 14;
+        uint32_t r_GIRDA_TASK_START_TX_sts: 1;
+        uint32_t r_GIRDA_TASK_START_RX_sts: 1;
+        uint32_t reserved: 14;
+    };
+} PLATFORM_REG_GIRDA_TASK_EVNT_STS_TYPE;
+
+/*0x4000_6344 PLATFORM_REG_GIRDA_TASK_EVNT_STS*/
+#define PLATFORM_REG_GIRDA_TASK_EVNT_STS_r_GIRDA_EVNT_TXDONE_sts_Pos                                         0U
+#define PLATFORM_REG_GIRDA_TASK_EVNT_STS_r_GIRDA_EVNT_TXDONE_sts_Msk                                         (0x1UL << PLATFORM_REG_GIRDA_TASK_EVNT_STS_r_GIRDA_EVNT_TXDONE_sts_Pos)
+
+#define PLATFORM_REG_GIRDA_TASK_EVNT_STS_r_GIRDA_EVNT_RXDONE_sts_Pos                                         1U
+#define PLATFORM_REG_GIRDA_TASK_EVNT_STS_r_GIRDA_EVNT_RXDONE_sts_Msk                                         (0x1UL << PLATFORM_REG_GIRDA_TASK_EVNT_STS_r_GIRDA_EVNT_RXDONE_sts_Pos)
+
+#define PLATFORM_REG_GIRDA_TASK_EVNT_STS_reserved_1_Pos                                                      2U
+#define PLATFORM_REG_GIRDA_TASK_EVNT_STS_reserved_1_Msk                                                      (0x3FFFUL << PLATFORM_REG_GIRDA_TASK_EVNT_STS_reserved_1_Pos)
+
+#define PLATFORM_REG_GIRDA_TASK_EVNT_STS_r_GIRDA_TASK_START_TX_sts_Pos                                       16U
+#define PLATFORM_REG_GIRDA_TASK_EVNT_STS_r_GIRDA_TASK_START_TX_sts_Msk                                       (0x1UL << PLATFORM_REG_GIRDA_TASK_EVNT_STS_r_GIRDA_TASK_START_TX_sts_Pos)
+
+#define PLATFORM_REG_GIRDA_TASK_EVNT_STS_r_GIRDA_TASK_START_RX_sts_Pos                                       17U
+#define PLATFORM_REG_GIRDA_TASK_EVNT_STS_r_GIRDA_TASK_START_RX_sts_Msk                                       (0x1UL << PLATFORM_REG_GIRDA_TASK_EVNT_STS_r_GIRDA_TASK_START_RX_sts_Pos)
+
+#define PLATFORM_REG_GIRDA_TASK_EVNT_STS_reserved_Pos                                                        18U
+#define PLATFORM_REG_GIRDA_TASK_EVNT_STS_reserved_Msk                                                        (0x3FFFUL << PLATFORM_REG_GIRDA_TASK_EVNT_STS_reserved_Pos)
+
+/* 0x0348   0x4000_6348
+    0       R/W1C   r_I2C0_EVNT_ERROR_sts                               1'b0
+    1       R/W1C   r_I2C0_EVNT_STARTED_sts                             1'b0
+    2       R/W1C   r_I2C0_EVNT_STOPPED_sts                             1'b0
+    15:3    R       reserved_1                                          13'h0000
+    16      R/W1C   r_I2C0_TASK_START_sts                               1'b0
+    31:17   R       reserved                                            15'h0000
+ */
+typedef union _PLATFORM_REG_I2C0_TASK_EVNT_STS_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t r_I2C0_EVNT_ERROR_sts: 1;
+        uint32_t r_I2C0_EVNT_STARTED_sts: 1;
+        uint32_t r_I2C0_EVNT_STOPPED_sts: 1;
+        uint32_t reserved_1: 13;
+        uint32_t r_I2C0_TASK_START_sts: 1;
+        uint32_t reserved: 15;
+    };
+} PLATFORM_REG_I2C0_TASK_EVNT_STS_TYPE;
+
+/*0x4000_6348 PLATFORM_REG_I2C0_TASK_EVNT_STS*/
+#define PLATFORM_REG_I2C0_TASK_EVNT_STS_r_I2C0_EVNT_ERROR_sts_Pos                                            0U
+#define PLATFORM_REG_I2C0_TASK_EVNT_STS_r_I2C0_EVNT_ERROR_sts_Msk                                            (0x1UL << PLATFORM_REG_I2C0_TASK_EVNT_STS_r_I2C0_EVNT_ERROR_sts_Pos)
+
+#define PLATFORM_REG_I2C0_TASK_EVNT_STS_r_I2C0_EVNT_STARTED_sts_Pos                                          1U
+#define PLATFORM_REG_I2C0_TASK_EVNT_STS_r_I2C0_EVNT_STARTED_sts_Msk                                          (0x1UL << PLATFORM_REG_I2C0_TASK_EVNT_STS_r_I2C0_EVNT_STARTED_sts_Pos)
+
+#define PLATFORM_REG_I2C0_TASK_EVNT_STS_r_I2C0_EVNT_STOPPED_sts_Pos                                          2U
+#define PLATFORM_REG_I2C0_TASK_EVNT_STS_r_I2C0_EVNT_STOPPED_sts_Msk                                          (0x1UL << PLATFORM_REG_I2C0_TASK_EVNT_STS_r_I2C0_EVNT_STOPPED_sts_Pos)
+
+#define PLATFORM_REG_I2C0_TASK_EVNT_STS_reserved_1_Pos                                                       3U
+#define PLATFORM_REG_I2C0_TASK_EVNT_STS_reserved_1_Msk                                                       (0x1FFFUL << PLATFORM_REG_I2C0_TASK_EVNT_STS_reserved_1_Pos)
+
+#define PLATFORM_REG_I2C0_TASK_EVNT_STS_r_I2C0_TASK_START_sts_Pos                                            16U
+#define PLATFORM_REG_I2C0_TASK_EVNT_STS_r_I2C0_TASK_START_sts_Msk                                            (0x1UL << PLATFORM_REG_I2C0_TASK_EVNT_STS_r_I2C0_TASK_START_sts_Pos)
+
+#define PLATFORM_REG_I2C0_TASK_EVNT_STS_reserved_Pos                                                         17U
+#define PLATFORM_REG_I2C0_TASK_EVNT_STS_reserved_Msk                                                         (0x7FFFUL << PLATFORM_REG_I2C0_TASK_EVNT_STS_reserved_Pos)
+
+/* 0x034c   0x4000_634c
+    0       R/W1C   r_I2C1_EVNT_ERROR_sts                               1'b0
+    1       R/W1C   r_I2C1_EVNT_STARTED_sts                             1'b0
+    2       R/W1C   r_I2C1_EVNT_STOPPED_sts                             1'b0
+    15:3    R       reserved_1                                          13'h0000
+    16      R/W1C   r_I2C1_TASK_START_sts                               1'b0
+    31:17   R       reserved                                            15'h0000
+ */
+typedef union _PLATFORM_REG_I2C1_TASK_EVNT_STS_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t r_I2C1_EVNT_ERROR_sts: 1;
+        uint32_t r_I2C1_EVNT_STARTED_sts: 1;
+        uint32_t r_I2C1_EVNT_STOPPED_sts: 1;
+        uint32_t reserved_1: 13;
+        uint32_t r_I2C1_TASK_START_sts: 1;
+        uint32_t reserved: 15;
+    };
+} PLATFORM_REG_I2C1_TASK_EVNT_STS_TYPE;
+
+/*0x4000_634c PLATFORM_REG_I2C1_TASK_EVNT_STS*/
+#define PLATFORM_REG_I2C1_TASK_EVNT_STS_r_I2C1_EVNT_ERROR_sts_Pos                                            0U
+#define PLATFORM_REG_I2C1_TASK_EVNT_STS_r_I2C1_EVNT_ERROR_sts_Msk                                            (0x1UL << PLATFORM_REG_I2C1_TASK_EVNT_STS_r_I2C1_EVNT_ERROR_sts_Pos)
+
+#define PLATFORM_REG_I2C1_TASK_EVNT_STS_r_I2C1_EVNT_STARTED_sts_Pos                                          1U
+#define PLATFORM_REG_I2C1_TASK_EVNT_STS_r_I2C1_EVNT_STARTED_sts_Msk                                          (0x1UL << PLATFORM_REG_I2C1_TASK_EVNT_STS_r_I2C1_EVNT_STARTED_sts_Pos)
+
+#define PLATFORM_REG_I2C1_TASK_EVNT_STS_r_I2C1_EVNT_STOPPED_sts_Pos                                          2U
+#define PLATFORM_REG_I2C1_TASK_EVNT_STS_r_I2C1_EVNT_STOPPED_sts_Msk                                          (0x1UL << PLATFORM_REG_I2C1_TASK_EVNT_STS_r_I2C1_EVNT_STOPPED_sts_Pos)
+
+#define PLATFORM_REG_I2C1_TASK_EVNT_STS_reserved_1_Pos                                                       3U
+#define PLATFORM_REG_I2C1_TASK_EVNT_STS_reserved_1_Msk                                                       (0x1FFFUL << PLATFORM_REG_I2C1_TASK_EVNT_STS_reserved_1_Pos)
+
+#define PLATFORM_REG_I2C1_TASK_EVNT_STS_r_I2C1_TASK_START_sts_Pos                                            16U
+#define PLATFORM_REG_I2C1_TASK_EVNT_STS_r_I2C1_TASK_START_sts_Msk                                            (0x1UL << PLATFORM_REG_I2C1_TASK_EVNT_STS_r_I2C1_TASK_START_sts_Pos)
+
+#define PLATFORM_REG_I2C1_TASK_EVNT_STS_reserved_Pos                                                         17U
+#define PLATFORM_REG_I2C1_TASK_EVNT_STS_reserved_Msk                                                         (0x7FFFUL << PLATFORM_REG_I2C1_TASK_EVNT_STS_reserved_Pos)
+
+/* 0x0350   0x4000_6350
+    0       R/W1C   r_AUXADC_EVNT_DONE_sts                              1'b0
+    15:1    R       reserved_1                                          15'h0000
+    16      R/W1C   r_AUXADC_TASK_ONE_SHOT_SAMPLE_sts                   1'b0
+    31:17   R       reserved                                            15'h0000
+ */
+typedef union _PLATFORM_REG_AUXADC_TASK_EVNT_STS_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t r_AUXADC_EVNT_DONE_sts: 1;
+        uint32_t reserved_1: 15;
+        uint32_t r_AUXADC_TASK_ONE_SHOT_SAMPLE_sts: 1;
+        uint32_t reserved: 15;
+    };
+} PLATFORM_REG_AUXADC_TASK_EVNT_STS_TYPE;
+
+/*0x4000_6350 PLATFORM_REG_AUXADC_TASK_EVNT_STS*/
+#define PLATFORM_REG_AUXADC_TASK_EVNT_STS_r_AUXADC_EVNT_DONE_sts_Pos                                         0U
+#define PLATFORM_REG_AUXADC_TASK_EVNT_STS_r_AUXADC_EVNT_DONE_sts_Msk                                         (0x1UL << PLATFORM_REG_AUXADC_TASK_EVNT_STS_r_AUXADC_EVNT_DONE_sts_Pos)
+
+#define PLATFORM_REG_AUXADC_TASK_EVNT_STS_reserved_1_Pos                                                     1U
+#define PLATFORM_REG_AUXADC_TASK_EVNT_STS_reserved_1_Msk                                                     (0x7FFFUL << PLATFORM_REG_AUXADC_TASK_EVNT_STS_reserved_1_Pos)
+
+#define PLATFORM_REG_AUXADC_TASK_EVNT_STS_r_AUXADC_TASK_ONE_SHOT_SAMPLE_sts_Pos                              16U
+#define PLATFORM_REG_AUXADC_TASK_EVNT_STS_r_AUXADC_TASK_ONE_SHOT_SAMPLE_sts_Msk                              (0x1UL << PLATFORM_REG_AUXADC_TASK_EVNT_STS_r_AUXADC_TASK_ONE_SHOT_SAMPLE_sts_Pos)
+
+#define PLATFORM_REG_AUXADC_TASK_EVNT_STS_reserved_Pos                                                       17U
+#define PLATFORM_REG_AUXADC_TASK_EVNT_STS_reserved_Msk                                                       (0x7FFFUL << PLATFORM_REG_AUXADC_TASK_EVNT_STS_reserved_Pos)
+
+/* 0x0354   0x4000_6354
+    0       R/W1C   r_SPI3W_EVNT_END_sts                                1'b0
+    15:1    R       reserved_1                                          15'h0000
+    16      R/W1C   r_SPI3W_TASK_START_sts                              1'b0
+    31:17   R       reserved                                            15'h0000
+ */
+typedef union _PLATFORM_REG_SPI3WIRE_TASK_EVNT_STS_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t r_SPI3W_EVNT_END_sts: 1;
+        uint32_t reserved_1: 15;
+        uint32_t r_SPI3W_TASK_START_sts: 1;
+        uint32_t reserved: 15;
+    };
+} PLATFORM_REG_SPI3WIRE_TASK_EVNT_STS_TYPE;
+
+/*0x4000_6354 PLATFORM_REG_SPI3WIRE_TASK_EVNT_STS*/
+#define PLATFORM_REG_SPI3WIRE_TASK_EVNT_STS_r_SPI3W_EVNT_END_sts_Pos                                         0U
+#define PLATFORM_REG_SPI3WIRE_TASK_EVNT_STS_r_SPI3W_EVNT_END_sts_Msk                                         (0x1UL << PLATFORM_REG_SPI3WIRE_TASK_EVNT_STS_r_SPI3W_EVNT_END_sts_Pos)
+
+#define PLATFORM_REG_SPI3WIRE_TASK_EVNT_STS_reserved_1_Pos                                                   1U
+#define PLATFORM_REG_SPI3WIRE_TASK_EVNT_STS_reserved_1_Msk                                                   (0x7FFFUL << PLATFORM_REG_SPI3WIRE_TASK_EVNT_STS_reserved_1_Pos)
+
+#define PLATFORM_REG_SPI3WIRE_TASK_EVNT_STS_r_SPI3W_TASK_START_sts_Pos                                       16U
+#define PLATFORM_REG_SPI3WIRE_TASK_EVNT_STS_r_SPI3W_TASK_START_sts_Msk                                       (0x1UL << PLATFORM_REG_SPI3WIRE_TASK_EVNT_STS_r_SPI3W_TASK_START_sts_Pos)
+
+#define PLATFORM_REG_SPI3WIRE_TASK_EVNT_STS_reserved_Pos                                                     17U
+#define PLATFORM_REG_SPI3WIRE_TASK_EVNT_STS_reserved_Msk                                                     (0x7FFFUL << PLATFORM_REG_SPI3WIRE_TASK_EVNT_STS_reserved_Pos)
+
+/* 0x0358   0x4000_6358
+    0       R/W1C   r_SPI0_EVNT_START_sts                               1'b0
+    1       R/W1C   r_SPI0_EVNT_END_sts                                 1'b0
+    15:2    R       reserved_1                                          14'h0000
+    16      R/W1C   r_SPI0_TASK_START_sts                               1'b0
+    31:17   R       reserved                                            15'h0000
+ */
+typedef union _PLATFORM_REG_SPI0DUAL_TASK_EVNT_STS_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t r_SPI0_EVNT_START_sts: 1;
+        uint32_t r_SPI0_EVNT_END_sts: 1;
+        uint32_t reserved_1: 14;
+        uint32_t r_SPI0_TASK_START_sts: 1;
+        uint32_t reserved: 15;
+    };
+} PLATFORM_REG_SPI0DUAL_TASK_EVNT_STS_TYPE;
+
+/*0x4000_6358 PLATFORM_REG_SPI0DUAL_TASK_EVNT_STS*/
+#define PLATFORM_REG_SPI0DUAL_TASK_EVNT_STS_r_SPI0_EVNT_START_sts_Pos                                        0U
+#define PLATFORM_REG_SPI0DUAL_TASK_EVNT_STS_r_SPI0_EVNT_START_sts_Msk                                        (0x1UL << PLATFORM_REG_SPI0DUAL_TASK_EVNT_STS_r_SPI0_EVNT_START_sts_Pos)
+
+#define PLATFORM_REG_SPI0DUAL_TASK_EVNT_STS_r_SPI0_EVNT_END_sts_Pos                                          1U
+#define PLATFORM_REG_SPI0DUAL_TASK_EVNT_STS_r_SPI0_EVNT_END_sts_Msk                                          (0x1UL << PLATFORM_REG_SPI0DUAL_TASK_EVNT_STS_r_SPI0_EVNT_END_sts_Pos)
+
+#define PLATFORM_REG_SPI0DUAL_TASK_EVNT_STS_reserved_1_Pos                                                   2U
+#define PLATFORM_REG_SPI0DUAL_TASK_EVNT_STS_reserved_1_Msk                                                   (0x3FFFUL << PLATFORM_REG_SPI0DUAL_TASK_EVNT_STS_reserved_1_Pos)
+
+#define PLATFORM_REG_SPI0DUAL_TASK_EVNT_STS_r_SPI0_TASK_START_sts_Pos                                        16U
+#define PLATFORM_REG_SPI0DUAL_TASK_EVNT_STS_r_SPI0_TASK_START_sts_Msk                                        (0x1UL << PLATFORM_REG_SPI0DUAL_TASK_EVNT_STS_r_SPI0_TASK_START_sts_Pos)
+
+#define PLATFORM_REG_SPI0DUAL_TASK_EVNT_STS_reserved_Pos                                                     17U
+#define PLATFORM_REG_SPI0DUAL_TASK_EVNT_STS_reserved_Msk                                                     (0x7FFFUL << PLATFORM_REG_SPI0DUAL_TASK_EVNT_STS_reserved_Pos)
+
+/* 0x035c   0x4000_635c
+    0       R/W1C   r_SPI1_EVNT_START_sts                               1'b0
+    1       R/W1C   r_SPI1_EVNT_END_sts                                 1'b0
+    15:2    R       reserved_1                                          14'h0000
+    16      R/W1C   r_SPI1_TASK_START_sts                               1'b0
+    31:17   R       reserved                                            15'h0000
+ */
+typedef union _PLATFORM_REG_SPI1MST_TASK_EVNT_STS_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t r_SPI1_EVNT_START_sts: 1;
+        uint32_t r_SPI1_EVNT_END_sts: 1;
+        uint32_t reserved_1: 14;
+        uint32_t r_SPI1_TASK_START_sts: 1;
+        uint32_t reserved: 15;
+    };
+} PLATFORM_REG_SPI1MST_TASK_EVNT_STS_TYPE;
+
+/*0x4000_635c PLATFORM_REG_SPI1MST_TASK_EVNT_STS*/
+#define PLATFORM_REG_SPI1MST_TASK_EVNT_STS_r_SPI1_EVNT_START_sts_Pos                                         0U
+#define PLATFORM_REG_SPI1MST_TASK_EVNT_STS_r_SPI1_EVNT_START_sts_Msk                                         (0x1UL << PLATFORM_REG_SPI1MST_TASK_EVNT_STS_r_SPI1_EVNT_START_sts_Pos)
+
+#define PLATFORM_REG_SPI1MST_TASK_EVNT_STS_r_SPI1_EVNT_END_sts_Pos                                           1U
+#define PLATFORM_REG_SPI1MST_TASK_EVNT_STS_r_SPI1_EVNT_END_sts_Msk                                           (0x1UL << PLATFORM_REG_SPI1MST_TASK_EVNT_STS_r_SPI1_EVNT_END_sts_Pos)
+
+#define PLATFORM_REG_SPI1MST_TASK_EVNT_STS_reserved_1_Pos                                                    2U
+#define PLATFORM_REG_SPI1MST_TASK_EVNT_STS_reserved_1_Msk                                                    (0x3FFFUL << PLATFORM_REG_SPI1MST_TASK_EVNT_STS_reserved_1_Pos)
+
+#define PLATFORM_REG_SPI1MST_TASK_EVNT_STS_r_SPI1_TASK_START_sts_Pos                                         16U
+#define PLATFORM_REG_SPI1MST_TASK_EVNT_STS_r_SPI1_TASK_START_sts_Msk                                         (0x1UL << PLATFORM_REG_SPI1MST_TASK_EVNT_STS_r_SPI1_TASK_START_sts_Pos)
+
+#define PLATFORM_REG_SPI1MST_TASK_EVNT_STS_reserved_Pos                                                      17U
+#define PLATFORM_REG_SPI1MST_TASK_EVNT_STS_reserved_Msk                                                      (0x7FFFUL << PLATFORM_REG_SPI1MST_TASK_EVNT_STS_reserved_Pos)
+
+/* 0x0364   0x4000_6364
+    0       R/W1C   r_METER_EVNT_DATARDY_sts                            1'b0
+    1       R/W1C   r_METER_EVNT_ABS_COMP0_sts                          1'b0
+    2       R/W1C   r_METER_EVNT_ABS_COMP1_sts                          1'b0
+    3       R/W1C   r_METER_EVNT_ABS_COMP2_sts                          1'b0
+    4       R/W1C   r_METER_EVNT_ABS_COMP3_sts                          1'b0
+    5       R/W1C   r_METER_EVNT_REL_COMP0_sts                          1'b0
+    6       R/W1C   r_METER_EVNT_REL_COMP1_sts                          1'b0
+    7       R/W1C   r_METER_EVNT_REL_COMP2_sts                          1'b0
+    8       R/W1C   r_METER_EVNT_REL_COMP3_sts                          1'b0
+    9       R/W1C   r_METER_EVNT_FW_REL_COMP_sts                        1'b0
+    15:10   R       reserved_1                                          6'h0
+    16      R/W1C   r_METER_TASK_ONE_SHOT_sts                           1'b0
+    31:17   R       reserved                                            15'h0000
+ */
+typedef union _PLATFORM_REG_TMETER_TASK_EVNT_STS_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t r_METER_EVNT_DATARDY_sts: 1;
+        uint32_t r_METER_EVNT_ABS_COMP0_sts: 1;
+        uint32_t r_METER_EVNT_ABS_COMP1_sts: 1;
+        uint32_t r_METER_EVNT_ABS_COMP2_sts: 1;
+        uint32_t r_METER_EVNT_ABS_COMP3_sts: 1;
+        uint32_t r_METER_EVNT_REL_COMP0_sts: 1;
+        uint32_t r_METER_EVNT_REL_COMP1_sts: 1;
+        uint32_t r_METER_EVNT_REL_COMP2_sts: 1;
+        uint32_t r_METER_EVNT_REL_COMP3_sts: 1;
+        uint32_t r_METER_EVNT_FW_REL_COMP_sts: 1;
+        uint32_t reserved_1: 6;
+        uint32_t r_METER_TASK_ONE_SHOT_sts: 1;
+        uint32_t reserved: 15;
+    };
+} PLATFORM_REG_TMETER_TASK_EVNT_STS_TYPE;
+
+/*0x4000_6364 PLATFORM_REG_TMETER_TASK_EVNT_STS*/
+#define PLATFORM_REG_TMETER_TASK_EVNT_STS_r_METER_EVNT_DATARDY_sts_Pos                                       0U
+#define PLATFORM_REG_TMETER_TASK_EVNT_STS_r_METER_EVNT_DATARDY_sts_Msk                                       (0x1UL << PLATFORM_REG_TMETER_TASK_EVNT_STS_r_METER_EVNT_DATARDY_sts_Pos)
+
+#define PLATFORM_REG_TMETER_TASK_EVNT_STS_r_METER_EVNT_ABS_COMP0_sts_Pos                                     1U
+#define PLATFORM_REG_TMETER_TASK_EVNT_STS_r_METER_EVNT_ABS_COMP0_sts_Msk                                     (0x1UL << PLATFORM_REG_TMETER_TASK_EVNT_STS_r_METER_EVNT_ABS_COMP0_sts_Pos)
+
+#define PLATFORM_REG_TMETER_TASK_EVNT_STS_r_METER_EVNT_ABS_COMP1_sts_Pos                                     2U
+#define PLATFORM_REG_TMETER_TASK_EVNT_STS_r_METER_EVNT_ABS_COMP1_sts_Msk                                     (0x1UL << PLATFORM_REG_TMETER_TASK_EVNT_STS_r_METER_EVNT_ABS_COMP1_sts_Pos)
+
+#define PLATFORM_REG_TMETER_TASK_EVNT_STS_r_METER_EVNT_ABS_COMP2_sts_Pos                                     3U
+#define PLATFORM_REG_TMETER_TASK_EVNT_STS_r_METER_EVNT_ABS_COMP2_sts_Msk                                     (0x1UL << PLATFORM_REG_TMETER_TASK_EVNT_STS_r_METER_EVNT_ABS_COMP2_sts_Pos)
+
+#define PLATFORM_REG_TMETER_TASK_EVNT_STS_r_METER_EVNT_ABS_COMP3_sts_Pos                                     4U
+#define PLATFORM_REG_TMETER_TASK_EVNT_STS_r_METER_EVNT_ABS_COMP3_sts_Msk                                     (0x1UL << PLATFORM_REG_TMETER_TASK_EVNT_STS_r_METER_EVNT_ABS_COMP3_sts_Pos)
+
+#define PLATFORM_REG_TMETER_TASK_EVNT_STS_r_METER_EVNT_REL_COMP0_sts_Pos                                     5U
+#define PLATFORM_REG_TMETER_TASK_EVNT_STS_r_METER_EVNT_REL_COMP0_sts_Msk                                     (0x1UL << PLATFORM_REG_TMETER_TASK_EVNT_STS_r_METER_EVNT_REL_COMP0_sts_Pos)
+
+#define PLATFORM_REG_TMETER_TASK_EVNT_STS_r_METER_EVNT_REL_COMP1_sts_Pos                                     6U
+#define PLATFORM_REG_TMETER_TASK_EVNT_STS_r_METER_EVNT_REL_COMP1_sts_Msk                                     (0x1UL << PLATFORM_REG_TMETER_TASK_EVNT_STS_r_METER_EVNT_REL_COMP1_sts_Pos)
+
+#define PLATFORM_REG_TMETER_TASK_EVNT_STS_r_METER_EVNT_REL_COMP2_sts_Pos                                     7U
+#define PLATFORM_REG_TMETER_TASK_EVNT_STS_r_METER_EVNT_REL_COMP2_sts_Msk                                     (0x1UL << PLATFORM_REG_TMETER_TASK_EVNT_STS_r_METER_EVNT_REL_COMP2_sts_Pos)
+
+#define PLATFORM_REG_TMETER_TASK_EVNT_STS_r_METER_EVNT_REL_COMP3_sts_Pos                                     8U
+#define PLATFORM_REG_TMETER_TASK_EVNT_STS_r_METER_EVNT_REL_COMP3_sts_Msk                                     (0x1UL << PLATFORM_REG_TMETER_TASK_EVNT_STS_r_METER_EVNT_REL_COMP3_sts_Pos)
+
+#define PLATFORM_REG_TMETER_TASK_EVNT_STS_r_METER_EVNT_FW_REL_COMP_sts_Pos                                   9U
+#define PLATFORM_REG_TMETER_TASK_EVNT_STS_r_METER_EVNT_FW_REL_COMP_sts_Msk                                   (0x1UL << PLATFORM_REG_TMETER_TASK_EVNT_STS_r_METER_EVNT_FW_REL_COMP_sts_Pos)
+
+#define PLATFORM_REG_TMETER_TASK_EVNT_STS_reserved_1_Pos                                                     10U
+#define PLATFORM_REG_TMETER_TASK_EVNT_STS_reserved_1_Msk                                                     (0x3FUL << PLATFORM_REG_TMETER_TASK_EVNT_STS_reserved_1_Pos)
+
+#define PLATFORM_REG_TMETER_TASK_EVNT_STS_r_METER_TASK_ONE_SHOT_sts_Pos                                      16U
+#define PLATFORM_REG_TMETER_TASK_EVNT_STS_r_METER_TASK_ONE_SHOT_sts_Msk                                      (0x1UL << PLATFORM_REG_TMETER_TASK_EVNT_STS_r_METER_TASK_ONE_SHOT_sts_Pos)
+
+#define PLATFORM_REG_TMETER_TASK_EVNT_STS_reserved_Pos                                                       17U
+#define PLATFORM_REG_TMETER_TASK_EVNT_STS_reserved_Msk                                                       (0x7FFFUL << PLATFORM_REG_TMETER_TASK_EVNT_STS_reserved_Pos)
+
+/* 0x0368   0x4000_6368
+    0       R/W1C   r_DMA_EVNT_INT_TFR3_sts                             1'b0
+    1       R/W1C   r_DMA_EVNT_INT_TFR4_sts                             1'b0
+    2       R/W1C   r_DMA_EVNT_INT_BLK3_sts                             1'b0
+    3       R/W1C   r_DMA_EVNT_INT_BLK4_sts                             1'b0
+    15:4    R       reserved_1                                          12'd0
+    16      R/W1C   r_DMA_TASK_CHN_EN3_sts                              1'b0
+    17      R/W1C   r_DMA_TASK_CHN_EN4_sts                              1'b0
+    31:18   R       reserved                                            14'd0
+ */
+typedef union _PLATFORM_REG_DMA_TASK_EVNT_STS_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t r_DMA_EVNT_INT_TFR3_sts: 1;
+        uint32_t r_DMA_EVNT_INT_TFR4_sts: 1;
+        uint32_t r_DMA_EVNT_INT_BLK3_sts: 1;
+        uint32_t r_DMA_EVNT_INT_BLK4_sts: 1;
+        uint32_t reserved_1: 12;
+        uint32_t r_DMA_TASK_CHN_EN3_sts: 1;
+        uint32_t r_DMA_TASK_CHN_EN4_sts: 1;
+        uint32_t reserved: 14;
+    };
+} PLATFORM_REG_DMA_TASK_EVNT_STS_TYPE;
+
+/*0x4000_6368 PLATFORM_REG_DMA_TASK_EVNT_STS*/
+#define PLATFORM_REG_DMA_TASK_EVNT_STS_r_DMA_EVNT_INT_TFR3_sts_Pos                                           0U
+#define PLATFORM_REG_DMA_TASK_EVNT_STS_r_DMA_EVNT_INT_TFR3_sts_Msk                                           (0x1UL << PLATFORM_REG_DMA_TASK_EVNT_STS_r_DMA_EVNT_INT_TFR3_sts_Pos)
+
+#define PLATFORM_REG_DMA_TASK_EVNT_STS_r_DMA_EVNT_INT_TFR4_sts_Pos                                           1U
+#define PLATFORM_REG_DMA_TASK_EVNT_STS_r_DMA_EVNT_INT_TFR4_sts_Msk                                           (0x1UL << PLATFORM_REG_DMA_TASK_EVNT_STS_r_DMA_EVNT_INT_TFR4_sts_Pos)
+
+#define PLATFORM_REG_DMA_TASK_EVNT_STS_r_DMA_EVNT_INT_BLK3_sts_Pos                                           2U
+#define PLATFORM_REG_DMA_TASK_EVNT_STS_r_DMA_EVNT_INT_BLK3_sts_Msk                                           (0x1UL << PLATFORM_REG_DMA_TASK_EVNT_STS_r_DMA_EVNT_INT_BLK3_sts_Pos)
+
+#define PLATFORM_REG_DMA_TASK_EVNT_STS_r_DMA_EVNT_INT_BLK4_sts_Pos                                           3U
+#define PLATFORM_REG_DMA_TASK_EVNT_STS_r_DMA_EVNT_INT_BLK4_sts_Msk                                           (0x1UL << PLATFORM_REG_DMA_TASK_EVNT_STS_r_DMA_EVNT_INT_BLK4_sts_Pos)
+
+#define PLATFORM_REG_DMA_TASK_EVNT_STS_reserved_1_Pos                                                        4U
+#define PLATFORM_REG_DMA_TASK_EVNT_STS_reserved_1_Msk                                                        (0xFFFUL << PLATFORM_REG_DMA_TASK_EVNT_STS_reserved_1_Pos)
+
+#define PLATFORM_REG_DMA_TASK_EVNT_STS_r_DMA_TASK_CHN_EN3_sts_Pos                                            16U
+#define PLATFORM_REG_DMA_TASK_EVNT_STS_r_DMA_TASK_CHN_EN3_sts_Msk                                            (0x1UL << PLATFORM_REG_DMA_TASK_EVNT_STS_r_DMA_TASK_CHN_EN3_sts_Pos)
+
+#define PLATFORM_REG_DMA_TASK_EVNT_STS_r_DMA_TASK_CHN_EN4_sts_Pos                                            17U
+#define PLATFORM_REG_DMA_TASK_EVNT_STS_r_DMA_TASK_CHN_EN4_sts_Msk                                            (0x1UL << PLATFORM_REG_DMA_TASK_EVNT_STS_r_DMA_TASK_CHN_EN4_sts_Pos)
+
+#define PLATFORM_REG_DMA_TASK_EVNT_STS_reserved_Pos                                                          18U
+#define PLATFORM_REG_DMA_TASK_EVNT_STS_reserved_Msk                                                          (0x3FFFUL << PLATFORM_REG_DMA_TASK_EVNT_STS_reserved_Pos)
+
+/* 0x036C   0x4000_636c
+    0       R/W1C   r_SDMK_EVNT_DONE_sts                                1'b0
+    15:1    R       reserved_1                                          15'h0000
+    16      R/W1C   r_SDMK_TASK_START_sts                               1'b0
+    31:17   R       reserved                                            15'h0000
+ */
+typedef union _PLATFORM_REG_SDMK_TASK_EVNT_STS_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t r_SDMK_EVNT_DONE_sts: 1;
+        uint32_t reserved_1: 15;
+        uint32_t r_SDMK_TASK_START_sts: 1;
+        uint32_t reserved: 15;
+    };
+} PLATFORM_REG_SDMK_TASK_EVNT_STS_TYPE;
+
+/*0x4000_636c PLATFORM_REG_SDMK_TASK_EVNT_STS*/
+#define PLATFORM_REG_SDMK_TASK_EVNT_STS_r_SDMK_EVNT_DONE_sts_Pos                                             0U
+#define PLATFORM_REG_SDMK_TASK_EVNT_STS_r_SDMK_EVNT_DONE_sts_Msk                                             (0x1UL << PLATFORM_REG_SDMK_TASK_EVNT_STS_r_SDMK_EVNT_DONE_sts_Pos)
+
+#define PLATFORM_REG_SDMK_TASK_EVNT_STS_reserved_1_Pos                                                       1U
+#define PLATFORM_REG_SDMK_TASK_EVNT_STS_reserved_1_Msk                                                       (0x7FFFUL << PLATFORM_REG_SDMK_TASK_EVNT_STS_reserved_1_Pos)
+
+#define PLATFORM_REG_SDMK_TASK_EVNT_STS_r_SDMK_TASK_START_sts_Pos                                            16U
+#define PLATFORM_REG_SDMK_TASK_EVNT_STS_r_SDMK_TASK_START_sts_Msk                                            (0x1UL << PLATFORM_REG_SDMK_TASK_EVNT_STS_r_SDMK_TASK_START_sts_Pos)
+
+#define PLATFORM_REG_SDMK_TASK_EVNT_STS_reserved_Pos                                                         17U
+#define PLATFORM_REG_SDMK_TASK_EVNT_STS_reserved_Msk                                                         (0x7FFFUL << PLATFORM_REG_SDMK_TASK_EVNT_STS_reserved_Pos)
+
+/* 0x0370   0x4000_6370
+    0       R/W1C   r_OSC10M_EVNT_CAL_DONE_sts                          1'b0
+    15:1    R       reserved_1                                          15'h0000
+    16      R/W1C   r_OSC10M_TASK_CAL_sts                               1'b0
+    31:17   R       reserved                                            15'h0000
+ */
+typedef union _PLATFORM_REG_OSC10M_CAL_TASK_EVNT_STS_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t r_OSC10M_EVNT_CAL_DONE_sts: 1;
+        uint32_t reserved_1: 15;
+        uint32_t r_OSC10M_TASK_CAL_sts: 1;
+        uint32_t reserved: 15;
+    };
+} PLATFORM_REG_OSC10M_CAL_TASK_EVNT_STS_TYPE;
+
+/*0x4000_6370 PLATFORM_REG_OSC10M_CAL_TASK_EVNT_STS*/
+#define PLATFORM_REG_OSC10M_CAL_TASK_EVNT_STS_r_OSC10M_EVNT_CAL_DONE_sts_Pos                                 0U
+#define PLATFORM_REG_OSC10M_CAL_TASK_EVNT_STS_r_OSC10M_EVNT_CAL_DONE_sts_Msk                                 (0x1UL << PLATFORM_REG_OSC10M_CAL_TASK_EVNT_STS_r_OSC10M_EVNT_CAL_DONE_sts_Pos)
+
+#define PLATFORM_REG_OSC10M_CAL_TASK_EVNT_STS_reserved_1_Pos                                                 1U
+#define PLATFORM_REG_OSC10M_CAL_TASK_EVNT_STS_reserved_1_Msk                                                 (0x7FFFUL << PLATFORM_REG_OSC10M_CAL_TASK_EVNT_STS_reserved_1_Pos)
+
+#define PLATFORM_REG_OSC10M_CAL_TASK_EVNT_STS_r_OSC10M_TASK_CAL_sts_Pos                                      16U
+#define PLATFORM_REG_OSC10M_CAL_TASK_EVNT_STS_r_OSC10M_TASK_CAL_sts_Msk                                      (0x1UL << PLATFORM_REG_OSC10M_CAL_TASK_EVNT_STS_r_OSC10M_TASK_CAL_sts_Pos)
+
+#define PLATFORM_REG_OSC10M_CAL_TASK_EVNT_STS_reserved_Pos                                                   17U
+#define PLATFORM_REG_OSC10M_CAL_TASK_EVNT_STS_reserved_Msk                                                   (0x7FFFUL << PLATFORM_REG_OSC10M_CAL_TASK_EVNT_STS_reserved_Pos)
+
+/* 0x0374   0x4000_6374
+    0       R/W1C   r_OSC80M_EVNT_CAL_DONE_sts                          1'b0
+    15:1    R       reserved_1                                          15'h0000
+    16      R/W1C   r_OSC80M_TASK_CAL_sts                               1'b0
+    31:17   R       reserved                                            15'h0000
+ */
+typedef union _PLATFORM_REG_OSC80M_CAL_TASK_EVNT_STS_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t r_OSC80M_EVNT_CAL_DONE_sts: 1;
+        uint32_t reserved_1: 15;
+        uint32_t r_OSC80M_TASK_CAL_sts: 1;
+        uint32_t reserved: 15;
+    };
+} PLATFORM_REG_OSC80M_CAL_TASK_EVNT_STS_TYPE;
+
+/*0x4000_6374 PLATFORM_REG_OSC80M_CAL_TASK_EVNT_STS*/
+#define PLATFORM_REG_OSC80M_CAL_TASK_EVNT_STS_r_OSC80M_EVNT_CAL_DONE_sts_Pos                                 0U
+#define PLATFORM_REG_OSC80M_CAL_TASK_EVNT_STS_r_OSC80M_EVNT_CAL_DONE_sts_Msk                                 (0x1UL << PLATFORM_REG_OSC80M_CAL_TASK_EVNT_STS_r_OSC80M_EVNT_CAL_DONE_sts_Pos)
+
+#define PLATFORM_REG_OSC80M_CAL_TASK_EVNT_STS_reserved_1_Pos                                                 1U
+#define PLATFORM_REG_OSC80M_CAL_TASK_EVNT_STS_reserved_1_Msk                                                 (0x7FFFUL << PLATFORM_REG_OSC80M_CAL_TASK_EVNT_STS_reserved_1_Pos)
+
+#define PLATFORM_REG_OSC80M_CAL_TASK_EVNT_STS_r_OSC80M_TASK_CAL_sts_Pos                                      16U
+#define PLATFORM_REG_OSC80M_CAL_TASK_EVNT_STS_r_OSC80M_TASK_CAL_sts_Msk                                      (0x1UL << PLATFORM_REG_OSC80M_CAL_TASK_EVNT_STS_r_OSC80M_TASK_CAL_sts_Pos)
+
+#define PLATFORM_REG_OSC80M_CAL_TASK_EVNT_STS_reserved_Pos                                                   17U
+#define PLATFORM_REG_OSC80M_CAL_TASK_EVNT_STS_reserved_Msk                                                   (0x7FFFUL << PLATFORM_REG_OSC80M_CAL_TASK_EVNT_STS_reserved_Pos)
+
+
+#define PLATFORM_REG_BASE 0x40006000
+
+#define PLATFORM_REG_READ(Offset)\
+    ((uint32_t)*((volatile uint32_t*)(PLATFORM_REG_BASE+(Offset))))
+
+#define PLATFORM_REG_WRITE(Offset, Value)\
+    ((*((volatile uint32_t*)(PLATFORM_REG_BASE + (Offset)))) = (Value))
+
+#define PLATFORM_REG_UPDATE(Offset, Mask, Value) \
+    do {\
+        uint32_t temp;\
+        temp = PLATFORM_REG_READ(Offset) & ~(Mask);\
+        PLATFORM_REG_WRITE(Offset, (temp | ((Value) & (Mask))));\
+    } while(0)
+
+#define PLATFORM_REG_READ_BITFIELD(Offset, Bitfield)                   \
+    (((Offset##_TYPE)PLATFORM_REG_READ(Offset)).Bitfield)
+
+#define PLATFORM_REG_WRITE_BITFIELD(Offset, Bitfield, Value)           \
+    do {                                                        \
+        Offset##_TYPE temp = {.d32 = PLATFORM_REG_READ(Offset)};       \
+        temp.Bitfield = Value;                                         \
+        PLATFORM_REG_WRITE(Offset, temp.d32);                          \
+    } while(0)
+
+#endif //#define PLATFORM_REG_H
diff --git a/bee/soc/inc/rtl87x2j/ppu_reg.h b/bee/soc/inc/rtl87x2j/ppu_reg.h
new file mode 100755
index 00000000..b6511889
--- /dev/null
+++ b/bee/soc/inc/rtl87x2j/ppu_reg.h
@@ -0,0 +1,1359 @@
+#ifndef PPU_REG_H
+#define PPU_REG_H
+#include <stdint.h>
+
+/* ================================================================================ */
+/* ================                PPU Register               ================ */
+/* ===========     Reference: Bee5_PPU_Power_Register_Table_20251023A.xlsx     =========== */
+/* ================================================================================ */
+#define PPU_PPU_PWPR_VPON_PPU   0x0000
+#define PPU_PPU_PMER_VPON_PPU   0x0004
+#define PPU_PPU_PWSR_VPON_PPU   0x0008
+#define PPU_Reserved_VPON_PPU   0x000C
+#define PPU_PPU_DISR_VPON_PPU   0x0010
+#define PPU_PPU_MISR_VPON_PPU   0x0014
+#define PPU_PPU_STSR_VPON_PPU   0x0018
+#define PPU_PPU_UNLK_VPON_PPU   0x001C
+#define PPU_PPU_PWCR_VPON_PPU   0x0020
+#define PPU_PPU_PTCR_VPON_PPU   0x0024
+#define PPU_PPU_IMR_VPON_PPU    0x0030
+#define PPU_PPU_AIMR_VPON_PPU   0x0034
+#define PPU_PPU_ISR_VPON_PPU    0x0038
+#define PPU_PPU_AISR_VPON_PPU   0x003C
+#define PPU_PPU_IESR_VPON_PPU   0x0040
+#define PPU_PPU_OPSR_VPON_PPU   0x0044
+#define PPU_PPU_FUNRR_VPON_PPU  0x0050
+#define PPU_PPU_FULRR_VPON_PPU  0x0054
+#define PPU_PPU_MEMRR_VPON_PPU  0x0058
+#define PPU_PPU_EDTR0_VPON_PPU  0x0160
+#define PPU_PPU_EDTR1_VPON_PPU  0x0164
+#define PPU_PPU_DCDR0_VPON_PPU  0x0170
+#define PPU_PPU_DCDR1_VPON_PPU  0x0174
+#define PPU_PPU_IDR0_VPON_PPU   0x0FB0
+#define PPU_PPU_IDR1_VPON_PPU   0x0FB4
+#define PPU_PPU_IIDR_VPON_PPU   0x0FC8
+#define PPU_PPU_AIDR_VPON_PPU   0x0FCC
+#define PPU_ID_REG_VPON_PPU_1   0x0FD0
+#define PPU_ID_REG_VPON_PPU_2   0x0FD4
+#define PPU_ID_REG_VPON_PPU_3   0x0FD8
+#define PPU_ID_REG_VPON_PPU_4   0x0FDC
+#define PPU_ID_REG_VPON_PPU_5   0x0FE0
+#define PPU_ID_REG_VPON_PPU_6   0x0FE4
+#define PPU_ID_REG_VPON_PPU_7   0x0FE8
+#define PPU_ID_REG_VPON_PPU_8   0x0FEC
+#define PPU_ID_REG_VPON_PPU_9   0x0FF0
+#define PPU_ID_REG_VPON_PPU_10  0x0FF4
+#define PPU_ID_REG_VPON_PPU_11  0x0FF8
+#define PPU_ID_REG_VPON_PPU_12  0x0FFC
+
+/* 0x0000   0x4000_2000
+    3:0     RW      PWR_POLICY                  DEF_PWR_POLICY
+    7:4     RO      RESERVED_4                  0x0
+    8       RW      PWR_DYN_EN                  DEF_PWR_DYN_EN
+    11:9    RO      RESERVED_3                  0x0
+    12      RW      LOCK_EN                     0x0
+    15:13   RO      RESERVED_2                  0x0
+    19:16   RW      OP_POLICY                   DEF_OP_POLICY
+    23:20   RO      RESERVED_1                  0x0
+    24      RW      OP_DYN_EN                   DEF_OP_DYN_EN
+    31:25   RO      RESERVED                    0x0
+ */
+typedef union _PPU_PPU_PWPR_VPON_PPU_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t PWR_POLICY: 4;
+        uint32_t RESERVED_4: 4;
+        uint32_t PWR_DYN_EN: 1;
+        uint32_t RESERVED_3: 3;
+        uint32_t LOCK_EN: 1;
+        uint32_t RESERVED_2: 3;
+        uint32_t OP_POLICY: 4;
+        uint32_t RESERVED_1: 4;
+        uint32_t OP_DYN_EN: 1;
+        uint32_t RESERVED: 7;
+    };
+} PPU_PPU_PWPR_VPON_PPU_TYPE;
+
+/*0x4000_2000 PPU_PPU_PWPR_VPON_PPU*/
+#define PPU_PPU_PWPR_VPON_PPU_PWR_POLICY_Pos                         0U
+#define PPU_PPU_PWPR_VPON_PPU_PWR_POLICY_Msk                         (0xFUL << PPU_PPU_PWPR_VPON_PPU_PWR_POLICY_Pos)
+
+#define PPU_PPU_PWPR_VPON_PPU_RESERVED_4_Pos                         4U
+#define PPU_PPU_PWPR_VPON_PPU_RESERVED_4_Msk                         (0xFUL << PPU_PPU_PWPR_VPON_PPU_RESERVED_4_Pos)
+
+#define PPU_PPU_PWPR_VPON_PPU_PWR_DYN_EN_Pos                         8U
+#define PPU_PPU_PWPR_VPON_PPU_PWR_DYN_EN_Msk                         (0x1UL << PPU_PPU_PWPR_VPON_PPU_PWR_DYN_EN_Pos)
+
+#define PPU_PPU_PWPR_VPON_PPU_RESERVED_3_Pos                         9U
+#define PPU_PPU_PWPR_VPON_PPU_RESERVED_3_Msk                         (0x7UL << PPU_PPU_PWPR_VPON_PPU_RESERVED_3_Pos)
+
+#define PPU_PPU_PWPR_VPON_PPU_LOCK_EN_Pos                            12U
+#define PPU_PPU_PWPR_VPON_PPU_LOCK_EN_Msk                            (0x1UL << PPU_PPU_PWPR_VPON_PPU_LOCK_EN_Pos)
+
+#define PPU_PPU_PWPR_VPON_PPU_RESERVED_2_Pos                         13U
+#define PPU_PPU_PWPR_VPON_PPU_RESERVED_2_Msk                         (0x7UL << PPU_PPU_PWPR_VPON_PPU_RESERVED_2_Pos)
+
+#define PPU_PPU_PWPR_VPON_PPU_OP_POLICY_Pos                          16U
+#define PPU_PPU_PWPR_VPON_PPU_OP_POLICY_Msk                          (0xFUL << PPU_PPU_PWPR_VPON_PPU_OP_POLICY_Pos)
+
+#define PPU_PPU_PWPR_VPON_PPU_RESERVED_1_Pos                         20U
+#define PPU_PPU_PWPR_VPON_PPU_RESERVED_1_Msk                         (0xFUL << PPU_PPU_PWPR_VPON_PPU_RESERVED_1_Pos)
+
+#define PPU_PPU_PWPR_VPON_PPU_OP_DYN_EN_Pos                          24U
+#define PPU_PPU_PWPR_VPON_PPU_OP_DYN_EN_Msk                          (0x1UL << PPU_PPU_PWPR_VPON_PPU_OP_DYN_EN_Pos)
+
+#define PPU_PPU_PWPR_VPON_PPU_RESERVED_Pos                           25U
+#define PPU_PPU_PWPR_VPON_PPU_RESERVED_Msk                           (0x7FUL << PPU_PPU_PWPR_VPON_PPU_RESERVED_Pos)
+
+/* 0x0004   0x4000_2004
+    0       RW      EMU_EN                      0x0
+    31:1    RO      RESERVED                    0x0
+ */
+typedef union _PPU_PPU_PMER_VPON_PPU_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t EMU_EN: 1;
+        uint32_t RESERVED: 31;
+    };
+} PPU_PPU_PMER_VPON_PPU_TYPE;
+
+/*0x4000_2004 PPU_PPU_PMER_VPON_PPU*/
+#define PPU_PPU_PMER_VPON_PPU_EMU_EN_Pos                             0U
+#define PPU_PPU_PMER_VPON_PPU_EMU_EN_Msk                             (0x1UL << PPU_PPU_PMER_VPON_PPU_EMU_EN_Pos)
+
+#define PPU_PPU_PMER_VPON_PPU_RESERVED_Pos                           1U
+#define PPU_PPU_PMER_VPON_PPU_RESERVED_Msk                           (0x7FFFFFFFUL << PPU_PPU_PMER_VPON_PPU_RESERVED_Pos)
+
+/* 0x0008   0x4000_2008
+    3:0     RO      PWR_STATUS                  PCSMMODESTAT[3:0]
+    7:4     RO      RESERVED_4                  0x0
+    8       RO      PWR_DYN_STATUS              DEF_PWR_DYN_EN
+    11:9    RO      RESERVED_3                  0x0
+    12      RO      LOCK_STATUS                 0x0
+    15:13   RO      RESERVED_2                  0x0
+    19:16   RO      OP_STATUS                   PCSMMODESTAT[7:4]
+    23:20   RO      RESERVED_1                  0x0
+    24      RO      OP_DYN_STATUS               DEF_OP_DYN_EN
+    31:25   RO      RESERVED                    0x0
+ */
+typedef union _PPU_PPU_PWSR_VPON_PPU_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t PWR_STATUS: 4;
+        uint32_t RESERVED_4: 4;
+        uint32_t PWR_DYN_STATUS: 1;
+        uint32_t RESERVED_3: 3;
+        uint32_t LOCK_STATUS: 1;
+        uint32_t RESERVED_2: 3;
+        uint32_t OP_STATUS: 4;
+        uint32_t RESERVED_1: 4;
+        uint32_t OP_DYN_STATUS: 1;
+        uint32_t RESERVED: 7;
+    };
+} PPU_PPU_PWSR_VPON_PPU_TYPE;
+
+/*0x4000_2008 PPU_PPU_PWSR_VPON_PPU*/
+#define PPU_PPU_PWSR_VPON_PPU_PWR_STATUS_Pos                         0U
+#define PPU_PPU_PWSR_VPON_PPU_PWR_STATUS_Msk                         (0xFUL << PPU_PPU_PWSR_VPON_PPU_PWR_STATUS_Pos)
+
+#define PPU_PPU_PWSR_VPON_PPU_RESERVED_4_Pos                         4U
+#define PPU_PPU_PWSR_VPON_PPU_RESERVED_4_Msk                         (0xFUL << PPU_PPU_PWSR_VPON_PPU_RESERVED_4_Pos)
+
+#define PPU_PPU_PWSR_VPON_PPU_PWR_DYN_STATUS_Pos                     8U
+#define PPU_PPU_PWSR_VPON_PPU_PWR_DYN_STATUS_Msk                     (0x1UL << PPU_PPU_PWSR_VPON_PPU_PWR_DYN_STATUS_Pos)
+
+#define PPU_PPU_PWSR_VPON_PPU_RESERVED_3_Pos                         9U
+#define PPU_PPU_PWSR_VPON_PPU_RESERVED_3_Msk                         (0x7UL << PPU_PPU_PWSR_VPON_PPU_RESERVED_3_Pos)
+
+#define PPU_PPU_PWSR_VPON_PPU_LOCK_STATUS_Pos                        12U
+#define PPU_PPU_PWSR_VPON_PPU_LOCK_STATUS_Msk                        (0x1UL << PPU_PPU_PWSR_VPON_PPU_LOCK_STATUS_Pos)
+
+#define PPU_PPU_PWSR_VPON_PPU_RESERVED_2_Pos                         13U
+#define PPU_PPU_PWSR_VPON_PPU_RESERVED_2_Msk                         (0x7UL << PPU_PPU_PWSR_VPON_PPU_RESERVED_2_Pos)
+
+#define PPU_PPU_PWSR_VPON_PPU_OP_STATUS_Pos                          16U
+#define PPU_PPU_PWSR_VPON_PPU_OP_STATUS_Msk                          (0xFUL << PPU_PPU_PWSR_VPON_PPU_OP_STATUS_Pos)
+
+#define PPU_PPU_PWSR_VPON_PPU_RESERVED_1_Pos                         20U
+#define PPU_PPU_PWSR_VPON_PPU_RESERVED_1_Msk                         (0xFUL << PPU_PPU_PWSR_VPON_PPU_RESERVED_1_Pos)
+
+#define PPU_PPU_PWSR_VPON_PPU_OP_DYN_STATUS_Pos                      24U
+#define PPU_PPU_PWSR_VPON_PPU_OP_DYN_STATUS_Msk                      (0x1UL << PPU_PPU_PWSR_VPON_PPU_OP_DYN_STATUS_Pos)
+
+#define PPU_PPU_PWSR_VPON_PPU_RESERVED_Pos                           25U
+#define PPU_PPU_PWSR_VPON_PPU_RESERVED_Msk                           (0x7FUL << PPU_PPU_PWSR_VPON_PPU_RESERVED_Pos)
+
+/* 0x000C   0x4000_200c
+    31:0    RO      Reserved                    0x0
+ */
+typedef union _PPU_Reserved_VPON_PPU_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t Reserved;
+    };
+} PPU_Reserved_VPON_PPU_TYPE;
+
+/*0x4000_200c PPU_Reserved_VPON_PPU*/
+#define PPU_Reserved_VPON_PPU_Reserved_Pos                           0U
+#define PPU_Reserved_VPON_PPU_Reserved_Msk                           (0xFFFFFFFFUL << PPU_Reserved_VPON_PPU_Reserved_Pos)
+
+/* 0x0010   0x4000_2010
+    10:0    RO      PWR_DEVACTIVE_STATUS        0x0
+    23:11   RO      RESERVED                    0x0
+    31:24   RO      OP_DEVACTIVE_STATUS         0x0
+ */
+typedef union _PPU_PPU_DISR_VPON_PPU_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t PWR_DEVACTIVE_STATUS: 11;
+        uint32_t RESERVED: 13;
+        uint32_t OP_DEVACTIVE_STATUS: 8;
+    };
+} PPU_PPU_DISR_VPON_PPU_TYPE;
+
+/*0x4000_2010 PPU_PPU_DISR_VPON_PPU*/
+#define PPU_PPU_DISR_VPON_PPU_PWR_DEVACTIVE_STATUS_Pos               0U
+#define PPU_PPU_DISR_VPON_PPU_PWR_DEVACTIVE_STATUS_Msk               (0x7FFUL << PPU_PPU_DISR_VPON_PPU_PWR_DEVACTIVE_STATUS_Pos)
+
+#define PPU_PPU_DISR_VPON_PPU_RESERVED_Pos                           11U
+#define PPU_PPU_DISR_VPON_PPU_RESERVED_Msk                           (0x1FFFUL << PPU_PPU_DISR_VPON_PPU_RESERVED_Pos)
+
+#define PPU_PPU_DISR_VPON_PPU_OP_DEVACTIVE_STATUS_Pos                24U
+#define PPU_PPU_DISR_VPON_PPU_OP_DEVACTIVE_STATUS_Msk                (0xFFUL << PPU_PPU_DISR_VPON_PPU_OP_DEVACTIVE_STATUS_Pos)
+
+/* 0x0014   0x4000_2014
+    0       RO      PCSMPACCEPT_STATUS          0x0
+    7:1     RO      RESERVED_1                  0x0
+    15:8    RO      DEVACCEPT_STATUS            0x0
+    23:16   RO      DEVDENY_STATUS              0x0
+    31:24   RO      RESERVED                    0x0
+ */
+typedef union _PPU_PPU_MISR_VPON_PPU_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t PCSMPACCEPT_STATUS: 1;
+        uint32_t RESERVED_1: 7;
+        uint32_t DEVACCEPT_STATUS: 8;
+        uint32_t DEVDENY_STATUS: 8;
+        uint32_t RESERVED: 8;
+    };
+} PPU_PPU_MISR_VPON_PPU_TYPE;
+
+/*0x4000_2014 PPU_PPU_MISR_VPON_PPU*/
+#define PPU_PPU_MISR_VPON_PPU_PCSMPACCEPT_STATUS_Pos                 0U
+#define PPU_PPU_MISR_VPON_PPU_PCSMPACCEPT_STATUS_Msk                 (0x1UL << PPU_PPU_MISR_VPON_PPU_PCSMPACCEPT_STATUS_Pos)
+
+#define PPU_PPU_MISR_VPON_PPU_RESERVED_1_Pos                         1U
+#define PPU_PPU_MISR_VPON_PPU_RESERVED_1_Msk                         (0x7FUL << PPU_PPU_MISR_VPON_PPU_RESERVED_1_Pos)
+
+#define PPU_PPU_MISR_VPON_PPU_DEVACCEPT_STATUS_Pos                   8U
+#define PPU_PPU_MISR_VPON_PPU_DEVACCEPT_STATUS_Msk                   (0xFFUL << PPU_PPU_MISR_VPON_PPU_DEVACCEPT_STATUS_Pos)
+
+#define PPU_PPU_MISR_VPON_PPU_DEVDENY_STATUS_Pos                     16U
+#define PPU_PPU_MISR_VPON_PPU_DEVDENY_STATUS_Msk                     (0xFFUL << PPU_PPU_MISR_VPON_PPU_DEVDENY_STATUS_Pos)
+
+#define PPU_PPU_MISR_VPON_PPU_RESERVED_Pos                           24U
+#define PPU_PPU_MISR_VPON_PPU_RESERVED_Msk                           (0xFFUL << PPU_PPU_MISR_VPON_PPU_RESERVED_Pos)
+
+/* 0x0018   0x4000_2018
+    7:0     RO      STORED_DEVDENY              0x0
+    31:8    RO      RESERVED                    0x0
+ */
+typedef union _PPU_PPU_STSR_VPON_PPU_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t STORED_DEVDENY: 8;
+        uint32_t RESERVED: 24;
+    };
+} PPU_PPU_STSR_VPON_PPU_TYPE;
+
+/*0x4000_2018 PPU_PPU_STSR_VPON_PPU*/
+#define PPU_PPU_STSR_VPON_PPU_STORED_DEVDENY_Pos                     0U
+#define PPU_PPU_STSR_VPON_PPU_STORED_DEVDENY_Msk                     (0xFFUL << PPU_PPU_STSR_VPON_PPU_STORED_DEVDENY_Pos)
+
+#define PPU_PPU_STSR_VPON_PPU_RESERVED_Pos                           8U
+#define PPU_PPU_STSR_VPON_PPU_RESERVED_Msk                           (0xFFFFFFUL << PPU_PPU_STSR_VPON_PPU_RESERVED_Pos)
+
+/* 0x001C   0x4000_201c
+    0       WO      UNLOCK                      0x0
+    31:1    RO      RESERVED                    0x0
+ */
+typedef union _PPU_PPU_UNLK_VPON_PPU_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t UNLOCK: 1;
+        uint32_t RESERVED: 31;
+    };
+} PPU_PPU_UNLK_VPON_PPU_TYPE;
+
+/*0x4000_201c PPU_PPU_UNLK_VPON_PPU*/
+#define PPU_PPU_UNLK_VPON_PPU_UNLOCK_Pos                             0U
+#define PPU_PPU_UNLK_VPON_PPU_UNLOCK_Msk                             (0x1UL << PPU_PPU_UNLK_VPON_PPU_UNLOCK_Pos)
+
+#define PPU_PPU_UNLK_VPON_PPU_RESERVED_Pos                           1U
+#define PPU_PPU_UNLK_VPON_PPU_RESERVED_Msk                           (0x7FFFFFFFUL << PPU_PPU_UNLK_VPON_PPU_RESERVED_Pos)
+
+/* 0x0020   0x4000_2020
+    7:0     RW      DEVREQEN                    SeeTable
+    18:8    RW      PWR_DEVACTIVEEN             SeeTable
+    23:19   RO      RESERVED                    0x0
+    31:24   RW      OP_DEVACTIVEEN              SeeTable
+ */
+typedef union _PPU_PPU_PWCR_VPON_PPU_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t DEVREQEN: 8;
+        uint32_t PWR_DEVACTIVEEN: 11;
+        uint32_t RESERVED: 5;
+        uint32_t OP_DEVACTIVEEN: 8;
+    };
+} PPU_PPU_PWCR_VPON_PPU_TYPE;
+
+/*0x4000_2020 PPU_PPU_PWCR_VPON_PPU*/
+#define PPU_PPU_PWCR_VPON_PPU_DEVREQEN_Pos                           0U
+#define PPU_PPU_PWCR_VPON_PPU_DEVREQEN_Msk                           (0xFFUL << PPU_PPU_PWCR_VPON_PPU_DEVREQEN_Pos)
+
+#define PPU_PPU_PWCR_VPON_PPU_PWR_DEVACTIVEEN_Pos                    8U
+#define PPU_PPU_PWCR_VPON_PPU_PWR_DEVACTIVEEN_Msk                    (0x7FFUL << PPU_PPU_PWCR_VPON_PPU_PWR_DEVACTIVEEN_Pos)
+
+#define PPU_PPU_PWCR_VPON_PPU_RESERVED_Pos                           19U
+#define PPU_PPU_PWCR_VPON_PPU_RESERVED_Msk                           (0x1FUL << PPU_PPU_PWCR_VPON_PPU_RESERVED_Pos)
+
+#define PPU_PPU_PWCR_VPON_PPU_OP_DEVACTIVEEN_Pos                     24U
+#define PPU_PPU_PWCR_VPON_PPU_OP_DEVACTIVEEN_Msk                     (0xFFUL << PPU_PPU_PWCR_VPON_PPU_OP_DEVACTIVEEN_Pos)
+
+/* 0x0024   0x4000_2024
+    0       RW      WARM_RST_DEVREQEN           WARM_RST_DEVREQEN_CFG
+    1       RW      DBG_RECOV_PORST_EN          DBG_RECOV_PORST_CFG
+    31:2    RO      RESERVED                    0x0
+ */
+typedef union _PPU_PPU_PTCR_VPON_PPU_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t WARM_RST_DEVREQEN: 1;
+        uint32_t DBG_RECOV_PORST_EN: 1;
+        uint32_t RESERVED: 30;
+    };
+} PPU_PPU_PTCR_VPON_PPU_TYPE;
+
+/*0x4000_2024 PPU_PPU_PTCR_VPON_PPU*/
+#define PPU_PPU_PTCR_VPON_PPU_WARM_RST_DEVREQEN_Pos                  0U
+#define PPU_PPU_PTCR_VPON_PPU_WARM_RST_DEVREQEN_Msk                  (0x1UL << PPU_PPU_PTCR_VPON_PPU_WARM_RST_DEVREQEN_Pos)
+
+#define PPU_PPU_PTCR_VPON_PPU_DBG_RECOV_PORST_EN_Pos                 1U
+#define PPU_PPU_PTCR_VPON_PPU_DBG_RECOV_PORST_EN_Msk                 (0x1UL << PPU_PPU_PTCR_VPON_PPU_DBG_RECOV_PORST_EN_Pos)
+
+#define PPU_PPU_PTCR_VPON_PPU_RESERVED_Pos                           2U
+#define PPU_PPU_PTCR_VPON_PPU_RESERVED_Msk                           (0x3FFFFFFFUL << PPU_PPU_PTCR_VPON_PPU_RESERVED_Pos)
+
+/* 0x0030   0x4000_2030
+    0       RW      STA_POLICY_TRN_IRQ_MASK     0x0
+    1       RW      STA_ACCEPT_IRQ_MASK         0x1
+    2       RW      STA_DENY_IRQ_MASK           0x0
+    3       RW      EMU_ACCEPT_IRQ_MASK         0x1
+    4       RW      EMU_DENY_IRQ_MASK           0x1
+    5       RW      LOCKED_IRQ_MASK             0x1
+    31:6    RO      RESERVED                    0x0
+ */
+typedef union _PPU_PPU_IMR_VPON_PPU_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t STA_POLICY_TRN_IRQ_MASK: 1;
+        uint32_t STA_ACCEPT_IRQ_MASK: 1;
+        uint32_t STA_DENY_IRQ_MASK: 1;
+        uint32_t EMU_ACCEPT_IRQ_MASK: 1;
+        uint32_t EMU_DENY_IRQ_MASK: 1;
+        uint32_t LOCKED_IRQ_MASK: 1;
+        uint32_t RESERVED: 26;
+    };
+} PPU_PPU_IMR_VPON_PPU_TYPE;
+
+/*0x4000_2030 PPU_PPU_IMR_VPON_PPU*/
+#define PPU_PPU_IMR_VPON_PPU_STA_POLICY_TRN_IRQ_MASK_Pos             0U
+#define PPU_PPU_IMR_VPON_PPU_STA_POLICY_TRN_IRQ_MASK_Msk             (0x1UL << PPU_PPU_IMR_VPON_PPU_STA_POLICY_TRN_IRQ_MASK_Pos)
+
+#define PPU_PPU_IMR_VPON_PPU_STA_ACCEPT_IRQ_MASK_Pos                 1U
+#define PPU_PPU_IMR_VPON_PPU_STA_ACCEPT_IRQ_MASK_Msk                 (0x1UL << PPU_PPU_IMR_VPON_PPU_STA_ACCEPT_IRQ_MASK_Pos)
+
+#define PPU_PPU_IMR_VPON_PPU_STA_DENY_IRQ_MASK_Pos                   2U
+#define PPU_PPU_IMR_VPON_PPU_STA_DENY_IRQ_MASK_Msk                   (0x1UL << PPU_PPU_IMR_VPON_PPU_STA_DENY_IRQ_MASK_Pos)
+
+#define PPU_PPU_IMR_VPON_PPU_EMU_ACCEPT_IRQ_MASK_Pos                 3U
+#define PPU_PPU_IMR_VPON_PPU_EMU_ACCEPT_IRQ_MASK_Msk                 (0x1UL << PPU_PPU_IMR_VPON_PPU_EMU_ACCEPT_IRQ_MASK_Pos)
+
+#define PPU_PPU_IMR_VPON_PPU_EMU_DENY_IRQ_MASK_Pos                   4U
+#define PPU_PPU_IMR_VPON_PPU_EMU_DENY_IRQ_MASK_Msk                   (0x1UL << PPU_PPU_IMR_VPON_PPU_EMU_DENY_IRQ_MASK_Pos)
+
+#define PPU_PPU_IMR_VPON_PPU_LOCKED_IRQ_MASK_Pos                     5U
+#define PPU_PPU_IMR_VPON_PPU_LOCKED_IRQ_MASK_Msk                     (0x1UL << PPU_PPU_IMR_VPON_PPU_LOCKED_IRQ_MASK_Pos)
+
+#define PPU_PPU_IMR_VPON_PPU_RESERVED_Pos                            6U
+#define PPU_PPU_IMR_VPON_PPU_RESERVED_Msk                            (0x3FFFFFFUL << PPU_PPU_IMR_VPON_PPU_RESERVED_Pos)
+
+/* 0x0034   0x4000_2034
+    0       RW      UNSPT_POLICY_IRQ_MASK       0x0
+    1       RW      DYN_ACCEPT_IRQ_MASK         0x1
+    2       RW      DYN_DENY_IRQ_MASK           0x1
+    3       RW      STA_POLICY_PWR_IRQ_MASK     0x1
+    4       RW      STA_POLICY_OP_IRQ_MASK      0x1
+    31:5    RO      RESERVED                    0x0
+ */
+typedef union _PPU_PPU_AIMR_VPON_PPU_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t UNSPT_POLICY_IRQ_MASK: 1;
+        uint32_t DYN_ACCEPT_IRQ_MASK: 1;
+        uint32_t DYN_DENY_IRQ_MASK: 1;
+        uint32_t STA_POLICY_PWR_IRQ_MASK: 1;
+        uint32_t STA_POLICY_OP_IRQ_MASK: 1;
+        uint32_t RESERVED: 27;
+    };
+} PPU_PPU_AIMR_VPON_PPU_TYPE;
+
+/*0x4000_2034 PPU_PPU_AIMR_VPON_PPU*/
+#define PPU_PPU_AIMR_VPON_PPU_UNSPT_POLICY_IRQ_MASK_Pos              0U
+#define PPU_PPU_AIMR_VPON_PPU_UNSPT_POLICY_IRQ_MASK_Msk              (0x1UL << PPU_PPU_AIMR_VPON_PPU_UNSPT_POLICY_IRQ_MASK_Pos)
+
+#define PPU_PPU_AIMR_VPON_PPU_DYN_ACCEPT_IRQ_MASK_Pos                1U
+#define PPU_PPU_AIMR_VPON_PPU_DYN_ACCEPT_IRQ_MASK_Msk                (0x1UL << PPU_PPU_AIMR_VPON_PPU_DYN_ACCEPT_IRQ_MASK_Pos)
+
+#define PPU_PPU_AIMR_VPON_PPU_DYN_DENY_IRQ_MASK_Pos                  2U
+#define PPU_PPU_AIMR_VPON_PPU_DYN_DENY_IRQ_MASK_Msk                  (0x1UL << PPU_PPU_AIMR_VPON_PPU_DYN_DENY_IRQ_MASK_Pos)
+
+#define PPU_PPU_AIMR_VPON_PPU_STA_POLICY_PWR_IRQ_MASK_Pos            3U
+#define PPU_PPU_AIMR_VPON_PPU_STA_POLICY_PWR_IRQ_MASK_Msk            (0x1UL << PPU_PPU_AIMR_VPON_PPU_STA_POLICY_PWR_IRQ_MASK_Pos)
+
+#define PPU_PPU_AIMR_VPON_PPU_STA_POLICY_OP_IRQ_MASK_Pos             4U
+#define PPU_PPU_AIMR_VPON_PPU_STA_POLICY_OP_IRQ_MASK_Msk             (0x1UL << PPU_PPU_AIMR_VPON_PPU_STA_POLICY_OP_IRQ_MASK_Pos)
+
+#define PPU_PPU_AIMR_VPON_PPU_RESERVED_Pos                           5U
+#define PPU_PPU_AIMR_VPON_PPU_RESERVED_Msk                           (0x7FFFFFFUL << PPU_PPU_AIMR_VPON_PPU_RESERVED_Pos)
+
+/* 0x0038   0x4000_2038
+    0       RW      STA_POLICY_TRN_IRQ          0x0
+    1       RW      STA_ACCEPT_IRQ              0x0
+    2       RW      STA_DENY_IRQ                0x0
+    3       RW      EMU_ACCEPT_IRQ              0x0
+    4       RW      EMU_DENY_IRQ                0x0
+    5       RW      LOCKED_IRQ                  0x0
+    6       RW      RESERVED_1                  0x0
+    7       RO      OTHER_IRQ                   0x0
+    18:8    RW      PWR_ACTIVE_EDGE_IRQ         0x00
+    23:19   RO      RESERVED                    0x0
+    31:24   RW      OP_ACTIVE_EDGE_IRQ          0x0
+ */
+typedef union _PPU_PPU_ISR_VPON_PPU_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t STA_POLICY_TRN_IRQ: 1;
+        uint32_t STA_ACCEPT_IRQ: 1;
+        uint32_t STA_DENY_IRQ: 1;
+        uint32_t EMU_ACCEPT_IRQ: 1;
+        uint32_t EMU_DENY_IRQ: 1;
+        uint32_t LOCKED_IRQ: 1;
+        uint32_t RESERVED_1: 1;
+        uint32_t OTHER_IRQ: 1;
+        uint32_t PWR_ACTIVE_EDGE_IRQ: 11;
+        uint32_t RESERVED: 5;
+        uint32_t OP_ACTIVE_EDGE_IRQ: 8;
+    };
+} PPU_PPU_ISR_VPON_PPU_TYPE;
+
+/*0x4000_2038 PPU_PPU_ISR_VPON_PPU*/
+#define PPU_PPU_ISR_VPON_PPU_STA_POLICY_TRN_IRQ_Pos                  0U
+#define PPU_PPU_ISR_VPON_PPU_STA_POLICY_TRN_IRQ_Msk                  (0x1UL << PPU_PPU_ISR_VPON_PPU_STA_POLICY_TRN_IRQ_Pos)
+
+#define PPU_PPU_ISR_VPON_PPU_STA_ACCEPT_IRQ_Pos                      1U
+#define PPU_PPU_ISR_VPON_PPU_STA_ACCEPT_IRQ_Msk                      (0x1UL << PPU_PPU_ISR_VPON_PPU_STA_ACCEPT_IRQ_Pos)
+
+#define PPU_PPU_ISR_VPON_PPU_STA_DENY_IRQ_Pos                        2U
+#define PPU_PPU_ISR_VPON_PPU_STA_DENY_IRQ_Msk                        (0x1UL << PPU_PPU_ISR_VPON_PPU_STA_DENY_IRQ_Pos)
+
+#define PPU_PPU_ISR_VPON_PPU_EMU_ACCEPT_IRQ_Pos                      3U
+#define PPU_PPU_ISR_VPON_PPU_EMU_ACCEPT_IRQ_Msk                      (0x1UL << PPU_PPU_ISR_VPON_PPU_EMU_ACCEPT_IRQ_Pos)
+
+#define PPU_PPU_ISR_VPON_PPU_EMU_DENY_IRQ_Pos                        4U
+#define PPU_PPU_ISR_VPON_PPU_EMU_DENY_IRQ_Msk                        (0x1UL << PPU_PPU_ISR_VPON_PPU_EMU_DENY_IRQ_Pos)
+
+#define PPU_PPU_ISR_VPON_PPU_LOCKED_IRQ_Pos                          5U
+#define PPU_PPU_ISR_VPON_PPU_LOCKED_IRQ_Msk                          (0x1UL << PPU_PPU_ISR_VPON_PPU_LOCKED_IRQ_Pos)
+
+#define PPU_PPU_ISR_VPON_PPU_RESERVED_1_Pos                          6U
+#define PPU_PPU_ISR_VPON_PPU_RESERVED_1_Msk                          (0x1UL << PPU_PPU_ISR_VPON_PPU_RESERVED_1_Pos)
+
+#define PPU_PPU_ISR_VPON_PPU_OTHER_IRQ_Pos                           7U
+#define PPU_PPU_ISR_VPON_PPU_OTHER_IRQ_Msk                           (0x1UL << PPU_PPU_ISR_VPON_PPU_OTHER_IRQ_Pos)
+
+#define PPU_PPU_ISR_VPON_PPU_PWR_ACTIVE_EDGE_IRQ_Pos                 8U
+#define PPU_PPU_ISR_VPON_PPU_PWR_ACTIVE_EDGE_IRQ_Msk                 (0x7FFUL << PPU_PPU_ISR_VPON_PPU_PWR_ACTIVE_EDGE_IRQ_Pos)
+
+#define PPU_PPU_ISR_VPON_PPU_RESERVED_Pos                            19U
+#define PPU_PPU_ISR_VPON_PPU_RESERVED_Msk                            (0x1FUL << PPU_PPU_ISR_VPON_PPU_RESERVED_Pos)
+
+#define PPU_PPU_ISR_VPON_PPU_OP_ACTIVE_EDGE_IRQ_Pos                  24U
+#define PPU_PPU_ISR_VPON_PPU_OP_ACTIVE_EDGE_IRQ_Msk                  (0xFFUL << PPU_PPU_ISR_VPON_PPU_OP_ACTIVE_EDGE_IRQ_Pos)
+
+/* 0x003C   0x4000_203c
+    0       RW      UNSPT_POLICY_IRQ            0x0
+    1       RW      DYN_ACCEPT_IRQ              0x0
+    2       RW      DYN_DENY_IRQ                0x0
+    3       RW      STA_POLICY_PWR_IRQ          0x0
+    4       RW      STA_POLICY_OP_IRQ           0x0
+    31:5    RO      RESERVED                    0x0
+ */
+typedef union _PPU_PPU_AISR_VPON_PPU_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t UNSPT_POLICY_IRQ: 1;
+        uint32_t DYN_ACCEPT_IRQ: 1;
+        uint32_t DYN_DENY_IRQ: 1;
+        uint32_t STA_POLICY_PWR_IRQ: 1;
+        uint32_t STA_POLICY_OP_IRQ: 1;
+        uint32_t RESERVED: 27;
+    };
+} PPU_PPU_AISR_VPON_PPU_TYPE;
+
+/*0x4000_203c PPU_PPU_AISR_VPON_PPU*/
+#define PPU_PPU_AISR_VPON_PPU_UNSPT_POLICY_IRQ_Pos                   0U
+#define PPU_PPU_AISR_VPON_PPU_UNSPT_POLICY_IRQ_Msk                   (0x1UL << PPU_PPU_AISR_VPON_PPU_UNSPT_POLICY_IRQ_Pos)
+
+#define PPU_PPU_AISR_VPON_PPU_DYN_ACCEPT_IRQ_Pos                     1U
+#define PPU_PPU_AISR_VPON_PPU_DYN_ACCEPT_IRQ_Msk                     (0x1UL << PPU_PPU_AISR_VPON_PPU_DYN_ACCEPT_IRQ_Pos)
+
+#define PPU_PPU_AISR_VPON_PPU_DYN_DENY_IRQ_Pos                       2U
+#define PPU_PPU_AISR_VPON_PPU_DYN_DENY_IRQ_Msk                       (0x1UL << PPU_PPU_AISR_VPON_PPU_DYN_DENY_IRQ_Pos)
+
+#define PPU_PPU_AISR_VPON_PPU_STA_POLICY_PWR_IRQ_Pos                 3U
+#define PPU_PPU_AISR_VPON_PPU_STA_POLICY_PWR_IRQ_Msk                 (0x1UL << PPU_PPU_AISR_VPON_PPU_STA_POLICY_PWR_IRQ_Pos)
+
+#define PPU_PPU_AISR_VPON_PPU_STA_POLICY_OP_IRQ_Pos                  4U
+#define PPU_PPU_AISR_VPON_PPU_STA_POLICY_OP_IRQ_Msk                  (0x1UL << PPU_PPU_AISR_VPON_PPU_STA_POLICY_OP_IRQ_Pos)
+
+#define PPU_PPU_AISR_VPON_PPU_RESERVED_Pos                           5U
+#define PPU_PPU_AISR_VPON_PPU_RESERVED_Msk                           (0x7FFFFFFUL << PPU_PPU_AISR_VPON_PPU_RESERVED_Pos)
+
+/* 0x0040   0x4000_2040
+    1:0     RW      DEVACTIVE00_EDGE            0x0
+    3:2     RW      DEVACTIVE01_EDGE            0x0
+    5:4     RW      DEVACTIVE02_EDGE            0x0
+    7:6     RW      DEVACTIVE03_EDGE            0x0
+    9:8     RW      DEVACTIVE04_EDGE            0x0
+    11:10   RW      DEVACTIVE05_EDGE            0x0
+    13:12   RW      DEVACTIVE06_EDGE            0x0
+    15:14   RW      DEVACTIVE07_EDGE            0x0
+    17:16   RW      DEVACTIVE08_EDGE            0x0
+    19:18   RW      DEVACTIVE09_EDGE            0x0
+    21:20   RW      DEVACTIVE10_EDGE            0x0
+    31:22   RO      RESERVED                    0x0000
+ */
+typedef union _PPU_PPU_IESR_VPON_PPU_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t DEVACTIVE00_EDGE: 2;
+        uint32_t DEVACTIVE01_EDGE: 2;
+        uint32_t DEVACTIVE02_EDGE: 2;
+        uint32_t DEVACTIVE03_EDGE: 2;
+        uint32_t DEVACTIVE04_EDGE: 2;
+        uint32_t DEVACTIVE05_EDGE: 2;
+        uint32_t DEVACTIVE06_EDGE: 2;
+        uint32_t DEVACTIVE07_EDGE: 2;
+        uint32_t DEVACTIVE08_EDGE: 2;
+        uint32_t DEVACTIVE09_EDGE: 2;
+        uint32_t DEVACTIVE10_EDGE: 2;
+        uint32_t RESERVED: 10;
+    };
+} PPU_PPU_IESR_VPON_PPU_TYPE;
+
+/*0x4000_2040 PPU_PPU_IESR_VPON_PPU*/
+#define PPU_PPU_IESR_VPON_PPU_DEVACTIVE00_EDGE_Pos                   0U
+#define PPU_PPU_IESR_VPON_PPU_DEVACTIVE00_EDGE_Msk                   (0x3UL << PPU_PPU_IESR_VPON_PPU_DEVACTIVE00_EDGE_Pos)
+
+#define PPU_PPU_IESR_VPON_PPU_DEVACTIVE01_EDGE_Pos                   2U
+#define PPU_PPU_IESR_VPON_PPU_DEVACTIVE01_EDGE_Msk                   (0x3UL << PPU_PPU_IESR_VPON_PPU_DEVACTIVE01_EDGE_Pos)
+
+#define PPU_PPU_IESR_VPON_PPU_DEVACTIVE02_EDGE_Pos                   4U
+#define PPU_PPU_IESR_VPON_PPU_DEVACTIVE02_EDGE_Msk                   (0x3UL << PPU_PPU_IESR_VPON_PPU_DEVACTIVE02_EDGE_Pos)
+
+#define PPU_PPU_IESR_VPON_PPU_DEVACTIVE03_EDGE_Pos                   6U
+#define PPU_PPU_IESR_VPON_PPU_DEVACTIVE03_EDGE_Msk                   (0x3UL << PPU_PPU_IESR_VPON_PPU_DEVACTIVE03_EDGE_Pos)
+
+#define PPU_PPU_IESR_VPON_PPU_DEVACTIVE04_EDGE_Pos                   8U
+#define PPU_PPU_IESR_VPON_PPU_DEVACTIVE04_EDGE_Msk                   (0x3UL << PPU_PPU_IESR_VPON_PPU_DEVACTIVE04_EDGE_Pos)
+
+#define PPU_PPU_IESR_VPON_PPU_DEVACTIVE05_EDGE_Pos                   10U
+#define PPU_PPU_IESR_VPON_PPU_DEVACTIVE05_EDGE_Msk                   (0x3UL << PPU_PPU_IESR_VPON_PPU_DEVACTIVE05_EDGE_Pos)
+
+#define PPU_PPU_IESR_VPON_PPU_DEVACTIVE06_EDGE_Pos                   12U
+#define PPU_PPU_IESR_VPON_PPU_DEVACTIVE06_EDGE_Msk                   (0x3UL << PPU_PPU_IESR_VPON_PPU_DEVACTIVE06_EDGE_Pos)
+
+#define PPU_PPU_IESR_VPON_PPU_DEVACTIVE07_EDGE_Pos                   14U
+#define PPU_PPU_IESR_VPON_PPU_DEVACTIVE07_EDGE_Msk                   (0x3UL << PPU_PPU_IESR_VPON_PPU_DEVACTIVE07_EDGE_Pos)
+
+#define PPU_PPU_IESR_VPON_PPU_DEVACTIVE08_EDGE_Pos                   16U
+#define PPU_PPU_IESR_VPON_PPU_DEVACTIVE08_EDGE_Msk                   (0x3UL << PPU_PPU_IESR_VPON_PPU_DEVACTIVE08_EDGE_Pos)
+
+#define PPU_PPU_IESR_VPON_PPU_DEVACTIVE09_EDGE_Pos                   18U
+#define PPU_PPU_IESR_VPON_PPU_DEVACTIVE09_EDGE_Msk                   (0x3UL << PPU_PPU_IESR_VPON_PPU_DEVACTIVE09_EDGE_Pos)
+
+#define PPU_PPU_IESR_VPON_PPU_DEVACTIVE10_EDGE_Pos                   20U
+#define PPU_PPU_IESR_VPON_PPU_DEVACTIVE10_EDGE_Msk                   (0x3UL << PPU_PPU_IESR_VPON_PPU_DEVACTIVE10_EDGE_Pos)
+
+#define PPU_PPU_IESR_VPON_PPU_RESERVED_Pos                           22U
+#define PPU_PPU_IESR_VPON_PPU_RESERVED_Msk                           (0x3FFUL << PPU_PPU_IESR_VPON_PPU_RESERVED_Pos)
+
+/* 0x0044   0x4000_2044
+    1:0     RW      DEVACTIVE16_EDGE            0x0
+    3:2     RW      DEVACTIVE17_EDGE            0x0
+    5:4     RW      DEVACTIVE18_EDGE            0x0
+    7:6     RW      DEVACTIVE19_EDGE            0x0
+    9:8     RW      DEVACTIVE20_EDGE            0x0
+    11:10   RW      DEVACTIVE21_EDGE            0x0
+    13:12   RW      DEVACTIVE22_EDGE            0x0
+    15:14   RW      DEVACTIVE23_EDGE            0x0
+    31:16   RO      RESERVED                    0x0000
+ */
+typedef union _PPU_PPU_OPSR_VPON_PPU_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t DEVACTIVE16_EDGE: 2;
+        uint32_t DEVACTIVE17_EDGE: 2;
+        uint32_t DEVACTIVE18_EDGE: 2;
+        uint32_t DEVACTIVE19_EDGE: 2;
+        uint32_t DEVACTIVE20_EDGE: 2;
+        uint32_t DEVACTIVE21_EDGE: 2;
+        uint32_t DEVACTIVE22_EDGE: 2;
+        uint32_t DEVACTIVE23_EDGE: 2;
+        uint32_t RESERVED: 16;
+    };
+} PPU_PPU_OPSR_VPON_PPU_TYPE;
+
+/*0x4000_2044 PPU_PPU_OPSR_VPON_PPU*/
+#define PPU_PPU_OPSR_VPON_PPU_DEVACTIVE16_EDGE_Pos                   0U
+#define PPU_PPU_OPSR_VPON_PPU_DEVACTIVE16_EDGE_Msk                   (0x3UL << PPU_PPU_OPSR_VPON_PPU_DEVACTIVE16_EDGE_Pos)
+
+#define PPU_PPU_OPSR_VPON_PPU_DEVACTIVE17_EDGE_Pos                   2U
+#define PPU_PPU_OPSR_VPON_PPU_DEVACTIVE17_EDGE_Msk                   (0x3UL << PPU_PPU_OPSR_VPON_PPU_DEVACTIVE17_EDGE_Pos)
+
+#define PPU_PPU_OPSR_VPON_PPU_DEVACTIVE18_EDGE_Pos                   4U
+#define PPU_PPU_OPSR_VPON_PPU_DEVACTIVE18_EDGE_Msk                   (0x3UL << PPU_PPU_OPSR_VPON_PPU_DEVACTIVE18_EDGE_Pos)
+
+#define PPU_PPU_OPSR_VPON_PPU_DEVACTIVE19_EDGE_Pos                   6U
+#define PPU_PPU_OPSR_VPON_PPU_DEVACTIVE19_EDGE_Msk                   (0x3UL << PPU_PPU_OPSR_VPON_PPU_DEVACTIVE19_EDGE_Pos)
+
+#define PPU_PPU_OPSR_VPON_PPU_DEVACTIVE20_EDGE_Pos                   8U
+#define PPU_PPU_OPSR_VPON_PPU_DEVACTIVE20_EDGE_Msk                   (0x3UL << PPU_PPU_OPSR_VPON_PPU_DEVACTIVE20_EDGE_Pos)
+
+#define PPU_PPU_OPSR_VPON_PPU_DEVACTIVE21_EDGE_Pos                   10U
+#define PPU_PPU_OPSR_VPON_PPU_DEVACTIVE21_EDGE_Msk                   (0x3UL << PPU_PPU_OPSR_VPON_PPU_DEVACTIVE21_EDGE_Pos)
+
+#define PPU_PPU_OPSR_VPON_PPU_DEVACTIVE22_EDGE_Pos                   12U
+#define PPU_PPU_OPSR_VPON_PPU_DEVACTIVE22_EDGE_Msk                   (0x3UL << PPU_PPU_OPSR_VPON_PPU_DEVACTIVE22_EDGE_Pos)
+
+#define PPU_PPU_OPSR_VPON_PPU_DEVACTIVE23_EDGE_Pos                   14U
+#define PPU_PPU_OPSR_VPON_PPU_DEVACTIVE23_EDGE_Msk                   (0x3UL << PPU_PPU_OPSR_VPON_PPU_DEVACTIVE23_EDGE_Pos)
+
+#define PPU_PPU_OPSR_VPON_PPU_RESERVED_Pos                           16U
+#define PPU_PPU_OPSR_VPON_PPU_RESERVED_Msk                           (0xFFFFUL << PPU_PPU_OPSR_VPON_PPU_RESERVED_Pos)
+
+/* 0x0050   0x4000_2050
+    7:0     RW      FUNC_RET_RAM_CFG            0x0
+    31:8    RO      RESERVED                    0x0
+ */
+typedef union _PPU_PPU_FUNRR_VPON_PPU_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t FUNC_RET_RAM_CFG: 8;
+        uint32_t RESERVED: 24;
+    };
+} PPU_PPU_FUNRR_VPON_PPU_TYPE;
+
+/*0x4000_2050 PPU_PPU_FUNRR_VPON_PPU*/
+#define PPU_PPU_FUNRR_VPON_PPU_FUNC_RET_RAM_CFG_Pos                  0U
+#define PPU_PPU_FUNRR_VPON_PPU_FUNC_RET_RAM_CFG_Msk                  (0xFFUL << PPU_PPU_FUNRR_VPON_PPU_FUNC_RET_RAM_CFG_Pos)
+
+#define PPU_PPU_FUNRR_VPON_PPU_RESERVED_Pos                          8U
+#define PPU_PPU_FUNRR_VPON_PPU_RESERVED_Msk                          (0xFFFFFFUL << PPU_PPU_FUNRR_VPON_PPU_RESERVED_Pos)
+
+/* 0x0054   0x4000_2054
+    7:0     RW      FULL_RET_RAM_CFG            0x0
+    31:8    RO      RESERVED                    0x0
+ */
+typedef union _PPU_PPU_FULRR_VPON_PPU_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t FULL_RET_RAM_CFG: 8;
+        uint32_t RESERVED: 24;
+    };
+} PPU_PPU_FULRR_VPON_PPU_TYPE;
+
+/*0x4000_2054 PPU_PPU_FULRR_VPON_PPU*/
+#define PPU_PPU_FULRR_VPON_PPU_FULL_RET_RAM_CFG_Pos                  0U
+#define PPU_PPU_FULRR_VPON_PPU_FULL_RET_RAM_CFG_Msk                  (0xFFUL << PPU_PPU_FULRR_VPON_PPU_FULL_RET_RAM_CFG_Pos)
+
+#define PPU_PPU_FULRR_VPON_PPU_RESERVED_Pos                          8U
+#define PPU_PPU_FULRR_VPON_PPU_RESERVED_Msk                          (0xFFFFFFUL << PPU_PPU_FULRR_VPON_PPU_RESERVED_Pos)
+
+/* 0x0058   0x4000_2058
+    7:0     RW      MEM_RET_RAM_CFG             0x0
+    31:8    RO      RESERVED                    0x0
+ */
+typedef union _PPU_PPU_MEMRR_VPON_PPU_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t MEM_RET_RAM_CFG: 8;
+        uint32_t RESERVED: 24;
+    };
+} PPU_PPU_MEMRR_VPON_PPU_TYPE;
+
+/*0x4000_2058 PPU_PPU_MEMRR_VPON_PPU*/
+#define PPU_PPU_MEMRR_VPON_PPU_MEM_RET_RAM_CFG_Pos                   0U
+#define PPU_PPU_MEMRR_VPON_PPU_MEM_RET_RAM_CFG_Msk                   (0xFFUL << PPU_PPU_MEMRR_VPON_PPU_MEM_RET_RAM_CFG_Pos)
+
+#define PPU_PPU_MEMRR_VPON_PPU_RESERVED_Pos                          8U
+#define PPU_PPU_MEMRR_VPON_PPU_RESERVED_Msk                          (0xFFFFFFUL << PPU_PPU_MEMRR_VPON_PPU_RESERVED_Pos)
+
+/* 0x0160   0x4000_2160
+    7:0     RW      OFF_DEL                     0x00
+    15:8    RW      MEM_RET_DEL                 0x00
+    23:16   RW      LOGIC_RET_DEL               0x00
+    31:24   RW      FULL_RET_DEL                0x00
+ */
+typedef union _PPU_PPU_EDTR0_VPON_PPU_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t OFF_DEL: 8;
+        uint32_t MEM_RET_DEL: 8;
+        uint32_t LOGIC_RET_DEL: 8;
+        uint32_t FULL_RET_DEL: 8;
+    };
+} PPU_PPU_EDTR0_VPON_PPU_TYPE;
+
+/*0x4000_2160 PPU_PPU_EDTR0_VPON_PPU*/
+#define PPU_PPU_EDTR0_VPON_PPU_OFF_DEL_Pos                           0U
+#define PPU_PPU_EDTR0_VPON_PPU_OFF_DEL_Msk                           (0xFFUL << PPU_PPU_EDTR0_VPON_PPU_OFF_DEL_Pos)
+
+#define PPU_PPU_EDTR0_VPON_PPU_MEM_RET_DEL_Pos                       8U
+#define PPU_PPU_EDTR0_VPON_PPU_MEM_RET_DEL_Msk                       (0xFFUL << PPU_PPU_EDTR0_VPON_PPU_MEM_RET_DEL_Pos)
+
+#define PPU_PPU_EDTR0_VPON_PPU_LOGIC_RET_DEL_Pos                     16U
+#define PPU_PPU_EDTR0_VPON_PPU_LOGIC_RET_DEL_Msk                     (0xFFUL << PPU_PPU_EDTR0_VPON_PPU_LOGIC_RET_DEL_Pos)
+
+#define PPU_PPU_EDTR0_VPON_PPU_FULL_RET_DEL_Pos                      24U
+#define PPU_PPU_EDTR0_VPON_PPU_FULL_RET_DEL_Msk                      (0xFFUL << PPU_PPU_EDTR0_VPON_PPU_FULL_RET_DEL_Pos)
+
+/* 0x0164   0x4000_2164
+    7:0     RW      MEM_OFF_DEL                 0x00
+    15:8    RW      FUNC_RET_DEL                0x00
+    31:16   RO      RESERVED                    0x00
+ */
+typedef union _PPU_PPU_EDTR1_VPON_PPU_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t MEM_OFF_DEL: 8;
+        uint32_t FUNC_RET_DEL: 8;
+        uint32_t RESERVED: 16;
+    };
+} PPU_PPU_EDTR1_VPON_PPU_TYPE;
+
+/*0x4000_2164 PPU_PPU_EDTR1_VPON_PPU*/
+#define PPU_PPU_EDTR1_VPON_PPU_MEM_OFF_DEL_Pos                       0U
+#define PPU_PPU_EDTR1_VPON_PPU_MEM_OFF_DEL_Msk                       (0xFFUL << PPU_PPU_EDTR1_VPON_PPU_MEM_OFF_DEL_Pos)
+
+#define PPU_PPU_EDTR1_VPON_PPU_FUNC_RET_DEL_Pos                      8U
+#define PPU_PPU_EDTR1_VPON_PPU_FUNC_RET_DEL_Msk                      (0xFFUL << PPU_PPU_EDTR1_VPON_PPU_FUNC_RET_DEL_Pos)
+
+#define PPU_PPU_EDTR1_VPON_PPU_RESERVED_Pos                          16U
+#define PPU_PPU_EDTR1_VPON_PPU_RESERVED_Msk                          (0xFFFFUL << PPU_PPU_EDTR1_VPON_PPU_RESERVED_Pos)
+
+/* 0x0170   0x4000_2170
+    7:0     RW      CLKEN_RST_DLY               CLKEN_RST_DLY_CFG
+    15:8    RW      ISO_CLKEN_DLY               ISO_CLKEN_DLY_CFG
+    23:16   RW      RST_HWSTAT_DLY              RST_HWSTAT_DLY_CFG
+    31:24   RO      RESERVED                    0x000
+ */
+typedef union _PPU_PPU_DCDR0_VPON_PPU_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t CLKEN_RST_DLY: 8;
+        uint32_t ISO_CLKEN_DLY: 8;
+        uint32_t RST_HWSTAT_DLY: 8;
+        uint32_t RESERVED: 8;
+    };
+} PPU_PPU_DCDR0_VPON_PPU_TYPE;
+
+/*0x4000_2170 PPU_PPU_DCDR0_VPON_PPU*/
+#define PPU_PPU_DCDR0_VPON_PPU_CLKEN_RST_DLY_Pos                     0U
+#define PPU_PPU_DCDR0_VPON_PPU_CLKEN_RST_DLY_Msk                     (0xFFUL << PPU_PPU_DCDR0_VPON_PPU_CLKEN_RST_DLY_Pos)
+
+#define PPU_PPU_DCDR0_VPON_PPU_ISO_CLKEN_DLY_Pos                     8U
+#define PPU_PPU_DCDR0_VPON_PPU_ISO_CLKEN_DLY_Msk                     (0xFFUL << PPU_PPU_DCDR0_VPON_PPU_ISO_CLKEN_DLY_Pos)
+
+#define PPU_PPU_DCDR0_VPON_PPU_RST_HWSTAT_DLY_Pos                    16U
+#define PPU_PPU_DCDR0_VPON_PPU_RST_HWSTAT_DLY_Msk                    (0xFFUL << PPU_PPU_DCDR0_VPON_PPU_RST_HWSTAT_DLY_Pos)
+
+#define PPU_PPU_DCDR0_VPON_PPU_RESERVED_Pos                          24U
+#define PPU_PPU_DCDR0_VPON_PPU_RESERVED_Msk                          (0xFFUL << PPU_PPU_DCDR0_VPON_PPU_RESERVED_Pos)
+
+/* 0x0174   0x4000_2174
+    7:0     RW      ISO_RST_DLY                 ISO_RST_DLY_CFG
+    15:8    RW      CLKEN_ISO_DLY               CLKEN_ISO_DLY_CFG
+    31:16   RO      RESERVED                    0x0000
+ */
+typedef union _PPU_PPU_DCDR1_VPON_PPU_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t ISO_RST_DLY: 8;
+        uint32_t CLKEN_ISO_DLY: 8;
+        uint32_t RESERVED: 16;
+    };
+} PPU_PPU_DCDR1_VPON_PPU_TYPE;
+
+/*0x4000_2174 PPU_PPU_DCDR1_VPON_PPU*/
+#define PPU_PPU_DCDR1_VPON_PPU_ISO_RST_DLY_Pos                       0U
+#define PPU_PPU_DCDR1_VPON_PPU_ISO_RST_DLY_Msk                       (0xFFUL << PPU_PPU_DCDR1_VPON_PPU_ISO_RST_DLY_Pos)
+
+#define PPU_PPU_DCDR1_VPON_PPU_CLKEN_ISO_DLY_Pos                     8U
+#define PPU_PPU_DCDR1_VPON_PPU_CLKEN_ISO_DLY_Msk                     (0xFFUL << PPU_PPU_DCDR1_VPON_PPU_CLKEN_ISO_DLY_Pos)
+
+#define PPU_PPU_DCDR1_VPON_PPU_RESERVED_Pos                          16U
+#define PPU_PPU_DCDR1_VPON_PPU_RESERVED_Msk                          (0xFFFFUL << PPU_PPU_DCDR1_VPON_PPU_RESERVED_Pos)
+
+/* 0x0FB0   0x4000_2fb0
+    3:0     RO      DEVCHAN                     DEVCHAN_CFG
+    7:4     RO      NUM_OPMODE                  NUM_OPMODE_CFG
+    8       RO      STA_OFF_SPT                 0x1
+    9       RO      STA_OFF_EMU_SPT             STA_OFF_EMU_SPT_CFG
+    10      RO      STA_MEM_RET_SPT             STA_MEM_RET_SPT_CFG
+    11      RO      STA_MEM_RET_EMU_SPT         STA_MEM_RET_EMU_SPT_CFG
+    12      RO      STA_LGC_RET_SPT             STA_LGC_RET_SPT_CFG
+    13      RO      STA_MEM_OFF_SPT             STA_MEM_OFF_SPT_CFG
+    14      RO      STA_FULL_RET_SPT            STA_FULL_RET_SPT_CFG
+    15      RO      STA_FUNC_RET_SPT            STA_FUNC_RET_SPT_CFG
+    16      RO      STA_ON_SPT                  0x1
+    17      RO      STA_WRM_RST_SPT             0x1
+    18      RO      STA_DBG_RECOV_SPT           STA_DBG_RECOV_SPT_CFG
+    19      RO      RESERVED_1                  0X0
+    20      RO      DYN_OFF_SPT                 DYN_OFF_SPT_CFG
+    21      RO      DYN_OFF_EMU_SPT             DYN_OFF_EMU_SPT_CFG
+    22      RO      DYN_MEM_RET_SPT             DYN_MEM_RET_SPT_CFG
+    23      RO      DYN_MEM_RET_EMU_SPT         DYN_MEM_RET_EMU_SPT_CFG
+    24      RO      DYN_LGC_RET_SPT             DYN_LGC_RET_SPT_CFG
+    25      RO      DYN_MEM_OFF_SPT             DYN_MEM_OFF_SPT_CFG
+    26      RO      DYN_FULL_RET_SPT            DYN_FULL_RET_SPT_CFG
+    27      RO      DYN_FUNC_RET_SPT            DYN_FUNC_RET_SPT_CFG
+    28      RO      DYN_ON_SPT                  DYN_ON_SPT_CFG
+    29      RO      DYN_WRM_RST_SPT             DYN_WRM_RST_SPT_CFG
+    31:30   RO      RESERVED                    0x0
+ */
+typedef union _PPU_PPU_IDR0_VPON_PPU_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t DEVCHAN: 4;
+        uint32_t NUM_OPMODE: 4;
+        uint32_t STA_OFF_SPT: 1;
+        uint32_t STA_OFF_EMU_SPT: 1;
+        uint32_t STA_MEM_RET_SPT: 1;
+        uint32_t STA_MEM_RET_EMU_SPT: 1;
+        uint32_t STA_LGC_RET_SPT: 1;
+        uint32_t STA_MEM_OFF_SPT: 1;
+        uint32_t STA_FULL_RET_SPT: 1;
+        uint32_t STA_FUNC_RET_SPT: 1;
+        uint32_t STA_ON_SPT: 1;
+        uint32_t STA_WRM_RST_SPT: 1;
+        uint32_t STA_DBG_RECOV_SPT: 1;
+        uint32_t RESERVED_1: 1;
+        uint32_t DYN_OFF_SPT: 1;
+        uint32_t DYN_OFF_EMU_SPT: 1;
+        uint32_t DYN_MEM_RET_SPT: 1;
+        uint32_t DYN_MEM_RET_EMU_SPT: 1;
+        uint32_t DYN_LGC_RET_SPT: 1;
+        uint32_t DYN_MEM_OFF_SPT: 1;
+        uint32_t DYN_FULL_RET_SPT: 1;
+        uint32_t DYN_FUNC_RET_SPT: 1;
+        uint32_t DYN_ON_SPT: 1;
+        uint32_t DYN_WRM_RST_SPT: 1;
+        uint32_t RESERVED: 2;
+    };
+} PPU_PPU_IDR0_VPON_PPU_TYPE;
+
+/*0x4000_2fb0 PPU_PPU_IDR0_VPON_PPU*/
+#define PPU_PPU_IDR0_VPON_PPU_DEVCHAN_Pos                            0U
+#define PPU_PPU_IDR0_VPON_PPU_DEVCHAN_Msk                            (0xFUL << PPU_PPU_IDR0_VPON_PPU_DEVCHAN_Pos)
+
+#define PPU_PPU_IDR0_VPON_PPU_NUM_OPMODE_Pos                         4U
+#define PPU_PPU_IDR0_VPON_PPU_NUM_OPMODE_Msk                         (0xFUL << PPU_PPU_IDR0_VPON_PPU_NUM_OPMODE_Pos)
+
+#define PPU_PPU_IDR0_VPON_PPU_STA_OFF_SPT_Pos                        8U
+#define PPU_PPU_IDR0_VPON_PPU_STA_OFF_SPT_Msk                        (0x1UL << PPU_PPU_IDR0_VPON_PPU_STA_OFF_SPT_Pos)
+
+#define PPU_PPU_IDR0_VPON_PPU_STA_OFF_EMU_SPT_Pos                    9U
+#define PPU_PPU_IDR0_VPON_PPU_STA_OFF_EMU_SPT_Msk                    (0x1UL << PPU_PPU_IDR0_VPON_PPU_STA_OFF_EMU_SPT_Pos)
+
+#define PPU_PPU_IDR0_VPON_PPU_STA_MEM_RET_SPT_Pos                    10U
+#define PPU_PPU_IDR0_VPON_PPU_STA_MEM_RET_SPT_Msk                    (0x1UL << PPU_PPU_IDR0_VPON_PPU_STA_MEM_RET_SPT_Pos)
+
+#define PPU_PPU_IDR0_VPON_PPU_STA_MEM_RET_EMU_SPT_Pos                11U
+#define PPU_PPU_IDR0_VPON_PPU_STA_MEM_RET_EMU_SPT_Msk                (0x1UL << PPU_PPU_IDR0_VPON_PPU_STA_MEM_RET_EMU_SPT_Pos)
+
+#define PPU_PPU_IDR0_VPON_PPU_STA_LGC_RET_SPT_Pos                    12U
+#define PPU_PPU_IDR0_VPON_PPU_STA_LGC_RET_SPT_Msk                    (0x1UL << PPU_PPU_IDR0_VPON_PPU_STA_LGC_RET_SPT_Pos)
+
+#define PPU_PPU_IDR0_VPON_PPU_STA_MEM_OFF_SPT_Pos                    13U
+#define PPU_PPU_IDR0_VPON_PPU_STA_MEM_OFF_SPT_Msk                    (0x1UL << PPU_PPU_IDR0_VPON_PPU_STA_MEM_OFF_SPT_Pos)
+
+#define PPU_PPU_IDR0_VPON_PPU_STA_FULL_RET_SPT_Pos                   14U
+#define PPU_PPU_IDR0_VPON_PPU_STA_FULL_RET_SPT_Msk                   (0x1UL << PPU_PPU_IDR0_VPON_PPU_STA_FULL_RET_SPT_Pos)
+
+#define PPU_PPU_IDR0_VPON_PPU_STA_FUNC_RET_SPT_Pos                   15U
+#define PPU_PPU_IDR0_VPON_PPU_STA_FUNC_RET_SPT_Msk                   (0x1UL << PPU_PPU_IDR0_VPON_PPU_STA_FUNC_RET_SPT_Pos)
+
+#define PPU_PPU_IDR0_VPON_PPU_STA_ON_SPT_Pos                         16U
+#define PPU_PPU_IDR0_VPON_PPU_STA_ON_SPT_Msk                         (0x1UL << PPU_PPU_IDR0_VPON_PPU_STA_ON_SPT_Pos)
+
+#define PPU_PPU_IDR0_VPON_PPU_STA_WRM_RST_SPT_Pos                    17U
+#define PPU_PPU_IDR0_VPON_PPU_STA_WRM_RST_SPT_Msk                    (0x1UL << PPU_PPU_IDR0_VPON_PPU_STA_WRM_RST_SPT_Pos)
+
+#define PPU_PPU_IDR0_VPON_PPU_STA_DBG_RECOV_SPT_Pos                  18U
+#define PPU_PPU_IDR0_VPON_PPU_STA_DBG_RECOV_SPT_Msk                  (0x1UL << PPU_PPU_IDR0_VPON_PPU_STA_DBG_RECOV_SPT_Pos)
+
+#define PPU_PPU_IDR0_VPON_PPU_RESERVED_1_Pos                         19U
+#define PPU_PPU_IDR0_VPON_PPU_RESERVED_1_Msk                         (0x1UL << PPU_PPU_IDR0_VPON_PPU_RESERVED_1_Pos)
+
+#define PPU_PPU_IDR0_VPON_PPU_DYN_OFF_SPT_Pos                        20U
+#define PPU_PPU_IDR0_VPON_PPU_DYN_OFF_SPT_Msk                        (0x1UL << PPU_PPU_IDR0_VPON_PPU_DYN_OFF_SPT_Pos)
+
+#define PPU_PPU_IDR0_VPON_PPU_DYN_OFF_EMU_SPT_Pos                    21U
+#define PPU_PPU_IDR0_VPON_PPU_DYN_OFF_EMU_SPT_Msk                    (0x1UL << PPU_PPU_IDR0_VPON_PPU_DYN_OFF_EMU_SPT_Pos)
+
+#define PPU_PPU_IDR0_VPON_PPU_DYN_MEM_RET_SPT_Pos                    22U
+#define PPU_PPU_IDR0_VPON_PPU_DYN_MEM_RET_SPT_Msk                    (0x1UL << PPU_PPU_IDR0_VPON_PPU_DYN_MEM_RET_SPT_Pos)
+
+#define PPU_PPU_IDR0_VPON_PPU_DYN_MEM_RET_EMU_SPT_Pos                23U
+#define PPU_PPU_IDR0_VPON_PPU_DYN_MEM_RET_EMU_SPT_Msk                (0x1UL << PPU_PPU_IDR0_VPON_PPU_DYN_MEM_RET_EMU_SPT_Pos)
+
+#define PPU_PPU_IDR0_VPON_PPU_DYN_LGC_RET_SPT_Pos                    24U
+#define PPU_PPU_IDR0_VPON_PPU_DYN_LGC_RET_SPT_Msk                    (0x1UL << PPU_PPU_IDR0_VPON_PPU_DYN_LGC_RET_SPT_Pos)
+
+#define PPU_PPU_IDR0_VPON_PPU_DYN_MEM_OFF_SPT_Pos                    25U
+#define PPU_PPU_IDR0_VPON_PPU_DYN_MEM_OFF_SPT_Msk                    (0x1UL << PPU_PPU_IDR0_VPON_PPU_DYN_MEM_OFF_SPT_Pos)
+
+#define PPU_PPU_IDR0_VPON_PPU_DYN_FULL_RET_SPT_Pos                   26U
+#define PPU_PPU_IDR0_VPON_PPU_DYN_FULL_RET_SPT_Msk                   (0x1UL << PPU_PPU_IDR0_VPON_PPU_DYN_FULL_RET_SPT_Pos)
+
+#define PPU_PPU_IDR0_VPON_PPU_DYN_FUNC_RET_SPT_Pos                   27U
+#define PPU_PPU_IDR0_VPON_PPU_DYN_FUNC_RET_SPT_Msk                   (0x1UL << PPU_PPU_IDR0_VPON_PPU_DYN_FUNC_RET_SPT_Pos)
+
+#define PPU_PPU_IDR0_VPON_PPU_DYN_ON_SPT_Pos                         28U
+#define PPU_PPU_IDR0_VPON_PPU_DYN_ON_SPT_Msk                         (0x1UL << PPU_PPU_IDR0_VPON_PPU_DYN_ON_SPT_Pos)
+
+#define PPU_PPU_IDR0_VPON_PPU_DYN_WRM_RST_SPT_Pos                    29U
+#define PPU_PPU_IDR0_VPON_PPU_DYN_WRM_RST_SPT_Msk                    (0x1UL << PPU_PPU_IDR0_VPON_PPU_DYN_WRM_RST_SPT_Pos)
+
+#define PPU_PPU_IDR0_VPON_PPU_RESERVED_Pos                           30U
+#define PPU_PPU_IDR0_VPON_PPU_RESERVED_Msk                           (0x3UL << PPU_PPU_IDR0_VPON_PPU_RESERVED_Pos)
+
+/* 0x0FB4   0x4000_2fb4
+    0       RO      PWR_MODE_ENTRY_DEL_SPT      PWR_MODE_ENTRY_DEL_CFG
+    1       RO      SW_DEV_DEL_SPT              SW_DEV_DEL_CFG
+    2       RO      LOCK_SPT                    LOCK_CFG
+    3       RO      RESERVED_3                  0x0
+    4       RO      MEM_RET_RAM_REG             MEM_RET_RAM_REG_CFG
+    5       RO      FULL_RET_RAM_REG            FULL_RET_RAM_REG_CFG
+    6       RO      FUNC_RET_RAM_REG            FUNC_RET_RAM_REG_CFG
+    7       RO      RESERVED_2                  0x0
+    8       RO      STA_POLICY_PWR_IRQ_SPT      STA_POLICY_PWR_IRQ_CFG
+    9       RO      STA_POLICY_OP_IRQ_SPT       STA_POLICY_OP_IRQ_CFG
+    10      RO      OP_ACTIVE                   OP_ACTIVE_CFG
+    11      RO      RESERVED_1                  0x0
+    12      RO      OFF_MEM_RET_TRANS           OFF_MEM_RET_TRANS_CFG
+    31:13   RO      RESERVED                    0x0
+ */
+typedef union _PPU_PPU_IDR1_VPON_PPU_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t PWR_MODE_ENTRY_DEL_SPT: 1;
+        uint32_t SW_DEV_DEL_SPT: 1;
+        uint32_t LOCK_SPT: 1;
+        uint32_t RESERVED_3: 1;
+        uint32_t MEM_RET_RAM_REG: 1;
+        uint32_t FULL_RET_RAM_REG: 1;
+        uint32_t FUNC_RET_RAM_REG: 1;
+        uint32_t RESERVED_2: 1;
+        uint32_t STA_POLICY_PWR_IRQ_SPT: 1;
+        uint32_t STA_POLICY_OP_IRQ_SPT: 1;
+        uint32_t OP_ACTIVE: 1;
+        uint32_t RESERVED_1: 1;
+        uint32_t OFF_MEM_RET_TRANS: 1;
+        uint32_t RESERVED: 19;
+    };
+} PPU_PPU_IDR1_VPON_PPU_TYPE;
+
+/*0x4000_2fb4 PPU_PPU_IDR1_VPON_PPU*/
+#define PPU_PPU_IDR1_VPON_PPU_PWR_MODE_ENTRY_DEL_SPT_Pos             0U
+#define PPU_PPU_IDR1_VPON_PPU_PWR_MODE_ENTRY_DEL_SPT_Msk             (0x1UL << PPU_PPU_IDR1_VPON_PPU_PWR_MODE_ENTRY_DEL_SPT_Pos)
+
+#define PPU_PPU_IDR1_VPON_PPU_SW_DEV_DEL_SPT_Pos                     1U
+#define PPU_PPU_IDR1_VPON_PPU_SW_DEV_DEL_SPT_Msk                     (0x1UL << PPU_PPU_IDR1_VPON_PPU_SW_DEV_DEL_SPT_Pos)
+
+#define PPU_PPU_IDR1_VPON_PPU_LOCK_SPT_Pos                           2U
+#define PPU_PPU_IDR1_VPON_PPU_LOCK_SPT_Msk                           (0x1UL << PPU_PPU_IDR1_VPON_PPU_LOCK_SPT_Pos)
+
+#define PPU_PPU_IDR1_VPON_PPU_RESERVED_3_Pos                         3U
+#define PPU_PPU_IDR1_VPON_PPU_RESERVED_3_Msk                         (0x1UL << PPU_PPU_IDR1_VPON_PPU_RESERVED_3_Pos)
+
+#define PPU_PPU_IDR1_VPON_PPU_MEM_RET_RAM_REG_Pos                    4U
+#define PPU_PPU_IDR1_VPON_PPU_MEM_RET_RAM_REG_Msk                    (0x1UL << PPU_PPU_IDR1_VPON_PPU_MEM_RET_RAM_REG_Pos)
+
+#define PPU_PPU_IDR1_VPON_PPU_FULL_RET_RAM_REG_Pos                   5U
+#define PPU_PPU_IDR1_VPON_PPU_FULL_RET_RAM_REG_Msk                   (0x1UL << PPU_PPU_IDR1_VPON_PPU_FULL_RET_RAM_REG_Pos)
+
+#define PPU_PPU_IDR1_VPON_PPU_FUNC_RET_RAM_REG_Pos                   6U
+#define PPU_PPU_IDR1_VPON_PPU_FUNC_RET_RAM_REG_Msk                   (0x1UL << PPU_PPU_IDR1_VPON_PPU_FUNC_RET_RAM_REG_Pos)
+
+#define PPU_PPU_IDR1_VPON_PPU_RESERVED_2_Pos                         7U
+#define PPU_PPU_IDR1_VPON_PPU_RESERVED_2_Msk                         (0x1UL << PPU_PPU_IDR1_VPON_PPU_RESERVED_2_Pos)
+
+#define PPU_PPU_IDR1_VPON_PPU_STA_POLICY_PWR_IRQ_SPT_Pos             8U
+#define PPU_PPU_IDR1_VPON_PPU_STA_POLICY_PWR_IRQ_SPT_Msk             (0x1UL << PPU_PPU_IDR1_VPON_PPU_STA_POLICY_PWR_IRQ_SPT_Pos)
+
+#define PPU_PPU_IDR1_VPON_PPU_STA_POLICY_OP_IRQ_SPT_Pos              9U
+#define PPU_PPU_IDR1_VPON_PPU_STA_POLICY_OP_IRQ_SPT_Msk              (0x1UL << PPU_PPU_IDR1_VPON_PPU_STA_POLICY_OP_IRQ_SPT_Pos)
+
+#define PPU_PPU_IDR1_VPON_PPU_OP_ACTIVE_Pos                          10U
+#define PPU_PPU_IDR1_VPON_PPU_OP_ACTIVE_Msk                          (0x1UL << PPU_PPU_IDR1_VPON_PPU_OP_ACTIVE_Pos)
+
+#define PPU_PPU_IDR1_VPON_PPU_RESERVED_1_Pos                         11U
+#define PPU_PPU_IDR1_VPON_PPU_RESERVED_1_Msk                         (0x1UL << PPU_PPU_IDR1_VPON_PPU_RESERVED_1_Pos)
+
+#define PPU_PPU_IDR1_VPON_PPU_OFF_MEM_RET_TRANS_Pos                  12U
+#define PPU_PPU_IDR1_VPON_PPU_OFF_MEM_RET_TRANS_Msk                  (0x1UL << PPU_PPU_IDR1_VPON_PPU_OFF_MEM_RET_TRANS_Pos)
+
+#define PPU_PPU_IDR1_VPON_PPU_RESERVED_Pos                           13U
+#define PPU_PPU_IDR1_VPON_PPU_RESERVED_Msk                           (0x7FFFFUL << PPU_PPU_IDR1_VPON_PPU_RESERVED_Pos)
+
+/* 0x0FC8   0x4000_2fc8
+    11:0    RO      IMPLEMENTER                 -.
+    15:12   RO      REVISIONIMPLEMENTATION      -
+    19:16   RO      VARIANTIMPLEMENTATION       -
+    31:20   RO      PRODUCT_IDIMPLEMENTATION    -
+ */
+typedef union _PPU_PPU_IIDR_VPON_PPU_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t IMPLEMENTER: 12;
+        uint32_t REVISIONIMPLEMENTATION: 4;
+        uint32_t VARIANTIMPLEMENTATION: 4;
+        uint32_t PRODUCT_IDIMPLEMENTATION: 12;
+    };
+} PPU_PPU_IIDR_VPON_PPU_TYPE;
+
+/*0x4000_2fc8 PPU_PPU_IIDR_VPON_PPU*/
+#define PPU_PPU_IIDR_VPON_PPU_IMPLEMENTER_Pos                        0U
+#define PPU_PPU_IIDR_VPON_PPU_IMPLEMENTER_Msk                        (0xFFFUL << PPU_PPU_IIDR_VPON_PPU_IMPLEMENTER_Pos)
+
+#define PPU_PPU_IIDR_VPON_PPU_REVISIONIMPLEMENTATION_Pos             12U
+#define PPU_PPU_IIDR_VPON_PPU_REVISIONIMPLEMENTATION_Msk             (0xFUL << PPU_PPU_IIDR_VPON_PPU_REVISIONIMPLEMENTATION_Pos)
+
+#define PPU_PPU_IIDR_VPON_PPU_VARIANTIMPLEMENTATION_Pos              16U
+#define PPU_PPU_IIDR_VPON_PPU_VARIANTIMPLEMENTATION_Msk              (0xFUL << PPU_PPU_IIDR_VPON_PPU_VARIANTIMPLEMENTATION_Pos)
+
+#define PPU_PPU_IIDR_VPON_PPU_PRODUCT_IDIMPLEMENTATION_Pos           20U
+#define PPU_PPU_IIDR_VPON_PPU_PRODUCT_IDIMPLEMENTATION_Msk           (0xFFFUL << PPU_PPU_IIDR_VPON_PPU_PRODUCT_IDIMPLEMENTATION_Pos)
+
+/* 0x0FCC   0x4000_2fcc
+    3:0     RO      ARCH_REV_MINOR              0x1
+    7:4     RO      ARCH_REV_MAJOR              0x1
+    31:8    RO      RESERVED                    0x0
+ */
+typedef union _PPU_PPU_AIDR_VPON_PPU_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t ARCH_REV_MINOR: 4;
+        uint32_t ARCH_REV_MAJOR: 4;
+        uint32_t RESERVED: 24;
+    };
+} PPU_PPU_AIDR_VPON_PPU_TYPE;
+
+/*0x4000_2fcc PPU_PPU_AIDR_VPON_PPU*/
+#define PPU_PPU_AIDR_VPON_PPU_ARCH_REV_MINOR_Pos                     0U
+#define PPU_PPU_AIDR_VPON_PPU_ARCH_REV_MINOR_Msk                     (0xFUL << PPU_PPU_AIDR_VPON_PPU_ARCH_REV_MINOR_Pos)
+
+#define PPU_PPU_AIDR_VPON_PPU_ARCH_REV_MAJOR_Pos                     4U
+#define PPU_PPU_AIDR_VPON_PPU_ARCH_REV_MAJOR_Msk                     (0xFUL << PPU_PPU_AIDR_VPON_PPU_ARCH_REV_MAJOR_Pos)
+
+#define PPU_PPU_AIDR_VPON_PPU_RESERVED_Pos                           8U
+#define PPU_PPU_AIDR_VPON_PPU_RESERVED_Msk                           (0xFFFFFFUL << PPU_PPU_AIDR_VPON_PPU_RESERVED_Pos)
+
+/* 0x0FD0   0x4000_2fd0
+    31:0    RO      RESERVED                    32'h0
+ */
+typedef union _PPU_ID_REG_VPON_PPU_1_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED;
+    };
+} PPU_ID_REG_VPON_PPU_1_TYPE;
+
+/*0x4000_2fd0 PPU_ID_REG_VPON_PPU_1*/
+#define PPU_ID_REG_VPON_PPU_1_RESERVED_Pos                           0U
+#define PPU_ID_REG_VPON_PPU_1_RESERVED_Msk                           (0xFFFFFFFFUL << PPU_ID_REG_VPON_PPU_1_RESERVED_Pos)
+
+/* 0x0FD4   0x4000_2fd4
+    31:0    RO      RESERVED                    32'h0
+ */
+typedef union _PPU_ID_REG_VPON_PPU_2_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED;
+    };
+} PPU_ID_REG_VPON_PPU_2_TYPE;
+
+/*0x4000_2fd4 PPU_ID_REG_VPON_PPU_2*/
+#define PPU_ID_REG_VPON_PPU_2_RESERVED_Pos                           0U
+#define PPU_ID_REG_VPON_PPU_2_RESERVED_Msk                           (0xFFFFFFFFUL << PPU_ID_REG_VPON_PPU_2_RESERVED_Pos)
+
+/* 0x0FD8   0x4000_2fd8
+    31:0    RO      RESERVED                    32'h0
+ */
+typedef union _PPU_ID_REG_VPON_PPU_3_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED;
+    };
+} PPU_ID_REG_VPON_PPU_3_TYPE;
+
+/*0x4000_2fd8 PPU_ID_REG_VPON_PPU_3*/
+#define PPU_ID_REG_VPON_PPU_3_RESERVED_Pos                           0U
+#define PPU_ID_REG_VPON_PPU_3_RESERVED_Msk                           (0xFFFFFFFFUL << PPU_ID_REG_VPON_PPU_3_RESERVED_Pos)
+
+/* 0x0FDC   0x4000_2fdc
+    31:0    RO      RESERVED                    32'h0
+ */
+typedef union _PPU_ID_REG_VPON_PPU_4_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED;
+    };
+} PPU_ID_REG_VPON_PPU_4_TYPE;
+
+/*0x4000_2fdc PPU_ID_REG_VPON_PPU_4*/
+#define PPU_ID_REG_VPON_PPU_4_RESERVED_Pos                           0U
+#define PPU_ID_REG_VPON_PPU_4_RESERVED_Msk                           (0xFFFFFFFFUL << PPU_ID_REG_VPON_PPU_4_RESERVED_Pos)
+
+/* 0x0FE0   0x4000_2fe0
+    31:0    RO      RESERVED                    32'h0
+ */
+typedef union _PPU_ID_REG_VPON_PPU_5_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED;
+    };
+} PPU_ID_REG_VPON_PPU_5_TYPE;
+
+/*0x4000_2fe0 PPU_ID_REG_VPON_PPU_5*/
+#define PPU_ID_REG_VPON_PPU_5_RESERVED_Pos                           0U
+#define PPU_ID_REG_VPON_PPU_5_RESERVED_Msk                           (0xFFFFFFFFUL << PPU_ID_REG_VPON_PPU_5_RESERVED_Pos)
+
+/* 0x0FE4   0x4000_2fe4
+    31:0    RO      RESERVED                    32'h0
+ */
+typedef union _PPU_ID_REG_VPON_PPU_6_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED;
+    };
+} PPU_ID_REG_VPON_PPU_6_TYPE;
+
+/*0x4000_2fe4 PPU_ID_REG_VPON_PPU_6*/
+#define PPU_ID_REG_VPON_PPU_6_RESERVED_Pos                           0U
+#define PPU_ID_REG_VPON_PPU_6_RESERVED_Msk                           (0xFFFFFFFFUL << PPU_ID_REG_VPON_PPU_6_RESERVED_Pos)
+
+/* 0x0FE8   0x4000_2fe8
+    31:0    RO      RESERVED                    32'h0
+ */
+typedef union _PPU_ID_REG_VPON_PPU_7_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED;
+    };
+} PPU_ID_REG_VPON_PPU_7_TYPE;
+
+/*0x4000_2fe8 PPU_ID_REG_VPON_PPU_7*/
+#define PPU_ID_REG_VPON_PPU_7_RESERVED_Pos                           0U
+#define PPU_ID_REG_VPON_PPU_7_RESERVED_Msk                           (0xFFFFFFFFUL << PPU_ID_REG_VPON_PPU_7_RESERVED_Pos)
+
+/* 0x0FEC   0x4000_2fec
+    31:0    RO      RESERVED                    32'h0
+ */
+typedef union _PPU_ID_REG_VPON_PPU_8_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED;
+    };
+} PPU_ID_REG_VPON_PPU_8_TYPE;
+
+/*0x4000_2fec PPU_ID_REG_VPON_PPU_8*/
+#define PPU_ID_REG_VPON_PPU_8_RESERVED_Pos                           0U
+#define PPU_ID_REG_VPON_PPU_8_RESERVED_Msk                           (0xFFFFFFFFUL << PPU_ID_REG_VPON_PPU_8_RESERVED_Pos)
+
+/* 0x0FF0   0x4000_2ff0
+    31:0    RO      RESERVED                    32'h0
+ */
+typedef union _PPU_ID_REG_VPON_PPU_9_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED;
+    };
+} PPU_ID_REG_VPON_PPU_9_TYPE;
+
+/*0x4000_2ff0 PPU_ID_REG_VPON_PPU_9*/
+#define PPU_ID_REG_VPON_PPU_9_RESERVED_Pos                           0U
+#define PPU_ID_REG_VPON_PPU_9_RESERVED_Msk                           (0xFFFFFFFFUL << PPU_ID_REG_VPON_PPU_9_RESERVED_Pos)
+
+/* 0x0FF4   0x4000_2ff4
+    31:0    RO      RESERVED                    32'h0
+ */
+typedef union _PPU_ID_REG_VPON_PPU_10_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED;
+    };
+} PPU_ID_REG_VPON_PPU_10_TYPE;
+
+/*0x4000_2ff4 PPU_ID_REG_VPON_PPU_10*/
+#define PPU_ID_REG_VPON_PPU_10_RESERVED_Pos                          0U
+#define PPU_ID_REG_VPON_PPU_10_RESERVED_Msk                          (0xFFFFFFFFUL << PPU_ID_REG_VPON_PPU_10_RESERVED_Pos)
+
+/* 0x0FF8   0x4000_2ff8
+    31:0    RO      RESERVED                    32'h0
+ */
+typedef union _PPU_ID_REG_VPON_PPU_11_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED;
+    };
+} PPU_ID_REG_VPON_PPU_11_TYPE;
+
+/*0x4000_2ff8 PPU_ID_REG_VPON_PPU_11*/
+#define PPU_ID_REG_VPON_PPU_11_RESERVED_Pos                          0U
+#define PPU_ID_REG_VPON_PPU_11_RESERVED_Msk                          (0xFFFFFFFFUL << PPU_ID_REG_VPON_PPU_11_RESERVED_Pos)
+
+/* 0x0FFC   0x4000_2ffc
+    31:0    RO      RESERVED                    32'h0
+ */
+typedef union _PPU_ID_REG_VPON_PPU_12_TYPE
+{
+    uint32_t d32;
+    struct
+    {
+        uint32_t RESERVED;
+    };
+} PPU_ID_REG_VPON_PPU_12_TYPE;
+
+/*0x4000_2ffc PPU_ID_REG_VPON_PPU_12*/
+#define PPU_ID_REG_VPON_PPU_12_RESERVED_Pos                          0U
+#define PPU_ID_REG_VPON_PPU_12_RESERVED_Msk                          (0xFFFFFFFFUL << PPU_ID_REG_VPON_PPU_12_RESERVED_Pos)
+
+#define PPU_VPON_BASE 0x40002000
+#define PPU_VCORE_BASE 0x4001B000
+
+#define PPU_REG_READ(Base, Offset)\
+    ((uint32_t)*((volatile uint32_t*)(Base+(Offset))))
+
+#define PPU_REG_WRITE(Base, Offset, Value)\
+    ((*((volatile uint32_t*)(Base + (Offset)))) = (Value))
+
+#define PPU_REG_UPDATE(Base, Offset, Mask, Value) \
+    do {\
+        uint32_t temp;\
+        temp = PPU_REG_READ(Base, Offset) & ~(Mask);\
+        PPU_REG_WRITE(Base, Offset, (temp | ((Value) & (Mask))));\
+    } while(0)
+
+#define PPU_REG_READ_BITFIELD(Base, Offset, Bitfield)                   \
+    (((Offset##_TYPE)PPU_REG_READ(Base, Offset)).Bitfield)
+
+#define PPU_REG_WRITE_BITFIELD(Base, Offset, Bitfield, Value)           \
+    do {                                                        \
+        Offset##_TYPE temp = {.d32 = PPU_REG_READ(Base, Offset)};       \
+        temp.Bitfield = Value;                                         \
+        PPU_REG_WRITE(Base, Offset, temp.d32);                          \
+    } while(0)
+
+#endif //#define PPU_REG_H
diff --git a/bee/soc/inc/rtl87x2j/rom_uuid.h b/bee/soc/inc/rtl87x2j/rom_uuid.h
new file mode 100755
index 00000000..d4bb7c75
--- /dev/null
+++ b/bee/soc/inc/rtl87x2j/rom_uuid.h
@@ -0,0 +1,4 @@
+#ifndef _symboltable_uuid_h
+#define _symboltable_uuid_h
+#define DEFINE_symboltable_uuid { 0x28,0x6c,0x67,0x26,0xdf,0x9d,0xf0,0x11,0x89,0x0a,0xd3,0x6b,0xbf,0x19,0x12,0x7d }
+#endif
diff --git a/bee/soc/inc/rtl87x2j/vector_table.h b/bee/soc/inc/rtl87x2j/vector_table.h
new file mode 100755
index 00000000..c89f1e28
--- /dev/null
+++ b/bee/soc/inc/rtl87x2j/vector_table.h
@@ -0,0 +1,17 @@
+#ifndef VECTOR_TABLE_H
+#define VECTOR_TABLE_H
+
+// *INDENT-OFF*
+#include "vector_table_auto_gen.h"
+
+#define SUB_IRQ_DEF(first_irq, second_index) (((first_irq) << 8) | (second_index))
+#define GET_FIRST_IRQn(sub_irq)              ((sub_irq) >> 8)
+
+typedef void (* P_SECOND_VECTOR_UPDATE)(uint32_t irqn, IRQ_Fun isr_handler);
+bool ram_vector_table_register(uint8_t irqn, P_SECOND_VECTOR_UPDATE reg_func);
+
+bool ram_vector_table_init(uint32_t ram_vector_addr);
+bool ram_vector_table_update(int irqn, IRQ_Fun isr_handler);
+
+// *INDENT-ON* 
+#endif //#define VECTOR_TABLE_H
diff --git a/bee/soc/inc/rtl87x2j/vector_table_auto_gen.h b/bee/soc/inc/rtl87x2j/vector_table_auto_gen.h
new file mode 100755
index 00000000..3165ea10
--- /dev/null
+++ b/bee/soc/inc/rtl87x2j/vector_table_auto_gen.h
@@ -0,0 +1,135 @@
+#ifndef VECTOR_TABLE_AUTO_GEN_H
+#define VECTOR_TABLE_AUTO_GEN_H
+
+// *INDENT-OFF*
+#include "stdint.h"
+#include "stdbool.h"
+#include "cmsis_compiler.h"
+
+typedef void (*IRQ_Fun)(void);       // < ISR Handler Prototype
+
+/* ================================================================================ */
+/* ================                  IRQ_NUMBER                    ================ */
+/* ======== Reference: Bee5_Vector_Table_20250822v0.xlsx   =========== */
+/* ================================================================================ */
+
+typedef enum IRQn
+{
+    NMI_IRQn =                             -14,
+    HardFault_IRQn =                       -13,
+    MemoryManagement_IRQn =                -12,
+    BusFault_IRQn =                        -11,
+    UsageFault_IRQn =                      -10,
+    SecureFault_IRQn =                     -9,
+    RSVD0_IRQn =                           -8,
+    RSVD1_IRQn =                           -7,
+    RSVD2_IRQn =                           -6,
+    SVCall_IRQn =                          -5,
+    Debug_Monitor_IRQn =                   -4,
+    RSVD3_IRQn =                           -3,
+    PendSV_IRQn =                          -2,
+    SysTick_IRQn =                         -1,
+    AON_IRQn =                             0,
+    WDT_IRQn =                             1,
+    RXI300_IRQn =                          2,
+    BTMAC_0_IRQn =                         3,
+    BTMAC_0_WRAP_AROUND_IRQn =             4,
+    TIMER0_CH0_CH1_IRQn =                  5,
+    BT_BZ_DMA_0_IRQn =                     6,
+    PROPIETARY_2P4G_IRQn =                 7,
+    RTC_IRQn =                             8,
+    SCH_PLN_IRQn =                         9,
+    I2S_0_RX_IRQn =                        10,
+    I2S_0_TX_IRQn =                        11,
+    TIMER1_CH0_IRQn =                      12,
+    TIMER1_CH1_IRQn =                      13,
+    TIMER1_CH2_IRQn =                      14,
+    TIMER1_CH3_IRQn =                      15,
+    TIMER1_CH4_IRQn =                      16,
+    TIMER1_CH5_IRQn =                      17,
+    TIMER1_CH6_IRQn =                      18,
+    TIMER1_CH7_IRQn =                      19,
+    TIMER1_CH8_IRQn =                      20,
+    TIMER2_CH0_IRQn =                      21,
+    RSVD4_IRQn =                           22,
+    PERIPHERAL_ISR_IRQn =                  23,
+    UART0_IRQn =                           24,
+    UART1_IRQn =                           25,
+    UART2_IRQn =                           26,
+    UART3_IRQn =                           27,
+    SPI_0_IRQn =                           28,
+    SPI_1_IRQn =                           29,
+    I2C_0_IRQn =                           30,
+    I2C_1_IRQn =                           31,
+    DMA0_CH0_IRQn =                        32,
+    DMA0_CH1_IRQn =                        33,
+    DMA0_CH2_IRQn =                        34,
+    DMA0_CH3_IRQn =                        35,
+    DMA0_CH4_IRQn =                        36,
+    DMA0_CH5_IRQn =                        37,
+    GPIOA0_7_IRQn =                        38,
+    GPIOA8_15_IRQn =                       39,
+    GPIOA16_23_IRQn =                      40,
+    GPIOA24_31_IRQn =                      41,
+    IR_IRQn =                              42,
+    KEYSCAN_IRQn =                         43,
+    LPQDEC_IRQn =                          44,
+    ADC0_IRQn =                            45,
+    SPI3W_IRQn =                           46,
+    LPC_IRQn =                             47,
+    MAILBOX_IRQn =                         48,
+    TM_IRQn =                              49,
+    A2C_IRQn =                             50,
+    SHA256_IRQn =                          51,
+    TRNG_IRQn =                            52,
+    RAP_IRQn =                             53,
+    MAE_IRQn =                             54,
+    PPU0_IRQn =                            55,
+    PPU1_IRQn =                            56,
+    USB_IRQn =                             57,
+    USB_ENDP_MULTI_PROC_INT_IRQn =         58,
+    USB_SUSPEND_N_INT_IRQn =               59,
+    USB_IN_EP_INT_0_IRQn =                 60,
+    USB_IN_EP_INT_1_IRQn =                 61,
+    USB_IN_EP_INT_2_IRQn =                 62,
+    USB_IN_EP_INT_3_IRQn =                 63,
+    USB_IN_EP_INT_4_IRQn =                 64,
+    USB_IN_EP_INT_5_IRQn =                 65,
+    USB_IN_EP_INT_6_IRQn =                 66,
+    USB_OUT_EP_INT_0_IRQn =                67,
+    USB_OUT_EP_INT_1_IRQn =                68,
+    USB_OUT_EP_INT_2_IRQn =                69,
+    USB_OUT_EP_INT_3_IRQn =                70,
+    USB_OUT_EP_INT_4_IRQn =                71,
+    USB_OUT_EP_INT_5_IRQn =                72,
+    USB_OUT_EP_INT_6_IRQn =                73,
+    USB_SOF_INT_IRQn =                     74,
+    GPIOA32_39_IRQn =                      75,
+    GPIOA40_47_IRQn =                      76,
+    GPIOA48_55_IRQn =                      77,
+    PAD_IRQn =                             78,
+    SPI_2_IRQn =                           79,
+    AUDIO_IRQn =                           80,
+    TMETER_FW_IRQn =                       81,
+    RXI300_EXT_IRQn =                      82,
+    GRTC_CH0_IRQn =                        83,
+    GRTC_CH1_IRQn =                        84,
+    GRTC_CH2_IRQn =                        85,
+    GRTC_CH3_IRQn =                        86,
+    GRTC_CH4_IRQn =                        87,
+    GRTC_CH5_IRQn =                        88,
+    GRTC_CH6_IRQn =                        89,
+    GRTC_CH7_IRQn =                        90,
+    IRQn_MAX,
+} IRQn_Type;
+
+#define IRQn_TO_VECTORn(irqn)   ((irqn) + 16)
+
+extern void *RomVectorTable[] ;
+extern void *RamVectorTable[IRQn_TO_VECTORn(IRQn_MAX)];
+
+void VTORInit(void);
+void vector_table_ram_init(void);
+
+// *INDENT-ON*
+#endif //#define VECTOR_TABLE_AUTO_GEN_H
diff --git a/bee/sys/CMakeLists.txt b/bee/sys/CMakeLists.txt
new file mode 100644
index 00000000..39018cc8
--- /dev/null
+++ b/bee/sys/CMakeLists.txt
@@ -0,0 +1,4 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_include_directories_ifdef(CONFIG_SOC_SERIES_RTL87X2G inc/rtl87x2g)
diff --git a/bee/sys/inc/rtl87x2g/sys_reset.h b/bee/sys/inc/rtl87x2g/sys_reset.h
new file mode 100644
index 00000000..36f0a46a
--- /dev/null
+++ b/bee/sys/inc/rtl87x2g/sys_reset.h
@@ -0,0 +1,102 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*============================================================================*
+ *               Define to prevent recursive inclusion
+ *============================================================================*/
+#ifndef __SYS_RESET_H_
+#define __SYS_RESET_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*============================================================================*
+ *                               Header Files
+*============================================================================*/
+#include "wdt/inc/rtl_wdt.h"
+
+/*============================================================================*
+ *                         Types
+ *============================================================================*/
+/**
+  * @brief       Watch Dog Mode structure definition.
+  * @note        Watch Dog Reset reason introduction:
+  *              1.If you want to get reset reason from aon 0x15, deviding three types:
+  *              a) HW reset: aon reg 0x15 is cleared to 0, magic pattern on ram will change
+  *              b) SW RESET_ALL: aon reg 0x15 is cleared to 0,but magic pattern on ram not change
+  *              c) SW RESET_ALL_EXCEPT_AON: obtain reset reason by reading aon reg 0x15 .
+  *              2. Attention: don't use 0x1 as your reset reason when using RESET_ALL_EXCEPT_AON type! Because 0x1 is default value.
+  */
+typedef enum
+{
+    RESET_REASON_HW                         = 0x0,
+    RESET_REASON_WDT_TIMEOUT                = 0x1,
+    RESET_REASON_BOOT_EFUSE_INVALID         = 0x2,
+    RESET_REASON_BOOT_FLASH_INVALID         = 0x3,
+    RESET_REASON_BOOT_RETRY_COUNT_LIMIT     = 0x4,
+    RESET_REASON_HARD_FAULT                 = 0x5,
+    RESET_REASON_FLASH_IOCTL                = 0x6,
+    RESET_REASON_LOWER_STACK                = 0x7,
+    RESET_REASON_PASSWORD_DEBUG             = 0x8,
+    RESET_REASON_ENTER_FT_MODE              = 0x9,
+    RESET_REASON_SWITCH_TO_HCI_MODE         = 0xA,
+    RESET_REASON_SWITCH_TO_OTA_MODE         = 0xB,
+    RESET_REASON_DFU_FW_RESET               = 0xC,
+    RESET_REASON_DFU_UPDATE_IMG             = 0xD,
+    RESET_REASON_DFU_UPDATE_IMG_FAIL        = 0xE,
+    RESET_REASON_DFU_DISCONN_RSP            = 0xF,
+    RESET_REASON_DFU_DISCONN_IND            = 0x10,
+    RESET_REASON_ROM_DFU_OPCODE_SYSTEM_RESET = 0x11,
+    RESET_REASON_DATATRANS_PATCH_ACTIVE     = 0x12,
+    RESET_REASON_DATATRANS_SYSTEM_RESET     = 0x13,
+    RESET_REASON_MP_RESET                   = 0x14,
+    RESET_REASON_FEATURE_CHECK_FAIL         = 0x15,
+    RESET_REASON_FLASH_LAYOUT_OVERFLOW      = 0x16,
+    RESET_REASON_DFU_UPDATE_COMPRESSED_IMG  = 0x17,
+    RESET_REASON_BRANCH_TO_NS_FAIL          = 0x18,
+    RESET_REASON_BRANCH_TO_S_FAIL           = 0x19,
+    RESET_REASON_DLPS                       = 0x1A,
+    RESET_REASON_POWER_DOWN                 = 0x1B,
+    RESET_REASON_ZEPHYR                     = 0x1C,
+    SW_RESET_APP_END                = 0xFF,
+} T_SW_RESET_REASON;
+
+/*============================================================================*
+ *                              Functions
+*============================================================================*/
+/**
+ * @brief Execute a system reset via the watchdog.
+ * 
+ * This function performs a system reboot using the specified watchdog mode
+ * `wdt_mode`, and optionally logs the reason for the reset as `reset_reason`.
+ * 
+ * @param wdt_mode Specifies the watchdog mode for the reset, refer to @ref WDTMode_TypeDef.
+ * @param reset_reason Provides the reason for the system reset, useful for further diagnostics and tracking.
+ */
+
+extern void WDG_SystemReset(WDTMode_TypeDef wdt_mode, int reset_reason);
+
+/**
+ * @brief Retrieve the reason for the system reset.
+ * 
+ * This function returns the reason for the most recent system reset, useful for diagnosing reboot events.
+ * 
+ * @param none
+ * @return Returns the reason for the system reset, type T_SW_RESET_REASON.
+ */
+
+static inline T_SW_RESET_REASON reset_reason_get()
+{
+    extern T_SW_RESET_REASON sw_reset_reason;
+    return sw_reset_reason;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYS_RESET_H_ */
diff --git a/bee/tools/mpcli/configs/README b/bee/tools/mpcli/configs/README
new file mode 100644
index 00000000..286ca604
--- /dev/null
+++ b/bee/tools/mpcli/configs/README
@@ -0,0 +1,5 @@
+# Realtek MPCli Tool Configuration Files
+
+This directory contains configuration files required for flashing **essential system images** (such as Bootloader patches, System patches, and Configuration files) to Realtek Bee series SoCs using the Realtek MPCli tool integration in Zephyr.
+
+These JSON files are used by the `west flash` command to define the memory layout and the location of the binary blobs.
diff --git a/bee/tools/mpcli/configs/rtl8752h_essential_images.json b/bee/tools/mpcli/configs/rtl8752h_essential_images.json
new file mode 100644
index 00000000..02d142f6
--- /dev/null
+++ b/bee/tools/mpcli/configs/rtl8752h_essential_images.json
@@ -0,0 +1,41 @@
+{
+    "mptoolconfig": {
+        "port": "",
+        "baud": "1000000",
+        "appimage": {
+            "relativepath": "../../../../zephyr/blobs/bee/rtl8752h/bin/single_bank",
+            "file": [
+                {
+                    "id": 0,
+                    "address": "0x00801000",
+                    "name": "configFile_2025.09.28.09-c56ff8be480e864851703087f3d661d3.bin",
+                    "enable": "1"
+                },
+                {
+                    "id": 0,
+                    "address": "0x00802000",
+                    "name": "OTAHeader_Bank0_1.0.0.1-b2dff20b37cc479bf054669db699e2e1.bin",
+                    "enable": "1"
+                },
+                {
+                    "id": 1,
+                    "address": "0x0080A000",
+                    "name": "BANK0_fsbl_MP_master_1.2.4.0_722f404-e67afdd707414f84601a5bf52b53c788.bin",
+                    "enable": "1"
+                },
+                {
+                    "id": 2,
+                    "address": "0x00803000",
+                    "name": "BANK0_Patch_MP_release_0.0.322.2_56a2dbcd-2ca079e00bca6b92dd2af96124332221.bin",
+                    "enable": "1"
+                },
+                {
+                    "id": 3,
+                    "address": "0x0080B000",
+                    "name": "bt_stack_patch_MP_master_0.0.145.0_ab89e0d5-982493ffb677098b7f324aef124f9554.bin",
+                    "enable": "1"
+                }
+            ]
+        }
+    }
+}
diff --git a/bee/tools/mpcli/configs/rtl87x2g_essential_images.json b/bee/tools/mpcli/configs/rtl87x2g_essential_images.json
new file mode 100644
index 00000000..e035dd22
--- /dev/null
+++ b/bee/tools/mpcli/configs/rtl87x2g_essential_images.json
@@ -0,0 +1,47 @@
+{
+    "mptoolconfig": {
+        "port": "",
+        "baud": "1000000",
+        "appimage": {
+            "relativepath": "../../../../zephyr/blobs/bee/rtl87x2g/bin",
+            "file": [
+                {
+                    "id": 0,
+                    "address": "0x4001000",
+                    "name": "configFile_2025.09.02.14-e600f2d80e7f4ab3e6f089b6174ff6d7.bin",
+                    "enable": "1"
+                },
+                {
+                    "id": 1,
+                    "address": "0x4002000",
+                    "name": "BANK0_boot_patch_MP_release_1.0.183.27_e91dd4ad-dffb4c6d9a02fea1a24302c6e1a76fda.bin",
+                    "enable": "1"
+                },
+                {
+                    "id": 2,
+                    "address": "0x400a000",
+                    "name": "BANK1_boot_patch_MP_release_1.0.183.27_e91dd4ad-8a0390ad5ea191e414f1c00c6b4e366c.bin",
+                    "enable": "1"
+                },
+                {
+                    "id": 3,
+                    "address": "0x4012000",
+                    "name": "OTAHeader_Bank0_1.0.0.1-3e442e5fa761e6422f0b936bc5fb0c25.bin",
+                    "enable": "1"
+                },
+                {
+                    "id": 4,
+                    "address": "0x4013000",
+                    "name": "BANK0_sys_patch_MP_release_1.0.183.27_e91dd4ad-59b00aef9fefc715b8fb60de65a1ffe2.bin",
+                    "enable": "1"
+                },
+                {
+                    "id": 5,
+                    "address": "0x401b000",
+                    "name": "bt_stack_patch_MP_master_0.0.126.0_a075812a-ac40d4abfa2d071f5ad63aac0daad0f2.bin",
+                    "enable": "1"
+                }
+            ]
+        }
+    }
+}
diff --git a/bee/tools/mpcli/configs/rtl87x2j_essential_images.json b/bee/tools/mpcli/configs/rtl87x2j_essential_images.json
new file mode 100644
index 00000000..efc39aaa
--- /dev/null
+++ b/bee/tools/mpcli/configs/rtl87x2j_essential_images.json
@@ -0,0 +1,41 @@
+{
+    "mptoolconfig": {
+        "port": "",
+        "baud": "1000000",
+        "appimage": {
+            "relativepath": "../../../../zephyr/blobs/bee/rtl87x2j/bin",
+            "file": [
+                {
+                    "id": 0,
+                    "address": "0x2000000",
+                    "name": "bootloader_MP_sdk_0.0.0.3_aca08d52-5b63d3ad719587339914e4cc8562921a.bin",
+                    "enable": "1"
+                },
+                {
+                    "id": 0,
+                    "address": "0x2012C00",
+                    "name": "OTAHeader_Bank0_1.0.0.1-4d66efc3f9a32560260733ef737839b8.bin",
+                    "enable": "1"
+                },
+                {
+                    "id": 1,
+                    "address": "0x2013000",
+                    "name": "sys_patch_MP_sdk_0.0.0.0_16104e62-66a73929aca0d223da6cf0ef24f994fa.bin",
+                    "enable": "1"
+                },
+                {
+                    "id": 2,
+                    "address": "0x2200400",
+                    "name": "sys_config_MP-024219133a8640b23830162e320f49ee.bin",
+                    "enable": "1"
+                },
+                {
+                    "id": 3,
+                    "address": "0x2019000",
+                    "name": "lowerstack_MP_100_3.0.0.111_831ea602-129ec9e990d94682d92c3f24f75d6333.bin",
+                    "enable": "1"
+                }
+            ]
+        }
+    }
+}
diff --git a/bee/util/CMakeLists.txt b/bee/util/CMakeLists.txt
new file mode 100644
index 00000000..dc45c34a
--- /dev/null
+++ b/bee/util/CMakeLists.txt
@@ -0,0 +1,7 @@
+# Copyright (c) 2026, Realtek Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_include_directories_ifdef(CONFIG_SOC_SERIES_RTL87X2G inc/rtl87x2g)
+zephyr_include_directories_ifdef(CONFIG_SOC_SERIES_RTL8752H inc/rtl8752h)
+zephyr_include_directories_ifdef(CONFIG_SOC_SERIES_RTL87X2J inc/rtl87x2j)
+zephyr_include_directories(inc)
diff --git a/bee/util/inc/access.h b/bee/util/inc/access.h
new file mode 100644
index 00000000..32548c88
--- /dev/null
+++ b/bee/util/inc/access.h
@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef IO_H
+#define IO_H
+
+#ifndef LITTLE_ENDIAN
+#define LITTLE_ENDIAN                        0
+#endif
+
+#ifndef BIG_ENDIAN
+#define BIG_ENDIAN                           1
+#endif
+
+#define SYSTEM_ENDIAN                        LITTLE_ENDIAN
+
+#define SWAP32(x) ((uint32_t)(                         \
+                                                       (((uint32_t)(x) & (uint32_t)0x000000ff) << 24) |            \
+                                                       (((uint32_t)(x) & (uint32_t)0x0000ff00) <<  8) |            \
+                                                       (((uint32_t)(x) & (uint32_t)0x00ff0000) >>  8) |            \
+                                                       (((uint32_t)(x) & (uint32_t)0xff000000) >> 24)))
+
+#define WAP16(x) ((uint16_t)(                         \
+                                                      (((uint16_t)(x) & (uint16_t)0x00ff) <<  8) |            \
+                                                      (((uint16_t)(x) & (uint16_t)0xff00) >>  8)))
+
+#if SYSTEM_ENDIAN == LITTLE_ENDIAN
+#ifndef rtk_le16_to_cpu
+#define rtk_cpu_to_le32(x)      ((uint32_t)(x))
+#define rtk_le32_to_cpu(x)      ((uint32_t)(x))
+#define rtk_cpu_to_le16(x)      ((uint16_t)(x))
+#define rtk_le16_to_cpu(x)      ((uint16_t)(x))
+#define rtk_cpu_to_be32(x)      SWAP32((x))
+#define rtk_be32_to_cpu(x)      SWAP32((x))
+#define rtk_cpu_to_be16(x)      WAP16((x))
+#define rtk_be16_to_cpu(x)      WAP16((x))
+#endif
+
+#elif SYSTEM_ENDIAN == BIG_ENDIAN
+#ifndef rtk_le16_to_cpu
+#define rtk_cpu_to_le32(x)      SWAP32((x))
+#define rtk_le32_to_cpu(x)      SWAP32((x))
+#define rtk_cpu_to_le16(x)      WAP16((x))
+#define rtk_le16_to_cpu(x)      WAP16((x))
+#define rtk_cpu_to_be32(x)      ((uint32_t)(x))
+#define rtk_be32_to_cpu(x)      ((uint32_t)(x))
+#define rtk_cpu_to_be16(x)      ((uint16_t)(x))
+#define rtk_be16_to_cpu(x)      ((uint16_t)(x))
+#endif
+#endif
+
+#define HAL_READ32(base, addr)            \
+    rtk_le32_to_cpu(*((volatile uint32_t *)(base + addr)))
+
+#define HAL_WRITE32(base, addr, value32)  \
+    ((*((volatile uint32_t *)(base + addr))) = rtk_cpu_to_le32(value32))
+
+#define HAL_UPDATE32(addr, mask, value32)  \
+    HAL_WRITE32(0, addr, (HAL_READ32(0, addr) & ~(mask)) | ((value32) & (mask)))
+
+#define HAL_READ16(base, addr)            \
+    rtk_le16_to_cpu(*((volatile uint16_t *)(base + addr)))
+
+#define HAL_WRITE16(base, addr, value)  \
+    ((*((volatile uint16_t *)(base + addr))) = rtk_cpu_to_le16(value))
+
+#define HAL_UPDATE16(addr, mask, value16)  \
+    HAL_WRITE16(0, addr, (HAL_READ16(0, addr) & ~(mask)) | ((value16) & (mask)))
+
+#define HAL_READ8(base, addr)            \
+    (*((volatile uint8_t *)(base + addr)))
+
+#define HAL_WRITE8(base, addr, value)  \
+    ((*((volatile uint8_t *)(base + addr))) = value)
+
+#define HAL_UPDATE8(addr, mask, value8)  \
+    HAL_WRITE8(0, addr, (HAL_READ8(0, addr) & ~(mask)) | ((value8) & (mask)))
+
+
+#endif //#define IO_H 
diff --git a/bee/util/inc/bitops.h b/bee/util/inc/bitops.h
new file mode 100644
index 00000000..af7041f4
--- /dev/null
+++ b/bee/util/inc/bitops.h
@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _BITOPS_H_
+#define _BITOPS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*============================================================================*
+ *                               Header Files
+*============================================================================*/
+
+#include <stdlib.h>
+#include <stdint.h>
+#include <stdbool.h>
+
+/*============================================================================*
+ *                              Types
+*============================================================================*/
+
+#define BIT0        0x00000001
+#define BIT1        0x00000002
+#define BIT2        0x00000004
+#define BIT3        0x00000008
+#define BIT4        0x00000010
+#define BIT5        0x00000020
+#define BIT6        0x00000040
+#define BIT7        0x00000080
+#define BIT8        0x00000100
+#define BIT9        0x00000200
+#define BIT10       0x00000400
+#define BIT11       0x00000800
+#define BIT12       0x00001000
+#define BIT13       0x00002000
+#define BIT14       0x00004000
+#define BIT15       0x00008000
+#define BIT16       0x00010000
+#define BIT17       0x00020000
+#define BIT18       0x00040000
+#define BIT19       0x00080000
+#define BIT20       0x00100000
+#define BIT21       0x00200000
+#define BIT22       0x00400000
+#define BIT23       0x00800000
+#define BIT24       0x01000000
+#define BIT25       0x02000000
+#define BIT26       0x04000000
+#define BIT27       0x08000000
+#define BIT28       0x10000000
+#define BIT29       0x20000000
+#define BIT30       0x40000000
+#define BIT31       0x80000000
+
+#ifndef BIT
+#define BIT(_n)     (uint32_t)(1U << (_n))
+#endif
+#define BIT64(_n)   (1ULL << (_n))
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  // _BITOPS_H_
+
diff --git a/bee/util/inc/rtl8752h/utils.h b/bee/util/inc/rtl8752h/utils.h
new file mode 100644
index 00000000..56dcf0e9
--- /dev/null
+++ b/bee/util/inc/rtl8752h/utils.h
@@ -0,0 +1,97 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _UTILS_H_
+#define _UTILS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*============================================================================*
+ *                               Header Files
+*============================================================================*/
+#include <stdint.h>
+#include <stdbool.h>
+#include <stddef.h>
+/** @defgroup  PLATFORM_UTILS Platform Utilities
+    * @brief Utility helper functions
+    * @{
+    */
+
+/*============================================================================*
+ *                              Constants
+ *============================================================================*/
+/** @defgroup PLATFORM_UTILS_Exported_Constants Platform Utilities Exported  Constants
+    * @brief
+    * @{
+    */
+
+#define CLOCK_100MHZ    100000000
+#define CLOCK_90MHZ     90000000
+#define CLOCK_40MHZ     40000000
+#define CLOCK_53MHZ     53333333
+#define CLOCK_80MHZ     80000000
+#define CLOCK_20MHZ     20000000
+#define CLOCK_10MHZ     10000000
+#define CLOCK_5MHZ      5000000
+#define CLOCK_2P5MHZ    2500000
+#define CLOCK_1P25MHZ   1250000
+#define CLOCK_625KHZ    625000
+
+/** @} */ /* End of group PLATFORM_UTILS_Exported_Constants */
+
+
+
+
+/*============================================================================*
+ *                              Functions
+ *============================================================================*/
+/** @defgroup PLATFORM_UTILS_Exported_Functions Platform Utilities Exported Functions
+    * @brief
+    * @{
+    */
+
+/**
+ * @brief Busy delay for specified millisecond
+ * @param t   to specify t milliseconds to delay
+ * @return none
+ */
+extern volatile void (*platform_delay_ms)(uint32_t t);
+
+/**
+ * @brief Busy delay for specified micro second
+ * @param t   to specify t micro seconds to delay
+ * @return none
+ */
+extern volatile void (*platform_delay_us)(uint32_t t);
+
+/**
+ * @brief Get the vendor timer tick
+
+ * @param none
+ * @return none
+ * @note Features of the vendor timer:
+ *         (1) clock rate is 40M
+ *         (2) width is 26 bits (max 0x3FFFFFF)
+ *         (3) tick counter is incremental
+ *
+ */
+static inline uint32_t platform_vendor_tick(void)
+{
+    return ((*(uint32_t *)(0x4005817C)) & 0x3FFFFFF);
+}
+
+/** @} */ /* End of group PLATFORM_UTILS_Exported_Functions */
+
+/** @} */ /* End of group PLATFORM_UTILS */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/bee/util/inc/rtl87x2g/utils.h b/bee/util/inc/rtl87x2g/utils.h
new file mode 100644
index 00000000..4ab578bf
--- /dev/null
+++ b/bee/util/inc/rtl87x2g/utils.h
@@ -0,0 +1,191 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _UTILS_NS_H_
+#define _UTILS_NS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+/*============================================================================*
+ *                               Header Files
+*============================================================================*/
+#include <stdint.h>
+#include <stdbool.h>
+#include "utils_nsc.h"
+
+/** @defgroup PLATFORM_UTILS  Platform utils
+  * @brief
+  * @{
+  */
+
+/*============================================================================*
+ *                              Macros
+ *============================================================================*/
+/** @defgroup PLATFORM_UTILS_Exported_Macros Platform utils Exported Macros
+  * @brief
+  * @{
+  */
+
+#ifndef ABS
+#define ABS(x)     (((x) > 0) ? (x) : ((~(x))+1))
+#endif
+
+#define BIT64(_n)   (1ULL << (_n))
+
+#define DIVIDE_AND_ROUND(dividend, divisor)     (((dividend) + ((divisor) >> 1)) / (divisor))
+
+#define DIVIDE_AND_ROUNDUP(dividend, divisor)   (((dividend) + ((divisor) - 1)) / (divisor))
+
+#define CLOCK_COUNT_DIFF(clk_begin, clk_end, bit_mask) (((((uint64_t)clk_end & ((uint64_t)bit_mask - 1)) | (uint64_t)bit_mask) - ((uint64_t)clk_begin & ((uint64_t)bit_mask - 1))) & ((uint64_t)bit_mask - 1))
+
+#define VENDOR_COUNTER_BASE_ADDRESS 0x40006000
+
+#define VENDOR_COUNTER_READ(Vendor_offset) \
+    ((uint32_t)*((volatile uint32_t*)(VENDOR_COUNTER_BASE_ADDRESS+(Vendor_offset))))
+#define VENDOR_COUNTER_WRITE(Vendor_offset, Value) \
+    ((*((volatile uint32_t*)(VENDOR_COUNTER_BASE_ADDRESS + (Vendor_offset)))) = (Value))
+
+#define CPU_CNT_BIT_NUM             BIT64(32)
+
+#define PF_RTC_BIT_NUM              BIT64(32)
+
+#define PLATFORM_ASSERT(x) if( ( x ) == 0 ) { vAssertHandler(__FUNCTION__, __LINE__); }
+
+#define BUILD_BUG_ON_ZERO(e)  (sizeof(struct { int _; int:-!!(e); }) - sizeof(struct { int _; }))
+#ifndef SAME_TYPE
+#define SAME_TYPE(a, b)  __builtin_types_compatible_p(typeof(a), typeof(b))
+#endif
+#define MUST_BE_ARRAY(a)  BUILD_BUG_ON_ZERO(SAME_TYPE((a), &(*a)))
+
+#ifndef ARRAY_SIZE
+#define ARRAY_SIZE(a) ((sizeof(a) / sizeof(*a)) + MUST_BE_ARRAY(a))
+#endif
+#ifndef hex2char
+#define hex2char(val) ("0123456789abcdef"[(val) & 0xf])
+#endif
+
+#define count_1bits(x) (uint8_t)__builtin_popcount(x)
+#define count_0bits(x) (32 - count_1bits(x))
+#define check_inverse(data, inverse_data, mask) ((data ^ inverse_data) == mask)
+#define SET_BIT(val, mask)          ((val) |=  (mask))
+#define CLR_BIT(val, mask)          ((val)  &= ~(mask))
+
+extern uint32_t (*get_SystemCpuClock)(void);
+
+#define US_TO_CPU_CLK(us, residual)\
+    cal_quotient_remainder(1000000, get_SystemCpuClock(), us, &residual)
+
+#define CPU_CLK_TO_US(cpu_clk)\
+    cal_quotient_remainder(get_SystemCpuClock(), 1000000, cpu_clk, NULL)
+
+/** End of PLATFORM_UTILS_Exported_Macros
+  * @}
+  */
+
+/*============================================================================*
+ *                              Types
+ *============================================================================*/
+/** @defgroup PLATFORM_UTILS_Exported_Types Platform utils Exported Types
+  * @brief
+  * @{
+  */
+
+typedef enum
+{
+    ROUND                   = 0,
+    ROUNDUP                 = 1,
+    ROUNDDOWN               = 2,
+} RoundType;
+
+typedef enum
+{
+    SYSTICK_EXTERNAL_CLOCK   = 0,
+    SYSTICK_PROCESSOR_CLOCK  = 1
+} SYSTICK_CLK_SRC_TYPE;
+
+/** End of PLATFORM_UTILS_Exported_Types
+  * @}
+  */
+
+/*============================================================================*
+*                              Functions
+*============================================================================*/
+/** @defgroup PLATFORM_UTILS_Exported_Functions Platform utils Exported Functions
+  * @brief
+  * @{
+  */
+
+#if   defined ( __CC_ARM )
+/**
+ * @brief Busy delay for specified micro second
+ * @param t   to specify t micro seconds to delay
+ * @return none
+ */
+extern volatile void (*platform_delay_ms)(uint32_t t);
+/**
+ * @brief Busy delay for specified millisecond
+ * @param t   to specify t milliseconds to delay
+ * @return none
+ */
+extern volatile void (*platform_delay_us)(uint32_t t);
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) || defined (__GNUC__)
+/**
+ * @brief Busy delay for specified micro second
+ * @param t   to specify t micro seconds to delay
+ * @return none
+ */
+extern void (*platform_delay_ms)(uint32_t t);
+/**
+ * @brief Busy delay for specified millisecond
+ * @param t   to specify t milliseconds to delay
+ * @return none
+ */
+extern void (*platform_delay_us)(uint32_t t);
+#endif
+
+extern uint32_t (*cal_quotient_remainder)(const uint64_t, const uint64_t, const uint32_t,
+                                          uint32_t *);
+
+void empty_function(void);
+bool true_function(void);
+void *void_ptr_function(void);
+
+extern void vAssertHandler(const char *pFuncName, uint32_t funcLine);
+
+uint32_t reverse_bits_in_word(uint32_t num);
+bool is_overlapped(uint32_t range0[2], uint32_t range1[2]);
+
+uint64_t clk_cnt_diff(uint64_t clk_begin, uint64_t clk_end, uint64_t bit_mask);
+bool clk_cnt_cmp(uint64_t clk_begin, uint64_t clk_end_1, uint64_t clk_end_2, uint64_t bit_mask);
+uint32_t us_to_rtc_clk(uint32_t us, RoundType round_type);
+uint32_t rtc_clk_to_us(uint32_t rtc_clk, RoundType round_type);
+void dwt_cyccnt_init(void);
+uint32_t read_cpu_counter(void);
+
+SYSTICK_CLK_SRC_TYPE get_sys_tick_clk_type(void);
+
+uint32_t get_SystemCoreClock(void);
+
+extern uint32_t (*get_stack_en)(void);
+
+void update_cpu_tick_to_us(uint32_t cpu_freq);
+
+#define IS_USE_VHCI (get_stack_en())
+
+/** End of PLATFORM_UTILS_Exported_Functions
+  * @}
+  */
+
+/** End of PLATFORM_UTILS
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/bee/util/inc/rtl87x2g/utils_nsc.h b/bee/util/inc/rtl87x2g/utils_nsc.h
new file mode 100644
index 00000000..90a6412c
--- /dev/null
+++ b/bee/util/inc/rtl87x2g/utils_nsc.h
@@ -0,0 +1,98 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _UTILS_NSC_H_
+#define _UTILS_NSC_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*============================================================================*
+ *                               Header Files
+*============================================================================*/
+#include <stdbool.h>
+#include <stdint.h>
+#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#include "cmsis_armclang.h"
+#endif
+
+#define PLATFORM_STATIC_ASSERT(condition, identifier) typedef char PALStaticAssert_##identifier[(condition) ? 1 : -1]
+
+#define DIVIDE_AND_ROUND(dividend, divisor)     (((dividend) + ((divisor) >> 1)) / (divisor))
+
+#define DIVIDE_AND_ROUNDUP(dividend, divisor)   (((dividend) + ((divisor) - 1)) / (divisor))
+
+/*============================================================================*
+ *                              Variables
+ *============================================================================*/
+typedef enum
+{
+    PERION_000_NS     = 0x01,
+    PERION_004_NS     = 0x02,
+    PERION_008_NS     = 0x04,
+    PERION_00C_NS     = 0x08,
+    PERION_010_NS     = 0x10,
+    PERION_014_NS     = 0x20,
+    PERION_018_NS     = 0x40,
+    PERION_020_NS     = 0x80,
+    PERION_024_NS     = 0x100,
+    PERION_028_NS     = 0x200,
+    PERION_02C_NS     = 0x400,
+    PERION_SPIC0_NS   = 0x800,
+    PERION_SPIC1_NS   = 0x1000,
+    PERION_SPIC2_NS   = 0x2000,
+    PERION_RSVD       = 0x4000,
+    PERION_400_NS     = 0x8000,
+    PERION_ALL_NS     = 0xFFFF,
+} PERION_NS_ACCESS_PERMISSION;
+
+
+/*============================================================================*
+ *                              Functions
+ *============================================================================*/
+/** @defgroup UTILS_Exported_Functions Platform Utils Exported Functions
+    * @brief
+    * @{
+    */
+
+void deinit_swd_pinmux(void);
+
+void setup_non_secure_nvic(void);
+
+bool get_disable_hci_set_uart_baudrate(void);
+bool get_disable_hci_rf_dbg_func(void);
+bool get_disable_hci_read_chip_info(void);
+bool get_disable_hci_bt_extension(void);
+bool get_airplane_mode(void);
+void set_airplane_mode(bool airplane_mode);
+bool get_disable_hci_flash_access(void);
+bool get_disable_hci_system_access(void);
+bool get_disable_hci_efuse_access(void);
+bool get_timer_clk_src_from_40m(void);
+bool get_disable_hci_wifi_coexist_func(void);
+bool get_disable_hci_bt_test(void);
+uint8_t get_default_hci_rx_pin(void);
+uint8_t get_default_hci_tx_pin(void);
+uint8_t get_stack_patch_valid(void);
+uint32_t get_stack_patch_rom_header_addr(void);
+void update_cpu_tick_to_us_nsc(uint32_t cpu_freq);
+void enable_nonsecure_access_peri_on_register(PERION_NS_ACCESS_PERMISSION perm_bitmap, bool enable);
+uint32_t get_occd_addr(void);
+uint32_t get_occd_size(void);
+uint32_t get_extra_occd_addr(void);
+uint32_t get_extra_occd_size(void);
+
+/** @} */ /* End of group UTILS_Exported_Functions */
+
+
+/** @} */ /* End of group UTILS */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/bee/util/inc/rtl87x2j/utils.h b/bee/util/inc/rtl87x2j/utils.h
new file mode 100644
index 00000000..d6bff0f7
--- /dev/null
+++ b/bee/util/inc/rtl87x2j/utils.h
@@ -0,0 +1,443 @@
+/*
+ * Copyright (c) 2026, Realtek Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _UTILS_H_
+#define _UTILS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdlib.h>
+#include <stdbool.h>
+#include <stdint.h>
+
+/*============================================================================*
+ *                               Header Files
+*============================================================================*/
+/** @defgroup  PLATFORM_UTILS Platform Utilities
+    * @brief Utility helper functions
+    * @{
+    */
+#define RTK_STATIC_ASSERT_MSG(MSG, COUNTER) RTK_STATIC_ASSERT_MSG_(MSG, COUNTER)
+#define RTK_STATIC_ASSERT_MSG_(MSG, COUNTER) static_assertion_##MSG##COUNTER
+#define RTK_STATIC_ASSERT(COND,MSG) typedef char RTK_STATIC_ASSERT_MSG(MSG, __COUNTER__)[(COND)?1:-1];
+
+#define ASSERT_CONCAT_(a, b) a##b
+#define ASSERT_CONCAT(a, b) ASSERT_CONCAT_(a, b)
+#define STATIC_ASSERT(e, m) \
+    enum { ASSERT_CONCAT(static_assert_, __COUNTER__) = 1/(!!(e)) }
+
+#define    SIZE_OF_TYPE_EQUAL_TO(type, size, msg) \
+    RTK_STATIC_ASSERT(sizeof(type) == size, msg)
+
+#define BUILD_BUG_ON_ZERO(e)  (sizeof(struct { int _; int:-!!(e); }) - sizeof(struct { int _; }))
+#ifndef SAME_TYPE
+#define SAME_TYPE(a, b)  __builtin_types_compatible_p(typeof(a), typeof(b))
+#endif
+#define MUST_BE_ARRAY(a)  BUILD_BUG_ON_ZERO(SAME_TYPE((a), &(*a)))
+
+#ifndef ARRAY_SIZE
+
+#ifdef __ARMCC_VERSION
+#define ARRAY_SIZE(a) (sizeof(a) / sizeof(*a))
+#else
+#ifdef __GNUC__
+#define ARRAY_SIZE(a) ((sizeof(a) / sizeof(*a)) + MUST_BE_ARRAY(a))
+#endif
+#endif
+
+#endif
+
+#define hex2char(val) ("0123456789abcdef"[(val) & 0xf])
+#define count_1bits(x) (uint8_t)__builtin_popcount(x)
+#define count_0bits(x) (32 - count_1bits(x))
+#define check_inverse(data, inverse_data, mask) ((data ^ inverse_data) == mask)
+#define SET_BIT(val, mask)          ((val) |=  (mask))
+#define CLR_BIT(val, mask)          ((val)  &= ~(mask))
+
+#ifndef MAX
+#define MAX(a, b) (((a) > (b)) ? (a) : (b))
+#endif
+
+#ifndef MIN
+#define MIN(a, b) (((a) < (b)) ? (a) : (b))
+#endif
+
+#ifndef CLAMP
+/**
+ * @brief Clamp a value to a given range.
+ *
+ * @note Arguments are evaluated multiple times. Use Z_CLAMP for a GCC-only,
+ * single evaluation version.
+ *
+ * @param val Value to be clamped.
+ * @param low Lowest allowed value (inclusive).
+ * @param high Highest allowed value (inclusive).
+ *
+ * @returns Clamped value.
+ */
+#define CLAMP(val, low, high) (((val) <= (low)) ? (low) : MIN(val, high))
+#endif
+
+#ifndef  CONTAINER_OF
+#define CONTAINER_OF(ptr, type, member) \
+    ((type *)((uintptr_t)ptr - offsetof(type, member)))
+#endif
+
+/** Calculate integer bit count of b'1 */
+#define INT_BIT_COUNT(integer, count)   {               \
+        count = 0;                                      \
+        while (integer)                                 \
+        {                                               \
+            count++;                                    \
+            integer &= integer - 1;                     \
+        }                                               \
+    }
+
+/** Stream skip len */
+#define STREAM_SKIP_LEN(s, len)     {                   \
+        s += len;                                       \
+    }
+
+/** Stream to array */
+#define STREAM_TO_ARRAY(a, s, len)  {                   \
+        uint32_t ii;                                    \
+        for (ii = 0; ii < len; ii++)                    \
+        {                                               \
+            *((uint8_t *)(a) + ii) = *s++;              \
+        }                                               \
+    }
+
+/** Array to stream */
+#define ARRAY_TO_STREAM(s, a, len)  {                   \
+        uint32_t ii;                                    \
+        for (ii = 0; ii < len; ii++)                    \
+        {                                               \
+            *s++ = *((uint8_t *)(a) + ii);              \
+        }                                               \
+    }
+
+/** Little Endian stream to uint8 */
+#define LE_STREAM_TO_UINT8(u8, s)   {                   \
+        u8  = (uint8_t)(*s);                            \
+        s  += 1;                                        \
+    }
+
+/** Little Endian stream to uint16 */
+#define LE_STREAM_TO_UINT16(u16, s) {                   \
+        u16  = ((uint16_t)(*(s + 0)) << 0) +            \
+               ((uint16_t)(*(s + 1)) << 8);             \
+        s   += 2;                                       \
+    }
+
+/** Little Endian stream to uint24 */
+#define LE_STREAM_TO_UINT24(u24, s) {                   \
+        u24  = ((uint32_t)(*(s + 0)) <<  0) +           \
+               ((uint32_t)(*(s + 1)) <<  8) +           \
+               ((uint32_t)(*(s + 2)) << 16);            \
+        s   += 3;                                       \
+    }
+
+/** Little Endian stream to uint32 */
+#define LE_STREAM_TO_UINT32(u32, s) {                   \
+        u32  = ((uint32_t)(*(s + 0)) <<  0) +           \
+               ((uint32_t)(*(s + 1)) <<  8) +           \
+               ((uint32_t)(*(s + 2)) << 16) +           \
+               ((uint32_t)(*(s + 3)) << 24);            \
+        s   += 4;                                       \
+    }
+
+/** Little Endian uint8 to stream */
+#define LE_UINT8_TO_STREAM(s, u8)   {                   \
+        *s++ = (uint8_t)(u8);                           \
+    }
+
+/** Little Endian uint16 to stream */
+#define LE_UINT16_TO_STREAM(s, u16) {                   \
+        *s++ = (uint8_t)((u16) >> 0);                   \
+        *s++ = (uint8_t)((u16) >> 8);                   \
+    }
+
+/** Little Endian uint24 to stream */
+#define LE_UINT24_TO_STREAM(s, u24) {                   \
+        *s++ = (uint8_t)((u24) >>  0);                  \
+        *s++ = (uint8_t)((u24) >>  8);                  \
+        *s++ = (uint8_t)((u24) >> 16);                  \
+    }
+
+/** Little Endian uint32 to stream */
+#define LE_UINT32_TO_STREAM(s, u32) {                   \
+        *s++ = (uint8_t)((u32) >>  0);                  \
+        *s++ = (uint8_t)((u32) >>  8);                  \
+        *s++ = (uint8_t)((u32) >> 16);                  \
+        *s++ = (uint8_t)((u32) >> 24);                  \
+    }
+
+/** Little Endian array to uint8 */
+#define LE_ARRAY_TO_UINT8(u8, a)    {                   \
+        u8  = (uint8_t)(*(a + 0));                      \
+    }
+
+/** Little Endian array to uint16 */
+#define LE_ARRAY_TO_UINT16(u16, a)  {                   \
+        u16 = ((uint16_t)(*(a + 0)) << 0) +             \
+              ((uint16_t)(*(a + 1)) << 8);              \
+    }
+
+/** Little Endian array to uint24 */
+#define LE_ARRAY_TO_UINT24(u24, a)  {                   \
+        u24 = ((uint32_t)(*(a + 0)) <<  0) +            \
+              ((uint32_t)(*(a + 1)) <<  8) +            \
+              ((uint32_t)(*(a + 2)) << 16);             \
+    }
+
+/** Little Endian array to uint32 */
+#define LE_ARRAY_TO_UINT32(u32, a) {                    \
+        u32 = ((uint32_t)(*(a + 0)) <<  0) +            \
+              ((uint32_t)(*(a + 1)) <<  8) +            \
+              ((uint32_t)(*(a + 2)) << 16) +            \
+              ((uint32_t)(*(a + 3)) << 24);             \
+    }
+
+/** Little Endian uint8 to array */
+#define LE_UINT8_TO_ARRAY(a, u8)    {                   \
+        *((uint8_t *)(a) + 0) = (uint8_t)(u8);          \
+    }
+
+/** Little Endian uint16 to array */
+#define LE_UINT16_TO_ARRAY(a, u16)  {                   \
+        *((uint8_t *)(a) + 0) = (uint8_t)((u16) >> 0);  \
+        *((uint8_t *)(a) + 1) = (uint8_t)((u16) >> 8);  \
+    }
+
+/** Little Endian uint24 to array */
+#define LE_UINT24_TO_ARRAY(a, u24) {                    \
+        *((uint8_t *)(a) + 0) = (uint8_t)((u24) >>  0); \
+        *((uint8_t *)(a) + 1) = (uint8_t)((u24) >>  8); \
+        *((uint8_t *)(a) + 2) = (uint8_t)((u24) >> 16); \
+    }
+
+/** Little Endian uint32 to array */
+#define LE_UINT32_TO_ARRAY(a, u32) {                    \
+        *((uint8_t *)(a) + 0) = (uint8_t)((u32) >>  0); \
+        *((uint8_t *)(a) + 1) = (uint8_t)((u32) >>  8); \
+        *((uint8_t *)(a) + 2) = (uint8_t)((u32) >> 16); \
+        *((uint8_t *)(a) + 3) = (uint8_t)((u32) >> 24); \
+    }
+
+/** Big Endian stream to uint8 */
+#define BE_STREAM_TO_UINT8(u8, s)   {                   \
+        u8   = (uint8_t)(*(s + 0));                     \
+        s   += 1;                                       \
+    }
+
+/** Big Endian stream to uint16 */
+#define BE_STREAM_TO_UINT16(u16, s) {                   \
+        u16  = ((uint16_t)(*(s + 0)) << 8) +            \
+               ((uint16_t)(*(s + 1)) << 0);             \
+        s   += 2;                                       \
+    }
+
+/** Big Endian stream to uint24 */
+#define BE_STREAM_TO_UINT24(u24, s) {                   \
+        u24  = ((uint32_t)(*(s + 0)) << 16) +           \
+               ((uint32_t)(*(s + 1)) <<  8) +           \
+               ((uint32_t)(*(s + 2)) <<  0);            \
+        s   += 3;                                       \
+    }
+
+/** Big Endian stream to uint32 */
+#define BE_STREAM_TO_UINT32(u32, s) {                   \
+        u32  = ((uint32_t)(*(s + 0)) << 24) +           \
+               ((uint32_t)(*(s + 1)) << 16) +           \
+               ((uint32_t)(*(s + 2)) <<  8) +           \
+               ((uint32_t)(*(s + 3)) <<  0);            \
+        s   += 4;                                       \
+    }
+
+/** Big Endian uint8 to stream */
+#define BE_UINT8_TO_STREAM(s, u8)   {                   \
+        *s++ = (uint8_t)(u8);                           \
+    }
+
+/** Big Endian uint16 to stream */
+#define BE_UINT16_TO_STREAM(s, u16) {                   \
+        *s++ = (uint8_t)((u16) >> 8);                   \
+        *s++ = (uint8_t)((u16) >> 0);                   \
+    }
+
+/** Big Endian uint24 to stream */
+#define BE_UINT24_TO_STREAM(s, u24) {                   \
+        *s++ = (uint8_t)((u24) >> 16);                  \
+        *s++ = (uint8_t)((u24) >>  8);                  \
+        *s++ = (uint8_t)((u24) >>  0);                  \
+    }
+
+/** Big Endian uint32 to stream */
+#define BE_UINT32_TO_STREAM(s, u32) {                   \
+        *s++ = (uint8_t)((u32) >> 24);                  \
+        *s++ = (uint8_t)((u32) >> 16);                  \
+        *s++ = (uint8_t)((u32) >>  8);                  \
+        *s++ = (uint8_t)((u32) >>  0);                  \
+    }
+
+/** Big Endian array to uint8 */
+#define BE_ARRAY_TO_UINT8(u8, a)    {                   \
+        u8  = (uint8_t)(*(a + 0));                      \
+    }
+
+/** Big Endian array to uint16 */
+#define BE_ARRAY_TO_UINT16(u16, a)  {                   \
+        u16 = ((uint16_t)(*(a + 0)) << 8) +             \
+              ((uint16_t)(*(a + 1)) << 0);              \
+    }
+
+/** Big Endian array to uint24 */
+#define BE_ARRAY_TO_UINT24(u24, a)  {                   \
+        u24 = ((uint32_t)(*(a + 0)) << 16) +            \
+              ((uint32_t)(*(a + 1)) <<  8) +            \
+              ((uint32_t)(*(a + 2)) <<  0);             \
+    }
+
+/** Big Endian array to uint32 */
+#define BE_ARRAY_TO_UINT32(u32, a)  {                   \
+        u32 = ((uint32_t)(*(a + 0)) << 24) +            \
+              ((uint32_t)(*(a + 1)) << 16) +            \
+              ((uint32_t)(*(a + 2)) <<  8) +            \
+              ((uint32_t)(*(a + 3)) <<  0);             \
+    }
+
+/** Big Endian uint8 to array */
+#define BE_UINT8_TO_ARRAY(a, u8)    {                   \
+        *((uint8_t *)(a) + 0) = (uint8_t)(u8);          \
+    }
+
+/** Big Endian uint16 to array */
+#define BE_UINT16_TO_ARRAY(a, u16)  {                   \
+        *((uint8_t *)(a) + 0) = (uint8_t)((u16) >> 8);  \
+        *((uint8_t *)(a) + 1) = (uint8_t)((u16) >> 0);  \
+    }
+
+/** Big Endian uint24 to array */
+#define BE_UINT24_TO_ARRAY(a, u24)  {                   \
+        *((uint8_t *)(a) + 0) = (uint8_t)((u24) >> 16); \
+        *((uint8_t *)(a) + 1) = (uint8_t)((u24) >>  8); \
+        *((uint8_t *)(a) + 2) = (uint8_t)((u24) >>  0); \
+    }
+
+/** Big Endian uint32 to array */
+#define BE_UINT32_TO_ARRAY(a, u32)  {                   \
+        *((uint8_t *)(a) + 0) = (uint8_t)((u32) >> 24); \
+        *((uint8_t *)(a) + 1) = (uint8_t)((u32) >> 16); \
+        *((uint8_t *)(a) + 2) = (uint8_t)((u32) >>  8); \
+        *((uint8_t *)(a) + 3) = (uint8_t)((u32) >>  0); \
+    }
+
+#define DIVIDE_AND_ROUND(dividend, divisor)     (((dividend) + ((divisor) >> 1)) / (divisor))
+
+#define DIVIDE_AND_ROUNDUP(dividend, divisor)   (((dividend) + ((divisor) - 1)) / (divisor))
+
+#define CLOCK_COUNT_DIFF(clk_begin, clk_end, bit_mask) (((((uint64_t)clk_end & ((uint64_t)bit_mask - 1)) | (uint64_t)bit_mask) - ((uint64_t)clk_begin & ((uint64_t)bit_mask - 1))) & ((uint64_t)bit_mask - 1))
+
+#define CPU_CNT_BIT_NUM             BIT64(32)
+
+/*============================================================================*
+ *                              Types
+ *============================================================================*/
+typedef enum
+{
+    ROUND                   = 0,
+    ROUNDUP                 = 1,
+    ROUNDDOWN               = 2,
+} RoundType;
+
+typedef struct _RTLNUM_Type
+{
+    uint16_t rtl_num1;
+    uint16_t rtl_num2;
+} RTLNUM_Type;
+
+/*============================================================================*
+ *                              Variables
+ *============================================================================*/
+
+
+
+/*============================================================================*
+ *                              Functions
+ *============================================================================*/
+/** @defgroup PLATFORM_UTILS_Exported_Functions Platform Utils Exported Functions
+    * @brief
+    * @{
+    */
+
+/**
+ * @brief Busy delay for specified micro second
+ * @param t   to specify t micro seconds to delay
+ * @return none
+ */
+void platform_delay_ms(uint32_t t);
+
+/**
+ * @brief Busy delay for specified millisecond
+ * @param t   to specify t milliseconds to delay
+ * @return none
+ */
+void platform_delay_us(uint32_t t);
+
+void update_cpu_tick_to_us(uint32_t cpu_freq);
+
+#if (CONFIG_DWT_PRESENT == 1)
+void dwt_cyccnt_init(void);
+#endif
+uint32_t read_cpu_counter(void);
+
+void empty_function(void);
+bool true_function(void);
+void *void_ptr_function(void);
+
+uint16_t count_zeros(uint8_t *data, uint8_t byte_size);
+bool check_zero_count(uint8_t *data, uint8_t byte_size, uint16_t num_of_zeros);
+
+bool data_cmp(const void *d1, const void *d2, uint32_t length);
+bool is_overlapped(uint32_t range0[2], uint32_t range1[2]);
+void swap_buf(const uint8_t *src, uint8_t *dst, uint16_t len);
+
+uint32_t cal_quotient_remainder(const uint64_t divisor_upper,
+                                const uint64_t divisor_lower,
+                                const uint32_t dividend, uint32_t *remainder);
+uint32_t reverse_bits_in_word(uint32_t num);
+uint64_t clk_cnt_diff(uint64_t clk_begin, uint64_t clk_end, uint64_t bit_mask);
+int32_t saturate_by_boundary(int32_t value, int32_t upperbound, int32_t lowerbound);
+
+uint32_t us_to_tick_32000(uint32_t us, RoundType round_type);
+uint32_t tick_32000_to_us(uint32_t tick, RoundType round_type);
+uint32_t us_to_tick_32768(uint32_t us, RoundType round_type);
+uint32_t tick_32768_to_us(uint32_t tick, RoundType round_type);
+
+#define us_to_rtc_clk(a, b)  us_to_tick_32000(a,b)    //TODO
+#define rtc_clk_to_us(a, b)  tick_32000_to_us(a,b)    //TODO
+
+void dump_raw_mem(uint32_t *start_addr, uint32_t size);
+
+RTLNUM_Type get_soc_rtl_num(void);
+bool check_code_is_xip(uint32_t address);
+
+extern uint32_t (*lowerstack_SystemCall_in_platform)(uint32_t opcode, uint32_t param,
+                                                     uint32_t param1,
+                                                     uint32_t param2);  //TODO: only used for lowerstack
+
+/** @} */ /* End of group PLATFORM_UTILS_Exported_Functions */
+
+
+/** @} */ /* End of group PLATFORM_UTILS */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/zephyr/blobs/bee/rtl87x2j/bin/OTAHeader_Bank0_1.0.0.1-4d66efc3f9a32560260733ef737839b8.bin b/zephyr/blobs/bee/rtl87x2j/bin/OTAHeader_Bank0_1.0.0.1-4d66efc3f9a32560260733ef737839b8.bin
new file mode 100644
index 00000000..07122e97
Binary files /dev/null and b/zephyr/blobs/bee/rtl87x2j/bin/OTAHeader_Bank0_1.0.0.1-4d66efc3f9a32560260733ef737839b8.bin differ
diff --git a/zephyr/blobs/bee/rtl87x2j/bin/bootloader_MP_sdk_0.0.0.3_aca08d52-5b63d3ad719587339914e4cc8562921a.bin b/zephyr/blobs/bee/rtl87x2j/bin/bootloader_MP_sdk_0.0.0.3_aca08d52-5b63d3ad719587339914e4cc8562921a.bin
new file mode 100644
index 00000000..fc43d7f5
Binary files /dev/null and b/zephyr/blobs/bee/rtl87x2j/bin/bootloader_MP_sdk_0.0.0.3_aca08d52-5b63d3ad719587339914e4cc8562921a.bin differ
diff --git a/zephyr/blobs/bee/rtl87x2j/bin/flash map.ini b/zephyr/blobs/bee/rtl87x2j/bin/flash map.ini
new file mode 100644
index 00000000..6064f743
--- /dev/null
+++ b/zephyr/blobs/bee/rtl87x2j/bin/flash map.ini	
@@ -0,0 +1,71 @@
+[Property]
+IC_TYPE=RTL87x2J
+MMU=Enable
+FLASH_SIZE=976
+OTA_SWITCH=Disable
+IMG_HDR_SIZE=1024
+[OTAHeader]
+OTA_BIN_VER1=1
+OTA_BIN_VER2=0
+OTA_BIN_VER3=0
+OTA_BIN_VER4=1
+[HighLevel]
+BOOT_PATCH_ADDR=0x02000000
+BOOT_PATCH_SIZE=0x00012C00
+OTA_BANK0_ADDR=0x02012C00
+OTA_BANK0_SIZE=0x000A1400
+OTA_BANK1_ADDR=0x03000000
+OTA_BANK1_SIZE=0x00000000
+OTA_TMP_ADDR=0x03000000
+OTA_TMP_SIZE=0x00001000
+BKP_DATA1_ADDR=0x03001000
+BKP_DATA1_SIZE=0x00000000
+BKP_DATA2_ADDR=0x03001000
+BKP_DATA2_SIZE=0x00000000
+[OTABank]
+BANK0_OTA_HEADER_ADDR=0x02012C00
+BANK0_OTA_HEADER_SIZE=0x00000400
+BANK0_SYS_PATCH_ADDR=0x02013000
+BANK0_SYS_PATCH_SIZE=0x00006000
+BANK0_SYS_PATCH_EXE_ADDR=0x02C00000
+BANK0_BT_CONTROLLER_ADDR=0x02019000
+BANK0_BT_CONTROLLER_SIZE=0x00036400
+BANK0_BT_CONTROLLER_EXE_ADDR=0x02C40000
+BANK0_BT_HOST_ADDR=0x0204F400
+BANK0_BT_HOST_SIZE=0x00000000
+BANK0_APP_ADDR=0x0204F400
+BANK0_APP_SIZE=0x00064C00
+BANK0_APP_DATA1_ADDR=0x020B4000
+BANK0_APP_DATA1_SIZE=0x00000000
+BANK0_APP_DATA2_ADDR=0x020B4000
+BANK0_APP_DATA2_SIZE=0x00000000
+BANK0_APP_DATA3_ADDR=0x020B4000
+BANK0_APP_DATA3_SIZE=0x00000000
+BANK0_APP_DATA4_ADDR=0x020B4000
+BANK0_APP_DATA4_SIZE=0x00000000
+BANK0_APP_DATA5_ADDR=0x020B4000
+BANK0_APP_DATA5_SIZE=0x00000000
+BANK0_APP_CFG_DATA_ADDR=0x020B4000
+BANK0_APP_CFG_DATA_SIZE=0x00000000
+BANK1_OTA_HEADER_ADDR=0x00000000
+BANK1_OTA_HEADER_SIZE=0x00000000
+BANK1_SYS_PATCH_ADDR=0x00000000
+BANK1_SYS_PATCH_SIZE=0x00000000
+BANK1_BT_CONTROLLER_ADDR=0x00000000
+BANK1_BT_CONTROLLER_SIZE=0x00000000
+BANK1_BT_HOST_ADDR=0x00000000
+BANK1_BT_HOST_SIZE=0x00000000
+BANK1_APP_ADDR=0x00000000
+BANK1_APP_SIZE=0x00000000
+BANK1_APP_DATA1_ADDR=0x00000000
+BANK1_APP_DATA1_SIZE=0x00000000
+BANK1_APP_DATA2_ADDR=0x00000000
+BANK1_APP_DATA2_SIZE=0x00000000
+BANK1_APP_DATA3_ADDR=0x00000000
+BANK1_APP_DATA3_SIZE=0x00000000
+BANK1_APP_DATA4_ADDR=0x00000000
+BANK1_APP_DATA4_SIZE=0x00000000
+BANK1_APP_DATA5_ADDR=0x00000000
+BANK1_APP_DATA5_SIZE=0x00000000
+BANK1_APP_CFG_DATA_ADDR=0x00000000
+BANK1_APP_CFG_DATA_SIZE=0x00000000
diff --git a/zephyr/blobs/bee/rtl87x2j/bin/flash_map.h b/zephyr/blobs/bee/rtl87x2j/bin/flash_map.h
new file mode 100644
index 00000000..0c6e3ec1
--- /dev/null
+++ b/zephyr/blobs/bee/rtl87x2j/bin/flash_map.h
@@ -0,0 +1,131 @@
+/**
+*****************************************************************************************
+*     Copyright(c) 2025, Realtek Semiconductor Corporation. All rights reserved.
+*****************************************************************************************
+* @file    flash_map.h
+* @brief   Flash Layout Configuration, and flash layout must be changed with config file!
+* @note    flash_map.h must be generated by FlashMapGenerateTool!
+* *************************************************************************************
+*/
+
+#ifndef _FLASH_MAP_H_
+#define _FLASH_MAP_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*============================================================================*
+*                        Flash Layout
+*============================================================================*/
+/*  Flash total size                                976KB
+MMU enable
+example:
+	1) Boot Patch:                                       75K (0x02000000)
+	2) OTA Bank0:                                       645K (0x02012C00)
+		a) OTA Header                    1K (0x02012C00)
+		b) Sys Patch                    24K (0x02013000)
+		c) BT Controller               217K (0x02019000)
+		d) BT Host                       0K (0x0204F400)
+		e) APP code                    403K (0x0204F400)
+		f) APP data1                     0K (0x020B4000)
+		g) APP data2                     0K (0x020B4000)
+		h) APP data3                     0K (0x020B4000)
+		i) APP data4                     0K (0x020B4000)
+		j) APP data5                     0K (0x020B4000)
+		k) APP config data               0K (0x020B4000)
+	3) OTA Bank1:                                         0K (0x03000000)
+		a) OTA Header                    0K (0x00000000)
+		b) Sys Patch                     0K (0x00000000)
+		c) BT Controller                 0K (0x00000000)
+		d) BT Host                       0K (0x00000000)
+		e) APP code                      0K (0x00000000)
+		f) APP data1                     0K (0x00000000)
+		g) APP data2                     0K (0x00000000)
+		h) APP data3                     0K (0x00000000)
+		i) APP data4                     0K (0x00000000)
+		j) APP data5                     0K (0x00000000)
+		k) APP config data               0K (0x00000000)
+	4) OTA Tmp:                                           4K (0x03000000)
+	5) APP Defined Section1:                              0K (0x03001000)
+	6) APP Defined Section2:                              0K (0x03001000)
+*/
+
+/*============================================================================*
+*            Flash Layout Configuration (Generated by FlashMapGenerateTool)
+*============================================================================*/
+
+#define MMU_ENABLE                          1  
+#define FLASH_START_ADDR                    0x02000000  //Fixed
+#define FLASH_MAX_SIZE                      0x000F4000  //976K Bytes
+
+/* ========== High Level Flash Layout Configuration ========== */
+#define BOOT_PATCH_ADDR                     0x02000000
+#define BOOT_PATCH_SIZE                     0x00012C00  //75K Bytes
+#define OTA_BANK0_ADDR                      0x02012C00
+#define OTA_BANK0_SIZE                      0x000A1400  //645K Bytes
+#define OTA_BANK1_ADDR                      0x03000000
+#define OTA_BANK1_SIZE                      0x00000000  //0K Bytes
+#define OTA_TMP_ADDR                        0x03000000
+#define OTA_TMP_SIZE                        0x00001000  //4K Bytes
+#define BKP_DATA1_ADDR                      0x03001000
+#define BKP_DATA1_SIZE                      0x00000000  //0K Bytes
+#define BKP_DATA2_ADDR                      0x03001000
+#define BKP_DATA2_SIZE                      0x00000000  //0K Bytes
+
+/* ========== OTA Bank0 Flash Layout Configuration ========== */
+#define BANK0_OTA_HEADER_ADDR               0x02012C00
+#define BANK0_OTA_HEADER_SIZE               0x00000400  //1K Bytes
+#define BANK0_SYS_PATCH_ADDR                0x02013000
+#define BANK0_SYS_PATCH_EXE_ADDR            0x02C00000                          
+#define BANK0_SYS_PATCH_SIZE                0x00006000  //24K Bytes
+#define BANK0_BT_CONTROLLER_ADDR            0x02019000
+#define BANK0_BT_CONTROLLER_EXE_ADDR        0x02C40000                          
+#define BANK0_BT_CONTROLLER_SIZE            0x00036400  //217K Bytes
+#define BANK0_BT_HOST_ADDR                  0x0204F400
+#define BANK0_BT_HOST_SIZE                  0x00000000  //0K Bytes
+#define BANK0_APP_ADDR                      0x0204F400
+#define BANK0_APP_SIZE                      0x00064C00  //403K Bytes
+#define BANK0_APP_DATA1_ADDR                0x020B4000
+#define BANK0_APP_DATA1_SIZE                0x00000000  //0K Bytes
+#define BANK0_APP_DATA2_ADDR                0x020B4000
+#define BANK0_APP_DATA2_SIZE                0x00000000  //0K Bytes
+#define BANK0_APP_DATA3_ADDR                0x020B4000
+#define BANK0_APP_DATA3_SIZE                0x00000000  //0K Bytes
+#define BANK0_APP_DATA4_ADDR                0x020B4000
+#define BANK0_APP_DATA4_SIZE                0x00000000  //0K Bytes
+#define BANK0_APP_DATA5_ADDR                0x020B4000
+#define BANK0_APP_DATA5_SIZE                0x00000000  //0K Bytes
+#define BANK0_APP_CFG_DATA_ADDR             0x020B4000
+#define BANK0_APP_CFG_DATA_SIZE             0x00000000  //0K Bytes
+
+/* ========== OTA Bank1 Flash Layout Configuration ========== */
+#define BANK1_OTA_HEADER_ADDR               0x00000000
+#define BANK1_OTA_HEADER_SIZE               0x00000000  //0K Bytes
+#define BANK1_SYS_PATCH_ADDR                0x00000000
+#define BANK1_SYS_PATCH_SIZE                0x00000000  //0K Bytes
+#define BANK1_BT_CONTROLLER_ADDR            0x00000000
+#define BANK1_BT_CONTROLLER_SIZE            0x00000000  //0K Bytes
+#define BANK1_BT_HOST_ADDR                  0x00000000
+#define BANK1_BT_HOST_SIZE                  0x00000000  //0K Bytes
+#define BANK1_APP_ADDR                      0x00000000
+#define BANK1_APP_SIZE                      0x00000000  //0K Bytes
+#define BANK1_APP_DATA1_ADDR                0x00000000
+#define BANK1_APP_DATA1_SIZE                0x00000000  //0K Bytes
+#define BANK1_APP_DATA2_ADDR                0x00000000
+#define BANK1_APP_DATA2_SIZE                0x00000000  //0K Bytes
+#define BANK1_APP_DATA3_ADDR                0x00000000
+#define BANK1_APP_DATA3_SIZE                0x00000000  //0K Bytes
+#define BANK1_APP_DATA4_ADDR                0x00000000
+#define BANK1_APP_DATA4_SIZE                0x00000000  //0K Bytes
+#define BANK1_APP_DATA5_ADDR                0x00000000
+#define BANK1_APP_DATA5_SIZE                0x00000000  //0K Bytes
+#define BANK1_APP_CFG_DATA_ADDR             0x00000000
+#define BANK1_APP_CFG_DATA_SIZE             0x00000000  //0K Bytes
+
+
+#ifdef __cplusplus
+}
+#endif
+/** @} */ /* _FLASH_MAP_H_ */
+#endif
diff --git a/zephyr/blobs/bee/rtl87x2j/bin/lowerstack_MP_100_3.0.0.111_831ea602-129ec9e990d94682d92c3f24f75d6333.bin b/zephyr/blobs/bee/rtl87x2j/bin/lowerstack_MP_100_3.0.0.111_831ea602-129ec9e990d94682d92c3f24f75d6333.bin
new file mode 100644
index 00000000..faf1d0f2
Binary files /dev/null and b/zephyr/blobs/bee/rtl87x2j/bin/lowerstack_MP_100_3.0.0.111_831ea602-129ec9e990d94682d92c3f24f75d6333.bin differ
diff --git a/zephyr/blobs/bee/rtl87x2j/bin/sys_config_MP-024219133a8640b23830162e320f49ee.bin b/zephyr/blobs/bee/rtl87x2j/bin/sys_config_MP-024219133a8640b23830162e320f49ee.bin
new file mode 100644
index 00000000..d650db3e
Binary files /dev/null and b/zephyr/blobs/bee/rtl87x2j/bin/sys_config_MP-024219133a8640b23830162e320f49ee.bin differ
diff --git a/zephyr/blobs/bee/rtl87x2j/bin/sys_patch_MP_sdk_0.0.0.0_16104e62-66a73929aca0d223da6cf0ef24f994fa.bin b/zephyr/blobs/bee/rtl87x2j/bin/sys_patch_MP_sdk_0.0.0.0_16104e62-66a73929aca0d223da6cf0ef24f994fa.bin
new file mode 100644
index 00000000..ddb13a10
Binary files /dev/null and b/zephyr/blobs/bee/rtl87x2j/bin/sys_patch_MP_sdk_0.0.0.0_16104e62-66a73929aca0d223da6cf0ef24f994fa.bin differ
diff --git a/zephyr/blobs/bee/rtl87x2j/bin/version b/zephyr/blobs/bee/rtl87x2j/bin/version
new file mode 100644
index 00000000..169d4ab0
--- /dev/null
+++ b/zephyr/blobs/bee/rtl87x2j/bin/version
@@ -0,0 +1,168 @@
+manifest:
+
+    remotes:
+      - name: origin
+        url-base: ssh://cn4soc.rtkbf.com:29418
+
+    defaults:
+      remote: origin
+
+    projects:
+      - name: sdk
+        repo-path: HoneyRepo/sdk
+        revision: master 537c47237020f64f6d466f08042c07526a663e52
+        path: realtek
+
+      - name: bin-rtl87x2j
+        repo-path: HoneyRepo/bin/rtl87x2j
+        revision: master
+        path: realtek/bin/rtl87x2j
+
+      - name: driver
+        repo-path: HoneyRepo/driver
+        revision: master 21b17c5363d2be394633d6a0655c7da7df1026e9
+        path: realtek/driver
+        groups:
+            - driver
+
+      - name: fmc
+        repo-path: HoneyRepo/driver/fmc
+        revision:  master 92819b9720d8adc86d311651bef208885f7f1662
+        path: realtek/driver/fmc
+        groups:
+            - fmc
+
+      - name: crypto
+        repo-path: HoneyRepo/driver/crypto
+        revision:  master 045a9393feb99bf1733680a5a7d6969899070556
+        path: realtek/driver/crypto
+        groups:
+            - crypto
+
+      - name: usb
+        repo-path: HoneyRepo/driver/usb
+        revision:  master
+        path: realtek/subsys/usb
+        groups:
+            - usb
+
+      - name: kernel
+        repo-path: HoneyRepo/kernel
+        revision:  refs/heads/bee5-v0 4fb270cb2902250c647193ff55d83bcba57b146f
+        path: realtek/kernel
+        groups:
+            - kernel
+
+      - name: soc
+        repo-path: HoneyRepo/soc
+        revision:  refs/heads/bee5 f4b790762cc8d5959f0fbca05530daab3f7f6e7a + aca08d523a6cb2117c33210593fe9becde2cafa5(zephyr support)
+        path: realtek/soc
+        groups:
+            - soc
+
+      - name: phy
+        repo-path: HoneyRepo/PHY/Dev
+        revision:  refs/tags/PHY-v2.2.0
+        path: realtek/soc/phy/common
+        groups:
+            - phy
+
+      - name: pm
+        repo-path: HoneyRepo/PM/Dev
+        revision:  refs/tags/PM-v3.0.0
+        path: realtek/soc/pm/common
+        groups:
+            - pm
+
+      - name: romdriver
+        repo-path: HoneyRepo/driver
+        revision: refs/heads/rom-driver-bee5-v0  8b165c8f59c2dcc972a8df25fedc1b5bc143da06 tag: bee5-driver-v0.0.5-bl
+        path: realtek/soc/driver
+        groups:
+            - romdriver
+
+      - name: btcontroller
+        repo-path: HoneyRepo/lowerstack
+        revision: lowerstack-dev-bee5-v0.0  831ea6025f3f0b03fed36f6fd20eeb540c134dcc
+        path: realtek/subsys/bluetooth/bt_controller/src
+        groups:
+            - btcontroller
+
+      - name: btcontrollerImage
+        repo-path: HoneyRepo/lowerimage
+        revision: master 28e2167248e1a835ba363760a3f2483a525d95b8
+        path: realtek/subsys/bluetooth/bt_controller/image
+        groups:
+            - btcontrollerImage
+
+      - name: patch
+        repo-path: HoneyRepo/syspatch
+        revision: bee5-master-v0.0 8e407b0c89cd07de31a9e4d0244eaaa54bbb257e
+        path: realtek/patch
+        groups:
+            - patch
+
+      - name: PHYpatch
+        repo-path: HoneyRepo/PHY/Patch
+        revision: phy-patch-v2.2.0 a5f8527f12298fb78e81ef14d366d7ac961f2ecc
+        path: realtek/patch/phy/common
+        groups:
+            - PHYpatch
+
+      - name: PMpatch
+        repo-path: HoneyRepo/PM/Patch
+        revision: pm-patch-v3.0.0 67aca5acf00fcd7f98336e6cbe4e8c70f7eea02f
+        path: realtek/patch/pm/common
+        groups:
+            - PMpatch
+
+      - name: lowerpatch
+        repo-path: HoneyRepo/lowerpatch
+        revision: stack-patch-v4.0
+        path: realtek/patch/bt_controller_patch
+        groups:
+            - lowerpatch
+
+      - name: bthostpatch
+        repo-path: HoneyRepo/btimprove/bt-host-patch
+        revision: master
+        path: realtek/patch/bt_host_patch
+        groups:
+            - bthostpatch
+
+      - name: jenkinsScript
+        repo-path: HoneyRepo/build
+        revision: v2
+        path: .jenkins
+        groups:
+            - jenkinsScript
+
+      - name: sample-peripheral
+        repo-path: HoneyRepo/samples/peripheral
+        revision: refs/heads/bee5
+        path: realtek/sample/peripheral
+        groups:
+            - sample-peripheral
+
+      - name: application
+        repo-path: HoneyRepo/application
+        revision: master
+        path: realtek/application
+        groups:
+            - application
+
+      - name: sample
+        repo-path: HoneyRepo/sample
+        revision: master
+        path: realtek/sample
+        groups:
+            - sample
+
+
+    self:
+        path: manifest
+        west-commands: west_commands_extention/west-commands.yml
+        userdata:
+            owner: grace_guan
+
+    group-filter: [-bthost,-protected]
diff --git a/zephyr/module.yml b/zephyr/module.yml
index 5306e1e1..f6fac40b 100644
--- a/zephyr/module.yml
+++ b/zephyr/module.yml
@@ -1,53 +1,516 @@
 name: hal_realtek
+package-managers:
+  pip:
+    requirement-files:
+      - ameba/scripts/requirements.txt
 build:
-  cmake: .
-  kconfig: Kconfig
+  cmake-ext: True
+  kconfig-ext: True
 blobs:
-  - path: amebadplus/bin/km0_image2_all.bin
-    sha256: c4b6d631d4353e45beae134f0ce2c1d2184c1ab8baba65c207e3efcdbfd66930
+
+  # ===== amebad bins =====
+
+  - path: ameba/amebad/bin/bootloader_all.bin
+    sha256: 74d86e9c144fe5018835de4dfb308c1350057d614fda016576099ea379a60d6e
+    type: img
+    version: '1.0'
+    license-path: LICENSE
+    url: https://github.com/Ameba-AIoT/nuwa_lib/raw/f60fc97640d8960d3313e5183aecf28442273c08/amebad/bin/bootloader_all.bin
+    description: "Binary images for the Ameba series bootloader"
+    doc-url: https://github.com/Ameba-AIoT/nuwa_lib
+
+  - path: ameba/amebad/bin/km0_image2_all.bin
+    sha256: 8ee218d37bda05fff30d89a72ce5b342d6ae92501985c829214be030b3039a3b
     type: img
     version: '1.0'
     license-path: LICENSE
-    url: https://github.com/Ameba-AIoT/nuwa_lib/raw/d9a23ec60d44628a27b354d89597ac58093d4a20/amebadplus/bin/km0_image2_all.bin
-    description: "Binary libraries supporting the Ameba series RF subsystems"
+    url: https://github.com/Ameba-AIoT/nuwa_lib/raw/f60fc97640d8960d3313e5183aecf28442273c08/amebad/bin/km0_image2_all.bin
+    description: "Binary libraries supporting the Ameba series subsystems"
+    doc-url: https://github.com/Ameba-AIoT/nuwa_lib
+
+  # ===== amebad libs =====
+
+  - path: ameba/amebad/lib/coex/lib_coex.a
+    sha256: e5e4bfeaf56707ea5bb1c073922849f428b306bac3dc3b2362d594962384495b
+    type: lib
+    version: '1.0'
+    license-path: LICENSE
+    url: https://github.com/Ameba-AIoT/nuwa_lib/raw/f60fc97640d8960d3313e5183aecf28442273c08/amebad/lib/coex/lib_coex.a
+    description: "Binary libraries supporting the Ameba series Wi-Fi subsystems"
+    doc-url: https://github.com/Ameba-AIoT/nuwa_lib
+
+  - path: ameba/amebad/lib/coex/lib_rtw_event.a
+    sha256: 439d7982d19a07b58d910f2a82ff071f92a12fc43544d460761ddc015c6f3614
+    type: lib
+    version: '1.0'
+    license-path: LICENSE
+    url: https://github.com/Ameba-AIoT/nuwa_lib/raw/f60fc97640d8960d3313e5183aecf28442273c08/amebad/lib/coex/lib_rtw_event.a
+    description: "Binary libraries supporting the Ameba series Wi-Fi subsystems"
+    doc-url: https://github.com/Ameba-AIoT/nuwa_lib
+
+  - path: ameba/amebad/lib/coex/lib_wifi_api.a
+    sha256: 1cfec125bcdfe9724f2cf3c0f5cb2b516f281c341c974410843e2b9991f71d43
+    type: lib
+    version: '1.0'
+    license-path: LICENSE
+    url: https://github.com/Ameba-AIoT/nuwa_lib/raw/f60fc97640d8960d3313e5183aecf28442273c08/amebad/lib/coex/lib_wifi_api.a
+    description: "Binary libraries supporting the Ameba series Wi-Fi subsystems"
+    doc-url: https://github.com/Ameba-AIoT/nuwa_lib
+
+  - path: ameba/amebad/lib/coex/lib_wifi_com_sec.a
+    sha256: 927c8fbc62e3e0405f592d153b8b6dcf8418422d180e9bfd7969bdbd42fcc4e4
+    type: lib
+    version: '1.0'
+    license-path: LICENSE
+    url: https://github.com/Ameba-AIoT/nuwa_lib/raw/f60fc97640d8960d3313e5183aecf28442273c08/amebad/lib/coex/lib_wifi_com_sec.a
+    description: "Binary libraries supporting the Ameba series Wi-Fi subsystems"
+    doc-url: https://github.com/Ameba-AIoT/nuwa_lib
+
+  - path: ameba/amebad/lib/coex/lib_wifi_rtk_app.a
+    sha256: 74c742d067c3f0b4d954102e24d6ebd099574ee4ecc9b95c1d208ebd4b5eb776
+    type: lib
+    version: '1.0'
+    license-path: LICENSE
+    url: https://github.com/Ameba-AIoT/nuwa_lib/raw/f60fc97640d8960d3313e5183aecf28442273c08/amebad/lib/coex/lib_wifi_rtk_app.a
+    description: "Binary libraries supporting the Ameba series Wi-Fi subsystems"
+    doc-url: https://github.com/Ameba-AIoT/nuwa_lib
+
+  - path: ameba/amebad/lib/coex/lib_wifi_single_core.a
+    sha256: 59b4a793a8026c868f0509d7933b5ab5d91171677ad18b344cf47f8dded0a401
+    type: lib
+    version: '1.0'
+    license-path: LICENSE
+    url: https://github.com/Ameba-AIoT/nuwa_lib/raw/f60fc97640d8960d3313e5183aecf28442273c08/amebad/lib/coex/lib_wifi_single_core.a
+    description: "Binary libraries supporting the Ameba series Wi-Fi subsystems"
     doc-url: https://github.com/Ameba-AIoT/nuwa_lib
-  - path: amebadplus/bin/km4_boot_all.bin
+
+  - path: ameba/amebad/lib/coex/lib_wpa_lite.a
+    sha256: 8c344f63e15fdd9e3c30e0a946546441aeb73784131a828ed8ef672f03b09b8e
+    type: lib
+    version: '1.0'
+    license-path: LICENSE
+    url: https://github.com/Ameba-AIoT/nuwa_lib/raw/f60fc97640d8960d3313e5183aecf28442273c08/amebad/lib/coex/lib_wpa_lite.a
+    description: "Binary libraries supporting the Ameba series Wi-Fi subsystems"
+    doc-url: https://github.com/Ameba-AIoT/nuwa_lib
+
+  - path: ameba/amebad/lib/lib_rtw_event.a
+    sha256: abac54021365c01728b1e90e1ba4f7867e4a57fe9e2dd59cd75e9acc3b5619f5
+    type: lib
+    version: '1.0'
+    license-path: LICENSE
+    url: https://github.com/Ameba-AIoT/nuwa_lib/raw/f60fc97640d8960d3313e5183aecf28442273c08/amebad/lib/lib_rtw_event.a
+    description: "Binary libraries supporting the Ameba series Wi-Fi subsystems"
+    doc-url: https://github.com/Ameba-AIoT/nuwa_lib
+
+  - path: ameba/amebad/lib/lib_wifi_api.a
+    sha256: 1cfec125bcdfe9724f2cf3c0f5cb2b516f281c341c974410843e2b9991f71d43
+    type: lib
+    version: '1.0'
+    license-path: LICENSE
+    url: https://github.com/Ameba-AIoT/nuwa_lib/raw/f60fc97640d8960d3313e5183aecf28442273c08/amebad/lib/lib_wifi_api.a
+    description: "Binary libraries supporting the Ameba series Wi-Fi subsystems"
+    doc-url: https://github.com/Ameba-AIoT/nuwa_lib
+
+  - path: ameba/amebad/lib/lib_wifi_com_sec.a
+    sha256: 927c8fbc62e3e0405f592d153b8b6dcf8418422d180e9bfd7969bdbd42fcc4e4
+    type: lib
+    version: '1.0'
+    license-path: LICENSE
+    url: https://github.com/Ameba-AIoT/nuwa_lib/raw/f60fc97640d8960d3313e5183aecf28442273c08/amebad/lib/lib_wifi_com_sec.a
+    description: "Binary libraries supporting the Ameba series Wi-Fi subsystems"
+    doc-url: https://github.com/Ameba-AIoT/nuwa_lib
+
+  - path: ameba/amebad/lib/lib_wifi_rtk_app.a
+    sha256: 74c742d067c3f0b4d954102e24d6ebd099574ee4ecc9b95c1d208ebd4b5eb776
+    type: lib
+    version: '1.0'
+    license-path: LICENSE
+    url: https://github.com/Ameba-AIoT/nuwa_lib/raw/f60fc97640d8960d3313e5183aecf28442273c08/amebad/lib/lib_wifi_rtk_app.a
+    description: "Binary libraries supporting the Ameba series Wi-Fi subsystems"
+    doc-url: https://github.com/Ameba-AIoT/nuwa_lib
+
+  - path: ameba/amebad/lib/lib_wifi_single_core.a
+    sha256: e2508f419bd7584590fd33967e203275b7c76bc4d400c3354c4b3352b8b0277c
+    type: lib
+    version: '1.0'
+    license-path: LICENSE
+    url: https://github.com/Ameba-AIoT/nuwa_lib/raw/f60fc97640d8960d3313e5183aecf28442273c08/amebad/lib/lib_wifi_single_core.a
+    description: "Binary libraries supporting the Ameba series Wi-Fi subsystems"
+    doc-url: https://github.com/Ameba-AIoT/nuwa_lib
+
+  - path: ameba/amebad/lib/lib_wpa_lite.a
+    sha256: 8c344f63e15fdd9e3c30e0a946546441aeb73784131a828ed8ef672f03b09b8e
+    type: lib
+    version: '1.0'
+    license-path: LICENSE
+    url: https://github.com/Ameba-AIoT/nuwa_lib/raw/f60fc97640d8960d3313e5183aecf28442273c08/amebad/lib/lib_wpa_lite.a
+    description: "Binary libraries supporting the Ameba series Wi-Fi subsystems"
+    doc-url: https://github.com/Ameba-AIoT/nuwa_lib
+
+  # ===== amebadplus bins =====
+
+  - path: ameba/amebadplus/bin/floader_amebadplus.bin
+    sha256: c4147f2747a1c511483454657bf93b6a95399a371781e23b2b269d337f9ed7bf
+    type: img
+    version: '1.0'
+    license-path: LICENSE
+    url: https://github.com/Ameba-AIoT/nuwa_lib/raw/f60fc97640d8960d3313e5183aecf28442273c08/amebadplus/bin/floader_amebadplus.bin
+    description: "Binary images for the Ameba series bootloader"
+    doc-url: https://github.com/Ameba-AIoT/nuwa_lib
+
+  - path: ameba/amebadplus/bin/km0_image2_all.bin
+    sha256: a0d7969a855265d5a05a3fd47d999bdd32867400ca40ea7786ea6684a81a724a
+    type: img
+    version: '1.0'
+    license-path: LICENSE
+    url: https://github.com/Ameba-AIoT/nuwa_lib/raw/f60fc97640d8960d3313e5183aecf28442273c08/amebadplus/bin/km0_image2_all.bin
+    description: "Binary libraries supporting the Ameba series subsystems"
+    doc-url: https://github.com/Ameba-AIoT/nuwa_lib
+
+  - path: ameba/amebadplus/bin/km0_image2_all_coex.bin
+    sha256: b776f94b4bffb522e9ffb6e2c14346a74fe8cadf20455b15505a651d02c1b4c4
+    type: img
+    version: '1.0'
+    license-path: LICENSE
+    url: https://github.com/Ameba-AIoT/nuwa_lib/raw/f60fc97640d8960d3313e5183aecf28442273c08/amebadplus/bin/km0_image2_all_coex.bin
+    description: "Binary libraries supporting the Ameba series Wi-Fi subsystems"
+    doc-url: https://github.com/Ameba-AIoT/nuwa_lib
+
+  - path: ameba/amebadplus/bin/km4_boot_all.bin
     sha256: 254e92da9fb071f272ac0ca05bafac9c85657c39899cf75b84386e4cdb7b055d
     type: img
     version: '1.0'
     license-path: LICENSE
-    url: https://github.com/Ameba-AIoT/nuwa_lib/raw/d9a23ec60d44628a27b354d89597ac58093d4a20/amebadplus/bin/km4_boot_all.bin
-    description: "Binary libraries supporting the Ameba series RF subsystems"
+    url: https://github.com/Ameba-AIoT/nuwa_lib/raw/f60fc97640d8960d3313e5183aecf28442273c08/amebadplus/bin/km4_boot_all.bin
+    description: "Binary images for the Ameba series bootloader"
     doc-url: https://github.com/Ameba-AIoT/nuwa_lib
-  - path: amebad/bin/bootloader_all.bin
-    sha256: 74d86e9c144fe5018835de4dfb308c1350057d614fda016576099ea379a60d6e
+
+  # ===== amebadplus libs =====
+
+  - path: ameba/amebadplus/lib/lib_bootloader.a
+    sha256: 25c038543aa96c871de3f1c0019119ad2e17758fdc1969c8ead1b124f80b7e5b
+    type: lib
+    version: '1.0'
+    license-path: LICENSE
+    url: https://github.com/Ameba-AIoT/nuwa_lib/raw/f60fc97640d8960d3313e5183aecf28442273c08/amebadplus/lib/lib_bootloader.a
+    description: "Binary images for the Ameba series bootloader"
+    doc-url: https://github.com/Ameba-AIoT/nuwa_lib
+
+  - path: ameba/amebadplus/lib/lib_chipinfo.a
+    sha256: 6cbab69602feb99388624a4be0366e4b361726ea406db269c2e3dddf0829d7cf
+    type: lib
+    version: '1.0'
+    license-path: LICENSE
+    url: https://github.com/Ameba-AIoT/nuwa_lib/raw/f60fc97640d8960d3313e5183aecf28442273c08/amebadplus/lib/lib_chipinfo.a
+    description: "Binary libraries supporting the Ameba series chip information"
+    doc-url: https://github.com/Ameba-AIoT/nuwa_lib
+
+  - path: ameba/amebadplus/lib/lib_coex_api.a
+    sha256: dae333a4533b4840a18ea23aeba6dec87333d2c99a00782854c20756d42a21ce
+    type: lib
+    version: '1.0'
+    license-path: LICENSE
+    url: https://github.com/Ameba-AIoT/nuwa_lib/raw/f60fc97640d8960d3313e5183aecf28442273c08/amebadplus/lib/lib_coex_api.a
+    description: "Binary libraries supporting the Ameba series Wi-Fi subsystems"
+    doc-url: https://github.com/Ameba-AIoT/nuwa_lib
+
+  - path: ameba/amebadplus/lib/lib_rtw_event.a
+    sha256: b19c5c1f114551c18e331ff0786fc3d46b5340426a23cb0bbcd866076cae4881
+    type: lib
+    version: '1.0'
+    license-path: LICENSE
+    url: https://github.com/Ameba-AIoT/nuwa_lib/raw/f60fc97640d8960d3313e5183aecf28442273c08/amebadplus/lib/lib_rtw_event.a
+    description: "Binary libraries supporting the Ameba series Wi-Fi subsystems"
+    doc-url: https://github.com/Ameba-AIoT/nuwa_lib
+
+  - path: ameba/amebadplus/lib/lib_usbd.a
+    sha256: 39466937375ab9e514e5363bf710c10e5ae68a788e87ed004d772ff660a3abff
+    type: lib
+    version: '1.0'
+    license-path: LICENSE
+    url: https://github.com/Ameba-AIoT/nuwa_lib/raw/f60fc97640d8960d3313e5183aecf28442273c08/amebadplus/lib/lib_usbd.a
+    description: "Binary libraries supporting the Ameba series USB subsystems"
+    doc-url: https://github.com/Ameba-AIoT/nuwa_lib
+
+  - path: ameba/amebadplus/lib/lib_wifi_api.a
+    sha256: 1742dee99549ec8eea592dc9a4fa7fd8126ac1bc9449bf06fcd1dd5b31672ae2
+    type: lib
+    version: '1.0'
+    license-path: LICENSE
+    url: https://github.com/Ameba-AIoT/nuwa_lib/raw/f60fc97640d8960d3313e5183aecf28442273c08/amebadplus/lib/lib_wifi_api.a
+    description: "Binary libraries supporting the Ameba series Wi-Fi subsystems"
+    doc-url: https://github.com/Ameba-AIoT/nuwa_lib
+
+  - path: ameba/amebadplus/lib/lib_wifi_com_sec.a
+    sha256: b4ab276ffde90b41937635689f8f446084dc7f9649e196d9d878802dcd63f931
+    type: lib
+    version: '1.0'
+    license-path: LICENSE
+    url: https://github.com/Ameba-AIoT/nuwa_lib/raw/f60fc97640d8960d3313e5183aecf28442273c08/amebadplus/lib/lib_wifi_com_sec.a
+    description: "Binary libraries supporting the Ameba series Wi-Fi subsystems"
+    doc-url: https://github.com/Ameba-AIoT/nuwa_lib
+
+  - path: ameba/amebadplus/lib/lib_wifi_rtk_app.a
+    sha256: 2a8fbb1690f5b060ee082dbaf3973e4afc23b132856937aa23fdae2eb68f866b
+    type: lib
+    version: '1.0'
+    license-path: LICENSE
+    url: https://github.com/Ameba-AIoT/nuwa_lib/raw/f60fc97640d8960d3313e5183aecf28442273c08/amebadplus/lib/lib_wifi_rtk_app.a
+    description: "Binary libraries supporting the Ameba series Wi-Fi subsystems"
+    doc-url: https://github.com/Ameba-AIoT/nuwa_lib
+
+  - path: ameba/amebadplus/lib/lib_wifi_whc_ap.a
+    sha256: 81640f33d5606465391b7a07ae6695cab049e559f70b4a6e61dfd54716791317
+    type: lib
+    version: '1.0'
+    license-path: LICENSE
+    url: https://github.com/Ameba-AIoT/nuwa_lib/raw/f60fc97640d8960d3313e5183aecf28442273c08/amebadplus/lib/lib_wifi_whc_ap.a
+    description: "Binary libraries supporting the Ameba series Wi-Fi subsystems"
+    doc-url: https://github.com/Ameba-AIoT/nuwa_lib
+
+  - path: ameba/amebadplus/lib/lib_wpa_lite.a
+    sha256: dd8c3de332edd297152a8102e8baddc31a47cb0710126342d063c07e7ce53d4f
+    type: lib
+    version: '1.0'
+    license-path: LICENSE
+    url: https://github.com/Ameba-AIoT/nuwa_lib/raw/f60fc97640d8960d3313e5183aecf28442273c08/amebadplus/lib/lib_wpa_lite.a
+    description: "Binary libraries supporting the Ameba series Wi-Fi subsystems"
+    doc-url: https://github.com/Ameba-AIoT/nuwa_lib
+
+  # ===== amebag2 bins =====
+
+  - path: ameba/amebag2/bin/amebagreen2_boot.bin
+    sha256: 02ea21bbddb6854fd464c2c36746b9475699117f59c0f529c5782915617f0aea
     type: img
     version: '1.0'
     license-path: LICENSE
-    url: https://github.com/Ameba-AIoT/nuwa_lib/raw/d9a23ec60d44628a27b354d89597ac58093d4a20/amebad/bin/bootloader_all.bin
-    description: "Binary libraries supporting the Ameba series RF subsystems"
+    url: https://github.com/Ameba-AIoT/nuwa_lib/raw/f60fc97640d8960d3313e5183aecf28442273c08/amebag2/bin/amebagreen2_boot.bin
+    description: "Binary images for the Ameba series bootloader"
     doc-url: https://github.com/Ameba-AIoT/nuwa_lib
-  - path: amebad/bin/km0_image2_all.bin
-    sha256: 8ee218d37bda05fff30d89a72ce5b342d6ae92501985c829214be030b3039a3b
+
+  - path: ameba/amebag2/bin/floader_amebagreen2.bin
+    sha256: dfbd6bb24237308527bcc0478cf3ec9d3ff3c6d1aa0d6b1017ffcce24af5b6c5
     type: img
     version: '1.0'
     license-path: LICENSE
-    url: https://github.com/Ameba-AIoT/nuwa_lib/raw/d9a23ec60d44628a27b354d89597ac58093d4a20/amebad/bin/km0_image2_all.bin
-    description: "Binary libraries supporting the Ameba series RF subsystems"
+    url: https://github.com/Ameba-AIoT/nuwa_lib/raw/f60fc97640d8960d3313e5183aecf28442273c08/amebag2/bin/floader_amebagreen2.bin
+    description: "Binary images for the Ameba series bootloader"
     doc-url: https://github.com/Ameba-AIoT/nuwa_lib
-  - path: amebaG2/bin/km4ns_image2_all.bin
+
+  - path: ameba/amebag2/bin/km4ns_image2_all.bin
     sha256: 50509337fabc31396b9333b5a514e039b4aabc3e6c45065dc59b0955854036c6
     type: img
     version: '1.0'
     license-path: LICENSE
-    url: https://github.com/Ameba-AIoT/nuwa_lib/raw/9b2364666b0529b9d07aecf6745bb40ba9b153c9/amebaG2/bin/km4ns_image2_all.bin
-    description: "Binary libraries supporting the Ameba series RF subsystems"
+    url: https://github.com/Ameba-AIoT/nuwa_lib/raw/f60fc97640d8960d3313e5183aecf28442273c08/amebag2/bin/km4ns_image2_all.bin
+    description: "Binary libraries supporting the Ameba series subsystems"
     doc-url: https://github.com/Ameba-AIoT/nuwa_lib
-  - path: amebaG2/bin/amebagreen2_boot.bin
-    sha256: 02ea21bbddb6854fd464c2c36746b9475699117f59c0f529c5782915617f0aea
+
+  - path: ameba/amebag2/bin/km4ns_image2_all_coex.bin
+    sha256: 4521d284d1d0865e40ef13a4a602b1e8df0929505d8096523c027519b65d7f89
     type: img
     version: '1.0'
     license-path: LICENSE
-    url: https://github.com/Ameba-AIoT/nuwa_lib/raw/9b2364666b0529b9d07aecf6745bb40ba9b153c9/amebaG2/bin/amebagreen2_boot.bin
-    description: "Binary libraries supporting the Ameba series RF subsystems"
+    url: https://github.com/Ameba-AIoT/nuwa_lib/raw/f60fc97640d8960d3313e5183aecf28442273c08/amebag2/bin/km4ns_image2_all_coex.bin
+    description: "Binary libraries supporting the Ameba series Wi-Fi subsystems"
+    doc-url: https://github.com/Ameba-AIoT/nuwa_lib
+
+  # ===== amebag2 libs =====
+
+  - path: ameba/amebag2/lib/lib_bootloader.a
+    sha256: 4c8ce8936a544fd13615edbebf8898653eabcf9dbc808da685f8c5260bafb4ca
+    type: lib
+    version: '1.0'
+    license-path: LICENSE
+    url: https://github.com/Ameba-AIoT/nuwa_lib/raw/f60fc97640d8960d3313e5183aecf28442273c08/amebag2/lib/lib_bootloader.a
+    description: "Binary images for the Ameba series bootloader"
+    doc-url: https://github.com/Ameba-AIoT/nuwa_lib
+
+  - path: ameba/amebag2/lib/lib_chipinfo.a
+    sha256: f31c84ffe0359f3c4b7b333a8f6747481b03c97df681c3b90e1bfed321aed877
+    type: lib
+    version: '1.0'
+    license-path: LICENSE
+    url: https://github.com/Ameba-AIoT/nuwa_lib/raw/f60fc97640d8960d3313e5183aecf28442273c08/amebag2/lib/lib_chipinfo.a
+    description: "Binary libraries supporting the Ameba series chip information"
+    doc-url: https://github.com/Ameba-AIoT/nuwa_lib
+
+  - path: ameba/amebag2/lib/lib_coex_api.a
+    sha256: c25754677da253b352b9beb9446219e26d430dcf69db363739901ee5861cce44
+    type: lib
+    version: '1.0'
+    license-path: LICENSE
+    url: https://github.com/Ameba-AIoT/nuwa_lib/raw/f60fc97640d8960d3313e5183aecf28442273c08/amebag2/lib/lib_coex_api.a
+    description: "Binary libraries supporting the Ameba series Wi-Fi subsystems"
+    doc-url: https://github.com/Ameba-AIoT/nuwa_lib
+
+  - path: ameba/amebag2/lib/lib_pmc.a
+    sha256: 5ad67483bb20fa8e13ac43d067f5c8ba0353e6fe6de77c9c81a6c48cdea49616
+    type: lib
+    version: '1.0'
+    license-path: LICENSE
+    url: https://github.com/Ameba-AIoT/nuwa_lib/raw/f60fc97640d8960d3313e5183aecf28442273c08/amebag2/lib/lib_pmc.a
+    description: "Binary libraries supporting the Ameba series power management"
+    doc-url: https://github.com/Ameba-AIoT/nuwa_lib
+
+  - path: ameba/amebag2/lib/lib_rtw_event.a
+    sha256: f67e00ab3553a8f5fa63853cd724252a7928d0ab8867f617f51603c816ddaf44
+    type: lib
+    version: '1.0'
+    license-path: LICENSE
+    url: https://github.com/Ameba-AIoT/nuwa_lib/raw/f60fc97640d8960d3313e5183aecf28442273c08/amebag2/lib/lib_rtw_event.a
+    description: "Binary libraries supporting the Ameba series Wi-Fi subsystems"
+    doc-url: https://github.com/Ameba-AIoT/nuwa_lib
+
+  - path: ameba/amebag2/lib/lib_usbd.a
+    sha256: 05555f879fc92eb0685eb46a33bc6a59e7fe4c46c8eeb8cd49864b4a27934e47
+    type: lib
+    version: '1.0'
+    license-path: LICENSE
+    url: https://github.com/Ameba-AIoT/nuwa_lib/raw/f60fc97640d8960d3313e5183aecf28442273c08/amebag2/lib/lib_usbd.a
+    description: "Binary libraries supporting the Ameba series USB subsystems"
+    doc-url: https://github.com/Ameba-AIoT/nuwa_lib
+
+  - path: ameba/amebag2/lib/lib_usbh.a
+    sha256: 5a5554c129d5d4655880c0119ee5167fca7a8cd6b4b7a097c7a197d821614bd7
+    type: lib
+    version: '1.0'
+    license-path: LICENSE
+    url: https://github.com/Ameba-AIoT/nuwa_lib/raw/f60fc97640d8960d3313e5183aecf28442273c08/amebag2/lib/lib_usbh.a
+    description: "Binary libraries supporting the Ameba series USB subsystems"
     doc-url: https://github.com/Ameba-AIoT/nuwa_lib
+
+  - path: ameba/amebag2/lib/lib_wifi_api.a
+    sha256: 433f0b82e121c5f1e87e65d7660f69634ddc181323a951c57f1ca0e34be5b8b6
+    type: lib
+    version: '1.0'
+    license-path: LICENSE
+    url: https://github.com/Ameba-AIoT/nuwa_lib/raw/f60fc97640d8960d3313e5183aecf28442273c08/amebag2/lib/lib_wifi_api.a
+    description: "Binary libraries supporting the Ameba series Wi-Fi subsystems"
+    doc-url: https://github.com/Ameba-AIoT/nuwa_lib
+
+  - path: ameba/amebag2/lib/lib_wifi_common.a
+    sha256: c5d4f71a87576c78ee495f4338335251b68c05062c41fd58b8176fbcb1e8e6b8
+    type: lib
+    version: '1.0'
+    license-path: LICENSE
+    url: https://github.com/Ameba-AIoT/nuwa_lib/raw/f60fc97640d8960d3313e5183aecf28442273c08/amebag2/lib/lib_wifi_common.a
+    description: "Binary libraries supporting the Ameba series Wi-Fi subsystems"
+    doc-url: https://github.com/Ameba-AIoT/nuwa_lib
+
+  - path: ameba/amebag2/lib/lib_wifi_rtk_app.a
+    sha256: 5069ebcab86bbc848fd71902960cd8fd6b40337151503eec6fa0351a0779526f
+    type: lib
+    version: '1.0'
+    license-path: LICENSE
+    url: https://github.com/Ameba-AIoT/nuwa_lib/raw/f60fc97640d8960d3313e5183aecf28442273c08/amebag2/lib/lib_wifi_rtk_app.a
+    description: "Binary libraries supporting the Ameba series Wi-Fi subsystems"
+    doc-url: https://github.com/Ameba-AIoT/nuwa_lib
+
+  - path: ameba/amebag2/lib/lib_wifi_whc_ap.a
+    sha256: e04d858f439d3279b93390da8e6ddacc1c5dce878de7b7ac8f1336680b4239d4
+    type: lib
+    version: '1.0'
+    license-path: LICENSE
+    url: https://github.com/Ameba-AIoT/nuwa_lib/raw/f60fc97640d8960d3313e5183aecf28442273c08/amebag2/lib/lib_wifi_whc_ap.a
+    description: "Binary libraries supporting the Ameba series Wi-Fi subsystems"
+    doc-url: https://github.com/Ameba-AIoT/nuwa_lib
+
+  - path: ameba/amebag2/lib/lib_wpa_lite.a
+    sha256: e8e3b0fb2d411281975822bd2d44db8781f49cd57d6bdc8f36133923c3752780
+    type: lib
+    version: '1.0'
+    license-path: LICENSE
+    url: https://github.com/Ameba-AIoT/nuwa_lib/raw/f60fc97640d8960d3313e5183aecf28442273c08/amebag2/lib/lib_wpa_lite.a
+    description: "Binary libraries supporting the Ameba series Wi-Fi subsystems"
+    doc-url: https://github.com/Ameba-AIoT/nuwa_lib
+
+  # ===== bee bins =====
+  - path: bee/rtl87x2g/bin/configFile_2025.09.02.14-e600f2d80e7f4ab3e6f089b6174ff6d7.bin
+    sha256: 58dc2e17cc616e692f30018eed33715887f36ed5d814dac6addc5c785b687204
+    type: img
+    version: '0.0'
+    license-path: LICENSE
+    url: https://github.com/rtkconnectivity/realtek-zephyr-project/raw/refs/tags/v3.7-rtk-00.01.01/bin/rtl87x2g/configFile_2025.09.02.14-e600f2d80e7f4ab3e6f089b6174ff6d7.bin
+    description: "Config file"
+    doc-url: https://docs.realmcu.com/sdk/rtl87x2g/common/en/latest/doc/platform/image_layout/text_en/README.html#flash-layout
+  - path: bee/rtl87x2g/bin/OTAHeader_Bank0_1.0.0.1-3e442e5fa761e6422f0b936bc5fb0c25.bin
+    sha256: db04cbe1ee8f13a4525881d27209f1e917d05b12813e17d176415a8788c57630
+    type: img
+    version: '0.0'
+    license-path: LICENSE
+    url: https://github.com/rtkconnectivity/realtek-zephyr-project/raw/refs/tags/v3.7-rtk-00.01.01/bin/rtl87x2g/OTAHeader_Bank0_1.0.0.1-3e442e5fa761e6422f0b936bc5fb0c25.bin
+    description: "OTA header"
+    doc-url: https://docs.realmcu.com/sdk/rtl87x2g/common/en/latest/doc/platform/image_layout/text_en/README.html#flash-layout
+  - path: bee/rtl87x2g/bin/BANK0_boot_patch_MP_release_1.0.183.27_e91dd4ad-dffb4c6d9a02fea1a24302c6e1a76fda.bin
+    sha256: 514440728abbc14fe52d547bf7ffdc04dc7c4c32be5df1543d35e8bf86fe37d8
+    type: img
+    version: '183.27'
+    license-path: LICENSE
+    url: https://github.com/rtkconnectivity/realtek-zephyr-project/raw/refs/tags/v3.7-rtk-00.01.01/bin/rtl87x2g/BANK0_boot_patch_MP_release_1.0.183.27_e91dd4ad-dffb4c6d9a02fea1a24302c6e1a76fda.bin
+    description: "Boot patch bank0"
+    doc-url: https://docs.realmcu.com/sdk/rtl87x2g/common/en/latest/doc/platform/image_layout/text_en/README.html#flash-layout
+  - path: bee/rtl87x2g/bin/BANK1_boot_patch_MP_release_1.0.183.27_e91dd4ad-8a0390ad5ea191e414f1c00c6b4e366c.bin
+    sha256: a4c10821ceff84c680b502d00697ed71d69c905a7e4558440f84976dbf04e794
+    type: img
+    version: '183.27'
+    license-path: LICENSE
+    url: https://github.com/rtkconnectivity/realtek-zephyr-project/raw/refs/tags/v3.7-rtk-00.01.01/bin/rtl87x2g/BANK1_boot_patch_MP_release_1.0.183.27_e91dd4ad-8a0390ad5ea191e414f1c00c6b4e366c.bin
+    description: "Boot patch bank1"
+    doc-url: https://docs.realmcu.com/sdk/rtl87x2g/common/en/latest/doc/platform/image_layout/text_en/README.html#flash-layout
+  - path: bee/rtl87x2g/bin/BANK0_sys_patch_MP_release_1.0.183.27_e91dd4ad-59b00aef9fefc715b8fb60de65a1ffe2.bin
+    sha256: 1144ecca0010e92c203a350ad13cd23dac81c0f6900e1a9cfaac272ebe0a7fe5
+    type: img
+    version: '183.27'
+    license-path: LICENSE
+    url: https://github.com/rtkconnectivity/realtek-zephyr-project/raw/refs/tags/v3.7-rtk-00.01.01/bin/rtl87x2g/BANK0_sys_patch_MP_release_1.0.183.27_e91dd4ad-59b00aef9fefc715b8fb60de65a1ffe2.bin
+    description: "Sys patch"
+    doc-url: https://docs.realmcu.com/sdk/rtl87x2g/common/en/latest/doc/platform/image_layout/text_en/README.html#flash-layout
+  - path: bee/rtl87x2g/bin/bt_stack_patch_MP_master_0.0.126.0_a075812a-ac40d4abfa2d071f5ad63aac0daad0f2.bin
+    sha256: 81d9dbac674a80c16c5bb2997a2f34ffaf4a72e113435b48ef2621de4e782046
+    type: img
+    version: '126.0'
+    license-path: LICENSE
+    url: https://github.com/rtkconnectivity/realtek-zephyr-project/raw/refs/tags/v3.7-rtk-00.01.01/bin/rtl87x2g/bt_stack_patch_MP_master_0.0.126.0_a075812a-ac40d4abfa2d071f5ad63aac0daad0f2.bin
+    description: "BT stack patch"
+    doc-url: https://docs.realmcu.com/sdk/rtl87x2g/common/en/latest/doc/platform/image_layout/text_en/README.html#flash-layout
+  - path: bee/rtl8752h/bin/single_bank/configFile_2025.09.28.09-c56ff8be480e864851703087f3d661d3.bin
+    sha256: ff35de5c1ade92efbebc5500135b073891301410ea4131de853cd3759cc01067
+    type: img
+    version: '0.0'
+    license-path: LICENSE
+    url: https://github.com/rtkconnectivity/realtek-zephyr-project/raw/refs/tags/v3.7-rtk-00.01.01/bin/rtl8752h/single_bank/configFile_2025.09.28.09-c56ff8be480e864851703087f3d661d3.bin
+    description: "Config file(OEM header)"
+    doc-url: https://docs.realmcu.com/sdk/rtl8752h/common/en/latest/platform/image_layout/text_en/README.html
+  - path: bee/rtl8752h/bin/single_bank/OTAHeader_Bank0_1.0.0.1-b2dff20b37cc479bf054669db699e2e1.bin
+    sha256: edad96b1ccd3d99a87b37aa184881ee4b9cb8752a47ee9b2d1bcad3b9e3e36ec
+    type: img
+    version: '0.0'
+    license-path: LICENSE
+    url: https://github.com/rtkconnectivity/realtek-zephyr-project/raw/refs/tags/v3.7-rtk-00.01.01/bin/rtl8752h/single_bank/OTAHeader_Bank0_1.0.0.1-b2dff20b37cc479bf054669db699e2e1.bin
+    description: "OTA header bank0"
+    doc-url: https://docs.realmcu.com/sdk/rtl8752h/common/en/latest/platform/image_layout/text_en/README.html
+  - path: bee/rtl8752h/bin/single_bank/BANK0_fsbl_MP_master_1.2.4.0_722f404-e67afdd707414f84601a5bf52b53c788.bin
+    sha256: d690ce0adb372dbfa266ca50d52bae8c0d79f2d9d437407484b2ad3830725031
+    type: img
+    version: '1.2.4.0'
+    license-path: LICENSE
+    url: https://github.com/rtkconnectivity/realtek-zephyr-project/raw/refs/tags/v3.7-rtk-00.01.01/bin/rtl8752h/single_bank/BANK0_fsbl_MP_master_1.2.4.0_722f404-e67afdd707414f84601a5bf52b53c788.bin
+    description: "FSBL(secure boot loader) bank0"
+    doc-url: https://docs.realmcu.com/sdk/rtl8752h/common/en/latest/platform/image_layout/text_en/README.html
+  - path: bee/rtl8752h/bin/single_bank/BANK0_Patch_MP_release_0.0.322.2_56a2dbcd-2ca079e00bca6b92dd2af96124332221.bin
+    sha256: 67c46b46685026fdd6bedcaa6036cd80edd11baea828ba427a8b987ce74616fb
+    type: img
+    version: '0.0.322.2'
+    license-path: LICENSE
+    url: https://github.com/rtkconnectivity/realtek-zephyr-project/raw/refs/tags/v3.7-rtk-00.01.01/bin/rtl8752h/single_bank/BANK0_Patch_MP_release_0.0.322.2_56a2dbcd-2ca079e00bca6b92dd2af96124332221.bin
+    description: "ROM patch bank0"
+    doc-url: https://docs.realmcu.com/sdk/rtl8752h/common/en/latest/platform/image_layout/text_en/README.html
+  - path: bee/rtl8752h/bin/single_bank/bt_stack_patch_MP_master_0.0.145.0_ab89e0d5-982493ffb677098b7f324aef124f9554.bin
+    sha256: 01de230ab0a1f133db2547af7a1b99cbd963add51713ec5f682173edf1420365
+    type: img
+    version: '0.0.145.0'
+    license-path: LICENSE
+    url: https://github.com/rtkconnectivity/realtek-zephyr-project/raw/refs/tags/v3.7-rtk-00.01.01/bin/rtl8752h/single_bank/bt_stack_patch_MP_master_0.0.145.0_ab89e0d5-982493ffb677098b7f324aef124f9554.bin
+    description: "BT stack patch bank0"
+    doc-url: https://docs.realmcu.com/sdk/rtl8752h/common/en/latest/platform/image_layout/text_en/README.html